Digital PDFs

DEC-16-HMMMA-A-D

December 1973

137 pages

Original

11MB

Document:	PDP16m Maint
Order Number:	DEC-16-HMMMA-A-D
Revision:
Pages:	137
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-16-hmmma/dec-16-hmmma-a-d.pdf

OCR Text

‘

M'§§t:ard?‘fi'2?siithu§éfl2'at'°”

MAINTENANCE MANUAL

EJflEflflElll

DEC -1 6-HMMMA-A-D

PDP16-M

MAINTENANCE MANUAL

digital equipment corporation mognord, mossochusetts
-

lst Edition February 1973

The material in this manual is for informational
purposes and is

subject to change without notice.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIUl'l'AL

COM’P'TER LAB

CONTENTS

Page
CHAPTER 1

GENERAL INFORMATION

1.1

Introduction

1.2

Functional Description

1.2.1

Control

1-1

......................

Program Control Sequencer

1.2.1.2

Control PROM

1.2.1.3

Evoke Decoders

1.2.1.4

Flag (MUX and PAGE) Module
Page Evoke Module
Boolean Input Multiplexer

1-3

........

1-3

...............

1-3

..............

1-3

......

1-3

............

1.2.1.6
1.2.2

1-1

.................

1.2.1.1

1.2.1.5

1-1

......................

1-3

.........

Data Processor

1-3

..................

1.2.2.1

General Purpose Arithmetic (GPA) Register

1-4

1.2.2.2

General Purpose Arithmetic (GPA) Control

1-4

1.2.2.3

Link (L) Flip-Flop

1.2.2.4

Constant (C) Generator

..........

1.2.2.5

Transfer Register (TR)

1.2.2.6

Boolean Output/Flags (FF1

1.2.2.7

General Purpose Interface No. 1 (GPI I)

1.2.2.8

Bus Sense and Termination Module

1.2.3

Memory Options

—

FF3) Module

Constant Generator M R 16-D
Data PROM MR 16-E

1.2.3.3

Scratch Pad (SP) Register MS16-C

1.2.3.4

Data R/W MOS Memory MSIG-D

1.2.3.5

Data R/W MOS Memory MS16—E

1-4

1-5
1-5
-------------------

1-5

1-5
1-6

...................

Boolean Input Multiplexer PCS16-D

1.2.4.4

Boolean Output/Flag Module KFL16

1.2.4.5

PDP-11 Peripheral Interface DA16-F

Interfacing Details
Peripheral Interface

1-6

.....

1-6

..........

1-6
1-6
1-7

1-7

................

Interface Sockets

1.2.5.3

DC16-B Serial Interface Adapter

1.4

Physical Description
Specifications

1.4.1

Processor

1.4.2

Mechanical

1.4.3

Electrical

1.4.4

Environmental

......

..................

.....................

....................

.....................

Configuration Data

CHAPTER 2

INSTALLATION

2.1

General

2.2

Unpacking
Inspection

1-7

..............

.....................

1.5

1-7

............

1.2.5.2

..................

...................

.........................

.......................

1-5
1-5

.....

1.2.4.3

1-4

.....

General Purpose Interface DBIG-A

2.3

.....

Serial Interface DC16-A

1.3

........

1.2.4.2

1.2.5.1

............

1.2.4.1

1.2.5

1-4
1-4

...................

.................

1.2.3.2

l/O Options

nnnnnnnnnnnnnnnnnnn

...........

1.2.3.1

1.2.4

1-4

.............

...................

1-7

1-8
1-11
1-11

1-13
1-14

1-14
1-14

CONTENTS (Cont)

Page
2.4

Installation Procedure

2.5

Checkout Procedure

....................................

.....................................

2—3

.......................................

2-3

Equipment Required

2.5.2

Procedures

CHAPTER 3

OPERATION AND PROGRAMMING

3.1

Controls and Indicators

3.2

Instruction Format

...................................

3-1

......................................

3-1

....................................

3-2

...................................

.....................................

3-2

3.2.1

LET Instruction

3.2.2

GOTO Instruction

3.2.3

IF Instruction

3.2.4

CALL Instruction

3.2.5

EXIT Instruction
Basic Instruction Set

...................................

3-2

....................................

3-3

.....................................

3-3

...................................

3-3

.....................................

3-4

.....................................

3-4

3.3.1

Arithmetic Group

3.3.2
3.3.3

Logical Group
Register Group

3.3.4

Constant Generator Group

3.3.5

I/O Group

3.3.6

Command Group

3.3.7

Test Group

3.3.8

Conditional Jump Group

3.3.9

Subroutine Group

...............................

3-5

.......................................

3-5

....................................

.......................................

3-6

................................

3-6

...................................

3-7

........................

3-7

3.4

A and B Registers

3.5

Link (Overflow)

3.6

Boolean I/O

3.7

GPII (General Purpose Interface)

3.8

Constant Generator (C)

3.9

Transfer Register (TR)

3.10

Bus Sense and Terminator

3.11

MUX Selection

3.12
3.13

Page Selection
Page Linkages

CHAPTER 4

THEORY OF OPERATION

3-8
3-8

Introduction

Control Section

—

Parallel I/O

....................................

3-9

..................................

3-9

........................................

3-10

........................................

3-10

.........................................

.......................................

4-1

4-4

..............................

4-4

......................

4-4

...............................

4-4

.................................

4-4

4.2.1.3

State Generator

.........................

4-5

................................

4-7

4.2.2

Program Counter (PC) and Stack
Memory and Page Select

4.2.3

Boolean Input Multiplexers

4.2.4

Evoke Decoders

4.3.1

3-9

........................................

Program Control Sequencer
Start, Clock, and Evoke Enable Logic

Data Section

3-8
3-9

Instruction Decoder

4.3

.......................

...................................

4.2.1.2
4.2.1.4

.........................................

4.2
4.2.1.1

..............

.......................................

4.1

4.2.1

2-3

..................................

2.5.1

3.3

2-1

..............................

4-7

....................................

4-8

.........................................

4-9

General Purpose Arithmetic (GPA) Unit, LINK and OVERFLOW

...........

4 9

CONTENTS (Cont)

Page
4.3.2

Transfer Register (TR)

4.3.3

Constant Generator (C)

4.3.4

General Purpose Interface No. 1 (GPl1)

4-11

4.3.5

Bus Sense and Termination Module (BS)

4-11

4.3.6

Data Transfer Timing

4-14

CHAPTER 5

MAINTENANCE

5.1

Preparation and Maintenance
Equipment Required

5.1.1
5.1.2

4-10
................................

---------------------------------

nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn

Maintenance Modules

.................................

5.1.2.1

Bus Monitor Module M7332

5.1.2.2

Service Module M7335

5.1.2.3
5.1.3
5.1.4

Option Switch Module M7334
Maintenance Setup

5.2
5.3

Corrective Maintenance

5.3.2

Repair Procedure
Module Swapping Priorities

....................................

5.3.2.1

Data Error

5.3.2.2

Control Error

APPENDIX A

...........................

..............................

Maintenance Programs
Preventive Maintenance

5.3.1

4-11

5-13

....................................

5-13
5-14

HARDWARE OPTION DESCRIPTIONS
DA16-F Peripheral Interface Option (M623)
DB 16-A Parallel l/O Option (M7311)

DC16-A Serial l/O Option (M7313)

KFL16 Boolean Output/Flag Option (M7306)
MR16-D Constant Generator Option (M7325)
MR16-E/F Data PROM Option (M7327)
MS16-C Scratch Pad Register Option (M7318)
MS16-D Data R/W MOS Memory Option (M7319)
MS16-E Data R/W MOS Memory Option (M7324)
PCS16-B Control PROM Option (M7327)

PCS16-D Boolean Input Multiplexer Option (M7329)

APPENDIX B

MAINTENANCE HARDWARE CONSTRUCTION PROCEDURE

APPENDIX C

SIGNAL LISTING

APPENDIX D

PDP16-M MACHINE CODES

ILLUSTRATIONS
Title

Figure No.

5-10

1-1

PDP16-M Minicomputer, Block Diagram

1-2

PDP16-M Oblique View

ILLUSTRATIONS (Cont)

Page
1-3

Logic Assembly Configuration Diagram

Instruction Format

...........................

......................................

4-1

Evoke Data Transfer Scheme

ControlScheme

Start, Clock, and Evoke Enable Logic

.................................

.....

............................

4-16
4-17

State Generator State Diagram

State Generator Timing Diagram

414

LET Instruction
Program Counter and Stack
GOTO/ IF (true) Instruction
Program Counter and Stack
IF (not true) Instruction
Program Counter and Stack
Program Counter and Stack CALL Instruction
EXIT Instruction
Program Counter and Stack
Memory and Page Select Logic
Boolean Multiplexers

415

Evoke Decoder

416

GPA Registers and Control

417

Transfer Register

418

4Word Constant Generator

419

General Purpose Interface

420

Bus Sense and Termination Module

421

Data Transfer Timing Logic

Bus Monitor Module M7322, Application Diagram

Bus Monitor Module M7322

Service Module M7335, Application Diagram

Service Module M7335

Option Switch Module M7334, Application Diagram
Option Switch Module M7334
Logic Assembly Maintenance Configuration Diagram
Repair Procedure Flow Diagram
H740 Power Supply Fuses and Adjustment Controls
Serial I/O Jumper Plug

411

412
413

56
57
58
59
3-1

4-3
4-15

.....................................

Instruction Decoder

State Generator

410

4-2

.......................................

44
45

4-9

1-9
3-1

................................

4-17

...............................

4-18

.......................

4-19

.................

4-20

—

...................

4-21

......................

4-22

.......................

4-23

................................

4-24

.....................................

4-25

........................................

4-25

——

—

..................................

.......................................

4-26

.................................

427

..................................

4-28

.............................

4-29

.................................

4-30

.....................

5-3

.................................

5-3

........................

5-4

....................................

5-5

....................

5-6

................................

5-6

....................

...............................

5-12

....................

5-13

....................................

B-3

TABLES

Table No.

Title

..........................

1-9

......................................

1-14

.........................................

1-1

Module Slot Assignment and Description

1-2
2-2

Configuration Data
DC Voltages
Diagnostic Option Select Switches

State Table

2-1

Page

..............................

2-4

..........................................

4-5

Boolean Multiplexers Input

GPA Units Operations Summary

Basic PDP16-M Registers and Functions

.................................

...............................

4-8
4-9

...........................

4-14

..............................

5—1

....................................

5-7

PDP16-M Field Service Repair Kit

Option Diagnostic Key

TABLES (Cont)

Page
5-3

Preventive Maintenance Schedule (3 months or 500 hours)

5-4

DC Voltages

C-1

PDP16-M I/O Slot Pin Assignments (By Signal Name)

C-2

PDP16-M Data Bus Pin Assignments (By Signal Name)

C-3

PDP-11 Unibus Pin Assignments (By Signal Name)

.................

.........................................

vii

....................

5-11

5-13
C-1

...................

C-4

.....................

C-5

FOREWORD

All information necessary to service and maintain the PDP16-M

minicomputer is contained in this manual. The

manual contains five chapters and four appendices:

Chapter 1 provides a general functional and physical description of the PDP16—M and its options. Specifications and
configuration data are also detailed in this chapter.
Chapter 2 contains installation and checkout procedures. The basic diagnostic and all relevent option diagnostic
programs are performed after installation to verify that the PDP16—M is operating properly.
Chapter 3 covers operating and programming details. In addition to the operating information, a complete
description of the basic instruction set for the PDP16-M is included. Instructions that are implemented through
options are detailed in the appropriate option descriptions (Appendix A).
Chapter 4 contains the theory of operation of the basic PDP16-M. Theory of operation for the Options is included in
the appropriate option description (Appendix A).

Chapter 5 provides maintenance information. All optional maintenance modules and programs are described in this
chapter. Procedures for performing corrective maintenance are also included in this chapter.
Appendix A contains the option descriptions. Each option description provides a general description of the option,
installation details, programming information, and theory of operation.
Appendix B presents details on building jumper modules and plugs that will facilitate maintenance and testing.
Appendix C is an alphabetic listing of PDP16—M and PDP-i 1 bus and l/O signals.

Appendix D lists all PDP16-M instruction machine codes, execution times, and mnemonics.

CHAPTER 1

GENERAL INFORMATION

1.1

INTRODUCTION

The PDP16-M is a programmable minicomputer with built-in flexibility for memory and l/O expansion. It can be
used as a stand-alone controller or as a subprocessor in a larger system.
A prewired mainframe facilitates expansion of control memory, data memory, and l/O Options simply by inserting
the

appropriate option module in its assigned slot. Insertion slots are also reserved on the mainframe for standard

l/O interfacing cables and PDP16-M maintenance Options. The application program is stored in a control PROM
which can be reprogrammed at least 100 times. Once a PROM is loaded and installed in a PDP16-M, the machine
exhibits the characteristics of

dedicated controller. However, the PROM

can

be reloaded with

different

application program and/or a different application PROM can be installed in the PDP16-M. This feature permits the
PDP16-M

used

not

only

dedicated

controller, but

general

purpose controller,

monitor,

preprocessor.

Application programs can be written for virtually any kind of application within the range of the arithmetic, logic,
memory, and l/O capabilities of the PDP16—M. Data logging, waveform analysis, data format and media conversion,
preprocessing, and postprocessing are some applications for which a PDP16—M can be implemented.
1.2

FUNCTIONAL DESCRIPTION

The basic PDP16-M consists of a general purpose arithmetic unit (GPA), 256-location control PROM, a high speed

register, a 16-bit l/O interface, three programmable flip-flops (Boolean outputs or flags), 3 4-word data
ROM, and six external Boolean inputs (Figure 1-1). Space is reserved within the chassis for prewired
memory and l/O options which can expand the machine to 1K of control PROM, 33 registers, 256, 512, 1K, 1.25K

transfer

constant

2K of 16-bit read-write MOS memory, 28 constants, three 16-bit l/O interfaces, two serial l/O interfaces, six
programmable flip-flops, 3 256-word 8 or 16-bit data PROM, and 22 external Boolean inputs.

The control program is stored in a semiconductor PROM which may be erased and reloaded

using ultraviolet light
special PROM loader interface. Data constants used by the control program are not stored in the control
memories. They are stored in either a high speed 4-word ROM, 24-word ROM or a 256-word 8- or 16-bit
semiconductor PROM. This feature allows the data to be easily changed without having to reprogram the control
and

memories.

The program may be started by the front panel start switch or by auto start after power on.

1.2.1

Control

The programmable control section of the PDP16-M generates all control signals that cause data transfers and execute
the instructions stored in the control PROMs. It includes a control module, a control memory (expandable to 4), 4
evoke decoders (expandable to 6), and a 30-channel Boolean multiplexer (expandable to 2). The control section also
contains a 16-level automatic hardwired subroutine push down stack. The CALL and EXIT instructions control the
stack operations.

1-1

16 DATA BITS
MSYN

DATA READY
MSYN

SSYN
C1

CONTINUE

FFI

SLOT

l/O

FF<1-6>

DATA

SSYN

MUXAND

FF<I-6>

EXT

EXT<1—22

PROGRAM

M7329
BOOLEAN
MUX

SEQUENCER

733s

CONTROL

OVF-ZERO
-BS

.
.

:
:

fi%UTs

DN-DP-DZ

AODR-RO
M7332
BUS SENSE
AND TERM

ADDR

DATA

A<O-15>

M7327

M7328

nggfiPL

DEXgEER
0

Z‘l

:32
hNSTRUCNONs

M7301
GPA

LD ADDRREAD-WRnE

2
M7300
GPA
CONTROL

M7306
MUX-PAGE

M73E30KE
FF1

FF2

M7307
CONSTANT

MUX

R D LD
-

M7305
TRANSFER

RD_LD

FF3
16 st

1/0 1

PAGE

'N'OUT

FROM

EV KE
DECODER

SLOT
1s st

1e mTS

16' 0020

OFHONS

Figure 1-1 PDP16-M Minicomputer, Block Diagram

The control section of the PDP16-M consists of the following modules:

Program Control Sequencer (PCS), M7336
Control PROM, M7327

EVOKE Decoders, M7328

MUX/PAGE Flag Module, M7306

Page Evoke Module, M7310
Boolean Multiplexer, M7329

Program Control Sequencer

1.2.1.1

—

The M7336 program control sequencer controls the operation and timing of

the PDP16-M. It contains the start-stop circuitry, the clock, addressing circuitry, memory request logic, instruction
decoder state generator, and evoke enable logic.

1.2.1.2

Control PROM

—

The M7327 Control PROM stores the control program. One PROM is provided with the

basic PDP16-M, while three are optional. A special interface is required to load the control program into the PROM.

The PROM may be erased with ultraviolet light and reloaded with a different program.
1.2.1.3

Evoke Decoders

—

The M7328 Evoke Decoders are used to decode the 8-bit operation codes used in the

Each

decoder will

decode 32

instructions. There

are

six decoders for the

192

instructions. (Two decoders are optional.)

The evoke enable line from the control module allows the selected decoder to generate a control signal for the

specified data transfer operation. It will remain asserted until the data operation is completed.

Flag (MUX and PAGE) Module

1.2.1.4

—

An M7306

Flag Module houses the PAGE flip-flop and the MUX select

flip-flop.
The PAGE flip-flop is controlled by the PAGEO and PAGE1 instructions. It is used to select the upper 512 or lower
512 control memory locations.

The MUX

flip-flop is controlled by the MUXO and MUX1 instructions. It is used to enable one or the other
multiplexer for internal or external bit testing, using the IF instruction.
1.2.1.5

Page Evoke Module

1.2.1.6

Boolean

—

The M7310 Evoke Module controls the operation of the PAGE select flip-flop.

The M7329 Boolean Multiplexer serves as a 30-channel input multiplexer for
Input Multiplexer
the program control sequencer. It multiplexes external and internal Boolean inputs to be tested in response to the
5—bit operation code used in the conditional and unconditional jump instructions.

1.2.2

—

Data Processor

The data processor section has a fully implemented 16-bit arithmetic and logic instruction set, a parallel l/O channel,
a

4-word data ROM, three programmable flip-flops (Boolean outputs/flags), LlNK and six external Boolean inputs.

The backplane is prewired to accept

variety of memory and l/O options to allow the basic processor to be

expanded as required to fit many different applications.

1-3

The processor section of the PDP16-M consists of the following modules:
General Purpose Arithmetic (GPA)

General Purpose Arithmetic (GPA) Control, M7300
LINK (L) flip-flop, M7306
Constant (C) Generator, M7307

Transfer Register (TR), M7305
Boolean Output/Flag (FF1

FF3) Module, M7306

—

General Purpose Interface (GPl), M7311
Bus Sense (BS) Module, M7332

1.2.2.1 General Purpose Arithmetic (GPA) Register —The M7301 GPA Register performs arithmetic and logical
operations on data in two 16-bit registers designated A and B. The M7301 cannot be used alone; it is only half of a
GPA unit. The M7300 GPA control makes up the other half of the GPA unit and must be located in the socket

adjacent to the M7301. Control signals are routed from the M7300 to the M7301 by way of an H851 Edge
Connector which plugs into the handle end of each unit.

Purpose Arithmetic (GPA) Control —The M7300 GPA control performs the control functions
needed to operate the M7301 GPA Register.
1.2.2.2

General

1.2.2.3

Link (L) Flip-Flop

—

The Link flip-flop located in an M7306 Flag Module in slot C9 is connected to the left

and right shift inputs (LSI and RSI). (Figure 4-2). When a shift instruction is executed, the link bit is shifted into the
vacant bit location. The Link flip-flop is unchanged by the shift operation. The instructions

L=1, L=0, L=LNOT, and

L=OVF may be used to condition the Link flip-flop.
1.2.2.4

Constant (C) Generator

—

The M7307 Constant Generator provides a convenient way to store hard-wired

Up to four 16-bit constants may be encoded by clipping out jumper wires
associated with a diode read-only memory. The constants, normally all 19 and Os are created by cutting out wires.
constants for

1.2.2.5

PDP16—M program.

Transfer Register (TR)

Register is a 16-bit storage register that communicates with
inputs from the evoke decoders load data from the bus to the register, or read
data from the register to the bus. The register is divided into lower and upper bytes that can be loaded or read
separately (8 bits) or together (16 bits).
—

The M7305 Transfer

the PDP16-M data bus. Command

1.2.2.6

Boolean Output/Flags (FF1

—

FF3) Module

-—

The M7306 module contains three control flip-flops which

may be set or cleared under program control. Their outputs are available at the MUX and FF I/O slot for external

device control (Boolean output channels) or they may be used as internal 1-bit registers (flags).
1.2.2.7

General Purpose Interface No. 1

(GPI1)

—

The M7311 General Purpose Interface provides for bidirectional

(parallel l/O) between external equipment and the PDP16-M data bus. The output interface includes a
register that is loaded by an output command. The register buffers the output data until the next output
command. The input interface consists of a gating structure only. An input command samples the input by gating it

data transfers

16-bit

to the PDP16—M data bus.

1.2.2.8
for the

Bus Sense and Termination Module

asynchronous timing

—

The M7332 Bus Sense and Termination Module provides the control

circuits; these circuits make all other transfer and flow operations possible. The bus

sense

module also terminates the control and data bus. In addition, this unit provides

some

useful

supporting

functions. An overflow storage circuit, control switch inputs, a power clear bus output, and detect positive, negative,
and zero logic are included in the M7332 Bus Sense and Termination Module.

1.2.3

Memory Options

The PDP16-M is prewired to accept a variety of memory options for data/constant storage. The following memory

options can be implemented simply by inserting the option module into its preassigned slot (Paragraph 1.5):
Constant (K) Generator, M7325 (MR16-D)
Data PROM, M7327 (MR16—E)

Scratch Pad (SP) Register, M7318 (MS16-C)
Data R/W MOS Memory (256 words), M7319 (MS16-D)
Data R/W MOS Memory (1024 words), M7324 (MS16—E)

1.2.3.1

Constant Generator MR16—D—The MR16-D Constant Generator

provides

convenient way to store

hard-wired constants in a PDP16-M. Up to twenty-four 16-bit constants may be encoded by soldering a wire to the

apprOpriate split lug for the constant desired (1-24) at the top of the module. The wire must then be woven
through the core of the appropriate bit (1—16) to create a ”1.” If a “0" is desired, the wire must be woven through
the hole of the appropriate bit (1—16).
The module is shipped with a test wire already woven into place. When wiring constants 1—24, care must be taken to
pass wires through the cores in the same direction as the test wire.

1.2.3.2

Data PROM MR16-E

This option is implemented by using one or two MR16—E 256—word PROM options.

This option provides a convenient way to store 8- or 16-bit data constants such as code conversion tables, text, or
numeric data to be used by the program. One MR16—E option will provide 256 8-bit constants; two memories will
allow 256 16-bit constants.
The PROM memories

are

the same type that

are

used to store the control program.

They may be erased with

ultraviolet light and reprogrammed using a special interface.

1.2.3.3

Scratch Pad (SP) Register MS16-C —The MS16-C

High-Speed SP Register is a 16-word X 16-bit storage

register that is organized to operate like 16 independent registers for temporary storage.
Space for two of these options is reserved in the basic machine. An evoke decoder must be added to the PDP16-M
Register option that is implemented. (NOTE: The basic machine has four decoders. Space is
a
total
of six.)
for
provided

for each MS16-C

1.2.3.4

Data R/W MOS

Memory MS16-D

—

The MS16-D R/W MOS Memory is a 256-word by 16-bit read/write

memory with built-in address and memory buffers. It is interchangeable with the 1024-word R/W MOS Memory

(MS16-E) option.
1.2.3.5

Data R/W MOS

Memory MS16-E

—

The M816-E R/W MOS Memory is a 1024-word by 16—bit read/write
interchangeable with the 256—word R/W MOS Memory

memory with built-in address and memory buffers. It is

option.

1-5

I/O Options

1.2.4

The PDP16-M is prewired to accept several additional l/O options. The following I/O options can be implemented

simply by inserting the option module into its preassigned slot (Paragraph 1.5).
General Purpose Interface No.2 (GPl2), M7311 (DBIB-A)
General Purpose Interface No.3 (GPI3), M7311 (DBlG-A)
Serial Interface No. 1

(SII), M7313 (DC16-A)

Serial Interface No.2 (Sl2), M7313 (DC16-A)
Boolean Input Multiplexer 1 (MUXI ), M7329 (PCS16-D)
Boolean Output/Flag (FF4

PDP-11

1.2.4.1

——

FF6) Module, M7306 (KF L16)

Peripheral Interface, M623 (DA16-F)

General Purpose Interface DB16—A

—

Two additional 16-bit parallel I/O channels may be added to the basic

PDP16-M. Each interface contains a 16-bit flip-flop output register and a 16-bit input register. All inputs and outputs
are TTL

levels. A separate cable socket is provided for each interface at the rear of the logic assembly.

The DBI 6—A General Purpose Interface provides for bidirectional data transfers between external equipment and the
PDP16-M data bus. The output interface includes a 16-bit register that is loaded by an output command. The register
buffers the output data until the next output command. The input interface consists of a gating structure only. An

input command samples the input data by gating it to the PDP16—M data bus.
1.2.4.2

Serial Interface DC16—A

—

The DC16-A Serial Interface allows the PDPIB-M to interface with teleprinters

through the SI Adapter DC16-B option. Two serial I/O channels can be
implemented. The DC16-A option contains a transmitter, a receiver, and built-in crystal clock. Data rates available
are 110, 150, 300, 600, 1200, and 2400 baud. The number of bits/character can be 5, 6, 7, or 8 and the number of
and serial data communication

lines

stop bits can be 1 or 2.
Standard 20 mA current loops are available on a connector mounted on the side of the SI Adapter. This connector is

compatible with the standard PDP-11 teleprinter. TTL compatible input and output is available on the MUX and FF
I/O connector socket.
The TAPEI

TAPE2 instruction causes one character to be read from the paper tape reader on a teleprinter. To

continue reading, more TAPE commands must be issued.
Bit

configuration and baud rate are selected by jumpers on the SI Adapter option. Space is reserved in the basic

processor for up to two DC16-A Serial Interface Options.

optional multiplexer may be used to expand the number of
external inputs from 6 to a total of 22. Bit 0 and 15 of the B Register, the link, and remaining A Register bits may
1.2.4.3

Boolean

Input Multiplexer PCS16-D

—

The

also be tested when this option is implemented.
The power OK level from the power

supply is also available for testing by the programmer if ac power fail

procedures are necessary.
1.2.4.4

Boolean

Output/Flag Module KFL16

Three additional programmabie flip-flops may be implemented in

the basic PDP16—M with the KF L16 option. Each flip-flop may be tested by MUXO and their outputs are available at
the MUX and FF I/O socket at the rear of the logic assembly.

1-6

The PDP-11 peripheral interface option provides the necessary logic
Peripheral Interface DA16-F
for interfacing the PDP16-M with a PDP-ll low-speed peripheral device. Three slots on the PDP16-M logic assembly
provide the control, address, and data signals required by the peripheral device. Since the PDP-ll l/O connections
are distributed between only two slots (double height), a special interface is required. Refer to DA16-F option
description for details.

PDP-11

1.2.4.5

——

Interfacing Details

1.2.5
1.2.5.1

Peripheral Interface

—-

The basic processor is wired to allow PDP-ll

peripherals that do not need to become

the master device to be interfaced to the PDP16-M control and data bus. Two instructions, DATI and DATO, allow
the PDP16-M to use the peripheral as a slave device. Interfacing requires three cable connections on the PDP16-M.

GPII cable carries a 16-bit address. Bits 17 and 18 must be hard wired at the controller to +3V.

MUX and FF I/O cable carries MSYNC and SSYNC control signals and C1 signal from FF1.

The third cable connects the 16-bit PDP16-M data bus to the PDP-ll

Cable lengths

must

not

peripheral data bus.

exceed 5 feet and the data bus cable must be terminated with

KTM16

option at the

peripheral controller.
For longer distances, a module interface must be constructed to drive the long lines. A maximum of one additional

terminator may be added to the PDP16-M data bus.
All parallel and Boolean l/O are implemented with standard TTL inputs and outputs.
signals are high for assertion. Signals must be buffered with K or M series modules if distances greater than 5 feet
are to be driven or received by the interface. Each parallel I/O interface has a cable socket assigned to it at the rear
of the logic assembly. The output of one programmable flip-flop is also available at each interface socket to be used
for I/O Synchronization or control. FF1 is available with GPI1, FF2 with GPI2, and FF3 with GPI3.

1.2.5.2

Interface Sockets

—

All

The outputs of these three flip-flops as well as FF4, FF5, and FF6 are also available’at the MUX and FF I/O socket.
The MUX and FF l/O socket is located at the rear of the logic assembly and contains the following signals.
External Inputs:

EXT1 through EXT22 are available for inputting Boolean logic levels to be tested by IF instruction

in the control program.

MSYNC and SSYNC:

PDP-ll control signals MSYNC and SSYNC are available (if option DA16-F is implemented)

for the control of PDP-ll

low-speed peripherals.

CONTINUE: A low for assertion TTL pulse on this input will continue the program after the last programmed
HALT instruction. The front panel START switch will restart the program at location 000 on the current page.
Sll <SI>, Sl2 <Sl>: TTL serial inputs for serial interface 1 and 2.

Sll <SO>, SI2 <SO>: TTL serial outputs for serial interface 1 and 2.

1.2.5.3

DC16—B Serial Interface Adapter

—

This module is used to define the characteristics of serial interfaces 1

Lugs are provided for the user to specify the baud rate, stop bits, and data bits for each serial interface. Two
Mate—N-Lok plugs are provided on the module to be used to connect standard 20 mA current loop devices such as
Teletype, VT05, and LA30 directly to the PDP16-M.
and 2.

1-7

1.3

PHYSICAL DESCRIPTION

The PDP16—M

(Figure 1-2) is packaged in a small table-top or rack-mountable cabinet with a self-contained power
supply, two cooling fans, an air filter, and a simple front panel.

LOGIC
H740

ASSEMBLY

POWER SUPPLY

AIR

FILTER

COOLING FANS

Figure 1-2 PDP16-M Oblique View (top cover removed)

Each slot of the logic assembly has been wired to accept only a specific module type.
CAUTION

Damage

may result to the machine if a module is inserted into

the wrong slot.

Figure

1-3 and Table 1-1 illustrate the

prewired configuration and describe each module of the PDP16-M. Four
are designed to facilitate maintenance and
optional
Refer
to
Maintenance
5
and
PDP76—M
Users
Guide for details.
program debugging.
Chapter

additional

modules

are

available from DEC. These modules

1-8

1/0—3

SLOT

1/0-2

1/0—1

SLOT

MUX

1/0 SLOT

SLOT

AND

M1307

PCS

M7335

MUXO

M7329

18
17

CONT PROMO M7327

15
AND M1307
AND

M1307

AND

14
13

M1307

AND M1307

GP11

AND

M1307

M7311

M1307

GPA

CONT

AND M1307

GPA

REG M7301

AND M1103

L,PAGE,MUX M7306

M7305

EVOKE

DEC 5

M7300

(A013)

10
9

M7328

6
EVOKE

DEC 2

M7328

EVOKE

DEC1

M7328

EVOKE

DEC 0

M7328

SWCAB

OPTIONS

M908
D

FF1-3

M7305

EVOKE

M7310

M7307

BUS SENSE AND TERM

M7332

A
16-0027

Figure 1-3 Logic Assembly Configuration Diagram

Table 1-1
Module Slot Assignment and Description

Slot

Module No.

Model No.

Description

Configuration
Row A

Test Slot

M7332

KBSI 6-A

Basic

M7318

MS16-C

M7318

MS16-C

Option
Option

Timing Control, Data Testing, Bus Terminator
16-Bit Registers, SP17 through SP32
16-Bit Registers, SP1 through SP16

M7307

MR16-A

Basic

4-Word Constant Generator

M7319

MS16-D

MEM1

M7319

MSIG-D

M7325

MR16—D

Option
Option
Option

M7305

MS16-A

Basic

16-Bit Register with Byte Control

M7301

KAR16

Basic

ALU and Registers A and B

M7300

KAC16

Basic

ALU Control Unit

M7311

DB16-A

Basic

GPII -16-Bit l/O TTL Interface

M7311

DBIG-A

GPI2

M7311

DB16-A

M7311

DB16-A

M7313

DC16-A

M7313

DC16-A

Option
Option
Option
Option
Option

—

MEM2

—

256 X 16 R/W MOS Memory
256 X 16 R/W MOS Memory

24-Word Constant Generator

1-9

GPI3

—

16-Bit I/O TTL Interface

16-Bit l/O TTL Interface

Interface for 8 or 16 X 256 data PROM
S|1

S|2

—

Asyn Serial l/O Interface
Asyn Serial I/O Interface

Table 1-1 (Cont)
Module Slot Assignment and Description

Slot

Module No.

Model No.

Description

Configuration
Row A (Cont)

M7329

PCSlG-D

Basic

MUXO

M7329

PCS16-D

Option

MUX1

M7336

PCS16-E

Basic

Processor Control

—-

—

Input Multiplexer
input Multiplexer

NOTE
The following variation is permitted for sockets A6 and A7.

M7324

MS16-E

M7324

MS16—E

Option
Option

MEM1
MEM2

—

1K X 16 R/W MOS Memory
1K X 16 R/W MOS Memory

Row B

Test Slot

Row C

M7310

KEV16

Basic

M7306

KFL16

Basic

FF1, FF2 and FF3

M7328

PCS16-C

Basic

Evoke Decoder 000—0378

M7328

PCSl 6-C

Basic

Evoke Decoder 040—0778

M7328

PCS16-C

Basic

Evoke Decoder 100—1373

M7328

PCS16-C

M7328

PCSlB-C

Option
Option

SP1—SP16 Evoke Decoder 140—1778

M7328

PCS16-C

Basic

Evoke Decoder 240—1773

M7306

KFL16

Basic

Link, MUX Select, PAGE Select

M1307

KOR16—B

Basic

Control Logic

M1307

KOR16-B

Basic

Control Logic

M1307

KOR16-B

Basic

Control Logic

M1307

KO R16-B

Basic

Control Logic

Basic

Control Logic

PAGEO and PAGE1 Control

SP17—SP32 Evoke Decoder 200—2378

M1307

KOR16-B

M7327

MR16—E

Option

8 X 256 Data PROM (lower 8 bits)

M7327

PCS16-B

Basic

Control PROM Loc 0000—03773

M7327

PCS16-B

Option

Control PROM Loc 1000—13778

M1307

KOR16-A

Basic

Control Logic

”0 Socket

Basic

EXT1—EXT23, FF1—FF6, Sl1, Sl2,
MSYNC and SSYNC

VD Socket

Basic

GP12 HO and FF2

Row D

M908

Panel

Basic

Front Panel and Autostart (SWCAB)

Socket
2

M7306

KFL16

Option

FF4, FF5 and FF6

M1103

KOR16-A

Basic

Control Logic

Table 1-1 (Cont)
Module Slot Assignment and Description

Module No.

Slot

Model No.

Description

Configuration

Row D (Cont)

Control Logic

M1307

KOR16—B

Basic

M1307

KOR16-B

Basic

Control Logic

M1307

KOR16-B

Basic

Control Logic

M1307

KOR16-B

Basic

Control Logic

M623

DA16-F

M7327

MR16-E

M7327

PCS16-B

M7327

PCS16—B

M7333

DC16-B

Option
Option
Option
Option
Option

Serial I/O Interface Adapter

PDP-11 MSYNC & SSYNC Interface
8 X 256 Data PROM (upper 8 bits)

Control PROM Loc 0400—07778
Control PROM Loc 1400—17778

I/O Socket

Basic

GP|1 I/O and FF1

l/O Socket

Basic

GPl3 l/O and FF3

1.4

1.4.1

SPECIFICATIONS
Processor

Word Length

Control Program:

8 bits

Memory Address:

9 bits (10th bit is programmable)

Program Data:

16 bits

Memory

Programmed Instruction:

256-word

reprogrammable control ROM (PROM)

—

Expandable to 1024 in

256-word increments.

Program Data (Constants):

4-word

diode

ROM

Expandable by 24 words and/or 256 8-

words.

Auxiliary Data Storage:

256 to 2048 words of 16-bit Read/Write MOS memory.

Control PROM

Type:

Electrically alterable quartz window ROM.

Organization:

256 8-bit words

Minimum Prop. Delay:

300 ns

Maximum Prop. Delay:

1 usec

16-bit

Voltage Spec:

+5V i 5%

~9V t 5%

Outputs:

1 TTL unit load drive. Tri-state output or open collector drivers.

Address:

8-bit TTL address. Internally decoded. Two memory select inputs.

Programming:

The semiconductor PROM control memories are programmed by using a
special electrical interface. The Quartz Window PROM can be erased with
ultraviolet light and reprogrammed at least 100 times.

Scratch Pad Register

(byte addressable)

Accumulators

(A)

Argument Register

1 (B)

—

Expandable by 16- or 32-word addressable registers.

l/O Channels

Flags (Boolean Outputs):

Boolean Inputs:

Parallel:

1 (PDP-11 Unibus compatible)

—

Expandable to 6
Expandable to 22
—

Expandable by 2 straight data l/O channels.
NOTE

The three standard flags are available at the channel interface for

l/O synchronization.
Serial:

2 (optional)

NOTE
The serial channels will accommodate baud rates of 110, 150,

300, 600, 1200, or 2400; one or two stop bits; and 5, 6, 7, or 8
data bits.

Maximum Execution Time

Instructions

LET:

2.4 usec

GOTO:

3.2 psec

lF:

2 usec if false

Machine Code

0—2773
3008 and 3013
3028
373s
—

3.2 usec if true
CALL:

3.2 usec

EX|T:

3.2 usec

374s and 3753
3768 or 3773

NOTE
The

LET

and

EXIT

instructions require

one

8-bit memory

location each and the GOTO, IF, and CALL instructions use two
8-bit locations each; one for the operation code and the other for
the jump address. The GOTO and IF instructions

are

the same

electronics with the condition for the GOTO instruction always
true.

1-12

Bus

Pin Assignments:

(Slots A1 —A11 7)

Voltage:

Current:

1.4.2

Bit

AA1 (L83)

AK1

A81

AL1

AC1

AM1

AD1

AN1

AE1

AP1

AF1

AR1

AH1

AJ1

Logic 1
Logic 0
Logic 1
Logic 0

A81
AU1

Control

Overflow

BA1

Power Clear

BB1

Data Accept

BC1

Done

801

Data Ready

BE1

(MSB)

0 to 0.4V
3.0 to 4.0V

24 to 31 mA with one terminator

1.5 to 4.0 mA

Mechanical

Chassis

Dimensions:

19 X 13 X 10.44 inches; 48 X 33 X 26.5 cm

Fans:

Two fans exhaust from left side of cabinet. Filter is located on right side of
cabinet.

Weight:
Mounting:

55 lb (approx); 25 kg (approx)
Chassis slides for rack mounting in standard 19 in. cabinet. Without slides the

cabinet may be used as a table-top unit.
Front Panel

Run Light:

LED Indicator is on when the program is running.

Power Light:

LED Indicator is on when +5V is available from internal power supply.

Start Switch:

Initiates program exeCUtion.

Pane| Lock:

Disables the START switch.

1.4.3

Electrical

PDP16-MA:

Primary Power:

115 Vac 47—63 Hz 2A maximum

PDP16-MB: 230 Vac 47—63 Hz 1A maximum
H740 Power Supply:

1.4.4

(+5V @ 17A, -15V @ 2A)

Environmental

Temperature:

0 to 60°C ambient

Relative Humidity:

95% maximum (without condensation)

Altitudes:

10K ft; 3000m

Vibration:

1.89G rms overall from 0—70 Hz. Acceleration spectral density—0.029
G2 /Hz from 10—50 Hz with an approximate 8 dB/octave roll-off from 50 to
70 Hz.

1.5

CON FIGURATION DATA

The basic PDP16-M

expanded simply by inserting the desired option module into its preassigned slot. To
implement
options,
prerequisites to the basic machine are required. These prerequisites, the resident slot
in the logic assembly, the module number, the option number and name and the purpose of each option are detailed
can

some

in Table 1-2.

Table 1-2

Configuration Data
Option Name

Purpose

Increase storage for Control

Control

program to 512 words

PROM 1

Increase storage for Control

Control

program to 768 words

PROM 2 or 3

Option

Module

Model No.

No.

PCS16—B

PCS16-B

Slot

Prerequisite

M7327

D16

None

M7327

C17

PCS16-B

in slot D16

D17

NOTE
If only 768 words are implemented, it is desirable to insert the

3rd control PROM in slot D17 (thereby defining it as the 4th
PROM

with

the

3rd

PROM

not

implemented)

avoid

complicated page linking code.

increase storage for Control

Control

program to 1024 words

PROM 3

PCS16—B

M7327

D17

PCS16-B
in slots 016

and C17

Increase storage for Program

Constant

Data (constants) from 4 to

Generator

28 words

(K)

iviR‘iB-D

‘vi7325

A88

None

Table 1-2 (Cont)

Configuration Data
Option Name

Purpose

Option

Module

Model No.

No.

Slot

Prerequisite

Increase storage for Program

Data PROM 1

MR16-E

M7327

D15

DB16-A in

Data (constants) from 4 to

and

MR16-E

M7327

C15

slot A315

260 words

Data PROM 2

NOTE
Both Data PROM 1

and 2 must be used if 16-bit data is

required. If only 8-bit data is to be stored (such as characters

messages), then only one or the other need be
implemented. Both the constant generator (K) and the Data
PROMs can be implemented to extend data storage to 288

for

words.

Increase Scratch Pad Registers

Fast Registers

from 1 to 17 or 1 to 33

(SP1 to 16)
Fast Registers

MSlG-C

M7318

AB4

PC16-C in
slot CD6

MS16-C

M7318

A33

(SP1? to 32)

PCS16-C in
slot CD7

NOTE
One Scratch Pad

Register, designated the Transfer Register
(TR), is implemented in the basic machine. If additional
Scratch Pad Registers are required either or both of the above
option can be implemented.
Add Read/Write MOS Memory

MEM 1 and 2

for Aux Data Storage

256 words

MEM 1

MS16-D

M7319

AB6

512 words

MEM 2

MS16-D

M7319

AB7

None

MS16-D in
slot A36

1024 words

MEM 1

M316-E

M7324

ABG

1280 words

MEM 2

MS16-D

M7319

AB7

None
MS16-E in
slot A36

MEM 2

2048 words

MS16-E

M7324

AB7

MS16-E in
slot A86

NOTE
MEM 2 can be implemented without MEM 1. The listing above
serves

only to illustrate what is required to expand the RM

memory from the minimum through all available sizes to the

maximum.

Table 1-2 (Cont)

Configuration Data
Option Name

Option

Module

Model No.

No.

MUX 1

PCS16’D

Expand flags from 3 to 6

Flags FF4—6

Add 2nd Parallel l/O

Add 3rd Parallel l/O

Purpose

Expand Boolean Inputs (EXT)

Slot

Prerequisite

M7329

AB19

None

KFL16

M7306

None

GP|2

DB16-A

M7311

AB13

None

GPl3

DB16-A

M7311

AB14

from 6 to 22; or test even

bits of A Register, test

LSB and M38 of B Register,
test LINK or test PWOK using

IF instruction

DB16-A in
slot A313

Add one serial HO

8”

DC16-A

M7313

AB16

Add 2nd serial l/O

Sl2

DC16-A

M7313

AB16

DC16-B
DC16-A in
slot AB16

DATA PROM option Interface
Decode EVOKES for SP1-16

GPI

DB16-A

M7311

A815

None

EVOKE

PCS16-C

M7328

CD6

None

PCS16-C

M7328

CD7

None

Decoder
Decode EVOKES for SP17—32

EVOKE
Decoder

Maintenance Configuration

See Maintenance

Chapter 5

CHAPTER 2

INSTALLATION

2.1

GENERAL

Installation of a PDP16-M requires no special tools or equipment. Normal hand tools are all that is necessary.
2.2

UNPACKING

Unpack the equipment, using the following procedure.

2.3

Remove the shipping straps.

Open the outer carton.

Lift out the inner carton.

Open the inner carton.

Slide the computer out, using care not to damage the switch.

Check that all equipment is included, as specified on the inventory checklist.

Install the chassis slides using the hardware, if necessary.

INSPECTION

After removing the equipment packing material, inspect the equipment.

InSpect the external surfaces of the chassis for surface, bezel, switch, and light damage, etc.
Internally inspect the cabinet for console and processor damage; loose or broken modules; fan damage,
loose nuts, bolts, screws, etc.

2.4

Inventory all hardware against key sheet.

Inventory all prints against drawing directory.

INSTALLATION PROCEDURE

Install the equipment, using the following procedure.
1.

Turn off power switch. Do not plug in the PDP16-M until step 4 of this procedure.
WARNING
Do not touch the computer after plugging in power until the

computer is checked for proper ground.

2-1

Ensure that all ac power is received from the same source, if the PDP16-M is a part of a system.
Disconnect the dc harness at the rear of the logic assembly.
WARNING
Ensure that

lugs

end

of do harness

are

not

touching

anything.

Plug in power.
Before touching the computer, check frame to ground voltage.

Unplug power.
Turn on computer power key switch and push the circuit breaker on the rear panel.

Repeat steps 4 and 5.
Check that the dc voltages at the dc harness are in accordance with those specified in Table 2-1.

Table 2-1
DC Voltages

Wire (Color)

Voltage (dc)

Red

+4.8 to 5.2 Vdc

Blue

-14.5 to -15.5 Vdc

Gray

+2.8 to 5.5 Vdc

Blk

Ground

Orn

+1.0 to 2.0 Vdc

10.

Turn off power

11.

Connect the dc harness at the rear of the logic assembly.

12.

If the AUTO RUN option is desired, install a jumper between pins D0181 and DO1U1 on module M908.
This jumper should not be installed to start the machine using the START switch.

13.

Check that modules are in their assigned slot in accordance with Table 1-1.
WARNING
Sockets have been preassigned for all options. Modules may be

damaged if inserted into the wrong socket. (Figures 1-3 and
5-7).

2.5

2.5.1

CHECKOUT PROCEDURE

Equipment Required
1 set PDP16-M Diagnostic PROMs

Basic Test PROMS

PROM 2:

M7327 YC

PROM 3:

M7327 YD

Option Test ROMS
PROM O: M7327 YA
PROM 1:

—

2
2

—

——

M7327 YB

KBM16 Bus Monitor (M7322)
KSM16 Service Module (M7335)

KSL16 Option Switch Module (M7334)
Extender Cables (7007222)

Extender Module (Double Height) W984
NOTE

jumpers for the following modules and plugs must be
installed by the user. Refer to Appendix B for details.

The

2
1
1

2.5.2

—

Mate-N-Lok jumper plugs
Interface Jumper Module 1 (W971)

Interface Jumper Module 2 (W971)

Procedures
1.

Install Diagnostic PROMs 0, 1, 2 and 3 in sockets C16, D16, C17, and D17, respectively.

Plug in KBM16 Bus Monitor M7322 in socket A01 and KSM16 Service Module M7335 in socket BO1.
Both modules should be on 7007222 extender cables. Insert Mate-N-Lok serial l/O jumper plugs in
module M7333 located in slot D18.

Install W971 Interface Jumper Module 1 in socket CD19 and W971 Interface Jumper Module 2 in CD20.

Set SI and BP switches on service module to OFF position.
4.

Turn on power. Check the power light for ON condition.

If autostart jumper is installed, proceed to step 9.

Check RUN light for OFF condition, and DATA READY and DATA ACCEPT lights on Bus Monitor for
ON condition.

Turn panel switch to panel lock position, push START switch, and check RUN light for OFF condition.

Turn panel switch to ON position and push START switch.

Check RUN

light for ON condition. The basic diagnostic should be running. If the program halts, refer

to Chapter 5 for service information.

2-3

10.

Perform

the

acceptance

test

for the basic

PDP16-M

encountered, the program will halt with the RUN

for 30 minutes. If abnormal conditions

light

off.

Refer to

Chapter

are

5 for maintenance

information if required.
11.

Turn off power and replace the M7311 module in location AB12 with the KSL16 option switch module
M7334 on the extender module.

12.

Refer to Table 2-2 and set the switch on the M7334 module to select the option to be tested. Only one
switch may be selected at a time.

13.

Turn on power and push START. Run the diagnostic for the time period indicated in Table 2-2.

14.

Turn off power.

15.

Repeat steps 12 and 13, selecting a different option switch until all implemented options have been
tested.

NOTE
If no switch is selected, the basic diagnostic will be executed.

This will result in a false error indication because the M7311 in

socket A12 has been

replaced by the M7334 option switch

module.

Table 2-2

Diagnostic Option Select Switches
Switch

Option

DB16-A

Slot No.

AB 13

Module

Run

Symptoms of

.Option

Tested

Mode

Correct Operations

Acpt Time

M7311

Single
Step &

Using single step, watch

1 min.

the bus monitor up

Auto

count the data bus to
a

count of (108 ). Put

into Auto Run and

watch up count. Runs
until error or power

down.

DBlS-A

A814

M7311

Single
Step &

Same as switch 0. Up

1 min.

count starts at 28.

Auto

2 & 15

DB 16-A

A15

M7311

RUN light OFF. Proper

Check all

C/D 15

M7327

data displayed in the

256 loca-

M7327

light register

tions.

Auto

the

M7334 module. Press
START switch to dis-

play next location.
257th push displays
checksum. Push again
for high speed checksum. Check for

2-4

equal.

Table 2-2 (Cont)

Diagnostic Option Select Switches
Switch

Option

MR16-D

Slot No.

A88

Module

Run

Symptoms of

Tested

Mode

Correct Operations

Option
Acpt Time

Single

Each constant will be

Check each

Step

displayed in the M7322

const.

M7325

Bus Monitor. Refer to

(NOTE):

diagnostic listing for

ALL con-

program operation.

stants must

Checksum displayed in

be wired.

M7334 at end of test.
MS16-D

M7319

Auto

RUN light ON. Bus
monitor lights
on

MS16-E

M7324

Auto

M7318

Auto

RUN light ON. Same

5 min.

RUN light ON. Shows
an

5 min.

all

and flickering.

as switch

MS 1 6-C

5 min.

up count in the bus

monitor.

MS16-C

M7318

Auto

DC 1 BA

A16

M7313

Auto

Same as switch 6.

5 min.

RUN light OFF and

10 times

4008 is displayed in
the light switch register (M7334)

after the

program ha’its in loc 0313.

Test shows an up count
to 4008 in the bus monitor M7322.

DC 1 6-A

A17

M7313

Auto

KFL16

M7306

Auto

Same as switch 8.

10 times

RUN

1 min.

light ON and

bits 4 and 5 are on the

bus monitor. 177777

displayed in the lights
on

M7334.

Not used.

DATI &

DATO

D14

M623

RUN light is ON and all

Single
Step &

data lights in the bus

Auto

monitor are ON. Single

step until the data bus
seems to complement.

13——14

Not used.

Used with switch 2.

2-5

1 min.

CHAPTER 3
OPERATION AND PROGRAMMING

3.1

CONTROLS AND INDICATORS

Once started, the PDP16-M will be under complete control of the program stored in the control PROM. The

operator cannot intervene except to stop the machine by turning the power off. Therefore, an elaborate front panel
is not required. The front panel of the PDP16—M houses only a power key switch, a POWER indicator, a START
switch, and a RUN light. A pushbutton circuit breaker is located on the rear panel of the PDP16—M.

The PDP16-M can be started automatically upon power up or manually by depressing the START switch. A jumper
must be installed/removed to select one or the other start method (see Installation Chapter, Paragraph 2.4).

3.2

INSTRUCTION FORMAT

There are five basic types of instructions in the PDP16-M. They are:
LET

Used for Arithmetic/Logical operations and Data Transfers

GOTO

Unconditional Jump

Conditional Jump

CALL

Jump to Subroutine on Same Page

EXIT

Return from Subroutine on Same Page

The LET and EXIT instructions each require one 8-bit memory location and the GOTO, IF, and CALL instructions
use two

8-bit locations each (Figure 3-1). The GOTO and IF instructions use the same electronics with the condition

for the GOTO instruction always true.

OP
r

LET
EXIT

OP
l

GOTO
IF
CALL

fil

0
I

I
WORD

ADDRESS

(IZODE

(IIODE

WORD 2

l6-OOZ3

Figure 3—1 Instruction Format

3-1

LETInstruction

3.2.1

Codes: 0 to 2778

Operation that the PDP16-M is capable of performing has been assigned an 8-bit machine code. These
are stored in the control PROM and are decoded by the instruction and evoke decoders in the
control section and executed by the data section as 16-bit operations.
Each data

codes (object codes)

Control signals from the evoke decoders are wired to the control inputs (source and destination registers) of the data
sections to implement the instruction set of the machine.

Examples:
LET

/Clear the A Register

LET

A + 1

/lncrement the A Register

LET

/Load the B Register with constant 1

LET

A + B

/Add A and B together

LET

/Save results in Transfer Register

NOTE
The

assembler

will

allow

the

word

"LET"

used

optionally by the programmer.
3.2.2

GOTOInstructIon

Codes:

3008 and 3018

Address:

0—3778

n+1

X X

X X X

Bit M and the 8 bits in the next PROM location (n + 1) form a 9-bit address for a location on the current page. The
next instruction executed will be at the specified address.

3.2.3

lFInstruction

C C

CCCCC: MUX Channel

X X

°°d951t°358

Codes: 3028 to 3738

Address:

"+1

X X

0—3778

Bit M and the 8 bits in the next PROM location (n + 1) form a 9-bit address for a location on the current page.

The

next instruction executed will be at

the

specified address if the condition tested is true, otherwise the next

sequential instruction (n + 2) will be fetched.
3.2.4

CALLInstruction

Codes:

3748 and 3758

Address:

0—3773

"+1

R X [ X X X l X X Xj

Bit M and 8 bits in the next PROM location (n + 1) form a 9-bit address for a location on the current page. The next

instruction will be at the

specified address and the 9-bit return address will be saved in the 16-level hardware

pushdown stack.
3-2

3.2.5

EXlTlnstruction

C) ode:

3768 or 3778

6
—-J

_-|

—J

-J

The next instruction executed will be at the 9-bit address specified at the top of the subroutine pushdown stack. The
return point will be on the same page as the EXIT instruction.

BASIC INSTRUCTION SET

3.3

Only the basic instruction set is discussed in this chapter. Instructions implemented through options are discussed in
the option description. The following paragraphs define the octal machine code, execution time in microseconds,
instruction mnemonic, and description of all the instructions implemented in the basic machine.
3.3.1

Arithmetic Group

operations are executed by the General Purpose Arithmetic (GPA) Control (M7300) and Registers
(M7301). The following arithmetic operations have been implemented in the basic PDP16-M:

All arithmetic

Evoke

Time

(Octal Code)

(,USec)

Instruction

Description

000

2.4

Clear A

001

2.4

A gets 8

002

2.4

A + 1

increment A

003

2.4

Decrement A

004

2.4

A=A+B

005

2.4

A=A-B

AgetsA+B
AgetsA—B

A/2

A gets A/2 (shift right)

AX2

A gets AX2 (shift left)

012

2.4

013

2.4

014

2.4

A=A+ 1(3)

015

2.4

A=A-1(S)

016

2.4

A + B(S)

Same as above except overflow (OVF) bit is

017

2.4

020

2.4

B(S)
A/2(S)
AX2(S)

saved so it can be tested.

021

2.4

022

2.4

Clear B

023

2.4

B gets A

024

2.4

B=A+B

025

2.4

B=A—B

BgetsA+B
BgetsA-B
B gets B/2 (shift left)

8/2

032

2.4

033

2.4

B =A+B(S)

034

2.4

035

2.4

074

1.8

075

1.8

L =1

Set LINK

257

2.4

A + 1

B gets A incremented

260

2.4

A + 1(S)

B gets A incremented with OVF saved

261

2.4

B gets A decremented

B getsA +8 and save OVF

B(S)
B/2(S)

B gets A

B and save OVF

B gets B/2 (shift right) and save OVF

Reset LlNK

—

262

2.4

263

2.4

AX2

B gets AX2 (shift left)

264

2.4

AX2(S)

B gets AX2 (shift left) and save OVF

265

2.4

A/2

B gets A/2 (shift right)

266

2.4

A/2(S)

B gets A/2 (shift right) and save OVF

B gets A decremented with OVF saved

1(S)

3-3

Evoke

Time

(Octal Code)

(usec)

Description

lnstruction

267

1.8

270

1.8

272

2.4

273

2.4

OVF

LINK gets OVF

LNOT

Complement LINK

8/2

A gets B/ 2 (shift right)

B/2(S)

A gets B/2 (shift right) and save OVF

NOTE

The

Destination

then be tested using the conditional test instruction (Paragraph

3.3.8).

3.3.2

Logical Group

logical operations are also executed by the General Purpose Arithmetic (GPA) Control (M7300) and Registers
(M7301 ). The following logical operations have been implemented in the basic PDP16-M.

All

Evoke

Time

(Octal Code)

(usec)

Instruction

Description

006

2.4

A=AXORB

A gets A V B

007

2.4

A=AORB

A gets A V B

010

2.4

A =AB

A gets A A B

2.4

A =ANOT

Complement A

026

2.4

B =AXORB

B gets A V B

027

2.4

B =AORB

B gets A V B

030

2.4

B =AB

B gets A A B

031

2.4

01 1

BNOT

Complement B

3.3.3

The A

The following register instructions have been implemented in the basic PDP16-M:

Evoke

Time

(Octal Code)

(usec)

Description

Instruction

130

2.3

TR=A

Transfer Register gets A

131

2.1

A=TRU

A upper gets upper byte of TR

132

2.1

A lower gets lower byte of TR

133

2.1

A gets Transfer Register

250

2.0

276

2.3

277

2.3

A lower

A upper

-l-l-l>50:1 :" ”Om>>

0
0

Clear Transfer Register

Transfer Register upper gets upper byte of A
Transfer Register lower gets lower byte of A

Constant Generator Group

3.3.4
The

the GPA

and

the

Constant

Generator

module

(M7307) are-involved in executing these

instructions. The following constant instructions have been implemented in the basic PDP16—M:

Evoke

Time

(Octal Code)

(,Ltsec)

Instruction

Description

046

2.4

047

2.4

B gets Data constant 2

136

2.4

B gets Data constant 3

137

2.4

B gets Data constant 4

3.3.5

B gets Data constant 1

l/O Group

The basic PDP16-M is equipped to handle Boolean inputs, Boolean outputs, and 16-bit parallel l/O. Optionally, two

l/O channels and two additional parallel l/O channels can be added. Conditional jump instructions are
implemented for the Boolean input channels (Paragraph 3.3.8). The Boolean output channels can also serve as
program flags. Module M7306 contains the three flip-flops that serve as the flags and the source of the Boolean
output channels. As for the parallel l/O channel, both registers of the GPA (A and B Registers) and the General
Purpose Interface module (M7311) are involved in executing the parallel I/O channel instructions. The following l/O

serial

instructions for the Boolean output channels/flags and the parallel l/O channels have been implemented in the basic

PDP16'M:

Evoke

Time

(Octal Code)

(usec)

Description

Instruction

GPl1 getsA (Data out)

040

2.2

GPl1

041

2.0

056

1.8

FF1= 0

057

1.8

FF1 =1

Set Flag 1

060

1.8

FF2

Reset Flag 2
Set Flag 2

GPl1

A gets GPl1 (Data in)

Reset Flag 1

061

1.8

FF2

062

1.8

FF3

Reset Flag 3

063

1.8

FF3

Set Flag 3

255

2.2

GPl1

256

2.0

GPl1 gets 8 (Data out)

B gets GPl1 (Data in)

GPl1

Conditional Jump instructions are also implemented in the basic PDP16-M for testing the Boolean output channels
and for testing the odd bits of the A Register (Paragraph 3.3.8). Option PCSlG-D (Boolean input multiplexer option)
can

be installed to implement additional conditional jump instructions for testing the even bits of the A Register and

the M88 and LSB of the B

the LINK bit and the power OK signal.

3.3.6

Command Group

The command

instruction group facilitates the switching of control memory pages, switching Boolean input
and stopping the program. The instructions for switching pages and multiplexers serve their function

multiplexers
only if more than two control PROMs and/or the optional Boolean input multiplexer have been implemented. The
command instructions are:

3-5

Evoke

Time

(Octal Code)

(Lisec)

Instruction

Description

Get next instruction from PAGE 0

072

1.8

PAGE 0

073

1.8

PAGE 1

Get next instruction from PAGE 1

076

1.8

MUXO

Select test group 0 for IF instruction

077

1.8

MUX1

Select test group 1 for IF instruction

HA LT

Stops program

271

3.3.7

—

Test Group

Any time data is transferred via the PDP16—M data bus, a test for positive, negative, or zero data is automatically
performed. The result is stored in one of three registers (DP, UN and D2) in the M7332 Bus Sense and Termination
Module. One of three conditional jump instructions can then be programmed (Paragraph 3.3.8) to jump to another
part of the program based on the stored test result. Some register-transfer instructions do not transfer data on the
bus and therefore the result from the previous test is cleared since no data (zero data) is on the bus. To facilitate

retesting the contents of the A or B Register for a subsequent conditional jump, the following two test instructions
have been implemented in the basic PDP16—M:

Evoke

Time

(Octal Code)

(usec)

Instruction

Description

036

2.4

EXA

Examine A and set DP, DN, or D2

037

2.4

EXB

Examine B and set DP, DN, or DZ

3.3.8

Conditional Jump Group

The GOTO and IF instructions are considered to be conditional jump instructions in the PDP16-M. A 30-channel
Boolean input multiplexer is employed to provide the condition to be tested in response to the object code (machine
code) of the programmed jump instruction. The GOTO instruction selects channel 00 of the multiplexer. This
channel

connected

+3V and therefore the GOTO instruction will always

cause

jump resulting in

unconditional jump. The other channels of the multiplexer are connected to internal and external Boolean
conditions. These conditions may be true or not true. The program control sequencer (M7336) performs the test for
true or not true to determine which program sequence to execute. The following conditional jump instructions have

been implemented in the basic PDP16-M:

Machine Code

Time

(Octal)*

(psec)

MEMO

MEM1

300

Instruction

False

True

Description

301

2.0

3.2

GO TO

Test channel 0 input (+3V)

302

303

2.0

3.2

IF EXT1, LABEL

Test channel 1 input (EXT1)

304

305

2.0

3.2

IF EXT2, LABEL

Test channel 2 input (EXT2)

306

307

2.0

3.2

IF EXT3, LABEL

Test channel 3 input (EXT3)

310

311

2.0

3.2

IF EXT4, LABEL

Test channel 4 input (EXT4)

3.2

IF EXT5, LABEL

Test channel 5 input (EXTS)

3.2

IF EXT6, LABEL

Test channel 6 input (EXT6)
Test channel 7 input (DZ)

312
314

313

2.0

315

2.0

317

2.0

3.2

IF DZ, LABEL

320

321

2.0

3.2

IF DP, LABEL

Test channel 8 input (DP)

322

323

2.0

3.2

IF DN, LABEL

Test channel 9 input (DN)

316

Machine Code

Time

(Octall*

(usecl

Instruction

Description

MEMO

MEM1

True

False

324

325

2.0

3.2

IF OVF, LABEL

Test channel 10 input (OVF)

326

327

2.0

3.2

IF A<1>, LABEL

Test channel 11 input (A<1>)

330

331

2.0

3.2

IF A<3>, LABEL

Test channel 12 input (A<3>l

332

333

2.0

3.2

IF A<5>, LABEL

Test channel 13 input (A<5>)

334

335

2.0

3.2

IF A<7>, LABEL

Test channel 14 input (A<7>)

336

337

2.0

3.2

IF A<9>, LABEL

Test channel 15 input (A<9>)
Test channel 16 input (A<11>)

340

341

2.0

3.2

IF A<11>, LABEL

342

343

2.0

3.2

IF A<13>, LABEL

Test channel 17 input (A<13>)

344

345

2.0

3.2

IF A<15>, LABEL

Test channel 18 input (A<15>)

346

347

2.0

3.2

IF FF1, LABEL

Test channel 19 input (FF1)

350

351

2.0

3.2

IF FF2, LABEL

Test channel 20 input (FF2)

352

353

2.0

3.2

IF FF3, LABEL

Test channel 21 input (FF3)

354

355

2.0

3.2

IF FF4, LABEL

Test channel 22 input (FF4)

356

357

2.0

3.2

IF FF5, LABEL

Test channel 23 input (FF5)

360

361

2.0

3.2

IF FF6, LABEL

Test channel 24 input (FF6)

362

363

2.0

3.2

IF KF1, LABEL

Test channel 25 input (KF1)

364

365

2.0

3.2

IF PF1, LABEL

Test channel 26 input (PF1)

366

367

2.0

3.2

IF KF2, LABEL

Test channel 27 input (KF2)

370

371

2.0

3.2

IF PF2, LABEL

Test channel 28 input (PF2)

372

373

2.0

3.2

IF CLK, LABEL

Test channel 29 input (clock)

*Codes are given for jumps into or within memory 1 and into or within memory 2. The least significant bit of the
machine code is in M (memory) bit.

3.3.9

Subroutine Group

The hardware stack in the program control sequencer (M7336) automatically keeps track of the return address when
a

subroutine is called. Sixteen return addresses can be stored in the stack. Therefore, up to sixteen subroutines can

be called before

returning to the main program. The following instructions have been implemented in the basic

PDP16-M to facilitate jumping to and returning from subroutines:

Machine Code

Time

(Octal)

(usec)
3.2

374

Instruction

Description

CALL LABEL

Jump to a subroutine in memory 0 of
the current page

375

3.2

CALL LABEL

Jump to a subroutine in memory 1 of
the current page

3.2

377

3.4

EXIT

Return from a subroutine

A AND B REGISTERS

The A and B Registers are used to perform arithmetic and logical operations (Paragraph 3.3) on 16-bit data. Program
data is not stored in the control PROM but in separate Constant or Data ROMS. The A Register is the accumulator
and the 8

Register is the argument register. The status of bits 1, 3, 5, 7, 9, 11, 13 and 15 of the A Register can be
option is implemented, the remaining bits of the

tested with the IF instruction if MUXO is selected. When the MUX1

3-7

MUX1 in the program. An example of how to write the IF instruction for the A and B Registers follows:
IF A<3>, TRUE

TRUE

Instruction for false condition

/A<3> is logic 0

Instruction for true condition

/A<3> is logic 1

Notice that a comma separates (delimits) the MUX condition (A<3>) to be tested and the program label (TRUE),
and a space (or tab) separates the instruction word (IF) and the MUX condition (A<3>).

3.5

LINK (OVERFLOW)

The Link bit is connected to the left and right shift inputs of the A and B Registers. It is affected only by the four
Link instructions:

/Clear Link

/Set Link to Logic “1"

LNOT

/Complement Link

OVF

/Set Link Equal to Overflow

zero during power on. Its state may be tested by an IF instruction if the MUX1 option is
implemented, and MUX1 is declared in the source program. Refer to PCSIG-D option description in Appendix A.

The Link is set to

3.6

BOOLEAN l/O

Three programmable control flip-flops (FFI

—-

FF3) and six external Boolean inputs (EXTI

—

EXT6) are provided

in the basic PDP16-M. Space is reserved for expansion to 6 programmable flip-flops and 22 external

inputs. These

inputs and outputs may be used for l/O synchronization or for testing external TTL logic levels under program
control. All signals are available through the MUX and FF l/O socket located at the rear of the logic assembly.
Each input presents one TTL unit load and each flip-flop output can drive seven TTL unit loads.

inputs and outputs are unbuffered TTL logic levels. If distances greater than five feet are to be driven and
received, it will be necessary to use a K or M series module interface to buffer the signals. Refer to the DIGITAL
Control and Logic Handbooks (C110 and C105).

These

3.7

GPI1 (GENERAL PURPOSE INTERFACE)

—-

PARALLEL l/O

The basic PDP16—M contains one 16-bit parallel l/O interface designated GPI1. Space is reserved on the data bus for

parallel l/O options. The interface consists of a 16-bit flip-flop output register and 16 input gates for
FF3 are available at the interface of
placing external data on the PDP16-M bus under program control. Flags FFI
GPI1
GPI3, respectively, for use in l/O synchronization.

two additional

—

Once data is loaded into the output register, it will remain unchanged until the next time data is transferred to the
interface. The output register is set to zero during power on.

3-8

CONSTANT GENERATOR IC)

3.8

The basic PDP16-M contains a ROM Constant Generator (C) capable of storing four 16-bit data constants. Since data
constants that may be

required for the program cannot be stored in the control PROM, the constant generator is

included in the basic machine to store these constants.

TRANSFER REGISTER (TR)

3.9

The Transfer

storing results.

3.10

BUS SENSE AND TERMINATOR

The bus sense and terminator module contains three 1-bit registers (DP, DN, and D2), the bus terminator, and some
timing logic. Every time a data transfer is evoked, a test for positive, negative, and zero is automatically performed
and the result is automatically stored in one of the three 1-bit registers. Since no data is transferred on the bus when
a FF, PAGE, MUX, LINK, or HALT instruction is executed, the bus is zero and the D2 Register will then be set.
The EXA and EXB instructions are therefore provided to permit the previous data transfer to be re-examined for a
subsequent conditional jump (IF DP, LABEL).
For example:
LET A

/A is incremented

A + 1

MUXO

/MUXO is selected

EXA

/A Register is retested for DP, DN, or DZ

IF DP, POSITIVE
Instruction for not positive condition
POSITIVE

3.11

Instruction for positive condition

MUX SELECTION

NOTE
This feature of the PDP16—M

applies only to those machines

that have the MUX1 option (PCS16-DI implemented.

The instructions MUXO and MUX1

are

used to select the

input multiplexer to be used for executing the IF

instruction. Channel 0 (instruction code 3008 and 3018) on both multiplexers are hard wired to +3V for the GOTO
instruction. Once a

multiplexer is selected, it will remain selected until the other multiplexer is specified by a MUXO
The MUXO and MUX1 instructions also zero the bus. Therefore, a detect zero (DZ)
conditional jump instruction (IF DZ, LABEL) will always be true if it is preceded by a MUX instruction.
or

MUX1

instruction.

For example:

MUX1

/change multiplexer

IF DZ. LABEL

/this test will be true

NOTE
At the time the PDP16-M is turned on, MUXO is selected and
remains selected until a MUX1 command is executed.

3-9

3.12

PAGE SELECTION
NOTE
This feature of the PDP16-M

applies only to those machines

that

control

have

than

two

PROMs (>512 words)

implemented. At the time the PDP16—M is turned on, PAGEO
is selected and remains selected until

PAGE1 command is

executed.

The 1024 X 8 control memory (maximum that can be implemented) is divided into two pages with 512 locations on
each page. Any location within a page, can be directly addressed, however, locations in the other page are not
directly addressable. Two instructions, PAGEO and PAGE1, are used to control the PAGE select flip-flop to switch

from one page of instructions to the other.
When the paging instructions are used, the next instruction executed will be in the page requested at an address one

greater than the address of the instruction.
Instructions cannot be sequentially executed from one page to the next. The next location after the last location on
the page is the first location on the same page.

The page instructions also zeros the bus. Therefore, a detect zero (DZ) instruction will always be true if it is
preceded by a page instruction. (See Paragraph 3.10 for example.)
3.13

PAGE LINKAGES

The programmer must write some code (page linkages) for switching pages and calling subroutines on the other page
This code is illustrated in examples A and B that follow:
A.

Switching Pages
1.

The program will start at Location 0 in Page 0 and run until it reaches the GOTO P1 instruction.

At label P1 (location 775), Page 1 will be selected and the next instruction will be fetched from location

1776. This will cause a jump to the location labeled XYZ in Page 1.
3.

The program will run until it reaches the GOTO P0 instruction.

label

P0 (location

1775), Page 0 will be selected and the next instruction will be fetched from

location 776. This will cause a jump to the location labeled ABC in Page 0.

0000

1000

XYZ

GOTO P1
ABC

GOTO P0

HA LT

ORG 1775

ORG 0775
0775

0776

PAGE1

1775

GOTO ABC-

1776

0777

PAGEO
GOTO XYZ

1777

Page 1

Page 0
3-10

Calling Subroutines on the other Page
1000

0000

SUBI

CALL SUB1 X

EXIT

CALL SUB1X
SUB2

CALL SUB2X

GOTO A
SUB3

CALL SUBBX

EXIT
0766

SUB2X

ORG 766

EXIT

PAGE1

ORG 1767

0767

1767

0770

1770

CALL SUBZ

PAGEO

1771

0771
0772
0773

SUBI X

0774

EXIT

1772

PAGE1

1773

CALL SUBB

1774

SUBBX

PAGEO
CALL SUB1

1775

0775
0776

PAGE1

1776

PAGEO

0777

EXIT

1777

EXIT

Page 1

Page 0

Call SUBI on Page 1 from Page 0 twice.

Call SUB2 on Page 1 from Page 0.

SUB2 calls SUBS on Page 0.

Repeat.

Notes For Examples A and B:
1.

Use

origin statement (ORG n) to position linkage. For example, the statement following ORG 1778 will be

stored in location 2008
2.

No linkage is required in calling subroutines on the same page.

Remember that the next instruction that is executed after a PAGE instruction will be that instruction which
appears in the next sequential location on the specified page.

GOTO, conditional jumps (IF), CALLs and EXlTs
PAGE1 instruction must be used for this purpose.

cannot

jump across page boundary. The PAGEO and

CHAPTER 4
THEORY

4.1

OF OPERATION

INTRODUCTION

Two types of instructions are implemented in the PDP16-M:
Evoke Data Transfer

Jump (Control)
A data transfer between the PDP16—M data modules is evoked by any of the

involving the specified data module registers.
Instructions (LET)
Arithmetic and Logical Set
A Register

B Register

L (LINK)

Boolean Set
FF1

FF2
FF3
Data Memory Set

TR Register
C Constant Generator

l/O Set
GP|1

Commands

PAGEO, PAGEl
MUXO, MUX1
HALT

4-1

following instructions/commands

assigned octal codes 0—277. Individual evoke signals are produced by the
Register and a module
Destination Register via a 16-bit data bus (Figure 4-1). A 5-line control bus carries DATA READY, DATA ACCEPT,

The 192 data transfer instructions

are

evoke decoders in response to these codes. The transfer is made between a module Source

and DONE timing signals to ensure proper interlock for all data transfers. The control bus also carries the POWER

signal and the OVERFLOW (OVF) bit. All data modules are connected to the control and data bus. The
High impedance receivers and open-collector drivers are employed in each
data module to transfer data between the module Source and Destination Registers. A bus terminator (load and
pull-up resistors) is located in the bus sense and termination module to terminate each bus line with a TTL level and
to provide the necessary current for the bus receivers.
CLEAR

data bus of the PDPlG-M is bidirectional.

The evoke data transfer instructions are implemented by the wire-wrap connections from the evoke decoder outputs
to the control

(LET A
<-

inputs of the data modules. For example, the evoke decoder output for the instruction A <- A + B

A + B) is wired to the control input A + B of a module Source Register (resulting in a data transfer of BUS

A + B) and to the control

input LDA (load the A Register) of a module Destination Register (resulting in a data

transfer of A <- BUS). After the data transfer of BUS <— A + B, the DATA READY control signal is asserted which
allows the data transfer A <- BUS to be completed. After the data transfer A <- BUS, the DATA ACCEPT control

signal is asserted. The DONE signal is asserted after both DATA READY and DATA ACCEPT have been asserted.
The DONE signal restarts the clock and causes the next instruction to be fetched.

CONTROL
PROM

(1024 MAX)
B-BIT
M DATA

IO-BIT
ADDR

0-277

PROGRAM
CONTROL
SEQUENCER

EVOKE DECODER
(192 MAX)
2

A=A+B

B=A+B(S)

A=GPI1

LDA

(DESTHSOURCE)
GPl‘I

LDB

GPA
REGISTER M7301
(DEST)

A+1

A-‘I

OVF

ZERO

BUS

GPA CONTROL M7300
(SOURCE)

DATA READY
DATA ACCEPT
DONE
W
R CLEAR

16 DATA BITS

IG-OOOI

Figure 4-1 Evoke Data Transfer Scheme

A jump (control) is caused whenever any of the following instructions is executed:

GOTO
IF

CALL
EXIT

These instructions are not involved with data transfers on the data bus (Figure 4-2). The GOTO and IF instructions
effect a test of a particular input to Boolean multiplexer 0. Octal codes 300 through 373 have been assigned to these
instructions (this amounts to 60 combinations). However, the least significant bit of the instruction code is the M

(Memory) address bit, resulting in only 30 possible test instruction codes. The M bit is tested every time a GOTO, a
lF, or a CALL instruction is executed. This bit is then stored and added as the most significant bit to the jump
address fetched from the control memory. Before the inputs to Boolean multiplexer 0 can be tested with the IF
true

instruction, the MUXO command must be declared in the control program. MUXO is selected when the PDP16—M is
turned on. It remains selected until MUX1 is declared in the program. Then, the only way a MUXO condition can be
tested

is to redeclare MUXO in

the program. The IF instruction (octal codes 302—373)

causes

either

skip

(increment PC) to the next instruction (test is not true) or a memory request to fetch the eight least significant bits
of the jump address (test is true). The most significant bit of the address is the M bit of the instruction code. The

GOTO instruction (octal code 300—301) will always cause a memory request to fetch the eight least significant bits
of the

jump address because this test will always be true. It will be true because the multiplexer channel for the

GOTO instruction is hard wired true.

CONTROL

[—Pd

(1024MAX)
B’B'T
MEM DATA

lO-BiT
ADDR

0-2778
EVOKE EN

>0
MR0

CALL

EXIT

8-BIT
MEM DATA

EVOKE DECODER

(192MAX’)

778

768

MUXO

MUX1

(PUSH) (POP)
_

0—j

STACK
MBY
‘—-->O

PROGRAM

3 00

CONTROL
SEQUENCER
TEST

3738

MUX1

( MUXO
BOOLEAN MUX o

CONDITION

0i 1i 2i

.—

______________________

(OPT)

2§i

TEST CONDITIONS
l6-OOZ4

Figure 4-2 Control Scheme

The CALL and EXlT instructions (octal codes 374—377)

use

neither the data bus nor the Boolean

multiplexer.

These instructions use the stack in the program control sequencer to store the 9-bit return address. The stack is 16
words deep, allowing up to 16 calls before returning.

4.2

CONTROL SECTION

4.2.1

Program Control Sequencer

As the

name implies, the program control sequencer is the controlling element in the PDP16-M. The following
operations are performed by the program control sequencer.

Decodes Instruction

Generates timing states for executing instructions

Keeps track of the program count (PC) or address

Keeps track of the return address for a subroutine call

4.2.1.1

Start, Clock, and Evoke Enable Logic

—

When the PDP16-M is started, it is initialized by

resetting the

program counter (PC) and the state generator (Figure 4-3). After a small delay, the RUN light is turned on and the
clock is enabled. However, the clock remains off until the MBY (memory busy) single-shot recovers.

This single-shot is triggered when the machine is started or when the state generator is in state 0 or 6. After the MBY

single-shot recovers, the state generator is clocked to execute the instruction. If the instruction is an evoke data
transfer instruction (LET instruction or command), the Evoke flip-flop is set to enable the evoke decoders. Upon
completion of the data transfer, the DONE signal will reset the Evoke flip-flop. Termination of the DONE pulse will
restart the clock.

4.2.1.2

Instruction

Decoder—Simple combinational logic (Figure 4-4)

is used to decode the 8-bit instructions

fetched from the control PROM. Besides the seven bits of the Memory Data (MD1—MD7), the combinational logic
receives INST DEC EN from the state generator and TEST CONDITION from the Boolean input multiplexer. The
instruction decoder is enabled when the machine is started and after each instruction is executed. It is enabled for

only one-half clock period when the state generator is in state 0. Only one output from the instruction decoder is
asserted when the decoder is enabled. This output then jam sets the state generator to a specific count.
4.2.1.3

State Generator

The state generator (Figure 4-5) consists of three input gates, a 3-bit register, a
binary-to-octal decoder and feedback logic. The input gates receive the output from the instruction decoder to jam

set the state generator.

—

The state generator is reset (state 0) when the machine is started and after each instruction is

executed. A memory request (MRO) is issued and the instruction decoder is enabled by state 0. Flip-flop A is set by
the state 0 output of the state generator and reset the next time the clock goes low. Therefore, the instruction
decoder is enabled for only one-half clock period. From the jam set count, the state generator will progress through

series of states (Figure 4-6) as it is clocked. The sequence is defined by the jam set state and the feedback logic. All
operations required to execute the decoded instruction are performed during these states.

The state generator has 8 states (0

through 7). Each state is assigned a particular function. These functions are

described in state Table 4-1. The table also identifies the jam state for each instruction, current state, and next state.
A general timing diagram is given in Figure 4-7.

By examining Figure 4-5, one will notice that the feedback logic is arranged so that a return to state 0 can only be
achieved from state 3 or state 7. The clock loads the 3-bit register with whatever the feedback logic receives and then.
enables the binary-to~octal decoder. The register is clocked on the positive clock transition and the binary-to-octal
decoder is enabled for the negative clock period.

Table 4-1
State Table

Current/Jam State

Instruction

START

Description
Memory Request (MRO).

Next State

Depends on

Instruction is decoded be-

Instruction

tween state 0 and the next

Decoded

state (state generator is

disabled while clock is high)
IF not true

lncrement PC

CALL

Stack return address

LET

Decode evoke, transfer

data, and increment PC
EXIT

Get Return address and

load into PC

Test and store M bit of

lF true

instruction code and
increment PC

——

Memory Request

Load PC with M bit

and jump address

4.2.1.4

Program Counter (PC) and Stack

-—

The PC is a 9-bit register that points to the memory location within a

page of the control PROM from which the current instruction was fetched. The PC can be incremented to point to
the next sequential memory location or it can be loaded with the jump address from the control PROM or from the
stack. The jump address from the control PROM is only 8 bits. These 8 bits are loaded into the 8 least significant bit

positions of the PC. The ninth bit, which is taken from the least significant bit position of the instruction code, is
flip-flop. A 9-bit address can address up to 512 words of storage. The PAGE flip-flop, which is
programmable with the PAGEO and PAGE1 commands, serves as the tenth bit of the address extending the
addressing capability to 1024 words. The stack is a read—write memory with 16 9-bit locations. A 4-bit up/down
counter serves as a pointer to address the stack. The stack can be loaded with the contents of the PC or the PC can
be loaded with the contents of the stack. Each time the stack is loaded with a word, the pointer is incremented to
select another stack location for the next entry. When the stack is to be read, the pointer is decremented before the
stack is read to get the correct return address. Each of the following types of instruction operate on the PC in a
stored in the M

different way:
LET

—

evoke data transfer

GOTO/lF (true)
lF (not true)

CALL

EXlT

—

—-

—

unconditional/conditional jump

conditional jump

subroutine jump
subroutine return

After the memory request (state 0), which occurs when the program is started or after an instruction is executed, the
state generator will progress in a fashion described

by the instruction code itself and the feedback logic of the state

generator. The memory request is not directly involved with fetching the instruction from the control PROM. it is

only issued

stop the state generator clock long enough

transfer the data from the control PROM to the

instruction decoder or the PC if it is a jump address.
If the PC

points to a memory location containing an evoke data transfer (LET) instruction state 3 is asserted, an

interlocked data transfer (Figure 4-7) is effected and the PC is incremented to point to the next instruction (Figure

4-8)

If the PC points to a GOTO or an lF instruction that is true, the following occurs:

State 5 is asserted after state 0 (Figure 4-9). This is because the instruction decoder found that the test is
true

(Figure 4-4). The M bit of the instruction code is tested and stored. The PC is also incremented to

advance to the jump address location.
The state generator advances to state 6, causing another memory request to be issued. This stops the
state generator clock long enough to transfer the data (in this case it will be the 8-bit jump address) to
the receivers for the PC.

State 7 is then asserted to load the PC with the M bit and the 8-bit jump address.
After state 7, state 0 is asserted to fetch and decode the next instruction.

If the PC points to an IF instruction that is not true, the following occurs:
State 1 is asserted after state 0 (Figure 4-10). The PC is incremented in state 1 and incremented again in
state

3. incrementing the PC twice for this instruction results in a skip over the jump address and leaves

the PC pointing to the next instruction.

State 0 is then asserted to fetch and decode the next instruction.

If the PC points to a CALL instruction, the following occurs:

State 2 is asserted after state 0 (Figure 4-11). The contents of the PC is loaded into the stack and the

pointer is incremented.

NOTE
The contents of the PC is not changed.

The M bit of the CALL instruction code is tested and stored. The PC is also incremented to advance to
the jump address location.

('3

The state generator advances to state 6, causing another memory request to be issued. This stops the
state generator clock long enough to transfer the data (in this case it will be an 8-bit jump address) to the

receivers for the PC.

State 7 is then asserted to load the PC with the M bit and the 8-bit jump address.
After state 7, state 0 is again asserted to fetch and decode the next instruction.

4-6

If the PC points to an EXIT instruction, the following occurs:

Following state 0 and before

state

(instruction is decoded while the clock is high and the state

generator is disabled), the stack is decremented to point to the most recent subroutine return address.
b.

When state 4 is asserted (Figure 4-12), the contents of the addressed stack location is loaded into the PC.

State 1

is then asserted. The PC is incremented in state 1 and again in state 3. The PC is incremented

twice because the address received from the stack is the address of the CALL and the location following
the call

was

the

jump address. Therefore, to continue with the program, the stacked address must be

incremented twice.

4.2.2

After state 3, state 0 is again asserted to fetch and decode the next instruction.

Memory and Page Select

The control program for the PDP16—M is stored in a programmable Read-Only-Memory (PROM). Any constants or
data that may be

required by the program are stored in a separate ROM constant generator. Up to four control

PROM modules (Figure 4-13) can be implemented in the PDP16—M. One is supplied with the basic PDP16-M and the

remaining three are optional. Each PROM module can store 256 8-bit words. Fully implemented, the 1024-word
control memory is divided into two 512 word pages; each containing a memory 0 and a memory 1 of 256-words
each (Figure 4-13). Eight address bits (MA00—07) are required to address every location in a given memory. The
ninth bit (MA8) is used to select the desired memory (0 or 1) in a given page. This bit is the M bit (LSB) of the
control code for a jump (GOTO, IF, and CALL) instruction. The tenth address bit (PAGE bit) is used to select the
desired page. This bit is not stored in the control PROM but is programmable.

Whenever PAGEO

PAGE‘l

is declared in the control program, the BS

0 and the PAGE

evoke logic is

activated. The clock in the program control sequencer is also stopped when either PAGE command is declared. The

clock is

not the
stopped while both data transfers are evoked and is restarted only by the CONTINUE signal
Two
in
evoke
circuits
are
used
to
allow
the
select
to
series
stabilize
before
signal.
page
logic
asserting the
CONTINUE signal to reactivate the clock.
——

DONE

4.2.3

Boolean Input Multiplexers

The Boolean multiplexers (Figure 4-14) are used only with the GOTO and IF instructions

—

not with the evoke data

transfer nor the CALL instruction. The basic PDP16-M is supplied with one Boolean

input multiplexer, designated
MUXO. The other Boolean input multiplexer (MUX1) is optional. Each multiplexer is capable of selecting one of 30
data inputs for test. The test for the GOTO and IF instruction is performed by the instruction decoder in the
program control sequencer. Table 4-2 lists the conditions that can be tested.

NOTE
Octal

machine

memory

0 and

codes
in

are

() into

given for jumps
or

into

within

within memory 1. The least

significant bit of the code is the M (Memory) address bit.

The commands MUXO and MUXl must be declared in the application program to test the corresponding data set.

Once a multiplexer is selected, it will remain available until the other multiplexer is selected. MUXO is automatically
selected during power-up.

4-7

Table 4-2
Boolean Multiplexers Inputs

MUXO

Condition

MUX1

Octal
Machine Code

4.2.4

+3V (GOTO)

300 (301)

EXT 1

A <0>

302 (303)

EXT 2

A <2>

304 (305)

EXT 3

A <4>

306 (307)

EXT4

A<6>

310(311)

EXT 5

A <8>

312 (313)

EXT 6

A<10>

A<12>

A <14>

B <0>

314(315)
316(317)
320 (321)
322 (323)

OVF

B <15>

324 (325)

A <1>

EXT 7

326 (327)

A <3>

EXT 8

330 (331)

A <5>

EXT 9

332 (333)

A <7>

EXT 10

334 (335)

A <9>

EXT 1 1

336 (337)

A <11>

EXT 12

340 (341)

A <13>

EXT 13

342 (343)

A <15>

EXT 14

344 (345)

FF1

EXT 15

346 (347)

FF2

EXT 16

350 (3131)

FF3

EXT 17

352 (353)

FF4

EXT 18

354 (355)

FF5

EXT 19

356 (357)

FF6

EXT 20

360 (361)

KF1

EXT 21

362 (363)

PF1

EXT 22

364 (365)

KF2

366 (367)

PF2

PWOK

370 (371)

CLK

GND

372 (373)

Evoke Decoders

not with the jump
(Figure 4-15) are used only with the evoke data transfer instructions
(GOTO, IF, CALL, or EXIT) instructions. The basic PDP16—M is supplied with four evoke decoders. Two are
optional and are required if the Scratch Pad (SP) memories are implemented. Each evoke decoder module is capable
of decoding 32 unique evoke signals for data transfers. Each decoder receives the 8-bit memory data (MD00—07).
The three most significant bits of the memory data (machine control code) are used to select the proper decoder.

The evoke decoders

The five least significant bits (MD00—04)

—

are

used to select

one

of the 32

possible output states. The decoder

address (MD05—07) is decoded by the three exclusive OR gates. Each decoder socket is prewired to provide the
Exclusive OR gate a unique combination of ground and +5V (see table of Figure 4-15). Therefore, all evoke decoders
are

interchangeable within the range of their assigned sockets without modification.

4.3

4.3.1

DATA SECTION

General Purpose Arithmetic (GPA) Unit, LINK and OVERFLOW

The GPA unit (Figure 4-16) is formed by two adjacent modules: GPA Control M7300 and GPA

Register M7301.
operation encoder, the right shift logic, and drivers while the M7301 contains the A
Register (accumulator), the B Register (argument register), the Arithmetic and Logic Unit (ALU), and the data ready
and accept logic. The Link flip-flop is located on a separate module. All arithmetic and logical operations that have
been implemented in the PDP16-M are executed by the GPA unit. The LlNK Register permits simpler algorithms to
be employed in performing arithmetic.
The M7300 contains the

The output from the evoke decoders evoke the arithmetic or logical operation and the transfer of data between the

registers of the GPA unit and LINK. By using the proper instructions, data transfers can also be evoked between
GPA registers A or B and other data module registers (TR, GPl1, etc.). As mentioned earlier, a data module may
have a Source Register, a Destination Register or both. The GPA unit has two registers (A and B). Either of these
registers can serve as Source or Destination Registers.

The ALU and the right shift/driver logic

(output logic) serve as a function generator when an arithmetic or logical
specified in the instruction. A summary of the implemented arithmetic and logical operations and
associated encoder outputs for the ALU and output logic is given in Table 4-3. The operations can only be
performed on the contents of the A or B Register (source) and the result can only be stored in the A or B Register
operation

(destination)

—

not the TR or GPI1 etc.

Table 4-3

GPA Units Operations Summary
I

Source Evokes

Encoder Output

Operation
S/2

A + 1

A + B

A X 2

A/ 2

B/ 2

NOTA

NOTB

0
0

A0 RB

AXOR B

Destination Evo kes

A (LDA)

See Above

B (LD B)

See Above

4-9

Once the arithmetic or logical operation is executed and the result is stored in A or B, the data can be transferred to
another data module Destination Register (TR or GP|1 in the basic machine) using the appropriate instructions. The

receive data

can

only from the

are

available to

expand the Destination Registers.

Constants/Data required in performing arithmetic or logical operation are stored in a 4-word constant generator (C

Register) ROM. Since a ROM can only be read, it can therefore only serve as a Source Register. Constants in this
register must be transferred to the B Register using the appropriate instruction. Besides the A, B, and C Registers,
additional Source Registers in the basic machine are the TR and GPI1. Using the appropriate instructions, data from
these registers can be read into the GPA unit. The result from an arithmetic or logical operation that is temporarily
stored in the TR can be read back into the A Register but not the B Register. Data from the “outside world” (GPI1)
can

be read into either the B or the A Register.

For each arithmetic or logical operation and for each data transfer involving the GPA, a DATA READY and a DATA

Registers, respectively. Bits O1, 03, O5, O7, 09, 11, 13, and 15
Register
input
multiplexer 0. These bits can be tested using the IF
instruction. The remaining bits of the A Register and bits 00 and 15 of the B Register can be made available for test
if the multiplexer 1 option is incorporated into the basic machine. Examples of the test instruction follow:

ACCEPT is generated by the Source and Destination
of the A

are

routed to

channels of Boolean

IF A <1>, LABEL 1
IF A <3>, LABEL 2
IF A <15>, LABEL 3
If the condition tested is true (logical 1), then a jump to the specified program label is executed; otherwise, the next

instruction is executed.
The OVF

1-bit

capability of the GPA unit. It is used as a Carry Register for 2's complement arithmetic or as a Holding Register for
shift operations. Under program control, the OVF bit can be checked and loaded into the LINK Register. LINK can
then be rotated

part of the A or B Register to simplify arithmetic algorithms. The LINK Register can also be

cleared, set, and complemented. The following instruction evoke data transfers to the LINK bit register:
INSTRUCTION

Destination

4.3.2

Source

Remarks

OVF

OVF is stored in bus sense (BS) module if saved (S)

imaginary source
imaginary source
imaginary source

LNOT

Transfer Register (TR)

The TR

(Figure 4-17) is a one-word byte and word addressable register. It can be used for temporarily storing results

of arithmetic or

logical operations appearing in the A Register or storing data from the outside world via GP|1 and

the A Register. The stored data can be read back into the A Register when needed, using the appropriate instruction.

The following instructions evoke data transfers between the TR and the A Register via the data bus.

STOR E

Destination
TR

TRU
TRL

—

READ

Source

Destination

Source

4-10

Remarks

word

TRU

upper byte

TRL

lower byte

To complete the data transfers specified by the above instructions, a DATA READY is issued by the Source Register
and a DATA ACCEPT is issued by the Destination Register.

4.3.3

Constant Generator (C)

The constant generator (C) is

a four-word diode ROM (Figure 4-18). The desired constants/data are selected by
removing or not removing the jumpers associated with a given word. With the jumper left in place, logic Is are placed
on the bus (bus lines are asserted
LOW) when the constant is transferred. If a 0 is desired for a particular bit
HIGH), the corresponding jumper must be cut. Constants can be
position of a word (bus is not asserted
transferred only to the B Register. The following instructions evoke data transfers between the constant generator
and the B Register via the data bus:
—

—

INSTRUCTION

Destination

To complete the data transfers

Source

Remarks

Word 1

Word 2

Word 3

Word 4

specified by the above instructions, a DATA READY is issued by the constant

generator and a DATA ACCEPT is issued by the GPA unit.
4.3.4

General Purpose Interface No. 1 (GPl1)

The GPII

(Figure 4-19) is a one-word l/O interface. It can be used for transferring data between the A or B Registers

and the outside world. The following instructions evoke data transfers between the A or B Registers and the outside

world via the GPII.
RECEIVE

SEND

Destination

Source

Destination

GPI 1

GP|1

Source

GPII

GPI1

To complete the data transfer Specified by the above instruction, 3 DATA READY is issued by the Source Register
and 3 DATA ACCEPT is issued by the Destination Register.

Details for interfacing with the PDP-11 low-speed peripherals are presented in the DA16~F option description (refer
to Appendix A).

4.3.5

Bus Sense and Termination Module (BS)

The bus sense and termination module (Figure 420) performs a variety of functions:
a.

The module terminates the data bus and provides the source current for the open-collector drivers of all

Source Registers in the data modules.
b.

as a Destination Register (3-bits) to recapture the test result (positive, negative, or
zero) from the previous data transfer. This may be required if a conditional test (IF instruction) on the

The module serves

transferred data is to be made after a FF, PAGE, MUX, LINK, or HALT instruction is executed. These
instructions zero the bus (no data is transferred on the bus) and activate the DZ Register in the bus sense
and termination module. Therefore, the test result from the previous data transfer is lost and must be

recaptured in order to execute the conditional test successfully.

4-11

The module serves as a Destination Register (1 bit) to store the overflow (if any) from the GPA unit.

The module serves

pseudo Source and Destination Register to zero the bus (BS), and a pseudo

Source Register to zero the GPA unit A or B Registers or the Transfer Register (TR).
The module generates the DONE signal whenever a Destination Register (in any data module connected

to the

bus) accepts the data

—

DATA ACCEPT is asserted. The DONE signal restarts the clock after a

data transfer instruction.

The module generates the START signal (AUTO/MANUAL) and POWER CLEAR signal.

The bus terminators and current sources are not shown in

Figure 4-20. Refer to circuit schematic D-CS-M7332 for

the circuit details.

Every data transfer instruction causes an automatic test of the data being transferred. The test is for positive,
negative, or zero data. The following instructions evoke data transfers between the A or B Register and the bus sense
and termination (BS) module just to test the data without any actual transfer of data between any data registers.
EXA
EXB

complete the data transfers specified by the above instructions, a DATA READY is issued by the GPA unit
register (A or B) and a DATA ACCEPT results by asserting the BUS gate of the bus sense and termination module.
The DATA ACCEPT signal clocks flip-flops DN, D2, and DP and generates the DONE signal. Each of the three
flip—flops receives, as its data input, a logic level derived from the bus through combinational logic. The following
logic definitions prevail on the data bus because the bus is driven by open-collector drivers that are turned on by
logic 15 (HIGH):
To

HIGH

LOW

LOGIC 0

LOGIC 1

When data bit 15, the most significant data bit (sign bit in 2’s complement representation), is low (logic 1) the DN

flip-flop will be reset when clocked. This causes the output from this flip-flop (“zero" side) to go high. The DZ
flip-fIOp is reset only when all data inputs are high (no data bits are low). The DP flip-flop is reset when both of the
above two conditions are not true. The outputs from the "zero” side of these flip-flops are brought to three input
channels of Boolean multiplexer 0 to permit these conditions to be tested using the IF instruction.
For example:

IF DN, LABEL
lF DZ, LABEL
lF DP, LABEL
If the condition tested is true (logic

1), then a jump to the specified program label is exeCuted. if the condition is

not true, the next instruction is executed.

Registers can result in a carry (overflow). it is important to keep
track of this overflow whenever arithmetic routines are written for the PDP16-M. Therefore, the following
instructions are implemented to keep track, test, and manipulate the overflow bit:
Arithmetic operations performed by the A and B

X 2

I!‘\

y to;

lF OVF, LABEL
L =OVF

4-12

Any data transfer instruction suffixed with (S) asserts the OVF gate and causes the overflow bit to be tested and
clocked into the OVF flip-flop of the bus sense and termination module. The output from this flip-flop is applied to
an

input channel of Boolean multiplexer 0 and the 1-bit LlNK Register. The IF instruction is used to determine

whether an overflow occurred. If it did, then the L

OVF instruction can be used to add the carry to the contents

of the GPA unit register.

Data Register A, B, and TR can be zeroed using the following instructions.
Destination

Source

0
0

No Source Register is evoked when these instructions are executed. However, a DATA READY signal is generated
by the ZERO gate of the bus sense and termination module to make it appear as if data was placed on the bus. Since
no Source

The following evoke data transfer instructions/commands zero the data bus.
PAGE1

l—l—l— ”I

PAGE2
HALT

FFn=i
FFn=O

OVF
0
1

LNOT

MUXO
MUX1

This

causes a

pseudo data transfer of zero because a DATA READY is issued by the ZERO gate and a DATA

ACCEPT results from asserting the BUS gate (for PAGE and HALT commands), both of which are in the bus sense
and termination module, or because a DATA ACCEPT is issued by the flag module

(FFn, L, or MUX).

Therefore, whenever any of these instructions/commands are used and the data from the previous data transfer is
needed for a decision, the data of interest in the A or B Register must be examined again. For example:
EXA
EXB

operation permits the data of interest to be tested after switching pages or multiplexers, setting or resetting
flags, or operating on the LlNK.

This

The DONE signal is generated every time a Destination

clock is then restarted to fetch and decode the next instruction.
The bus sense and termination module also generates the POWER CLEAR and the START signals. An RC network
between +5V and ground initiates the POWER CLEAR signal every time power is turned on. The START signal is

generated automatically upon power up by the power clear RC network if the jumper in the switch cable is installed
or by the front panel START switch if this jumper is not installed.

443

4.3.6

Data Transfer Timing

As emphasized throughout this chapter, every data transfer evoked causes a DATA READY, a DATA ACCEPT, and

DONE signal to be generated and placed on the control bus. The DATA READY is always generated by a Source
Register and the DATA ACCEPT is always generated by the Destination Register. in summary, Table 4-4 lists the
Source and Destination Registers and functions that are part of the basic PDP16-M.

Table 44
Basic PDP16-M Registers and Functions

Source

Destination

Registers
A

A
B

TRL

TRU

GPll

C1, C2, C3, C4

DN, DZ, DP
(Examine A or B)
Save OVF
(S)

GPl1
0 (Pseudo Source)

——

1 (Pseudo Source)

FF”
Functions

MUXn

PAGEn

A + 1
A

HALT

A + B
A X 2
A / 2
B /2

NOTA
NOTB
A OR B

AXORB

input of the source and destination modules asserts the
After both DATA READY and DATA ACCEPT are
respectively.
signals,
asserted, the result from the data test is stored in the DN, DZ, and DP flip-flops of the bus sense and termination
module, and the DONE signal is asserted to reset the Program Control Sequencer.
In all cases, the EVOKE signal wired to the evoke control

DATA READY and DATA ACCEPT

4-14

START

PULSER

RESETfi

RESET STATE

GE!

DELAY

RUN

—o>—

2
STOP

CONTINUE

‘

sgxge

:cmcx:

) MSBSY

RUN
FF

—

STAR

LIGHT

—O R

-—

CLOCK STATE

GEN

LET
—

>
-:

EVOKE
_

£5

EVOKE
FF
C

°~———<=> F

l6-0002

Figure 43 Start, Clock, and Evoke Enable Logic

4-15

INST DEC EN
MD 01

IF TRUE IGOTO

IF NOT TRUE

TEST
CONDlTlON

16-0004

Figure 4-4 Instruction Decoder

4-16

CLOCK STATE GEN

TNST DEC
EN

:I ::

RESET STATE
GEN
EXIT
IF TRUE

ZEN

1b?

CALL

2%
3%
2
4 Of;

5%
LET
6

TF NOT TRUE

ST$TE

Figure 45 State Generator

IF (TRUE WOTO

LET

I F (NOT

TRUE)

CALL

EXIT

16—0026

Figure 4-6 State Generator State Diagram

LOAD
REGISTER
TH O

STATE
GENERATOR
0'5””:
ENABLE

DECODE
AND JAM
REQSTER

LOAD

TXTREGISTER
2: "I
m1:
WTATE

‘

STATE

STATE 0

JAM STATE

NEXT
STATE

3 on 7
‘

‘

'
I
I

I
I

MRO

I
I

I
I
I

MBY

I
I

I
I
I

INSTR DEC EN

EVOKE EN

Ii—

'
I
I

:
I

DATA READY
I

EVOKE DATA
TRANSFER

,
I
'

ONLY (LET)
DATA

DONE
l6-0025

Figure 47 State Generator Timing Diagram

4-18

ADDRESS AND

MRQl TO CONTROL PROM
O4

MRO

STATE
0

PAGE 1

PAGE O
——

9 BIT

4-BIT

(PROGRAM COUNTER)

9X16 RAM

UP/DOWN

(STACK)

COUNTER

(POINTER)
WRITE

STROBE

6H7

1- MEMORY REQUEST
2- INCREMENT PC

I
I

DATA FROM

CONTROL PROM

Figure 48 Program Counter and Stack

[6—0005

—

LET Instruction

ADDRESS AND

MRQl TO CONTROL PROM
I

PAGEI

MRQ

STATE

PAGE 0
‘

9 BIT REGISTER
(PROGRAM COUNTER)

4- BIT
UP/DOWN
COUNTER

9X16 RAM

(STACK)

(POINTER)
WRITE EN

OZ'I7

I-MEMORY REQUEST
2- TEST M BIT AND INCREMENT PC
3-MEMORY REQUEST
4-LOAD PC WITH M BIT AND DATA

4
I

DATA FROM

CONTROL PROM

16~0006

_2_
STATE
5

Figure 4-9 Program Counter and Stack

-—

GOTO/ IF (true) Instruction

ADDRESS AND

r
09
PAGE1

MRQQO CONTROL PROM
O4

STATE
0

PAGE 0

INCR

9 BIT REGISTER

(PROGRAM COUNTER)

STATE

STATE
3

4-BIT
UP/DOWN
COUNTER
(POINTER)

9X16 RAM

(STACK)

WRITE EN
STROBE

DOWN

lZ'i?

1-MEMORY REQUEST
2-INCREMENT PC
3-INCREMENT PC

DATA FROM

CONTROL PROM

Figure 410 Program Counter and Stack

I6-OOO7

-—

IF (not true) Instruction

ADDRESS AND

MRQLTO CONTROL PROM

PAGEI

t MRO

STATE
0

PAGE 0

4-BIT

9 BIT REGISTER
(PROGRAM COUNTER)

9X16 RAM

UP/DOWN
COUNTER

(STACK)

(POINTER)
WRITE

DOWN

ZZ'V

I-MEMORY REQUEST
2- STACK ADDRESS
3- TEST M BIT AND INCREMENT PC
4-MEMORY REQUEST
5‘LOAD PC WITH M BIT AND DATA

I__

m-“

“7

DATA FROM

CONTROL PROM

I
I6

,3—
STATE
5

Figure 4-11 Program Counter and Stack

—

CALL Instruction

0008

ssaaoov an

60
new

{—— 8

low 01 woamoo woad
’00

£0

‘T"

1 03w

BlViS

39Vd O

.Ll8

39m

HELSIOBH

WVUSOHd) (831N003

31_vx§

3111.19

ilQ-b
NMOO/dfi
aamnoa

91X6 WVU

(MOVLS)

(UHiNIOd)
BLIHM

4-23

-l AHOWBW .LSEDOEH
GVOW-Z 3d H.L|M SSBHGGV NO MOVLS
lNEWBHDNI‘E 3d
lNBWEHDNI-b 3d

0——

I
VLVG W083

‘IOHLNO? woad

0|~3*‘—J

amfigj 3H7 weJBmd Ja1un03 pue )pels

6000—9:

—

.LIX3 uononnsu'

PAGE 0

STOP CLOCK

HALT

_
'

PAGE 1

EVOKE

EVOKE
BSo—O

ARM

EVOKE
PAGE.—I

DONE

ARM

EVOKE

CONTINUL

CONTINUE

EVOKE
BShO

EVOKE
Amid PAGEHO
EVOKE

/
EVOKE

“

_'l I

MBY

EVOKE TIMING

ARM

Mo
I

DONE

D—

c—s

MEM O
PAGE 0

>°—_‘°

an
D
G
c
9

p———————->00
:01

’8§ MEM
DATA
>

9—0
F4
O
I}

EVOVE
MO

_
‘

73'?

MEM 1
PAGE 0

:04
+05
:06
:07

PAGE

E1’

__qR

PAGE
SEL

cs
PAGE ‘

MEM 2
PAGE 1

D—
D-——

MEN 3
PAGE I

cs
MAOB

M000
1

9——

BIT

IF(TRUE)

E.
,

GOTO
C

CALL
I

06 04 02

o7 05 03
MEM

ADDR
l6-0010

Figure 4—13 Memory and Page Select Logic

MUX 1

CONDITIONS
0

CONDITIONS

18
DATA
SEL

I
:

‘

;

DATA

SEL

M001
M002
M003

TEST

EVOKE

M004

M005
O

DATA
SEL

2
I

DATA
SEL

‘8

:
I
:

I:
2

I
29

IFINSTl7[615I4F[2l1TCj
ABBJEEA
Iuho

yunm

—‘

MUX O

M BIT

16-0012

Figure 4-14 Boolean Multiplexers
EVOKES
o

M000

0
0

M001

1
2

M002

4 T016
DECODER

M003

;

M004

15
9—.

I‘;
°—':
18

L""""'.
DECODER
I
4 T016

EVOKE EN

LDC,—

3'1

0————.

M005

I
M006

ADDRESS CODE
A02 A01
ADO

M07

DATA
M06

M05

DECODER

DATAB

000—-037

040—077

100—137

140—177

200—237

240—277

ID—

M007

ADO
.

if"
-_-__:AD1
=

«v.

+5V
16—0011

A02

Figure 415 Evoke Decoder

4—25

FIXED
DELAY

“A

DATA READY

To BOOLEAN
MUX

DATA
BUS

LINK

5/2

RIGHT SHIFT LOGIC
”'33
AND DRIVERS

D—<DVF>

EVOKE
SOURCE

cp—
OPERATION

Egg

ENCODER
3‘

CARRY
'N

32
$3

CARRY
OUT

EVOKE
DEST

DATA

L55

ALU

0V F
MSB

EVOKE
BEST

B REGISTER

I___'__]
TO BOOLEAN MUX
DATA BUS

Iii—0013

Figure 4—1 6 GPA Registers and Control

DATA
READY

EVOKE

SOURCE

MRU

READ

EVOKE

BEST

TRU:

LDU

LOAD

{>0

TRU

DRIVERS

'_I

DATA

EVOKE
BEST

TIES
TRUA

L9‘-

LOAD
fl

TRL

SOURCE

DRIVERS

(T—

3-4}
EVOKE

BUS

READ

A' L
ATR
we
FIXED
DELAY

Figure 4—17 Transfer Register

4-26

DATA

00A—

O1;

DATA

BUS
C
O
O
O
O
O

o—v
1

FB c1
=

u=CZ

)0
FIXED

EVOKE_

DELAY

SOURCE;

DATA
READY
’

[6—0007

L
Figure 448 4-Word Constant Generator

4-27

RECEIVERS

EVOKE
SOURCE

DATA READY
B=GPH

{6PM

DATA READY

DATA ACC EPT

EVOKE
DEST

F DATA OUTPUT

DATA ACCEPT
=

8
16-002!

Figure 449 General Purpose Interface

4-28

ON
ON

DZ
DZ

()
BUS- 03

(SEE NOTE)
DP

<OVF_>

OVFD

EVOKE DEST

EX
EVOKE DEST

VQI‘L‘
bk.

uvul

%ZER0 \,

DATA ACCEPT

FIXED
DELAY

b
o

CAI

L__/

é:

NOTE:
Each data input line is terminated with
(See schematic D-CS- M7332)

START
SWITCH

load

and

current

source.

‘

°_q

DATA

“

DONEA

ACCEPT
H -—1

+5V

} l:

SS
RUN

AUTO RUN
0‘
AHZ

POWER CLEAR

“LIA—s1

E72
5

AU1

SWITCH CABLE
D01
16-0015

Figure 4—20 Bus Sense and Termination Module

BUS

GATE DATA TO BUS

SOURCE MODULE
EVOKE

EVOKE

DECODER
GATE DATA FROM BUS

a;
DESTINATION MODULE

EVOKE EN

BUS SENSE AND TERM

PROGRAM CONTROL SEQUENCER

lS'OOlG

Figure 4-21 Data Transfer Timing Logic

4-30

CHAPTER 5
MAINTENANCE

5.1

PREPARATION FOR MAINTENANCE

The maintenance philosophy for the PDP16-M is to isolate the defective module by selective substitution in response
to diagnostic program results.

5.1.1

Equipment Required

The following equipment is required to perform preventive and corrective maintenance on the PDP16-M.
a.

PDP16—M Field Service Repair Kit (Table 5-1)

Osciiioscope

Multimeter, Radio Shack J22846 or equivalent

Scope probes

Vacuum Cleaner

1‘.

Nonflammable solvent

Clean soft cloth

Tektronix type 453 or equivalent

Table 5-1
PDP16-M Field Service Repair Kit

Purpose
Maintenance Module
Maintenance Module

Description

Quantity

Part No.

Service Module KSM16

M7335

Option Switch Module KSL16

M7334
M7322

Maintenance Module

Bus Monitor KBM16

Maintenance Module

Interface Jumper Module

W971

Module

KAC16 GPA CONT

M7300

KAR16 GPA REG

M7301

M31 6-A TR

M7305
M7306

Module
Module
Module

KFL16 FF4—6

Module

AND Gates

M1307

Module

AND Gates

M1103

5-1

Table 5-1 (Cont)
PDP16-M Field Service Repair Kit

Purpose

Description

Quantity

Part No.

Module

KEV16 EVOKE

M7310

Module

DB16-A GPl

M7311

Module

DCS16-A

M7313

Module

M316-C SP

M7318

Module

MS16-D MEM

M7319

Module

MR16-D K

M7325

Module

PCS16-C EVOKE DEC

M7328

Module

PCS16-D MUX1

M7329

Module

KBS16~A BS

M7332

Module

PCS16-E PCS

M7336

Diagnostic ROM

PCS16—B DIAG PROMO

M7327 YA

Diagnostic ROM

PCS16-B DIAG PROM1

M7327 YB

Diagnostic ROM

PCS16—B DIAG PROM2

M7327 YC

Diagnostic ROM

PCS16-B DIAG PROM3

M7327 YD

W984

Miscellaneous Parts
Extender Module

Mate-N-Lok Jumper Plugs

Extender Cables

7007222

Edge Connector
Diagnostic Listings

H851

5.1.2

Maintenance Modules

Three

special modules (options)

have been

——

modules are:

Bus Monitor Module, M7322 (KBM16)

Service Module, M7335 (KSM16)

Option Switch Module, M7334 (KSL16)

(Figures 5-1 and 5—2), which plugs into slot A01 via
7007222, shows the operator what is on the 16-bit data bus and also if timing signals DA (DATA
ACCEPT) and DR (DATA READY) are present. At power-on time, the DATA READY and DATA ACCEPT lights
(LEDs) should be lit. No lights on the data bus should be lit. When the basic diagnostic is running correctly, the data
5.1.2.1

Bus Monitor Module M7332—The bus monitor

extender cable

bus lights will exhibit a down counter. Spare 1 and spare 2

lights represent the overflow and Link bits respectively

under certain program conditions. When operating the PDP16—M under single step control, visual inspection of the

LlNK, OVERFLOW, DATA ACCEPT, and DATA READY signals is possible; the content of the bus can also be
visually inspected.

5-2

<OVF>

BUS MONITOR
D ATA

LINK

DRDALOVF'012

9101112131415

OOOOOOOOOOOOOOOOOOOO

11
BUS
SENSE
AND
TERM

A
DATA

DATA

READY:
ACCEPT
7

DONE
_

O
OVERFLOW

POWER

CLEAR
‘

DATA BITS

IG-OOGS

Bus Monitor Module M7322, Application Diagram

Figure 5-1

LL01234567891011|2131415|
|

OVERFLOW

DATA

BUS

LINK
DATA

DATA

READY

Figure 5-2 Bus Monitor Module M7322

5.1.2.2

Service Module M7335

—

The service module plugs into slot 801 via extender cable 7007222. The M7335

Register and a 12-bit Address Register. Bits 10 and 11 of the
Register are not used; bit 9 of the Address Register is the page bit. When lit, PAGEl is selected and the
Opposite is true for PAGEO. Bits 0 through 8 contain the address; bits 0 through 7 of the Data Register contain the
numerical code of the instruction being performed. There are 12 address switches labeled A0 through All on the
module (Figures 5-3 and 5-4) contains an 8-bit Data

Address

module, and these switches correspond to the address bit of the same number. Hence Witch 0 and bit 0 both
represent address bit 0. A switch labeled Break Point (BP) is used in conjunction with the address switches. All
switches are asserted to a 1 when the white dot on the switch is visible. The pushbutton step switch is used when the
switch labeled Single Instruction (SI) is asserted.

MRQ
MBY

9:
PROGRAM
CONTROL

CONTROL
PROM

SEQUENCER

CONTROL

ADDRESS
»

STOP
CW

000

A11

A10

000

CONTROL

GED
STEP

000

COMPARATOR

iiiiiiiiiiii
BUD DUB EDD DUB
All

A10

A0
l6-0065

Figure 53 Service Module M7335, Application Diagram
Using the Step and SI Switches
First turn on power to the PDP16-M. Assert the SI switch and push the START key to generate a start pulse. By
pushing the step button, the PDP16-M will single step through the diagnostic program, displaying the data bus on the
M7322. The lights on the M7335 module display the address and the data instruction contained in that address along
with the memory page. This is not an examine function and does not check the diagnostic sequencially. It does step
through the diagnostic in the manner that the program runs. By de-asserting the SI switch and pushing the START
key or the step button, the program will return to auto run.

Using the BP and Address Switches
The BP and address switches

are

used to halt the diagnostic at a particular address without

the program to that point. By

the BP

having to single step

switch, placing the desired stop address in the switches,

through
asserting
setting page switch to the page desired, turning power on, and pushing the START key the PDP16-M will auto run
until reaching the break point; it then halts. For example, assume the diagnostic failed at PAGE1 address 221
(1221). Using the break point feature, the program could be stopped at address 214 of PAGEl (1214) and the single
step feature could then be employed. This avoids having to single step through the entire diagnostic. To use the
break point function, the address selected has to contain an instruction being performed by the program. Locations
that contain jump addresses or HALT commands should not be used as break points. The break point halt will occur
before the instruction is executed. Refer to the diagnostics listing to select an appropriate break point address.

CONTROL ROM
ADDRESS INDICATORS

CONTROL ROM
DATA
PAGE

'07 as

04 03

02 01

Do1

A»;

(SINGLE (BREAKPOINT)
INSTRUCTION)

A7 A6

m”

A7 A6

A4 A3

A0'

A6 A4

PAGE
ADDRESS

SWITCHES

Figure 54 Service Module M7335

5.1.2.3

Option Switch Module M7334

——

To run the option diagnostic, steps 5 through 7 of Paragraph 5.1.4 must

be completed and the basic diagnostic must have run without error. The M7334 module (Figures 5-5 and 5—6) has a

Register and 16 switches. Each switch identifies a particular option to the diagnostic program. In only
application is more than one switch used at a time. To test an option, find the desired switch setting in Table 5-2
and assert the switch to a 1 (white dot showing). In situations where data is to be examined, the Data Register will
16-bit Data

one

contain the data read.

The diagnostics have been written to test for correct data and to identify and isolate inoperative register bits. For

instance, a register is loaded with a particular bit pattern, read back, and tested to determine if the data is the same.
If it is not, the program will illuminate the Data

diagnostics is helpful in troubleshooting modules.
Set the desired switch setting, turn power on, and run the diagnostic single step or auto, using the instructions in
Table 5-2.

5.1.3

Maintenance Programs

The MAINDEC

designated

diagnostics required

for

this procedure have been preloaded into the M7327 PROMs and are

M7327 YA to YD. These modules are included in the repair kit listed in Table 5-1. The M7327 YA and

M7327 YB modules, which plug into slots C16 and D16, respectively, are PAGEO or the option diagnostic. Slots 017
and D17 house the M7327 YC and YD modules, respectively. These modules contain the basic diagnostic or PAGE1.

The diagnostic listings are also included in the repair kit listed in Table 51.

Q 0
GPI1=B

BIT

BIT
1

GPI1=A
.

GOO

OPTlON

GOO

COCO)

SWITCH MODULE

A=6PI1

BUS
SENSE

UDE EDU DUI] EDD DUE
51g

TERM

tag
O

DATA READY

DATA ACCEPT

DONE

OVERFLOW

POWER CLEAR

1e DATA BIT

|6-0064

Figure 5-5 Option Switch Module M7334, Application Diagram

NOT

DATA BUS

USED

Ins

14131211109

876

115

14131211109

543

210I

I
NOT USED

OPTION

SWITCHES

Figure 5-6 Option Switch Module M7334

5-6

Table 5-2

Option Diagnostic Key
Switch

Option

DB16-A

Slot No.

A813

Module

Run

Symptoms of

Option Test

Tested

Mode

Correct Operations

Times

M7311

Single
Step &

watch the bus moni-

Auto

tor up count the data

Using single step,

10 min.

bus to a count of 108.

Put into auto run and
watch up count. Runs
until error or power

down.
DB16-A

A814

GPI3
M7311

Single
Step &

Same as switch 0. Up

10 min.

count starts at 28.

Auto

2&15

DB16-A

A815

DATA

C/D15

PROM

RUN light OFF. Proper

If customer

data displayed in the

PROM, check

M7311

light Switch Register

all locations.

M7327

Single
Step

M7334 Control

Module.

134701

152303

161375
011707
007301
133762
005377
007746
147420
005750
134420
152352

161020
000457
054346
000021
055671

002456
MR16-D

AB8

CONSTANT
GEN

Single
Step

M7325

RUN light OFF and

177773 displayed in
the light Switch Register (M7334).

5-7

15 min.

Table 5-2 (Cont)

Option Diagnostic Key
Switch

Option

MS16-D

Slot No.

Module

Run

Symptoms of

Option Test

Tested

Mode

Correct Operations

Times

MEM1

Auto

M7319

RUN light ON. Bus

30 min.

monitor lights all on
and flickering.

MS16-E

MEM2

Auto

M7324
MS16-C

SP1—16

RUN light ON. Same

Auto

M7318

RUN light ON. Shows
an

30 min.

as switch

20 min.

up count in the bus

monitor.

MS16-C

SP17—32

Auto

DC16-A

A16

3”

Auto

M7313

Same as switch 6.

20 min.

RUN light OFF and

25 times

OCTAL 400 is displayed
in the light Switch Register (M7334), after the

program HLTS in LOC

0313. Test shows an up
count to 4008 in the bus

monitor lights.

DC16-A

A17

SI 2

Auto

Same as switch 8.

25 times

RUN light ON and bits

10 min.

M7313

KFL16

FF4—6

Auto

4 and 5 are ON in the

M7306

bus monitor. 177777

displayed in Switch
Register and lights on
M7334.

Not used.

DA16-F

D14

PDP-11 lNT
M623

RUN light is ON and

Single
Step &

data lights in the bus

Auto

monitor are ON. Single

step until the data bus
seems to

—

complement.

Not used.

Used with switch 2.

5-8

10 min.

5.1.4

Maintenance Setup
1.

Remove the customers PCS16-B, M7327 memory PROM or PROMs and replace with the four diagnostic
M7327 YA

——

YD memory PROMS. Place M7327 YA in slot C16, M7327 YB in slot D16, M7327 YC in

slot C17, and M7327 YD in slot D17 (Figure 5-7). Slots D16 and D17 contain the basic diagnostic and
slots C16 and C17 contain the option diagnostic.

l/O-3

SLOT

l/O-Z

SLOT

PCS

l/O-1

SLOT

MUX

I/O SLOT

MUX1

ADAPT M7333*

AND

M1307

MUXO

M7336

M7329

S|2

M7313

$11

M7313

DAT PROM INT M7311

GPI3

M7311

GPIZ

M7311

DAT PROMI M7327

DAT

POP-11 INT M623

AND M1307

M1307

AND M1307

AND

M1307

AND

M1307

GPA

CONT

AND M1307

AND

M1307

GPA

REG M7301

M7305

AND

M1103

PROMZ M7327

M7329

13
12

L,PAGE,MUX M7306

M7300

(A83)

10
9

EVOKE

DEC 5

EVOKE

DEC

4 M7328

MEM2

M7319/M7324

EVOKE

DEC

3 M7328

MEM1

M7319/M7324

EVOKE

DEC

M7328

M7325

M7307

EVOKE

DEC

M7328

SP1-16

EVOKE

DEC

M7328

SP17—32

FF4 -6

M7306

9(- =OPTION

FF1-3

M7306

EVOKE

M7310

M7318

BUS SENSE AND TERM

M7332

MAINTENANCE

A
‘6'0028

SLOT

Figure 5-7 Logic Assembly Maintenance Configuration Diagram

Insert input/output jumper modules No. 1 and No.2 (W971) in slots CD19 and CD20, respectively, and
connect Mate-N-Lok serial

l/O jumper plugs on module M7333 located in slot D18.
NOTE

The

jumper wires
Mate-N-Lok plugs before they can
Appendix B for details.

user

must

install

these modules and

installed.

Refer

Insert two 7007222 cables, one in slot A01 and one in B01.
Insert M7322 Bus Monitor into the cable from slot A01. Insert M7335 Service Module into the cable
from slot B01. The M7335 is a double-width module and the cable is inserted over the A section of the

output/input “Gold Fingers."
NOTE
The basic diagnostic is

now

ready to run. Press the START

switch and allow the basic diagnostic to run for 10 minutes.

run the option portion of the diagnostic, remove the M7311 from slot AB12 and insert the M7334
Option Switch Module on a double extender module (W984).

NOTE
The basic and Option diagnostics will not run at the same time.

Remove the M7327 YC and YD modules from slots C17 and D17 and place in slots C15 and D15.
Run the

appropriate option test following the switch setting and times specified in Table 5-2 and the

maintenance procedure on the M7334 in Paragraph 5.1.2.3.

5.2

PREVENTIVE MAINTENANCE

consists of procedures performed prior to the initial operation of the computer and
periodically during its operating life. These procedures include visual inspections, cleaning, mechanical checks, and
operational testing. A log should be kept for recording specific data that indicates the performance history and rate
of deterioration; such a record can be used to determine the need and time for performing corrective maintenance
Preventive maintenance

the system.

Scheduling of computer usage should always include specific time intervals set aside for scheduled maintenance
purposes. Careful diagnostic testing programs can then reveal problems which may only occur intermittently during
on-line operation (Paragraph 5.1).
Digital Equipment Corporation suggests the schedule defined in Table 5-3.

5.3

5.3.1

CORRECTIVE MAINTENANCE

Repair Procedure

Always follow the Repair Procedure Flow Diagram in Figure 5-8. Strict adherence to this flow will ensure the most
efficient use of your time (Paragraph 5.1). For this procedure, the basic diagnostic errors have been divided into two
sections: control and data.

Data error: A data error occurs when the diagnostic halts at a legal location

having a data code of 271

(H LT). The RUN light will be off. By checking the 8-bit data lights on the M7335 (for a 271) and the
address location in the diagnostic

listing, a data error can be suspected. For these type failures, swap the

modules as described in Paragraph 5.3.2.1.

Control

error: A control error is to be assumed if the PDP16-M halts or the program hangs up at any
location except a legal halt. if this is the case, swap the modules as described in Paragraph 5.3.2.2.

The M7307 4-word Constant Generator (C) is tested for proper timing circuitry only when the basic diagnostic is in
auto run. To examine the 4

words, check the jumpers to see what they are cut for. Using the break point function,

halt the program at location 1242. Single step the program and visually check the data on the M7322 Bus Monitor
data bus.

5-10

Table 5-3
Preventive Maintenance Schedule

(3 months or 500 hours)

Type

Action

Cleaning

Clean the exterior and interior of the computer cabinet, using a vacuum cleaner and/or
clean cloths moistened in nonflammable solvent.

Clean the air filter. Use

vacuum

cleaner to

remove

accumulated dirt and dust, or

wash with clean hot water and thoroughly dry before using.

Lubricate

Lubricate slide mechanisms and casters with a light machine oil or powdered graphite.

Wipe off excess oil.
Inspect

Visually inspect equipment for general condition. Repaint any scratched areas.
Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks,
strains, and mechanical security. Tape, solder, or replace any defective wiring or cable

covering.
Inspect the following for mechanical security: key switch,
transformers, fans, capacitors, etc. Tighten or replace as required.

lamps,

connectors,

Inspect all module mounting panels; be sure that each module is securely seated in its
connector. Remove and clean any module that may have collected excess dirt or dust.

InSpect power supply components for leaky capacitors, over-heated resistors,
Replace any defective components.
Check the output of the H740 Power

etc.

Supply as specified in Paragraph 5.3.1. Use a

multimeter to make these measurements without disconnecting the load. If any output

voltage

is not within tolerance, the

supply

is considered

defective, and corrective

maintenance should be performed.
Perform

Run all

relevant

diagnostic

programs to

verify proper computer operation. Each

program should run for the time specified in Paragraph 5.1.4.

Enter preventive maintenance results in the log book.

MAINT SETUP

(PARA 5.1.4)

TURN ON

RUN USERS
PROGRAM IF
POSSIBLE

POWER

CHECK

INDISGTOR

VOLTAGES
(PARA 5.3.1)

YES

NO
END

YES

RUN BASIC
DIAGNOSTIC

INSERT CONTROL
PROMS IN SLOTS
0/0 15

CHANGE
MODULES
(PARA 5.3.2.1)

RUN DATA PROM

DIAGNOSTICS
(OPTION SWITCH
2 AND 15)
SEE PARA 5.1.4

CHANGE
MODULES
(PARA 5.3.2.1)

CONTROL
ERROR

CHECK DATA IN ALL
LOCATIONS AGAINST
SOURCE LISTING

TESTEN CONZSEAINT
M

GENERATE NEw
SOURCE TAPE
AND REPROGRAM
PROM

(PARA 5.3.1)

YES

REPLACE
MODULE AND
RECUT
CONSTANTS

NO
SETUP
AND
OPTION

RUN

DIAGNOSTIC
PARA 5.1.4

YES

CHANGE OPTION
MODULE AND
RERUN DIAG

FAILED

16- 0022

Figure 5-8 Repair Procedure Flow Diagram

5-12

When power

supply problems are suspected, the H740 Power Supply can be checked by referring to Table 5-4.

Controls and fuses are identified in Figure 5-9.
Table 5-4

DC Voltages

Voltages (dc)

Wire Color

Red

+4.8 to +5.2 Vdc

Blue

—14.5 to-15.5 Vdc

Black

GND

Orange
Gray

+1 .0V to +2.0V

+2.8V to +5.5V

Maintenance of the data control bus may be required if the basic philosophy of the module swapping does not fix
the problem. The bus must then be checked for broken, nicked, or burnt wires, broken or bad pins, loose wirewraps,
and for any obstructions in the bus slots or pins. If the bus is to be checked, first turn off power and unplug the ac

cord. Remove the four

screws

under the chassis that hold the bus in

place. Lift the bus out, being careful not to

bend any logic pins. The power harness is long enough to enable the bus to remain hooked up for dc power.

:3
+5 AND+15V
F1 (15 AMP)

O¢——-————+15v

R35

®————+5v

R50

g]
-15V

F2 (5A)

®<—————15v R26

l:l

ll-lOOS

Figure 5-9 H740 Power Supply Fuses and Adjustment Controls

5.3.2

5.3.2.1

Module Swapping Priorities
Data

Error- For

suspected

data error, swap the modules

adherence to this list will ensure the most efficient use of your time.

Module

Slot No.

M7336

A820

M7332

A802

M7300

A811

M7301

A810

M7311

A812

M7305

A809

M7307

A805

M7306

C09

M7306

002

5-13

listed in the exact order written. Strict

Swap modules listed in Paragraph 5.3.2.2 before swapping the modules below.

5.3.2.2

M1307

C10 to C14,C18,D10,Dl3

M1103

Control Error

—

For

suspected control error, swap the modules listed in the exact order written. Strict

adherence to this list will ensure the most efficient use of your time.

Module

Slot No.

M7336

AB20

M7332

AB02

M7328

CD03

M7328

CD04

M7328

CD05

M7328

CD08

M7306

C09

M7310

CO1

M7329

AB18

M1307

D13

M1307

C18

M1307

C14

5-14

APPENDIX A

HARDWARE OPTION DESCRIPTIONS

All memory (control and data) and Ho options that are offered for the PDP16-M are discussed in this appendix.
Each option is covered in a separate description. The descriptions include details on operation, installation, and
programming. The options covered are:

DA16-F

PDP-11 Peripheral Interface (M623)

DBIG«A

Parallel l/O (M7311)

DC16-A

Serial l/O (M7313)

KFL16

Boolean Outputs/Flags (M7306)

M R 1 6-D

Constant Generator (M7325)

M R16-E/F

Data PROM (M7327)

MSIB-C

Scratch Pad Register (M7318)

MSlB-D

Data R/W MOS Memory (M7319)

M81 6—E

Data R/W MOS Memory (M7324)

PCSI 6—B

Control PROM (M7327)

PCSI 6—D

Boolean Input Multiplexer (M7329)

Maintenance procedures including details on diagnostic tests for the options are presented in Chapter 5.

A-l

DA16-F
PERIPHERAL INTERFACE OPTION

(M623)

The PDP16-M has been prewired to interface with PDP-ll peripheral devices that do not need to become master
devices. Only accumulator-type transfers can transpire between the PDP16-M and PDP-ll peripherals. One prewired
module slot, slot

D14, is reserved on the logic assembly for installing the DA16-F option (module M623). This

module contains AND gate bus drivers that interface with the data transfer interlock control signals of the PDP16~M
and the PDP-11 device

connecting

(Figure 1). In addition to the M623 module, the following items are also required when

PDP-ll device to a PDP16-M:

One H803 Connector Block

Three BCO2X-05 or three BCOBH-05 cables

.One KTM16 Bus terminator option (M962)
NOTE
A BC11A cable

(preferably BC11A-02) is also required. This

cable is supplied with the PDP-1‘1 peripheral device.

signals, the address, and the data required for operating a PDP-11 peripheral are distributed between
logic assembly. Therefore, three cables are necessary.'Since the pin assignments for the
various signals on the PDP16-M l/O slots do not match those of the PDP-ll device input slot, an H803 Connector
Block is employed to match the signals through wire wrapping. In addition, the H803 Connector Block is used to
provide ground and +3V to certain PDP-ll device input lines. Figure 2 and Table 1 detail the pins on the connector
block to be wire wrapped.

The control

three slots on the PDP16—M

PDP16M

EXTERNAL EQUIPMENT

l
r

BCOZX

{/F

DATA

BCOZH

READY

MSYN Ta

MSYN
DATO (EVOKE

M623

SOURCE)

BUS=A

DATA ACCEPT

Mux

DATI(EVOKE

M623

DEST)

—“—‘—‘_‘—‘

AND FF

SLOT
302

1/213LOT

g
(1;

A: BUS

!-«Fig.

BC11A
CABLE

C‘

flig_

CABLE

“1.0
*‘

’E_

353:

e
R

acozx OR BCOSH

DATA BUS

ADDR<OO-15>

H380
CONNECTOR

(”0705 ”
SLoT

CABLE
e
GPI‘l: B

BCOZX OR BCOEH

DATA BUS

SLOTS

¢—————————

DATA<OO-15>
A

Aai—ABiT

SLOT
A01

CABLE
C
NOTES
l

Connector
’

block must be

wiiewropped lmerconnection details are shown ln Table 1
be: use

the do a b is,

connector block Do not lermmoie The bus at the

Peripheral

j‘b e usl

35 shc H
s Dossb e

8 m-noled:
”he

SLOT
A303

I
KMT16
BUS

TERMINATOR

Figure 1 PDP-11 Peripheral Interface Option DA16-F, Block Diagram
DA16-F (1)

Q
U
(NOTE 2)

PDP-n

PERiPHERAL
DEVICE

After the H803 Connector Block is wire wrapped, the cables can be installed as shown in Figure 1. The KTM16
option must be installed in slot A03 of H803 to terminate the data bus.
The instructions that evoke data transfers between the PDP16-M and the PDP-11

peripheral devices are decoded by
(Paragraph 4.2.4). No additional evoke decoders are required. Besides
the instructions expressly implemented for transferring data to or from the peripheral, some standard instructions
are also used in programming the data transfers because of the manner in which the device is interfaced with the
PDP16-M. That is, FF1 is used as a flag to denote the direction (input or output) of the data transfer, and GP|1 is
the standard evoke decoders of the PDP16-M

used to transfer the device address.

21
121
21
2
0A.
0A0
0A0
0A.
0130
cc.

on.
01-20
OF.
OH.

OJ.
A

OK.
01..
OM.

ON.
OP.
OR.

as.
OT.
0U.

0130

CC.

0130
CC.

000

OE.

one
GE.

0F.

OH.

OF.
OH.

OJ.
OK.

.1.
OK.

CL.
OM.

ON.
0P0

ON.
OP.

OR.

as.

OR.

as.

or.

ouo

OT.

ouo

0130

QC.
on.

CEO
OF.

OH.
OJ.
OK.
CL.

OM.
ON.
0p.
OR.

05.
or.

ouo

ovo
ovo
ovo
ovo
121
2121
2

121
21
21
2
CA.
CA.
0A.
0A.

0130
CC.
000
OE.

OF.
OH.

0J0
5

OK.

01..
OM.

0110
OP.

OR.
as.
or.

0U.
ovo

ca.

CC.
000

OE.

0130
GE.

01:.

OH.

or.
OH.

DJ.
OK.

0.10
ox.

CL.

OM.

01..
OM.

on.
OP.

ON.
OP.

OR.

as.

OR.

.50

CT.

ouo

CT.

ouo

ovo

121

0130
oco

ovo

0130

QC.
one

CEO
01:.

OH.

0110
OK.
01..

OM.

ON.
OP.
OR.

as.
CT.

ouo
ovo

2121

2
16-0069

Figure 2 H803 Connector Block, Pin Assignments

DA16-F (2)

The machine code (octal), execution time, and description of all instructions relevant to programming data transfers
between the PDP16-M and the PDP-II

peripheral device follow:
SEND DATA TO DEVICE

Evoke

Time

(Octal Code)

(psec)

Instruction

Description

057

1.8

FF1

040

2.2

GPI1

Send address to device from A Register.

255

2.2

GP|1

Send address to device from B Register.

275

Prepare input section of device.

DATO

Send data from A Register to device.

READ DATA FROM DEVICE
Evoke

Time

(Octal Code)

(,usec)

Instruction

056

1.8

FF1

040

2.2

GPI1

255

2.2

GPII

274

—

A summary of PDP 11

Appendix A of the

Description

Prepare output section of device.
Send address from A Register to device.

Send address from B Register to device.

DATI

low-speed peripheral

device

Read device data into A Register.

addresses,

status

registers,

and control

registers is given in

P16-M User’s Guide. When addressing a PDP-11 device, the complement of the given address

must be used because the address lines are driven with TTL levels from GPII rather than open-coiiector drivers.

NOTE
A

new

PDP-1 1

Peripheral

Interface

option,

Unibus

converter/l/O Interface Module, will be available in the future.
This option will simplify the interfacing procedure.

Table 1

H803 Connector Block Wire-Wrap Connections
PDP16—M

From

PDP-11

Signal

Name

+5V

GND
GN D

*A01 A2
*AO1 C2
*A01 T1

AO4A2

BO4A2

+5V

A04C2

A04T1

GND

A04T1

BO4C2

G ND

BO4C2

BO4T1

GND

+5V

*BO1 A2

BO4A2

+5V

GND

*BO1C2
*BO1T1

80402

GND

BO4T1

GND

+5V

A01 A2

803A2

+5V

BO3A2

+5V

BO3C2

G ND

BO3C2

GND

BO3T1

GND

BO3T1

GND

+5V

801 A2

GND

A01 C2

GND

BO1C2

GND

A01T1

GND

BO1T1

A03A2

A03C2

A03T1

DA16-F (3)

Table 1

(Cont)

H803 Connector Block Wire-Wrap Connections
PDP16—M

From

PDP-11

Signal

Name

D00

DATA BIT 00

A01A1

A03A1

AO4C1

DATA BIT 01

A0181

A0381

A04D2

D01

DATA BIT 02

A01C1

A03C1

A04D1

D02

DATA BIT 03

A01 D1

A03D1

A04E2

D03

DATA BIT 04

A01 E1

A03E1

A04E1

D04

DATA BIT 05

A01 F1

A03F1

A04F2

D05

DATA BIT 06

A01 H1

A03H1

A04F1

D06

DATA BIT 07

A01J1

A03J1

A04H2

DO7

DATA BIT 08

AO1K1

A03K1

A04H1

D08

DATA BIT 09

A01 L1

A03L1

A04J2

D09

DATA BIT 10

A01M1

A03M1

A04J1

D10

DATA BIT 11

A01N1

A03N1

A04K2

D11

DATA BIT 12

A01P1

A03P1

A04K1

D12

DATA BIT 13

A01 R1

A03R1

A04L2

D13

DATA BIT 14

A0181

A0381

A04L1

D14

DATA BIT 15

A01U1

A03U1

A04M2

D15

+3V

BO3A1

BO4F1

AC LO

+3V

80381

BO4P2

DCLO

A00

D00

80182

BO4H2

DO1

801 D2

BO4H1

A01

DO2

801 E2

BO4J2

A02

DOB

801 F2

804J1

A03

D04

801 H2

804K2

A04

D05

BO1J2

804K1

A05

D06

801 K2

BO4L2

A06

D07

801 L2

BO4L1

A07

D08

801 M2

BO4M2

A08

D09

801 N2

BO4M1

A09

D10

BO1P2

BO4N2

A10

801 R2

BO4N1

A11

D12

80182

BO4P2

A12

013

BO1T2

BO4P1

A13

D14

BO1U2

80482

A14

D15

BO1V2

80481

A15

GND

BO4T1

80482

A16

GND

80481

A17

+3V

B03C1

BO4U2

MSYN

BO2K2

BO3D1

BO3DI

BO4V1

MSYN

SSYN

802V2

BO3E1

803E1

BO4U1

SSYN

F F1

BOZNZ

804T2

C1.

GND

802T1

BO4T1

GND

Use 933 Bus Strips for these connections (power and ground). For all other connections, use 24 AWG bus wire.

DA16-F (4)

DB16-A
PARALLEL l/O

OPTION (M7311)

l/O channel (GPI1) is included in the basic PDP16-M. Two additional channels can be added by
implementing one DB16—A option (module M7311) for each channel. Two prewired module slots are reserved on the

One parallel
PDP16-M

logic assembly for installing the M7311 l/O modules. Both slots are wired directly to the PDP16-M register

transfer bus. The module slots are also wired to l/O slots on the logic assembly to facilitate convenient interfacing to

implement either l/O channel, it is necessary only to install the option module in one of the
or set-up procedure is required except to connect the external equipment to the
assigned
slot.
Refer
to
I/O
Chapter 2 of the PDP16-M User’s Guide for interfacing details.
interfacing
external equipment. To

slots. No other wiring

RECEIVERS

—

DATA OUTPUT

DATA BUS

DRIVERS

D AT A

R EAD Y

DATA

INPUT

READY

DATA ACCEPT
DATA ACCEPT

1670066

n=2 0R3

Figure 1 Parallel l/O Option DB16—A, Block Diagram

The M7311 l/O module contains 16 bus receivers and drivers, 3 16-bit data output register, and evoke logic (Figure

1). The module is identical to the one used for the standard I/O channel in the basic PDP16-M. The register outputs
and receiver inputs (bus drivers) are TTL levels. Each output bit of the register can drive up to 10 unit loads (16 mA)

input must be driven with at least 1 unit load (1.6 mA). The two prewired l/O module slots are
assigned a different mnemonic for programming reasons. The mnemonics are: GPl2 for slot A813 and GP|3

and each receiver

each

DB16-A(1)

for slot ABI4. The instructions that evoke data transfers between the PDP16-M and the external equipment via the

parallel I/O channels are decoded by the standard evoke decoders of the PDPIG-M (Paragraph 4.2.4). No additional
evoke decoders are required. The machine code (octal), execution time, and description of each instruction follows:

CHANNEL NO. 2 (GPIZ)
Evoke

Time

(Octal Code)

(usec)

042
043

Instruction

2.2

GPI2

2.0

GPI2

Description

GPI2 gets A (Data Out)
A gets GPI2 (Data In)

CHANNEL N0. 3 (GPI3)
Evoke

Time

(Octal Code)

(usec)

044
045

Notice that the B

Instruction

2.2

GPI3

2.0

GPI3

Description

GPI3 gets A (Data Out)
A gets GPI3 (Data In)

Register cannot be used in programming data transfers via the optional parallel I/O channels.
Registers can be used in programming data transfers via the standard parallel I/O channel

However, both A and B

(GPII) (Paragraph 4.3.4).

Output data is preserved (buffered) in the output data register until another output data transfer is executed. Input
data, however, is not buffered and can therefore change at any time.
Input and output data may or may not be structured, depending on the application. If data is to be transferred
sequentially to or from the external equipment, it may be necessary to synchronize the transfers to accommodate
the operating speed of the external equipment. The
FFn output, the EXTn input, or one or more I/O data bits can
be employed as flags for synchronizing the data transfers.
It is for this reason that the FFl—3 outputs are wired to the respective parallel l/O interface slots. The state of the

FFn outputs, the EXTn inputs, and the odd data bits (A Register contents) can be tested using the IF instruction to
facilitate their use in synchronizing data transfers.
For example:
IF FF2, LABEL1
IF FF3, LABEL2
IF EXTI, LABEL3
IF A<1>, LABEL4

IF A<3>, LABEL 5
The PCSIS-D multiplexer

Option

must

implemented if it becomes necessary to test the even bits of the A

DBIB-A (2)

DC16-A
SERIAL I/O OPTION (M7313)

Two serial l/O channels can be implemented in a PDP16-M. Both channels require interface adapter DC16-B (M7333

module) to provide character format selection and TTY current loop connections. Three prewired module slots are
on the PDP16—M logic assembly for implementing the serial l/O channels: two are reserved for the M7313

reserved

I/O Modules and one is reserved for the M7333 Interface Adapter Module. The two slots for the M7313 modules are
wired directly to the PDP16-M register transfer bus.

FUNCTIONAL DESCRIPTION
The M7313 l/O module (Figure 1) contains one LSI chip, designated the UART, and some control logic to interface

Register Transfer bus (and ASR 33 paper tape reader if used). The module also contains signal
converters for handling TTL and TTY compatible serial data signals Of the terminal device. Therefore, TTY and TTL
compatible terminal devices can be connected directly to the HO channels. EIA converters, on standard K-series
modules, can be purchased from DEC to interface with long communications lines via modems. These modules are
not offered as PDP16-M options.

with the PDP16-M

[OBI—DB8
I

NB‘.

TTY

ass

JUMPERS
+5v

BITS
I
REGISTER:

HEUNH

I l l IMSB

CONTROL
HOLDING

I"'

i l l l LSBI I

ADAPTER

DATA BITS
HOLDING

FROM

UAgTI.

110 BAUD

DINzo

150 BAUD

PARALLEL-TOwSERI/AL
TRANSMITTER SHIFT REGISTER

300 BAUD
CLOCK

24.24 79' 7°. 32' 1"17'21’

15 I'
7* I+a
19 1E

R DR EN

DRIVER

+3V

N82

DéAITT’AS%g§

<k 9

600 BAUD
40

1200 BAUD

TCP

24008AUD

DATA ACCEPT

‘

24
l
L. we
A
____BE“ETE____

TTY

OUT

RECEIVER

TTL OUT
I

TTY

IN
'

TTL

SERIAL-TO-PARALLEL

RECEIVER SHIFT REGISTER

SIn=A
DEST

EVOKE

IN
To RDR
EN FF
I6

STE

"lIIOLDING REGISTER:
STATUS BITS

DATA BITS
HOLDING REGISTER

FLAG

MSB

LSB
I2

L“

4
RDE

<PFn>_

II
8

RDI-RDa

DATA BUS
BITS 0—7

l
I

A=SIn

I
CLOCK
FREQUENCIES
Lili
HO

176KHZ

‘Iso

240ml

I300

Aaoxm

I600

960KH2

I200

‘1

I
I

DATA

READY

DELAY

<KFn>

LLBA

I9 20mm

¥24OOL3840KH2

e=SIn

RDA

LEE£__EEL
I

55
_

KEYBOARD
FLAG

ISTOOSB

Figure 1 Serial I/O Option DC16-M, Block Diagram

DC16—Al1)

SOURCE
EVOKE

The UART (Universal Asynchronous Receiver/Transmitter) is

full

duplex receiver-transmitter. The chip accepts

asynchronous serial binary characters from the terminal and converts them to a parallel format for the PDP16—M. It
also accepts parallel binary characters from the PDP16—M and converts them to a serial asynchronous stream
(including start and stop bits) for the terminal. When transferred to and from the register transfer bus, the data bits
are right justified to the LSB (bit 0) of the data bus.
The UART is universal in that the number of desired data bits

(5, 6, 7, or 8), the number of stop bits (1 or 2) and

the required baud rate (1 10, 150, 300, 600, 1200, 2400) are externally selectable. The characteristics are selected by

installing a specific combination of jumpers on the interface adapter module. Other l/O connections on the UART
for controlling and synchronizing data transfers between the terminal and the PDP16-M register transfer bus.
Table 1 lists and describes the UART input and output signals that are used in the PDP16-M serial l/O channels.

are

Table 1

UART l/O Connections

Pin No.

I/O

Name

Function

Symbol

VCC Power Supply

VCC

+5V supply

VGG Power supply

VGG

'12V supply

Ground

Received Data Enable

RDE

A low on the receiver enable line places the

received data onto the output lines.

5—12

Received Data Bits

RD8—RD1

These are the eight data output lines. These
lines may be wire'ORed. When 5-, 6-, or 7level code is selected, the most significant
unused bits

low. Character will be right
justified
(pin 12) is the least significant bit, RD8 (pin
5) is the most significant bit. A high
are

into the least significant bits. RD1

indicates a mark.
13

Receive Parity Error

PER

Not used

Framing Error

FER

Not used

Overrun

Not used

Status Word Enable

SWE

A low on this line places the status word bits

(PE, DA, TBMT, FE, OR) onto the output
'

lines.

Receiver Clock Line

RCP

This

line

frequency

will

contain

times

clock

whose

(16X) the desired

receiver baud rate.
18

Reset Data Available

RDA

DC16-A (2)

A low on this lne mil reset the DA lne.

Table 1 (Cont)
UART I/O Connections
Pin No.

l/O

Name

Received Data Available

Symbol

’

Function

line goes to high when an entire
character has been received and transferred
This

to the receiver holding register.

Serial Input

This line accepts the serial bit input stream.

high must be present when data is not
being received. High is a mark; low is a

space.

External Reset

be pulsed after power turn on
(Power Clear) to a high. Resets all registers.

Should

Sets serial output line to a high. Sets TBMT
to a high. Sets EOC to a high.

Transmitter Buffer

TBMT

Not used

Empty
l

Data Strobe

high transition

A low to

this line will

enter the data bits into the data bits holding

End of Character

EOC

This

by the

line goes to

character
It

is controlled

a high each time a full
including stop bits is transmitted.

remains at this level until the start of

transmission of the next character. Start of
transmission is defined as the mark to space
transition of the start bit. It will remain at a

high when data is not being transmitted.
25

Serial Output

This line will

serially, by bit, provide the

entire transmitted character. it will remain

high when no data is being transmitted.
High is a mark; low is a space.

at a

26-33

Data Bit Inputs

DBl—DBB

These are the eight parallel data input lines.
If 5, 6,

7 bits

are

transmitted, the least

significant bit is used. D81 is the least
most significant bit (pin 26). D88 is the
most significant bit (pin 33). A high input
will cause a mark (high) to be transmitted.
most

Control Strobe

A high on this lead will enter the control bits

(POE NBl

NB2, SB, NP) into the control

bits holding register. This line can be strobed
or

DC16-A (3)

hard wired to a high level.

Table 1 (Cont)
UART l/O Connections
Pin No.

l/O

Name

Symbol

No Parity

Function

A high on this lead will eliminate the parity

bit

from

character.

the

transmitted

received

and

The stop bits 'will immediately

follow the last data bit on transmission. The
receiver will not check parity or reception. It
will, when asserted, also clamp the PE to a
low.

238

Two Stop Bits

This lead will select the number of stop bits.

One

to be appended immediately
parity bit. A low will insert one
stop bit and a high will insert two stop bits.
two

after the

37—38

Number of Bits/

N32, N81

These two leads will be internally coded to

Character

select either 5, 6, 7, or 8 data bits/character.
N82 (37)

N31 (38)

Bits/Character

0 (L)

1 (H)

0 (L)

1 (H)

(H)

Even Parity Select

POE

Not Used

Transmitter

TOP

This

will

line

contain

whose

clock

frequency is 16 times (16X) the desired
transmitter baud rate.

The serial

asynchronous bit stream for each character produced and received by the UART contains one start bit,
(Figure 2). A parity bit, which may be odd, even, or turned off, is

five to eight data bits and one or two stop bits

also acceptable to the UART, but is not implemented for the PDP16-M. If

implemented, the parity bit will follow

the last data bit.

STOP

DATA BITS
___.._._

___

BITS
A

‘fi
..__

—__

——

—'T

MARKIII

-———

6
I
5
'
2
3
'
I
START
l
l
i
SERIBAIT
(MSBI '
(L38) {—
I ____J__.__l.___.L_—__L___.l___J____L___L___..L__._.l
STREAM j

CLOCKl l l ili

SPACE(O)

IIIIIIIIII
16-0062

Figure 2 Character Bit Stream Format Options

001 6-A (4)

Both the receiver and the transmitter are double buffered. The UART will internally synchronize the start bit with
the clock to ensure uniform encoding and deco ing of the serial bit stream. Each bit of the seriai stream is

maintained at 16 clock periods.
Receiver

input (Sl, pin 20) line, the
pulses until
validate
the
to
8th
first
at
the
clock
is
line
serial
is
sensed.
The
and
bit
pulse
data
selected
each
sampled
input
stop
start bit and then at multiples of 16 clock pulses to decode the data and stop bits. The start bit is validated to guard

When the receiver is idle and the first mark to space transition

receiver will sample the serial

occurs

the serial

input line at the 8th clock pulse and thereafter at multiples of 16 clock

against false triggering due to noise spikes. The receiver will revert to the idle condition if the start bit

is not

validated.

If the start bit is validated, the receiver will enter the data entry state and store the state of the serial input line for

each data sampling point in the receiver shift register. One clock pulse after the stop bit(s) is sampled, a parallel data
transfer between the receiver shift register and the holding register is executed. At the same time, the Data Available

(DA) flag in the status bits holding register is set.
Transmitter
When the transmitter is idle, the serial output (80, pin 25) line will be marking (logic high). A low to high transition

(DS, pin 23) causes a mark to space transition on the serial output line. The delay between the
period. The transmitter produces one start bit, 5, 6, 7, or 8
data bits and 1 or 2 stop bits. The number of data and stop bits are determined by the control bits holding register.
The serial output line is presented with the least significant data bit (031, pin 26) first and the most significant data
bit (088, pin 33) last. The stop bit(s) follows the last data bit. All bits of the serial output stream are maintained at
of the data strobe

data strobe and mark to Space transition is one clock

constant width of 16 clock periods. The End Of Character flag (EOC, pin 24) will be low any time a Character Se in

the process of being converted and transmitted; the flag will go high each time a full character including the stop

bit(s) is transmitted.
Interface Control
The UART is interfaced with the terminal device via input receivers/converters and output drivers/converters. Both

compatible signals are available. Combinational and sequential logic are used for interfacing the
register transfer bus with the UART. Logic is included for printing (or displaying) a character on the
terminal and for reading a character from the terminal keyboard or paper tape reader.

TTY and TTL

PDP16—M

The following instructions evoke data transfers between the PDP16-M A and B Registers and the terminal.

READ

PRINT/DISPLAY

Sln

Destination

Source

Destination

Source

SIn

Sln

TAPE
n=1or2

DC16-A (5)

The

TAPEn command must precede the A and B

SIn instructions when reading from an ASR 33 paper tape reader.

This command advances the paper tape one character and transfers the serial bit stream to the UART. Whenever the

TAPEn command is executed, the RDR EN flip~flop is set and 3 DATA ACCEPT signal is issued. The RDR EN
flip-flop is reset by the first transition of the serial input bit stream. The TAPEn command is not required for
reading characters from other terminals. When the serial input bit stream is fully assembled and transferred to the
data bits holding register, the keyboard flag
(KFn) goes high. This flag can be tested by the following instruction:
IF

KFn, LABEL

After the flag goes high, the A

SIn or B

SIn instruction can be used to transfer the data to the PDPlB—M A or B

Registers. A DATA READY signal is issued by the serial l/O module (Source Register) and a DATA ACCEPT signal
is issued by the Destination Register (A or B) to interlock the data transfer.
In printing or displaying a character on a terminal, the A or B Register must first be loaded with the character
(justified to the LSB, bit 0) and the SIn A or SIn B instructions must be executed. After the DATA READY
signal is issued by the Source Register (A or B), the PUNCH FLAG flip-flop is set, causing the Punch flag (PFn) to go
low. At the same time, the data strobe (08, pin 23) is pulsed. On the low to high transition of the pulse, the data is
loaded into the data bits holding register and the conversion and transmission operation is started. After a full
character including the stop bit(s) is transmitted to the terminal, the END OF CHARACTER (EOC, pin 24) signal
goes high, causing the PUNCH FLAG flip-flop to be reset and the Punch flag (PFn) to go high. The flag can be tested
by the following instructions:
=

PFn, LABEL

After the flag goes high, the next instruction can be executed.
Clock

The clock for encoding and decoding the serial asynchronous data stream is derived from a frequency divider chain
that is driven by an 844.8 kHz crystal oscillator (Figure 3). One of seven operating frequencies can be selected from

installing a jumper on the interface adapter module. The operating speed and quality of
the determining factors for selecting the operating frequencies. The following
are
the
frequencies
produced by
frequency divider chain.

the divider chain simply by
the

communication

line

are

Terminal Speed

Operating Frequency
1.76 kHz

110 baud

2.4 kHz

150 baud

4.8 kHz

300 baud

9.6 kHz

600 baud

19.2 kHz

1200 baud

38.4 kHz

2400 baud
NOTE

The operating frequency is 16 times the terminal baud rate.

DClB-A (6)

844.8KHz
XTAL

IC7473
E'.

OSC

IC7492
E8

qr»

l+ 2)

2400 BAUD
;

(+11)

38.4KH2

IC7493
E11
14

1200

BAUP

192KHz

600

300

BAU_D
9.6K]:

BAU_D

4.8KHz

IC7473
E18

IC7492
E15

(*2)

IC7490
E12

(+12)

150 BAUD

2.4104:

no BAUD

1.76KHZ

(+10)

16‘0061

Figure 3 Clock Frequency Divider Chain, Block Diagram

INSTALLATION
Three prewired module slots are reserved on the PDP16-M logic assembly for

implementing the serial l/O channels.

They are:

Slot

Module

Name

A816

M7313

AB17

M7313

Sl2

D18

M7333

SI Adapter

S|1

The $1 adapter, module M7333, contains a set of split lugs and a Mate-N-Lok connector for each channel

(Figure 4).

The split lugs facilitate jumper installation for selecting the desired bit stream format. The number of data
bits and channel baud rate can be selected to complement the terminal device. Use the

bits, stop

following chart for installing

the required jumpers.

Stop Bits

Yes

Data Bits

N 81

Yes

N 82

Yes

Baud Rate

110

150

300

600

1 10

Yes

150
300

1200

2400

Yes
Yes

Yes

600

Yes

1200

Yes

2400

DC16-A (7)

J2
SI2 TTY
CONNECTOR

SI1
STOP AND
DATA BIT
SPLIT LUGS

BAUD RATE
SPLIT LUGS

|—.I_.__|
SII
SI2

$12
STOP AND
DATA BIT
SPLIT LUGS

J‘I
811 TTY
CONNECTOR

Figure 4 SI Adapter Module M7333, TTY Connectors and Split Lug Identification

The Mate-N-Lok connector is the TTY 20«mil current

loop interface connector for interfacing with the terminal

device. TTL compatible serial I/O connections are made available on the MUX I/O slot (C19).

PROGRAMMING
The instructions that evoke data transfers between the PDP16-M and a terminal via the two serial I/O channels (LET

instruction)

are

decoded

by the standard evoke decoders of the PDP16-M (Paragraph 4.2.4). No additional evoke

decoders are required. The machine code (octal), execution time, and description of each instruction follows:

CHANNEL NO. 1

Evoke

Time

(Octal Code)

(usec)

(SI1)
Description

Instruction

ST1 gets A (Data Out)

3.5

SI1

2.1

A=S|1

Agets SI1 (Data In)

052

1.7

TAPE1

Move paper tape and assemble one character

251

2.1

252

3.5

SI1

050
051

SI1
B

B gets SI1 (Data In)

SI1 gets B (Data Out)

CHANNEL N0. 2 (SI2)
Evoke

Time

(Octal Code)

(psec)

Instruction

Description

SI2 gets A (Data Out)

053

3.5

SI2

054

2.1

A=S|2

Agets SI2 (Data In)

055

1.7

TAPE2

Move paper tape and assemble one character

253

2.1

B=S|2

BgetsS|2(DataIn)

254

3.5

SI2

SI2 gets B (Data Out)

DC 1 6-A (8)

The TAPE1 and TAPE2 commands are required in a program only when reading data from a paper tape. They need
not be programmed when reading data from other types of devices, that is,

Random data transfers between

the terminal

keyboards or modems.

device and the PDP16—M

are not possible since the serial l/O
parallel and vice versa. The conversion time is
determined by the selected baud rate. For example, at a baud rate of 110 with a character format of one start bit,
eight data bits, and two stop bits, the maximum transfer rate possible is 10 characters per second (100 milliseconds
per character). Since the PDP16-M operates at a much faster speed, the data transfers must be synchronized to the

receiver/transmitter (UART)

must convert the data from serial to

conversion speed of the UART. For this reason, each channel has two flags:

punched or displayed; the other flag

(KFn)

is set when

one

flag (PFn) is set when a character is
ready to be read into the

character is assembled and

computer. The flag outputs are received and multiplexed by multiplexer 0 so that the IF instruction can be used to
test the flags for synchronizing the data transfers.

The flags are received by the following channels if multiplexer 0.

Input

MUXO Channel

KFl

PFl

KF2

PF2

DClG-A (9)

KFL16

BOOLEAN OUTPUT/FLAG OPTION

Three Boolean outputs/flags are included in the basic PDP16-M

(M7306)

(Paragraphs 1.2 and 2.6). Three additional Boolean

outputs/flags (FF4 through FF6) can be added by implementing the KF L16 option (M7306 module) (Figure 1). The
option module contains three flip-flops that can be set, reset, and tested under program control. One prewired
module slot, slot D2, is reserved on the PDP16-M logic assembly for installing the M7306 Option Module. The logic
1 sides (TRUE) of the flip-flops are wired to the MUX and FF l/O slot on the logic assembly to facilitate convenient
interfacing when the flip-flops are used as Boolean outputs. To implement this option, it is only necessary to install
the option module in the assigned slot. No other wiring or setup procedure is required, except if used as Boolean
outputs, to connect the external devices to be driven

to the MUX and

FF l/O slot. Refer to

Chapter 2 of the

PDP16-M User's Guide for interfacing details.

DA ENABLE

( +5v 1

FF=1

[FHDATA
NOT USED
DATA

LFF

3—9——

———Do—

FIXED
DELAY

DATA ACCEPT

45)

Jl>o——Jc Ro

FF=0

POWER
CLEAR
16-0056

Figure 1 Boolean Output/Flag Option KF L16, Block Diagram (1 of 3 Circuits)

flip-flops to be set and reset are decoded by the standard evoke decoders of the
No
additional
evoke decoders are required. The machine code (octal), execution time,
4.2.4).
(Paragraph

The instructions that cause the
PDP16-M

and description of each instruction follows:

SET

Evoke

Time

(Octal Code)

(usec)

FF'1
Instruction

Description

065

1.8

FF4

Set FF4

067

1.8

FF5 =1

Set FF5

071

1.8

FF6 =1

Set FF6

KLF16(1)

RESET
Evoke

Time

(Octal Code)

(11sec)

FFn
Instruction

Description

064

1.8

FF4

066

1.8

FF5

Reset FF5

070

1.8

FF6

Reset FF6

Reset FF4

The state of the flip-flop can also be tested using the IF instruction to facilitate the use of the flip-flops as program

flags. The machine code (octal), execution time, and description of the instructions follows:

Machine Code

Time

(Octal)

(usecl

Instruction

Description

MEMO

False

True

354

2.0

3.2

IF FF4, LABEL

Test FF4

356

2.0

3.2

lF FF5, LABEL

Test FF5

360

2.0

3.2

IF FF6, LABEL

Test FF6

KLF16 (2)

MR16-D

CONSTANT GENERATOR OPTION (M7325)

A 4-word diode ROM for storing constants is included in the basic PDP16—M. Transformer ROM storage for 24

additional constants can be added by implementing the MR16—D option (M7325 module). The module contains 16

(Figure 1). Each 16-bit constant is installed by stringing a wire from a split lug
each
core to the companion split lug. Twenty-five split lugs are provided at each
hole)
(adjacent

toroidal cores and data gating logic

around

through

end of

one

core

bank for this purpose

(Figure 2). One split lug pair is a test (T) pair to which a test wire is

connected. The test wire is strung through all cores to show the direction in which the wires for the constants must
be threaded. When

logic

installed, each wire establishes a current path for enabling and reading out a specific constant. A

1 is produced where the wire is threaded through the core and a logic 0 is produced where the wire is threaded

around the core (through the adjacent hole). When installing constants, the wires should be connected to companion

lug pairs so that a given constant wire can be easily identified. The lugs are numbered so that companion pairs can be
identified. The numbers assigned to the lugs correspond to the constant number (K1 through K24).

.-24

0..
15.2
41,1
+ 5v

‘

a IT
0
\q
T“

00)

+5v

I;
‘

BIT
1

‘l'A

D1_

EVOKE
SOURCE

I
b

DATA

BUS

AUJHJV
1.: Wu 1b

O
I
'

0
Q

;

+ 5v

‘L

B IT

+5V—NVV7

DATA

READY

1670053

Figure 1 Constant Generator Option MR16—D, Block Diagram

MR16-Dl1)

LTJ 1

15
'

CONSTANTCOREBANK

egg?

L'——‘|'——-’
SPLIT
LUGS

(CONSTANT
ENABLE)

(+5v)

Figure 2 Constant Generator Module M7325, Core Bank and Split Lug Location
,,

Prewired module slot

gait-12.3% the PDP16—M logic assembly is reserved for the M7325 Constant Generator Module.

implement this option, it is only necessary to install the module in the assigned slot. Except for threading and
connecting the constant wires, no wiring or set-up procedure is required. The module slot is prewired directly to the
register transfer bus. If it becomes necessary to change the constants from time to time, it can be done simply by
rethreading the wires or by installing an alternate constant generator module.
The instructions that evoke data transfers from the constant generator to the Destination
the standard evoke decoders of the PDP16-M

(Paragraph 4.2.4). No additional evoke decoders are required. The

machine code (octal), execution time, and description of each instruction follows:

Evoke

Ti me

(Octal Code)

(,usec)

Instruction

Description

Bgets K1

100

2.4

B=K1

101

2.4

102

2.4

103

2.4

104

2.4

105

B gets K2

B gets K3

B gets K4

B gets K5

2.4

B gets K6

106

2.4

B gets K7

107

2.4

B gets K8

110

2.4

MR 16-D (2)

gets K9

Evoke

Time

(Octal Code)

(psec)

Instruction

Description

111

2.4

B=K1O

112

2.4

B=K11

113

2.4

B=K12

Bgets K10
Bgets K11
Bgets K12

114

2.4

B=K13

B gets K13

115

2.4

B=K14

B gets K14

116

2.4

B=K15

B gets K15

117

2.4

B=K16

8 gets K16

120

2.4

B=K17

B gets K17

121

2.4

B=K18

B gets K18

122

2.4

B=K19

B gets K19

123

2.4

B=K20

B gets K20

124

2.4

B=K21

B gets K21

125

2.4

B=K22

B gets K22

126

2.4

B=K23

B gets K23

127

2.4

B=K24

B gets K24

MR16-D (3)

MR16-E/F

DATA PROM

OPTION (M7327)

The data PROM

(programmable read-only memory) option extends the read-only data memory Of the PDP16-M
(Figure 1). One or two data PROM Options (M7327 modules) can be implemented. Each Option (MR16-E) provides

256 8—bit bytes of storage. Both options (MR16-F) must be implemented to obtain 256 16-bit words of
storage. In

addition, a DB16-A general purpose interface option (M7311 module) is required when implementing the PROM(s)
interface the PROM(s) with the register transfer bus. This Option is also used in
establishing the parallel l/O

channels of the PDP16-M. However, in

implementing the PROM option, the M7311 module serves as the Memory
Register (MAR) and provides the necessary address/data gating logic and the bus drivers and receivers. The
data PROM(s), which is identical to the control PROM, can be used not
only to store additional constants but also
Address

to store canned

messages (ASCII

reserved on the PDP16-M

or EBCDIC characters), tables, or data
arrays. Three prewired module slots are
logic assembly for implementing the data PROM Option: two are reserved for the M7327

PROM modules and
purpose interface

one is reserved for the M7311 General
Purpose Interface Module. The slot for the general
module, slot A815, is wired directly to the register transfer bus. Each M7327 PROM module

provides storage for 256 8-bit bytes. Slot C15 is wired to the general purpose interface module to transfer the eight
data bits from the PROM to the eight low order bits of the register transfer bus, and slot D15 is wired to transfer the
data to the eight high order bits of the bus. If only eight data bits are implemented (one

MR16), the other eight bits

will always contain 15 when the data is transferred.

M7311

GPI

RECEIVERS

RMAR
REGISTER

M7327

M7327
DATA BUS

(PROM)

CIS

(PROM)

015

on
DRIVERS

oooo 0.000

_~ 01

A=ROM
EVOKE
SOURCE

DATA READY
B=R0M

DATA ACCEPT

EVOKE
DEST

16-0055

Figure 1 Data PROM Option MR 16-E/F, Block Diagram

MR16-E/Fl1)

The loading procedure for the data PROM is identical to that described for the control PROM. Refer to Chapter 5 of
the PDP16-M User’s Guide. The procedure for preparing the object tape, however, is different. Since a PDP16—M
program does not contain data,

provision for handling data is included in the PAL16 Assembler. Therefore,

object code must be used to define the required data constants, messages, and arrays to be loaded into the PROM.
The object tape can be prepared under the control of the Symbolic Editor.
If both data PROMs are to be implemented, one tape must be prepared for each PROM. After the tape is punched,
the PROM

be loaded

can

using the utility software/hardware package as described in Chapter 5 of the PDP76-M

User’s Guide. Only the following characters can be used in preparing the object code for the PROM.

Function

Character

To specify an 8-bit constant.

Three consecutive octal digits followed

by CR and LF.
To specify ASCII or EBCDIC

Octal Character Code

characters for canned messages.

Select random PROM load address

% followed by three octal numbers.

(preset PC with new address).
To indicate end of object code.

To form a 16-bit constant (for data tables or arrays), the coder must break up the desired 16-bit number into two

8-bit octal numbers, one for each data PROM. Two tapes, each containing one half of the constant, must then be

prepared. Care must be taken to ensure that both 8-bit parts of the constant fall in the same absolute location of the
PROMs. Then, when the-constant of that location is read, the correct 16-bit constant is transferred to the specified
Destination Register. Because the complement of the constant is stored in the PROM, the data must be
complemented to obtain the correct constant. Two instructions are available for complementing the data. They are:
A

ANOT and B

BNOT.

It is important to remember that the object code is loaded under control of the utility load program in sequential

locations starting with location 000 unless the address is changed using the % sign followed by an octal number. The

address and/or

base addresses of the constants, messages, and arrays must be recorded for the application
programmer’s use. Before a data transfer from the PROM to a Destination Register can be programmed, the desired
PROM location must be addressed. Once addressed, the general purpose interface retains the address in a Buffer
Register until another address is transferred. The instructions that evoke address and data transfers are decoded by
the standard evoke decoders of the PDPIG-M. No additional evoke decoders are required. The machine code (octal),
execution time, and description of each instruction follows:

ADDRESS PROM
Evoke

Time

(Octal Code)

(usec)

134

2.2

Instruction

RMAR

Description

RMAR gets A (send address
to PROM

Memory Address

2.2

RMAR

RMAR gets B (send address
to PROM Memory Address

READ DATA
Evoke

Time

(Octal Code)

(used

135

2.3

Instruction

A=ROM

Description

A gets ROM (transfer data
to A

011

2.4

147

2.3

B=ROM

ANOT

Complement data
B gets ROM (transfer data
to 8

031

2.4

BNOT

Complement data

*After the constant is read, it must be complemented to obtain the correct constant because the constants are stored in com-

plement form. This step can be avoided if the object code for the data PROM is prepared in complement form.

MR16-E/F (3)

MS16-C
SCRATCH PAD REGISTER OPTION

(M7318)

One temporary storage register (the byte and word addressable Transfer Register, TR) is included in the basic
PDP16—M. Thirty-two additional word addressable temporary storage registers (Scratch Pad Registers) can be added

by implementing two MS16—C options (M7318 modules) and two PCS16-C options (M7328 modules). The M7318
module contains 16 high-speed word addressable registers (Figure 1), and the M7328 module contains the evoke
pad instruction codes to evoke data transfers
Registers (Paragraph 4.2.4). All 32 Scratch Pad Registers need not be
implemented. Installing one MSl6-C option and one PCS16-C option provides 16 Scratch Pad Registers. Four
prewired module slots are reserved on the PDP16-M logic assembly for installing the option modules. The two slots
for the M7318 Scratch Pad Register Modules are wired directly to the PDP16—M register transfer bus. The two slots
are assigned their own respective sets of mnemonics for programming reasons. To implement either 16 or 32 Scratch
Pad Registers, it is necessary only to install the option modules in the assigned slots. No other wiring or set-up
procedure is required. Slot assignments for the scratch pad option are as follows:

decoders for these

registers.

The evoke decoders decode scratch

between the specified Source and Destination

Slot

Module

Assigned Function

AB4

M7318

SP1—SP16 Registers (Group 1)

A83

M7318

SP17—SP32 Register (Group 2)

C06

M7328

Evoke Decoder 3 (SP1—SP16)

CD7

M7328

Evoke Decoder 4 (SP17—SP32)

0(A=SP1)
16(SP1=A)
Ao

1(A=SP2)
EVOKE
REG'STER

17(SP2=A)
.
.

15(A=SP16)

ADDRESS
ENCODER

'6 X16

DRIVERS

31(SP16=A)

{L
F

WRlTE

‘

READ

O(A=SP1)
1(A=SP2)

Evo KE

SOURCE

(DATA BUS>

}

DATA BUS

M1307

.
-

A = SPn

READ

FIXED
DELAY

DATA

READY_

15(A=SP16)

(16(SP1=A)
17(SP2=A)
FIXED
DELAY

EVOKE
DEST

DATA

ACCEPT:
(6-0054

Figure 1 Scratch Pad Register Option MSlB-C, Block Diagram

MSlB-C (1)

assignments must be adhered to in installing the options and/or programming the data transfers
Register evoke signals are hard wired. The instructions that evoke data transfers
to and from the Scratch Pad Registers are decoded by the evoke decoders. The machine code (octal), execution
time, and description of each instruction follows:

The above slot

because the Scurce and Destination

SCRATCH PAD REGISTER GROUP 1 (SP1—SP16)

Evoke

Time

(Octal Code)

(usec)

Instruction

Description

140

2.2

SP1

A gets SP1

141

2.2

SP2

A gets SP2

142

2.2

SP3

A gets SP3

143

2.2

A = SP4

A gets SP4

144

2.2

SP5

A gets SP5

145

2.2

SP6

A gets SP6

146

2.2

SP7

A gets SP7

147

2.2

SP8

A gets SP8

150

2.2

SP9

A gets SP9

151

2.2

A=SP10

152

2.2

A=SP11

153

2.2

A= SP12

154

2.2

A=SP13

155

2.2

A =SP14

156

2.2

A=SP15

157

2.2

160

2.6

SP1

161

2.6

SP2

162

2.6

SP3

163

2.6

SP4

164

2.6

SP5

165

2.6

SP6

166

2.6

SP7

167

2.6

170

SP16

Agets SP10
Agets SP11
Agets SP12
Agets SP13
Agets SP14
Agets SP15
Agets SP16

SP1 gets A

SP2 gets A

SP3 gets A

SP4 gets A

SP5 gets A

SP6 gets A

SP8

SP8 gets A

2.6

SP9

SP9 gets A

171

2.6

SP10=A

SP109etsA

172

2.6

SP11

SP11 gets A

173

2.6

SP12

SP12 gets A

174

2.6

SP13= A

175

2.6

SP14=A

176

2.6

SP15=A

177

2.6

SP16= A

SP13getsA
SP14getsA
SP159etsA
SP169etsA

‘

SP7 gets A

SCRATCH PAD REGISTER GROUP 2 (SP17—SP32)
Evoke

Time

(Octal Code)

(usec)

Instruction

Description

200

2.2

SP17

A gets SP1?

201

2.2

A=SP18

Agets SP18

202

2.2

SP19

A gets SP19

MS16—C (2)

SCRATCH PAD REGISTER GROUP 2 (SP17—SP32) (Cont)
Evoke

Time

(Octal Code)

(usec)

Instruction

Description

203

2.2

SP20

A gets SP20

204

2.2

SP21

A gets SP21

205

2.2

SP22

A gets SP22

206

2.2

SP23

A gets SP23

207

2.2

SP24

A gets SP24

210

2.2

SP25

A gets SP25

211

2.2

SP26

A gets SP26

212

2.2

SP27

A gets SP27

213

2.2

SP28

A gets SP28

214

2.2

SP29

A gets SP29

215

2.2

SP30

A gets SP30
A gets SP31

216

2.2

SP31

217

2.2

SP32

220

2.6

SP17

221

2.6

SP18

222

2.6

SP19

223

2.6

SP20

224

2.6

225

A gets SP32

SP17 gets A

SP18 gets A

SP19 gets A

SP20 gets A

SP21

SP21 gets A

2.6

SP22

SP22 gets A

226

2.6

SP23

SP23 gets A

227

2.6

SP24

SP24 gets A

230

2.6

SP25

SP25 gets A

231

2.6

SP26

SP26 gets A

232

2.6

SP27

SP27 gets A

233

2.6

SP28

SP28 gets A

234

2.6

SP29

SP29 gets A

235

2.6

SP30

SP30 gets A

236

2.6

SP31

SP31 gets A

237

2.6

SP32

SP32 gets A

The 8 Register cannot be used in programming data transfers to and from the Scratch Pad Registers.

MS16—C (3)

MS16-D
DATA

R/W MOS MEMORY OPTION

(M7319)

The MSlG-D data R/W MOS memory option extends the read/write data memory of the PDP16-M (Figure 1). One
data memory options (M7319 modules)

can be implemented. Each data memory option provides 256 words
prewired module slots are reserved on the PDP16-M logic assembly for installing the M7319
modules. To implement a data memory option, it is necessary only to install the option module in one of the
assigned slots. No other wiring or set-up procedure is required.
or two

of storage. Two

MARn=A

DATA

DATA READY

LOAD
ADDRESS

A0
A1

8-BIT
ADDRESS
REGISTER

A4
A5

256 X16
MOS
REGISTER

DRIVERS

DATA READY

l6"0052

Figure 1

Data R/W MOS Memory Option MS16-D, Block Diagram

MS16-D (1)

Register (MAR), a 256 X 16 Data Register (MEM), 16 bus
drivers, and evoke logic for loading the address, reading data, and writing data. The instructions that evoke address
The M7319 module contains an 8-bit Memory Address

and data transfers between the PDP16-M working registers and the memory options are decoded
evoke decoders of the PDP16-M

by the standard
two
are
The
module
slots
each
4.2.4).
prewired
(Paragraph
assigned different

mnemonics for accessing the Memory Address and Data Registers. The mnemonics are:

Slot

The above slot

Memory Address
Register

Data

A86

MAR 1

MEM1

AB7

MAR2

MEM2

assignments must be adhered to in installing the options and/or programming address and data

transfers because the Source and Destination Register evoke signals are hard wired.

The machine code (octal), execution time, and description of each instruction follows:

TRANSFER ADDRESS
Evoke

Time

(Octal Code)

(psec)

240

2.3

Instruction

MAR1

Description

MAR1 gets A (send address to
MEM1 Memory Address Register)

243

2.3

MAR2

MAR2 gets A (send address to
MEM2 Memory Address Register)

TRANSFER DATA

Evoke

Time

(Octal Code)

(usec)

Instruction

241

3.6

MEM1

242

3.9

244

3.6

MEM2

245

3.9

Description

MEM1 gets A (write data)

MEM1

A gets MEM1 (read data)

MEM2 gets A (write data)

MEM2

A gets MEM2 (read data)

The B Register cannot be used in programming address and data transfers involving the RM MOS memory option.

MS‘lB-D (2)

MS16-E
DATA R/W MOS MEMORY OPTION

The MSlG-E

R/W MOS data memory extends the read/write data memory of the PDP16-M. One or two data

memory options

With the

(M7324)

(M7324 modules) can be implemented. Each data memory option provides 1024 words of storage.

exception of the memory size, which requires a 10-bit address, the MSlB—E option is identical to the

MSlG—D option. Only two data R/W MOS memory options (MSlG-D and/or MSlG-E) can be implemented. Refer to
MSlB-D option description for installation and programming details.

MSlG-E (1)

PCS16-B
CONTROL PROM OPTION (M7327)

The control PROM (programmable read-only memory) extends the control program memory of the PDP16-M. One
control PROM is included in the basic PDP16-M, while three are optional. Each PROM provides program storage for

256 8-bit words. Four prewired module slots are reserved on the PDP16—M

logic assembly for the control PROMs.

They are:

Slot

PROMO

C16

Name

Remarks

MEMO, PAGEO

Standard locations

(0000
PROM1

D16

MEM1, PAGEO

—

03778)

Optional locations
(0400
07778)
-—

Refer to

PROM2

C17

MEMO, PAGE1

Optional locations
(1000 —13778)

PROM3

D17

MEM1, PAGE1

Optional locations
(1400 —17778)

Paragraph 4.2.2 for the description of the memory and page select logic and refer to Chapter 5 of the

PDP76-M User’s Guide for details on loading, simulating, and checking the application program.

PCS16-B (1)

PCS16-D
BOOLEAN INPUT MULTIPLEXER OPTION (M7329)

multiplexer (MUXO) for multiplexing 30 external and internal inputs is included in the basic
PDP16-M (Paragraph 4.2.3). One additional Boolean input multiplexer (MUX1) can be added by implementing the
PCSlB-D option (M7329 module). The option module multiplexes 30 additional external and internal Boolean
inputs which can be selected for test under program control using the IF instruction. The MUX1 command must be
declared in the program to select the optional multiplexer. If the test is found to be true, a branch to another
instruction is executed; if the test is found to be not true, then the next instruction is executed. One prewired
module slot, slot A819, is reserved on the PDP16-M logic assembly for installing the M7329 Multiplexer Module.
The slot is wired directly to the control memory bus. The module slot is also wired to the MUX and FF l/O slot on
the logic assembly to facilitate convenient interfacing for external Boolean inputs. To implement the multiplexer
option, it is only necessary to install the option module in its assigned slot. No other wiring or set-up procedure is
required except to connect the external Boolean inputs, if used, to the MUX and FF l/O slot. Refer to Chapter 2 of
the PDP16-M User’s Guide for interfacing details.
One Boolean input

The M7329 Multiplexer Module contains two data selector chips and output signal combining logic (Figure 1). Each

chip can handle 16 inputs. Only one input is selected at any one time. The selection is made by the IF instruction
machine code bits 1 through 5. The machine code serves as the address for the data selectors. The machine code
(octal), execution time, and description of the MUX1 lF instruction set follows:

2,9,
27
O

BOOK—E3?

DATA

SELECTOR

O
O
O

CONTROL
CODE

(ADDRESS)
ENABLE

(MUX1 COMMAND)

BOOLEAN
INPUT

EXT IN
FROM MUXO

TEST

DATA

0...

SELE1CTOR

l6'0057

Figure 1

Boolean lnput Multiplexer Option PCSlB-D, Block Diagram

PCSlG-D (1)

Machine Code

Time

(Octal)

(usec)

MEMO

Instruction

Description

MEM1

False

True

300

301

2.0

3.2

GOTO

Test channel 0 input (+3V)

302

303

2.0

3.2

IF A<O>, LABEL

Test channel 1 input (A<0>)

304

305

2.0

3.2

IF A<2>, LABEL

Test channel 2 input (A<2>)

306

307

2.0

3.2

IF A<4>, LABEL

Test channel 3 input (A<4>I

310

311

2.0

3.2

IF A<6>, LABEL

Test channel 4 input (A<6>I

312

313

2.0

3.2

IF A<8>, LABEL

Test channel 5 input (A<8>)

314

315

2.0

3.2

IF A<10>, LABEL

Test channel 6 input (A<10>)

316

317

2.0

IF A<12>, LABEL

Test channel 7 input (A<12>)

320

321

2.0

3.2

IF A<14>, LABEL

Test channel 8 input (A<14>I

322

323

2.0

3.2

IF B<0>, LABEL

Test channel 9 input (B<0>)

324

325

2.0

3.2

IF B<15>, LABEL

Test channel 10 input (B<15>)

326

327

2.0

3.2

IF EXT7, LABEL

Test channel 11 input (EXT7)

330

331

2.0

3.2

IF EXT8, LABEL

Test channel 12 input (EXT8)

332

333

2.0

3.2

IF EXT9, LABEL

Test channel 13 input (EXTQ)

334

335

2.0

3.2

IF EXT10, LABEL

Test channel 14 input (EXTIO)

336

337

2.0

3.2

IF EXT11, LABEL

Test channel 15 input (EXT11)

340

341

2.0

3.2

IF EXT12, LABEL

Test channel 16 input (EXT12)

342

343

2.0

3.2

IF EXT13, LABEL

Test channel 17 input (EXT13)

344

345

2.0

3.2

IF EXT14, LABEL

Test channel 18 input (EXT14)

346

347

2.0

3.2

IF EXT15, LABEL

Test channel 19 input (EXT15)

350

351

2.0

3.2

IF EXT16, LABEL

Test channel 20 input (EXT16)

352

353

2.0

3.2

IF EXT17, LABEL

Test channel 21 input (EXT17I

354

355

2.0

3.2

IF EXT18, LABEL

Test channel 22 input (EXT18)

356

357

2.0

3.2

IF EXT19, LABEL

Test channel 23 input (EXT19)

360

361

2.0

3.2

IF EXT20, LABEL

Test channel 24 input (EXT20)

362

363

2.0

3.2

IF EXT21, LABEL

Test channel 25 input (EXT21)

364

365

2.0

3.2

IF EXT22, LABEL

Test channel 26 input (EXT22I

366

367

2.0

3.2

IF L, LABEL

Test channel 27 input (LINK)

370

371

2.0

3.2

IF PWOK, LABEL

Test channel 28 input (POWER OK)

372

373

2.0

3.2

Not used

Ground return for external inputs

PCS16-D I2)

APPENDIX B

MAINTENANCE HARDWARE

CONSTRUCTION PROCEDURE

To facilitate diagnostic testing without having to connect the parallel and serial l/O channels to external equipment,
the following jumper modules and plugs must be prepared by the user.

lnterface Jumper Module 1

Interface Jumper Module 2
Two Serial l/O Jumper Plugs
Two W971

double-height modules and two Mate-N-Lok plugs are included with the equipment shipped. The user

should install jumpers on the modules and plugs as detailed in the following paragraphs.

lnterface Jumper Module 1
a.

Secure the following items:
1.

W971 Module

22 AWG Bus Wire

Teflon Tubing

Using the Teflon tubing as insulation, connect the following pins together.

From

BA1

BB2

BB1

BDZ

BC1

8E2

BD1

BF2

BE1

BH2

BF1

BJ2

BH1

BK2

BJ1

BL2

BK1

BM2

BL1

BN2

BM1

BP2

BN1

BR2

B-l

From

BP1

BSZ

BR1

BT2

BS1

BU2

BU1

BV2

AK2

AV2

AA1

A31

A81

AC1

AD1

AE1

AF1

BA1

Interface Jumper Module 2

Secure the following items:
1.

W971 Module

22 AWG Bus Wire

Teflon Tubing

Using the Teflon tubing as insulation, connect the following pins together.

From

BA1

BB2

AA1

A82

881

BD2

A81

A02

BC1

BE2

AC1

AE2

BD1

BF2

AD1

AF2

BE1

BH2

AE1

AH2

BF1

BJ2

AF1

AJ2

BH1

BK2

AH1

AK2

BJ1

BL2

AJ1

AL2

BK1

BM2

AL1

AN2

BL1

BN2

AM1

AP2

BM1

8P2

AN1

AR2

BN1

BR2

AP1

AS2

BP1

BSZ

AR1

AT2

BR1

BT2

A81

AU2

BS1

BU2

AU1

AV2

BU1

BV2

AK1

AM2

B-2

Serial l/O Jumper Plugs
a.

Secure the following items:
1.

Two Mate-N-Lok plugs

Six male pins

24 AWG Teflon stranded wire

On each plug connect pins 2, 5, and 7 together (Figure 8-1).

CAUTION
The serial I/O interface module (M7313) will be damaged if

pins are connected together. A total of eight pins
pin insertion slots are
not numbered
but are designated 1—8 as shown.

the wrong
can

be installed in the connector; the
—

N'Housing (male) DEC No.12-9340-01
2-Connector Pins (male) DEC No.12-9378
4required per cable

1- Mate

16-0068

Figure 3-1 Serial l/O Jumper Plug

B-3

APPENDIX C

SIGNAL LISTING

Alphabetic signal listings with associated pin assignments of PDP16-M I/O and BUS signals and PDP-11 l/O signals
in this appendix (Tables C-1 C-2, and C-3).

are contained

Table 6-1
PDP16-M l/O Slot Pin Assignments (By Signal Name)
Slot

AUTO RUN

D01

S1/U1

CONTINUE

C19

EXT 1

C19

EXT 2

C19

EXT 3

C19

EXT 4

C19

EXT 5

C19

EXT 6

C19

EXT 7

C19

Signal

EXT 8

C19

EXT 9

C19

EXT 10

C19

EXT 11

C19

EXT 12

C19

EXT 13

C19

EXT 14

C19

EXT 15

C19

EXT 16

C19

EXT 17

C19

EXT 18

C19

EXT 19

C19

EXT 20

C19

EXT 21

C19

EXT 22

C19

FF1

C19

FF1

D19

FF2

C19

FF2

C20

FF3

C19

FF3

D20

C-1

Table 0-1 (Cont)

PDP16-M l/O Slot Pin Assignments (By Signal Name)
Slot

Signal

FF4

C19

FF5

C19

FF6

C19

GPI1

DOO

D19

GPI1

D01

D19

GPI1

DO2

D19

GPI1

D03

D19

GPI1

DO4

D19

GPI1

D05

D19

GPI1

DOG

D19

GPI1

DO7

D19

GPI1

D08

D19

GPI1

D09

D19

GPI1

D10

D19

GPI1

D11

D19

GPI1

D12

D19

GPI1

D13

D19

GPI1

D14

D19

GPI1

D15

D19

GPI1

FF1

D19

GPI1

100

D19

GPI1

101

D19

GPI1

102

D19

GPI1

103

D19

GPI1

104

D19

GPI1

105

D19

GPI1

106

D19

GPI1

107

D19

GPI1

108

D19

GPI1

109

D19

GPI1

110

D19

GPI1

111

D19

GPI1

112

D19

GPI1

113

D19

GPI1

114

D19

81
U1

GPI1

115

D19

GP12

D00

C20

GP12

D01

C20

D2
E2

GP12

D02

C20

GP12

D03

C20

GP12

D04

C20

GP12

DOS

C20

GP12

D06

C20

GP12

D07

C20

L2
M2

GP12

D08

C20

GP12

D09

C20

GP12

D10

C20

C-2

Table C-1 (Cont)
PDP16—M 1/0 Slot Pin Assignments (By Signal Name)
Slot

Signal

GP12

D11

C20

GP12

D12

C20

GP12

D13

C20

GP12

D14

C20

GP12

D15

C20

GP12

FF2

C20

GP12

100

C20

GP12

101

C20

GP12

102

C20

GP12

103

C20

GP12

104

C20

GP12

105

C20

GP12

106

020

GP12

107

C20

GP12

108

C20

GP12

109

C20

GP12

110

C20

GP12

111

C20

GP12

112

C20

GP12

113

C20

GP12

114

C20

GP12

115

C20

GP13

D00

D20

GP13

D01

D20

GP13

D02

D20

GP13

D03

D20

GP13

D04

D20

GP13

D05

D20

GP13

D06

D20

GP13

D07

D20

GP13

D08

D20

GP13

D09

D20

GP13

D10

D20

GP13

D11

D20

GP13

D12

D20

82
T2

GP13

D13

D20

GP13

D14

D20

GP13

D15

D20

GP13

FF3

D20

GP13

100

D20

GP13

101

D20

GP13

102

D20

GP13

103

D20

GP13

104

D20

GP13

105

D20

GP13

106

020

GP13

107

D20

C-3

Table C-1 (Cont)

PDP16-M I/O Slot Pin Assignments (By Signal Name)
Slot

Signal

GPI3

I08

D20

GPI3

I09

D20

GPI3

I10

020

GPI3

I11

D20

GPI3

I12

D20

GPI3

I13

D20

GPI3

I14

020

GPI3

I15

D20

GROUND

C19

MSYN

C19

S|1

C19

SI1

C19

812

C19

812

C19

SSYN

Table C-2

PDP16-M Data Bus Pin Assignments (By Signal Name)
Pin

Signal

(Slots ABO1

—

Data Bit 00

AA1

Data Bit 01

A31

Data Bit 02

AC1

Data Bit 03

AD1

Data Bit 04

AE1

Data Bit 05

AF1

Data Bit 06

AH1

Data Bit 07

AJI

Data Bit 08

AK1

Data Bit 09

AL1

Data Bit 10

AM1

Data Bit 11

AN1

Data Bit 12

AP1

Data Bit 13

AR1

Data Bit 14

A81

Data Bit 15

AU1

DATA ACCEPT

BA1

DATA READY

BB1

DONE

BC1

OVERFLOW

BDI

POWER CLEAR

BE1

0-4

AB17)

Table C-3

PDP-11 Unibus Pin Assignments (By Signal Name)

Signal

AOOL

BH2

D06L

AFl

A01L

BHl

DO7L

AH2

A02L

8J2

DO8L

AHl

A03L

BJ1

DOQL

AJ2

A04L

BK2

D10L

AJl

A05L

BKl

01 1 L

AK2

A06L

BL2

Dl2L

AK1

A07L

BL1

D13L

AL2

A08L

BM2

D14L

AL1

A09L

BM1

D15L

AM2

A10L

BN2

GROUND

AB2

A11L

BN1

GROUND

AC2

A12L

8P2

GROUND

AN1

A13L

BPl

GROUND

APl

A14L

8R2

GROUND

ARl

A15L

BRl

GROUND

ASl

A16L

882

GROUND

AT1

A17L

BSl

GROUND

AV2

ACLOL

BF1

GROUND

BBZ

BBSYL

AP2

GROUND

BC2

BG4H

8E2

GROUND

BDl

BG5H

BBl

GROUND

BEl
BT1

BG6H

BAl

GROUND

BG7H

AV1

GROUND

BV2

BR4L

BD2

INITL

AAl
ABl

BR5L

BCl

INTRL

BR6L

AU2

MSYNL

BV1

BR7L

AT2

NPGH

AUl

COL

BU2

NPRL

A82

C1 L

BT2

PAL

AMl

DOOL

AC1

PBL

AN2

D01 L

AD2

+5V*

AA2

D02L

ADl

+5V*

BA2

DO3L

AE2

SACKL

AR2

DO4L

AEl

DCLOL

BF2

D05L

AF2

SSYNL

BUl

*+5V is wired to these pins to supply power to the bus terminator only.

+5V sh0u|d never be connected via the Unibus between system units.

C-S

APPENDIX D

PDP16-M MACHINE CODES

This is a list of all PDP16-M machine instructions. The basic PDP16-M hardware consists of:

Quantity

d—i—d

Model No.

Module No.

Name

Slot

KBS16—A

Bus Control

M7332

A82

KAC16

GPA Control Unit

M7300

A811

KAR16

GPA Register Unit

M7301

A810

MR16—A

4-Word Constants

M7307

ABS

MS16-A

Transfer Register

M7305

A39

DB16~A

General Purpose

M7311

AB 1 2

PCS1 6-A

PCS Control

M7336

AB20

PCS16-B

PCS Control PROM

M7327

C16

PCS1 6-C

Evoke Decoders

M7328

CD3,4,5,8

Generator

Interface 1

(0, 1, 2, 5)
PCS16—D

MUXO

M7329

AB18

KFL16

Flags (1,2,3)

M7306

Machine Code

Time

(Octal)

(usec)

I nstructio n

Evoke
Decoder No.

Evoke
Decoder
Channel

000

2.4

001

2.4

002

2.4

003

2.4

004

2.4

005

2.4

006

2.4

007

2.4

010

2.4

01 1

2.4

OOOOO dONOLfl-th—‘O
-l-—I

D-1

Option

Slot

Ti me

(Octal)

(psec)

Instruction

Evoke
Decoder No.

Evoke

Option

Slot

Decoder

Channel

01 2

2.4

A=A/2

01 3

2.4

A=AX2

01 4

2.4

A=A+1 (S)

01 5

2.4

01 6

2.4

A=Ar11S)
A=A+B(S)

01 7

2.4

A=A— B(S)

020

2.4

021

2.4

A=A/2(S)
A=AX2(S)

022

2.4

B=0

023

2.4

024

2.4

025

2.4

23
+B

026

2.4

027

2.4

030

2.4

031

2.4

W W U W> > >

032

2.4

B=B/2

033

2.4

B=A+B(S)

034

2.4

B=A-B(S)

035

2.4

B=B/2(S)

036

2.4

EXA

037

2.4

EXB

040

2.2

GPI1=A

—B

XORB

ORB
B

B=BNOT

041

2.0

A=GPI1

042

2.2

GPI2=A

043

2.0

A=GP|2

044

2.2

GP|3=A

045

2.0

A=GP|3

046

2.4

B=C1

047

2.4

B=C2

050

3.5

S|1=A

051

2.1

A=Si1

052

1.7

TAPE1

053

3.5

Sl2=A

054

2.1

A=SIZ

055

1.7

TAPE2

056

1.8

FF1=0

057

1.8

FF1=1

060

1.8

FF2=0

061

1.8

FF2=1

062

1.8

FF3=0

063

1.8

FF3=1

064

1.8

FF4=0

065

1.8

FF4=1

066

1.8

FF5=0

067

1.8

FF5=1

dd—i—L—n—de—I—Id—l—b—a—I_\._|._\d—d—L—t-AOOOOOOOOOOO

D-2

24
25

26
27

30
31
32

33
34

36
37

mwa—‘o

DB16-A

A813

DB16—A

A813

DB16-A

A814

DB16-A

A814

DC16-A

A816

DC16—A

A816

DC16-A

A816

DC16-A

A817

DC16-A

A817

DC16-A

A817

KLF16

16
17

20
21

Time

(Octal)

(usec)

Instruction

Evoke
Decoder No.

Evoke

Option

Slot

Decoder
Channel

070

1.8

FF6=0

KLF16

071

1.8

FF6=1

KLF16

072

1.8

PAGEO

MORE THAN

CD16

2 PCS16-B

CD17

073

1.8

PAGE1

MORE THAN

CD16

2 PCS16-B

CD17

A819

074

1.8

L=0

075

1.8

L=1

076

1.8

MUXO

077

1.8

MUX1

PCS16-D

100

2.4

B=K1

MR16-D

A88

101

2.4

B=K2

MR16-D

A88

102

2.4

B=K3

MR16-D

A88

103

2.4

B=K4

MR16-D

A88

104

2.4

B=K5

MR16-D

A88

105

2.4

B=K6

MR16-D

A88

106

2.4

B=K7

MR16—D

A88

107

2.4

B=K8

MR16-D

A88

110

2.4

B=K9

MR16—D

A88

111

2.4

B=K10

MR16-D

A88

112

2.4

B=K11

MR16-D

A88

113

2.4

B=K12

MR16-D

A88

114

2.4

B=K13

MR16-D

A88

115

2.4

B=K14

MR16-D

116

2.4

B=K15

MR16-D

A88

117

2.4

B=K16

MR16—D

A88

120

2.4

B=K17

MR16-D

A88

121

2.4

B=K18

MR16-D

A88

122

2.4

B=K19

MR16-D

A88

123

2.4

B=K20

MR16-D

A88

124

2.4

B=K21

MR16-D

A88

125

2.4

B=K22

MR16-D

A88

126

2.4

B=K23

MR16-D

A88

127

2.4

B=K24

MR16-D

A88

130

2.3

TR=A

131

2.1

A=TRU

132

2.1

A=TRL

133

2.1

A=TR

134

2.2

RMAR=A

PCS16—B

ABCD15

and DB16-A

135

2.3

A=ROM

PCS16-B

ABCD15

and DB16-A

136

2.4

B=C3

137

2.4

8=C4

140

2.2

A=SP1

MS16-C

A84

141

2.2

A=SP2

MS16-C

A84

D-3

Time

(Octal)

(usecI

Instruction

Evoke

Decoder No.

Evoke

Option

Slot

Decoder

Channel
142

2.2

A=SP3

M816-C

AB4

143

2.2

A=SP4

M816-C

AB4

144

2.2

A=SP5

MS16-c

A84

145

2.2

A=SP6

M816-C

AB4

146

2.2

A=SP7

M816-C

AB4

147

2.2

A=SP8

M816-C

AB4

150

2.2

A=8P9

M816-C

AB4

151

2.2

A=SP10

MS16-C

AB4

152

2.2

A=SP1 1

M816-C

AB4

153

2.2

A=SP12

M816-C

AB4

154

2.2

A=SP13

M816-C

AB4

155

2.2

A=SP14

MS16-C

AB4

156

2.2

A=SP15

M816-C

AB4

157

2.2

A=SP16

M816-C

AB4

160

2.6

SP1=A

MS16-C

AB4

161

2.6

8P2=A

M816-C

AB4

162

2.6

8P3=A

M816-C

AB4

163

2.6

8P4=A

MS16-C

AB4

164

2.6

SP5=A

M816-C

AB4

165

2.6

8P6=A

M816-C

AB4

166

2.6

SP7=A

M816-C

AB4

167

2.6

8P8=A

MS16-C

AB4

170

2.6

8P9=A

M816-C

AB4

171

2.6

SP10=A

M816-C

AB4

172

2.6

8P11=A

M816-C

AB4

173

2.6

SP12=A

M816-C

AB4

174

2.6

8P13=A

MS16-C

AB4

175

2.6

8P14=A

M816-C

AB4

176

2.6

8P15=A

MS16-C

AB4

‘

177

2.6

SP16=A

MS16-C

AB4

200

2.2

A=SP17

M816-C

AB3

201

2.2

A=SP18

M816-C

AB3

202

2.2

A=SP19

MS16-C

AB3

203

2.2

A=SP20

M816-C

AB3

204

2.2

A=SP21

M816-C

AB3

205

2.2

A=SP22

M816-C

AB3

206

2.2

A=SP23

MS16-C

AB3

207

2.2

A=SP24

MS16-C

AB3

210

2.2

A=SP25

M816—C

AB3

211

2.2

A=SP26

MS16-C

AB3

212

2,2

A=SP27

M816-C

AB3

213

2.2

A=SP28

M816—C

AB3

214

2.2

A=SP29

M816-C

AB3

215

2.2

A=SP30

M816-C

AB3

216

2.2

A=SP31

MS1 6-C

A33

217

2.2

A=SP32

M816-C

ABS

0-4

Time

(Octal)

(usec)

Instruction

Evoke
Decoder No.

Evoke

Option

Slot

Decoder

Channel

220

2.6

SP17=A

MS16-C

A83

221

2.6

SP18=A

MS16-C

A83

222

2.6

SP19=A

MS16-C

A83

223

2.6

SP20=A

MS16-C

A83

224

2.6

SP21=A

MS16-C

A83

225

2.6

SP22=A

MSIB-C

A83

226

2.6

SP23=A

MS16-C

A83

227

2.6

SP24=A

MS16-C

A83

230

2.6

SP25=A

MS16-C

A83

MS16-C

A83

MS16-C

A83

MS16-C

A83

MS16-C

A83

MS16-C

A83

MS16-C

A83

MS16-C

A83

MS16-D or E

A86

MS16-D or E

A86

MS16-D or E

A86

MS16-D or E

A87

MS16-D or E

A87

MS16-D or E

A87

PCS16-B

ABCDIS

231

2.6

SP26=A

232

2.6

SP27=A

233

2.6

SP28=A

234

2.6

SP29=A

235

2.6

SP30=A

236

2.6

SP31=A

237

2.6

SP32=A

240

2.3

MARI=A

241

3.6

MEM1=A

242

3.9

A=MEM1

243

2.3

MAR2=A

244

3.6

MEM2=A

245

3.9

A=MEM2

246

2.2

RMAR=B

247

2.3

B=ROM

mmmmbbhhbkhbhhb

m‘wa—IO

and DB16—A

PCS16-B

ABCD15

and DB16—A

250

2.0

TR=O

251

2.1

B=Sl1

DC16-A

A816

252

3.5

Sl1=B

DC16-A

A816

253

2.1

B=SI2

DC16-A

A817

254

3.5

$12=B

DC16-A

A817

255

2.2

GPI1=B

256

2.0

B=GPI1

257

2.4

B=A+1

260

2.4

B=A+1 (S)

261

2.4

B=A~1

262

2.4

B=A— 1 (S)

263

2.4

B=AX2

264

2.4

B=AX2(S)

265

2.4

B=A/2

266

2.4

B=A/2(S)

267

1.8

L=OVF

270

1.8

L=LNOT
HALT

271

272

2.4

A=B/2

273

2.4

A=B/2(S)

mmmmmmmmmm

D-5

15
16
17

20
21
22

23
24
25

26
27

30
31
32
33

Time

(Octal)

(usec)

Instruction

Evoke
Decoder No.

Evoke

Slot

Option

Decoder
Channel

274

—

275

DATI

DATO

276

2.3

TRU=A

277

2.3

TR L=A

—

CONDITIONAL JUMP INSTRUCTIONS (INPUT MULTIPLEXERI
Machine Code

Time

(0ctal)*

(usec)

MEMO

MEM1

Instruction

False

True

Multiplexer

No. **

Channel

300

301

2.0

3.2

GOTO

302

303

2.0

3.2

IF EXT1,

304

305

2.0

3.2

IF EXT2,

306

307

2.0

3.2

IF EXT3,

310

311

2.0

3.2

IF EXT4,

312

313

2.0

3.2

IF EXT5,

314

315

2.0

3.2

IF EXT6,

316

317

2.0

3.2

IF DZ,

320

321

2.0

3.2

IF DP,

322

323

2.0

3.2

IF DN,

‘11

324

325

2.0

3.2

IF OVF,

326

327

2.0

3.2

IF A<1>,

330

331

2.0

3.2

IF A<3>,

332

333

2.0

3.2

IF A<5>,

334

335

2.0

3.2

IF A<7>,

336

337

2.0

3.2

IF A<9>,

340

341

2.0

3.2

IF A<11>,

342

343

2.0

3.2

IF A<13>,

344

345

2.0

3.2

IF A<15>,

346

347

2.0

3.2

IF FF1,

350

351

2.0

3.2

IF FF2,

352

353

2.0

3.2

IF FF3,

354

355

2.0

3.2

IF FF4,

356

357

2.0

3.2

IF FF5,

360

361

2.0

3.2

IF FF6,

362

363

2.0

3.2

IF KFI,

364

365

2.0

3.2

IF PF1,

366

367

2.0

3.2

IF KF2,

370

371

2.0

3.2

IF PF2,

372

373

2.0

3.2

IF CLK,

300

301

2.0

3.2

GOTO

302

303

2.0

3.2

IF A<0>,

304

305

2.0

3.2

IF A<2>,

0-6

CONDITIONAL JUMP INSTRUCTIONS (INPUT MULTIPLEXERI (Cont)

Machine Code

Time

(0ctal)*

(usec)

Instruction

Multiplexer

No. **

Channel

MEMO

MEM1

False

True

306

307

2.0

3.2

IF A<4>,

310

311

2.0

3.2

IF A<6>,

312

313

2.0

3.2

IF A<8>,

314

315

2.0

3.2

IF A<10>,

316

317

2.0

3.2

IF A<12>,

320

321

2.0

3.2

IF A<14>,

322

323

2.0

3.2

IF B<0>,

324

325

2.0

3.2

IF B<15>,

326

327

2.0

3.2

IF EXT7,

330

331

2.0

3.2

IF EXT8,

332

333

2.0

3.2

IF EXT9,

334

335

2.0

3.2

IF EXT10,

336

337

2.0

3.2

IF EXT11,

340

341

2.0

3.2

IF EXT12,

342

343

2.0

3.2

IF EXT13,

344

345

2.0

3.2

IF EXT14,

346

347

2.0

3.2

IF EXT15,

350

351

2.0

3.2

IF EXT16,

352

353

2.0

3.2

IF EXT17,

354

355

2.0

3.2

IF EXT18,

356

357

2.0

3.2

IF EXT19,

360

361

2.0

3.2

IF EXT20,

362

363

2.0

3.2

IF EXT21,

364

365

2.0

3.2

IF EXT22,

366

367

2.0

3.2

IF L,

370

371

2.0

3.2

IF PWOK,

372

373

2.0

3.2

Not used

SUBROUTINE INSTRUCTIONS
Machine Code

Time

(Octal I

(#sec)

Instruction

374

3.2

CALL

375

3.2

CALL

376

3.2

EXIT

—

-—

Jump to a Subroutine in Memory 0
Jump to a Subroutine in Memory 1
Return from a Subroutine

*Codes are given for jumps into or within memory 1 and into or within memory 2. The least significant bit of the machine code is
the M (memory) bit.

“Multiplexer 1 (PC8160) Is optional and resides in slot A819 of the logic assembly. The MUXO and MUX1 commands are used to
select one or the other multiplexer.

D-7

PDPlé-M MAINTENANCE MANUAL

READER’S COMMENTS

DEC-16-HMMMA-A-D

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of
our

publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well

written‘ etc.? Is it easy to use?

What features are most useful?

What faults do you find with the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs?

Why?

Would you please indicate any factual errors you have found.

Please describe your position.
Name

Organization

Street

Department

City

State

Zip or Country

——

-—

—

——

DoNotTear-FoldHereandStaple-——

——

-——

——

—

FIRST CLASS
PERMIT NO. 33

MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES

Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
146 Main Street

Maynard, Massachusetts 01754

—

——

DIGITAL

Engflnan WORLD-WIDE

EQUIPMENT CORPORATION

SALES AND SERVICE

MAIN OFFICE AND PLANT
146 Main Street, Maynard. Massachusetts, USA, 01754 ' Telephone: From Metropolitan Boston: 646—8600
TWX: 710-347-0212 Cable: DIGITAL MAYN Telex: 94—8457

Elsewhere: (677}89751”

UNITED STATES
MID-ATLANTIC

NORTHEAST

REGIONAL OFFICE
275 Wyman Street. Waltham. Massachusetts (2154
TWX: 710-324-6919

Telephone: (617)—w0-0320/03w
WALTHAM

15 Lunda Street, Waltham, Massachusetts 02154
TWX: 710-324—6919
Telephone: (617)-891-1011)

CAMBRIDGE/BOSTON

Cambridge, Massachusetts 02139
TWX. 710-320-1167
Telephone. (617)-491-6130

899 Main Street.
ROCHESTER

130 Aliens Creek Road. Rochester, New York 14618
TWX- 710-253-3078
Telephone (716)-461-1700

CONNECTICUT
240 Pomeroy Ave. Meriden. Conn

Telephone' (203)—237~8441/7466

MID-ATLANTIC

06450
TWX

710-461-0054

SOUTHEAST

-——-

REGIONAL OFFICE:
US. Route 1. Princeton. New Jersey 08540

Telephone: (609)—452-2940

TWX: 510-685-2338

95 Cedar Lane. Engiewood. New Jersey 07631

Telephone: (201)-871-4984. (212)-594-6955. (212)-736-0447
TWX: 710-991-9721
NEW IERSEY
1259 Route 48. Parsippany. New Jersey 07054
TWX: 710-w7-B319
Telephone: (201)-335-3300

Telephone: (809) 452-2940

Ridgelake Drive. Suite 108
Metairie. Louisiana 70002

Knoxville, Tennessee 37919

ISLAND

Telephone:

TWX: 810-583-0123

Telephone: (615)-588-6571

REGIONAL OFFICE

REGIONAL OFFICE:

310 Sequel Way.

Sunnyvale, California 940$
Telephone: (408)-735-9200

1850 Frontage Road, Northbrook. lilinms 60062
TWX: 910-666-0655
Telephone: (312)-498-2500

ANAHEIM

PITTSBURGH

801 E. Ball Road, Anaheim. California 92805

400 Penn Center Boulevard

Telephone: (714)- 776- 6932/8733

Pittsburgh, Pennsylvania 15235
TWX: 710-797-$57
Telephone: (412)-243-9404

WEST LOS ANGELES
1510 Cotner Avenue, Los Angelee,
90025
TWX: 910-342-6999
Telephone. (213}-479-3791/4318

{SAN DIEGO
3444 Hancock Street

San Diego. California 92110
Telephone: (714)-298-0591. 0593

ANN ARBOR
230 Huron View Boulevard. Ann Arbor. Michigan 48103

1400 Terra Bella

Mountain View. California 94040
TWX: SIG-3731266
Telephone: (415)-WOO
PALO ALTO
560 San Antonio Rd. Palo Alto. California 94306

INDIANAPOLIS
—

MINNEAPOLIS

CLEVELAND

PHILADELPHIA

Station Square Three, Paoii. Pennsylvania 19301

Telephone: (415)-989-6200

Telephone: (215)—647-4900/4410

Telex: 510-668-8395

WASHINGTON
Executive Building
6811 Keniiworth Ave.. Riverdale. Maryland 20840
TWX: 710—826-9662
Telephone: (m1)-779-1600/752-8797

DURHAM/CHAPEL HILL:
2704 Chapel Hill Boulevard
J
Durham. North Carolina 27707
TWX: 510-927-0912
Telephone: (919)-489-3347

Missouri

TWX: 910-576-2818

Telephone: (415)-635-5453/7830

TWX: 910-356-7238

ALBUQUERQUE

3Progress

TWX: 910-373-1266

OAKLAND
7850 Edgewater Drive
Oakland. California 94621

South

6303 Indian School Road. NE.
Albuquerque. NM. 87110

Bldg. 35104 Euclid Ave.
Willoughby. Ohio 44094
TWX: 810-427-2818
Telephone: (216)—946-8484
ST. LOUIS
Suite 110 115

TWX: 910-335-1230

SAN FRANCISCO

TWX: 810-223-6053

Suite 6
Beachway Drive
Indianapolis. Indiana 46224
TWX. 810-341-34x
Telephone: (317)-2438341

TWX: 910-591-1189

Californa

CHICAGO
1850 Frontage Road. Northbrook. liiinois 60062
TWX: 910-686-0655
Telephone: (312)—498-2500

Park Hill

1 Huntington Quadrangle
Suite 1807 Huntington Station. New York 11746
Telephone: (516)694-4131. (212)-895—8195

504-837-0257

WEST

CENTRAL

Minneapolis. Minnesota.55420
Telephone: (612)-854-6562-3-4—5
TWX: 510-685-2338

CENTRAL (cont)
NEW ORLEANS
3100

Kingston Pike, Suite 21E

Suite 111. 8030 Cedar Avenue

PRINCETON
US. Route 1
Princeton. New Jersey 08540

‘

6311
‘

Telephone: (313)-761-1150

NEW YORK

LONG

SOUTHEAST (cont)

—

KNOXVILLE

Telephone: (505)-296-5411/5428

Telephone: (314)-878-4310

Denver. Colorado 80222

Telephone: (313)-757-3332/758-1656/750-1659

TWX: 910764-0831

TWX: 910-931-2650

DAYTON
3101 Kettering Blvd.. Dayton. Ohio 45439

Telephone: (513)-299-7377

TWX: 910-9w-0614

DENVER
2375 South Colorado Blvd. Suite #5

Pky.. Maryland Heights.

SEATTLE
1521 131th NE. Bellevue, Washington saws
TWX: 910—443-2316
Telephone: (206)—454-4058/455—5404

TWX: 810-459-1676

SALT LAKE CITY

MILWAUKEE

431 South 3rd East. Salt
Lake City. Utah 84111
TWX: 910-925-5834
Telephone: (301)-328-9838

8531 W. Capitol Drive. Milwaukee, Wisconsin 53222

Telephone: (414)—463-9110

TWX: 910262-1199

ORLANDO

DALLAS

Suite 130.7001 Lake Ellenor Drive Orlando. Florida 32809
TWX: 8110—850-Om
Telephone: (315)-851—4450

8855 North Stemmons Freeway
Dallas. Texas 75247

ATLANTA
2815 Clearview Place. Suite 100.

Telephone. (214)- 638 4880

Atlanta. Georgia 30340

3417 Milam

Telephone: (404)-451-3734/375/373 TWX: 810-757-4223

Telephone:'(713)-524-2961

PHOENIX
4358 East Broadway Road

Phoenix, Arizona 5040

Telephone: (612) 266-3488

TWX: 910 861 4000
'

HOUSTON

Street. Suite A, Houston. Texas 77002
TWX: 910-681-1651

TWX: 9109504891
PORTLAND
Suite 168
5819 S.W. Canyon Court, Portland. Ore. 97221
Telephone: (503) 297-3761 /3765

INTERNATIONAL
EUROPEAN

HEADQUARTERS

Digital Equipment Corporation International Europe

81 Route de I'Aire
1211 Geneva 26. Switzerland

Telephone: 42 79 50

Telex

22 683

FRANCE
Equipment Digital S.A.R.L.

NEW ZEALAND
Digital Equipment Corporation Ltd

STOCKHOLM
Vretenvagen 2. S-171 54 Soina. Sweden
Telex: 170 50
Telephone: 98 13 90
Cable: Digmi Stockhotm

AUCKLA

Telex: 21336

Waldenmarthraneegate 845$
Oslo 1. Norwa

Telephone: 3719 85. 37 02 30

Telephone: (613)—257-2615
Telex: 166 43

DENMARK

Digital Equipment GmbH

Digital Equipment Corporation

MUNICH

COPENHAGEN

Vesterbrogade 140. 1620 Copenhagen V

5 Koein. Bismarckstrasse 7,

SWITZERLAND
Digital Equipment Corporation S.A.

Telex: 888-2269
Telephone: 0221-522181
Telegram: Flip Chip Koeln

81 Route de I'Aire

GENEVA
1211 Geneva 26. Switzerland

Telephone: 42 79 50

Telex. 22 683

ZURICH
Scheuchzerstrasse 21
CH—3006 Zurich. Switzerland

Digital Equipment Corporation

Ges.m.b.H

Marlahllferstraaae 115.1150 Vienna 15. Austria

Telephone. 85 51

Digital Equipment Co., Ltd.
UK. HEADQUARTERS

Arkwright Road. Reading, Berks.
Telephone: 07514-583555

Telex: 84327

READING
The Evening Post Building, Tessa Road
Reading. Berks.
BIRMINGHAM

29/31. Birmingham Road. Sutton Coldfield. Warwicks.
Telex: 337 060
Telephone: (0044) 21-355 5501

Telephone 01/60 35 66

Telex. 56059

ITALY
,

MILAN

Corso Garibaldi 49. 20121 Milano.

Telephone: 872 748 694 $4

Italy

Telex: 32515

EDINBURGH

Livingston.

NETHERLANDS

BARCELONA
Ataio lngeniaros S.A.. Ganduxer 76. Barcelona 6
Telephone: 221 44 fi

Digital Equipment Corporation Ttd.

Sir Winston Churchilliaan 370
RijswiJk/T he Hague. Netherlands

Telephone: 070-995-160

Telex: 32533

Cable: Digital.

Sydney

60 Park Street. South Melbourne. Victoria. 3205
Telex: W16
Telephone: “-142
PERTH

CHILE
Coaain Chile Ltda. (sales only)
Caaiiia 14588. Correc 15, Santiago

Telephone: $6713

Cable: COACHIL

JAPAN
TOKYO
Rikei Trading Co.. Ltd. (sales only)

Kozato-Kaikan Bldg.

Minato-Ku. Tokyo. Japan
Telex: 781—4208
Telephone: 5915246
Digital Equipment Corporation international
Kowa Building No. 17. Second Floor
27 Nishi-Azabu 1-Chome

Telex: AA9210

BRISBANE
1:9 Merivaie Street. South Brisbane

Minato-Ku. Tokyo. Japan

Telephone: 404-5894’6

Telex: TK-6428

PHILIPPINES
Stanford Computer
P.O. Box 1608

Corporation

416 Dasmarinas St.. Manila
Telex: 742-0352
Telephone: 49—68-96

INDIA

BRUSSELS

Digital Equipment N.V./S.A.

ADELAIDE

we Rue D'Arion
1040 Brussels. Belgium

6 Montrose Avenue

Telephone: 02-13256

Telex: 012-2284

No. 18-14. Niahiahimbashi 1-chome

MELBOURNE

Queensland. Australia 4101
Telex: WIS
Telephone 444-047

BELGIUM

ARGENTINA
BUENOS AIRES
Coasin SA.
Virrey del Fine 4071. Buenos Aires

SANTIAGO

AUSTRALIA
Digital Equipment Australia Pty. Ltd.

Telephone: 214-993

Digital Equipment N.V.

Avenue

Vancouver 9. British Columbia. Canada
TWX: 610929-2006
Telephone: (604)-736-5616

CARACAS
Coasin SA. (Sales only)
Apartado 50939
Salana Grande No. 1. Caracas
Cable: iNSTRUVEN
Telephone: 72-9637

643 Murray Street
West Perth. Western Australia 6115

THE HAGUE

TWX: 610-831-2248

VENEZUELA

SYDNEY

Shiei House. Craigshili.

2210 West 12th

Telephone: 52—3185

PO. Box 491. Crows Nest
N,S.W. Australia 5065
Telex: AA2074)
Telephone: 439-2566

West Lothian, Scotland
Telephone: 32715 I Telex: 727113

Telephone: (403)-434-9333

MADRID

MANCHESTER

LONDON

EDMONTON
5531
103 Street
Edmonton, Alberta, Canada

Ataio Ingenieroa S.A.. Enrigue Least: 12, Madrid 16
Telephone: 215 35 43 / Telex: 27249

13 Upper Precinct. Walkden. Manchester M28 5A2
Telex: 668666
Telephone: 061-790-8411

Biiton House. Uxbridge Road. Ealing. London W.5.
Telex: 22371
Telephone 01-579-2334

Dorvai. Quebec. Canada 760
TWX: 610-422-4124
Telephone: 514-636-9393

VANCOUVER

SPAIN

UNITED KINGDOM

TWX: 610-492-4306

MONTREAL

Digital Equipment at Canada. Ltd,

Digital Equipment S.p.A.

AUSTRIA

Telephone: (416)274-1241
9675 Cote de Liesse Road

FRANKFURT
6078 Neu-Isenburg 2

HANNOVER
3 Hannovar. Podbielakletraase 1m
Telex: 922-952
Telephone: 0511-69-70-95

TWX: 610-562-w07

TORONTO
230 Lakeshore Road East. Port Credit. Ontario

8 Muenchen 13. Wallensteinplatz 2
Telex: 524-226
Telephone: (311-35031

Telex: 41-7682

TWX: 610-561-1651

OTTAWA
120 Holland Street. Ottawa 3, Ontario KIY 0X7

Telephone: (613)-725-2193

GERMANY

Telephone: 06102-5526

150 Rosamond Street. Carleton Place. Ontario

GRENOBLE

Am Forethaus Gravenbruch 5-7

Telephone:

CANADIAN HEADQUARTERS

Service

10 rue Auguste Ravier. F-38 Grenoble. France
Telex: 32 882 F (Code 212)
Telephone: (76’) 87 87 32

COLOGNE

Auckland, New Zealand

Digital Equipment 01 Canada, Ltd.

OSLO
c/o FIrma

Hilton House. 43) Queen Street Box 2471 A,

CANADA

NORWAY
Digital Equipment

327 Rue de Charanton. 75 Paris 12 "I. France

Telephone. 34436-07

SWEDEN
Digital Equipment Aktieboiag

Telex: 2587

Norwood, South Australia 5157
Telex: AA82825
Telephone: 631-339

H.S. Sonawala Mg Director (Sales Only)
HINDITRON SERVICES PUT LTD.
69/A Nepean Sea Road
Bombay, India