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DEC-14-HGZB-D

1972

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Document:	PDP-14 Maintenance Manual
Order Number:	DEC-14-HGZB-D
Revision:	000
Pages:	164
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DEC-14-HGZB-D

MAINTENANCE MANUAL

digital equipment corporation • maynard nnassachusetts

1st Edition March,

1970

2nd Edition July, 1972

The material in this manual is for informational

purposes and is subject to change without

notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDF

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS

Page

CHAPTER 1

GENERAL INFORMATION

1.1

General

2.3.2

System Description

1-1

1.2.1

Purpose and Use

1-1

1.2.2

Stand-Alone Applications

1-1

i.2.3

Monitoring Applications

1-1

1.2.4

Interactive Applications

1-1

1.2.5

Operating Concepts

1-2

1.3

Equipment Description

1-2

1.3.1

General
Control Unit Mainframe

1-4

1.3.2.1

Power Supply Filter Assembly

1-4

1.3.2.2

Power Supply

1-4

1.3.2.3

Read-Only Memory

1-4

Control Unit

1-4
1-5

1.3.5

O Boxes
A Boxes

1-5

1.3.6

Storage Module

1-5

1.3.4

1.3.7

Operating Summary
Specifications

1.4

CHAPTER 2

General

2-1

2.2

Maintenance Information

2-1

2.2.1

Maintenance Philosophy

2-1

2.2.2

Controller Description

2-1

2.2.2.1

ROM

2-1

2.2.2.3

Boxes BX14-DA and BX14-DD

2-3

2.2.2.5

A Box

2-4

2.2.3

Recommended Test Equipment

2-5

2.2.4

Recommended Spare Parts

2-5

2-9

2.3.6

Fault Isolation For Equations Involving Timer Functions

2-9

2.3.7

Fault Isolation For Equations Involving Retentive Memory Factors

2-9

A Box Storage Functions

2.3.8

Fault Isolation For Equations Involving

2.3.9

Fault Isolation For Major System Failure

2-11

2.3.10

Troubleshooting Hints and Kinks

2-11

2.3.1

Module Substitution and Replacement Notes

2-11

2.3.12

Mainframe Replacement

2-11

2.3.13

Power Supply Replacement

2.3.14

2.3.15

A Box Replacement

2-11

2.4

Fault Isolation With A Computer

2-11

2.4.

Fault Isolation Approach

2-11

2.4.2

Connecting a Computer

2-13

2.4.3

Loading of Binary (BIN) Loader Tape (DEC-08-LBAA-PM)

2-16

2.4.4

Loading of Diagnostic Tapes

2-16

2.4.5

Control Unit Fault Isolation Using TEST-1

2-16

2.4.6

Control Unit I/O Interface Fault Isolation Using TEST-1

2-19

2.4.7

Output Fault Isolation Using TEST-1

2-19

2.4.8

ROM Fault Isolation Usmg VER-14 (MAINDEC-14-DlAB-D)

2-20

2.4.9

Accessory Box Fault Isolation Using ABE-1 4 (MAINDEC-1 4-D8AB-D)

2-21

2.4. 1

Fault Isolation Using ROL- 1

2-22

CHAPTER 3

THEORY OF OPERATION

3.1

General

3-1

3.2

System Relationships

3-1

3.2.1

Operating Configurations and Modes

3-1

3.2.2

Control Unit Block Diagram Description

3-1

2-11

O, and A Box Replacement

2-11

2-3

O Boxes BX14-DA and BY14-DD

2.3

Fault Isolation Example Number 2

2-1

2.2.2.4

2.3

2.3.5

1-5

Control Unit

2-9

1-5

USER MAINTENANCE

2.2.2.2

2-6

Fault Isolation Example Number 1

1-4

Boxes

1.3.3

Input and Output Assignment Tables

2.3.4

1-2

1.3.2

1.3.2.4

2-6

2.3.3
1-1

1.2

Input and Output Organization

Fault Isolation Without a Computer

2-5

General Approach

2-5

3.2.2.1

General

3-1

3.2.2.2

Bus Arrangement and Internal Transfers

3-1

3.2.2.3

Registers

3-2

3.2.2.4

I/O Interface

3-2

3.2.2.5

Computer Interface

3-2

CONTENTS (Cont)
Page

Page

3.2.2.6

Control

3-2

3.5.7

Instruction Decoding and Register Control

3.2.3

ROM Block Diagram Description

3-2

3.5.8

I/O Interface Circuits

3-15

3.2.4

Box Block Diagram Description

3-2

3.5.8.1

General

3-15

O Box Block Diagram Description
A Box Description

3-3

3.5.8.2

Input Tests

3-16

3-4

3.5.8.3

Output Tests

3-16

3.3

Instruction Set

3-4

3.5.8.4

Output Functions

3-16

3 3.1

General

3-4

3.5.9

Conditional Jum" Circuits

3-16

3.3.2

Internal Mode Instruction Set

3-4

3.5.10

Computer Interface

3-16

General

3-16

3.2.5

3.2.6

3-15

3.3.2.1

General

3-4

3.5.10.1

3.3.2.2

Test Instructions

3-4

3.5.10.2

Device Selector Logic

3-17

Decision Instructions

3-5

3.5.10.3

Skip Bus

3-17

Interrupt Operation

3-17
3-18

3.3.2.3

3.3.2.4

Operate Instructions

3-6

3.5.1 0.4

3.3.2.5

Monitoring Instructions

3-6

3.5.1 0.5

External Mode Operation

3.3.2.6

Housekeeping Instructions

3-6

3.6

3.3.3

lOT Instructions

3-6

3.6.1

Input Circuits

3-19

3.3.4

External Mode Instructions

3-9

3.6.1 .1

3-19

3.4

Instruction Flow

3-9

3.6.1.2

AC Input Converter
DC Input Converter

3.4.1

General

3-9

3.6.2

Output Circuits

3.4.2

3-9

3.6.2.1

Isolated

3-9

3.6.2.2

DC Output Driver

3-20

3-9

3.6.3

Acces«3ry Box Circuits

3-20

3.4.5

FETCH Cycle for Internal Mode
FETCH Cycle for Interrupt Mode
FETCH Cycle for External Mode Operation
EXECUTE Cycle

3-9

3.6.3.1

Timer Circuits

3-20

3.5

Logic and Circuit Description

3-10

3.6.3.2

K274 Retentive Memory

3-21

3.5.1

General

3-10

3.5.2

Initialization

3-10

CHAPTER 4

DETAILED MAINTENANCE

3.5.3

Manual Controls

3-11

3.5.4

Major States and Timing

3-11

3.4.3

3.4.4

3.5.4.1

General

3-11

3.5.4.3
3.5.5

Major Registers

3-12

3.5.5.1

General

3-12

3.5.5.2

Program Counter 1 (PCI)

3-12

Program Counter 2 (PC2)

3-13

3.5.5.4

Memory Buffer

3-13

Instruction Register (IR)

Input Register

3-13

3.5.5.7

Output Register

3-13

3.5 .5 .8

Memory Port Buffer

3-13

3.5.6

ROM Circuits

3-13

3.5.6.1

General

3-13

3.5.6.2

Address Selection

3-13

3.5.6.3

Timing Circuits

3-13

Data Sense Circuits

3-19

4.1

General

4-1

Level of Maintenance

4-1

4.2.

Personnel Intended to Use This Chapter

4-1

4.2.2

Relationship to Other Chapters

4-1

4.3

Tools and Test Equipment

4-1

4.4

System Checkout

4-1

4.4.

Power Voltage Checks

4-1

4.4.2

Power Supply Ripple Check

4-1

4.4.3

Power-up Sequence and Manual Controls

4-1

4.4.3.1

Power-up Sequence

4-1

4.4.3.2

Manual Controls Check

4-2

3-13

3.5.5.6

3.5.6.4

3-19

4.2

3-12

3.5.5 .3

3.5 .5 .5

AC Switch

3-19

3-11

FETCH Cycle
EXECUTE Cycle

3.5.4.2

O, and A Box Circuit Description

4.4.4

Processor Timing Checks

4-2

4.4.4.

General

4-2

4.4.4.2

Processor Timing Assumptions

4-2

4.4.4.3

Detailed Timing Analysis (FETCH Cycle)

4-3

4.4.4.4

Detailed Timing Analysis (EXECUTE Cycle: JFF, JFN, SKE,

4.4.4.5

Detailed Timing Analysis (Two-word EXECUTE Cycle: JMP,

SKZ, TRR, NOP, JMR, and SKP)
3-13

JMS, and TRM Instructions)

4-3

4-4

CONTENTS (Cont)
Page

Page
4.4 .4.

Detailed Timing Analysis (I/O Execution

TXD TYD S YF
,

APPENDIX A PDP-1 4 SIGNAL GLOSSARY

A-1

APPENDIX B REFERENCE DRAWINGS

B-1

4-4

4.4.5

SYN, TXF, TXN, TYF, and TYN)
Memory Timing Checks

4-5

4.4.6

I/O Timing Checks and Notes

4-5

4.4.7

Computer Interface Check

4-5

4.4.7.1

Running Standard DEC Software on the Serial-Line Interface

4-6

4.4.8

Scope Loops and How You Get Them

4-7

4.4.8.1

General

4-7

4.4.8.2

Procedure

4-7

4.5

I/O Troubleshooting

4-7

4.5.1

Test True

4-7

4.5.2

Sample Return Troubleshooting

4-7

1-1

Stand-Alone Application

1-1

4.5 .3

Address Line Troubleshooting

4-8

1-2

Monitored Application

1-1

4.5.3.1

Address Line 1

4-8

1-3

Interactive Application

1-1

4.5.3.2

Address Line 2

4-8

1-4

PDP-14 Program Execution Cycle

1-2

4.5.3.3

Address Line 4

4-8

1-5

Typical PDP-14 Control System

1-3

4.5.3.4

Address Line 8

4-8

1 -6

PDP- 1 4 Control System

1-4

4.5.4

Package Select Lines

4-8

1-7

Power Supply Connections

4.5 .5

Only One Address Fails

4-8

2-1

PDP-14 Mainframe Showing Module Locations

2-2

4.5.6

Set and Reset Lines

4-8

2-2

Box Layout and Hierarchy

2-3

4.5.7

Clear Lines

4-9

2-3

O Box Layout and Hierarchy

2-4

4.5.8

A Box

4-9

2-4

A Box Layout and Hierarchy

2-5

4.6

Timer Adjustment

4-9

2-5

User Maintenance Steps

2-6

4.6.1

Timer Adjustment With a Computer

4-9

2-6

Input/Output Relationships

2-7

4.6.2

Timer Adjustment Without a Computer

4-9

2-7

Decision Diagram, Fault Isolation Example Number 1

2-8

4.7

Memory Troubleshooting

4-9

2-8

Decision Diagram, Fault Isolation Example Number 2

2-9

4.7.1

General

4-9

2-9

Decision Diagram, Fault Isolation for Equations Involving Timer

4.7.2

4-10

4.7.2.2

No Memory Output
No Memory Output and Processor is Halting
No Memory Output and the Processor Continues to Run

4.7.3

One Bit in Every Word Set or Cleared

4.7.4
4.7.5

ILLUSTRATIONS
Figure No.

Title

Page

Functions

2-10

2-1

K302 Timer Components

2-11

4-10

2-1

Decision Diagram, Fault Isolation for Major System Failure

2-12

4-10

2-12

Diagnostic Test Usage

2-13

One Bit in Every Eighth Word is Bad

4-10

2-13

M921 Connections for a Device Code of 16gOr 17g

2-13

Groups of Eight Words Bad

4-10

2-14

PDP-14 Cabling

2-14

4.7.6

STROBE 1 to STROBE 8

4-10

3-1

PDP-14 Control Unit, Block Diagram

3-1

4.7.7

Current Switches

4-11

3-2

Box Block Diagram

3-3

4.7.8

Matrix-Base Driver Transistors

4-11

3-3

One-Half Memory Select

4-11

O Box Block Diagram
A Box Block Diagram

3-3

4.7 .9

4.7.10

Field Select

4-11

3-5

Test Instructions

3-5

4.8

Troubleshooting and Repair Techniques

4-11

3-6

Decision Instructions

3-5

4.8.1

Logic Troubleshooting

4-11

3-7

Operate Instructions

3-6

4.8.2

Module (Circuit) Troubleshooting

4-11

3-8

TXD and TYD Instructions and Display Words

3-6

4.8.3

Repairs and. Replacements

4-12

3-9

Housekeeping Instructions

3-7

4.8.4

Validation Tests

4-12

3-10

lOT Instructions

3-8

4.7.2.1

4-10

3-4

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

3-1

Power Control Timing

3-10

3-1

Control Logic Timing

3-11

Title

Page

4-8

Memory Timing Checks (Paragraph 4.4.5)

4-5

4-9

I/O Timing Checks (Paragraph 4.4.6)

4-5

4-6

Delay and Pulser Operation

3-12

3-14

3-1

ROM Functional Diagram
ROM Timing Relationships
ROM Data Sense Circuits, Simplified Logic Diagram

3-15

3-1

Input Test Functional Diagram

3-17

3-1

PDP-1 4 Interrupt Mode Timing

3-18

3-1

Input Converter Circuits

3-19

3-20

3-21

AC Isolated Switch
DC Driver

3-22

Timer Module, Time Delay Circuit, Simplified Schematic Diagram
and Equivalent Logic Diagram

3-21

3-23

Timer Relationships

3-21

2-2

Spare Parts Recommended for a Typical Configuration

2-6

4-1

Startup Timing

4-2

2-3

RIM Loader

2-16

4-2

Manual Controls Check

4-2

2-4

Test Program Error Code/Module Location Cross Reference

2-18

4-3

Free-Running Multivibrator

4-2

2-5

Accessory Box Module/ ABE-14 Error Code Cross Reference

2-22

FETCH Cycle Timing Analysis (Paragraph 4.4.4.3)

4-3

3-1

PDP-1 4 Major Registers

3-2

4-5

Internal Execution (JFF, JFN, SKE, SKZ, TRR, NOP, JMR and

3-2

External Mode Instructions

3-9

4-1

Recommended Tools and Test Equipment

4-1

4-2

Short Patch for Computer Interface Checkout

4-6

4-3

I/O Fault Identification

4-7

4-4

Scope ijQop Program lOr lestmg an input or vjutput

4-8

4-5

ROM Fault Isolation

4-10

3-1
3-1
3-1

3-15

SKP) (Paragraph 4.4.4.4)
4-6

Two-Word Instruction Execution (JMS JMP, and TRM)
,

4-4

I/O Execution Cycle (TXN, TXF, TYN, TYF, TXD, TYD, SYN, and

SYF) (Paragraph 4.4.4.6)

PDP-8/PDP-1 4 Interface

Tape Flag for Counting Screwdriver Turns

4-9

4-12

Integrated Circuit Location

4-12

4-13

Integrated Circuit Pin Locations - Top View

4-12

TABLES
Table No.

4-4

(Paragraph 4.4.4.5)
4-7

4-10
4-11

3-20

Figure No.

4-4

Title

Rccuiiuiiciidcu Spaic raits by Majui Uiiiis

Page
2-3

INTRODUCTION

This manual contains instructions and drawings for maintaining the PDP-14 Programmable Controller manufactured by Digital Equipment Corporation, Maynard, Massachusetts.

The manual is organized into four chapters

for various levels of maintenance personnel.

Chapter 1 provides a brief description and specifications for the PDP-14 and is designed to give the reader a first
level introduction to the system.

Chapter 2 presents the first level maintenance philosophy and procedures to be used by maintenance personnel
assigned to the machine.

The techniques described are those of module swapping which, when systematically

performed, will correct most problems.
Chapters 3 and 4 are intended to be used by highly trained and qualified maintenance personnel. Chapter 3
explains the theory of operation and Chapter 4 outlines techniques to be used for fault isolation on a particular

module.

TEST-14/L, MAINDEC-14-D7LA-D-(D): Same as TEST-14 except for PDP-14/L.

ABE-14, MAINDEC-14-D8AB-D: This document contains the program listing and instructions for
loading, running, and interpreting the results of ABE-14. ABE-14 is a diagnostic program for testing
PDP-14 and PDP-14/L Accessory Boxes.

VER-14, MAINDEC-14-DlAB-D: This document contains the program Usting and instructions for
using VER-14. VER-14 is a program that verifies the contents and operation of a Read-Only Memory
(ROM).

LOAD-14, DEC-14-LZPB-D: This document contains the program Usting and instructions for
LOAD-14. LOAD-14 is used to enter a ROM program into the computer memory for verification by
VER-14.
ROL-14, DEC-14-MWZC-PB: This document contains the program Hsting and instructions for using
the ROL-14 program. ROL-14 is an interrogation and control program that can be used with an
on-line system for diagnostic tests.

REFERENCES
For additional information concerning the PDP-14, the PDP-14/L, or system-related equipment, refer to the

MAINTENANCE PHILOSOPHY
This manual contains two levels of maintenance instructions. The first level, designated User Maintenance, is

following DEC publications:

presented in Chapter 2 and is intended primarily for end user maintenance personnel. However, it should also be

PDP-14 Reference Card
PDP-14 User's Manual
Control Handbook
Small Computer Handbook

used as the first level of maintenance for DEC Field Service personnel. This level of maintenance assumes the
user is familiar with industrial control systems and basic electrical repair techniques but may not be familiar with

programmable controllers.
There are two primary divisions of user maintenance; one for fault isolation using module substitution techniques

SOFTWARE DOCUMENTATION

and a second for using computer diagnostics. In either case, only module replacement is recommended; repair of
the modules should only be attempted by quaUfied personnel.

The following diagnostic documentation is also provided by DEC:
TEST-14, MAINDEC-14-D7AB-D: This document contains the program hsting for TEST-14 plus
instructions for using the diagnostic program and interpreting its results.

prehensive test of the PDP-14 Processor, Input Boxes, and Output Boxes.

TEST-14 performs a com-

Detailed Maintenance is the second level of maintenance and is intended only for DEC Field Service personnel or
user personnel thoroughly trained in electronic repair (and solid-state digital repair techniques). This level is

intended primarily for module repair and is presented in Chapter 4.

vii

CHAPTER 1
GENERAL INFORMATION

1.1

GENERAL

1.2.3

This chapter defines the purpose of the PDP-14 Controller, Msts typical system applications, and describes the

major elements of the controller.

A summary of equipment specifications is also included at the end of the

Monitoring Applications

The PDP-14 can be connected to a small, general purpose computer such as the PDP-8/E for monitoring
(Figure 1-2).

The PDP-14 still performs control functions as described in Paragraph 1.2.2; however, it also

reports status information to the PDP-8/E.

chapter.

The PDP-8/E analyzes this data to determine if the machine is work-

ing properly and/or stores production information (e.g., piece counts, cycle times, scheduled tool changes, etc.).
1.2
1.2.1

SYSTEM DESCRIPTION
Purpose and Use

PDP-8/E
8/1 ,8/L

ROM

PDP-14

OR PDP-12

The PDP-14 Controller replaces conventional relay control systems in virtually all types of industrial applications

STATUS

CONTROL
OUTPUTS
STATUS
INPUTS

COMPUTER

MACHINE
OR PROCESS
CONTROL
SYSTEM

requiring high-reliability control operations. Typical uses include the PDP-14 as the controller for:

• Transfer and assembly lines

Figure 1-2 Monitored Application

• Machine tool systems
• Packaging and materials handUng systems
• Chemical mixing systems
• Elevator control systems

In other appUcations, the PDP-14 does not control machine operation (this function is provided by relays or

other control systems). Instead, the PDP-14 acts as an interface for the computer and tests inputs from the

The PDP-14 can control any operation or process sequence that comprises discrete steps and involves on/off
status inputs and on/off control outputs.

The controller can be used in a stand-alone application or can be used

with a computer in a monitoring application or an interactive application.

1.2.2

machine in an order defined by a ROM program (or by the computer) and provides the test results to the
computer. Since the PDP-14 does not control any outputs in this apphcation, it can be configured to accept up
to 512 discrete status inputs.

1.2.4

Stand- Alone Applications

Interactive Applications

When used in a stand-alone or independent application (Figure 1-1), the PDP-14 controls the machine or process

The PDP-14 can also be used with a small, general purpose computer in an interactive apphcation (Figure 1-3).

system operating sequence using a program in its Read-Only Memory (ROM). This program establishes the con-

In this application, the PDP-14 can provide the fundamental control for the machine and return status informa-

trol relationships between status inputs and control outputs.

tion to the computer.

provided by the PDP-14 or upon other information available to the computer (such as analog signals from a

Status inputs are provided as on/off inputs from machine

system pushbutton switches, limit switches, etc. The pro-

gram continually tests the status inputs (and outputs) and,

ROM

PDP-14

CONTROL
OUTPUTS
STATUS
INPUTS

MACHINE
OR PROCESS
CONTROL
SYSTEM

based upon the results, advances the control sequence by

measuring device).
CONTROL
PDP-8/E
8/I,8/L

turning outputs (to solenoids, motor starters, etc.) on or off.
In a stand-alone application, the PDP-14 can accept up to

The computer can then direct the control in the PDP-14 based upon the status information

OR PDP-12
COMPUTER

Figure 1-1

INSTRUCTIONS .

ROM

STATUS

PDP-14

CONTROL
OUTPUTS
STATUS
INPUTS

Stand- Alone Application

MACHINE
OR PROCESS

CONTROL
SYSTEM
14-0094

256 status inputs and can control up to 255 outputs.
Figure 1 -3 Interactive Application

1-1

1.2.5

A logical OR function could be represented as follows:

Operating Concepts

The controller directs the machine or process system sequence by solving input/output relationships, using a

Yl = XI + X2, where + signifies that either input (or both) can activate an output; i.e., a logical

program (a method or procedure for solving a problem) stored in its memory.

OR function.

Basically, this program defines

what outputs are to be turned on or off (and in what order or sequence) and what combinations of inputs (and
outputs) are to effect an output. In other words, the controller controls the machine or process system sequence

The "ladder diagram" for the above example is shown at the right.

by solving input/output equations.

For solution of this equation, both inputs need be tested only if

^-T^

the one checked first is off. Each Test instruction could be linked

The controller cannot directly react to an input (or output) change of state (on-to-off or off-to-on). Therefore,
it

must test the pertinent inputs (and outputs) many times a second and it must define the pertinent state of the

test.

to an Operate instruction (using a Decision instruction) if either

input is on.
14-012

With each test, the controller must decide whether to turn an output on or off before continuing the testing

The PDP-1 4 Controller has the capabilities for checking inputs

procedure. Following a valid test decision, the controller turns the output on or off, then continues testing.

(or outputs) for either an on or off state. In addition, there are other instructions to control sequences. There-

The above operations are all performed as discrete steps of a program. The smallest part of a program is called an
instruction.

The instruction is stored in a discrete memory location called an address.

action to be performed.

The controller uses three basic types of instructions:

fore, the control programs can be written in a number of ways.

It defines a single step or

Test, Decision, and Operate.

Test instruction defines the input (or output) to be tested and the applicable state (on or off).

To summarize, a typical PDP-1 4 control program is made up of a
series of instructions that are stored in a Read-Only Memory (ROM).

A Decision

instruction links the Test instructions with other Test instructions or with the Operate instructions. That is, for a
valid decision, either an Operate instruction can be performed to turn an output on or off, or another Test

instruction can be performed.

These instructions can be arranged in ^oups as shown in Figure 1 -4.

Each group of instructions solves a Boolean equation by testing

SOLVE

specific PDP-1 4 inputs and outputs and, at the end of the test, turns

OUTPUT

FOR
1

OFF
*

SET Y1

an output either on or off.

The basic logic operators (AND and OR) for solving input/output equations are inherent in the arrangement of
the Test, Decision, and Operate instructions.

The following example defines one way the controller might solve

an input/output equation.

The final instruction in the program is an unconditional jump instruction.

This instruction returns the PDP-1 4 to the first instruction in

the program and the program execution cycle is repeated. Thus, the

SOLVE
FOR
OUTPUT
2

Assume a machine motion requires two inputs; for example, POWER ON and START.

POWER ON is repre-

sented as XI (input 1), START as X2 (input 2), and the machine motion as Yl (output 1), then:

OFF

SET Y2

PDP-1 4 control program consists of a closed loop of instructions

which are executed every 1 5 to 60 milliseconds (the actual execution

1
f

time is dependent on the number of instructions in the program).
i

Yl = XI * X2, where * signifies both inputs are needed concurrently; i.e., a logical AND function.
1.3

SOLVE
FOR
OUTPUT

EQUIPMENT DESCRIPTION

The "ladder diagram" for the above example is shown at the right.
1.3.1

General

OFF

SETY20

For solution of this equation, the controller could test input XI
for an on condition. It could then examine the test result with a

Decision instruction. If XI is off, there is no need to test input

POWER
ON

X2; therefore, the controller can continue the program by testing

START

—o o
X2

other equations. Input XI would then be tested again on the next

complete cycle through memory.

If, however,

XI is on, the

A PDP-1 4 Controller comprises the four major assemblies that are

identified in Figure 1-5. Figure 1-6 depicts the functional relationships

In a typical control application, the PDP-1 4 Controller consists of a
,4-t

Control Unit, a Read-Only Memory (ROM), Input (I), Output (O),

and Accessory (A) Boxes. The Control Unit is fundamentally the
for X2. This Test instruction could then be followed with another

Decision instruction. If X2 is off, the controller returns to other testing. If X2 is on, however, the program is

Y to cause machine motion.

heart of the controller.

NOTE
identified with the letter Y.

Execution Cycle

from manual control inputs, the stored program, input (or output) test

controlling a machine or process system.

by the controller.

Similarly,

The ROM stores the program for evaluating status inputs and

An I Box converts machine or process system inputs into signals usable

O Boxes convert controller outputs into signals usable by the machine or process

system. Accessory (A) Boxes provide timer functions, storage functions during normal operation, and special
storage functions during power-off conditions.

1-2

Figure 1-4 PDP-1 4 Program

It directs and coordinates the overall operation

results, or information supplied by a computer.

Inputs are always identified with the letter X; outputs are always

GO TO Yl

of the major assemblies that are described in subsequent paragraphs.

Decision instruction could hnk the program to a Test instruction

linked to an Operate instruction that turns on output

ON
i

COMPUTER
POWER SUPPLY

INTERFACE CABLES

I BOX
CABLE

PDP-14

MAINFRAME
WITH COVER
REMOVED

BOX
CABLE
PDP-14

MAINFRAME

•

M ^Hl'

•

* "

STORAGE
MODULE

CONTROL
UNIT

SLOTS FOR ROM
BANKS 2, 3, 84

Figure 1-5 Typical PDP-14 Control System

1-3

CONTROL UNIT
MAINFRAME

ROM
(READ-ONLY
MEMORY)

POWER SUPPLY

NO.l

NO. 2

8
7
1

)

I
BOXES

nilTPIIT

ADDRESS

INPUTS „

INPUT
SAMPLE RETURN

CONTROL

1
'

ADDRESS

AC OR DC
OUTPUTS K

SET, RESET,

6
.

115

VAC

MACHINE

\0R

/PROCESS

BOXES

OR CLEAR

SYSTEM

GND

+ 5V

UNIT

COMPUTER <

INSTR.

INPUT

AC OR DC

MACHINE
OR
PROCESS
SYSTEM

ADDRESS

N
Figure 1 -7 Power Supply Connections
+ 5V

POWER
SUPPLY
1

BOXES

The ROM is a passive device; i.e., it provides an instruction only when requested by the Control Unit.

OUTPUT, SAMPLE RETURN

In its

maximum configuration, the ROM provides the capability for storing up to 4096 instructions; therefore the
14-0095

Control Unit must be capable of addressing 4096 locations.
Figure 1-6

PDP-1 4 Control System

The ROM is not interchangeable with ROM units used in other PDP-1 4 control systems.

It is functionally

equivalent to the interconnections in a relay control system, and as such, is specifically programmed (wired) for

each application.
1.3.2 Control Unit Mainfram e

Control Unit - The Control Unit directs the operation of the controller based upon manual inputs,

The control unit mainframe consists of a heavy steel frame that is hinged to a mounting base frame (Figure 1-5).

1.3.2.4

The mainframe contains a low-voltage power supply (or supplies), module sockets for Control Unit and Read-

program instructions, test results, or information provided by a computer.

only Memory (ROM) logic, and module sockets for Input (I) Box, Output (O) Box, and Accessory (A) Box connectors.

It interfaces with the

ROM, all I, O,

and A Boxes, and the computer.

The Control Unit begins operation by initializing the controller (placing its circuits in a state for starting operation).

Power Supply Filter Assembly - This assembly contains an input power terminal strip, a utility recep-

1 .3.2.1

Next, it addresses the first

ROM location and fetches an instruction. The Control Unit interprets (decodes)

then performs (executes) the instruction.

ON/OFF switch, and a 2A line fuse. The assembly also contains two manual control switches. The
START/STOP switch, as the name implies, starts or stops the controller's timing circuits. The CONTINUE

Instruction execution can entail testing an input or output, making a decision, or turning an output on or off.

switch sllo WS tll.6 COntrollsr iO- r es tirrt f^ firVfirfltJon at t Vlf T>oint it Twa^ gtf>Ti'nf*<^

After executing an instruction, the Control Unit repeats the cycle by fetching another instruction.

tacle, an

n f>/Mi tract

a otnrt rtr^ornt-trt n r- n iicr^c

the program to begin at its initial step. These manual switches are not used during normal operation or trouble-

For a Test Input instruction, the Control Unit addresses the input circuit. The input circuit responds by providing

shooting.

the on/off state of the input to the Control Unit on the input sample return hne.

The Control Unit temporarily

stores this information. It then fetches another instruction to evaluate the input.

1.3.2.2

Power Supply — The +5V power supply provides the operating potential for logic circuit operation.

The supply operates from a 105 to 125 Vac (or 210 to 250 Vac), 47 to 500 Hz source.

It provides a nominal

+5 Vdc at 7A. The power supply is short-circuit proof and provides over-load protection for logic circuits.

An identical operation is performed for a Test Output instruction. For an Operate instruction, however, the
Control Unit also specifies the function to be performed; i.e., whether an output is to be turned on (SET) or off

(RESET), or whether all outputs are to be turned off (CLEARED).

Two power supplies are required for controller configurations having load currents in excess of 7A. These
supplies are connected in parallel as shown in Figure 1-7.

1 .3.2.3

Read-Only Memory - The PDP-1 4 Memory stores a program that defines the machine system operating

sequence. The memory is termed "read-only" because it cannot be altered electrically (i.e., written on).

1.3.3

An I Box accepts on/off status inputs from the machine or process system and converts them into logic levels
usable by the controller.
I

A machine program consists of many discrete steps called instructions. Each instruction is stored in a discrete
ROM location called an address and is retrieved (fetched) from memory by Control Unit action. When executed

I Boxes

Each I Box is capable of accepting up to 32 ac or dc inputs (but not both). Up to eight

Boxes can be used in a typical control appUcation for a total of 256 inputs. Machine inputs are connected to

screw terminals on the front of I Box modules. Control cables (one from each I Box) connect the I Boxes with
the Control Unit.

by the Control Unit, an instruction causes the controller to perform a single action such as testing an input or
turning on an output.

A Test Input instruction defines the input to be tested and the state (on or ofO- When the controller executes
one of these instructions, the Control Unit sends an input address (for selecting one of 32 inputs) to the I Boxes

1-4

and selects one of eight possible I Boxes. The selected I Box, in turn, decodes the address and selects two input
circuits.

Information from the selected input circuits is then provided on two sample return lines and the PDP-14

Control Unit must determine which sample return is vaUd.

1.3.6

Storage functions can be provided by elements in the Control Unit as well as the A Box.

be installed in the Control Unit O Box connector slots.
1

1.3.4

Storage Module

It provides

A storage module can

6 storage outputs but precludes the use of

6 "real" outputs. The storage module is addressed in the same manner as "real" outputs.

O Boxes

An O Box converts controller logic levels into outputs used by machine or process system load circuits (such as
indicators, solenoids, motor starters, etc.). Up to sixteen outputs can be handled by one O Box. These outputs
can be either ac or dc (but not both). Up to sixteen O Boxes can be used in an application for a total of 255
outputs (the last output address, 256, is reserved for a special function). Output connections are provided by

screw terminals on the output modules. Control cables (one from each O Box) connect the O Boxes to the

Operating Summary

A Test instruction defines whether an input or output is to be tested, the state (on or off) to be checked, and
which input or output (address). For a Test Input instruction, the Control Unit provides the input address
selection code to the I Boxes.

The state of the applicable input is then provided to the Control Unit on the input

sample return line. The Control Unit temporarily stores this state, then fetches another instruction from the

Control Unit.

ROM.

An output can be turned on or off or tested for an on or off state by the program instructions. These instructions
define the output and the function to be executed. When the controller executes one of these instructions, the
Control Unit addresses the output and defines the function. An output is turned on by a SET function and
remains on until turned off by a RESET or CLEAR function. For testing of an output, the Control Unit simply
addresses the output. In return, the

1.3.7

O Box provides the state of the addressed output to the Control Unit on the

A Test Input instruction can be followed by a Decision instruction. This instruction compares the test result
with a programmed state (on or off). Based upon the comparison, the program can branch to:
on; 2) turn an output off; or 3) continue testing. This branching defines the next

ROM address.

Following the above action, the Control Unit fetches the next instruction from the specified ROM address and

decodes the instruction.

output sample return line.

1) turn an output

An Operate instruction defines the output function and the output address. For an

Operate instruction, the Control Unit provides the output address selection code to the O and A Boxes.
1.3.5

It also

specifies a timi-on (SET) or turn-off (RESET) function. If a "real" output is specified, an output is provided to

A Boxes

the machine or process system.

An A Box is a special purpose assembly that provides timer, retentive memory, and storage functions. An A Box
requires one O Box cable slot in the mainframe and thus precludes the use of 1 6 output drivers.

The A Box uses

the same addressing logic and instructions as the O Box.

As the above operation continues, only pertinent portions of the ROM program are used (as determined by pro-

gram branching). When the end of a ROM cycle is reached, the operation recycles.

If no input (or output)

states have changed since the last test, the program will follow the same memory path. If, however, input or

Up to 16 timer (or delay) circuits can be used in an A Box. The circuits are packaged two per board. Each timer

output conditions have changed, program branching will cause a different path through the ROM, thereby

circuit can provide a delay interval from 0.01 seconds to approximately 3 minutes. Each timer has an associated

changing the output states.

storage register (flip-flop) that is turned on (SET) or off (RESET) by program instructions.

When set, this flip-

flop starts the delay interval. After the timeout interval, the timer is considered on with respect to testing.

timer must be turned off (RESET) before it can be used again.

A program instruction or an initiahze operation

As mentioned previously, A Boxes permit the use of timers, retentive memories, or storage elements. Outputs
provided by these elements do not directly control system outputs and are not considered "real" outputs.

Accessory (A) Boxes use the same instruction and address selection scheme as O Boxes.

resets the associated flip-flop to implement this action.

A retentive memory is a device that retains its state during power shutdown, power-off, or power-up conditions.

1.4

SPEaPICATIGNS

Its principal use is to record a critical action or event and to retain the state corresponding to the event even

though power is lost. Thus, its output can be used as a reference point when power is restored.

Overall System

Two types of retentive memory modules are available. The K274 module provides two retentive memories (with
indicator Ughts). The retentive memories are addressed in the same manner as outputs. Up to 16 retentive
memories can be accommodated in one A Box by using K274 modules. The K272 module provides one retentive

Number of Inputs:

memory and only uses the even-numbered addresses on the right side of the A Box. Therefore, up to four retentive memories can be accommodated in an A Box by using K272 modules.

Type of Inputs:

ac or dc

Number of Outputs:

Up to 255 (sixteen O Boxes with sixteen outputs each;

512 inputs by decreasing output capabiUty accordingly.

output address 256 is reserved for clearing all outputs).

Each retentive memory has an associated control flip-flop. Each memory is turned on (SET) or off (RESET) by
program instructions and is unaffected by an initialize operation.

Unused timer or retentive memory module slots can be used for storage outputs.

A storage module is inserted

in the vacant slots to connect the output of two storage register flip-flops to the output sample return line.

Up to 256 (eight I Boxes with 32 inputs each). Further
expansion in units of 32 is possible up to a maximum of

Type of Outputs:

ac or dc

Average Instruction Execution Time:

20 lis ± 20%

ROM Capacity:

1024 to 4096 12-bit instruction words in increments of
1

024 words.

1-5

*Average ROM Program Execution Times
for Program Usage:

15 ms

30 ms

45 ms

60 ms

Environmental:
Operating Temperature

BY14-DA Output (O) Box
Number of Outputs:
Output Voltage and Drive:

6 (with indicators)

15 Vac; 500 VA (maximum) per output or a distributed

maximum of 1000 VA per 1/4 O Box.

0° to 70°C (32° to 160°F) at controller; 0° to 55°C

(32° to 1 30°F) ambient (outside enclosure).

BY14-DD Output (O) Box
Relative Humidity

Vibration

Other

Number of Outputs:

three normal axes.

Output Voltage:

10 to 250 Vdc (dc switched to ground)

Designed for NEMA 1 2 enclosure.

Output Current:

Output Saturation Voltage:

2.5

1.25 g's (maximum);

to 100 Hz (sinusoidal) in each of

Power Requirements:
Voltage

105 to 125 Vac or 210 to 250 Vac

Frequency

47 to 500 Hz

Wattage

86W (average power dissipation for maximum system

6 (with indicators)

A (maximum) for each circuit
V (maximum)

BAM Accessory (A) Box
*Number of Retentive Memories:

16 maximum using the K274 module (2 memories per

module)

using ac inputs and outputs)

module)

BX14-DA Input (I) Box
Number of Inputs:

32 (with indicators)

Input Voltage and Loading:

115 Vac @ 1.5 VA

Input Threshold:

100 Vac (minimum)

Response:

16 to 32 ms for K578A usage; 8 ms (minimum) for

*Number of Timers:
Timer Intervals:

6 maximum (2 timers per K302 module)

0.01 to 30 sec (standard).

Up to 4 min, 45 sec with

additional resistance.
* Storage Outputs:

16 maximum (2 outputs per K022 module)

BF14-M Storage Module

K578B usage.

Storage Outputs:

BX14-SA Input (I) Box

16 non-active outputs. Plugs into PDP-14 mainframe in
place of an ac or dc Output Box.

Number of Inputs:

32 (with LED indicators)

Input Voltage and Loading:

115 Vac@ 1.5 VA

Input Threshold:
Response:

8 to 1 2 ms

BX14-DD Input (I) Box
Number of Inputs:
Input Voltage Range:

32 (with indicators)
10 to 55 Vdc (above 55 Vdc with external series resistor
at 50 olims per volt)

Input Voltage and Current (typical):

12 Vdc @ 10

24 Vdc @ 10 or 30 mA
48 Vdc @ 20 mA
Response Time:

2 ms excluding contact bounce

Bounce Rejection:

will reject up to a 3-ms bounce

*Based upon a IQ-jXs instniotion execution time and 75% usage of program instructions.

1-6

*One A Box can accommodate various combinations of up to eight retentive memory, timer, and storage modules (Figure 2-4).

CHAPTER 2
USER MAINTENANCE

the binary content of eight 1 2-bit instructions. (If the wire is routed through the transformer, it results
in a logical 1 for the pertinent bit when the wire is pulsed; if the wire is routed around, it results in a

GENERAL

2.1

This chapter contains instructions that enable user personnel to maintain the PDP-1 4 Controller; they are also

logical

intended as the first level of maintenance for field service personnel. The chapter has three primary divisions:

system; i.e., it

The braid arrangement is functionally equivalent to the wiring in a conventional control
forms a list of permanently wired instructions that define the control operation. Once
it is encapsulated for immunity to accidental change. The module is then attached
formed,
braid
is
the
module
to form one plug-in assembly.
the
to
G923

Maintenance Information — 1) defines the maintenance philosophy; 2) briefly describes the controller
units and functional relationships; and 3) lists the recommended test equipment and spares.

The G923 module decodes three bits of address to select one of eight groups of sense amplifiers. Each
group consists of 1 2 sense amplifiers or one for each bit in an instruction. This selection (in conjunction
with that of the G924) selects one 1 2-bit instruction out of 1 024 possible instructions ( 1 28 wires x

Fault Isolation and Repair Without A Computer — provides the recommended approach and procedures
for isolating and repairing the PDP-1 4.

Fault Isolation and Repair With

bit).

8 instructions per wire).

A Computer — provides the procedure for using computer diagnostics

The selected instruction is made available to the Control Unit when the G924

module notifies the Control Unit that an instruction cycle is completed.

and for repair of the PDP-1 4.

NOTE
The information content of each G922 module is unique; there-

MAINTENANCE INFORMATION

2.2

fore, do not substitute this plug-in assembly.

Maintenance Philosophy

2.2.1

2.2.2.2

The PDP-1 4 requires no periodic maintenance or adjustments and, therefore, no scheduled downtime.

From a

If the PDP-14 cannot be fixed by module

replacement, replace the next larger assembly or contact your DEC Field Service representative. Module repair

should only be attempted by personnel thoroughly trained in electronics and digital repair techniques.

2.2.2

It consists of a

Controller.

maximum configuration is shown; a number of the modules (and connectors) axe required only if the controller
interfaces with a computer.

ControDer Description

ROM - A ROM (Read-Only Memory) stores the program instructions for implementing a machine or
process system sequence. A ROM can be comprised of up to four banks as shown in Figure 2-1 Each ROM bank
2.2.2.1

Senses power-up and power-down conditions, initializes the system, and starts system timing.

Interfaces with the START/STOP and CONTINUE switches to provide manual control.

Detects timing failures and holds the system in an initialize state.

Decodes two bits of the memory address to enable one out of four possible ROM banks.

Provides control (and three bits) for Test and Display instructions used for computer monitoring.

Each bank can store

up to 1024 12-bit instructions. The functions provided by each module are described below:
a.

address selection, the Control Unit enables one memory bank and provides a 10-bit address and a

selected group of sense amplifiers to load an instruction in its output buffer. It then notifies the
d.

Control Unit that the memory cycle is complete.

G922 ROM Braid and G923 Sense Amplifier - The G922 module contains a pattern or braid of 1 28
wires.

Each wire is routed either through or around 96 (8 sets of 1 2) Ferrite-core transformers to form

Decoding of instructions
Execution of instructions

Sampling and storing input or output test results

M747 Program Counter 1 (PCI) - Two M747 modules comprise PC 1

This register addresses the

ROM

to fetch an instruction. It is an incrementing type register; i.e., its count can be incremented by one.

G922-G923 assembly. After a short interval allotted for circuit settling, the G924 module pulses the

Fet ching of instructio ns

ROM operation. For an

timing pulse to start the operation. The G924 module receives seven of these address bits and selects
one of 1 28 braid wires. The three remaining bits select one out of eight rows of sense amplifiers on the

M741 Major States and Timing - This module provides the timing relationships and control signals for:
1

G924 ROM Selection - This module selects the instructions stored in the ROM as specified by the
control unit. This module also contains the timing circuits for controlling

A brief functional description of the modules follows:

M742 Switch and Power Control — This module:

consists of three modules, two of which (the G922 and G923) form one plug-in assembly.

number of modules with perhaps the most complex interrelationships of the system.

Figure 2-1 shows the Control Unit modules and includes a brief title that defines their function. Note that the

maintenance standpoint, it is operated continually until a system malfunction occurs.

For the user, the recommended level of repair is module replacement.

Control Unit - As mentioned previously, the Control Unit is fundamentally the heart of the PDP-1

M746 Memory Buffer (MB) Register - Two M746 modules comprise the MB Register. This register
temporarily stores instructions provided by the

ROM or computer.

M746 Instruction Register (IR) - Two M746 modules comprise the IR. This register accepts the
instructions from the

MB Register and stores them for decoding and execution.
2-1

ON/OFF

Box

System

Cable

Address

Slot

(Octal)

0-37

40-77

100-137

140-177

200-237

240-277

300-337

340-377

OBox

System

OBox

System

Cable

Address

Cable

Address

Slot

(Octal)

Slot

(Octal)

0-17

200-217

20-37

220-237

40-57

240-257

60-77

260-277

START/STOP

ROM Bank

100-117

300-317

120-137

320-337

140-157

340-357

160-177

360-377

CM
00

O
00
(D

Notes:

<J>

CN
03

CM
00

•a-

IP X>

<31

o Oi

Maximum configuration shown.

in,

r»

S-i

r^ C;

Module
IVI249

Memory Port

M745 Computer Interface

—

M746
M921
3.

819

AB18
A17, B17

[^Output Register

C17, D17

Device Selector

Storage Module M232 can be used in any
provide up to 16 storage outputs.

A25
Box cable slot to

CM
00

CN
00

CM
CO

^
<s
CM

CN
CO

CN
00

CM
00

o
M

•Serial Line Interface Option

Figure 2-1 PDP-14 Mainframe Showing Module Locations
2-2

1
1

J,.__._,

— CD to

1
CL

\
Q.
ir>

1°
^ CM ^

a:,

r~-

'^ £

5-:='

5?-

p
3

CO
CM

e
3
o
c

1Q)

i
or

sec
DI ^ ^ •=
O CD M
03

CN
cn

lii

c
£

3
Cl

o
-o
li

1
H

-1

£Q

£1

^
o

c
01

r--

O-

Q-

22 21

j
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^m ^E
P

^f^.i^'Ei^-

«u
5
O

ei-

^
CO
r- o
(o7coS
£Or-Sr~oi^^r-.H'
1

~ P

g <
O

^ 2i

"I
ta
^S

o 1^ o

o—

CO en

/\
J

5>„ ino ob

Slot

j Input Register

13
1

ROM Bank 4
60008-7777g

s 1

The following modules are used only with a computer application:

—

ROM Bank 3
40008-5777g

n
B

-5

< 8IS "

5
o

X>
.3
CM
00

"c
cS .2

<
03

ROM Bank 2
200O8-3777g

00008-17778

Control Unit

M740 (or M7400) Instruction Decoder — This module examines each instruction and provides unique

control signals for instruction execution. (The M7400 module must be used with MAP-14.) This

module decodes parts of the instruction to:
1

Define the type and specific instruction to be executed

Select the source register for internal transfers

Select the destination register for internal transfers

M743 I/O Interface - This module interfaces the Control Unit with the I, O, and A Boxes. It provides

the input or output circuit address and designates the required function for outputs.

It also compares

the test result with the program-expected result and provides this comparison result to the M741

module.

M746 Program Counter 2 (PC2) - Two M746 modules comprise PC2. This register is used only for

program subroutines.

NOTE 2

It stores the program return address for subroutines.

M747 Spare Register - Two M747 modules comprise the Spare Register. This register is not normally

included in the PDP-14 and is not required. If included, this register is used as a utiUty register.

M745 Computer Interface — This module interprets computer input/output transfer (lOT) instructions

and synchronizes controller operations with the computer.

M746 Input Register — Two M746 modules comprise the Input Register. The register is only used for

computer operations. The register accepts and buffers 1 2-bit data from the computer for internal
register transfer instructions.

M746 Output Register — Two M746 modules comprise the Output Register. The principal use for this

I BOX

MODULE LAYOUT

M921 Device Selector — This module is only used for computer operations. It establishes a device code

for the PDP-14 Controller so that the computer can communicate with the controller.

BOX
CABLE
A03

LEVEL

K136 OR
K135

B02

LEVEL

M249 (or Ml 06) Memory Port — This module is only used for computer operations. The register

accepts and buffers 12-bit instructions from the computer and provides them to the

MB register for

The M249 Memory Port must be used with the PDP-8/E computer. PDP-14s used with the
PDP-8/I or PDP-8/L computer may also use the Ml 06 Memory Port in place of M249 if the proper
execution.

-PHASE INVERTER

ECO is installed.
K161
C03

LEVEL
2

2.2.2.3

I Boxes

BX14-DA and BX14-DD — As mentioned previously, each I Box provides the capability for

K161
C02

-DECODER-

handling 32 status inputs. These inputs can be either ac or dc (but not both). For ac inputs, a system uses I Box

BX14-DA. For dc inputs, a system uses I Box BX14-DD. These I Boxes differ only in the input converter

578
7^AB04

LEVEL
1

module used. Figure 2-2 depicts the module layout for an I Box and the hierarchy of modules as related to fault
isolation.

INPUT
CONVERTER"

ADDR

0-7

The modules are described in subsequent paragraphs.

K578
AB01

K578
CD04

ADDR
20-27

ADDR
10-17

INPUT
CONVERTER

K578
CD01

ADDR
30-37

I BOX HIERARCHY
a.

K578 AC Input Converter — This module accepts up to eight ac inputs and converts them into logic
levels.

Inputs are connected to a terminal strip on the front of the module.

(NOTE 2)

A neon indicator is pro-

NOTES:

vided for each input; this indicator lights when 1 1 5 Vac is present at the input.
b.

K564 DC Input Converter - This module accepts up to eight dc inputs and converts them into logic
levels. This module accepts inputs having a range from 10 to 55 Vdc (or above 55 Vdc with an external
series resistor at 50 ohms per volt).

module.

Relative address

DC input converter
used
in all

place of
input slots

in octal.

K564 con be
K578 converter

(BX14-DD X Box).

K579 is used in BX14-SA I Box.

Inputs are connected to a terminal strip on the front of the

A light-emitting diode (LED) is provided for each input. This indicator lights when voltage is
Figure 2-2

present at the input terminal.
c.

Box Layout and Hierarchy

K161 Decoder - This module is used in the addressing (or selection) of inputs. It decodes three bits of
address from the Control Unit to select one of the eight input circuits on a K578 or K564 Input

O Boxes BY14-DA and BY14-DD — Each O Box contains

Converter.

2.2.2.4

K136 (or K135) Inverter — This module contains four independent inverter circuits used in the

machine or process system devices. The outputs can be either ac or dc (but not both) depending upon system

addressing of input circuits and in input test return circuits.

NOT function.

Each inverter circuit performs a logical

usage.

6 independent output circuits that drive

A BY14-DA O Box provides ac outputs; a BY14-DD O Box provides dc outputs. These boxes differ only

in the output driver modules used.

2-3

Figure 2-3 depicts the module layout for an O Box and the hierarchy of modules as related to fault isolations.

K614 Isolated AC Switch — Four of these modules can be used in a BY14-DA O Box. Each module
contains four independent ac driver circuits. Each circuit is independently rated at 500 VA, however,

The modules are briefly described in the following paragraphs.

the collective total power rating for a module is 1 000 VA. Each circuit is equipped with a neon indicator.
b.

This indicator lights when 1 1 5 Vac is being provided to the load.

K657 DC Driver - Four of these modules can be used in a BY14-DD O Box. Each module contains
four dc driver circuits. Each circuit can be used to switch a dc load (having a source voltage from 1

250 Vdc) to ground. Each driver circuit is rated at i A (maximum). Each output has an LED that
indicates when the output path is completed.

NOTE 1-

10
c.

o *

causes the output circuit path to be completed.

ID
it

o
o
CM
^

K207 Flip-Flop - This module contains four storage registers (flip-flop circuits) that control the output circuit on a K614 or K657 module. When turned on (SET) by a program instruction, a flip-flop
The flip-flop remains in this state until turned off

(RESET) by a program instruction or an initialize operation. The state of the K207 flip-flop is tested
by the control program to determine if an output is on or off.

K161 Decoder — This module is used in the addressing (or selection) of outputs. It decodes three bits
of address from the Control Unit for selection of one of eight flip-flop circuits contained in two K207
modules.

K135 Inverter — This module contains four independent inverter circuits used in the addressing of
output circuits and in the output test return circuits. Each inverter circuit performs a logical NOT

^ o

o ^

function.
15

A Box — An A Box can be used to provide timer (delay), retentive memory (event storage during
power-off states), or normal storage functions. Each A Box requires one O Box cable slot. In most instances,
A Boxes are assigned an upper system address to differentiate from "real" outputs. An A Box can be configured
in a number of ways. Figure 2-4 depicts the module location and hierarchy for an A Box. A brief description of
the modules is provided in subsequent paragraphs. (For additional details concerning A Box functions and
2.2.2.5

o
CJ
^

BOX

MODULE LAYOUT

relationships, refer to Chapter 1 ).

LEVEL

K135
A02

-PHASE INVERTER

LEVEL

A timer circuit is addressed in the same maimer as
O Box module s, except the sample ret urn is ge ne rated on this module and not on the K207. Up to
eight K302 Timer modules (16 timer circuits) can be accommodated in one A Box.

vide delay intervals up to 4 minutes, 45 seconds.

LEVEL

K161

C03

K161

-DECODER

C02

— FLIP-FLOP —

K207
D03

K207

K6t4
CD04

K614

B02

— FLIP-FLOP-

K272 Retentive Memory — A retentive memory retains its state during power off and is unaffected by
an initialize operation. Up to four K272 Retentive Memory modules can be used in an A Box, each
providing one retentive memory circuit. These modules are addressed in the same manner as "real"
outputs but only even-numbered relative addresses on the right-hand side of the A Box can be used.

K207
B03

LEVEL

K302 Timer — A K302 Timer module contains two timer circuits. Each circuit is capable of providing
standard delay intervals from 0.01 to 30 seconds. With the additional resistance, a timer can also pro-

-BC14A

BOX
CABLE
A03

K207
D02

K274 Retentive Memory — This module functions in the same manner as the K272 module, but contains two retentive memory circuits per board. Up to eight K274 modules can be accommodated in
one A Box to provide a total of 1 6 retentive memory circuits.

NOTE 2- "\
LEVEL

'K614

AB04

OUTPUT
DRIVER

AB01

ADDR
4-7

ADDR

0-3

OUTPUT
driver"

K614
CD01

ADDR

10-13

14-17

BOX HIERARCHY

of the module slot.

NOTES:
1.

Relative oddress

Con use

e.
in

K022 Storage Module — This module can be inserted in the unused timer or retentive memory slot to
provide two storage outputs. The module connects the outputs from two K207 flip-flops to the output
test return circuits in an A Box. The storage outputs provided by the K022 use the relative addresses

octal.

K657 DC driver or K616 Isolated AC Switch.

K207 Flip-Flops — This module contains four flip-flops. Each flip-flop can be independently set and
reset or all can be collectively reset. Each flip-flop can control one timer or one retentive memory or
can be used with a K022 Storage module to provide one storage output. Unlike the O Box, the sample
return in an

Figure 2-3

O Box Layout and Hierarchy
/.

A Box is not generated from this module.

K16I Decoder - This module is used in the addressing of A Box circuits. It decodes three bits of
address from the Control Unit to select one of eight K207 flip-flops.
,^
,

(continued on next page)

2-4

K135 Inverter — This module contains four independent inverter circuits used in the addressing of

A Box circuits. Each inverter circuit performs a logical NOT function.

2.2.3

Recommended Test Equipment

A VOM (such as Simpson, Model 260 or Triplett, Model 630NA) is recommended for user maintenance. An
oscilloscope (such as Tektronix, Model 453) is considered optional.

-NOTE

RELATIVE
ADDRESS

NOTE 1-

2.2.4

CM CM

*0 a 1

Recommended Spare Parts

Table 2-1 lists the recommended spare parts by major units. Table 2-2 lists the spare parts recommended for a

typical PDP-1 4 configuration.
.O
12 a 13

Table 2-1

cMr^

Recommended Spare Farts by Major Units

OCJ

CONTROL UNIT SPARES
4 8 5
OCM

CJh-

OCM

A BOX MODULE

K135

LEVEL

Major States and Timing

M742
M743
M744
M746
M747

Comparator

BC14A-15

I/O Cable

one for

M249
M745
M746
M921

K161
003

)

control

K207
803

LEVEL
2

-FLIP FLOP

•

Memory Port

one for

LEVEL
1

K302

K022 OR
K274 OR
K302

A04

B04

K022 OR
K274 OR

K302
C04

K022 OR
K274 OR
K302
D04

ADDR

0,1

2,3

4,5

6,7

K302
A01

ADDR
10, n

K022 OR
K272 OR
K274 OR
K302

801

COI

ADDR

12,13

14,15

16.17

Binary-To-Octal Decoder

K6 1 4/K6 1 6

Isolated

every
>

Bus Register

Inverter

one for

Fhp-FIop

every

AC Switch

\wo

three

K657

boxes

DC Driver

computer

Device Selector

ACCESSORY (A) BOX SPARI:s

interfaces

one for

ROM Sense Amplifier
every
ROM Selection and Timing / four
I

K022 OR
K272 OR
K274 OR
K302
001

K135
K161
K207

Computer Interface

K207
D02

K022 OR
K272 OR
K274 OR
K302

boxes

AC Input Converter

OUTPUT (0) BOX SPARES

Incrementing Bus Register

ROMs

FUSES
K022 OR
K272 OR
K274 OR

K578/K579

Bus Register

K207
B02

two

units

C02

K207
003

one for

DC Input Converter
or

K161

G923
G924

Binary-To-Octal Decoc

three

-J

DECODER

Inverter

K564

Switch and Power Control

MEMORY SPARES
LEVEL

K136
K161

I/O Interface

COMPUTER INTERFACE SPARES

-PHASE INVERTER

A02

Instruction Decoder

M741

LAYOUT

BOX
CABLE
A03

LEVEL

M740

INPUT (I) BOX SPARES

Littelfuse 5A type 276005 for K614 Isolated

K135
K161
K207
K302
K022
K272

K274

Inverter

Binary-To-Octal Decoder

one for

Flip-Flop

Timer

A Box Storage Module
Retentive Memory

Retentive Memory

every

[two
boxes

Switch

A BOX HIERARCHY
NOTES:
1

Relative

K272

address

retentive

in octal

2.3

FAULT ISOLATION WITHOUT A COMPUTER

memory contains

one memory and uses only even numbered
relative addresses. K274 retentive memory
contains two memories ond uses botti addresses.

2.3.1

General Approach

Fault isolation of a machine system malfunction can be analogous to isolating faults in the automobile. That is,

the same general principles apply. First, we try to analyze the fault in major categories; whether the entire system

Figure 2-4

A Box Layout and Hierarchy

is inoperative or, if it works,

what part works and what part does not work.

2-5

Figure 2-5 illustrates the basic steps of user maintenance described below.

Table 2-2

Step 1

Determine what functions the machine or process system will and
will not perform.

Recommended Spares
Configuration

Quantity

DEFINE MACHINE
1

Spare Parts Recommended for a Typical Configuration

In some instances, the malfunction may be

readily apparent from the lack of a machine motion (or action) or

Spare

ISOLATE FAULT TO
MACHINE SYSTEM
OR PDP-14 CONTROLLER

malfunction is checked first. This approach will generally isolate

the machine or process system load circuits. If the PDP-1 4 is not
3

ISOLATE MACHINE
FAULT OR CONTROLLER
FAULT AND REPAIR

from control panel status.

One PDP-1 4 Control Unit
One Computer Interface
Two IK ROMs

i
1

Four I Boxes
Four
Boxes

One A Box

Two Storage Modules

1
1

BC14A-15 I/O Cable
G923 ROM Sense AmpUfier

G924 ROM Selection and Timing
K022 A Box Storage Module
K135 Inverters
K161 Binary-To-Octal Decoders
K207 Flip-Flops
K274 Retentive Memory
K302 Timer
K578 or K579 AC Input Converters
(or K564 DC Input Converters)
K614 or K616 Isolated AC Switches
(or K657 DC Drivers)

M232 Storage Module (BF14-M)
M249 Memory Port
M740 Instruction Decoder
M741 Major States and Timing

Step 2,

M742 Switch and Power Control
M743 I/O Interface
M744 Comparator
M745 Computer Interface
M746 Bus Registers
M747 Incrementing Bus Register
M921 Device Selector

Use the information from Step 1 to begin fault isolation. In
general terms, the PDP-1 4 Controller output(s) for the appUcable

providing the output, the machine status inputs (for this output)

must be checked. This approach generally isolates the PDP-14
from the machine system input circuits.
Step 3.

OR PROCESS SYSTEM
MALFUNCTION

Locate and replace the machine components (switch, solenoid,
etc.) or the PDP-14 malfunctioning module.

(For maintenance

VERIFY REPAIR

purposes, the machine system includes all input and output
wiring to and from the machine system.)
tCiJ T.

vclixy Liiat lilc Sj'Sueni upciaLcS ikOXxiicLiky aiLC^i uiq icj^oii.

Figure 2-5

User Maintenance Steps
2.3.2

Input and Output Organization

As mentioned previously, the PDP-14 prog"am establishes the relationships between inputs denoting machine
Status and controller outputs denoting machine action. Before this program can be written, however, the input

and output relationships must be defined. Then, the inputs and outputs must be assigned to I and O circuits.
In the traditional relay control system, control relationships are often established using ladder diagrams and

symboUc equations. Both are also useful tools in defining control relationships for PDP-14 Controller appUcations.

Figure 2-6 shows an example of a ladder diagram, symbolic equation usage, and the Boolean equivalent.

It also

illustrates the usage of Input and Output Assignment Tables and defines the logical operators and the input and

For example, if someone told you that your car won't run, you'd probably begin by finding out if the starting

output designations for controller use.

system will turn over the engine. If it did not, you'd probably suspect the starting system (battery, starter motor,

The A part of Figure 2-6 illustrates a logical AND function and the B part illustrates a logical AND-OR function

solenoid, etc.).

From this point, you can continue the investigation or begin substitution of components. If,

however, the engine can be rotated but fails to start, you'd suspect a different set of components (possibly the

with grouping of combinations using parentheses. Parentheses are used to eliminate ambiguity in the relationships.

The B part also defines the use of a NOT operator.

carburetor, distributor, etc.) and would begin isolation from this point.

After input and output relationships have been established, each PDP-14 output and input is assigned a terminal

The same principles apply to the machine system you are troubleshooting.

First, you must have a good under-

standing of what the machine does and in what order it does it. Next, you must analyze the failure in major

number. The symbolic equation, its Boolean equivalent, and the device(s) involved are then entered into Input
or Output Assignment Tables such as those illustrated in Figure 2-6.

categories. Is it a complete failure? If yes, you should literally begin at the power source of the controller. If no,

examine the equipment and equipment sequence for additional symptoms or clues.
Since each machine or process system sequence is unique, the information provided in this chapter can only be

considered as guidelines to systematic troubleshooting.

2.3.3

Input and Output Assignment Tables

Input/output relationships (and the devices providing the status or using the output) are usually defined in Input

and Output Assignment Tables. From a fault isolation standpoint, the information in these tables is very useful.
Therefore, a brief description of their content and typical use follows.

(Continued on page 2-9)

2-6

Prog

EQUATIONS

LADDER DIAGRAMS

INPUT ASSIGNMENT TABLE
Notes

Input Device

No.

Terminal

POWER Control Relay CR1

START pushbutton PB1

SLOW switch LS2

FORWARD Motor Starter IV12

From NC contacts
of

"AND" OPERATOR: DENOTES
BOTH CR1 AND PB1 MUST BE
CLOSED TO ENERGIZESOLA.

IBox

-A,y^

PB1

'
'

% S0LA CR1*'^1
=

SYMBOLIC
EQUATION
CR1

H XO
YO

PDP-14

J\p

^ YO XO *XT
^

PB1

SOLA

"AND" OPERATOR: DENOTES
115 VAC (OR DC INPUT) MUST
BE PRESENT AT BOTH XO AND
XI TO PROVIDE YO
INPUTS ARE

BOOLEAN

FORWARD

EQUIVALENT

Motor Starter

DESIGNATED X

OUTPUTS ARE
DESIGNATED Y

PARENTHESES USED TO GROUP COMBINATIONS
"OR" OPERATOR: DENOTES EITHER (OR BOTH)
COMBINATIONS CAN LIGHT 2LT

B
OUTPUT ASSIGNMENT TABLE

-^o.

[mZ^ 2LT=CS0LA* LS2)+/M2

-Q)

LS2

SYMBOLIC

Output Device

Output Control Equation

Prog

OBox

Identification

X = Input, Y = Output, + = OR, * = AND, / = NOT

No.

Terminal

RESTART Sol.
SOLA

S0LA = CR1 *PB1

SLOW light

2 LT = {SOLA* LS2)+/M2

2LT

Y1 = (YO * Y2) + X3

EQUATION

LS2

YO = XO * XI

PDP-14

Y1
j

O
2LT

% Y1MY0*X2)+i<3
BOOLEAN
EQUIVALENT

Figure 2-6

"NOT" OPERATOR: PHYSICAL DESCRIPTION
THAT DENOTES NOT ENERGIZED

OR TRIPPED.
"OR" OPERATOR: DENOTES EITHER
(OR BOTH) COMBINATIONS CAN
LIGHT 2LT (YD.

NOTE THE ABSENCE OF "NOT" OPERATOR
IN BOOLEAN EQUIVALENT. A "NOT"
OPERATOR HERE DENOTES ABSENCE OF
115 VAC (OR DC INPUT).

Input/Output Relationships

2-7

EXAMPLE ASSUME THAT Y0=X0*X1 (SOLA=CRrPB1) AND
THAT Y0 IS OFF.
1:

START

ENTRY POINT FOR GOOD
INPUTS OF EXAMPLE 2

Assumes machine system can be
started and some motion or action

Use BT14 interrogator Box to

can be performed.

Swap level 2 module in

check functioning of input

Box

hierarchy for applicable inputs

modules.

(see Fig. 2 2 for

Box layout).

Define area of system failure, i.e.,

which solenoid, relay, etc did not
Doerate.

SOLA..

Use output assignment table to
locate

Replace and mark defective module,

Skip these stef» if a BT14

Box output (Y) that

Interrogator Box is not

then return to normal operation.

Procedure repeated for
each G924 module.

activates the inoperative device.
available.

Problem external to controi system.

Swap CM- substitute next higher

Denotes output device malfunction

level

Return to normal operation.

module.

SOLA}.

Check and repair machine
system ckt.

ENTRY POINT
FOR BAD OUTPUTS
OF EXAMPLE 2.

Substitute G924 module in

next ROM bank:

Bank 2, slot 9
Bank 3, slot 5
Bank 4, slot 1

NOTE: A ROM can be comprised

Use output assignment table to

Swap level 2 module in O Box

of up to 4 banks. Each bank

define output control equation.

contains one <ald24 moauie.

Y0=X0*X1 ._

Define input device(s) using input

(from Fig. 2-6)

assignment table.

(see Fig. 2-3).

Substitute input converter module
{level 1, Fig. 2-2).

Check applicable input terminals

Box for 1 1 5 Vac (or DC

Remove G922-G933 assembly fror
bank 1, disassemble G923 from
G922, and install a spare G923
module. Then reinstall assembly in

input level).

Replaee a«d -mark defective

module and return to normal
operation.

Return to normal operation.

mainframe.

Swap or substitute next higher
level

module.

Now, check the control unit.

Problem external to control system.

Denotes input device malfunction.
Substitute M743 i/0 Interface

module (slot CD24 rn control

PDP-14 malfunction or control

unit).

output device malfunction. Proceed by checking applicable

LiSing moduie swapping or sub-

stitution.

Return to normal operation.

Check fuse for applicable output
(see appendix for fuse locations).

NOTE; One G922-G923 assembly
is

Replace fuse; recheck for
overload.

contained in each ROM bank.

Remove memory nwdules (G923
and G924) and disronnect I/O

If fuse is blown,

Replace applicable

iocate overhead and repair

cables.

Subsrtitute M747 module in slot

or replace machine system

component.

(See Paragraph 2.3,14 for

b. Remove old control unit and

C19 (PCI, bits 0-05}.

replacement.)

install spare.
c.

Re-instal! memory modules and I/O

cables.

Substitute

O Box output driver
Return to normal operation.

module (level 1, Fig. 2-3),

Return to normal operation.

Return to normal operation.
Return control unit to DEC
Restore original module, then

Return to normal operation.

Replace applicable O Box.
(See Paragrai* 2.3.14 for
replacement.)

service center for repair.

substitute M747 in slot D19

(PCI, bits 6-11).

Next, check applicable

Return to normal operation.

Box using

module swapping or substitution.

Return to normal operation.

Reverify this procedure and
call

Proceed bv checking the ROM.

2-8

Figure 2-7

Decision Diagram, Fault Isolation Example Number 1

DEC Field Service

personnel.

An Output Assignment Table usually identifies the device being controlled, the symbolic and Boolean equations
for the output, and a PDP-14 terminal number for the output. Terminal numbers are generally assigned using the

system address (in octal) for the output circuit. These terminal numbers range from

to 377, excluding numbers

Define area of system failure,
i.e.

containing the digits 8 or 9. Generally, non-real outputs (storage, timer, or retentive memory outputs) are

which solenoid, motor starter,

etc. did not operate.

aS1*LS2-SOL50»/SOL22) ((LS10*PB12+SOL61 + (LS30»LS15+PB25)I

= [X1*X2*'Y60VY221

OUTPUT
CONTROL EQUATION

assigned the upper-most program numbers.
Use output assignment table to
locate

An Input Assignment Table generally defines the input device supplying the status input plus any pertinent notes

|(X10*X12+Y61 + (X30'X15+X25)]

COMMON FACTORS AUTO MODE

O Box output (Y) that

activates the inoperative device.

related to system functions. Input tables can be arranged by terminal number order as shown in Figure 2-6.

Terminal numbers for inputs can be from

to 377, excluding numbers containing the digits 8 or 9.
Check and repair machine system
ckt,

2.3.4

(component and wiring)

Fault Isolation Example Number 1

Figure 2-7 is a decision diagram that illustrates the recommended methods of fault isolation.

The example

assumes the RUN indicator (Figure 2-6) is off, yet some machine action or motion can be performed (the system
can be started or is not locked in an initialize condition). Note that malfunctions external to the controller can

be readily identified and that in the worst case condition, the decision diagram must be followed to the end (or
near the end). The decision diagram is presented in general terms so that it is generally applicable to all output

Denotes fault is

Denotes fault is in

common factors

equations.

mode.

The decision diagram has two entry points other than START. These points are used when more

complex equations are encountered as illustrated in Fault Isolation Example Number 2. Use of steps involving

Locate and check inputs for

common factors. (XI and X2)

automatic factors. (XlOand X12)

the BT 14 Interrogator Box are optional, but are strongly recommended if a BT14 is available.

2.3.5

Check for 90 to 115 Vac

Check tor 90 to 115 Vac

at input terr^inals.

at input terminals.

Fault Isolation Example Number 2

Figure 2-8 is a decision diagram that indicates how more complex equations should be handled. Note that the

Check and repair machine

general approach is to determine if an alternate mode works.

and wiring}

system ckt. (components

Note also that if the fault is isolated to the control-

ler, the isolation is continued using Figure 2-7.

2.3.6

Examine outputs. in common

PDP-14 fault. UseFig. 2-7 to

factors (Y6D and Y22)

continue fault isolation.

Fault Isolation For Equations Involving Timer Functions

In general, timer malfunctions can be readily detected by observing system symptoms.

A timer malfunction
Check fuse for primary

manifests itself by the lack of an interval between two machine or process system events or the second event

output (Y6)

never occurs.

Timer malfunctions are isolated in a manner similar to that of active outputs, except that there are no indicators
Branch to another equation,

to define whether the timer is working. In addition, each timer module is unique from a substitution standpoint;

Use Fig. 2-7 to continue
fault isolation.

i.e., its

components are set up to provide a unique time interval. In addition, substitution is compounded because

each timer module contains two timer circuits.

Exit to Fig, 2-7

The general approach for equations involving timers is to check all other parts of the equation first, using the
methods described in Paragraphs 2.3.4 and 2.3.5.

If the fault is isolated to the timer term of an equation, use the

Figure 2-8

method illustrated in Figure 2-9 to isolate the fault. As can be observed, all modules involved in the selection

Decision Diagram, Fault Isolation Example Number 2

are changed first, since timer substitution is difficult because each timer is unique and possibly affects two
circuits.

NOTE
When substituting or replacing a timer module, always match
timing capacitor usage; i.e., clip the same capacitor leads as on
the old module (see Figure 2-10 for timing capacitor location).

For gross adjustment of the timer interval, refer to Paragraph
4.5.2.

2.3.7

Fault Isolation For Equations Involving Retentive Memory Factors

When a retentive memory is suspected of being defective, replace the retentive memory module first. If the fault
is not corrected, restore original module, then continue isolation using Figure 2-7. The K274 Retentive Memory
module is easily isolated since an LED indicator is used to display the status of each circuit. K272 and K274
modules have switches to clear the retentive memory. This switch should be in the center position for proper
operation.

2-9

G>
Swap level 2 module in

Box

related to timer inputs.

START

":)

^X,^

1
Check timer input factors.

Swap or substitute next higher
level module in

Fault

Box.

^N,,^

corrected or

^V,^

changed?

Replace defective level 2 module

and return to normal operation.

Tno
Check and repair machine
input devices.

Restore original module.

UseBT14 Interrogator Box to

Yes

Any

^X"*^

^s^

check functioning of input
modules.

Replace defective input module.

Swap level 2 module in A Box

Remove suspected timer. Match
timing capacitor usage on new

hierarchy related to timer

address (see Fig. 2-4 for A Box

NOTE:

layout).

Must be done
for both timer

module with that for old module.
Clip same capacitor leads (see
Fig. 2-101.
-

circuits on

module.

Set timing potentiometers on new

module the same as on old module.

Swap or Kjbstitute next higher
level

module in A Box.

Replace defective level 2

Refer to Paragraph 4.5.2.

module and return to
normal operation.
Substitute timer module.

Return to norma! operation.

Restore original timer; then
substitute M743 module.

Return to normal operation.

Restore original M743 module

and begin fault isolation of
processor.

c
Figure 2-9 Decision Diagram, Fault Isolation for Equations Involving Timer Functions

2-10

Exit to Fig. 2-1

^^^

ODD-NUMBERED

2.3.12

RELATIVE ADDRESS
TIMING COMPONENTS

EX • 4 .1.1

EVEN-NUMBERED

When replacing the mainframe, be sure it is operational before putting it on-line. Do not swap the processor

-RELATIVE ADDRESS
TIMING COMPONENTS

modules. Remove 1 10 Vac power from the entire system before starting. Then carefully mark all cables and

ROM sections before removing them. Make sure the same number of power suppUes are installed on the new
mainframe as were present on the mainframe being removed. Finally, recheck all memories and cables after they

-POTENTIOMETER

are plugged into the new processor before applying power.

Mainframe Replacement

2.3.13

Power Supply Replacement

When replacing power suppUes, be sure the jumpers between the two supplies are properly installed before applying power (if two power supplies are used).

Figure 2-10

2.3.14

K302 Timer Components

O, and A Box Replacement

When replacing I, O, and A Boxes, be sure all power to the system is off. Attempting to change 1, O, and A
Boxes with the power on can result in serious damage to the system. Make sure the correct input and output
2.3.8

Fault Isolation For Equations Involving A Box Storage Functions

modules (ac or do) are used in the replacement box.

When a K022 Storage module is suspected of being defective, replace the K022 module first. If the fault is not
corrected, restore original module and continue fault isolation using the procedure in Figure 2-7. Use of the

BT14 Interrogator Box will allow the state of the storage bit to be determined.
2.3.9

2.3.15

A Box Replacement

When replacing A Boxes, make sure the correct modules are installed in each slot (timers, retentive memories,
and storage modules). Remember the timers must be individually adjusted for the proper timing. See Paragraph

Fault Isolation For Major System Failure

4.5.2 or use a computer.
If the system cannot be started or is locked in an initiahze condition, the fault is probably in an area
all logic functions.

common to

For example, the low-voltage power supply, the power-up and power-down sequence, or con-

troller timing should be suspected.

When a problem of this nature is encountered, use a systematic isolation

method such as that illustrated in Figure 2-11.

Troubleshooting Hints and Kinks

2.3 1
.

2.4

FAULT ISOLATION WITH A COMPUTER

2.4.1

Fault Isolation Approach

Four diagnostic test tapes are provided to aid in fault isolation. In general, three of the test tapes (TEST-14,

VER-14, and ABE-14) are used for major or complete failures. The fourth test tape (ROL-14) provides an ona.

Intermittent Problems - For intermittent problems, always check the common earth ground between

line interrogation feature to examine inputs and outputs.

A #6 copper wire (or larger) should be used for the
common ground. Also check common ground between the processor and the I, O, and A Boxes.

major or complete failures.

the machine or process system and controller.

Power Supply Foldback - To detect a power supply foldback problem, disconnect the load, then
return to full load while observing output voltage for a 0. 1 V or greater change. If output voltage

change is greater than 0.1 V, replace power supply.

Figure 2-1 2 shows the recommended types of tests and the general dependency of the tests. Note that three tests

can be performed using TEST-14. The first test, in general terms, checks the power control functions, major
states and timing, computer interface, and all the other Control Unit functions except I/O interface and I/O

timing.

Module Substitution and Replacement Notes

2.3.1

The ROL-14 tape is generally used for other than

The second test (TEST-14 with one storage module) checks the I/O interface and I/O timing. The third

test involving TEST-14, checks

O Box functions with the O Box 115 Vac (or dc) source disconnected.

K578 AC Input Converter - When replacing a K578, Rev. B, always use a Rev. B or greater, because of

The VER-14 test checks the operation and contents of the ROM against a ROM tape entry in the computer that

the speed of the input converter.

defines what the

M744 Comparator — If TEST-14 denotes a faulty M744 module, continue troubleshooting unless the
controller is performing SKE or SKZ functions. The M744 module does not normally affect control

The ABE-14 test checks the timer, storage, and retentive memory functions performed by A Box circuits. Thus,

operation.
c.

Modules for PDP-SjE Interface - An M745, Rev. E is required with M249 usage.

K302 Timer Module - When substituting or replacing a K302 Timer module, use the old module as a
guide and cUp out the same capacitor(s) on the new module. This must be done for both circuits if

ROM should contain. Both sequential and random addressing are used.

in the case of a major or complete failure, the system is tested from basic Control Unit functions through all

output functions.

The ROL-14 test enables interrogation of inputs and outputs using the teleprinter. Thus, ROL-14 is generally
used to evaluate malfunctions other than those considered a major or complete failure. In other words, ROL-14
is used

when the machine or process system functions normally with only an isolated failure or failures.

both are used. For gross adjustment of the time delay, refer to Paragraph 4.5.2.

2-11

Cannot start system
Substitute M742 module

or major failure.

Check and repair line source.

Restore original M742 module,

then substitute M741 module.

Fl,2Anip

Line
fuse

^S. No

Replace line fuse and

check tor overload.

Restore original M741 module;

then substitute M740 module.

Return to normal operation.

Restore original M740 module;

then substitute M747 module
in slot

C19 (PCI, bits 0-5).

Replace pwr supply.
Restore original M747 module;

then substitute G924 in slot

ABCD13.

Return to normal operation.

Restore original G924 module;

then substitute G923 in slot

ABCD16.
Replace mainframe and install

ROM modules from old mainframe.

Figure 2-1 1

2-12

c
Decision Diagram, Fault Isolation for Major System Failure

Assumes the computer end its
I/O equipment are working.

The following modules are required for the computer interface:
Module

Slot

*M249 Memory Port
M745 Computer Interface

M746
Use ROL-14 for fault
isolation.

Paragraph 2.4.10.)

r Input Register
1^

(Refef to

B19

AB18
A17andB17
CI 7 and Dl

Output Register

M921 Device Selector

A25

Run TEST-14 for control
unit only.

[Paragrapfi

2.4.5).

*An Ml 06 module may be used in place of the M249 in any
configuration except the PDP-8/E or PDP-8/M.

The M92 1 module selects the device code of the controller.

It must have the device

A portion wired to provide

a device code of 16g or 17g (corresponding to BMB03 through 05 and 06 through 08 respectively). Figure 2-13

shows these connections. Figure 2-14 shows the cabling for the PDP-14-to-computer interface.

Run TEST-14 with one
storage module.

(Paragraph 2.4.6).

JUMPERS FOR
168 OR

I'^S

DEVICE CODE
(9

Run TEST-14 witfi

OC1

Box

(disconnect 115 Vacordc).

(Paragraph 2.4.7).

Run VER-14.
(Paragraph 2.4.3).

>13

OS1

Return to rwrmal operation.

Run ABE-14.

PIN SIGNAL ASSIGNMENTS

(Paragraph 2-4.9).

E2
F2
H2

Figure 2-12 Diagnostic Test Usage

K2
L2

M2
N2

2.4.2

Connecting a Computer

P2
R2
S2

OUT
DEVICE B DEVICE

MB3(0)
MB3(1)

MB4 (0)
MB4 (11
MBS (0)
MB5 (1)
MB6(0)
MBS (n

MB7 (0)
MB? (1)
MBS (0)
MBS ID

DEVICE A
A1
Dl
HI
Lt
PI
Ul

B1
E1

C1
F1

K1
N1
SI

Ml
R1
VI

SIGNAL
MBS
MB4
MBS

MBS
MB7
MB8

UNLESS OTHERWISE INDICATED;
ARE SPLIT LUGS

A computer can be used for fault isolation of a controller used in a stand-alone application. However, since the
computer is not an integral part of the system, interface modules must be installed and the computer must be
connected to the PDP-1 4.

Figure 2-13

M921 Connections for a Device Code of 16„ or 17„

2-13

PDP-8/L

PDP-8/I
(POSITIVE BUS)
"V

(8K)

TOP

PWR

-V

T-

SUPPLY

A A
?n 19 M

4
2

A
20

B
B
B
34 35 36

—

\
\

M249

M106

Ml 06
J

l-KUNT-

A
19

4
B

06 05 04 03 02

PWR

SUPPLY

POWER SUPPLY
PDP-14 MODULE HANDLE VIEW

BA08
BOTTOM VIEW

PDP-14 MODULE HANDLE VIEW

MODULE HANDLE VIEW
BC08C or BC08D
CABLES

BC08A or BC08B
CABLES
V.
A34

D34

834

AC IN

^\\

A19

\\
A35

D35

B35

BMB 0-11

A 20

A36

D36

BA08 EXT

PDP-8/L (4K)

TTY CABLE

TOP

PWR
A

>-r
A

20 19

M
-7

4
5

^r-f

TOP

-y

SUPPLY

-VY-

"inn
U U U
3

PWR

V-f^

—

A A
20 19

—

4
2

CABLE CABLE CABLE
\

4
B

M249

COMPONENT ST0E

M106

M249
ONLY

POWER SUPPLY

M8350 MODULE
ME

MODULE HANDLE VIEW

PDP-8/L 4K OF MEMORY
BOTTOM VIEW

PDP-14 MODULE HANDLE VIEW

/^f

BC06A or BC08B
CABLES

///
1

_ M8350
I

E M8350

A19

CABLE

BMB 0-11

D35

BAC 0-11

BMB 0-11

L
A20

BAC 0-11

CABLE 2

D36

(4K)

4
2

034

B20

PDP-8/E OR PDP-8/M

—

-J-.

SUPPLY

B36

BAC 0-11

M8350

B20

CABLE 3

AC IN

LT
14-01038

Figure 2-14 PDP-14 Cabling (Sheet 1 of 2)

2-14

PDP-8 (NEGATIVE BUS)
'-

SIDE LOGIC

PWR T
SUPPLY

A A
20 19 M

RIGHT HAND
SIDE LOGIC

LEFT HAND

ME ME

35 34

MF MF

35 34

UPPER
SECTION
LOGIC

> PWR >

•

SUPPLY

7
4

M249
or

—

M106
A A A A A A
06 05 04 03 02 Ot

A A A
22 21 20
r

POP -14 MODULE HANDLE VIEW

M623
M623
M623

N14
N15
NI6

LOWER

DW08-B MODULE HANDLE VIEW

SECTION
LOGIC

A A
?n IS M

4
B

20
\
\

M249
or

M106

M906
L.INSTALL
HERE
PDP-14 MODULE HANDLE VIEW

PDP-12 REAR MOUNTING DOOR
MODULE HANDLE VIEW

BC02M or BC03C
CABLES

LINC 8 (NEGATIVE BUS)

PDP-8/I
(NEGATIVE BUS)

PWR

T SUPPLY

SUPPLY
A

20 19 M

4
Z

4
B
20

y
1

A
?0 19

20
\

M249

M106

M106
J

PDP-14 MODULE HANDLE VIEW

0$ 05 04 03 02 01

—

PDP-14 MODULE HANDLE VIEW

MODULE HANDLE VIEW

A A
22 21 20

PE2

06 05 04 03 02 01

DW08B MODULE HANDLE VIEW

PF2

DW08-B MODULE HANDLE VIEW
BC02M orBC03C
CABLES

BC08A or BC08B
CABLES

REAR MOUNTING DOOR
MODULE HANDLE VIEW

|mE34

|mF34

|mE35

POP -8/1
NEGATIVE BUS
LINC- S

,^ CABLES

h<'VbAC

'°'l

0-11

B20
1

AOZ]

^
\^
MF35:

BC08A

—

BCO2MorBC03C

BMB 0-11

.-,

u..'

1
1

A2oJ

A04|
1

11
J
>

M—
L

A06

'
'

DW08-B

\ AC IN

-^Aisl
PDP-14
01048

Figure 2-14 PDP-14 Cabling (Sheet 2 of 2)

2-15

Loading of Binary (BIN) Loader Tape (DEC-08-LBAA-PM)

2.4.3

Toggle in the Read-In Mode (RIM) Loader for the low-speed paper-tape reader (33 ASR Teletype® or equivalent)
or the high-speed paper-tape reader (PC04, PC05, PR-8/I or equivalent) as appHcable:
1 .

Turn on computer.
Qpt iin ctqi-tJrxt OflHrocc 111 111 lOI
press

lO /'^'-+p1 TT:/^\ 4^ i-U^ ,,^™«,,+a^'o c,,,;+^h ^o/.;oY-^r /^CD^

Insert Binary (BIN) Loader tape in apphcable paper-tape reader.

Turn on reader and depress START.

10.

If tape stops before completion, restart tape at beginning.

1 1

After binary tape is loaded, depress STOP, turn off reader and remove tape.

<-V.a»,

LOAD ADDR switch*. (Refer to Chapter 10 of the PDP-14 User's Manual for a description of

the computer's front panel and the octal numbering system.)
3.

Loading of Diagnostic Tapes

2.4.4

The following procedures can be used to load all diagnostic tapes (TEST-14, VER-14, LOAD-14, ABE-14, or

Set first instruction in SR for low- or high-speed reader (as apphcable) using the information in

ROL-14):

Table 2-3. Then depress DEP key.

Turn on computer and depress STOP key.

Table 2-3

To address the Binary (BIN) Loader program, set 7777g into SR. The correct switch configuration for
this number is:

RIM Loader
Low-Speed Reader
Address

7756
7757
7760
7761

7762
7763
7764
7765
7766
7767
7770
7771

7772
7773
7774
7775

High-Speed Reader

Instruction

Address

110 000 Oil 010

(6032,)

110 000 011 001

(6031)

101011 101 111
110 000 011 110
111 001 000 110
111 000 000 110
111 101 001 000
101 oil 101 111

(5357)

111 000 000 110

(7006)

110 000 011 001

(6031)

101 oil 110 111
110 000 011 100

LOAD ADDR key.

Press

Load diagnostic tape into apphcable paper-tape reader.

For high-speed reader, set SRO to 0. For low-speed reader, leave SRO set to 1

With reader on, depress START key.

When tape stops, verify that the computer's accumulator (AC) contains all Os (all AC indicators off).

110 000 001 100

(6014„)

110 000 001 001

(6011)

(5357)

7756
7757
7760

101 oil 101 111

(5357)

(6036)

7761

110 000 001 110

(6016)

(7106)

111 001 000 110

(7106)

111000 000 no

(7006)

111 101 001 000

(7510)

This condition denotes that the tape was loaded correctly. If AC contains all Os, remove tape and turn

on 111 100

(5374)

off reader. If not, reattempt loading. If error still occurs, the tape is bad, the equipment is malfunc-

111000 000 110
110 000 001001
101011 110111

(7006)

tioning, or the Binary Loader is not properly loaded.

(5367)

7762
7763
7764
7765
7766
7767
7770

(5367)

(6034)

7771

110 000 001 no

(6016)

7772
7773
7774
7775

111 100 010 000

(7420)

Test Summary — This test checks all the functions performed by the Control Unit except those performed for the

on 111 111 no
on on 111 no

(3776)

I/O interface.

101 oil 10! Ill

(5357)

(7006)
(7510)

111 100 010 000

(7420)

oil 111 111 110

(3776)

oil oil 111 110

(3376)

(5356)

101 oil 101

111 111 111 111

Instruction

101

(6011)
Control Unit Fault Isolation Using TEST-1

2.4.5

It includes testing of the computer interface, timing, register transfers, etc.

(3376)
Requiremerits arid Limitations - This test Ttquneso^^
Test Setup - The following procedures ready the PDP-14 and the computer for testing. If the computer is an

Repeat Step 3 for each remaining instruction.

To verify RIM was loaded correctly:

integral part of the system and the BIN Loader is maintained in the computer's memory, this part can usually be

skipped.

To set up the equipment:

Set SR to 7756g

If necessary, connect the PDP-1 4 to the computer using the instructions in Paragraph 2.4.2.

Depress LOAD ADDR

If necessary, toggle in

Depress EXAM

Compare MB contents with the first instruction in Table 2-3. (For PDP-8/E, set selector switch to

MD position.)
e.

RIM Loader and load the binary tape loader using the instructions in Paragraph

2.4.3.
3.

If necessary, load TEST-14 diagnostic tape using the instructions in Paragraph 2.4.4.

Procedures - To run TEST-14:

Repeat Steps c and d for remaining instructions.
If necessary, turn on computer, teleprinter, and PDP-14.

If an instruction was loaded incorrectly, set

SR to the address of the instruction then press LOAD

ADDR. Next, set SR for "correct instruction content," then depress DEP.
7.

® Teletype

After verifying RIM is correctly loaded, set SR to 7756o then depress LOAD ADDR.

Depress computer STOP key.

Address TEST-14 program by setting SR to 0200g, then press LOAD ADDR key. The switch settings

trademark of Teletype Corporation.
PDP-8/I - If top of SR switch is out, the bit is a binary 1 otherwise it is a binary 0.
PDP-8/L or PDP-8/E - If SR switch is up, the bit is a binary 1 otherwise it is a binary 0.
is a registered

for 0200„ are:

000 010 000 000

;

2-16

(continued on next page)

Define the test operation by setting the SR as follows. If Control Unit C20 and D20 module slots are

13.

If the program types:

empty, set SR to:

PDP-14 HUNG

012
000

678

345
000

9 10 11

RUN light goes off, check if 5 Vdc is present at the PDP-14 backplane. Then substitute
M741 (module slot AB23) and re-run test by setting SR to 020 Ig and depressing LOAD ADDR key.

or computer

If this action does not correct fault, re-install original M741

and substitute M745 (module slot AB18).

Then re-run test.
If C20 and

D20 contain modules, set SR to:
1 4.

000 000 000 000

If the computer detects other malfunctions, it types a 2-letter code (flanked by asterisks) followed by

a brief description of the test or defining the faihng error condition. This code identifies the module or

The program responds to SR bits

Action

Selection
1

Loop on Current Test
Don't Loop

tried.

Don't Halt on Error
Halt on Error

modules that should be substituted to remedy the malfunction. Table 2-4 lists the error codes, the
respective module slots, and the type of module. Where more than one module is listed, substitute
first module then re-run test. If this action does not correct fault, restore original module then substitute second module listed and re-run test. Continue this practice until all listed modules have been

through 6 as follows:

15.

If the computer detects a register error, the error printout can be as follows:

BASIC GATING AND INTERFACE TESTS

**AA **

Don't Print Errors
Print Errors

OLD

Long Test

GOOD

BAD~^

Short Test

INPUT

0002

0000

Repeat All Tests

INPUT

0003

0001

Stop at End of Tests

INPUT

0006

0004

Spare Register Not Plugged In

INCORRECT REGISTER CONTENTS

Spare Register is Plugged In

In the example shown above, the error designator is AA.

Press START key on computer.

The operator can go to the module-call
The tests being performed
involve some of the basic gating of the PDP-1 4 and the PDP-8E/8I/8L-to-PDP-l 4 interface module.
The failing register was the Input Register (or possibly the Output Register, as it is impossible to tell at
this point in the testing scheme). Since the old contents of the register are not important, there is no
entry in that column. The GOOD Column lists the data entered by the test program. The BAD
table (Table 2-4) and look up AA, or he can analyze the rest of the message.

The program responds by typing:

HOW MANY BOXES?
I

Respond to this query by typing the number 0, then press the carriage return (RETURN) key.

The program then types:

Column lists the incorrect register contents. Analysis of the typeouts indicate a problem with the

HOW MANY O BOXES?
The program then types:

Respond to this query by typing the number 0, then press the RETURN key.

The program then begins testing the PDP-14 Control Unit.

If the Control Unit is operating correctly,

BIT^

01 2

0002
0003
0006

000
000
000

345 678 91011
000 000
000 000
000 000
1

the program types the following in 1.5 to 2 minutes:
16.
10.
11.

If the program types:

BIT->

0000
0001

0004

345 678
000 000 000
000 000 000
000 000 000

01 2

9 10 11

Bit 10 does not compare

PASS 1 COMPLETE
If the Control Unit is malfunctioning, the program types an error statement as explained in Step 14.

Binary Equivalent

Octal

Binary Equivalent

Octal

HOW MANY HALF S BOXES?

BAD Column

GOOD Column

Respond by typing the number 0, then press the RETURN key.
8.

_^__^^

gating of bit 1 0.

more than one register can be affected in a test. In the example shown below, gating
between the Spare Register and PCI was being tested. Since the data in the Spare Register was
destroyed, both registers contained the wrong numbers when the test was completed. The number
It is possible that

following the error code is the PDP-14 instruction.

PDP-14 STOPPED
** AO**

INSTRUCTION

then substitute M741 (module slot AB23) and M742 (module slot AB22).
1 2.

If necessary, restart test program and re-run tests.

set SR to 0201 g , then press

queries.

0334

(JMR)

TEST

OLD

GOOD

BAD

SPARE

3642

3600

PCI

0000

3643

3600

To do this without redefining the configuration,

LOAD ADDR key. The program resumes testing without configuration

(continued on next page)

2-17

17.

If more information is desired about a malfunction after an error stop, depress computer

The test then continues until another error stop or the test is completed.

key.

CONTINUE

Table 2A (Cent)

If a series of error

Test Program Error Code/Module Location Cross Reference

diagnostics is desired, set SR=1 (continue after error).
If no failure has been located with the above program tests, continue testing

by performing storage

module test, Paragraph 2.4.6.

Error

Location/

Typed

(Type)

**AA**

ABI8
^''

**AC**

(Type)

Error

Module

Code

Location/

Typed

(Type)

**BN**

Same as **BH**

**B0**

Module Function

Test Program Error Code/Module Location Cross Reference

**AW**

CD22

(M744)

Comparator

(M740)

Instruction Decoder

AB23
AB24

(M741)

AB24

(M740)

Instruction Decoder

C23

(M746)

Instruction Reg, 0—05

C23

(M746)

Instruction Reg, 0—05

D23

(M746)

Instruction Reg, 06—1

D23

(M746)

Instruction Reg, 06—1

(M745)

Module

Error

Module Function

Computer Interface

Code

Location/

Typed

(Type)

Module Function

—

**AH**

Same as **AD**

**AI**

AB18

rM745)

Computer Interface

B19

rM106'l
|^M249j

Memory Port

AR73

rM74t\
*,-- y

\Anir>r Q+o+«<.
^^^^^^ o«^ Xirvi^Tirt

fuioe')

[U249] Memory Port
Input Reg, 0-05

B17

**AX**

Same as **AJ**

* * RP* *

Same as **B0**

**AY**

Same as **AJ**

**B0**

Same as **BH**

**AZ**

Same as **AJ**

**BR**

Same as **B0**

**BA**

Same as **AJ**

**BS**

Same as **BH**

**BB**

Same as **AJ**

**BT**

Same as **B0**

Major States and Timing

(M746)

Input Reg, 06-1

rf^n

r-Kir-i,t^\

*^. ..

«^i.

V.J.VX/'-tO^

(juipui i^eg, u— U3

(M746)

Output Reg, 06-1

C19

(M747)

Program Counter 1, 0-05

D19

(M747)

Program Counter 1, 06-1

**BC**

Same as **AJ**

**BIJ**

Same as **BO**

CI 8

(M746)

D18

(M746a

Memory Buf, 0-05
Memory Buf, 06-11

**BD**

Same as **AJ**

**gV**

Same as **BJ**

**BE**

Same as **aj**

**BW**

Same as **B0**

**gp**

Same as **aJ**

**BX**

Same as **BH**

**BG**

Same as **AJ**

**BY**

Same as **BH**

**BH**

CD24
AB22

(M743)

I/O Interface

**BZ**

Same as **BJ**

(M742)

Switch and Pwr Control

AB23

(M741)

Major States and Timing

**CA**

Same as **BJ**

AB24

(M740)

Instruction Decoder

**CB**

Same as **BH**

C23

(M746)

Instruction Reg, 0-05

D23

(M746)

Instruction_Reg, 06— 1

**cc**

Same as **BH**

**CD**

AB18

tM745)

B19

Memory Port
f^^^
\^M249j

>^<-

j^^

U...^

iii.,i^i^

CI 8

(M746)

D18

(M746)

Memory Buf, 0-05
Memory Buf, 06-1

-A«?a

(M741-)

4fejor States and Timing

AB24

(M740)

Instruction Decoder

AB24

(M740)

Instruction Decoder

C23

(M746)

Instruction Reg, 0-05

C23

(M746)

Instruction Reg, 0-05

D23

(M746)

Instruction Reg, 06—1

D23

(M746)

Instruction Reg, 06—1

C19

(M747)

Program Counter 1, 0-05

AB24

(M740)

Instruction Decoder

(M746)

Instruction Reg, 0—05

(M746)

Instruction Reg, 06-1

**AJ**

D19

(M747)

Program Counter 1 06-1

C23

CI 8

(M746)

Memory Buf, 0-05

D23

D18

(M746)

Memory Buf, 06-1

AB24

(M740)

Instruction Decoder

C23

(M746)

Instruction Reg, 0-05

D23

(M746)

C2I

**AK**

Same as **AJ**

**AL**

Sameas**AJ**

Instruction Reg, 06-1

_**AM**

Sameas**AJ**

(M746)

Program Counter 2, 0-05

**AN**

Same as **AJ**

D21

(M746)

Program Counter 2, 06-1

CI 8

(M746)

Memory Buf, 0-05

**AO**

Same as **AJ**

D18

(M746)

Memory Buf, 06-1

**AP**

Same as **AJ**

**AQ**

Same as **AJ**

**AR**

AB23

(M740)

Instruction Decoder

C23

(M746)

Instruction Reg, 0-05

D23

(M746)

Instruction Reg, 06-1

C20

D20
CI 8

D18

AB24

(M747)
(M747)

(M746)
(M746)
(M740)

Memory Buf, 0-05
Memory Buf, 06-11

(M746)

Instruction Reg, 0-05
Instruction Reg, 06—1

Same as **AD**

**AG**

Same as **AB**

D23
**AS**

Instruction Decoder

(M746)

**AF**

C23

Spare Reg, 06-11

C23

Same as **AB**

AB24

Spare Reg, 0-05

D23

**AE**

2-18

Typed

Module Function

Same as **AJ**

(M746)

AB24

**AD**

Location/

**AV**

A17

D17

**AB**

Module

Code

Table 2-4

Module

Code

Error

—
—
—

(M741)
(M740)
(M746)
(M746)

—
—
—
—

Instruction Decoder

Instruction Reg, 06-1

(M741)

Major States and Timing

CD22
AB24

(M744)

Comparator

(M740)

Instruction Decoder

C23

(M746)

Instruction Reg, 0—05

D23

(M746)

Instruction Reg, 06-1

Same as **AJ**

**AU**

Same as **AJ**

**gj**

CD24
AB24

(M743)

I/O Interface

(M740)

Instruction Decoder

AB24

(M740)

Instruction Decoder

C23

(M746)

Instruction Reg, 0-05

C23

(M746)

Instruction Reg, 0-05

D23

(M746)

Instruction Reg, 06— 1

D23

(M746)

Instruction Reg, 06-1

CI 9

(M747)

Program Counter 1, 0-05

D19

(M747)

Program Counter 1, 06—1

AB22

(M742)

Switch and Pwr Control

**BK**
**BL**

**pp**
CE*

Same as **BJ**
Same as **BH**

Instruction Reg, 0—05

AB23

**AT**

Same as **BH**

—
Major States and Timing

—
—

Computer Interface

**B1**

**BM**

AB22

(M742)

Switch and Pwr Control

AB24

(M740)

Instruction Decoder

CD24
AB24

(M743)

I/O Interface

C23

(M746)

Instruction Reg, 0—05

{M740)

Instruction Decoder

D23

(M746)

histruction Reg, 06-1

C23

(M746)

Instruction Reg, 0-05

D23

(M746)

Instruction Reg, 06—1

Control Unit I/O Interface Fault Isolation Using TEST-14

2.4.6

Computer then types:

HOW MANY HALF S BOXES?

Test Summary — This test checks the I/O interface and I/O timing functions for the Control Unit.

Respond to this query by typing the number 1 then press the RETURN key.
,

Requirements and Limitations — This test requires that the Control Unit be able to pass the tests in Paragraph
2.4.5.

In addition, an M232 Storage module is a necessary item for this test.

The program automatically begins testing the Control Unit and the I/O interface. If they ^re both
operating correctly, the computer types the following in approximately two minutes:

Test Setup — The following steps ready the PDP-14 and the computer for testing:
1

If necessary, connect the PDP-1 4 to the computer using the instructions in Paragraph 2.4.2.

If necessary, toggle in

If necessary, load the TEST-14 diagnostic tape using the instructions in Paragraph 2.4.4.

Tag all I, O, and A Box cables at Control Unit end, then disconnect all I, O, and A Box cables at

PASS 1 COMPLETE
10.

**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0000
**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0001
**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0002
**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0003

RIM Loader and load binary tape loader using the instructions in Paragraph 2.4.3.

Control Unit end.
5.

If the I/O interface is malfunctioning, the computer types out an error message such as:

The above example indicates a problem in the I/O interface of the PDP-14. The operator can refer to

Insert an M232 Storage module in module slot C32 (the first

the module-call table (Table 2-4) for error BH after reading this message, or he can further analyze the

O Box cable slot).

message.
iVoce^/wre — To run TEST-14:
11.

When testing is complete, turn off the PDP-14, remove M232 Storage module, and reconnect I/O
cables. If necessary, continue fault isolation using the procedures in Paragraph 2.4.7.

If necessary, turn on computer, teleprinter, and PDP-14.

Depress computer STOP key.

To address the TEST-1 4 program, set SR to 0200g then press the LOAD ADDR key.

To define the test operation, set the SR as follows. If Control Unit module slots C20 and D20 are

Output Fault Isolation Using TEST-1

2.4.7
,

Test Summary — This test is performed only if a fault prevails but cannot be located with the tests in Paragraphs
2.4.5 and 2.4.6. This text exercises all

O Box functions except the output drivers.

empty, set SR to:

Requirements and Limitations — This test requires that the O Box 1 1 5 Vac (or dc output voltage) be discon-

000 000 100 000

nected to prevent equipment damage.
If C20 and D20 contain modules, set

SR to:
Test Setup — The following steps ready the PDP-14 and the computer for testing:

000 000 000 000
The program responds to SR bits

through 6 as follows:
Action

Selection

If necessary, connect the PDP-14 to the computer using the instructions in Paragraph 2.4.2.

If necessary, toggle in

RIM Loader and load the binary tape loader using the instructions in Paragraph

2.4.3.

Loop on Current Test
Don't Loop
Don't Halt on Error

If necessary, load TEST-14 into the computer using the instructions in Paragraph 2.4.4.

Turn off and disconnect 1 1 5 Vac (or dc) for output drivers.

Tag all I, O, and A Box cables at Control Unit end, then disconnect all I and A Box cables at Control

Halt on Error

Don't Print Errors

Unit end.

Print Errors

Long Test

Insert all

O Box cables and M232 modules in the first O Box cable slots of the Control Unit.

Short Test

Repeat All Tests

Procedures — To run TEST-14:

Stop at End of Tests
Spare Register Not Plugged In

If necessary turn on computer, teleprinter, and PDP-14.

Depress computer STOP key.

To address the TEST-14, set SR to 0200„ then press LOAD ADDR key.

Spare Register is Plugged In
5.

Press START key on the computer.

The program responds by typing:

HOW MANY BOXES?

Answer this query by typing the number 0, then press the carriage return (RETURN) key.

Computer then types:

HOW MANY O BOXES?
Respond by typing the number 0, then press the RETURN key.

(continued on next page)

2-19

Select the desired operation for the test using SRO through SR6 as follows:

Set As

Action

Test Summary — This diagnostic test compares the contents of the ROM with information that defines what the
ROM should contain. Sequential address tests are performed first, then random address tests are implemented to
verify ROM operation and content. The diagnostic program provides error halts and error messages in the same

Loop on Current Test
Don't Loop
Don't Halt on Error
Halt on Error

manner as for TEST- 14.

Don't Print Errors

A user-furnished paper tape defines what instructions the ROM should contain. This tape is normally generated

Print Errors

during initial programming and is updated to reflect any

Long Test

the computer's memory using a LOAD-14 tape; i.e., the user enters LOAD-14 into memory and uses this program

Short Test

4
6

the tape is

Spare Register Not Plugged In

input/output tests).
Test Setup — The following procedures ready the PDP-14 and the computer for testing:

The program responds by typing:

HOW MANY BOXES?
I

Respond to this query by typing the number 0, then press the RETURN key.

If necessary, connect the PDP-1 4 to the computer using the instructions in Paragraph 2.4.2.

If necessary, toggle in

The program then types:
3

Respond to this query by typing the number 0, then press RETURN key.

To enter LOAD- 1 4 tape
a.

Turn on computer and depress STOP key.

To address the BIN loader program set SR to 7777g

Press

Place LOAD-14 tape in applicable paper-tape reader.

The program then types:

HOW MANY HALF S BOXES?

Respond to this query by typing the total number of O Boxes and M232 Storage modules in use, then
press the

RETURN key.

The program then begins testing the PDP-14.

If the Control Unit, I/O interface and

O Boxes are
4.

operating correctly, the program types the following message in one to two minutes:

PASS 1 COMPLETE
10.

If an

O Box is malfunctioning, the program types out an error message such as:
**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0000
**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0001
**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0002
**BH** SYF 377 LEFT ON OUTPUT OR TEST FLOP ALWAYS SET BY TYN 0003

The above example denotes a problem in either the O Box or the I/O interface. However, since the I/O
interface has already been checked, the fault must be in the O Box.

12.

Substitute the O Box modules related to the malfunction beginning with the level 2 module first (see

Figure 2-3 for O Box hierarchy).
If this action does not correct fault, restore original module, then substitute next higher level.

If this

action does not correct fault, continue with next higher level.
1

For high-speed reader, set SRO to 0. For low-speed reader, leave SRO set to 1
With reader on, depress START key.
When tape stops, verify that the computer's accumulator (AC) contains all Os, then remove tape.

Address LOAD-14 tape by setting SR to 7400c and depressing LOAD ADDR.
Select the appHcable paper-tape reader.
reader, leave SRO set to

Load tape into applicable reader, then depress START.

When tape loading is complete, remove tape and turn off reader.

Procedure — To load and use VER-14, proceed as follows:
1

Load VER-14 using the instructions in Paragraph 2.4.4.

Address VER-1 4 by setting SR to 6000g then depressing LOAD ADDR

Select the memory bank to be tested using the following:

SRI

If all higher level items have been substituted and the fault is still not corrected, turn off 1 1 5 Vac (or

If all modules have been substituted without correction of fault, substitute

For high-speed reader, set SRO to 0. For low-speed

SRO

dc source) to O Box and substitute output driver related to fault.
15.

LOAD ADDR key.

To enter ROM tape:
a.

11.

13.

RIM Loader and load binary tape loader using the instructions in Paragraph

2.4.3.

HOW MANY O BOXES?

ROM tape. The information content of the ROM tape is always unique; therefore, verify that
the correct one for the ROM you are checking.

Requirements and Limitations — This test requires that the Control Unit be able to run TEST-14 (exgluding

Spare Register is Plugged In

Press computer START key.

ROM changes. The content of this tape is entered into

to enter the user's

Repeat All Tests
Stop at End of Tests

ROM Fault Isolation Using VER-14 (MAINDEC-14-D1 AB-D)

2.4.8

BANK
First Bank

Second Bank
Third Bank

O Box.
1

Fourth Bank

(continued on next page)

2-20

Set SRI

Test Setup — The following procedures ready the PDP-14 and the computer for testing:

and SRI 1 to 0. (See following for the program operation selected)

SRIO
Loop on Data Error

If necessary, connect the PDP-14 to the computer using the instructions in Paragraph 2.4.2.

If necessary, toggle in

Don't Loop on Data Error

SRll

Procedure — To test an Accessory Box using ABE-14:

Halt on Data Error
5.

Turn off PDP-14, then power up PDP-14 while holding START/STOP switch at STOP.

Depress computer START key.

Turn on computer, teleprinter, and PDP-1 4.

NOTE
Reset all retentive memories before beginning test. Ensure
K272 memories are not latched (switch is in center position)

Depress PDP-14 ST ART/ STOP switch to START. The program now begins testing.
If the

and that A Box (with K272 modules) is in upright position.

ROM content and operation are correct, the program rings the teleprinter bell after each program

pass.
2.

ROM content or operation is incorrect, the program types out an'error message, then halts.

If the

10.

Error messages can be for either the sequential or random address tests as shown below:

ADDR

GOOD

0470
0471
0472
0473
0474
0475
0476
0477

"2457

2031
1075

1657

5477

3056
0344
3456

BAD
0000
0000
0000
0000
0000
0000
0000
0000

See

Note 2

Below

0061

2425

0071

3177
2061
3561
7015
3172
2525
2617
2225

0101
0111

0121
0131
0141
0171
6261

0425
1177
0061
2561 S
5015
1172
0525
0617

Loop on Current Test
Don't Halt on Error
Halt on Error

See

Note 3
Below

Don't Print Errors
Print Errors

Repeat Timing of Current Output (allows timer adjustment)
Don't Repeat Timing of Current Output

Depress computer START key. Program then types:

A BOX IS CONNECTED TO SLOT
5.

read for the program entry.
6.

0470—0477 are bad.

Respond to this statement by typing the connector slot letter for the A Box. (Refer to Figure 2-1 for
connector slot designations and locations.)

The program then types:

IDENTIFY THE HARDWARE ASSOCIATED WITH EACH ADDRESS BY TYPING
T FOR TIMER, M FOR RETENTIVE MEMORY, ALL ELSE EMPTY

This could be caused by an open wire (number 47 in this

example) on the G922 module or by an open transistor on
the G924 module.

0000

3. In the random address test, bit

1 is being dropped. This
could be caused either by a transformer on the G923 module

Using Figure 2-4 as a guide for relative addresses, type:

T if module slot A04 contains a K302 or K022
M if module slot A04 contains a K274 or K272
if module slot A04 is empty

or by the integrated circuit associated with that transformer.

Accessory Box Fault Isolation Using ABE-1 4 (MAINDEC-14-D8AB-D)

NOTE

A Box circuits.

Each A Box must be checked individually. The content of an A Box is defined during the test so that the pro-

gram can perform a timer or retentive memory test. For each timer, the program types out its delay interval.
Each retentive memory is checked for a power-down and power-up sequence. Upon successful completion of the
test, the teleprinter bell rings.

Action

Set As

Don't Loop

0225^

Test Summary — This diagnostic checks the timer and retentive memory functions performed by

Select program operation using the following (usually, the SR is set to OOOOg ):

The first column defines the address, the second (GOOD)
denotes the program entry, and the third (BAD) the result

2. In the sequential address test, addresses

NOTES
1

To address ABE-1 4 program, depress computer STOP key. Set SR to 0200g then depress LOAD

ADDR key.

RANDOM ADDRESS TEST
BAD >
ADDR
GOOD

SEQUENTIAL ADDRESS TEST

2.4.9

If necessary, load ABE-14 tape using the instructions in Paragraph 2.4.4.

Don't halt on Data Error

RIM Loader and then load binary tape loader using the instructions in Paragraph

2.4.3.

K272 Retentive Memory modules have only one memory circuit
and use only the even numbered relative address for a module
slot. For a K272 module, answer "0" for the second (oddnumbered) address. K274 modules have two memory circuits
and use both relative addresses.

Error messages and error stops are provided for malfunctions.

Requirements ami Limitations — This test requires that the Control Unit is able to successfully complete its portion of TEST-1 4.

(continued on next page)

2-21

10.

Program replies by typing:

Table 2-5

0001

Accessory Box Module/ABE-14 Error Code Cross Reference

Respond by typing T, M, or

for relative address 0001

ABE-14 Error Code

Continue until the A Box configuration is defined. After the reply for address 0017g the program is
,

automatically run.
11.

For each address having a correctly operating timer, the program checks the timer interval and types it

on the teleprinter. An example follows:

OUTPUT 0000 SET ON IN ABOUT 00000010 MILLISECONDS
OUTPUT 0001 SET ON IN ABOUT 00004980 MILLISECONDS
OUTPUT 0006 SET ON IN ABOUT 00000203 MILLISECONDS
OUTPUT 0007 SET ON IN ABOUT 00032513 MILLISECONDS
12.

For each address containing a faulty timer, retentive memory, or storage module, the program types
an error message such as the one that follows. Refer to Table 2-5 for modules to be substituted for

Accessory Box Module Type

**BL**
**BN**
**BQ**
**BX**
**BY**
**CB**

K207,K161,K135

**CF**
**CG**

K302

**CH**

K272, K274, K022, K302, K207, K161, K135

error codes.

**CH** TIME OUT ERROR, OUTPUT 0000

2.4.10

NOTES
1

For additional information on the fault, depress computer

outputs on or off, and store and type out data entered into the PDP-14 Output Register. The ROL-14 program

ABE-14 currently tests timers up to a maximum of 61

can be implemented while the PDP-14 is idle or is running a computer or a ROM program.

The following tocatrons can be changed once
ABE-14 is loaded to extend the timing capability of ABE-14.
Change To

Was

0060
0626
0763

7665
1363
0113

7761
1046

program:

0000

An example follows.

OUTPUT 0010 SET ON IN ABOUT 00000000 MILLISECONDS
OUTPUT 001 SET ON IN ABOUT 00000000 MILLISECONDS
1

For each address containing a correctly operating memory circuit, the program types a message such
as:

OUTPUT 0010 SET ON IN ABOUT 00000000 MILLISECONDS
OUTPUT 001 SET ON IN ABOUT 00000000 MILLISECONDS
OUTPUT 001 2 SET ON IN ABOUT 00000000 MILLISECONDS
OUTPUT 0013 SET ON IN ABOUT 00000000 MILLISECONDS

IX, lY

Interrogate a single input (IX) or output (lY) and type its state (0 or 1).

YN,YF

Set a single output on (YN) or off (YF) (Enabled only when SR switch

Clear all outputs, and stop ROL-14 execution of the control program if currently

After successfully completing this phase, the program tests each retentive memory for retaining its on
state through a power-down, power-off, and power-up sequence.

For this test, it types:

POWER DOWN THE PDP-14, THEN POWER IT UP AGAIN, DEPRESS PDP-8 CONTINUE
16.

If a retentive memory malfunctions, the program types an error message such as the following.
Table 2-5 defines the A Box modules to be substituted for the error codes.

POWER DOWN THE PDP-14, THEN POWER IT UP AGAIN, DEPRESS PDP-8 CONTINUE
**CG** ONE LOST IN POWER SHUTDOWN BY RM0013
18.

Enable YN and YF commands.

SR0=1
SR10=

Store and type any numbers loaded into the Output Register.

SRIO =

Don't store any further values but type any currently stored.

SRll = 1

Clear the storage buffer and stop typing Output Register values.

The following commands and features are available while the PDP-14 is not running a program:
Sn

Start program at location n.

Read a binary tape on the low-speed reader.

Read a binary tape on the high-speed reader.

This test is repeated to determine if each retentive memory retains its off state. Hence, the above

message is repeated.
17.

The teleprinter bell rings when the A Box test is complete.

Test Requirements and Limitations - This test requires that the controller be able to perform at least some of
the I/O functions; i.e., the controller does not have a major or complete failure.

The buffer area that stores output words can overlap (and destroy) the Binary Loader; therefore, it is necessary
to reload the Binary Loader after using ROL-14 or else relocate the Binary Loader.

The YN and YF commands are enabled only when SRO is set to 1
against unwanted outputs being accidently turned on or off.

2-22

is set on).

in progress.

15.

When the PDP-14 is

4dle, ROL-14 can be used to read a tape from either the high- or low^eed reader.

The following commands and features are available while the PDP-14 is idle or is running a ROM or computer

)cation

For each address containing a correctly operating K022 module, the program denotes the output was
set on immediately.

14.

Test Summary - This program is an on-line program that allows the user to interrogate inputs and outputs, set

CONTINUE key.
seconds.

13.

Fault Isolation Using ROL-14

This feature provides added protection

Test Setup — The following procedures ready the PDP-14 and computer for using ROL-14:
1.

If necessary, connect the PDP-14 to the computer using the instructions in Paragraph 2.4.2.
If necessary, toggle in

RIM Loader and load the binary (BIN) tape loader using the instructions in

Paragraph 2.4.3.
3.

If necessary, load ROL-1 4 using the instructions in Paragraph 2.4.5.

Procedures — To use ROL-14:
1.

If necessary, turn on computer, teleprinter, and PDP-14.

To address ROL-1 4, depress computer STOP key, set SR to 7000g then depress LOAD ADDR key.

Set up SR for the desired program operation using the information in Paragraph 2.4.4.

Depress START key. The program is now available for testing.

To interrogate an output, type lY followed by the octal address of the output. Then depress the

carriage

RETURN key. The program responds by typing the state of the output. For an off state,

the program types a 0; for an on state, the program types a 1
6.

To interrogate an input, type IX followed by the octal address of the output. Then depress the
carriage

RETURN key. The program responds by typing the input state (0 for off or

for on).

To set an output on or off, set SRO to 1 then type YN (for on) or YF (for off) followed by the octal
address of the output. Then depress the carriage RETURN key.
,

2-23

CHAPTER 3
THEORY OF OPERATION

3.1

GENERAL
INPUT

This chapter contains theory of operation for the PDP-1 4 Controller in two primary levels: a block diagram level

M746

and a detailed level.

3.2

SYSTEM RELATIONSHIPS

BAC

3.2.1

00-11-

Operating Configurations and Modes

MEMORY

MEMORY
PORT
MZ49

BUFFER
M746

ROM

—

ADDRESS
PROGRAM
\
COUNTER

M746

To reiterate,
t

a stand-alone application does not normally interface with a computer.

A PDF- 14 Controller used in a stand-alone
REGISTER

M746

A monitoring or a monitoring and control application entails the use of a computer. A controller used in a
monitoring or a monitoring and control application can operate in the internal mode (with interrupt operation)
or the external mode.

MEM

DONE

^iV.

OUTPUT

application therefore only operates in the internal mode (all instructions provided by the ROM).

IR
00-11

INST.

7^
The primary operating configurations (or applications) for the controller are described in Chapter 1

PROGRAM
COUNTER

G922
G923
G924

M746

BUS 00-11

P
u

T
AC

E
R

00-11

DESTINATION

SOURCE
REGISTER.^
SATING

(SOR)

(LD)

AN-

LOAD PULSE

SKIP-"
INT.

The interrupt operation is basically a cycle-steal operation in which the ROM program is interrupted so that the
controller can execute one computer-supplied instruction. After this instruction is executed, the

automatically resumes at the point it left off.

RQST

ROM program

The principal use of this operation is to provide test results to the

BMB 03-8-

COMPUTER

00-11

INTERFACE

BIOP'S-

TO
STORAGE

MAJOR
STATES

DEVICE

AND

SELECT
M921

TIMING

I/O

INSTRUCTION

DECODER

I/O INST.

INTERFACE

CONTROL

FUNCTION vMODULES

'AND 1,0,
AND A
BOXES

SAMPLE
RETURN

computer on an as-needed basis and to change the operating mode to external.
In the external mode, the computer provides the instructions.

To enter the external mode, the computer must

TEST RESULT

request a PDP-1 4 interrupt and then issue an instruction to enter the external mode. In the external mode, the

ROM program is suspended and the computer provides all program instructions. To return to ROM (or internal)

START/STOP

SWITCH

AND
POWER

operation, the computer must issue an instruction to leave the external mode.

CONTROL

MEMORY
BANK
ENABLE

M742

3.2.2
3.2.2.1

Control Unit Block Diagram Description
General — Figure 3-1 shows the major registers, control elements, and interfaces that constitute the

Figure 3-1

PDP-1 4 Control Unit, Block Diagram

Control Unit. For description purposes, mode switching is represented as a double-pole, double-throw, switch.

When this switch is placed to the INT position, the Control Unit provides the ROM with a timing input and an
address. Thus, the Control Unit fetches instructions from the ROM. When momentarily placed to EXT, an interrupt operation is active.

The Control Unit receives one instruction from the computer, then resumes operation

with the ROM (swritch returns to INT).
tions from the computer.

When placed to EXT and held there, the Control Unit receives its instruc-

3.2.2.2

Bus Arrangement and Internal Transfers - A 1 2-bit data transfer bus, designated BUS 00- 1 1 handles
,

the majority of internal transfers. This bus interconnects the major registers shown in Figure 3-1

each register are directly connected to BUS 00-1 1

The inputs of

The outputs, however, are connected to the bus by gating

structures on the respective registers. Thus, for a transfer between registers, one register is specified as the source

3-1

The source register receives an output gating pulse while the destination

The contents of a register placed on the bus then can transfer back to the same

provided to the MB Register via the Memory Port logic or to BUS 00-1 1 via the Input Register (Figure 3-1).

The interface provides the control for these functions.

It also controls the gating of Output Register data to the

computer's accumulator.

decrementing) of counters. (The decrementing capability is not presently used.) All register transfers are jamtransfers.

3.2.2.6

Control - The Control Unit uses three major control sections as shown in Figure 3-1

The switch and

power control area senses power-up and power-down conditions and initiahzes the system. For power-up
3.2.2,3
use.

Registers - Table 3-1 lists the Control Unit registers, their source and destination codes, and their major

The least significant octal digit of a register transfer instruction defines the destination register. The more

conditions, it also starts Control Unit timing. This control area also interfaces with the START/STOP and

CONTINUE switches for manual control functions.

significant octal digit defines the source register.

The major states and timing control area provides the basic timing for fetching and executing instructions.

Table 3-1
functional area also contains logic for storing test results and evaluating these results with Decision instructions.

PDP-14 Major Registers
Source Code

Destination Code

The instruction decoder is the third major control area.

Major Use

It,

as the name indicates, decodes the instructions and

provides the discrete control signals for executing them. In addition to these control signals, the decoder gene-

Dummy (No Register)

000 = Og

None

Implied register. Can be used for transfer

rates the source gating and destination load strobes for internal transfers.

of all Is into a register.
Instruction Register (IR)

001 = 1,

001 = Ig

Stores the instruction for decoding and

execution.

Memory Buffer (MB)

010 = 2g

010 = 2,

011=3s

011=33

Program Counter 1 (PCI)

100 = 4g

100 = 43

ROM Block Diagram Description

The ROM is organized in 1024 (IK) word increments called banks. Up to four banks can be used for a total

Temporary storage for instruction fetched
from ROM or entered from computer via

Memory Port.
Spare Register (Optional)

3.2.3

retrieve instructions.

A bank is selected by the two most significant bits (MSBs) of PCI

These bits are decoded

by the switch and power control module (M742). This module then selects the applicable bank. The remaining

Utility register; not normally used.

Stores the address for the next

word capacity of 4096. Each bank is a complete functional entity; i.e., it contains all the necessary circuits to

ROM in-

struction. It is an incrementing-type regis-

10 bits of PCI select one of 1024 locations within the bank.

The ROM operates asynchronously with the Control Unit. For retrieval of an instruction, the Control Unit ad<iress«s the

ter used as a counter.

ROM and provides a MEM GO pulse. TheROM, in turn, selects thelocation and transfers the content

of the location in an internal output buffer. The outputs of this buffer then set corresponding bits of the MB

Program Counter 2 (PC2)

101 =5^

101 -Sg

Stores the return address for a subroutine.

Input Register

110 = 6g

None

Input buffer for data transfer from computer. Its major use is for loading of PCI

or PC2 from the computer.

None

Output Register

110 = 6g

Output buffer for data transfer to the

ROM provides a MEM DONE timing output. This pulse denotes the instruction

access cycle is complete and signifies an instruction is available.
it is cleared at

the start of another instruction access.

The instruction remains in the MB Register until

To access one instruction requires about 450 to 500 nano-

seconds, however, this can vary from bank to bank without detriment to system operation since asynchronous

timing is used.

computer.
3.2.4

3.2.2.4

I/O Interface - This element, as the name implies, interfaces storage modules and I, O, and A Boxes with

the Control Unit.

As part of this function, the I/O interface receives IR inputs (specifying the I/O address) and

control inputs (denoting the type of instruction) from the instruction decoder.

From these inputs, it selects the

input or output circuit and initiates the desired function. For Operate instructions, this interface simply specifies the function (SET,

RESET, or CLEAR). For Test instructions, the I/O interface also compares the test state

with the program-defined state. The result is then temporarily stored for evaluation by a Decision instruction.

Box Block Diagram Description

For Test and Operate instructions, the I/O interface decodes the IR bits and asserts one of eight package select
Unes.

Each package select line is connected to one I Box and two O Box cable slots. When asserted, the package

select line selects one I Box and two

O Boxes (or else a combination of O Box, A Box, or storage modules). For

selection of circuits within the boxes, the I/O interface provides a 4-bit address selection code. This selection

code is provided to all I Box and O Box cable slots.
Figure 3-2 shows the functional relationships of the major elements in an I Box. For selection of the I Box, the

package select hne is asserted and the 4-bit selection code is provided. The MSB of this code and the package
3.2.2.5

Computer Interface - This functional area interfaces the PDP-14 with a computer I/O bus for program-

med data transfers. It has the capabilities for operating with a computer's skip chain or with its program interrupt
facility.

As part of this interface function, the interface interprets computer input/output transfer (lOT) instruc-

tions, selects the operating mode (internal or external), and synchronizes controller operations with the computer

for input and output transfers.

The interface also provides the capabilities for interrupting ROM operation on a

cycle-steal basis so that one computer instruction can be implemented.

3-2

Data from the computer's accumulator is

select input are combined to enable one of two binary-to-octal decoders to respond to the three remaining

MSB is asserted, a decoder
selects one input circuit in octal group 10 through 17 and one in 30 through 37. If the MSB is not asserted, the
selection code bits.

Each decoder selects two input circuits concurrently.

second decoder selects one input in octal group

If the

through 7 and one in 20 through 27. With this arrangement,

two sample return lines are required and the I/O interface must determine which line is to be sampled. For an on
input, the selected circuit asserts the sample return Hne.

Figure 3-3 shows the functional relationships of the O Box. For a turn on (Operate) instruction, the I/O interface
supplies a 4-bit selection code, a package select, and enable set signal.

I/O INTERFACE M743

SELECT

The MSB of the selection code and the

package select enable one decoder circuit. The respective decoder, in turn, decodes the remaining three bits of

SELECTION
CODE
(4 LINES)

the selection code and selects one of eight flip-flops to perform the designated function. For a turn on function,

the respective flip-flop is set to turn on an output.

y//////////////y//////////////////////////A

(reset for all output flip-flops).

It remains set until reset by an

ENABLE RESET or CLEAR

With the flip-flop on, the output driver is turned on.

MSB
KI36

I/O INTERFACE M743

GATE

SELECTION

ENABLE

3 LINES y.

ENABLE

'/'

BINARY-TOOCTAL
DECODER

K1G1

Kiel

LINES

PACKAGE
SELECT

CODE
(4 LINES)

W/////////////////////////////////////////.

NEON LAMP
OR LED
K135
GATE

AC NEUTRAL
3 LINES

ENABLE

K578 ^^^^:^^^^Z//////////////////////////M///Z^

•K578 OR K579 ISOLATED 5VAC
INPUT CONVERTER A K564
DC INPUT CONVERTER CAN
ALSO BE USED,
1

108

278
AC NEUTRAL

%
O^
%

BINARY-TO-

OCTAL
DECODER

K161

'/,

-O

ENABLE SET

I/O
INTERFACE \ ENABLE RESET

^^////////////////////////////////^^^^

M743

^^
•

STORAGE
REGISTER
(4)

CLEAR ALL

AC HOT
'78

K135

AC NEUTRAL

K136
GATE

K136

GATE

GATE
O-t
-O

SAMPLE RETURN
(OUTPUTS 08 TO 178
TO I/O
INTERFACE
M743

#2 (INPUTS ZOs -37a)
SAMPLE RETURN

TO I /O

[-INTERFACE

#1 (INPUTS 08-1781

M743

)

138

AC NEUTRAL

O-l

Figure 3-2

Box Block Diagram

4e-

-o

^//////M

^^^^»K614

68
783.2.5

O Box Block Diagram Description

»K614 OR K616 AC ISOLATED
SWITCH.
K657 DC DRIVER
CAN ALSO BE USED.

The same circuit selection methods are used for O Boxes as for I Boxes. There is one minor difference, however.
Since each O Box (or equivalent) has sixteen outputs and up to sixteen
selection combinations are required for outputs as inputs.

O Boxes can be used, the same number of

However, each asserted package select line selects two

Figure 3-3

O Box Block Diagram

O Boxes concurrently. With this arrangement and a 4-bit selection code (common to all O Boxes), two output
circuits (one in each of two boxes) are addressed concurrently. Again, two sample return lines are required and

the I/O interface must interpret the result for Test instructions. In addition, two sets of function lines (SET and

For a Test instruction, the output circuit is addressed in the manner described above. However, the I/O interface

RESET) are required for Operate instructions.

does not assert a function line. The address selection simply gates the state of the selected flip-flop to a sample

3-3

return line. This line is common to the gated outputs of all 16 flip-flops in a box.

The sample return output is

provided to the I/O interface for interpretation.

Up to 16 timer circuits can be used. Each circuit can provide a delay interval from approximately 0.01 seconds
up to 4 minutes and 45 seconds.

A delay interval is started when the flip-flop associated with the timer is set.

The timer is not considered on, however, until its delay interval has expired.
3.2.6

A Box Description

The A Box addressing and function (SET or RESET) structures are identical to those described for the O Box.

Up to 16 retentive memories can be provided in one A Box by using K274 Retentive Memory modules. Each
module provides two memory circuits and precludes the use of two timers (or two storage circuits). Each mem-

The A Box, however, is used for special circuits such as timers, retentive memory, or storage elements.

ory circuit has an indicator to denote its state (on or off) and a switch to clear (turn off) the memory.

Figure 3-4 shows the functional relationships of the

A Box.

Up to four retentive memories can be provided in one A Box by using K272 Retentive Memory modules. Each
module contains only one memory circuit and precludes the use of two timers (or two storage circuits). Although
a K272 module consumes the space normally allotted for two addresses, it can only be addressed by the evennumbered relative addresses for the A Box. Each K272 memory circuit has a switch to clear the memory.

I/O INTERFACE M743

PACKAGE
SELECT

SELECTION
CODE
(4 LINES)

Testing of

A Box outputs differs from that of O Boxes. Instead of testing the output state of the control flip-flop
O Boxes), an A Box test samples the output of the actual output circuit; e.g., the output of a

(as is done for

timer or retentive memory.

»* K135 CAN ALSO
BE USED

Unused A Box output slots can be used for storage outputs by using a K022 Storage module. Each module
contains two diode gating circuits.

Each circuit gates the output of one control flip-flop to the sample return

line when selected by the addressing circuits.

3.3

INSTRUCTION SET
General

3.3.1

The PDP-14 Controller uses two basic sets of instructions; one for internal mode (ROM) operation and one for
external mode operation.

I/O
INTERFACE

The external mode set includes all of the internal mode instructions plus instructions

that control external mode operations. In addition to these instructions, the PDP-14 musH: recognize and execute

ENABLE RESET

input/output transfer (lOT) instructions from the computer.

tOg*

3.3.2
3.3.2.1

Internal Mode Instruction Set

General — The internal mode instruction set can be divided into five basic classes directly related to the

functions performed. These classes are:

138

»K272

Test — Sample input or output state (on or ofO-

Decision — Jump (or branch) if input or output is in the state defined by the instruction.

Operate — Set output on or off.

Monitoring — These instructions test an input or output and place the test result and other pertinent

EVEN
ADDRESS
14„« ONLY

information in an Output Register for transfer to the computer.

Housekeeping - These instructions, in general, provide the basic address links for performing a pro-

gram efficiently. These instructions include register transfer and subroutine operations.

3.3.2.2

MODULE TYPES
K302 TIMER MODULE
K022 STORAGE MODULE

octal codes and briefly describes the function of each Test instruction.

K272T. RETENTIVE

held in a common TEST flip-flop used for all input and output testing.

K274 J MEMORY MODULES

Figure 3-4

3-4

Test Instructions — Figure 3-5 shows the format of Test instructions.

A Box Block Diagram

It also lists the symbolic and

Note that inputs are designated X and

outputs are designated Y and that each can be tested for an on or off condition. Also note that test results are

= TEST FOR ON
0= TEST FOR OFF

3.3.2.3

001= TEST 0UTPUT = l8
010=TEST INPUT= Zg

°
-

i
i

Decision Instructions — Two basic Decision instructions are used. Figure 3-6 shows the format of

Decision (conditional jump) instructions and defines their codes and function. As mentioned previously, these
4

instructions link the Test instructions with Operate or other Test instructions.

Note that the TEST flip-flop can

be tested for either an on (SET) or off (RESET) state. Observe also that it is reset (if set) after it is tested,
regardless of the test result.

08-78 I/O
PACKAGE SELECT
(1

00a -17a
SELECTION CODE
ADOR ,2 ,4 a 8)

OF 8

(

0=OFF

SAMPLE RETURN LINE

^ =0N

SELECTION:
1= UPPER GROUP

O'LOWER GROUP
I/O CIRCUIT ADDRESS OOOs - 3778
(t OF 256

«YYY OR XXX

NNN=0008 -3778
(PAGE ADDRESS)

Symbolic Code

TYF

Octal Code

10
+

Y Y Y*

Description

Test output for OFF; set TEST flip-flop if output Is

JFF

TYN

14
+

TXF

Test output for ON; set TEST flip-flop if output is ON.

Y Y Y
Test input for OFF; set TEST flip-flop if input is OFF.

JFN

NNN (NNN->PC1); if TEST flip-flop is ON, then clear

5 4
-H

2 4

Test input for ON; set TEST flip-flop if input is ON.

TEST flip-flop (0-*TEST flip-flop).
TEST flip-flop is ON, jump to location specified by
NNN and reset TEST flip-flop (NNN->PC, OBTEST
FLAG). If TEST flip-flop is OFF, continue with next
If

N N N

(377 max)

X X X

TEST flip-flop is OFF, jump to location specified by

+ N N N
(377 max)

+ X X X*

TXN

Function

Octal Code

Symbolic Code

OFF.

instruction.

iqNi_—»

Don't

JFF
Jump if Flop
Is OFF

JFN
Jump if Flop
is

ON
fOFpJ—^

NOTE:

Don't jump

All other PDP-14 instructions have no effect upon the TEST flip-flop.

Test false

Figure 3-5 Test Instructions

Figure 3-6 Decision Instructions

3-5

3.3.2.4

Operate Instructions — Three basic Operate instructions are used. Figure 3-7 depicts the format of

address consists of 12 bits, it can specify any location within a 4096-word ROM; i.e., an unconditional jump can

Operate instructions and defines their codes and functions. Note that an output can be turned on or off.

address any memory location. Figure 3-9 also defines the bit structure of the second word for a jump instruc-

Observe that the upper-most output address is used for a clear-all-outputs function, and therefore cannot address

tion.

a "real" output.

provided to the Output Register. There are no restrictions on the content of the TRM word.
3.3.3
= ON
0=OFF

Similarly, for the 2-word transfer instruction (TRM), the content of the location following the

TRM is

lOT Instructions

12
1

3
1

As mentioned previously, the PDP-i4 must recognize and execute lOT instructions to communicate with a
6

9
1

PDP-8 family computer or PDP-12 computer. Figure 3-10 depicts the format of lOT instructions and defines

their use.

OP CODE

08-7b I/O
(1

0= INPUT

OOg -178
SELECTION CODE
ADDR ,2,4a8)

PACKAGE SELECT
OF 8)

1 =

OUTPUT

—

(

OF 16)

-f-^

FUNCTION (SETS RESET) CONTROL
LINE SELECTION
1= UPPER GROUP
= LOWER GROUP

-I

OP CODE

00„
'B -17b
"B
selection coce
TaDDR 1,2,4 88)

I/O
oi\rv nnt: qci crx
(1 OF 8)

YYY (0008-3768)

OF 16)

SAMPLE RETURN LINE
SELECTION

GROUP
LOWER GROUP

1= UPPER
=

Symbolic Code

Octal Code

Description

SYF

3
+ Y Y Y

Set output OFF (interrupt output circuit, clear retentive

3 4
+ Y Y Y

Set output ON (complete output circuit, set retentive

3 3 7 7

Clear all outputs.

SYN
CLR

XXX OR YYY

memory or storage, or turn off timer).

memory or storage, or start delay timer).

Octal Code

Symbolic Code

TXD

Test Input and Display (test input and place TXD word

TYD
Figure 3-7 Operate Instructions

3.3.2.5

Description

X X X

in Output Register).

7 4

Test Output and Display (test output and place TYD word

+ Y Y Y

in Output Register).

Monitoring Instructions - There are two basic Monitoring instructions. Figure 3-8 illustrates the format

of these instructions and their associated output words. Observe that each display defines which input or output,

whether it is an input or output, the state (on or ofO of input or output, and the state of the TEST flip-flop.
1

3.3.2.6

Housekeeping Instructions - The PDP-14 Controller uses up to nine basic Housekeeping (transfer and

minor arithmetic) instructions. Figure 3-9 shows the format of these instructions and defines their content. Note
that bits 4 and 5 define the type of operation. (Although a transfer and decrement capability is provided, it is

not presently used.) Observe also that bits 6 through 8 define the source register and bits 9 through 1 1 define the

TEST FLOP
STATE
1=0N

destination register. Further, observe that a skip operation is implemented by- transferring the content of PCI

0=OFF

to the transfer bus, incrementing this value, and loading the result back into PCI (corresponding to a code of

0344g).

STATE OF INPUT

OR OUTPUT
1=0N
0=OFF

I/O ADDRESS NUMBER

0=TXD
=TYD
1

There are two 2-word jump instructions ( JMP and JMS) and one 2-word transfer instruction. For jump instructions, the content of the location (NNNN) following the jump instruction defines the jump address.

3-6

Since this

Figure 3-8

TXD and TYD Instructions and Display Words

,2.3,4,5,S,7.8,9,i0.n

^-^

^-h^

'
\

^-h^

FORMAT OF SECOND WORD FOR
UNCONDITIONAL JUMP INSTRUCTIONS
(JMPor JMS)

OP CODE

OPERATION

ROM
BANK NO.
(1 0F4)

DESTINATION
REGISTER

SOURCE
REGISTER

PAGE
OF 4)

0008-3778

1K ROM

Octal

Operation

Not Used

Transfer &

Decrement

Mem Buf

Transfer

Spare Reg

Transfer &.

——

PCi J

Increment

-cr

PC2

Input Reg

Output Reg

Not Used

Octal Code

Function

NOP

No operation.

SKP

Skip next location, PC1+1->-PC1.

JMP

Octal

Dummy

Transfer

Symbolic Code

ADDRESS

4 2 2 4

Unconditional jump to location NNNN

N N N N

(2nd word of 2-word instruction in Memory Buffer),

MB^PCI.

JMS

4 6 4 5

Jump to subroutine at location NNNN

N N N N

(2nd word of 2-word instruction) PC1^PC2, then

NNNN^PCI.

JMR

3 5 4

TRM

4 2 2 6

Transfer next memory word to Output Register

N N N N

{PC1+1^PC1, MB->Output Register).

TRR

X Y

Jump return from subroutine (PC2-*PC1, PC1+1->PC1).

Transfer Register X to Register Y; where X equals Source
Register and Y equals Destination Register.

SKZ

6 3 N 4

Skip next location if Register N Is equal to zero; if
RegN = 0, PCI-H^PCI.

SKE

6 7 N 4

Skip next location if Register N is equal to contents of
PC2.

HALT

RegN = PC2, thenPCI+I^PCI.

Halt the PDP-14 Control Unit.

Figure 3-9 Housekeeping Instructions

3-7

2
1

GN!

Symbolic Code

Octal Code

Description

Symbolic Code

16 5

Generate Interrupt - This instruction sets INTERRUPT

L!R

Octal Code

16 2

Description

Load Input Register — This Instruction loads the infor-

REQUEST FLAG in the PDP-14, clears EXT FLAG, and
transfers BACOO-1 1 to MB Register upon completion of

The principle use for this transfer path is for placing an

present PDP-14 instruction.

address in PCI or PC2.

mation from BACOO-1 1 into the Input Register.

PCI is not incremented.
EXT FLAG is set upon completion and control returns to
the ROM.

ROR

17 6

NOTE
A GNI can be used with the PDP-14 external

Read Output Register - This instruction gates the conIt also clears
tents of the Output Register to AGOG— 1 1
.

the output flag.

mode to provide a memory readout capability
for diagnostic purposes. That is, if the GNI
provides a TRM, the content of the ROM loca-

SEF

Skip On EXT FLAG - This instruction samples the EXT

FLAG. If set, a SKIP pulse is returned to the computer.
As a result, the computer skips the next instruction.

tion specified by PCI is transferred to the Out-

put Register for examination by the computer.

LDE

16 4

Load and Execute — This instruction loads MB Register

from^ACOO-tVand clears the EXT fH.7fliG.

SOF

Following

OUTPUT FLAG. If set, a SKIP pulse is returned to the

this action, the controller transfers the instruction to the

computer to cause it to skip the next instruction.

IR, increments PCI, then executes the instruction.

Skip On OUTPUT F LAG — This instruction samples the

After

execution, the EXT FLAG is set to denote the controller
is

CEF

16 7

ready for another action.

STF

17 3

Skip On TEST FLAG — This instruction samples the

TEST flip-flop.

Clear EXT FLAG. Used for External operation.

If set, a

SKIP pulse is returned to the com-

puter to cause it to skip the next instruction.

CLF

17 2

Clear OUTPUT FLAG - The controller sets this flag when

data is entered into the Output Register. This instruction
also returns an

AC CLEAR to the computer. Thus, this

SCR

17 5

Skip on Controller Running — This instruction samples the

RUN flip-flop. If set, a SKIP pulse is returned to the com-

Output Register transfers to the computer.

puter to cause it to skip the next instruction.

Figure 3-10

3-8

instruction can be used as a preparatory instruction for

lOT Instructions

External Mode Instructions

3.3.4

Following this action, the Control Unit can continue operation by obtaining another instruction (either from the

In addition to the internal mode operating instructions, the controller can also perform six external mode instruc-

ROM or the external computer) or can halt operation if a halt instruction is decoded.

tions.

These instructions are used for mode control and related operations. The format for external instructions

The timing states for the FETCH and EXECUTE cycles are denoted at the left edge of drawing D-FD-PDP- 14-0-6.

is the

same as that for internal mode Housekeeping instructions (Figure 3-9). Table 3-2 describes the function of

Note that the FETCH cycle is invariable and that it consists of an interval for START cycle, PAUSE, time states

each external mode instruction.

and 2 (TSl and TS2), and END CYCLE. Note also that only part of the EXECUTE cycle uses PAUSE (specif-

ically 2- word instruction such as

JMP or TRM).

Table 3-2
3.4.2

External Mode Instructions

Symbolic

Code

When the PDP-14 is operated in the internal mode, instructions are fetched from the ROM. The flow diagram

Octal
Description

Code

(D-FD-PDP- 14-0-6) FETCH cycle shows the major events for this function.
a

EEM

0600

START CYCLE pulse initiates

memory timing. A short interval is required for the access as denoted in the flow diagram. Upon completion of

A generate interrupt (GNI) instruction loads the EEM instruction into the MB Register from the computer's

ROM transfers the instruction to the MB Register (this
gating or load strobe) and generates a MEM DONE pulse.

accumulator during the FETCH cycle. During the EXECUTE cycle, the EXT

MODE flip-flop is set. Next, the EXT FLAG is set to notify the computer
0645

First, a

MEM GO pulse. This pulse clears the MB Register (to prepare it for receiving the ROM instruction) and starts

Enter External Mode - This instruction sets the EXT MODE flip-flop so that
the controller operates with the computer.

EES

FETCH Cycle for Internal Mode

the access, the

is a direct-set operation

and requires no

The MEM DONE pulse advances the timing to TSl from the PAUSE state. The end of TSl causes the transfer of

that the PDP-14 is ready for another instruction.

the instruction in the

Enter External Mode and Subroutine — This instruction performs the same

PCI is incremented. Next, the Control Unit generates an END CYCLE pulse which sets up the EXECUTE cycle.

MB to the IR. The Control Unit then advances to TS2 and at the end of this time state

functions as the EEM instruction and it prepares the controller for a sub-

routine jump; i.e., the contents of PCI (next

ROM address) is stored in PC2

3.4.3

FETCH Cycle for Interrupt Mode

for return from the subroutine.

LEM

0400

Leave External Mode — This instruction returns the controller to the internal
operating mode by resetting the EXT
the

LER

0454

MODE flip-flop. The controller resumes

ROM program at the address specified by PCI

Leave External Mode and Return From Subroutine — This instruction resets
the EXT

MODE flip-flop and transfers the contents of PC2 to PCI so that the

ROM program can resume at the place it was interrupted.
TRM

TRS

For interrupt mode operation, the computer provides a GNI lOT instruction. This instruction sets the

INTERRUPT flip-flop, and when synchronization is achieved (next END CYCLE pulse), the Control Unit begins
a FETCH cycle for interrupt operation. With the START CYCLE pulse, the MB Register is cleared and the
contents of the computer's accumulator are transferred to the MB Register. Following this action, the Control

Unit generates an EXT DONE.

From this point on, the interrupt mode differs from the internal mode only in

that PCI is not incremented. Thus, after execution of the current instruction, the program returns to the point

where it was interrupted, unless the GNI instruction was used to provide an EEM or EES instruction.

4226

Transfer Memory to Output Register — This instruction transfers the contents

NNNN

of the next memory location to the Output Register (via the MB Register) for

When several GNI instructions are provided by the computer in rapid succession, the PDP-14 will process at least

transfer to the computer.

one ROM instruction between every GNI, unless one of the GNI instructions forces the PDP-14 into the external

4225

Transfer Register and Store — This instruction transfers the contents of the

mode.

NNNN

next ROM address to PC2 via the MB Register. Since PC2 stores the program
return address for subroutines, this instruction can be used to change the

3.4.4

FETCH Cycle for External Mode Operation

return address during the subroutine.

The FETCH cycle for external mode operation begins with the clearing of the MB Register. Concurrently, the
Control Unit sets the EXT FLAG to signify to the computer that it is ready for another operation.

When the

computer senses this condition, it places an instruction in its accumulator and issues an LDE (6164g) lOT
3.4

INSTRUCTION FLOW

this point, an

3.4.1

EXT FLAG and loads the accumulator word in the MB Register. From
EXT DONE pulse is generated and the remaining part of the FETCH cycle is the same as for internal

instruction. This instruction clears the

General

mode operation.

Drawing D-FD-PDP- 14-0-6 (Appendix B) depicts the flow of all instructions. For external mode operation, the
machine follows the path labeled EXT MODE (1). Similarly, for a single instruction interrupt, the machine
follows the path labeled INTERRUPT (1). For internal or

ROM operation, the machine follows the third or

unlabeled path; unlabeled lines can also be common to other modes.

3.4.5

EXECUTE Cycle

The major events for instruction execution are also shown on D-FD-PDP-1 4-0-6. The events are generally selfexplanatory; however, a couple of explanations are necessary. Note that 2-word instructions (JMP + JMS)

ROM or external computer). Also observe that I/O instructions do

The flow diagram consists of two major cycles; FETCH and EXECUTE. During the FETCH cycle, the Control

require another memory access (either from

Unit retrieves an instruction from memory (ROM operation) or accepts an instruction from the computer (EXT

not require the discrete time states (PAUSE, TSl and TS2). Note also that controller operation is halted at the

MODE or INTERRUPT). During the EXECUTE cycle, the Control Unit decodes and executes the instruction.

end of an EXECUTE cycle if the RUN flip-flop is reset; otherwise, a FETCH cycle is started.

3-9

LOGIC AND aRCUIT DESCRIPTION

3.5

held in the initialize state by holding the START switch depressed.)
initialized output is discontinued, and CI 4 begins charging again.

3.5.1

General

When the START switch is released, the

Approximately 200 milliseconds later, the

threshold of Q7 and Q8 is exceeded and E2 generates a START EXT L pulse to set the RUN flip-flop and to

The major logic functions and circuits are described in subsequent paragraphs.

The description, in general,

start processor timing.

references drawings in Appendix B, however, simplified diagrams are provided where necessary. For a definition

of signals, refer to the signal glossary in Appendix A.

3.5.2

Initialization

POWER
SHUTDOWN'

The PDP-1 4 is initialized:

1) during a power-up sequence; 2)

when the START/STOP switch is depressed to
+ 5V

START while the RUN flip-flop is cleared; 3) when a timing error is detected for internal mode operation; and

DC POWER

4) when power is removed (power shutdown or power failure). In general terms, the initialize operation resets
all control flip-flops and clears the

MB, PCI PC2, and the IR.
,

In addition, an I/O

CLEAR pulse generated from

the INITIALIZE output, clears all output, storage, and accessory flip-flops except the retentive memories.

SHUTDOWN

The

INITIALIZE signal sets the FETCH flip-flop and, since PCI is cleared, the processor begins a FETCH cycle at

INITIALIZE

CLR PC
CLR MB

memory location 0.
Drawing D-BS-PDP- 14-0-3 shows the functional relationships of the power control logic and drawing

Run iij Bi Ay
CONTROLS ENABLE /t_

C-CS-M742-0-1 depicts the circuits that generate the INITIALIZE outputs. Transistor Ql and associated RC
networks (drawing C-CS-M742-0-1) function as a power-up sensor and delay circuit; its output is ORed with the
output of the power shutdown circuits. Transistors Q3 and Q4 form an emitter-coupled differential pair that
senses a power shutdown. Transistors Q5 and Q6 function as inverter drivers for the power shutdown circuit.

Transistors Q7 and Q8 form a Schmitt trigger for switch filtering with a driver stage (Q9). These stages are used
for manual control functions (START and CONTINUE) and power-up functions.

SWITCH ON
START EXT L

During power up, the +5V potential reaches a usable value in approximately 16 milliseconds (corresponding to
approximately one ac input cycle) after power is switched on. During this interval, and for approximately 50 to

END CYCLE

90 milliseconds after, Ql is forward-biased by the charging of C9. As a result, the SHUTDOWN L signal resets
the

RUN ffip-flop, and causes INITIALIZE L, INITIALIZE H, CLR PCI H, and CLR MB H outputs as shown in

START
CYCLE DELAY

Figure 3-11.

aTAST_CY.CLE

voltage at Node

A exceeds the threshold of Schmitt trigger Q7 and Q8. With Q7 and Q8 on, Q9 switches on and

START EXT pulse generator E2. This stage, in turn, sets the RUN flip-flop and clears the STOP flip-flop
with a 200-nanoseconds ground-asserted pulse. The START EXT L output also starts Control Unit timing by
triggering a start delay stage in the M741 module. With this action, the Control Unit begins a FETCH cycle at
triggers

memory location

MB PULSE
NOT RECEIVED
WITHIN

CLR

(PCI = 0000).

130-140(13

During power shutdown (or a power failure), the machine system is shut down in a predictable manner by returning the PDP-1 4 to an initialized state.

For detection of power shutdown or a power drop, the base of Q3 is
Figure 3- 1 1

referenced to +2.8V while the base of Q4 is referenced to approximately +2.5V. With this arrangement, Q4 is

conducting while Q3 is off during normal operation.

Power Control Timing

When the +5V source drops to approximately +4.6V,

however, Q3 conducts hard and Q4 is cutoff. (The bias for this action is maintained by C 1 1 so that the process
continues until the +5V drops to an unusable value, nominally in about 200 nanoseconds.) With Q4 off, Q5
switches off and Q6 switches on. With Q6 on, the system is initialized and the

RUN flip-flop is reset (Figure 3-11).

The machine system is also initialized when the START/STOP switch is depressed to START (provided the RUN
flip-flop is cleared).

For this function, the START switch provides a ground level during switch closure. As a

result of this level, diode D3 completes a discharge path for CI 4.

With CI 4 discharged below the threshold of

Schmitt trigger Q7 and Q8, Q9 switches off. With Q9 off, E9 generates an initialize output. (The system can be

3-10

Detection of a timing malfunction for internal (ROM) mode operation also initializes the system.

An integrating

monostable multivibrator (designated E3 on circuit schematic) detects a timing malfunction. This stage is quaU-

RUN input denoting the RUN flip-flop is set. A CLR MB L triggers stage E3 following the setting of
RUN flip-flop. As a result, E3 generates a ground-level output. If the stage does not receive another
CLR MB pulse within 130 to 140 microseconds, reverts to its stable state (+5V at pin 6). As a result, the
fied by a

the

system is held in the initialized state until the timing malfunction is cleared and the system is restarted.

Manual Controls

3.5.3

The PDP-1 4 uses three manual controls: an ON/OFF switch; a spring-loaded, center-off START/STOP switch;
and a spring-loaded CONTINUE switch. The ON/OFF switch controls primary power to the power supply as

TIME

shown in drawing C-CS-70063 14-0-1. When this switch is placed to the ON position, the PDP-1 4 automatically
begins its control sequence as described in the previous paragraphs.
a

INTERNAL

TWO-WORD

INPUT /OUTPUT

JFF JFN SKE SKZ TRR
NOP JMR SKP
WITH INTERNAL MEMORY

JMP JMS TRM

TXN TXF TYN TYF
TXD TYD SYN SYF
WITH INTERNAL MEMORY

The PDP-1 4 control sequence continues until

WITH INTERNAL MEMORY

(MICROSECONDS)-

FETCH (DM

HALT instruction is executed, the START/STOP switch is depressed to STOP, a timing malfunction is detected,

20.8

L^-T

(A23J1)

or power is removed.
EXECUTE 1)H
j

(A23E1
SE11

Drawing D-BS-PDP-1 4-0-3 shows the functional relationships of the START/STOP and CONTINUE switches with
the M742 module.

The STOP position of the START/STOP switch momentarily grounds an input to the M742

PAUSE (1) H
(B23T2)

module. This input directly resets the STOP flip-flop. With the STOP flip-flop reset, the RUN flip-flop is reset
at the end of the current instruction cycle.

TS1 (1) H

(B23M2)

With the RUN flip-flop reset, the M742 provides a ground-asserted CONTROL ENABLE level to the START
position of the START/STOP switch and to the CONTINUE switch. Thus, when either switch is closed, a ground-

TS2 (1) H
(B23L2)

asserted pulse is returned to the M742 module. This input discharges CI 4 in the RC delay network of Schmitt

nj.

trigger Q7 and Q8 (drawing C-CS-M742-0-1).

START CYCLE H 1150,^
(A23T2) l"STi

With CI 4 discharged below the turn off of Q7 and Q8, Q9 provides a positive-asserted output. This output is
gated with START H to initiaUze the system during the interval the START switch is closed.

As long as the

MEM. GO H
I

(A23N1)

START/STOP switch is held in the START position, the system is held in an initialized state.
When the START switch is released, CI 4 must again charge to the turn-on threshold of Q7. This action provides

MEM. DONE L

transition to ground.

As a result, pulse generator E2 starts the controller timing and sets the RUN flip-flop.

lRI^

Major States and Timing

3.5.4

T PULSE H

00 ns

uyjj

(B23H1)
I
I

400ns-

General — The logic circuits that comprise this functional area are shown in block schematic form on

3.5.4.1

D-CS-M741-0-1

irii

ill

iMJ^

Figure 3-1 2 shows the pertinent timing relationships for the logic.

FETCH Cycle - During initialization, the FETCH/EXECUTE flip-flop is set to the FETCH state. At the
end of an initialize function, the power control provides a START EXT pulse. This pulse triggers a delay and

r
L

-I

NOTE; MAINFRAME TEST POINT
COORDINATES INDICATED
IN PARENTHESES

D-BS-PDP-1 4-0-3, Sheet 1. These logic circuits are contained on an M741 module and are detailed on

END CYCLE L
a
START EXTERNAL
(A23F1)0R(B23K2)

M
J.

—
—
n

(A23E2)

a 200-millisecond delay interval to eliminate switch bounce. After 200 milliseconds, Q9 provides an output

I/O CYCLE (1)H,

(B23U2)

p-18.5,=

I/O STROBE L j_
(B23R1)

-|^
I

3.5.4.2

Figure 3-12 Control Logic Timing

pulser stage. Since these circuits are somewhat unique and are also used in other control areas, the circuit is

described in detail in subsequent paragraphs before continuing with the FETCH cycle.

Figure 3-13 depicts the circuit schematic, logic equivalent, and timing relationships for a delay stage and a pulser
stage.

The circuit shown is used for start delay timing and START pulse generation; however, it is representative

The positive transition of the START EXT L initiates the delay action. This transition causes El 6 to switch Q9
off.

With Q9 off, CI 7 begins charging toward +5V. After an interval of 150 nanoseconds, the voltage across CI

of other delay and pulser circuits in the Control Unit.

exceeds the turn-on threshold («2V) of El 7.

A start delay of approximately 150 nanoseconds is estabUshed by RC network C17— R31 and the turn-on

The turn-on of El 7 places Node C at approximately +0.7 V and CI 2 couples the-5V charge to the base of Q6.

threshold of El 7. At end of the delay, this circuit triggers the pulser circuit to generate a 200-nanosecond

Since the base of Q6 is driven negative, Q6 switches off and remains off until CI 2 discharges through R23.

START pulse (Figure 3-13).

interval required for this action is approximately 200 nanoseconds; thus, Q6 generates a 200-nanoseconds positive

pulse. This

In a quiescent state, C17 is charged to +5V, the charge across CI 2 is equalized at approximately +0.7

pulser output (Node E) is a logical 0.

V and the

With the negative transition of the START EXT L pulse, transistor Q9

The

START CYCLE pulse begins the major state timing.

The trailing edge of the START cycle pulse sets the PAUSE flip-flop as shown in Figure 3-12. Setting the PAUSE

switches on and CI 7 discharges to approximately OV. With both inputs to El 7 a logical 0, El 7 switches off and

flip-flop triggers a 1 00-nanoseconds pulser circuit.

CI 2 rapidly charges to the difference between the base voltage of Q6 and +5V.

This circuit and associated gating generate a CLR MB L and

MEM GO H pulse.

3-11

DELAY

The trailing edge of the resulting pulse (T PULSE) resets the TSl flip-flop and sets the TS2 flip-flop. During TS2,

PULSER
A

No further action occurs during TS2. The interval for TS2 is also 500 nanoseconds (this
At the end of TS2, a T PULSE is ANDed with TS2 to
generate an END CYCLE L pulse. This pulse resets the FETCH/EXECUTE flip-flop to begin an EXECUTE
PCI is incremented.

+ 5V

+5V

+ 5V

+5V

R3I
1.5K

470

•^ I
09

START EXT L

cycle.

lOOpf

E17

cution cycle. The decoding of an instruction op code begins when the instruction is transferred to the IR. This

information is not acted upon, however, until at least the beginning of the EXECUTE cycle. The operations and

J^C17

EXECUTE Cycle - The END CYCLE L pulse also triggers the START CYCLE timing to begin the exe-

3.5.4.3

RUN (D-

C1Z

7402

END CYCLE L

sR23

interval is estabUshed by the same pulser circuits as TSl).

timing for the EXECUTE cycle are instruction dependent. These relationships can perhaps best be understood
using the instruction flow diagram (D-FD-PDP-1 4-0-6) and major state timing (Figure 3-12).

330pf

If the instruction is a NOP, JFN, IFF, SKE, SKZ, or a TRR instruction, the TSl flip-flop is set by the START
CYCLE H pulse. If the instruction is a JFN, JFF, SKE, or SKZ instruction, the related decision is executed

during TSl and the result is received either in the JF-OK flip-flop (for JFN or JFF) or the SKIP OK (for SKE or

CIRCUIT SCHEMATIC

SKZ). For register-to-register transfer (TRR) instructions, the transfer is implemented during TS 1
instruction no action is performed during TS 1

For a NOP

At the end of TSl the timing advances to TS2. During this state,
,

PCI is updated for the Decision instructions (JFN, JFF, SKE, and SKZ). At the end of TS2, the END CYCLE L
END CYCLE L

7400
START EXT H

J-

pulse initiates another FETCH cycle by complementing the FETCH flip-flop and initiating a start cycle delay.

7402^ _r PULSER^

ISOnsjO-

RUN (1)-

LOGIC EQUIVALENT

START EXT L

If the decoded instruction is a 2-word instruction (JMP, JMS, or TRM), then the START CYCLE H pulse sets the
PAUSE flip-flop. This action results in another ROM access. During TSl the control transfers the second word
of the JMP or TRM to the register designated by the JMP, JMS, or TRM instruction. Then, the control advances
to TS2. During TS2, the PCI is updated if required. For a JMS instruction, PCI receives the contents of the
MB Register. For a JMP instruction, the JMP address (entered into PCI during TSl) is incremented. Following
TS2, the control again generates an END CYCLE L pulse to begin another FETCH cycle or halt.
,

If the decoded instruction is an I/O instruction (TXF, TXN, TYF, TYN, SYF, SYN, TXD, or TYD), the START
CYCLE H pulse sets the I/O CYCLE flip-flop at the beginning of the EXECUTE cycle. This action starts a 2-

microsecond (approximate) delay to allow for selection of the input or output circuit. At the end of this delay
interval, the control generates a 6.5-microsecond (approximate) strobe. This strobe clocks the SET and

RESET

functions for SYN and SYF instructions. At the end of this pulse, the T PULSE circuit is triggered to produce

another END PULSE. This pulse strobes the sample return hne for Test instructions and also loads the Output
Register for Test and Display instructions.

3.5.5

TIMING RELATIONSHIPS

Major Registers

3.5.5.1

General — Drawing D-BS-PDP- 14-0-4 shows the major registers comprising the basic Control Unit.

Drawing D-BS-DA14-L-3 shows the major registers added for a computer interface. Each register is updated by
a jam-transfer that occurs on the trailing edge of the load pulse.

Figure 3-13 Delay and Pulser Operation
3.5.5.2

Program Counter 1 (PCI) — This 12-bit register stores the address of the next ROM instruction. This

The MEM GO H pulse starts a ROM cycle (refer to Paragraph 3.5.6.3 for details of memory timing). Upon completion of this cycle (approximately 450 to 550 nanoseconds later), the ROM returns a MEM DONE L pulse
(Figure 3-12).

The leading edge of this pulse initiates TSl during which the instruction is transferred to the IR.

The traihng edge of MEM DONE resets the PAUSE flip-flop. Time state 1 has a duration of approximately
500 nanoseconds.

Two pulser circuits determine this interval. These pulser circuits are connected in tandem

with the 400-nanosecond pulser first. The trailing edge of its output pulse triggers the 1 00-nanosecond pulser.

BUS 00—1

source register or a direct input. This register

contains a summation and carry structure at its input that enables it to be incremented (or decremented) by 1

To increment a count, the contents of PCI are gated to
4-1
0-3
1 by SOR-PCl
and SOR-PCl
1 gating levels from the instruction decoder.
The instruction

(At present, the decrementing capabiUty is not used.)

BUS 00-1

decoder also provides an INCREMENT input which enables the summation structure. The decoder also provides
an LD PCI strobe. This strobe, derived from a 1 00-nanosecond T PULSE, loads and increments PCI. The content of PCI directly drives the
register.

3-12

It can also be loaded from a

ROM selection circuits and can be gated to BUS 00—1

for transfer to another

3.5.5.3

Program Counter 2 (PC2) — This 12-bit register stores the program return address from subroutines.

If all banks are removed, a timing loop in the major states and timing module is completed to effectively bypass

Program Counter 2 receives this address from PCI when a jump-to-subroutine instruction is executed. This transfer is implemented via BUS 00—1 1

ROM timing. With this arrangement, the Control Unit continuously executes NOP instructions.

When the subroutine is completed, PC2 provides this address to PCI so that

the program can resume at the correct address. Again the transfer is implemented via BUS 00—1 1

Unlike PCI

Figure 3-14 depicts the functional circuits for a

ROM bank and is used for the ensuing discussion.

this program counter cannot be incremented (or decremented).

Address Selection - A ROM address is specified by PCI The two MSBs (PCI 00 and PCI 01) select
ROM bank. These bits are decoded by a structure in the M742 power control module as shown in
Figure 3-14. This decoder then selects the applicable bank with one of four discrete ENABLE MEM signals. An
ENABLE MEM signal, when asserted, gates MEM GO to the respective bank timing chain.
3.5.6.2

Memory Buffer — This 12-bit register accepts instructions from the ROM, the computer Memory Port,
or from the PDP-14 transfer bus (BUS 00-1 1). Instructions from the ROM or the computer Memory Port are
3.5.5.4

provided to the direct-set inputs (MBS 00—1 1) of the MB Register and therefore require no load strobe. However,

the

the register must be cleared before loading it via the direct-set inputs. Data can also be loaded from a BUS 00—1

source register. For this jam-transfer, the control provides a 100-nanosecond LD MB pulse.

MB Register can also be transferred to BUS 00-1
3.5.5.5

The contents of the

decoder structure decodes PCI 02 through 05 to select one of sixteen matrix transistor rows.

by SOR-MB (0-3) and SOR-MB (4-11) pulses.

circuit decodes PCI

ROM (or a computer) are transferred to the IR from the MB Register via BUS 00—1

1 .

LOAD IR strobe (in conjunction with an SOR-MB gating pulse) performs this transfer. The IR content is made
directly available to the instruction decoder until updated by the next jam-transfer.

The content of IR can be

gated to BUS 00- 1 1 by a SOR— IR gating pulse from the source register decoder in the M740 module.

Input Register — This 12-bit register is only used for computer interface functions.

to load PCI or PC2 from BUS 00—1 1
pulse.

06 through 08 to select one of eight current switch columns. This latter action is not per-

Each of the 1 28 braid wires is routed through or around 96 Ferrite-core transformers to form eight binary instructions.

If the wire passes through a transformer, a logical 1

vsdre is pulsed by the address selection circuits.

for the bit.

for the corresponding bit when the braid
is generated

09 through 1 1 select one of eight groups of 1 2 sense amplifiers (Figure 3-14).

Its principal use is

For this input transfer, the computer interface provides an LD INPUT

This pulse is derived from BIOP timing as a result of an lOT instruction. For an output transfer, the

instruction decoder provides a SOR— INPUT gating pulse that places the contents of the Input Register on

3.5.6.3

Timing Circuits — For selection and pulsing of a braid wire, the gated MEM GO pulse triggers the read

pulse generator (Figure 3-15). This stage, in turn, produces a 350-nanosecond pulse that enables the current

switch decoder to complete the selection matrix by selecting one of eight lines. As an end result, one of 128

BUS 00-11.
braid wires is pulsed.
3.5.5.7

is generated

If the wire passes around the transformer, a logical

Only one of the eight binary instructions formed by the braid routing is selected at a time. For this

selection, PCI

3.5.5.6

A second decoder

formed, however, until the respective decoder is pulsed.

Instruction Register (IR) — This 12-bit register stores the instructions for decoding and execution.

Instructions from the

The next seven MSBs of PCI (PCI 02 through PCI 08) select one of 128 braid wires. For this function, a 4-bit

Output Register — This 1 2-bit register is used only for computer interface functions.

The gated MEM GO also triggers a 1 50-nanosecond strobe delay pulser in the timing chain.

The delay interval provided by this stage permits switching transients to settle before strobing the output. The
It is loaded from a

BUS 00-1 1 source register (principally the IR or MB Register) by an LD OUTPUT strobe. The Output Register

trailing edge of the delay pulse triggers a strobe pulse generator.

The 1 50-nanosecond pulse generated by the

stage pulses the outputs of a word decoder to select 12 of 96 sense amplifiers. (This action is described in detail

does not utilize its integral output gating structure. Instead, a gating structure on the computer interface module
in Paragraph 3.5.6.4.)

(M745) transfers the Output Register contents to the computer's bus. The computer interface module also

The trailing edge of the 1 50-nanosecond strobe pulse also triggers a MEM DONE pulser. This stage, in turn, pro-

provides the transfer strobe for this function.

duces a 1 50-nanosecond pulse which informs the Control Unit that the memory cycle is complete and an instruc3.5.5.8

Memory Port Buffer - The Memory Port contains a 12-bit register that buffers inputs from the

tion is available.

BAC 00—1 1 lines and provides outputs that direct-set the MB Register. The principal use of this register is to
supply computer instructions via the MB Register path. The computer interface module (M745) generates the
strobe for loading this register. This strobe is derived from the computer bus timing.

The computer interface also

generates the output gating strobe for this register.

3.5.6
3.5.6.1

there are 96 Ferrite-core transformers associated with the braid. These transformers (and their related sense

instruction is selected at a time.

However, only one

PCI 09 through 1 1 select the instruction by strobing only one of the eight

groups of sense amplifiers.

General - A ROM bank consists of three primary divisions:

1) a

G924 ROM Selection and Timing

module; 2) a G922 ROM Braid module; and 3) a G923 Sense Amplifier module. The general relationships of
these divisions are described in Paragraph 2.2.2.1

;

D-BS-MR- 14-0-2 shows the module interconnections. Module

circuit details are shown in D-CS-G924-0-1, C-CS-G922-0-1, and D-CS-G923-0-1, respectively.

As mentioned previously, the ROM consists of up to four 1024-word banks for a total storage capacity of 4096
12-bit instructions. Also, each bank is an operating entity.

the

Data Sense Circuits — Figure 3-14 illustrates the general arrangement of the sense circuits. As indicated,

amplifiers) are arranged to provide eight 12-bit instructions for each braid wire pulsed.

ROM Circuits

module slots for bank 1 (Figure 2-1).

3.5.6.4

For a IK ROM, this bank must be installed in the

If other banks are used, they must be inserted in consecutive bank slots or

Figure 3-16 illustrates the method used to obtain one bit of an instruction and provide it to the MB Register.

reiterate, if a braid wire passes through the transformer, a pulse is induced in the sense winding when the braid

wire is pulsed. If the braid wire is routed around the transformer, no pulse is generated when the braid is pulsed.

The sense amplifier for the stage is strobed after switching transients have settled.
passes through the transformer, the sense amplifier output is ground-asserted.
bit is set and, in turn, direct-sets a corresponding stage of the

If the drive wire for the bit

As a result, the latch circuit for the

MB Register. The latch is cleared when the PAUSE

input returns to ground. This action readies it for another cycle.

ROM will not respond correctly and the PDP-14 timing will stop.

3-13

NOTES:
(1)

RQM TRANSFORMER SENSE WINDINGS ON G923 BOARD.

(2)

DRIVE WIRES (PROGRAM) ON G9Z2 BOARD.
SAME AS READ PULSE GENERATOR ONESHOT.

FgG923 (SENSE WINDINGS) (NOTE 1)

G924 DRIVE WIRE SELECT MATRIX

ffifWt
fmfffl

8 OTHER-

TRAN-

T—

MATRIX

SISTORS IN
THIS ROW

_L-r\TRAN-

*—f f

/-r-?l

\~L y SISTOR

^-^ (10F128)

PCI
BITS 2-5

MATRIX
BASE
SELECT

WIRES

ffifflfi
I

TO 15

OTHER
TRAN-

DECODER

^fffiffl

SISTORS
IN THIS

COLUMN

ffiffffl

ffiTO^

L
CURRENT
SWITCH
(1

READ PULSE
GENERATOR
1+6

I
I

T
+ 5|

+ 5|

OF 8)

ffiffffl

S WIRES

ENABLE

CURRENT
SWITCH
DECODER

wffm

128 DRIVE WIRES
(1

ONE SHOT (OS)

PER MATRIX
TRANSISTOR)

S922 (DRIVE WIRES) (NOTE 1)

±1
150ns

STROBE GEN OS

BITS 6-8

(NOTE 2)

PCI BITS 9-11

(FROM PAUSE
CONTROL)

PCI
BITS
00.01

ENABLE
r MODULE
r

ROM
MODULE
DECODE
iABZ2 (M742)

MPc
_ LIN"
"°™
^ r
1

r '°

J MODULEES

>MEM DONE
150ns

STROBE DELAY GEN
(NOTE

K:^

MEMORY DONE OS
(NOTE

2,3,AND 4

Figure 3-14

3-14

tSOns

ROM Functional Diagram

(L)

(TO TIME STA'
STATE

CONTROL)

AT2

M741

START CYCLE H

BT2

M741

PAUSE CYCLE H

ROM
MODULE

WAVEFORM

MODULE SIGNAL

STROBE
MORE WORD
XXXN SENSE AMPLS

M741

AN1

FROM 7 MORE
INTERNAL

G9Z4

INTERNAL

G923

READ PULSE

INTERNAL
DATA BUS

6924

BK1

WIRED-OR
FUNCTION

G924

M746

=r>J

STROBE DELAY

WORD XXXN

STROBE PULSE

MEM DONE L

ROM—"MB

PAUSE (H)
BM2

ROM DATA BUS
(LOGICAL 1 = 0V)
..

DATA BITn OF
12-BIT BUFFER

ROM DATA

BUS BITn(L)

(BUFFER REGISTER

ENABLE (H))

M741

A DRIVE WIRE BRAID CONSISTS
OF 128 DRIVE WIRES, EACH
WIRE IS THREADED THROUGH
OR AROUND 96 SENSE
TRANSFORMERS AS REQUIRED
FOR EACH BIT. DRIVE WIRE

note:
Test points accessible from wiring side of mainframe ore
stiown for ROM rto. 1, ottier waveforms must be observed on

G923 module of ROM assembly.

Figure 3-15

3.5.7

BITn
A

WORD XXXN
STROBE (H)

(DIRECT SET)

(1 of !2)

(DIRECT SET INPUT)

BITn SENSE AMPL
BL1

MB REGISTER

BITn (L)

XFMR OUTPUT

TWO-PART FERRITE
SENSE TRANSFORMER
G924

ENABLE TO REST OF
BUFFER REGISTER
4

BITn SENSE
AMPLIFIERS

FERRITE

INTERNAL

MAIN
FRAME

ROM Timing Relationships

J^
FROM UP TO 3 ADDITIONAL ROM MODULES (BITn)

THREADED THROUGH TRANSFORMER
TRANSFORMER

FOR "1" BIT, AROUND
FOR "0" BIT.

Instruction Decoding and Register Control

The M740 module decodes the instructions and generates the discrete control signals for executing the instructions.

The decoding operation is performed in four basic parts and involves four decoder circuits as shown in

Figure 3-16

ROM Data Sense Circuits, Simplified Logic Diagram

D-BS-PDP-1 4-0-3 (Sheet 1). Drawing D-CS-M7 40-0-1 shows the logic circuits for the functional areas.

The op code (IR 00-03) is decoded by a block labeled INSTRUCTION DECODER. This operation begins when
the instruction is transferred to the IR (at TSl of the FETCH cycle). Thus, discrete control signals defining the
instruction overlap the FETCH and EXECUTE cycles.

(increment or decrement). Figure 3-9 lists the codes and functions associated with these bits.

A 500-nanosecond

EXECUTE cycle, strobes this decoder to synchronize the appUcable operation with

the transfer.

The source register decoder decodes IR 06 through IR 08 of instructions involving transfers (TRR, EEM, LEM,
JMP, JMS, SKE, and SKZ instructions) to generate source gating strobes.

00-nanosecond T PULSE input clocks the load pulse operation. Since the decoder output is only active

during TSl of an EXECUTE cycle, a single load pulse is generated at the end of TSl (corresponding to the end

of the source gating strobe).

An operate decoder deciphers IR 04 and 05 to define minor arithmetic operations associated with transfers
pulse, occurring at TSl of the

Source and destination strobes are also generated for conditions within the Control Unit. For example,

SOR-MB (0-3) and SOR-MB (4-11) output gating strobes and an LD-IR must be provided during TSl of a
FETCH cycle to update the IR. Similarly, to increment PCI at TSl of a FETCH cycle, SOR-PCl 0-3 and
LD— PCI load strobe must be generated. To prevent the incrementing of PCI during an interrupt operation,
INT SYNC qualifies the generation of the LD-PCl strobe.

A 500-nanosecond pulse, derived from

TS 1 and EXECUTE conditions, clocks this operation. Figure 3-9 defines the source codes for the registers.

3.5.8

The destination register decoder, as the name implies, decodes IR 09 through IR 1 1 to generate pertinent load

3.5.8.1

pulses for the registers.

Timing for this decoder is provided by TSl and EXECUTE conditions; thus, the decoder

output is active for only 500 nanoseconds.

I/O Interface Circuits
General — As mentioned previously, the I/O interface circuits select the I/O package and address the

circuits within the package.

For a Test instruction, these circuits also compare the state of the input or output

with the state specified by the Test instruction and provide the comparison result to the TEST flip-flop. For

3-15

Operate instructions, these interface circuits select the output circuit and define the function to be performed

the function lines. There are two lines (E SET

and 1) for a SET function, two for RESET (E RSET

and 1),

and one for a CLEAR. This arrangement is required because the addressing scheme addresses two circuits con-

(SET, RESET, or CLEAR).

Bit 03 of the IR determines whether a set or reset function is implemented. (If IR 03 is a logical 1

currently.

The general relationships of the I/O interface circuits are shown in D-BS-PDP- 14-0-5. This drawing also defines
the input and output addresses associated with a PACKAGE SELECT (PS) line and the output function lines.

SET function is performed; if not, a RESET function is performed.) Similarly, IR 07 selects the group line. If
IR 07 is a logical 1 the upper group is selected (either E SET or E RSET 1). If not, E SET or E RSET is
1

Drawing D-CS-M743-0-1 shows the logic and circuit details for the I/O interface.

selected.

3.5.8.2

Input Tests — Figure 3-17 illustrates the circuits used for testing inputs. For discussion purposes, a

specific input address is used.

3.5.9

However, circuit operation is the same for all other input addresses.

For an example of circuit operation, assume the IR contains a TXN instruction for input address 7 (octal 2407).
With this instruction in the IR, the instruction decoder asserts the I/O instruction line (TXF, TXN, TYF, TYN,

Conditional Jump Circuits

Figure 3-1 7 also shows the jump comparator and JF-OK flip-flop. These circuits are used with Decision
(conditional jump) instructions.

SYF, SYN, TXD, or TYD). As a result, the I/O package decoder circuit decodes IR 04 through .06 and asserts

The jump comparator logic is enabled during TSl of the EXECUTE cycle for a JFN or JFF instruction.

PACKAGE SELECT 1. Concurrently, the I/O interface address gating asserts ADDR 1, 2, and 4, and negates

pares the state of the TEST flip-flop with a bit (IR 03) defining the jump conditions and sets the JF-OK flip-flop

ADDR 8.

if a favorable comparison results.

The PACKAGE SELECT 1 output is ANDed with the MSB (and its complement) of the address bits to enable

Note that after the TEST flip-flop is tested, it is reset (if set) regardless of the

test result.

one of two circuit decoders within the I Box. For the example, the K161 decoder for addresses Og — 7g and

There are two comparison conditions which set the JF-OK flip-flop.

20g - 27g is selected since ADDR 8 is a logical 0. This octal decoder, in turn, decodes the ADDR 1

is a logical

lines and positive-asserts output line 7.

2, and 4

As shown in Figure 3-17, output line 7 selects the gating circuits for two

input converters, one for address 7g and one for address 27g

Assume at this point that the inputs for addresses

7 and 27 are on. With this condition, the converters for these addresses provide +5 V (logical 1 ) outputs. Since
the decoder gating strobe is also positive, the output diodes are forward-biased and both sample return lines are

It com-

First, if the

TEST flip-flop is set and IR 03

(denoting a JFN instruction), the JF-OK flip-flop is set. Second, if the TEST flip-flop is reset and

IR 03 is a logical

(as for a JFF instruction), then the JF-OK flip-flop is set. All other comparison conditions

have no effect on the JF-OK flip-flop.

The JF-OK flip-flop is clocked by a 1 00-nanosecond T pulse occurring at the end of TSl in the EXECUTE cycle.
The state of this flip-flop is then used to initiate a transfer during TS2. This transfer establishes the jump

asserted.

address.

The sample return lines are gated with IR 07 (and its complement) to select the pertinent line. This method has
the same net effect as choosing one input out of 32 and using one sample return line. For the example, IR 07 is
a logical

so the state of

X RET

selected. This result is then qualified by control signals denoting that a test

input instruction is active (TXN, TXY, or TXD). Immediately following this gating, the state of the input is

compared with IR 03. This bit defines whether the input is to be tested for an on or off state. For the example,
IR 03 is a logical 1 (denoting an on test) and, since the input is on, results in TEST TRUE H being positiveasserted. This output sets the TEST flip-flop. This action occurs at the end of the

EXECUTE cycle. The TEST

A conditional jump can be implemented only on the same ROM page (256 locations) because bits

through 3 of

a JFF or a JFN must be used to define the instruction, thus leaving only bits 4—11 to define the jump address.

In addition, there are no facihties for updating PCI 0—3 concurrently. Thus, the bank bits (defined by PC 00

and 01) and page bits (defined by PCI 02 and 03) can only specify the same ROM bank aiKi page.

The jump address is established by loading MB 04— 1 1 and PCI 00—03 into PCI. This action is performed
during TS2 of the EXECUTE cycle as illustrated in D-FD-PDP- 14-0-6. For this transfer, the instruction decoder

flip-flop provides one input to the jump comparator where it is used in a Decision (JFF or JFN) instruction.

generates concurrent SOR— PCI 0—3 and SOR— MB (4—11) gating strobes. This action places the address on

This function is described in Paragraph 3.5.9. The TEST flip-flop remains set until reset by a JFF or JFN instruc-

BUS 00—1 1. The address is loaded into PCI by a 1 00-nanosecond LD— PCI pulse occurring at the end of TS2.

tion.

This action occurs at the end of the EXECUTE cycle for these instructions.

TEST TRUE signal is not asserted and the
TEST flip-flop is not set. Similarly, if the input for address 7 was on and was tested for off, the TEST TRUE
signal is not asserted and the TEST flip-flop is not set. If, however, the address 7 input is off and is tested for
off, TEST TRUE is asserted and the TEST flip-flop is set.
If the input for address 7 was off, however, and was tested for on, the

3.5.8.3

Output Tests - Output testing is identical to that for inputs except for the arrangement of the address-

ing circuits.

The same number of addressing combinations are required. However, each I/O PACKAGE SELECT

O Boxes instead of one. With this arrangement, two circuits are selected for each basic address.
These circuits, however, are in different O Boxes. Again, two sample return lines are used and IR 07 selects the
line selects two

As a net result, the next instruction is accessed at the jump address.

The JF-OK flip-flop is also cleared concurrently with the address transfer. The qualifying signal for this action is
TSl returning to a logical

3.5.10
3.5.10.1

state.

Computer Interface
General — The computer interface contains the circuits for operating the PDP-14 with a computer's

I/O bus for programmed data transfers. The circuits involved in this function are housed on an M745 Interface
Control module and an M249 Memory Port Register module for the PDP-8/E. (An Ml 06 Memory Port Register
is used v/ith the

PDP-8/I and PDP-8/L, but will not operate with the PDP-8/E. The M249 will work with the

PDP-8/L, PDP-8/I, or PDP-8/E with the appropriate ECO, 14-0039, installed in the PDP-14.)

correct line.

Drawing D-BS-DA 14-1-2 shows, in block diagram form, the major functional areas for a negative I/O bus interface
3.5.8.4

Output Functions - The same addressing scheme is used for output functions. The I/O interface, how-

ever, must also assert a function line.

3-16

Drawing D-BS-PDP- 14-0-5 shows, in block form, the circuits that control

such as for a PDP-8/I computer. Drawing D-BS-DA 1 4- L-2 shows the equivalent for a positive I/O bus such as for
a PDP-8/L computer.

The interface control module decodes the device code provided by the computer and executes the transfer

PART OF M743

instructions.

PART OF I BOX
CONV

AC OR DC INPUT

[INPUT ADD_R78_

As part of this overall function it:

1) selects the operating mode; 2) selects and synchronizes an

interrupt operation; 3) generates input load strobes for accepting BAC inputs; 4) interfaces PDP-14 flags with the

computer's skip chain and program interrupt request bus; and 5) performs output gating for transfers to the

computer.

The Memory Port Register, in contrast, simply buffers instructions transferred from the computer.
PS1 H
POSITIVE -

-Ul

AC OR DC INPUT-

ASSERTED
FOR ACTIVE
SELECTION

K135

[INPUT ADDR 278 '

i>^

|IR 04 -06(H)

I/O

ENABLE

vry/

|+TXD+TYD(H)

GRD-ASSERTED
FOR ENABLE

TYPICAL FOR
OTHER 3 BITS

other I/O bus peripherals. The controller, however, recognizes two device codes (namely 1 6g and 1 7g ) on

CKT
DECODER
I

^^208-278)

ONE OUTPUT LINE IS

V
POSITIVE-

"ASSERTED

IR09-11 (H)-

K161

l-^

H—

A0DR1 H

1 1

(subdevice code) to perform the lOT operations. With

08-78 AND

ADDRESS
GATING
AND
DRIVERS

BMB 03 through 08. It also decodes BMB 09 through

(ADDRESSES 8 LINES

ADDR
IR08(H)-

Device Selector Logic — The lOT device selector (and subdevice) circuits are similar to those used by

PACKAGE
SELECT
DECODER 7

TXFtTXN
TYF*TYN
K+SYF+SYN

3.5.10.2

I/O PACKAGE

SELECT

instructions to the PDP-14 internal bus under control of the interface control logic.

(ALL OTHER

OUTPUTS
ARE GROUND)

It gates the

this arrangement, up to

14 lOT instructions could be recognized; however, only 10 lOT instructions are imple-

POSITIVE-ASSERTED
FOR SELECTION (ALL
OTHER OUTPUT LINES

mented (Figure 3-10).

ARE GROUND
CONCURRENTLY)

The BMB 03 through 07 inputs are provided in complement pairs. An M92 1 connects the pertinent lines to a
device selector gate in the M745 module. This selector gate recognizes the basic device code of 16g or 1 7g

CKT
DECODER

Its

output is then ANDed with BMB 08 to determine whether the code is 1 6g or 1 7g

(ADDRESSES 8 LINES
108-178

308-378)

Timing for the lOT operation is provided by the BIOPl, 2, and 4 pulses. Like other peripherals, the controller

uses these pulses to estabhsh transfer relationships.

the sampling of flags for the skip bus; BI0P2 timing is used for the clearing of flags and for the generation of an

GROUND-ASSERTED FOR ON INPUT
'

PART OF M743
SAMPLE RETURN
LINE

(XRETO)

NyBUFFER

And like that for other peripherals, BIOPl timing is used for

AC clear; and BI0P4 performs input loading, output gating, and clearing of specific flags.

_FOR OUTPUT SAMPLE
/^RETURN CIRCUITS
I— IN

TEST

COMPARATOR

3.5.10.3

Skip Bus — There are four controller status conditions that can be interrogated by computer lOT

instructions.

These lOT instructions and conditions are:
Condition

Instruction

SCR(6175g)

RUN (1) — This condition denotes the controller is operating; i.e., it is not
in a power-off or stop state (SCR = SKIP ON INITIALIZE).

SEF(6161g)

EXT FLAG (1) — This condition denotes an interrupt transfer operation
has been completed.

STF(6 1 73g

PART OF M741

TEST TRUE H

TEST FLOP ( ) — This condition denotes the I/O condition checked for
1

was true.
JUMP
COMPARATOR

SOF(6 1 7 1 g )

OUTPUT FLAG ( ) — This condition signifies the controller has information
1

in the Output Register for transfer to the computer.

If the condition interrogated is true, the interface control returns a skip pulse to the computer.

establishes the timing for the skip pulse.

A BIOPl pulse

The skip pulse causes the computer to skip the next sequential memory

location.

3.5.10.4

Interrupt Operation - A GNI (6165g) instruction initiates an interrupt operation. During this opera-

ROM access and accepts an instruction from the computer. The controller subsequently executes the computer-suppUed instruction, then resumes operation with the ROM at the next
tion, the controller interrupts

Figure 3-17 Input Test Functional Diagram

sequential address.

3-17

Since a GNI instruction can be issued any time during a FETCH or EXECUTE cycle, the interrupt operation must

The controller then awaits the completion of an EXECUTE cycle. Thus, if the GNI instruction is issued during a

be synchronized with controller operation. Thus, there are two flip-flops associated with an interrupt. The first,

controller FETCH cycle, the controller completes the current FETCH cycle and an EXECUTE cycle.

designated INTERRUPT, stores a bit denoting that a GNI instruction has been issued while the controller is

the GNI is received during an EXECUTE cycle, the interface control waits for the completion of the current

«,^/4^ rT!\T \>rrknn r\\

nrul«w OV^VyjlVA
A n;r,.nf>^ ^Qc;rTr.ofo/i TKrrr7DT?rrPT rTMT^

signifies a point in the Control Unit cycle has been reached where the interrupt can be implemented.

flop establishes interrupt timing paths and also prevents PCI

operation. Thus, the

cvMr
This flip-

from being incremented during the interrupt

ROM program resumes at the next sequential address.

An interrupt operation starts when the computer issues a GNI instruction. As a result of this lOT instruction,
the interface control generates an lOT 1 65 (LD INTER) pulse. The leading edge of this pulse loads the content
of the computer's accumulator into the Memory Port Buffer Register. The leading edge also sets the EXT FLAG
to denote the interface is busy (Figure 3-1 8).
flip-flop.

The trailing edge of the JOT 1 65 pulse clocks the INTERRUPT

If the controller is operating in the internal mode, the

INTERRUPT flip-flop is set to permit the

I_lJ^^t_J^^KJ I. i-i i^y x^L\y.

k lining i\ji

t.1110

^to^Cv^i 10 jL^iyj vi\.iv\^

iiiv i-iLyx^ x^x \^x^i^ |^vtiov.

i iiv iv.'UViiiig ^v»£,v \^x

If,

however,

Lino ^uio^

SYNC flip-flop. The traihng edge initiates START DELAY timing and sets the FETCH/EXECUTE
flip-flop to the FETCH state as illustrated in Figure 3-18.

sets the INT

After the normal 350-nanosecond start delay, the PAUSE flip-flop is set. With the setting of the PAUSE flip-flop,
the control clears the MB Register to ready it for receiving information from the Memory Port Buffer. Next, the
instruction decoder logic generates an SOR—

Memory Port Buffer to the MB

MEMPORT gating pulse. This pulse transfers the content of the
EXT GO pulse which clears

the EXT FLAG and INTERRUPT flip-flops to prepare the control for ending the interrupt. This event does not
occur, however, until the end of the EXECUTE cycle.

The EXT GO pulse, after a small propagation delay, gene-

EXT DONE pulse. This pulse, in turn, produces a MEM DONE pulse. The leading edge of the MEM

controller to acquire synchronization. (If the controller is already in the external mode, the synchronization

rates an

function is not required.)

DONE pulse initiates TSl. The trailing edge loads the contents of the MB Register into the IR. The traiUng edge
PAUSE flip-flop so that the timing can advance. The remaining portion of the FETCH cycle is the
same as for normal operation except that the INST SYNC flip-flop prevents the incrementing of PCI during this
FETCH cycle. As an end result, the next instruction is accessed from the next sequential memory location.
also resets the

POP-M COMPLETES
CURRENT FETCH OR
FETCH AND EXECUTE
CYCLES
I

START
DELAY
3S0ns

FETCH OR EXECUTE^^ EXECUTE

During the EXECUTE cycle, the controller executes the instruction in the IR. At the end of the EXECUTE
cycle, the controller clears the INT

SYNC flip-flop to allow the next access from the ROM. The GNI can be used

to enter or leave the external mode as described below.

The GNI instruction can also be used in the external

mode to provide computer-supplied instructions without incrementing PC 1
3.5.10.5

External Mode Operation — The external mode enables the PDP-14 to stop the execution of its

ROM

program and accept and execute instructions supplied via the Memory Port. For selection of the external mode,
the computer places an EEM (0600g ) instruction in its accumulator, then issues a GNI instruction. During the

FETCH cycle for the GNI, the applicable instruction is transferred to the IR. During the EXECUTE cycle for
the GNI, the controller decodes the IR content and sets the EXT MODE flip-flop. It also implements the register
transfer for the EES instruction. To leave the external mode, the computer supplies an LEM (0400g) instruction.
These instructions can be provided by a GNI or LDE instruction; the LDE instruction increments PCI while a
GNI does not.
Drawing D-FD-PDP- 14-0-6 shows the overall functions performed for EEM and LEM instructions. For an EEM
instruction, the EXT

MODE flip-flop is set during TSl of the EXECUTE cycle. For an EES instruction, the

EXT MODE flip-flop is set and a register transfer is implemented during TSl. That is, the contents of PCI are
transferred to PC2 to ready the controller for a subroutine jump.

At the beginning of the next fetch, the external mode control clears the MB Register and asserts the EXT FLAG.
It then waits for the

computer to provide its next instruction. The computer, upon sensing the EXT FLAG

condition, can supply another instruction using a GNI (if PCI is not to be incremented) or an LDE (if PCI is to

be incremented).
EXT GO

Upon receipt of one of these lOTs, the controller clears the EXT FLAG (to denote the inter-

face is busy), then transfers the content of BAC 0—1 1 to the

{PAUSE«EXT MODE S INT SYNC)

MB Register via the Memory Port Buffer. After this

function is complete, the controller generates an EXT DONE pulse. This pulse advances the timing from PAUSE

EXT DONE L
(EXT GO«IIMT SYNC)

to TSl

MEM DONE H

During TSl, the MB Register content is transferred to the IR. During TS2 of an LDE, PCI is

incremented.
*

DENOTES AN AND FUNCTION

To leave the external mode and return to ROM operation, the computer provides an LEM or LER instruction.
Figure 3-18 FDP-14 Interrupt Mode Timing

3-18

A GNI or an LDE lOT instruction can be used to transfer the mode control instructions. During the FETCH
cycle, the LEM or LER is placed in the IR. During the EXECUTE cycle, the EXT MODE flip-flop is reset and

for LER instructions a register transfer is implemented. This transfer returns the content of PC2 (the subroutine

return address) to PCI so that

STEP- DOWN
TRANSFORMER a
FULL-WAVE

ROM operation can resume at the correct memory location.

OUTPUT

RECTIFIER

GATE

^
3.6

O, AND A BOX CIRCUIT DESCRIPTION

w—

FILTER AND
BLEEDER

3.6.1

Input Circuits

—

TT-^

AC Input Converter — Each K578 module contains eight identical converter circuits. Each circuit
(Figure 3-1 9) consists of a full-wave rectifier (and filter) that converts a
5-Vac input to +5 Vdc. A neon indicator is included at the input to denote the presence of an ac input. A diode output gate connects the logic sig3.6.1.1

SCHMITT
TRIGGER

w—

1 1

nal to a signal return line.

K579 AC INPUT CONVERTER

The operation of the K579 module is essentially the same as the K578. The K579

contains light-emitting diodes (LEDs) instead of neon lights and a Schmitt trigger for contact-bounce filtering.

STEP-DOWN
TRANSFORMER a
FULL-WAVE

The K579 is used only in the BX14-SA input box.

RECTIFIER

3.6.1.2

FILTER AND

NEON /^-v
INPUT ( •)
INDICATOR VLX

DC Input Converter — Each K564 module contains eight identical dc converter circuits. Figure 3-19

also shows the circuit elements for a dc converter.

The dc converter consists of a transistor input switch, an RC filter, a Schmitt trigger, and an output gate.

OUTPUT

BLEEDER
1

GATE

—f~

"'^^

light-emitting diode (LED), in series with the dc input line, denotes the presence of an input.

K578 AC INPUT CONVERTER

The converter can accept inputs having a range from 10 to 55 Vdc (or with an external resistor, inputs from 55
to 1 30 Vdc).

For input voltages greater than 24 Vdc, a jumper clamps the base of the input switch to ground.
DC INPUT
10-55 VDC

This jumper collectively controls all input switches in the module. With this jumper connected, the input switch

remains off, and inserts a 1 .5K resistor in the input voltage divider. For input voltages from 10 to 24 Vdc, the

jumper is disconnected and the input switch shunts the 1 .5K resistor.

LIGHT-

*;) EMITTING
DIODE

The input filter removes input transients (such as may be caused by switch bounce) to prevent erroneous triggering of the Schmitt trigger.

The circuit has a response time of 2 milliseconds.

An overvoltage clamp protects the filter and the Schmitt trigger from excessive input voltages.
-,:

r-'

OVERVOLTAGE

fCLAMP

The Schmitt trigger has an upper (or turn-on threshold) of -H2.7 to 3 Vdc and a lower (or turn-off threshold)
of 1 .5 Vdc or less. Thus, with a dc voltage of + 10 Vdc or greater at the input terminal, the Schmitt trigger latches
in the on state and provides a positive asserted output.

This output remains positive until the input drops below

the lower threshold of the circuit.

CONNECTED

FOR AN INPUT

•

GREATER THAN 24V

—w\ »

DEC
384

3.9^F
3.6.2
3.6.2.1

Output Circuits
Isolated AC Switch — Each K614 or K61 6 module contains four identical ac output circuits and one

R-C
FILTER

common master oscillator. Each output circuit consists of a diode AND gate (for positive inputs), a 2-MHz

(essentially an open circuit) to the load.

—
-W—
H

OUTPUT
GATE

DC INPUT CONVERTER

gated (or slave) oscillator, and a Triac output switching circuit as shown in Figure 3-20.

The active switching device for an output is the Triac.

SCHMITT
TRIGGER

-wv

In an off state, this device provides a high impedance

For turn on, this device requires a negative dc gate voltage.

Figure 3-19 Input Converter Circuits

Two

oscillators are used to develop this gate voltage as described below.

The master oscillator operates at a natural frequency of approximately 5 kHz.

Its output is a non-symmetrical

waveform with a positive pulse equal to approximately 10 percent of the duty cycle. The master oscillator out-

The slave oscillator drives a Ferrite-core isolation transformer. The high-energy pulses coupled to the secondary

put is gated to the slave oscillator by setting the K207 flip-flop.

of this transformer are rectified and filtered. The resulting negative dc level (a nominal 2 to 4 dc) is used to

pulses gate "on" the slave oscillator.

With this action, the master oscillator's positive

The slave oscillator operates at a natural frequency of approximately 2 MHz.

Thus, its output is a burst of 2-MHz pulses occurring at a 5-kHz rate.

switch on the Triac.
terminal.

When on, the Triac provides a low-impedance path between the ac input and the load

A neon indicator denotes the output is present.
3-19

Range 0.01 to 0.3 seconds — The 22 /nF and 220 mF capacitors are disconnected from the RC network.
Range 0.1 to 3.0 seconds — The 220 (iF capacitor is disconnected from the RC network.

Range

FERRITE
CORE

AC "HOT"

TRANSFORMER

- All three capacitors are connected in the RC network.
Range up to 4 minutes, 45 seconds — Capacitance is added to the RC network in place of the jumper.
1

.0 to 30 seconds

5kHz MASTER
OSCILLATOR
+5V

+ 5V

+ 5V
INPUT °

+ 5V

M—

DISABLE

(NOT USED)

INPUT

GATE

-+«-

K207 INPUT o-

2 MHz GATED
OSCILLATOR

INPUT
GATE

TO OTHER GATED
OCILLATORS

o LOAD GRD

OUTPUT
SWITCH

Figure 3-20

AC Isolated Switch
Figure 3-2 1

DC Driver

The Triac is switched off by eliminating the gate potential. For this function, the external control flip-flop is
switched off. This action disables the slave oscillator input gate. The Triac does not switch off, however, until

Figure 3-22 is a schematic and simplified diagram of a timer circuit.

zero current is drawn by the load.

flip-flop input to the diode input gate.

The Triac circuit has a number of protective features.

A 5 A fuse protects the Triac from excessive load current

The timer circuit is controlled by a K207

With the flip-flop reset, Ql is on, Q3 is on, and C^^ is charged to approxi-

mately +5V. With Node A at approximately +5V, Q5 is off, Q6 is off, Q9 is off, and Q13 is on. As a result, the
timer output is at ground level.

and a Varistor (or Thyrector) protects it from high-voltage transients. In addition, a high-frequency filter shunts

The delay interval is started when the flip-flop is set. With this action, the positive input to the diode gate

the device. This filter prevents accidental turn on by high-frequency pulses.

switches Ql off, which, in turn, turns off Q3. With Q3 off, C^ begins to discharge through the resistance of the
3.6.2.2

DC Output Driver — Each K657 module contains four identical dc driver circuits. Each circuit consists

of an input gate, a buffer, and a Darlington-pair output switch as shown in Figure 3-21
stages only switch a load to ground.

As denoted, the output

RC network. Transistor Q5 remains off until the voltage at Node A decreases below the emitter reference of Q5
The time required to reach the turn-on threshold of Q5 is the delay interval for the timer. When Q5 begins to

A diode clamp is

conduct, it turns on Q6. Regenerative feedback (provided by the feedback resistor between the collector of Q6

Each circuit uses an LED to denote that its output is on.

also provided to protect the output stages from inductive transients.

This diode is normally connected between

the switched output and the positive source and can be clipped out if not needed.

and the base of Q5) causes Q5 and Q6 to rapidly saturate. The emitter current of Q6 is now provided by the
base-emitter junction of Q5. With Q6 on, Q9 turns on and switches Q13 off and Ql 1 on.

The end result is that

Q13 provides a logical 1 to the sample return. This output denotes the timer is on.
3.6.3

Accessory Box Circuits

The timer flip-flop must remain set until the timer completes its timeout.
3.6.3.1

Timer Circuits — Each K302 Timer module contains two independent timer circuits. Each circuit pro-

is set

If not, Q3 turns on when the flip-flop

and ends the delay function. In addition, if the inputs that qualify a timer for turn-on are part of the timer

vides standard time delay ranges. These ranges are established by selecting capacitor values for an RC network.

turn-off equation, then they too must remain true during timeout. Figure 3-23 illustrates the timing relation-

A potentiometer, that is also part of the network, enables vernier adjustments within the selected delay range.

ships for these features.

The selectable delay ranges are as follows:

can be used again.

3-20

The timer flip-flop must be reset (and C^^ must again be fully charged) before the timer

GATED
TRUE
OUTPUT

INPUT DATA

DIODE

^
K^
,

(FROM >-0
K207 FF) ^

M
f^ M

INPUT GATE 1, ri
(NOT USED)

*-~VAt

(

INVERT

OUTPUT
(TEST GATE)

OUTPUT

—

GATE

TRUE
OUTPUT

INPUT DATA
INPUT GATE

U>]

^ 09

DETECTOR
Q5,Q6

pX^^^
[y^^
I

INVERTED OUTPUT
(NOT USED)

Figure 3-22 Timer Module, Time Delay Circuit, Simplified Schematic Diagram

and Equivalent Logic Diagram

TIMER
SYF

PART OF
ROM CYCLE
TIME

3.6.3.2

CONTROL

K274 Retentive Memory — During normal operation of the K274, a flip-fiop is set by a combination of

SET and ENABLE signals for the appropriate memory.

INPUTS

flip-flop.

It is then reset by

RESET and ENABLE for the same

The reed relay simply follows the operation of the flip-flop.

K207 CONTROL
FLIP-FLOP

The sample return for the PDP-14 is sampled from the flip-flop and not the reed relay; hence, the system does not
0.3% OF MAXIMUM
have to wait on the propagation time of the relay. This means much faster response from the retentive memory

DELAY INTERVAL

than would be possible using the relay contacts.

The relay state is sampled during INITIALIZE H to re-establish the state of the flip-flop before the power failure.
Otherwise, the relay only follows the flip-flop.
TYN
TRUE

TIMER

OUTPUT

power from the relay coils permitting the flip-flop to stabiUze before the relay coils are energized when
^v-

TYF TRUE

When INITIALIZE H is generated by the PDP-14, it removes

-TYF TRUE

INITIALIZE H is removed.
The LEDs on the K274 module Ught when the memory is set. The memory can be manually reset by actuating
SI

Figure 3-23 Timer Relationships

Moving SI up will clear the upper memory (even addresses) and moving it down will clear the lower memory

(odd addresses).

3-21

CHAPTER 4
DETAILED MAINTENANCE
GENERAL

4.1

Table 4-1

Recommended Tools and Test Equipment
The information presented in tliis chapter is more in the form of performance standards and measurement pro-

Model

Manufacturer

VOM

630NA

Triplett

Voltage measurement

Oscilloscope

453

Tektronix

Voltage and waveform measurement

Module Extender
Module Extender

W982
W984

DEC
DEC

Access to double-height modules

Soldering Iron

PU-1

Weller

Module repair

Solder Remover

Standard

SoldapuUt

Solder sucker for parts removal

I/O Interrogator

BT14

Checking input and output conditions

Computer

PDP-8

DEC
DEC

Item

cedures rather than adjustment data. However, pertinent adjustment information is included wherever appropriate.

In those areas where it is not included, it is assumed the individual servicing the equipment is adequately

trained to perform the test, interpret the results, and if necessary, substitute components.

LEVEL OF MAINTENANCE

4.2

The PDP-14 user is encouraged to maintain his controller by judiciously replacing modules thought to be defective with known good modules as described in Chapter 2.

This is recommended for two reasons:

l)it

is the

fastest way to repair the controller; and 2) it requires less training for the maintenance personnel at the site.

Use

Access to single-height modules

Diagnostic

Time does not permit most users to find specific problems within a module and defective modules can be returned
to DEC for repair at a modest charge.

4.4

SYSTEM CHECKOUT

Personnel Intended to Use This Chapter

4.2.1

4.4.1

Power Voltage Checks

This chapter contains information intended to aid the well qualified maintenance individual in isolating faults

within a module or modular unit. Maintenance at this level should be attempted only by persons thoroughly
familiar with Chapters 1,2, and 3 of this manual and with digital troubleshooting and maintenance techniques.

The PDP-14 power supply is designed for a nominal +5 Vdc output. This voltage, measured at terminals 1 and 2
of TB 1 should be 5. 1 5 V when the PDP-1 4 is first started with no load. After warm-up the voltage may drop to
,

no less than 4.90V under full load (7A). Should the voltage be incorrect, make the appropriate adjustment on
4.2.2

the power supply printed circuit card.

Relationship to Other Chapters

It is important to re-emphasize that Chapter 2 is intended for the user and the troubleshooting techniques

described there would be carried out by the user's electricians.

to perform the level of maintenance detailed in this chapter but only after the technicians are thoroughly famihar

with the contents of Chapter 3.

4.4.2

Power Supply Ripple Check

The user might wish to train a few technicians

It is further assumed that the procedures described in Chapter 2 have been

Use a Tektronix Model 453 or equivalent oscilloscope to check the ripple content of the power supply at terminals 1 and 2 of TBI.

The ripple should not exceed 10 mV peak-to-peak under full load.

thoroughly explored before proceeding with the tests described here.
4.4.3

4.3

TOOLS AND TEST EQUIPMENT

Table 4-1 Usts the tools and test equipment recommended for maintenance of the PDF-14. Use of lesser quaUty
instruments is not recommended, as it may seriously affect the reliability of the measurements and lead to false
conclusions.

4.4.3.1

Power-up Sequence and Manual Controls
Power-up Sequence - The following checks are made on the M742 module located in slots A22 and B22.

Each check is performed by turning the power off and then making the appropriate test as power is turned back
on. Synchronize oscilloscope on B22H1 for all tests.

The waveforms illustrated in Figure 4-1 correspond to the

following step numbers.

4-1

MODULE

(AB22)

M742

EMTR
Q7

NODE A

2.8
t.4

M742

AN2

STARTUP-*- —Rl N

WAVEFORM

SIGNAL

(?) SWITCH ON

_y^

--^
ZOOMS

MODULE

SIGNALS

(AB22)

RESHOLD OFSCHMITT TRIGGER C

-STOP SWITCH PRESSED

AE2

M74Z

CONTROLS
ENABLE L

AH 2

M742

RUN(I) H

-\v-

BH1

M742
M742
M742

INITIALIZE H

-^v-

-130NS

k
y •—200ns
1

START EXT L

M742

AJ2

BO 2

BF2

M742
M742
M742

BH1

BJ2
BF2

INITIALIZE H
CLR PCKD H
CLR MB H

(CHECK ALL 3)

M742

BUI

(4Al

SHUTDOWN L

90 MS

90MS

SYNC A22E2

NOTES:
1.

SYNC B22H1

NOTE

CLR pa (1) H
CLR MB H
(CHECK ALL 3)

Pin numbers refer to

Pin numbers refer to M742 located in slots AZ2 and B22.
circled reference paragraph 4.4.3.t of the te«t.

Refer to text porogroph
for restart

Numbers

Check charging of CI 4 at the emitter Q7.
trigger in about 200 milliseconds.

It should reach the threshold (2.8V) of Q7,

Q8 Schmitt

4.4.4

in slots

A22

4.4.3.2 and

fig. 4-1

checks.

Processor Timing Checks

4.4.4.1
2.

located

Figure 4-2 Manual Controls Check

Figure 4-1 Startup Timing

M742

and B22.

;

Check the output of Schmitt trigger Q7, Q8, and Q9. The output at pin AN2 (SWITCH ON L) should
drop, then go high for about 200 milliseconds after power is turned on and finally return low.
Check that the 200-nanosecond START EXT L pulse is generated at AJ2 by the high-to-low transition
of the collector of Q9. This pulse is used to start the PDP-14 timing.
Check INITIALIZE H (BHl), CLR PCI H (BJ2), and CLR MB H (BF2) to ensure they go high for
90 milliseconds after power on. Also check SHUTDOWN L which generates these pulses (BUI).

General — The PDP-14 is an asynchronous processor; it does not use a common clock and hence each

timing component is largely independent of all others. All of the timing in the PDP-14 is accomplished by oneshot multivibrators with the last one-shot in the system triggering the first one
to start the next cycle. Note in Figure 4-3 that a free-running multivibrator

can be built using two one-shots.

ONE-SHOT

The on time and off time of a one-shot can be independently controlled. This
concept is utilized in the PDP-14 to permit the timing of each part of the sys-

Check INITIALIZE L (BK2) to ensure it goes low for 90 milliseconds after power up. INITIALIZE H
is the inverted signal of

4.4.3.2

INITIALIZE L.

Manual Controls Check — All of the following tests reference components and pins on the M742 module

The waveforms

Check operation of the STOP switch by depressing it and check RUN ( 1 ) H (AH2) to ensure it goes low.

Check CONTROLS ENABLE (AE2) and RUN ( 1 ) H (AH2) with the processor stopped to make sure it
is at OV.

pulses.

The length of each pulse is independent of all others.

The PDP-14 System is easy to troubleshoot since a pulse can be injected and
then traced as it is propagated through the system. In the PDP-14, depressing

illustrated in Figure 4-2 correspond to the following step numbers.

ONE -SHOT

many one-shots as are necessary to generate the required number of timing

located in slots A22 and B22. Synchronize the oscilloscope on A22E2 for the following checks.

tem to be optimized. The concept can be further expanded by cascading as

This line enables the START and CONTINUE switches only when the controller is stopped.

Before pressing CONTINUE check to make sure INITIALIZE H (BHl), CLR PCI H (BJ2), and

Figure 4-3

Free-Running Multivibrator

START or CONTINUE injects a pulse that starts the timing. The pulse that
starts the timing is the START EXT L pulse which can be measured at pin
AJ2 of the M742 module. This pulse appears once each time the START or CONTINUE switch is released, provided the controller was halted before activating the START or CONTINUE switch. Figures 4-4 and 4-5 define
the timing chain sequence.

CLR MB H (BF2) have all gone high and INITIALIZE L (BK2) has dropped low. This check ensures
that the timing failure detect E3 is functioning properly.
4.

Pressing either START or CONTINUE causes the processor to resume timing.
as the power-up sequence described in Paragraph 4.4.3.1

4-2

4.4.4.2

and Figure 4-1

The sequence is the same
when the switch is released.

Processor Timing Assumptions — The following paragraphs assume that the controller switches to a RUN

START EXT L. The START EXT L pulse is generated each time the START or
CONTINUE switches are pressed and then released. The RUN state is defined by the following conditions:
state each time it sees

Signal

INITIALIZE H
INITIALIZE L
CLR PCI H

State

Low
High

CLR MB H

Low
Low

SHUTDOWN L

High

CONTROLS ENABLE L
SWITCH ON H
RUN(1)H

High

NOTE:

Low
High

M742 Pin

Processor timing is initiated by the presence of a pulse at BK2 (START EXT L) that is generated on
the M742 module during power up or when the START switch or CONTINUE switch is pressed. If

BH2
BK2

processor timing will not run, it is necessary to inject this pulse by pressing the START or CONTINUE
switch.

BJ2

BF2
BUI
AE2

AN2
AH2

The leading edge of START EXT L triggers the START DELAY which is a 1 50-nanosecond pulse. The
START DELAY pulse can be measured at the collector of Q6 and is 200 nanoseconds in duration.

The trailing edge of START DELAY triggers START CYCLE H which lasts 200 nanoseconds and is
measured at pin AT2.

Logical High = 3.0 to 5.0V
Logical Low = 0.0 to 0.7V

FETCH H (pin AJ ) is high, the traiUng edge of START CYCLE triggers MEM GO (pin AN ) which

is a

4.4.4.3

Detailed Timing Analysis (FETCH Cycle) — The following tests are made on the M741 module located
5.

in slots A23 and B23.

The step numbers refer to numbered waveforms on Figure 4-4. Before proceeding with

these tests it is desirable to remove the ROMs (ROM timing is covered in Paragraph 4.4.5).
will function without the memory.

It is later reset

by MEM

With the memory removed, the trailing edge of MEM GO triggers MEM DONE (pin 10 of IC El 1

ETCH REV C). This is a

If the controller still does not run, proceed with the

The steps are presented .with Figure 4-4 to assist the reader in utilizing this type of timing chart for troubleshooting

50-nanosecond pulse.

The trailing edge of MEM DONE ( 1 00 nanoseconds) resets PAUSE ( 1 ) H (pin BT2) and initiates
TSl (l)H(pinBM2).

The procedure for utilizing Figures 4-5, 4-6, and 4-7 is the same and therefore only a general discussion
8.

of these timing charts is included.

The leading edge of MEM GO causes PAUSE ( 1 ) H (pin BT2) to go high.

DONE.

following steps.

purposes.

200-nanosecond pulse.

The controller timing

If removing the memory from a PDP-14 which will not run causes the con-

troller to start, the problem is in the memory timing.

The propagation of the pulses is traced as outlined in the remaining steps.

EXECUTE CYCLE

MODULE

The leading edge of TSl (1) H starts a 400-nanosecond one-shot consisting of E17 and Q8. The output
of this timer can be seen at the collector of Q8 as a 400-nanosecond pulse. The falling edge of the
one-shot output (collector of Q8) triggers T PULSE (pin BHl) which has a duration of 100 nanoseconds.
The trailing edge of T PULSE H (pin BHl ) ends TS 1 (pin BM2) and initiates TS2 (pin BL2).

(AB23)

BK2

M741

COLL
06

M741

AT 2

M741

10.

The leading edge of TS2 starts another 400-nanosecond one-shot consisting of El 5 and Q4. The output
of this one-shot can be measured at the collector of Q4. The trailing edge of the one-shot then generates another T PULSE H (pin BHl). When both T PULSE H (pin BHl) and TS2 are present, then

END CYCLE (pin AFl) is generated.
11.

The trailing edge of T PULSE resets TS2 (pin BL2) and END CYCLE (pin AF 1 ) and initiates a START

CYCLE (collector of Q6) for the EXECUTE cycle.
AN1

M741

BT2

M741

4.4.4.4

- The internal EXECUTE cycle is initiated by the END CYCLE pulse generated at the completion
of the FETCH cycle. Before trying to troubleshoot this section, be sure the processor is attempting to execute

Ell

PIN 10

Detafled Timing Analysis (EXECUTE Cycle: JFF, JFN, SKE, SKZ, TRR, NOP, JMR, and SKP

Instructions)

M741

one of the instructions noted in the paragraph heading.

If the memory has been removed and the PDP-8 is not

connected, the controller will be executing NOPs and this is the best place to start.
BM2

M741

Other instructions can be traced in the same manner using the oscilloscope loop procedure outhned in Paragraph
BH1

M741

4.4.8.

BL2

M741

the procedure outlined in Paragraph 4.4.4.3. If the processor will not run, it is necessary to depress the START

AF1

M741

Figure 4-5 is the timing diagram for the internal EXECUTE cycle.

The troubleshooting procedure is the same as

or CONTINUE switch and then trace the propagation of the pulses through the system.
SYNC ON B23K2

Figure 4-4

FETCH Cycle Timing Analysis (Paragraph 4.4.4.3)

4-3

FETCH CYCLE-

MODULE SIGNAL

WAVEFORM

M741

AFi

MODULE SIGNAL

[AB23)

— —EXECUTE CYCLE

(AB23)

END CYCLE L
AF1

M74)

END CYCLE L
SYNC ON A23 F1

M741

AT2

M74(

BM2

START CYCLE H

M741

START CYCLE H

M741

MEM GO H

TS) (1) H
AN1

BL2

M741

TS2 (1) H
PAUSE (1)H

M741

BH1

T PULSE H

E11

MEM DONE L

PIN 10

M741

AFt

SYNC ON A23F1

BL2

M741

TSl (1) H

M741

TS2{1) H

M741

T PULSE H

Figure 4-5 Internal Execution (JFF, JFN, SKE, SKZ, TRR, NOP, JMR, and SKP)

(Paragraph 4.4.4.4)

END CYCLE L

O AND

The following actions occur during TSl and TS2:

TSl
Figure 4-6
a.

A decision is made and the result of the decision is stored in the JF-OK or SK-OK flip-flop.
The register transfer is made if a TRR instruction is being executed.

PCI is updated if the instruction is a JMR or SKP instruction.

(Paragraph 4.4.4.5)

TS2

MODULE] SIGNAL

100NS

AF1

M74I

END CYCLE L

DetaUed Timing Analysis (Two-word EXECUTE Cycle: JMP, JMS, and TRM Instructions) - The 2-word
START CYCLE H

EXECUTE cycle requires an additional access to memory to obtain the data word. This type of instruction is
therefore identical to the FETCH cycle, except that the MB is transferred to the register specified by the previous

AT2

instruction instead of the word being decoded by the IR and then being executed. Therefore, the procedure

BU2

M741

BRl

M741

I/O STROBE L

BH1

M741

T PULSE H

AF1

M741

END CYCLE L

M741

;

16 to

described in Paragraph 4.4.4.3 can be followed.

18.5(i.s

I/O CYCLE 11) H

ASSERT ADDRESS

SET OR
RESET OUTPUT

The timing diagram for the 2-word EXECUTE cycle is shown in
6.5(is

Figure 4-6.

4.4.4.6

WAVEFORM

(AB23)

PCI is updated by adding 1 (i.e., PCI + 1 -> PCI).

4.4.4.5

Two-Word Instruction Execution (JMS, JMP, and TRM)

No action if the instruction is a NOP.

Detafled Timing Analysis (I/O Execution: TXD, TYD, SYF, SYN, TXF, TXN, TYF, and TYN) -

ICONS

Figure 4-7 shows the I/O cycle beginning with the END CYCLE pulse generated at the end of the FETCH cycle.

The I/O cycle is very long to permit gates in the K-Series modules to settle. Therefore, the I/O CYCLE ( 1 ) H
(pin BU2) is 16 to 18.5 microseconds and I/O STROBE L (pin BRl) is 6.5 microseconds. During the I/O cycle

the address to the I/O Box is asserted.

ICONS

SYNC ON A23F1

The test data is then strobed back to the processor and is stored in the

TEST flip-flop by END CYCLE if the tested condition is met. The I/O STROBE is used to turn outputs on or
off if the instruction is an SYN or SYF.

Figure 4-7 I/O Execution Cycle (TXN, TXF, TYN, TYF, TXD, TYD, SYN, and SYF)

(Paragraph 4.4.4.6)

4-4

4.4.5

during I/O STROBE L. If a Test instruction (TXN, TXF, TYN, TYF) is decoded, nothing happens until

Memory Timing Checks

Memory timing is initiated by MEM GO (pin ALl) and
PAUSE (1) H (pin AL2) on the G924 ROM Selection board located in slots Al 3, B 13, CI 3, and Dl 3 for the first
Figure 4-8 shows the timing relationships in the memory.

END CYCLE when the results are strobed into the TEST flip-flop. If the test is true, the TEST flip-flop is set;
if the test is not true, the condition of the

TEST flip-flop remains the same.

K of memory.

MODULE SIGNAL

WAVEFORM

MODULE

SIGNAL

WAVEFORM

(AB23)

AT2

M74i

BT2

M741

AN1

M741

INTERNAL

G924

START CYCLE H
AE1

M741

EXECUTE (1) H

AT 2

M741

START CYCLE H

BU2

M741

I/O CYCLE (1) H

BR1

M741

I/O STROBE L

BH1

M741

T PULSE H

AF1

M741

END CYCLE L

BD1

M741

(TEST TRUE)

ACI

M741

PAUSE CYCLE H

READ PULSE

FERRITE

INTERNAL

G923

XFMR OUTPUT

INTERNAL

G9Z4

STROBE DELAY

BK1

G924

STROBE PULSE

BL1

G924

MEM DONE L

El
(lof 12)

M746

ROM—MB

BM2

M741

TEST FLOP (1) H

(DIRECT SET)

SYNC ON A23F1

NOTE:

Figure 4-9 I/O Timing Checks (Paragraph 4.4.6)

Test poims accessible from wiring side of mainframe are
shown for ROM no. 1, other waveforms must be observed on
G923 module of ROM assembly.

Figure 4-8

Memory Timing Checks (Paragraph 4.4.5)

The address and sample return lines are connected to all boxes and the package select line to only one box.
Therefore, consider the following points when troubleshooting the I/O system on the PDP-14:

The output of the Ferrite transformers is connected directly to a gate which is selected by STROBE 1 through

If 50 percent of the test instructions are yielding false results, the sample return lines should be checked

for an open or short circuit condition.

STROBE 8. The output of this gate is then connected to a SET-RESET flip-flop which is set by the STROBE
PULSE and is cleared at the end of PAUSE.

If a given input in every Input Box or a given output in alternate Output Boxes yields false results, the

address lines from the M743 module should be checked.

The data from the memory output is applied to the direct-set inputs of the memory buffer. The data is present
at the memory output for about 300 nanoseconds.
It is important to note that the processor timing as discussed in the previous paragraphs must be operating

If one entire Input or Output Box is inoperable, check the package select lines.

If only one input or output malfunctions, check the modules in the I or

O Box.

properly before the memory timing can be checked. The step-by-step procedure that is used to check the mem-

ory is of the same type as the procedure used to check the rest of the processor.

4.4.7

The

Computer Interface Check

DAM Computer Interface between the PDP-8 family computer and the PDP-14 can be used for a variety of

4.4.6 I/O Timing Checks and Notes

apphcations.

The I/O process is initiated by a START CYCLE H pulse which sets I/O CYCLE (1) H as shown in Figure 4-9.
During I/O CYCLE (1) H the appropriate input or output is selected and the K-Series logic in the Input or Output

Box is given time to settle.

If an SYN or SYF instruction is decoded, the appropriate output is set on or off

The most common use of the interface is during startup of the PDP-1 4 to develop and test the pro-

gram which the ROM will eventually contain. The second mode of operation permits the PDP-8 to monitor functions being performed by the PDP-14 or to use the PDP-8 to analyze analog data and then have the PDP-14

execute the decision. In either event, the hardware is the same.

4-5

Figure 4-10 illustrates the basic relationship between the

INPUT

Table 4-2

(See note)

PDP-8andthePDP-14.
PDP-8
Using the DA 14 Computer Interface, the PDP-8 can

COMPUTER

MEMORY PORT
(DEVICE CODE 16g)

Short Patch for Computer Interface Checkout

PDP-14

OUTPUT REGISTER
(DEVICE CODE Ug)

transfer instructions to the Memory Port or determine

events in the PDP-14 by reading the Output Register.

NOTE

There are three registers which permit the PDP-14 to

Input register is not used on late model machines.

communicate with the PDP-8. The most frequently used
register is the Memory Port.

When instructions are

entered into the PDP-14 via the Memory Port, the PDP-14

Figure 4-10 PDP-8/PDP-1 4 Interface

operates exactly as though the information is coming from
its Read-Only

7300

7601

1222

7602
7603
7604
7605
7606
7607
7610

6165
6161
5203

_.7611
~r-r

Memory. The second register is the Output

7600

7612
7613
7614
7615
7616
7617
7620
7621
7622
7623
7624

The results of tests on

inputs and outputs are displayed in the Output Register.

The third register is the Input Register. The Input Register will not be discussed in this chapter because it is used
at very few installations and is not available in late mode! machines wired for MAP-14.

Many of the problems which appear to be PDP-14 problems may be due to a PDP-8 I/O bus problem, skip and
interrupt bus problem, or cable problem. However, before any troubleshooting can begin, the PDP-14 timing

must be operating. This can most easily be determined by checking INITIALIZE on pin B23H1 of the M741

START,

CLA CLL
TAD EEM

/CLEAR AC & LINK
/GET EEM
/INTERRUPT PDP-14
/WAIT FOR COMPLETION

GNI
SEF
JMP .-1
TAD K4226

1224
6164

/LOAD TRM

LDE
SEF
JMP .-1

6161

5207
7240
6164
6161
5213
1223
6164
6176
7402
5200
0600
0400

CLA CMA
LDE

/AC=7777
/LOAD PDP-14 MEMORY PORT

SEF
JMP .-1

/WAIT FOR EXTERNAL FLAG

TAD LEM

/LEAVE EXTERNAL MODE

LDE

ROR

/GET OUTPUT REGISTER TO AC
/HALT WITH 7777 IN AC
/DO AGAIN

HLT
JMP START
EEM,
LEM,
K4226,

0600
0400
4226

module.

With the PDP-14 running, run TEST-I4 which will check the entire PDP-14 Processor and the computer interface.

The following tests should only be used if TEST-14 prints PDP-14 HUNG or PDP-14 STOPPED and it is known
that the PDP-14 is actually running, or the PDP-14 is not executing instructions properly as received from the

If any of the above conditions are not met, then a thorough investigation of the problem must be undertaken.

Remember that PDP-8 diagnostics may not necessarily find problems related to the I/O bus. This test should be
repeated after replacing the

PDP-8. The PDP-14 is running if INITIALIZE H (pin B22H1) is low.

Is.

The short patch presented in Table 4-2 performs the functions listed below.

CMA with a NOP which will cause conditions c, d,

and g to be all Os instead of all

Figure 3-1 8 may be of assistance in determining the timing of the interface.

It should be used in conjunction

with Figure 3-18 and the associated test.

4.4.7.1

Running Standard DEC Software on the Serial-Line Interface - All DEC standard software for program

-trE'vcujpiiiettt aitKi uiagii^aiic^uipuaca^ iiiciuuiiig piziciiv^o coutainuu in iHis manuat, eaii oc run^ on
a.

Generate a PDP-14 interrupt.

interface.

Place the PDP-14 in external mode.

program:

Transfer all 1 s from the PDP-8 through the Memory Port to the Output Register and back to the

me senar*nne

In order to do this, it is necessary to set up the Channel Status Register using the following short

Location

Contents

Comment

PDP-8 through the Output Register.
d.

Return the PDP-14 to internal mode.

Halt the PDP-8 with all Is in the AC.

7604
0206
6143
7602
5605
0200

By replacing HLT with NOP the computer will loop and any of the BAC, BMB, or skip and interrupt lines on the
PDP-8 can be checked. The following items can then be easily scoped to check if they are operating properly.
a.

Interrupt flip-flop on M745.

External mode flip-flop on M745.

d.
e.
f.

4-6

BMB lines should all be Is at one time.
BAC lines should all be Is at one time.
The skip and interrupt buses on the PDP-8 can be checked.
The Output Register should contain all 1 s after one pass.
The AC should contain all s after the computer stops.
1

LAS

ANDK17
LCSR

HLT CLA
JMP I ±

200
K17,

To use this program, proceed as follows:

Load the desired program (i.e., ABE-14, DEMON-14, etc.) in the normal manner.
Once it is loaded, toggle the above program into core in the same manner as the RIM loader.
Load the starting address which is 7600.
Set the Switch Register equal to the channel number of the PDP-14 to be worked with.

Press CLEAR, then CONTINUE.

The program sets up the Channel Status Register, and if CONTINUE is pressed, a jump to location 200 is executed
and the program loaded in Step 1 above starts. If the program starts at an address other than 0200, do not press

Table 4-3
I/O Fault Identification

CONTINUE, but instead start the program in the conventional manner.

Type of Fault

Scope Loops and How You Get Them

All tests showing true (or false)

Test True line

0-17 addresses in all I Boxes failing

XS RET

scope a given function within the controller. They are particularly useful when troubleshooting functions within

20-37 addresses in all I Boxes failing

XS RET

a module.

C Row, O Box testing fails

YS RET

D Row,

4.4.8
4.4.8.1

4.4.8.2

General — Scope loops are used to make the controller perform a given function repeatedly in order to

Procedure — To set up scope loops, proceed as follows:

If necessary, connect the computer using the instructions in Paragraph 2.4.2.

If necessary, load

If necessary, load TEST-1 4 tape using the instructions in Paragraph 2.4.4.

To address TEST-1 4, depress computer STOP key, set SR to 0200, then depress LOAD ADDR key.

If Spare Register is not provided, set SR6 to 1, then depress

Answer program queries for I, O, and A Boxes by typing Os, then depress RETURN key.

The program now begins testing the controller.

4.5

4.5.1

4.5.2

YS RET 1 H

4.5.2

Same address failing in all boxes

ADD 1-2-4-8

4.5.3

Alternate addresses faiUng in all boxes

ADD H

4.5.3.1

Addresses fail in groups of two

ADD2H
ADD4H
ADD8H

Box testing fails

RIM and BIN loaders using the instructions in Paragraph 2.4.3.
Addresses fail in groups of four
Addresses fail in groups of eight

START key.

A maximum of one

Box and two

Boxes failing

4.5.3.2
4.5.3.3

4.5.3.4

Package Select

4.5.4

(PS«H)
Only one address fails

When the program detects an error it types out the error, then halts. If it is desired to loop on the first
error, simply place SRO to 1 before the teleprinter completes the error typeout. If not, depress com-

Cannot set or reset outputs

puter CONTINUE key.
9.

Paragraph

Solution

Module or wire
in box

4.5.5

Set or reset

4.5.6

lines

The program then resumes testing until another error is detected. Repeat Step 8 until the desired point
in the program testing is reached.

SYF 377 will not clear all outputs

Clear hne

4.5.7

(CLEAR I/O L)

A Box

A Box problem

I/O TROUBLESHOOTING

4.5.8

The PDP-1 4 uses four address (ADD) lines and eight package select lines to address inputs and outputs and four
sample return (S RET) lines for testing inputs and outputs. The ADD and S RET Unes are paralleled to all Input

4.5.1

Test True

and Output Boxes; therefore, a fault at any point (backplane, cables, I, O, or A Boxes) will affect all boxes.

The sample return from the Input and Output Boxes is compared with the type of test being performed. The
Each S RET line connects to either all Input Boxes or one-half of all the Output Boxes.

On the input side, an

S RET line connects to either the lower half (address 0—17^) or upper half (addresses 20— 37g) of all Input
Boxes.

On the output side, each S RET line connects to either all outputs plugged into the C Row of the control-

D Row of the controller. If any of these four hues are grounded, it will cause
or
side
of the box) or one-half of the outputs (C Row or D Row) to test "on".
one-half of the inputs (low
high
ler or to all outputs plugged into the

The C-Row output S RET line is also connected to one pin of all sockets in the D Row so that Input Boxes may
be plugged into slots in Row D to provide additional input capability.

TEST TRUE H. For example, if a TXF 00

and

is being executed

Input 1 is off, TEST TRUE H will go high momentarily. However, if Input 1 in the example is on, TEST TRUE H
will remain low.

The state of TEST TRUE H is stored in the TEST flip-flop on the M741 module. To check these

B23U2 (I/O CYCLE 1 H) and observe A23C1 (TEST TRUE H). The 1 side
of the TEST flip-flop can be observed at B23D2. The TEST flip-flop can only be set by the TXN, TXF, TYN, or
TYF instructions and is cleared by the JFF or JFN instructions or INITIALIZE.
lines, synchronize the oscilloscope on

4.5.2

Each package select line affects one Input Box and two Output Boxes. Therefore, if one of the package select

maximum of three boxes.

fault rather quickly with a PDP-8 computer or a BT14 Interrogator Box.

Sample Return Troubleshooting

Synchronize on B23U2 (I/O CYCLE 1 H). Test all input slots, pins D2 (XS RET

The PDP-1 4 utilizes four sample return lines (S RET). XS RET

Because each of the types of addressing lines affect the I/O Boxes in a different way, it is possible to isolate the

Take time in the beginning to establish

whether or not the input or output failures are falUng into a pattern. Table 4-3 should assist in identifying the
fault.

When inputs are used in output slots, these

inputs must be tested with a TYF or TYN instruction.

lines is grounded or open, it will affect a

result is placed on the test true line A23C1

H), and pins B2 (XS RET 1 H).

H returns the test status for addresses Og - 17g

XS RET H returns the test status for addresses 208 - 37g (right side) of all I Boxes.
H returns the status of all O Boxes plugged into the C Row of slots in the controller. YS RET H
H returns the status of inputs 20g — 37g
returns the status of all O Boxes plugged into the D Row or YS RET
when an Input Box is plugged into the D Row output slots to expand the input capability. YS RET H returns
(left side) of all I Boxes.

YS RET

4-7

the low side (Og — 17g) of these boxes. If an input is plugged into the D Row, the slot above it in C Row cannot

4.5.3.1

be used. The most common problem is that one of these lines is grounded and indicates that the input or output

(ADD 1 H) is the least significant bit. If it remains low (i.e., grounded at some point on the system), it will

being tested is on. The S RET line should remain high until an on input or output is tested, at which time it

inhibit the selection of all even-numbered inputs and outputs (i.e., 0, 2, 4, etc.). If it remains high (probably a

should go low for 5 to 1 5 microseconds and then return high. Generally, the fault can be most easily isolated by

bad driver on the M743 module), it will inhibit selection of all odd-numbered inputs and outputs (i.e., 1, 3, 5,

removing all cables from the processor, replacing them one at a time and checking the sample return after replac-

etc.).

Use the procedure described in Paragraph 4.5.3 for troubleshooting.

The source of the S RET in the I Boxes is the input converter (K579 or K564) which uses the

ing each one.

Kl 36 module to drive the S RET line to the controller. The source for the sample return line in the O Boxes
is the

Address Line 1 - Synchronize on B23U2 (I/O CYCLE 1 H). Test A32N2 (ADD 1 H). Address line 1

K207 module which uses the K 135 to drive the YS RET to this controller. The system has no way of

knowing if the output module (K616 or K657) is responding. See Paragraph 4.5.8 for a discussion of the sample
returns in the

4.5.3.2

(ADD 2 H) affects inputs and outputs in groups of two. If it remains low (i.e., grounded), it will inhibit selection
of inputs

and 1, 4 and 5, etc. Use the procedure described in Paragraph 4.5.3 to troubleshoot.

A Box.
4.5.3.3

4.5.3

Address Line 2 - Synchronize on B23U2 (I/O CYCLE 1 H). Test A32R2 (ADD 2 H). Address line 2

Address Line Troubleshooting

The PDF- 14 utiUzes four address lines which select two inputs in the same box and one output in each of two
boxes (one O Box plugged into Processor Row C and one in Row D). To test these lines it is necessary to use

Address Line 4 - Synchronize on B23U2 (I/O CYCLE 1 H). Test A32T2 (ADD 4 H). Address line 4

(ADD 4 H) affects inputs and outputs in groups of four. Therefore, if it is grounded, it will always select a number between Og — 3g, lOg — 13g, etc. If it remains high, indicating an open wire or defective driver on the M743
module, it will always select an alternate number (i.e., in the range of 4g — 7g, 14„ — 17g, etc.).

either a computer running a scope-loop program (Table 4-4) or the interrogator box. Synchronize the oscilloscope

on the leading edge of I/O CYCLE 1 H (B23U2) and watch for an 1 8 to 22 microsecond high-going pulse on the
lines corresponding to the address being selected.

Use SYF 377 (3377g) to assert all address lines.

The four address Unes are decoded in the I, O, or A Boxes by the K161 decoders to select the appropriate point.
Again, a scope loop or interrogator box can be used to determine if they are working properly. Synchronize the
oscilloscope on the leading edge of I/O CYCLE 1

H (B23U2) and use the program listed in Table 4-4.

4.5.3.4

Address Line 8 - Synchronize on B23U2 (I/O CYCLE 1 H). Test A32V2 (ADD 8 H). Address line 8

(ADD 8 H) affects the inputs and outputs in groups of eight. If this Une is grounded, it will always select a
number between Og - 7g and 20g - 27g in the Input Boxes or Og - 7g in the Output Boxes. If the line remains
high, indicating a bad wire or open drive? on the M743 module, it wiH always select a number between lOg 7g
and 30g - 37g in the Input Boxes or lOg - 17g in the Output Boxes. Use the procedure described in Paragraph
1

4.5.3 to troubleshoot.

4.5.4

Table 4-4

Scope Loop Program for Testing an Input or Output
Location

7600
7601

7602
7603
7604
7605

Comments

Contents

CLA CLL

7300
7604
6165

LAS
GNI
SEP
JMP .-1
JMP .-5

6161

5203
5200

/CLEAR AC AND LINK
/SWITCHES CONTAIN INSTRUCTIQ
/INTERRUPT PDP- 14
/WAIT FOR PDP-14 EXTERNAL FLAG

/DO AGAIN

Package Select Lines

Synchronize on B23U2 (I/O CYCLE 1 H). Test pin L2 of faiUng input or output slot on the controller (PS«,

where « is 1, 2, .... 8).

Each package select line selects one Input Box and two Output Boxes.

If it is grounded, it will inhibit selection

of a maximum of three boxes (depending on the configuration). The inputs or outputs in these three boxes will
always test off since no package is being selected.

If one of the package select lines remains high, the test results

will be correct for the selected boxes and the results for any other boxes will be the inclusive-OR of the selected

box and the box whose package select hne is high. Package select Hnes are on pin L2 of each input slot (total of
eight lines).

SET SWITCH REGISTER TO:

TXF

TXN
TYF
TYN
SYF

SYN
CLR

2000
2400
1000
1400
3000
3400
3377

+XXX
+XXX
+XXX
+XXX
+XXX
+XXX

WHERE XXX IS INPUT TO BE TESTED
WHERE XXX IS INPUT TO BE TESTED
WHERE XXX IS INPUT TO BE TESTED
WHERE XXX IS INPUT TO BE TESTED
WHERE XXX IS INPUT TO BE TESTED
WHERE XXX IS INPUT TO BE TESTED

4.5.5

Only One Address Fails

When only one address fails, the trouble may be in a number of places. If the system is rather small (not large
enough to have more than one address affected), it could be one of the problems described previously.

Test instruction that fails, the module-swapping technique described by the flow chart in Chapter 2 should be

thoroughly utilized.

If this does not locate the problem, a broken wire in the box should be suspected since any

of the wires connected to the controller will affect more than one input or output.

SAME AS SYF 377

Example: To test input 24 for an off condition, the instruction is TXF 24 OR 2000 + 024
2024.

4.5.6

Set and Reset Lines

Synchronize on B23U2. Test F2 (E SET n H) of failing output slot, or K2 (ER SET n H) of faihng output slot,

where n is

4-8

If it is a

or 1

The same addressing lines (i.e., address 1

2, 4, 8 and package select) are used to set or reset the outputs.

to set an output on, the selection lines are asserted and then one of two set lines is asserted (high).

output, the addressing Unes are asserted and then one of two reset lines are asserted.

In order

To reset an

The set lines are E SET

1 1

The program will automatically run after you identify address 00 1 7.

12.

Adjust the timer while the computer is running the test, but be sure to get two successive time typeouts

at the time setting you desire.

H (pin F2 of all D Row output slots). The reset lines are
ER SET H (pin K2 of all Row C outputs) and ER SET H (pin K2 of all Row D output slots). Each of these

13.

The program may be stopped and restarted by pressing the STOP and CONTINUE keys.

lines connect to eight Output Boxes and should one become grounded, it will be impossible to set or reset a large

14.

To proceed to the next timer, set key SR3=0 until the teleprinter stops printing the time, then set

(pin F2 of all C Row output slots) and E SET 1

SR3=1 again to repeatedly test thenext timer.

number of outputs.
15.

Repeat Steps 12 through 14 until all timers have been set to the desired time.

Clear Lines

4.5.7

Timer Adjustment Without a Computer

4.6.2

The SYF 377 instruction will clear all outputs except the retentive memories. Should the outputs be clearing
occasionally, the system could be going into initialize (power low) or the system could have an intermittent ground

on the clear line.

If the line were held high, it would not permit the system to be cleared.

The clear line can be

If a computer is not available, a timer can be set reasonably close using the following procedure.

that you practice Step 3 on the new module before attempting it on the defective module.

observed on pin J2 of any output slot (CLEAR I/O L).

A Box

4.5.8

It is suggested

Remove the defective K302 module from the A Box.

Use a piece of tape to make a flag on a small screwdriver (Figure 4-11).

The S RET in the A Box is connected to the accessory device rather than the K207 module as in the O Box. The
accessory device acts as the connection between the output of the K207 module and the S RET line. For

example: the K022 will report the status of the K207 in order to use the output as a storage bit; the K302

module provides an adjustable delay between the time the K207 is set and the time the S RET line indicates to
the controller that the output is on; the K272 or K274 modules contain a mechanically-latched relay which is

sampled. The relay will not be reset by the initiaUze condition and wall therefore retain its state through a power
failure.

TIMER ADJUSTMENT

4.6

Figure 4-1 1

Tape Flag for Counting Screwdriver Turns

Timer Adjustment With a Computer

4.6.1

Use the following procedure to adjust the timer with a computer.

Turn the screwdriver adjustment counterclockwise while carefully counting the turns; listen carefully
for a click. The click must be heard the first time it occurs. Count the turns to the nearest 1 /8th turn

Ensure the appropriate capacitors on the timer have been clipped (Figure 2-10).

Connect the PDP-8 if not already connected according to Paragraph 2.4.2.

If necessary, toggle in

If necessary, load ABE-14 tape using the procedure in Paragraph 2.4.4 for loading diagnostic tapes.

Turn on computer, teleprinter, and PDP-14.

Repeat Steps 3 through 5 for the other timer adjustment on the K302 module.

To address ABE-14, depress computer STOP key. Set SR to 0200, then depress LOAD ADDR key.

cup and remove the same capacitors on the new module that were clipped on the old module.

Set SR3 to a 1 which vdll cause ABE-14 to continually time the first timer and print the time in milli-

Insert the new module into the slot vacated by the old module.

(e.g.,

RIM Loader using the instructions in Paragraph 2.4.3.

11-3/8 turns).

Subtract one turn from the number of turns counted in Step 3 (e.g., 1 1-3/8 — 1 = 10-3/8).

After turning the potentiometer on the new module fully counterclockwise, carefully turn the same

adjustment on the new module clockwise the number of turns determined in Step 4 (e.g., 10-3/8 turns).

seconds on the teleprinter.
8.

Depress computer START key. The program then types:

A BOX IS CONNECTED TO SLOT.
9.

Respond to this statement by typing the connector slot letter for the A Box to be tested. (Refer to
Figure 2-1 for connector slot designations and locations.) The program then types:

IDENTIFY THE HARDWARE ASSOCIATED WITH EACH ADDRESS BY TYPING T FOR
TIMER, M FOR RETENTIVE MEMORY. ALL ELSE EMPTY.
10.

Identify the hardware in each slot using Figure 2-4 as a guide.

4.7
4.7. 1

MEMORY TROUBLESHOOTING
General

Before attempting repairs at the level described in this section, the procedure outUned in Chapter 2 (Paragraph
2.4.8) should be utihzed. Furthermore, the technician must be thoroughly familiar with the theory of operation

of the memory as described in Paragraph 3.5.6.

Any fault that appears in the memory will usually manifest itself

as a group of instructions that are not being retrieved properly. Therefore, thorough analysis of the memory will

usually yield a pattern indicating the problem.

4-9

To make the above analysis, LOAD- 14 and VER-14 diagnostics must be used in conjunction with a computer.
It is important

that the technician be thoroughly familiar with Paragraph 2.4.8 on using VER-1 4 for

ROM fault

Study the output of VER-14 to determine how it relates to the faults listed in Table 4-5. Once the

isolation.

type of fault has been determined, study the appropriate paragraph and perform the tests outlined in that

strobes the data from the sense amplifiers to the buffer, and if it is not present, the buffer will never be loaded.

This condition would be characterized by the memory outputting all Os.
If the memory is outputting all Is, it is probably not being cleared by

PAUSE (1) H at pin BUI on the G923

board.
paragraph.

4.7.3

Table 4-5

ROM Fault Isolation
Type Fault

One Bit in Every Word Set or Cleared

This condition is usually caused by a fault in the data path on the G923 Sense Amplifier board or the M746

module in CI 8 or D18. For purposes of clarity, only bit

See Paragraph

Cause

will be discussed, but the data paths of all bits are the

same (only the specific pin locations change).

No memory output and:
a.

4.7.2
If bit

Timing

Controller halts

b. Controller is running

is faiUng, first determine if it is failing in all

4.7.2.1

Buffer or Strobe

4.7.2.2

Buffer or MB

4.7.3

Every eighth word bad.

Sense Amp

4.7.4

Groups of eight words bad.

Bad Wire

4.7.5

One bad word out of every lOg.

Strobe 1-8

4.7.6

memory stacks by observing the output of the memory

buffer (CI 8D2). If part of the memory is working and another portion is not, it suggests that the M746 module

On the other hand, if the bit is always set (or cleared) and the input to the M746 module (C18E1 for
M746 module. Replace the M746 module and check again. If the output
is still faiUng, replace the M744 module and recheck. If the M746 output is still bad, check the backplane wiring
on the output side of the M746 module.
is all right.

One bit in every word set or cleared.

Group of 8 bad words in 1 OOg

Current Switch

4.7.7

Matrix base drivers

4.7.8

One-half memory select

4.7.9

bit 0) is changing, the problem is in the

Having eliminated the M746 as a possibility (i.e., the input to M746 is static) the problem is on the G923 Sense
Amplifier board or in the backplane between the two. Use a module extender and check the Une connecting to
pin 1 2 of E26 on Drawing G923-0-1 (for bit 0). This is the wired-OR of all the gates that strobe data into the

or 2 groups of lOOg words out

buffer consisting of E25 and E26. If this line is static, determine which gate is causing the problem and replace it.

of IK memory.

No output from one-half of memory

4.7.4

(i.e.,512ioOf 1024io).

Count select 1 K of memory or
selecting more than 1 K.

Field select on M742

One Bit in Every Eighth Word is Bad

This condition is caused by a problem on the G923 Sense Amphfier board. Using bit

4.7.10

as an example, if T85

(Drawing G923-0-1) is open, gate E6 will always see an AND condition and will always set bit

to a 1 whenever

STROBE 8 is generated. If the sense winding is shorted or STROBE 8 is not present, gate E6 cannot see the

AND condition and the flip-flop formed by E25 and E26 remains cleared. These same conditions could be
No Memory Output

4.7.2

caused by a broken core in the memory and this possibility should be investigated first. The cores can be

The two conditions under which there would be no memory output are:

examined by carefully disassembling the memory.
1)

memory timing has failed and the

information is never strobed to the buffer contained in the memory system; and 2) the strobe to the buffer in the

Groups of Eight Words Bad

memory system has failed or the buffer is not being cleared.

4.7.5

The following two paragraphs describe in detail how to troubleshoot these two situations.

Whenever VER-14 shows one group of eight words to be bad, the problem is on the G922 ROM Braid board or
the G924

No Memory Output and Processor is Halting - Synchronize the oscilloscope on PAUSE (1) H (B23T2)
and observe MEM GO H (AL2 of the G924 in doubt). Use the procedure described in Paragraph 4.4.5. The
4.7.2.1

presence of the

MEM GO H pulse indicates that the memory

is getting a start

pulse. If this pulse is not present,

MEM GO H pulse

present, then check

examine the wires from the braid where they are soldered to the connector pins. Examine the pin corresponding
to the defective address and carefully resolder the connection if necessary. If the wire is broken, install a new

wire on the other side of the

MEM DONE L on pin A23E2. If MEM DONE L is present,

MEM GO H is present and MEM DONE L

For a detailed description of how this is done,

in question (i.e., Ql to Q128 on Drawing G924-0-1).

4.7.6
is not,

it.

This problem could also be due to a failure of the transistor driving the wire

it indi-

cates that the memory timing is all right and the timing problem must be solved before further troubleshooting

can take place on the memory. If

ROM as though you were changing

refer to the PDP-14 User's Manual.

check the processor timing as described in Paragraph 4.4.4.
If the

ROM Selection board. The wire for the defective address is open or shorted to ground. Carefully

STROBE 1 to STROBE 8

refer to Paragraph 4.4.6.

The three least significant bits of the address contained in PCI select which strobe hne on the G923 board is
4.7.2.2

No Memory Output and the Processor Continues to Run - A number of faults can cause this condition.

First, the strobe that loads the buffer on the G923 Sense Amphfier board must be checked.

rated on the G924

4-10

STROBE is gene-

ROM Selection Board and connects to the G923 Sense Amphfier at pin BVl

This signal

asserted.

PCI

bits 9-1 1 , are decoded to one of eight hnes by E34.

E32 and E33 then AND the output with the

memory strobe from G924 to form STROBE 1-8. A failure anywhere in the strobe system will cause one word
in every eight to fail.

side of the logic.

Current Switches

4.7.7

Care should be exercised when probing the logic to prevent shorting between pins. Shorting of

signal pins to power supply pins can result in damaged components.

PCI

bits 6, 7, and 8, are decoded by El

Within modules, unused gate inputs are held

(Drawing G924-0-1) to one of eight lines. Each of these eight Unes
at +3V.

then drives a current-switch transistor which grounds the emitters of sixteen other transistors. If one of the
current switches is not functioning properly, a total of 1 28 words from the memory will fail in groups of eight.

WARNING

The current switches are Q 133 to Q 140 on Drawing G924-0-1.

Standard safety practices should be observed when working
with energized equipment. Remember that the controller convenience outlet is energized even when the PDP-14 is off.

Observing the collector of each of the current-switch transistors will indicate whether or not that line is working
properly.

Matrix-Base Driver Transistors

4.7.8

4.8.2

Bits 3, 4, and 5, of PCI are decoded by E5 (Drawing G924-0-1 ) to one of eight lines.
drives two gates.

One of the two gates is enabled by PCI

bit 2.

Each of these eight lines

The output of the selected gate drives the base

Module (Circuit) Troubleshooting

Schematic diagrams of each module are supplied with the PDP-14 and should be referenced for detailed circuit
information. Copies of the schematic diagrams are contained in Appendix B of this maintenance manual.

of eight transistors. The matrix transistor is fully selected when the appropriate current switch is enabled by PCI
Visually inspect the module on both the component side and the printed-wiring side to check for overheated or

bits 6—8, and the base is enabled by PCI, bits 2—5.

broken components, etc.

PCI

bit 2, selects one-half of a Read-Only

confirm a fault condition,

use the multimeter to measure resistance.

One-Half Memory Select

4.7.9

If this inspection fails to reveal any signs of trouble or fails to

Memory stack. If this line is low, it selects the lower half of the ROM

CAUTION

A failure in this line (it is held high or low) will not permit the
system to access one-half of each ROM. The failure could be in PCI the backplane wiring, or on the G924 ROM

Do not use the lowest or highest resistance ranges of the

Selection board.

range is suggested. Failure to heed this warning may result

and if high, it selects the .upper half of the ROM.

multimeter when checking semiconductor devices. The XIO

in damage to components.

4.7.10
Bits

Field Select

and 1 of PCI are decoded on the M742 module to one of four lines. Each of these four lines connect to 1

of ROM. PCI, therefore, selects the appropriate ROM bank via these lines.

A failure in PCI would cause the

A failure on the M742 module would not permit a
ROM to be selected or to be selected at all times. If a ROM bank is not selected, system timing fails and if
system to select the same 1 K of memory more than once.

selected all the time, it will cause an inclusive-OR of the selected memory and the defective one.

Measure the forward and reverse resistance of diodes. Diodes should measure approximately 20 ohms forward

and more than 1000 ohms reverse. (Front-to-back ratio should always be greater than 10 to 1 .)

If readings in

each direction are the same and no parallel circuit paths exist, replace the diode.

Measure in both directions the emitter-collector, collector-base, and emitter-base resistances of transistors. Short
circuits between collector and emitter or an open circuit in the base-emitter path cause most failures.

4.8

transistor indicates an open circuit in both directions between collector and emitter.

TROUBLESHOOTING AND REPAIR TECHNIQUES

A good

Normally 50 to 1 00 ohms

exist between the emitter and the base, or between the collector and the base in the forward direction, and an

4.8.1

Logic Troubleshooting

open circuit condition exists in the reverse direction. To determine forward and reverse directions, consider a

Logic troubleshooting in the PDP-14 is best accomplished using the technique of "reverse signal tracing". That is,

when a malfunction has been isolated to a section of logic, dupUcate that type of failure using a small program or
a scope loop option in a diagnostic MAINDEC. Then, by comparing the logic drawings with the machine status,

and tracing the faulty signal back to the faihng gate, that portion of logic which is causing the failure becomes

transistor as two diodes connected back-to-back.

In this analogy, PNP transistors would have cathodes connected

together to form the base, and both the emitter and collector would assume the function of an anode. In NPN
transistors, the base would be a common-anode connection and both the emitter and collector would be the

cathode.

evident.

Multimeter polarity must be checked before measuring resistance because many meters apply a positive voltage

NOTE

to the common lead when in the resistance mode.

An unconnected input to an M-Series gate, if not tied to a
terminator, floats at approximately +2.0V.

Since integrated circuits contain complex circuits with only the input, output, and power terminals available,
static multimeter testing is limited to continuity checks for shorts between terminals.

Before attempting to troubleshoot the logic, ensure that proper and calibrated test equipment is available. Always
is

caMbrate the vertical preamplifier and probes of the oscilloscope before using them.

Make certain that the

Integrated circuit checking

best done under dynamic conditions and using a module extender to make terminals readily accessible. Figure

4-12 illustrates the technique that is used for locating integrated circuits on a circuit card. Note that integrated
oscilloscope has a good ac ground, and keep the dc ground from the probe as short as possible.

circuits are numbered starting at the contact end of the board in the upper-right comer; the numbers increase

When a row is completed, the next integrated circuit is located in the next row at the contact

Use the oscilloscope to trace signal flow through the suspected logic element. Oscilloscope sweep can be synchro-

toward the handle.

nized by control pulses or by level transitions which are available at individual module terminals on the wiring

end of the board (Figure 4-1 2). The pins on each integrated circuit are located as shown in Figure 4-13.

4-11

Repairs and Replacements

4.8.3

Integrated circuits may be easily removed by using a solder
puller to remove all excessive solder from contacts.

NOTE

Then, by

straightening the leads, lift the integrated circuit from its terminal

DEC recommends replacing defective modules with

points. If it is not desirable to save the defective integrated circuit

modules of known good quality on a one-for-one basis
and returning the defective module to a DEC field

for test purposes, then the terminals may be cut at the body and

office for subsequent repair and/or replacement. If

orient the new integrated circuit in the same position as the one

however, for expediency, field repairs must be performed, it is imperative to take the following pre-

removed.

each terminal removed from the board individually. Be sure to

ULJTJLJLJTJLr
1

When soldering semiconductor devices (transistors, diodes, or

7
12-0134

CAUTION

cautions.

rectifiers, any of which

n n n n n n n

Never attempt to remove solder from terminal points
by heating and rapping modules against another sur-

Figure 4-13 Integrated Circuit

face. This practice usually results in module or com-

Pin Locations — Top View

ponent damage. Always remove solder with a solder-

may be damaged easily by heat, physical

sucking tool.

shock, or excessive electrical current), take the following special

When removing any part of the equipment for repair and replacement, ensure that all leads or wires which are

precautions:

unsoldered, or otherwise disconnected, are legibly tagged or marked for identification with their respective termi-

Use a heat sink, such as a pair of pliers, to grip the

—o

nals.

lead of the component.

Replace defective components with parts of equal or better quality and tolerance.

In all soldering and unsoldering operations involving the repair and replacement of parts, avoid placing excessive

solder or flux on adjacent parts or service lines.
b.

Use a 6V iron with an isolation transformer. Use the
smallest iron adequate for the work.

Use of an iron

without an isolation transformer may result in ex-

When the repair has been completed, remove all excess flux by

washing junctions with a solvent such as trichlorethylene. Be very careful not to expose painted or plastic surfaces
E4

to this solvent.

_r-

4.8.4

Validation Tests

cessive voltages present at the iron tip.

Figure 4-12 Integrated Circuit Location
c.

4-12

Always return repaired modules to the location from which they were taken.

If a defective module is replaced by

Perform the soldering operation in the shortest poss-

a new one during a repair period, tag the defective module, noting the location it was taken from and the nature

ible time to prevent damage to the component and

of the failure.

delamination of the module-etched wiring.

whether or not the repairs have corrected the problem.

When repairs are complete, install the repaired module in its original location and determine

APPENDIX A
PDP-14 SIGNAL GLOSSARY

Module

Soittce

Signal

AC 00-11 L

Signal

Description

Access Pin

M745

AB18

Source

Description

Reference

Source

Module

Logic

D-BS-DA14-L-2

Output Register of PDP-14 to accumulator

D-BS-DAl 4-1-2

(AC) of computer.

DECREMENT ENABLE L

Source

Access Pin

M740

AB24AP1

D-BS-PDP-14-0-3
(Sht 1)

Decoder output signifying bits 4 and 5 of an
instruction are a logical
respectively.

ADD8H
ADD4H
ADD2H

M743

ADDl H
BUS 00-11 L

CD24CV2
CD24CT2
CD24CR2
CD24CN2

M746

D-BS-PDP-14-0-5
(Sht 1)

Binary-weighted address lines for I, 0, or

signal can decrement PCI or the Spare

A Box circuit selection. Derived from

IR08-11.

(EEM + LEM) H
D-BS-PDP-14-O-t

PDP-14 internal transfer bus.

M740

AB24AK1

D-BS-PDP-14-0-3

Decoder output denoting an Enter External

(Sht 1)

Mode (EEM) or Leave External Mode (LEM)

Bit 00 is MSB.

instruction is in the IR.

This bus is on a wired-OR type that is ground

BUS 00-1 1 H

END CYCLE L

asserted for a logical 0.

M741

AB23AF1

CLEAR I/O

M743

CD24a2

D-BS-PDP-14-0-5

System reset signal for clearing all output

(Sht 2)

addresses. Derived from an INITIALIZE

D-BS-PDP-14-0-3

100-ns negative pulse derived from T pulses.

(Shtl)

Pulse is generated at the end of TS2 if a I/O

END CYCLE H

cycle is not in progress. For an I/O cycle,
this pulse occurs concurrently with the I/O

input or from decoding of a CLR instruction.

CLRMBH

M742

AB22BF2

D-BS-PDP-1 4-0-3

CLEAR MEMORY BUFFER. This signal,

(Sht 2)

derived from INITIALIZE or CLR 1 MB,
resets the

STROBE pulse trailing edge.

EN MEMOIR

M742

AB22BJ2

BS-PDP-14-0-3
(Sht 2)

CLR 1 MB L

M741

AB23AB1

M742

02 H

MB Register at the start of a

03 H

memory access.

CLRPCl H

and a logical 1,

The DECREMENT ENABLE

04H

AB22BT2
AB22BV2
AB22BU2
AB22AS1

D-BS-PDP-14-0-3
(Sht 2)

01 counts denoting the memory bank selected
for the current instruction;

EN MEM 01

selects the first IK of memory, 02 the second

IK, etc.

CLEAR PROGRAM COUNTER 1. This
signal, derived from INITIALIZE, resets PCI

ENABLE MEMORY. Decoded PCI 00 and

EN LOOP

G923

DC2

D-BS-PDP-14-0-3

Enable Loop.

When G923 module is removed

D-BS-PDP-14-0-3

CLEAR 1 MEMORY BUFFER. 100-ns

from the ROM, this signal enables a control-

(Sht 1)

pulse that is generated for each memory

ler timing test loop that bypasses

access.

the

It is

timing.

ORed with INITIALIZE to clear

ROM

With G923 module installed, this

signal is a ground level and inhibits the timing

MB Register.

loop.

CONTINUE

AB22AD2

D-BS-PDP-14-0-3
(Sht 2)

Ground level input from CONTINUE switch
that starts the processor timing.

ERSET

M743

CD24CF2

D-BS-PDP-14-0-5
(Sht 2)

CONTROLS ENABLE L

M742

AB22AE2

D-BS-PDP-14-0-3
(Sht 2)

Enable reset signal for the following Output

Boxes and addresses:

The RUN flip-flop controls this signal. With
the

RUN flip-flop reset (controller stopped),

this signal is at ground level.

It is provided to

the START and CONTINUE controls to

enable the respective function.

Box Address (Octal)

200-217

0-17
40-57

C
E

240-257

100-117

140-157

N
R

300-317
340-357

A-1

Module

Source

Access Pin

M743

CD24CE2

Module

Logic
Signal

Description

Signal

Reference

ERSET

D-BS-PDP- 14-0-5

Enable reset signal for the following Output

M743

CD24CH2

Logic
I

D-BS-PDP-14-0-5
(Sht 2)

EXT MODE (1)H

Source

Access Pin

M745

AB18BN1

D-BS-DA14-L-2

Flip-flop output denoting the external com-

D-BS-DA14-I-2

puter is providing controller instruction.
Flip-flop is set by an Enter External Mode
(EEM) instruction (0600g) and is reset by a

Box Address (Octal)

20-37

220-237

60-77

260-277

120-137

320-337

160-177

360-376

Enable set signal for the following Output

Boxes and addresses:

Description

Reference

Boxes and addresses:

Box Address (Octal)

Source
I

(Sht2)

E SET

Leave External Mode (LEM) instruction

(0400g) or an initialize operation.

EXT PCI CLEAR L
FETCH (1)H
EXECUTE (0) H

Not used.

M741

AB23AJ1

D-BS-PDP-14-0-3

AB23AH1

(Sht 1)

AB24BP2

D-BS-PDP-14-0-3

100-ns positive pulse denoting IR contains a

(Sht 1)

HALT instruction (0007g). This pulse sets

Output of FETCH/EXECUTE flip-flop denoting the current cycle.

Box Address (Octal)

E SET 1 H

Box Address (Octal)

0-17

200-217

C
E

40-57

240-257

100-117

140-157

N
R

EXECUTE (0) L

HALTL

M740

300-317

the STOP flip-flop to terminate operation at

340-357

the end of the current cycle.

M743

CD24CC1

D-BS-PDP-14-0-5
(Sht 2)

Enable set signal for the following Output

Boxes and addresses:

INCREMENT ENABLE H

M740

AB24AN1

D-BS-PDP-14-0-3

Decoder output signifying that bits 4 and 5

(Sht 1)

of an instruction are both logical Is. The

Box Address (Octal)

INCREMENT ENABLE signal can increment

PCI or the Spare Register.

20-37

220-237

60-77

260-277

INITIALIZE H

120-137

320-337

INITIAUZE L

360-376

160-177

M742

AB22BH1
AB22BK2

D-BS-PDP-14-0-3

System reset lines; active during power up,

(Sht 2)

power down, or whenever a timing failure is
detected.

EXECUTE (1)H
FETCH (0)H

M741

AB23AE1
AB23BP2

D-BS-PDP- 14-0-3
(Sht 1)

Output of FETCH/EXECUTE flip-flop de-

INOH

M743

CD24DP1

D-BS-PDP-14-0-5

noting current cycle.
(Sht 1)

EXT DONE L

M745

AB18BF1

D-BS-DA14-L.2

Pulse denoting the current lOT instruction

D-BS-DA14-I-2

is complete.

TYD output word is derived from this signal.
INO H is positive-asserted if the input or out-

Derived from a LDE (6164 g)

or GNI (6165g) when in the external mode

or from a 100-ns EXT GO pulse for a single

This signal denotes the state of the input or

output being tested. Bit 01 of a TXD or

put is off.

INT RQST BUS L

M745

AB18AM2

D-BS-DA14-L-2

Computer INTERRUPT REQUEST bus from

D-BS-DA14-I-2

peripheral devices.

D-BS-DA14-D2

Output of INT SYNC flip-flop that prevents

interrupt instruction.

EXT FLAG (1)L

M745

AB18BH2

D-BS-DA14-L-2

Flip-flop output denoting a GNI instruction

D-BS-DAl 4-1-2

has been completed.

INT SYNC (0) H

M745

AB18BL2

D-BS-DA14-I-2

EXT GO H

M741

AB23AD1

the incrementing of PCI if an interrupt oper-

D-BS-PDP- 14-0-3

EXTERNAL GO. 100-ns positive pulse gene

ation is in process (controller is performing a

(Sht 1)

rated for interrupt or external mode opera-

GNI).

tion. This pulse is comparable to

for

MEM GO

I/O CYCLE (1)H

ROM usage.

M741

AB23BU2

D-BS-PDP-14-0-3

Output of I/O CYCLE flip-flop denoting an
I/O instruction is being executed (15—1 8 /us).

(EXT MODE ® INT) L

M745

AB18BJ2

D-BS-DA14-I^2

EXCLUSIVE OR of external mode with

D-BS-DA14-I-2

Interrupt Sync. Signal denotes the external

mode has been selected or that a Generate
Interrupt instruction is being executed.

A-2

I/O DONE H

M741

AB23BS2

I/O STROBE L

M741

AB23BR1

Not used.
D-BS-PDP-14-0-3
(Sht 1)

6.5-Ais negative pulse that strobes

SYN and

SYF levels to set an output on or off.

Module

Source

Module

Source

Logic

Logic
Signal

Signal

Description

IREL

Source

Access Pin

M742

AB22BE1

D-BS-PDP-14-0-3

C-CS-M742-0-1

IR ENABLE L

INSTRUCTION REGISTER ENABLE. A
Test and Display instruction (TXD or TYD)
generates this signal.

IRE in turn, generates

Description

Reference

LD-SPAREL

Source

Access Pin

M740

AB24BM1

D-BS-PDP-14-0-3
(Sht 1)

MEM DONE H

M741

AB23AB2

the SOR-INPUT gating strobe to transfer the

D-BS-PDP-14-0-3
(Sht 1)

IR contents to BUS 00-1 1 for transfer to
the Output Register.

D-BS-PDP-14-0-3

MEM DONE loads IR and initiates TSl.
MEM DONE can be generated from a MEM

Not
ilovU.
llUl nspH

GO when the G923 module is removed from
the ROM. This feature bypasses ROM timing.

IR00-11(1)H

M746

CD23

D-BS-PDP-14-0-4

Instruction Register bits

(JFN + JFF)L

M740

AB24AH1

D-BS-PDP-14-0-3

Decoder output signifying a Jump If On

through 1 1

MEM DONE L

G924

BLl

D-BS-PDP-14-0-3
(Sht 1)

(JFN) or Off (JFF) instruction is in the IR

JF-0K(1)H
JF-OK(0)H

AB23AV2
AB23AU2

D-BS-PDP-14-0-3

Flip-flop output denoting a jump is required.

When set, causes a program jump to the loca-

MB Register.

MEM GO H

M741

AB23AN1

D-BS-PDP-14-0-3

(Shtl)

tion specified by IR 04—1 1 ; i.e., it causes

IR 04-1 1 to be loaded into PCI to address

M740

AB24AM2

D-BS-PDP-14-0-3

Decoder output signifying an unconditional

(Sht 1)

Jump (JMP) or a conditional Jump to Sub-

complete.

DUT ENABLE L

M742

AB22BJ1

D-BS-PDP-14-0-3

OUTPUT ENABLE. This line enables the

(Sht 2)

Output Register to be loaded through the

routine (JMS) instruction (4000g) is active.

K OUT ENABLE H

M742

AB22BP1

D-BS-PDP-14-0-5

Set and reset signal to M743.

LDEQIH

G782

A32AE2
A32AH2
D32DH2
D32DE2

D-BS-PDP-14-0-5

LOAD EQUALIZER - These Unes provide

AB18BP1

D-BS-DA14-L-2

LD EQ 2 H

IX)EQ3H

LDEQ4H
LD INPUT L

M745

generation of an LD-OUT L pulse during

TXD TYD.
-f

OUTPUT FLAG (1)L

M745

AB18BH1

filter time constant equalization for I, 0, or

A Boxes as G782 modules on BC14A cables

MEMORY GO. Nominal 100-ns positive
pulse that starts a ROM cycle for instruction
access. The ROM responds with a MEM
DONE pulse when the memory cycle is

the next memory access.

(JMP + JMS)H

MEMORY DONE L. ISO-ns negative pulse
signifying the ROM has retrieved an instruction and the instruction is available in the

(5000g).

M741

ROM MEM DONE or

EXT DONE input during normal operation.

(Sht 1)

MEMORY DONE H. 100-ns positive pulse
denoting the ROM or computer has completed
the trailing edge of a

output format.)

M741

an instruction retrieval. Pulse is derived from

BUS 00-02 is ORed

with output of M742. (See TXD or TYD

IRSYNC(1)H

Destination register load strobe for Spare

PAUSE (1)H

M741

AB23BT2

are added or deleted.

D-BS-DA14-L-2

Denotes the PDP-14 has information in the

D-BS-DA14-I-2

Output Register for transfer to the computer.

D-BS-PDP-14-0-3
(Sht 1)

A nominal 650-ns pulse that denotes a ROM
access is in progress.

The leading edge of

PAUSE initiates a MEM GO to begin an

Load Input Register pulse.

access. Pause is terminated by the trailing

D-BS-DA14-I-2

edge of MEM DONE.

LD-IRL

M740

AB24BL1

D-BS-PDP-14-0-3
(Sht 1)

Destination register load strobe for IR
(trailing ec^e jam-transfer).

PCI CARRY

M747

D19A1

D-BS-PDP-14-0^
(Sht 2)

LD-MBL

M740

AB24BJ1

D-BS-PDP-14-0-3

Destination register load strobe for Memory

(Sht 1)

Buffer Register (trailing edge jam-transfer).

PCI 00-11 (1)H

M747

CD19

D-BS-PDP-14-0-4

Carry output from low-order PCI stages

(06-1 1) to next stage (05) of PCI

OutputofProgramCounter 1 (PCI).

Bit

00 is MSB.

LD-OUTL

M740

AB24BV1

D-BS-PDP-14-0-3
(Sht 1)

Destination register load strobe for Output
Register (trailing edge jam-transfer).

PC2 00-11(1)H

M746

CD21

D-BS-PDP- 14-0-2

Output of Program Counter 2 (PC2). Bit 00
is

LD-PCl L

M740

AB24BN2

D-BS-PDP-14-0-3
(Sht 1)

(trailing edge jam-transfer).

POWER SENSE

+5V
Supply

LD-PC2L

M740

AB24BP1

D-BS-PDP-14-0-3
(Sht 1)

MSB.

Destination register load strobe for PCI

AB22AA1

D-BS-PDP-14-0-3

-^5

V input for sensing a power-up condition.

(Sht 2)

Destination register load strobe from PC2
(trailing edge jam-transfer).

A-3

Module

Source

Access Pin

M743

CD24DA!

Logic
Signal

Description

Signal

Reference

PSl H

2H
3H

5H
6H
7H
8H

Source

Logic

Package select lines for I, O, and A Boxes and

START CYCLE H

Source

Access Pin

M741

AB23AT2

tem address of 0-37g, PS2 selects 40-77g,

edge of an END CYCLE pulse.

START EXT L

M742

AB22AJ2

D-BS-PDP-14-0-3
(Sht 2)

AB22AH2

M742

AB22BU1

M740

AB24AN2

M740

AB24AJ1

SKIP-0K(1)H

D-BS-PDP-14-0-3

Output of RUN flip-flop signifying the con-

(Sht 2)

troller is operating; i.e., it is not in a power-

START L

M742

AB22AM2

D-BS-PDP-14-0-3
(Sht 2)

M745

M741

AB18AK2

This signal generates INITIALIZE during
a power-up or power-down sequence.

timing.

SWITCH ON L

D-BS-PDP-14-0-3

Decoder output signifying a Skip If Equal

(Shtl)

(SKE) or Skip If Zero (SKZ) instruction is

M742

AB22AN2

D-BS-PDP-14-0-3

This signal is generated for a power-up se-

(Sht 2)

quence, manual START and CONTINUE.

For a power-up sequence or CONTINUE,
this signal only tri^ers the

Decoder output denoting a Skip If Equal

pulses to begin a processor cycle. For a

(Shtl)

(SKE) instruction is in the IR. Output

START operation, the signal causes an

strobes the comparison between PC2 and a

INITIALIZE pulse and then starts processor

source register. Diagnostic instruction.

timing.

D-BS-DAl 4-1^2

When low, causes the computer to skip a

D-BS-DAl 4-1-2

location.

AB23AH2

D-BS-PDP-14-0-3

SKIP flip-flop output that causes the next

AB23AJ2

(Shtl)

memory location to be skipped. Flip-flop

contents equals

SOR-IR H

M740

AB24BD1

M740
M740

AB24AS2
AB24AT2

M740

AB24AC1

D-BS-PDP-14-0-3

Decoder output denoting a Set Output On

(Sht 1)

(SYN) or Off (SYF) instruction is in the IR

T ENABLE L

M742

AB22BH2

TEST FLOP (1)H
TEST FLOP (0)H

M741

AB23BD2
AB23BE2

D-BS-PDP-14-0-3

(Shtl)

S0R-PC1(4-11)H
S0R-PC2 H

M740
M740
M740

M740

contents of Input Register to BUS 00-1 1

with input on, TXF with input off, etc.).

D-BS-PDP-14-0-3

Source register gating signal that transfers

Flip-flop is reset by J

D-BS-PDP-14-0-3
(Sht 1)

D-BS-PDP-14-0-3

AB24AU1

D-BS-PDP-14-0-3

(Shtl)

D-BS-PDP-14-0-3

(Shtl)

the IR contents to BUS 00-1 1

TEST TRUE H

M743

CD24DN1

Denotes the input or output tested was in the

(Sht 1)

state (on or ofO defined by the test instruc-

tion (TXN, TXF,

the contents o&the Memory Buffer to

Source register gating signals that transfer

M741 module.

T PULSE

M741

AB23BH1

the contents of the spare register to

D-BS-PDP-14-0-3
(Sht 1)

[TSl(l)- EXECUTE (1)] H

M741

AB23AL2

the contents of PC2 to BUS 00-1 1

Source register gating signal that transfers

TYN or TYF). This signal,

when asserted, sets the TEST FLOP in the

PCI contents to BUS 00-1 1
Source register gating signal that transfers

FN and IFF instructions.

D-BS-PDP-14-0-S

Source register gating signals that transfer

BUS 00-11.

A-4

TXN

(Shtl)

AB24AU2
AB24AV2

AB24BC1

the last input or output test. Flip-flop is set
if condition tested for is true (e.g., for

(Sht 1)

SOR-SPARE H

TEST FLOP. Output denoting the result of

Source register gating signal that transfers

BUS 00-11.
SOR-PCl (0-3) H

Not used.

(Sht 2)

PC2

for an SKZ instruction.

D-BS-PDP-14-0-3

(Shtl)

SOR-MB (0-3) H
S0R-MB(4-11)H

(SYN + SYF)L

(3000g).

for an SKE instruction or if source register

AB24AV1

START EXT

D-BS-PDP-14-0-3

is set if source register contents equals

M740

Ground level input from START switch that
begins controller operation. This signal
initializes the controller, then starts processor

D-PDP-14-0-3

D-CS-M740-0-1

SKIP-OK(0)H

SOR INPUT H

STOP flip-

RUN flip-flop and begin

processor timing.

M742

SKE ENABLE L

SKIP BUS L

200-ns pulse generated at the end of an
initialize condition to clear the

flop, set the

in the IR. Diagnostic instruction.

SKEL

200-ns positive pulse that starts processor
timing; this pulse is generated 1 50 ns after an
initialize operation or following the trailing

etc.

(Sht 2)

(SKE + SKZ) H

D-BS-PDP-14-0-3
(Sht 1)

down or an initialize state.

SHUT DOWN L

Description

Reference

BF14-M Storage Modules. PSl selects a sys-

DL2
DN2
DR2
DV2
DU2
DT2

4 H

RUN(1)H

D-BS-PDP-14-0-5

DJ2

Module

TS1(1)H

M741

AB23BM2

100-ns positive pulse generated at the end of

TS1,TS2 and an I/O cycle.

D-BS-DA14-L-2

500-ns pulse derived from TSl and EXECUTE

D-BS-DAl 4-1-2

states.

D-BS-PDP-14-0-3
(Sht 1)

500-ns pulse that is active for the first time
state (TSl) in a cycle.

Module

Source

Logic
Signal

TS2(I)H

Access Pin

M741

AB23BL2

D-BS-PDP-14-0-3

(Shtl)

TXDL

M740

AB24AK2

D^BS-PDP-14-0-3
(Sht 1)

(TXD + TYD) L

M740

AB24AF2

D-BS-PDP-14-0-3
(Sht 1)

Source

Signal

Reference

Source

Module

Logic
Description

Description

Reference

500-ns pulse that is active for the second

XSRET 1 H

Source

Access Pin

Box

CD24DD2

time state (TS2) of a cycle.

D-BS-PDP-14-0-5
(Sht 1)

M740

AB24AA1

+ TYN+TYF

D-BS-PDP-14-0-3
(Sht 1)

Box Address (Octal)

20-37

Decoder output denoting a Test Input and

60-77

260-277

Display (TXD) or Test Output and Display

120-137

320-337

160-177

G
H

Decoder output signifying a Test Input and

YSRET

IR.

OBox

CD24CB2

l>BS-PDP-14-0-5
(Sht 1)

+ TXD + TYD) H

AB24AB1

M740

AB24AL2

0-17

On (TXN) or Off (TXF) instruction is in the

C
E

40-57

240-257

100-117

300-317

140-157

N
R

D-BS-PDP-14-0-3

Decoder output signifying a Test Output and

YSRET 1 H

D-BS-PDP-14-0-3

Decoder output denoting a Test Output for

(Sht 1)

On (TYN) or Off (TYF) instruction is in the
IR(lOOOg).

XSRETOH

Box

CD24CD2

D-BS-PDP-14-0-5
(Sht 1)

200-217

340-357

Display (TYD) instruction is in the IR

OBox

CD24DB2

D-BS-PDP-14-0-5
(Sht 1)

AB24AE1

Box Address (Octal)

(Shtl)

(74OO3).

M740

Address (Octal)

Decoder output denoting a Test Input for

(Sht 1)

(TYN + TYN)L

Boxes and addresses:

D-BS-PDP-14-0-3

IR(2000g).

TYDL

360-377

Signal return line for the following Output

Box

M740

220-237

Decoder output denoting an I/O instruction
is in the

+ SYN + SYF

(TXN + TXF) L

Boxes and addresses:

Display instruction is in the IR (7000g).

(TYD) instruction is in the IR (7000g).

(TXN+TXF

Signal return line for the following Input

Boxes and addresses:

Box Address (Octal)

0-17

200-217

240-257

40-57
100-117
140-157

G
H

300-317

Signal return line for the following Output

Boxes and system addresses:

Box Address (Octal)

20-37

60-77

260-277

120-137

320-337

160-177

360-376

220-237

340-357

A-5

APPENDIX B

REFERENCE DRAWINGS
OVERALL SYSTEM
Module Utilization

Page(s)

D-MU-PDP 14-0-1

B-2, B-3

MODULES

Page(s)

G782

Cable Connector

B-32
B-33

Major Registers

D-BS-PDP 14-0-4

B-8, B-9

G924

Interface Box Control

D-BS-PDPl 4-0-5

B-10,B-11

K022

ROM Braid Board
ROM Sense Amplifier
ROM Selection & Timing
A Box Storage Module

Flow Diagram

D-FD-PDP 14-0-6

B-12

K135

Inverters

B-39

K136
K161
K161

Inverters

B-40

Binary-to-Octal Decoder, Rev. B

B-41

Binary-to-Octal Decoder, Rev. D

B-42, B-43

K207

Flip-Flop

B-44

K272
K274
K302
K564
K578
K579

Retentive Memory

B-45

Dual Retentive Memory

B-46

Timer

B-47

DC Input Converter
AC Input Converter
AC Input Converter
Isolated AC Switch
Isolated AC Switch
DC Driver

B-48, B-49

Compare Control

D-BS-PDP 14-0-2

B-5

PDP-14 Control

D-BS-PDPl 4-0-3

B-6, B-7

G922
G923

INPUT (I) BOXES
BX14-DA Unit Assembly
BX14-DA AC Input Box
BX14-DD DC Input Box

D-UA-BX14-DA-0
D-BS-BX14-DA-1
D-BS-BX14-DD-1

B-13

B-14
B-15

OUTPUT (O) BOXES
BY14-DA Unit Assembly
BY14-DA AC Output Box
BY14-DD DC Output Box

D-UA-BY14-DA-0

B-17

K614

D-BS-BY14-DA-1

B-18

K616

D-BS-BY14-DD-1

B-19

K657
Ml 06

ACCESSORY (A) BOX

BAH Unit Assembly
BAH Accessory Box

D-UA-BA14-0-0

B-20

D-BS-BA 14-0-01

B-21

COMPUTER INTERFACE (DA14)
PDP-8/I Interface

D-BS-DAl 4-1-2

B-22

PDP-8/L Interface

D-BS-DA14-L-2

B-23

Registers

D-BS-DA14-L-3

B-24, B-25

D^NLY MEMORY (MRU)

B-34, B-35
B-36, B-37

B-38

B-50,B-51
B-53
B-54, B-55

B-56, B-57
B-58, B-59

Memory Port

B-60

M232
M249
M740
M7400

Addressable Storage Module

B-61

Memory Port

B-62, B-63

Instruction Decoder

B-64, B-65

Instruction Decoder

B-66, B-67

M741

Major States & Timing

B-68, B-69

M742
M743
M744
M745
M7450
M746
M747
M921

Switch & Power Control

B-70, B-71

I/O Interface

B-72, B-73

Comparator

B-74, B-75

Computer Interface

B-76, B-77

Computer Interface

B-78, B-79

Bus Register

B-80

Incrementing Bus Register

B-81

Device Selector

B-82

Power Supply

B-83

Unit Assembly

D-UA-MR 14-0-0

B-26, B-27

714

Block Schematic

D-BS-MRl 4-0-2

B-28-B-31

Power S upply Filter Circuit (D-CS-70063 14-0-1)

B-84

B-1

0-t7ldCld

•*M7450

,.,S824

-A^

G923

lEI

-A-£

jaii_

G322

ZKi

Gag?

582 4

ZKi

6823
J

S824
r

4,1

M74B /M74S" M749/M9e3
583

OUT

o»

OUT 09

ABLE

AC 00
TO

omi

IH42
z

AC OS

CONTMEM
04

AC 13

OUT
ROM

ROII

ROM

BRtlD

SEIECTION

SENSE

ROU

SEIECTION

BRAID
BOARD

tMPllFI^R

ROM

ROII

ROM

SEIECTION

SENSE
tUPLIflER

ROM

BRAID
BOARD,

SENSE
AMPLIFIER

RDM
SEIECTION

ROM

BRAID
BOARD

ROM

SKIP
BUS

SENSE
AMPIIEIER

A
MEMORY
(OPTIONAl ADDRESSES 4100-5777)
THIRD MRI4 UlSTAilEII

FOURTH KRH JNSTAIL D

;OPTIONAl ADDRESSES 2000-3777
SECOND MRI4 INSTAl ED

ENAB

BUS
01

BMB

BUS
00

INT

(OPTIONS ADDRESS 6DD9-7777

ROL

FIRST IIRI4 INSTAUED

ROST
BUS
OUTPUT

SKIP
BUS

IRE

INT

BUS

Ft AG

RQST
3US

CLR
MB

IZ£

CLEAR

DATA

BUS

EXT

2
NITIAL-

CIEAR
BUS

START
EXT

FLAG

M749 /Mg49

CLR

"TI5T

0»2 lOCABI,E

MBS

OUT
ENAB

BAC OD BAC 09

INITIAL 2t
I

PO»ER
CLEAR

TNTER
EN
MEM
01

BlOP

MEM
2

BlOP 4

HEM

24
TTW"

23
hiur
CIR
MB

SKIP
INSTRUCTION
OK (I) DECDDII G
SKIP

SOURCi

OK (0)
IP

EXEC-

UTE (I SYNC
START
JF-OK
I

AND

DESTIN^TTION

M>464

M7403

M7a05

DEVlCi:

57^2

G7B2

BRET

CODE

XSRET

SELECf^lON
XSREl

XSRET

PS 3

ADD

BMB3
TO

CONTROI

I
1

(3)

JF-OK
<l)

ADD

ADO

UTE (3 TEST
FLOP

{ADD 2

ADD 2

AOD

(I)

AOD 4

ADO 4

ADD 4

AOD 4

ADO

ADD

ADD 8

ADO

EXEC-

FETCH
(0)

HEM
GO
T

PULSE

TEST

FLOP
(0)
TS 2

G762

G7B2

ItiQ

FETCH
I/O

|ADD

XSRET

(I)

XSRET

STROBE
I/O

XSRET
i

XSJtET

XSRET

DONE
!

PS B
I/O

CYCLE

ADO

PS 6

PS 4

PS 2

ADD

AOD

ADD

AOD 2

AOD

ADD 2

AOD

ADD 4

AOD 4

ADD

ADD e

ADO

OPTIONS:

FIRST USED ON OPTION/ MODEL

PDP-14

A = MRI4 - READ ONLV MEMORV

EQUIPMENT

DO NOT SCALE DRAWING

BDSeQSD CORPORATION

UNLESS OTHERWISE SPECIFIED
DIMCNSION

m INCHES

TOLERANCES

O = 0AI4-I - COMPUTER INTERFACE

DECIMALS

10 POP 9

FBUCTIONS

ANGLES

- 1/64
= 0-30'
riNAL SURFACE QUALITY

= .OOS

D BREAK SHARP

- DA 14-1 - COMPUTER INIERFACE

TO POP 9

# = DC14-A- SERIAL LINE INTERFACE
Jf =

DLH -MAP-)4 HARDWARE

MODULE

^^?^^'bTT.
PROoi

IbATE

M.
NEXT HIGHER ASSY

A-ML-PDPI4-P
NONE

SCALE

OF
I

UTILIZATION

NUMBER

SKEJCODEI

"ST.

'
I

III

B-2

REV.

PDPI4-0-

DMU

F
I

l-0-l7ldCd

M746

PC2
BUS a

30
I

PC2

BUS D2

VEMORY

PC2 3 2

MEMORY

BUS 03
PC2 33
BUS 84
_PC2

a£

BUS as

PC235

JtjM-

JllM-

BU S J6
PCI

86
iUS 37

BUS

PC2 37

BUS 05

M743

_G712_

TEST
TRUE

CLE«R

ySRET

1/0
03

ESET
CLEAR

ADO

ADD

TS'IET

ESET

CLEAR

I/O

ERSET

ESET

CLEAR

ADD 4

ERSET

ADD

PS 4

ADO

ADD

ADD 2

ADD

ADD 4

ADO 4

AOO 4

ADD i

ADD 9

ADO 9

AOD

BUS

=CI

PCZM.

SLjJ

I/O

ERSET

ERSEl

PS 2

I/O
3

PS 9

CLEAR

I/O
3

SUS

YSRET

ESET

ESgT

32
G7B2
CABLE
YSRET

YSRET

31
CABLE

G7B2

HBIE

CABLE

'CI

PS 3

ADD 9

ADD
PS

ADD

AOO

ADD

ADO

ADD

AOD 2

AOD 4

ADD 4

AOO 4

ADD

AOD

ADD 9

TO
PS

-mr

S782
CABLE
'

;a bi.£

ySRET
ESET

XSRET
a

ESET

ERSET CLEAR

BUS 39

TFoT

ERSET

CLEAR

I/O

ERSET

CLEAR
I/O

I/O

ERSET

PS 4

CLEAR

I/O

ERSET

PS 5

PS 6

CLEAR

ADD
ADD 2
ADD 4
ADD 9

AOD

ADD

AOD

ADD 2
ADD 4

AOD 2

ADD

ADD 2

AOO 4

ADD 4

ADO 4

AOO 4

AOD 4

ADD 4

AOO 9

ADO 9

ADD

ADD 9

AOO 9

AOO

PS 9
I

BUS

CLEAR

I/O

CLEAR

ADD

AOO

FIRST USED ON OPTION/MODEL

PDP-14

DO NOT SCALE DRAWING
UNLESS OTHEFTWISE SPECIFIED
DIMENSION IN INCHES

EQUIPMENT

tATE

;-9-6
CHK'D.

DATE

SDIDDSD CORPORATION

TOLERANCES
DECIMALS

FRACTIO'^S

FINAL SURFACE QUALITY

ANGLES

MODULE

REMOVE BURRS AND BREAK SHJiRP

j-^L.jj.^

UTILIZATION

Ei^

NEXT HIGHER ASSY

A-ML-PDPI4-P
SCALE NONE

SIZE CODE

D MU

PDPI4-

REV.

B-3

THIS PAGE LEFT INTENTIONALLY BLANK

B-4

Z-'ef-bldOd ISaio|2

COMPARE H
M7-14

cDsa

CV2

b\/2

BUS QS0 H

BUS 0\ M

&US ^2H

BUS 553 H

CDa

CEe
BIT COO

pce (j)«(i)H

BIT5»I

PCS eidiH

Biras

PCS aari) h

CFS

CJS

cua

BUS 04 H

CN2

BUS 0S M

CR2

BIT®4
BIT

BUS0S H

BIT©S

BUS ©"7 H

BIT 07

BUS BS H

BIT OS

BUS C2iq H

BIT5)«»

CP2

•pca i?4 (iiH

PCa 05 (DM

DES

pca 9>s(i)H

DH2

•PCS fll7(l)H

•pca^BdiH

DPS

DSS
BIT 11
|CT2

PCS «i3(l)H

cse

DM a

BIT 1*

Busll H

CMS

BIT as

-pca

d H

(11

-pca i^niM

-PCS 11(11 H

iDT£

FIRST USEQ ONOPTtON/MOOEL

PDP14
UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

TOLERANCES
OCCUULS
FMCTUMS
= .005
1: 1/M

ANCLES

± 0^-

FINAL 5URflU:E QUAUTY

REMOVE B MtS AND BDEAK ShiErp
CORNERS
hIATERIAL

EQUIPMENT

DHN^

DATE

CHK-D/-

DATE

Sii^

DATE

COMPARE CONTROL

f^
Tf^ifi!^

CORPORATION

WEXT HIGHER ASSY
ft-ML-POPI4-j3

SiZElCODEl

SCALE

DBS PDPI4-0-2

SHEr

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)

B-5

?-0-t7ldadlSaa|2
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DU Ki E«iiipRiw>t CmmiMnn •ml •'VH n
l

EXT GO H

ABes

CL.RI
L

MEM
GOH

END CYCLE L
FETCH* l)H EXECUTEIBIH
ST APT
TPJLSEHlCYCLE H

TEST

TS201H PAUSEdlH

TSUIIM

JF-OK

FLOP(*)H FLOP(\>H

JF-OK
lllM

(CZIIH

I/O CYCLE. (OH

SKIPOKcaiH

OKIh H

Aja

ahs

SKIP-

FETtH(i2)- EXECUTED H

-I/O DONE H

I/O STROBE L

AT 2

-1-0-

Aua

MEMORY CONTROL

TSe

FETCH |EXECUTE|

.PAUSE

AMS AFS AEe

I/O CYCLE

CONTROL

TTMING

TEST FLOP
AND CONTROL

I/O
TIMING

MAJOR STATE AND TIMING STATE CONTROL

AVS

Boe

BE2

BSS

SMP-OK
I

-RUN (I) H

START
EXT L

ADS

INITIALIZE H

ENABLE U

(EXT MODE

EXT

+INTERRUPT)l. DONEL

INITIALIZE L

LOOPH

TEST
TRUE H

fTYM-tTYP") L

IRSlSdlH

(JFNt
JFF)L

COMPARE

(SK.E->

SK,Z)H

MEM

DONE L

C^xvi^~xi^) i_

(TXN +

TXF +
TYNt
TYF +
SYN*
SYF-t-

(TXN +
TXF)L

TXD +

(SKEt

TYDJH

SK.Z)H

* « S0R-1RIJ)-3H
SKE L

SOR-MB(4-ll)H

%* SOR-IR 4-im-;

SOR-PCKO-an

SOR-PC2 H

:SOR-MB©-3)H SOR-SPARE SOR-PCl{4-i!)H SOR-INPUT H
!

(TrN+
TrF)L

(SYN-f

(JFNi-

SYF)L JFF)L

AEl ABl ACl

(TXDf

(JIVlPt

TYD)L

JM3>H

JAH,

(EEM+

INCREMENT

LEM)H

AJiJa:

IR5>aWH

IROI(»H

YADI

«InhCtxd + tyd)l

LD
LD-PCI u LD PC2 L OUT L

«» MEM SO MEM H

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BJ2|BDi

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Ava

AUl

BJI

AVI

SOURCE REGISTER DECODER

AMI_ APS

IR553<nH

jATg ;bci

,Asa

OPERATE
DECODER

Ata

IR02(hH

SPARE

ENABLE H

INSTRUCTION DECODER

AOa

LD-IRL LD-MBL

-IRBSHIM

BB: A51 ARiIbwI 3Ei|BKI BHI _ _

FETCH

07(I1H

U)H

DESTINATION REGISTER DECODER

'^'^^M^^^^'i^^^^Z
jF-OK

SPE qPCJEL

BRa

BRl

BSI

IROSIllH

IRiadlH

IRIKDH

B82
*»MEM(iO H

IMT 5YMCi0)l-

* BAS(l^) H
TS2

EXECUTE JF-OK SKIP- MBE L PCIEL INE L
(II H
(II H
OK(B)H

5>6<11H 06(1) H (1)H
* SIGNALS ONLY USED WITH DV.I* OPTION
** SI6NAL ONLY CONNECTED ON MAtiHINBS

eusj

1SS2T3J

BNia

TPUL^EH OUTPUT

ENABLE L

KLD 14 Bus L

WIRED POR DLI4. + DCI4. OPTIONS
'

^95T USED ON OPTIOn/mODEL

PDPI 4

EQUIPMENT

DATE

UNLESS OTHERWISE SPECIFIED

CORPORATION

UNLESS OTHERWISE SPECIFIED
DIUENSKW in INCHES

'01' h>/'

TOLERANCES
FINAL SUNFUE QU*LITV

REMOVE BUHnS *HD BNE*H SM<B
CORNERS

'SSiXL,
DATE

PDP 14 CONTROL

iJI.^,^SXS
NEXT HIGHER ASSY

A-ML-PDPI4-P

NUMBER

SIZE CODE

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SELECTOR

Sl^ EN MEM 01 H
EN MEM 02 H

TXD+TYD ^El
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REGISTER igj^
CONTROL f^—= T ENABLE

EXECUTEC0)L^t^
CTXD+TYD) L-

-5^2 EN MEM 03 H

^^ EN MEM U4 H

ig^

I/O DONE hBS^I

„^^ ^^^g^^ ^

BUS 00

TEST FLOP (0) H

BUS

(5|

BUS 02 L

POWER
FAIL

DETECTOR

BR2,

SHUT DOWN H

rO
I

Q
Q.

M742
AB22

USED On OPTION

FLfiST

"°"^

PDPI4

.UNLESS OTHERWISE SPECIRED

UNLESS OTHERWISE SPECIFIED
OlMErtSKM IN INCHES

TOLERANCES
DECIMALS
?;

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NUMBER

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PDPI4-(5-3
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EQUIPMENT

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DATE

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MAJOR REGISTERS

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INSTRUCTION REGISTER
S

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SD SD

SD
LI

9
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MEMORY BUFFER
1

SD SD

CUR PCI H

SDSD SD

MBS MBS
as L

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MBS MBS
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MBS
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VI INCRE-

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i2l

<3l

PROGRAM COUNTER a

SD SD SD ~7SD SD

9i6 L

PCS

CARRY

PCI

0(l)H IICOH

0-?Cl)H

decrement l-D PCS L

PCIS
I

•

BUS

aSH

BUS

07 H

BUS

(SB H

IZI"1

BUS

I0H

BUS
I1M

FIPST USEC ON OPTION/MOOcL

P0PI4

EQUIPMENT

UNLESS OTHEHWtSE SPECfflED
2/^jz^tjf<jti^i

UNLESS OTHERWISE SPECIRED
ONIIMSMH IN llfCKES

TOLERAKCES
[ICC1MALS
HUCrrjm
± 1/M
X .OOS

AHOUS
± 0*30-

FIHAL SURFilCE WMUTT

RCUewt UWIS JIMO

MCW SUM

T^ rf^

CORPORATION
DATE

EH«-n

DATE

rm^

gg>.

(BITS 6-11)

MAJOR REGISTERS

KliJIGHCf) ASSY

A-HL-PDPl4-i&

mm
dIbS PDPI4-0-4

s»ttrr

2
I

B-9

9-i0-l7ldad

TNPOT
+ 5V X SRE T

H -

SRET 0HLD EG H LD EC? 2H-

IMPUT

INPUT
ADDRESS

ADDRESS

AO DRESS

ADDRESS

32-fc3

(2,4-95

9t-l27

I2S-I39

1685-191

'A2\

f^
82

C2
DS

1-2

E2
H2

INPOl

INPUT

ADDRESS

£2
h2

£2

ADDRESS
22A-255

C2
D2

ACC ei-i-

R8
Te

G7Si

&7S2

(;782

6782

G782

832

>43f

B3/

A30

PS IH

PS EH

PS3H

PS4M

ADC ct-i-

INPUT

192-223

B2.

C2
02

IMPOT

ADDRESS

Ra
re

&TOZ
B30

6762

G782
82»

PSSH

1^2

/^^9

PStH

PS7H

PSSH
TEST TRUE H
DNI
l/ffTCST

•"^74 3'
CO SI

CNia

-IR*3m M
-IN* M

W2 DL2 DN2 BR2 Dva D02 DT2

DAI

a 3 4
5 e 7
BINARY TO 8 UNC DECODER
I

cpa

(TXNtTXFt

lRffl4ll)H

DRjj

— INPUT TEST

OUTPUT TEST

ONTROU

CONTROU

>JiNPi

oEa

IReSIIIH IF<ee(l)H

OKe

DM a

iRseinH

iRpiniM

Dpa
TXD L

TVTKDoa

DH3

yi.
ID

sSii

CB2

DBS

IR»7fiH_YSRET
S5H

YSRET

Cos

a
Q
a

TYN+TYF +

TXDtTYD*
SYN+STF^H
(TXNtTXFli,

XSRET
q>H

XSRET
IH

(TYN + TYF) I.

F»ST USeOON OPTION/MODEL

PDPII

EQUIPMENT

DATE

UNLESS OTHERMSE SPECIFIED
(HMENSWH rN MCHES

HCMUU

TOURANCES
nUCTIOMS

MtfiLU

CORPORATION
-

INTERFACE BOX
CONTROL

(^.iZilJuJJg
uTY

y
^^iU/^

ftrlT-J-^?

N£XTm[Ch£R ASsr
A-ML- PDPi 4- P

NUMMR

StZEjCOOel

REV

DBS PDPi4-0-5
0F2

B-IO

'Si

i-ci

9-£?-'WdQd|Sa*[2
uaawnw
|3003i3zisl

OUTPUT
ADDRESS
0-P6

32-47

£)4-7S

IS-III

128-1*3

CL£*fl I/O

OUTPUT
ADDRESS
22^-«a"l

C2
1.

LD EQ 3H
S£T

11Z-SV7

I6»-175

AS
-t-5\

rsR£r0 H

OUTPUT OUTPUT
ADDRESS ADDRESS

OUTPUT OUTPUT OUTPUT OUTPUT
ADDRESS ADDRESS ADDRESS ADDRESS

K.a

SET <i H

PSIH

—
RS
ADD £ H —
ADO

PS5«-

PS3«~

PSZfr-

—

ADD 4 H
ADD e H

f\2

C32

|V2|

C2f

C3/

X/O STROBE L

BPI

CD 22

CSYM+SYF) I-

OUT

r<,

ENJAS^E

C2&

C27

C28

4782
025

PSSN-

PS7H-

PS6/*-

OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
OUTPUT
ADDRESS ADDRESS ADDRESS AODP.ESS /-DDRtSS ADDRESS ADDRESS
17C.-I1I
e©s-aa3
i+4-i?>q
6e-«i5 112-127
ife-31
4e-fe3

AS
f-SVfee

Eve

YSRE"

PS8H-

ADD

LDtO 4 H
E

SET

E2
F2
je

CLEAR ;/OLER SET

Ee
-

OUTPUT

ADDRESS
a4g-265

H -

PSI« -

ADD IH y sutTs »-

H -

-X SRET
Bl

ADO-^ H -

-YSRETfB H
-

X SB.ETO H

'"m743

ADD 8 H-

K.e

PS2H-f<

PS6H-

PS3H-

PS7H

PS7H-

•

LO f<» 3H -

ADD 2 H -

—
Ml

PS6H-

\CE2

Ice

CH2
ICH

ICFe

Ik
Q-

/4p\

PS5HD3

/Bp\ /4a\

/bdX

TC Nl

-INITIALIZE L

CLEAR ALL
OUTPUTS

OUTPUT

PS4/J-

SET- RESET CONTROU

PS3H

ADD 2W-

CM2

DHa r^

PSZHTS

Te
i»DO

PS IH

—

D32

&782

G782

D3/

030

6782
S>g2
D29

&782
025

gV2
028

e27

K COT EMABLE

+ 3V

ve
/«D0 e

CBI

CAI

iP.a3ioH

IRCJ7C0H
FIRST USED ON OPTON/MODEL

PDPI4
^JWy^ OTHERWISE SPEaFTED_

OtCmAiS

- .008

nUCTKMS
a:

l/«*

AHOUS
i OTff

FINM. SunfNrE QIWUTT

KMOK UmS W4C> BREAK VIMP
HATEfHN.

CORPORATION
DATE

CMMCrUiOM IN INCHCS

TOLEMNCES

EQUIPMENT

>^r>^ S

UNLESS omERWISc SPECIFIED

PKU-t»6,

INTERFACE BOX

CONTROL

'm.,L...^\p..^
NEXT HIGHER ASSY

A-MbPDPt4- P

NUMBER

SIZEICOOEI

DPS PDPI4-0^
asT.

C
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B-11

B-12

o-vaH7ixa|vn o
drawing and specifications, henein, are the
Of Digitil Equipnant Cofpocation ind shaJ) n
reproduced or capiecl or used in wtiola «- in part >£
Oasis lor the rraniXactuF* or »«l« of rtemi without

FOR DWG INDEX L\S\ WE.'v'J.Vi

SEEDtTW\_X

±
a

«^
i®3

(bHU^
r
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r
(J

i<
iO
"
(

^AODOLE «>\0^ S,WOWN

m
g<
33

2 REF

IRST USED ON OPTION MODEL

EQU PM ENT

UNLESS OTHERWISE SPECIFIED

CORPORATION

UNLESS OTHERWISE SPECIFIED
DIMENSKn IN INCHES
TOLEft\NCES
KCIUALS FRACTIONS
ANGLES

^ JJ05

± 1/64

t 0°30'

BOX ASSY,

nUL SURFACE QUALHY
REMOVE BUE«S AND BREAK SHARP

^e5

INPUT

MATERIAL

NUMBER

SIZE a)DE

5*^

lEX

-r—

-/-

RBT.

D iJABX54-DA-0
Klrjj

C
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DEC FCHM NQ.

B-13

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T>n ^a-** and iptotaMnm.

sao

I-

K57B

KS78
8

Kiae

Kl£t

^578

K.lfet

K578

<i
it'

m
IS

5AMPLE RETJRN 'I

SAMPLE RtTLRN'

FiUST USED On OPTiOr^MOoeL

PDP-14

EO U P M E N T
CORPORATI ON

UNLESS OTHERWISE SPECIFi£D

UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

TOLERANCES
DECIMALS

FIIACTtONS

- 005

- I'M

= 0*30-

INPUT
INTERFACE BOX

jr'i^/yyA^

Fm*L SURflCE QUALITY /
REMOVE BURRS AND BAEAK %nXaP

DATE

£.''t.
i£XT HIGHEP aSSv

A-ML-BXI4 DA
SCALE

j—

BXI4-PA-I

D BS!
DIST.

B-14

NUMBER

SIZE CODE]

i-aa-1
>»ixa

p^«j?

M%B uo-i-i*
Ml ^7-3^
CURKENT

USB

tABte

6777

KSit

K',/,^

KI3&

KIM

Kiei

^S^4

^5^4

FRONT

s^Lt Moies i,ze3

X
CD

/•

co'^/t^cr /^ssw/B^i -v«jjr. 9^/0 tj/v each

Z. TeRnwfic

o>=' CACj-i

fS6* »usT ee

COUHtCrSO TO CH/VS,IS GROUND /IT /I fiO/A/T
ccoic TO T//f ///reer^f SHdL
3. ne f/eeu^Tiuf toiminal of /tA/v »uo /tct- /jc
Poueg: souK.(s suPnyiNfr /uPcr coneefrr
TO

3AMP1-F RETURN *1

SAMPLE f>ErLRN''2

s kS(,4 /oas,T /K.SO ee Ti(t> to c»/iss/s

'-.-

CORPOWA-

[

D.C. INPUT

INTERFACE BOX
BXI4-DD-I
I

.
I

-n

B-15

TfflS PAGE LEFT INTENTIONALLY BLANK

B-16

I
I

-A3a

0-va-i7ua|vn|D| 2

I
I

aaawnw

«ty of Digital EquiptiMnt Corpontian ai
Feproduced or copied or iisad in whok
"

ago gzts I

I
I

NOTES:

basis for the miniActura or sBia cX

FOR DWG INDEX LIST REFER TO DWG
NO.

C-DI-BYI4-DA-3

SEE DETAIL A

JL
CM

2
ID

L A

_
10.44 REF

CVJ

>CD

33
A

DETAIL A
(MODULE SIDE SHOWN)

VIEW A-A
2 REF
FIRST USED ON OPTION|MOOE^j

PDP-14

EQUIPMENT

UNLESS OTHERWISE SPECIFIED

CORPORATION

UNLESS OfflEFWISE SPECIFIED
DIMENSION IN INCHES

TOLEFIANCES

IXCUtUS
iWlrCnONS
ANGLES
*: 1/6*
± 0*30±. JB5
FMAL SURFACE QUALHY

BOX

REfclCVe BURRS >t«l BREAK SHARP

MATERIAL

NUMBER

"sS
""^

ASS'Y,

OUTPUT
BYI4-DA-0
°isT.

Igl

B-17

i-va-t-ua isqa|2

I/O =ACi<.AOE SELECT

K135

-ct

-I -=-16

-c

A.S2

CURRENT i,-_C.~^'

LSB

C»3

eN.AB:.E

K.aB7

Keffi7

D«3

K207
BBZ

=tT

EM *5Lt RESn

sIlTK
|AH

e.e

AN K&I-'V

-*I43

ABC* BH

ADiZ)

Kri5

KaiA

fc®

cnn

—©

B©

a©
®

—®£

Ka«7 KSC17
KI61

Kiel

K£ 1^

KSI-^
><,aci7 K2ffl7

-t

K6I4
COOl

CDS'!

—©

n
CC

B®

-1

;

KI3%

AB2
1/

sU7

A0a

FRSi' US£D On OPTiON^OOEL

PDF - 14

(jty

^EQU IPMENT
CORPORATION

UNtESS OTHERWtSE SPtOFlED
OlMtNSWN Wt INCHES
TOL£RJVtCES
DECIMALS
nKTIONS *rt&US
,

SUKFIICE QUW-m
'

N SHttP
RcwovE BuaiK and bnean

CODNEH

OUTPUT
INTERFACE BOX
S13£ aX>E

NLIMBEn

BY 4-DA-

D BS
«ST.

B-18

JZE

I/O PACRAOt 6FLeCT

MSB

uo-i-a
HI-1-16

CURRENT ADDRESS

USB

ENABLE SET
ENABLE RESET
CLEAR

S777 KI35
^^57

Ki,S7

K2«7 Ka*7
KISI

Kiel

Ki57

>;'^57

K807 K207

FRONT

Q
t5V
(0

Should bs' coKnecTSo to r<e<s.
Side of lo/=)d supply />hd to

FWST USED ON OPTfOH/MODEL

PDP-14
UfOSS OTHEHWISE SPECtFED
UNLESS OTHERMSE SPEOFED

s^
yu6*^<^

EQUIPMENT

DATE

CORPORATION
*--

SfTE
± OTO± I/M
RNM. sutwitcc giMurr

I .000
REMOVE

y
HMn UW MCAK ShMP

5S?r"
(jjjji^X^

D.C.

OUTPUT

INTERFACE BOX

'*!/.-^^

i^S

(CXT H(GHEb/aSST

A-ML-BYI4-DD

BYI4-DDI

OMnn.

B-19

5(-0-fiva vnlo

VI
I
1

I
i

s tJrawrng

and specifications, herein, are the property of Digital Equipment Corporation and shall not be
reproduced or copied or used in whole or in part as
the easis tor the manufacture or »le of items without
'*!

Nores-2.

To £>MG NO- O-DX-BA/^-0-3
TN SLOTS M/)RKeD * *.

MODULES cfiH 6£ USED
XN SLOTS M/JRKED * ONLY
K.392; l<02Z,OR K274 MODULES
C/iN

—

—
K

N
*

!!!

fa^<t ie£-^

&£ USED'

*•

>
iV»

(Vi

»<

<
CD

(Mooace sice ^MowM)

ie£p:

OF' K^0Z /9A/0 k«a2,K27f/«iND K272 MODULE &.
M/»./Me//^ A/£//if£me of=-4csye ^oi^o^^s /s <r

2££ D£m/l-'/^'
TO fiOjdST T/M€'je MOOi/i-S^. T^e/^

FIRST USED ON OPTION MCO!

PDRI4
UNLESS OTHERWISE SPECIFIED

TOLce^f^ces)

UNLESS OTHERWISE SPECIHEB
DIMENSION

INCHES

TOLERANCES

,WX«
,XX
x.

.OoS

t .OS
t.

TTTTninTrp

ANGLES

REMOVE BURRS AND BREAK SHARP

MATERIAL

B-20

IIIIIIIWN ]

FntM- SURFACE QUALmr

EQUIPMENT
CORPORATION

ijK-j2f-l7iVg|Sai

&777
Kt35

K i35'

NOTES'.

J/O

P/!CX/5&E

MSB

SELECT

AND

SI-OT fl.a.CD-/

C^N

l)--?

fl,

8, Cj

/=1CCOMO 0'=?Tf

EITHER /0(S2,A<«i22 /< 2 /-f
OR K272 MODULES fl5
NOTED N 2, ?> se/.flK' TrtE
NJfMefR IS OPTION»I-.
2. IW SI-07"5 MfiRKED X OMIV
K3^Z., K0Z2 Ofi KZl=f ,:^0t>LiLB^
/

ADDRESS

puis IP Im
K 6
/

IN SLOT'S I^FIRKEP * *
K3a2,/«»22^ KZTf, OR K27Z.
MODULES OflN Bf (JSfD.
4. WHEW
RETENTIVE ME'MOSr
MODULES (;K2 72) /)«£ USED
/^
66X MU.ST 8F ;/V
VERTICAL POSITION TO

LSS

,_iu
/

C *3

C02

IPJSURE

PROPER OPERflT-IOh

K27S A^OOULfS

flODHESS
D\FU\L

Ka*7

El'EW

PFlOJif§-

S0<!-

SET

EN/^BLC

K2 07

O03

ENABLE RE^ET
j:Nj~rifi L.

A ** IfOf S777 <

l\J

8 -C* redjJKJ*

c *« Kiil ^Jll

k_JF

,« K'Hk2(! «

Kzr4

K3(t>Z

DSS/

D01

IT'TTJ" ,V

KZ7*
6« +

ONLY

LOOflT/oyS,

K.30Z

K^Sz :

V s
_M.

K 3 02

K2.72

C0I

C(2S'

'^
YltL
JXlii.

K3jSa

C04

-U.

«2 7-1-

K3<4z.

cai4

K2.72

Btpi

JiL

K302

K.0ZZ.

D*4

-iif

K2 >4

K3 52

K27 2

*<I3^

FLl P FLOP

/T^

RETURN

GTTV

A03
FIRST USED ON OPTIOM/MODEL

DESCRIPTION

PDPI4

EQUIPMENT

UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

CORPORATION

TOLERANCES

RlCKETrS
REMOVE BURRS AND BREAK SHARP
CORNERS SURFACE QUALITY v^

ACCESSORY
INTERFACE BCX
CBAi4~)

NEXT HIGHER ASSY.
A4>/i:.-

DEC FORM NO

3A14-B

NUMBFR

BS BAI4-0-0!
P'ST

Mil T
1

B-21

M745
ABIB
OUT00(I)H
J0I

M9IZ3

PDPe/1

BZ0

W03I

J03
PDP8/I
C2

(OH
t2i

819

(1)H

JT0I coH^ti|—
LD INPUT

BIOP
H
BIOP 2 H
BIOP 4 -

-MBS0el L
E2

(OH

;

DEVICE
SELECTOR

BAC 02 -

OUT02O)H
DUAL

S^— MBS0I

rH\^

AC CLEAR BUS L

BUS

BAC 00 -

BAC 01

M903
A20

OUT03(I)M

M921
A25

:i?— MBS02 L

OUT04(I)H
BAC 03 -

BMB 03 (0) H

(OH

BAC 04 -

(OH

MBS03 L

BMB 03 (I)h

3EVICE

CODE

OUT 05 (OH

SELECT

-^^— M8S04 L

BAC 05 .

(OH

BMB 04 (0)H
BMB 0" CO H

BAC 06-

(OH

BL_MBS05 L

OUT06(I)H

BAC 07 _

BMB 05 (0) H

(OH

—J— MBS 06 L

OUT 07(OH

AR2

BMB 05(1) H

BAC 0!

(OH

MBS 07 L

t5i'

-^^-^MBS 08 L

W031
J02

W03I
Jj04

PDP8/I

PDPen

i^MBS09 L

Q
D2

BAC 09.
(0 H
BAC 10 -

BAC
(0 H
1

-MBSia L

BMB 06 (8) H

(1)

02:

F2I

H2I

BMB

—

;H2i

^) H

J2i

i-LD MB EXT H
BIOP

-MBS II L

BMB 06(I)H

H-

jiEi
M2

BI0P2HnZ\

LD INTER
/

TSI0).\

^tl_ INT SYNC (0)H

ifxECUTE(i;/H^

BI0P4H-

BMB 07 (I) H

|J2l

BMB 08I

'^'"

Si^EXT MODECOH

lEXTEHNftL

BKI

AND

Iftia4(l)H

(eem+lem)h5E^

MODE

EXT 60 H-^^
CLBI MB L-B^!^

CoSTfeLn^T '*»E ^^™- BMB09
EXT DONE L
an?
"-"^

6 BE

END C
ITE(0)H ^^^^_^
EXECUTE(0)

BRif

INITIALIZE L
[NCTIALIZE H-

FLAG

^B2.[NTERRUPT(I)H |8"B 0^

INTER

(OH

TEST

FLOP(.l)H

BMB M

|(0H

iBS2
I

BMB 10 '

LD MB EXT H

CONTOL

V2
.

BUNg)H-

BH? EXT
FLAG(I)H
fitl!

OUTPUT
FLAG(I)H
[FIRST USED ON OPTION/

„_„
^
PDP-14

iMOOEL

UNLESS OTHEBVWSE Sf^aFIED

DR«0 I

UNLESS OTHERWISE SPECIFIED
UMCNSKm IN INCKES

!t-i-

11.

TOLERitNCES
niMTlCHS
PCCMiUS
- l/M
- OM

MfiLCS

= CM-

FiHM. su*rj>cc quMLITY

io>S

MATERIAL

REMOVC WMtS AMP WEAK SHM^
CtMNERS

^-^

EQUrPMENT

IMTE

CORPORATION
SDATE

PDP8/I

•^mJJ}^

INTERFACE TO
PDPI4

i.?Afc
DATE

f^yst.

nEkt HL&HEf- ASSY

A-ML-DAI4-I

NUMBER

DAI4-I-2
aST.

B-22

2-i-t7tva
aSBiinN
^- or D«M>I Eq«iipm«i« Coqioralion wid tf

saa
2
3003
3ZlSi

M745
ABI8
OUT00(I)H

M904
036

MQe'i

035

CPDPe/L)

ez0

(POPS/l)

M904
A20

BIOP

BK2

.BPI

BAC 00

BUS

(OH
BAC 01

.REGISTER

BI9

OUT02(I)H

BIOP 2,

-MBS0eS L

DUAJQJ

M249

BIOP 4 -

OEVICE

H
El

SELECTOR

-MBS0I L

(OH

M9fl4
034 (POPB/Q

OUT0I CDH

LD INPUT L

0UT|S3(I)H

M92I

8AC 02 -

(OH

A25

i^— MBS(S2 L

OUT04(I)H

BAC 03 .

BMB 03 (0)H

(OH
BAC 04-

MBS 03 L

^=J

BMB S3 CU H
DEVICE

(OH

CODE
P2

BAC 05 .

OUT05(I)H^^

SELECT

-MBSC4 L

(I)H

BMB 04 (0) H
BMB S4 (OH

BAC 06-

(OH

MBS 05 L

OUT06(I)H

BAC 07 _

BMB 05 CZiJ H -

(OH

-MBS06 L

12^

OUT 07(OH

S2J

BAC 08-

BMB 05(1) H

(l)H

-MBS07 L
'

-MBS 08 L

iA2
•
B2j
;

-MBS 09 L

OUT09(()h'^

—

C2'

^—

BAC 09 .
(0 H
BAC 10 -

02i
-•-

-MBSie) L

BMB 07 (0) H

OUT

'-LD MB EXT H

H-

(OH

<
L2

^t^INTSYNC(0)H

TSI(1).\

I^XECUTEflJI
"lull
H

(eem+lem)h^E^
T2

U2!

EXT 60 H-=^JCLRI MB L-B^
END CYCLE L BB2
EXECUTE(0)

RNI

AND

^B^INTERRUPT(OH 1^^^%^^-

MODE

tONTmL^^^'^T MODE
SFI

INT)L

g^g ^,3 _

FLAG
CONTOL
g

OUTPUT LI

(OH
BMB

S2)

(OH

EXT DONE L

B02 LD MB EXT H

BS2
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,4^]l}^-7Cl-^[^°

^Ijjl^^n^CLr

[vLLig^r

[Cl-^;^^

t °'°Yp^

pj^y.jrj

[vU-'g^?|

—

°'°y}^

°'°yv*\

[UJ-^l"!

p^v^is£'2*

— pXgyr

[CLy^^

[Cr^^r [Cl-^;¥

°'°yf^

[Vbi-y^f
'

WIS2
-DJI

IUI53

-DFl

[CL^:,r

'[d-^^f

i^X-zf

[C^r [CG^ [dl^ [CL^r [CSi! [wl^f
[Cl-^;;'

[CLg^?

[CL^^?

i^Xj^qI^i"

Ea^SBtffiE JJ-^^i^E^'- --

[CI-^^?

yi67

-0L2

[dl^

VI77

176
0(^2

^ jg

-DR2

SELECTION G924
G924-0-I
hi

«»
DlST.

TtT

3m, H5"l,UiS

P|r>

B-37

K022

J3QQ3 3ZrS

K022

THIS SCHEMATIC ;S FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE

CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION

R2
1

UNLESS OTHERWISE

DIODES

fNDICATED:

ARE 4.7K I/4W, 10%
ARE DBOO

RESISTORS

IDRN
'

G£Ofte£

TRANSISTOR & DIODE CONVERSION CHART

WYATT

^&J*^ mh
DATE

PROD.

B-38

Qi!

EQU PM E NT
I

CORPORATION
Cf

'"^'

ABOX STORAGE MODULE
K022

SIZE

CODE

NUMBER

K022-0-I

tiail

PRINTED CIRCUIT REV.

K135

3Q00 3ZIS

THIS SCHEMATIC IS FURNISHED ONLY FOB TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT t969 BY DIGITAL EQUIPMENT CORPORATION

V
<M
CC

L J^J

rTi rx n

Q
A

YVS

-LnV

X 1

X
±

PARTS LIST

A-PL-KI35-0-

UNLESS OTHERWISE INDICATED:
RESISTORS ARE I/4W 10%
CAPACITORS ARE 220 MMF
DIODES ARE D600
TRANSISTORS ARE DEC

TRANSISTOR & DiODE CONVERSION CHART

X X

DATE

#^'fA/iJ

d:^g.

INVERTERS KI35

t.a,

EQUIPMENT

CORPORATION

SIZE

CODE

DUMBER

KI35-0-I

PRINTED CIRCUIT REV.

T IT T \im T t T
T T T T T T T
o

B-39

K136

THIS SCHEIiWTK; is furnished OMLV for TES". *N0 MAINTtNAMCE PUBPOSES. THE
CmCUl^ ARE PROPRIETARY IN NATURE AND SHOUI.E) BE TREATED ACCORDINGLY.

K136

4©

ev DtGITAL EQUIPMENT CORPORATION

.1
'T

lO-L
o:> (eJ

in<

ro<'D<

—

"T"T

HI—

UNLESS OTHERWISE INWCATEO*.
R^fSTOftS = I/4W, K>%
CAPACITORS = lOOV

-HI-

=DEC7«I

E2 = DEC 360
PIN
=GND
PIN 8 =-l-5V
I

ON E2
'

'ON El

DfiN

'0*TE

TRANSISTOR 1 DIODE CONVERSION CHART

INVERTERS

toATE

EQU PMENT

CORPORATION

rODE

SIZE

cs
I

PRINTED CIRCUIT REV

B-40

K161,B

THIS SCHEMATIC IS FURNISHED ONLY FCR TEST AND MAlNTF.NANCf PURPOSES Th
CIRCUITS «RE rSOrBIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY

R33

R30

R27

D5
( Q14 j

Dll

(°'^ )

D14

—

(

—

)--(

( Q16 J

)

D19

D20
D17

013

016

026

>-<:
-<. C5 JR32

RZ9

023

022

025

R31

- —

D13

RZ8

R23

R22

R26

R25

R11

R10

010

024
D21

—

D15

R17
R14

— —
— —

R16

DIS

DI2

D9
D6

"KnOr'^"^
(

010

( °' )

-CED-

TRANSISTOR [)EC6534D
OR D£C22!9A
TRANSISTOR DECOOOI

Ql, 03,05, Q7.QB
1

R32,R33
R2I,R23^4.R2C,K27,R29,R30,

- Q-» fail

Ires.

i.8k

i/4W

io% cc

l^K

1/4W

10% CC

Qlg Dlj! I^IK Dl-T (S JO fSJ

TrES.

RI0,Rt3.RI6^t9,R2g,R25,Rg8.R31

IDIODE D600
CAP,

680MMF lOOV 5% 0-W.

iCAP.

.01 MFD

[PARTS

'"'

TRANSISTOR & DIODE CONVERSION CHART
'date
DATE

'fy^

DATE

DECeSMO 1MPS6534
DEC22I9A

|gN2Z!9

lOOV 20% DISC
a-pl-k;6i-q-o

LIST

OESCRfPTION

REFERENCE PESIGN&TIOH

EQU PM ENT

BINARY TO OCTAL
DECODERKiei
NUMBER

CORPORATION

KI6I-0-I
PRINTED CIRCUIT BEV,

B-41

K161,D
-0H9IX

NOTES:

V
u
T

/E5-*

filB

Rae
,.o*

RI7

L
K

/iar

/I3£

/f33

cjs

/?3

H4- 2>3

/Sjr

Jfa*.

AZ3
/fit

/fX

E
D

fKZ
/fai

£3

T
US

DS.

_
P36

RS
R 3?

B-42

RI3

R
P
N

/f4

ff/a

VS9

Rao

/t3tf

/?/

C{>

.ML.

l-OI9l>l

09
-OIUF

+5V
CIO
390 PF

{Ras

H(
RI3

--VW|r2I

vW"

390PF

-Or
R14

012

390 PF
RI5

—wv—

I CO

UNLESS OTHERWISE INDICATED
RESISTORS - l.aK,l/4W,5"yo
TRANSISTORS- DEC 3009B

ETCH REV D
FIRST USED ON QPTIOH/HTODEL

DESCRIPTION

PARTS LIST
UNLESS OTHERWISE SPECIFIED

''AArj

DllhENSION It* INCHES.

TOLERANCES

mum

EQUIPMENT

CORPORATION

BINARV
NEXT HIGHEH ASSY

NUMBER

cs
SHEET e

KI6i-0-

'III
1

B-43

K207

THIS SCHEMATIC IS FURNISHED ONLY hOR TEST ANO MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN ^ATy«E AND SHOblD BE IREAIED ACCORDINGLY.
COPYRIGHT 969 BY DIGITAL EQUIPMENT
I

V OR

EXPANDER

HI-

UNLESS OTHERWISE INDICATED:
DIODES ARE 0600
TRANSISTORS ARE DEC
CAPACITORS ARE pf,IOOV,5%
RESISTORS ARE I/4W, 10%
EI,E2,E3,E4 ARE OeC7401
E5 IS DE;7400
PIN 7 ON EACHIC = GND
I

ON EACH IC = -l-SV

TRANSISTOR & DIODE CONVERSION CHART

FLIP FLOP K207

digiltail
A.RICKETTS

JEOUIPMENT

NUMBER

K207-0-I

^CORPORATION

;

B-44

PRINTED CIRCUIT REV.

K272

-0-EiEX

•A3a

3Q03

3ZIS

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

o
5

Ud)
1

^
^

^^'^aM Wi9
ifT-EAif;
DAtP

RETENTIVE MEMORY K272

EQUIPMENT

CORPORATION

CODE

NUMBER

K272-0-I

-J

O
W

i©

1
1

PRINTED CIRCUIT REV

TRANSISTOR & DIODE CONVERSION CHART

DRN.

UNLESS OTHERWISE INDICATED:
DIODES ARE D6C0
RESISTORS ARE I/4W 10%
Kl IS HGSM5020 RELAY
SI IS SWITCH ri07

B-45

K274

B-46

K302

This schematic is fURNISHtO ONLY FOR TEST »N0 l**INIEN»NCE PURPOSCS. THE
CIRCUITS *RE PHOPRIETABT IN NATURE AND SHOULD 6E TREATED ACCOBDiNGtT.
COPYRIGHT (9A9 BY DIGITAL tQUlPMENT CORPORATION

*
a

in
cc

A
^

-czo
I.I. .1.1. ,1,1

-LJU JO
°

s
1

,11 -c " )-

©©

"1
^

J_l

lO
(C

la *

^
a:

UNLESS OTHERWISE INDICATED

CAPACITORS ARE eeOMMf iOOV
DIODES ARE D600
RESISTORS ARE 1/4* iO%
R36,R37ARE POTS HELITRIM 76PR
O ARE JUMPERS

Y
Y

TRANSISTOR & DIODE COIWERStON CHART

TWO TIMERS K302
EQU P M ENT

DATE

5!fcaaj^

ill

0EC6S4D
DEC2219A

I
!

MPS6534

CORPORATION

2N2ai9A

"•

CODE

NUMBER

K302-0-1

PRIKTEO CIBCUIT REV.

B-47

K564

K564
14-0150

B-48

COMMHT tm- H

UNLESS OTHERWISE INDICATED
RESISTORS ARE 1/4*, 10%
CAP*CITORS ARE 3.9UF, IOV,IO%
ARE D6&4
TRANSISTORS ARE 0ECS5J1
DEC384- EI.E2

CK)

.OIUF

-LauF

lOOV

20%

DIOCES

GND, ACI . AC2

PMI'GND
ON DEC3e4
PIN 8»+5V

TITIE

DC INPUT CONVERTER
«!««

Ull caoEl
OS

K!i64-0-l

„,.nDC«>jniic.

IBM II

XlI

B-49

K578
R3

-M-

D26

-MD5

D4
-*h-

-«R5
01

—M
D25
—M

R9
R12

D12

028

M
C4

D11

D10

D9
R11

-M-

027

—W—

030

—M—
014
—M

R15
R18

Die

w
—017

__C6

_[C5

015

013

—M—

R17

029

RI3

020

R21

W
032

—W—

R24
023

M
024
021

—W—

022

W
R23
R19

B-50

019

-M—
031
-W—

K578

THIS SCHEMATrC rS FURNISHED ONLY FOR TE5T AND MAINTENANCE PURPOSES- THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BV DIGITAL EQUIPMENT CORPORATION

ADZ

AB2

AT2

AS2

ADI

ABI

ATI

ASI

9
if D24

OACI,AC2 GND

oo
o

TERMINAL BLOCK
Tl,-T8
R5,R6,RII,RI2,RI7,RI8,R23, R24

BLOCK, 9 TERMiNAL 699-2-370!-9
TRANSFORMER, POWER
RES. 4.7K I/4W 10% CC

II-T8
RI,R5,R7,R9,RI3,RI5,RI9,R2I

RES.

390

I/4W 10% CC

DIODE D600
DI,D2,D7,08,DI3,DI4,DI9,D2O,D25-032 DIODE 0672
CAP.
68 MFD 15V
CI THRU C8
D3-D6,D9-DI2,DI5-DI8,D2I-D24

A-PL-K578-0-0

REFERENCE DESIGNATION
DRN.

[DATE

"^M^

izzlh4

DESCRIPTION
PARTS LIST

TRANSISTOR & DIODE CONVERSION CHART

AC INPUTS

\I^L f/bzlgi

EQUIPMENT

CORPORATION

K578

SIZE

CODE

NUMBER

REV

K578-0-(

PRINTED CIRCUIT REV.

B-51

TfflS PAGE LEFT INTENTIONALLY BLANK

B-52

K579

B-53

K614
-

<~^^~~>-

—

5 0-

—

L-El

R t

—

R30

—

-C1E>

nrr

j—

—

R14

—

)

-(
—

)

—

„2

9
-CIcl^—

DI1

—

CI5

-c

R39

-C

CI9

—

R38

-dJEDR44

-r R36
^^
I

-C
—

D6
I

-C

cie

—

-a
—

—

R19

>
D8

CIS

Rll

Rt7

—

—(

R23

022

DI2

—

—
)

—

R43

—

—(

C20

)

—

R45

—

CI8

(

C14

—

)

Wy
-(

B-54

—

~T4—

—(

)

R13

-CHZ)-

R52

-CIO

—

QllJ
CIS

K6I4

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

Q7,Q8,QI3,QI4
Q3,0S,Q9,QII

01,02,04,06,0 10,012

RSO, R3I,R54,R55

RZ6,R29, R50,R53
R24,R27, R48,R5

TRIAC RCA 40430
TRANSISTOR DECI008-S
TRANSISTOR DEC6534D
RES. I5K I/4W 10% CC
VARISTOR 333 BNR - 7
RES. lOK
2W 10% CC

li::'J

R44-R47,R49,R52

1/4

R7,RII,R20-R23,R25,R28,R33,R35,
^aaFSi«,RI4-Rr7, R38-R4I

RI9, R32,H34,R36,R37,R42,R43jR4

10% CC

RES.

4.7K

I/4W

10% CC

RES.

I.2K

I/4W

10% CC

RI,R2,«a,R6y,»,RI0,RI2,RI3,RI8,
DIODE D672
D7, 08,015,016

DI- D6,D9-DI4

DIODE 0600

CII,CI2,C2I,C22
C7,C8,CI7, CI8

CAP.
CAP.

C5,C6,CI5,CI6
C3,C4,CI3,CI4

CAP.
CAP,

^C»,C9,CI0, CI 9,C20

.047 MFO 400V

2.2MFD
lOOMMF

20%

20V 10%
lOOV

5% DM

1000016

680MMF 500V 10% CER.

.047MFD 250V 20%
CAP 22MFD 6V 10% TANT
PARTS LIST

CAP.

A-PL-K6I4-O-0

DESCRIPTION

REFERENCE DESIGNATION

PARTS LIST

RN
olo
O O
o o

o O
O O
o o

Y^'

[DATE

,..- -:^iAv^i
,

olo

imOD

DATE

TRANSISTOR & DIODE CONVERSION CHART

digital ISOLATED AC SWITCH K6I4
EQUIPMENT

CORPORATION

MAYNAAO, MASSACHUSETTS

SIZE

CODE

NUMBER

K6I4-0-!

RFV

PRINTED CIRCUIT REV

B-55

K616
I-0-9I9M

WIIWH

B-56

(!-,»«».-»

a 2

3ZW

I-0-9I9M

a
S3
3goo ]zn

«tO at OHIfl riiiiwnunt CwtecB— id ^
miiuitirl or cspiM or mad m artistt or
Hw teM far Hia manafacnin ar aaia a( Haa

AF/.AFa /^i
AH'.AHZ

|CD

IP
R^0

sTTT

xn
L
RCSISroPS l/'i-VJ 5Vo
CAPACITORS - /i,^ V, a.^ •%
PIN 7 = SNO ON £•/

ITEM

DESCRIPTION

REF DESIGNATION

UNLESS OTHSRWISe INDICATED:

ETCH BOARD REV

pm 14= ts^

JUL

^fe-w-^,

DATE

SEMICONDUCTOR CONVERSION CHART

DATt

ISOLATED

OUTPUT

^ ^•NEXT HIGHER ASSY
DEC NO.

EQU P M ENT

CORPORATION

ElA NO.

NO.

CODE

NUMBER

REV.

K6io-0-i

CTST.

[

B-57

K657

B-58

PURPOSES THE
iS fUHNlSHED ONLY FOP TEST JVND •^ftlNTENRNCE
C\RCunS ftftE PBOPaiETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 197 1 &Y DIGITAL EQUIPMENT CORPORATION

TH\S SCHEMMIC
L

^^^

UNLESS OTHERWISE
DIODES ARE DSOO
PIN

=GND,
ON ALL IC3

PIN8 =+5V

INDICATED:

+ 5V,AAI,AA2-

C.I

3.9UF

C2
.OIUF

SHEETZ0F2
RN
CHK-n

DATE
I

f^JlM^

TRANSISTOR & DIODE CONyERSlON CHART

POP

(DATE

lEQU P M E NTl
InnHPORATlON'i
1

SIZE

1 CODE

14
]

D.C.

DRIVER

NUMBE

K657-0-\

NTED CIRCUIT Rt>

•wrm

B-59

M106
THrS SCHEMATIC IS FUftNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

Al -

Cl-

y
D4

I.I.I

D2F2-

111111
-CIEI>-

-C

DIO

R2A2 +5

T2-

UNLESS OTHERWISE INDICATED!
DIODES ARE D664
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = + 5V
IC'S ARE DEC888I
CAPACITORS ARE .01 uf, lOOV, 20%

T
DI2

DRN.

DATE

ili»;t^<ic^

1'-t'(-9

TRANSISTOR & DIODE CONVERSION CHART

digii tal

EQUIPMENT

CORPORATION

DOT NOR GATES Ml 06
CODE

NUMBER

MI06-0-I

PRINTED CIRCUIT REV,

B-60

REV.

lAlll

M232

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PRO°RIETAR> IN NATURE AND SHOULD BE TREATED ACCORDINGLCOPYRIGHT 1970 e- DIGITAL EQUIPMENT CORPORATION

H(
O

cjl

[

;

^
(T

;

*
O o
lO

ID
CC

-^^

©
JNLESS otherwise indicated:
RESISTORS ARE 3-9K, l/4W,578
CAPACITORS ARE I200pf ,lOOV,57o
DIODES ARE D664
El IS DECT '81

E3 IS DeC740l
E2,E5,£6 !S DEC7400
.

GND 1

=+5Vj ON E2,E3,E5,E6

Hf-

TRANSISTOR & DIODE CONVERSION CHART
D6S4

'(7.fij<^

°'''-76

IM3E06

'"''

BIT ADDRESSABLE
STORAGE M232

EQUIPMENT
CORPORATION

rM'j^3M_^4lM

NUMBER

M232-0-I
PRINTED CIRCUIT REV

I'^IBI

£'.

B-61

M249

VW-

—
R3 —
R2

li
TT

^AA^

VW-

i
C5

1
T

11
TT
C4

E8
E7

11
TT
C7 C6

B-62

THIS SCHEMATIC IS FUftNISHEL' ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1971 BY DIGITAL EQUIPMENT CORPORATION

R6
2.-2K

-V^A,
CI

+ 3V INTERNAL

UNLESS OTHERWISE INDICATED:
RESISTORS = I/4W, 5%
CAPACITORS = .OIUF, lOOV, 20%
DEC 7402 = E8
DEC888I= EI,E3,E6

DEC40I6P = E2,E4,E7
DEC7437 = E5
PIN 8

GND f^p, .. __

+5V™^2'"'^^

I6 =

PIN
PIN

7 =GND
14 =

+5V ON ALL OTHER IC'S

DATE

DRN
/va/vo' M00I2E

TRANSISTOR & DIODE CONVERSION CHART
DEC3009B

CWS

DATE

P.JgfeL f-^'^-»

;

ZH3009

gii

EQUIPMENT

CORPORATION

BUS REGISTER
CODE

NUMBER

M249-0-

PRINTED CIRCUIT RE^/

B-63

M740
—(

A
Y

A
V

<1-

en
UJ

V
-(

—

s
UJ

B-64

M740

--i-.

4-55

B-65

M7400

-0^^^^

NOTES:
(

UNICSS OTHCRWISC: SPECIFI£D,ALL
CAPACITORS ARE IdtV, Z0%
ALL RESISTORS AR£ //*W,S%

RfSBTANCE- IS JN OHMSCAPACITANCE IS IN PICOFARADS.

4
3
2
,

REF

^'~\-

h
iL

•\l

^^=B-

k f"

„

clo
1

5.19 REF
as

(ft

ff7

B£S 2.2K I/4I 5S

C(6

lie.

-..

its':

K.
,

AAZ,BA2

117 THRU
€19
,

BCa.BTI

MFC,

IC DEC

lc.3

7402

DEC 74H40

IC DEC

sU7

lUO

IC DEC 7410

E3.E4.E7.EII.E15,EI6,EI9

CAP.

.^JUI

.01

l)f

lOOV 20t DISC

CAP. 39 UF 10V I0« TANT

-5.94 REF

EYELET, GS4-7 STillPSON
HANDLE. FLIP CHIP. BAGEUTA

ETCHED CIRCUIT HOAPO
B'MN-117400'0-6

IIOOaLE ECO HISTORY

K-Y LOOROIKATE HOLE LOCATION

K-CO-II7400.D-4

ASSY/DRILLING HOLE LAYOUT

D-AH-U7400-0-5
ITEM
NO.

REF DESIGNATION
FIRST USED ON OPTION MODEL

DLI4

ETCH BOARD REV

EQUIPMENT
CORPORATION

CHKD. ^.^

DATE

^I^T2
DATE

WW7J

I\STRUCTIOM

ViJ^ ^.

T^ii

^Jt-

iEXT HIGHER ASSY

GNO AND 5V ARE USUALLY PIN 7 AND 14
RESPECTWELV EXCEPTIONS ARE STATED ABOVE
IC PIN' LOCATIONS

B-66

-/EIA NO.

DEC NO.

SEMICONDUCTOR CONVERSION CHART

DECODER e CONTRO.
azEHBEf^
'0

jCbi

DIST.

NUMBER

M7400-C-I

Y]
ASH

J^^^Vi-

|S0|a|2

l-p-00l7Zlrt
~B3tHnfl

I
[

i?3f/jJ3ZIS

~OFCR£M£Nr ENABLE H

-INCREMENT ENABLE H

50R-PC:(t--'!) f^

y^^M^ soR-pc.1(0- 3) H

—w\>—

PCIEL^-£^

SOK-MB '.4-lllH

^"^fY^-^iOR-NtB (S;-31H
R7

iNTsmc ca)n Si^

—vw

_g9.

^^£M-&^-M£M H

bOR-IRl-'-l!)H

IRE L S&^

aOR'IR(0-3jH

is
SOR-iPARE H

IR0i.(l>H -BBLM.
iRiyojH j4a !±

—

5,3^5
SOR-Pf:£ //

SOR-INPUT H

SoggJOf &

DESCRIPTION

REF DESIGNATION

PARTS LIST
ETCH BOARD REV

EQU IPMENT

dSTe

aM^i/u,i^,

CORPORATION

f-/-!-7£

DATE

'"k'lyitHQi

^^.//<g.^ ^v/;a
I.

ENa

DATE

^r J/tfn^tt^
(^XT HIGHER ASSY

INSTRUCTION

DECODER i CONTROL
NUMBER

SIZE CODE

SOIIE

SEMICONDUCTOR CONVERSION CHART

DCS
°gT.

M74(Zi0-0-l

B-67

M741
R1

-GE)-

-QE>
-

—

—
0-

-CEI]*
3lij

RIO

^'^

—

-CfliZh

—(_C6_J-

—
—

RI6

1—

R17

—

"'^

h A

B-68

^'^

—

R20

—

M741

B-69

M742

AA<VC12-

® GvG^

R7
R8

diC5

1
T

•R30

R29

R27
C8

B-70

1
T

M742

THIS SCHEMATIC IS FURMSHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

RUN (II H CAH2)
+5
I

ol==
LOR

CONTINUE L

START

NODE A

1.4

0.7 r
0'

I200MS

W.ITCH ON (AN2)
I

LET
+ 5V POWER
+5

ZOOMS
SWITCH ON (AN21
+ 5|

SHUT DOWN L

(BUI)

+ 51
I

IV-!

90MS
START EXT L
+51

]

- -200NS

„J___U
INITIALIZE H (SHI),

+5i
I

M742 TIMING

UNLESS OTHERWISE INDICATED".
CAPACITORS ARE .01 MFD, lOOV, 20%
DIODES D67Z
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC =+5V
El

ISDEC7474N

E2,E6 ARE DEC7400N
E5,E7 ARE DEC740EN
E4 IS DEC740IN

EXECUTE B)H

E8 IS DEC7440N
RESISTORS ARE I.8K, I/4W, 10%

,,y (TXD+TYD)L 9^

TRANSISTORS ARE DEC3009B

E9 IS EC74I0N
E3 IS DEC 9601

.
fOBN.

DATE

BUTLER

«-l7-*f

ENG,

»-go-ai
[Ate

A.RtCKETTS

|7-2l-6i

Tc2 Tra

C4 'Tc5

r r

|C6

'™' SWITCH AND POWER

TRANSISTOR & DK3DE CONVERSION CHART

dli giiltia;!
!°ig

^^m

EQU PM ENT
I

CORPORATION

CONTROL M742
CODE

NUMBER

M742-0-1

REV
I

PWINTEO CIRCUIT REV,

B-71

M743
D33

*
UJ

R30

R26

R29

CJ
Lii

R25

^
Ui

R23

*
*
iLl

R18

«-

034

D31

D32

D2T
D28

D29

D30
D25

D26

—
—
—
—

D23

D24

D2 1
D2 2

D19

020
017
Die

R16

—
—

— A
—

-CIEDD1

V-

03
UJ

R10
R11

R8
UJ

R4
R5

A
to

R2
R13

R14
R15

-d

—
—
—
:
—
—
—

°'°

T
^

D14

011

-1

—

(

>—
M743

B-72

TKI< SChCMMIC is FudMWEO ONLY raft TEST AND tUINTENAHCE PURPOSES THE
T»t*TeO ACCOOWHGLY
SMOUtO
CIRCUITS «RE PfNJPRIErART [N NATURE

CO»'«MG«T 19«» en WGiTAL EQUIPMENT COgPOW*T>QN

PSi H
BAI

PS2H

PS3H

PS4H

PS5H

6J Z

BL2

BN2

BR2

PS6H
BV2

PS7H
BU2

PSSH
BT2

I/O STROBE H
AAI

D3oX

4
I

flXN+TXF+TYN+TYF

"^027

•

'«

£d29

<»

^(-SYN + SYF+TXD +TYOy

UNLESS OTHERWISE INDICATEDRESISTORS ARE 4.7K
RESISTORS ARE l/4W,5%
CAPACITORS ARE Ol MFD
DIODES ARE 0664
TRANSISTORS ARE DEC3009e
PIN 7 OM EACH IC - GND EXCEPT E9
PIN 14 QIN EACH IC = +5V EXCEPT E9
E3,t4,E7, EIO,EII ARE DEC7400
Ei,E2 ARE QEC74I0
E6.E8 ARE DEC7450
£5 IS DEC7430
E9 IS DEC825)B
PIN 8 ON E9' + 5V
PIN 16 ON E9 = GND

;5j:.-°.-"^i

B-73

M744

'1
I

00
UJ

»t

LiJ

•*

R12

—

R13

—

:i
r-

•-

— C2)—
(

R14

^
»-

•a-

N-

—

Rt5

R16

M744
r

B-74

THIS SCHEMATIC iS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES- THE
CIRCUITS AR£ PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
1

£3
II

u
9

W
9

E5
8

E5
2

V
5

E5
6

^=
3

A A

E8
12

t-WV -AA'V-i

•

(*)I0

llf

>-^VW-»-WV-i

ElO

EIO

_9]

ElO

^5]

EI3

^5|

EI3

ir i2J

EI3

ilr

EI5

iTT

12]

A A

„J

EI5

J
4

r\
V

—

E12

V~9
9
8

A A

4E2

A02

4H2

AF2

^?9
2

A A A

AK2

AJ2

AM2

AL2

AP2

AN2

AS2

^?9
5

AR2

BE2

BD2

^?9
9

U~9

A A

BH2

BF2

BK2

BJ2

BM2

BL2

BN2

BP2

8R2

BS2

UNLESS OTHERWISE INDICATEQ;
EI,E4,E6,E9,EII,EI4,ARE DEC7400N
E2,E7,EI2, ARE

DEC7402N

E3,E5, E8, EI0,EI3,EI6 ARE DECr40!N

RESISTORS ARE

I.5K I/4W

5%
MFD

.01

MFD

[date"

TRANSISTOR 4 DIODE CONVERSION CHART

t^*

dilgi lit jail

EQU PM E NT
I

jSTr

=~^ 8^2^:8^;—'^

DRN.

C2:

CI
.01

CORPORATION

SIZE

CODE

NUMBER

M744-0-I

MAVNARO. MASSACHUSETTS PRINTED CIRCUIT REV.

B-75

M745
D20
D19

R16

-/VW

^7^

(uio)

Q1
D18

017

E3
Q3

D16

D25

R3
05

R5 -^vw

D5
D12

—WV/

(

012

R12 -JVAA,
1

+•-

R8
-AA/V09
R9

R15
015

013

024

015

023

R13

R14

026

E8
E7

Q16

R20
R21

R22

017

R23
R19
Ell

D27

E9
C6

R18

022
E15

R24

+t-

R17

021

C8
El 8

E13
-]-

E17

M745

B-76

B-77

M7450
NOTES:
OTH£RIVJX SPeclFtCD:
R£ili-m/JCe 7S IN OHMS,

/ UNLCSS

C/lfyKlT/l/lKe TS IN PlCOKWtfiDZ

B-78

a
30
3003 ans

)-0Si7/.l/M
ifiWHnM
•ny of Diciai Equcmant CMHWWmn Md

tSV

3«wl or uwd ^ iriHloai

LDMBEXT H
ID OUTPUT L
^Sii ^xr/««aQr c <; w

£KT MODE t
ZNT SrNC H
-INT SYNC OiH
->i26^

M-fiC^C-

(SJT-

PUT
(.aM-tLEMJHt

Sl^ INT SYNC (0)H

IHiriAU^EL

C&i7&f&m)
BBi

7474 >2S_
^25-

^/IC d&L

>
_L
I

EXT SO H

K4l ^3

SiL-

INITIfiLIZEH

(I0T&/C&)^
Jp'«*~--Y%2a_

3E>'

DCDH fe>^^
&I6X

f 7 3^2-

/3,t

^
fN OUT DRIVER L

3S4
iiTEST point)

..r^
t±£2_

flue latoV-

—

fayM

.±t5!

6<6£

ft't

i-OblPLT FL/iGmi

<r^r /-z^ i-/j«

7**2)

&I63 tte^

74«*\^2__*4 <f/3
^E13 J~^

1<S7

-EXT Fl^ (lit

-ID

-inT PQ.sr I

575
-0^

74/5/

/:>/

fS"

04
Tfjr noecDH-

IX.

Lad—-^

07
se
III

^ Qg'

&irx
pie,

4iS
_49

tme <K (IJ „

/IRiJ

f 7 >*S_

on
0£

J J

sa
It

BMti0^(l)H ^^i^
CK.

>»6_
f5->^

/oi° ga lY

REF DESIGNATION

\ 7i*a

isJi-iy

<5W
ETCH BOARD REV

13 -la.aibyf'^

DESCRIPTION

7-ftS4

:o/

"Jf/f/.-ri

&*IB 17 (h "^mi

CHK'D.^

EQUIPMENT

CWTE
.

^/'ii7i
DATE

SDSDaSD CORPORATION

fi:>^-

iiO^^
flH-f£5fif!aw^

JTERFACE

NEXT HIGHER ASSY
CODE
SCALE

-/-

NUMBER

>y:74 50-0-1

SEMICONDUCTOR CONVERSION CHART

B-79

M746

THIS SCHEMATIC IS UIRNISHID nM" FDR T[5T *N11 HAINTLNftNCf I'lltil'DSES THE I
BF IHIAUD ACCGHUIMJLV
CIRCUITS ARE PfiOPMIL1At)Y IN NAIIIRK ftNl) SHOUi
[
'VOIGMT I9S9 BY OlCIIfll KJltlCMFN' COI't'ORAllON
j

—

-f

UNLESS OTHERWISE INDICATED:
RESISTORS ARE IMW, lO%,2.2K
PIM 7 ON EACH IC = GND
PiN 14 ON EACH IC = +5V
El AND £4 ARE DEC 7401N
E2,E3 AND E5 ARE DECTAT'JN
CAPACITORS ARE ,0l MPD.lOOV, ?0%,Di SC

TRANSISTOR & DIODE CONVERSION CHART

d
ld*TE

g,i:t a|

EQUIPMENT

CORPORATION

BUS REGISTER iVI746
CODE

NUMBER

M746-0-I

PRINTED CIRCUIT REV.

B-80

13]

r*i

Y
T

-L^

'CHK;

)

t»t

r ~r
C4

—(

)

III
C3

)

M747

S SCHEMATIC IS

KURNISHED ONLY FOP TEST SND MAINTENANCE PURPOSES Tf

CPRCUITS ARE PROPRIfTAPY IN NATURE ANO SHOULD BE TREftTED flCCORDIMGLY,
COPYRIGHT (969 BY DIGITAL EQUIPMENT CORPORATION

X X XX JL JL jL JL O^JLO,

T TT T TTT T
'

T T TT

CLEAR

UNLESS OTHERWISE INDICATED
CAPACITORS ARE .OIMFD lOOV
DIODES ARE D662
RESISTORS ARE 2.2K 1/4 W 10%
PIN 7 ON FI,E3,E4, E6,E7,E9=GND
PIN 14 ON EI,E3.E4,ES.E7, E9^+5V
El

MC300I

E4,E? ARE DEC740IN
E3,E6, E9 ARE DEC7474N
E2,E?,E8 JIRE DEC74e£. N

PIN 4 ON E2,E5,Ee =-l-5V
PIfJ 11 ON E2,E5,E8 ^ GND

riTte

TRANSISTOR & DIODE CONVERSION CHART

SfLijfi^Jg
/

DATE

DCC

INCREMENTING BUS REGISTER

EIA

0662

n (iM^ Wo

Ne45

EQUIPMENT

CORPORATION

SIZE

CODE

M747
MUMKR

M747-0-r

PRINTED CIRCUIT REV,

-^1

B-81

M921
\

A3 a.

I-0-IE6W

d38NnN

3000 3ZIS

PURPOSES. THE

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION

PIN SIGNAL

ASSIGNMENTS
OUT

DEVICE A

SIGNAL

DEVICE C

DEVICE 8

D2 OAl

MB 3

MB4

MBS

MB6

MB7

E2 OF2 O-

MBS

1
I
1
I
1

H2 OJ2 O-

39
Q>-

1
I
1
1
1
I
1

ODI

MB3(I )

MB4(0)

046

MB4(

(^47

(^29

1VIB5(0)

M2 O-

MB5{I

N2 O-

MB6(0)

MB6(I

MB7(0)

MB7(I

MB8(0)

)

043

)

MB8(

OFI

OMI

OKI

ONI

ORI

03:

OSI

014
I

1
X

)

031
OPI

R2 O-

OCI

K2 a-

OLI

-OBI

Oji

MB3(0)

OEI

O-

OHI

044

-OAI

S2 O-

54
OUI

1
I

016

OVI
35

OT2

UNLESS OTHERWISE INDICATED:
Q) ARE SPLIT LUGS

DRN.

DATE

///^/69

TRANSISTOR & DIODE CONVERSION CHART
DEC

DEC

'0'-~/>^^

EQUIPMENT

CORPORATION

y/f.fePfiOD.
-I

DEC FORM NO
DRE 1C2

B-82

L-

(

'"''DEVICE CODE SELECT

DATE

_^ )uiAVNARO,

JUMPER BOARD

d'iiglrtlail
SIZE

CODE

NUMBER

M92I-0 -I

MASSACHUSETTS PRINTED CIRCUIT PEV.

714
ri}d/i'^^^-S~

PL UGr
ao^-

5/L

r^A,

—

-«

y\A.

lOfi

R£D- *^/VrJU^^

/^g rtA/-^.;tD

Lorto

isLk-^;V/9.oG
j'>*^ r\

—

-9

A-Rw-^yS-fl^f.

\/<0'^ ^^j^ui^

—
47.1-

iNjaof/'/i^'

--^

—

-w

R /'j,v"'.^o<

.t-.

9- A/

30 ST

<i—\A/-

ofcta.

.0/

y6v

^:
—

B-83

THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE r'URPOSES. THE |
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
|
COPYRIGHT
BY OIGITAL EQUIPMENT CORPORAIION
,
,

TBI

SOLDER
I

TeRMlNAi.&
SOPPLieS

£1

<s>

O
TRANS F25-X
THS'RACTOR

lfcOI347

£RS'20SPeB'^J

IO'2eiS

Fust Hoo::).

900&99(£>

5>W/

Sfefe-5

SMITH

SOCKET licO-4
TERMINAL STRIP
TSl
DESCRIPTION
R£P DESICbNATiON
PART5 CIST
PI

j?:5'

'"''

TRANSISTOR 4 DIODE CONVERSIO!^ CHART

dig

fa
EQUIPMENT
i

PART MO.

FILTER
SIZE

cooeT

CIRCUIT

number

17006314-0-

PRINTED CIRCUIT REV

B-84

201S9io

POWER SUPPLY

CORPORATION

cOi 199
I20r25l

PDP-14 MAINTENANCE MANUAL

READER'S COMMENTS

DEC-14-HGZB-D

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