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DEC-12-SRZB-D

June 1971

321 pages

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Document:	PDP-12 System Reference Manual 3rd Printing
Order Number:	DEC-12-SRZB-D
Revision:	000
Pages:	321
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-12-srz/dec-12-srzb-d.pdf

OCR Text

Digital Equipment Corporation

Maynard, IViassachusetts

[•iiil.iiiubi

PDP-12

SYSTEM
REFERENCE MANUAL

DEC-12-SRZB-D

PDP-12

SYSTEM REFERENCE MANUAL

DIGITAL

EQUIPMENT

CORPORATION

•

MAYNARD, MASSACHUSETTS

1st Printing (Preliminary) June

1970

2nd Printing (Revised) July 1970
3rd Printing (Revised) August 1971

The material in this manual is for reference
only. Instruction times,

operating speeds,

and the like are provided solely as reference
information, and are subject to change at
any time without prior notice. The drawings, specifications, and descriptions herem
are

the

property

Digital

Equipment

Corporation, and shall not be reproduced or
copied in whole or in part as the basis for
the manufacture or sale of items without

written permission.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS

Chapter

Page

CHAPTER 1 GENERAL DESCRIPTION
1.1

Description

1.1.1

System

^.j

1.1.2

Central Processor

1-3

1.1.3

Memory

1-4

1.1.4

Operating Modes

I.4

•

1 .5

1.2

|.|

Input/Output Facilities and Display

1-5

Symbols and Abbreviations

1-6

CHAPTER 2 CONTROLS AND INDICATORS
2.1

PDP- 12 Console Controls and Indicators

2-1

2.2

Data Terminal

2-1

2.3

2.4

CRTDisplay, Type VR12
LINCtape Transport, Type TU5

2.5

Teletype, Model 33 ASR

2-1
2-1
2-1

CHAPTER 3 LINC MODE PROGRAMMING
3.1

Organization of Memory

3-1

3.1.1

General

3-1

3.1.2

Program Counter

3-2

3.1.3

Instruction and Data Field Registers

3-2

3.2

Memory Addressing Methods

3-3

3.2.1

General

3-3

3.2.2

Direct Addressing

3-3

3.2.3

Indirect Addressing; j3-Class

3-3

3.2.4

Addressing: a-Class

3-6

3.3

LINC Mode Instructions

3-6

3.3.1

Instruction Formats

3-6

3.3.2

Instruction Descriptions

3-7

3.3.3

Full-Word Instructions

3.7

3.3.4

Full-Word Logic

3.3.5

Full- Word Comparison

3-12

3.3.6

Half- Word Operations

3-13

3-11

3.3.7

a-Class Operations

3-14

3.3.8

Program Control

3-I5

3.3.9

Shift and Rotate Operations

3-16

3.3.10

Skips

3-19

111

CONTENTS (cont)
Page

Chapter
3.3.11

Miscellaneous

3-21

3.3.12

Console Switches

3-22

3.3.13

Mode Control

3-22

3.3.14

Input/Output Bus

3-23

3.3.15

Memory Address Control

3-24

3.3.16

Special Functions

3-29

3.3.17

Instruction Trap

3-30

3.4

CRT Display, Type VR 12

3-31

3.4.1

Point Displays

3-32

3.4.2

Character Displays

3-32

3.4.3

Half-Size Characters

3-33

3.4.4

Character Set

3-33

3.5

Data Terminal

3-35

3.5.1

Analog Inputs

3-35

3.5.2

Relays

3-36

3.6

LINCtapeTypeTCn

3-37

3.6.1

Organization of Data

3-37

3.6.2

Programming
Tape Motion

3-41

3-43

3.6.8

LINCtape Instructions
Extended Operations
Extended Address Format
Extended Units
Tape Interrupt Enable

3.6.9

No Pause Condition

3-48

3.6.10

Hold Unit Motion

3-48

3.6.11

MARK Condition

3-48

3.6.12

Maintenance Mode

3-49

3.6.13

Tape Trap

3-49

3.6.14

Tape Word Skip

3-49

3.6.3

3.6.4
3.6.5

3.6.6
3.6.7

CHAPTER 4

3-42

3-45

3-46
3-47
3-47

8 MODE PROGRAMMING

4.1

Organization of Memory

4-1

4.1.1

Organization

4.1.2

PageO

4-1

4. 1 .3

Extended Memory

4-2

4.2

Memory Addressing Methods

4-2

4.2.1

Direct Addressing

4-2

4.2.2

Indirect Addressing

4-3

4.2.3

Autoindexing

4-4

4.3

8 Mode Instructions

4-5

4.3.1

Memory Reference Instructions

4-5

4.3.2

Operate Class Instructions

4.4

Program Interrupt

4-12

4.4.1

Operation

4-12

4.4.2

Using the Program Interrupt

4-13

4.5

Extended Arithmetic Element Type KE 12

4-13

4.5.1

Operation

4-13

4.5.2

4-13

4.5.3

EAE Instructions
EAE Programming

4.6

Extended Memory

4-19

4-6

4-16

CONTENTS (cont)
Chapter

Page

4.6.1

Registers

4-19

4.6.2

Instructions

4-20

4.6.3

Programming

4-21

CHAPTER 5 INPUT/OUTPUT BUS DESCRIPTION

5.1.1

Programmed Data Transfers and I/O Control
Timing and lOP Generator

5.1.2

Device Selector (DS)

5-7

5.1.3

Input/Output Skip (lOS)

5-8

5.1.4

Accumulator

5.1.5

Input Data Transfers

5- 1

5.1.6

Output Data Transfers

5-11

5.1.7

Program Interrupt

5-11

5.2

Multi-Level Automatic Priority Interrupt

5-15

5.2.1

Interrupts

5-15

5.2.2

Push

5-15

5.2.3

Restore-"POP"(REST-IOT6771)

5-16

5.2.4

Vectoring

5-16

5.2.5

Maintenance Logic

5-17

5.2.6

Programming

5-18

5.2.7

Programming Restrictions

5-19

5.2.8

Instruction List

5-19

5.2.9

DM12

5-20

5.3

Data Break Transfers

5-21

5.3.1

Single-Cycle Data Breaks

5-22

5.3.2

Input Data Transfers

5-22

5.3.3

Output Data Transfers

5-23

5.3.4

Memory Increment

5-27

5.3.5

Three-Cycle Data Breaks

5-29

5.4

Interface Design and Construction

5-30

5.4.1

PDP- 1 2 Interface Modules

5-30

5.4.2

M Series Flip Chip Modules

5-34

5.4.3

Construction of Interfaces

5-39

5.4.4

lOT Allocations

5-43

5.4.5

Interface Connections

5-44

5.1

5-4
5-6

5-9

CHAPTER 6 PERIPHERAL DEVICES
Introduction

6-1

6.1

Teletype

6-3

6.1.1

6-3

6.1.4

Model 33 ASR
Model 33 KSR
Model 35 KSR
Model 37 KSR

6.1.5

Teletype Controls

6-4

6.2

Real Time Clocks

6-18

6.2.1

Real Time Interface, Type

6.2.2

KW12-B and KW12-C Fixed Interval Clocks

6-25

6.3

Disk Storage

6-27

6.3.1

Random Access Disk File, Types DF/DS32 and DF/DS32-D
Disk Memory System Type RF/RS08

6-27

6.1.2
6.1.3

6.3.2

6-3

6-4
6-4

KW 12-

6-18

6-30

CONTENTS (cont)
Page

Chapter
6.3.3

RK8 Disk Cartridge Memory System

6-38

6.3.4

Disk Software

6-44

6.4

Magnetic Tape

6-45

6.4.1

Automatic Magnetic Tape Control, Type TC58

6-45

6.4.2

Magnetic Tape Transports

6-54

6.4.3

LINCtape Option TCI 2-F

6-57

6.5

Line Printers

6-59

6.5.1

Line Printers and Control, Type LP 1

6-59

6.5.2

Line Printers and Control, Type LP08

6-60

6.6

Card Readers

6-63

6.6.1

Card Reader and Control, Type CR12

6-63

6.6.2

Optional Mark Card Reader Type CM 1

6-66

6.7

Incremental Plotters

6-68

6.7.1

Incremental Plotter and Control, Type XYl 2

6-68

6.8

Paper Tape

6-71

6.8.1

6-71

6.8.3

High-Speed Paper- Tape Punch and Reader, Type PC 12
High-Speed Paper-Tape Punch, Type PPl 2
High-Speed Paper-Tape Reader, Type PR 12

6.9

Data Buffers

6-73

6.9.1

Data Buffer Type DB12-P, N

6-73

6.10

6-74

6. 1 0.

Power Fail/Restart
Power Failure Option, Type KP 1

6.11

Analog- To-Digital

6-76

6.1 1.1

General Purpose Multiplexed Analog-to-Digital Converter System, Type AFOl-A

6-76

6.12

Digital-To- Analog

6-82

6.12.1

Digital- to- Analog Converter, Type AAOl -A

6-82

6.8.2

6-7

6-72

6-74

CHAPTER 7 PROGRAM LIBRARY
7.1

PDP- 12 Programs

7.1.1

LAP 6 - DIAL Display Interactive Assembly Language (DEC- 2-SE2D-D)

7.1.2

Peripheral Interchange Program (PIP)

7-3

7.1.3

QUANDA(DEC-12-FISA-D)

7-3

7.1.4

7-3

7.1.6

DATAM (DEC-L8-FDAA-D)
GRAPHA (DEC-L8-UGAA-D)
FRQANA (DEC-L8-FANA-D)

7.1.7

MAGSPY(DEC-12-UZSA-D)

7-3

7.1.8

COMPAR (DEC-L8-EUCA-D)

7-3

7.1.9

7-3

7.1.10

SEARCH (DEC-L8-EUSA-D)
CONVERT (DEC- 12-ESYB-D)

7.1.11

MARK

7-4

7.1.12

7-4

7.1.15

L8SIM(DEC-12-SI1B-D)
FRED (DEC- 12-FZFA-D)
PRTC 1 2-F (DEC- YI Y A-D)
SIGAVG/SINPRE (DEC-1 2-UZ 1 A-D/DEC-1 2-UW4A-D)

7.1.16

CATACAL(DEC-12-UW1A-D)

7-4

7.1.17

NMRSIM (Nuclear Magnetic Resonance Simulation) (DEC-1 2-UW5 A-D)

7-4

7.1.18

ADTAPE/ADCON(DEC-12-UW2A-D)

7-5

7.1.19

TISA(DEC-12-UW3A-D)

7-5

7.1.20

FOCAL 12

7-5

7.2

PDP-8 Programs

7-5

7.2.1

System Programs

7-5

7.1.5

7.1.13

7.1.14

7-1
1

2 (DEC- 1 2- YITB-D)

7-1

7-3
7-3

7-3

7-4
7-4

7-4

CO^fTENTS (Cont)
'

Chapter

Page

7.2.2

Elementary Function Routines

7.2.3

Utility Program

7-9

7.3

DECUS Program

7-10

7.4

Diagnostic Programs

7-27

7-7

APPENDIX A LINC MODE INSTRUCTIONS

APPENDIX B

8 MODE INSTRUCTIONS

APPENDIX C

I/O BUS INSTRUCTIONS

APPENDIX D 8 MODE PERFORATED-TAPE LOADER
APPENDIX E TAPE MAINTENANCE INSTRUCTIONS
E.l

General

E-1

E.2

Tape Maintenance Instructions

^"^

E.2.1

JOT 6141

E-1

E.2.2

E-2

E.2.3

IOT6152
IOT6154

E.2.4

lOT 6 154 Detailed Transfer Information

E-3

E-2

APPENDIX F TABLE OF CODES
E-

F.5

Model 33/35 ASR/KSR Teletype Code
Model 33 ASR/KSR Teletype Code in Binary Form
LT-37 Transmit and Receive Code Table
Card Reader Codes
LP08 Line Printer Code

F,6

LP 12 Automatic Line Printer Code

E-7

F. 1

F.2
F.3

F.4

E-2
E-3
E-5

E-^

APPENDIX G CABLE CONNECTIONS TO PDP-12 FRONT PANEL

APPENDIX H MATH DATA

INDEX

TABLES

Table No.

Page

Title

2-1

Central Processor Register Indicators

2-3

2-2

Central Processor Major State Indicators

2-3

Central Processor Miscellaneous Indicators

2-3

2-4

Tape Processor Major State Indicators

2-4

2-5

Tape Processor Miscellaneous Indicators
Function of Computer Consoel Keys

2-6

2-4
2-5
,

2-7

Toggle Switch Registers

2-7

2-8

Individual Console Toggle Switches

2-7

2-9

Analog Knobs and Power Switch Panel

2-9

2-10

Relay and Analog Input Panel

2-11

VR 2 Display Scope Controls

2- 1

2-12

TU5 5 Tape Transport Controls and Indicators

2-12

2-13

Teletype Model 33 ASR Controls

2-14

3-1

ASR-33 Character Set Display Pattern

3-34

4-1

2-9

Summary of Addressing Methods in 8 Mode

4-4

5-1

Stack Register

5-16

M Series Module Summary

^'^^

5-3

Cable Connections to the PDP- 12 I/O Bus

^^^

6-1

6-10

6-4

PT08 Specifications
PT08 Device Codes
DC02-E Specifications
DF32 Instructions Compared with RF/RS08 Instructions

6-35

6-5

Input Signal Scaling

6-77

6-6

System Conversion Characteristics

6-79

A-1

LINC Mode Instructions
8 Mode Memory Reference Instructions
8 Mode Group
Operate Microinstructions
8 Mode Group 2 Operate Microinstructions
8 Mode Extended Arithmetic Element Microinstructions
lOT Instructions

A-1

6-2
6-3

B-1

B-2
B-3

B-4
C-1

6-11

6-14

B-1

B-3

B-4
C-1

E-2

AC Bit Functions
AC Bit Functions

E-3

lOT 61 54 Effect of Tape Maintenance Instructions

E-2

E-4

Tape Maintenance Instruction Register Equals 1 Og

E-3

E-5

Tape Maintenance Instruction Register Equals 1

E-4

E-6

Tape Maintenance Instruction Register Equals 1 28

E-4

E-7

Tape Maintenance Instruction Register Equals ISg

E-4

E-8

Tape Maintenance Instruction Register Equals Kg

E-5

E-9

Tape Maintenance Instruction Register Equals 158

E-5

F-

Model 33/35 ASR/KSR Teletype Code (ASCII) in Octal Form
Model 33 ASR/KSR Teletype Code (ASCII) in Binary Form

F-

E-1

F-2

E-1

E-2

F-2

TABLES (cont)
Table No.

Title

Page

F-3

LT-37 Transmit and Receive Code Table

F-3

F-4

Card Reader Codes

F-5

LP08 Line Printer Code
LP 12 Automatic Line Printer Code
Cable Connections for PDP- 1 2 Front Panel

F-6

G-

F-7

G-2

ILLUSTRATIONS

Figure No.

Frontispiece
1 -

Title

PDP- 1 2 Program Data Processor
PDP- 1 2 Functional Block Diagram

Page

-2

2-2

PDP- 1 2 Operator Console
Analog Knobs and Power Switch Panel

2-3

Relay and Analog Input Panel

2-10

2-4

2- 1

2-6

Type VR 2 CRT Display
TU5 5 Tape Transport Control Panel
Teletype Model 33 ASR

3-1

Assignment of LINC Address within Memory

3-1

3-2

Direct Address Instruction Format

3-3

j3-Class Instruction Format

3-4

jS-Class Format

3-6

3-5

a-Class and Non-Memory Reference Format

2-5

2-8

2-11

2-13

3-6

Rotate Left

3-17

3-7

Rotate Right

3-17

3-8

Scale Right

3-18

3-9

QAC Transfer Path

3-22

3-10

Data Path: IB, IF, DF, and AC

3-27

3-1

Data Path, RMF Instruction

3-28

3-12

Special Functions

3-29

3-13

CRT Grid

3-31

3-14

Display Pattern for DSC

3-33

3-15

Relay Terminals and Corresponding AC Bits

3-36

3-16

Standard LINCtape Format

3-38

3-17

LINCtape Processor Information Paths

3-40

3-18

3-41

3-19

LINCtape Instruction Format
Extended Operations Buffer Bit Assignments

4-1

Organization of Memory, 8 Mode

4-2

Memory Reference Instruction Format

4-3

4-7

Group I Operate Class Instruction Format
Rotation Scheme for RAR, RTR, RAL, RTL
Group II Operate Class Instruction Format
EAE Instruction Format
Shift Path for NMI, SHL

4-8

Shift Path for

ASR

4-16

4-9

Shift Path for LSR

4-16

4-10

Data Path to SF and AC

4-20

5-1

Logic Symbols

5-3

5-2

lOT Instruction Decoding
Programmed Data Transfer Interface Block Diagram

5-4

4-4
4-5

4-6

5-3

3-45

4-8

4-10
4-13
4- 1

5-5

ILLUSTRATIONS (cont)
Figure No.

5-4

Title

Page

5-5

Programmed Data Transfer Timing
Generation of lOT Command Pulses by Device Selectors

5-7

5-6

Typical Device Selector

5.3

5-7

Use of lOS to Test the Status of an External Device

5-8

Accumulator Input or Output

5-6

5-9

5-10

5-9

Loading Data into the Accumulator from an External Device

5- 1

5-10

Loading a Six-Bit Word into an External Device from the AC

5-12

5-1

Program Interrupt Request Signal Origin

5-12

5-1

Multiple Inputs to lOS and PI Facilities

5-13

Illustration of I*ush and POP Operations

5. 13

5-14

Vector Flow Diagram

5.17

5-15

DM12 Cable Diagram

5.20

5-16

Data Break Transfer Interface

5-21

5-17

Single-Cycle Data Break Input Transfer Timing

5-23

5-18

Device Interface Logic for Single-Cycle Data Break Input Transfer

5-24

5-19

Single-Cycle Data Break Output Transfer Timing

5-25

5-20

Device Interface Logic for Single-Cycle Data Break Output Transfer

5-26

5-21

Memory Increment Data Break Timing

5-27

5-22

Three-Cycle Data Break Timing

5-29

5-23

Typical Mill /M906 Positive Input Circuit

5-3

5-24

Typical M5 1 6 Positive Bus Receiver Input Circuit

5-3

5-25

Typical M623/M906 Positive Output Circuit

5-32

5-26

M660 Terminated Bus Driver Output Circuit

5-32

5-27

M 03 Device Selector Logic Circuit

5*33

5-28

Ml 01 Bus Data Interface Logic Circuit

5-34

5-29

I/O Bus Configuration

540

5-30

I/O Cable Connections

541

6-1

Relationship Between Paper Tape and Accumulator

6-3

6-2

Punched Paper Tape Format for the Number 4

6-4

6-3

6-13

6-5

PT08 Equipment Configurations
PT08 Program Response Time
KW 1 2-A Real Time Interface

6-18

6-6

KW 2-A Organization

6- 1

6-7

Simplified Input Synchronizer Logic Diagram

6-20

6-8

KW 2-A Timing Diagram

6-2

6-9

Automatic Restart Program Events

6-75

6-1

Typical Power Failure Program Service Routine

6-75

6-4

6-11

FDP-12 Fnograinmed Data Processor

CHAPTER 1
GENERAL DESCRIPTION

1.1

DESCRIPTION

1.1.1

System

The PDP-12 (Programmed Data Processor-12) is a versatile digital computer which includes within its single central
processor two distinct operating modes, each with its own complete instruction set. This versatility of the PDP-12

makes it, on the one hand, a laboratory-oriented machine with several built-in facilities for input/output, auxiliary
storage, and control and sensing of external equipment; and on the other hand, a general-purpose computer with a
flexible input/output capability to which numerous peripheral devices may be easily attached. The central
processor logic is fully parallel, using a basic word length of 12 bits. The processor cycle time is 1.6 microseconds
±20%; most instructions require from 1 to 3 cycles for execution.
Like its predecessor, the LINC-8, the PDP-12 operates in one mode as a LINC (Laboratory Instrument Computer)

and in the other mode as a PDP-8 computer - specifically, a PDP-8/I. Unhke the LINC-8, however, the PDP-1 2 has
one central processor, and both operating modes have equal status. (In the LINC-8, the LINC mode was
subordinate to the PDP-8 mode.) The computer may be stopped and started in either mode, and programs may
switch from one to the other at will. Computations in one mode are immediately available to programs operating in
the other mode because only one set of processing registers is involved.

The PDP-12 is offered in three configurations, A, B, and C, in order of decreasing capabihty. The two smaller
systems, B and C, are expandable into the A configuration. The system discussed in this handbook is the PDP-1 2A.
The capacity of basic core memory storage in the PDP-12 is 4096 (4K) 12-bit words which can be expanded to
32,768 (32K) 12-bit words.

Figure 1-1 shows a system block diagram with many of the options and peripherals available, such as:

LINCtape —

Two TU55 tape transports or one TU56 dual drive transport controlled by a
buffered subprocessor

CRT Display —

6" x 9" screen, two intensification channels

Analog Inputs —

Eight external inputs, eight variable potentiometers

Relay Buffer —

Six relays for control of external equipment
1-1

*>.l

*v*

•

H tj

E°

r
I

Q
o
o

S
,,

i_
Ph

1-2

The PDP-12 is also equipped with a positive-logic, PDP-8/I-type, input/output (I/O) bus which can be used for
interfacing all 8-family peripherals and options, as well as the standard Teletype® Model 33

ASR.

1.1.2 Central Processor

The central processor contains all the logic and registers required to carry out the functions of both operating
modes of the PDP-1 2. The central processor can best be described in terms of its active registers:

Accumulator (AC) 12 Bits

This

contains

data

being

operated

upon.

Its

may be shifted or rotated right or left; incremented, cleared, or complemented; stored in memory or
added to the contents of a memory register; and logically
contents

arithmetically

compared with the contents of any

memory register. The AC holds the sum after an addition,
and part of the product after a multiplication. The AC is
also involved in the transfer of data to and

from various

other registers outside the central processor.

Link (L) 1 Bit

The Link is an extension of the AC. When a carry occurs
out of ACqo during a 2's complement addition, the Link is

complemented. It may be set or cleared independently of
the

AC under 8 mode control, and may or may not be

included in shifting and rotating operations performed on
the contents of the AC.

Program Counter (PC) 12 Bits

This register contains the address of the next instruction to

memory field selected by the
Instruction Field Register (see below J. In 8 mode, the PC

be executed within the
acts as a

2-bit counter; in

LINC mode, it acts as a 1 0-bit

counter.

Instruction Register (IR) 12 Bits

This register contains the complete binary code of the
instruction being executed.

Memory Address Register (MA) 12 Bits

This register contains the address for memory references.

Whenever a core memory location is being accessed, either
for reading or for writing, the

MA contains the address of

that location.

Memory Buffer (MB) 12 Bits

All

information

registers

the

passing between memory and other
PDP-12 must go through the Memory

Buffer Register, whether the transfer involves the central
processor,

an external I/O device, or another

memory

Mode Status Register 1 Bit

This register indicates the current operating mode (LINC
or 8) of the central processor.

® Teletype is the registered trademark of the Teletype Corporation.
1-3

Instruction Field Register (IF) 5 Bits

This

selects

executable program.

the
In

memory field containing the
LINC mode, it is used to

the

designate one of up to thirty-two

024-word segments. In

the 8 mode, the three high-order bits of the IF are used to

designate one of up to eight 4096-word fields.

Data Field Register (DF) 5 Bits

This register selects the memory field containing data to be
indirectly accessed

by the memory reference instructions

of a program. The fields are specified in each mode in the

same way that the IF specifies the Instruction Field.

Memory

1.1.3

The principal unit of core memory is a module of 4096 (4K) 1 2-bit words. Additional modules of 4K words may
be added, up to a total of eight, or 32,768 words. Within each module, the logical organization of memory depends

on the operating mode. In the LINC mode, each module is divided into four 1024-word segments. At any given
time, only two of these segments are active: the Instruction Field, which contains the executable program and the
directly accessed data; and the Data Field, which contains only indirectly accessed data. Absolute addresses may be
assigned and changed at will using the IF and DF described above.
In the 8 mode, the memory field (a 4K module) is divided into 32 pages of 128 words each. Within a single page,

data

may be accessed directly; between pages, indirect addressing must be used. If more than 4K of memory is

provided, the IF and DF registers specify the active fields.

1.1.4 Operating Modes

The two operating modes, LINC and 8, are independent of each other, though they can be combined and
intermixed vdthin a program. The user can run programs from the already-existing libraries for the 8 family of
computers, including the LINC-8. By using the I/O Handler (LINC-8 Simulator Trap Processor) program provided
with the PDP-12 basic software, most programs written for the LINC-8 can be run without modification. (Some

LINC-8 programs may require slight changes.) A complete software system designed for the PDP-12 allows the
programmer to assemble coding for either or both modes in a single program.

LINC Mode - In this mode, the instruction set of the classic LINC computer is implemented. In addition, several
new provisions are available:
Extended Tape Addressing - This allows the programmer to transfer information between LINCtape and any
section of core, removing the restriction of data transfer to only specific segments of a given memory field. Other
features include:

Tape Interrupt, which connects the tape processor status to the Program Interrupt.

No-pause, which permits the central processor to resume operation after initiating a tape transfer without

waiting for completion.

Hold-motion, which allows a unit to remain in motion after it has been deselected.

I10 Bus Access — In

LINC mode the user has immediate access to those devices activated by LINC instructions:

analog inputs. Display, Relays, Sense Lines, and LINCtape. Devices connected to the I/O bus may be directly

LINC mode programming by means of a special two-word instruction, in which the second word
enables the bus and initiates the PDP-8 lOT timing chain. This second word is interpreted as a standard PDP-8 lOT
instruction, but the program continues to operate in LINC mode.
accessed from

1-4

Special Functions — The LINC programmer may, by setting certain flip-flops,

Change the size of characters displayed on the CRT;

Enable the program trap, which intercepts certain LINC instruction codes;

Disable interrupts from the ASR-33;

Speed the sampling of analog inputs;

Clear the PDP-12 I/O status by generating an I/O PRESET pulse.

8 Mode - In this mode, the user has available the entire PDP-8/I instruction set.

Interaction

Between Modes - The user may switch from one mode to the other at will. In the LINC mode,

PDP causes the processor to change immediately to 8 mode operation, and all
subsequent instructions are interpreted as PDP-8/I instructions. To switch from 8 mode to LINC mode, the lOT

execution of the instruction
instruction LINC is used.

1.1.5

Input/Output Facilities and Display

There are two main paths for the transmission of data from the central processor or memory to peripheral devices.

One path, which is controlled by LINC mode programming, leads to the CRT display, LINCtape, A-D converter,
and relays. The other path, which is the I/O bus, leads to the ASR-33 and to a large number of optional devices,
such as plotters, high-speed paper tape, magnetic tape, A-D, and card readers, disk storage, and line printers.

- The Cathode Ray Tube has a 58.5-square-inch (6.5 x 9 inches) screen, on which individual points and
whole characters may be displayed. The unit has two selectable channels, controlled by programming and by a
switch on the display. Characters are plotted on a 4-point x 6-point matrix; a full character can be displayed with

Display

two instructions. Provision is made for displaying two sizes of characters.
Data Terminal

— A Data Terminal provides a flexible means of receiving analog inputs and controlHng the

operation of external equipment not internally interfaced to the PDP-12.

Analog Inputs

— Sixteen analog inputs feed a 10-bit A-D converter. A single LINC mode instruction

samples any one of the 1 6 channels. Eight of the inputs are taken from phone jacks mounted on the Data

Terminal Panel and fed through preamplifiers to the converter. The remaining eight are taken from
continuously variable

0-tum potentiometers which are also mounted on the panel. A second set of 1

channels, with preamplifiers, may be added to the basic facility.

Relay Buffer — Six relays, mounted on the data terminal panel, can be switched individually or in
combination, by means of a LINC mode instruction. The relays may be used to start and stop operations
in external equipment. The states of the relays can be read into the AC.

Auxiliary Scope Connector — A connector mounted on the Data Terminal Panel is wired to accept an
auxiliary CRT for displaying information. All display information (X,

Y and Z) available to the internal

display is also available at the remote connector.

Sense Lines - These 12 digital sense lines may be individually tested with a LINC mode instruction.

LINCtape — Two TU55 transports (or one TU56 dual drive transport) are controlled by a fully-buffered tape
processor; once initiated

by the LINC program, tape operations are carried out independently of the central

processor. Tapes normally are written and read in standard LINCtape format, though nonstandard formats may be
used.

A special hardware option, TCI2-F, permits the use of tapes with a different format, such as PDP-8 DECtape.

In addition to the basic

LINCtape commands, the PDP-12 also includes an Extended Operations facility, which
1-5

allows, among other features, the transmission of data between tape and any program-defined area of memory, and

the addition of TU55 transports to a total of eight (or four dual drive TU56s).

InputI Output (I10) Bus - This connecting facility provides the control and data transmission path between the
central processor and any peripheral device attached to the bus. Some devices, such as paper tape readers and
punches, hne printers, and incremental plotters, transfer data via the accumulator (AC). Others, including magnetic
tape and disk, use the three-cycle or single-cycle Data Break for direct memory access. The I/O bus uses positive
logic and accepts peripherals used with the 8 family of computers. The processor is prewired to accept the

following I/O bus options:

Extended Arithmetic Element (EAE), Type KE12

Programmable Real-time Clocks, Type KW12-A, B, or C
Incremental Plotter and Control, Type XY12

TTY/Dataphone®, Type DP12-A, B
Converter, many other devices

With the inclusion of the BA12 Peripheral Expander and the DW08A I/O and Bus
of higli-speed paper tape reader
can be added to the PDP-12 I/O bus. The Peripheral Expander allows the addition
Bus Converter provides for the
The
interfaces.
communication
and punch, card reader, Une printers, and optional
and associated multiplexers
converters
A/D
and
storage
addition of disk and IBM-compatible magnetic tape
designed for the negative-logic PDP-8 I/O Bus.

the user and the

Key board/Printer (Model 33 ASR) - An important means of direct communication between
of the PDP-12. It is
operating program is the Model 33 ASR Keyboard/Printer, standard on all configurations
mode. The
operating
either
in
programs
output
by
or
input
for
accessed
to the I/O bus, and can be
connected

and

Model 33 ASR is equipped with paper tape reader and punch; the reader and keyboard use the same input path
maximum transfer rate in
instructions, while the printer and punch use the same output path and instructions. The
either direction is 10 characters per second.

The Model 33 ASR operates

full-duplex

mode, that

data

may

be transmitted

both directions

simultaneously.

1.2

SYMBOLS AND ABBREVIATIONS

The following symbols and abbreviations are used throughout this handbook:
AC, MB, PC, MQ, MA, L, IF, DF, IR

Central Processor registers: Accumulator, Memory Buffer,

Program Counter, Multiplier Quotient, Memory Address,
Link, Instruction Field, Data Field, Instruction Register.

General representation of any register.

C (R)

The contents of register R.

C (Rj)

The content of bit j of register R.

C (Rj.n)

The contents of bits j through n, inclusive, of register R.

® Dataphone is a registered trademark of A.T.&T.
1-6

C(Ri)

The contents of the left half of register R.

C(Rr)

The contents of the right half of register R.

C(R)

The one's complement of the contents of register R.

The effective address of an operand.

The Indirect address bit of an instruction. In the LINC
mode, I represents bit 7; in the 8 mode, bit 3.

C (R)^C (S)

The contents of register R replace those of register S.

N^C (R)

The quantity N replaces the contents of register R.

Inclusive

-v-

Exclusive OR

AND

1-7

CHAPTER 2
CONTROLS AND INDICATORS

This chapter describes the function of the controls and indicators of the PDP-12 computer console, Data Terminal,

Type VR12 CRT Display, Type TU55 LINCtape Transport, and Teletype Model 33 ASR.
2.1

PDP-12 CONSOLE CONTROLS AND INDICATORS

Tables 2-1 through 2-8 describe the controls and indicators located on the console of the PDP-12. Figure 2-1
provides a front view of the console.

2.2

DATA TERMINAL

The Data Terminal is the area behind the door on the left front of the PDP-12. Normally, up to four separate
panels are placed here. A storage rack to hold LINC tapes may be placed in any of the unused spaces of the Data

Terminal area. The four standard panels are:

Power Switch Panel

Relay and Analog Input Panel

Analog Extension Panel

Clock Input Panel

The first two are described in Tables 2-9 and 2-10 and illustrated in Figures 2-2 and 2-3; the last two are described
with the associated options (AG 12 and KW12-A).
2.3

CRT DISPLAY, TYPE VR 12

Table 2-1 1

Lists

the controls and indicators of the Type VR12 CRT Display. Figure 2-4 shows a front view of the

CRT Display.
2.4

LINC TAPE TRANSPORT, TYPE TU55

Table 2-12 lists the functions of controls and indicators of the Type TU55 LINCtape transport. Figure 2-5 provides
a front view of the transport.

2.5

TELETYPE, MODEL 33 ASR

Table 2-13 lists the functions of controls of the Teletype, Model 33 ASR. Figure 2-6 provides a front view of the
teletype.
2-1

O
Q
04

2-2

Table 2-1. Central Processor Register Indicators

Indicator

Bits

Table 2-2. Central Processor Major State Indicators

Indicator

State

INST FIELD

Instruction Fetch

DATA FIELD

Deferred Address

RELAYS

Instruction Execution

INSTRUCTION REGISTER

Instruction Execution 2

PROGRAM COUNTER

INT

Program Interrupt

MEMORY ADDRESS

Word Count

MULTIPLIER QUOTIENT

Current Address

ACCUMULATOR

Break

Tape Break

LINK

MEMORY BUFFER

Table 2-3. Central Processor Miscellaneous Indicators

Indicators

Interpretation When Lit

SKIP

Skip Flip-Flop is set

FLO

Overflow Flip-Flop is set

MODE

Processor is in the PDP-8 Mode

LINC MODE

Processor is in the LINC Mode

RUN

Processor is running

AUTO

Auto Restart Flip-Flop is set

TRAP

Trap flip-flop is set

INT PAUSE

An internal pause is occurring

ION

Program Interrupt facility enabled

I/O PAUSE

An I/O Pause is occurring

2-3

Table 2-4. Tape Processor Major State Indicators

Indicator

State

Idle

Block

Check Word

Turn Around

Table 2-5. Tape Processor Miscellaneous Indicators

Indicator

Interpretation

Function

In Progress

Indicates that a tape operation is In Progress.

Extended Address Mode

Indicates that

the Extended

the processor

Indicates that the processor

in the

Address mode.

No Pause Mode

No Pause

mode.

Mark Flip-Flop

Indicates that the Mark Flip-Flop is set.

TAPE INST

3-bit Tape Instruction Register

These three lights indicate the contents of the 3-bit

Tape Instruction register.

2-4

Table 2-6. Function of Computer Console Keys

Key
I/O PRESET

Function

This switch causes the processor to halt

when it is in Internal Pause state

during a tape instruction, and sets processor mode to the state of the console

MODE switch. The Inst Field register is set to 2 and the Data Field register is
set to 3.

I/O PRESET pulse and the I/O BUS INITIALIZE pulse clear all I/O

device flags and operations. The AC and Link are cleared.

This switch causes the processor to perform one instruction. In the LINC

mode, the processor performs the instruction defined by the Left Switches
(and the Right Switches, if it is a double word instruction). In the 8 mode,
the processor performs the instruction defined by the Left Switches.

START 20

This switch causes the processor to start at location 20 of the currently
selected Instruction Field.

START 400

This switch causes the processor to start at location 400 of the currently
selected Instruction Field.

START LS

This switch causes the processor to start at the 15-bit address specified by
the Left Switches and the Instruction Field Switches.

CONT

EXAM

This switch causes the processor to resume operation.

The contents of the Left Switches are transferred into the Memory Address
The contents of the absolute core address designated by the Left

Switches are displayed in the Memory Buffer register.

STEP EXAM

This switch increments the contents of the

Memory Address register and

displays the contents of this new address in the Memory Buffer register. This

incrementing extends over 10 bits in LINC mode and 12 bits in 8 mode.

FILL

The contents of the Left Switches are transferred into the Memory Address
The contents of the Right Switches are deposited into the memory
location whose absolute address is designated by the Left Switches and the
register.

Instruction Field switches.

FILL STEP

Depressing this switch causes the contents of the Right Switches to be
deposited into the memory location whose address is in the Memory Address
register.

Memory
LINC mode

Releasing this switch increments the contents of the

Address register. This incrementing extends over 1
or 12 bits in the 8 mode.

bits in the

The Memory Buffer register then displays the
new contents of the Memory

contents of the location specified by the

Address register.

MODE

This switch determines the mode (LINC or 8) to which the processor will be
set

when the 1/0 PRESET switch is activated. The MODE switch is effective

only when the computer is not running.

2-5

Table 2-6. Function of Computer Console Keys (cont)

Key

Function

AUTO

This switch sets the AUTO RESTART flip-flop if it is held down at the same
time one of the following keys is actuated: STEP EXAM, FILL STEP, DO,
or CONT.

AUTO RESTART

The

flip-flop

causes

the

central

processor

start

automatically at the end of a variable time delay (determined by the console
controls) after the central processor stops for any of the following reasons:
a.

SING STEP switch activated

FETCH STOP address match

EXEC STOP address match

The end of a STEP EXAM operation

The end of a FILL STEP operation

The end of a DO switch operation

The Auto Restart Flip-Flop is cleared by any of the following conditions:
a.

STOP switch pressed while processor is running

DO, FILL STEP, or STEP EXAM switch activated and the AUTO

switch not pressed

A processor HLT instruction executed (either mode)

I/O PRESET pulse is generated

To start a program in AUTO RESTART mode:
a.

Start the program with the SING STEP switch up.

With the AUTO key depressed, depress CONT.

2-6

Table 2-7. Toggle Switch Registers

Bits

Function

LEFT SWITCHES

These switches form a 12-bit word which can be
read into the accumulator with the LINC mode
instruction LSW (517). This word also specifies the

address to be examined when the

EXAM switch is

used, the address into which data will be placed

when the FILL switch is used, the stopping address
for EXEC STOP and FETCH STOP functions, and
the instruction to be performed when the DO
switch is used.

RIGHT SWITCHES

The contents of these switches form a 1 2-bit word
which can be read into the accumulator with the

LINC mode instruction RSW (516) or the 8 mode
instruction

OSR (7404). This word also provides

data to be stored in memory

when the FILL or
FILL STEP switches are used. When the DO switch
is

used,

the

Right Switches contain the second

word of two-word instructions.

INST FIELD

These

are

high-order

extension

of the

Left

Switches. They provide addressing information for

systems equipped with 8K or more of memory for

EXAM, FILL, START LS, EXEC STOP, and
FETCH STOP functions.
the

SENSE SWITCHES

These

switches are individually interrogated

LINC mode

skip

instructions,

thereby enabling

console control of program branching.

Table 2-8. Individual Console Toggle Switches

Switch

STOP

Function
This switch causes the processor to stop at the end of an instruction. For the
purposes of the STOP switch. Traps, Interrupt, Tape Break, and single-cycle

Data

Break

are

considered

single-cycle

instructions.

During

three-cycle Data Break, the processor is stopped after the Break cycle.

SING STEP

RUN flip-flop to be cleared, thereby disabling the
timing circuits at the end of one cycle of operation. Thereafter, repeated
operation of the CONT switch steps the program one cycle at a time so that
This switch causes the

the operator can observe the contents of registers in each major state.

FETCH STOP

This switch causes the processor to stop when the address designated by the
Left Switches matches the current address in the Memory Address register

during the Fetch cycle. For systems with more than 4K of memory, the Inst
Field switches designate the three most significant bits of the address.

2-7

Table 2-8. Individual Console Toggle Switches (cont)

Function

Switch

EXEC STOP

This switch causes the processor to stop when the address designated by the
Left Switches matches the current address in the Memory Address register

during any computer cycle except a Fetch cycle. For systems having more

than

of memory,

the

Inst

Field switches designate the three most

significant bits of the address.

AUTO RESTART DELAY

ANALOG CHANNELS 0-7

COARSE
2

FINE
t

SPEAKEt^ VOLUME

MtSK

tow

/
ON

OFF

|P|^

LOCK

Figure 2-2. Analog Knobs and Power Switch Panel

2-8

Table 2-9. Analog Knobs and Power Switch Panel

Panel Controls

OFF/ON/LOCK

Function

This 3-position, key-locking switch is used to turn the PDF- 12 on as well as
console intervention during an operating program. When fully
counterclockwise, the PDF- 12 is off. When turned to the center position, the
inhibit

PDF- 12

When the switch is fully

turned on and the console activated.

PDP-12 is on, but console control functions are totally
inhibited while the PDP-12 RUN light is on. Only the Left Switches, Right
clockwise,

the

Switches, and Sense Switches remain operative.

SPEAKER VOLUME

The volume of the speaker is controlled by this knob. (The speaker, which is
driven by AC bit 0, is added to the system when the

AD 12 is included in the

system configuration.)

AUTO RESTART DELAY

These two knobs control the delay period of Auto Restart after a processor
stop due to an EXEC STOP, FETCH STOP, or SING STEP operation. (See

AUTO switch description in Table 2-6.)
COARSE and FINE

The COARSE delay selects overlapping ranges from 2.4 ^s to .38 sec. The

FINE control gives variation within a range of 20:

of the selected COARSE

delay.

ANALOG CHANNELS 0-7
(knobs)

These 10-turn potentiometers are connected to analog input channels 0-7 of
the AD 12 Analog-to-Digital Converter. These knobs therefore provide eight
continually-variable parameters within the range of ±5 12^0

for program

usage.

Table 2-10. Relay and Analog Input Panel

Terminals

Function

ANALOG CHANNELS 10-17

These are 3-conductor phone jacks providing ± 1 Volt input connections for

(Input Jacks)

AD 12 Analog-to-Digital converter channels lOg-Hg.

RELAY REGISTER

One set of form C contacts for each of the six system relays is available at

Contacts

the binding posts.

EXTENSION SCOPE

A 24-pin connector for an extension scope provides for remote operations,
multiple displays, or photographing of display output. See Appendix G for
pin connections and drive characteristics.

2-9

Figure 2-3. Relay and Analog Input Panel

Figure 2-4.

2-10

Type VR 1 2 CRT Display

Table 2-11.

Control

VR12 Display Scope Controls

Function

CHANNEL

Selects one or both channels for scope display.

BRIGHTNESS

Controls level of brightness.

X GAIN

Controls horizontal size of display.

X POS

Controls horizontal position of display.

Y GAIN

Controls vertical size of display.

Y POS

Controls vertical position of display.

Figure 2-5.

TU55 Tape Transport Control Panel

2-11

Table 2-12. TU55 Tape Transport Controls and Indicators

Function

Control or Indicator

Forward Tape-motion
(designated in

Figure

2-5

Switch
by arrow

pointing to the left)

Provides forward tape motion

(i.e.,

from right to

left) only if REMOTE/OFF/LOCAL switch is set

to LOCAL.

WRITE ENABLED/WRITE LOCK switch
WRITE ENABLED

Permits TCI 2 control system to write information

on the TU55.

WRITE LOCK

WRITE ENABLED

control system is
writing.
If TCI 2
commanded to write on tape while the WRITE
LOCK is set, the control signals a TAPE NOT OK.

Prevents

when

Lights

WRITE ENABLE/WRITE LOCK

switch is in the WRITE ENABLE position.

Unit Selector

When this selector is dialed to one of the numerals

REMOTE/OFF/LOCAL switch is set to
REMOTE, the central processor may gain access to
and the

the unit.

2
3

4
5

6
7

OFF LINE

When

the

selector

dialed to

OFF LINE, the

transport cannot be selected by the tape control.

NOTE
Some earlier units were equipped with a unit
selector position 8, which is the same as unit
0.

REMOTE/OFF/LOCAL Switch

REMOTE
OFF

Permits tape processor to control the transport.

Removes power from reel motors and releases the
brakes. This permits the operator to change the
tape.

2-12

Table 2-12.

TU55 Tape Transport Controls and Indicators (cont)

Control or Indicator

Function

LOCAL

Permits

the

forward

and

reverse

tape-motion

switches to provide tape motion in direction of the
arrows. The transport cannot be selected.

REMOTE Indicator

Lights only when transport is selected by the tape
processor.

Reverse

Tape-motion

(designated in

Switch

Figure 2-5 by arrow

pointing to the right)

Provides for motion in the reverse direction (i.e.,
from left to right), but only when REMOTE/OFF/

LOCAL switch is on LOCAL. If both reverse and
forward tape-motion switches are pressed simultaneously, reverse motion takes place.

Figure 2-6. Teletype Model 33 ASR

2-13

Table 2-13. Teletype Model 33 ASR Controls

Function

Control

Punch Controls

REL Pushbutton

Disengages the tape in the punch to allow removal
or loading.

B SP Pushbutton

Backspaces

the

manual

allowing

tape

the

correction

punch one
or

space,

rubout of the

character just punched.

ON and OFF Pushbuttons

ON engages the punch for operation under local or
program control. OFF removes the punch from
control.

Reader Control

START/STOP/FREE

In the FREE (lowest) position, the tape feed wheel
is

disengaged, and tape can be loaded or unloaded.

In the STOP (center) position, the wheel is engaged

but the reader cannot be operated. In the START
(highest) position, the reader can be operated
under local or program control.

LINE/OFF/LOCAL Switch

In the LINE position, the Teletype is energized and

connected as an I/O device to the computer. In the
OFF position, the Teletype is not energized. In the

LOCAL position, the Teletype is energized for
off-line

operation, and signal connections to the

processor

disconnected. Both LINE and
of the Teletype require that the

are

LOCAL use

computer OFF/ON/LOCK switch is ON.

2-14

CHAPTER 3
LINC

MODE PROGRAMMING

ORGANIZATION OF MEMORY

3.1

3.1.1

General

The LINC mode instruction set deals with two 1024io-word Memory Fields. The INSTRUCTION FIELD is the
1024io-word section of memory from which programs
indu-ectly accessed.
set allows

are executed, and in which data may be directly or
The DATA FIELD is a second 1024^0 -word section of memory to which the LINC instruction

only indirect reference for data manipulation and storage. The physical locations of the Data Field and

maximum 32,768jo-word memory are specified by the contents of the 5-bit Data
Field Register and the 5-bit Instruction Field Register. These are set and modified under program control or from
Instruction Field within the

the console; they need not be adjacent, or in any particular order, and can even be identical. With respect to a

LINC program, addresses within a Field remain constant, regardless of the actual location of the Field. Addresses
within the Instruction Field are 0000 through Xlll^; addresses within the Data Field are 20008 through 3111^.
Thus, no matter where they are assigned, the two fields may be considered logically contiguous.

The PDP-8 instruction set (described in Chapter 4) divides memory into 4096io-word Fields, which are specified
by the most significant 3 bits of the Instruction Field and Data Field Registers. Therefore, the term Field
designates a 1024io-word segment of memory in LINC mode, and a
4096i Q-word segment of memory in 8 mode.
In Figure 3-1, the division of the first 4096io words of memory is shown, assuming LINC mode, INST FIELD =
01, DATA FIELD = 03.

ABSOLUTE ADDRESS (OCTAL)
FIELD
LINC ADDRESS ( OCTAL)

0000-1777

2000-3777

4000-5777

INST

0000- 1777

6000-7777
DATA
2000-3777

Figure 3-1. Assignment of LINC Addresses within Memory

3-1

3.1.2 Progra

m Cou nter
programs can be stored only in

The Program Counter acts as a 10-bit counter in the LINC mode, so that executable
beyond 1777, they return to 0000; the two
the Instruction Field. If the contents of PC2-11 are incremented
= 3777 yields C(PC) = 2000. Likewise, 5777 is
high-order bits of the PC are unaffected. Thus, incrementing C(PC)

LINC mode operations.

incremented to 4000, and 7777 to 6000. This 10-bit indexing is very common in
3.1.3

Instruction and Data Field Registers

high-order bits of each
These two 5-bit registers select the IK segments to be used by the LINC program. The three
of the IF and DF may
contents
The
register.
Field
Memory
8
mode
corresponding
the
of
bits
register are the three
instructions.
LINC
of
use
the
by
time
any
at
examined
be set, changed, or
3.1.3.1

Instruction Field Reserved Locations - This field contains the executable program. The following registers

are set aside in this field for special uses:

Use

Field Address

0000

Holds return address after execution of JMP.

0001

Holds horizontal coordinate during execution of

DSC.
0001-0017

jS-registers,

instructions

used

indirect-reference

hold the effective address of an

operand.

0000-0017

As a-registers, used by SET, XSK, and DIS,

0020

Program

start

location

when

Start

20 key

start

location

when

Start

400 key

pressed.

0400

Program
pressed.

When the instruction field is assigned to the lowest segment of memory (that is, when C(IF) = 00), the following
registers are also reserved:

Use

Field Address

0000
0001

PDP-8 Interrupt locations (Paragraph 4.4)

0040

Holds return address after a program interrupt
during LINC mode operation.

0041

Location to which control

transferred after a

program interrupt during LINC mode operation.

0140
0141

Holds return address after an instruction trap.
Location to which control is transferred after an
instruction trap.

3.1.3.1

Data Field Reserved Locations - There are no specially-reserved registers in this field. Its contents cannot

be accessed directly; data can be stored or retrieved only by indirect addressing.

3-2

3.2

MEMORY ADDRESSING METHODS

3.2.1

General

Almost every program, at some time during its execution, will need an item of data stored in memory. Such an
operand can be obtained only by specifying the address of the register in which it is stored or to be stored. An
instruction which requires a reference to memory can designate the desired location in two ways. It may include

the address of the operand as part of the instruction itself and directly address the location of the operand. Or, the
instruction

may specify the address, not of the operand, but of a register containing the address of the operand,

thus indirectly addressing the data storage register.

The need for indirect addressing is readily apparent; with eleven bits required to specify a Data Field address, not

much is left of a 12-bit word to use for instruction codes. It is necessary to reduce the number of address bits
available within a memory reference instruction, and to use a limited set of directly addressable locations as
pointers containing the effective address of the desired data. The LINC instruction set provides for both types of
addressing.

3.2.2 Direct Addressing

LINC programming, direct access to memory registers is limited to the Instruction Field. A full address in this

two bits for instruction codes. The three instructions, ADD, STC,
and JMP, are described in detail in Paragraph 3.3. The format of a direct-address instruction is shown in Figure 3-2.
field requires ten bits (0000-1777), leaving only

Bits

and 1 are used for the operation code, bits 2-1 1 for the address.

OPERATION
CODE

ADDRESS
A
2

Figure 3-2. Direct Address Instruction Format

3.2.3

Indirect Addressing: jS-Class

For access to registers in the Data Field, an indirect address is required. The instruction specifies one of a small set
of special registers which are used to hold the effective addresses of desired data. The format of these j3-class
instructions

shown in Figure 3-3. Bits 3-6 are available for operation codes; bits 8-11, together with bit 7,

determine which of four addressing schemes is to be used.

3-3

OPERATION
CODE

A
3

Figure 3-3. j3-Class Instruction Format

3.2.3.1

/3-Registers

- In a j3-class instruction, the contents of bits 8-1 1, when not zero, designate one of fifteen

registers at locations

0001-0017 of the Instruction Field. The contents of the specified /3-register are used to

determine the effective address of the operand. When the contents of bits 8-11 are zero, the effective address is

found in the register which immediately follows the referencing instruction.
Bit 7, the 1-Bit, determines the manner in which the register designated by bits 8-11

to be used in locating the

operand. There are four addressing schemes, described in the following table.
Effective Address

Bits 8-11 (jS)

Bit 7 (I)

The

contents

bits

1-1 1

the

immediately following the instruction.

The address of the register immediately following
the instruction. The operand itself is in this
register.

01-17

The

contents

bits

1-11

of the

designated

(3-register.

01-17

The contents, incremented by 1, of bits 1-1 1 of the
designated (3-register. Ten-bit indexing is used (see
text).

In the first scheme, the register

which follows the referencing instruction contains the effective address. In the

second scheme, the operand itself is in that register. When either of these two schemes is used (that is, when the
contents of bits 8-1 1 are zero), the program counter automatically skips over the register immediately following the
instruction, and the next instruction is fetched from the second register following.

The following examples illustrate the use of all four addressing schemes.
The instruction STA (Store Accumulator) causes the contents of the AC to be stored in memory. The operation
code for STA is 1040. The register R is the one which immediately follows that containing the STA instruction.
(1)

STA

Octal code: 1040

C(R)=2345

1=0, i3=00

Destination of C(AC):

3-4

Location 2345 (Location 345 in the Data Field)

(2)

STA

Octal code: 1060

I=l,/3=00

(3)

STA

Destination of C( AC):

Location R

Octal code: 1025

C(0012)=3456

I=0,/3=12

(4)

STA

Destination of C(AC):

Location 3456 (Location 1456 in the Data Field)

Octal code: 1072

C(0012)=3456

I=l,/3=12
Destination of C( AC):

Location 3457 (Location 1457 in the Data Field)

(The contents of )3-register 0012 are incremented

and the result, 3457, is used as the effective

address.)

In the next example, the use of these addressing schemes in a program sequence is demonstrated. The instruction

ADA (Add to Accumulator) adds the operand to the contents of the AC, leaving the result in the AC. The program
sequence starting at location 1000 adds the numbers N^

Nj N3 and N4
,

leaving the sum in the AC.

ADDRESS

OCTAL

CONTENTS

REMARKS

0007

1500

/REPLACED BY 1501 AFTER INDEXING

1000

1100

ADA

/INDIRECT THROUGH 1001, ADD Nl to C(AC)

*1000

1001

1477

/ADDRESS OF Nl

1002

1120

ADA I

/DIRECT TO 1003; ADDS N2 TO C(AC)

1003

3211

1004

1107

1005

1127

N2,

3211

ADA 7
ADA I 7

/INDIRECT THROUGH 7 TO 1500, ADDS N3
/INDIRECT THROUGH 7, INDEXED, ADDS N4

*1477
1477

1234

Nl,

1234

1500

1235

N3,

1235

1501

4321

N4,

4321

3.2.3.2 j3-Register Indexing — When the j3-indexing scheme is used (I = 1, /3 ?^ 00), effective addresses may specify
registers in either memory field,

but the i3-register cannot be incremented from one field to the other. Indexing is

only over ten bits, as it is in the PC; the two high-order bits are unaffected. Thus, the contents of the |3-register will
be incremented from 1777 to 0000, from 3777 to 2000, from 5777 to 4000, and from 7777 to 6000. To change
access from one field to the other, it is necessary to change the contents of bit 1 of the (3-register.

3-5

of the

Bit

jS-register

has no effect in most indirect references, but it does have a special use in half-word

operations, in multiplication, and in character display.
3.2.4 Addressing: a-Class

Three LINC mode instructions - SET, XSK, and DIS - have specialized memory reference schemes. Although each
of them accesses memory in a unique way, all make use of one of the registers in locations 0000 through 0017.

These are called a-registers, to differentiate between these instructions and those of the j3-class.

SET and XSK are described in Section 3.3. DIS is described in Section 3.4.

3.3

LINC MODE INSTRUCTIONS
(Complete list is provided in Appendix A.)
Instruction Formats

3.3.1

There are three basic LINC mode instruction formats.

3.3. 1

3.3.1.2

Direct Address (See Figure 3-2) - This class consists of the three instructions ADD, STC, and JMP.

Indirect Address, (3-class (See Figure 3-4)

— This class consists of 15 |3-class instructions, with operation

codes between 1000 and 1740.

OPERATION
CODE

^
1

r
7

Figure 3-4.

j3-Class Format

3.3.1.3 a-class and Others (See Figure 3-5) — There are 16 basic instructions in this group, and they have operation

codes between 0000 and 0777. Each of these instructions has up to 32 variants, depending on the contents of bits
7-11.

ALL ZEROS

OPERATION
CODE

OPERATION

CODE, a - REGISTER

OR FUNCTION DESIGNATORS
Figure 3-5. a-Class and Non-Memory Reference Format

3-6

Instruction Descriptions

3.3.2

The descriptions are organized according to function and class, as follows:
Full-word Data Transfers
Full-word Arithmetic

STC, LDA, STA
ADD, ADA, ADM, LAM, MUL

BCL, BSE, BCO
SAE, SRO
LDH, STH, SHD

Full-word Logic
Full-word Comparison

Half-word Operations
a-class Operations

SET, XSK

Program Control

JMP

Shift and Rotate

Console Switches

ROL, ROR, SCR
APO, AZE, LZE, QLZ, FLO, SNS,
SXL, KST, SKP, STD, TWC
HLT, CLR, COM, NOP, QAC
LSW, RSW

Mode Control Switch

PDP

I/O Bus Enable

JOB

Skips

Miscellaneous

Memory Address Control

LIF, LDF, lOB/IOTs

Program Interrupt

lOB/IOTs, DJR

Special Functions

ESF, SFA

Instructions related to the Display, Data Terminal, and LINCtape are described in Sections 3.4, 3.5, and 3.6.
In general, the description of each instruction is presented in the following manner:

Mnemonic
Form

Operation Performed

Octal code

Execution time
Operation

The second line shows the general form of the instruction when used in a program. The octal code is that of the
instruction itself, plus the octal value of any other elements which may be present, such as the I-bit or |3-register
bits. (The I-bit, for example, being represented by bit 7, has an octal value of 20

3.3.3

when it is present.)

Full-Word Instructions

3.3.3.1

Full-Word

Data

Transfers

—

These

three

instructions

move complete

12-bit

words between the

Accumulator and Memory.

STC

Store and Clear (Direct Address)

Form:

STC Y

Octal code:

4000+

Execution time:

3.2 /:is

Operation:

Store the contents of the

AC in register Y, then clear the AC. This is a direct address

instruction; Y must be in the Instruction Field.

3-7

LDA

Load Accumulator ( ^-Class)

Form:

LDA

Octal code:

1000 + 20I + i3

Execution time:

4.8 jus; 3.2jus. when I = 1 and i3 = 00

Operation:

Place the contents of register Y, where Y is the address specified by I and C{fi), in the AC. The

previous contents of the AC are lost; the contents of Y are unchanged.

STA

Store Accumulator (^-Class)

Form:

STA I ^

Octal code:

1040 + 201 + j3

Execution time:

4.8 ^s; 3.2 jus. when I =

Operation:

Store the contents of the AC in memory register Y, where Y is the address specified by I and

and i3 = 00

C(i3). The previous contents of

3.3.3.2

Y are lost; the contents of the AC are not changed.

Full-Word Arithmetic - The instructions ADD, ADA, and

result of an addition, a

carried out of bit

of the sum,

ADM use one's complement arithmetic. If, as a

added to the sum. This end-around carry is the

defining property of a one's complement addition. If there is no carry, the sum is left as is.

2435
+ 1704

Example 1:

4341

no carry; sum is left as is.

2435

Example 2:

+5704 (-2073)

^\ 0341

—

end-around carry; 1 added to sum.

0342
In either case, the Link is not affected.

The instruction LAM uses two's complement arithmetic. If a carry from bit
the sum is left unaffected.
1

of the sum occurs, the Link is set to

;

Overflow - In any LINC mode addition, a number is considered to be positive if its high-order bit (bit 0)

3.3.3.2.1

sum of opposite sign, overflow is
is 0, and negative if this sign bit is 1. Whenever two addends of like sign produce a
said to occur. When this happens, the

FLOW flip-flop is set to 1. If no overflow occurs, the FLOW flip-flop is set to

0. Overflow cannot, by definition, occur when the addends have unlike signs. Note that overflow and carry are not

the same thing.

3.3.3.2.2

Instructions

ADD Add to Accumulator (Direct Address)
Form:
Octal code:

ADD Y
2000 + Y

Execution time:

3.2 /us

Operation:

The contents of register Y are added to the contents of the AC, using one's complement
addition; the sum is left in the AC. The previous C(AC) are lost; the Link and C(Y) are not
changed.

3-8

ADA

Add to Accumulator (^-Class)

Form:

ADA

Octal code:

1100+20I +

Execution time:

4.8 /us; 3.2 jUS. when I = 1 and /? = 00

Operation:

The contents of register Y, as specified by I and C(i3), are added to the contents of the AC,
using one's complement addition; the sum is left in the AC. The previous C(AC) are lost; the
Link and C(Y) are not changed.

ADM Add to Memory ((5-Class)
Form:

ADM

Octal code:

11 40 + 201 +i3

Execution time:

4.8 jUs; 3.2 jus. when I = 1 and |3 = 00
The contents of register Y, as specified by I and C(j3), are added to the contents of the AC,
using one's complement addition; the sum is left in both the AC and Y. The previous contents

Operation:

of both registers are lost; the Link is not changed.

LAM

Link A dd to Memory (^-Class)

Form:

LAM

Octal code:

1200 + 20I+/3

Execution time:

4.8 /xs; 3.2 //s. when I = 1 and |S = 00

NOTE
This description presents the logical sequence of events; in practice, the operations
are carried out simultaneously.

The contents of the Link are added to the contents of the AC, using two's complement
addition; the sum is left in the AC. If there is a carry out of bit 0, the Link is set to 1 if not,

Operation:

;

the Link is cleared. Next, the contents of register Y, as specified by I and C((3), are added to

the new contents of the AC, again using two's complement addition; the sum is left in both the

AC and Y. If there is a carry from bit

this time, the

Link is set to

;

if not,

the Link is

unchanged.

C(AC) = 3743

Example:

(1)

C(AC)
+C(L)

(2)

Results:

C(AC)

C(Y) = 6517

C(L) = 1

3743
+

3744

no carry; Link is c

3744
+6517
1
2463

carry; Link is set t

C(AC)
C(Y)
C(L)

2463
=

2463
1

3-9

MUL

Multiply (^-Class)

Form:

MUL

Octal code:

1240 + 20I + /3

Execution time:

9.6 ^s; 8 /us. when I = 1 and j3 = 00

The contents of the AC (multiplicand) are multiplied by the contents of register Y
(multiplier). The product is left in the AC and the MQ. The sign of the product appears in the

Operation:

Link and ACq

The multiplier and multiplicand are treated as 1 2-bit one's-complement numbers. If bit of an operand is set to 1
the operand is negative. The sign of the product is always correct; that is, operands of like sign give a positive
product, and operands of unlike sign give a negative product. Overflow cannot occur; the FLOW flip-flop is not
affected by multiplication.

Either integer or fractional operands may be specified, as follows: if bit

of the designated jS-register contains a 0,

the operands are treated as integers; the binary points of both multiplier and multiplicand are considered to be to
the right of bit 1 1. If C()3o) =
(sign)

bit

and

bit

the operands are taken as fractions; the binary points are considered to be between

Note that when

and ^ = 00, there is no effective address. In this case, integer

multiplication is performed.

When integer multiplication is performed, the low-order 1 1 bits of the product appear in ACi-i and the absolute
The sign appears in ACq and the Link. The
j

value of the low order 11 bits of the product appears in MQo-io-

high-order bits of the product are lost.

When fractional multiphcation is performed, the high-order 11 bits of the product appear in ACi-n ^nd the
absolute value of the low-order bits appears in bits MQo-i o The sign appears in ACq and the Link. The contents of
•

the

MQ can be accessed by using the QAC instruction (see Paragraph 3.3.11).

Examples:

(1)

(all octal form)

Integers

(a.)

(b.)

(c.)

3-10

0432
x0006
00003234

C(AC)
C(Y)
product

2764
x0153
00476374
2764
X7624
77301403

(=-153)
(= -00476374)

C(AC)=3234

C(MQ)=6470

C(AC)=2374

C(MQ)=4770

C(AC)=5403

(=_3154)

C(MQ)=4770
(

(2)

Fractions

0432

(a.)

(b.)

(c.)

C(AC)

X0006
00003234

C(Y)

2764
x0153
00476374

C(AC)

2764
X7624
77301403

C(AC)
C(Y)

product

C(AC)=0000

C(MQ)=6470

C(AC)=0117

C(MQ)=4770

C(AC)=7660

C(MQ)=4770

C(Y)
product

(-00476374)

3.3.4 Full-Word Logic

In each of these Boolean functions, the operation

performed between corresponding bits of the AC and the

operand, independent of the other bits in either word.

BCL

Bit Clear (^-Class)

Form:

BCL

Octal code:

Execution time:

4.8 jus; 3.2 jUS. when I = 1 and j3 = 00

540 + 201 + /3

For each bit of the operand that is a 1, the corresponding bit of the AC is cleared to 0. For

Operation:

each operand bit that

a 0, the corresponding

AC bit is unchanged. The operand is not

changed. The following truth table gives the relationship between the corresponding bits, with
the results of the comparison.

C(ACj)

1
1

C(Yi)

The Boolean statement of this relation is AC A Y.

Example

C(AC)=2307
C(Y) =1616
Result :=2\Q\

BSE

010011000111
001110001110
010001000001

Bit Set ((i-Class)

Form:

BSE

Octal code:

1600 + 20I + /3

Execution time:

4.8 jus; 3.2 jUS. when I =

Operation:

For each bit of the operand that is a 1, the corresponding bit of the AC is set to 1. For each

and i3 = 00

operand bit that is 0, the corresponding AC bit is not changed. The operand is not affected.

The truth table for this relation, which is the familiar inclusive OR, is as follows:

3-11

C(ACj)
1

C(YO
1

The Boolean statement of this relation is AC V Y.

C(AC)=2307

Example

C(Y) =1616
Result =3111

BCO

010011000111
001110001110
011111001111

Bit Complement f^-Class)

Form:

BCO

Octal code:

1640 + 201 + |3

Execution time:

4.8 jus; 3.2 jUS. when 1=1 and |3 = 00

Operation:

For each bit of the operand that is a 1, the corresponding bit of the AC is complemented. For
each operand bit that is 0, the corresponding AC bit is unchanged. The operand is not changed.

The truth table for this relation, which is the exclusive OR, is as follows:

C(AQ)
1
1

C(Yi)
1

The Boolean statement of this relation is AC

^ Y.

C(AC)=2307
C(Y) =1616

Example

Result:=35ll

3.3.5

010011000111
001110001110
011101001001

Full-Word Comparison

In both of these operations, the next succeeding memory location in the program sequence is skipped if the stated

condition is met. When /3 t^ 00, this presents no unusual circumstance. When j3 = 00, however, the memory location

immediately following the skip instruction contains either the operand itself or its address. When such is the case,
this location is automatically skipped, and the one beyond that is considered to be the next location in the program

sequence. If a skip occurs under these conditions, the program will proceed from the third location following the
skip instruction.

SAE

Skip If Accumulator Equal To Operand (^-Class)

Form:

SAE

Octal code:

Execution time:

440 + 201 + j3
4.8 jUs; 3.2 /xs. when 1=1 and |3 = 00

Operation:

If the contents of the Accumulator are equal to the contents of

and

|3),

Y (where Y is specified by

continues without skipping. The contents of the AC and of Y are not changed.

3-12

the next instruction in the program sequence is skipped. Otherwise, the program

SRO

Skip and Rotate (fi-Class)

SRO I P

Form:
Octal code:

1500 + 201 + /3

Execution time:

4.8 /is; 3.2 /is. when I = 1 and jS = 00

Operation:

If bit 1 1 of the operand is 0, the contents of Y (that is, the operand) are
rotated right one
place and the next sequential instruction is skipped. Otherwise, the program proceeds without

skipping.

Example:

ADDRESS

OCTAL

REMARKS

CONTENTS
*20

0020

SRO 1

PI,

3725

P2,

NOP
NOP

0022

1520
3725
0016

0023

0016

P3,

0021

/THE OPERAND IS IN REG 21
/OPERAND BIT = 1, SO NO SKIP
/PROGRAM CONTINUES FROM HERE
1 1

After the test is performed, the contents of PI are rotated right one place; the result, which is retained in PI, is

5752. If the instruction in register P were then to be executed again, the skip would occur, because the new
contents of bit 11 of PI equal 0. The program would then proceed from register P3, skipping the instruction in P2.

Half-Word Operations

3.3.6

3.3.6.1

Half-Word Addressing - The three instructions, LDH, STH, and SHD, operate on either half of a memory

independent of the other half. The addressing scheme is basically that of other j3-class instructions, with

the following difference: whenever bit

of the register containing the effective address holds a 0, the left half of

the addressed operand is used; when bit

contains a

the right half is used. In either case, the data is transferred

or compared between the designated half of the operand and the right half of the AC.

The following examples demonstrate the

effects of half-word addressing.

The instruction

LDH transfers the

designated half of the operand into the right half of the AC; the left half of the AC is cleared.
a. LDH
I = 0, /3 = 00.
C(R) = 0370. (R is the register following LDH). The effective address is 0370.
Because CCRq) = 0, the contents of the left half of register 0370 are placed in the right half of the AC, and the left

half of the AC is cleared.

LDH 12

= 0, jS = 12, C(0012) = 4370. Bit

of j3-register 12 contains a 1 therefore, the contents of the
;

right half of register 0370 are placed in the right half of the AC, and the left half of the

LDH 10

= 00. C(R) = 6527. This is a direct reference, so that there is no explicit effective
address. In this case, the left half of the operand in register R is taken. In the example, the quantity 65 is placed in
c.

AC is cleared.

the right half of the AC, and the left half of the AC is cleared.

LDH 112

= 1, |3 = 12. C(0012) = 0370.

The effective address (that is, C(0012)) must be incremented before it is used. Instead of 1, however, 4000 is added
to the contents of the i3-register (remember that the half-word indicator is in bit 0). Given the conditions specified
above, the contents of j3-register 12 are first augmented from 0370 to 4370, and the right half of the operand in
register 0370 is taken. If a second LDH I 12 is then executed, the |3-register is again incremented by 4000. The sum,
which leaves C()3o )=0, results in a carry out of the high-order bit. The carry causes 1 to be added to the sum,
resulting in a final effective address of 0371. The new operand is then taken from the left half of the new register.
The indexing sequence is thus: left half, right half, left half of the next succeeding register, etc.
Because the basic indexing scheme is operative only over bits 2-11 of the i3-register, half-word addressing proceeds

from the right half of register 1777 to the left half of register 0000, and from the right half of register 3777 to the
left half of register

2000. C(iS) are thus incremented from 1777 to 5777 to 0000, and from 3777 to 7777 to 2000.

3-13

NOTE
Another way of looking at the half-word indicator may help clarify this method of
addressing. If the indicator is considered to be just to the right of bit 11, rather than
in bit 0, it becomes apparent that half-word indexing is just like fuU-word indexing,
with 1 added to the low-order bit (that is, the half-word indicator) each time. You
can, if you like, imagine a binary point between the half-word indicator and bit 1

of the |3-register, so that successive addresses might be read as 0370, 0370 1/2, 0371,
0371 1/2, 0372, etc. (Or, in octal, 0370.0, 0370.4, 0371.0, 0371.4, 0372.0, etc.)

LDH

Load Half

Form:

LDH

Octal code:

1300 + 201 + /3

Execution time:

4.8 /xs; 3.2 ms when I = 1 and |3 = 00

Operation:

The contents of the designated half of register Y (where Y is specified by I and C(j3)) are
placed in the right half of the Accumulator. The left half of the AC is cleared. The previous
C(AC) are lost. The contents of Y are not changed.

STH

Store Half

Form:

STH

Octal code:

1340 + 201 + 13

Execution time:

4.8 jus; 3.2 jus when I = 1 and j3 = 00
The contents of the right half of the Accumulator are stored in the designated half of register
Y. The contents of the AC and of the other half of Y are not disturbed.

Operation:

SHD

^kip If Half Differs

Form:

SHD

Octal code

Execution time:
Operation:

400 + 201 + jS
4.8 jus; 3.2 jus when I = 1 and jS = 00
If the contents of the designated half of register

Y are not equal to the contents of the right

AC, the next instruction in the program sequence is skipped; otherwise, the
program proceeds without skipping. The contents of Y and of the AC are not changed. As in
the other i3-class skips (SAE, SRO), the register immediately following the SHD is
automatically passed over when j8 = 00.

half of the

3.3.7 a-Class Operations

Each of these instructions uses the

registers

0000-0017

in a

unique way.

A third a-class instruction, DIS, is

described in Paragraph 3.4, CRT Display.

SET

Set a-Register

Form:

SET

Octal code:

0040 + 201 + a

Execution time:

6.4 pts; 4.8 us when I = 1
The contents of the a-register specified by bits 8-11 of the SET instruction are replaced by the
operand, whose location is determined by the state of the I-bit, as follows:

Operation:

If I

instruction.

3-14

the operand

in the register immediately following that containing the

SET

If I

- 0, the effective address of the operand is in the register immediately following that

SET instruction.
SET always requires two successive locations; the program always continues from the second
containing the

Address

Contents

SET I 1 5

P + 1

2537

P+2

....

Action

/THE OPERAND IS IN REGISTER p+1
/OPERAND 2537 IS STORED IN REGISTER
/PROGRAM CONTINUES FROM THIS REGISTER
1

The previous contents of the a-register are lost. The AC is not disturbed, and the contents of the register containing
the operand are not changed.

XSK

Index and Skip

Form:

XSK

Octal code:

0200 + 201 + a

Execution time:

3.2 jws

Operation:

If I = 1, the contents of the designated a-register are incremented by 1, using 10-bit two's
complement addition as in /3-class indexing. If I = 0, a is left undisturbed. Then if the contents

of bits 2-1 1 of the a-register are equal to 1777, the next instruction in the program sequence is
skipped. Otherwise, the skip does not occur.

When C(a) are incremented, the two high-order bits are not affected. Thus, 1777 is incremented to 0000, 3777 to
2000, etc.
3.3.8

Program Control

IMF Jump
Form:

JMP Y

Octal code:

6000 + Y

Execution time:

3.2 /us when Y ^ 0000; 1.6 jUS when Y = 0000
The quantity Y is placed in PCa-i i, and the next instruction is taken from register Y. The

Operation:

program proceeds from that point.
If Y T^ 0000, the 10-bit address of the register immediately following the JMP instruction (i.e., the contents of the
Program Counter) is stored in location 0000 of the Instruction Field as a JMP instruction. This permits the JMP to

be used not only as an unconditional transfer of program control, but also as a subroutine calling instruction. If Y =

0000, the jump is executed, but nothing is stored in register 0000. JMP
shown in the example.

used to return from a subroutine, as

3-15

Example

ADDRESS OCTAL

REMARKS

CONTENTS
*0000

0000

0001

0000

0175
0176

0016
0000

0177

0000

0242
0243
0244

6000
0000
0000

JMP

6175

JMP 175

0017
0000
0000

NOP

0000,

/WILL CONTAIN 6573 AFTER JMP 175 IS

/EXECUTED
*0175

NOP

/START OF LINEAR SUBROUTINE WHICH
/CONTAINS NO JMP INSTRUCTIONS

*0242

/RETURN FROM SUBROUTINE

*0572

0572
0573
0574
0575

/JUMP TO SUBROUTINE AT REGISTER 0175
/SUBROUTINE RETURNS TO THIS LOCATION

When JMP 175 is executed, CCPCj-i i) = 0573. This, combined with 6000 (the octal code for JMP), is placed in
transfers program control to register 0000, where JMP 573
register 0000. When the subroutine has finished, JMP
the same time, JMP 1 is stored in register 0000, but that
program.
(At
is executed, returning control to the calling
is incidental to

the actions of interest here.)

When a new Instruction Field has been selected (see paragraph 3.3.14. Memory Address Control), the first JMP Y
(Y 9^ 0000) following the field selection performs the actual switching of the field; the target register of the JMP is
has no effect on
in the new field, and the return jump is stored in register 0000 of the new Instruction Field. JMP
the field registers.
3.3.9 Shift and Rotate Operations

These instructions rotate the contents of the Accumulator left or right, or shift them right (scaling), propagating
the sign bit.

A single instruction can cause a shift of up to Hg bit positions, or 1-1/2 times the length of the AC.

On shifts or rotations right, the MQ is treated as a 1 2-bit extension of the AC, so that bits shifted out of ACi i
enter MQo as shown in Figures 3-7 and 3-8. In all these operations, the Link is included when I = 1 and excluded
,

when 1 = 0. Execution times depend on the number of positions shifted.

ROL

Rotate Left

Form:

ROL I N

Octal code

0240 + 201 + N,
< N < 1 78
1.6-6.4^5
The contents of the AC are rotated left N places. If I = 1, the Link is included. The rotation
scheme is shown in Figure 3-6. The contents of the MQ are not affected.

Execution time:
Operation:

3-16

I»0

D
1 = 1

Figure 3.6. Rotate Left

ROR

Rotate Right

Form:

ROR

Octal code:

0300 + 201 + N,

Execution time:

1 .6 -

Operation:

The contents of the AC are shifted right N places. Bits shifted out of ACj j enter MQo and are
shifted down the MQ. Bits shifted out of MQj
are lost. If I = 1, the Link is included in the
i
rotation. The scheme is shown in Figure 3-7.

0<N<178

6.4 /us
,

1=0

D
MQ

LOST

I»1

D
MO

v.*

LOST

Figure 3-7. Rotate Right

3-17

SCR

Scale Right

Form:

SCR

Octal code:

0340 + 201 + N,

Execution time
Operation:

0<N<178

1.6- 6.4 /is

The contents of the AC are shifted right N places. The sign bit (contents of ACq) is not
changed, and is placed in the N bits to the right of ACq Bits shifted out of ACj j enter MQo
.

and are shifted down the MQ.

ACi

Bits shifted out of MQi i are lost. If 1=1, bits shifted out of

also enter the Link, so that, at the completion of the operation, C(L) = C(MQo). If I = 0,

the Link is unaffected. The shifting scheme is shown in Figure 3-8.

Example:

C(AC) = 4371

C(MQ) = 0000

Instruction:

SCR

Because I =

the Link will receive the contents of

AC^ at each

shift. The result of the operation:

The sign bit, which was 1

C(AC) = 7743

is loaded in

the vacated bits (ACj .g

C(MQ) = 7100

Bits shifted out of the

AC entered the

MQ at the high-order end.
C(L) = I

The last bit shifted out of ACi
1.

was a

Check: C(L) = C(MQo).

1=0
L

D^H
G[

LOST

1=1

^rf
V*

_
Figure 3-8. Scale Right

3-18

LOST

3.3.10 Skips

These instructions

test the states

of various

registers,

flip-flops,

and external inputs. In every case, the next

succeeding instruction in the program sequence is skipped if

(1)

and the condition is met

1=1 and the condition is not met

(2)

Otherwise, the program proceeds v^'ithout skipping.

The skip instructions (with the exception of the unconditional skip instruction, SKP) have an associated "skip
condition", such as a register being cleared or one of the external digital inputs ("external levels") being asserted. If
the skip condition is met (e.g., the register is cleared or the external level is asserted) at the time the instruction is

executed, a skip occurs. This means that the next instruction is taken from the second location following the skip
instruction, rather than

from the usual

location.

Normally, the skip instruction is followed by a single-word

instruction that is skipped or executed according to whether or not the tested condition was met. No distinction is

made between

and double-word instructions; if the skip instruction were followed by a double-word
would be transferred to the second word of the instruction if a skip occurs. Generally skip
instructions should not be followed by double-word instructions. In the skip instructions discussed here, (but not
in the "addressable" skips: SHD, SAE, and SRO), the i bit inverts the sense of the skip. That is, if the i bit is zero,
single-

instruction, control

the instruction skips only if the skip condition is met. If the i bit is a one, the skip occurs only if the condition is

not met.

APO

Accumulator Positive

Form:

APO I

Octal code:

0451+201

Execution time

1 .6

Condition:

The sign bit (contents of ACq) is 0, that is, C(AC) is a positive number.

AZE

)us

Accumulator Zero

Form:

AZE I

Octal code:

0450 + 201

Execution time:

1.6 /us

Condition:

The contents of the AC equal 0000 (+0) or 7777 (-0).

LZE

Link Zero

Form:

LZE I

Octal code:

0452 + 201

Ex ecution time

1 .

Condition:

The contents of the Link equal 0.

QLZ

6 /lis

MQ Low-Order Bit Zero

Form:

QLZ I

Octal code:

0455 + 201

Execution time

1 .6

Condition:

The contents of MQi i equal 0. (This is identical to the LINC-8 instruction, ZZZ.)

/us

3-19

FLO

Overflow

Form:

FLO I

Octal code:

0454 + 201

Execution time:

1.6 pis

The FLOW flip-flop is set to 1. When overflow occurs as the result of an addition (ADD, ADA,
ADM, or LAM), the FLOW flip-flop is set to 1. If overflow does not occur as a result of the

Condition:

above instructions, the FLOW flip-flop is cleared.

SKP

Skip Unconditionally

Form:

SKP I

Octal code:

0456 + 201

Execution time:

1.6 jus

Condition:

The next

instruction

skipped unconditionally. (In LINC-8 and early PDP-12 assembly

programs SKP was defined as 466.)

The following skips test for various external input conditions.

IBZ

LINCtape Inter-Block Zone

Form:

IBZ

Octal code:

0453 + 201

Execution time

6 jus

LINCtap^ unit is in one of the inter-block zones and the tape is moving, the
next instruction is skipped. This instruction will sense an IBZ only if the tape is in motion (i.e.,
only after a tape instruction with "I = 1").

Condition:

SNS

1 .

the selected

Sense Switch

Form:

SNS

Octal code:

0440 + 201 + N,

Execution time

0<N<5

1.6 ixs

Sense Switch N on the Operator's Console is set to

Condition:

1. If 1=1,

the skip will occur when the

selected switch is set to 0.

SXL

Skip On External Level

Form:

SXL

Octal code:

0400 + 201 + N,

Execution time:

1.6 jus

Condition:

An external input level is +3v. If I = 1, the skip will occur when the external level is at ground

0<N<178

(OV). In the basic PDP-12, only three of these levels have been defined; the others are available
for the user's options.

When nothing is connected to the External Level Lines, they are

preloaded to +3V. These external levels are digital inputs to the I/O bus, and should not be

confused with the analog inputs to the A-D Converter.

NOTE
The connection
Chapter 5).

3-20

for the External Level lines

made via the I/O Bus cables (see

The three defined levels and their mnemonics are:

SXL
SXL
SXL

(KST)
(STD)

Key Struck (See below)
Tape Instruction Done (See Paragraph 3,6.9)

(TWO

Tape Word Complete (See Paragraph 3.6. 14)

KST Key Struck
Form:

KST 1

Octal code:

0415 + 201

Execution time:

1.6 jws

Condition:

A key has beer
been struck on the ASR-33 keyboard, the character code has been assembled in the
I

Teletype buffer, and the Keyboard flag is raised. (The flag is cleared when the character is read
into the AC.)
3.3.11

Miscellaneous

These instructions perform various tasks. All are self-contained and require no memory references.

HLT

Halt

Octal code:

0000

Execution time:

1.6 /us to fetch and decode

Operation:

The computer stops. The contents of the AC, MQ, Link, and other active registers and
flip-flops are not affected. The Program Counter contains the address of the register
immediately following the HLT. If the operator presses CONTINUE, the program resumes
from the point indicated by the C(PC).

CLR

Clear

0011

Octal code:

Execution time:

1.6 /LIS

Operation:

The AC, MQ, and Link are cleared to zero. No other registers or flip-flops are affected.

COM

Complement AC
0017

Octal code:

Execution time

1 .

6 /us

The contents of the AC are complemented. Bits containing Os are changed to contain Is, and

Operation:

vice versa. No other registers are affected.

NOP No Operation
Octal code:

0016

Execution time:

1.6 /Lis

Operation:

None. Nothing happens. NOP provides a 1.6-/18 delay, and is often used to hold a place in the

program for instructions which might be changed or added during the course of execution.

QAC

Place

MQ in AC
0005

Octal code:

Execution time
Operation:

6 /us

The contents of MQo-i o are placed in ACj -^ i ACo is cleared. This instruction provides access
.

to the low-order bits of a fractional product. Figure 3-9 shows the transfer path.

3-21

SET TO
ZERO

Figure 3-9.

QAC Transfer Path

To obtain all 12 bits of the MQ, the following program sequence may be used:

OCTAL CODE

REMARKS

INSTRUCTION
*0020

QAC
ROL
QLZ

0005
0241

0475
6026
1620

JMP
BSE

0001

/C(MQO-IO) PLACED IN AC 1-1
/ROTATE C(AC) LEFT 1 PLACE, WITHOUT LINK.

/SKIPIFC(MQ11)=

.+3
I

0001

/C(MQ1 1) = 0. JUMP TO THIRD REGISTER BEYOND.
/C(MQ1 1) = 1. SET ACl 1 EQUAL TO 1.

/OPERAND TO SET ACl

(QAC is identical to the LINC-8 instruction, ZTA.)

3.3.12 Console Switches

These instructions provide access to the states of the switches in the Left and Right Switch Registers on the
Operator's Console. The I-bit has no effect in these instructions.

LSW

Left Switches

0517

Octal code:

Execution time

1 . 6 /xs

The contents of the Left Switches Register on the Console are placed in the AC. The previous
C(AC) are lost.

Operation:

RSW

Right Switches

0516

Octal code:

Execution time:

1.6 /js

Operation

The contents of the Right Switches Register are placed in the AC. The previous C( AC) are lost.

3.3.13

Mode Control

PDF

Switch To The 8 Mode

0002

Octal code:

Execution time
Operation:

1 .

6 jus

Beginning with the next succeeding instruction, the central processor will operate in the 8

mode; all subsequent instructions are interpreted as PDP-8 operations. A similar instruction,

LINC (6141), in the PDP-8 mode instruction set, causes a switch to LINC mode.

3-22

3.3.14 Input/Output Bus

In addition to the input and output devices controlled directly by LINC instructions (see Paragraphs 3.4,

3.5, and

LINC mode program also has direct access to any device connected to the PDP-12 I/O Bus. By using the
special two-word enabhng instruction, lOB, any 8 mode lOT instructions can be included within a LINC program
3.6), the

sequence.

lOB

110 Bus Enable

lOB (first word) lOT (second word)
0500 (first word)

Form:
Octal code:

Execution time:

5.9 jms

Operation:

The lOT timing chain is activated by the second word of this instruction. Bits 3-11 of this
second word are interpreted as a PDP-8 lOT command; bits 0-2 have no effect.

Example 1:
The following sequence may be used to read and store a character from the high-speed tape reader:

/ENABLE I/O BUS
/READ TAPE READER BUFFER
/STORE IN REGISTER SPECIFIED BY C(0014)

lOB

RRB
STA 14

Example 2:
The following sequence waits for the high-speed reader flag and then reads the character buffer

OCTAL CODE

0500
6011

6020

0500
6016

INSTRUCTION

REMARKS

0020
lOB

/ENABLE I/O BUS

RSF
JMP

/SKIP IF HIGH-SPEED READER FLAG IS SET
/NOT SET. GO BACK TWO SPACES

lOB

RRB

.-2

/FLAG IS SET. ENABLE THE BUS, AND...
/READ THE CHARACTER

Note that, in the skip loop, the program must jump back two locations, because the lOB must be executed each time.

Several lOB/IOT pairs are used in LINC Memory Address Control and Program Interrupt operations.

3-23

Memory Address Control

3.3. 1 5

The two memory Fields used by a LINC program are program-selectable. The assignments are made by setting the
two 5-bit Memory Field Registers, which can address any of 32 1024-word memory segments. Considered with
respect to the physical configuration of memory, the three high-order bits of each Field Register determine which
4096-word memory bank is to be used, while the two low-order bits specify one of the four segments within that
bank. The two LINC memory Fields need not be adjacent, or in any particular order. Normally, however, they
would not be assigned to the same segment.
In addition to the Instruction Field (IF) and Data Field (DF) Registers described in Chapter 1, the PDP-12 Memory

Control contains two other registers of interest to the LINC mode programmer.
3.3.15.1 Instruction Field Buffer (IB) 5 Bits - This register holds the number specifying a new Instruction Field.
Once loaded, its contents are transferred to the IF at the occurrence of the next JMP Y instruction.

3.3.15.2 Save Field Register (SF) 10 Bits

- Whenever the Instruction Field is changed, either by programmed

action or by a program interrupt or trap, the contents of the IF and DF are placed in the Save Field Register. From
the SF, the Contents of the IF and DF can be restored, so that execution of an interrupted program, for example

may be resumed. The contents of the SF may be read into the AC. (See also the Program Interrupt discussion in
Paragraph 3.3. 1 5.4.) For historical reasons the SF is also called Interrupt Buffer in some places.

3.3.15.3

Memory Control Programming — The Instruction Field and Data Field registers can be loaded directly,

using LINC mode instructions.

LIF

Load LINC Ins true tion Field Buffer

Form:

LIF N
0600 + N,

Octal code:

Execution time
Operation:

1 .

< N < 378

6 /xs

The five-bit quantity N is placed in the Instruction Field Buffer (IB). The present contents of
the IF and

DF are transferred to the Save Field Register (SF). When the next JMP Y

(Y ^ 0000) is executed, N is transferred from the IB to the Instruction Field
Register. The return JMP is stored in location 0000 of the new Instruction Field, and program

instruction

control is transferred to register Y of the new Instruction Field.

The automatic saving of the IF and DF in the Save Field Register is especially useful when
subroutines are called across memory fields; that is, when a called subroutine is located in a

memory field other than the current one. The subroutine may pick up the field information
needed in obtaining arguments and generating subroutine returns by interrogating the Save
Field Register.

The execution of the LIF

instruction will internally inhibit the execution of a Program

Interrupt even if ION has been given. This Interrupt Inhibit lasts from the LIF instruction until

the first LINC mode JMP instruction is fetched and executed in the newly selected Instruction
Field. This allows the Save Field Register to

be used for cross field subroutine linkage in

programming which uses the Program Interrupt.

Because LINK Instruction Trap (see Paragraph 3.3.17) also uses the Save Field Register for program linkage, an instruction which will be trapped must not be given between an LIF and the next JMP

reference will ultimately need the Save Field Register linkage information.

3-24

Y (Y

0000) if the cross field

Example:

The program is operating in Field 2. Control is to be transferred to location 1000 of Field 5.
Address

Action

LIF 5

Contents

/5 IS

PLACED IN THE IB

/C(IF) AND C(DF) ARE PLACED IN THE SF

JMP 1000

p +k

/C(IB) ARE TRANSFERRED TO THE

P + K + 1 IS STORED IN REGISTER
/OOOO OF FIELD 5, AND THE PROGRAM
/IF. JMP

/PROCEEDS FROM REGISTER 1000 OF FIELD 5
JMP

has no effect on the Memory Field registers. If it is used to return to a calling program in a different field,

the change of field is effected by the JMP instruction stored in register 0000 of the subroutine's field.

(LIF replaces the LINC-8 instruction, LMB)

LDF

Load LINC Data Field Register

Form:

LDF N

Octal code:

0640 + N,

Execution time

Operation:

1 .6

< N < STg

jus

The 5-bit quantity N is placed in the Data Field Register. All subsequent indirect references to
the Data Field are made to the newly selected field. The previous C(DF) are lost. The contents
of the other Memory Control registers are not affected.

(LDF is identical to the LINC-8 instruction, UMB)
The contents of the Memory Field Registers can be examined by using the following lOB/IOT pairs.

lOB
RIF

B-ead Instruction Field

Octal code:

0500
6224

Execution time:

5.9 JUS

Operation:

The contei
contents of the Instruction Field Register are ORed into bits ACg-i o- The remaining AC
bits are unaffected, and the contents of the IF are unchanged.

NOTE
When executed in LINC mode, the three lOT instructions, RIF, RDF, and RIB, are
the only cases where an lOT has a slightly different function than when executed in
8 mode. For these instructions, all five bits of the IF and/or DF are read into the AC

when in LINC mode, while only the most significant three bits of each are used in 8
mode.

3-25

lOB

RDF

Read Data Field
0500
6214

Octal code:

Execution time:

5.9 jus

Operation:

The contents of the Data Field Register are ORed into bits AC^-i o- The remaining AC bits are
unaffected, and the contents of the DF are not changed.

3,3.15.4 Program Interrupt In L INC Mode

- To facilitate the handling of data being transmitted to and from

PDP-12 includes a Program Interrupt Facility. When an external device is ready for
servicing, a signal (flag) associated with that device is set. With Interrupt enabled, the following sequence of events
several peripheral devices, the

will occur when a flag is set:

The instruction being executed at the time of the interrupt request is completed.

The contents of the Program Counter are stored in register 0040 of memory field

(regardless of the

current Instruction Field assignment).

The contents of the Memory Field registers are placed in the Interrupt Buffer (Save Field Register).

Program execution proceeds from register 004 1 of Memory Field 0.

The normal procedure from this point calls for the interrupt service routine beginning in location 0041 to
determine which device flag caused the interrupt request, perform the appropriate tasks, restore the Memory Field
registers, re-enable the interrupt, and jump back to the interrupted program at the point where the Program
Interrupt occurred.

Whenever a change of LINC Instruction Field occurs, the Program Interrupt is inhibited (between Steps 1 and 2
above) until the first JMP is executed in the new field. This allows the programmer to obtain and save the contents
of the SF after the Field change, before a waiting interrupt request destroys the contents of the SF.

The interrupt control instructions and related memory field instructions are all lOB/IOT pairs.

lOB

ION

Interrupt On

Octal code:

0500
6001

Execution time:

5.9 jUS

Operation:

The Interrupt Facility is enabled immediately after the next succeeding instruction (following
the ION) is executed. From that point on, any interrupt request wUl cause the sequence of
events described above. If a device flag is already raised

waiting

request

serviced immediately.

when the Interrupt is enabled, the

The one-instruction delay before enabling the

interrupt ensures that the interrupt service routine can return to an interrupted program before

a new request is honored without losing its place.

lOB
lOF

Interrupt Off

Octal code:

0500
6002

Execution time:

5.9 jUS

Operation:

The Interrupt is disabled. The facility is disabled immediately; subsequent requests will not
cause an interrupt until the facility is enabled again.

3-26

The next two instructions are related to the Save Field Register, wherein the original contents of the IF and DF are
stored whenever the contents of the IF are being changed, by an LIF instruction, or as the result of an Interrupt

request or a Program Trap.

INST. FIELD

BUFFER

MP AFTER LIF
'r

INST. FIELD

\\\\\

SAVE FIEL D

DATA FIELD
IWTFRRIIPT TRAP LIF

INSTRUCTION

ACCUMULATOR

Figure 3-10. Data Path: IB, IF, DF, and AC

lOB
RIB

R ead In temip t Buffer

Octal code:

0500
6234

Execution time:

5.9 pis

Operation:

The contents of the Interrupt Buffer (Save Field Register) are ORed into bits ACqAC4-1 1 as shown in Figure 3-10. AC2-3 and the contents of the SF are unchanged.

and

RIB is most commonly used immediately after a change of instruction field or a program trap,
to save the record of the origin fields while the Program Interrupt is inhibited. (If inhibit were

not provided, a waiting interrupt request could destroy the contents of the Save Field Register.

The first JMP instruction executed after a trap or change of Instruction Field reenables the
Interrupt.)

lOB

RMF

Restore Memory Fields

Octal code:

0500
6244

Execution time:

5.9 jus, including lOB
The contents of SF5.9

Operation:

are placed in the Data Field Register, and the contents of SF0.4 are

placed in the Instruction Field Buffer. At the next occurrence of a JMP Y instruction (Y

0000), the contents of the IB are transferred to the IF, effecting a return to the proper field
after servicing an interrupt request. The data transfer path is shown in Figure 3-11.

3-27

INSTRUCTION FIELD
1

DATA FIELD REGISTER
(JMPY)

4
J

(

4
(RMF)

Y
i\

(RMF)
J

SAVE FIELD REGISTER

Figure 3-11, Data Path, RMF Instruction

Disable JMP Return

DJR

0006

Octal code:

Execution time:

1.6 )us

Operation:

DJR sets a flip-flop, preventing contents of location 0000 from being changed when the next
and only the next LINC mode JMP is given. The DJR instruction is used when returning from
Program Interrupt or Trap service routines. The DJR should be given prior to the ION
instructions. This is useful because an interrupt can occur within a LINC mode subroutine that

uses Location 0000 of its IF to retain the subroutine return; hence, it must not be destroyed.

Example:

A program operating in Field 7 is interrupted while the instruction in register 0531 is being executed.
( 1

C(PC) are stored in location 0040 of Field 0.

(2)

C(DF) and C(IF) are placed in the SF, as shown in Figure 3-10.

(3)

Program execution resumes in location 0041 of Field 0; in other words, 00 is placed in the IF, and 0041

inPC2-ii(4)

The interrupt is disabled.

The interrupt service routine must do three things. First, it sets up a return jump enabling the program to get back
to the point of the break. Next, it identifies the cause of the request and services the condition. Finally, it restores

the conditions prevailing at the time the interrupt occurred and returns to the main program.

sequence shows how these tasks may be accomplished.

3-28

The following

ADDRESS OCTAL

CONTENTS

0040

*0040
0532

0041

0042
0043

0532
4000
2040
1620

STC ACSAV

ADD 0040
BSE I

REMARKS
/CONTENTS OF PC AT TIME OF INTERRUPT
/SAVE C(AC), THEN CLEAR AC
/SAVED ADDRESS (0532) TO AC
/MAKE JMP INSTRUCTION: C(AC)
/V C(0044)

0044
0045

6000

4071

STC RTN

0046

0000

0047
0050
0051
0052
0053
0054
0055
0056
0057
0060

0000
0000
0000
0016
0016
0016
0016
0000
0000
0500

NOP
NOP
NOP
NOP

0061

6244

RMF

lOB

/OCTAL CODE OF JMP INST.
/STORE JMP 532 AT END OF SERVICE
/ROUTINE
/MAIN PART OF SERVICE ROUTINE, IF
/NECESSARY
/OTHER ACTIVE REGISTERS (MQ,L,ETC)
/SHOULD BE SAVED ALSO
/THE REST OF THE ROUTINE

/EXIT SEQUENCE, ENABLE lOT TIMING
/CHAIN
.AND RESTORE MEMORY FIELDS,
/.
.

/(07 TO IB)

0062
0063
0064
0065
0066

0067
0070
0071
0072
0073
0074
0075
0076

4076
2000
0006
0000
0000

STC TEMP
/CLEAR AC WITHOUT DISTURBING MQ AND L
ADD ACSAV /RESTORE ORIGINAL C(AC)
DJR
/SET PROCESSOR SO THAT NEXT JMP INST
/WILL NOT STORE IN LOCATION ZERO OF
/MEMORY BANK TO WHICH JMP AT "RTN"
/WILL GO

0500

lOB
ION

6001

6532
0000
0000
0000
0000
0000

RTN,

JMP 0532

TEMP,

0000

/RE-ENABLE INTERRUPT
/JMP TO ORIGINAL FIELD

RMF=6244
ION=6000
3.3.16 Special Functions

A set of six Special Functions allows the LINC programmer to establish any of five operating states, or generate an
I/O PRESET pulse. The special functions are determined by AC2-7

as shown in Figure 3-12.

INSTRUCTION

TRAP

I/O PRESET

PULSE
DISABLE

TAPE
TRAP

TELETYPE
INTERRUPT
FAST

CHARACTER

SAMPLE

SIZE
Figure 3-12. Special Functions

3-29

These functions have the following characteristics:
1.

Instruction Trap Enable — Causes an immediate program interrupt to register 0141

when an undefined

LINC instruction code is encountered.
The instruction trap is described in detail in Paragraph 3.3.17.
2. Tape Trap - When this function and Instruction Trap Enable are both set, a program interrupt to register
0141 will occur whenever a LINCtape instruction or one of the other trapped codes is encountered. The LINCtape

instruction is not executed. Tape Trap is described in detail in Paragraph 3.6. 13.
3.

Character Size

— This function determines the size of a character displayed on the CRT by the DSC

instruction. It is described in detail in Paragraph 3.4. 1.
4.

Fast Sample — This function reverses the order of events of the SAM instruction; i.e., read the converter

buffer and initiate a new conversion, then continue without pausing (see Paragraph 3.5.1).
5. Disable Teletype Interrupt - Interrupt requests from the ASR-33 Keyboard or Printer are inhibited. No
program interrupt will occur when either TTY flag is set even if the Interrupt Facility is enabled (see Chapter 6).
6. Generate I/O Preset - If this bit is set when the enabling instruction (ESF)
is executed, an I/O PRESET
pulse is generated clearing all device flags, disabling the Interrupt, clearing the Tape Extended
Operations Buffer,
and generating the TAPE PRESET pulse. Other Special Functions are cleared, or in the case of CHARACTER

SIZE, set to full size. The active registers of the Central Processor are not affected, and the system continues
operate with

effectively nullified if I/O

PRESET is given. All the Special Functions except I/O PRESET are controlled by

flip-flops set from the designated

ESF

RUN on. Any or all of these functions may be enabled at the same time, except that they are
AC bits; the states of these flip-flops may be examined at any time.

Enable Special Functions

Octal code:

0004

Execution time:

1 .6

Operation:

The contents of AC2-6 are placed in their respective flip-flops, as shown in Figure 3-12. For

jus

each AC bit set to

the corresponding function is enabled. For each AC bit set to 0, the

corresponding function is disabled. If AC7

set to 1, the I/O

PRESET pulse is generated. All

Special Function bits are cleared (except ESF 04, Full Size Character, which is set to a 1) by

I/O PRESET, either from the console or program control.

SFA

Place Special Function Flip-Flops in

Octal code:

0024

Execution time:

1.6 ;us

Operation:

3.3.17

The contents of the Special Function flip-flops are placed in their respectively designated AC
bits, as shown in Figure 3-12. ACq-i and 7-11 are cleared.

Instruction Trap

Several sets of operation codes in the LINC repertoire are undefined. The LINC programmer can make use of these
codes without having to hard-wire them, by means of subroutines and the Instruction Trap. When the Trap is
enabled (ESF with C(AC2) = 1), any undefined LINC codes will cause a program trap. When the undefined code is

encountered, program control is transferred to register 0141 of Memory Field 0, regardless of the current setting of
the IF. The contents of the Program Counter are placed in register 140, and the contents of the IF and DF are
placed in the Save Field Register. The subroutine beginning at 0141 can examine the trapped code (using the
information stored in 0140 and the SF) to determine what program-defined operations are to be performed. (Also,
see Paragraphs 3.3.15.3 and 3.3.15.4 for interaction with Program Interrupt.

These are the undefined LINC codes which cause a program trap

3-30

Operate class

501-515,521-535

Execute class

74O-747

Undefined

540-577

Undefined

1700-1737

The LINC codes 1700-1737
instruction

are

considered as

j3-class

instructions. Therefore,

encountered, the address contained in location 140

when either a 1700 or 1720

the address of the trapped instruction

incremented twice (trapped instruction address +2). All other undefined codes will cause location 140 to contain
the address of the trapped instruction incremented once (trapped instruction + 1).

Probably the most common use of the Instruction Trap is in the execution of programs written for the LINC-8. A

LINC-8 Trap Simulator is provided in the basic PDP-12 software package. Close study of this program will be most
helpful for the

programmer wishing to use the Trap facility. The Trap facility is further useful for developing

device-independent software.
3.3.17.1

Tape Trap

- When both the Tape Trap and Instruction Trap functions are enabled, the LINCtape

instructions (codes 700-737) are trapped also. This

useful if the

programmer wishes to substitute another

external storage device, such as a Disk, for the LINCtape.

3.3.17.2 Program Interrupt and Instruction Trap - If the interrupt is enabled when an Instruction Trap occurs, the
interrupt is inhibited until the execution of the first JMP after the trap. This permits the trap program to store the

contents of the Save Field Register immediately after the trap, so that the record of where the trap took place is
not destroyed by an interrupt request, which also causes the contents of the IF and DF to be placed in the SF (also
see Paragraphs 3.3.15.3 and 3.3.15.4).

3.4

CRT DISPLAY, TYPE VR 12

The 6.5 inch x 9 inch rectangular screen of the PDP-12 CRT Display Type VR12 has a total display
square inches. Grid dimensions are 512 x 512 points. The horizontal distance between

area of 58.5

points is 0.0176 inches; the

0.0127 inches. The (0,0) grid point is at the midpoint of the left side of the screen, as shown
in
the schematic representation in Figure 3-13. Grid co-ordinates are given in octal.

vertical distance is

0,+377

777. -f377

777,0

0,-377

Figure 3-13.

777,-377

CRT Grid

The display system is fully buffered. Coordinates are held in two 9-bit buffers; during the execution of DSC, the

word is retained in a 12-bit Pattern Intensification Register. Either of two multiplexed intensification
channels can be specified. A switch on the VR12 front panel allows either or both channels to be displayed.
pattern

Below the channel selector is a variable knob which allows the user to change the intensity of the displayed points.

A level control located within the VR 12 presets the maximum brightness level, preventing spot bums.
A 24-contact connector on the Data Terminal Panel allows the user to connect an auxiliary scope (VR- 2 A CRT
1

Display, Tektronix 561, or similar unit) for remote display of the same information sent to the main screen. The

channel selectors can be independently set so that each scope displays one of the channels, thus allowing
independent simultaneous displays on two scopes.

A complete set of connection points for the VC12/VR12 display system is shown in Appendix G.

3-31

The output drive capability of the D-A converters is Ov to -5.85v capable of driving a load resistance of 1 kO,
connected to ground. This allov^^s up to 200 feet of cable for a remote VR-12. The absolute values of the D-A
outputs are not held closer than ±0.3v but are stable to within 3.0%. The D-A converters are loaded by jam
transfer. The D-A used to drive the scope is also available as a single-ended output to drive external devices. The Ov

D-A point is equivalent to the lower left hand corner of the display screen.
The LINC display instructions allow the programmer to display single grid points or a small array of points. In
either case, the full buffering allows the program to proceed after the display operation has been initiated. If a
subsequent display instruction

encountered before the previous display operation has been completed, the

program will pause until the display control is free, then execute the new instruction.

3.4.1

Point Displays

DIS

Display (a-Class)

Octal code:

DIS I a
0140 + a,

Execution time:

3.2 pis; 23 /xs for completion of display

Form:

0>a>\ls

A single point on the screen is intensified. The vertical coordinate is specified by AC3-1
horizontal coordinate by bits 3-11 of the designated a-register. If bit
0,

on Channel 0; if C(ao) =

the point will be displayed

;

the

of the a-register is set to

the point will be displayed on

Channel 1.
If I = 0, the contents of a are taken as is. If I =

two's complement addition. Bits

1 ,

C(a) are first incremented by 1 using 10-bit,
,

and 1 are not affected.

3.4.2 Character Displays

DSC

Display Character (^Class)

Form:

DSC

Octal code:

Execution time:

1740 + 201 +j3, |3<2<178
4.8 us when I = 1, j3 = 00; 6.4 ^s when 1 =

Operation:

A vertical 2x6 array of points is displayed according to a pattern word stored in register Y (Y
is

or iS^^ 00 Control complerion time 20-56 jus.

defined as with other )3-class instructions). For each bit of the pattern that

the

corresponding point is intensified; for each bit that is a 0, the corresponding point is left dark.
In Figure 3-14, the circles represent the points of array; the small

numbers refer to the

corresponding bit positions of the pattern word. The small arrows show the order in which the
pattern bits are examined and displayed.

As with DIS, the vertical coordinate is held in the

Accumulator. The horizontal coordinate is held in register 0001 for this reason, register 0001
;

cannot be used as a 18-register with DSC. The character may be displayed in either of two sizes:
full size, in which the spacing between points in both directions is four grid positions, and
half-size, in

which the spacing is two positions. The following description assumes full-size

characters.

When a DSC instruction is executed, the following events occur:
(1)

The intensification pattern is transferred from Y to the display control Intensification

Buffer.
(2)

The contents of AC3-6 are placed in the display control Y-buffer; AC7.1 , are set to SOg.

The contents of register 0001, the X-coordinate, are incremented by lOg, and transferred to
the display control X-buffer.

3-32

The foregoing operations take 4.8 or 6.4 /us to do their work, after which the central processor
is

free to resume program execution.

The remaining operations are performed by the display

control.

(3) The pattern word is examined in the order shown in Figure 3-14. The time required to scan
and display the points varies according to the number of points to be intensified. Reaching the
first

point requires 20 jUS, then 1 jus for each point to be left dark and 3 /us for each point to be

displayed. This action continues until all points are intensified.

Because of the manner in which the Y-coordinate is used, full-size character arrays may start
only at coordinates which are multiples of 408 e.g., 000, 040, 100, -100. Since the array itself
;

only SOg points high, this gives the programmer an automatic vertical spacing of lOg points

between the bottom of one line and the top of the one immediately below it.

Y+308(FULL SIZE)
[Y+l4g,HALF size]
(2)

©^

O
©
©
©
©-

X+I08( FULL SIZE)
X+ 48 (HALF SIZE)

Figure 3-14. Display Pattern for DSC

3.4.3

Half -Size Characters

If the programmer clears the CHARACTER SIZE bit of the Special Function
Register [ESF with C(AC4) = 0] all
increments are by two grid positions, rather than four. AC3-7 provides the initial Y
coordinate; after the two
coordinates have been transferred to the display control's buffers, the contents of
ACg-i will be 1
and the
,

j
X
48,
coordinate in register 0001 will be incremented by 4 instead of by lOg. Vertical spacing is likewise
halved; arrays
may start at intervals of 208 points, with 4 points between lines. I/O PRESET sets this bit of the Special

Function

3.4.4 Character Set

Any character that can be represented on a 4 x 6 grid (24 points) can be displayed by using two DSC instructions,
with two consecutive storage words providing the complete 24-bit character pattern. Table 3-1 lists
the display
patterns for the ASR-33 character set. Nondisplayed characters have patterns of all zeros.

The table entries, each

consisting of two words, are arranged in order of ASCII codes.

3-33

Table 3-1. ASR-33 Character Set Display Pattern

External

Internal

Character

ASCII

Code

245

246

211

TAB

250

251

252

253

254

255

256

(

Character

Pattern

External

Internal

Words

ASCII

Code

3114
0643
5166
0526
0000
0000
3600

274

275

276

277

4100
0036
2050
0050
0404
0437
0500
0006
0404
0404

301

302

303

304

305

0001

306

0412
2100
1212
1212
0021

1204
4020
2055
4477
7744
5177

0041
)

—

2651

4136
2241

4177
3641

4577
4145
4477

4044
4136
2645

0000
257

260

0601

307

4030
4136

310

2101

0177
4523

262

263

311

7741

0041

4142
4076

312

313

1077

4324
0177

M
N

2151

4122
2651

264
265

64
65

4
5

2414
0477
5172

314

0301

315

0651

266

1506
4225

316

267

4443
6050
5126

317

320

321

2200
0000

322

4601

323

270

271

272

273

3651

0000

3-34

3077

7730
3077
7706
4177
7741

2651

5122

1077

7710

3641
261

Pattern

Words

4477
3044
4276
0376
4477
3146
5121
4651

Table 3-1

External

Internal

ASCII

Code

324

325

ASR-33 Character Set Display Pattern (cont)

Character

nternal

Character

Pattern

External

Words

ASCII

Code

4040
4077
0177

335

]

336

212

Words

FEED

0000
0000
0000
0000

0000

LINE

327

SPACE

7701
1463

240

330

6314
0770
7007
4543

241

242

6151

215

RETURN

244

331

3.5

0176
7402
0677

332

333

[

334

4177
0000
0204
1020

0000
7741

7701

326

Pattern

0000
7500
0000
7000
0070
0000
0000
4731

4275

DATA TERMINAL

The Data Terminal provides analog inputs and relay-controlled outputs for use by LINC mode programs. The
facility includes the following:

3.5.1

The

Analog Inputs

Sixteen channels

Relays

Six relays for external equipment control

Auxiliary Scope Connector

24-pin connector for an auxiliary CRT

Analog Inputs

AD 12 Analog-Digital Converter and Multiplexer consists of 16 input channels, a Sample and Hold, a

multiplexer, and a 10-bit A-D converter. Eight of the channels are for external inputs via phone jacks. These feed

through preamphfiers to the multiplexer. The acceptable voltage range of these inputs is ± Iv with a sensitivity of

approximately 2 mv/count.

The other eight channels are controlled by continuously variable knobs mounted on the Data Terminal. The knobs
give ten turns stop-to-stop however, 7 turns provide the full 10-bit range to the converter (1-1/2 to 2 turns from

each extreme is beyond the A-D range of -111^ to +111 ^). The knobs can be used to control speeds (as in the

continuous display of data from tape), set threshold levels or other test parameters, etc.

A single LINC mode instruction selects the input channel, initiates the conversion, and transfers the contents of the
buffer into the AC.

3-35

SAM

Sample

Form:

SAM N

Octal code:

0100 + N,

Execution time:

18.2 jUs (Normal mode); 1.6 //s (Fast sample mode)

Operation:

Input channel N is selected. In normal mode, the voltage level present at the input is sampled

< N < IVg (Basic system);

< N < STg (extended system)

and converted to a 1 0-bit number (including sign), which is assembled in the converter buffer.

When the conversion is complete, the contents of the buffer are transferred into AC3-1 1 The
•

sign is placed in AC0-2

When the FAST SAMPLE Special Function is selected [ESF with C(AC5 ) = 1], the order of
events is reversed. The current contents of the converter buffer are transferred to the AC. Then
the specified channel

selected

and a new conversion is initiated. The results of this new

SAM instruction, unless the KW12-A Real Time
mode 4, 5, 6, or 7; in this case only, the KW12-A may initiate the

conversion can be read by a subsequent
Interface

selected to

A-D conversion. If a conversion is still in progress when the next SAM is encountered, the processor waits until the conversion is complete before executing the new SAM.

3.5.2 Relays

Six DPDT relays mounted on the Data Terminal can be switched by LINC mode instructions, allowing the user to
control the operation of various pieces of external equipment that are not interfaced directly with the PDF- 1 2. The
states of the relays can be

examined at any time. One set of form C contacts for each of the relays is available at
the binding posts on the Analog Input Panel as indicated in Figure 3-15. A second set of contacts is brought out to
spht lugs on the relay printed circuit board.

N.O,

N.C.

COM
RELAY

AC BIT
1

4
5

o
o
o
o
o
o

6
7
8
9

10
11

12-0209

Figure 3-15. Relay Terminals and Corresponding AC Bits

3-36

ATR

AC to Relays
0014

Octal code:

Execution time

1 .

6 jus

The contents of ACg-ii

Operation:

are transferred to the Relay Buffer; the state of each relay

determined as follows:
If the corresponding
If the corresponding

RTA

AC bit is 0, the relay is switched off.
AC bit is the relay is switched on,
1 ,

Relays to AC

0015

Octal code:

Execution time:

1.6 /xs

Operation:

The contents of the Relay Buffer

are transferred into

corresponding bit will be 0; if it is on, the bit will be

3.6

ACe-ii-

If the

relay

off,

the

Bits ACq-s are not changed.

LINCTAPETYPETC12

The basic LINCtape system consists of either two DECtape Transports Type TU55 or one DECtape Transport Type
TU56 controlled by a fully buffered subprocessor. A single ten-channel tape head serves for both reading and
writing. Information is redundantly recorded; one line of tape contains five bits, each recorded in two non-adjacent
channels, as shown in Figure 3-16. Three bits are actual data; the other two provide control information for the
tape processor. The Timing track determines the position of each recorded line. Four lines are required to
accommodate a full 12-bit word; the corresponding Mark Track code identifies the nature of the data word. The
recording technique and tape layout are described in detail in the PDP-12 Maintenance Manual.

3.6.1

Organization of Data

On a standard-format LINCtape, information is recorded in blocks of 256 12-bit words each, with identifying data
at
1

One reel of Standard format LINCtape has a capacity of 512 blocks, for a total of
words of data. (In other formats, this capacity may be extended to 225,000i o words.)

each end of the block.

3 1 ,072 1

The organization of a tape is schematically presented in Figure 3-16. At each end of the tape is a long End Zone
which allows the transport to reverse direction or come to rest without pulling the tape off the reel. Between the
end zones and the terminal blocks, and between blocks, are Interblock Zones which can be sensed by the LINC
instruction IBZ. An interblock zone is 5 words long.

Figure 3-1 6B represents a typical block of 256 data words preceded and followed by control and identifying
information. The serial bit sequence on the Mark Track, is decoded so that the control can determine whether the
adjacent data bits form true data, checksum words, guard words, etc. The symbols BM, CM, GM, etc. (defined

below), refer to these Mark Track bit patterns.

3-37

2
<<
_l
tr.

r^'^^A

CO
o
o
O UJ <

Q 2
2 o
U N

LjJ

o
o
_J UJ
m Z
a: o
UJ N
1z
—
z *
m o

O CO

°^

o <
< a:

^ 2
< 1

5 <
irffls

z to
m o

•-«

5 I-

E *
6

\aJ

•V/N/

2
3
COQ /"

N ^ ro N ^

CD i£

E ^

•^

m 0) ^ lO (D

O ^ CD O t OO

U
,-1

UJ*
CD

I
o

"o^

Q::

2
ro

CVJ

CD i£

<
Q

^ CM ro ^

cvj

_i _i -I -I _i -I
UJ UJ UJ UJ UJ UJ

K/sys/vJ

z o
CO
1

^
o

a2
< <
_1
Ul
UJ

^.W^

-JO.

3<
u-t-

3-38

>O ^
IT

a UJ
zz
o

<<<<<<
XXXIII
O
uo o o
<<<<<<K
<<<<<<
a Q oa o o
CJ

o
_l UJ
CD z
tc o
UJ N
1z

z z zz z z
2 Z ZZ Z Z

I- I- I- I- I-

>>.

A block consists of 256 data words preceded and followed by control and identifying information, as shown in the
second drawing in Figure 3- 1 6.

Block Number

This identifies the block.

On a standard LINCtape, block numbers are

sequential, from 0000 through 07778

(BM)
Guard Word

This protects the Block Number from transients when the read/write current

(GM)

turned on and off, and allows time for the tape processor to switch from

Search to Read or Write modes.

Data Words

This is the information recorded on tape from core memory. The final Data
Word is specially identified, to signal the end of the block. When writing a

(DM,FM)

tape, this signal conditions the tape processor to write the checksum in the

next word position.

Checksum
(CM)

This is the two's complement of the 12-bit sum of all the data words in the

block plus the constant 1111^. The result of adding the data sum to the

checksum should be 0000; this provides a check (hence the name) on the
accuracy of the transfer.

Check Words

These are dummy words whose Mark Track code is the same as that for the

(CM)

Checksum. They are provided to insure that the Write current will be turned
off before the Reverse Block Number is encountered. The Guard and Check
words are not of general interest to the programmer except as they affect
timing.

Reverse Block Number

This

the Block

Number that identifies the

block

when tape is being

searched in the reverse direction.

(RBM)
Subprocessor

The LINCtape processor controls all information transfers between memory and tape. It is fully buffered; once an
operation has been initiated by a LINC mode instruction, it is carried to completion by the tape processor. The
central processor

may either wait unfil the tape transfer is complete, or proceed immediately after the tape

instruction has been initiated, testing at some later time for completion of the operation.

Transfers are effected in either Standard or Extended modes. In Standard mode, transfers are made to and from
fixed

memory locations. Extended Operations provide for a flexible addressing facihty, program interrupt, and

additional tape units.

As can be seen in Figure 3-17, the tape subprocessor contains seven registers which provide the transmission path
for data and for control information.

Data Path

Read/ Write Buffer (RWB), 12-Bits - When reading, the four Lines of a data word are assembled in this register, in
the

bit

positions

shown

in the third drawing of Figure 3-16.

When writing, the contents of the RWB are

disassembled and written on four consecutive lines of tape. Essentially, the RWB is a three-section shift register,

with the three bits of a tape line entering (or leaving) the register at four-bit intervals, as indicated by the arrows in
Figure 3-17.

3-39

TAPE
HEAD

SEARCH ONLY

TBN

RWB

12 bits

SHIFT

12 bits

7^
TMA

12 bits

ADDER
READ/SEARCH

WRITE

TMA

SETUP

12 bits

ADDER

XOB

c
READ/
WRITE

TB + TAC

12 bits

2:^1

TAC

12 bits

LINCtape

PROCESSOR

c
CENTRAL
PROCESSOR

CZZIZll) TAPE DATA
CONTROL INFORMATION

(

12 BITS )

Figure 3-17. LINCtape Processor Information Paths

Tape Buffer (TB), 12 Bits — When reading, the assembled word is transferred from the RWB to the TB, and from
there sent to the

MB in the central processor. When writing, the direction is reversed; information from the MB
RWB for disassembly onto the tape.

enters the TB, and from there is placed in the

Tape Accumulator (TAC), 12 Bits — As each data word is read or written, the data sum is accumulated in the TAC.
When reading, this sum is added to the Checksum read from tape, to determine whether the transfer was completed
accurately. When writing, the data sum is complemented when the final data word signal is received, and the
resulting Checksum is written in the word position following the final data word. The contents of the TAC can be

brought into the central processor AC, using the Line mode TAC instruction. In searching operations, the TAC also
holds the sum of the desired block number and the last block number read from tape.

Control Registers

In Standard mode operations, these registers are automatically set up; in Extended Operations, the program must
set the

3-40

XOB and TMA Setup Register.

Tape Block Number (TBN), 12 Bits - This contains the number of the block to be accessed in a data transfer. As
the tape is searched, the Block Number read from tape

is compared with that in the TBN; when the numbers
match, the tape is positioned so that the transfer can begin. During group operations, the TBN contains the number

of the first block to be accessed.

Tape Memory Address (TMA), 12 Bits - This contains the address of the memory location to or
from which the
data is being transferred. In extended address mode, TMA is loaded from the TMA Setup
Register at the beginning
of a tape instruction; in Standard mode, the MBLK and TBLK information in the
second tape instruction word are
used to determine the initial contents of TMA, The TMA is incremented by 1 for each
data word transferred.

TMA Setup Register, 12 Bits - In Extended Address mode, the register retains the first memory address of the data
to be transferred. If the transfer is not successful, the contents of

TMA

Setup are placed in the TMA, and the
operation is repeated. The TMA Setup Register is loaded from the AC, using the TMA instruction.

Extended Operations Buffer (XOB) 12 Bits - The contents of this register determine which of the various
extended tape operations are in effect. These include extended memory addressing, tape interrupt, the no-pause
condition, hold motion, and extended units.

3.6.2

Programming

The tape transfer operations are the same for both Standard and Extended Operation modes. Data may be read or
written in single blocks or groups of contiguous blocks (in the extended address mode, only single blocks
are
transferred), with or without error-checking. Step-by-step searches can be performed, and block numbers can
be
identified without reading or writing data.

All

LINCtape instructions require two words. The first word specifies the operation to be performed, one of two

tape units, and the motion of tape at the end of the operation. The second word gives the tape block number and
in Standard mode also gives the memory block number. The structure of the two words is shown in Figure 3-18.

FIRST WORD

' '

9
V.

OPERATION
MOT! ON

SECOND WORD

INSTRUCTION CODE

MUST BE =0
^_A_.

UN IT

BLOCK NUMBER (EXTENDED ADDRESSING)

A
2

"~Y

MEMORY BLOCK
NUMBER

TAPE BLOCK NUMBER (TBLK)

(MBLK)

Figure 3-18. LINCtape Instruction Format

3-41

The general instruction code for the LINCtape class is 0700. The particular
operation to be performed is specified by bits 9-1 1 of the first word. In the

First Word

basic system, one of the two TU55 units is selected by bit 8. If this bit is 0,

the unit dialed to

selected; if this bit is a

unit

is chosen.

Bit 7 (the

I-bit) is used to determine the state of the unit's motion when the operation
is completed.

See Paragraph 3.6.3 below.

In Standard Addressing, bits 3-11 of the second word specify the number of

Second Word

the tape block to be accessed. Bits 0-2 specify one of four blocks of a LINC

Memory Field to or from which data is to be transferred. These memory
blocks are assigned to specific addresses in each field. There are four blocks
in each LINC field, each being 256 words (1 tape block) long. The blocks are

assigned as follows

Memory
Block Number

(MBLK)

LINC

LINC
Memory Field

Field Addresses

Instruction Field

0000-0377

Instruction Field

0400-0777

Instruction Field

1000-1377

Instruction Field

1400-1777

Data Field

2000-2377

Data Field

2400-2777

Data Field

3000-3377

Data Field

3400-3777

memory block correspond exactly. All
of
single-block transfers are effected between the tape block and the memory block specified by the second word
In

Standard

Mode

addressing,

the contents of a tape block and a

the tape instruction. In group transfers, where several contiguous blocks are transferred, the second word is
instructions in Paragraph 3.6.4.) The two
interpreted in a slightly different way. (See description of RCG and

WCG

non-transfer instructions, MTB and CHK, use the second word in still different ways.

3.6.3

Tape Motion

Tape is read or written in the forward direction. It may be searched in either the forward or backward direction.
operation
Bit 7 of the first word of a LINCtape instruction determines the motion of the tape when a LINCtape
has been completed.
If bit 7 (the I-bit) is set to a 1, the tape

left

moving in the direction in which it was going at the completion of

the operation. Except for searches backward, this will usually be the forward direction.

the tape processor enters the Turnaround State at the completion of the operation, which is
Checkword
State. When a block mark is encountered, the tape stops, leaving the Turnaround State
the end of the
and entering the Idle State. If a subsequent tape instruction occurs while the tape processor is in the Turnaround
If bit 7 is set to a 0,

State, searching begins with the tape moving forward.

3-42

If the tape has stopped, a subsequent tape instruction will begin with tape motion in the backward direction. It will

search backwards until a block number has been encountered. This first block number is used to determine the

required direction to complete the instruction.

NOTE
The foregoing discussion

applies only to tape

instruction. It should not be confused with the

motion

at the

completion of an

NO PAUSE Extended Operation,

which affects central processor action after a tape operation has begun.
3.6.4

LINCtape Instructions

In the subsequent instruction descriptions, the following terms are used:

Data sum

two's complement sum of all 256 data words in a block

Checksum

two's complement of (Data sum + 1111 s )

Data sum + Checksum + 1111^

Transfer check

If the transfer is successful, the transfer check = 1111^

If not, the transfer check 7^ 1111 ^

MBLK, TBLK

As shown in Figure 3-18

NOTE
It is

assumed that Extended Address and NO PAUSE are

not used in the following discussion.

RDE

Read Tape

Form:

RDE

Octal code:

0702 + 201+ lOU

Execution time:

3.2 JUS

Operation:

Block TBLK is read from tape into

memory block MBLK. The transfer check is left in the

TAC and AC. The contents of the tape are unchanged.

RDC

Read and Check

Form:

RDC

Octal code

0700 + 201 + 1 OU

Execution time:

3.2 jus

Operation:

Block TBLK is read from tape into memory block MBLK. If the block is transferred correctly,
the transfer check

left in the

TAC and AC; otherwise, the operation is repeated. The

information on tape is unchanged.

RCG Read and Check Group
U

Form:

RCG

Octal code:

0701 + 201 + lOU

Execution time:

3.2 //s

Operation:

Block TBLK is read from tape into the memory block designated by the three low-order bits
of TBLK; e.g., tape block 773 is read into memory block 3, tape block 027 into memory block
7.

The next consecutive tape blocks are read into successive memory blocks. Tape block 000
follows memory block 7. MBLK is the number of

follows tape block 777, and memory block

additional consecutive blocks to be transferred.

3-43

Example: Transfer blocks 202-205 from unit 1 to memory, leaving the unit in motion at the end.
Instruction

Octal

RCG I

0731

3202

/READ AND CHECK GROUP INST
/MBLK = 3, THE NUMBER OF ADDITIONAL BLOCKS

3202

/TBLK = 202.

Data is transferred from tape block 202 into memory block 2, then from 203 to memory block 3, 204 to memory
block 4, and 205 to memory block 5.

Each block transfer is checked. If the transfer is successful, the transfer check (7777) is left in the TAC; otherwise,
that block is repeated. If the entire group is transferred successfully, 7777 is left in the TAC and

AC at the end of

the operation.

WRI

Write Tape

Form:

WRI

Octal code:

0706 + 201 + lOU

Execution time:

3.2 /xs

Operation:

The contents of memory block MBLK are copied into block TBLK; the transfer check is left in
the TAC. The contents of memory are unchanged.

WRC

Write and Check

Form:

WRC

Octal code:

0704 + 201+1 OU

Execution time:

3.2 /lis

Operation:

The contents of memory block

MBLK are copied into block TBLK. If the transfer is

successful, the transfer check (7777) is left in the

TAC and PAC; otherwise, the operation is

repeated.

WCG

Write and Check Group

Form:

WCG

Octal code:

0705 + 201+1 OU

Execution time:

3.2 jus

Operation:

MBLK is the number of additional consecutive memory blocks whose contents are written on
The low-order digit of TBLK specifies the first memory block to be accessed. The
contents of this block are copied into block TBLK of tape. The contents of the next MBLK
tape.

memory blocks are copied into the next successive tape blocks. Memory block
follows
memory block 7, and tape block 000 follows block 777. The scheme is identical with that for
RCG. If the transfer is successful, the transfer check (7777) is left in the TAC and AC;
otherwise, the operation is repeated.

3-44

The following two instructions do not transfer data.

MTB Move Toward Block
Form:

MTB

Octal code:

0703 + 201 + lOU

Execution time:

3.2 ]us

Operation:

first tape block number encountered (or reverse block number, if the tape is
moving backwards) from TBLK, leaving the difference in the TAC and AC. If 1 = 0, the tape
stops. If I = 1 the tape is left moving forward if the difference is positive or 0, and backward if

Subtract the

negative. If motion =

when this instruction is given, it starts moving backward; otherwise it

continues in the direction in which it had been going. The MBLK bits of the second word are
ignored.

CHK

Check one Tape Block

Form:

CHK

Octal code:

0707 + 201 + lOU

Execution time:

3.2 jus

Operation:

Find block BN, form its transfer check and leave it in the TAC and AC. The information on
tape and the contents of memory are unchanged.

The contents of the Tape Accumulator can be examined by using the following instructions.

TAC

Tape Accumulator to AC

0003

Octal code:

Execution time:

1.6 jus

Operation:

The contents of the Tape Accumulator are placed in the central processor AC. The previous
C(AC) are lost; C(TAC) are unchanged. This instruction is used to verify transfer Checksums
for

NO PAUSE tape operations. Because this instruction uses the tape ADDER data path, jt

must not be given while a tape operation is in progress.
3.6.5

Extended Operations

LINCtape Extended Operations give the programmer a more flexible addressing scheme for information transfers,
additional control functions, and a tape processor maintenance facility. These operations are controlled by the

contents of the Extended Operations Buffer, defined as shown in Figure 3-19. The XOB can be loaded from the AC

and vice versa. The function of these bits is described in Paragraphs 3.3.6 through 3.6.12.

EXTENDED OPERATIONS BUFFER (XOB)
1

EXTENDED
MEMORY
ADDRESS

MARK
CONDITION

ENABLE
TAPE
INTERRUPT

MAINTENANCE

MODE

HOLD
UNIT

MOTION

DO NOT
PAUSE DURING
EXECUTION

ENABLE
EXTENDED
ADDRESS
MODE

Figure 3-19. Extended Operations Buffer Bit Assignments

3-45

AXO AC to XOB
0001

Octal code:

Execution time:

1.6 /us

Operation:

The contents of the AC are placed in the Extended Operations Buffer. The previous C(XOB)
are lost; C(AC) are unchanged. Changing these states while a tape operation is in progress may
cause incorrect execution.

XOA

XOB to AC
0021

Octal code:

Execution time:

1,6 jUS

Operation:

The contents of the Extended Operations Buffer are placed in the AC. The previous C(AC) are
lost;

C(XOB) are unchanged.

This instruction must not be given when the tape is in progress because the data path inchides
the tape ADDER.

3.6.6

Extended Address Format

This facility releases the programmer from the limitation of block-to-block transfers, as described previously.
Instead, a block transfer may begin in any register of any memory field, regardless of the settings of the Memory

Field Registers. The first memory address affected in the data transfer is placed in the

TMA Setup Register by the

program, using the instruction TMA. When the Extended Address Mode is enabled (by setting bit 7 of the XOB to
1),

all

subsequent tape transfers are executed as follows. At the occurrence of a tape transfer instruction, the

contents of the
1

1-bit block

TMA Setup Register are placed in the TMA. The second word of the instruction is taken as an

number, and placed in the TBN. The transfer is effected between tape and the designated area of the

4096-word memory bank specified by bits 0-2 of the XOB. The transfer is thus independent of the LINC Memory
Field assignments.

As in all extended memory operations, whether with tape or not, the transfer will not cross 4096io memory field
bank boundaries; address 7777 is followed by address 0000.

NOTE
The group transfer instructions RCG and WCG cannot be used in extended address
mode.

TMA

Load TMA Setup Register

Octal code:

0023

Execution time:

1.6 /us

Operation:

The contents of the AC are placed in the Tape Memory Address Setup Register. The previous
contents of TMA Setup are lost; C(AC) are unchanged. This instruction must not be given
when the tape is in progress because the data path includes the tape ADDER.

3-46

Example:

Read the contents of block 365 of unit

into

memory, beginning at absolute location 105408

(05408 in the second 4096i g-word bank of memory).

Instruction

Code

LDA

1020
0540
0023

Action

1020

AXO

0001

/LOAD AC WITH STARTING ADDRESS
/STARTING ADDRESS OF TARGET AREA
/PLACE STARTING ADDRESS IN TMA SETUP
/LOAD AC WITH EXTENDED OPERATIONS BITS
/BANK 1; ENTER EXTENDED ADDRESS MODE
/LOAD XOB FROM AC

RDC

0700
0365

/READ AND CHECK FROM UNIT
/BLOCK 365

0540

TMA
LDA

0365

1020

The data will be read into registers 05408 - 11 378 of the second 4096i o-word bank of memory.

3.6.7 Extended Units

The two Extended Units bits (XOBio-ii) may be thought of as an extension of the unit bit of a LINCtape
instruction (bit 8). Taken together, the three bits can select one of up to eight transports which may be attached to
the

TCI 2 tape

control.

The

logical unit

numbers

are assigned

by rotating the

dials

on the transports; they

correspond to the unit select bits as follows:

Extended Unit
Bits (XOB)

Instruction

Unit Bit

Transport

Selected

1
1

3.6.8

Tape Interrupt Enable

When this bit (XOBj ) is set, a program interrupt will occur whenever INTERRUPT is enabled and the TAPE DONE
flag is set (i.e., the tape operation is completed). As with other LINC interrupts, control is transferred to register
0041 of memory field 0; the contents of the PC are stored m register 0040. (If the central processor is in the 8
mode, the interrupt uses registers 0001 and 0000.) TAPE DONE is set by the completion of a tape instruction and
cleared by the execution of a new tape instruction or the tape maintenance instruction LMR (lOT 6151) with
AC4(1). (See Paragraph 3.6.9 and Appendix E.)

3-47

3.6.9

No Pause Condition

Normally, the central processor waits until a tape operation is finished before proceeding. Such delays may be
eliminated by setting the NO PAUSE condition bit (XOBg). When this condition is enabled, the processor
continues with the program as soon as the LlNCtape instruction has been interpreted and the operation initiated.
Subsequently, the program can monitor the Tape Done flag to determine when the operation has finished. The

Tape Done flag is set when a tape operation has been completed and is cleared at the beginning of the next tape instruction. The flag can also be sensed and cleared by the following instructions. When in the no pause condition, a
second tape instruction should not be used until the previous tape instruction has been completed.

lOB

LMR

Load Maintenance Register

0500

Octal code:

6151
Execution time:

5.9 MS (LINC mode)

Operation:

The maintenance lOT (see Appendix E) is used to test and clear the TAPE DONE flag.
(ACo s = 1 ) Skip if Tape Done Flag is set.
(ACo4 = 1) Clear Tape Done Flag

Do not have other AC bits on a

STD

1 ,

as this instruction has many additional functions.

Skip if Tape Done

Form:

STD

Octal code:

0416 + 201

Execution time
Operation:

1 .6 //s

If I

= 0, skip the next instruction if no tape operation is in progress; otherwise, execute the

next instruction. If I = 1, skip if an operation is still in progress. This instruction is identical to

SXL I

16.

Used in conjunction with the tape flag and tape interrupt, the NO PAUSE condition can save
considerable amounts of time in central processor programming. When NO PAUSE is set, the
Transfer Check is not placed in the accumulator at the end of tape instruction. The instruction

TAC (see Paragraph 3.6.4) should be used to recover the Transfer Check.
3.6.10 Hold Unit Motion

Normally, a tape transport stops as soon as another unit has been selected.

When XOB9 is set, however, the

transport will continue in the direction it has been moving when the unit is deselected. This is a useful feature for
certain operations involving several units, and must be used with caution. Note that it is not the same as the motion
bit of a

LlNCtape instruction, which determines the motion state of a unit at the completion of an instruction

only.

NOTE
With the Hold Unit Motion and No Pause bits both set, it is impossible to do two backto-back tape instructions and enable both units
3.6.11

and 1 for simultaneous motion.

MARK Condition

This bit (XOB4 ) is used in conjunction with the MARK switch on the operator's console to allow the MARK 1
program (see Chapter 7 on Program Library) to record Timing and Mark tracks on a new tape. The interaction

between the switch and the XOB is designed to minimize the possibility of accidentally destroying a tape by
enabling the

MARK flip-flop. The flip-flop can be set only when the MARK switch is held down while an AXO

instruction is being executed with AC4 set to 1

3-48

3.6.12 Maintenance Mode

When XOBfi is set, all timing signals and data are prevented from entering the tape

control registers from the
by lOT instructions are used as input to the tape control, in order to
simulate the functions of the tape head and the tape processor. The
Maintenance Mode is designed for diagnostic
purposes and is not intended for general use. See Appendix E for a hst
of Maintenance Mode
reader-writers. Instead, signals generated

tape control

instructions.

3.6.13 Tape Trap

Whenever the TAPE TRAP and INSTRUCTION TRAP Special Functions are enabled (ESF with AC2-3 set),
LINCtape instructions are not executed. When one is encountered, a program trap to register 0140 of memory field
occurs. The Tape Trap is intended primarily for use with LlNC-8 programs and the 1/0 Handler
(LINC-8 Trap
Simulator) to ensure compatibility. Also, device-independent software can make use of Tape Trap to substitute
other mass storage devices, such as disks for LINCtape.

3.6.14 Tape Word Skip

TWC

Skip on Tape Word Complete

Form:

TWC

Octal code:

0417 + 201

Execution time
Operation:

.6 //s

This instruction is used when formatting a tape using the

MARK

2 Program.

3-49/3-50

CHAPTER 4
8

MODE PROGRAMMING

8-mode programming of the PDP-12 is covered in this chapter, which is divided into six sections: Organization of
Memory, Memory Addressing Methods, PDP-8 Instructions, Program Interrupt, Extended Arithmetic Element, and
Extended Memory.

4.1

ORGANIZATION OF MEMORY

4.1.1

Organization

In the 8 mode, the basic 4096-word memory is divided into 32 pages of 128 words each for addressing purposes

Within one of these pages, operands

may be addressed directly by memory reference instructions. Access to

operands across page boundaries (except for Page 0) requires indirect addressing.
Executable programs may be stored in any page of memory, and program sequences may extend across several
pages. The program counter is indexed over all

2 bits in the 8 mode, so that a straight-line program sequence will

from the last word of a page to the first word of the next. A programmed jump across page boundaries,
however, requires an indirect reference. The organization of one memory field in 8 mode is shown in Figure 4-1.
pass

4.1.2

The

PageO

first

page of memory (addresses 000-177) contains several registers reserved for special use, which the

.programmer must take into account. These are:

Use

Address

0000

During a program interrupt, holds C(PC).

0001

Contains the first instruction to be executed after a

program interrupt.

00 1 0-00 1

Automatic index registers (see Paragraph 4. 2.2).

4-1

PAGE (cx:tal)

z
3

4
5

6
7
10
11

12
13
14
15
16
17

20
21

22
23
24
25
26
27
30
31

32
33
34
35
36

Figure 4- 1

addresses

0000--0177
0200--0377
0400--0577
0600--0777
1000--1177
1200--1377
1400--1577
1600--1777
2000--2177
2200--2377
2400--2577
2600--2777
3000--3177
3200--3377
3400--3577
3600--3777
4000--4177
4200--4377
4400--4577
4600--4777
5000--5177
5200--5377
5400--5577
5600--5777
6000--6177
6200--6377
6400--6577
6600--6777
7000--7177
7200--7377
7400--7577
7600--7777

Organization of Memory, 8 Mode

4.1.3 Extended Memory

Additional 4K

memory fields are organized in the same manner as the basic field. The Memory Field registers

determine the assignment of fields (see Paragraph 4.6).

4.2

MEMORY ADDRESSING METHODS

4.2.1

Direct Addressing

In the 8 mode, all memory reference instructions have the same structure, which is shown in Figure 4-2.

4-2

Note that only seven bits (5-11) are available for use as an address. This is just sufficient to give access to 128
registers,

or exactly one page. The state of bit 4 of the instruction determines which of two possible pages the 7-bit

page address references. If this bit is

the page address is on the current page; that is, the one in which the

instruction itself is stored. If bit 4 is 0, the page address is on Page 0. Thus, a memory reference instruction has
direct access to a total of 256 registers of memory; the

28 locations of Page 0, and those of the current page.

Examples:

To store the contents of the AC in register 1 50 of the current page:

DCA

350

The page address is 150; bit 4 (Page bit) set to 1 gives a total octal

Octal code: 3350.

value of 350 for the address.

To store the contents of the AC in register 1 50 of Page 0:

DCA

Octal code: 3150. With the page bit set to 0, the complete octal address is 150.

150

As one can see from these examples, it is useful to think of page addresses running from 000-177 on Page 0, and
from 200-377 on the current page.

4.2.2 Indirect Addressing

To gain access to registers outside of Page
ory reference instruction is set to
as the "effective" address
ister in the

or the current page, indirect addressing must be used. If bit 3 of a mem-

(see Figure 4-2), the contents of the register designated by bits 5—11 are taken

of the operand. This is a full 12-bit number which gives the absolute address of any reg-

4K memory field.

MEMORY

OPERATION
CODE

PAGE

Y
INDIRECT

PAGE

ADDRESSING

ADDRESS

Figure 4-2.

Memory Reference Instruction Format

4-3

In the following examples, as in normal 8 mode programming, the letter I is used as a mnemonic to represent the

presence of a 1 in bit 3.

Examples:

To store the contents of the AC in register 100 of page 10 (absolute address 2100), using an effective

address stored on the current page:

Address

Contents

0410

DCA

0500

2100

Action

300

/OCTAL CODE: 3700. THE
/EFFECTIVE ADDRESS IS

/CONTAINED IN REGISTER 500,
/(PAGE ADDRESS 300)

To store the C(AC) in register 2100, using an effective address stored in Page 0:

Address

Contents

0050

2100

0410

DCA

Action

/EFFECTIVE ADDRESS, STORED
/ON PAGE
/OCTAL CODE: 3450. (BIT 4=0)

Summary of Addressing Methods in 8 Mode

Table 4-1.

Bit 4

Bit 3

Effective Address

The operand is in Page
bits 5 through

at the address specified by

1 1

The operand is in the current page at the address
specified by bits 5 through 1 1

The absolute address of the operand is taken from

the contents of the location in Page

designated

by bits 5 through 1 1

The absolute address of the operand is taken from

the contents of the location in the current page

designated by bits 5 through 1 1

4.2.3 Autoindexing

The eight registers in locations 10-17 of Page
such a register are

incremented by

have a special function when indirectly addressed. The contents of

is taken as the effective address of the operand. This
autoindexing feature allows the programmer to address a series of contiguous locations without extra address

first

1 ;

the result

modification, as shown in the following example.

4-4

Example:

To obtain the sum of 100 numbers stored in registers 1000-1077.
Address
Label

Instruction

CLA
TAD

GO,

/CLEAR THE AC
LIST

DCA 10
TAD COUNT
DCA INDEX
TAD
10

LOOP,

Operation

/PUT 777 IN AC (ADDRESS- 1 OF THE TABLE OF NUMBERS)

/DEPOSIT IN AUTOINDEX REGISTER 10. (CLEARS AC)
/PUT -1 00 IN AC (COUNT OF ADDENDS IN TABLE)
/DEPOSIT IN REGISTER FOR COUNTING
/C(10) INCREMENTED BY 1, THEN USED AS

/EFFECTIVE ADDRESS TO GET ADDEND FROM TABLE
ISZ

[NDEX

]

/INCREMENT COUNT. IF RESULT IS 0000, SKIP
/THE NEXT INSTRUCTION.

JMP LOOP

HLT

END,

/IF NOT FINISHED,

GO BACK TO GET NEXT ADDEND
/WHEN FINISHED, STOP; AC CONTAINS THE SUM

LIST,

777

COUNT,

-100

/ADDRESS- OF TABLE OF ADDENDS
/COUNT OF TABLES ENTRIES

INDEX,

0000

/HOLDS COUNT DURING EXECUTION OF PROGRAM

When register 10 is first accessed, its contents are incremented from 777 to 1000, then used as the effective address
to obtain the first addend. The next time around the loop, C(10) is again incremented by 1, to 1001, for the next

operand. At the end of the sequence, C(10) = 1077.

4.3 8

MODE INSTRUCTIONS (See Appendix B)

4.3.1

Memory Reference Instructions

There are six memory reference instructions: DCA, TAD, AND, ISZ, JMP, and JMS. All may use either direct or
indirect addressing. When indirect addressing is specified, 1.6 microseconds is added to the execution time.

DCA

Deposit and Clear A ccumulator

DCA v
3000 + Y

Form:
Octal code:

Execution time:

3.2 ixs

Operation:

The contents of the AC are deposited in register Y; the AC is then cleared to 0000. The
previous C(Y) are lost.

TAD

Two

Complement Add to Accumulator

Form:
Octal code:

TAD v
1000 + Y

Execution time:

3.2 /xs

Operation:

The contents of Y are added to the contents of the AC, using two's complement addition. If
there is a carry out of bit 0, the Link is complemented; otherwise, the Link is unchanged. The

previous contents of the AC are lost; the contents of Y are not changed.

4-5

AND

Logical

AND to Accumulator
AND Y
0000 + Y

Form:
Octal code:

Execution time:

3.2 jus

The contents of the AC and the contents of Y are combined according to the Boolean AND
relation, with the result left in the AC. The operation is performed on corresponding bits of
each operand, independent of the other bits in the two operands. The truth table for the AND
relation is shown below:

Operation:

C(ACj)

C(YO
1

When corresponding bits of AC and Y are both 1

the result is 1

Otherwise, the result is 0. The

previous C(AC) are lost; the C(Y) are unchanged.

ISZ

Increment And Skip If Zero

Form:

ISZ

Octal code:

2000 + Y

Execution time:

3.2 jus

The contents of Y are incremented by 1. If the result is 0000, the next instruction in sequence
is skipped; otherwise, the next instruction is executed. The contents of the AC are not

Operation:

affected.

JMP

Jump

JMP Y

Form:

5000 + Y

Octal code:

Execution time

Operation:

IMS

6 jus

The address Y is placed in the PC, and the next instruction is taken from register Y; the
program continues from that point. The contents of the AC are not affected.

Jump to Subroutine

Form:

JMS Y

Octal code:

4000 + Y

Execution time:

3.2 jus

The contents of the PC are stored in Y. The address Y + 1 is placed in the PC, and the program
continues from Y + 1 The contents of the AC are not affected. To return from the subroutine

Operation:

to the point at which the JMS was given (i.e., to the register immediately following the JMS),

JMP
Y is executed. The contents of Y are taken as the effective address;
Y contains the PC stored at the time of the JMS, control returns to the calling program.

the instruction
since

4.3.2 Operate Class Instructions

This class

divided into

two groups,

and II, Group I instructions include miscellaneous operations on the

Accumulator and Link. Group II instructions include skips, program halt, and access to the console switches.

4-6

operate

microprogrammable; they may be combined to provide several operations within a

class instructions are

single instruction.

However, combinations can be made only within a group; operations from different groups

cannot be combined. To ease this restriction, the operation CLA (Clear the AC) is available in both groups. All
Operate Class instructions require 1.6 microseconds for execution.

4.3.2.1

Operate Class: Group

- The microprogram structure of Group I instructions is shown in Figure 4-3. Any

combination of these functions can be made, but the programmer must be aware of the order in which the
operations are performed when the instruction is executed. This order is as follows:

CLA,CLL

CMA, CML

RAR, RAL, RTR, RTL

Certain combinations of Group

operations are

common enough to be assigned separate mnemonics. These are

described in Paragraph 4.3.2.2.

ROTATE
ROTATE POSITION IFO,
AC AND L 2 POSITIONS
1

OPERATION
CODE 7

CMA

CLA

CONTAINS

OTO

RIGHT

CLL

CML

SPECIFY

GROUP

Figure 4-3.

ROTATE
AC AND L
LEFT

lAC

Group I Operate Class Instruction Format

NOP No Operation
Octal code:

7000

Operation:

None. This instruction may be used to provide short delays (1.6 microseconds per instruction),
or to hold a place for instructions to be inserted by the programmer.

CLA

Clear A ccumulator

Octal code:

Operation:

CLL

7200
The contents of the AC are cleared to 0000.

Clear Link

Octal code:

7100

Operation:

The content of the Link is cleared to 0.

CMA

Complement Accumulator

Octal code:

Operation:

7040
The one's complement of the contents of the AC replaces the original contents of the AC.
Each bit that is becomes 1, and vice versa.

4-7

CML

Complement Link

Octal code

Operation:

lAC

7020
The content of the Link is complemented.

Increment Accumulator

Octal code:

7001

Operation:

The contents of the AC are incremented by 1, using two's complement arithmetic. A carry out
complements the Link.
of bit

RAR

Rotate Accumulator Right

Octal code:

7010

Operation:

The contents of the AC and Link, taken as a 13-bit register, are rotated right one position. A
bit rotated out of ACn enters the Link; the bit rotated out of the Link enters ACq. (See
Figure 4-4.)

RTR

Rotate Two Places R igh

Octal code:

Operation:

RAL

7012
The contents of the AC and Link, taken as a 13-bit register, are rotated two positions to the
right. (See Figure 4-4.) This is the equivalent of two RAR instructions.

Rotate Accumulator Left

Octal code:

Operation:

7004
The contents of the AC and Link, taken as a 13-bit register, are rotated one place to the left. A
(See Figure 4-4.)
bit leaving ACq enters the Link; a bit leaving the Link enters ACi
i

RTL

Rotate Two Places Left

Octal code:

Operation:

7006
The contents of the AC and Link, taken as a 13-bit register, are rotated two positions left. (See
Figure 4-4.) This is equivalent to two RAL instructions.

RAR

RTR
-'

RAL

RTL

Figure 4-4. Rotation Scheme for RAR, RTR, RAL, RTL

4.3.2.2

Combined Operations: Group

for programming convenience.

4-8

- The following combined operations have been given separate mnemonics

STA

Set Accumulator (CLA + CMA)

Octal code:

7240

Operation:

Clear, then complement the AC. Resulting C(AC) = 7777.

STL

Set Link (CLL + CML)

Octal code:

7120

Operation:

Clear, then complement the Link. Resulting C(L) =

CIA

Complement and Increment Accumulator (CMA + lAC)

Octal code:

7041

Operation:

Complement the AC, then increment the result by 1. This gives the two's complement of the
original C(AC). The two's complement of a number is defined as the one's complement plus 1.

GLK

Get Link (CLA + RAL)

Octal code:

7204

Operation:

Clear the AC, then rotate one place left, thus putting the contents of the Link into AC^ ^

This

instruction is useful in multiple precision arithmetic.

Other Useful Combinations — The programmer can place a number of selected constants in the AC by combining

Group I operations as shown
Octal Code

Resulting C(AC)

Combination

CLA
CLA
CLA
CLA
CLA

7201

7326
7325
7307
7327
7344

lAC

STL
STL

CLL
STL

7346

STA
STA

CLL
CLL

7330
7332
7333

CLA
CLA
CLA

STL
STL
STL

0001

RTL
lAC
lAC
lAC

RAL
RTL
RTL

RAL
RTL
RAR
RTR
lAC

RTR

0002
0003
0004
0006
7776 (-2)
7775 (-3)
4000
2000
6000

Group II — The microprogram structure of Group II operations is shown in Figure 4-5. Any
of these operations may be combined, but the programmer must be aware of the sequence of events. In addition,
the sense of the skip instruction determines the manner in which combined skips are interpreted. If bit 8 is a 0, the
4.3.2.3 Operate Class:

logical

OR of the tested conditions will cause a skip; if this bit is a 1, the logical AND of the conditions will cause

the skip. In the

first case,

this

means that the skip will occur if any one of the conditions tested is true; in the

second case, the skip will occur only if all the conditions tested are true. The various combinations are described in
Paragraph 4.3.2.4.

The sequence of events in a Group II instruction is as follows:
1.

Skips

CLA
3. OSR
4. HLT occurs after all other specified operations have been performed.
2.

4-9

OPERATION
CODE 7

CLA

SNA
OR
SZA

DETERMINES
SENSE
OF SKIP

HLT

X
1

W-^
CONTAINS 1
TO SPECIFY
GROUP 2

SMA
OR
SPA

SNL
OR
SZR

OSR

CONTAINS
TO SPECIFY

OPERATE ^
CLASS **

* THIS BIT DISTINGUISHES GROUP H OPERATE CLASS INSTRUCTIONS FROM THE
OPTIONAL EAE INSTRUCTION SET, IN WHICH THIS BIT IS SET TO 1.

Figure 4-5. Group II Operate Class Instruction Format

CLA

Clear

Octal code:

7600

Operation:

Clear the AC

SKP

Skip Unconditionally

Octal code:

Operation:

SNL

Skip On Non-Zero Link

Octal code:

Skip condition:

SZL

Skip condition:

7440
The contents of the AC equal 0000.

Skip On Non-Zero Accumulator

Octal code:

Skip condition:

SMA

7430
The contents of the Link equal 0.

Skip On Zero Accumulator

Octal code:

SNA

7420
The contents of the Link equal 1.

Skip On Zero Link

Octal code:

SZA

7410
The next instruction in the program sequence is unconditionally skipped.

7450
The contents of the AC are not equal to 0000.

Skip On Minus Accumulator

Octal code:

Skip condition:

7500
The contents of ACq equal
significant digit

4-10

By convention, a negative number is one in which the most

Thus, all numbers between 4000 and 7777, inclusive, are negative. The

two's complement of such a

number

its

positive counterpart.

In this sense,

7777

equivalent to -1; 4000 is equivalent to -4000. The two's complement sum of a number and its

two's complement is always zero.

SPA

Skip On Plus Accumulator

Octal code:

Skip condition:

7510
The contents of ACq equal 0. By the convention described above, a number is positive if its
most significant digit is 0.

OSR

OR Switch Register With Accumulator
7404
The contents of the console switch register (Right Switches) are combined with the contents
of the AC by the logical Inclusive OR relation; the result is left in the AC.

Octal code:

Operation:

If either bit of a corresponding pair is set to 1, the result is 1. The result is
only if both AC
and SR bits are 0. This instruction is normally used with CLA to obtain the actual status of the

Switches (see below).

HLT

Halt

7402
The processor stops. The PC contains the address of the register following the HLT instruction.
The contents of the other processor registers are not affected.

Octal code:

Operation:

LAS

Load Accumulator From Switches (CLA + OSR)

Octal code:

7604

Operation:

Clear the AC, then

OR the contents of the Right Switches with C(AC). This places the status

of the switches in the AC. If the switch is set to 1, the corresponding AC bit is set to 1.

4.3.2.4

Combined Skips In Group II - The possible skip combinations are listed, with the conditions for a skip to

occur.

Combination

SZA
SZA

SMA

SNL

SMA

SNL

SZA

SMA

SNL

A skip will occur if

Octal Code

7460
7540
7520
7560

C(AC)=0000, or C(L)=1, or both
C(AC)=0000, or C(ACo )= 1 or both
C(ACo )= 1 or C(L)= 1 or both
,

C(AC)=0000, or C(ACo)=l, or C(L)=1, or
any, or all of these.

A skip will occur if and only if
SNA
SNA
SPA

SNA

SZL
SPA
SZL
SPA

SZL

7470
7550
7530
7570

C(AC>^0 and C(L)=0
C(AC)=r^OandC(ACo)=0

C(ACo)=OandC(L)=0
C(AC)¥=0000 and C(ACo)=0 and
C(L)=0

CLA is combined with any skip, the AC is cleared after the conditions have been tested.
4-11

4.3.2,5 Input/Output Transfer Class - These instructions, all of which have the basic operation code of 6000, are
used to service peripheral devices, enable and disable the program interrupt, operate the memory extension control,

change from 8 to LINC programming mode, and provide maintenance operations for the LINCtape subprocessor.

Most of these instructions are described in Chapter 6 with their associated devices. The program interrupt and

memory extension control are discussed with their respective instructions in Paragraphs 4.4 and 4.6 of this chapter.

Mode Control - To change operating mode from 8 to LINC, the following lOT instruction is used.
Switch to LINC Mode

LINC

6141

Octal code:

Execution time

Starting with the next succeeding instruction, the central processor will operate in LINC mode.

Operation:

4.4

4.25 jus

PROGRAM INTERRUPT

Operation

4.4.1

To facilitate the handling of data transfers and the checking of peripheral device status, provision is made for
interrupting a program when a given condition exists. In general, an interrupt occurs when a peripheral device flag
is

raised

(i.e.,

when the device is available for service, when an operation has been completed, or when a specific

condition, such as an alarm, occurs within the device).

The Program Interrupt (PI) is enabled or disabled by the program. When it is disabled, a device flag must be sensed
by means of a skip; the program is not interrupted. When the interrupt is enabled, any device flag that is connected
to the interrupt system will cause the following sequence of events to occur when that flag is raised:

The instruction in progress at the time of the PI request is completed.

The contents of the program counter are stored in register 0000, and 0001 is placed in the PC.

Processing continues, beginning with the instruction in register 0001.

The PI facility is disabled.

The two lOT instructions which control the PI facility are described below.

ION

Interrupt On

6001

Octal code:

Execution time
Operation:

4.25 /xs

The

PI facility

enabled immediately after the instruction following the

ION has been

executed. If a PI request is waiting at the time of the ION, the interrupt will occur after the

next instruction has been completed. The enabling is delayed in this manner so that a PI
service routine can return to the interrupted program before a subsequent PI request destroys
the contents of register 0000.

4-12

lOF

Interrupt Off

6002

Octal code:

Execution time

4.25 jus

The PI facility is disabled. Subsequent requests will not cause a PI, although any flag causing a

Operation:

request may be sensed in the usual manner with an lOT skip.
4.4.2 Using the Program Interrupt

Normally, when a PI occurs, the instruction in register 0001 is a JMP to a PI service routine, which examines the

expected flags to determine which device or condition caused the request. The appropriate routine is then called to
service the device. During this time, the PI facihty is disabled. When the device service routine is completed, control

normally returns to the PI handling routine for restoring the PI facility and exiting to the main program. The last

two instructions of such a routine would be:

ION
JMP

/ENABLE PI FACILITY
/RETURN TO MAIN PROGRAM AT THE ADDRESS
/STORED IN REGISTER 0000

The PI is not enabled until the JMP I

has been executed, so that the return to the main program is completed

before a waiting request can cause another PI.

NOTE
Refer to Paragraph 3.3.15 for the discussion of additional aspects of Program
Interrupt during LINC mode programming.
4.5

EXTENDED ARITHMETIC ELEMENT TYPE KE12

4.5.1

Operation

The Extended Arithmetic Element (EAE), Type KE12, adds a complete automatic multiplication and division
facility to the PDP-12. Programming is provided by a class of 8 mode instructions. The AC and MQ are used to
accommodate full 24-bit products and dividends, and the remainder and quotient after a division. Shifting,
normalizing,

and

programmer must

setup instructions are included. All operands are treated as unsigned integers; the

establish

his

own

sign conventions.

The normalizing instruction

facilitates

the writing of

floating-point subroutines.

4.5.2

EAE Instructions

The EAE instruction set has a basic operation code of 7401 some functions are microprogrammable, as in Operate
;

Class instructions. The microprogram structure of the EAE class is shown in Figure 4-6.

CONTAINS

1T0

OPERATION
CODE 74

SPECIFY

MQA

MQL

EAE GROUP

Y
CLA

SCA

1=SCL

2»MUY 3=DVI
4*NMI 5»SHL
6*ASR 7=LSR
Figure 4-6.

EAE Instruction Format
4-13

As with other microprogrammed instructions, EAE operations are performed in a given order. Operations can be
combined in a single instruction, except that operations occurring at the same time cannot be combined with
meaningful results.

The order of events is as follows:

CLA
MQA,MQL, SCA

SCL, MUY, DVI, NMI, SHL, ASR, LSR

CLA

Clear

AC
7601

Octal code:

Execution time:

1.6 jus

Operation:

Clear the AC. The

CAM

Clear

AC and MQ
7621

Octal code:

Execution time:

Place

1.6 jus

The AC and the MQ is cleared.

Operation:

MQA

MQ and Link are unaffected.

MQ in AC

Octal code:

7501

Execution time:

1.6 jUS

Operation:

The contents of the MQ are ORed into the AC. The C(MQ) are unchanged.

NOTE
All twelve bits are

transferred;

this

not identical to the LINC mode

QAC

instruction (Paragraph 3.3.1 1).

MQL

Load MQ from A C
7421

Octal code:

Execution time

Operation:

SCA

1.6 jis

The MQ is cleared. The contents of the AC are placed in the MQ. The previous C(MQ) are lost.
The AC is cleared at the end of the instruction.

Step Counter to AC

Octal code:

7441

Execution time:

1.6 ms

Operation:

The contents of the step counter are ORed inclusively with the contents of AC7_] j the result
is left in the AC.
To obtain the actual step count, SCA is combined with CLA (combined op;

eration code:

7641).

All other EAE instructions, except NMI, require two words: the first contains the operation to be performed, the

second contains the operand. In the following descriptions, the notation p + 1 designates the register containing the
operand.

SCL

Load Step Counter

Octal code:

7403

Execution time:

3.2 /us

Operation:

The complement of the contents of bits 7-1 1 of p + 1 is placed in the SC.

4-14

MUY

Multiply

Octal code:

7405

Execution time:

9.0 ms

Operation

The number in the MQ is multipHed by the number in register p + 1 At the conclusion of this
instruction the Link contains a 0. The most significant 1 2 bits of the product are in the AC
.

and the least significant 1 2 bits are in the MQ.

DVI

Divide

Octal code:

7407

Execution time:

4.0 jus to 10.0 ^s

Operation:

The 24-bit dividend is held m the AC (most significant part) and MQ (least significant part);
the divisor is in register p + 1

At the conclusion of the division, the quotient is
the MQ, and
the remainder in the AC. If the division was carried out, the Link is left clear. If either
.

dividend or divisor is zero, the operation ends after one step and the Link is set to

indicate that a divide overflow occurred.

NMI

Normalize

Octal code:

7411

Execution time:

1 .6 /xs

Operation:

The AC and MQ are treated as a single 24-bit register. The combined contents of the AC and

+ 0.40 jus/step

MQ are shifted left until C(ACo

) differs from C(ACi ) or until 6000
0000 is contained in the
combined AC and MQ. Bits shifted out of ACq enter the Link; bits shifted out of the Link are

lost.

Zeros enter MQj j and are shifted up the registers. At the end of the operation, the SC

contains the

number of shifts performed, which is the exponent of the normalized floating

point fraction. The shift path is shown in Figure 4-7.

AC
LOST

-[>
MQ

Figure 4-7. Shift Path for NMI, SHL

SHL

Shift Left

Octal code:

7413

Execution time:

3.2 jUs + 0.40 jis/step

Operation:

The combined contents of the Link, AC and MQ are shifted left N + 1 places, where N is the
number contained in bits 7-1 1 of register p + 1. Bits shifted out of the Link are lost; zeros are
shifted into MQi j and up the registers. The shift path is identical to that for NMI, as shown in

Figure 4-7.

4-15

ASR

Arithmetic Shift Right

Octal code:

7415

Execution time:

3.2 //s + 0.40 Ms/step

Operation:

The combined contents of the AC and MQ are shifted right N + 1 places, where N is the
number contained in bits 7-1 1 of register p + 1 The sign bit (ACq) is reproduced in all vacated
.

bit positions,

and

also placed in the Link. Bits shifted out of MQi i

are lost, as

the

previous C(L). The shift path is shown in Figure 4-8.

LOST

Figure 4-8. Shift Path for ASR

LSR

Logical Shift Right

Octal code:

7417

Execution time:

3.2 jus + 0.40 /us/step

Operation:

The combined contents of the AC and MQ are shifted right N + 1 places, where N is the
number contained in bits 7-11 of register p + 1. Bits shifted out of the MQj i are lost; zeros are
shifted into the Link and down the register. The shift path is shown in Figure 4-9.

[hkiiHin

3
MQ

LOST
^m

Figure 4-9. Shift Path for LSR

EAE Programming

4.5.3

4.5.3.1

4-16

Multiplication - Multiplication is performed as follows:

Load the AC with the multiplier using the TAD instruction.

Transfer the contents of the AC into the

MQ using the MQL command.

Give the MUY command.

Note that steps 2 and 3 can be combined into one instruction.

The contents of the MQ are then multiplied by the contents of the next successive core memory location (p + 1).
At the conclusion of the multiplication the most significant 1 2 bits of the product are held in the AC and the least
significant bits are held in the

MQ. This operation takes 9.0 microseconds; at the end of this time, the next

instruction is executed.

The following program examples demonstrate the operation of the EAE during multiplication:
a.

Multiplication of 1 2-bit Unsigned Numbers

Enter v^^ith a 12-bit multiplicand in AC and a 12-bit multiplier in core memory. Exit with high order half of

product in a core memory location labelled HIGH, and with low order half of product in the AC. Program
time is approximately 1 3 microseconds.

MLTPLR,

MQL MUY

/LOAD MQ WITH MULTIPLICAND, INITIATE

0000

DCA HIGH

/MULTIPLICATION
/MULTIPLIER
/STORE HIGH ORDER PRODUCT

MQA

/LOAD AC WITH LOW ORDER PRODUCT

Multiplication of 1 2-Bit Signed Numbers, 24-Bit Signed Product

Enter with a 12-bit multiplicand in AC and a 12-bit multiplier in core memory. Exit with signed 24-bit

product in core memory locations designated HIGH and LOW.

CLL
SPA

CMA CML lAC
MQL

/MULTIPLICAND POSITIVE?
/NO. FORM TWO'S COMPLEMENT
/LOAD MULTIPLICAND INTO MQ

TAD MLTPLR
SPA

CMA CML lAC
DCA MLTPLR
RAL
DCA SIGN

MUY
MLTPLR,

0000

/MULTIPLIER POSITIVE?
/NO. FORM TWO'S COMPLEMENT

/SAVE LINK AS SIGN INDICATOR
/MULTIPLY
/MULTIPLIER

DAC HIGH
TAD SIGN

RAR
MQA

/LOAD LINK WITH SIGN INDICATOR

SNL
IMP LAST

/IS

PRODUCT NEGATIVE?

/NO, MULT DONE, EXIT

CLL CMA lAC

/YES

DCA LOW
TAD HIGH
CMA

/COMPLEMENT RESULT

SZL

/LINK USED TO COUPLE CARRY

/FROM BIT 12 TO BIT 11
/OF DOUBLE-LENGTH PRODUCT
lAC

DCA HIGH
SKP
LAST,

DCA LOW
4-17

4.5.3.2 Division — Division is performed as follows:

Load the least significant 1 2 bits of the dividend into the AC using the TAD instruction, then transfer the

contents of the AC into the

MQ using the MQL command.

Load the most significant 12 bits of the dividend into the AC.

Give the DVI command.

The 24-bit dividend contained in the AC and MQ is divided by the 12-bit divisor contained in the next successive
core memory location (p + 1). This operation takes a maximum of 10.0 microseconds; when complete, a 12-bit
quotient is held in the MQ, the 12-bit remainder is in the AC, and the Link holds a

if divide

occur. To prevent divide overflow, the divisor in the core memory must be greater than the

overflow did not

2 bits of the dividend

held in the AC. When divide overflow occurs, the Link is set and the division is concluded after only one cycle.

memory should be an SZL microinstruction to test for
SZL may be a jump to a subroutine that services the overflow. This

Therefore, the instruction following the divisor in core
overflow.

The

instruction following the

subroutine may cause the program to type out an error indication, rescale the divisor or the dividend, or perform
other mathematical corrections, then repeat the divide routine.

The following program examples demonstrate the use of the EAE in division,
a.

Division of 24-Bit Unsigned Numbers

Enter with the low order 12 bits of the dividend in the AC and the high order 12 bits of the dividend in

memory location labeled HIGH 12. The divisor is in memory location labeled DIVISOR upon entry. Exit
with the quotient in the AC and the remainder in location labeled REMAIN.

TAD HIGH 12

/CLEAR LINK FOR OVERFLOW CHECK.
/LOAD MQ WITH LOW ORDER DIVIDEND
/LOAD AC WITH HIGH ORDER DIVIDEND

DVI

/INITIATE DIVIDE

CLL

MQL
DIVISOR, (12 BIT DIVISOR HERE)

SZL
JMP EXIT

/OVERFLOW?

DCA REMAIN

/NO - STORE REMAINDER
/AND LOAD AC WITH QUOTIENT

/YES - EXIT

MQA
b.

Division of 24-Bit Signed Numbers

Enter with the low order 1 2 bits of the dividend in memory location labeled LOW 1 2 and the high order
12 bits of the dividend in

memory location labeled HIGH 12. The

12 bit divisor is in location labeled

DIVISOR. Exit with the unsigned remainder in location labeled REMAIN, and the signed quotient in the
AC.

CLA CLL
TAD HIGH 12
SMA CLA
JMP .+12

TAD LOW 12

CMA lAC
DCA LOW 12
TAD HIGH 12

4-18

/CLEAR AC AND LINK
/LOAD AC WITH HIGH ORDER DIVIDEND
/DIVIDEND NEGATIVE?
/NO - SKIP NEGATION
/YES - LOAD AC WITH LOW ORDER DIVIDEND
/NEGATE IT AND
/STORE IT BACK
/LOAD AC WITH HIGH ORDER DIVIDEND

CMA
SZL
lAC

DCA HIGH 12
CLL CML
TAD DIVISOR
SPA

/IS IT POSITIVE?

CMA CML lAC

/NO - NEGATE IT
/AND STORE IT BACK
/CHECK LINK FOR SIGN OF RESULT
/POSITIVE - STORE -1 IN SIGN
/NEGATIVE - STORE IN SIGN

DCA DIVISOR
SNL

CMA
CLL

DCA SIGN
TAD LOW 12
MQL
TAD HIGH 12
DVI
DIVISOR, (DIVISOR STORED HERE)
SZL
JMP EXIT

/GET LOW ORDER DIVIDEND
/STORE IT IN MQ

/LOAD AC WITH HIGH ORDER DIVIDEND
/DIVIDE

/OVERFLOW?
/YES - EXIT ON OVERFLOW

DCA REMAIN

/NO - STORE UNSIGNED REMAINDER

MQA

/LOAD AC WITH QUOTIENT
/SHOULD QUOTIENT BE NEGATIVE?
/YES - NEGATE IT

ISZ SIGN

CMA lAC
4.6

/NEGATE IT
/WAS THERE A CARRY FROM LOW ORDER?
/YES - INCREMENT HIGH ORDER
/AND STORE IT BACK
/SET LINK TO 1 FOR SIGN CHECK
/LOAD AC WITH DIVISOR

EXTENDED MEMORY

When additional 4096-word memory banks are attached to the PDP-12, the Memory Extension Control provides
access to the additional storage, both for programs and data. The registers of the Control are already built into the

PDP-12; they are described in Paragraph 3.3.15 in relation to LINC mode memory control. In the 8 mode, the
functions of these registers are the same, but only a portion of each register is used. The Instruction Field (IF),

Data Field (DF), and Instruction Field Buffer (IB) registers are each five bits long; the two low-order bits of the
5-bit total pertain only to

LINC mode programming operations. In 8 mode the Save Field register (Interrupt

Buffer) uses only six bits; the four low-order bits are unused.

4.6.1

Registers

4.6.1.1

Instruction Field Register (IF), 3 Bits - These three bits serve as an extension of the PC for determining

the 4096-word field from which executable instructions are to be taken. All direct memory references are made to
registers in the Instruction Field.

With one exception, all JMP and JMS instructions, whether direct or indirect, are

to registers within the Instruction Field. The exception is the first JMP or JMS executed after a CIF instruction is
given. This causes the field to change.

4.6.1.2 Data Field Register (DP), 3 Bits - These three bits serve as an extension of the Memory Address register
for determining which memory field contains the operands to be accessed by the memory reference instructions
AND, TAD, DCA, and ISZ when indirect addressing is used. The Data Field and Instruction Field may be set to the

same field.

4.6. 1.3

Instruction Field Buffer (IB), 3 Bits - This serves as an input buffer for the IF. Except for a direct transfer

from the console switches, all transfers into the IF must pass through the IB. When a CIF or RMF instruction is
executed, information going to the IF is first placed in the IB. At the next occurrence of a JMP or JMS, the
contents of the IB are transferred to the Instruction Field register, and programming continues in the. new field,
starting in the target register of the jump.

4-19

4.6.1.4 Save Field Register (SF), 6 Bits — Also called the Interrupt Buffer. When a program interrupt occurs, the

contents of the IF and
serviced,

DF are stored in the Save Field register, as shown in Figure 4-10. After the PI has been

an RMF instruction will cause the contents of the SF to be restored to the DF and IB. The SF can be

examined by using the RIB instruction.

4.6.1.5 Break Field Register (BF), 3 Bits — When an external device requires extended memory for the transfer of

data using the Data Break Facility, the contents of the BF specify the memory field to be accessed.

4.6,2 Instructions

All Extended Memory lOT instructions require 4.3 microseconds for execution.

IB)

Figure 4-10. Data Path to SF and AC

CDF

Change Data Field

0<N<7

Octal code:

62N1,

Operation:

The quantity N is transferred to the Data Field register. All subsequent indirect memory
references by AND, TAD, ISZ, and DCA are to the new field.

CIF

Change Instruction Field

0<N<7

Octal code:

61N2,

Operation:

The quantity N is transferred to the Instruction Field Buffer. At the occurrence of the next

IMP or JMS instruction, whether direct or indirect, the contents of the IB are transferred to
the IF. The effective address of the jump is placed in the PC, and the program continues from
that address in the new Instruction Field.
In both CIF and CDF, the number

RDF

N occupies bits 6-8 of the instruction code.

Read Data Field

Octal code:

6214

Operation:

The contents of the Data Field register are ORed into ACg-g. The other bits of the AC are
unaffected.

4-20

RIF

Read Instruction Field
6224
The contents of the Instruction Field register are ORed into ACg-g. The other bits of the AC

Octal code:

Operation:

are unaffected.

Read In terrup t B uffer

RIB

6234
The contents of the Save Field register (Interrupt Buffer) are transferred to the AC, as follows:

Octal code:

Operation:

Bits 0-2 (IF) are ORed into AC^-g

RMF

;

bits 3-5 (DF) are ORed into AC9-1 j

Restore Memory Field

6244
The contents of the Save Field register are placed in the Instruction Field Buffer and DF as

Octal code:

Operation:

follows:

Bits 0-2 (original Instruction Field) are transferred to the IB; bits 3-5 (original Data

Field) are restored to the Data Field register. This instruction is used to restore the Memory

Field registers after a program interrupt has been serviced. Normally, the next instruction after

the

RMF would be JMP I 0; the address of the interrupted program, stored in register 0000 of

field 0, is

placed in the PC, and the contents of the IB are placed in the Instruction Field

program thus returns to the main program with the Memory Fields restored to

their original values.

4.6.3

Programming

All instructions, effective addresses, and directly- addressed operands are taken

from the field specified by the

contents of the Instruction Field Register. All indirectly-addressed operands are taken from (or are stored in) the
field specified by the contents of the Data Field Register. The following chart shows the results of the four possible

addressing combinations, when the IF and DF designate different memory fields.
Instruction Bits
Indirect

Page

Fields

Effective

Address

The operand is in Page
of Field m at the address
specified by instruction bits 5-11.
The operand is in the current page of Field m.
The effective address of the operand is in Page of
Field m at the location specified by instruction bits
5-1 1
The operand is in Field n, in the location
.

specified

by the contents of the effective address.

The

effective address

page

of Field m, at the location specified by

taken from the current

instruction bits 5-11. The operand is in Field n, in

the

location

specified

by the contents of the

effective address.

4-21

Autoindexing — When any memory field is used as an Instruction Field, registers 10-17 of that field have
do. This is necessary so that a program can
autoindexing properties, just as the corresponding locations in field
4.6.3.1

operate correctly regardless of the actual memory field assigned by the IF. When an autoindex register is indirectly
addressed, the resulting effective address is used to obtain the operand from the Data Field specified by the DF.

Example:
C(IF) = 2.

C(DF) = 4.

In field 4:

C(4326)= 1107
C(0012) = 4325

In field 2;

The instruction TAD

C(AC) = 0.

2 is executed in field 2.

C(0012) + 1 -^ C(0012). Resulting effective address is 4326.
C(4326) in field 4 are added to the AC.
C(AC) = 1 1 07 when the instruction is completed.

4.6.3.2 Calling A Subroutine Across Fields — The problem is to let the subroutine know which field contains the
calling program, so that it can return to the proper point when it's finished. This is most easily done by setting the

DF to the same field as the IF, then setting the IF to the field containing the subroutine, and executing a JMS to
read the subroutine. The subroutine uses the DF to indirectly obtain data from the calling field, then transfers the
C(DF) back to the IF Buffer to return to the calling program. The following example shows a general procedure for
doing this.

/CALLING PROGRAM IN FIELD 2, SUBROUTINE IN FIELD 4
/CURRENT DATA FIELD IS 1
/CALLING SEQUENCE SAVES CURRENT DF, PUTS IF IN DF, CALLS
/SUBROUTINE. ON RETURN, ORIGINAL DF IS RESTORED

CLA
TAD KCDF
RDF
DCA RESDF
TAD KCDF

/CDF INSTRUCTION TO AC
/C(DF) TO AC 6-8 FORMS CDF 10 (621 1)
/STORE IN SEQUENCE TO RESTORE DF

/CDF TO AC
/C(IF) TO AC 6-8 FORMS CDF 20 (6221)

RIF

DCA SETDF

/STORE IN SEQUENCE TO SET DF

0000
CIF 40

RESDF,

0000

/SETS DF TO CURRENT IF
/SET IF BUFFER TO SUBROUTINE FIELD 4
/JUMP TO SUBROUTINE IN FIELD 4
/RESTORES ORIGINAL DF (FIELD 1)

SUB ADR,
KCDF,

SUBRTN
CDF

/ABSOLUTE ADDRESS OF SUBROUTINE
/CONSTANT

SETDF.

JMS

SUBADR

/IN FIELD 4, THE SUBROUTINE HAS THE FOLLOWING GENERAL FORM

/C(PC) FROM CALLING PROGRAM

SUBRTN,

RESIF,
4-22

TAD KCIF
RDF
DCA RESIF

/STORE IN SEQUENCE TO RESTORE CALLING FIELD

0000

/SETS IF BUFFER TO RESTORE CALLING FIELD

/CIF INSTRUCTION TO AC

/C(DF) TO AC 6-8 FORMS CIF 20 (6222)

JMP I SUBRTN
KCIF,

CIF

/JUMP BACK TO CALLING PROGRAM
/CONSTANT

The original contents of the IF, placed in the DF by the calling program, are used to form a CIF instruction which
is placed in the

4.6.3.3

subroutine program sequence just before the exit, to restore the original calling field.

Program Interrupt - If, when the PI facility is enabled, a PI request occurs, the contents of the IF and DF

are saved in the Interrupt Buffer.

The contents of the PC are stored in register 0000 of Field 0, and the next

instruction is taken from register 0001 of Field 0. Regardless of the states of the Memory Field register, a PI always
transfers control to Memory Field 0. When the interrupt has been serviced, the

RMF instruction is used to restore

the Memory Field registers to their original states. The last three instructions of a general interrupt service routine

should be as follows:

RMF
ION
JMP I

/RESTORES DF, PUTS ORIGINAL IF IN IF BUFFER
/ENABLE INTERRUPT
/SETS IF FROM IF BUFFER, AND RETURNS TO
/MAIN PROGRAM.

4-23/4-24

CHAPTER 5
INPUT/OUTPUT BUS DESCRIPTION

Because the processing power of a computer depends largely upon the range and number of peripheral devices that
can be connected to it, the PDP-12 has been designed to interface readily with a broad variety of external

equipment. This chapter defines the interface characteristics of the computer thus allowing the user to design and
implement any electrical interfaces required to connect I/O devices to the PDP-12.

The simple I/O technique of the PDP-12, the availability of DEC's FLIP CHIP logic circuit modules, and DEC's
oolicy of giving assistance wherever possible allow inexpensive, straightforward device interfaces to be realized,

hould questions

arise relative

to the

modules, or installation planning,

computer interface

characteristics, the design of interfaces using

DEC

customers are invited to telephone any of the sales offices or the main plant in

Maynard, Massachusetts, Digital Equipment Corporation makes no representation that the interconnection of its
circuit modules in the manner described herein will not infringe on existing or future patent rights. Nor do the
descriptions contained herein imply the granting of licenses to use, manufacture, or sell equipment constructed in

accordance herewith.

The PDP-12 contains a central processor and core memory composed of Digital's M Series TTL circuit modules.
These circuits have an operating temperature range exceeding the limits of 50° F to 1 1 0° F, so air-conditioning is
not required. Standard 115V, 50/60-Hz power operates an internal solid-state power supply that produces all
required voltages and currents. High-capacity, high-speed I/O capabilities of the PDP-12 allow it to operate a variety

of peripheral devices in addition to the standard Teletype keyboard/printer, tape reader, and tape punch. DEC
options, consisting of an interface and normal data processing equipment, are available for connecting into the

computer system. These options include a random access disk file, card equipment, line printers, magnetic tape
transports, magnetic drums, analog-to-digital converters. CRT displays, and digital plotters. The PDP-12 system can
also accept other types of instruments or hardware devices that have appropriate interfaces.

Up to 61 devices

requiring three programmed command pulses, or up to 183 devices requiring one programmed command pulse can

be connected to the computer. The interface of any device to the computer does not require any modification to
the central processor, and thus can be achieved in the field.

Control of some kind is needed to determine when an information exchange is to take place between the PDP-12

and peripheral equipment, and to indicate the location(s) in the computer memory which will accept or yield the
data. Either the

computer program or the I/O device can exercise

this

control. Transfers controlled

by the

computer, hence under control of its stored program, are called programmed data transfers.
Transfers made under control of the external I/O devices through the data break facility are called data break
ansfers.

5-1

Programmed Data Transfers
The majority of I/O transfers occur under program control. To transfer and store information under program
control takes about six times as much computer time as under the data break facility. In terms of real time, the
duration of a programmed transfer is rather small, due to the high speed of the computer, and is well beyond that

required for laboratory or process control instrumentation.

To realize full benefit of the built-in control features of the PDP-12, programmed I/O transfers should be used in
most cases. Controls for devices using programmed data transfers are usually simpler and less expensive than
controls for devices using data break transfers. Using programmed data transfer facilities, simultaneous operation of
devices is limited only by the relative speed of the computer with respect to the device speeds, and the search time

required to determine the device requiring service. Analog-to-digital converters, digital-to-analog converters, digital
plotters, line printers, message switching equipment, and relay control systems typify equipment using programmed

data transfers.

Data Break Transfers
Devices which operate at very high rates of speed or which require very rapid response from the computer use the
data break facilities. Use of these facilities permits an external I/O device to insert or extract words from the

computer core memory, almost arbitrarily bypassing all program control logic. Because the computer program has

no cognizance of such transfers, programmed checks of input data are made prior to use of information received in
this manner. The data break is particularly well suited for devices that transfer large amounts of data in block form;
e.g.,

random access disk file, high-speed magnetic tape systems, high-speed drum memories, or CRT display systems

containing memory elements.

Program Interrupt
It is

sometimes very useful for a program to be able to initiate operation of an I/O device and then continue with

execution of programming which is not immediately related to the input-output operation, rather than wait for the
device to become ready to transfer data. In this mode of operation, the device itself, through use of the PDP-12

Program Interrupt facility, initiates execution of the programming to transfer data to or from the computer. When
the device requires service (i.e., when the device is ready to transfer data), it transmits an interrupt request signal to
the computer. This signal causes the execution of the program currently underway to be interrupted, and program
control to be transferred to a specific memory location.

The contents of the program counter are stored in this

location, and subroutine for servicing the I/O device beginning in the next core memory location is executed. After

completion of the data transfer, the interrupted program is resumed by returning to the location specified by the
contents of the program counter, which were saved when the interrupt occurred. The program interrupt hardware
is designed so

that interrupt requests from devices may be ignored if the program so desires.

Logic Symbols

The PDP-12 uses TTL logic internally. In order to discuss some of the internal logic pertaining to interfacing, it is
necessary to understand the TTL symbology used in the PDP-12. The logic symbols are shown in Figure 5-1.

Signal Names

H (high)
H is high when the pulse is being generated, and at all other times is ground.

All signals not originating at a flip-flop output are true when the line is at the level indicated by the suffix

or L (low). Thus, a line labeled lOP
Similarly,

5-2

AC CLEAR L is at ground for assertion, and positive otherwise.

+ 3V INPUT

CLOCK

CLOCK PULSE WILL CAUSE
DATA INPUT TO APPEAR
AT "1" OUTPUT

DATA

3^lSEC
6)1SEC

TAPPED DELAY

+ 3V OUTPUT

ADJUSTABLE

GND OUTPUT

DELAY

SINGLE SHOT WITH

LOGICAL AND GATE
FOR POSITIVE SIGNAL
WITH POSITIVE OUTPUT

COMPLEMENTARY OUTPUTS

GENERAL
PURPOSE

LOGICAL OR GATE
FOR POSITIVE SIGNALS
WITH POSITIVE OUTPUT

FILTER

AMPLIFIER

LOGICAL NAND GATE (AND)
POSITIVE SIGNALS

(OR LEVEL CONVERTER)

Figure 5-1. Logic Symbols

Signals originating at flip-flops are defined in terms of the flip-flop state.

The following table illustrates the

convention.
Signal Name

State of

MB Flip-Flop

Signal Voltage

MB 03 (0) H
MB 03 (0) L

+3V
ov

MB03(1)L
MB03(1)H

OV
+3V

NOTE
The line MB 03(0)H is the same line as MB 03(1 )L, and MB 03(1 )H is the same line
as

MB 03(0)L.

5-3

5.1

PROGRAMMED DATA TRANSFERS AND I/O CONTROL

The majority of I/O transfers take place under control of the PDP-12 program, taking advantage of control
elements built into the computer. Although programmed transfers take more computer and actual time than data
break transfers, the timing discrepancy is insignificant, considering the high speed of the computer with respect
to
most peripheral devices. The maximum data transfer rate for programmed operations of 12-bit words is 148 kHz

when status checking (end, transfer check, etc.) is not done. This speed is well beyond the normal rate required for
typical laboratory or process control instrumentation.

The PDP-12 is a parallel-transfer machine that distributes and collects data in bytes of up to twelve bits. All
programmed data transfers take place through the accumulator, the 12-bit arithmetic register of the computer. The
computer program controls the loading of information into the accumulator (AC) for an output transfer, and for
storing information in core memory from the AC for an input transfer. Output information in the AC is power
amplified, and supplied to the interface connectors for bussed connection to many peripheral devices. Then the

program-selected device can sample these signal lines to strobe AC information into a control or information
Input data arrives at the AC as pulses received at the interface connectors from bussed outputs of many

devices. Gating circuits of the program-selected device produce these pulses. Command pulses generated by the
device are connected to the input/output skip facility (lOS) to sample the condition of I/O device flags.

The lOS allows branching of the program based upon the condition or availability of peripheral equipment,
effectively making programmed decisions to continue the current program or jump to another part of the program,
such as a subroutine to service an I/O device.

The bussed system of input/output data transfers imposes the following requirements on peripheral equipment:
a.

Each device must be able to sample the select code, generated by the computer during an lOT instruction*,

when selected, must be able to produce sequential lOT command pulses in accordance with the
computer-generated lOP pulses. Circuits which perform these functions in the peripheral device are called

and,

Device Selectors (DS). Figure 5-2 shows the decoding of the lOT instruction.

lOP GENERATOR

CONTROL

DEVICE
SELECTION
CODE

Figure 5-2.

lOT Instruction Decoding

Each device receiving output data from the computer must contain gating circuits at the input of a
receiving register capable of strobing the

AC signal information into the register when triggered by a

command pulse from the DS. Gating is also recommended at the input to the peripheral device in order to
minimize loading on the BAC signal lines.

*Appendix C provides a listing of lOT instructions.

5-4

Each device sending input data to the computer must contain gating circuits at the output of the
transmitting register capable of sampling the information in the computer output register and supplying a
pulse to the computer input bus when triggered by a command pulse from the DS.

Each device should contain a Busy/Done flag (flip-flop) and gating circuits that can pulse the computer I/O
skip bus (lOS) upon command from the DS when the flag is set in the binary

state, to indicate that the

device is ready to transfer another byte of information.

Figure 5-3 shows the information flow within the computer which effects a programmed data transfer with I/O
equipment. All instructions stored in core memory as a program sequence are read into the memory buffer register

(MB) and the instruction register (IR)
significant bits (bits 0,

for execution. The transfer of the operation code in the three most
and 2) of the instruction into the instruction register (IR) takes place and is decoded to

produce appropriate control signals. The computer, upon recognition of the operation code as an lOT instruction,
enters a 4.25-microsecond expanded computer cycle and enables the lOP generator to produce time-sequenced lOP

pulses as determined by the three least significant bits of the instruction (bits 9, 10, and 11 in the MB). These lOP
pulses and the buffered output of the select code from bits 3-8 of the instruction word in the

MB are bussed to

device selectors in all peripheral equipment.

BITS

0-2

INSTRUCTION
REGISTER
(IR)

12-BIT

NflEMORY

WORD

INSTRUCTION

^
lOP

INSTRUCTION

CORE

lOT
IR

DECODER

BITS 9-11

lOP

PULSES

GENERATOR

—w

MEMORY
BUFFER
REGISTER
(MB)

BITS

3-8

BITS 3-8
Ol ITPIIT

DATA

ACCUMULATOR
REGISTER
(AC)

INPUT OUTPUT
SKIP
FACILITY

INPUT DATA

—w
^
CONNECTIONS

y TO INPUT/ OUTPUT

SKIP

(lOS)

PROGRAM

PROGRAM
INTERRUPT
FACILITY

INTERRUPT

^ REQUEST
^

(PI)

SI-0II9

Figure 5-3. Programmed Data Transfer Interface Block Diagram

5-5

MEMORY UFFCK

ni HMMLILC
TOKVICE)

T* • (AMULAH.E
TO OCMCE)

MOT

(TOOCVKO

•lOPt
(TO OCVKE)

OP 4
(TOOEVKEt

Figure 5-4. Programmed Data Transfer Timing

Figure 5-4 indicates the timing of programmed data transfers.

Devices which require immediate service from the computer program, or v^'hich require too much computer time to
mode
discontinue the main program until transfer needs are met, can use the program interrupt (PI) facility. In this
device
of operation, the computer can initiate operation of I/O equipment and continue the main program until the
of the
conditions
the
of
storing
causes
interrupt
program
a
requesting
the
PI
input
to
signal
requests servicing. A

main program and initiates a subroutine to service the device. At the conclusion of this subroutine, the main
program is reinstated until another interrupt request occurs.

5.1.1

Timing and

OP Generator

When the IR decoder detects an operation code of eOOOg, it identifies an lOT instruction and the computer
generates a slow cycle. The Slow Cycle signal is ANDed with TP4 to generate I/O Start and sets the I/O PAUSE
flip-flop.

The logic of the lOP generator consists of a re-entrant delay chain which generates three time states.
lOP 4, respectively. Note that
states are gated with MB bits 1 1, 10, and 9 to generate lOP 1, lOP 2, and

These time

an lOP is generated only if the corresponding MB bit is set although the I/O timing
each lOP, the state of the I/O interface is sampled by an I/O strobe pulse.

remains constant. At the end of

Following the end of lOP 4 time, the PAUSE flip-flop is reset and the normal timing chain is restarted.

5-6

Unlike PDP-8/I, the PDP-12 does not make a timing distinction between internal I/O functions and normal I/O,
thus all I/O instructions cause the slow cycle.

Instruction

lOP

lOT

Event

Used Primarily For,

Bit

Pulse

Time

But Not Restricted To

lOP 1

lOT 1

I0P2
rOP4

I0T2
I0T4

10
9

Sampling Flags, Skipping.

Clearing Flags, Clearing AC.

Reading Buffers,

Loading Buffers and Clearing

Buffers.

5.1.2 Device Selector (DS)

Bits 3 through 8 of an lOT instruction serve as a device or subdevice select code. Bus drivers in the processor buffer

the

and

output signals of MB3.8 and distribute them to the interface connectors for bussed connection to all

device selectors. Each DS is assigned a select code and is enabled only when the assigned code is present in the MB.

When enabled, a DS regenerates lOP pulses as lOT command pulses and transmits these pulses to skip, input, or
output gates within the device and/or to the processor to clear the AC.

Each group of three command pulses requires a separate DS channel, and each DS channel requires a different
select code (or 1/0 device address). Therefore, one I/O device can use several DS channels. Note that the processor

produces the pulses identified as lOP
selector produces pulses lOT

1 ,

1, lOP 2, and lOP 4 and supplies them to all device selectors. The device
lOT 2, and lOT 4, which initiate a transfer or effect some control. Figure 5-5 shows

generation of command pulses by several DS channels.

DEVICE

SELECTOR

lOT 6341

lOT 6S41

lOT 6S42 H

lOT 6342 L
lOT 6344 H
lOT 6344 L

DEVICE 34 SELECTED

lOP LINES

(BUSSED TO ALL
DEVICE SELECTORS)

Figure 5-5. Generation of lOT Command Pulses by Device Selectors

5-7

The logical representation for a typical channel of the DS, using channel 34, is shown in Figure 5-6. An 8-input
AND gate is wired to receive the appropriate signal outputs from the MBg.g for select code 34, which activates the
channel. In the DS module, 6 input pins are connected to the complementary outputs of MBg.g and 2 are open to
,

receive subdevice or control condition signals as needed. Either the 1 or the

to the

signal from each

MB bit is connected

AND gate when establishing the select code. The positive output of the AND gate indicates when the lOT

instruction selection selects the device, and can, therefore, enable circuit operations with the device. This output
also enables three' power

NAND gates, each of which produces a ground output pulse if the corresponding lOT

The ground output from each gate is an lOT command pulse identified by the select code and the
number of the initiating lOP pulse. Three inverters receive the negative lOT pulses to produce complementary lOT

pulse occurs.

output pulses.

lOT 6344 H
B lOP 4 H

B lOP 2 H

=3
:r>

lOT 6344 L

lOT 6342 H

lOT 6342 L

I0T6341 H
B lOP

HlOT 6341

AVAILABLE FOR
SUB- DEVICE
ENCODING

634XH
(DEVICE SELECT LINE

USED FOR BAC
INPUT GATING)
SI-OIII

Figure 5-6. Typical Device Selector (Device 34)

An amplifier module can be connected in each channel of the DS to provide greater output drive.

5.1.3

Input/Output Skip (lOS)

Generation of an lOS pulse can be used to test the condition or status of a device flag, and to continue to or skip
the next sequential instruction based upon the results of this test. This operation is performed by a 2-input AND
gate in the device connected as shown in Figure 5-7. One input of the skip gate receives the status level (flag output
signal), the second input receives an lOT pulse,

and the output drives the computer skip (designated SKIP BUS L)

to ground when the skip conditions are fulfilled. The state of the skip bus is sampled at the end of each lOT. If the

bus has been driven to ground, the contents of the program counter are incremented by 1 to advance the program
count without executing the instruction at the current program count. In this manner, an lOT instruction can

check the status of an I/O device flag and skip the next instruction if the device requires servicing. Programmed
testing in this manner allows the routine to jump out of sequence to a subroutine that services the device tested.

5-8

PDP-12

A
BUILT-IN LOAD 8 RECEIVER

SKIP BUS L

lOT 6342

(FROM DEVICE
SELECTOR)

r>
M623 SECTION
STATUS
FLIP-FLOP

(PWR "AND" GATE
WITH OPEN COLLECTOR)

81 -0107

Figure 5-7. Use of lOS to Test the Status of an External Device

Assuming that a device is already operating, a possible program sequence to test its availability is:
/SKIP IF DEVICE 34 IS READY

100,

6342

101,

5100

/JUMP.-l

102,

5XXX

/ENTER SERVICE ROUTINE FOR DEVICE 34.

When the program reaches address 100, it executes an instruction skip with 6342. The skip occurs only if device 34
is ready when the lOT 6342 command is given. If device 34 is not ready, the flag signal disqualifies the skip gate,
and the skip pulse does not occur. Therefore, the program continues to the next instruction, which is a jump back
to the skip instruction. In this example, the program stays in this waiting loop until the device is ready to transfer
data, at which time the skip gate in the device is enabled and the skip pulse is sent to the computer lOS facility.

When the skip occurs, the instruction in location 102 transfers program control to a subroutine to service device
34. This subroutine can load the

AC with data and transfer it to device 34, or can load the AC from a register in

device 34 and store it in some known core memory location.

5.1.4 Accumulator

The binary

output signal of each flip-flop of the AC, buffered by a bus driver, is available

at the interface

connectors. These computer data output lines are bus-connected to all peripheral equipment receiving programmed
data output information from the PDP-12.

The I/O bus input on each flip-flop of the AC is connected to the

interface connectors for bussing to all peripheral equipment supplying programmed data input to the PDP- 1 2. An

lOP that drives the input bus terminal to ground sets the corresponding AC flip-flop. Output and input connections
to the accumulator appear in Figure 5-8.

The status of the hnk bit is not available to enter into transfers with peripheral equipment (unless it is rotated into
the AC). A bus driver continuously buffers the output signal from each AC flip-flop. These buffered accumulator
(BAC) signals are available at the interface connectors.

5-9

BACOKOL

I/O STROBE

(OCCURS AT END

OF EACH lOP)

1/0 ENABLE (ASSERTED BY ALL lOP's)

AC CLEAR BUS
(FROM I/O INTERFACE)

AC 01 BUS L
(FROM I/O INTERFACE)

Figure 5-8. Accumulator Input or Output

5.1.5

Input Data Transfers

When a device is ready to transfer data into the PDP-12 accumulator, it sets a flag. The program senses the ready
status of the flag and issues an lOT instruction to read the contents of the external device buffer register into the

AC. If the AC CLEAR BUS L is not asserted, the resultant word in the AC is the inclusive OR of the previous word
in the AC and the word transferred from the device buffer register. The AC CLEAR BUS L may also be used as an
I/O AC clear by activating only this line from a separate lOT.

The illustration in Figure 5-9 shows that the accumulator has an input bus for each bit flip-flop. Setting a 1 into a
particular bit of the accumulator necessitates grounding of the interface input bus by the standard interface gate. In
the illustration, the 2-input

AND gates set various bits of the accumulator. In this case an lOT pulse is AND

combined with the flip-flop state of the external device to transfer into the accumulator. (The program need not
include a clear AC command prior to loading in this manner.)

5-10

Following the transfer (possibly in the same instruction) the program can issue a command pulse to initiate further
operation of the device and/or clear the device flag.

AC CLEAR BUS L

TRANSFER lOT

(

)

r^
ir<

PWR "AND GATES
WITH OPEN COLLECTORS
M623 OR EQUIVALENT

f
IF

OMIT THIS GATE
"ONES TRANSFER"
DESIRED

DATA REGISTER
OF I/O DEVICE

Figure 5-9. Loading Data into the Accumulator from an External Device

5.1.6

Output Data Transfers

The AC is loaded with a word (e.g., by a CLA TAD instruction sequence); then the lOT instruction is issued to
transfer the word into the control or data register of the device by an lOT pulse (e.g., lOP 2), and operation of the
device is initiated by another lOT pulse (e.g., lOP 4). The data word transferred in this manner can be a character
to be operated upon, or can be a control word sampled by a status register to establish a control mode. The BAC
lines should be gated by the select code at each device to prevent excessive loading. A special module, the Ml 01, is
provided for this purpose.
Since the BAC interface bus lines continually present the status of the AC flip-flops, the receiving device can strobe

them to sense the value in the accumulator. In Figure 5-10, a strobe pulse samples six bits of the accumulator to
transfer to an external 6-bit data register. Since this is a jam transfer, it is not necessary to clear the external data
register. The gates driving the external data register are part of the external device and are not supplied by the
computer. The data register can contain any number of flip-flops up to a maximum of twelve. If more than twelve
flip-flops are involved, two or more transfers must take place. Obviously the strobe pulse shown in Figure 5-10
must occur when the data to be placed in the external data register is held in the accumulator. This pulse,
therefore, must be under computer control to effect synchronization with the operation or program of the
computer.

5.1.7.

Program Interrupt (PI)

When a large amount of computing is required, the program should initiate operation of an I/O device, then
continue the main program, rather than wait for the device to become ready to transfer data. The program
interrupt facility, when enabled by the program, relieves the main program of the need for repeated flag checks by

allowing the ready status of I/O device flags to automatically cause a program interrupt. When a program interrupt
occurs, program control transfers to a subroutine that determines

which device requested the interrupt, and

initiates an appropriate service routine.

5-11

DATA REGISTER OF
EXTERNAL DEVICE
lOT (F ROM MI03 )

(STROBE PULSE

MlOl INPUT GATES

DEVICE SELECT LINE
(FROM 103)

BAC INPUTS

FROM COMPUTER
Figure 5-10. Loading a Six-Bit Word into an External Device from the Accumulator

In the example shown in Figure 5-11, a flag signal from a device status flip-flop operates a standard gate with no
internal load. When the status flip-flop indicates the need for device service, the Program Interrupt Request bus is

driven to ground and requests a program interrupt.

INTERRUPT
BUS

M623 OR EQUIVALENT GATE
GATE IS ACTIVATED WHEN
FLIP-FLOP IS SET
X~^

DEVICE FLAG
OR STATUS
FLIP-FLOP

FLIP-FLOP

lOT TO

CLEAR FLAG

Figure 5-11. Program Interrupt Request Signal Origin

only one device is connected to the PI facility, program control can be transferred directly to a routine that

services the device when an interrupt occurs. This operation occurs as follows (example in 8 mode):

Tag

Address

Instruction

/MAIN PROGRAM
/MAIN PROGRAM CONTINUES
/INTERRUPT REQUEST OCCURS
/INTERRUPT OCCURS

1000
1001

1002

/PROGRAM COUNT (PC = 1003) IS

0000
0001

5-12

Remarks

JMPSR

/STORED IN 0000
/ENTER SERVICE ROUTINE

SR,

2000

/SERVICE SUBROUTINE FOR

3001

/INTERRUPTING DEVICE AND
/SEQUENCE TO RESTORE AC, AND
/RESTORE LINK IF REQUIRED
/RESTORE MEMORY FIELDS
/TURN ON INTERRUPT

RMF

3002
3003

ION
JMP I 0000

3004

/RETURN TO MAIN PROGRAM
/MAIN PROGRAM CONTINUES

1003

1004

most PDP-12 systems, numerous devices are connected to the PI facility, so the routine beginning in core

memory address 0001 must determine which device requested an interrupt. The interrupt routine determines the
device requiring service by checking the flags of all equipment connected to the PI and transfers program control to

device encountered that has its flag in the state required to request a program

a service routine for the

first

interrupt. In other words,

when program interrupt requests can originate in numerous devices, each device flag

connected to the PI must also be connected to the lOS.

_r<

DEVICE 1
SKIP lOT

::r>
DEVICE

FLAG

^r>'
DEVICE 2
SKIP lOT

f—

DEVICE 2

FLAG

INTERRUPT
BUS

SKIP

BUS

Figure 5-12. Multiple Inputs to lOS and PI Facilities

5-1

5.1.7.1

Multiple Use of lOS and PI - In common practice, more than one device is connected to the PI facility. In

the basic PDP-12, the teletype flags are already connected. Therefore, since the computer receives a request that is
of requests from all devices connected to the PI, the lOS must identify the device making the
the inclusive

request. When a program interrupt occurs, a routine is entered from address 0001 in 8 mode (0041 in Line mode)

to sequentially check the status of each flag connected to the PI and to transfer program control to an appropriate
service

routine for the device whose flag

requesting a program interrupt. Figure 5-12 shows

lOS and PI

connections for two typical devices.

The following program example illustrates how the program interrupt routine determines the device requesting
service (example in 8 mode):

Tag

Address

Remarks

Instruction

/MAIN PROGRAM
/MAIN PROGRAM CONTINUES
/INTERRUPT REQUEST OCCURS

1000
1001

1002

INTERRUPT OCCURS
0000

JMP FLG CK

0001

FLG CK,

10T6341
SKP
JMP SR34
lOT 6441
SKP
JMP SR44
lOT 6541
SKP
JMP SR54

/STORE PC (PC = 1003)
/ENTER ROUTINE TO DETERMINE
/WHICH DEVICE CAUSED INTERRUPT
/SKIP IF DEVICE 34 IS REQUESTING
/NO - TEST NEXT DEVICE
/ENTER SERVICE ROUTINE 34
/SKIP IF DEVICE 44 IS REQUESTING
/NO - TEST NEXT DEVICE
/ENTER SERVICE ROUTINE 44
/SKIP IF DEVICE 54 IS REQUESTING
/NO - TEST NEXT DEVICE
/ENTER SERVICE ROUTINE 54

Assume that the device that caused the interrupt is an input device (e.g., tape reader). The following example of a
device service routine might apply:

Tag

Instruction

SR,

DCA TEMP
lOTXX
DCA I 10
ISZ COUNT
SKP
JMP END

TAD TEMP
RMF
ION
JMP 10

5-14

Remarks

/SAVE AC

/TRANSFER DATA FROM DEVICE BUFFER TO AC
/STORE IN MEMORY LIST
/CHECK FOR END
/NOT END
/END. JUMP TO ROUTINE TO HANDLE
/END OF LIST CONDITION

/RESTORE LINK AND OTHER STATUS IF REQUIRED
/RELOAD AC
/RESTORE MEMORY FIELDS
/TURN ON INTERRUPT
/RETURN TO PROGRAM

caused the interrupt was essentially an output device (receiving data from computer), the lOT
then - DCA I 10 sequence might be replaced by a TAD I 10 - then - lOT sequence.
If the device that

5 2
.

MULTI-LEVEL AUTOMATIC PRIORITY INTERRUPT

The KF12B Multi-Level Automatic Priority Interrupt is designed to reduce the central processor overhead during
the servicing of program interrupts. It is prewired in the EP section of the PDP-12 in racks P and R and utilizes approximately 55 M series modules. There are three major services provided automatically by the KF12B.
a.

Automatic determination of device priority and vectoring of interrupt service routines.

Automatic saving and restoring of all major registers and machine status which include the following:
PC, AC, IF, DF, MQ, LINK, FLOW, UF, MODE and the current processor level.

Automatic stacking of the saved parameters permitting multiple levels of interrupts.

Storing, or stacking, of parameters is called Pushing and restoring the CP to its original status prior to an interrupt
is called Popping.

The CP is in the break state for the duration of each operation. It takes five break cycles for each

Push and five break cycles for a Pop. This does not affect the normal operation of the data break facility in the
PDP-12. One data break device can be handled without the addition of a multiplexer. The KF12B has the lowest
priority on the bus and break requests from another device are acknowledged during push and restore operations.

The KF 1 2B control has its own timing generator and is asynchronous with computer timing.
oscillator provides the various clocking pulses.

A free running 5 mHz

An Ml 55 decoder provides the enable levels to enable data on the

bus.

5.2.1

Interrupts

Up to 15 levels of interrupts can be accommodated with each level having a two-word vector address. The interrupts can be accepted from a prewired option or from up to six external devices.
terrupt by a jumper module, M905 at location Rl 6. Level

A priority is assigned to each in-

has the highest priority. Interrupts of a higher priority

can occur after executing the first instruction in the interrupt service routine. When the KFl 2B is not enabled (API

ON (0)), interrupts are processed through the interrupt cycle in the normal manner. The "TRAP" feature has not
been modified by the KFl 23, but caution should be exercised when using this feature.

5.2.2

Push

When the level of the device requesting an interrupt is greater than the current machine level a Push operation is
performed. The Push and Break Req flip-flops are set and the processor enters the Break cycle. The active registers
and status levels are stored (pushed) in five consecutive memory locations specified by the contents of the STACK
The starting location of the stack is specified by the program (lOT 6776) and is automatically incremented during the push operation. The stack increments and decrements across field boundaries.
The CP is always in 8 MODE at the completion of an interrupt-push operafion. If the CP is in LINC mode when a
Push occurs it is returned to LINC mode at the completion of a Restore command.
register.

(Refer to Table 5-1 .)

5-15

Table 5-1.

STACK Register

location

Data Stored

AC 0-11

P+1

PC 0-11

P+2

MODE o; FLOW

P+3

MQo-11

P+4

UFi;IF2_6;DF7_n

LINK 2; MACHINE LEVEL g--11

;

P = Initial STACK address.

NOTE:

5.2.3

the subscript indicates the corresponding memory bits.

Restore-"POP" (REST-IOT 6771)

Every interrupt subroutine should be terminated with a Restore command.

This restores the major registers and
machine status from the stack and resumes programming at the memory location specified by the program counter.

For every Push operation performed a Pop (restore) must be performed; however, the two operations do not have

The Restore command should not be issued when the CP is

to occur in any particular sequence (see Figure 5-13).

in a non-interruptable state because an Interrupt Inhibit is set due to the LIF or CIF instruction, or
set due to a

/
CORE

AN EhflPTY STACK

2. PIJSHING

A DATUM

ONTO

PU,5HINe

ANOTHER D ATUM

ON rO THE STACK

T HE STACK

/
4.

SAVE PC is not

DJR instruction.

ANOTHER PUSH

POP

PUSH

POP
12-0297

Figure 5-13. Illustration of Push and Pop Operations

5.2.4

Vectoring

Each of the 15 interrupt levels has an associated vector address to specify the appropriate interrupt service routine.
The vector address is transferred to the PC during the Push operation, as shown in Figure 5-14. Vector bits 0, 1,
and 2 specify the memory field and are set with AC bits 3, 4, and 5 by an lOT. Vector bits 3 through 9 specify the

MA (0-6) and are set with AC bits 0-6 by an lOT. The interrupt level specifies
memory address bits 7 through 10 with level "0" setting these bits to zero. A vector address is always an even number address; therefore, each interrupt level is allotted two memory locations.
seven most significant bits of the

5-16

The following are the vector address assignments, which can reside in any memory field. Vector bits 3 through 9
(MAO-6) are set to Is by the SVEC instruction:
Address

Level

Address

Level

7760

7740

7761

7741

7742
7743
7744
7745
7746
7747
7750
7751
7752
7753
7754
7755
7756
7757

1
1

2
2
3
3

4
4
5
5

6
6
7
7

7771

7772
7773
7774
7775

9
10
10
11
11

14
14

MEMORY
FIELD

MEMORY ADDRESS BITS

TRIAL
LEVEL

VECTOR REGISTER

7762
7763
7764
7765
7766
7767
7770

3-5

INTERRUPT
LEVEL

AC BITS
t

Figure 5-14. Vector Flow Diagram

5.2.5

Maintenance Logic

The maintenance logic included in the KF12B provides the capability of checking the major portion of the option
for proper operation. Two JOT instructions simulate the 15 interrupt level inputs to check the priority lo^c and
initiate the Push operation.

5-17

Function

Instruction

lOT 605

ACO-

1 1

to LEVELS 0- 1

( 1 s transfer)

lOT 6052

AC 9, 10, 11 to LEVELS 12, 13, 14
( 1 s transfer)

The levels remain set for only one computer cycle. This feature allows enough time to initiate a Push function
when the selected level has priority and API is enabled.
The KF12B features a new two-word instruction called push jump (PUSHJ, lOT 676X), This instruction permits
jumping to subroutines across field boundaries in both Line and PDP-8 Modes. The instruction causes the stacking
of the active registers and machine status and automatically jumps to the memory location specified by the 1 5-bit
address associated with the PUSHJ.

The instruction code is (lOT) 616X and is similar to an lOT except that X de-

fines the new memory field and the following location (P+1) specifies the 12-bit memory address of the subroutine.

The PC, which is saved on the stack during the execution of the PUSHJ, points to the location following the twoword instruction as shown in the following example

Address

Instruction

Octal Code

15432

PUSHJ

15433
15434*

1000

6760
1000
7200

CLA

01000 — Programming is transferred to this memory location.
* Field and PC saved on stack.

The program is resumed at this

location following a Restore.

5.2.6

Programming

The following is a typical example of a program to service a Teletype interrupt, which is level 5.

START/CLA

TAD FLDLEV
SMLV
CLA
TAD STACK

5-18

/set stack and vector fields

and machine level

SSTK

/set stack

CLA
TAD VEC
SVEC

/set vector

APION
NOP

/enable KF 12

JMP. -1

/wait for interrupt

*6412/JMSTTYR

/go to teletype reader subn

* 6413/REST

/restore to status prior to p

VECTOR ADDRESSES
TTYR/XXXX
CLA
KRS
DCA I SAVE
KCC
JMP I TTYR

/return address saved here

/read keyboard buffer
/save word
/clear reader flag

/return to restore

FLDLEV/0017
STACK/7000
VEC/6400

Programming Restrictions

5.2.7

The REST and PUSHJ commands should not be issued when the processor is in a non-interruptable state due to the
following conditions:

"Interrupt Inhibit" being set due to the execution of a CIF or LIF instruction;

The DJR instruction is being executed or Save PC is not set due to the previous execution of a DJR
instruction.

If the

REST command is issued and the CP is not in an interruptable condition, the Restore operation will not be

performed until the condition becomes satisfactory.

If the

PUSHJ command is issued and the CP is not in an inter-

ruptable condition, the second word of the instruction is treated as a new instruction, and when the condition be-

comes satisfactory, the PUSHJ operation will not be properly executed. The ESF Disable Teletype instruction is not
effective when the KF12B is enabled (API ON (1)); the TTY and DP 12 interrupts will always be acknowledged.
When the KF12B is not enabled (API ON (0)), the ESF instruction functions in the normal manner. Location zero
is not saved

on the stack; therefore, caution should be exercised when using this location in conjunction with a LINC

JMP instruction.

5.2.8

Instruction List

Function

Octal

ION

Enable software interrupt system

6001

lOF

Disable all interrupts

6002

APION

Enable API (KF12B) system

6006

Instruction

Disable software interrupt

The next instruction will be executed before an interrupt
is processed.

PUSH-J

676X

PUSH JUMP to 15 bit address
(XXXXX)

REST

Restore machine to previous level

SMLV'

Set current machine level to AC 8-1 1

(P+1)

xxxx
6771

AC7= 1

set

6772

stack field to ACO-2 and vector field to ACS -5.

*The KF12B must be deselected to execute these instructions (i.e., API ON (0)).

5-19

Instruction

Function

Octal

RFLD

Read stack field into ACO-2, vector field into AC3-5,

6773

current level into AC8-1 1 (Read in complement form)

RSTK

Read least significant 1 2 bits of current stack pointer ad-

6774

dress (Read in complement form)

RVEC

Read vector bits 3-9 into AC bits 0-6, Trial levels into
AC bits 7—10 (Read in complement form)

6775

SSTK*

Set the least significant 12 stack bits to ACO-1

6776

SVEC*

Set bits 309 of the vector address (MAO-6) to AC 0-6

6777

When the above instructions are given in LINC mode they should be preceded by an lOB in-

Note:

struction.

*The KF12B must be deselected to execute these instructions (i.e., API ON (0)).
5.2.9

DM12

The DM12, which is prewired in the PDP-12, provides the capability of operating up to three data break devices in
Both three-cycle and single-cycle devices can be simultaneously con-

either three-cycle or single-cycle data break.

DM 2. The KF 2B

for the DM 1 2 because the KF 1 2B and DM 1 2 use the same timing
and control signals, which originate in the KF12B. The DM12 uses M series positive logic; all signals are clamped at
trolled by the

is a prerequisite

OV and +3V.
Because both options use the control and timing of the KF12B, the theory of operation is similar.
device issues a break request, the corresponding Level flip-flop is set.

When an external

The three level flip-flops and the API flip-flop

are decoded to determine priority. Either PRO, PRl, or PR2 is generated and the appropriate Data Address and con-

The EN BRK flip-flop corresponding to the device that has been decoded is set at
TPl, allowing the B BREAK signal to go to the device that has control of the bus. The B BREAK signal is used to
trol signals are enabled on the bus.

control the data on the bus for transfer between memory and the external devices.

Both options use the same lOTs; thus, when testing the DM12 the KF12B must be disabled using jumpers that allow
only the DM12 priorities to be enabled.

The DM12 priorities are determined by cable location. Two cables from each device are used for the data address,
data bits, and status signals. The cables from the device having the highest priority are inserted in locations P20 and
P21 as illustrated in Figure 5-15.

COAXIAL CABLES TOTAL LENGTH ON BUS 45ft. MAX.

EM12

EP12

BMB

DEVICE

I/O BUS *
HIGHEST
PRIORITY

KF 12

DM12

LOWEST
PRIORITY

DATA ADDRESS

P20

DATA BITS
P21

DATA ADDRESS
P22

DATA BITS
P23

DATA ADDRESS
P.24

DATA BITS
P25

COAXIAL CABLES-MAX, LENGTH 25ft.
If

the priority Interrupt system Is used

(ref.

the

KF12B this cable is connected separately from each devic

BS-KFt2-CAB).

Figure 5-15.

5-20

DM 2 Cable Diagram
1

5.3

DATA BREAK TRANSFERS

The Data Break facility allows an I/O device to transfer information directly with the PDP-12 core memory on a
cycle-stealing basis. The Data Break is particularly well suited for devices which transfer large amounts of
information in block form, and can be expanded to accommodate more than one device by using the DM01 or

DM04 multiplexers. The DM01 will multiplex up to seven devices and is a negative bus option. The DM04 (positive
bus) will multiplex three devices and up to three DM04s may be added for a total of nine devices.

Peripheral I/O equipment operating at high speeds can transfer information with the computer through
the data
break facility more efficiently than through programmed means. The combined maximum transfer rate of the
data
break facility is 6.5 million bits per second. Information flow to effect a Data Break transfer with an I/O device
appears in Figure 5-16.

MEMORY
EXTENSION

CONTROL
TYPE

ADDRESS

EXTENDED DATA

^ ADDRESS

(

BIT)

MCI2

MEMORY
ADDRESS

DATA ADDRESS
^(12 BITS)

CORE

MEMORY

DATA INFORMATION
DATA

MEMORY
BUFFER
REGISTER
(MB)

1^(12 BITS IN)

DATA INFORMATION
(12 BITS OUT)

ADDRESS
ACCEPTED

WORD COUNT

CONNECTIONS TO
DEVICE

OVERFLOW
BREAK STATE
DATA

BREAK
FACILITY

^ BREAK REQUEST
TRANSFER
DIRECTION (IN)

CYCLE SELECT

^ + -» CA INHIBIT
1

INCREMENT MB

Figure 5-16. Data Break Transfer Interface Block Diagram
In contrast to programmed operations, the Data Break facihties permit an external device
transfers. Therefore,

to control information

Data Break device interfaces require more control logic circuits, causmg a higher cost than

programmed-transfer interfaces.

Data Breaks are of two basic types: single-cycle and three-cycle. In a single-cycle Data Break, registers

in the device

memory address of each transfer and count the number of transfers to
determine the end of data blocks. In the three-cycle Data Break, two computer core memory locations
perform
(or device interface) specify the core

these functions, simplifying the device interface by omitting two hardware registers.

5-21

In general terms, to initiate a Data Break transfer of information, the interface control must do the following:

Specify the affected address in core memory.

Provide the data word by establishing the proper logic levels at the computer interface (assuming an input
data transfer), or provide input gates and storage for the word (assuming an output data transfer).

Provide a logical signal to indicate direction of data word transfer.

Provide a logical signal to indicate single-cycle or three-cycle break operation.

Request a Data Break by supplying a proper signal to the computer data break facility.

5.3.1

Single-Cycle Data Breaks

Single-cycle Data Breaks are used for input data transfers to the computer, output data transfers

from the

computer, and memory increment data breaks. Memory increment is a special Data Break in which the content of a
memory address is read, incremented by 1, and rewritten at the same address. It is useful for counting iterations or
external events without disturbing the computer program counter (PC) or accumulator (AC) registers.

5.3.2

Input Data Transfers

Figure 5-17 illustrates

timing of an input transfer data break. The address to be affected in core is normally

provided in the device interface in the form of a 12-bit flip-flop register (data break address register) which has

been preset by the interface control by programmed transfer from the computer.
External registers and control flip-flops supplying information and control signals to the Data Break facility and
other PDP-12 interface elements are shown in Figure 5-18. The data register (DR in Figure 5-18) holds the 12-bit
data word to be written into the computer core memory location specified by the address contained in the address
register (AR in Figure 5-17).

Appropriate output terminals of these registers are connected to the computer to supply ground potential to
designate binary Is. Since most devices that transfer data through the Data Break facility are designed to use either
single-cycle or three-cycle breaks, but not both, the Cycle Select signal can usually be supplied from a stable source

(such as a ground connection or a +3v clamped load resistor), rather than from a bistable device as shown in Figure
5-18.

establish the data

word in the input buffer

an input data transfer, and

Other portions of the device interface, not shown in Figure 5-18,

control the break request flip-flop. These operations can be performed simultaneously or sequentially, but
transients should occur before the data break request is

all

made.

When the Break Request is recognized, the computer completes the current instruction, generates an Address
Accepted pulse (at TPl, the beginning of the break cycle) to acknowledge receipt of the request, then enters the
Break state to effect the transfer. The Address Accepted pulse can be used on the device interface to clear the
BREAK REQUEST flip-flop, increment the content of the address register, etc. If the Break Request signal is

removed before TP2 time of the data break cycle, the computer performs the transfer and returns to programmed
operation.

5-22

TP2

TP4

TPJ

COMPUTER TIME
I

cYac

mjm-

- Bt»E*K

CYCLE

-NEXT CYCLE

-SIGNAL MUSTGO T0+3V *T STMT Of AOOncSS ACCEPT PULSE IF NEXT CYCLE

BREAK SYNC FLIP FLOP

SET AT SAMPLE TIME

IINTERNALI

•

USED TO SELECT BREAK CYCLE AT TP

TO BE A BREAK

3 CYCLE

CYCLE SELECT
(SAMPLE TO PROCESSOR

CYCLE

+ 3V
B- BREAK SIGNAL
lOUTPUT TO I/O DEVICE)

DATA ADDRESS
INPUT LEVELS
(INPUT TO PROCESSOR)

START OF BREAK CYCLE

END OF BftCAK CYCLE -

GNO
+ 3V

ADDRESS
/•EXT.MEM.
READ —

GND

T READ

—

PROCESSOR

EARLIEST TIME POSSIBLE TO REMOVE ADDRESS IS AT START Of BREAK CYCLE

+ 3V
ADDRESS ACCEPT PULSE
lOUTPUT TO I/O DEVICE)

GNO
IN (+3V)

TRANSFER DIRECTION

KWST BE SET UP AT TP2

(INPUT TO PROCESSOR)

-CAN CHANCE ANYTIME AFTER TP3

OUT (GNO)
DATA SIGNAL INPUT TO MB
(INPUT TO PROCESSOR)

AVAIL (+3V)

LATEST POSSIBLE TIME TO SPECIFY
INPUT DATA IS TP2

SAMPLED AT TP3 BY PROCESSOR

NOT AVAIL (GNO)
OUTPUT DATA AVAILABLE IN MB

AVAIL 03V)

AVAILABLE ATTP3

(OUTPUT TO I/O DEVICE)

-TIME DURING WHKH DATA MUST BC STROBED BY I/O DEVICE

NOT AVAIL (+3V)

^L.

BTS5
lOUTPUT TO I/O DEVICE)

GNO
BTS2

+3V

lOUTPUT TO I/O DEVICE)

GNO

* WORD COUNT OVERFLOW

+3V

lOUTPUT TO I/ODEVICE)

Figure 5-17. Single Cycle Data Break Input Transfer Timing Diagram

5.3.3

Output Data Transfers

Timing of operations occurring in a single-cycle output Data Break is shown in Figure 5-19. Basic logic circuits for
the device interface used in this type of transfer are shown in Figure 5-20. Address and control signal generators are
similar to those discussed previously for input data transfers, except that the Transfer Direction signal must be at

ground potential to specify the output transfer of computer information. An output data register (OB in Figure
5-20) is usually required in the device interface to receive the computer information. The device must supply strobe
pulses for all data transfers out of the computer (programmed or data break) since circuit configuration and timing
characteristics differ in each device.

5-23

ADDRESS

ARO

AR1

ADDRe

zy
y-

BREAK REQUEST

6R0UMD TO REQUEST BREAK CYCLE

>T0 PDP-12

ADDRESS ACCEPTED (FROM PDP-121

DRO

~~~J)C^D.

::::>
(•

DIRECTION

(

+ 3 FOR INPUT)

CYCLE SELECT

NOTE

;

AR=ADDRESS
DR=DATA REGISTER
D=TRANSFER DIRECTION (FLIP-FLOP)
BR=BREAK REQUEST (FLIP-FLOP)

Figure 5-18. Device Interface Logic for Single-Cycle Data Break Input Transfer

5-24

TPS

TP»

COMPUTER TIME
I

-NEXT CYCLE
-S10N*L MUST<!OTO + SV*TST*I»TOF»00«SS*CCEPT PULSE IF NEXT CYCLE

BREAK SYNC FLIP FLOP

•

SET AT SAMPLE TIME

(INTERNAL)

USED TO SELECT BNEAK CYCLE AT TP

TO BE * MEAi

3 CYCLE

CYCLE SELECT
(SAMPLE TO PROCESSOR)
1

CYCLE

+ 3V
e- BREAK SIGNAL
(OUTPUT TO I/O DEVICE)

DATA ADDRESS
INPUT LEVELS
(INPUT TO PROCESSOR)

•

ENO OF BREAK CYCLE

START OF BWE AK CYCLE

SND
+ 3V

EAD AT
TPI BY
address t
/Xext.mem
READ —^ PROCESSOR
R

_•

GND

EARLIEST TIME POSSIBLE TO REMOVE AOORESS IS AT START OF BREAK CYCLE

+ 3V

ADDRESS ACCEPT PULSE
(OUTPUT TO 1/0 DEVICE)

GND
IN (-fSV)

TWANSFER DIRECTION
(INPUT TO PROCESSOR)

DATA SKXAL INPUT TO MB
(INPUT TO PROCESSOR)

LATEST POSSIBLE TIME IS TP2

OOT (GND)
AVAIL (+3V)

LATEST POSSIBLE TIME TO SPECIFY
INPUT DATA ISTPi

NOT AVAIL (GND)
TPUT DATA AVAILABLE IN MB
(OUTPUT TO I/O DEVICE)

:^m^

-CAN OUNCE ANYTIME AFTER TP 3

AMAIL(43V)

AVAILABLE AT TP3

-TIME DURING WHICH DATA MUST BE STROBED BY I/O DEVICE

NOTAVHIL (+3V)

MB INCREMENT REQUEST

NO REQUEST (+3V)

MUST OCCUR EARIER THAN TP 2

(INPUT TO PROCESSOR!

•IrEOUMWB*

MUST OCCUR ONLY WHEN B BREAK -

REQUEST (GNOI
+3V

BTS5
(OUTPUT TO I/O DEVICE)

SRN

BTS2

+3V

(OUTPUT TO I/O DEVICE)

6N0
* 1»C)RD COUNT OVERFLOW
(OUTPUT TO I/O DEVICE)

+3V

SIGNAL MOT USED FOR OUTPUT

TRANSFERS

SHOWN FOR REFERENCE ONLY

Figure 5-19, Single-Cycle Data Break Output Transfer Timing Diagram

5-25

—

ADDRESS a

ADDRESS

ADDRESS
<i

BREAK REQUEST L

-_)^
ADDRESS ACCEPTED L

BREAK

BTS5

::r>

ENABLE

B BREAK

OBI

r[>

:i>

DIRECTION
(0 FOR OUTPUT)

NOTE:

OB = OUTPUT BUFFER
AR = ADDRESS REGISTER
BR = BREAK REQUEST
IFLIP-FLOP)

rry--

-^>

f>
CYCLE SELECT

Figure 5-20. Device Interface Logic for Single-Cycle Data Break Output Transfer

5-26

When the Break Request is recognized the computer completes the current instruction and generates an Address
Accepted pulse as it enters the Data Break cycle. At TPl time, the address supplied to the PDP-12 is loaded into
the MA, and the Break state is entered. Not more than 900 nsec after TPl (at time TP3), the contents of the
device-specified core memory address are read and available in the MB. (This word is automatically rewritten at the

same address during the last half of the Break cycle, and is available for programmed operations when the Data
Break is finished.) Data Bit signals are available as static levels of ground potential for binary Os and +3v for binary
Is.

The

MB is changed at time TP3 of each computer cycle, so the data word is available in the MB for

approximately 1.6 microseconds to be strobed by the device interface.

Generation of the strobe pulse by the device interface can be synchronized with computer timing through use of
timing pulses BTS2 or BTS5, which are available at the computer interface. In addition to a timing pulse (delayed
or used directly from the computer), generation of this strobe pulse should be gated by condition signals that occur

only during the Break cycle of an output transfer. Figure 5-20 shows typical logic circuits to effect an output data
transfer. In this

example, BTS5 and B

BREAK set the BREAK ENABLE flip-flop, which remains set for one

computer cycle (unless successive cycles are requested). This enabling signal loads the buffered MB lines into the
data inputs of a D type flip-flop. At BTS2 time, the data will be clocked into the Output Buffer flip-flops. Note
that

BTS2 can generate a strobe pulse only during a BREAK ENABLE cycle. Interface input gates are Ml 01;

output bus drivers are M623.

By careful design of the input and output gating, one register can serve as both the input and the output buffer
register.

Most DEC options using the Data Break facility have only one data buffer register with appropriate gating

to allow it to serve as an output buffer when the Transfer Direction signal is at ground potential or an input buffer

when the Transfer Direction signal is +3v.

5.3.4

Memory Increment

In this type of Data Break the contents of core memory at a device-specified address are read into the MB, are

incremented by

and are rewritten at the same address within one 1.6-microsecond cycle. This feature is

particularly useful in building a histogram of a series of measurements, such as in pulse-height analysis applications.

For example, in a computer-controlled experiment that counts the number of times each value of a parameter is
measured, a Data Break can be requested for each measurement, and the measured value can be used as the core

memory address to be incremented (counted).
Signal interface for a

memory increment Data Break is similar to an output transfer Data Break except that the

MB signal and does not generate a strobe pulse (no data transfer occurs
PDP-12
I/O
device).
Timing
of memory increment operations appear in Figure 5-21
and
the
between the
device interface generates an Increment

5-27

TPZ

COMPUTER TIME
|

-NEXT CYCLE
-SIOWAL MOST GO TO+JV AT START OF AOOACSS ACCEPT PULSE IF NEXT CYCLE

SAMPLED AT OFF- PAUSE BY PROCESSOR

SAMPLE
SET AT SAMPLE TIME

AT TP

USED TO SELECT BMCAK CYCLE AT TP

TO BE A BREAK

J SAMPLED AT TPI

j^~TYPICALLY HARDWIRED FOR A GIVEN DEVICE
1

CYCLE
-t-SV
•

START OF BREAK CYCLE

EMC OF BREAK CYCLE

6N0
+ 3V

DATA ADDRESS
INPUT LEVELS
(INPUT TO PROCESSOR)

yixT.MEM.

/ADDRESS
_• HEAD

QND

AT
• •- EARLIEST TIME POSSIBLE TO REMOVE AOORESS
^ READ
TPI BY
PROCESSOR
I

AT START Of BREAK CYCLE

l__

+ 3V

GND
IN

(+JV)

•

LATEST POSSIBLE TIME IS TP2

OUT (GNO)

-CAN CHANGE ANYTIME AFTER TPS

—JEbbbbdCddI

*VAIL(+3V) •

:=^3==

NOT AVAIL (GNO)
OUTPUT DATA AVAILABLE IN MB
lOUTPUT TO 1/0 DEVICE)

CAN CHAHM ANYTIME AFTER TRS

AVAIL {+3V)

AVAILABLE AT TPS

-TIME DUNMG WHICH DATA MUST BE STROBED BY I/O DEVICE

NOT AVAIL (+3V)

NO REQUEST (+3V)
MUST FALL EARLIER THAN TP 2

imaSmoj

"'^'^ occur only when b break • i

REQUEST (GND)
+3V

CRN
+3V

GNO
* WORD COUNT OVERFLOW
(OUTPUT TO I/O DEVICE)

+3V
OCCUffS IF MEMORY INCREMENT IS RCOUCSTEO
AND THE WORD COUNT OVERFLOWS

SIGNAL NOT USED
SHOWN FOM REFERENCE ONLY

Figure 5-21

OFF-PAUSE OCCURS 200i>» BEFORE TP5 IF lOP INSTRUCTION
IN PROCESS, OFF lOP SAMPLES BREAK REQUEST.
.

Memory Increment Data Break Timing Diagram

An interface for a device using memory increment Data Breaks must supply twelve Data Address signals, a Transfer
Direction signal, a Cycle Select signal, and a Break Request signal to the computer Data Break facility as in an

output transfer data break. In addition, a ground potential increment MB signal must be provided at least 250

nanoseconds before time TP3 of the Break cycle. The signal can be generated in the device interface by ANDing the

B Break Computer Output signal, the output transfer condition of the Transfer Direction signal, and the Condition
signal in the device that indicates that an increment operation should take place. When the computer receives this

Increment MB signal, it forces the MB control element to generate a Carry Insert signal at time TS3 to increment
the contents of the MB.

5-28

5.3.5 Three-Cycle Data Breaks

Timing of input or output three-cycle Data Breaks is shown in Figure 5-22. The three-cycle Data Break uses the
block transfer control circuits of the computer. The block transfer control provides an economical method of
controlUng the flow of data at high speeds between PDP-12 core memory and fast peripheral devices, e.g., drum,
disc, magnetic tape and line printers, allowing transfer rates in excess of 208 kHz.

TP2

TP3

TP4

IPS

TPl

|«

.SAMPLED AT
"loFF- PAUSE Br

[processor*

TPJ

TP3

TP4

TPS

TP2

TPI

WORD COUNT STATE

TP5
I

TP4

TP5

TPI

TP2

CURRENT AOORESS STATE

TP3 TP4 TP5
I

BREAK CTCLE

TPI

TP2

TPJ

TP4 TP5
I

TPI
I

»)

-^
I

-SAMPLED AT TPI

+JV SNO
EXT. MEM.

ADDRESS
SAMPLED

SAMPLED AT TPI

FF REGISTER SUPPLIES THESE INPUTS TIMING IS IDENTICAL TO THAT SHOWN ON FIG. 5- 13

SND
IN

(«Vl
SAMPLED AT TPS OF SRCAK CYCLE

O0T(SN0)
AVAIL.

LATEST POSSIBLE TIME TO SPECFV INPUT DATA IS 900 NS BEFORE TP S-*!

SAMPLED AT TPS BY PROCESSOR

NOT AVAIL,
AVAIL.

AVAILABLE AT TPS -

NOT KKAIL. •
+ 3V

•

-TPJ OCCURS ONLY DURING LAST TRANSFER OF A BLOCK TRANSFER

GNO
+3V

LATEST POSSIBLE TIME TO SPECIFY INHIBIT CA
INCREMENT IS 3O0 NS BEORE TPI

B SRE&K SIGNAL

+3V

-SAW LED AT TPS BY PROCESSOR

_1_

SND
.

START OF BREAK CYCLE

(OUTPUT TO I/O DEVICE)

CND

END OF BREAK CYCLE

•1-3V

(OUTPUT TO I/O DEVICE)

GND

+JV

* OFF-PAUSE OCCURS SOOm BEFORE

TP5. IF lOP INSTRUCTION IN PROCESS, OFF

lOP

J1~

SAMPLES BREAK REQUEST.

Figure 5-22. Three-Cycle Data Break Timing Diagram

The three-cycle Data Break facility provides separate current address and word count registers in core memory for
the connected device, thus eliminating the necessity for flip-flop registers in the device control.

When several

devices are connected to this facility, each is assigned a different set of core locations for word count and current
address, allowing interlaced operations of all devices as long as their combined rate does not exceed 208 kHz. The

device specifies the location of these registers in core memory, and thus the software remains the same, regardless

of what other equipment is connected to the machine. Since these registers are located in core memory, they may
be loaded and unloaded directly without the use of lOT instructions. In a procedure where a device request to
transfer data to or from core

memory, the three-cycle Data Break facility performs the following sequence of

operations:
a. An address is read from the device to indicate the location of the word count register. This address is
always the same for a given device; thus it can be wired in and does not require a flip-flop register.

5-29

The contents of the specified address are read from memory and 1 is added before rewriting. If the
as a result of the addition, a WC Overflow pulse will be transmitted to the device.
contents of this register become
To transfer a block of N words, this register is loaded with -N during programmed initialization of the device. After
b.

the block has been fully transferred this pulse is generated to signify completion of the operation.
c.

The next sequential location is read from memory as the current address register. Although the contents of

this register are normally

incremented before being rewritten, an increment CA inhibit (+ 1 -^ CA Inhibit) signal

from the device may inhibit incrementation. To transfer a block of data beginning at location A, this register is
program initialized by loading with A-1.

The contents of the previously read current address are transferred to the MA to serve as the address for
the data transfer. This transfer may go in either direction in a manner identical to the single-cycle Data Break
system. The three-cycle Data Break facility uses many of the gates and transfer paths of the single-cycle Data Break
d.

system, but does not preclude the use of standard Data Break devices.

Any combination of three-cycle and

Data Break devices can be used in one system, as long as a multiplexer channel is available for each.
Two additional control lines are provided with the three-cycle data break. These are:
single-cycle

Word Count Overflow - A level change from GND to +3V, from TP3 of the cycle requesting the word count to
TP3 of the next cycle is transmitted to the device when the word count becomes equal to zero.
Increment CA Inhibit - When ground potential, this device-supplied signal inhibits incrementation of the current
address word.
In

summary, the three-cycle Data Break is entered similarly to the single-cycle Data Break, with the exception of

supplying a ground-level Cycle Select signal to allow entry of the WC (Word Count) state to increment the fixed
core memory location containing the word count. The device requesting the break supplies this address as in the
single-cycle

Data Break, except that this address is fixed and can be supplied by wired ground and +3V signals,

rather than from a register. Following the

WC state, a Current Address (CA) state is entered, in which the core

memory location following the WC address is read, incremented by one, restored to memory, and used as the
transfer address (by

5.4

MB -^ MA). Then the normal Break (B) state is entered to effect the transfer.

INTERFACE DESIGN AND CONSTRUCTION

This section describes the PDP-12 interface techniques, available modules, interface conventions, and interface
connections.

5.4.1

PDP-12 Interface Modules

PDP-12 interfacing is constructed of Digital FLIP-CHIP modules. The Digital Logic Handbook describes more than
150 of these modules, their component circuits, and the associated acessories; i.e., power supplies and mounting
panels.

The user should study this catalog carefully before beginning the design of a special interface.

The interface modules of the PDP-12 are the Mill, M906, M516, M660, and M623 modules. Interface signals to
the computer use either a combination of the Ml 1 1 and M906 modules or the MS 16 module. Interface signals from
the computer will originate from a combination of M623 and M906 modules for data signals, and M660 modules
for timing signals.

Ml 11/M906 Positive Input Circuit (See Figure 5-23) -The Mill Inverter module is used in conjunction
with the M906 Cable Terminator module, which clamps the input to prevent excursions beyond +3 volts and
ground. The M906 also provides the puUup resistors to +5 volts.

5.4.1.1

5-30

B1 Q

OUTPUT SIGNAL TO PROCESSOR

Milt
(

6 INVERTERS)

A1 Q

r
+5V

-WV

M906
(18 C IRCUITS)

BIO POSITIVE BUS INPUT SIGNAL
(FROM EXTERNAL DEVICE)
12-0136

Figure 5-23. Typical Ml 1 1/M906 Positive Input Circuit

M516 Positive Bus Receiver Input Circuit (See Figure 5-24) — Six four-input NAND gates with overshoot
and undershoot clamp on one input of each gate. Pullup resistors connected to +5V are also provided.
5.4.1.2

8 1 p

OUTPUT SIGNAL TO PROCESSOR

M516
(SIX GATES

)

5P^
-O 01

-O CI
-O 81

A1 6

——

USED
INTERNALLY

-1-5V

POSITIVE BUS INPUT SIGNAL
(FROM EXTERNAL DEVICE)
12-0136

Figure 5-24. Typical M5 1 6 Positive Bus Receiver Input Circuit

- The M623 Bus Driver module contains twelve
M906 Cable Terminator module, the output is

5.4.1.3

M623/M906 Positive Output Circuit

circuits

with negative NOR gates. Used in conjunction with the

(See Figure 5-25)

clamped to prevent excursions beyond +3 volts and ground. Output can drive +5 milliamperes at the high level and
sink 20 milliamperes at the low level.

5-31

M906

(18 CIRCUITS)

POSITIVE BUS OUTPUT SIQNALS
{TO EXTERNAL DEVICE)

^""
OBI
AlO
OUTPUT SIGNALS FROM PROCESSOR

12-0136

Figure 5-25. Typical M623/M906 Positive Output Circuit

5.4.1.4

M660 Bus Driver Output Circuit (See Figure 5-26) — Three circuits which provide low impedance 100-ohm

terminated cable driving capability using

M Series levels or pulses of duration greater than 100 nanoseconds. The

output can drive 5 ma at the high level and sink 20 ma at the low level, in addition to termination current required

by the G717 termination module. The M660 module is used in the PDP-12 for the following output signals:

lOP 1 lOP 2, lOP 4, TS 2, TS 5
,

POSITIVE BUS OUTPUT SIGNAL
(TO EXTERNAL DEVICE)
O D2

M660
(

3 CIRCUITS)

OUTPUT SIGNAL
FROM PROCESSOR
I

12-0136
Figure 5-26.

5.4.1.5

Module Selection for

M660 Terminated Bus Driver Output Circuit

Interface Circuits of Peripheral

Equipment -

Two FLIP-CHIP modules are of

particular interest in the design of equipment to interface with the PDP-12. Complete details on these and other

FLIP CHIP modules can be found in the Digital Logic Handbook.

5-32

Ml 03 Device Selector (See Figure 5-27) — The Ml 03 selects an input/output device according to the code
word (being held in the memory buffer during the lOT cycle). Ml 03 module includes diode
protection clamps on input lines so that it may be used directly on the PDP-12 positive bus.
5.4.1.6

in the instruction

-O K1

Ml O

U2 O-

02 OE2 OF2 O-

M2 OJ2 OK2 O-

L2 ON2 0-

BMB 03(01
BMB 04(0)

r> ^:>

DEVICE

SELECTED

-O V2

BMB 05(0)

BMB 06(0)
BMB 07(0)
BMB 08(0)
NOT USED
NOT USED
P2 O-

BIOP

•^
1

\>_^poh>^
I0T1

-O B1

>-,^-^I0T2
R2 O-

BIOP 2

I0T2

-O01

S2 0-

BIOP 3

\)--^^-<i\l£I^
I0T4

-O F1

FROM PROCESSOR I/O BUS
TO

Figure 5-27.

5.4.1.7

EXTERNAL DEVICE

Ml 03 Device Selector Logic Circuit

Ml 01 Bus Data Interface (See Figure 5-28) - Fifteen two-input NAND gates with one input of each gate
common line. For use in strobing data off of the PDP-12 I/O bus. The Ml 01 module includes diode

tied to a

protection clamps on input lines so that it may be used directly on the PDP-1 2 positive bus.

5-33

BAC 07

DEVICE SELECTED (FROM MI03)
CI

O-

BAC

BAC 00

82 O-

08
-O P2

-O 81

>H2

BAC 01

BAC

,__)^^"
BAC

BAC 02
PI

O-

K2 O-

O-

O L2
TO EXTERNAL
DEVICE

BAC 03

M2 O-

O-

BAC

-O K1

O-

O N2

BAC 04
-o R2

O-

BAC 05

S2 O-

)^^—

Z\
Rl

O-

BAC 06

j^^^'

U2 O-

p
Figure 5-28.

5.4.2

O SI

O Y2

Ml 01 Bus Data Interface Logic Circuit

M Series Flip Chip Modules

The following is a list of M Series modules available from Digital Equipment Corporation that can be used in
designing special interfaces and special devices. The majority of these modules are described in the Digital Logic
Handbook. For those that cannot be found in the Handbook, contact the nearest Digital representative.

5-34

Table 5-2.

Type

M002

M Series Module Summary

Function

15 Loads

Description

Fifteen +3 volt sources each capable of driving ten
unit loads. Can be used for tying off unused inputs.

M040

Solenoid Driver

Output ratings of -70 volts and 0.6 amp allow these

two drivers to be used with a variety of medium
current loads.

M050

50 ma Indicator and
Relay Driver

Output ratings of -20 volts and 50 ma. Allow any
of the twelve circuits on this module to drive a
variety of incandescent lamps. These drivers can
also be used as slow speed open collector PNP level
shifters to -3 volt systems.

MlOl

Bus Data Interface

Fifteen two-input

each

gate

tied

NAND gates with one input of

common line. For use in

strobing data off of the PDP-8/I or PDP-12 I/O
bus. Pin compatible with Mill.

Ml 03

Device Selector

Similar to W103, but for use with PDP-8/I and
PDP-12 options. Output pulses are not regenerated

but only buffered.

Mill

Inverter

Sixteen inverter circuits with a fan-in of one unit
load and fan-out of ten unit loads.

M112

NOR Gate

Ten positive NOR gates with a fan-in of one unit
load and fan-out of ten unit loads.

M113

M115

10 2-Input

Ten two-input positive NAND gates with a fan-in

NAND Gates

of one unit load and fan-out of ten unit loads.

8 3-Input

Eight

NAND Gates

fan-in of one unit load

three-input

positive

NAND gates with a

and a fan-out of ten unit

loads.

M117

M119

NAND gates with a fan-in

6 4-Input

Six four-input positive

NAND Gates

of one unit load and a fan-out of ten unit loads.

3 8-Input

Three eight-input positive

NAND Gates

fan-in of one unit load

NAND gates with a

and a fan-out of ten unit

loads.

M121

AND/NOR Gates

Six gates which perform the positive logic function

AB + CD. Fan-in on each input is one unit load and
gate fan-out is ten unit loads.

5-35

Table

5-2.

Type

Function

M141

NAND/OR Gates

M Series Module Summary (cont)
Description

Twelve two-input positive NAND gates which can
be used in a wired OR manner. Gates are grouped
in a 4-4-3-1 configuration, with a fan-in of one unit

load and a fan-out which depends on the number

of gates ORed together.

M160

Gate Module

Three general purpose multi-input gates which can
be used for system input selection. Fan-in is one
unit load and fan-out is ten unit loads.

M161

Binary to Octal/

A binary-to-eight line or BCD -to -ten line decoder.

Decimal Decoder

Gating is provided so that up to six binary bits can

be decoded using only Ml 6 Is. Accepts a variety of

BCD codes.
M162

Parity Circuit

Two

of which

each

circuits,

can

used

generate even or odd parity signals for four bits of

binary input.

M169

Gating Module

Four circuits that can be used for input selection.
Each circuit is of an AND/OR configuration with
four two-input AND gates.

M202

Triple J.K.

Three J-K flip-flops with multiple input AND gates

Flip-Flop

and K. Versatile units for many control or

counter purposes. All direct set and clear inputs are
available at module pins.

M203

Set-Reset

Eight single-input set/reset flip-flops for use as

Flip- Flops

buffer storage. Each circuit has a fan-in of one unit

load and a fan-out of ten unit loads.

M204

Counter-Buffer

Four J-K flip-flops which can be interconnected as
a ripple or synchronous counter or used as general

control elements.

M206

Six Flip-Flops

Six D-type flip-flops
registers

counters,

which can be used in shift
and general

buffer registers,

purpose control functions.

M207

Flip- Flops

Six single-input J-K type flip-flops for use in shift
register,

counters,

and

general

purpose

connected

8-bit

buffer

or shift

ripple

control functions.

M208

Buffer Shift Register

internally

parallel

input.

5-36

load,

bipolar parallel

output, and

serial

Table 5-2.

Type

M211

M Series Module Summary (cont)

Function

Description

Binary Up/Down

A six-bit binary up/down ripple counter with

Counter

control gates for direction changes via a single
control line.

M212

6-Bit L-R

An internally

Shift Register

Provisions are made for gated single-ended parallel

connected

left/right shift register.

load, bipolar parallel output, and serial input.

M213

BCD Up/Down

One decade of 8421 up

Counter

possible with this module. Provisions are made for

down counting

parallel loading, bipolar output, and carry features.

M230

Binary to BCD Shift

One decade of a modified

allows high speed conversion (100 nsec per binary
bit) of binary data to

8421

shift

which

BCD code. System use

of this module requires additional modules.

M302

One Shot Delay

Two pulse or level triggered one-shot delays with
output delay adjustable from 50 nsec to 7.5 msec.
Fan-in

2.5 unit loads and fan-out

25 unit

loads.

M310

Delay Line

Fixed tapped delay line with delay adjustable in
50-nsec increments from 50 nsec to 500 nsec. Two
digital

output

amplifiers

and

one

driver

are

included.

M360

Variable Delay

Continuously variable delay line with a range of 50
nsec

500

nsec.

Module includes delay

line

drivers and digital output amplifiers.

M401

Clock

gateable

clock

negative pulse outputs.

with

both positive and

The output frequency is

adjustable from 10 MHz to below 100 Hz.

M405

Crystal Clock

Stable system clock frequencies from 5 kHz to 10

mHz are available with this module. Frequency
drift at either the positive or negative pulse output
is less than

M410

Reed Clock

0.01% of the specified frequency.

A stable low frequency reed control clock similar
to the M452. Stability in the range 0°C to 70°C is
better than 0,15%. For use with communications

systems and available with only standard teletype

and data set frequencies.

M452

Variable Clock

Provides square wave output of 880 Hz, 440 Hz,

and 220 Hz necessary for clocking the M706 and
M707 in a 1 10-baud teletype system.

5-37

Table

5-2.

M Series Module Summary (cont)

Type

Function

Description

M501

Schmitt Trigger

Provides regenerative characteristics necessary for
sv^itch filtering, pulse shaping,

sensing. This circuit can be

M502

and contact closure

AND/OR expanded.

Negative Input

Pulses as short as 35 nsec can be level shifted from

Converter

-3 volt systems to standard

M Series levels by the

two circuits in this converter. This module can also
drive low impedance terminated cables.

M506

Negative Input

This converter will level shift pulses as short as 1 00

Converter

nsec from -3 volt systems to

M Series levels. Each

of the six circuits on this module provides a low

impedance output for driving unterminated long
lines.

M507

Bus Converter

Six

inverting level

shifters

which accept -3 and

GND, as inputs and have an open collecter NPN
transistor at the output. Output rise is delayed by
1

M516

00 nsec for pulse spreading.

NOR gates with overshoot and

Positive Bus

Six

Receiver

undershoot clamps on one input of each gate. In

four-input

addition, one input of each gate is tied to +3 volts

with the lead brought out to a connector pin.

M602

Pulse Generator

The two pulse amplifiers in this module provide
standard 50-nsec or 110-nsec pulses for

M Series

systems.

M617

M627

6-4 Input

NOR

Six four-input positive

NOR gates with a fan-in of

Buffers

one unit load and a fan-out of 30 unit loads.

Power Amplifier
Module

with a fan-in of 2.5 unit loads and a fan-out of 40

Six

four-input high speed positive

NAND gates

unit loads.

M650

Negative Output

Converter

The three non-inverting level shifters on this
module can be used to interface the positive levels
or pulses (duration greater than 1 00 nsec) of K and

M Series to -3 volt logic systems.
M652

Negative Output

These two circuits provide high-speed non-inverting

Converter

level shifting for pulses as short as 35 nsec or levels

from M Series to -3 volt systems. The output can
drive low impedance terminated cables.

M660

low-impedance

Positive Level

Three

Driver

100-ohm terminated cable driving capability, using

circuits

which

provide

M Series levels or pulses of duration greater than
100 nsec. Output drive capability is 50 ma at +3
volts or ground.

5-38

Table

5-2.

M Series Module Summary (cont)

Type

Function

M661

Positive Level

Three

Driver

unterminated

Description

which

circuits

similar to

cable

low-impedance

provide

driving.

Characteristics

are

M660 with the exception that +3 volts

drive is 5 ma.

M730

8/1 Bus Positive

General Purpose positive bus output module for

Output Interfacer

use in interfacing

many positive level (0 to +20

volt) systems to the PDP-8/I or

PDP-12. Module

includes

parallel

device

selector,

12-bit

output

buffer, and adjustable timing pulses.

8/1 Bus Negative

M731

Output Interfacer

Identical to M730, except outputs are level shifted

to -20 volt systems to the PDP-8/I or PDP-1 2.

for

Module includes device

selector,

12-bit

parallel

input buffer, and adjustable timing pulses.

M733

8/1 Bus Negative

Identical to

M732, except inputs are level shifted

from negative voltage systems.

M90I

Flexprint® Cable

Double-sided 36-pin Flexprint cable connector. All

Connector

pins are available for signals or grounds. Pins A2,

B2, Ul, and VI have 10 f2 resistors in series.

M902

Resistor Terminator

Double-sided 36-pin terminator module with 100
12

terminations on signal leads. Alternate grounds

are provided as in the M903 and M904.

M903

Connector

Double-sided

36-pin

Flexprint

cable

connector

with alternate grounds for I/O bus cables.

M906

Cable Terminator

18 load resistors clamped to prevent excursions

beyond +3 volts and ground. It may be used in
conjunction

with

the

M623

provide

cable

driving ability.

5.4.3 Construction of

nterfaces

This section provides the interface designer with information on design procedures, module layout, wiring, and
cable selection. Additional help may be obtained from local DEC sales offices.

5.4.3.1

Physical

— The PDP-12 was designed to provide the user maximum ease and flexibility in implementing

special interfaces.

External devices and interfaces are constructed and mounted outside of the basic machine,

thereby eliminating the necessity for modifications to the basic processor. All signals to and from the computer are
carried on coaxial or Flexprint cables.

©Flexprint is a registered trademark of Sanders Associates, Inc.

5-39

To implement several devices, the cables parallel-connect each peripheral in a serial type form (see Figure 5-29).
Three dual cables are used for program interrupt cable connections in (or out). Two additional dual cables are used,
for a total of five, when Data Break devices are implemented.

5.4.3.2

Module Layout — In general, module layout is based on the functional elements within a system and is

primarily a matter of common sense.
Digital has, however, layout conventions for I/O cabling to extend devices. The interface designer may wish to use

these conventions as a guide.

The general rule is DO NOT DEAD END THE I/O BUS. This means that parallel

connections should always be made at each device to handle possible future expansion.

DUAL PROGRAM
INTERRUPT CABLES

9-^
2 DUAL DATA

BREAK CABLES

DEVICE

PDP-12

Figure 5-29.^ I/O Bus Configuration

Figure 5-30 shows

the I/O cable connections in an option mounting panel.

Module slot locations

(looking at the wiring pin side) are reserved for program transfer cable connections in (or out).

through 3

Module slot

locations 4 to 5 are reserved for data break cable connections in (or out). Slot 6 is used for Sense lines.

Module slot locations 1 through 6 in the bottom half of the option mounting panel are wired in parallel with the
top module slot locations 1 through 6. To continue the I/O cabling to the next device, the bottom slots are used,
and the I/O cable connections are exactly the same as mentioned above.

5.4.3.3 Cable Selection — Two types of cables are recommended for I/O interface connections.

The first is 9-conductor coaxial cable. This cable protects systems from radiated noise and cross talk between
individual lines. Coax cable used and sold by Digital has the following nominal specs:

Z = 95 ± 5 n
C = 13.75 pF/foot approx. (unterminated)
L = 124 nH/foot approx.

R = 0.095 n/foot nominal

Y = 79% of velocity of light, approx. (1.5 tisec/ft.)

5-40

The second type is a 19-conductor (9 signals and 10 grounds), #30 gauge flat copper Flexprint.
The total length of I/O cabling, from the PDP-12 to the last device, can be a maximum of 50 feet, and can be
composed of 50 feet of coax or a combination of coax and Flexprint, in which case the Flexprint cannot exceed a
total of 15 feet.

5.4.3.4 Connector

Selection

— Of the many connectors available in the module product line, several have

particular application to I/O connectors. Price and ordering information is available on these and other connectors
in the Digital Logic

Handbook. Of particular interest are the M903 and M904 connectors described

in the

subsequent paragraphs.

CABLE LOCATION

BACOOTO

AC 00 BUS
TO

BAC11

DATA ADD 00
TO

-f

-i

DATA 00
TO
DATA 11

DATA ADD 11

BT 53, 1

CA INCREMENT

INTRQSTBUS

B INITIALIZE

BMB 00 TO
BMB 11

AC CLEAR
BUS

SENSE
LINES

MB INCREMENT

EXT DATA ADD

B ADD

ACCEPTED
B BREAK

B WC
OVERFLOW

8 INITIALIZE

SAME ASSIGNMENTS AS ABOVE

Figure 5-30. I/O Cable Connections

5-41

M903 Connector — Double sided 36-pin Flexprint cable connector with alternate grounds for I/O bus

cables. (Two Flexprint cables are utilized with this connector module.)

M904 Connector - Double-sided 36-pin coaxial cable connector with alternate grounds for I/O bus cables.

(Two coax cables are utilized with this connector module).
(1) Signals:

B1,D1,E1,H1,J1,L1,M1,P1,S1,
D2, E2, H2, K2, M2, P2, S2, T2, V2
(2) Grounds:

A1,C1,F1,K1,N1,R1,T1,
C2, F2, J2, L2, N2, R2, U2
Signal Terminating — The G717 module is used for terminating the following signals:

lOP 1,I0P2, I0P4, TS2,TS5.
This module contains five

O0*ohm terminating resistors and should be located in the last device of the I/O cabling

scheme.

Wiring Hints — These suggestions may help reduce mounting panel wiring time. They are not intended to replace

,any special wiring instructions given on individual module data sheets or in application notes. For fast, neat wiring,
the following order is recommended:

All power wiring (Pins A2, B2, C2, Tl) and any horizontally bussed signal wiring. Use Horizontal Bussing

Strips, Type 933. (Pin-B2 is bussed with -15V for modules requiring -15V,)

Vertical grounding wires interconnect chassis ground with Pins C2 and Tl grounds. Run these wires from

the uppermost mounting panel to the bottom panel. On the first and last blocks of the mounting panel, connect
the grounds to the chassis.

All other ground wires. Always use the nearest ground pin, unless a special grounding pin has been provided

in the module.

Wire all signal wires in convenient order. Point-to-point wiring produces the shortest wire lengths, goes in
fastest, is easiest to trace and change, and generally results in better appearance and performance than cabled
4.

wiring. Point-to-point wiring is strongly urged.

The recommended wire size for use with H803 mounting blocks and H9 1 1 mounting panel is #30. Larger or
smaller wire may be used depending on the number of connections to be made to each lug. Solid wire and a heat
resistant insulation is recommended. The H803 mounting blocks are only available with wire wrap pins which
necessitates the use of a wire wrap tool. (Digital can supply #30 gauge wire in

1000 foot rolls.)

Adequate grounding is essential. In addition to the connections between mounting panels mentioned above, there
must be continuity of grounds between cabinets and between the logic assembly and any equipment with which
the logic communicates.

5-42

When wire wrapping is done on a mounting panel containing modules, the wire wrap tool must be grounded, except
when all modules are removed from the mounting panel. This procedure must be followed because, even with tools
isolated from the ac power Une, such as those operated by batteries or compressed air, static charges may build to
sufficient amplitudes so that damage to semiconductors may result.

Cooling — The low power consumption of
typical H911

M Series modules results in a total of about

1 5

watts dissipation in a

mounting panel containing 64 modules. Convection cooling is sufficient for a few mounting panels,

but forced air cooling should be used when a very large system is built.

5,4.4

lOT Allocations

lOT

Option

Interrupt

High Speed Reader Type PR 1

High Speed Punch Type PP 1

Teletype Keyboard/Reader

Teletype Teleprinter/Punch

Displays, Types VC8/I and KV8/I

Displays, Types VC8/I, and Light Pen Type 370

1
1

Power Fail Option KP 1
Teletype System Type PT08
Teletype System Type PT08

Real Time Clock Type

Mode Change (lOT 6 1 4 1

Tape Maintenance

16
17

20
21

22
23

24
25

26
27
30

Memory Extension Control Option Type MCI 2
Memory Extension Control Option Type MCI
Memory Extension Control Option Type MCI 2
Memory Extension Control Option Type MC 1
Memory Extension Control Option Type MC 1
Memory Extension Control Option Type MC 1
Memory Extension Control Option Type MC 1
Memory Extension Control Option Type MCI
User Interfaces

User Interfaces

36
37
40

User Interfaces

Teletype System Type DP 12

User Interfaces
Teletype System Type DP 12

Teletype System Type PT08

5-43

Teletype System Type PT08

Incremental Plotter Type XY 1

General Purpose A/D Converters and Multiplexers, Types AFOIA, AM02A,

AM03A and AF04A Scanning Digital Voltmeter
54

General Purpose A/D Converters and Multiplexers, Types AFOIA, AM02A,

AM03A and AF04A Scanning Digital Voltmeter
D/ A Converter Type AAO 1
D/ A Converter Type AAO 1

D/A Converter Type AAOIA, Sample and Hold Control Type ACOIA and

AF04A Scanning Digital Voltmeter
Random Access Disk File and Control Type DF32 and Synchronous Modem

Interface Type DPOIA

Random Access Disk File and Control Type DF32 and Synchronous Modem

Interface Type DPOIA

Random Access Disk File and Control Type DF32 and Synchronous Modem

Interface Type DPOIA

63
64

Card Reader Type CR 1

Synchronous Modem Interface Type DPOIA

66
67
70

Card Reader Type CR12 and Synchronous Modem Interface Type DPOIA

Automatic Mag Tape Type TC58

Synchronous Modem Interface Type DPOIA
Synchronous Modem Interface Type DPOIA

Automatic Mag Tape Type TC58

DECtape Control TCOl
DECtape Control TCOl

76
77

5.4.5

Interface Connections

All interface connections to the

PDP-12

are

made at assigned module receptacle connectors in the Processor

Mounting Frame. Capital letters designate vertical rows of modules within a mounting frame. The letters progress
alphabetically from right to left when viewed from the wiring side. Module receptacles are numbered from top to

bottom within a row. Terminals are assigned capital letters from right to left, with the letters G, I, O, and Q
omitted. Double-sided connectors or modules use the suffix number 1 to designate the top side of a module and
the suffix number 2 to designate the bottom side.

The module receptacles and assigned use for interface signal connections are:
Use

Receptacle

5-44

N13

SENSE LINES

N 14

AC, lOP, TIMING OUTPUTS

N15

MB OUTPUTS

N
N
N

AC, SKIP, INT. REQUEST INPUTS

1
1

DATA BREAK ADDRESS INPUTS
DATA BREAK DATA INPUTS

Terminals Al, CI, Fl, Kl, Nl, Rl, Tl, C2, F2, J2, L2, N2, R2, and U2 of these receptacles are grounded within
the computer, and terminals Bl, Dl, El, HI, Jl, LI, Ml, PI, SI, D2, E2, H2, K2, M2, P2, S2, T2, and V2 carry
signals. Terminals

A2 and B2 are not used. These terminals mate with either M903 or M904 Cable Connectors,

Interface connection to the

PDP-12 can be established

for

all

peripheral equipment

by making series cable

connections between devices. In this manner only one set of cables is connected to the computer and two sets are

connected to each device; one receives the computer connection from the computer itself or the previous device,

and one passes the connection to the next device. Where physical location of equipment does not make series bus
connections feasible, or when cable length becomes excessive, additional interface connectors can be provided near
the computer. All logic signals passing between the PDP-12 and input/output equipment are positive voltage levels,

allowing direct TTL logic interface with appropriate diode clamp protection.

Positive level for a low logic state is

to 0.4 volts. Positive level for a high logic state is +3.6 volts.

The following table presents cable connections to the PDP-12 I/O Bus. A signal is true when its polarity matches
the suffix character of its name (i.e., 100 BAC 00 (1) H will be high when AC 00 (1) and a program interrupt will
be requested when the line EXT INT RQST BUS L is pulled low).

Table 5-3. Cable Connections to the PDP-12 I/O Bus

Signal

lOB XL 00 H
lOB XL 01 H
lOB XL 02 H
lOB XL 03 H
lOB XL 04 H
lOB XL 05 H
lOB XL 06 H
lOB XL 07 H

lOBXL 10 H

Connection

N13B1
N13D1
N13E1
N13H1
N13J1

N13L1

N13M1
N13P1
N13S1

IOOBAC00(l)H
lOOBACOl (1)H
IOOBAC02(1)H
IOOBAC03(1)H
IOOBAC04(1)H
IOOBAC05(1)H
IOOBAC06(1)H
IOOBAC07(1)H
IOOBAC08(1)H

N14B1
N14D1
N14E1
N14H1

IOOBMBOO(1)H
lOOBMBOl (1)H
IOOBMB02(1)H
100 BMB 03 (0) H
IOOBMB03(1)H
100 BMB 04 (0) H
IOOBMB04(1)H
lOO BMB 05 (0) H
lOOBMB 05(1)H

N15B1
N15D1
N15E1
N15H1

N14J1

N14L1

N14M1
N14P1
N14S1

N15J1

N15L1

N15M1
N15P1
N15S1

Signal

lOB XL 1 1 H

lOBXL 12 H
lOB XL 13 H
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED

Connection

N13D2
N13E2
N13H2
N13K2
N13M2
N13P2
N13S2
N13T2

N13V2

IOOBAC09(1)H
100 BAC 10(1)H
100 BAC 11 (1)H
100 BIOP 1 H
100 BIOP 2 H
100 BIOP 4 H
I00BTS5(1)H
I00BTS2(1)H
100 BA INITIALIZE H

N14D2
N14E2
N14H2
N14K2
N14M2

100 BMB 06 (0) H

N15D2
N15E2
N15H2
N15K2
N15M2

IOOBMB06(1)H
100 BMB 07 (0) H
IOOBMB07(1)H
100 BMB 08 (0) H
IOOBMB08(1)H
IOOBMB09(1)H
lOOBMB 10(1)H
100 BMB 11 (1)H

N14P2
N14S2
N14T2

N14V2

N15P2
N15S2
N15T2

N15V2

5-45

Table 5-3. Cable Connections to the PDF- 12 I/O Bus (cont)

Signal

Connection

Signal

Connection

EXT 10 BUS 00 L
EXT 10 BUS 01 L
EXT 10 BUS 02 L
EXT 10 BUS 03 L
EXT 10 BUS 04 L
EXT 10 BUS 05 L
EXT 10 BUS 06 L
EXT 10 BUS 07 L
EXT 10 BUS 08L

N16B1
N16D1
N16E1
N16H1

EXT 10 BUS 09L
EXT 10 BUS 10 L
L
EXT 10 BUS
EXT SKIP BUS L
EXT INT RQST BUS L
EXT AC CLEAR BUS L
100 B RUN (0) H
NOT USED
NOT USED

N16D2
N16E2
N16H2
N16K2
N16M2

EXT DATA ADD 00 L
EXT DATA ADD 01 L
EXT DATA ADD 02 L
EXT DATA ADD 03 L
EXT DATA ADD 04 L
EXT DATA ADD 05 L
EXT DATA ADD 06 L

N17B1
N17D1
N17E1
N17H1

N17D2
N17E2
N17H2
N17K2
N17M2

N17L1

EXT DATA ADD 09 L
EXT DATA ADD 10 L
L
EXT DATA ADD
EXT BREAK RQST L
EXT DATA IN H
100 BREAK (0) H

N17M1

100 ADD

EXT DATA ADD 07 L
EXT DATA ADD 08 L

N17P1
N17S1

ACCEPTED (0) H
EXT INCREMENT MB L
100 BB INITIALIZE H

N17S2
N17T2
N17V2

EXT DATA 00 L
EXT DATA 01 L
EXT DATA 02 L
EXT DATA 03 L
EXT DATA 04 L
EXT DATA 05 L
EXT DATA 06 L
EXT DATA 07 L
EXT DATA 08 L

N18B1

N18J1

EXT DATA 09 L
EXT DATA 10 L
EXT DATA 1 L
EXT 3 CYCLE L
lOB CA INCREMENT H

N18D2
N18E2
N18H2
N18K2
N18M2

N18L1

100 WC OVERFLOW (0) H

N18M1

EXT EXTEND DATA ADD 02 L
EXT EXTEND DATA ADD 01 L
EXT EXTEND DATA ADD 00 L

N18P2
N18S2
N18T2
N18V2

5^6

N16J1

N16L1

N16M1
N16P1
N16S1

N17J1

N18D1
N18E1
N18H1

N18P1
N18S1

1 1

N16P2
N16S2
N16T2

N16V2

N17P2

CHAPTER 6
PERIPHERAL DEVICES

INTRODUCTION
This chapter contains descriptions of all the standard prewired I/O bus options which are available with the

PDP-12.

describes the peripheral logic expander, BA12, and options contained within the panel, as well as the

most commonly used PDP-8 and PDP-12 family of I/O bus options. In general, most PDP-8 family of options can
be operated without modification on the PDP-12 I/O bus. The reader, therefore, should refer to the DEC Small

Computer Handbook (1970) for additional information.
Prewired options and options contained in the

PDP-12 power supply. The

BA12 Peripheral Expander panel derive their power from the

Peripheral Expander contains the necessary buffering to provide the isolation and

current driving requirements for I/O devices. The control logic for these options is contained in plug-in modules;
therefore,

when one of these options is added, wiring changes or additions are not needed. Separate power supplies

are normally included with all the other options.

Option Groupings

Option Type Number

Prewired
Teletype Model 33 ASR
Additional Teletype or Dataphone

DP12-A,B

Real-Time Interface

KW12-A

Fixed Interval Clocks

LINCtape to DECtape format converter

KW12-B,C
TC12-F

Digital Plotter and Control

XY12

Power Fail

KP12

Peripheral Expander Type BA12

4-Station 11 Y Control

Line Printer

DC02-D,E
LP12

High-speed Paper Tape Reader/Punch

PC12, PP12, andPR12

Standard or Mark Sense Card Reader

CR12, CM12

Data Buffers

DB12-P, N

6-1

Option Groupings

Option Type Number

I/O Bus Stand Alone Peripherals

32 Station TTY Control

Magnetic Tape Control

DC02-F,G
PT08
LP08
TC58

Magnetic Tape Transport

TU20

Disk Fixed Head, 32K
Disk Movable Head 800K

DF32, DS32
RF08, RS08
RK8, RKOl

A-D Converter
D-A Converter

AFOIA
AAOIA

and 2-Station TTY Control

Line Printer

Disk Fixed Head, 256K

The above groupings represent the physical organization of the PDP-12; however, the options will be described in
the following order:

Option Descriptions

6-2

Page Number

Teletype Controls (TTY)

5.3

Real-Time Interface and Clocks

5_18

Disks

6-27

Tapes

5.45

Line Printers

6-59

Card Readers

6-63

Plotters

6.68

High-Speed Paper Tape

5.7 j

Data Buffers

6-73

Power Fail/Restart

6-74

A-D Converter
D-A Converter

6-76
6-82

6.1

TELETYPE

6.1.1

Model 33 ASR

The Teletype Model 33 ASR is the standard Teletype device offered with the PDF- 12. It may be used to type in or
print out information at a rate of up to ten characters per second, or to read in or punch out perforated-paper tape
at ten characters per second. Signals transferred between the Model 33 ASR and the control logic are standard,
serial, 11 -unit code, Teletype signals. The signals consist of marks and spaces which correspond to idle and bias
current in the Teletype, and to zeros and ones in the teletype control and computer. The start mark and
subsequent eight-character bits are one-unit-of-time duration, and are followed by the stop mark, which occupies
two units. The 8-bit code used by the Model 33 ASR Teletype unit is the American Standard Code for Information
Interchange (ASCII) modified. To convert the ASCII code to Teletype code, add 200 octal (ASCII + 2008 =
Teletype). Bits are numbered from right to left, from 1 through 8, with bit 1 having the least significance.
Figure 6-1 illustrates the relationship between paper tape information and the AC.

SPROCKET
FEED HOLES

TAPE HOLE AND
CHANNEL NUMBERS

PAPER TAPE

AC BIT LOCATION

NOTE;
AC BITS 0-3 ARE NOT USED.

Figure 6-1. Relationship Between Paper Tape and Accumulator

The character (number) four (4) as it would be punched on paper tape is shown in Figure 6-2.

The Model 33 ASR set generates all assigned codes except 340 through 374 and 376. Generally codes 207, 212,
215, 240 through 337, and 377 are sufficient for Teletype operation. The Model 33 ASR detects all characters, but
does not interpret all of the codes that it can generate as commands. The standard number of characters printed per
line is 72. The sequence for proceeding to the next line is a carriage return followed by a line feed (as opposed to a
line feed followed by a carriage return). Appendix F lists the character codes for the Teletype.

6.1.2

Model 33 KSR

This Teletype model is similar to the 33 ASR, except that it does not have either a paper tape reader or punch. The
control logic, however, is the same as that used with the 33 ASR.

6-3

SPROCKET FEED HOLE
I

TAPE CHANNEL

BINARY CODE

(1 =

6
I

PUNCH)

OCTAL CODE

Figure 6-2.

6.1.3

Punched Paper Tape Format for the Number 4

Model 35 KSR

This unit is functionally the same as the 33 KSR.

It is

designed for heavy duty use and extended reliability. The

control logic, however, is the same as that used in the 33 ASR.

6.1.4

Models? KSR

This Teletype is offered as part of the LT37-AD, AE (50 Hz) option. It has an expanded character set (i.e., upper

and lower case) and control functions, and operates at 1 5 characters per second, both transmitting and receiving.

The LT37-AD option has a front panel switch which can effectively convert the unit to operate as a 33 ASR. Only
upper case characters would then be received or transmitted. The LT37 option provides the following programmed
operations:

Horizontal tab set and clear

Motor control; on and off
Vertical tab; set and clear at full line increments
d. Ribbon color shift

b.
c.

Reverse linefeed; full and half line increments

The LT37 is useful for the preparation of formal reports, business forms and graphical plots.
Table F-3 in Appendix F provides the character and control codes for each mode of operation.

6.1.5 Teletype Controls

The basic programmed operation of the following devices is similar:
Console Teletype
Prewired Dataphone Option, Type DP12-A, B

Add-on Single and Dual TTY Control, Type PT08-B, C

They all transmit and receive asynchronous, full-duplex, bit-word information. These devices use control modules

M706 (Receiver) and M707 (Transmitter), which are positive logic modules, or W706 (Receiver) and W707

6-4

(Transmitter), which are the negative equivalent logic control modules. These modules are fully described in the
Digital Logic Handbook. The main differences in these options being controlled are:

Source of data (e.g., Dataphone, keyboard/display terminal, Teletype, etc.)

Speed of operation

Slow speed devices such as Teletype are driven by the stabiUzed RC oscillator clock module (M452).
Higher speed requires a high stability of the selected frequency; therefore, a crystal-controlled clock
module (M405) is used. The frequency of operation must be specified for each separate device.
Voltage level of inputs

Typically,

DEC equipment will interface directly with EI A RS-232-B industry standard devices or the

standard 0, 20

mA Teletype current loop (sometimes referred to as 0, +3V logic level). As the console

Teletype is typical of the three different controls discussed in this section, it will be described in detail.

The differences which are noteworthy in the PT08 and DPI 2 will be further discussed.

PDP-12 Console Teletype Control - The Teletype control uses the standard M706 receiver, M707
and M452 clock modules for basic logic. It will drive any one of the previously discussed Teletype
requires a slight adjustment of the clock to operate at 15 characters per second).
KSR-37
(the
models
6.1.5.1

transmitter,

Serial information read or written by the Teletype unit is assembled or disassembled

parallel transfer to the accumulator (AC).

The control

also provides the

by the Teletype control for

program flags that cause a program

interrupt or an instruction skip depending on the availability of the Teletype and the processor.

all

programmed operation, the Teletype unit and control are considered as a Teletype in (TTI) for input data

from the keyboard or the perforated-tape reader, and as a Teletype out (TTO) for computer output information to
be printed and/or punched on tape. Therefore, two device select codes are used. Select code 03 initiates operations
associated

with the

keyboard/reader

(TTI)

and

select

code 04 performs operations associated with the

teleprinter/punch (TTO). Parallel input and output functions are performed by corresponding lOT pulses produced

by the two device selectors. Pulses produced by the lOPl pulse trigger skip gates; pulses produced by the I0P2
pulse clear the control flags and/or the accumulator; and pulses produced by I0P4 initiate data transfers to and

from the control.

6.1.5.2

Keyboard Reader- The keyboard and tape reader control contains an 8-bit shift register (TTI) which

assembles and holds the code for the last character struck on the keyboard or read from the tape. Teletype
characters from the keyboard/reader are received serially by register TTI. The code of a Teletype character is

loaded into the TTI so that spaces correspond to binary zeros and holes (marks) correspond to binary ones. Upon
program command, the contents of the TTI are transferred in parallel to the accumulator.

When a Teletype character starts to enter the TTI, the control de-energizes a relay in the Teletype unit to release
the tape feed latch. When released, the latch mechanism stops tape motion only when a complete character has
been sensed, and before sensing of the next character is started. A keyboard is set when an 8-bit computer
character has been assembled in the TTI from a Teletype character. The program must sense the condition of this
flag with a KSF instruction, and, if the flag is set, issue a KRB instruction which clears the AC, clears the keyboard
flag, transfers

the contents of the TTI into the AC, and enables advance of the tape feed mechanism. Program

interrupt can be controlled by the LINC mode instruction ESF (0004) (refer to Paragraph 3.3.16). This instruction
either enables or inhibits interrupts when either the TTI or

6.1 .5.3

TTO flag is set.

Instructions - Instructions for use in supplying data to the computer from the Teletype are as follows:

6-5

KSF

Skip on Keyboard Flag

6031

Octal code:

Event time:

Execution time:

4.25 /is

Operation:

keyboard flag is set, the contents of the PC are incremented by one so that the next

If the

sequential instruction is skipped.
If Keyboard Flag =

Symbol:

KCC

1 ,

then PC + 1 ^ PC

Clear Keyboard Flag

6032

Octal code:

Event time:

Execution time:

4.25 jus

Operation:

The AC and the keyboard flag are cleared. If there is tape in the reader and the reader is on,
the character over the read head is loaded into the TTI and the tape advanced one frame. If
there is no tape or the reader is off (STOP or FREE) the character struck on the keyboard is
assembled into the TTI. In either case, when the character is completely assembled in the TTI,
the hardware sets the keyboard flag.

O^AC

Symbol:

-^ Keyboard flag allowing the hardware to cause:

Keyboard/Tape Character -^ TTI
I

-> Keyboard flag (approximately

00 ms after issuing the instruction)

KRS R ead Key board Buffer Sta tic
6034

Octal code:

Event time:

Execution time:

4.25 /is

Operation:

The contents of the TTI are transferred into AC4.1 1 This is a static command in that neither
the AC nor the keyboard flag is cleared. KRS can be microprogrammed with KCC.
TTI V AC4-1 j -AC4-1
-> Keyboard Flag
.

Symbol:

NOTE
The KRS instruction has been redefined in a later version of the PDP- 1 2 to permit
clearing of the TTI flag without advancing the paper tape and assembling the next
character.

KRB

R ead Key board Buffer Dynamic

Octal code:

6036

Event time:

2,3

Execution Time:

4.25 /IS

Operation:

This instruction combines the functions of the KCC and KRS. The AC and keyboard flag are

both cleared and the contents of the TTI are transferred into AC4.1 ^. Clearing the keyboard
flag

allows the hardware to begin assembling the next input character into the

described for KCC).

causes the flag to be set, indicating that TTI again has a character ready for transfer.

Symbol:

O^AC

C(TTI)VC(AC4-n)^AC4.ii

-> Keyboard Flag allowing the hardware to cause:

Tape Reader to advance 1 character
Keyboard/Tape Character -^ TTI
1 -* Keyboard Flag when down (approximately
1 00 ms after issuing instruction)

6-6

TTI

(as

When the character is completely assembled in the TTI, the hardware

KST Key Struck (LINC mode)
Form:

KST I

Octal code:

0415 + 201

Execution time:

1.6)lis

Condition:

A key has been struck on the ASR-33 keyboard, the character code has been assembled in the
Teletype buffer, and the Keyboard flag is raised. (The flag is cleared when the character is read
into the AC.)

The program example shown below will read 1 character from the keyboard.
*200

/CLEAR KEYBOARD FLAG

KCC

INPUT,

JMS LISN

DCA STORE
HLT
/SKIP ON KEYBOARD FLAG

LISN,

KSF
JMP.-l

/READ KEYBOARD BUFFER

KRB
JMP I LISN
STORE,

The main program begins with KCC. In general, the main program should begin by clearing the flags of all devices
to be used later in the program. If the above program is started at location 200, it will proceed to the KSF, JMP.—
loop, and stay in this loop endlessly until a key on the Teletype unit is pressed or a paper tape is loaded into the
reader. When the ASCII code for the character is assembled in the keyboard/reader buffer register, the flag will be
set to a 1 and the program will skip out of the loop. The contents of the buffer will be transferred into the
accumulator, and the buffer and flag will be cleared.
6.1.5.4 Teleprinter/Punch — On program

command, a character is transferred from the accumulator (AC) to the

output shift register (TTO) for transmission to the teleprinter/punch unit. The teleprinter control generates the
start space, shifts the eight character bits serially into the printer selector magnets of the teletype unit,

and then

generates two stop marks. Bit transfer rate from the TTO to the teleprinter/punch unit is at the normal Teletype
rate of 1 10 baud.
last bit

A character transfer requires 100 milliseconds for completion. The teleprinter flag is set when the

of the character code is sent to the teleprinter/punch, indicating that the TTO is ready to receive a new

character from the AC. The flag activates either the program interrupt synchronization element or the instruction
skip element. When using instruction skip, the program checks the flag by means of TSF instruction. If the flag is

the program must issue a TLS instruction which clears the flag and sends a new character from the AC to the
TTO. AC to TTO transfer time is short compared to the print/punch time, so the program must wait for the flag to
set,

set before issuing another TLS. Instructions for use in outputting data to the teleprinter /punch are as follows:

TSF

Skip on Teleprinter Flag

Octal code:

6041

Event time:

Execution time:

4.25 /xs

Operation'

the teleprinter flag is set, the contents of the PC are incremented by one so that the next

sequential instruction is skipped.

Symbol:

If Teleprinter Flag =

1 ,

then PC + 1

^ PC

6-7

TCF

Clear Teleprinter Flag

Octal code:

6042

Event time:

Execution time:

4.25 /xs

Operation:

The teleprinter flag is cleared. Can be microprogrammed with TPC.
-^ Teleprinter Flag

Symbol:

TPC

Load Teleprinter and Print

Octal Code:

6044

Event time:

Execution time:

4.25 /IS

Operation:

AC4-1 1 are parallel transferred to the TTO, then the hardware starts shifting the character out
to the printer/punch unit. When the transfer is complete (approximately 1 00 ns), the TTO flag
is set.

C(AC4.i 1 ) ^ TTO causing:
C(TTO) -* printed and (if punch is on) punched

Symbol:

TLS

Load Teleprinter Sequence

Octal Code:

6046

Event time:

2,3

Execution time:

4.25 MS

Operation:

This is an instruction that combines

TCF and TPC. The teleprinter flag is cleared, then the

contents of AC4-1 j are parallel transferred to the TTO, where the hardware serially shifts the
character-bits out to the printer/punch unit. When the printer/punch has finished outputting
the character, the hardware sets the teleprinter flag. The whole operation, from the time TLS
clears the flag and

TPC starts character transfer until the time the hardware finishes with the

character and again sets the flag, requires 1 00 ms.

Symbol:

->•

Teleprinter flag

C(AC4-n ) ^ TTO causing:
C(TTO) -^ Printed and (if punch on) punched
1 -> Teleprinter flag when done (approximately 1 00 ns after issuing instruction)
Shown below are several programming examples illustrating the use of the TTO control.
TYPE,

TLS
TSF

/LOAD TTO FROM AC AND PRINT/PUNCH

JMP.-l

/TEST FLAG SKIP IF = 1
/JMP BACK & TEST FLAG AGAIN AND AGAIN

CLA

/CLEAR CHARACTER FROM AC

JMP I TYPE

/EXIT TO MAIN PROGRAM

By rearranging this subroutine, the 100 ms spent waiting for the character to be output and the flag to be set is
used to continue the main program, making more efficient use of program time.

6-8

TYPE,

/TEST FLAG TO SEE IF TELEPRINTER FREE, SKIP IF NOT
/WAIT TILL IT IS BY TESTING AGAIN AND AGAIN

TSF
JMP.-l

TLS

CLA CLL
JMP I TYPE

/OUTPUT CHARACTER
/CLEAR CHARACTER FROM AC
/EXIT TO CONTINUE PROGRAM

This subroutine tests the flag first, and waits only if a previous character is still being output. It clears the AC and
exits

immediately after sending the character to the TTO, and continues to run the user's program instead of

waiting while the teleprinter (a much slower device)
initialize

off typing/punching the last character.

The user must

the control by setting the teleprinter flag to a one. Otherwise, the subroutine will "hang-up" the first time

through (in the TSF, JMP .-1 loop). The initialization can be accomplished by issuing a TLS or TPC instruction at
the beginning of the mainline program.

Format Routines
Input and output routines are very often written in the form of subroutines, like the TYPE subroutine in the
previous example. The example below is a carriage return/line feed subroutine that calls the TYPE subroutine to

execute a carriage return and line feed on the printer, thus advancing to a new line for the printing of information.
Carriage Return/ Line Feed Subroutine:

CRLF,

TADK212
JMS TYPE

TADK215
JMS TYPE
JMP I CRLF
212
215

K212,
K215,

/ASCII FOR CARRIAGE RETURN
/ASCII CODE FOR A LINE FEED

TYPE,

TSF
JMP .-1
TLS

CLA CLL
JMP I TYPE

Subroutines similar to the one above could be written to tab space the carriage a given number of spaces, or to ring
the bell of Teletype Model 33 ASR by using the respective codes for these nonprinting control characters.

Type DP12-A (prewired) - This internal option provides an interface which is
programmed similar to the standard console Teletype. The device select codes are lOTs 40 and 41. Interrupts
caused by either the transmitter or receiver flags can be disabled by the LINC mode instruction ESF (refer to
6.1.5.5 Single Teletype Control,

Paragraph 3.3.16).

6.1.5.6 Dataphone Control, Type DP12-B - This option is a modification of the DP12-A, which permits
communication to most standard Dataphone sets. An extra crystal-controlled clock permits the user to specify a

baud rate from 110 to lOOK baud in order to provide the necessary frequency stability required at higher baud
the option is suppUed with a 25-ft cable. Type BCOlA-25, which will connect (via a 25-pin
connector) to a Dataphone set. This cable has a card connector (M850), which converts the EIA standard RS-232-B
rates. In addition,

signals to

DEC logic levels of

and +3V

6-9

6.1.5.7 Single and Dual

TTY Control Type PT08 - The PT08 is a serial-to-parallel, parallel-to-serial converter

which provides full-duplex communication between an asynchronous channel and a PDP-12 computer. Two basic
configurations are offered: PT08-B (one full-duplex channel) and PT08-C (two full-duplex channels). Systems may
be expanded up to five duplex channels by stacking PT08 units.

The PT08-B and C are designed to supply transmit and receive keying current that is intended for use with 20 mA,
dc-keyed devices. Digital Equipment Corporation's Model 33 or 35 teleprinter units have been modified to be
compatible with the PT08.

Devices equivalent to the modified teleprinter units are also compatible with the PT08.

The PT08-B and C are negative bus options (0, -3V) and, therefore,
converter must be used when connecting the PT08 to the PDP-12.

DW08-A negative-to-positive I/O bus

The PT08-F option provides EI A standard RS-232-B level conversion as well as a 25-ft cable designed to connect to
a Dataphone set. Another option, the PT08-X, can be installed in any channel for customer selection of character
format and speed. With the PT08-F and PT08-X options combined, the bit rate can be increased to lOOK baud for
driving

medium-to-high-speed

asynchronous

modems.

This

combination

can be used

for

an economical

intercomputer communication channel, or for interfacing to special equipment with unique asynchronous speeds

and character formats.
Specifications

Performance specifications are summarized in Table 6-1.

Table 6-1.

PT08 Specifications
Specifications

10 baud is standard; up to lOOK (software limited) with PT08-X option.

Speed

Character Format

Standard:

1-unit start; 8 character bits; 2-unit stop.

PT08-X Option:

5 or 8 character bits, 1- or 1.5-unit stop element at user's request.

Operating Mode

Full duplex.

Interface

Standard:

Supplies transmit and receive keying current that is intended for

use with 20 mA, dc-keyed devices.

PT08-F Options: Provides interface that conforms to EI A RS-232-B devices.
Transmission Distance

1500-ft maximum (environment dependent) for local terminals.

EIA interface transmission distance is limited only by characteristics of modem and
associated communication facility.

A 25-ft cable to the modem is supplied.

Figure 6-3 illustrates the various PT08 equipment configurations for both the standard system expansion and
interface provisions.

Programming

lOT instructions test for character-ready conditions and transfer assembled characters to and from the computer's
accumulator. The same basic commands are used for all channels, with individual channels assigned different device
selection codes. For PT08 channel 1, the devices codes are 40 and 41, etc. (See Table 6-2 for complete listings of
PT08 device codes.) It will be noted that channel 1 lOTs are the same as assigned to the internal prewired option
DP12-A or B. When channel 1 is implemented, the lOT for channel must be revised to an unused device select
code. This normally would be one of the device codes 30 through 37. The basic mnemonic plus the PT-number
1

designator identifies the mnemonic for the specific channel.

6-10

'W070

-I/O
PDP-12

(+)

BUS

DW08-A

PT08B

ORG

»i LOCAL

I
I

TERMINAL

I
I
I

(TELEPRINTER)
(UP TO 1500 FEET

MAXIMUM)
110

PT08F

PT08B

ORG

BAUD ^fpia RS~232B
[TYPE MODEM

MAXIMUM OF 5 FULL
>-

[(DATA PHONE, ETC)

DUPLEX LINES (20mA

DC-KEYING) OF

SERIAL-START-STOPCODE

PT08B

CONTINUATION OF
I/O BUS TO OTHER
PERIPHERALS

ORG

PTOSTI jPTOBF

Figure 6-3.

UP TO

fHToTT-'sFEED

19?.^

ASYNCHRONOUS
MODEM

BAUD

^lJBELL_202D_,ETC)j

PT08 Equipment Configurations

Table 6-2. PT08 Device Codes

Channel Number

Basic

Mnemonic

KSF

KCC
KRS

KRB
TSF

TCF
TPC
TLS

6421

6441

6461

6111

6301

KSFPT2

KSFPT3

KSFPT4

KSFPT5

KSFPTl

6422

6442

6462

6112

6302

KCCPT2

KCCPT3

KCCPT4

KCCPT5

KCCPTl

6424

6444

6464

6114

6304

KRSPT2

KRSPT3

KRSPT4

KRSPT5

KRSPTl

6426

6446

6466

6116

6306

KRBPT2

KRBPT3

KRBPT4

KRBPT5

KRBPTl

6431

6451

6471

6121

6311

TSFPT2

TSFPT3

TSFPT4

TSFPT5

TSFPTl

6432

6452

6472

6122

6312

TCFPT2

TCFPT3

TCFPT4

TCFPT5

TCFPTl

6434

6454

6474

6124

6314

TPCPT2

TPCPT3

TPCPT4

TPCPT5

TPCPTl

6436

6456

6476

6126

6316

TLSPT2

TLSPT3

TLSPT4

TLSPT5

TLSPTl

Instructions

The following instructions are used with the PT08:

KSF

Skip on Receive Flag

Event time:

Indicators:

lOT, Fetch, Pause

Execution time:

4.25 [is

Operation:

Causes the program to skip the next instruction if the receive flag is set, indicating that an

assembled character is ready.

Symbol:

If receive flag =

1 ,

PC + 1 -^ PC

6-11

KCC

Clear Receive Flag and A C

Event time:

Indicators:

lOT, Fetch, Pause

Execution time:

4.25 ms

Operation:

Clears the accumulator and the receive flag.

Symbol:

-> AC,

^ RF

KRS Read Receive Buffer (Static)
Event time:

Indicators:

lOT, Fetch, Pause

Execution time:

4.25 //s

Operation

Transfers an assembled character from the receive buffer to AC4-, ^

Does not reset AC or

receive flag.

Symbol:

KRB

RB ^ AC4-1

Read Receive Buffer (Dynamic)

Event time:

2, 3

Indicators:

lOT, Fetch Pause

Execution time:

4.25 /zs

Operation:

Performs the functions of KCC and KRS together, so that the receive flag and AC are cleared
before data is transferred from the receive buffer to the AC.

Symbol:

0->AC, O^RF

RB^AC4-ii
TSF

Skip on Transmit Flag

Event time:

Indicators:

JOT, Fetch, Pause

Execution time:

4.25 /us

Operation:

Causes the program to skip the next instruction if the transmit flag is set, indicating that the
transmit flag = 1, PC + 1 -> PC

TCF

Clear Transmit Flag

Event time:

Indicators:

lOT, Fetch, Pause

Execution time:

4.25 /us

Operation:

Resets the transmit flag.

Symbol:

0->TF

TPC

Load Transmit Character

Event time:

Indicators:

lOT, Fetch, Pause

Execution time:

4.25 /us

Operation:

Loads the transmit buffer from AC4-1

Symbol:

AC4-1 j -^ TB

6-12

and initiates transmission of a character.

TLS

Load Transmit Sequence

Event time:

2, 3

Indicators:

lOT, Fetch, Pause

Execution time:

4.25 yjs

Operation:

Performs the functions of TCP and TPC together.

^ TF

Symbol:

AC4.1 1 -^ TB

Maximum Data Rates
In transmitting the PT08 provides a full character cycle for the program to deliver new data. In receiving, one bit

required to read in necessary data. However, for maximum data transfer rates, the time at which data
transfer can occur is limited to an aperture equal to the stop bit time plus half a bit time. This response time is

time

measured from the beginning of a stop bit (the time at which the transmit or receive flag is reset), and the midpoint
of the next character's start bit. If the program fails to respond within this time, a character is lost. Timing is
illustrated in Figure 6-4.

TIME
(1/BAUD RATE)
BIT

DATA

START

STOP

BITS

STOP BIT TIME
(BIT TIME X STOP UNITS)

START

DATA BITS

CHARACTER
TIMING

RECEIVE

TRANSMIT OR
FLAG RESET

LAST TIME TO
RESPOND TO FLAG
81-0079

Figure 6-4.

PT08 Program Response Time

For example, at 1 10 baud (9.09 ms bit time), response time is:
Stop bit time + half a data bit time

= 2x9.09 + 9.09/2
= 22.725 ms

Note that the number of bits per character need not be considered.
6.1.5.8 Multiple Teletype Control, Type DC02-E (see Table 6-3) - The DC02-E option, which is prewired in the

BA12 Peripheral Expander, allows the user to add up to four serial-to-parallel, parallel-to-serial asynchronous data
channels. It consists of a DC02-E multiple station control and from one to four DC02-D station interfaces (each

A Type BCOl A-25 cable is available that will connect to most Dataphones via a 25-pin connector and
+ 3 volts.
will convert EIA standard RS-232-B signals to DEC logic levels of
full-duplex).

The control will handle teletypes at their normal baud rate of 110. In addition, higher speed devices may be
operated by using crystal clocks. In this case the baud rate must be specified by the user. Up to two clocks may be
used and may be connected by a jumper module in any combination to control the stations' transmitters and
receivers.

6-13

Table 6-3.

DC02-E Specifications

Characteristics

Specifications

10 baud is standard; up to lOOK baud crystal controlled.

Speed

Character Format

Standard:

1-unit start; 8 character bits; 2-unit stop.

Option:

5 or 8 character bits 1- or 1.5-unit stop element at user's request.

Operating Mode

Full duplex.

Interface

Standard:

Supplies transmit and receiver keying current that is intended for

use with 20 mA, dc-keyed devices.

1500 ft maximum (environment dependent) EIA interface transmission distance is

Transmission Distance

limited only by characteristics of modem and associated communication faciUty. A
25-ft cable to the modem is supplied. (BCOlA-25).

DC02-E Control Instructions
The following instructions are used with the DC02E control:

MTPF

Multiple Teleprinter Flag

Octal code:

6113

Event time:

Execution time:

4.25 jus

Operation:

Transfer status of teleprinter flags to AC 0-3

Symbol:

Teleprinter flags -^ AC0-3

•

0-^AC4-ii.

MINT

Multiple Interrupt

Octal code:

6115

Event time:

Execution time:

4.25 /us

Operation:

Interrupt on if ACj j

Symbol:

ACj

MTON

is set

(interrupt request if any flags).

-^ Interrupt Enable

Multiple Station Select

Octal code:

6117

Event time

1 ,

Execution time:

4.25 /us

Operation:

Transfer AC0-3 to selection register (select stations when bit is set).

Symbol:

AC0-3 ^ SR

MTKF

2, 3

Multiple Keyboard Flag

Octal code:

6123

Event time:

Execution time:

4.25 /us

Operation:

Transfer status of keyboard flags to AC0-3

Symbol:

KF^ACo-3

^ AC4-1

6-14

MINS

Multiple In terrup t and Skip

Octal code:

6125

Event time:

Execution time:

4.25 jus

Operation:

Skip if the interrupt request is active (if interrupt is on and any flag is raised).

Symbol:

If interrupt request is active,

PC +

-*•

MTRS Read Station Select Status
Octal code:

6127

Event time:

I, 2,

Execution time:

4.25 jus

Operation:

Transfer the status of the selection register to AC0-3

Symbol:

SR^ACo-3
0^AC4.ii

DC02-D Instructions
Decoder instructions for the DC02-D are in two basic groups: receiver and transmitter. The receiver instructions are
6111, 6112, 6114, and 6116; the transmitter instructions are 6121, 6122, 6124, and 6126. The "Station Select"
flip-flop is gated with each device select code; therefore, these

lOTs are effective only when a particular station is

selected.

MKSF

Skip On Keyboard Flag

Octal code:

6111

Event time:

Execution time:

4.25 )us

Operation:

Skip if the selected keyboard flag is set.

Symbol:

*MKCC

Clear Keyboard Flags

Octal code:

KF =

1 ,

PC + 1 ^ PC

6112

Event time

Execution time:

4.25 /us

Operation:

Clear the keyboard flag of the selected station; clear AC. If the paper tape reader is on, the

tape will advance

character and the receiver flag will be set approximately 100 ns after

issuing the instruction.

^ KF, ^ RF, ^ AC

Symbol

MKRS

Read Keyboard Register Static

Octal code:

6114

Event time:

Execution time:

4.25 //s

Operation:

Transfer the keyboard register contents to AC4-1 1

Symbol:

ACo-j , V KR to ACo-^ ^

On some systems a logic revision has been added which inhibits tape advance and consequent setting of the receiver flag.

6-15

MKRB

Load Keyboard Sequence

Octal code:

6116

Event time:

2,3

Execution time:

4.25 /us

Operation:

Clear the keyboard and reader

flags,

clear

AC; transfer the keyboard register contents to

AC4-, J (MKCC and MKRS combined).
->

Symbol:

^ RF
^ AC
KR ^ AC4.11
MTSF

Skip on Teleprinter Flag

Octal code:

6121

Event time:

Execution time:

4.25 /us

Operation:

Skip if the selected teleprinter flag is set.

Symbol:

MTCF

TF = 1, PC +

^ PC

Clear Teleprinter Flag

Octal code:

6122

Event time:

Execution time:

4.25 /us

Operation:

Clear the teleprinter flag of the selected keyboard station.

Symbol:

O^TF

MTPC

Multiple Load Teleprin ter Register and Prin

Octal code:

6124

Event time:

Execution time:

4.25 11^

Operation:

Load AC4-1 ^ into the teleprinted register (begin print/punch).

Symbol:

AC4.1

^TR

MTLS Load Teleprinter Sequence
Octal code:

6126

Event time:

Execution time:

4.25 /lcs

Operation:

Clear the teleprinter flag and load AC4-1 1 into the teleprinter register

(MTCF and MTPC

combined).

Symbol:

O^TF
AC4-1

^ TR

Multiple Teletype Control, Type DC02-F
This control is similar to the DC02-E in operation and design. It consists of a double row of logic (10-1/2" x 19"

nominal rack space) complete with power supplies. This unit will handle up to eight stations. The DC02-F is
designed so that four controls may be connected together in such a way that 32 stations total may be operated. A

jumper module is used to enable selected signals when the system is expanded.
As in the four-station control DC02-E, the high order bits of the AC are used to select a station. AC0-7 are used to
are used to select any one of up to four DC02-F controls. Up to
select the stations within one control and ACg-j
1

6-16

three separate clocks

may be specified. In addition, two frequency divide registers are available with outputs at
The resultant timing pulses may be connected in any combination with jumper

divide-by-8 and divide- by- 128.

modules to provide timing for the transmitter and receiver modules of the stations.

The specifications for this control are the same as those of the DC02-E. The program instructions are likewise
identical except for the following.

MTPF

Multiple Teleprinter Flag

Octal code:

6113

Event time:

Execution time:

4.25 /xs

Operation:

Transfer status of teleprinter flags AC0-7

Symbol:

Teleprinter flags ->-ACo -7

ACg-i 1 selects one of four controls.

O^ACg-ii

MTKF

Multiple Keyboard Flag

Octal code:

6123

Event time:

Execution time:

4.25 jws

Operation:

Transfer status of keyboard flags to ACo_7

Symbol:

KF^ACo.7

O^ACg.ii

MTON

Multiple Teleprinter

Octal code:

6117

Event Time:

1, 2,

Execution time:

4.25jLts

Operation:

Transfer AC0.7 to selection register select stations when bits are set. ACg.i 1 selects one of

four controls.

AC0-7 ^ SR

Symbol:

O^ACg.u
MINS

Multiple Interrupt and SKP

Octal code:

6125

Execution time:

4.25 jlxs

Operation:

Skip if the interrupt request is active (i.e.,

interrupt is on and any flag is raised) ACg-i ^

select one of four controls.

Symbol:

O^ACg-n

MTRS

Multiple Teleprinter Read Status

Octal code:

6127

Event time:

1, 2,

Execution time:

4.25 ;us

Operation:

Transfer the status of the selection register to AC0-7. ACg-i 1 selects one of four controls.

Transfer status of interrupt enable flip-flop to ACi 1

Symbol:

If ACj j

= 1, the interrupt enable is set.

SR ^ AC0-7
Interrupt Enable -* ACi j

O^ACg-'io

6-17

6.2

6.2.1

REAL TIME CLOCKS
Real Time Interface, Type KW12-A

The KW12-A (see Figures 6-5 and 6-6) is a prewired PDP-12 option with an input control panel, which mounts
behind the vertical door on the left front of the PDP-12. The Real Time Interface can be used to synchronize the
central processor to external events, count external events, measure intervals of time between events, or provide
program interrupts at programmable intervals from 2.5
operations can be done simultaneously.

Figure 6-5

jlis

to over

40 seconds. Some of the above mentioned

KW 2-A Real Time Interface
1

Time Base
The programmable time base provides count pulses to the counter register at any of the following rates derived
from a 400 kHz crystal clock:
400 kHz

100 kHz

100

10 kHz

6-18

kHz
Hz

Input channel

may be used to enable an external source to drive the counter. This external source may be

switch-selected to be either the

power line waveform or an

actual signal

from a laboratory instrument. The

programmable selection of the rate is accomplished with the three rate-bits of the clock control register.
Input Synchronizers

Three input channels are used to convert external events into a synchronized control and status signal for the clock.
Each input channel consists of an input Sclimitt trigger with pulse generator, five flip-flops, and associated control
gating.

The Schmitt trigger and pulse generator converts the preselected voltage threshold crossing by an external

signal into a single event (pulse). This Schmitt trigger has level and slope selection controls available on the front

panel.

They provide selection of any threshold between ±6V and either positive or negative-going slope. The

Schmitt trigger has a hysteresis of 0.3V.

TO AC (12 BITS)

CLOCK BUFFER PRESET REG (12 BITS)
10 BUS

10 AND MODE

(12 BITS)

CONTROL

FROM AC (12 BITS)

START A- D CONVERTER

PROGRAM
INTERRUPT
AND SKIP

OVERFLOW
INPUT

COUNT

CLOCK COUNTER (12 BITS)

LOGIC

INPUT
1

CLEAR
CLOCK

SYNC

(12 BITS)

INPUT
2

SYNC
RATE CONTROL

INPUT
3

SYNC

CRYSTAL

400 kHz

r-4

-10

-rlO

100kHz

10kHz

tkHz

MO
100

Hz
12-ono

Figure 6-6.

KWl 2- A Organization

The five Input Circuits flip-flops are: INPUT ENABLE, INPUT, PRE-EVENT, EVENT, and ENABLE EVENT

INTERRUPT (see Figure 6-7). Figure 6-8 shows a basic timing of the Input Synchronizer.

6-19

Not shown in Figure 6-7

the logic which clears the

EVENT and PRE-EVENT flip-flops when the CLSA

instruction is given. This logic ensures that events occurring during the execution of the present CLSA instruction
are indicated when the next CLSA instruction is given.

Input Enable Flip-Flop - Gates on and off input signals to the clock. It is set and cleared under program control.

Input Flip-Flop - Set by an external signal from the Schmitt trigger input or under program control with the

CLLR instruction. The INPUT flip-flop provides synchronization between external timing and internal clock
timing.

Pre-Event Flip-Flop - Strobed into the EVENT flip-flop by the strobe

signal.

This clears the INPUT flip-flop if

EVENT is clear.
Event Flip-Flop — Loaded with the PRE-EVENT flip-flop on the next strobe 1 and set to a 1 by the second strobe
1

following the setting of the INPUT flip-flop. Subsequent to EVENT being loaded, PRE-EVENT is cleared.

Event Enable Interrupt Flip-Flop — Permits external events to cause program interrupts. It is set and cleared by the

CLEN instruction.
The occurrence of strobe 2 with EVENT (0) and PRE-EVENT ( 1 ) is the actual single event used by other parts of
the clock logic such as counting and transfers from counter to buffer register.
The status of the EVENT and PRE-EVENT flip-flops is loaded into the AC under program control. When this
transfer occurs, the corresponding INPUT, PRE-EVENT, and EVENT flip-flops are cleared.
If a second

input occurs before the EVENT flip-flop is cleared, then both the PRE-EVENT and EVENT flip-flops

will remain set, indicating an error.

SYNc_-_-r\
STROBE
1A

^ ^^
l-^

Figure 6-7. SimpUfied Input Synchronizer Logic Diagram

6-20

SYNC.

STROBE

innr^ nnnm

SYNC
STROBE

-f

T~mf

COUNTER

100ns

TO
600ns BUFFER
HERE
I

INPUT
FLIP-FLOP

SYNC
STROBE 2

COUNTER
INCREMENTED
HERE —*

PRE-EVENT
FLIP-FLOP
INPUT

FLIP-FLOP

EVENT
FLIP-FLOP
Timing diagram for Channel 1 only

PRE-EVENT
FLIP-FLOP

rate field equals
is

enabled

the

63 and ChanneM input

EVENT
FLIP-FLOP

CP INTERRUPT
HERE

~ V
NORMAL

V
ERROR

NOTES
1

PRE-EVENT Is reset.
EVENT was olreody set,
PRE-EVENT remains set as an error

may be used to increment the

Normally
If

however

counter. For this cose the
timing diagram is shown below.

flog; indicating that more than one
input occured between clearing of the

EVENT flip-flop.
2. EVENT is cleared only by the CPU using
the

6135 (CLSA) instruction

following exception

Inputs

Error indication that 6135
(CLSA) instruction was not
issued soon enough followin g
an

EVENT,

with the
to

Channel

Figure 6-8.

KW 12- A Timing Diagram

Counter Register

The counter register is a 1 2-bit counter that is loaded from the buffer-preset register or can be transferred into the
buffer-preset register.

The counter may be used to count events, measure intervals of time between events, or provide processor interrupts
at program selected intervals from 2.5 jus to over 40 seconds.

OVERFLOW Flip-Flop - The OVERFLOW flip-flop is set by the most significant bit of the counter register going
from 1 to 0.
Buffer-Preset Register — Used to buffer the current counr in the clock register at the occurrence of an event when

operating with

Mode 1(1). With Mode 1 (0) and Mode 2(1), the buffer-preset register holds the number to be

transferred into the counter when overflow occurs. The buffer-preset register can be loaded into the AC or the AC

can be transferred into the buffer-preset register.

6.2.1.1

Use of Interface with A-D - With Mode

(1),

the occurrence of overflow

used to start an

A-D

conversion if the A-D is in the Fast Sample Mode. With Clock Mode 0(1), the A-D is triggered only by the clock.

When a SAM instruction is given, the result of the last conversion is transferred to the AC, and a new analog
channel is selected for the next conversion to be performed when the clock overflows. If the SAM instruction is
given while a conversion triggered by the clock

in progress, the processor waits in timestate

TS5 until the

conversion is complete.

6-21

6.2 A. 2

KW12-A Input Panel - The input panel for the clock is located behind the door on the left side of the

front of the PDP-12. External signals (from up to three instrument/sources) are connected to the Input jacks on the
front panel (see Figure 6-5) via standard 3-conductor telephone plugs. Each Input and Output jack is wired in
parallel

permit convenient connection of the external input signals to the

Analog-to-Digital Converter.

KW12-A and, if desired, the

The input is differential, ±5V range, input resistance greater than 10,000 ohms, and

protected against inputs up to ±50V. A level control and a slope control are associated with each input. The level
control selects the threshold voltage at which the trigger pulse is generated. The slope determines the polarity of
the input signal causing a trigger pulse. The trigger pulse sets the associated input flip-flop of the clock if that input

channel is enabled.

6.2.1.3

KW12-A Real Time Interface Instructions - The KW12-A is controlled by PDP-12 lOT instructions. These

instructions can be used from either 8 or LINC mode. Execution time for the lOTs is 4.25 jus when in 8 mode and

5.9 )us when in LINC mode (using lOB).

CLSK

Skip On Clock Interrupt

Octal code:

6131

Event time:

Execution time:

4.25 /xs

Operation:

Skip if clock interrupt condition exists. The interrupt conditions are as follows:

CLLR

Enable Event 1 Interrupt (1) and Event 1(1).

Enable Event 2 Interrupt (1) and Event 2(1).

Enable Event 3 Interrupt (1) and Event 3(1).

Enable Overflow Interrupt (1) and Overflow (1).

Load Clock Control Register

Octal code:

6132

Event tjme:

Execution time:

4.25 /xs

Operation:

The contents of the AC are transferred to the clock control register. Three bits are used to
provide simulated data input to each of the three Event input channels. The AC is unchanged.

Function

Bit

00
01

Mode Control Register Bit
Mode Control Register Bit 1
Mode Control Register Bit 2

Not used

6-22

Count Rate Register Bit
Count Rate Register Bit 1
Count Rate Register Bit 2

Simulate Input to Channel 1

Not used

Simulate Input to Channel 2

Not used

Simulate Input to Channel 3

The rate of the counter register input count pulses is determined by the contents of the count rate register.
int Rate

Frequency of

agister

Count Pulses

000

Stop

001

400 kHz

010

100 kHz

oil

10 kHz

100
101

IkHz
100 Hz

110

Rate of Input Channel 1

111

Stop

NOTE
When Channel

used as the time base for the counter, the Event

automatically cleared and Channel

flag

Interrupt Enable would normally be left off.

Also the clock counter is advanced one count each time an 10 PRESET is performed
either manually or under program control.

The contents of the mode control register determine the method by which the clock system operates.
Program Example

The following program rings the teleprinter bell once for every 10 inputs (60 Hz) on external channel three. If the
source knob is turned to line frequency the Teletype bell will ring once/per second on computers connected to 60
Hz power lines.

PMODE
CLA

BEGIN,

CLLR
CLEN
TAD K74
CIA

CLAB
CLA
TAD KOI 00
CLLR
CLSA
CLA
TAD K0320
CLEN
PUT CHAN

LOOP,

/NO. OF COUNTS

/FORM 25 COMP
/LOAD PRESET REG
/CLEAR AC
/SETAC05=1

/GENERATE CLEAR COUNTER
/CLEAR STATUS AND POSSIBLE OVERFLOW
/CLEAR AC
/LOAD AC
/LOAD BUFFER INTO COUNTER, ENABLE INTERRUPT ON OVERFLOW,
AND ENABLE IN

CLA
TAD K6 100
CLLR

/CLEAR AC
/LOAD AC
/START CLOCK BY ENABLING RATE

CLSK
JMP LOOP
CLSA

/SKIP ON CLOCK FLAG

CLA
TAD K207
TLS
JMP LOOP
K74,

/PSEUDO TO LAP6 DIAL ASSEMBLER
/CLEAR AC
/CLEAR ALL MODES
/CLEAR ENABLES

KOI 00,

100

K0320,

320

K6100,
K207,

207

AVAIT

/CLEAR STATUS
/CLEAR AC
/LOAD AC
/RING TELEPRINTER BELL

/RETURN TO WAIT LOOP
/CONSTANTS

6100

6-23

Mode Control Register
000

Free-run

Counter runs selected rate. Overflow occurs every 4096 counts. The overflow flag remains
set until cleared with

CLSA instruction,

Preset Time

001

Counter runs

selected

rate.

When

overflow occurs, the contents of the Clock

Buffer-Preset register are transferred automatically to the Counter which continues. The

Overflow flag remains set until cleared with a CLSA instruction. When Mode is changed
from XOO to XOl, the clock counter is zeroed.

010

Time Base (measures intervals between events)
Counter runs at selected rate. On the occurrence of an Input Event, the contents of the
counter are transferred automatically to the Buffer Preset

and the counter

continues to count.

Time Base (measures intervals between events)

This is identical to Mode 10, except that the Clock Counter register is cleared after its

contents have been transferred to the Buffer Preset register on Event 3. Events 1 and 2

remain only to cause transfer from the clock counter to the Buffer Preset register.

101

When Mode bit
is set to a I, the occurrence of Overflow is used to trigger the A-D
converter if A-D control also has the FAST-SAMPLE flip-flop set. This allows

110

analog-to-digital conversions to take place

1 1

clock. In this

100

under the automatic timing control of the

mode, A-D conversions are triggered only by the clock counter overflow.
The SAM instruction reads the result of the previous conversion and sets the channel
number for the next conversion. For details of the Analog-to-Digital converter, see
Paragraph 6. 1 1 The remaining two Mode Control bits are decoded exactly as above.
.

CLAB

AC to Buffer Frese R egister
t

6133

Octal code:

Event time:

Execution time

2
:

Operation:

4.25 /xs
Transfer AC to Buffer Preset register. The previous contents of the Buffer Preset registers are
lost and the

AC is unchanged.

CLEN Load Clock Enable Register
Octal code:

6134

Event time:

Execution time:

4.25 jLts

Operation:

The contents of the AC are transferred to the Clock Enable register. The function of each bit is
given below:

6-24

Function

Bit

Not used
Not used
Not used
Not used

00
01

02
03
04
05
06
07
08
09

Inclusive OR Clock Buffer into counter if mode = XOl and overflow =
Enable Interrupt when overflow ( 1
Enable Interrupt on Event 1
Enable Input Channel 1
Enable Interrupt on Event 2
Enable Input Channel 2
Enable Interrupt on Event 3
Enable Input Channel 3

10
11

CLSA

Clock Status to AC

Octal code:

6135

Event time:

1,3

Execution time:

4.25 MS

Operation:

This instruction interrogates the

CLOCK INPUT and OVERFLOW STATUS flip-flops. The

clock status information is inclusive ORed into the AC. Then the AC status bits which are set
are cleared. This ensures that only

one occurrence of an EVENT will be transferred to the

program.

AC Bit

Status Condition

OVERFLOW FUp-Flop

Not used
Not used
Not used
Not used
Not used

02
03
04
05
06
07
08
09

CLBA

Event 1
Pre-Event 1

Event 2
Pre-Event 2

Event 3

Pre-Event 3

Buffer Preset Register to AC

Octal code:

6136

Event time:

2,3

Execution time:

4.25 jlis

Operation:

The AC is cleared and the contents of the Clock Buffer Preset register are transferred into the
AC.

CLCA

Counter to AC

Octal code:

6137

Event time:

1,2,3

Execution time:

4.25 ius

Operation:

The

cleared

and

the

contents

of the

Clock

Counter are transferred to the

BUFFER-PRESET register. Then the contents are transferred into the AC.
6.2.2

KW12-B and KW12-C Fixed-Interval Clocks

The KW12-B provides a means of interrupting the CP at intervals determined by a variable RC Oscillator. The

KWl 2-C is similar to the KWl 2-B except that the RC oscillator is replaced by a crystal oscillator with a single fixed
frequency. The KWl 2-B or KWl 2-C may be turned on or off under program control. However, variations in
frequency require physically altering or changing the oscillator.

6-25

Instruction Set

The KW12-B and KW12-C are controlled by lOT instructions. These instructions can be used from either mode.
Execution time for the Simple Clock lOTs is 4.25 ijls when in 8 mode and 5.9 /xs when in LINC mode (using lOB).

CSOF

Skip on Clock Flag

Octal code:

6131

Execution time:

4.25 jus

Operation:

Skip if clock flag is set.

CTOC

Turn Off Clock

Octal code:

6132

Execution time:

4.25 jus

Operation:

Turn off the clock, clear the clock flag, and disable the clock interrupt.

CTON

Turn On Clock

Octal code:

6134

Execution time:

4.25 jtxs

Operation:

Turn the clock on and clear the flag.

CR UN

Clock Running

Octal code:

6135

Execution time:

4.25 jus

Operation:

Turn on the clock, enable the clock interrupt, clear the clock flag, skip if the clock flag was set

when the instruction was issued.
Frequency Range

KW12-B

The KW12-B uses the M401 variable clock in slot F18 for a time base. The frequency may be
by adjusting a potentiometer on the module. Five frequency ranges are

varied with a range
available.

The KW12-B is nominally

set to

the 1.75 kHz-to-17.5

kHz frequency range by

jumpering F18N2 to F18T2. Other frequency ranges may be achieved by removing the jumper

from F 1 8T2 and attaching as shown below. The exact frequency may be checked by observing
the signal on F18D2 with an oscilloscope.

Frequency Range

17.5 kHz to

KW12-C

6-26

50 kHz

Interconnections Required

F18N2-F18S2

1.75 kHz to 17.5 kHz

F18N2 - F18T2 (nominal setting)

175 Hz to 1.75 kHz

F18N2-F18P2

The KW 1 2-C uses the M405 crystal clock in slot F 1 8 for a time base. The frequencies are fixed
by a series resonant crystal oscillator to obtain a frequency stability of .01 percent of the
specified value between 0°C and +55°C. The frequencies available are in the range of 5 kHz to
50 kHz ,and must be specified in advance by the customer.

6.3

DISK STORAGE

Random Access Disk File, Types DF/DS32 and DF/DS32-D

6.3.1

The DF32 and DF32-D operate through the three-cycle data break facility to provide 32,768 13-bit words (12 bits
plus 1 parity bit) of storage, and are economically expandable to 131,072 13-bit words using the respective
expander disk, DS32 or DS32-D.

The DF32 and DF32-D comprise two basic assemblies: the storage unit containing the read/write circuits and the
computer interface logic. The storage unit contains a nickel cobalt plated disk driven by a hysteresis synchronous
motor. Data is recorded on a single disk surface by 16 read/write heads in fixed positions. The disk motor,
read/write data heads, and photocell assembly (on DF32) are all mounted on a rack assembly that permits sliding
the unit in and out of a DEC 1 9-inch Standard Cabinet.

The following table summarizes the DF32 and DF32-D:

DF32

DF32-D

60Hz

50Hz

60Hz

50Hz

16.67

Same

Data Transfer rate
(microseconds per word)

Average Access Time
(milUseconds)

Timing and Address Track
"Start

& Finish" Sensing

Type of Logic

Photo-electric

marker

reflective

Special

Start

and

outer

coding

and

decoding

disk

perimeter

timing track

Negative

DF32DP - Positive
DF32DN - Negative

Finish

Instructions

The DF32 and DF32-D disk systems share the following instruction set:

DCMA

Clear Disk Memory Address Register

Octal code:

6601

Event time

Execution time:

4.25 /.is

Operation:

Clears Memory Address Register, parity error, and completion flags. This instruction clears the
disk memory request flag and interrupt flags.

Symbol:

-> completion flag
-^ error flag

6-27

DMAR

Load Disk Memory A ddress Register and Read

Octal code:

6603

Event time;

1,2

Execution time

4.25 MS

Operation:

The contents of the AC are loaded into the disk memory address register and the AC is cleared.
Begins to read information from the disk into the specified core location. Clears parity error

and completion flags. Clears interrupt flags.

AC.

Symbol:

DMAo-

-^ completion flag

-^ error flag

DMA W

Load Disk Memory Address Register and Write

Octal code:

6605

Event time:

1,3

Execution time:

4.25 MS

Operation:

The contents of the AC are loaded into the disk memory address register and the AC is cleared.
Begins to write information onto the disk from the specified core location. Clears parity error
and completion flags. Clears interrupt flags. Data break must be allowed to occur within 66
microseconds after issuing this instruction.

ACo-ii ^DMAo-n
-^ completion flag

Symbol:

-^ error flag

DCEA

Clear Disk Extended Address Register

Octal code:

6611

Event time:

Execution time:

4.25 //s

Operation:

Clears the Disk Extended Address and Memory Address Extension register.

Symbol:

-* Disk Extended Address Register
-* Memory Address Extension Register

DSAC

Skip on Address Confirmed Flag

Octal code:

6612

Event time:

Execution time:

4.25 /xs

Operation:

Skips next instruction if address confirmed Flag is set. Flag is set for 16 ^s (AC is cleared).

Symbol:

If address confirmed flag = 1, then

PC + 1 -> PC

DEA L

L oad Disk Ex ten ded A ddress

Octal code:

6615

Event time:

1,3

Execution time:

4.25 jus

Operation:

The disk Extended Address and Memory Address Extension registers are cleared and loaded
with the track address data in the AC.

Symbol:

AC^-g "* Core Memory Extension
ACi-5 ->• Disk Address Extension 32K, 64K, 96K, 128K

ACq 9-11 used in DEAC instruction
(See NOTE on opposite page)

6-28

DEA C Read Disk Extended Address Register
6616

Octal code:

Event time:

2,3

Execution time:

4.25 /lis

Operation:

Clear the

AC then load the contents of the disk Extended Address register into the AC

allowing program evaluation. Skip next instruction if address confirmed flag is set.

Disk Address Extension 32K, 64K, 96K, 1 28K

Symbol:

^ ACi -g

Core Memory Extension -^ AC^ -g
Photo-cell sync mark -> ACq (Available 200 /xs)

Data Request Late flag ^ AC9
Non-Existent or Write Lock svi^itch on -> ACj
Parity Errors -^ ACi ^

NOTE
For the DEAL and DEAC instructions, refer to the diagrams shown below.

BITS 1-5
(DEAL INST)

ACCUMULATOR

DISC

(LOW ORDER 12 BITS)

ADDRESS

0-llofDMAWorDMAR

(17 BIT)

CURRENT ADDRESS
(MEMORY) ADDRESS

FIELD BITS

CELL 7751
(CURRENT ADDRESS)

6-8

(DEAL INST)

DFSE

(15 BIT)

Skip on Zero Error Flag

6621

Octal code:

Event time

Ex ecution time

1
:

Operation:

4. 2 5 /us

Skips next instruction if parity error, data request late, and write lock switch flag are clear.
Indicates no errors.
If Parity Error flag =

Symbol:

and Data Request Late flag = 1
and Write Lock Switch flag = 1 then PC + 1 -> PC
,

DFSC

Skip on Data Completion Flag

Octal code:

6622

Event time:

Execution time:

4.25 /us

Operation:

Skips next instruction

Symbol:

If Completion flag =

1 ,

the completion flag

set.

Indicates data transfer

complete.

PC + 1 ^ PC

6-29

DMA C

Read Disk Memory Address Register
6626

Octal code:

Event time:

2,3

Execution time:

4.25 /is
Clears the AC then loads contents of the Disk Memory Address register into the

Operation:

AC allowing

program evaluation. During read, the final address is the last one transferred.
Symbol:

DMAq-i

-* ACq-j

The computer can handle 12 bits; therefore, the high order bits for Disk and Memory addresses are manipulated by
the DEAL and DEAC instructions. Low order bits are manipulated in the accumulator (AC).
The Disk address is a

Memory address is a

17-bit value. Bit

DEAL and DEAC instructions is the most significant bit. The
DEAL and DEAC instructions is the most significant bit.

of the

7-bit value. Bit 6 of the

Note that the Word Count 7750 is the two's complement of the number of words to be transferred and that the
Disk address is the desired starting address. The Memory or Current address (775 1) is the desired address-1.

NOTE
Write Lock
instructions.

Switch status is true only when the disk module contains write
The nonexistent disk condition will appear following the completion of

a data transfer during read, where the address acknowledged was the last address of a

disk

and the next word to be addressed

falls

within a nonexistent disk.

The

completion flag for the data transfer is set by the nonexistent disk condition 16
microseconds following the data transfer.
6.3.2 Disk Memory System Type RF/RS08

The RF08 control and RS08 disk combine as a fast, low-cost, random access bulk storage package for the
PDP-12A. One RS08 and RF08 provide 262,144 13-bit words (12 bits plus parity) of storage. Up to four RS08
disks can be added to the RF08 control for a total of 1,048,576 words of storage.

Data transfer rate on 60 Hz power is 16.2 microseconds per word or 20 microseconds per word on 50 Hz. Data
transfer is accompUshed through the three-cycle data break system of the PDP-1 2 A.

Average access time with a 60 Hz disk is 16.67 milliseconds, or 20 miUiseconds at 50 Hz power. Worst case access
time is 33 miUiseconds on 60 Hz power, or 40 miUiseconds on 50 Hz power.

The RS08 disk unit contains a nickel-cobalt plated disk driven by a hysteresis synchronous motor. Data is recorded
on a single disk surface by 128 fixed read/write heads. The RF08 and RS08 are designed for mounting in a
standard 1 9-inch DEC cabinet.

The input-output transfer instructions for the RF/RS08 Disk Memory system are identical with the input-output
transfer instructions for the Type DF32 Random Access Disk file (Table 6-4).

Instructions

The RF/RS08 has the following DF32 Programming Compatibility:

DCMA

Clear Disk Memory A ddress Register

Octal code:

6601

Event time

Execution time:

4.25 jUS

Operation:

Clear the Disk
interrupt enable.

6-30

Memory Address register, and all other disk and maintenance flags except

DMAR

Load Disk Memory Address Register and Read
6603

Octal code:

Event time:

1,2

Execution time

4.25 jUS

Operation:

Load the low order 12 bits of the Disk Memory Address with information (initial address) in
the accumulator. Then clear the AC. Begin to read information from the disk into the specified
core location. Clear parity error and completion flags. Clear interrupt flags.

During Read, the final address status is the last address transferred + 1

When reading the last address of the last available disk the nonexistent disk flag is raised in
coincidence with the completion flag.

DMA W

Disk Memory Address Register and Write

Octal code:

6605

Event time:

1,3

Execution time:

4.25 jus

Operation:

Load the low order 12 bits of the Disk Memory Address register with information (initial
address) in the accumulator (AC), Then clear the AC. Begin to write information onto the disk

from the specified core location. Clear parity error and completion flags. Clear interrupt flags.
During Write, the final address status is the last address transferred.
Write Lock Switch status is true only when disk module contains a Write Command.

PROCESSOR
ACCUMULATOR

'
'

DISK ADDRESS

LEAST SIGNIFICANT BITS

The DF32 maintenance instruction lOT 663X is not assigned to the RF08 system.

DCIM

Clear Interrupt Enable and Core

Octal code:

MA Extension Registers

6611

Event time:

Execution time:

4.25 ^us

Operation:

Clears the disk interrupt enable and core memory address extension registers.

DSAC

Skip on Confirmed Flag

Octal code:

6612

Event time

Execution time:

4.25 jUs

Operation:

Maintenance Instruction Skip next instruction if the Address Confirmed flag is a 1. (AC is
cleared.)

6-31

DIML

Clear Interrupt Enable and

MA Extension Register and Load

6615

Octal code:

Event time:

1,3

Execution time:

4.25 jus
Clears the interrupt enable, and memory address extension register. Then loads the interrupt

Operation:

enable and memory address extension registers with data held in the accumulator. Then clears

AC.

INT

ENB
CLOCK

MEM

INT

ENB
ERR

ENB
COMPL

MEM

PROCESSOR
ACCUMULATOR

'A&iMdl

Z
f
INTERRUPT
ENABLE
REGISTER

RF08
STATUS REG

1
t
1
CORE MEMORY
EXTENSION

PROCESSOR

EXTENDED
MEM SEL

MEM.
FIELD

DIMA

Clear

771

6/f\y

AC and Load from Status

Octal code:

6616

Event time:

2,3

Execution time:

4.25 jus

Operation:

Clears the accumulator.

Then loads the contents of the status into the accumulator to allow

program evaluation

PROCESSOR
ACCUMULATOR PCA DRE WLS
/

EIE

PIE
i

CIE
i

F.3
i

F.2
i\

F.I

DRL NXD PER

RF08
STATUS REG

DFSE

Skip on Zero Error Flag

Octal code:

6621

Event time:

Execution time:

4.25 fis

Operation:

Skips the next instruction if there is a Parity Error, Data Request Late, Write Lock Status, or

Nonexistent Disk flag set.

6-32

DFSC

Skip on Data Completion Flag

6622

Octal code:

Event time

Execution time:

4.25 ius

Operation:

Skips next instruction if the Completion flag is a 1 (data transfer is complete).

DISK

Skip on Error or Completion Flag

6623

Octal code:

Event time:

1,2

Execution time:

4.25 )us

Operation:

Skips next instruction if either the Error or Completion flags or both are set.

DMA C

Read Disk Memory A ddress Register
6626

Octal code:

Event time:

2,3

Execution time:

4.25 jUS
Clears the accumulator. Then loads the contents of the Disk Memory address register into the

Operation:

accumulator to allow program

This

evaluation.

instruction

must be issued when the

completion flag is set,

DCXA

Clear Address Register

Octal code:

6641

Execution time:

4.25 /is

Operation:

Clears the high order 8-bit disk address register.

DXA L

Clear A ddress R egister and Load from A C

Octal code:

6643

Execution time:

4.25 /xs

Operation:

Clears the High Order 8 bits of the disk address register. Then loads the disk address register
from the data held in the accumulator. Then clears the AC.

PROCESSOR
ACCUMULATOR

RF08

i^ &

DISK SELECT

DISK ADDRESS
HIGH ORDER BITS

LEAST SIGNIFICANT BITS

DXA C

Clear

AC and Load

Octal code:

6645

Execution time:

4.25 jUS

Operation:

Clears the accumulator, then loads the contents of the High Order 8-bit disk address register

into the accumulator.

6-33

DISK

RF08

SELECT

DISK ADDRESS
HIGH ORDER BITS

LEAST SIGNIFICANT BITS

DMMT

(Maintenance Instruction)

Octal code:

6646

Execution time:

4.25 jUs

Operation:

For maintenance purposes only, with the appropriate maintenance cable connections and the
disk disconnected from the RS08 logic, the following standard signals may be generated by
lOT's 646 and associated
issuing an lOT 601

AC bits. AC is cleared. The maintenance register is initiated by

command.

ACii(l)
ACio(l)

Track A Pulse

AC^d)
AC^d)

Track C Pulse

AC,(1)

+1 Photocell

ACo(l)

+1 DBR

Setting

Track B Pulse

DATA PULSE (DATA HEAD #0)

DBR to a

causes Data Break Request in computer.

NOTE
TAP must be generated to strobe Track B signal into address comparison network.

Disk Address Register — 20 bits

TRACK
SELECT

DISK

SELECT

BITS

TRACK
POSITION

bits'

BITS'

EXTENDED
DISK
MEMORY ADDRESS

MEMORY ADDRESS

BEITS

12 BITS

DISK

Programming Example

A programming example that writes a block of data onto the disk is shown below. For simplicity, the example
assumes that all data and instructions are within the same page, but in actual practice this may not be true.

6-34

Table 6-4.

DF32 Instructions Compared with RF/RS08 Instructions

DF32

Octal

RF08

RF08 to DF32

Mnemonic

Code

Mnemonic

Comparison

DCMA

6601

same

Identical functions.

DMAR

6603

same

Identical functions.

DMAW

6605

same

Identical functions.

DCEA

6611

DCIM

Clears interrupt enable, does not clear EMA. On both
units, clears memory address extension.

DSAC

6612

same

DEAL

6615

DIME

Identical functions.

except functions transmitted from the AC

Similar,

are different.

EMA information not transmitted. See

DXAL.

DEAC

6616

DIMA

Similar, except that functions transmitted to the

are different. See DXAC.

DFSE

6621

same

Instruction is skip on error, rather than skip-no error.

NXD added as an error.
DFSC

6622

same

Identical function.

(none)

6623

DISK

New instruction. Skips on error or data completion,
or both. (DFSE and DFSC combined.) Skip enabled
at lOP 2.

DMAC

6626

same

Identical functions.

(none)

6641

DCXA

Clears EMA.

(none)

6643

DXAL

Clear

and

load

EMA

with

information

the

accumulator.

(none)

6645

DXAC

Clear accumulator and load address in

EMA into the

accumulator.

(none)

6646

DMMT

Maintenance instruction. See description.

6-35

/CALLING SEQUENCE
JMS WRT

SUB,

/JUMP TO WRITE SUBROUTINE
/CONTAINS WORD COUNT
/CONTAINS INITIAL CORE MEMORY ADDRESS
/CONTAINS TRACK AND UNIT NUMBER
/CONTAINS TRACK ADDRESS

XXX

/CONTINUE WITH MAIN PROGRAM

/WRITE SUBROUTINE
WRT,

/ENTER WRITE SUBROUTINE
/FETCH WORD COUNT
/DEPOSIT IN WORD COUNT REGISTER
/INCREMENT POINTER
/FETCH INITIAL CORE MEMORY ADDRESS
/DEPOSIT INTO CURRENT ADDRESS REGISTER
/INCREMENT POINTER

TAD WRT
I

DCAWC
ISZ WRT

TAD WRT
I

DCACA
ISZ WRT
TAD WRT
I

DIML
ISZ WRT

TAD I WRT
DXAL

/FETCH TRACK AND UNIT NUMBER
/DEPOSIT INTO REGISTER IN RF08 CONTROL
/INCREMENT POINTER
/FETCH TRACK ADDRESS
/TRACK ADDRESS TO DMA IN DISK;
/START WRITE OPERATION
/WRITE OPERATION
/FOR ERROR OR COMPLETE

ISZ WRT

TAD I WRT

DMAW
DISK
JMP .-1
DFSE
JMP .+2
JMP ERR

/NO, WAIT

/ANY ERRORS?
/NO, SKIP OVER ERROR EXIT
/YES, TO ERROR SUBROUTINE

ISZ WRT

/INCREMENT POINTER TO EXIT ADDRESS

JMP I WRT

/EXIT PROGRAM

NOTE
This coding assumes no live interrupts.

The calling subroutine must be set up so that the subsequent locations to SUB (SUB+1, SUB+2, etc) contain the
parameters as shown in the comments column.

The JMS WRT instruction causes a subroutine jump location WRT with the contents of the PC-1 (which contains
symbolic address SUB-1) deposited into location

WRT.

Since location

WRT now contains SUB+1, the first

instruction of the subroutine (TAD I WRT) loads the AC with the contents of SUB+1 or the word count. The word

count is then deposited into the WC (Memory Address 7750) register. Similarly, the initial address is deposited into
the

CA (Memory Address 7751) register. The program then proceeds to set up the EMA and DMA registers and

starts the write operation.

DMAW

After the
instruction is issued, the data transfer operation begins and continues
independently of the program; it operates under control of the data break faciUty to transfer data. When the
transfer is complete, the DCF (Data Complete Flag) comes up and, when sensed by the DFSC control, passes to the

DFSE instruction. DFSE then senses for errors; and if any are detected, control jumps to an error or diagnostic
(not shown) routine. If no errors are found, control exits from the subroutine back to the main program to resume
main processing.

should be noted that, since the data transfer operates independently of the program, the subroutine could be

exited following the
since the DCF and

6-36

DMAW instruction. An interrupt subroutine could handle the post data transfer processing,

ERROR FLAGS generated an interrupt.

An identical program could handle data transfers for a read operation, except that the DMAW instruction is
replaced by the

DMAR instruction.

Specifications:

Storage Capacity

Each RS08 stores 262,144 13-bit words (12 plus one parity bit).

Disks

Four RS08s may be controlled by one RF08 for 1,048,576 words.

Data Transfer Path

Three-Cycle Break

Address Locations

7750 Word Count
7751 Memory Address
Data Transfer Rate

60 Hz Power

50 Hz Power

16.2 JUS per word

20 JUS per word

Minimum Access Time

258 JUS

320 ms

Average Access Time

16.9 ms

20.3 ms

Maximum Access Time

33.6 ms

40.3 ms

Program Interrupt

33 ms Clock Flag

Data Transmission Complete Flag
Error Flag
Write Lock Switches

Eight switches per disk capable of locking out any combination of eight 16,384

word blocks in address
Data Tracks

128

Words Per Track

2048

Recording Method

NRZI

Density

1100 BPI Maximum

Timing Tracks

3 plus 3 spare

Operating Environment

to 1 3 1 ,07 1

Recommended temperature 65°

to 90°F.

Relative humidity

20% to 80%. No

condensation during storage or operating.

Vibration/Shock

Good isolation is provided. Vibrating, shaking, or rocking of the cabinet with
large,

Uft

low frequency displacements can cause data errors. For example, hand fork

trucks operating

which could cause

on wooden

errors.

floors cause excessive vertical displacements

The RS08 is not designed for aircraft or shipboard

mounting.

Heat Dissipation

RF08: 150 watts
RS08: 500 watts

AC Power Requirements

1 1

RS08

Motor start 5.5 amps for 20 ± 3 sec. Motor run 4.0 amps continuous.

5 ± 1

Vac, single phase, 50 ± 2 or 60 ± 2 Hz

6-37

Maximum line frequency drift 0.

Line Frequency Stability

set

Hz/sec. A constant frequency motor-generator

or static ac/ac inverter should be provided for installations with unstable

power sources.
Six recoverable errors and one nonrecoverable error in 2 x 10^ bits transferred.

Reliability

recoverable error is defined as an error that occurs only once in four successive
reads.

All other errors are nonrecoverable. On-off cycling of the

RS08 is not

recommended. The RS08 motor control operates independently of the computer

power control, thus eliminating on-off cycling except for power failures.

A H950 cabinet is designed to accommodate one RF08, up to two RSOSs, and
power supplies. Two additional RSOSs can be mounted in a second H950. Other
equipment should not be mounted in disk cabinets.

Cabinet

6.3.3

RK8 Disk Cartridge Memory System

The RK08 Control and RKOl Disk Drive (RK8) are low cost, random access, removable disk storage devices. One

RK08/RK01

provides 831,488

13-bit (12 bits plus parity)

words of storage. Up to four RKOl disks can be

operated by the RK08 Control for a total of 3,325,952 words of storage.

The removable cartridge utilized is an IBM 2315 disk pack or equivalent with a single aluminimum disk platter
coated on both sides with magnetic oxide. Average access time is 1 54 miUiseconds with the read/write head at
random positions. Data transfer rate is 16.7 microseconds via the PDP-12 single-cycle data break faciHty. The

RK8-P will operate off the positive I/O bus. An RK8-N is also available for connection to a negative I/O bus.
Instructions

DLDC

Load Command Register

Octal code:

6732

Operation:

LxDads the Command Register from the AC, clears the AC.

COMMAND
REGISTER

ENABLE CHANGE IN
INTERRUPT STATUS

J
DOUBLE
DENSITY

ENABLE PROGRAM
INTERRUPT ON
TRANSFER DONE

DISK
FILE

EXTENDED

MEM

ENABLE INTERRUPT
ON ERROR

ADDRESS

UNUSED

SEEK TRACK 8
SURFACE ONLY

ENABLE READING OR
WRITING OF 2

HEADER WORDS

6-38

L0GICAL1 = FUNCTI0N TRUE

NUMBER

*DLDR

Load Disk A ddress and Read

Octal code:
Operation:

6733
Loads track, surface, and sector address from AC, then clears AC and starts to read

data from

disk if Command Register bit 4 = 0.

*DLDW Load Disk Address and Write
Octal code:

Operation:

*DCHP

6735
Loads track, surface, and sector address from AC, then clears AC. Starts to write on disk if
Command Register bit 4 = 0.

Load Disk Address and Check Parity

Octal code:
Operation:

6737
Loads track, surface, and sector address from AC, then clears AC. Reads data and
checks
parity if Command Register bit 4 = 0.

1 1

TRACK ADDRESS

SURFACE /SECTOR
ADDRESS
REGISTER

)

TR/\CK

S ECTO R
AD DRE SS

ADDF*ESS

SURFACE
BIT
12-0199

*If command register bit 4 = 1, instruction will be executed only to seek track and surface. These three instructions
start all disk operations.

6-39

DRDA R ead Disk A ddress
Octal code:

6734

Operation:

Clears AC and then reads Track Address Counter and surface/sector counter into AC.

DRDC

Read Disk Command Register

Octal code:

6736

Operation:

Clears

DRDS

AC then reads Command Register into the AC.

Read Disk Status Register

Octal code:

6741

Operation:

Clears the AC and then reads the Status Register into the AC.

0123 456789

STATUS
REGISTER
t\

ERROR
TRANSFER DONE
CONTROL BUSY
ERROR
TIME OUT ERROR
PARITY OR
TIMING ERROR

DATA RATE ERROR

TRACK ADDRESS
ERROR
SECTOR NO GOOD
ERROR
WRITE LOCK ERROR

TRACK CAPACITY
EXCEEDED ERROR
SELECT ERROR

BUSY
LOGICAL 1= FUNCTION TRUE

DCLS

Clear Status Register

Octal code:

Operation:

6-40

6742
Qears the Status Register.

DMNT

Load Maintenance Register
6743
Loads Maintenance register from AC and carries out the operation specified. Bits will remain
set until DMNT is issued with AC bits = 0.

Octal Code:

Operation:

MAINTENANCE
CE
REGISTER

LOGICAL 1 = FUNCTION TRUE

AC Bit
Transfer contents of Track address Register to Track counter Register.
1

Transfer Data Register to Serial Register.

Transfer Serial Register to Data Register.

Qear AC and Read Data Register into AC.

Shift a " 1" into the Serial Register.

Shift a "0" into the Serial Register.

Unformatted Disk

Sector Pulse.

Index Pulse.

9-11

DLDA

Not used.

Load Disk Address (Maintenance Only)

Octal code

6731

Operation:

Loads the disk address register with the content of AC.

DlSKD

Skip on Transfer Done Flag = 1

Octal code:

6745

Operation:

Skips next instruction if the Transfer Done Flag is a 1

DSKE

Skip on Error Flag = 1

Octal code:

6747

Operation:

Skip when Error flag is equal to 1

DCLA

Clear All

Octal code:

6751

Operation:

Clears selected Disk to Track 000.

Then clears all control registers and flags except disk

selection. Transfer done set when disk positioned on Track 000.

6-41

DR WC Read Word Coun t Register
Octal Code

6752

Operation:

Clears AC, then reads the contents of the Word Count register into the AC.

DL WC Load Word Coun t Register
Octal code:

6753

Operation:

Loads Word Count register from AC, then clears the AC.

Load Curren t A ddress Register

DL CA

Octal code:
Operation:

DRCA

6755
Load Current Address register from AC; then clears the AC.

Read Current Address Register

Octal code:

6757

Operation:

Clears the AC then reads the contents of the Current Address register into the AC.

Example of I/O Subroutine
DISKIO,

TAD CNT
DLWC
TAD CUR
DLCA
TAD 0000
DLDC
TAD ADR
DLDR
DSKD
JMP.-l

DSKE
JMP I DISKIO
JMP ERR

/PUT COMMAND IN ACCUMULATOR

/LOAD COMMAND REGISTER
/FETCH TRACK, SURFACE, & SECTOR
/LOAD DISK ADR AND READ DATA
/DLDW WOULD HAVE WRITTEN
/DONE WITH TRANSFER?
/NO - GO BACK 1
/YES - IS THERE AN ERROR?
/NO ERROR - RETURN
/GO TO ERROR SUBROUTINE
/# WORDS TO BE READ

CNT
CUR

/BEG. ADDR. OF MEMORY BUFFER

/DISK ADDRESS

ADR
Models

/SUBROUTINE ENTRY POINT
/FETCH # OF WORDS TO BE READ
/LOAD WORD COUNT REGISTER
/FETCH ADD OF MEMORY BUFFER
/LOAD CUR ADDR. REGISTER

RK8-P

Positive Bus System; includes RKOl and RK08-P

RK8-N

Negative Bus System; includes RKOl and RK08-N

RKOl

Consists of disk drive, interface and removable cartridge (up to 4 per RK8 system)

RK08-P

Positive Bus disk control

RK08-N

Negative Bus disk control

See RK8 Manual for details.

6-42

Specifications

Disks

Four RKOls per RK08 for 3,325,952 words.

Storage Capacity

Each RKOl stores 831,488, 12-bit words.

Data Transfer Rate

16.7 /us per word

Transfer Path

Single-cycle Data Break

Minimum Access Time

2.35 ms

Average Access Time

154 ms

Maximum Access Time

477 ms

Settle Time

37 ms

Program Interrupt

Transfer Done Flag

Write lock

Two words at the beginning of each track contain status information that is
automatically

checked for write lock of

sectors.

Also total disk can be

write-locked.

Data Tracks

200 plus 3 spare

Words per Track

4096 (2048 on each of two sides)

Sectors

1 6

Words per Sector

256

Min. Block Size

256 words

Max. Block Size

4096 words

Recording Method

Double Frequency-Time plus Data

Density

Speed

1500 rpm

per track

026 bits/inch max.

Environmental Requirements
Operating Temp

+65°F to 90°

Operating Humidity

20% to 80% excluding all conditions which would cause condensation.

Heat Dissipation

RK08- 150 watts
RKOl per drive; 700 watts, 1 KW, surge

AC Power Requirements

115±10VAC, 60±»/2Hertz
230 ±20 VAC, 60 ±1/2 Hertz

6-43

One standard DEC cabinet will accommodate the RK08 and one RKOl. A

Mechanical Package

second cabinet will house two RKO 1 units. A third cabinet will house a fourth

RKOl.

6.3.4 Disk Software

Mass Storage LAP6-DIAL-MS, commonly referred to as DIAL-MS or DISK-DIAL,

a modified version of

LAP6-DIAL that may use a disk for the LAP6-DIAL System and/or user programs. The minimum hardware
configuration required is 8K of core storage and two LINCtape transports. LAP6-DIAL-MS will support one of the
following:

One or two DF32 or FD32D Disks

One to four RF08 Disks

One RK8 Disk.

LAP6-DIAL-MS will use only one of the above; for example, the RK8 rather than a DF32, or a RK8 rather than a
It is not possible to operate a DF32 and a RF08 in the same
system as the lOT instructions are similar.
RF08, if more than one are installed in the system.

A brief description of LAP6-DIAL-MS is provided in Paragraph 7.1.1,

6-44

6.4

MAGNETIC TAPE

6.4. 1

Automatic Magnetic Tape Control, Type TC58

Functional Description

The Type TC58 will control the operation of a maximum of eight digital magnetic tape transports, Types TU20
and TU20A. The Type TC58 interfaces with the PDP-12 three-cycle data break facility, which it uses for data
transfer directly between system core memory and magnetic tape. The tape transports offer industry compatibility
(or IBM compatibility) in both 7- and 9-channel tape transports with the following characteristics:

Tape Speed

Densities

Transport

(ips)

(bpi)

TU20 (7-channel)
TU20A (9-channel)

45
45

200/556/800
800

Transfers are governed by the

memory word count (WC) and current address (CA) registers associated with the

assigned data channel (memory locations 328 ^^'^ SSg). Since the CA is incremented before each data transfer, its
initial

contents should be set to the desired initial address minus one. The

WC is also incremented before each

transfer and must be set to the two's complement of the desired number of data words to be transferred. In this

way, the word transfer which causes the word count to overflow (WC becomes zero) is the last transfer to take
The number of lOT instruction required for the TYPE TC58 is minimized by transferring all necessary

place.

control data (unit number, function, mode, direction, etc) from the PDP-12 accumulator (AC) to the control using

lOT instructions. Similarly, all status information (status bits, error flags, etc) can be read into the AC from the
control unit by JOT instructions.
During normal data reading, the control assembles 12-bit computer words from successive frames read from the
information channels of the tape. During normal data writing, the control disassembles 1 2-bit words and distributes
the bits so they are recorded on successive frames of the information channels.

Instructions

The instructions for the Magnetic Tape Control System are as follows:

MTSF

Skip on Error Flag or Magnetic Tape Flag

Octal code:

6701

Event time:

Execution time:

4.25 /is

Operation:

The status of the error flag (EF) and the magnetic tape flag (MTF) are sampled. If either or

Symbol:

both are set, the contents of the PC are incremented by one, skipping the next instruction.
If MTF or EF = 1 PC + 1 ^ PC

MTCR

Skip on Tape Control Ready

Octal code:

6711

Event time:

Execution time:

4.25 /xs

Operation:

If the tape control

ready to receive a command, the PC is incremented by one, skipping the

next instruction.

Symbol:

If Tape Control Ready, PC +

-^ PC

6-45

MTTR

Skip on Tape Transport Ready

Octal code:

6721

Event time:

Execution time:

4.25 /lis

Operation:

The next sequential instruction is skipped if the tape transport is ready.
If tape unit ready, PC + 1 -^ PC

Symbol:

MTAF

Clear Registers, Error Flag and Magnetic Tape Flag

Octal code:

6712

Event time:

4.25 /us

Operation:

Clears the status and command registers, and the EF and

MTF if tape control is ready. If tape

control is not ready, clears MTF and EF flags only.

Symbol:

If tape control is ready,

^ MTF,

-^ EF,

-^ command register
If tape control not ready,

MTRC

Inclusive

Octal code:

^ MTF,

OR Contents of Command Register
6724

Event time:

Execution time:

4.25 jus

OR the contents of the command register into ACq-i

Operation:

Inclusively

Symbol:

AC V command register -^ ACq-i

MTCM

Inclusive

-> EF

OR Contents of Accumulator

Octal code:

6714

Event time:

Execution time:

4.25 /us

Operation:

Inclusively

OR the contents of ACq-s ,9-1

into the command register:

8 (command function).

AC0-5 AC9-1 j V command register -> command register

Symbol:

ACg.g -> command register bits 6-8

MTLC

Load Command Register

Octal code:

6716

Event time:

2,3

Execution time:

4.25 jus

Operation:

Load the contents of ACq-i 1 into the command register.
ACq-i 1 -> command register

Symbol:

Inclusive OR Contents of Status Register

Octal code:

6704

Event time

Execution time:

4.25 /is

Operation:

Inclusively

Symbol:

Status Register

6-46

OR the contents of the status register into ACq-i
V AC ^ ACq-i
j

JAM transfer bits 6, 7,

MTRS Read Status Register
Octal code:

6706

Event time:

2,3

Execution time:

4.25 [xs

Operation:

Read the contents of the status register into ACq-i i

Symbol:

Status Register ->• ACq-i i

MTGO Mag Tape GO
Octal code:

6722

Event time:

Execution time:

4.25 /xs

GO bit to execute command in the command register if command is legal.

Operation:

Set

Symbol:

None

MCLA

Clear the

Octal code:

AC
6702

Event time:

Execution time:

4.25 MS

Operation:

Clear the accumulator.

Symbol:

O^AC

Although any number of tapes may be rewinding simultaneously, data transfer may take place to or from only one
transport at any given time. In this context, data transfer includes these functions: read or write data, write EOF

(end of file), read/compare, and space. When any of these functions is in process, the tape control is in the not

ready condition. A transport is said to be not ready when tape is in motion, when transport power is off, or when it
is off line.

Data transmission may take place in either parity mode, odd-binary or even-BCD. When reading a record in which
the number of characters is not a multiple of the number of characters per word, the final characters come into

memory left-justified.
Ten bits in the magnetic tape status register retain

error and tape status information.

Some error types are

combinations, such as lateral and longitudinal parity errors (parity checks occur after both reading and writing of
data), or have a combined meaning, such as illegal command, to allow for the maximum use of the available bits.

The magnetic tape status register reflects the state of the currently selected tape unit. Interrupts may occur only
for the selected unit. Therefore, other units which may be rewinding, for example, will not interrupt when done.

A special feature of this control is the Write Extended Inter-Record Gap capability. This occurs on a write
operation when Command Register bit 5

is set. The effect is to cause a 3-inch inter-record gap to be produced
before the record is written. The bit is automatically cleared when the writing begins. This is very useful for

creating a gap of blank tape over areas where tape performance is marginal.

Magnetic Tape Functions

For all functions listed below, upon completion of the data operation (after the end-of-record character passes the
read head), the MTF (magnetic tape flag) is set, an interrupt occurs (if enabled), and errors are checked.

No Operation - A NO OP instruction defines no function in the command register. A MTGO instruction with NO
OP will cause an illegal command error (set EF).

6-47

Space - There are two instructions for spacing records, SPACE FORWARD and SPACE REVERSE. The number
of records to be spaced (two's complement) is loaded into the WC. CA does not need to be set. MTF (magnetic
tape flag) is set, and an interrupt occurs at
first.

WC overflow, EOF (end of file), or EOT (end of tape), whichever occurs

When issuing a space instruction, both the density and parity bits must be set to the density and parity in

which the records were originally written.

Load Point or Beginning of Tape (BOT) detection during a backspace terminates the function with the BOT bit set.
SPACE REVERSE instruction is given when a transport is set at BOT, the instruction is ignored, the illegal

If a

command error and BOT bits are set, and an interrupt occurs.
Read Data - Records may be read into memory in the forward mode only. Both CA and WC must be set; CA to
the initial core address minus one, WC to the two's complement of the number of words to be read. Both density
and parity bits must be set.

WC is set to less than the actual record length, only the desired number of words are transferred into memory. If
WC is greater than or equal to the actual record length, the entire record is read into memory. In either case, both
If

parity checks are performed, the

MTF is set, and an interrupt occurs when the end-of-record mark passes the read

head. If either lateral or longitudinal parity errors or bad tape have been detected, or an incorrect record length
error occurs (WC not equal to the number of words in the record), the appropriate status bits are set. An interrupt

occurs only when the MTF is set.

To continue reading without stopping tape motion, MTAF (clear MTF) and MTGO instructions must be executed.
If the

MTGO command is not given before the shut down delay terminates, the transport will stop.

Write Data - Data may be written on magnetic tape in the FORWARD DIRECTION ONLY. For the WRITE
DATA function, the CA and WC registers and density and parity bits must be set. WRITE DATA is controlled by
the WC in such a way that, when the WC overflows, data transfer stops, and the EOR (end of record) character and
IRG (inter-record gap) are written. The MTF is set after the EOR has passed the read head. To continue writing, a
MTGO instruction must be issued before the shut-down delay terminates. If an error occurs, the EF will be set
when the MTF is set.

EOF - The Write EOF instruction transfers a single character (IVg) record to magnetic tape and follows it
with the EOR character; CA and WC are ignored for WRITE EOF. The density bits must be set, and the command
Write

be set to even (BCD) parity.

If it is set to

odd parity, the control will automatically

change it to even.

When the EOF marker is written, the MTF is set and an interrupt occurs. The tape transport stops, and the EOF
status bit is set, confirming the writing of EOF. If odd parity is required after a WRITE EOF, it must be specifically

requested through the MTLC instruction.

Read/Compare - The READ/COMPARE function compares tape data with core memory data. It can be useful for
searching and positioning a magnetic tape to a specific record, such as a label or leader, whose content is known in
core memory, or to check a record just written.

READ/COMPARE occurs in the forward direction only; CA and

comparison failure, incrementing of the CA ceases, and the READ/COMPARE error
WC must be
Tape motion continues to the end of the record; the MTF is then set, and an
in
the
status
register.
set
bit is
set. If there is a

interrupt occurs. If there has been a READ/COMPARE error, examination of the CA reveals the word that failed to

compare.

Rewind - The high speed REWIND instruction does not require setting of the CA or WC. Density and parity
settings are also ignored. The REWIND instruction rewinds the tape to loadpoint (BOT) and stops. Another unit

may be selected after the instruction is issued and the rewind is in process. MTF is set, and an interrupt occurs (if
the unit is selected) when the unit is ready to accept a new instruction. The selected unit's status can be read to
determine or verify that REWIND is in progress.

6-48

Continued Operation

To continue operating the same mode, the MTGO instruction is given before tape motion stops. The order

of instructions required for continued operation are as follows:

(1)

MTLC, if the instruction is to be changed.

(2)

MTAF, clears only MTF and EF flags, since tape control will be in a Not Ready state.

(3)

MTGO, if MTLC requested an illegal condition; the EF will be set at this time.

To change modes of operation, either in the same or opposite direction, the MTLC instruction is given to

change the mode and a MTGO instruction is given to request the continued operation of the drive. If a change in
direction is ordered, the transport will stop, pause, and automatically start up again.

If the

WRITE function is being performed, the only forward change in command that can be given is

WRITE EOF.
d.

If no

MTGO instruction is given, the transport will shut down in the inter-record gap.
NOTE
Flags will not be set when the control or the transport becomes ready, except if the

REWIND instruction is present in the command register and the selected drive
reaches BOT and is ready for a new instruction.

If a

WRITE (odd parity) instruction is changed to WRITE EOF, the parity is automatically changed to

even.

NOTE
Even parity will remain in the command register unless changed by a new command
instruction, MTLC, which clears and loads the entire command register.

Status or Error Conditions

Twelve bits in the magnetic tape status register indicate status or error conditions. They are set by the control and
cleared by the program.

6-49

The magnetic tape status register bits are
Function (When Set)

Bit

Error flag (EF)
1

Tape rewinding

Beginning of tape (BOT)

command

Illegal

Parity error (Lateral or Longitudinal)

End of file (EOF)
End of tape (EOT)
Read/Compare error

6
7

Record length incorrect

WC =
WC 9^

(long)
(short)

Data request late

9
10

Bad tape

Magnetic tape flag (MTF) or job done

The register bits are equivalent in position to the AC bits (i.e., SRq = ACq, etc).

MTF ( SRI 1) - The MTF flag is set under the following conditions:
a.

Whenever the tape control has completed an operation (after the EOR mark passes the read head).

When the selected transport becomes ready following a normal REWIND function. These functions will

also set the EF if any errors are present.

EOF (SR5) - End-of-file (EOF) is sensed and may be encountered for those functions which come under the
heading of READ STATUS FUNCTION; i.e., SPACE, READ DATA, or READ/COMPARE and WRITE EOF.
When EOF is encountered, the tape control sets EOF = 1. MTF is also set; hence, an interrupt* occurs and the EOF
status bit may be checked.

EOT (SR6) and BOT (SR2) - End-of-tape (EOT) detection occurs during any forward instruction when the EOT
reflective strip is sensed. When

EOT is sensed, the EOT bit is set, but the function continues to completion. At this

time the MTF is set (and EF is set), and an interrupt occurs.

Beginning-of-tape (BOT) deflection status bit occurs only when the beginning-of-tape reflective strip is read on the
transport that is selected.

When BOT detection occurs, and the unit is in reverse, the function terminates. If a tape unit is at load point when
a REVERSE instruction is given, an illegal command error bit is set, causing an EF with BOT set. An interrupt then
occurs.

*A11 references to interrupts assume the tape flags have been enabled to the interrupt (command register bit 9 - 1)

and the unit is selected.

6-50

Command Error (SR3) - The illegal command error bit is set under the following conditions:

Illegal

A command is issued to the tape control with the control not ready.

A MTGO instruction is issued to a tape unit which is not ready when the tape control is ready.

Any instruction which the tape control, although ready, cannot perform; e.g.:

(1)

WRITE with WRITE LOCK condition

(2) 9-channel tape and incorrect density

(3)

BOT and SPACE REVERSE

Parity (SR4) — Longitudinal and lateral parity checks will occur in both reading and writing.
for

either

lateral

or longitudinal parity failure.

The parity bit is set

A function is not interrupted, however, until MTF is set.

Maintenance panel indicators are available to determine which type of parity error occurred.

Read Compare Error (SR 7) - When

READ/COMPARE function is underway, SR7
READ/COMPARE ERROR (see earlier section on READ/COMPARE for further details).

set

for

Bad Tape (SRIO) — A BAD TAPE ERROR indicates detection of a bad spot on the tape. Bad tape is defined as
three or more consecutively missing characters followed by data, within the period defined by the READ
SHUTDOWN DELAY. The error bit is set by the tape control when this occurs. MTF and interrupt do not occur
until the end of the record in which the error was detected.

Record Length Incorrect (SR8) - During a read or read/compare, this bit is set when the WC overflow differs from
the number of words in the record. The EF flag is set.
Data Request Late (SR9) - This bit can be set whenever data transmission is in progress. When the DATA FLAG
causes a break cycle, the data must be transmitted before a write pulse or a read pulse occurs. If it does not, this
error occurs, and data transmission ceases. The EF flag and bit 9 of the status register are set when the MTF is set.
Error Flag (SRO) - The ERROR FLAG (EF) is set whenever an error status bit is present at the time that MTF is
set. However,

when an ILLEGAL COMMAND is given, the EF is set and the MTF is not set.

Command Register Contents

UNIT

CORE
DUMP

SELECTION
(0-7)
r
1

COMMAND

v^
WRITE

0-EVEN

EXTENDED

INTER

^-^

PARITY

1«0DD

DENSITY

<-^

FLAGS
"DISABLE
' ENABLE

RECORD GAP
(3^ OF BLANK

TAPE BEFORE
RECORD)

6-51

Unit Selection
Bits
fnit

Density Selection
Bits

Density

200 bpi
556 bpi
800 bpi
800 bpi

9 channel

Command Selection

Command

NO OP
Rewind
Read
Read/Compare

1
1
1

Write EOF

Space Forward

Space Reverse

Magnetic Tape Function Summary

LEGEND

CA = Current Address Register = 33

WC = Word Count Register =328
F = Forward

R = Reverse
DS = Density Setting
PR = Parity Setting

EN = Enable Interrupt

6-52

Write

Function

NO-OP

Characteristics

CA: Ignored

Status of Error Types

Illegal

WC: Ignored

BOT

DS: Ignored

Tape Rewinding

PR: Ignored

EN: Ignored

SPACE FORWARD

CA: Ignored
2's comp. of number

WC:

of records to skip

Illegal

EOF
Parity

DS: Must be set

Bad Tape

PR: Must be set

MTF, BOT,

EN: Must be set

EOT

SPACE REVERSE

Illegal

EOF
Parity

Same as SPACE FORWARD

Bad Tape

BOT
MTF

READ DATA

CA: Core Address - 1
WC: 2's comp. of number of

EOF

words to be transferred

Parity

Illegal

Bad Tape
PR: Must be set

MTF
EOT

EN: Must be set

Data Request Late

DS: Must be set

Record Length
Incorrect

WRITE DATA

Illegal

EOT
Parity

Same as READ DATA

MTF
Bad Tape
Data Request Late

WRITE EOF

CA: Ignored

Same as WRITE

WC: Ignored

DATA plus EOF

DS: Must be set
PR: Must be set

EN: Must be set

READ/COMPARE

Illegal

EOF
Same as READ DATA

Read/Compare Error
Bad Tape

MTF
EOT
Data Late

Record Length Incorrect

REWIND

CA: Ignored

Illegal

WC: Ignored

Tape Rewinding

DS: Ignored

MTF
BOT

PR: Ignored

EN: Must be set

6-53

6.4.2 Magnetic Tape Transports

The following paragraphs describe some of the Magnetic Tape Transports that are available for the PDF- 12 A. These
machines are also compatible with the automatic Tape Control Type TC58.

6.4.2.1

Magnetic Tape Transport, Type TU20 (7-Channel)

- The Type TU20 is a digital magnetic tape transport

designed to be compatible with the Type TC58 Magnetic Tape Control. The transport operates at a speed of 45
inches per second, and has three selectable densities: 200, 556, and 800 bpi. The maximum rate is 36,000 six-bit
characters per second. Standard seven-channel IBM-compatible tape format is used. The specifications for the unit
are as follows:

Format: NRZI. Six data bits plus one parity bit. End and loadpoint sensing compatible with IBM 729 I-VI.

Tape: Width 0.5 in., length 2400 ft. (1.5 mil.). Reels are 10.5 in. in diameter, IBM-compatible, with file protect

(WRITE LOCK) ring.

Head: Write-read gap 0.300 in.. Dynamic and skew is less than 14 microseconds.

Tape Specifications: 45 ips speed. Start time is less than 5 milliseconds. Start distance is 0.080 in. (+0.035, -0.025
in.).

Stop time is less than 1.5 milliseconds. Stop distance is 0.045 in. (±0.05 in.).

Density: 200, 556, and 800 bpi. Maximum transfer rate is 36 kHz.

Transport Mechanism: Pinch roller drive; vacuum column tension.

Controls:

ON/OFF, ON LINE, OFF LINE, FORWARD, REVERSE, REWIND, LOAD, RESET.

Physical Specifications: Width 22-1/4 in., depth 27-1/6 in., height 69-1/8 in., weight 600 lbs.

Read (ReadI Compare) Shutdown Delay:

3.6 milliseconds.

Write Shutdown Delay: Approximately 4.5 milliseconds.

9-Track Operation

and 7-track transports

may be

intermixed on the Type

TC58 control. When a transport is selected, it

automatically sets the control for proper operation with its number of tracks.

Control of 9-track operation is identical to 7-track, except as noted below:

Write:

A word in memory is written on tape with the following format:

LATERAL PARITY BIT OF CHARACTER

CHARACTER
BIT

X-

6-54

THESE BITS ARE IGNORED

Read — A word is read into memory from tape with the following format:

— LATERAL PARITY BIT OF CHARACTER
X

BIT

Read/Compare —

CHARACTER

A direct comparison of the characters on tape is made with those in memory. The parity bit is

ignored, as are bits 0-3 in each memory word.

Core Dump Mode

— This mode is used only with 9-track transports. It is entered by setting bit 4 of the command

Core dump mode permits the dumping of complete memory words in the form of two six-bit characters. The
format is:

CHARACTER

CHARACTER 2

BIT

This is accomplished by utilizing only 7 of the 9 tracks on the tape.

Tape written in CORE DUMP MODE must be READ (READ/COMPARE) in this same mode. These operations are
the same as for a 7-track transport.
6.4.2.2 Magnetic

Tape Transport, Type

TU20A (9-Channel) - The Type TU20A is a digital magnetic tape

transport designed to be compatible with the Type TC58 Magnetic Tape Control. The transport operates at a speed

of 45 inches per second, and a density of 800 bpi. The maximum transfer rate is 36,000 eight-bit characters per
second. Standard nine-channel IBM-compatible tape format is used. The specifications for the unit are as follows:

Format: NRZI. Eight data bits plus one parity bit. End and loadpoint sensing compatible with IBM.
Tape: Width 0.5 in., length 2400 ft. (1.5 mil.). Reels are 10.5 in. in diameter, IBM-compatible, with file protect

(WRITE LOCK) ring.
Heads: Write-read gap of 0. 1 50 in. Dynamic and static skew is less than 14 microseconds.

Tape Specifications: 45

ips speed.

Rewind time is less than 5 milliseconds. Start distance is 0.080 in. (+0.035,

-0.025 in.). Stop time is less than 1.5 milliseconds. Stop distance is 0.045 in. (±0.015 in.).

Density: 800 bpi. Maximum transfer rate is 36 kHz.

Transport Mechanism: Pinch roller drive; vacuum column tension.

Controls:

ON/OFF, ON LINE, OFF LINE, FORWARD, REVERSE, REWIND, LOAD, RESET,

Physical Specifications: Width 22-1/4 in., depth 27-1/6 in., height 69-1/8 in. Weight 600 lbs.

Read (READI COMPARE) Shutdown Delay:
Write Shutdown Delay:

3.6 milliseconds.

Approximately 4,5 milliseconds.

6-55

6.4.2.3 Magnetic Tape Transport, Type TU20C

General Description

The TU20C connects to the PDP-12 via the TC58 Automatic Magnetic Tape Control. lOT instructions, issued by
the PDP-1 2, control the operation of the tape transport; these instructions are decoded within the tape control unit
to specify the type of tape transport operation. To write on tape, the tape control unit sends a motion-forward

instruction and a write-enable instruction, and, for each character to be recorded, a record data pulse. For spacing

and reading tape, the tape control unit sends the required motion instruction. Therefore, regardless of the
operation, the tape is always being read and the data is always being transmitted to the tape control unit; this
information

used for detecting end-of-record to terminate operation. The TU20C operates at 45 inches per

second, and has the capability of recording in three densities, 200, 556, and 800 bpi; maximum transfer rate is,
therefore, 800 x 45 = 36,000 six-bit characters per second. Standard seven-channel IBM-compatible tape format
is used.

IBM-compatible

nine-channel

version

the

TU20C,

designated

TU20B,

also

available;

remaining

characteristics of the TU20B are essentially the same as those for the TU20C.

Operation
Either version of the Tape Transport (TU20C, TU20B) may be operated in the local mode from the control panel

mode from the PDP-12. Local operation is selected by depressing the front panel OFF LINE
FORWARD, RESET, REVERSE, and REWIND switches to become operable. If
either the FORWARD, REVERSE, or REWIND control is depressed, the tape moves in the specified direction until
or in the remote

control; this action causes the

RESET is depressed, the beginning of the tape is detected for rewind, or the end of the tape is detected for
FORWARD. Activating the front panel ON-LINE control places the Tape Transport in the remote mode, wherein it
is controlled

by the PDP-12; the Tape Transport must, however, be selected by the TC58 Tape Control.

Switches

The following switches are located on the control panel:
Function

Switch

POWER

ON LINE

Applies power to the tape transport.

Selects

programmed (remote) operation by the

computer.

OFF LINE

Selects local operation by the control panel.

FWD

In local operation, spaces the tape in the forward
direction.

REV

In local operation, spaces the tape in the reverse
direction.

REWIND

In local operation, rewinds the tape at high speed.

RESET

In local operation, terminates the space forward,

space reverse, or rewind operation.

LOAD

Loads the tape into the tape column.

Unit Select Switch

Selects the tape transport unit by number. This
number is used in the program to select the tape

transport.

6-56

Indicators

The following indicators are provided on the control panel:
Indicators

Meaning When Illuminated

SELECT

The tape transport is selected by the tape control
(or program).

READY

The tape transport

ready

(vacuum on, and

settle-down delay complete), no motion.

LOAD POINT

The tape is at load point.

END POINT

The tape is at end point (end of tape).

WRITE LOCK

The write lock-out ring is missing from the tape
reel, which prevents the write function.

WRITE STATUS

The program has enabled the write function in the
tape transport.

This transport is a 9- track type.

This transport is a 7-track type.

REWIND

The tape transport is in the rewind operation.

LOAD

The vacuum is on and the tape is loaded into the
vacuum columns.

REV

Reverse operation is specified.

RESET

No motion

(forward,

reverse,

rewind)

specified.

6.4.3

FWD

Forward motion of the tape is specified.

LOCAL

Local operation by the control panel.

REMOTE

Remote operation by the computer.

POWER

Power is applied to the tape transport.

LINCtape Option TC12-F

The TC12-F option (prewired) in conjunction with the PRTC12-F program extends the TCI 2 LINCtape control to
read and write DECtapes formatted on the PDP-8, PDP-9, PDP-10, and PDP-15 computers.

standard PDP- 1 2 A system. Tape units

It will

operate on a

through 7 are selectable under program control. Description document

DC-12-YIYA-D explains the differences between the LINCtape and DECtape formats and describes the PRTC12-F
program.

6-57

Data is transferred between the tapes and the computer on the I/O bus. Two status flags enable the program to
identify the information on tape. The BLOCK flag is set, indicating that a block mark was encountered on tape and
the Block Number (BN) is in the tape accumulator. This number is then read into the PDP-12 AC and is processed
to determine if the desired block has been found, or to initiate the necessary adjustments to access the desired
block.

The WORD flag is set after four Unes of data have been assembled and are ready to store in memory when reading
from the tape. When writing data on tapes, the flag indicates that a 12-bit word has been written on tape and the
control is ready to accept another word from the computer.

The system program PRTC12-F no. DC-12-YIYA-PB for this option is contained on the standard LAP6-DIAL
system tape.

NOTE
This option does not permit the user to execute tape operations using DEC tape
instruction subroutines.

Instructions

lOT 6152
Octal code:

6152

Event time:

Execution time:

4.25 MS

Operation:

As shown below:

AC Bit
5(1)

Clear Block FF

5(1)

Set Backward

6(1)

Select unit 1

7(1)

Set forward

9(1)
10(1)

Set motion
Select DECtape

& ACj

SWD 0457

Skip on word flag

STB 0414

Skip on block flag

TAPE PRESET
TAPE PRESET
TAPE PRESET

6-58

Function

-^ DECtape write
-> Motion

Deselect DECtape

write

6.5

LINE PRINTERS

6.5.1

Line Printer and Control, Type LP12

The Line Printer and Control Type LP 12 allows the PDP-12 computer to output data at up to 600 lines per minute
(depending upon which printer is used). Either the Mohawk Data Sciences Model 4000 or 5000 series line printers
can be used.

Model

Lines Per Minute

Columns Per Line

4000
5000

up to 300
up to 600

132

Total number of characters available: 64

A 6-bit line printer code

loaded into the LP12 buffer from ACg-i j with the instruction Load Printer Buffer

(LLB). The Print (LPR) instruction causes the hneprinter to print the characters in the lineprinter buffer. After the
buffer is filled the LPR instruction should be given to print the contents of the buffer. Two status flags indicate the

The Error Flag is set when a printer instruction is given if an error status exists, such as
power off, paper supply low, or control circuits not reset. The Done Flag is set by a BUFF AVAILABLE pulse,
generated by the line printer, after the following lOT instructions are given: Load Printer Buffer (LLB) 6654,
Load Format Register and Print (LPR) 6664 and Clear Printer Buffer (LCB) 6662. The BUFF AVAILABLE pulse

line printer conditions.

indicates that the line printer buffer is ready to receive another character or the lineprinter is ready to print a line.

The Done Flag is cleared by the lOT instruction Clear Line Printer Flags (LCF) 6652 or the status of the Done Flag
can be checked by the lOT instructions. Skip on Line Printer Done Flag (LSD) 6661.

A three-bit format register in the Printer is loaded from AC9-1

during a print command. This register selects one

of eight channels of a perforated tape in the printer to control spacing of the paper.

The Print Fhp-Flop is set when the print instruction is given and, when the Print Flip-Flop and the Done Flag are
both set, a program interrupt request is generated, indicating that the printer has finished printing a line. The Print
Flip-Flop can be cleared by an lOT instruction Clear Printer Buffer (LCB). ACg is loaded into the Space Flip-Flop
during a print instruction. If the Space Flip-Flop is set, the paper is advanced according to the selected channel of
the format tape in the line printer. If the Space Flip-Flop is clear, the paper advance is inhibited.

LSE

Skip on Line Printer Error Flag

Octal code:

665

Event time:

Execution time:

4.25 /xs

Operation:

The status of the Printer Error Flag is sensed, and, if it is set, the contents of the PC are
incremented by one, skipping the next sequential instruction.
If Printer Error Flag = 1 then PC + 1 ^ PC

Symbol:

LCF

Clear Line Printer Flags

Octal code:

6652

Event time

Execution time:

4.25 fis

Operation:

The Line Printer Error and Done Flags are cleared.

Symbol:

-> Line Printer Error Flag

^ Done Flag

6-59

LLB

Load Prin ter Buffer

Octal code:

6654

Event time:

Execution time:

4.25 /xs

Operation:

The contents of AQ-j j are loaded into the Printer Buffer.

Symbol:

AC^-i i ^ Printer Buffer

ACg -> Space Flip Flop

O^AC
LSD

Skip on Line Printer Done Flag

Octal code:

6661

Event time:

Execution time:

4.25 /lis

Operation:

The status of the Line Printer Done Flag is sensed, and, if it is set, the contents of the PC are

Symbol:

incremented by one, skipping the next sequential instruction.
If Line Printer Flag = 1 then PC + 1 -^ PC

L CB

Clear Prin ter Buffer

Octal code:

6662

Event time:

Execution time:

4.25 us

Operation:

The Printer Buffer is cleared.

^ Printer Buffer

Symbol:

LPR

Load Format Register and Print Character

Octal code:

6664

Event time:

Execution time:

4.25 jUS

Operation:

The contents of AC9-1 j

are loaded into the line printer format register and the line contained

in the printer buffer is printed.

Paper is advanced in accordance with the selected channel of

the format tape.

Symbol:

C (AC9-1 ) -> Format Register
ACg -^ Space Flip-Flop
1

Print Line

0->AC

6.5.2 Line Printer and Control, Type LP08

The LP08 Line Printer interface allows control of the four models of Data Products Line Printers by the PDP-12 or
bus PDP-8 family of computers through the use of lOT instructions. The printers are available in
80-column and 132-column printing widths with either a 64 or 96 visible character set. The device select code for

positive

theLP08is668.
The 80-column

printer contains a 20-character (24-character in

132 column) buffer and prints 20 characters

simultaneously when either the character buffer is full or a format control character (carriage return, paper feed,

form feed) instruction is given. A paper feed or form feed command must be given to move the paper at the end of
a line or overprinting will result. Characters and commands are given by loading the AC with the appropriate setting
derived from the LP08 Character Code Chart (Appendix F-4) and issuing the lOT 6664 (LPC).

6-60

The three format commands in addition to initiating the print cycle are:
a.

Paper Feed - Advances the paper one line. The perforation between pages is automatic.

Carnage Return - Returns the print position to the leftmost edge of the paper.

Form Feed - Advances the paper to a new page. Nonvisible characters are decoded as spaces if they are not

control characters.

Instructions

LSF

Skip on Demand Character Flag

Octal code:

6661

Operation:

If printer is

ready for the next character, this flag accounts for timing required to store

character in buffer, print from buffer, and advance paper.

Symbol:

LCF

If Character Flag =

then PC + 1 ^ PC

Clear Character Flag

Octal code:

Operation:

6662
The line printer character flag is cleared.
-^ Character Flag.

Symbol:

LSR

1 ,

Skip on Not Ready

Octal code:

6663

Operation:

The next instruction is skipped if the error status flag is set. Such errors as out-of-paper, drum
gate open, paper jam, etc. will set error status flag.

Symbol:

If Error Flag =

1 ,

then PC + 1 -^ PC

LLC Load Buffer from AC

Operation:

6664
Load the character into the Print Buffer and print if buffer is full or character was a control
function. This instruction does not clear the AC.

Symbol:

AC -> Print Buffer

Octal code:

LIN'

Se t Program In terrup ts Enable

Octal code:
Operation:

6665
Sets the device interrupt flip-flop to initiate program interrupt when the demand character flag
is set

Symbol:

or an error condition exists.

-> Int Enable

LPC Load Buffer from AC and Clear Flag

Operation:

6666
The print buffer is loaded from the
cbmbination of LCF and LLC.

Symbol:

Octal code:

LCP

->•

Print Buffer,

AC and the character flag is cleared. Microprogram

-^ Character Flag.

Clear Program In terrupt Enable

Octal code:

Operation:

Symbol:

6667
The program interrupt enable is cleared.
-^ Int Enable

6-61

Print rate

80 column model
64 character

356 Lines/minute, columns 1-80

460 Lines/minute, columns 1-60
650 Lines/minute, columns 1-40
1110 Lines/minute, columns 1-20
96 character

253 Lines/minute, columns 1-80

330 Lines/minute, columns 1-60
478 Lines/minute, columns 1-40
843 Lines/minute, columns 1-20
132 column model

64 character

245 Lines/minute, columns 1-132

290 Lines/minute, columns 1-110
356 Lines/minute, columns 1-88
460 Lines/minute, columns 1-66
650 Lines/minute, columns 1-44
1110 Lines/minute, columns 1-22
96 character

173 Lines/minute, columns 1-132

205 Lines/minute, columns 1-110

253 Lines/minute, columns 1-88
330 Lines/minute, columns 1-66
478 Lines/minute, columns 1-44
843 Lines/minute, columns 1-22

Format

Top-of-form

control,

single

line

advance, and perforation step over.

Paper Feed

One pair of pin-feed tractors for
1/2 inch hole center, edge-punched

Adjustable for any paper
width from 4 inches to 9-7/8 inches
paper.

on the 80 column model; or

maximum width of 14-7/8 inches
for the 132 column model.

Paper slew speed

6-62

13 inches per second

6.6

CARD READERS

6.6.1

Card Reader and Control, Type CR12

The Card Reader and Control Type CR12 reads 12-row, 80-column punched cards at a nominal rate of 200 cards
per minute by a photoelectric process. Cards are read by column, beginning with column 1 One select instruction
starts the card moving past the read station. Once a card is in motion, all 80 columns are read. Column information
can be read in one of two program selectable modes, alphanumeric or binary. In the alphanumeric mode, the 12
information bits in one column are automatically decoded and transferred into the least significant half of the AC
as a 6-bit Hollerith code. In the binary mode, the 1 2 bits of a column are transferred directly into the AC so that
A punched hole is
the top row (12) is transferred into ACqo and the bottom row (9) is transferred into ACi
.

interpreted as a binary 1 , and the absence of a hole is interpreted as a binary 0.

Three program flags indicate card reader conditions. The data ready flag sets and a program interrupt is requested

when a column of information is ready to be transferred into the AC. A read alphanumeric or read binary
instruction

must be issued within 1.4 milliseconds after the data ready flag is set to prevent data loss. The card

done flag is set and a program interrupt is requested when the card leaves the read station. A new select instruction
must be issued immediately after this flag is set to keep the reader operating at maximum speed. Sensing of this flag
can eliminate the need for counting columns or, combined with column counting, can provide a check for data loss.
The reader-not-ready flag can be sensed by a skip instruction to provide an indication of card reader power off,
pick failure, a dark check indication, a stacker failure, hopper empty, stacker full. Sync failure, or light check
indication. When the flag is set, the reader cannot be selected and select instructions are ignored. The
reader-not-ready flag is not connected to the program interrupt facility, and cannot be cleared under program
control. Manual operation is required to clear the reader-not-ready flag. Instructions for the CR12 are:

RCSF

Skip on Data Ready

Octal code:

6631

Event time:

Execution time:

4.25 MS

Operation:

The status of the data ready flag is sensed, and if it is set (indicating information for one card
column is ready to be read) the contents of the PC are incremented by one skipping the next
sequential instruction.
If Data Ready Flag =

Symbol:

R CRA

1 ,

then PC + 1

^ PC

R ead A Iphan u meric

Octal code:

6632

Event time:

Execution time:

4.25 jlis

Operation:

The 6-bit Hollerith code for the 12 bits of a card column is transferred into AC^

and the

data ready flag is cleared.

Symbol:

ACg-i V Hollerith^ ACg-i i
^ Data Ready Flag
i

RCRB Read Binary
Octal code:

6634

Event time:

Execution time:

4.25 MS

Operation:

The

12-bit binary

code for a card column is transferred directly into the AC, and the data

ready flag is cleared. Information from the card column is transferred into the AC so that card

Symbol:

rows 12, 11, and enter ACo-a and card rows 1 through 9 enter AC3.1 j respectively.
^ Data Ready Flag

6-63

RCSD

Skip on Card Done Flag

6671

Octal code:

Event time:
Execution time

1
:

4.25 jus

The status of the card done flag is sensed, and if it is set (indicating that the card has passed

Operation:

the read station) the contents of the PC are incremented, skipping the next instruction.
If Card Done Flag =

Symbol:

RCSE

1 ,

then PC + 1 -^ PC

Select Card Reader and Skip if Ready

Octal code:

6672

Event time:

Execution time:

4.25 MS

Operation:

The status of the card reader flag is sensed and if the reader is ready, the PC is incremented
skipping the next sequential instruction, a card

started

toward the read station from the

input hopper, and the card done flag is cleared.
If Reader Ready Flag =

Symbol:

1 ,

then PC + 1 ->• PC

-^ Card Done Flag

RCRD

Clear Card Done Flag

Octal code:

6674

Event time:

Execution time:

4.25 jus

Operation:

The card done flag is cleared. This instruction allov/s a program to stop reading at any point in
the card deck.
-> Card Done Flag

Symbol:

A logical instruction sequence to read cards is:
START,

RCSE
JMP NOT RDY

/START CARD MOTION AND SKIP IF READY
/JUMP TO SUBROUTINE THAT TYPES OUT
/"CARD READER MANUAL INTERVENTION
/REQUIRED" OR HALTS

NEXT,

RCSF
JMP DONE

/DATA READY?

RCRA or
RCRB
DCA STR

/YES. READ ONE CHARACTER OR ONE

RCSD
JMP NEXT
JMP OUT

/END OF CARD?

DONE,

/NO. CHECK FOR END OF CARD

/COLUMN AND CLEAR DATA READY FLAG
/STORE DATA

/NO, READ NEXT COLUMN
/YES, JUMP TO SUBROUTINE THAT CHECKS

/CARD COUNT OR REPEATS AT START FOR
/NEXT CARD

The CRl 2 does not perform validity checking, although a programmed validity check can be made by reading each
card column in both the alphanumeric and binary mode (within the 1.4 miUisecond time limitation), then
performing a comparison check.

The following discussion and controls and indicators deal with the General Design Industries (GDI) Model 100 card
reader. Other card readers can be used and will have similar controls and indicators.

6-64

Before commencing a card reading program, load the input hopper with cards and press Motor Start and Read Start

pushbuttons. The functions of the manual controls and indicators are as follows (as they appear from left to right):

Function

Control or Indicator

A - POWER switch

On/Off

toggle

Applies power to

switch.

circuits

all

except drive motor.

B - MOTOR START

Momentary action pushbutton, with separate indicator.
Applies power to main drive motor. Motor start is also
used as a reset to clear error indicators, and therefore
will

not operate

there

an unremedied condition

such as:

Input hopper is empty.

C - READ START

Output hopper is full.
All photo cells are not illuminated.
Internal power supply is not operational.

Momentary action pushbutton, with separate indicator.
Causes ready

line

to go

high, enabling card reading

under control of the external read instructions. If read

command

open

card

reading

begins

Momentary action pushbutton with

indicator.

Stops

high,

immediately at full rated speed.

D - READ STOP

card reading if depressed without stopping drive motor.

However,

READ STOP light can indicate a stopped

motor or a ready line low condition.

E - INDICATORS

Several detection circuits are incorporated in the card

Whenever any red indicator lights, the drive
motor is stopped after completion of the current card
reader.

cycle.

PICK FAIL Indicator

Lights when a card fails to enter the read station after

two successive pick attempts.

DARK CHECK Indicator

After the card enters the read station, a check is made at
the hypothetical 0th and 8 1 st hole positions to be sure
all

photocells are dark.

indicator

lights

and

data

not,

the

outputs

DARK CHECK
are

immediately

inhibited.

STACKER FAIL Indicator

When three cards have passed the read station and none
have been stacked, a STACK FAIL is indicated. Prevents
more than three cards from being in the track at once.

HOPPER EMPTY Indicator

Indicates input hopper is empty.

STACKER FULL Indicator

When approximately 400

cards

are

the

stacker

hopper, indicator light lights.

6-65

SYNC FAIL is indicated if the sync signal is lost.

SYNC FAIL Indicator

Internal timing signals are derived

from an oscillator

which is synced to the track speed.
7.

LIGHT CHECK INDICATOR

The photocells must always be
during

the

time

a card

illuminated

being read.

except

The LIGHT

CHECK detector is inhibited each time a card enters the
read station until position (count oO 84 is reached. If a
card fails to leave the read station by this time, a LIGHT

CHECK is indicated.

6.6.2 Optical Mark Card Reader Type

CM 12

The GDI Model 100-MS is an optical-mark card reader that reads (12-row Hollerith) reflective data cards of various
format designs at a rate of up to 200 cards per minute by a photoelectric process. Cards are read column by
column, beginning with column 1. A single select instruction will cause the reader to feed and read a card. Once a
card is in motion, all columns are read. Column information is read in one of two program-selectable modes,
alphanumeric or binary. In the alphanumeric mode, the 12 information bits in one column are automatically

decoded and transferred into the least significant half of the AC as a 6-bit Hollerith code. In binary mode, all 1

column are transferred directly into the AC so that the top row (12) is transferred into ACqo and the
bottom row (9) is transferred into ACj j A punched hole or a nonreflective spot (either nonreflective ink or No. 2
bits of a

pencil) is interpreted as a binary 1

and the absence of a hole or reflective spot is interpreted as a binary 0.

Instructions

The instruction set associated with the optical mark reader is identical to that of the CR12 in Paragraph 6.6. 1.
Characteristics

Size:

The complete unit is 14 in. wide, 18 in. deep, and 18 in. high. The card deck is tilted back at a 45-degree

angle.

Weight:

Complete unit weighs 47 lbs.

Card Rate: 200 per minute.
Input Power:

15 VAC ±10 VAC, 60 ±5 Hz single phase, at 300

VA maximum.

Card Specification: The card reader is designed to read 7-3/8 in. x 3-1/4 in. optical mark cards conforming to the
material and size requirements of EIA Standard RS-292 Media I. Format and printing requirements are specified in

the DEC Mark Sense Card Specification.

Card Capacity: Both input hopper and output stacker hold 450 cards. Cards may be added or removed during
reader operation.

Environment:

Operating:

32° to 120°F ambient

Storage:

30° to 1 50°F ambient

5% to 80% relative humidity

0% to 1 00% relative humidity

6-66

Controls and Indicators

Power Switch: An alternate action rocker-type switch used to apply AC power to the Card Reader.
Start Switch

A momentary pushbutton switch used to condition the unit to read cards. When it is depressed, the

drive motor will start, and any error indicators will be reset if the error has been cleared. When it is released and the

motor has reached operating speed, the reader may accept a "read command' and process cards.

A momentary pushbutton switch used to stop the reader. When it is depressed, the motor will stop;

Stop Switch:

if it is depressed during a time a card is in process, the card

Power:

cycle will be completed before the motor stops.

A green indicator to verify AC power on; mounted next to the POWER switch.

On Line: A green indicator to verify that the START switch has been depressed and the unit is ready to operate.
Light will remain on until the STOP switch is depressed or an error condition is sensed; mounted next to START
switch.

Cards:

A red indicator to identify an input hopper empty or an output stacker full condition.

Feed Error:

A red indicator to identify when a card has not been fed from the input hopper to the read station at

the end of a feed cycle.

Stacker Error:

A red indicator to identify when a card has not been properly delivered to the output stacker.

Motion Error:

A red indicator to indicate a card jam in the read station.

L.D. Error:

A red indicator to identify when a Light or Dark Check of the read station was not met.

6-67

6.7

INCREMENTAL PLOTTERS

6.7.1

Incremental Plotter and Control, Type XY12

Calcomp (California Computer Products) Models 563 and 565 available in three step-size models and four models
of the Complot (Houston Instruments) digital plotters can be operated from a Digital Equipment Corporation Type

XY12 Incremental Plotter Control. The characteristics of the recorders are summarized:

Name

Model

Calcomp

Paper Width

Speed

(inches)

(step/minute)

12,000

563

Step Size

.01-in.

.005-in.

.1-mm
18,000

565

.01-in.

.005-in.

.1-mm
Complot

DP-1-1

18,000

DP- 1-5

18,000

.005-in.

DP-1-M2
DP-l-Ml

18,000

.25-mm
.1-mm

.01-in.

The principles of operation are basically the same for each of the recorders. Bidirectional rotary step motors are
employed for both the X and Y axes.
Recording is produced by movement of a pen relative to the surface of the graph paper, with each instruction
causing an incremental step. X-axis deflection is produced by motion of the drum; Y-axis deflection, by motion of
the pen carriage. Instructions are used to raise and lower the pen from the surface of the paper. Each incremental
step can be in any one of eight directions through appropriate combinations of the

recording (discrete points, continuous curves, or symbols)

X and Y axis instructions. All

accomplished by the incremental stepping action of

the paper drum and pen carriage. Front panel controls permit single-step or continuous-step manual operation of
the

drum and carriage, and manual control of the pen solenoid. The recorder and control are connected to the

computer program interrupt and instruction skip facility.
Instructions for the recorder and control are:

PLSF

Skip on Plotter Flag

Octal code:

6501

Event time:

Execution time:

4.25 /xs

Operation:

the Plotter Flag is set, the contents of the

sequential instruction is skipped.
If Plotter Flag =

Symbol:

PLCF

1 ,

then PC + 1 ^ PC

Clear Plotter Flag

Octal code:

6502

Event time:

Execution time:

4.25 MS

Operation:

Clear the AC and Plotter Flag

Symbol:

0-^AC

^ Plotter Flag
6-68

PC are incremented by one so that the next

PLPU

Pen Up

Octal code:

6504

Event time:

Execution time:

4.25 jus

Operation:

Raise the plotter pen from the paper surface.

Symbol:

None

PLPR

Pen Right

Octal code:

6511

Event time:

Execution time:

4.25 /xs

Operation:

Move the plotter pen to the right in either the raised or lowered position.
None

Symbol:

PLDU Drum Up
Octal code:

6512

Event time:

Execution time:

4.25 jUS

Operation:

Move the plotter paper drum upward. This instruction can be combined with the PLPR and

PLPD commands.
None

Symbol:

PLDD

Drum Down

Octal code:

6514

Event time:

Execution time:

4.25 jus

Operation:

Move the plotter paper drum downward.
None

Symbol:

PLPL

Pen Left

Octal code:

6521

Event time:

Execution time:

4.25 ^s

Operation:

Move the plotter pen to the left in either the raised or lowered position.
None

Symbol:

PLUD

Drum Up

Octal code:

6522

Event time:

Execution time:

4.25 )lis

Operation:

Move the plotter paper drum upward. This instruction is similar to the 65 12 instruction except
that it can be combined with the PLPL or PLPD instructions.

Symbol:

None

6-69

PLPD

Pen Down

Octal code:

6524

Event time:

Execution time:

4.25 ius

Operation:

Lower plotter pen to the surface of the paper.
None

Symbol:

Program sequence assumes that the end location is known at the start of a routine since there is no means of
specifying an absolute pen location in an incremental plotter. Pen location can be preset by the manual controls on

the recorder. During the subroutine, the PDP- 1 2 can track the location of the pen on the paper by counting the
instructions that increment position of the pen and the drum.

6-70

6.8

PAPER TAPE

6.8.1

High-Speed Paper-Tape Punch and Reader, Type PC12

The High-Speed Paper-Tape Punch and Reader Type PCI 2 provides the user with a faster means of inputting or
outputting information from paper tape to the PDP-12 than that provided by the standard Teletype tape
reader/punch. The PC 12 is functionally a PP12, ffigh Speed Paper Tape Punch, and a PR 12, High Speed Paper Tape
Reader, configured mechanically in the same unit. The operating characteristics are discussed in the following
paragraphs.
6.8.2 High-Speed Paper-Tape Punch, Type PP12

The High-Speed Paper-Tape Punch option Type PP12 consists of a PC05-P paper-tape punch that perforates 8-hole
fanfold paper-tape at a rate of 50 characters per second. Information to be punched in tape is loaded in an 8-bit
punch buffer (PB) from AC4-1 1 The punch flag is set at the completion of the punching action, signaling that new
information may be transferred into the punch buffer and punching may be initiated. The control circuitry for this
.

device is located in the BA12 Peripheral Expander. The punch flag is as described for the Teletype unit. The punch
instructions are:

PSF

Skip on Punch Flag

Octal code:

6021

Event time:

Execution time:

4.25 //s

Operation:

The punch flag is sensed, and, if it is set, the contents of the PC are incremented by one,
skipping the next sequential instruction.

Symbol:

PCF

If Punch Flag =

1 ,

the PC -i- 1

^ PC

Clear Punch Flag

Octal code:

6022

Event time:

Execution time:

4.25 /is

Operation:

The punch flag and the punch buffer are both cleared in preparation for receiving a new
character from the computer.
^ Punch Flag, PB

Symbol:

PPC

Load Punch Buffer and Punch Character

Octal code:

6024

Event time:

Execution time:

4.25 jus

Operation:

An 8-bit character is transferred from AC4-1

into the punch buffer, and then the character is

punched. This instruction does not clear the punch flag or the punch buffer.

Symbol:

PLS

AC4.i , ^PB -^PB

Load Punch Buffer Sequence

Octal code:

6026

Event time:

2,3

Execution time:

4.25 jus

Operation:

The punch flag and punch buffer are both cleared, the contents AC4-1 are transferred into
the punch buffer, the character in the PB is punched in tape, and the punch flag is set when
the operation is completed. Combines PCF and PPC.
1

^ Punch Flag, PB

Symbol:

AC4-, 1 ^ PB
1

-> Punch Flag when done

6-71

A program sequence loop to punch characters when the punch buffer is "free" can be written as follows:
FREE,

/SKIP WHEN FREE

PSF

JMP FREE

/LOAD PB FROM AC AND PUNCH CHARACTER

PLS

JMP FREE
6.8.3

High-Speed Paper-Tape Reader, Type PR 12

The High-Speed Paper-Tape Reader (PC05-R) option Type PR 12 senses data in a 8-hole perforated-paper tape
(unoiled) photoelectrically at 300 characters per second. The reader control requests reader movement, transfers
data from the reader into the reader buffer (RB), and signals the computer when incoming data is present. Reader
tape movement is started by clearing the Reader Flag. Data is assembled into the Reader Buffer from the
perforated tape. The Reader Buffer is transferred into AC4-11 under program control. The Reader Flag is
connected to the program interrupt and instruction skip faciUties, and is cleared by lOT pulses. Control circuitry
for this device is located in the BA12 Peripheral Expander. Computer instructions for the reader are:

RSF

Skip on Reader Flag
601

Octal code:

Event time:

Execution time:

4.25 us

Operation:

The status of the Reader Flag is sensed, and, if it is set, the contents of the PC are incremented
by one, skipping the next sequential instruction.
If Reader Flag = 1 then PC + 1 ^ PC

Symbol:

RRB Read Reader Buffer
6012

Octal code:

Event time:

Execution time

2
:

4.25 /is

Operation:

The contents of the reader buffer are transferred into AC4-1
This instruction does not clear the AC.

Symbol:

RB V AC4.1 ^ AC4-1

and the Reader Flag is cleared.

-^ Reader Flag

RFC

Reader Fetch Character

Octal code:

6014

Event time:

Execution time:

4.25 jus

Operation:

The Reader Flag and the reader buffer are both cleared. A character is loaded into the reader
buffer from tape, and the Reader Flag is set when this operation is completed.

^ Reader Flag, RB

Symbol:

Tape Data -> RB
1 -^ Reader Flag when done.

A program sequence loop to read characters from perforated tape can be written as follows:
LOOK,

RFC
RSF
JMP LOOK

CLA
RRB
JMP LOOK

6-72

/FETCH CHARACTER FROM TAPE
/SKIP WHEN RB FULL

/LOAD AC FROM RB

6.9

DATA BUFFERS

6.9.1

Data Buffer Type DB12-P,N

The DB12 option is an input/output transfer register, consisting of a 12-bit input bus driver and a 12-bit output
buffer register. The basic logic for this option is contained on an M735 module, which is described in the Logic
Handbook (1970). Three DB12 options are prewired in the BA12 Peripheral Expander. The device select gating and
data lines provide the capability for transferring data into or out of the PDF- 12 accumulator. The user selects a
device code by inserting jumpers in the M921 Device Code Select Jumper module located in row A, slot 19, of the
BA12 Peripheral Expander. Two I/O cables (Flexprint®) terminating in M903 connector modules are provided to
connect the DB12 to the external I/O device. The output register is buffered to provide either positive (0, +3V) or
negative (0, -3V) logic levels. The option designation is DB12-P (positive) or DB12-N (negative).

® Flexprint

is a Registered

Trademark of Sanders Associates Inc.

6-73

6.10

POWER FAIL/RESTART
Power Failure Option, Type KP12

6.10.1

General

The KP12 Power Failure Option protects an operating program upon failure or interruption of the computer's
primary power source. In the event of a power abnormality, a program interrupt is initiated by the KP12 and
enables continued operation of the central processor for

millisecond. During this interval, the interrupt routine

identifies the power low condition as the initiator of the interrupt.

The interrupt routine then stores the contents

of active registers (AC, L, MQ, etc) and the program counter in known core memory locations. Upon restoration of

power, the power low flag is cleared and a routine in the 8 mode beginning at address OOOOg starts automatically,
restoring the contents of the active registers and the program counter, and then continues the interrupted program.

Operation

A manual RESTART switch enables or disables the automatic restart operation upon restoration of primary power.
When it is ON (down), the program counter is cleared and a signal which simulates the console START key (RCL

START PC) is produced 200 milUseconds after power conditions become satisfactory. Operation is restarted
(always in the 8 mode) by executing the instruction contained in address OOOOg

;

this instruction is a

JMP to the

starting address of a subroutine which restores the contents of the active registers and the program counter to the

conditions that existed prior to the power low interrupt. The 200-millisecond delay assures that slow mechanical
devices, such as Teletype equipment, have completed any previous operation before the program is resumed.

When the RESTART switch is OFF (up), the power low flag is cleared upon the return of normal power
conditions, but the program must be manually restarted, possibly after resetting peripheral equipment.

Programming

SPL

Skip on Power Low

Octal code:

6102

Event time:

Execution time:

4.25 /xs

Operation:

The condition of the power low flag is sampled; if set (indicating a power failure has occurred),
the contents of the PC are incremented by one, skipping the next sequential instruction.

Symbol:

If Power

Low Flag = 1

then PC + 1 -^ PC

Figures 6-9 and 6-10 illustrate the Automatic Restart Program Events and Typical Power Failure Program Service

Routine, respectively.

6-74

ENTER DEVICE
"SEARCH"
SUBROUTINE

POWER FAIL SUBROUTINE NOT ENTERED
THE REGISTER CONTENTS ARE NOT
SAVED PROGRAM. HAS TO BE MANUALLY
RESTARTED FROM BEGINNING.

YES

THE PROGRAM CONTINUES FLAG CHECKING.
NOTE WITH REAL TIME APPLICATIONS,
THE TIME REQUIRED FOR
CHECKING REDUCES THE TIME
FOR THE REAL TIME SERVICE
SUBROUTINE POSITION KP12
INQUIRY NEAR THE BEGINNING.

STOP THE NEXT SEQUENTIAL
INSTRUCTION AND ENTER
KPI2 SERVICE ROUTINE
/INTERRUPT WAS CAUSED BY POWER LOSS FLAG
/SAVE AC
/GET LINK
/SAVE LINK
/GET MO

DCA AC
RAR
DCA LINK

MQA
DCAMQ

/SAVE MQ
/GET PC
/SAVE PC
/GET RESTART JUMP INSTRUCTION
/DEPOSIT RESTART INSTRUCTION IN

TAD OOOOo
°
DCA PC
TAD RESTRT X
DCA OOOOa

OOOOg

HLT

Figure 6-9. Automatic Restart Program Events

PROGRAM MUST BE RESTARTED
MANUALLY.
UPON
RESTART, THE
INSTRUCTION IN
LOCATION OOOOs
IS

PERFORMED

LOCATION
0/ JMP X

LOCATION X CONTAINS THE
BEGINNING OF THE RESTART
PROGRAM, WHICH RESTORES
THE CONTENTS OF LINK,AC.PC
AND ANY OTHER INFORMATION
STORED BY PWR FAIL SERVICE
SUBROUTINE. CONTINUATION
OF THE PROGRAM
AUTOMATICALLY OCCURS^

CONTINUE
MAIN PROGRAM

)

Figure 6- 1 0. Typical Power Failure Program Service Routine

6-75

6.11

ANALOG-TO-DIGITAL

6.1 1 .1

General Purpose Multiplexed Analog-to-Digital Converter System, Type AFOl-A

The Type AFOl-A General-Purpose Multiplexed Analog-to-Digital Converter combines a versatile, multipurpose
converter with a multiplexer to provide a fast, automatic, multichannel scanning and conversion capability.

It is

intended for use in systems that sample and process analog data from sensors or other external signal sources at
high rates of speed. The

AFOl-A is used when greater accuracy than that provided by the standard AD12 A-D

converter is needed. The Type AFOl-A option is used with the PDP-12 to multiplex up to 64 analog signals and to
convert the signals to binary numbers. Analog data on each of 64 channels can be accepted and converted into
12-bit digital numbers 420 times per second.*

Switching point accuracy in this instance is 99.975 percent, with an additional quantization error of half the analog
value of the least significant bit (LSB).

A/D Converter Specifications
The Type AFOl-A has a successive approximation converter that measures a

to -10 volt analog input signal and

provides a binary output indication of the amplitude of the input signal. The characteristics of the A/D converter
are as follows:

Accuracy and Conversion Times:

See Table 6-6 (includes all linearity and temperature errors)

Converter Recovery Time:

Zero.

to -lOV at 10 megohms standard. Input scaling may be

Input and Input Impedance:

specified using the amphfier or sample and hold options
(see Table 6-5).

Input Loading:

±1 juA and 1 25 pf for

Output:

Binary

number of 6

to - 1 OV input signal.

bits,

with

negative

numbers

represented in two's complement notation. A OV input gives a

40008; a -5V input a OOOOg and a -lOV (minus 1 LSB) input
number.

gives 37778

Provision

made for using the Type A400 Sample and Hold Amplifier (AH02 option) between the multiplexer

output and A/D converter input to reduce the effective aperture to less than 150 ns. The Type A400 may also be
used to scale the signal input to accept ±10V, or

to +10V. The Type A200 amplifier (AH03 option) may be

substituted for the Type A400 to accomplish the same signal scaling without reducing the effective aperture. Both

the AH02 and AH03 options may be used to obtain high input impedance and small aperture. (See Table 6-4.)

Multiplexer Specifications

The multiplexer can include from
high-speed, insulated gate

16 Type

A121 Switch Modules. Each module contains four single-pole,

FET switches with appropriate gating. The Type A121 Switches are arranged as a

64-channel group of series-switching single-pole switches with a separate continuous ground wire for each signal
input. The switched signal input wire and the continuous ground for each channel are run as twisted pairs to the

input connectors mounted on the rear panel. The continuous grounds for all channels are terminated at the high
quality ground of the AFOl-A System. Specifications (measured at input connector) are as follows:

Conversion rate

= [(35 + 2) (10 - 6) (64)] -1 = 420 cycles/sec.
= [(9 + 2) (10- 6) (64)] - 1

6-76

=1420 cycles/sec.

Input Operating Signal Voltages:

+10Vto-10V

Current:

On Resistance

500 ohm (max)

Voltage Offset

1/iV

"Off Leakage"

10 nA(max)

Capacitance

10 pf (max)

Speed
1
1

0% Input to within
LSB of output

2 ms

The time required to switch from one channel to another is 2 /us

Operate Time

to within

LSB of the final voltage. This time is preset within

the control and starts when a set or index command is received.

Table 6-5. Input Signal Scaling

Input
Configuration

Gain

Input

Impedance
(ohms)

Signal

10 meg.

40008
OOOOg

-10

10 meg.

37778

lOK
lOK
lOK

37778
OOOOg

lOK
lOK
lOK

37778

40008
OOOOg

10 meg.

-1

Hold

-1

-5

Sample &

-1/2

+10

Hold

-1/2

Amplifier

-1/2

-10

-1-1

-5

> 100 meg.
> 100 meg.
> 100 meg.

+ 1/2

+10

>100 meg.

-10

> 100 meg.
> 100 meg.

Amplifier

+1/2
+ 1/2

and Sample

+5+10
OorO

&Hold

-1/2

-5

Amplifier

-1

Option
Designation

-5

Standard

Sample &

Input

Output

> 100 meg.
> 100 meg.
> 100 meg.

-10

STD

AH02

40008

OOOOg

AH02

40008

AH03

37778

AH03

37778
37778
OOOOg

40008

AH03
&
AH02

NOTE
Unipolar signals (0 to +5, or

to +10v) may also be specified with either the AH03

or AH02 pption.

6-77

System Operation

The Type AFO 1 System may be operated in either the random or sequential address modes. In the random address
mode, the control routes the analog signal from any selected channel to the A/D converter input. In the sequential
address mode, the multiplexer control advances its channel address by one each time an index instruction is
received. After indexing through the maximum number of channels implemented, the address is returned to 0.

The multiplexer switch settling time is preset vi^ithin the control to initiate the conversion process automatically
after a channel has been selected in either the random or sequential address mode. A separate A/D Convert I/O
Transfer instruction may also initiate one or more conversions on a currently selected channel.

A/D conversion times are increased by 2 microseconds when multiplexer channels are switched to allow for settling
time of the analog signal at the multiplexer output. Conversion times are increased an additional 3 microseconds

when AH03 is used. These items are added to the conversion times shown in Table 6-6 under selected channel
conversion time, which is the only time required for each successive conversion on a selected channel.

When the Type AH02 Sample and Hold option is required, the multiplexer switch settling time and the sample and
hold acquisition time are overlapped. The total conversion and switching time is increased by 10 microseconds.
(See A400 specifications.)

A/D CONVERTER/MULTIPLEXER CONTROLS
Designation

WORD LENGTH:

Function
Rotary switch selects digital word length or conversion accuracy. Refer to
Table 6-6 for corresponding conversion times.

POWER ON/OFF:

Applies 117 Vac power to internal power supplies.

CLR:

Clears multiplexer channel-address registers; i.e., selects analog channel

for

conversion.

INDEX:

Advances multiplexer channel-address

by one each time

depressed, enabling manual addressing of channels (up to 64) in sequential

mode. Returns address to zero when maximum value is reached.

ADC:

Starts conversion of the analog voltage on the selected channel to a binary

number when depressed.

A/D CONVERTER:

Indicates binary contents of A/D converter register.

MULTIPLEXER:

Indicates binary contents of multiplexer channel-address register.

POWER:

Indicates ON/OFF status.

Programming

Programmed control of the converter/multiplexer by the POP- 12 is accomplished with the lOT instructions listed
below. PDP-12 selects the converter/multiplexer with two device selection codes, SSg and 548, depending upon
whether conversion or multiplexing function is being selected. The converter/multiplexer interprets the device
selection code to enable execution of the lOP command pulse generated by the lOT instruction.

6-78

Table 6-6. System Conversion Characteristics

Random
Selected
or

Channel
Sequential

(A/D)

Max
Word Length

Switching

(No. of Bits)

Point

(MPX & A/D)

AH03

AH02

MPX

AH02
AH03

A/D

MPX & A/D
Conversion

Conversion

Time

ifJLS)**

(//s)**

(fXS)**

(/iS)**

ins)**

9.0

11.0(9.5)

14.0(11.0)

19.0(14.0)

21.0(18.0)
22.5(19.5)

Error*

±1.6%
±0.8%
±0.4%
±0.2%
±0.1%
±0.05%
±0.025%

6
7
8
9

10
11

10.5

12.5(11.0)

15.5(12.5)

20.5(15.5)

12.0

14.0(12.5)

17.0(14.0)

22.0(17.0)

24.0(21.0)

13.5

15.5(14.0)

18.5(15.5)

23.5(18.5)

25.5 (22.5)

18.0

20.0(18.5)

23.0(20.0)

28.0(23.0)

30.0 (27.0)

25.0

27.0

30.0

35.0

37.0

35.0

37.0

40.0

45.0

47.0

* ± 1 /2 LSB for quantizing error.

**If system is to operate at less than 10 bits continuously, conversion times may be reduced to times shown in
parentheses.

ADSF

Skip on A-D Flag

Octal code:

6531

Event time:

Execution time:

4.25 us

Operation:

The A-D converter flag is sensed, and if it is set (indicating that the conversion is complete) the
contents of the PC are incremented by one, skipping the next instruction.
If A-D Flag = 1 then PC + 1 ^ PC

Symbol:

ADCV

Convert Analog Voltage to Digital Value

Octal code:

6532

Event time:

Execution time:

This time is a function of the accuracy and word length switch setting as listed in Table 6-6.

Operation:

The A-D converter flag is cleared, the analog input voltage is converted to a digital value, and
then the A-D converter flag is set. The number of binary bits in the digital-value word and the
accuracy of the word are determined by the preset switch position.
-^ A-D Flag at start of conversion, then

Symbol:
1

ADRB

-^ A-D Flag when conversion is done.

Read A-D Converter Buffer

Octal code:

6534

Event time:

Execution time:

4.25 MS

Operation:

The converted number contained in the converter buffer (ADCB) is transferred into the AC
left justified; unused bits of the AC are left in a clear state, and the A-D converter flag is
cleared. This instruction must be preceded by a CLA instruction.

Symbol:

ADCB ^ AC
-> A-D Converter Flag

6-79

ADCC

Clear Multiplexer Channel

Octal code:

6541

Event time:

Execution time:

4.25 /lis

Operation:

The channel address register (CAR) of the multiplexer is cleared in preparation for setting of a
new channel.

Symbol:

0->CAR

ADSC

Set Multiplexer Channel

Octal code:

6542

Event time:

Execution time:

4.25 /is

Operation:

The channel address register of the multiplexer is set to the channel specified by AC5-1
maximum of 64 single-ended input channels can be used.

ADIC

Increment Multiplexer Channel

Octal code:

6544

Event time:

Execution time:

4.25 jus

Operation:

The contents of the channel address register of the multiplexer are incremented by one. If the

maximum address is contained in the register when this instruction is given, the minimum
address (00) is selected.

Symbol:

CAR + ^ CAR
1

The converter/multiplexer may be operated by the program in either the random or sequential addressing mode. In
the random addressing mode, the analog channel is selected arbitrarily by the program for digitizing and the
resultant binary word is read into the accumulator. A sample program for the random addressing mode is as
follows:

TAD ADDR

/YES-GET CHANNEL ADDRESS

ADSC

/AND SEND TO MULTIPLEXER
/CONVERT A TO D
/CLEAR AC

ADCV
CLA
ADSF
JMP.-

ADRB

/SKIP ON A/D DONE FLAG

/WAIT FOR FLAG
/AND READ INTO AC

In the sequential address mode, the program advances the multiplexer
each time an analog value is converted and read into the accumulator.

channel-address register to the next channel

Should the converter/multiplexer be operated in the interrupt mode, the computer will be signaled
binary word is ready, enabling the system to use processor time more efficiently.

6-80

each tune that a

Amplifier, Sample and Hold Options for AFOl-A

The AH03 consists of a DEC amplifier (part #1505379-10) mounted on an A990 Amplifier Board with appropriate
scaling networks and gain trim and balance potentiometers.

Open loop gain

2x 10^

Rated output voltage

(@ 10 ma) ±1 IV

Frequency response
Unity Gain, small signal

10 MHz

Full output voltage

Slewing rate

IOOV/ms

Overload recovery

50 ms

Input voltage offset

Avg vs temp
Vs supply voltage
Vs time
Input current

Avg vs temp
Vs supply voltage

MHz

Adjustable to O

20MvrC
15/Liv/%
1

Mv/day

50 pAmax
doubles every 10°C

lOpA/%

Input impedance (ohms)

Between inputs

10^'>(5pFshuntc)

Common mode

lO^'' (5pFshuntc)

Input Voltage

Max common mode
Common mode rejection

±15V
±10V
50,OOOV

Power
Voltage

±15 to 16V

Current at rated load

40 ma

A400 (standard gain options)
Acquisition time to 0.01% (full-

Hold inaccuracy (droop)

<12ms
<150ns
<l mv/ms

Temperature coefficient

0.1

Gain (negative)

1.0 or 0.5

scale step)

Aperture time

mv/ms/°C

Input range (volts)

±5.0 ±10.0

Output Impedance

<1 .0 ohm

6-81

6.12

DIGITAL-TO-ANALOG

6. 1 2. 1

Digital-to-Analog Converter, Type AA01-A

The general-purpose Digital-to-Analog Converter Type AAOl-A converts 12-bit binary numbers into analog
voltages. The basic option consists of three channels, each containing a 12-bit digital buffer register and a
digital-to-analog converter (DAC). A common digital input to all three registers is provided by a 12-bit input
channel which receives bussed output connections from the accumulator. Appropriate precision voltage reference
supplies are provided for the converters.

One lOT microinstruction simultaneously selects a channel and transfers a digital number into the selected register.
Each converter operates continuously on the contents of the associated register, providing an analog output
voltage.

Type AAOl-A options can be

specified in a

wide range of basic configurations; e.g., with from one to three

channels, with or without output operational amplifiers, and with internally or externally supplied reference
voltages. Configurations with double buffer registers in each channel are also available.

Each single-buffered channel is operated by a single lOT command. Select codes of 55, 56, and 57 are assigned to
the AAOl-A, making it possible to operate nine single-buffered channels or various configurations of
double-buffered channels. A typical instruction for the AAOl-A is:

DALI

Load Digital-to-Analog Convert 1

Octal code:

6551

Event time:

Execution time:

4.25 /xs

Operation:

The contents of the accumulator are loaded into the digital buffer register of channel 1.

Symbol:

AC-^DACl

6-82

CHAPTER 7

PROGRAM LIBRARY

Because of the dual nature of the PDF- 12, virtually all PDP-8 classic LINC, and LINC-8 programs will run on the
PDF- 12 equipped with the necessary peripherals. The following programs are normally supplied with the PDF- 12,

run on just the PDF- 12 A. There are other programs available from both Digital Equipment
Corporation and from DECUS. These have not been included in the Standard Library. This chapter is divided into

and most

will

four sections: PDF- 12 Programs, FDP-8 Programs,

DECUS Programs,

and Diagnostic Programs. This hst

representative and subject to change. The Digital Program Library and the DECUS Program Library maintain the

current program lists.

7.1

PDP-12 PROGRAMS

The PDP-12 is deUvered to the user complete with an extensive selection of system programs and routines making
the full data processing capability of the new computer immediately available to each user, and eliminating many

commonly experienced initial programming delays.
7.1.1

LAP6-DIAL Display Interactive Assembly Language (DEC-12-SE2D-D)

LAP6-DIAL provides the PDP-12 user with an operating system that includes editing, assembling, and data handling
capabilities. An interactive display permits quick user response; a File Index and Peripheral device Interchange
Program (PIP) facilitate file manipulation. The minimum hardware configuration for using LAP6-DIAL is a 4K
PDP-12B system, (The character editing facility is, however, designed primarily around the use of the AD 12
Analog-to-Digital Converter and Multiplexer for the PDF- 12 A.) In addition, the system will utilize an additional 4K
of memory to improve its efficiency significantly.

The LAP6-DIAL system is provided to the user on LINCtape. Each tape contains a reserved area occupied by
LAP6-DIAL, a working area for temporary storage of user programs, and a file area for permanent storage of user
programs. The LAF6-DIAL area of the tape contains the Editor, Assembly and Utility Programs, and a File Index.

The Index stores the name, starting block number, and length of each stored file. User programs are saved as named
files in the tile area of the system tape. The scope is used as a moving window to view source programs in the
working area. Up to 17 lines with up to 40 characters per line can be displayed at a time on the scope (maximum of
256). In the edit mode, any portion of a program in the Working Area can be displayed by an appropriate locate
request.

A LINCtape containing LAF6-DIAL is designated as the system tape, and is assigned to tape unit 0. Some
operations

may be performed with only one LINCtape containing LAP6-DIAL, but many procedures, such as

assembling programs, require two tapes. Most efficient operation is achieved when both tapes contain LAP6-DIAL.
7-1

On startup the system automatically enters the edit mode. A source program may be typed in via the TTY
keyboard.

The program

will

reside

the

Working Area and

will

displayed

on the

CRT

Display

character-by-character as it is entered. The LAP6-DIAL Editor may be used at this time to add, modify, or delete
characters, lines, or large sections of the program.

A command may also be issued via the TTY keyboard to the

Monitor. When called, the Monitor writes out its buffer pointers and is replaced by the called program. When the

system program operation is completed, the Monitor is automatically called back into core and it retrieves its
buffer pointers.

The Monitor Commands are summarized in the following table. Items in parentheses are optional; if they are
omitted, the user's program that was most recently manipulated is used.

Commands

Functions

Assemble (U = 0, 1

(N,U)
(N,U)

(L, L,)

(N, U)

Assemble & List (U - 0, 1)

Load Binary

(L, L,)

(N, U)

Assemble & Quick List (U = 0, 1)

PS
SB
SP

(L(,L),)

(N,U)

Print Source

N, U(,M[A])

(L, L,) N,

CU)

Display Index

PX
CL

(,U)

Print Index

Save Binary

N, U

Save Program (Source)

U or B, U

Add Program (Source)

Clear Working Area
Peripheral Interchange Program

Exit

X(Y), U

Monitor Command (READS IN
USER PROGRAM FROM FREE AREA)
User's

Legend:

M = Mode (L for LINC or P for PDP-8)

N = File Name
U = Tape Unit

A = Address (5 digits-used only if mode is specified)

L = Line Number

B = Tape Block Number

The assembler processes both LINC mode and 8 mode statements, assembling programs up to 8K in length.
Six-character alphanumeric symbols can be defined; source Ustings, assembly listings, or abbreviated assembly
listings may be optionally obtained on the Teletype or, if provided, the Line Printer. To facilitate the preparation
of system programs and large programs, conditional assembly pseudo-operations are provided along with a facility
to preserve the tag table definitions from one assembly to another assembly (or to several assemblies).

Upon loading, programs may be started automatically in either LINC or 8 mode at any memory location.

A second version of LAP6-DIAL, LAP6-DIAL-MS, provides the user of the PDP- 2 (with 8K of memory and a
1

disk) with a fully-integrated tape-disk system. The additional facihties include:

7-2

Mass storage capabilities to support DF32, RS08, or RK8 disks (or LINCtape).

Monitor commands to clear the Binary Working Area and to merge binary files.

I/O routines to read, write, or move data.

An automatic system built to specialize the system tapefor the user's present configuration.

Increased assembler facilities for processing large programs.

7.1.2 Peripheral Interchange Program (PIP)

The Peripheral Interchange Program provides a flexible means of transferring data among peripheral devices such as
LINCtape, Teletype, High Speed Paper-Tape Reader/Punch, Line Printer, Disk, and Card Reader. Symbolic and
binary files, as well as absolute data, are processed in response to scope-directed operator requests.

QUANDA {DEC-12-FISA-D)

7.1.3

QANDA is a subroutine which allows a user to display textual information on the CRT Display, ask questions of
the viewer, allow editing of the input, and receive answers.

DATAM* (DEC-L8-FDAA-D)

7.1.4

The DATAM program retrieves, displays, and stores individual data blocks from LINCtape and provides the user
with a repertoire of mathematical operations for manipulating this data. These operations include high and low pass
constant, and
filtration, differentiation and integration, attenuation and ampUfication, inversion, addition of a
plotting of a bar graph. The data or resulting waveforms are continuously displayed.

7.1.5

GRAPHA* (DEC-L8-UGAA-D)

The GRAPHA program allows data to be retrieved from LINCtape and displayed, and allows a graph to be
composed for this data, with appropriate lettering and axes. The graph is assembled on the display and the finished
product may be photographed, plotted on an incremental plotter, or saved on LINCtape for future reference.

7.1.6

FRQANA* (DEC-L8-FANA-D)

The FRQANA program performs a frequency analysis of 5 1 2 points of data, and resolves the resulting spectrum
into 64 components. The sine, cosine, and rms spectra are subsequently displayed and can be scaled. A resynthesis
from the spectra can then be performed to provide a comparative display of the original data and the resynthesized
waveform.
7.1.7

MAGSPY (DEC-12-UZSA-D)

The MAGSPY program provides a moving window for scanning data stored on LINCtape. The data is displayed on
the scope and can be scanned at a rate determined by a potentiometer setting. The data is interpreted either as a
binary point plot or as packed ASCII characters depending on a switch setting.
7.1.8

C0MPAR*(DEC-L8-EUCA-D)

The COMPAR program compares contents of specified LINCtape blocks on a word by word basis.
7.1.9

SEARCH* (DEC-L8-EUSA-D)

The SEARCH program performs a search of blocks of LINCtape for a specific word. The user may specify the word
to be searched and a mask of bits for comparison.
7.1.10

CONVERT (DEC-12-ESYB-D)

The CONVERT program is used to convert symbolic text from LAP-4 and LAP-6 manuscripts for compatibihty
with the LAP6-DIAL Assembler.

^LINC-8 Programs.

7-3

7.1.11

MARK 12(DEC-12-YITB-D)

The MARK 12 program is used to format tapes to be used with the PDP-12. Several format options are available
and, by using the subroutines vi'ithin MARK 1 2, the user can generate a tape of arbitrary format.
7.1.12

L8SIM (DEC-12-SnB-D)

The LINC-8 Simulator Trap Processor handles Teletype input and output for LINC-8 and classic LINC programs so
they can be run on the PDP-12 without modifications. It must be loaded into the PDP-12 core memory with any
LINC-8 or classic LINC program which uses the keyboard or the Teleprinter, in order for that program to be run on
the PDP-12.

The trap processor operates by using the PDP-12 Instruction Trap Facility to detect execution of either of the two
LINC-8 Teletype input/output instructions by the user's program. It responds to user's execution of a Teletype
instruction by executing coding to simulate the instruction's LINC-8 or classic LINC effect. After simulation of the
instruction, the trap processor returns control to the user program.

Users may easily adapt the LINC-8 Simulator Trap Processor to handle other devices or for their own purposes.
Explicit instructions for a

number of useful adaptations are provided in this document, along with enough

information on the internal operation of the program to permit users to easily implement adaptations of their own
invention.

An important limitation of the trap processor is that it is not interruptible. It may not be operated when the
PDP-12 Program Interrupt facility is enabled.
7.1.13

FRED (DEC-12-FZFA-D)

The File Replacement, Entry, and Deletion subroutine processes the LAP6-DIAL Index for the user, freeing him
from the clerical function of maintaining the file entries. A second version Mildred (DEC-12-FZDA-D) performs
these operations in a disk based system.

7.1.14

PRTC 12-F (DEC-12-YIYA-D)

PRTC12-F is a PDP-12 program to utilize the TC12-F tape hardware option in transferring data between LINCtape
and DECtape. The DECtape may have been formatted on a PDP-8, PDP-8/I, PDP-9, PDP-10, and PDP-15. For a
complete description of the TC12-F hardware see Section 6.4.3.
7.1.15

SIGAVG/SINPRE (DEC-12-UZ1A-D/DEC-12-UW4A-D)

SIGAVG is a multisweep signal averager that allows the user to enhance signals with a low signal/noise ratio and
them on the CRT Display. SIGAVG will sample at rates ranging from 55 to 4095 us per point per
instrument, supporting a maximum of five instruments. It can take up to 4096 sweeps, and can output averaged
results to LINCtape. SINPRE converts the output of SIGAVG (two-word) to the commonly used one-word format.
display

7.1.16

CATACAL (DEC-12-UW1A-D)

CATACAL is a "boxcar" averager and data manipulation program that acquires data from an external instrument
at rates that range from .2 ms to 35 seconds per point. CATACAL is capable of reading and writing on LINCtape; it
can output one or two data files (spectra) to either the CRT display or an X-Y recorder. It can also differentiate,
integrate, edit (strip), and compare data files (spectra), and display the results on the scope. It has the capability of

curve-fitting and de convolution, using Lorentzian or Gaussian equations.

7.1.17

NMRSIM (Nuclear Magnetic Resonance Simulation) (DEC-12-UW5A-D)

NMRSIM allows the user to calculate theoretical spectra of a wide variety of compounds. The user inputs the
appropriate parameters from the keyboard (such as spin, chemical shifts, and coupling constants), and calculated

7-4

line-spectra are then displayed on the scope.

and display a

series

NMRSIM can output spectra to LINCtape and can also read, merge,

of spectra from LINCtape which effectively simulate large spin systems or mixtures of

compounds.
7.1.18

ADTAPE/ADCON (DEC-12-UW2A-D)

ADTAPE is a data acquisition program that allows the user to: sample simultaneously from
at

to 16 A/D channels

sampling rates ranging from 1000 points per second to 40 seconds per point; display the output of any two

channels on the

CRT display; and output all results to LINCtape in real time. ADTAPE has a setup mode that

allows the user to define a wide variety of sampUng schemes using either the keyboard, CRT display or LINCtape.

The program ADCON is utilized upon completion of ADTAPE and allows the user to sort the ADTAPE LINCtape
output for a given channel onto contiguous tape blocks for further processing.
7.1.19

TISA (DEC-12-UW3A-D)

TISA can acquire asynchronous (time-independent) or synchronous data simultaneously from up to five
instruments at rates that do not exceed 2 milliseconds per point. TISA stores data on LINCtape and supports up to

32K of core. Data is displayed on the CRT display via a moving window and cursor with X-Y decimal readout.
TISA has a setup mode that allows the user to define a wide variety of parameters using either the keyboard/CRT
display of LINCtape. TISA is capable of acquiring data from instruments that are interfaced via shaft encoders or
potentiometers, or both. With the abiUty to call any LAP6-DIAL program, TISA is able to interact with all PDP-12
software.

7.1.20

FOCAL 12

FOCAL- 12 is an adaptation of the conversational FOCAI@ (FOrmula CALculator) language designed specifically
to optimize use of the

PDP-12 computer and its standard peripheral devices. The LINCtape, console switches,

external sense lines, and VR12 display can all be utilized effectively through FOCAL-12. Simple data acquisition

and reduction tasks may be quickly programmed using FOCAL-12, and the language can be used to analyze
previously generated data stored on LINCtape. FOCAL-12 requires 8K of memory.

7.2

PDP-8 PROGRAMS

The PDP-8 programs available to the user are listed in this section. The programs described in these abstracts come
from two sources, past programming efforts on the PDP-5, 8, 8/S, 8/1, 8/L, and present and continuing
programming effort on these machines plus the PDP-12. Thus the programming system takes advantage of the

many man-years of program development and field testing by Digital computer users. There are over 3500
Family-of-8 systems already in the field.

Although all utility and functional program documentation is issued in a newer format than that introduced with
the Family-of-8 computers, in many cases PDP-12 programs originated from previous Family-of-8 computers.
Programs written by users of Family-of-8 computers and submitted to the DECUS library (DECUS - Digital

Equipment Corporation User's Society) are immediately available to PDP-12 users. Consequently, users of all
PDP-12 computers can take full advantage of continuing program developments.
7.2.1

System Programs

DEC-08-AJAD-D FOCAL - FOCAL (for FOrmula CALculator) is an on-hne, conversational service program for
the PDP-8 family of computers, designed to help scientists, engineers, and students solve numerical problems. The

language

consists

of short imperative English statements which are relatively easy to learn.

Mathematical

expressions are typed in standard notation for the most part. No previous programming experience is needed either
to understand the manual or to use

language

sit

at the

FOCAL at the Teletype console. However, the best way to learn the FOCAL

Teletype and try the commands, starting with the examples given in the Programming

Languages Handbook.

7-5

DEC-D8-SDAB-D Disk Monitor System (8 Mode) - This system consists of a keyboard-oriented Monitor, which
enables the user to efficiently control the flow of programs through his PDP-12, and a comprehensive software

package, including a

FORTRAN Compiler, Program Assembly Language (PAL-D), Edit program (EDITOR),

Peripheral Interchange Program (PIP), and

Dynamic Debugging Technique (DDT-0) program. Also provided is a

program (BUILDER) for generating a customized monitor according to the user's particular machine configuration

(amount of core, number of discs, etc).

The system is modular and open-ended, permitting the user to construct the software required in his environment,
and allows the user full access to his disk (referred to as the system device) for storage and retrieval of his programs.
By typing appropriate commands into the Monitor, the user can load a program (construct it from one or more
units of binary coding previously punched out on paper tape or written on the disk by the Assembler, and assign it

core locations), save it (write it out, with an assigned starting address, on the system device), and later call it (read
it

back into core from the system device) for execution. See Introduction To Programming for further details.

DEC-OS- AFCO-D, 4K FORTRAN

The 4K FORTRAN Compiler lets the user express problems in a mixture of English words and mathematical
statements. It reduces the time needed for program preparation and enables users with Uttle or no knowledge of the
computer's organization and operating language to write effective programs.

The 4K

FORTRAN language consists of four general types of statements; arithmetic, logic, control, and

input/output. FORTRAN functions include addition, subtraction, multiplication, division, sine, cosine, arctangent,

square root, natural logarithm, and exponentiation.

DEC-08-KFXB-D, 8K FORTRAN
The 8K FORTRAN system translates a source program into relocatable binary code. The relocatable binary code is
output on paper tape and then loaded into the computer for program execution. The 8K FORTRAN system
features:

USA Standard FORTRAN syntax; subroutines; two levels of subscripting; function subprograms;

input/output supervisors; relocatable output loaded by the 8K Linking Loader;

COMMON statements;

F, E, A,

X, and H format specifications; and arithmetic and trigonometric Ubrary subroutines.

The 8K FORTRAN system consists of a one-pass compiler, the 8K SABR Assembler, 8K Linking Loader, and a
comprehensive Library of subprograms. The system requires a PDP-8 Family Computer with at least 8K words of
core memory, an ASR33 Teletype, and a high-speed paper tape reader and punch. 8K FORTRAN utilizes all
available core to 32K.

8K FORTRAN is a modified version of USASI Basic FORTRAN and is further described in

Programming Languages Handbook.

DEC-08-CDDB-D, DDT
The Dynamic Debugging Technique provides a means for on-line program debugging at the symbolic or mnemonic
level. By typing commands on the console teleprinter, memory locations can be examined and changed, program
tapes can be inserted, selected portions of the program can be run, and the updated program can be punched. This
and it's octal counterpart ODT-8 (DEC-08-C0C0-D) are described in Introduction To Programming.

DEC-08-YQYB-D, Floating-Point System

A Basic System (DEC-08-YQ1B-PB)
B

Interpreter, I/O, I/O Controller (-YQ2B-)

C Interpreter, I/O Functions (-YQ3B-)

D Interpreter, I/O, I/O Controller, Functions (-YQ4B-)

7-6

As described in Programming Languages Handbook this includes Floating-Point Interpreter and I/O subsystems.
Allows the programmer to code his problem in floating-point machine language.
Floating-point operations automatically align the binary points of operands, retaining the

maximum precision

by discarding leading zeros. In addition to increasing accuracy, floating-point operations relieve the
programmer of the scaling problems common in fixed-point operations. This system includes elementary function
available

subroutines programmed in floating-point. These subroutines are sine, cosine, square root, logarithm, arctan, and
exponential functions. Data being processed in floating-point is maintained in three words of memory (12-bit

exponent, 24-bit mantissa). An accuracy of six digits is maintained.

DEC-08-AFA2-PB, FORTRAN SYMBOL PRINT
Loaded after the FORTRAN Compiler, this program lists the variables used and where they will be located in core.
It also indicates the section of core not used

by the compiled program and data.

7.2.2 Elementary Function Routines

The following routines are described in the Program Library Math Routines Manual (DEC-08-FFAC-D)
and in the
Programming Languages Handbook.
Square Root Subroutine-Single Precision

Forms the square root of a single-precision number. An attempt to take the square root of a negative number will
give

for a result.

Signed Multiply Subroutine-Single Precision

Forms a 22-bit signed product from 1 1-bit signed multiplier and multiplicand.
Signed Divide Subroutine-Single Precision
This routine divides a signed 11-bit divisor into a signed 23-bit dividend giving a signed

1-bit

quotient and a

remainder of 1 1 bits with the sign of the dividend.
Double-Precision Multiply Subroutine-Signed

This subroutine multiplies a 23-bit signed multiplicand by a 23-bit signed multiplier and returns with a 46-bit
signed product.

Double-Precision Divide Subroutine-Signed

This routine divides a 23-bit signed divisor into a 47-bit signed dividend and returns with a 23-bit signed quotient

and a remainder of 23 bits with the sign of the dividend.

7-7

Sine Routine-Double Precision

The Double-Precision sine subroutine evaluates the function Sin (X) for -4 < 4 (X is in radians). The argument is a
double-precision word, two bits representing the integer part and 21 bits representing the fractional part. The result
is

a 23-bit fraction -1

< Sin(X)

Cosine Routine-Double Precision
This subroutine forms the cosine of a double-precision argument (in radians). The input range is -4

< X < 4.

Four-Word Floating-Point Package
This is a basic floating-point package that carries data as three words of mantissa and one

word of exponent.

Common arithmetic operations are included as well as basic input/output control. No functions are included.
Logical Subroutines

Subroutines for performing the logical operations of inclusive and exclusive OR are presented as a package.

Arithmetic Shift Subroutines

Four basic subroutines, arithmetic shift right and arithmetic shift left at both single and double precision, are
presented as a package.
Logical Shift Subroutines

Two basic subroutines, logical shift right at both single and double precision are presented as a package.
Digital-8-21-F Signed Multiply (Uses EAE) Single Precision

This subroutine forms a 22-bit signed product from an

1 1-bit

signed multiplier and multiplicand using the

Extended Arithmetic Element. It occupies less storage and takes less time to execute than its non-EAE counterpart,
and it has the same calling sequence.
Digital-8-22-F Signed Divide (Uses EAE) Single Precision

This subroutine divides a double-precision signed 22-bit dividend by a signed
1 1-bit

1-bit divisor, producing a signed

quotient and a remainder of 1 1 bits having the sign of the dividend.

makes use of the Extended Arithmetic Element instruction set and occupies less storage and takes less time to

execute than its non-EAE counterpart. It has the same calling sequence except that the subroutine name is changed

from DIVIDE to SPDIV.
Digital-8-23-F Signed Multiply (Uses EAE) Double Precision

This subroutine multiplies a 23-bit, signed 2's

complement binary number by a 23-bit signed 2's complement
It makes use of the Extended

binary number, giving a 46-bit product with two signs on the higher order end.

Arithmetic Element instruction set and, because of this, occupies less storage and takes less time to execute than its

non-EAE counterpart. Its calling sequence is comparable with the non-EAE version.
Digital-8-25-F EAE Floating-Point Package

These packages perform the same tasks as the Floating-Point Packages (DEC-08-YQ IB through YQ4B), except that
certain routines have been speeded up by the use of the Extended Arithmetic Element.

For a detailed description of floating-point arithmetic and the interpretive Floating-Point Packages, the reader is
referred to DEC-08-YQYB-D or the Programming Languages Handbook.

7-8

7.2.3

Utility Program

DEC-08-LRAA-D, Read-In-Mode Loader
The RIM Loader is a minimum-sized routine for reading and storing the information in Read-In Mode coded tapes
ASR Perforated Tape Reader (also high speed reader version).

via the 33

DEC-08-LBAA-D, Binary Loader (33 ASR, PR12, MC12 Memory Extension)
The Binary Loader is a routine for reading and storing the information in binary-coded tapes via the 33 ASR
Perforated Tape Reader or by means of the Type PR 12 High-Speed Perforated Tape Reader.
DEC-08-PMP0-D, RIM Punch
This program provides a means of punching out the information in selected blocks of core memory as (Read-In
Mode) RIM-coded tape via the 33 ASR Perforated Tape Reader or the High Speed Punch PP12.

DEC-08-YX1A, Binary Punch (33 ASR)
DEC-08-YX2A, Binary Punch (PP12)
This program provides a means of punching out the information in selected blocks of core memory as binary-

coded tape via the 33 ASR Perforated Tape Punch or the High Speed Punch PP12.

DEC-08-YPPA, Octal Memory Dump
This routine reads the console switches to obtain the upper and lower limits of an area of memory, then types on
the Teletype an absolute address plus the octal contents of the first four words specified; it repeats this until the

block is exhausted, at which time the user may repeat the operation.
Digital-8-1 1-U Double Precision BCD-to-Binary by Radix Deflation

This subroutine converts a 6-digit BCD number to its equivalent binary value contained in two computer words.

Digital-8-1 2-U Incremental Plotter Subroutine

This subroutine moves the pen of an incremental plotter to a new position along the best straight line. The pen may

be raised or lowered during the motion.
DigitaI-8-14-U Binary to Binary-Coded-Decimal Conversion

This subroutine provides the basic means of converting binary data to binary-coded-decimal

(BCD) data for

typeout, magnetic tape recording, etc.
Digital-8-1 5-U-SYM Binary-to-Binary-Coded-Decimal Conversion (Four Digit)

to 4095 in a single
method used in Digital-8- 1 4-U so that binary integers from
computer word may be converted to four binary-coded-decimal characters packed in two computer words.

This subroutine extends the

Digital-8-1 7-U

EAE Instruction Set Simulator

This routine permits the automatic multiply-divide hardware option to be simulated.

7-9

Digital-8-20-U-SYM Character String Typeout Subroutine
This basic subroutine types messages stored internally as a string of coded characters. All 33 ASR characters are
legal.

Digital-8-21-U-SYM Symbolic Tape Formal Generator

The Format generator allows the user to create PDP-8 symbolic tapes with Formatting. It may be used to condense
tapes with spaces by inserting tabs, or merely to align tabs, instructions, and comments.

Digital-8-22-U-SYM Unsigned Decimal Print, Single Precision
This subroutine permits the typeout of the contents of a computer word as a four-digit, positive, decimal integer.

Digital-8-23-U-SYM Signed Decimal Print, Single Precision
This subroutine permits the typeout of the contents of a computer word as a signed two's complement number. If

of the computer word is a 1, the remaining bits represent a negative integer in two's complement form; if bit

bit

equals 0, the remaining bits represent a positive integer. If the

number is negative, a minus sign is printed; if

positive, a space.

Digital-8-24-U-SYM Unsigned Decimal Print, Double Precision
This

subroutine permits the typeout of a double-precision integer stored in the usual
double-precision numbers (see DEC-08-FFAC-D or Programming Languages Handbook). The

convention

for

one exception is that

all

24 bits are interpreted as magnitude bits (i.e., the bit

of the high-order word is not a sign bit). The typeout is

in the form of a seven-digit, positive, decimal integer.

Digital-8-25-U-SYM Signed Decimal Print, Double Precision
This subroutine permits the typeout of the contents of two consecutive computer
words as one signed,
double-precision, two's complement number. If bit
of the high order word is a
the remaining 23 bits
1
represent a negative integer in two's complement form; if bit
equals 0, the remaining bits represent a positive
integer. If the number is negative, a minus sign is printed; if positive, space.
,

Digital-8-28-U-SYM Single Precision Decimal-to-Binary Conversion & Input (ASR-33) Signed or Unsigned
This routine accepts a string of up to four decimal digits (single precision for the PDP-12) from the Teletype
keyboard and converts it to the corresponding two's complement binary number. The string may contain as legal
characters a sign (+, -, or space) and the digits from 0-9. If the first legal character is not a sign, the
conversion is

unsigned.

Digital-8-29-U-SYM Double Precision Decimal-to-Binary Conversion & Input (ASR-33) Signed or Unsigned
This routine accepts a string of up to eight decimal digits (double-precision for the PDP-12) from the Teletype
keyboard and converts it to the corresponding two's complement binary number. The string may contain as legal
characters a sign (+,

or space) and the digits 0-9. If the

first legal

character is not a sign, the conversion is

unsigned.
7.3

DECUS PROGRAM

DECUS is the Digital Equipment Corporation Users' Society, which collects, files, and distributes user-written
programs for all DEC computers. Below is a partial list of PDP-8 programs available through DECUS. More detailed
lists are available in the periodic DECUS program catalog.

7-10

DECUS No. 5-5, EXPANDED ADDING MACHINE
Expanded Adding Machine is a minimum-space version of Expensive Adding Machine (DEC 5-43-D) using a table
lookup method including an error space facility.
This is a basic version to which additional control functions can easily be added. Optional vertical or horizontal
format, optional storage of intermediate result with reentry, fixed-point output of results within reason, and other
features that can be had in little additional space under switch register control. (Write-up and Listing Only)

DECUS NO. 5/8-9, ANALYSIS OF VARIANCE PDP-5/8
An analysis of variance program for the standard PDP-5/8 configuration.
The output consists of:
A. For each sample:

sample number

sample size

sample mean

sample variance

sample standard deviation

The grand mean

C. Analysis of Variance Table

This is the standard analysis of variance table that can be used with the F test to determine the significance, if any,

of the differences between sample means. The output is also useful as a first description of the data.
All arithmetic calculations are carried out by the Floating Point Interpretive Package DEC-08-YQYB-D described in

Programming Languages Handbook.

DECUS NO. 5/8-1 8a, BINARY TAPE DISASSEMBLY PROGRAM
Disassembles a PDP-8 program, which is on tape in BIN format. It prints the margin setting, address, octal contents,

and mnemonic interpretation (PAL) of the octal contents. A normal program or a program which uses Floating
Point may be disassembled.

7-11

DECUS NO. 5/8-20, REMOTE OPERATOR FORTRAN SYSTEM
Program modification and instructions to make the FORTRAN OTS version dated 2/12/65 operate from remote
stations.

DECUS NO. 5/8-21, TRIPLE PRECISION ARITHMETIC PACKAGE
An arithmetic package to operate on 36-bit signed integers. The operations are add, subtract, multiply, divide,
The largest integer which may be represented is 2^^ -1 or 10 decimal

input conversion, and output conversion.
digits.

The routines simulate a 36-bit (3 word) accumulator in core locations 40,41, and 42, and a 36-bit multiplier

quotient register in core locations 43, 44, and 45. Aside from the few locations in page 0, the routines use less core
storage space than the equivalent double-precision routines.

DECUS NO. 5-25, A PSEUDO RANDOM NUMBER GENERATOR
The random number generator subroutine, when called repeatedly, will return a sequence of 12-bit numbers which,
though deterministic, appears to be drawn from a random sequence uniform over the interval OOOOg to 1771 sSuccessive

numbers will be found to be statistically uncorrected. The sequence will not repeat itself until it has

been called over 4 billion times.

DECUS NO. 8-26a, COMPRESSED BINARY LOADER (CBL)
The CBL (Compressed Binary Loader) format, in contrast to BIN format, utilizes all eight information channels of
the tape, thus achieving nearly 25% in time savings.

Whereas BIN tapes include only one checksum

at the

end of the tape,

CBL tapes are divided into many

independent blocks, each of which includes its own checksum. Each block has an initial loading address for the
block and a word count of the number of words to be loaded.

The CBL loader occupies locations 7700 through 7777.

DECUS NO. 8-26c, XCBL - EXTENDED MEMORY CBL LOADER

XCBL is used to load binary tapes punched in CBL format into any 4K memory field. This loader occupies
locations 7670 through 7777 of any memory field.

DECUS NO. 8-26d, XCBL PUNCH PROGRAM
This program permits a user to prepare an XCBL tape of portions of extended memory through the control of the

keyboard of the on-line Teletype.

7-12

DECUS NO. 5/8-27a, BOOTSTRAP LOADER AND ABSOLUTE MEMORY CLEAR
Bootstrap Loader inserts a bootstrap loading program in page

from a minimum of toggled instructions.

Absolute Memory Clear leaves the machine in an absolutely clear state and, therefore, cycling around memory,

obeying an AND instruction with location zero. Should not be used unless one plans to reinsert the loader program.

DECUS NO. 5/8-28a, PAL III MODIFICATIONS-PHOENIX ASSEMBLER
This modification of the PAL III Assembler speeds up assembly on the ASR-33/35 and operates only with this I/O
device. Operation is essentially the same as PAL III, except that an additional pass has been added. Pass 0. This pass
starts in the usual

manner but, with the switches set to zero, reads the symbolic tape into a core buffer area.

Subsequent passes then read the tape image from storage instead of from the Teletype.

DECUS NO. 5/8-29, BCD TO BINARY CONVERSION SUBROUTINES
These two subroutines improve upon the DEC-supplied conversion routine.

DECUS NO. 5-30, GENPLOT - GENERAL PLOTTING SUBROUTINE
This self-contained subroutine is for the PDP-5 with a 4K memory and a CALCOMP incremental plotter. The

subroutine can

move (with the pen in the up position) to location (x,y), make an x at this location, draw a Une

from this present position to location (x,y), and initialize the program location counters.

DECUS NO. 5-31, FORPLOT - FORTRAN PLOTTING PROGRAM

FORPLOT is a general-purpose plotting program for use in conjunction with the CALCOMP 560 Plotter. It is
self-contained and occupies memory locations 0000 to 4177. FORPLOT accepts decimal data inputted on paper
tape in either fixed or floating point formats. Formats can be mixed at

will.

FORTRAN output tapes are

acceptable directly, and any comments on these are filtered out.

DECUS NO. 5/8-32a, PROGRAM TO RELOCATE AND PACK PROGRAM IN BINARY FORMAT
Provides a means to shuffle machine language program around in

memory to make the most efficient use of

computer storage.

DECUS NO. 5/8-33, TAPE TO MEMORY COMPARATOR
Tape to Memory Comparator is a debugging program which allows comparison of the computer memory with a
binary tape. It is particularly useful for detecting reader problems, or during stages of debugging a new program.
Presently uses high-speed reader, but may be modified for TTY reader.

DECUS NO. 5/8-35, BCD TO BINARY CONVERSION SUBROUTINE AND BINARY TO BCD SUBROUTINE
(DOUBLE PRECISION)
This program consists of a pair of relatively simple and straightforward double-precision conversions.

7-13

DECUS NO. 5/3-38, FTYPE - FRACTIONAL SIGNED DECIMAL TYPE-IN
Enables a user to type fractions of the form: .582. -.73, etc, which will be interpreted as sign plus 1 1 bits (e.g., 0.5

M 2000). Subroutine reads into 300-3177 and is easily relocated, as it will work on any page without modifications.

DECUS NO.

5/8-39,

DSDPRINT, DDTYPE - DOUBLE-PRECISION SIGNED DECIMAL INPUT-OUTPUT

PACKAGE
DSDPRINT, when given a signed 24-bit integer, types a space or minus sign, and then a 7-digit decimal number in
the range -8388608 to +8388607.

DDTYPE enables user to type in a signed decimal number in either single or

double precision. These routines are already separately available, but the present subroutine package occupies only

one memory page and allows for more efficient memory allocation. Located in 3000-3177, but will work on any
page.

DECUS NO. 5/8-43, UNSIGNED OCTAL-DECIMAL FRACTION CONVERSION
This routine accepts a four-digit octal fraction in the accumulator and prints it out as an N-digit decimal fraction

where N =

2 unless otherwise specified. After N digits, the fraction is truncated. Programs are included for use

with the Extended Arithmetic Element.
Storage requirements:

55 Octal locations for the PDP-5, 47 Octal locations for the PDP-8.

DECUS NO. 8-44, MODIFICATIONS TO THE FIXED POINT OUTPUT IN THE PDP-8 FLOATING POINT
PACKAGE (DEC-08-YQYA-D)
The Floating Point Package (DEC-08-YQYA-D) includes an Output Controller which allows output in fixed point as
well as floating point format. This Output Controller takes the form of a certain number of patches to the "Floating
Output E Format" routine, plus an additional page of coding.
Certain deficiencies were noted in the fixed-point output format, particularly the lack of any automatic rounding off.

For example, the number 9, if outputted as a single digit, appears as 8. Modification attempts to provide automatic
rounding off resulted

in the

Output Controller being completely rewritten with minor changes in the format.

This new version of the Output Controller is also in the form of patches to the Floating Output with an additional

page of coding, thereby not increasing the size of the Floating-Point Package.

7-14

The following summarizes this new version:
1.

The number output is automatically rounded off to the last digit printed, or the sixth significant digit,
first. Floating point output is rounded off to six figures, since the seventh is usually

whichever is reached
meaningless.

A number less than one is printed with a zero preceding the decimal point (e.g., +0.5 instead of +.5).

A zero result, after rounding off, is printed as +0 instead of +.

4. The basic Floating Point Package includes the facihty to specify a carriage return/line feed after the
number using location 55 as a flag for this purpose. The patches for the Output Controller caused this facility to be
lost. This version restores this facility.

DECUS NO. 8-47, ALBIN - A PDP-8 LOADER FOR RELOCATABLE BINARY PROGRAMS
ALBIN is a simple method for constructing relocatable binary formatted programs, using the PAL III Assembler.
memory page (128io registers.). When loading an
ALBIN program, the actual absolute addresses of indicated program elements (e.g., the keypoint of subroutines)
Allocation of these programs can be varied in units of one

are

noted down in fixed program-specified location on page zero. In order to make a DEC symboHc program

suitable for translation into its relocatable binary equivalent, minor changes are required which, however, do not

influence the length of the program. Due to its similarity to the standard DEC BIN loader, the ALBIN loader is also
able to read-in normal DEC binary tapes. ALBIN requires 122i o locations, RIM loader included. Piling-up in core
memory of ALBIN programs stored on conventional or DECtape can be achieved using the same method with some

modifications.

DECUS NO. 5/8-48, MODIFIED BINARY LOADER MKIV
The Mark IV loader was developed to accomplish four objectives:
1.

Incorporate the self-starting format described in DECUS 5/8-27, ERC Boot.

Select the reader in use automatically, without svdtch register settings.

Enable a newly-prepared binary tape to be checked prior to loading by calculating the checksum.

Reduce the storage requirements for the loader so that a special program would fit on the last page of

memory with it.

DECUS NO. 8-49, RELATIVISTIC DYNAMICS
Prints tables for relativistic particle collisions and decay in the same format as the Oxford Kinematic Tables. It can

be used in two ways

1 .

Two-particle Collisions - Given the masses of incident, target, and emitted particles, the incident energy,

and center-of-mass angles, the program calculates angles and energies of the emitted particles in the Lab frame. If
the process if forbidden energetically, program outputs E, allowing the threshold energy to be found.

Single Particle Decays

- By specifying M2 =

(target), the

problem will be treated as a decay, and tables

similar to the above will be printed.

7-15

DECUS NO. 5/8-50, ADDITIONS TO SYMBOLIC TAPE FORMAT GENERATOR (DEC-8-21-U)
Performs further useful functions by the addition of a few octal patches. By making the appropriate octal patches
via the toggles, the

Format Generator can also format FORTRAN tapes, shorten tape by converting space to tabs,

and convert the type of tape.

A short binary tape may be made and added on to the end of 8-2 1-U to edit an original tape that was punched
off-line.

The rubout character will cause successive deletion of the previous characters until the last C. R. is reached but not
removed. The use of -^ will cause the current line to be restarted. Thus an input tape may be prepared off-line
without attention to format spacing, with mistakes corrected as they occur, and finally passed through the Format

Generator to create a correctly formatted, edited, and line-fed on either rolled or fanfold paper tape.

DECUS NO. 5/8-51, CHARACTER PACKING AND UNPACKING ROUTINES
ASCII characters may be packed two to a word and recovered. Control characters are also packable but are
preceded by a 37 before being packed into the buffer. The two programs total 663 ^ o registers.

The program occupies 72], o registers.

DECUS NO. 5/8-54, TIC-T AC-TOE LEARNING PROGRAM - T^
This program plays Tic-tac-toe, basing its moves on stored descriptions of previously lost games. The main program
is

written in FORTRAN. There is a short subroutine written in PAL II used to print out the Tic-tac-toe board. The

program comes already educated with about 32 lost games stored. Requires FORTRAN Object Time System.

DECUS NO. 5/8-56, FIXED POINT TRACE NO. 1

A minimum size monitor program which executes the user's program one instruction at a time and reports the
contents of the program counter, the octal instruction, the contents of the accumulator and hnk, and the contents

of the effective address by means of the ASR-33 Teletype. Storage Requirements: two pages.

DECUS NO. 5/8-57, FIXED POINT TRACE NO. 2
Similar to Fixed Point No.

(6000).

except that the symbolic tape provided has a single origin setting instruction of

Any four consecutive memory pages can be used, with the exception of page zero, by changing this one

instruction.

DECUS NO. 8-58, ONE-PAGE DECTAPE ROUTINE (522 CONTROL)

A general-purpose program for reading, writing, and searching of magnetic tape. This program was written for the
Type 552 Control. It has many advantages over both of the standard DEC routines and also over the DECUS No.
5-46. The routines are one page long and can be operated with the interrupt on or off. The DEC program delays the
calling program while waiting for the unit and movement delays to time out. This routine returns control to the
calling program. This saves 1 /4 second every time the tape searches forward, and half that time when it reverses. In
addition, it will read and write block O,. This program is an advantage over the previous one-page routines in that it

allows interrupt operations, doesn't overflow by one location, interrupts the end zone correctly and not as an error,

and provides a calling sequence identical to the DEC program.

7-16

DECUS NO. 8-60, SQUARE ROOT FUNCTION BY SUBTRACTION REDUCTION

A single precision square routine using EAE. This routine is usually faster than the DEC routine and can easily be
modified for double precision calculation at only twice the computation time.

DECUS NO. 8-61, IMPROVEMENT TO DIGITAL 8-9 F SQUARE ROOT
An improved version of the DEC Single Precision Square Root Routine (without EAE). Saves a few words of
storage and execution is speeded up by 12 per cent.

DECUS NO. 8-62, HIGH-SPEED READER OPTION FOR FORTRAN COMPILER
Program modification that allows the PDP-8 FORTRAN Compiler to read source tapes through the high-speed
reader, and punch on the ASR-33. The program is loaded in over the compiler. It can be punched on an extension
of the compiler tape so that, by depressing the CONTINUE key, it can be read in immediately following the
compiler.

DECUS NO. 8-65, A PROGRAMMED ASSOCIATIVE MULTICHANNEL ANALYZER
The program describes the use of a small computer as an associate analyzer with special reference to the PDP-8. The
advantages and limitations of the method are discussed in the write-up, and general program algorithms are
presented.

DECUS NO. 8-68 a LABEL for PDP-8, ALP PROGRAM
The ALP Program punches labels for paper tapes. When a key is stuck on the on-line Teletype keyboard, no echo is
performed, but the computer outputs a few characters to the Teletype punch which form the outline of the
character associated with the key.

The character outUnes have a fixed width of 5 lines of tape, followed by 3 blank lines for separation between
characters; all 8 columns of the paper tape are used to provide the maximum height of character outlines.

DECUS NO. 5/8-69, LESQ29 and LESQU
The purpose of the program is to fit the best sequences of parabolas to a given 400-point parabola least squares fit
to approximate a given data curve. Approximately 400 individual parabolas are computed.

DECUS NO. 8-70, EAE ROUTINES FOR FORTRAN OPERATING SYSTEM (DEC-08-CFA3)
These are two binary patches to the FORTRAN Operating System which utilizes the Type 182 EAE hardware for
single

precision multipUcation

system).

and normaUzation, replacing the software routines

FOSSIL (the operating

The binary tape is loaded by the BIN Loader after FOSSIL has been loaded. Execution time of a

Gauss-Jordan matrix inversion is reduced by approximately 30%.

Other Programs Needed:

FORTRAN Operating System (DEC-08-CFA3-PB), dated March 2, 1967.

7-17

DECUS NO. 8-72, MATRIX INVERSION - REAL NUMBERS
The program inverts a matrix, up to size 12 x 12, of real numbers. The algorithm used is the Gauss-Jordan method.

A unit vector of appropriate size is generated internally at each stage. Following the Gauss sweepout, the matrix is
shifted in storage, another unit vector is generated, and the calculation proceeds.

Other Programs Needed:

FORTRAN Compiler and FORTRAN Operating System.

Storage: This program uses essentially all core not used by the

FORTRAN Operating System.

Execution time: Actual computation takes less than 10 seconds. Data read-in and read-out may take up to five
minutes.

DECUS NO. 8-73, MATRIX INVERSION - COMPLEX NUMBERS
The program inverts a matrix, up to size 6 x 6, of complex numbers. The algorithm used is the Gauss-Jordan
method, programmed to carry out complex number calculations. A unit vector of appropriate size is generated
internally.

Following the Gauss sweep-out, the matrix

shifted,

another unit vector

generated, and the

calculation proceeds. The print-out of the matrices uses the symbol J to designate the imaginary part; e.g.,

A=a+

jb.

Other Programs Needed:

FORTRAN Compiler and FORTRAN Operating System.

Storage: This program uses essentially all core not used by the

FORTRAN Operating System.

Execution Time: Actual computation takes less than 10 seconds. Data read-in and read-out may take up to five
minutes.

DECUS NO. 8-74, SOLUTION OF SYSTEM OF LINEAR EQUATION: AX = B, BY MATRIX INVERSION AND
VECTOR MULTIPLICATIONS

AX = B by inverting matrix A, using a Gauss-Jordan
method. When the inverse matrix has been calculated, it is printed out. At that point, the program requests the
This program solves the set of linear algebraic equations

B-vector entries. After read-in of the B-vector, the product is computed and printed out. The program then loops
back to request another B-vector, allowing the system to solve many sets of B-vectors without the need to invert

matrix A again. Maximum size is 8 x 8.

Other Programs Needed:

FORTRAN Compiler and FORTRAN Operating System.

Storage: This program uses essentially all core not used by the

Execution Time: Actual computation
minutes.

7-18

is less

FORTRAN Operating System.

than 10 seconds. Data read-in and read-out may take up to five

DECUS NO. 8-75, MATRIX MULTIPLICATION - INCLUDING CONFORMING RECTANGULAR MATRICES
This program multiplies two matrices, not necessarily square but which conform for multiplication.

Other Programs Needed:

FORTRAN Compiler and FORTRAN Operating System.

Storage: This program uses essentially all core not used by the

FORTRAN Operating System.

Execution Time: Actual computation takes less than 10 seconds. Data read-in and read-out may take up to five
minutes.

DECUS NO. 8-76, PDF NAVIG 2/2
This program utiHzes the output of the U.S. Navy's AN/SRN-9 satellite navigation receiver to obtain fixes. This

program except for some details of input and output, follows very closely NAVIG 2 written for the IBM 1620,
which, in turn, is derived from the TRIDON program written at the Applied Physics Laboratory of Johns Hopkins
University for the IBM 7090.

PDP NAVIG 2/2 is written in PAL III for 4096-core machine using the ASR-33. Floating point numbers using two
12-bit words as mantissa and one 12-bit word as exponent are employed. The accuracy is slightly less than that when

using 7 decimal digits per word.

DECUS NO. 8-77, PDP-8 DUAL PROCESS SYSTEM
The purpose of this system is to expedite the programming of multiprocessing problems on the PDP-8. It maximizes
both the input speed and the portion of real time actually used for calculations by allowing the program to run during
the command.
the intervals between issuing I/O commands and the raising of the device flag to signal completion of
The technique also allows queuing of input data or commands so that the user need not wait while his last line is
length. The
being processed, and so that each line of input may be processed as fast as possible regardless of its
PDP-8.
system uses the interrupt facilities, and has about 0.1% overhead on the

method is especially useful for a slower machine where the problem may easily be calculation-limited, but
would, without such a system, become 1/0 Bound.
This

The system requires 6008 registers for two TTYs plus buffer space. Several device configurations are possible.

DECUS NO. 8-78, DIAGNOSE: A VERSATILE TRACE ROUTINE FOR THE PDP-8 COMPUTER WITH EAE
This trace routine will track

down logical errors in a program (the sick program). Starting at any convenient

location in the sick program, instructions are executed, one at a time, and a record of all operations is printed out
via the Teletype.

To avoid tracing proven subroutines, an option is provided to omit subroutine tracing. The
more versatile than two other trace routines in the DECUS library (DECUS Nos.

present routine is significantly

8-56 and 8-57 - Biavati) for the PDP-8 in that it is able to trace sick programs containing floating-point, extended
arithmetical,

and a variety of input-output instructions. Diagnose is, however, at a disadvantage compared with

7-19

Biavati's routines in requiring more memory space than his first one (DECUS No. 8-56) (five pages as opposed to

two) and in not possessing the trace-suppression features of his second one

(DECUS No. 8-57). The mode of

operation of Diagnose is quite different from that of the trace routines of Biavati.

Minimum Hardware: PDP-8 with EAE
Other Programs Needed
Storage:

Floating Point Package needed for floating point tracing.

5(4) pages of memory.

Miscellaneous: Program is relocatable.

DECUS NO. 8-79, TAC-TAC-TOE (TRINITY COLLEGE VERSION)
This TIC-T AC-TOE game is programmed, using internal logic, so that the computer will either win or stalemate, but

not lose a game. Either the player or the computer may choose to go first. At the termination of a game, the

program restarts for the next game by typing anew the grid code to be followed.

DECUS NO. 8-80, DETERMINATION OF REAL EIGENVALUES OF A REAL MATRIX
This is a two-part program for determining the real eigenvalues of a real-valued matrix. The matrix does not have to

be symmetric. Part I uses the power method of iterating on an eigenvector to determine the largest eigenvalue of
the matrix. Part II then deflates the matrix using the results of part I so as to produce a matrix of order one less

than that solved for in Part I. Part I can then be reloaded, and the next eigenvalue in line may be calculated. In this

manner, all the real eigenvalues may be computed in order.

DECUS NO. 5/8-83A AND B, OCTAL DEBUGGING PACKAGE (WITH AND WITHOUT FLOATING POINT)
This program is an on-line debugger which will communicate with the operator through the ASR-33 Teletype. It
allows

examination and modification, octal dumping, binary punching, multiple and simultaneous

breakpoints, starting a program, and running at a particular location with preset

AC link. ODP is completely

relocatable at the beginning of all pages except page zero, and is compatible with the PDP-5, the PDP-8, and the

PDP-8/S.
Requirements: The high version of

ODP requires locations 7000-7577. The low version requires locations

0200-0777. All versions will require three pages. Also, location 0002 is used for a breakpoint pointer to ODP.

Equipment: The standard PDP-8 with ASR-33 Teletype is required. A highspeed punch is optional.

DECUS NO. 5/8-85, SET MEMORY EQUAL TO ANYTHING
This program will preset all locations to any desired settings. Thus, combining a memory clear, set memory equal to

HALT, etc, into a single program. The program is loaded via the switch registers into core.

7-20

DECUS NO. 5/8-126, CUMULATIVE GAUSSIAN DISTRIBUTION CURVE FITTING
This is a curve fitting program that will take a set of any number of points with any spacing describing a cumulative

Gaussian distribution and determine the mean and standard deviation by an iterative least squares differential-

correction technique.

The mean square error of the final fitted curve is also computed. The program is coded in

PDP-8 FORTRAN.

DECUS NO. 8-133, FIRST ORDER KINETICS
First order kinetic processes are

common in chemistry and in other areas. This program accepts up to 42 data

points, calculates the rate constant and intercept by the method of least squares, and gives the rms deviation, the

correlation coeffecient, and an estimate of the error in slope. It permits graphical (CRT) examination of deviations

from the

least squares line

and iteration to a "best" infinity value.

deviation between observed and calculated quantities

It also

provides options for plotting the

on a CRT, and may be used in other cases in which one

wishes to correlate the natural logarithm of one quantity with another, as in linear free energy relationships.

DECUS NO. 8-134, LSQ: LEAST SQUARES SUBROUTINE
The subroutine calculates the slope and intercept for the equation y; = mxj + b by the method of least squares. It
also returns the ms deviation of y, the correlation coefficent, and an estimate of the error in the slope. The calcu-

lated values of y and the differences between the given and calculated values are also available on return from the

subroutine.

Other Programs Needed:

FLOAT, floating point interpreter "C" - (DEC-08-YQ3B-PB)

DECUS NO. 8-136, FOURIER TRANSFORM PROGRAM IN FORTRAN II
The program, written in PDP-8 FORTRAN II, performs the discrete Fourier Transform of a function defined over

N(N<200) evenly spaced points. I/O is via the ASR-33. The program requests the number of function points, then
that number of function values, and then prints out the values of the sine and cosine components of the function at
each defined harmonic. A conventional (not Cooley-Tukey) algorithm is used, since I/O time relative to computing
time is significant.

DECUS NO. 8-143, FFTS-R: FAST FOURIER TRANSFORM SUBROUTINE FOR REAL VALUED FUNCTIONS
This subroutine computes the Fast Fourier Transform (FFT) or its inverse of a data sequence which has been
stored in core.

It will

accommodate up to 2048 time samples, and will transform that number in under 5 seconds.

Minimum Hardware: PDP-8, PDP-8/I, or PDP-12 with EAE

DECUS NO. 8-144, FFTS-C: FAST FOURIER TRANSFORM SUBROUTINE FOR COMPLEX DATA
FFTS-C enables computation of the Discrete Fourier Transformation in a minimum amount of time. By using the
Cooley-Tukey algorithm, up to 1024 points may be transformed in only 4.5 seconds, introducing a reduction of 99
percent in computation time.

Minimum Hardware: PDP-8, PDP-8/I, or PDP-12

7-21

DECUS NO. 8-192, TALC (TAYLOR'S ALGEBRAIC LINEAR CALCULATOR)

TALC is a general-purpose calculator designed to evaluate a general algebraic equation, given all quantities involved
in the equation. In effect, TALC turns any of the family-of-eight computers into a powerful desk calculator capable
of evaluating complex algebraic, trigonometric, and logarthmic functions. In addition, TALC utilizes the concept of
"idiot-proofing" to virtually eliminate the possibility of an operator error invalidating the equation. Thus, TALC is
easy to use and presents unlimited possibilities in any field where fast and accurate calculations are required.

Minimum Hardware: 4K PDP-8 or PDP-12 High-Speed Reader, DF32 Disk File, and ASR-33/35

DECUS NO. 8-195, POLY BASIC

POLY BASIC is a compiler and operating stand-alone system designed for the PDP-8 family. It has a total user
program storage of 32K characters in which the disk is utilized. Some of the features of the compiler are:

It has all

BASIC system commands.

It has all

BASIC operations.

It contains all built-in functions except

Its accuracy is

Maximum program size is 6144 characters as in regular (Dartmouth) BASIC.

Maximum usable statement number 4095 rather than 99999.

Maximum array space is 3600 characters, and maximum number of statements is 330; however, these can

TAN,

part in 2^ ^ rather than 1 part in 2^^

because of word size difference.

be traded off against one another at the rate of 25 array elements per statement.

There are no matrix operations.

The argument "EDIT resequence" is implemented, and the command "EDID" renumbers the user file from

line number 1 00 in steps of 1 0.

There is a set of error messages to signal compilation errors and a set for execution errors.

Minimum Hardware: PDP-8 or PDP-12 with DECtape, DF32 Disk, RF08 Disk, or LINCtape

DECUS NO. 8-202, PLOT
PLOT will plot data points on a graph, calculate and plot a linear, least squares regression Une, and print out the
coefficient of correlation, the equation of the regression line, and other pertinent parameters.

Minimum Hardware: 4K PDP-8 or PDP-12 with a Houston Instrument Complot Plotter Model 6650, DP-1-1, or
equivalent

7-22

DECUS NO. 12-2, PDP-12 UTILITY AND DATA REDUCTION PROGRAMS

Contains a variety of programs written for the classic LINC or LINC-8 and modified to run in the PDP-12. Included
are

data reduction programs which perform autocorrelation, fourier analysis, power spectral analysis, and

convolution. UtiHty programs allow selected blocks of LINCtape to be searched, compared, or typed out. Also

included are programs which allow the user to convert LAP-4 or LAP-6 manuscripts into

LAP6-DIAL or to

disassemble binary code into LAP6 or LAP6-DIAL source. The current version of this tape contains binary and/or

source for the programs listed below. Also listed are the original authors. Documents, but no listings, are available

from DECUS.

FREQAN
AUTOCOR
QAFILTER
FFOURIER
FFSAMPLE

DATAM
FRQANA
TAPEDUMP
SEARCH
COMPAR
COMPARE

SIMONS

HANCE
GLAESER
BRYAN
BRYAN
HANCE
ENGEBRETSON
LANAHAN
STEIN

BINLAP6
L8SIM0

DAVISSON
NICHOLS
BJERKE
BJERKE
langbein

LAP4Q+A
DSCTABLE

McDonald
OVERTON

PARAMS

NICHOLS

DIVSUB
SPFLT
QIKDIV

STEIN
DILL

HANCE

RANDOM
NU INDEX

CLAYTON

LAP4-6

LEWIS

DECUS NO. 12-3, 8K OPERATING SYSTEM
This modification of DECUS NO. L-80 adapts it to run on the PDP-1 2.

DECUS NO. 8-203, ALPHA

ALPHA is used for titling graphs on the plotter. It can be used in conjunction with DECUS NO. 8-202.
Minimum Hardware: 4K PDP-8 with a Houston Instrument Complot Plotter Model 6650, DP-1-1
Storage Requirement:

Restriction:

2, 10,

1 1,

or equivalent

12, 20-167, 200-3654, 4000-777 is reserved for storage.

When used in conjunction with PLOT (DECUS No. 8-202), extended memory is required.

DECUS NO. FOCAL-14, LEAST SQUARES FIT TO A STRAIGHT LINE
This is a program using the principle of least squares to fit a straight line to a set of up to 35 experimental data
points.

7-23

The program requires one pass of the data. At the end of the pass the output gives the values of the slope and the
intercept of the straight line equation. In addition, the calculated values of the experimental data based on the
straight line equation are pointed out. Finally, the program gives the value of

R which is a criterion of fitness of

equation to the input data.

DECUS NO. FOCAL-15, LEAST SQUARES FIT TO A CUBIC POLYNOMIAL
This is a program using the method of least squares to fit a cubic polynomial to a set of experimental data. The

program demands two passes of the data for its completion; however, the coefficients of the polynomial are
outputted after the first pass, and, at the end of the second pass, the output gives the value of R which is a criterion
of fitness and gives the calculated values of the experimental data based on the cubic polynomial.
In addition, a section of the program can be used as a self-contained program for solution of a set of

N by N linear

equations.

DECUS NO. FOCAL-16, ONE-SAMPLE STATISTICS, TWO-SAMPLE STATISTICS, WELCH PROCEDURE;
ONE-WAY ANALYSIS OF VARIANCE; SHEFFE'S CONTRAST BETWEEN MEANS

A three part program used to perform one-sample and two-sample statistics, Welch Procedure; One-way Analysis of
Variance: and Sheffe's Contrast Between Means, which allows one to investigate more thoroughly the source of the
difference between group means.

DECUS NO. FOCAL-17, FOCAL: HOW TO WRITE NEW SUBROUTINES AND USE INTERNAL ROUTINES
The aim of this document is to help the user to code specific routines in FOCAL so that his dialect of FOCAL can
be apphed to his application (without being forced to understand in detail all the working of FOCAL). In this way,
perhaps, each user can make his particular dialect of FOCAL "perfect".

It is

assumed that the reader has a basic knowledge of PDP-8 processor instructions and PAL mnemonics, as well as

a familiarity with the Floating Point Package. In addition, he should be familiar with the

This

FOCAL language.

document is an attempt to explain how user-developed software can be interfaced with the basic FOCAL

package, without requiring the user to spend valuable time trying to understand all of its detailed workings. Section
II

deals with a general description of how

FOCAL works. Section III is concerned with the philosophy of the

language; and the last few sections are technically oriented toward helping the user actually code his additions.
Several examples and ready-coded routines which may be used to simplify the user's problems are included.

DECUS NO. FOCAL-25, PAYROLL CALCULATIONS (CALIFORNIA, 1968)
This routine is used to calculate payrolls. It is based on the California State Unemployment Insurance rate, FICA
rate, and withholding tax.

This program could be modified easily to fit the rules of any particular state. If some of the pay ranges would not

be used, they could be omitted from the two tables, making more room for other routines, such as providing

running totals on gross pay, deductions, and net pay.

DECUS NO. FOCAL-26, CURVE FITTING
This program finds the best curve of a set of points. There are three types of curves involved:

Exponential Curve Y = Ae^-^

7-24

The variables solved for are A and B. The function is reduced to linear form by logarithms: LOG Y = BX + LOG A.
A table of values is formed and solved simultaneously to get the values of A and B.
Power Curve Y = AX^
This function is reduced to linear form:

LOG Y = N LOG X + LOG A. Once a table of values is made, it is solved

simultaneously for A and N.
Linear Line Y =

MX + B

A table is made and solved simultaneously for the value of M and B.

DECUS NO. FOCAL-33, SQUARE MATRIX MULTIPLY
The arduous task of multiplying two square matrices is quickly done by this FOCAL Matrix Multiplication routine.
The user inputs "N", indicating the number of rows and columns each matrix will have. The computer then
of the elements of the two matrices. The result of the multiplication

requests input

typed out in an

understandable matrix-like format.

Notable characteristics of this program are:

It is expressed in

It will

only five lines of FOCAL script so that it loads quickly.

process matrices of varying dimensions. Size of each matrix is Hmited only by memory capacity. (In

4K FOCAL the limit is about 6 rows and columns.)
c.

Because it inputs and outputs the matrix values in a matrix-Uke format, input transcription errors are less

likely to occur.

DECUS NO. FOCAL-37, Nth DEGREE POLYNOMIAL DATA POINT FITTING ROUTINE, Nth DEGREE
POLYNOMIAL DATA POINT FITTING ROUTINE WITH RMS ERROR
Nth Degree Polynomial Data Point Fitting Routine - This program accepts the x- and y-coordinates for an
unlimited number of data points and calculates for the equation
a.

Y = Aq + AjX + A2X2+
the coefficients

+ AnXN,

A^ which best fit the equation to the data points. The fitting criterion is "least squares". The

program allows the user to select the degree, N, of the fitting equation. N may be as large as 7.
b.

Nth Degree Polynomial Data Point Fitting Routine with RMS Error - This program is the same as Nth

Degree Polynomial Fitting Routine except that it calculates the RMS error between the y-coordinates of the data
points and the evaluated fitting equation. It will accept only a limited number of data points and the maximum
equation degree allowed is inversely related to this number.

DECUS NO. FOCAL-40, SIMPLE CHI-SQUARE TEST
The program will type out the data matrix and cell contents. Each cell will contain two values, = xxx.xxx and E =
xxx.xxx. The "0=" number is the "OBSERVED" value which was typed in by the user. The "E=" value is the

7-25

expected value calculated by the program. The program will also type out row sums (RS= ) and column sums

(CS= ), and the grand total (T= ). The last hne of output will be "X2= " and "DF= ". These are the CHI-SQUARE
and degrees of freedom.

DECUS NO. L-11, DATUM

DATUM8 is a revision of an addition to DAT AM by James Hance contained in the general library supplied with the
LlNC-8 computer. This program has retained all the features of DAT AM. Some of the original routines have been
changed in order to eliminate undesired features. In addition, DATUM8 has the ability to multiply, subtract, and
display the data with

two cursors. The data not included between the cursors can be suppressed, allowing, for

instance, integration between definite limits. The program has been receded to facilitate future modifications.

Minimum Hardware: LINC (2K) or LINC-8

DECUS NO. L-60, FORTRAN WITH LINCTAPE
The system adapts 4K PDP-8 FORTRAN to make use of the magnetic tape facility of the basic LINC-8 computer.

FORTRAN programs can be called from the left-hand tape (unit 0) by statements in the FORTRAN program in
the core; data can be stored and recalled by WRITE and READ statements, using the right-hand tape (unit 1).
The programs may be called in any order, and may be read in at less than full length in order to leave data in core.
Data can be transferred to and from tape in blocks of any length which may be chosen to correspond with program
variables. Incorporation of the program-calling facility does not involve

any sacrifice of core space for program or

data; use of the data transfer facilities uses from half to one page of core.

The system includes a modified, improved version of SYMBOL PRINT, increases the maximum length of the
statement number tables, and corrects some errors in the compiler.

Other Programs Needed: PDP-8 FORTRAN System (DEC-OS- AFCO)
Source Language:

PAL III

DECUS NO. L-80 AND 12-3, 8K OPERATING SYSTEM
The 8K Operating System was developed at the University of Michigan (Cooley Electronics Lab). It is a
two-tape-resident operating system for the LINC-8 with a special 33ASR reader modification. It allows a user to
enter and edit programs from the Teletype keyboard, store them in files on magnetic tape, assemble or compile
these files into PDP-8 machine language, and run the resulting program. These operations are done entirely from
the Teletype keyboard without the use of paper tapes or manipulation of the switches. One of the language
translators is the

DEC 8-K FORTRAN system (February 1969 version).

The 8K Operating System consists of 3 system components: a filing system, a system of loaders for running
programs, and a command language interpreter. A file is a collection of information (which the user generates) in
machine-readable form; for example, it may be the set of characters comprising a FORTRAN program. Using the
filing system,

the user may name this set of characters and store it on magnetic tape. To use the file containing the

program (for example, in a FORTRAN compilation) the user need only refer to the file name and the system will
handle all bookkeeping necessary to communicate the

file

to the

FORTRAN compiler. A user may change the

contents of files, destroy files, and copy files from other users' tapes. The assembler processes both LINC mode and

PDP-8 mode statements, assembling programs up to 8K in length. Six character alphanumeric symbols can be
defined; source listings, assembly Ustings, or abbreviated assembly listings

may be (optionally) obtained on the

Teletype or, if present, the Line Printer. To facilitate the preparation of system programs and/or large programs.

7-26

conditional assembly pseudo ops are provided, along with a facility to preserve the tag table

definitions from one

assembly to another, or to several others.

Upon loading, programs may be started automatically in either LINC or PDP-8 mode at any memory location
permanent file by means of a "SAVE" command.
The loading system contains two separate loaders, the absolute loader and the relocating loader. These loaders do
(This
not load programs directly into core memory, but rather into a core memory image kept on magnetic tape.
Both
loaders.)
the
of
desired
flexibility
and
the
intermediate step is necessary because of core space Umitations
for changing and
loaders take their binary (and core image) input from the system files; both include provisions

viewing the contents of various core image locations.

The absolute loader operates on the binary output of either the MACRO-8 of PAL-III assemblers to produce a core
capable of merging an extant core image into the core image it is building. It will also page-relocate
binary input information to be within a different memory page from that for which it was assembled.

image.

It is

The relocating loader operates on FORTRAN compiler and SABR assembler output. It is the final part of the
for the
3-part FORTRAN/ SAB R/Relocating Loader package, which allows the programmer to write programs
PDP-8 disregarding the memory addressing structure of the machine. After the loading process is complete, the core
image file containing the program is available to the user in -B, and may be saved or run immediately using the

"RUN" command.

The "RUN" command software is also part of the loading system. It allows execution of a program contained in a
core image file.

7.4

DIAGNOSTIC PROGRAMS

PDP-12 PROCESSOR TESTS
Maindec-12-DOAB Tests SKIPs and data handling (LINC mode).
These diagnostics test the LINC mode processor and memory control instructions.

PDP-12 TAPE CONTROL TESTS (TC12)
Maindec-12-D3AC Tests tape control logic and intenregister transfers.
These diagnostics make use of the TCI 2 maintenance instructions to thoroughly test the tape control. After all
static tests are performed, data transfers and dynamic characteristics are tested.

PDP-12 DISPLAY TEST (VR12)
Maindec-12-D6BA Tests display system using DIS and DSC instructions.
The diagnostic tests both the VC12 CRT display control and the VR12 CRT display oscilloscope.

PDP-12 REAL-TIME INTERFACE TEST (KW12)
Maindec-12-D8CB
This diagnostic thoroughly tests the

PDP-12

KW12-A Real-Time Interface.

AD TEST (AD 12)

Maindec-12-D6CB-Tests A-D converter and calibration.
This test verifies the logic of the AD 12 and allows checking and alignment of all 32 channels of the A-D converter.

Mamdec-08-D03A-D Basic JMS and IMP Test
This is a diagnostic program for testing the JMP and JMS instructions of the PDP-8/I.

7-27

Maindec-08-D04B-D Random JMP Test

JMP instruction of the PDP-12. Most of memory is used as a JUMP field with a random
number generator selecting each JUMP FROM and JUMP TO location.
This program tests the

Maindec-08-D05B-D Random JMP-JMS Test

FROM and TO addresses are selected for each test.
The JMP instruction is tested in that each test requires a JMP to reach JMS.
This program tests the JMS instruction of the PDP-12. Random

Maindec-08-D07B-D Random ISZ Test

FROM location, and a TO
OPERAND from a random number
generator, with the option of holding any or all constant. Part 2 uses fixed set of FROM, TO, and OPERAND
This program tests the ISZ instruction of the PDP-12. An ISZ instruction is placed in a

location contains the OPERAND. Part 1 of the program selects FROM, TO, and

numbers.

Maindec-08-DOAA-D Instruction Test (EAE) Part 3A
This program tests the Extended Arithmetic Element

Type KE12. The following instructions are tested: MQL,
MQA, SHL, LSR, ASR, NMI, SCA. An attempt is made to detect and isolate errors to their most basic faults and to
the minimum number of logic cards. Multiply and divide are tested by Maindec-08-DOBA-D.

Maindec-08-DOBA-D Instruction Test (EAE) Part 3B
Divide overflow detection hardware and divide and multiply hardware are tested by using a pseudo random-number

generator to produce the parameters for each test. A software simulated divide and multiply are used to test the
results of the hardware divide and multiply.

Maindec-08-DlAC-D Memory Power On/Off Test
This program is a Memory Data Validity Test to be used after a simulated power failure.

Maindec-08-DlLl-D Memory Checkerboard Test Low
Maindec-08-DlL2-D Memory Checkerboard Test High
Tests memory for core failure on half-selected lines under the worst possible conditions for reading and writing. It
is used primarily

for testing the operation of memory at marginal voltages.

Maindec-08-DlCA-D Extended Memory Control Part 1
This program exercises and tests Extended Memory instructions CDF, CIF, RDF, RIF, RMF, and RIB, for proper
operation.

Basically,

this

program

tests

the

control

section

the

memory.

Data

tested

tests

Maindec-08-DlLl-D, Maindec-08-D 1 L2-D and Maindec-08-DlDA-D.

Maindec-08-DlDA-D Extended Memory Checkerboard Part 2
This preliminary program tests for core memory failures on half-selected lines under worst-case conditions of
reading and writing. It is used to test memory module X while running the program in memory module Y.

Maindec-08-D2PE-D Teletype Reader Test
This program tests performance of the Teletype Model 33 Perforated Tape Reader, using the reader to scan a
closed-top test page punched with alternating groups of character codes 000 to 377. Each character is tested for

7-28

bits

dropped or gained while reading; each group of characters is checked for characters missed entirely or read

more than once.

Maindec-08-D2BA-D Exerciser for the Teletype Paper-Tape Reader
This exerciser program tests for the Teletype Paper-Tape Reader. Test tapes are read in a random start-stop fashion

and errors are reported on the Teletype printer.

Maindec-08-D2CA-D Teletype Punch Test
This program punches a test tape in a predetermined pattern. The tape passes directly from the Teletype punch to
the Teletype reader, which checks the pattern for accuracy.

Maindec-08-D2DA-D Teleprinter Test
This program tests the Teleprinter performance of the Teletype 33 Keyboard Printer. There are two parts to the
test, selectable by the operator. The first part tests keyboard input by immediately causing the character typed to
be printed for comparison. The second part tests continuous operation of the teleprinter by causing a line
consisting of the ASCII character set to be repeatedly printed. The latter also tests for correct functioning of the

interrupt after a character has been printed.

Maindec-08-D2GF-D High Speed Reader Test
This program tests performance of the Type 750 High-Speed Perforated-Tape Reader and control by scanning a
closed-loop tape for transmission accuracy.

The reader control is tested for correct operation with the PDP-8

interrupt system.

Maindec-08-D2FA-D High Speed Reader Test (PR 12)
This is a diagnostic program for the Digitronics 2500, the PR12, and the PR8/I High-Speed Paper-Tape Readers.
The program is divided into three parts. The first is a test tape generator that punches test tapes for parts two and
three on the high-speed punch. Part two is a series of specific tests with module isolation provided for error
situations. Part three reads a preselected tape pattern

with the choice of random or fixed block lengths and stalls

between blocks.

Maindec-08-D2GA-D High Speed Punch Test
This program consists of two separate tests. The first causes the PP12 and PP8/I High-Speed Paper-Tape Punch to
produce a tape containing a sequence of pseudo-random character codes. This tape is checked for accuracy, using
either the high-speed reader or the Teletype reader.

In the second test, the character code represented by the setting SR4.1 j is punched repeatedly. The switch setting

may be changed while the test is running.
Maindec-08-D6CB-D Calcomp Plotter Test
This program tests the CALCOMP or HOUSTON Plotters and their control. All control and plotting functions are
tested.

PDP-12 JMP SELF MAINDEC-12-DlBA-D
This program tests the abiUty of the read/write gates to switch rapidly between read and write.

7-29

PDP-12 Instruction Test 1 MAINDEC-12-D0BA
This program tests for the basic overall test of most of the LINC

mode instructions.

PDP-12 Address Test (R/W Gate) MAINDEC-12-D1CA
This program tests the abihty of the R/W gates to rapidly change addresses. It generates two random addresses,
loads these addresses with jumps to each other, and allows the jump sequence to continue until interrupted.

PDP-12 Memory Data Test (Float Is and Os) MAINDEC-12-D1EB
This program floats a single one then a single zero through all of memory to evaluate data handling.

PDP-12 Memory Checkerboard MAINDEC-12-D1DA
Tests memory for core failure on half-select Imes under the worst possible conditions for reading and writing.

primarily for testing the operation of memory.

7-30

It is used

APPENDIX A
LINC MODE INSTRUCTIONS

The following table lists all LINC mode instructions and their mnemonics, octal codes, and execution times. Full
instruction descriptions are in Chapter 3.

Table A-1.

Mnemonic

LINC Mode Instructions
Function

Octal

Add memory to AC (full address)
Add memory to AC (index class)
Add AC to memory (sum also in AC)
Add link and AC to memory (sum also in AC)

2000
1100
1140
1200

3.2*

1240

Time (us)

ADD
ADD
ADA
ADM
LAM

3.2*

3.2*
3.2*

MULTIPLY

MUL

Signed multiply

LOAD
LDA
LDH

Load AC, full register
Load AC, half register

1000

3,2*

1300

3.2*

STORE (sum also in AC)
STC

Store and clear AC (full address)
Store AC (index class)

4000
1040

3.2

STA
STH

Store half AC

1340

3.2*

0240
0300
0340

1.6-6.4

3.2*

SHIFT/ROTATE

ROL N
ROR N
SCR N

Rotate left N places
Rotate right N places
Scale right N places

1.6-6.4

* See Note at end of table.

A-1

Table A- 1

LINC Mode Instructions (cont)

Octal

Time (jus)

0000
0016

1.6

No operation
Clear AC and LINC

0011

1.6

Set register N to contents or register Y

0040
6000
0006
0004
0024
0005

4.8

Mnemonic

Function

OPERATE

HLT
NOP
CLR
SET
JMP

DJR

Halt

Jump to register Y
Disable JMP return save

ESF
SFA

Enable Special Function

QAC

MQ transfer to AC

Special Function to AC

1.6

1.6*
1.6
1.6
1.6
1.6

LOGICAL OPERATIONS
BCL

Bit clear (any combination of 1 2-bits)

1540

3.2*

BSE

Bit set (any combination of 1 2-bits)
Bit complement (any combination of

1600

3.2*

1640

3.2*

0017

1.6

1440

3.2*

1400

3.2*

ECO

12 bits)

COM

Complement AC
SKIP
Skip next instruction if:

SAE
SHD

AC equals memory register Y
Right half AC unequal to specified half
of memory register Y

SNSN

SENSE switch N is set

0440+N

1.6

SKP

Unconditional skip

1.6

AZE
APO

AC equals 0000 or 7777
AC contains positive number

0456
0450
0451

1.6

LZE

Link bit equals

1.6

IBZ

Between blocks on LINC tape

FLO
QLZ

Add overflow is set

MQ low-order bit zero

0452
0453
0454
0455

SXLN

External level N is low

0400+N

1.6

KST
SRO

Keyboard has been struck

0415
1500

3.2*

0200

3.2

1.6

Rotate memory register right one place;
then if bit

1.6

1.6
1.6

1.6

of Y equals 0, skip next

instruction

XSK

Index memory register Y, skip when
contents of Y equal 1777

INPUT/OUTPUT

ATR
RTA

AC to relay buffer
Relay buffer to AC

0014
0015

SAMN

Sample analog chan N

0100+N

1.6**

Display point on oscilloscope

0140

3.2-23**

DIS
**See Note at end of table.

A-2

1.6-18.2

Table A- 1

LINC Mode Instructions (cont)

Mnemonic

DSC

Function

Display character on oscilloscope

Octal

Time (/us)

1740

4.8-56**

0516
0517
0500

1.6

5.9

6141

4.25

(2x6 matrix)

RSW
LSW

RIGHT SWITCH register to AC
LEFT SWITCH register to AC

lOB

Execute input/output control through

1.6

10 Bus

LINC

8 Mode to LINC Mode

MEMORY
LDF

Load instruction field buffer with N
Load data field register with N

0600
0640

1.6

lOB
RIP

Read instruction field

0500
6224

5.9

RDF

Read data field

0500
6214

5.9

lOB
RIB

Read interrupt buffer (Save Field)

0500
6234

5.9

Restore memory fields

0500
6244

5.9

0702
0700

3 2**

0701

3.2**

LIF

lOB

RMF

1.6

LINC TAPE

RDE
RDC
RCG
WRI

Read one block into memory
Read and check one block
Read and check N consecutive
Write one block on tape

3.2**

3 2**

WRC
WCG
CHK

Write and' check one block

0706
0704

Write and check N blocks

0705

3.2**

Check one block of tape

3 2**

MTB

Move tape toward selected block

0707
0703

AXO
XOA
TMA

AC to Tape Extended Operations Buffer
Extended Operations Buffer to AC
AC to TMA setup register

0001

1.6

0021

1.6
1.6

STD

Skip if tape idle

0023
0416

TWC

Skip if tape word complete

0417

1.6

3.2**

1.6

*Indicates both direct and indirect addressing; add 1.6 jusec when indirect addressing is used.

**Indicates additional time depenaent on I/O device such as tape (Chapter 3 LINC Mode Instructions.)

A-3/A-4

APPENDIX B

8-MODE INSTRUCTIONS

Table B-1.

8-Mode Memory Reference Instructions

Direct Addr.

Mnemonic
Symbol

Opera-

Indirect Addr,

Execu-

tion

States

Code

En-

States
tion

Time

En-

(ms)

(MS)

0000

F,E

Time

tered

ANDY

Operation

tion

3.2

F,D,E

4.8

AND ope-

Logical

AND. The

ration

performed between the

contents of memory location Y

and the contents of the AC. The
result is left in the

AC, the ori-

ginal contents of the

AC are lost,
Y are re-

and the contents of

stored. Corresponding bits of the

and

Y are operated upon

independently. ACj A Y; -»- ACj

TADY

1000

F,E

3.2

F,D,E

4.8

Two's complement add. The contents of memory location

Y are

added to the contents of the AC
in two's complement arithmetic.

The result of this addition is held
AC, the original contents

in the

of the AC are lost, and the contents of
a

carry

Y are restored. If there is
from ACq, the

link

complemented.

AC + Y -> AC

B-1

Table B-1.

8-Mode Memory Reference Instructions (cont)

Direct Addr.

Mne-

Opera-

monic
Symbol

tion

States

Code

En-

Indirect Addr,

Execu-

ExecuStates

Time

tered

En-

2000

F,E

Time

tered
(MS)

ISZY

Operation

tion

3.2

(MS)

F,D,E

4.8

Increment and skip if zero. The
contents of memory location Y
are incremented

resultant

by one.

If the

Y equals

contents of

zero, the contents of the PC are

incremented

and the

struction

skipped.

If the re-

Y do not

contents

sultant

in-

equal zero, the program proceeds
to the next instruction.

The in-

cremented contents of Y are restored to memory. If resultant

= 0, PC + 1 -^ PC.

DCA

3000

F,E

3.2

F,D,E

4.8

Deposit and clear AC. The contents of the

AC are deposited in

core

memory at address Y and

the

AC is cleared. The previous

contents of memory location Y
are lost.

AC^Y
O^AC
JMSY

4000

F,E

3.2

F,D,E

4.8

Jump

to subroutine.

tents of the

The con-

PC are deposited in

core memory location Y and the

next instruction

taken from

core memory location Y + 1

PC + 1 ^ Y
Y + 1 ^ PC

JMPY

5000

1.6

F,D

3.2

Jump to Y. Address Y is set into
the PC so that the next instruction is taken from core memory
address Y.

The original contents

of the PC are lost.

Y->PC

B-2

Table B-2. 8 Mode Group 1 Operate Microinstructions

Mnemonic
Symbol

Code

NOP

7000

lAC

7001

Octal

Sequence

Operation

No operation. Causes a 1.6 /is program delay.
Increment AC. The contents of the AC are incremented by one
in two's complement arithmetic.

RAL

7004

Rotate AC and L left. The contents of the AC and the L are
rotated left one place.

RTL

7006

Rotate two places to the left. Equivalent to two successive RAL
operations.

RAR

7010

Rotate

AC and L right. The contents of the AC and L are

rotated right one place.

RTR

7012

Rotate two places to the right. Equivalent to two successive

CML
CMA

7020
7040

CIA

7041

2,3

CLL
CLL RAL
CLL RTL
CLL RAR
CLL RTR

7100
7104
7106
7110
7112
7120
7200

Complement L.
Complement AC. The contents of the AC are set to the one's
complement of its current contents.
Complement and increment accumulator. Used to form two's
complement number.
Clear L. The L is cleared to contain a binary zero.
Shift positive number one left.
Clear Link, rotate two left.
Shift positive number one right.
Clear Link, rotate two right.
Set Link, the L is set to contain a binary one.
Clear AC. To be used alone or in OPR 1 combinations.

7201

1,3

Set AC = 1.

7204
7300
7240

1,4

Get link, Transfer L into ACj j

Clear AC and L.

Set AC = -1. Each bit of the AC is set to contain a binary one.

RAR operations.

STL

CLA
CLA lAC
GLK
CLA CLL
STA

1,4
1,4
1,4

1,4
1,2

Table B-3. 8 Mode Group 2 Operate Microinstructions

Mnemonic
Symbol

Octal

HLT

7402

Code

Sequence

Operation

Halt.

Stops

the

program

after

completion of the cycle in

process. If this instruction is combined with others in the OPR

2 group, the other operations are completed before the end of
the cycle.

OSR

7404

SKP

7410
7420
7430
7440
7450

OR with Right Switch register. The OR function is performed
between the contents of the RSW and the contents of the AC,
with the result left in the AC.

SNL
SZL
SZA

SNA

Skip, unconditional. The next instruction is skipped.

Skip if L =5^ 0.

Skip if L = 0.

Skip if AC = 0.

Skip if AC ¥= 0.

B-3

Table B-3,

Mnemonic
Symbol

Octal

SZA SNL
SNA SZL

7460
7470
7500

SMA

8 Mode Group 2

Operate Microinstructions (cont)

Operation

Sequence

Code
1

Skip if AC = 0, or L = 1 or both.

Skip if AC 9t

and L = 0.

Skip on minus AC. If the AC contains a negative number, the

next instruction is skipped.

SPA

Skip on positive AC. If the AC contains a positive number, the

7510

next instruction is skipped.

SMA SNL
SPA SZL

SMA SZA
SPA SNA
CLA
LAS
SZA CLA

SNA CLA

SMA CLA
SPA CLA

7520
7530
7540
7550

Skip if AC < 0, or L = 1 or both.

Skip if AC

> and if L = 0.
Skip if AC < 0.
Skip if AC > 0.

7600
7604
7640

Clear AC. To be used alone or in OPR 2 combinations.

1,2

Load AC with SR.
Skip if AC = 0, then clear AC.

7650
7700
7710

1,2

Skip if AC -^ 0, then clear AC.

1,2

Skip if AC

1,2

Skip if AC

2,3

< 0, then clear AC.
> 0, then clear AC.

Table B-4. 8 Mode Extended Arithmetic Element Microinstructions

Mnemonic
Symbol

Octal

MUY

7405

Operation

Sequence

Code
Multiply. The number held in the MQ is multiplied by the
number held in core memory location PC + 1 (or the next
successive core memory location after the MUY Command). At

the conclusion of this instruction the most significant 1 2 bits of
the product are contained in the AC and the least significant 1
bits of the

product are contained in the MQ.

Y X MQ -^ AC,MQ
DVI

7407

Divide.

The 24-bit dividend held in the AC (most significant 1

and the MQ (least significant 12 bits) is divided by the

bits)

number held in core memory location PC +
core

successive

(or the next

memory location following the DVI instruc-

tion). At the conclusion of this instruction the quotient is held

in the MQ, the remainder is in the AC, and the L contains a 0. If

the

L contains a 1, divide overflow occured so the operation

was concluded after the first cycle of the division.

AC,MQ -^ Y ^ MQ.
NMI

7411

Normalize. This instruction is used as part of the conversion of
a binary

number to a fraction and its exponent for use in

floating-point arithmetic. The combined contents of the AC and

the

MQ are shifted left by this one instruction until the content

of ACo

not equal to the content of ACj

thus forming the

fraction. Zeros are shifted into vacated MQi i positions for each
shift.

B-4

Table B-4.

Mnemonic
Symbol

Octal

8 Mode Extended Arithmetic Element Microinstructions (cont)

Sequence

Operation

Code
At the conclusion of this operation, the step counter contains a
number equal to the number of shifts performed. The content
of L is lost.

ACj-ACj~,

ACo^L
MQo^ACii
MQj-^MQj-i

MQi

SHL

7413

until ACo i^ ACj

Shift left. This instruction shifts the combined contents of the

AC and MQ to the left one position more than the number of
positions indicated by the contents of the core

address PC +

memory at

(or the next successive core memory location

SHL instruction). During the shifting, zeros are
MQi positions. Shift Y + 1 positions as

following the

shifted into vacated

foUow^s:

ACj

AGJ"!

ACo

MQo ^ AC,
MQj^MQj-i
1

O^MQu
ASR

7415

Arithmetic shift right. The combined contents of the AC and
the

MQ are shifted right one position more than the number

contained in memory location PC +

(or the next successive

core memory location following the ASR instruction). The sign
bit,

contained in

ACq

enters vacated positions, the sign bit is

preserved, information shifted out of MQ, ,

undisturbed during this operation. Shift

is lost, and the

Y +

L is

positions as

follows:

ACq "* ACq
ACj -^ ACj +

AC, 1 ^ MQo
MQj -> MQj +

LSR

7417

Logical shift right. The combined contents of the AC and

are shifted right one position more than the number contained
in memory location PC + 1 (or the next successive core memory

location following the

LSR instruction). This instruction is

ASR instruction except that zeros enter vacated

similar to the

positions instead of the sign

MQ,

Shift

Y+

bit.

Information shifted out of

and the L is undisturbed during this operation.

lost

positions as follows:

O^ACo
ACj ^ ACj +
AC,i ^MQo
MQj ^ MQj +

B-5

Table B-4.

Mnemonic
Symbol

Octal

MQL

7421

Code

8 Mode Extended Arithmetic Element Microinstructions (cont)

Operation

Sequence

Load multiplier quotient. This instruction clears the MQ, loads
the contents of the AC into the MQ, then clears the AC.

O^MQ
AC->MQ

O^AC
SCA

Step counter load into accumulator. The contents of the step

7441

counter are transferred into the AC. The AC should be cleared
prior to issuing this instruction or the CLA instruction may be

combined with the SCA to

clear

the

AC, then

effect the

transfer.

SC V AC -> AC

SCL

Step counter load from memory. Loads complement of bits 7

7403

through 11 of the word in memory following the instruction
into the step counter.

Two's MB7.ii^SC

PC + 2 -^ PC

MQA

Multiplier quotient load into accumulator. The contents of the

7501

MQ are transferred into the AC. This instruction is given to load
the

least

significant

bits

of the product into the

following a multipUcation or to load the quotient into the AC

following a division. The AC should be cleared prior to issuing
this instruction or the

CLA instruction can be combined with

the MQA to clear the AC then effect the transfer.
MQ V AC -> AC

CLA

Clear

7601

The

AC is

cleared

instruction

to be

combined with other

accumulator.

allowing

this

instructions that load the

O^AC
7621

1,2

Clear accumulator and multiplier quotient.

CAM = CLA MQL

B-6

EAE

AC during sequence 2 (such as SCA

and MQA).

CAM

during sequence

APPENDIX C
I/O BUS INSTRUCTIONS

In the 8

mode these instructions are given directly, whereas in the LINC mode they must be preceded by the

instruction lOB (0500).

Table C-1.

Mnemonic

lOT Instructions
Operation

Octal

Program Interrupt

ION

6001

Turn interrupt on and enable the computer to respond to an interrupt
request. When this instruction is given, the computer executes the next
instruction, then enables the interrupt. The additional instruction allows exit

from the interrupt subroutine before allowing another interrupt to occur.

lOF

6002

Turn interrupt off; i.e., disable the interrupt.

High-Speed Perforated-Tape Reader and Control Type PR 12

RSF

6011

Skip if reader flag is a 1

RRB

6012

Read the contents of the reader buffer and
instruction does not clear the AC). RB

RFC

6014

V AC4-1

clear the reader flag. (This
1

-* AC4.1

Clear reader flag and reader buffer, fetch one character from tape and load it
into the reader buffer, and set the reader flag when done.

High-Speed Perforated-Tape Punch and Control Type PP12

PSF
PCF
PPC

6021

Skip if punch flag is a 1

6022

Clear punch flag and punch buffer.

6024

Load the punch buffer from AC4-i 1

and punch the character. (This

instruction does not clear the punch flag or punch buffer).

PLS

6026

AC4-11 VPB^PB
Clear the punch flag, clear the punch buffer, load the punch buffer from
AC4.1 1 punch the character, and set the punch flag when done.
,

C-1

Table C-1.

Mnemonic

lOT Instructions (Cont)

Operation

Octal

Teletype Keyboard/Reader

KSF

6031

Skip if keyboard flag is a 1

KCC
KRS

6032
6034

Clear AC and clear keyboard flag.

Read keyboard buffer static. (This is a static command in that neither the

AC nor the keyboard flag is cleared.)
TTIVAC4.il -^AC4.ii

KRB

6036

Clear AC, clear keyboard flag, and read the contents of the keyboard buffer
into AC4 -1 1

TTO VAC4-11 -^AC4-ii
Teletype Teleprinter/Punch

TSF
TCF
TPC

6041

Skip if teleprinter flag is a 1

6042
6044

Clear teleprinter flag.

TLS

6046

Load the TTO from AC4-11,
punch the character.

Load the TTO from AC4 -1 1 and print and/or punch the character.

clear the teleprinter flag,

and print and/or

Power Fail/Restart Type KP12

SPL

6 1 02

Skip if power is low.

Memory Extension Control Type MCI

CDF

62N1

Change to data field N. The data field register is loaded with the selected

number (0 to 7). All subsequent memory requests for operands are
number is
changed by a new CDF instruction.
Prepare to change to instruction field N. The instruction buffer register is
loaded with the selected field number (0 to 7). The next JMP or JMS
field

automatically switched to that data field until the data field

CIF

62N2

RDF
RIF
RIB

6214
6224
6234

RMF

6244

instruction causes the new field to be entered.

Read data field into ACg.g Bits 0-5 and 9-11 of the AC are not affected.
Same as RDF except reads the instruction field.
Read interrupt buffer. The instruction field and data field stored during an
.

interrupt are read into ACg.g and AC9-1 1 respectively.

Restore memory field. Used to exit from a program interrupt.

Incremental Plotter and Control Type XY12

PLSF
PLCF
PLPU
PLPR

6501

Skip if plotter flag is a 1

6502
6504

Clear plotter flag.
Plotter pen up. Raise pen off paper,

6511

Plotter pen right.

PLDU
PLDD

6512
6514

Plotter drum (paper) upward.

C-2

Plotter drum (paper) downward.

Table C-1. lOT Instructions (Cont)

Operation

Mnemonic

Octal

PLPL

6521

Plotter pen left.

PLUD

6522
6524

Plotter drum (paper) upward. (Same as 651 2).

PLPD

Plotter pen down. Lower pen to paper.

Random Access Disk File Type DF32

DCMA

DMAR

memory

address register, parity error and completion

flags.

This

6601

Clears

6603

instruction clears the disk memory request flag and interrupt flags.
The contents of the AC are loaded into the disk memory address register and

the AC is cleared. Begin to read information from the disk into the specified
core location. Clears parity error and completion flags. Clears interrupt flags.

DMAW

6605

DCEA
DSAC
DEAL

6611

DEAC

6616

6612
6615

The contents of the AC are loaded into the disk memory address register and
the AC is cleared. Begin to write information into the disk from the specified
core location. Clears parity error and completion flags.
Clears the disk extended address and memory address extension register.
Skips next instruction if address confirmed flag is a 1 (AC is cleared).

The disk extended address extension registers are cleared and loaded with
the track data held in the AC.
Clears the AC, then loads the contents of the disk extended address register
into the

AC to allow program evaluation. Skips next instruction if address

confirmed flag is a 1

DFSE

6621

DFSC

6622

DMAC

6626

Skips next instruction if parity error, data request late, or write lock switch
flag is a zero. Indicates no errors.

Skips next instruction if the completion flag is a 1. Indicates data transfer is

complete.
Clears the AC, then loads contents of disk memory address register into the

AC to allow program evaluation.
Disk Control and Disk File Type RF08/RS08

DCMA

6601

Clears

memory

address register, parity error and completion

flags.

This

instruction clears the disk memory request flag and interrupt flags.

DMAR

DMAW

6603

6605

The contents of the AC are loaded into the disk memory address register and
the AC is cleared. Begin to read information from the disk into the specified
core location. Clears parity and completion flags. Clears interrupt flags.
The contents of the AC are loaded into the disk memory address register and
the AC is cleared. Begin to write information into the disk from the specified

DCIM
DSAC
DIME
DIMA
DFSC
DFSC

6611

DMAC

6626

core location. Clears parity error and completion flags.
Clears the disk interrupt flag and memory address extension register.

6612
6615
6616

Skips next instruction if address confirmed flag is a 1 (AC is cleared).
Accumulator to interrupt enables and memory extension register.

6621

Skip on error condition.

6622

Skip next instruction if the completion flag is a

Status to AC.

1 .

Indicates data transfer is

complete.
Clears the AC then loads contents of disk memory address register into the

AC to allow program evaluation.

C-3

Table C-1.

Mnemonic

lOT Instructions (cont)

Octal

Operation

Disk Cartridge Memory Type RK8/RK01

DLDC
DLDR

6732
6733

Loads the command register from the AC and then clears the AC.
Loads the track, surface, and sector address from the AC; the instruction then
clears the

AC and starts to read data from the disk if command register bit 4 is

aO.

DLDW

6735

Loads the track, surface, and sector address from the AC. The instruction
then clears the AC and starts to write on the disk if command register bit 4 is

aO.

DCHP

6737

Loads the track, surface, and sector address from the AC. The instruction
then clears the AC and reads data and checks parity if command register bit 4
is a 0.

DRDA

6734

Clears the

AC and then reads the Track Address Counter and surface/sector

counter into the AC.

DRDC
DRDS

6736

Clears the

6741

Clears the

DCLS

6742
6743

Clears the status register.

DMNT

AC and then reads the command register into the AC.
AC and then reads the status register into the AC.

Load maintenance register. This instruction loads the maintenance register
from the AC and carries out the operation specified. The bits will remain set

6731

DMNT is reissued with all AC bits cleared to 0.
Loads the disk address. This instruction is a maintenance operation.

6745
6747

Skip when the error flag is set to 1

6751

Clear All. This instruction clears the selected disk to Track

until

DLDA
DSKD
DSKE
DCLA

Skip On Transfer Done flag equal to 0.

clears

all

000 and then

the control registers and status flags except the disk selection.

Transfer Done is set when the disk is positioned on Track 000.

DRWC

6752

Read word count register. This instruction

clears the

AC, then reads the

contents of the word count register into the AC.

DLWC

6753

Load word count register. This instruction loads the word count register from
the AC and then clears the AC.

DLCA

6755

Load current address register. This instruction loads the current address
AC and then clears the AC.
Read current address register. This instruction clears the AC and then reads

DRCA

6757

the contents of the current address register into the AC.

Real Time Interface Type KW12A

CLSK
CLLR
CLAB
CLEN
CLSA
CLBA
CLCA

6131

Skip if Clock Interrupt condition exists

6132
6133
6134
6135
6136
6137

AC to Clock Control register
AC to Clock Buffer-Preset register
AC to Clock Enable register
Clock Status to AC
Clock Buffer-Preset register to AC
Clock Counter to Buffer Preset register and AC.

Fixed-Interval Clock Type KW12-B, C

CSOF
CTOC

CTON

C-4

6131

Skip on clock flag.

6132
6134

Turn off the clock, clears the clock flag and disables the clock interrupt.
Turn the clock on and clears the flag.

Mnemonic

Operation

Octal

Fixed-Interval Clock Type KW12-B,C (cont)

CRUN

6135

Clock running. Turns on the clock, enables the clock interrupt, and clears the
clock

flag.

the clock flag was set when the instruction was issued, it will

skip.

Automatic Line Printer and Control Type LP12

LSE
LCF
LLB

LSD
LCB
LPR

6651

Skip if the printer done flag is a 1

6652
6654
6661
6662
6664

Clear both sections of the printing buffer.

Skip if line printer error flag is a 1
Clear line printer done and error flags.

Load printing buffer from the contents of AC5-1 1 and clear the AC.
Clear the format register, load the format register from the contents of

AC9 -1

print the line contained in the section of the printer buffer loaded

last, clear

the

AC, and advance the paper in accordance with the selected

channel of the format tape if the content of ACg = 1. If the content of ACg

= 0, the line is printed and paper advance is inhibited.
Line Printer Type LP08

LSF
LCF

LSR

6661

Skip on character flag.

6662
6663

Clear the character flag.

Skip on error status Une. (Error status line monitors interrupts caused by the
printer not being ready; i.e., power error, paper jam, out of paper, etc.)

6664

Load the character into the print buffer and print if buffer is full or character

LIN

6665

was a control function. This instruction does not clear the AC.
Set the program interrupts.

LLS

6666
6667

LPC

Enable

LIF

Microprogram combination of LCF and LPC.
Clear the program interrupt flag.

Card Reader and Control Type CR12

RCSF

663

Skip if card reader data ready flag is a 1

RCRA

6632

The alphanumeric code for the column is read into ACg-ij, and the data

RCRB

6634

ready flag is cleared.

The binary data in a card column is transferred into ACq-i 1

and the data

ready flag is cleared.

RCSP
RCSE

667

Skip if card reader card done flag is a 1

6672

Clear the card one flag, select the card reader and start card motion towards

RCRD

6674

the read station, and skip if the reader-not-ready flag is a 1.
Clear card done flag.

Automatic Magnetic Tape Control Type TC58

MTSF

6701

Skip on error flag or magnetic tape flag. The status of the error flag (EF) and
the magnetic tape flag (MTF) are sampled. If either or both are set to 1

contents of the

the

PC are incremented by one skipping the next sequential

instruction.

C-5

lOT Instructions (cont)

Table C-1.

Mnemonic

Operation

Octal

Automatic Magnetic Tape Control Type TC58 (cont)

MTCR

6711

Skip on tape control ready (TCR). If the tape control is ready to receive an
instructionn, the

PC is incremented by one skipping the next sequential

instruction.

MTTR

6721

Skip on tape transport ready (TTR). The next sequential instruction

skipped if the tape transport is ready.

MTAF

6712

Clear the status and command registers, and the EF and MTF if tape control
ready. If tape control not ready, clears MTF and EF flags only.

MTRC
MTCM

6724
6714

Inclusively
Inclusively
register;

MTLC
MTRS

MTGO

6716
6704
6706
6722

OR the contents of the command register into ACq-i
OR the contents of ACq-s and ACg-xi into the command
i

JAM transfer bits 6, 7, 8 (command function).

Load the contents of ACo-i i into the command register.
Inclusively

OR the contents of the status register into ACq-j

Read the contents of the status register into ACq-i i
Set "to" bit to execute instructions in the command register if instruction is
legal.

MCLA

6702

Clear the accumulator.

General Purpose Converter and Multiplexer Control Type AFOIA

ADSF

6531

Skip if A/D converter flag is a 1

ADVC

6532

Clear A/D converter flag and convert input voltage to a digital number; flag
will

set

end of conversion.

Number

of bits in converted

number

determined by switch setting, 1 1 bits maximum.

ADRB
ADCC
ADSC

6534

Read A/D converter buffer into AC, left justified, and clear flag.

6541

Clear multiplexer channel address register.

6542

Set up multiplexer channel as per ACg -j i

Maximum of 64 single-ended or

32 differential input channels.

ADIC

6544

Index multiplexer channel address (present address +

1).

address limit, increment will cause channel 00 to be selected.

C-6

Upon reaching

APPENDIX D

8-MODE PERFORATED - TAPE LOADER

READIN MODE LOADER
The readin mode (RIM) loader is a minimum length, basic, perforated-tape reader program for the 33 ASR. It is
stored in memory by manual use of the operator console keys and switches. The loader is permanently

initially

stored in 1 8 locations of page 37.

A perforated tape to be read by the RIM loader must be in RIM format:

87654S321

Tape Channel

Format
Leader-trail code

A3
XI

X3
1

A3
XI

X3
(Etc.)
1

A2
A4

Absolute address to contain next 4 digits

X2
X4

Contents of previous 4-digit address

A2
X2

Address

X2
X4

Content
(Etc.)

Leader-trailer code

The RIM loader can only be used in conjunction with the 33 ASR reader (not the high-speed perforated-tape
reader). Because a tape in RIM format is, in effect, twice as long as it need be, it is suggested that the RIM loader be

used only to read the binary loader when using the 33 ASR. (Note that some PDP-12 diagnostic program tapes are
in RIM format.)

D-1

The complete PDP-12 RIM loader (SA = 7756) is as follows:

Absolute

Octal

Address

Content

Tag

Instruction 1 Z

7756
7757

6032

BEG,

KCC

/CLEAR AC AND FLAG
/SKIP IF FLAG = 1

7760,

7766,

5357
6036
7106
7006
7510
5357
7006

KSF
JMP-1

7767,

6031

7770,

5367
6034
7420
3776
3376
5356

6031

7761,
7762,

7763,
7764,
7765,

7771,
7772,

7773,
7774,

7775,

KRB
CLL RTL
RTL
SPA

JMPBEG+1
RTL
KSF

/CHANNEL 8 IN ACO
/CHECKING FOR LEADER
/FOUND LEADER
/OK, CHANNEL 7 IN LINK

/READ, DO NOT CLEAR

KRS

DCA TEMP
DCA TEMP
JMP BEG

/CHECKING FOR ADDRESS
/STORE CONTENT
/STORE ADDRESS
/NEXT WORD
/TEMP STORAGE

JMPX

/JMP START OF BIN LOADER

SNL
1

5XXX

7777,

/LOOKING FOR CHARACTER
/READ BUFFER

JMP-1

TEMP,

7776,

Comments

Manually loading the RIM loader in core memory is accomplished as follows:
Set the starting address 7756 in the Left Switches.

Set the first instruction (6032) in the Right Switches.

Press the FILL Switch and then press the FILL STEP Switch.

Set the next instruction (603 1 ) in the Right Switches.

Press the FILL STEP Switch.

Repeat steps 4 and 5 until all 16 instructions have been deposited.

To ensure that RIM is in core, press Exam. The MA will = 7756, and the MB should = the first RIM

instruction (6032 for low-speed reader).
8.

To check sequential core locations, press Step Exam, and observe the contents of the MB.

To load a tape in RIM format, place the tape in the reader, set the Left Switches to the starting address 7756 of the
RIM loader (not of the program being read), press the START LS key, and start the Teletype reader.
Refer to Digital Program Library document Digital-8-l-U for additional information on the Readin Mode Loader

program.

BINARY LOADER (8 MODE)
The binary loader (BIN) is used to read machine language tapes (in binary format) produced by the program
assembly language (PAL). A tape in binary format is about one half the length of a comparable RIM format tape. It
can, therefore, be read about twice as fast as a RIM tape and is, for this reason, the more desirable format to use

with the 10 cps 33 ASR reader or the Type PRl 2 High-Speed Perforated-Tape Reader.

The format of a binary tape is as follows:

LEADER: About 2 feet of leader-trailer codes.

D-2

BODY:

Characters representing the absolute, machine language program in easy-to-read binary (or octal)

form. The selection of tape may contain characters representing instructions (channels 8 and 7 not punched)
or origin resettings (channel 8 not punched, channel 7 punched), and is concluded by 2 characters (channels 8

and 7 not punched) that represent a checksum for the entire section.

TRAILER: Same as leader.

BODY:

Characters representing the absolute, machine language program in easy-to-read binary (or octal)

and 7 not punched) that represent a checksum for the entire section.

TRAILER: Same as leader.
Tape Channel Memory
8

Location

Content

Comments
leader-trailer code

origin setting

0200

CLA

0201

TAD 277

0202

DCA 276

0203

HLT

0200

1
1

0277

origin setting

0053

1
1

1007

sum check
leader-trailer code

To load BIN
1.

Select the 8 mode.

Press the 10 Preset switch twice.

Put tape in the TTY reader, turn the reader on.

Press Start LS (still set to 7756).

When tape is read in, turn the reader off and stop the computer by pressing the Stop switch.

D-3

To load binary tapes with the BIN loader
1.

Place 7777 in Left Switches.

Set bit

of Right Switches to

for low-speed reader

(TTY) or set bit

of Right Switches to

for

high-speed reader.
3.

Press Start LS.

Tape is read in and computer halts.

AC unequal to 0000 a checksum error has occurred.

After a BIN tape has been read in, one of the two following conditions exists:

No checksum error: halt with AC =

Checksum error:

halt with

AC = (computed checksum) - (tape checksum)

Operation of the BIN loader in no way depends upon or uses the RIM loader. To load a tape in BIN format place
the tape in the reader, set the Left Switches to 7777 (the starting address of the BIN loader), set Right Switch
register bitoo

up for loading via the Teletype unit or down for loading via the high-speed perforated-tape reader,

then press the START LS key, and start the tape reader.

Refer to Digital Program Library document Digital-8-2-U-RIM for additional information on the Binary Loader
program.

APPENDIX E
TAPE MAINTENANCE INSTRUCTIONS

E.l

GENERAL

In the Maintenance Mode,

all

signals

from the tape transport are inhibited and data is simulated under program

control. This mode is especially useful for troubleshooting and checking the operation of the TCI 2 Tape Control

Logic.

E.2

TAPE MAINTENANCE INSTRUCTIONS

E.2.1

I0T6141

This instruction is used to load the Tape Maintenance Instruction Register (used with lOT 6 1 54) and to provide
data and timing information to the TCI 2 tape control unit when it is operating in the maintenance mode. It also

checks the status of the Tape Done flag. This instruction is not to be microprogrammed and it should not be used
to generate timing information during tape transfers, although it can be used to set the Tape Maintenance
Instruction Register at any time.

Any deviation from the above should be carefully checked with the logic diagrams to determine the expected
result. The functions of the

AC bits during this instruction are shown in Table E-1.
Table E-1.

AC Bit Functions

AC Bit Number

Function

Load into the Tape Maintenance Register (Bit 0)
Load into the Tape Maintenance Register (Bit 1
Load into the Tape Maintenance Register (Bit 2)
Load into the Tape Maintenance Register (Bit 3)
Clear the Tape Done Flag
Skip if Tape Done Flag is set

Generate TTO

Generate TT3

Simulate input data Mark Channel

Simulate input data Data Channel 1

Simulate input data Data Channel 2

Simulate input data Data Channel 3

00
01

02
03

E-1

E.2.2

IOT6152

This instruction is used to generate various control pulses within the TCI 2 Tape control unit. These control signals
are

used

primarily

for maintenance purposes.

In special situations

these

controls are useful

for handling

nonstandard tape formats.

The bits of instruction 6152 are gated with individual bits of AC register to generate a specific control function.
These functions are intended to be used singly, and not while a tape instruction is in progress, and this instruction
cannot be microprogrammed. Any deviation from the above should be carefully checked with the logic diagrams to
determine the exact result. The functions of the AC bits during this instruction are shown in Table E-2.

Table E-2.

AC Bit Functions

AC Bit Number

Function

Tape Preset

RWB

Shift

TB ^ RWB
TB + TAC -> TAC

03
04*

Clear 8 Block

05*

Set Direction Backward

06*

Select Unit number 1

07*

Set Direction Forward

08*

Set Write Sync

09*

Set Motion. Set Direction Forward if motion

10*
11*

Select 8 Tape

was cleared

ACi

^ 8 Write Flip-Flop

*These Bits are used in the TC12-F Tape Control

E.2.3

IOT6154

This instruction is used to load and examine the various registers of the TCI 2 Tape Control Unit. The action of this
instruction is controlled by the contents of the Tape Maintenance Instruction Register and this action is shown in

Table E-3. This instruction is not to be used during the operation of a tape instruction.
Table E-3.

lOT 6154 Effect of Tape Maintenance Instruction

Contents of bits 0, 1

E-2

2,&3

Binary

Octal

0000

0001

0010

0011

Function Performed

AC->TB
AC ^ TBN
AC -* TAC
AC -> TMA

0100

TMA Setup ^ AC

0101

TBN -> AC

Table E-3.

lOT 61 54 Effect of Tape Maintenance Instruction (cont)

Contents of bits 0, 1

E.2.4

Function Performed

Binary

Octal

0110

0111

TB->AC
RWB -> AC

1000

Mark Window ^ AC

1001

Control States, Timing -> AC

1010

Units & MTN -* AC

1011

Tape Inst ^ AC

1100

Misc. Status

1101

Misc. Status 2

1110

TMA ^ AC

nil

^ AC

lOT 6154 Detailed Transfer Information

The Tape Maintenance Instruction Register is decoded to give a count of OOg to Hg. These count levels generate
the signals necessary to enable the selected data onto the Tape Bus for a 1 2-bit parallel transfer between the AC
and the Tape Registers. The following tables show the contents of the AC after the instruction associated with each
table is given.

Table E-4, Tape Maintenance Instruction Register Equal 1 Og

Mark Window ^ AC

AC Bit

Data Read into AC

LWN Wind Shade (1)
LWN Wind 00(1)
LWN Wind 01 (1)
LWN Wind 02(1)
LWN Wind 03(1)
LWN EM
LWN CM

LWNGM

LWN DM

09
10

LWNFM
LWNBM

LWNIM

02
03

04
05

E-3

Table E-5. Tape Maintenance Instruction Register Equals 1 Ig
Control States & Timing -> AC

AC Bit

Data Read Into AC

TAC = 7777

LCSIdle(l)

LCS Search (1)
LCS Block (1)
LCS Check Word (1)
LCS Turn Around (1)
LCS Write (1)
LCS Write Cycle (1)
LTD ACIP

04
05

06
07
08

LTD TTOK
LTD Timing OK
LTD Tape Fail Delay

09
10
11

Table E-6. Tape Maintenance Instructions Register Equals 1 2^,
Units & Motion - AC

AC Bit

Data Read Into AC

LTC Unit (0)
LTC Unit 1 (0)
LTC Unit 2 (0)
LTC Unit 3 (0)
LTC Unit 4 (0)
LTC Unit 5 (0)
LTC Unit 6 (0)
LTC Unit 7 (0)

02
03

04
05

06
07
08
09
10

LMU motion (1)
LMU Direction (1)
LCS Tape OK (1)

LTC Write EN (1)

Table E-7. Tape Maintenance Instruction Register Equals \3g

TINSTR -- AC

AC Bit

Data Read Into AC

LIN RDC
LIN RCG
LIN RDE
LIN MTB
LIN WRC
LIN WRG
LIN WRI

02
03

04
05

E-4

Table E-7. Tape Maintenance Instruction Register Equals ISg (cont)

TINSTR - AC

AC Bit

Data Read Into AC

LIN CHK
LIN I (1)

LGPGPO(l)

LGPGP

LGPGP2(1)

(1)

Table E-8. Tape Maintenance Instruction Register Equals 14 g

MSC Status 1

AC Bit

Data Read Into AC

LTS PHASE

LIP IN PROGRESS (1)

LTS LCOO (1)
LTS LC 01 (1)

Mark Chan Write
Data Chan 1 Write
Data Chan 2 Write
Data Chan 3 Write
LGPGP = GPC(1)

LGPGPCNTO(l)

LGPGPCNTl (1)
LGPGPCNT2(1)

04
05

06
07

Table E-9. Tape Maintenance Instruction Register Equals 15f

MSC Status 2

AC Bit

Data Read Into AC

TCI 2-F WRITE SEL (1)
TC12-F TAPE SEL(l)

00
01

04
05

Not used

08
09
10
11

E-5

APPENDIX F
TABLES OF CODES

Table F-1

Model 33/35 ASR/KSR Teletype Code (ASCII) in Octal Form

8-Bit Code

Character

8-Bit Code

Character
(in octal)

(in octal)

301

241

242

302

303

243

304

244

305

245

306

%
&

307

247

310

(

250

311

)

251

312

246

252

313

253

314

254

315

316
317

255
256

257

272

320

321

;

273

322

274

323

275

T
U
V

324

276

325

277

326

300

327

[

333

X
Y

330

334

331

]

335

332

336

•<-

337

260
1

261

Leader/Trailer

200

262

Line-Feed

212

263

Carriage-Return

215

264

Space

240

265

Rub-out

377

266

Blank

000

267

alt-mode

375

270

escape

233

271

F-1

Table F-2. Model 33 ASR/KSR Teletype Code (ASCII) in Binary Form

HOLE PUNCHED = MARK
NO HOLE PUNCHED = SPACE

MOST SIGNIFICANT BIT
LEAST SIGNIFICANT BIT

^"8 7 6 5 4 s 3 2 \^
1'

SPACE

••

1
1

END OF MESSAGE

END OF TRANSMISSION

WHO ARE YOU

ARE YOU

BELL

(

FORMAT EFFECTOR

)

VERTICAL TAB

FORM FEED

CARRIAGE RETURN

SHIFT OUT

LINE FEED

—

DCO
1

READER ON

TAPE (AUX ON)

READER OFF

(AUX OFF)

ERROR

SYNCHRONOUS IDLE

LOGICAL END OF MEDIA

RUB OUT
I

S6
S7

]

[

^-^ ^

^
^

SAMP

-W

SAME

SAME
r.^ ..-

F-2

SHIFT IN

HORIZONTAL TAB

•

START OF MESSAGE

END OF ADDRESS

NULL/IDLE

aMryic.

Table F-3. LT-37 Transmit and Receive Code Table

33 ASR MODE

37 KSR MODE

SHIFT

NOT SHIFT

CHARACTER CODE

NOT SHIFT

SHIFT

CHARACTER CODE

CHARACTER

CODE

101

341

301

102

342

302

303

143

104

344

303
304

E
F

305

145

305

306

146

G
H

107

110

347
350

G
H

306
307
310

311

151

311

312

152

113

353

314

154

312
313

115

355

116

356

360

314
315
316
317
320

321

322
323
324
325

157

317

120

Q
R

321

161

322

162

123

324

363
164

125

365

126

366

U
V

327

167

X
Y

330

170

131

X
Y

330

371

132

372

332

SPACE

240

U
V

#
$

%
&
>

(
)

;

42
243
44
245

246
47
250

60
1

2
3

4
5

6
7

261

262
63
264
65
66
267
270

240

241

242

243

244

%
&

245

246

247

(

250

262
263
264
265
266
267
270

251

271

272

252

273

253

)

252

254

276

256

257

277

140

300

173

[

333

374

334

254

275

276
77

@
[

300
333

{

134

261

274
275

;

260

<
>

331

SPACE

251

273

326
327

255

257

F-3

Table F-3. LT-37 Transmit and Receive Code Table (cont)

37 KSR MODE

33 ASR MODE

NOT SHIFT

SHIFT

CHARACTER

CODE

]

335

336

^•

CHARACTER

137

~
DEL

NULL

000

DLE

SOH
STX
ETX
EOT

201
3

DCl
DC2
DC3

204

DC4

ENQ
ACK

NAK

202

vTAB

FORM
RETURN
So
Si

OR MODE

220

NULL

200

DEL
DLE

SOH

201

DCl

221

22
223
24
225

STX

202
203
204

DC2
DC3
DC4

222
223
224

205

NAK

225

206

226
227
230

377

SUB
ESCAPE

215

GS
RS
QS

213

216
217

EXT
EOT
ENQ
ACK
BELL
BACK SPACE

375

377
220

210

SYNC
ETB
CANCEL

211

231

232

^TAB
NEW LINE

212

vTAB

234
35

FORM
RETURN

232
233
234
233
236

237

213
214
215
216
217

SUB
ESCAPE

207

GS
RS
QS

NOTE
Letter codes transmitted from the 37 KSR keyboard in 33 mode will be upper case
regardless of the position of the shift key; however, letter codes received by the KSR

37 in 33 mode will be printed in upper or lower case, as received.

F-4

CODE

ALT

231

210

CHARACTER

336
337

BACK SPACE

CODE
335

]

176

207

CHARACTER

175

226

BELL

^TAB
NEW LINE

CODE

SYNC
ETB
CANCEL

NOT SHIFT

SHIFT

237

Table F-4. Card Reader Codes

The following table gives the octal representation of the internal (binary) codes for the Hsted punch combinations.
These internal codes are generated by the card reader and are transmitted to the PDP-12 upon execution of the
appropriate lOT instruction. Any combination of punches which is not shown in the table is invalid, and the card
reader can not detect invalid combinations.

Card Code

Zone

Num.

Internal

Character

Code
00 0000

8-2

1010

8-3

1011

Card Code

Internal

Zone Num.

Code

Character

G
H

Space

0111

[

1000

•

1001

10 0001

8-4

1100

8-5

1101

(

10 0010

1110

10 0011

10 0100

M
N

8-6

8-7

nil

0000

10 0101

8-2

10 1010

10 Olio

8-3

10 1011

10 0111

10 1100

$
*

8-4

10 1000

8-5

10 1101

)

10 1001

8-6

10 1110

;

01 0010

8-7

nil

01 0011

10 0000

—

01 0100

0001

01 0101

U
V

8-2

1010

]

01 Olio

8-3

1011

0111

8-4

1100

1000

X
Y

8-5

1101

<r-

1001

8-6

1110

8-7

nil

00 0001

8-3

00 1011

00 0010

8-4

00 1100

8-5

00 1101

8-6

00 1110

8-7

nil

0001

00 1010

00 0011

00 0100

00 0101
00 Olio

00 0111

0010

0011

00 1000
00 1001

0100

0101

Olio

E
F

F-5

Table F-5. LP08 Line Printer Code

64-Character Printer

___A__

r
AGs

AG9

AGj

1
1
1

%
&

E
F

U
V

(

G
H

)

X
Y

[

*
*

•

{

]

Y
96-Character Printer

F-6

B
C

•II

1
1

space

AC7

AGs

Table F-6. LPl 2 Automatic Line Printer Code

Character

6-Bit Code

Character

6-Bit Code

(ASCII)

(in octal)

(ASCII)

(in octal)

&
'

43
44
45
46
47

(

)

53
54
55
56
57
60

50
51

23
24
25

W
X
Y
Z
[

\
]
t

26
27
30

6
7
8

63
64
65
66
67
70

32
33

;

72
73

34
35
36
37

4
5

<
=

75
76

F-7/F-8

APPENDIX G

CABLE CONNECTIONS TO PDP-12 FRONT PANEL

Access to analog channels 10-17 and the extension scope socket is by means of the relay and analog input panel
(see Figure 2-3),

The addition of 16 channels of analog input with the AG12 option, 16 additional preamplifiers,

connects channels 208 to 37 g to the analog extension panel supplied with the option.

Analog knobs Og to 1^, analog channels lOg to 37s, console scope display, and extension scope display utilize the
following connectors and connect to the following module slots in the EM 12 memory wing:
Front Panel Connector

Module Slot

Analog Knobs 08-7g

5K, 1 0-turn Potentiometers

Analog Chan lOg-Hg

Switchcraft JAX#13B

F33
F32

Analog Chan 20g-278

Amphenol 26-440 1-32P
Amphenol 26-440 1-32P
Amphenol 26-440 1-24P
Amphenol 57-30240

Device

Analog Chan 308 -37g
Extension Scope Display

Console Display

F31

F30
F39
F38

Table G-1 hsts cable connections and signal names from each front panel termination to its corresponding slot in
the

EM 12 memory wing.

G-1

Table G-1

Cable Connections for PDP-1 2 Front Panel

FRONT
DEVICE

SIGNAL NAME

Analog

+7 volts

Knobs

0-7

Analog
Channels
10-17

MODULE

PANEL PIN

7 volts
All Knobs

Analog Chan 7
Analog Chan 6
Analog Chan 5
Analog Chan 4
Analog Chan 3
Analog Chan 2
Analog Chan 1
Analog Chan

All Knobs

Knob 7
Knob 6
Knob 5
Knob 4
Knob 3
Knob 2

Knobl
KnobO

SIGNAL NAME

FRONT PANEL PIN

SLOT PIN

- Analog Chan 10
+ Analog Chan 10
Analog Chan 1
+ Analog Chan 1
- Analog Chan 12
-H Analog Chan 12
- Analog Chan 1
-H Analog Chan 13
Analog Chan 14
+ Analog Chan 14
- Analog Chan 15
+ Analog Chan 15
- Analog Chan 16
+ Analog Chan 16
- Analog Chan 17
+ Analog Chan 17

Analog Phone Jack 10
Analog Phone Jack 10
Analog Phone Jack 1
Analog Phone Jack 1
Analog Phone Jack 12
Analog Phone Jack 12
Analog Phone Jack 13
Analog Phone Jack 13
Analog Phone Jack 14
Analog Phone Jack 14
Analog Phone Jack 15
Analog Phone Jack 1
Analog Phone Jack 16
Analog Phone Jack 16
Analog Phone Jack 1
Analog Phone Jack 17

Ul
VI

Bl
CI

Dl
El

HI
Jl

Kl
LI

Ml
Nl
PI
SI

Analog
Channels

- Analog Chan 20
+ Analog Chan 20

Analog Chan 30
+ Analog Chan 30

20-37

DRAIN

GND

- Analog Chan 21
+ Analog Chan 21

Analog Chan 31
+ Analog Chan 31

2
3
4
5

DRAIN

6
7
8

6
7

GND

Analog Chan 22
+ Analog Chan 22
-

DRAIN
Analog Chan 32
+ Analog Chan 32

9
10

DRAIN
Analog Chan 33

9
10

GND

Analog Chan 23

+ Analog Chan 23

+ Analog Chan 33

DRAIN

13
14

Analog Chan 34
+ Analog Chan 34

12
13
14

GND

Analog Chan 24
+ Analog Chan 24

DRAIN

15
16

GND

Analog Chan 25
+ Analog Chan 25

DRAIN

DRAIN
-

- Analog Chan 26
+ Analog Chan 26

DRAIN
-1-

Analog Chan 27
Analog Chan 27

DRAIN
Console

DSX Chan Sel. (1) H

Display

System GND

and

Ml
Nl

Analog Chan 35
+ Analog Chan 35

DRAIN

GND

30
29
28
27
26

- Analog Chan 36
+ Analog Chan 36

30
29

Analog Chan 37
+ Analog Chan 37

28
27
26

GND

DRAIN

GND

DRAIN

Ul
VI

DRAIN

2
3

GND

Extension

DSC Intensity L

Scope

System GND

CI
Dl

GND

Display

DRAIN

XHQGND

DSX X Defl.
DRAIN

9
10

GND

Y HQ GND

Type 503 Scope
Connections

G-2

DSY Y Defl.
DRAIN

GND

503 Intensify
System GND

DRAIN

GND

APPENDIX H

MATHEMATICAL DATA

Scales of Notation

2" IN De cima
2-

33874 62581
72557 11335
16050 79633
64359 01078
17485 09503
75432 38973
38204 23785
05803 98468
78234 97782

1.0O069
1.00138
1.00208
1.00277
1.00347
1.00416
1.00486
1.0O556
1,00625

0.001

0.002
0.003
0.004

0005
0.006

0007
0.008
0.009

0.03
0.04
0.05
0.06
0.07
0.08
0.09

10'*"'^

144
750
23 420

?
3

303 ?40
641 100
113 ?00
360 400
545 000

5
6

46
575
346

55500 56719
94797 90029
21257 07193
38266 56067
49238 41377
57608 41121
66836 23067
80405 61380
01824 53360

1.00695
1.01395
1.02101
1.02811
1.03526
1.04246
1.04971
1.05701
1.06437

0.01
0.02

146
243
651
0.000 032 155 613 530 704

476 132 610 706
206 157 364 055
015 327 745 152
001 257 143 561
000 104 560 276

64
37
75

3.32192
6.64385
9.96578
13.28771
16.60964

1.20411 99827
1.50514 99783

4
5

14869 83549 97035
44133 44916
79107 72894
35623 73095
65665 10398
47927 12471
11265 92248
59830 73615

1.23114
1.31950
1.41421
1.51571
1.62450
1.74110
1.86606

10"

16 432 451 210 000
221 411 634 520 000
657 142 036 440 000

0.000
0.000
0.000
0.000
0.000

000
000
000
000
000

000 006 676 337 66
000 000 537 657 77
000 000 043 136 32
000 000 003 411 35
000 000 000 264 11

500 000
200 000
400 000
000 000

0.000
0.000
0.000
0.000

000
000
000
000

000 000 000
000 000 000
000 oOO 000
000 000 000

66
77
15

34 327 724 461
434 157 115 760
5 432 127 413 542
67 405 553 164 731

022 01
001 63
000 14
000 01

Decimal
n logio 2

n log2 10

n logio 2
0.30102 99957
0.60205 99913
0.90308 99870

0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9

112 402 762 000
351 035 564 000

000 00

n log,^ 2, n log 2 10 IN

1.07177 34625 36293

10"

1.000 000 000 000 000
0.063 146 314 631 463
0.005 075 341 217 270
0.000 406 111 564 570

0.000 002
0.000 000
0.000 000
0.000 000
0.000 000

X
0.1

IN Octal

10-

10"

80949
61898
42847
23795
04744

n log!
19.93156
23.25349
26.57542
29.89735
33.21928

1.80617 99740
2.10720 99696
2.40823 99653
2.70926 99610
3.01029 99566

6
7

8
9

10
85693
66642
47591
28540
09489

Addition and Multiplication Tables
Multiplication

Addition

Binary Scale

+
4

-1-

0X0 =
0X1 = 1X0 =
1X1 =

= 1
= 10

Octal Scale
01

Mathematical Constants in Octal Scale

In w

log] n

vlo

3.11037

552421,

= 2.55760

521305,

0.24276

301556,

e-i

- 0.27426

530661,

In >

1.61337

611067,

VT=

1.11206
1.51544

3.12305

0.44742 147707,

0.43127 233602,

logo ^^ - .0.62573 030645,

1.51411

230704,

404435,

logio e = 0.33626

754251,

V2"=

1.32404

746320,

163223,

logie =

1.34252

166245.

In 2

0.54271

027760,

407267,

log) 10 =

3.24464

741136.

2.23273

067355,

H-1

Powers of Two
-n

0,5

1.0

0.25

8
16

0,125
0.062 5
0.031 25
0.015 625
0.007 812 5
0.003 906 25
0.001 953 125
0.000 976 562 5
0.000 488 281 25
0.000 244 140 625
0.000 122 070 312 5
0.000 061 035 156 25
0.000 030 517 578 125
0.000 015 258 789 062 5
0.000 007 629 394 531 25
0.000 003 814 697 265 625
0.000 001 907 348 632 812 5
0.000 000 953 674 316 406 25
0.000 000 476 837 158 203 125
0.000 000 238 418. 579 101 562 5
0.000 000 119 209 289 550 781 25
0.000 000 059 604 644 775 390 625
0.000 000 029 802 322 387 695 312 5
0.000 000 014 901 161 193 847 656 25
0.000 000 007 450 580 596 923 828 125
0.000 000 003 725 290 298 461 914 062 5
0.000 000 001 862 645 149 230 957 031 25
0.000 000 000 931 322 574 615 478 515 625
0.000 000 000 465 661 287 307 739 257 812 5
0.000 000 000 232 830 643 653 869 628 906 25
0.000 000 000 116 415 321 826 934 814 453 125
0.000 000 000 058 207 660 913 467 407 226 562 5
0.000 000 000 029 103 830 456 733 703 613 281 25
0.000 000 000 014 551 915 228 366 851 806 640 625
0.000 000 000 007 275 957 614 183 425 903 320 312 5
0.000 000 000 003 637 978 807 091 712 951 660 156 25
0.000 000 000 001 818 989 403 545 856 475 830 078 125
0.000 000 000 000 909 494 701 772 928 237 915 039 062
0.000 000 000 000 454 747 350 886 464 118 957 519 531
0.000 000 000 000 227 573 675 443 232 059 478 759 765
0.000 000 000 000 1 13 686 837 721 616 029 739 379 882

32
64
128
256
512
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
262 144
524 288
1
048 576
2 097 152
4 194 304
8 388 608
16 777 216
33 554 432
67 108 864
134 217 728
268 435 456
536 870 912
1 073 741 824
2 147 483 648
4 294 967 296
8 589 934 592
17 179 869 184
34 359 738 368
68 719 476 736
137 438 953 472
274 877 906 944
549 755 813 888
1 099 511 627 776
2 199 023 255 552
4 398 046 511 104
8 796 093 022 208
17 592 186 044 416
35 184 372 088 832
70 368 744 177 664
140 737 488 355 328
281 474 976 710 656
562 949 953 421 312
125 899 906 842 624
1
2 251 799 813 685 248
4 503 599 627 370 496
9 007 199 254 740 992
18 014 398 509 481 984
36 028 797 018 963 968
72 057 594 037 927 936
144 115 188 075 855 872
288 230 376 151 711 744
576 460 752 303 423 488
152 921 504 606 846 976
1
2 305 843 009 213 693 952
4 611 686 018 427 387 904
9 223 372 036 854 775 808
18 446 744 073 709 551 616
36 893 488 147 419 103 232
73 786 976 294 838 206 464
147 573 952 589 676 412 928
295 147 905 179 352 825 856
590 295 810 358 705 651 712
180 591 620 717 411 303 424
1
2 361 183 241 434 822 606 848
4 722 366 462 869 645 213 696

H-2

6
7

9
10
11

12
13
14
15

16
17
18
19

20
21

22
23
24
25
26
27
28
29

30
31

32
33
34
35
36
37
38
39
40
41

42
43
44
45
46
47
48
49
50
51

52
53
54
55
56
57
58
59

60
61

62
63
64
65
66
67
68
69
70
71

25
625
812 5
000 000 000 000 056 843 418 860 808 014 869 689 941 406 25
0.000 000 000 000 028 421 709 430 404 007 434 844 970 703 125
0.000 000 000 000 014 210 854 715 202 003 717 422 485 351 562 5
000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25
0.000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625
0.000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312 5
0.000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656 25
O.OOO 000 000 000 000 444 089 209 850 062 616 169 452 667 236 328 125
0.000 000 000 000 000 222 044 604 925 031 308 084 726 333 618 164 062 5
0.000 000 000 000 000 HI 022 302 462 515 654 042 363 166 809 082 031 25
0.000 000 000 000 pOO 055 511 151 231 257 827 021 181 583 404 541 015 625
0.000 000 000 000 000 027 755 575 615 628 913 510 590 791 702 270 5u7 812 5
0.000 000 000 000 000 013 877 787 807 814 456 755 295 395 851 135 253 906 25
0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 925 567 626 953 125
0.000 000 000 000 000 003 469 446 951 953 614 188 823 848 962 783 813 476 562 5
0.000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 391 906 738 281 25
0.000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140 625
0.000 000 000 000 000 000 433 680 868 994 201 773 602 981 120 347 976 684 570 312 5
0.000 000 000 000 000 000 216 840 434 497 100 886 801 490 560 173 988 342 285 156 25
0.000 000 000 000 000 000 108 420 217 248 550 443 400 745 280 086 994 171 142 578 125
0.000 000 000 000 000 000 054 210 108 624 275 221 700 372 640 043 497 085 571 289 062 5
0.000 000 000 000 000 000 027 105 054 312 137 610 850 186 320 021 748 542 785 644 531 25
000 000 000 000 000 000 013 552 527 156 C68 805 425 093 160 010 874 271 392 822 265 625
000 000 000 000 000 000 006 776 263 578 034 402 712 546 580 005 437 135 696 411 132 812 5
0.000 000 000 000 000 000 003 388 131 789 017 201 356 273 290 002 718 567 848 205 566 406 25
000 000 000 000 000 000 001 694 065 894 508 600 678 136 645 001 359 283 924 102 783 203 125
0.000 000 000 000 000 000 000 847 032 947 254 300 339 068 322 500 679 641 962 051 391 601 562 5
0.000 000 000 000 000 000 000 423 516 473 627 150 169 534 161 250 339 820 981 025 695 800 781 25
0.000 000 000 000 000 000 000 211 758 236 813 575 084 767 080 625 169 910 490 512 847 900 390 625

Octal -Decimal Integer Conversion Table
1

0000

0777

0511

<Octal)

(Datimol)

Octal

Decimal

4096
10000
8192
20000
30000 12288
40000 16384
50000 20480
60000 24576
70000 28672

0000
0010
0020
0030
0040
0050
0060
0070

0000
0O08
0016
0024
0032
0040
0048
0056

0512

1777

1023

(Octal)

(Dvcimol)

0001 0002 ooo;} 0004 0005
0009 0010 0011 0012 0013
0017 0018 0019 0020 0021
0025 0026 0027 0028 0029
0033 0034 0035 0036 0037
0041 0042 0043 0044 0045
0049 0050 0051 0052 0053
0057 0058 0059 0060 0061

0100
0110
0120
0130

0064 0065
0072 0073
0080 0081
0088 0089
OHO 0096 0097
0150 0104 0105
0160 0112 0113
0170 0120 0121

0066
0074
0082
0090
0098
0106
0114
0122

0200
0210
0220
0230
0240
0250
0260
0270

0128
0136
0144
0152
0160
0168
0176
0164

0129
0137
0145
0153
0161
0169
0177
0185

0130
0138
0146
0154
0162
0170
0178
0186

0300
0310
0320
0330
0340
0350
0360
0370

0192
0200
0208
0216
0224
0232
0240
0248

0193
0201
0209
0217
0225

0194
0202
0210
0218
0226
0233 0234
0241 0242
0249 0250

1000

0067
0075
0083
0091
0099
0107
0115
0123

0068
0076
0084
0092
0100
0108
0116
0124

0132
0140
0148
0156
0164
0171 0172
0179 0180
0187 0188
0131

0139
0147
0155
0163

0069
0077
0085
0093
0101
0109
0117
0125

0006
0014
0022
0030
0038
0046
0054
0062

0007
0015
0023
0031
0039
0047
0055
0063

0400
0410
0420
0430
0440
0450
0460
0470

0256
0264
0272
0280
0288
0296
0304
0312

0257 0258 0259
0265 0266 0267
0273 0274 0275
0281 0282 0283
0289 0290 0291
0297 0298 0299
0305 0306 0307
0313 0314 0315

0070
0078
0086
0094
0102
0110
0118
0126

0071

0500
0510
0520
0530
0540
0550
0560
0570

0320
0328
0336
0344
0352
0360
0368
0376

0321

0191

0600
0610
0620
0630
0640
0650
0660
0670

0384
0392
0400
0408
0416
0424
0432
0440

0385 0366 0387
0393 0394 0395
0401 0402 0403
0409 0410 0411
0417 0418 0419
0425 0426 0427
0433 0434 0435
0441 0442 0443

0700
0710
0720
0730
0740
0750
0760
0770

0448
0456
0464
0472
0480
0488
0496
0504

0449
0457
0465
0473
0481
0489
0497
0505

0450
0458
0466
0474
0482
0490
0498
0506

0451
0459
0467
0475
0483
0491

077p
0778
0786
0794
0802
0810
0818
0826

0771

0772
0780
0788
0796
0804
0812
0820
0828

0773
0781
0789
0797
0805
0813
0821
0829

0774
0782
0790
0798
0806
0814
0822
0830

0775
0783

0835 0836 0837
0843 0844 0845
0851 0852 0853
0859 0860 0861
0867 0868 0869
0875 0876 0877
0883 0884 0885
0891 0892 0893

0838
0846
0854
0862
0870
0878
0886
0894

0839
0847
0855
0863
0871
087S
0887
0895

0133 0134
0141 0142
0149 0150
0157 0158
0165 0166
0173 0174
0181 0182
0189 0190

0079
0087
0095
0103
0111
0119
0127

0135
0143
0151
0159
0167
0175

0183

0195 0196 0197
0203 0204 0205
0211 0212 0213
0219 0220 0221
0227 0228 0229
0235 0236 0237
0243 0244 0245
0251 0252 0253

0198
0206
0214
0222
0230
0238
0246
0254

0199
0207
0215
0223
0231
0239
0247
0255

1000
1010
1020
1030
1040
1050
1060
1070

0512
0520
0528
0536
0544
0552
0560
0568

0513 0514
0521 0522
0529 0530
0537 0538
0545 0546
0553 0554
0561 0562
0569 0570

0515 0516 0517
0523 0524 0525
0531 0532 0533
0539 0540 0541
0547 0548 0549
0555 0556 0557
0563 0564 0565
0571 0572 0573

0518
0526
0534
0542
0550
0558
0566
0574

0519
0527
0535
0543

1100
1110
1120
1130
1140
1150
1160
1170

0576
0584
0592
0600
0608
0616
0624
0632

0577
0585
0593
0601
0609
0617
0625
0633

0579
0587
0595
0603
0611
0619
0627
0635

0581
0889
0597
0605
0613
0621
0629
0637

0582
0590
0598
0606
0614
0622
0630
0638

0583
0591
0599
0607
0615
0623

1200
1210
1220
1230
1240
1250
1260
1270

0640
0648
0656
0664
0672
0680
0688
0696

0641

1300
1310
1320
1330
1340
1350
1360
1370

0704
0712
0720
0728
0736
0744
0752
0760

0705 0706 0707
0713 0714 0715
0721 0722 0723
0729 0730 0731
0737 0738 0739
0745 0746 0747
0753 0754 0755
0761 0762 0763

0578
0586
0594
0602
0610
0618
0626
0634

0642
0650
0658
0666
0674
0681 0682
0689 0690
0697 0698
0649
0657
0665
0673

0580
0588
0596
0604
0612
0620
0628
0636

0643 0644
0651 0652
0659 0660
0667 0668
0675 0676
0683 0684
0691 0692
0699 0700
0708
0716
0724
0732
0740
0748
0756
0764

0329
0337
0345
0353
0361

0369
0377

0322
0330
0338
0346
0354
0362
0370
0378

0260
0268
0276
0284
0292
0300
0308
0316

0261
0269
0277
0285
0293
0301
0309
0317

0262
0270
0278
0286
0294
0302
0310
0318

0263

0323 0324
0331 0332
0339 0340
0347 0348
0355 0356
0363 0364
0371 0372
0379 0380
0386
0396
0404
0412
0420
0428
0436
0444

0452
0460
0468
0476
0484
0492
0499 0500
0507 0508

0271

0279
0287
0295
0303
0311

0319

0325 0326 0327
0333 0334 0335
0341 0342 0343
0349 0350 0351
0357 0358 0359
0365 0366 0367
0373 0374 0375
0381 0382 0383
0389
0397
0405
0413
0421
0429
0437
0445

0390
0398
0406
0414
0422
0430
0438
0446

0391

0453 0454
0461 0462
0469 0470
0477 0478
0485 0486
0493 0494
0501 0502
0509 0510

0455
0463
0471
0479
0487
0495
0503
0511

0399
0407
0415
0423
0431

0439
0447

1400
1410
1420
1430
1443
1450
1460
1470

0768
0776
0784
0792
0800
0808
0816
0824

0769
0777
0785
0793
0801
0809
0817
0825

0631
0639

1500
1510
1520
1530
1540
1550
1560
1570

0832
0840
0848
0856
0864
0872
0880
0888

0833 0834
0841 0842
0849 0850
0857 0858
0865 0866
0873 0874
0881 0882
0889 0890

0645 0646 0647
0653 0654 0655
0661 0662 0663
0669 0670 0671
0677 0678 0679
0685 0686 0687
0693 0694 0695
0701 0702 0703

1600
1610
1620
1630
1640
1650
1660
1670

0896
0904
0912
0920
0928
0936
0944
0952

0897 0898 0899 0900
0905 0906 0907 0908
0913 0914 0915 0916
0921 0922 0923 0924
0929 0930 0931 0932
0937 0938 0939 0940
0945 0946 0947 0948
0953 0954 0955 0956

0901 0902 0903
0909 0910 0911
0917 0918 0919
0925 0926 0927
0933 0934 0935
0941 0942 0943
0949 0950 0951
0957 0958 0959

0710
0718
0726
0734
0741 0742
0749 0750
0757 0758
0765 0766

1700
1710
1720
1730
1740
1750
1760
1770

0960
0968
0976
0984
0992
1000
1008
1016

0961

0962
0970
0978
0986
0994
1001 1002
1009 1010
1017 1018

0965
0973
0981
0989
0997
1005
1013
1021

0709
0717
0725
0733

0551

0559
0567
0575

0711
0719
0727
0735

0743
0751

0759
0767

0969
0977
0985
0993

0779
0787
0795
0803
0811
0819
0827

0963 0964
0971 0972
0980
0988
0996
1004
1011 1012
1019 1020

0979
0987
0995
1003

0966
0974
0982
0990
0098
1006
1014
1022

0791

0799
0807
0815
0823
0831

0967
0975
0983
0991
0999
1007
1015
1023

H-3

Octal-Decimal Integer Conversion Table (Cont)
2

1026 1027
1034 1035
1041 1042 1043
1049 1050 1051
1057 1058 1059
1065 1066 1067
1073 1074 1075
1080 1081 1082 1083

1024
1032
1040
1048
1056
1064
1072

2100
2110
2120
2130
2140
2IS0
2160
2170

1088
1096
1104
1112
1120
112B
1136
1144

1089
1097
1105
1113
1121
1129
1137
1145

2200
2210
2220
2230
2240
2250
2260
2270

1152
1160
1168
1176
1184
1192
1200
1208

1153

2300
2310
2320
2330
2340
2350
2360
2370

1216
1224
1232
1240
1248
1256
1264
1272

1025
1033

2000
2010
2020
2030
2040
2050
2060
2070

1090 1091
1098 1099
1106 1107
1114 1115
1122 1123
1130 1131
1138 1139
114C 1147

•

1030
1038
1046
1054
1062
1070
1078
1086

1031
1039
1047
1055

1282
1290
1298
1306
1314
1322
1330
1338

1283
1291
1299
1307
1315
1323
1331
1339

1284
1292
1300
1308
1316
1324
1332
1340

1285
1293
1301
1309
1317
1325
1333
1341

1286
1294
1302
1310
1318
1326
1334
1342

1287
1295
1303
1311
1319
1327
1335
1343

1281

1063
1071
1079
1087

1092 1093 1094 1095
1100 1101 1102 1103
1108 1109 1110 nil
1116 1117 1118 1119
1124 1125 1126 1127
1132 1133 1134 1135
1140 1141 1142 1143
1148 1149 1150 1151

2500
2510
2520
2530
2540
2550
2560
2570

1344
1352
1360
1368
1376
1384
1392
1400

1345 1346 1347 1348 1349
1353 1354 1355 1356 1357
1361 1362 1363 1364 1365
1369 1370 1371 1372 1373
1377 1378 1379 1380 1381
1385 1386 1387 1388 1389
1393 1394 1395 1396 1397
1401 1402 1403 1404 1405

1350
1358
1366
1374
1382
1390
1398
1406

1351
1359
1367
1375
1383
1391
1399
1407

2600
2610
2620
2630
2640
2650
2660
2670

1408 1409
1416 1417
1424 1425
1432 1433
1440 1441
1448 1449
1456 1457
1464 1465

1410
1418
1426
1434
1442
1450
1458
1466

1411

1412 1413
1420 1421
1428 1429
1436 1437
1444 1445
1452 1453
1460 1461
1468 1469

1414
1422
1430
1438
1446
1454
1462
1470

1415
1423
1431
1439
1447
145S
1463
1471

2700
2710
2720
2730
2740
2750
2760
2770

1472
1480
1488
1496
1504
1512
1520
1528

1473

1474
1482
1490
1498
1506
1514
1522
1530

1475
1483

1489
1497
1505
1513
1521
1529

1477
1485
1493
1501
1509
1517
1525
1533

1478
1486
1494
1502
1510
1518
1526
1534

1479
1487
1495
1503

1157
1165
1173
1181
1169
1197
1205
1213

1158
1166
1174
1182
1190
1198
1206
1214

1159
1167
1175
1183

1218 1219
1226 1227
1234 1235
1241 1242 1243
1249 1250 1251
1257 1258 1259
1265 1266 1267
1273 1274 1275

1220
1228
1236
1244
1252
1260
1268
1276

1221
1229
1237
1245

1222
1230
1238
1246
1254
1262
1270
1278

1223
1231
1239
1247
1255
1263

1280
1288
1296
1304
1312
1320
1328
1336

1154 1155 1156
1162 1163 1164
1169 1170 1171 1172
1177 1178 1179 1180
1185 1186 1187 1188
1193 1194 1195 1196
1201 1202 1203 1204
1209 1210 1211 1212
1217
1225
1233

2400
2410
2420
2430
2440
2450
2460
2470

1028 1029
1036 1037
1044 1045
1052 1053
1060 1061
1068 1069
1076 1077
1084 1085

1161

H-4

1539 1540
1547 1548
1555 1556
1563 1564
1571 1572
1579 1580
1587 1588
1595 1596

1253
1261

1269
1277

1541

1191

1199
1207
1215

1271

1279

1542 1543
1550 1551
I55S 1559
1566 1567
1574 1575
1582 1583
1590 1591
1598 1599

3400 1792
3410 1800
3420 1808
3430 1816
3440 1824
3450 1832
3460 1840
3470 1848

1289
1297
1305
1313
1321
1329
1337

1481

1419
1427
1435
1443
1451
1459
1467

1476
1484
1492
1499 1500
1507 1508
1515 1516
1523 1524
1531 1532
1491

1798
1806
1814
1822
1830
1838
1846
1854

1799

3000

1807,

1815
1823

3777

2047

(Octal)

(Oacinel)

1858
1866
1874
1882
1890
1898
1906
1914

1859
1867
1875
1883
1891
1899
1907
1915

1860
1868
1876
1884
1892
1900
1908
1916

1922
1929 1930
1937 1938
1945 1946
1953 1954
1961 1962
1969 1970
1977 1978

1923

1601

1602 1603 1604
1610 1611 1612
1618 1619 1620
1626 1627 1628
1634 1635 1636
1642 1643 1644
1650 1651 1652
1658 1659 1660

1605 1606 1607
1613 1614 1615
1621 1622 1623
1629 1630 1631
1637 1638 1639
1645 1646 1647
1653 I6j4 1655
1661 1662 1663

3500
3510
3520
3530
3540
3550
3560
3570

1856 1857
1864 1865
1872 1873
1880 1881
1888 1889
1896 1897
1904 1905
1912 1913

3200
3210
3220
3230
3240
3250
3260
3270

1664
1672
1680
1688
1696
1704
1712
1720

1665
1673

1666 1667 1668
1674 1675 1676
1682 1683 1684
1690 1691 1692
1698 1699 1700
1706 1707 1708
1714 1715 1716
1722 1723 1724

1669
1677
1685
1693
1701
1709
1717
1725

1670 1671
1678 1679
1686 1687
1694 1695
1702 1703
1710 1711
1718 1719
1726 1727

3600
3610
3620
3630
3640
3650
3660
3670

1920
1928
1936
1944
1952
1960
1968
1976

1921

1924
1932
1940
1948
1956
1964
1972
1980

1925
1933

3300
3310
3320
3330
3340
3350
3360
3370

1728
1736
1744
1752
1760
1768
1776
1784

1729
1737
1745
1753

1735
1743

3700
3710
3720
3730
3740
3750
3760
3770

1984

1992
2000
2008
2016
2024
2032
2040

1985 1966 1987 1988
1993 1994 199S 1996
2001 2002 2003 2004
2009 2010 2011 2012
2017 2018 2019 2020
2025 2026 2027 2028
2033 2034 2035 2036
2041 2042 2043 2044

1989
1997
2005
2013
2021
2029
2037
2045

1721

1761

1769
1777
1785

1730
1738
1746
1754
1762
1770
1778
1786

1731
1739
1747

1755
1763
1771
1779
1787

1732 1733
1740 1741
1748 1749
1756 1757
1764 1765
1772 1773
1780 1781
1788 1789

1734
1742
1750
1758
1766
1774
1782
1790

1751
1759
1757
1775

1783
1791

1511
1519
1527
1535

1600
1608
1616
1624
1632
1640
1648
1656

1689
1697
1705
1713

Decimal

1797
1805
1813

3100
3110
3120
3130
3140
3150
3160
3170

1681

Octal

4096
10000
8192
20000
30000- 122B8
40000 16384
50000 20480
60000 24576
70000 28672

1538
1546
1554
1562
1570
1578
1586
1594

1649
1657

1533
(Dtcimol)

1796
1804
1812
1820
1828
1836
1844
1852

1537
1545
1553
1561
1569
1577
1585
1593

1641

2777
(Otiol)

1536
1544
1552
1560
1568
1576
1584
1592

1609
1617
1625
1633

1024

1795
1803
1811
1819
1827
1835
1843
1851

1793 1794
1801 1802
1809 1810
1817 1818
1825 1826
1833 1834
1841 1842
1849 1850

3000
3010
3020
3030
3040
3050
3060
3070

1549
1557
1565
1573
1581
1589
1597

2000

1931
1939
1947
19J5

1963
1971
1979

1821

1829
1837
1845
1853
1861

1869
1877
1885
1893
1901

1909
1917

1831
1639
1847
1855

1862 1863
1870 1871
1878 1879
1886 1887
1894 1895
1902 1903
1910 1911
1918 1919

1926
1934
1941 1942
1949 1950
1957 1958
1965 1966
1973 1974
1981 1982

1927
1935
1943
1951

1959
1967
1975
1983

1990 1991
1998 1999
2007
2015
2023
2031
2039
2047

2006
2014
2022
2030
2038
2046

1536
to

Octal-Decimal Integer Conversion Table (Cont)

4777

2559

(Ocioll

iDrcimat'

Octal

Decimal

10000- 4096
20000- 8192
30000- 12288

40003-16384
50000 • 20480
60000 - 24576
70000 • 28672

4000
4010
4020
4030
4040
40S0
4060
4070

2048
2056
2064
2072
2080
2088
2096
2104

2050
2058
2066
2074
2081 2082
2089 2090
2097 2098
2105 2106

2052 2053 2054
2059 2060 2061 2062
2067 2068 2069 2070
2075 2076 2077 2078
2083 2084 2065 2086
2091 2092 2093 2094
2099 2100 2101 2102
2107 2108 2109 2110

2055
2063

4100
4110
4120
4130
4140
4150
4160
4170

2112
2120
2128
2136
2144
2152
2160
2168

2113 2114
2121 2122
2129 2130
2137 2138
2145 2146
2153 2154
2161 2162
2169 2170

2115 2116 2117
2123 2124 2125
2131 2132 2133
2139 2140 2141
2147 2148 2149
2155 2156 2157
2163 2164 2165
2171 2172 2173

2119
2127
2135
2143

4200
4210
4220
4230
4240
4250
4260
4270

2176
2184
2192
2200
2208
2216
2224
2232

2177 2178 2179 2180
2185 2186 2187 2188
2193 2194 2195 2196
2201 2202 2203 2204
2209 2210 2211 2212
2217 2218 2219 2220
2225 2226 2227 2228
2233 2234 2235 2236

4300
4310
4320
4330
4340
4350
4360
4370

2240
2248
2256
2264
2272
2280
2288
2296

2241

2049
2057
2065
2073

2249
2257
2265
2273
2281
2289
2297

2051

2242
2250
2258
2266
2274
2282
2290
2298

2243 2244
2251 2252
2259 2260
2267 2268
2275 2276
2283 2284
2291 2292
2299 2300

2118
2126
2134
2142
2150
2158
2166
2174

2182
2190
2198
2206
2214
2221 2222
2229 2230
2237 2238

2071
2079
2087
2095

2103
2111

2151

2159
2167
2175

2181

2183

2189
2197
2205
2213

2191

4400
4410
4420
4430
4440
4450
4460
4470

2304
2312
2320
2328
2336
2344
2352
2360

4500 2368 2369 2370
4510 2376 2377 2378
4520 2384 2385 2386
4J30 2392 2393 2394
4540 2400 2401 2402
4550 2408 2409 2410
4560 2416 2417 2418
4570 2424 2425 2426

2239

4600
4610
4620
4630
4640
4650
4660
4670

2432
2440
2448
2456
2464
2472
2480
2468

2245 2246 2247
2253 2254 2255
2261 2262 2263
2269 2270 2271
2277 2278 2279
2285 2286 2287
2293 2294 2295
2301 2302 2303

4700
4710
4720
4730
4740
4750
4760
4770

2496
2504
2512
2520
2528

2199
2207
2215
2223
2231

2306
2314
2322
2330
2338
2345 2346
2353 2354
2361 2362
2305
2313
2321
2329
2337

2307 2308 2309 2310
2315 2316 2317 2318
2323 2324 2325 2326
2331 2332 2333 2334
2339 2340 2341 2342
2347 2348 2349 2350
2355 2356 2357 2358
2363 2364 2365 2366

2311
2319
2327
2335

2M3
23SI

2359
2367

2371 2372 2373 2374 2375
2379 2380 2381 2382 2383
2387 2388 2389 2390 2391
2395 2396 2397 2398 2399
2403 2404 2405 2406 2407
2411 2412 2413 2414 2415
2419 2420 2421 2422 2423
2427 2428 2429 2430 2431

2433 2434
2441 2442
2449 2450
2457 2458
2465 2466

2435 2436 2437
2443 2444 2445
2451 2452 2453
2459 2460 2461
2467 2468 2469
2473 2474 2475 2476 2477
2481 2482 2483 2^84 2485
2489 2490 2491 2492 2493

2497 2498 2499 2500
2505 2506 2507 2508
2513 2514 2515 2516
2521 2522 2523 2524
2529 2530 2531 753?
2536 2537 2538 2539 2540
2544 2545 2546 2547 2548
2552 2553 2554 2555 2556

2438
2446
2454
2462
2470
2478
2486
2494

2439
2447
2455
24^3

2502
2510
2518
2528
2534
2541 2542
2549 2550
2557 2558

2503
2511
2519
2527
2535
2543
2551
2559

7501

2509
2517
2525
2533

2471
2479
2487
2495

5000

2560

5777

3071

(Ociol)

(Dccimol)

2566
2574
i5^2
2590
2598
2606
2614
2622

2567
2575
2583
2591
2599
2607
2615
2623

5400
5410
5420
5430
5440
5450
5460
5470

2816
2824
2832
2840
2848
2856
2864
2872

2817 2818 2819 2820
2825 2826 2827 2828
2833 2834 2835 2836
2841 2842 2843 2844
2849 2850 2851 2852
2857 2858 2859 2860
2865 2866 2867 2868
2873 2874 2875 2876

2630
2638
2646
2654
2661 2662
2669 2670
2677 2678
2685 2686

2631
2639
2647
2655

5500
5510
5520
5530
5540
5550
5560
5570

2880
2888
2896
2904
2912
2920
2928
2936

2882
2890
2898
2906
2914
2921 2922
2929 2930
2937 2938

2944
2952
2960
2968
2976
2384
2992
3000

2945
2953
2961
2969
2977
2985
2993
3001

2946
2954
2962
2970
2978
2986
2994
3002

2947
2955
2963
2971
2979
2937
2995
3003

3008
3016
3024
3032
3040
3048
3056
3064

3009
3017
3025
3033
3041
3049
3057
3065

3010
3018
3026
3034
3042
3050
3058
3066

3011

5000
5010
5020
5030
5040
5050
5060
5070

2560
2568
2576
2584
2592
2600
2608
2616

2609
2617

2563 2564
2571 2572
2579 2580
2587 2568
2595 2596
2603 2604
2611 2612
2619 2620

2565
2573
2581
2589
2597
2605
2613
2621

5100
5110
5120
5130
5140
5150
5160
5170

2624
2632
2640
2648
2656
2664
2672
2680

2625 2626 2627 2G28
2633 2634 2635 2636
2641 2642 2643 2644
2649 2650 2651 2652
2657 2658 2659 2660
2665 2666 2667 2668
2673 2674 2675 2676
2681 2682 2683 2684

2629
2637
2645
2653

5200
5210
5220
5230
5240
5250
5260
5270

2688
2696
2704
2712
2720
2728
2736
2744

2689
2697
2705
2713
2721
2729
2737
2745

2690
2698
2706
2714
2722
2730
2738
2746

2691

5300
5310
5320
5330
5340
5350
5360
5370

2;. 2

2760
2768
2776
2784
2792
2800
2808

2753 2754
2761 2762
2769 2770
2777 2778
2785 2786
2793 2794
2801 2802
2809 2810

2755
2763
2771
2779
2787
2795
2803
2811

2561

2569
2577
2585
2593
2601

2562
2570
2578
2586
2594
2602
2610
2518

2692
2700
2708
2716
2724
2731 2732
2739 2740
2747 2748

2699
2707
2715
2723

2756
2764
2772
2780
2788
2796
2804
2812

2663
2671

2679
2687

2693 2694
2701 2702
2709 2710
2717 2718
2725 2726
2733 2734
2741 2742
2749 2750

2695
2703
2711
2719
2727
2735
2743
2751

5500
3610
5620
5630
5640
5650
5660
5670

2758
2766
2774
2782
2790
2798
2806
2814

2759
2767
2775
2783
2791
2799
2807
2815

S700
5710
5720
5730
5740
5750
5760
5770

2757
2765
2773
2781
2789
2797
2805
2813

2881

2889
2897
2905
2913

2871

2123

2829
2837
2845
2853
2861
2869
2877

2822
2830
2838
2846
2854
2B62
2870
2878

2883 2884
2892
2900
2908
2916
2924
2931 2932
2939 2940

2885
2893
2901
2909
2917
2925
2933
2941

2886
2894
2902
2910
2918
2926
2934
2942

2948
2956
2964
2972
2980
2938
2996
3004

2949
2957
2965
2973
2981
2989
2997
3005

2950
2958
2966
2974

3012
3020
3028
3036
3044
3051 3052
3059 3060
3067 3068

3013
3021
3029
3037
3045
3053
3061
3069

2891

2899
2907
2915
2923

3019
3027
3035
3043

2982
2990
2998
3006
3014

3022
3030
3038
3046
3054
3062
3070

2891

2831
2847
28SS
2863
2871
287tt

2887
2895
2903
2911
2919
2927
2935
2943

2951
2959
2967
2975
2983
2991
2999
3007
3015
3023
3031
3039
3047
3055
3063
3071

H-5

Octal -Decimal Integer Conversion Table (Cont)

6000
8010
6030
6030
6040
60S0
6060
6070

3072
3080
3088
3096
3104
3112
3120
3128

3073
3081
3089
3097
3105
3113

3074
3082
3090
3098
3106
3114
3122
3130

3121

3129

3136
3144
31S2
3160
3168
61 SO 3176
6160 3184
6170 3192

3138
3146
3153 3154
3161 3162
3169 3170
3177 3178
3185 3186
3193 3194

6200 3200
3208
3216
3224
3232
3240
6260 3248
6270 32S6

3201

6300
6310
6320
6330
6340
6350
6360
6370

3265
3273
3281
3289
3297
3305
3313

6100
6110
6120
6130
6140

«210
6220
6230
6240
62S0

H-6

3264
3272
3280
3288
3296
3304
3312
3320

3137

3H5

3330
3338
3346
3354
3362
3370
3378
3386

3331
3339
3347

3078
3086
3094
3102
3110
3118
3126
3134

3079
3087
3095
3103
3111
3119
3127
3135

6400
6410
6420
6430
6440
6450
6460
6470

3328
3336
3344
3352
3360
3368
3376
3384

3139 3140 3141 3142 bl43
3147 3148 3149 3150 3151
3155 3156 3157 3158 3159
3163 3164 3165 3166 3167
3171 3172 3173 3174 3175
3179 3180 3181 3182 3183
3187 3188 3189 3190 3191
3195 3196 3197 3198 3199

6500
6510
6520
6530
6540
6550
6560
6570

3392 3393 3394 3395
3400 3401 3402 3403
3408 3409 3410 3411
3416 3417 3418 3419
3424 3425 3426 3427
3432 3433 3434 3435
3440 3441 3442 3443
3448 3449 3450 3451

3075 3076 3077
3063 3084 3085
3091 3092 3093
3099 3100 3101
3107 3108 3109
3115 3116 3117
3123 3124 3125
3131 3132 3133

3329
3337
3345
3353
3361
3369
3377
3385

3396
3404
3412
3420
3428
3436
3444
3452

3397
3405
3413
3421
3429
3437
3445
3453

3460
3468
3476
3484
3492
3500
3508
3516

3461
3469
3477
3485

3524
3532
3540
3548
3556
3564
3571 3572
3579 3580

3205
3213
3221
3229
3237
3245
3253
3261

3206
3214
3222
3230
3238
3246
3254
3262

3207
3215
3223
3231
3239
3247
3255
3263

6600
6610
6620
6630
6640
6650
6660
6670

3456
3464
3472
3480
3488
3496
3504
3512

3457
3465
3473
3481
3489
3497
3505
3513

3458
3466
3474
3482
3490
3498
3506
3514

3459
3467
3475
3483
3491
3499
3507
3515

3267 3268 3269
3275 3276 3277
3283 3284 3285
3291 3292 3293
3299 3300 3301
3307 3308 3309
3315 3316 3317
3323 3324 3325

3270
3278
3286
3294
3302
3310
3318
3326

3271
3279
3287
3295

6700
6710
6720
6730
6740
6750
6760
6770

3520
3528
3516
3544
3552
3560
3568
3576

3521 3522
3529 3530
3537 3538
3545 3546
3553 3554
3561 3562
3569 3570
3577 3578

3523
3531
3539
3547
3555
3563

3321

3266
3274
3282
3290
3298
3306
3314
3322

3311
3319
3327

3651
3659
3667
3675
3683
3691

7200
7210
T230
7230
7340
7350
7360
7370

3712
3720
3738
3736
3744
3752
3760
3768

3713 3714
3721 3732
W39 3730
3737 3738
3745 3746
37S3 37S4
3761 3763
3769 3770

3715
3723
3731
3139
3747
3755
3763
3771

7)00
7310
T)30
7330
7340
7350
7360
7870

3776
3784
3792
3800
3801
3816
3834
3833

3799
3807
8815
3823
3831
3839

•7710

3479
3487
3495
3503
3511
3519

3073

6000
6777

3583

(Octal)

(Otcimol)

Decimal

Octal

4096
10000
8192
20000
30000 12288
40000 16384
50000 20480
60000 24576
70000 -28672

3463

3525
3533
3541
3549
3557
3565
3573
3581

3526
3534
3542
3550
3558
3566
3574
3582

3527
3535
3543
3551
3559
3567
3575
3583

3471

3910
3918
3926
3934
3942
3950
3958
3966

3911
3919
3927
3935
3943
3951
3959
3967

3969
3977
3985
3993
4001
4009
4017
4025

3970
3978
3986
3994
4002
4010
4018
4026

3972
3980
3988
3996
4004
4012
4020
4028

3973
3981
3989
3997
4005
4013
4021
4029

3974
3982
3990
3998

4030

3975
3983
3991
3999
4007
4015
4023
4031

4033
4041
4049
4057
4065
4073
4081
4089

4034
4042
4050
4058
4066
4074
4082
4090

4036
4044
4052
4060
4068
4076
4084
4091 4092

4037
4045
4053
4061
4069
4077
4085
4093

4038
4046
4054
4062
4070
4078
4086
4094

4039
4047
4055
4063
4071
4079
4087
4095

7700 4032
4040
7720 4048
7730 4056
7740 4064
7750 4072
7760 4080
7770 4088

3791

3462
3470
3478
3486
3493 3494
3501 3502
3509 3510
3517 3518

3909
3917
3925
3933
3941
3949
3957
3965

3968
3976
3984
3992
4000
4008
4016
4024

3783

3650
3658
3666
3674
3682
3690
3698
3706

3439
3447
3455

3908
3916
3924
3932
3940
3948
3956
3964

7600
7610
7620
7630
7640
7650
7660
7670

3782
3790
3798
3808
3814
3822
3B30
3838

3649
3657
3665
3673
3681
3689
3697
3705

3431

3905 3906 3907
3913 3914 3915
3921 3922 3923
3929 3930 3931
3937 3938 3939
3945 3946 3947
3953 3954 3955
3961 3962 3963

3711

3777 3778 3779 3780 3781
3785 3786 3787 3788 3789
3793 3794 3795 3796 3797
3801 3802 3803 3804 3805
3809 3810 3811 3812 3813
3817 3818 3819 3820 3821
9835 3826 3827 3828 3829
3833 3834 3835 3836 3837

3648
3656
3664
3672
3680
3688
3696
3704

3399
3407
3415
3423

3846
3854
3862
3870
3878
3886
3894
3902

3719
3727
3735
3743
3751
3759
3767
3775

3718
3726
3734
3742
3750
3758
3786
3774

7100
7110
7130
7130
7140
7150
7160
7170

3599
3607
3615
3623
3631
3639
3647

3398
3406
3414
3422
3430
3438
3446
3454

3845
3853
3861
3869
3877
3885
3893
3901

3904
3912
3920
3928
3936
3944
3952
3960

8717
3725
3733
3741
3749
3757
376S
3773

3716
3724
3732
3740
3748
37S6
3764
3773

3587
3595
3603
3611
3619
3627
3635
3643

3335
3343
3351
3359
3367
3375
3383
3391

3843 3844
3851 3852
3859 3860
3867 3868
3875 3876
3883 3884
3891 3892
3899 3900

7500
7510
7520
7530
7540
7550
7560
7570

3655
3663
3671
3679
3687
3695
3703

3653
3661
3669
3677
3685
3693

3586
3594
3602
3610
3618
3626
3634
3642

3847
3855
3863
3871
3879
3887
3895
3903

3841 3842
3^49 3850
3857 3858
3865 3866
3873 3874
3881 3882
3889 3890
3897 3898

3654
3662
3670
3678
3686
3694
3701 3702
3709 3710

3652
3660
3668
3678
3684
3602
3699 3700
3707 3708

3585
3593
3601
3609
3617
3625
3633
3641

3840
3848
3858
3864
3872
3880
3888
3896

3591

3589
3597
3605
3613
3621
3629
3637
3645

3584
3592
3600
3608
3616
3674
3632
3640

7400
7410
7420
7430
7440
7450
7460
7470

3590
3598
3606
3614
3622
3630
3638
3646

3588
3596
3604
3612
3620
3628
3636
3644

7000
7010
7020
7090
7040
70S0
7060
7070

•

3203 3204
3211 3212
3219 3220
3227 3228
3235 3236
3243 3244
3251 3252
3259 3260

3303

3332 3333 3334
3340 3341 3342
3348 3349 3350
3355 3356 3357 3358
3363 3364 3365 3366
3371 3372 3373 3374
3379 3380 3381 3382
3387 3388 3389 3390

3202
3210
3218
3226
3234
3242
3250
3258

3209
3117
3225
3238
3241
3249
3257

3971
3979
3987

3995
4003
4011
4019
4027

4035
4043
4051
4059
4067
4075
4083

4006
4014
1022

7000

3584

7777

409S

(Ociol)

(Decimal)

Octal -Decimal Fraction Conversion Table
DEC.

OCTAL

DLC.

OCTAL

oooooo
.001953

.005859
.007812
.009765
.011718
.013671

.100
.101
.102
.103
.104
.105
,106
.107

.125000
126953
128906
. 130859
132812
. 134765
.136718
.138671

.200
.201
.202
.203
.204
.205
.206
.207

.110
.111
.112
.113
.114
.115
.116
.117

140625
.142578

.210

144531

.212

146484
148437
. 150390
. 152343

.213
.214

.017

.015625
.017578
.019531
.021484
.023437
.025390
027343
. 029296

154296

.217

.020
.021
.022
.023
.024
.025
.02^
.027

.031250
. 033203
.035156
.037109
039062
.041015
042968
.044921

.120

156250
. 158203

.220

.122
,123
.124
.125
.126
.127

.160156
.162109
164062
.166015
. 167968

.222
.223
.224
.225
.226
.227

.030
.031

.130

.171875
.173828
.175781
. 177734
. 179687
. 181640
. 183593
185546

,230
.231

.037

046873
.048828
.050781
052734
054687
056640
058593
060546

.040

.140
.141

187500
189453
191406

,240

.041

062500
064453
066406
068359
.070312
072265
,074218
,076171

193359
.195312
. 197265
.199218
.201171

.243
.244

.150
.151

,203125
.205078
207031
.208984
.210937
.212890
.214843
.216796

.250
.251

.056
.057

.078125
. 080078
.082031
.083984
,085937
. 087890
089843
,091796

.060

,160

.161

.218750
.220703
222656
.224609
226562
.228515
.230468
.232421

.260

.061

.234375
.236328
.238281
.240234
.242187
.244140
.246093
. 248046

OCTAL
.000
.001

.002
.003
.004
.005
.006
.007
.010
.011
.012
.013
.014
.015
.016

.032
.033
.034
.035
.036

.042
.043
.044
.045
.046
.047
.050
.051
.052
.053
.054
.055

(J03906

.066
.067

093750
095703
097656
099609
.101562
.103515
105468
.107421

.070
.071
.072
.073
.074
.075
.076
.077

109375
.111328
.113281
.115234
.117187
.119140
121093
. 123046

.062
.063
.064
.0fr5

.121

.131

.132
.133
,134
.135
.136
.137

.142
.143
,144
.145
,146
.147

.152
,153
.154
,155
,156
.157

,162
.163
.164

.165
.166
.167
.

170

.171

.172
.173
.174
.

175

.176
.177

169921

DtC.

OCTAL

UKC.

250000

.300

.251953
. 253900
. 255859
.257812

.301

.375000
.370953

.302
.303
.304
.305
.306
.307

.37890f>

265625
.267578
.269531
.271484
.273437
. 275390
.277343
.279296

.310
.311
.312
.313
.314
.315

.390625
.302578
.394531
.396484
.398437
.400390
.402343

.317

.404296

.281250
283203
.285156
.287109
289062
.291015
292968
.294921

.320
.321

.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921

296875
,298328
.300781
302734
.304687
,306640
,308593
,310546

.330
.331

.312500
.314453
.316406
.318359
.320312
. 322265
.324218
,326171

.340

.328125
330078
.332031
333984
.335937
337890
339843
.341796

.350
.351

.265
.266
.267

.343750
345703
. 347656
349609
.351562
.353515
.355468
.357421

.360
.361
.362
.363
.364
.365
.366
.367

.270
.271
.272
.273
.274
.275
.276
.277

.359375
.361328
.3G32S1
.365234
.367187
.369140
.371093
373046

.370
.371

.211

.215
.216

.221

.232

.233
.234
.235
.236
.237
.241

.242

.245

.246
.247

.252
,253
.254

.255
.256
.257

.259765
.261718
.263671
.

.261

.262
.263

.264

.316

.322
.323
.324
.325
.326
,327

.332
.333
.334
.335
.336
.337
.341

.342
.343
.344

.345

.346
.347

.352
,353
.354

.355
.356
.357

.372
,373
.374
,375

.376
.377

.380859
.382812
.384765
.386718
.388671

.421875
.423828
.425781
.427734
.429687
.431640
.433593
.435546
.437500
.439453
.441406
.443359
.445312
.447265
.449218
,451171

.453125
. 455078
.457031
. 458984
460937
462890
,464843
,466796
,

468750
470703
.472656
.474609
476562
.478515
.460468
.482421
,

.484375
.486328
.4882^1
.490234
.492187
.494140
.496093
.498048

H-7

Octal -Dec! ma

Fraction Conversion Table (Cont)
OCTAL

DEC.

000300
.000301
.000302

.000732
.000736
. 000740

000499
000503
. 000507
.000511
. 000514

.000303
.000304
.000305
. 000306
.000307

.000743
. 000747
.000751
. 000755
. 000759

.000297
.000301

.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217

.000518
.000522
. 000526
. 000530
.000534
. 000537
. 000541
. 000545

.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317

.000762
.000766
,000770
.000774
. 000778
.000782
.000785
.000789

.000120
.000121
.000122
.000123
.000124
.000125
.000126
.000127

.000305
.000308
.000312
.000316
.000320
.000324
.000328
.000331

.000220
.000221
.000222
.000223
.000224
.000225
.000226
.000227

.000549
.000553
.000556
.000560
.000564
000568
. 000572
. 000576

000320
.000321
. 000322
. 000323
.000324
. 000325
000326
. 000327

.000793
.000797
.000801
. 000805
. 000808
.000812
.000816
.000820

.000036
.000037

.000091
.000095
.000099
.000102
.000106
.000110
.000114
.000118

.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137

.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362

.000230
.000231
.000232
.000233
.000234
.000235
.000236
.000237

.000579
.000583
. 000517
.000591
. 000595
.000598
.000602
.000606

.000330
.000331
. 000332
.000333
.000334
.000335
.000336
.000337

.000823
.000827
.000831
. 000835
.000839
.000843
.000846
.000850

.000040
.000041
.000042
.000043
. 000044
.000045
.000046
.000047

.000122
.000125
.000129
.000133
.000137
.000141
.000144
.000148

.000140
.000141
.000142
.000143
.000144
.000145
.000146
.000147

.000366
.000370
.000373
.000377
.000381
.000385
.000389
.000392

.000240
.000241
.000242
.000243
.000244
.000245
.000346
.000247

000610
000614
. 000617
.000621
. 000625
. 000629
.000633
.000637

.000340
.000341
.000342
.000343
.000344
.000345
.00034b
.000347

.000854
.000858
. 000862
.000865
.000869
. 000873
.000877
.000881

OOOOSO
.000051
.000052
.000053
.000054
.000055
.000056
.000057

.000152
.000156
.000160
.000164
.000167
.000171
.000175
.000179

.000150
.000151
.000152
.000153
.000154
.000155
.000156
.000157

.000396
.000400
.000404
.000408
.000411
.000415
.000419
.000423

.0002M
.000251
.000252
.000253
.000254
.000255
.000256
.000357

.000640
.000644
.000648
.000652
.000656
.000659
.000663
.000667

.000350
.000351
.000352
.000353
.000354
.000355
.000356
.0003..

.000885
.000888
.000892
. 000896
.000900
.000904
. 000907
.000911

.000060
.000061
.000062
.000063
. 000064
.000065
.000066
.000067

.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209

.000160
.000161
.000162
.000163
.000164
.000165
. 000166
.000167

.000427
.000431
.000434
.000438
.000442
.000446
.000450
.000453

.000260
.000261
.000262
.000263
.000264
.000265
.000266
.000267

,000671
.000675
. 000679
.000682
. 000686
. 000690
. 000694
.000698

.000360
.000361
.000362
.000363
.000364
000365
.000366
.000367

.000915
.000919
.000923
.000926
. 000930
. 000934
. 000938
. 000942

.000070
.000071
.000072
.000073
.000074
.000075
.000076
.000077

.000213
.000217
.000221
.000225
.000228
.000232
.000236
.000240

.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177

.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484

.000270
.000271
.000272
.000273
.000274
.000275
.000276
.000277

.000701
. 000705
.000709
.000713
.000717
.000720
.000724
.000728

.000370
.000371
.000372
.000373
.000374
.000375
.000376
.000377

.000946
. 000949
.000953
.000957
.000961
. 000965
.000968
.000972

DEC.

OCTAL

DEC.

OCTAL

.000003
.000004
. OOOOOS
.000006
.000007

OOOOOO
000003
.000007
.000011
.000015
.000019
.000022
.000026

.000100
.000101
.000102
.000103
000104
. 000105
.000106
.000107

.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270

.000200
.000201
.000202
.000203
.000204
.000205
.000206
.000207

.000010
. 000011
.000012
.000013
.000014
.0000 IS
.000016
.000017

.000030
.000034
.000038
.000041
000045
.000049
.000053
.000057

,000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117

.000274
.000278
.000282
.000286
.000289

.000020
.000021
.000022
.000023
000024
.000025
.000026
.000027

.000061
.000064
.000068
.000072
.000076
.000080
.000083
.000087

000030
.000031
.000032
.000033
.000034

OCTAL
.000000
.000001
.000002

.0iK>035

H-8

.0002U

DEC.
000488
000492
. 000495
.

.
.

Ocfal-Decimal FracMon Conversion Table (Cont)
OCTAL

DEC.

OCTAL

DEC.

. 000400
.000401
. 000402
. 000403
.000404

00040S
.000406
. 00040T

.000976
000980
.000984
.000988
.000991
.000995
.000999
.001003

.000500
.000501
. 000502
000503
.000504
.000505
. 000506
.000507

.001220
.001224
.001228
.001232
.001235
.001239
.001243
.001247

000410
.000411
.000412
.000413
. 000414
.000415
. 000416
.000417

.001007
.001010
.001014
.001018
.001022
.001026
.001029
.001033

.000510
.000511
.000512
.000513
.000514
.000515
.000516
.000517

.001251
.001255
.001258
.001262
.001266
.001270
.001274
.001277

000420
.000421
. 000422
.000423
.000424
.000425
. 000426
.000427

.001037
.001041
.001045
.001049
.001052
.001056
.001060
.001064

000520
.000521
. 000522
.000523
. 000524
.000525
.000526
.000527

.001281
.001285
.001289
.001293
.001296
.001300
.001304
.001308

.000430
. 000431
.000432
.000433
.000434
.000435
.000436
.000437

.001068
.001071
,001075
.001079
.001083
.001067
.001091
.001094

.000530
.000531
. 000532
.000533
.000534
. 000535
.000536
.000537

.001312
.001316
.001319
.001323
.001327
.001331
. 001335
. 001338

.000440
.000441
.000442
.000443
.000444
.000446
.000446
.000447

.001098
.001102
.001106
.001110
.001113
.001117
.001121
.001125

.000540
.000541
.000542
.000543
.000544

.000545
.000546
.000547

.001342
. 001346
.001350
. 001354
.001358
.001361
.001365
.001369

.000450
.000451
.000452
.000453
.000454
.000455
.000456
.000457

.001129
.001132
.001136
.001140
.001144
.001148
.001152
.001155

.000550
.000551
.000552
.000553
.000554
.000555
.000556
.000557

.001373
.001377
.001380
.001384
.001388
.001392
001396
.001399

.000460
.000461
.000462
.000463
.000464
.000465
.000466
000467

000560
.000561
. 000562
.000563
.000564
.000565
.000566

.001159
.001163
.001167
.001171
.001174
.001178
.001182
.001186

.000470
.000471
.000472
.000473
.000474
.000475
.000476
.000477

.001190
.001194
.001197
.0012
.001205
001209
.001213
.001216

OCTAL

DEC,

000700
.000701
. 000702
. 000703
. 000704
.000705
. 000706
,000707

.001708
.001712

.001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522

.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717

.001739
.001743
.001747
.001750
.001754
.001758
.001762
.001766

000620
.000621
.000622
. 000623
. 000624
. 000625
. 000626
.000627

.001525
.001529
.001533
.001537
.001541
.001544
.001548
.001552

. 000720
.000721
. 000722
000723
. 000724
.000725
.000726
.000727

.001770
.001773
.001777
.001781
.001785
.001789
.001792
.001796

000630
.000631
. 000632
,000633
. 000634
, 000635
. 000636
.000637

.001556
.001560
.001564
.001567
.001571
.001575
.001579
.001583

.000730
.000731
. 000732
. 000733
.000734
.000735
.000736
. 000737

.001800
.001804
.001808
.001811

000640
.000641
.000642
. 000643
. 000644
.000645
.000646
.000647

.001586
.001590
,001594
.001598
.001602
.001605
.001609
.001613

000740
.000741
. 000742
. 000743
. 000744
. 000745
. 000746
. 000747

.001831
.001834
,001838
,001842

000650
.000651
000652
.000653
. 000654
. 000655
.000656
.000657

.001617
.001621
.001625
.001628
.001632
.001636
.001640
.001644

000750
.000751
.000752
. 000753
.000754
. 000755
. 000756
, 000757

.001861
.001865
.001869
.001873
.001876
.001880
.001884
.001888

000660
.000661
.000662
.000663
000664
.000665
.000666
000667

.001647

.000567

.001403
.001407
.001411
.001415
.001419
.001422
.001426
.001430

.001651
.001655
.001659
.001663
,001667
.001670
.001674

000760
,000761
,000762
, 000763
, 000764
, 000785
. 000766
. 000767

.001892
.001895
.001899
,001903
.001907
.001911
.001914
.001918

000570
.000571
.000572
.000573
. 000574
. 000575
. 000576
. 000577

.001434
.001438
.001441
.001445
.001449
.001453
.001457
.001461

.000670
.000671
.000672
000673
000674
.000675
.000676
.000677

.001678
.001682
.001686
.001689
.001693
.001697
.001701
.001705

000770
.000771
.000772
.000773
. 000774
. 000775
.000776
.000777

.001922
.001926
.001930
.001934
.001937
.001941
.001945
. 001949

OCTAL

DEC.

000600
.000601
. 000602
. 000603
. 000604
000605
. 000606
. 000607

.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491

.000610
.000611
.000612
.000613
.000614
.000615
.000616
.000617

.001716
.001720
.001724

.001728
.001731
.001735

.001815
.001819
.001823
.001827

.001846
.001850
,001853
.001857

H-9

Index

B
AAOl-A Digital-To- Analog
Accumulator (AC), Description

6-82
1-3

BA 1 2 Peripheral Expander

1 -6

j3-Class Format

3-6

Accumulator, I/O Transfers

5-9

j3-Class Instruction Format

3-4

A-D Converter Controls
A-D Converter Instructions

6-78

j3-Register

6-78

jS-Register Indexing

3-5

AD 12 Analog-Digital Converter and Multiplexer

3-35

Block, (LINCtape)

3-39

3-6

Block Number (BM)

3-39

Break Field Register, Extended Memory

4-19

Addressing: a-Class
Addressing, Combination of

Extended Memory Programming

4-21

Addressing Methods, 8 Mode

4-2

Addressing Methods, Memory

3-3

Addressing: a-Class

3-6

Cable Connections, Front Panel

G-1

^-Register

3-4

Cable Connections to I/O Bus

5-45

j3-Register Indexing

3-5

Cable Selection

5-40

Direct Addressing, LINC mode

3-3

Card Readers

Indirect Addressing: j3-Class

3-3

AFOl-A A-D Converter Specifications
AFOl-A Analog-To-Digital Converter
AFOl-A Sample and Hold Options

6-63

Card Reader and Control CR12

6-63

6-76

CM 1 2 Optical Mark Card Reader
CM 12 Optical Mark Card Reader Instructions

6-66

6-76

6-66

6-81

Controls and Indicators CMl 2

6-67

a-Class, Addressing

3-6

Control or Indicator, CRl

6-65

a-Class and Non-Memory Reference Format

3-6

Instructions,

CM 12 Optical Mark

Card Reader

6-66

a-Class and Others

3-6

a-Class Operations

3-14

Instructions, CRl 2 Card Reader

6-63

Analog-To-Digital Converter AFOl-A

6-76

Optical Mark Card Reader

CM 1

6-66

Card Reader and Control CRl
Central Processor, Logic Description

6-63

Analog Inputs
Analog Inputs, Equipment
Analog Knobs and Power Switch Panel

1-5,3-35
1-1

2-8

Accumulator (AC), Description

1-1

1-3

6-76

Instruction Field Register (IF), 5-Bits

1-4

A-D Converter Controls

6-78

Instruction Register (IR), 12 Bits

1-3

Analog-To-Digital Converter AFOl-A

6-76

Link (L) 1 Bit

1-3

Instructions, A-D Converter

6-78

1-3

Sample and Hold Options, AFOl-A

6-81

Specifications, AFOl-A A-D Converter

6-76

Memory Address Register (MA) 12 Bits
Memory Buffer (MB), 1 2 Bits
Mode Status Register 1 Bit

Analog- t'o-Digital

1-3

ASR-33 Character Set Display Pattern

3-34

Program Counter (PC) 12 Bits

1-3

Autoindexing, Extended Memory Programming

4-21

Central Processor, Major State Indicators

2-3

Autoindexing, 8 Mode

4-4

Central Processor, Miscellaneous Indicators

2-4

Auxiliary Scope Connector

1-5

Central Processor, Register Indicators

2-3

I-l

Character Displays

3-32

Character Set

3-33

Character Size

Data Break Transfers

5-2,5-21

Data Break Input Interface Logic

5-24

1-5,3-29

Data Break Output Interface Logic

5-26

Checksum (CM)
Check Words (CW)
Classic LINC
CM 12 Optical Mark Card Reader

3-39

Data Break Output Transfer Timing

5-25

3-39

Data Break Single Cycle Timing

5-23

1-4

Data Break Transfer Interface

5-21

6-66

Increment CA Inhibit, Three Cycle Data Break

5-30

Controls and Indicators CM 12

6-67

Input Data Transfers, Data Break

5-22

Codes, Table of

F-1

4-9

Memory Increment, Data Break
Memory Increment, Data Break Timing

5-27

Combining Group 1 Operations

Combined Operations: Group 1
Combined Skips In Group II

4-8

Output Data Transfers, Data Break

5-23

4-11

Three Cycle Data Break

5-29

Command Register, Contents, Magnetic Tape

6-51

Three Cycle Data Break Timing

5-29

Word Count Overflow, Three Cycle Data Break

5-30

5-28

Configuration of, PDP-1

1-1

Connections, Front Panel Cable

G-1

Data Break Transfer Interface

5-21

Connections, Interface

5-44

Data Break, Types of

5-21

Connections, I/O Bus Cable

5-45

Data Buffer DB12-P,N

Connector Selection

5-41

Data Field

Console Controls and Indicators

2-1

Data Field in Memory

Console Key Functions

2-6

Data Field Register, Extended Memory

Console Switches

3-22

3-1

1-4

4-19

Data Field Reserved Locations

3-2

Console Toggle Switches

3-7

Data, Mathematical Table

H-1

Console Teletype Control

6-5

Data Path

Controls and Indicators

2-1

Data Terminal

Control Registers

3-40

Analog Extension Panel

Continued Operations, Magnetic Tape

6-49

ATR AC to Relays

5-39

Clock Input Panel

Construction of Interfaces

Converting ASCII Code to PDP-1 2 Teletype
Conventions, Logic

6-3,F-3
5-3

CRT Display Character Size
CRT Display Equipment
CRT Display, Remote
CRT Display, VRl 2

1-45
1-1

3-31
2-1,3-31

Fast Sample

Power Switch Panel
Relay and Analog Input Panel

3-39
1-5,3-35
2-1

3-37
2-1

3-36
2-1

2-7

Relay Terminals and Corresponding AC Bits

3-36

RTA Relays to AC
SAM Sample

3-37
3-36

ASR-33 Character, See Display Pattern

3-34

Data Transfers, see Programmed Data Transfers

Character Displays

3-32

Data Transfers, Input

5-10

Character Set

3-33

Data Transfers, Output

5-11

DIS Display (a-Class)

3-32

Data Transfer Timing

5-6

DSC Display Character (/3-Class)
DSC Display Pattern for

3-32

Data Words (DM, FM)

3-39

3-33

DB12-P, N Data Buffer

6-73

Half-Size Characters

3-33

6-15

6-62

DC02-D Instructions
DC02-E Control Instructions
DC02-E Multiple Teletype Control
DC02-F Multiple Teletype Control
DC02-F Instructions
Decoding, Instruction lOT

5-29

Device Selector

Point Displays

3-32

CR12 Card Reader and Control
CR12 Card Reader, Control or Indicator
CR12 Card Reader Instructions
Counter Register, KW12-A
Current Address, Three Cycle Data Break

6-63

6-65
6-63

5-2

6-14
6-13

6-16
6-17
5-4
5-7

DF/DS32, -D Random Access Disk File,

D
Dataphone Control, Type DP12-B

6-9

Dataphone Interface DP12-B

1-6

Instructions

6-27

Digital-To-Analog

6-82

Digital -To- Analog AAOl-A

Digital-To-Analog AAOI-A

6-82

Data Break, Input Data Transfers

5-22

Direct Address

3-6

Input Interface Logic

5-24

Direct Addressing

4-2

Memory Increment

5-27

Direct Address Format of

Output Data Transfers

5-23

DIS Display (a-Class)

3-32

Output Interface Logic

5-26

Disable Teletype Interrupt

3-29

Output Transfer Timing

5-25

Disk Cartridge Memory, RK8/RK0I

6-38

Request for

5-22

Disk Memory System, RF/RS08

6-30

Single Cycle

5-21

Disk, RK8-P, RK8-N, RKOl, RKOl-K

6-43

5-23

Disk Storage

6-27

Single Cycle Timing

Three Cycle
Three Cycle Timing

1-2

5-21,5-29

5-29

bF/DS32, -D Instructions
Disk Cartridge Memory, RK8/RK01

3-3

6-27
6-38

Disk Memory System, RF/RS08

6-30
6-35

RIB Read Interrupt Buffer
RIF Read Instruction Field

4-20

Instructions, RF32 to RF/RS08 Comparison
Instructions, RK08/RK01

6-38

RMF Restore Memory Field

4-20

Programming, Disk Software

6-44

Program Interrupt, Extended Memory

4-22

Programming, RK08/RK01 I/O Subroutine

6-42

Programming, Extended Memory

4-21

4-19

Save Field Register, Extended Memory

4-19

Random Access Disk File,
DF/DS32 and DF/DS32-D
RF/RS08 Instructions
RF/RS08 Programming, Example
Specifications, RF/RS08
Specifications, RK9/RK01

6-27
6-30
6-34

Extended Memory, 8 Mode see also

LINC mode control

3-22

6-37

Extended Operations

3-45

6-43

Extended Operations Buffer
Extended Operations, LINCtape

3-41

1-5

Display

4-20

3-40

Display Scope Controls

2-11

Extended Tape Addressing

1-4

Division

4-18

Hold-motion

1-4

No-Pause

1-4

4-17

Program Interrupt

1-4

5-20

Tape Interrupt

1-4

3-32

with Core

1-4

3-33

Extended Units

3-47

External Level Lines

3-20

External Skips

3-20

Division of 24-bit numbers

EAE Programming
DM12
DSC Display Character (|3-Class)
DSC Display Pattern for,
DW08A I/O and Bus Converter

1-6

E
EAE Instruction Format
EAE Instructions
ASR Arithmetic Shift Right

4-13

4-16

Fast Sample

ASR, Shift Path for

4-16

Field Address, Use of

CLA Clear AC

4-14

First Word

3-42

DVI Divide

4-15

Fixed Interval Clocks

6-25

LSR Logical Shift Right

4-16

LSR, Shift Path for

4-16

Format Routines
Frequency Range, KW12-B,C

6-26

MQA Place MQ in AC
MQL Load MQ from AC
MUL Multiply

4-14

Front Panel Cable Connections

G-1

4-14

Full-Word Arithmetic

3-8

4-15

Full-Word Comparison

3-12

NMI Normalize
NMI,SHL Shift Path for,
SCA Step Counter to AC
SCL Load Step Counter
SHL Shift Left
Effective Address, 8 Mode

4-15

Full-Word Data Transfers

4-15

Full-Word Instructions

4-14

Full-Word Logic

4-14

Functional Description, Magnetic

4-13

4-15

3-29
3-2

6-7

3-7

3-7
3-11

6-45

Tape Control

4-4

Effective Addressing

3-3

8 Mode Instructions

B-1

8 Mode Perforated Tape Loader

D-1

General Description, System PDP-12

1-1

End-around carry

3-8

Group I, Operate Class Instruction Format
Group 11, Combined Skips
Group 11, Operate Class
Guard Word (GM)

4-7

Extended Address Format
Extended Arithmetic Element,

Programming for

3-46

4-16

Extended Arithmetic Element (EAE), KE12
Extended Arithmetic Element, KE12

1-6,4-13

Extended Memory

4-2,4-19

4-13

3-33
3-13,3-14

4-21

Half-Word Addressing, defined

Autoindexing, Extended Memory Programming

4-21

Hold-Motion, Extended Tape Addressing

Break Field Register, Extended Memory

4-19

Hold Unit Motion

Data Field Register, Extended Memory

4-19

Memory Progran-'jning

Extended Memory, Calling A Subroutine
Across Fields

4-9

3-39

H
Half-Size Characters

Addressing Combination of Extended

4-11

1-4

3-48

4-21
3-4

Instruction Field Buffer, Extended Memory

4-19

1-Bit

Instruction Field Register, Extended Memory

4-19

1-Bit, Octal Value

3-7

Instructions, Extended Memory

4-19

1-Bit, 8 Mode Addressing

4-4

4-20

Increment CA Inhibit, Three Cycle

CDF Change Data Field
CIF Change Instruction Field

4-20

RDF Read Data Field

4-20

Data Break
Incremental Plotter XYl 2

5-30
1-6

1-3

Type XY 12

6-68

Indexing, jS-Register

3-5

& Controls

5-30

interface Modules

Incremental Plotter and Control

Interrupt, LINC mode.

3-27

data path during

2-3

Interrupt, LINC Mode Service Routine

3-29

Analog Knobs and Power Switch Panel

2-8

Interrupt OFF, lOF

4-13

Central Processor Major State Indicators

2-3

Interrupt ON, ION

Central Processor Miscellaneous Indicators

2-4

Interrupts, LINC Mode

Central Processor Register Indicators

2-3

Instruction Decoding, lOT

5-4

Console Key Functions

2-6

Instruction Descriptions, see Instructions

3-7

Display Scope Controls

2-11

Indicators

Individual Console Toggle Switches

Tape Processor Major State Indicators
Teletype Model 33ASR Controls

Toggle Switch Registers

TU55 Tape Transport Controls and Indicators
Indirect Address, j3-Class
Indirect Addressing

3-7

2-4

2-14
2-6

2-12
3-6
3-3,4-3

4-12

Instruction Field

Instruction Field Buffer (IB)
Instruction Field and Data Field Registers

3-2
1-4

Instruction Field Register,

Extended Memory
Instruction Field Reserved Locations
Instruction Format

5-10

Instruction Format, Group II Operate Class

Input Data Transfers, Data Break

5-16

Instruction Formats, Direct Address,

3-22,5-1

Indirect Address j3-Class, a-Class and others

Instruction Register (IR), 12 Bits

Input/Output Facilities and Display,

LINC mode, I/O Bus

1-5

3-1

3-24

Instruction Field Register (IF), 5-Bits

Input Data Transfers

Input/Output Bus Description

3-26

Instruction Set, 8 Mode

Analog Inputs

1-5

AND Logical And to AC

Auxiliary Scope Connector

1-5

CIA Complement and Increment AC

Dataphone Interface DP12-B

1-6

Data Terminal

1-5

Display

1-5

Extended Arithmetic Element (EAE) KEI2

1-6

CLA Clear Accumulator
CLL Clear Link

Incremental Plotter XY12

1-6

Input/Output I/O Bus

1-6

CMA Complement Accumulator
CML Complement Link
DCA Deposit and Clear Accumulator
GLK Set Link

Keyboard/Printer

1-6

HLT Halt

4-19
3-2
3-7,3-41

4-10
3-6
1-3

3-l,4-5,B-l

4-6
4-9

4-10
4-7
4-7
4-8
4-5

4-9

4-11

LINCtape

1-5

lAC Increment Accumulator

4-8

Programmable Real-Time Interface KW12A

1-6

ISZ Increment and Skip if Zero

4-6

Relay Buffer

1-5

4-6

Sense Lines

1-5

TTY Interface, DPI 2-A

1-6

JMP Jump
JMS Jump to Subroutine
LAS Load Accumulator from Switches
LINC Switch to LINC mode
NOP No Operation

Input/Output Skip
Input/Output Transfer Class

5-8

4-12

4-6

4-10
4-12
4-7

Interface Connections

5-44

OSR OR Switch Register with AC
RAL Rotate Accumulator Left

Interface Construction

5-39

RAR Rotate Accumulator Right

4-8

Interface Design and Construction

5-30

4-8

Interaction between Modes Switching

4-11
4-8

Cable Connections to I/O Bus

5-45

RTL Rotate Two Places Left
RTR Rotate Two Places Right

Cable Selection

5-40

SKP Skip Unconditionally

4-10

Connector Selection

5-41

5-39

Interface Coimections

5-44

Interface Modules

5-30

lOT Allocations, Octal
Module Cooling
Module Layout
Module Selection for Interface Circuit of
Peripheral Equipment

5-43

SMA Skip on Minus AC
SNA Skip on Non-Zero AC
SNL Skip on Non-Zero Link
SPA Skip on Plus AC
STA Set Accumulator

4-10

Construction of Interfaces

5^0

STL Set Link
SZA Skip on Zero AC
SZL Skip on Zero Link

5-32

TAD Two's Complement Add to AC

M-Series Flip Chip Modules

5-34

Instruction Trap

M-Series Module Summary

5-35

Instructions,

Ml 01 Bus Data Interface
Ml 03 Device Selector
Ml 11/M906 Positive Input Circuit
M516 Positive Bus Receiver Input Circuit
M623/M906 Positive Output Circuit
M660 Bus Driver Output Circuit

5-33

A-D Converter

6-78

5-33

CM 12 Optical Mark Card Reader

6-66

5-30

CR12 Card Reader

6-63

5-31

Console Teletype Control

5-31

5-32

DC02-D
DC02-E

5-32

Descriptions

Wiring Hints

1-4

1-5

5-43

4-8

4-10
4-10
4-11

4-9
4-9

4-10
4-10
4-5

3-29,3-30,3-49

6-5

6-15

6-14
3-7

3-2,A-l

DF/DS32, -D

6-27

LINC Mode Instructions

EAE

4-13

Character Size

3-29

Extended Memory

4-19

Console Switches

3-22

Format Explanation of

3-7

Disable Teletype Interrupt

3-29

I/O Bus

C-1

Fast Sample

3-29

lOT

Full-Word Arithmetic

3-8

Full-Word Comparison

3-12

LINC
KP12
KW12-A
KW12-B,C

i-l,3-6,A-l

6-74

Full-Word Data Transfers

3-7

6-22

Full-Word Instructions

3-7

6-26

LP08 Line Printer
LP12 Line Printer

6-60

Magnetic Tape Control

6-45

6-59

ADA Add to Accumulator (j3-Class)
ADD Add to Accumulator
ADM Add to Memory (j3-Class)

3-9

3-19

3-8
3-9

PR 12 Reader

6-72

APO Accumulator Positive
AZE Accumulator Zero
BCL Bit Clear (jS-Class)
BCO Bit Complement (/3-Class)

PT08

6-11

BSE Bit Set (i3-Class)

341

RF32 to RF/RS08 Comparison
RF/RS08
RK08/RK01

6-35

CLR Clear

3-21

6-30

COM Complement AC

3-21

6-38

DJR Disable JUMP Return

3-28

Tape Maintenance

E-1

ESF Enable Special Functions

3-30

Two-word

1-4

FLO Overflow
HLT Halt

3-20

IBZ LINCtape Inter-Block Zone
lOBIOF Interrupt Off

3-20

lOB-ION Interrupt On
lOB-RIB Read Interrupt Buffer
lOB-RDF Read Data Field
lOB-RIF Read Instruction Field

3-26

3-27

5-5

lOB-RMF Restore Memory Fields
JMP Jump
KST Key Stuck
LAM Link Add to Memory (jS-Qass)

5-6

LDA Load Accumulator (jS-Qass)

PC12,PP 12 Paper Tape
6-71

Readers and Punch

XY 12 Plotter

6-68

lOB I/O Bus Enable
lOB/IOT

3-23
3-25
1-4

I/O Bus Access
I/O Bus Cable Connections

5-45

I/O Bus External Level Lines

3-20

I/O Bus Instructions

C-1

I/O Control

5-4

I/O Handler, LINC-8 Simulator

Trap Processor

lOP Generation
lOP Generation and Timing

3-19

341

342

3-21

3-26

3-27
3-26
3-25

345
3-21

3-9
3-8

3-29

LDF Load LINC Data Field Register

3-25

I/O Program Interrupt

5-11

LDH Load Half

3-14

lOS, Multiple Inputs

5-13

LIF Load UNC Instruction Field Buffer
LINC Switch to the LINC Mode (see PDP]

3-24

5-13

LSW Left Switches

3-22

543

LZE Link Zero

3-19

5-7

MUL Multiply (J3-Class)

3-10

14
14

NOP No Operation

3-21

PDP Switch to the 8 Mode

3-22

QAC Place MQ in AC

3-21

QLZ MQ Low-Order Bit Zero

3-19

3-16

5-15

ROL Rotate Left
ROR Rotate Right
RSW Right Switches

6-74

SAE Skip if Accumulator Equal to

I/O Preset Pulse

lOS and Program Interrupts,

Multiple Inputs

lOT Allocations, Octal
lOT Command Pulse Generation
lOT Instruction
lOT Instruction Decoding
J-K
Keyboard Reader

6-5

Keyboard/Printer

1-6

KF12B
KP12 Instructions
KP12 Power Failure Option
KP12 Power Fail/Restart
KW12-A Input Panel
KW12-A Instructions
KW12-A Real-Time Interface
KW12-AwithA-D
KW12-B,KW12-C
KW12-B, C Instructions

6-74

Operand (J3-Class)

3-17
3-22

3-12

6-74

SCR Scale Right

3-18

6-22

SET Set a-Register

3-14

6-22

SFA Place Special Function FUp-Flops in AC 3-30

6-18

SHD Skip if Half Differs

3-14

SKP Skip Unconditionally
SNS Sense Switch

3-20

SRO Skip and Rotate (j3-Class)
STA Store Accumulator 03-Class)

3-13

6-22
6-25

6-26

STC Store and Clear (Direct Address)
LAP6-DIAL-MS
LINC Instruction Trap
LINC Mode Direct Access Devices

3-22

6-44

3-24

3-20

3-8

3-7

STH Store Half
SXL Skip on External Level

3-14

XSK Index and Skip

3-15

3-20

1-5

Full-Word Logic

Half-Word Addressing, defined

LINC Mode I/O Bus Access
LINC Mode lOT Instructions
LINC Mode, Memory Modules
LINC Mode Programming
LINC Mode Program Interrupt
LINC Mode Provisions of
LINC Switch to LINC Mode
LINCtape, Equipment Required

Tape Buffer (TB)

3-11

Tape Memory Address (TMA)
Tape Motion

1-4

3-25

Tape Trap
Tape Word Skip

3-1

3-26
1-4

4-12
1-1,1-5

340
347

Tape Interrupt Enable

3-13,3-14

LINC-8, Comparison with PDP-12

LINC-8 Programs

341

342
349
349
1-1

3-31,349

LINC-8 Program Changes

Line Printers

6-59

LINCtape Formats

3-37

Instructions, LP08 Line Printer

LINCtape Instructions

3-43

Instructions, LP12 Line Printer

6-59

LINCtape Option, TCI 2-F
LINCtape Processor Information Paths
LINCtape Programming

6-57

Line Printer and Control LP08

6-60

3-40

Line Printer and Control, LP12

LINCtape Registers

3-39

LINCtape Transport, Type TU55
LINCtape TCI

2-1

LP08 Line Printer Specifications
Line Printer and Control LP08
Line Printer and Control, LP12

6-59

6-62
6-60
6-59

3-37

Unk

Block (LINCtape)

3-39

Link (L) I Bit

1-3

Block Number (BM)

3-39

Logic Conventions

5-3

Check Words (CM)
Checksum

3-39

Logic Symbols, Figure 5-1

3-39

LP08 line Printer and Control
LP08 Line Printer Instructions
LP08 Line Printer Specifications
LP12 Line Printer and Control
LP12 Line Printer Instructions

Control Registers

3-40

Data Path

3-39

Data Words (DM, FM)

3-39

Extended Address Format

346
345
341
347
342

Extended Operations
Extended Operations Buffer
Extended Units
First Word

Guard Word (GM)
Hold Unit Motion
Instruction Format
LINCtape Instructions

AXO AC to XOB
CHK Check One Tape Block
lOB-LMR Load Maintenance Register

MTB Move Toward Block
RDC Read and Check
RDE Read Tape
RDG Read and Check Group

3-8,3-9

5-3

LT37-AD Option, Teletype

6-60
6-60
6-62
6-59
6-59

64,F-3

M
Magnetic Tape

645

3-39

Command Register Contents, Magnetic Tape

348
341

Continued Operations, Magnetic Tape

6-49

Functional Description, Magnetic Tape Contro

6-45

6-51

3-43

General Description, TU20C

6-56

346
345
348
345
343

Instructions, Magnetic Tape Control

645

LINCtape Option, TCI 2-F

6-57

Magnetic Tape Control, TC58
Magnetic Tape Functions

645
647

Magnetic Tape Transports

6-54

3-43

Magnetic Tape Transports, TU20

343

(7 Channel, 9-Track)

Magnetic Tape Transport, TU20C

6-54

STD Skip if Tape Done

3-48

TAC Tape Accumulator to AC

345

TMA Load TMA Setup Register
TWC Skip on Tape Word Complete
XOA XOB to AC

3-46

Magnetic Tape Control Instructions

6-45

349
346

Magnetic Tape Functions

6-47

Magnetic Tape Transports

6-54

3-44

Magnetic Tape Transports, TU20

344
344
340

Magnetic Tape Transport, TU20C

6-56

Maintenance Mode

3-49

Mark Condition
MARK 12 Program

3-48

WCG Write and Check Group
WRC Write and Check
WRI Write Tape
LINCtape Processor Information Paths
LINCtape Programming

1-6

3-41

6-60

341

Maintenance Mode

3-49

Mark Condition

No Pause Condition

348
348

Organization of Data

3-37

Organization of LINCtape Data, Schematic

3-38

Read/Write Buffer (RWB)

Magnetic Tape Control, TC58

(7 Channel, 9-Track)

6-56
6-45

6-54

3-48

Mathematical Tables

H-1
6-13

3-39

Maximum Data Rates PT08
Memory Address Control
Memory Addressing Methods
Autoindexing, 8 Mode

Reverse Block Number (RBM)

3-39

Direct Addressing

4-2

Second Word

3-42

Indirect Addressing

4-3

Sub processor, LINCtape
Tape Accumulator (TAC)

3-39

Memory Reference Instruction Format
Summary Addressing Methods,

4-3

Tape Block Number (TBN)

341

340

8 Mode, Table of

3-24
4-2

Memory Address Register (MA) 12 Bits
Memory Buffer (MB), 12 Bits
Memory Control Programming

1-3

CRT Display, Character Size

1-3

Extended Tape Addressing with Core,
Tape Interrupt, Program Interrupt,
No-Pause, Hold-motion

1-4

Hold-Motion, Extended Tape Addressing

1-4

3-24

Memory, Description, Organization of,

1-5

Segments of, Pages of

1-4

Memory Extension Control

4-19

Interaction between Mode Switching

1-5

Memory Increment, Data Break
Memory Increment Data Break Timing

5-27

I/O Bus Access

1-4

5-28

No-Pause, Extended Tape Addressing

1-4

3-1

Special Functions, LINC Programming

1-5

1-1

Tape Interrupt, Extended Tape Addressing
Operation, Program Interrupt

4-12

4-7

Optical Mark Card Reader, CM 12

6-66

Memory, Organization of

Memory Reference Instructions
Memory Size, PDP-12
Microprogrammable

Microprogrammable EAE Instructions

Microprogramming Operate Class Group II

Mode Control
Mode Control, from 8 to LINC
Mode Programming,
Extended Memory
Organization of Memory, 8 Mode
PageO
Mode Status Register 1 Bit
Model 33ASR, Teletype
Model 33KSR, Teletype
Model 35KSR, Teletype
Model 37KSR, Teletype
Modes of Operation, LINC and 8

4-1,4-3,4-5

4-13
4-9

3-38

Organization of LINCtape Data, Schematic

Organization of Memory, 8 Mode

4-2

4-1

Organization of Memory, General

3-1

3-2

4-2

Data Field Reserved Locations
Field Address, Use of

4-1

Instruction Field and Data Field Registers

3-2

1-3

Instruction Field Reserved Locations

3-2

6-3

Program Counter, LINC mode
Reserved Field Address, 8 and LINC mode

3-2

4-2

6-3

3-2

6-4

Output, Data Transfers

5-11

6-4

Output, Data Transfers, Data Break

5-23

1-1

Overflow, defined

3-8

PageO

4-1

M-Series Module Summary

5-35

5-40

5-32

Pages, Memory

4-1

4-17

Paper Tape Punch and Reader PC 12

6-71

5-34

Paper Tape

6-71

Multiplication of 12-bit Numbers

Ml 01 Bus Data Interface
Ml 03 Device Selector
Ml 1 1/M906 Positive Input Circuit
M516 Positive Bus Receiver Input Circuit
M623/M906 Positive Output Circuit
M660 Bus Driver Output Circuit
M706 Receiver, Teletype Control

3-37

3-22

5-43

M-Series Flip-Chip Modules

6-1

Organization of Data

4-12

Module Cooling
Module Layout
Module Selection for Interface
Circuits of Peripheral Equipment

EAE Programming

Option Groupings, Peripheral Devices

1-4

5-33

Instructions, PCI 2, PP12 Paper Tape

Readers and Punch

6-71

5-30

Paper Tape Punch and Reader PC 12

6-71

5-31

PC 12 Paper Tape Punch and Reader
PC12,PP12 Instructions

6-71

6-5

PDP-8 Options used with PDP-12
Perforated Tape Loader

D-1

6-5

5-31

5-32

6-71

6-1

Peripheral Devices

6-1

Multi-Level Automatic Priority Interrupt

5-15

Peripheral Equipment requirements of

5-4

Multiple Teletype Control DC02-E

6-13

Peripheral Expander, BA12

6-1

Multiple Teletype Control, DC02-F

6-16

Peripheral Status Testing

Multiple Use of lOS and Program Interrupt

5-14

Point Displays

3-32

4-16

PP12 Paper Tape Punch

6-71

M707 Transmitter, Teletype Control

Multiplication

Prewired, Optional Groupings

Power Fail/Restart

Non-Bus I/O Devices

1-5

No Pause Condition

3-48

No Pause, Extended Tape Addressing

1-4

6-74

KP12 Power Fail/Restart
KP12 Power Failure Option

6-74

Program Counter, LINC mode
Program Counter (PC) 12 Bits

Operands

3-3

Program Interrupt

Operate Class: Group I

4-7

Operate Class: Group II

4-9

Program Interrupt, see LINC
Mode and 8 Mode Programming

4-6

Programmed Data Transfers

Operate Class Instructions

6-1

6-74

Instructions, KP12

Program Control

5-9

6-74
3-15
3-2
1-3

4-12,5-12

5-2

Operation of EAE

4-13

Conventions, Logic

5-3

Operating Modes

1-4

Data Break Transfers

5-2

1-5

Logic Symbols

5-3

Character Size, CRT Display

1-7

Program Interrupt

5-2

KW12-A Input Panel

6-22

Signal Names

5-2

KWl 2- A Instructions

6-22

5-4

6-22
6-26

Accumulator, I/O Transfers

5-9

KW12-AwithA-D
KW12-B,KW12-C

Data Transfer Timing

5-6

KW 2-B C Instructions

Data Transfers, Input

5-10

Programmed Data Transfers and I/O Control

5-7

Device Selector
Input Data Transfers

5-10

Input/Output Skip

5-8

5-13

lOT Command Pulse Generation
lOT Instruction Decoding
Multiple Use of lOS and Program Interrupt

5-14

Output Data Transfers

5-11

Peripheral Status Testing

Programmed Data Transfer Interface Diagram
Programmed Data Transfer Timing
Programmed Interrupt, I/O
Timing and lOP Generator
Program Intenupt
lOF Interrupt Off

5-7

5-9
5-5

5-6

5-11
5-6

4-12
4-13

Program Interrupt, Multiple Inputs
Program Interrupt Request

Program Interrupt, Using the

Programmable Real-Time Interface KW12A
Programmed Data Transfers description of

Programmed Data Transfer Interface Diagram
Programmed Data Transfer Timing
Programmed Interrupt, I/O
Programmed Interrupt and Instruction Trap
Ptogramming

6-18

4-19
3-36

Relays

Relay Buffer Equipment Description
Reserved Field Address, 8 and LINC Mode

1-1,1-5

3-36
3-2

Reverse Block Number (RBM)

3-39

RF/RS08 Disk Memory System
RF/RS08 kistructions
RF/RS08 Programming, Example
RF/RS08 Specifications
RK08/RK01 Disk Cartridge Memory
RK08/RK01 Instructions
RK08/RK01 I/O Subroutine Programming Example
RK08/RK01 Specifications

6-30
6-30
6-34
6-37
6-38
6-38
6-43

6-43

4-13

Program Interrupt, Using the

Program Interrupt LINC mode

Real Time Interface, KW12-A

6-25

4-12

ION Interrupt On
Program Interrupt, Extended Memory Programming
Program Interrupt, Extended Tape Addressing

Relay Terminals and Corresponding AC Bits

lOS and Program Interrupt
Multiple Inputs

Sample and Hold Options AFOl A

6-81

Save Field Register, Extended Memory

4-19

Save Field Register, purpose

3-24

Scaling, defined, see Shift and Rotate Operations

3-16

5-12

Second Word

3-42

4-13

Sense Lines

4-22
1-4

3-26,4-13

5-13

1-6
5-1

5-5

5-6
5-11
3-31

1 -5

Shift and Rotate Operations

3-16

SHL, NMI Shift Path for
Signal Names

4-15

Single and Dual

5-2
3-8

Sign-bit

TTY Control,

Type PT08 Teletype Control
Single Teletype Control Type DP 12-

6-10
6-9

Disk Software

6-44

Skip, defined

3-19

EAE

4-16

Skip Instructions

3-19

Extended Memory

4-21

Skip loop programming example

3-23

6-7

Skips external

3-20

3-1

Format Routine, Teletype

LINC Mode
PT08

RK8/RK01 I/O Subroutine
Teletype

Skips, Miscellaneous

3-21

6-10

Special Functions, LINC mode

3-29

6-42

Special Functions, LINC progranuning

1-5

6-7

Specifications, AFOl-A A-D Converter

6-76

4-1

Specifications, DC02-E

6-14

PR12 Paper Tape Reader

6-72

Specifications, RF/RS08

6-37

PR 12 Paper Tape Reader Instructions

6-72

Specifications, RK08/RK01

6-43

8 Mode

PT08 Equipment Configuration
PT08 Instructions
PT08 Programming
PT08 Specifications

6-11
6-11

6-10
6-10

Stand Alone Peripherals, list of

3-42

Standard Mode, LINCtape

3-40

Status or Error Conditions,

Magnetic Tape
Subprocessor, LINCtape

Q-R

6-2

Standard Mode Addressing, LINCtape

6-49

3-39

Summary Addressing Methods, 8 Mode
4-4

Random Access Disk File,
Types DF/DS32 and DF/DS32-D
Read/Write Buffer (RWB)

6-27

Symbols and Abbreviations

1-6

3-39

System Configuration

1-1

Real Time Qocks

6-18

Analog Inputs, Equipment

1-1

Counter Register, KW12-A

6-22

CRT Display, Equipment

1-1

Frequency Range, KW12-B, C

6-26

LINCtape, Equipment Required

1-1

Input Synchronizers, KW12-A

6-19

Relay Buffer, Equipment Description

1-1

1-8

Table of

PT08 Equipment Configuration
PT08 Specifications

6-11

6-10

Table of Codes

F-1

Single Teletype Control, DP 12-

Tape Accumulator (TAC)

340

Specifications, DC02-E

Tape Block Number (TBN)
Tape Buffer (TB)

341

Stand Alone Peripherals, List of

6-2

Teleprinter/Punch

6-7

Tape Interrupt Enable
Tape Interrupt, Extended Tape Addressing
Tape Maintenance Instructions

340
347
14

6-9

6-14

Teletype Controls

1-6

Teletype Interface, DP12-A

E-1

Teletype Model 33ASR Controls

Tape Motion
Tape Memory (TMA)

342

Teletype, Subroutine

341

Ten Bit indexing. Program Counter

3-2

Tape Processor Major State Indicators
Tape Trap

Three Cycle Data Break
Three Cycle Data Break Timing

5-29

Timing and lOP Generator

5-6

3-21,3-31,349

Tape Word Skip
TC12-F LINCtape Option

3-49

TC58 Instructions

645
645

6-57

TC58, Magnetic Tape Control
Teleprinter/Punch

6-7

Teletype Code, discussion

6-3

Teletype

6-3

Console Teletype Control

6-5

Dataphone Control, DPI 2-B

6-9

DC02-D Instructions
DC02-E Control Instructions

6-15

6-14
6-7

Format Routines
Instructions, Console Teletype Control

6-5

Instructions, PT08

6-11

Keyboard Reader

6-5

LT37-AD Option, Teletype
Maximum Data Rates PT08
Model 33ASR, Teletype
Model 33KSR, Teletype
,

DC02-E
Multiple Teletype Control, DC02-F

Multiple Teletype Control

Option Groupings, Peripheral Devices
Prewired, Optional Groupings

Programming the PT08

Transfer Class, Input/Output

4-12

Transfers, Data Break

5-15

Transports, Magnetic Tape

6-54

Turnaround State, Tape
TU20 Magnetic Tape Transport,

3-42

6-54,6-56

General Description

TU20C Magnetic Tape Transport
TU55 Tape Transport Controls and Indicators
TU55/56 Tape Transports
Two-Word EAE Instructions
Two-Word Instruction

6-56
2-12
1-5

4-14

u-v-w

6-4

6-3

5-29

2-6

Toggle Switch Registers

Wiring Hints

542

Word Count Overflow, Three Cycle Data Break

5-30

64
64

Model 35KSR, Teletype
Model 37KSR, Teletype

6-7

6-13
6-3

2-1,2-14

X-Y-Z

6-13

6-16
6-1

6-1
6- 1

XY Plotters

6-68

Incremental Plotter and Control,

XY12
instructions XY12 Plotter

6-68
6-68

1-9

PDP-12 COMPUTER
SYSTEM REFERENCE MANUAL

DEC-12-SRZB-D

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