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OCR Text

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LV8/LV12/LV11

printer/plotter
user’s guide

laboratory data products

DEC-1 2-HLVAA-A-D

LV8/LV12/LV11

printer/plotter
user’s guide

digital equipment corporation magnard, mossochusetts
-

_.._._._,

First Edition, January 1973
2nd Printing, August 1973

The material in this manual is for informational purposes and is
notice.

subject to change without

The technical information and halftones contained in

Chapter 2, Installation, are reprinted courtesy of
Versatec, Inc., Cupertino, California.

The

following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS

Page
CHAPTER 1

INTRODUCTION

1.1

Scope

1.2

General Description

1.3

Functional Description

1.3.1

Print Mode

1.3.2-

Plot Mode

1.3.3

LV8 Interface

1.3.4

LV11 Interface

............................................

.....................................

....................................

.......................................

.....................................

1-4

INSTALLATION

2.1

Unpacking Instructions
Removing LVOl Unit from Shipping Container
Inspecting LVOl Unit for Shipping Damage
Opening the Mechanical Module
Operating Supplies
Cabling Requirements

...................................

....................

......................

2-4

....................................

......................................

2-4

LVOl to Interface Controller

2.2.3

LV11, LV8 Interface Controller Module Mounting

.............................

2.3

Jumper Configurations
LV11 (M7258) Jumpers
LV8 (M8302) Jumpers
Packing LVOl for Shipment

CHAPTER 3

OPERATION AND PROGRAMMING

3.1

3.2

Operating Instructions
Loading Roll-Type Electrographic Paper
Loading Fanfold Type Electrographic Paper
Loading with Toner
Operator Controls and Indicators

3.3

LVOl Printer ASCII Character Set

3.4

Format Control Codes

3.5

Programming Considerations

3.6

PDP-ll Programming

3.1.1
3.1.2

3.1.3

..................

.................................

.............................

..............................

.................................

2-4

2-4
2-5
2-5
2-6
2-6

....................................

3-1

........................

3-1

......................

..................................

..............................

....................................

3-4
3-10

3-11
3-12
3-13

.................................

3-14

....................................

3-14

3.6.1

Control and Status Register (LVCS)

3.6.2

Data Buffer Register (LVDB)

3.6.3

2-1

2-2

2.2.2

2.2.4.2

2-1

...................................

Power Cable

2.2.4.1

2—1

............................

2.2.1

2.2.4

1-3
1-3

CHAPTER 2

2.2

1-2

....................................

Reference Documents

2.1.4

1-2

1-3

1.5

2.1.3

1-2

.....................................

LVOl Specifications

2.1.2

1-1

.....................................

1.4

2.1.1

1-1

..........................

3-15

.............................

3-16

.......................................

3-16

.................................

3-16

....................................

3-16

.....................................

3-17

3.7

Interrupts
PDP-8/PDP-12 Programming

3.7.1

IOT Instructions

3.7.2

Status Register

3.7.3

Programming Considerations

..............................

iii

3-18

CONTENTS (Cont)

Page
CHAPTER 4

PRINCIPLES OF OPERATION

4.1

LVOl Printer/Plotter

.....................................

4.1.1

General Operation

4.1.2

Electrostatic Writing Technique

4.2
4.2.1

...................................

LVll Detailed Description

..................................

Address Selection Logic

................................

4.2.1.1

Address Inputs

4.2.1.2

4.3.1

Outputs
Interrupt Control
Data Register Logic
Printer Control Logic
LV8 Detailed Description
IOT Decoding

4.3.2

Printer Control

4.3.3

Data Register

4.3.4

Interrupt and Skip Control

4.2.2
4.2.3
4.2.4
4.3

..................................

.....................................

MAINTENANCE

5.1

Inspection
Diagnostics

4-1

4-2

4-2
4-2
4-3

4-5

...................................

4-6

..................................

4-7

.................................

..................................

.....................................

CHAPTER 5

5.2

............................

4-1

.....................................

......................................

...............................

4-7
4-9
4-10
4-11
4-12

4-12

..........................................

5-1

..........................................

5-1

ILLUSTRATIONS
Title

Figure No.
1-1

LVOl Functional Block Diagram

2-1

Damage Inspection

Page

...............................

......................................

.....................................

2-2

......................................

2-3

2-2

Back Panel Removed

2{3

Platen Raised View

244

3-5

Removing Packing Material
Paper Removal
Inserting Cross in Roll Paper
Inserting Roll Paper
Paper Pulled Out
Paper Transport Module

3-6

Control Panel

3-7

Fanfold Paper Guide

3-8

3-16

Paper Stacking Insert
Paper Supply Compartment
‘Fan’ the Paper to Loosen the Sheets
Position of Stack for Fanfold Operation
Loading Paper over the Paper Guide Assembly
Positioning the Paper Left-to-Right on the Paper Roller
Paper Loaded and Top Casting Closed
Location of Paper Receiver Basket
Inserting Tubes in Toner Bottle

3-17

Toner and Concentrate Bottles Installed

3-18

Control and Status Register Bit Assignments

3-1
3-2
3-3
3-4

3-9
3-10
3-11

3-12
3-13
3-14
3-15

1-2
2-1

.................................

2-3

........................................

3-2

.................................

3-2

.....................................

.......................................

3-3

...................................

3-4

........................................

3-4

.....................................

3-5

.....................................

3-5

.................................

3-5

............................

3-7

...........................

3-8

........................

3-8

...................

3-9

............................

3-9

..............................

3—9

...............................

3-10

...........................

.........................

3-10

3-15

ILLUSTRATIONS (Cont)
Title

Figure No.

Page

.....................................

3-16

....................................

4-1

3-19

Data Buffer Register

4—1

LVOl Interface Signals

4—2

LVll Functional Block Diagram

4.3

Address Selection Logic, Simplified Diagram

4.4

Controller Select Address Format

Interrupt Control Logic, Simplified Block Diagram

4—6

LVll Character Transfer, Timing Diagram

4.7

FF and LF Timing Diagrams

4—8

Remote Control Timing Diagram

4—9

Plot Mode Timing Diagram

4—10

LV8 Functional Block Diagram

...............................

........................

..............................

.....................

..........................

.................................

4-3
4-4
4-4

4-6

4-8
4-9

..............................

4-10

..................................

4-10

...............................

4-11

TABLES

Table No.

Title

2-1

M7258 Jumpers

3-1

LVOl Controls and Indicators

3-2

LVOl ASCII Codes

3-3

Format Control Codes

3-4

IOT Programming Instructions

3-5

Status Register Bit Assignments

4—1

Select Lines

4-2

Gating Control Signals

.......................................

................................

......................................

....................................

................................

...............................

.........................................

....................................

"“‘v a-wnmv

m'"\w "v

u”,

Page
2-5
3-11
3-12
3-13
3-17

3-17

4-5
4-5

CHAPTER 1

INTRODUCTION

1.1

SCOPE

guide contains operating, installation, programming, and technical reference data on the LV8/LV12/LV11
Printer/Plotter System. The printer/plotter system consists of two components: an LVOl Line Printer/Plotter
(manufactured by Versatec, Inc.) and a Digital Equipment Corporation (DEC) computer interface unit. The
interface unit designations for use with each DEC computer are listed below.
This

Interface

Used with DEC Computer

LV8

LV12

PDP-8/E, PDP-8 / M
PDP-12, PDP-8/I, PDP-8/L
(positive bus only)

LVll

PDP-ll

For example, the LV11 system consists of an LVOl Printer/Plotter and an LVll Interface Controller for use with a

PDP-ll computer.

guide and the Versatec maintenance manual must be used together for a complete understanding of the
printer/plotter system. The prime subject of this guide is the LV8, LV12, and LVll Controller. The prime subject of
This

the Versatec maintenance manual is the printer/plotter itself; the manual presents a detailed discussion of the print
and plot mechanisms, including installation, operation, maintenance, troubleshooting, and engineering drawings.

Paragraph 1.5 lists all reference documents related to the printer/ plotter system.
1.2

GENERAL DESCRIPTION

The LVOl Printer/Plotter is a hard copy device manufactured by Versatec, Inc., Cupertino, California, to an exacting
set of DEC

specifications. Its speed, compact size, and quietness of operation make it ideal for use in hospitals,

research laboratories, and offices. The line printer has 132 columns, a 96 ASCII character set, and prints at a speed
of up to 500 lines per minute (full line). The plotter speed is 120 lines per second maximum, with a data transfer
rate of 500K bytes per second maximum.

Printing is accomplished by depositing an electrostatic charge on a dielectric surface and blackening the charged
areas with fine particles deposited from a liquid toner. The paper is then dried by directing air flow over the paper.
The LVOl is available in two models. The 115V model, designated LVOl-BA, handles 104—132 Vac at 50 or 60 Hz.
The 240V model, designated LVOl-BB, handles 208—264 Vac at 50 or 60 Hz.

1-1

Interfaces between the LVOl and most DEC computers

are

available. The interface between the LVOl and

PDP-8/E or PDP-8/M is designated LV8; the interface between the LVOl and a PDP-12 is designated LV12; the
interface between the LVOl and a PDP-ll is designated LV11. The LV8 and LVll interfaces are described in this
manual; LV12 operation is identical to the LV8 interface operation.
1.3

FUNCTIONAL DESCRIPTION (Figure 1-1)

1.3.1

Print Mode

In the print mode of operation, the LVOl accepts, in parallel, 7-bit ASCII input code from the LV8, LV12, or LVll

Controller. Each character received is stored in a l32-character memory (buffer). These 132 characters represent one

full line of data on 11-inch wide paper. Once the 132-character memory is full, the LVOl automatically prints the
132 characters on a line and then performs an automatic carriage return. If less than a full line is received, certain
format control codes (described in Table 3-3) must be transmitted to the LVOl to initiate printing of that line.

CONTROL,STATUS
OMNIBUS

PDP- 8/E

PROCESSOR

LV8
INTERFACE

DATA

mfg/PER /
PLOTTER

CONTROL,STATUS
PUP-12 0R
PDP-8/I
PROCESSOR

POS. r/o BUS

LV12
,NTERFACE

DATA

LVO‘
PRINTER/
PLOTTER

CONTROL,STATUS
POP—11

UNIBUS

LV11

PROCESSOR

INTERFACE

DATA

mfg/19%,
PLOTTER

(SP-0413

Figure 1-1
When

LVOl Functional Block Diagram

printing is to occur, each ASCII character must be decoded and translated in the form of horizontal and

vertical dots that can produce a recognizable image on the paper surface. Each character is composed of dots within
7 X 9 matrix; a total of 63 bits of binary information are associated with each character. Read-only memories
(ROMS) are used to store this information until needed by the printer. These bits are sequentially applied to the
a

writing points to produce the desired pattern. When a black dot is required, a charge is placed on the paper; when no
dot is required, no charge is applied to the paper. This process, which is also known as the raster scan method of
writing, is similar to the writing technique used in television and on television-like terminals.
1.3.2

Plot Mode

When the plot mode of operation is selected, the LVOl accepts, in parallel, 8-bit data bytes. This binary information
is stored in a 1024-bit buffer which represents a full scan line on ll-inch paper. The line is automatically printed

byte (128th) is received. The character generator used in the print mode is disabled and the
unweighted binary information is transferred directly to the writing surface. Input bit 08 prints as the left-most
writing point in the current byte when viewing the resultant printout. As an example, input bit 08 would print as the
first dot on a scan line if set in the first byte of data transmitted.

when the last

Because of the electrostatic method of writing, data must be presented to the plotter in the form of a bit map of the

graphical information. This can be accomplished with a basic software package which translates simple
required binary data. Unlike pen plotters, speed is not dependent on the complexity of the
image to be produced. For example, the LVOl could produce an 8-1/ 2 inch long X 11 inch wide graph or chart in 10
seconds, regardless of complexity. This opens a new dimension in the use of plotting with computers, since pen
plotters have always had a severe limitation on speed due to the necessity of writing every line with a single writing
desired

commands into the

pen.

The ability to produce shading or complex minute patterns in a plot is a feature of the LV01. The writing points are

spaced at 0.010 inch intervals and allow the accurate reproduction of minute details.
Plotting applications that can be accommodated on fanfold paper are easier to store, handle, and preserve for future
reference. For this reason, the ASCII functions of Form Feed (FF) and End-of-Transmission (EOT) are made
available to the user. They are accomplished by pulsing the remote control line associated with that function. These
two functions allow formatting of the graphics so printing can begin at the top of a page and the finished graph can
be ejected into the viewing area for examination and/ or removal.
1.3.3

LV8 Interface

The LV8 Interface Controller transfers data from the PDP-8/E AC (via the DATA lines on the OMNIBUS) to the
LV01 under program control. In the plot mode, data is transferred in 8-bit bytes using AC bits 04 through 11. The
most

significant digit is bit AC 04, which prints at the left-most writing point of the data byte when viewing the

c0py. For the print mode, data is transferred in 7-bit characters using AC bits 05 through 11. AC bit 11 is bit 01 of
the ASCII character.
In addition, the LV8 monitors all line printer error conditions and initiates interrupt requests to the PDP-8. All of

the LV8 logic is contained on one module designated M8302. This interface module is discussed in detail in Chapter
4 of this guide.

NOTE
The interface controller for the PDP-12 and PDP-8/I (positive

I/O bus only) is designated LV12 and operates similarly to
the LV8.

1.3.4

LV11 Interface

The LV11 Interface Controller provides interface logic between the LV01 and a PDP-ll processor. The PDP-ll
transfers data utilizing byte instructions to the low order byte of a PDP-ll word (bits 07 through 00). For the print

mode, 7-bit ASCII characters (the eighth bit, bit 07, is ignored) are transferred to the LV11 via the Unibus. The plot
mode utilizes all eight bits of the low order PDP-ll word. The LV11, in turn, transfers the characters to the line
printer/ plotter while maintaining program status information and generating program interrupts.
'

All logic for the LV11 is implemented on one M7258

quad integrated circuit module. This interface module is

discussed in detail in Chapter 4 of this guide.

1.4

LV01 SPECIFICATIONS

Physical
Width

19 in. (0.48m)

Height
Depth
Weight

38 in. (0.96m)

18 in. (0.46m)

160 lb. (72 kg)

Electrical
LV01-BA

104—132 Vac, 47—63 Hz, single-phase

LV01-BB

208—264 Vac, 47—63 Hz, single-phase

Power/ Heat Dissipation

600W/ 2000 Btu/hr

Environmental

Operating Temperature
Relative Humidity

50° to 110°F (10° to 45°C)
20% to 80% (non-condensing)

Operational
Paper Drive
Paper Drive Increment
Paper Advance Speed
Writing Spot Size
Paper Width

Incremental
0.010 in.

1.20 in./ second
0.0075 in. diameter
11 in.

Plotter

Plotting Area
Total Writing Points
Writing Point Spacing
Input

10.24 in.
1024
0.010 in. center to center

8-bit bytes/ parallel

Data Transfer Rate

500K bytes/ second maximum

Plotting Speed
Memory

One line buffer (1024 bits)

120 lines/ second maximum

Printer

Columns

12.5 in.

Line Spacing

7.6 in.

Character Font

7 X 9 dot matrix

Character Generator

Read-only memory (ROM)
5001ines/minute printing 132 columns/line
7-bit ASCII, USASX3.4-1968, parallel
no parity
96 (95 printing characters and a space)
One line buffer (132 characters)

Speed
Input Code
Character Set

Memory
1.5

132

Character Spacing

REFERENCE DOCUMENTS

The following documents supplement the information contained in this guide:

PDP-8/E and PDP-8/M Small Computer Handbook, DEC., 1972
PDP-8/I Maintenance Manual, Volume 1, DEC-SI-HRIA-D

PDP-8/E, PDP-8/F and PDP-8/ M Maintenance Manual, Volume 1, DEC-8E-HR1B-D
PDP-ll Peripherals and Interfacing Handbook
PDP-l 1/ 20, PDP-l 1/40, PDP-11/45 Handbooks

PDP-12 Maintenance Manual, Volume 1, DEC-12-HRlB-D

Versatec, Inc. Maintenance Manual for 1100A DEC Printer/Plotter, document number M-llOOA-DEC-Ol

CHAPTER 2

INSTALLATION

2.1

UNPACKING INSTRUCTIONS

2.1.1

Removing LV01 Unit from Shipping Container

The LV01 is shipped in a shock-resistant wooden box. Lift the entire top portion of the box off of the base (after
the restraining straps have been removed). Next unstrap the LV01 unit and lift it off the base.

2.1.2

Inspecting LV01 Unit for Shipping Damage

A complete inspection should be made for any shipping damage. A typical sign of a damaged machine could appear
as

cabinet distortion. The top casting (Figure 2-1) should be opened and closed carefully to ensure that it has not

been damaged, distorted, or misaligned during shipment. Check the casters and observe that the unit rolls about

freely.
PLATEN

TOP CASTING

_.-

41""

Figure 2-1

Damage Inspection

2-1

The front panel is hinged on the left side and held in place by a magnetic catch on the right side. Pull at the upper

right corner to open this panel. The side panels are held in place by two snaps at the top. To remove the panel, pull
out on the top of the panel, then lower the panel to remove it. The back panel is taken off by loosening (1/2 turn to
the left) the two fasteners at the top. After the rear panel is removed, a visual inspection should be made to
determine if any of the electrical components have become loose during shipment (Figure '2-2).

Figure 2-2

2.1.3

Back Panel Removed

Opening the Mechanical Module

Open the top casting as far as it will go. In the raised position, it is held open by its own weight. Raise the black
handle (Figure 2-3) which releases the platen module. Raise the platen until it is held open by its own weight.
Remove the protective packing material that has been placed over the writing head and toner channel (Figure 2-4).

The metal “spool-cross” is normally taped in place in the “L” shaped brackets. This can be freed by removing any

tape that was used to secure it during shipping.

Inspect for possible damage to the back-up electrodes (double segmented bar) and paper drive roller located at the
top of the module. The writing head is located between the paper supply compartment and the toner applicator
channel.
A light attempt to move the writing head should determine if it has loosened during shipment. If it has loosened,

re-alignment of the writing head is necessary. This procedure is described in the preventive maintenance chapter of
theVersatec maintenance manual.

Figure 2-4

Removing Packing Material

2-3

2.1.4

Operating Supplies

The following items are included with each LV01 unit:
One (1)

LV8/LV12/LV11 User’s Guide (DEC no. DEC-12-HLVAA-A-D)

One (1) two-gallon bottle of Toner Pre-Mix (DEC no. 49—01099)

One (1) eight-ounce bottle of Toner Concentrate (DEC no. 49-01100)
One (1) bottle of clear dispersant for cleaning purposes (DEC no. 49—01 101)
One (1) carton of 1000 feet continuous form fanfold paper (DEC no. 36-11227—01)

Since print quality depends on the type and characteristics of paper and toner used, supplies furnished by DEC are

recommended for proper operation. Performance may be
performance cannot be guaranteed.
2.2

degraded

if other

supplies

are

used and machine

CABLING REQUIREMENTS

2.2.1

Power Cable

A 7.5-foot power cord is permanently attached to the LV01 at the rear of the machine adjacent to the fuse holder.

The cord for 60 Hz systems terminates in a standard 3-wire, male, wall-type plug (NEMA 5-15P). The cord for 50 Hz

systems has 3 15A, 250V male plug (NEMA 6-15P).
CAUTION

LV01 power requirements are 104—132 Vac, 3A, 47—63 Hz
or 208—264 Vac, 47—63 Hz, 600W maximum. Prolonged

operation above or below rated voltages may cause equipment
failure and void the warranty. A 3-wire (hot, neutral, ground)
receptacle must be available for proper power application. If a
proper 3-wire receptacle is not available, a separate wire must
be connected from the LV01 chassis to “earth groun ”.
WARNING
Do not work

the LV01 unit without disconnecting main

power to the machine. Make sure that the safety screen over
the power supply section at the rear of machine is always

Dangerous voltages of approximately 1000V are
present in this section during operation.

installed.

2.2.2

LV01 to Interface Controller

The interface cable between the LV01

and the

D-IA-7009133—0-0. The LV01 connects to

respective LVll

LV8 interface is shown

DEC

drawing

Cannon DCC-37P located at the lower left corner on the rear of the

LV01. The cable terminates at the interface in a Berg connector (DEC no. 12-09941).

2.2.3

LVl 1, LV8 Interface Controller Module Mounting

The M7258 module (LVll) is mounted in either a DDll-A mounting unit

or one

of the slots of the processor

mounting box. Refer to the PDP-I 1 Peripherals and Interfacing Handbook for detailed information on mounting and
Unibus connections.

The M8302 module (LV8) should be mounted in accordance with the recommended order of PDP-8/E module

installation as listed in Table 2-3 of the PDP—8/E, PDP—8/F and PDP-8/M Maintenance Manual, Volume 1.

2.2.4

Jumper Configurations

2.2.4.1

LV11 (M7258) Jumpers

—

Table 2-1 lists the required M7258 jumpers and their function.

Table 2-1

M7258 Jumpers

Jumper

Purpose

Function

A4, A5, A7

Address Selection

Jumpers A3 through A12 are used to select the bus address to which
the M7258 module will respond. The assigned address, 77751x, is
selected by removing all “A” jumpers except A4, A5, and A7.

J14

Address Selection

Jumpers J12, J 13, and J 14 are used to further define the bus address
for the LV11. The LV11 is normally configured with J14 installed.
This causes the address logic to assert BUS SSYN L when either
address 777514 or 777516 is decoded.

Vector Address

The LV11

uses

the vector block at address 200. Removing all “V”

jumpers except V7 will produce this interrupt vector address.
Nl

NPR latency

This jumper is normally installed to improve bus latency on NPR

devices. New systems on the PDP-11/15 and PDP-11/20 are shipped

with a KHll option which allows use of the N1 jumper. If the LV11
is an add-on option to a PDP-l 1/15/20, verification that the KHll

has been installed must be made or the system may malfunction. If
the KHll has not been installed, removal of the N1 jumper will

disable this circuitry on the M7258.

The M7258 module

was

designed as a multipurpose interface/controller. Jumpers J1 through J 11 are used to

accommodate differing signal polarities and control features of these various devices. A general discussion of the

jumpers as they apply to the LV11 follows.
J1

Miscellaneous

Jumpers J l and 12 provide conversion of lower case ASCII codes to
the corresponding upper case character before loading the LVDB.
With J1 installed, ASCII bit 6 is
receivers to the data register.

13, J5

passed unaltered from the bus

These jumpers allow connection of the P DATA 8 H signal to ASCII
bit 6, thus allowing the P DATA 8 H signal to be used as a control
line. Jumpers J3 and J5 are installed on the LV11 and pass the data

unaltered from the LVDB to the LVOl.

2-5

Table 2-1 (Cont)
M7258 Jumpers

Jumper

Function

Purpose

Jumpers J6 and J7 select the proper clock polarity for the clock
input to the Done flip-flop. J7 is installed for the LVll since the
Ready line from the LVOl is low (ground) when true. Thus, the
high-to-low transition of the Ready line is inverted and applied to
the clock input as a positive transition clocking the Done flip-flop.

Jumpers J8 and J9 select the correct Strobe polarity for the LVOl.
The LVOl requires a positive pulse for a strobe signal so jumper J9 is
installed for LVll operation.

JlO

Jumper J 10 is normally installed to allow the remote functions of
BUF

CLR, REM EOT, REM FF, LINE TERM, and MODE. These

remote

functions facilitate

formatting and data output when the
Jumper J11 installed will disable

LVll is used in the plot mode.
these functions.

2.2.4.2

LV8 (M8302) Jumpers

—

The only jumpers required on the LV8 M8302 module are the address decoders

that allow the 6657 instruction to be utilized. The

following jumpers are required on the M8302 for LV8

operation: W1, W3, W5, W7, W11, W12, and W14.
2.3

PACKING LVOl FOR SHIPMENT

Never ship the LVOl unit with toner and concentrate installed; ensure that critical items are secured before packing,

otherwise damage may result.
1.

Open front door and unscrew toner hose cap from the bottle. Remove concentrate bottle hose after
allowing the hose to drain in toner bottle.
Wrap paper towels around all of the tubes and cap and tape securely to prevent leakage.
Discard unused portion of toner and concentrate. Do not attempt to reseal bottles since leakage and

damage may occur during shipment.
Raise machine top cover and mechanical module top.
Remove roll type paper and tape empty “spool-cross” to its holder.

If fanfold paper is being used, remove paper guide and paper stacking insert from the machine. Remove
paper tray on rear of machine. Package these parts separately.

Fold paper towels to fit in toner applicator channel and insert with light pressure. There are three
sections, and each will hold at least one paper towel.

Using clear dispersant, wipe any dirt and toner from mechanical module, side, back panels, and door.
Close mechanical module top and lock.
10.

Wrap AC input cord and place inside the machine. Strap machine in original container for shipment.

2-6

CHAPTER 3
OPERATION AND PROGRAMMING

This chapter describes the loading procedures for both roll and fanfold paper and the toner, the LVOl operating

controls, the ASCII character set, the format control codes, and presents PDP-ll and PDP-8 programming
information relative to the LVOl.
3.1

OPERATING INSTRUCTIONS

This section describes the procedures for loading paper and toner and preparing the machine for operation.

3.1.1

Loading Roll-Type Electrographic Paper

To load roll paper, follow the instructions listed below.
1.

Remove paper roll from moisture resistant bag (Figure 3-1).

Insert “spool-cross” into paper core (Figure 3-2).

Position spool-cross in the spool holder which consists of the two “L”-shaped brackets on each side of
the paper supply compartment (Figure 3-3).
NOTE

The spring-loaded edge guide (a button on the right side) must

be held “in”

by the paper when properly
spool-cross should sit squarely in the holder.

loaded. The

Paper should come off the top of the roll (Figure 34). Since the paper has a dielectric coating on one
side only, it must be mounted correctly, as shown. No writing will occur if paper is mounted up-side
down (coming off the bottom of the roll).
Pull the paper forward off of the roll approximately 2 feet. It should pull easily if the spool-cross has

been installed correctly. With the platen module about 3/4 closed, run the paper back over the paper
drive roller onto the platen (ensure that paper is centered left to right on the roller) then close the platen
(Figure 3-5). Lock the platen module in place with the black handle on the left side.

After the platen has been lowered into place and locked, lift the paper and pull up. At this point the
paper is resting against the paper tear bar. With a twisting motion, paper can be torn off evenly against
this tear bar.
Check the position of the ROLL/FAN FOLD switch. It should be in the ROLL position. This switch is
located on the right side of the frame after opening the front panel (Figure 3-6).

3-1

‘

Figure 3-1

...¢...,..,_

Mum...» u-

Paper Removal

Cross

fit
in

”L“

Figure 3-2

Inserting Cross in Roll Paper

shaped bracket

the

must

squarely
bracket

4th
'

Aw.~\n~w)~‘/“w

”W

Figure 3-3

Flgure 34

Inserting Roll Paper

Paper Pulled Out

Figure 3-5

Paper Transport Module

Figure 3-6

3.1.2

Control Panel

Loading F anfold Type Electrographic Paper

The pages of the fanfold paper are perforated at the top and bottom for ease of folding, handling, and separating.

The fanfold paper guide and paper stacking insert are shown in Figures 3-7 and 3-8. These two parts are used for
fanfold paper Operation only. They are packaged separately for shipment.
To load fanfold paper, follow the instructions listed below: *
1.

Remove the spool-cross from the L-shaped paper support brackets. (One L-shaped bracket is located at

each side of the paper

supply compartment.) The spool-cross is used with roll paper only. Figure 3-9

shows the paper supply compartment with the spool-cross removed.

3-8) in the bottom of the paper supply compartment. For
“D” in Figure 3-11. Notice that the hinges on the paper stacking insert are located

Position the paper stacking insert (Figure

positioning,

see

toward the front of the machine when the insert is positioned properly.
*

Refer to Figures 3-11 and 3-12. These two figures are also found on the inside of the front panel.

Figure 3-7

Fanfold Paper Guide

Figure 3-8

Paper Stacking Insert

Remove a pack of fanfold paper from its carton. “Break” and “fan” the paper from both ends to loosen

the stack before installing in the machine (Figure 3-10).
For accurate positioning the paper should sit in the paper stacking insert. The rear of the stack of paper

should be higher than the front edge of the paper. The front edge of the stack should be under the hinge
of the paper stacking insert flap.

Load the paper stack with the

leading edge of the first sheet toward the front of the machine. The
rectangular black mark should be at the front right-hand edge of the stack (see “E”, Figure 3-11).
Printing occurs on the side of the paper opposite to that on which the black mark is located. The black
mark is sensed by the optical mark sensor located on the right side in the top of the mechanical module
directly below the back-up electrode (Figure 3-9).
Install the fanfold paper guide

assembly into the L-shaped paper support brackets (Figure 3-16). The
brace welded to each end of the fanfold paper guide should form the hypotenuse (hypotenuse being the
line of the triangle opposite the right angle) of a right triangle. The right angle of this same triangle is

formed by the L-shaped paper support brackets.
Pull the first fanfold sheet back under, then forward over the top of the Teflon coated tension roller, as

shown in Figure 3-12. The paper DOES NOT GO BETWEEN the horizontal aluminum spacer bar and
the tension roller. The paper DOES GO AROUND both the spacer bar and the tension roller.
Place the

U-shaped retainer, attached to a small chain on the right side of the installed assembly,
flange on the spring-loaded roll paper guide and the L-shaped paper support bracket (see
“H”, Figure 3-12). This keeps the roll paper guide depressed, which prevents interference to the paper
travel during fanfold operation.

between the

Pull out about 3 feet of paper as shown in Figure 3-13. Lower the platen module and ensure that the
paper is centered right and left on the paper roller, then fold the paper back onto the platen. Close the
platen module and lock it in place by pushing the black handle on the left side of the module all the way

down.
Close the top casting as shown in Figure 3-14. Notice that the black mark is not visible.
10.

Mount the paper receiver basket on the rear of the machine as shown in Figure 3-15. Metal hangers are

provided for the paper basket on the back of each machine.
ll.

Check the position of the ROLL/FAN FOLD switch. This switch is located on the front of the frame

(Figure 3-6) and can be seen after opening the front panel. At this time it should be in the FAN FOLD
position. Normal operation with fanfold paper can now proceed. Turn LVOl unit on. Press the FORM
FEED pushbutton and observe that the paper advances a page at a time. When actual operation begins,
check to see that the paper begins folding correctly in the receiver basket.
12.

If fanfold paper operation does not proceed properly, the paper may be misaligned with respect to the
sensor. Check paper and fanfold paper

guide assembly for correct installation (Figure 3-7).

If the

sensor becomes dirty or clogged with foreign material or
paper debris, it will not function
properly. Ensure that the sensor is kept clean at all times.

3—6

If the black mark is not sensed for any reason (e.g., dirty sensor, missing black mark on paper, or sensor

lamp failure) the sensor logic is disabled and the LVOl unit treats an EOT or FF the same as a line feed
(LP).

In the event that the sensor logic is disabled, turn power “off”, determine the cause of the malfunction

and correct it.

After the malfunction is corrected and power is turned “on” again, the sensor logic is automatically
reset.

When the ROLL/FAN FOLD switch is in the ROLL position, or when the LVOl unit is in the plot mode
of operation, the

top-of-form detection circuit is disabled. In the ROLL position, the FF, and EOT

control signals advance the paper 2.5 and 8 inches, respectively.

One L-shaped bracket is mounted at each end of the paper supply compartment. This assembly just sits in the

L-shaped brackets. It is not attached to the LVOl unit in any way.

Figure 3-10

‘Fan’ the Paper to Loosen the Sheets

L -s haped

Support

Figure 3-11

Fan Fold

Paper

Stacking

Insert

Bracket

Position of Stack for Fanfold Operation

6 Paper Guide

Spring Ioaded‘rOII
paper guide button

Figure 3-12

Loading Paper over the Paper Guide Assembly

Figure 3-13

Figure 3-14

Positioning the Paper Left-to-Right on the
Paper Roller

Paper Loaded and Top Casting Closed

Figure 3-15

Location of Paper Receiver Basket

3.1.3

Loading with Toner
1.

Open front door and remove packing tape from toner hoses and tubes.

Remove cap and aluminum seal from large bottle of toner pre-mix. Insert tubes into toner bottle and
screw cap on

securely (Figure 3-16).

Inspect all hoses to be sure that they are held securely in place. Hose clamps hold the top of the hoses to
the toner channel. Visual inspection should determine if any of the hoses have vibrated loose during
shipment. After the toner pump is turned on inspect the system for leaks.

Install small toner concentrate bottle in its holder as shown in Figure 3-17. Connect the small hose from

the injector spout to the top of the large bottle.
DO NOT ADD CONCENTRATE UNTIL NEEDED. The normal mixture of the toner pre-mix, as shipped, is usually

sufficient for four to six rolls of paper usage. The print may become light after this amount of usage (depending on
the amount of print-out or “black” being put on the paper). When concentrate is needed, it should be added a little
at a time (three injections maximum). It may take several minutes of operation to note a darkening in the print. The

decrease in contrast or fading of the printed message is a gradual one; therefore, an optimum toner mix can be
obtained by experimenting.

Figure 3-16

Inserting Tubes in Toner Bottle

Figure 3-17

3-10

Toner and Concentrate Bottles Installed

DO NOT ADD EXCESSIVE CONCENTRATE. If this is done, a dark background will appear, and the quality of the

record will be poor. In this event, the toner pre-mix will have to be diluted with clear dispersant.
Under normal operating conditions, the two-gallon toner pre-mix and eight-ounce toner concentrate is sufficient for
five to ten thousand feet of paper. Replace these bottles when the 10w level mark, identified on the toner pre-mix

bottle, is reached. NEVER ADD OLD TONER TO A NEW BOTTLE. The replacement reservoir (toner bottle) is a
positive design feature of the toning system, since any residue collected in the bottle should be discarded
periodically.
3.2

OPERATOR CONTROLS AND INDICATORS

Table 3-1 lists the functions of the LVOl controls and indicators.

Table 3-1
LVOI Controls and Indicators

Nomenclature

ON/OFF

Function

Applies ac power to the LVOl. When power is applied, the
switch is illuminated and remains depressed. Depressing the
switch a second time removes power from the unit.

PAPER ADVANCE

Depressing this switch causes paper to advance provided no
data remains in the LVOl data buffer. The switch remains

inoperative until the data is printed. Printing may be
accomplished under computer control or by depressing the
FORM FEED switch located just below the PAPER
ADVANCE switch. Paper movement will continue until the
switch is released.
FORM FEED

the printer to enter a print cycle and
in the data buffer. Upon
remaining
print
of
the
of
line, the paper is advanced to
completion
printing
the top of the next page when using fanfold paper and the
ROLL/FAN FOLD switch is in the FAN FOLD position, or
for a distance of 2-1/2 inches when this switch is in the
ROLL position.

This switch

LOW PAPER

This

causes

data

any

indicator is

red

color

and, when illuminated,

condition in the printer. The
LVOl will not accept data when this condition exists. An

indicates

out-of-paper

additional supply of paper should be loaded.

CONTRAST

The contrast adjustment is located inside the front panel of

ADJUSTMENT

the LVOl and is labeled DARK. Its purpose is to allow the

operator

compensate for variations in contrast due to

humidity changes in the atmosphere. It should be turned as
far clockwise as necessary to permit high contrast writing
without excessive background writing.

3-11

Table 3-1 (Cont)
LV01 Controls and Indicators
Nomenclature

Function

ROLL/FAN FOLD

This switch is located on the frame behind the front door.
When this switch is in the ROLL position, the top-of-form

detection circuit is disabled. The paper is advanced 2-1/2
inches for a FF and 8 inches for an EOT. When in the FAN

FOLD position, the commands are executed as described in

Paragraph 3.3. Should this switch be placed in the FAN
FOLD position when using roll paper, the top-of-form
circuitry will be disabled following the first \FF or EOT
command. These commands will then be treated as 3 LF

command when in print mode, or as a Line Terminate in
the plot mode.

CAUTION
Should any of the manual controls be depressed while the
LVOl is in operation, printing will be interrupted to perform
the manual function indicated.

LVOl PRINTER ASCII CHARACTER SET

3.3

Table 3-2 lists the ASCII codes recognized by the LVOI line printer. The complete 96-character set (95 characters

and a space) is available for use.

Table 3-2
LV01 ASCII Codes
Bit No.

’

(
)

g
h

;

[

J
k

(

]

}

)

#
$

EOT

3-12

-—

3.4

FORMAT CONTROL CODES

The format control characters used in the print mode of operation are LF (Line

Feed), FF (Form Feed), CR
(Carriage Return), and EOT (End-of-Transmission). Table 3-3 lists each control character and defines the action
taken by the printer upon receipt of that code. The explanation assumes fanfold paper is being used and the
ROLL/FAN FOLD switch is in the FAN FOLD position. If the switch is in the ROLL position, the action taken is as
described in Table 3-1.

Table 33
Format Control Codes

Mnemonic

Octal Code

012

Function

Paper is advanced one line and printing occurs except
under the following conditions: (1) LP is the first
character received following printing on a full buffer;
(2) LF is received as the first character following a CR
which caused printing and paper advance of one line;
(3) LP is received as the first character following a CR
which was immediately preceded by printing on a full
buffer. The Demand (or Ready) line will go false upon
receipt of the LF code and remain false until the
printing operation has been completed. The column
control will be returned to the left margin and the line
buffer will be cleared.

015

Paper is advanced one line only if a minimum of one
character is loaded into the buffer. The column control
will be returned to the left margin and the line buffer
will be cleared. If this command is received following the

printing on a full buffer, it is ignored and no action is
taken by the printer. Subsequent CR commands will be
ignored by the printer and cause no paper advance or
printing unless a minimum of one character has been
loaded into the buffer. The Demand (or Ready) line will
go false upon receipt of the CR code and remain false
until the printing operation is completed.

EOT

004

Data contained in the data buffer will be printed. The
paper will be advanced 8 inches, the toner pump will be
disabled, and the paper will continue to advance to the
next

top-of-form sensor. The column control will be

returned to the left margin and the line buffer will be

cleared. The Demand (or Ready) line will go false until
the EOT operation is completed.
FF

014

Data contained in the data buffer will be printed. The

paper will be advanced to the next top-or-form sensor. If
this distance is greater than 8 inches, the toner pump

will shut down and paper movement to the top-of-form
sensor

will continue. The Demand (or Ready) line will

go false until the FF operation is completed.

The LVOl

operation, when used as a printer, is very similar to a conventional impact printer in terms of data
transfer, programming, and format control. An exception to this is in the handling of the CR function. In a line
printer, the CR function prints the line but does not advance the paper. This is not possible with the LVOl. Printing
can only occur as the paper is
being advanced in the electrostatic printer. In most cases, this should not present a
problem. However, the user should be aware that this difference exists. The control codes are handled in a manner
that prevents multiple line spacing when using standard printer output routines. The following examples show the
variety of line terminating sequences available that will not produce multiple line spacing.

Sequence

Results

1. Transmit X number of characters

Characters loaded into the buffer.

2. Transmit CR code

The line is printed and paper is advanced by one line.

1. Transmit X number of charaCters

Characters loaded into the buffer.

2. Transmit CR code

The line is printed and paper is advanced by one line.

3. Transmit LF code

LF code is ignored.

1. Transmit X number of characters

Characters loaded into the buffer.

2. Transmit LF code

The line is printed and paper is advanced by one line.

3. Transmit CR code

CR code

is ignored.

Although the LF and CR codes produce the same results when data is to be printed, it is recommended that “driver’
routines for the LVOl use the conventional line terminating sequence of CR followed by an LP code. This enables
the same routine to be shared with other printer devices requiring both codes. Specialized software, usable on only
one device, is thus avoided.
3.5

PROGRAMMING CONSIDERATIONS

Points to consider for desirable programming techniques include efficiency, speed, and print quality. Programming

only affect one of the factors related to print quality. It can vary the time from application of the charge to
application of the toning liquid by controlling the data transfer rate. The important consideration is to maintain a
relatively constant data transfer rate so that toning time for each line remains constant. This will eliminate contrast
variations in the printed information. It is worth noting that data which is not toned within several minutes after
can

transmission may be lost.

To obtain maximum efficiency and printing speed, data should be transmitted as quickly as possible to the LVOl It
.

can

accept one byte of information per microsecond when loading the data buffer. In many cases, this is faster than

the processor can transfer. When printing is to occur, it can take 120 ms for a line of text or 8.3 ms for a plot line.

This is quite long and the processor should not be held in a loop waiting for completion of the print operation. An

interrupt driven handler should be set up and the processor allowed to continue its normal program tasks. If no
printing has occurred within the last 1.5 seconds, an additional 1.5 second delay will be encountered when the first
line is to be printed. This allows the toner sufficient time to rise in the toning channel before paper movement
begins. Again, an interrupt routine would save valuable processor time.
3.6

PDP-ll PROGRAMMING

All software control of the LVll Controller is performed by means of two device registers (control/status and data).

These device registers have been assigned Unibus addresses and can be read or loaded by any PDP-ll instruction that
refers to their address.

3-14

3.6.1

Control and Status Register (LVCS)

Address:

777514

14¢

$08

04‘—————>OO
CP-O415

Figure 3-18

Control and Status Register Bit Assignments

Figure 3-18 shows the bit assignments for the LVCS. Loading “read only” bits has no affect on the bit position.
Loading unused bits results in data being lost in the corresponding bit position. “Write only” bits will be read as
logic Os. INIT refers to the initialization signal generated by the processor when powering up, when powering down,
for a RESET instruction, or by depressing START on the processor console.
Bit

Meaning and Operation

Name

ERROR

Asserted

(1) whenever an error condition exists in the printer. Error

conditions are:
1. No paper
2. Power off

3. No printer connected to LVll
This bit is reset only by manual correction of the error condition. Read

only.
14—08

Unused

READY

Asserted

(1) whenever the printer is ready

transfer. Indicates that the

receive the next data

previous function is either

been started and continued to

complete or has

point where the printer can accept the

next data. This bit is set only by the LVOl. Read only.

INTERRUPT ENABLE

Unused

Set or cleared under program control. Cleared by INIT signal from Unibus.
When set, an interrupt is requested when READY or ERROR becomes a 1.

BUFFER CLEAR

Set under program control. Clears the buffer indicated
Control bit. Write only.

REMOTE END

Set under program control. Forces the LVOl to perform an ASCII EOT
when in plot mode. Write only.

OF TRANSMISSION

3-15

by the Mode

Bit

Name

Meaning and Operation

REMOTE FORM FEED

Set under program control. Forces the LV01 to
when in the plot mode. Write only.

LINE TERMINATE

Set under program control. Forces the LV01 to print the
prior to receipt of a complete scan line. Write only.

MODE CONTROL

May be set or cleared under program control. Cleared by INIT from the

perform an ASCII FF

graphics line

Unibus. When cleared the LVOl interprets data as 7-bit ASCII (1968). The

complete 96-character set will be printed. It will respond to the control
characters in the manner listed in Table 3-3. When asserted ( 1), the LV01
interprets data as a bit map of computer graphics. A complete scan or
assertion of the Line Terminate status bit is required to print the line.
Data Buffer Register (LVDB) (Figure 3-19)

3.6.2

Address:

777516

OO
CP—O414

Figure 3-19

Data Buffer Register

Meaning and Operation

Bit

Name

15—08

Unused

The data is lost in these bits if they are loaded.

07—00

DATA

Eight-bit data buffer. Bits 06—00 contain the ASCII characters. Bit 07 is used
only in the plot mode.

3.6.3

Interrupts

A program interrupt sequence is initiated whenever the Error or Ready bit is set in the LVCS and the Interrupt
Enable bit is set. An interrupt request is generated when the interrupt is granted. It uses the vector block at location

200. The normal priority level is BR4; however, this level may be changed by using a different priority plug in the
LVll

controller module. Detailed

descriptions of PDP-ll

Unibus

interrupt

sequences

are

contained in the

Peripherals and Interfacing Handbook.

3.7

3.7.1

PDP-8/PDP-12 PROGRAMMING
IOT Instructions

The IOT programming instructions and commands that command the LV01 are presented in Table 3-4.

3-16

Table 3-4
IOT Programming Instructions

Octal Code

Mnemonic

6657

LPB

6661

LSF

Function

Load the contents of AC bits 06 through 11 into the status register.

Skip on LVOl Done flag. The state of the Done flag is sensed. If it is
1, the content of the PC is incremented by one so that the next
sequential instruction is skipped.

6662

LCF

Clear Character flag. The LVOl flag is cleared to a logic 0.

6663

LSR

Skip on error. The state of the Ready line is sensed and, if it is a 0,
indicating an error exists, the content of the PC is incremented by
that the next sequential instruction is skipped. Errors
one
so
detected with this instruction are Paper Out, Power Off, or the
printer is physically disconnected from the LV8.

6664

LLC

Load printer buffer. Data is transferred to the LV01 buffer from the
contents of AC bits 04 through 11. All eight bits are used during a

plot operation while only seven are used in the print mode.
6665

LSP

Enable program interrupt. Sets the Interrupt Enable flip-flop.

6666

LPC

Clear the printer Done flag and load printer buffer. Micro-instruction
combination of LCF and LLC.

6667

LCP

Disable program interrupt. Clears the

Program Interrupt Enable

flip-flop.

3.7.2

Status Register

The status register bit assignments are described in Table 3-5.

Table 3-5
Status Register Bit Assignments
Bit

Name

Description

MODE CONTROL

Setting this bit forces the LVOl to enter the plot mode of operation.
Clearing it indicates a print mode. Initialized to the print mode.

MODE ENABLE

Setting this bit enables the LPB IOT to load status bit 11 from the
content of AC bit 11. A O prevents the changing of bit 11.

REMOTE FORM FEED

Setting this bit forces the LVOl to perform an ASCII FF when in the
plot mode.

3-17

Table 3-5 (Cont)
Status Register Bit Assignments
Name

Bit

Description

REMOTE END

Setting this bit forces the LVOl to perform an ASCII EOT function

OF TRANSMISSION

when in the plot mode.

BUFFER CLEAR

Setting this bit forces the LVOl to clear all data contained in the buffer
regardless of the status of the Mode Control bit. Printing returns to the
left margin and no paper movement will occur.

LINE TERMINATE

This bit is used only in the plot mode. If the Mode Control bit is a 0,

this function will be disabled. It will also be disabled

during the

instruction which writes a 1 into the Mode Control bit.

3.7.3

Programming Considerations

Programming of the LV8 is similar to the LP08 with the one exception of the LPB (6657) IOT instruction. The
addition of this instruction adds the graphic features of the electrostatic printer. The user is allowed access to ASCII,
FF and EOT functions for convenience in formatting graphical information on fanfold paper. In addition, the
graphic scan line can be terminated at any time without the necessity of transmitting unnecessary data to the
printer.
When used in the print mode, the LVOl will respond to the control codes listed in Table 3-3. With the exception of

the CR and EOT codes, the response is identical to the LPO8 line printer. When data is in the buffer, the CR code
an LF (Line Feed) function in the LVOl. This is due to the electrostatic method of writing. It is
impossible to write the line of characters without moving the paper.

will also force

The EOT code is different because it is not available for use on the LP08. Its function is to ensure that the last
information printed will reach the viewing area so the operator can examine and/or remove the printed copy. In
exact terms, it will advance the paper 8 inches and then to the next top of form indicator.

Double spacing between lines of characters will not occur due to the manner in which the format control codes are
handled by the LVOl. The first CR, LP, or CR/LF combination received following the printing due to a full buffer
condition is ignored by the printer.
a Done flag which aids the program transfer of data to the printer. When raised, the
Done flag indicates that the printer is ready to receive another byte of data. This flag is raised in less than 1 us after a

The LV8 interface contains

load data command for all data except the last transfer of the line, a CR, LF, FF, or EOT code. At these discrete

times, printing will occur and the time necessary for the flag to return will vary with the function transmitted.
If no printing has occurred within the last 1.5 seconds, the flag is delayed an additional 1.5 seconds. This additional
time is necessary to ensure that the toner pump starts up and that the toner has sufficient time to reach the paper.

changing between plot and print modes. Once the print cycle has been initiated under
either mode, it will continue under that mode even though the Mode Control line is changed. It is not necessary,
therefore, to sense the Ready line prior to initiating the mode change.

No restrictions exist when

3-18

CHAPTER 4

PRINCIPLES OF OPERATION

This chapter presents a general operating discussion Of the LVOl Printer/Plotter and detailed descriptions of the LV8
and LV11 Interface Controllers. (The LV12 operates identically to the LV8.) Complete detailed technical data for
the LVOl is contained in the Versatec, Inc. maintenance manual supplied with each unit.

Voltage levels in the LVOl and respective interface are TTL compatible. A 0 state is defined as 0V to +0.8V. A 1
state is defined as +3.0V tO +5.0V. A high is also defined as a logic 1, while a low is defined as a logic 0.
4.1
4.1.1

LVOl PRINTER/PLOTTER

General Operation

Figure 4-1 shows all Of the interface signals between the LVOl and the interface controller. The print mode of
operation is entered whenever the Mode Control line is asserted to a logic high or 1. Conversely, the LVOl operates
in the plot mode when the Mode Control line is 0. Following system turn-on and initialization, the interface receives
the low condition Of the Ready line, which indicates that the LVOl is capable of receiving data. The processor
eventually responds with data that is then loaded into the LVOl Via lines DATA 1—8, by means of the Data Strobe
pulse. As determined by the state Of the Mode Control line, the data is either interpreted as printing characters or
plot information.
,

DATA

1-8

MASTER RESET
DATA STROBE

DATA

LVO1

‘

MODE CONTROL
LINE TERMINATE
POP-8

BUFFER CLEAR

LV8,

PDP-12,0R

LV12,0R

pop-”
PROCESSOR

LVH
INTERFACE

REMOTE EOT

PRINT/

PLOT
BUFFER

REMOTE FF
INPUT MODE

STATUS,
CONTROL

DEMAND(READY)
ON

LINE

LOW

PAPER

CP-0412

Figure 4-1

LVOl Interface Signals

4-1

The Ready line then goes false (high) following the leading edge of the Strobe pulse and returns true (low) when the
LVOl is ready for more data. This procedure is repeated until the LVOl buffer is full, at which time its contents are

printed. An unfilled buffer, however, may be printed upon the receipt of one of the format control codes listed in
Chapter 3.
4.1.2

Electrostatic Writing Technique

In the electrostatic writing process, the paper passes in front of a writing head, which is a laminated
assembly
consisting of conducting wires in a linear array permanently affixed in a rugged fiberglass structure. The surface of
the paper is coated with a nonconducting dielectric material that holds electrical charges received when

voltages are
applied to the individual writing points. This potential varies between two levels, writing and nonwriting, and can be
related directly to the binary data output of the computer.
The writing potential deposits a minute electrical charge on the insulating surface of the paper. A negligible electric
current is involved so there is no problem of arcing or

burning. Since the electrical signals are placed directly on the
truely electrostatic writing technique. There is no intermediate step or mechanism, such as
mechanical parts or light sources, as is the case in most office copying devices. There are no moving parts associated
with the writing process, only a paper transporting mechanism is used.
paper, the LVOl

uses a

In order to write in this manner, since the

writing points do not move, they must be made to write in a
predetermined manner. The nonmoving writing point is only capable of writing a small dot on the paper; many
hundreds of these are used to write across a standard size sheet of paper. Controlled information, therefore, must be

provided in order to create a recognizable image.
In the electrostatic method, images on the paper, formed from the small dot charges, become visible when the paper

surface passes over a toner applicator channel and is exposed to a liquid toner. This toner contains suspended
particles of a colored material which contrast to the paper. The particles are of opposite charge to the charge dot on
the paper, and are attracted and fixed permanently to the charged areas, making them visible. The trailing edge of
the toner channel wipes the excess liquid from the paper and air is directed over the paper’s surface for drying. No
further fixing or special handling is necessary and the record is available for immediate use. The finished copy
exhibits excellent archival qualities and is reproducible on office copying machines.

4.2

LVll DETAILED DESCRIPTION

The following paragraphs provide a logic level description of the M7258 Interface Module functional units (Figure

Address Selector, Interrupt Control, Data Register, and Printer Control. The LV11 logic is shown on
engineering drawing D-CS-M7258-O-l (Printer Interface), sheets 1 through 3. These sheets are, respectively, the Data

4-2):

Register (sheet P-2), the Printer Control (sheet P-3), and the Address Selection and Interrupt Control (sheet P-4).
4.2.1

Address Selection Logic

The address selection logic (sheet P-4) decodes the address information from the Unibus and provides three gating

signals (only two are used) and four select line signals (two are used) to control the LVll controller registers.
Jumpers are arranged so that the module responds only to standard device register addresses 777514 through
777517 (jumpers in A4, A5, A7, 114). Although these addresses have been selected by DEC as the standard address
assignments for the LVll Controller, the customer can change the jumpers to any address desired. However, any
MAINDEC program that references the LVll Controller standard address assignments must be modified to reflect
the new assignments.

{\ II

LV11 (M7258)

j BUS BR SIGNALS
'

I
IE,INTA H

BUS u<oz=oe>

"égfififi‘éil

PRINTER
CONTROL

lug/6350)

LOGIC

U
N
|

a
u
S

BUS

1 BUS o<o7=oo>

DATA
REGISTER
LOGIC

(LVDB)

BUSC<1IO>
BUS MSYN

ADDRESS
SELECTOR
LOGIC

Figure 4-2

ERRORS

lSTROBE
I

DOG,DO7,015(LVCS)

J BUS A <17:oo>

.l DEMAND,

LVO1
pRlNTER/
PLOTTER

4 DATA

I
I

LVll Functional Block Diagram

The first five octal digits of the address (77751x) indicate that the LVll has been selected as the device to be used.
The final octal digit, consisting of A02, A01, and A00, determines which register has been selected and whether a
word or byte operation is to be performed. The two mode control lines, C00 and C01, determine whether the
selected register is to perform an input or output function. The three jumpers, J12, J 13, and J14, determine the
responses to the last octal digit of the address as follows:

J12
J14
J13

4.2.1.1

—

——

a response

only from 0 and 2 and no response (no SSYN) from 4 and 6.

a response

only from 4 and 6 and no response (no SSYN) from 0 and 2 (standard).

a response

from 0, 2, 4, and 6.

Address Inputs

—

A simplified block diagram of the address selection logic is shown in Figure 4-3. Note that

IN and OUT are always used with respect to the master (controlling) device. Thus, when the line printer controller is

used, an OUT transfer is a transfer of data out of the master (the processor) and into the device. Likewise, an IN
transfer is the operation of the controller furnishing data to the processor.
The address selection logic input signals consist of 18 address lines, A (17:00); 2 bus control lines, C (1:0); and a
master synchronization, MSYN, line. The address selection logic decodes the incoming address as described below.

This address format is shown in Figure 44. Note that all input gates are standard bus receivers.
a.

Line A00 is used for byte control.

Lines A01 and A02 are decoded to select one of the two control registers (status or data buffer).

Decoding of lines A (12:03) is determined by jumpers. When a given line contains a jumper, the address
logic searches for a 0 on that line. If there is no jumper, the logic searches for a 1.

(1.

Address lines A (17:13) must be all ls. This specifies an address within the top 8K byte address bounds
for device registers.

EXT CAP
EB1

EEI

BUS MSYN L

BUS
CONTROL

BUS A17 L

5‘52

ED?

3
E

EK2

a M2

EP._1._°___0 A” 0—...

ER1

EP2

—-——d—-—o A10 0——

SELECT O

NOT
USED

A
D

EK1

EU,

SELECT 2

318057!)

P—4 STATUS
SELECT H

SELECT
L'NES

SIGNALS

ERZ
9-4 BUFFER
SELECT H

—E—U2—OI——o’\o——5§
A4

W
BUS A03 L-————q———o A3 9——
.

ET2

——0 A6 0——

EV1

532

0——
———-——-<:EN2 ——OA9
5
-——0 AB 0——

BUS SSYN L

551

JUMPER FOR
A O
0 J12 o

a 413 o
BUS A02 L

BUS AOI L
BUS AOO L
BUS C1 L

BUS CO L

E“

J“

5’“

EHZ

3:?

57.

CATING

Ed;

CONTROL

P'4 OUT “'5“

GATING
5.5.NAL5

9-4 1N H

,gwléfl

EL2
0—— REG SEL

ADDRESS SELECTION LOGIC

”1t

9-4 OUT Low H

EXIGND

(MUST BE GROUNDED)
NOTE:

*Not used in this system

+5V EAz
GND EC2,ET1, EA‘l

CP-Ole

Figure 4-3 Address Selection Logic, Simplified Diagram

1.1

SELECTED

‘

BY JUMPERS

MUST BE ALL 1's

DECODED FOR 10F 4 REGISTERS
BYTE CONTROL

‘wL

”-0029

Figure 4-4

Controller Select Address Format

Outputs The address selection logic output signals permit selection of two 16-bit registers and provide
signals that are used for gating information into and out of the master device. All of the output signals are
listed in Table 4-2. Note, however, that only two gating signals are listed (IN and OUT). Actually, there are two OUT
signals, OUT LOW and OUT HIGH, but OUT HIGH is not used by the LVll Controller. The logic diagram (drawing
P-4) shows two additional select line signals, SELECT 0 and SELECT 2. Neither of these signals is used by the
4.2.1.2

-—

three

controller.
Tables 4-1 and 4-2 indicate the input signals that select the control output line states.

Table 4—1
Select Lines

Select Lines True (+3V)

Input Lines A (02:01)
00

not used

in LPll

(Status)
(Data)

NOTES
1. Lines A (17:13) must be all Is (0V on Unibus).
2. Lines A (12:03) are selected by jumpers.

Table 4-2

Gating Control Signals
Mode Control C (1:0)

Byte Control A00

DATI

DATIP

OUT LOW

DATO

Gating Control Signals True (+ 3V)

Bus Sequence

OUT HIGH
10

OUT LOW

DATO

OUT HIGH
11

OUT LOW

DATOB

OUT HIGH

DATOB

NOTES

Gating control signals may become true although select lines are not.

2. OUT HIGH not used in LV11 Controller.

When EXT CAP is grounded, it inhibits the
selection logic.

acknowledgment signal (SSYN) normally generated by the address

4-5

Interrupt Control

4.2.2

interrupt control logic (drawing P-4) permits the LV11 Controller to gain control of the bus (become bus
master) and perform an interrupt operation. The jumpers on this logic are arranged so that the logic has a normal
vector address of 200 Gumper in bit position 7). Although this is the recommended vector address, the user may
change the jumpers to correspond to any address desired, but MAINDEC programs and other software referencing
the standard vector address assignment of 200 must be changed to reflect the new assignments.
The

The

interrupt control logic consists of a dual-input request and grant acknowledge circuit for establishing bus

control. The interrupt occurs at vector address 200. The B input portion of the logic is disabled because neither an
INT B

INT ENB B can be generated by the LV11 Controller (these two input lines are grounded as shown on

drawing P-3).
Before the interrupt control logic can generate an interrupt request, two input signals must be high: INT A and INT
ENB A. The logic that generates these two signals is shown on drawing P-3. When a 1 is loaded into bit 06 of the
status register, it sets the INT ENB flip-flop in the E14 IC to produce INT ENB A H. The data input to this flip-flop

is the 1 from BUS D06 and the clock input is the load signal P-4 (SEL 4 H and P-4 OUT LOW H).

The second signal that must be present to generate an interrupt is INT A H. The INT A H signal is produced by an
OR gate and an inverter that is qualified when either a DONE

or an

ERROR condition exists. The DONE and

ERROR conditions are described in Paragraphs 4.2.3 and 4.2.4.
The master control section of the interrupt logic (Figure 4-5) is used to gain control of the bus. When both the INT
A and INT ENB A requesting inputs are asserted, a bus request is made on the BR level corresponding to the level of

the priority plug. The standard level for the LV11 Controller is BR4, but this may be changed by the priority plug, if

desired. When the priority arbitration logic in the processor recognizes the request and issues a bus grant signal, the
master control circuit

acknowledges with a SACK signal. When the controller has fulfilled all requirements to

become bus master (BBSY false, SSYN false, BG false), the master control section asserts BBSY.

INT

INT ENB A

LP-2
LP—2

:11

————«

864 IN H
BUS

SSYN L

BUS NPR L

o—o—FK‘ BUS 008 L

mg”;— BUS 00-, L

FE”

:3)

F01

o—pffl— BUS 006 L
o——«L>—F-Fi—— BUS 005 L

w—pfli— BUS 004 L

o—p—Fii— BUS 003 L

o—o—FE—Z— BUS 002 L

MASTER
CONTROL

c—m

“1

-—E-A—1-—BG4 OUT H
o—F—PL— BUS 8R4 L
0-53— BUS SACK L

050—1—- BUS BBSY L
Dim—— BUS INTR L
LP—z
LP-2

INT 8 H

INT ENB B H

33——

NOTES:

Input 8 not used (INT 8 and INT ENB B
request made on level 4.
Interrupt vector is 200.

Jumpers

are

grounded)

in LV11

controller.

Bus

are:

jumpers for

1.
cp-omr

Figure 4-5 Interrupt Control Logic, Simplified Block Diagram
4-6

Once the controller has gained bus control by means of a BR request, an interrupt is generated. The interrupt vector

address is selected by jumpers on the logic as shown on Figure 4-5. Because the vector is a 2-word (4-byte) block, it
is not necessary to assert the state of bits 00 and 01. The seven selectable lines determine the vector address.

The BC IN signal is allowed to pass through the logic to BUS BG OUT when the controller is not issuing a request.
To request bus use, the AND condition of INT A and INT ENB A must be satisfied. These levels must be true until

interrupt service routine clears INT or INT ENB. Once bus control has been attained, it is released when the
processor responds with BUS SSYN after it has strobed in the interrupt vector. After releasing bus control, the logic
inhibits further bus requests even if INT A and INT ENB A remain asserted. In order to make another bus request,
INT A or INT ENB A must be dropped and then reasserted to cause the logic to reassert the request line. This
prevents multiple interrupts when the master control is used to generate interrupts.
the

4.2.3

Data Register Logic

The data register logic (sheet P-2) consists of an 8-bit data buffer, the decoding circuitry necessary to detect the LF

and FF commands when in the print mode, and the line drivers for the eight data lines and the prime signal. The

eight bits of data from BUS D00 L through BUS D07 L are applied to the data inputs of the two 74175 D-type
flip-flop ICs and clocked into the register by the LD BUF H signal. The LD BUF H signal is asserted when both P-4
BUFFER SELECT H and P4 OUT LOW H are true. The P4 BUFFER SELECT H signal indicates that the LV11
data register address has been decoded by the address decoding logic. The P4 OUT LOW H signal indicates that a
DATO or DATOB bus operation is in progress. Thus, the data register is loaded by addressing the LVDB and
initiating a DATO or DATOB transfer.
The output of the data buffer is monitored by the LF and FF decoding circuits. If either code (0128
detected, P-2 LF/FF L is asserted when P-3 GATE H is generated by the printer control logic.

0148) is

The outputs of the data buffer are also applied to the 7437 line drivers that drive the cable lines going to the LV01.
The 1K resistors help terminate the interface cable to minimize reflections and noise.
The BUS INIT L signal is bufferred and inverted by E20. It is then applied as a high signal to the 7437 driver where
it undergoes a second inversion and is transmitted to the LV01 as a low true signal called P PRIME L.

The data register logic also contains the interrupt priority plug (E26). The LV11 is normally configured with a BR4

interrupt level priority plug.
4.2.4

Printer Control Logic

The printer control logic (sheet P-3) monitors line printer control lines, provides the interrupt control logic with

interrupt request information, contains the LV11 Control and Status Register (LVCS), and provides a strobe signal
to load data from the LVDB into the LV01 buffer. In addition, the printer control logic contains circuitry to force
the transmission of a CR code to the LV01 when the P-2 LF/FF signal is asserted.
During data transfers, other than LF and FF, the trailing edge of P-2 LD BUF H (asserted by the data register logic)
fires a 74123 monostable multivibrator (one-shot) which generates a 500 ns pulse. This time interval is used to allow
the data lines to settle before strobing the information into the LV01. The trailing edge of this pulse (pin 13 of E25)
fires a second one-shot whose output is applied to a line driver through jumper J9. The output of the 7437 driver is
used as the strobe signal for the LV01. Strobe is a positive TTL level pulse with a duration of approximately 500 ns.
Refer to Figure 4-6 for character transfer timing.
P-2 LD BUF H also clears the Done flip-flop (Done is initially set by BUS INIT L) and fires another 74123 one-shot

(E23) producing P-3 GATE H (pin 13 of E23). P-3 GATE H is an input to the data register logic and generates P-2
LF/FF L, if an LP or FF code is contained in the LVDB. With P-2 LF/FF L unasserted, the Hold flip-flop remains
clear and P DEMAND will set the DONE bit when the character has been accepted by the LV01. The DONE bit may
then be read under program control and a new DATO transfer to the LVDB initiated. If the interrupt enable (IE) bit
in the LVCS is set, an interrupt request is generated. The PDP-ll can then service the Done interrupt by sending
another character to the LVDB.
4-7

TIME DEPENDS ON BUS TIMING

P-Z LD BUF H

500ns

E25 MN 1

STROBE

<: :*/500ns

APPROX

DONE(1)H

2ps

ZOOns
P-3 GATEII

/
P DEMAND H

CP~O4|6

Figure 4-6

LV11 Character Transfer, Timing Diagram

If, when P-3 GATE H is asserted, P-2 LF/ FF is generated by the data register logic indicating that an LF or FF is to
be output to the LV01, the Hold flip-flop is direct set (Figure 4—7). This forces the lower three data bits (P DATA 1
through P DATA 3) to an octaI 05, converting the LF (012) or FF (014) code to a CR (015) command at the LV11
output lines. The reset side of the Hold flip-flop is connected to the data input of the Done flip-flop. Therefore,
when the converted CR is loaded into the LV01 by Strobe, P DEMAND does not set Done, but clears the Hold
flip-flop. The clearing of the Hold flip-flop fires a 200 ns one-shot (pin 13 of E25). The sequence then proceeds the
same as in a normal

character transfer. The 74123 one-shot (pin 4 of E24) is fired to generate Strobe which loads the

LP or FF character, still in the LVDB, into the LV01 buffer. With Hold now clear, P DEMAND will set the Done

flip-flop when the LF or FF operation has been completed.
The printer control logic also generates P-3 INT A H when an error condition exists in the LV01. If P HDWR H or P

PAPER H is asserted from the LV01, ERROR H is generated for at least 400 ms by a 74123 one-shot (E23). (Signals
P FAULT L and P SELECT L are not used by the LV01.) ERROR H produces P-3 INT A H and inhibits Done from

being read by the program. Therefore, ERROR H or DONE ( 1) H generates P-3 INT A H which initiates an interrupt
request to the interrupt control logic, if the IE bit is set in the LVCS. Signals P-4 IN H and P4 STATUS SELECT H
drive bits 06 (IE), 07 (Done), and 15 (Error) onto the respective Unibus D lines during a DATI operation to the
LVCS.

The functions of BUF CLR, REM EOT, REM FF, and LINE TERM are produced by the 74174 IC (E14) and the

74123 one-shot (E25). These signals are initiated under program control and are controlled by the Unibus D lines
when the LVCS register is addressed. This discussion is for BUF CLR; the other functions are generated in-a similar
When a DATO to the LVCS register is performed, P-4 OUT LOW H and P4 STATUS SELECT 4 H are
generated by the address selection logic. These two signals are ANDed to form the clock signal for the 74174 control
register (E14). The leading edge of this clock pulse loads P-2 BD04 H (buffer clear) into the register. The trailing
edge of the clock pulse fires the 74123 one-shot (E25) producing a 500 ns pulse at its output. This pulse is gated by
the output of the control register (pin 12 of E14) and a 500 ns negative pulse is transmitted to the BUF CLR line.
The leading edge of the pulse also clears the Done flag, prohibiting further data transfers until the BUF CLR
operation has been completed.

manner.

4-8

“A H“
P-Z LD BUF H
A

«h

J. ~4r~

J
D

‘1’

J
j

‘1“

-L “f
m.

P'3 GATE H

/200ns

[7
DONE (1) H

P2 LF-FF L

/K
j

-L T

HOLD (1) L
7

525-13

"-500”

*—

STROBE

500ns

STROBES CR

<
LL

4)
P DEMAND

E24-5
1
fl

500ns

J
D

4 I

STROBES LF OR FF
seem

I
_J

H
CP-O4l7

Figure 4-7

FF and LF Timing Diagrams

The remaining bit in the control register is the Mode bit. The state of this bit determines whether the LVOl will

interpret the data presented to it as ASCII characters or as graphical information. The Mode bit is cleared by BUS
INIT L and places the LVOl in the print mode following the application of power or a program initialize. Setting
this bit will force the LVOl to enter the plot mode of operation and accept the data presented to it as unweighted

binary data in the form of a bit map of the desired graphical information. The Ready flag is not cleared when the
mode of operation is changed.
The LVOl

timing associated with REM EOT, REM FF, BUF CLR, and P PRIME L is shown in Figure 4-8. The

timing for LINE TERM is shown in Figure 4-9.
4.3

LV8 DETAILED DESCRIPTION

The LV8 Printer/Plotter System is contained on a quad 8E card whose pins are defined by the 8E OMNIBUS. The

interface is designated the M8302 and the logic is shown on drawing D-CS-M8302-0-1, sheets 1 and 2. The logic is
divided into four functional units (Figure 4-10): IOT Decode, Interrupt and Skip Control, Printer Control, and Data

Register. The following paragraphs provide a logic level explanation of these functional units. The level of discussion
assumes that the reader is familiar with the principles of operation covered in the PDP-8 reference manuals listed in
Paragraph 1.5.

4-9

100 ns

MAX—.l

~—

—~

50ns MIN
500% MAX

l»— 25ps MAX FOR BUFFER CLEAR

—%

_________

DEMAND

PRIME '-

r__-__fl

a
7 SEc

300 ns MIN
Zps MAX

-'|300ns M|N|‘—

MAX FOR

7’“ WORST CASE FF

‘—”

‘

F—

REM EOT
REM FF
BUF CLR
12 SEc MAX FOR
WORST CASE
EOT

CP-O420

Figure 4-8

128th
DATA

Remote Control Timing Diagram

BYTE

W//

STROBE

P DEMAND

—.|

h— 300ns MIN 2ps MAX

LINE TERM

F 8.3 MS

MAX

___..

~————8.3 Ms MAX

__..

CP-O4l9

Figure 4-9 Plot Mode Timing Diagram

4.3.1

IOT Decoding

Control Of the LV8 system is accomplished by using programmed input/output transfer instructions (IOTs). Seven
IOT codes are used in the LV8 and an Operational description of each can be found in Paragraph 3.7.

IOT codes 6650 through 6667 are decoded in the IOT decoding logic.

IOT’s 6660 through 6667 are fixed by design and their function is exactly the same as the standard LP08 or LE8
line printers. No modifications to present software is necessary to output tO the LV8 as a line printer.
An additional IOT has been added to implement the graphic features of the LVOl and to provide the functions of
LINE TERM, REM FF, and REM EOT in the graphic or plot mode of operation. The IOT used for this function is

selectable using jumpers, but the M8302 is supplied with IOT 6657 as the standard code. Any software supplied by
DEC will use this code as the LPB instruction.

4-10

O
0

l
”003‘"

I/O PAUSE

DATA 04-11

M
N
'
B

6
SKIP

BUS

LV8 (M8320)

I
|
I
|
I
|
r

[
INTERRUPT

BUS

IOT 6662 6657
IOT
DECODE

IOT 6664 6666

PRINTER
CONTROL

STATUS(3 LINES)

REMOTE FUNCTIONS (4 LINES)

STROBE
MASTER CLEAR

l
I

LV‘IQE1R/

IOT

22213}
6665}
6667

SKIP
MODE CONTROL

INTERRUPT

INTERRUPT
AND SKIP
CONTROL

BUFFERED
MD 04-11

IOT 6664

PRIN
PLOTTER

l
I

I
DGA;$ER DATA(8 LINES)

OR 6666

I
f

CP-O42I

Figure 4-10 LV8 Functional Block Diagram

Decoding of these codes is accomplished by examining the state of MDO3 through MDll and I/O PAUSE. I/O
PAUSE, when true, indicates that an IOT has been decoded by the CPU (octal code 6XXX). I/O PAUSE is used as
an enable input to the Device Selection logic (E9 and E17). Pin 3 of E9 will be high during an IOT for Device code
66. This signal is inverted by ES and used as an enable to the IOT generator (E6). The other inputs to E6 (MDO9,
MDIO, and MD11) define the specific IOT to be performed. The signal at pin 3 Of E9 is also inverted by E18 and
provides the INTERNAL I/O signal to the OMNIBUS.
Pin 3 of E17 will be high during an IOT instruction for device code 65 (standard). The IOT decoding proceeds in a
manner similar to that outlined for the 66 device code.

4.3.2

Printer Control

The function of the

printer control is to (a) initiate the transfer of data between the LV8 Data Register and the
provide operating mode information to determine print or plot modes
of operation, (C) initiate remote functions under program control, and ((1) process the LVOl status signals for use
by the interrupt and skip control.
LVOl by generating the STROBE signal, (b)

Data can be transmitted to the LVOl by loading the Accumulator Register (AC) in the CPU and performing a 6664
or

6666 IOT instruction. The decoded 6664 (pin 9 of E6) and 6666 (pin 4 of E6) are ORed by ES and NANDed

with TP3 by ES providing a negative 100 ns pulse at pin 8 of E5. This pulse is inverted by E15 and clocks the data

register. The pulse also fires a 74123 monostable multivibrator (one-shot) which produces a positive 500 ns pulse at
its output (pin 5 of E3). This time period is used to allow the data lines to settle before strobing the data into the

LVOl. The trailing edge of this pulse fires a second one-shot whose output is used as the strobe signel to the LVOl.
AC bit 11, called the mode bit, is used as the data input to the Print/Plot flip-flop. The clock input is controlled by
AC bit 10 and the LDB instruction. Therefore, AC bit 10 is used as an enable to the Print/Plot flip-flop. Whenever
AC 10 is true, AC 11 will be loaded into the Print/Plot control. The Print/Plot flip-flop is Cleared by the INIT signal
on

the OMNIBUS placing the LV8 in the print mode of Operation. Setting it places the system in the plot mode of

operation.

4-11

During the LDB instruction (6657), the state of AC bits 07,08, and O9 is sensed to determine if a BUF CLR, REM
EOT, or REM FF is to be performed. The LOAD STATUS L signal (pin 12 of E23) is gated by the Data Bus signals
and, if the Data line is true (low), fires a 74123 one-shot producing a 500 ns negative pulse on the corresponding
remote function line.

The RLTER function is

performed in a similar manner. However, the RLTER function is disabled during the

instruction which changes the Print/Plot flip-flop to plot mode (sets it). The RC time constant associated with R8

and C41 holds E7 reset until the leading edge of the LDB instruction has passed. This disables the RLTER one-shot

and prevents it from firing.
The set side of the Print/Plot flip-flop also gates the remote functions to the LVOl and prevents their use during

printing operations. LVOI timing associated with REM FF, REM EOT, BUF CLR, and P PRIME L is shown in
Figure 4-8. The timing for LINE TERM is shown in Figure 4-9.
The

printer control also monitors the status signals from the LVOl to the LV8 interface. The ON LINE L and

PAPER OUT L signals are inverted and ORed by E26 to form the error signal to the Interrupt and Flag control. The
READY L signal enters on pin X of the 40 pin Berg connector and is terminated by a resistor network that matches
the characteristic impedance of the interconnecting cable. It is inverted by E23 to provide a positive edge to set the

Flag flip-flop. The FLAG signal is then fed to the Interrupt and Skip control as a high signal.
Flag flip-flop can be cleared under program control by the LCF (6662) or LPC (6666) instruction. It is also
during an REM FF, REM EOT, BUF CLR, LINE TERM, or P PRIME L operation. The false-to-true
transition of the Ready line sets the flag when the function is complete.

The

cleared

4.3.3

Data Register

The data register consists of eight 7474 D-type flip-flops. The data inputs to the data register are the bufferred data
lines from the CPU. During an IOT instruction, these lines reflect the contents of the CPU (AC). The clock for the

during an LLC or LPC IOT instruction. Therefore, the contents of the AC are
transferred to the data register during the LLC or LPC instruction.

data register is generated by TP3

4.3.4

Interrupt and Skip Control

Two methods of data transfer, program transfer and program interrupt, may be used when programming the LV8.

Use of the first method, program transfer, involves the skip control section of the LV8 interface. The state of the
flag is sensed during execution of the LSF instruction producing a skip (PC+l->MA) if the flag is set. Another

instruction, LSR, is used to sense the state of the error signal produced in the printer control. Should an error exist,
a low level is

placed on the skip bus producing a program skip in the CPU.

interrupt control section of the LV8 interface. The
interrupt control consists of the Interrupt Enable flip-flop and two 8881 bus drivers. The LSP (6665) instruction
sets Interrupt Enable and an interrupt request is generated whenever an error condition exists or the Done flag is set.
It is the responsibility of the interrupt service routine to determine the cause of the interrupt and service it
accordingly. The LCP (6667) instruction disables the program interrupt control by clearing the Interrupt Enable

Use of the second method, program interrupt, involves the

flip-flop. Interrupt Enable is also cleared by INIT on the OMNIBUS.

4-12

CHAPTER 5

MAINTENANCE

LVOl Printer/Plotter maintenance is discussed in detail in the Versatec, Inc. maintenance manual supplied with each
unit. The only maintenance tasks concerning the LV11 and LV8 interface controllers are inspection and diagnostic

procedures.
5.1

INSPECTION

Inspection of the LV11 and LV8 is a Visual check to ensure that the module is configured properly and not
damaged.
1.

Check that the LV11 module (M7258) or LV8 module (M8302) is plugged into the correct slots.

Check the LVOl cable for proper connection to the M7258 or M8302 module.

Remove and check the M7258

M8302 for broken connections or damaged components. Look for

discoloration on all surfaces and loose solder joints.
4.

5.2

Check that jumpers are installed correctly as outlined in Paragraph 2.2.4.

DIAGNOSTICS

The
LV11
and
LV8/LV12 logic is completely checked by running MAINDEC-ll-DALVA-A and
MAINDEC-OS—DALVA-A, respectively, for ten passes. These programs, including a program listing, are supplied with
each LV11, LV12, or LV8 shipped. The program listing contains a program description and explanation, along with
instructions for running the diagnostic.

5-1

LV8/LV12/LV11
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