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DEC-12-GQZA-D

December 1971

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Equipment Corporation
Maynard, Massachusetts
Digital

PDP-12
User's Manual

FPP-12

Floating Point Processor

DEC-12-GQZA-D

FPP-12

FLOATING POINT PROCESSOR
USER'S MANUAL

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

1st Edition December 1970
2nd Edition April 1971

The material in this manual is for information purposes and

subject to change with-

out notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS
Page

CHAPTER 1 FPP12 PROGRAMMING DATA
1

1.2

Scope of the Manual

1-1

Introduction

1-1

Floating Point Number System

1-2

System Description

1.5

FPP12 Register Organization

1-4

1.6

Active Parameter Table

1-6

1.7

Programming the FPP12

1-7

1.7.1

Initialization

1-7

1.7.2

Serial vs Parallel Processing

1-10

1.7.3

IOT Instructions

1-10

1.7.4

IOT List

1-11

1.7.5

Instruction Set-Address Methods

1-12

1.7.6

Index Registers

1-12

1.7.7

Instruction Set

1-12

1.8

Data Reference Instructions

1-13

1.8.1

Special Format 1

1-14

1.8.2

Special Format 2

1-14

1.8.3

Conditional Jumps

1-15

1.8.4

Pointer Moves

1-15

1.8.5

Special Format 3

1-16

1.8.6

Operate Group - Special Format 3

1-17

-3

CHAPTER 2 FPP12 PROGRAMMING EXAMPLES
2.1

Introduction

2-1

2.2

Program Initialization

2-1

2.3

Index Registers as Address Modifiers and Loop Counters

2-3

2.4

Use of Index Registers to Create Push-Down Stacks

2-4

2.5

Branch or Jump on Condition Instructions

2-5

2.6

Writing Re-entrant Subroutines

2-5

2.7

Use of the FPHLT Instruction

2-6

2.8

Debugging FPP1 2 Programs on Units Attached to
PDP-12 Computers

2-6

2.9

Using the Execute Stop Switch

2-7

2.10

Care Necessary in the Use of Examine and Deposit

2-7

Switches
iii

CONTENTS (Cont)
Page
2.11

Additional Programming Hints

2-8

2.11.1

Illegal Mantissa

2-8

CHAPTER 3 FPP12 COMPONENTS
3.1

FPP1 2 Hardware Description

3-1

3.2

Description of Registers

3-2

3.3

Major States

3-5

3.4

Description of Registers

3-9

3.5

3-10

3.6

Data Break Control

3-10

3.7

Modules Introduced in the FPP1 2

3-11

3.8

Flow Diagrams

3-12

3.8.1

INITIATE

3-13

3.8.2

FETCH

3-14

3.8.3

DEPOSIT

3-15

3.8.4

EXIT

3-17

3.8.5

LDA and STR

3-17

3.8.6

DP ADD and SUB

3-17

3.8.7

ADD/SUB of FP NOS

3-18

3.8.8

MULTIPLY

3-19

3.8.9

DIVIDE

3-19

3.8.10

Special Instructions

3-20

3.9

Maintenance Logic

3-20

CHAPTER 4 FPP 12 INSTALLATION
4.1

Installation

4-1

4.2

Ac Power Requirements

4-1

4.3

CheckOut

4-3

ILLUSTRATIONS
Figure

No.

Page

Title

1-1

PDP-12 12/40 System Configuration

1-4

1-2

Typical Configuration of the PDP-12 with
Multiply Devices

1-5

ILLUSTRATIONS (Cont)
Figure No.

Title

Page

3-1

PDP-12 Single Cycle Data Break Timing

3-2

PDP-8 Single Cycle Data Break Timing

3-3

FPP12 User IOT Decoder System

3-4

Timing and Enable System in FPP12

3-4

3-5

FPP12 Data Flow System

3-5

o-O

Timing Diagram of State Generator

3-6

1-7

Rlrifk
diock Din/ii-i-im
L/iagram nt
or FPP19
rrr iz FFT(~H
rci^n Fl«n,

O IE

o o

diock uiagram or rrr

now

ucrUMi now

3-16

T A Dl EC

Table No.

Title

Page

1-1

Active Parameter Table Format

1-7

1-2

AC After Read Status Instruction

1-8

1-3

Command Register Setting

1-8

1-4

Instruction Execution Times

1-9

2-1

APT After FEXIT in Example 2-1

2-3

3-1

Functions Performed by DEC74181

3-13

3-2

Equivalence Between Instructions and Flow Routines

3-21

3-3

Definition of AC Bits After IOT 6562 Read States

3-22

4-1

PDP-8/L, PDP-8/1 Positive Bus and PDP-8/E

4-1

4-2

PDP-8, LINC-8, and PDP-8/1 with Negative Bus

4-2

4-3

Module Changes for Negative Bus Computers

4-2

CHAPTER 1
FPP12 PROGRAMMING DATA

1.1

SCOPE OF THE MANUAL

This manual contains instructions for programming and servicing the Floating Point Processor (FPP12),

a peripheral device for PDP-8 and

mation.

PDP-12 Computers. Chapters 1 and 2 contain programming infor-

Chapter 3 describes the logical components of the FPP12.

cedures are found in Chapter 4.

It is

Installation and check-out pro-

assumed that the reader is familiar with the operation of the

PDP-8/I, PDP-8/L, PDP-8, LINC-8, PDP-8/E or PDP-12 Computers.

It is

suggested that the reader

have as a reference the FPP Assembler Manual

1.2

INTRODUCTION

The Floating Point Processor (FPP12) is a programmable, peripheral, digital processor that attaches to
the input/output (I/O) bus of any PDP-8, PDP-8/I, PDP-8/L, PDP-8/E,

The FPP12 is a parallel processor with its own instruction set.

LINC-8, or PDP-12 Computer.

utilizes the direct memory access

or data break facility to "steal " memory cycles from the Central Processor Unit (CPU).

Similar to

a disk, the FPP12 is activated by the CPU through the use of programmed input/output IOT instructions.

Once activated, the FPP12 steals a maximum of 50 percent of the memory cycles from the

PDP-8, PDP-8/I, PDP-8/L, or PDP-8/E CPU.

For the PDP-12 there are two operating modes,

parallel and serial

In parallel

mode, the FPP12 steals a maximum of 50 percent, or every other memory cycle, from the

PDP-12, thus permitting the PDP-12 and the FPP12 to operate simultaneously.
serial

Once initiated in

mode, the FPP12 locks out the PDP-12 CPU for the duration of a complete calculation.

Serial

mode increases the FPP12 calculation speed by approximately 20 percent.
The FPP12 performs arithmetic operations on floating-point numbers 20 to 100 times faster and with
100 to 200 fewer memory cycles than software interpreters.

The FPP12 instruction set facilitates the

programming of complicated algorithms and the building of compilers for mathematical languages.
Variable length instructions are part of a flexible addressing scheme.

1-1

Direct addressing of 32K of

core memory is available using a 24-bit instruction format.

A 12-bit instruction format, in which

the operand address is relative to a programmable base register, reduces program length and facilitates

re-entrant coding.

Any eight sequential core locations can be used as an index register to modify

operand addresses.

Index registers are adjusted prior to use in address modification, to account for

the different number of core locations used in the two data formats permitted by the FPP12.

1.3

FLOATING POINT NUMBER SYSTEM

The term floating point implies a movable binary point similar to the movable decimal point used in
scientific notation.

An exponent is used to keep track of the number of spaces the binary or decimal

point is moved.

Examples of scientific notation:

234 = 23.4 x 10

= 2.34 x 10

Examples of binary floating-point notation:

(1011) = (101.1)x 2

(1.011) x 2

= (10.11) x 2

= (l.Oll)x 23

=0.1011 x 2 4 = 0.01011 x 2

In the example of binary floating-point notation given above, there are four significant bits.
in the last term, the fraction that multiplies the

bits,

it is

However,

Given a fixed number of

exponent contains six bits.

desirable to adjust the exponent and the binary point to eliminate leading zeros.

justment retains the maximum numerical significance for a given format length.

This ad-

The FPP12 normalizes

or removes leading zeros as the last step in every floating-point arithmetic operation.

The floating-point data format used by the FPP12 is identical to the format used by the PDP-8 floatingpoint system (DEC-08-YQYB-D) .

As shown below, there is a 12-bit signed 2's complement exponent

and a 24-bit signed 2's complement mantissa.

EXPONENT

MSW OF MANTISSA

BINARY POINT

LSW OF MANTISSA
0

12-0264

1-2

The FPP12 carries all calculations to 28 bits of precision, then rounds to 24 bits after normalization;
after rounding, the result

rechecked for proper normalization prior to completing the instruction.

In fixed-point arithmetic, the precision of a

number varies with the number's magnitude.

In addition,

the range of fixed-point numbers is generally limited in most mini computers to 12 or 16 bits.

With

the FPP12, the number range is 2+2047 to 2~2048; precision is maintained at 24 bits throughout the

number range.

Exceeding the upper limit, 2+2047, causes the FPP12 to interrupt the PDP-12 CPU

and set its exponent overflow status bit.
is

A calculation resulting in a exponent smaller than 2~2048

an exponent underflow that can cause a program interrupt.

At initialization, the programmer

has the option to request that the underflow trap be ignored, in which case the result of calculation
in

which underflow occurred is set to 0.

Fixed-Point 24-Bit Fraction Format
For those calculations where full 24-bit precision is not necessary and where core space is at a pre-

mium, the FPP12 can be used in fixed-point 24-bit mode.
2's

Each operand consists of a 24-bit signed

complement fraction as shown below.

BINARY POINT

12-0265

As in the case of the floating-point mode, each calculation is carried to 28 bits of precision and
rounded to 24 bits but no normalization is performed.
the precision of subsequent calculations.

Therefore, leading zeros occur which reduce

In fixed-point

mode, calculations resulting in a fraction

overflow cause the FPP12 to initiate a program interrupt with the fraction overflow status bit set to 1

1.4

SYSTEM DESCRIPTION

The FPP12 is initialized and interrogated as to its status via PDP-8 IOT instructions issued on the pro-

grammed I/O bus.

Once initialized, the FPP12 operates as a processor fetching instructions and

operands via the data break or direct memory access bus.
of a

PDP-12 and a FPP12 is shown in Figure 1-1

A typical system configuration consisting

Note that the PDP-12 Computer contains two data

break ports; one is permanently reserved for the LINCtape control, the other is available for a device

1-3

RELAYS

CRT DISPLAY

ANALOG TO

LINCtapes

DIGITAL CONV

3
J

REAL-TIME

LINCtape PORT

TELETYPE

INTERFACE
FACE KW12A

PDP-1Z

MEMORY
4-32K
12

BIT

PDP-12
CPU

PROGRAMMED PDP-8 I/O BUS

WORDS
FLOATING
POINT PROC.
FPP1 2

EXTERNAL DATA BREAK BUS

The FPP12 attaches to the EXTERNAL data break and programmed
I/O bus of the PDP-12 computer without additional hardware.

Figure 1-1

PDP-12 12/40 System Configuration

such as a disk, data break card reader control CD12, or the FPP12.
in addition to the

two or more data break devices,

LINCtape, are attached to the PDP-12, a memory multiplexer (DM12) is generally

required (see Figure 1-2). The exception is that the Analytical Instrumentation Package (AIP12) and
the FPP12 may both be attached to the data break bus without a memory multiplexer.

A special cable

that connects the FPP12 to the AIP12 contains the signals necessary to arbitrate data break requests be-

tween the AIP12 and the FPP12.

On the PDP-8, PDP-8/I, and PDP-8/L Computers only one direct memory access port is available;
attaching an FPP12 and DECtape, for example, requires a memory multiplexer.

Each data break de-

vice has its own memory port on the PDP-8/E Computer; therefore, a separate memory multiplexer is
not required on the PDP-8/E for up to 12 separate data break devices.

1.5

FPP12 REGISTER ORGANIZATION

There are eight registers in the FPP that are of interest to the programmer.
registers,

The functions of these

named below, will be discussed in the remainder of this chapter.
Function

Floating Point Accumulator (FAC)

36-bit register split into 12-bit exponent and
24-bit fraction.

Index Register Address Pointer (X0)

Contains the T5-bit core location of index
register 0.

1-4

RELAYS

CRT DISPLAY

)

( ANALOG TO

^DIGITAL

CONy

REALTIME
INTERFACE

LINCTAPE
»
PORT

KW12
PDP-12

MEMORY
4-32K

PDP-12
CPU

12 BIT

PROGRAMMED PDP-8

I/O

BUS

WORDS
256K
FIXED
HEAD
DISK

800K
REMOVEABLE

FLOATING
POINT

ANALYTICAL

DISK

PROC.

INTERFACE

RF08

INSTR.

FPP12

DATA

BREAK
EXTERNAL DATA BREAK BUS PRIORITY
MULIPLEXER
DM12

Figure 1-2

Typical Configuration of the PDP-12 with Multiple Devices

Function

Base Register (Base)

Contains the 15-bit base address used in calculating single-word addresses.

Floating Point Program Counter (FPC)

Contains the 15-bit address that is the location
of the next FPP12 instruction

Active Parameter Table Pointer

Loaded via IOTs with the 15-bit address of
the first location of the Active Parameter

Table (APT).

Command Register

The command register is loaded with an IOT
instruction. The command register selects
FPP12 operating modes, sets the FPP12 interrupt enable, chooses the important parameters
to be saved in the APT,

and fixes the most

significant 3 bits of the 15-bit APT pointer.

Status Register

The status register may be interrogated by the
CPU to determine the cause of an exit operation by the FPP12. The status register also
indicates if the FPP12 is in the run or (run) A
(F PAUSE) state.

1-5

Function

The operand address register is deposited in the

Operand Address Register

APT and contains one of the following:
a.

the last address-bearing instruction prior

to the exit was of the data reference class,

the operand address register contains the

15-bit address of the least significant word
of the operand.

the last address-bearing instruction prior

to the exit was an executed jump instruction,

the operand address register contains the jump
address.

If after

initialization an exit is performed prior

to the execution of a

jump or data reference

instruction, the operand address register

contains the FPC originally set by the APT.
d. The instructions SET BASE (SET B) and SET XO

ACTIVE PARAMETER TABLE

The Active Parameter Table (APT) (refer to Table 1-1) contains information necessary for starting or
restarting an FPP12 program.

The APT is defined as any two to eight locations in core.

pointer is set to point at the first entry of the APT.

The APT

The initialization procedure for the FPP12 in-

cludes two IOT instructions that set up a command register and set the 15-bit APT pointer to the first
location of the APT, shown as location P in Table 1-1 .

up the contents of the APT.

Following the second IOT, the FPP12 picks

Whenever the FPP12 performs an EXIT, the current contents of the APT

overlay the initial APT contents.

The APT performs three services for the programmer.

This reduces the CPU
It reduces the number of IOTs necessary to initialize the FPP12.
program overhead which is critical in multitask and time-shared environments.

It automatically

It provides convenient access to the information necessary for debugging FPP12 programs and determining the cause of FPP12 "error" exits such as exponent overflow,
underflow, or attempted division by 0.

saves the status of interrupted FPP12 programs.

With the exception of the operand address, all parameters contained in the APT are used in initializing the FPP12.

The operand address is stored for the use of the CPU program when the FPP12

exits.

1-6

Table 1-1
Active Parameter Table Format

Contents

Location
P

Field Bits

Field Bits of

of Operand

of Base

Index Register

Address

Location

Field Bits

P+l

Lower 12 bits c>f FPC

P+2

Lower 12 bits of Index Register 0 location X 0

P+3

Lower 12 bits of Base Register

P+4

Lower 12 bits of operand address

P+5

Exponent of FAC

P+6

MSW of FAC

P+7

LSW of FAC

of FPC

NOTE: APT address points to location P.

1.7

PROGRAMMING THE FPP12

The FPP12 is initialized and interrogated by PDP-8 type IOT instructions.

Once started, the FPP12

operates much like an actual processor, fetching instructions and operands and storing results in the

PDP-8 or PDP-12 core memory.
FPP12 as needed.

Data breaks or "stolen" memory cycles are generally requested by the

The maximum number of breaks requested is generally one per regular PDP-8 or

PDP-12 instruction.

This means that while the FPP12

run simultaneously at 50 to 70 percent of normal speed.

operating, PDP-8 or PDP-12 programs can be
Typically LINCtape, display, analog data

acquisition, and other forms of I/O can be performed by the PDP-12 Computer while the FPP12 is cal-

culating.

An optional mode is available to the FPP12 attached to a PDP-12 Computer.
the maximum FPP12 program speed

For calculations where

required, setting the proper command register bit (refer to Table

1-2) locks out the PDP-12 processor during FPP12 program execution.

Using the "lock out" mode on

the PDP-12 speeds up FPP12 programs by 15 to 25 percent (refer to Table 1-4).

1.7.1

Initialization

To execute the first instruction of any program, the FPP12 must have the 15-bit core address of the
first

instruction that is contained in the first two locations of the APT.

1-7

The contents of other locations

Table 1-2

AC Bit

Fixed-point mode.

Trapped instruction caused exit.

FPHLT instruction caused exit.

•

Fraction overflow in fixed-point mode caused exit.

Exponent overflow caused exit.

Exponent underflow has occurred.

Thp
IIC FAC wq<
VTUg not
UII^I^VJ.
IUI nlt^rf^H

Atfemnted
dividf*
IblllUI
UIVIUu nv
uUU JCU f»xit
OA II.
/ 0 routed
• 1

Exit on exponent underflow

optional

Unused

The FPP12 is currently paused.

The FPP12 is currently in a run state.

Table 1-3

Command Register Setting

AC Bit

ia>

Function if AC Bit Set to 1

h (~> O

AC After Read Status Instruction

Function when AC Bit Set to

AC bits 0-11 have the following function when the FPCOM IOT is issued.
0
1

Select fixed-point mode upon initiation.
Exit if exponent underflow occurs.

Otherwise, set result of cal-

culation and continue.

Forbid access to 4K memory fields other than the field that is oc-

cupied by the last location of the APT.
3

Enable CPU program interrupt when FPP12 Interrupt Request flag
is set. Skip is always enabled.

Do not store operand address on exits. The operand address is never
retrieved on initiate.

Do not store the address of index register 0 from or in the APT.

Do not store the base register from or in the APT.

Do not store the FAC from or in the APT.

Lock out the PDP-12 processor during FPP12 program execution.
Unused on PDP-8 FPP12 systems.

(Continued on next page)

1-8

Table 1-3 (Cont)

Command Register Setting

AC Bit

Function when AC Bit Set to 1

AC bits 0-11 have the following function when the FPCOM IOT is issued.
9
Most-significant 3 bits of APT pointer.

10
11

Note:

Setting bits 4-7 of the command register speeds up initiation and exit operations.
Setting command register bits 4-7 does not alter the relative position of items on

the APT.

multijob environments, command register bits 4-7 are typically set

to 0.

Table 1-4
Instruction Execution Times*

Serial

Instruction

FLDA

FADD
FSUB
FDIV

FMUL

FADDM
FMULM
FSTA

Octal Code

0200+X
1200+X
2200+X
3200+X
4200+X
5200+X
6200+X
7200+X

Double Precision
Execution Time

Mode

Parallel

Floating Point

Execution Time

Mode**

Double Precision
Execution Time

Floating Point

Execution Time

(us)

23
23

24
23

27
26
33

27
27
24
30

*AII times were measured using the single-word direct reference format.

30
39

Timing tolerance is ±20%.

**rbr these measurements the PDP-12 was performing mostly single cycle instructions.

of the APT are often useful in starting a program and essential in restarting an interrupt task.

Once

the appropriate parameters are placed in an APT table by the CPU, two IOTs must be issued.

FPCOM

(6553) loads a command register and the most significant 3 bits of the APT pointer.
of the bits in the command register is shown in Table 1-3.

12 bits of the APT pointer and starts the FPP12.

The significance

FPST (6555) loads the least significant

A typical initiate sequence is shown in Example 2-1.

Once initiated, the FPP12 will execute instructions until:
a.

An error condition, such as exponent overflow, occurs.

An FEXIT instruction is encountered.

1-9

1.7.2

An FPHLT IOT is issued by this CPU.

An I/O preset is issued by the CPU.

The CPU encounters any type of halt.

Serial vs Parallel Processing

The most efficient use of resources occurs when the CPU and FPP12 are programmed to operate in parallel.

For instance, in the display oriented research analysis

(DORA) program which faciliates display

interactive manipulation of data files, the PDP-12 refreshes a CRT display, performs Teletype®,

LINCtape, and disk I/O, and samples knob and sense switch positions while the FPP12 is performing
floating-point arithmetic.

Because the FPP12 and the CPU access the same core memory, the communi-

cation methods are virtually unlimited; either processor can alter the other's program or data.

Usually

the CPU is assigned the job of scheduling and I/O, while the FPP12 performs complex arithmetic.

However, in the DORA program, the FPP12 schedules I/O by passing parameters to the PDP-12 CPU.
There are occasions when it is desirable to complete an FPP12 calculation between operations per-

formed by the CPU„

Setting the appropriate command register bit in the FPP12 permits serial operation

with the PDP-12 Processor.

In serial

mode, the PDP-12 CPU is locked out from the executing instruc-

tions while the FPP12 is operating.

There is no provision for a true serial mode for an FPP12 on a PDP-8 type processor.

The fastest wait

loop for a PDP-8, PDP-8/I, or PDP-8/L Computer consists of a JMP instruction with the programmed
interrupt facility enabled, because data breaks can occur only between complete instructions.

the

PDP-8/E Computer, the data break facility is structured so that data breaks may occur after any

major state or multistate instructions.

Therefore, the particular CPU program in progress does not

affect the FPP12 instruction execution time on a

1.7.3

PDP-8/E Computer,

IOT Instructions

A complete list follows of IOT instructions with device code 55 that apply to programming the FPP12.
IOT instructions with device code 56 are relegated to maintenance programs.
IOTs is presented in Chapter 3.

The use of maintenance

a conflict exists between the FPP device select codes and the de-

vice select codes of another peripheral, the conflict must be resolved in the hardware by altering wired

connections in either the FPP12 or the conflicting device.

It is

recommended that the FPP12 device

codes not be altered because of the necessity of changing extensive diagnostic and system software.

However, the logic to be altered in changing device codes is found on Prints FPP12-0-CI!
FPP12-0-CI2, and FPP12-0-CI3.

Teletype is a registered trademark of Teletype Corporation.

1-10

1.7.4 IOT List

Mnemonic

Octal Code

Function

FPINT

6551

Skip when the FPP12 Interrupt Request flag is set.

FPICL

6552

Unconditionally reset the FPP12 including all flags.

To the FPP12, the IOT FPICL is the same as I/O preset.

FPCOM

6553

the FPP12 is not in a Run state and the FPP12 Inter-

rupt Request flag is not set, the FPP12 command register
is

loaded with the contents of the AC*.

in a

the FPP12

Run state, or if the Interrupt Request flag is set,

the FPCOM instruction is ignored.

FPHLT

6554

Force the FPP12 to exit, dump its status in the APT, and
set the Interrupt Request flag at the end of the current
instruction. The FPHLT instruction is used to abort an
FPP12 program in a multijob environment or in software
debugging. The following special features apply to the

FPHLT instruction.
a.

If FPHLT is issued prior to the FPST instruction, the
FPP12 will execute only one instruction after initiation and then exit with the FPC pointing to the

succeeding instruction. This facilitates single stepping through an FPP12 program under CPU control
b.

the FPP12 is in a Pause state, the FPP12 will exit

with the FPC pointing at the pause instruction. This
means that if a job was aborted in a Pause state it
will

be resumed in a Pause state.

Normally, if an exit is forced by FPHLT, AC02 will
be set to a 1 when either read status FPRST or FPIST
is issued.
However, if the forced exit causes the
FPP12 program to abort while an FEXIT instruction
is being executed, the CPU forced exit flag is
cleared. Thus, the CPU forced exit flag is an absolute indicator that a program was prematurely

aborted.

FPST

6555

the FPP12 is not running and the Interrupt Request flag is

not set, the least significant 12 bits of the APT pointer are

AC and the FPP is started. If the
FPP12 is in a Run state, but paused, the FPST instruction
will cause the FPP 12 to continue. Otherwise, the FPST
instruction has no affect on the FPP12. If the FPST instruction causes the FPP12 to start or continue, the CPU will
skip the instruction following FPST.
set to the contents of the

FPRST

6556

Read the FPP12 status register into the AC. FPRST may
be issued at anytime.

FPIST

6557

Skip if the FPP12 Interrupt Request flag is set.

the skip

occurs, read the FPP12 status register in the AC and
clear the status flags and the Interrupt Request.

*AC refers to the PDP-12 or PDP-8 accumulator while FAC refers to the FPP12 accumulator.

1-11

1.7.5

Instruction Set-Address Methods

Three types of data reference instructions are available:
a.

24-bit instruction with a 15-bit absolute address.

12-bit instruction with a 7-bit relative address.

12-bit instruction with a 3-bit relative address that specifies a 15-bit indirect address.

Full indexing capability is available for types a and c.

The determined operand address points at the

exponent of the operand in floating-point mode and at the most significant word of the operand in
fixed-point mode.

1.7.6 Index Registers

Any core location may be used as an index register. The core address of the current index register 0
is

stored in the XO register.

SET X instruction.

The XO register is initially set from the APT, but may be altered by the

Index register X is in location XO+X, where X = 0, .... ,7.

Accessing an array of data points requires incrementing the address of the current point by the data
length to yield the address of each successive point.

address modification.
it is

Index registers are used to accomplish this

The index register is incremented by one to access each successive point, but

multiplied by the data length, three for floating point and two for fixed point.

This quantity is

used as the displacement from the address specified in the instruction to yield the address of the current point.

Adjusting of index registers simplifies "skipping" through data arrays and permits a single

index register to be used as both a loop counter and address modifier (see Example 2-2).
is

selected by bit 5 of data reference instructions types a and c.

testing, and performing arithmetic on index registers.

Pre-incrementing

Instructions are available for setting,

In particular, the instruction ADDX,

which

adds the contents of bits 12-23 of the instruction to the contents of the index register specified by
bits 9-11 of this instruction,

1.7.7

useful in manipulating

"push-down stacks".

Instruction Set

The FPP12 instruction set is divided into two basic classes: data reference instructions and special
instructions.

Data reference instructions are those that operate on the two data formats specified in

Paragraph 1.8.

Data reference instructions include the basic arithmetic operations plus load and store.

All other instructions are special instructions that include index registers modifiers, jumps, pointer

moves, and the operate-type instructions.

The instruction set is presented in detail in the following paragraphs.

each group of instructions.

1-12

The instruction format follows

1.8

DATA REFERENCE INSTRUCTIONS*
OP Code

Mnemonic

FLDA

C(Y) - FAC

FADD

C(Y) + C(FAC)

-FAC

FADDM

C(Y) + C(FAC)

-Y

FSUB

C(FAC) - C(Y) -C FAC

FDIV

C(FAC)/C(Y) - FAC

FMUL

C(FAC) * C(Y) -FAC

FMULM

C(FAC) * C(Y) *Y

FSTA

C(FAC) - C Y

Data Function

Data Reference Instruction Formats

OP CODE
0

ADDRESS

ADDRESS
23

DOUBLE-WORD DATA REFERENCE INSTRUCTION
12-0270

Y = C (bits 9-23) + M * (C (X + XO) + C (bit 5)

OP CODE
0

)

*5 (X)

OFFSET
5

SINGLE-WORD DIRECT REFERENCE
12-02 71

Y = C (base register) + 3 (offset)

*In fixed-point mode the exponent of the

FAC is never altered.

1-13

OP CODE
0

OFFSET

X
6

SINGLE-WORD INDIRECT REFERENCE
12-0268

Y = C (bits 21-36 of C (base reg .) + 3* offset))
(

+ (M) * (C X + XO) + C(bit 5))* 5 (X)

8(X)= 1 if X/^OandOif X = 0

1.8.1

= 2 if fixed-point mode
3 if floating-point mode

Special Format 1

OP Code

Mnemonic

Function

JXN

The index register X is incremented if
bit 5 = 1 and a jump is executed to the
address contained in bits 9-23, if index register X is nonzero.
The instruction -trap status bit is set and
the FPP12 exits causing a PDP interrupt.
The unindexed operand address is dumped
into the APT.

Trapped

Instruc-

tions

6
7

OP CODE
0

ADDRESS

ADDRESS
SPECIAL FORMAT

1.8.2

23
1

Special Format 2

OP Code

Extension

Mnemonic

LDX

Function

The contents of the index register specified by
bits 9-1 1 are replaced by the contents of bits
12-23.

ADDX

The contents of bits 12-23 are added to the
index register specified by bits 9-11.

1-14

1.8.3 Conditional Jumps

Jumps,

performed, are to the location specified by bits 9-23 of the instruction.

OP Code

Extension

Mnemonic

JEQ

Jump if FAC = 0

JGE

Jump if FAC > 0

JLE

Jump if FAC < 0

Jump always

JNE

Jump if FAC ^ 0

JLT

Jump if FAC < 0

JGT

Jump if FAC > 0

JAL

Jump if impossible to fix the floating-point
number contained in the FAC; i.e., if the ex-

Function

ponent is greater than (23), n .

.8.4 Pointer Moves

OP Code
1

Extension

Mnemonic

SETX

Function
Set XO to the address contained in bits 9-23
of the instruction.

SETB

Set the base register to the address contained
in bits 9-23.

Jump and save return. Jump to the location

JSR

specified in bits 9-23 and the return is saved
in bits 21-35 of the first entry of the data block.
1

An unconditional jump is deposited in the ad-

JSA

dress and address + 1 , where address is specified
by bits 9-23. The FPC is set to address + 2.

OP CODE
0

EXTENSION

SPECIAL FORMAT 2

1-15

1.8.5

Special Format 3

OP Code
0

Function

Mnemonic

Extension

ALN

The mantissa of the FAC is shifted until the
FAC exponent equals the contents of the index
If bits 9-11 are
register specified by bits 9-11
zero, the FAC is aligned so that the exponent =
.

(23) ]Q-*

double-precision mode, an arith-

metic shift is performed on the FAC fraction.
The number of shifts is equal to the absolute

value of the contents of the specified index
register. The direction of shift depends on the
sign of the index register contents.

A positive

sign indicates a shift toward the least significant
bit, while a

negative sign indicates a shift

toward the most significant bit. The FAC exponent is not altered by the ALN instruction in
double-precision mode.
0

ATX

The contents of the FAC are fixed and the least
significant 12 bits of the mantissa are loaded into the index register specified by bits 9-11.

double-precision mode the least significant 12
bits of the FAC are loaded into the specified

index register.

The FAC itself is not altered by

the FLATX instruction.
.

XTA

The contents of the index register specified by
bits 9-11 are loaded right-justified into the FAC
mantissa. The FAC exponent is loaded with
(23)io and then the FAC is normalized. This
operation is typically termed floating a 12-bit

number.

double-precision mode, the FAC is

not normalized.

5-7

12-17

14-17

NOP

The single-word instruction performs no operation.

(

reserved

These codes are reserved for instruction
set expansion and should not be used.

*Setting the exponent = (23)}0 integerizes or fixes the floating-point number.
tests to see if fixing is possible.

1-16

The JAL instruction

1.8.6

Operate Group - Special Format 3

OP Code

Extension

Mnemonic

9-11 Bits

Function

Dump active registers into the APT,

FEXIT

reset the FPP12 RUN flip-flop to

the 0 state, and interrupt the PDP-12

processor.
1

FPAUSE

Wait for synchronizing signal
IOT
FFST (6555) will restart the instruction following FPAUSE.
.

FCLA

Zero the FAC mantissa and exponent.

FNEG

Complement FAC mantissa.

FNORM

Normalize the FAC.
precision mode

FNORM

doubleis

START F

Start floating-point mode.

START D

Start double-precision mode.

JAC

NOP.

Jump to the location specified by
the least significant 15 bits of the

FAC mantissa.

OP CODE
0

0
2

EXTENSION

0
4

SPECIAL FORMAT 3
12-0273

1-17

CHAPTER 2
FPP12 PROGRAMMING EXAMPLES

2.1

INTRODUCTION

Programming examples for the Floating Point Processor and a procedure for initializing the FPP12 are
contained in this chapter.

Several examples are provided that utilize index registers. A re-entrant

sine subroutine illustrates a technique for writing re-entrant code.

discussed in detail .

FPP assembler.

Program debugging techniques are

The mnemonics and syntax used in this chapter are consistent with those of the

A complete description of the assembler can be found in the manual entitled, FPP

Assembler Manual,

DEC-12-AQZA-D. A math package for the FPP is described in a manual entitled

FPP Support Library (DEC-12-YEXA-D).

2.2

PROGRAM INITIALIZATION

Each FPP12 program consists of one or more instructions and an Active Parameter Table (APT).

Upon

initialization, the APT (refer to Table 1-1) contains the initial setting of important FPP12 registers.

Whenever the FPP12 finishes or aborts a program, the APT is updated before the CPU is interrupted.
The CPU program in Example 2-1 starts the FPP12 with the APT pointer set to location 01000, which
is

word 1000 of field 0.

The FPP12 normally does not recognize page or field boundaries.

started in location 07777 , the least significant 12 bits of the

the APT

FPC would be found in location 10000.

Example 2-1 , the FPP12 will pick up locations 02000, 02001 , 02002, 02003, 02005, 02006, and

02007 of the APT.

Note that the operand address, location 02004 in this example, is never retrieved

from the APT by the FPP12.
first

After retrieving the contents of location 02007, the FPP 12 will fetch its

instruction from location 01000.

The 4 in the second digit of the contents of location 01000 in-

dicates that the instruction is a 2-word, direct addressing, data reference instruction.
first

digit of location 01000 indicates that the instruction

an FLDA.

specify the address, which is not indexed when bits 6-8 are all zero.

Bits

The 0 in the

9-23 of the instruction

After fetching the address, the

FPP12 will break to 12000, 12001 , and 12002 to load the operand into the FAC.

After retrieving the least significant word of the FAC from location 12002, the FPP12 will fetch an-

other instruction from location 01002.

The instruction in location 01002 is an FEXIT, equivalent

2-1

/ Sample program to initialize FPP12

00020

2000

ORG

00020

/Psuedo OP sets assembler origin at

APTPT,

APT

location (20) 8
/Pointer to APT

of field 0.

ORG 200
BEGIN,

/Clear AC
/Load 0's to FPP12 command register

CLA

FPCOM
TAD APTPT

/Set APT points to 02000 and start
/If no skip FPP12 is not ready to be started

FPST

HLT
FPINT
JMP. -1
HLT

/Wait
/Program done

/ A Sample
/ FPP12 Program is below

ORG 01000

Loc

contents

01000
01001

0401
2000

FLDA TAG

01002

0000

FEXIT

/Load contents of
/Location TAG into FAC

/Dump APT
/Into core and interrupt CPU

/ Active parameter table

ORG 02000

contents

Loc

02001

0
1000

02002

3000

02000

APT,

0000

/most sig bits

1000

/FPC
/X0

3000
4000

/Base

/ Operand address
/FAC exp
/FAC MSW
/FAC LSW

ORG
12000
12001

12002

12000

0002
3000
0000

TAG,

Example 2-1

to a halt instruction for the CPU.

/constant (3.0)^q

3.0

Sample FPP12 Program

Prior to stopping, the

FPP12 dumps the current APT over the initial

APT, beginning with the least significant word of the FAC in location 02007 and ending with
02000.

The APT at the completion of the FEXIT instruction is shown in Table 2-1

2-2

location

Table 2-1

APT After FEXIT in Example 2-1
02000
02001
02002
02003
02004
02005
02006
02007

1000
1003

/current Field Bits

2000
4000
2002
0002
3000
0000

/XO

/current FPC

/Base

/ Operand address
/exponent

/MSW
/LSW

Only after dumping the APT is the FPP12 Skip or Interrupt flag set.
ecutes a WAIT loop while the FPP12 is operational.

Example 2-1 , the CPU ex-

would be far more efficient for the CPU to

perform some other task, such as tape or Teletype I/O, while the FPP12 is calculating.

2.3

INDEX REGISTERS AS ADDRESS MODIFIERS AND LOOP COUNTERS

The FPP12 program in Example 2-2 moves a list of (200)g floating point numbers from an area of core
starting at location ALPHA to an area starting at location BETA.

both for loop counting and address modification.
set to -200 using the LDX instruction.
fier for the

Index register 1

FLDA instruction at location LOOP.

Note that index registers are used

set to -1

and index register 0 is

incremented prior to use as an address modi-

Index register 0 is used as a loop counter by the JXN

instruction.

LDX
LDX
FLDA

BEGIN,

LOOP,

-1,

/set index register 1 = -1

-200 , 0

/set index register 0 = (-200)g

ALPHA, 1+

/first C(l +

X0)= C (1 + X0)

+ 1 Then load FAC from loc.

FSTA

BETA,

ALPHA + C (1 + X0) *3
/Store FAC in loc BETA + C
(1

JXN LOOP, 0 +

+ X0) *3

/first

C (X0+ 0) = C(X0+ 0)

+1
/then go to loop if C (X0 + 0) ± 0
FEXIT

/trap to CPU

ORG 4000
ALPHA,

ORG 6000
0

BETA,

Example 2-2

It is

Move List from ALPHA to BETA Using Index Registers

possible to use the same index register as a loop counter and as an address modifier, because of

the method used

the FPP12 hardware to calculate indexed addresses.

an address, the FPP12 checks to see if indexing is required.

2-3

the process of formulating

indexing is required, the contents

of the specified index register are retrieved and "adjusted" by the appropriate multiplier,
for floating-point mode and 2 for fixed-point mode.

which is 3

Then the adjusted index register is added to the

unindexed address and the resulting addition, initially performed with 24 bits of precision, is truncated
to 15 bits by dropping the 9 most significant bits of the result.

method of indexed address calculation.

If it is

Example 2-3 illustrates the standard

necessary to use index register 5 as a loop counter,

additional care must be used in selecting the pointer to list A contained
the case where the loop counter is set to (-200)g.

[A + M(C (I) + (30000)g]

the instruction.

Consider

Then the pointer to list A must be modified to be

C (I) is the initial setting of the index register and M is the number of

12-bit bytes in the data word.

Example 2-4 is similar to Example 2-2; however, only one index

Initially

XO = 14003
C(X0 + 5) = 0001

FLDA A, 5

Instruction

0451
2003

A is location 12003
Address calculation proceeds as follows:
1.

The contents of (X 0 + 5) are retrieved and multiplied
by three.

The "adjusted" index register is added to 00012003 the
unindexed address to yield 00012006.

This address is truncated to 12006.

Example 2-3

Indexed Address Calculation

2.4 USE OF INDEX REGISTERS TO CREATE PUSH-DOWN STACKS
The subroutines in Example 2-5 illustrate the use of the ADDX instruction in creating push-down or
last-in-firsf-out

lists.

The PUSH routine is called with an argument in the accumulator.

routine returns with elements removed from the stack in the accumulator.

The POP

These subroutines are de-

signed to be called with the JSA instruction which places an unconditional jump to the return in the
first

two locations of the subroutine.

The PUSH and POP subroutines in Example 2-5 are valid for either fixed-point or floating-point mode,
as long as second and additional calls are in the same mode as the very first call.

2-4

BEGIN,

LDX COUNT,

LOOP,

FLDA ALPHA-(M*COUNT-50000),
JXN LOOP, + FSTA ALPHA-(M*COUNT-50000)

M = 3, If floating point mode
2, if fixed point mode

K = (70000L
Example 2-4

PUSH,

Index Register 1

Used as Both an Address Modifier and Counter

0
0

/Place contents of AC in stack

FSTA STACK, 2 +
JA PUSH

POP,

0
0

FLDA STACK, 2

/Retrieve item from stack

ADDX 2, -1

/Decrement stack pointer

JA POP

/Return from subroutine

Example 2-5

2.5

/Return from subroutine

Push-Down Stacks

BRANCH OR JUMP ON CONDITION INSTRUCTIONS

Seven conditional jump instructions are provided in addition to the JXN instruction.

Six of these,

JEQ, JGE, JLE, JNE, JCT, and JGT, test the FAC mantissa. The seventh, JAL, executes a jump
if

the FAC cannot be represented as a (24)]q bit binary number.

greater than (23) -jq or (27)g.

2.6

This occurs when the FAC exponent

WRITING RE-ENTRANT SUBROUTINES

A re-entrant subroutine is one in which the code is not altered during execution.
the interruption of a

This property permits

task which is executing a given re-entrant subroutine and the starting of another

task that uses the same subroutine.

The advantage of re-entrant coding is that two or more jobs can

use the same subroutine without concern as to when a given job is interrupted.

The single-word data reference instructions and a re-entrant jump to subroutine facilitate the writing
of re-entrant codes.

With the JSR instruction, the return address is saved in bits 21-35 of the location

pointed at by the contents of the base register.

If it is

necessary to store temporary values during sub-

routine execution, single-word instructions should be used^
to the base register setting.

This will force addressing to be relative

Each task will have a unique base register setting; therefore, the effective

addresses for temporary storage for each task will be unique, even though the offsets for the data instructions are never charged In the pure subroutine.

The return from the re-entrant subroutine consists

2-5

of the two instruction sequence,

FLDA ALPHA, JAC, shown in Example 2-6. JSR causes the return

address to be deposited into the first location of the data block,

base register.

ALPHA, which is defined by the

The return address is deposited into the FAC with the instruction FLDA ALPHA.

The

JAC instruction actually executes the return jump by setting FPC equal to bits 9-23 of the FAC.

/ Main Prog

MPROG,

JSR SUB
FEXIT

/Jump to sub prog.

SUB,

FLDA ALPHA
JAC

/Load return address

/Jump to the address contained in
/bits 9-23 of the FAC fraction

Base ALPHA

ALPHA,
Example 2-6

Return from Re-Entrant Subroutine

2.7 USE OF THE FPHLT INSTRUCTION
The FPHLT IOT (6554) permits the CPU to force the abortion of a running FPP12 program or to force
the FPP12 to execute one instruction each time

initialized.

In a

multitask or time-shared en-

vironment, it is often necessary to suspend a calculation prior to completion.

program,

it is

often desirable to examine the results of each instruction's execution.

FPHLT is issued while the FPP12 is executing a program, that program will be aborted at the end

of the current FPP12 instruction.

program interrupt.
if

When debugging a

The FPPI2 will dump the current APT in core and then cause a CPU

the current instruction is anything except FEXIT, status bit 02 will be set to 1

FPHLT forced the FPP12 to stop program execution.

Issuing

FPHLT prior to FPST will cause the FPP to initialize, execute one instruction, then exit.

repeating this procedure, the CPU can force the FPP12 to single step through a program.

2.8

DEBUGGING FPP12 PROGRAMS ON UNITS
ATTACHED TO PDP-12 COMPUTERS

The PDP-12 console (described in the PDP-12 System Reference Manual) is a powerful fool for debugging FPP12 programs.

Using the switches, one can single step through FPP12 programs, observing the

transfers between the FPP and the

PDP-12 memory on the console lights. Alternatively, the FPP12

program can run until a specific memory address is accessed, in which case the computer will halt,
permitting the console light to be examined.

While the computer is halted, memory may be examined

2-6

and altered with the switch register without disturbing the program counters associated with either
the CPU or the FPP12.

IOT instructions may be issued with the console switches that examine registers

within the FPP12.

If the

stop switch is raised during the execution of a FPP12 program, the PDP-12 will stop at the end

of a complete instruction or a data break caused by some external device such as the FPP12.

Depressing

the continue switch with the stop switch raised causes the execution of one CPU instruction or one

data break for each actuation of the continue switch.

one data break for each CPU instruction.
pressed a data break will occur.

Operating in this mode, the FPP12 will receive

This means that every other time the continue switch is de-

Whenever the break indicator light is lit, the MA and MB lights on

the console refer to the data break address and memory buffer contents associated with the FPP12

program.

The single step switch causes similar results, except the halts occur at the end of each major

state of the CPU instructions.

The single step switch is useful when the CPU program that runs in

parallel with the FPP12 program contains tape instructions.

The stop switch has no affect for the dura-

tion of LINCtape instructions.

If bit

8 of the FPP12 command register is set to 1, the CPU will be locked out while FPP12 programs

are executing.
tinue switch

2.9

This is reflected in the fact that the break light will stay on continuously as the con-

actuated.

USING THE EXECUTE STOP SWITCH

the execute stop switch is raised the PDP-12 will halt whenever the memory location whose address

contained in the left switches is accessed during any cycle except a CPU fetch cycle.

left switches to the first

Setting the

location of the next APT to be used and raising the execute stop switch causes

the PDP-12 to halt following the first FPP12 data break following FPST IOT.

2.10 CARE NECESSARY IN THE USE OF EXAMINE

AND DEPOSIT SWITCHES
Some care is necessary when using the examine and deposit switches, if they are to be used while a
FPP12 program is temporarily halted.

Problems arise because of the logical implementation of the

break field register within the PDP-12.

The 4K memory field examined on the first push of the examine

switch following a program may be the field into which the FPP12 was breaking when the program stop

occurred.

To be sure that the proper data for an examine operation is displayed in the MB register,

the examine switch should be actuated twice for the first operation following a program stop.

When

the computer system is restarted, the first PDP-12 cycle following an examine or deposit operation will

be a break cycle if the FPP12 is requesting a data break.

To ensure that the FPP12 breaks to the proper

4K memory field, the last operation after any series of examines and deposits must be a fill step.
2-7

2.11

ADDITIONAL PROGRAMMING HINTS

2.11.1

Illegal Mantissa

In the 2's
is

complement number system the number consisting of a one followed by twenty-three zeros

an illegal number because it and its 2's complement are both equal to -1

not allow this number to be generated as the result of any calculation.
to -1/2 the result shows up in the FPP as -1/2 *2 or -1.

than calculations.
the CPU's switches.

For instance,

it is

The FPP12 logic will

For instance,

possible for this

-1/2 is added

number to arise in other

possible to intentionally place a number into core memory from

The routine in Example 2-7 illustrates a test for the illegal fraction.

/The value in location A possibly has an illegal fraction

BEGIN,

FLDA
JGE

/Get C (A)

GOOD

/If C(A) 0 all

FNEG

/Form 2's complement of fraction

JLT BAD

GOOD,
BAD,

/Number is OK
/Number has illegal fraction

FEXIT
FEXIT

Example 2-7

Test for Illegal Fraction 100000000. . .000

Example of Re-Entrant Sine and Exponential Subroutines
Examples 2-8 and 2-9 contain the FPP code for calculating SINE (X) and X (X **Y).
indicate what each step of the routines is doing.

The comments

Both subroutines are written in the mnemonics and

syntax of the FPP assembler.

2-8

0001
v

CI CI
ti 01
yj

00
V V CSS
VJ

0006
0007
p /
0010
if

0
»0
tl 1
X 1X
0019
WWX£
(71511
7
«J
Xw

vvX"
(7101

V 1X
V9
C0
If
P0
X0
Pi

u 10 X /

IK'5 W X

ft 1

C O
1
1 IC 5 16 (.

77
77
lilt

ffl

C?j

0504
1 ft
? 0*5
VJ
X If 5
1 ft Pi 0 £

0 Pi 9 3

It'

051 1

0
If 7
If
f
X 05
X *J

POSITIVE

/GO TO CAL IF

1001
X
X
0 6 03

JEQ DONE

/GO TO DONE IF

0003 MOD,

FNEG
LDX 0,0

/NEGATE FAC
/SET INDEX REG TO 2ER0

002?
wet

JGT CAL

0503 1061
X W X

PI I7I

SINE USES THE 1ST 3 ENTRIES IN
THE BLOCK AND INDEX REG. 0.U2
X IS PASSED THROUGH THE 2ND ENTRY
IS RETURNED
/ IN THE BLOCK AND SINCX)
/ THROUGH THE SAME LOCATION
ORG 10500
BASE 0
X = l#3
XSQR=2#3
/ CALCULATE ABSOLUTE VALUE OF X. INDEX
/ REG 0 SET TO 0 INDICATES SIGN OF X
/ WAS NEGATIVE
FLDA X
SINE,
/INITIATE INDEX REG
LDX -1,0
/
/
/

0003
0004

P51X 9

fc-

•*

If ft*

KJ If iw \i
ft.

X f HV

0000
X-

IV It'

IL>

REDUCE X TO 1ST CYCLE USING THE
IDENTITY SIN(X)5SIN<N*2*PI*X)
009
^401
/DIVIDE X BY 2*PI
FDIV TWOPI
Iff £ A
^ X CAL.
V 1X 5 1X 9
£ O
0607
FSTA X
0027 10514 6201
Wc^ X
/X IS TOO LARGE
JAL ERROR
0030 10515 1 071
x ^ X w 0606
0
If 094
If £ «t

/
/

00if £3R3
10

ll^

ALN 0
v 0X
0032
FNORM
/GET INTEGER PART
0004
vw
0033 10521 2201
FSUB X
/GET FRACTIONAL PART
FNEG
0034 10522 0003
/SIN(2*PI*N> IS 2ER0
JEQ DONE
0035 10523 1001
^
10524 0603
/NORMALIZE TO BETWEEN 0 AND 2*PI
FMUL TWOPI
0036 10525 4401 REM
10526
V 0607
X
FSTA X
0037 10527 6201
0040
/ REDUCE X TO 1ST HALF CYCLE USING
/ THE IDENTITY SIN(X) x-SIN(X-PI) FOR
0041
/ PKX< = 2«PI
0042
FSUB PI
0043 10530 2401
10531 0612
JLT PCHECK
/IF X IS LESS THAN PI GP TO PCHECK
0044 10532 1051
10533 0543
/SET X TO X-PI
FSTA X
0045 10534 6201
/IF INDEX REG 0 WAS -1 SET TO 0 AND
JXN RESET 0 +
0046 10535 2101
10536 0541
/GO TO PCHECK*1
JA PCHECK+1
0047 10537 1031
10540 0544
LDX -1 ,0
/IF INDEX REG 0 WAS 0 SET IT TO -1
0050 10541 0100 RESET,
7777
10542
If

4. iy

t-J

-J f~

Example 2-8

SINE Routine (Sheet 1 of 2)

2-9

0052
/ REDUCE X TO 1ST QUARTER CYCLE USING
/ THE IDENTITY SIN(X)s SIN(PI-X) FOR
0053
/ PI/2<X<=PI
3054
0055 10543 0201 PCHECK, FLO A X
FSUB PIBY2
0056 10544 2401
/IF X IS LESS THAN OR EQUAL TO
10545 0615
JLE PALG
/GO TO PALG
0057 10546 1021
10547 0555
FID A PI
0060 10550 0401
10551 0612
/REPLACE X WITH P -X
0061 10552 2201
FSUB X
JA PALG+1
0062 10553 1031
10554 0556
FLDA X
0063 10555 0201 PALG
0064 10556 34 01
FDIV P BY 2
10557 K615
FSTA X
/NORMAL 2 E X TO BETWEEN 0 & 1
0065 10560 6201
FMUL X
0066 10561 4201
FSTA XSQR
/CALCULATE X«»2
0067 10562 6202
LDX -4,1
/SET UP INDEX REG 1
0070 10563 0101
10564 7774
LDX -1,2
/SET UP INDEX REG 2
0071 10565 0102
10566 7777
FCLA
0072 10567 io002
<C9#(2«*X/PI )«*2
/ CALCULATE SIN(X) =
0073
0074
/ C7)*(2«X/PI )«#2 + C5)«(2*X/PI )»*2
/ +C3)«(2«X/PI )»*2*PI)«2*X/PI
0075
F ADD C9,2+
/ADD C9 ON 1ST PASS, C7 ON
0076 10570 1521 LOOP,
2ND PASS, ECT.
10571 0620
0077 10572 4202
FMUL XSQR
/MULTIPLY PARTIAL SUM BY X«»2
0100 10573 2111
JXN L00P.1+
/GO TO LOOP 4 TIMES
10574 0570
0101 10575 1401
F ADD PIBY2
10576 0615
0102 10577 4201
FMUL X
0103 10600 2001
JXN DONE,0
/GO TO DONE IF X WAS POSITIVE
10601 0603
0104 10602 0003
FNEG
/NEGATE ANSWER
0105 10603 6201 DONE,
FSTA X
/STORE ANSWER
0106 10604 0200
FLDA 0
0107 10605 £007
JAC
/RETURN TO CALL
0110 10606 0000 ERROR,
FEXIT
/EXIT ON ERROR
0111 10607 0003 TWOPI,
3.1415926#2.0
10610 3110
10611 3756
0112 10612 0002 PI,
3,1415926
10613 3110
10614 3756
0113 10615 £001 PIBY2,
3,1415926/2.0
10616 3110
10617 3756
0114 10620 7764 C9,
*1 .5146190E-04
10621 2366
106 22 5615
0115 10623 7771 C7,
-4.6737656E-03
10624 5466
001/
0116 10626 7775 C5,
+7.9689679E-02
10627 2431
10630 5053
0117 10631 0000 C3,
-6.4596371E-01
10632 5325
I

(

FfiZZ

Example 2-8

(

SINE Routine (Sheet 2 of 2)

2-10

/ EXP USES THE 1ST 6 ENTRIES IN
0001
/ THE BLOCK
0002
0003
/ INDEX REG, 0 MUST BE SET TO THE
0004
/ POSITION OF THE EXPONENT OF THE
0005
/ 5TH ENTRY IN THE BLOCK
0006
/ X IS PASSED THROUGH THE 2ND ENTRY
000 7
/ IN THE BLOCK AND EXP(X) IS RETURNED
0010
/ THROUGH THE SAME LOCATION
ORG 10500
0011
BASE 0
0012
X = l#3
0013
F = l»3
0014
FSQR=2»3
0015
TEMP=3»3
0016
10X0=4*3
0017
0020
/ CALCULATE THE ABSOLUTE VALUE OF X
/ INOEX REG 3 SET TO 0 INDICATES THAT
0021
/ THE SIGN OF X WAS NEGATIVE
0022
0023 10500 0201 EXP
FLDA X /GET X
/INITIATE INDEX REG 3 TO -1
0024 10501 0103
LDX -1,3
10502 7777
JNE NZRO
0025 10503 1041
/GO TO NZRO IF X IS NOT EQUAL TO
10504 0511
FLOA Kl
/SET FAC TO 1
0026 10505 0401
10506 0601
/RETURN TO CALL
JA RETURN
0027 10507 1031
10510 0573
/GO TO GTZERO IF X WAS POSITIVE
JGT GT2ER0
0030 10511 1061 NZRO,
10512 0516
/SET INDEX REG 3 TO 0 TO INDICATE
LDX 0,3
0031 10513 0103
X WAS NEGATIVE
10514 0000
FNEG
/NEGATE THE FAC
0032 10515 0003
0033 10516 4401 GTZERO FMUL LG2E
/MULTIPLY X BY L0G2(E)
10517 0576
/STORE RESULT TEMPORARILY
FSTA TEMP
0034 10520 6203
FLDA Kl
0035 10521 0401
10522 0601
FSTA 10X0
/SET IDX0 TO l*2»»l»i/2
0036 10523 6204
FLDA TEMP
0037 10524 0203
ALN 0
/F AC=Ns NTEGER PART OF X*L0G2(E)
0040 10525 0010
ATX 0
/IDX0=2»*N*l/2
0041 10526 0020
/IDX0=2*»<N+1)«1/2=2»»N
AODX 1,0
0042 10527 0110
10530 0001
THE 5TH ENTRY IN THE BLOCK
0043
CONTAINS 2«#N WHERE N IS THE
0044
INTEGER PART OF X*L0G2CE>
0045
FIND F = FRACT ONAL PART OF X*L0G2(E)
0046
FNORM
/FAC CONTAINS INTEGER PART OF
0047 10531 0004
X»L0G2(E)
0050 10532 2203
FSUB TEMP
FNEG
/FAC CONTAINS FRACTIONAL PART OF
0051 10533 0003
X*L0G2(E>
FSTA F
0052 10534 6201
>

Example 2-9

Exponential Subroutine (Sheet

2-11

of 2)

/ CALCULATE 2»»FH*2»( A-F*B*F*»2t
0054
C/(D+F«*2>
0055
FMUL F
0056 10535 4201
/FSQR*F«»2
FSTA FSQR
0057 10536 6202
F ADD 0
0060 10537 1401
10540 0620
/TEMP=D*F»»2
FSTA TEMP
0061 10541 6203
FLO A C
0062 10542 0401
10543 0615
/FAC=C/(D*F»«2>
FDIV TEMP
0063 10544 3203
FSUB F
0064 10545 2201
FADD A
0065 10546 1401
10547 0607
/TEMP=A-F*C/(D*F»»2)
FSTA TEMP
0066 10550 6203
FLDA B
0067 10551 0401
10552 0612
FMUL FSQR
0070 10553 4202
FADD TEMP
007i 10554 1203
/TEMP=B»F«»2+A-F*C/(0*F»*2)
FSTA TEMP
0072 10555 6203
FLDA X
0073 10556 0201
/FAC*2»F
FMUL K2
0074 10557 4401
10560 0604
FDIV TEMP
0075 10561 3203
/FAC s l*2»F/< B*F«»2*A-F + C/(D*F«»2>
FADD Kl
0076 10562 1401
10563 0601
/ CALCULATE EXP X =2 »• X«L0G2 < E
0077
<2»«N)M2»*F)
/
0100
FMUL IDX0
0101 10564 4204
/GO TO RETURN IF X WAS POSITIVE
JXN RETURN. 3
0102 10565 2031
10566 0573
/ CALCULATE EXP(-X)*1/EXP<X)
0103
FSTA X
0104 10567 6201
FLDA Kl
0105 10570 0401
10571 0601
FDIV X
0106 10572 3201
/STORE RESULT IN X
FSTA X
0107 10573 6201 RETURN
FLOA
0
0200
0110 10574
/RETURN TO CALL
JAC
0111 10575 0007
1,442695
0112 10576 0001 LG2E.
10577 2705
10600 2434
1,0
0113 10601 0001 Kl,
10602 2000
10603 0000
2.0
0114 10604 0002 K2,
10605 2000
10606 0000
9,954596E*01
0115 10607 0007 A.
10610 3070
10611 5703
3.465736E-02
0116 10612 7774 8
10613 2157
10614 5161
6,179723E*02
0117 10615 0012 C.
10616 2323
10617 7434
8,741750E*01
0120 10620 0007 0,
10621 2566
10622 5341
<

(

)

Example 2-9

Exponential Subroutine (Sheet 2 of 2)

2-12

)

CHAPTER
FPP12

3.1

COMPONENTS

FPP12 HARDWARE DESCRIPTION

The FPP12 is a peripheral processor that attaches to both the programmed I/O bus and the data break

I/O bus. Figure 1-2 shows a typical configuration of an FPP12 attached to a PDP-12, with several
other peripherals.

It is

of major importance to fully understand the differences between the I/O bus

LINC-8, PDP-8, PDP-8/I, PDP-8/L, and PDP-8/E Computers.

of the PDP-12,

computers share a compatible I/O structure.

compatible with all of these computers.
a.

All of DEC's 12-bit

Most peripherals such as the FPP12 are nearly plug-in

Major differences are listed below:

PDP-8/L, PDP-8/E, PDP-12, and some PDP-8/l's have what is referred to as a positive

I/O bus which implies that the I/O signal levels are TTL compatible. The PDP-8,
LINC-8, and some PDP-8/l's have a negative I/O bus which implies that the I/O signal
levels are 0 and -3V with reference to chassis ground. Bus driver and receiver modules
in

the FPP12 are selected for either positive or negative bus computers.

The sense of the IOP pulses is inverted on those computers with a negative I/O bus. To
account for this, certain wiring changes must be made on FPP12 logic to convert it to
negative bus units. These changes are detailed in Chapter 4. If the original purchase
order for the FPP specifies an FPP12N, the negative bus changes will be factory installed.
Data break timing on the PDP-12 Computer differs slightly from data break timing on
PDP-8 type computers. On the PDP-12, the trailing edge of ADDRESS ACCEPT
indicates memory buffer strobe; on the PDP-8s, PDP-8/1, PDP-8/L, and PDP-8/E the
leading edge of BUFFERED TIME STATE 3 indicates memory buffer strobe. The line
that carries the signal BUFFERED TIME STATE 3 on the PDP-8 type computer is the same
one that carries BUFFERED TIME STATE 5 on the PDP-12 Computer. Therefore, the
FPP12 wired in the positive-bus PDP-8/1, PDP-8/L, and PDP-8/E configuration will
operate on a PDP-12 but will not achieve optimum performance.
the

Raising pin N16V2 of the I/O cable on a PDP-12 Computer will lock out the CPU.
The FPP12P will utilize this option when command register bit 8 is set to 1. Time
comparisons are shown in Table 1-3. On computers other than the PDP-12, pin N16V2
Therefore, run F05U2 - B03V2 is deleted in the FPP12
is used for different purposes.
when it is configured for processors other than the PDP-12.

Data break timing diagrams for the PDP-12 and other Family of 8 Computers are shown' in Figures 3-1

and 3-2.

3-1

III
TP4

"•3

TPS

CYCLE

SET AT SAMPLE TIME

Tfl

TPJ

Tf S

MEM

frf*

TPI

/EXT. MEM

DATA ADDRESS
INPUT LEVELS

HEAD AT
ADORESS TP BY
READ
k»l PROCESSO,

—

TPS

NEXT CYCLE

END Of WEAK CVCLE

START Of BREAK CYCLE

(INPUT TO PROCESSOR)

*f*

L_ USED TO SELECT BREAK CYCLE AT TP

SAMPLE
AT TP

TP*

CYCLE

EARLIEST TIME POSSIBLE TO REMOVE ADDRESS IS AT START Of SAC AM CYCLE

~
TPI -TP
j

GNO
IN

(+3V)

—CAN CHANGE ANYTIME AFTER TPS

LATEST POSSIBLE TIME IS TP

OUT (GNO)
AVAIL <+3V) -

7
WffiF

NOT AVAIL «M01
AVAIL (43 V

AVAILABLE AT TP 3
NOT AVAIL (+3V)

TIME DURING WHICH DATA MUST BE STROBED BY I/O DEVICE

NO REOU£ST(+3V)

MUST OCCUR EARIER THAN 1PZ

"yt-ut'n
"l REQUIRES

MUST OCCUR ONLY WHEN B BREAK

REQUEST (CNO)
+3V

GRN

•

+3V

OHO

Figure 3-1

PDP-12 Single Cycle Data Break Timing

3.2 DESCRIPTION OF REGISTERS
Floating Point Processor Systems organization is shown in Figures 3-3, 3-4, and 3-5.

The User IOT

Decoder System (see Figure 3-3) describes the simplest communication path between the CPU and the
FPP12.

LOT (device code 55) instructions of interest to systems programmers are described in detail

in Chapter 1.

Maintenance IOT's (device code 56) are described in Paragraph 3.9.

The FPP12 Timing and Enable system are shown in Figure 3-4.

The Major State and Time Slot gen-

erator provides up to 16 major time states in any 6 major or enable states.

Each major time state con-

tains 4 mini states; therefore, a total of 384 time slots are provided by the FPP12 timing system.

timing diagram for the state generator is shown in Figure 3-6.

Typically at any one instant of time,

one or two gates in one of the 6 state enable sections is qualified.

A qualified gate in the state

enable system may conditionally qualify any number of Register Gates.
register gate causes a register transfer on the next clock pulse.

The

It is

A conditionally qualified

appropriate to observe that the

FPP12 logic is fully clocked, i.e. , all flip-flops change state on the occurrence of a pulse from the
system clock generated by a free-running RC oscillator adjusted to a frequency of 5 mHz.

3-2

TP1

TPZ

TP3

TP I

TP2

COMPUTER TIME
I

PREVIOUS CYCLE

—»4*

SUMP LEO AT TP BY PROCESSOR

m\m

SAMPLE AT TP 4 -

NEXT CYCLE

SIGNAL MUST GO TO-3V AT START OF ADDRESS ACCEPT PULSE IF NEXT CYCLE IS NOT TO

SET AT TP1

BREAK CYCLE -

BE A BREAK

JSEO TO SELECT BREAK CYCLE AT TP 4

YCLE'OV -i
-

I—

CLE'-3V

SAMPLED AT TP 3, TYPICALLY HARDWIRED FOR A GIVEN DEVICE

START OF BREAK CYCLE

END OF BREAK CYCLE

-3V-Q

GND-I

DATA ADDRESS
INPUT LEVELS
(INPUT TO PROCESSOR

READ AT TP 4 —
PROCESSOR

<"-l

EST TIME POSSIBLE TO REMOVE ADDRESS IE AT ADDRESS ACCEPT PULSE

-3V«0

OND

ITP4-TP1

035-0.49MI
OUTIGNDI

-i

SAMPLED AT TPS BY PROCESSGR
IN I-3V)

I—

IGND)

I—

CAN CHANGE ANYTIME AFTER TP 2 OF BREAK CYCLE

[*— SAMPLED AT TP g B PROCESSOR
NOT AVAIL. (-3V)

-J

AVAIL (GNO)

AVAILABLE AT TP 2

WHICH DATA MU5T BE STROBED BY I/O DEVICE

NOT AVAIL (-3V)

REQUEST IGNO)
'[/^TIME'/if

MUST RISE EARLIER THAN TP 4

REQUIRED a

NO REQUEST I-3VI -

GATlEO IN PROCESSOR By
B BREAK

MUST FALL BY TP 4

GND -

i__r
GND

r—

-av

IOUTPUT TO I/O DEVICE)

r
PULSE OCCURS IF MEMORY
INCREMENT IS REQUESTED
AND THE WORD OVERFLOWS

Negative I/O Bus & Logic

TP!

TP4

COMPUTER TIME

+ SV
-

[»— SI

TP3

— BREAK

SAMPLED AT TP1 BY PROCESSOR

GND -

J
GND

»>

NEXT CYCLE

SIGNAL

BE A E

USED TO SELECT BREAK CYCLE AT TP4

SAMPLE AT TP 4

CYCLE

- SAMPLE D AT TP 3

TYPICALLY HARD-WIRED FOR A GIVENOEVICE

•

END OF BREAK CYCLE

START OF BREAK CYCLE

GND*
DATA ADDRESS
INPUT LEVELS
(INPUT TO PROCESSOR)

CYCLE -

tsvo

TPZ

PREVIOUS CYCLE

+ 3V-0

EARLIEST POSSIBLE TIME TO REMOVE ADORESS IS AT ADDRESS ACCEPT PULSE

GND'

+ 3V

GNO

INI+3V]

OUT [GND) +

CAN CHANGE ANYTIME AFTER TP? OF 8REAK CYCLE

3VO '//////////M.

GNO •

SAMPLED AT TPZ BY PROCESSOR %j

IGNALS MUST BE + 3V
NLESS 8 BRE AK IS

RESENT

+ 3VO
TIME DURING WHICH DATA MUST BE STORED BY I/O DEVICE

AVAILABLE AT TP2

NO REQUESTS 3V) -

" INCREMENT TO REQUEST
(INPUT TO PROCESSOR)

L EARLIER THAN TP4

REQUIRED

REQUEST (GND]

|||

L
PULSE OCCURS IF MEMORY
INCREMENT 13 REQUESTED

-AND THE WORD OVERFLOWS

Positive

Figure 3-2

I/O Bus & Logic

PDP-8 Single Cycle Data Break Timing

3-3

STATUS REQ.
(FPRST)+(FPIST) (INTERRUPT)

(INTERRUPT) (FPI ST + FPINT) +( RESTART) + START)
(

•

SKIP BUS

RESTART

CPU IOP PULSES
(RUN) (FPAUSE)

IOT

BUFFERED MB BITS

3-11

DECODER
(NOT RUN) (INTERRUPT CLEAR

)

-START FPP12

(FPCOM+FPSTXNOT RUN) (INTERRUPT CLEAR)

CPU BUFFER AC

(FPCOMMNOT RUNKINTERRUPT CLEAR)

DATA
SWITCH

(FPICD-HI/O PRESET)+(FPIST) (INTERRUPT SET)

•APT POINTER

"COMMAND REGISTER
•GLOBAL RESET
12-0274

Figure 3-3

FPP12 User IOT Decoder System

INITIATE

DATA BREAK

ENABLES

CONTROL

FETCH

ENABLES
COUNTERS

AND
MAJOR

REGISTERS

EXECUTE
ENABLES

STATE

a
TIME

SLOT
GENERATOR

PROCESS
ENABLES

ARITHMETIC
LOGIC
UNIT

DEPOSIT
ENABLES

EXIT

DIGITAL

ENABLES

MULTIPLEXER

SYSTEM CLOCK-

Figure 3-4

Timing and Enable System in FPP12

3-4

DATA BREAK DATA LINES

FAC
FPP1 2 AC

XO INDEX
REGISTER
POINTER

BASE
REGISTER

MQ
REGISTER

SHIFT

A
REGISTER

COUNTER
DIGITAL

DATA MUX
B

CPU MEMORY BUF

APT
POINTER

PROGRAM
COUNTER

OPERAND
ADD REG.

DATA BREAK

ADDRESS

Figure 3-5

FPP12 Data Flow System

The FPP12 data flow system is shown in Figure 3-5.

In some respects

FPP12 architecture is similar to

the PDP-8 in that major registers are multiplexed through a central arithmetic logic unit.

However,

FPP12 logic design is based on the use of medium-scale integrated circuit technology (MSI).

The

Operand Address Register, Program Counter (FPC), and APT pointer are formed from 4-bit binary

up/down counters.

This permits the incrementing of address registers and the performance of arithmetic

operations on data variables simultaneously.

The arithmetic logic unit consists of seven 24-pin MSI

devices that can each perform all 16 Boolean and 16 different arithmetic functions on two variables.
Full carry -look -a head permits the addition or subtraction of two variables in under 100 ns.

3.3

MAJOR STATES

The FPP12 logic is organized into six major states:

INITIATE

FETCH
PROCESS
EXECUTE
DEPOSIT
EXIT

3-5

MINI

STATE ADVANCE?

STATES

CLOCK

MINI 2

MINI 3

STATE CHANGE

D (1)

4 MINI PULSES

RESET CHANGE

AT THIS TIME, IF
ZERO OR STROBE
GO HIGH, INCREMENT
IS RESET

INCREMENT

INDEX

ONLY ONE OF INDEX
0 STATES, OR LOAD STATE
GOES LOW DEPENDING ON
WHICH OF INCREMENT, ZERO,
OR STOBE IS HIGH

STOBE STATES

LOAD STATE

Figure 3-6

Timing Diagram of State Generator

3-6

With one exception, if any major state flip-flop on print CNR is set the FPP12 will be actively
calculating.

If all

major state flip-flops are reset, the FPP12 will be inactive.

The single exception

has to do with the instruction FPAUSE, which causes the FPPI2 to wait for a synchronizing signal before preceding.

The FPP12 operations that occur in each major state are detailed below:

INITIATE

INITIATE begins at the trailing edge of IOP 4 when IOT instruction 6555
is issued by the CPU, if the FPP12 is not running and the FPP12 and the
FPP12 Interrupt Request flag is reset. During INITIATE, the contents of
the APT are retrieved.

NOTE
Only the first two locations of the APT must be used as
these contain the 15-bit initial setting FPP12 program

counter (FPC).

erand address,

The fifth location of the APT, the opnot retrieved during INITIATE.

Following the completion of INITIATE the FPP12 proceeds to FETCH time
state 0.

Schematic drawings for INITIATE are found on print ARS2.

FETCH

During FETCH, preliminary decoding of instructions occurs. Instructions
that require only one major time state to be completed, such as FCLA,

are completely finished during FETCH State 0.

Special instructions that

require more than one major time state, such as ALN 0, or more than one

memory cycle, such as ATX, cause the FPP12 logic to go from FETCH
State 0 to PROCESS State 1.

All data reference instructions require

FETCH to continue beyond FETCH State 0 in order to calculate the operand address. At the end of the FETCH cycle for all data reference
instructions, a transfer is made to EXECUTE State 0, with the Operand
Address Register appropriately loaded. FETCH begins in State 0 and ends
when the address calculation is complete. FETCH schematics are found
on prints FTH1 through FTH3.

PROCESS

Most special instructions that require more than one major time state or
more than one memory cycle are completed in PROCESS. With the exception of NORM and XTA, the FPP12 returns to FETCH State 0 after
the completion of PROCESS. Processing for XTA and NORM is completed
in

DEPOSIT.

PROCESS begins in major time state 1. PROCESS schematics

are found on prints SPIT through SPI3.

EXECUTE

The execution of all data reference instructions begins during EXECUTE.
FLDA and FSTA are completed during EXECUTE. For all other data
reference instructions the FPP 12 proceeds to DEPOSIT at the completion
of EXECUTE if no EXECUTE error is encountered. EXECUTE errors are
defined as:
a.

An attempt to divide by 0

A fraction overflow in fixed-point mode.

3-7

EXECUTE
(Cont)

At the completion of EXECUTE for instructions other than FLDA and FSTA,
the un-normal ized result of any calculation is stored in the O register and
an exponent is stored in the MQLSW. The exponent contained in the
MQLSW is the operand exponent for FMUL, FMULM, and FDIV and the
resultant exponent before normalization for FADD, FADDM, and FSUB.
The shift counter is 0 if no fraction overflow occurred, and 1 if a floatingpoint fraction overflow occurred.

EXECUTE schematics are found on

prints ASTO through AST3.

DEPOSIT

DEPOSIT begins in major time state 11 and ends in major time state 15.
As DEPOSIT is the only function performed during these time states,
DEPOSIT enables shown on prints DEP1 through DEP3 are not gated with
the

DEPOSIT flip-flop found on the CNR print.

During DEPOSIT the

following functions are performed in the order listed:

The results of all floating-point arithmetic calculations are
normalized. The number of shifts is stored in the shift counter.

The normalized result is rounded to 24 bits.

For FMUL and FMULM the FAC exponent is added to the

MQLSW.
d.

For the FDIV instruction the MQLSW is subtracted from the

FAC exponent.
e.

The contents of the shift counter are added to the un-normalized
exponent.

If the exponent resulting after normalization is within bounds,
-2048 to +2047, the resultant answer is stored in the FAC for all
operations except FADDM and FMULM. For FADDM and FMULM,

the resultant answer is stored in the addressed location.

After

FPP12 returns to FETCH State 0,
unless the IOT FPHLTwas issued by the CPU during the current

storing the resultant answer, the

instruction

the exponent is not within bounds after normalization the ap-

propriate status bit is set and the FPP12 enters EXIT State 0.

DEPOSIT schematics are found on prints DEP1 through DEP3.
EXIT

During EXIT the current APT is deposited into core over the initial APT.
Only the first two locations of the APT must be deposited; the other locations are optional according to the command register setting. The items
in the APT are always located in the same position relative to one another.
If

the programmer chooses not to deposit the operand address the fifth lo-

cation of the APT is simply skipped.

The field bits of the base register,
X0, and FPC are the first retrieved on INITIATE and last deposited during
EXIT.

EXIT is entered for any of the following conditions:
a.

A FEXIT instruction is encountered.

A fraction overflow occurs in fixed-point mode.

An exponent overflow or underflow occurs in floating-point
mode. If EXIT is entered for an exponent underflow command,
register bit
If it is set

tested.

If it is

set to 1, the

EXIT is continued.

to 0, the result of the previous calculation is set to 0

3-8

and the FPP12 returns to FETCH State 0. If an exponent underflow
occurs, status bit 6 is set as an indicator, even if command reg-

EXIT (Cont)

ister bit

set to 0.

An attempt to divide by 0 is made.

A FPHLT IOT is issued by the CPU.

At the end of EXIT the FPP12 halts in major time state 0 with all major
The FPP12 skip flag is set and the CPU program

state flip-flops reset.
interrupt is actuated

command register bit 3 is set to 1.

3.4 DESCRIPTION OF REGISTERS
Most major registers of the FPP12 are described in Paragraph 1.5.
B register,

and O register are hidden from the programmer.

The MQ, shift counter, A register,

Their characteristics are as follows:

The MQ is a 28-bif parallel-serial input, parallel output, left-right shift
register. It is divided into an MQLSW of 12 bits and an MQMSW of 16

contains the absolute value of the
During multiplication, the
temporarily contains the
the
division,
During
multiplier mantissa.
un-normalized absolute value of the quotient. When entering deposit, the
MQLSW contains the un-normalized resultant exponent for FADD, FADDM,
and DSUB and the operand exponent for FMUL, FMULM, and FDIV. The
bits.

found on print MQR1

SHIFT COUNTER The SHIFT COUNTER is a 6-bit binary up/down counter. As its name
implies, it is used to count shifts. The SHIFT COUNTER is found on
print CAR 6.

A REGISTER

These 28-bit registers are inputs to the arithmetic logic unit (ALU) of the

AND

M190. The A register is a 28-bit storage register; the B register is a

B REGISTER

parallel-serial input parallel output shift register that shifts towards the
least significant bit.

O REGISTER

The O register is the 28-bit output buffer for the M190.

It is

a parallel-

serial input, parallel output shift register that shifts towards the most

significant bit.

The A, B, and O Registers are found on the AMSW, ALSW, and EXT prints.
The following registers (listed below with the prints on which they are found) were described in
Paragraph 1.5.

CAR 2 and CAR 3
CAR 4
CAR 5
CAR
CAR

FAC
X0 REGISTER

BASE REGISTER
FPC
APT POINTER
OPERAND ADDRESS
CAR
REGISTER
CAR 8
STATUS REGISTER
COMMAND REGISTER CAR 8
1
1

3-9

The operand address register, the FPC, and the APT pointer provide the addresses for data breaks.
These registers are attached to a digital multiplexer that drives the EXT address lines of the CPU,

The

FAC, XO register, base register, 0 register, MQ, and shift counter feed the digital multiplexer that
loads the

3.5

A and B Registers.

The OR gates in the register gating system found on prints RG1 through RG10 funnel enables from many
sources into signals that,

when added with a clock pulse, cause a register action.

a load, shift, count, or a clear.

through RG10.

This action can be

The signals that actuate the data multiplexer are found on prints RG7

The multiplexer gates are enabled for at least the duration of a mini time state.

time from the beginning of the mini time state until the clock pulse, shown on Figure 3-6,

The

allowed

for the data to settle on the register inputs.

3.6

DATA BREAK CONTROL

The FPP12 accesses core memory via the single-cycle data break facility.

The data break control

serves the following functions:

Channels data break and direction requests to the CPU from the state enables.

Gates the proper address register onto the EXT ADD bus of the CPU.

Gates the proper data register onto the EXT DATA bus of the CPU if an input break
is

required.

Synchronizes the FPP12 time state generator to the particular CPU memory timing
is attached.

to which the peripheral

The synchronizing logic for the data break control

BREAK L requests the data break from the processor.

shown on print DBC1.
This signal

The signal DBC1 REQUEST

actuated by the condition:

(REQ BRK CYCLE (1) H) (BREAK (0) H)
The first term is the output of a flip-flop that permits the FPP12 to remember that it is currently requesting a data break.

The second term is the signal from the CPU that a break is not in progress.

Once the break cycle begins, noted by the disqualification of Break (0) H, the FPP12 break request
must be removed

In the

lower right-hand side of the DBC1 prints there is a signal DBC1

for this signa

ENAB DATA H.

is:

(BREAK (1)H) (DBC1 REQ BRK CYCLE (1) H) + CI2 MAINT READ L

3-10

The equation

The signal DBC1 ENAB DATA H permits the placing of data on the I/O bus during the break cycle
requested by the FPP12.

The DONE flip-flop, which is clocked by the trailing edge of ADDRESS

ACCEPT in the PDP-12 or the falling edge of BTS3 in the PDP-8, restarts the FPP12 timing chain.

A data break may be initiated by any of the function enables placing a low level on the input of three
sets of

OR gates found on DBC2.

These OR gates funnel break requests to the DBC1

REQ BRK CYCLE

flip-flop and choose which of three address registers to use for the break address.

A data break for the purpose of retrieving data from core memory is an OUTPUT BREAK. A data break
for the purpose of storing data in core memory is an INPUT

cremented an INCREMENT BREAK is performed.

BREAK.

If a

core memory location is in-

The FPP12 data source for INPUT BREAKS is selected

on DBC3.

There are four data sources used for INPUT BREAKS.

They are: the field bits of the APT, the operand

address register, the least significant word of the B multiplexer, and the most significant word of the

A multiplexer.
If the data

source selected for an INPUT BREAK is either the A or B multiplexer, an additional eight

possibilities exist.

The actual data source is resolved on prints RG7 through RG10.

There are several wiring changes specified for converting a positive bus FPPI2 logic to a negative bus
logic.

3.7

These changes are in Chapter 4 of this manual.

MODULES INTRODUCED IN THE FPP12

There were three etch boards and five new modules introduced for the FPP12.

The following list shows

the module number and the function of these modules.

Function

Module No.

M155

One of 16 decoders using 74154 IC decoders.

M190

4-bit arithmetic logic module using 74181 arithmetic logic unit
integrated circuit.

M191

M238

Two carry look-ahead 74182 ICs for the 74181
Two separate 4-bit synchronous binary up/down counters with
separate up and down clocks.

M245

Uses two 74193 ICs.

Two separate, 4-bit parallel-serial input, parallel serial output
shift registers.

Uses two 8271 ICs.

3-11

The M178 Digital Multiplexer, with 8 inputs for each of 6 outputs, is used in the FPP12 although this

module was originally built for a new PDP-10 processor.

The M191, M238, and M245 use a common

etch board, the 5008912, which is a mount for 2-16 pin dip packages with pin 16 reserved for +5V

The M155 is constructed on a 24-pin DIP mount, the 5008908.

and pin 8 reserved for ground.

The

M190 is a unique module layout containing 8 ICs including the 24-pin arithmetic logic unit.
Full specifications for new MSIs may be found in either the

DEC specification file or from the

The 74182, 74181, 74193, and 74154 ICs are listed in catalog number CC301

manufacturer's catalog.

by Texas Instruments Inc.

The 8271 and the 8291 (74197 from TI) are listed in Signatic's MSI

Specifications Handbook,

DCL Vol. II.

All five of the modules introduced with the FPP12 are tested on Digital Equipment Corporation's com-

puterized module tester.

3.8

FLOW DIAGRAMS

The flow diagrams are the key to troubleshooting the FPP12 logic.
diagrams,

In order to understand the flow

necessary to understand the timing generator and the register structure.

recom-

It is

mended that the reader thoroughly study Chapter 3, Paragraphs 3. 1-3.7 and Chapter 4 of this manual
before attempting to understand this section.

A brief review of the timing generator and the register structure is presented here.

The timing gen-

erator has the following properties:

1 .

There are 16 possible major time states.

These are named State 0 through State 15.

The timing generator can be forced to jump to any state; that is, if the timing genif the proper enables are gen-

erator is in State 3, the next state could be State 11

erated
3.

During the time a state is enabled, four different enabling pulses are generated; they are
These pulses occur sequentially and are one
1 through Mini State 4.
clock cycle long. The end of the major time state occurs at the end of Mini State 4 and
the next major time state is enabled at the trailing edge of the next clock cycle. When
called Mini State

a state

entered, the timing generator stops until

receives a timing advance.

the advance is enabled, the four mini states are generated.

cycle, Mini State 1

When

During an output break

used to enable the clocking of the data from the MB into the

appropriate register.

The characteristics of the M190 are important also in understanding the flow diagrams.

Recall that

there are three registers; the outputs of the A and the B registers are connected to the two inputs of
the

ALU, DEC 74181.

The output of the ALU is connected to the input of the O register.

and O registers each have unique properties.
plemented value of the inputs.

The A, B,

The A register can be loaded with the true or the com-

The B register is a shift register that can be shifted toward the least

3-12

significant bit; the
It is

O register

a shift register that can be shifted toward the most significant bit.

important to realize the many functions that the DEC74181 can perform.

The functions used in

the FPP12 are listed in Table 3-1, along with the enables that are required to perform the function.

Table 3-1
Functions Performed by DEC74181

Inhibit

Carry

A minus B - O

A plus B - O

A plus A -* O

A -O

A plus
Logical
B

-O

* O

-O

Logical 0 -

Note that the function B minus A cannot be performed.

In order to do this the I's complement must

be loaded in A, A plus B with a carry insert enabled, and the result loaded into O.

The following paragraphs contain a brief description of each of the flows.

INITIATE

3.8.1

The initiate flow diagram refers to the INITIATE major state.

INITIATE (1) H A

When the INITIATE flip-flop is set,

STATE 0 H generates an output data break request at the address selected by the

ADRS register. As with all enable states where a data break is requested, the timing generator is
advanced at the trailing edge of address accept.
mini states are generated.

When the timing generator is advanced, the four

The first mini state loads the data read from core (the first location of the

APT table) into the most significant 12 bits of the A register (AMSW) and into the field bits of the
appropriate address registers.

The second mini state increments the ADRS register so that it points to

the second location of the APT table.

Mini States 3 and 4 are not used in this case.

Mini State 4, State 0 is reset; at the trailing edge of the next clock cycle, State
(State

At the end of
generated.

H A ) (INITIATE (1) H) again requests an output data break at the address selected by the ADRS
The trailing edge of address accept will again advance the timing generator and produce

3-13

the four mini states.

In this

case, Mini State

significant 12 bits of the A register (ALSW).

used to load the data from memory into the least

Note that the least significant 15 bits of the A register

now contain the initial setting of the FPP12 program counter (FPC). During (STATE 1 A) (MINI STATE 2),
the contents of the A register are transferred to the
to point at the next location in the APT table.

significant 15 bits of the

O register, and the ADRS register

incremented

Mini State 3 is used to enable the transfer of the least

O register to the operand address register (OP ADDR) and the FPC

loaded

from the OP ADDR during Mini State 4.

All the other registers are conditionally loaded from the APT depending on the state of the appropriate

command register (refer to Table 1-3).

bit in the

In the

case where the register is not loaded from the

APT, the timing generator is advanced when the ENABLE state is entered and the only function performed during that time state is incrementing the ADRS register to the next location in the APT table.

At the end of the INITIATE cycle, the FETCH major state flip-flop is set, and the timing generator is
set to State 0.

3.8.2 FETCH

A block diagram of the FPP12 FETCH flows is shown in Figure 3-7. (FETCH (1) H A ) (STATE 0 H
an output data break request at the address specified by the FPC.

Mini State

)

generates

generates the enable

During

that causes the data read from core to be loaded info the FPP12 instruction register (FIR).

Mini State 1 , a 27_ is loaded in the A register and the exponent of the contents of the FPP12 accumu8
lator (FAC) is loaded in the B register. The difference is then loaded in the O register during Mini

The result that is stored in the O register is used only if a JAL instruction was fetched.

State 2.

this case, the

27Q

O register can be tested during Mini State 4 to see if the FAC exponent

greater than

This allows the JAL instruction to be treated the same as the other conditional jumps.

FIR3 = 0 and FIR4 = 0, the FIR is decoded in a different fashion from that of the data reference

instructions.

Each of these special instructions has a unique flow diagram.

The FIR and the FPP12

mode bit (CRO) determine which flow diagrams are pertinent.
a.

LDA (FLDA)

STR (FSTA)

D.P. ADD & SUB (FADD, FADDM, or FSUB & Double-Precision Mode)

ADD & SUB of F.P. NOS. (FADD, FADDM, or FSUB & Floating Point Mode)

MULTIPLY (FMUL or FMULM)

DIVIDE (FDIV)

3-14

DOUBLE WORD

FPC

BREAK

OFFSET 3
+PO ADD

0+1

BREAK
TWICE
FOR
OPADD

INBREAK

GET

X + BITS

INDEX

0 PADD

INDIRECT ADDR.

>FROM INOE

BREAK
FOR
SPECIAL

INSTRUCTION
TO PROCESS

CIX+XO)

DIRECT ADD.
SINGLE

WORD
TO

D.P

EXECUTE

INDEX + OPADD

—

OPADD

OPADD+0
TO EXECUTE

—•OPADD

Figure 3-7

3.8.3

Block Diagram of FPP12 FETCH Flow

DEPOSIT

At fhe end of any arithmetic calculation, the FPP12 normalizes and rounds off the result.
the calculation of fhe exponent of the result, this is done during the

Figure 3-8).

Along with

DEPOSIT major state (see

The DEPOSIT major state is enabled by causing the timing generator to jump to State 1 1.

When State 11 is enabled, the 0 register is shifted toward the most significant bit until the number is
normalized; this is indicated in the flows as 0 (N) 0 (N-l).
shifts required is tallied in the

The 2's complement of the number of

SHFT CNTR. When the number in the 0 register is normalized, the

timing generator is advanced and the four mini states are generated.

Normalization is performed by

the clock that is free running even when the timing generator is not running.

State 11 Mini State

clears the B register, loads the A register with the contents of the 0 register, and sets the CHECK FOR

FLO flip-flop if the number in the 0 register is positive.
off of the result.

State 11 Mini State 2 causes the rounding

The only case where overflow can occur is if the 0 register contained a 37777777

and the most significant bit of the 0 register extension was set.

Hence, if the 0 register is negative

after the rounding operation and the CHECK FOR FLO flip-flop is set, an overflow has occurred.

the FPP12 is in the double-precision mode, the overflow causes the FPP12 to exit.

If the

FPP12 is in

floating-point mode and the rounding causes an overflow, the contents of the 0 register are shifted
right one position and one

added to the exponent.

This is done during State 12 Mini State

and 2.

Since the 0 register cannot shift right, the contents of the 0 register are right-shifted through the
multiplexer and loaded into the B register.

The B register is then loaded info the 0 register and the

3-15

DOUBLE PRECISION

TEST
FOR
NORMALIZE

RESULT

GET

MEM

EXP

TEST
FOR

NORM

OVER

FLOW

FAC

DOUBLE PRECISION TO

(+SC)

NOT

NORM

0 (N) -*
0 N +1 )

0 (N)»

(

FPLNK*

O(N-I)
DEC SC

0(0)

BREAK

FRAC

0 -»MB

RESULT

YES
IN

BREAK

MEM

INC SC

-2048 < EXP<2047
DOUBLE

FETCH

PRECISION

EXP

OVERFLOW
TO

EXIT

EX IT

FPP DEPOSIT

Figure 3-8

Block Diagram of FPP12 DEPOSIT Flow

SHFT CNTR incremented. The mantissa of the result is now in the 0 register^ the number of left shifts
that was required to normalize the 0 register is contained in the SHFT CNTR.

State 13 is used to store the least significant half of the mantissa in memory, in the case of an
or FMULM instruction.
in the case of an
bits of the

During State 14, the most significant half of the 0 register is stored in memory

FADDM or FMULM instruction.

The 0 register is loaded into the least significant 24

FAC for all other instructions during State 14.

During State 14 of DEPOSIT, the value of

the exponent of the normalized and rounded result is calculated.
result

FADDM

assumed to be stored in the least significant 12 bits of the

except FMUL, FMULM, and FDIV.

The exponent of the un-normalized

MQ (MQLSW) for all instructions

In the case of these three instructions, note that there are still

two mini states (3 and 4) that can be used to generate enables so that the special instructions requiring
only two mini states can be completed during FETCH and State 0.

The other special instructions that

require more time states cause FETCH to be reset and the PROCESS major state to be set at the end of
State 0.

FIR3 =

or FIR4 = 1, the instruction is decoded as a data reference instruction.

In the case of a

double-word instruction (FIR3 = 1 and FIR4 = 0), States 1, 2, and 3 are skipped, and State 4 is enabled
after State 0.

The operand address or the location of the indirect address for single-word instructions

3-16

calculated during States 1 and 2, and the indirect address is fetched during States 3 and 4.

The

remaining time states in the FETCH cycle are used to modify the operand address with the contents of

an index register if any index modification has been specified.
instructions, the indirect address is stored temporarily in the

In the case of the single-word indirect

MQ (State 3 Mini State 2 and State 4

Mini State 1) and then loaded into the A register when it is required (State 7 Mini State 1).

There is also a flow diagram for each of the data reference instructions.

When the OP ADDR has been

set to the appropriate value, the FETCH flow diagram indicates a transfer to the

In this case, the

EXECUTE major state.

EXECUTE flip-flop is enabled and the timing generator returned to State 0. The in-

struction in the operand exponent is assumed to be stored in the MQLSW.

State 15 of DEPOSIT loads

the exponent of the normalized and rounded result in the appropriate register and checks the value of

the exponent to see if it is out of range; that is, less than 4000 or greater than 3777.

3.8.4 EXIT
The EXIT major state is discussed in detail in Paragraph 3.3.
pointing at the highest memory location in the APT.

After INITIATE, the ADRS register is

During EXIT, the active registers are loaded

into APT starting at the highest location and decreasing to the lowest.

The conditional trapping of an exponent underflow error is performed in the EXIT major state; that is,
all error conditions

including exponent underflow cause the EXIT major state to be set instead of the

FETCH major state. During EXIT State 0 the cause of the exit is checked to determine if it was an
exponent underflow.

If bit

of the command register is set, the usual exit routine is followed.

If,

on the other hand, bit 1 of the command register is not set, the FAC or the operand (for ADDM or

MULM) is set to 0 and the FETCH major state is set; this allows the program to proceed.

3.8.5

LDA and STR

The LDA flow diagram is executed during the EXECUTE major state of an FLDA instruction.

If the

FPP is in floating-point mode, the contents of the three sequential memory locations defined by the
contents of the OP ADRS register are loaded into the FAC.

In double-precision mode,

contents of two sequential memory locations are loaded in the FAC.

plemented during the EXECUTE major state of a FSTA instruction.

only the

The STR flow diagram is im-

In this case, the appropriate 12-bit

bytes of the FAC are stored in the memory locations defined by the OP ADRS register.

3.8.6

DP ADD and SUB

This flow diagram refers to the

EXECUTE state of an FADD, FADDM, or FSUB instruction, when the

FPP12 is in double-precision mode.

If the result is

greater than 37777777)

3-17

or less than 40000001)

the fraction overflow bit (bit 4 of the status register) is set and

the EXIT major state is enabled

causing the FPP12 to halt.

3.8.7 ADD/SUB of FP NOS
This flow diagram

implemented during the EXECUTE major state of an FADD, FADDM, or FSUB

instruction, when the FPP12

in floating-point mode.

In order to add or subtract two floating-point

numbers, the exponents must be aligned; that is, the fractional part of the

number with the smallest

exponent must be shifted right and the exponent incremented until the two

exponents are equal.

Since the A register cannot be shifted, the fraction of the number with

be loaded into the B register.

This is done in the following fashion.

the smallest exponent must

During State 0 Mini State 1

and 2 the difference between the FAC exponent and the operand exponent is
in 0.
is

The operand exponent is stored in the MQLSW for future reference.

calculated and stored

The sign of the difference

loaded into the
used to determine which exponent is larger and, hence, which fraction must be

The absolute value of the difference is also loaded into the SHFT CNTR

B register.

sequently used to determine the number of times the B register is shifted.

During State 0 Mini State 3

and 4, the number of shifts required is checked to determine if it is more than 27) g ;
fraction to be shifted will be completely shifted out of the B register.

which is sub-

that is,

the

The OVERSHFT flip-flop,

which is set during State 1 Mini State 2, is used to indicate that the required number

of shifts is

greater than 27)g.

State

and State 2 are used to fetch the most significant word of the operand fraction.

where the operand exponent is greater than the FAC exponent, the

of FSUB,

operand fraction is loaded into the A.

In the case

complement of the

This is necessary since the ALU cannot perform the operation

B minus A.

Before the B is shifted, the fraction of the number with the largest
register)

checked to make sure that it is nonzero.

exponent (which is stored in the A

This prevents the loss of significance when a

number with a nonzero exponent and a zero fraction is added to or subtracted from
If the

another number.

stored in the B register
fraction of the number with the largest exponent is zero, the fraction

loaded into the 0 register and its associated exponent is loaded into MQLSW

and the DEPOSIT

major state is enabled.

When State 3 is enabled, the B register is shifted toward the least significant bit. The number of
When shifting is completed, the
positions is determined by the number contained in the SHFT CNTR.
timing is advanced and Mini State
registers.
set the

used to perform the required operation between the A and B

the operation causes an overflow condition, adjust the fraction one bit

SHFT CNTR to 1.
3-18

position right and

At the end of State 3, the result of the addition or subtraction of the aligned fractions is stored in
the 0 register,

MQLSW contains the value of exponent of the aligned fractions, and SHFT CNTR

contains a 0 or contains a

in the case when the fraction of the result was shifted right.

The

DEPOSIT major state is entered to perform the normalization, rounding, exponent calculation, and
storage of the result.

3.8.8 MULTIPLY
The MULTIPLY flow diagram details the algorithm used by the FPP12 to perform floating-point and
double-precision multiplications.

The absolute values of the two fractions are multiplied together to

give a positive result which is negated if either but not both of the fractions are negative.
solute value of the operand fraction is loaded in the

The ab-

MQ during State 0 and State 1. If the FAC

fraction is negative, the complement is loaded in A and a CARRY INSERT is generated when A and B

are added during the multiply cycle so that the 2's complement of the FAC fraction is added to the

contents of the B register.

Each cycle of the algorithm requires

The multiplication of the two fractions is performed in State 2.

two clock pulses.

The first clock pulse is used to load A plus B into the O register and to decrement

the SHFT CNTR.

The second clock pulse loads the partial sum divided by 2 into the B register if the

23rd bit of the

in B is divided by two.

the 23rd bit of the

0, the previous partial sum that is contained

The second clock pulse also shifts the

MQ toward the least significant bit,

which brings the next binary bit of the multiplier into the 23rd position for testing on the next cycle.
The final product is stored in the B register.

The remaining time states used in MULTIPLY store the product in O and load the operand exponent
in the

MQLSW for use in the DEPOSIT cycle.

3.8.9

DIVIDE

The Divide algorithm used in the FPP12 is shown in the DIVIDE flow diagram.

Again, the divide

routine makes both the divisor and the dividend positive, calculates the quotient, and negates it if
either but not both of the divisor or the dividend was negative.

During State 0 and State 1, the FAC and the absolute value of the operand fraction are loaded into

A and the B registers, respectively.

During State 2, the division of the fractions occurs.

Again, like

the MULTIPLY algorithm, two clock cycles are required for a shift cycle of the divide algorithm.

Dur-

ing the first half of the cycle, the divisor is subtracted from the current remainder (which is stored in

the A register) and,

the result is positive

(CARRY OUT = 1), the difference is loaded into the

3-19

O register and a

shifted into the least significant bit of the

MQ.

During the second half of the

cycle, the new remainder is multiplied by two and stored in the A register.
shifted left so that the contents of the A and the

subtraction is negative (CARRY

O registers are the same.

The O register is also
If

the result of the trial

OUT = 0), a zero is shifted into the least significant bit of the MQ

and the current remainder, which is stored in both the O and the A registers, is multiplied by two.
This multiplication

done by shifting the O register.

The second half of the cycle then loads the

contents of

O register into the A register.

complete.

The remaining time states used in the divide routines load the

operand exponent into the MQLSW.

The 28-bit quotient is found in the

MQ when division

MQ into the O, and the

During State 2 Mini State 3, the quotient is divided by two

and a one is loaded into the shift counter if the first subtraction gave a positive result.

This will

occur if the dividend is greater than the divisor.

3.8.10 SPECIAL INSTRUCTIONS
The remaining flow diagrams are those associated with the instructions that use Special
and 3.

Four of these instructions (FEXIT,

FETCH State 0.
is

FCLA, STARTF, and STARTD) are performed completely in

All of the conditional jumps are also completed in

not true; that is,

if the

jump is not performed.

entered at the beginning of State 1 .

Format 1 , 2,

In all

FETCH State 0, if the condition

other cases, the PROCESS major state is

Table 3-2 shows the equivalence between the instruction mnemonic

and its corresponding flow diagram heading.

3.9

MAINTENANCE LOGIC

Maintenance logic, built into the FPP12, permits the CPU to examine, in detail, the operation of
the FPP12.

For instance, the CPU can issue IOTs that force the FPP12 to cease operation after every

major time state.

Other IOTs permit the CPU to examine internal registers in the FPP12.

Using these

tools, a diagnostic program can pinpoint the exact step in the flow charts in which the FPP12 fails.

This should isolate the failure to within one or two gates.

used to debug programs.

Diagnostic instructions can sometimes be

For instance, there is a maintenance instruction that reads the 12 least

program has more than one APT it can be desirable to deter-

significant bits of the APT pointer.

If a

mine which APT is currently in use.

This can be done by issuing the maintenance

IOT 6565 with the

AC clear.

A complete list of maintenance IOTs and their functions follows.
ORed into the AC when the maintenance mode IOTs are used.

3-20

Data from the FPP12 is inclusively

Octal Code

Mnemonic

6561

Enter Maintenance Mode

Function
a.

This

IOT is typically issued prior to FPST

to begin maintenance mode.

or Maintenance Step

6561 is issued when halted at the end of
a major time state to cause the advance
to the next time state.

Maintenance mode is cleared whenever
the FPP Interrupt Request flag is cleared.

6562

Read States

The current major time state and enable state
are ORed into the AC, according to Table 3-3.

6563

Read OMSW

OR the OMSW register into the AC.

6564

Read OLSW

OR the OLSW into the AC.

6565

Read APT

OR the least significant 12 bits of the APT
pointer into the AC.

6566

Read MQLSW

6567

Load Shift Counter

OR MQLSW into the AC.
Load the shift counter with the significant 6
bits of the AC.

Maintenance Instructions are detailed on print D-BS-FPP12-0-C12.

Table 3-2
Equivalence Between Instructions and Flow Routines

Instruction

Flow Diagrams

FEXIT
F PAUSE

EXT
PSK

FCLA

CLR

FNEG
FNDRM

NEG
NRM

STARTF

STF

STARTD

STD

JAC

RTN

ALN
ATX
XTA

FNOP

NOP's

LDX

ADDX

ADX

JEQ

J MPS

(Continued on next page)

3-21

Table 3-2 (Cont)

Equivalence Between Instructions and Flow Routines

Flow Diagram

Instruction

JMPS
JMPS
JMPS
JMPS
JMPS
JMPS
JMPS

JGE
JLE

JA
JNE
JLT

JGT
JAL
SETX

MUX

SETB

MVP

JSA

JSB

JSR

JMK
JXN

JXN

Table 3-3
Definition of AC

Bits After

IOT 6562 Read States

Function

Bit

Most significant bit of major time state counter

Bit

02
03

Bit 2 of major time state counter

04
05
06
07
08
09

CRN deposit flop (1) H
CNR fetch flop (1) H
CRN execute flop (1) H
CNR exit flop (1) H
CNR initiate flop (1) H
CNR process flop (1) H

AST0 shft FAC FRAC H

AST1 no shft (1) H

of major time state counter

Bit 3 of major time state counter

3-22

CHAPTER 4
FPP12 INSTALLATION

4.1

INSTALLATION

The Floating Point Processor is a standard PDP-8 type, data break I/O bus peripheral.

The FPP12 is

attached to positive bus computers with BC08B cables and to negative bus computers with BC08D
cables, according to drawing D-UA-FPP 12-0-0.
puters.

Standard FPP12 logics are wired for PDP-12 com-

PDP-8/L, PDP-8/E, PDP-8, and LINC-8 Computers

Slight wiring alterations for PDP-8/I,

are normally made as the units are checked out in the factory.
sion are shown in Tables 4-1 and 4-2.

It is

The wiring changes for field conver-

also necessary to exchange six modules when converting

the FPP12 from a positive to negative I/O bus.

These modules and their locations are shown in

Table 4-3.

4.2

AC POWER REQUIREMENTS

Typically, the FPP12 is shipped in a standard DEC 19-in. cabinet.

The AC power for the H721 Power

Supply is controlled through a H854 (H854B for 50 Hz) Power Control .
to the

This power control

connected

AC power with a line cord terminated in a Hubbell 30-amp twist-lock male plug.

Total power consumption for the FPP12 logic and power supply is

150W.

Table 4-1

PDP-8/L, PDP-8/I Positive Bus and PDP-8/E

Name

Add

Run

Delete

CI1 ADD ACC (1) L

D04D1

D30N1

EXT ENAB INT PAUSE H

F05U2

B03V2

CI1 BIS 05 (1) H

D30N1

A11T2

4-1

Table 4-2

PDP-8, LINC-8, and PDP-8/I with Negative Bus

Name

E01M2

A01H1

C01M2

X
X

C01M2

A10FI

C01N2
C01N2
C01N2
C01N2

E01N2
A10P2
E01N2

A10N1

E01P2
A10S1

F05U2

C01M2

CI1 IOP

cn iop h

C01P2
C01P2
C01P2
C01P2

E01P2

A10R1

X
X
X
X
X
X
Y
A
X
X
X

CIl INIT L

B31P2

A21D1

CI1 INIT H

B31P2

A21E1

All ADD ACC (1) L

A11V2

D04D1

D04D1
D04D1

D30N1
A11V2

D30N1

A11S2

CIl BTS 05 (1) L

Delete

B03V2

EXT ENAB INT PAUSE H
CI1 IOP

Add

Run

X
X

Table 4-3

Module Changes for Negative Bus Computers

Slot

Positive Bus Modules

Negative Bus Modules

B08

M101

Ml 00

M623

M633

M623

M633

M623

M633

D05

M623

M633

M101

Ml 00

M101

M100

M623

M633

F05

M623

M633

4-2

4.3

CHECK OUT

Diagnostic programs necessary for checking out the FPP12 are as follows:

FPP12 Instruction Test 1

MAINDEC-12-D0LA

FPP12 Instruction Test 2A

MAINDEC-12-D0MA

FPP12 Instruction Test 2B

MAINDEC-12-D0NA

FPP12 Instruction Test 2C

MAI N D EC- 1 2- DOO A

FPP12 Address Test

MAI N D EC- 1 2- DO PA

FPP12 Exerciser

MAINDEC-12-D0QA

These diagnostic programs should be run in accordance with instructions packed with the diagnostic

programs.

On the PDP-12 Computer, it is advisable to run the system program for Display Oriented

Research Analysis (DORA).

(AIPOS).

DORA is part of the Analytical Instrumentation Package Operating System

AIPOS and DORA will run on any PDP-12 Computer equipped with 8K of core memory, the

AD12 analog knobs, and the FPP12.

Instructions for the operation of

manual (DEC-12-SQ1A-D).

4-3

DORA are contained in a separate