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DEC-08-I8BA-D

December 1968

50 pages

Original

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Document:	DP01 Data Communications Channel 19
Order Number:	DEC-08-I8BA-D
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Pages:	50
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-08-i8b/dec-08-i8ba-d.pdf

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DEC-OS-ISBA—D

DATA COMMUNICATION

CHANNEL

DPO1A

INSTRUCTION
FOR

MANUAL

USE WITH

DIGITAL EOUIF’MENT CORPORATION

PDP—8

MAYNARD. MASSACHUSETTS

CONTENTS

Page
CHAPTER I
INTRODUCTION AND DESCRIPTION

Functional Description
Data Format

Specifications
‘CHAPTER 2
INSTALLATION

Mechanical Assembly

N_NI\>N

Cabling

2—1

Module Locations

2-2

Power

2-2

EIA Interface

2—2

CHAPTER 3

OPERATION
CHAPTER 4

PROGRAMMING
IOT Commands

CHAPTER 5
PRINCIPLES OF OPERATION

Logic Elements
o

IOT Selection Logic

—A

Skip and Priority Interrupt Logic

ummmmmm LZRLproLa'wbob

Receive Logic
—A

AQJN

Receive Buffer Register
Receive Shift Register

Sync Character Detector
V

Control

Logic

Transmit Logic
d

Abra

Transmit Buffer Register and Gating
Transmit Shift Register

Sync Character Detector
Last Bit Detector

.0.

III

CONTENTS (Cont)

Control Logic
—d

EIA RS-232B Interface

Sequence of Operation
Receiving Channel

mmwmmmmmmmwwmwmwbmwbm
O~O~O~O~O~O~ #Aww

Starting Condition
Receive Active

\IO‘U‘I-lho.>l\J—'k
d

NNN U1-kCAJN

Sentinel Bit

Input to Computer
Next Character
Receive in Progress Delay
Receive End Flag

Transmitting Channel
Starting Condition

5-12

First Character

5-12

Successive Data Characters

5—12

Ending Message (Not Idle Mode)

5—13

Ending Message (Idle Mode)

5-13

Exclusive OR Buffer (Optional)

5—13

CHAPTER 6
MAINTENANCE

Diagnostics

6-1

Marginal Checks

6—1

Adiustments

6-1

Adiusting One-Shot Delays

6-1

Corrective Maintenance

6-2

Diagnostic Testing

6-2

CHAPTER 7
ENGINEERING DRAWINGS AND GLOSSARY

Engineering Drawings

Signal Glossary

7-3
.

ILLUSTRATIONS
1-1

DPOIA Synchronous Data Channel

1—2

1 -2

DPOIA Serial Message Format (9-Bit Characters)

1-3

2-1

DPOIA Physical

2-1

5-1

DPOIA Data Flow

5-2

DPOIA Receiving Channel Timing

5-7

5—3

Receive Logic Detailed Flow Chart

5-8

5—4

DPOIA Transmitting Channel Timing

5—1 0

5-5

Transmit Logic, Detailed Flow Chart

5-1 I

6-1

Connections for Diagnostic Testing Using .Maindec-O8-D8FA

6-3

Layout

TABLES
Reference Documents

1—1

DPOIA Summary of Specifications

1-3

Logic Diagram and Schematic Index

CHAPTER I

INTRODUCTION AND DESCRIPTION

This manual provides general information,

installation, operation, programming, maintenance,

and technical reference data for the DPOIA Bit Synchronous Data Communication Channel manufactured

by Digital Equipment Corporation, Maynard, Massachusetts.
The DPOIA is an interface between the PDP-8 computer and a full-duplex serial asynchronous
modem communication link having interface characteristics

compatible with Electronics Industries Asso-

ciation (EIA) Standard RS-232B.

The DPOIA consists of two basic assemblies, a control section and a computer interface section.

The Type 637 control section performs serial-to-parallel and parallel-to-serial conversion and

The interface section adapts the 637 to the input/output bus of the PDP-8 computer.

data set control.

(With another interface, the 637 can also be used with other computers.)

An XOR option adds a nOn-memory reference XOR command to the PDP-8,

cial character detection and longitudinal message parity generation.

facilitate spe-

‘

Other publications that contain information pertinent to the DPOIA or related equipment are
listed in Table 1-]

Table I—I
Reference Documents

Title

Document Number

Digital Logic Handbook

C-l05
F-85

PDP-8 User Handbook
‘

F-87

PDP-8 Maintenance Manual

RS-232B*

EIA Standard:

Interface between Data Processing Terminal

Equipment and Data Communication Equipment
Maindec-08-D8KA-D
Maindec-08-D8FA-D

DPOIA IOT and Data Test
DPOIA Bit Synchronous Data Communication System IOT
and Data Test

*Published by Engineering Department, Electronic Industries Association.

I .I

FUNCTIONAL DESCRIPTION
The DPOIA (Figure I-l) consists of two independent serial channels controlled by programmed

IOT instructions from the PDP-8, and synchronized by timing pulse streams from the associated data set.

(Timing can optionally be generated within the DPOIA.)

I-I

guzsgg
U

l—

TRANSMITTED DATA

I/O
BUS

OUTPUT
SHIFT
REG.

CONTROL
POP-8
COMPUTER

COMPUTER

EIA
INTERFACE

INTERFACE

RECEIVED DATA

I
DATA
SET

INPUT
SHIFT
REG

‘9

CONTROL AND TIMING
INPUT

BUFFER

‘

XOR
BUFFER
(OPTION)

"I
l

Figure 1-]

DPOlA Synchronous Data Channel

Output characters are transferred in parallel from the computer to a buffer register, then

serially shifted to the data set communication terminal. 'Input characters from the data set are shifted
into a register, transferred to a buffer register, and made available to the PDP-8 on an interrupt basis.

Double buffering, both on input and output, allows a full character time in which to coordinate the
program and the real-time data.

Control of the communication terminal is also through programmed

IOT commands.

Synchronization between the DPOlA and the distant data set is established by a sync character
code.

Once a sync character is detected, a receiving channel assembles every 6, 7, 8, or 9 successive

bits to form a character.

Data Format

Serial data is transmitted and received continuously once synchronization is achieved.

The

transmission format consists of sync characters (three in succession are recommended) followed by the

characters which make up the text of the message.

Character lengths of 6, 7, 8, or 9 bits are selected

by a prewired patch plug, to allow the DPOlA to communicate with remote sites at various word lengths.
Sync characters provide a time reference at the start of every message to enable a receiving terminal to
determine which successive bits in the incoming serial stream make up each character.

When a receiving

terminal recognizes a sync character, it assembles every Nth bit in a buffer (N=6, 7, 8, or 9).
characters employed by the DPOlA are:

Sync

Sync Characters

Bits Per Character

010

O 010

TO 010

010

A brief message using 9-bit characters is illustrated in Figure l-2.

SERIAL
DATA

Figure l-2

1.2

DPOlA Serial Message Format (9-Bit Characters)

SPECIFICATIONS

Specifications for the DPOlA are summarized in Table l-Z.

Table 1-2
DPOlA Summary of Specifications

Type of Channel

Serial synchronous, half or full duplex

Speed

Up to 50,000 baud

Interface

Conforms to EIA Standard RS-232B

'Data Format

6, 7, 8, or 9-bit serial characters selected by prewired plug-in connector; unique sync character code
for each character length; least significant bit is

transmitted first.

Compatible Data Sets

Type

Speed (Baud)
2K

Bell

201A

Bell
Bell

2013

2400

205B

600, lZOO, l8OO

1-3

Table 1-2 (cont)
DPOiA Summary of Specifications

Compatible Data Sefs (cont)

Speed (Baud)

Type
7

Rixon

Lenkurf

FM—12
Sebif 48
TDM Series
26C

1-4

1200
4800

2400
150-2400

CHAPTER 2

INSTALLATION

MECHANICAL ASSEMBLY

2.I

The DPOIA logic is divided into a control section and an interface section, each occupying
one

Type I943 standard DEC mounting panel (see Figure 2-I).

The

logic mounting panels may be inI

stalled in any standard I9-in. rack assembly, such as the DEC CAB-3 option cabinet.

BIT LENGTH
SELECTION
CONNECTOR
,

10—1/2"

POP-8

INTERFACE

WIRING
SIDE

Figure 2-I

2.1.1

DPOIA Physical Layout

Cabling‘
The control and interface panels are connected together and to the computer I/O bus by plug-

in ribbon cables, For installation flexibility.

Additional connector sockets are provided For extension of
L

the I/O bus to other options.

Connections to the associated data set are through a 25-ft interconnecting cable terminated

by a Cinch or Cannon DB-I9604—432 (DBZ5-P) hooded connector.
System cabling is shown in drawing number D-IC-637—0-I2 in Chapter 7 of this manual.

2-I

2 l .2
.

Module Locations
Connector slot assignments for logic and cable modules are shown on the Module Utilization

Diagra'ms, drawing numbers D-MU-637-0-8 and D-MU-637-0-l l supplied in Chapter 7.
,

2.2

POWER
The DPOlA usually obtains dc power directly from the +10 and —l5V power supplies of the

PDP-8.

(In most PDP-8 systems the existing power supplies have adequate reserve power to Operate the

DPOlA without an additional power source.) Current demand, for system planning purposes, is as follows.

Power Supply Current

+lOV
2.24A‘

-I5V
105 mA

2.3

EIA INTERFACE

The DPOlA EIA Line Interface shown in drawing number D-BS-637-0-3 (Chapter 7) consists of

level-conversion modules and an interconnecting cable for direct connection to a data set.

Characteris-

tics of the interface signals are summarized below.

Request to Send

This signal is under control of the DPOlA.

It is turned ON when the first

sync character of a message is loaded and is held ON throughout transmission.

mission is completed, this output is turned OFF under program control.

When trans-

The SERIAL CLOCK

TRANSMIT signal must be available from the data set in order to turn this line on or off.

Transmitted Data

Serial data is presented to the data set on this output.

A positive polarity

(+6V) represents a binary 0, or space, and a negative polarity (-6V) represents a binary l, or
mark.

Between transmissions, the line is held in the marking (-6V) condition.

Local Timing
DPOlA.

This optional output is used only when data set timing is supplied from the

The output is obtained from a R405 crystal clock module.

Data Terminal Ready

This output controls connection of the data set signal converter to the

communication channel.

Serial Clock Transmit

(For a detailed description refer to EIA STD RS-23ZB.)

This square wave signal from the data set synchronizes DPOlA output

data with the data set transmitter timing.

When DPOIA internal timing is used, the LOCAL

TIMING signal is returned to the DPOIA, under data set control as SERIAL CLOCK TRANSMIT.

2-2

Serial Clock Receive

This square wave signal From the data set is similar to the SERIAL

CLOCK TRANSMIT signal, but is synchronized with the data set receiver timing circuits.
Data Set Ready
ceive data.

This input is ON at all times when the data set is prepared to send or re-

When OFF, the line indicates that the data set is not in an operative condition.

Clear to Send
state.

This input is OFF when the data set is activated but not in the transmitting

The line turns ON approximately 150 ms after the DPOTA generates a REQUEST TO

SEND signal.

(During this delay, a line echo suppressor operates and the distant receiver

establishes carrier synchronization.)
Received Data

Incoming serial data From the data set is received by the DPOlA at this input.

A positive polarity indicates a binary 0, negative polarity a binary 1.

Ring Indicator

When ON, this input indicates that a ringing signal is being received by the

data set from a remote station

2—3

CHAPTER 3
OPERATION

The DPOlA has no operating controls except the marginal check switches described in

Chapter 6. Operation is automatic, under control of the PDP-8 program and the timing signals From
the associated data set.
The only other operator Function is installing a character-length-selection connector in the

receptacle on a bracket at the right side of the control logic assembly.

Connectors For 6, 7, 8, and

9-bit characters are supplied with the equipment and are labeled accordingly.
in drawing number D-AR-637-O—9.

Wiring details are shown

CHAPTER 4
PROGRAMMING

4.]

IOT COMMANDS

The Following IOT commands are assigned to the DPOlA.

Instruction

Skip on Transmit Flag (STF)

Octal Code

Description

V66”

Causes the program to skip the next instruction
if the Transmit Flag is in the 0 state.

When the

Transmit Flag is in the I state, the transmit buffer register is ready to accept another character.

Clear Transmit Flag (CTF)

[/6602

Resets the Transmit Flag.

It Transmit Active

Flag is not set, CTF also causes the program to
skip the next instruction.
Transmit a Character (TAC)

t/‘ééOI

Causes the contents of the PDP-8 accumulator
(6,7,8, or 9 bits right-iustified) to be transferred into the transmit buffer register.

Clear Idle Mode (CIM)

M6604

Resets the transmit logic Idle Mode flip-Flop.

Set Idle Mode (SIM)

V6614

Sets the transmit Idle Mode

Skip on Receive Flag (SRF)

665 l

flip-flop.

Causes the program to skip the next instruction
if the Receive Flag is not set.

(The Receive
Flag is set when the first incoming sync character is detected, and stays set untilthe Receive

End Flag is set.)

Read Receive Buffer (RRB)

#5612

Transfers the contents of the Receive Butter (6,

7, 8, or 9 bits right-iustified) to the PDP-8 accumulator.

Skip on Receive End Flag (SEF)

V6621

RRB also resets the Receive Flag.

Causes the program to skip the next instruction
if the Receive End Flag is not set.

(The Receive
logic

End Flag Flip—Flop is set when the receive

has stopped receiving serial data from the communications equipment due to termination of the

SERIAL CLOCK RECEIVE pulse train.)

Clear End Flag (CEF)

é"6622

Set Ring Enable (SRE)

M6624

Resets the Receive End Flag.
Set the Ring Enable flip-Flop which permits the

Ring Flag to request a program interrupt.
Clear Ring Enable (CRE)

M6644

Resets the Ring Enable Flip-flop.

Instruction

Skip

Ring Indicator (SRI)

Octal Code

iss’i663l

Description
Causes the program to skip the next instruction
if the Ring Flag is not set.

The Ring Flag is set
when a RING input is received from the data
set.

Clear Ring Flag (CRF)

“6632

Resets the Ring Flag.

Set Terminal Ready (STR)

L.»7'"6634

Sets 'the Terminal Ready flip-flop.

(See descrip-

tion of DATA TERMINAL READY interface

signal.)
Clear Terminal Ready (CTR)

a..&""”6642

Resets the Terminal Ready flip-flop.

Skip on Data Set Ready (SSR)

V/664l

Causes the program to skip the next instruction

if the communications equipment is in the

"ready" state. (See description of the DATA
SET READY interface line.)

Clear Receiver Active (CRA)

6652

Resets the Receive Active flip-flop,

taking the
No
"active"
state.
logic
more incoming characters are transferred to the
receive buffer register until another sync charreceive

out of the

acter is detected

‘

The following commands pertain to the Exclusive OR Buffer Option only.

Clear XOR Buffer (COB)

666i

Clears the Exclusive OR Buffer.

Inclusive OR Buffer (IOB)

6664

Transfers ls from the AC to the buffer register.

Read OR Buffer (ROB)

6662

Transfers the buffer register content to the input
mixers of the PDP—8 accumulator.

Exclusive OR Buffer (XOB)

6654

Causes an Exclusive OR of the AC with the

buffer register.

CHAPTER 5
PRINCIPLES OF OPERATION

A simplified block diagram of the DPOIA appears in Figure 5-l
of a computer interface,

The system consists basically

input and output character assembly logic, and an EIA interface section.

The computer interface operates from the PDP computer I/O bus, responding to programmed
IOT instructions assigned to the DPOI

System.

The IOT instructions transfer parallel data to and from

the character assembly logic, set or reset control circuits, and test control flags for a skip condition.

Output data is transferred from the computer accumulator to a buffer register and then, under
control of data-set timing signals, transferred to a shift register and shifted serially to the data set.

The

input circuits operate in reverse, assembling serial data from the data set until the shift register contains
a

complete character.‘ The character is then transferred to a buffer register and held until it can be read

by the computer.
The EIA interface section converts data and control levels from DEC logic levels to signals

conforming to EIA Specification RS-23ZB.

5.]

LOGIC ELEMENTS

5.1.]

IOT Selection

Logic

IOT commands from the PDP-8 or 8/5 are interpreted by the WIO3 IOT selector modules shown
in drawing number D-BS-637—O-I3.

The W103 outputs are identified by the instruction's octal code.

R107 inverters distribute decoded outputs to the communications control logic through interconnecting

cables.

The R107 outputs are identified by the instruction's mnemonic code.
Additional inverters are provided in the communications logic to supply the opposite polarity

of all the IOT command pulses.

These are shown on drawing number D-BS-637-0-4.

The read-in gates that transfer assembled input characters to the computer's AC are shown on

the same drawing.

IOT 6612 (RRB) strobes the receive buffer register content to the computer IM 3-H

lines through the interconnecting cable.

5.1.2

Skip and Priority Interrupt Logic
The gates that generate the SKIP and PI signals to the computer are shown in drawing number

D-BS-637-0-4.

A priority interrupt request is produced under the following conditions.

Receive Flag is set

Receive End Flag is set

5-]

CONNECTORS
OTHER

DEVICES

COMPUTER

INTERFACE

LOGIC

DATA
y“

PDP-B
COMPUTER

NC BUS

I—

BMB 3-8

)

INVERTER:

IOP1.2,4

OEVICE
SELECTORS

IM11—3

READ-IN

CONTROL

LOGIC

.__.I

K—-———>

AND

DECODED IOT COMMANDS (TAC , ETC.)

INVERTERS

lRRB
I

RCBI-S

GATES

@ACII-s

Z‘S

OBI-9
(CHR—oTCBI

LPow CLEAR
LPI

CONTROL

TRANSMIT

OONTROL
SIGNALS

\SKP‘

SHIFT

‘

BUFFER

3mg

GA E

R08

TRANSw; i;
TRANSMIT

OUTPUT

ACTIVE (1 I

GATE

BUFFER
OB 0-H

REQ

X03

TBIU)

EIA

$(RB—DRCB)

-. TB)

WORD LENGTH
SELECTION

REQ
Q.—

(PLUG—IN)

RECEIVE
<I——-—-———-—

‘

(OPTIONAL)

DATA

SET

I
J

Figure 5-I

DPOIA Do’rOI Flow

RB I-9

INTERFACE

EXCLUSIVE
0R BUFFER
IOB

SHIFT

RECEIVE
DATA (0)

ACTIVE

xoe

BUFFER

SHIFT RB

H FT

xoe
103
R08

RECEIVE

Rem—9

TCB 1-9

INTERCON NECTING
CABLE

REG.

Transmit Flag is set

Ring Flag is set when the Ring Enable flip-flop is also set
The PI line is inverted on drawing number D-BS-637—0-I3 and the resulting signal is ORed to the PDP-8
INTERRUPT line.
‘

When the SKIP logic produces a negative pulse during one of the six assigned I/O

skip in-

structions, the computer's program is incremented so that the program skips the next instruction.
the STF instruction, for example, if the transmit flag is reset, a SKIP pulse is generated.

During

If the transmit

flag is set during the STF, no SKIP pulse occurs; the program executes the next instruction. The other

skip instructions Operate in the same way.
The negative SKIP pulse is inverted and ORed to the PDP—8 SKIP line.

5 I .3

Receive Logic

The receive logic on drawing number D-BS-637-0—I consists of the receive buffer register

(RCB I-9), the receive shift register (RB I-9), a sync character detector, and the control logic that
determines the receive timing sequence.

5 .I .3.I

Receive Buffer Register

The RCB register stores assembled characters from the RB register

until they can be sampled by the computer.

Each character is iam-transferred in by the RB

—-+

RCB

pulse. Sampling is performed by the RRB instruction, through gating logic in the computer interface
section of the DPOIA.

All nine bits of the register are transferred to the computers AC input lines,

regardless of the selected character length:
RCB Register Bit

Computer Input Bit
II

l
3

Characters having fewer than nine bits are right-justified by the character assembly cycle.

5 .I .3.2

Receive Shift Register

This register continually assembles serial data from the data set.

When a sync character is detected, a I is set into the input stage of the register and shifting continues

until the I is present in stage RBI

After one more shift, a fully assembled character is transferred to

the RCB register and another I is set into the input stage.
manner

are

as long

Input character assembly continues in this

the RECEIVE CLOCK input from the data set triggers the SHIFT RB pulses.

shifted into the RB register least significant bit first.

5-3

Characters

The register is of variable length, depending on the number of bits per character in the
In the 9-bit connection, the RECEIVE DATA (0) line drives a pair of pulse

assigned message format.

amplifiers which iam the data bit into shift register stage RB9 by collector pulldown.

The register is

shifted toward RBl and a new bit is entered into RB9 during every SHIFT RB pulse.

5. l .3.3

SJ/nc Character Detector

tect the sync

An expanded R] H NAND gate, is connected as a decoder to de-

character appropriate to the selected character length

Bits RB8 and RB9 are patched to

the decoder so that the sync character is detected as it appears shifted one place left.

the 9-bit sync character (OlO 010

HO) is detected as lOO

TO]

For example,

100.

In systems using half-duplex 4-wire operation, the TRANSMIT ACTIVEU) level inhibits sync

character detection, and thus prevents setting of the Receive Active state, when the Transmit Active
mode is in effect.

Furthermore, systems using 2-wire transmission will terminate with a Receive End

Flag.

5.l .3.4

Control Logic

Operation of the control flip-flops and logic gating are discussed later in the

description of the receiving sequence of operation.

5 l .4
.

Transmit Logic

The transmit logic on drawing number D-BS-637-O-2 consists of the transmit buffer register
and data gating, the transmit shift register, a sync character decoder,
and the control

5. l .4.l

logic that determines the transmit operating sequence.

Transmit Buffer Register and Gating

The TCB register stores parallel characters from the

computer until the transmit shift register is ready for another character.
in

by the CHR

"last bit transmitted" detector,

Each character is iam-transferred

TCB pulse during a TAC instruction.

The input gating preceding the register employs Rl07 inverters which provide both polarities
of the computer data to permit iam transfer without resetting thenTCB register.
are

identical to the computer BAC output bus lines except for numbering.

puter accumulator as follows.

Computer Output Bit

DB Line
l

1 l
'

The data lines (DB 1-9)

Data is gated from the com-

5. l .4.2

Transmit Shift Register

This variable-length register shifts data characters to the data-set

TRANSMITTED DATA line when the Transmit Active condition is in effect.

The number of stages is

matched to the selected character length by the plug-in bit-length selection connector. Shown in broken lines on the print are the connections for a 9-bit character.

When data is transferred in from

The END bit synchronizes the demand for new characters.

the TCB register by TCB

-D

TB, a l is set into the END stage. Each subsequent SHIFT TB pulse shifts

the character and END bit toward TBI , and shifts 05 into the END bit.

5. I -._4.3

Slnc Character Detector

The decoder at the lower right of drawing number D-BS-637-0-2

monitors the contents of the TCB register during a TAC instruction

The TCB

SYNC CHR signal is at

ground when the TCB register contains a sync character appropriate to the selected character length.

5. I .4.4

Last Bit Detector

Another decoder at the upper right of drawing number D-BS-637—0-2 mon-

itors the contents of the TB register and produced the LAST BIT TRANSMITTED signal when TB3 through 9

and the END bit are all Os.

This condition occurs at the beginning of a transmission after the register

has been cleared, or after the END bit has been shifted to TB2.

5.1.4.5

Control Logic

Control flip-fl0ps and logic gates on drawing numbers D—BS-637-0—2 and

D-BS-637-0-3 develop the enabling conditions and strobe pulses that set up the transmission sequence

These signals are discussed in the following description of sequential operation.

5 .I .5

EIA RS-232B Interface

Signals exchanged with the associated data set or communication equipment are converted
from standard DEC logic levels of 0 and -3V to voltages conforming to Electronics Industries Association

(EIA) Standard RS-23ZB.
than -3V.

EIA interface signals are voltages more positive than +3V and more negative

They are interpreted as follows.
.

Data Circuits

Control Circuits

Mark (I)

OFF

Polarity
-

Space (0)

Timing inputs and the RING signal from the data set are shaped by W501 Schmitt Triggers
before being distributed to the communications control logic.

The SERIAL CLOCK RECEIVE and SERIAL

CLOCK TRANSMIT inputs are converted to standard positive pulses producing Receive and Transmit

clocks, as shown on drawing D-BS-637—O-3.
Shown on the same drawing are some of the flag flip-flops associated with the data set control
lines.

Functions of these signals are summarized in Chapter 2.

5.2

SEQUENCEVOF OPERATION

5 .2 .1

Receiving Channel
A detailed timing chart of a receive sequence, showing the important logic states during

reception of a sync character and two data characters consisting of alternate ls and Os, appears in
Figure 5-2. A detailed flow chart appears in Figure 5-3.
Serial data on the RECEIVED DATA line is continually assembled in a shift register under
control of the SERIAL CLOCK RECEIVE pulse stream from the data set.

When a sync character is de-

tected, a sentinel bit is set in the most significant bit of the receiving shift register. The next incoming
character is fully assembled when the sentinel bit is shifted out of the least significant stage.
time the assembled character is transferred to the receive buffer register,

At that

program interrupt request is

generated, and a new sentinel bit is inserted into the shift register M53. The program responds to the
interrupt request with an instruction which loads the assembled character into the computer's accumulator.

This sequence is repeated for every character until the data set clock stops.

5 .2. l .l

Starting Condition

The INI signal, derived from the computer power clear generated during

power on, clears the status flip-flops indicated on the flow chart.

Thereafter, events are under control

of the SERIAL CLOCK RECEIVE line from the data set, which develops the SHIFT RB pulses.

5.2. l .2

Receive Active

SHIFT RB pulses enter serial data from the data set's RECEIVE DATA line

into the most significant stage of the RB register.

pulse sets the REC ACTIVE flip-flop.
puter by enabling the RB

-’

Once a sync character is detected, the next shift

This flip-flop enables transfer of assembled characters to the com-

RCB pulse discussed later.

The flip-flop is reset either when the RECEIVE

IN PROGRESS delay times out or when a CRA instruction is delivered by the computer.

5.2.l .3
a

Sentinel Bit

When the REC ACTIVE flip-flop is set after sync character detection, it triggers

pulse amplifier which resets the RB register (wiping out the sync character).

The RB register reset pulse

also triggers a

pulse which is patched through the bit—length selection connector to force the shift regis-

ter input stage

(RB9 for a 9-bit character) to the l condition.

This acts as a sentinel bit; a complete

character will be present in the RB register when this bit is shifted out of RBI

5-6

PWR CLR

ism“
CRE

RING ENABLE

RING

TERM

SEND

REC

['9

RING

FLAG

RDY

SET ROY

DATA

ELI—L

REG

DATA

I
IcRF

____[STR

CTR

___l

7____

I I I

amw

JILLIH

SHIFTRB

I I I I I I I

I I I I I I I I I I I I I I I I I I I I I

—> RC8

ACTIVE

o—uza

REC

I._.______

FLAG

I I

RRB

REC IN PROG

WILL

GENERATE

WILL

GENERATE

END FLAG

‘

l—b R89

(9-BIT

I I

RB-SYNC

REC

TRIGGERS A DELAY
TO MARK THE
RECEIVE DATA LINE

_____I

CHAR)

Figure‘5-2

DPOIA Receiving Channel Timing

CEF

POWER
CLEAR
IINI)

O‘REC
O‘REC
O’REC
O‘REC

FLAG
ACTIVE
AND
FLAG
TERM READY

‘

RECEIVE
ACTNE

I———d
®<——~
0
.—...

RECEIVE

CLOCK
TIME

__________

’I

[—

400
uszc
DELAY

FLAG
l—‘REC
I NTERRUPT
A

RECEIVE
CLOCK

AVAIL’fBLE

'_.____1
p.—

’’’’’’

I CRA

o—baac ACTIVE

lSRF

l
._

l
__J

I
I

l
I
0—9 REC acme
I—->REC
END

______

__l

‘l

FLAG

.mE

___________

Figure 5-3

5.2.1.4

Input to Computer

Receive Logic Detailed Flow Chart

Once the sentinel bit is detected in RBI , the RB

erated, after a 1 ps delay. The RB

-’

RCB pulse is gen-

RCB pulse transfers the assembled character to the RCB buffer

(See

drawing number D-BS-637-0-4.) The program normally responds with an SRF instruction to test whether
it is the Receive Flag that is interrupting.

Since the test is for "receive flag not set", the program pro-

ceeds to the next instruction, normally a iump to a subroutine that handles received data.

As a minimum,

the subroutine must read the buffered character with an RRB instruction, which also resets the REC FLAG

flip~flop and turns off the interrupt.

5-8

Next Character

5.2. l .5

During the interrupt, character assembly continues in the shift register while

the previous character is stored in the buffer register.

Each RB

chain which enters a new sentinel bit in the RB input stage.
RB

-9

RCB pulse also triggers the logic

After the sentinel bit is shifted to RBI,

RCB is again generated, an interrupt request is made, and the cycle repeats.

A character is lost

if the program fails to read it before the next character is ready, but assembly continues without in-

terruption

5.2. l .6

Receive in Progress Delay

PROGRESS delay from recovering.
the

delay unit

recovers

As long as SHIFT RB pulses occur, they prevent the RECEIVE IN

If the shift pulses st0p for more than the delay period (l-l/2 bit time),

and the RECEIVE IN PROGRESS line steps to ground.

frequently used baud rates are shown'on drawing number D-BS-637-O-l
Until a sync character is received, timeout has no effect.

Delays for the three most

Thereafter, a timeout resets the REC

ACTIVE. flip—fl0p and stops character transfer to the computer until another sync character is detected.

5.2. l .7

Receive End Flag

When the data set receive clock stops long enough for the RECEIVE IN

PROGRESS delay to time out (l-l/2 bit time), the REC END FLAG flip-flop is set, causing a program

interrupt request. The condition of the flip-flop can be tested by an SEF instruction and reset by a CEF
instruction

5 .2.2

Transmitting Channel
A detailed timing chart of a short message transmission appears in Figure 5-4.

A detailed

flow chart appears in Figure 5-5.
The DPOlA transmit logic enters the "transmit active" mode when the program loads a sync
character for transmission.

Thereafter, the character is shifted out on the TRANSMITTED DATA line

under control of the data set SERIAL CLOCK TRANSMIT pulse stream.

Since the DPOlA operates in a bit synchronous mode, data must be made available for transmission as it is needed, since every N bits are assembled to form a character.

dropped bit will cause faulty character assembly at the receiving station

Even an extra bit or a

The DPOIA safeguards against

interruptions in the character pattern by double buffering and by program interrupt requests for new
characters.
In the normal "transmit active" mode of operation automatically selected by the first sync

character of a new transmission, the DPOlA will stop transmitting (hold the TRANSMITTED DATA line
in the binary I

condition) if a new character is not available for transmission.

idle" mode can also be set up by the program.

An alternate ”transmit

In the transmit idle mode, when a new character is not

5-9

PWR CLR

START

CRE
RING ENABLE

5R5

SRE

RING

DATA

I I

FLAG

TERM RDY

SET RDY

SER CLK

XMT

CLK

SHIFT

RING

CRF

WHEN ENABLED
wILL INTERRUPT

me -> T8

CH"

TCB

ANS. To RING

S“

CLEAR CHAR FLAG—
SET TRANS FLAG

TAC

ANSI T0 TERM RDY

SETS

TAC

CHAR FLAG

TCB = SYNC

SEND REG

OI'S

REO

SEND

CLR

SEND

I
ANS. TO REQ
TO SEND

‘

—-—-;
CHAR FLAG

TRANS

ACTIVE

LAST

o—sooms

f—J

—__I

________—_I

I_____.
I

J
,

TRANS

I ICTF

FLAG

CTF

ACTIVE TB
I

YES
SRE

CAUSE

STR

22%

YES

TAo
IN

SYNC

Figure 5-4

I—-.

YES
we

DATA
I

TAD
IN
DATA

I—- E‘T‘E

DPOIA Transmitting Channel Timing

I
5

YES

INTERRUPT

POWER CLEAR

(XNI)

l
WAIT
FOR TAc

0—>TB 1—9
0—>TRANS FLAG.
TRANS ACTIVE.

DATA SET
STATUS AND
TIMING

CHR FLAG,
IDLE MDDE.
—

REG TO SEND.
SEND REO.
TERM READY.

‘-

FAG

LOCAL TIMING,

CHR—> TCB

RING ENABLE.
RING FLAG

—____J

DATA
SET
READY

1 —->
CHAR FLAG

TAC RECEIVED
BEFORE TRANS
CLOCK

YES

TRANS
ACTIVE

YES

TCB=
SYNC CHAR
?

1——>
SEND REO

1-—>

TRANS ACTIVE
>

._____l
0—»
REOTO SEND

TRANSMIT
CLOCK

—>

REO TO SEND

LAST BIT
TRANSMITTED

YES

TRANSMIT
CLOCK

1—. TRANS FLAG

0—> CHR FLAG
1—>P1

_——u——_

STF

L________l

Figure 5-5

Transmit Logic, Detailed Flow Chart

5-H

aV'ailable, communication with the distant terminal is maintained by repeating an idle character (the
last character that was transmitted).

The idle mode is desirable in applications that require a relatively

long time to establish transmission.

5.2.2.]

Starting Condition

After a power clear pulse from the PDP-8 (INI), the transmit logic is in the

condition shown at the upper left of the detailed flow chart.
or

reset

The IDLE MODE flip-flop can be either set

by the program.
Because the REQ TO SEND flip-flop is reset, the data set holds the CLEAR TO SEND line

OFF.

As a result, the TRANSMIT CLOCK is blocked and no shift pulses are generated.

TRANS ACTIVE flip-flop is also reset, the transmit data line

permanent mark condition

First Character

(ACTIVE. TB (1)) is held at ground, for

Nothing more happens until the PDP-8 delivers a character to the transmit

buffer register, by a TAC instruction

5.2.2.2

Since the

The TAC instruction produces the CHR

—o

TCB strobe pulse which transfers

'data from the PDP-8 DB lines to the TCB register, and also sets the character flag.

option to test the transmit flag at this time by a CTF instruction

The program has the

(On the first character cycle, of course,

the transmit flag is always reset.)
If the first character is a sync character, the SEND REQ and TRANS ACTIVE flip-flops are
set.

During the next TRANSMIT TIMING pulse, the REQ TO SEND flip-flop is set and the corresponding

signal is applied to the data set.

Once the data set replies with a CLEAR TO SEND signal, the TRANS-

MIT TIMING pulse train is gated to the TRANSMIT CLOCK line.

If the character in TCB is not a sync character, the SEND REQ flip-flop is reset and the next

TRANSMIT TIMING pulse resets the REQ TO SEND flip-flop.
On the first (sync) character, because the TB register is reset, the LAST BIT TRANSMITTED

signal is true. Consequently, the first TRANSMIT CLOCK generates the TCB
the SHIFT TB

pulse.

The TCB

-9

TB pulse rather than

-’

TB pulse sets the Transmit Flag and resets the Character Flag.

Transmit Flag forces the computer INTERRUPT line to ground, for a program interrupt request.
dition of the Transmit Flag can be tested by an STF instruction to confirm that it is

The

The con-

theyDPOlA that is

interrupting. (When the Transmit Flag is set, a "no skip" condition on the SKIP line results.)

5.2.2.3

Successive Data Characters

must respond to the

In order to sustain continuous serial transmission, the PDP-8

interrupt and deliver another character for the TCB register by a TAC instruction

before the next TRANSMIT CLOCK pulse.

If the TAC is received in time, CHR

character, sets the CHAR FLAG, and resets the TRANS FLAG.

5-12

-0

TCB loads the

Starting with the next TRANSMIT CLOCK pulse, SHIFT TB pulses are produced .to shift the
TB register toward TBI

Bits in TBI

are

presented to the ACTIVE TB(I) line. When the character is

fully shifted out, the LAST BIT TRANSMITTED line blocks further SHIFT TB pulses and enables the
TB pulse, transferring the buffered character to the shift register and enabling a new character
TCB
—+

demand via the PI line.

This sequence continues until the PDP-8 fails to deliver a character before the

next TRANSMIT CLOCK

pulse.

5.2.2.4

Ending Message (Not Idle Mode)

When the program fails to deliver a new character in time

and IDLE MODE is not selected, both SHIFT TB and TCB

flip-flop is reset.

The transmit logic resets the SEND REQ‘and REQ TO SEND flip-flops and waits for

another sync character to set up the transmit sequence again

5.2.2.5

TB are inhibited and the TRANS ACTIVE

Ending Message (Idle Mode)

If the IDLE MODE is selected, when the last bit of a character

is transmitted and a TAC is not received in time, TCB

-9

TB and related signals are generated, replacing

the previous character in the output shift register. "SHIFT TB pulses are enabled until the last bit is transmitted again, and the TCB

TB sequence is repeated.

In this manner, the last character received

from the PDP-8 is retransmitted continuously, until a new data character is delivered by TAC instruction
or

the idle mode is reset by a CIM instruction.

5.3

EXCLUSIVE OR BUFFER (OPTIONAL)
An exclusive OR buffer, can be added to the computer interface section.

(See drawing number

D-BS-DPOIA-0—3.)
The buffer logic consists of an II-stage flip-flop register, input loading and XOR gating, and
output gating.
All stages of the OB register are cleared by the COB command.

be used to transfer Is from the computer AC to the register.

The IOB command can then

If clearing is omitted, the IOB command

places the inclusive OR of AC and OB in the register.
The XOR function is performed by the DCD input gates under control of the XOB command.
'

Logic of a single stage follows the truth table below:
BAC Bit

New OB Bit

Previous OB Bit
'

5-I3

Note that it the BAC bit is a

l, the corresponding OB bit is complemented to place the exclusive OR of

BAC and QB in CB.
The content of the OB register is placed on the [M 0-“ lines during an ROB command.

5—14

CHAPTER 6

MAINTENANCE

The DPOlA always operates in association‘with a PDP-8 computer installation; the general
instructions in Chapter 9 of the PDP-8 Maintenance Manual apply to the DPOlA as well.
maintenance equipment is required.

No additional

Periodic preventive maintenance and mechanical checks for the

PDP-8 installation should include the DPOlA assembly.

6.]

DIAGNOSTICS
The following diagnostic programs are designed specifically for checkout of the DPOlA logic.

Use these tests during marginal checking and trouble analysis.

Document Number

Title

Maindec-O8-D8FA-D

DPOlA Bit Synchronous Communication

System IOT and Data Test
Maindec-O8-D8K8-D

6.2

DPOlA IOT and Data Test

MARGINAL CHECKS
The DPOlA receives +l0V and -l5V dc power directly from the PDP-8 power supplies.

Marginal check selector switches on the DPOlA logic panels permit the marginal check features of the
PDP-8 to be applied to the DPOlA logic as well.

Follow the marginal check instructions in Chapter 9

of the PDP-8 Maintenance Manual, and select the DPOlA
or

module row to be checked by'placing the +10
(See Figure 2-l .) DUring marginal check-

-l5 selector switch for that row in the MC position (up).

ing, run the diagnostic programs to verify DPOlA operation

Be sure to turn all DPOlA marginal check switches off (down) after completing tests.

6.3

ADJUSTMENTS

6 3. l

Adjusting One-Shot De lays

All one-shot delays in the DPOlA are listed below.

usually do not need adiustment unless a module is replaced.

These are calibrated at the factory and

A simple way to start a delay for adiustment,

without a pulse generator or other timing source, is to momentarily ground the inputs to the delay's DCD

input gate, while observing the delay on a scope. Screwdriver adiustments are provided on the modules

for delay time adjustment.

The delay can be observed dynamically during a diagnostic test cycle, for

confirmation of accuracy.

If modules are replaced, delays should be adiusted before running diagnostics.

Delay

Module

Logic Print

Assembled Character

R302

D-BS-637-O-l

l .0 ps

R303

D-BS-637—O-l

See table on

Timing

Sampling
Receive in Progress

Logic Print
R302

Inactive Data Muting

4.5 ms

D-BS-637-0-3

CORRECTIVE MAINTENANCE

6.4

Refer to the PDP-8 Maintenance Manual for general instructions.

Troubleshooting the DPOlA system is straightforward.

The

diagnostic self-test permits methodi-

cal performance checking with the DPOIA completely independent of the data set.
can

Equipment operation

be checked against the flow charts and timing diagrams in Chapter 5 of this manual.

No special

test equipment is required.

6 .4.l

Diagnostic Testing
MAINDEC-08-D8FA-D supplied with the

stalled as shown in Figure 6-l

DPOIA requires that the W990 test connector is in-

Timing is generated under program control by connecting unused IOT

command 6354 to the LOCAL TIMING output line and feeding the pulses into the SERIAL CLOCK TRANS-

MIT and RECEIVE input lines.

The program-controlled TERMINAL READY line is also wrapped around to

simulate the DATA SET READY and RING inputs to the DPOIA.

Similarly, REQUEST TO SEND simulates

CLEAR TO SEND, and TRANSMIT DATA simulates RECEIVE DATA.

readily simulated by the program.

A complete duplex message is

A transmitted sync character, assembled by the receive logic, ini-

tiates a receive sequence, and every character transmitted thereafter is assembled by the receive circuits for checking.

MAINDEC-08-D8K8-D supplied with the DPOlA, is
nected to a modem.

designed

to operate with

the DPOIA con-

w990 TEST CONNECTOR

I
I

TRANSMIT DATA

I
I

REQUEST To SEND

CLEAR To SEND

/ (SUPPLIED WITH
EQUIPMENT)

RECEIVE DATA

wsoz
310

R202
A9

LOCAL
TIMING

‘

I
__

—»

I
I

TERMINAL READY
V

I
|

_.|

CLK
R405
89

I
REMOVE THIS
MODULE IF
INSTALLED

SERIAL
CLOCK TRANSMIT

SERIAL
CLOCK RECEIVE

I
l

‘

I
1

LOCAL TIMING

DATA SET READY

I
I
I

‘
I

JUMPER REo'D

—>

RING

L
3

l
I

I
I

“"03
AIS
DPOIA
COMPUTER
INTERFACE
SECTION

Figure 6-]

10T6654

DPO1A
CONTROL
SECTION

I
I
_I

Connections for Diagnosfic Testing Using Moindec-08-D8FA

CHAPTER 7
ENGINEERING DRAWINGS AND GLOSSARY

7.]

ENGINEERING DRAWINGS

This section contains reduced copies of DPOIA logic diagrams and special-purpose module
schematics.

Drawings reproduced here for reference purposes apply to standard production equipment.

During actual maintenance, refer to the current prints supplied with the equipment.

Logic diagram graphic conventions, logic symbols, and signal names correspond to those used
in the PDP-8 drawing system.

Refer to the PDP-8 Maintenance Manual for definitions.

A schematic is provided (following the logic diagrams) for the 5202 Dual Flip-Flop module.

All other module types are described in the Digital Logic Handbook (C-IO5).
Other engineering drawings (assembly drawings, parts lists, etc.) used'primarily for reference

in maintenance are listed on the master drawing breakdown

(D-DI-637—0-l6).

Table 7—I is an

index to the drawings and schematics supplied in this section.

Table 7-I

Logic Diagram and Schematic Index
Title

Drawing Number

Revision

Page

Logic Diagrams
D-BS-637—0-I

Receiver Logic

7-5

D-BS-637—0-2

Transmit Logic

7-7

D-BS-637-0-3

Std. RS-232 Interface

7-9

D-BS-637—0-4

PDP-8 Interface

7-H

D—MU-637-0-8

Module Utilization (Control Logic)

7-I3

D-AR-637-0—9

DPOIA Word Length Selection

7-l5

D-MU-637-O-II

Module Utilization (Interface Section)

D-IC-637—0-12

Interconnecting Cable Diagram (DPOIA)

D-BS—637-0.-I3'

IOT Selection Logic (DPOIA)

D-BS-637-0-l4

I/O Connectors

D-DI-DPOIA-O-I

DPOIA Master Drawing Breakdown

D-BS-DPOIA-0-3

OR Buffer (optional)

Schematics
B-CS-SZOZ-O-I

5202 Dual

Flip-Flop

7-17
7-19
_

7-21
7-23

7-25
7-27

7-29

SIGNAL GLOSSARY

7.2

A glossary of signal names for the DPOIA appears at the end of this section
on

the D-BS-637—

Signals generated

series of logic diagrams are defined and the originating print number is given.

For

similar information on the signals on the PDP-8 I/O bus, refer to the PDP-8 Maintenance Manual.

SIGNAL GLOSSARY

Signal

Function

Logic Print
(D-BS-637-0—

ACTIVE TBl(l)

)

Transmitted serial data to output level converter

Enables transfer of characters from TCB to TB

ALLOW TRANSMIT

Decoded CEF instruction

CHR FLAG

Character flag

CHR

Strobes computer AC to TCB register during

TCB

TAC instruction
CIM

CIM instruction decoded

CLEAR TO SEND

Control line from data set; enables transmit
clock

CRE

CRE instruction decoded

CTF

CTF instruction decoded

CTR

CTR instruction decoded

DATA SET READY

Control line from data set; condition can be
tested by SSR instruction

END

TB register END bit

IDLE MODE

Status flip-flop set and reset by program

IM 3-H

I/O bus input lines to computer AC

Derived from computer POWER CLEAR pulse

INI

INTERRUPT

Computer program interrupt request line

LAST BIT TRANSMITTED

TB 3-9 and END bit all Os

LOCAL TIMING

DPOlA internal clock (optional)

7-2

SIGNAL GLOSSARY (cont)

Signal

Function

PI
RB

Logic Print

-b

RCB

Program interrupt request gate

Gates assembled received characters From RB to
RCB register

SYNC CHR

RB register contains sync character appropriate
to selected character

length

RB 1-9

Receive shift register

RCB 1-9

Receive character butter register

REC ACTIVE

Status flip-Flop; set when sync character is

detected, reset when data set Receive clock
stream is interrupted.

RECEIVE CLOCK

RECEIVE TIMING, inverted

RECEIVE DATA

Serial data from data set

RECEIVE IN PROGRESS

Delay that times out when data set receive
clock stops longer than a selected interval.

RECEIVE TIMING

Data set SERIAL CLOCK RECEIVE,

shaped and

inverted

REC FLAG

Status flip-FIOp; is set and requests interrupt

when an assembled character is ready; reset by
RRB instruction

REQ TO SEND

Control line to data set, requests service in
transmit mode; turned on when a sync character
is delivered from the computer and held on For
one clock time
'

RING

Control line From data set; indicates ringing on
communication line

RING ENABLE

Status flip-Flop, set and reset by program

RING FLAG

Status flip-FIOp; set by RING

line, reset by

program; condition can be tested by SRI instruction

RRB

RRB instruction decoded

SEF

S EF instruction decoded

SEND REQ

Synchronizing flip-flop for REQ TO SEND line

7-3

SIGNAL GLOSSARY (cont)

Signal

SHIFT RB

Function

Logic Print

RB register shift pulses

SHIFT TB

TB register shift pulses

SIM

SIM instruction decoded

SKIP

Computer I/O bus SKIP line

SRE

SRE instruction decoded

SRF

SRF instruction decoded

SRI

SRI instruction decoded

SSR

SSR instruction decoded

STR

STR instruction decoded

TAC

TAC instruction decoded

TB 1-9

Transmit

TCB=SYNC CHAR

shift, register

TCB I-8 contains sync character appropriate to

selected character length
TCB

Transfers computer output characters from TCB
to

TB register

TCB l-9

Transmit character buffer register

TERM READY

Status flip-flop, set and reset by program;
controls DATA TERMINAL READY output line
to data set

TRANS ACTIVE

Status flip-flop; set when sync character is

delivered, enabling data transfer to shift register and output shifting; reset when computer
fails to deliver the next character in time (unless idle mode is selected).
TRANS FLAG

Status flip-flop; set when buffered data is
transferred to shift register; reset by program

TRANSMIT CLOCK

Pulse train driven by TRANSMIT TIMING;
enabled only when CLEAR TO SEND is on

TRAN SMIT TIMIN G

Shaped version of data set SERIAL CLOCK
TRANSMIT

[

5202
A32

‘

R3 ~49 RC3

2,.

R
3

1“

JR603
8,5

H J

i(a

RECEIVE
CLOCK

STT

—

‘

R5203

(I)

RA22062
__

_I_

(IOT)

’l

I
._

____I__

{$2333—
AIG
BIG

l
1

|
RRB

”b

1 F387

REC<>|

(a
ACTIVE

J
mA

‘

R233

9 RCB

so PIN

SHIFT R3

332(O)———¢K MA

R39

(I)

“—‘3‘9

R340)

TRANSMIT

ACTIVEU)

CANNON

4.8:

'“—°”'

R232
A22

R360)

3370)
R380)
R390)

TABLE

NOTE

SHIFT RE

M
P

S
‘

FOR

I/z DUPLEX OPERATION)

CONNECT PIN 4s T049
—

3M3.

DELAY EQUALS I.5 TIMES ‘—

R39(o)

’

RB7(O)
R95 (0)

5 M5.

‘

R86 (0)

AI8

DELAY

R602
A22

“9

4‘9

R36(I)————Lo
RENO)

RECEIVE
DATA (0)

AI7

RBS(O)—SOROOI

R'“

R330)

(o)—————-+-¢

R88

<—
R3=SYNC CHR

CANNON

Z. ~.l

It
"P

13:4

I
l

SHIFT RB

wpé’zo

—

—"—*>K

IN PROGRESS

—

RECEIVE

I
RB~>RCB

"‘l

r—O
to
I

“‘

LiBJR

[EFERTPT’ELEJ

A20

RBIU)

RECEIVEIN
PROGRESS

IN PROGRESS

--— J

—

SHIFT RB

RIII
AI7

RECEIVE

:
~

DEL

I
I

15> 0'9

CRA

I
u

‘

ENDFLAG

—

SHIFT RB

DREC

'—

CEF

REEWE

’1

R232

—

SHIFT RB

U
s

’

R99

A”

' N'

._~

R603—-—{>

H J

RCBS

R3 —>RC3

BAUD

D-BS-637-0-I

Receiver Logic
7-5

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DESCRIPTION

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A—ML—DPDIA-C

U-MU-SST-D-C
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LOGIC PANEL Assv
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7-27

DIGITAL EOLJIF’IVIENT

CORPORATION
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MAYNARD. MASSACHUSETTS

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