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DEC-08-I3AB-D

December 1972

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PDP-8

Maintenance Manual

TCO1
Dectape Control Unit

mnannan

DEC-O8-I3AB-D

PDP-8
TCO1
DECTAPE CONTROL UNIT
*

DIGITAL

EQUIPMENT

CORPORATION

MAYNARD, MASSACHUSETTS

1st Edition September 1967
2nd Printing April 1968
3rd Printing April 1969

4th Printing July 1969
5th Printing November 1969

6th Printing February 1971
7th Printing December 1972

1972 by

Digital Equipment Corporation

The Following are trademarks of Digital
Corporation, Maynard, Massachusetts:

Equipment

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS

CHAPTER I

INTRODUCTION
General Description
Referenced Documents

ODOJCON

Physical Description
Equipment Characteristics
Electrical Requirements
CHAPTER 2

OPERATION AN D PROGRAMMING

DECtape Format

—l—d

Mark—Track Format

DECtape Instructions
Status Register A Functions
Status Register B Functions

NNMNNNM'MNNMNNN

Control Modes and Functions
Control Functions
Move

0\|O~in:P-wr\>
_.d

Read Data
Read All
Write Data

Write All
Write Timing and Mark Tracks

Enable to the Interrupt

Programmed Operation

Simplified Search Procedure
Bootstrap Loading

01-th

Upper Bound Protection for Data Transfer

Write/Read in Opposite Direction
Turn Around Specifications

Available Software
Subroutines

Library Calling System

00.

Ill

CONTENTS (continued)

Performatting Tape Programs

2-18

Maintenance Programs

2-18

Symbols and Abbreviations

2-19

CHAPTER 3

PRINCIPLES OF OPERATION

Functional

wmwwwwmwwmwwwwwwwMNNNNNNNNNNNNN

‘OGDVOU‘IAOJOJN

Description

Information Flow

3—1

Command Flow Registers

3-l

Detailed Logic Operations

3-4

Basic Read/Write

3-10

Logic

Read and Write Amplifiers

3—12

Device Selector Logic

3-12

STATUS A Decoding

3-l2

Status Register B and

Skip Instructions

3—13

UnitSelectLogic

3—14

Motion Control

3—15

Function Selection

3-15

Interrupt Enable

3—15

Unit/Motion Select

3-15

Timing Pulse Generation

3-l6

Counter Register (C)

3-i7

Window Register (W)

3-17

New

CON-d

3-i

Counter Synch Level
Start Block Marks

(C-SYNC)

3—23

(MK BLK MK)

3—23

Data AAarks

3-24

State Register

3-25

Memory Field Register (MF)

3-27

Function

3-27

CDperations

Aone Tape

3-27

3-28

Read Data

3—28

Read All Function

3-29

.15.5

VVHte Data FuncHon

3—30

.l5.6

Write All Function

3—31

#(JN—d

CONTENTS (continued)

wwwwwwwwwwNNNNNNNNNMN

.15.7

Write Timing and Mark-Track

3-31

.16

Read and Write

Sequences

3-37

.16.

Read/Write Control Signals

3-43

.17

Longitudinal Parity Buffer Operation

3-44

.17. 1

LPB Control

Signals

3-45

.18

Power Clear and Error Stop Logic

3-45

.19

Increment CA Inhibit

3-45

.20

Address Accepted

3-46

.21

Transfer Direction

3—46

.22

B RUN Level

3—46

.23

Fixed Address

3-46

.24

Interrupt Request

3-46

.25

ERROR FLAGS (EF)

(+1

CA IN H)

3-46
_

.25.

Mark-Track Error (MK TR K)

3-48

.25.

Select Error (SE)

3-48

Parity Error (PAR)

3-49

Timing Error (TIM)

3-49

End Error (END)

3-49

DECtape Flag (DTF)

3-49

Panel Indicator Drivers

3-50

.25.

.25.
.25.
.26

.27

#h-b-h-b- 3.313

01-th

CHAPTER 4

INSTALLATION

Installation Procedures

4-1

Site Preparation

4-1

Environmental Conditions

4-1

Power and Cable Requirements

4-1

DECtape Signal Connectors
CHAPTER 5
MAINTENANCE
Maintenance

01010101 03019

Equipment

5-1

Maintenance Control Panel

5-1

DEC Modules

5-4

Module Locations and Complement

5-4

CONTENTS (continued)

UIUIU‘IU‘IU‘IU‘IU‘IU‘IU‘I

.3.2

Circuit Descriptions

5—5

.3.3

Module Replacement Procedure

5-18

Power

5—1 8

Supply 779

.4.1

Mechanical Characteristics

5-19

.4.2

Power

Supply Checks

5-19

.4.3

Marginal Checks
Power Control Panel

.6.l

5—20

(Type 834)

5—2l

Preventive Maintenance

5-22

Mechanical Checks

5-22
CHAPTER 6
ENGINEERING DRAWINGS

Symbols and Designations

6-I

Drawing List

6-1

ILLUSTRATIONS
TCOl

System Configuration

DECtape Track Allocation
DECtape Control and Data Word Assignments

DECtape Recording Format
DECtape Mark Track Format
Status Register A, Format
Status Register B, Format
Turn Around

Sequence Diagram

Type TCOl DECtape Control Functional Block Diagram
Status Register A, Instruetion Flow

Diagram (Part I)

Status Register .A, Instruction Flow Diagram (Part II)
Status Register A, Instruction Flow

Diagram (Part III)

Status Register A, Instruction Flow

Diagram (Part IV)

Status Register A, Instruction Flow

Diagram (Part V)

Status Register B, Instructions Flow Diagram

3-10

Read/Write Logic and Waveforms

3-10

Slicer Network Waveforms

3-14

Timing and State Sequence Diagram (Sheet l)

3-19

Timing and State Sequence Diagram (Sheet 2)

3—21

CONTENTS (continued)
Mark-Track Decoding (C-SYNCH)

3-23

Mark-Track Decoding (MK BLK MK)

3-24

Mark-Track Decoding (MK BLK START—2l0)

3-24

Mark-Track Decoding (MK BLK START—010)

3-24

Mark-Track Decoding (MK DATA 070)

3-25

Mark-Track Decoding (MK BLK END)

3-25

Write All Function,

Timing Sequence Diagram (Sheet 1)

3—33

Write All Function,

Timing Sequence Diagram (Sheet 2)

3-35

Error Check Flow Diagram

3-47

TCOI Unit Single Cabinet Installation Dimensions

4-2

TCOI

Control, Cable Diagram

Maintenance Control Panels

4-3

(Switch and Indicators)

Master Slice Control, G008
Sense Amplifier, G009.

Manchester Reader/Writer, G882
Diode Network, R002

Inverter, $107
Diode

Gate, 51 II

Diode Gate, R113

5-10

Diode Gate, R123

5-10

Diode Gate, Rl4l

5-11

5—H

Binary-to-Octal Decoder, 5151

5-11

5—12

Flip-Flop, R201

5—12

5—13

Dual

5-12

5—14

Triple Flip-Flop, 5203

5-13

5-15

Dual

5-13

5-16

Delay (One Shot), R302

5-14

5—1 7

Integrating (One Shot), R303

5-14

5-18

Variable Clock, R401

5-15

5—19

Pulse Amplifier, $602

5-15

5-20

Pulse Amplifier, $603

5—16

5—21

Clamped Load, W005

5-16

5—22

30 MA Indicator Driver, W050

5-17

5—23

Device Selector, W103

5-17

Flip-Flop, $202
Flip-Flop, $205

CONTENTS (continued)
5-24

Comparator, W520

5-25

Power

5—26

Power Control Panel

5-18

Supply Type 779, Schematic Diagram

5-19
5-21

Type 834
TABLES

DEC Documents

1-2

Summary of Equipment Characteristics For the TCOI DECtape Control

i—3

Mark-Track Coding

2-5

TCOl

2-6

DECtape Instruction List

Status A—bit Assignments

2-7

Status B, Bit Assignment

2-9

Control Function Procedures and Errors

2—1 2

Summary of Timing Data For TCOI Operation

2—1 5

Symbols and Abbreviations

2-19

Counter Register Sequence

3-17

Sequence of Block Marks and Control States

3-26

Sequence of Events During Write Operation“)

3-38

Sequence of Events During Write Operation“)

3-40

Maintenance

5—1

Equipment
(Maintenance Control Panel)

Switch and Indicators

5-3

TCOI Module Complement

5-7

Engineering Drawing List

6—1

ENGINEERING DRAWINGS

BS-D-TCOi-O-Z

MF, USR, MR, FR

BS—D-TCOi—O-B

WINDOW, MK TRK, STATE, LPB

6—5

BS-D-TCOl-O-4

Error Flags

6-7

BS-D-TCOl-0-5

Control

6—9

BS-D-TCOi—O—é

TP GEN TT GEN

6—H

MU-D-TCOl—O-9

Utilization Module List (Sheet 1)

6-13

MU—D-TCOl-0-9

Utilization Module List (Sheet 2)

6—1 5

BS-D-TCOl-O-IZ

Panel Indicator Drivers

6—1 7

BS—D-TCOI-O-lB

Maintenance Control Panel

6-19

BS-D-TCOl-O—l4

Error

6-21

BS-D—TCOI-O-I5

R/W AMPS, SP GEN, TEST CONN.

Flags

viii

6—23

CHAPTER

INTRODUCTION

This manual,

together with the referenced documents, provides information on the installation,

Operation, and maintenance of the Type TCOl DECtape Control, manufactured by Digital Equipment

Corporation, Maynard, Massachusetts.

The TCOl buffers and controls information transfers between a

This document

TU55 DECtape Transport and its associated data processor.

assumes use

of the TCOl in

coniunction with either a DEC PDP-8 or PDP-8/I Programmed Data Processor. Except where specifically
noted otherwise, all references to the PDP-8 also apply to the PDP-8/I.

The level of discussion pro-

vided in this document assumes a prior knowledge and understanding of the TU55 DECtape Transport and

the particular processor (PDP-8 or PDP~8/I) provided with the user's system.
GENERAL DESCRIPTION

1.1

The Type TCOl
tween

DECtape control is used to buffer and control the transfer of binary data be-

the PDP-8 processor and up to eight Type TU55 DECtape transports.

shown on Figure l-l

The system configuration is

POP—B
PROCESSOR

TCOl

<:>

DECTAPE
CONTROL

(1:?)

UP TO SEVEN ADDITIONAL

—.

Figure l-l

TCOl

TU55
DEC TAPE
TRANSPORTS

—

TU55 TAPE TRANSPORTS

System Configuration

The TU55 DECtape transport is a bidirectional device consisting of a magnetic tape transport
and solid state

logic.

During both input and output operations, the TCOl receives data and control information from
the processor and generates the
med commands.

appropriate signals to the selected transport to execute the program-

Binary information

l2-bit computer word every

is transferred between the tape transport and the computer

133—1/3 us.

During reading the TCOl assembles the

successive 3-bit words into one 12—bit word for transfer to the computer.

data-break

(high-speed channel)

parallel for a l2—bit word.

facility of the computer.

block number.

transfer,

The program

four

Transfers between the com-

Data transfers

use

the

3—cycle

As the start and end of each block

detected, the TCOl generates a DECtape control flag signal (DTCF) which causes a
terrupt in the computer.

one

writing, the TCOl disassembles the l2—bit computer word

into four successive 3-bit words to be written on tape.

puter and the control always occur in

program

are

in—

interrupt is used by the computer program to determine the

When it determines that the

forthcoming block

it selects the read or write control function.

1-]

is the

one

selected for

data

Each time a word is assembled or DECtape is ready

receive

data break.
a

word from the computer,

the control

produces a data flag signal (DF) to request a

Therefore, when each I2-bit computer word is assembled, the data break initiates

transfer.

1.2

REFERENCED DOCUMENTS

The DEC documents listed in Table l-l contain material which supplements the information in
this manual.

These documents may be obtained from the nearest DEC field office or from the main office.

Digital Equipment Corporation
I46 Main Street

Maynard, Massachusetts
Table I-I
DEC Documents
Doc. No.

Title

Description

C105

Digital Logic Handbook

Specifications and descriptions Of the FLIP CHIP
modules and a simplified explanation of selection
and use of these modules in various applications.

CIOO

System Modules

Specifications and descriptions of basic system
modules and power supplies. This manual provides a simplified explanation of selection and
use

PDP-8 User Handbook

F—85

of these modules in system applications.

Programming and Operating information for the
computer, including brief instructions on the
TCOI

F—87

DECtape Control.

Complete information on the internal operations
logic, memory basic in/out, and pro-

PDP-8 Maintenance Manual

of PDP-8
cessor

Digital 8-27-U

PDP-8 Programming Manual

options.

Programs for PDP—8. Complete descriptions of
DECtape subroutines designed for assembly with
an obiect program, the DECtape library system,
and the DECtape utility routines.

H -T U55

Maintenance Manual

Transport drive logic and internal Operations, plus
preventive and corrective maintenance instructions.

Small Computer Handbook

Handbook of basic functions of PDP-8/I computer.

Type TU55 DECtape Transport

C—800

DEC-8/I—HMAA

PDP-8/I Maintenance

Complete information on the internal operation
logic, memory, basic in/out, and

of PDP-8/I

Manual

processor Options.
In addition to the documents listed in Table

I-l, a complete set of library programs are

available.
1.3

PHYSICAL DESCRIPTION

The Type TCOI DECtape control logic is mounted in three FLIP CHIP mounting panels which
can

be installed together with up to three TU55

DECtape transports in a standard DEC cabinet.

For de-

tailed information on the mounting panels and cabinets, refer to the hardware section of the Digital

Logic Handbook (CI05).

The standard DEC computer cabinet is constructed with a welded steel frame and sheet steel
Double doors on the front and rear are, held closed by magnetic latches.

covering.

Power supplies and

power controls are mounted inside the rear double doors on a full-width plenum door latched by a Spring-

loaded pin at the top.

Module mounting panels are mounted behind the double door in front with the

wiring side facing outward.
over

Fans at the bottom of the bay draw cooling air through dust filters, pass it

the electronic components, and exhaust it through the wiring and other openings in the front and

tap of the cabinet.

Four casters provide mobile support for the system.

blank panels in the Space not occupied by components.
power from the Type 779 Power Supply and a

The rear plenum door contains

The TCOl control and DECtape units receive

Type 834 Power Control.

These units are mounted near the

bottom of the plenum door.

The cabinet has an access door which extends 8-3/4 in.

plenum door which extends 13-3/4 in. to the rear.
front and rear for access and maintenance.
uous

the front of the cabinet and a

At least a 3-ft clearance should be allowed at both

Cabinets may be bolted together at the sides to form contig-

units.

Equipment Characteristics

1 .3.l

A summary of the characteristics of the TCOl control and associated equipment is listed in

Table 1-20

Table 1-2

Summary of Equipment Characteristics
for the TCOl DECtape Control
Characteristics

Equipment
TCOl Control

15-3/4 in. high, T9 in. wide for equipment which operates up to eight
Type TU55 transports

TU55 Transport

10-1/2 in. high, 19-1/2 in. wide, 9-3/4 in. deep. Chassis can be
extended 16-3/4 in. beyond the mounting surface for maintenance

Cabinet

69—1/8 in. high, 22-1/4 in. wide, 27—1/6 in. deep.

Will hold a
maximum of one TCOl control and three TU55 tranSports

Weight
TCOl Control

30 lb

TU55 Tran5port

65 lb

Cabinet

555 lb

(rack mounted)

(with maximum equipment mounted)

Power Requirements

TCOl Control

115V, 60 c/s, 4A
A Type 834 Power Control and a

with the Type TCOl Control

Type 729 Power Supply are included
(N9M transformer used for 50 c/s)

TU55 TranSport

ll5V :ElO°/o, 60 c/s, 2A maximum, l.5A idle

Cabinet

115V, 60 c/s source capable of delivering 20 A

Tape Characteristics and Density
260 ft of 0.75 in., l.0 Mylar tape per 3.5 in. reel
a.
b.

350 =l=55 lines per inch

849, 036 usable lines per tape

60 lines of control information

1-3

Table l-2
(Cont)
of
Summary
Equipment Characteristics
for the TCOI DECtape Control

Characteristics

Equipment
e.

4096 is the maximum number of addressable blocks per reel

Number of words in a block must be divisible by 3
_

212112

NB—N W +15—

NB=decimal number of blocks

NW=number of words per block

Capacity for I90,000 l2-bit words in blocks of I29 words

Word Transfer Rate
a.

One tape line is read or written every 33-l/3 ps and one 12-bit word is read and assembled or

disassembled and written in l33-i/3 ps.
b.

In reverse direction, the transfer rate varies by 20% as the effective reel diameter changes.

Transfers require l .2% of PDP-8 cycles after the initial 200—ms start time.

Addressing
a.

Mark and timing tracks allow searching for a particular block.

Start time is <375 ms, stop time is <375 ms, turn—around time is <375 ms.

Start and stop distances are approximately 8 in.

Time

Input Signals to Transport from Control
Commands

FORWARD

N orma I I y comp I emen t ary I eve I 5

REVERSE
GO

STOP
ALL HALT

Unit Select

N orma II y comp I ementary l eve I 5

(stops transport when computer halts)
through select 8
Analog write signals to the recording head
Select unit l

Information

Output Signal from Tran5port to Control
Control

WRITE ENABLE

Information

(ground level assertion)
Analog read signals from the recording head

Environmental Conditions

Thermal Dissipation

2l50 Btu/hr

Operating Temperature

50°

Humidity

10%

95°F ambient

90% relative humidity

1—4

NOTE
The magnetic tape manufacturer recommends 40%
tive humidity and 60°
vironment for

I.3.2

DECtape.

60% rela-

80°F as an acceptable operating en-

Electrical Requirements
A cable rated at

II5V, 60 c/s, 30A furnishes power for the TCOI DECtape Control.

cable is terminated by a Hubbell Twist Lock plug rated at 30A, I25

This

Vac.

Signals between the TCOI DECtape Control and-the computer are the standard voltage levels
for the DEC FLIP CHIP modules,
tween

stated in the

Digital Logic Handbook (CIO5).

Command signals be-

the TCOI and the tape tranSport are also standard FLIP CHIP levels except for the SINGLE UNIT

signal which is a dc level between 0 and -9V. During writing, the information carries 200 ma in either
direction with a 20V peak—to-peak waveform,

symmetrical with respect to ground.

When reading, the

peak-to-peak head-voltage waveform is between 8 and I2 mV when the tape is up to speed.
nal

The inter-

logic for the TCOI consists of DEC FLIP CHIP modules. All internal signals are standard FLIP CHIP

levels and pulses, except those for the read/write amplifiers and the SINGLE UNIT signals.

I-5

CHAPTER 2
OPERATION

AND

PROGRAMMING

This chapter contains the information required for the operation and programming of the TCOI

DECtape Control unit.

Included in this chapter is a description of the format of information on the

DECtape magnetic tape, and the modes of Operation used in the programming of TCOI Operations.

The

general operating information for the TU55 DECtape tranSport is contained in the TU55 maintenance
manual listed in Table I-I

2. i

DECTAPE FORMAT

The format of the DECtape (Figure 2-1) used in-the DECtape tranSports provides ten tracks, of

which three pairs of tracks are available for data and two pairs for timing and mark information.
IO-track recording head reads and writes the five duplexed channels of the DECtape.

Duplication of

each track by nonadiacent read/write heads, wired in series, eliminates most dropouts due to noise and

dust, and minimizes skew problems.
tween
on

tracks.

The location of the redundant tracks eliminates most cross talk be-

In addition, the location of the timing tracks along the edges of the tape permits strobing

the analog sum of the timing-track signals and reading of the data tracks, when they are in the most

favorable position.

The location of the data tracks in the middle of the tape also minimizes the effects

of skew.

MARK

TRACK

“T

INFORMATION

TRACK

INFORMATION

TRACK 2

INFORMATION

TRACK 3

INFORMATION

TRACK

3/4

(Same as IT I)
INFORMATION TRACK 2A
(Same as IT 2)
IN FORMATION

TRACK

REDUNDANT

(Same as IT 3)
MARK

TRACKS

TRACK

(Same as MT I)
TRACK
(Same as TT I)
TIMING

Figure 2—]

DECtape Track Allocation

Data is recorded by the Manchester method in which a

read/write operations.

either one direction or the other (non-return to zero,
current is reversed.

fixed time intervals.

prerecorded timing track synchronizes

When writing on the tape, the write amplifiers supply the maximum current in

NRZ).

To Write a pulse, the polarity of the write

The timing track is prerecorded with alternate positive and negative transitions at

The negative transition is used during writing to load the write buffer and

2-]

during

reading to shift data.

The positive transition is used during both reading and writing.

During writing,

this transistion is a signal to switch the polarity of the write current in all write heads.

being written, the current, which starts out positive for writing ZEROs,
in a negative transition.

During reading, the positive transition of the timing track

strobe the data and mark track read—amplifier outputs into the read buffer.

transition is sensed at strobe time,

At strobe

If a

positive

ONE is placed in the buffer; otherwise a ZERO is strobed in.

Because the strobe is a relatively narrow

strobe time.

is switched to negative resulting

If a ONE is being written, the current starts out negative and generates a

positive transition when switched to positive.
is a signal to

If a ZERO is

pulse, the system is not affected by noise outside the

time, all data signals are negative pulses representing ZEROs or positive pulses

representing ONEs. These pulses are all at their peaks. To have any effect, a noise pulse must be
large enough to reverse the polarity of a data pulse. Data can be written over previously written data
because the timing is controlled by the timing track that is written on the tape.
Information is stored on the tape in block form (Figure 2-2). Block

length is flexible and deterI

mined by information on the mark—track.

number of blocks up to 4096.

A complete reel of tape

A uniform block

(849,036 lines) can be divided into any

length can be established over tlhe entire length of a

reel of tape by a program which writes mark and timing information at specific locations.

However, the

ability to write variable-length blocks is useful for certain formats, for example, where small blocks
containing index or tag information need to be alternated with the large blocks of data.
ONE COMPLETE

j:
-:ZONE

B'Locx“-.ELE>cK

iambic. aLocki aLo'ck'

BLOCK I'eLoéK.

BLOCK

REEL

BL'CJ'CKE

Q.m

260 FT.

—

4096

BLOCKS

BLOCK:.-5LOOf<"'f_BLdCK’.II'BLQCKfI-UEL‘QQ

swcx-

I
r

-————«-——M

BLonK. as man wono LOCATIONS

ONE

TIMING TRACK
MARK

TRACK

$732M

TRACKS

2%
ui
ggé
0‘

sss
HIE In g
gig
sessssssss-s
_

“1

Wu.

afigégé
5\'

DATA
WORDS

“1'

’

mi 112

sss‘s
E
g
.

113-

55553

CONTROL WORDS

Figure 2-2

—|29Io DATA

WORD LOCATIONS

CONTROL WORDS

DATA
WORDS

DECtape Control and Data Word Assignments

Each block contains data and control words as shown on Figure 2-3 which are assembled
the TCOl:

DECtape Control.

dress and checking information.
are

used.

Control words separate the data portions of adiacent blocks and record ad-

Although control words usually occupy six lines, only the last four lines

Data words contain stored information and occupy four lines on tape

2—2

(l2 bits).

To maintain

compatibility with the mark-track format, data words are recorded in lZ-line segments (which is the
lowest common multiple of 6-line marks and 4-li-ne data words) correSponding to three 12-bit data words.
Therefore the number of words per block must be evenly divisable by 3.

Line
I

TlMlNG

MARK

Line
2

Llna

Line

Line
5

Llne

Line

Line
4

Line

Line
6

Line

Line
3

Line

Line
2

Line
3

Line
4

Llne

Line

Line
3

Llne
4

TRACK

.1:

INFORMATION
TRACKS

.l”

REDUNDANT
_

TRACKS

NOT

SHOWN
6

lines ()8 bits)

lines

Figure 2-3

(IR bits)

lines (l2 bits

block n+l

Ilnes

(l2 bits)

lines

(t2 bits)

DECtape Recording Format

Block numbers normally occur in sequence from I
one

to n.

There is one block numbered 0 and

Programs are entered with a statement of the first block number to be used and the total

number of blocks to be read or written.

The maximum number of blocks is determined by the following

equation.

2.] .l

£91435
W

-2

_NB

decimal number of blocks

NW decimal number of words per block
(NW must be divisible by 3.)
=

Mark-Track Format

The mark track contains six-bit serially stored codes which initiate controls to raise flags in
the program, request data breaks, detect block mark numbering and block ends, and protect control

portions of the tape (Figure 2-4).

The DECtape control unit automatically identifies these codes.

The

mark track also provides for automatic bidirectional compatibility, variable block formatting, and end-

of-tape sensing.
In all tape

processing Functions except the recording of the timing and mark tracks, a single

mark track bit is read from each line of tape regardless of whether the information is being read or written into the data
center of the

tracks.

Each tape line in both the information and mark tracks is positioned at the

timing track as shown on Figure 2-3. The mark track code is contained within six lines of

the mark track.
A change of polarization on tape read in one direction produces a pulse opposite in
to

that produced by the same change read in the opposite direction.

reverse

has the order of bits reversed and the bits complemented.

2-3

polarity

Consequently, a mark code read in

Forward dIrIction ol lupu motlon_

ONE BLOCK

I
|
|
I
I
I
[EXPAND BIDCK REVERSE
I CODE

:‘M’TQE

MARK

Eff

GUARD

-G-

I
I

96.0 lB-BIT WORD LOCATIONS

I29“,

IZ-BIT DATA

worm LOCATIONS
-

I
l
REVERSE

LOCK

REVERSE

CHECK REVERSE PRE~
SUM
FINAL FINAL

DATA

-r'

"5c;

PERMITS EXPANSION OF
BLOCK NUMBER

-F"

DATA

o“;

__o
.

I35

DATA

5-.qu

PREFINAL

REVERSE
I
CHECK REVERSE
BLOCK EXPAND I
FINAL
SUM
LOCK
GUARD MARK
CODE

0125

Dias

DIZB

0129

PERMITS

EXPANSION 0F BLOCK
NUMBER

SIGNIFIEO START OF BLOCK AND
ALLOWS COMPUTER

PROGRAM TO

BLOCK

NUMBER A5

REVERSE

DIRECTION

IDENTIFY. BLOCKS

PROVIDES: WRITE
DIRECTION

PROTECTION

—"

REVERSE

SAME

FUNCTION

AS REVERSE

LOCK

AND SYMMETRY
PROTECTS TAPE IN EVENT OF MARK CHANNEL
ERRORS

NOT

USED IN PDP‘B CONFIGURATIONS BUT
PROVIDED TO ALLOW COMPATIBILITY WITH

PROVIDES AUTOMATIC ERROR DETECTION
AND END OF BLOCK DETECTION WHEN READING

OTHER COMPUTERS
--

PROVIDES, SYMMETRICAL ERROR PROTECTION
IDENTIFIES FINAL DATA WORD AND REQUESTS

BOTH IDIRECTIONS

CHECKSUM
SAME

AS FINAL

IN REVERSE DIRECTION

(FIRST DATA WORD)
——

SAME

NOT USED BUT PROVIDED TO ALLOW TAPE
COMPATIBILITY WITH OTHER SYSTEMS

AS PRE-FINAL IN REVERSE DIRECTION

(SECOND DATA WORDI

SUCCESSIVE

ADDITIONAL DATA WORDS

DATA WORDS

NOTE:

END

MARKS

OF THE

WHICH

IDENTIFY

PHYSICAL

ENDS

TAPEl ARE THE ONLY MARKS NOT SHOWN.

Coda tuncIionI listed apply only

Figure 2-4

THE

In tho dlucllon

Indlcotod,

DECtape Mark Track Format

For example, the mark read forward as IOOIOI is read as OIOI IO in reverse.
ence

one

is termed the complement obverse or the complement image.

This carrespond-

Every 6-bit code has one and only

complement obverse which is constructed by complementing all bits and reversing their order.

Therefore, the complement obverse of the complement obverse is the original code itself.

In octal nota-

tion, the complement obverse of any pair of digits is constructed by reversing the order of digits, then

performing the Following transformation on each:
O—>7

I—-'-3

2-—>5

3—>I

4—>6

5—a-2

6—D4

7-->O

The transformations indicate that there are eight octal codes which are their own complement obverses:

07, I3, 25, 3I, 46, 52, 64, and 70. All other possible combinations of two octal digits (there are 56)
are

different from their complement obverses.

mark is designated by the minus sign
Since the

As shown in Table 2-I, the complement obverse of any

(e.g., mark (3

5I has the complement obverse -G

32).

DECtape system allows reading and writing in both directions of tape motion, the

mark—track must be coded to present the same information when entering a block from either direction.

The marks at the end of a block are the complement obverses of the marks at the beginning, in reverse
order.

For example, if the control reads the marks E, M, -G as the first three marks beginning a block

in forward motion, then it will read

(3, -M,

in that order,

the last three marks of the same

block.

In reverse motion,

track;

thus the first information, when reading the block in reverse, is -(—- E),

however, the control sees the complement obverse of the contents of the mark

-(-M), -(G), which is

identical to E, M, -G.
All marks used in the standard DECtape format are listed in Table 2-]
exist even

though a given code may have different designations.

for the operation of the Type TCOI

DECtape Control.

2-4

Only ten valid codes

Some of these marks are not required

Table 2-]
Mark- Track Coding
Mark

Octal Code

Function

Signifies the end of a mark frame whose first two lines
were the forward
parity check group.

(Check)

-C

(Reverse Check)

Signifies that the 6-bit reverse longitudinal parity

‘

check group is contained in the control unit read/
write buffer and that the beginning of the data por—
tion of a block is in the forward direction.

D, -D (Data)

In both forward and reverse tape motion, the data mark
occupies all mark frames in the data portion of the
‘block except for the final and prefinal marks. The
number of data marks is limited only by the length of

tape.
i

E, -E (Extension)

The first and last mark of every block (no-op mark).

(Forward End)

Indicates the end zone of tape in forward direction.
The forward end mark is positioned approximately
l0 ft from. actual tape end.

Indicates the end zone of tape in reverse direction.
The reverse end mark is positioned approximately
10 ft from end of tape.

Signifies that the last word read from the data portion

End

~END

(Reverse End)

(Final)

of the block is in the read/write buffer and data
buffer. Signals that the next frame begins with the
6-bit forward longitudinal parity check group.

(Reverse Final)

-F

Signifies that the last word read from the block, in
the reverse direction, is in the read/write buffer and
data buffer.

(Guard)

Performs same function as -L (reverse lock).

-G (Reverse Guard)

Not used.

L (Lock)

Indicates the first of four octal l0 marks.

-L (Reverse Lock)

Protects subsequent records in the event of mark-track

M (Forward Block)

errors.

Signifies the start of a block and'indicates that the
block number is contained in the TCOl control.

-M

(Reverse Block)

P (Prefinal)

-P

(Reverse Prefinal)

Not used.

In the forward tape direction, the prefinal mark is the
next to last mark in the data
portion of a block. It
is the first of four marks using octal code 73.

In the reverse tape direction, signifies the next to last
mark in the data portion of a block.

The standard mark—track uses the serial code of 6-bit characters to divide the

tape into words.

Codes are written on the mark track opposite word locations to identify the type of information stored at

that location on tape.

Block addresses are written for both forward and reverse directions and identified

by two types of mark codes.

A checksum is written at each end of the block.

2-5

The hardware computed

checksum is the six bit logical equivalent (i.e., the complement of the "exclusive OR") of each six bits
written on tape plus the reverse checksum previously recorded.

By including the reverse checksum in

the computation, the block may be read in either direction at a later time without an error.
trol uses the final marks to establish synchronism and raise
words

block-end flags.

The con-

Data marks locate data

2.2

DECTAPE INSTRUCTIONS

The six basic lOT instructions used in the programming of thePDP-El for TCOl

DECtape Opera-

tions are listed in Table 2-2, with the octal code assignments and a description of the instruction opera-

tion.

These instructions apply to two functional groups within the TCOl, designated as status A and

status

B, and are used to clear, read, and load the status registers A and B.

to govern

These two registers are used

tape operations and provide status information to the computer program.
Table 2-2
TCOl

DECtape InstructionList

Mnemonic

Octal Code

Operation

DTRA (read status

676]

The contents of status register A are loaded into the
accumulator by an OR transfer. Refer to Table 2-3
for the AC bit assignments.

6762

Status register A is cleared.

DTXA (load status

The DECtape and error

flags are undisturbed.

The exclusive OR of the contents of bits 0 through 9 of
the accumulator is loaded into status register A, and
bits l0 and ll of the accumulator are sampled to control the clearing of the error and DECtape flags,
res ectively.
Loading status register A from AC
0 t rough 9 establishes the tranSport unit select,
motion control, function, and enables or disables
the DECtape control flag to re uest a program interto Table 2-3 for
rupt as described in DTRA.
AClO and ACll bit assignments.

Refer

DTSF (skip on flags)

677]

The content of both the error and DECtape flags is
sampled. If any flag is set, the content of the program counter is incremented by one to skip the next

sequential instruction.
DTRB (read status

6772

The content of status register B is loaded into the accumulator by an inclusive OR transfer. The AC bit assignments are as follows.
ACO
ACl

AC2
AC3
AC4

Error flag (EF)
Mark-track error (MKTRK)

End-of-tape error (END)
Select error (SE)
Parity error (Pl)
Timing error (TIM)
8
Memory field (MF)

AC5
AC6
Not used
AC9-l0
ACH
DECtape flag
=

—

2-6

(DTF)

TCOl
Mnemonic

Octal Code

DTLB (load status

6774

Table 2-2 (Cont)
DECtape Instruction List
The memory field portion of the accumulator (AC6—8) is
loaded into the memory field register. The accumulator is cleared and the error flags are undisturbed.

2.2.]

Operation

Status Register A Functions

Figure 2-5 is the format for the status register A.
two motion

bits,

one

This register contains three unit select bits,

mode bit, three function bits and three bits which control the flags.

assignments for the status register A are provided in Table 2-3.

TRANSPORT
UNIT SELECT

MOTION

DECTAPE FLAG

ERROR FLAG

ENABLE
lNTERRUPT FLAG

MODE

FUNCTION

Figure 2-5

'Status Register A, Format

Table 2-3
Status A-bit Assignments
Function

TranSport Unit Select

Conditions

AC Bit

0—2

Octal Code
000
00]
010
Oil
100
10]
110
iii

Motion

- '0
-O
-'O

Mode

2-7

Forward (FWD)
Reverse (REV)

C 2.

Vomawum

Stop motion (STOP)
Start motion (GO)
ll

Normal mode (NM)
Continuous mode (CM)

The bit

Table 2-3 (Cont)
Status A-bit Assignments
Function

AC Bit

Function

Conditions

6, 7, 8

Code

Cleeration

000
00l
010
0]]
l00
l0]
llO
l ll

Enable the interrupt

Move

Search
,

Read data
Read all
Write data
Write all

Write timing
Unused (causes
select error)
Enable DECtape control
flog (DTCF) to the

program interru pt

2.2.2

Error flag

DECtape flag

- '0
- 'O

Clear all error flags
Error flags undisturbed
ll
ll

Clear DECtape flag
DECtape flag undisturbed

Status Register B Functions

Figure 2-6 shows the format of the information in the status register B.
6 bits of error status information, 3 memory field bits and the DECtape flag bit.

This register contains
Table 2-4 lists the

function of the bit assignments.

ERROR FLAG

MAINTRACK ERROR

——l

1 1

l—

{

——————~—~—-

END or
TAPE ERROR

DECTAPE FLAG

UNUSED

MEMORr FIELD

SELECT ERROR

TIMING ERROR

PARITY ERROR

Figure 2-6

Status Register B, Format

2—8

Table 2-4
Status B, Bit Assignment
Function
Error Flag

(EF)

AC Bit

Conditions

Detection of any nonoperative condition by the control
listed in the error Functions described in AC bits I
through 5 of this table. These conditions stop tranSport
motion except for parity errors.
=

as
'

Mark-Track Error

(MKTRK)
End of

Tape Error
(END)

Select Error (SE)

Information read from mark track was erroneously decoded

the end zone on either end of tape is over read head.
-

This error occurs 5 ps after loading status register A to indicate one or more of the following conditions.

(a)

The unit select code Specified does not corres

any transport select number or is set to more t

nd to
an one

tran5port.

(b) Awrite functionwasspecifiedwhenthe WRITE ENABLE/
WRITE LOCszitch is in the WRITE LOCK position.

(c) Specifies on unused function code (I I I)bits 6 through
_8 of the status register A.
(d) Specifieda functionotherthan Read All withthe maintenance control panel RDMK/WRTM/NORMAL switch
in the RDMK position.

(e) Sp'ecifieda function other than Write Timingand Mark
Track with the RDMK/WRTM/NORMAL switch in the
WRTM position.

(f)
Parity Error (PAR)

Timing Error (TIM)

Specified the Write Timing and Mark-Track function
with the RDMK/WRTM/NORMAL switch in a position
other than WRTM.

Error occurs during a Read Data function if the longitudinal parity over entire data block including reverse
checksum and checksum, is not equal to I. If a
parity
error is to be set at the end of a
block, it will be set at
the same time the DTF is set. During CM if a word count
overflow does not occur at the end of a block, the
parity
error is set at the end of the block in which the word
count overflow occurs.
The parity error cannot be set after
the DTF is set.
=

(a)

Program fault caused by one of the following conditions:
A data break request is not answered within 66 ps i30%
of the data break request.

(b) The DTF was not cleared by the program before the
control attempted to set it.

(c)

The read data or write data function was specified after
the current data block has been entered to prevent incomplete data block transfers.

2-9

Table 2-4 (Cont)
Status B, Bit Assignment
Function

AC Bit

Memory Field (MF)

DECtape Flag (DTF)

2.3

Conditions.

6, 7, 8

Indicates the memory field from or to which data transfers
take place.

9-l0

Unused

DECtape operation complete

CONTROL MODES AND FUNCTIONS

The TCOl control unit Operates in either the normal mode (NM) or continuous mode
determined by the mode bit (5) in the status register A.

(CM) as

ln the normal mode, the data transfer and flag

indications are controlled by the format of the information on tape.

In the continuous mode, data trans-

fer ancl flag indications are controlled by a word count (WC) read from core memory during the first

cycle of each three cycle data break, and by the tape farmat.
The normal mode differs from the continuous mode primarily in the time at which the DECtape

flag (DTF) is set.

The DECtape flags which occur in the normal mode are inhibited in the continuous

made until a word count overflow has occurred.

In both modes, data break requests occur only when a

word count overflow has not occurred during the Specified current function.

2.4

CONTROL FUNCTIONS

The DECtape system performs one of the seven following functions during either the normal or
continuous mode,

mand.

2.4.]

determined by the octal digit loaded into the status register A during a DTXA com-

A summary of the procedures and possible errors which may occur are listed in Table 2-5.

Move

Initiates motion, in either direction, of the Specified tape tranSport.

The mark— track is read

but mark- track errors are inhibited except for end of tape errors. The move functionIs used to rewmd tape.

2.4.2

Search
Provides random access to the data blocks on tape.

As the tape is moving in either direction,

the sensing of a block mark causes a data transfer of the block number.

causing a program interrupt at each block number.
number which causes the word count overflow.

In normal mode the DTF is set,

In continuous mode the D'TF is set only at the block

After the first block number is found, the continuous

mode can be used to avoid all intermediate interrupts between the current and desired block number.

The block number is read into the memory location specified by the current address register (Memory
location 7755).

The current address register is not incremented.

2.4.3

Read Data

This function reads data in either direction and transfers blocks of data into core memory with
the transfer controlled by tape format.
a

program interrupt.

In the continuous

In the normal mode, DTF is set at the end of each block causing

mode, transfer stops when the word count overflows; however,

the remainder of the block is read for parity checking and the DTF is then set.
2.4.4

Read All

This function allows the reading of all.bits".on tape after the tape motion reaches up to speed.

The three information tracks are continuously read and transferred to the computer.
used to check only for mark-track and end of tape errors.
is set at each data transfer.

The mark-track is

During the normal mode, the data tape flag

During continuous mode, the data tape flag is set only when a word count

overflow occurs.

2.4.5

Write Data

This function is used to write blocks of data in either direction with the transfer controlled by
the standard tape format.
zeros are

Written in all the remaining lines of tape until the end of a block and then the checksum over

the entire block is written.

2.4.6

When a word count overflow occurs during the Writing of a block of data,

The DTF is set in a similar manner as that for the Read Data function.

Write All

This function allows the writing of all bits on tape even though the information is not in the
standard tape format.

The mark-track will only check for mark-track and end of tape errors.

is set for the same conditions described in

2.4.7

The DTF

Paragraph 2.4.4. This mode is used to write block numbers on tape.

Write Timing and Mark Tracks

This function is used to write timing and mark-tracks to establish or change the lengths of
blocks.

2.4.8

Enable to the Interrupt

The TCOl control has an Enable-to-Interrupt (ENl) function which permits the program to remove

the TCOl from the program interrupt of the PDP-8 processor.

Table 2-5
Control Function Procedures and Errors
Procedures

Octal
No..
0

Control Function
MOVE

Normal Mode (NM)Not involved

Continuous Mode (CM)

Possible
Errors

Not involved

SE,
END

Block number read into
core location specified

Same as NM

SE
END
TIM

CA is not incremented

Same as NM

MK TRK

WC is incremented

Same as NM

DTF is set at each block
number

DTF is set only at the
block number causing
WCO

Transfer data as long as
WCO has not occurred.
If WCO occurs in mid—
dle of block, the block
is read for parity
checking but no more
data transfers are made.

Same as NM

Both WC and CA are

Same as NM

by contents of‘CA

READ DATA

SE
END
TIM
PAR
MK TRK

incremented.

READ ALL

DTF is set at each block
end.

DTF is set only at end
of block in which
WCO occurs.

Transfer data until WCO

Same as NM

SE
END

Both WC and CA are
incremented.

Same as NM

TIM
MK TRK

DTF is set at each word
transfer.

DTF is set at WCO

Transfer data as long as
WCO has not occurred.
lf WCO occurs in
middle of block, zeros
are Written to end of
block and checksum is
written

Same as NM

Both WC and CA are
incremented.

Same as NM

DTF is set at end of
If no new
function is specified,
the tape continues to
move but the write
heads are disabled.
(TIM will occur at the
end of next block if
DTF is not cleared.)

DTF is set at end of
block in which WCO
occurred. When
WCO occurs and if no
new function is Specified, the tape continues
to move but the writers

occurs.

WRITE DATA

each block.

2-12

are

disabled.

SE
END
TIM
MK TRK

Table 2—5 (Cont)
Control Function Procedures and Errors
Procedures

Octal
No.

Control Function

Normal Mode

WRITE ALL

WRITE TIMING
AND MARK
TRACK (WRTM)

2.5

Possible

Continuous Mode (CM)

Transfer data as long as
WCO has not occurred.
Word which causes WCO
is last one written. Tape
continues to move but
the writers are disabled.

Same as NM

Both WC and CA are
incremented

Same as NM

DTF is set at each word
transfer

DTF is set at WCO

Transfer data as long as
WCO has not occurred.
After WCO, the writers
are not disabled and
zeros are Written.

Same as NM

Both WC and CA are
incremented.

Same as NM

DTF is set at each word
transfer.

DTF is set at WCO

Errors

SE
END
TIM
MK TRK

SE
TM

PROGRAMMED OPERATION
Prior to using the

Type TCOI DECtape Control for data storage, the prerecording of a reel of
In the first pass, the

DECtape is accomplished in two passes.
tape.

(NM)

timing and mark-tracks are placed on the

During the second pass and the forward and reverse block, mark numbers are written.

These

functions can be performed by the PDP-8 program.

.Prerecording utilizes the WRTM control function

and the manual switch on the maintenance control

panel of the Type TCOI DECtape Control to write on

the timing and mark tracks,
to

to activate

enable flags for program control.

clock which produces the timing track recording pattern, and

Unless the WRTM control function and switch are used simultane—

ously, the writing on the mark or timing channels is inhibited.
maintenance

A red indicator lights on the control

panel when the manual switch is in the RDMK or WRTM position. The mark-track can be

written only when the switch is in the WRTM position.

Only one prerecording operation is required for

each reel of DECtape.
The six basic IOT instructions

are

generated as required by the PDP-8 program to clear, read

and load the status A and clear and read the statusBelements.

the status ofthe DECtape control

TheIOT skipinstruction is availableto test

Since all data transfers between the Type TCOI

DECtape Control and the

PDP-8 memory are controlled by the data break facility, the PDP-8 program sets the word count (WC)and current address

(CA) registers (location 7754 and 7755 respectively) using the memory reference instruction

in the processor

initializing a block transfer.

checks for error conditions.

Before and after a

DECtape operation, the PDP—8 program

A program interrupt is initiated if the TCOI is enabled to the

2-I3

interrupt

system and if the interrupt is on.
block number selected for transfer;

The

DECtape system is started with the search function to locate the

then when the correct block is found, the transfer is accomplished

by setting the WC, CA, and the STATUS A and STATUS B elements.
When searching, the DECtape control reads only black numbers. These are used by the operating program to locate the correct block number.

In NM, the DTF is raised at each block number.

In CM, the DTF is raised only after the WC reaches zero." The CA is not incremented during searching,
and the block number is placed in core memory at the location Specified by the contents of the CA.
Data is transferred to or from PUP-8 memory from locations Specified by the CA which is incremented

before each transfer.
When the start of the data position of the block is detected, DF is raised to initiate a data
break request to the data break facility each time the DECtape system is ready to transfer a l2-bit word.

Therefore, the main computer program continues running but 3 memory cycles are stolen approximately
every

l33-l/3 us for the transfer of a word.

memory locations specified by the CA.

ing routine.

The initial transfer address-l is stored in the CA by an initializ—

The number of words transferred is determined by the tape format, if in NM,

format and WC, if in CM.
gram

Transfers occur between the DECtape and successive core

At the conclusion of the data block

by the tape

transfer, the DTF is raised and a pro-

interrupt occurs. The interrupt subroutine checks the DECtape error bits to determine the validity

of the transfer and either initiates a search for the next information to be transferred or returns to the
main program.

During all normal writing transfers, a checksum (the 6-bit logical equivalent of the words in
the data block) is computed automatically by the control and is automatically recorded as one of the
control words immediately following the data portion of the block.

reading

to determine

The same checksum is used during

that the data playback and recognition takes place without error.

Any one of the eight tape l'l‘CInSpOl'l’S may be selected for use by the program.

After using a

particular transport, the program can step the drive currently being used and select a new drive, or can
select another tranSport while permitting the original selection to continue running.

searching, since several tranSports may be used simultaneously.

This allows rapid

Caution must be exercised because,

although the original tranSport continues to run, no tape—end detection or other sensing take place

All functions provide for automatic end sensing, but this feature stops tape in the selected tape drive

only. The timing for the TCOl operations are summarized in Table 2-6.

Table 2-6

Summary of Timing Data for TCOl Operation
Time

Operation
Time to Answer Data Break Request

Up to 66 us (i30°/o)

Data Break Transfer Rate

4.5 ps

Word Transfer Rate

1 -12 bit word every 133 us

Block Transfer Rate

Start Time

< 375 ms

(i20%)

Stop Time

< 375 ms

(i 20%)

Turn Around Time

< 375 ms

($2070)

Search
block

Read Data Function change for present

Up to 400 PS (i30%)

Search
block

Write Data Function change for present

Up to 400 ps (i30°/o)

(3 cycles) per word

l29 word block every l8.2 ms

Read

Search Function change for nextblock #

Up to 1000 p5 (ism/o)

Write

for next block #

Up to 1000 us (i30°/o)

Search Function change

(i30%)

(i30°/o)

DTF Occurrence:
Move:

None

NM, CM

Search:

NM
NM
Read Data:
NM
Write Data:

Every 18.2 ms (i30%)

Search:

(WC) X18.2 ms ($3070)

Read Data:
Write Data:

(#block) X18.2 ms (i30%)

CM
CM

NM
Read All:
NM
Write All:
Write Timing and Mark Tracks:

Read All:
CM
Write All: CM
Write Timing and Mark Tracks:

2.5.1

Every l33 ps (i30°/o)

(we) x133 us

Simplified Search Procedure
The use of the following procedure simplifies the search operation.
a.

Search in NM and find the first block mark.

Compute the difference (d) between this block mark and the desired block number.

Load the 25

Change to CM and continue search.

The next DTF interrupt is the desired block.

complement of this difference into the WC.
The block number is in the address Specified

by the CA, if a program check is desired. This procedure results in only two interrupts compared to
cl + l

interrupts found in the method which interrupts at each block mark.

2 5. 2

Bootstrap Loading

The CA specifies the address into which the data is loaded.

The CA points to the WC, and the

first word that is transferred specifies the number of words to transfer.

Then, the CA points to itself, and

the second word that is transferred determines where the

subsequent data is to be loaded. This technique

requires the use of the 3-cycle break, which contains the WC and the CA.
or

No program

interrupts, timing,

computation is needed for the location of data.

Upper Bound Protection for Data Transfer

2.5.3

The WC controls all data transfers and, after a word count overflow occurs no further data
transfers take place.
to

the upper bound.

To protect the memory, when reading a block of unknown

length, the WC is set

Similar action prevents writing beyond a predetermined point on the tape.

Write/Read in Opposite Direction

2.5.4

Writing or reading in opposite directions can be accomplished with the TCOl, but two steps
are

required to return the data to the original memory format.

One step is necessary because the CA

only increments and does not invert the reverse order of the words. The other step is necessary because
the word returned from the TCOl is in the following format compared with the original. For example
Original bitpositions:

TON

Returnedbitpositions:

The reorganization procedure that is required can be performed in real time, provided that
sufficient time is available.

This procedure should be avoided when other program interrupts are too

frequent and where using the fastest possible data rate of 133 p5 i30% per word.
2.5.5

Turn Around

Specifications

During a search operation a turn around command can be issued, to change the tape motion
without affecting the other command parameters.

This requires two standard block

lengths of tape to

enable the transport to reach "up to speed” before searching for the block in the opposite direction.
To search for blocks No. 0 next to the tape end zone, the tape must be moved into the end
zone

least two block lengths before changing tape direction.

moved into the end zone at least one block

To search for block No.

length before changing direction.

tape to allow the transport to reach up to speed before searching for the block.
tion the TOG-8 program

l, the tape is

This provides Sufficient
To eliminate this opera-

provides two black lengths of enter-block zone—marks (NO-OP marks) at the

end of tape so that the tape can reverse motion at the end zone and still locate block 0 or block l.

TAPEHEAD

U
{—— REV

4
'—

u. a:
oin
~~

TAPE MOTION

‘1
l"

rnv

FWD -—D

<
*'

MN
~~

4
’-

L Q)

SEARCH REVERSE TO
BLOCK N0. 21 (21R)

AROUND AND
® TURN
SEARCH FORWARD TO

NOTE: F - FWD.
R- REV.

BLOCK N0. 24 (24F)

Figure 2-7

Turn Around Sequence

Diagram

length of tape equal to two standard-block lengths 02910

tape transport heads before
4 in. of tape.

turn around command

is issued.

This is

-—

l2-bit words) must pass the

equivalent to approximately

The formula for calculating, the nonstandard block delay that is required for turn around

is listed as follows.

EXAMPLE
Turn around delay calculation for
129 (words/block)

2.6

X 2

7210 words per block

3.6 block delay
(4.0 block delay used
for simplified search Operations)

AVAILABLE SOFTWARE

The software available for use with the PDP-8 is described in the following paragraphs.

2.6.l

Subroutines
Subroutines may easily incorporate into a program for data storage,

data buffering

logging, data acquisition,

(queuing), etc.

The subroutines include a series that will read or write any number of DECtape blocks, read
any number of l29—word blocks as 128 words

128 decimal

locations;

(or one memory page) in which 200 octal locations equal

search for any block that is used by read and write or to position the tape.

These programs are assembled with the user's program and are called by a iump-to-subroutine (JMS)
instruction.

The program interrupt is used to detect the setting of the DECtape (DTF) flag thus allowing

the main program to proceed while the DECtape Operation is being completed.
when the Operation has been completed.
tion of several

A program flag is set

The program, therefore, allows effective and concurrent opera-

input/output devices as well as the DECtape.

2-17

2.6.2

Library Calling System
A Library Calling System is used for storing named program on

DECtape and provides a means

of calling them with a minimal size loader.

The Library Calling System leaves the state of the computer unchanged when it exits and is

capable of calling programs by name from the keyboard and allowing for expansion of the program file
stored on the tape. It also conforms to existing system conventions by allowing all of memory except for
the last memory page

(76008______77778) to be available.

This convention permits the binary loader

(paper tape) and/or future versions of this loader to reside in memory at all times.
System is loaded by a l7IO instruction bootstrap routine that starts at 76008:“
larger program into the last memory page.
the contents of memory from
those same locations.

60008

This loading calls a

The function of the larger program is to preserve on the tape

75777., and then load the INDEX program and the directory into

Because the information in this area has been preserved, it can be restored when

the operations have been completed.

INDEX

The PDP-8 Library

The skeleton library tape contains the following programs.

Typing this program causes the names of all programs currently on file
typed out.

to be

UPDATE

Allows the user to add a new program to the files.

UPDATE queries the

operator about the program's name, its starting address, and its location
in core memory.

GETSYS

Generates a skeleton

DELETE

Causes a named file to be deleted from the tape.

library tape on a Specified DECtape unit.

Starting with the skeleton library tape, the user can build a complete file of active programs
and continuously update them.

For example,

program that is to be used repeatedly is written on li-

brary tape. The library tape can be used by the programmer to call the FORTRAN compiler.

The com-

piler, in turn, can be used to compile a program to obtain the obiect program. Then, the FORTRAN
Operating System can be called from the library tape and used to load the object program. At this time,
the library UPDATE program is called and the operator defines a new program file (consisting of the
FORTRAN Operating System and the obiect program) and adds it to the library tape.
entire operating program and the obiect program are available on the

2.6.3

As a result, the

DECtape library tape.

Preformatting Tape Programs
There are available programs for preformatting tapes which are controlled from the Teletype to

write the timing and mark tracks, to write block formats, to exercise the tape and check for errors, and
to

provide ease of maintenance.

2.6.4

Maintenance

Programs

A package of maintenance programs are available which exercise the
set of programs exercises

test, using
a

DECtape system.

the various functions separately and provides scope lOOp operation.

program which does random transport selection,

central processor test, is provided.

searching,

One

A system

and data checking while running

2.7

SYMBOLS AND ABBREVIATIONS

Table 2—7 lists the symbols and abbreviations used throughout this manual and on the logic

drawings contained in Chapter 6.
Table 2-7

Symbols and Abbreviations

Accumulator

ADDRESS ACC

Address accepted

BAC

Buffered accumulator

B BREAK

Buffered break signal supplied by PDP—8

BLK

Block of DECtape data

BMB

Buffered memory buffer

BMR

Buffered motion register

B RUN

Flip~Flop located in PDP-8 (PDP-8/I) which indicates whether

BTC

Block transfer control

(PDP—8/I)

processor is performing instructions.

+ l—'CA

lNH

Signal which inhibits incrementing the CA

C0, C2, C3, C4

Control clock flip-flaps

Current address register

Check

CK], CK2

Clock counter

CLEAR STATUS A

400-ns control

Continuous mode

COMP RWB 0-2

Complement RWB bits 0 through 2

C SYNCH

Level

pulse initiated by IOP 2

indicating whether control clock is synchronized with

DECtape marks
CXA

Clear status A pulse or exclusive OR status A pulse

DATA

Data flip-fIOp of state register

Data buffer

DCD

Diode capacitor gate

Data flag

DTF

DECtape flag

DTCF

DECtape control flag

Error flag

Enable

END

End of tape

ENl

Enable—to-the-interrupt

EOT

End-of-tape error

Error stop

Table 2-7 (Cont)
Symbols and Abbreviations

Function decoder

Function register

FR], FR2, FR3

FR flip-flops

Input mixer

Inclusive

INH

Inhibit

I/O

Input/output

ION

Interrupt on

‘

IOP

Input/output pulse

IOR

Inclusive OR

IOT

Input/output transfer

IOT SKIP ON DTCF (I)

400—ns status B SKIP command

LOAD STATUS B

400-ns control pulse initiated by IOP 4

LPB

Longitudinal parity buffer

Memory address register

Memory buffer register

MK BLK END

Flag marking end of a data block

MK BLK START

Flag marking start of a data block

MK DATA

Flag marking the data portion of a block

MK END

End flag indicating that the end zone has been entered

MCP

Maintenance control

Memory field register

MK(—)

SerialIy stored codes on DECtape

MK TK

Mark track error flip-fIOp

Motion register

Pulse amplifier

PAR

Parity error

Program counter

Program interrupt

PWR CLR

Power clear pulses

RATE DY

Rate delay

RD MK

Read mark level output from MCP switch

panel

RD + WD

Read clata or write data

READ STATUS A

400-ns control pulse initiated by IOP 23

READ STATUS B

400-ns control

REV CH

Reverse check

ROTATE DB/RWB

Rotate contents of DB and RWB

pulse initiated by IOP 2

2-20

Table 2-7 (Cont)
Symbols and Abbreviations

RWB

Read-write buffer

RWB 'V' LPB

Computes parity check in LPB

RWB SHIFT LEFT

Shift contents of RWB to the left and read next line of tape

SAD

Status A delay

Select error enable

SEL

Select error flip-flap

SHIFT ST

Shift state pulse

Speed of DECtape

State or start

STB

Strobe

ST BLK MK

State in which control senses block numbers

ST CK

State in which automatic error detection (when reading)is

provided
ST FINAL

Final data word of block state

ST IDLE

State in which DECtape tran5port is stopped or not up to Speed
or between blocks

ST REV CK

State in which reverse checksum is over head

SWTM

Switch timing and mark level output of MCP switch

SYNC

Synchronize

Time

PDP-8 time state i

PDP-8 time state 2

PDP-8 time state 3

TIM

Timing error

T/M ENABLE

Timing mark ENABLE

TPO

DECtape timing pulse which designates instant that center of
left polarization of timing track passes the head inductors
(beginning of a line on tape)

TPl

DECtape timing pulse which designates instant that center of
right polarization of timing track passes the head inductors
(center of a line on tape)

TRK

Track

Timing track

Unit or motion

UP TO SPEED

Signal indicating DECtape tranSport is running at Operating
Speed

USR

Unit select register

Window register

Word count Flip- lop

2—21

Table 2-7 (Cont)
Symbols and Abbreviations

Word count overflow pulse

WCO
WD
W

Write data enable

Write inhibit

lNH

WREN

Write enable

WRITE OK

WRITE ENABLE/WRlTE LOCK switch sensing from selected
TU55

WRTM

Write timing and mark

XOR

Exclusive OR

XOR STATUS A

400-ns control

XSAD

pulse initiated by lOP 4
XOR STATUS A delayed 400 ns

X SA DY

Delayed CXA pulse

0-‘STATUS A

400-ns CLEAR STATUS A pulse for clearing USR

0—‘(device symbol)

Clears all bits of device designated

l—*(device symbol)

Sets all bits of device designated

C—" (device symbol)

Complements all bits of device designated

(4 digits)
+l -*

C0- C3

(device symbol)

or 0 of 4-digit word designates; i or 0 output of
respective control clock Flip—Flap OD, Cl, C2, or C3

Each l

Increment the contents of device designated by l

Inclusive OR

3>l><t<

Exclusive OR
AND

ONES complement of the content of A.
Content of bit 5 of register A

A5(l)

Bit 5 of register A contains a 1

A6-ll

Contents of bits 6 through ll of register A

overbar
e ‘9 0 I

(SWTM)

Negation of signal level. Also refers to complement of signal

FLIP-FLOP (0)

ZERO output of designated flip-flop

FLIP-FLOP (l)

ONE output of designated flip-flop

2-22

CHAPTER3
PRINCIPLES _OF

OPERATION

This section includes a brief description of the basic functional elements of the TCM

control, together with the general information on data and control information transfer.
tains a detailed description of the TCOl
grams contained in

3.l

control operation, with reference to the block schematic dia-

Chapter 6 of this manual.

processors, and TU55

DECtape

It also con-

For detailed information on the POP-8 and PDP-8/I

DECtape Transport, refer to the documents listed in Table l-l

FUNCTIONAL DESCRIPTION
The basic Functional elements of the TCOl

transport interface blocks are shown on Figure 3-l

control, the PDP-8 (PDP-8/I) processors, and TU55
The numerals in the lower right-hand corner of the

blocks indicate the bit capacity of the element. The numerical subscripts on the signal flow lines indicate

the bit assignments of the signals.

dicated by an A or B,

3.l .l

Blocks that represent the Status A and Status B functions are in-

respectively, in the tap right-hand corner of the block.

Information Flow
A description of the registers associated with the information flow are
a.

Data Buffer

(DB)

listed, as follows.

The data buffer is a 12—bit register used as a storage buffer to syn-

chronize data transfers as a function of tape timing between the memory buffer register of the computer
and the read/write register.

Read/Write Buffer (R/WB)

2-bit shift registers.

The read/write buffer is a 6-bit register consisting of three,

During read operations, one bit from each of the three data channels on tape is

read into the read/write buffer and shifted right or left depending on the tape direction.
c.

Write

Amplifiers

The five write amplifiers receive timing signals, mark-track, and

data information from the read/Write buffer and provide the necessary current to the tape heads to write

the data on tape.
d.

Read

Amplifier

The five read amplifiers transfer timing signals, mark-track and data

information from the tape heads to the window register and read/write buffer.

3.1.2

Command Flow Registers

The registers and signals which control the tranSport Operations and the data flow are de—
scribed as follows.
a.

Longitudinal Parity Buffer (LPB)- The longitudinal parity buffer is a 6—bit register used to

perform a parity check on the three information channels. The Operation is performed by setting the
6—bits of information read from two consecutive lines on tape into the LPB and complementing each stage
of the LPB if the correSponding bit of the R/WB contains a zero.

3—l

POP-e

H———-—~PDP_B/I
MBO-H

M83-a

euFFER

IRWB)
DATA
BuFFER
(DB)

wRIT E CURR E NT

(MRI

READ VOLTAGE

READ

AMPLIFIERS

L.._._....__.._

TRACK

LONGITUOINAL

Iq—

DATA FLAG

IDFI

PARITIIQIIJIFFER

WINDOW

(w,

I
I

BREAK REQUEST
wORD CNT OVERFLDw

ADDRESS ACCEPTED
DATA

CYCLE SELECT

F335AI<Y

BREAK STATE

TRANSFER DIR IINI

CONTROL

+19 CA INHIBIT
INCREMENT M8

MEMORY

I
“EMF"

DATA ADDRESS II2I

ADDRESS

WIRING

E’AIENDEO

EII‘TEEmgng

MEMORY

ADDRESS (3)

IOP
GE NERATOR

IOP PULSES (3)

E0;

T 5R

“

UNIT

SELECT

FIELD
R

CONTROL

”0”)"

RECIISIITIER

Ace-a

FUNCTION
REGISTER
I'm

Aco-z
AC3"

ENABLE TO
=

NUMERALS IN LOWER RIGHT CORNER
or BLOCKS INDICATE BIT CAPABILITY

9332,93:

LETTERS A AND BIN UPPER RIGHT or
BLOCKS INDICATE EITHER STATUS A
OR STATUSB GROUP OF ELEMENTS

MOVE
SEARCH
RE AD DATA

(EN!)

READ ALL

TIEA

INTERRURT

AC -9
Ac .. 0

wRITE DATA

»——1

WRITE ALL
WRITE TIMING
AND MARK
TRACKS

(FD)

I
ERRORS:
_

MARK TRACK

END SELECT
TIMING PARITY 5

1/0 SKIP

SKIP
(EATING

stp

ERROR FLAG
(EF)

INTERRDRT
FACILITY

DECTIIRE FLAG
IDTFI
I

PRO-GRAN

PROGRAM INTERRUPT RE Q UEST

Figure 3-]

MOTION
CONTROL

NOTES
.

Aces-a

DALA__§IQEL‘£FYEIBEY_ u

NORMAL DR CONTINUOUS MODE

—

FACILITY

UNIT

SELECT

“we“:

CODE

SELIEEIgITOR

116-“

SELECT

UNIT
SELECT DECOOER
MD)

REIGISTEn3

(USR

ACCUMUL ATOR

MARK

ILI

READ/w RIT E

I
I—-—

u55-———+I

IRwaI

(2)

wRITE
AMPLIFIERS

—<

v1.

—1

READ/WRITE

I2)

MEMORY

RELCI FFTEERR
(I IASB)

.14

TCOI

7r.

'"IIETRQUGPT

DECTAPE
CDNTRDL FLAG
IDTCFI
I

Type TCOI DECfOpe Control FunctionOI Block Diagram

3-2

I
I

Window

(W)

The window is a 9—bit register through which mark-track information is

serially Shifted to generate control signals for the DECtape system.
c.

Data

Flag (DF)

The data flip—flap requests a data break from the processor when a word

is ready to be transferred to or from the TCOl

Memory Address

dress for data transfers
e.

The memory address are l2-bits which constitute a fixed memory ad-

during the 3—cycle data break.

Memory Field (MF)

The memory'field register is a 3-bit register which is loaded by

program control when a data transfer operation is Specified and constitutes bits 6, 7 and 8 of the status

This information, together with the address supplied during the current address cycle, pro-

vides a 15-bit address for the actual data transfer during the third cycle of the

Word Count Overflow Pulse

—

3-cycle data break.

This pulse is received at the end of the first cycle of the

3-cycle data break when a word count overflow occurs and clears the WC flip-flop to indicate that the
current data transfer is

The pulse is used primarily during continuous mode.

complete.

It stops data trans-

fer, however, during the normal mode.
9.

granted.

Address Accepted Pulse

This pulse is generated each time a 3-cycle data break is

It clears the DF signifying that the data transfer has occurred.

Control

The control logic generates the timing and synchronizing pulses to perform the

functions Specified in the function register and to coordinate the operations between processor and TU55

transport.
i.

Device Selector

The device selector decodes the IOT instructions for the DECtape and

generates the necessary pulses to load status registers, read status registers and generate SKIP pulses.

Unit Select Register

gram control from

Unit select register is a 3-bit register which is loaded under pro-

the accumulator bits 0 through 2, and Specified a particular TU55 transport.

Unit Select Decoder

This device decodes the number in the unit select register and

activates a select line to a Specific TU55 tranSport.

Motion Register

The motion register is a 2—bit register loaded from the accumulator,

bits 3 and 4, with the apprOpriate command of GO or STOP (bit 4), FORWARD or REVERSE (bit 3).
m.

Function Register

The function register is a 4—bit register, which Specified the opera-

tion to be performed by the

DECtape. The first bit of this register is a mode bit which selects either

normal or continuous mode.

The remaining three bits are used to Specify one of the seven functions.

bits l

Function Decoder

The function decoder decodes the contents of the function register,

through 3, and transfers the decoded information to the control.
0.

Enable to the interrupt

This is a l—bit register loaded from the accumulator, bit 9,

enable or disable the DECtape from the program interrupt.
p.

Error Register

A 5-bit register each section of which may be set by the TCOl control to

indicate one of five error conditions.
q.

Error Flag

DECtape Fla

The error flag is set by one or more errors indicated by the error register.
-

The DECtape flag is set at the completion of the currently specified

operation.

Flip—Flop

The WC flip-flop is set on an XOR Status A command.

3-3

DECtape Control Flag

The DECtape control flag is set by the error flag and/or the

DECtape flag. This flag is skipped on the SKIP lO'T instruction and is also gated into the interrupt to
request program interrupts.

Skip gating logic generates a pulse from the DECtape control flag and the
SKIP lOT to request a skip from the PDP-8. This gating is not affected by the enable to the interrupt.
U.

Skip Gatin

interrupt Gatin

—

The interrupt requests the program interrupt from the PDP-8 when the

DECtape control flag is set and the DECtape is enabled to the interrupt.
3.2

DETAILED LOGIC OPERATIONS

The information contained in the following paragraphs is a detailed description of the Operations of TCOl

DECtape control and is supported by the instruction flow diagrams Figures 3-2 and 3-3,

and the engineering drawings located in Chapter 6 of this manual.

The engineering drawings are refer-

enced only by the last number of the drawing designation and the signal and module locations on the

drawings are referenced according to the coordinates on the margin of the drawings.

3-4

IOT 7“
READ STATUS
REGISTER A

NH 764
LOAD STATUS

STATUS A

F'NI MOVE V
WRITE DATA

DATA smcn (or

RITE DAYA

AC 0- 9 V
STATUS A
STATUS A

AC ~0- M

-o:

F'N'
READ ALL
7

(IOOO) —. CO 3
DATA SVNCHH)
-

O *E'

ROYAYE DB/RWB

F‘NwmrE ALL
7

SEARCH V
AC‘HO)

READ DATA
7

r‘m
mam: DATA A
mu svucm
7

[01' 762
CLEAR STATUS
REGISTER A

C(IOOI)
A MK ELK UK
A TPO

0—- STAYUS A

XSA DV
5.0 “SEC

U+M DVH)

1—ODTF

emu

IF DESIRED BLOCK NUMBER. PROGRAM
IS REQUIRED TO CLEAR DTF AND CHANGE
TO READ 0R WRITE DATA FUNCTlON
IA

BLK STAR T
5T B L x mm)
A TPD

Figure 3—2

S’ra’rus Register A, Instruction Flow Diagram (Par’r I)

3-5

WAIT ron
END ZONE.

SHIFT STATE TO
81’ REV CK (II

C3 (OIA
WREN (O)

TPO‘

C2 (0) A

51 cxm

TPI

ST REV GK“)

RWB ‘V LPB

SHIFT STATE TO
ST IDLE (II

C3 (0) A
ROTATE ENABLE

I-O-OTF

orrm

ROTATE

C2 (OI A
ST DATA A

DB/RWB
RWB V LPB

READ DATA
7

NOTE;
TPIA

ST ex (0) A READ DATA A

WREN (OI

[mom v (FRO m we (01)]

RWB SHIFT LEFT

ELK START
A ST REV CK (I)
A TPO

TPO A
MK BLK END

A DATAIII

SHIFT STATE
DATA (1)
ST DATA

SHIFT STATE T0
ST FINAL (I)

TF'O A
MK ELK END
A 51' FINAL III
?

RWB SHIFT

LEFT

Figure 3-2

SIa’rus Register A, Instruction Flow Diagram (Part II)

TPIA
wREN (0)

T/M ENABLE
(ENABLE TIMING AND
MARK TRACK
WRITE AMPLIFIERS
AND START TIME
TRACK GENERATOR

RWB SHIFT LEFT

CLOCK

c3 (0) A
ROTATE ENABLE

WRITE SET A
c2 (0)

ROTATE DB IRWB

WREN (I)

(22(0)

SEE NOTE I
I—>DF

ZEROS ARE WRITTEN
UNTIL A NEW
OPERATION IS
INITIATED

EXPECT I1) 3 CYCLE DATA
BREAK (2) ADDRESS ACCEPTED
PULSE TO CLEAR DF

NOTE!
1. WREN (I) A CZIOIA FRI II)
A ROTATE

DB/RWB

EXPECT PROGRAM
TO CLEAR DTF

Figure 3—2

r—D‘

Status Register A, Instruction Flow Diagram (Part III)

3-7

w— m (n WHEN

ALL comma I
| wane ISSUED

SEE NOTE I
ROTATE
DB/RWB

SEE NOTE 2

C2(O) A
WR|TE SET
?

WHEN U)

]

rpm

WREN m

?
NOTE

Figure 3-2

ROTATE DB/RWB A WRITE
ALL I\ WREN (O) A C2 (Ci

ROTATE DB/RWB A C2 (OlA
WREN (H A FRI (I)

S’rafus Regisrer A, Instruction Flow Diagram (Pouri- IV)

3-8

C (I00!)
A MK BLK MK II

SEE NOTE I

Tgo

cum A
ROTATE EN

NOTE‘

WRITE DATA A ST REV
cxm A c: (01

MK BLK START A ST REV

57' FINAL (1) A com A MK

CKII) A TPO AWRITE DATA
0*. DB

SHIFT STATE T0
ST BLK MK (I)

I —-DF

ROTATE DB/RWB

BLK END

DFII)

4 ~37 CK (0) A

In A

:—

[mo (0) v (Free

wc10))]

DATA BREAK

BMB —- DB
———-J

—

w BLK
sum A 51' BLK
MKHMTPO

SEE NOTE 2

smn STATE T0
ST REV CK W

SHIFT STATE DATA“)
ST DATA WREN (O)
TPI A

ROTATE DB/RWB

WWIv
ST FINAL (1

ST REV CM”
7

WREN (I)
A TPI

ROTATE DB/RWB
RWB V LPB

SEE NOTE 3

RWB “V LPB

LPB —v- 08

TPI A
WREN (0)

'?
C3(I)I\
WREN (1)
?
RWB SHIFT
LEFT

SEE NOTE 4

RWB SHIFT LEFT

*fi

WAIT FOR
NEW COMMAND
—.

Figure 3-2

.—

'
—1

Status Refis’rer A, Instruction Flow Diagram (Part V)

WREN (O)

nor 774
LOAD STATUS
REGISTER e

IOT 771
SKIP 0N DTCF

IOT 772
READ STATUS
REGISTER e

‘

AC 6-6

smtus 3
V AC—o—
AC

9—.

MF 0-2

Figure 3-3

3.2.l

Status Register B, Instructions Flow Diagram

Basic Read/Write Logic

The basic read/write logic for the Type TCOI DECtape control is shown on the left—hand side
of Figure 3-4.

Each channel of the read/Write circuit contains a flip-flap» and input gates,

write am-

plifier governed by the flip-flap outputs and a read amplifier. Read inputs are paralleled with the write
amplifier outputs across the head allowing the read amplifier to respond to signals from both the head and
the Write amplifier.

WRITING
m

gasses/m...)

(2)

coup RWBo-ZITP-I)

(3)

DATA (GND-II

Rwao

LI v

WRITE CURRENT

(6)

READ AMP OUTPUTS

I
I

I
l

'
I

mm
Mmm

{

____——_---_---.----—--—--—------——-—---——_-____-_-__---_—u---——-—_

‘7)

TAPE
DIRECTION OF

POLARIZATION,
THIS CHANNEL

.-__-____-____-___________-———----_-n___--m_-_--_—--__—_—-_—____--

(8)

HEAD VOLTAGES

(9)

READ AMP OUTPUTS

(10)

RWB SHIFT LEFT

(ll)

RINSE

{
{

(TP-Ol

GNDt

Figure 3-4

Read/Write Logic and Waveforms

The read amplifier is a high gain differential amplifier augmented by a transient positive
feedback.

When a signal of either polarity is sensed by the head, the read-amplifier outputs switch im—

mediately and are asserted unambiguously regardless of noise which prevents head cross talk resulting

3-10

from simultaneous writing, in the data channels and reading in the timing-and-mark channels.

amplifier outputs U and V are standard DEC logic levels of -3V and ground.
tive than

The read

When input E is more posi-

D, the output V is asserted at ground and U is negative; when D is more positive, the output

levels are reversed.

Due to the positive feedback, the read amplifier oscillates in the absence of input

The read amplifier output waveforms therefore are rectangular whenever the differential input

signals.

signal is indeterminate.
The write amplifier is a saturated grounded-emitter push-pull amplifier with its output collec—
tors connected

through resistances to pins J and K.

If the enable level is asserted negative, the write
When the flip-flop is I, K floats while J is

amplifier is governed entirely by the state of the flip-flap.

returned through the resistance and saturated output collector to -I3V.

while K is negative.

When the flip-flap is O, J floats

In the two tracks correSponding to each channel on tape, information is recorded

in a manner that makes read signals from the two head inductors reinforce on playback.
tors

can

The two induc-

be considered as a single head inductor whose winding is center-tapped to ground, reading and

writing in a single track.
When a write flip-flop contains 0, current flows from ground through the head inductor into K,
and the polarization of the head core is oriented clockwise.
across

The tape polarization,

the head, is oriented toward the left regardless of the direction of tape motion.

the tape moves

Similarly when

the flip—flop contains l, tape polarization is oriented to the right regardless of the direction of tape
motion.

When reading, the current induced in the head by a change in polarization flows opposite to

the current required to cause the same change;

(L-R)

consequently, the current induced by a left-to-right

tape-polarization change is a current flowing out of the head toward pin E.

and when

terminal is

current source it is

read amplifier input E to be positive;

positive.

Thus

The head is a source,

L-R tape—polarization change causes the

consequently V is ground and U is negative. By the same reason-

ing the right-to-Ieft (R-L) polarization change induces a positive signal at D and results in V being
asserted negative and U at ground.

The Manchester recording system used in the Type TCOI
to write each bit in a channel.

The first pulse, ROTATE DB/RWB

DECtape Control requires two pulses
or

RWB SHIFT LEFT, loads the write

flip-flop with the value of the bit to be written, the second pulse, RWB 0-2, complements the flip-flap.
Depending on the state of the flip—fIOp, the ROTATE DB/RWB pulse may or may not cause a polarization
change on the tape. The RWB 0-2 pulse, however, causes a tape polarization change because the com-

plement always changes the state of the flip-flop.

When reading, the value of a recorded bit is detected

by observation of the head inductor output as the polarization change (corresponding to the complement)
passes over the head.

loaded with l;

The RWB 0-2 pulse produces a R-L tape polarization change when the flip-fIOp is

and produces a L-R change when the flip—flop is loaded with 0.

In Figure 3-4, the ROTATE DB/RWB

first pulse sets the flip—flop to the assertion of the I

posite state.

level, the second pulse sets the flip-flop to the op-

The RWB 0-2 and the ROTATE DB/RWB

RWB SHIFT LEFT occur at l6.6 ms intervals.

This relationship is shown in lines I and 2 of Figure 3-4.

Since the flip—flop is loaded through capacitor-

diode gates, the data input is free to change at each ROTATE DB/RWB

3 shows a string of consecutive bits to be written on tape.

bit at a ROTATE DB/RWB

The

RWB SHIFT LEFT and RWB 0-2 pulses alternate.

RWB SHIFT LEFT pulse.

Line

In line 4, the write flip-flap receives each

RWB SHIFT LEFT pulse and assumes the Opposite state on a RWB 0-2 pulse.
3—Il

In line 9'of Figure 3—4, the direction of tape polarization is labeled as R and L for right and

left, reSpectively. The R-L and L-R transitions are detected by the read amplifier as negative and positive half sinusoids at pin E (opposite polarity at D).

If the tape is read in the same direction as written,

the. tape positions correSponding to the time that the write flip-flap was complemented will show an R-L
change as a l;
line 10;

L-R change as a 0.

The head voltages at read amplifier inputs E and D are shown in

the read amplifier outputs are shown in line 11.

In reading, the shift pulses in line 12 for the

RWlB coincide with those in line 2 which complemented the Write flip-flop in writing.
zation change representing

The R-L polari-

l results in a ground level at U at the time of the shift pulse.

Conse—

quently, as shown in line 13, a l is shifted into the shift register as the first bit read.
If the tape is read Opposite to the direction in which it was written, the polarizations reach
the head gap in reverse order;
contents of the mark

that is, the head senses an L-R change where

channel are selected to take advantage of this condition.

was

written,

etc.

The

Data written in one

direction and read in the opposite direction will be complemented.

3.2.2

Read and Write Amplifiers

The read and write amplifiers are shown on Drawing No; 15.
The READ T TRK and READ MK TRK read amplifiers produce timing and mark-track outputs.
The associated write amplifiers are only used to format tape.

amplifier also serve as inputs

to a sense

The D and E inputs to the READ T TRK read

amplifier which provides an SP input for the generation of an UP

TO SPEED signal.

The READ D0, READ D1 and READ D2 read amplifiers and correISponding Write amplifiers on

Drawing No. 15 produce the outputs necessary for the transfer of data between their associated RWB bits

(RWB 3-5) and the DECtape. Appropriate inputs and outputs for this purpose are described in later
sections of the manual.

3.2.3

Device Selector Logic

The device selector logic decodes the output of the memory buffer, bits 3 through 8, and
generates IOT

pulses used to initiate the status A and status B operations listed in Table 2-2.

pulses are produced by the circuit shOWn on the left-hand side of Drawing No. 14;

STATUS A

STATUS B pulses by

the circuit on the upper right-hand side of Drawing No. 6.

3.2.3.1

STATUS A Decoding

The control operations which are initiated by computer instructions

and which involve status register A are shown
A (DTRA), Clear Status Register A

Figure 3-2.

These instructions are Read Status Register

(DTCA), and Load Status Register A (DT'XA).

The status A instructions

contain an octal 76 in bits 3 through 8 of the memory buffer register and are decoded by device selector

W103, location B7 of Drawing No. 14.

Read Status Register A at event time

device selector to produce the 400 ns READ STATUS A pulse.
on

Drawing No. 2), consisting of unit select (USRO-Z),

1, IOP1 is gated with the

The information on status register A (shown

motion control

(MRO and MR1) function register

(FRO-FR3), enable interrupt (ENI), and DECtape Flag (D F) is gated with READ STATUS A pulse location

3-12

B2-B8 to produce outputs (IMO-8) which are loaded into the PDP—8 accumulator through connector

DT05 or DTA05.
Instruction IOT 6762, Clear Status A, is also decoded by the device selector on Drawing

Pulse IOP2 is produced and gated with the decoded output to generate

No. I4 and during Event Time 2.

The CLEAR STATUS A output produces the 0 —"STATUS A, loca-

the 400 ns CLEAR STATUS A signal.
tion

to clear the status

DI,

D8, Drawing No. l4. The positive going CXA pulse triggers the 5 ps delay at R302 providing a —3V
XSA DY output for the duration of the delay.

Clearing status register A selects tape unit (8) by the 000

configuration of the unit select register. The negative XSA DY level at location BI of Drawing No. 2
holds both the STOP and GO levels at ground to prevent a change of motion to tape unit previously

Specified. The positive going end of the XSA DY pulse jams the contents of MRI into BRMI motion.
Either the BRMI (0) output or MRI (0) pulse will provide a ground level at both the FWD and REV outputs
of SI07, preventing a direction change from occurring to insure that only the newly selected unit receives the new command.

IOT 7764, Load Status Register A, is decoded at the device selector and gated with the IOP4

pulse at event time 3 to generate the 400—ns XOR STATUS A pulse. The ground XOR STATUS A pulse
output performs an exclusive OR function with the buffered accumulator outputs shown at the center of

Drawing No. 2, complementing the data in the status register A when the buffered input level (BACO—8)
goes to ground at least 400 us before the XOR STATUS A pulse is received.

This permits Specific infor-

mation in the status register to be changed without affecting the remaining information.

The negative XOR STATUS A pulse is amplified by PA603 (center right of Figure 5-I) to

produce

negative XSAD pulse at Sl07 and a positive XSAD pulse at the amplifier output.

The

positive XSAD pulse is gated into PA603 (bottom right of Figure 5-l) to provide a 0—""AC pulse
which will clear the information in the accumulator.

3.2.4

Status Register B and Skip Instructions

The status register B and skip-on-flag instructions, which are selected by an octal 77 in bits
3 through 8 of the memory buffer register in the PDP-8,

Cl—C3 of Drawing No. 6.

ON DTCF (I), 400 ns

82.

decoded by W—l03, location Dl-D3 and

These instructions are Skip on Flags (DTSF), Read Status Register B (DTRB)

and Load Status Register B (DTLB).
At event time

are

The flow diagram is shown on Figure 3-5.

I, when a programmed IOPI pulse is received, the PA produces the IOT SKIP

pulse outputs. The output pulse is NANDed with the output of RI I3, location

If either an error flag exists or the DECtape flag is set, then the output of SI II will generate a

ground SKIP pulse at pin K of W02I

The SKIP pulse causes the program counter in the PDP-8 to be

incremented by one and skip to the next sequential instruction.

When a programmed IOP2 pulse appears at event time 2, the next PA Will
READ STATUS B outputs.

produce the 400 ns

The READ STATUS B pulse is a common pulse input to the NAND gates associ—

ated with Rl23 modules shown on

Drawing No. 2, location Bl-B8.

A -3V level on any of the gate inputs which indicates that an error exists, the DECtape flag
is set,

the bit configuration of the MEMORY FIELD register, will result in ground IM outputs from the

3—13

/'\
A
A
A
\/
V
U

fvmvflvflv
a.

NORMAL READ-WRITE till) OUTPUT

STARTING

STOPNNG

UAV

I————

VAV/lv ii

9K;
.———.——9‘

U+M DELAY (I20 mac)

AMPLIFIED READ -WR|TE HEAD OUTPUT DURING TURN AROUND

5P OUTPUT PULSES

ill

Figure 3-5

associated gate at connection W02]

Slicer Network Waveforms

This information is loaded into the PDP-8 accumulator by an OR

transfer.
If a load status B instruction is programmed at event time 3,

resulting in 400 ns,

IOP4 pulse will be generated

LOAD STATUS B pulse outputs from the amplifier on Drawing No. 6, location Dl

The -3V pulse outputs are applied to the DCD gates associated with the 3-bit
shown on Drawing No. 2, location DI and

outputs BACé-BAC8
3.2.5

to be

reSpectively.

The unit select information USRO-2 in status register A is decoded
Decoder Sl5l,

memory field register (MF),

D2, causing the memory field information from the buffered

loaded into MFO-MF2,

Unit Select Logic (Drawing No.

Drawing No. l4, location C7 and C8.

enable a SELECT level within the specified TU55

by the Binary to Octal

A ground level on one of the eight outputs will

DECtape tranSport.

3.2.6

Motion Control

(Drawing No. 2)

The motion control information in MRO and MRl of status register A determines when the selected TU55 tranSport will be activated and the direction of tape travel.
duce either a FWD or REV level at location Dl

of the tape.

The output of MRO will pro-

which is gated into the TU55 and to determine the motion

Only one direction signal can be active at a given time. The MRl flip-flop output is

gated with the XDA DY delay level at C2 and determines as previously discussed the STOP or GO levels
to

the selected tape unit.

3.2.7

Function Selection

(Drawing No. 2)

The outputs of the function registers (FRl-3) are decoded by the Binary-to-Octal decoder

Rl5l, at location C3 and C4, Drawing No. 2, resulting in a ground level output on one of the selected
Function lines.

If an octal 7 is indicated, all FR flip-flops set,

DCD gate at the SEL flip-flop,
set

select error level will condition the

Drawing No. l4 location D5 and allow the negative XSA DY pulse to

the SEL flip-flop.

3.2.8

Interrupt Enable (Drawing No. 2)
Bit 9 of the AC determines the status of the DECtape Control flip-flap (ENI) which enables

ENl(l) or disables ENl(0), the DECtape Control Flag, from causing a program interrupt. The output of
ENl(l) will cause an interrupt request to be sent to the PDP-8 at location Bl, Drawing No. 6.
3.2.9

New Unit/Motion Select

(Drawing No. 6 and No. l4)

The buffered accumulator outputs, BACO-4,

are

sampled by the OR gate, Drawing No. l4,

location B6, to determine whether a new unit or motion has been Specified.

A ground level on any

BACO-4 input or at buffered memory bit BMB9(0) which indicates a change on bits 0-4 of the status A
will result in a ground level NEW U+M output.

This level allows the negative going CXA pulse

(Drawing No. 6) to be produced by XOR STATUS A or CLEAR STATUS A, to trigger the 120 ms U+M
delay. The U+M(l) output from the delay is used to reset the up—to-speed flip—flop, location D8. The
output of the up-to-speed flip—flop, when reset, disables the READ T TRK (0) inputs, location B6 and
C6, from generating the timing pulse outputs TPO and TN

When the U+M delay is set, the negative output prevents the timing track pulses (SP) read
from tape during the up to speed operation from triggering the RATE DY flip-flop.

The SP signals are produced by a slicer network consisting of a sense amplifier and a slice
control circuit at location C8 (Drawing No.

l5). When the tranSport is running at normal speed, the

amplifier input from the read/write head is a sinusoid of constant amplitude, as shown on Figure 3-5.
When the tranSport stops or starts or changes direction of motion, the sine wave amplitude and frequency
varies as a function of speed. This variation is illustrated by the amplified read/write head output on

sense

Figure 3-5.
cuit G008.

The slicer level shown in this illustration is preset and controlled by the slicer control cir—

The sense amplifier uses the slicer level as a bottom clamp for the positive excursions of the
Since the amplitudes and frequency of the positive l00ps vary with the tranSport speed, the

sine wave.

loop crossover at the slicer level provides a measure of the tranSport Speed, and this information is contained in the SP output pulses generated at the first crossover of each loop.
When the U+M delay is reset, the ground level output conditions the DCD gate to allow the
first SP pulse to set the rate delay. The ground level output of the rate delay conditions the DCD gate
associated with the up-to-Speed flip—fIOp to allow the next SP pulse which occurs within a 70 ps interval
to set

the up-to-speed flip-flop and start the TCOl

operations.

The up-to--speed flip-flop is reset by the

positive transition of the BRMl (0) level which indicates a stOp motion and by the ground output of the
timing mark enable level (T/M ENABLE) generated at Sl07, location D57. Resetting this flip-flap pro-

duces a O -—’W|NDOW pulse which clears the window register on Drawing No. 3 while the tape is not
up to speed.

3.2.]0

Timing Pulse Generation (Drawing No. 6)
Timing pulses are required for both formatting the tape and for reading information from tape.

During WRTM function the T/M ENABLE level activates the clock and allows timing pulses TPO and TN
to be

generated, provided that the maintenance control panel switch (location B4),

is in the WRTM

position. This position causes the WRTM/RDMK indicator to light and generates the SWTM level. The
SWTM level is ANDed with MN (1) and WRTM level, to produce TM/ENABLE which starts the l20 kc
On the positive transition of the clock pulse, the CKl

flip—flop is; complemented. The positive
transitions of the CKl flip-flop output complements the CKO flip-flop. The outputs of CKl and CKO at
location C5, result in the generation of 100 ns timing pulses TPO and TN which occur alternately every
16.6 ps. The CKO output is also applied to the timing track write amplifier, Drawing No. l5, to pro-

clock.

duce the timing track pattern written on tape.

Timing pulses are also enabled by the SWTM output from the maintenance control panel switch
and by the WREN level at location C4 and B4.
I

During the write function when the C2 flip-flop goes to zero, the negative transition sets the
WREN flip-flop and generates the WREN“) output.

The WREN flip-flop is reset again at C2(O) when

any one of the ANDed inputs, that is associated with the Write functions, is removed.

allows a full data word to be Written,

even

This flip-flop

though one of the enabling level inputs have been removed

before the end of a word had been reached.

Timing pulses TPO and TM are generated during read Operations; when the UP-TO-SPEED(l)

flip-flop is set at location B7, Drawing No. 6.

The inverted output is gated with W level which is

present, when the maintenance control panel switch is any position other than WRTM,

provide a

ground conditioning level to the DCD gates associated with the TH and TPO power amplifiers.

When the

timing track signals READ T TRK are received at location C6 and 86, the positive going pulse to the DCD
gate, generates the timing signals.

The TPO and TN outputs are applied to PA, location A5.

The out-

put of the power amplifier triggers a lO-ps delay during reading and writing data, producing a -3V output to inhibit any extraneous timing signals which may be generated as a result of cross talk between data
and timing channels.

3.2. H

Counter Register (C)

(Drawing No. 5)

The counter register, location D5-D7, Drawing No. 5, consists of four flip-flaps used to con—
trol the blocks of information on the tape,

shown on the timing diagram (Figure 3-6).

the C2 and C3 flip-flops provide a four count used in formatting a data word on tape.
and C3 provide a count of six for the mark-track information.

The outputs of

Outputs CO, Cl,

Initially the counter register is set to

lOOO by the l000—'C0-3 pulse produced by the ground C-SYNCH and the positive transition of TPO.

This count presets the counter in synchronization with the tape and starts the first count of both the four
and six counts.

The count sequence is shOWn on Table 3-l

The word count sequence (C2 and C3) re-

peats every four TPO pulses and mark-track count (C0, Cl, and C3) repeats every six TPO pulses.
Table 3-i
Counter Register Sequence

3.2.12

Window Register (W)

TPO Pulse

(C-SYNCH

TPO)

(Drawing No. 3)

The window register Wl—9, shown on Drawing No. 3, location D4-D8 provides a temporary
storage for the mark-track information read from tape during all tape functions except WRTM.
start of the

At the

loading operations all flip-flaps are cleared by the 0—-"WINDOW pulse generated by re—

setting the UP-TO-SPEED flip-flop on Drawing No. 6.

When the tape is up to Speed, the READ MK

TRK information conditions the DCD gates associated with W9 flip-flap to allow the TPl timing pulses to
shift the mark track information through the window register.

The next TPl

pulse which appears after

flip-flap which will remain set until cleared by the 0—-*W|NDOW pulse. The outputs of the window register are applied as inputs to six separate AND gates which

the W2 flip—flop is set, will set the W]

decode the inputs and generate Specific mark—track level outputs.

:mile

al'l°T'l°l'l°T'l°l7l°l

TOOIIOIOOOIOOOOOIOOOOOIOOOOOIOOOIilOOO
TPOTPO

(I¢¢¢)~>CO—3
1

C3
0

’
C2.
0

‘W

I
C

C 9‘

L___l

725

gear;
ST

\DLE

‘

I_____J

L__._l

[._____’
MK

C'SYNCH

BLK START

C( ‘ O 0 0

ELK

‘11“

MARK

REV CK

DATA

REV CK

sum

BLK STAR‘I

BLK

START

I”
MK

Onol

loxol

~+~‘

TRACKS.

L_]

L__.__.._J
MK

Imol

ZIO

.MK BLK MK

——+——_‘5T

BLK START

DATA

Q70

DATA

FlRST DATA woa

2ND DATA WORD

ETC.

“(2:556
“Wis
.

(w:.::;m

L
T

T
T

T T TTT T

DETRETTTTTTTTJTTTTTTTTM

55:21:25:TTJTTTTTTTTTTTTTTTTTTLTTTTTTTTTTTm

{EVEZTS’ExngEHT/ALLARRows)l
comp

RWB

o—a

(SHORT ARROW$)J

f1? fo 1T? fo fTI TTT TT

Figure 3-6

FTC

Timing and State Sequence Diagram
(sheet 1)

3-19

MARK

TRACK

I
0

TPO

TPI

QW
;W

C¢

MK BLK

MK DATA

MARK

TRACK

DECODING

REEBEZ’DBPB
RI’ISR’TTLSB
LPB+DB

ETC

2ND

BLK END

LAST

[

LAST DATA WORD

MK BLK

END

373

IDLE

CHKK

SUM

MK BLK

FINAL—+—STCK4+—\

DATA WORD

373

=I|=

DATA

(—

END

073

O70

PARITY
ERROR

FOR

T I

am:IIILIIIIIIILILIIIIIm
22:22:;

IIIIIIIIIIIIIIIIIIIIIIIII

i‘é’fwii'ég

ITI ITLIIIITI III III III ITIITI ITLITI

COMP

RWBQ>-2

(SHORT ARROWS)

Figure 3-6

Timing and Sfafe Sequence Diagram

(sheet 2)

3-21

3.2.12.1

Counter Synch Level

(C-SYNC)

Ilnitially, when reading mark-track information either in

the forward or reverse direction, the first code to be recognized and used for synchronization is a result

This information appears after the reverse end mark

of the bit information formed by octal 525 or 725.

The bit configurations (shown on Figure 3-7) is decoded by the

codes sequence through the W—register.

C-SYNCH gating logic (location C1),
the control register.

produce a' series of C-SYNCH level outputs which condition

For the Specific mark-track codes refer to Table 2-'l

a»—

TAPE MOTlON

EXTENélON

REV BLOCK

MARK

525

Figure 3-7

FWD BLOCK

EXTENSION

OCTAL.

Mark—Track Decoding (C—SYNCH)

The first code recognized by the C-‘SYNCH gating appears at
coded with the -3V output of $111

CD. These nine bits

are

de—

(location D2) and with WRTM and generate the C-SYNCH levels for

all Operations except write timing mark.
With two extension marks (E) inserte

in the mark-track information, the C-SYNCH signal

will appear six times at the input to the AND gate and produce the C—SYNCH level to reset the control

clock.

Only at the last decoding

@, however, will the control clock initiate

count and synchronize

the counter with the mark-track information.

3.2.12.2

Start Block Marks (MK BLK MK)

The next bit configuration in the W-register, which is

recognized, is the forward or reverse block mark.

This information appears during the next TPl

after the C- SYNCH level is generated, as shown on Figure 3-6.
which precedes the TP1

pulse

sets

the counter register to (1001).

with the WM— level and the counter register outputs,

pulse

The positive transition of the TPO pulse
The W-register information is gated

C0(1), and C1 (0), to generate the MR BLK MK

outputs, as shown on Figure 3-8.
The octal 2 position of the reverse guard mark, in the forward tape direction, or octal 5

portion of the guard mark in the reverse tape direction is recognized together with the lock marks to
generate the next mark-track signal MK BLK START as shown in Figure 3-9.

3-23

TAPE MOTION

‘—

MARK

EXTENSION

FWD BLOCK

OCTAL

526

REV

GUARD
2

I_____..J

Figure 3-8

Mark-Track Decoding (MK BLK MK)

TAPE MOTION

4-—

LOOK 2

LOCK I

REV GUARD

MARK

210

—-O

ETC

OCTAL

I_____J

Mark-Track Decoding (MK BLK START—210)

Figure 3-9

The outputs from the W-register, except for W2,
MK BLK START outputs at location C5.

shown on Figure 3-6.
ate

are

AND gated and inverted resulting in the

This occurs at the next 1000 count of the control register,

This lock mark is the first of four that are programmed on tape.

the MK BLK START levels.

Each will gener-

The bit configuration required for the next three lock marks are shown in

Figure 3-l0.

a—-

MARK

OCTAL

TAPE MOTION
LOCK 2

LOCK I
1

LOCK 3
0

LOCK 4
O

OIOOOIOOOOOIOOOOOIOOOOOIOOO

_.L_.*_____J
C3)

Figure 3-lO

Mark-Track Decoding (MK BLK START-OIIO)

The same AND gate which decoded the

(2108) W-register configuration will decode the

(0I08) and produce the additional MK BLK START level,
3.2.I2.3

Data Marks

location B5 and C5.

shown on Figure 3-6.

The data mark follows the last lock mark and is decoded by AND gate R002,

The W-register configuration is shOWn on Figure 3-] I

3-24

0—-

MARK

LOCK

OCTAL

070

4
7

TAPE MOTION

DATA I

DATA 2
7

DATA 3

ETC

Figure 3-l l

Mark-Track Decoding (MKDATA 070)

The -3V inputs are inverted and generates the MK DATA output levels as shown on Figure 3-6.
After the last data mark has been decoded, AND gate (location B7 and C7) decodes an octal

073 and three octal 3735 from the W-register to generate a series of four mark block end signals (MK
BLK

END) as shOWn on Figure 3-l2. This is accomplished by not decoding inputs from the W2 or W3

flip-flops.
6—

MARK

DATA

OCTAL

TAPE MOTION

PRE FINAL

FINAL

CHECK SUM

LOCK

007,3

373OOOIIIOIOITIOIOIllOlOIl1010

Q _J_.~__i
(9
Q)

Figure 3-l2

Mark-Track Decoding (MK BLK END)

The next two mark-track codes, guard mark (51‘) and block mark (45), which follow the lock

mark, are not decoded and the decoding continues through the same sequence, as previously specified,
until the end marks (222) are decoded by AND gate (location C8), which generates the MK END level.

3.2.l3

State Register (Drawing No.

The state register (Drawing No. 3, location B5-B7) is a ring counter which indicates the
control states of the TCOl

determined by the mark-track decoding sequence.

cleared each time the UP-TO-SPEED flip-flop (Drawing No. 6) is reset.

The state register is

The control states are se-

quenced through the state register by the positive transition of the SHlFT ST pulses which are produced

by monitoring both the decoded outputs of the mark-track and by the outputs of the state register at
location D3. The outputs of the state register are connected to the maintenance control panel to provide a visual indication during DECtape Operations.
and control states that are generated.

Table 3-l lists in sequence the various block marks

The first five events occur prior to the generation of the first

SHIFT ST pulse.
3-25

At event 6, the first block mark is decoded.

The ground MK BLK MK level is inverted by

Sl07 at location C3, and applied as one input to the two-input AND gate, location C3.

The other in-

put is held at -3V.

This signal results in the first SHIFT ST pulse at event time 7, which sets the ST

BLK MK flip-fIOp.

At event time

IO, the mark-track decoded output MK BL START is gated with the

-3V ST BLK MK (I) output and generates the second SHIFT ST pulse.

flip-HOP and resets the ST BLK MK flip-flop.

This pulse sets the ST REV CK

The second MK BL START level produced by the mark-

track decoding network, is gated with the -3V OUI'pUT of ST REV CK flip-flog) to produce the third
SHIFT ST pulse at event time 13, which sets the DATA flip-flop.

The DATA flip-fIOp remains set for all

data words and until the MK BLK END level is decoded which allows the SHIIFT ST pulse at event time

I7 to set the ST FINAL flip-IIOp.

The second MK BLK END pulse is ANDed with the ST FINAL(I) out-

put producing a SHIFT ST pulse, at event time 20, and sets the ST CK Hip-fIOp.

The ST CK (I) -3V

output AND gated with the counter register output C2(I) sets the ST IDLE flip-flap at event time 23
which will allow the sequence of events, starting at event time 6,

to repeat

for the next block.

Table 3-2

Sequence of Block Marks and Control States
Event No.

Blgkaf/Zlgk

Tape Stopped (ST IDLE)

Start Tape

UP TO

C SYNCH

DATA SYNCH (I)

C (IOOI)

SHIFT ST

Eloclzohgagr)

Code

SPEED(I)

725 or 525

MK BLK MK

I26

ST BLK MK (I)

MK BLK START

SHIFT ST

I I

ST REV CK (I)

MK BLK START

SHIFT ST

DATA (I)

MK DATA

070

MK BLK END

073

SHIFT ST

ST FINAI. (I)

MK BLK END

SHIFT ST

ST CK (I)

2IO

OIO

373

3-26

Table 3-2 (Cont)
Sequence of Block Marks and Control States
Block Mark
or State

Event No.

Block Mark Code

(Octal)

3.2.l4

c2 (1)

SHIFTST

ST IDLE (l)

Start at Event No. 6

l26

Memory Field Register (MF) (Drawing No. 2)
The 3-bit memory field register (Drawing No. 2, location Dl and D2) uses data in the one

outputs of BAC bits 6 through 8 to provide extended data addresses for the memory extension control of
the PDP-8.

The MF function requires a ground O---MF pulse input to clear each flip—flap and a -3V

LOAD STATUS B pulse input to load each flip-flop.

the end of each LOAD STATUS B pulse.

The 0—OMF pulse is applied to clear the MF at

The required delay is introduced by the LOAD STATUS B

pulse from device selection (Drawing No. 6) as an input to PA location C2. The desired ground
0—"MF pulse output is delayed until the trailing edge of the -3V LOAD STATUS B pulse appears at
the PA input.

When the MF has been cleared, the LOAD STATUS B input at event time three produces

either a -3V or ground level

MF0(l), MFl (l), and MF2(l) depending upon whether the flip-fIOp has

been enabled by its BAC input.

This information is returned to the PDP-8 memory extension control

through NAND gates (Drawing No. 2, location B3 and B4). Upon receipt of a READ STATUS B pulse
from the device selector, the -3V or ground level NAND outputs are transferred to their corresponding
memory extension control addresses

lMé, IM 7, and IM8.

Information contained in these NAND out-

puts represents the programmed extended address initially loaded into the ME by BAC6 (1) through
BAC 8(1).

3.2.l5

Function Operations

(Drawing No. 2)

Function bits FRl-FR3 of the status register A are decoded to provide one of the seven function levels which are used to select the tape unit Operations.

A description of the logical operations

within the control unit for each function is described'in the following paragraphs.

3.2.l5.l

Move Tape

The move tape function (MOVE) used to reposition or rewind tape is imple-

mented by a Load Status Register instruction which Specifies all zeros in the Function Register FRl

through FR3 (Drawing No. 2).

The move functionallows the tape unit selected to move in the direction

Specified by the motion register (MRO) until the end of tape zone is detected, without allowing data
transfers to occur.

flip—flop to be set at the end of
the XSA DY delay and starts the tape motion in the direction Specified by MRO. When "up-to-Speed"
The MRI (1) level from the motion register allows the BRMl

is reached the mark—track information is read from the tape.

3—27

If no select error is detected, the tape-

motion continues and the mark-track information is read without effect on the operation until the end
zone

The decoded end zone generates a MK END level (Drawing No. 3) which allows the

is.- detected.

END flip-flop (Drawing No.

3.2.l5.2

l4) to be set by the TPO timing.

The Search function is used to locate block numbers on tape.

During this function,

only block numbers are transferred to the PDP-8 where
the program performs a comparison of the information received with a Specified block number to deter-

all information is read from the tape, however,

mine whether the two are the same.

The search function is initiated by an octal l in the function register

FRl-FR3.

When the

tape tranSport comes "up to speed, ”the timing track pulses READ T TRK generate the TPO and TH

pulses, (Drawing No. 6). The control Operations performed are similar to the READ function. The
WREN (0) output allows the TH pulses to generate RWB SHIFT LEFT pulses which assemble the information from tape in the RWB.

The decoded mark-track information produces up to seven C-SYNCH levels,

the last of which generates the first ROTATE DB/RWB pulse and rotates the first half of the block num-

ber into the DB.

Two more shift pulses are then generated at TPl times to assemble the next half of the

block number into the RWB, and the MK BLK MK signal is decoded to shift the state to ST BLK MK.
At the C3 (0) transition another ROTATE DB/RWB pulse loads the data buffer with the block mark inforation and, at the same time, the TPO pulse generates a l-—ODF pulse
to set the data

quest

flag generating a break request.

(Drawing No. 5 at location Di)

In the normal mode, the

DTF‘Iflip-flop is also set to

re-

program interrupt to determine whether the block number transferred is; the block number desired.

in the continuous mode the DTF is only set if a word count overflow WCO pulse is received.

Unless another function is Specified, the control continues in the search function, the mark—
track decoding is performed and the data is assembled and shifted in the DB/RWB.

The l--*DF pulse

which Sets the data flag will not be generated, however, until the next MK BLK is decoded.

During the ST REV CK state, the 0 --*LPB and RWB 4+ LPB are generated for the parity comThe parity has no significance, hOWever, during search and the PAR flip-flop is inhibited.

putation.

During the search function, the +l—D'CA lNH level, at location B6, will prevent the incre-

menting of the current address cycle
3.2.15.3

Read Data

the PDP-8.

The read data function is normally performed afterthe program has searched and

and located the desired block number.

Read data is specified by an octal 2 in function register FRl-FR3.

After tllhe search function is completed, the control is normally in the ST BLK MK state. When the mark—track

informelation is decoded
ST REViCK.

as a

MK BLK START, the SHIFT ST pulse (Drawing No.

During the previous states of the search function the ROTATE DB/RWB and RWB SHIFT LEFT

pulses were generated.

No data read,

The ST REV CH level enables the TH
clears the LPB.
are

3) changes the state to

however, was allowed to be transferred to the proceSsor.

pulses to generate the 0—0- LPB pulses (Drawing No. 5) which

The RWB A«7‘ LPB pulses, which exclusive ORs the 6-bit RWB information into the LPB,

also produced during the ST REV CH.

This permits the reverse check word! (the last 6-bit read) to

be included in the parity computation, and the last O—~LPB pulse clears the LPB before the first data
word is read.

The ST DATA is entered and the data is assembled and shifted by the RWB SHlFT LEFT

3-28

and ROTATE DB/RWB pulses as described in the read and write sequence (Paragraph 3.2.I6).
a

Each time

ROTATE DB/RWB pulse is generated, a RWB ¥- LPB pulse allows the parity computation to be performed.
If the WC register is set, indicating that a word-count overflow has not occurred, the I—r-DF

pulse (Drawing No. 5, location D2) at the C2 (0) transition will set the Data Flag (DF) requesting the
3-cycIe data break to transfer the word in the DB to the PD P-8. When the request is granted, the
ADDR AC pulse (location B5) clears the DF. The data-break request must be granted before the next
ROTATE DB/RWB or the information in the DB is no longer valid, and a timing error will occur as a result of the ROTATE RWB/DB pulse and the D‘F (I) level.
This sequence continues until the end of the data portion of a block occurs which is signified

by the ST CK state. When the ST CK flip-flop is reset, the contents of the LPB should contain all "ones"
or

the parity error will be indicated by the

LPBf’I input‘which sets the PAR flip-flop.

At this time in

the normal mode, the ST CK (I) pulse will generate l—'DTF pulse which will set the DTF flip-flop.
In the continuous mode, the DTF flip-flop will be set if a word-count overflow had been issued during

the previous data block.

If the DTF flip-flop is set, the programs must specify a new operation.

If it

is not set and the continuous mode is specified, the operation will continue as previously described.

When a word-count overflow occurs during the middle of a data block, the data transfers will

The

stop.

remaining words, however, are read and parity is computed.
3.2.15.4

Read All Function

The real—all function, specified by an octal 3 in the function register

FRI-FR3, allows all information written in thedata tracks on tape, including reverse check, bIocknum-

bers, etc. to be read and transferred to the PDP—8 processor.

Read all can be programmed

after a search function which locates a specific block on tape before reading begins.

initially

When the tape had

reached speed, only one C-SYNCH level is required to set the DATA SYNCH flip-flop and the information on tape is read even though it may not be synchronized.

This can occur in the middle of a data

word on tape.
The operations within the DB/RWB during the read all function are similar to the operations

which occur during the read-data function.
at time TPI

The RWB SHIFT LEFT pulses (Drawing No. 5) are produced

enabled by the WREN (0) output to assemble the information into the RWB.

The ROTATE

DB/RWB pulse then occurs as a result of the ROTATE ENABLE level and C3 (0) transition, causing the information in the RWB to be transferred to the DB.
ate

No.

an RWB

The same enable level and pulse transition also gener-

'V‘ LPB pulse which allows the parity computation.

I4) is disabled during the read-all function.

However, the parity flip-flop (Drawing

The next two RPI

pulses again produce two RWB

SHIFT LEFT pulses followed by another ROTATE ENABLE and RWB ’v‘ LPB pulse. At this time, the C2 (0)

input (Drawing No. 5), enabled by the READ ALL input will generate I—‘DF pulse which sets the DF

flip—flop, requesting a data break.
In the normal mode, with the FRO(O) V WRTM input applied, the I—+DF pulse will also set

the DTF flip-flop requesting the program to specify a new operation.

Although the next word is not

transferred, the setting of the data flag may result in a timing error requiring a new function to be specified or a similar operation to be performed.
set when

In the continuous

the WCO pulse occurs from the PDP—8.

mode with

FRO(T), the DTF flip-flop is

The tape motion will continue, but no additional data

transfers will occur.
3—29

During the read-all function, although parity is computed, mark-track information is decoded,
and the state register changes, these Operations have no effect on data transfer.

3.2. l5.5

Write Data Function

The write data function, Specified by an octal 4 in the function

register FRI -FR3, is used to Write data on tape in the data areas assigned by the mark-track coding. The
write data function is normally initiated following a search Operation which determines the block posi—
tion on tape where the data will be written.

The initialization process allows the tape to reach speed,

the DATA SYNC flip-fIOp to be set, and the counter to be synchronized with the mark-track information.

Specifying write data before the DATA SYNCH flip-fIOp has been set will result in no Operation.
When the write data function is Specified after a search function, the control is normally in
the START BLOCK MARK state. The ST BLK MK (I) level is gated with the decoded window register
output MK BLK START level (Drawing No. 3, location D3)
the ST REV CK flip-fIOp,

changing the state of the control.

generate or SHIFT ST pulse which sets

Pulses 0—-LPB and RWB Jv‘ LPB,

quence of pulses (Drawing No. 5) will load and clear the LPB during the reverse check state.

a se-

However,

the reverse checksum which occurs one 6-bit word before the data state will be included in the parity

computation. Pulse A0-->DB generated during the ST REV CK by the Cl (0) transition, clears the DB
and generates a l—v DF pulse at location C3 which sets the DF flip-fIOp and requests a data break.

The ST REV CK (I) level is gated with CO (I), location BZ,

to generate

the WD EN level.

This level

allows the WREN flip-flop to be set at the C2 (0) transition and enable the data to be Written.
the transition of C2 (0), the control enters ST DATA.

The WREN (I) output, gated with TPl at location

B7 produces the first COMP RWB 0-2 pulse, which is required for the Write sequence.

With the

WREN (l) flip-flop set, the RWB SHIFT LEFT pulses are produced at the C3 (l) transition.
for the write operation is described in

During

Paragraph 3.2. l6.

The sequence

If a word count overflow has not occurred

during the previous word, the data flag (DF) will be set each time the O—-|~ DB pulse is produced.

If a

word count overflow is issued during a previous word, the write sequence continues, but the DF flip-

fIOp is not set with the result that all zeros are written in the remaining block on tape.
At the end of a data block, the parity check character is loaded into the DB by the LPB

DBO‘-5 pulse that is produced by the positive transition of the second MK BLK END level which is en-

abled by ST FINAL, CO (I), and WRITE DATA.

The LPB information is written on tape in the checksum

slot the same as a data word.
In the normal mode at the end of a data block, the positive transition of the ST CK (0) level

will set the DTF flip-flap and in the continuous mode the same transition will also set the DTF flip-fIOp

provided that a word-count overflow WC (0) has occurred during the previous data block. The Writers
are

disabled after the parity is written by the WREN flip-flOp which is reset by the ground WD EN level

produced when the data state is changed.

The control continues to change states if DTF is 'not set and

begins writing again in the block and the Operations repeat in the same sequence.

3-30

3.2.I5.6

Write all Function

The write—all

Function, specified by an octal 5 in the bits FRI—FR3 of the

function register, allows nonstandard Formats to be written on tape, such as the insertion of block numbers
or

codes at unusual locations on tape.

This function can be preceded by the search function which determines the position on tape

where the information will be written and can be implemented at any time after the tape has come "up—

to-speed" after only one C-SYNCH level has been generated, which may cause the writing to be displaced by a half word.
The positive transition of the WRITE ALL level,

sets

the W INH flip-flop (Drawing No. 5).

This prevents the WREN flip-flop from being set and inhibit writing at this time.
for the WRITE ALL function is shown in Figure 3-l3.

The timing sequence

The positive transition when counter flip-flop C2

is set, will reset W INH provided that the WC flip—flap

(Drawing No. 2), was previously set.

The

0 -'DB pulse is also generated at this time resulting in a I——-¢-DF pulse requesting a data break to
write the first word.

If the write all function is Specified before the middle of the area assigned on tape for a data

word, the first word will be written in the next data area which follows.

If the function is Specified

after the middle of the current data word position, the next data-word position will be skipped before

the data word is written.

however, the LPB

-—+

The write sequence then continues.

Parity is computed during this function,

DBO—5 pulse which is required to write parity is not produced.

The state register

continues to shift but has no effect on the operation.

In the normal mode, the I--*DF pulse will set the DTF flip-flop generating an interrupt re—

quest when enabled by ENI (I).

During continuous mode, when a word-count overflow occurs, the

WCO pulse will set the DTF flip-flap.

The WC (0) level at this time will also set the W INH flip—flop

inhibiting the writing of future words on tape; however, the tape motion will continue.
3.2. l5.7

Write Timing and Mark-Track

The Write timing and marl<-track functions,

specified by an

octal 6 in the function register is used to format a new- tape by recording the timing and mark-tracks

prior to the recording of data.
This function is only enabled with the WRTM/RDMK/NORMAL switch on the TCOI control

panel in the WRTM position and with the WRITE ENABLE/WRITE LOCK switch of the TU55 tranSport in
the WRITE ENABLE position. The control panel switch (Drawing No. 6) generates a SWTM level which
is gated with MRI (I) and the WRTM level to produce the TM ENABLE levels.

The TM ENABLE level

activates the I20 l<c clock producing the CKI and CKO outputs which generate the TPO and TPI

timing

pulses.
The CKO and CKI and TM ENABLE outputs are applied to the T TRK write amplifier (Drawing
No.

I5) to generate the pattern to be written on the timing track.
The TM ENABLE level (Drawing No. 6) resets the UP—TO-SPEED flip-flop resulting in a

O -—~WINDOW level which prevents mark-track information from being decoded.

DATA SYNCH flip—flap preventing synchronization of the control operations.

3-31

It also resets the

iifiiiiiiMd+T+T+T+f+L+f+i+f+i+Tif+f+i
W
W
I
CASEIZ(WRtTE

ALL

WHEN

COMMAND

WRlTE

DATA

WORD

DATA

WORD

DATA

WORD

r DATA WORD—.-

cz(¢))

ALL

W‘INH

O——-—DB$ DBRK

RQsT
i

__._._~

FIRST
WRiTTEN

WREN

CASE

z;(WR1TE

ALL COMMAND

WHEN

WRITE

FIRST WORD
MB——-DB -’l

[7";

DATA WORD
1N THlS SLOT

——l

C20»

ALL

W- INH

____:‘:i—r*

F. MB—FOB—‘i
FIRST WORD

DBéDBRK

RQST
WC

WREN

F‘FlRST

woRD WRITTEN
\N THlS SLOT

—+-|

Figure 3-13 Write a” Function, Timing Sequence
Diagram (sheet 1)

3-33

TP¢
TPI

iIlIIIIIIIIIJIIIIIIIIIIIMIIIIILLIIII

W
W
D ATA WORD
CASE

DATA

WORD

DATA WORD

DATA

WORD

[ DATA WORD—>-

I:(CM)
T

F—b;__

WRITE ALI.
F

WT INH
(D

WORD MB—’DB
WCO

LAET
0—» DB g DBRK

RQST

PULSEF‘I
l
.

I
WC

WREN

—>

DTF

"‘9—

H—L———i—I

|~——1-———P

(CM)

CHANGE FUNCTION
AFTER THIS TIME

CASE 2:(NM)
T
WRITE ALI.
F

T—l:

W~INH
CHANGE

FUNCTION
DURING
THIS TIME

L’EST W%RD_+_
3
'4

o—v-

OB$ DBRK RQST

—"

Figure 3-13 Write all Function, Timing Sequence'
Diagram (sheet 2)

3-35

The WRTM and SWTM levels are gated with associated outputs to produce the WRITE SET level

(Drawing No. 5).

At the C2 (0) transition, the WREN flip-flOp is set and enables the data track ampli-

fiers (Drawing No.

l5) to Write the information contained in the RWB. The first word that is written on

tape, however, will be within the 10 ft of tape designated for the reverse end code and will not be read

during the read tape function.

The WREN (l) level allows the RWB SHIFT LEFT pulses, the ROTATE DB/RWB pulses, and the
COMP RWB 0—2 pulses to perform the write Operation as described in

Paragraph 3.2.l6. The ROTATE

DB/RWB at the C2 (0) transition generates the 0—~D_B pulse which clears the DB and sets the DF flipfl0p, requesting the first word.

The programming format for the mark-track requires that the mark-track information appear
in bits 0,

3, 6, and 9 of the data word. The information received by the mark-track write amplifiers

(Drawing No. l5) is from RWBO (Drawing No. 4). Therefore, the only data bits which appear in this
buffer are bits 0, 3, 6, and 9.

This information also appears in data track l

tape which also receives

information from RWBO.

When the WRTM function is completed, the TM ENABLE levels are held active by the SWTM
and WREN (1)

inputs (Drawing No. 6). Enough TPO pulses are produced to cause the C2 (0) transition

necessary to reset the WREN fli'p-fIOp (Drawing No. 5) and prevents the disabling of the write amplifiers

with write current.

3.2.l6

Read and Write Sequences

The sequence of events that occur during the read and write functions are summarized in

Tables 3-2 and 3-3,

reSpectively.

Abbreviations and symbols used in these tables are defined in a list

of abbreviations in Chapter 2.

The times of each event are Specified in terms of control clock pulses

C2, C3 and timing pulses TPl

Illustrations of the bit contents of the RWB and DB sections after each

event has occurred are shown in
are

the diagrams in the last column of the tables.

The DB/RWB registers

shown on Drawing No. 2.

The events for the read Operation in Table 3-2,

are

programmed to assemble a l2-bit data

word in the DB for subsequent transfer to the MB of the PDP-8 during a data break.

At the start of the

assembly, the first three bits 0 through 2 of the data word are strobed from the read amplifiers into the
right half of the RWB (RWB 3-5). Bits 0 through 2 are then shifted left into the left half of RWB (RWBO-Z)
and the second three bits (bits 3 through 5) of the data word are strobed into RWB3-5.

parity check is performed on the first half of the l2-bit data word.
of the data word from the WRB into one half of the DB

strobe the last six bits (bits 6 through

ll)

(DB6-l l).

The

the first half

The same sequence is followed to

into the WRB and to perform a parity check on them.

rotation transfers bits 0 through 5 from DB6-ll to another half of the DB

from the WRB to DB6-l l

At this time,

next event rotates

Another

(DBO-5) and bits 6 through ll

The l2-bit word is completely assembled in the reSpective halves of the DB

and is ready for transfer to the BMB of the PDP-8.

3—37

0-2

out(3)

Operation

amplifier3-5.

R/W
RWB
from

RWB
5

0-2 am-

amplifier

W
left 3-5.
from RWB

shifted into

(Le.
5

am- 3-5. 3.

contents

6-”
DB

RWB

R/W RWB event
from into inas

RWB W 3-5. 3.
into from RWB event

left into in
as
II

shifted through strobed same

same
s
t
r
o
b
e
d
t
h
r
o
u
g
h
throughstrobed parity 0-5RWB
bits
o
u
t
p
u
t
s
Resulting thre strobed Bits: O'throughbits Bits: through 0-5: 6-I 0—5: bits Bits: through word outputs Bits:
First puts RWB: Word Bits and outputs RWB: Word Compute bits Rotate
RWB Word plifier Contents RWB: Word Bits and plifier Contents RWB: Word
into
bits

5).

into

8 9

DB DB

(I)

3-3

Table

(4A4)

(5D8)

(4A4)

(4A5)

DB/RWB
RWB ROTATE

LEFT

SHIFT

RWB

Operation Input LEFT

(4A5)
LEFT

(335)

Write

SHIFT

LPB

(2)

SHIFT
I
n
i
t
i
a
t
i
n
g
During RWB

Events
of

Sequence

‘9‘

RWB

TPI

C2(0)
Time C3(0)

C2(0)
C3(I)

C2(I)
C3(0)

C2(I)
C3(I)

first

data DB
w
o
r
d
.
check

last

parity first from

as emblydata

Event
of

Event

word

as emblydata

Begin half

word

as emblydata
of

Complete

half
first

of to

data half RWB

Perform

half
first Rotate word

No.

Event
3-38

word

as emblydata
of

Iete aIf

Begin half

Com last

0-5,
(i.e. RWB 0-5into
,

into

contents event and
5).

(3)

RWB

Operation RWB through0-5,
of

bits DB

parity data into

Resulting through 6-H 6-H

enginering
block. respective
its

data on

Computebits Rotate DBO—5: DB6-i: RWBO—S:

DB DB

mid le

(1)

the

Operation Input (335) DB/RWB(5D8)
(2)

(Cont)
3-3

word

LPB

Write

I
n
i
t
i
a
t
i
n
g
During RWB ROTATE
of

initiating

location

reading indicates completed.

‘V'

Table Events

input

l-—’

the

5C3) event
start
(e.g. after

from

Event

Sequence Time transition

asumed

ctable ombination

(0)
to
C2
1

check
Event parity data
contents

asem-

completeword
DB

Perform last Rotate and

Transfer bled PDP—8

read

The

No
6

Event

Numeral-leter—numeral

6).

Chapter schonotewnts

sequence (see

RWB

word RWB

half

and

Notes:
3-39

drawing Diagrams
3.

flip-flopfrom

BMB.

(3)

DF
set "n"

Operation buter word
and

data

"n—l
0

word

Resulting data request 0-5:
Clear

(1)

Table During

Events
of

transfered

half "n"
last word

data

lnitiating 0—. l—‘DF
DB

Sequence Time ROTATE

(0).

word

Event data

Request

C2
-

R
W
B
O
5
,
half 0-5.
of

last

into

bits

rotated into providesamplifiers.
DB

EC-In

word

event

.e.

RW§0:2bits -24.--same contents event
4. as

012 contents amplifiers.

-_A_f._

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complementwrite parity through
T

“3 6

OIr

DBé-l: RWBO-5: l2-bit DEC-5: DBé-l: RWBO-5: RWBO-2 DBé-l: RWBO—S: Complement provide putsContents RWBO—5: Compute bits
write DBO-5:
DB DBo-l

(508)
(5C8)

icompletionnstruction
Data

PDP—8 progres

transfered

RWB

LPB

COMP

RWB

V‘

TPl
-

transition

(0)
C2
-

(0) to
C2

(0)
C3

RWB bits l'n"

BMB
”n” from

word

(3B5)

-2
0

from

(4A8)

DB/RWB
ROTATE

BMB—+DB

(1)

Event DB/RWB WREN

"n-l"

inputs
and

into

0-5

(2)

Operation Input (5D8)(5D2)
Write
3-4

DB.

write

contents and

DB
to

word

of
2

bits write
and
0

Rotate and through
0

No.

Event
3-40

parity Section

Complementthroughcomplemented Computes
2

bits

word 3.14)

of or

through(see
0

bits "n"

bits in
as
and
left write same

ampli-

(3)

to
x

shifted inputs remain

as of

Resulting providedContents

in- of
as

0-2 4,

RWB Contents

4
3

bits

contents amplifier.

complementwrite

Operation
(Cont)! Write
3-4

During

Table Events
of

event

in Z

as '3?

same

RWB
into

-2

RWB

COMP

RWB
of

contents wrandite

Shift left 3-5

bits.
bits write
3

and

Complementthroughcomplemented
5

transfered

bits

"H
"n

word “n
data

(5D8) (5D2)
DB DE

0-—> 1—.

(sca)
DB

—.

BMB
of

icompletion nstruction progres.
At

PDP—8

word

trans- DB

write data

+1"

RWB conof

2
I

0-5:
r
e
q
u
e
s
t
tents inputs Clear
DBé-I: RWBO-5: I2-bit DB. 030-5:

bits

RWB

"n+I
and
word
set

DB/RWBWREN
ROTATE C2(I)-

(0)-C3(I)-

Sequence Time C3(I)-C2(O)
of

”

(I)

TPI

Event

provideamplifier.

DB/RWB
ROTATE

Initiating RWBSHIFT

Rrotated WBO-2 write bdatufear data

(5D8)

(4A8)

Input LEFT

Event

x
x

(5A8)

(2)

flip-flopfrom

and 6,
0—5 bits

Contents fiers. event RWBO-5: Complementprovide putsremain RWBO—5:
3.

(I)

0-5

BMB.

con- 7,
8

Operation RWBO-5

contents and RWBO—Z. next
DB of

Rotate and tents Request

No.
5

Event
3-41

BMB
word from

Data fer ed

bits

"n+1"

7
6

bits
"n"

7
6

DB6-I: RWBO-5:

block. drawing.

write the

DB6-l bits

(i.e.

providedContents

R_WB_0:_2 9101 contents event shifted event I3_W§_Q-2_t_o awrmpilitfieers. same RWBO-S provideamplifiers.
e
n
g
i
n
e
r
i
n
g
write
word amplifiers.
Operation contents Contents event l )in write same 10H contents'of inputsremain RWBO-Z obsolete 10H "n+l”bits mid le respective
"n+l
parity
c
o
m
p
l
e
m
e
n
t
c
o
m
p
l
e
m
e
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t
r
o
t
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t
e
d
05
.
while
through through remain
Resulting
wo
r
d
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i
n
p
u
t
s
R
W
B
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—
5
:
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W
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O
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5
:
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W
B
O
—
5
:
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DBé-l: RWBO-5: word input
to to
8

(3)

remain

6, DB

bits of

RWB

and
left

"n"

RWB

l0,

and

bits to

Lu-U“)
to
4.1”-I

into

0-5 of

I..

bits

"n"

data
a

as of

"n"

bits

bits as of

0-5 DB of
DB into

its
on

"n"

(I)

(2)

Operation RWBO—Z
Write Initiating
Input

(Cont)
3-4

(5A8)

(4A8)

‘V-

SHIFT

RWB

(5D8)

(4A8)
-2

LEFT

LPB

COMP

During

Table Events

(3B5)

RWB

COMP

for

‘

(0)
C3
of

”n
6

bits word
of

Complementthrough
8

complemented
write

and bits.

RWB

"n”

check
bits word
paritythrough "n" contents write

Perform bits word
6

and
Shift left

transition

bits woofrd

through

com- word

event

and n+l

step word

Complementthrough pletes Repeatcontinue write
write This

and bits. l nl

asumed
is

table
the

3-42

after

(e.g. DB

combination

Numeral-leter-numeral

and

RWB
of

contents

bit

sequence show
write
Diagrams

The
I.

No.

location completed.

complemented writing sequence
of

operation 584)indicates event

(0)
to
C2 0

”n”

initiating

C3(l)-C2(l)'TPi

C3(i)'C2(i)

Event

the

from

Event C2(l)~

Event

writing

DB/RWB
ROTATE

TPl

Sequence Time

Notes:

2. 3.

The events for the write operation in Table 3-4 are programmed to request a l2-bit data word
from the PDP-8, store it temporarily in the DB, and transfer it in 3—bit segments to the write amplifiers.

The First half of the I2—bit data word is stored in one section of the DB (DB 0-5) and the second half

(DB 6-l I) in another section.

A DB/RWB rotation transfers the first half of the I2-bit word into the

RWB and makes the first three bits (bits 0 through 2) available to the write amplifiers.

then performed on the first half of the data word.

the Write amplifiers.

In addition,

Then the contents of RWB are shifted left so that bits 3 through 5 re-

supplied
place bits 0 through 2 in RWB 0-2.
to

A parity check is

bits 0 through 2 are complemented and

Bits 3 through 5 are now available to the write amplifiers in normal

and complement form in the same manner as bits 0 through 2.

Event 7 on Table 3—4 rotates the second half of the data word into the RWB, where it is

available to the write amplifiers in the same sequence as that used for the first half of the word.

During

this event, the next data word is requested and each half is temporarily stored in its apprOpriate section
of the DB as at the start of the sequence.
as soon as

3.2.l6.l
occur are

The sequence for writing the stored data word can be started

the writing of the preceding data word is completed.

Read/Write Control Signals

The control signals which cause the read/write sequence to

produced by the logic shown on Drawing No. 5. The timing sequence in relation to the inforI

mation transfer is shown on Figure 3—6, sheets I and 2.

The following paragraphs are descriptions of the control signals and their origin.
a.

RWB SHIFT LEFT

The RWB SHIFT LEFT pulses are required to shift the RWB register to the left during the
read and write operations.

Although several conditions must be satisfied to generate these pulses, the

RWB SHIFT LEFT pulses for reading occur at every TPI, those for writing at every other TPO.

The network for generating RWB SHIFT LEFT pulses (shown on Drawing No. 4, location B7)
includes two DCD input gates.

One gate initiates pulses for the read operation and is enabled when the

write-enable (WREN) flip-flop is reset.

When the ground TPI

pulses appear at the input to the DCD

gate, the PA produces corresponding ground WRB SHIFT LEFT pulses.

The other DCD gate initiates

pulses for the Write operation and is enabled when the WREN flip—fIOp is set during the write functions.
The RWB SHIFT LEFT pulses generated are supplied as inputs to Drawing No. 4.

COMP WRBO-2
Ground COMP RWB 0-2 pulses are required to complement RWB flip—flops 0 through 2 in

Drawing No. 4,

to convert

the bits contained in the flip-flaps to the complementary form.

This Opera-

tion is performed because of the phase recording method used which requires that the word bits be fur-

nished in complementary as well as in normal form.
TPI

The COMP RWB 0 through 2 pulses occur at every

The DCD

input gate (Drawing No. 5,

location B7) for the PA which generates COMP RWB 0-2

pulses is enabled when the write-enable (WREN) flip—fIOp is set. When TPI pulses appear at the gate
input, the PA produces ground COMP RWB 0-2 pulses for application to RWB 0-2 (Drawing No. 4.) The
COMP RWB 0-2 output is also used as an enabling input for the generation of RWB V LPB pulses.

3—43

c .

Rotate DB/RWB

The ROTATE DB/RWB pulse, location B7, is required to transfer the contents of the RWB
the contents of DB 6-“ to DB 0-5, and the contents of DB 0-5 to RWB 0-5.

to DB 6-l l,

The pulse is generated when the counter register is reset by the l000-—>C3 pulse and by the
C3 (0) transition when the ROTATE ENABLE level is present.
with the mark-track information,

functions.

Before the counter is in synchronization

ROTATE DB/RWB pulses will occur during the search or read data

During the search function, this allows the ROTATE DB/RWB pulse to be synchronized with

the first six bits of the block number preventing the block numbers from being out of sequence.
d.

O-—°DB

The O—vDB pulse, location C6 (Drawing No. 5) is generated to clear the DB and to re-

quest the next word for data transfer during write operations.

During the write data function, the ST

REV CK (l) gated with the WRITE DATA level to generate the 0——*DB during the reverse check state to

allow the first word to be available when the ST DATA is entered.
duced at the second gate circuit by the ROTATE

The O—-’DB pulses are then pro-

DB/RWB when pulse WREN flip-fIOp is set.

During the write-all function the first data word is made available by the 0—> DB pulse
enabled by the third gate when the ROTATE DB/RWB pulse is produced.

The subsequent 0—- DB pulses

during this function are produced by the second gating circuit previously described.
e.

BMB—. DB

The ground BMB—-*DB pulse (Drawing No. 5, location BZ) is used to load the DB register in

Drawing No. 4 with the data bits, BMBO-BMB H from the PDP-8 memory buffer.
The BMB-DB ground pulse is produced by the T2 timing pulse input, from the PDP-8 at pin T

of connector W02], location A3.

The T2 pulse is inverted by Sl07 and gated into PA603 when the

ground DATA OUT level is produced. When a PDP-8 Data break has been granted, the -3V B(BREAK)
level at pin P of connector W02], location B5, is gated with -3V FRl (l) level, produced during a write
function or select error, to produce the DATA OUT levels.

3.2.l7

Longitudinal Parity Buffer Operation
The longitudinal parity buffer (LPB) (Drawing No. 3, location Bl-B4) performs the parity

check of the information in the data tracks.
zeros

Essentially the parity check reads the number of binary

in each half of l2-bit data words and forms a parity bit which is recorded in the checksum control

word at the end of the data block.

The checksum is computed by complementing the bits of the LPB

when the reSpective bit of the RWB is a 0.

The LPB register outputs are gated at location B2 (Drawing

No. 3) to produce the LPB=l and LPBfl levels.

If all LPB register flip-flops are not set during a read

data Operation, the LPBfl level will set the parity flip-flop (PAR)(Drawing No.

l4)

indicating a

parity error has occurred.
At the end of a write data operation, the contents of the LPB is gated into DB 0-5 to be written after the

lost data word.

3-44

3.2.l7.l

LPB Control

Signals

The signals which control the LPB operations are defined in the follow-

ing paragraphs and are produced by the logic shown on Drawing No. 5.

The timing sequence for these

signals are shown on Figure 3-6, sheets I and 2.
a.

O—Iv-LPB Pulse

The O—-LPB pulse clears the LPB at- the beginning of'each block.
ated by TPI

Six pulses are gener-

during the reverse check state, ST REV CK (I) to initialize the LPB register for computation

of the parity character.

However, only the last pulse is required for the Operation.

RWB ‘V' LPB Pulse

The RWB ’v‘ LPB pulse is used to perform the parity computation from the RWB to the LPB.
The parity is computed at the same time the ROTATE DB/RWB pulse is generated during a read operation
and at the same time the COMP 0—2 pulse is produced during the write operation.
c.

LPB—*DB 0—5
A LPB—“DB 0-5 pulse, location C7, is required at the end of the ST FINAL block to

initiate the formation of a parity bit for recording the checksum control word at the end of the data

block.
The enabling conditions used for the generation of the LPB—hDB 0-5 pulse are a WRITE
DATA level from the function decoder, ST FlNAL(l) level from the state counter, and a CO (I) level
from the control clock.

When a ground MK BLK END pulse from the mark-track decoding network ap-

pears at the gate 603, LPB—*DB 0-5 pulse is produced.

This pulse is transferred to the RWB and DB

registers in Drawing No. 4 for use in gating information received from LPBO (I) through LPB5 (l) into

correSponding DB 0-5.
3.2.l8

Power Clear (Initialize) and Error Stop Logic

The PDP-8 Processor produces, and transmits to the TCOI control

logic, a series of power clear

(PWR CLR) pulses whenever the processor is started or stopped. The PDP—8/l, under these same conditions,
generates a single pulse called lNlTlALlZE.
are

These pulses, inverted at location A3, Drawing No. l4,

applied to the PA, location C2, together with the error stop signal, to generate the PWR CLR + ES

pulses.

The error stop signal is produced by monitoring the outputs of the error flip-flops MKTK, SEL,

TIM, and END at location C4. When a (I) condition exists on any input to the NOR gate, as a result of
an

error, the ERROR STOP level will be produced.

The ground PWR CLR pulses are used to reset the

DATA SYNC flip-fIOp, WREN flip-flop, MF 0-2, DTF flip—flop, and the DF flip-flop when power is

initially applied or removed from the PDP-8.

In addition, the ground PWR CLR

ES signal will continu-

ally set the U + M flip—flop (Drawing No. 6) enabling the delay to prevent UP-TO—SPEED flip-flop from
being set during the detection of an error or when the PWR CLR (INITIALIZE) pulse(s) are received.

3-45

Increment CA Inhibit (+1

3.2.19

—’

INH)

(Drawing No. 5, location 36) is generated during the search function
to prevent the incrementing of the current address. When the current address (CA) is not incremented,
The H

-’

CA INH signal

the block number is placed in core memory at the same location for each block number transferred.
3 .2 .20

Address Accepted

The address accepted pulse (ADDR ACC) (Drawing No. 5, location B5) is received at connector W02l from

the PDP-8 during the 3-cycle data break.

fixed data address,

This pulse clears the DF flip-fl0p when the

Specified by the control, has been accepted for data transfer.

Transfer Direction

3.2.2]

Function bit FRl is used to indicate to the PDP-8 processor the direction of data transfer.

During Write functions, bit FRl of the function register is "one,' indicating transfer out of the PDP-8.
B RUN Level

3.2.22

The B RUN level input is received from the PDP-8 at location A2,
B RUN (0)

input,

MR1 and BMRl

3 .2 .23

Drawing No. 14.

The

indicating that the PDP-8 is stepped, is used to reset the motion register flip-flaps

(Drawing No. 2) and is applied to the TU55 tranSports to halt all tran5port motion.

Fixed Address

The fixed address is a preselected (wired) memory address Specified by the TCOl control.

The

address is determined by logic levels applied to DATA ADDR (0-1 1) at connector W02l location A5-A8,

Drawing No. 2.

This address determines the memory location of the data which is transferred to the

memory buffer in the PDP-8 during the

3.2.24

3-cycle data break.

lnterrupt Request
The INTERRUPT REQUEST level (location B], Drawing No. 6) from the control is used to

initiate a program interrupt in the PDP-8 processor.

the ENI

flip—fIOp (Drawing No. 2).

The interrupt enable is determined by the status of

When ENl is set, either an error flag EF (l) input or DECtape flag

DTF (i) will result in the request for a program interrupt.

3.2.25

ERROR FLAGS (EF)

The five flip-flops (Drawing No. 14) produce error signals at the occurrence of any of the
errors

listed under the STATUS B functions in Table 2-4.

When a specific type of error occurs, the error

detection circuits shift the appropriate flip-flops to a l state.

The error input conditions that initiate a specific type of error signal are as shown in

Figure 3—l4. All error flip-flops are cleared by either a ground B PWR CLR pulse or a ground pulse
from the output at location C6.

These pulses are produced when a BAC l0 (0) level from the PDP—8

and a XOR STATUS A pulse from the device selector appear simultaneously at the gate input.
3-46

When any error signal except PAR appears at one of the inputs to NOR gate location B4, the

gate produces an ERROR STOP output level .' This output is used in forming the PWR CLR+ES signal.
The same output is also passed through an inverter to produce an error Flag EF (l) or EF (0) level.

EF (l)

and EF (0) levels are also provided when a PAR error signal appears at the
input of inverter at location

B3.

ERROR CHECK

MK TK (1)
(MARK TRACK
ERROR)

END (l)
(END ZONE
ENTERED)

SEL (1)
(SELECT

ERROR)

PAR (1)
(PARITY
ERROR)

TIM (i)
(TIMING
ERROR)

NOTES-

TK (1)

coiomiib'VEAST IDLE(O)/\ST BLK MARKlO)
A

V MK

()4

SEL

ll)

ERROR
STOP
PULSE

MK BLK STARTVMK DATAV MK BLK END
(_

XSA

END

)

DYA[(WRTMASWTM)/\lFR|CI)/\(WR|TE OK)

V(WRTM/\SWTM)V(RDMK AREAD ALL)
v (s' l—NG_L-E__UNIT
b

)]

PAR (i)

STCK(0)I\READ DATAALPBiI

TIM (1)

(l-~DTFADTF(1))V(ROTATE OB/RwaAoch)

NO
Pnoc. mt.

V(xSAD/\ST BLK MARK(0)/\ST IDLE(0))

REQUEST

Figure 3-l4

Error Check Flow

Diagram

The EF (T) level resulting from any of the error signals is passed through another inverter to

produce a correSponding complementary EF (T) level.

Ground level EF (1) serves as one of the inputs to

the NAND gate (Drawing No. 6, location B2) For generating an lNTERRUPT REQUEST level while the
-3V EF(l) level is used as one of the inputs to the NAND gate (Drawing No. 2, location B8).

gate, and similar ones for Specific errors,

outputs which show the status of the TCOl

are

This

enabled by a PDP-8 READ STATUS B instruction to provide

3—47

Mark-Track Error (MK TRK)

3.2.25.I

(Drawing No. I4,

location

A MK TRK

error

signal is produced by MK TRK flip-flap

D6) when information read from the mark channel is erroneously recorded.

When MK TRK errors are detected by the input gating, the gating output enables the DCD input gate of
the flip-flop.

A ground CO(O)

pulse from the control clock will set the flip-flop to a I state.

A ground

CO(0) pulse indicates that a 6-bit character has been read from the mark-track and is in the window.
One input to the MK TRK gating circuit represents one of four mark-track codes which is
MK BLK START.

These codes appear at times throughout the reading of the DECtape.

Other inputs to the gating circuit prevent MK TRK error indications during a MOVE function
and during the ST IDLE and ST BLK MARK intervals.

These intervals are indicated by -3V ST IDLE(O)

The MK TRK decodings are not valid during the ST IDLE and ST BLK MARK

and ST BLK MARK (0) levels.

intervals because the control may not be synchronized with the

3.2.25.2

Select Error (SE)

A select error

DECtape at these times.

(SE) is produced by SEL flip—flop (Drawing No. I4) when

any of the select errors listed in Table 2—4 are detected.

After the input gate is enabled by an SE de-

tection signal, the flip-flop is set by a ground XSA DY pulse at the

gate. iinput.

The following conditions will result in an SE error:
WRTM

S—VVT—M-:

MCP switch is not set on WRTM while PDP-8 program is attempting to

Write timing and mark data on new tape.

FR3 (”WE—5K:

SWTM:

MCP switch is set on WRTM while PDP-8 program has Specified another

function.

DECtape transport control switch is set on WRITE LOCK while

PDP-8 program is attempting to write.
RD MK

at.

MCP switch is set on RD MK but READ ALL function is not speci-

fied? by PDP-8.
e.

The function register contains a binary III which is not a legal function.

In addition to the conditions
No.

listed, the single unit comparator circuits shown on Drawing

I4, (location A5) monitors the single unit line from the TU55 transports and generates a select error

(SE) output if the line indicates either no units or more than one unit have been selected. This is effec-

tively accomplished by noting the resistance of the SINGLE UNIT line and generating a ground select
error level (SE) if the resistance is not within the
Specified limits.
With no units connected, the voltage at pins E and K of comparator W520 is -9V.

The

voltage at pin D and pin L is held constant at -7.5V and -5V, reSpectively, by the resistance network
consisting of RI, R2, and R3.
cause a

When this condition exists,

pin D being more positive than pin E will

ground level SE output at pin H indicating a select error.

tance of the

When one unit is selected, the resis-

line which is effectively in parallel with resistor R5, results in a voltage at pin K which is

between the constant voltage at pin D of --7.5V and pin E of -5\/.

This voltage condition prevents the

difference amplifiers from conducting, and the output at pin H and N will be -3V indicating a no-error
condition.

If more than one unit is selected on the line, the resistance in parallel with R5 will be de-

creased resulting in a voltage at pin K more positive than the -5V at pin L and the difference amplifier

willi'conduct, resulting in

ground SE output at pin N.
3-48

3.2.25.3

Parity Error (PAR)

A PAR error signal is produced by PAR flip—flop (Drawing No.

I4,

location D4), during a READ DATA function if the LPB check at the end of the data block does not equal
I.

The READ DATA and LPB 7‘“ levels at the. inputs of NAND gate (location C4) indicate the error

condition and enable the DCD input gate to the flip-flop.

input will set the flip-flop.
3.2.25.4

A ST CK (0)

Timing Error (TIM)

Then a ground ST CK (0) pulse at the gate

pulse occurs at the end of a data block.

A timing error (TIM) is produced by the TIM flip-flap (Drawing No.

l4)

when any of the TIM error conditions listed in Table 2-4 are detected.
One Operation that produces
occurs

timing error is to ROTATE DB/WRB when 0 DE (I).

An error

because the data in the DB is no longer the same as it was at the instant the DF was set.

The ille-

gal operation is indicated to the TIM flip-flap when a ROTATE DB/WRB ground pulse appears at the DCD

input gate at a time when the gate is enabled by a DP (I) ground level.
Another TIM occurs when a I--> DTF ground pulse appears at the input to the DCD input
gate of PA 5603 (location D4) at a time when this gate is enabled by a DTF (I) ground level.

This ille—

gal condition means that the TCOI is attempting to set the DTF at the end of a current operation but that
the program did not clear the DTF at the end of the last operation.

The error is indicated to the TIM

flip-flop by collector triggering its I output with the ground level generated by the amplifier.
A third TIM occurs when —3V levels appear simultaneously at each input to 4-input NAND
gate

(location D3). This condition is illegal because it indicates that an attempt is being made to

READ DATA or WRITE DATA while passing over the data position on the tape.
and ST IDLE (0)

The -3V ST BLK MARK (O)

input levels indicate that the head is not passing over the ST BLK MARK and ST IDLE

blocks and therefore is passing over the data position.

The —3V XSAD input is a standard IOO-ns pulse

which is generated by PA 5603 (location CI (I4CI)) 400 ns after receipt of an XOR STATUS A pulse.

When all inputs to the NAND gate are -3V, the resulting ground level is used for collector triggering
the I output of the TIM flip-fIOp.

3.2.25.5

End Error

(END)

In normal operation the window register contains an end zone code

when the end zone of the DECtape is reached.

(222)

At this time the ground level at the window decoder out—

put serves to enable the DCD input gate to the END flip—flap (Drawing No. I4, location D3).
the next TPO appears at the gate input, the flip—flop is set.

When

A ground level at the 0 output of the END

flip-flop indicates an error it it is not eXpected by the program but is legitimate if used to indicate the
end of a normal Operation (e.g., rewind).
3.2.26

DECtape Flag (DTF)
The DECtape flag (DTF) network in the top center of Drawing No. 5 provides appropriate DTF

of Specific operations.
output control levels which indicate the completion
DTF flip-flop is cleared by either collector triggering its 0 output with a ground level from

NAND gate R123 (location D5) or by the appearance of a PWR CLR ground pulse at its direct clear

the
A ground level for clearing through the 0 output is provided when a -3V BAC II (0) level from

put.

PDP-8 and a -3V XOR STATUS A pulse appear simultaneously at the input to the NAND gate.

cleared, a ground I—fiDTF pulse from one of three input gating circuits will set
state

in-

3—49

When

the flip—flop to a I

The inputs to gating circuit location C6 indicate the following conditions:
a.

FR3 (1):

selection of any one of the SEARCH, READ ALL or WRITE ALL functions by

function register.

WRTM:

selection of WRTM function by function register.

FRO (i):

selection of CM of Operation.

When a FR3 (l) or WRTM ground level and 0 -3V FRO (T) level appear at the gating circuit

input, the resulting ground level enables the DCD input gate to PA 5603 (location C5). .A ground WCO

pulse input at the DCD input gate will produce the desired PA output pulse.

The ground WCO input

pulse is necessary because DFT settings in the NM are inhibited in the CM until a WCO has occurred.
One of the DCD input gates to PA 5602
and 0 -3V FRO (0)
a

(location C4) is enabled when 0 -3V WRTM+FR3 (i)

(indicating NM) appear simultaneously at the inputs to the NAND gate.

Then when

ground i--~DF pulse is applied to the DCD gate, the PA generates the desired i—fiDTF pulse.
Another input gating network controls the generation of a l—‘DTF pulse at the start of the

parity check in the NM or CM.

In the NM, either a ground level READ DATA or WRITE DATA input

from the function decoder plus a FRO (0) level

input enables DCD input gate (5D4).

Then the appearance

of a ground ST CK (0) from the state register (Drawing No. 3) at the start of the parity check causes the
desired l—vDTF pulse to be generated.

in the CM,

enabling input is applied to the DCD input gate

when the RD+WD, FRO (i) and WC (0) inputs are at -3V.

3.2.27

Panel Indicator Drivers
The indicator drivers in Drawing No. 12 control the indicator lamps on the Maintenance

Control Panel.

These lamps are remote indicators of various TCOl

flip-flaps and are lighted when 0 -3V

level from the 1 output of the re5pective flip-flap appears at the input of the indicator driver.

3-50

CHAPTER 4

INSTALLATION

This section contains general information on the installation and maintenance of the TCOi

DECtape control. The installation procedures refer to a single cabinet installation of both TCOl control
and two TU55

DECtape tranSports. installation information for mounting additional TU55 transports or

TCOl control in an existing cabinet is available upon request.

4.]

INSTALLATION PROCEDURES

The TCOl

DECtape control and associated TU55 tranSports are shipped either as a single unit

cabinet mounted and crated or as individual units to be installed in an existing cabinet.
tion information in this chapter refers primarily to cabinet mounted units as the

The installa-

requirements for separate

units vary according to the Specific existing system.

Upon receipt of the unit, an initial visual inspection should be performed to insure that no
obvious physical damage has been incurred during shipment.

4. l .l

Site

Preparation

No special site preparation is required for the installation of the TCOl unit.

clearance must be provided for proper installation and for servicing.

Adequate

Figure 4-l shows the installation

dimensions required by the unit.

When the cabinet is not physically attached‘to the PDP-8 console, both the power and signal

cables enter through holes provided in the base of the cabinet.
to

Casters are mounted on the cabinet base

enable the unit to be easily positioned and to allow sufficient clearance for the cables.

No sub-

flooring is normally required.
4. l .2

Environmental Conditions

The environmental conditions for the proper operation of the TCOl control unit are limited by
the magnetic tape used with
are an

DECtap‘e.

The acceptable environmental conditions for the magnetic tape

ambient air temperature between +60°F and +80°F with a relative humidity level between 40%

and 60%.

The TCOl

DECtape control operating environment is the same as that required by the PDP—8

processor.

The installation site must also be as free as possible from excess dirt and dust, corrosive
fumes and vapors, and strong magnetic fields

4.] .3

Power and Cable Requirements

The TCOl control and associated TU55 tranSports operate from single phase line voltage of
lO5V to

l25V, 60 (3/5.

The maximum current requirement is dependent on the number of TU55 transports

swmcmc
PLENUM
coon

“RX

——T
a: lo-

SWINGING
DOORS (2)

—‘—_—_"—a

TCOl

N ‘l

TAPE UNIT

mli

‘—
U o I:

(DI- =

“——“
co

blot

22'; —_"

SWINGING
oooasm

CABINET FRONT

Figure 4—1

included in the system.

TCOl Unit Single Cabinet Installation Dimensions

The maximum current requirement for the TCOl control is 4A, and each trans-

port requires approximately 2A maximum.

A Hubble,

3-terminal, 220V twist—lock flush receptical

rated at 30A with ground neutral should be installed near the site of the cabinet to allow connection to

the power cable supplied.

Figure 4-2 shows the internal and external cable interconnections as viewed from the rear of
the cabinet.

All other interconnections between TCOl

panel assemblies are facilitated by the panel

wiring which is exposed to the front of the cabinet.
Panel locations DTAOl
DTFOl

through

DTFl l

through DTAll are connected by panel wiring to panel locations

This allows the interconnecting cables to the PDP-8 processor to be attached to

the bottom of the TCOl unit and the cables to additional

locations

4.l .4

peripheral units to be connected to the DTA

DECtape Signal Connectors
The following cable connectors are used to interface the TCOl control to the TU55 tranSport

and lPDP-8 processor.

A description of the cable connectors are listed in the

C-l05.

4-2

Digital Logic Handbook

TO ADDlTIONAL
TU55 TRANSPORTS

AC POWER CABLE

COMMAND
CABLE
INFO CABLE

DTA l-H CONNECYED TO DTF 1‘11

CONTROL PANEL

SWITCH CABLE

FROM

NOV. 60 CYCLES

FIXED OR VAR PWR SUPPLY

H|098765432|DTF

ME34
MF34

ME35
MF35

PEOZ

BLOWER

PFOZ

T0 PDP-B
PROCESSOR

PEOS

PF03
PEOa
PF04
PE05

J01

J02
J03
J04

J05
J06

401
J08
J09
no
Jll

Figure 4—2

TCOI Control‘, Cable Diagram

4-3

92585356;

Connector W02l

Connector W023

l6 pin card connector to interface the PDP-8 and TCOl control.

l8 pin card connector which provides signals to the maintenance con-

trol panel and to the TU55 transport.
c.

to and

Connector W032 -32 pin double card connector which provides analog read/write signals

from the heads of the TU55 tranSport.

4-4

CHAPTER 5
MAINTENANCE

The information contained in the following paragraphs is required for servicing the TCOI

DECtape control.

Information pertaining to the TU55 transport is contained in the TU55

DECtape

Instruction Manual listed in Paragraph l.3.

The maintenance procedures contain a description of the switches and indicators on the
maintenance control

panel and general preventive maintenance instructions. When used in conjunction

with the PDP-8 Operating program and the TCOI maintenance programs, the control

panel provides a

visual indication of the operating state and content of the TCOI control.

5.]

MAINTENANCE EQUIPMENT

Table 5-l is a list of the equipment recommended for servicing the TCOI control in addition
to

the standard hand tools normally required.

Table 5-I
Maintenance

Equipment
Model

Manufacturer

Equipment
Multimeter

Triplett or Simpson

630—MA or 260

Oscilloscope

Tektronix

Series 540 or 580, with
Type CA differential

Head Cleaner kit (8705)

Potter

amplifier
P/ N A 425 484

Variable Power supply

DEC

730 or 765

Module extender*

DEC

I954

*Furnished with the PDP-8 Processor

5.2

MAINTENANCE CONTROL PANEL

The maintenance control panel on the DTA/DTB mounting panel is located at the cabinet

front, behind the access doors.

The panel contains a switch used in the Operation of the TCOI and in—

dicators which display the status and information in the control.

Table 5—2 lists the function and panel designation of the switch and indicators shown on

Figure 5-I

The number of indicators for each designation is enclosed in parenthesis in Table 4—2.

5—I

as“:

Figure 5-]

Maintenance Control Panels (Switch and

Indicators)

Table 5-2
Switch and Indicators
(Maintenance Control Panel)
'

Designation

Function

STATUS (Indicators)
USR (3)

Indicates the contents of the unit select register.

MR (2)

Indicates the status of the motion control registers which selects; stap, go, forward, reverse.

FR (4)

Indicates the contents of the function register.
FR (0)

Normal/Continuous Mode.

FR (I-3)

ENI (I)
US (I)

Octal code of the selected function.

Lights to indicate that the TCOI is enabled to
the PDP-8 program interrupt.
Lights to indicate that the selected TU55 tranSport
has reached the required Speed for reading or

writing.
WC (1)

Lights to indicate a word count overflow has not
yet occurred.

MR (Indicator)

(I)

Lights to indicate that a mark-track error has
been detected.

END (Indicator)

(I)

Lights to indicate that the end of tape has been
detected.

SE (Indicator)

(I)

Lights to indicate that a function select error, or
no transport selected, or more than one
transport
selected.

PAR (Indicator)

(I)

Lights to indicate that a parity error has been
detected.

TIM (Indicator)

(I)

Lights to indicate a program timing fault.

STATE (Indicators)
BM (l)

Lights to indicate that the Block Mark state is
activated.

RC (I)

Lights to indicate that the Reverse Check state is
activated.

DO)

Lights to indicate that the Data State is activated.

F(l)
GU)

Lights to indicate that the Final State is activated.

HI)

Lights to indicate that the Idle State is activated.

Lights to indicate that the Check State is activated.

5-3

Table 5-2 (Cont)
Switch and Indicators
(Maintenance Control Panel)
Function

Designation
DATA BUFFER (Indicators)

(O-2)(3-5)(6-8)(9-I I)

Indicates the content of the data buffer register.

RWB (Indicators)

(0-2)(3-5)

Indicates the content of the read/write buffer

Lights to indicate that the DECtape flag is set.

(I)
DF (Indicator)

Lights to indicate that a data flag is set requesting

(I)

data break.

W (Indicator)

Lights to indicate that the write enable level is

(1)

activated.
LPB

(Indicators)

(O-2)(3-5)

Indicates the content of the longitudinal
buffer.

parity

COUNTER (Indicators)

C0,CI,C3

Provides indication of the 6-count function of the
counter register used for mark—track decoding
.

C2,C3

5.3

Provides an indication of the 4--count Function of
the counter register used for assembling data
words.

DEC MODULES

The standard DEC modules used on the TCOI control are described in Digital Logic Handbook
C-IO5 except for modules G882, GOO8, and G009, which are described in the following paragraphs.
One spare module of each type is generally recommended to facilitate maintenance of the TCOI control.

5.3.]

Module Locations and Complement
The position of the modules within the mounting panels,

shown in Drawing D-MU-TCOI-9 (sheets I and 2)of Chapter 6.

the circuits that are contained on the module.

viewed from the wiring side , is

In this drawing, each module is repre-

sented by a rectangle with the module type designation at the top.
to show

Each rectangle in turn is subdivided

In general, the circuits are identified by the

logic signa|(s) available at the circuit outputs.
Table 5-3 lists the type and quantity of modules used in the TCOI and references the figure
number of the module schematic diagrams (Figures 5-5 through 5-24).

5-4

5.3.2

Circuit Descriptions

The following circuit descriptions are providedto supplement the information in the Digital

Logic Handbook C-iO5.
a.

MANCHESTER READER/WRITER G882
The Manchester Reader/Writer G882 is a standard size FLIP CHIP module for use in read-

ing and Writing one channel of DECtape Type 55 Microtape.
and one high-gain differential read amplifier.

Each module contains two write amplifiers

The read amplifier saturates with a l mV input.

MASTER SLICE CONTROL, G008, and Sense Amplifier G009
The Master Slice Control, G008, is a standard size FLIP CHIP module which supplies

slice and clamp voltages for the 2-input Sense Amplifier G009.
and G009 modules are shown on Figures 5-2 and 5-3,

The schematic diagram for the G008

reSpectively.

Terminal connections between modules G008 and G009 are as follows.
G008

G009

Voltage

Terminals

lst stage clamp

M,B

K,B

2nd stage clamp

N, B

slice

H,A

S, D

Each voltage circuit contains a zener diode network with silicon diodes for temperature

compensation. Emitter follower stages provide current drawing capability and low impedance outputs.
The first stage clamp voltage is fixed while the second stage clamp voltage and the slice voltage are

adiustable.
The output characteristics are as follows.
ist Stage Clamp M,B is fixed at +3.9V with reSpect to -l5\’.

2nd Stage Clamp N,B is variable from +0.6 to +1 T .3V with reSpect to -15V.
Slice Level H,A is Variable from 0 to -l l .6V with reSpect to +l0V.

The power requirements of the module are

5-5

-i5V/45 ma; +lOV(A)/0 ma;

and +lOV (B)/7O ma.

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Sense

Amplifier, G009

Table 5-3
TCOI Module Complement
Number

Required

Type

Description

Figure

G008

Master Slice Control

5-2

G009

Sense Amplifier

5-3

G882

Manchester Reader/Writer

5-4

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Diode Network

5-5

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Inverter

5-6

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Diode Gate

5-7

RI l3

Diode Gate

5-8

Rl23

Diode Gate

5-9

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Diode Gate

5-l0

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Binary-to-Octal Decoder

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Delay (One Shot)

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Integrating (One Shot)

5-I7

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Variable Clock

5-l8

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Pulse Amplifier

5—I9

5603

Pulse Amplifier

5-20

W005

Clamped Load

5-2I

W050

30 MA Indicator Driver

5-22

Wl03

Device Selector

5—23

W520

Comparator

5-24

5-I3
5-I4

5-I6

Module Characteristics

The terminals for the module are shown in Figure 5-4.
are as

The input and output characteristics

follows.
Reader Inputs E, D

are

differential signals centered at ground.

is approximately 400 ohms to ground.

A nominal

The input impedance

input signal is a sine wave between

5 kc and 30 kc.
Reader Outputs U,V

are

standard DEC levels of —3V and ground.

drive I0 mo of load at ground.

The outputs can

Writer lnEuts

N, R, and P are standard DEC levels of -3V and ground.

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load of 2 ma is shared by the inputs at ground level.
Writer

OutEuts

J and K,

are

nominal l80—ma current pulses from ground to —l5V.

The power requirements of the module are +l0 (A)/l8 ma and -l5 (B)/235 ma.

The marginal

check limits in both cases are i20%.

Both the reader and the writer circuits are returned to a common C, F ground.

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Figure 5-10

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R 4

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Figure 5-H

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Figure 5-12

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Figure 5-16

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Figure 5-17

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Figure 5-18

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Device

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Figure 5--24

5.3.3

Comparator, W520

Module Replacement Procedure

When necessary to remove modules, the procedure is as follows.
Turn off all power to the Type TCOl

b.
‘

damage

DECtape Control.

Gently pull the module from the mounting panel.

to plug connections and

Use a straight even pull to avoid

the printed-«wiring board.

Access to adjustment controls on the module or access to

signal tracing points can be gained

by removing the module, connecting a Type W980 Module Extender into the mounting panel, and inserting the module into the extender.
5.4

POWER SUPPLY 779
Power Supply 779 is a dual power

supply unit designed for installation on a plenum door.

One of the supplies furnished +lOV and -l5V suitable for

logic power; the other is a lightly filtered,
center-tapped 30V floating supply suitable for furnishing power to solenoids, etc. The -l5V outputs of
the power supply are connected in

parallel to supply logic power to both the TCOl and TU55 tranSports.

The schematic diagram of this power
are

supply is shown in Figure 5-25 and the electrical characteristics

listed in DEC System Module Handbook C-lOO.

lnput voltages:

l15 Vac, 60 0/5 (105V to- l25V)

Output voltages:

+l0V; -15V; center-tapped 30V (+l5V ~15V)

Maximum output current:

8A (limited by curve)

Line load regulation:

+lOV regulated to 9-] iv;
regulated to l4-léV

(under all line and load
conditions)

all +l5V supplies

Ripple:

lV at +lOV;

Size frequency regulation:

i3%

Maximum voltage between

300V

500 mV at —l5V;

2.5V at 30V

output and chassis:

ORANGE

-0———-——‘

lI5V AC

60m

I
"

BROWN

______

EML

MFG

[:10INCH

‘

YELLOW

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35.000
MFD
25v

I5v

I
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_______

YELLOW

GREEN
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GREEN

INDICATED

TAB-

PLASTIC

BUSHING

TERMINAL

STRIP

Figure 5-25

5.4.]

I5V

JONES

enowm

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MFD
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Power

Supply Type 779, Schematic Diagram

Mechanical Characteristics
Pertinent mechanical characteristics of Power Supply 779 are as follows.

5.4.2

Panel width:

16—5/8 in.

Finish:

Chromate conversion, coating

Power input plug:

Jones No. 141

Power output plug:

Heyman tab terminals

strip

Power Supply Checks

The use of a multimeter permits output voltage measurements to be made on the Type 779
power supply without disconnecting the power supply.

An oscillosc0pe should be used to measure the

peak-to-peak ripple content of each dc output voltage.

Because the power supply is not adjustable,

unit that does not meet the following tolerances should be considered defective and steps should be taken
to correct the deficiency!

Naminal

Output
Voltage

Voltage
Outputs
(volts)

Output Ripple Voltage
(volts)

Range

(vo|t_2_
9-l l

l4—l6

0.5

+10
-l5
$15

Maximum Peak-to-Peak

(for center tapped 30V circuit)

5.4.3

Marginal Checks
Marginal checks are performed to aggravate borderline circuit conditions within the control

logic and thus produce observable faults.

By recording the bias voltage levels at which circuits fail,

progressive deterioration can be plotted and expected failure dates can be predicted. This procedure

provides a means for planned replacement. Marginal checks are also useful as a troubleshooting aid to
locate marginal or intermittent components (e.g. , deteriorating transistors).

Marginal checks are performed by operating the logic circuits from an adiustable external
power supply located in the PDP-8 or a DEC Type 734B Dual Variable Power Supply.
not varied for

PDP-8/I supply is

marginal checks; marginal checks however, can be made with an external supply. Raising

the bias level above +lOV increases the transistor cutoff required to be overcome by the preceding tran-

Lowering the bias level below +lOV reduces the tran-

sistor, thus causing a below-par transistor to fail.
sistor base bias and noise rejection.

This procedure provides detection of high-leakage transistors and

simulates high-temperature conditions for checking thermal runaway.

Raising and lowering the -l5\/

supply has little effect on the logic circuits because the collector load voltage of most modules is
clamped at -3V.

It does,

however, increase and decrease the output pulse amplitude of the pulse ampli-

fier circuits (e.g. , the delay circuits) and then provides a sensitivity check of the circuits which follow.

CAUTION

Increasing the -l5V power to a value more negative than -l8V
will cause damage within the logic circuits.

The panel for conducting marginal checks of the Type TCOl
left-hand side of the wired panel assembly.
from the marginal check bus;

When switched on

DECtape Control is located at the

(up), switches. 1A through lF apply power

when switched off (down), normal power is applied.

the tap switch on each panel selects the marginal check voltage of +IOV.

the fixed voltage of +lOV.

The ”up" position of

The ”down” position selects

The lower switch of each panel performs the same function with the -l5V.

A color-coded connector on the right side of each panel connects the normal and marginal

operating voltages to the marginal check panel. The normal and marginal power buses are common to
all panels.
to

The normal power bus is connected to the Type 779 Power Supply, the marginal power bus

the marginal check power supply on the PDP-8.

5-20

A marginal check is performed as Follows.
a.

Set selector switch on marginal-check power supply to +10 Mo and adiust the power

supply output for H 0V
b.
Start DECtape operation in a normal program or in a routine which fully utilizes the cir.

cuits in the rack to be tested.

if no suitable program is available in the normal system application,

lect an apprOpriate maintenance routine.

se-

The maintenance programs provide basic exercises of Specific

functions and. scape loops for these functions as well as a routine which redundantly exercises all

functions.

Set the tap normal/marginal check switch on the panel to be tested to its "up"

Decrease the marginal—check power supply output voltage until normal system operation

interrupted.

Record the marginal-check voltage.

position.

if desired, locate and replace the marginal tran-

sistors at this time.
e.

Restart DECtape Operation and increase the marginal—check power supply output voltage

until normal operation is interrupted.

Record the marginal-check voltage.

If desired, locate and re-

place the marginal transistors at this time.
t.

Set the t0p normal/marginal check switch in step c to its "down" position.

Repeat steps a through i for the center normal/marginal switch on the panel being tested.

Set selector switch on the marginal-check power supply to -15 mc and adiust the power

supply output for -l5V.
i.

Repeat step b.

Set the bottom normal/marginal switch on the panel being tested to its "up" position.

Repeat steps at and e and then return the bottom normal/marginal switch to its ”down"

Adiust the output of the marginal-check power supply to 0V and set the selector switch to

position.
its ”off"

5.5

position.
POWER CONTROL PANEL (Type 834)
The Power Control Panel is mounted on the plenum door at the rear of the cabinet and is used

in conjunction with the

Figure 5-26

Type 779 Power Supply.

The schematic diagram of the panel is shown on

”Ia BLK

#Ianeo

RED

I
I
I
i

#IAWHT

,
'
l

msv c~
FAST OFF

.1
20-

3o—

NOTES:
8 C2 CAPACITOR BATHTUB'DEC PURCH SPEC#CAF-OOOI
2X.IMFO GOOVDC CORNELL DUBLIER.
SWITCH #1 ST52P,
EM-l |l5VAC EBERT ELECTRONICS.
CBI CIRCUIT BREAKEvao-ZZO-IOI 20AMPS Z5OV. 60 CYC-CURVE4
GENERAL ELECTRIC 20 SF4 54, NEW
DI.DZ THYRECTOR

SI
Kl RELAY

TOGGLE

50-

Figure 5-26

Power Control Panel Type 834

5-21

PREVENTIVE MAINTENANCE

5.6

Preventive maintenance consists of procedures performed prior to the initial operation of the

equipment and periodically. during its operating life.

These procedures include visual inSpections,

cleaning, mechanical checks, and circuit element checks. Marginal checks are also conducted when
considered necessary to aggravate border-line conditions or intermittent failures so that they'can be
detected and corrected.

A log book should be

available-for'recording specific data which indicates the

rate of performance deterioration and provides information for determining when components should be

replaced.
Except for marginal checks all preventive maintenance procedureslshould be performed once
a

month or every 200 operating hours, whichever occurs first.

5.6.l

Mechanical Checks
The following mechanical checks should reveal any substandard conditions in the mechanical

operation of the control unit.
a.

Clean the exterior and the interior of the control by‘means of a vacuum cleaner or by

using clean cloths moistened in a nonflammable solvent.
b.

Clean the air filter at the bottom of each cabinet.

Remove the filter by removing the

fan and housing which are held in place by two knurled and slotted screws.

water,

Wash the filter in soapy

dry in an oven or by Spraying with compressed gas, and spray with Filter-kote (Research

Products Corp., 1015 E.

Washington Ave., Wisconsin, 53703).

Clean all rotary switches with a Spray cleaner such as Contactene.

cl.

Lubricate door hinges and casters with a light machine oil.

Wipe off excess oil

Visually inspect the TCOl for completeness and general condition.
Inspect all wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and

mechanical security.

Repair or replace any defective wiring.

lnSpect switches, controls, knobs, iacks, connectors, transformers, fans, capacitors,
lamp assemblies, etc. Tighten or replace as required.
g.

InSpect switches for binding, scraping, misalignment, and positive action. Adiust,

align, or replace as necessary.
i.

lnSpecl' all racks of logic to assure that each module is securely seated in its connector.

lnSpect power supply capacitors for leaks, bulges, or discoloration. Replace any capa—
citors exhibiting these signs of malfunction.
i.

5—22

CHAPTER6

ENGINEERING

DRAWINGS

This chapter contains the logic block diagrams and module location diagrams of the TCOI

DECtape Control. The equivalent drawings for the TU55 DECtape tranSport are contained within the
TU55 Instruction Manualo

6.I

SYMBOLS AND DESIGNATIONS

The block and signal symbols used on the logic diagrams are defined in Chapter IO of the
PDP-8 Maintenance Manual together with a

description of standard DEC logic levels. The signal desig-

nations assigned are defined in Table 2-6 of this manual.

6.2

Drawing List
Table 6-I lists the pertinent engineering drawings referenced in this manual.

relate to the discussions in this manual and do not necessarily reflect the latest revisions
in the equipment.

These drawings

incorporated

When discrepancies exist between the drawings contained in this manual and the

drawings shipped with the device, the latter should be assumed to be the correct drawing set.
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