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DEC-08-I2AB-D
December 1969
123 pages
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DEC-08-I2AB-D
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INSTRUCTION MANUAL DECTAPE CONTROL UNIT TYPE TC01 DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS DEC-08-I3AB-D DECTAPE CONTROL UNIT TYPE TC01 INSTRUCTION MANUAL April 7968 DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS 1st Printing September 1968 2nd Printing (Rev) April 1968 3rd Printing March 1969 4th Printing July 1969 Copyright (C) 1968, 1969 by Digital Equipment Corporation InstrucHon times, operating speeds and the like are in- cluded In this manual for reference only; they are not to be taken as specifications. The following ore registered trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC PDP FLIP CHIP FOCAL COMPUTER LAB DIGITAL CONTENTS CHAPTER 1 INTRODUCTION 1 .1 General Description 1-1 1 .2 Referenced Documents 1-2 1 .3 Physical Description 1-2 1 .3.1 Equipment Characteristics 1-3 1 .3.2 Electrical Requirements 1-5 ^ LI A DTCD O CHArl cK z OPERATION AND PROGRAMMING 0 A UtCtape rormat 2-1 Z.I.I Mark-Track Format 2-3 Z.Z DbCtape Instructions 2-6 btatus Register A Functions 2-7 o o o z.z.z Status Register B Functions 2-8 z.o Control Modes and Functions 2-10 Z .*f Control Functions 2-10 iViove z- 0 1 . 1 z.z. Z ^. . 1 1 1 o in z- ? 4 ? 1 r\eaa uara 2-1 2 4 4 R^nH All 9 1 Z- 9 4 vvrire '^ 9 4 6 1 uara 1 1 2-1 WritP All V V lie rtl z- 1 1 Write Timing and Mark Tracks 2-1 1 Enable to the Interrupt O 11 2-1 Programmed Operation O 1O 2-13 2.5.1 Simplitied Search Procedure 2-15 2.5.2 Bootstrap Loading 2-16 2.5.3 Upper Bound Protection for Data Transfer 2-16 2.5.4 Write/Read in Opposite Direction 2-16 2.5.5 Turn Around Specifications 2-16 2.6 Available Software 2-17 2.6.1 Subroutines 2-17 2.6.2 Library Calling System 2-18 9 4 ^.7 / Z . 9 4 fl 9 Z 0 . OCT 1 1 iii CONTENTS (continued) 2.6.3 Performatting Tape Programs 2.6.4 Maintenance Programs 2.7 Symbols and Abbreviations 2-18 O 1Q O L1 i- 7 1 CHAPTER 3 PRINCIPLES OF OPERATION 3-1 3.1 Functional Description 3.1 .1 Information Flow 3.1 .2 Command Flow Registers 3.2 Detailed Logic Operations 3.2.1 Basic Read/Write Logic 3.2.2 Read and Write Amplifiers 3.2.3 Device Selector Logic 3.2.3.1 STATUS A Decoding 3.2.4 Status Register B and Skip Instructions 3.2.5 Unit Select Logic 3.2.6 Motion Control 3.2.7 Function Selection 3.2.8 Interrupt Enable 3.2.9 New Unit/Motion Select 3.2.10 Timing Pulse Generation 3.2.11 Counter Register (C) 3.2.12 Window Register (W) Counter Synch Level (C-SYNC) 3-23 3.2.12.1 3.2.12.2 Start Block Marks (MK BLK MK) 3-23 3.2.12.3 Data Marks 3.2.13 State Register 3.2.14 Memory Field Register (MF) 3.2.15 Function Operq^tions 3.2.15.1 Move Tape 3.2.15.2 Search 3.2.15.3 Read Data 3.2.15.4 Read All Function 3.2.15.5 Write Data Function 3.2.15.6 Write All Function 3-1 3-1 3-4 3-10 3-12 3-12 3-12 3-13 3-14 3-15 3-15 3-15 3-15 3-16 3-17 3-17 3-24 3-25 3-27 3-27 3-27 3-28 3-28 3-29 3-30 3-31 iv CONTENTS (continued 3.2.15.7 Write Timing and Mark-Track 3.2.16 Read and Write Sequences 3.2.16.1 Read/Write Control Signals 3.2.17 Longitudinal Parity Buffer Operation 3.2.17.1 LPB Control Signals 3.2.18 Power Clear and Error Stop Logic 3.2.19 Increment CA Inhibit (+1 3.2.20 Address Accepted 3.2.21 Transfer Direction 3.2.22 B RUN Level 3.2.23 Fixed Address 3.2.24 Interrupt Request 3.2.25 ERROR FLAGS (EF) 3.2.25.1 Mark-Track Error (MK TRK) 3.2.25.2 Select Error (SE) 3.2.25.3 Parity Error (PAR) 3.2.25.4 Timing Error (TIM) 3.2.25.5 End Error (END) 3.2.26 DECtape Flag (DTF) 3.2.27 Panel Indicator Drivers CA INH) CHAPTER 4 INSTALLATION 4.1 Installation Procedures 4.1 .1 Site Preparation 4.1 .2 Environmental Conditions 4.1.3 Power and Cable Requirements 4.1 .4 DECtape Signal Connectors CHAPTER 5 MAINTENANCE 5.1 Maintenance Equipment 5.2 Maintenance Control Panel 5.3 DEC Modules 5.3.1 Module Locations and Complement CONTENTS (continued) 5.3.2 Circuit Descriptions 5-5 5.3.3 Module Replacement Procedure 5-18 5.4 Power Supply 779 5-18 5.4.1 Mechanical Characteristics 5-19 5.4.2 Power Supply Checks 5-19 5.4.3 Marginal Checks 5-20 5.5 Power Control Panel (Type 834) 5-21 5.6 Preventive Maintenance 5-22 5.6.1 Mechanical Checks 5-22 CHAPTER 6 ENGINEERING DRAWINGS 6.1 Symbols and Designations 6-1 6.2 Drawing List 6-1 ILLUSTRATIONS 1- 1 TCOl System Configuration 1-1 2- DECtape Track Allocation 2-1 2-2 DECtape Control and Data Word Assignments 2-2 2-3 DECtape Recording Format 2-3 2-4 DECtape Mark Track Format 2-4 2-5 Status Register A, Format 2-7 2-6 Status Register B, Format 2-8 2- 7 Turn Around Sequence Diagram 2-17 3- Type TCOl DECtape Control Functional Block Diagram 3-2 3-2 Status Register A, Instruction Flow Diagram (Part I) 3-5 3-2 Status Register A, Instruction Flow Diagram (Part II) 3-6 3-2 Status Register A, Instruction Flow Diagram (Part III) 3-7 3-2 Status Register A, Instruction Flow Diagram (Part IV) 3-8 3-2 Status Register A, Instruction Flow Diagram (Part V) 3-9 3-3 Status Register B, Instructions Flow Diagram 3-10 3-4 Read/Write Logic and Waveforms 3-10 3-5 Slicer Network Waveforms 3-14 3-6 Timing and State Sequence Diagram (Sheet 1) 3-19 3-6 Timing and State Sequence Diagram (Sheet 2) 3-21 1 1 vi CONTENTS (continued) 3-7 Mark-Track Decoding (C-SYNCH) 3-23 3-8 Mark-Track Decoding (MK BLK MK) 3-24 3-9 Mark-Track Decoding (MK BLK START-210) 3-24 3-10 Mark-Track Decoding (MK BLK START-010) 3-24 3-11 Mark-Track Decoding (MK DATA 070) 3-25 3-12 Mark-Track Decoding (MK BLK END) 3-25 3-13 Write All Function, Timing Sequence Diagram (Sheet 1) 3-33 3-13 Write All Function, Timing Sequence Diagram (Sheet 2) 3-35 3-14 Error Check 3-47 4-1 TCOl Unit Single Cabinet Installation Dimensions 4-2 4-2 TCOl Control, Cable Diagram 4-3 5-1 Maintenance Control Panels (Switch and Indicators) 5-2 5-2 Master Slice Control, G008 5-6 5-3 Sense Amplifier, 5-4 Manchester Reader/Writer, G882 5-8 5-5 Diode Network, R002 5-8 5-6 Inverter, SI 07 5-9 5-7 Diode Gate, S1 1 5-9 5-8 Diode Gate, Rl 13 5-10 5-9 Diode Gate, R123 5-10 5-10 Diode Gate, R141 5-11 5-11 Binary-to-Octal Decoder, 5-12 Flip-Flop, R201 5-12 5-13 Dual Flip-Flop, S202 5-12 5-14 Triple Flip-Flop, S203 5-13 5-15 Dual Flip-Flop, S205 5-13 5-16 Delay (One Shot), R302 5-14 5-17 Integrating (One Shot), R303 5-14 5-18 Variable Clock, R401 5-15 D- V rulse AmpI itier, S602 5-15 5-20 Pulse Amplifier, S603 5-16 5-21 Clamped Load, W005 5-16 5-22 30 MA Indicator Driver, W050 5-17 5-23 Device Selector, W103 5-17 1 Flow Diagram G009 5-6 SI 51 5-11 vii CONTENTS (continued) 5-24 Comparator, W520 5-18 5-25 Power Supply Type 779, Schematic Diagram 5-19 5-26 Power Control Panel Type 834 5-21 TABLES 1-1 DEC Documents 1-2 1- 2 Summary of Equipment Characteristics for the TCOl DECtape Control 1-3 2- 1 Mark-Track Coding 2-5 2-2 TCOl DECtape Instruction List 2-6 2-3 Status A-bit Assignments 2-7 2-4 Status B, Bit Assignment 2-9 2-5 Control Function Procedures and Errors 2-12 2-6 Summary of Timing Data for TCOl Operation 2-15 2- 7 Symbols and Abbreviations 2-19 3- Counter Register Sequence 3-17 3-2 Sequence of Block Marks and Control States 3-26 3-3 Sequence of Events During Write Operation^' ^ 3-38 3-4 Sequence of Events During Write Operation (1) 3-40 5-1 Maintenance Equipment 5-1 5-2 Switch and Indicators (Maintenance Control Panel) 5-3 5- 3 TCOl Module Complement 5-7 6- 1 Engineering Drawing List 6-1 1 ENGINEERING DRAWINGS BS-D-TCOl-0-2 MF, USR, MR, FR 6-3 BS-D-TCOl-O-3 WINDOW, MK TRK, STATE, LPS 6-5 BS-D-TC01-0-4 Error Flags 6-7 BS-D-TCOl-0-5 Control 6-9 BS-D-TCOl-0-6 TP GEN TT GEN 6-11 MU-D-TCOl-0-9 Utilization Module List (Sheet 1) 6-13 MU-D-TCOl-0-9 Utilization Module List (Sheet 2) 6-15 BS-D-TCOl-0-12 Panel Indicator Drivers 6-17 BS-D-TCOl-0-13 Maintenance Control Panel 6-19 BS-D-TCOl-0-14 Error Flags 6-21 BS-D-TCOl-0-15 R/W AMPS, SP GEN, TEST CONN. 6-23 viii CHAPTER 1 INTRODUCTION This manual, together with the referenced documents, provides Information on the installation, operation, and maintenance of the Type TCOl DECtape Control, manufactured by Digital Equipment Corporation, Maynard, Massachusetts. The TCOl buffers and controls information transfers between a TU55 DECtape Transport and its associated data processor. This document assumes use of the TCOl in conjunction with either a DEC PDP-8 or PDP-8/I Programmed Data Processor. noted otherwise, all references to the PDP-8 also apply to the PDP-8/I. Except where specifically The level of discussion pro- vided in this document assumes a prior knowledge and understanding of the TU55 DECtape Transport and the particular processor (PDP-8 or PDP-8/I) provided with the user's system. GENERAL DESCRIPTION 1.1 The Type TCOl DECtape control is used to buffer and control the transfer of binary data be- tween the PDP-8 processor and up to eight Type TU55 DECtape transports. The system configuration is shown on Figure 1-1 PDP-e ^ r\ PROCESSOR \j TCOl TU55 DECTAPE CONTROL DECTAPE TRANSPORTS II UP TO SEVEN ADDITIONAL TU55 TAPE TRANSPORTS Figure 1-1 TCOl System Configuration The TU55 DECtape transport is a bidirectional device consisting of a magnetic tape transport and solid state logic. During both input and output operations, the TCOl receives data and control information from the processor and generates the med commands. appropriate signals to the selected transport to execute the program- Binary information Is transferred between the tape transport and the computer as one 12-bit computer word every 133-1/3 ps. the TCOl In writing, into four successive 3-bit words to be written on tape. disassembles the 1 2-bit computer word During reading the TCOl assembles the four successive 3-bit words into one 12-bit word for transfer to the computer. puter and the control always occur in parallel for a 12-bit word. data-break (high-speed channel) facility of the computer. detected, the TCOl transfer, it Data transfers use the 3-cycle start and end of each block are generates a DECtape control flag signal (DTCF) which causes a program in- terrupt in the computer. block number. As the Transfers between the com- The program interrupt is used by the computer program to determine the When it determines that the forthcoming block is the one selected for a data selects the read or write control function. 1-1 Each time a word is assembled or DECtape is ready to receive a word from the computer, the control produces a data flag signal (DF) to request a data break. Therefore, when each 12-bit computer word is assembled, the data break initiates o transfer. 1 REFERENCED DOCUMENTS .2 DEC documents listed in Table 1-1 contain material which supplements the information in These documents may be obtained from the nearest DEC field office or from the main office. this manual. The Digital Equipment Corporation 146 Main Street Maynard, Massachusetts Table 1-1 DEC Documents Doc . No Description Title Specifications and descriptions of the FLIP CHIP modules and a simplified explanation of selection and use of these modules in various applications. Handbook CI 05 Digital Logic ClOO System Modules Specifications and descriptions of basic system modules and power supplies. This manual provides a simplified explanation of selection and use of these modules in system applications. PDP-8 User Handbook F-85 Programming and operating information for the computer, including brief instructions on the TCOl DECtape Control. PDP-8 Maintenance Manual F-87 Complete information on tho internal operations of PDP-8 logic, memory basic in/out, and processor options. Digital 8-27-U Programs for PDP~8. PDP-8 Programming Manual Complete descriptions of DECtape subroutines designed for assembly with an object program, the DECtape library system, and the DECtape utility routines. H-TU55 Type TU55 DECtape Transport Maintenance Manual Transport drive logic and internal operations, plus C-800 Small Computer Handbook Handbook of basic functions of PDP-8/I computer. DEC-8/I-HMAA PDP-8/I Maintenance Manual of PDP-8/I logic, memory, basic in/out, and preventive and corrective maintenance instructions. Complete information on the internal operation processor options. In addition to the documents listed in Table 1-1, a complete set of library programs are avai lable o 1.3 PHYSICAL DESCRIPTION The Type TCOl DECtape control logic is mounted in three FLIP CHIP mounting panels which can be installed together with up to three TU55 DECtape transports in a standard DEC cabinet. For de- tailed information on the mounting panels and cabinets, refer to the hardware section of the Digital Logic Handbook (CI 05). 1-2 The standard DEC computer cabinet is constructed with a welded steel frame and sheet steel Double doors on the front and rear are held closed by magnetic latches. covering. Power supplies and power controls are mounted inside the rear double doors on a full-width plenum door latched by a springloaded pin at the top. Module mounting panels are mounted behind the double door in front with the wiring side facing outward. Fans at the bottom of the bay draw cooling air through dust filters, pass it over the electronic components, and exhaust it through the wiring and other openings in the front and top of the cabinet. Four casters provide mobile support for the system. blank panels in the space not occupied by components. The rear plenum door contains The TCOI control and DECtape units receive power from the Type 779 Power Supply and a Type 834 Power Control. These units are mounted near the bottom of the plenum door. The cabinet has an access door which extends 8-3/4 in. to the front of the cabinet and a plenum door which extends 13-3/4 in. to the rear. At least a 3-ft clearance should be allowed at both front and rear for access and maintenance. Cabinets may be bolted together at the sides to form contig- uous units. Equipment Characteristics 1.3.1 A summary of the characteristics of the TCOI control and associated equipment is listed in Table 1-2. Table 1-2 Summary of Equipment Characteristics for the TCOI DECtape Control Characteristics Equipment TCOI Control 15-3/4 in. high, 19 in. wide for equipment which operates up to eight Type T055 transports TU55 Transport 10-1/2 in. high, 19-1/2 in. wide, 9-3/4 in. deep. Chassis can be extended 16-3/4 in. beyond the mounting surface for maintenance Cabinet 69-1/8 in. high, 22-1/4 in. wide, 27-1/6 in. deep. Will hold a maximum of one TCOI control and three TU55 transports Weight TCOI Control 30 lb TU55 Transport 65 lb (rack mounted) Cabinet 555 lb (with maximum equipment mounted) Power Requirements TCOI Control 1 15V, 60 c/s, 4A A Type 834 Power Control and a Type 729 Power Supply are included with the Type TCOI Control (N9M transformer used for 50 c/s) TU55 Transport 1 15V ±10%, 60 c/^, 2A maximum, Cabinet 1 15V, 60 c/s source capable of delivering 20 A Tape Characteristics and Density .0 Mylar tape per 3.5 in. reel a. 260 ft of 0.75 n., b. 350 ±55 lines per inch c. 849,036 usable lines per tape d. 60 lines of control information 1 1-3 1 .5A idle Table 1-2 (Cont) Summary of Equipment Characteristics for the TCOl DECtope Control Equipment Characteristics e. 4096 is the maximum number of addressable blocks per reel f. Number of words in a block must be divisible by 3 g. NoB 212112 „ Ng- decimal number of blocks N^+15 Ny^= number of words per block h. Capacity for 190,000 12-bit words in blocks of 129 words Word Transfer Rate a. One tape line is read or written every 33-1/3 |js and one 12~bit word is read and assembled or disassembled and written in 133-1/3 (js. b. In reverse direction, the transfer rate varies by c. Transfers require 1 20% as the effective reel diameter changes. .2% of PDP-8 cycles after the initial 200-ms start time. Addressing a. Mark and timing tracks allow searching for a particular block. a. Start time b. Start and stop distances are approximately 8 in. Time is <375 ms, stop time is <375 ms, turn-around time is <375 ms. Input Signals to Transport from Control Commands FORWARD Normally complementary levels REVERSE GO STOP ALL HALT Normally complementary levels (stops transport when computer halts) Unit Select Select unit 1 through select 8 Information Analog write signals to the recording head Output Signal from Transport to Control Control WRITE ENABLE Information (ground level assertion) Analog read signals from the recording head Environmental Conditions Thermal Dissipation 2150 Btu/hr Operating Temperature 50°-95°F ambient Humidity 10% -90% relative humidity 1-4 NOTE The magnetic fape manufacturer recommends 40% - 60% relative humidity and 60° - 80°F as an acceptable operating environment for DECtape. 1.3.2 Electrical Requirements A cable rated at 1 15V, 60 c/s, 30A furnishes power for the TCOl DECtape Control. cable is terminated by a Hubbell Twist Lock plug rated at 30A, 125 Signals between the TCOl for the This Vac. DECtape Control and the computer are the standard voltage levels DEC FLIP CHIP modules, as stated in the Digital Logic Handbook (C105). Command signals be- tween the TCOl and the tape transport are also standard FLIP CHIP levels except for the SINGLE UNIT signal which Is a dc level between 0 and -9V. During writing, the information carries 200 ma in either direction with a 20V peak-to-peak waveform, symmetrical with respect to ground. When reading, the peak-to-peak head-voltage waveform is between 8 and 12 mV when the tape is up to speed. nal logic for the TCOl consists of DEC FLIP CHIP modules. All Internal signals are standard FLIP CHIP levels and pulses, except those for the read/write amplifiers and the 1-5 The inter- SINGLE UNIT signals. CHAPTER 2 OPERATION AND PROGRAMMING This chapter contains the information required for the operation and programming of the TCOl Included in this chapter is a description of the format of information on the DECtape Control unit. The DECtape magnetic tape, and the modes of operation used in the programming of TCOl operations. general operating information for the TU55 DECtape transport is contained in the TU55 maintenance manual listed in Table 1-1 . DECTAPE FORMAT 2.1 The format of the DECtape (Figure 2-1) used in the DECtape transports provides ten tracks, of which three pairs of tracks are available for data and tv/o pairs for timing and mark information. lO-track recording head reads and writes the five duplexed channels of the DECtape. A Duplication of each track by nonadjacent read/write heads, wired in series, eliminates most dropouts due to noise and dust, The location of the redundant tracks eliminates most cross talk be- and minimizes skew problems. tween tracks. the location of the timing tracks along the edges of the tape permits strobing In addition, on the analog sum of the timing-track signals and reading of the data tracks, when they are in the most The location of the data tracks in the middle of the tape also minimizes the effects favorable position. of skew. TIMING TRACK MARK TRACK INFORMATION TRACK INFORMATION TRACK t ' 2 INFORMATION TRACK 3 . Same OS IT I INFORMATION TRACK 2A Same as IT 2) INFORMATION TRACK 3A Same Q3 ( 0 I IT 3) MARK TRACK Snma as MT J .1- .'Q.^ i I 0 ' I 9 (' o' 0 1 -0 t.l -.'i'_ I 0 0 i' I 0 I "S 0 1 :0.::p:- ' 'r p - I 0" I ; 1;- ^'.;.::i'' .:o .. I 0 . I o /.^o;-.:; i,. . tOOO I o": I Q- ' i I -I - I - I I ( ( .1 01 lOIQi 1-0 ro INFORMATION TRACK lA [ 0 10', 00 (, 0 I 0- i 1 0. " 6. ^ 0 .' 0 0 1,1 I V i:;:.''.d:; I I I 1^ 000 I I I I I I 0 ( 0 ; " 0' ' I lOOOl I 0 I 0 . i r • 0 r O", ( 00 0 0 ~i t I •" I 1 0 ".J i I 0 I 0 I I b .o':-so.-.'..ir"r.. .-i. ';c*. - ,i I ; • i I I 0 I -.1 T' i o . 0 o I 0 . - ' i 0 1-1. 0 .'i;,- o' REDUNDANT TRACKS i": I TIMING TRACK lA Same os TT ( I Figure 2-1 DECtape Track Allocation Data is recorded by the Manchester method in which a prerecorded timing track synchronizes read/write operations. When writing on the tope, the write amplifiers supply the maximum current in either one direction or the other (non-return to zero, NRZ). To write a pulse, the polarity of the write current is reversed. The timing track is prerecorded with alternate positive and negative transitions at fixed time intervals. The negative transition is used during writing to load the write buffer and during 2-1 The positive transition is used during both reading and writing. reading to shift data. this tronsistion is negative transition. If ONE a is is switched to negative resulting During reading, the positive transition of the timing track If a a signal to strobe the data and mark track read-amplifier outputs into the read buffer. transition is ZERO is being written, the current starts out negative and generates a positive transition when switched to positive. is If a a signal to switch the polarity of the write current in all write heads. being written, the current, which starts out positive for writing ZEROs, in a During writing, sensed at strobe time, a ONE is positive placed in the buffer; otherwise a ZERO is strobed in. Because the strobe is a relatively narrow pulse, the system is not affected by noise outside the At strobe time, strobe time. representing ONEs. data signals are negative pulses representing ZEROs or positive pulses all These pulses are all at their peaks. To hav^e any effect, a noise pulse must be Data can be written over previously written data large enough to reverse the polarity of a data pulse. because the timing is controlled by the timing track that is written on the tape. Information is stored on the tape in block form (Figure 2-2). mined by information on the mark-track. A complete reel of tape (849,036 lines) can be divided into any A uniform block length can be established over the entire length of a number of blocks up to 4096. reel of tape by a Block length is flexible and deter- program which writes mark and timing information at specific locations. ability to write variable-length blocks is useful for certain formats, for example, However, the where smoll blocks containing index or tag information need to be alternated with the large blocks of data. ONE COMPLETE REEL ' ZONE SLOCK BLOCK SLOCK BLOCK BLOCK SLOCK BLOCK BLOCK *iP - BLOCK 260 FT 4095 BLOCKS - BLOCK BLOCK BLOCK SLOCK SLOCK SLOCK BUfiCK ^ BLftEK END SOaCK: '^j;^ - ONE BLOCK, 86 18-BIT WORD LOCATIONS - TIMING TRACK MARK TRACK '.r™ATION , TRACKS ,3 iei i i IU-lJJUJ'?Ullil Ld i i S S DATA _ WORDS i Hi SSI LiJ i i i UI-UI liJ 5 I § 8|I I i I i I i UJUj2ulUlWliilUUJUJ 88 S ig5iSggg§S llJ CONTROL WORDS - Figure 2-2 129,0 i i I i g s i UIUIUIUUUIUIUJEUJUJ g5§§g5§$gS DATA WORD LOCATIONS - IjJ Ll) Ul lU SjJ lij LLIllj5w^^l»J- S i S S 8 S S - ili 5 CONTROL WORDS - DECtape Control and Data Word Assignments Each block contains data and control words as shown on Figure 2-3 which are assembled by the TCOl DECtape Control. Control words separate the data portions of adjacent blocks and record ad- dress and checking information. are used. Although control words usually occupy six lines, only the last four lines Data words contain stored information and occupy four lines on tape (12 bits). 2-2 To maintain compatibility with the mark-track format, data words are recorded in 12-line segments (which is the lowest common multiple of 6-line marks and 4-line data words) corresponding to three 12-bit data words. Therefore the number of words per block must be evenly divisable by 3. Figure 2-3 DECtape Recording Format Block numbers normally occur in sequence from one block n+1 . 1 to n. There is one block numbered 0 and Programs are entered with a statement of the first block number to be used and the total number of blocks to be read or written. The maximum number of blocks is determined by the following equation 212112 Ng=-jq — IJTJ^ ^ ~2 Ng - decimal number of blocks Ny^ = decimal number of words per block (N^ must be divisible by 3.) 2.1.1 Mark-Track Format The mark track contains six-bit serially stored codes which initiate controls to raise flags in control the program, request data breaks, detect block mark numbering and block ends, and protect portions of the tape (Figure 2-4). The DECtape control unit automatically identifies these codes. The mark track also provides for automatic bidirectional compatibility, variable block formatting, and endof-tape sensing. In all tape processing functions except the recording of the timing and mark tracks, a single mark track bit is read from each line of tape regardless of whether the information is being read or written into the data tracks. Each tape line In both the Information and mark tracks Is positioned at the center of the timing track as shown on Figure 2-3. The mark track code is contained within six lines of the mark track. A change of polarization on tape read in one direction produces a pulse opposite in polarity to that produced by the same change read in the opposite direction. reverse has the order of bits reversed and the bits complemented. 2-3 Consequently, a mark code read in Forward diraction of tops motion ONE BLOCK a6,o 18 -BIT WORD LOCATIONS 129to 12-BIT I EXPAND BLOCK REVERSE CODE MARK GUARD LOCK I HEVERSE REVERSE CHECK REVERSE PRESUM FINAL FINAL DATA DATA WORD LOCATIONS DATA t t t f Di Og Da D4 DATA DATA FlNA FINAL t f t t t t REVERSE CHECK REVERSE 6UJCK EXPANDj SUM LOCK GUARD MARK CODE D|£5 SIGNIFIES START OF BLOCK AND ALLOWS COMPUTER PROGRAM TO IDENTIFY BLOCKS BLOCK NUMBER AS REVERSE DIRECTION SAME FUNCTION AS REVERSE LOCK NOT USED IN PDP-B CONFIGURATIONS BUT PROVIDED TD ALLOW COMPATIBILITY WITH OTHER COMPUTERS ADDITIONAL DATA WORDS SUCCESSIVE DATA WORDS Coda funcTioni IKttd apply aniy Figure 2-4 In th» direction indicated. DECtape Mark Track Format For example, the mark read forward as lOOIOl is read as 0101 10 in reverse. This correspond- ence is termed the complement obverse or the complement image. Every 6-bit code has one and only one complement obverse which is constructed by complementing all bits and reversing their order. Therefore, the complement obverse of the complement obverse is the original code itself. tion, the complement obverse of any pair of digits is In octal nota- constructed by reversing the order of digits, then performing the following transformation on each: 0—*? 4—^6 I 5 —^3 2 -2 6 —^5 —^4 3 7 —^1 —-O The transformations indicate that there are eight octal codes which are their own complement obverses: 07, 13, 25, 31, 46, 52, 64, and 70. All other possible combinations of two octal digits (there are 56) are different from their complement obverses. As shown in Table 2-1, the complement obverse of any mark is designated by the minus sign (e.g., mark G = 51 has the complement obverse -G = 32). Since the DECtape system allows reading and writing in both directions of tape motion, the mark-track must be coded to present the same information when entering a block from either direction. The marks at the end of a block are the complement obverses of the marks at the beginning, order. in For example, if the control reads the marks E, forward motion, then it will read G, block. In track; thus the first information, in reverse M, -G as the first three marks beginning a block -M, - E, in that order, as the last three marks of the same reverse motion, however, the control sees the complement obverse of the contents of the mark identical to E, when reading the block in reverse, is -(-E), -(-M), -(G), which is M, -G. All marks used in the standard DECtape format are listed in Table 2-1 exist even though a given code may have different designations. for the operation of the Type TCOl DECtape Control. 2-4 . Only ten valid codes Some of these marks are not required Table 2-1 Mark Track Coding Mark Octal Code Function C (Check) 73 Signifies the end of a mark frame whose first two lines were the forward parity check group. -C (Reverse Check) 10 SicinifieS that the 6— bit rPVf^r^p InnnlfiirJi nnl rw-irlf\/ check group is contained in the control unit read/ write buffer and that the beginning of the data portion of a block is in the forward direction. D, -D (Data) E, -E (Extension) 25 The first and last mark of every block (no-op mark). End (Forward End) 22 Indicates the end zone of tape in forward direction. both forward and reverse tape motion, the data mark occupies all mark frames in the data portion of the block except for the final and prefinal marks. The number of data marks is limited only by the length of tape. In The forward end mark is positioned approximately f\ Cl C ^ ill. 10 tt from actual tape end. 1 -END (Reverse End) 55 1 Indicates the end zone of tape in reverse direction. The reverse end mark is positioned approximately 10 ft from end of tape. "TO r (r\na\) 73 Signifies that the last word read from the data portion Or OCk Id^ in fa l^i ffctv rtr\i4 VI tnfi iiib D i\j\^r\ III f iiic re^nr4 cKjKjy/ wr vvMic uuirsi QriQ <-J^4>n QurQ 1 I I i i buffer. Signals that the next frame begins with the 6-bit forward longitudinal parity check group. -F (Reverse Final) 10 Signifies that the last word read from the block, in the reverse direction, is in the read/write buffer and data buffer. v7 ^Vjuard; 51 Performs same function as -L (reverse lock). -iy (Reverse Guard) 32 Not used. L (Lock) 10 Indicates the first of four octal 10 marks. -L (Reverse Lock) 73 Protects Subseouent records in thp ^avt^nt nf mnrU — frn/^L' M (Forward Block) 26 Signifies the start of a block and indicates that the block number is contained in the TCOI control. -M (Reverse Block) 45 Not used. P (Prefinal) 73 In -P (Reverse Prefinal) 10 In the errors the forward tape direction, the prefinal mark is the next to last mark in the data portion of a block. It is the first of four marks using octal code 73. reverse tape direction, signifies the next to last mark in the data portion of a block. The standard mark-track uses the serial code of 6-bit characters to divide the tape into words. Codes are written on the mark track opposite word locations to identify the type of information stored at that location on tape. Block addresses are written for both forward and reverse directions and identified by two types of mark codes. A checksum is written at each end of the block. 2-5 The hardware computed checksum is the six bit logical equivalent (i.e., the complement of the "exclusive OR") of each six bits written on tape plus the reverse checksum previously recorded. By including the reverse checksum in the computation, the block may be read in either direction at a later time without an error. uses the final marks to establish synchronism and raise block-end flags. trol The con- Data marks locate data words DECTAPE INSTRUCTIONS 2.2 The six basic lOT instructions used in the programming of the PDP-8 for TCOl DECtape operations are listed in Table 2-2, with the octal tion. code assignments and a description of the instruction opera- These instructions apply to two functional groups within the TCOl, designated as status A and status B, and are used to clear, read, and load the status registers A and B. These two registers are used to govern tape operations and provide status information to the computer program. Table 2-2 TCOl DECtape Instruction List Mnemonic Octal Code Operation DTRA (read status 6761 The contents of status register A are loaded into the accumulator by an OR transfer. Refer to Table 2-3 for the AC bit assignments. 6762 Status register A is cleared. flags are undisturbed. 6764 The exclusive OR of the contents of bits 0 through 9 of the accumulator is loaded into status register A, and of the accumulator are sampled to conbits 10 and register A) DTCA (clear status register A) DTXA (load status register A) 1 The DECtape and error 1 the clearing of the error and DECtape flags, respectively. Loading status register A from AC 0 tnrough 9 establishes the transport unit select, motion control, function, and enables or disables the DECtape control flag to request a program interrupt as described in DTRA. Refer to Table 2-3 for ACl 0 and AC 11 bit assignments. trol DTSF (skip on flags) 6771 The content of both the error and DECtape flags is sampled. If any flag is set, the content of the program counter is incremented by one to skip the next sequential instruction. DTRB (read status register B) 6772 The content of status register B is loaded into the accumulator by an inclusive OR transfer. The AC bit assignments are as follows. ACO = Error flag (EF) ACl = Mark-track error (MKTRK) AC2 = End-of-tape error (END) ACS = Select error (SE) AC4 = Parity error (PI) ACS - Timing error (TIM) AC6- 8 = Memory field (MF) AC9-10 = Not used ACll = DECtape flag (DTF) 2-6 Table 2-2 (Cont) TCOl Mnemonic Octal Code DTLB (load status 6774 DECtape Instruction List Operation The memory field portion of the accumulator (AC6-8) is loaded into the memory field register. The accumulator is cleared and the error flags are undisturbed. register B) 2.2.1 Status Register A Functions Figure 2-5 is the format for the status register A. This register contains three unit select bits, two motion bits, one mode bit, three function bits and three bits which control the flags. assignments for the status register A are provided in Table 2-3. 0 1 2 3 4 5 6 8 7 9 10 1 1 TRANSPORT UNIT SELECT DECTAPE FLAG - ERROR FLAG ENABLE INTERRUPT FLAG Figure 2-5 Status Register A, Format Table 2-3 Status A-bit Assignments Function Transport Unit Select AC Bit 0-2 Conditions Octal Code Unit 000 8 001 1 010 2 on no 3 4 5 6 in 7 100 101 Motion 0 = Forward (FWD) = Reverse (REV) 3 1 0 = Stop motion (STOP) = Start motion (GO) 4 1 Mode 0 = Normal mode (NM) = Continuous mode (CM) 5 1 2-7 The bit Table 2-3 (Cont) Status A-bit Assignments AC Bit Function Conditions Operation Code 6,7,8 Function Move 000 001 Search 010 Read data Read all 011 101 Write data Write all 1 Unused (causes 100 1 1 select error) 9 Enable the interrupt = Enable DECtape control 1 (DTCF) to the program interrupt flag Error flag 10 DECtape flag 11 0 = Clear all error flags = Error flags undisturbed 1 0 = Clear DECtape flag = DECtape flag undisturbed 1 2.2.2 Status Register B Functions Figure 2-6 shows the format of the information in the status register B. 6 bits of error status information, 3 memory field bits and the DECtape flag bit. This register contains Table 2-4 lists the function of the bit assignments. 0 ERROR FLAG 1 2 3 4 5 6 7 8 9 J 10 1 L DECTAPE FLAG UNUSED MAINTRACK ERROR END OF MEMORY FIELD TAPE ERROR TIMING ERROR SELECT ERROR PARITY ERROR Figure 2-6 Status Register B, Format 2-8 Table 2-4 Status B, Bit Assignment AC Bit Function Error Flag (EF) Conditions 0 = Detection of any nonoperotive condition by the control 1 OS listed in the error functions described in through 5 of this tobie. AC bits I These conditions stop transport motion except for parity errors. Mark-Track Error End of Tape Error 1 = Information read from mark track was erroneously decoded. I = the end zone on either end of tape is over read head. 1 (MKTRK) 2 (END) Select Error (SE) 3 This error occurs 5 ps after loading status register A to indicate one or more of the following conditions. The unit select code specified does not correspond to any transport select number or is set to more than one (a) transport. (b) A write function was specified when the WRITE ENABLE/ WRITELOCKswitchisinthe WRITE LOCK position. V^/ jpccirieson unusea runcrion code (I 8 of the status register A. (d) Specified a function other than Read All with the maintenance control panel RDMK/WRTM/NORMAL switch in the I I jbits 6 through RDMK position. Specified a function other than Write Timingand Mark Track with the RDMK/WRTM/NORMAL switch in the (e) WRTM position. Specified the Write Timing and Mark-Track function with the RDMK/WRTM/NORMAL switch in a position other than WRTM. = Error occurs during a Read Data function if the longitudinal parity over entire data block including reverse checksum and checksum, is not equal to . If a parity error is to be set at the end of a block, it will be set at the same time the DTF is set. During if a word count overflow does not occur at the end of a block, the parity error is set at the end of the block in which the word count overflow occurs. The parity error cannot be set after (f) Parity Error (PAR) 4 1 1 CM the Timing Error (TIM) 5 I DTF is set. = Program fault caused by one of the following conditions: (a) A data break request is not answered within 66 ps ±30% of the data break request. (b) The DTF was not cleared by the program before the control attempted to set it. (c) The read data or write data function was specified after the current data block has been entered to prevent incomplete data block transfers. 2-9 Table 2-4 (Conf) Status B, Bit Assignment Function AC Bit Conditions Memory Field (MF) 6, 7, 8 Indicates the memory field from or to which data transfers take place. 9-10 Unused 11 1 DECtope Flag (DTF) = DECtape operation complete CONTROL MODES AND FUNCTIONS 2.3 The TC01 control unit operates in either the normal mode (MM) or continuous mode (CM) as determined by the mode bit (5) in the status register A. In the normal mode, the data transfer and flag indications are controlled by the format of the information on tape. fer and flag indications are controlled by a word count In the continuous mode, data trans- (WC) read from core memory during the first cycle of each three cycle data break, and by the tape format. The normal mode differs from the continuous mode primarily in the time at which the DECtape flag (DTF) is The DECtape flags which occur in the normal mode are inhibited in the continuous set. mode until a word count overflow has occurred. In both modes, data break requests occur only when a word count overflow has not occurred during the specified current function. 2.4 CONTROL FUNCTIONS The DECtape system performs one of the seven following functions during either the normal or continuous mode, as determined by the octal digit loaded into the status register A during a mand. 2.4.1 DTXA com- A summary of the procedures and possible errors which may occur are listed in Table 2-5. Move Initiates motion, in either direction, of the specified tape transport. The mark-track is read but mark-track errors are inhibited except for end of tape errors. The move function is used to rewind tape 2.4.2 Search Provides random access to the data blocks on tope. As the tape is moving in either direction, the sensing of a block mark causes a data transfer of the block number. causing a program interrupt at each block number. number which causes the word count overflow. In In normal mode the DTF is set, continuous mode the DTF is set only at the block After the first block number is found, the continuous mode can be used to avoid all intermediate interrupts between the current and desired block number. The block number is read into the memory location specified by the current address register (Memory location 7755). The current address register is not incremented. 2-10 2.4.3 Read Data This function reads data in either direction and transfers bloctcs of data into core memory with the normal mode, the transfer controlled by tape format. In a program interrupt. mode, In the continuous DTF is set at the end of each block causing transfer stops when the word count overflows; the remainder of the block is read for parity checking and the 2.4.4 however, DTF is then set. Read All This function allows the reading of all bits on tape after the tope motion reaches up to speed. The three information tracks are continuously read and transferred to the computer. used to check only for mark-track and end of tape errors. is set at each data transfer. The mark-track is During the normal mode, the data tape flag During continuous mode, the data tape flag is set only when a word count overflow occurs. 2.4.5 Write Data This function is used to write blocks of data in either direction with the transfer controlled by When a word count overflow occurs during the writing of a block of data, the standard tape format. zeros are written in all the remaining lines of tape until the end of a block and then the checksum over The DTF is set in a similar manner as that for the Read Data function. the entire block is written. 2.4.6 Write All This function allows the writing of all bits on tape even though the information standard tape format. is The mark-track will only check for mark-track and end of tape errors. not in the The DTF is set for the same conditions described in Paragraph 2.4.4. This mode is used to write block numbers on tape. 2.4.7 Write Timing and Mark Tracks This function is used to write timing and mark-tracks to establish or change the lengths of blocks. 2.4.8 Enable to the Interrupt The TCOl control has an Enable-to-lnterrupt (ENI) function which permits the program to re- move the TCOl from the program interrupt of the PDP-8 processor. 2-11 Table 2-5 Control Function Procedures and Errors Procedures Octal No. 0 ISlormn lU Control Function MOVE 1 1 1 11 AAnrJp (NJM) f V lUU C \IN/V1^ Possible onhimiriii^ luwuo AArirIp iviwwic (tKAl C v.iWi 1 1 1 1 Not involved Not involved Errors SE, C IN L/ 1 SEARCH Block number read into core location specified by contents of CA Same as NM CA is not incremented Same as NM WC is incremented Same as NM r^TF II lO ^pt n hirtflf Ul pnf CUXtfil 9CI ni UIV^IS nXF I? SE END TIM MK TRK rtnlv nf f np block number causing number WCO 2 READ DATA T £ S L Transfer data as long as 1 Same as NMA C k. 1 ii SE WCO has not occurred. WCO occurs in mid- END TIM PAR If dle of block, the block IS read tor parity K^IICLi^ilIU U\J 1 1 i\J MK TRK illUIC data transfers are made. Roth W(~ nnri CA orp incremented. DTF is set at each block DTF is set only at end of block in which occurs. end. WCO O RFAD Al 1 Transfer data until WCO Same as NM occurs Both WC and CA are Same as NM TIM MK TRK incremented. DTF is set at each word DTF is set at WCO transfer. 4 WRITE DATA tit T 1 Transfer data as long as has not occurred. Same as NM SE WCO WCO occurs in END middle of block, zeros are written to end of L L block and checksum is MK TRK TIM It 1 1 1 I written Both WC and CA are Same as NM incremented. DTF is set at end of If no new each block. function is specified. the tape continues to move but the write heads are disabled. (TIM will occur at the end of next block if DTF is not cleared.) 2-12 DTF is set at end of WCO block in which occurred. When occurs and if no new function is specified, the tape continues to move but the writers are disabled. WCO Table 2-5 (Conf) Control Function Procedures and Errors Procec ures Octal No. 5 Normal Mode (NM) Control Function WRI TP Al iruiiarcr 1 bame as NM uuru uo lon^ us WCO has not occurred. Word which causes WCO last one written. is Possible Continuous Mode (CM) Errors cc ot END TIM MK TRK Tape continues to move but the writers are disabled. Same as NM Both WC and CA are ' 1 1 incremented DTF is set at WCO DTF is set at each word transfer 6 WRITE TIMING AND MARK Transfer data as long as has not occurred. MTier yy^vjf rne writers are not disabled and zeros are written. Same as NM WC and CA are Same as NM WCO Both SE TM incremented. DTF is set at WCO DTF is set at each word transfer. 2.5 PROGRAMMED OPERATION Prior to using the Type TCOl DECtape Control for data storage, the prerecording of a reel of DECtape is accomplished in two passes. tape. In the first pass, the timing and mark-tracks are placed on the During the second pass and the forward and reverse block, mark numbers are written. functions can be performed by the PDP-8 program. These Prerecording utilizes the WRTM control function and the manual switch on the maintenance control panel of the Type TCOl DECtape Control to write on the timing and mark tracks, to activate a clock which produces the timing track recording pattern, and to enable flags for program control. Unless the WRTM control function and switch are used simultane- ously, the writing on the mark or timing channels is inhibited. A red indicator lights on the control maintenance panel when the manual switch is in the RDMK or WRTM position. written only when the switch is in the WRTM position. The mark-track can be Only one prerecording operation is required for each reel of DECtape. The six basic lOT instructions are generated as required by the PDP-8 program to clear, read and load the status A and clear and read the status B elements the status of the DECtape control . . The lOT skip instruction is available to test Since all data transfers between the Type TCOl DECtape Control and the PDP-8 memory are controlled by the data break facil ity, the PDP-8 program sets the word count (WC)and current address (CA) registers (location 7754 and 7755 respectively) using the memory reference instruction in the processor initializing a block transfer. checks for error conditions. Before and after a DECtape operation, the PDP-8 program A program interrupt is initiated if the TCOl is enabled to the interrupt 2-13 system and if the interrupt is on. block number selected for transfer; The DECtape system is started with the search function to locate the then when the correct block is found, the transfer is accomplished by setting the WC, CA, and the STATUS A and STATUS B elements. When searching, the DECtape control reads only block numbers. These are used by the op- NM, the DTF is raised at each block number. The CA is not incremented during searching, In CM, the DTF is raised only after the WC reaches zero. erating program to locate the correct block number. In and the block number is placed in core memory at the location specified by the contents of the CA. Data is transferred to or from PDP-8 memory from locations specified by the CA which is incremented before each transfer. When the start of the data position of the block is detected, DP is raised to initiate a data break request to the data break facility each time the DECtape system is ready to transfer a 12-bit word. Therefore, the main computer program continues running but 3 memory cycles are stolen approximately every 133-1/3 ps for the transfer of a word. memory locations specified by the CA. ing routine. Transfers occur between the The initial transfer address-1 is DECtape and successive core stored in the CA by an initializ- The number of words transferred is determined by the tape format, format and WC, if in CM. gram interrupt occurs. if in NM, or by the tape At the conclusion of the data block transfer, the DTF is raised and a pro- The interrupt subroutine checks the DECtape error bits to determine the validity of the transfer and either initiates a search for the next information to be transferred or returns to the main program. During all normal writing transfers, a checksum (the 6-bit logical equivalent of the words in the data block) is computed automatically by the control and is automatically recorded as one of the control words immediately following the data portion of the block. The same checksum is used during reading to determine that the data playback and recognition takes place without error. Any one of the eight tape transports may be selected for use by the program. After using a particular transport, the program can stop the drive currently being used and select a new drive, or can select another transport while permitting the original selection to continue running. searching, since several transports may be used simultaneously. This allows rapid Caution must be exercised because, although the original transport continues to run, no tape-end detection or other sensing take place . All functions provide for automatic end sensing, but this feature stops tape in the selected tape drive only. The timing for the TCOI operations are summarized in Table 2-6. 2-14 Table 2-6 Summary of Timing Data for TCOI Operation Operation Time Time to Answer Data Break Request Up to 66 |JS (±30%) Data Break Transfer Rate 4.5 |js (3 cycles) per word Word Transfer Rate I - 12 bit word every 133 us Block Transfer Rate 1 - 129 word block every 18^2 ms Start Time <375 ms (±20%) Stop Time <375 ms (±20%) Turn Around Time <375 ms (±20%) Search block Read Data Function change for present Up to 400 |Js (±30%) Search block Write Data Function change for present Up to 400 |as (±30%) Read Search Function change for next block ^ Up to 1000 MS (±30%) Write Search Function change for next block* Up to 1000 MS (±30%) (±30%) (±30%) DTF Occurrence: Move: NM, CM None NM NM NM Every 18.2 ms (±30%) CM (WC) X18.2 ms (±30%) Search: Read Data: Write Data: Search: Read Data: Write Data: Read All: CM CM NM (^h\ock) XI 8 2 ms f±30%^ NM Write All: Write Timing and Mark Tracks: Every 133 |js (±30%) NM CM Read All: Write All: CM Write Timing and Mark Tracks: (WC) X133 fjs CM Simplified Search Procedure 2.5.1 The use of the following procedure simplifies the search operation. by the CA, d + 1 NM and find the first block mark, a. Search in b. Compute the difference (d) between this block mark and the desired block number. c. Load the 2s complement of this difference into the WC. d. Change to CM and continue search. e. The next DTF interrupt is the desired block. if a program check is desired. The block number is in the address specified This procedure results in only two interrupts compared to interrupts found in the method which interrupts at each block mark. 2-15 2.5.2 first Bootstrap Loading The CA specifies the address into which the data is loaded. The CA points to the WC, and the word that is transferred specifies the number of words to transfer. Then, the CA points to itself, and the second word that is transferred determines where the subsequent data requires the use of the 3-cycle break, or computation 2.5.3 is is which contains the WC and the CA. to be loaded. This technique No program interrupts, timing, needed for the location of data. Upper Bound Protection for Data Transfer The WC controls all data transfers and, after a word count overflow occurs no further data transfers take place. To protect the memory, when reading a block of unknown length, the WC is set to the upper bound. Similar action prevents writing beyond a predetermined point on the tape. 2.5.4 Write/Read in Opposite Direction Writing or reading in opposite directions can be accomplished with the TCOl, but two steps are required to return the data to the original memory format. One step is necessary because the CA only increments and does not invert the reverse order of the words. the word returned from the TCOl is The other step is necessary because in the following format compared with the original. 23456789 10 Original bit positions: 0 Returned bit positions: 9Tori6783 450T2 1 For example 11 The reorganization procedure that is required can be performed in real time, provided that sufficient time is available. This procedure should be avoided when other program interrupts are too frequent and where using the fastest possible data rate of 133 ps ±30% per word. 2.5.5 Turn Around Specifications During a search operation a turn around command can be issued, to change the tape motion without affecting the other command parameters. This requires two standard block lengths of tape to enable the transport to reach "up to speed" before searching for the block in the opposite direction. To search for blocks No. 0 next to the tape end zone, the tape must be moved into the end zone at least two block lengths before changing tape direction. To search for block No. moved into the end zone at least one block length before changing direction. tape to allow the transport to reach up to speed before searching for the block. tion the TOG-8 program provides two block lengths of enter-block zone-marks 1 , the tape is This provides sufficient To eliminate this opera- (NO-OP marks) at the end of tape so that the tape can reverse motion at the end zone and still locate block 0 or block 2-16 1 . TAPE MOTION (T) SEARCH REVERSE TO BLOCK NO. 21 (21RI note: F- FWD. (T) TURN AROUND AND SEARCH FORWARD TO BLOCK NO 24 I24F1 R " REV. Figure 2-7 Turn Around Sequence Diagram A length of tape equal to two standard block lengths (129.|q - 12-bit words) must pass the tape transport heads before a turn around 4 in. of tape. is The formula command is issued. for calculating, the nonstandard This is equivalent to approximately block delay that is required for turn around listed as follows. EXAMPLE Turn around delay calculation for 72^q words per block 129 (words/block) / , / — I rr 72 (words/block) y o x ui X2 3.6 block j delay -j i i (4^0 ^lock delay used for simplified search operations) 2.6 AVAILABLE SOFTWARE The software available for use with the PDP-8 is described in the following paragraphs. 2.6.1 Subroutines Subroutines may easily incorporate into a program for data storage, logging, data acquisition, data buffering (queuing), etc. The subroutines include a series that will read or write any number of DECtape blocks, read any number of 129-word blocks as 128 words (or one memory page) in which 200 octal locations equal 128 decimal locations; or search for any block that is used by read and write or to position the tape. These programs are assembled with the user's program and are called by a jump-to-subroutine (JMS) instruction. The program interrupt is used to detect the setting of the DECtape (DTF) flag thus allowing the main program to proceed while the DECtape operation is being completed. when the operation has been completed. A program flag is set The program, therefore, allows effective and concurrent opera- tion of several input/output devices as well as the DECtape. 2-17 Library Calling System 2.6.2 A Library Calling System is used for storing named program on DECtape and provides a means of calling them with a minimal size loader. The Library Calling System leaves the state of the computer unchanged when it exits and is capable of calling programs by name from the keyboard and allowing for expansion of the ^jrogram file stored on the tape. It also conforms to existing system conventions by allowing all of memory except for the last memory page (7600g ^^^^Q> ^° available. This convention permits the binary loader (paper tape) and/or future versions of this loader to reside in memory at all times. System is loaded by a 17jq instruction bootstrap routine that starts at 7600g. larger program into the last memory page. INDEX program and the directory into Because the information in this area has been preserved, the operations have been completed. This loading calls a The function of the larger program is to preserve on the tape the contents of memory from 6000g - 7577j, and then load the those same locations. The PDP-8 Library it can be restored when The skeleton library tape contains the following programs. INDEX Typing this program causes the names of all programs currently on file to be typed out. UPDATE Allows the user to add a new program to the files. UPDATE queries the operator about the program's name, its starting address, and its location in core memory. GETSYS Generates a skeleton library tape on a specified DECtape unit. DELETE Causes a named file to be deleted from the tape. Starting with the skeleton library tape, the user can build a complete file of active programs and continuously update them. brary tape. The library tape can be used by the programmer to call the FORTRAN compiler. in turn, piler, For example, a program that is to be used repeatedly is written on li- can be used to compile a program to obtain the object program. Then, the FORTRAN Operating System can be called from the library tape and used to load the object program. the library UPDATE program is called and the operator defines a The com- At this time, new program file (consisting of the FORTRAN Operating System and the object program) and adds it to the library tape. entire operating program and the object program are available on the As a result, the DECtape library tape. Preformatting Tape Programs 2.6.3 There are available programs for preformatting tapes which are controlled from the Teletype to write the timing and mark tracks, to write block formats, to exercise the tape and check for errors, and to provide ease of maintenance. 2.6.4 Maintenance Programs A package of maintenance programs are available which exercise the DECtape system. One A system set of programs exercises the various functions separately and provides scope loop operation. test, using a program which does random transport selection, searching, and data checking while running a central processor test, is provided. 2-18 SYMBOLS AND ABBREVIATIONS 2.7 Table 2-7 lists the symbols and abbreviations used throughout this manual and on the logic drawings contained in Chapter 6. Table 2-7 Symbols and Abbreviations AC Accumu lator ADDRESS ACC Address accepted BAC Buffered accumulator B BREAK Buffered break signal supplied by PDP-8 (PDP-8/I) BLK Block of DECtape data BMB Buffered memory buffer BMR Buffered motion register B RUN Flip-flop located in PDP-8 (PDP-8/I) which indicates whether processor is performing instructions. BTC + 1 Cq/ Block transfer control CA INH ^3' ^4 CA CK Signal which inhibits incrementing the CA Control clock flip-flops Current address register Check Clock counter CLEAR STATUS A 400-ns control pulse initiated by lOP 2 CM COMP RWB 0-2 Continuous mode C SYNCH Level indicating whether control clock is synchronized with CXA Clear status A oulse or exclusive OR status A oulse DATA Data flip-flop of state register DCD Diode capacitor gate DF Data flag DTP DECtape flag DTCF DECtape control flag EF Error flag EN END Enable ENI Enable-to-the-interrupt EOT End-of-tape error ES Error stop Complement RWB bits 0 through 2 DECtape marks End of tape 2-19 Table 2-7 (Cont) Symbols and Abbreviations FD Function decoder FR Function register FRq, FRy FR2, FR^ FR flip-flops IM Input mixer IN Inclusive INH Inhibit I/O Input/output ION Interrupt on lOP Input/output pulse lOR Inclusive OR lOT Input/output transfer lOT SKIP ON DTCF (1) 400-ns status B SKIP command LOAD STATUS B 400-ns control pulse initiated by lOP 4 LPB Longitudinal parity buffer MA Memory address register MB Memory buffer register MK BLK END MK BLK START MK DATA MK END Flag marking end of a data block MCP MF Flag marking start of a data block Flag marking the data portion of a block entertarl End the \A flao Indicotina lit lu that III \A vi v III W end ^^yi w has W lU zone v w heen V W 111 W V U fan 1 1 1 1 • 1 1 1 1 1 1 1 Maintenance control panel Memory field register MK(— MK TK Mark track floo WAN error W %y flio— \^mj fj MR Motion register PA Pulse amplifier PAR Parity error PC Program counter PI Program interrupt PWR CLR Power clear nulses RATE DY Rate delay Serially stored codes on f T 1 ffN I 1 \rf 1 1 1 1 1 1 1 DECtape 1 D__J LA Pi Read markIIlevel outputj.ffrom MCP switch 1 J. • I RD + WD Read data or write data READ STATUS A 400-ns control pulse initiated by IOP2 READ STATUS B 400-ns control pulse initiated by lOP 2 REV CH Reverse check ROTATE DB/RWB Rotate contents of DB and RWB 2-20 I 1 1 Table 2-7 (Cont) Symbols and Abbreviations RWB Read-write buffer RWB -V- LPB Computes parity check in LPB KvvD orllr 1 Ltr 1 Shift contents of RWB to the left and read next line of tape Status A delay SE Select error enable SEL Select error flip-flop SHIFT ST Shift state pulse SP Speed of DECtape ST State or start STB Strobe ST BLK MK State in which control senses block numbers STCK State in which automatic error dptertion (vjkor, ronA'inr,\',c provided ST FINAL Final data word of block state ST IDLE State in which DECtape transport is stopped or not up to speed or between blocks o 1 Kt State in which reverse checksum is over head ovv l/Vl Switch timing and mark level output of MCP switch SYNr C L synchronize T Time Tl PDP-8 time state • 1 72 PDP-8 time state 2 T3 PDP-8 time state 3 TIM "Timing error T/M ENABLE Timing mark ENABLE TPO DECtape timing pulse which designates instant that center of left polarization of timing track passes the head inductors (beginning of a line on tape) TPl DECtape timing pulse which designates instant that center of right polarization of timina track oasses thp hpnrJ inrlnr-tm-c (center of a line on tape) TRK Track TT Timing track U + M Unit or motion UP TO SPEED Signal indicating DECtape transport is running at speed USR Unit select register W Window register WC Word count flip-flop 2-21 operating Table 2-7 (Cont) Symbols and Abbreviations Word count overflow pulse VV^W wn - FNN Write data enable W - INH Write inhibit WRFN VV N Write enable V V U/ I- 1 VV 1 1 1 1 l\L. 1 VVKI WRITE ENABLE/WRITE LOCK switch sensing from selected TU55 C \Jr\ 1 mm Write timing and mark Exclusive OR XOR XOR STATUS A A, 400-ns control pulse initiateW by lOP 4 XOR STATUS A delayed 400 ns Delaved CXA oulse 400-ns CLEAR STATUS A pulse for clearing USR JM L/ T n ^<^TAT1 yucv A Clears all bits of device designated ay njwi 1 1 1 » ^devi ce svmbol) "1 ^uc;v t.c 3 y M v_ 1 1 i / Sets all bits of device designated Complements all bits of device designated 1 or 0 of 4-digit word designates 1 or 0 output of respective control clock flip-flop CO, CI, C2, or C3 Each +1 — (device symbol) Increment the contents of device designated by V Inclusive OR V Exclusive OR A AND A A5 ONEs complement of the content of A Content of bit 5 of register A A5(]) Bit 5 of register A6-11 Contents of bits 6 through overbar e.g., (SWTM) Negation of signal level . FLIP-FLOP (0) ZERO output of designated flip-flop FLIP-FLOP (1) ONE output of designated flip-flop /\ A contains a 2-22 1 1 1 1 of register k- Also refers to complement of signal CHAPTER 3 PRINCIPLES OF OPERATION This section includes a brief description of the basic functional elements of the control, together with the general information on data and control information transfer. tains a detailed description of the It also con- TCOl control operation, with reference to the block schematic dia- grams contained in Chapter 6 of this manual. For detailed information on the PDP-8 and PDP-8/I processors, and TU55 DECtape Transport, refer to the documents listed in Table 1-1 3.1 TCOl DECtape . FUNCTIONAL DESCRIPTION The basic functional elements of the TCOl control, the PDP-8 (PDP-8/I) processors, andTU55 transport interface blocks are shown on Figure 3-1 . The numerals in the lower right-hand corner of the blocks indicate the bit capacity of the element. The numerical subscripts on the signal flow lines indi- cate the bit assignments of the signals. Blocks that represent the Status A and Status B functions are in- dicated by an A or B, respectively, in the top right-hand corner of the block. 3.1.1 Information Flow A description of the registers associated with the information flow are listed, as follows. a. Data Buffer (DB) - The data buffer is a 12-bit register used as a storage buffer to syn- chronize data transfers as a function of tape timing between the memory buffer register of the computer and the read/write register. b. Read/Write Buffer (R/WB) - The read/write buffer is a 6-bit register consisting of three, 2-bit shift registers. During read operations, one bit from each of the three data channels on tape is read into the read/write buffer and shifted right or c. left depending on the tape direction. Write Amplifiers - The five write amplifiers receive timing signals, mark-track, and data information from the read/write buffer and provide the necessary current to the tape heads to write the data on tape. d. Read Amplifiers - The five read amplifiers transfer timing signals, mark-track and data information from the tape heads to the window register and read/write buffer. 3.1.2 Command Flow Registers The registers and signals which control the transport operations and the data flow are de- scribed as follows. a. Longitudinal Parity Buffer (LPB)- The longitudinal parity buffer is a 6-bit register used to perform a parity check on the three information channels. The operation is performed by setting the 6-bits of information read from two consecutive lines on tape into the LPB and complementing each stage of the LPB if the corresponding bit of the R/WB contains a zero. 3-1 POP - s REAO/WRITE SUFFER IRWB) MEMORY WRITE CURRENT 2 DATA BUFFER BUFFER REGISTER p (OB) (MB) READ VOLTAGE LONGITUDINAL PARITY BUFFER ILPBl BREAK REQUEST WORD CNT OVERFLOW ADDRESS ACCEPTED ' ' DATA BREAK FACILITY CYCLE SELECT BREAK_STATE ^ ^ TRAKSfER Dl« (iNl + ->CA INHIBIT INCREMENT MB 1 MEMORY DATA ADDRESS 112) ADDRESS REGISTER MEMORY ADDRESS WIRING EXTENDED MEMORY EXTENSION DATA ADDRESS ;3) CONTROL lOP PULSES (3) " MEMORY UNIT FIELD HSEUCT REGISTER REGISTER lUSRl DEVICE MOTION SELECTOR REGISTER (OS) (MR) SELECT CODE - STOP/GO ,FWD/REV NORMAL OR C(3NTINU0US MODE FUNCTION REGISTER '. IFHl LETTERS A AND B IN UPPER RIGHT OF BLOCKS INDICATE EITHER STATUS A OR STATUS B GROUP OF ELEMENTS MOVE SEARCH READ DATA READ ALL ACCUMULATOR ENABLE TO T^£ INTERRUPT (END WRITE DATA WRITE ALL WRITE TIMING AND MARK TRACKS , {FDt errors: mark track end select b ' timing parity 5 e ERROR F .AG (EF) 1 t PROGRAM INTERRUPT OECTAPE CONTROL FLAG PROGRAM INTERRUPT HE(JUEST (DTCF) FACILITY , Figure 3-1 Type TCOl DECtape Control Functional Block Diagram 3-2 b. Window (W) - The window is a 9-bit register through which mark-track information serially shifted to generate control signals for the DECtape c. is is system. Data Flag (DF) - The data flip-flop requests a data break from the processor when a word ready to be transferred to or from the TCOl d. Memory Address - The memory address are 12-bits which constitute a fixed memory ad- dress for data transfers during the 3-cycle data break. e. Memory Field (MF) - The memory field register is a 3-bit register which is loaded by program control when a data transfer operation is specified and constitutes register B. bits 6, 7 and 8 of the status This information, together with the address supplied during the current address vides a 15-bit address for the actual data transfer during the third cycle of the f• cycle, pro- 3-cycle data break. Word Count Overflow Pulse - This pulse is received at the end of the first cycle 3-cycle data break when a word count overflow occurs and clears the WC current data transfer is complete. of the flip-flop to indicate that the The pulse is used primarily during continuous mode. It stops data trans- however, during the normal mode. fer, 9' granted. It Address Accepted Pulse - This pulse is generated each time a 3-cycle data clears the h. break is DF signifying that the data transfer has occurred. Control - The control logic generates the timing and synchronizing pulses to perform the functions specified in the function register and to coordinate the operations between processor and TU55 transport. i. Device Selector - The device selector decodes the lOT instructions for the DECtape and generates the necessary pulses to load status registers, read status registers and generate SKIP pulses. i* Unit Select Register - Unit select register is a 3-bit register which is gram control from the accumulator bits 0 through 2, and specified a particular ^' loaded under pro- TU55 transport. Unit Select Decoder - This device decodes the number in the unit select register and activates a select line to a specific TU55 transport. I. bits 3 and 4, m. Motion Register - The motion register is a 2-bit register loaded from the accumulator, with the appropriate command of Function Register - The function register is a 4-bit register, which specified the opera- tion to be performed by the normal or continuous mode. n. bits 1 GO or STOP (bit 4), FORWARD or REVERSE (bit 3). DECtape. The first bit of this register Is a mode bit which selects either The remaining three bits are used to specify one of the seven functions. Function Decoder - The function decoder decodes the contents of the function register, through 3, and transfers the decoded information to the control. °- Enable to the Interrupt - This is a I -bit register loaded from the accumulator, bit 9, to enable or disable the DECtape from the program interrupt. p. Error Register - A 5-bit register each section of which may be set by the TCOl control to indicate one of five error conditions. q. Error Flag - r. DECtape Flag - The DECtape flag is set at the completion of the currently specified s. WC Flip-Flop - The WC flip-flop is set on an XOR Status A command. The error flag is set by one or more errors indicated by the error register, operation. 3-3 t. DECtape flag. and/or the DECtape Control Flag - The DECtape control flag is set by the error flag gated into the interrupt to This flag is skipped on the SKIP lOT instruction and is also request program interrupts. u. control flag and the Skip Gating - Skip gating logic generates a pulse from the DECtape SKIP lOT to request a skip from the PDP-8. V. This gating is not affected by the enable to the interrupt. from the Interrupt Gating - The interrupt requests the program interrupt PDP-8 when the DECtape control flag is set and the DECtape is enabled to the interrupt. 3.2 DETAILED LOGIC OPERATIONS description of the operaThe information contained in the following paragraphs is a detailed flow diagrams Figures 3-2 and 3-3, tions of TC01 DECtape control and is supported by the instruction drawings are refer- and the engineering drawings located in Chapter 6 of this manual. The engineering locations on the enced only by the last number of the drawing designation and the signal and module drawings are referenced according to the coordinates on the margin of the 3-4 drawings. 3-5 Figure 3-2 Status Register A, Instruction Flow Diagram (Part II) 3-6 Figure 3-2 Status Register A, Instruction Flow Diagram (Part III) 3-7 2 ROTATE DB/RWBAC2(0)A WREN 111 A FRl (II Figure 3-2 Status Register A, Instruction Flow Diagram (Part IV) 3-8 lOT 774 lOT 771 SKIP ON DTCF lOT 772 READ STATUS LOAD STATUS REGISTER B REGISTER 8 AC 6-8 STATUS B V AC—* Uf 0-2 AC 0-AC Figure 3-3 Diagram Basic Read/Write Logic 3.2.1 of Figure Status Register B, Instructions Flow left-hand side The basic read/write logic for the Type TCOl DECtape control is shown on the 3-4. Each channel of the read/write circuit contains a flip-flop and input gates, a write am- plifier governed by the flip-flop outputs and a read amplifier. Read inputs are paralleled with the write amplifier outputs across the head allowing the read amplifier to respond to signals from both the head and the write amplifier. Figure 3-4 Read/Write Logic and Waveforms The read amplifier is a high gain differential amplifier augmented by a transient positive feedback. When a signal of either polarity is sensed by the head, the read-amplifier outputs switch im- mediately and are asserted unambiguously regardless of noise which prevents head cross talk resulting 3-10 from simultaneous writing, in the data channels and reading in the timing-and-mark channels. amplifier outputs U and V are standard DEC logic levels of -3V and ground. tive than D, the output V is asserted at ground and U levels are reversed. negative; is The read When input E is more posi- when D is more positive, the output Due to the positive feedback, the read amplifier oscillates in the absence of input signals. The read amplifier output waveforms therefore are rectangular whenever the differential input signal indeterminate. is The write amplifier is a saturated grounded-emitter push-pull amplifier with its output collectors connected through resistances to pins J and K. the enable level If amplifier is governed entirely by the state of the flip-flop. In the asserted negative, the write When the flip-flop is 1, K floats while J is returned through the resistance and saturated output collector to -13V. while K is negative. is When the flip-flop is 0, J floats two tracks corresponding to each channel on tape, information is recorded in a manner that makes read signals from the two head inductors reinforce on playback. tors can be considered as a single head inductor whose winding is center-tapped to ground, reading and The two induc- writing in a single track. When a write flip-flop contains 0, current flows from ground through the head inductor into K, and the polarization of the head core is oriented clockwise. across the head, is oriented toward the left regardless The tape polarization, as the tape moves of the direction of tape motion. Similarly when the flip-flop contains 1, tape polarization is oriented to the right regardless of the direction of tape motion. When reading, the current induced in the head by a change in polarization flows opposite to the current required to cause the same change; consequently, the current induced by a left-to-right (L-R) tape-polarization change is a current flowing out of the head toward pin E. and when a terminal is a current source it is positive. read amplifier input E to be positive; The head is a source, Thus an L-R tape-polarization change causes the consequently V is ground and U is negative. By the same reason- ing the right-to-left (R-L) polarization change induces a positive signal at D and results in V being asserted negative and U at ground. The Manchester recording system used in the Type TCOl DECtape Control requires two pulses to write each bit in a channel. The first pulse, ROTATE DB/RWB or RWB SHIFT LEFT, loads the write flip-flop with the value of the bit to be written, the second pulse, RWB 0-2, complements the flip-flop. Depending on the state of the flip-flop, the ROTATE DB/RWB pulse may or may not cause a polarization change on the tape. The RWB 0-2 pulse, however, causes a tape polarization change because the com- plement always changes the state of the flip-flop. When reading, the value of a recorded bit is detected by observation of the head inductor output as the polarization change (corresponding to the passes over the head. loaded with In first 1; The RWB 0-2 pulse produces a R-L tape polarization change when the flip-flop is and produces a L-R change when the flip-flop is loaded with 0. Figure 3-4, the ROTATE DB/RWB or pulse sets the flip-flop to the assertion of the posite state. complement) RWB SHIFT LEFT and RWB 0-2 pulses alternate. 1 level, the second pulse sets the flip-flop to the op- The RWB 0-2 and the ROTATE DB/RWB or This relationship is shown in lines The RWB SHIFT LEFT occur at 16.6 ms intervals. and 2 of Figure 3-4. Since the flip-flop is loaded through capacitordiode gates, the data input is free to change at each ROTATE DB/RWB or RWB SHIFT LEFT pulse. Line 1 3 shows a string of consecutive bits to be written on tape. bit at a ROTATE In line 4, the write flip-flop receives each DB/RWB or RWB SHIFT LEFT pulse and assumes the opposite state on a RWB 0-2 pulse. 3-11 In line left, respectively. 9 of Figure 3-4, the direction of tape polarization is labeled as R and L for right and The R-L and L-R transitions ore detected by the read amplifier as negative and posi- tive half sinusoids at pin E (opposite polarity at D) . If the tape is read in the same direction as written, the tape positions corresponding to the tim^ that the write flip-flop was complemented will show on R-L change as a 1; an L-R change as a 0. line 10; The heed voltages at read amplifier inputs E and D are shown in the read amplifier outputs are shown in line 11. In reading, the shift pulses in line 12 for the RWB coincide with those in line 2 which complemented the write flip-flop in writing. zation change representing a 1 quently, as shown in line 13, a If The R-L poluri- results in a ground level at U at the time of the shift pulse. 1 is Conse- shifted into the shift register as the first bit read. the tape is read opposite to the direction in which it was written, the polarizations reach the head gap in reverse order; that is, the head senses an L-R change where a 1 was written, etc. The Data written in one contents of the mark channel are selected to take advantage of this condition. direction and read in the opposite direction will be complemented. 3.2.2 Read and Write Amplifiers The read and write amplifiers are shown on Drawing Noi 15. The READ T TRK and READ MK TRK read amplifiers produce timing and mark-track outputs. The associated write amplifiers are only used to format tape. The D and E inputs to the READ T TRK read amplifier also serve as inputs to a sense amplifier which provides an SP input for the generation of an UP TO SPEED signal. The READ DO, READ Dl and READ D2 read amplifiers and corresponding write amplifiers on Drawing No. 15 produce the outputs necessary for the transfer of data between their associated RWB bits (RWB 3-5) and the DECtape. Appropriate inputs and outputs for this purpose are described in later sections of the manual. 3.2.3 Device Selector Logic The device selector logic decodes the output of the memory buffer, bits 3 through 8, and generates iOT pulses used to initiate the status A and status B operations listed in Table 2-2. pulses are produced by the circuit shown on the left-hand side of Drawing the circuit on the upper right-hand side of Drawing 3.2.3,1 STATUS A No. 14; STATUS B pulses by No. 6. STATUS A Decoding - The control operations which are initiated by computer instructions and which involve status register A are shown on Figure 3-2. These instructions are Read Status Register A (DTRA), Clear Status Register A (DTCA), and Load Status Register A (DTXA). The status A instructions contain an octal 76 in bits 3 through 8 of the memory buffer register and are decoded by device selector W103, location B7 of Drawing No. 14, Read Status Register A at event time 1, lOPl device selector to produce the 400 ns READ STATUS A pulse. is gated with the The information on status register A (shown on Drawing No. 2), consisting of unit select (USRO-2), motion control (MRO and MRl) function register (FR0-FR3), enable interrupt (ENI), and DECtape Flag (DF) is gated with READ STATUS A pulse location 3-12 B2-B8 to produce outputs (IMO-8) which are loaded Into the PDP-8 accumulator through connector DT05 or DTA05. Instruction lOT 6762, Clear Status A, is also decoded by the device selector on Drawing No. 14 and during Event Time 2. the 400 ns CLEAR STATUS Pulse IOP2 is produced and gated with the decoded output to generate A signal The CLEAR STATUS A output produces the 0 . —STATUS A, loca- A functions, on Drawing No. 2 and the ground CXA pulse location D8, Drawing No. 14. The positive going CXA pulse triggers the 5 fjs delay at R302 providing a -3V XSA DY output for the duration of the delay. Clearing status register A selects tape unit (8) by the 000 configuration of the unit select register. The negative XSA DY level at location BI of Drawing No. 2 tion D1, to clear the status register holds both the STOP and specified. GO levels at ground to prevent a change of motion to tape unit previously The positive going end of the XSA DY pulse jams the contents of MRl into BRMI motion. Either the BRMI (0) output or MRl (0) pulse will provide a ground level at both the FWD and REV outputs of S107, preventing a direction change from occurring to insure that only the newly selected unit re- ceives the new command. lOT 7764, Load Status Register A, is decoded at the device selector and gated with the IOP4 pulse at event time 3 to generate the 400-ns XOR STATUS A pulse. The ground XOR STATUS A pulse output performs an exclusive OR function with the buffered accumulator outputs shown at the center of Drawing No. 2, complementing the data in the status register A when the buffered input level (BACO-8) goes to ground at least 400 |js before the XOR STATUS A pulse is received. This permits specific information in the status register to be changed without affecting the remaining information. The negative XOR STATUS A pulse is amplified by PA603 (center right of Figure 5-1) to produce a negative XSAD pulse at 5107 and a positive XSAD pulse at the amplifier output. positive XSAD pulse is gated into PA603 (bottom right of Figure 5-1) to provide a 0 —AC The pulse which will clear the information in the accumulator. 3.2.4 Status Register B and Skip Instructions The status register B and skip-on-flag instructions, which are selected by an octal 77 in bits 3 through 8 of the memory buffer register in the PDP-8, are decoded by W-103, location DI-D3 and C1-C3 of Drawing No. 6. These instructions are Skip on Flags (DTSF), Read Status Register B (DTRB) and Load Status Register B (DTLB). The flow diagram is shown on Figure 3-5. At event time 1, when a programmed lOPl pulse is received, the PA produces the lOT SKIP ON DTCF (I), 400 ns pulse outputs. The output pulse B2. If is NANDed with the output of RI 13, location either an error flag exists or the DECtape flag is set, then the output of SI 1 1 will generate a ground SKIP pulse at pin K of W021 . The SKIP pulse causes the program counter in the PDP-8 to be incremented by one and skip to the next sequential instruction. When a programmed IOP2 pulse appears at event time 2, the next PA will produce the 400 ns READ STATUS B outputs. The READ STATUS B pulse is a common pulse input to the NAND gates associated with RI23 modules shown on Drawing No. 2, location B1-B8. A -3V level on any of the gate inputs which indicates that an error exists, the DECtape flag is set, or the bit configuration of the MEMORY FIELD register, will result in ground IM outputs from the 3-13 • NORMAL REAO-WIHTE HEM) OUTPUT Figure 3-5 associated gate at connection W021 . Slicer Network Waveforms This information is loaded into the PDP-8 accumulator by an OR transfer. If a load status B instruction is programmed at event time 3, on IOP4 pulse will be generated LOAD STATUS B pulse outputs from the amplifier on Drawing No. 6, location Dl The -3V pulse outputs are applied to the DCD gates associated with the 3-bit memory field register (MF), resulting in 400 ns, shown on Drawing No. 2, location Dl and D2, causing the memory field information from the buffered outputs BAC6-BAC8 to be loaded into MF0-MF2, respectively. 3.2.5 Unit Select Logic (Drawing No. 2) The unit select information USRO-2 in status register A is decoded by the Binary to Octal Decoder S151, Drawing No. 14, location C7 and C8. A ground level on one of the eight outputs will enable a SELECT level within the specified TU55 DECtape transport. 3-14 3.2.6 Motion Control (Drawing No. 2) The motion control Information in MRO and MR) of status register A determines when the se- lected TU55 transport will be activated and the direction of tape travel. The output of MRO will pro- duce either a FWD or REV level at location DI which is gated into the TU55 and to determine the motion of the tape. Only one direction signal can be active at a given time. The MRI flip-flop output is gated with the XDA DY delay level at C2 and determines as previously discussed the STOP or GO levels to the selected tape unit. 3.2.7 Function Selection (Drawing No. 2) The outputs of the function registers (FRl-3) are decoded by the Binary-to-Octal decoder R151, at location C3 and C4, Drawing No. 2, resulting in a ground level output on one of the selected function lines. If an octal 7 is indicated, all FR flip-flops set, a select error level will condition the DCD gate at the SEL flip-flop. Drawing No. 14 location D5 and allow the negative XSA DY pulse to set the SEL flip-flop. 3.2.8 Interrupt Enable (Drawing No. 2) Bit 9 of the AC determines the status of the DECtape Control flip-flop (ENI) which enables ENI(l) or disables ENI(0), the DECtape Control Flag, from causing a program interrupt. The output of ENI(l) will cause an interrupt request to be sent to the PDP-8 at location BI, Drawing No. 6. New Unit/Motion Select (Drawing No. 6 and No. 14) 3.2.9 The buffered accumulator outputs, BACO-4, are sampled by the OR gate. Drawing No. 14, location B6, to determine whether a new unit or motion has been specified. A ground level on any BACO-4 input or at buffered memory bit BMB9(0) which indicates a change on bits 0-4 of the status A will result in a ground level NEW U + M output. This level allows the negative going CXA pulse (Drawing No. 6) to be produced by XOR STATUS A or CLEAR STATUS A, to trigger the 120 ms U + delay. M The U + M(l) output from the delay is used to reset the up-to-speed flip-flop, location D8. The output of the up-to-speed flip-flop, when reset, disables the READ T TRK (0) inputs, location B6 and C6, from generating the timing pulse outputs TPO and TPl When the U + M delay is set, the negative output prevents the timing track pulses (SP) read from tape during the up to speed operation from triggering the RATE DY flip-flop. The SP signals are produced by a slicer network consisting of a sense amplifier and a slice control circuit at location C8 (Drawing No. 15). When the transport is running at normal speed, the sense amplifier input from the read/write head is a sinusoid of constant amplitude, as shown on Figure 3-5. When the transport stops or starts or changes direction of motion, the sine wave amplitude and frequency varies as a function of speed. Figure 3-5. This variation is illustrated by the amplified read/write head output on The slicer level shown in this illustration is preset and controlled by the slicer control cir- cuit G008. 3-15 The sense amplifier uses the slicer level as a bottom clamp for the positive excursions of the Since the amplitudes and frequency of the positive loops vary with the transport speed, the sine wave. loop crossover at the slicer level provides a measure of the transport speed, and this information is contained in the SP output pulses generated at the first crossover of each loop. When the U + M delay is reset, the ground level output conditions the DCD gate to allow the first SP pulse to set the rate delay. The ground level output of the rate delay conditions the DCD gate associated with the up-to-speed flip-flop to allow the next SP pulse which occurs within a 70 jjis interval to set the up-to-speed flip-flop and start the TCOl operations. The up-to-speed flip-flop is reset by the positive transition of the BRMl (0) level which indicates a stop motion and by the ground output of the timing mark enable level (T/M ENABLE) generated at S107, location D5. duces a 0 —WINDOW pulse which clears the window register on Drawing Resetting this flip-flop pro- No. 3 while the tape is not up to speed. 3.2.10 Timing Pulse Generation (Drawing No. 6) Timing pulses are required for both formatting the tape and for reading information from tape. During WRTM function the T/M ENABLE level activates the clock and allows timing pulses TPO and TPl to be generated, provided that the maintenance control panel switch (location B4), is in the WRTM WRTM/RDMK indicator to light and generates the SWTM level. The SWTM level is ANDed with MRl(l) and WRTM level, to produce TM/ENABLE which starts the 120 kc position. This position causes the On the positive transition of the clock pulse, the CKl flip-flop is complemented. The positive transitions of the CKT flip-flop output complements the CKO flip-flop. The outputs of CKl and CKO at clock. location C5, result in the generation of 100 ns timing pulses TPO and TPl which occur alternately every 16.6 |as. The CKO output is also applied to the timing track write amplifier. Drawing No. 15, to pro- duce the timing track pattern written on tape. Timing pulses are also enabled by the SWTM output from the maintenance control panel switch and by the WREN level at location C4 and B4. During the write function when the C2 flip-flop goes to zero, the negative transition sets the WREN flip-flop and generates the WREN(l) output. The WREN flip-flop is reset again at C2(0) when any one of the ANDed inputs, that is associated with the write functions, is removed. This flip-flop allows a full data word to be written, even though one of the enabling level inputs have been removed before the end of a word had been reached. Timing pulses TPO and TPl are generated during read operations when the UP-TO--SPEED(]) flip-flop is set at location B7, Drawing present, No. 6. The inverted output is gated with SWTM level which is when the maintenance control panel switch is any position other than WRTM, to provide a ground conditioning level to the DCD gates associated with the TPl and TPO power amplifiers. When the timing track signals READ T TRK are received at location C6 and B6, the positive going pulse to the gate, generates the timing signals. The TPO and TPl outputs are applied to PA, location A5. DCD The out- put of the power amplifier triggers a 10-^JS delay during reading and writing data, producing a -3V output to inhibit any extraneous timing signals which may be generated as a result of cross talk between data and timing channels. 3-16 3.2.11 Counter Register (C) (Drawing No, 5) The counter register, location D5-D7, Drawing No. 5, consists of four flip-flops used to con- trol the blocks of information on the tape, as shown on the timing diagram (Figure 3-6). the C2 and C3 flip-flops provide a four count used in formatting a data word on tape. and C3 provide a count of six for the mark-track information. 1000 by the 1000 —CO-S The outputs of Outputs CO, CI, Initially the counter register set to is pulse produced by the ground C-SYNCH and the positive transition of TPO. This count presets the counter in synchronization with the tape and starts the first count of both the four and six counts. The count sequence is shown on Table 3-1 . The word count sequence (C2 and C3) re- peats every four TPO pulses and mark-track count (CO, CI, and C3) repeats every six TPO pulses. Table 3-1 Counter Register Sequence 3.2.12 CO CI C2 C3 1 0 0 0 1 1 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 1 0 1 0 7 1 0 1 1 8 0 0 0 0 9 0 0 0 1 10 0 1 1 0 11 0 1 1 1 12 TPO Pulse (C-SYNCH -TPO) Window Register (W) (Drawing No. 3) The window register Wl-9, shown on Drawing No. 3, location D4-D8 provides a temporary storage for the mark-track information read from tape during all tape functions except WRTM. start of the loading operations all flip-flops are cleared by the 0 setting the UP-TO-SPEED flip-flop on Drawing No. 6. —^WINDOW At the pulse generated by re- When the tape is up to speed, the READ MK TRK information conditions the DCD gates associated with W9 flip-flop to allow the TPl timing pulses to shift the mark track information through the window register. The next TPl pulse which appears after the W2 flip-flop is set, will set the Wl flip-flop which will remain set until cleared by the 0 DOW pulse. The outputs of the window register are applied as inputs to six separate decode the inputs and generate specific mark-track level outputs. 3-17 —WIN- AND gates which MARK TRACK C3 I C 2. t L t r O 1 o 4* ( C0 o C-SYNCH MK BLK START MK BLK START 2IO 010 CflOOl) 725 OR f 5T IDLE -ST BLK MARK- MK BUK START MK BLK START WlK 0)0 ST REV CK DATA Q30 0AT-A DATA REV CK TRACKS SUISA FIRST DATA WORD ZNO DATA WORD ETTC O ^ DB J (WRITE DATA \ L I RWB V LPB (READ) t T t T T T ft t T f T RWB V LPB (WRITE) 0-» LPB t T T T t T f T T t t ROTATE DB/ RWB S= T T T T RWB SHIFT LEFT (WRITE) (TALL A RROWS') COIAP RWB O-a (short ARROWS) t T T T f T t f t t T T t T T T T T T T r t T r T T T T T t T f f T T t ttt ttt ttt T T t ttt T t t T T T tTt tTt Figure 3-6 t tt Timing and State Sequence Diagram (sheet 1) 3-19 3 7 TRACK 5 I I o ; I I OOOl lOI 1 11 lo ( I O 1 1 I 1 101 I I I lOlOOl lOOlOl I I I TPl C3 o I c a o I o I c (p NftK MK DATA 070 MARK TRACK DECODING DATA f- BLK END W\K BLK END 073 373 ETC STCK 2HD LAST DATA WORD LAST DATA WORD J I O-^ DB MK BLK END BLK END 373 373 -3r FIHAL.- - WlK ST - idle: — CHECK. SUM CK FOR PARITY ERROR rwbVlpb 1 RW8VLPB T fwRiTe:) l_PB ROTATE DB/ RWB X^^- RWB SHIFT UErT(WKlTE) T t t ttt i T T T A A I 1_ DB RWB SHIFT UEFT (READ) . t i i IL X . T t ttt t t tit T t t t tTt t T t T T T T T T T T t t T T t T T t t T t T ! t t t T t T ttt i\i ttt ttt ttt ttt tit COMP RWB0-2 (SHORT ARROWS) Figure 3-6 Timing and State Sequence Diagram (sheet 2) 3-21 ^•2- '2-' Counter Synch Level (C-SYNC) - Initially, when reading mark-frack information either in the forward or reverse direction, the first code to be recognized and used for synchronization is a result of the bit information formed by octal 525 or 725. This information appears after the reverse end mark codes sequence through the W-register. The bit configurations (shown on Figure 3-7) is decoded by the C-SYNCH gating logic (location CI), to produce a series of C-SYNCH level outputs which condition the control register. For the specific mark-track codes refer to Table 2-1 - MARK REV BLOCK I TAPE MOTION | EXTENSION I oTfENSmN 525 tOOIOlOIOlOl 0 I FWD BLOCK 1 5 2 0 I 6 2 0 t 0 I 0 1 1 O 1 © © © ©• ® 0 Figure 3-7 Mark-Track Decoding (C-SYNCH) The first code recognized by the C-SYNCH gating appears at (T). coded with the -3V output of SI all 1 1 (location D2) and with These nine bits are de- WRTM and generate the C-SYNCH levels for operations except write timing mark. With fwo extension marks (E) inserted in Will appear six times at the input clock. Only at the last decoding the counter with the mark-track ^•^•^^•^ the mark-track information, the C-SYNCH signal tothe AND gate and produce the C-SYNCH ©, however, will the control clock level to reset the control initiate a count and synchronize information. Block Marks (MK BLK MK)- The next bit configuration in the W-register, recogn.zed, is the forward or reverse block mark. after the C-SYNCH level is generated, as shown on Figure 3-6. wh.ch pre_cedes the TPl pulse sets the counter register to (1001). w.th the WRTM level and the counter register outputs, C0(1), The W-register information is gated and CI (0), The octal 2 position of the reverse guard to generate the mark, in the forward tape direction, or tape direction is recognized together with generate the next mark-track signal MK BLK START as shown in Figure 3-9. 3-23 pulse The positive transition of the TPO pulse outputs, as shown on Figure 3-8. portion of the guard mark in the reverse which is This information appears during the next TPl MR BLK MK octal 5 the lock marks to TAPE MOTION MARK OCTAL Mark-Track Decoding (MK BLK MK) Figure 3-8 TAPE MOTION • Figure 3-9 Mark-Track Decoding (MK BLK START-210) and inverted resulting in the The outputs from the W-register, except for W2, are AND gated MK BLK START outputs at location C5. shown on Figure 3-6. ate the This occurs at the next 1000 count of the control register, as This lock mark is the first of four that are programmed on tape. Each will gener- MK BLK START levels. The bit configuration required for the next three lock marks are shown in Figure 3-10. TAPE MOTION © Figure 3-10 © Mark-Track Decoding (MK BLK START-010) will decode the The same AND gate which decoded the (210g) W-register configuration (OlOg) and produce the additional 3.2.12.3 Data Marks - location B5 and C5. MK BLK START level, as shown on Figure 3-6. The data mark follows the last lock mark and is decoded by AND The W-register configuration is shown on Figure 3-1 3-24 1 gate R002, TAPE MOTION 0 0 0 1 I I © ® Figure 3-1 1 Mark-Track Decoding (MK DATA 070) MK DATA output levels as shown on Figure 3-6. AND gate (location B7 and C7) decodes an octal The -3V inputs are inverted and generates the After the last data mark has been decoded, 073 and three octal 373s from the W-register to generate a series of four mark block end signals (MK BLK END) as shown on Figure 3-12. This is accomplished by not decoding inputs from the W2 or W3 flip-flops. - MARK TAPE MOTION PRE FINAL DATA FINAL | CHECk"suM | LOCiT 073 or 373 0 © © © Figure 3-12 Mark-Track Decoding (MK BLK END) The next two mark-track codes, guard mark (51) and block mark (45), which follow the lock mark, are not decoded and the decoding continues through the same sequence, as previously specified, until the end marks (222) are decoded by 3.2.13 State Register (Drawing AND gate (location C8), which generates the MK END level. No. 3) The state register (Drawing No. 3, location B5-B7) is a ring counter which indicates the control states of the TCOl as determined by the mark-track decoding sequence. cleared each time the UP-TO-SPEED flip-flop (Drawing No. 6) is reset. The state register is The control states are se- quenced through the state register by the positive transition of the SHIFT ST pulses which are produced by monitoring both the decoded outputs of the mark-track and by the outputs of the state register at location D3. The outputs of the state register are connected to the maintenance control panel to pro- vide a visual indication during DECtape operations. and control states that are generated. Table 3-1 lists in sequence the various block marks The first five events occur prior to the generation of the first SHIFT ST pulse. 3-25 At event 6, the first block mark is decoded. The ground MK BLK MK level is inverted by S107 at location C3, and applied as one input to the two-input AND gate, location C3. The other inthe ST put is held at -3V. This signal results in the first SHIFT ST pulse at event time 7, which sets BLK MK flip-flop. At event time 10, the mark-track decoded output MK BL START is gated with the -3V ST BLK MK (1) output and generates the second SHIFT ST pulse. This pulse sets the ST REV CK the markflip-flop and resets the ST BLK MK flip-flop. The second MK BL START level produced by track decoding network, is gated with the -3V outpur of ST REV CK flip-flop to produce the third SHIFT ST pulse at event time 13, which sets the DATA flip-flop. MK BLK END level data words and until the 17 to set the ST FINAL flip-flop. is The DATA flip-flop remains set for all decoded which allows the SHIFT ST pulse at event time The second MK BLK END pulse is ANDed with the ST FINAL (1) out- put producing a SHIFT ST pulse, at event time 20, and sets the ST CK flip-flop. The ST CK (1) -3V output AND gated with the counter register output C2(l) sets the ST IDLE flip-flop at event time 23 which will allow the sequence of events, starting at event time 6, to repeat for the next block. Table 3-2 Sequence of Block Marks and Control States Block Mark or State 1 Tape Stopped (ST IDLE) 2 Start Tape 3 UP TO SPEED (1) 4 5 C SYNCH DATA SYNCH (1) 6 C (1001) 7 SHIFT ST 8 ST BLK MK(1) 9 MK BLK START 10 SHIFT ST 11 ST REV CK(1) 12 MK BLK START 13 SHIFT ST 14 DATA(l) • MK BLK MK 16 MK DATA MK BLK END 17 SHIFT ST 18 ST FINAL (1) 19 MK BLK END 20 SHIFT ST 21 ST CK (1) 15 Block Mark Code (Octal) 725 or 525 126 210 010 070 073 373 3-26 Table 3-2 (Cont) Sequence of Block Marks and Control States Event No. DIOCK fVlUrK RI/^^L' tKnf^flx i^y^^A DIOCK iViarK v_.ouc or State (Octal) 22 C2 (1) 23 SHIFT ST 24 ST IDLE(l) 25 Start at Event No. 6 126 Memory Field Register (MF) (Drawing No. 2) 3.2.14 The 3-bit memory field register (Drawing No. 2, location Dl and D2) uses data in the one outputs of BAG bits 6 through 8 to provide extended data addresses for the memory extension control of the PDP-8, The MF function requires a ground 0 —MF pulse input to clear each flip-flop and a -3V — LOAD STATUS B pulse input to load each flip-flop. The 0 MF pulse is applied to clear the MF at the end of each LOAD STATUS B pulse. The required delay is introduced by the LOAD STATUS B pulse from device selection (Drawing 0 —MF the No. 6) as an input to PA location C2. The desired ground pulse output is delayed until the trailing edge of the -3V LOAD STATUS B pulse appears at PA input. When the MF has been cleared, the LOAD STATUS B input at event time three produces either a -3V or ground level MFq(1), MFj(1), and MF2(1) depending upon whether the flip-flop has been enabled by its BAG input. returned to the PDP-8 memory extension control This information is NAND gates (Drawing No. 2, location B3 and B4). Upon receipt of a READ STATUS B pulse from the device selector, the -3V or ground level NAND outputs are transferred to their corresponding memory extension control addresses IM6, IM7, and IMS. Information contained in these NAND outthrough puts represents the programmed extended address initially loaded into the MF by BAC6(1) through BAG8(1). 3.2.15 Function Operations (Drawing No. 2) Function bits FR1-FR3 of the status register A are decoded to provide one of the seven function levels which are used to select the tape unit operations. within the control unit for each function 3.2.15.1 is A description of the logical operations described in the following paragraphs. Move Tape - The move tape function (MOVE) used to reposition or rewind tape is imple- mented by a Load Status Register instruction which specifies all zeros in the Function Register FR1 through FR3 (Drawing No. 2). The move function allows the tape unit selected to move in the direction specified by the motion register (MRO) until the end of tape zone is detected, without allowing data transfers to occur. The MRl (1) level from the motion register allows the BRMl flip-flop to be set at the end of the XSA DY delay and starts the tape motion in the direction specified by MRO. is reached the mark-track information is read from the tape. 3-27 If When "up-to-speed" no select error is detected, the tape • motion continues and the mark-track information is read without effect on the operation until the end zone is detected. The decoded end zone generates a MK END level (Drawing No. 3) which allows the END flip-flop (Drawing No. 14) to be set by the TPO timing. 3.2.15.2 Search - The Search function is used to locate block numbers on tape. all information is During this function, read from the tape, however, only block numbers are transferred to the PDP-8 where the program performs a comparison of the information received with a specified block number to deter- mine whether the two are the same. The search function is initiated by an octal in the function register 1 FR1-FR3. When the tape transport comes "up to speed, " the timing track pulses READ T TRK generate the TPO and TPI pulses, (Drawing No. 6). The control operations performed are similar to the READ function. The WREN (0) output allows the TPI pulses to generate RWB SHIFT LEFT pulses which assemble the information from tape in the RWB. The decoded mark-track information produces up to seven C-SYNCH levels, the last of which generates the first ROTATE DB/RWB pulse and rotates the first half of the block num- ber into the DB. Two more shift pulses are then generated at TPI times to assemble the next half of the block number into the RWB, and the MK BLK MK signal is decoded to shift the state to ST BLK MK At the C3 (0) transition another ROTATE DB/RWB pulse loads the data buffer with the block mark infor- —»DF No. 5 at location Dl) ation and, at the same time, the TPO pulse generates a 1 to set the data flag generating a break request. normal mode, the DTF flip-flop is also set to re- In the pulse (Drawing quest a program interrupt to determine whether the block number transferred is the block number desired. In the continuous mode the DTF is only set if a word count overflow WCO pulse is received. Unless another function is specified, the control continues in the search function, the marktrack decoding is performed and the data is assembled and shifted in the DB/RWB. which sets the data flag will not be generated, however, During the ST REV CK state, the 0 until the —LPB and RWB -V- The 1 —»DF pulse next MK BLK is decoded. LPB are generated for the parity com- The parity has no significance, however, during search and the PAR flip-flop is inhibited. putation. During the search function, the +1 menting of the current address cycle 3.2.15.3 in —*CA INH level, at location B6, will prevent the incre- the PDP-8. Read Data - The read data function is normally performed after the program has searched and and located the desired block number. Read data is specifiedby an octal 2 in function register FR1-FR3. After the search function is completed, the control is normally in the ST BLK information is decoded as a STREVCK. . When the mark-track MK BLK START, the SHIFT ST pulse (Drawing No. 3) changes the state to During the previous states of the search function the ROTATE DB/RWB and RWB SHIFT LEFT pulses were generated. No data read, however, was allowed to be transferred to the processor. The ST REV CH level enables the TPI pulses to generate the 0 clears the LPB. —LPB pulses (Drawing No. 5) which The RWB -V- LPB pulses, which exclusive ORs the 6-bit RWB information into the LPB, are also produced during the ST REV CH. This permits the reverse check word (the last 6-bit read) to be included in the parity computation, and the last word is read. MK state 0—•LPB pulse clears the LPB before the first data The ST DATA is entered and the data is assembled and shifted by the RWB SHIFT LEFT 3-28 and ROTATE DB/RWB pulses as described in the read and write sequence (Paragraph 3.2.16). Each tir ime a ROTATE DB/RWB pulse is generated, a RWB -V- LPB pulse allows the parity computation to be performed. the if WC register is set, indicating that a word-count overflow has not occurred, the 1—»DF pulse (Drawing No. 5, location D2) at the C2 (0) transition will set the Data Flag (DF) requesting the 3-cycle data break to transfer the word in the DB to the PDP-8. ADDR AC pulse (location B5) clears the DF. When the request is granted, the The data-break request must be granted before the next ROTATE DB/RWB or the information in the DB is no longer valid, and a timing error will occur as a result of the ROTATE RWB/DB pulse and the DF (1) level. This sequence continues until the end of the data portion of a block occurs which is signified by the ST CK state. When the ST CK flip-flop is reset, the contents of the LPB should contain all "cones or the parity error will be indicated by the LPB/1 input which sets the PAR flip-flop. At this tirme in the normal mode, the ST CK(1) pulse will generate In the continuous mode, the the previous data block. is If 1 — I »"DTF pulse which will set the DTF flip-flop. DTF flip-flop will be set if a word-count overflow had been Issued during the DTF flip-flop is set, the programs, must specify a new operation. If It not set and the continuous mode is specified, the operation will continue as previously described. When a word-count overflow occurs during the middle of a data block, the data transfers will stop. The remaining words, however, are read and parity is computed. 3'2.15.4 Read All Function - The real-all function, specified by an octal 3 in the function register FR1-FR3, allows all information written in the data tracks on tape, including reverse check, bers, etc. to be read and transferred to the PDP-8 processor. block num- Read all can be progrommed initially or after a search function which locates a specific block on tape before reading begins. When the tape had reached speed, only one C-SYNCH level is required to set the DATA SYNCH flip-flop and the Information on tape is read even though It may not be synchronized. This can occur in the middle of a data word on tape. The operations within the DB/RWB during the read all function are similar to the operations which occur during the read-data function. The RWB SHIFT LEFT pulses (Drawing No. 5) are produced WREN (0) output to assemble the information Into the RWB. The ROTATE DB/RWB pulse then occurs as a result of the ROTATE ENABLE level and C3 (0) transition, causing the in- at time TP1 enabled by the formation in the RWB to be transferred to the DB. The same enable level and pulse transition also gener- ate anRWB V- LPB pulse which allows the parity computation. However, the parity flip-flop (Drawing No. 14) is disabled during the read-all function. The next two RP1 pulses again produce two RWB SHIFT LEFT pulses followed by another ROTATE ENABLE and RWB V- LPB pulse. At this time, the C2 (0) input (Drawing No. 5), enabled by the READ ALL input will generate 1--^DF pulse which sets the DF flip-flop, requesting a data break. In the the normal mode, with the FRO(O) V WRTM input applied, the 1 —DF pulse will also set DTF flip-flop requesting the program to specify a new operation. Although the next word Is not transferred, the setting of the data flag may result in a timing error requiring a new fied or a similar operation to be performed. set when the In the continuous function to be speci- mode with FRO(l), the DTF flip-flop is WCO pulse occurs from the PDP-8. The tape motion will continue, but no additional data transfers will occur. 3-29 During the read-all function, although parity is computed, mark-track information is decoded, and the state register changes, these operations have no effect on data transfer. Write Data Function - The write data function, specified by an octal 4 in the function 3.2.15.5 register FR1-FR3, is used to write data on tape in the data areas assigned by the mark-track coding. The write data function is normally initiated following a search operation which determines tion on tape where the data will be written. the block posi- The initialization process allows the tape to reach speed, information. the DATA SYNC flip-flop to be set, and the counter to be synchronized with the mark-track Specifying write data before the DATA SYNCH flip-flop has been set will result in no operation. When the write data function is specified after a search function, the control is normally in the START BLOCK MARK state. output The ST BLK MK (1) level is gated with the decoded window register MK BLK START level (Drawing No. 3, location D3) to the ST REV CK flip-flop, changing the state of the control. generate a SHIFT ST pulse which sets Pulses 0 —LPB and RWB ¥ LPB, a se- quence of pulses (Drawing No. 5) will load and clear the LPB during the reverse check state. However, the reverse checksum which occurs one 6-bit word before the data state will be included in the parity computation. Pulse and generates a 1 AO —DB — DF generated during the ST REV CK by the CI (0) transition, clears the DB pulse at location C3 which sets the DF flip-flop and requests a data break. The ST REV CK (1) level is gated with C0(1), location B2, to generate the WD EN level. This level allows the WREN flip-flop to be set at the C2 (0) transition and enable the data to be written. the transition of C2 (0), the control enters ST DATA. The WREN (1) output, gated with TPl at location B7 produces the first COMP RWB 0-2 pulse, which is required for the write sequence. With the WREN (1) flip-flop set, the RWB SHIFT LEFT pulses are produced at the C3 (1) transition. for the write operation is During described in Paragraph 3.2.16. If a The sequence word count overflow has not occurred 0 during the previous word, the data flag (DF) will be set each time the —DB pulse is produced. If a word count overflow is issued during a previous word, the write sequence continues, but the DF flipflop is not set with the result that all zeros are written in the remaining block on tape. At the end of a data block, the parity check character is loaded into the DB by the LPB DBO-5 pulse that is produced by the positive transition of the second MK BLK END level which is enabled by ST FINAL, C0(1), and WRITE DATA. The LPB information is written on tape in the checksum slot the same as a data word. In will set the the normal mode at the end of a data block, the positive transition of the ST CK (0) level DTF flip-flop and in the continuous mode the same transition will also set the DTF flip-flop provided that a word-count overflow WC (0) has occurred during the previous data block- The writers are disabled after the parity is written by the WREN flip-flop which is reset by the ground WD EN level produced when the data state is changed. The control continues to change states if DTF is not set and begins writing again in the block and the operations repeat in the same sequence. 3-30 3.2.15.6 Write all Function - The write-all function, specified by an function register, allows nonstandard formats to be written on tape, octal 5 in the bits FR1-FR3 of the such as the insertion of block numbers or codes at unusual locations on tape. This function can be preceded by the search function which determines the position on tape where the information will be written and can be implemented at any time to-speed" after only one after the tape has come "up- C-SYNCH level has been generated, which may cause the writing to be dis- placed by a half word. The positive transition of the WRITE ALL level, sets the This prevents the for the WRITE ALL function is 0 set, will reset — W INH flip-flop (Drawing No. 5). WREN flip-flop from being set and inhibit writing at this time. is shown in Figure 3-13. The timing sequence The positive transition when counter flip-flop C2 W INH provided that the WC flip-flop (Drawing No. 2), was previously set. The DB pulse is also generated at this time resulting in a I —DF pulse requesting a data break to write the first word. If the write all function is specified before the middle of the area assigned on tape word, the first word will be written in the next data area which follows. for a data the function is specified after the middle of the current data word position, the next data-word position will be skipped before the data word is written. however, the LPB The write sequence then continues. —* DBO-5 pulse which is If Parity is computed during this function, required to write parity is not produced. The state register continues to shift but has no effect on the operation. In the normal mode, the quest when enabled by EN! (1). 1 DF pulse will set the DTF flip-flop generating an interrupt re- During continuous mode, when a word-count overflow occurs, the WCO pulse will set the DTF flip-flop. The WC (0) level at this time will also set the inhibiting the writing of future words on tape; ^•^•'^•'^ W INH flip-flop however, the tape motion will continue. Write Timing and Mark-Track - The write timing and mark-track octal 6 in the function register is used to format a new tape by functions, specified by an recording the timing and mark-tracks prior to the recording of data. This function is only enabled with the WRTM/RDMK/NORMAL switch on the TCOl control panel in the WRTM position and with the WRITE ENABLE/WRITE the WRITE ENABLE position. is LOCK switch of the TU55 transport in The control panel switch (Drawing No. 6) generates a SWTM level which gated with MRl (1) and the WRTM level to produce the TM ENABLE levels. The TM ENABLE level activates the 120 kc clock producing the CKl and CKO outputs which generate the TPO and TPl timing pu Ises The CKO and CKl and TM ENABLE outputs are applied to the No. T TRK write amplifier (Drawing 15) to generate the pattern to be written on the timing track. The TM ENABLE level (Drawing No. 6) resets the UP-TO-SPEED flip-flop resulting in a 0— WINDOW level which prevents mark-track information from being decoded. DATA SYNCH flip-flop preventing synchronization of the control operations. 3-31 It also resets the TP (b TP 1 t t t t t t t t f > t t t « t > t > t t ) > t t t t t , t > t > t > t r C3 DATA CASE I : (WRITE ALL COMMAND t DATA WORD WORD DATA WORD DATA WORD DATA V70RD- WHEN CefjS)) WRITE ALL T W-INH FIRST WORD . O—^DB^DBRK RQST WC 0 I WREN CASE z:('WRITE ALL COr-lMAND WHEN -1 FIRST DATA WORD WRITTEN IN THIS SLOT H Ce(l)) WRITE ALL W-INH O FIRST WORD >-DB~~H ['*~nB DB<^DBRK RQST — . WC 0 WREN I FIRST WORD WRITTEN \N THIS SLOT Figure 3-13 Write al! Function, Timing Sequence Diagram (sheet 1) 3-33 TP0 TP 1 t I I t ^ t t I . I . I , t , I . I , t t I . I , I , I t t . I t I L r 0 I cz 0 DATA WORD DATA WORD DATA WORD DATA WORD DATA WORD- CASE l:(CM) T WRITE ALL F I W-INH 0 O —i-DB^DBRK RQST LAST WORD nB-»D& J-r£WCO£ULSE^ I WC 0 I WREN I -CHANGE FUNCTION AFTER THIS TIME 0 ^ DTF (CM) CASE 2:(NM) T WRITE ALL F I W-INH CiTOISH O LAST WORD ~ p- DB MB —^DB^ DBRK RC5ST FUNCTION ^ DURIN& _J THIS TIME I WC I WREN 0 Figure 3-13 Write all Function, Timing Sequence Diagram (sheet 2) 3-35 The WRTM and SWTM levels are gated with associated outputs to produce the WRITE SET level (Drawing No. 5). fiers At the C2 (0) transition, the WREN flip-flop is set and enables the data track ampli- (Drawing No. 15) to write the information contained in the RWB. The first word that is written on tape, however, will be within the 10 ft of tape designated for the reverse end code and will not be read during the read tape function. The WREN (1) level allows the RWB SHIFT LEFT pulses, the ROTATE DB/RWB pulses, and the COMP RWB 0-2 pulses to perform the write operation as described in Paragraph 3.2.16. DB/RWB at the C2 (0) transition generates the 0 —DB The ROTATE pulse which clears the DB and sets the DF flip- flop, requesting the first word. The programming format for the mark-track requires that the mark-track information appear in bits 0, 3, 6, and 9 of the data word. The information received by the mark-track write amplifiers (Drawing No. 15) is from RWBO (Drawing No. 4). buffer are bits 0, 3, 6, and 9. Therefore, the only data bits which appear in this This information also appears in data track 1 on tape which also receives information from RWBO. When the WRTM function is completed, the TM ENABLE levels are held active by the SWTM and WREN (1) inputs (Drawing No. 6). Enough TPO pulses are produced to cause the C2 (0) transition necessary to reset the WREN flip-flop (Drawing No. 5) and prevents the disabling of the write amplifiers with write current. 3.2.16 Read and Write Sequences The sequence of events that occur during the read and write functions are summarized in Tables 3-2 and 3-3, respectively. Abbreviations and symbols used in these tables are defined in a list of abbreviations in Chapter 2. The times of each event are specified in terms of control clock pulses C2, C3 and timing pulses TPl Illustrations of the bit contents of the RWB and DB sections after each . event has occurred are shown in the diagrams in the last column of the tables. are shown on Drawing The DB/RWB registers No. 2. The events for the read operation in Table 3-2, are programmed to assemble a 12-bit data word in the DB for subsequent transfer to the MB of the PDP-8 during a data break. At the start of the assembly, the first three bits 0 through 2 of the data word are strobed from the read amplifiers into the right half of the RWB (RWB 3-5). Bits 0 through 2 are then shifted left into the left half of RWB (RWBO-2) and the second three bits (bits 3 through 5) of the data word are strobed into RWB3-5. parity check is performed on the first half of the 12-bit data word. of the data word from the WRB into one half of the DB (DB6-1 1). strobe the last six bits (bits 6 through 1 1) At this time, a The next event rotates the first half The same sequence is followed to into the WRB and to perform a parity check on them. Another rotation transfers bits 0 through 5 from DB6-11 to another half of the DB (DBO-5) and bits 6 through from the WRB to DB6-1 1 . 1 The 12-bit word is completely assembled in the respective halves of the DB and is ready for transfer to the BMB of the PDP-8. 3-37 CM <i (no aj E • SP Q. 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CO a: I CO in 0 15 QJ CO 5: CM -o O CO MP 0 u <u a. ~ "> E o Q. c t- rf\ E O-8 o (I) ' 0 i. S. o-.ES ^ IT) i_ 0 0 O 00 CO 0 i §5 o CO Uo.t: ^ o o 5 < 10 < a. c (U c E o ay g£| 00 00 <u o C *- D I OQ X E s ii O. > 10 X o 4/1 '5 <u E " > > JS o £ "-a a X col"— a, '->- CO 5 o tt) D C „ c' O .- O **- O oc —Q-—c oio" c 5 CO <1> a: • <- I o CO O O CI3 CO The events for the write operation in Table 3-4 are programmed to request a 12-bit data word from the PDP-8, store it temporarily in the DB, and transfer it in 3-bit segments to the write amplifiers. The first half of the 12-bit data word is stored in one section of the DB (DBO-5) and the second half A DB/RWB rotation transfers the first half of the 12-bit word into the RWB and makes the first three bits (bits 0 through 2) available to the write amplifiers. A parity check is (DB6-11) in another section. then performed on the first half of the data word. supplied to the write amplifiers. In addition, bits 0 through 2 are complemented and Then the contents of RWB are shifted left so that bits 3 through 5 re- place bits 0 through 2 in RWB 0-2. Bits 3 through 5 are now available to the write amplifiers in normal and complement form in the same manner as bits 0 through 2. Event 7 on Table 3-4 rotates the second half of the data word into the RWB, where it is available to the write amplifiers in the same sequence as that used for the first half of the word. this During event, the next data word is requested and each half is temporarily stored in its appropriate section of the DB as at the start of the sequence. The sequence for writing the stored data word can be started as soon as the writing of the preceding data word is completed. 3.2.16.1 Read/Write Control Signals - The control signals which cause the read/write sequence to occur are produced by the logic shown on Drawing No. 5. mation transfer is shown on Figure 3-6, sheets 1 The timing sequence in relation to the infor- and 2. The following paragraphs are descriptions of the control signals and their origin. a. RWB SHIFT LEFT The RWB SHIFT LEFT pulses are required to shift the RWB register to the left during the read and write operations. Although several conditions must be satisfied to generate these pulses, the RWB SHIFT LEFT pulses for reading occur at every TPl, those for writing at every other TPO. The network for generating RWB SHIFT LEFT pulses (shown on Drawing No. 4, location B7) includes two DCD input gates. One gate initiates pulses for the read operation and is enabled when the write-enable (WREN) flip-flop is reset. When the ground TPl pulses appear at the input to the DCD gate, the PA produces corresponding ground WRB SHIFT LEFT pulses. The other DCD gate initiates pulses for the write operation and is enabled when the WREN flip-flop is set during the write functions. The RWB SHIFT LEFT pulses generated are supplied as inputs to Drawing No. 4. b. COMP WRB 0-2 Ground COMP RWB 0-2 pulses are required to complement RWB flip-flops 0 through 2 in Drawing No. 4, tion is to convert the bits contained in the flip-flops to the complementary form. This opera- performed because of the phase recording method used which requires that the word bits be fur- nished in complementary as well as in normal form. The COMP RWB 0 through 2 pulses occur at every TPl. The DCD input gate (Drawing No. 5, location B7) for the PA which generates COMP RWB 0-2 pulses is enabled when the write-enable (WREN) flip-flop is set. input, the When TPl pulses appear at the gate PA produces ground COMP RWB 0-2 pulses for application to RWB 0-2 (Drawing No. 4.) The COMP RWB 0-2 output is also used as an enabling input for the generation of RWB ¥ LPB pulses. 3-43 c. Rotate DB/RWB The ROTATE DB/RWB pulse, location B7, to is required to transfer the contents of the RWB DB6-n, the contents of DB6-11 to DBO-5, and the contents of DBO-5 to RWB 0-5. The pulse is generated when the counter register is reset by the 1000 C3 (0) transition when the ROTATE ENABLE level is present. —CS pulse and by the Before the counter is in synchronization with the mark-track information, no ROTATE DB/RWB pulses will occur during the search or read data functions. During the search function, this allows the ROTATE DB/RWB pulse to be synchronized with the first six bits of the block number preventing the block numbers from being out of sequence. d. 0 —DB The 0 —»DB pulse, location C6 (Drawing No. 5) is generated to clear the DB and to re- quest the next word for data transfer during write operations. During the write data function, the ST REV CK (1) gated with the WRITE DATA level to generate the 0 —DB allow the first word to be available when the ST DATA is entered. during the reverse check state to The 0 *DB pulses ore then pro- duced at the second gate circuit by the ROTATE DB/RWB when pulse WREN flip-flop is set,, — DB produced. The subsequent 0 — DB During the write-all function the first data word is made available by the 0 enabled by the third gate when the ROTATE DB/RWB pulse is pulse pulses during this function are produced by the second gating circuit previously described. e. BMB —"DB The ground BMB ter in —*DB pulse (Drawing Drawing No. 4 with the data bits, BMBO-BMB 1 No. 5, 1 location B2) is used to load the DB regis- from the PDP-8 memory buffer. The BMB-DB ground pulse is produced by the T2 timing pulse input, from the PDP-8 at pin T of connector W021, location A3. The T2 pulse is inverted by S107 and gated into PA603 when the ground DATA OUT level is produced. When a PDP-8 Data break has been granted, the -3V B(BREAK) level at pin P of connector W021, location B5, is gated with -3V FRl (1) level, produced during a write function or select error, to produce the DATA OUT levels. 3.2.17 Longitudinal Parity Buffer Operation The longitudinal parity buffer (LPB) (Drawing No. 3, location B1-B4) performs the parity check of the information in the data tracks. Essentially the parity check reads the number of binary zeros in each half of 12-bit data words and forms a parity bit which is recorded in the checksum control word at the end of the data block. The checksum is computed by complementing the bits of the LPB when the respective bit of the RWB is a 0. The LPB register outputs are gated at location B2 (Drawing No. 3) to produce the LPB=1 and LPB/1 levels. If all LPB register flip-flops are not set during a read data operation, the LPB/1 level will set the parity flip-flop (PAR)(Drawing No. 14) indicating a parity error has occurred. At the end of a write data operation, the contents of the LPB is gated into DBO-'j to be written after the last data word. 3-44 LPB Control Signals - The signals which control the LPB operations are defined in the follow- 3,2,17.1 ing paragraphs and are produced by the logic shown on Drawing signals are shown on Figure 3-6, sheets a. 0 —LPB —LPB 1 No. 5. The timing sequence for these and 2. Pulse The 0 pulse clears the LPB at the beginning of each block. Six pulses are gener- ated by TPl during the reverse check state, ST REV CK (1) to initialize the LPB register for computation of the parity character. b. However, only the last pulse is required for the operation. RWB Y LPB Pulse The RWB •¥ LPB pulse is used to perform the parity computation from the RWB to the LPB. The parity is computed at the same time the ROTATE DB/RWB pulse is generated during a read operation and at the some time the COMP 0-2 pulse is produced during the write operation. c. —DBQ-5 —DBO-S A LPB LPB pulse, location C7, is required at the end of the ST FINAL block to initiate the formation of a parity bit for recording the checksum control word at the end of the data block The enabling conditions used for the generation of the LPB —DBO-S pulse are a WRITE DATA level from the function decoder, ST FINAL (1) level from the state counter, and a C0(1) level from the control clocks When a ground MK BLK END pulse from the mark-track decoding network apDBO-S pulse is produced. This pulse is transferred to the RWB and DB pears at the gate 603, LPB — registers in Drawing No. 4 for use in gating information received from LPBO(l) through LPB5(]) into correspondi ng 3.2.18 DB 0-5 Power Clear (Initialize) and Error Stop Logic The PDP-8 Processor produces, and transmits to the TCOl control logic, a series of power clear (PWR CLR) pulses whenever the processor is started or stopped. generates a single pulse called INITIALIZE. The PDP-8/1, under these same conditions, These pulses, inverted at location A3, Drawing No. 14, are applied to the PA, location C2, together with the error stop signal, to generate the PWR CLR + ES pulses. The error stop signal is produced by monitoring the outputs of the error flip-flops MKTK, SEL, TIM, and END at location C4. When a (1) condition exists on any input to the NOR gate, as a result of an error, the ERROR STOP level will be produced. The ground PWR CLR pulses are used to reset the DATA SYNC flip-flop, WREN flip-flop, MF 0-2, DTF flip-flop, and the DF flip-flop when power is initially applied or removed from the ally set the U + PDP-8. In addition, the ground PWR CLR + ES signal will continu- M flip-flop (Drawing No. 6) enabling the delay to prevent UP-TO-SPEED flip-flop from being set during the detection of an error or when the PWR CLR (INITIALIZE) pulse(s) are received. 3-45 3.2.19 Increment CA Inhibit (+1 -» The +1 to prevent the CA INH) - CA INH signal (Drawing No. 5, location B6) incrementing of the current address. is generated during the search function When the current address (CA) is not incremented, the block number is placed in core memory at the same location for each block number transferred. 3.2.20 Address Accepted The address accepted pulse (ADDR ACC) (Drawing No. 5, location B5) is received at connector W021 from the PDP-8 during the 3-cycle data break. This pulse clears the DF flip-flop when the fixed data address, specified by the control, has been accepted for data transfer. 3.2.21 Transfer Direction Function bit FRl is used to indicate to the PDP-8 processor the direction of data transfer. During write functions, bit FRl of the function register is "one," indicating transfer out of the PDP-8. 3.2.22 B RUN Level The B RUN level input is received from the PDP-8 at location A2, Drawing No. 14. B The RUN (0) input, indicating that the PDP-8 is stopped, is used to reset the motion register flip-flops MRl and BMRl (Drawing No. 2) and is applied to the TU55 transports to halt all transport motion. 3.2.23 Fixed Address The fixed address is a preselected (wired) memory address specified by the TCOl control. The address is determined by logic levels applied to DATA ADDR (0-1 1) at connector W021 location A5-A8, Drawing No. 2. This address determines the memory location of the data which is transferred to the memory buffer in the PDP-8 during the 3-cycle data break. 3.2.24 Interrupt Request The INTERRUPT REQUEST level (location BI, Drawing No. 6) from the control is used to initiate a program interrupt in the PDP-8 processor. the EN! flip-flop (Drawing The interrupt enable is determined by the status of No. 2). When ENI is set, either an error flag EF(1) input or DECtape flag DTF (1) will result in the request for a program interrupt. 3.2.25 ERROR FLAGS (EF) The five flip-flops (Drawing No. 14) produce error signals at the occurrence of any of the errors listed under the STATUS B functions in Table 2-4. When a specific type of error occurs, the error detection circuits shift the appropriate flip-flops to a 1 state. The error input conditions that initiate a specific type of error signal are as shown in Figure 3-14. All error flip-flops are cleared by either a ground B PWR CLR pulse or a ground pulse from the output at location C6. These pulses are produced when a BAC 10 (0) level from the PDP-8 and a XOR STATUS A pulse from the device selector appear simultaneously at the gate input. 3-46 When any error signal except PAR appears at one of the inputs to NOR gate location B4, the gate produces an ERROR STOP output level. This output is used in forming the PWR CLR + ES signal. The same output is also passed through an inverter to produce an error flag EF (1) or EF (0) level. EF (1) and EF (0) levels are also provided when a PAR error signal appears at the input of inverter at location B3. ERROR CHECK MK TK (1) (MARK TRACK ERROR) END 111 lEND ZONE ENTERED! SEL (11 (SELECT ERROR) PAR (1) (PARITY ERROR) TIM (I) (TIMING ERROR) EF (11 (ERROR FLAS) 2. MK TK (1) - CO (0)AMOVEAST IDLE(0}AST BLK MARK(O) A ( mk BLK S TARTVMK DATAVMK BLK END VMK end) ERROR STOP PULSE XSA DyA[(WRTMASWTM)A(FRICI)A(WRITE OK) V(WRTMASWTM)V(RDMKAREAD ALL) V(SINGLE UNIT)] 4. PAR (1) STCK(O) A READ DATA A LPB )t 5- TIM (1) (1-»DTF ADTF(1))V (ROTATE DB/RWB A DFCOl) 1 V(X3ADAST BLK MARK(0)AST Figure 3-14 PROG. INT RE(3UEST lOLE(O)) Error Check Flow Diagram The EF (1) level resulting from any of the error signals is passed through another inverter to produce a corresponding complementary EF (1) level. Ground level EF (1) serves as one of the inputs to NAND gate (Drawing No. 6, location B2) for generating an INTERRUPT REQUEST level while the -3V EF(1) level used as one of the inputs to the NAND gate (Drawing No. 2, location B8). This the is gate, and similar ones for specific errors, are enabled by a PDP-8 READ STATUS B instruction to provide outputs which show the status of the TCOl 3-47 3.2.25.1 Mark-Track Error (MK TRK) - A MK TRK error signal is produced by MK TRK flip-flop (Drawing No. 14, location D6) when information read from the mark channel is erroneously recorded. When MK TRK errors are detected by the input gating, the gating output enables the DCD input gate of A ground CO (0) pulse from the control clock will set the flip-flop to a the flip-flop. 1 A ground state. C0(0) pulse indicates that a 6-bit character has been read from the mark-track and is in the window. One input to the MK TRK gating circuit represents one of four mark-track codes which is MK BLK START. These codes appear at times throughout the reading of the DECtape. Other inputs to the gating circuit prevent MK TRK error indications during a MOVE function and during the ST IDLE and ST BLK MARK intervals. and ST BLK MARK (0) levels. intervals because the control 3.2.25.2 These intervals are indicated by -3V ST IDLE(O) The MK TRK decodings are not valid during the ST IDLE and ST BLK MARK may not be synchronized with the DECtape at these times. Select Error (SE) - A select error (SE) is produced by SEL flip-flop (Drawing No. any of the select errors listed in Table 2-4 are detected. 14) when After the input gate is enabled by an SE de- tection signal, the flip-flop is set by a ground XSA DY pulse at the gate input. The following conditions will result in an SE error: SWTM: MCP switch is not set on WRTM while PDP-8 program is attempting to WRTM a. write timing and mark data on new tape. b. WRTM SWTM: MCP switch is set on WRTM while PDP-8 program has specified another c. FR3 (!)• WRITE OK: • function. DECtape transport control switch is set on WRITE LOCK while PDP-8 program is attempting to write. d. fied by RD MK • READ ALL: MCP switch is set on RD MK but READ ALL function is not speci- PDP-8. e. The function register contains a binary 111 which is not a legal function. In addition to the conditions listed, the single unit comparator circuits shown on Drawing No. 14, (location A5) monitors the single unit line from the TU55 transports and generates a select error (SE) output if the line indicates either no units or more than one unit hove been selected. tively accomplished by noting the resistance of the error level (SE) if the resistance is This is effec- SINGLE UNIT line and generating a ground select not within the specified limits. With no units connected, the voltage at pins E and K of comparator W520 is -9V. The voltage at pin D and pin L is held constant at -7.5V and -5V, respectively, by the resistance network consisting of RI, R2, and R3. When this condition exists, pin D being more positive than pin E will cause a ground level SE output at pin H indicating a select error. When one unit is selected, the resis- tance of the line which is effectively in parallel with resistor R5, results in a voltage at pin K which is between the constant voltage at pin D of -7.5V and pin E of -5V. This voltage condition prevents the difference amplifiers from conducting, and the output at pin H and N will be -3V indicating a no-error condition. If more than one unit is selected on the line, the resistance in parallel with R5 will be de- creased resulting in a voltage at pin K more positive than the -5V at pin L and the difference amplifier will conduct, resulting in a ground SE output at pin N. 3-48 3.2.25.3 Parity Error (PAR) - A PAR error signal location D4), during a READ DATA function 1 if is produced by PAR flip-flop (Drawing No. 14, the LPB check at the end of the data block does not equal The READ DATA and LPB 7^1 levels at the inputs of NAND gate (location C4) indicate the error . condition and enable the DCD input gate to the flip-flop. input will set the flip-flop. 3.2.25.4 Then a ground ST CK (0) pulse at the gate A ST CK (0) pulse occurs at the end of a data block. Timing Error (TIM) - A timing error (TIM) is produced by the TIM flip-flop (Drawing No. 14) when any of the TIM error conditions listed in Table 2-4 are detected. One operation that produces a timing error is to ROTATE DB/WRB when a DF (1). An error occurs because the data in the DB is no longer the same as it was at the instant the DF was set. gal operation is indicated to the The ille- TIM flip-flop when a ROTATE DB/WRB ground pulse appears at the DCD input gate at a time when the gate is enabled by a Another TIM occurs when a 1 DF (1) ground level — DTF ground pulse appears at the input to the DCD input gate of PA 3603 (location D4) at a time when this gate is enabled by a DTF (1) ground level. gal condition means that the TCOl is the program did not clear the DTF at the end of the last operation. flip-flop by collector triggering its I This ille- attempting to set the DTF at the end of a current operation but that The error is indicated to the TIM output with the ground level generated by the amplifier. A third TIM occurs when -3V levels appear simultaneously at each input to 4-input NAND gate (location D3) . This condition is illegal because it indicates that an attempt is being made to READ DATA or WRITE DATA while passing over the data position on the tape. The -3V ST BLK MARK (0) and ST IDLE (0) input levels indicate that the head is not passing over the ST BLK MARK and ST IDLE blocks and therefore is passing over the data position. The -3V XSAD input is a standard 100-ns pulse which is generated by PA S603 (location CI (14C1)) 400 ns after receipt of an XOR STATUS A pulse When all inputs to the NAND gate are -3V, the resulting ground level is used for collector triggering the 1 output of the TIM flip-flop. 3.2.25.5 End Error (END) - In normal operation the window register contains an end zone code (222) when the end zone of the DECtape is reached. At this time the ground level at the window decoder output serves to enable the DCD input gate to the END flip-flop (Drawing the next TPO appears at the gate input, the flip-flop is set. No. 14, location D3) . When A ground level at the 0 output of the END flip-flop indicates an error it it is not expected by the program but is legitimate if used to indicate the end of a normal operation (e.g., rewind). 3.2.26 DECtape Flag (DTF) The DECtape flag (DTF) network in the top center of Drawing No. 5 provides appropriate DTF output control levels which indicate the completion of specific operations. DTF flip-flop is cleared by either collector triggering its 0 output with a ground level from NAND gate R123 (location D5) or by the appearance of a PWR CLR ground pulse at its direct clear inA ground level for clearing through the 0 output is provided when a -3V BAC (0) level from the PDP-8 and a -3V XOR STATUS A pulse appear simultaneously at the input to the NAND gate. When put. cleared, a ground 1 1 1 » DTF pulse from one of three input gating circuits will set the flip-flop to a state 3-49 1 The inputs to gating circuit location C6 indicate the following conditions: a. FR3 (1): selection of any one of the SEARCH, READ ALL or WRITE ALL functions by function register. b. WRTM: selection of WRTM function by function register. c. FRO(l): selection of CM of operotion. When a FR3 (1) or WRTM ground level and a -3V FRO (1) level appear at the gating circuit DCD input gate to PA S603 (location- C5) input, the resulting ground level enables the pulse input at the DCD input gate will produce the desired PA output p'llse. pulse is necessary because DFT settings in the . The ground A ground WCO WCO input NM are inhibited in the CM until a WCO has occurred. One of the DCD input gates to PA S602 (location C4) is enabled when u -3V WRTM + FR3 (I) and a -3V FRO (0) (indicating NM) appear simultaneously at the inputs to the NAND gate. a ground 1 "DF pulse is applied to the DCD gate, the PA generates the desired Another input gating network controls the generation of a parity check in the NM or CM. In the 1 —DTF 1 NM, either a ground level READ DATA or WRITE DATA input of a ground ST CK (0) from the state register (Drawing 1 pulse. pulse at the start of the from the function decoder plus a FRO (0) level input enables DCD input gate (5D4). desired * DTF Then when * DTF pulse to be generated. In Then the appearance No. 3) at the start of the parity check causes the the CM, an enabling input is applied to the DCD input gate when the RD + WD, FRO(l) and WC (0) inputs are at -3V. 3.2.27 Panel Indicator Drivers The indicator drivers in Drawing No. 12 control the indicator lamps on the Maintenance These lamps are remote indicators of various TCOl flip-flops and are lighted when a -3V Control Panel. level from the I output of the respective flip-flop appears at the input of the indicator driver. 3-50 CHAPTER 4 I NSTALLATION This section contains general information on the installation and maintenance of the TCOl DECtape control. The installation procedures refer to a single cabinet installation of both TCOl control and two TU55 DECtape transports. Installation information for mounting additional TU55 transports or TCOl control in an existing cabinet is available upon request. INSTALLATION PROCEDURES 4.1 The TCOl DECtape control and associated TU55 transports are shipped either as a single unit cabinet mounted and crated or as individual units to be installed in an existing cabinet. The installa- tion information in this chapter refers primarily to cabinet mounted units as the requirements for separate units vary according to the specific existing system. Upon receipt of the unit, an initial visual inspection should be performed to insure that no obvious physical damage has been incurred during shipment. 4.1.1 Site Preparation No special site preparation is required for the installation of the TCOl unit. Adequate clearance must be provided for proper installation and for servicing. Figure 4-1 shows the installation dimensions required by the unit. When the cabinet is not physically attached to the PDP-8 console, both the power and signal cables enter through holes provided in the base of the cabinet. Casters are mounted on the cabinet base to enable the unit to be easily positioned and to allow sufficient clearance for the cables. flooring is 4.1.2 No sub- normally required. Environmental Conditions The environmental conditions for the proper operation of the TCOl control unit are limited by the magnetic tape used with DECtapfe. The acceptable environmental conditions for the magnetic tape are an ambient air temperature between +60°F and +80°F with a relative humidity level between 40% and 60%. The TCOl DECtape control operating environment is the same as that required by the PDP-8 processor. The installation site must also be as free as possible from excess dirt and dust, corrosive fumes and vapors, and strong magnetic fields 4.1.3 Power and Cable Requirements The TCOl control and associated TU55 transports operate from single phase line voltage of 105V to 125V, 60 c/s. The maximum current requirement is dependent on the number of TU55 transports 4-1 SWINGING PLENUM DOOR SWINGING DOORS 12) Figure 4-1 included in the system. TCOl Unit Single Cabinet Installation Dimensions The maximum current requirement for the TCOl control is 4A, and each trans- port requires approximately 2A maximum. A Hubble, 3-terminal, 220V twist-lock flush receptical rated at 30A with ground neutral should be installed near the site of the cabinet to allow connection to the power cable supplied. Figure 4-2 shows the internal and external cable interconnections as viewed from the rear of the cabinet. All other interconnections between TCOl panel assemblies are facilitated by the panel wiring which is exposed to the front of the cabinet. Panel locations DTAOl through DTFOl through DTFl 1 . DTAl 1 are connected by panel wiring to panel locations This allows the interconnecting cables to the PDP-8 processor to be attached to the bottom of the TCOl unit and the cables to additional peripheral units to be connected to the DTA locati ons. 4.1.4 DECtape Signal Connectors The following cable connectors are used to interface the TCOl control to the TU55 transport and PDP-8 processor. A description of the cable connectors are listed in the Digital Logic Handbook C-105. 4-2 TO ADDITIONAL TU55 TRAI^SPORTS AC POWER CABLE O 6 5 3 2 AC POWER CABLE DTA 1-11 CONNECTED TO DTF 1-11 CONTROL PANEL SWITCH CABLE DTD FIXED OR VAR PWR SUPPLY DTE MEM - - • - MF54 ME35 MF35 PE02 PF02 PE03 PF03 PE04 PF04 PE05 J02 J03 J04 JOS J06 - J07 - JOS - - - - Figure 4-2 TCOl Control, Cable Diagram 4-3 ' trol a. Connector W021 - 16 pin card connector to interface the PDP-8 and TC01 control. b. Connector W023 - 18 pin card connector which provides signals to the maintenance con- panel and to the TU55 transport. c. Connector W032-32 pin double card connector which provides analog read/write signals to and from the heads of the TU55 transport. 4-4 CHAPTER 5 MAINTENANCE The information contained in the following paragraphs is required for servicing the TCOl DECtope control. Information pertaining to the TU55 transport is contained in the TU55 DECtape Instruction Manual listed in Paragraph 1.3. The maintenance procedures contain a description of the switches and indicators on the maintenance control panel and general preventive maintenance instructions. When used in conjunction with the PDP-8 operating program and the TCOl maintenance programs, the control panel provides a visual indication of the operating state and content of the TCOl control. MAINTENANCE EQUIPMENT 5.1 Table 5-1 is a list of the equipment recommended for servicing the TCOl control in addition to the standard hand tools normally required. Table 5-1 Maintenance Equipment Equipment Manufacturer Model Multimeter Triplett or Simpson 630-MA or 260 Oscilloscope Tektronix Series 540 or 580, with Type CA differential amplifier 5.2 Head Cleaner kit (8705) Potter P/N A 425 484 Variable Power supply DEC 730 or 765 Module extender* DEC 1954 * Furnished with the PDP-8 Processor MAINTENANCE CONTROL PANEL The maintenance control panel on the DTA/DTB mounting panel is located at the cabinet front, behind the access doors. The panel contains a switch used in the operation of the TCOl and in- dicators which display the status and information in the control. Table 5-2 lists the function and panel designation of the switch and indicators shown on Figure 5-1 . The number of indicators for each designation is enclosed in parenthesis in Table 4-2. 5-1 STATE STATUS rmmnrmnnnnnnnnn MP W, .•.l;-,,->^J^-. i*-.-' WRTM WRTM RDMK ' ' ' rR . NORMAr' RDHK ^. ,. BM CNI DTF DF W RC D F C LPB nnnrmnm \ Xw / MR END SE PAR TIM COUNTER CO Figure 5-1 CI C2 C3 Maintenance Control Panels (Switch and Indicators) 5-2 Table 5-2 Switch and Indicators (Maintenance Control Panel) Designation Function STATUS (Indicators) USR (3) Indicates the contents of the unit select register. MR (2) Indicates the status of the motion control registers which selects; FR(4) stop, go, forward, reverse. Indicates the contents of the function register. FR (0) Norma I/Continuous Mode. FR (1-3) Octal code of the selected function. ENI(l) Lights to indicate that the TCOl the PDP-8 program interrupt. US(1) Lights to indicate that the selected TU55 transport is enabled to has reached the required speed for reading or W WC(1) 1 1 1 1 1 « Lights to indicate a word count overflow has not yej occurrea. MR (Indicator) 0) Lights to indicate that a mark-track error has been detected. END (Indicator) (1) Lights to indicate that the end of tape has been detected. SE (Indicator) (1) Lights to indicate that a function select error, or iiuiiapuii acict^rcu/ Or more man on© rransporr 1 selected. PAR (Indicator) 0) ki^iii^ iw iiiui vj pui 1 1 y tsrror nus oeen detected. TIM (Indicator) (1) Liohts to indicate a nroarfim timmn fniilf STATE (Indicators) BM(1) Liahts to Inrlirntp thnfr th^a Rln/*L- K/nrL- ctr**^ Ic activated. Kv- (i) Lights to indicate that the Reverse Check state is activated. DO) Lights to indicate that the Data State is activated. F(I) Lights to indicate that the Final State is activated. C(l) Lights to indicate that the Check State is activated. 1(1) Lights to indicate that the Idle State 5-3 is activated. Table 5-2 (Cont) Switch and Indicators (Maintenance Control Panel) Function Designation DATA BUFFER (Indicators) (0-2) (3-5) (6-8) (9-11) Indicates the content of the data buffer register. RWB (Indicators) (0-2) (3-5) Indicates the content of the read/write buffer register. DTF (Indicator) 0) Lights to indicate that the DECtape fJag is set. DF (Indicator) \i) Lights to indicate that a data flag is set requesting a data break. W (Indicator) U) Lights to indicate that the write enable level is activated. LPB (Indicators) (0-2) (3-5) indicates the content of the longitudinal parity buffer. COUNTER (Indicators) C0,C1,C3 Provides indication of the 6-count function of the counter register used for mark-track decoding. C2,C3 Provides an indication of the 4-count function of the counter register used for assembling data words 5.3 C-105 DEC MODULES Handbook The standard DEC modules used on the TCOI control are described in Digital Logic except for modules G882, G008, and G009, which are described in the following paragraphs. One spare module of each type is generally recommended to facilitate maintenance of the TCOI control. 5.3.1 Module Locations and Complement The position of the modules within the mounting panels, as viewed from the wiring side , shown in Drawing D-MU-TCOl-9 (sheets 1 and 2)of Chapter 6. In this drawing, sented by a rectangle with the module type designation at the top. to show the circuits that are contained on the module. In is each module is repre- Each rectangle in turn is subdivided general, the circuits are identified by the logic signal(s) available at the circuit outputs. figure Table 5-3 lists the type and quantity of modules used in the TCOI and references the number of the module schematic diagrams (Figures 5-5 through 5-24). 5-4 5.3.2 Circuit Descriptions The following circuit descriptions are provided to supplement the information in the Digital Logic Handbook C-105. a. MANCHESTER READER/WRITER G882 The Manchester Reader/Writer G882 is a standard size FLIP CHIP module for use in read- Each module contains two write amplifiers ing and writing one channel of DECtape Type 55 Microtape, and one high-gain differential read amplifier. b. The read amplifier saturates with a 1 mV input. MASTER SLICE CONTROL, G008, and Sense Amplifier G009 The Master Slice Control, GOO?, is a standard size FLIP CHIP module which supplies slice and clamp voltages for the 2-input Sense Amplifier G009. The schematic diagram for the G008 and G009 modules are shown on Figures 5-2 arid 5-3, respectively. Terminal connections between modules G008 and G009 are as follows. G008 G009 Terminals Terminals clamp M, B K,B 2nd stage clamp N,B N, B slice H,A S,D Voltage 1st stage Each voltage circuit contains a zen^r diode network with silicon diodes for temperature compensation. Emitter follower stages provide current drawing capability and low impedance outputs. The first stage clamp voltage is fixed while th^ second stage clamp voltage and the slice voltage are adjustable. The output characteristics are as follows. 1st Stage Clamp M, is fixed at +3.9V with respect to -15V. 2nd Stage Clamp N,B is variable from +0.6 to +1 1 .3V with respect to -15V. Slice Level H,A is Variable from 0 to -1 1 .6V with respect to +10V. The power requirements of the module are 5-5 -15V/45 ma; +10V(A)/0 ma; and +10V (B)/70 ma. -OA* lOV FIKED -OB -15 V UNLESS OTHERWISE INDICATED ARE i/4W,5Vb CAPACITORS ARE MFD DIODES ARE D - 66 2 R3 a RI3 ARE A )t2TSP RESISTORS notes: # IN429 6.2V 5% «M IN762 S.5V 250ra« 5% Figure 5-2 Master Slice Control, G008 4 , 220 10% UNLESS OTHERWISE INDICATED DIODES ARE 0664 CAPACITORS ARE MFD RESISTORS ARE l/4W(-, 5% MF RESISTORS ARE t/SW-, 1% Figure 5-3 Sense Amplifier, 5-6 G009 ( A> Table 5-3 TCOl Mod ule Complement Number Required Type Description Figure 1 GOOB ^ taster Slice Control 5-2 1 G009 Sense Amplifier 5-3 5 G882 Manchester Reader/Writer 5-4 n R002 Diode Network 5-5 9 SI 07 Irjiverter 5-6 9 SI 1 Diode Gate 5-7 4 R] 13 Diode Gate 5-8 7 R123 Diode Gate 5-9 1 R141 Diode Gate 5-10 2 S15I Binary— to— Octal Decoder 5-1 3 R201 Flip-Flop 5-12 20 S202 Dual U U Flin—Flon vU 5-13 4 S203 Tri u e III dI w FliD—Fioo II U \^ 1^ 5-14 8 S205 Dual Flip-Flop 5-15 1 R302 delay (One Shot) 5-16 2 R303 Integrating (One Shot) 5-17 1 R401 Variable Clock 5-18 4 S602 Pulse Amplifier 5-19 7 S603 Plilse Amplifier 5-20 1 1 1 1 1 1 1 1 1 1 1 W005 8 W050 30 MA Indicator Driver 5-22 2 W103 device Selector 5-23 1 W520 C om pa rotor 5-24 lamped Load 5-21 Module Characteristics The terminals for the module are shown in Figure 5-4. The input and output characteristics are as follows. Reader Inputs E, D - are differential signals centered at ground. is approximately 400 ohms to ground. The input impedance A nominal input signal is a sine wave between 5 kc and 30 kc Reader Outputs U,V - are standard DEC levels of -3V and ground. drive 10 mo of load at ground. 5-7 The outputs can Writer Inputs - N, R, and P are standard DEC levels of -3V and ground. load of 2 ma is The input shared by the inputs at ground level. Writer Outputs - J and K, are nominal 180-ma current pulses from ground to -15V. The power requirements of the module are +10 (A)/18 ma and -15 (B)/235 ma. check limits in both cases are ±20%. Both the reader and the writer circuits are returned to a common C, F ground. Xuo 0670 750 560 350D ' 'eno D4 I 08 SRB >7,500 >l,500 ?7,5i UNLESS OTHERWISE INOIC«TED RESISTORS ARE l/4Wi5% CAPACITORS ARE MMFD OlOOES ARE 06S4 Figure 5-4 Manchester Reader/Writer, G882 DIO -W- -w- Figure 5-5 Diode Network, R002 5-8 The marginal Its 00,000 100,000 ^ MFD ^0- I I I it" « ^ • ' 0(4 016 019 », .D-U2 SMI 0-««Z '1,000 $RI2 0-6625RI3 010 ; D-6«2'{ DM ' D-eszj ^-662$ltl4 >)|000 '3,000 J,000 0-662 SI^0O0 .D-6S2SI9,000 .O-6e2SIS,O0O UNLESS OTHCRWISC INDICATED RCSISTOnS ARC l/4W|9% DIODES ARE D-G64 TRANSISTORS ARE DEC 963> PRINTED CIRCUIT REV FOR DSL BOARD IS SIA Figure 5r6 Inverter, SI 07 OA.IOVIAI UNLESS OTHERWISE INDICATED: TRANSISTORS ARE DEC 969* RESISTORS ARE l/4WilO% DIODES ARE D-662 PRINTED CIRCUIT REV. FOR DGL BOARD IS SIA Figure 5-7 Diode Gate, Sill 5-9 OTHERWISE INDICATED RESISTORS ARE 1/4 W, 5% DIODES ARE D66Z UNLESS Figure 5-8 Diode Gate, Rll 3 Figure 5-9 Diode Gate, R123 UNLESS OTHERWISE INDICATED: TRANSISTORS ARE DEC 3C39-0 RESISTORS ARE l/4W,5% DIODES ARE D-664 5-10 DI4 -OA +ioy tAi • DZI 013 27,000 10% » Rro 100,000 012 020 -\4DiO MFD 019 Die DI7 05 H404 D3 DI6 01 015 UNLESS OTHERWISE INDICATED'RESISTORS ARE IMW, 5% DIODES ARE 0-664 Figure 5-1 p Diode Gate, Rl 41 UNLESS OTHERWISE (NDlCftlED RESISTORS ARE l/4v/;5% TRANSISTORS ARE DEC 3659 DtODES ARE D-664 2^ FF Figure 5-1 1 Binary-to-Octal Decoder, S151 5-11 i fP40 1 ion i 2 i D44 D4jj[ D3 ,018 0-0 ez 100 R3 >IS.OOO > I90OOO 19,000 >I5J000 >4,700> 4,700 >I5,000 RI2 15,000 UNLESS OTHERWISE INDICATED' RESISTORS ARE l/4«:5% CAPACITORS ARE MMFD DlOOeS ARE D-6S4 Figure 5-12 Flip-Flop, R201 UNLESS OTHERWISE INDICATED TRANSISTORS ARE DEC 3639 RCStSTORS ARE 16,000 RESISTORS ARE l/4WtS% CAPACITORS ARC MMFD DIODES ARC D-0B4 Figure 5-13 Dual Flip-Flop, S202 5-12 RI3 (5,000 RI4 15.000 RI6 15/500 >RI7 > laoo UNLESS OTHERWISE INDICATED: IIESISTORS ARE l/4WiS% CAPACITORS ARE HMFD DIODES ARE D-6e4 TRANSISTORS ARE DEC 3«» Figure 5-14 Triple Fllp-Flop, Figure 5-15 Dual Flip-Flop, S205 5-13 S203 UNLESS OTHERWISE indicated; RESISTORS ARE l/4W; 5% CAPACITORS ARE MMFD DIODES ARE D664 TRANSISTORS ARE DEC3639 Figure 5-16 Delay (One Shot), R302 RESSTCnS ARE I/4W 10% «• rS A 279P DUDES ARE D-662. TRANSISTORS ARE DEC 3639, CAPACITORS ARE MPD , Figure 5-17 Integrating 5-14 (One Shot), R303 OC GND -wor XD8 0-662 > DECZZiar-i DEC I0« •on ; 30091 HO-)H' 1 r 02B^-3r I—ou XaD-e CIS LoieiL-)|J UNLESS OTHERWISE INDSCATED^ RESISTORS ARE </4W: 5% CAmcrroRS are mmfd Onoes ARE D-««4 TRANSISTORS ARE DEC 3839-0 Rll IS A ttZTSP Figure 5-18 Variable Clock, R401 1 UNLESS OTHERWISE INDICATED. RESISTORS ARE l/4Wi 57o CAPACITORS ARE MMFD DIODES ARE D-664 TRANSISTORS ARE 0EC2894-Z9 Figure 5-19 Pulse Amplifier, S602 5-15 OCJi GND UNLESS OTHERWISE INDICATED RESISTORS ARE l/4Wj lO% CAPACITORS ARE MMFD DIODES ARE 0-664 TRANSISTORS ARE DEC 3639-0 Figure 5-20 Pulse Amplifier, S603 Figure 5-21 Clamped Load, W005 5-16 01 oae: UNLESS OTHERWISE INDICATED: RESISTORS ARE I/4W,' 10% TRANSISTORS ARE 0ECaBS4D IDECeS34B MAT BE SUBSTITUTED) Figure 5-22 ~ ' ' 30 MA Indicator Driver, — '~' W050 • OTHERWISE INDICATED: TRANSISTORS ARC DEC 36!9 UNLESS RESISTORS ME 1/4 W, 5% CAPACITORS ARE MMFO DIODES ARE D-eB4 Figure 5-23 Device Selector, W103 5-17 * —— • O/LC, ec GND UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4*; 5% DIODES ORE 0-664 TRANSISTORS ARE DEC 30093 Figure 5-24 5.3.3 Comparator, W520 Module Replacement Procedure When necessary to remove modules, the procedure is as follows. a. Turn off all power to the Type TCOl DECtape Control. b. Gently pull the module from the mounting panel. Use a straight even pull to avoid damage to plug connections and the printed-wiring board. Access to adjustment controls on the module or access to signal tracing points can be gained by removing the module, connecting a Type W980 Module Extender into the mounting panel, and inserting the module into the extender. 5.4 POWER SUPPLY 779 Power Supply 779 is a dual power supply unit designed for installation on a plenum door. One of the supplies furnished +10V and -I5V suitable for logic power; the other is a lightly filtered, The -15V outputs of center-tapped 30V floating supply suitable for furnishing power to solenoids, etc. the power supply are connected in parallel to supply logic power to both the TCOl and TU55 transports. The schematic diagram of this power supply is shown in Figure 5-25 and the electrical characteristics are listed in DEC System Module Handbook C-100. 15 Vac, 60 c/s (105V to 125V) Input voltages: 1 Output voltages: +10V; Maximum output current: 8A (limited by curve) Line load regulation: (under all line and load conditions) +10V regulated to 9-1 IV; -15V; center-tapped 30V (+15V -15V) regulated to 14-16V 5-18 all +15V supplies Ripple: IVat+lOV; 500 mV at -15V; 2.5V at 30V Size frequency regulation: ±3% Maximum voltage between 300V output and chassis: |N0 141 I I UNLESS OTHERWISE INDICATED » HETMAN MFG CO TAB TERMINAL IN PLASTIC BUSHING TERMINAL STRIP 1 CINCH JONES Figure 5-25 5.4.1 Power Supply Type 779, Schematic Diagram Mechanical Characteristics Pertinent mechanical characteristics of Power Supply 779 are as follows. 5.4.2 Panel width: 16-5/8 in. Finish: Chromate conversion, coating Power input plug: Jones No. 141 strip Power output plug: Heyman tab terminals Power Supply Checks The use of a multimeter permits output voltage measurements to be mode on the Type 779 power supply without disconnecting the power supply. An oscilloscope should be used to measure the peak-to-peak ripple content of each dc output voltage. Because the power supply is not adjustable, a unit that does not meet the following tolerances should be considered defective and steps should be taken to correct the deficiency! 5-19 Nominal Voltage Outputs Output Voltage Range Maximum Peak-to-Peak (volts) (volts) (volts) +10 9-11 -15 14-16 Output Ripple Voltage 1 0.5 ±15 (for center tapped 30V circuit) 5.4.3 Marginal Checks Marginal checks are performed to aggravate borderline circuit conditions within the control logic and thus produce observable faults. By recording the bias voltage levels at which circuits fail, progressive deterioration can be plotted and expected failure dates can be predicted. provides a means for planned replacement. This procedure Marginal checks are also useful as a troubleshooting aid to locate marginal or intermittent components (e.g., deteriorating transistors). Marginal checks are performed by operating the logic circuits from an adjustable external power supply located in the PDP-8 or a DEC Type 734B Dual Variable Power Supply. PDP--8/I supply is not varied for marginal checks; marginal checks however, can be made with an external supply. Raising the bias level above +10V increases the transistor cutoff required to be overcome by the preceding transistor, thus causing a sistor Lowering the bias level below +10V reduces the tran- below-par transistor to fail. base bias and noise rejection. This procedure provides detection of high-leakage transistors and simulates high-temperature conditions for checking thermal runaway. Raising and lowering the -15V supply has little effect on the logic circuits because the collector load voltage of most modules is clamped at -3V. fier circuits It does, however, increase and decrease the output pulse amplitude of the pulse ampli- (e.g., the delay circuits) and then provides a sensitivity check of the circuits which follow. CAUTION Increasing the -15V power to a value more negative than -18V will cause damage within the logic circuits. The panel for conducting marginal checks of the Type TCOl DECtape Control is located at the left-hand side of the wired panel assembly. from the marginal check bus; When switched on (up), switches lA through IF apply power when switched off (down), normal power is appli.ed. the top switch on each panel selects the marginal check voltage of +10V. the fixed voltage of +10V. The "up" position of The "down" position selects The lower switch of each panel performs the same function with the -i5V. A color-coded connector on the right side of each panel connects the normal and marginal operating voltages to the marginal check panel. all panels. The normal and marginal power buses are common to The normal power bus is connected to the Type 779 Power Supply, the marginal power bus to the marginal check power supply on the PDP-8. 5-20 A marginal check is performed as follows. a. Set- selector switch on marginal-check power supply to +10 Mc and adjust the power supply output for +10V. bo Start DECtape operation in a normal program or in a routine which fully utilizes the cir- cuits in the rack to be tested. no suitable program is available in the normal system application, se- If lect an appropriate maintenance routine. The maintenance programs provide basic exercises of specific functions and scope loops for these functions as well as a routine which redundantly exercises all functions. is c. Set the top normal/marginal check switch on the panel to be tested to its "up" position. d. Decrease the marginal-check power suppi/ output voltage until normal system operation interrupted. Record the marginal-check voltage. If desired, locate and replace the marginal tran- sistors at this time. e. until Restart DECtape operation and increase the marginal-check power supply output voltage normal operation is interrupted. Record the marginal-check voltage. If desired, locate and re- place the marginal transistors at this time. f. Set the top normal/marginal check switch in step c to its "down" position. g. Repeat steps a through f for the center normal/marginal switch on the panel being tested. h. Set selector switch on the marginal-check power supply to -15 mc and adjust the power supply output for -15V. i . Repeat step b. j. Set the bottom normal/marginal switch on the panel being tested to its "up" position, k. Repeat steps d and e and then return the bottom normal/marginal switch to its "down" position I. Adjust the output of the marginal-check power supply to OV and set the selector switch to "off" position. its 5.5 POWER CONTROL PANEL (Type 834) The Power Control Panel is mounted on the plenum door at the rear of the cabinet and is used in conjunction with the Type 779 Power Supply. The schematic diagram of the panel is shown on Figure 5-26 m1 1 —O REMOTE NOTES; a C2 CAPACITOR BATHTUB-DEC PURCH. SPEC -^CAF-OOOI gX.IMFD 6DDVDC CORNELL OUBLIER. CI TOGSLE SWITCH *f ST52P. RELAY *EM-I II5VAC EBERT ELECTRONICS. C81 CIRCUIT BREAKER^lSO-aZO-IOI 20AMPS 250V, 60CYC-CURVE4 DI.OE THYRECTOR GENERAL ELECTRIC 20 Sr-4 B4, liSV S I Kl 6 TERM JONES STRfP #5^1-6 Figure 5-26 Power Control Panel Type 834 5-21 5.6 PREVENTIVE MAINTENANCE Preventive maintenance consists of procedures performed prior to the initial operation of the equipment and periodically during its operating life. These procedures include visual inspections, cleaning, mechanical checks, and circuit element checks. Marginal checks are also conducted when considered necessary to aggravate border-line conditions or intermittent failures so that theycan be detected and corrected. A log book should be available for recording specific data which indicates the rate of performance deterioration and provides information for determining when components should be replaced. Except for marginal checks all preventive maintenance procedures should be performed once a month or every 200 operating hours, whichever occurs first. 5.6.1 Mechanical Checks The following mechanical checks should reveal any substandard conditions in the mechanical operation of the control unit. a. Clean the exterior and the interior of the control by means of a vacuum cleaner or by using clean cloths moistened in a nonflammable solvent. b. Clean the air filter at the bottom of each cabinet. Remove the filter by removing the fan and housing which are held in place by two knurled and slotted screws. Wash the filter in soapy water, dry in an oven or by spraying with compressed gas, and spray with Filter-kote (Research Products Corp., 1015 E. Washington Ave., Wisconsin, 53703). c. Clean all rotary switches with a spray cleaner such as Contactene. d. Lubricate door hinges and casters with a light machine oil. e. Visually inspect the TC01 for completeness and general condition. f. Inspect all wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and mechanical security. g. Repair or replace any defective wiring. Inspect switches, controls, knobs, jacks, connectors, transformers, fans, cofsacitors, lamp assemblies, etc. h. Wipe off excess oil. Tighten or replace as required. Inspect switches for binding, scraping, misalignment, and positive action . Adjust, align, or replace as necessary. i. Inspect all racks of logic to assure that each module is securely seated in its connector, j. Inspect power supply capacitors for leaks, bulges, or discoloration. citors exhibiting these signs of malfunction. 5-22 Replace any capa- CHAPTER 6 ENGINEERING DRAWINGS This chapl-er contains the logic block diagrams and module location diagrams of the DECtape Control. TCOI The equivalent drawings for the TU55 DECtape transport are contained within the TU55 Instruction Manual 6.1 SYMBOLS AND DESIGNATIONS The block and signal symbols used on the logic diagrams are defined in Chapter 10 PDP-8 Maintenance Manual together with a description of standard DEC logic levels. of the The signal desig- nations assigned are defined in Table 2-6 of this manual. 6.2 Drawing List Table 6-1 lists the pertinent engineering drawings referenced in this manual. These drawings relate to the discussions in this manual and do not necessarily reflect the latest revisions incorporated in the equipment. When discrepancies exist between the drawings contained in this manual and the drawings shipped with the device, the latter should be assumed to be the correct drawing set. Table 6-1 Engineering Drawing List Number Revision Title BS-D-TCOl-0-2 E MF, USR, MR, FR BS-D-TCOl-0-3 B WINDOW, MD TRK, STATE, LPB BS-D-TCOl-0-4 C Error Flags BS-D-TCOl-0-5 D Control BS-D-TCOl-0-6 E TP GEN TT GEN MU-D-TCOl-0-9 (Sheet 1) F Utilization Module List MU-D-TCOl-0-9 (Sheet 2) F Utilization Module List BS-D-TCOl-0-12 Panel Indicator Drivers BS-D-TCOl-0-13 Maintenance Control Panel BS-D-TCOl-0-14 E Error Flags BS-D-TCOl-0-15 E R/W AMPS, SP GEN, TEST CONN. 6-1 H J H J i yRiTE SINGLE UNIT i FWD Emu REV BRUN s'o STOP XSA DY IVDZI rr^ r r r r CYCLE SELECT fsi0 7 iDTDII I £" -owco WCO r r fsTo? . DTCII T E r E e^e r ^ °wc H SE DTDI3 7 D S 3 ^ 2 -p-i> 0 I DTDIZ D I 2l 2° CLR , 1 T S S t=-' Trr^ S +7-' _t SEARCH t" f t t~l J S fz-l J fr-' I _ r-'l STATUS B ! READ DATA SEARCH. WRITE READ DATA- ALL MOVE OMOVE r |t BAC6<0) BAC 6(0 BAG 7 0 SAC BAC8;?il BACSfO 7(1) BMRI(0)-£oCf-| N SI07 ^ 7 1 4 3 I 22 +ES R > t L 1 T U sisi S203 DTE3I 1 I 22 f_ READ READ ALL DATA I . S 1 DATA WRITE WRTM ALL ' W02I DTAIO WRITE ALL L SE [*^? SI5I WRITE WRTM DTP 10 WRITE OK r PWR CLR- J { BMR0 CI „ S202 *DTC50 2< ^ 1 1 DTC 28 0 i 2° BRUNfO;^ I I BAC 0(0 BAC I BAC 2 to (I) >BAC 3 (I) > BAC 4 (I) BAC 5 to BAC S (0 BAC 7(0 SI07 BAC 1(0) 1 . DTC29 I H^STOP BMRlC0)-^^=i^ W02I DTA05 W02I , DTF05 M ( > H ^ H K M IM 2 IM3 IM4_ IM 1 RI23 p" usRad'i-Ji USRl(l) USROi'l)- M R 0(0— DTE 10 tr MRi(i>— FRO(I) Ifrk,)'^ READ STATUS A L.L= •on READ STATUS B- L WJS'Z 1 , 0TA1^7 C »D C D W02I • W0ZI fE E fH H >K >M iP »S K M P S i DTF07 »T < T < V DTA)S8(. D V W!^2I D E DTF^fS^ ! i 1 1 1 i i 1 DATA DATA DATA DATA DATA DATA DATA DATA DATA ADDR 0(1) ADDR 1(1) ADDI?2(l),ADDR 3(l)A DDR4(l)ADDIf S(l)ADDIf 6(0 ADD(?7(0)A DDI?8(0 DATA DATA DATA ADDR9CI) ADDI?I0S3)ADDRII®) note: GND PINS C,F;j,L,N,R,U ON ALL W02rS * USE SLOT DTBOl IF SERIAL NO. OF TCOl IS LESS THAN I3J MF,USR,MR,FR BS-D-TC01 -0-2 Rev. E 5 6 7 I \ T 4 \ 3 \ 2 1 1 WINDOW, MK TRK, STATE, LPB Rev. B 6-5 BS-D-TCOl-0-3 B- ROTATE db/rwb l<WB SHIFT 1 D, R*B3(0J LPB-^DBO -5 Error Flags BS-D-TCOl -0-4 6-7 Rev. C Control BS-D-TCOl-0-5 Rev. D 8 I 8 7 6 I 6 7 \ \ 5 _1 4 5 f 4 \ \ 3 P 2_J I I 3 2 \ TP GEN TT GEN \ 1 1 BS-D-TCOl-0-6 6-n Rev. E 7 3 2 10 12 14 13 15 16 17 18 19 20 21 Mil DATA BMBo(i) B*C9( I BH B2< lOP DT A 1 iOP 2 ADDR lolj) TO DATA DATA ADDH llli; 1 BMB3(0) 6(183(1) 25 26 27 28 29 30 32 31 1 D4T4 BIT 9 TO DATA DATA BIT 8 LOAOS MAINT M'iCE [)ATA BJ T BMBgii, I em CLR i.'85e BIT DATA ADDRj!i ADDR8 BK Bm 24 -BIT 9 DATA BACI Id) 23 DATA ADDR 90) TO 22 1 1) '^050 B-RQT OB RV¥B USROf 1) USRI ( DTFI I) USR2I i) MRO wREN( I LPBO( I DF( I) I END ro ( ) t DBII MRI FRO( FRI ( I) FR2{ 1) FR3( 1) ( 1 0) 1 DT B UP TO TO LPB5! IM (0 WC( o ST BLK MR ( I ( [)ATA( I CDNTiOL - SE[ I) TIM{ i PAR( ) Flt^K ST CK( 1 ST ) maintemnce: I TRK{ I) i ST RtV CK ST BLK MR( I C0( I) TO C3( ) ENI ( IP TO ^f: EttI SPEED (0 I I I FNDf 1) I ST ST REV IDLi;[ I CKU) S202 COOOO, HO" MK BLK 222 BAC S{p) MK END 2ZZ R/W C( 1001 0-5 c (looi) DT TIME TRACK MK BLK MK BLK - MK BK C MK BLK LPB5 END INTERRUP" t/m . ENABLE MARK TRACK R./W Dl 02 TRACK TRACK CiaCK 120 KC 070 COMM CABLE MCP MK DATA — START SWITCH 210 or 010 REQUEST 070 MCP MK DATA LIGHT MK END t/m 222 MK BLK ST 210 OR OK ENABLE S20g TRANSPORT IKFO CABLE S202 HOVE rv;B2 R/'W D0 TRACK SEARCH RWB5 ST G853 SHIFT MOTION ST A S2g3 TP^ FMD REV (iE) FWD SELECT ERROR REV WRITE BLK DT READ DATA AODR (PAR) D WRITt Data MK READ ALL WRITE DATA WRITt ALL BLK UbR0-2 SHI FT DECODER ST WRITE SET ACC PARITY ERROR WRI IE SET (TIM) TIM! NG ENABLE iiJITCri WRITE ROTATE END WRTM WM TE ENABLt MCP SET DB/RWB 373 dR 073 MK BLK FND -OR MCDUlE count 5EE PL* A-TCOI-0-9 Utilization Module List MU-D-TCOl -0-9 (Sheet 1) 6-13 Rev. F 1 2 1 3 1 4 I 5 1 6 1 7 1 1 2 3 4 5 6 7 8 9 iO II 12 13 14 52S5 S205 S205 5?1)5 S?B5 5153 RI23 RI23 Ri23 R123 S232 S20 2 S202 15 17 16 p. SB'S 18 19 20 21 22 23 WI03 W103 R302 5107 SI R002 EF{ USR 0 DBq DB3 CBj DB5 OBij A DBB-2 - D86~8 nT m™ - ysR2 READ STATUS MB, TPI MFI DBS -5 - - 0B9-I!- !M 0-5 JM 6-9 MB OT SK BAC f DSg DB7 DR DBg MRq FRq 6 —>-AC — ~ MR| ERROR X 5A lit SH IFT C0 = z W02I W021 RyrE PARITY BMBq( -Ei4C9( 1 1 ) LPB BM6| [ BHB6(0) EM Bgt 1 ADDH .9 DT B BAC8* lOP 1 1 - TO BMB7(ei) BMB3(i3) EM B-;.( DATA lOP 2 F BMB3[ 1 1 Tl BMB8(0) BMBg( lOP U sKBi^i n BM Bgi 1 1 CLEAR READ ST-ATys A STATUS B ) BIT Q INT REQ DATA — ADDB3 ^ftC B RUN BMB5(0) BMS|(j( MFq BMB5( 1) BMB 1 1 ( Rl 13 5503 .Sid? U -i-M 5503 Sin 0 TRANS DIR TO OATA -BIT 8 (B) Bfi^AK V-; CYC SEL — CA INH WCO HFl 1 1 W1 (1) _ TO I« 5-8 +1 BLK £NC MFOI 1) in W9 ST DATA II XSA EF(0) (1] CK 0 HI EF(l3) 1 PWR CLR —^DTF XOR DATA SYNCH ADDR aCC MFI LOAD STATUS A STATUS B 1 3 £M 0-2 OB U» TO SPEED 0 OB or ROTATE EMABLE LPB-^DB C- 0-5 1—»-DF ES TM RATE DY[1 U+MID HK^RK SYNC H it 1 OB/RWB SP 1 ^ DATA CK 1 (1) |.if2(l) t COMP RvJB C )CA SYNCH OUT R WD DF XSAD DATA II - 5fin? PWR CLR SY\cH —»-EF B RUf*{31 WK DATA DATA BIT 0 - S107 LPB—*-DF 5E WK BLK ST ROTATE B PWR CLR EN W02 3 SYNCH MK BLK UK EKI T2 1>S W02 3 C- SPEED FR| - WD 1 TO IH3 ) ADDR BREAK RQ SKIP ! TO 1 - — DATA 1 6MB2! n S202 UP ADDR 10 - "11 M DATA 3AC0( S202 DATA 1 "BACM {ir - RATE S202 i-TF LP3-*LPB DATA I- TO RI23 V C2 ERROR CI EF 4- -W5T W021 A —'{YMT~ STOP 0—h-AC 8QST . c 0- 5 OY BRK C3 DF 000 0 ROTATE ENABLE 1 32 31 ^?C13 — SEL — STOP l/B| 30 R;lS ~(HK Tk)ERROR c USR, 29 LEFT II TRANS 28 S602 1 N 1 26 •3 R WB3 - 25 CO^N _- _ U+M 1—^DF BUS 24 —w^as ) NEW TPI DTCF( t) A 1 1 ON i« a-5 MF2 ~- 1 1 1 8 1 MK ENABLE (51 l-*-OTF B TK C- MK TRK 0J BEAD Dan; WRITE READ Die; READ j2ni TM T M 1 1 NG PWR CLh ERROR OK - NEW — 1—OF 1 •LPB U-t-M DF NEW ENABLE Ll — DTF 1 DTF + M. C C D D " 1 1 2 1 3 1 4 t 5 1 1 6 7 8 Utilization Module List MU-D-TCOl-0-9 (Sheet 2) 6-15 Rev. F ! DTBOI , 22 PIN rwoso 2 2 PIN fwoso AMP DTB04- AMP DTB06 W023 22 PikJ AMP, DTBIO 5 USRC(n DATA (I) USRKO ST FINALfn- USRZ{I) STCK (O MRO (D- ST IDLE (I) n IZ PIN ^ W023* W023 * DTBIO fwoeo DTB06 ID LPB3(]) DBI ID LPB4(l) I (I) AMP fn] OTBiZ DBIOfI) RlVBO(l) - ^ W0Z3 * DTBII T - LPBSfO --15V RWBI (I) CO(ll - DBO(I) RIVBZ(I') Cl(l) - FRO (l) DBI (I) RW63(0 C2(0 - FRI (I) DBZlO RWB4CU csO) - W0|3* 2.2 PIN AMP. U MRI (I) I Pi I rTN - ^050 IV050 DTS03 FRZ (l) DTB05 0B3f0 - DTB07 DTB02> MK TK (l) RWB5(I) W0Z3 * D TBI2 DTF(0 DB4(I) - 12 PIU AMP. O ^ i END(0- K ENI CO- UP TO SPEED (l ) - WC (I) DBSfl) DFfI) DBfe(l) WREN(I) DBTfl) LPBO(I) DBSfO- LPei(0 - • selCO - PAR(l) - TIM(ll - 12 PIN AMP. 5T REV Ck(|> 0B9(0 - - LPB2(I) - -J « |MSER~ JUMPERS P.W e CAki SO THAT PIN A AND BE USED Panel Indicator Drivers 6-17 BS-D-TCOl-0-12 oo 7 6 5 22 PIN AMPHENa wo 2 3* DTBIO DTBII (FEMALEKMALQ USRO A A INDICATOR BRACKET • C USRI USR2 B C B C •- MRO D MRI E D E D E \ FRO F F F 1 H FRI • J FR2 K FR3 H J K K L L « * INSERT JUMPERS \H W023'S SO PINS A AND B CAN BE USED • L ENI U M M US N N • WC N »*49I0 AND 4904'S WITH TRANSISTORS REPLACED BY A JUMPER FROM BASE TO COLLECTOR H J P 12 PIN DTB12 1 12 PIN AMPHENOL CONNECTOR W023* AMPHENOL CONNECTOR W023* DTBZ3 (FEMAL5IWALE) INDICATOR BRACJ(ET '^^904** ' © © © © 0 © © © © © 2 (FEMALE) iMALQ ^1CATQR_ BRACK'' K 4904 *^ ©- DBI ' ee- ' ' LPBO C3 -©- ' LPB2 e- , LPB3 ee- ' -e- DBS LPB5 ' -0- e- ' ' I P ' BM P R R 1 *** -15 JUMPERED TOGETHER AND TIED TO -15 ON SIDE PANEL WITH "fASTON" TAB CONNECTOR 3 4910 ** A c3 B 22 PIN AMPHENOL CONNECTOR (FEMALQWALS _INDICATgR BRACKET W02S» CONNECTOR 4 i RC R S S S D T T T F U U C V V I w w • U • V X X Y Y 2 2 © © © © © © W023 WRTM RDMK DTC27 , INDICATOR B ' -e- RWB2 eNORMAL e-e- RDMK a. 8 7 6 5 t 4 3 2 1 Marntenance Control Panel 6-19 BS-D-TCOl-0-13 STAIUS A CLEAR OBAC8 '{» XOR STATUS A- WOZI DTF02 lOP I I0P2 I0P4j uozi DTA02 Error Flags BS-D-TC01 -0-14 6-21 Rev, E 1 W0E3 ^ DT^£' TEST ^ f^-^^f^^ wim w2m 0^oB w3(i) W4I1) f f W5ti) well f^-f wtm) warn f lpb^i f mm f f f TEST CONN *3 ^ s.L— ^ DTE24 V ^ fJ 9~ I TkVBf- 0COMP RWB0-Z LPB PB 0^DB C25D T/M DF(0 F3IP ENABLE W023 DTF20V__ •B 0TE24 ( .A 'C r TEST C0NN*1 C-SYNCH r f f Ctl!301). MK MK MK BLK ST DATA BLK f f MK END MK BLK END r ST r CK0I1) DATA r CKHD r r RATE U+Mdl DY(1) f f W-INH(I) DATA SYNCHdl ,r . «B «C TEST « ? CONN 3 C (1000) l^DF C0-3 LPB^ aWB DTB0-5 SHIFT LEFT ROTATE SB/RWB MK TO D22 D- UTC29 G682 0682 DTC16 READ T TRK 11) MKTRK > V " RWB i (I READ , Dt > U /\ V RWB l(() RWB 0(1) RWB 0(0 CK0(l) DTC21 DTC2<i I < CK 0(1) G882 DTC22 1^882 ~l G882 DTC17 RWB 2(1) M ENABLE RWB HO RWB 0(i RWB2(() WREN (0 N W032 DT CI9 C »CF «CJ «CH • DP »CK 'DM 'DN •DL DJ •DF \ •DH ^ •DE DT DI9 ' TO !-' I HS SHLD BLU WHT T U 55 R/W AMPS, SP GEN, TEST CONN. BS-D-TCOl-0-15 6-23 Rev. E PDP-8 LCX3IC SYMBOLS Negative pulse Positive going pulse Negative level Ground level Flow - 15v Load clamped at - 3v PNP Transistor inverter 2.- 1 . 2. 3. nA emitter base collector And gate 11 V 1 Or gate Nand gate A Diode-capacitor-diode gate Flip-flop 3.-*. BO PA Inverting bus driver Pulse amplifier 2. 3. level input trigger input pulse output 1. 2. 3. set to one Set to zero direct clear 1 . mm DIGITAL EQUIPMENT CORPORATION • MAYNARD. MASSACHUSETTS Printed in U.S.A.
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