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XX-4ADE4-FC

July 1977

24 pages

Original

2.3MB

Document:	MSC3102 PDP8semiMem Jul76
Order Number:	XX-4ADE4-FC
Revision:
Pages:	24
Original Filename:	http://svn.so-much-stuff.com/svn/trunk/Eagle/projects/32k-Omnibus/MSC3102_PDP8semiMem_Jul76.pdf

OCR Text

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MAINTENANCE MANUAL
MONOSTORE

V/PLANAR

PDP-8 ADD-IN
SEMICONDUCTOR

MEMORY

SYSTEM

MSC 3102

TeT AT 7

: AJBICID .EVFiGiH,

14 Inverness Drive East, Englewood, Colorado 80112 (303) 770-7400

REV | ECO

DESCRIPTION

DATE

fee PREVESED
ee

J.W

"Information contained in this manual is disclosed in confidence
and may not be duplicated in full or in part by any person without
prior
written approval of Monolithic Systems Corporation.
Its sole purpose is
to provide the user with adequately detailed documentation so as to efficiently install, operate, maintain, and order spare parts for the system
supplied.
The use of this document for all other purposes is specifically
prohibited."
|

Systems

14 Inverness
Englewood,

Corporation

Drive East

Colorado,

80110

303-770-7400
THIS DOCUMENT IS PROPRIETARY AND SHALL NOT BE FORWARDED TO ANY NON-COMP
ANY
INDIVIDUALS WITHOUT THE WRITTEN CONSENT OF MONOLITHIC SYSTEMS
CORP.

Reve

REV
STATUS

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CYS MONOLITHIC SYSTEMS CORP.

SPECIFIED DIMENSIONS
UNLESS

OFFICES OR

OTHERWISE

ARE IN INCHES. TOLERANCES ARE:

TE NANCE MANUAL
NO TORE V/PLANAR
MONOS
P DP-8 ADD-IN
MSC 3102
ICODE IDENT NO DWG NO.
MA IN

MATERIAL

APPROVED

i
1

J. Waldinger!

SIZE

A |}5151

SCALE

REV

100-0023-000

SHEET

MONOSTORE

V/PLANAR

PDP-8

Add-In

SEMICONDUCTOR

MEMORY

SYSTEM

CONTENTS

SECTION

1.1
1.2
1.3
1.4

INTRODUCTION
GENERAL DESCRIPTION

MODES OF OPERATION ©
SYSTEM SPECIFICATIONS

SECTION

2.1
2.2
2.3
2.4

INTRODUCTION
UNPACKING AND INSPECTION
INSTALLING MEMORY SYSTEM
I/O SIGNALS

SECTION III
3.1
<3.2

GENERAL

DESCRIPTION

INSTALLATION

DATA CHANNEL
TIMING CIRCUITRY

SECTION

4.1
4.2
4.3

INTRODUCTION
PREVENTIVE MAINTENANCE
TROUBLESHOOTING

SECTION

DRAWINGS

5.1
5.2
5.3

PARTS

LIST

ASSEMBLY
SCHEMATIC

MAINTENANCE

CY»
MSF—1005

OO
NAA

THEORY OF OPERATION

- ADDRESS CHANNEL

3.4
3.5

eet

& OPERATION

_INTRODUCTION.© +
|
i
MEMORY LOCATION PROGRAMMINGae

3.3

3
4
4
4

AND

ae
yy

eS
2

TROUBLESHOOTING

SIZE |CODE IDENT NO.|

DWG NO.
100-0023-000

SECTION

GENERAL

DESCRIPTION

INTRODUCTION

This manual provides information for installing, operating,
and maintaining
the MONOSTORE V/Planar PDP-8 add-in memory systems.
The material is arranged

- in

five

sections

Section

follows:

General

This section provides
A general description

Section

Description
the
and

Installation

Instructions

are

memory

system.

Section

III

provided

scope,
a list

and

Operation

for

unpacking,

inspecting

and

of the memory system is provided

' diagrto
am
aid in understanding

and arrangement of
specifications are

the manual.
also given.

installing

Maintenance

along with a timing

the system
and to support

troubleshooting.

and Troubleshooting

This section gives recommended general maintenance procedures and
shooting information for diagnosing and locating a malfunction.

Section

This

Drawings

section

contains

schematics,

assembly,

and

system.

parts

list

for

trouble-

the memory

SiZE_] CODE IDENT NO. DWG NO.
100-0023-000

MSF—1005

the

Theory of Operation

.° An overall description

Section

contents,
of system

GENERAL

DESCRIPTION

The MONOSTORE V/Planar PDP-8 Add-In Memory System, P/N
303-0112-000,
consists of a single planar 8Kx12 memory assembly.
All electronics and
semiconductor static N-channel memory storage element
s are contained on

a single

printed

circuit

board.

All signal interface is made through the DEC omMNisus™
Assembly.
Data
interfacing is provided by 12 bidirectional data bits.
Addressing any
one of the 8192 words is provided by 13 binary address
bits, together
with command and control information to Gefine the memory
mode required.
The

memory

system uses

The

maximum

capacity

also be configured

the

+5V power

available

of the board is 8192. words

in 1024 word

increments

the

OMNIBUS

by 12 bits.

assembly.
The system

from 1024 up to and including

words.

8192

can

MODES OF OPERATION

Read

Cycle

1.2

Transfers
OMNIBUS.

—™ sec

data from memory
.
&

to the

Read/Write Cycle - 1.4 “sec
;
_fransfers data from memory tothe.
OMNIBUS

during

then writes
the OMNIBUS

SYSTEM

MD DIRL=1

and

data into memory from
during MD DIRL=0.

nr “apes

—

SPECIFICATIONS

Characteristic

Specification

Storage

1024

Capacity

words

8192 words
(1024 word

Cycle

x 12 bits
x 12 bits
increments)

Time

Read
Read/Write

DEC

;

and OMNIBUS

are

trademarks

of Digital

SIZE |CODE IDENT NO.|

‘

sec

Equipment Corporation.

DWG NO. —

1.4

System

Specifications

continued

Characteristic
Read

Access

Time

Specification

600

Input Power
Operating

nsec

+5V- =3.0 "amps

Environment

Temperature

Relative

0°C

Humidity

Physical Dimensions
Height
_
¢
Depth

90%

:
'

Width

+50°C

maximum without
condensation.

8.44
0.5

inches
inches

10.44

inches

SIZE |CODE IDENT NO.| DWG NO.

NTN
oxy
MSF—1005

SCALE
A

100--0023~000

SECTION

INSTALLATION

2.1

& OPERATION

INTRODUCTION

This section contains information for installation
memory system.
2.2

UNPACKING

AND

and operation of the

INSPECTION

Carefully remove the memory system from the
shipping
any packing material from the assembly.
Inspect the
or loose connections.

2.3

INSTALLING
Remove
system

system

MEMORY

container ; Remove
system for any damage

SYSTEM

the external top cover from
into the OMNIBUS Assembly.

is now ready

for use.

the PDP-8 computer.
Insert the memory
Reassemble the top cover.
The memory

| SIZE |CODE IDENT NO.| DWG NO.

100~0023~<000

MSF—1005

Ww 4

1/0 SIGNALS

7177reprhieee

MASL

IROL

{1/0 PAUSE

TP1H

EB j] MAIL

[oo

MA1OL

MDSL

TP4H

| -

STROBE L

MD11L

be)

DATA

MODE

F SET L
PULSE

>3 °o

3 E

La
g

XFER

H | INITIALIZE

MD7L

H| LINK

&e e :B

ardt

(8
8

DATA

L|DATA

sl
Th

DATA

OL | RETURN

DATA

1L | WRITE

OK H | DATA

ROM
ADDRESS
3L

CODE IDENT NO.| DWG NO.

100-0023-000

MSF—1005

pba

SIZE

DOs
pan| POWER

(8
E12
8]
gf
::

B i

00
KE
CONTROL

Hf
: q5

;

TS3L

INT ROST L

DH
a

Jab

]

MA7L

See

ee :
SER

qd
ale
Bs
ea t

nr
B

TS1L

> °o t

icles

MD1OL

~15V

5 E

a2
a5V

all
A

LINK

SECTION
THEORY

3.1

III

OF OPERATION

INTRODUCTION

This

section

describes

the

overall

organization

and

MONOSTORE V/Planar PDP-8 Add-in Semiconductor Memory
has a maximum capacity of 8192 words of 12 Bits.

This

section

is organized

into

Description
Memory

Location

Address

Channel

Data

3.2

the following major

Circuitry

MEMORY

LOCATION

of the

System.

The

parts:

Programming

3.2
.

3.3

3.4
3.5

PROGRAMMING

The memory location is Programmed via wire jumpers
on the board.
. €an program the memory to any location according
to the following

system

_ Paragraph -

Channel

Timing

operation

SPATR
ING

O=HI LEVEL’
EMA

4Kx8K
PROGRAM

BOARD

The user
table:

5PROGRA:M

mores [O
172 T
|e] > | camcry [als
mx | efesf»
lo
| ]
#
[ifs

« (ele [op] = Te
nd ee
= lebp [|= (if
= fofef sl=)ah
=
toteb Te=l(eh
«otf
=
ah
PETE see
BK

we@

WK .

Ds
y

”ie

MSF—1005

100~0023~a00

3.2

WNemory

Location

Programming

continued

...

The computer generated addresses EMAO, EMAl, and EMA2 are Gecoded
in blocks
Of 4K with a maximm of two 4K blocks of memory on a single
board.
If the
generated
initiated

3.3

ADDRESS

addresses are within the programmed range a memory cycle
will be
by MEM START L.
This circuitry is shown on Sheet 1 of the schematic.

CHANNEL

When

a memory cycle is initiated

MAOL

~—»

MAIL

MA2L ->
complete

_MAOL,

is used

the information

follows:

MAIIL - These
memory array.

address

MAIL

- These

address

bits

are

on the address

buffered

decoded

in order

lines
to drive

in conjunction

with

the

EMA2

to generate the 1K, 2K...8K cenable pulses required by the memory
elements.
The cenable pulse then enables only one row of memory elements
at any one time thereby preventing interaction of data bits.
The

3.4

address

channel

and

cenable

circuits

are

shown

Sheet

1 of

the

schematic.

DATA CHANNEL
When

a memory

cycle,

READ,

is initiated,

the information

previously

the memory elements is accessed and transmitted onto the MDOL
for use by the computer for as long as MD DIR'L = 1.

—»

stored in

MD1I1L lines

When a memory cycle, READ/WRITE, is initiated the READ cycle is repeated
until
MD DIRL= 0.
At that time the WRITE phase of the memory cycle is performed
and the information on the MDOL —> MD11L lines is buffered and stored in
the
memory elements at the same address as the first phase READ portion of the
cycle.

The

3.5

;

data

TIMING

channel

circuit

is shown

Sheet

2 of

MEM

schematic.

CIRCUITRY

All internal and I/0 pulses or signals, except
are generated from timing pulses TS1L —-» TS4L,
OMNIBUS interface.
The

the

START

READ/WRITE

L signal

cycle

fis received

depending

the storage element “write" pulse,
TP1H—»TP3H, received at the

by the memory

upon whether

system

and

The timing pulses and signals at the GMNIBUS fnterface are
to the following timing diagram.
The miscellaneous timing
is shown on Sheets 1 and 2 of the schematic.
;

| SIZE |CODE IDENT NO.} DWG NO.
A

MSF—1005

generates

MD DIR L is a "1" or

| |

a READ or

"1/0" respectively.

generated according
and control circuitry

:
100~0023~000

- PpP-g
nsec

200 200
{
t

1/0

‘

TS1

;

TPl

300
{

{

;
.

wle-

400

500
1

600
!

)

700
)

fob

ete

1000
{

“4

900
1

800

1.1

1.2

1.31.4

;

Sec

1.5

1.6

‘

{

TS2

:
i
!

TP2
TS3

TP3

TSs4

ae
mi

{

H
t
:
:
4

! NOT WALI
{
{
'
I
i
'
48

MDXXWR

i NOT

: Eo

MDXX,,

MD DIR,

MD DIR...

‘

Ve:

{

i
‘

mre

' VALID
!
\
i
i

{

VALI

!
'

{

{
{

{

a
e 2
{

ee
{

{

ITE, DATA VALID!
cn,

{

'
I

{

—

{

['TP2|MovEs TO THIS IIME:FOR A RD/WR CYCLE
y

{

t
‘

{

VALID

SIZE. |CODE IDENT NO.| DWG NO.

| \ MSF—1005

DURING

’

fS3

& €S4 ¥OR

®D/RR

CYCLE

PDP-8
Oi

st MSF—1005

Bee

“

#00

’

{

‘

____y

700 800
!

900 1000
|
i

’

A,l
t

1.21.3. 1,4
i
1
i

1.5
1
’

1,6
‘

SECTION

MAINTENANCE AND TROUBLESHOOTING

4.1

INTRODUCTION
This section presents troubleshooting instructions for ease of trouble
location.
Further localization of the trouble is to be found by means

of
the maintenance drawings in SectionV. The theory of operation in Section III
should be read and understood, along with a detailed review of the schematics

in Section

4.2

V in order

to make

effective

use

of this

section.

~ PREVENTIVE MAINTENANCE
4.2.1

Visual

Inspection

This inspection inclodes checking for loose programming
components, and discoloration of parts.
The inspection
performed with a minimum of prying or moving of parts.
422.2

Cleaning

should

be limited

Never use any abrasive on
connectors.
Low pressure

to removal

of excess

dust

or particles.

any part of the gold fingers on the edge
compressed air can be used for removing

_. @ust or dirt and an aerosol
to do the gold contacts. 4.2.3

wires,
should

cleaner can.1.be used,

with

light

brushing,

DC Voltages

The

+5V DC voltage

should

be maintained

at:

+5V
+ 5%

4.3

TROUBLESHOOTING
To facilitate écouhyesneeking jrhe following information,
can be used to isolate the proglem to a particular area.

schematics

should be used

Effect
Single
all

bit

to determine

the exact

Cause

failure,

Data

component

and effect,
there on the

that

receiver/driver/read

is at fault.

addresses.

Complete word failure,
all addresses.

DC voltage/WR

SIZE |CODE IDENT NO.| DWG NO.

MSF—1005

cause
From

pulse/strobe

pulse.

Troubleshooting

continued

Effect

Single
single

...
Cause

bit failure,
address.

Memory

Four bit failure,
all addresses

Read

Complete

CENABLE

a 1K

Complete
word

word

failure,

section.

element

driver/CEN

jumpers/address
MAIL.

or major part of

failure,

all

Non-retention

Address

data

I/O driver.

programming

circuit

for MAOL

receiver/address

buffer.

addresses
data.

DC voltage.

SIZE |CODE IDENT NO.] DWG NO.
100-0023~000
>
a

MSF—1005

and

4.4 TEST PROGRAMS
To provide

reliable memory operation

locations,

it is necessary

system

to exercise

failed bits or

the memory system with memory

tests.

The DEC memory

recommended
Three

and to locate

tests which are available

for testing

as standard

are

the MSC Monostore V/PDP-8 memory system.

tests are used for field maintenance

for preventative

maintenance

failures.

tests

These

test software

purposes

and should

be run periodically

and also used to locate memory

are as follows:

1.
2.
_
3.

PDP-8E EXTENDER MEMORY ADDRESS TEST, MAIN DEC-8E-DIFB-D.
PDP-8E EXTENDED MEMORY DATA AND CHECKERBOARD TEST, MAIN
DEC-08-DHKMA-AD.
MEMORY ADDRESS TEST, MAIN DEC-8E-DIEC-D.

Normal

trouble-shooting

procedures

are applied

in using the memory

tests.

First,

the problem

is isolated

to a particular memory

determined by the fact that the memory

has been assigned

(stack) identification on the memory bus.

If the board

the unit represents

ane field.

If the board

two fields.

are

8 total

fields

numbered

4K with

the"0"

field

Each

field

There

represents

By looking at the table under

section.

thru

representing

3.2 and checking

a certain

"7".

the first 4K.

the programming

wires on

[SHEET yu
|

field

it represents

100-0023-000

MSF—1005

is a 4K board,

is an 8K board,
"0"

This

the board,

the memory can be identified

as to the field

to which

it is

assigned.

In many cases,
defective

of maintenance

failures

Element

each element

represents

then

element

locating

the element

print out is shown

for removal

of the

would be to isolate a defective

failures

of one particular

by examining

board.

because

bit.

the test program

physically on the memory

to illustrate

component.

because of the number of elements

are Single bit oriented

1024 locations

is located

call

by another.

are the most probable

on the board.

A failed

program will

memory and replacement

The next level
Element

the maintenance

print out and
A typical

the method.

PDP-8E EXT MEM DATA & CHKBD
SETUP SR & ‘CONT
’ 4 FIELDS IN THIS SYSTEM.
FIELDS SEL'D ARE 7 6 5
PROG WILL RELOCATE
PR LOC FAIL ADR GOOD BAD PATTERN
01662
74000
0000 2000 ALL O - NC
01662
74000
0000 2000 ALL O - 2c.
01662
74001
0000 2000 ALL O - NC
01662
74001
0000 2000 ALL O - 2c
OX

The print out shows the failed addresses
and the bad bit-pattern.

(FAIL ADR), the good bit pattern

The print out is octal.

the field

by the left most digit of the address

as field

This corresponds

V/PDP-8 board.

The address

identifies

and can be read directly

to the 5K thru 8K marked

on the Monos tore

Now we know the field and must locate the particular

row and then the bit.

This will

then identify the element at fault.

SIZE |CODE IDENT NO.| OWG NO.

100-0023-000
SHEET |5
MSF—1005

1K
The

particular

row is identified

by the two upper bits of the next octal

digit just to be right of the left most digit.

The following

OCTAL

K_ROW LOWER

K ROW UPPER

1K
1K
2K
2k

5k
5K
6K
6K
7K
7K
8K
BK

BINARY

0
1
2
3
4
5
6
7

00
00
01
01
10
10
11
i

oO}
1
0
1
0
1
0
4

3K
4k
4k

code applies:

The row is the. 7K because ee the 4 Bene. out and the upper field as

previously identified.

The remainder of the address
bad.

tells us that the first two locations are

Now we must find the bit to complete

pattern

is all zeros

and we see that we have an octal

010.

Bits are identified

bad.

The complete

it to one element

Other failures

2 which

as 0 thru 11 from right to left.

location

or 7K row depending

the identification.

is the board assigned

upon the field assignment

to field

and bit 10.

to be replaced.

would

be approached

in a similar manner.

SIZE |CODE IDENT NO.| DWG NO.

eyo teee ae

MSF—1005

The test

gives an

Bit 10 is
7, the 3K

This

narrows

DRAWINGS

PARTS

LIST

303-0112-000

ASSEMBLY

303-0112-000

SCHEMATIC

305-0112-—000

SIZE

MSF——-1005

| CODE IDENT NO.}

DWG

NO.

100~0023<000

hal
REVISIONS
|

DESCRIPTION

DATE

[tieslt itine ncien ieee ag

yaiets pTSe

1
6
|
8-26-76] OM

ADDED NEW MSC I.-C. PARTS NOS.

3-4-76

’

|p | ITEMS 23 &24 REVISED PER ECO 0580
[E | REVISED PER ECO 0608
|

fa-9-77 | BAW
2/24/77| Be S

REVISED PER EC) 0640
REPLACED SHEET 4 PER ECO 0681

CHANGED PER ECO 0816

ALL EQUIPMENT

vat ten,

REVISION

LEVELS ARE

THIS DOCUMENT IS PROPRIETARY AND SHALL NOT
INDIVIDUALS WITHOUT THE WRITTEN CONSENT OF

"C",

BE FORWARDED TO ANY NON-COMPANY
MONOLITHIC SYSTEMS CORP.

mnrt m m +
iz

UNLESS OTHERWISE
SPECIFIED DIMENSIONS
ARE IN INCHES TOLERANCES FRACTIONS
DECIMALS ANGLES
MATERIAL

MO-V

Li]
SAF
LPPROVED

MSF - 1004

APPROVED

AGF

<i>

MSC 3102
PL/PDP8 ASSEMBLY

OFFICES OR

$
OTY/DASH NO.
| 1 [ood 001]

LIST OF MATERIAL
DESCRIPTION

PART NO.

MATERIAL OR NOTE

ASIN
SEULTW

304-0112-001

P.C. BOARD

||
tsts| 10-0605-001
pt dss

1.C. SN7475

210-0200-001

1.C. SN7408

Lie lie: ies: 2 10- 0103-0 02

I.C. SN74H04

Ped

— e oO e

10 | 10
Part

210- 1104-00:

i al 2: 210-0100-002

U7,9,10,12,13,18

’;
og

U8,15,22,24,25,26,27,28, 30,35

I.C. SN74H00

U11,31.°—

merry

210-0105-002

TC. SN74H10

Y14,19,21

oth

210-0200--002

I.C. SN74H08

Y16,20

eel

210-0308-001

I.C. SN7438

U17,33,34

ie ae

210-0914-001

I.C. SN74155

U23.

de is

Shee

bea

SSIs
Td]

210-0504-001

210-1003-916
| [fast -| 210-1003-016

090-zT10-eGE
&

1.C. SN74123

100-147

0
ia) nm
eet

1.C.

317-0058-001 .

MODIFICATION

HEADER

16 PIN
INSTRL

ee
>
ff
Pr
|;
|W
>

FAIRCHILD

[os] as| 201-0018-001

CAP. 6.84F,10V

C3-C27

falar

701-0001-003

CAP.

C28-58

201-0006-046

CAP 100pf

FAIRCHILD

—fos)
~

.4F,59V

ENE

U100-U195

ae]

208-0023-001

U29

MEMORY ELEMENT
—

|
SPECIFICATION

oO:NO
(vo
~
MN
hor
—Rho]

OTY/DASH NO.
| | loo2}o07,

PART NO.

LIST OF MATERIAL
DESCRIPTION

MATERIAL OR NOTE

SPECIFICATION

ITEM

| NO

SLOL—4ASWN

nnn hee
|
{|14}24]208-060-001

pean
esa

SINT:
rear
|

P|
2 |2]208-0057-001

poms

| |r

SEIS
[as |

ee
ee
ee Pe
P= ght + 208-0011-002
prs
|
Tw
2 2
ee
eee
ee eee
ee
ee
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a
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a 22
ee
ee
ees
ee
2
Mal
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ees
WR
od
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