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AA-HD92A-TK

December 1987

533 pages

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Document:	VAXmate Technical Reference Manual Volume 1 Feb1987
Order Number:	AA-HD92A-TK
Revision:
Pages:	533
Original Filename:	http://bitsavers.org/pdf/dec/vaxmate/AA-HD92A-TK_VAXmate_Technical_Reference_Manual_Volume_1_Feb1987.pdf

OCR Text

AA-HD92A-TK

Technical
Reference Manual
Volume 1
LIBRARY
DIGITAL EQUIPMENT CORP.

DECLIT
I;,;
CF\aSS
HD92A

swore

mate

Technical
Reference Manual
Volume 1

First Printing, February 1987

© Digital Equipment Corporation 1987. All Rights Reserved.
The material in this document is for informational purposes and is subject to change
without notice; it should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility for any errors
that may appear in this document.
Digital Equipment Corporation assumes no responsibility for the use or reliability of its
software on equipment that is not supplied by Digital.
MS-DOS, MS-WINDOWS, and MS-NET are trademarks of Microsoft Corporation.
Topview is a trademark ofInternational Business Corporation.
Motorola is a registered trademark of Motorola, Inc.
IBM PC AT is a trademark of International Business Machines Corporation.
The following are trademarks of Digital Equipment Corporation.

mamaala

DEC
DECmate
DEC net
D ECsystem -10
DECSYSTEM-20
DECUS
DECwriter
DIBOL
EduSystem

Printed in U.S.A.

lAS

MASSBUS
MicroPDP
MicroVAX
MINC-II
OMNIBUS
OS/8
PDP
PDT
P/OS

Professional
Rainbow
RSTS
RSX
ThinWire
VAX
VAXmate
VMS
VT

Work Processor

Contents

Preface . ...

xxxiii

VOLUME 1
Chapter 1 VAXmate Workstation Overview.
Base System . . . . .
Optional Components . . . . . . . . . . .

Chapter 2 VAXmate Microprocessor.
Overview . . . . . . . . . . . . . . . . .
Real Address Mode . . . . . . . .
Protected Virtual Address Mode.
Coprocessor. . . . . . . . . . . .
Additional Sources of Information . .
Memory Map . . . . . . . . .
Input/Output Address Map .
Interrupt Vector Map . . . .
Bus Timing and Structure. .
Expansion Box Technical Specifications
Expansion Box Operating Ranges .

Chapter 3 Interrupt Controllers
Overview . . . . . . . . . . . . . . .
Additional Source of Information.
Read/Write Control . . . . . . . .

1-1
1-1

1-3
2-1
2-1
2-1
2-1
2-2
2-2
2-3
2-4
2-6
2-9

2-10
2-10

3-1
3-1
3-3

3-3

Contents iii

Initialization Command Words . . . . . . . . . . . . . . . . . .
Initialization Command Word 1 . . . . . . . . . . . . . . .
Initialization Command Word 2 .....
Initialization Command Word 3 . . . . . . . . . . . . . . .
ICW3 (Master) . . . . . . . . . . . . • . . . . . . . . .
ICW3 (Slave) . . . . . . . . . . . . . . . . . . . . . . .
Initialization Command Word 4 . . . . . . . . . . . . . . .
Operation Command Words . . . .
Operation Command Word 1.
Operation Command Word 2.
Priority Rotation. . . . . . . .
Operation Command Word 3 .
Interrupt Request and In-Service Registers
Interrupt Request Register . .
In-Service Register .
Poll Command . . . . . .
Poll Data Register .
Interrupt Sequence. . . . . .
Programming Example . . . .
Constant Values and Data Structures. . . .
Initialization Data . . . . . . . . . . . . . . . . . . . . . . .
Initializing the Peripheral Interrupt Controller . . . . .
Issuing an End-of-Interrupt Command . . . . . . . . . .
Masking Interrupts . . . . .
. . . . . . . . . .

Chapter 4 DMA Controller... .
Overview . . . . . . . . . . . . . .
Additional Source of Information.
Operation. . . .
. ..... .
Idle Cycle . . . . . . . . . . .
Active Cycle . . . . . . . . .
Single Transfer Mode. .
Block Transfer Mode . .
Demand Transfer Mode
Cascade Mode . . . . .
Data Transfers. . . . .
Auto-Initialize ... .
Priority . . . . . . . .
Address Generation.
iv Contents

3-5
3-7
3-8

3-9
3-9
3-9
3-10
3-11
3-11

3-12
3-13
3-15

3-16
3-16
3-16
3-17

3-17
3-18

3-21
3-22
3-22
3-24
3-26
3-26
4-1
4-1
4-2
4-2
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-5
4-5

Registers. . . . . . . . . . . . . . . . . . .
Base and Current Address Register.
Base and Current Word Register
Command Register .. . . . . .
Write Single Mask Bit.
Write All Mask Bits .
Mode Register . .
Request Register. . .
Status Register. . . .
Temporary Register .
Programming Example
Constant Values . . .
Data Structures ...
Initializing the DMA Controller
Opening a DMA Channel. . . . .
Preparing a Channel for Data Transfer .
Disabling a DMA Channel . . . . . . . .

Chapter 5 Real-Time Clock and CMOS RAM.
Overview . . . . . . . . . . . . . . .
Additional Source of Information.
Battery-Backup Considerations. .
Addressing the Real-Time Clock.
Real-Time Clock Registers
Register A.
Register B.
Register C.
Register 0
Real-Time Clock Data Registers.
Alarms . . . .
Update Cycle . . . . . . . . .
Interrupts . . . . . . . . . . .
Update-Ended Interrupt
Alarm Interrupt ..
Programming Example
Constant Values . .
Data Structures ..
Reading the Registers and RAM.
Writing the Registers and RAM.
Calculating the Checksum . . .
Converting Binary-Coded Data.
Reading the Date. . . . . . . . .

4-7
4-7
4-8

4-9
4-11
4-11
4-12
4-13
4-14

4-14
4-15
4-15
4-17
4-18

4-19
4-20
4-22
5-1
5-1

5-2
5-2
5-2
5:3
5-4
5-6
5-8
5-9
5-10
5-12
5-13
5-14
5-14
5-14
5-15
5-16
5-18
5-20

5-21
5-22
5-23
5-24

Contents v

Reading the Time . . . .
Displaying the Date . . .
Displaying the Time. . .
Displaying the Diskette Drive Type .
Displaying the Hard Disk Type .
Handling the Clock Interrupts . .
Interpreting the RAM Contents .
Initializing the Real-Time Clock.
Restoring the Interrupt Vectors.
Real-Time Clock Example . . . .

Chapter 6 Three-Channel Counter and Speaker
Overview. . . . . . . . . . . . . . . . .
. .....
Additional Source of Information. . .
. . . . . .
Block Diagram . . . .
. . . . . .
Counter Description . . . . . . . . . . . .
Mode Definitions . . . . . . . . . . . . . .
Mode 0 (Interrupt on Terminal Count) . . . . .
Initializing Mode 0 . . . . . . . . . . . . . .
Mode 0 Cycle. . . . . . . . . . . . . . . . . .
Mode 1 (Hardware Retriggerable One-Shot) . .
Initializing Mode 1 .
Mode 1 Cycle. . . . .
Mode 2 (Rate Generator)
Initializing Mode 2 .
Mode 2 Cycle. . . .. . . . . . . . . . . . . .
. Mode 3 (Square Wave Mode). . . . .
Initializing Mode 3 . . . . . . .. . . . . .
Mode 3 Cycle. . . . . . . . . . .. . . . . .
Mode 4 (Software Triggered Strobe).
Initializing Mode 4 . . . . . . . .
Mode 4 Cycle. . . . . . . . . . . .
. . . . . . . .
Mode 5 (Hardware Triggered Strobe). . . . . . . . .
Initializing Mode 5 .
. . . . . . . .
Mode 5 Cycle. . . . . .
. . . . . . . . .
Registers. . . . . . . . . . . .
. . . . . . . . .
System Register . . . . . .
. . . . . . . . . . • . .
Control Word Register . . . . . . . . . . . . . . . . . . . . . .
Counter-Latch Command (Control Word Register). .
Read-Back Command (Control Word Register) . .
Status Response (Read-back Command) . . . . . . . .
vi

Contents

5-25
5-26
5-27
5-28
5-29
5-30
5-32
5-34
5-35
5-36
6-1
6-1
6-1
6-2
6-2
6-3
6-4
6-4
6-4
6-4
6-4
6-4
6-5
6-5
6-5
6-5
6-6
6-6
6-6
6-6
6-7
6-7
6-7
6-7
6-8
6-9
6-11
6-12
6-13
6-14

Programming Example
Constant Values . .
Writing a Counter.
Making a Bell Sound
Counter and Speaker Example.

6-16
6-16
6-18
6-18
6-20

Chapter 7 Video Controller . ....

7-1
7-1
7-1
7-2
7-2
7-2
7-3
7-4
7-5
7-6
7-6
7-7
7-8
7-9
7-10
7-10
7-18
7-22
7-23
7-25
7-25
7-25
7-28
7-28
7-29
7-29
7-30
7-30
7-31
7-31
7-32
7-33
7-33
7-34
7-34
7-34

Introduction. . . . . . . . . . . . . .
Industry-Standard Text and Graphics Features.
Enhancements to Industry-Standard Features
Industry-Standard Features Not Available
Extra Features . . . . . . . . .
Block Diagram . . . . . . . . . . . .
Additional Sources of Information .
Video Modes . . . . . . . . . .
Text Modes . . . . . . . . . . . . . .
Character Buffer Format . . . .
Character Position to Memory Location Mapping
Programmable Cursor . . . . . . . . . . . . . . . .
Programmable Character Generator (Font RAM) .
Graphics Mode . . . . . . . . . . . . .
Mapping the Display to Address
Video Look-Up Table . . . . .
Video System Registers . . . .
Special Purpose Register.
CRTC Registers . .
Index Register.
Data Register
Register RO
Register Rl
Register R2
Register R3
Register R4
Register R5
Register R6
Register R7
Register R8
Register R9
Register RIO
Register Rll
Register R12
Register R13

Contents vii

Register R14
Register R15
Register R16
Register R17
Status Register A. .
Status Register B . . . .
Write Data Register. .
Color Select Register
Control Register A .
Control Register B. .
Monitor Interface . . . .
Monitor Specification Summary.
Programming Example . . . . . . . . .

Chapter 8 Keyboard-Interface Controller and Keyboard.
Introduction . . . . . . . . . . . . . . .
Keyboard-Interface Controller . . . . . . . . . . .
Physical Interface to the CPU . . . . . .
Physical Interface to the Keyboard . .
Logical Interface. . . . . . . . . . . . . .
Control Functions . . . . . . . . . . . . .
Keyboard-Interface Controller Diagnostics.
Keyboard-Interface Controller Registers
Data Register. . . .
Command Register
Status Register ...
Command Register
Read Command Byte.
Write Command Byte.
Self-Test . . . . . .
Interface Test . . .
Disable Keyboard.
Enable Keyboard .
Read Port 1. . . . .
Read Port 1. . . . .
Read Port 2. . . . .
Write Port 2 . . . .
Read Test Inputs .
Write Status Register.
Pulse Output Port. . .
Keyboard-Interface Controller Error Handling ..
viii Contents

7-35
7-35
7-36
7-36
7-37
7-38
7-39
7-39
7-41
7-43
7-44
7-44

7-45
8-1
8-1
8-1
8-1
8-2
8-2
8-3

8-4
8-5
8-5
8-5
8-6
8-9
8-10
8-10
8-12
8-12
8-12
8-12
8-12
8-12
8-13
8-13
8-13
8-13
8-13
8-14

LK250 Keyboard. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LK250 Keyboard Command Codes . . . . . . . . . . . . . . .
Invalid Commands . . . . . . . . . . . . . . . . . . . . . .
Request Keyboard ID. . . . . . . . . . . . . . . . . . . . .
Enter DIGITAL Extended Scan Code Mode. . . . . . . .
Exit DIGITAL Extended Scan Code Mode. . . . . . . .
Set Keyboard LED. . . . . . . . . . . . . . . . . . . . . .
Reset Keyboard LED. . . . . . . . . . . . . . . . . . . . .
Set Keyclick Volume. . . . . . . . . . . . . . . . . . . . .
Enable Autorepeat. . . . . . . . . . . . . . . . . . . . . . .
DisableAutorepeat . . . . . . . . . . . . . . . . . . . . . .
Keyboard Mode Lock . . . . . . . . . . . . . . . . . . . . .
Keyboard Mode Unlock. . . . . . . . . . . . . . . . . . . .
Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . .
LEDs On/Off. . . . . . . . . . . . . . . . . . . . . . . . . .
Echo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Autorepeat Delay and Rate . . . . . . . . . . . . . . .
Enable Key Scanning. . . . . . . . . . . . . . . . . . . . .
Disable Key Scanning and Restore to Defaults . . . . . .
Restore To Defaults. . . . . . . . . . . . . . . . . . . . . .
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resend . . . . . . . . . . . . . . . . . . . . . . . . .
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LK250 Keyboard Responses . . . . . . . . . . . . . . . . . . . . .
Buffer overrun. . . . . . .
Self-test success. . .
ECHO . . . . . . . . . . . .
Release Prefix . . . . . . .
Acknowledge lACK). . . .
Self-Test Failure . . . . . .
Resend . . . . . . . . . . .
LK250 Keyboard Error Handling. . . . . . . . . . . . . . .
U.S. and Foreign Keyboards. . . . . . . . . . . . . . . . . .
Programming Example . . . . . . . . . . . . . . . . . . . . . . .

8-16
8-15
8-22
8-23
8-23
8-23
8-23
8-23
8-24
8-24
8-24
8-24
8-25
8-25
8-25
8-26
8-26
8-26
8-27
8-28
8-28
8-28
8-29
8-29
8-29
8-30
8-30
8-30
8-30
8-31
8-31
8-31
8-31
8-31
8-31
8-46

Chapter 9 Serial Communications. . . . . . . . . . . . . . . . .

9-1
9-1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents ix

Additional Sources of Information . . . . . . . . . . . . . . . . .
Receive Buffer RegisterlTransmitter Holding Register. . .
Interrupt Enable Register. . . . . . . . . . . . . . . . .
Interrupt Identification Register. . . . . . . . . . . . .
Line Control Register . .
. . . . . . . . . . . . . .
Modem Control Register
. . . . . . . . . . . . . .
Diagnostic Loopback
. . . . . . . . . . . . . .
Line Status Register. . .
. . . . .
. . . . .
Modem Status Register.
Divisor Latches. . . . ..
.. . . . . . . . . . .
Modem Control Programming Exceptions
Special Purpose Register . . . . . . .
Communications Connector Signals . . .
Printer Connector Signals. .
Modem Connector Signals. .
Programming Example . . .
Program Description . .

Chapter 10 Mouse Information.
Introduction. . . . . . . . . . . . .
Communication Requirements . .
Additional Source of Information.
Mouse Commands . . . . . . . . .
.. . . . . .
Prompt Mode Incremental Stream Mode. . .
Request Mouse Position. . . .
. . . . .
Invoke Self-Test . . . . . . . .
Vendor Reserved Function . .
Mouse Reports . . . . . . . .
Position Report - Byte 1.
Position Report - Byte 2.
Position Report - Byte 3.
Self-Test Report - Byte 1 .
Self-Test Report - Byte 2 .
Self-Test Report - Byte 3 .
. ......... .
Self-Test Report - Byte 4 .
. ......... .
Serial Interface. . . . . . . ..
. . . . . . . . . . .
Transmit Holding Register and Receive Buffer
Status Register. . .
Mode Register 1 . .
Mode Register 2 . .
Command Register
Programming Example
x Contents

9-1
9-3
9-4
9-6
9-7
9-9
9-10
9-11
9-13
9-15
9-17
9-18
9-19
9-20
9-21
9-22
9-23
10-1
10-1
10-2
10-2
10-2
10-3
10-3
10-3
10-3
10-4
10-4
10-5
10-5
10-6
10-6
10-7
10-7
10-8
10-8
10-9
10-10
10-11
10-12
10-14

Chapter 11 Diskette Drive Controller
Introduction. . . . . . . . . . . . . . .
Diskette Drive Controller Registers .
Control Register . . . .
Main Status Register . . . . .
Data Register. . . . . . . . . .
Data Transfer Rate Register .
Change Register . . . . . . . .
Diskette Drive Controller Internal Registers.
Internal Register - Command. . . . .
Internal Register - Head/Unit Select
Internal Register - Status Register 0
Internal Register - Status Register 1
Internal Register - Status Register 2
Internal Register - Status Register 3
Internal Register - SRTIHUT
Internal Register - HLT/ND
Internal Register - C .
Internal Register - H.
Internal Register - R.
Internal Register - N
Internal Register - EOT.
Internal Register - GPL .
Internal Register DTL
Internal Register· SC ..
Internal Register - D. . .
Internal Register - STP .
Internal Register- PCN .
Internal Registers - NCN .
Diskette Drive Controller Programming
Command State
Execution State . . . . . . . . . . . .
Result State . . . . . . . . . . . . . .
Command and Result Register Sets.
Programming Example . . . . . . . . . .
<>

Chapter 12 Hard Disk Drive Controller.
Introduction. . . . . . . . . . . . . . . . . . .

11-1
11-1
11-2
11-3
11-4
11-5
11-6
11-6
11-7
11-7
11-8
11-9
11-10
11-12
11-13
11-14
11-15
11-15
11-15
11-15
11-16
11-16
11-16
11-16
11-16
11-17
11-17
11-17
11-17
11-18
11-18
11-20
11-20
11-20
11-27
12-1
12-1

Contents xi

Hard Disk Controller Registers. .
Data Register. . . . . . . . . .
Write Precompensation Register.
Error Register . . .' . . .
Sector Count Register. . . . . . .
Sector Number Register . . . . .
Cylinder Number Low Register.
Cylinder Number High Register.
S DH Register. . . . . .
Cpmmand Register . .
Restore Command
Seek Command . .
Read Sector Command.
Write Sector Command.
Format Track Command.
Read Verify Command ..
Diagnose Command. . . .
Set Parameters Command.
Status Register. . . . . . .
Alternate Status Register.
Hard Disk Register . .
Digital Input Register.
Programming Example . .

Chapter 13 Network Hardware Interface.
Introduction to the LANCE . . . . . . . . . .
Additional Source of Information. . . . . . . .
Functional Description of the Network Hardware Interface
The Coax Transceiver Interface . . .
The Serial Interface Adapter. . . . .
The Local Area Network Controller.
Programming the LANCE . . . . . . . .
Initialization Block . . . . . . . . . .
Receive and Transmit Descriptor Rings
Data Buffers . . . . . . .
Programming Sequence .
Register Description. . . .
Register Data Port (RDP)
Register Address Port (RAP)
Control And Status Register 0 .
Control And Status Register 1 .
Control And Status Register 2 .
xii

Contents

12-1
12-3
12-4
12-5
12-7
12-7
12-8
12-8
12-9
12-10
12-11
12-12
12-13
12-15
12-17
12-19
12-21
12-22
12-23
12-25
12-25
12-26
12-27
13-1
13-1
13-2
13-2
13-2
13-2
13-2
13-3
13-4
13-4
13-4
13-4
13-5
13-6
13-7
13-8
13-13
13-14

Control And Status Register 3 .
NI CSR . . . . . . .
Initialization Block. . .
Mode Field . . . . . . .
Physical Address Field
Logical Address Filter Field
Receive Descriptor Ring Pointer Field
Transmit Descriptor Ring Pointer Field
Buffer Management. . . . . .
Descriptor Rings in Memory . . . . . . .
Receive Descriptor Rings. . . . . . . . .
Receive Message Descriptor 0 (RMDO) .
Receive Message Descriptor 1 (RMD1) .
Receive Message Descriptor 2 (RMD2) .
Receive Message Descriptor 3 (RMD3) .
Transmit Descriptor Ring. . . . . . . . .
Transmit Message Descriptor 0 (TMDO) .
Transmit Message Descriptor 1 (TMDll .
Transmit Message Descriptor 2 (TMD2) .
Transmit Message Descriptor 3 (TMD3) . .
Network Interface External Interconnect .
Network Interface System Bus Interconnect.

13-15
13-17
13-18
13-19
13-22
13-22
13-23
13-25
13-27
13-28
13-29
13-29
13-30
13-32
13-33
13-34
13-34
13-35
13-37
13-38
13-40
13-40

Index
VOLUME 2
Chapter 14 System Startup.

14-1
14-1
14-1
14-9
14-9
14-10
14-11
14-12
14-13
14-14

Overview . . . . .
Powerup Test . . . . . . . . . .
Initialization . . . . . . . .
Real Mode Versus Virtual Protected Mode .
Extended Self-Test ...
Configuration List .
Soft Reset . . . . . . . .
Hard Reset . . . . . . .
Hardware Jumper Configuration.

Chapter 15 ROM BIOS ..... .

15-1
15-3
15-4
15-5
15-5

Interrupt 02H: Nonmaskable Interrupt.
Interrupt 05H: Print Screen
Interrupt 08H: Clock Tick.
Interrupt 09H: Keyboard . .
Contents

xiii

Interrupt OBH: COM2 / Modem
Interrupt OCH: COMI / Serial .
Interrupt OEH: Floppy Disk. . .
Interrupt 10H: Video Input/Output
Function OOH: Set Video Mode.
Function 01H: Set Cursor Type .
Function 02H: Set Cursor Position
Function 03H: Read Cursor Position
Function 04H: Read Light-Pen Position
Function 05H: Set Page Function. . . .
Function 06H: Scroll Active Page Up ..
Function 07H: Scroll Active Page Down
Function 08H: Read Character and Attribute at Cursor
Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function 09H: Write Character and Attribute at Cursor
Position . . . . . . . . . . . . . . . . . . . . . . . . . .
Function OAH: Write Character at Cursor Position.
Function OBH: Set Color Palette
Function OCH: Write Pixel . . . . . . . . . . . . . . .
Function ODH: Read Pixel . . . . . . . . . . . . . . .
Function OEH: Write Character Using Terminal Emulation.
Function OFH: Read Current Video State . . . . . . . . . . .
Function 13H: TTY Write String . . . . . . . . . . . . . . . .
Function DOH: Enable/Disable 256 Character Graphic Font.
Function DIH: Font RAM and Color Map Support ..
Font RAM Functions . . . .
Color Map Functions . . . . .
Interrupt llH: Read Configuration .
Interrupt 12H: Return Memory Size.
Interrupt 13H: Disk Input/Output {I/O) .
Hard Disk Functions . . . . . . .
Hard Disk Errors . . . . . . . . .
Hard Disk Parameter Tables ...
Function OOH: Initialize Entire Disk Subsystem.
Function 01H: Return Status Code of Last 110 Request.
Function 02H: Read One or More Disk Sectors .
Function 03H: Write One Or More Disk Sectors
Function 04H: Verify One or More Disk Sectors
Function 05H: Format a Track . . . . . . . . . . .
Function 08H: Return Current Drive Parameters.
Function 09H: Initialize Drive Characteristics.
Function OAH: Read Long . . . . . . . . . . . . . .
xiv Contents

15-6
15-6
15-7
15-8
15-10
15-12
15-13
15-14
15-15
15-16
15-17
15-17
15-19
15-20
15-21
15-22
15-23
15-24
15-25
15-27
15-28
15-30
15-31
15-31
15-32
15-35
15-37
15-38
15-40
15-40
15-41
15-42
15-43
15-44
15-45
15-46
15-47
15-48
15-49
15-50

Function OBH: Write Long . . . . . . . . .
Function OCH: Seek to Specific Cylinder.
Function ODH: Hard Disk Reset.
Function 10H: Test Drive Ready . . . . . .
Function llH: Recalibrate Drive . . . . . . .
Function 14H: Execute Controller Internal Diagnostics
Function 15H: Return Drive Type . . . . . .
Function DOH: Read Long 256 Byte Sector
Diskette Functions. . . . . . . .
Diskette Errors . . . . . . . . . . . . . .
Diskette Parameter Tables. . . . . . . .
Function OOH: Initialize Diskette Subsystem
Function 01H: Return Status Code of Last I/O Request.
Function 02H: Read One or More Track Sectors .
Function 03H: Write One or More Track Sectors.
Function 04H: Verify One or More Track Sectors.
Function 05H: Format a Track . . . . . . . .
Function 15H: Return Drive Type . . . . . . . . . .
Function 16H: Return Change Line Status . . . . .
Function 17H: Set Drive and Media Type for Format
Interrupt 14H: Asynchronous Communications.
Function OOH: Initialize Asynchronous Port.
Function 01H: Transmit Character.
Buffer Mode Enabled . . . . . .
Function 02H: Receive Character . .
Buffer Mode Enabled . . . . . . .
Function 03H: Return Asynchronous Port Status.
Buffer Mode Enabled. . . . .
Function DOH: Extended Mode
Buffering Enabled. . .
Notification Enabled ..
Error Codes Returned .
Function DIH: Send Break.
Function D2H: Set Modem Control.
Function D3H: Retry on Timeout Error
Function D4H: Set Baud Rate ...
Interrupt 15H: Cassette Input/Output.
Function 80H: Open Device
Function 81H: Close Device . . . .
Function 82H: Termination. . . . .
Function 83H: Set a Wait Interval.
Function 84H: Joystick Support ..

15-51
15-52
15-53
15-54
15-55
15-56
15-57
15-58
15-59
15-59
15-59
15-61
15-62
15-63
15-64
15-65
15-66
15-67
15-68
15-69
15-70
15-72
15-73
15-73
15-74
15-74
15-75
15-76
15-77
15-80
15-81
15-83
15-84
15-85
15-86
15-87
15-88
15-89
15-89
15-90
15-90
15-91
Contents xv

Function 85H: Service System Request Key ..
Function 86H: Wait {No Return to User) ... .
Function 87H: Move a Block of Memory ... .
Function 88H: Return Memory Size Above One Megabyte
Function 89H: Begin Virtual Mode . . . . . . .
Function 90H: Device Is Busy . . . . . . . . . . . . . . .
Function 91H: Interrupt Completion Handler . . . . . .
Function DOH: Return DIGITAL Configuration Word.
Interrupt 16H: Keyboard Input . . . .
Table of Returned Scan Codes . .
Combination Keys . . . . . . . . .
System Reset . . . . . . . . .
System Request Key {Sys Req)
Extended Self-test. .
Break . . . . .
Pause . . . . . . . . .
Print Screen . . . . .
Automatic LED Control.
Function OOH: Keyboard Input. .
Function 01H: Keyboard Status.
Function 02H: Keyboard State. .
Function DOH: Key Notification.
Key Stroke Notification Enabled
Key Buffering Notification Enabled.
Function DIH: Character Count . . . . .
Function D2H: Keyboard Buffer . . . . . . .
Function D3H: Extended Codes And Functions . . . . .
Function D4H: Request Keyboard ID. . . .
. ... .
Function D5H: Send to Keyboard . . . . . . . . . . . . .
Function D6H: Keyboard Table Pointers . . . . . . . .
Keyboard Translation Table Formats And Usage.
Interrupt 17H: Printer Output . . . . . .
Function OOH: Transmit Character . .
Function 01H: Initialize Printer . . . .
Function 02H: Return Printer Status
Function DOH: Redirect Parallel Printer . .
Function DIH: Printer Type . . . .
Function D2H: Parallel Port Retry
Interrupt 18H: Basic . . . . . . . . . . .
Interrupt 19H: Bootstrap . . . . . . . .
DIGITAL Hard Disk Boot Block
xvi

Contents

15-91
15-92
15-93
15-95
15-96
15-98
15-98
15-99
15-101
15-102
15-107
15-107
15-107
15-108
15-108
15-108
15-108
15-108
15-109
15-109
15-110
15-111
15-112
15-113
15-114
15-115
15-116
15-118
15-119
15-120
15-121
15-123
15-124
15-125
15-126
15-127
15-129
15-131
15-132
15-133
15-134

15-135
15-136
15-136
15-137
15-138
15-138
15-139
15-139
15-140
15-140
15-141
15-141
15-142
15-143
15-145
15-145
15-146
15-148
15-148
15-148
15-149
15-150
15-150
15-151
15-151
15-151

Interrupt lAH: Time-of-day . . . . . . .
Function OOH: Read System Clock
Function 01H: Set System Clock.
Function 02H: Read Real-Time Clock.
Function 03H: Set Real-Time Clock.
Function 04H: Return RTC Date
Function 05H: Set RTC Date
Function 06H: Set Alarm . . . . .
Function 07H: Cancel Alarm .. .
Function DOH: Return Days-Since-Read Counter.
Interrupt IBH: Keyboard Break .
Interrupt 1CH: Timer Tick . . . . . . . . . .
Interrupt IDH: Video Parameters . . . . . .
Interrupt lEH: Diskette Parameter Tables.
Interrupt 1 FH: Graphics Character Table Pointer.
Interrupt 40H: Revector of Interrupt 13H . . . . .
Interrupt 41H and 46H: Hard Disk Parameter Tables
Interrupt 4AH: RTC Alarm. . . . . . . . .
Interrupt 70H: Real-Time Clock . . . . . . . . . . . . .
Interrupt 71H: Redirect to Interrupt OAH . . . . . . .
Interrupt 72H: Local Area Network Controller (LANCE).
Interrupt 73H: Serial Printer Port.
Interrupt 74H: Mouse Port.
Interrupt 75H: 80287 Error . . . .
Interrupt 76H: Hard Disk . . . . .
Interrupt 77H: Available (IRQI5)

Chapter 16 Programming the VAXmate Under MS-DOS
16-1
16-1
16-2
16-2
16-2
16-3
16-3
16-3
16-5
16-5
16-5
16-5
16-7
16-8

Overview . . . . . . . . . . . . . . . . . . . .
MS-DOS Operating System Versions.
Loading MS-DOS Operating System .. .
MS-DOS Memory Map . . . . . . . . .
MS-DOS Interrupt 21H Digital Specific Functions
Function 30H Get MS-DOS OEM Number
Function 38H Get/Set Country Code .
Loadable MS-DOS Device Drivers.
ANSI.SYS . . . . . . . . .
Installing ANSI.SYS .. .
Cursor Control Functions.
Erase Functions . . . . .
Set Graphics Rendition . .
Contents

xvii

Set Mode Function . . . . . . . . . . . . .
Reset Mode Function . . . . . . . . . . .
Keyboard Key Reassignment Function .
Mouse Driver . . . . . . . . . . .
Detecting the Mouse Driver . . . . . .
Video Support . . . . . . . . . . . . . .
Function OOOOH: Mouse Initialization
Function 0001H: Show Cursor ... .
Function 0002H: Hide Cursor . . . . .
Function 0003H: Get Mouse Position and Button Status
Function 0004H: Set Mouse Cursor Position ...
Function 0005H: Get Button Press Information . . . . .
Function 0006H: Get Button Release Information . . . .
Function 0007H: Set Minimum and Maximum X-Axis
Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function 0008H: Set Minimum and Maximum Y-Axis
Position . . . . . . . . . . . . . . . . . . . .
Function 0009H: Define Graphics Cursor . . . .
Function OOOAH: Define Text Cusor . . . . . . .
Function OOOBH: Read Mouse Motion Counters
Function OOOCH: Define Event Handler . . . . .
Function OOODH: Enable Light-Pen Emulation.
Function OOOEH: Disable Light-Pen Emulation.
Function OOOFH: Set Mouse Motion/Pixel Ratio
Function 0010H: Conditional Hide Cursor.
Function 0013H: Set Speed Threshold.
Function 001CH: Get Driver Version.
Function 0024H: Get Configuration ..
Function 0025H: Set Configuration ..
Enhanced Graphics Adapter (EGA} Functions
Function FOH: Read EGA Register ... .
Function FIH: Write EGA Register ... .
Function F2H: Read EGA Register Group
Function F3H: Write EGA Register Group
Function F4H: Read EGA Register List.
Function F5H: Write EGA Register List
Function F AH: EGA Functions Installed
MS-DOS Media ID Tables
Disk Parameters .

xviii Contents

16-10
16-11
16-12
16-13
16-14
16-14
16-16
16-17
16-17
16-18
16-19
16-20
16-21
16-22
16-23
16-24
16-26
16-27
16-28
16-30
16-30
16-31
16-31
16-32
16-32
16-33
16-33
16-34
16-35
16-35
16-36
16-36
16-37
16-38
16-38
16-39
16-40

MS-DOS International Support
FONT and GRAFTABL. .
FONT. COM. . . . . . .
GRAFTABL.COM. . . . .
Description of Fonts. . . .
. . . . . . .
How FONT.COM Affects KEYB.COM and SORT.EXE .
Font File Structures. .
Loading Font Files. . .
KEYB . . . . . . . . . . . .
Keyboard Remapping.
Creating Keyboard Map Tables for International Countries .
How Compose Sequences Are Recognized. . . . . . . . .
How Dead Diacritical Keys Are Recognized. . . . . . . .
Format and Use of the Compose Sequence Pointer Table
Format and Use of the Compose Sequence Translation
Table. . . . . . . . . . . . . . . . . . . . . . .
Changing to STDUS.KEY and Back Again
Keyboard Map File Structure
LCOUNTRY . . . . . . . . .
Country File Structure .
Case Conversion Tables.
SORT. . . . . . . . . . . . .
Format for Sorting Order.
Creating Sort Tables for Character Sets. .

Chapter 17 MS-Windows on the VAXmate
Introduction. . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . .
Keyboard Driver for the LK250 Keyboard
Numeric and Edit Keypads. . . . . . .
Keyboard LEDs for the VAXmate LK250 .
VAXmate Compose Handling . . . . . . . .
Reserved Keys Under MS-Windows. . . . .
DIGITAL MS-Windows Keyboard Extensions.
DecSetLockState (lock) .
DecSetKClickVol (vol). . . . . . .
DecSetAutorep (repeat). . . . . .
DecGetKbdCountry ( ) : Result. .
DecSetComposeState (compose_mode) .
DecSetNumlockMode (numlock_mode) .

16-41
16-41
16-41
16-42
16-42
16-42
16-42
16-45
16-45
16-45
16-47
16-49
16-49
16-49
16-50
16-50
16-50
16-52
16-52
16-54
16-55
16-55
16-55
17-1
17-1
17-1
17-2
17-3
17-4
17-4
17-5
17-5
17-6
17-7
17-7
17-8
17-9
17-10

Contents xix

Windows Keyboard Processing Anomalies . . . . . . . . .
Repeating Key Allowed to Change Focus. . . . . . . .
Illogical Set of Keyboard Messages . . . . . .
Key Mappings for VAXmate's LK250. . . . . .
AnsiToOem, OemToAnsi .
ANSI to OEM Table
OEM to ANSI Table
Mouse . . . . . . . . . . . . .
Communications . . . . . . .
. . . . . . . .
LAT Support Through the Windows Asynchronous Serial
. . . . .
Communications Interface.
OpenComm . . . . .
WriteComm . . . . .
TransmitCommChar
ReadComm. . .
CloseComm . .
SetCommState
GetCommState
EscapeCommFunction .
SetCommBreak . . . . . .
ClearCommBreak . . .
SetCommEventMask
GetCommEventMask
FlushComm . . . . . .
GetCommError . . . .
. ......... .
Custom LAT Application Interface Under Windows .
OpenLat (lpServiceName, IpNodeName, IpPortNamel :
Latid . . . . . . . . . . . .
CloseLat (Latidl : Result . . .
ReadLat (Latidl : Result . . . .
WriteLat (Latid, chI: Result .
GetLatStatus (Latidl : Result
SendLatBreak (Latidl : Result . . .
InquireLatServices ( I : LResult . . . . . . . . .
GetLatService (lpServiceNamel : Result ...
Display on the VAXmate . . . .
Standard Applications Support . . . . . . . . . .
Keyboard Handling . . . . . . . . . . . . . . .
Keyboard Handling Inside an MS-Windows Window.
Keyboard Handling Outside an MS-Windows Window.
ANSI Support Inside an MS-Windows Window . . . . . . .
xx

Contents

17-11
17-11
17-12
17-13
17-55
17-55
17-58
17-61
17-61
17-62
17-63
17-63
17-64
17-64
17-64
17-65
17-65
17-65
17-65
17-65
17-65
17-65
17-65
17-66
17-66
17-67
17-68
17-68
17-69
17-69
17-70
17-70
17-71
17-73
17-74
17-75
17-75
17-78
17-79

Video Modes Handled Inside an MS-Windows Window.
Interrupt llh Support
Interrupt 12h Support
Interrupt 15h Support
Unique Icons ..
Printers . . . . . . . . . .
DECWIN.H File Listing.

Chapter 18 VAXmate Network Software.
Introduction. . . . . . . .
Documentation List . . . . . .
Datalink . . . . . . . . . . . . . . .
Common Definition Formats.
Multicast Address Format
Software Capabilities .
Datalink Functions . . . .
Datalink Return Codes . .
Function OOH: Initialization Idll_init) .
Function 01H: Open a Datalink Portalldll_open).
Function 02H: Close a Datalink Portalldll_close).
Function 03H: Enable Multicast Addresses
Idll_enable_mul) . . . . . . . . . . . . . . . . .
Function 04H: Disable Multicast Addresses
(dll_disable_mul). . . . . . . . . . . . . . . . .
Function 05H: Transmit Idll_transmit) . . . .
Function 06H: Request Transmit Buffer Function
(dllJequest_xmit) . . . . . . . . . . . . . . . . . . . .
Function 07H: Deallocate Buffer (dll_deallocate) ..
Function 08H: Read Channel Status (dllJead_chan).
Function 09H: Read the Portal List (dll_read_plist)
Functions OAH: Read the Portal Status
IdllJead _portal) . . . . . . . . . . . . . . . . .
Function OBH: Read the Datalink Counters
(dllJead_count) . . . . . . . . . . . . . .
Function OCH: Network Boot Request
(dll_network_boot) . . . . . . . . . . . . .
Function ODH: Enabling a Channel Function
(ddl_enable_chan) . . . . . . . . . . . . . . . . .
Function OEH: Disabling a Channel (dll_disable_chan).
Function llH: Read Decparm String Address
(dll_readecparm) . . . . . . . . . . . . . . . . . . .

17-79
17-82
17-82
17-83
17-83
1 '7-83
17-85
18-1
18-1
18-4
18-5
18-6
18-7
18-8
18-11
18-13
18-16
18-18
18-21
18-22
18-24
18-25
18-27
18-28
18-29
18-31
18-32
18-34
18-38
18-39
18-40
18-41
Contents

xxi

Function 12H: Set Decparm String Address
(dll_setdecparm) . . . . . . . . . . . . . . . . . .
Function 13H: External Loopback (dll_ext_loopback)
Maintenance Operation Functions. . . . . . . . . . . . .
Data Link Interface to the MOP Process . . . . . . . '.'
Function OFH: Mop Start and Send System 10
(dll_start_mop) . . . . . . . . . . . . . . . . .
Function 10H: Mop Stop (dll_mop_stop).
Sample Datalink Session .
Local Area Transport . . .
LAT Services. . . . . .
LAT Command Line
Data Structures . . . .
. ....
LAT Functions. . . . .
. . . . .
Function 03H: LAT Get Status ..
Function DOH: Open Session ...
Function DOH: Close LAT Session.
Function 02H Read Data. . . . . . .
Function 01H: Send Data . . . . . .
Function D5H: Get Next LAT Service Name.
Function D6H: LAT Service Table Reset
Function D1H: Send Break Signal
Sample Terminal Program .
Session . . . . . . . . . . . . . . . . . . . .
Software Capabilities . . . . . . . . .
MS-Network Session Control Block.
DIGITAL-Specific Session Control Block ..
Synchronous Requests . . . . . . . . . .
Asynchronous Requests. . . . . . . . . .
Asynchronous Notification Routine ...
Network Addressing. . . . . . . . . . . .
Session Level Services . . . . . . . . . .
MS-Network Compatible Session Level Services
MS-Network Session Level Return Codes . . . .
Function OOH and Function B800H: Check for Presence
of MS-Network Session . . . . . . . . .
Function 35H: Cancel (synchronous) ..
Function 32H: Reset (synchronous). .
Function 33H: Status (synchronous) ..
Function B3H: Status (asynchronous) .
Function 30H: Add Name (synchronous).
Function BOH: Add Name (asynchronous).
xxii Contents

18-42
18-43
18-44
18-47
18-47
18-47
18-48
18-56
18-57
18-57
18-60
18-66
18-67
18-68
18-69
18-70
18-71
18-72
18-73
18-74
18-75
18-84
18-86
18-86
18-89
18-90
18-90
18-91
18-91
18-92
18-93
18-94
18-97
18-98
18-99
18-100
18-100
18-103
18-103

Function 31H: Delete Name (synchronous) .
Function B1H: Delete Name (asynchronous)
Function 34H: Name Status (synchronous) .
Function B4H: Name Status (asynchronous)
Function 10H: Call (synchronous) ..
Function 90H: Call (asynchronous) ..
Function 11H: Listen (synchronous) .
Function 91H: Listen (asynchronous).
Function 12H: Hangup (synchronous)
Function 92H: Hangup (asynchronous).
Function 14H: Send (synchronous) ...
Function 94H: Send (asynchronous) ..
Function 17H: Send Double (synchronous).
Function 97H: Send Double (asynchronous) .
Function 15H: Receive (synchronous) ... .
Function 95H: Receive (asynchronous) ... .
Function 16H: Receive Any (synchronous) ..
Function 96H: Receive Any (asynchronous) .
Datagram Commands . . . . . . . . . . . . . . .
Function 20H: Send Datagram (synchronous) .
Function AOH: Send Datagram (asynchronous) .
Function 21H: Receive Datagram (synchronous)
Function A1H: Receive Datagram (asynchronous)
Function 22H: Send Broadcast (synchronous) ..
Function A2H: Send Broadcast (asynchronous) ..
Function 23H: Receive Broadcast (synchronous) .
Function A3H: Receive Broadcast (asynchronous)
DIGITAL-Specific Session Level Services ...
Function OOH: DIGITAL Function Check
(decfunccheck) . . . . . . . . . . . . . . . . .
Function 01H: Add a Node (decfuncadd) ..
Function 02H: Delete Entry Given the Node Number
(decfuncdelnum) . . . . . . . . . . . . . . . . . . . .
Function 03H: Delete Entry Given Node Name
(decfuncdelname) . . . . . . . . . . . . . . . . . . .
Function 04H: Read Node Entry Given Node Number
(decfuncreadnum) . . . . . . . . . . . . . . . . . . . . . .
Function 05H: Read Node Entry Given Node Name
(decfuncreadname). . . . . . . . . . . . . . . . . .
Function 06H: Read Node Entry Given Index
(decfuncreadindex). . . . . . . . . . . . . . . . . .
Function 07H: Delete All Node Entries (decfuncdelall).
Contents

18-104
18-104
18-105
18-105
18-107
18-107
18-109
18-109
18-110
18-110
18-111
18-111
18-112
18-112
18-113
18-113
18-114
18-114
18-115
18-116
18-116
18-117
18-117
18-118
18-118
18-119
18-119
18-120
18-121
18-122
18-123
18-124
18-125
18-126
18-127
18-128
xxiii

Server Message Block (SMB) Protocol . . . . . . . . . . . .
Extended Function DOH: Get Current Date and Time ,

Appendix A Support Code for Examples ..
File: SUPPORT.ASM '.
File: EXAMPLE.H .
File: KYB.H ... .
File: RB.H . . . . .
File: VECTORS.C
File: RB.C .. .
File: DEMO.C .. .

. .....

18-129
18-130
A-I
A-I
A-9
A-I0
A-ll

A-12
A-16
A-18

Appendix B 80286 Instruction Set

B-1

Appendix C VT220 and VT240 Terminal Emulators.

C-l
C-2
C-2
C-2
C-2
C-2
C-2
C-2
C-3
C-3
C-3
C-3
C-3
C-4
C-4
C-4
C-4
C-4
C-5
C-5
C-5
C-5
C-6

VT220 Emulator and VT220 Terminal Differences
Saving and Restoring Set-Up Selections. .
Video Differences . . . . . . . . . . . .
Scrolling . . . . . . . . . . . . . . . .
Blinking Characters Remapped . .
No Control Representation Mode.
Font Selection . . . . . . . . . . . .
Communications Differences. . . . . .
LAT Protocol Support (Network Terminal Services) .
No Split Baud Rate. . .
Session Logging. . . . .
Autotyping Characters .
Keyboard Differences . . .
Keyboard LEDs . . . .
Alternate Characters .
Keyclick. . . . . . . . .
Autorepeat Selection . . . . . .
Character Sets . . . . . . . . . . . .
DEC MCS to ISO Latin-l 8-bit Transition
Language Selection . . . . . . . . . . . .. .
Compose Sequences. . . . . . . . . . . . . .
Additional VT220 Emulator Escape Sequences
Assign User-Preference Supplemental Character Set
(DECAUPSS) . . . . . . . . . . . . . . . . . . . . . . . .
Request User-Preference Supplemental Character Set
(DECRQUPSS) . . . . . . . . . . . . . . . . . . . . . . . .
Select User-Preference Supplemental Coded Character
Set (SCS). . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxiv Contents

C-6
C-6
C-6

Select DEC Supplemental Coded Character Set .(SCS) .
Select ISO Latin-l Supplemental Coded Character Set
(SCS) . . . . . . . . . . . . . . . . .
Primary Device Attribute (DA) . . . . .
Secondary Device Attribute (DA) . . . .
Announcing ANSI Conformance Levels
Printing . . . . . . . .
Printer Options .
Print Terminator
Print Size. . . . .
VT240 Emulator and VT240 Terminal Differences
Saving and Restoring Set-Up Selections.
Video Differences . . . . . . . . . . . .
Video Modes . . . . . . . . . . . . .
Automatic Video Mode Switching.
Scrolling . . . . . . . . . . . . . . .
No Control Representation Mode.
Underlined Characters. . . . . . .
Line Attributes . . . . . . . . . . .
Double Width Lines for Fast Text Only
Double Height/Double Width Lines for Fast Text Only
Communications Differences. . . . . . . . . . . . . . . . .
LAT Protocol Support (Network Terminal Services) .
Session Logging. . . . .
Autotyping Characters.
Keyboard Differences . . .
Keyboard LEDs . . . . .
Alternate Characters. .
No "Printer to Host" Mode.
Character Sets . . . . . . . .
DEC MCS to ISO Latin-l S-bit Transition
Compose Sequences. . . . . . . . . . . . . .
Additional VT240 Emulator Escape Sequences
User-Preference Supplemental Character Set
(DECAUPSS) . . . . . . . . . . . . . . . . . . .
Request User-Preference Supplemental Character Set
(DECRQUPSS) . . . . . . . . . . . . . . . . . . . . . . . .
Select User-Preference Supplemental Coded Character
Set (SCS). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select DEC Supplemental Coded Character Set (SCS) .
Select ISO Latin-l Supplemental Coded Character Set
(SCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C-7
C-7
C-S
C-S
C-S
C-9
C-9
C-9
C-9
ColO
ColO
C-IO
C-IO
C-IO
C-IO
ColO
C-lI
C-lI
C-II
C-II
C-12
C-12
C-12
C-12
C-12
C-12
C-12
C-12
C-13
C-13
C-13
C-13
C-13
C-14
C-14
C-15
C-15

Contents xxv

Primary Device Attribute (DA) . . . . .
Secondary Device Attribute (DA) . . . .
Announcing ANSI Conformance Levels

C-15
C-16

Bibliography
Index
Tables
Table 2-1 Physical Memory Map. . . .
Table 2-2 Input/Output Address Map .
Table 2-3 Interrupt Vector Map . . . .
Table 2-4 8-Bit Expansion Bus Transfer Times
Table 2-5 Expansion Slot Power Ratings . .
Table 3-1 Interrupt Request Lines . . . . . . . .
Table 3-2 Master and Slave 110 Addresses . . .
Table 3-3 Accessing the Interrupt Controller Registers.
Table 4-1 DMA Request Line Assignments. . . . . . . .
Table 4-2 DMA Controller States . . . . . . . . . . . . .
Table 4-3 DMA Controller and Page Register Address Map.
Table 5-1 Real-Time Clock Address Map
Table 5-2 Rate Selection Bits. . . . . . .
Table 5-3 RTC Data Register Ranges . .
Table 5-4 RTC Automatic Alarm Cycles.
Table 6-1 Counter Signals. . . . . . . . .
Table 6-2 Modes Used by the Three Counters
Table 6-3 8254 and System Register Addresses.
Table 7-1 Available Video Modes. . . . . . . . . .
Table 7-2 Attribute Byte Bit Definitions . . . . .
Table 7-3 Text Mode Display Pages (ROM BIOS) .
Table 7-4 Default VLT Contents . . . . . . . . . . .
Table 7-5 VLT Contents' for Video Modes DIH and D2H.
Table 7-6 Video Processor 1/0 Registers.
Table 7-7 CRTC Internal Registers . . . . . . . .
Table 7-8 CRTC Register Values . . . . . . . . . .
Table 7-9 Color Select Register Bit Assignments
Table 7-10 Color Palettes Selected by CPS and SIC.
Table 7-11 Selecting Video Modes . .
Table 7.. 12 Monitor Interface Signals
Table 8-1 Port 1 Bit Definitions . . .
Table 8-2 Port 2 Bit Definitions . . .
Table 8-3 Keyboard-Interface Controller Commands
Table 8-4 Command Byte Bit Definitions. . . . . . .
xxvi

Contents

2-3
2-4
2-7
2-10
2-10

3-2
3-3
3-4
4-2
4-2
4-6
5-3
5-5
5-11
5-12
6-3
6-3
6-8
7-5
7-6
7-8
7-20
7-21
7-22
7-26
7-27
7-40
7-40
7-42
7-44
8-3
8-4
8-9
8-10

Table 8·5 LK250 Scan Codes and Industry·standard
Equivalent Values . . . . . . . . . . . . . . . . . . .
Table 8·6 Scan Codes Translated But Not Used.
Table 8·7 LK250 Keyboard Command Codes.
Table 8·8 LK250 Keyboard Responses ...
Table 9·1 8250 UART Register Addresses
Table 9·2 Interrupt Identification . . . . .
Table 9·3 Baud Rate Table . . . . . . . . .
Table 9·4 Communications Connector Signals .
Table 9·5 Printer Connector Signals. . . . . . .
Table 9·6 Modem Telephone Line Connector Signals .
Table 9·7 Handset Connector Signals . .
Table 10·1 Mouse Command Summary.
Table 10·2 Serial Interface Registers . .
Table 10·3 Baud Rate Table. . . . . . . .
Table 11·1 Diskette Drive Controller Registers
Table 11·2 Diskette Drive Controller Commands
Table 11·3 Register Sets for Read Data Command
Table 11·4 Register Sets for Write Data Command.
Table 11·5 Register Sets for Read Deleted Data Command
Table 11·6 Register Sets for Write Deleted Data Command.
Table 11·7 Register Sets for Read Track Command. .
Table 11·8 Register Sets for Read ID Command. . . .
Table 11·9 Register Sets for Format Track Command
Table 11·10 Register Sets for Scan Equal Command .
Table 11·11 Register Sets for Scan Low or Equal Command.
Table 11·12 Register Sets for Scan High or Equal Command
Table 11·13 Register Sets for Recalibrate Command . .
Table 11·14 Register Sets for Sense Interrupt Status
Command . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11·15 Register Sets for Specify Command . . . .
Table 11·16 Register Sets for Sense Drive Status Command
Table 11·17 Register Sets for Seek Command. . . . . . . .
Table 12·1 Hard Disk Controller Registers . . . . . . . . . .
Table 12·2 Hard Disk Controller Diagnostic Result Codes.
Table 12·3 Memory Image of a Sector Interleave Table ...
Table 12·4 Hard Disk Controller Diagnostic Result Codes.
Table 13·1 Network Interface Registers . . . . . . . . . . . .
Table 13·2 LANCE CSR3 Required Values for the VAXmate
Workstation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14·1 VAXmate Powerup and Self·Test Error Codes
Table 14·2 VAXmate Processor Board Jumpers . . . . . .
Contents

8·17
8·21
8·22
8·30
9·2
9·6
9·16
9·19
9·20
9·21
9·21
10·2
10·8
10·11
11·2
11·19
11·21
11·21
11·22
11·22
11·23
11·23
11·24
11·24
11·25
11·25
11·26
11·26
11·26
11·27
11·27
12·2
12·6
12·18
12·21
13·5
13·16
14·8
14·14
xxvii

Table 15-1 ROM BIOS Interrupt Vectors . . . .
Table 15-2 Interrupt lOH: Video 110 Functions
Table 15-3 Video Modes . . . . . . . . . . . . . .
Table 15-4 Mode Dependent Values for Set CursQr Type .
Table 15-5 Default Color Map. . . . . . . . . . . , . . . .
Table 15-6 Color Map for Video Modes D1H and D2H .
Table 15-7 Hard Disk Error Codes. . . . . . . " . . .
Table 15-8 Hard Disk Parameter Table Descri~tion .
Table 15-9 Diskette Error Codes. . . . . . . . • . . .
Table 15-10 Diskette Parameter Table Desgription .
Table 15-11 Communications Control B1,~k (CCB)
Description
Table 15-12 CCB Buffer Structure Descrip,tt<m . . .
Table 15-13 Keyboard Scan Codes Return~ by The ROM
BIOS . . . .
Table 15-14 Diskette Parameter Table D~~ription . . .
Table 15-15 Hard Disk Parameter Tabl~ Description . ,
Table 16-1 Cursor Control Functions . " . . .
Table 16-2 Erase Function . . . . . . . . . . .
Table 16-3 Set Graphics Rendition Function. .
Table 16-4 Set Mode Function . . . . . . . . .
Table 16-5 Reset Mode Function. . . . . . . .
Table 16-6 Keyboard Key Reassignment Function.
Table 16-7 Standard Mouse Drive Functions. . . . . . .
Table 16-8 Extended Mouse Driver Ftmctions . . . . . .
Table 16-9 Video Sytems and Modes Supported by
MOUSE.SYS . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-10 Extens~~ms to Interrupt 10H EGA Functions.
Table 16-11 EGA ~ister Groups and Associated Registers
Table 16-12 Hard Disk Types. . . . . . . .
Table 16-13 BIOS Parameter Block Data.
Table 16-14 .FNT File Structure ..
Table 16-15 .GRF File Structure. . . . . .
Table 16-16 Keyboard Tables. . . . . . . .
Table 16-17 Keyboard Map File Structure
Table 16-18 Characters Causing Problems for
COMMAND. COM . . . . . . . . . . . . . . . . . .
Table 16-19 Sort Order for Industry-Standard Character Set
(S1'D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-20 Sort Order for DIGITAL Multinational Character
Set (MCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxviii

Contents

15-1
15-9
15-10
15-12
15-33
15-34
15-40
15-41
15-59
15-60
15-78
15-80
15-104
15-143
15-147
16-6
16-7
16-8
16-10
16-11
16-12
16-13
16-14
16-15
16-34
16-34
16-39
16-40
16-43
16-15
16-16
16-50
16-54
16-56
16-57

Table 16-21 Sort Order for International Standards
Organization Character Set (ISO) . . . . . . . . . . . . .
Table 16-22 Sort Order for French 7-Bit National
Replacement Character Set (FR7) . . . . . . . . . . . .
Table 16-23 Sort Order for German 7-Bit National
Replacement Character Set (GR7) . . . . . . . . . . . .
Table 17-1 Keyboard Messages Transmitted by MS-Windows .
Table 17-2 US to ASCII Translation Table. . .
Table 17-3 Danish to ASCII Translation Table.
Table 17-4 Finnish to ASCII Translation Table
Table 17-5 French to ASCII Translation Table.
Table 17-6 French Canadian and Bilingual Canadian to ASCII
Translation Table. . . . . . . . . . . . . . . . . . . .
Table 17-7 German to ASCII Translation Table. .
Table 17-8 Italian to ASCII Translation Table ...
Table 17-9 Norwegian to ASCII Translation Table.
Table 17-10 Spanish to ASCII Translation Table .
Table 17-11 Swedish to ASCII Translation Table .
Table 17-12 Swiss French to ASCII Translation Table.
Table 17-13 Swiss German to ASCII Translation Table.
Table 17-14 Translation of ANSI Set to OEM Set.
Table 17-15 Translation of OEM Set to ANSI Set.
Table 17-16 INT 10H Functions . . . . . . . . . . .
Table 17-17 Supported Video Modes. . . . . . . . .
Table 17-17 Character Sets Supported by Each Printer.
Table 18-1 Interrupt 6D: Datalink Functions. . . . . . . .
Table 18-2 Datalink Return Codes . . . . . . . . . . . . . .
Table 18-3 Recommended Values for Datalink Parameters ..
Table 18-4 LAT Call Back Routine . . . . . . . .
Table 18-5 Interrupt 6A: LAT Functions . . . . . . .
Table 18-6 Session Control Block Fields . . . . . . . . .
Table 18-7 DIGITAL Session Control Block Fields ..
Table 18-8 Interrupt 2A: MS-Network Compatible Services ...
Table 18-9 Interrupt 2A: DIGITAL Specific Session Extensions
Table 18-10 Error Codes Returned by Session .. .
Table 18-11 Session Status Buffer . . . . . . . . . . .
Table C-1 DEC MCS - ASCII Graphics Set (0-7) ..
Table C-2 DEC MCS - Supplemental Graphics Set
Table C-3 ISO Latin-1 Character Set (0-7) ... .
Table C-4 ISO Latin-1 Character Set (8-15) ... .
Table C-5 DEC Special Graphics Character Set.
Contents

16-58
16-59
16-60
17-12
17-15
17-21
17-23
17-27
17-30
17-33
17-36
17-39
17-42
17-45
17-48
17-51
17-55
17-58
17-80
17-82
17-84
18-12
18-13
18-17
18-62
18-66
18-87
18-89
18-92
18-92
18-94
18-100
C-18
C-19
C-20
C-21
C-22
xxix

Figures
Figure 1-1 Base Configuration Workstation . .. . . . .
Figure 1-2 Workstation With Installed Expansion Box.
Figure 1-3 Optional 80287 Coprocessor. . . . . . . .
Figure 1-4 Optional Two Megabyte DRAM Module. . .
Figure 1-5 Optional Modem Module. . . . . . . . . . . .
Figure 1-6 Block Diagram of Workstation Components.
Figure 2-1 8-Bit And 16-Bit Bus Connectors.
Figure 3-1 Priority Before Rotation
Figure 3-2 Priority After Rotation. . . . . . .
Figure 3-3 Interrupt Sequence . . . . . . . . .
Figure 6-1 Three Channel Counter/Timer Block Diagram
Figure 7-1 Block Diagram of the VAXmate Video Controller.
Figure 7-2 Character Buffer Format. . . . . . . . . . . . . . .
Figure 7-3 Memory Organization for 320 x 200 4-Color Mode.
Figure 7-4 Pixel to Bit-Field Map for 4-Color Mode. . . . .
Figure 7-5 Memory Organization for 320 x 200 16-Color
Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-6 Pixel to Bit-Field Map for 16-Color Mode . . . .
Figure 7-7 Memory Organization for 640 x 200 2-Color Mode.
Figure 7-8 Pixel to Bit-Field Map for 2-Color (Monochrome)
Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-9 Memory Organization for 640 x 200 4-Color Mode .
Figure 7-10 Pixel to Bit-Field Map for 4-Color Mode . . . .
Figure 7-11 Memory Organization for 640 x 400 2-Color
Mode . . . .
Figure 7-12 Pixel to Bit-Field Mapfor 2-Color Mode . . . .
Figure 7-13 Memory Organization for 640 x 400 4-Color
Mode . . . .
Figure 7-14 Pixel to Bit-Field Map for 4-Color Mode . . . .
Figure 7-15 Memory Organization for 800 x 252 4-Color
Mode . . . .
Figure 7-16 Pixel to Bit-Field Map for 4-Color Mode
Figure 8-1 Keyboard Position Labels .. .
Figure 8-2 U .S.lU.K. Keyboard . . . . .
Figure 8-3 Canadian/English Keyboard .
Figure 8-4 Danish Keyboard . . . . . .
Figure 8-5 Finnish Keyboard . . . . . .
Figure 8-6 French/Canadian Keyboard
Figure 8-7 French Keyboard . . . . . .
Figure 8-8 German/Austrian Keyboard
Figure 8-9 Hebrew Keyboard . . . . . .
xxx

Contents

1-2
1-3
1-4
1-4
1-4
1-5
2-11
3-14
3-14
3-20
6-2
7-3
7-6
7-11
7-11
7-12
7-12
7-13
7-13
7-14
7-14
7-15
7-15
7-16
7-16
7-17
7-17
8-16
8-32
8-33
8-34
8-35
8-36
8-37
8-38
8-39

Figure 8-10 Italian Keyboard . . .
Figure 8-11 Norwegian Keyboard
Figure 8-12 Spanish Keyboard ..
Figure 8-13 Swedish Keyboard ..
Figure 8-14 Swiss/French Keyboard.
Figure 8-15 Swiss/German Keyboard
Figure 10-1 VAXmate Mouse (Part Number VSXXX)
Figure 13-1 Descriptor Rings . . . . . . . . . .
Figure 14-1 Test Sequence - Processor Board
Figure 14-2 Test Sequence - 110 Board ... .
Figure 14-3 Test Sequence - Options . . . . .
Figure 14-4 Test Sequence - Initialization and Bootstrap.
Figure 14-5 VAXmate Configuration Screen . . . . . . . .
Figure 14-6 VAXmate Processor Board Jumper Configuration
Figure 15-1 LK250 Keyboard Layout . . . . . .
Figure 16-1 MS-DOS Date and Time Structure
Figure 17-1 Keyboard Position Labels. . . .
Figure 18-1 VAXmate Network Components ..
Figure 18-2 Multicast Address Format . . . . .
Figure 18-3 Session Interface Implementation.

8-40
8-41
8-42
8-43
8-44
8-45
10-1
13-28
14-2
14-4
14-5
14-6
14-12
14-14
15-103
16-4
17-14
18-2
18-7
18-85

Contents xxxi

Preface

Audience
This manual provides reference material about the VAXmate workstation. It
covers all programmable components, the firmware, and several MS-DOS related environments. The material and its presentation are directed to experienced programmers or software designers.

Manual Organization
This manual is divided into four parts and appendixes:
• Chapter 1 provides an overview of the VAXmate workstation and optional
equipment.
• Chapters 2 through 13 introduce the VAXmate workstation
programmable hardware devices. Each chapter discusses a single hardware programming task, such as video input/output (1101, external interrupt processing, or serial communications and includes the following
information:
A brief device description
A list of additional references
A description of the programmable hardware registers
A programming example
A discussion of the example
The examples are written in the C programming language to reduce the
size of the examples and focus on the task rather than the detail required
by the language.
• Chapter 14 describes the power-up diagnostics and system startup.
• Chapter 15 describes the read-only memory basic input/output system
(ROM BlOSl.
• The appendixes contain additional information, including a bibliography of
other useful publications.
Preface

xxxiii

Terminology
The following terms are used throughout this manual and are defined as
follows:
Term

Definition

Industry-standard

The computer industry recognizes two open architectures
as industry standards, the IBM PC AT bus structure and
the Microsoft disk operating system (MS-DOS}. Moreover,
supporting MS-DOS requires a defined set of ROM BIOS
services. The term industry-standard refers to compatibility with these architectures.

Reserved
Available
Unassigned

To avoid confusion and incompatibility, the use of certain
items such as memory space, 110 space, interrupt vectors,
and ROM BIOS parameters or return values must be
clearly defined. These three categories define those items
that do not have a specific use.
Reserved

In future hardware or software releases,
DIGITAL may define a specific use for this
item. Hardware or software applications
that use this item may not work with
future releases.

Available

Hardware or software applications can use
this item. DIGITAL has defined the specific use of this item as available for
applications.
Hardware or software applications can use
this item. However, there remains some
risk that DIGITAL may define a specific
use for this item.

Unassigned

xxxiv Preface

Federal Communications Commission
Radio Frequency Interference
Class A Computing Devices
This equipment generates, uses, and may emit radio frequency energy. The
equipment has been tested and found to comply with the limits for a Class A
computing device pursuant to Sub-part J of Part 15 of FCC Rules, which are
designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation of this equipment
in a residential area may cause interference in which case the user at his own
expense may be required to take measures to correct the interference.
If this equipment does cause interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged
to try to correct the interference by one or more of the following methods:

• re-orient the receiving antenna
• relocate the computer with respect to the receiver
• move the computer away from the receiver
• plug the computer into a different outlet so that computer and receiver
are on different branch circuits.
If necessary, the user should consult the dealer or an experienced radio

and television technician for additional suggestions. The user may find the
booklet, How to Identify and Resolve RadiolFV Interference Problems,
prepared by the Federal Communications Commission helpful. This booklet is
available from the U.S. Government Printing Office, Washington, DC 20402,
Stock No. 004-000-00398-5.
NOTE
Shielded cables are provided for use with this device. Should any
cables be replaced or added for any reason, these cables should
be the same as, or with higher shielding capabilities, than those
provided by Digital Equipment Corporation.

Preface

xxxv

Chapter 1
VAXmate Workstation Overview
This chapter describes the VAXmate workstations physical appearance, base
configuration, optional components, and the logical relationship of the
components.
The VAXmate workstation is a high-performance, standalone, desktop personal
computer that executes industry-standard software. The integral Ethernet interface allows the VAXmate workstation to communicate on a network. The hard
disk storage, provided in the optional expansion box, allows the VAXmate
workstation to be a server on a network.

Base System
In the base configuration, the VAXmate workstation has three units:

• System unit
• Keyboard
• Mouse
Figure 1-1 shows a base configuration workstation.

VAXOlate Workstation Overview

1- 1

Figure I-I

Base Configuration Workstation

In the base configuration, the system unit contains the following major
components:
•
•
•
•
•
•
•
•
•
•
•
•
•

1- 2

80286 microprocessor
One megabyte of dynamic random-access memory (DRAM)
Video monitor and controller
Diskette drive and controller
Ethernet controller
Keyboard interface controller
Event timer
Real time clock and calendar
Serial communications port
Serial printer port
Serial mouse port
Speaker
Power supply

VAXmate Workstation Overview

Optional Components
The workstation provides for the following optional components:
• An expansion box, part number RCD31-EA, that attaches to the bottom
of the system unit. Figure 1-2 shows the system unit with the expansion
box attached. The expansion box contains an additional power supply, a
battery, a 20 megabyte hard disk drive and controller, and two industry"
standard expansion slots.
• An 80287 coprocessor, part number FP287, that installs in the system
unit. Figure 1-3 shows the 80287 coprocessor.
• A two megabyte DRAM module, part number PC50X-AA, that installs in
the system unit. Figure 1-4 shows the two megabyte DRAM module.
• A modem module, part number PC50X-MA, that installs in the system
unit. Figure 1-5 shows the modem module.

Figure 1-2

Workstation With Installed Expansion Box

VAXmate Workstation Overview

1- 3

LJ-0725

Figure 1-3

Optional 80287 Coprocessor

o
C]oC]oC]oC]
==C]OC]OC]OC]
C]OC]OC]OC]
==C]OC]OC]OC]
=OC]OC]OC]OC]
C]OC]OC]OC]
=C]OC]OC]OC]
C]OC]OC]OC]
OC]OC]OC]OC]

Figure 1-4

0= =

Do
o

c:JOCJ

=
0
0

Optional Two Megabyte DRAM Module

===
===
= =

Figure 1-5

1- 4

Optional Modem Module

VAXmate Workstation Overview

Figure 1-6 shows the relationship of the workstation components. The battery
is present only when an expansion box is installed.

SPEAKER

'-ir--tr-- SER!Al PRINTER
t---t-----it-- SERIAL COMM

t - - t - t - I - - T E LEPHQNE

AC --.-~t---t

--------,
I
I
I
I
HARD DISK CONTROLLER

/~....

I
L

SLOT
#2

II
BATTERY BACK·UP
FOR REAL TIME CLOCK

"::'

I
II

-----------------~

Figure 1-6

Block Diagram of Workstation Components

VAXmate Workstation Overview

1- 5

Chapter 2
V AXmate Microprocessor
Overview
The VAXmate microprocessor is an Intel 80286 central processing unit (CPU).
The CPU is a high-performance, 8 MHz microprocessor with a 16-bit external
data path and a 24-bit address path. The CPU provides two modes of operation, real address mode and protected virtual address mode.

Real Address Mode
On powerup, the CPU operates in real address mode. In real address mode, the
80286 CPU behaves as though it is a fast 8086 CPU. It is limited to the 1
Mbyte address range of the 8086 CPU. In real address mode, the ROM is accessed in the address range OFOOOOH-OFFFFFH.

Protected Virtual Address Mode
In protected virtual address mode, the 80286 CPU can access 16 Mbytes of
physical memory and 1 gigabyte of virtual memory.
The ROM is redundantly mapped to two physical address ranges, OFOOOOHOFFFFFH and FFOOOOH-FFFFFFH. Therefore, in protected virtual address
mode, the 80286 CPU can access the ROM at either physical address range.
However, the majority of the ROM BIOS code is not valid in protected virtual
address mode.
The CPU uses the keyboard interface controller or a double exception fault to
reset to real address mode from protected virtual address mode. The keyboard
interface controller is discussed in Chapter 8.

VAXmate Microprocessor

2- 1

Coprocessor
The optional coprocessor for the VAXmate workstation is an Intel 80287 processor extension chip. It is a high-performance, numeric processor that extends
the CPU data types to include floating-point, extended-integer, and binarycoded decimal (BCDI.

Additional Sources of Information
The following Intel Corporation documents provide additional information on
the CPU and coprocessor:

• Introduction to the iAPX 286 (Publication Number 2103081
• iAPX 286 Hardware Reference Manual (Publication Number 210760}
• iAPX 286 Programmer's Reference Manual (Publication Number 2104981
• Microsystem Components Handbook (Publication Number 2308431

2- 2

VAXmate Microprocessor

Memory Map
The base configuration workstation has 1 Mbyte of RAM and 64 Kbytes of
ROM. An optional memory module can be added without an expansion box.
Table 2-1 describes the VAXmate workstation's physical memory map. The 1
Mbyte of RAM is divided into three, noncontiguous blocks. In Table 2-1, these
blocks are labeled BLOCK1, BLOCK2, and BLOCK3.
Table 2-1

Physical Memory Map

From

Size
(Bytes)

Description

OOOOOOH

09FFFFH

640K

System RAM (BLOCK1)

OAOOOOH

OAFFFFH

64K

Reserved

OBOOOOH

OBFFFFH

64K

Video RAM
During video mode setup, the video
RAM is dynamically mapped. Only
the video RAM required by the current video mode is accessible.

OCOOOOH

OCFFFFH

64K

Available for options with expansion
ROM

ODOOOOH

OEFFFFH

128K

DIGITAL private RAM (BLOCK2)

OFOOOOH

OFFFFFH

64K

System ROM

100000H

EFFFFFH

14336K

Optional RAM space

FOOOOOH

FIFFFFH

128K

Reserved RAM space

F20000H

F5FFFFH

256K

DIGITAL private RAM (BLOCK3)

F60000H

F7FFFFH

128K

Reserved RAM space

F80000H

FEFFFFH

448K

Reserved ROM space

FFOOOOH

FFFFFFH

64K

System ROM (redundantly mapped
from OFOOOOH)

VAXmate Microprocessor

2- 3

Input/Output Address Map
Table 2-2 describes the VAXmate workstation's 110 address map. Many of the
110 ports have an industry-standard assignment. Recognition of that assignment does not indicate that the device is present in the workstation.
Table 2-2

Input/Output Address Map

From

Device

Description

OOOOH

001FH

8237A-5

DMA controller

0020H

003FH

8259A

Interrupt controller #1

0040H

005FH

8254-2

Timer

0060H

006FH

8042

Keyboard interface controller

0070H

Bit 7 controls the NMI mask register

0070H

0077H

MC146818

Real-time clock and CMOS RAM

0078H

007FH

0080H

009FH

74LS670

DMA page registers

OOAOH

OOBFH

8259A

Interrupt controller #2

OOCOH

OODFH

Reserved

OOEOH

OOEFH

Unassigned

Reserved

OOFOH

Clear math coprocessor busy

OOFIH

Reset math coprocessor

OOF2H

00F7H

00F8H

OOFFH

0100H

01EFH

OlFOH

01F8H

01F9H

OlFFH

Unassigned

0200H

0207H

Game port 110

0208H

0277H

Unassigned

0278H

027FH

Parallel printer port #2

0280H

02F7H

Unassigned

02F8H

02FFH

2- 4

Unassigned
80287

Math coprocessor
Unassigned

WD2010

8250

VAXmate Microprocessor

Hard disk controller

Serial port #2 Untegral modem option'

Table 2-2

Input/Output Address Map (cont.)

From

0300H

031FH

Reserved

0320H

035FH

Unassigned

0360H

036FH

Reserved

0370H

0377H

Unassigned

0378H

037FH

Parallel printer port 111

0380H

038FH

Reserved

0390H

039FH

Unassigned

03AOH

03AFH

Reserved

03BOH

03BFH

Reserved

03COH

03CFH

Reserved

03DOH

03DFH

03EOH

03EFH

03FOH

03F5H

03F6H

03F7H

03F8H

03FFH

0400H

OBFFH

Unassigned *

OCOOH

OC1FH

System CSR 1

OC20H

OC3FH

Ethernet ROM

OC40H

OC5FH

OC60H

OC7FH

Device

6845

Description

Graphics video controller
Unassigned

PD765A

Diskette controller
Hard disk and diskette controllers

8250

2661

Serial port 111

Universal Asynchronous Receiver/
Transmitter (UART) for mouse port
Network Controller and Interface

OC80H

Special purpose register

OC81H

OC9FH

OCAOH

OCA7H

OCA8H

ODFFH

Reserved

OEOOH

FFFFH

Unassigned *

Reserved
8250

Integral serial printer port

* Industry-standard, processor-board, 110 ports in the address range OOOOHOOFFH respond to these 110 addresses. Therefore, 110 to the expansion
box in this address range is undefined.
VAXmate Microprocessor

2- 5

Interrupt Vector Map
Table 2-3 shows the VAXmate workstation's interrupts. The four columns in
Table 2-3 provide the following information:
• The interrupt column identifies the interrupt number in hexadecimal.
• The type column is interpreted as follows:
The letter E indicates a processor exception interrupt.
The letter H indicates a hardware interrupt.
The letter S indicates a software interrupt.
The letter P indicates that the interrupt vector space contains a
pointer to a parameter table or an application routine.
The letter N indicates that the vector has no assignment.
• The description column identifies the specific assignment of the interrupt
vector.
• The service column indicates whether or not the ROM BIOS services the
interrupt. During system startup, interrupt vectors that are not serviced
by the ROM BIOS are initialized to point to an interrupt return URET)
instruction, indicated by IRET. For information on ROM BIOS-serviced
software interrupts, see Chapter 15.

2- 6

VAXmate Microprocessor

Table 2-3

Interrupt Vector Map

Interrupt

Type

Description

Service

OOH

Divide by zero

IRET

01H

Single step

IRET

02H

NMI

ROM BIOS

03H

Breakpoint (Used by DEBUG)

IRET

04H

Overflow

IRET

05H

Print Screen function

ROM BIOS

06H-07H

Reserved

IRET

08H

Timer interrupt service (lRQO)

ROM BIOS

09H

Keyboard interrupt service (IRQl)

ROM BIOS

OAH

Reserved (lRQ2 interrupt from controller #2) IRET

OBH

Serial port #2 (Asynchronous) (modem
option) (IRQ3)

IRET

OCH

Serial port #1 (Asynchronous) (lRQ4)

ROM BIOS

ODH

Unassigned (lRQ5)

IRET

OEH

Diskette interrupt service (lRQ6)

ROM BIOS

OFH

Parallel printer port #1 (lRQ7)

IRET

10H

Video I/O

ROM BIOS

llH

Return configuration

ROM BIOS

12H

Return memory size

ROM BIOS

13H

Diskette and hard disk 110

ROM BIOS

14H

Asynchronous communications 110

ROM BIOS

15H

Extended ROM BIOS functions

ROM BIOS

16H

Keyboard 110

ROM BIOS

17H

Printer Output

ROM BIOS

18H

Invoke network boot/Maintenance Operation ROM BIOS
Protocol (MOP)

19H

Bootstrap

ROM BIOS

VAXmate Microprocessor

2- 7

Table 2·3

Interrupt Vector Map (cont.)

Interrupt

Type

Description

Service

1AH

Time of day

ROM BIOS

1BH

Keyboard BREAK vector

IRET

1CH

Timer tick vector

IRET

1DH

Video parameter table

ROM BIOS

1EH

Diskette parameter table

ROM BIOS

1FH

Graphics character table (Character codes
80H-FFH)

ROM BIOS

20H-3FH

Reserved for MS-DOS

IRET

40H

INT 13H redirect when hard disk in use

ROM BIOS

41H

Parameter table pointer for hard disk 0

ROM BIOS

42H-45H

Reserved

IRET

46H

Parameter table pointer for hard disk 1

ROM BIOS

47H-5FH

Reserved

IRET

60H-67H

Available for application or user program
interrupts

IRET

68H-6FH

Reserved for DECnet software

IRET

70H

Real time clock interrupt (lRQ8)

ROM BIOS

71H

Redirect to interrupt OAH - Old IRQ2
(IRQ9)

IRET

72H

Ethernet controller (IRQ10)

ROM BIOS

73H

Serial printer port (IRQll)

ROM BIOS

74H

Mouse port (lRQ12)

IRET

75H

80287 error (lRQ13)

ROM BIOS

76H

Hard disk controller (IRQ14)

ROM BIOS

77H

Unassigned (IRQ15)

IRET

78H-7FH

Unassigned

IRET

80H-FOH

Reserved

IRET

F1H-FFH

Unassigned

2- 8

VAXmate Microprocessor

Bus Timing and Structure
The 8 MHz clock rate results in a 125 ns processor cycle. Normal operation of
the 80286 CPU requires two processor cycles. With zero wait states, a read or
write cycle requires 250 ns.
There are three data bus structures:
• A 16-bit local bus
• An 8-bit expansion bus
• A 16-bit expansion bus

I6·Bit Local Bus
The local bus connects the CPU to on-board memory and on-board peripherals.
One wait state is added to local bus memory transfers, resulting in a 375 ns
bus cycle. Two wait states are added to local bus input/output (110) transfers,
resulting in a 500 ns bus cycle.
The RAM access time is 150 ns. The ROM access time is 250 ns.
NOTE
In assembly language programming, directing two or more contiguous 110 instructions at the same device may not provide
enough time for the device to respond. This is possible because
peripheral devices respond more slowly than the 80286 processor executes. A jump instruction consumes processor cycles and
clears the processor pre-fetch queue. Thus, jumps to successive
110 instructions provide the required response time. The C language I/O functions, commonly named inO and outO or illPO and
outsO, provide enough response time because they contain sufficient overhead in the calling sequence.

I6·Bit Expansion Bus
The 16-bit expansion bus supports word transfers to memory and I/O. One wait
state is automatically added, resulting in a 375 ns bus cycle.

8· Bit Expansion Bus
The 8-bit expansion bus supports byte and word transfers to memory and I/O.
Word transfers are controlled by hardware, which issues two sequential byte
transfers (low byte first and high byte second). Table 2-4 describes the bus
cycle times for all transfer types on the 8-bit expansion bus.
VAXmate Microprocessor

2- 9

Table 2-4

8-Bit Expansion Bus Transfer Times

Type

Size

Time

Wait States

Memory

Byte

750 ns

Memory

Word (two, 8-bit transfers)

1500 ns

110

Byte

1125 ns

110

Word (two, 8-bit transfers)

2250 ns

Expansion Box Technical Specifications
The VAXmate expansion box provides two expansion module slots. Each slot
accommodates a single expansion module. If a mother-daughter board is used
in one of the slots, then both slot areas will be used and it will not be possible
to add a second module. Table 2-5 shows the amperage (current) and wattage
values available for each slot. Each slot has an 8-bit and a 16-bit bus connector.
Figure 2-1 shows the pin numbers and signal names for the 8-bit and 16-bit
bus connector.
Table 2-5

Expansion Slot Power Ratings

Slot

+5.1V

+ 12.1V

-12.0V

-5.0V

Watts

OPT-1
OPT-2

1.300
1.300

0.100
0.100

9.540
9.540

Expansion Box Operating Ranges
Ambient Operating Temperature: 15 C (59 F) to 32 C (90 F)
Relative Humidity: 8% to 80%

2- 10

Vi\Xnlate ~icroprocessor

8-Bit Bus Connector

GROUND
Bl
RESET H
IB2
+SV
B3
IRQ9 H
B4
BS
-SV
DRQ2 H
B6
-12V
B7
OYS L
B8
+12V
B9
GROUND
IBlO
HEKV L
IB11
HEHR L
B12
lOY L
IB13
lOR L
B14
DACK3 L
BlS
DRQ3 H
B16
DACKI L
B17
DRQ1 H
B18
REFRESH L B19
CLOCK H
B20
IRQ7 H
B21
IRQ6 H
B22
IRQS H
B23
IRQ4 H
B24
IRQ3 H
B2S
DACK2 L
B26
TIC H
B27
ALE H
B28
+SV
B29
OSC H
B30
GROUND
B31

Al
A2
A3
A4
AS

A6
A7
A8
A9
A10
All
A12
A13
A14
A1S
A16
A17
A18
A19
A20
A2l
A22
A23
A24
A2S
A26
A27
A28
A29
A30
A3l

16-Bit Bus Connector

I/O CHK L
SD7 H
SD6 H
SDS H
SD4 H
SD3 H
SD2 H
SDI H
SDO H
I/O RDY H
AEN H
SA19 H
SA18 H
SA17 H
SA16 H
SA1S H
SA14 H
SA13 H
SA12 H
SAll H
SAlO H
SA9 H
SA8 H
SA7 H
SA6 H
SAS H
SA4 H
SA3 H
SA2 H
SAl H
SAO H

Figure 2-1

01
HEH16 L
I/016 L
D2
IRQlO H
D3
IRQll H
D4
IRQ12 H
DS
IRQlS H
D6
IRQ14 H
D7
D8
DACKO L
DRQO H
D9
DACKS L ** DlO
DRQS H ** Dll
DACK6 L ** D12
DRQ6 H ** D13
DACK7 L ** D14
DRQ7 H ** DIS
016
+SV
KASTER L D17
018
GROUND

C1
C2
C3
C4
CS
C6
C7
C8
C9
ClO
Cll
C12
C13
C14
CIS
C16
C17
C18

SBHE L
UA23 H
UA22 H
UA2l H
UA20 H
UA19 H
UA18 H
UA17 H
EHEHR L
EHEKV L
SD08 H
SD09 H
SDlO H
SDll H
SD12 H
SD13 H
SD14 H
SD15 H

** Not Implemented

8-Bit and 16-Bit Bus Connectors

VAXmate Microprocessor

2 - 11

Chapter 3
Interrupt Controllers
Overview
The VAXmate 80286 central processing unit (CPU) has two interrupt input
lines, the Non-Maskable Interrupt (NMI) and the Interrupt Request (lNTRI.
When these hardware inputs are active, the CPU suspends execution of the
current program and begins execution of an interrupt handler. An interrupt
handler is a program or program segment that responds to a specific event.
This allows an immediate response to asynchronous external events and the
segregation of program responsibility for handling those events.
The interrupt input lines are assigned to different classes of events. The NMI
is dedicated to two catastrophic events, memory parity errors and 110 bus
errors. The INTR is assigned all other external interrupt sources, such as
diskette and hard disk controllers, serial and parallel ports, and clocks. The
reason for this division is the way the CPU implements the two interrupts:
• The NMI has a higher priority than the INTR.
• The CPU has no way to disable the NMI input.
• The CPU provides handshaking protocol during INTR processing, but not
during NMI processing.
• The NMI generates only one interrupt vector, which is fixed.
Because the CPU does not provide handshaking during NMI processing, the
CPU cannot communicate with an interrupt controller. Therefore, the NMI
sources are connected directly to the NMI input. To determine the source of
the interrupt, the NMI interrupt handler must read the status output of the
sources.

Interrupt Controllers - Hardware Description

3- 1

The INTR input is buffered by two, 8259A interrupt controllers. The interrupt
controllers reduce the CPU interrupt processing overhead in the following
ways:
• They resolve the priority of simultaneous or overlapping interrupts.
• They concentrate multiple interrupts into one source.
• They provide the vector number of the interrupt handler.
Each interrupt controller is capable of handling eight interrupt requests. The
16 inputs are labeled IRQO-IRQI5. Controller 1 buffers IRQO-IRQ7 and controller 2 buffers IRQ8-IRQI5. Although they are physically identical, the interrupt
controllers have a master/slave relationship. The output of controller 2 Ithe
slave) is connected to the IRQ2 input of controller 1 (the master). The output
of the master is connected to the INTR input of the CPU. Table 3-1 shows all
of the IRQ inputs.
Table 3-1
Priority

Interrupt Request Lines
Controller
#l MASTER

Controller
#2 SLAVE

Source

IRQO

Event timer output 0

IRQl

Keyboard controller

IRQ2

Slave interrupt controller

3.1

IRQ8

Real-time clock

3.2

IRQ9

Software redirection to IRQ2

3.3

IRQIO

LANCE (Ethernet)

3.4

IRQl1

Serial printer port

3.5

IRQI2

Mouse port

3.6

IRQI3

Coprocessor error

3.7

IRQI4

Hard disk drive controller

3.8

IRQI5

Available, I6-bit bus

IRQ3

Reserved, integral modem option

IRQ4

Asynchronous communications port

IRQ5

Available, 8-bit bus

IRQ6

Diskette drive controller

IRQ7

Available, 8-bit bus

3- 2

Interrupt Controllers - Hardware Description

Additional Source of Information
The following Intel Corporation document provides additional information:
•

Microsystem Components Handbook (Publication Number 230843)

Read/Write Control
The 8259A interrupt controller has the following registers:
Initialization Command Words (lCW) - There are four initialization command words (lCW1-ICW4). They establish the operating conditions of the
interrupt controller and are written only during system initialization.
Operation Command Words (OCW) - There are three operational command
words (OCW1-OCW3). These registers select access to internal controller
registers and control the run-time aspects of the interrupt controller.
Interrupt Mask Register (IMR) - The IMR selectively enables and disables
the interrupt controller's interrupt input lines. In this manual, IMR refers to
the physical register and OCWl refers to the command to read or write the
interrupt mask register.
Interrupt Request Register (IRR) - Following a CPU interrupt acknowledge,
each bit in the IRR reflects the state of the corresponding interrupt input.
In-Service Register (lSR) - The ISR register indicates the interrupt input
lines that the CPU is currently servicing.
Poll data - The poll data indicates whether any enabled interrupt inputs are
active. If any enabled interrupt inputs are active, it also contains the interrupt input number of the highest priority input requesting service.
Although the 8259A interrupt controller has many registers, it has only two
input/output (110) ports. Table 3-2 shows the master and slave 110 port addresses. Table 3-3 shows the registers and the requirements to access them.
Table 3-2

Master and Slave 110 Addresses

Port

Master

Slave

0020H

OOAOH

0021H

00A1H

Interrupt Controllers - Hardware Description

3- 3

Table 3-3

Accessing the Interrupt Controller Registers

R/W Port

Access Method

ICW1

When bit 4 of the value written to port 0 equals 1,
ICW1 is selected.

ICW2

Must be the next byte written after ICW1.

ICW3

The interrupt controller expects ICW3 only if ICW1,
bit 1 equals 1. If written. ICW3 must be the next
byte written after ICW2.

ICW4

The interrupt controller expects ICW4 only if ICW1.
bit 0 equals 1. If ICW 4 is written and ICW3 is not.
ICW4 must be the next byte written after ICW2. If
ICW3 and ICW4 are written, ICW4 must be the
next byte written after ICW3.

OCW1

R/W 1

Reading or writing OCW1 requires only that the initialization process be complete. Reading or writing
OCW1 accesses the interrupt mask register.

OCW2

Writing OCW2 requires that the initialization process be complete and OCW2 bits 4-3 are equal to O.

OCW3

Writing OCW3 requires that the initialization process be complete, OCW3 bit 4 equals 0, and OCW3
bit 3 equals 1.

IRR

Reading the IRR is a two-step process. First, issue
the read IRR command (write OCW3 with OCW3
bit 1 equals 1 and OCW3 bit 0 equals 01. Then, read
the IRR through port O. Until another command is
written to OCW3. subsequent reads of port 0 return
the IRR.

ISR

Reading the ISR is a two-step process. First. issue
the read ISR command (write OCW3 with OCW3
bit 1 equals 1 and OCW3 bit 0 equals 11. Then. read
the ISR through port O. Until another command is
written to OCW3. subsequent reads of port 0 return
the ISR.

Poll Data

Reading the poll data is a two-step process. First,
issue the read poll data command (write OCW3 with
OCW3 bit 2 equals 11. Then. read the poll data
through port O. The OCW3 poll command must
always be written prior to reading the poll data.

3- 4

Interrupt Controllers - Hardware Description

Initialization Command Words
The 8259A interrupt controllers do not have a hardware reset. After power is
applied to the system and until they are initialized, the interrupt controllers are
in an undefined state. The VAXmate startup code initializes the interrupt
controllers.
Initializing the 8259A interrupt controller requires from two to four initialization command words written in sequence.
The interrupt controller recognizes ICW1 as the start of an initialization sequence. An ICW1 resets the interrupt controller as follows:
1.

The trigger mode is cleared to edge-triggered mode and the edge sense
circuit is reset. After initialization, an interrupt request input must make
a low-to-high transition to generate an interrupt.

All bits in the IMR are cleared (enabled). Because the initialization sequence enables interrupt inputs, on completion of the initialization sequence, the interrupt controllers can immediately issue interrupt
requests. Therefore, the interrupt vectors and handlers should be initialized prior to initializing the interrupt controllers.

The IRQ7 input is assigned priority 7.

The slave mode address is set to 7.

If ICW1 bit 0 equals 0, all bits in ICW 4 are cleared (0).

In the OCW3 register, the special mask mode is cleared (disabled) and
status read bits are set to read the IRR.

The interrupt controller enters fully nested mode. All other modes of operation are variations of this mode. In fully nested mode, the interrupt
inputs have a fixed order of decreasing priority and the priority of an
input corresponds to its input number 0 (highest) - 7 (lowest). While the
CPU is servicing an interrupt (until the interrupt controller receives an
end-of-interrupt command), the controller inhibits interrupts of equal or
lower priority. However, the current interrupt service can be nested in
favor of a higher priority interrupt as follows:
The higher priority interrupt input must be unmasked (enabled).
The CPU INTR input must be enabled (STI instruction).
NOTE
The 8259A interrupt controller is compatible with two
microprocessor families, 8080/8085 and 8088/8086/80286.
Because the VAXmate CPU is an 80286. this manual describes
only the 80286 application. Those bits dedicated to the 8080/
8085 family are unused and described only as belonging to the
8080/8085 family.
Interrupt Controllers - Hardware Description

3- 5

The 8259A interrupt controller has the following mutually exclusive methods of
indicating whether an interrupt controller is a master or a slave:
• The initialization sequence selects non buffered mode in
ICW4. In nonbuffered mode, a hardware connection to the
SP/EN pin determines whether the controller is a master
or a slave. In this mode, a high level at the SP/EN pin
indicates a master and a low level at the SP/EN pin indicates a slave. The VAXmate workstation uses this method.
• The initialization sequence selects a buffered master or a
buffered slave in ICW4.

3- 6

Interrupt Controllers - Hardware Description

Initialization Command Word 1 (OO20H/OOAOH)
7

HODE
0

SINGLEI ICV4
CASCADE REQUEST

TRIGGER

Bit

RIW Description

7-5

Always 0 (These bits are used only by the 8080/8085 CPU family.)

Always 1
For values written to port 0, this bit distinguishes an leWl from
operational command words 2 and 3. For additional information,
see Table 3-3.

TRIGGER MODE
0= Edge-triggered mode
1 = Level-triggered mode
For either trigger mode, a low-to-high transition at an interrupt
input generates an interrupt request. In edge-triggered mode, to
generate another interrupt request at the same input, the input
must change from high to low and back to high. In level-triggered
mode, while that interrupt input remains high, the controller can
generate additional interrupt requests for that input. The
VAXmate startup code initializes the interrupt controllers to edgetriggered mode.

Always 0 (This bit is used only by the 8080/8085 CPU family.)

SINGLE/CASCADE
0= Cascade mode
1 = Single mode
Single mode indicates that this is the only interrupt controller in
the system. Therefore, it is neither a master nor a slave and ICW3
is not written,' Cascade mode indicates that there is more than one
interrupt controller in the system. Therefore, it is either a master
or a slave and ICW3 is required. The VAXmate workstation uses
cascade mode.

ICW4 REQUEST
0= ICW4 is not required
1 = ICW4 is required
This bit indicates whether ICW4 is required in the initialization sequence. The VAXmate workstation requires ICW 4.

For the master ICWl and the slave ICWl, use llH.
Interrupt Controllers - Hardware Description

3- 7

Initialization Command Word 2 (002 1H/OOAl H)
7

I I I I I I I I
17

Bit

RIW Description

7-3

o
0

Bits 7-3 of the interrupt number for interrupt input O.
This value corresponds to the address of the interrupt vector divided by four. The interrupt controller generates a sequential interrupt number for each of the interrupt inputs by ORing the
interrupt input number and ICW2. Because the interrupt input
number is OBed to the value in ICW2, there is no carry involved.
Therefore, the value in ICW2 must be evenly divisible by 8
Imodulo 8).

2-0

Always 0

For the master ICW2, use 08H. For the slave ICW2, use 70H.

3- 8

Interrupt Controllers - Hardware Description

Initialization Command Word 3 (002 1H/OOAl H)
When there are two or more interrupt controllers in the system, an ICW3 is
used in the initialization sequence. The VAXmate workstation has two interrupt
controllers and requires ICW3. The meaning and use of ICW3 depends on
whether the interrupt controller is a master or a slave.

ICW3 (Master)
7

I I I I I I I I I
57

Bit

RIW Description

7-0

For each master interrupt input that is connected to a slave, the
corresponding ICW3 bit is set (1). The master interrupt controller
can then determine which interrupt inputs require a slave identification on the cascade lines. For the master ICW3, use 04H.

ICW3 (Slave)
6

Bit

R/W Description

7-3

Always 0

2-0

SLAVE ID - Slave Identification

The slave identification is the master interrupt input (7-0) to which
the slave is connected. During the CPU interrupt acknowledge sequence, the slave compares its cascade input to these bits. If they
are equal, the slave places the interrupt vector number on the 110
data bus. For the slave ICW3, use 02H.
Interrupt Controllers - Hardware Description

3- 9

Initialization Command Word 4 (0021H/OOA1H)
6

0
Bit

RIW Description

7-5

3-2

MASTERI
SLAVE

EOI
MODE

CPU
MODE

SPECIAL
FULLY
BUFFER
NESTED MODE
MODE

Always 0
SPECIAL-FULLY-NESTED MODE *
Disable special-fully-nested mode
1 = Enable special-fully-nested mode

BUFFERED MODE and MASTERISLAVE
OX = Nonbuffered mode - In nonbuffered mode, a hardware connection to the SP/EN pin determines whether the controller is a master or a slave and bit 2, the master/slave
selection, has no effect. In this mode, a high level at the
SP/EN pin indicates a master and a low level at the SP/
EN pin indicates a slave. The VAXmate workstation uses
this mode.
10 =
Buffered mode slave - The VAXmate workstation is incapable of operating in this mode.
11 = Buffered mode master - The VAXmate workstation is incapable of operating in this mode.
EOI MODE - End-of-interrupt Mode
Normal EOI - In this mode, the CPU must write an EOI
command to the interrupt controller. The VAXmate startup
code initializes the interrupt controller to normal EOI mode.
The EOI command is explained in the operation command
word 2 description.
1 = Automatic EOI - In automatic EOI mode, the interrupt controller generates its own EOI on the second acknowledge
pulse.

CPU MODE
8080/8085 microprocessor family
1 = 8088/8086/80286 microprocessor family

The VAXmate workstation uses the 80286 CPU mode.

3- 10

Special-fully-nested mode is for master interrupt controllers. For the
master interrupt controller, each slave controller is a single interrupt
input. Thus, the master controller cannot resolve the priority of the slave
controller interrupt inputs. If a slave controller has an active, low priority interrupt that is nested in favor of a higher priority interrupt, the
master inhibits the new slave interrupt request. This effectively disables
Interrupt Controllers - Hardware Description

nesting of slave interrupts. In special-fully-nested mode, the master interrupt controller acts on all slave interrupt requests, which allows the slave
to nest interrupts. The VAXmate workstation startup code disables the
special-fully-nested mode.
For the master ICW4 and the slave ICW4, use OlH.

Operation Command Words
The interrupt controller provides three operation command words (1-31 that are
programmed after the initialization sequence is complete. The operation command words select various modes or operations as follows:
•
•
•
•
•
•
•
•

Read or write the interrupt mask register
Accept specific or nonspecific end-of-interrupt commands
Enable or disable various automatic priority rotation schemes
Set a specific priority level
Set or reset the special mask
Read poll data
Read the interrupt request register
Read the in-service register

Operation Command Word 1 (002 1H/OOAl H)
7

I : : :

: : : I

Bit

R/W Description

7-0

R/W Interrupt mask register bits
o = Corresponding interrupt inputs are unmasked (enabledl
1 = Corresponding interrupt inputs are masked {disabledI

OCWI reads or writes the interrupt mask register {IMRI. Each bit in the IMR
enables or disables the corresponding interrupt input.

Interrupt Controllers - Hardware Description

3- 11

Operation Command Word 2 (0020H/OOAOH)
6

'ROTATE' SL , EO! , 0 , 0 ,

~uPT ~L ,

Bit

R/W Description

7-5

ROT ATE/SLlEOI
000 = Disable rotation in automatic EOI mode
001 = Nonspecific end-of-interrupt (EOI)
010 = No operation
011 = Specific end-of-interrupt
100 = Enable priority rotation in automatic EOI mode
101 = Rotate priority on nonspecific EOI
110 = Rotate priority to specific interrupt input
111 = Rotate priority on specific EOI

Always 0
For values written to port O. this bit distinguishes operational command words 2 and 3 from an lew!. See Table 3-3.

Always 0
This bit distinguishes OeW2 from OeW3. See Table 3-3.

2-0

INTERRUPT LEVEL
For interrupt-specific operations, these bits contain the interrupt
input number (0-7) to act on. For nonspecific operations, these bits
are ignored.

oeW2 issues an end-of-interrupt command or sets a priority rotation mode.
Some OeW2 operations are nonspecific. (They act on the interrupt input that
has the highest priority, whichever one that may be.) Non-specific commands
do not use INTERRUPT LEVEL (OeW2 bits 2-0). Specific OeW2 operations
require the interrupt input number (0-7) in INTERRUPT LEVEL.
For the master OeW2 and the slave OeW2, use 20H (nonspecific EOI
command).

3- 12

Interrupt Controllers - Hardware Description

Priority Rotation
In nonspecific or automatic EOI mode, priority rotation has the effect of
assigning equal priorities to all interrupt inputs. On receipt of an EOI command, the interrupt controller assumes that the active interrupt input with the
highest priority is the interrupt just completed. The priority bits are rotated
until the just completed interrupt has the lowest priority (7). If that interrupt
input requires further service, it must wait until it is again the highest priority
interrupt or until all interrupts of higher priority are inactive.
In Figure 3-1, interrupt inputs 2, 5, and 6 are requesting service and interrupt
input 2 has a higher priority than interrupt inputs 5 and 6. After interrupt
input 2 is serviced, the interrupt controller rotates the priority as shown in
Figure 3-2. In Figure 3-2, interrupt input 3 has the highest priority, but it is
inactive. Because interrupt input 5 has the highest priority of the active interrupts, it is the next interrupt input serviced.
Rotating priorities to a specific interrupt input is another method of priority
rotation. In this method, the lowest priority is set, thereby fixing all other
priorities. For example, if interrupt input 2 is programmed as the lowest priority, then interrupt input 3 becomes the highest. OCW2 bits 2-0 define the interrupt input number that is assigned the lowest priority. This method is not
used in the VAXmate workstation startup code.

Interrupt Controllers - Hardware Description

3- 13

In-Service Bits

101111 101011 10

I0 I

Priority Status

I I I I I I I 1 101
7

Figure 3-1

Priority Before Rotation

In-Service Bits

10111 1

I 0 I 0 I 0 101 0 I

Priority Status
7

Figure 3-2

3 - 14

Priority After Rotation

Interrupt Controllers - Hardware Description

Operation Command Word 3 (OO20H/OOAOH)
6

SPECIAL
SPECIAL MASK
MASK
HODE
HODE

POLL

READ
IR REG

READ
IS REG

ENABLE

Bit

R/W Description

Always 0

6-5

ENABLE SPECIAL MASK MODE/SPECIAL MASK MODE
00 = No action
01 = No action
10 = Disable special mask mode
11 = Enable special mask mode
Some operations require that an interrupt service routine dynamically change the priority structure. Masking an interrupt input in
the special mask inhibits that priority level and enables all other
priority levels (lower and higher I that are unmasked. After enabling
special mask mode, the special mask is read or written to the
IMR.

Always 0
For values written to port 0, this bit distinguishes operational command words 2 and 3 from an ICWl. See Table 3-3.

Always 1
This bit distinguishes OCW3 from OCW2. See Table 3-;,.

2-0

POLL/READ IR REG/READ IS REG
000 = No action
001 = No action
010 = Read the IRR. *
011 = Read the ISR. *
100 = Read the poll data. **
101 = Read the poll data. **
110 = Read the poll data. **
111 = Read the poll data. **

*
**

See Table 3-3 and the IRRIISR description.
See Table 3-3 and the poll command description.

For standard operation of the VAXmate workstation, neither the master nor
the slave use OCW3.
Interrupt Controllers - Hardware Description

3- 15

Interrupt Request and In-Service Registers
Interrupt Request Register
7

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQl

IRQO

In-Service Register
7

I I I I I I I I
IS7

IS6

ISS

IS4

IS3

IS2

IS!

ISO

The Interrupt Request Register (lRR) and the In-Service Register (lSR) maintain the state of the interrupt controller. During the first interrupt acknowledge
of the CPU interrupt acknowledge sequence, the IRR latches the state of the
interrupt input lines. The internal output of the Interrupt Mask Register (lMR)
gates the output of the IRR to the priority encoder. Assuming that one or
more IRR bits are set (active) and unmasked (enabled), the priority encoder determines which one has the highest priority. During the second interrupt acknowledge, that IRR bit is strobed into the corresponding ISR bit, the edge
sense circuitry for that interrupt input is reset, and the interrupt vector
number is placed on the I/O data bus.
Because the interrupt controller can nest interrupts, the ISR can contain one,
two, or more bits that are set. This shows that another interrupt was acknowledged before other interrupt processing was completed. A specific end-ofinterrupt (EOI) clears the indicated ISR bit. A nonspecific EOI clears the
highest-priority ISR bit.
If an IRR bit is set (active) and masked (disabled), unmasking (enabling) that
active IRR bit creates an interrupt.

3- 16

Interrupt Controllers - Hardware Description

Poll Command
When issued, the poll command performs steps similar to those described in
the IRR/ISR description. The poll command replaces the function of the CPU
interrupt acknowledge sequence. Instead of placing the interrupt vector number
on the I/O data bus, the poll command connects the output of the poll data
register to the port 0 output buffer. The polling interrupt handler then reads
the poll data to determine if an interrupt input is active and, if so, which one.
To complete the interrupt sequence, the polling interrupt handler must issue an
EOI.

Poll Data Register
6

Bit

Description

6-3

Always 0

2-0

INTERRUPT INPUT NUMBER

INT ACTIVE FLAG - Interrupt active flag
No active interrupt inputs
1 = At least one interrupt input is active

If bit 7 equals 1, these bits contain the interrupt input number (07) of the highest priority interrupt input that is active. If bit 7
equals 0, these bits have no meaning.

Interrupt Controllers - Hardware Description

3- 17

Interrupt Sequence
The following list describes interrupt processing. Each item in the list describes
a system state or event. After a discussion of the state or event, the description indicates the next state or event. For the following interrupt processing
description, it is assumed that the interrupt controllers are initialized as previously described. Later, Figure 3-3 shows the same logic in the form of a flow
chart.
1.

Until one or more interrupt controller input lines become active, the controller is idle. If one or more inputs are active, go to 2.

If any of the newly active inputs are unmasked (enabled), go to 4.

Otherwise, go to 3.
3.

If other interrupt inputs are pending, go to 5. Otherwise, go to 1.

If no other interrupt inputs are pending, go to 7. Otherwise, go to 6.

If the controller is waiting for an end-of-interrupt command, go to 6.

Otherwise, go to 7.
6.

If any interrupt has a priority higher than the one being processed by
the CPU, nest the interrupts and go to 7. Otherwise, go to 8.

The controller activates its interrupt output line and waits for an acknowledge signal from the CPU.
If the interrupt controller input is a slave input. then the slave interrupt
output line activates the master interrupt controller IRQ2 interrupt
input. The master interrupt process starts at step 2. Eventually, the
master IRQ2 input becomes the highest priority master interrupt that is
active and the master controller arrives at this step. At that time, both
controllers are waiting for the CPU acknowledge signal.

In either case, the master interrupt controller activates its interrupt
output line, which triggers an external latch. The external latch drives
the CPU INTR input.
NOTE
This external latch, between the master interrupt controller interrupt output and the CPU INTR input, was incorporated due
to an advisory on an 80286 CPU design flaw.
Disabling the CPU INTR input before disabling an interrupt
controller input or initializing the interrupt controllers can leave
the latch set. On reenabling the CPU INTR input. the latch
could indicate an interrupt request when none exists.
To avoid this situation, disable the interrupt controller input or
write the first master interrupt controller initialization command
before disabling the CPU INTR input.
3- 18

Interrupt Controllers - Hardware Description

If the CPU INTR input is disabled, the interrupt controller continues to
wait. If other interrupt controller inputs become active during this waiting
period, go to 2. When the CPU INTR input is enabled, the CPU recognizes the interrupt request and responds with an acknowledge signal.
On receiving the acknowledge, the interrupt controller sets the highest
priority bit in the in-service register and resets the corresponding bit in
the interrupt request register. This allows the controller to recognize another interrupt request at that interrupt controller input.

The CPU issues a second acknowledge signal. When the master interrupt
controller recognizes the second acknowledge signal, it determines
whether the interrupt input source is a slave interrupt controller. If the
interrupt input source is not a slave, the master controller places a
preprogrammed 8-bit interrupt vector on the input/output (I/O~ data bus.
If the interrupt input source is a slave, the master controller places the
slave address (master interrupt input number 0-7~ on the cascade lines.
When enabled by the slave address on the cascade lines, the slave places
the preprogrammed 8-bit interrupt vector on the input/output (I/O) data
bus. In either case, the CPU reads the 8-bit interrupt vector, stacks the
current state and begins executing the interrupt handler that is pointed
to by the contents of the interrupt vector.
8. The interrupt controller(s) are waiting for an end-of-interrupt (EOl) command. When a slave interrupt is processed, an EOI command is required
by both the slave and the master.
If an interrupt occurs during this waiting period, go to step 2. When the
CPU writes the end-of-interrupt command, go to step 1.

Interrupt Controllers - Hardware Description

3- 19

INTERRUPT
r----l~ CONTROLLER

IS IDLE

ISR&IRR
NEST
INTERRUPTS

ACTIVATE
INTERRUPT
OUTPUT

SET ISR
RESETIRR

ICW3
SLAVE
RESPONDS
>-------~ TO CASCADE
ADDRESS
ICW3

ISR & ICW2
SLAVE PUTS
8-BIT VECTOR
ON I/O BUS

SLAVE IS
WAITING
FOR EOI

LJ-1309

Figure 3·3
3- 20

Interrupt Sequence

Interrupt Controllers· Hardware Description

Programming Example
The following programming examples demonstrate:
• Initializing a master or slave 8259A peripheral interrupt controller (PIC)
• Programming the PIC interrupt mask register
• Issuing end-of-interrupt commands to a master or slave PIC
The example provides routines as described in the following:
pic_init

Initializes the master and slave PICs.

imask

Masks or unmasks the specified bit in the interrupt mask
register.

eoi

Issues an end-of-interrupt command to the appropriate PICs.
CAUTION
Improper programming or improper operation of this device can
cause the VAXmate workstation to malfunction. The scope of
the programming example is limited to the context provided in
this manual. No other use is intended.

Interrupt Controllers - Programming Example

3- 21

Constant Values and Data Structures
The constant value NPIC defines the number of peripheral interrupt controllers
in the VAXmate workstation.
The constant value EOI defines the bit value that must be issued to OCW2 to
establish an end-of-interrupt condition.
The structure type PIC defines the input/output ports of the 8259A peripheral
interrupt controller (PIC). These two ports access the PIC registers. The bit
values written to registers and the read or write sequence determine the accessed register.
The structure type PIC DAT defines the type of data required to initialize a
PIC.
-

Initialization Data
The array of structures allpies provides the actual data for initializing the
master and slave PIes. Later, references to the PIC number refer to the position of an element in the array allpies.

3- 22

Interrupt Controllers - Programming Example

1***********************************************************************1
1* define constants and structures used in 8259 PIC example
*1
1***********************************************************************1
#define NPIC 2
#define EOI Ox20

1* number of pics in system *1
1* bit value of EOI cOlllllland *1

typedef struct

1* define pic liD structure *1

{

1* when address line AO • o *1
1* when address line AO ... 1 *1

unsigned char portO;
unsigned char port1;
} PIC;
typedef struct
{

1* base liD address of pic *1
1* modulo 8 base int vector *1
1* ir has a slave or slave id *1
1* icw4 mode data *1

PIC *base;
char icw2;
char icw3;
char icw4;
} PIC_OAT;

1***********************************************************************1
1* define pic initialization data
*1
1***********************************************************************1
PIC_OAT allpics[NPIC]

1* device data tables *1

{
{

(PIC *)OxOO20, Ox08, Ox04, Ox01 },

{ (PIC *)OxOOaO, Ox70, Ox02, Ox01 },

1* pic 0 is the master *1
1* pic 1 is the slave *1

};

Interrupt Controllers - Programming Example

3- 23

Initializing the Peripheral Interrupt Controller
The function pic init initializes the master and slave PICs. Because the ROM
BIOS startup sequence initializes the peripheral interrupt controllers (PICI, initialization of the PICs is not normally required.
Because the initialization sequence clears the interrupt mask register, the CPU
interrupt flag is cleared after the initialization is started and before the initialization is complete. Thus, no interrupts are pending when the initialization is
started an~ the CPU will not respond to any interrupts that become active
during the initialization sequence.
The first two instructions write a value to port 0 of the indicated PIC. The
value of bit 4 is key to this operation. Writing a value to port 0, with bit 4 set,
selects the ICWI register and indicates a reset sequence. The PIC stores the
remaining ICWI bits in the ICWI register, which starts the initialization
sequence.
• Bit 0 is set, indicating that the initialization sequence includes ICW 4.
•

Bit 1 is clear, indicating that the addressed PIC is involved in a cascade
(master/slave1 arrangement and that ICW3 must be written during the initialization sequence. That is, the PIC is not operating in a standalone
environment.

•

Bit 3 is clear, indicating that the PIC is operating in edge-triggered mode.

• All other ICWI bits apply to the 8085 mode of operation and are not
used.
Because two PICs must be initialized. the rest of the initialization sequence is
performed within a for loop as follows:
1.

The first instruction initializes a pointer to the required data.

The second instruction initializes a pointer to the port 0 I/O address.

The third instruction writes the base interrupt vector to port 1. Because
this is the second value written in the sequence, the PIC routes the
value to ICW2.
This base interrupt vector refers to the interrupt vector for interrupt
input zero. To generate a unique interrupt vector number for each interrupt input, the PIC ORs the interrupt input number (0-71 and the base
interrupt vector number. Therefore, the base interrupt vector must be
modulo 8.

3 - 24

The fourth instruction is dependent upon whether the PIC is a master or
a slave. Because this is the third value written in the sequence and
ICWI indicated a cascade mode, the PIC routes the value to ICW3.
Interrupt Controllers - Programming Example

•

If the PIC is a master, each bit set in the value indicates that the

corresponding interrupt input is connected to a slave PIC. For the
VAXmate, only bit 2 is set.
• If the PIC is a slave, the value is the slave identification. The slave
identification is a value between 0 and 7 inclusive, and corresponds to
the master interrupt input to which it is connected.

/***********************************************************************/
*/

/* pic_init() - initialize master and slave pics

/***********************************************************************/
void pic_ini to

/* initialize all pics */

{

int i;
int intr31g;
register PIC_OAT *ppd;
register PIC *pps;

/* variable for loop control */
/* to hold CPU IF state */
/* pointer to PIC data */
/* pointer PIC I/O structure */

outp(allpics[O] .base, Oxll);
outp(allpics[l].base,Oxll);
intr_flg = int_off();
for(i = 0; i < NPIC; i++)

/* write master ICWl is cascade */
/* write slave ICWl is cascade */
/* turn CPU interrupts off */

{

ppd = lallpics[i];
pps = ppd->base;
outp(lpps->portl, ppd->icw2);
outp (lpps->port 1 , ppd->icw3);
outp (lpps->port 1 , ppd->icw4);
outp (lpps->port 1 , Oxff);

/* assign pointer to PIC data */
/* assign pointer to I/O ports */
/* write ICW2 */
/* write ICW3 */
/* write ICW4 */
/* mask all interrupts */

}

/* turn CPU interrupts on */
}

The fifth instruction writes the ICW4 value to port 1.
• Bit 0 determines the microprocessor family. In this case, it is set and
indicates the 8086/80286 mode.
• Bit 1 is clear, indicating that the interrupt handling routine issues an
end-of-interrupt command after the interrupt is processed.
• Bits 2 and 3 are clear, indicating the nonbuffered mode of operation.
For the VAXmate, a permanent hardware connection determines the
master/slave relationship.
• Bit 4 is clear, indicating that the PIC is not in special-fully-nested
mode.
• All other bits are not used and are clear.
Interrupt Controllers - Programming Example

3- 25

The sixth instruction masks fdisables) all interrupts. The interrupt inputs
must be unmasked before the PIC can generate an interrupt to the CPU.

To complete the initialization, the last instruction enables CPU interrupts.
Because the PIC interrupt mask is cleared during initialization, it is possible
that the PIC will recognize an active interrupt input between instructions 5 and
6. Before a PIC interrupt input is unmasked, an interrupt handler must be
available and the appropriate interrupt vector initialized.
A PIC interrupt input that is not active long enough to be latched is considered
a glitch. If a glitch occurs, the PIC generates an interrupt for IRQ7 fmaster) or
IRQ15 fslave). To determine whether an interrupt for IRQ7 or IRQ15 is a
glitch, test ISR bit 7 of the appropriate controller. If the ISR bit 7 is set, the
interrupt is a valid interrupt. If the ISR bit 7 is clear, the interrupt is a glitch.

Issuing an End-of-Interrupt Command
In fully nested mode (default mode), the PIC processes the highest priority interrupt that is pending. When the PIC receives a nonspecific end-of-interrupt
(EOI), it clears the highest priority bit that is set in the in-service register.
Until no interrupts are pending, the PIC continues by processing the highest
priority interrupt that is pending.
To allow the PIC to process the same interrupt or an interrupt of lower priority, the eoi function is called at the end of an interrupt handling sequence. The
calling parameter indicates which PIC issued the interrupt. If an interrupt is
issued by the slave PIC, an EOI must be issued to the slave and then to the
master.
During interrupt processing, it is possible for a higher priority interrupt to
become active. If this happens, the PIC attempts nesting the interrupts. For
the PIC to nest interrupts, the CPU interrupt request input must be enabled.
Otherwise, the CPU will not issue the required acknowledge sequence. During
the interrupt processing. the CPU automatically stacks its current state and
clears the interrupt enable flag. Because none of the interrupt handlers, in
these examples, enable the CPU interrupt request input, nesting of interrupts
is effectively disabled.

Masking Interrupts
The function imask masks or unmasks a bit in the interrupt mask register
(OCWl). The calling parameters indicate the PIC number, the bit number (0-7),
and whether the bit should be masked or unmasked.

3- 26

Interrupt Controllers - Programming Example

/***********************************************************************/
/* eoi() - establish End-Of-Interrupt for pic(s)

/***********************************************************************/
void eoi(pic)

/* send nonspecific E01 */

int pic;

/* which pic handled interrupt */

{

outp(l(allpics[pic] .base)->portO. EOI);
i f (pic)
outp(l(allpics[O] .base)->portO. EOI);

/* write eoi as indicated */
/* was it the slave pic 1 */
/* write eoi to master */

}

/***********************************************************************/
/* imask() - mask or unmask desired bit in pic mask register
*/
/***********************************************************************/

void imask(pic. bitno. enable)
int pic;
int bitno;
int enable;

/* set or clear bit in mask */
/* register of desired pic */
/* which pic 1 */
/* which bit ? */
/* enable or disable ? */

{

/* current contents of MR */
/* the mask to write */
/* pointer PIC I/O structure */

unsigned char current;
unsigned char mask;
register PIC *pps;
pps = allpics[pic] .base;
current = inp(lpps->portl);
mask = 1 « bitno;
if(enable) current l= -mask;
else current 1= mask;
outp(lpps->portl. current);

/* assign pointer to I/O ports */
/* read current mask */
/* set up correct bit */
/* clear the bit */
/* or set it */
/* write the resulting mask */

}

Interrupt Controllers - Programming Example

3- 27

Chapter 4
DMA Controller
Overview
The direct-memory-access (DMA) controller is an Intel 8237A-5, programmable,
DMA controller operating at 4 MHz. The DMA controller allows the direct
transfer of 8-bit data between DMA-capable, input/output (I/O) devices and
memory. The DMA controller has four, independent DMA channels. Table 4-1
lists the assignment of the four DMA request lines. Each channel has 16 address lines and an external 8-bit page register. Thus, each channel can transfer
a maximum of 64 Kbytes anywhere in the 16 Mbyte address range.
The following list shows the operational modes and restrictions of the DMA
controller.
Single transfer

This is the suggested mode of operation.

Block transfer

To prevent interference with DRAM refresh cycles,
limit block transfers to 8 transfers per block.

Demand transfer

To prevent interference with the DRAM refresh
cycle, limit demand transfers to 8 transfers per
demand.

Cascade

As bus master, the slave DMA controller should release the bus after 10 ps.

Compressed timing

Compressed timing is not supported by the processor
board hardware.

Memory to memory

Memory-to-memory transfers are not supported by
the processor hardware.

Extended write cycle

The extended-write cycle does not provide sufficient
data setup time. Use the normal DMA write cycle.

DMA Controller - Hardware Description

4- 1

Table 4-1

DMA Request Line Assignments

Channei

Request Line

Available
Available
Diskette Controller
Available

2
3

Additional Source of Information
The following Intel Corporation document provides additional information:
•

Microsystem Components Handbook (Publication Number 230843)

Operation
When the DMA controller receives a DMA request from a peripheral device,
the DMA controller sends a hold request signal to the CPU. When the CPU
responds with a hold acknowledge signal, the DMA controller takes control of
the 110 data bus, the system address bus, and the control bus. The controller
then generates a 16-bit memory address and activates the corresponding OMA
acknowledge line, the 110 read or write line, and the memory read or write line.
On seeing the DMA acknowledge, the OMA-capable 110 device transfers (reads
or writes) the data on the data bus. Thus, the data is transferred directly between the I/O device and memory.
The DMA controller operates in two major cycles, idle and active. Each DMA
cycle can assume seven, separate states. Each state is composed of one full,
clock period. Table 4-2 describes the various controller states.
Table 4-2

DMA Controller States

State

Description

This is the inactive state. No valid DMA requests are pending and the
CPU can program the DMA controller.

This is the first active state of DMA service. The controller has requested a CPU hold, but the CPU has not acknowledged a hold.
Programming of the DMA controller can continue until the acknowledge is received.

SI-S4

These are the DMA working states.

When more time is required to complete a transfer, wait states are
inserted between S2 and S3, or S3 and S4.

4- 2

DMA Controller - Hardware Description

Idle Cycle
When none of the I/O channels is requesting DMA service, the DMA controller
enters the idle cycle and performs SI states. At each clock cycle in the idle
cycle, the DMA controller samples the DMA request lines and the chip select
line.
If a DMA request line becomes active, the DMA controller goes to the active
state. Otherwise, if CPU has selected the DMA controller and the CPU has
control of the bus, the CPU can read or write the DMA controller internal
registers.

Active Cycle
When the DMA controller is in the idle cycle and a nonmasked channel
requests DMA service, the controller issues a hold request to the CPU and
enters the active cycle. The DMA service will then occur in one of the four
following modes.

Single Transfer Mode
The DMA controller is programmed to perform only one transfer in this .mode.
After the transfer, the word count is decremented and the address is either
decremented or incremented. When the word count goes from OOOOH to
FFFFH, a terminal count (Tel signal is generated, and will auto~initialize the
channel to its original condition if it had been programmed to do so.
The ROM BIOS uses this mode for data transfers between the diskette controller and memory.

Block Transfer Mode
In this mode, the DMA controller is activated by a DMA request to continue
making transfers until a TC (word count has reached FFFFH) or an external
end-of-process (EOP) signal occurs. If the channel has been programmed for
auto-initialization, the auto-initialization occurs at TC or EOP. This mode
should be limited to eight transfers (assuming no additional wait states) to prevent interference with refresh cycles.

Demand Transfer Mode
The DMA controller performs transfers until a TC or external EOP occurs, or
until there is no DMA request. Transfers may continue until the I/O device has
exhausted its data capacity. Once the I/O device has caught up, DMA service is
reestablished by means of a DMA request. The intermediate values of address
and word count are stored in DMA controller internal registers between services while the CPU is running. At the end of the service, only an EOP can
cause auto-initialization to occur. This mode should be limited to eight transfers
per demand to prevent interference with refresh cycles.
DMA Controller - Hardware. Description

4- 3

Cascade Mode
This mode is used when DMA controllers are cascaded for system expansion.
In this configuration, the initial controller determines the priority of the additional controllers. Each of the additional controllers establish priority within
themselves and make the DMA request to the initial controller. The initial controller does not output any address or control signals, since they could conflict
with the outputs of the added controller.

Data Transfers
The DMA controller can perform read, write, or verify operations in each
transfer mode. Read transfers move data from memory to an I/O device; write
transfers move data from an I/O device to memory; and verify transfers are
pseudo data transfers. In verify mode, the controller operates as if in read or
write mode, however the memory and 1/0 control lines are not active.
Memory-to-memory transfers are a special case of DMA transfer. Channel 0 is
the source and channel 1 is the target. In memory-to-memory transfers, channel 0 uses one cycle to read the data byte and store it in the temporary register. On the following cycle, channel 1 writes the value in the temporary
register to the target location.

Auto-Initialize
Restores the DMA channel to its original condition following an EOP. Autoinitialization is accomplished by restoring the original values of the Current
Address and Current Word Count registers from the Base Address and Base
Word Count registers. The CPU loads the current registers and base registers
which do not change during the DMA service. When the channel is in autoinitialize mode, the mask bit is not set. After auto-initialization and a receipt of
a DMA request, the channel can perform DMA service without CPU
intervention.

4- 4

DMA Controller - Hardware Description

Priority
The two types of priority, fixed and rotating, are defined as follows:
Fixed Priority

In fixed priority, the channels are placed in order based
on the descending value of their assigned number. The
assigned number range is from zero to three (0-3), with
zero as the highest priority.

Rotating Priority The channel being serviced is assigned lowest priority
value, and all others rotate to the next higher value.

Address Generation
The eight, high-order address bits (15-8) are multiplexed on the I/O data lines.
At the Sl state, the high-order 8-bits are output to an external latch and
placed on the system address bus. The low-order bits are output directly from
the DMA controller to the system address bus. For multiple transfers, such as
block and demand transfers, the addresses are generated sequentially. The data
in the external latch (high-order byte) can remain the same for many transfers,
and have to be changed only when a borrow or carry takes place in the normal
sequence of addresses. The controller executes Sl states only when updating of
the high-order byte is required.

DMA Controller - Hardware Description

4- 5

Table 4-3

DMA Controller and Page Register Address Map

Port

RIW

Channel

OOOOH

W
R

0
0

Base and Current address
Current address

OOOlH

W
R

0
0

Base and Current word count
Current word count

0OO2H

W
R

1
1

Base and Current address
Current address

0OO3H

W
R

1
1

Base and Current word count
Current word count

0OO4H

W
R

2
2

Base and Current address
Current address

0OO5H

W
R

2
2

Base and Current word count
Current word count

0OO6H

W
R

3
3

Base and Current address
Current address

0OO7H

W
R

3
3

Base and Current word count
Current word count

0OO8H

W
R

Command
Status

0OO9H

Request

OOOAH

Write single mask register bit

OOOBH

Mode register

OOOCH

W
R

Clear byte pointer flip/flop
Temporary

OOODH

Master clear

OOOEH

Clear mask register

OOOFH

Write all mask register bits

0080H

Channel 1 page register

0081H

Channel 2 page register

0082H

Channel 3 page register

0083H

Channel 0 page register

4- 6

DMA Controller - Hardware Description

Registers
The DMA controller has 16 110 ports to access 26 internal registers.
Additionally, the DMA circuitry has four 110 ports to access four page registers. Table 4-3 lists the 110 ports and the registers accessed.

Base and Current Address Register

(OOOOH/OOO2H/OOO4H/OOO6H)
7

:
:

~v B~ ~F _!S

READ OR VRI'ITEN FIRST

:
14

8r~ B~~OF ~ss

READ OR

:
10

VRI'ITEN SECOND

:
8

Each DMA channel has a I6-bit base address register and a I6-bit current address register. The base address register contains the initial value. Writing a
value to the base address register initializes the current address register to the
same value. The current address register is incremented or decremented after
each transfer. When the required number of transfers have occurred and if
auto-initialize (see the mode register) is enabled, the current register is initialized from the base register.
Before performing a I6-bit read or write, clear the byte pointer flip/flop.
To write a base register, write two, 8-bit bytes in succession to the same port.
To read a current register, read two, 8-bit bytes in succession to the same port.
In either case, the low byte is accessed first and then the high byte.

DMA Controller - Hardware Description

4- 7

Base and Current Word Register
(OOOlH/0003H/0005H/0007H)

:
15

:
14

~~ OF :~~WM
12

READ OR

VRITl'EN SECOND

8IGB:B~ OF:CURRENT:VORD

wvREAD OR VRITl'EN FIRST

Each DMA channel has a I6-bit base word count register and a I6-bit current
word count register. The value written to this register determines the number
of transfers performed. The number of transfers is the programmed value plus
one. The current word count is decremented after each transfer. When the current word count is decremented below zero (FFFFHl, a terminal count is generated. When the required number of transfers have occurred and if auto-initialize
(see the mode register) is enabled, the current register is initialized from the
base register.
Before performing a I6-bit read or write. clear the byte pointer flip/flop.
To write a base register, write two, 8-bit bytes in succession to the same port.
To read a current register, read two, 8-bit bytes in succession to the same port.
In either case, the low byte is accessed first and then the high byte.

4- 8

DMA Controller - Hardware Description

Command Register (0008H)
7

DACK
SENSE

DREQ
SENSE

VRITE
SELECT

TIMING

Bit

R/W Description

CHANNEL MEMORY
TO
0
ADDRESS MEMORY
BOLD

DACK SENSE - DMA Acknowledge Sense

o = DACK sense active low
"1 = DACK sense active high

DREQ SENSE - DMA Request Sense
DREQ sense active high
1 = DREQ sense active low

WRITE SELECT
Late write selected
1 = Extended write selected

For the VAXmate workstation, the extended write mode does not
provide an adequate write cycle. Use only the late write mode.
If bit 3 equals 1 (compressed mode), bit 5 is a don't care value.

However, the VAXmate workstation is not capable of using compressed mode.
4

PR - Priority
Fixed priority 0 (highest), 1, 2, and 3 (lowest)
1 = Rotating priority

Initially, the priority is the same order as in fixed priority. In the
rotating priority scheme. the currently serviced DMA channel becomes the lowest priority channel. However, the channels always
maintain their priority in numeric order. That is, the priority decreases as the channel number increases and wraps between channels 3 and O.

DMA Controller - Hardware Description

4- 9

Bit

RIW Description (Command Register - cont.)

TIMING

o = Normal read/write timing - A read/write cycle requires a

minimum of three clock cycles and is subject to wait states.
The VAXmate workstation uses this mode.
1 = Compressed read/write timing - A read/write cycle occurs in
two clock cycles. The VAXmate workstation is not capable of
using compressed mode.
If bit 0 equals 1 (memory-to-memory enabled), bit 3 (timing) is a
don't care value.

CE - Controller Enable

o = Controller disabled
1 =

Controller enabled

CHANNEL 0 ADDRESS HOLD

o = Disable channel 0 address hold
1 =

Enable channel 0 address hold

Channel 0 address hold causes the DMA controller to copy a single
byte to the specified number of destination bytes.
If bit 0 equals 0 (memory-to-meniory disabled), bit 1 (channel 0 address hold) is a don't care value.

MEMORY-TO-MEMORY

o = Memory-to-memory transfers disabled
1 = Memory-to-memory transfers enabled
The VAXmate workstation does not support memory-to-memory
transfers.

This 8-bit register controls the operation of the DMA controller. It is cleared by
a hardware reset or a master clear instruction.

4- 10

DMA Controller - Hardware Description

Write Single Mask Bit (OOOAH)
7

Bit

R/W Description

7-3

1-0

DON'T CARE (any value 1
MASK BIT
Enable the selected channel
1 = Disable the selected channel

CHANNEL SELECT
00 = Select channel 0 mask bit
01 =
Select channel 1 mask bit
10 = Select channel 2 mask bit
11 = Select channel 3 mask bit

Each channel has a mask bit, which can be set to disable the incoming DMA
request. These bits are ~et if their associated channel produces an EOP and
auto-initialize is not enabled.

Write All Mask Bits (OOOFH)
7

DON'T CARE
I

Bit

R/W Description

7-4

3-0

3
I

1
I

0
I

MASK BITS
CHANNEL CHANNEL CHANNEL CHANNEL
1
0
3
2
I

DON'T CARE (any valuel
MASK BITS
Enable the indicated channel (CHANNEL 3-01
1 = Disable the indicated channel (CHANNEL 3-01

DMA Controller - Hardware Description

4 - 11

Mode Register (OOOBH)
7

OPERATION
MODE
I

INCR/
DECR
SELECT

Bit

R/W Description

7-6

AUTO
INIT

1
I

TRANSFER TYPE CHANNEL SELECT
I

OPERATION MODE
00 =
Demand mode
01 = Single mode
10 = Block mode
11 =
Cascade mode
INCR/DECR SELECT - IncrementlDecrement selection
Increment selected
1 = Decrement selected

AUTO INIT - Auto-initialization enable

o = Disable auto-initialization
1 =

3-2

2
I

Enable auto-initialization

TRANSFER TYPE
00 =
Verify
01 = Write
10 = Read
11 =
Invalid value
A read transfer moves data from memory to the I/O device. A
write transfer moves data from the I/O device to memory. That is,
the orientation is from the 110 device, not the CPU.
If bits 7-6 equal 11, then the transfer type is a don't care value.

1-0

CHANNEL SELECT
00 =
Channel 0 selected
01 =
Channel 1 selected
10 =
Channel 2 selected
11 =
Channel 3 selected
Each DMA channel has a 6-bit mode register. Register selection is
determined by bits 1 and O.

4- 12

DMA Controller - Hardware Description

Request Register (0009H)
7

Bit

RIW Description

7-3

1-0

DON'T CARE (any value I
REQUEST BIT
Reset the indicated request bit
Set the indicated request bit

o=
1 =

CHANNEL SELECT
00 =
Channel 0
Channel 1
01 =
10 = Channel 2
11 =
Channel 3

The DMA controller responds to requests for DMA service from both software
and the DMA request signal. Each channel has a request bit that can be set or
reset as determined by the Request register. These bits are not maskable and
are subject to prioritization.

DMA Controller - Hardware Description

4 - 13

Status Register (0008H)
7

6
I

DHA REQUEST PENDING

1
I

TERMINAL COUNT REACHED

CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL

Bit

R/W Description

7-4

3-0

DMA REQUEST PENDING
Indicated channel does not have a request pending
{CHANNEL 3-01
1 = Indicated channel has a request pending {CHANNEL 3-01

TERMINAL COUNT REACHED

o = Indicated channel has not reached the terminal count
1 =

{CHANNEL 3-01
Indicated channel has reached the terminal count or external
EOP applied {CHANNEL 3-01

Temporary Register (OOOCH)
7

Bit

R/W Description

7-0

Last data byte transferred in a memory-to-memory transfer

Between the read and write cycles of a memory-to-memory transfer, the DMA
controller stores the source byte in this register. This register is cleared by a
hardware reset or a master clear.

4- 14

DMA Controller· Hardware Description

Programming Example
The following programming example demonstrates:
• Initializing the 8237A DMA controller
• Enabling and disabling a channel
• Preparing a channel for data transfer
The example provides routines as described in the following list:
dma init

Resets the DMA controller.

dma_open

Enables the indicated DMA channel.

dma transfer

Prepares the indicated channel for data transfer.

dma close

Disables the indicated channel.

Constant Values
The constant values DMA PAGEO through DMA PAGE3 define the 110 address of the indicated page-register. The values CHANNELO through
CHANNELl define the channel select bit values for the mode, mask, and
request registers. The values MTM ENA through BIT SET define the bit
values for various conditions of the command, status, mode, and request
registers.

1***********************************************************************1
1* define constants used in 8237 DMA example
*1
1***********************************************************************1
#define DMA_PAGEO Ox83
#define DMA_PAGEl Ox80
#define DMA_PAGE2 Ox8l
#define DMA_PAGE3 Ox82

1* DMA page register 0 I/O address *1
1* DMA page register 1 liD address *1
1* DMA page register 2 liD address *1
1* DMA page register 3 liD address *1

#define CHANNELO OxOO
#define CHANNELl OxOl
#define CHANNEL2 Ox02
#define CHANNEL3 Ox03

1* select channel Obit value *1
1* select channel 1 bit value *1
1* select channel 2 bit value *1
1* select channel 3 bit value *1
DMA Controller· Programming Example

4- 16

/* command register bit definitions */
#define MTM_ENA OxOi
/* Memory-to-memory enable */
#define HOLD_ENA Ox02
/* channel 0 hold address enable */
#define DMA_DIS Ox04
/* dma controller disable */
#define C_TIME
Ox08
/* compressed timing */
#define ROT_PRI Oxi0
/* rotating priority */
#define EXTD_WR Ox20
/* extended write */
#define DREQ_LO Ox40
/* DREQ active when low */
#define DACK_HI Ox80
/* DACK active when high */
/* status register bit definitions */
#define CHO_TC
OxOi
/* channel 0 bas reached terminal count */
#define CHCTC
Ox02
/* channel 2 has reached terminal count */
#define CH2_TC
Ox04
/* channel 3 has reached terminal count */
#define CH3_TC
Ox08
/* channel 4 has reached terminal count */
#define CHO_REQ Oxi0
/* channel 0 requesting service */
#define CHCREQ Ox20
/* channel 1 requesting service */
#define CH2_REQ Ox40
/* channel 2 requesting service */
#define CH3_REQ Ox80
/* channel 3 requesting service */
/* mode register bit definitions */
#define TRAN_VR OxOO
#define TRAN_WR Ox04
#define TRAN_RD Ox08
#define AUTO_IE Oxi0
#define ADR_DEC Ox20
#define MODE_DM OxOO
#define MODE_SI Ox40
#define MODE_BK Ox80
#define MODE_CS OxCO

/* verify transfer */
/* write transfer */
/* read transfer */
/* auto-initialize enable */
/* address decrement */
/* demand mode */
/* single mode */
/* block mode */
/* cascade mode */

/* request register bits */
#define BIT_SET Ox04

/* set selected mask bit */

4- 16

DMA Controller· Programming Example

Data Structures
The structure DMA CHANNEL resembles the 110 space of the address and
word count registers-for a channel. Multiple instances of this structure are used
in the declaration of the DMA CONTROLLER structure. The
DMA CONTROLLER structure defines the 110 space of DMA controller internal registers. The value DMA BASE defines the base address for referencing
the structure DMA CONTROLLER.
/***********************************************************************/
/* declare structures used in 8237 DMA example
*/
/***********************************************************************/
typedef struct

/* define dma channel I/O structure */

{

unsigned char bc_addr;
unsigned char bc_word;
} DMA_CHANNEL;
typedef struct

/* write base address, read current address */
/* write base word, read current word */

/* define dma controller I/O structure */

{

DMA_CHANNEL chO;
/* channel zero registers */
DMA_CHANNEL chi;
/* channel one registers */
DMA_CHANNEL ch2;
/* channel two registers */
DMA_CHANNEL ch3;
/* channel three registers */
unsigned char csr;
/* write control, read status */
unsigned char req;
/* write request register */
unsigned char wsmb;
/* write single mask bit */
unsigned char mode;
/* write mode register */
unsigned char temp;/* write clears byte pointer flip-flop, read temp */
unsigned char master_clr;
/* write master clear/reset */
unsigned char clr_mask;
/* clear all mask bits */
unsigned char wr_mask;
/* write all mask bits */
} DMA_CONTROLLER;
#define DMA_BASE (DMA_CONTROLLER *)OxOOOO

/* base address */

DMA Controller - Programming Example

4- 17

Initializing the DMA Controller
The DMA controller is initialized by issuing a MASTER CLEAR instruction.
This clears all bits in the command register and effectively disables the controller. The second instruction, which explicitly clears the control register, ensures
that the controller is disabled.

/***********************************************************************/
/* dma_init() - initialize the 8237 DMA controller

/***********************************************************************/
dma_initO
{

DMA_CONTROLLER *pdc = DMA_BASE;
outp(lpdc->master_clr, 0);
outp(lpdc->csr, 0);

/* point to DMA controller */
/* reset DMA controller */
/* all command register bits to 0 */

}

4- 18

DMA Controller - Programming Example

Opening a DMA Channel
The dma open function assumes that the channel is currently disabled. It
writes valid values to th~ registers that control the indicated channel.
For this C compiler, offset 0 in the data segment is used only for monitoring
NULL pointers. With a zero word count, an inadvertent data transfer can move
only one byte before expiring.
The last instruction enables the indicated channel.
/***********************************************************************/
/* dma_open() - open a DMA channel
*/
/***********************************************************************/
dma_open(channel)
int channel;

/* which DMA channel to open */

{

DMA_CONTROLLER *pdc
DMA_CHANNEL *pch;
int i;

/* point to DMA controller */
/* pointer to a channel structure */
/* loop control */

for(i = channel, pch = &pdc->chO; i; i--) /* discover which channel */
pch++;
/* point to next channel */
outp(&pdc->mode, channel);
/* clear mode register for this channel */
outp(&pdc->req, channel); /* clear channel request for this channel */
/* clear first/last flip-flop */
outp(&pdc->temp, 0);
outp(&pch->bc_addr, 0);
/* write 0 to low byte */
outp(&pch->bc_addr, 0);
/* write 0 to high byte */
/* clear first/last flip-flop */
outp(&pdc->temp, 0);
outp(&pch->bc_word, 0);
/* write 0 to low byte */
outp(&pch->bc_word, 0);
/* write 0 to high byte */
outp(&pdc->wsmb, channel);
/* clear mask bit for this channel */
}

DMA Controller . Programming Example

4- 19

Preparing a Channel for Data Transfer
The dma transfer function prepares a channel for~data transfer. Next, the function disabies the channel. It then initializes the page, address, word count, and
mode registers.
NOTE
Before writing a I6-bit register, the byte pointer flip/flop must
be cleared. This sequence loads the two sequential bytes in the
correct locations. Because interrupt processing could disrupt the
process, the dma transfer function disables CPU interrupts
before clearing the byte pointer flip/flop. Interrupts are not
enabled until after the I6-bit registers have been written.
/***********************************************************************/
/* dma_transfer() - set parameters for a DMA transfer
*/
/***********************************************************************/
dma_transfer(channel. page_val. addr. count. ttype)
int channel;
int page_val;
unsigned char *addr;
unsigned int count;
int ttype;

/* transfer on which DMA channel 7 */
/* page register contents */
/* transfer address */
/* count to transfer */
/* transfer type */

{

DMA_CONTROLLER *pdc = DMA_BASE;
DMA_CHANNEL *pch;
unsigned int page_reg;
int ch_mode;
int .intr3lag;

/* point to DMA controller */
/* pointer to a channel structure */
/* which page register to write */
/* channels mode */
/* to hold CPU IF state */

switch(channel)

/* which channel 7 */

{

case 0:
pch = &pdc->chO;
page_reg = DMA_PAGEO;
ch_mode = 0;
break;

4- 20

/* channel 0 ? */
/* point to channel 0 registers */
/* set page register address */
/* auto-initialize & increment/decrement */

DMA Controller - Programming Example

case 1:
pch = otpdc->ch1;
page_reg = DMA_PAGE1;
ch_mode = 0;
break;

/* channel 1 ? */
/* point to channel 1 registers */
/* set page register address */
/* auto-initialize ok increment/decrement */

case 2:
pch = otpdc->ch2;
page_reg = DMA_PAGE2;
ch_mode = MODE_SI;
break;

/* channel 2 ? */
/* point to channel 2 registers */
/* set page register address */
/* auto-initialize ot increment/decrement */

case 3:
pch = otpdc->ch3;
page_reg = DMA_PAGE3;
ch_mode = 0;
break;

/* channel 3 ? */
/* point to channel 3 registers */
/* set page register address */
/* auto-initialize ok increment/decrement */

}

outp(okpdc->wsmb. BIT_SET I channel);/* set mask bit for this channel */
outp(otpdc->req. channel); /* clear channel request for this channel */
outp(okpdc->mode. ttype I ch_mode I channel);
/* set mode register */
intr_flag = int_off();
/* no interrupts please */
outp(otpdc->temp. 0);
/* clear first/last flip-flop */
outp(otpch->bc_addr. (unsigned int)addr ok Oxff);
/* write low byte */
outp(otpch->bc_addr. (unsigned int)addr » 8);
/* write high byte */
outp(otpch->bc_word. count ok Oxff);
/* write low byte */
outp(otpch->bc_word. count » 8);
/* write high byte */
int_on(intr_flag);
/* allow interrupts */
outp(page_reg. page_val);
/* write the page register */
outp(otpdc->wsmb. channel);
/* clear mask bit for this channel */
}

DMA Controller - Programming Example

4- 21

Disabling a DMA Channel
The dma close function closes the channel by masking (disabling~ that channel's request input line.
/***********************************************************************/
/* dma_close() - close a DNA channel
*/
/***********************************************************************/
dma_close(channel)
unsigned char channel;

/* which DNA channel to close */

{

DNA_CONTROLLER *pdc - DMA_BASE;

/* point to DMA controller */

outp(lpdc->wsmb, BIT_SET I channel):/* set maak bit for this channel */
}

4- 22

DMA Controller· Programming Example

Chapter 5
Real-Time Clock
and CMOS RAM
Overview
The VAXmate processor board contains an MC146818 real-time clock. The realtime clock has the following features:
• Time-of-day clock with alarm and 100-year calendar
• Counts seconds, minutes, and hours of the day
• Counts days of the week, days of the month, month, and year with automatic end-of-month and leap year recognition
• Binary or binary-coded-decimal (BCD) representation of date, time, and
alarm (the ROM BIOS and MS-DOS use BCD).
• 24-hour clock or 12-hour clock with a.m./p.m. indication
• Daylight savings time option
• Internal time base and oscillator
• External time base 32.768 KHz crystal
• 64 byte, low-power, static RAM (14 bytes of registers and 50 bytes of
general purpose RAM)
• Square wave generator
• Programmable interrupts
Time-of-day alarm, once-per-second to once-per-day
Periodic interrupt rates from 30.5 flS to 500 ms
End-of-update interrupt

Real-time Clock and CMOS RAM - Hardware Description

5- 1

Additional Source of Information
The following Motorola Inc. document provides additional information on programming the real-time clock.

• 8·Bit Microprocessor & Peripheral Data

Battery-Backup Considerations
To keep time and maintain RAM when system power is off, the real-time clock
requires a battery-backup source. The two lithium batteries in the VAXmate
expansion box provide the only battery power source.
NOTE
The lithium battery used in the VAXmate expansion box has an
operational life expectancy of 6 years and a shelf life of 10
years.

Addressing the Real-Time Clock
The real-time clock (RTC) is addressed by the contents of an 8-bit latch at I/O
port 0070H and the RTC data is read or written through I/O port 0071H.
NOTE
The RTC address latch is write only. Bit 7 of the RTC address
latch (I/O port 0070H) is the nonmaskable interrupt (NMI) mask
register. If bit 7 equals zero, the NMI is enabled. Otherwise, the
NMI is disabled. For more information about the nonmaskable
interrupt, see Chapters 3 and 15.
The RTC dedicates the first 14 bytes of RAM (OOH through OOH) as registers
for the real-time clock functions. The remaining 50 bytes of RAM (OEH
through 3FH) are not dedicated to the RTC. Table 5-1 describes the RTC address map.

5- 2

Real-time Clock and CMOS RAM . Hardware Description

Table 5-1

Real-Time Clock Address Map

Latch Value

R/W

Location Accessed

OOH

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Seconds register
Seconds alarm register
Minutes register
Minutes alarm register
Hours register
Hours alarm
Day-of-week register
Day-of-month register
Month register
Year register
Register A
Register B
Register C
Register 0
Remaining 50 bytes of RTC RAM *

OlH

02H
03H
04H
05H
06H
07H
08H
09H
OAH
OBH

OCH
ODH
OEH-3FH

* See the definition of the structure RTC in the programming example.

Real-Time Clock Registers
The real-time clock (RTC) has two types of registers:
• Data (locations OOH through 09H)
• Control and status (locations OAH through ODH)
Data registers are valid only when the RTC is not updating. During clock updates, the RTC disconnects the data registers from the RTC bus. The specifics
of data register processing are discussed later.
The control and status registers are available at all times.

Real-time Clock and CMOS RAM - Hardware Description

5- 3

4
I

UIP

DIVIDER SELECTION BITS
DS2

I DSl I DSO

1
I

RATE SELECTION BITS
RS3

I RS2 I RSl I RSO

Bit

R/W Description

R/W UIP - Update In Progress
o = For all time bases, at least 244 ps remain before the update
cycle begins. The data registers are available for reading.
1 = Update cycle is in progress or begins in less then 244 ps.
The UIP bit is a read-only bit. For the 32.768 KHz time base, the
update cycle time is 1984 ps. Writing a 1 to the Register B SET
bit inhibits the update cycle and clears the UIP status bit. A hardware reset does not modify the UIP bit.

6-4

R/W DIVIDER SELECTION BITS

These bits identify the time base to use. Writing 111 to these bits
resets the divider. One second after removing the divider reset, the
first update cycle begins. For the VAXmate workstation time base
of 32.768 KHz, set these bits to 010. A hardware reset does not
modify the DIVIDER SELECTION bits.
3-0

R/W RATE SELECTION BITS
These bits select one of 15 taps on a 22-stage divider or disable
the divider. Table 5-2 shows the bit values for the possible interrupt rates. A hardware reset does not modify the RATE
SELECTION bits. On powerup, the ROM BIOS sets these bits to

5- 4

Real-time Clock and CMOS RAM - Hardware Description

Table 5-2

Rate Selection Bits

RS3

RS2

RSI

RSO

Periodic Interrupt Rate

None (divider disabled)

3.90625 J,lS

7.8125 J,lS

122.070 J,lS

244.141 J,lS

488.281 J,lS

976.562 J,lS

1.953125 IDS

3.90625 IDS

7.8125 IDS

15.625 IDS

31.250 IDS

62.5 IDS

125.0 IDS

250.0 IDS

500.0 IDS

Real-time Clock and CMOS RAM - Hardware Description

5 - I)

AlE

I lITE

I SQVE

I I I
SET

PIE

lOKI

I DSE

Bit

R/W Description

R/W SET
o = Allow update cycles to occur once per second
1 = Abort any update cycle in progress and inhibit update cycles
until cleared. (This allows initialization of the date, time, and
alarm registers.)
A hardware reset does not modify the SET bit.

R/W PIE - Periodic Interrupt Enable
o = Disable periodic interrupts (default value)
1 = Enable periodic interrupts at the rate specified by RS3-RSO
in Register A
A hardware reset clears the PIE bit to O.

R/W AlE - Alarm Interrupt Enable
o = Disable alarm interrupts (default value)
1 = Enable alarm interrupts. (The interrupt frequency depends on
the contents of the alarm registers.)
A hardware reset clears the AlE bit to O.

R/W UIE - Update-ended Interrupt Enable
o = Disable the update-ended interrupt (default value)
1 = Enable the update-ended interrupt
A hardware reset or setting the register B SET bit clears the UIE
bit to O.

R/W SQWE - Square Wave Enable
o = Disable the square-wave output (default value)
1 = Enable the square-wave output

The square-wave output is not connected to anything, so the
SQWE bit should always be written as O. A hardware reset clears
the SQWE bit to O.
5- 6

Real-time Clock and CMOS RAM - Hardware Description

Bit

RIW Description (Register B - cont.)

RJW DM - Data Mode

o=
1 =

Binary-coded-decimal (BCD) data format used for date, time,
and alarm registers
Binary data format used for date, time, and alarm registers

A hardware reset does not modify the DM bit. However, the ROM
BIOS clears DM to O.
1

R/W HM - Hour Mode
o = Hours register and hours alarm register use a 12-hour clock
with a.m. or p.m. indication
1 = Hours register and hours alarm register use a 24-hour clock
A hardware reset does not modify the HM bit. However, the ROM
BIOS sets HM equal to 1.

R/W DSE - Daylight Savings Enable
o = Disable daylight savings
1 = Enable daylight savings. Daylight savings changes occur at 2
a.m. on the last Sunday in April and the last Sunday in
October.
A hardware reset does not modify the DSE bit. However, the
ROM BIOS clears DSE to O.

Real-time Clock and CMOS RAM - Hardware Description

5- 7

Bit

RJW Description

RJW IRQF - Interrupt Request Flag

3-0

When one or more of the following conditions are true, the RTC
sets the IRQF bit to 1:
PIF = PIE = 1
AIF = AlE = 1
UIF = UIE = 1
RJW PIF - Periodic Interrupt Flag
When register B, bit PIE equals 1, the PIF bit indicates the state
of the periodic interrupt. If PIF equals 1, the RTC sets IRQF.
Register A bits RS3-RSO establish the rate of this interrupt.
RJW AIF - Alarm Interrupt Flag
When register B, bit AlE equals 1, the AIF indicates the state of
the alarm interrupt. When AIF equals 1, the current time matches
the alarm time and the RTC sets IRQF.
RJW UIF· Update-ended Interrupt Flag
When register B, bit AlE equals 1, the UIF bit indicates the state
of the update-ended interrupt. At the end of each update cycle, the
RTC sets this bit to 1 and sets IRQF.
RJW Always 0

Resetting hardware or reading register C clears all bits in register C. Writing
to Register B does not modify the bits in Register C.

5- 8

Real-time Clock and CMOS RAM - Hardware Description

'WIT' 0' 0' 0' 0' 0' 0' 0 I
Bit

RIW Description

R/W VRT - Valid RAM and Time
o = Since the last time this register was read, the power-sense
circuitry detected a loss of power to the RTC. The RTC registers and RAM contain invalid data.
1 = Since the last time this register was read, power to the RTC
has remained stable.

Reading this register sets the VRT bit. It is the only way to set
the VRT bit. After setting the date, time, or alarm, read this register so that the VRT bit indicates that the registers are valid.
A hardware reset does not modify the VRT bit.
6-0

R/W Always 0

Real-time Clock and CMOS RAM - Hardware Description

5- 9

Real-Time Clock Data Registers
The real-time clock (RTC) formats the date and time in either binary or binarycoded-decimal {BCD). All data registersJOOH through 09H) must use the same
format. If the data format is changed, the data registers must be initialized in
the new format. The ROM BIOS uses the BCD data format. Bit 2 of register
B controls the format.
The HOUR MODE bit in Register B controls the range of the hour and hour
alarm registers. When the HOUR MODE bit is set U), the hour and hour
alarm registers have the range 0-23. When the HOUR MODE bit is clear {OJ,
the hour and hour alarm registers have the ranges 1-12 (a.m.) and 129-140
(p.m.).
The hours, minutes., and seconds alarm registers have an additional range of
COH-FFH. This is an alarm register don't care code. For more information, see
the alarm description. Table 5-3 shows the format and ranges of the data
registers.

5- 10

Real-time Clock and CMOS RAM - Hardware Description

Table 1)-3

RTC Data Register Ranges

Latch
Value

Function

Binary Range

BCD Range

OOH

Seconds

All modes

0-59

00H-59H

01H

Seconds
Alarm

Specific time

0-59

00H-59H

Each second

192-255

COH-FFH

02H

Minutes

All modes

0-59

00H-59H

03H

Minutes
Alarm

Specific time

0-59

00H-59H

Each minute

192-255

COH-FFH

24-hour mode

0-23

00H-23H

12-hour mode a.m.

1-12

01H-12H

12-hour mode p.m.

129-140

81H-92H

Specific time
(24-hour mode)

0-23

00H-23H

Specific time (12-hour 1-12
mode a.m.)

01H-12H

Specific time (12-hour 129-140
mode p.m.)

81H-92H

Each hour (all modes) 192-255

COH-FFH

04H

05H

Hours

Hours Alarm

06H

Day-of-Week

1-7

01H-07H

07H

Day-of-Month

1-31

01H-31H

08H

Month

1-12

01H-12H

09H

Year

0-99

00H-99H

Real-time Clock and CMOS RAM - Hardware Description

I) - 11

Alarms
During each real-time clock (RTC) update cycle, the RTC compares the hour,
minute, and second registers to the corresponding alarm registers. If all of the
time registers match all of the alarm registers, the RTC sets the register C
AIF. If, when this occurs, the register B alarm interrupt enable (AlE) bit is
enabled, the alarm interrupt triggers IRQ8.
An alarm register value in the range COH-FFH is a don't care code. When an
alarm register contains a don't care code, that alarm register matches any
value in the corresponding time register.
Table 5-4 shows the eight different types of automatic alarm cycles provided by
the real-time clock (RTC).
Table 5-4

RTC Automatic Alarm Cycles

Cycle Description

Hour Alarm

Minute Alarm Second
Alarm

Once per second every second

COH-FFH

Once per second for a
one-minute span every hour
Once per second for a oneminute span every 24 hours

COH-FFH

Specified

COH-FFH

Specified

COH-FFH

Once per second for a one-hour
span every 24 hours

Specified

COH-FFH

Once per minute every minute

COH-FFH

Specified

Once per minute for a one-hour
span every 24 hours

Specified

COH-FFH

Specified

Once per hour every hour

COH-FFH

Specified

Once every 24 hours

Specified

Also, there is a nonautomatic way to use the alarm function. To use this
method, set a specific alarm time. At each subsequent alarm interrupt, set the
next specific alarm time.

5- 12

Real-time Clock and CMOS RAM - Hardware Description

Update Cycle
Once per second. the real-time clock (RTC) performs an update cycle. With a
32.768 KHz time base, the update cycle requires 1948 IlS. The update cycle
comprises the following steps:
• The RTC sets (1) the register A UIP bit.
• After 244 IlS, the RTC disconnects the data registers from the external
bus and connects them to the internal bus.
• The RTC increments the seconds register.
• The RTC checks for an overflow condition. If no overflow condition exists,
the RTC goes to the next step. Otherwise, the RTC zeros the register
and increments the next register in the series.
• The RTC compares the hour, minute, and seconds registers to the corresponding alarm registers. If a match occurs for all three registers, the
RTC sets (1) the register C alarm flag (AIF).
• The RTC disconnects the data registers from the internal bus and connects them to the external bus.
• The RTC clears (0) the register A UIP bit.
• The RTC sets (1) the register C update-ended interrupt flag (UIF)
During an update cycle, the data registers are disconnected from the external
bus. Therefore, while an update is in progress, reading or writing a data register produces invalid results. Use one of the following methods to avoid update
cycles:
• Monitor the register A update-in-progress (UIP) bit. The update cycle
begins 244 IlS after the RTC sets the UIP bit. Thus, if the UIP bit is
clear, the data registers will remain valid for at least 244 IlS.
• Enable the update-ended interrupt. This interrupt occurs after every
update cycle. The date and time registers remain valid for over 999 ms
after the RTC sets the UIF. If the processor must handle an excessive
amount of interrupts, the interrupt handler for the RTC should also monitor the UIP bit.
• Monitor the register C periodic interrupt flag (PIF). The periodic interrupt
is synchronized with the update cycle. For any given periodic interrupt,
there is a time after the interrupt when the data registers are valid. For a
32.768 KHz time base, use only the rates between 3.90625 ms and 500
ms. Use the following formula to calculate the valid time span:
Time Span = 244 IlS + (RATE I 2)
Real-time Clock and CMOS RAM - Hardware Description

5- 13

Interrupts
Periodic Interrupt
If the PIE bit is set (1), the periodic interrupt triggers IRQ8 at the rate specified by the RATE SELECT bits in register A.

Update-Ended Interrupt
If the UIE bit is set (1), the update-ended interrupt triggers IRQ8 once per
second. The next RTC update cycle starts 1000 ms after the update-ended
interrupt.

Alarm Interrupt
During each RTC update cycle, the RTC compares the hour, minute, and
second registers to the corresponding alarm register. If the time and alarm registers match and if the AlE bit is set (1), the alarm interrupt triggers IRQ8.

5- 14

Real-time Clock and CMOS RAM - Hardware Description

Programming Example
The real-time clock (RTC) programming example demonstrates:
•
•
•
•

Reading and writing the RTC registers and RAM
Handling RTC interrupts
Interpreting the data stored in the RTC RAM
Calculating the checksum that ensures data integrity

The next programming example provides the following routines:
rd rtc

Reads the indicated RTC register or RAM location

wr rtc

Writes the indicated RTC register or RAM location

rtc cksum

Returns the calculated RTC RAM checksum

btb

Returns the binary equivalent of a binary-coded decimal
(BCD) value

bed

Returns the binary-coded decimal (BCD) equivalent of a
binary value

rd date

Reads the date-related registers and stores the results in
the indicated structure

rd time

Reads the time-related registers and stores the results in
the indicated structure

shw date

Displays the current date at location 0,0

shw time

Displays the current time at location 0,72

shw_ddtyp

Displays the diskette drive types

shw_hdtyp

Displays the hard disk drive types

rtc int hand

Handles hardware interrupts from the RTC

shw hdw

Displays the hardware setup from RTC RAM

rtc init

Initializes the RTC interrupt vector (70H) and the RTC
alarm registers

rtc rest

Restores the RTC interrupt vector (70H) and disables clock
interrupts

rtc

Provides menu selection of the examples and executes the
examples

Real-time Clock and CMOS RAM - Programming Example

5- 15

CAUTION
Improper programming or improper operation of this device can
cause the VAXmateworkstation to malfunction. The scope of
the next programming exa~ple is limited to the context provided in this manual. No other use is intended.

Constant Values
The file (kyb.h) that is inc1uqed defines constant values for function keys. See
Chapter 8 for information about keyboard programming.
The file (example.h) that is included defines the structure type MESSAGE that
is used to display the menu.
The constant valuesCKSUM START and CKSUM END define the start and
end offsets of the RTC RAM that is under checksum control. If any value in
this rang~ is changed, a new checksum must be written to reflect this change.
The constant values UJP. thtough VRT define bit values for registers A through
D. The value DIVIDE;_SEL defines the divider that divides the base input frequenCY for the internal RTC operation. This value is related to the VAXmate
hardware design and· should be com~.idered a fixed value.

5~ 16

Real-time Clock and CMOS RA1d - Programming Example

#include "kyb.h"
#include "example.h"

/* reference function key constants */
/* reference menu structure */

/*********************************************.*************************/
/* define constants used in RTC example
*/
/***********************************************************************/
#define CKSUM_START Ox10
#define CKSUM_END
Ox20

/* offset of start of checksum area */
of checksum area */
/* offset of en4

/* define register A bit values */
#define UIP
#define DIVIDE_SEL
#define RATE_SEL

Ox80
Ox20
OxOd

/* update in progress bit */
/* FIXED VALUE - Hardware related */
/* Programmer defined interrupt rate */

/* define register B bit values */
#define SET_UPD
#define PIE
#define AlE
#define UIE
#define SQWE
#define OAT_MOD
#define CLK24
#define DSE

Ox80
Ox40
Ox20
Ox10
Ox08
Ox04
Ox02
Ox01

/* disable updating ,of date ok time */
/* Periodic Interrupt Enable */
/* Alarm Interrupt Enable */
/* Update-Ended Interrupt Enable */
/* Square Wave Enable */
/* Data mode (BCD = 0, Binary = 1) */
/* 12-hour clock = p, 24 hour = 1 */
/* Daylight Savings Enable */

/* define register C bit values */
#define IRQF
#define PIF
#define AIF
#define UIF

Ox80
Ox40
Ox20
Ox10

/* InterrllP~Request Flag */
/* Periodic Interrupt Flag */
/* Alarm :Interrupt Flag */
/* Upda,te-Ended Flag */

/* define register o 'bit values */
#define VRT

Ox80

/* Valid Ram ok Time bit */

Real-time Clock and CMOS RAM - Programming Example

5- 17

])ata Structures
The structure type RTC defines the 1/0 space that accesses the real-time clock.
The offset within the real-time clock WOH-3FH) is written to an 8-bit latch that
addresses the real-time clock. This latch is located at 110 address 0070H. Data
is read or written through 1/0 address 0071H.
The structure type CMOS defines how each RAM location is used within the
real- time clock. The real-time clock dedicates the first 14 locations as registers. The remaining 50 bytes of RAM are defined according to industrystandard usage.
The structure type DATIM provides a consistent format for moving date and
time information.

/***********************************************************************/
/* declare structures used in RTC example

/***********************************************************************/
typedef struct
{

unsigned char addr_port;
unsigned char data_port;
} RTC;

/* write RTC/CMOS address to this port */
/* read/write data through this port */

typedef struct
{

unsigned char seconds;
unsigned char aIr_sec;
unsigned char minutes;
unsigned char aIr_min;
unsigned char hours;
unsigned char alr_hr;
unsigned char dow;
unsigned char dom;
unsigned char month;
unsigned char year;
unsigned char rega;
unsigned char regb;
unsigned char regc;
unsigned char regd;
unsigned char diag;
unsigned char reset;
unsigned char ddtyp;
unsigned char reserv1;
unsigned char hdtyp;
unsigned char reserv2;

5- 18

/* seconds (0-59) current time */
/* seconds alarm */
/* minutes (0-59) current time */
/* minutes alarm */
/* hours (0-11/23) current time */
/* hours alarm */
/* day-of-week (1-7) */
/* day-of-month (1-28/29/30/31) */
/* month (1-12) current date */
/* year (0-99) current date */
/* register A */
/* register B */
/* register C */
/* register D */
/* diagnostics byte */
/* reason for reset */
/* diskette drive type */
/* reserved byte */
/* hard disk type */
/* reserved byte */

Real-time Clock and CMOS RAM . Programming Example

unsigned char syscfg;
/* system configuration byte */
unsigned char bmeml;
/* base memory size low byte */
unsigned char bmemh;
/* base memory size high byte */
unsigned char lememl;
/* expansion memory size low byte */
unsigned char lememh;
/* expansion memory size high byte */
unsigned char reserv3[Ox2e - Ox19];
/* reserved */
unsigned char cksumh;
/* high byte of checksum (always 0) */
unsigned char cksuml;
/* low byte of checksum */
/* expansion memory size low byte */
unsigned char hememl;
unsigned char hememh;
/* expansion memory size high byte */
unsigned char century;
century
byte of date (19 from 1986) */
/*
unsigned char info;
/* information flag */
/* reserved */
unsigned char reserv4[Ox40 - Ox34];
} CMOS;

typedef struct
{

int seconds;
int minutes;
int hours;
int dow;
int dom;
int month;
int year;

/* seconds (0-59) */
/* minutes (0-59) */
/* hours (0-11/23) */
/* day-of-week (1-7) */
/* day-of-month (1-28/29/30/31) */
/* month (1-12) */
/* year (century * 100 + year register) */

} DATIM;

Real-time Clock and CMOS RAM - Programming Example

5- 19

Reading the Registers and RAM
The function rd rtc reads the indicated byte of real-time clock RAM. Before
accessing the bYte, the offset is compared to the range OOH-09H. This is the
offset range of the data registers, which are invalid during update cycles. If the
offset falls within this range, the read is synchronized with the update-inprogress bit.
/ ••••••••• *.*************************.**********************************/
/* rd_rtc() - read an RTC byte (if date or time, monitor UIP bit)
*/
/***********************************************************************/
int rd_rtc(offset)

/* read RTC byte */
/* byte offset to read *1

int offset;
{

RTC *prtc;
CMOS *pcmos;
unsigned int intr_flg;
unsigned char retval;

/* ptr to address l data ports */
/* ptr to RTC/CMOS structure */
/* CPU IF state */
/* value to return */

prtc = (RTC *)Ox10;
pcmos = 0;
if(offset < (int)(lpcmos->rega»

/* assign I/O address *1
/* structure offset is zero */
1* need to monitor UIP ? */

{

while (1)

1* break out when ready */

{

intr_flg = int_off();
outp(lprtc->addr_port, lpcmos->rega);
if(inp(lprtc->data_port) l UIP)
. int_on(intr_flg);
else break;

/* no interrupts allowed */
/* set to reg A */
/* test UIP bit */
/* allow interrupts *1

}
}

else intr_flg = int_off();
outp(lprtc->addr_port, offset);
retval = inp(lprtc->data_port);
int_on(intr_flg);
return(retval);

/* no interrupts allowed */

1* set to desired offset */
/* read data */

1* allow interrupts */
/* return data byte */

}

5- 20

Real-time Clock and CMOS RAM - Programming Example

Writing the Registers and RAM
The function wr rtc writes the indicated byte of real-time clock RAM. Before
accessing the byte, the offset is compared to the range OOH-09H. This is the
offset range of the data registers, which are invalid during update cycles. If the
offset falls within this range, the write is synchronized with the update-inprogress bit.
/***********************************************************************/
/* wr_rtc() - write an RTC byte
*/
/***********************************************************************/
void wr_rtc(offset, value)

/* write RTC byte */

int offset;
unsigned char value;

/* offset to write */
/* byte value to write */

{

RTC *prtc;
CMOS *pcmos;
unsigned int intr_flg;

/* ptr to address • data ports */
/* ptr to RTC/CMOS structure */
/* CPU IF state */

prtc = (RTC *)Ox70;
pcmos = 0;
if(offset < (int)(.pcmos->rega»

/* assign I/O address */
/* structure offset is zero */
/* need to monitor UIP ? */

{

while (1)

/* break out when ready */

{

intr_flg = int_off();
outp(.prtc->addr_port, .pcmos->rega);
if(inp(.prtc->data_port) • UIP)
int_on(intr_flg);
else break;

/* no interrupts allowed */
/* set to reg A */
/* test UIP bit */
/* allow interrupts */

}
}

else intr_flg = int_off();
outp(.prtc->addr_port, offset);
outp(.prtc->data_port, value);
int_on(intr_flg);

/* no interrupts allowed */
/* set to desired offset */
/* write data */
/* allow interrupts */

}

Real-time Clock and CMOS RAM - Programming Example

5- 21

Calculating the Checksum
The function rtc cksum calculates the checksum and returns the result to the
caller. The checksum is the sum, modulo 256, of all bytes in the range
CKSUM_START through CKSUM_END.

/***********************************************************************/
/* rtc_cksum() - calculate the CMOS checksum and return its value

/***********************************************************************/
unsigned char rtc_cksum()

/* calculate the CMOS checksum */

{

int i;
unsigned char sum;

/* loop control */
/* accumulates the checksum */

sum = 0;
/* sum starts out zero */
for(i = CKSUM_START; i <= CKSUM_END; i++)
/* all checksum bytes */
sum += rd_rtc(i);
/* read data and add to sum */
return(sum);
/* return calculated checksum */
}

5- 22

Real-time Clock and CMOS RAM - Programming Example

Converting Binary-Coded Data
The ROM BIOS defines the data mode as binary-coded decimal (BCDI and
therefore, so does this example. This requires converting between BCD and
binary. The function btb converts a BCD value to its binary equivalent. The
function bed converts a binary value to its BCD equivalent.

/***********************************************************************/
/* btb - convert bed value to binary integer value
*/
/***********************************************************************/
btb(bcd_val)

/* bed to binary integer */

unsigned char bcd_val;

/* bed value */

{

/* assume valid bed value */
return«(bcd_val »

* 10) + (bcd_val l OxOf»;

}

/***********************************************************************/
/* bed

- convert binary value to bed value

/***********************************************************************/
unsigned char bcd(val)

/* binary to bed */

unsigned char val;

/* binary value */

{

/* assume valid bed value */

unsigned char tmp;
tmp = (val / 10) «
tmp 1= val % 10;
return(tmp);

/* tens in upper nibble */
/* ones in lower nibble */
/* return BCD value */

}

Real-time Clock and CMOS RAM - Programming Example

5- 23

Reading the Date
The function rd_date reads all of the date-related registers and stores the
results in the DATIM structure pointed to by the calling parameter. It can be
called at any time without restriction.
The century byte is not a real-time clock register. The century byte is an
industry-standard location that overcomes the lOO-year calendar limitation. It
must be updated manually or by software.
/***********************************************************************/
/* rd_date() - read date and write to DATIM structure
*/
/***********************************************************************/
void rd_date(pd)
DATIM *pd:

/* read the date */
/* where to store data */

{

CMOS *pcmos:

/* ptr to RTC/CMOS structure */

pcmos .. 0:
/* structure offset is zero */
pd->dow
- btb(rd_rtc(ipcmos->dow»:
/* day-of-week */
pd->dom
.. btb(rd_rtc(ipcmos->dom»:
/* day-of-month */
pd->month .. btb(rd_rtc(ipcmos->month»;
/* month */
pd->year
- btb(rd_rtc(ipcmos->century» * 100:
/* century */
pd->year
+= btb(rd_rtc(ipcmos->year»:
/* year */
}

6- 24

Real-time Clock and CMOS RAM - Programming Example

Reading the Time
The function rd time reads all of the time-related registers and stores the
results in the DATIM structure pointed to by the calling parameter. This function assumes the use of the 24-hour clock mode. It can be called at any time
without restriction.
/***********************************************************************/
/* rd_time() - read time and write to DATIM structure
*/
/***********************************************************************/
/* read the time */
DATIM *pd;

/* where to store data */

{

CMOS *pcmos;

/* ptr to RTC/CMOS structure */

pcmos = 0;
/* structure offset is zero */
pd->seconds
btb(rd_rtc(&pcmos->seconds»;
/* seconds */
/* minutes */
pd->minutes = btb(rd_rtc(&pcmos->minutes»;
= btb(rd_rtc(&pcmos->hours»;
/* hours */
pd->hours
}

Real-time Clock and CMOS RAM - Programming Example

5- 25

Displaying the Date
The function shw date displays the current date starting at row 0 and column
O. It can be calledat any time without restriction.

/***********************************************************************/
/* define some day and month names

/***********************************************************************/
char day_name [8] [10]
{

"Invalid" ,
/* rtc is 1 based */
"Sunday" ,"Monday", "Tuesday", "Wednesday",
"Thursday", "Friday". "Saturday"
};

char month_name [13] [10]
{

"Invalid".
"January" ,"February". "March"
"May"
• "June"
• "July"
"September". "October" . "November".

/* rtc is 1 based */
"April".
"August".
"December"

};

/***********************************************************************/
/* shw_date - show date starting at row 0 column 0

/***********************************************************************/

DATIM dt;
char sdate[50];

/* date and time structure */
/* place to store output */

rd_date(&dt);
/* read current date */
sprintf(sdate. "%9s %9s %2d. %04d". &day_name[dt.dow] [0] ,
&month_name[dt.month] [0] , dt.dom. dt.year);
disp_str(O, 0, sdate);
/* display it */
}

5- 26

Real-time Clock and CMOS RAM - Programming Example

Displaying the Time
The function shw time displays the current time starting at row 0 and column
72. It can be called at any time without restriction.

/***********************************************************************/
/* shw_time - show time on row 0 column (last_column - 7)

/***********************************************************************/
shw_timeO
{

DATIM dt;
char stime[50];

/* date and time structure */
/* place to store output */

rd_time(It;dt);
/* read current time */
sprintf(stime, "%2d:%02d:%02d" , dt.hours, dt.minutes, dt.seconds);
disp_str(O, 72, stime);
/* display it */
}

Real-time Clock and CMOS RAM - Programming Example

5- 27

Displaying the Diskette Drive Type
The function shw ddtyp is a text-formatting subroutine that generates the
diskette drive type according to the calling parameters. It is only called by the
function shw hdw.

1***********************************************************************1
1* shw_ddtyp - show diskette drive type
*1
1***********************************************************************1
void shw_ddtyp(pc, ddtyp, drive)

1* show diskette drive type *1

char *pc;
char ddtyp;
char drive;

1* buffer to write to *1
1* diskette drive type *1
1* drive letter *1

{

1* temp for index *1

int i;
i = sprintf (pc, liDiskette drive %c is ", drive);
switch (ddtyp)

1* general opening *1

{

case 0:
sprintf(lpc[i], "non-existent"):
break;
case 1:
sprintf (lpc [1], "48-TPI double sided"):
break:

1* no drive *1

1* 48 tpi dsdd *1

case 2:
1* 96 tpi dsdd hc *1
sprintf(lpc[i], "an RX33 96-TPI double-sided, high-capacity"):
break;
default:
sprintf (&:pc [1], "an unknown type");
break:

1* unknown type *1

}
}

5- 28

Real-time Clock and CMOS RAM - Programming Example

Displaying the Hard Disk Type
The function shw hdtyp is a text-formatting subroutine that generates the hard
disk drive type according to the calling parameters. It is only called by the
function shw hdw.
/***********************************************************************/
/* shw_hdtyp - show hard disk type
*/
/***********************************************************************/
void shw_hdtyp(pc, hdtyp, drive)

/* show hard disk type */

char *pc:
char hdtyp:
char drive:

/* hard disk type */
/* drive letter */

{

int i:
i = sprintf (pc , "Hard disk drive %c is ", drive):
if (hdtyp) sprintf (II:pc [1], "type %d", hdtyp):
else sprintf(II:pc[i], "non-existent"):

/* drive type */
/* no drive */

}

Real-time Clock and CMOS RAM - Programming Example

5- 29

Handling the Clock Interrupts
The function rtc int hand is the real-time clock interrupt handler. It checks for
all of the three possible interrupts, update-ended flag (UIF), alarm flag (AF),
and periodic interrupt flag (PIF). After handling the interrupts, the interrupt
handler notifies the interrupt controller.
The update-ended interrupt occurs once per second. At each interrupt, the interrupt handler increments the global flag, time flag, to indicate that at least
one second has elapsed.
The alarm interrupt is initialized to the first second of every day. At each interrupt, the interrupt handler increments the global flag, date_flag, to indicate
that at least one day has elapsed.
The periodic interrupt is initialized to a rate of 125 ms. At each interrupt, the
interrupt handler increments the global counter, metronome. The 8254 timer
and speaker example in Chapter 6 uses this counter for output timing. Also,
the periodic interrupt handler calls unbeep. If required, unbeep turns off the
bell (beep sound). The example programs use the speaker to generate a bell
(beep sound).

5- 30

Real-time Clock and CMOS RAM - Programming Example

/***********************************************************************/
/* rtc_int_hand() - real-time clock interrupt handler
*/
/***********************************************************************/
int time_flag;
int date_flag;
unsigned int metronome;
int motor_flag;
int head_settle;

/* 1 second update flag */
/* 1 day update flag */
/* timer for sound output */
/* timer for diskette drive motors */
/* head settle timer for diskette drives */

void rtc_int_hand()

/* rtc int handler */

{

CMOS *pcmos;
unsigned char tmp;

/* ptr to RTC/CMOS structure */
/* temp to read in reg C */

pcmos = 0;
/* structure offset is zero */
tmp = rd_rtc(&pcmos->regc);
/* read current interrupt requests */
if(tmp & UIF) time_flag++;
/* time updates once per second */
if(tmp & AIF) date_flag++; /* alarm set for once per day at 00:00:00 */
if(tmp & PIF)
/* periodic interrupt ? */
{

metronome++;
unbeepO;
if (motor 3lag)
i f (--motor_flag
motor_off 0 ;
i f (head_settle)
head_settle--;

/* increment timing for speaker demo */
/* unbeep turns off speaker if bell */
/* if timing diskette drive motors */
/* if timed out */
/* call routine to turn motors off */
/* if timing head settle */
/* reduce count */

}

eoi(l) ;

/* end of interrupt for interrupt controller */

}

Real-time Clock and CMOS RAM - Programming Example

5- 31

Interpreting the RAM Contents
The function shw hdw interprets the industry-standard locations in the realtime clock RAM and displays the results. The ROM BIOS interprets this data
in the same manner.
/***********************************************************************/
/* sh_hdw() - show hardware setup in CMOS
*/
/***********************************************************************/

UDsigned char tmpj
unsigned int uij
CMOS *pcmosj
char *PCj
char line[612]j

/* to hold CMOS byte read */
/* to hold memory size */
/* ptr to RTC/CMOS structure */

#define ROW 16
#define COL 17
pcmos .. 0;
/* structure offset is zero */
tmp - rd_rtc(ipcmos->syscfg);
/* read system config */
sprintf (line , "%d diskette drive(s) present", (tmp » 6) + 1) j
disp_str(ROW, COL, line);
switch«tmp i Ox30) » 4)
/* check video type */
{

case 0:
pc .. "Invalid video type";
breakj

/* not a valid type */

case 1:
pc = "40 column color graphics"j
breakj
case 2:
pc .. "80 column color graphics";
break;
case 3:
pc .. "Monochrome adapter with parallel port";
break;
}

disp_str(ROW + 1, COL, pc);
tmp = rd_rtc(ipcmos->ddtYP)j

5- 32

/* display video type */
/* read diskette drive types */

Real-time Clock and CMOS RAM· Programming Example

shw_ddtyp(line, tmp »4, 'A');
/* get drive a type */
disp_str(ROW + 2, COL, line);
/* display drive a type */
shw_ddtyp(line, tmp t OxOf, 'B');
/* get drive b type */
disp_str(ROW + 3, COL, line);
/* display drive b type */
tmp = rd_rtc(tpcmos->hdtyp);
/* read hard disk types */
shw_hdtyp(line, tmp »4, 'C');
/* get drive c type */
disp_str(ROW + 4, COL, line);
/* display drive c type */
shw_hdtyp(line, tmp t OxOf, 'D');
/* get drive d type */
disp_str(ROW + 5, COL, line);
/* display drive d type */
tmp = rd_rtc(tpcmos->bmemh);
/* base memory high byte */
ui = (unsigned int)tmp « 8;
/* shift and assign */
tmp = rd_rtc(tpcmos->bmeml);
/* base memory low byte */
ui 1= (unsigned int)tmp;
/* add low byte */
sprintf (line, "Base memory = %dK bytes", ui);
disp_str(ROW + 5, COL, line);
/* display base memory */
tmp = rd_rtc(tpcmos->lememh);
/* expanded memory high byte */
ui = (unsigned int)tmp « 8;
/* shift and assign */
tmp = rd_rtc(tpcmos->lememl);
/* expanded memory low byte */
/* add low byte */
ui 1= (unsigned int)tmp;
sprintf (line , "Expansion memory = %dK bytes", ui);
disp_str(ROW + 6, COL, line);
/* display expanded memory */
tmp = rd_rtc(tpcmos->hememh);
/* expanded memory high byte */
ui = (unsigned int)tmp « 8;
/* shift and assign */
tmp = rd_rtc(tpcmos->hememl);
/* expanded memory low byte */
ui 1= (unsigned int)tmp;
/* add low byte */
sprintf (line , "Expansion memory
%dK bytes", ui);
disp_str(ROW + 7, COL, line);
/* display expanded memory */
}

Real-time Clock and CMOS RAM - Programming Example

5- 33

Initializing the Real-Time Clock
To start up real-time clock interrupt processing, the rtc_init function:
• Disables real-time clock interrupts and update cycles
• Initializes the processor interrupt vector, the real-time clock control, and
alarm registers; and unmasks the interrupt controller input
• Enables the real-time clock interrupts and update cycles
/***********************************************************************/
/* rtc_init() - initialize alarms and vectors
*/
/***********************************************************************/
rtc_init 0
{

CMOS *pcmos;

/* ptr to RTC/CMOS structure */

pcmos = 0;
/* structure offset is zero */
wr_rtc(kpcmos->regb,
/* prepare to init */
imask(1, 0, 0);
/* disable PIC interrupt */
iv_init(Ox70);
/* initialize RTC interrupt vector */
wr_rtc(kpcmos->rega, DIVIDE_SEL
RATE_SEL);
/* set pi rate */
wr_rtc(kpcmos->alr_hr, OxOO);
/* write hours alarm */
wr_rtc(kpcmos->alr_min, OxOO);
/* write minutes alarm */
wr_rtc(kpcmos->alr_sec, OxOO);
/* write seconds alarm */
);
/* enable clock */
wr_rtc(kpcmos->regb, AlE I UIE I PIE I CLK24
imask(1, 0, 1);
/* enable PIC interrupt */
}

5- 34

Real-time Clock and CMOS RAM - Programming Example

Restoring the Interrupt Vectors
To shut down real-time clock interrupt processing, the rtcJest function:
• Disables the real-time clock interrupts
• Masks the interrupt controller input
• Restores the interrupt vector to its previous condition
NOTE
Update cycles remain enabled. If update cycles are disabled, the
clock stops.
/***********************************************************************/
/* rtc_rest() - disable interrupts and restore vectors
*/
/***********************************************************************/
rtc_restO
{

CMOS *pcmos;
pcmos = 0;
wr_rtc(&pcmos->regb, CLK24);
imask(l, 0, 0);
iv_rest(Ox70);

/* ptr to RTC/CMOS structure */
/* structure offset is zero */
/* disable clock interrupts */
/* disable PIC interrupt */
/* restore interrupt vector */

}

Real-time Clock and CMOS RAM - Programming Example

5- 35

Real-Time Clock Example
The function rtc displays the menu, accepts input, and execute~ the examples.
/***********************************************************************/
/* rtc() - execute RTC examples
*/
/***********************************************************************/
rtcO
{

static MESSAGE mrtc[) =

/* rtc menu */

{
{ 3,
{ 6,
{ 6,
{ 7,
{ 8,
{ 9,
{ 10,
{ 11,
{ 12,
{ 0,

24, "Real-time Clock and CMOS Example" },
24, "Fl. Display CMOS hardware setup" },
24, "F2. Display CMOS checksum" },
24,. "F3. Display calculated CMOS checksum" },
24, "F4. Set CMOS checksum" },
24, "F5. Set date" },
24, "F6. Set time" },
24, "F7. Set day-of-week" },
24, "FlO. Return to Main menu" },
0, o },

};

unsigned char tmp;
unsigned char sum;
char line[512);
int i;
int r;
DATIM dt;
CMOS *pcmos;

/* to hold CMOS byte read */
/* to hold calculated checksum */
/* to hold input line */
/* to hold menu selection */
/* temp value */
/* place to store date t time */
/* ptr to RTC/CMOS structure */

#define ROW 16
#define COL 17
pcmos = 0;
line[O) = 0;
while (1)

/* structure offset is zero */
/* null terminated */
/* forever (see FlO) */

{

disp_menu(mrtc);
switch(line[O)

/* display the rtc menu */
/* determine menu selection */

{

case Fl:
sh_hdwO;
break;

5- 36

/* show CMOS hardware */

Real-time Clock and CMOS RAM - Programming Example

case F2:
sprintf (line , "CMOS checksum = %02x",
rd_rtc(&pcmos->cksuml»;
disp_str (ROW , COL, line);
break;

/* get current checksum */

case F3:
/* calculate checksum */
sprintf (line, "Calculated checksum = %02x", rtc_cksumO);
disp_str(ROW, COL, line);
break;
case F4:
sum = rtc_cksum();
/* write calculated checksum */
wr_rtc(&pcmos->cksuml, sum);
sprintf (line , "Checksum byte set to %02xH", sum);
disp_str(ROW, COL, line):
break;
case F6:
while (1)

/* set new date */

{

disp_str(ROW
, COL,"Enter date as MM/DD/YVYY");
disp_str(ROW + 1, COL, "Where MM represents the month (1 - 12)");
disp_str(ROW + 2, COL, "Where DD represents the day (1 - 31)"):
disp_str(ROW + 3, COL, "Where YVYY represents the year (0000 9999)");

disp_str(ROW + 4, COL, "Date: II):
get_keys(ROW + 4, COL + 6, line);
r = sscanf (line , "%2d/%2d/%4d", &dt.month,
&dt.dom, &dt.year):
if(r != 3) continue:
else break:
}
/* note: no limit check */
wr_rtc(&pcmos->month, bcd(dt.month»:
/* write month */
wr_rtc(tpcmos->dom, bcd(dt.dom»:
/* write day-of-month */
wr_rtc(&pcmos->year, bcd(dt.year % 100»:
/* write year */
wr_rtc(&pcmos->century, bcd(dt.year / 100»; /* write century */
rd_rtc(&pcmos->regd):
/* make date valid, set the VRT bit */
shw_dateO:
disp_menu(mrtc):
break:
case F6:
while (1)

/* set new time */

{

, COL, "Enter time as HH:MM:SS"):

Real-time Clock and CMOS RAM - Programming Example

5- 37

disp_str(ROW + 1, COL, "Where HH represents the hour (0 - 23)"):
disp_str(ROW + 2, COL, "Where MM represents the minutes (0 - 69)"):
disp_str(ROW + 3, COL, "Where SS represents the seconds (0 - 69)");
disp_str(ROW + 4, COL, "Time: ");
get_keys(ROW + 4, COL + 6, line);
r = sscanf (line , "%2d:%2d:%2d", tdt.hours, tdt.minutes,
tdt.seconds);
if(r != 3) continue;
else break;
}
/* note: no limit check */
wr_rtc(tpcmos->hours, bcd(dt.hours»;
/* write hours */
wr_rtc(tpcmos->minutes, bcd(dt.minutes»;
/* write minutes */
wr_rtc(l:pcmos->seconds, bcd(dt.seconds»;
/* write seconds */
rd_rtc(tpcmos->regd);
/* make time valid, set the VRT bit */
shw_timeO;
disp_menu(mrtc);
break;
case F7:
while (1)
{

disp_str(ROW, COL, "Enter day-of-week (1 - 7): II);
get_keys (ROW, COL + 27, line);
r = sscanf(line, "%d" , tdt.dow);
if(r != 1) continue;
else break;
}
/* note: no limit check */
wr_rtc(tpcmos->dow, bcd(dt.dow»;
/* write day-of-week */
rd_rtc(tpcmos->regd);
/* make DOW valid, set the VRT bit */
shw_dateO;
disp_menu(mrtc);
break;
case FlO:
return;

/* return to caller (main menu) */

}

line[O] = get_fkey();

/* get a function key for menu selection */

}
}

5- 38

Real-time Clock and CMOS RAM - Programming Example

Chapter 6
Three-Channel Counter
and Speaker
Overview
The VAXmate processor board has an 8254 programmable interval timer that
provides three independent I6-bit counters for counting or timing. All three
counters have a 1.1931816 MHz clock input. The counters are programmable
and are used by the ROM BIOS as follows:
• Counter 0 is a general purpose timer to provide:
A time-of-day clock
A diskette drive motor timer
A screen blanking timer
Its output goes to IRQO of the interrupt logic.
CAUTION: Reprogramming this counter can destroy the timing.
• Counter 1 provides the dynamic RAM refresh timing. The ROM BIOS
programs it for a 15 I1S cycle time. Its output is connected to the refresh
counter.
CAUTION: Reprogramming this counter can destroy the refresh cycle.
• Counter 2 provides a frequency-modulated square wave output for the
speaker interface.

Additional Source of Information
The following Intel Corporation document provides additional information on
the 8254 three-channel counter/timer.

• Microsystems Components Handbook {Publication Number 230843)

Three-Channel Counter and Speaker - Hardware Description

6- 1

Block Diagram
Figure 6-1 shows the block diagram of an 8254. The data bus buffer interfaces
the I/O data bus; and the read/write logic interfaces the address bus on the
CPU module.

I/O
Data
Bus 'I

Data
Bus
Buffer

I
RD

va
AO
Al

..--

Time of
Day Clock.

Clk 0
Gate 0

I
N

Counter 0

Out 0
(IRQO)

T
E

Read/
Vrite
Logic

N
A
L

Refresh
Timing

Clk 1
Gate 1

Counter 1

Out 1
(Refresh)

Control
Vord
Register

Speaker
Vaveform

Clk 2
Gate 2

Counter 2

Out 2
(Speaker)

1
Figure 6·1

Three-Channel Counterrrimer Block Diagram

Counter Description
The three 16-bit synchronous down counters are identical in operation, but fully
independent. Each counter has two 8-bit input latches Icountregisters), two 8bit output latches, and a counting element. The counter control logic enables
only one latch at a time. Therefore, writing a 16-bit count requires two 8-bit
writes to the same register and reading a 16-bit count requires two 8-bit reads
from the same register.
The control word register provides for 8-bit and 16-bit counts. The 8-bit count
can be written to either the least significant byte ILSB) or the most significant
byte IMSB). Loading one 8-bit count register of a 16-bit pair clears the other
count register. That is, writing an 8-bit count to the LSB clears the MSB and
writing an 8-bit count to the MSB clears the LSB.

6- 2

Three-Channel Counter and Speaker - Hardware Description

The signals CLK, GATE, and OUT are all connected to control logic on the
CPU module. A 14.31818 MHz signal divided by 12 provides a 1.1931816 MHz
clock to all three counters.
A high level (1t at the GATE input enables counting and a low level (Ot at the
GATE input disables counting.
Table 6-1 shows the CLK input frequency, the GATE source, and the destination of the OUT signal.
Table 6-1

Counter Signals

Counter

CLK Frequency

GATE Source

OUT Destination

1.1931816 MHz
1.1931816 MHz
1.1931816 MHz

Tied high
Tied high
System CSR (bit Ot

IRQO
Refresh timer
Speaker driver

1
2

Mode Definitions
The three-channel counter/timer has six modes of operation:
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5

Interrupt on Terminal Count
Hardware Retriggerable One-Shot (not usedt
Rate Generator
Square Wave Mode
Software Triggered Strobe
Hardware Triggered Strobe (retriggerablet

Table 6-2 lists the default mode and function of each counter in the VAXmate
workstation (as established by the ROM BIOSt.
Table 6-2

Modes Used by the Three Counters

Counter Function

Mode

Description

Output

Time-of-day clock

Hardware triggered strobe

IRQO

Refresh timing

Rate generator

Refresh counter

Speaker waveform 3

Square wave

Speaker driver

Three-Channel Counter and Speaker - Hardware Description

6- 3

Mode 0 (Interrupt on Terminal Count)
Mode 0 is used for one-shot event counting.

Initializing Mode 0
Programming the control word for mode 0 causes OUT to go low. The GATE
input has no effect on the OUT signal.
If a new count is written during counting, the new count is loaded on the next

CLK pulse and counting continues from the new count.

Mode 0 Cycle
Writing a new count starts the cycle. Where n equals the count, the mode 0
cycle is n + 1 CLK pulses long. During the start of the cycle, the OUT signal
is low for n CLK pulses (while the counter decrements from n to 0.) On the
next CLK pulse, the OUT signal makes a transition from low-to-high. The OUT
signal remains high until the control word is written or until a new count is
written.

Mode 1 (Hardware Retriggerable One-Shot)
Mode 1 is used for one-shot event counting. Because the GATE input is the
trigger, mode 1 is viable only on counter 2 (the GATE input of counters and
1 are tied high.) Mode 1 could be used for sound generation, but it is not normally used on the VAXmate workstation.

Initializing Mode 1
Programming the control word for mode 1 and writing a new count causes
OUT to go high and arms the trigger. The GATE input has no effect on the
OUT signal.
Writing a new count during counting has no effect on the current count.
However,.if the GATE input is triggered, the cycle restarts with the new count.

Mode 1 Cycle
With the trigger armed, a low-to-high transition at the GATE input triggers
the cycle. On the next CLK pulse, the count is loaded and the OUT signal
makes a high-to-Iow transition. Where n equals the count, the OUT signal remains low for n CLK pulses. That is, when the count decrements to 0, the
OUT signal goes high.
After the trigger is armed for the first time, the trigger remains armed until
the control word is reprogrammed. Thus, after a count has decremented to 0,
triggering the GATE input restarts the cycle. The count is reloaded

6- 4

Three-Channel Counter and Speaker - Hardware Description

automatically.
Triggering the GATE input before a count decrements to 0 restarts the cycle
on the next CLK pulse. The count is reloaded automatically. Because the count
did not expire, the OUT signal remains low.

Mode 2 (Rate Generator)
Where n equals the initial count, mode 2 functions like a divide by n counter.
It generates pulses at a rate equal to the input frequency divided by the initial
count I nl. Mode 2 is periodic, repeating the cycle every n CLK pulses.
The ROM BIOS uses counter 1 in mode 2 to provide the refresh timing signal.

Initializing Mode 2
Programming the control word for mode 2 causes OUT to go high. Providing
that the GATE input is high, the cycle starts 1 CLK pulse after the initial
count is written.
If the GATE input goes low, the OUT signal goes high immediately. On the

CLK pulse following a low-to-high transition at the GATE input, the counter
reloads the initial count. Thus, the GATE input can synchronize the count to
an external event.
Writing a new count during counting has no effect on the count for the current
cycle. When the cycle repeats, the count is reloaded with the new count.
However, if the GATE input is triggered, the new count is loaded on the next
CLK pulse and cycle restarts.

Mode 2 Cycle
Where n is the initial count, the mode 2 cycle is n CLK pulses long. During
the start of the cycle, the OUT signal is high. The OUT signal remains high
until the count decrements to 1. When the count decrements to 1, the OUT
signal makes a high-to-Iow transition and the counter reloads the initial count.
The OUT signal is low only for that CLK pulse. On the next eLK pulse, the
OUT signal goes high and the cycle repeats.
NOTE
In mode 2, a count of 1 is invalid.

Mode 3 (Square Wave Mode)
Mode 3 generates a square wave at the OUT signal. Where n is the count, the
OUT signal has a frequency equal to CLK I n. When n is an even number, the
OUT signal is high for n I 2 CLK pulses and then low for n I 2 CLK pulses.
When n is an odd number, the OUT signal is high for In + 11 I 2 CLK pulses
and then low for In - 11 I 2 CLK pulses.
Three-Channel Counter and Speaker - Hardware Description

6- 5

Initializing Mode 3
Programming the control word for mode 3 causes OUT to go high. Providing
that the GATE input is high, the cycle starts 1 clock pulse after the initial
count is written.
If the GATE input goes low, the OUT signal goes high immediately. On the

CLK pulse following a low-to-high transition at the GATE input, the counter
reloads the initial count. Thus, the GATE input can synchronize the count to
an ~xternal event.
Writing a new count during counting has no effect on the count for the current
cycle. When the cycle repeats, the count is reloaded with the new count.
However, if the GATE input is triggered, the new count is loaded on the next
CLK pulse and cycle restarts.

Mode 3 Cycle
In the first CLK pulse, the initial count is loaded. If the count is odd, then
count - 1 is loaded. The cycle starts with the next CLK pulse.
With each succeeding CLK pulse, the count is decremented by two. When the
count decrements to 0, the initial count is tested for an odd or even value. If
the initial count was even, the OUT signal makes an immediate transition from
high-to-Iow. If the initial count was odd, the counter waits one more CLK pulse
and then makes a high-to-Iow transition. The initial count is reloaded and decremented by two, which starts the second half of the cycle. With each succeeding CLK pulse, the count is decremented by two. When the count decrements
to 0, the OUT signal makes an immediate transition from low-to-high; the initial count is reloaded and decremented by two, which starts a new cycle.

Mode 4 (Software Triggered Strobe)
In mode 4, the count cycle is triggered by writing a new count. Where n equals
the initial count, the OUT signal is high for n + 1 eLK pulses, low for 1 CLK
pulse, and then high until a new count is written.

Initializing Mode 4
Programming the control word for mode 4 causes OUT to go high. The GATE
input has no effect on the OUT signal.
If a new count is written during counting, the new count is loaded on the next

CLK pulse and counting continues from the new count.
For a 2-byte count, writing the first byte has no effect on counting. Writing the
second byte allows the count to be loaded on the next CLK pulse.
Writing a new count while the original count is counting allows the new count
to be loaded on the next CLK pulse.
6- 6

Three-Channel Counter and Speaker - Hardware Description

Mode 4 Cycle
The mode 4 cycle is triggered by writing a new count. The new count is loaded
on the next CLK pulse, but not decremented. With each successive CLK pulse,
the count is decremented .. When the count decrements to 0, the OUT signal
goes low. It remains low for 1 CLK pulse. When the count decrements to
FFFFH, the OUT signal goes high. Until a new count is written, the OUT
signal remains high, which restarts the cycle.

Mode 5 (Hardware Triggered Strobe)
Because the GATE input is the trigger, mode 5 is viable only on counter 2 (the
GATE input of counters 0 and 1 are tied high.) Where n. equals the initial
count, the OUT signal is high for n. + 1 CLK pulses, low for 1 CLK pulse,
and then high until the GATE input triggers another cycle.

Initializing Mode 5
Programming the control word for mode 1 and writing a new count causes
OUT to go high and arms the trigger. The GATE input has no effect on the
OUT signal.
Writing a new count during counting has no effect on the current count.
However, if the GATE input is triggered, the cycle restarts with the new count.

Mode 5 Cycle
With the trigger armed, a low-to-high transition at the GATE input triggers
the cycle. The new count is loaded on the next CLK pulse, but not decremented. With each successive CLK pulse, the count is decremented. When the
count decrements to 0, the OUT signal goes low. It remains low for 1 CLK
pulse. When the count decrements to FFFFH, the OUT signal goes high.
After the trigger is armed for the first time, the trigger remains armed until
the control word is reprogrammed. Thus, after a count has decremented to 0,
triggering the GATE input restarts the cycle.
Triggering the GATE input before a count decrements to 0 restarts the cycle
on the next CLK pulse. The count is reloaded automatically. Because the count
did not expire, the OUT signal remains high.

Three-Channel Counter and Speaker . Hardware Description

6- 7

Registers
This section discusses the 8254 registers. Because bit 0 controls the GATE
input of counter 2 and bit 1 controls the output to the speaker, the system
register is also discussed here. Table 6-3 shows the addresses of the 8254 registers and the system register.
Table 6-3

8254 and System Register Addresses

RIW

Address

8254 - Counter 0
8254 - Counter 1
8254 - Counter 2
8254 - Command Word
System

R/W
R/W
R/W
W
R/W

0040H
0041H
0042H
0043H
0061H

6- 8

Three-Channel Counter and Speaker - Hardware Description

System Register (0061H)
7

654

I/O
PARITY CHECK
CHECK

RAM

R/W Description

RAM PARITY CHECK
0= Processor board RAM parity good
1 = Processor board RAM parity error

Always 0

110 CHECK
0= No bus 110 error or option RAM parity error
1 = Bus 110 or option RAM parity error exists

Always 0

COUNTER 2 OUT SIGNAL
0= Counter 2 OUT signal is low
1 = Counter 2 OUT signal is high

Always 0

REFRESH REQUEST
0= Refresh request not active
1 = Refresh request active

COUNTER REFRESH ENABLE ENABLE SPEAKER COUNTER
DATA
RAM
2
2 OUT REQUEST I/O
SIGNAL
GATE
CHECK PARITY
INPUT

Bit

The diagnostic software uses this bit to check the operation of the
DRAM refresh circuitry.
W

Always 0

R/W ENABLE 110 CHECK
0= Enables checking of the bus 1/0 check line and option RAM
parity (enabled by ROM BIOS)
1 = Disable bus 1/0 error checking

R/W ENABLE RAM PARITY CHECK
0= Enable processor board RAM parity checking (enabled by
ROM BIOS)
1 = Disable processor board RAM parity checking

Three-Channel Counter and Speaker - Hardware Description

6- 9

Bit

RIW Description (System Register - cont.)

R/W SPEAKER DATA
o = No sound output from speaker
1 = Sound output from speaker (Counter 2 OUT signal must be
high or generating a frequency)
The output of this bit is ANDed with the Counter 2 OUT
SIGNAL. Assuming that the counter 2 OUT signal is high, toggling this bit generates a pulse train to the speaker driver.
Otherwise, to enable sound output to the speaker, this bit must
equal 1.

6- 10

R/W COUNTER 2 GATE INPUT
o = Counter 2 GATE input is low
1 = Counter 2 GATE input is high

Three-Channel Counter and Speaker - Hardware Description

Control Word Register (OO43H)
6

SELECT
COUNTER

READ!

2
I

MODE
SELECT

WITE
I

Bit

RIW Description

7-6

SELECT COUNTER
00 = Select counter 0
01 = Select counter 1
10 = Select counter 2
11 = Read-back command

5-4

READ/WRITE
00 =
Counter-latch command
01 =
Read/Write LSB
10 = Read/Write MSB
11 = Read/Write LSB first, then MSB *

3-1

MODE SELECT
000 = Mode 0
001 = Mode 1
X10 = Mode 2
XII = Mode 3
100 = Mode 4
101 = Mode 5

o
BINARY
CODED
DECIMAL

BINARY CODED DECIMAL

o = Binary counter 16 bits
.
1 = Binary-coded-decimal (BCD) counter (4 decades)

* The counter does not start counting until the second byte of the 2-byte
pair is written to the counter latch.

Three-Channel Counter and Speaker - Hardware Description

6 - 11

Counter-Latch Command (Control Word Register)
7

~~ I I I I I I I

COUNTER

Bit

R/W Description

7-6

SELECT COUNTER
00 =
Select Counter 0
01 = Select Counter 1
10 =
Select Counter 2
11 =
Undefined

5-0

Always 0 for counter-latch command

Counter-latch commands do not affect the programmed mode of the counter.
The counter-latch command latches the contents of the counters without affecting the count in progress. When the 8254 receives a counter-latch command, it
latches the selected counter into the counters output latch. The latched count
is held until read by the CPU (or until the counter is reprogrammed). After the
latched count is read, the output latch follows the count in the counter.
When a counter-latch command is issued for more than one counter, each
counter output latch holds the count until read. When any given counter is
latched two or more times without an intervening read, only the first latch
command is effective. When read, the count is the count latched by the first
counter-latch command.
The latched count must be read according to the programmed format (LSB,
MSB, or LSB and MSB).

6- 12

Three-Channel Counter and Speaker - Hardware Description

Read-Back Command (Control Word Register)
7

LATCH
COUNT

LATCH
STATUS

COUNTER COUNTER COUNTER
2

SELECT

Bit

R/W Description

7-6

Always 11

5-4

LATCH COUNT and LATCH STATUS
Latch status and count of selected counter(s)
00 =
01 =
Latch count of selected counter(s)
10 =
Latch status of selected counter(s)
11= Undefined

COUNTER 2 SELECT
0= Counter 2 not selected
1 = Counter 2 selected

COUNTER 1 SELECT
0= Counter 1 not selected
1 = Counter 1 selected

COUNTER 0 SELECT
0= Counter 0 not selected
1 = Counter 0 selected

Always 0

The read-back command is written to the control word register. For the selected counters, the read-back command latches a status byte and/or the current count.
The status byte format is described under Status Response. The status byte is
read from the indicated counter register as a single 8-bit byte. When the readback command latches both status and count, the status byte is read first and
then the count. Thereafter, any read returns an unlatched count.
The latched count follows the format described under Counter-Latch Command.
If multiple read-back commands are issued without intervening reads, all but
the first are ignored. The status read is the status at the time of the first
read-back command.

Three-Channel Counter and Speaker - Hardware Description

6- 13

Status Response (Read-back Command)
7

4
I

OUT
PIN

NULL

COUNT

READI

VRITE
I

Bit

RIW l>escription

3
I

1
I

SELECTED
MODE
I

o
BINARY
CODED
DECIMAL

OUT PIN
1 = OUT pin is high U)
o = OUT pin is low (0)
NULL COUNT

o = New count is loaded and is available for reading.
1 = Null count
A write to the control word register has occurred, which sets the
null count bit of specified counter. If the counter is programmed
for 2-byte counts, when the second byte is written, the null count
goes to 1.

5-4

3-1

6- 14

READ/WRITE
00 = Counter-latch command
01 = Read/Write LSB
10 = Read/Write MSB
U = Read/Write LSB first, then MSB.
SELECTED MODE
000 = Mode 0
001 = Mode 1
X10 = Mode 2
XU = Mode 3
100 = Mode 4
101 = Mode 5
BINARY CODED DECIMAL

o = Binary counter 16 bits
1 = Binary-coded-decimal (BCD) counter (4 decades)

Three-Channel Counter and Speaker - Hardware Description

This page is intentionally blank.

Three-Channel Counter and Speaker - Hardware Description

6- 15

Programming Example
The three channel counter/timer and speaker programming example
demonstrates:
• Writing the counter/timer registers
• Enabling and disabling the output to the speaker
• Setting the output frequency to the speaker
The example provides routines as described in the following list:
wr cntl6
beep
unbeep
tim_spk

Writes a 16-bit value to the indicated counter
Enables the bell (beep) at the speaker
Disables the bell (beep) at the speaker
Initializes the counter, displays the menu, and executes the example program

Constant Values
The included file kyb.h defines constant values for function keys. For information about keyboard programming, see Chapter 8. For a listing of the file
kyb.h, see Appendix A.
The included file example.h defines the structure type MESSAGE that is used
to display the menu. For a listing of the fHe example.h, see Appendix A.
The constant value systat defines the offset of the system status register in
I/O space.
The constant values cwrdreg through count2 define the offset of the 8254
counter/timer registers in I/O space.
The constant values selcntO through rbcnt2 define the bit values of various
8254 counter/timer commands.
The constant value inpfreq defines the input frequency to all three counterl
timers.

6- 16

Three-Channel Counter and Speaker - Programming Example

#include "kyb.h"
#include "example.hl!

/* reference function key constants */
/* reference menu structure */

/***********************************************************************/
/* define constants used to program 8254 timer

/***********************************************************************/
Ox61

/* system status register in I/O space */

#define CWRDREG Ox43
#define COUNTO Ox40
#define COUNT 1 Ox41
#define COUNT2 Ox42

/* control word register in I/O space */
/* counter 0 register in I/O space */
/* counter 1 register in I/O space */
/* counter 2 register in I/O space */

#define SELCNTO OxOO
#define SELCNTI Ox40
'define SELCNT2 Ox80
'define SELRDBK Ox CO

/* select counter 0 */
/* select counter 1 */
/* select counter 2 */
/* select read back */

#define SYSTAT

'define LATCOM
'define RWLSB
#define RWMSB
'define RWLSMS

OxOO
Oxl0
Ox20
Ox30

/* select latch command */
/* read/write LSB */
/* read/write MSB */
/* read/write LSB then MSB */

'define TMODEO
'define TMODEI
'define TMODE2
'define TMODE3
'define TMODE4
#define TMODE5

OxOO
Ox02
Ox04
Ox06
Ox08
Ox09

/* select timer mode 0 */
/* select timer mode 1 */
/* select timer mode 2 */
/* select timer mode 3 */
/* select timer mode 4 */
/* select timer mode 5 */

#define BINDAT
#define BCDDAT

OxOO
OxOl

/* binary count data */
/* binary coded decimal count data */

'define LATCNT
#define LATSTA
#define RBCNTO
'define RBCNTI
'define RBCNT2

Ox20
Oxl0
Ox02
Ox04
Ox08

/* read back cmd latch count */
/* read back cmd latch status */
/* read back counter 0 */
/* read back counter 1 */
/* read back counter 2 */

'define INPFREQ 1193181L

/* 14.31818 Mhz / 12 - 1.1931816 Mhz */

Three-Channel Counter and Speaker - Programming Example

6- 17

Writing a Counter
The function wr cnt16 writes a 16-bit value to the indicated counter. A 16-bit
value is written 8-bits at a time (low byte firstl to the same port.

Making a Bell Sound
The function beep enables the speaker output at 1000 Hz. It provides the bell
(beep sound1 for the ASCII character BEL (07HI. This function can be called at
any time. The speaker output is automatically disabled by the function unbeep.
The function unbeep monitors the variable beep flag. If required, it disables the
speaker. This function is called from within the real time clock interrupt handler. It tracks the number of 125 ms periods that the speaker has been on for
a bell (beep soundl. After 500 ms total, the speaker output is disabled. If the
real time clock interrupts are not enabled, the speaker output will not be
disabled automatically.

6- 18

Three-Channel Counter and Speaker - Programming Example

1***********************************************************************1
1* wr_cnt16(} - write 16-bit value to counter
*1
1***********************************************************************1
wr_cnt16 (counter , value}
unsigned char counter;
unsigned int value;

1* which counter to set *1
1* 16-bit value *1

{

unsigned int intr_flag;
intr_flag = int_off(};
outp(counter I COUNTO, value i Oxff};
outp(counter I COUNTO, value » 8};
int_on(intr_flag};

1* to hold current IF state *1
1* disable interrupts *1
1* write counter low byte "'/.
1* write counter high byte *1
1* enable interrupts *1

}

1***********************************************************************1
1* beep(} - start up beep sound at speaker
*1
1***********************************************************************1
int beep_flag;
1* true while beeping *1
beepO
{

wr_cnt16(2, (int) (INPFREQ I 1000L)};
outp(SYSTAT, Ox03};
beep_flag '" 1;

1* set desired frequency *1
1* turn speaker on *1
1* set flag, speaker is on *1

}

1***********************************************************************1
1* unbeep(} - time to stop beep sound at speaker ?
*1
1***********************************************************************1
unbeepO
{

if (beep_flag)
if(++beep_flag > 3}

1* are we making a beep sound *1
1* has it been on long enough *1

{

outp(SYSTAT, OxOO};
beep_flag = 0;

1* turn it off *1
1* reset flag *1

}
}

Three-Channel Counter and Speaker - Programming Example

6- 19

Counter and Speaker Example
The function tim spk initializes the counter, displays the-menu, and executes
the example.
-

/***********************************************************************/
/* tim_spk() - execute timer and speaker examples

/***********************************************************************/
tim_spkO
{

static MESSAGE mtim_spk[] =

/* menu for timer/speaker example */

{

3, 24, "8254 Timer and Speaker Example" },
5, 24, "Fl. Set frequency to speaker" },
6, 24, "F2. Speaker on" },
7, 24, "F3. Speaker off" },
8, 24, "F4. DO-RE-MI" },
9, 24, "FlO. Return to Main menu" },

{

{
{
{

{

o },

};

static int tone[8] =
/* frequencies for notes to do-re-mi */
{
2281, 2032, 1810, 1709, 1524, 1366, 1209, 1140 };
char line[512];
unsigned int freq;
unsigned int tval;
unsigned int i;
extern unsigned int metronome;

/* to hold input line */
/* to remember frequency */
/* general temporary */
/* iteration control */
/* defined in clock example */
/* maintains beat of do-re-mi */

#define ROW 16
#define COL 17
line[O] = 0;
freq = 1000;

/* default frequency */
/* initialize counter mode */
outp(CWRDREG, SELCNT2 I RWLSMS I TMODE3 I BINDAT);
while (1)

{

disp_menu(mtim_spk);
switch(line[O])
{

case Fl:
/* set output frequency */
disp_str(ROW, COL, "Enter new frequency (t9Hz - 20000Hz):");

6- 20

Three-Channel Counter and Speaker - Programming Example

get_keys (ROW, COL + 37, line);
sscanf(line, "%d" , lfreq);
if(freq < 18) freq = 19;
else if(freq > 20000) freq = 20000;
tval = (int)(INPFREQ / (long)freq);
wr_cnt16(2, tval);
disp_menu(mtim_spk);
break;
case F2:
outp(SYSTAT, Ox03);
break;

/* turn speaker on */

case F3:
outp(SYSTAT, OxOO);
break;

/* turn speaker off */

case F4:
i = 0;

metronome = Oxffff;
while (metronome) ;
wr_cnt16(2, tone[i++]);
outp(SYSTAT, Ox03);
while(i < 9)

/* play do-re-mi */
/* iteration count = 0 */
/* prepare counter to overflow */
/* wait until it overflows */
/* start first note */
/* enable speaker */
/* do all notes */

{

/* hold note for 500 ms */

if (metronome > 3)
{

/* next note */
/* reset counter */

wr_cnt16(2, tone[i++]);
metronome = 0;

/* redisplay time for menu ? */
}

outp(SYSTAT, OxOO);
tval = (int)(INPFREQ / (long)freq);
wr_cnt16(2, tval);
break;
case FlO:
return;

/* turn speaker off */
/* reset frequency */

/* return to caller */

}

line[O]

= get_fkey();

/* get function key */

}
}

Three-Channel Counter and Speaker . Programming Example

6- 21

Chapter 7
Video Controller
Introduction
The VAXmate video controller is on the 110 board and drives a monochrome
monitor. The video controller can process 16 colors or shades of gray. In this
chapter, the term color also means shades of gray or intensity levels.

Industry-Standard Text and Graphics Features
The VAXmate video controller has the following industry-standard text and
graphics features:
•

80 x 25 and 40 x 25 text display

•

8 x 8 graphics character cell

•

character attributes:
16 foreground colors
16 background colors or 8 background colors plus blink

•

bit map graphics with industry-standard color palettes
320 x 200 4 colors
640 x 200 2 colors

Video Controller - Hardware Description

7- 1

Enhancements to Industry-Standard Features
The video controller has the following enhancements to industry-standard
features:
•

The screen resolution is 640 horizontal pixels by 400 scan lines.
Industry-standard graphics (200 scan lines) is accomplished by
displaying each scan line twice.

•

The character pattern is 8 horizontal pixels by 16 scan lines, resulting in higher quality characters in text modes.

•

The 256-character font RAM provides flexibility in terminal emulation and multilingual applications.

•

The dual-port video memory eliminates annoying screen flicker (disabling the screen before accessing video memory is unnecessary).

•

The 16-bit data path to video memory, coupled with the dual-port
access results in faster screen updates.

Industry-Standard Features Not Available
The video controller does not support these features:
•
•
•
•

160 x 100 16-color graphics mode
15.75 KHz monitor support
Border color support
Light pen support

Extra Features
The video controller has the following additional graphic features:
•
•
•
•
•
•

7- 2

640 x 400 2-color graphics
640 x 400 4-color graphics
640 x 200 4-color graphics
800 x 252 4-color graphics
320 x 200 16-color graphics
256-character soft font

Video Controller - Hardware Description

Block Diagram
The video controller consists of a display processor and video memory that
reside on the 110 board. As shown in Figure 7-1, the display processor includes
a translation ROM, a 6845 CRT controller, text video logic, graphics video
logic, a video look-up table, and status and control registers.

VIDEO GATE ARRAY
16BIT
DATA
BUS

4 KBYTE FONT RAM ~ IGRAPHICS VIDEO LOGIC I

I 64 KBYTE VIDEO RAM ~ ITEXT VIDEO LOGIC
I

6845 CRT CONTROLLER ~

ITRANSLATION ROM

~
8
BIT

1/0

BUS

I
I

STATUS REGISTERS I IVIDEO LOOK-UP TABLE I
CONTROL REGIST2RSI

I MONITOR INTERFACE I
Figure 7-1

Block Diagram of the VAXmate Video Controller

The translation ROM translates industry-standard color graphic adapter data to
data that is correct for the DIGITAL video controller.
The 6845 CRT Controller (CRTC) internal registers control horizontal and vertical positioning. synchronization, video and cursor starting addresses, and
width of video display.
Two status registers monitor vertical synchronization, video blanking time, and
various modes in the control registers.
The two control registers enable the various text and graphics modes, enable
and disable the display, select the font RAM, select the video look-up table
(VLT) , and provide screen saver support.

Video Controller - Hardware Description

7- 3

64K bytes of dual-ported memory. which maps into the address space of the
VAXmate CPU.
The display processor converts memory data into various raster formats. The
display processor generates IROB outputs that drive the monochrome monitor.
The VAXmate monitor displays the color information as different levels of intensity ~shades of gray).

Additional Sources of Information
The following documents provide additional information on the video controller:
Device

Company

Document

6845-1
HD46505S

Motorola
Hitachi

8·Bit Microprocessor & Peripheral Data
8116·Bit Multi·Chip Microcomputer Data Book

7- 4

Video Controller - Hardware Description

Video Modes
The video controller has several modes, some of which have a mode number
assigned indicating that the ROM BIOS supports these modes. For modes not
supported by the ROM BIOS, the hardware must be programmed directly.
Table 7-1 shows the available video modes.
For industry-standard color graphic adapters, the difference between a color
and a monochrome mode is the presence (color) or absence (monochrome) of the
color burst signal in the composite video output. Because the VAXmate video
controller does not provide a composite video output, there is no difference between the color and the monochrome modes.
On powerup or system reset, the video system is initialized to mode 03H.
Table 7-1

Available Video Modes

Mode Size
OOH
01H
02h
03h
04H
05h
06h
dOh
d1h
d2h

*
**

40 x 25
40 x 25
80 x 25
80 x 25
320 x 200
320 x 200
640 x 200
320 x 200
640 x 400
640 x 400
800 x 252
640 x 200

Description
text mode monochrome (industry-standard)
text mode color (industry-standard)
text mode monochrome (industry-standard)
Text mode color (industry-standard)
4-color graphics mode (industry-standard)
monochrome graphics (industry-standard)
monochrome graphics mode (industry-standard)
16-color graphics mode (digital extended) *
2-color graphics mode (digital extended)
4-color graphics mode (digital extended)
4-color graphics mode (digital extended) **
4-color graphics mode (DIGITAL extended) *

No ROM BIOS support
Limited ROM BIOS support

Video Controller - Hardware Description

7- 5

Text Modes
The video controller has a 16 Kbyte text buffer in the address range B8000HBBFFFH. Video modes OOH, 01H, 02H, and 03H use the text buffer.
For modes OOH and 01H, the text buffer provides 8 display pages of 2048
bytes each. For modes 02H and 03H, the text buffer provides 4 display pages
of 4096 bytes each.

Character Buffer Format
A displayed character is represented by two consecutive bytes. The first byte,
of the 2-byte pair, is the character code. The character code is stored at an
even address. The second byte, of the 2-byte pair, is the attribute byte. The
attribute byte is stored at the odd address following the character code. Figure
7-2 shows the character code and attribute byte addressing. Table 7-2 defines
the meaning of each bit within the attribute byte.

B80008 B80018 B80028

Even

Odd

Char
Code

Attr

880038

Even
Char
Code

Odd

BBFFEH BBFFFH

Char
Code

Character Buffer Format

Attribute Byte Bit Definitions

Bit

Symbol

Definition

7
6
6
4
3
2
1

Ib
Rb
Gb
Bb

Background intensity I Blink *
Red contribution to background color
Green contribution to background color
Blue contribution to background color
Foreground intensity
Red contribution to foreground color
Green contribution to foreground color
Blue contribution to foreground color

Rf
Gf
Bf

Attr

--'----""--------'

Table 7-2

Odd

-~--~-,-------,

Attr

-- -- -- -Figure 7-2

Even

-- -- -- --

* The selection of background intensity or blink is determined by bit 7 of
control register A. Control register A is described later in this chapter.
When blink is enabled, the blink frequency is 1.9 Hz.

7- 6

Video Controller - Hardware Description

Character Position to Memory Location Mapping
Character positions on the screen are identified as row (vertical} and column
(horizontal) locations. The first character is displayed in the upper-left corner of
the screen, which is location 0,0. To translate between screen positions and the
address within the text buffer, use the following formula:
Character code address = start_address + (row * 2 * Y) + (column * 2)
Attribute address = Character code address + 1
Where:
start address =

Display page start address (see Table 7-3)

row =

o to 24
o to 79 (80 X 25 modes)
o to 39 (40 X 25 modes)

column =

80 (80 X 25 modes)
40 (40 X 25 modes)

In text modes, the video processor supports multiple display pages. For direct
programming, registers R12 and R13 (described later in this chapter) control
the display-page start address. Each displayed character requires 2 bytes (character code and attribute byte). Therefore, the 80 x 25 modes require 4000
bytes (80 x 25 x 2) and the 40 x 25 modes require 2000 bytes
(40 x 25 x 2). The ROM BIOS also supports multiple display pages and
rounds the memory requirements to 4096 bytes and 2048 bytes respectively.
Table 7-3 shows the display page addresses as defined by the ROM BIOS.

Video Controller - Hardware Description

7- 7

Table 7-3

Text Mode Display Pages (ROM BIOS)

Address

80 x 25
Display Page

40 x 25
Display Page

B8000H

B8800H
B9000H

I
I

B9800H
BAOOOH

BA800H
BBOOOH

2
4

5
3

BB800H

Programmable Cursor
For text modes only, the video controller provides a programmable cursor blink
rate and cursor block size. The cursor blink is determined by bits 6-5 of register RIO. The cursor blinks with alternate foreground and background color of
the character at the cursor position. The cursor block size is controlled by bits
4-0 of registers RIO and RI1. Registers RIO and Rll are discussed later in
this chapter.

7- 8

Video Controller - Hardware Description

Programmable Character Generator (Font RAM)
The video controller has a 4 Kbyte programmable font RAM. The font RAM
can store patterns for 256 characters. Normally, the font RAM is accessible
only to the video controller. That is, the font RAM is not mapped into the
normal CPU address space. Accessing the font RAM requires that the video
mode be one of the text modes OOH, 01H, 02H, or 03H. Bit 4 of control register B (described later in this chapterl controls access to the font RAM. When
bit 4 of control register B equals 1, access to the video text buffer is disabled
and access to the font RAM is enabled. Only even text buffer addresses are
connected to the font RAM. The text buffer to font RAM mapping appears as
follows:
Text Buffer Offset

Font Ram Offset

B8000H
B8001H
B8002H
B8003H
B8004H
B8005H

OOOOH (first byte of font RAM)

B9FFDH
B9FFEH

0001H (second byte of font RAM)
0002H (third byte of font RAM)

OFFFH (last byte of font RAM)

NOTE
The ROM BIOS does not support the use of the font RAM in
any graphics video mode.
A character pattern consists of 16 bytes of pixel information. Each byte represents 8 consecutive pixels of a horizontal scan line for the character. The most
significant bit (bit 7) corresponds to the left-most pixel (pixel 0). The least significant bit (bit 0) corresponds to pixel 7. Each byte of the character pattern is
read or written to an even address. Thus, each character pattern requires 32
bytes of address space and an entire 256-character font requires 8K bytes. To
calculate the address of the first byte of a character pattern, use the following
formula:
Character pattern start address = B8000H + (character code * 32)

Video Controller - Hardware Description

7- 9

Graphics Mode
Each pixel on the screen is mapped into a bit-field of the corresponding byte in
the display buffer. The width of the bit-field can be of 1, 2 or 4 bits depending
on whether a 2-color, 4-color, or 16-color format is chosen.

Mapping the Display to Address
The logical display consists of a rectangular array of 200, 252, or 400 scan
lines of pixels. For 200 scan line mode, the hardware generates two physical
scan lines for each logical scan line. Each scan line is represented by
(M / 8) * n consecutive bytes, where:
M = Number of pixels per scan line
n = 1, for I-bit per pixel ~2-color displayl
n = 2, for 2-bits per pixel ~4-color displayl
n = 4, for 4-bits per pixel U6-color displayl
The memory maps for various graphic formats are shown on the following
pages. Each memory map shows two or more blocks of memory that refer to:
~L MOD PI

Where:
L is the desired scan line
P is the number of memory blocks for the current video mode
R is the remainder of the division LIP

The remainder, R, specifies the memory block for a particular scan line.

7- 10

Video Controller - Hardware Description

320 x 200 4-Color Mode
ROM BIOS Video Modes: 04H and 05H - Industry-Standard
In 4-color mode, a single byte corresponds to 4 consecutive pixels on the screen
with the most significant bit of the byte corresponding to the left of the screen.
See Figure 7-3 for the memory organization. See Figure 7-4 for the pixel to
bit-field map.

1 - - - - - - - 80 DYTES PER SCAN LINE - - - - - - - - 1
B804FB

D8000B

o
I

(L HOO 2)

G
I

D9FOOB

D9F3FB

DAOOOB

DA09FB

V
I

0
E
0

(L HOO 2)

DDFOOB

DDF3FB
L = SCAN LINE 0 TO 199

Figure 7-3

Memory Organization for 320 x 200 4-Color Mode

CDI

CDO

CDl

CDO

CDI

CBO

CDI

CDO

LEFT HOST PIXEL

RIGHT HOST PIXEL

Figure 7-4 Pixel to Bit-Field Map for 4-Color Mode

Video Controller - Hardware Description

7 - 11

320 x 200 16·Color Mode
No ROM BIOS Support· DIGITAL Extended
In 16-color mode, a single byte corresponds to 2 consecutive pixels on the
screen with the most significant bit of the byte corresponding to the left of the
screen. See Figure 7-5 for the memory organization. See Figure 7-6 for the
pixel to bit-field map.

160 BYTES PER SCAN LINE

T IBBmm

(L HOD 4) = 0

(L HOD 4) = 1

(L HOD 4) = 2

BC09PBI

IBBOOOB

(L HOD 4) = 3

B809PBI

D .B9FOOB
I
G
I
T
A . BBEAOB
L
V

B809PBI
B9F3FB.

BA09PBI
BBF3FB .

I .BDEAOB
D

BDF3FB

1
o

BFF3FB

BFEAOB
L = SCAN LINE 0 TO 199
Figure 7-5

Memory Organization for 320 x 200 lO-Color Mode

CB3

CB2

CBt

CBO

CB3

CB2

CBl

eBO

LEFT

PIXEL

I
Figure 7-6

7 - 12

RIGHT PIXEL

Pixel to Bit-Field Map for lO-Color Mode

Video Controller - Hardware Description

640 x 200 2-Color Mode
ROM BIOS Video Mode: 06H - Industry-Standard
In 2-color mode, a single byte corresponds to 8 consecutive pixels on the screen
with the most significant bit of the byte corresponding to the left of the screen.
See Figure 7-7 for the memory organization. See Figure 7-8 for the pixel to
bit-field map.

80 BYTES PER SCAN LINE

B804FB

B8000H

D
I

(L HOD 2) = 0

I
T
A
L

B9FOOH

B9F3FB

BAOOOH

BA09FB

I
D
(L HOD 2) = 1

BBFOOH

BBF3FH
L = SCAN LINE 0 TO 199

Figure 7-7

Memory Organization for 640 x 200 2-Color Mode

CBO

CBO
RIGHT
HOST
PIXEL

LEFT

HOST
PIXEL
Figure 7-8

Pixel to Bit-Field Map for 2-Color (Monochrome) Mode

Video Controller - Hardware Description

7 - 13

640 x 200 4-Color Mode
No ROM BIOS Support· DIGITAL Extended
In 4-color mode, a single byte corresponds to 4 consecutive pixels on the screen
with the most significant bit of the byte corresponding to the left of the screen.
See Figure 7-9 for the memory organization. See Figure 7-10 for the pixel to
bit-field map.

1 - - - - - - - 160 BYTES PER SCAN LINE - - - - - - - - 1
BS09FH

B8000H

D
I
G
I
T

(L HOD 2) = 0

BBDEOH

BBE7FH

BCOOOH

BC09FH

V
I

(L HOD 2)

D
E

BFE7FH

BFDEOH
L = SCAN LINE 0 TO 199
Figure 7·9

Memory Organization for 640 x 200 4·Color Mode

CBl

CBO

CBl

CBO

CBl

CBO

CBl

CBO

RIGHT HOST PIXEL

LEFT HOST PIXEL
Figure 7·10

7 - 14

Pixel to Bit·Field Map for 4·Color Mode

Video Controller . Hardware Description

640 x 400 2-Color Mode
ROM BIOS Video Mode: DOH· DIGITAL Extended
In 2-color mode, a single byte corresponds to 8 consecutive pixels on the screen
with the most significant bit of the byte corresponding to the left of the screen.
See Figure 7-11 for the memory organization. See Figure 7-12 for the pixel to
bit-field map.

1------- 80

T
D
I
G
I
T
A
L
V

B8000H

B809FH
(L MOD 4) = 0

B9FOOH

B9F3PH

BAOOOB
BBFOOH

(L MOD 4)

BA09FHi
BBF3FH

BCOOOB

(L MOD 4)

BC09FHi
BDF3FH_

I
BDFOOH
D i
E
0 BEOOOH

BYTES PER SCAN LINE - - - - - - - - 1

BE09FH
(L MOD 4) = 3

BFFOOH

BFF3FH
L = SCAN LINE 0 TO 399

Figure 7-11

Memory Organization for 640 x 400 2-Color Mode

CBO

CBO
RIGHT
MOST
PIXEL

LEFT

MOST
PIXEL
Figure 7-12

Pixel to Bit-Field Map for 2-Color Mode

Video Controller - Hardware Description

7 - 15

640 x 400 4-Color Mode
ROM BIOS Video Mode: DiH - DIGITAL Extended
In 4-color mode, a single byte corresponds to 4 consecutive pixels on the screen
with the most significant bit of the byte corresponding to the left of the screen.
See Figure 7-13 for the memory organization. See Figure 7-14 for the pixel to
bit-field map.

1------- 160 BYTES PER SCAN LINE - - - - - - - - 1

T
D
I

BOO9FH

BOOOOH
(L MOD 4) = 0

B3DEOH

B3E7FH

I
T
A

B409FH

B4000H
B7DEOH

(L MOD 4)

B7E7FH

B8000H

B809FH

I
D
E
0

BBDEOH

BBE7FH
BC09FH

BCOOOH
(L MOD 4) = 3

BFDEOH

BFE7FH

L = SCAN LINE 0 TO 399
Figure 7-13

Memory Organization for 640 x 400 4-Color Mode

CB1

CBO

CB1

CBO

CB1

CBO

CB1

CBO

LEFT MOST PIXEL
Figure 7-14

7 - 16

RIGHT MOST PIXEL
Pixel to Bit-Field Map for 4-Color Mode

Video Controller - Hardware Description

800 x 252 4-Color Mode
ROM BIOS Video Mode: D2H (Limited ROM BIOS Support) - DIGITAL
Extended
In 4-color mode, a single byte corresponds to 4 consecutive pixels on the screen
with the most significant bit of the byte corresponding to the left of the screen.
See Figure 7-15 for the memory organization. See Figure 7-16 for the pixel to
bit-field map.

1------- 200 BYTES PER SCAN LINE - - - - - - - - i

T
D
I

G
I
T
A

IBOOOOU

BOOC7UI

(L HOD 4) = 0

B30708
B40008

B31378
B4OC78

(L HOD 4)

1B8OOOU

(L HOD 4)

BSOC78
BB1378

IBCOOOB

(L HOD 4) == 3

BCOC78
BP137H

B70708

B71378

V
I
D
E

~B0708

BP0708

I
I

L = SCAN LINE 0 TO 251
Figure 7-15

Memory Organization for 800 x 252 4-Color Mode

CB1

CBO

CB1

CBO

CB1

CBO

CB1

CBO

LEFT HOST PIXEL
Figure 7-16

RIGHT HOST PIXEL
Pixel to Bit-Field Map for 4-Color Mode

Video Controller .. Hardware Description

7 - 17

Video Look-Up Table
The video processor has a video look-up table (VLT) that translates attribute or
graphic color data. The VLT is arranged as 16 words of IRGB output data.
Each location corresponds to one of the 16 possible colors. When the video controller accesses video memory, the attributes or graphic data are used as an
offset into the VLT. The contents of that location in the VLT are sent to the
video output circuit. Because the VLT has only 16 entries, the VLT can alter
the color interpretation of the bit map without rewriting every pixel.
For 2-color mode graphics (640 x 400 or 640 x 200), the foreground color (pixel
equals 1) is determined by the color-select register bits 3-0. The background
color (pixel equals 0) is determined by the contents of VLT entry O. The color
select register is described later in this chapter.
Normally, the VLT is accessible only to the video controller. That is, the VLT
is not mapped into the normal CPU address space. Accessing the VLT requires
that the video mode be one of the text modes OOH, 01H, 02H, or 03H. Bit 2 of
control register B (described later in this chapter) controls access to the VLT.
When bit 2 of control register B equals 1, access to the video text buffer is
disabled and access to the VLT is enabled.
NOTE
Only write access to the VLT is enabled. To read the VLT indirectly, program the video processor for 320 x 200 16-color
mode. For each of the 16 possible colors (OOH-OFH):

7 - 18

Write the same color value to each pixel.

Wait until the display is inactive (register B bit 7
equals 1)

Disable CPU interrupts (CLI instruction)

Wait until the display is active (register B bit 7 equals 0)

Status register A bits 7-4 (lRGB) are equal to the contents of the VLT location specified by the color value.

Enable CPU interrupts (STI instruction)

Video Controller - Hardware Description

Only even-text buffer addresses are connected to the VLT. The text buffer to
VLT mapping appears as follows:

Text
8uffer
Offset

VLT
Offset

Text
8uffer
Offset

VLT
Offset

B80008
880018
880028
880038
880048
880058
880068
880078
880088
B80098
B800AB
880088
B800CH
B800D8
B800E8
B800F8

00008

B80108
880118
880128
880138
880148
880158
880168
880178
880188
880198
8801AB
880188
8801e8
880108
8801E8
8801F8

00088

00018
00028
00038
00048
00058
00068
00078

00098
oooAB
00088
OOOCB

00008
OOOE8
OOOF8

Text mode attributes are referenced in the order IRGB, but the VLT addressing and contents are referenced in the order RGB!. To calculate the offset
accessed by any IRGB value, use the following bit values:
Bit Value

Attribute

I Hntensity)
B (Blue)
G (Green)

1
2
3

R (Red)

Thus, a text attribute of intensified red (lRGB = COH) accesses location 09H
of the 16 locations in the VLT.
On power-up or system reset, the VLT is initialized to the values in Table 7-4.
The VLT values defined in Table 7-4 support video modes OOH, 01H, 02H,
03H, 04H, 05H, 06H and DOH. When changing from any of these modes to
video mode DIH or D2H, initialize the VLT to the values defined in Table 7-5.

Video Controller - Hardware Description

7- 19

Default VLT Content.~

Table ,7-4
Gffse~

Contents'

Color

A;J, A2 Al AO
11 G B I

D3 D2 Dl DO
R G B I

Intensity

Black
Gray
Blue
Light blue
Green
Light green
Cyan

White

Red

O.
1

9
10

Light red
Magenta
Light magenta
Brown

Yellow
Light cyan
Intense white

1
1

7 - 20·'

Video Controller - Hm:dware :pescription

1
2

3
4
5
6

11
12
7

Table 7-5

VLT Contents for Video Modes D1H and D2H

Offset
A3 A2 Ai AO

Contents
D3 D2 Dl DO

Black

Green

Red

Light cyan

Not Used

Color

Intensity

Video Controller - Hardware Description

7 - 21

Video System Registers
Table 7-6 lists the video processor input/output (110) registers.
Table 7-6

Video Processor 110 Registers

Address Width R/W

Compatibility

03DOH
03DIH

4-0
7-0

W
R/W

CRTC Index Register
CRTC Data Register

DIGITAL Extended
DIGITAL Extended

03D4H
03D5H

4-0
7-0

W
R/W

CRTC Index Register
CRTC Data Register

Industry-Standard
Industry-Standard

03D8H
03D9H

7-0
7-0

W
W

Control Register A
Color Select Register

Industry-Standard
Industry-Standard

03DAH

7-0

Status Register A

Industry-Standard

03DDH

7-0

Status Register B

DIGITAL Extended

03DEH

7-0

Write Data Register

DIGITAL Extended

03DFH

7-0

Control Register B

DIGITAL Extended

OC80H

7-0

R/W

Special Purpose Register DIGITAL Extended

7- 22

Video Controller - Hardware Description

Special Purpose Register (OC80H)
7

654

WITE TRACK 0 INDEX
PROTECl'

SPEED

DISULB SPLIT
VIDEO BAUD

COMM

DISABLE SPEED
SELBCl'

Bit

R/W Description

Write protect
0= Selected diskette drive is not write protected
1 = Selected diskette drive is wri~ protected

Track 0
0= Head of selected diskette drive is not at track 0
1 = Head of selected diskette drive is at track 0

Index
0= Index hole not in position for selected diskette drive
1 = Index hole in position for selected diskette drive
Speed Indicator
0= Modem control speed select asserted
1 = Modem control speed select not asserted

RIW Disable Video
0= Video controller disabled
1 = Video controller enabled

R/W Split Baud Rates
0= (Receive = Transmit = programmed)
1 = (Receive = 1200) (Transmit = programmed)

R/W Disable Communications
0= Integral communications ports connected to I/O address
space
1 = Integral communications ports disconnected from I/O address
space

R/W Speed Select
0= Speed select asserted
1 = Speed select not asserted

Video Controller - Hardware Description

7 - 23

The special purpose register is located at I/O address OC80H. When bit 3
equals 0, the entire DIGITAL video system is disconnected from the memory
and 110 address space. This allows the installation and use of industry-standard
video adapters in the VAXmate workstation.
If the ROM BIOS finds an industry-standard video adapter during the powerup sequence, the ROM BIOS clears bit 3 of the special purpose register. This
allows the industry-standard video adapter to function without conflict.

7- 24

Video Controller - Hardware Description

CRTC Registers
The CRT controller (CRTC) has two registers, the index and data registers,
that are accessible in the CPU 1/0 space. Writing a value to the index register
selects one of the 18 internal registers RO-R17. The selected register is read or
written through the data register.

Index Register (03DOH/03D4H)
7

Bit

RIW Description

7-5

Always 0

4-0

A value between 0 and 17 written to this register selects one of
the corresponding internal registers (RO-R17).

Data Register (03D IH/03D5H)
7

Bit

R/W Description

7-0

R/W Data and width are dependent upon the register selected by the

index register. To determine if the data register can be read or
written, see the description of the register selected by the index
register.

Video Controller • Hardware Description

7 - 25

The index and data registers can be accessed through two sets of 1/0 ports.
The industry-standard set is 03D4H (index) and 03D5H (data). The DIGITAL
extended set is 03DOH (index) and 03D1H (data). Data written to the industrystandard set pass through a translation ROM and then go to the CRTC. Data
written to the DIGITAL extended set go directly to the CRTC.
The translation ROM converts CRTC parameters, for an industry-standard
color graphics adapter, to values that are correct for the extended capabilities
of the DIGITAL video system. Thus, applications that directly program the
CRTC of an industry-standard color graphics adapter function correctly.
Table 7-7 lists the CRTC internal registers and their functions. Table 7-8 lists
the corresponding parameters for the video modes defined in Table 7-1. The.
parameters listed in Table 7-8 are written to the CRTC through the DIGITAL
extended 1/0 ports 03DOH (index) and 03D1H (data).
Table 7-7

CRTC Internal Registers

Index

R/W Description

RO
R1
R2
R3
R4
R5
R6
R7

OOH
01H
02H
03H
04H
05H
06H
07H

W
W
W
W
W
W
W
W

R8
R9
RIO
R11

08H
09H
OAH
OBH

W
W
W
W

R12
R13
R14
R15
R16
R17

OCH
ODH
OEH
OFH

RlW
RlW
RlW
RlW

InterlacelSkew
Max scan line address
Cursor start
Cursor end
Start address (High byte)
Start addless (Low byte)
Cursor address (High byte)
Cursor address (Low byte)

10H
11H

R
R

Light pen (High byte) *
Light pen (Low byte) *

Horizontal total
Horizontal displayed
Horiz sync position
Sync width
Vertical total
Vertical total adjust
Vertical displayed
Vertical sync position

* The DIGITAL video system does not support light pens.

7 - 26

Video Controller - Hardware Description

Table 7-8

CRTC Register Values
320 x
200
4-color

320 x
200
l6-color

800 x
252
4-color

640 x
400
4-color

640 x
200
2-color

640 x
200
4-color

640 x
400
2-color

80 x 25

40 x 25

Graphics Graphics Graphics Graphics Text

Text

RO
RI
R2
R3

69H
50H
58H
58H

83H
64H
60H
5AH

69H
50H
58H
58H

34H
28H
2CH
54H

69H
50H
58H
58H

34H
28H
20H
54H

R4
R5
R6
R7

36H
OOH
32H
33H

60H
OIH
3FH
53H

60H
OOH
64H
66H

IAH
08H
I9H
I9H

R8
R9
RIO
Rll

40H
07H
OOH
OFH

40H
03H
OOH
OFH

42H
03H
OOH
OFH

40H
03H
OOH
OFH

40H
OFH
OOH
OFH

RI2
RI3
RI4
RI5

OOH
OOH
OOH
OOH

Video Controller - Hardware Description

7 - 27

RIW Description

7-0

~~~TM~

I : :
Bit

HORIZONTAL TOTAL

This register determines the horizontal synchronization frequency.
It is the number of displayed characters (Rl) plus the retrace (in
character times) minus one.

Bit

RIW Description

7-0

HORIZONTAL DISPLAYED

This register determines the number of displayed characters on a
line. The value in Rl must be less than the value in RO.

7- 28

Video Controller - Hardware Description

Bit

RIW Description

'-0

HORIZONTAL SYNCHRONIZATION POSITION
This register determines the position of the horizontal synchronization delay and the horizontal scan delay. When this value is increased, the display shifts left. When this value is decreased, the
display shifts right.

VERTICAL

SYNCHRONIzATION

HORIzONTAL SYNCHRONIzATION

PULSE VIDTB

VS3

VS2

VSl

PULSE VIDTB
I

VSO

HS3

HS2

HSl

aso

Bit

RIW Description

7-4

VERTICAL SYNCHRONIZATION PULSE WIDTH
A value of 1-15 produces a pulse width of the indicated number of
scan-line periods. A value of zero produces a pulse width of 16
scan-line periods.

3-0

HORIZONTAL SYNCHRONIZATION PULSE WIDTH
A value of 1-15 produces a pulse width of the indicated number of
character periods. If the value equals 0, then a horizontal synchronization pulse is not provided.

Video Controller - Hardware Description

7 - 29

Bit

RIW Description

Always 0

6-0

VERTICAL TOTAL
This value determines the vertical synchronization frequency. It is
the number of displayed character lines plus the retrace (in character line times) minus one.

Bit

RIW Description

7-5

Always 0

4-0

VERTICAL TOTAL ADJUST

This value is the number of scan-line periods required, in addition
to R4, to produce a vertical synchronization frequency of exactly
50Hz or 60Hz.

7- 30

Video Controller - Hardware Description

Bit

R/W Description

Always 0

6-0

VERTICAL DISPLAYED

This value specifies the number of displayed character lines. It
must be less than the value in R4.

:
Bit

R/W Description

Always 0

6-0

VERTICAL SYNCHRONIZATION POSITION

This value determines the position of the vertical synchronization
delay and the vertical scan delay. When this value is increased, the
display shifts up. When this value is decreased, the display shifts
down.

Video Controller - Hardware Description

7 - 31

7
I

CURSOR SKEV
CS1

DISPLAY I ENABLE
SKEV

CSO

DS1

DSO

INTERLACE MODE

Bit

RIW Description

7-6

5-4

3-2

Always 0

1-0

INTERLACE MODE
00 =
Normal mode
01 = Interlace synchronization mode
10 = Normal mode
11 = Interlace synchronization and video mode

7 - 32

CURSOR SKEW
00 == No skew
01 = One character skew
10 = Two character skew
11 = Invalid value
DISPLAY ENABLE SKEW
00 = No skew
01 = One character skew
10 = Two character skew
11 = Invalid value

Video Controller - Hardware Description

IM1

IMO

Bit

RIW Description

7-5

Always 0

4-0

MAXIMUM SCAN LINE

This value specifies one less than the number of scan lines per
character line including spacing.

: ~~~.: I
Bit

RIW Description

Always 0

6-5

CURSOR DISPLAY MODE
00 = Nonblinking cursor
01 =
Cursor not displayed
10 = Blinking cursor (3.75 Hz)
11 = Blinking cursor (1.875 Hz)

4-0

CURSOR START
This value specifies the scan line, within the character cell. on
which the cursor starts. A value of 0 starts the cursor at the top
of the character cell.

This register is meaningful only in text video modes.
Video Controller - Hardware Description

7 - 33

101 0 I 0 I

~~ :

Bit

RIW Description

7-5

Always 0

4-0

CURSOR END
This value specifies the scan line, within the character cell, on
which the cursor ends. A value of 15 ends the cursor at the
bottom of the character cell.

This register is meaningful only in text video modes.

: ~~~<

:: I

R12 and R13 are a write-only register pair that determine which part of the
video RAM is used to generate the display. The address in R12 and R13 must
be an even value. This address points to the first character position.

7- 34

Video Controller - Hardware Description

:=R :=ss:
HIGH

:=R :=ss:
LOV

R14 and R15 are a read/write register pair that determine the location of the
cursor as an offset from the beginning of video RAM. The address in R14 and
R15 must be an even value. The address points to the character byte of a character byte/attribute byte pair.

Video Controller - Hardware Description

7- 35

~GBT
~
POSITI~
I I I :
HIGH BYTE

~GBT~~B~ITI~ : : I

R16 and R17 are a read only register pair that capture the CRTC refresh address when the light pen strobe pin is pulsed.

NOTE
The VAXmate workstation does not support the use of light
pens.

7 - 36

Video Controller - Hardware Description

Status Register A (03DAH)
765

VIDEO

VSYNC

LIGHT PEN

RETRACE

Bit

RIW Description

VIDEO I - Video Intensity Signal

o = Video intensity signal inactive
1 =

2-1

Video intensity signal active

VIDEO R - Video Red Signal
Video red signal inactiv~
1 = Video red signal active

VIDEO G - Video Green Signal
Video green signal inactive
1 = Video green signa! active

VIDEO B - Video Blue Signal
Video blue signal inactive
1 = Video blue signal active

VSYNC - Vertical Synchronization
Vertical synchronization inactive
1 = Vertical synchronization active

LIGHT PEN IContents undefined)
RETRACE IHorizontal or vertical)
Display active
1 = Retrace period

Because the dual-port RAM eliminates display interference caused
by accessing video memory, checking this bit is not required. For
those programs that do check, this bit flips with each read.
Because a retrace period appears to be in effect every other time it
is checked, this has the effect of speeding up video memory
accesses.

Video Controller - Hardware Description

7 - 37

Status Register B (03DDH)

VIDEO
BLANK

CR-B3

CR-B5

CR-A4

CR-AI

CR-AO

¥RITE

PORT

CHECK

Bit

RIW Description

CR-B5
Control Register B bit 5 (Control register A bit 3 enable)

CR-A4
Control Register A bit 4 (Mode bit 2)

CR-Al
Control Register A bit 1 (Mode bit 1)

CR-AO
Control Register A bit 0 (Mode bit 0)

VIDEO BLANK
Video is in an active display state
1 = Video is in a blanking state
CR-B3
Control Register B bit 3 (Display enabled)

WRITE CHECK
Since the write data register (03DEH) was last read, an 110
write to port 03D4H or 03D5H has not occurred.
1 = Since the write data register (03DEH) was last read, an 110
write to port 03D4H or 03D5H has occurred. This bit is
cleared by reading the write data register (03DEH).

PORT CHECK
Of the pair, 03D4H and 03D5H, 03D4H was the last port
written.
1 = Of the pair, 03D4H and 03D5H, 03D5H was the last port
written.

This bit is used in conjunction with bit 1.

7 - 38

Video Controller - Hardware Description

Write Data Register (03DEH)
5

I I I I I I I I I
Bit

R/W Description

7-0

Contains the last data written into the CRTC through register
03D4H or 03D5H. Status register B bits 1-0 indicate which port
the data was written to. Reading this register clears status register
B bit 1.

Color Select Register (03D9)

CPS

SIC

Bit

R/W Description

7-6

Always 0, always ignored

CPS - Color Palette Select (See Table 7-9 and Table 7-10)

SIC - Select Intensified Colors (See Table 7-9 and Table 7-10)

I - Intensity (See Table 7-9)

R - Red (See Table 7-9)

G - Green (See Table 7-9)

B - Blue (See Table 7-9)

Video Controller - Hardware Description

7 - 39

The use of the color select register bits depends on the current video mode.
Table 7-9 d~scribes the bit meanings for the affected modes. Table 7-10
describes the color palettes selected by bits 5-4 (CPS and SIC).
Table 7-9

Color Select Register Bit Assignments
640 x 200 x 2-Color
640 x 400 x 2-Color
Graphics

Bit

Text Modes

320 x 200
4-Color
Graphics

Ignored

5
4

Ignored

CPS
SIC

Ignored
Ignored

3-0

Border color

Border and
background
color

Foreground color

Ignored

NOTE
For the VAXmate workstation, the border color is always black.
Table 7-10

Color Palettes Selected by CPS and SIC

Color Bit
cbl
cbO

CPS = 0
SIC = 0

CPS = 1
SIC = 0

CPS = 0
SIC = 1

CPS = 1
SIC = 1

Background

Green

Cyan

Light green

White

Red

Magenta

Light red

Light magenta

Brown

Light cyan

Light yellow

Intense white

The color bits (cbllcbO) in Table 7-10 are any 2 bits that describe a pixel color
in the 320 x 200 4-color video mode.

7- 40

Video Controller - Hardware Description

Control Register A (03D8H)
7

BLINK
ENABLE

HODE DISPLAY
BIT 2 ENABLE

HODE
BIT 1

HODE
BIT 0

Bit

RIW Description

7-6

Always 0

BLINK ENABLE
0= Text mode background intensity bit (II remains in effect
1 = Text mode background intensity bit (I) becomes blink bit
MODE BIT 2 (See Table 7-11)

DISPLAY ENABLE

If control register B (03DFH) bit 6 equals 0, this bit is ignored. If
control register B bit 5 equals 1, the following is true:
o = Display disabled
1 = Display enabled
Always 0 (Reserved)
MODE BIT 1 (See Table 7-11)
MODE BIT 0 (See Table 7-11)

Video Controller - Hardware Description

7 - 41

Table 7-11 lists the video modes selected by the mode bits in control registers
A and B.
Table 7-11
Control
Register A
Mode Bits
2 1 0

Selecting Video Modes
Control
Register B
Bit
7

Mode

Compatibility

0 0 0

40 x 25 Text

Industry-standard

0 0 1
0 1 0

80 x 25 Text

Industry-standard

320 x 200 x 4
color graphics

Industry-standard

0 1 1

320 x 200 x 16 DIGITAL extended
color graphics

1 0 0

640 x 400 x 2
color graphics
640 x 200 x 4
color graphics

DIGITAL extended

1 0 1

DIGITAL extended

1 1 0

640 x 200 x 2
color graphics

Industry-standard

1 1 1

640 x 400 x 4
color graphics

DIGITAL extended

1 1 1

800 x 252 x 4
color graphics

DIGITAL extended

7- 42

Video Controller - Hardware Description

Control Register B (03DFH)
7

FONT
MONITOR SCREEN CR-AS RAM
DISPLAY VLT
MODE
SAVER
ENABLE ENABLE ENABLE ENABLE

Bit

RIW Description

MONTIOR MODE
0= 400 scan lines
1 = 252 scan lines

SCREEN SAVER
Toggling this bit to 0 and then back to 1 blanks the display. The
next memory or 110 access to the video address space reenables
the display. Program to 1 for normal operation.

CR-A5 ENABLE
0= Control register A bit 5 ignored
1 = Control register A bit 5 enabled

FONT RAM ENABLE
0= Access to font RAM disabled
1 = Access to font RAM enabled

DISPLAY ENABLE
0= Display blanked
1 = Display enabled

VLT ENABLE
0= Access to video look-up table disabled
1 = Access to video look-up table enabled

1-0

Always 0

Video Controller - Hardware Description

7 - 43

Monitor Interface
Table 7-12 lists the monitor interface signals. These signals are applicable to
both a monochrome or a color monitor.
Table 7-12

Monitor Interface Signals

Pin No.

Signal Description

Horizontal synchronization (active low)

Vertical synchronization (active low)

Intensity Video (active high)

Red Video (active high)

Green Video (active high)

Blue Video (active high)

400/252 select (low for 400 scans; high for 252 scans)

(reserved)

Signal ground

+5 return

+5V dc (200 mA max.)

(spare)

Monitor Specification Summary
The following are specifications for the monochrome monitor on the VAXmate
workstation:
CRT

340 mm (14 in) diagonal, amber or green phosphor

Active Display

240 mm horizontal by 150 mm vertical (9.6 x 6 in)

Resolution

640 pixels horizontal by 400 pixels vertical
800 pixels horizontal by 262 pixels vertical

Horizontal scan rate

26.40 kHz (640 x 400)
26.49 kHz (800 x 252)

Vertical scan rate

60 Hz noninterlaced

Video Bandwidth

22.384 MHz (640 x 400)
27.984 MHz (800 x 252)

7-44

Video Controller - Hardware Description

Programming Example
The following programming example demonstrates:
•
•
•
•

Programming the video controller for a specific mode
Writing the video look-up table
Reading and writing the font RAM
Displaying characters in text and graphics modes

NOTE
Whenever possible, ROM BIOS Interrupt 10H video calls are
preferred over direct programming of the video hardware.
Do not mix ROM BIOS calls and direct programming of the
hardware.
Before directly programming the hardware, use ROM BIOS calls
to determine the state of the video system. On exit, use the
ROM BIOS to restore the previous state.
CAUTION
Improper programming or improper operation of this device can
cause the VAXmate workstation to malfunction. The scope of
the programming example is limited to the context provided in
this manual. No other use is intended.

Video Controller - Programming Example

7- 45

The example provides routines as described in the following list:
get_mode_p
get_mess_p
w vlt
r w font

Returns a pointer to a table of data about the indicated mode.
Returns a pointer to character string that describes the indicated mode.
Writes the video look-up table.

mode init

Reads or writes the font ram.
Initializes the video controller and mode registers from a table
of data.

mv cursor

Positions the cursor to the indicated row and column position.

cursor on
cursor off

Positions the cursor and makes it visible.
Makes the cursor invisible.

set mode

Sets the current mode, clears video memory and enables the
display.

Enables or disables the display.
screen on
clear vid mem Clears the screen by writing the appropriate values to video
memory.
do border

Forms a border around the screen (like a picture frame), by
displaying the letter E at the extreme positions of the screen.
It also displays a message, in the center of the screen, that
describes the current mode.
Displays, in graphics mode, the pixel representation of a
character.
Displays characters for text mode.
Sets up the conditions and executes the examples.

7- 46

Video Controller - Programming Example

This page is intentionally blank.

Video Controller· Programming Example

7- 47

The constants defined in this example are in the include file VIDEO.H.
The other include files, EXAMPLE.H and KYB.H, support the example, but
are not pertinent to the video section.
The constant values TRUE and FALSE are used as calling parameters for several routines.
The constant values CRTC INDEX through CTRL REGB define the addresses, in input/output spice, of the registers usedto control the video mode
and attributes. These registers are described in Table 7-7.
The constant value VB8 defines the industry-standard start address for color
graphics video memory. The constant value VBO defines the VAXmate extended start address for color graphics video memory. These values are far
pointers expressed as long integers.
The structure type VLT defines the organization of the video look-up table.
When access is enabled, the first byte of the video look-up table is written at
B800H:0000H (segment:offset). The next byte is written at B800H:0002H (segment:offset). Thus, the video look-up table can be defined as an array of 16
structures of type VLT. Notice that this organization should be used only for
accessing the video look-up table. It should not be used when reserving space,
because 50 percent of the space would be wasted.
The structure type FONT defines the organization of the font RAM. When
access is enabled, the first byte of the font RAM is read or written at
B800H:0000H (segment:offset). The next byte is read or written at
B800H:0002H (segment:offset). Each character font requires 16 bytes. The font
for each of the possible 256 characters can be defined. Thus, the font RAM can
be defined as a two-dimensional array of structures of type FONT, where the
first subscript is 256 and the second subscript is 16. Notice that this organization should be used only for accessing the font RAM. It should not be used
when reserving space, because half the space would be wasted.
The structure type M TABLE defines data or pointers to data that is required
to program the various video modes. Later in the example, an array of structures of type M TABLE is defined. The values used are gathered from information providedearlier in this chapter.

7- 48

Video Controller - Programming Example

#include "video.h"
#include "example.h"
#include "kyb.h"
/***********************************************************************/
/*
Declare constants and structures used in examples
*/
/***********************************************************************/
#define TRUE
Oxffff
#define FALSE
OxOOOO
#define CRTC_INDEX Ox03dO
#define CRTC_DATA
Ox03d1
Ox03d8
'define CTRL_REGA
Ox03d9
'define COLR_SELC
Ox03da
'define STAT_REGA
Ox03dd
'define STAT_REGB
Ox03df
'define CTRL_REGB
Oxb8000000L
'define VB8
OxbOOOOOOOL
'define VBO

/* True is nonzero */
/* False is zero
*/
/* crtc index register in i/o space */
/* crtc data register in i/o space */
/* control register A in i/o space */
/* color select register in i/o space*/
/* status register A in ilo space
*/
/* status register B ini/o space
*/
/* control register B in i/o space *1
/* normal base address of video memory */
/* extended base address */

typedef struct
{

unsigned char
unsigned char
} VLT;

vlt_byte;
skip_byte;

1* vlt entries at even address *1

font_byte;
skip_byt.e;

1* font entries at even address *1
1* skip byte at odd address */

/* skip byte at odd address */

typedef struct
{

unsigned char
unsigned char
} FONT;
typedef struct
{

unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
long
unsigned int
unsigned int
unsigned int
unsigned int
unsigned int
} M_TABLE;

/* pointer into crtc_table *1
*ct;
/* pointer into vlt_table *1
*vt;
cra;
/* control register A value (Table 1-11) *1
crb;
1* .control register B value */
csr; /* color select register value (Table 7-10) */
base;
/* segment:offset base address *1
nsp;
1* number of scan pages *1
/* scan page size *1
sps;
color
bits per pixel *1
cb;
/*
width;
/* bytes per character line or scan line */
length;
/* in chars or pixels depending on mo.de *1

Video Controller . Programming Example

7- 49

The array crtc defines six sets of CRT controller initialization values. The
values used are those listed in Table 7-8, which supports all of the defined
V AXmate video modes. Notice that each state supports more than one video
mode. In that case, the distinguishing factor is the contents of control register
A, control register B, the color select register and the video look-up table.
These relationships are demonstrated later in the mode_table definition.
The array vlts defines two sets of video look-up table initialization values. The
values used are those listed in Table 7-4 and Table 7-5. Notice that each state
supports more than one video mode. These relationships are demonstrated later
in the mode table definition.
The array mode list is not required to program the video modes, however, the
example uses this array to index through the various modes as it performs the
demonstration.
NOTE
The two video modes, Oxfe and Oxff, are not defined or supported by the ROM BIOS. The mode numbers, Oxfe and Oxff,
are defined only within the limits of this example.

7- 50

Video Controller - Programming Example

/***********************************************************************/
/*
Define table values and declare globals used in examples
*/
/***********************************************************************/
/* Refer to Table 1-1 t 1-S */

unsigned char crtc[6] [16]
{

{ Ox34 , Ox2S, Ox2d, Ox54 , Ox1a, OxOS, Ox19, Ox19,
Ox40, OxOf, OxOO, OxOf, OxOO, OxOO, OxOO, OxOO },

/* TEXT */
/* 40 x 25 */

{ Ox69 , Ox50, Ox5S, Ox5S, Ox1a, OxOS, Ox19, Ox19,
Ox40, OxOf, OxOO, OxOf, OxOO, OxOO, OxOO, OxOO },

/* TEXT */
/* so x 26 */

{ Ox34 , Ox2S, Ox2c, Ox54 , Ox6d, OxOO, Ox64 , Ox66 ,
Ox40, Ox03, OxOO, OxOf, OxOO, OxOO, OxOO, OxOO },

/* GRAPHICS */
/* 320 x 200 x 4 */
/* 640 x 200 x 2 */
/* 640 x 400 x 2 */

{ Ox69 , Ox50, Ox5S, Ox5S, Ox6d, OxOO, Ox64 , Ox66 ,
Ox42, Ox03, OxOO, OxOf, OxOO, OxOO, OxOO, OxOO },

/* GRAPHICS */
/* 640 x 400 x 4 */
/* 640 x 200 x 4 */

{ OxS3, Ox64 , Ox6d, Ox5a, Ox6d, Ox01, Ox3f, Ox53,
Ox40, Ox03, OxOO, OxOf, OxOO, OxOO, OxOO, OxOO },

/* GRAPHICS */
/* SOO x 250 x 4 */

{ Ox69 , Ox50, Ox5S, Ox5S, Ox36, OxOO, Ox32, Ox33 ,
Ox40, Ox01, OxOO, OxOf, OxOO, OxOO, OxOO, OxOO },

/* GRAPHICS */
/* 320 x 200 x 16 */

};

unsigned char vlts[2] [16] =
{

{ OxOO,
Ox04,
OxOS,
OxOc,

Ox01,
Ox05,
Ox09,
OxOd,

Ox02,
Ox06,
OxOa,
Ox01,

Ox03,
OxOe,
OxOb,
OxOf },

/* See Table 7-4 */

{ OxOO,
OxOO,
OxOO,
OxOO,

Ox04,
OxOO,
OxOO,
OxOO,

OxOS,
OxOO,
OxOO,
OxOO,

Ox01,
OxOO,
OxOO,
OxOO },

/S See Table 1-5 */

};

int mode_list[12]

{ OxOO, Ox01, Ox02, Ox03, Ox04, Ox05,
Ox06, OxdO, Oxd1, Oxd2, Oxfe, Oxff };

Video Controller - Programming Example

7 - 51

The array mode table is an array of structures of type M TABLE. Each structure contains data or pointers to data that are required to-program a particular
video mode. Refer back to the declaration of the structure type M TABLE to
determine the relative placement or meaning of each value. The base address,
number of scan pages, color bits per pixel, and width are determined from
Figure 7-3 through Figure 7-16.
The array message is not required to program the video modes, however, the
example program uses a string from the array message to identify and confirm
the current video mode. The appropriate string is determined by the function
get_messy.
The array rltr e defines the character font for a reverse (mirror image} letter
'E'. It is used to demonstrate writing the font RAM and the effect it has. The
character cell size is 8 x 16.
The array cJont reserves enough space to store the font for an entire character set (256 characters having a cell size of 8 x 16). The example program
copies the current contents of the font RAM to this space.
The variable font h allows the program to dynamically change, between
demonstrations, the height of the character font. The variable font w is provided for consistency.
The variable vid_mode allows the currently selected mode to be known globally.

7- 52

Video Controller - Programming Example

M_TABLE mode_table[13] =
{

{ .t;crtc[O][O], .t;vlts[O] , Ox08, Ox68 , OxOO, VB8, 8, Ox0400, Ox04, 40, 26 },
{ .t;crtc[O] [0] , blts[O] , Ox08, Ox68 , OxOO, VB8, 8, Ox0400, Ox04, 40, 2.6 },
{ .t;crtc [1] [0] , blts[O] , OxOQ, Ox68 , OxOO, VB8, 4, Ox0800, Ox04, 80, 26 },
{ .t;crtc [1] [0] , blts[O] , Ox09, Ox68 , OxOO, VB8, 4, Ox0800, Ox04, 80, 26 },
{ .t;crtc[2] [0] , blts[O] , OxOa, Ox68, OxOO, VB8, 2, Ox2000, Ox02, 80, 200 },
{ .t;crtc[2] [0] , blts[O] , OxOa, Ox68, OxOO, VB8, 2, Ox2000, Ox02, 80, 200 },
{ .t;crtc[2] [0] , blts[O] , Oxla, Ox68, Ox07, VB8, 2, Ox2000, OxOl, 80, 200 },
{ .t;crtc[2] [0] , .t;vlts[O] , Ox18, Ox68 , Ox07, VB8, 4, Ox2000, OxOl, 80, 400 },
{ .t;crtc [3] [0] , blts[l] , Oxlb, Ox68 , OxOO, VBO, 4, Ox4000, Ox02, 160, 400 },
{ .t;crtc[4] [0] , blts[1] , Oxlb, Oxe8, OxOO, VBO, 4, Ox4000, Ox02, 200, 260 },
{ .t;crtc[6] [0] , .t;vlts[O] , OxOb, Ox68 , OxOO, VB8, 4, Ox2000, Ox04, 160, 200 },
{ .t;crtc[3] [0] , blts[l] , Ox19, Ox68 , OxOO, VB8, 2, Ox4000, Ox02, 160, 200 },
};

char message [12] [24]
{

40 x 25 monochrome",
40 x 26 color",
80 x 26 monochrome",
80 x 26 color",
320 x 200 x 4-color",
320 x 200 monochrome",
640 x 200 x 2-color" ,
640 x 400 x 2-color",
640 x 400 x 4-color",
800 x 260 x 4-color",
320 x 200 x 16-color",
640 x 200 x 4-color",
};

char press [32]

"Press any function key to exit";

char rltr_e[16] = { OxOO, OxOO, Oxfe, Ox02, Ox02, Ox02, Ox7e, Ox02,
Ox02, Ox02, Ox02, Oxfe, OxOO, OxOO, OxOO, OxOO };
char c_font[266][16];

/* space to store current character set */

char c_cursor[8] = { Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff } ;
int font_w = 8;
int font_h = 16;
int vid_mode = 2;

/* font width in pixels */
/* font height in pixels */
/* current video mode */

Video Controller - Programming Example

7- 53

The function get_mode""p provides a single source for a pointer to video mode
data.

NOTE
The two video modes. Oxfe and Oxff. are not defined or supported by the ROM BIOS. The mode numbers, Oxfe and Oxff,
are defined only within the limits of this example.
The function get_mess""p provides a single source for a pointer to a string that
describes the currently selected video mode. This function is not required to
program the video modes, however, it is used to support the example program.

7- 54

Video Controller - Programming Example

/***********************************************************************/
/*
get_Mode_pC) - returns a pointer to a mode table
*/
/***********************************************************************/
M_TABLE *get_mode_p(d_mode)
/* get mode table pointer */
int d_mode;

/* desired mode */

{

switch (d_mode)

/* discover desired mode */

{

case
0: return(lmode_table[O]);
case
1 : return(lmode_table[l]);
case
2: return(lmode_table[2]);
case
3: return(lmode_table[3]);
case
4: return(lmode_table[4]);
case
5: return(lmode_table[S]);
case
6: return(lmode_table[6]);
case OxdO: return(lmode_table[7]);
case Oxdl: return(lmode_table[8]);
case Oxd2:·return(lmode_table[9]);
case Oxfe: return(lmode_table[10]);
case Oxff: return(lmode_table[ll]);

40 x 26 monochrome */
/* 40 x 26 color */
/* 80 x 26 monochrome */
/* 80 x 26 color */
/* 320 x 200 x 4 color */
/* 320 x 200 monochrome */
/* 640 x 200 x 2 color */
/* 640 x 400 x 2-color */
/* 640 x 400 x 4-color */
/* 800 x 260 x 4-color */
/* 320 x 200 x 16-color */
/* 640 x 200 x 4-color */
/*

}
}

/***********************************************************************/
/* get_mess_pC) returns a pointer to a string that describes the mode */
/***********************************************************************/
char *get_mess_p()
/* get message pointer */
{

switch(vid_mode)

/* discover current mode */

{

case
0: return (lmessage [0] [0]);
case
1 : return (lmessage [1] [0]);
case
2: return(lmessage[2][0]);
case
3: return (lmessage [3] [0]);
case
4: return (lmessage [4] [0]);
case
5: return(lmessage[5] [0]);
case
6: return (lmessage [6] [0]);
case OxdO: return (lmessage [7] [0]);
case Oxdl: return(lmessage[8] [0]);
case Oxd2: return(lmessage[9][0]);
case Oxfe: return(lmessage[10] [0]);
case Oxff: return (lmessage [11] [0]);

40 x 25 monochrome */
/* 40 x 26 color */
/* 80 x 25 monochrome */
/* 80 x 26 color */
/* 320 x 200 x 4 color */
/* 320 x 200 monochrome */
/* 640 x 200 x 2 color */
/* 640 x 400 x 2-color */
/* 640 x 400 x 4-color */
/* 800 x 250 x 4-color */
/* 320 x 200 x 16-color */
/* 640 x 200 x 4-color */
/*

}
}

Video Controller - Programming Example

7- 55

The function w_ vlt writes the video look-up table.
The parameter pva is a pointer to a packed array of byte values.
Notice-that the routine waits until the start of video blanking time to perform:
the operation and that video output is disabled on return.
/***********************************************************************/
/* w_vltO - cophs a set of vlt-values to the video look-up table
*/
/***********************************************************************/
/* write vlt */
register char

/* ptr to array of characters */

*pva:

{

/* loop counter */

/* pointer to access vlt */

pvlt ... (VLT far *)VB8;
while(inp(STAT_REQB) & Ox80)
while(inp(STAT_UOS) & Ox80

/* initialize pointer to vlt */
/* wait until display is active */
0)

/* wait until beginning of */

/* display bla~ked */
/* enable vlt access */
/* do all 16 vlt values */

outp(CTRL_REGB, OJt04);
for(i - 0; i < 16: i++)
vlt_bxte - *pva++;
outp(CTRL_REGB. 0);

(pvlt++)->
/* write to vlt */
/* return to normal */

}

7- 56

Video Controller . Programming Example

The function r_wJont reads or writes the font RAM. If the parameter dir is
false, it reads from the font RAM. Otherwise, it writes to the font RAM.
The parameter pfa is a pointer to a packed array of byte values.
Notice that to access the font RAM. the current mode must be one of the text
modes. The mode is changed temporarily and then restored to the mode indicated by vid_ mode.
Also notice that the routine waits until video blanking time to perform the operation and that video output is disabled on return.
/***********************************************************************/
/* r_w_font() copies the indicated number of character fonts to or
*/
/*
from the font ram starting at the indicated character
*/
/***********************************************************************/
/* read or write font ram */
register char
*pfa;
int
dir;
unsigned char c_value;
register int count;

/* pointer to font array */
direction
to move font data */
/*
/* start at this char value */
/* number of character fonts */

{

int
i'
FONT far *pfnt;

/* loop counter */
/* pointer to access font ram */

mode_init(2);
/* text mode required */
outp(CTRL_REGB. OxlO);
/* enable font ram access */
count «= 4;
/* 16 bytes of data per char pattern */
pfnt = (FONT far *)VB8;
/* initialize pointer to font ram */
pfnt += (unsigned int)c_value « 4;
/* offset to start of pattern */
if(dir)
/* nonzero means write font ram */
while (count--)
/* do requested count */
(pfnt++)->font_byte
*pfa++;
/* write to font ram */
else
/* zero means read font ram */
while (count--)
/* do requested count */
*pfa++ = (pfnt++)->font_byte;
/* read font ram */
outp{CTRL_REGB. OxOO);
/* disable font ram access */
mode_init(vid_mode);
/* restore current video mode */
}

Video Controller - Programming Example

7- 57

The function mode in it places the video processor in a predefined mode state
as indicated by the-parameter d mode. The video look-up table is initialized
first because w vItO waits for blanking time to start its operation and the
display is disabled when it returns.
Because the CRT controller is in an unstable state during initialization, the
video output must be disabled.
The CRT controller has 18 internal registers, RO through R17. The last two,
R16 and R17, are read only. Thus, they are ignored during initialization. The
crt controller has two external registers, the index register and the data register. To access one of the 18 internal registers, write the desired register
number to the index register and read or write the data register.
The control register A and color select register are initialized to ensure that the
contents are appropriate for the mode.
Initializing control register B would enable the display. It was not done at this
time to prevent flashing the display if other operations have to be performed.
Other operations might include changing the font RAM, changing the video
look-up table from the default or preparing the video memory.
The function mv cursor positions the cursor at the desired row and column
location.
-

7- 58

Video Controller - Programming Example

/***********************************************************************/
/* mode_initC) initializes the crtc and mode registers by moving a
*/
/*
table of values to the appropriate registers
*/
/***********************************************************************/
mode_initCd_mode)
/* initialize to desired mode */
d_mode;

int

/* desired video mode */

{

/* loop control */
/* pointer to crtc_table */
/* pointer to mode_table */
/* CPU IF state */

pmt = get_mode_pCd_mode);
intr_flag = int_off();
w_vlt(pmt->vt. TRUE);
pc = pmt->ct;
for(i = 0; i < 16; i++)

/* get pointer to video mode table */
/* no interrupts please */
/* write vlt data */
/* assign pointer to crtc_table */
/* do registers RO through R15 */

{

outp(CRTC_INDEX. i);
outp(CRTC_DATA. *pc++);

/* indicate desired register */
/* write appropriate value */

outp(CTRL_REGA. pmt->cra);
outp(COLR_SELC. pmt->csr);
int_on(intr_flag);

/* set control register A */
/* set color select register */
/* allow interrupts */

}

/***********************************************************************/
/* mv_cursor() moves the cursor to the desired location
*/
/***********************************************************************/
mv_cursor(row. col)
int row;
int col;

/* desired row */
/* desired column */

{

int i;
register M_TABLE *pmt;
unsigned int intr_flag;

/* pointer to video mode table */
/* CPU IF state */

intr_flag = int_off();
pmt = get_mode_p(vid_mode);
i = (pmt->width * row) + col;
if(vid_mode == 0 II vid_mode

/* no interrupts please */
/* get pointer to video mode table */
1 I I vid_mode == 2 I I vid_mode == 3)

{

outp(CRTC_INDEX. 14);
outp(CRTC_DATA. i » 8);
outp(CRTC_INDEX. 15);

/* indicate desired register */
/* write appropriate value */
/* indicate desired register */

Video Controller - Programming Example

7- 59

outp(CRTC_DATA. i ~ Oxff);

/* write appropriate value */

}

int_on(intr_fla,);
}

7- 60

Video Controller - Programming Example

/* allow interrupts */

The function cursor on positions the cursor and turns the cursor on, so that it
is visible.
The function cursor_off turns the cursor off, so that it is invisible.

/***********************************************************************/
/*

cursor_on() turns the cursor on

/***********************************************************************/
cursor_on(row. col)
int row;
int col;

/* desired row position */
/* desired column position */

{

unsigned int intr_flag;

/* CPU IF state */

if(vid_mode == 0 I I vid_mode == 1 II vid_mode == 2 I I vid_mode -- 3)
{

intr_flag = int_off();
mv_cursor(row. col);
outp(CRTC_INDEX. 10);
outp(CRTC_DATA, 0);
outp(CRTC_INDEX, 11);
Qutp(CRTC_DATA. font_h - 1);
int_on(intr_flag);

/* no interrupts please */

/* indicate desired register */
/* write appropriate value */
/* indicate desired register */
/* write appropriate value */
!* allow interrupts */

}
}

/***********************************************************************/
/*

cursor_off() turns the cursor off

/***********************************************************************/
cursor_off 0
{

unsigned int intr_flag;

/* CPU IF state */

if(vid_mode == 0 I I vid_mode

1 livid_mode == 2 II vid_mode -- 3)

{

intr _flag = int_off 0 ;
outp(CRTC_INDEX, 10);
outp(CRTC_DATA, 17);
int_on(intr_flag);

/* no interrupts please */
/* indicate desired register */
/* write appropriate value */
/* allow interrupts */

}
}

Video Controller . Programming Example

7- 61

The function set mode establishes a new video mode. It does this by initializing
the mode, clearing the screen (video memory) to an empty (blank) state, enabling the display and advertising the new mode in vid_mode.
Notice that the video memory is cleared after the mode is initialized. This is
because each mode enables only certain sections of video memory.
The function screen on enables or disables the video output as indicated by the
parameter flag. This-is done through control register B.
/***********************************************************************/
/* set_mode() sets the mode as indicated, clears the screen and
*/
/*
sets the current video mode flag
*/
/***********************************************************************/
set_mode (d_mode)
/* set desired video mode */
int

d_mode;

/* desired mode */

*pmt;

/* pointer to mode_table */

{

M_TABLE

vid_mode = d_mode;
pmt = get_mode_p(d_mode);
mode_init(d_mode);
clear_vid_memO;
screen_on(TRUE);

/* tell world what new mode is */
/* get pointer to video mode table */
/* disable display & initialize mode */
/* clear screen */
/* enable the display */

}

/***********************************************************************/
/* screen_one) enables or disables the display (blanking / unblanking) */
/***********************************************************************/
screen_on(flag)
/* disable or enable display */
int

flag;

/* what to do */

{

*pmt;

if (flag)

/* pointer to video mode table */
/* nonzero means enable display */

{

pmt = get_mode_p(vid_mode);
outp(CTRL_REGB, pmt->crb);

/* get pointer to video mode table */
/* control reg B enables display */

}

else outp(CTRL_REGB, 0);

/* all bits off will disable */

}

7- 62

Video Controller - Programming Example

The function clear vid mem initializes video memory to a value appropriate for
the current mode. That is, in text modes the character byte is set to a space
character and the attribute byte is set to medium intensity white foreground
and a black background. For graphics modes, the color bits are set to zero
Iblackl. Only the addressable video memory is initialized.
Notice that the pointer to video memory is declared as a pointer to an integer.
The video memory data bus is a full 16-bit bus. Because text mode utilizes a
character and attribute byte pair and graphics mode values are all zero, it is
appropriate to take advantage of the 16-bit data bus. Also, the normal storage
for an integer is low byte first and high byte second.
The scan page size is specified in bytes. To calculate the correct memory size,
the number of scan pages is multiplied by half of the scan page size.
/***********************************************************************/
/* clear_vid_mem() based on the current mode, video memory is cleared */
/*
to spaces or NULLs. The size of memory to clear
*/
/*
is calculated from the mode table.
*/
/***********************************************************************/
clear_vid_memO
{

/* loop control */
/* pointer to video memory */
/* pointer to video mode table */

pmt = get_mode_p(vid_mode);
pvm = (int far *)pmt->base;
size = pmt->nsp * (pmt->sps »
switch(vid_mode)

1);

/* ptr to current mode data */
/* ptr to start of video mem */
/* number of integers to init */
/* text or graphics mode 1 */

{

case 0:
case 1:
case 2:
case 3:
while(size--) *pvm++
break;
default:
while(size--) *pvm++
break;

/* text modes initialized to */
/* a space character with */
/* medium intensity */
Ox0720;

/* write char t attribute */

OxOOOO;

/* for graphics modes, just */
/* set all bits off */

}
}

Video Controller - Programming Example

7- 63

The function do border displays the indicated character in a pattern or border
(like a picture frame) at the extremes of the screen. It first decides whether the
mode is a text mode or a graphics mode. For text mode, it retrieves the row
and column counts from the mode table. Graphics mode programming is
slightly more difficult. The row count is calculated by dividing the total scan
lines by the fonts scan line height. The column count is calculated by dividing
scan line width (measured in bytes) by the the number of color bits per pixel
(only character fonts 8 pixels wide are supported in the example).
It then executes a for loop to generate the pattern. After the pattern is
displayed, a message is displayed describing the current video mode. Notice
that in graphics mode, the font height is temporarily changed to display the
message. This is because the message is displayed using an 8 x 16 character
font and it must be accommodated when displaying the border in an 8 x 8
character font.
/***********************************************************************/
/* do_border()
From the mode table, the maximum number of
*/
/*
displayable lines is calculated and a border
*/
/*
is drawn using the indicated character.
*/
/***********************************************************************/

char

*pc;

{

unsigned char attr;
char
*pm;
int
row, rows;
int
col, cols;
int
t_font_h;
M_TABLE *pmt;
pmt = get_mode_p(vid_mode);
pm = get_mess_p(vid_mode);
switch(vid_mode)

/* get pointer to mode table */
/* get pointer to message */
/* discover the current mode */

{

case 0:
/* text mode 0 or */
case 1 :
/* text mode 1 or */
case 2:
/* text mode 2 or */
case 3:
/* text mode 3? */
attr
Ox07;
/* black background t medium intensity foregrnd */
rows = pmt->length;
/* length specified in table */
cols = pmt->width;
/* width specified in table */

7- 64

Video Controller· Programming Example

for(row = 0; row < rows; row++)
{

disp_t(row, 0, *pc, attr);
if(row == 0 I I row == rows - 1)
for (col = 1; col < cols - 1; col++)
disp_t(row, col, *pc, attr);
disp_t(row, cols - 1, *pc, attr);

/* write left side */
/* first or last row */

/* write right side */

};

col = (cols - strlen(pm» » 1;
/* center message */
while (*pm)
disp_t(rows » 1, col++, *pm++, attr);
/* do message */
pm = press;
col = (cols - strlen(pm» » 1;
/* center message */
while (*pm)
disp_t«rows » 1) + 1, col++, *pm++, attr); /* do message */
break;
default:
attr = Oxff » (8 - pmt->cb);
rows = pmt->length / font_h;
cols = pmt->width / pmt->cb;
for (row = 0; row < rows; row++)

/* medium intensity */
/* rows for this font */
/* columns this mode */
/* do all rows */

{

disp_t(row, 0, *pc, attr);
/* write left side */
if(row == 0 II row == rows - 1)
for (col = 1 ; col < cols - 1 ; col++)
disp_t(row, col, *pc, attr);
disp_t(row, cols - 1, *pc, attr);
/* write right side */
};

t_font_h = font_h;
/* save current font */
font_h = 16;
message
font is 8 x 16 */
/*
col = (cols - strlen(pm» » 1;
/* center message */
while (*pm)
disp_t(pmt->length » 5, col++, *pm++, attr); /* do message */
pm = press;
col = (cols - strlen(pm» » 1;
/* center message */
while (*pm)
disp_t«rows » 1) + 1, col++, *pm++, attr) ; /* do message */
font_h = t_font_h;
/* restore current font */
break;
}
}

Video Controller - Programming Example

7- 65

The function disp g displays a character at the desired row and column location. The color bit-pixels that form the character are set to value in attr. The
routine assumes that it is provided an attribute that is consistent with the
number of color bits per pixel.
The routine calculates the position as a constant offset to the first byte of the
first scan line. After the scan line has been displayed, the scan line offset is
incremented to the next scan page. After writing a scan line to each scan page,
the scan line offset is zeroed and the constant offset is incremented by the
length of one scan line. The actual position is the constant offset plus the scan
line offset.
The middle for loop ensures that all eight pixels of the scan line are displayed.
For example, a I6-color display requires four color bits per pixel or four bytes
per character scan line.
For each pixel, the interior for loop shifts the color bit image and if the pixel
bit is set, the color bit attribute is ORed into the color bit image. The number
of pixel representations per byte is determined by dividing the font width by
the number of color bits per pixel. Only eight pixel wide fonts are supported by
the example.

7- 66

Video Controller - Programming Example

/***********************************************************************/
/* disp_g()
Draws a character in graphics mode at the calculated
*/
/*
row and column position.
*/
/******************************************~****************************/

disp_g(row, col, pc, attr)
int row, col;
register unsigned char *pc;
unsigned char attr;
{

unsigned char far *pvm;
unsigned char bi;
unsigned char bd;
int bc;
int tbc;
int scan;
long coff;
unsigned int s_off;
register M_TABLE *pmt;

/* pointer to video memory */
/* bit image */
/* for bit testing */
/* bit count (current) */
/* terminating bit count */
/* current scan line */
/* character offset */
/* scan line offset */
/* mode data */

pmt = get_mode_p(vid_mode);
/* get pointer to mode table */
c_off = pmt->base + (col * pmt->cb) +
/* address of first byte */
(row * pmt->width * (font_h / pmt->nsp»;
tbc = font_w / pmt->cb;
/* bit image bit count per byte */
/* scan line offset */
for(scan = 0; scan < font_h; scan++, pc++)
/* do all scan lines */
{
i f (scan U
{

scan %pmt->nsp == 0)

/* done all scan pages '7 */

c_off += pmt->width;
s_off = 0;

/* offset by one scan line */
/* reset to first scan page */

}

pvm = (char far *)(c_off + s_off);
/* ptr to first byte of scan */
s_off += pmt->sps;
/* offset to next scan page, for next pass */
for(bd = Ox80; bd;)
/* start at left most bit/pixel */
{

bi = OxOO;
for(bc = 0; bc < tbc; bc++, bd »= 1)

/* null bit image */
/* do a byte of scan */

{

bi «= pmt->cb;
/* shift bit image by # of color bits */
if(*pc k bd) bi 1= attr;
/* or in next bit image */
}

*pvm++ = bi;

/* write a byte of scan line */

}

}
}

Video Controller - Programming Example

7- 67

The function disp t displays a character and attribute at the desired row and
column location. The example uses zero-based row and column values. When calculating the p0sition, this saves subtracting one from the row and column values.
Notice that the pointer to video memory is declared as a pointer to an integer.
The video memory data bus is a full16·bit bus. Because text mode utilizes a"
character and attribute byte pair. it is appropriate to take advantage of the
16·bit data bus. Also, the normal storage for an integer is low byte first and
high byte second.
/***********************************************************************/
/* disp_t{)
writes a character and its attribute to the indicated */
/*
row and column position
*/
/***********************************************************************/
disp_t{row, col, c, attr)
int
rOWj
int
colj
unsigned char Cj
unsigned char attrj
{

int far *pvmj
register M_TABLE *pmtj
if{vid_mode == 0 I vid_mode

/* pointer to video memory */
1 I vid_mode == 2 I vid_mode == 3)

{

pmt = get_mode_p{vid_mode)j

/* get pointer to mode table */
/* get address of character */

pvm = {int far *){pmt->base +
{row * (pmt->width « 1) + {col « 1»)j
*pvm = ({int)attr « 8) I {int)cj
/* character t attribute */
}

else disp_g{row, col, tc_font[c] [0] , attr)j
}

7- 68

Video Controller . Programming Example

The function video sets up various conditions and executes the example program. The major points are:
1.
2.
3.
4.
5.
6.

Read the current font and save it.
Select a video mode.
Change the pattern of the letter 'E' to a mirror image of the letter 'E.'
Restore the pattern of the letter 'E' from the saved font.
Display the letter 'E' border pattern in the selected video mode.
Restore the video mode to mode 3 and exit.

/***********************************************************************/
/* video() - execute video examples

/***********************************************************************/
videoO
{

static MESSAGE mvid[]

/* video menu */

{

{
{
{
{
{
{

{

3,
5,
6,
7,
8,
9,
0,

33,
24,
24,
24,
24,
24,
0,

"Video Example" },
"Fl. Select video mode" },
"F2. Invert letter E" },
"F3. Restore letter E" },
"F4. Display selected video mode" },
"FlO. Return to Main menu" },

o },

};

static MESSAGE mvmp []

/* video menu */

{
{

3,
5,
{ 6,
{ 7,
{ 8,
{ 9,
{ 10,
{ 11,
{ 12,
{ 13,
{ 14,
{ 0,
{

31,
24,
24,
24,
24,
24,
24,
24,
24,
24,
24,
0,

"Select Video Mode" },
"Fl. 40 x 25 Text" },
"F2. 80 x 25 Text" },
"F3. 320 x 200 x 4-color" },
"F4. 320 x 200 x 16-color" },
"FS. 640 x 200 x 2-color" },
"F6. 640 x 200 x 4-color" },
"F7. 640 x 400 x 2-color" },
"F8. 640 x 400 x 4-color" },
"F9. 800 x 2S2 x 4-color" },
"FlO. Return to video example" },

o },

};

char line[S12];

/* to hold input line */

Video Controller - Programming Example

7- 69

/* to hold menu selection */
/* temp value for mode */

int i;
int mode;
unsigned char c;
r_w_font(~c_font[O][O],

FALSE, OxOO, 256);

set_mode(3);
disp_menu(mvid);
line[O] = 0;
while (1)

/* read all font ram */
/* reset video mode */
/* display the video menu */
/* null terminated */
/* forever (see FlO) */

{

switch(line[O])

/* determine menu selection */

{

/* select video mode */
/* display the mode menu */
/* get a function key selection */

case Fl:
disp_menu(mvmd);
line [0] = get_fkeyO;
switch (line [0])
{

case Fl : mode
1;
case F2: mode
3;
case F3: mode
4;
case F4: mode
Oxfe;
6·,
case F5: mode
case F6: mode
Oxff;
case F7: mode
OxdO;
case F8: mode
Oxdl;
case F9: mode
Oxd2;
case FlO: break;

break;
break;
break;
break;
break;
break;
break;
break;
break;

}

break;

/* reverse 'E' to font ram */

case F2:
r_w_font(~rltr_e[O],

TRUE, 'E', 1);

set_mode(3);
break;

/* reset video mode */

case F3:
/* restore 'E' to font ram */
r_w_font (lI:c_font ['E'] [0], TRUE, 'E', 1);
set_mode(3);
/* reset video mode */
break;
case F4:
/* display selected mode */
set_mode(mode);
/* set the desired mode */
do_border("E");
/* write letter 'E' at screen extremes */
while(l) if(get_key(lI:c) >= 0 11:11: c == 0) break;
while(l) if(get_key(lI:c) >= 0) break;
set_mode(3);
/* set the desired mode */
break;

7- 70

Video Controller - Programming Example

case FlO:
return;

/* return to caller (main menu) */

}

disp_menu(mvid);
line[O] : get_fkey();

/* display the rtc menu */
/* get a function key for menu selection */

}

Video Controller . Programming Example

7- 71

Chapter 8
Keyboard-Interface Controller
and Keyboard
Introduction
The keyboard-interface controller is an Intel 8042 microcomputer with internal
firmware developed by DIGITAL. The keyboard-interface controller provides a
physical and logical interface between the LK250 keyboard and the VAXmate
CPU. Also, it provides several hardware control functions that are unrelated to
the LK250 keyboard.
The LK250 keyboard is an intelligent keyboard with 105 keys. The keys are
divided into functional groups as follows:
•
•
•
•

57 key main section
20 key function-key section
18 key keypad section
10 key auxiliary and direction key section

Keyboard-Interface Controller
Physical Interface to the CPU
The VAXmate CPU communicates with the keyboard-interface controller
through two 8-bit parallel ports in input/output (110) address space 0060H and
0064H. The registers accessed through these ports are:
•
•
•
•

Reading port 0064H accesses the status register.
Writing port 0064H accesses the command register.
Reading port 0060H accesses the output data register.
Writing port 0060H accesses the input data register.

The contents and usage of these registers are described later in this chapter.
Keyboard-Interface Controller - Hardware Description

8- 1

Physical Interface to the Keyboard
The keyboard-interface controller communicates with the LK250 keyboard over
a bi-directional serial data line. A second line provides serial clock rate. A combination of signals and timing on the serial clock line provides the communications protocol. These lines are in the coiled cable that connects the LK250
keyboard and the V AXmate workstation.

Logical Interface
The keyboard-interface controller has two modes of operation, pass-through or
translate. In pass-through mode, all data received from the LK250 keyboard
are stored in the output buffer without modification. In translate mode, all data
in the range OOH-99H and FOH are translated to an industry-standard or a
DIGITAL extended scan code and stored in the output buffer. Bit 6 of the
command byte controls this mode of operation. The keyboard-interface controllers default mode is pass through.
NOTE
During the system powerup initialization, the ROM BIOS sets
the keyboard-interface controller to translate mode. Therefore,
the operating system sees the keyboard-interface controller in
translate mode.

8- 2

Keyboard-Interface Controller - Hardware Description

Control Functions
The keyboard-interface controller performs some control and status functions
that are unrelated to LK250 keyboard operation. Therefore, the keyboardinterface controller has two 8-bit ports, port 1 and port 2, that are in the
keyboard-interface controller 110 address space. Commands are available that
instruct the keyboard-interface controller to read port 1 and read or write port
2. Those commands are discussed in the command register section. Table 8-1
defines the port 1 bits and Table 8-2 defines the port 2 bits.
Table 8-1

Port 1 Bit Definitions

Bit

Description

Undefined

Always 0

5-3

Undefined

EXPANSION BOX INSTALLED
Expansion box installed
Expansion box not installed

o=
1 =

RAM OPTION INSTALLED
RAM option installed
RAM option not installed

o=
1 =

RAM OPTION ERROR

o = RAM option parity error
1 =

No error

Keyboard-Interface Controller - Hardware Description

8- 3

Table 8-2

Port 2 Bit Definitions

Bit

Description

Keyboard data (output)

6
5

Keyboard clock inverted (output)
Undefined

2
I

CPU IRQI
Keyboard-interface controller not interrupting
I = Keyboard-interface controller interrupt to CPU
Undefined

Undefined
Gate system address line 20
o = System address line 20 enabled. Use this state for 80286 virtual protected mode.
I = System address line 20 disabled. Use this state for 80286 real
mode.
Reset 80286 CPU (affects only the CPU)
o = 80286 CPU in reset state
I = 80286 CPU not in reset state

Keyboard-Interface Controller Diagnostics
On powerup, the keyboard-interface controller executes a diagnostic test. The
test verifies the keyboard-interface controllers ROM and RAM. The keyboardinterface controller completes the test within 200 ms after powerup. During the
powerup test, the LK250 keyboard is ignored.
Failing this test is considered a fatal system error. If an error occurs during
powerup testing, the keyboard-interface controller will not respond to any input,
and must be reset. To reset the keyboard-interface controller, turn the
VAXmate workstation off and then on.

8- 4

Keyboard-Interface Controller - Hardware Description

Keyboard-Interface Controller Registers
Data Register (0060H)
7

Bit

R/W Description

7-0

R/W The CPU reads or writes this port to exchange data with the

keyboard-interface controller

Command Register (0064H)
5

I : : STATU~ co~ ~ISTBR:
OR

Bit

RIW Description

7-0

The CPU reads the keyboard-interface controller status register

The CPU writes the keyboard-interface controller command
register

Keyboard-Interface Controller - Hardware Description

8 - I)

Status Register (0064H)
7

PARITY RECEIVE XMIT
ERROR TIME- TIMEOtIT
OtIT
Bit

R/W Description

KEYBRD COMMAND SYSTEM INPtIT OtITPtIT
BUFFER BUFFER
INHIBIT IDATA FLAG
FULL
SVITCH
FULL

PARITY ERROR

o = No parity error
1 = Parity error
The keyboard to keyboard-interface controller serial communications use odd parity checking. When data from the keyboard contains a parity error, this bit is set to 1. Reading the status register
clears this bit.

RECEIVE TIMEOUT

o = No receive timeout error
1 =

An in-progress transmission from the keyboard was not completed within 2 ms.

Reading the status register clears this bit.
5

XMIT TIMEOUT - Transmit Timeout

o = No transmit timeout error

1 = An in-progress transmission from the keyboard-interface controller to the keyboard was not completed within 2 ms.
Reading the status register clears this bit.
This bit is also used in combination with the parity error bit or the
receive timeout bit to establish additional error conditions as
follows:
•

If the transmission to the keyboard completes within 2 ms, but

the response from the keyboard is not received within 20 ms,
then the transmit and receive timeout bits are set to 1.
•

8- 6

If the transmission to the keyboard and the response from the
keyboard complete within the designated time frame, but the
response contains a parity error, then the transmit timeout
and parity error bits are set to 1.

Keyboard-Interface Controller - Hardware Description

Bit

RIW Description (Status Register - cont.)

KEYBRD INHIBIT SWITCH - Keyboard Inhibit Switch
Keyboard is inhibited (locked)
1 = Keyboard is active (unlocked)

The VAXmate workstation does not have a keyboard lock, so this
bit is always set to 1.
3

COMMANDIDATA
Of the pair (0060H/0064H), the last 1/0 write was to the
data register, at 1/0 address 0060H.
1 = Of the pair (0060H/0064H), the last 1/0 write was to the
command register, at 1/0 address 0064H.

This bit is used internally by the keyboard-interface controller. It
determines whether the byte in the keyboard-interface controllers
input buffer is a command or data.
SYSTEM FLAG
o = ROM BIOS should execute a normal powerup initialization
process
1 = A virtual protected mode task request to reset the CPU to
real mode
The ROM BIOS interprets the state of the system flag to determine the reason the VAXmate CPU reset pin was toggled. If the
system flag is set, the VAXmate CPU is returning to real mode
from virtual protected mode. Otherwise, the ROM BIOS executes
a normal powerup initialization process.
During the keyboard-interface controllers powerup initialization sequence, the keyboard-interface controller clears the system flag to

O.
Setting or clearing the system flag is a two step process: Issue a
write-command-byte instruction by writing the value 0060H to the
command register at 1/0 address 0064H. The write-command-byte
instruction is discussed in detail later in this chapter.
Write the command byte to the input data register at 1/0 address
0060H. The system flag reflects the value of bit 2 of the command
byte. If bit 2 of the command byte is set to 1, so is the system
flag. When bit 2 is 0, the system flag is cleared to O.

Keyboard-Interface Controller - Hardware Description

8- 7

Bit

RIW Description ~Status Register - cont.)

INPUT BUFFER FULL
Keyboard-interface controller input data buffer is empty
1 = Keyboard-interface controller input data buffer contains data
that has not been processed by the keyboard-interface
controller.

Data written to the input data register is transferred to the
keyboard-interface controllers input data buffer. This bit reflects
the status of the input data buffer.
OUTPUT BUFFER FULL
o = Keyboard-interface controller output data buffer is empty
1 = Keyboard-interface controller output data buffer contains
data that the CPU has not read

The status register is an 8-bit read-only register at 110 address 0064H.
It contains information about the keyboard-interface controller and keyboard.
Status changes do not cause an interrupt. The status register can be read at

any time.
The keyboard-interface controller command EIH allows the CPU to initialize
bits 7-4 of the status register. See the keyboard-interface controller command
register description.

8- 8

Keyboard-Interface Controller - Hardware Description

Command Register (OO64H)
7

Bit

Description

7-0

Keyboard-interface controller commands from the CPU

The data written to this register are instructions to the keyboard-interface controller. Table 8-3 lists the keyboard-interface controller commands.
Table 8-3

Keyboard-Interface Controller Commands

Command
Value

Description

Command
Value

Description

00H-1FH

Reserved

COH

Read Port 1

20H

Read command byte

C1H

Read Port 1

21H-5FH
60H
61H-A9H

Reserved
Write command byte

C2H·CFH

Reserved
Read Port 2
Write Port 2

Reserved
Self-test

DOH
D1H
D2H-DFH

ACH

Interface test
Reserved for expansion

EOH
E1H

ADH

Disable keyboard

E2H-EFH

Reserved

AEH
AFH-BFH

Enable keyboard

FOH-FFH

Pulse output port

AAH
ABH

Reserved
Read test inputs
Write status
register

Reserved

Keyboard-Interface Controller - Hardware Description

-8 - 9

Read Command Byte (20H)
Write Command Byte (60H)
The keyboard-interface controller has an internally stored command byte that
determines how the interface controller responds to various conditions. The two
commands, read command byte and write command byte, provide access to
that command byte. When the keyboard-interface controller receives a readcommand-byte command, it places the internally stored command byte in the
output buffer. When the keyboard-interface controller receives a writecommand-byte command, it stores the next data byte, written to the input data
register at 1/0 address 0060H, to the internally stored command byte. Table
8-4 defines the command byte bits.
Table 8-4

Command Byte Bit Definitions

Bit

R/W Definition

7
6

R/W Always 0
R/W Scan Code Type
o = The LK250 scan codes are passed through without conversion 'pass-through mode).
1 = The keyboard-interface controller converts the LK250 keyboard scan codes to industry-standard one byte values
(translate mode).
R/W Interface Type - Always 0
R/W Disable Keyboard
o = Keyboard enabled
1 = Keyboard disabled
The keyboard-interface controller disables the keyboard by setting
the clock line to a low state. This bit is cleared by writing this
command byte or by writing LK250 keyboard data to the input
data register at 1/0 address 0060H.
R/W Inhibit Override
o = Keyboard inhibit switch enabled 'see status register bit 4).
1 = Keyboard inhibit switch disabled and the key lock function is
overridden 'see status register bit 4).

5
4

8- 10

Keyboard-Interface Controller - Hardware Description

Table 8-4

Command Byte Bit Definitions (cont.)

Bit

R/W Definition

R/W System Flag
o = ROM BIOS should execute a normal powerup initialization
process
1 = A virtual protected mode task request to reset the CPU to
real mode
The ROM BIOS interprets the state of the system flag to determine the reason the VAXmate CPU reset pin was toggled. If the
system flag is set, the VAXmate CPU is returning to real mode
from virtual protected mode. Otherwise, the ROM BIOS executes
a normal powerup initialization process.
During the keyboard-interface controllers powerup initialization sequence, the keyboard-interface controller clears the system flag to
zero.
See the status register bit 2 description.

R/W Always 0

R/W Enable Output-Buffer-Full Interrupt
o = Keyboard-interface controller does not generate interrupts to
the CPU
1 = When the keyboard-interface controller places data in the
output buffer, the keyboard-interface controller generates an
interrupt to the VAXmate CPU.

Keyboard-Interface Controller - Hardware Description

8- 11

Self-Test (AAH)
This command causes the keyboard-interface controller to perform internal
diagnostic tests. The command byte is reset to lOH (keyboard disabled) and
interrupts to the VAXmate CPU are disabled. The system flag (status register
bit 2) is not -changed. One of three possible diagnostic result codes is placed in
the output buffer.
Diagnostic Code

Meaning

55H
FEH
FDH

~o errors detected
Invalid ROM checksum
RAM test failed

Interface Test (ABH)
This command causes the keyboard~interface controller to test the state of the
LK250 keyboard-interface lines. One of five possible diagnostic result codes is
placed in the output buffer.
Diagnostic Code

Meaning

OOH
01H
02H
03H
04H

~o errors detected
LK250 keyboard clock line always low
LK250 keyboard clock line always high
LK250· keyboard data line always low
LK250 keyboard data line always high

Disable Keyboard (ADH)
This command sets bit 4 of the keyboard-interface controller command byte.
The keyboard-interface controller disables the keyboard-interface by setting the
clock line low.

Enable Keyboard (AEH)
This command clears bit 4 of the keyboard-interface controller command byte.
The keyboard-interface controller enables the keyboard interface by freeing the
clock line.

Read Port 1 (COH)
The keyboard-interface controller reads port 1 (bits 7-0), sets bits 3-0 to 1 (for
compatibility), and places the result in the output buffer. For port 1 bit
definitions, see Table 8·1. Because it overwrites any data in the buffer, this
command should not be used unless the output buffer is empty.

Read Port 1 (CIH)
The keyboard-interface controller reads port 1 (bits 7-0) and places bits 7-0
(without modification) in the output buffer. For port 1 bit definitions, see
8- 12

Keyboard-Interface Controller - Hardware Description

Table 8-1. Because it overwrites any data in the buffer, this command should
not be used unless the output buffer is empty.

Read Port 2 (DOH)
The keyboard-interface controller reads port 2 (bits 7-0) and places bits 7~0 in
the output buffer. For port 2 bit definitions, see Table 8-2. Because it overwrites any data in the buffer, this command should not be used unless the
output buffer is empty.

Write Port 2 (DIH)
The keyboard-interface controller takes the next byte of data written to the
input data register at 1/0 address 0060H and writes it to the keyboardinterface controller output port 2. For port 2 bit definitions, see Table 8-2.
CAUTION
Bit 0 of keyboard-interface controller output port 2 is connected
to the VAXmate CPU reset circuitry. Clearing bit 0 to a zero
places the VAXmate CPU in a permanent reset state.

Read Test Inputs (EOH)
The keyboard-interface controller reads its TO and Tl inputs and places the
data in the output buffer. This command writes over any data in the output
buffer that has not been read by the CPU. Bit 0 corresponds to the state of TO
and bit 1 corresponds to the state of Tl.

Write Status Register (EIH)
This is a diagnostic command. The keyboard-interface controller takes bits 7-4
of the next byte written to the input data register (60H) and writes them to
bits 7-4 of the status register. Only bits 7-4 are affected.
After the next keyboard-interface controller command that makes data available to the VAXmate CPU, the keyboard-interface controller updates the status
register to reflect the current status.

Pulse Output Port (FOH-FFH)
The keyboard-interface controller pulses bits 3-0 of port 2 according to the
value of bits 3-0 of the command value. Any of the bits 3-0 that are clear in
the command byte are pulsed low for approximately six microseconds.
All four bits (3-0) are affected by this command, but bits 3-2 are not connected
to anything. Bit 1 gates the address line A20. Bit 0 is connected to the
VAXmate CPU reset circuitry. The ROM BIOS uses this command to return
to real mode from virtual protected mode.

Keyboard-Interface Controller - Hardware Description

8 - 13

Keyboard-Interface Controller Error Handling
If the LK250 keyboard initiates a transmission sequence and the data is received with a parity error, the keyboard-interface controller issues a resend
command. If the response to the resend command is bad, the keyboardinterface controller places an FFH code in the output buffer and sets the parity
error bit in the status register.
If the keyboard-interface controller cannot start a transmission within 15 milliseconds or it cannot complete a transmission within two milliseconds after it
was started, the transmit timeout bit is set in the status register and an FEH
(keyboard resend request) is placed in the output buffer.
If the LK250 keyboard does not respond within 20 milliseconds, then the

transmit timeout bit and receive timeout bit are set in the status register. If
the LK250 keyboard response was received with a parity error, then the
transmit timeout bit and the parity error bit are set in the status register and
an FEH (keyboard resend request) is placed in the output buffer.
If the keyboard-interface controller has not inhibited the keyboard and a LK250

keyboard transmission does not complete within two milliseconds after it is
started, the receive timeout bit is set in the status register. A resend command
is not issued by the keyboard-interface controller.

8- 14

Keyboard-Interface Controller - Hardware Description

LK250 Keyboard
Scan Codes
When a key is pressed, the LK250 keyboard transmits a value, in the range
01H-99H, that identifies the pressed key. This value is known as a scan code.
If the key is held down for a time that exceeds the autorepeat delay time, the
keyboard repeatedly transmits the scan code at the autorepeat rate. When a
key is released, the LK250 keyboard transmits a release code of FOH followed
by the scan code of the released key.
The LK250 keyboard transmits scan codes to the keyboard-interface controller.
If the keyboard-interface controller is in pass-through mode, the keyboardinterface controller transmits the scan code or release code (FOHI and scan
code without conversion. If the keyboard-interface controller is in translate
mode, the keyboard-interface controller converts the LK250 scan code or release code (FOHI and scan code to an industry-standard I-byte value. In the
industry-standard representation, a released key is indicated by adding 80H to
the translated scan code value.
Table 8-5 lists the LK250 scan codes, their equivalent keyboard-interfacecontroller translated industry-standard value, and keyboard location label.
Figure 8-1, a representation of the LK250 keyboard, shows location labels for
each key position.
Table 8-6 lists values in the scan code range (01H-99HI that the LK250 keyboard does not use to represent keys. However, in translate mode, the
keyboard-interface controller translates them to the indicated industry-standard
value.

Keyboard-Interface Controller - Hardware Description

8- 15

,...
I

ia.

LED LED LED LED
1
2
3
4

1:1
....
So
~

(")

=
....
a

0000

....~

~
...
~

IG991GOO IG01 IG021 G03

..:..

I G05 G06 1 G071 G081 G09]

[G11IG121G131G141

I G15 1

G16

IG201 G21\ G22\ G231

1:1

- i=
...
~

...

E16 E17 E18

E20 E21 E22 E23

016 017 018

020 021 022 023

C17

C20 C21 C22 C23

a.==
lD

~...
~

0~
rn

.......

"a
....

1:1

loti

rn
....
....=
....
g

t""

!!!.
rn

C99

B16 B17 B18

B20 821 B22
A20
-

A23

A22
~

~~~

LJ-1310

Table 8-5

LK250 Scan Codes and Industry-Standard Equivalent Value

LK250
Scan
Code

Translated
Industry-Standard
Scan Code

Keyboard
Position

Key Name

OlH
03H
04H

43H
3FH
3DH

G08
G03
GOI

F9
F5
F3

05H
06H
09H
OAH

3BH
3CH
44H
42H

G99
GOO
G09
G07

Fl
F2
FlO
F8

OBH
OCH
ODH
OEH

40H
3EH
OFH
29H

G05
G02
DOO
BOO

F6
F4
Tab
'

llH
l2H
l4H
l5H

38H
2AH
lDH
10H

A99
B99
C99
DOl

Alt
Left Shift
Ctrl
qQ

l6H
lAH
lBH
lCH

02H
2CH
lFH
lEH

EOI
BOI
COl
COl

1!
zZ
s S
aA

lDH
lEH
2lH
22H

llH
03H
2EH
2DH

D02
E02
B03
B02

wW
2@
cC
xX

23H
24H
25H
26H

20H
l2H
05H
04H

C03
D03
E04
E03

dD
eE
4$
3 #

29H
2AH
2BH
2CH

39H
2FH
2lH
l4H

AOI
B04
C04
D05

Space Bar
vV
fF
tT

Keyboard-Interface Controller - Hardware Description

8 - 17

Table 8-5

LK250 Scan Codes and Industry-Standard Equivalent Value (cont.~

LK250
Scan
Code

Translated
Industry-Standard
Scan Code

Keyboard
Position

Key Name

20H
2EH
31H
32H

13H
06H
31H
30H

004
E05
B06
B05

rR
5%
oN
bB

33H
34H
35H
36H

23H
22H
15H
07H

C06
C05
006
E06

hH
gO
yY
6•

3AH
3BH
3CH
30H

32H
24H
16H
08H

B07
C07
007
E07

mM
j J
uU
7&

3EH
41H
42H
43H

09H
33H
25H
17H

E08
B08
C08
008

8 '"
,<
kK
i I

44H
45H
46H
49H

18H
OBH
OAH
34H

009
E10
E09
B09

o 0 (Letter~

4AH
4BH
4CH
40H

35H
26H
27H
19H

B10
C09
C10
010

I?
IL
,.

4EH
52H
54H
55H

OCH
28H
1AH
OOH

Ell
Cll
011
E12

58H
59H
5AH
5BH

3AH
36H
1CH
1BH

COO
B11
C13
012

8 - 18

o)
9 (
.>

pP
'Ii

[{

Lock
Right Shift
Return

]}

Keyboard-Interface Controller - Hardware Description

Table 8-5

LK250 Scan Codes and Industry-Standard Equivalent Value (cont.)

LK250
Scan
Code

Translated
Industry-Standard
Scan Code

Keyboard
Position

Key Name

5DH
66H
69H
6BH
6CH
70H
71H
72H

2BH
OEH
4FH
4BH
47H
52H
53H
50H

E12
E13
B20
C20
D20
A20
A22
B21

73H
74H
75H
76H

4CH
4DH
48H
01H

C21
C22
D21
E20

5
6 Right-Arrow
8 Up-Arrow
Esc

77H
79H
7AH
7BH

45H
4EH
51H
4AH

NumLock
+ (Keypad)
3 PgDn
- (Keypad)

7CH
7DH
7EH
7FH

37H
49H
46H
54H

E21
C23
B22
D23
E23
D22
E22

83H
84H
85H
86H

41H
54H
55H
56H

006
023
E16
E17

F7
F20
Find
Insert Here

87H
88H
89H
8AH
8BH
8CH
8DH
8EH

57H
58H
59H
5AH
5BH
5CH
5DH
5EH

E18
016
D17
D18
C17
B16
B17
B18

Remove
Select
Prev
Next
Up-Arrow
Left-Arrow
Down-Arrow
Right-Arrow

Delete (Word/Char)
1 End
4 Left-Arrow
7 Home

o Ins

. Del
2 Down-Arrow

PrtSc •
9 PgUp
ScrlLock Break
SysReq (Alt/F20)

Keyboard-Interface Controller - Hardware Description

8 - 19

Table 8-5

LK250 Scan Codes and Industry-Standard Equivalent Value (cont.)

LK250
Scan
Code

Translated
Industry-Standard
Scan Code

8F8
908
918
92H

5F8
60H
618
62H

938
948
958
96H

638
648
65H
66H
67H
688
69H

978
988
99H

8 - 20

Keyboard
Position

Key Name

011
012
013
014
015
016
020
021
022
EOO
A23

F11
F12
F13
F14
Help
Do
F17
F18
F19
Compose
Enter (Keypad)

Keyboard-Interface Controller . Hardware Description

Table 8-6

Scan Codes Translated But Not Used

Unused
Scan
Code

Translated
Industry-Standard
Scan Code

Unused
Scan
Code

Translated
Industry-Standard
Scan Code

02H
07H
08H
OFH
10H
13H
17H
18H

41H
58H
64H
59H
65H
70H
6AH
66H

51H
63H
66H
67H
5CH
6EH
6FH
60H

73H
74H
62H
6EH
76H
63H
76H
56H

19H
1FH
20H
27H
28H
2FH
30H
37H
38H
39H
3FH
40H

71H
5BH
67H
6CH
68H
50H
69H
5EH
6AH
72H
5FH
6BH

56H
77H
78H
79H
7AH
7BH
7CH
70H
7EH
7FH
6FH
57H

47H
48H
4FH
50H

60H
6CH
61H
60H

61H
62H
63H
64H
66H
67H
68H
6AH
60H
6EH
6FH
78H
80H
81H
82H

80H
81H
82H

Keyboard-Interface Controller - Hardware Description

8 - 21

LK250 Keyboard Command Codes
Table 8-7 provides a summary of the LK250 command codes. Following Table
8-7 are descriptions of each command. The command descriptions give the purpose of the command, the actions taken by the keyboard, and the response
code transmitted by the LK250 keyboard. The LK250 keyboard response codes
are described later in this chapter.
Table 8-7

LK250 Keyboard Command Codes

Value

Description

OOH-AAH
ABH

Invalid Commands

ACH

Enter Digital Extended Scan Code Mode

ADH
AEH

Exit Digital Extended Scan Code Mode
Set Keyboard LED (Digital Extended)

AFH

Reset Keyboard LED (Digital Extended)

BOH

Set Keyclick Volume (Digital Extended)

BlH

Enable Autorepeat

B2H

Disable Autorepeat

B3H

Keyboard Mode Lock

B4H

Keyboard Mode Unlock

B5H-ECH

Reserved

EDH

LEDs On/Off

EEH

Echo

EFH-F2H

Reserved

F3H

Set Autorepeat Delay and Rate

F4H

Enable Key Scanning

F5H

Disable Key Scanning and Restore to Defaults

F6H

Restore To Defaults

F7H-FDH

Reserved

FEH

Resend

FFH

Reset

8- 22

Request Keyboard ID (Digital Extended)

Keyboard-Interface Controller - Hardware Description

Invalid Commands (OOH-AAH)
I ndllstry-Standard
When the LK250 keyboard receives a code in the range OOH-AAH, it transmits
a res end request. The LK250 keyboard does not transmit an acknowledge
(ACK) for codes in this range.

Request Keyboard ID (ABH)
DIGITAL Extended
When the LK250 keyboard receives the code ABH, the keyboard clears its
output buffer and transmits a 2-byte response that identifies the version and
mode of the LK250 keyboard. The first byte returned is the version number.
The second byte is the current operating mode, 01H for industry-standard
mode or 02H for DIGITAL extended mode.
To successfully execute this command, the keyboard-interface controller must
be in pass-through mode. Otherwise, the keyboard controller attempts to
translate the data to an industry-standard scan code.
The LK250 keyboard does not transmit an acknowledge (ACK) for this
command.

Enter DIGITAL Extended Scan Code Mode (ACH)
DIGITAL Extended
When the LK250 keyboard receives the code ACH, the keyboard enables
DIGITAL extended mode, turns off LED #4, and transmits an acknowledge
(ACK).

Exit DIGITAL Extended Scan Code Mode (ADH)
DIGITAL Extended
When the LK250 keyboard receives the code ADH, the keyboard enables
industry-standard mode, turns on LED #4, and transmits an acknowledge
(ACK).
In this mode, only industry-standard scan codes are generated.

Set Keyboard LED (AEH)
DIGITAL Extended
When the LK250 keyboard receives the code AEH, the keyboard turns on LED
#4, and transmits an acknowledge (ACK). For LEDs 1-3, see LEDs On/Off
(EDH).

Keyboard-Interface Controller - Hardware Description

8- 23

Reset Keyboard LED (AFH)
DIGITAL Extended
When the LK250 keyboard receives the code AFH, the keyboard turns off LEO
114, and transmits an acknowledge (ACK). For LEOs 1-3, see LEOs On/Off

(EOH).

Set Keyclick Volume (BOH)
DIGITAL Extended
This is a 2-byte command consisting of a command byte and a value byte.
When the LK250 keyboard receives the code BOH, the keyboard stops scanning
for keys, transmits an acknowledge (ACK), and waits for the second byte.
When the LK250 keyboard receives the second byte, the keyboard sets the
volume to the indicated value, transmits an acknowledge (ACK) and returns to
the previous scanning state.
If bit 7 of the value byte is set to 1, the value is interpreted as a command.
The current command is aborted, the new command is executed and the LK250
returns to the previous scanning state.

The volume value byte can have one of the following values:
Value

Volume

OOH

No keyclick

02H

Soft

04H

Medium

06H

Loud

Enable Autorepeat (BtH)
DIGITAL Extended
When the LK250 keyboard receives the code BIH, the keyboard enables autorepeat for all keys and transmits an acknowledge (ACK). Autorepeat enabled is
the default condition.

Disable Autorepeat (B2H)
DIGITAL Extended
When the LK250 keyboard receives the code B2H, the keyboard disables autorepeat for all keys and transmits an acknowledge (ACK).

8- 24

Keyboard-Interface Controller - Hardware Description

Keyboard Mode Lock (B3H)
DIGITAL Extended
When the LK250 keyboard receives the code B3H, the keyboard disables the
key combination ALT/F17 and transmits an acknowledge (ACK). The key combination ALT/F17 toggles the keyboard between DIGITAL extended mode and
industry-standard mode. This key combination is detected and handled by the
keyboard, not the ROM BIOS.

Keyboard Mode Unlock (B4H)
DIGITAL Extended
When the LK250 keyboard receives the code B4H, the keyboard enables the
key combination ALT/F17 and transmits an acknowledge (ACK). The key combination ALT/F17 toggles the keyboard between DIGITAL extended mode and
industry-standard mode. This key combination is detected and handled by the
keyboard, not the ROM BIOS. ALT/F17 enabled is the default condition.

Reserved (B5H-ECH)
DIGITAL Extended
When the LK250 keyboard receives any of the reserved codes B5H-ECH, the
keyboard transmits an acknowledge (ACK) and resumes its previous scanning
state.

Keyboard-Interface Controller - Hardware Description

8 - 25

LEDs On/Off (EDH)
DIGITAL Extended

This is a 2-byte command consisting of a command byte and a value byte.
When the LK250 keyboard receives the code EDH, the keyboard stops scanning for keys, transmits an acknowledge ~ACK}, and waits for the second byte.
When the LK250 keyboard receives the second byte, the keyboard sets the
LEDs to the indicated value, transmits an acknowledge ~ACK} and returns to
its previous scanning state.
If bit 7 of the value byte is set to 1, the value is interpreted as a command.
The current command is aborted, the new command is executed and the LK250
returns to the previous scanning state.

The bits in the LED value byte have the following meanings:
Bit

Description

7-3

Reserved, always 0

Caps Lock

o = CapsLock LED off
1 =

Caps Lock LED on

NumLock

o=
1 =
o

NumLock LED off
NumLock LED on

Scroll Lock

o=
1 =

Scroll Lock LED off
Scroll Lock LED on

Echo (EEH)
Industry-Standard

When the LK250 keyboard receives the code EEH, the keyboard transmits the
same echo code ~EEH} and continues its previous scanning state. This command is a diagnostic tool.

Reserved (EFH-F2H)
Industry-Standard

When the LK250 keyboard receives any of the reserved codes EFH-F2H, the
keyboard transmits an acknowledge ~ACK) and resumes its previous scanning
state.
8- 26

Keyboard-Interface Controller - Hardware Description

Set Autorepeat Delay and Rate (F3H)
Industry-Standard
This is a 2-byte command consisting of a command byte and a value byte.
When the LK250 keyboard receives the code F3H, the keyboard stops scanning
for keys, transmits an acknowledge lACK), and waits for the second byte.
When the LK250 keyboard receives the second byte, the keyboard sets the
autorepeat delay and rate to the indicated values, transmits an acknowledge
lACK) and returns to its previous scanning state.
If bit 7 of the value byte is set to 1, the value is interpreted as a command.
The current command is aborted, the new command is executed and the LK250
returns to the previous scanning state.

The bits in the delay and rate value byte have the following meanings:
Bit

Description

Always 0

6-5

Autorepeat delay (± 20%)
00 =
01 =
10 =
11 =

4-0

.25 seconds
.5 seconds
.75 seconds
1. 0 second

Autorepeat rate (±
20%)
Bits 4-0

Rate per second

Bits 4-0

Rate per second

00000 =
00001 =
00010 =
00011 =
00100 =
00101 =
00110 =
00111 =
01000 =
01001 =
01010 =
01011 =
01100 =
01101 =
01110 =
01111 =

29.98
26.65
23.98
21.80
19.98
18.45
17.13
15.99
14.99
13.32
11.99
10.90
9.99
9.22
8.56
7.99

10000 =
10001 =
10010 =
10011 =
10100 =
10101 =
10110 =
10111 =
11000 =
11001 =
11010 =
11011 =
11100 =
11101 =
11110 =
11111 =

7.49
6.66
6.00
5.45
5.00
4.61
4.28
4.00
3.75
3.33
3.00
2.73
2.50
2.31
2.14
2.00

Keyboard-Interface Controller - Hardware Description

8- 27

Enable Key Scanning (F4H)
Industry-Standard

When the LK250 keyboard receives the code F4H, the keyboard clears its
output buffer. transmits an acknowledge (ACKI, and begins scanning for keys.
Use of this command assumes that key scanning was previously disabled. Any
key strokes that were recognized but not transmitted are lost.

Disable Key Scanning and Restore to Defaults (F5H)
Industry-Standard

When the LK250 keyboard receives the code F5H, the keyboard stops scanning, clears its output buffer, restores conditions to the default powerup state,
transmits an acknowledge (ACKI, and waits for additional commands. Keyboard
scanning remains disabled. Any key strokes that were recognized but not
transmitted are lost.
Feature

Default

Autorepeat delay
Autorepeat rate
ALT/F17 mode toggle
LEDs
Digital extended mode

.5 seconds
29.98 per second
Enabled
Off
Disabled

Restore To Defaults (F6H)
Industry-Standard

Default

Autorepeat delay
Autorepeat rate
ALT/F17 mode toggle
LEDs
Digital extended mode

.5 seconds
29.98 per second
Enabled
Off
Disabled

8- 28

Keyboard-Interface Controller - Hardware Description

Reserved (F7H-FDH)
Industry-Standard
When the LK250 keyboard receives any of the reserved codes F7H-FDH, the
keyboard transmits an acknowledge (ACKI and resumes its previous scanning
state.
Resend (FEH)
Industry-Standard
When the LK250 keyboard receives the code FEH, the keyboard repeats its
last transmission. This command is used when the keyboard-interface controller
detects a reception error. It can be sent only in response to a transmission
from the LK250 keyboard. Additionally, the resend command (FEHI must be
transmitted before the keyboard-interface controller allows the keyboard to
start another transmission. If the retransmitted data is still bad, the keyboardinterface controller places FFH in its output buffer and sets the parity error
and timeout error status bits.
Reset (FFH)
Industry-Standard
When the LK250 keyboard receives the code FFH, the keyboard transmits an
acknowledge (ACKI and waits for the the acknowledge to be accepted. Receipt
of the acknowledge (ACK) is indicated by reading the acknowledge (ACK) from
the keyboard-interface controller, setting port 2 bits 7-6 to 1, and leaving them
set for at least 500 p,s. When the keyboard recognizes acceptance of the acknowledge (ACK), the keyboard invokes its self-test diagnostic. On completing
the self-test, the keyboard transmits AAH (self-test success) or FCH (self-test
failurel. As a result of the self-test, the keyboard is reset to default conditions
and the keyboard output buffer is empty.
Feature

Default

Autorepeat delay
Autorepeat rate
ALT/F17 mode toggle
LEOs
Digital extended mode

.5 seconds
29.98 per second
Enabled
Off
Disabled

Keyboard-Interface Controller - Hardware Description

8- 29

LK250 Keyboard Responses
The LK250 keyboard must reply to every transmission sent to it. Most of the
time the reply is an acknowledge (ACK), but some commands have special
responses. Refer to LK250 keyboard command descriptions for details. Table
8-8 lists the LK250 keyboard responses.
Table 8-8

LK250 Keyboard Responses

Value

Description

OOH

Buffer Overrun

AAH

Self-Test Success

EEH

ECHO

FAH

Acknowledge (ACK)

FCH

Power-Up Self-Test Failure

FDH

Not Used

FEH

Resend

Buffer overrun (OOH)
Industry-Standard

This code indicates that the LK250 keyboard output buffer (20 bytes) has been
filled to capacity (19 key codes) and an attempt was made to store another
code. The 20th code is replaced with OOH.
If the keyboard-interface controller is in translate mode, the LK250 keyboard

buffer-overrun code OOH is translated to an industry-standard buffer overrun
code of FFH.

Self-test success (AAH)
Industry-Standard

This code indicates successful completion of the LK250 keyboard self-test diagnostics. The self-test diagnostics are invoked as part of the powerup sequence
and by the reset command (FFH).

ECHO (EEH)
Industry-Standard

This code indicates receipt of an echo command (EEH). In response to an echo
command (EEH), the LK250 transmits echo (EEH) instead of acknowledge
(ACK) (FAH).

8- 30

Keyboard-Interface Controller . Hardware Description

Release Prefix (FOH)
Industry-Standard

This code indicates that a key was released. It is followed by the scan code of
the released key.
If the keyboard-interface controller is in translate mode, this 2-byte sequence is

translated to an industry-standard I-byte release code by adding 80H to the
translated scan code.

Acknowledge (ACK) (FAH)
Industry-Standard

This code is transmitted by the LK250 keyboard in response to most of the
valid commands. Some commands have special responses. For example, request
keyboard identification (ABHI, echo (EEHI, and resend (FEHI. For additional
information, see the descriptions of the LK250 keyboard commands.

Self-Test Failure (FCH)
Industry-Standard

This code transmitted by the LK250 keyboard to indicate that a keyboard component failed the self-test diagnostics. Self-test is invoked during the powerup
sequence and the reset command (FFHI.

Resend (FEH)
Industry-Standard

This code is transmitted by the LK250 keyboard in response to a keyboardinterface controller transmission containing a parity error. Providing that the
last transmission to the keyboard was not a resend command (FEHI, the keyboard interrupt handler should retransmit the last keyboard command.

LK250 Keyboard Error Handling
If the LK250 keyboard receives an invalid command or a parity error, it replies
with a resend command.

U.S. and Foreign Keyboards
The LK250 keyboard is shipped with key legends appropriate for the destination country. Figure 8-2 through Figure 8-15 show the key legends for the
various country keyboards.

Keyboard-Interface Controller - Hardware Description

8 - 31

Figure 8-2

8- 32

U.S./U.K. Keyboard

Keyboard-Interface Controller - Hardware Description

~: ~.

;.
z

•

Figure 8-3

Canadian/English Keyboard

Keyboard-Interface Controller - Hardware Description

8- 33

Figure 8-4

8- 34

Danish Keyboard

Keyboard-Interface Controller - Hardware Description

Figure 8·5

Finnish Keyboard

Keyboard·Interface Controller· Hardware Description

8- 35

Figure 8-6

8- 36

French/Canadian Keyboard

Keyboard-Interface Controller - Hardware Description

Figure 8-7

French Keyboard

Keyboard-Interface Controller - Hardware Description

8- 37

Figure 8-8

8- 38

German/Austrian Keyboard

Keyboard-Interface Controller - Hardware Description

Figure 8-9

Hebrew Keyboard

Keyboard-Interface Controller - Hardware Description

8- 39

I~
,

•il
,

.1.!

Figure 8·10

8- 40

Italian Keyboard

Keyboard·Interface Controller· Hardware Description

Figure 8-11

Norwegian Keyboard

Keyboard-Interface Controller - Hardware Description

8- 41

II
~

~I
}

<>1

~
~

Figure 8-12

8- 42

Spanish Keyboard

Keyboard-Interface Controller - Hardware Description

Figure 8-13

Swedish Keyboard

Keyboard-Interface Controller - Hardware Description

8- 43

Figure 8-14

8- 44

Swiss/French Keyboard

Keyboard-Interface Controller - Hardware Description

Figure 8-15

Swiss/German Keyboard

Keyboard-Interface Controller - Hardware Description

8- 45

Programming Example
The subroutines in the keyboard example provide keyboard input support for all
of the examples in this manual. The keyboard example demonstrates:
• Communicating with the keyboard-interface controller
• The use of keyboard translation tables
• Extended features of the LK250 keyboard
CAUTION
Improper programming or improper operation of this device can
cause the VAXmate workstation to malfunction. The scope of
the programming example is limited to the context provided in
this manual. No other use is intended.
The example provides routines as described in the following list.
wr kcc

Writes a command byte to the keyboard-interface controller

wr kcd

Writes a data byte to the keyboard-interface controller

pass_thru

Sets the keyboard-interface controller to pass-through mode

kyb_init

Prepares the interrupt structure for keyboard interrupts

wr_kyb

Places data in a ring buffer for output to the keyboard

kyb_led

Turns LEDs on or off according to the keyboard state

kyb_send

Retrieves data from a ring buffer and writes it to the keyboard

kybJest
get_key

Restores the previous keyboard interrupt structure
Gets a I-byte value from the keyboard input ring buffer

kyb_int_hand Handles keyboard-interface-controller interrupts and performs
scan code translations
Provides an example environment for examining various aspects
of the keyboard

8- 46

Keyboard-Interface Controller - Programming Example

#include "rb.h"
#include "example.h"

/***********************************************************************/
/* define constants and structures used in keyboard examples
*/
/***********************************************************************/
#define COMMAND Ox64
#define DATAREG Ox60

/* command register in I/O space */
/* data register in I/O space */

/* define mask bits for keyboard state flag */
#define S_LSHF
#define S_RSHF
#define S_CTRL
#define S_ALT
#define S_SCRL
#define S_NUM
#define S_CAPS
#define S_INS

OxOl
Ox02
Ox04
Ox08
Oxl0
Ox20
Ox40
Ox80

/* left shift key is pressed */
/* right shift key is pressed */
/* control key is pressed */
/* Alternate key is pressed */
/* Scroll lock is in effect */
/* Numerics lock is in effect */
/* Caps lock is in effect */
/* Insert mode is active */

/* define modifier-key values returned by keyboard */
#define CTRL
#define LSHF
#define RSHF
#define ALT
#define CAPS
#define NUML
#define SCRL
#define INS
#define DEL

Oxld
Ox2a
Ox36
Ox38
Ox3a
Ox46
Ox46
Ox62
Ox53

/* control key */
/* left shift key */
/* right shift key */
/* alternate key */
/* Lock/Caps Lock key */
/* NumLock key */
/* ScrlLock key */
/* Ina (Insert) key */
/* Del key */

/* define some keyboard interface controller commands */
#define RDCB
#define WRCB

Ox20
Ox60

/* read command byte */
/* write command byte */

Keyboard-Interface Controller - Programming Example

8- 47

/* define some keyboard commands */
#define LED123 Oxed
#define LED4_0N Oxae
#define LED4_0F Oxaf
#define ENT_EXM Oxac
#define EXT_EXM Ox ad
#define AREPON Oxbl
#define AREPOFF Oxb2
#define SETAR
Oxf3
#define SETVOL OxbO
#define KYBID
Oxab
#define RESDEF Oxf6

/* control leds 1,2, and 3 */
/* turn led #4 on */
/* turn led #4 off */
/* enter DIGITAL extended keyboard mode */
/* exit DIGITAL extended keyboard mode */
/* auto-repeat on */
/* auto-repeat off */
/* set auto-repeat rate */
/* set speaker volume */
return
keyboard
ID and state */
/*
reset
keyboard
to
default
values */
/*

/* define some keyboard responses */
#define B_FULL
#define RESEND
#define ACK

OxOO
Oxfe
Oxfa

/* keyboard buffer full */
/* request to resend command or data */
/* keyboard acknowledge */

/* define some state dependent keyboard table index constants */
/* Note: The ROM BIOS has separate alpha and numeric tables. */
This example combines the alpha and numeric tables. */
/*
#define T_NORM
#define LALT
#define T_CTRL
#define T_SHFT
#define T_A_N

OxOO
Ox02
Ox04
Ox06
Ox08

/* look in normal key table */
/* look in alternate combination table */
/* look in control key table */
/* look in shift table */
/* look in alphanumeric table */

#define KB_SIZ

128

/* example keyboard buffer size is 128 bytes */

8- 48

Keyboard-Interface Controller - Programming Example

/***********************************************************************/
/* define key translation tables and variables

/***********************************************************************/
unsigned char kyb_state;
unsigned char last_send;
unsigned char key_buff [2] [KB_SIZ];
unsigned char released;
unsigned char depressed;
RING_BUFF kLrb;
RING_BUFF ko_rb;

/* state of modifier keys */
/* last character sent to keyboard */
/* place to store incoming keys */
/* last released key for demo */
/* last depressed key for demo */

/* ring buffer control structure */
/* ring buffer control structure */

/* define the keyboard tables */
/* Note: The ROM BIOS has separate alpha and numeric tables. */
/*
This example combines the alpha and numeric tables. */
static unsigned char keyboard [Ox70] [9] {

/* NORMAL
ALT
I CONTROL
SHIFT
I A/N */
Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff,
Oxlb, OxOl, Oxff, Oxff, Oxlb, OxOl, Oxlb, OxOl, OxOO,
OxSl, Ox02, OxOO, Ox78, Oxff, Oxff, Ox2l, Ox02, OxOO,
OxS2, OxOS, OxOO, Ox79 , OxOO, OxOS, Ox40, OxOS, OxOO,
OxSS, Ox04, OxOO, Ox7a, Oxff, Oxff, Ox2S, Ox04, OxOO,
OxS4, OxOS, OxOO, Ox7b, Oxff, Oxff, Ox24 , OxOS, OxOO,
Ox3S, Ox06, OxOO, Ox7c, Oxff, Oxff, Ox2S, Ox06, OxOO,
OxS6, Ox07, OxOO, Ox7d, Oxle, Ox07, OxSe, Ox07, OxOO,
OxS7, Ox08, OxOO, Ox7e, Oxff, Oxff, Ox26 , Ox08, OxOO,
OxS8, Ox09, OxOO, Ox7f, Oxff, Oxff, Ox2a, Ox09, OxOO,
Ox39 , OxOa, OxOO, Ox80, Oxff, Oxff, Ox28 , OxOa, OxOO,
OxSO, OxOb, OxOO, Ox8l, Oxff, Oxff, Ox29 , OxOb, OxOO,
Ox2d, OxOc, OxOO, Ox82 , Oxlf, OxOc, OxSf, OxOc, OxOO,
OxSd, OxOd, OxOO, Ox8S, Oxff, Oxff, Ox2b, OxOd, OxOO,
Ox08, OxOe, Oxff, Oxff, Ox7f, OxOe, Ox08, OxOe, OxOO,
Ox09, OxOf, Oxff, Oxff, Oxff, Oxff, OxOO, OxOf, OxOO,
Ox7l, OxlO, OxOO, OxlO, Oxll, OxlO, OxSl, OxlO, S_CAPS,
Ox77 , Oxll, OxOO, Oxll, Oxl7, Oxll, OxS7, Oxll, S_CAPS,
Ox6S, Oxl2, OxOO, Oxl2, OxOS, Oxl2, Ox4S, Oxl2, S_CAPS,
Ox72 , OxlS, OxOO, OxlS, Oxl2, OxlS, OxS2, OxlS, S_CAPS,
Ox74 , Oxl4, OxOO, Oxl4, Oxl4, Oxl4, OxS4, Oxl4, S_CAPS,
Ox79 , OxlS, OxOO, OxlS, Oxl9, OxlS, OxS9, OxlS, S_CAPS,
Ox7S, Oxl6, OxOO, Oxl6, OxlS, Oxl6, OxSS, Oxl6, S_CAPS,
Ox69 , Oxl7, OxOO, Oxl7, OxOg, Oxl7, Ox49, Oxl7, S_CAPS,
Ox6f, Oxl8, OxOO, Oxl8, OxOf, Oxl8, Ox4f, Oxl8, S_CAPS,
Ox70, Oxl9, OxOO, Oxl9, OxlO, Oxl9, Ox SO , Oxl9, S_CAPS,
OxSb, Oxla, Oxff, Oxff, Oxlb, Oxla, Ox7b, Oxla, OxOO,

/* overrun */
/* ESC */
/* I */
/* 2 */
/* S */
/* 4 */
/* S */
/* 6 */
/* -; */
/* 8 */
/* 9 */
/* 0 */
/* - */
/* - */
/* BS */

Keyboard-Interface Controller - Programming Example

/* TAB */
/* Q */
/* w*/
/* E */
/* R */
/* T */
/* y */
/* u */
/* I */
/* 0 */
/* p */
/* [ */

8- 49

Ox6d, Oxlb, Oxff, Oxff, Oxld, Oxlb, Ox7d, Oxlb, OxOO,
1* ] *1
OxOd, Oxlc, Oxff, Oxff, OxOa, Oxlc, OxOd, Oxlc, OxOO,
1* RET *1
Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
1* CTRL *1
Ox61, Oxle, OxOO, Oxle, OxOl, Oxle, Ox41, Oxle, S_CAPS,
1* A *1
Ox7S, Oxlf, OxOO, Oxlf, OxlS, Oxlf, Ox6S, Oxlf, S_CAPS,
1* S *1
Ox64 , Ox20, OxOO, Ox20, Ox04, Ox20, Ox44 , Ox20, S_CAPS,
1* D *1
Ox66 , Ox21, OxOO, Ox21, Ox06, Ox21, Ox46 , Ox21, S_CAPS,
1* F *1
Ox67 , Ox22 , OxOO, Ox22 , Ox07, Ox22 , Ox47 , Ox22 , S_CAPS,
1* G *1
Ox68 , Ox2S, OxOO, Ox2S, Ox08, Ox2S, Ox48 , Ox2S, S_CAPS,
1* G *1
Ox6a, Ox24 , OxOO, Ox24 , OxOa, Ox24 , Ox4a, Ox24 , S_CAPS,
1* J *1
Ox6b, Ox25 , OxOO, Ox26 , OxOb, Ox26 , Ox4b, Ox26 , S_CAPS,
1* K *1
Ox6c, Ox26 , OxOO, Ox26 , OxOc, Ox26 , Ox4c, Ox26 , S_CAPS,
1* L *1
OxSb, Ox27 , Oxff, Oxff, Oxff, Oxff, OxSa, Ox27 , OxOO,
1* *1
Ox27 , Ox28 , Oxff, Oxff, Oxff, Oxff, Ox22 , Ox28 , OxOO,
1* ' *1
Ox60, Ox29 , Oxff, Oxff, Oxff, Oxff, Ox7e, Ox29 , OxOO,
1* • *1
Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
1* LS *1
Ox6c, Ox2b, Oxff, Oxff, Oxlc, Ox2b, Ox7c, Ox2b, OxOO,
1* \ *1
Ox7a, Ox2c, OxOO, Ox2c, Oxla, Ox2c, Ox6a, Ox2c, S_CAPS,
1* Z *1
Ox78, Ox2d, OxOO, Ox2d, Oxl8, Ox2d, Ox58 , Ox2d, S_CAPS,
1* X *1
Ox6S, Ox2e, OxOO, Ox2e, Ox03, Ox2e, Ox4S, Ox2e, S_CAPS,
1* C *1
Ox76 , Ox2f, OxOO, Ox2f, Ox16, Ox2f, Ox66 , Ox2f, S_CAPS,
1* V *1
Ox62 , OxSO, OxOO, OxSO, Ox02, Ox30, Ox42 , OxSO, S_CAPS,
1* B *1
Ox6e, OxSl, OxOO, OxSl, OxOe, OxSl, Ox4e, OxSl, S_CAPS,
1* N *1
Ox6d, OxS2, OxOO, OxS2, OxOd, OxS2, Ox4d, OxS2, S_CAPS,
1* M *1
Ox2c, Ox3S, Oxff, Oxff, Oxff, Oxff, Ox3c, Ox3S, OxOO,
1* , *1
Ox2e, OxS4, Oxff, Oxff, Oxff, Oxff, Ox3e, Ox34 , OxOO,
1* *1
Ox2f, Ox35 , Oxff, Oxff, Oxff, Oxff, Ox3f, OxS6, OxOO,
1* I *1
Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
1* Right Shift *1
Ox2a, OxS7, Oxff, Oxff, OxOO, Ox72, Oxff, Oxff, OxOO,
1* PRTSC *1
Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
1* ALT *1
Ox20, Ox39 , Ox20, OxS9, Ox20, Ox39 , Ox20, OxS9, OxOO,
Space
Bar *1
1*
Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
1* CAPS Lock *1
OxOO, Ox3b, OxOO, Ox68 , OxOO, OxSe, OxOO, Ox64 , OxOO,
1* Fl *1
OxOO, Ox3c, OxOO, Ox69 , OxOO, OxSf, OxOO, OxS5, OxOO,
1* F2 *1
OxOO, OxSd, OxOO, Ox6a, OxOO, Ox60, OxOO, Ox66 , OxOO,
1* FS *1
OxOO, OxSe, OxOO, Ox6b, OxOO, Ox61, OxOO, OxS7, OxOO,
1* F4 *1
OxOO, OxSf, OxOO, Ox6c, OxOO, Ox62 , OxOO, Ox68 , OxOO,
1* F6 *1
OxOO, Ox40, OxOO, Ox6d, OxOO, Ox6S, OxOO, Ox69 , OxOO,
1* F6 *1
OxOO, Ox41, OxOO, Ox6e, OxOO, Ox64 , OxOO, Ox5a, OxOO,
1* F7 *1
OxOO, Ox42 , OxOO, Ox6f, OxOO, Ox65 , OxOO, Ox6b, OxOO,
1* F8 *1
OxOO, Ox4S, OxOO, Ox70, OxOO, Ox66 , OxOO, Ox6c, OxOO,
1* F9 *1
OxOO, Ox44 , OxOO, Ox71, OxOO, Ox67 , OxOO, Ox6d, OxOO,
1* FlO *1
Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
1* NumLock *1
Oxff, Oxff, Oxff, Oxff, OxOO, OxOO, Oxff, Oxff, OxOO,
1* ScrlLock *1
OxOO, Ox47 , Ox07, OxOO, OxOO, Ox77, OxS7, Ox47 , S_NUM,
1* keypad 7 *1
OxOO, Ox4B, OxOB, OxOO, Oxff, Oxff, OxSB, Ox4B, S_NUM,
1* keypad B *1
OxOO, Ox49 , Ox09, OxOO, OxOO, OxB4, OxS9, Ox49 , S_NUM,
1* keypad 9 *1

8- 50

Keyboard-Interface Controller - Programming Example

Ox2d, Ox4a, Oxff, Oxff, Oxff, Oxff, Ox2d, Ox4a, OxOO,
OxOO, Ox4b, Ox04, OxOO, OxOO, Ox73, Ox34 , Ox4b, S_NUM,
Oxff, Oxff, OxOS, OxOO, Oxff, Oxff, Ox3S, Ox4e, S_NUM,
OxOO, Ox4d, Ox06, OxOO, OxOO, Ox74 , Ox36 , Ox4d, S_NUM,
Ox2b, Ox4e, Oxff, Oxff, Oxff, Oxff, Ox2b, Ox4e, OxOO,
OxOO, Ox4f, OxOl, OxOO, OxOO, Ox7S, Ox31 , Ox4f, S_NUM,
OxOO, Ox50, Ox02, OxOO, Oxff, Oxff, Ox32 , OxSO, S_NUM,
OxOO, Ox51 , Ox03, OxOO, OxOO, Ox76 , Ox33 , OxSl, S_NUM,
OxOO, Ox52 , OxOO, OxOO, Oxff, Oxff, Ox30, OxS2, S_NUM,
OxOO, OxS3, Oxff, Oxff, Oxff, Oxff, Ox2e, OxS3, S_NUM,
OxOO, Ox98 , Oxff, Oxff, OxOO, OxbO, OxOO, Oxa4, OxOO,
OxOO, Ox8S, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
OxOO, Ox86 , Oxff, Oxff, OxOO, Oxe3, Oxff, Oxff, OxOO,
OxOO, Ox87 , Oxff, Oxff, OxOO, Oxel, Oxff, Oxff, OxOO,
OxOO, Ox88 , Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
OxOO, Ox89 , Oxff, Oxff, OxOO, Oxe4, Oxff, Oxff, OxOO,
OxOO, Ox8a, Oxff, Oxff, OxOO, Oxe2, Oxff, Oxff, OxOO,
OxOO, Ox8b, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
OxOO, Ox8e, Oxff, Oxff, OxOO, Oxbf, Oxff, Oxff, OxOO,
OxOO, Ox8d, Oxff, Oxff, OxOO, OxeO, Oxff, Oxff, OxOO,
OxOO, Ox8e, Oxff, Oxff, Oxff, Oxff, Oxff, Oxff, OxOO,
OxOO, Ox8f, OxOO, Oxb3, OxOO, Oxa7, OxOO, Ox9b, OxOO,
OxOO, Ox90, OxOO, Oxb4, OxOO, Oxa8, OxOO, Oxge, OxOO,
OxOO, Ox91 , OxOO, OxbS, OxOO, Oxa9, OxOO, Ox9d, OxOO,
OxOO, Ox92 , OxOO, Oxb6, OxOO, Oxaa, OxOO, Oxge, OxOO,
OxOO, Ox93 , OxOO, Oxb7, OxOO, Oxab, OxOO, Ox9f, OxOO,
OxOO, Ox94 , OxOO, Oxb8, OxOO, Oxae, OxOO, OxaO, OxOO,
OxOO, Ox9S, OxOO, Oxb9, OxOO, Oxad, OxOO, Oxal, OxOO,
OxOO, Ox96 , OxOO, Oxba, OxOO, Oxae, OxOO, Oxa2, OxOO,
OxOO, Ox97 , OxOO, Oxbb, OxOO, Oxaf, OxOO, Oxa3, OxOO,
OxOO, Oxbd, OxOO, Oxbd, OxOO, Oxbd, OxOO, Oxbd, OxOO,
OxOd, Ox9a, OxOO, Oxbe, OxOO, Oxb2, OxOO, Oxa6, OxOO,

/* keypad - */
/* keypad 4 */
/* keypad 6 */
/* keypad 6 */
/* keypad + */
/* keypad 1 */
/* keypad 2 */
/* keypad 3 */
/* keypad 0 */
/* keypad . */
/* F20 */
/* FIND */
/* INSERT */
/* REMOVE */
/* SELECT */
/* PREY */
/* NEXT */
/* UP */
/* LT */
/* RT */
/* ON */
/* F11 */
/* F12 */
/* F13 */
/* F14 */
/* F1S */
/* F16 */
/* F17 */
/* F18 */
/* F19 */
/ * COMPOSE */
/* ENTER */

};

Keyboard-Interface Controller - Programming Example

8- 51

/***********************************************************************/
/* wr_kcc() - Write keyboard controller command

/***********************************************************************/

/* command byte to write */

unsigned char cmd;
{

outp(COMMAND. cmd);
while((inp(COMMAND) t Ox02»

/* write command byte */
/* wait until KC has read command */

}

/***********************************************************************/

/* wr_kcd() - Write keyboard controller data

/***********************************************************************/

unsigned char data;

/* data byte to write */

{

outp(DATAREG. data);
while((inp(COMMAND) t Ox02»

/* write command data */
/* wait until KC has read data */

}

8- 52

Keyboard-Interface Controller - Programming Example

/***********************************************************************/
/* pass_thru() - set keyboard controller pass through mode
*/
/***********************************************************************/
pass_thru(flag)
int flag;

/* i f TRUE, set pass through */
/* else clear pass through */

{

unsigned char c;
unsigned int intr_flag;
intr_flag = int_off();
wr_kcc(RDCB);
while(l(inp(COMMAND) ~ OxOl»

/* tmp to hold internal command byte */
/* tmp to hold CPU IF state */
/* turn interrupts off */
/* give me current command byte */
/* wait until output buffer full */

c = inp(DATAREG);
/* read command byte from data buffer */
if(flag) c ~= -Ox40;/* if TRUE, do not decode keyboard transmissions */
else c 1= Ox40;
/* else, decode keyboard transmissions */
wr_kcc(WRCB);
/* tell interface controller to write command byte */
wr_kcd(c);
/* send command byte to write */
int_on(intr_flag);
/* allow interrupts */
}

/***********************************************************************/
/* kyb_init() - keyboard interrupt initialization
*/
/***********************************************************************/

/* no states established */
/* establish ring buffers */
init_rb(tkLrb, tkey_buff[O] [0] , KB_SIZ, 30, 16);
init_rb(~ko_rb, ~key_buff[l] [0], KB_SIZ, 30, 15);
imask(O,l,O);
/* disable PIC input for keyboard interface */
iv_init(Ox09);
/* keyboard interrupt is int Ox09 */
imask(O ,1,1) ;
/* enable PIC input for keyboard interface */
}

Keyboard-Interface Controller - Programming Example

8- 53

/***********************************************************************/
/* wr_kyb() - put value in output buffer to keyboard and start send
*/
/***********************************************************************/

/* value to send to keyboard */

unsigned char value;
{

unsigned intr_flag;

/* to hold current CPU IF state */

intr_flag = int_off();
rb_in(lko_rb. value);
if(llast_send) kyb_send(O);
int_on(intr_flag);

/* CPU interrupts off */
/* put value in ring buffer */
/* if keyboard not waiting for ACK */
/* allow interrupts now */

}

/***********************************************************************/
/* kyb_led() - handle changes to LED state
*/
/***********************************************************************/
kyb_ledO
{

/* temporary state variable */

unsigned char state;
state = kyb_state »
state l= Ox01;
wr_kyb(LED123);
wr_kyb(state);

/* shift into position */
/* only bits 2:0 are valid */
/* keyboard LED command to buffer */
/* LED state to buffer */

}

/***********************************************************************/
/* kyb_send() - send command to keyboard
*/
/***********************************************************************/
kyb_send(resend)
int resend;

/* re-send character if true */

{

if(resend) outp(DATAREG. last_send);
/* re-send command or data */
else if (rb_out(lko_rb. llast_send) >= 0)/* get char from output buff */
outp(DATAREG. last_send);
/* send command or data */
else last_send = 0;
/* no character to send */
}

8- 54

Keyboard-Interface Controller - Programming Example

/***********************************************************************/
/* kyb_rest() - restore keyboard interrupts to system

/***********************************************************************/

/* keyboard interrupt is int Ox09 */
}

/***********************************************************************/
/* get_key() - get character from keyboard input buffer

/***********************************************************************/
/* get char from input buf */
UDsigned char *pc;

/* where to put character */

{

/* get char from input buff */
}

/***********************************************************************/
/* put_key() - put key sequence into keyboard input buffer

/***********************************************************************/
int put_key(pc)

/* put key seq into input buf */

UDsigned char *pc;

/* where to get sequence */

{

if(pc[O]
else

== Oxff II pc[l] == Oxff) beep{);

/* invalid key combo? */

{

rb_in{lki_rb. *pc++);
return(rb_in(lki_rb. *pc»;

/* write ASCII character */
/* write scan code */

}
}

Keyboard-Interface Controller - Programming Example

8- 66

/***********************************************************************/
/* kyb_int_hand() - keyboard interrupt handler

/***********************************************************************/

1* tmp to hold keyboard transmission */

UDsigned char key:
key - inp(DATAREG):
if(key -- B_FULL) beep():
else if(key l OxBO)

/* get keyboard transmission */
1* tell typist, buffer full */
1* key release or keyboard reply ? */

{

switch (key)
{

case ACK:
kyb_send(O):
break:

1* keyboard acknowledge ? */

case RESEND:
kyb_send(l):
break:

1* keyboard re-send request 1 */

default:
switch(released - key l Ox7f)

1* must be a key release *1
1* save released key for demo *1

{

case CTRL:
kyb_state l- -S_CTRL:
break:
case LSHF:
kyb_state l- -S_LSHF:
break:

/* left shift key released 1 *1
1* clear from state byte *1

case RSHF:
kyb_state l- -S~RSHF:
break:

1* right shift key released 1,*1
1* clear from state byte *1

case ALT:
kyb_state l= -S_ALT:
break:

1* alternate key released? *1
1* clear from state byte *1

case CAPS:
case NUNL:
case SCRL:
break:

8- 56

/* and check modifier keys */
/* control key released ? */
/* clear from state byte */

1* caps lock, numlock or scrllock released? *1
1* these are toggle keys, only means it was *1
/* released. toggle is performed when pressed *1

Keyboard-Interface Controller - Programming Example

case INS:
kyb_state t= -S_INS;
break;
default:
break;

/* insert key released ? */
/* clear from state byte */

/* no default */

}

}
}

else switch(depressed = key t Ox7f)

/* save depress key for demo */

{

case CTRL:
kyb_state
break;

1= S_CTRL;

/* control key pressed ? */
/* set in state byte */

case LSHF:
kyb_state
break;

1= S_LSHF;

/* left shift key pressed ? */
/* set in state byte */

case RSHF:
kyb_state
break;

1= S_RSHF;

/* right shift key pressed 1 */
/* set in state byte */

case ALT:
kyb_state
break;

1= S_ALT;

/* alternate key pressed 1 */
/* set in state byte */

case CAPS:
if(kyb_state t S_CAPS)
kyb_state t= -S_CAPS;
else kyb_state 1= S_CAPS;
kyb_ledO;
break;

/* caps lock key pressed ? */
/* caps on ? */
/* turn caps off */
/* otherwise, turn caps on */
/* adjust Lock LED */

case NUML:
if(kyb_state t S_NUM)
kyb_state t= -S_NUM;
else kyb_state 1= S_NUM;
kyb_ledO;
break;

/* numlock key pressed ? */
/* numlock on 1 */
/* turn numlock off */
/* otherwise, turn numlock on 1 */
/* adjust NumLock LED */

case SCRL:
if(kyb_state t S_SCRL)
kyb_state t= -S_SCRL;
else kyb_state 1= S_SCRL;
kyb_ledO;

/* scrllock key pressed 1 */
/* scrllock on 1 */
/* turn scrllock off */
/* otherwise, turn scrllock on */
/* adjust ScrlLock LED */

Keyboard-Interface Controller - Programming Example

8- 57

break;

/* insert key pressed 1 */
/* set in state byte */

case INS:
kyb_state 1= S_INS;
break;

/* test for combination keys */
/* alt key pressed 1 */

default:
if(kyb_state t S_ALT)
{

/* ctrl key pressed 1 */

if(kyb_state t S_CTRL)
{

if(key == DEL) sys_reset();
/* CTRL/ALT/DEL 1 */
else beep();
/* NOTE: No ALT/CTRL table in demo. */
}

else if(kyb_state t (S_LSHF 1 S_RSHF»

/* shift key pressed 1 */

{

beep();

/* NOTE: No ALT/SHIFT table in demo */

}

else put_key (tkeyboard [key) [T_ALT);

/* use alt table */

}

else if(kyb_state t S_CTRL)

/* ctrl key pressed 1 */

{

if(kyb_state t (S_LSHF 1 S_RSHF»

/* shift key pressed 1 */

{

beepO;

/* NOTE: No CTRL/SHIFT table in demo */

}

else put_key (tkeyboard[key) [.T_CTRL);

/* use ctrl table */

}

else if(kyb_state t (S_LSHF 1 S_RSHF»

/* shift key pressed 1 */

{

if (keyboard [key) [T_A_N) t S_CAPS)

/* alpha character 1 */

if(kyb_state t S_CAPS)
/* caps lock in effect ? */
put_key (tkeyboard [key) [T_NORM);
/* use normal table ? */
else put_key (tkeyboard [key) [T_SHFT);
/* use shift table */

8- 58

Keyboard-Interface Controller - Programming Example

}

else if(keyboard[key][T_A_N] t S_NUM)

/* numeric character? */

{

if(kyb_state t S_NUM)
/* numlock in effect ? */
put_key(tkeyboard[key][T_NORM]):
/ * use normal table */
else put_key (tkeyboard[key] [T_SHFT]):
/* use shift table */
}

else put_key (tkeyboard [key] [T_SHFT]):

/* use shift table */

}

else put_key(tkeyboard[key][T_NORM]):
break:

/* use normal table */

}

eoi(O):

/* end of interrupt to PIC */

}

Keyboard-Interface Controller - Programming Example

8- 59

/****************************************************************~******/

/* kyb_exm() - keyboard example program

/********************************~************************~******~******/

kyb_exmO
{

static MESSAGE mmain[] -

/* opening menu */

{
{ 3, 24, "Keyboard Example" },
{ 6, 24, "Fl. Toggle DIGITAL extended mode on or off" },
{ 6, 24, "F2. Set key click volUl!le" },
{ 7, 24, "F3. Toggle autorepeat on or off" },
{ 8, 24, "F4. Set autorepeat delay and rate" },
{ 9, 24, "FS. Show keyboard version and mode" },
{ 10, 24, "F6. Restore keyboard to defaults" },
{ 11, 24, "F7. Show last depressed find last released keys" },
{ 12, 24, "FlO. Return to Main menu" ~,
{ 0, 0,

o },

};

char line[512];
int ext_mode = 0;
int auto_rep .. 0;
int d;
int x;
int y;
unsigned int intr_flag;
#define ROW 14
#define COL 17
wr_kyb(AREPON);
wr_kyb(EXT_EXM);
wr_kyb(LED4_0N);
line[O] .. 0;
while (1)

/* to hold input line */
/* to hold e~tende~ mode toggle state */
/* to hold auto-repeat toggle state */
/* to hold input */
/* to hold input */
/* to hold input */
/* to hold CPU IF state */
/* where to put input lines */
/* ensure autorepeat is on */
/* exit extended mode */
/* led #4 on */
/* null line */
/* forever until FlO */

{

disp_menu(mmain);
switch (line [0])

/* display menu for keyboard example */
/* which function key ? */

{

case Fl:
if (ext_mode)

/* toggle extended mode */
/* in extended mode ? */

{

wr_kyb(EXT_EXM);
wr_kyb(LED4_0N);
ext_mode .. 0;

/* exit extended mode */
/* led #4 on */
/* clear toggle */

}

8- 60

Keyboard-Interface Controller - Programming Example

else

/* not in extended mode */

{

wr_kyb(ENT_EXM);
wr_kyb(LED4_0F);
ext_mode = 1;

/* enter extended mode */
/* led #4 off */
/* set toggle */

}

break;
case F2:
/* change keyclick volume */
disp_str(ROW, COL,
"The key click volume has a range of 0 to 6 in 4 increments");
disp_str(ROW + 1, COL,
"0 = Off 2 = Low 4 = Medium 6" High");
disp_str(ROW + 7, COL,
"Enter key click volume (0 - 6):");
get_keys(ROW + 7, COL + 36, line);
/* get chioce */
sscanf(line, "%d", ty);
/* ascii to int */
if(y < 0 I I y > 6) y = 4;
/* keep it in bounds */
wr_kyb(SETVOL);
/* write set volume command */
wr_kyb(y);
/* write volume data */
break;
case F3:
if (auto_rep)

/* toggle auto-repeat 1 */
/* auto-repeat off 1 */

{

wr_kyb(AREPON);
auto_rep = 0;

/* autorepeat on */
/* clear toggle */

}

else

/* auto-repeat is on */

{

wr_kyb(AREPOFF);
auto_rep = 1;

1* autorepeat off */
/* set toggle */

}

break;
case F4:
/* set auto-repeat rate 1 */
disp_str(ROW, COL,
"The autorepeat rate has a range of 2 to 30 in 32 increments");
disp_str(ROW + 1, COL,
"The autorepeat rate is calculated as follows:");
disp_str(ROW + 2, COL,
"Rate = 1 / (.00417 * (2~Y) * (X + 8)");
disp_str(ROW + 3, COL,
"The delay, before autorepeat begins, has a range of");
disp_str(ROW + 4, COL,
".25 seconds to 1 second in .25 second increments");
disp_str(ROW + 6, COL,

Keyboard-Interface Controller - Programming Example

8- 61

"The delay, before autorepeat begins, is calculated as follows:"):
disp_str(ROW + 6, COL, "delay - (D + 1) * .26"):
disp_str(ROW + 7, COL,
"Enter repeat rate Y value (0 - 3):"):
disp_str(ROW + 8, COL,
"Enter repeat rate X value (0 - 7): "):
disp_str(ROW + 9, COL,
"Enter delay value D (0 - 3):"):
get_keys(ROW + 7, COL + 36, line):
/* get input */
sscanf(line, "%d" , ty):
/* ascii to int */
if(y < 0 I I y > 3) y = 2:
/* keep in bounds */
get_keys(ROW + 8, COL + 36, line):
/* get input */
sscanf (line, "%d", tx):
/* ascii to int */
if(x < 0 I I x > 3) x = 2:
/* keep in bounds */
get_keys(ROW + 9, COL + 30, line):
/* get input */
sscanf(line, "%d" , td):
/* ascii to int */
if(d < 0 I I d > 3) d = 2:
/* keep in bounds */
y «= 3:
/* shift into correct position */
d «= 6;
/* shift into correct position */
wr_kyb(SETAR):
/* write set auto-repeat rate command */
wr_kyb(d I y I x):
/* write auto-repeat data */
break;
case F6:
/* read keyboard ID and state */
intr_flag = int_off();
/* CPU interrupts off */
pass_thru(TRUE); /* interface controller in pass-through mode */
wr_kcd(KYBID);
/* write keyboard ID command */
while(l(inp(COMMAND) t OxOl»
/* wait until data available */
y = inp(DATAREG):
while(l(inp(COMMAND) t OxOl»

/* read version byte */
/* wait until data available */

x = inp(DATAREG);
/* read mode byte */
pass_thru(FALSE);
/* interface controller interprets */
int_on(intr_flag);
/* CPU interrupts on */
if(x == 2)
/* DIGITAL extended mode ? */
sprintf (line,
"Keyboard version #%d is in DIGITAL extended mode %d", y, x);
else
/* industry-standard mode */
sprintf(line,
"Keyboard version #%d is in industry-standard mode %d", y, x);
disp_str(ROW, COL, line);
/* display data */
break:
case F6:
wr_kyb(RESDEF);
break;

8- 62

/* reset keyboard to default values ? */
/* write reset to default command */

Keyboard-Interface Controller - Programming Example

case F7:
/* show last pressed and last released keys 1 */
line[O] = 0;
/* null line */
disp_str(ROW, 0, "Press F7 again to cancel");
while (line [0] 1= 0 I I line[l] 1= F7)
/* F7 terminates */
{

sprintf (line, "Last depressed: ~02x", depressed);
disp_str(ROW + 3, 0, line);
sprintf(line, "Last released: ~02x", released);
disp_str(ROW + 3, 40, line);
chk_dt();
/* display date and time 1 */
if(get_key(lline[O]» /* scan code */
while(lget_key(lline[l]» /* character code */
}

break;
case FlO:
return;
}

line[O] = get_fkey();

/* get menu selection */

}
}

Keyboard-Interface Controller - Programming Example

8- 63

Chapter 9
Serial Communications
Overview
The 8250A universal asynchronous receiver/transmitters (UART) in the
VAXmate workstation provide asynchronous communications for the communications port, the printer port, and the modem port.
The 8250A UART converts parallel data from the internal buses to serial data
for transmission to external devices. The 8250A UART receives serial data and
converts it to parallel data for the internal buses. The serial data has the
format of a start bit; five to eight data bits; an optional parity bit; and 1, 1-1/2,
or 2 stop bits.
The 8250A UART also has a programmable baud rate generator.

Additional Sources of Information
The following documents provide additional information on programming the
8250A UART serial communications devices.
•

Series 8000 Microprocessor Family Handbook (National Semiconductor
Corporation)

•

1984 Data Communications Products Handbook (Western Digital
Corporation)

Serial Communications - Hardware Description

9- 1

8250A UART Registers
Table 9-1 lists the 8250A UART registers and their registers at each port.
Table 9-1

8250A UART Register Addresses

Com!

Modem
(Com2)

Printer

Receive buffer (Read)lTransmit
holding register (Write) or
Divisor latch (LSB) *

03F8H

02F8H

OCAOH

Interrupt enable
or Divisor latch (MSB) *

03F9H

02F9H

OCA1H

Interrupt identification

03FAH

02FAH

OCA2H

Line control

03FBH

02FBH

OCA3H

Modem control

03FCH

02FCH

OCA4H

Line status

03FDH

02FDH

OCA5H

Modem status

03FEH

02FEH

OCA6H

9- 2

Bit 7 of the line control register controls access to the divisor latches.
The line control register is described later in this chapter.

Serial Communications - Hardware Description

Receive Buffer Register/Transmitter Holding Register
(03F8H/02F8H/OCAOH)
6

I : : :

Bit

RIW Description

7-0

Reading this register accesses the receive buffer.

Writing this register accesses the transmitter holding register.

Bit 0 (the least significant bit) is the first bit transmitted or
received.
When the line control register is programmed for word lengths of
less than 8 bits, the unused bits are read as zeros.
When bit 7 of the line control register is set to 1, reading or writing this register accesses the least significant byte of the divisor
latch.

Serial Communications - Hardware Description

9- 3

Interrupt Enable Register (03F9H/02F9H/OCAIH)
7

MODEM
STATUS
INTRFl'

RECEIVE TBRE
LINE
IRTRPT

RECEIVE

STATUS

DATA
AVAIL

IRTRPT

INTRPT

Bit

RIW Description

7-4

RJW Always 0

RJW MODEM STATUS INTRPT - Modem Status Interrupt
0= Modem status interrupt disabled
1 = Modem status interrupt enabled

RJW RECEIVE LINE STATUS INTRPT - Receive Line Status
Interrupt
0= Receive line status interrupt disabled
1 = Receive line status interrupt enabled

RJW THRE INTRPT - Transmit Holding Register Empty Interrupt
0= Transmit holding register empty interrupt disabled
1 = Transmit holding register empty interrupt enabled

RJW RECEIVE DATA AVAIL INTRPT - Receive Data Available
Interrupt
0= Receive data available interrupt disabled
1 = Receive data available interrupt enabled

Writing all Os to this register disables the 8250A UART interrupt structure. If
any of bits 3-0 are set, the 8250A UART interrupt structure is enabled. Only
the functions with set bits can cause an interrupt.
Because the 8250A UART has only one interrupt output line, you must read
the interrupt identification register to determine which function or functions
caused the interrupt. Later in this chapter, the interrupt identification register
description defines the interrupt conditions for each function.

NOTE
Each 8250A UART has a buffer between the interrupt output
line and the peripheral interrupt controller input. This buffer is
controlled by bit 3 of the modem control register. Writing a 1 to
bit 3 of the modem control register enables the buffer and therefore, the 8250A UART interrupt output line. The modem control
9- 4

Serial Communications - Hardware Description

register is described later in this chapter.
To use the 8250A UART in an interrupt-driven environment you
must program the peripheral interrupt controller. For more information on the peripheral interrupt controller, see Chapter 3.

Serial Communications - Hardware Description

9 - I)

Interrupt Identification Register (03F AH/02FAH/OCA2H)
5

I I I I I II~~~I~I
0

Bit

RIW Description

7-3

Always 0

2-1

INTERRUPT IDENTIFICATION
These two bits identify the highest priority interrupt pending.
Table 9-2 defines the meaning of the interrupt identification bits.

INTRPT PENDING - Interrupt Pending

o = One or more interrupts pending
1 =

No interrupts pending

Table 9-2

Interrupt Identification

Priority
Level

Interrupt
ID Bits
21

Interrupt
Enable
Register
Bit

Interrupt
Condition

Highest

1 1

Receiver line
status

Overrun, parity Reading the line
error, framing
status register
error, or break
interrupt

Second

1 0

Receive data
available

Assembling a
complete word
in the receive
buffer

Reading the receive buffer
register

Third

Transmit holding register
empty

Writing the
transmit holding
register

Fourth

Modem status

Change in state Reading the
of CTS, DSR,
modem status
RI, or RLSD
register
signals

9- 6

Serial Communications - Hardware Description

Interrupt
Reset

Line Control Register (03FBH/02FBH/OCA3H)
7

1
I

DLAB

BREAK STICK PARITY PARITY STOP
CONTROL PARITY SELECT ENABLE BITS

VORD LENGTH
I

Bit

RIW Description

RIW DLAB - Divisor latch access bit
0=
1 =

Access to the divisor latch is disabled
Access to the divisor latch is enabled

When access to the divisor latch is enabled, the least significant
byte of the divisor latch is read or written through the receive
buffer/transmit holding register, and the most significant byte of
the divisor latch is read or written through the interrupt enable
register.
The divisor latch is described later in this chapter.
6

RlW BREAK CONTROL
0= Break disabled
1 = A space Uogic 01 state forced on the serial output

RIW STICK PARITY

0= Stick parity disabled
1 = If parity is enabled (bit 3 equals 11, stick parity is enabled
When stick parity is enabled, the parity bit is transmitted and
received in the following manner:

• If bit 4 equals 1, the parity bit is always transmitted and
received as a O.

• If bit 4 equals 0, the parity bit is always transmitted and
received as a 1.

RlW PARITY SELECT
0= Even parity (except for stick parity as described in bit 51
1 = Odd parity (except for stick parity as described in bit 51

Serial Communications - Hardware Description

9- 7

Bit

RIW Description (Line Control Register - cont.)

R/W PARITY ENABLE
o = Parity disabled

1 =

Parity enabled

R/W STOP BITS

o = 1 stop bit
1=

1-112 stop bits (5-bit word length)
2 stop bits (6, 7, or 8-bit word length)
This bit sets the number of stop bits only for transmitted
characters. The receiver uses only the first stop bit detected.

1-0

9- 8

R/W WORD LENGTH

00 = 5 data bits
01 = 6 data bits
10 = 7 data bits
11 =
8 data bits
When reading the receive buffer, unused bits are read as O.

Serial Communications - Hardware Description

Modem Control Register (03FCH/02FCH/OCA4H)
7

I I I I I I I I I
0

Bit

R/W Description

7-5

R/W Always 0

R/W LOOP

R/W OUT2

LOOP

Our2

ourl

RTS

DTR

o = Diagnostic loopback disabled
1 = Diagnostic loopback enabled tsee the discussion that follows}
o = The buffer between the 8250A UART interrupt output and
the peripheral interrupt controller input is disabled.
1 = The buffer between the 8250A UART interrupt output and

the peripheral interrupt controller input is enabled.
Each 8250A UART has a buffer between the interrupt output line
and the peripheral interrupt controller input. This buffer is controlled by bit 3. Enabling the buffer enables the 8250A UART interrupt output line.

To use the 8250A UART in an interrupt-driven environment you
must program the peripheral interrupt controller. For more information on the peripheral interrupt controller, see Chapter 3.
2

R/W OUTI tnot connected to anything}

R/W RTS - Request to send
o = RTS is a logic 0 at the external connector
1 = RTS is a logic 1 at the external connector

R/W DTR - Data terminal ready
o = DTR is a logic 0 at the external connector
1 = DTR is a logic 1 at the external connector

NOTE
See the section "Modem Control Programming Exceptions" in
this chapter.

Serial Communications - Hardware Description

9- 9

Diagnostic Loopback
When the diagnostic loopback is enabled, the following conditions exist:
•

The serial output at the external connector is set to a space (logic 0)
state.

•

The serial input is internally disconnected.

•

The output of the transmit shift register is internally connected to the
input of the receive shift register.
The four modem inputs (DSR, CTS, RI, and RLSD) are internally
disconnected. The four modem outputs (DTR, RTS, OUT1, and OUT2)
are connected to the four modem inputs as follows:
The DTR output is connected to DSR input
The RTS output is connected to the CTS input
The OUT1 output is connected to the RI input
The OUT2 output is connected to the RLSD input

•

When the diagnostic loopback is enabled, the receive and transmit interrupts
continue to function normally. The modem control and the line status interrupts are also functional, but the source of the interrupt is changed as follows:
•

The line status interrupt is activated by writing an appropriate value to
one of the line status register bits 5-0. A set bit creates the interrupt
condition.

•

The modem status interrupt is activated by writing an appropriate value
to one of the modem status register bits 3-0. A set bit creates the interrupt condition.

9 - 10

Serial Communications - Hardware Description

Line Status Register (03FDH/02FDH/OCA5H)
7

XHIT
SHIFT
REG
EMPTY

XHIT
BREAK
FRAMING PARITY OVERRUN RECEIVE
HOLDING INTRPT ERROR ERROR ERROR DATA
READY
REG
EMPTY

Bit

RIW Description

Always 0
XMIT SHIFT REG EMPTY· Transmit Shift Register Empty

o = Transmit shift register contains data being transmitted
1 =

Transmit shift register is empty

This bit is cleared by writing data to the transmit holding register.
5

XMIT HOLDING REG EMPTY· Transmit Holding Register
Empty
o = Transmit holding register is full.
1 = The 8250A UART is ready to accept a character for
transmission. If the transmit holding register interrupt
enable bit (interrupt enable register I is set, this condition
creates an interrupt.
This bit is cleared by writing data to the transmit holding register.

R/W BREAK INTRPT . Break Interrupt
o = Break interrupt is not active
1 = The serial input line at the connector has been held in a
mark Hogic 11 state for longer than a full character
transmission, including start and stop bits.

This bit is cleared by reading this register or writing the bit.
3

R/W FRAMING ERROR
o = No framing error
1 = The received character did not have a stop bit.

This bit is cleared by reading this register or writing the bit.

Serial Communications . Hardware Description

9- 11

Bit

R/W Description (Line Status Register - cont.)

RJW PARITY ERROR
o = No parity error
1 = Received character did not have the correct parity.

This bit is cleared by reading this register or writing the bit.

R/W OVERRUN ERROR

o=
1 =

No overrun error
The CPU did not read the data in the Receive Buffer register before the next character was received. Thus. the unread
character was destroyed.

This bit is cleared by reading this register or writing the bit.

R/W RECEIVE DATA READY
o = Receive data buffer is empty.
1 = A complete character has been received and assembled into
the receive Buffer register.
This bit is cleared by reading this register or writing the bit.

When any of bits 4-1 are set, a receiver line status interrupt is generated.
When bit 0 is set. a receive data available interrupt is generated.

9- 12

Serial Communications - Hardware Description

Modem Status Register (03FEH/02FEH/OCA6H)
7

RLSD

DSR

CTS

Bit

RfW Description

TRAIL
DELTA EDGE OF DELTA
RLSD
RI
DSR

DELTA
CTS

RLSD - Received line signal detect
RLSD at external connector is a logic 0
1 = RLSD at external connector is a logic 1
RI - Ring indicator
o = RI at the external connector is a logic 0
1 =RI at the external connector is a logic 1

DSR - Data set ready
DSR at the external connector is a logic 0
1 = DSR at the external connector is a logic 1

CTS - Clear to send

o = CTS at the external connector is a logic 0
1 =

CTS at the external connector is a logic 1

DELTA RLSD - Delta Receive Line Signal Detect
RLSD has not changed state.
1 = Since the last time this register was read, the RLSD bit has
changed state.

Reading this register clears the bit.
2

TRAIL EDGE OF RI - Trailing Edge Of Ring Indicator

o = The ring indicator has not changed state.
1 =

Since the last time this register was read, the ring indicator
at the external connector changed from a logic 0 to a logic 1.

Reading this register clears the bit.

Serial Communications - Hardware Description

9-13

Bit

RIW Description {Modem Status Register - cont_)

Delta DSR - Delta Data Set Ready

o = DSR has not changed state. Reading the register clears the
bit.
Since the last time this register was read, the DSR signal
has changed state.
Reading this register clears the bit.

1 =

Delta CTS - Delta Clear to Send
CTS has not changed state.
1 = Since the last time this register was read, the CTS signal
has changed state.
Reading this register clears the bit.

If any of bits 3-0 in the Modem Status register are set, a modem status inter-

rupt is generated.
Bits 7-4 are the complement of the signal levels at the chip input pins.
However, the RS-232 receiver buffer inverts these signals, so the bits reflect
the true state of the lines at the external connector.

9- 14

Serial Communications - Hardware Description

Divisor Latches

:
15

:
14

~DIVISOR~LATCB ~
12

LEAST SIGNIFICANT BYTE

:
10

~DIVISOR~LATCBBYTE~

HOS~ SIGNIF~CANT

:
8

When bit 7 of the line control register (Divisor latch access bit) is equal to 1,
the least significant byte of the divisor latch is read or written through the
receive buffer/transmit holding register, and the most significant byte of the
divisor latch is read or written through the interrupt enable register.
These two, 8-bit latches store a 16-bit divisor in the range 1 to 65,535. The
output frequency of the baud rate generator is 1.8432 Mhz divided by the 16bit divisor. These divisors must be loaded during initialization. The desired
output frequency is 16 times the desired baud rate. Table 9-3 lists the divisor
used for the standard baud rates. Table 9-3 was calculated using the following
formula:
divisor = (1843200 / 16) / desired_baudJate

Serial Communications - Hardware Description

9- 15

Baud Rate Table

Table 9·3
Baud Rate

Divisor

2304

1536

110

1047

- 0.026

134.5

857

+0.058

150

768

200

576

300

384

600

192

1200

1800

2000

2400

3600
4800

7200

9600

19200

38400

9 - 16

Percentage of Error Between Desired
and Actual Rate

+0.69

Serial Communications . Hardware Description

Modem Control Programming Exceptions
Speed Select and Speed Indicator control signals are not controlled by the
8250A UART. Instead, these signals are controlled by writing to a special purpose register.
The special purpose register is located at 1/0 address OC80H.
NOTE
When changing the Speed Select or Split Baud Rate, maintain
the integrity of the other bits in this register. Split baud rates
are achieved by switching the output IRCLK Ht between two
sources, BD OUT CLK (baud out of the 8250A UARTt and a
1200 baud counter.

Serial Communications - Hardware Description

9 - 17

Special Purpose Register (OCBOH)
2

DISABLE SPLIT
VIDEO BAUD

COMM

76543

VRITE

PROTECT

TRACK 0 INDEX

Bit

RIW Description

SPEED

DISABLE SPEED
SELECT

Write protect
0= Selected diskette drive is not write protected
1 = Selected diskette drive is write protected
Track 0
R
0= Head of selected diskette drive is not at track 0
1 = Head of selected diskette drive is at track 0
Index
R
0= Index hole not in position for selected diskette drive
1 = Index hole in position for selected diskette drive
Speed Indicator
R
0= Modem control speed select asserted
1 = Modem control speed select not asserted
R/W Disable Video
0= Video controller disabled
1 = Video controller enabled

RIW Split Baud Rates
0= (Receive = Transmit = programmedI
1 = (Receive = 12001 (Transmit = programmedI

R/W Disable Communications
0= Integral communications ports connected to 1/0 address
space
1= Integral communications ports disconnected from 1/0 address
space

R/W Speed Select
0= Speed select asserted
1 = Speed select not asserted

9- 18

Serial Communications - Hardware Description

Communications Connector Signals
The communications connector, a 25-pin, male, D-subminiature, is located on
the rear bezel of the VAXmate workstation. This connector is functionally
compatible with RS-232-C and electrically compatible with RS-423, configured
as DTE (Data Terminal Equipment). Table 9-4 lists the signals supported by
this connector.
Table 9-4

Communications Connector Signals

Signal Name

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Protective ground
Transmitted Data
Received Data
Request to Send
Clear to Send
Data Set Ready
Signal ground
Receive Line Signal Detect
Not used
Speed Indicator

17
18
19
20
21
22
23
24
25

Data Terminal Ready
Ring Indicator
Speed Select

Serial Communications - Hardware Description

9- 19

Printer Connector Signals
The printer connector is a 6-pin MMJ, female, modified modular connector
located on the rear bezel of the VAXmate workstation. Table 9-5 lists the signals this connector supports.
Table 9·5

Printer Connector Signals

Signal Name

Data Terminal Ready

Transmit Data

Transmit Common (Signal ground)

Receive Common (Signal ground)

Receive Data

Data Set Ready

9 - 20

Serial Communications . Hardware Description

Modem Connector Signals
The modem connectors are modular TELCO (telephone line) compatible connectors located on the optionai modem board, protruding through the rear panel of
the VAXmate workstation. The connectors use an 8-pin, keyed modular housing
for an RCl1C jack (or CAl1 jack in Canada). Table 9-6 lists the signals for a
modem connector. Table 9-7 lists the signals for a handset connector.
Table 9-6

Modem Telephone Line Connector Signals

Pin No.

Signal Name

Meaning

1
2

N.C.
N.C.
MIC
TIP
RING
MI
N.C.
N.C.

No connection
No connection
Not used
TELCO signal source
TELCO signal return
Not used
No connection
No connection

3
4
5
6
7
8

Table 9-7

Handset Connector Signals

Pin No.

Signal Name

Meaning

1
2

N.C.
N.C.
MIC
RING
TIP
MI
N.C.
N.C.

No connection
No connection
Not used
TELCO signal return
TELCO signal source
Not used
No connection
No connection

3
4

5
6
7
8

Serial Communications - Hardware Description

9- 21

Programming Example
The examples in this chapter demonstrate:
•
•
•

Initializing an 8250A UARTA serial communications device
Handling interrupt-ciriven serial 1/0
Handling hardware and software handshaking protocols

The example provides routines as described in the following list:
device init
device_open
ser out
restart
device int
device close
put_buf
puts_buf

Establishes a known state for a serial port
Activates the serial port and interrupts
Handles character transmissions
Activates interrupt-driven serial transmissions
Coordinates all of the device interrupts
Deactivates the serial port and interrupts

get_buf

Puts a character into a ring buffer from the application
Puts a string of characters into a ring buffer from the
application
Gets a character from a ring buffer for the application

The serial example

int com!

An interrupt vector entry point for the com! serial port
interrupt handler
An interrupt vector entry point for the modem serial port
interrupt handler
An interrupt vector entry point for the serial printer port
interrupt handler

int modm

9- 22

Serial Communications - Programming Example

Program Description
Constant Value

Description

P _ENAB through WORD5

Define the line control register bit values.

RDRDY through BREAK

Define the line status register bit values.

ENA MOD through
ENA-THE

Define the interrupt enable register bit values.

DTR through LOOP

Define the modem control register bit values.

RLSD through CTS

Define the modem status register bit values.

HHS through DEV_OFF

Define the bit values used to maintain the driver
status. The driver status is part of the structure
type DEV_ DAT.

CLK RATE

Is divided by the desired baud rate to give the
value for the baud rate divisor registers.
Clarify the logic of the function, device_init.

Serial Communications - Programming Example

9- 23

#include "kyb.h"
#include "rb.h"
#include "example.h"

/***********************************************************************/
/* define constant values used in example serial driver

/***********************************************************************/
/ * def ine line control register bit values */
#define P_ENAB
#define P_EVEN
#define P_ODD
#define P_STIK
#define WORD8
#define WORD7
#define WORDti
#define WORD5

/* parity enabled */
/* EVEN parity select */
/* ODD parity select */
/* enable stick parity */
/* 8-bit word size */
/* 7-bit word size */
/* 6-bit word size */
/* 5-bit \10rd size */

Ox08
Oxl0
OxOO
Ox20
Ox03
Ox02
OxOl
OxOO

/ * define line status register bit values */
#define RDRDY
#define THRE
#define ERRORS
#define BREAK

OxOl
Ox20
OxOe
Oxl0

/* received data ready */
/* transmit holding reg empty */
/* overrun, parity, framing */
/* received break */

/* define interrupt enable register bit values */
#define ENA_MOD Ox08
#define ENA_REC Ox05
#define ENA_THE Ox02

9- 24

/* enable modem status */
recv
line stat & rd rdy */
/*
enable
trans hold empty */
/*

Serial Communications . Programming Example

/* define modem control register bit values */
#define DTR
#define RTS
#define OUT2
#define LOOP

Ox01
Ox02
Ox08
Oxl0

/* data terminal ready */
/* request to send */
/* out 2 interrupt ctrl */
/* loopback mode */

/* define modem status register bit values */
#define RLSD
#define RI
#define DSR
#define CTS

Ox80
Ox40
Ox20
Ox10

/* recv line signal detect */
/* ring indicator */
/* data set ready */
/* clear to send */

/* define driver status bit values */
#define HHS
Ox80
#define F_XOFF Ox40
#define F_XON
Ox20
#define DEV_CLS OxtO
#define SWAIT
Ox04
#define DEV_OFF Ox01

/* use hardware handshake */
/* x-off pending flag */
/* x-on pending flag */
/* device close request */
/* sending stopped */
/* driver off line */

/* define some general constants */
#define CLK_RATE 116200L
#define X_OFF
Ox13
#define X_ON
Ox11

/* 1843200 / 16 - 116200 */
/* x-off (DC3) character */
/* x-on (DC1) character */

/* program constants used to initialize the line control register */
'define NO_PAR
#define EV_PAR
#define OD_PAR
#define SC_PAR
#define SS_PAR
#define S_BIT2

0
1
2
3
4
Ox04

/* no parity */
/* even parity */
/* odd parity */
/* stick parity clear */
/* stick parity set */
/* 2 stop bits */

Serial Communications - Programming Example

9- 25

The structure type SERIAL declares the relationship of the 8250A UART registers in 1/0 space. The registers accessed by the members rtbl and iebh
depends on the following:
•

If bit 7 of the line control register is set, rtbl accesses the low byte
of the baud rate divisor and iebh accesses the high byte of the baud
rate divisor.

•

If bit 7 of the line control register is clear, rtbl accesses the receive

register when reading and the transmit register when writing, and
iebh accesses interrupt enable register.
The structure type DEV DAT stores the characteristics of the individual devices, the current status;-and the pointers to the buffers.
/***********************************************************************/
/* define structures used in example serial driver
*/
/***********************************************************************/
typedef struct
{

unsigned char rtbl;
unsigned char iebh;
unsigned char int_ident;
unsigned char line_ctrl;
unsigned char modem_ctrl;
unsigned char line_stat;
unsigned char modem_stat;
} SERIAL;

/* receive/transmit/baud low */
/* int enable reg/baud high */
/* int identification reg */
/* line control register */
/* modem control register */
/* line status register */
/* modem status register */

typedef struct dev_dat
{

SERIAL
*base;
unsigned int pic;
unsigned int ir_bit;
unsigned int baud;
unsigned int word_siz;
unsigned int parity;
unsigned int stop_bits;
unsigned int req_dsr;
RING_BUFF
*prbi;
RING_BUFF
*prbo;
unsigned char stat_drv;
} DEV_DAT;

/* base i/o address of device */
/* PIC number it belongs to */
/* IR bit in PIC */
/* desired baud rate */
/* desired word size */
/* even, odd, none, stick */
/* I, 1 - 1/2, 2 */
/* DSR required flag */
/* ptr to input ring buff */
/* ptr to output ring buff */
/* state of driver */

void int_onO;
int int_offO;

9- 26

Serial Communications - Programming Example

The function device init establishes a known state for the 8250A UARTA
serial device. Two items of interest are stick parity and stop bits. If stick
parity is selected, the parity bit is set to the opposite state of the even/odd
parity bit. If more than one stop bit is selected, the number of stop bits
depends on the word size. If the word size is five data bits, there are 1 1/2 stop
bits. All other word sizes generate 2 stop bits. These characteristics are a function of the device, not the code.
/***********************************************************************/
/* device_init() - establish a known state for a serial port
*/
/***********************************************************************/
void device_init(pdd)

/* pointer to device data */

initialize serial port */

{

unsigned int tbaud;
unsigned char tpar;
register SERIAL *ps;

/* temp to hold results */
/* temp to collect results */
/* pointer to SERIAL struct */

tbaud = CLK_RATE / pdd->baud;
switch(pdd->parity)

/* calculate baud rate divisor */

{

case
NO_PAR:
tpar
NO_PAR;
break;

/* no parity */

case
EV_PAR:
tpar
P_ENAB I P_EVEN;
break;

/* even parity */

case
OD_PAR:
tpar
P_ENAB I P_ODD;
break;

/* odd parity */

case
SC_PAR:
tpar
P_ENAB I P_STIK I P_EVEN;
break;

/* stick, parity bit clear */

case
SS_PAR:
tpar
P_ENAB I P_STIK I P_ODD;
break;

/* stick, parity bit set */

}

switch (pdd->word_siz)

/* desired word size ? */

Serial Communications - Programming Example

9- 27

{

case 8:
tpar 1- WORD8;
break;

/* 8 data bits 1 */

case 7:
tpar 1- WORD7;
break;

/* 7 data bits 1 */

case 6:
tpar 1- WORD6;
break:

/* 6 data bits */

case 6:
tpar 1= WORD6;
break;

/* 6 data bits 1 */

}

if(pdd->stop_bits) tpar 1- 8_BIT2;
ps - pdd->base;
outp(ips->iebh. 0);
outp(ips->modem_ctr1, LOOP);
outp(ips->line_ctr1, Ox80);
outp(ips->rtb1, tbaud);
outp(ips->iebh, tbaud » 8):
outp(ips->line_ctr1, tpar);
pdd->stat_drv 1= DEV_OFF;

/* set stop bits */
/* get shorter pointer */
/* interrupts off */
/* put in 100pback mode */
/* access baud rate divisor */
/* baud rate divisor 10 byte */
/* baud rate divisor hi byte */
/* bits per char, parity */
/* transmit int off */

}

9- 28

Serial Communications· Programming Example

The function device open prepares the driver to handle interrupts and the
device to receive characters. Because the modem interrupt has the lowest priority, it is enabled only for hardware handshaking. In that instance, it notifies
the driver to restart character transmissions.
Setting the modem control register bit OUT2 connects the 8250A UARTA interrupt output to the 8259A interrupt input. This bit must be set to operate a
serial device in an interrupt-driven environment.
/***********************************************************************/
/* device_open() - activate serial port and interrupts
*/
/***********************************************************************/
void device_open(pdd)

/* open a device */

/* pointer to device data */

{

/* pointer to SERIAL struct */

ps = pdd->base;
inp(leps->rtb1);
inp(leps->line_stat);
if(pdd->stat_drv Ie HHS)
{

if«inp(leps->modem_stat) Ie (DSR
CTS»
pdd->stat_drv Ie= -SWAIT;
else pdd->stat_drv 1= SWAIT;
outp(lcps->iebb, ENA_REC 1 ENA_MOD);

/* get sborter pointer */
/* empty receive data buffer */
/* clear status flags */
/* if hardware handshake */

-= (DSR 1 CTS»

/* mark as ok */
/* mark as not ok */
/* receive, line Ie modem */

}

else outp(leps->iebh, ENA_REC);
pdd->stat_drv Ie= -DEV_OFF;
imask(pdd->pic, pdd->ir_bit, ON);
outp(leps->modem_ctr1, DTRIRTSIOUT2);

/* just receive and line */
/* driver state - online */
/* c1r the interrupt mask */
/* set modem control bits */

}

Serial Communications . Programming Example

9- 29

The function ser out provides a single location for maintaining or restarting
interrupt-driven transmissions. It also provides a method for software handshake characters to preempt normal data transmissions. To prevent continuous
interrupts, when the output buffer is empty, the transmit interrupt is disabled.
/***********************************************************************/
/* ser_out() - transmit interrupt startup and maintenance
*/
/***********************************************************************/

/* pointer to device data */

{

1* pointer to SERIAL struct */

/* character to transmit */

void device_close();
ps = pdd->base;
if(inp(ips->line_stat) , Ox20 "
(inp(ips->modem_stat) , DSR I I
Ipdd->req_dsr»

/* get shorter pointer */
/* if terminal ready */
/* or dsr not required */

{

if(pdd->stat_drv , F_XOFF)
{

pdd->stat_drv
c = X_OFF;
flag = 1;

,= -F_XOFF;

/* pending x-off request ? */
/* clear pending flag */
/* send x-off */

}

else if(pdd->stat_drv , F_XON)
{

pdd->stat_drv
c = X_ON;
flag = 1;

,= -F_XON;

/* pending x-on request ? */
/* clear pending flag */
/* send x-on */

}

else if(l(pdd->stat_drv , SWAIT»

/* terminal ready */

{

flag = rb_out(pdd->prbo, 'c);
if(flag > -1) flag = 1;
else

1* request character to send */
/* character to send ? */

{

flag = 0;
if(pdd->stat_drv , DEV_CLS)

9- 30

Serial Communications - Programming Example

{

device_close(pdd);
return;
}

}
}

else flag = 0;
}

else flag = 0;
i f (flag)
{

/* enable transmit int */
outp(lps->iebh, inp(lps->iebh) I ENA_THE);
outp(lps->rtbl, c) ;

/* output character */

}

else
/* disable transmit int */
outp(lps->iebh, inp(lps->iebh) l -ENA_THE);
}

Serial Communications . Programming Example

9- 31

The function restart tests the interrupt enable register to. determine if interrupts are currently enabled. If they are not, it calls ser out to restart interruptdriven transmissions.
/***********************************************************************/
/* restart - attempt to restart i~terrupt-driven serial transmissions */
/***********************************************************************/
void restart(pdd)

/* restart serial output */

/* pointer to device data */

{

int flag:

/* temporary */

if(!(inp(lpdd->base->iebh) lENA_THE»

/* need to restart ? */

{

flag = int_off():
ser_out(pdd):
int_on(flag):

/* CPU interrupts off */
/* restart */
/* allow interrupts */

}
}

9- 32

Serial Communications - Programming Example

The functions comI int, modem int, and printer int are interrupt handlers for
the serial devices. These interrupt handlers call common interrupt handler,
device into

/***********************************************************************/
/* coml_int() - interrupt handler for coml serial device

/***********************************************************************/

void com Lint 0
{

extern DEV_DAT devdat[];
void device_int();
device_int(ldevdat[O]);

/* call common interrupt handler */

}

/***********************************************************************/
/* modem_int() - interrupt handler for modem serial device

1***************************************************** ******************/
void modem_int 0
{

extern DEV_DAT devdat[];
void device_int();
device_int(ldevdat[l]);

/* call common interrupt handler */

}

/***********************************************************************/
/* printer_int() - interrupt handler for printer serial device

/***********************************************************************/
void printer_int()
{

extern DEV_DAT devdat[];
void device_int();
device_int(ldevdat[3]);

/* call common interrupt handler */

}

Serial Communications· Programming Example

9- 33

The function device int is the major function within the device driver. It
coordinates interrupt processing, handshake protocol, and peripheral interrupt
controllers. For any given serial device, this function processes all pending interrupts during a single CPU interrupt. This reduces the CPU interrupt processing overhead.
Device communication errors are noted by placing a question mark in the input
s.tream.
The switch values are tested against the contents of the interrupt identification
register.

/***********************************************************************/
/* device_int() - interrupt handler for serial device

/***********************************************************************/
void device_int(pdd)

/* interrupt handler */

/* pointer to device data */

{

/* pointer to SERIAL struct */
/* register value read */

inp(&ps->int_ident»

& 1»

/* get shorter pointer */
/* while int pend */

{

switch (r_val)

/* discover which interrupt */

{

case 6:
inp(&ps->line_stat);
if(inp(&ps->modem_stat) & DSR I I
!pdd->req_dsr)

/* receive error int */
/* clear error */
/* if terminal ready */
/* or dsr not required */

{

rb_in(pdd->prbi, '1');

/* show error */

}

break;

case 4:
r_val = inp(&ps->rtbl);
if(inp(&ps->modem_stat) & DSR I I
!pdd->req_dsr)

/* receive data ready int */
/* read character */
/* if terminal ready */
/* or dsr not required */

{

if«pdd->stat_drv & HHS) == 0)

/* software handshake 1 */

{

switch(r_val & Ox7f)

9- 34

Serial Communications - Programming Example

{

case X_OFF:
pdd->stat_drv 1= SWArT;
break;

/* x-off character ? */

case X_ON:
pdd->stat_drv i= -SWArT;
restart(pdd);
break;

/* x-on character ? */

default:
if(rb_in(pdd->prbi, r_val) < 1)
/* save character */
{
/* if buffer near full */
pdd->stat_drv 1= F_XOFF;
/* stop input */
restart(pdd);
/* restart if needed */
}

break;
}

}

else if(rb_in(pdd->prbi, r_val) < 1)
outp(tps->modem_ctrl, DTR I OUT2);

/* save character */
/* no input please */

}

break;
case 2:
ser_out(pdd);
break;

/* xmit hold reg empty int */
/* transmit character */

case 0:
if(pdd->stat_drv t HHS)
if«inp(tps->modem_stat) t (DSR

/* modem status int */
/* hardware handshake ? */
CTS»
(DSR 1 CTS»

{

if(pdd->stat_drv t SWArT)

/* send stopped ? */

{

pdd->stat_drv t= -SWArT;
restart(pdd);

/* mark as ok */

else pdd->stat_drv 1= SWArT;
break;

/* mark as not ok */

}
}

eoi(pdd->pic);
}

Serial Communications . Programming Example

9- 35

The function device close disables all interrupts related to the device indicated.
It also puts the modem control lines in an off-line state.
/***********************************************************************/
/* device_close() - deactivate serial port interrupts
*/
/***********************************************************************/
void device_close(pdd)

/* close a device */

/* pointer to device data */

{

outp(ipdd->base->modem_ctrl, 0);
outp(ipdd->base->iebh, 0);

/* device offline */
/* 8250A UART interrupts off

*/
imask(pdd->pic, pdd->ir_bit, OFF);
pdd->stat_drv 1= DEV_OFF;

/* mask the interrupt */
/* driver state - offline */

}

9- 36

Serial Communications - Programming Example

The function put but loops until it has stored the indicated character in an
output buffer. After storing the character, it ensures that the transmit interrupt is enabled. The companion function puts but processes a null terminated
string by calling put buf at each character in the string. The null terminator is
not processed.
/***********************************************************************/
/* put_buf() - put character in output buffer
*/
/***********************************************************************/
void put_buf(pdd. c)

/* put char in output buf */

/* pointer to device data */
/* char to put in buffer */

{

int flag;
int r_val;

/* temporary */

for(flag = -1; flag < 0;)

/* wait until success */

{

flag = rb_in(pdd->prbo. c);
restart(pdd);

/* attempt to store */

}
}

/***********************************************************************/
/* puts_buf() - put string in to output buffer
*/
/***********************************************************************/
void puts_buf(pdd. pc)

/* string into output buf

/* pointer to device data */
/* pointer to string */

{

int flag;
while (*pc)
put_buf(pdd. *pc++);

/* while string not done */
/* do another character */

}

Serial Communications - Programming Example

9- 37

The function get but attempts to retrieve a character from the input buffer. If
no characters are available, it returns a -1 value. It also handles the input
handshake protocol.
/***********************************************************************/
/* get_buf() - get character from input buffer
*/
/***********************************************************************/
int get_buf(pdd)

/* get char from input buf */

/* pointer to device data */

{

/* temp to hold character */

char c;
int flag;
flag = rb_out(pdd->prbi, &c);
if(flag < 0) return(flag);
if(flag == 0)
{

if(l(pdd->stat_drv & HHS»

/* get char from input buff */
/* no characters available */
/* room to restart flow 1 */
/* and receive stopped */
/* software handshake 1 */

{

pdd->stat_drv 1= F_XON;
restart(pdd);

/* set x-on flag */

}

else outp(&pdd->base->modem_ctrl, DTRIRTSIOUT2);
}

flag = c;
return(flag & Oxff);

/* return character */

}

/***********************************************************************/
/* reserve storage for variables used in example serial driver
*/
/***********************************************************************/
#define BUF_SIZ 100
/* size of buffers */
#define HIWATER 16
/* buffer near full value */
#define LOWATER 26
/* buffer near empty value */
#define COMl (SERIAL *)Ox03f8
#define MODEM (SERIAL *)Ox02f8
#define PRINTER (SERIAL *)OxOCAO

/* base address of coml */
/* base address of modem */
/* base address of printer */

RING_BUFF rb[6];
char buff [3] [2] [BUF_SIZ] ;
DEV_DAT devdat[3] =

/* ring buff ctrl structs */
/* ring buffers */
/* device data tables */

9- 38

Serial Communications - Programming Example

{

{ COM1,
0, 4, 9600, 8, NO_PAR, 0, 1, lrb[O] , lrb[l] , o },
0, 3, 1200, 8, NO_PAR, 0, 1, lrb[2] , lrb[3] , o },
{ MODEM,
{ PRINTER, 1, 3, 4800, 8, NO_PAR, 0, 0, lrb[4] , lrb[6] , o },
};

Serial Communications - Programming Example

9- 39

The function so drives the examples by transmitting or receiving serial data. It
initializes the devices and data structures, executes the example and then
closes the device.
/***********************************************************************/
/* soO - example application that uses serial driver
*/
/***********************************************************************/
soO
{

atatic MESSAGE mao[] =

/* opening menu */

{
{
{
{
{
{
{
{
{

3, 26, "Serial Communications Example" },
6, 24, "Flo Select the COMI port" },
6, 24, "F2. Select the Modem (COM2) port" },
1, 24, "F3. Select the Printer port" },
8, 24, "F4. Transmit sample data" },
9, 24, "F6. Receive data" },
10, 24, "FlO. Return to Main menu" },
0, 0, o },

};

/* pointer to device data */
/* loop control */
/* loop control */
/* display position */
/* hold state of CPU IF */
/* to hold input line */
/* to hold CPU IF state */

for(i = 0; i < 2; i++)
{

pdd = tdevdat[i];
/* get pointer to data */
init_rb(pdd->prbi, tbuff[i] [0] [0] , BUF_SIZ, HIWATER, LOWATER);
init_rb(pdd->prbo, tbuff[i] [1] [1] , BUF_SIZ, HIWATER, LOWATER);
if(pdd->pic == 0) s = Ox08;
/* base vector for master pic */
else s = Ox10;
/* base vector for slave pic */
intr_flag = int_off();
/* no interrupts allowed */
iv_init(s + pdd->ir_bit);
/* init interrupt vectors */
device_init(pdd);
/* init serial device */
device_open(pdd);
/* activate device */
int_on(intr_flag);
/* allow interrupts */
}

line[O] = 0;
while(l)

/* null line */
/* forever until FlO */

{

9- 40

Serial Communications . Programming Example

disp_menu(mso);
line[O] = get_fkey();
switch (line [0])

/* display menu for serial example */
/* get menu selection */
/* which function key ? */

{

case F1:
pdd = &devdat[O];
break;

/* select com1 port */
/* get pointer to data */

case F2:
pdd = &devdat[1];
break;

/* select modem (COM2) port */
/* get pointer to data */

case F3:
pdd ~ &devdat[2];
break;

/* select printer port */
/* get pointer to data */

case F4:
/* transmit sample text */
disp_str(14 , 0, "Press F4 again to cancel");
i = 0;

while (line [0] != 0 I I line[1] != F4)

/* F4 terminates */

{

sprintf (Uine [0] , "This is line %d\r\n", i++);
puts_buf(pdd, line);
disp_str(16, 0, line);
chk_dt();
/* display date and time? */
if(get_key(&line[O]» /* scan code */
while(!get_key(&line[1]» /* character code */
}

break;
case F6:
/* receive serial data */
disp_str(14, 0, "Press F5 again to cancel");
col = 0;
while (line [0] != 0 I I line[1] != F6)
/* F6 terminates */
{

i = get_buf(pdd);
if(i > -1)
{

i &- Ox7f;
disp_t(16, col++, i, Ox07);
if(i == '\r' I I i == '\n') col = 0;
if(col == 80) col = 0;
}

chk_dt();
/* display date and time? */
if(get_key(&line[O]» /* scan code */
whileClget_key(&line[1]» /* character code */

Serial Communications - ProgrJlmming Example

9- 41

}

break;
case FlO:
for(i
0; i < 3; i++)
{

pdd
&devdat[i];
device_close(pdd);
if(pdd->pic -- 0) s = Ox08;
else s = Ox70;
intr_flag = int_off();
iv_rest(s + pdd->ir_bit);
int_on(intr_flag);

/* get pointer to data */
/* close device when done */
/* base vector for master pic */
/* base vector for slave pic */
/* no interrupts allowed */
/* restore interrupt vectors */
/* allow interrupts */

}

return;
}
}
}

9- 42

Serial Communications - Programming Example

Chapter 10
Mouse Information
Introduction
The VAXmate mouse (part number VSXXX) is a pointing device with three
input switches. The mouse has two encoders, one for the X axis and one for
the Y axis. The encoders have a resolution of 200 counts per inch. When
moved on a flat surface, the mouse monitors the motion relative to its position
at the beginning of the motion. Thus, the mouse maintains positional data in
the form of incremental XlY encoder counts. Figure 10-1 shows the mouse in
relation to its X/Y axes.

-V-axis

-X-axis -+-----+--------1r------ +X-axis

+V-axis

Figure 10·1 VAXmate Mouse (Part Number VSXXX)
Mouse Information - Hardware Description

10 - 1

Communication Requirements
The mouse communicates through an asynchronous serial interface at 4800
baud.
Data bytes have the following format:
•

1 start bit

•

8 data bits (least significant bit first)

•

1 parity bit (the mouse transmits odd parity, but ignores receive parity
errors.)

•

1 stop bit

If a byte is sent to the mouse while the mouse is transmitting, the mouse
aborts the transmission and processes the new command. If the mouse receives

a byte between the characters of a multibyte report, the mouse is considered to
be transmitting and aborts the report.
The VAXmate workstation communicates with the mouse through an
asynchronous serial interface (Signetics SCN2661 Enhanced Programmable
Communications Interface).

Additional Source of Information
The Signetics' document, Microprocessor Data Manual 1986, provides additional information on the SCN2661.

Mouse Commands
The Table 10-1 lists the mouse commands. The commands are issued by
transmitting the appropriate command code.
Table 10·1

Mouse Command Summary

ASCII

HEX

Function

44H
52H
50H
54H
5AH xx

Prompt Mode
Incremental Stream Mode
Request Mouse Position
Invoke Self·test
Vendor Reserved function

10- 2

Mouse Information· Hardware Description

R
P
T

Prompt Mode
Incremental Stream Mode
The mouse has two operating modes, prompt mode and incremental stream
mode. In prompt mode, which is the powerup default, the mouse generates a
report in response to a request mouse position command. In incremental
stream mode, whenever the mouse moves it generates a report of that movement. It also reports a change in button position since the last report. No
report is generated when the mouse is motionless and no buttons have been
changed.

Request Mouse Position
The mouse responds to this command by sending a position report and switching to prompt mode.

Invoke Self·Test
The mouse responds to this command by executing a self-test and then sending
a self-test report. Self-test leaves the mouse in the reset or powerup state.
During the self-test, any data sent to the mouse is ignored until the last byte
of the self-test report has been sent by the mouse. The 4-byte self-test report
consists of a 2-byte identification code and a 2-byte status code.

Vendor Reserved Function
The vendor reserved function is a 2-byte command, the ASCII character 'Z'
followed by any printable character. This command allows vendors to add special mouse functions. Normally, these functions are for quality control. The
manufacturer determines these functions, which may include transmitting specialized reports. These commands may not include new modes. On completion
of a vendor reserved function, the mouse must be restored to its previous state.

Mouse Information - Hardware Description

10 - 3

Mouse Reports
The mouse can transmit two reports, a 3-byte position report and a 4-byte selftest report.

Position Report . Byte 1
7

654

MIDDLE RIGHT
SIGN-X SIGN-Y LEFT
BtrI'TON BtrI'TON BtrI'TON
1

Bit

Description

Always 1

6-5

Always 0

10 - 4

SIGN-X (Sign bit for X-axis displacement)
Negative X-axis displacement
1 = Positive X-axis displacement

SIGN-Y (Sign bit for Y-axis displacement)
Negative Y-axis displacement
Positive Y-axis displacement

o=
1 =

LEFT BUTTON
Switch open
Switch closed

o=
1 =

MIDDLE BUTTON

o = Switch open
1 = Switch closed
RIGHT BUTTON
Switch open
Switch closed

o=
1 =

Mouse Information - Hardware Description

Position Report . Byte 2
765

Bit

Description

Always 0

6-0

X-AXIS DISPLACEMENT

The X-axis displacement is measured in encoder counts 1200 per
inch). The value returned in this byte is the distance moved since
the last report. In prompt mode, if reports are not requested often
enough, this value can overflow. If an overflow occurs, no indication
is given. Bit 0 is the least significant bit.

Position Report . Byte 3
7

654

Bit

Description

7
6-0

Always 0
Y-AXIS DISPLACEMENT

The Y-axis displacement is measured in encoder counts (200 per
inch). The value returned in this byte is the distance moved since
the last report. In prompt mode, if reports are not requested often
enough. this value can overflow. If an overflow occurs, no indication
is given. Bit 0 is the least significant bit.

Mouse Information - Hardware Description

10 - 5

Self-Test Report - Byte 1
7

Bit

Description

7-5

FRAME SYNCHRONIZATION

4-0

These bits are always 101. They provide a means of detecting the
first byte of a self-test report.
REVISION NUMBER
This is a hardware and software revision number for this design
cycle.

Self-Test Report - Byte 2
765

I I ~A~
0

Bit

Description

Always 0

6-4

MANUFACTURERS ID

3-0

DEVICE CODE
Always 0010

10 - 6

Mouse Information - Hardware Description

o~~ CO~

Self-Test Report - Byte 3
6

I I : : ~ORro~
0

Bit

Description

Always 0

6-0

ERROR CODE
OOH = No error
3EH = RAM or ROM checksum error
3DH = Button error

Self-Test Report - Byte 4
6

I I I I I
0

Bit

Description

7-3

Always 0

I~oou
o I~

BtrrTON

LEFT BUTTON
Switch good
1 = Switch closed or failed

MIDDLE BUTTON

o = Switch good
1 = Switch closed or failed
RIGHT BUTTON

o = Switch good
1 = Switch closed or failed

Mouse Information - Hardware Description

10 - 7

Serial Interface
The serial interface is a SIGNETICS SCN2661 Enhanced Programmable
Communications Interface. Table 10-2 lists the input/output UfO) ports that
access the serial interface registers.
Table 10-2 Serial Interface Registers
Address
OC40H

R/W

Receive buffer
Transmit holding register

W
W

Status register
SynllSyn2/DLE registers *

OC42H

R/W

Mode register 1 and mode register 2 * *

OC43H

R/W

Command register

OC41H

The Syn1, Syn2, and DLE registers are not used.

*
**

Mode registers 1 and 2 are accessed at the same 110 address. Read
mode register 1 and then read mode register 2, or write mode register
1 and then write mode register 2. Mode register 1 must be accessed to
access mode register 2.

Transmit Holding Register and Receive Buffer (OC40H)
7

Bit

R/W Description

7-0

R
W

10 - 8

Accesses the receive data buffer
Accesses the transmit holding register

Mouse Information - Hardware Description

Status Register (OC41H)
7

DATA
RxRDY
FRAMING OVERRUN PARITY DATA
CARRIER ERROR
ERROR
SET
DETECT
READY
1
CHANGED

TxRDY

DATA
SET
READY
1

Bit

R/W Description

DATA SET READY falways 1)

DATA CARRIER DETECT falways 1)

FRAMING ERROR
0= Normal
1 = Framing error

This bit is cleared by disabling the receiver, issuing the reset error
command, or reading the status register.
4

OVERRUN

o = Normal
1 =

Overrun error

This bit is cleared by disabling the receiver or issuing the reset
error command.
3

PARITY ERROR
Normal
1 = Parity error (if parity checking is enabled)

This bit is cleared by disabling the receiver, issuing the reset error
command, or receiving another character.
2

DATA SET READY CHANGED falways 0)
RxRDY - Receive Data Ready

o = Receive buffer is empty
1 =

Receive buffer contains data and an interrupt is pending

This bit is cleared by reading the receive buffer or disabling
the receiver fcommand register bit 2).
TxRDY - Transmit Holding Register Ready
o = Transmit holding register busy
1 = Transmit holding register empty and an interrupt is pending
This bit is cleared by writing the transmit holding register or disabling the transmitter fcommand register bit 0).

Mouse Information - Hardware Description

10 - 9

Mode Register 1 (OC42H)
7

STOP BITS

3
I

PARITY
TYPE

PARITY CHARACTER
CONTROL LENGTH

Bit

RIW Description

7-6

R/W STOP BITS
Invalid
00 =
1 stop bit
01 =
1-1/2 stop bits
10 =
11= 2 stop bits

R/W PARITY TYPE
0= Odd parity
1 = Even parity

R/W PARITY CONTROL
0= Parity checking disabled
1 = Parity checking enabled

3-2

R/W CHARACTER LENGTH
5 bits
00 =
01 =
6 bits
10 =
7 bits
11= 8 bits

1-0

RIW MODE AND BAUD RATE FACTOR
Synchronous 1 X rate
00 =
01 = Asynchronous 1 X rate
10 = Asynchronous 16 X rate
11= Asynchronous 64 X rate

1
I

MODE AND BAUD
RATE FACfOR
I

Mode registers 1 and 2 are accessed at the same 1/0 address. Read mode register 1 and then read mode register 2, or write mode register 1 and then write
mode register 2. Mode register 1 must be accessed to access mode register 2.
When programming mode register 1 on the V AXmate workstation, use a value
5EH.

10 - 10

Mouse Information - Hardware Description

Mode Register 2 (OC42H)
7

BAUD RATE

RECEIVE AND TRANSMIT
CLOCK SOURCE
1
1
1
I

Bit

Description

7-4

RECEIVE AND TRANSMIT CLOCK SOURCE
For the VAXmate workstation hardware, this value is fixed.

3-0

BAUD RATE
See Table 10-3

Mode registers 1 and 2 are accessed at the same 110 address. Read mode register 1 and then read mode register 2, or write mode register 1 and then write
mode register 2. Mode register 1 must be accessed to access mode register 2.
When programming mode register 2 on the VAXmate workstation, use a value
7CH.

Table 10-3 Baud Rate Table
Bits
3-0

Baud
Rate

Bits
3-0

Baud
Rate

0000
0001
0010
0011
0100
0101
0110
0111

50
75
110
134.5
150
300
600
1200

1000
1001
1010
1011
1100
1101
1110
1111

1800
2000
2400
3600
4800
7200
9600
19200

Mouse Information - Hardware Description

10 - 11

Command Register (OC43H)
5

OPERATING MODE REQUEST RESET
TO SEND ERROR

SYNCBI RECEIVE DTR
ASYNCB CONTROL

BIT
CONTROL

Bit

R/W Description

7-6

R/W OPERATING MODE
Normal operation
00 =
01 = Asynchronous (automatic echo mode)
10 = Local loop back
11= Remote loop back

R/W REQUEST TO SEND
0= Force request to send output high (disables interrupt buffer)
1 = Force request to send output low (enables interrupt buffer)
The 2661 EPCI has a buffer
between the interrupt output line and the peripheral interrupt controller input. This buffer is controlled by bit 3. Enabling the buffer
enables the 2661 EPCI interrupt output line.
RESET ERROR

Always 0

0=
1 =

No effect
Reset error flags (parity, framing, overrun)

R/W SYNCH/ASYNCH

0= Normal
1 = Force break
R/W RECEIVE CONTROL
0= Disable receiver, receive interrupt, and status register bit 1
1 = Enable receiver, receive interrupt, and status register bit 0

R/W DTR - Data Terminal Ready (output not connected)
0= Force data terminal ready output high
1 = Force data terminal ready output low

R/W XMIT CONTROL - Transmit Control

0=
1 =

Disable transmitter, transmit interrupt, and status register
bit 0
Enable transmitter, transmit interrupt, and status register
bit 0

When programming the command register on the VAXmate workstation, use a
10 - 12

Mouse Information - Hardware Description

base value of 30H. In addition to the base value, bits 0 and 3 (transmit and
receive control) must be applied as required.

Mouse Information - Hardware Description

10- 13

Programming Example
The mouse programming example demonstrates:
•
•
•
•

Communicating with the mouse
Interpreting the motion
Interpreting the buttons
Scaling the mouse motion to the screen

The example provides routines as described in the following list:
mouse init

send to mouse
mouse int

Initializes the SCN2661 serial interface.
Prepares the serial interface for interrupt driven
communications.
Sends commands to the mouse.
Is the serial interface interrupt handler.

mouse close
mouse

Deactivates the serial interface.
Executes the example program.

CAUTION
Improper programming or improper operation of this device can
cause the VAXmate workstation to malfunction. The scope of
the programming example is limited to the context provided in
this manual. No other use is intended.
The include file rb.h defines the ring buffer structure used in the serial interface interrupt handler. The include files kyb.h and exam,ple.h support the example, but are not pertinent to the mouse section.
The constant value MOUSE PORT defines the base address of the serial interface. The constant values MOUSE PIC through MOUSE HWI define the interrupt controller, interrupt input line, and the interrupt Vector for the serial
interface.
The constant values MMODE through CMND REG define bit values for the
serial interface registers. The constant values SELF TEST through POS REP
define the mouse command bytes. Finally, the constant values TESTMASK
through BUTTON_ERR define various values used in deciphering the mouse
reports.

10 - 14

Mouse Information - Programming Example

#include "rb.h"
#include "kyb.h"
#include "example.h"

/*************************************************************************/
/* define constant values used in example mouse driver
*/
/*************************************************************************/
#define MOUSE_PORT (MOUSE_UART *) OxOC40
#define MOUSE_PIC 1
#define MOUSE_INT 4
#define MOUSE_HWI Ox74

/* base address of mouse */
/* PIC that handles mouse */
/* mouse int request line */
/* harware int vector location */

/* SCN266l mode register bit values */
#define MMODE
#define P_ENAB
#define P_EVEN
#define P_ODD
#define WORD8
#define WORD7
#define WORD6
#define WORD5
#define S_BITl
#define S_BIT2
#define BD4800
#define CLKSPC

/* Aynchronous l6X rate */
/* Enable parity */
/* Even parity select */
/* Odd parity select */

Ox02
OxlO
Ox20
OxOO
OxOC
Ox08
Ox04
OxOO
Ox40
OxCO
OxOC
Ox70

/* 8 bit characters */
/* 7 bit characters */
/* 6 bit characters */
/* 5 bit characters */
/* One stop bit */
/* Two stop bits */
/* 4800 baud */
/* l6X clock */

/* SCN2661 status register bit masks */
#define THRE OxOl
#define RDRDY Ox02
#define ERRORS Ox38
#define PARITYERR Ox08
#define OVERRUN ERR Oxl0
#define FRAMINGERR Ox20

/* Transmit holding register is empty */
/* Receive holding register is full */
/* Parity, overrun or framing error */
/* Parity error */
/* Overrun error */
/* Framing error */

Mouse Information . Programming Example

10- 15

/* SCN2661 command register bit values */
#define TxEN OxOl
#define DTR
Ox02
#define RxEN Ox04
#define BREAK Ox08
#define RESET Oxl0
#define RTS
Ox20
#define CMODE OxCO
#define CMND_REG RTSIRESETIRxEN

/* Enable transmit control */
/* Disable data terminal ready */
/* Enable receive control */
/* Disable break */
/* Enable reset status */
/* RTS (normally on) */
/* Command mode (normally 0) */
/*normal operation, RTS=l, rec enabled */

/* Define mouse commands */
#define SELF_TEST 'T'
#define P_MODE
'D'
#define I_S_MODE 'R'
#define POS_REP
'P'

/* self-test command */
/* prompt mode */
/* incremental stream mode */
/* request position report */

/* These values are used to check the mouse */
#define TESTMASK OxeO
#define HEADER_BYTE Ox80
#define SELF TEST OxaO
#define POSREP Ox80
#define RIGHTBUTTON OxOl
#define MIDDLEBUTTON Ox02
#define LEFTBUTTON Ox04
#define XSIGN Oxl0
#define YSIGN Ox08
#define ROMRAM_ERR Ox3e
#define BUTTON_ERR Ox 3d

10 - 16

/* mask any header byte */
/* header byte indicator */
/* self-test header byte mask */
/* position report header byte mask */
/* right button mask */
/* left button mask */
/* middle button mask */
/* X-axis sign bit mask */
/* Y-axis sign bit mask */
/* self-test byte # 2 error type mask */
/* self-test byte # 2 error type mask */

Mouse Information· Programming Example

/***********************************************************************/
/* define structures used in example mouse driver
*/
/***********************************************************************/
typedef struct
{

unsigned char hr;
unsigned char status;
unsigned char mode;
unsigned char command;
} MOUSE_UART;

/* transmit/receive holding register */
/* status register */
/* mode register */
/* command register */

typedef struct mouse_dat
{

}

MOUSE_UART
RING_BUFF
RING_BUFF
MOUSE_OAT;

*base;
*prbi;
*prbo;

/* base i/o address of device */
/* pointer to input ring buffer structure */
/* pointer to output ring buffer structure */

/***********************************************************************/
/* reserve storage for variables used in example mouse driver
*/
/***********************************************************************/
#define BUF_SIZ 100
/* size of buffers */
#define HIWATER 76
/* buffer near full value */
#define LOWATER 26
/* buffer near empty value */
RING_BUFF rb[2];
/* ring buff ctrl structs */
char buff [2] [BUF_SIZ];
/* ring buffers */
unsigned char cmnd_reg;
/* value to write to command register */
MOUSE_OAT mouse_data = {MOUSE_PORT, trb[O] , trb[l] };
int quietmouse = OFF;

/* mouse state flag */

Mouse Information . Programming Example

10- 17

/***********************************************************************/
/* mouse_init() - establish a known state for the ~ouse and SCN266l
*/
/***********************************************************************/
void mouse_init()

/* initialize mouse and port */

{

/* pointer to mouse data */
/* pointer to mouse struct */
/* point to driver data */
/* assign base address */

/* initialize ring buffer structures */
init_rb(pdd->prbi, lbuff[O] [0] , BUP_SIZ, HIWATER, LOWATER):
init_rb(pdd->prbo, lbuffU] [0] , BUP_SIZ, HIWATER, LOWATER):
/* async l6x, enable parity, odd parity, eightbit data, one stop bit */
outp(lps->mode, MMODE I P_ENAB I P_ODD I WORD8 I S_BITl):
outp(lps->mode, BD4800 I CLKSPC):
/* l6x clock, 4800 baud */
cmnd_reg = CMND_REG:
/* init to normal contents */
outp(lps->co~and, cmnd_reg);
/* reset status errors */
}

NOTE
During the initialization process, it is possible to transmit or receive garbage characters. The mouse initialization function does
not account for this possibility.
/***********************************************************************/
/* mouse_open() - activate mouse interrupts
*/
/***********************************************************************/
void mouse_open()

/* open the mouse */

{

/* enable interrupt input */
}

10 - 18

Mouse Information . Programming Example

/***********************************************************************/
/* send_to_mouse() - write data to mouse
*/
/***********************************************************************/

unsigned char c;

/* byte value to transmit */

{

/* pointer to mouse data */
/* pointer to mouse struct */
/* hold state of CPU IF */

pdd = &mouse_data;
ps = pdd->base;
while (rb_in(pdd->prbo, c) < 0 )
intr_flg = int_off();
cmnd_reg 1= TxEN;
outp(&ps->command, cmnd_reg);
int_on(intr_flg);

/* point to driver data */
/* assign base address */
/* wait until stored in buffer */
/* disable CPU interrupt */
/* to enable transmitter */
/* enable transmitter */
/* enable CPU interrupt */

}

Mouse Information . Programming Example

10- 19

/***********************************************************************/
/* mouse_int() - interrupt handler for mouse serial port
*/
/***********************************************************************/
void mouse_intO

/* interrupt handler */

{

/* pointer to mouse data */
/* pointer to MOUSE_UART struct */

pdd = &mouse_data;
ps = pdd->base;

/* assign base address */

s = inp(&ps->status);

/* read status of port */

if(s & (PARITYERR I FRAMINGERR»
s = inp(&ps->hr);
else if(s & RDRDY)
{

if (rb_in(pdd->prbi. inp(&ps->hr»

/* garbage character ? */
/* read garbage character */
/* is there anything to read ? */
/* read and store in ring buffer */
< 1 )
/* buffer getting full ? */

{

send_to_mouse(P_MODE);
quietmouse = ON;

/* put mouse in prompt mode */

}
}

if(s & THRE)

/* ready to transmit ? */

{

if (rb_out(pdd->prbo. &c) < 0)
cmnd_reg &= TxEN;
else outp(&ps->hr. c);

/* any characters to transmit? */
/* disable transmitter */
/* write the character */

}

outp(&ps->command. cmnd_reg);
eoi(MOUSE_PIC);

/* reset status errors */
/* send EOI to interrupt controller */

}

NOTE
This routine could check for overrun errors, but it does not.
Because each mouse report has a fixed byte count, missing characters are detected in the record collection part of the mouse()
function.

10 - 20

Mouse Information - Programming Example

/***********************************************************************/
/* mouse_close() - deactivate mouse port interrupts
*/
/***********************************************************************/
void mouse_close()

/* deactivate the mouse */

{

/* pointer to mouse data */
/* pointer to MOUSE_UART struct */

pdd = lmouse_data;
send_to_mouse(P_MODE);
while (pdd->prbo->count)

/* point to driver data */
/* put mouse in prompt mode */
/* wait until ring buffer empty */

cmnd_reg = CMND_REG & RxEN;
/* disable receiver and transmitter */
ps = pdd->base;
/* assign base address */
outp(&ps->command, cmnd_reg);
/* write new command */
imask(MOUSE_PIC, MOUSE_INT, OFF);
/* disable interrupt input */
}

Mouse Information - Programming Example

10- 21

/***********************************************************************/
/* example application that uses mouse driver
*/
/***********************************************************************/
mouse 0
{

static MESSAGE mmouse[]

/* mouse menu */

{

3, 34,
5, 18,
{ 6, 16,
{
8, 24,
{ 9, 24,
{ 10, 24,
{ 11, 24,
{ 12, 24,
{ 14, 24,
{ 15, 24,
{ 16, 24,
{ 18, 24,
{ 19, 24,
{ 20, 24,
{ 21, 24,
{
0, 0,
{
{

"Mouse Example" },
"Move the mouse to see X and Y displacements." },
"Move cursor to a box and select with left button." },
"[ ] End Mouse Example" },
,,[ ] Increase X Scale" },
"[ ] Decrease X Scale" },
"[ ] Increase Y Scale" },
"[ ] Decrease Y Scale" },
"Left button status:
Up " },
"Middle button status: Up " },
"Right button status: Up " },
"X encoder counts:
0" },
0" },
"Y encoder counts:
"X Scale: 12" },
"Y Scale: 52" },
0 },

};

/* pointer to mouse data */

unsigned char i_buff[80];
/* input buffer */
char o_buff[80];
/* output buffer */
char kb;
unsigned char *pb;
/* pointer to input buffer */
int row = 0;
/* row position of cursor or text */
int tmp;
/* temporary variable */
int pos_rep = 0;
/* mouse position report flag */
int end_me = FALSE;
/* end mouse example flag */
int left_button = FALSE;
/* state of left button */
int bufLstate;
/* input buffer state flag */
int x_abs = 40;
/* absolute position of cursor in X-axis */
int y_abs = 12;
/* absolute position of cursor in Y-axis */
int x_cnts = 0;
/* accumulated X-axis encoder counts */
int y_cnts = 0;
/* accumulated Y-axis encoder counts */
int x_scale = 12;
/* encoder counts per column */
int y_scale = 52;
/* encoder counts per row */
int moved = 0;
/* flag to indicate that mouse reported motion */

10- 22

Mouse Information . Programming Example

int intr_flg;
int cnt_req;

/* hold state of CPU IF */
/* byte count required for report */

extern int time_flag;

/* defined in RTC example */

pdd = tmouse_data;
/* get pointer to data */
ps .. pdd->base;
/* assign base address */
intr_flg - int_off();
/* disable CPU interrupt */
iv_init(MOUSE_HWI);
/* init interrupt vectors */
mouse_initO;
/* init mouse */
int_on(intr_flg);
/* enable CPU interrupt */
mouse_openO;
/* activate mouse */
send_to_mouse(P_MODE);
/* ensure mouse is in prompt mode */
while(rb_out(pdd->prbi. ti_buff[O]) >s 0) /* while buffer not empty */
/* dump characters */
send_to_mouse(SELF_TEST);
/* issue self-test command */
/* disable CPU interrupt */
intr_flg - int_off();
time_flag = 0;
/* reset RTC second flag */
int_on(intr_flg);
/* enable CPU interrupt */
for(tmp = 0; time_flag < 3 tt tmp < 4; )
{

if (rb_out(pdd->prbi. ti_buff[tmp]) >= 0)

/* try to read character */

{

if«i_buff[tmp] t TESTMASK)
tmp = 1;
else if(tmp) tmp++;

SELFTEST)/* self-test header byte */
/* first byte of report */
/* additional report bytes */

}
}

tmp = 0;
if(time_flag >= 3)

/* check for time-out error */

{

strcpy(to_buff[O]. "Mouse time-out error");
/* error message */
tmp = 1;
/* set error indicator */
}

else if(i_buff[2] == Ox3e)

/* check for mouse ROM/RAM error */

{

strcpy(to_buff[O]. " Mouse ROM/RAM error");
/* error message */
tmp = 1;
/* set error indicator */
}

else if (i_buff [2]

== Ox3d)

/* check for mouse button errors */

{

strcpy(to_buff[O]. " Mouse button error");
/* error message */
tmp = 1;
/* set error indicator */
}
i f (tmp)
{

/* test error indicator */

Mouse Information· Programming Example

10- 23

disp_str(12, 35, to_buff[O])i
/* show error message */
disp_str(13 , 35, "Press FlO to continue")i
/* show help message */
while(l) if(get_key(tkb) == 1 tt kb =~ FlO) breaki
}

else
{

disp_menu(mmouse)i
cursor_on (y_abs, x_abs)i
send_to_mouse(I_S_MODE)i
cnt_req = -li
pos_rep = FALSEi
pb = tLbuff[O]i
while(end_me == FALSE)

/* display the mouse menu */
/* make cursor visible */
/* reset to incremental stream mode */
/* set byte count required to below zero */
/* no position report yet */
/* initialize pointer to input buffer */

{

chk_dt()i
/* check date and time for update */
buff_state = rb_out(pdd->prbi, pb)i
/* try to read mouse */
if (buff_state >= 0)
/* did the mouse send anything 1 */
{

if(*pb t HEADER_BYTE)

/* is it a header byte ? */

{

/* move to beginning of buffer */
Lbuff[O] = *pbi
pb = ti_buff[l]i
/* reset to next byte in input buffer */
if«i_buff[O] t TESTMASK)
POSREP) /* discover header type */
{

cnt_req
pos_rep

2i
TRUEi

/* remaining count required */
/* have header byte for position report */

}

/* anthing else is an error */

else
{

cnt_req
pos_rep

-li
FALSEi

/* set byte count required to below zero */
/* no position report */

}
}

else if(pos_rep)

/* if received a position report header byte */

{

if(++pb > ti_buff[10])
/* increment buffer pointer */
{
/* if pointer test is true, unexpected error condition */
pb = tLbuff[O]i
/* reset buffer pointer */
pos_rep = FALSE;
/* cannot be a position report */
cnt_req = -li
/* set byte count required to below zero */
}

if(--cnt_req == 0)

/* end of report ? */

{

/* get position increments */
moved = 0;
tmp = Lbuff [1] ;

10 - 24

/* clear mouse motion flag */
/* get X-axis increment */

Mouse Information - Programming Example

if(l(i_buff[O] t XSIGN» tmp = -tmp;
/* check sign bit */
x_cnts += tmp;
/* accumulate X-axis encoder counts */
sprintf(o_buff, "%4d", tmp);
/* convert to a string */
disp_str(18, 42, o_buff);
/* show X-axis increment */
tmp = x_cnts / x_scale;
/* enough to show motion? */
if (tmp)
{

x_cnts -= x_scale * tmp;
/* remove scaled counts */
x_abs += tmp;
/* add to absolute position */
if(x_abs < 0) x_abs = 0;
/* no off-screen motion */
if(x_abs > 79) x_abs = 79;
/* no off-screen motion */
moved = 1;
/* set flag to update cursor position */
}

tmp = i_buff[2];
/* get Y-axis increment */
if(l(i_buff[O] t YSIGN» tmp = -tmp;
/* check sign bit */
/* y-axis encoder counts are accumulated negatively to invert motion */
y_cnts -= tmp;
/* accumulate Y-axis encoder counts */
sprintf(o_buff, II %4d II , tmp);
/* convert to a string */
disp_str(19, 42, o_buff);
/* show Y-axis increment */
tmp = y_cnts / y_scale;
/* enough to show motion? */
if (tmp)
{

y_cnts -= y_scale * tmp;
/* remove scaled counts */
y_abs += tmp;
/* add to absolute position */
if(y_abs < 0) y_abs = 0;
/* no off-screen motion */
if(y_abs > 24) y_abs = 24;
/* no off-screen motion */
moved = 1;
/* set flag to update cursor position */
}

if(moved) mv_cursor(y_abs, x_abs);

/* update cursor */

/* display state of mouse buttons */
for(tmp = LEFTBUTTON, row = 14; row < 17; row++, tmp »= 1)
{

if(Lbuff[O] t tmp) disp_str(row, 46, "Down");
else disp_str(row, 46, "Up II);
}

if(i_buff[O] t LEFTBUTTON)

/* test for valid selection */

{

if(lleft_button) /* must release button from last select */
{

left_button = TRUE;
if(x_abs == 26)

/* left button pressed */

{

swi tch(y _abs)
{

case 8:

/* end mouse example */

Mouse Information - Programming Example

10- 25

end_me
break;

TRUE;

/* set to true */

case 9:
if (x_scale < 1000)
x_scale += 2',
break;

/* increase X scale */
/* arbitrary value */
/* arbitrary increment */

case 10:
if(x_scale > 2)
x_scale
2;
break;

/* decrease X scale */
/* cannot be zero */
arbitrary
decrement */
/*

case 11:
if(y_scale < 1000)
y_scale += 2;
break;

/* increase Y scale */
/* arbitrary value */
/* arbitrary increment */

case 12:
if(y_scale > 2)
y_scale
2;
break;

/* decrease Y scale */
/* cannot be zero */
/* arbitrary decrement */

}

sprintf (o_buff, "%3d", x_scale);
/* convert */
disp_str(20, 33, o_buff);
/* show new X-scale */
sprintf (o_buff, "%3d", y _scale) ;
/* convert */
disp_str(21, 33, o_buff);
/* show new Y-scale */
}
}
}

else left_button
pos_rep = FALSE;

FALSE;

/* reset left button state */
/* no position report */

}
}
}

/* If mouse disabled because the ring buffer was full, turn it back on */
if(quietmouse II buff_state -= 0) send_to_mouse(I_S_MODE);
}
}

mouse_close 0 ;
intr_flg = int_off();
iv_rest(MOUSE_HWI);
int_on(intr_flg);

/* close the mouse */
/* no interrupts allowed */
/* restore old vectors */
/* allow interrupts */

}

10- 26

Mouse Information . Programming Example

Chapter 11
Diskette Drive Controller
Introduction
The diskette drive controller interfaces the VAXmate system bus and the
diskette drives. The diskette drive controller supports the following drives and
media:
Drive Type

Media

5 ~ Inch - High capacity

1.2 Megabyte - 80 Track - High capacity
800 Kbyte - 80 Track - Standard
360 Kbyte - 40 Track - Standard (with
double stepping)

The diskette drive controller operates in either DMA or non-DMA mode. In
DMA mode, the processor initializes the DMA controller and issues the
transfer command to the diskette controller. The diskette controller and the
DMA controller transfer the data unattended. In non-DMA mode, the diskette
controller generates interrupts to the processor each time the controller
transfers a data byte.

Diskette Drive Controller - Hardware Description

11 - 1

Diskette Drive Controller Registers
The diskette drive controller has five 8·bit registers that are accessed through
four port addresses. Table 11·1 lists the registers.
Table 11·1: Diskette Drive Controller Registers
Address

RIW

03F2H
03F4H

Control register

Main status register

03F5H

RlW

Data register

03F6H
03F6H

Transfer rate register
Change register

11 - 2

Diskette Drive Controller . Hardware Description

Control Register (03F2H)
5

Bit

RIW Description

7-6

SELECT

Always 0
MOTOR B

o = Drive B motor off and disable bit 0
1 = Drive B motor on and enable bit 0
MOTOR A

o = Drive A motor off and disable bit 0
1 = Drive A motor on and enable bit 0
DMA ENABLE

o = Disable the diskette drive controllers DMA request, DMA acknowledge, and interrupt request
1 = Enable the diskette drive controllers DMA request, DMA acknowledge, and interrupt request

RESET

o = Reset the diskette drive controller
1 = Enable the diskette drive controller
Always 0
DRIVE SELECT

o = Select Drive A
1 = Select Drive B
This bit is enabled or disabled by bits 5-4.

Diskette Drive Controller - Hardware Description

11- 3

Main Status Register (03F4H)
7

REQUEST DATA
I/O
FOR
MASTER DIR

543

NON-DMA CONTROL DRIVE 3 DRIVE 2 DRIVE 1 DRIVE 0
MODE
BUSY
BUSY
BUSY
BUSY
BUSY

Bit

R/W Description

REQUEST FOR MASTER
0= Data register not ready
1 = Data register is ready to be read or written by processor

DATA 110 DIR - Data 110 Direction
0= Transfer data from processor to data register
1 = Transfer data from data register to processor

NON-DMA MODE
0= Result phase (execution phase ended)
1 = Execution phase

CONTROL BUSY
0= Controller ready to accept new command
1 = Controller processing a read or write command

DRIVE 3 BUSY
0= Drive 3 not seeking
1 = Drive 3 seeking new track
DRIVE 2 BUSY
0= Drive 2 not seeking
1 = Drive 2 seeking new track

11- 4

DRIVE 1 BUSY
0= Drive 1 not seeking
1 = Drive 1 seeking new track
DRIVE 0 BUSY
0= Drive 0 not seeking
1 = Drive 0 seeking new track

Diskette Drive Controller- Hardware Description

Data Register (03F5H)
765

I : :
Bit

RIW Description

7-0

RlW Status or data

:STATUS

~ DATA :

This register accesses several internal diskette drive controller registers. The
internal register accessed depends on the state of the diskette drive controller.
The internal registers and the diskette drive controller states are discussed
later in this chapter in the section Diskette Drive Controller Programming.

Diskette Drive Controller - Hardware Description

11 - 5

Data Transfer Rate Register (03F6H)
7

654

Bit

R/W Description

7-2

Always 0

1-0

TRANSFER RATE
00 = 500 KBits per second
01 = 250 KBits per second *
10 = 250 KBits per second
11 = Not used (selects 250 KBits per second I

* The industry-standard transfer rate for the bit values (011 is 300 KBits
per second.
On power-up, this register defaults to 250 KBits per second.

Change Register (03F6H)
7

1= 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bit

RIW Description

CHANGE STATUS

o = Since the last time this register was read, the diskette in the
1 =

6-0

11- 6

selected drive has not been removed.
Since the last time this register was read, the diskette in the
selected drive was removed.

Always 0

Diskette Drive Controller - Hardware Description

Diskette Drive Controller Internal Registers
The diskette drive controller has several internal registers that are read or
written through the data register as a series of command or status bytes. The
usage of these registers is dependent on the command. Tables 11-3 through
11-17 define the command specific usage.

Internal Register - Command
7

Bits R/W Description
7

MT - Multi-track (Must be 0 for some commands)

o = Disable multi-track
1 =

4-0

Enable multi-track (Accessing both sides of the diskette
automatically)

MFM - Modified Frequency Modulation

o = Use FM (Frequency Modulation) for reading and writing the
diskette
1 = Use MFM for reading and writing the diskette
SK - Skip (Must be 0 for some commands)
Do not skip sectors containing a DELETED DATA
ADDRESS MARK
1 = Skip sectors containing a DELETED DATA ADDRESS
MARK

COMMAND SELECT
00010 = Read Track
00011 = Specify
00100 = Sense Drive Status
00101 = Write Data
00110 = Read Data
00111 = Recalibrate
01000 = Sense Interrupt Status
01001 = Write Deleted Data

01010 = Read ID
01100 = Read Deleted Data
01101 = Format Track
01111 = Seek
10001 = Scan Equal
11001 = Scan Low or Equal
11101 = Scan High or Equal

Diskette Drive Controller - Hardware Description

11 - 7

Internal Register . Head/Unit Select
7

654

I I I I I I~ I ~ I
0

Bit

RtW Description

7·3

Always 0
HEAD SELECT

o = Select head on side 0
1 =

Select head on side 1

1·0

UNIT SELECT
00 = Select drive 0
01 = Select drive 1
10 = Select drive 2
11 = Select drive 3
Because the outputs are not connected, these bits are ineffective.
Use bits 5, 4, and 0 of the control register to select the drive.

11- 8

Diskette Drive Controller . Hardware Description

Internal Register . Status Register 0
76543

~un
CODE

Bit

RIW Description

7-6

INTERRUPT CODE
00 = Command completed successfully
01 = Command started but did not complete successfully
10 = Command was never started
11 = Abnormal termination (disk drive ready signal changed
state during command executionI
SEEK END
o = Seek not complete
1 = Seek complete
EC - Equipment Check
o = No error detected
1 = Fault signal detected or, during a recalibrate, the track 0
signal was not detected after 77 step pulses
NOT READY

o = Drive was ready

1 = Drive not ready signal was detected

HEAD ADDRESS

o = Side 0 selected
1 =

1-0

Side 1 selected

UNIT SELECT
00 = Drive 0 selected
01 = Drive 1 selected
10 = Drive 2 selected
11 = Drive 3 selected

Diskette Drive Controller - Hardware Description

11 - 9

Internal Register· Status Register 1
7

654

DATA
ERROR
0
RIW Description

NO DATA

HISSING
ADDRESS
HARK

EN - End of Cylinder
No error
1 = Controller attempted to access a sector beyond the last
sector of a cylinder

Always 0
DATA ERROR
No error
1 = Controller detected a cyclic redundancy check (CRC) error in
the ID or data field

OVERRUN

o = No error
1. =

OVERRUN

Bit

During a data transfer in non-DMA mode. the processor did
not service the controller within the required time interval

Always 0
NO DATA
No error
1 = One of the following conditions occurred:

During execution of a read data. a write-deleted data, or a scan
command. the controller could not find the specified sector.
During execution of a read ID command. the controller could not
read the ID field.
During execution of a read track command. the starting sector
could not be found.

11- 10

Diskette Drive Controller - Hardware Description

Bit

RIW Description (Status Register 1 - cont.)

NW - Not Writable

o = No error
1 =

During a write data. write-deleted data, or format track command, the controller detected a write-protect signal from the
disk drive.

MISSING ADDRESS MARK
No error
1 = One of the following conditions occurred:

The controller had detected the index hole twice, but had not
detected the ID field ADDRESS MARK.
The controller could not detect the DATA ADDRESS MARK
or the DELETED DATA ADDRESS MARK. When this bit
is set, status register 2 bit 0 (MDI is set.

Diskette Drive Controller - Hardware Description

11 - 11

Internal Register· Status Register 2
7

DATA
CONTROL ERROR
IWU{
IN DATA
FIELD

BIT
EQUAL

lID

SCAN

Bit

RIW Description

Always 0

CONTROL MARK
0= DELETED DATA ADDRESS MARK not detected
1 = During a read data or scan command, the controller found a
DELETED DATA ADDRESS MARK.

DATA ERROR IN DATA FIELD
0= No error
1 = Controller detected a cyclic redundancy check {CRC) error in
the data field.

WC - Wrong Cylinder
0= No error
1 = Cylinder number in the ID field does not match the cylinder
number in the internal register

SCAN EQUAL HIT
0= No match
1 = During the execution of a scan command, the equal condition
was satisfied.

SN - Scan Not Satisfied
0= No error
1 = During the execution of a scan command, the controller
could not find a sector on the cylinder that met the
condition.

BC - Bad Cylinder
0= No error
1 = Cylinder number in the ID field is FFH and does not match
the cylinder number in the internal register

MD - Missing ADDRESS MARK in Data Field
0= No error
1 = During execution of a read command, the controller could
not find a DATA ADDRESS MARK or DELETED DATA
ADDRESS MARK.

11- 12

Diskette Drive Controller - Hardware Description

Internal Register . Status Register 3
76543

1
I

FAULT

VRITE READY
PROTECT

TRACK 0

NO
SIDE

BEAD

ADDRESS

UNIT SELECT
I

Bit

RIW Description

FAULT

o = No error

1 = Diskette drive fault signal detected
6 R WRITE PROTECT
o = Diskette not write protected
1 = Diskette drive write protect signal detected
5

1-0

READY
Drive not ready
1 = Drive ready
TRACK 0
o = Read/Write heads not over track 0
1 = Read/Write heads over track 0

TWO SIDE
Diskette is single sided
1 = Diskette is double sided

HEAD ADDRESS
Side 0 selected
1 = Side 1 selected

UNIT SELECT
00 = Drive 0 selected
01 = Drive 1 selected
10 = Drive 2 selected
11 = Drive 3 selected

Diskette Drive Controller - Hardware Description

11- 13

Internal Register· SRTIHUT
7

I :

RIW Description

7-4

11- 14

7: I : ~ : I

Bit

3-0

SRT - Step Rate
0000 = 16 ms
0001 = 15 ms
0010 = 14 ms
0011 = 13 ms
0100 = 12 ms
0101= 11 ms
0110 = 10 ms
0111 = 9 ms
HUT - Head Unload Time
0000 = 0
0001 = 16 ms
0010 = 32 ms
0011 = 48 ms
0100 = 64 ms
0101= 80 ms
0110 = 96 ms
0111 = 112 ms

1000 =
1001 =
1010 =
1011 =
1100 =
1101 =
1110 =
1111 =

8 ms
7 ms
6 ms
6 ms
4 ms
3 ms
2 ms
1 ms

1000 =
1001 =
1010 =
1011 =
1100 =
1101 =
1110 =
1111 =

128 ms
144 ms
160 ms
176 ms
192 ms
208 ms
224 ms
240 ms

Diskette Drive Controller - Hardware Description

Internal Register· HLT/ND
7

654

Bit

RIW Description

7-1

HLT - Head Load Time
No head load time
0000000 =
0000001-1111111 = 2 ms to 254 ms in 2 ms steps
NO - Non-OMA Mode
o = OMA mode enabled
1 = DMA mode disabled

Internal Register· C
This 8-bit register specifies the currently selected cylinder/track number. To
ensure that it is at the correct cylinder/track, the diskette controller compares
this cylinder/track number to the cylinder/track in the sector header.

Internal Register . H
This 8-bit register specifies the currently selected read/write head. To ensure
that it is on the correct side of the diskette, the diskette controller compares
this head address to the head address in the sector header. Only 0 and 1 are
valid values.

Internal Register . R
This 8-bit register specifies the desired sector number.

Diskette Drive Controller - Hardware Description

11 - 15

Internal Register . N
This 8-bit register specifies the number of data bytes per sector as follows:
Value

Bytes per Sector

OOH
01H
02H
03H
04H
05H
06H

128
256
512
1024
2048
4096
8192

Internal Register . EOT
This 8-bit register specifies the last sector of a read/write operation. The value
written to this register is the last desired sector plus 1.
For example, to read or write one sector (sector number 5), internal register R
would contain 05H and internal register EOT would contain 06H. To read or
write five sectors (starting at sector 1), internal register R would contain 01H
and internal register EOT would contain 06H.

Internal Register . GPL
This 8-bit register specifies the gap between sectors. When executing the
format-track command, use a value of 54H. Otherwise, use a value of 1BH.
These are the values specified by the ROM BIOS. See Interrupt 13H in
Chapter 15.

Internal Register· DTL
When internal register N contains OOH, this 8-bit register specifies the number
of bytes to be read from or written into a sector. For this register, the ROM
BIOS definea a. value of FFH. See Interrupt 13H in Chapter 15.

Internal Register . SC
For the format-track command, this 8-bit register specifies the number sectors
per track.

11- 16

Diskette Drive Controller - Hardware Description

Internal Register . D
For the format-track command, this 8-bit register specifies the value used as a
fill byte. For this register, the ROM BIOS defines a value of F6H. See
Interrupt 13H in Chapter 15.

Internal Register . STP
For the scan commands, this register specifies contiguous sectors (interleave of
11 or alternate sectors (interleave of 2}.

Internal Register . PCN
For the sense-interrupt-status command, this 8-bit register returns the resulting present-cylinder number

Internal Registers· NCN
For the seek command, this 8-bit register specifies the desired cylinder/track
number {new cylinder number}.

Diskette Drive Controller - Hardware Description

11- 17

Diskette Drive Controller Programming
The diskette drive controller has three operational states, command, execution,
and result. The current state is determined by bit 7 IREQUEST FOR
MASTER) and bit 6 (110 DIR) of the main status register. If bit 7 is equal to
O. the diskette drive controller is in the execution state. Otherwise. the diskette
drive controller is in a command or result state. Bit 6 determines whether the
diskette drive controller is in the command or result state. If bit 6 is equal to
0, the diskette drive controller is in the command state. Otherwise, the
diskette drive controller is in the result state.

Command State
The diskette drive controller accepts a series of 1 to 9 command bytes that are
written to the data register. Each command has a fixed set of data bytes that
are required to initiate the command. For correct results, the set must not be
shortened.
On acceptance of a command, the diskette drive controller enters the execution
state. If a command is not accepted as a valid command, the diskette drive
controller sets the internal register, status register 0, equal to 80H.
The diskette drive controller has fifteen commands. Table 11-2 lists the
diskette drive controller commands. The commands listed in Table 11-2 are
described later in this chapter. The four internal status registers, 0-3, are
described in the section on Diskette Drive Controller Internal Registers.

11- 18

Diskette Drive Controller - Hardware Description

Table 11-2: Diskette Drive Controller Commands
Command

Description

Read Data

Multi-sector read of sectors with DATA ADDRESS
MARK in header lat the current track)

Write Data

Multi-sector write at the current track (writes a
DATA ADDRESS MARK in header)

Read Deleted Data

Multi-sector read at the current track (including those
with a DELETED DATA ADDRESS MARK in
header)

Write Deleted Data

Multi-sector write at the current track (writes a
DELETED DATA ADDRESS MARK)

Read Track

Read all sectors at the current track

Read ID

Reads the ID field of the first sector encountered at
the current track

Format Track

Formats sectors in the track as indicated

Scan Equal

Data on the diskette is compared for equality to data
in memory IS-bit data)

Scan Low or Equal

Data on the diskette is compared for equality or a
value less than the data in memory (S-bit data)

Scan High or Equal

Data on the diskette is compared for equality or a
value greater than the data in memory IS-bit data)

Recalibrate

Read/Write heads retract to track 0

Sense Interrupt Status

Returns the internally stored status registers

Specify

Sets the diskette controller parameters HEAD LOAD,
HEAD UNLOAD, and STEP RATE

Sense Drive Status

Loads the current drive status into the internal register, status register 3

Seek

Read/Write heads move to the specified track

Diskette Drive Controller - Hardware Description

11- 19

Execution State
The diskette drive controller executes the command as instructed. When the
operation is complete, the diskette drive controller generates an interrupt to
the processor and enters the result state.

NOTE
The seek and recalibrate commands do not have a result state.
The overlapped seek or recalibration capability, described in the
following explanation, is not supported by VAXmate diskette
drive controllers or industry-standard diskette drive controllers.
The floppy disk controller chip supports overlapped seeks and
recalibrations. That is, issuing a seek or recalibrate command to
two or more drives before the previous seek or recalibrate commands have completed. To provide this feature, the result state
was eliminated. After issuing one or more seek or recalibrate
commands, the controlling program must monitor the main
status register. Bits 3-0 of the main status register reflect the
status of the corresponding drive.

Result State
On completion of a command, the diskette drive controller provides a series of
status bytes that are read from the data register. These status bytes represent
the states of corresponding internal registers. Each command has a fixed set of
status bytes that result from a command. Until all of the status bytes have
been read, the diskette drive controller will not accept a new command.

Command and Result Register Sets
Each command has a specific set of internal registers that must be written
through the data register. During the result state, each command has a specific
set of internal registers that must be read through the data register.
Tables 11-3 through 11-17 define the command and result register sets for the
various commands.
Invalid command codes produce a result state that contains only status register
3.

11- 20

Diskette Drive Controller - Hardware Description

Table 11·3 Register Sets for Read Data Command
State

Order

Comment

Command

1
2
3

Command
HeadlU nit Select
C
H
R
N
EOT
GPL
DTL

Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Data Length

Status Register 0
Status Register 1
Status Register 2
C
H
R
N

Cylinder
Head address
Sector number
Sector Size

5
6
7
8
9

Result

1
2
3
4

5
6
7

Table 11·4 Register Sets for Write Data Command
State

Order

Comment

Command

1
2
3

Command
HeadlU nit Select
C
H
R
N
EOT
GPL
DTL

SK must be 0
Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Data Length

Status Register 0
Status Register 1
Status Register 2
C
H
R
N

Cylinder
Head address
Sector number
Sector Size

Result

5
6
7
8
9
1
2
3
4
5
6
7

Diskette Drive Controller· Hardware Description

11- 21

Table 11-5

State

Order

Command

1
2
3

Command
HeadlUnit Select
C
H
R

5
6
7

8
9
Result

1
2
3

EOT
GPL
DTL

5
6

Status Register 0
Status Register 1
Status Register 2
C
H
R

Comment

Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Data Length

Cylinder
Head address
Sector number
Sector Size

Table 11-6 Register Sets for Write Deleted Data Command
State

Order

Comment

Command

1
2
3

SK must be 0

Command
Head/Unit Select
C
H
R

EOT
GPL
DTL

8
9
Result

1
2
3
6

Status Register 0
Status Register 1
Status Register 2
C
H
R

4
5

11 - 22

Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Data Length

Cylinder
Head address
Sector number
Sector Size

Diskette Drive Controller - Hardware Description

Table 11·7 Register Sets for Read Track Command
State

Order

Comment

Command

1
2
3

Command
Head/Unit Select
C
H
R

MT must be 0

5
6
7
8
9

Result

1
2
3
4

5
6
7

EOT
GPL
DTL
Status Register 0
Status Register 1
Status Register 2
C
H
R
N

Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Data Length

Cylinder
Head address
Sector number
Sector Size

Table 11·8 Register Sets for Read ID Command
State

Order

Comment

Command

1
2

Command
HeadlUnit Select

MT and SK must be 0

Result

1
2
3

Status Register 0
Status Register 1
Status Register 2
C
H
R

4
5

Cylinder
Head address
Sector number
Sector Size

Diskette Drive Controller . Hardware Description

11- 23

Table 11-9 Register Sets for Format Track Command
State

Order

Comment

Command

1
2
3

Command
Head/Unit Select

MT and SK must be 0

Sector Size
Sectors per track
Gap length
Fill data

5
6

1
2
3

Result

SC
GPL
D

5
6

Status Register 0
Status Register 1
Status Register 2
C
H
R

Cylinder
Head address
Sector number
Sector Size

Table 11-10 Register Sets for Scan Equal Command
State

Order

Command

1
2
3

Command
Head/Unit Select
C

H
R

5
6

5
6
7

8
9

Result

1
2
3
4

11- 24

EOT
GPL
STP
Status Register 0
Status Register 1
Status Register 2
C
H
R

Comment

Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Interleave U or 21 .

Cylinder
Head address
Sector number
Sector Size

Diskette Drive Controller - Hardware Description

Table 11·11

State

Order

Command

1
2
3

Command
HeadlUnit Select
C
H
R

5
6
7
8
9

Result

1
2
3
4

5
6
7

EOT
GPL
STP
Status Register 0
Status Register 1
Status Register 2
C
H
R
N

Comment

Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Interleave (1 or 2)

Cylinder
Head address
Sector number
Sector Size

Table 11·12 Register Sets for Scan High or Equal Command
State

Order

Command

1
2
3

Head/U nit Select

Result

Command
C
H
R

EOT
GPL
STP

8
9
1
2
3
4

5
6
7

Comment

Status Register 0
Status Register 1
Status Register 2
C
H
R
N

Cylinder
Head address
Sector number
Sector Size
Last sector for operation
Gap length
Interleave (1 or 2)

Cylinder
Head address
Sector number
Sector Size

Diskette Drive Controller . Hardware Description

11 - 25

Table 11-13 Register Sets for Recalibrate Command
State

Order

Command

1
2

Command
HeadlUnit Select

Result

None

Comment

Issue a sense interrupt
status command

Table 11-14 Register Sets for Sense Interrupt Status Command
State

Order

Command

1
2

Command
Head/U nit Select

Result

1
2

Status Register 0
PCN

Comment

Present cylinder number

Table 11-15 Register Sets for Specify Command
State
Command

Order

Command
SRT/HUT
HLT/ND

3
Result

11 - 26

None

Comment

Command does not have a
result state

Diskette Drive Controller - Hardware Description

Table 11·16

State

Order

Command

1
2

Command
HeadlU nit Select

Result

Comment

Status Register 3

Table 11·17 Register Sets for Seek Command
State

Order

Comment

Command

1
2

Command
Head/Unit Select
NCN

New cylinder number

3
Result

None

Issue a sense interrupt
status command

Programming Example
The following programming example demonstrates:
• Initializing the diskette drive controller
• Using DMA data transfers
• Recalibrating the diskette drive
• Seeking to a track
• Hard formatting a diskette
CAUTION
Improper programming or improper operation of this device can
cause the VAXmate workstation to malfunction. The scope of
the programming example is limited to the context provided in
this manual. No other use is intended.

Diskette Drive Controller . Programming Example

11- 27

#include "kyb.h"
#include "example.h"

/***********************************************************************/
/* define constants used in diskette controller example

/***********************************************************************/
/* define bit values for diskette controller control register (DCCR)

/* bit mask for drive select */
/* bit value allows fdc to run
if this bit not set. fdc is reset */
'define DMA_INT_ON Ox08 /* value to enable DMA and interrupts to CPU */
/* bit value to turn on drive a motor */
'define DRVA_MOTOR Oxl0
#define DRVB_MOTOR Ox20
/* bit value to turn on drive b motor */
#define DRV_SEL
#define FDC_ON

OxOl
Ox04

/* define bit values for data transfer rate register */

#define DTR_500
#define DTR_300
#define DTR_250

OxOO
OxOl
Oxl0

/* bit value for 500 Kbit transfer rate */
/* VAXmate = 250 Kbit transfer rate */
/* bit value for 250 Kbit transfer rate */

/* define disk change register bit */
#define DISK_CnG

Ox80

/* diskette changed if set */

/* define bit values for FDC main s.tatus register */
#define FDDO_BUSY
#define FDD1_BUSY
#define FDD2_BUSY
#define FDD3_BUSY
#define FDD_BUSY
#define FDC_CB
#define FDC_NDM
#define DIO_RD
#define RQM

11 - 28

OxOl
/* diskette drive o busy doing seek */
Ox02
/* diskette drive 1 busy doing seek */
Ox04
/* diskette drive 2 busy doing seek */
Ox08
/* diskette drive 3 busy doing seek */
FDDO_BUSY I FDDCBUSY I FDD2_BUSY I FDD3_BUSY
Oxl0
/* controller busy */
Ox20
/* in non-DMA mode = execution phase busy */
Ox40
1* indicates processor should read data reg */
Ox80
/* data register ready to send or receive */

Diskette Drive Controller • Programming Example

/* define status register 0 bit values */
#define SRO_USO
#define SRO_US1
#define SRO_US2
#define SRO_US3
#define SRO_HD
#define SRO_NR
#define SRO_EC
#define SRO_SE
#define SRO_IC_AT
#define SRO_IC_IC
#define SRO_IC_NR
#define SRO_IC_NT

OxOO
Ox01
Ox02
Ox03
Ox04
Ox08
Ox10
Ox20
Ox40
Ox80
OxcO
OxOO

/* at interrupt time, unit select
drive 0 */
/* at interrupt time, unit select
drive 1 */
/* at interrupt time, unit select = drive 2 */
/* at interrupt time, unit select
drive 3 */
/* head address at interrupt time */
/* diskette drive not ready */
/* equipment check, could not reach track 0 */
/* seek command completed */
/* interrupt code = abnormal termination */
/* interrupt code = invalid command */
/* interrupt code = drive not ready */
/* interrupt code = normal termination */

/* define status register 1 bit values */
#define SRLMA
#define SRLNW
#define SRLND
#define SRLOR
#define SRLDE
#define SRLEN

Ox01
Ox02
Ox04
Ox10
Ox20
Ox80

/* missing address mark */
/* write protect signal detected */
/* couldn't find sector, or couldn't read ID */
/* did not receive data in time */
/* data field or ID field CRC error */
/* tried to access sector at end of cylinder */

/* define status register 2 bit values */
#define SR2_MD
#define SR2_BC
#define SR2_8N
#define SR2_SH
#define SR2_WC
#define SR2_DD
#define SR2_CM

Ox01
Ox02
Ox04
Ox08
Ox10
Ox20
Ox40

/* missing address mark in data field */
/* bad cylinder */
/* scan command could not find a sector */
/* scan equal hit */
/* wrong cylinder */
/* CRC error in data field */
/* deleted data address mark found */

/* define status register 3 bit values */
#define SR3_USO
#define SR3_US1
#define SR3_US2
#define SR3_US3
#define SR3_HD
#define SR3_TS
#define 8R3_TO
#define SR3_RDY
#define SR3_WP
#define SR3_FT

OxOO
OxOl
Ox02
Ox03
Ox04
Ox08
Oxl0
Ox20
Ox40
Ox80

/* unit select - drive 0 */
/* unit select - drive 1 */
/* unit select - drive 2 */
/* unit select - drive 3 */
/* head address */
/* drive signal - two side */
/* drive signal - track 0 */
/* drive signal - ready */
/* drive signal - write protect */
/* drive signal - FAULT */

Diskette Drive Controller . Programming Example

11- 29

/* define base values of fdc commands */
#define FDC_RD
#define FDC_RDD
#define FDC_WD
#define FDC_WDD
#define FDC_RT
#define FDC_ID
#define FDC_FT
#define FDC_SE
#define FDC_SLE
#define FDC_SHE
#define FDC_RECAL
#define FDC_SIS
#define FDC_SPE
#define FDC_SDS
#define FDC_SEEK
#define FDC_MT
#define FDC_MFM
#define FDC_SK

Ox06
OxOc
OxOS
Ox09
Ox02
OxOa
OxOd
Ox 11
Ox19
Oxld
Ox07
Ox08
Ox03
Ox04
OxOf
Ox80
Ox40
Ox20

/* read data */
/* read deleted data */
/* write data */
/* write deleted data */
/* read track */
/* read ID */
/* format track */
/* scan equal */
/* scan low or equal */
/* scan high or equal */
/* recalibrate drive */
sense
interrupt status */
/*
/* specify */
/* sense drive status */
/* seek */
/* multi-track */
/* modified frequency modulation */
/* skip deleted data address mark */

/***********************************************************************/
/* define some general constants
*/
/***********************************************************************/
#define RETRY_COUNT 4

/* maximum retries */

/***********************************************************************/
/* define some error codes
*/
/***********************************************************************/
#define ERR_FATAL
#define ERR_FAT_RD
#define ERR_FAT_WR
#define ERR_TO
#define ERR_DNR
#define ERR_RECAL
#define ERR_SEEK

11- 30

Oxffff
Oxfffe
Oxfffd
Oxfffc
Oxfffb
OxOOOl
OxOOO2

/* fatal error of unknown origin */
/* fdc was expecting write not read */
/* fdc was expecting read not write */
/* time out error */
/* drive not ready */
/* recalibrate error */
/* seek error */

Diskette Drive Controller . Programming Example

/***********************************************************************/
/* declare structures used in diskette controller example
*/
/***********************************************************************/
typedef struct
{

unsigned char dccr;
/* diskette controller control register */
unsigned char reserved1;
/* I/O space not used by controller */
unsigned char fdc_stat; /* diskette controller main status register */
unsigned char fdc_data;
/* diskette controller data register */
unsigned char reserved2;
/* I/O space not used by controller */
unsigned char dtr;
/* read <------- diskette change register */
/* write ---> data transfer rate register */
} FOC;
#define FOG_BASE (FOG *) Ox03F2

/* base address of FOG structure */

typedef struct
{

unsigned char mt;
unsigned char mfm;
unsigned char sk;
unsigned char last_cmd;
int busy;
int retry;
unsigned char dccr;
unsigned char dtr;
int hsd;
int msd;
int mod;
unsigned char ds;
unsigned char c;
unsigned char h;
unsigned char r;
unsigned char n;
unsigned char eot;
unsigned char sgpl;
unsigned char fgpl;
unsigned char sc;
unsigned char d;
unsigned char dtl;
unsigned char stp;
unsigned char srt;
unsigned char hIt;
unsigned char hut;
unsigned char nd;
} FOC_CMO;

/* multi-track */
/* mfm/fm */
/* skip */
/* last command sent to fdc */
/* busy flag */
/* retry count */
/* dccr contents */
/* data transfer rate */
/* head settle delay */
/* motor start up delay */
/* motor off delay */
/* drive select 0-3 */
/* cylinder number */
/* head side */
/* sector number */
/* bytes per sectors */
/* end of track */
sector
gap length */
/*
format
gap length */
/*
/* sector count */
/* format fill byte */
/* data length */
/* scan skip sector flag */
/* step rate time */
/* head load time */
/* head unload time */
/* non-OMA mode */

Diskette Drive Controller· Programming Example

11- 31

typedef struct
{

unsigned char mt;
unsigned char mfm;
unsigned char sk;
unsigned char dtr;
int hsd;
int msd;
unsigned char c;
unsigned char h;
unsigned char r;
unsigned char nj
unsigned char eotj
unsigned char sgpl;
unsigned char fgpl:
unsigned char sc:
unsigned char dtl:
unsigned char srt:
unsigned char hIt:
unsigned char hut:
} FDD:

1* multi-track *1
1* mfm/fm *1
1* skip *1
1* data transfer rate *1
1* head settle delay *1
1* motor start up delay *1
1* cylinder number *1
1* head side *1
1* sector number *1
1* bytes per sectors *1
1* end of track *1
1* sector gap length *1
1* format gap length *1
1* sector count *1
1* data length *1
1* step rate time *1
1* head load time *1
1* head unload time *1

typedef struct
{

unsigned char stOj
unsigned char stl;
unsigned char st2:
unsigned char st3;
unsigned char c;
unsigned char h;
unsigned char r;
unsigned char n;
unsigned char pcnj
unsigned int error:
unsigned char change;
} FDC_RESULTj

11- 32

1* status register o *1
1* status register 1 *1
1* status registex' 2 *1
1* status register 3 *1
1* cylinder number *1
1* head side *1
1* sector number *1
1* bytes per sectors *1
1* present cylinder number *1
1* error code/status *1
1* diskette change register *1

Diskette Drive Controller - Programming Example

/***********************************************************************/
/* declare some external timers

/***********************************************************************/
extern int head_settle;
extern int motor_flag;

/* head settle and motor startup timer */
/* automatic motor shut off timer */

/***********************************************************************/
/* declare space for fdc parameter data

/***********************************************************************/
FDC_CMD fdc_cmd =
{

OxOO,
FDC_MFM,
OxOO,
OxOO,
FALSE,
OxOO,
OxOO,
DTR_600,
6,

128,
612,
OxOO,
OxOO,
OxOO,
OxOl,
Ox02,
Oxl0,
Oxlb,
Ox64 ,
OxOf,
Oxf6,
Oxff,
OxOO,
OxOd,
Ox32,
Ox08,
OxOO,

/* not multi-track to start */
/* always mfm */
/* not skipping */
/* no last command yet */
/* not busy yet */
/* current retries */
/* nothing enabled until fdc is reset */
/* data transfer rate is 600 Kbits */
/* 3.90626 ms * 6 = 19.5312 ms = head settle delay */
/* 3.90626 ms * 128 = 500 ms motor startup delay */
/* 3.90625 ms * 612 = 2 seconds motor off delay */
/* no drive selected */
/* cylinder 0 to start */
/* head zero to start */
/* sector 1 to start */
/* 612 bytes per sectors */
/* end of track at sector 16 */
/* sector gap length */
/* format gap length */
/* 16 sectors per track */
/* format fill byte */
/* data length */
/* not skipping sectors during scan */
/* 3 ms step rate (1 - 16 me in 1 ms increment) OxOf = 1 ms */
/* 60 ms head load time ( OxOl = 2 ms, Ox02 = 4 ms ... ) */
/* 128 me head unload time ( OxOl = 16 ms, Ox02 = 32ms ... ) */
/* select dma mode (OxOO ~ dma mode, OxOl = non-dma mode) */

};

FDD fdd[2];
FDC_RESULT fdc_result;

/* place to store diskette parameters */

/* place to store result and error codes */

Diskette Drive Controller· Programming Example

11- 33

/***********************************************************************/
/* motor_off() - turn diskette drive motors off
*/
/***********************************************************************/
motor_off 0
{

FDC *pfdc = FDC_BASE;
int intr_flag;

/* to hold CPU IF state */

fdc_cmd.dccr t=
(DRVA_MOTOR 1 DRVB_MOTOR);
/* both motors off */
outp(tpfdc->dccr. fdc_cmd.dccr);
1* turn them off *1
intr_flag = int_off();
/* .no interrupts please */
motor_flag = 0;
1* clear motor timer *1
int_on(intr_flag);
/* allow interrupts */
}

1***************************************************** ******************/
/* select() - select the desired drive and turn on motor
*/
/***********************************************************************/
selectO
{

FDC *pfdc = FDC_BASE;
int intr_flag;

/* to hold CPU IF state */

if«fdc_cmd.dccr t DRV_SEL) != fdc_cmd.ds II
(fdc_cmd.dccr t (DRVA_MOTOR I DRVB_MOTOR»

/* if not current */
0)/* all motors off */

{

fdc_cmd.dccr t=
DRV_SEL;
/* deselect drives */
fdc_cmd.dccr 1= fdc_cmd.ds;
1* select drive */
fdc_cmd.dccr t=
(DRVA_MOTOR 1 DRVB_MOTOR);
/* both motors off */
if(!fdc_cmd.ds) fdc_cmd.dccr 1= DRVA_MOTOR;
/* desired motor on */
else fdc_cmd.dccr 1= DRVB_MOTOR;
outp(tpfdc->dccr. fdc_cmd.dccr);
/* write the register */
intr_flag = int_off();
/* no interrupts please */
motor_flag = 0;
/* clear motor timer */
int_on(intr_flag);
1* allow interrupts */
}
i f (!motor3lag)
{

head_settle = fdc_cmd.msd;
while (head_settle)

/* has motor stopped ? */
/* head settle timer to time start up */
/* wait until motor is up to speed */

}

intr_flag = int_off();
motor_flag = fdc_cmd.mod;
int_on(intr_flag);

/* no interrupts please */
/* write the motor off delay time */
1* allow interrupts */

}

11- 34

Diskette Drive Controller . Programming Example

/ •••• *••••••••••••••••••••••••••••••••• **.* •• *•••• ********.**.**.*******/
*/

/. fdc_in() - read data from fdc data register

/***********************************************************************/
fdc_inO
{

FOC *pfdc = FOC_BASE;
int i;
bead_settle = 2;
/* clk cycle
i = inp(tpfdc->fdc_stat);
wbile(l(i t RQM»

3.9 ms, must read in 2 cycles */
/* read fdc status register */
/* fdc ready ? */

{

if(lbead_settle)

/* time out error ? */

{

fdc_result.error
return;

ERR_TO;

/* mark error */

}

else i

= inp(tpfdc->fdc_stat);

/* read fdc status register */

}

i f (i t OIO_RO)

return(inp(tpfdc->fdc_data»;
else fdc_result.error = ERR_FAT_RO;

/* data direction = cpu read ? */
/* return data read */
/* mark fatal error */

}

Diskette Drive Controller . Programming Example

11- 35

/***********************************************************************/
/* fdc_outO - write data to fdc data register
*/
/***********************************************************************/
fdc_out(value)
unsigned char value;

/* value to write to fdc data register */

{

FOe *pfdc
int i;
head_settle = 2;
/* clk cycle
i = inp(&pfdc->fdc_stat);
while(l(i & RQM»

3.9 ms, must read in 2 cycles */
/* read fdc status register */
/* fdc ready ? */

{

if(lhead_settle)

/* time out error ? */

{

fdc_result.error = ERR_TO;
return;

/* mark error */

}

else i = inp(&pfdc->fdc_stat);

/* read fdc status register */

if«i & DIO_RD) == 0)
outp(&pfdc->fdc_data, value);
else fdc_result.error = ERR_FAT_WR;

/* data direction = cpu write? */
/* write fdc data register */
/* mark fatal error */

}

/***********************************************************************/
/* waitcc() - wait for command to complete
*/
/***********************************************************************/
waitcc()
{

while (fdc_cmd.busy)

/* wait until command complete */

{
i f ( ! motor 3lag)
{

/* time out ? */

fdc_result.error = ERR_TO;
/* time out error */
return;
}
/* do something useful while waiting, like check date */
chk_dtO;
/* and time for update. ROM BIOS does an INT 15H */
}

11 - 36

Diskette Drive Controller . Programming Example

if(fdc_result.error) return;
switch(fdc_cmd.last_cmd)

/* error ? */
/* discover last command issued */

{

case FOC_RECAL:
case FOC_SEEK:
head_settle = fdc_cmd.hsd;
while (head_settle)
fdc_cmd.last_cmd = FOC_SIS;
fdc_out(FOC_SIS);
if(fdc_result.error) return;
fdc_result.stO = fdc_in();
if(fdc_result.error) return;
fdc_result.pcn = fdc_in();
if(fdc_result.error) return;
break;

/* recalibrate ? */
/* seek ? */
/* set head settle delay timer */
/* wait for head settle to time out */
/* set last command issued */
/* sense interrupt status */
/* error ? */
/* read stO results */
/* error ? */
/* read present cylinder number */
/* error ? */

default:/* all other commands except FDC_SPE, FOC_SIS, and FDC_SDS */
fdc_result.stO = fdc_in();
/* read stO results */
if (fdc_result.error) return;
/* error ? */
fdc_result.stl = fdc_in();
/* read stl results */
if(fdc_result.error) return;
/* error ? */
fdc_result.st2 = fdc_in();
/* read st2 results */
if(fdc_result.error) return;
/* error ? */
fdc_result.c = fdc_in();
/* read cylinder results */
if (fdc_result.error) return;
/* error ? */
fdc_result.h = fdc_in();
/* read head results */
if(fdc_result.error) return;
/* error ? */
fdc_result.r = fdc_in();
/* read sector results */
if(fdc_result.error) return;
/* error ? */
fdc_result.n = fdc_in();
/* read bytes/sector results */
if (fdc_result. error) return;
/* error ? */
break;
}

}

Diskette Drive Controller . Programming Example

11- 37

/***********************************************************************/
/* specify() - set the diskette drive characteristics

/***********************************************************************/
specify 0
{

FOC *pfdc = FOC_BASEj
unsigned char UCj

/* temporary variable */

outp(tpfdc->dtr. fdc_cmd.dtr)j
/* set data transfer rate */
outp(tpfdc->dccr. fdc_cmd.dccr)j
/* set control register */
fdc_cmd.last_cmd = FOC_SPEj
/* last command is specify */
fdc_out(FOC_SPE)j
/* issue specify command */
if(fdc_result.error) returnj
/* error ? */
uc = fdc_cmd.srt « 4;
/* specify step rate */
uc 1= fdc_cmd.hutj
/* specify head unload time */
fdc_out(uc)j
/* issue step rate and head unload time */
if(fdc_result.error) returnj
/* error ? */
uc = fdc_cmd.hlt « 1j
/* specify head load time */
uc 1= fdc_cmd.nd;
/* specify dma mode */
fdc_out(uc)j
/* issue head load time and dma mode */
}

11- 38

Diskette Drive Controller - Programming Example

/***********************************************************************/
/* fdc_issue() - issue all fdc commands except specify and sis
*/
/***********************************************************************/
fdc_issue(cmd, drv)
int cmd;
int drv;

/* desired command */
/* desired drive 0 or 1 */

{

FOC *pfdc = FOC_BASE;
char oline[20];
fdc_cmd.ds = drv;
/* indicate the drive */
select(drv);
select appropriate drive */
fdc_out(FOC_SOS);
/* sense drive status */
if(fdc_result.error) return;
/* error ? */
fdc_out«fdc_cmd.h « 2) I fdc_cmd.ds);
/* second byte of SOS */
if(fdc_result.error) return;
/* error ? */
fdc_result.st3 = fdc_in();
/* read st3 results */
if(fdc_result.error) return;
/* error ? */
sprintf(oline, "%04x %04x", pfdc, kpfdc->dtr);
disp_str(16, 1, oline);
fdc_result.change
inp(kpfdc->dtr) k Ox80;
/* read disk change reg */
if(fdc_result.st3 k SR3_ROY)
/* drive ready ? */
{

fdc_cmd.last_cmd = cmd;
switch(cmd)

/* set last command issued */

{

case FOC_SOS:
return;
break;
case FOG_RECAL:
fdc_out(cmd);
if (fdc_result. error) return;
fdc_out(fdc_cmd.ds);
break;

/* recalibrate ? */
/* issue byte 1 */
/* error ? */
issue
byte 2 */
/*

case FOC_SEEK:
fdc_out(cmd);
if(fdc_result.error) return;
fdc_out«fdc_cmd.h « 2) I fdc_cmd.ds);
if(fdc_result.error) return;
fdc_out(fdc_cmd.c) ;
break;

/* seek ? */
issue
byte 1 */
/*
/* error ? */
/* issue byte 2 */
/* error ? */
/* issue byte 3 */

Diskette Drive Controller - Programming Example

11- 39

case FDC_ID:
fdc_out(fdc_cmd.mfm I cmd);
if (fdc_resul t. error) return;
fdc_out«fdc_cmd.b: « 2) I fdc_cmd.ds);
break;

/* read II)" ? */
/* issue byte 1 */
/* error ? */
/* issue byte 2 */

case FDC]T:
fdc_out{fdc_cmd.mfm I cmd);
if(fdc_result.error) return;
fdc_out«fdc_cmd.h « 2) I fdc_cmd.ds);
if (fdc_resul t . error) return;
fdc_out(fdc_cmd.n);
if(fdc_result.error) return;
fdc_out(fdc_cmd.sc);
if(fdc_result.error) return;
fdc_out(fdc_cmd.fgpl);
if(fdc_result.error) return;
fdc_out(fdc_cmd.d);
if(fdc_result.error) return;
break;

/* format track ? */
/* issue byte 1 */
/* error ? */
issue
byte 2 */
/*
/* error ? */
/* issue byte 3 */
/* error ? */
issue
byte 4 */
/*
/* error ? */
/* issue byte 6 */
/* error ? */
/* issue byte 6 */
/* error ? */

case FDC_RD:
/* read data? */
case FDC_RDD:
/* read deleted data? */
case FDC_WD:
/* write data ? */
case FDC_WDD:
/* write deleted data */
fdc_out(fdc_cmd.mt I fdc_cmd.mfm I fdc_cmd.sk I cmd);/* byte 1 */
if(fdc_result.error) return;
/* error? */
fdc_out«fdc_cmd.h« 2) I fdc_cmd.ds);
/* issue byte 2 */
if(fdc_l"esult.error) return;
/* error? */
fdc_out(fdc_cmd.c);
/* issue byte 3 */
if(fdc_result.error) return;
/* error? */
fdc_out(fdc_cmd.h);
/* issue byte 4 */
if(fdc_result.error) return;
/* error? */
fdc_out(fdc_cmd.r);
/* issue byte 6 */
if(fdc_result.error) return;
/* error? */
fdc_out(fdc_cmd.n);
/* issue byte 6 */
if(fdc_result.error) return;
/* error? */
fdc_out(fdc_cmd.eot);
/* issue byte 7 */
if(fdc_result.error) return;
/* error? *1
fdc_out(fdc_cmd.sgpl);
/* issue byte 8 */
if(fdc_result.error) return;
/* error? */
fdc_out(fdc_cmd.dtl);
/* issue byte 9 */
break;

11 - 40

Diskette Drive Controller -Programming Example

case FOe_RT:
fdc_out(fdc_cmd.mfm I fdc_cmd.sk I cmd);
if(fdc_result.error) return;
fdc_out«fdc_cmd.h « 2) I fdc_cmd.ds);
if(fdc_result.error) return;
fdc_out(fdc_cmd.c);
if(fdc_result.error) return;
fdc_out(fdc_cmd.h);
if(fdc_result.error) return;
fdc_out(fdc_cmd.r);
if(fdc_result.error) return;
fdc_out(fdc_cmd.n);
if(fdc_result.error) return;
fdc_out(fdc_cmd.eot);
if(fdc_result.error) return;
fdc_out(fdc_cmd.sgpl);
if(fdc_result.error) return;
fdc_out(fdc_cmd.dtl);
break;

/* read a track 1 */
/* issue byte 1 */
/* error 1 */
/* issue byte 2 */
/* error 1 */
/* issue byte 3 */
/* error 1 */
/* issue byte 4 */
/* error 1 */
/* issue byte 5 */
/* error 1 */
/* issue byte 6 */
/* error 1 */
/* issue byte 7 */
/* error 1 */
/* issue byte 8 */
/* error 1 */
/* issue byte 9 */

case FOe_SE:
/* scan equal 1 */
case FOe_SHE:
/* scan high or equal? */
case FOe_SLE:
/* scan low or equal 1 */
fdc_out(fdc_cmd.mt I fdc_cmd.mfm I fdc_cmd.sk I cmd);/* byte 1 */
if(fdc_result.error) return;
/* error 1 */
fdc_out«fdc_cmd.h « 2) I fdc_cmd.ds);
/* issue byte 2 */
if(fdc_result.error) return;
/* error? */
fdc_out(fdc_cmd.c);
/* issue byte 3 */
if(fdc_result.error) return;
/* error 1 */
fdc_out(fdc_cmd.h);
/* issue byte 4 */
if(fdc_result.error) return;
/* error 1 */
fdc_out(fdc_cmd.r);
/* issue byte 5 */
if(fdc_result.error) return;
/* error 1 */
fdc_out(fdc_cmd.n);
/* issue byte 6 */
if(fdc_result.error) return;
/* error 1 */
fdc_out(fdc_cmd.eot);
/* issue byte 7 */
if(fdc_result.error) return;
/* error? */
fdc_out(fdc_cmd.sgpl);
/* issue byte 8 */
if(fdc_result.error) return;
/* error 1 */
fdc_out(fdc_cmd.stp);
/* issue byte 9 */
break;
}
}

Diskette Drive Controller - Programming Example

11- 41

else
{

fdc_result.error
return;

/* drive not ready error */

}

if(fdc_result.error) return;
fdc_cmd.buay = TRUE;
waitccO;
disp_status(&fdc_result, &fdc_cmd);

/* error ? */
/* wait for command complete */
/* display result status */

}

/***********************************************************************/
/* fdc_init() - initialize diskette controller
*/
/***********************************************************************/
fdc3'nitO
{

FDC *pfdc = FDC_BASE;
int intr_flag;
intr_flag = int_off();
outp(&pfdc->dccr, DMA_INT_ON);
/* reset the fdc */
fdc_cmd.dccr = DMA_INT_ON I FDC_ON;
/* fdc not reset */
outp(&pfdc->dccr, fdc_cmd.dccr);
/* allow communications */
iv_init(OxOe);
/* initialize the interrupt vector */
int_on(intr_flag);
imask(O, 6, 1);
/* enable PIC input */
}

/***********************************************************************/
/* fdc_rest() - restore diskette controller and interrupt vector
*/
/***********************************************************************/
fdc_restO
{

FDC *pfdc = FDC_BASE;
outp(&pfdc->dccr, 0);
imask(O, 6, 0);
fdc_cmd.dccr = DMA_INT_ON I FDC_ON;
outp(&pfdc->dccr, fdc_cmd.dccr);
iv_rest(OxOe);

/* reset the fdc */
/* disable PIC input */
/* fdc not reset */
/* allow communications */
/* restore the interrupt vector */

}

11- 42

Diskette Drive Controller . Programming Example

/***********************************************************************/
/* fdc_int_hand() - fdc interrupt handler
*/
/***********************************************************************/
fdc_int_hand 0
{

fdc_cmd.busy
eoi(O);

FALSE;

/* no longer busy */

}

/***********************************************************************/
/* fdc() - execute diskette controller examples
*/
/***********************************************************************/
fdcO
{

static MESSAGE mfdc []

/* fdc menu */

{

{
{
{
{
{
{
{
{
{

3,
5,
6,
7,

10,
12,

27,
27,
27,
27,
27,
27,
27,
27,

"Oiskette Controller Example" },
"Fl. Turn drive A motor on" }.
"F2. Turn drive A motor off" },
"F3. Recalibrate" },
"F4. Seek track 40" },
"F5. Format diskette" },
"F6. Read 10" },
"FlO. Return to Main menu" },

o },

8,
9,

};

unsigned char tmp;
unsigned char sum;
char line[512];
char oline[512];
int i;
int r;
FOC *pfdc = FOC_BASE;
char *pc;
char far *fpc = oline;
long 1 = (long)fpc;
long 11;
long 12;
int pr;
int pa;

/* to hold CMOS byte read */
/* to hold calculated checksum */
/* to hold input line */
/* to hold output line */
/* to hold menu selection */
/* temp value */

#define ROW 16
#define COL 17

Diskette Drive Controller· Programming Example

11- 43

diBp_menu(mfdc):
11 - 1 i OxOOOOffff;
12 - 1 » 16;
12 «- 4;
1 - 12 + 11;
11 = 1 » 16:
pr - (tnt)11;
11 - 1 i OxOOOOffff;
pa - (tnt) 11;
BpecifyO;
line[O] - 0:
while (1)

/* diBplay the fdc menu */
/* build addre.a of buffer for DMA controller */

/* pointer to buffer */
/* page regiBter value */
/* null terminated */
/* forever (Bee FlO) */

{

diBp_BtatuB(ifdc_reBult, ifdc_cmd);
/* diBplay reBult BtatuB */
line[O] - set_fkey();
/* get • function key for menu Belection */
Bwitch(line[O])
/* determine menu Belection */
{

caBe Fl:
fdc_cmd.dB - 0;
BelectO;
break;

/* turn drive motor on */

caBe F2:
motor_off 0 ;
break;

/* turn drive motor off */

caBe F3:
aelect(O);
fdc_iBsue(FDC_RECAL, 0);
fdc_iBBue(FDC_RECAL. 0);
fdc_i.Bue(FDC_ID. 0);
break:

/* recalibrate drive */

caBe F4:
Be1ect(O);
fdc_cmd.c = 40;
fdc_iBBue(FDC_SEEK. 0);
fdc_iBBue(FDC_ID. 0);
break;

/* Beek to track 40 */

11- 44

Diskette Drive Controller . Programming Example

case F5:
/* hard format a diskette - interleave - 1 */
select(O);
fdc_issue(FDC_RECAL, 0);
fdc_issue(FDC_RECAL, 0);
fdc_issue(FDC_ID, 0);
for{i = 0; i < 80; i++)
{

fdc_cmd.c = i;
fdc_issue(FDC_SEEK, 0);
fdc_cmd.h = 0;
pc = oline;
for(r = 1; r < 16; r++)

/* side 0 */
/* build sector table */

{

*pc++ ... (char)!;
*pc++
'\000' ;
*pc++
{char)r;
*pc++
'\002' ;
}

r = (int)(l » 16);
dma_transfer(2, pr, pa, 60, 8);
fdc_issue(FDC_FT, 0);
fdc_cmd.h = 1;
pc = oline;
for(r = 1; r < 16; r++)

/* setup DMA */
/* format track */
/* side 1 */
/* build sector table */

{

*pc++
(char)! ;
*pc++ = '\001' ;
*pc++
(char)r;
'\002' ;
*pc++
}

r = (int)(1 » 16);
dma_transfer{2, pr, pa, 60, 8);
fdc_issue{FDC_FT, 0);

/* setup DMA */
/* format track */

}

break;

Diskette Drive Controller - Programming Example

11- 45

case F6:
select(O);
fdc_issue(FDC_RECAL. 0);
fdc_issue(FDC_RECAL. 0);
fdc_issue(FDC_ID. 0);
for(i = 0; i < 80; i++)

/* read any sector ID */

{

fdc_cmd.c = i;
fdc_issue(FDC_SEEK. 0);
fdc_cmd.h = 0;
fdc_issue(FDC_ID. 0);
fdc_cmd.h = 1;
fdc_issue(FDC_ID. 0);
}

break;
case FlO:
return;

/* return to caller (main menu) */

}
}
}

11- 46

Diskette Drive Controller . Programming Example

disp_status(pres, pcmd)

/* display status */

FOC_RESULT *pres;
FOC_CMO *pcmd;
{

char oline[60];
sprintf(oline, "Error status
Ox%04x", pres->error);
disp_str(19, 1, oline);
sprintf(oline, "Status reg 0
Ox%02x" , pres->stO);
disp_str(20, 1, oline);
sprintf(oline, "Status reg 1
OxYo02x", pres->stl);
disp_str(21 , 1, oline);
sprintf(oline, "Status reg 2
OxYo02x", pres->st2);
disp_str(22 , 1, oline);
sprintf(oline, "Status reg 3
Ox%02x", pres->st3);
disp_str(23, 1, oline);
sprintf(oline, "Present Cyl Num: Ox%02x", pres->pcn);
disp_str(24 , 1, oline);
sprintf(oline, "Change reg:
Ox%02x", pres->change);
disp_str(19, 41, oline);
sprintf(oline, "Cylinder (C):
Ox%02x", pres->c);
disp_str(20, 41, oline);
sprintf(oline, "Head (H):
Ox%02x", pres->h);
disp_str(21 , 41, oline);
sprintf(oline, "Sector (R): Ox%02x", pres->r);
disp_str(22, 41, oline);
sprintf(oline, "Sectors per track (N): Ox%02x", pres->n);
disp_str(23 , 41, oline);
sprintf(oline, "Last command: Ox%04x", pcmd->last_cmd);
disp_str(24 , 41, oline);
}

Diskette Drive Controller . Programming Example

11- 47

Chapter 12
Hard Disk Drive Controller
Introduction
The hard disk controller provides an interface between a hard disk drive and
the workstation microprocessor. The hard disk controller supports the following
features:
•
•
•
•
•

A 16-bit data path and an 8-bit input/output (1I0) path
ECC correction
Programmed 110 data transfers
Field formatting with unlimited sector interleave
Drives with a maximum of 16 heads and 1024 cylinders

Hard Disk Controller Registers
The hard disk controller has 13 registers that control hard disk operations and
provide status information. These registers are mapped to a set of primary or
secondary 110 addresses. Table 12-1 lists the registers and the corresponding
primary and secondary 110 addresses.

Hard Disk Drive Controller - Hardware Description

12 - 1

Table 12-1

Hard Disk Controller Registers

Primary
Address

Secondary
Address

RfW

OlFOH
OlFIH
OlFIH
OlF2H
OlF3H
OlF4H
01F5H
01F6H
OlF7H
OlF7H
03F6H
03F6H
03F7H

O170H
Ol71H
Ol71H
O172H
O173H
O174H
0175H
O176H
Ol77H
O177H
0376H
0376H
0377H

R/W
W
R
R/W
R/W
R/W
R/W
R/W
W
R
W
R
R

Data register (16 bits)
Write Precompensation Cylinder
Error Register
Sector Count
Sector Number
Cylinder Number - Low Byte
Cylinder Number - High Byte
SDH (sector size, drive, and head)
Command Register
Status Register
Hard Disk Register
Alternate Status Register
Digital Input Register

12 - 2

Hard Disk Drive Controller - Hardware Description

Data Register (OlFOH/0170H)
15

Bit

R/W Description

15-0

RlW DATA

:
1

The data register provides a I6-bit data path to the sector buffer. This register
is accessible only during execution of a read or write command.
Except for the four ECC bytes of a read long or write long command, all data
transfers are 16-bit transfers.
After transferring the data of a read long or write long command. the four
ECC bytes are transferred one byte at a time. The ECC bytes are transferred
through the high byte. The hard disk controller requires a minimum of 2 p,s
between ECC byte transfers. To transfer an ECC byte, the data request {DRQl
status bit {status register bit 31 must be set. The status register is defined later
in this chapter.

Hard Disk Drive Controller - Hardware Description

12 - 3

Write Precompensation Register (OlFIH/0171H)
765

Bit

RIW Description

7-0

12 - 4

432

This register specifies the cylinder at which the hard disk controller begins applying write precompensation. The value written to
this register is the desired cylinder number divided by 4.

Hard Disk Drive Controller - Hardware Description

Error Register (OlFIH/0171H)
7

BAD
BLOCK

ECC
ERROR

DETEct

ABORTED TRACK 0 DAM
COHHAND ERROR NOT
DETECT
FOUND

ID
NOT
FOUND
0

Bit

RIW Description

BAD BLOCK DETECT
0= No error
1 = The controller read a sector 10 field that contained a bad
block mark

ECC ERROR
0= No error
1 = An ECC syndrome error was detected

Always 0

10 NOT FOUND
0= No Error
1 = The hard disk controller failed to find the desired cylinder,
head, sector. or size parameter within eight revolutions of the
disk, or an 10 field CRC error has occurred.

Always 0

ABORTED COMMAND DETECT
0= No error
1 = The hard disk controller aborted a command
If a command is issued while the status signal, DRIVE READY L,
is inactive or the status signal, WRITE FAULT L is active, the
hard disk controller sets this bit.

TRACK 0 ERROR
0= No error
1 = The hard disk controller executed a restore command, issued
2047 step pulses, and did not detect track O.

DAM NOT FOUND - Data Address Mark Not Found
0= No error
1 = The hard disk controller read the correct sector 10 field, but
it did not contain a data address mark.

Hard Disk Drive Controller - Hardware Description

12 - 5

For the following conditions, the error register contains valid data:
•

After a command completion interrupt, if the status register error bit
fbit 0) equals 1, this register indicates the specific error condition.

•

On power-up or receiving a diagnose command, the hard disk controller
executes a set of diagnostic tests. On completion of those tests, the hard
disk controller places a result code in this register. The result code is
one of the codes listed in Table 12-2. For this condition, the status register error bit fbit 0) is ignored.

Table 12-2 Hard Disk Controller Diagnostic Result Codes
Value

Meaning

01H

No error

02H
03H

WD1015/WD2010 controller error
Sector Buffer RAM data error

04H
05H

WD1015/WDllCOOA-22 Register access error
WD1015 ROM checksum or RAM data error

12 - 6

Hard Disk Drive Controller - Hardware Description

Sector Count Register (OlF2H/0172H)
7

Bit

R/W Description

7-0

R/W The sector count for an operation

A value of OOH indicates a 256 sector transfer.
For a read, write, or read verify command, this register specifies the number of
sectors transferred. For the format command, this register specifies the
number of sectors to format. During a multiple sector operation. after each
sector is transferred or formatted, the hard disk controller decrements the
sector count.

Sector Number Register (OlF3H/0173H)
7

Bit

R/W Description

7-0

R/W The first sector for an operation

For a read, write, read verify, or format command, this register specifies the
first sector of an operation. During multiple sector operations, after each sector
is transferred or formatted, the hard disk controller increments the sector
number.

Hard Disk Drive Controller - Hardware Description

12 - 7

Cylinder Number Low Register (OlF4H/0174H)
7

Bit

R/W Description

7-0

R/W Lower 8 bits of the lO-bit cylinder number

This register specifies the 8 least significant bits of the 10-bit cylinder
number. The cylinder number high register specifies the 2 most significant
bits.

Cylinder Number High Register (OlF5H/0175H)
7

CYLIND~
I
I I I I I I
0

Bit

RIW Description

7-2

R/W Always 0

1-0

R/W Upper 2 bits of the 10-bit cylinder number

0
NUMBER

(HIGB,BYTE)

This register specifies the 2 most significant bits of the to-bit cylinder
number. The cylinder number low register specifies the 8 least significant
bits.

12 - 8

Hard Disk Drive Controller - Hardware Description

SDH Register (OlF6H/0176H)
7

654

I~A I~ I
SIZE

Bit

RIW Description

RJW ECC SELECT

: nAD~:

0= CRC used to check the data field of a sector
1 = ECC used to check the data field of a sector (ROM BIOS
requires ECC)
6

RJW Always 0

RlW DATA SIZE
0= 256 byte records (read operations only)
1 = 512 byte records

RlW DRIVE SELECT
0= Hard disk drive 0 selected
1 = Hard disk drive 1 selected

3-0

RJW HEAD SELECT
The binary value in bits 3-0 selects the corresponding head. To use
bit 3 of this field, the ENABLE-HEAD-SELECT-BIT-3 (bit 3 of
the hard disk register) must equal 1. Otherwise, bit 3 is ineffective
and bits 2-0 have a range of 0-7.

Hard Disk Drive Controller - Hardware Description

12 - 9

Command Register (OlF7H/0177H)
7

Bit

R/W Description

7-0

Hard disk controller command codes

When command codes are written to this register, the hard disk controller executes the command immediately. If the hard disk controller is busy fstatus register bit 7 equals I}, command codes cannot be written to the command
register. When the hard disk controller detects a command error condition, the
hard disk controller aborts the command and sets the ABORTED COMMAND
DETECT bit ferror register bit 2}. Some of the common command error conditions are:
•
•
•
•

WRITE FAULT is active
DRIVE READY is inactive
SEEK COMPLETE is inactive
Command code was invalid

The hard disk controller has the following commands:

•
•
•
•
•
•
•
•

Restore
Seek
Read Sector
Write Sector
Format Track
Read Verify
Diagnose
Set Parameter

12 - 10

Hard Disk Drive Controller - Hardware Description

Restore Command
7

: I
Bit

Description

7-4

RESTORE COMMAND (Always 0001)

3-0

STEP RATE
0000 = 35.0 J,1S
0001 = 0.5 ms
0010 = 1.0 ms
0011 = 1.5 ms
0100 = 2.0 ms
0101 = 2.5 ms
0110 = 3.0 ms
0111 = 3.5 ms

1000 = 4.0 ms
1001 = 4.5 ms
1010 = 5.0 ms
1011 = 5.5 ms
1100 = 6.0 ms
1101 = 6.5 ms
1110 = 3.2 J,1S
1111= 16.0 J,1S

Until a terminating condition occurs, the hard disk controller issues step pulses
to the selected drive. The terminating conditions are:
•

The TRACK 0 signal from the drive becomes active, which indicates a
successful completion of the command. In this case, the hard disk controller sets SEEK COMPLETE (status register bit 4) to 1.

•

The hard disk controller issues 2047 step pulses, which causes a
TRACK 0 ERROR (error register bit 3).

•

The DRIVE READY signal becomes inactive, which causes an
ABORTED COMMAND DETECT (error register bit 2).

•

The WRITE FAULT signal becomes active, which causes an ABORTED
COMMAND DETECT (error register bit 2).

While a restore command is in progress, the SEEK COMPLETE signal from
the drive controls the step rate. Bits 3-0 set the implied seek step rate. On
termination of this command, the hard disk controller generates an interrupt to
the CPU.

Hard Disk Drive Controller - Hardware Description

12 - 11

Seek Command
7

:
Bit

Description

7-4

SEEK COMMAND (Always 0111)

3-0

STEP RATE
0000 = 35.0 p.s
0001 = 0.5 ms
0010 = 1.0 ms
0011 = 1.5 ms
0100 = 2.0 ms
0101 = 2.5 ms
0110 = 3.0 ms
0111 = 3.5 ms

1000 = 4.0 ms
1001 = 4.5 ms
1010 = 5.0 ms
1011 = 5.5 ms
1100 = 6.0 ms
1101 = 6.5 ms
1110 = 3.2 p.s
1111 = 16.0 p.s

Until a terminating condition occurs, the hard disk controller issues step pulses
to the selected drive. The terminating conditions are:
•

The SEEK COMPLETE signal from the drive becomes active, which indicates a successful completion of the command. In this case, the hard
disk controller sets SEEK COMPLETE (status register bit 4) to 1.

•

The DRIVE READY signal becomes inactive, which causes an
ABORTED COMMAND DETECT (error register bit 2).

•

The WRITE FAULT signal becomes active, which causes an ABORTED
COMMAND DETECT (error register bit 2).

The seek command moves the read/write heads to the cylinder specified by the
10-bit value in the registers cylinder low and cylinder high. Bits 3-0 set the
implied seek step rate and control the step rate of the seek command. After
the hard disk controller starts the seek, the hard disk controller generates an
interrupt to the CPU. This interrupt indicates that the hard disk controller is
ready to accept another command. It does not indicate that the seek is complete. To determine when the seek is complete, the application program or
driver must monitor status register bit 4. When status register bit 4 equals 1,
the seek is complete.
12 - 12

Hard Disk Drive Controller - Hardware Description

Read Sector Command
7

6
I

5
I

4
I

3
I

1
I

Description

7-2

READ SECTOR COMMAND (Always OOlOOO)

RETRIES
DISABLE

READ LONG
After transferring a sector of data. the hard disk controller
calculates and checks the data field ECC. If a correctable
error occurs, the hard disk controller sets CORRECTED
DATA (status register bit 2). If an uncorrectable error occurs,
the hard disk controller sets ECC ERROR (error register bit
6) and ERROR (status register bit OJ. If an uncorrectable
error occurs during a multiple sector read, the multiple sector
read is terminated.

1 =

READ
LONG
0

Bit

READ SECTOR COKKAND
0

The hard disk controller does not calculate the data field
ECC. After transferring a sector of data, the hard disk controller transfers the four data field ECC bytes. The four ECC
bytes are transferred one at a time in the high byte of the
word. Until DRQ (status register bit 3) equals 1. an ECC byte
is not ready for transfer. The hard disk controller requires at
least 2 ps between ECC byte transfers.

RETRIES DISABLE
Retries enabled
1 = Retries disabled

To read a sector from the hard disk. the hard disk controller must
first find the sector. To find the correct sector, the hard disk controller selects the indicated head. performs any implied seek, and
waits for the index pulse. On receipt of the index pulse. the hard
disk controller begins scanning the track for a valid sector ID field.
A valid sector ID field contains the cylinder, head, sector number,
and size information that the hard disk controller is searching for.
The hard disk controller counts each index pulse as an attempt to
read a valid sector ID.

Hard Disk Drive Controller - Hardware Description

12 - 13

Bit

Description

(Read Sector Command - cont.)

If retries are enabled and the hard disk controller fails to read a
valid ID field within ten attempts, the hard disk controller performs
an auto-seek and an auto-scan. If the hard disk controller fails to
read a valid ID field within an additional ten attempts, the hard
disk controller sets ID Not Found (error register bit 4) and ERROR
(status register bit 0).
If retries are disabled and the hard disk controller fails to read a
valid ID field within two attempts, the hard disk controller sets
ID Not Found (error register bit 4) and ERROR (status register
bit 0). Also. the hard disk controller does not perform an auto-seek
or an auto-scan.

The read sector command transfers the specified number of sectors from the
selected drive. If the heads are not positioned at the specified cylinder, the controller performs an implied seek to the proper cylinder. The step rate used is
that of the most recently executed restore or seek command. Multiple sector
reads can cross head and cylinder boundaries. If the DRIVE READY signal
becomes inactive, or the WRITE FAULT signal becomes active, the hard disk
controller terminates the command and sets ABORTED COMMAND DETECT
(error register bit 2) and ERROR (status register bit 0).
When each sector is stored in the sector buffer and ready to be read by the
CPU, the hard disk controller generates an interrupt request to the CPU. The
hard disk controller does not generate an interrupt request to indicate command completion.

12 - 14

Hard Disk Drive Controller - Hardware Description

Write Sector Command
7

6
I

4
I

3
I

VRITE SEcrOR COMMAND

Description

7-2

WRITE SECTOR COMMAND (Always 001100)

¥RITE
LONG

RETRIES
DISABLE

WRITE LONG
The hard disk controller calculates the data field ECC and appends the ECC to the data field.

o=
1 =

Bit

The hard disk controller does not calculate the data field
ECC. After accepting a sector of data, the hard disk controller accepts the four data field ECC bytes. The four ECC bytes
are transferred one at a time in the high byte of the word size
data register. Until DRQ (status register bit 3) equals 1, an
ECC byte is not ready for transfer. The hard disk controller
requires at least 2 ps between ECC byte transfers.

RETRIES DISABLE
Retries enabled
1 = Retries disabled
To write a sector from the hard disk, the hard disk controller must
first find the sector. To find the correct sector, the hard disk controller selects the indicated head, performs any implied seek, and
waits for the index pulse. On receipt of the index pulse, the hard
disk controller begins scanning the track for a valid sector 10 field.
A valid sector 10 field contains the cylinder, head, sector number,
and size information that the hard disk controller is searching for.
The hard disk controller counts each index pulse as an attempt to
read a valid sector 10.

U retries are enabled and the hard disk controller fails to read a
valid 10 field within ten attempts, the hard disk controller performs
an auto-seek and an auto-scan. If the hard disk controller fails to
read a valid 10 field within an additional ten attempts, the hard
disk controller sets 10 Not Found (error register bit 4) and ERROR
(status register bit 0).

Hard Disk Drive Controller - Hardware Description

12 - 16

Bit

Description

(Write Sector Command - cont.)

If retries are disabled and the hard disk controller fails to read a
valid ID field within two attempts. the hard disk controller sets
ID Not Found (error register bit 4) and ERROR (status register bit
0). Also. the hard disk controller does not perform an auto-seek or
an auto-scan.

The write sector command transfers the specified number of sectors to the selected drive. If the heads are not positioned at the specified cylinder. the controller performs an implied seek to the proper cylinder. The step rate used is
that of the most recently executed restore or seek command. Multiple sector
writes can cross head and cylinder boundaries. If the DRIVE READY signal
becomes inactive. or the WRITE FAULT signal becomes active. the hard disk
controller terminates the command and sets ABORTED COMMAND DETECT
(error register bit 2) and ERROR (status register bit 0).
After the write sector command has been issued. immediately write the first
sector of data to the data buffer (monitor DRQ. status register bit 3). When
each sector is written to the hard disk. the hard disk controller generates an
interrupt request to the CPU. The hard disk controller does not generate an
interrupt request to indicate command completion.

12 - 16

Hard Disk Drive Controller - Hardware Description

Format Track Command
7

Bit

Description

7-0

FORMAT TRACK COMMAND (Always 01010000)

Using data from the internal registers and the sector buffer, the format track
command formats a single track at the specified cylinder and head location.
Before formatting a hard disk, the SDH register must be loaded and a restore
command must be issued. Assuming that a series of sequential format track
commands are issued to format the hard disk, only one restore command is
required. Prior to each format track command, the sector count register must
be loaded with the number of sectors per track and the cylinder registers must
be loaded with the cylinder number.
Instead of providing normal read/write data, the sector buffer provides sector
header information. Also, the organization of this sector header information
specifies the sector interleave. Table 12-3 lists the data (in memory order) that
is required for an interleave factor of 2. The data transfer using this table is
256 words long. A bad block is specified by replacing the OOH (normal block
mark) with an SOH (bad block mark). The sector interleave table is loaded into
the sector buffer in the same manner as a sector write. That is, the format
track command is issued and the sector buffer is loaded immediately (monitor
DRQ, status register bit 3).
When a track has been formatted, the hard disk controller clears the sector
buffer to zeros and issues a command completion interrupt. Following the next
format track command, the sector buffer must be reloaded.
The hard disk controller does not produce any error reports for this command.

Hard Disk Drive Controller - Hardware Description

12 - 17

Table 12·3

Memory Image of a Sector Interleave Table

Offset

2·Byte Sequence
Sector
Sector
Number
Status (OOH = Good, SOH = Badl
(High Bytel
(Low Bytel

OOH
02H
04H
06H
08H
OAH
OCH
OEH
10H
12H
I4H
I6H
I8H
IAH
ICH
IEH
20H
22H

OIH
OAH
02H
OBH
03H
OCH
04H
ODH
05H
OEH
06H
OFH
07H
IOH
08H
llH
09H
FFH
FFH
FFH
FFH
FFH

FFH

12 - 18

OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
FFH
FFH
FFH
FFH
FFH

Hard Disk Drive Controller . Hardware Description

Read Verify Command
7

7 ~~ ~~ :

Bit

Description

7-1

READ VERIFY COMMAND IAlways 01000001

I=~I

RETRIES DISABLE
Retries enabled
1 = Retries disabled

To read a sector from the hard disk, the hard disk controller must
first find the sector. To find the correct sector, the hard disk controller selects the indicated head, performs any implied seek, and
waits for the index pulse. On receipt of the index pulse, the hard
disk controller begins scanning the track for a valid sector ID field.
A valid sector ID field contains the cylinder, head, sector number,
and size information that the hard disk controller is searching for.
The hard disk controller counts each index pulse as an attempt to
read a valid sector ID.
If retries are enabled and the hard disk controller fails to read a
valid ID field within ten attempts, the hard disk controller performs
an auto-seek and an auto-scan. If the hard disk controller fails to
read a valid ID field within an additional ten attempts, the hard
disk controller sets ID Not Found lerror register bit 41 and ERROR
Istatus register bit 01.
If retries are disabled and the hard disk controller fails to read a
valid ID field within two attempts, the hard disk controller sets
ID Not Found lerror register bit 41 and ERROR Istatus register
bit 01. Also, the hard disk controller does not perform an auto-seek
or an auto-scan.

The read verify command scans the data in the specified number of sectors of
the selected drive. As the hard disk controller scans the data of each sector. it
calculates the ECC bytes and verifies that the ECC bytes calculated from the
data and ECC bytes read from the disk agree. If the heads are not positioned
at the specified cylinder, the controller performs an implied seek to the proper
cylinder. The step rate used is that of the most recently executed restore or
seek command. Multiple sector reads may cross head and cylinder boundaries.
If the DRIVE READY signal becomes inactive, or the WRITE FAULT signal
becomes active, the hard disk controller terminates the command and sets
Hard Disk Drive Controller - Hardware Description

12 - 19

ABORTED COMMAND DETECT (error register bit 2) and ERROR (status
register bit 0).
To indicate command completion or an error condition, the hard disk controller
generates an interrupt request to the CPU.

12 - 20

Hard Disk Drive Controller . Hardware Description

Diagnose Command

~~~: ~

Bit

Description

7-0

DIAGNOSE COMMAND tAlways 100100001

On receipt of this command. the hard disk controller executes a set of diagnostic tests. If a problem exists, the hard disk controller reports the results in
the error register tsee Table 12-41. The internal ROM, internal RAM, ECC circuitry, and data path circuitry are tested. When the diagnostic tests complete,
the hard disk controller loads the appropriate code into the error register. To
indicate command completion, the hard disk controller generates an interrupt
request to the CPU.
For the diagnose command, the code in the error register is interpreted differently than normal error register encoding. Table 12-4 lists the diagnose command result codes.
Table 12-4 Hard Disk Controller Diagnostic Result Codes
Value

Meaning

01H

No error

02H

WDIOI5/WD2010 controller error

03H

Sector Buffer RAM data error
WDI015/WDllCOOA-22 Register access error
WDI015 ROM checksum or RAM data error

04H
05H

Hard Disk Drive Controller - Hardware Description

12 - 21

Set Parameters Command
7

Bit

Description

7-0

SET PARAMETERS COMMAND (Always 10010001)

This command sets the drive parameters for the maximum number of heads
and sectors per track. Prior to issuing this command, the drive selection must
be specified in the Sector Size/Drive Select/Head Select task register, and the
Sector Count Register must be set. This command must be issued before any
multiple sector operations are performed. To indicate command completion, the
hard disk controller generates an interrupt request to the CPU.

12 - 22

Hard Disk Drive Controller - Hardware Description

Status Register (OlF7H/0177H)
7

BUSY

DRIVE
READY

¥RITE

SEEK
FAULT STATUS

Bit

RIW Description

DRO

INDEX

ERROR

BUSY

o = Hard disk controller is ready to accept commands. The
status and error registers contain valid data.
1 = Hard disk controller is busy. The error register contains
invalid data. Only this status register bit is valid.

This bit must be polled before reading any register.
6

DRIVE READY

o = Drive is not ready. Read, write, and seek commands are
inhibited.
1 = Drive is ready. If bit 4 equals 1, read, write, and seek
commands are possible.

WRITE FAULT

o = No error
1 = Improper operation of the drive. All commands will be
terminated with an aborted command error.

SEEK STATUS - Seek Complete
Seek operation, direct or implied, is incomplete.
1 = Seek operation is complete (read/write heads are in position).

DRQ - Data Request

o = Do not read or write the sector buffer
1 = Read or write the sector buffer as indicated by the last
command issued.

CD - Corrected Data

o = No error
1 = The sector read from the drive resulted in a correctable ECC
error. Correctable errors do not cause multiple sector
transfers to terminate.

Hard Disk Drive Controller - Hardware Description

12 - 23

Bit

RIW Description

(Status Register . cont.)

INDEX
Index not in position and not detected
1 = Index in position and detected

ERROR
No error
1 = A nonrecoverable error has occurred. The error register cohtains the error status.

The next command issued to the hard disk controller, clears this
bit. If the hard disk controller sets this bit during a multiple sector
transfer, the transfer is terminated.

12 - 24

Hard Disk Drive Controller • Hardware Description

Alternate Status Register (03F6H/0376H)
This read-only register duplicates the status register WIF7H/Ol77H).

Hard Disk Register (03F6H/0376H)
7

I I I I
0

Bit

RIW Description

7-4

Always 0
ENABLE HEAD SELECT BIT 3
Reduced write current enabled
1 = Head Select Bit 3 (SOH register bit 3) enabled. See the
SDH register description.

RESET
Hard disk controller enabled.
1 = When set, the hard disk controller enters the reset state and
remains there until this bit is cleared. This bit must stay set
for a minimum of 5 p.s. When this bit is cleared, the hard
disk controller performs a set of power-up diagnostic tests
and the busy bit (status register bit 7) remains set until tests
are completed.

INTRPT ENABLE - Interrupt Enable
Hard disk controller interrupt buffer is enabled. Setting this
bit does not clear the hard disk controller interrupt output.
When this bit is cleared, any pending interrupts will occur.
1 = Hard disk controller interrupt buffer is disabled.

This bit enables or disables a buffer between the hard disk controller output and the peripheral interrupt controller input.

Always 0

Hard Disk Drive Controller - Hardware Description

12 - 25

Digital Input Register (03F7H/0377H)
6

BEAD

HEAD

lflUTE
RESERVE GATE
SIGNAL

SELECT SELECT SELECT
SIGNAL SIGNAL SIGNAL
1

Bit

R/W Description

Reserved (Value undefined)

WRITE GATE SIGNAL
0= Write gate signal is active.
1 = Write gate signal is inactive.

Always 1

HEAD SELECT SIGNAL 2
0= Head select signal 2 is active.
1 = Head select signal 2 is inactive.

HEAD SELECT SIGNAL 1
0= Head select signal 1 is active.
1 = Head select signal 1 is inactive.

HEAD SELECT SIGNAL 0
0= Head select signal 0 is active.
1 = Head select signal 0 is inactive.

DRIVE SELECT SIGNAL 1
0= Drive select signal 1 is active.
1 = Drive select signal 1 is inactive.

DRIVE SELECT SIGNAL 0
0= Drive select signal 0 is active.
1 = Drive select signal 0 is inactive.

12 - 26

DRIVE DRIVE
SELECT SELECT
SIGNAL SIGNAL

Hard Disk Drive Controller - Hardware Description

Programming Example
The following programming example demonstrates:
•
•
•
•

Initializing the hard disk controller
Recalibrating the hard disk drive
Seeking to a track
Hard formatting a hard disk
CAUTION
Improper programming or improper operation of this device can
cause the VAXmate workstation to malfunction. The scope of
the programming example is limited to the context provided in
this manual. No other use is intended.

Hard Disk Controller . Programming Example

12 - 27

#include "kyb.h"
#include "example.h"
/***********************************************************************/
/* define constants used in hard disk controller example
*/
/***********************************************************************/
#define PRI_BASE
Ox01fO /* primary base address of controller regs */
#define ALT_BASE
Ox0170/* alternate base address of controller regs */
#define HOR_ASR

Ox03f6
Ox03f7

/* address of hard disk register */
/* and alternate status register */
/* address of digital input register */

/* define constant divisor for write precompensation cylinder */
#define WPC_OIV

Ox04

/* define bit values for error status register */
#define ERR_BBD
#define ERR_OFE
#define ERR_ID
#define ERR_ABR
#define ERR_TZE
#define ERR_DAMNF

Ox80
Ox40
Ox10
Ox04
Ox02
Ox01

/* bad block detected */
/* CRC/ECC error in data field */
/* could not locate correct ID field */
/* command aborted */
/* track zero error */
/* data address mark not found */

/* define bit values for hard disk register */
#define HEAD_SEL3
#define RESET_HOC
#define INT_ENA

Ox04
Ox02
Ox01

/* enables third head select bit */
/* resets hard disk controller */
/* enables hdc interrupts to CPU */

/* define bit values for sdh register */
#define SDH_ECC

Ox80

/* select ecc mode for data field */

#define SDH_256
#define SDH_512

OxOO
Ox20

/* sector size
266 */
/* sector size = 612 */

12 - 28

Hard Disk Controller . Programming Example

1* define bit values for status register *1
#define STAT_BSY
#define STAT_RDY
#define STAT_WF
#define STALSC
#define STAT_DRQ
#define STALDWC
#define STAT_ERR

1* hdc busy *1
1* drdy pin *1
1* write fault *1
1* seek complete *1
1* data request *1
1* data was corrected *1
1* nonrecoverable error *1

OxSO
Ox40
Ox20
OxlO
OxOS
Ox04
OxOI

1* define bit values for command register *1
#define SR_35US
#define SR_0_5MS
#define SR_LOMS
#define SR_L6MS
#define SR_2_0MS
#define SR_2_6MS
#define SR_3_0MS
#define SR_3_6MS
#define SR_4_0MS
#define SR3_6MS
#define SR_5_0MS
#define SR_6_6MS
#define SR_6_0MS
#define SR_6_5MS
#define SR_3_2US
#define SR_l_6US

OxOO
OxOI
Ox02
Ox03
Ox04
Ox05
Ox06
Ox07
OxOS
Ox09
OxOa
OxOb
OxOc
OxOd
OxOe
OxOf

1* step rate = 35 us *1
1* step rate 0.6 ms *1
1* step rate = 1.0 ms *1
1* step rate 1.6 ms *1
1* step rate 2.0 ms *1
1* step rate 2.5 ms *1
1* step rate 3.0 ms *1
1* step rate 3.6 ms *1
1* step rate 4.0 ms *1
1* step rate 4.6 ms *1
1* step rate 5.0 ms *1
1* step rate 6.5 ms *1
1* step rate .. 6.0 ms *1
1* step rate = 6.6 ms *1
1* step rate 3.2 us *1
1* step rate 1.6 us *1

#define CMD_IC
#define CMD_MSF
#define CMD_LM
#define CMD_TRY

OxOS
Ox04
Ox02
OxOI

1* interrupt control *1
1* multiple sector flag *1
1* long mode read and write *1
1* disable retries *1

#define CMD_REST
#define CMD_SEEK
#define CMD_READ
#define CMD_WRITE
#define CMD_SCAN
#define CMD_FRMAT
#define CMD_CC
#define CMD_PARM

OxlO
Ox70
Ox20
Ox30
Ox40
Ox50
OxOS
Ox91

1* restore command *1
1* seek command *1
1* read command *1
1* write command *1
read/verify
command *1
1*
1* format command *1
command *1
compute
correction
1*
1* set parameter command *1

Hard Disk Controller . Programming Example

12- 29

/***********************************************************************/
/* declare structures used in hard disk controller example
*/
/***********************************************************************/
typedef struct
{

unsigned char sec_buf;
unsigned char err_wpc;
unsigned char se:;
unsigned char aD;
unsigned char cyLlow;
unsigned char cyLhi;
unsigned char sdh;
unsigned char csr;
} HOC;

/* (R/W) sector buffer */
/* (R) error reg */
precompensation
cylinder */
/* (W) write
(R/W)
sector
count */
/*
(R/W)
sector
number
/*
*/
/* (R/W) lower 8 bits of cylinder number */
/* (R/W) upper 2 bits of cylinder number */
/* (R/W) sdh register */
/* (R) status reg. (W) command reg */

typedef struct
{

HOC *base;
/* primary or alternate base address of controller reg */
int busy;
/* busy flag */
int retry;
/* retry count */
unsigned int cyl;
/* cylinder number */
unsigned char last_cmd;
/* last command sent to hdc */
unsigned char ecm;
/* error correction method */
unsigned char srt;
/* step rate time */
unsigned char ds;
/* drive select 0 - 3 */
unsigned char hs;
/* selected head number */
unsigned char sc;
/* sector count */
unsigned char sn;
/* sector number */
unsigned char eot;
/* end of track */
unsigned char fgpl;
/* format gap length */
unsigned char nd;
/* non-DMA mode */
unsigned char ss;
/* sector size */
unsigned char t·•
/* retry flag */
} HDC..;.CMD;

12- 30

Hard Disk Controller . Programming Example

typedef struct
{

1* cylinder count *1
1* write precompensation cylinder *1
1* head count *1
1* sectors per track *1

unsigned int cc;
unsigned int wpc;
unsigned int hc;
unsigned int spt;
} HOD;
typedef struct
{

unsigned int cyl;
unsigned char error;
unsigned char sc;
unsigned char sn;
unsigned char sdh;
unsigned char status;
} HOC_RESULT;

1* cylinder number *1
1* error code/status *1
1* sector count *1
1* sector number *1
1* sdh register *1
1* status register *1

1***********************************************************************1
1* declare space for hdc parameter data
*1
1***********************************************************************1
HOD hdd[2]

1* hard disk descriptors *1

{
{
{

615, 300, 4, 17 },
615, 300, 4, 17 },

};

1* command data *1
1* result data *1
1* hdc 1/0 buffer *1

HDC_CMD hdc_cmd;
HOC_RESULT hdc_result;
int hdc_buff[256];

1***********************************************************************1
1* hds() - select the desired drive
*1
1***********************************************************************1
hds()

1* select error correction method, sector size, drive, and head *1

{

HOC *phdc = hdc_cmd.base;
outp(~phdc->sdh,

hdc_cmd.ecm

1* pointer to controller registers *1
hdc_cmd.ss I (hdccmd.ds «

4) I hdc_cmd.hs);

}

Hard Disk Controller - Programming Example

12- 31

/***********************************************************************/
/* wait_hdc() - wait for hard disk command to complete
*/
/***********************************************************************/
wait_hdcO
{

HOC *phdc = hdc_cmd.base;

/* pointer to controller registers */

while(hdc_cmd.busy)

/* wait until interrupt occurs */
/* busy bit should be clear, but just in case, */
while(inp(&phdc->csr) & STAT_BSY)
/* wait until busy bit is clear */
if(inp(&phdc->csr) & STAT_ERR)
hdc_result.error = inp(&phdc->err_wpc);
else hdc_result.error = 0;
switch(hdc_cmd.last_cmd)

/* if error condition */
/* read error register */
/* mark no error */

/* discover last command issued */

{

case CMO_REST :
while«inp(&phdc->csr) & (STAT_ROY 1 STAT_SC»

(STAT_ROY 1 STAT_SC»

break;
case CMO_SEEK
while«inp(&phdc->csr) & (STAT_ROY 1 STAT_SC»
break;
case CMO]RMAT:
break;
default
break;
}

hdc_result.sc = inp(&phdc->sc);
/* read sector count register */
hdc_result.sn = inp(&phdc->sn);
/* read sector number register */
hdc_result.cyl = inp(&phdc->cyl_low);
/* low 8 bits of cyl */
hdc_result.cyl 1= inp(&phdc->cyl_hi) « 8;
/* high 2 bits of cyl */
hdc_result.sdh = inp(&phdc->sdh);
/* read sdh register */
hdc_result.status = inp(&phdc->csr);
/* read status register */
dsp_hdc_stat();
/* display result status */
}

12 - 32

Hard Disk Controller . Programming Example

/ ..............................................................•........ /
/. hdc_issue() - issue all hdc commands

/ ....................................................................... /
hdc_issue(cmd)
int cmd;

/. desired command ./

{

HDC *phdc - hdc_cmd.base;
char oline[20];
hdc_cmd.last_cmd ~ cmd;
switch (cmd)

/. set last command issued ./

{

case CMD_REST:
hdc_cmd.cyl - 0;
hdc_cmd.hs = 0;
cmd 1= hdc_cmd.srt;
break:
case CMD_SEEK:
cmd 1= hdc_cmd.srt;
break;
case CMD_SCAN:
cmd 1= hdc_cmd.t;
break:
case CMD_READ:
case CMD_WRlTE:
break:

/. recalibrate 1 ./

/. restore command ./

/* seek 1 ./
/* seek command ./
/. read ID 1 ./
/. scan id command ./
/. read data 1 ./
/* write data 1 ./

default:
break:
}

outp(tphdc->err_wpc, hdd[hdc_cmd.ds].wpc » 2); /. write the wpc reg ./
outp(tphdc->sc, hdc_cmd.sc);
/. write the sector count ./
outp(tphdc->sn, hdc_cmd.sn);
/. write the sector number ./
outp(tphdc->cyl_low, hdc_cmd.cyl):
/. write 8 low bits ./
outp(tphdc->cyl_hi, hdc_cmd.cyl » 8):
/. write 2 high bits ./
/. select appropriate drive */
hdsO:
outp(tphdc->csr, cmd);
/* write the command */
hdc_cmd.busy = TRUE;
}

Hard Disk Controller . Programming Example

12- 33

/***********************************************************************/
/* hdc_init() - initialize hard disk controller and interrupt vector */
/************~**********************************************************/

iv_init(Ox76):
imask(l, 6, ON):
outp(HDR_ASR, INT_ENA):

/* reset the hdc */
/* must be reset for minimum of 6 U8 */
/* initialize the interrupt vector */
/* enable PIC input */
/* hdc not reset and allow interrupt */

}

/***********************************************************************/
/* hdc_rest() - restore hard disk controller and interrupt vector
*/
/***********************************************************************/

outp(HDR_ASR, RESET_HOC):
imask(l, 6, OFF):
iv_rest(Ox76):
outp(HDR_ASR, INT_ENA);

/* reset the hdc */
/* disable PIC input */
/* restore the interrupt vector */
/* hdc not reset and allow interrupt */

}

/***********************************************************************/
/* hdc_int_hand() - hdc interrupt handler
*/
/***********************************************************************/
hdc_int_hand 0
{

HOC *phdc = hdc_cmd.base;

/* pointer to controller registers */

hdc_result.status = inp(lphdc->csr);
hdc_cmd.busy = FALSE:
eoi(1) :

/* read status register */
/* no longer busy */

}

12 - 34

Hard Disk Controller . Programming Example

/***********************************************************************/
/* bdc() - execute bard disk controller examples
*/
/***********************************************************************/
bdcO
{

static MESSAGE mbdc[]

/* bdc menu */

{

3, 27, "Hard Disk Controller Example" },
6, 27, "Fl. Recalibrate" },
{
6, 27, "F2. Head +" },
{ 7, 27, "F3. Head _II } ,
{ 8, 27, "F4. Seek +" },
{ 9, 27, "F6. Seek _II},
{ 10, 27, "F6. Read ID" },
{ 11, 27, "F7. ** Format Disk ** (Erases data)" },
{ 12, 27, "FlO. Return to Main menu" },
{ 0, 0, o },
{
{

};

/* to bold input line */
/* to bold output line */
/* loop control */
/* loop control */

cbar line[S12];
cbar oline[S12];
UDsigned int cyl;
UDsigned int bead;
HDC *pbdc;
int *pi;
int i;
disp_menu(mbdc);
bdc_cmd.base = (HDC *)PR1_BASE;
bdc_cmd.ecm = SDH_ECC;
bdc_cmd.ss
SDH_612;
bdc_cmd.ds
0;
bdc_cmd.bs
bdd[O].bc;
bdc_cmd.sc
bdd[O].spt;
bdc_cmd.srt = SR_l_5MS;
pbdc = bdc_cmd.base;
bdc_issue(CMD_PARM);
wait_bdcO;
bdc_cmd.cyl = bdc_result.cyl;
dsp_bdc_stat 0 ;
bdc_cmd.bs = 0;

/* display tbe bdc menu */
/* controller addressed at primary */

/* assign step rate */
/* set parameters */

Hard Disk Controller - Programming Example

12- 35

line[O] .. 0;
whUe(1)

/* null terminated */
/* forever (see FlO) */

{

line[O] - get_fkey();
sWitch (line [0])

/* get a function key for menu selection */
/* determine menu selection */

{

case Fl:
/* recalibrate */
hdc_cmd.ecm = SDH_BCC;
hdc_cmd.sc - hdd[hdc_cmd.ds].spt;
hdc_cmd.sn .. 0;
hdc_issue(CMD_REST);
wait_hdc();
/* wait for command complete */
break;
case F2:
/* head select + 1 */
hdc_cmd.ecm .. SDH_BCC;
hdc_cmd.sc = hdd[hdc_cmd.ds].spt;
hdc_cmd.sn .. 0;
if(hdc_cmd.hs < hdd[hdc_cmd.ds] .hc) hdc_cmd.hs++;
if(hdc_cmd.hs oo= hdd[hdc_cmd.ds] .hc) hdc_cmd.hs--:
hdc_issue(CMD_SEEK);
wait_hdc();
/* wait for command complete */
break;
case F3:
/* head select -1 */
hdc_cmd.ecm - SDH_BCC;
hdc_cmd.sc - hdd[hdc_cmd.ds].spt;
hdc_cmd.sD - 0;
if(hdc_cmd.hs) hdc_cmd.hs--;
hdc_issue(CMD_SEBK);
wait_hdc();
/* wait for command complete */
break;
case F4:
/* seek + 1 cylinder */
hdc_cmd.ecm .. SDH_BCC;
hdc_cmd. sc ... hdd[hdc_cmd.ds],' spt;
hdc_cmd.sD - 0;
if(hdc_cmd.cyl < hdd[hdc_cmd.ds].cc) hdc_cmd.cyl++~
if(hdc_cmd.cyl ..... hdd[hdc_cmd.ds].cc) hdc_cmd.cyl--:
hdc_issue(CMD_SEEK);
wait_hdc();
/* wait for command complete */
break;

12 - 36

Hard Disk Controller· Programming Example

case F6:
/* seek - 1 cylinder */
hdc_cmd.ecm = SDH_ECC;
hdc_cmd.sc = hdd[hdc_cmd.ds].spt;
hdc_cmd.sn = 0;
if(hdc_cmd.cyl) hdc_cmd.cyl--;
hdc_issue(CMD_SEEK);
wait_hdc();
/* wait for command complete */
break;
case F6:
hdc_cmd.ecm = SDH_ECC;

/* scan id */

hdc_cmd. Be = 1;

for(i = 1; i <= hdd[hdc_cmd.ds].spt; i++)
{

hdc_cmd.sn = i;
hdc_issue(CMD_SCAN);
wait_hdcO;

/* wait for command complete */

}

break;
case F7:
/* hard format disk */
hdc_issue(CMD_REST);
wait_hdc();
/* wait for command complete */
interleave (hdc_buff, 266, 17, 2, Oxffff);
for(cyl = 0; cyl < hdd[hdc_cmd.ds].cc; cyl++) /* all cylinders */
{

hdc_cmd.cyl = cyl;
/* current cylinder */
forehead = 0; head < hdd[hdc_cmd.ds].hc; head++)/* all heads */
{

hdc_cmd.hs = head;
hdc_cmd.ecm = SDH_ECC;
hdc_cmd.sc = hdd[hdc_cmd.ds].spt;
hdc_cmd.sn = 0;
hdc_issue(CMD_SEEK);
/* seek to current cylinder */
wait_hdcO;
/* wait for command complete */
hdc_cmd.ecm = SDH_ECC;
hdc_cmd.sc = hdd[hdc_cmd.ds].spt;
hdc_cmd.sn = 0;
hdc_issue(CMD_FRMAT);
while(l(inp(iphdc->csr) i STAT_DRQ»
for(i = 0; i < 256; i++)
outw(iphdc->sec_buf, hdc_buff[i]);
wait_hdc();
/* wait for command complete */
}

}

break;

Hard Disk Controller . Programming Example

12 - 37

case F8:
interleave (hdc_buff, 256, 17, 2, Oxffff);
for(cyl = 0, head = 0; head < 30; head++)
{

sprintf(oline, "%04x ", hdcbuff[head);
disp_str(13 + (head / 10), (head % 10) * 5, oline);
}

break;
case FlO:
return;

/* return to caller (main menu) */

}
}
}

dsp_hdc_stat 0
{

HOC_RESULT *pres
char oline[50);
sprintf(oline, "Error Reg
disp_str(21 , I, oline);
sprintf(oline, "Sector Count
disp_str(21, 41, oline);
sprintf(oline, "Sector Number:
disp_str(22, I, oline);
sprintf (oline, "Cylinder Num
disp_str(22 , 41, oline);
sprintf(oline, "SOH Register
disp_str(23, I, oline);
sprintf(oline, "Status Reg
disp_str(23, 41, oline);
sprintf(oline, "Last command
disp_str(24 , I, oline);

Ox%02x", pres->error);
Ox%02x", pres->sc);
Ox%02x" , pres->sn);
Ox%04x" , pres->cyl);
Ox%02x", pres->sdh);
Ox%02x", pres->status);
Ox%02x", hdc_cmd.last_cmd);

}

12 - 38

Hard Disk Controller - Programming Example

interleave (pb , size, ent, iI, fill)
int *pb;
int size;
int ent;
int H;
int fill;

/* pointer to buffer */
/* size of buffer */
/* number of sectors */
/* inter1eave:1 */
/* fill byte */

{

int *pi;
int *pf;
int x, y;

/* temp pointer */
/* start of fill */
/* temp counter */

x = size - ent;
pf = pi = pb + ent;
whi1e(x--) *pi++ = fill;
for(x = 1; x <= ent; x++)

/* fill size */
/* offset to fill */
/* set fill bytes */

{

if(pi > pf) pi = pb++;
x« 8;
*pi++
for(y = 1; Y < i1; y++) pi++;
}
}

Hard Disk Controller - Programming Example

12 - 39

Chapter 13
Network Hardware Interface
Introduction to the LANCE
The network hardware interface is located on the VAXmate workstation 1/0
board. When the back of the VAXmate workstation is open and no options are
plugged in, the 110 board is visible.
VAXmate workstations may contain different versions of the LANCE, which
exhibit subtle differences on large networks with high levels of traffic. The different versions of hardware require special treatment by software. Digital
Equipment Corporation recommends that you avoid programming the hardware
interface directly. Instead, applications should use the MS-Network session
level interface, DECnet-DOS session level interface, and the Data Link interface to access the network. For additionl information about these software interfaces, see Chapter 18 in this manual.
The remainder of this chapter discusses the following topics:
•
•
•
•
•
•
•
•
•
•
•

Functional description of the Network Hardware Interface
Programming sequence
Register descriptions
Physical description
Physical address field
Logical address filter field
Buffer management
Receive descriptor rings
Transmit descriptor rings
Network interface external interconnect
Network Interface system bus interconnect

13- 1

Additional Source of Information
Additional information about the LANCE can be found in the
Advanced Micro Devices document:
•

MOS Microprocessors and Peripherals 1985 Data Book

Functional Description of the Network
Hardware Interface
The network hardware interface is connected to the system bus. The interface
contains address, data, and control lines capable of handling the controller functions. The interface is part of the standard communications and 110 functions
of the VAXmate workstation.
The Network Interface (Nn consists of three main integrated circuits. The
hardware also includes a small number of discrete components, system bus interfacing devices, and a female BNC connector mounted directly on VAXmate
110 module printed circuit board. The BNC connector connects the Network
Interface to the network.
The three integrated circuits in the NI are the:
• Coax Transceiver Interface (CTII
• Serial Interface Adapter (SIAl
• Local Area Network Controller for Ethernet (LANCEI

The Coax Transceiver Interface
The CTI interfaces to the coaxial cable by a BNC connector. The CTI performs
transmit. receive, and collision detect functions for the network controller. The
CTI is electrically isolated from the other devices as required by IEEE 802.3
specifications.

The Serial Interface Adapter
The SIA interfaces to the CTI through an isolation transformer. The SIA performs manchester phase encoding and decoding of the data transferred over
the network. The SIA also interfaces with the LANCE. The SIA filters noise
and interprets collisions for the LANCE circuit.

The Local Area Network Controller
The LANCE converts data beteen the network serial format and the system
byte-wide format. The LANCE is the primary interface between the network
hardware and the rest of the VAXmate workstation.
13- 2

In receive mode, the LANCE:
1.

Receives information from the SIA.

Converts the serial network bit stream into a parallel l8-bit wide) byte
stream.

Strips the Ethernet preamble and synchronization pattern.

Checks and removes the CRC bits.

Uses direct memory access and a 24-bit-wide physical address to place
the information in memory located in the CPU address space.

In transmit mode, the LANCE:
1.

Uses DMA to read data from system memory.

Converts the data to a serial bit stream.

Adds a preamble and sync pattern.

Calculates and adds the CRC at the end of the data packet.

Passes the data packet to the SIA for transmission on the ThinWire
Ethernet.

Programming the LANCE
This section defines the control registers, status registers, and the data structures that are used to program the hardware interface.
The LANCE is controlled by a set of four control and status registers lCSRs)
and three data structures. The CSRs are accessible within the CPU 1/0 address
space and the data structures located in the CPU memory address space. After
the LANCE is enabled, it acquires additional operating parameters by accessing
the data structures. The LANCE accesses system memory through bus arbitration between the LANCE, CPU, memory refresh controller, and the DMA
controller.
After the LANCE is programmed, it independently manages the data structures and transfers data packets on the ThinWire Ethernet.
The three data structures accessed by the LANCE are:
•
•
•

Initialization Block
Receive and Transmit Descriptor Rings
Data Buffers

13- 3

Initialization Block
The initialization block is 12 contiguous words of memory starting on a word
boundary. The controlling program stores the operating parameters in the initialization block. To acquire the operating parameters, which are necessary for
device operation, the LANCE reads the initialization block. The initialization
block contains the:
•

Mode of Operation
Physical Address
Logical Address Mask
Location of Receive and Transmit Descriptor Rings
Number of Entries in Receive and Transmit Descriptor Rings

•
•
•

Receive and Transmit Descriptor Rings
The receive and transmit descriptor rings are two ring structures: one for incoming and the other for outgoing packets. Each entry in the rings is four
words, and must start on a quadword boundary. The descriptor rings contain
the buffer address, length, and status.

Data Buffers
Data buffers are contiguous portions of memory reserved for buffering packets.
Data buffers can begin on arbitrary byte boundaries. Entries in the Receive and
Transmit Descriptor Rings point to the data buffers.

Programming Sequence
The general programming sequence of the LANCE is:
Load CSR1 and CSR2, which identifies the location of an initialization
block in memory.
Load CSR3, which sets the operating mode of the LANCE.
Set the INIT and STRT bits in CSRO, which causes the LANCE to
load the information from the initialization block and to access the
descriptor rings.

2.
3.

NOTE
The Thin Wire Ethernet interface conforms to the IEEE 802.3
specification, which requires a frequency accuracy of ±0.01 %.
The crystal oscillator in the VAXmate network hardware requires 1 Ms after power on to achieve ±10% accuracy, and 10
seconds to achieve ±0.01 % accuracy. Therefore, the network interface is considered operational 10 seconds after power-on of
the VAXmate workstation.
On powerup, the VAXmate diagnostics ensure the required 10
second settling time.
13- 4

Register Description
The Network Interface uses three physical I/O ports as registers: two in the
LANCE, and one in the interface logic. The registers in the LANCE comprise
five logical registers, for a total of six logical registers in the Network Interface
(NI).
The LANCE internal CSRs are accessed through its two bus addressable ports,
a register address port (RAP), and a register data port (RDP). The internal
CSRs are read (or written) in a two step operation. The address of the CSR is
written into the address port (RAP). Then the data is read from (or written
into) the selected CSR through the RDP. Once written, the address in RAP
remains unchanged until rewritten.
Table 13-1 describes the registers and their addressing.
Table 13-1 Network Interface Registers
Primary

Alias

1/0

Address

OC60H
OC62H
RAP = 0
RAP = 1
RAP = 2
RAP = 3
OC68H

R/W

Description

C064H

R/W

l6-bit

C066H

R/W

l6-bit

OC69H-OC6FH

R/W
R/W
R/W
R/W
W

16-bit
l6-bit
l6-bit
l6-bit
8-bit

LANCE Register Data
Port (RDP)
LANCE Register Address
Port (RAP)
LANCE CSR 0
LANCE CSR I
LANCE CSR 2
LANCE CSR 3
NICSR

The logical address is the contents of RAP bits 1-0, and applies to references
to LANCE internal CSR registers 3-0. These registers are physically addressed
at the LANCE RDP address on the VAXmate 110 bus, and individually selected by the contents of LANCE RAP bits 1-0.
The VAXmate address decode logic creates alias I/O port addresses for certain
registers. The alias 110 addresses are listed in Table 13-1.
NOTE
Because future revisions of hardware may not implement these
aliases, programs should not use the alias addresses.

13- 5

I : : : ~ ~n:
7

543

:: I
1

I : : : ~~: : : I
Bit

R/W Description

16-0 R

13- 6

CSR DATA
Writing data into RDP writes the data into the CSR selected in
RAP. Reading the data from RDP reads the data from the CSR
selected in RAP. CSR1, CSR2, and CSR3 are accessible only when
the STOP bit of CSRO is set.
If the STOP bit is not set while attempting to access CSR1,
CSR2, or CSRS, the LANCE returns READY, but a read operation returns undefined data and a write operation is ignored.

I : : : 7 : : : I
7

I : : u<
Bit
15-2
1-0

: : I c~

RIW Description
RES - Reserved (always 0)
R/W CSR - Control/Status Register Select

o = CSRO accessed through RDP
1 = CSR1 accessed through RDP
2 = CSR2 accessed through RDP
3 = CSR3 accessed through RDP

The register address port is cleared by STOP or Bus RESET.

13- 7

Control And Status Register 0 (RAP = 0)
15

Bit

RIW Description

13- 8

ERR - Error
o = The four bits BABL, CERR, MISS and MERR are all equal
to O.
1 = One or more of the four bits, BABL, CERR, MISS, or
MERR are equal to 1.
BABL - Babble
o = Less than 1519 bytes of data have been transmitted.
1 = 1519 bytes of data, or more, have been transmitted.
BABL indicates a transmitter error, caused by the transmitter
being on longer than the time required to send the maximum
length packet. The LANCE transmits data until the transmit
buffer byte count equals
zero. The LANCE assumes the Ethernet transmission is limited by
the physical channel interface.
If INEA = 1, an interrupt is generated when BABL is set.
0 = No effect
1 = Clears this bit
Bable is read/clear only. BABLE is cleared by Bus RESET or setting the STOP bit.

Bit

R/W Description

~CSRO . cont.)

CERR· Collision Error

o = No collision error
1 =

Collision error

The collision input failed to activate within 2 ps after a
transmission, started by the controller, was completed. Collision
after transmission is a test feature of the transceiver.
W

0 = No effect
1 = Clears this bit
CERR is READ/CLEAR ONLY
CERR is cleared by Bus RESET or setting the STOP bit.

MISS . Missed Packet
Receiver Owns a receive buffer or the SILO has not
overflowed
1 = The receiver loses a packet because it does not own a receive
buffer and the SILO has overflowed, indicating loss of data.
SILO overflow is not reported because there is no receive
ring entry in which to write the status.

o = No memory error
1 = LANCE is the Bus Master and has not received READY

No effect
1 = Clears the bit
If INEA equals 1 and MISS equals 1, an interrupt is generated.
MISS is READ/CLEAR ONLY. MISS is cleared by Bus RESET
or setting the STOP bit.
MERR . Memory Error

within 25.6 ps after asserting the address on the DAL lines.
When a Memory Error is detected, the receiver and
transmitter are turned off and an interrupt is generated if
INEA = 1.

0 =
1 =

No effect
Clears the bit

MERR is READ/CLEAR ONLY. MERR is cleared by Bus RESET
or setting the STOP bit.

13- 9

Bit

R/W Description

(CSRO - cont.~

RINT - Receiver Interrupt

R
W

o = No receiver interrupt
1 = Receiver interrupt
0 = No effect
1 =

Clears the bit

RINT = 1 when the status for an entry in the Receive Descriptor
Ring is updated.
If INEA = 1, an interrupt is generated when RINT is set.

RINT is READ/CLEAR ONLY
RINT is cleared by Bus RESET or setting the STOP bit.
9

TINT - Transmitter Interrupt
No transmitter interrupt
1 = When the status for an entry in the Transmit Descriptor
Ring is updated.

o = No effect

1 = Clears the bit
If INEA

= 1, an interrupt is generated when TINT is set.

TINT is READ/CLEAR ONLY
TINT is cleared by Bus RESET or setting the STOP bit.
8

lOON - Initialization Done

o = Initialization procedure not completed
1 = LANCE has completed the initialization procedure started by

setting the INIT bit. When lOON is set, the LANCE has
read the initialization block from memory and stored the new
parameters.

If INEA = 1, an interrupt is generated when lOON is set.

lOON is READ/CLEAR ONLY
W

0 = No effect
1 = Clears the bit
lOON is cleared by Bus RESET or setting the STOP bit.

INTR - Interrupt Flag

o = BABL, MISS, MERR, RINT, TINT, and lOON are all equal
o
1 = One or more of the following interrupt causing conditions
has occurred: BABL, MISS, MERR, RINT. TINT. lOON. If
INEA = 1 and INTR = 1 the INTR L 110 pin will be low.
INTR is cleared by Bus RESET or setting the STOP bit. INTR is
also cleared by clearing the conditions that caused the interrupt.

13- 10

Bit

RIW Description

(CSRO - cont.)

R/W INEA - Interrupt Enable
o = The INTR L I/O pin will be high, regardless of the state of
INTR.
1 = If INTR = 1, the INTR L I/O pin will be low.
INEA allows the INTR L 110 pin to be driven low when the
Interrupt Flag is set. If INEA = 0 INEA is cleared by Bus RESET
or setting the STOP bit.

axON - Receiver ON
Receiver disabled
1 = Receiver enabled

axON = 0 when IDON = 1, if Dax = 1 in the MODE register
or a memory error (MERR = 1) has occurred. RXON = 1 when
STRT is set in CSRO, if DRX 0 in the MODE field of the initialization block is IDON = 1.
axON is cleared by Bus RESET or setting the STOP bit.
4

TXON - Transmitter On
Transmitter enabled
1 = Transmitter disabled

When TXON = 0, IDON = 1, and DTX = 1 in the MODE register, an Underflow or Retry error has occurred during transmission
or a memory error (MERR) has occurred.
TXON = 1 when the INIT bit = 1, and when STRT =1 if DTX
= 0 in the MODE register in the initialization block. TXON is
cleared by Bus RESET or setting the STOP bit.
3

W
R

TDMD - Transmit Demand
0 = The packet is sent subject to the 1.6-millisecond polling interval delay.
1 = Packet is transmitted without the typical delay of the polling
interval, 1.6 milliseconds.

0 =
1 =

No effect
Clears this bit

TDMD, when set, causes the LANCE to access the Transmit
Descriptor Ring without waiting for the poll time interval to
elapse. TDMD need not be set to transmit a packet, it merely
hastens the LANCE response to a Transmit Descriptor Ring entry
insertion by the software.
TDMD is cleared by Bus RESET or setting the STOP bit. TDMD
is cleared by the LANCE after the Transmit Descriptor Ring is
accessed.

13-11

Bit

RIW Description

R/W STOP

(CSRO - cont.)

o = No effect
1 = LANCE disabled from all external activity and internal logic
cleared
STOP set is the equivalent of asserting Bus RESET L. The
LANCE remains inactive and STOP remains set until the STRT or
INIT bit is set. If STRT, INIT, and STOP are all set together,
STOP will override the other bits and only STOP will be set. Stop
will terminate all LANCE activities asynchronously.
STOP is cleared by setting INIT or STRT.

R/W STRT - Start
STRT enables the LANCE to send and receive packets, perform
direct memory access and do buffer management. Setting STRT
clears the STOP bit. If STRT and INIT are set together, the INIT
function will be executed first.
STRT is READ/WRITE WITH ONE ONLY. Writing a 0 into this
bit has no effect.
STRT is cleared by Bus RESET or setting the STOP bit.

R/W INIT - Initialize
o = No effect
1 = Starts LANCE initialization and reads initialization block.
Setting INIT clears the STOP bit.
If STRT and INIT are set together, the INIT function will be executed first.
INIT is cleared by Bus RESET or setting the STOP bit.

13- 12

Control And Status Register 1 (RAP = 1)
15

I : : :IADR(l:-S):
7

I : : ~(7-1:
Bit

Description

15-1

IADR

:
1

I 0I

The low-order 16 bits of the address of the first word (lowest address) in the initialization block.

Always 0

Accessible only when the STOP bit of CSRO equals 1. If STOP = 0, an access
returns READY, a Read operation returns undefined data and a Write operation is ignored. CSR1 is unaffected by Bus RESET L.

13- 13

Control And Status Register 2 (RAP = 2)
15

:
7

:
6

543

I : : ~ (Bi~S 23-16:
Bit

Description

15-8

RES

:
2

:
0

Reserved.
7-0

IADR (Bits 23-16)
The high order 8 bits of the address of the first word of the initialization block.

Accessible only when STOP equals 1 (CSRO). If STOP = 0, an access returns
READY, a Read operation returns undefined data and a Write operation is
ignored.
CSR2 is unaffected by Bus RESET L.

13- 14

Control And Status Register 3 (RAP = 3)

Bit
15-3
2

R/W Description

RES - Reserved (Always 0)
R/W BSWP - Byte Swap

o=
1 =

The LANCE does not swap high and low bytes
The LANCE swaps the high and low bytes on DMA data
transfers between the SILO and bus memory.

BSWP allows the LANCE to operate in systems that consider bits
15-8 to be the least significant byte and bits 7-0 to be the most
significant byte. Only data from Silo transfers is swapped, the initialization block data and the Ring Descriptor entries are NOT
swapped. BSWP is cleared by Bus RESET or setting the STOP bit
in CSRO.
1

R/W ACON - ALE Control
R/W 0 =
1 =

ALE is asserted high.
ALE is asserted low.

ACON defines the assertive state of ALE when the LANCE is a
Bus Master.
ACON is cleared by Bus RESET or setting the STOP bit in
CSRO.

13- 15

Bit

R/W Description

R/W BCON - Byte Control

BCON

o
1

(CSR3 - cont.)

110 Pin 16
BM 1 L
BUSAKO L

110 Pin 15
BM 0 L
BYTE H

110 Pin 17
HOLD L
BUSRQ L

BCON redefines the Byte Mask and Hold I/O pins.
BCON is cleared by Bus RESET or setting the STOP bit in
CSRO.
Table 13-2 lists the value required for each function for CSR3.
Table 13-2 LANCE CSR3 Required Values For The VAXmate Workstation
Bit

Function

Value Required

15-3

Undefined

should be zero

BSWP (Byte Swap)

ACON (ALE Control)

0
1

BCON (Byte Mask Control)

CSR3, which allows redefinition of the bus master interface, contains three
bits. They are used to customize certain hardware interface signals provided by
the LANCE when it is in bus master mode. The programming of these bits is
hardware implementation dependent. The VAXmate workstation values are in
Table 13-2.
Accessible only when the STOP bit of CSRO equals 1. If STOP = 0, an access
returns READY, a Read operation returns undefined data and a Write operation is ignored.
Bus RESET L or setting the STOP bit in CSRO, clears CSR3.

13- 16

NI CSR (OC68H)
7

Bit

RIW Description

LED SET - Diagnostic LED Indicator Set
No effect
LED on
RES - Reserved (undefined)

RES - Reserved (undefined)

W
3

0=
1 =

LED CLEAR - Diagnostic LED Indicator Clear
No effect
LED off (Power-on default)
INT CLEAR - Network Interface Interrupt Enable Clear
0= No effect
1 = Disable interrupts (Power-on default)

0=
1 =

RES - Reserved (undefined)

INT SET - Network Interface Interrupt Enable Set
No effect
Enable interrupts

0=
1 =

The NI CSR supports individual bit-set and bit-clear capability in a write-only
register. Writing a 1 to a bit invokes its particular set or clear operation on the
designated function. Writing a 0 to a bit does not invoke the particular set or
clear operation for the designated function. Writing 0 to both set and clear bits
for a designated function leaves the state of that function unchanged. Because
writing 1 to both the set and clear bits of a designated function will toggle the
state of that function, writing 1 to both the set and clear bits is not
recommended.

13- 17

Initialization Block
During initialization, the LANCE reads operating parameters from the initialization block.
When the INIT bit in CSRO is set, the LANCE begins reading the initialization
block. To ensure proper parameter initialization and LANCE operation, the
controlling program should set the INIT bit and then set the STRT bit. After
the LANCE reads the initialization block, the LANCE sets IDON in CSRO and
if INEA equals 1, the LANCE also generates an interrupt.
Higher Addresses

TLEN-TDRA (23-16)
TDRA (15-00)
RLEN-RDRA (23-16)
RDRA (15-00)
LADRF (63-48)
LADRF (47-32)
LADRF (31-16)
LADRF (15-00)
PADR (47-32)
PADR (31-16)
PADR (15-00)
Base Address of Block
MODE (15-00)

IADR +22
IADR +20
IADR +18
IADR +16
IADR +14
IADR +12
IADR +10
IADR +08
IADR +06
IADR +04
IADR +02
IADR +00

The base address, BASE ADDR, is formed from CSR2 bits 7-0 and CSR1 bits
15-1.

13- 18

Mode Field
(Initialization Block, Offset OOH)
15

Bit

Description

PROM - Promiscuous
o = Incoming packets matching physical or logical address filter
are accepted.
1 = All incoming packets are accepted.

14-7

RES - Reserved

INTL - Internal Loopback
INTL is used with the LOOP (bit 21 to determine where the loopback is to be done. Internal loopback allows the LANCE to receive
its own transmitted packet. The maximum transmit packet size allowed during loopback is 32 data bytes. The LANCE automatically
adds 4 bytes of CRC to the packet if DTCRC=O and therefore the
receive packet could be 36 bytes. INTL is only valid if LOOP = 1,
otherwise it is ignored.
INTL

Loop

1
1

LOOPBACK
No loopback, normal operation
external
internal

13- 19

Bit

Description

DRTY • Disable Retry
LANCE attempts 16 retransmissions of a packet after the
first collision before reporting a Retry error.
1 = LANCE attempts only one transmission of a packet. If there
is a collision on the first transmission attempt, a Retry Error
(RTRY) is reported in Transmit Message Descriptor 3
(TMD3).
COLL • Force Collision
o = Collision not forced
1 = Collision forced during subsequent transmission attempt
COLL allows the collision logic to be tested. For COLL to be valid,
the lance must be in internalloopback mode. When COLL = I,
16 transmissions are attempted, and a retry error is reported in
TMD3.
DTCR . Disable Transmit CRC
o = The transmitter generates and appends a CRC to the
transmitted packet.
1 = The CRC logic is allocated to the receiver and no CRC is
generated and sent with the transmitted packet.
During lOopback, DTCR = 0 generates a CRC on the transmitted
packet. CRC logic, shared by the receiver and the transmitter;
cannot generate and check CRe at the same time. Therefore, the
receiver does the eRe check. The generated eRe and data are
written into memory and can be checked by the software.
If DTeR = 1 during loopback, the software must append a eRe
value to the transmit data in the transmit buffer. The receiver
checks the eRe on the received data and reports any errors.

13- 20

(Mode Field . cont.)

Bit
2

Description

(Mode Field - cont.)

LOOP - Loopback
LANCE operates in normal mode
1 = LANCE operates in full duplex mode for test purposes

LOOP allows the LANCE to operate in full duplex loopback mode
for test purposes. The maximum transmit packet size is limited to
32 data bytes. The received packet may be 36 bytes because the
LANCE automatically adds 4 CRC bytes if DTCRC=O.
During loopback, the runt packet filter is disabled because the
maximum packet is forced to be smaller than the minimum size
Ethernet packet of 64 Bytes.
LOOP = 1 allows simultaneous transmission and reception for a
message constrained to fit within the SILO. The LANCE waits
until the entire message is in the SILO before serial transmission
begins. The incoming data stream fills the SILO from behind as it
is being emptied. Moving the received message out of the SILO to
memory does not begin until reception has ceased. In loopback
mode, transmit data chaining is not possible. Receive data chaining
is allowed, regardless of the receive buffer length. In normal operation, not loopback, the receive buffers must be at least 64 bytes
long to allow time for buffer lookahead.
1

DTX - Disable the Transmitter
LANCE can access the Transmit Descriptor Ring
1 = LANCE does not access the Transmit Descriptor Ring,
therefore no transmissions are attempted. DTX = 1 clears
the TXON bit in CSRO when initialization is complete.

DRX - Disable the Receiver
Receives incoming packets
1 = LANCE rejects incoming packets and does not access the
Receive Descriptor Ring. DRX = 1 clears the RXON bit in
CSRO when initialization is complete.

The Mode field allows alteration of the LANCE operating parameters. In
normal operation, the Mode Register clear.

13- 21

Physical Address Field
(Initialization Block, Offset 02H)
PADR, the Network Physical Address, is the unique 48-bit physical address
assigned to the LANCE. PADR(OI must be zero.

Logical Address Filter Field
(Initialization Block, Offset 08H)
LADRF, the Logical Address Filter Field, is a 64-bit mask used by LANCE to
accept the logical addresses.
The Logical Address Filter is a 64-bit mask that accepts incoming Logical
Addresses sent through the CRC circuit. After all 48 bits of the address have
travelled through the CRC circuit, the high-order 6 bits of the resultant CRC
are strobed into a register. This register selects one of the 64-bit positions in
the Logical Address Filter. If the selected filter bit equals 1, the address is
accepted and the packet is put in memory. The first bit of the incoming address must be 1 for a logical address. If the first bit is 0, it is a physical address and is compared against the physical address that was loaded through
the Initialization Block.
The Broadcast address, which is all ones, does not go through the Logical
Address Filter and is always enabled. If the Logical Address Filter is loaded
with all zeros, all incoming logical addresses except Broadcast are rejected.

13- 22

Receive Descriptor Ring Pointer Field
(Initialization Block, Offset lOH)
31

I : nm:
23

I : :~:
20

: I
17

I : : : ~ : : :
15

I : : : ~ : : :
765

I : : : ~ : 0: 0: 0 I

13- 23

Bit

Description

(Receive Descriptor Ring Pointer Field)

31-29

RLEN - RECEIVE RING LENGTH
The number of entries in the Receive Ring expressed as a power
of two.
RLEN
Number of Entries

o
1
2

28-24
23-0

13- 24

2
4

3
8
4
16
5
32
6
64
7
128
RES (Reserved)
RDRA - Receive Descriptor Ring Address
RDRA is the base address (lowest address) of the receive descriptor ring. Because the receive rings must be aligned on quadword
boundaries, bits 2-0 must be zeros.

Transmit Descriptor Ring Pointer Field
(Initialization Block, Offset 14H)
31

1
20

765

:
17

1
16

~
~
: : ~ :0:0:01
:

~ :

I :
23

13- 26

Bit

Description

31·29

TLEN
TLEN is the number of entries in the Transmit Ring expressed
as a power of two.
Number of
Entries
TLEN
1
o
2
4
3
8

28·24
23-0

13- 26

(Transmit Descriptor Ring Pointer Field)

5
6
7
8

64
128

266

RES - Reserved
TDRA • Transmit Descriptor Ring Address
TDRA is the base address (lowest address) of the Transmit
Descriptor Ring. Because the transmit rings must be aligned on
quadword boundaries, these bits 2-0 must be zeros.

Buffer Management
Buffer descripto~s, organized as ring structures in memory, are used for buffer
management. The buffer descriptors, also called message descriptors, are four
words long and point to a buffer. Two ring structures are allocated for the
LANCE: a ring of receive message descriptors jRMDs) and a ring of transmit
message descriptors jTMDs). To transmit or receive packets, the LANCE polls
each ring structure. The LANCE also enters status information in the descriptor entry. The LANCE is limited to looking only one descriptor entry ahead of
the one with which the LANCE is currently working.
The location of the descriptor rings and their length are found in the initialization block, which the LANCE accesses during the initialization procedure.
Writing a 1 into the STRT bit of CSRO causes the LANCE to start accessing
the descriptor rings and enables the sending and receiving of data packets.
The LANCE communicates with the data link layer program through the ring
structures in memory. Each entry in the ring is owned either by the LANCE
or the data link layer program. The ownership bit (OWN) in the message
descriptor entry determines who owns the entry. Therefore, ownership of a
descriptor entry is mutual exclusive. To gain ownership of a descriptor entry,
the communications partner (LANCE or data link layer program) must wait
until the owner gives ownership to the communications partner. Between the
time a communications partner relinquishes ownership of a descriptor entry and
the time that communications partner regains ownership, it must not change
any data in the descriptor entry.

13- 27

Descriptor Rings in Memory
Figure 13-1 shows receive and transmit descriptor rings with 128 message
descriptors each.

Higher
Addresses

THD(127)

T
R
A
N

S
M
I

T
TMD(l)

Base Address
of
Transai t Ring

THD(O)

I
N
G

Higher
Addresses

RMO(127)

Base Address
of
Receive Ring

RMO(l)

RMO(O)

I
N
G

Figure 13-1 Descriptor Rings

13- 28

R
E
C
E
I
V
E

Receive Descriptor Rings
Each descriptor in a ring in memory is a 4 word entry. The format of the
receive descriptor follows.

Receive Message Descriptor 0 (RMDO)
15

I : : : ~ : : :o I
7

I : : : ~ : : : I
Bit

Description

15-0

LADR - Low Order Address
The LADR of the buffer pointed to by this descriptor. LADR is
written by the software and unchanged by the LANCE. This is the
memory location to place the next received message.

13- 29

Receive Message Descriptor 1 (RMDl)
15

Bit

Description

OWN

~ :

o = Descriptor entry owned by the data link layer software
1 =

Descriptor entry owned by the LANCE

The LANCE clears the OWN bit after filling the buffer pointed to
by the descriptor entry. The software sets the OWN bit after
emptying the buffer. Once the LANCE or software has relinquished ownership of a buffer, it may not change any field in the
four words that comprise the descriptor entry.
ERR - Error
o = The four bits, FRAM, OFLO, CRC or BUFF, are all equal to
zero.
1 = One or more of the four bits, FRAM, OFLO, CRC or BUFF,
is equal to one.
ERR is set by the LANCE and cleared by the software.
FRAM - Framing Error
o = No framing error
1 = The incoming packet contained a non integer multiple of
eight bits and there was a CRC error.
A CRC error on the incoming packet is a necessary condition for
FRAM to equal 1 (even if there was a non integer multiple of eight
bits in the packet). FRAM is set by the LANCE and cleared by
the software.

13- 30

Bit

Description

(RMDI - cont.)

OFLO - Overflow Error

o = No overflow error
1 = The receiver has lost all or part of the incoming packet because it cannot store the packet in a memory buffer before
the internal SILO has overflowed.

OFLO is set by the LANCE and cleared by the software.
11

CRC - Cyclic Redundancy Check

o = No CRC error

1 = The receiver detected a CRC error on the incoming packet.
CRC is set by the LANCE and cleared by the software.

BUFF - Buffer Error

o = No buffer error
1 = The LANCE does not own the next buffer while data chain-

ing a received packet. This condition could occur if the OWN
bit of the next buffer was zero or the LANCE could not acquire the next status before silo overflow occurred.

BUFF is set by the LANCE and cleared by the software.
9

STP - Start of Packet
This is not the first buffer the LANCE uses for this packet.
1 = This is the first buffer LANCE uses for this packet. It is
used for data chaining buffers.

STP is set by the LANCE and cleared by the software.
8

7-0

ENP - End of Packet

o = This is last buffer LANCE uses for this packet.
1 = This is the last buffer used by the LANCE for this packet. It
is used for data chaining buffers.
Both STP and ENP set indicate that the packet fit into one buffer
and there was no data chaining. ENP is set by the LANCE and
cleared by the software.
HADR - High Order 8 Address Bits
The HADR of the buffer pointed to by this descriptor. This field is
written by the software and unchanged by the LANCE.

13- 31

Receive Message Descriptor 2 (RMD2)
15

I : : :

: : I

Bit

Description

15-12

Must be ones. This field is written by the software and unchanged
by the LANCE.

11-0

BCNT - Buffer Byte Count
BCNT is the length of the buffer pointed to by this descriptor expressed as a two's complement number. This field is written by the
software and unchanged by the LANCE. The minimum buffer size
is 64 bytes.

13- 32

Receive Message Descriptor 3 (RMD3)
15

Bit
15-12

Description
RES
Reserved and read as zeros.

11-0

MCNT - Message Byte Count
MCNT is the length in bytes of the received message. MCNT is
valid only when ERR is clear and ENP is set. MCNT is written by
the LANCE and cleared by the software. When data chaining,
RMD3 is only loaded by the LANCE when the status of last buffer
is updated. Only the status word is updated for the other buffers
in the data chain.

13- 33

Transmit Descriptor Ring
Each descriptor in a ring in memory is a 4 word entry. The format of the
transmit descriptor follows.

Transmit Message Descriptor 0 (TMDO)
15

~ : : : I
I : : : ~ : : : I

I:
7

Bit

Description

15-0

LADR - Low Order 16 Address Bits

The LADR of the buffer pointed to by this descriptor. LADR is
written by the software and unchanged by the LANCE.

13- 34

Transmit Message Descriptor 1 (TMDl)
15

I : : :
Bit

~ : : : I

Description

OWN

o=
1 =

Owned by the LANCE
Owned by the data link layer software

OWN indicates whether the descriptor entry is owned by the software (OWN = 0) or by the LANCE (OWN = 1). The software sets
the OWN bit after filling the buffer pointed to by this descriptor.
The LANCE clears the OWN bit after transmitting the contents of
the buffer. Neither the software nor the LANCE may alter a
descriptor entry after relinquishing ownership.
14

ERR - Error Summary

o = All of LCOL, LCAR, UFLO. and RTRY equal O.
1 = One or more of LCOL, LCAR, UFLO, or RTRY equal 1.
ERR is set by the LANCE and cleared by the software.

13
12

RES- Reserved (Always 0)
MORE

o = One retry or less was needed to transmit a packet.
1 = More than one retry was needed to transmit a packet.
MORE is set by the LANCE and cleared by the software.

13- 35

Bit

Description

(TMD1 - eont.~

ONE

o = The number of retries need to transmit a packet is not equal
1.

1 = Exactly one retry was needed to transmit a packet.
ONE is set by the LANCE and cleared by the software.
10

DEF - Deferred
The channel is ready for LANCE to transmit a packet.
1 = The channel is busy when the LANCE is ready to transmit a
packet.

DEF set by the LANCE and cleared by the software.
9

STP - Start of Packet

o = Not the first buffer LANCE uses for this packet.

1 = The first buffer to be used by the LANCE for this packet. It
is used for data chaining buffers.
STP is set by the software and unchanged by the LANCE.

ENP - End of Packet

o = Not the last buffer LANCE uses for this packet
1 = The last buffer to be used by the LANCE for this packet. It
is used for data chaining buffers.

7-0

If both STP and ENP are set. the packet fit into one buffer and
there was no data chaining. ENP is set by the software and unchanged by the LANCE.
HADR - High-Order 8 Address Bits

HADR is the high-order 8 address bits of the buffer pointed to by
this descriptor. HADR is written by the software and unchanged
by the LANCE.

13- 36

Transmit Message Descriptor 2 (TMD2)
15

I : : :~ : : :

Bit

Description

15-12

Always 1. This field is set by the software and unchanged by the
LANCE.
BCNT - Buffer Byte Count

11-0

BCNT is the number of bytes LANCE transmits of the buffer to
which TMD2 points. BCNT is expressed in 2's complement.
BCNT is written by the software and not affected by the LANCE.
The minimum size of the buffer is 64 bytes.

13- 37

Message Descriptor 3 (TMD3)
15

I : : : mR:
Bit
15

13
12

Description
BUFF - Buffer Error
No buffer error
1 = LANCE, during transmission. does not find the ENP flag in
the current buffer and does not own the next buffer. BUFF
= 1 also if the LANCE owns the next buffer but can not
read the next buffer's status parameters before the silo underflowed.
BUFF is set by the LANCE and cleared by the software. If a
Buffer Error occurs, an Underflow Error also occurs because the
transmitter continues to read data from the silo until empty.

UFLO - Underflow Error
No underflow error
1 = The transmitter has truncated a message due to lack of data
from memory. UFLO indicates that the Silo has emptied
before the end of the packet was reached.
UFLO is set by the LANCE and cleared by the software.

RES - Reserved (Always 0)
LCOL - Late Collision
No collision
1 = A collision occurred after the slot time of the channel has
elapsed.

The LANCE does not retry on late collisions. LCOL is set by the
LANCE and cleared by the software.

13- 38

Bit
11

Description

(TMD3 - cont.)

LCAR - Loss of Carrier

o = RENA does not go false during transmission
1 =

The carrier presence (RENA) input to the LANCE goes false
during a transmission initiated by the LANCE. The LANCE
does not retry upon Loss of Carrier.

LCAR is set by the LANCE and cleared by the software.
10

RTRY - Retry Error

o = No retry error
1 = The transmitter has failed in 16 attempts to transmit a
message due to repeated collisions on the medium. If DRTY
= 1 in the MODE register, RTRY sets after 1 failed
transmission attempt.
RTRY is set by the LANCE and cleared by the software.

9-0

TO R - Time Domain Reflectometry
The TOR shows the state of an internal LANCE counter that
counts from the start of a transmission to the occurrence of a collision. This value is useful in determining the approximate distance
to a cable fault. The TOR value is written by the LANCE and is
valid only if RTRY is set.

TMD3 is valid only if the LANCE has already set the ERR bit of TMDl.

13- 39

Network Interface External Interconnect
The VAXmate network hardware connects to the network coaxial cable through
a BNC T-connector. The VAXmate network hardware complies with IEEE
802.3 IOBASE2 specifications. The cable shield is isolated from the VAXmate
logic and chassis ground, and must be externally grounded by the interconnect
equipment. The VAXmate workstation does not contain a 50-ohm linetermination. The 50-ohm line terminator must be supplied externally, as required by the connection topology.

Network Interface System Bus Interconnect
The hardware interface uses the I6-bit and 8-bit system bus for data transfers.
It operates in both bus master and bus slave modes. In bus slave mode, the
registers respond to 1/0 cycles. The LANCE registers require I6-bit I/O and
the NI CSR register requires an 8-bit 110. All of the network interface registers
are located in proprietary 110 address space of the VAXmate workstation.
Accessing the LANCE registers can cause extra I/O wait states.
In the bus master mode, the LANCE initiates I6-bit memory cycles to transfer
data, commands and parameters to and from main system memory. The
VAXmate workstation supports both I6-bit and 8-bit memory cycles, but the
network interface supports only I6-bit memory cycles. Although the VAXmate
uses the READY signal to support asynchronous memory cycles, the network
interface supports only synchronous memory cycles. The network interface performs DMA transfers at the rate of 600 ns per cycle.
The network hardware works with standard system memory resident on the
VAXmate CPU module, and with the VAXmate memory option located in the
workstation main box. Accesses to 8-bit memory in the VAXmate expansion
box are not supported by the network hardware. If the memory complies with
the network hardware timing requirements, third-party I6-bit memory in the
expansion box may work correctly.
The interface does not support DMA to the VAXmate video display memory.
The interface uses the full 24-bit physical memory address space and operates
with physical addresses only.
The network hardware uses interrupt line IRQIO, and a special LAN DMA
request line, provided by the CPU Module. The special LAN DMA request line
has higher priority than all DRQs lines on the system bus.

13- 40

Index
802.3 Compatible mode 18-6
80287 error interrupt 15-151
8254 interval timer 6-1
block diagram 6-1
registers 6-8
8259A interrupt controller
initialization command words 3-5
initialization sequence 3-5
input/output ports 3-3
operation command words 3-11
registers 3-3
A

Acknowledge
LK250 keyboard responses 8-31
Active cycle
DMA controller 4-3
Add name for session 18-101
Add node for session 18-120
Address generation
DMA controller 4-5
Address map
input/output 2-4
Alarms 5-12
Alias 110 port addresses 13-5

Alternate status register 12-25
Anomalies
keyboard processing 17-11
ANSI Character Set 17-74
ANSI functions
not supported 17-79
ANSI support
inside a window 17-79
ANSI.SYS 16-5
Cursor control functions 16-5
Erase functions 16-7
installing 16-5
Keyboard key reassignment function 16-12
Reset mode function 16-11
Set graphics rendition function
16-8
Set mode function 16-10
AnsiToOem 17-55
Asynchronous
communications 9-1
interrupt 15-70
memory cycles 13-40
notification routine 18-90
requests 18-89
serial communications interface
17-62
serial mouse interface 10-2

Index

Attribute code 7-6
Auto-initialize
DMA controller 4-4
Automatic LED control 15-108
Available (lRQ15) interrupt 15-151
B

BACKSPACE
to abort compose sequence 17-5
Base and current
address register 4-7
word register 4-8
Basic interrupt 15-132
Baud rate 9-16
mouse 10-2
Beep function 6-18
Begin virtual mode function 15-96
Bell sound 6-18
Bits
DMA controller
write all 4-11
write single mask 4-11
Block transfer mode
DMA controller 4-3
Boot block, DIGITAL hard disk
15-134
Bootstrap interrupt 15-133
Buffer overrun
LK250 keyboard responses 8-30
Bus 13-3
16-bit expansion 2-9
16-bit local 2-9
8-bit expansion 2-9
arbitration 13-3
master mode 13-40
slave mode 13-40
timing and structure 2-9

2 Index

Button position 10-3
C

C programming language
subroutines A-I
Call function for session 18-105
Call-back
for datalink
line state change 18-9
user 18-8
for LAT 18-58
Cancel
alarm function 15-140
function for session 18-97
Cascade mode
o MA controller 4-4
Case conversion tables 16-29
Cassette input/output interrupt 15-88
Change register 11-6
Character
code 7-6
count 17-77
count function 15-114
pattern 7-9
position mapping 7-7
set provided in the custom font
17-74
Check for presence of session 18-96
ClearCommBreak 17-65
Clock tick interrupt 15-5
Close
datalink portal 18-20
device function 15-89
LAT session 18-67
CloseComm 17-64
CloseLat 17-68
CMOS configuration
updated 14-10

CMOS RAM
shutdown byte read during hard
reset 14-13
Coax transceiver interface 13-2
Color
map functions 15-32
select register 7-39
COMlIserial interrupt 15-6
COM2/modem interrupt 15-6
Combination keys 15-107
break 15-108
extended self-test 15-108
pause 15-108
print screen 15-108
system request key 15-107
system reset 15-107
Commands
counter-latch. three-channel
counter and speaker 6-12
disable keyboard, keyboardinterface controller 8-12
diskette drive controller 11-19
enable keyboard, keyboardinterface controller 8-12
incremental stream mode (mouse)
10-3
interface test. keyboard-interface
controller 8-12
invoke self-test (mouse) 10-3
keyboard-interface controller 8-9
mouse (table) 10-2
prompt mode (mouse) 10-3
pulse output port, keyboardinterface controller 8-12
read port 1, keyboard-interface
controller 8-12
read port 2, keyboard-interface
controller 8-13
read test inputs, keyboardinterface controller 8-13
read-back, three-channel counter
and speaker 6-13

read. keyboard-interface controller
8-10
self-test 8-12
vendor reserved function (mouse)
10-3
write port 2 8-13
write status register 8-13
write. keyboard-interface controller
8-10
Command and result register sets
diskette drive controller 11-20
Command codes
disable autorepeat 8-24
disable key scanning and restore
to defaults 8-28
echo 8-26
enable autorepeat 8-24
enable key scanning 8-28
enter DIGITAL extended scan
code mode 8-23
exit DIGITAL extended scan code
mode 8-23
invalid commands 8-23
keyboard mode lock 8-25
keyboard mode unlock 8-25
LEOs on/off 8-26
LK250 keyboard 8-22
request keyboard id 8-23
resend 8-29
reserved 8-25, 8-26. 8-29
reset 8-29
reset keyboard led 8-24
restore to defaults 8-28
set autorepeat delay and rate 8-27
set keyboard led 8-23
set keyclick volume 8-24
Command register 4-9. 10-12. 12-10
keyboard-interface controller 8-5.
8-9
Command state
diskette drive controller 11-18
Communications 17-61

Index 3

connector signals 9-19
extended self-test loopback test
14-10
full asynchronous parallel 17-61
full asynchronous serial 17-61
LAT support 17-62
Communications functions
ClearCommBreak 17-65
CloseComm 17-64
EscapeCommFunction 17-65
FlushComm 17-65
GetCommError 17-66
GetCommEventMask 17-65
GetCommState 17-65
OpenComm 17-63
ReadComm 17-64
SetCommBreak 17-65
SetCommEventMask 17-65
SetCommState 17-65
TransmitCommChar 17-64
WriteComm 17-63
Compose sequences 16-23, 17-4
aborting 17-5
default set 17-5
handling 17-4
how recognized 16-23
pointer table
format 16-24
use 16-24
translation table
format 16-24
use 16-24
two key 17-5
Configuration list 14-11
display 14-11
Console server identify self 18-42
Constant values
DMA controller
programming example 4-15
Control Panel 17-6
Control register 11-3
register A 7-41

4 Index

register B 7-43
registers 7-3, 7-41, 7-43
Control signals
speed indicator 9-17
speed select 9-17
Control word register 6-11
Controller
functions 13-2
keyboard-interface 8-1
Counter and speaker example 6-20
Counter signals 6-3
Counter-latch command
three-channel counter and speaker
6-12
CPU 13-3
Creating keyboard map tables 16-22
CRT Controller 7-3
CRTC registers
data 7-25
index 7-25
register RO 7-28
register R1 7-28
register RIO 7-33
register R11 7-34
register R12 7-34
register R13 7-34
register R14 7-35
register R15 7-35
register R16 7-36
register R17 7-36
register R2 7-29
register R3 7-29
register R4 7-30
register R5 7-30
register R6 7-31
register R7 7-31
register R8 7-3
register R9 7-33
Crystal oscillator 13-4
CTI - see coax transceiver interface

13-2
Ctrl and Alt keys
Del keys used for soft reset 14-12
with Home key for diagnostics
14-10
Cursor control functions 16-5
Custom LAT application interface
17-66
Cylinder number
high register 12-S
low register 12-S
D

.DEF files 17-10, 17-72
ID for LAT IS-55
Data
controller 13-3
link interface 13-1
structures accessed by LANCE
13-3
transfer 13-40
Data exchange for LAT 18-58
Data registers 7-39, 11-5, 12-3
accessing 7-26
keyboard-interface controller S-5
Data structures
DMA controller
programming example 4-17
Data transfers
DMA controller 4-4
rate register 11-6
Datagrams 18-113
defined 18-83
Datalink communication block (DCB)
18-7
functions 18-11
close a portal 18-20
deallocate buffer 18-26

disable a channel 18-38
disable multicast address 18-22
enable a channel 18-37
enable multicast address 18-21
external loopback 18-41
initialization 18-15
MOP start and send system ID
18-45
MOP stop 18-45
network boot request 18-36
open a portal 18-17
read channel status 18-27
read counters 18-32
read DECparm address 18-39
read portal list 18-29
request transmit buffer 18-25
set DECparm string address
18-40
transmit 18-23
overview 18-5
parameters 18-16
port driver 18-5
program example 18-46
read portal status 18-30
receive 18-10
return codes 18-12
transmit 18-10
user call-back routines 18-8
Date and time structure 16-3, 16-4
Dead diacritical keys 16-24, 17-4
how recognized 16-24
Deallocate buffer for datlink 18-26
DEC private RAM
powerup test checks 14-8
decfuncadd 18-120
decfunccheck 18-119
decfuncdelall 18-126
decfuncdelname 18-122
decfuncdelnum 18-121
decfuncreadindex 18-125

Index 5

decfuncreadname 18-124
decfuncreadnum 18-123
DecGetKbdCountry 17-8
DECnet DOS session level interface
13-1
DECparm address string 18-40
DecSetAutorep 17-7
DecSetComposeState 17-5, 17-9
DecSetKClickVol 17-7
DecSetLockState 17-6
DecSetNumlockMode 17-10
DECWIN.H 17-85
Delete
entry given node name for session
18-122
entry given node number for
session 18-121
name for session 18-102
node entries for session 18-126
Demand transfer mode
DMA controller 4-3
Device is busy function 15-98
Diagnose command 12-21
Diagnostic initialization procedure
14-12
hardware initialized 14-12
memory sized 14-12
Diagnostic loopback 9-10
Diagnostics
extended self-test 14-10
hard reset 14-13
keyboard-interface controller 8-4,
8-12
powerup test 14-1, 14-8
processor board tests 14-14
ROM 14-1, 14-8
ROM extended self-test 14-10
soft reset 14-12

6 Index

DIGITAL
function check for session 18-119
hard disk boot block 15-134
input register 12-26
session control block IDSCBI
18-85, 18-88
session functions 18-118
DIGITAL extended functions
extended codes and functions
15-116
set modem control 15-85
DIGITAL extension functions
character count 15-114
extended mode 15-77
key notification 15-111
keyboard buffer 15-115
keyboard table pointers 15-120
parallel port retry 15-131
printer type 15-129
redirect parallel printer 15-127
request keyboard id 15-118
retry on timeout error 15-86
return days-since-read counter
15-140
return DIGITAL configuration
word 15-99
send break 15-84
send to keyboard 15-119
set baud rate 15-87
DIGITAL extension interrupts
basic 15-132
bootstrap 15-133
local area network controller
ILANCE) 15-149
mouse port 15-150
Direct memory access and LANCE
13-3
Disable
autorepeat keyboard-interface controller command codes 8-24
channel for datalink 18-38
key scanning and restore to

defaults 8-28
keyboard command 8-12
multicast address for datalink
18-22
Disk input/output (110) interrupt
15-38
hard disk errors 15-40
hard disk functions 15-40
hard disk parameter tables 15-41
Disk parameters 16-14
Diskette
errors 15-59
functions 15-59
parameter tables 15-59
interrupt 15-143
Diskette drive controller
change register 11-6
command and result register state
11-20
command register 11-7
command state 11-18
commands 11-19
control register 11-3
D 11-17
data register 11-5
data transfer rate registers 11-6
DMA mode 11-1
DTL 11-16
EOT 11-16
execution state 11-20
extended self-test loopback test
14-10
GPL 11-16
H 11-15
head/unit select register 11-8
hlt/nd 11-15
internal registers 11-7
main status register 11-4
N 11-16
NCN 11-17
operational states 11-18
PCN 11-17
programming 11-18

programming example 11-27
R 11-15
register sets for
format track 11-24
read data 11-21
read deleted data 11-22
read id 11-23
read track 11-23
recalibrate 11-26
scan equal 11-24
scan high or equal 11-25
scan low or equal 11-25
seek 11-27
sense drive status 11-27
sense interrupt status 11-26
specify 11-26
write data 11-21
write deleted data 11-22
registers 11-2
result state 11-20
result state
invalid commands 11-20
SC 11-16
srt/hut 11-14
status register 0 11-9
status register 1 11-10
status register 2 11-12
status register 3 11-13
STP 11-17
Diskettes
extended self-test use of 14-10
DispatchMessage 17-4
Display
on VAXmate 17-73
processor 7-3
Divisor latches 9-15
DLL.EXE 18-5
dll close 18-20
dll deallocate 18-26
dll disable chan 18-38
dll- disable- mul 18-22

Index 7

dll enable chan 18-37
dll enable mul 18-21
dll_ext)oopback 18-41
dll init 18-16
dll network boot 18-36
dll_open 18-17
dll_readecparm 18-39
dB read chan 18-27
dB read counters 18-32
- dll_read_plist 18-29
dB_read_portal 18-30
dllJequest_xmit 18-26
dll_setdecparm 18-40
dB transmit 18-23
DMA channel programming examples for
disabling 4-22
DMA controller
active cycle 4-3
address generation 4-6
auto-initialize 4-4
base and current address register
4-7
base and current word register 4-8
block transfer mode 4-3
cascade mode 4-4
command register 4-9
data transfer 4-4
demand transfer mode 4-3
idle cycle 4-3
mode 4-12
modes and restrictions 4-1
operation 4-2
priorities 4-6
programming example 4-16
data structures 4-17
disabling DMA channel 4-22
initializing 4-18
opening D MA channel 4-19

8 Index

preparing DMA channel 4-20
registers 4-7
request register 4-13
single transfer mode 4-3
states 4-2
status register 4-11
temporary register 4-14
write all mask bits 4-11
write single mask bit 4-11
DMA mode 11-1
DRQ 13-40
E

Echo
keyboard-interface controller command codes 8-26
LK260 keyboard responses 8-30
Edit keypad 17-3
Enable
autorepeat 8-24
channel for datalink 18-37
key scanning 8-28
keyboard command 8-12
multicast address for datalink
18-21
Enable/disable
266 character graphic font function 15-30
additional key codes 17-77
End-of-interrupt command
issuing 3-26
Enter
DEC Mode 17-76
DIGITAL extended scan code
mode 8-23
Erase functions 16-7
Error handling
keyboard-interface controller 8-14
LK260 keyboard 8-31

Error register 12-5
EscapeCommFunction 17-65
Ethernet
CRC bits 13-3
preamble 13-3
sync pattern 13-3
transmission 13-8
Execute controller internal diagnostics function 15-56
Execution state
diskette drive controller 11-20
Exit
DEC Mode 17-76
DIGITAL extended scan code
mode 8-23
Expansion box
bus connectors 2-11
operating ranges 2-10
slot power ratings 2-10
technical specifications 2-10
Extended
codes and functions 15-116
mode function 15-77
scan code mode 17-2
Extended keyboard functions
enable/disable additional key codes
17-77
enter DEC mode 17-76
exit DEC mode 17-76
Extended keyboard functions (not
supported)
character count 17-77
get/set table pointer 17-78
key notification 17-77
keyboard buffer 17-77
request keyboard id 17-78
Extended self-test
CMOS configuration update 14-10
diskette drive controller 14-10
double-sided, high-intensity disks
used in 14-10

firmware diagnostics 14-10
hardware initialization 14-10
horizontal bar 14-10
loopback test
on communications 14-10
on mouse serial ports 14-10
on printer 14-10
memory sized 14-10
real-time clock 14-10
video failures 14-10
External loopback 18-41
F

Fetch next character from keyboard
17-75
File structure
LCOUNTRY 16-27
Firmware diagnostics
error codes 14-8
error values 14-8
extended self-tests 14-10
horizontal bar 14-8, 14-10
initialization procedure 14-8
ROM BIOS and 14-8
self-tests 14-8
Fixed disk register 12-25
Fixed priority
DMA controller 4-5
Floppy disk interrupt 15-7
Flow control for LAT 18-58
FlushComm 17-65
Focus
changing for repeating key 17-11
FONT 16-15
Font file structure
FONT. COM 16·17
GRAFTABL.COM 16·18
Font files

Index 9

loading 16-19
Font RAM
accessing 7-9
color map support function 15-31
functions 15-31
programming 7-9
Font sizes
terminal emulation 17-73
FONT. COM
affect on KEYB.COM 16-16
affect on SORT.EXE 16-16
font file structure 16-17
Fonts
description 16-16
Format track 15-66
command 12-17
function 15-47
diskette drive controller
register sets 11-24
Functional description of network
hardware interface 13-2
Functions
datalink 18-11
interrupt vector A-12
LAT 18-64
retrieving characters from a ring
buffer A-16
session 18-91
DIGITAL-specific 18-118
storing characters in a ring buffer
A-16
support for example programs
A-18
GDI 17-2
printer support 17-83
Get
Country Code Function 16-3
current date and time for 5MB
18-128
MS-DOS OEM Number Function
16-3

10 Index

next LAT service name 18-70
status for LAT 18-65
Get/Set Table Pointer 17-78
GetCommError 17-66
GetCommEventMask 17-65
GetCommState 17-65
GetLatService 17-71
GetLatStatus 17-69
GetMessage 17-4
GRAFTABL 16-16
GRAFTABL.COM
font file structure 16-18
Graphics
character table pointer interrupt
15-145
device interface 17-2
format memory maps 7-10
mode 7-10
H

Hangup for session 18-108
Hard disk
boot block, DIGITAL 15-134
interrupt 15-151
parameter tables interrupt 15-146
reset function 15-53
types 16-13
Hard disk controller
alternate status register 12-25
command register 12-10
cylinder number high register 12-8
cylinder number low register 12-8
data register 12-3
diagnose command 12-21
DIGITAL input register 12-26
error register 12-5
features 12-1
fixed disk register 12-25

format track command 12-17
programming example 12-27
read sector command 12-13
read verify command 12-19
registers 12-1
restore command 12-11
SDH register 12-9
sector count register 12-7
sector interleave 12-18
sector number register 12-7
seek command 12-12
set parameters command 12-22
status register 12-23
write precompensation register
12-4
write sector command 12-15
Hard reset 14-13
causes 14-13
shutdown byte 14-13
Hardware
extended self-test 14-10
initializing 14-8
retriggable one-shot 6-4
starting with CtrllAltlDel 14-12
system tests at startup 14-1
triggered strobe 6-7
Hardware interrupts
80287 error 15-151
available (lRQ15) 15-151
clock tick 15-5
COMlIserial 15-6
COM2/modem 15-6
floppy disk 15-7
hard disk 15-151
keyboard 15-5
local area network controller
ILANCE) interrupt 15-149
mouse port 15-150
nonmaskable interrupt 15-3, 15-76
real-time clock 15-148
redirect to interrupt OAH 15-148
serial printer port 15-150

110 cycle, wait states introduced by
LANCE 13-40
ICONEDIT.EXE 17-83
Icons
unique 17-83
Idle cycle
DMA controller 4-3
IEEE 802.3 specification 13-2, 13-4
10BASE2 specifications 13-40
Illogical keyboard messages 17-12
In-service register 3-16
Include files
LK250 keyboard A-10
ring buffer control structure A-11
structure declaration A-9
Incremental stream mode command
10-3
Index register
accessing 7-26
Industry-standard functions
begin virtual mode 15-96
cancel alarm 15-140
close device 15-89
device is busy 15-98
diskette
errors 15-59
functions 15-59
parameter tables 15-59
enable/disable 256 character
graphic font 15-30
execute controller internal diagnostics 15-56
font RAM and color map support
15-31
format a track 15-47, 15-66
hard disk reset 15-53
initialize

Index

asynchronous port 15-72
diskette subsystem 15-61
drive characteristics 15-49
entire disk subsystem 15-42
printer 15-125
interrupt completion handler 15-98
keyboard input 15-109
keyboard state 15-110
keyboard status 15-109
move a block of memory 15-93
open device 15-89
read
character and attribute at
cursor position 15-19
current video state 15-27
cursor position 15-14
long 15-50
long 256 byte sector 15-58
one or more disk sectors 15-44
one or more track sectors 15-63
pixel 15-24
real-time clock 15-137
system clock 15-136
recalibrate drive 15-55
receive character 15-74
return
asynchronous port status 15-75
change line status 15-68
current drive parameters 15-48
drive type 15-57, 15-67
printer status 15-126
RTC date 15-138
size above one megabyte 15-95
status code of last 110 request
15-43, 15-62
seek to specific cylinder 15-52
service system request key 15-91
set
a wait interval 15-90
alarm 15-139
color palette 15-22
cursor position 15-13
cursor type 15-12
page 15-16

12 Index

real-time clock 15-138
RTC date 15-139
system clock 15-136
termination 15-90
test drive ready 15-54
transmit character 15-73,15-124
TTY write string 15-28
verify one or more disk sectors
15-46
verify one or more track sectors
15-65
wait (no return to user) 15-92
write
character and attribute at
cursor position 15-20
character at cursor position
15-21
character using terminal emulation 15-25
long 15-51
one or more disk sectors 15-45
one or more track sectors 15-64
pixel 15-23
Industry-standard functions with
DIGITAL extensions
set drive and media type for
format 15-69
set video mode 15-10
Industry-standard interrupts
80287 error 15-151
available (lRQ15) 15-151
diskette parameter tables 15-143
floppy disk 15-7
hard disk 15-151
hard disk parameter tables 15-146
keyboard break 15-141
nonmaskable interrupt 15-3, 15-76
print screen 15-4
read configuration 15-35
read light-pen position 15-15
real-time clock 15-148
redirect to interrupt OAH 15-148
return memory size 15-37

revector of interrupt 13H 15-145
RTC alarm 15-148
serial printer port 15-150
timer tick 15-141
video parameters 15-142
Industry-standard interrupts with
DIGITAL extensions
asynchronous communications
15-70
cassette input/output 15-88
clock tick 15-5
COMlIserial 15-6
COM2/modem 15-6
disk input/output (I/O) 15-38
graphics character table pointer
15-145
keyboard 15-5
keyboard input 15-101
printer output 15-123
video input/output 15-8
time-of-day 15-135
Initialization for datalink 18-15
Initialize
asynchronous port 15-72
diskette subsystem 15-61
drive characteristics 15-49
entire disk subsystem 15-42
printer 15-125
Input/output registers
video processor 7-22
InquireLatServices 17-70
Installing
ANSI.SYS 16-5
options, extended self-test 14-10
INT 11H support 17-82
INT 12H support 17-82
INT 15H support 17-83
Interface
signals, monitor 7-44
test command, keyboard-interface
controller 8-12

Internal registers
diskette drive controller
C 11-15
command 11-7
D 11-17
DTL 11-16
EOT 11-16
GPL 11-16
H 11-15
head/unit select 11-8
hlt/nd 11-15
N 11-16
NCN 11-17
PCN 11-17
R 11-15
SC 11-16
srt/hut 11-14
status register 0 11-9
status register 1 11-10
status register 2 11-12
status register 3 11-13
STP 11-17
International support
FONT 16-15
GRAFTABL 16-16
Interrupt
completion handler function 15-98
enable register 9-4
identification register 9-6
line status 9-10
modem status 9-10
on terminal count
three-channel counter and
speaker mode 6-4
Interrupt
2A 18-83, 18-91
6A 18-64
6D 18-11
Interrupt 21H
function 30H 16-3
function 38H 16-3
Interrupt

Index

address map 2·6
controller register, accessing 3·4
controllers, programming example
3·21
line, IRQI0 13·40
processing 3·18
request lines 3·2
request register 3·16
Invalid commands
keyboard·interface controller com·
mand codes 8·23
Invoke self·test command 10·3

J
Joystick support function 15·91
Jumpers
processor board testing 14·14
K

Kernel 17·2
Key buffering notification enabled
15·113
Key combinations 15·107
break 15·108
extended self·test 15·108
pause 15·108
print screen 15·108
system request key 15·107
system reset 15·107
Key mappings
LK25017·13
Key notification 17·77
enabled 15·112
function 15·111
KEYB.COM. 16·19
how affected by FONT. COM 16·16
Keyboard
break interrupt 15·141
14 Index

buffer interface 8·1
buffer function 15·116
driver 17·2
illogical messages 17·12
input function 15·109
input interrupt 15·101
interface lines 8·12
interrupt 15·5
key reassignment function 16·12
layout, LK250 15·103
LEDs 17·4
LK250 17·2, 8·1
map file structure 16·26
map tables
creating 16·22
MS· Windows extensions 17·5
processing anomalies 17·11
scan codes 15·104
setting user preferences 17·6
state function 15·110
status function 15·109
table pointers function 15·120
translation 15·121
Keyboard extensions
DecGetKbdCountry 17·8
DecSetAutorep 17·7
DecSetClickVol 17·7
DecSetComposeState 17·9
DecSetLockState 17·6
DecSetNumlockMode 17·10
enable/disable autorepeat 17·6
return keyboard nationality 17·6
select compose processing 17·6
select Numlock processing 17·6
set keyclick volume 17·6
set Shift key 17·6
Keyboard handling
inside a window 17·75
outside a window 17·78
Keyboard mode
lock 8·25
toggling 17·4
unlock 8·25
Keyboard remapping 16·19

Keyboard-interface controller 8-1
command byte bit definitions 8-10
command codes
disable autorepeat 8-24
disable key scanning and restore
to defaults 8-28
echo 8-26
enable autorepeat 8-24
enable key scanning 8-28
enter DIGITAL extended scan
code mode 8-23
exit DIGITAL extended scan
code mode 8-23
invalid commands 8-23
keyboard mode lock 8-25
keyboard mode unlock 8-25
LEOs on/off 8-26
request keyboard id 8-23
resend 8-29
reserved 8-25, 8-26, 8-29
reset 8-29
reset keyboard led 8-24
restore to defaults 8-26
set autorepeat delay and rate
8-27
set keyboard led 8-23
set keyclick volume 8-24
command register 8-5, 8-9
commands 8-9
data registers 8-5
diagnostics 8-4
disable keyboard 8-12
enable keyboard 8-12
error handling 8-14
interface test 8-12
keyboard responses
acknowledge 8-31
buffer overrun 8-30
echo 8-30
release prefix 8-31
resend 8-31
self-test failure 8-31
self-test success 8-30
physical interface

to the CPU 8-1
to the keyboard 8-1
port bit definitions 8-3
pulse output port 8-13
read port 1 8-12
read port 2 8-13
read test inputs 8-13
self-test 8-12
status register 8-6
write port 2 8-13
write status register 8-13
Keypad
edit 17-3
numeric 17-3
Keys
Numlock 17-3
reserved under MS-Windows 17-5
L

LANCE
broadcast address 13-22
buffer descriptors, see LANCE
message descriptors 13-27
buffer management 13-17
control and status registers 13-3
control register 13-3
CRC 13-22
CSRO 13-5, 13-6, 13-7, 13-8, 13-18
CSRO-CSR3 13-5
CSR1 13-4, 13-5, 13-6, 13-7, 13-13
CSR2 13-4, 13-5, 13-6, 13-7, 13-14
CSR3 13-4, 13-6, 13-7, 13-15
CSRs 13-5
data buffers 13-3, 13-4
data chaining 13-27
data structures 13-3
descriptor entry 13-27
descriptor rings 13-4
Ethernet data stream 13-27
initialization block 13-3, 13-18,
13-27

Index

base address 13-18
mode 13-19
logical address filter field 13-22
logical address mask 13-4
message descriptors 13-27
mode of operation 13-4
physical address field 13-19
physical address mask 13-4
polling 13-27
programming 13-3
programming sequence 13-4
receive and transmit descriptor
rings 13-3, 13-4, 13-28
location of 13-4
number of entries 13-4
receive descriptor ring pointer
field 13-23, 13-24
receive descriptor rings
receive message descriptor 1,
rmd1 13-30, 13-27
receive mode 13-3
register address port 13-5, 13-7
register data port 13-5, 13-6
RMD2 13-32
RMD313-33
status register 13-3
TMDO 13-34
TMD1 13-35
TMD213-37
TMD313-38
transmit
descriptor ring pointer 13-25
message descriptors 13-27
mode 13-3
LANCE - see Local Area Network
Controller 13-2
LANCE interrupt 15-149
LAT
ID switch 18-55
IG switch 18-56
IR switch 18-56
call-back routine 18-58, 18-60
closing a session 18-58
command line 18-555

16 Index

custom application interface 17-66
data exchange 18-58
flow control 18-58
functions 18-64
close session 18-67
get next service name 18-70
get status 18-65
open session 18-66
read data 18-68
send break signal 18-72
send data 18-69
service table reset 18-71
overview 18-54
program example 18-73
service directory 18-56
session control block 18-59
session start 18-57
session status word 18-63
slots 18-57
LAT control blocks 17-62
LAT functions
CloseLat 17-68
GetLatService 17-71
GetLatStatus 17-69
InquireLatServices 17-70
OpenLat 17-67
ReadLat 17-68
SendLatBreak 17-70
WriteLat 17-69
LAT support 17-62
Latches, divisor 9-15
LCB 17-62
number available 17-62
LCOUNTRY 16-27
file structure 16-27
LEDs 17-4
automatic control 15-108
color indications 14-8
during powerup test 14-8
110 board 14-8
memory board option 14-8

processor board 14-8
supported 17-4
LEDs on/off
keyboard-interface controller command codes 8-26
Line
control register 9-7
LAT state change call-back 18-9
status interrupt 9-10
status register 9-11
Listen for session 18-107
LK250 keyboard 8-1, 17-2
command codes 8-22
control functions 8-3
error handling 8-31
key mappings 17-13
layout 15-103
logical interface 8-2
pass-through mode 8-2
physical interface 8-2
programming example 8-46
responses 8-30
acknowledge 8-31
buffer overrun 8-30
echo 8-30
release prefix 8-31
resend 8-31
self-test failure 8-31
self-test success 8-30
scan codes 8-15
and industry-standard equivalent
values 8-17
translated but not used 8-21
system powerup 8-2
translate mode 8-2
U. S. and foreign legends 8-31
Loadable device drivers
ANSI.SYS 16-5
Loading font files 16-19
Local area network controller 13-2
(LANCE) interrupt 15-149
Local Area Transport

see LAT 18-54
Loop services 18-42
Loopbacks
diagnostic 9-10
M

Main status register 11-4
Maintenance operations protocol
console server identify self 18-42
loop services 18-42
network boot request 18-43
remote read counters 18-43
Mapping
asynch serial comm devices to
LAT services 17-62
character position 7-7
input/output 2-4
interrupt address 2-6
memory 2-3
Memory
sizing
and initializing 14-8
during extended self-test 14-10
without initializing 14-12
use in real mode 14-8
use in virtual protected mode 14-8
three-channel counter and speaker
6-3
Memory map
physical 2-3
Messages
illogical keyboard 17-12
Mode register, 4-12
1 10-10
2 10-11
Mode-dependent values
set cursor type function 15-12
Modem
connector signals 9-21

Index 17

control register 9-9
programming exceptions 9-17
status interrupt 9-10
status register 9-13
Monitor
interface signals 7-44
specifications 7-44
MOP 18-42
start and send system ID 18-45
stop 18-45
Mouse 10-1, 17-61
asynchronous serial interface 10-2
baud rates 10-2, 10-11
button position 10-3
commands (table) 10-2
communication 10-2
data bytes 10-2
encoders 10-1
extended self-test loopback test
serial ports 14-10
incremental stream mode command 10-3
invoke self-test command 10-3
movement 10-3
port interrupt 15-150
position 10-3
programming example 10-14
prompt mode command 10-3
reports 10-4 - 10-7
request mouse position command
10-3
self-test 10-3
serial interface 10-2, 10-8
command register 10-12
mode register 1 10-10
mode register 2 10-11
status register 10-9
serial interface registers 10-8
transmit holding register and
receive buffer 10-8
Signetics
SCN2261 enhanced
programmable communications
interface 10-2, 10-8
18 Index

transmit holding register and receive buffer 10-8
vendor reserved function command
10-3
Mouse reports
position (byte 1) 10-4
position (byte 2) 10-5
position (byte 3) 10-5
self-test (byte 1) 10-6
self-test (byte 2) 10-6, 10-7
self-test (byte 3) 10-7
Move a block of memory 15-93
Movement 10-3
MS-DOS Date and Time Structure
16-3, 16-4
MS-Network
compatible session services 18-92
session level interface 13-1
MS-Windows
applications programming interface 17-2
entry points
AnsiToOem 17-55
OemToAnsi 17-58
Mulicast address
enable 18-21
disable 18-22
format 18-7
Multiplex messages 18-6
N

Name status for session 18-103
Network
addressing 18-90
boot request 18-36, 18-43
hardware interface 13-1
interconnect, CSR 13-17
Network interface 13-2
CSR 13-5
external interconnect 13-40

physical 110 ports 13-5
register description 13-5
system bus interconnect 13-40
Network software 18-1
components 18-2
datalink 18-5
overview 18-2
NI - see Network Interface 13-2
NI CSR 13-40
No return to user function 15-92
Nonmaskable interrupt 15-3, 15-76
Normal keyboard functions
fetch next character input from
keyboard 17-75
return current shift status 17-76
test for character available 17-75
Not supported functions
joystick support 15-91
Numeric keypad 17-3
Numlock
toggling numeric keypad 17-3

o
OemToAnsi 17-58
Open
datalink portal 18-17
device function 15-89
LAT session 18-66
OpenComm 17-63
OpenLat 17-67
Operational states
diskette drive controller 11-18
p

Parallel
bit stream, converted by LANCE
13-3

port retry function 15-131
Parameters
disk 16-14
Pass-through mode
keyboard 8-2
Peripheral interrupt controller
initializing 3-24
Pointer
diskette parameter tables 15-143
graphics character table pointer
15-145
hard disk parameter tables 15-146
video parameters 15-142
Poll command 3-17
Port driver 18-5
Portal
close 18-21
defined 18-5
read list 18-29
read status 18-30
Powerup test 14-1, 14-8
LEDs 14-8
RAM checks 14-8
self-test error codes 14-8, 14-10
sequence 14-1
Print screen 15-4
Printer
connector signals 9-20
extended self-test loopback test
14-10
GDI support 17-83
output interrupt 15-123
to Host mode C-12
type function 15-129
Priorities
DMA controller 4-5
rotation 3-13
Processor board
testing 14-14
Processor modes
real mode 14-8

Index 19

virtual protected mode 14-8
Programming
diskette drive controller 11-18
Programming examples
counter and speaker 6-20
datalink 18-46
diskette drive controller 11-27
DMA controller 4-15
constant values 4-15
data structures 4-17
disabling DMA channel 4-22
initializing 4-18
opening DMA channel 4-19
preparing DMA channel 4-20
interrupt controllers 3-21
LAT 18-73
LK250 keyboard 8-46
mouse 10-14
real-time clock 5-15
three-channel counter/timer 6-16
UART (8250A) 9-22
video controller 7-45
modem control 9-17
Prompt mode command 10-3
Pulse output port command
keyboard-interface controller 8-13
R
RAM
system
powerup test checks 14-8
Rate generator 6-5
Read
channel status for datalink 18-27
character and attribute at cursor
position function 15-19
command 8-10
configuration interrupt 15-35
current video state function 15-27
cursor position function 15-14

20 Index

data command 11-21
data for LAT 18-68
datalink counters 18-32
DECparm string address 18-39
deleted data command 11-22
id command 11-23
light-pen position function 15-15
long 256 byte sector 15-58
long function 15-50
node entry given index for session
18-125
node entry given node name for
session 18-124
node entry given node number for
session 18-123
one or more disk sectors function
15-44
one or more track sectors 15-63
pixel function 15-24
port 1 command 8-12
port 2 command 8-13
portal list for datalink 18-29
portal status for datalink 18-30
real-time clock function 15-137
sector command 12-13
system clock function 15-136
test inputs command 8-13
track command 11-23
verify command 12-19
Read-back command
three-channel counter and speaker
6-13
ReadComm 17-64
ReadLat 17-68
Real mode 14-8
Real-time clock
address map 5-3
addressing 5-2
alarm registers 5-12
ahtomatic alarm cycles 5-12
avoiding update cycles 5-13
battery backup source 5-2

data register ranges 5-11
data registers 5-10
extended self-test 14-10
features 5-1
interrupts 5-14
programming example 5-15
register A 5-4
register B 5-6
register C 5-8
register D 5-9
registers 5-3
update cycle 5-13
Real-time clock interrupt 15-148
Recalibrate command
diskette drive controller
register sets 11-26
Recalibrate drive function 15-55
Receive
any for session 18-112
broadcast for session 18-11 7
buffer/transmitter holding register
9-3
character function 15-74
datagram for session 18-115
for datalink 18-10
for session 18-111
message descriptor, see RMD
13-29
Redirect
parallel printer function 15-127
to interrupt OAH interrupt 15-148
Redirector 18-84
Register sets
format track command 11-24
read data command 11-21
read deleted data command 11-22
read id command 11-23
read track command 11-23
recalibrate command 11-26
scan equal command 11-24
scan high or equal 11-25
scan low or equal 11-25

seek command 11-27
sense drive status command 11-27
sense interrupt status command
11-26
specify command 11-26
write data command 11-21
write deleted data command 11-22
Registers
8250A UART 9-2
diskette drive controller 11-2
C 11-15
change 11-6
control 11-3
D ll-17

data 11-5
data transfer rate 11-6
DTL 11-16
EOT 11-16
GPL 11-16
H 11-15
head/unit select 11-8
hlt/nd 11-15
internal 11-7
main status 11-4
N 11-16
NCN 11-17
PCN 11-17
R 11-15
SC 11-16
srt/hut 11-14
status register 0 11-9
status register 1 11-10
status register 2 11-12
status register 3 11-13
STP 11-17
DMA controller 4-7
base and current address 4-7
base and current word 4-8
command 4-9
mode 4-12
request 4-13
status 4-14
temporary 4-14
interrupt enable 9-4

Index 21

interrupt identification 9-6
keyboard-interface command 8-9
keyboard-interface controller
command 8-5
data 8-5
status 8-6
line control 9-7
line status 9-11
modem control 9-9
modem status 9-13
receive buffer/transmitter holding
9-3
special purpose 9-18
three-channel counter and speaker
6-8
control 6-11
system 6-9
video controller
color select 7-39
control register A 7-41
control register B 7-43
status 7-37, 7-38
write data 7-39
Release prefix
LK250 keyboard responses 8-31
Remapping
keyboard 16-19
Remote read counters 18-43
Repeating key
changing focus 17-11
Request
line, DMA 13-40
mouse position command 10-3
register 4-13
transmit buffer for datalink 18-25
Request keyboard id 17-78
function 15-118
keyboard-interface controller command codes 8-23
Resend
keyboard-interface controller command codes 8-29

Index

LK250 keyboard responses 8-31
Reserved
keyboard-interface controller command codes 8-25, 8-26, 8-29
Reset
for session 18-98
keyboard-interface controller command codes 8-29
keyboard led
keyboard-interface controller
command codes 8-24
mode function 16-11
processor 14-13
Restore command 12-11
Restore to defaults
keyboard-interface controller command codes 8-28
Result state
diskette drive controller 11-20
Retry on timeout error 15-86
Return
asynchronous port status function
15-75
change line status function 15-68
current drive parameters function
15-48
current shift status flag 17-76
days-since-read counter function
15-140
DIGITAL configuration word
15-99
drive type function 15-57, 15-67
keyboard nationality 17-6
memory size above one megabyte
function 15-95
memory size interrupt 15-37
printer status function 15-126
RTC date function 15-138
status code of last 110 request
15-62, 15-43
Return codes

datalink 18-12
session 18-93
Revector of interrupt 13H interrupt
15-145
RMDO 13-29
ROM BIOS
available (IRQ15) interrupt 15-151
basic interrupt 15-132
bootstrap interrupt 15-133
clock tick interrupt 15-5
COMlIserial interrupt 15-6
COM2/modem interrupt 15-6
during soft reset 14-12
firmware diagnostics and 14-8
initialization procedure 14-12
loading operating system 14-12
local area network controller
(LANCE) interrupt 15-149
mouse port interrupt 15-150
nonmaskable interrupt 15-3, 15-76
print screen interrupt 15-4
read configuration interrupt 15-35
real-time clock interrupt 15-148
redirect to interrupt OAH interrupt 15-148
return memory size interrupt
15-37
revector of interrupt 13H interrupt
15-145
RTC alarm interrupt 15-148
serial printer port interrupt 15-150
ROM BIOS 80287 error interrupt
15-151
ROM BIOS asynchronous communications interrupt 15-70
extended mode 15-77
initialize asynchronous port function 15-72
receive character 15-74
retry on timeout error 15-86
return asynchronous port status
15-75
send break 15-84

set baud rate 15·87
set modem control 15-85
transmit character 15-73
ROM BIOS cassette input/output interrupt 15-88
begin virtual mode 15-96
close device 15-89
device is busy 15-98
interrupt completion handler 15-98
joystick support 15-91
move a block of memory 15-93
open device 15-89
return DIGITAL configuration
word 15-99
return memory size above one
megabyte 15-95
service system request key 15-91
set a wait interval 15-90
termination 15-90
wait (no return to user) 15-92
ROM BIOS disk 110 interrupt 15-38
diskette errors 15-59
diskette functions 15-59
diskette parameter tables 15-59
execute controller internal diagnostics 15-56
format track 15-47, 15-66
hard disk
errors 15-40
functions 15-40
parameter tables 15-41
reset function 15-53
initialize
diskette subsystem 15-61
drive characteristics 15-49
entire disk subsystem 15-42
read long 256 byte sector 15-58
read long 15-50
read one or more disk sectors 1544
read one or more track sectors 1563
recalibrate drive 15-55
return change line status 15-68

Index

return current drive parameters
15-48
return drive type 15-57, 15-67
return status code of last 110
request 15-43, 15-62
seek to specific cylinder 15-52
set drive and media type for
format 15-69
test drive ready 15-54
verify one or more disk sectors 1546
verify one or more track sectors
15-65
write long 15-51
write one or more disk sectors 1545
write one or more track sectors
15-64
ROM BIOS diskette
errors 15-59
functions 15-59
parameter tables 15-59
interrupt 15-143
ROM BIOS floppy disk interrupt
15-7
ROM BIOS graphics character table
pointer interrupt 15-145
ROM BIOS hard disk
interrupt 15-151
parameter tables interrupt 15-146
ROM BIOS initialization procedure
14-12
ROM BIOS interrupt
02H 15-3, 15-76
05H 15-4
08H 15-5
09H 15-5
OBH 15-6
OCH 15-6
OEH 15-7
llH 15-35
12H 15-37

24 Index

18H 15-132
19H 15-133
1BH 15-141
1CH 15-141
1DH 15-142
1EH 15-143
40H 15-145
41H 15-146
46H 15-146
4AH 15-148
70H 15-148
71H 15-148
72H 15-149
73H 15-150
74H 15-150
75H 15-151
76H 15-151
77H 15-151
ROM BIOS Interrupt 10H 15-8
enable/disable 256 character
graphic font 15-30
font RAM and color map support
15-31
read character and attribute at
cursor position 15-19
read current video state 15-27
read cursor position 15-14
read light-pen position 15-15
read pixel 15-24
scroll active page down 15-17
scroll active page up 15-17
set color palette 15-22
set cursor position 15-13
set cursor type 15-12
set page 15-16
set video mode 15-10
TTY write string 15-28
write character and attribute at
cursor position 15-20
write character at cursor position
15-21
write character using terminal
emulation 15-25

write pixel 15-23
ROM BIOS interrupt 13H 15-38
diskette errors 15-59
diskette functions 15-59
diskette parameter tables 15-59
execute controller internal diagnostics 15-56
format a track 15-47, 15-66
hard disk
errors 15-40
functions 15-40
parameter tables 15-41
reset 15-53
initialize
diskette subsystem 15-61
drive characteristics 15-49
entire disk subsystem 15-42
read long 256 byte sector 15-58
read long 15-50
read one or more disk sectors
15-44
read one or more track sectors
15-63
recalibrate drive 15-55
return
change line status 15-68
current drive parameters 15-48
drive type 15-57, 15-67
status code of last I/O request
15-43, 15-62
seek to specific cylinder 15-52
set drive and media type for
format 15-69
test drive ready 15-54
verify one or more disk sectors
15-46
verify one or more track sectors
15-65
write long 15-51
write one or more disk sectors
15-45
write one or more track sectors
15-64
ROM BIOS interrupt 14H 15-70

extended mode 15-77
initialize asynchronous port 15-72
receive character 15-74
retry on timeout error 15-86
return asynchronous port status
15-75
send break 15-84
set baud rate 15-87
set modem control 15-85
transmit character 15-73
ROM BIOS interrupt 15H 15-88
begin virtual mode 15-96
close device 15-89
device is busy 15-98
interrupt completion handler 15-98
joystick support 15-91
move a block of memory 15-93
open device 15-89
return digital configuration word
15-99
return memory size above one
megabyte 15-95
service system request key 15-91
set a wait interval 15-90
termination 15-90
wait {no return to user I 15-92
ROM BIOS interrupt 16H 15-101
character count 15-114
extended codes and functions
15-116
key notification 15-111
keyboard buffer 15-115
keyboard input 15-109
keyboard state 15-110
keyboard status 15-109
keyboard table pointers 15-120
request keyboard ID 15-118
send to keyboard 15-119
ROM BIOS interrupt 17H 15-123
initialize printer 15-125
parallel port retry 15-131
printer type 15-129
redirect parallel printer 15-127

Index 25

return printer status 15-126
transmit character 15-124
ROM BIOS interrupt lAH 15-135
cancel alarm 16-140
read real-time clock 16-137
read system clock 15-136
return
days-since-read counter 16-140
RTC date 16-138
set alarm 15-139
set real-time clock 15-138
set RTC date 15-139
set system clock 15-136
ROM BIOS interrupt vectors 15-1,
15-2
ROM BIOS keyboard
break interrupt 15-141
input interrupt 15-101
interrupt 15-5
character count 15-114
extended codes and functions
15-116
keyboard buffer 15-115
keyboard input 15-109
keyboard notification 15-111
keyboard state 15-11 0
keyboard status 15-109
keyboard table pointers 15-120
request keyboard 10 15-118
send to keyboard 15-119
ROM BIOS printer output interrupt
15-123
initialize printer 15-125
parallel port retry 15-131
printer type 15-129
redirect parallel printer 15-127
return printer status 15-126
transmit character 15-124
ROM BIOS time-of-day interrupt
15-135
cancel alarm 15-140
read real-time clock 15-137
read system clock 15-136

26 Index

return days-since-read counter
15-140
return rtc date 15-138
set alarm 15-139
set real-time clock 15-138
set rtc date 15-139
set system clock 15-136
ROM BIOS timer tick interrupt
15-141
ROM BIOS video
modes 15-10
parameters interrupt 16-142
ROM BIOS video input/output interrupt 15-8
enable/disable 256 character
graphic font 15-30
font RAM and color map support
15-31
functions 15-9
read character and attribute at
cursor position 15-19
read current video state 15-27
read cursor position 15-14
read light-pen position 15-15
read pixel 15-24
scroll active page down 15-17
scroll active page up 15-17
set color palette 15-22
set cursor position 15-13
set cursor type 15-12
set page 15-16
set video mode 15-10
tty write string 15-28
write character and attribute at
cursor position 15-20
write character at position 15-21
write character using terminal
emulation 15-25
write pixel 15-23
ROM diagnostics 14-1. 14-8
extended self-test 14-10
powerup test 14-1, 14-8
Rotating priority

DMA controller 4·5
RTC alarm interrupt 15·148

s
Scan codes 15·102
LK250 keyboard 8·15, 8·17
translated but not used 8·21
Scan equal command
diskette drive controller
register sets 11·24
Scan high or equal command
diskette drive controller
register sets 11·25
Scan low or equal command
diskette drive controller
register sets 11·25
Scroll active page down function 15·
17
Scroll active page up function 15·17
SDH register 12·9
Sector
count register 12·7
interleave 12·18
number register 12·7
Seek command 12·12
diskette drive controller
register sets 11·27
Seek to specific cylinder 15·52
Select
compose processing 17-6
numlock processing 17-6
Self-test command
keyboard-interface controller 8-12
Self-test failure
LK250· keyboard responses 8·31
Self·test success
LK250 keyboard responses 8·30
Send

break signal for LAT 18·72
broadcast ·for session 18·116
data for LAT 18·69
datagram for session 18·114
double for session 18·110
for session 18-109
Send break function 15·84
Send to keyboard function 15·119
SendLatBreak 17·70
Sense
drive status 11·27
interrupt status 11-26
Serial
data 9-1
printer port interrupt 15~150
bit stream, converted by LANCE
13-3
interface adapter 13-2, 13·3
Server message block 18-127
Service
directory 18-56
table reset for LAT 18-71
system request key function 15·91
Session
start for LAT 18·57
status word 18-63
for LAT 18-57
asynchronous notification routine
18-90
asynchronous requests 18-89
functions 18-91
add a node 18·120
add name 18·101
call 18-105
cancel 18-97
check for presence 18-96
delete all node entries 18·126
delete entry given node name
18·122
delete entry given node number
18-121
delete name 18·102

Index 27

DIGITAL function check 18-119
DIGITAL-specific 18-118
hangup 18-108
listen 18-107
name status 18-103
read node entry given index
18-125
read node entry given node
name 18-124
read node entry given node
number 18-123
receive 18-111
receive any 18-112
receive broadcast 18-117
receive datagram 18-115
reset 18-98
send 18-109
send broadcast 18-116
send datagram 18-114
send double 18-110
status 18-99
MS-Network compatible services
18-92
network addressing 18-90
overview 18-83
return codes 18-93
status buffer 18-100
synchronous requests 18-89
Session control block (SCB) 18-85
fields 18-86
for LAT 18-59
Set
a wait interval function 15-90
alarm function 15-139
autorepeat delay and rate 8-27
baud rate function 15-87
color palette function 15-22
country code function 16-3
cursor position function 15-13
cursor type function
Mode-dependent values 15-12
DECparm string address 18-40
drive and media type for format
function 15-69

28 Index

graphics rendition function 16-8
keyboard led 8-23
keyclick volume 8-24
mode function 16-10
modem control function 15-85
page function 15-16
parameters command 12-22
real-time clock function 15-138
RTC date function 15-139
system clock function 15-136
video mode function 15-10
SetCommBreak 17-65
SetCommEventMask 17-65
SetCommState 17-65
Shift key
affect on numeric keypad 17-3
SIA - See Serial Interface Adapter
13-2
Signals
communications connector 9-19
modem connector 9-21
printer connector 9-20
Signetics
SCN2261 enhanced programmable
communications interface 10-2,
10-8
Single transfer mode
DMA controller 4-3
Slots for LAT 18-57
5MB

get current date and time 18-128
overview 18-127
Soft reset 14-12
Software interrupts
asynchronous communictaions
15-70
basic 15-132
bootstrap 15-133
cassette input/output 15-88
disk input/output (i/o) 15-38

keyboard break 15-141
keyboard input 15-101
print screen 15-4
printer output 15-123
read configuration 15-35
return memory size 15-37
revector of interrupt 13h 15-145
RTC alarm 15-148
time-of-day 15-135
timer tick 15-141
video input/output 15-8
Software triggered strobe
three-channel counter and speaker
6-6
SORT 16-30
Sort tables 16-32
creating 16-30
SORT.EXE
how affected by FONT.COM 16-16
Sorting
format 16-30
Special purpose register 7-23, 9~18
Specify command
diskette drive controller
register sets 11-26
Speed
indicator control signal 9-17
select control signal 9-17
Square wave model
three-channel counter and speaker
mode 6-5
Standard applications support 17-74
temporarily suspending 17-79
Standard communication of the
VAXmate workstation 13-2
Startup
diagnostics 14-1, 14-8
diagnostics test modes 14-1
Status
buffer for session 18-100

for session 18-99
Status register 4-14, 7-3, 10-9, 12-23
A 7-37
B 7-38
keyboard-interface controller 8-6
Status response
three-channel counter and speaker
6-14
STDUS.KEY 16-25
changing to 16-25
Subroutines
assembly language A-I
Synchronous requests 18-89
SYSREQ 17-5
System
bus 13-2, 13-40
configuration list
during extended self-test 14-10
newly installed options 14-10
powerup 8-4
RAM powerup test checks 14-8
register 6-9
T

Temporary register 4-14
Terminal emulation
font size 17-73
Termination function 15-90
Test
drive ready function 15-54
for character available 17-76
reports for mouse self-test 10-3
Text modes 7-6
cursor rate 7-8
cursor size 7-8
ThinWire
Ethernet 13-3
interconnect 13-3

Index 29

network interface 13-4
Three-channel counter and speaker
control word register 6-11
counter and speaker example 6-20
counter-latch command 6-12
mode 06-4
mode 1 6-4
mode 2 6-5
mode 3 6-5
mode 4 6-6
mode 5 6-7
mode definitions 6-3
modes of operation 6-3
programming example 6-16
read-back command 6-13
status response 6-14
system register 6-9
Time-of-Day interrupt 15-135
Timer tick interrupt 15-141
Toggling keyboard mode 17-4
Translate mode
keyboard 8-2
TranslateMessage 17-4
Translating
attribute data 7-18
graphic color data 7-18
the keyboard 15-121
Transmit
character function 15-73, 15-124
for datalink 18-10, 18-23
holding register and receive buffer
10-8
descriptor ring pointer 13-26
TransmitCommChar 17-64
Transport error codes 18-95
TTY write string function 15-28

u
UART (8250AI registers 9-2

30 Index

programming example 9-22
Universal asynchronous receiver/
transmitters (8250A UARTI 9-1
User call-back routines for datalink
18-8

v
VAX mate
address decode logic 13-5
diagnostics 13-4
expansion box 13-40
110 board 13-1
110 bus 13-5
110 functions 13-2
memory option 13-40
network software 18-1
video display memory 13-40
workstation
base configuration 1-1
optional components 1-2
Verify
one or more disk sectors function
15-46
one or more track sectors 15-65
Video
input/output interrupt 15-8, 15-9
modes for the ROM BIOS 15-10
parameters interrupt 15-142
Video controller
color select register 7-39
control register A 7-41
control register B 7-43
enhancements to industry-standard
features 7-2
graphic features 7-2
industry-standard features 7-1
programming example 7-45
status register A 7-37
status register B 7-38
text modes 7-6
unavailable industry-standard fea-

tures 7-2
video modes 7-5
write data register 7-39
Video memory 7-3
Video modes 7-5
handling inside a window 17-79
no ROM BIOS
DIGITAL-extended 7-12, 7-14
ROM BIOS
industry-standard 7-11, 7-13
ROM BIOS
DIGITAL-extended 7-15, 7-1G,
7-17
Video processor
input/output registers 7-22
look-up table 7-18
Virtual protected mode 14-8
VT220
additional emulator escape sequences C-G
announcing C-8
character set differences C-5
communications differences C-3
DA C-8
DECAUPSS C-G
DECRQUPSS C-G
differences between emulator and
terminal C-2
keyboard differences C-4
printing C-9
SCS CoG, C-7
video differences C-2
VT240
additional emulator escape sequences C-13
announcing C-16
character set differences C-13
communications differences C-12
DA C-15, C-16
DECAUPSS C-13
DECRQUPSS C-14
difference between emulator and
terminal C-10

keyboard differences C-12
Printer to Host mode C-12
SCS C-14, C-15
video differences C-10

w
Windows
keyboard extensions 17-5
layer 17-2
reserved keys 17-5
Write
all mask bits 4-11
character and attribute at cursor
position 15-20
character at cursor position 15-21
character using terminal emulation
15-25
long 15-51
one or more track sectors 15-64
one or more disk sectors 15-45
pixel 15-23
Write command
keyboard-interface controller 8-10
Write data command
diskette drive controller register
sets 11-21
Write data register 7-39
Write deleted data command
diskette drive controller register
sets 11-22
Write port 2 command
keyboard-interface controller 8-13
Write precompensation register 12-4
sector command 12-15
single mask bit 4-11
status register command keyboardinterface controller 8-13
WriteComm 17-63
WriteLat 17-69

Index 31

Technical Reference Manual
Volume 1

AA-HD92A-TK

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Technical Reference Manual
Volume 1
AA-HD92A-TK

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FIRST CLASS PERMIT NO.33 MAYNARD MASS.

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SOFTWARE PUBLICATIONS
200 FOREST STREET

MR01-2l12

MARLBOROUGH. MA

01752

111"",11,11""11""1,11,1,,1,1,,1,1,,11,,,,,1,11
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DoNotTear-FoldHere

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