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MISC-6841C429

June 1983

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Document:	VAXstation 100 Engineering Spec
Order Number:	MISC-6841C429
Revision:
Pages:	64
Original Filename:

OCR Text

VAXSTATION 100 ENGINEERING SPEC

REV 0.1

15 MARCH 1983
15 JUNE 1983

1. OVERVIEW
The VS100 workstation is a 19- monochrome workstation desi~ned for the
professional user. The VS100 consists o~ a corporate standard multibox
containin~ an H7865 power suppl~,display processor module,a fiber optics
transmitter/receiver module and a bitblit accelerator module. The VS100 uses
a 19 in monitor (VR100) in a landscape format. The monitor has a screen
resoultion of 1088 pixel horizontall~ by 864 pixels verticall~. The VS100
interfaces to a VAX 11/7XX CPU throu~h a 10MHz fiber optic cable and a VAX
installed Unibus window module. The VS100 is supplied with a LK201Cx ke~board
and a VS10X-EA mouse as input devices. An optional di~itizin~ tablet VS10X-BA
is available.
2. PRODUCT DESCRIPTION AND FUNCTION

3. PRODUCT REQUIREMENTS
4. STANDARDS,REGULATIONS AND CERTIFICATION
The VS100 complies with the standards and
subsections.
4.1

re~ulations

listed in the

followin~

PRODUCT SAFETY
DEC.STD. 119 - di~ital product safet~ (covers Ul 478, Ul 114, eSA 22.2
NO. 154, VDE 0804, and IEC 435)
IEC 435

4.2

Safet~

reauirements for data

processin~

eauiptment

AC POWER
DEC. STD. 002 - AC power

wirin~,

~roundin~,

receptacles and nameplates

DEC.STD. 122 - AC power line standard ( operatin~ freauency 47-63 Hz,
volta~es 87-128VAC or 174-256VAC ).

operatin~

4.3

ELECTROMAGNETIC COMPATABIlITY
DEC. STD. 103 - electromaSnetic compability (EMC) hardware desiSn
reauirements.
FCC rules and
J (level A )

re~ulations,

part lS - Radio

freauenc~

devices, subpart

DIRECTIVE EEC - 76/889-EMI/RFI reauirements for the British Isles
VDE 0871 level N-12 - Limits of radio interference from radio freQuency
apparatus and installations.

4.4

ACOUSTIC NOISE
DIN 45635 PTl and PT16 - Measurement of airborne noise emmited by
machines
VDE2058 Part 2
DEC.std. 102, section 4 will supercede the above
available

4.5

~uidelines

when

ERGONOMICS
ZN1/535 -

Er~onomics

reauirements for display workstations in the office

enviroment.
4.6

ENVIRONMENT
DEC.std. 102 - Environment standard fo? computers and peripherals
( class S, with operatin~ temperature ranSe of 10 to 40 desrees C and
10 to 90 percent relative humidity).

4.7

LANGUAGE
DEC.std. 107 - Disital standard for terminals keyboards
DEC. std. 168 - Multinational character set

4.8

MISCELLANEOUS
DEC. std. 060 - DesiSn and certification of hardware products to national and international re~ulations and standards.
DEC. std. 092 - Color and finish standard
DEC.std. 105 - Display workstation ersonomics
VDE 0730 - office machine eauiptment
VDE 0860 - video display eauiptment

4.9

CERTIFICATION AND APPROVAL

The VSI00 is desi~ned such that it will obtain the followins listinss,
certifications, and approvals:
(safety) listinS asainst UL 478 and CSA 22.2, No 15(
(safety) certification of compliance to IEC 435
(EMI/RFI) international certification of compliance to FCC level A and
VDE N-12 level

5. HARDWARE

5.1

DISPLAY PROCESSOR BOARD

5.1.1

DESCRIPTION
The

processor module (DPM) in the VS100 contains the MC68000
rom, screen ram,and 1/0 ports. Connected to the displa~
processor module as dau~hter boards are the fiber optic transmitter/reciever
(FOT/R) module and the Bit Blit Accelerator (BBA) module.
The timin~'for the DPM is derived from a 79.96Mhz ECl oscillator and
divided down to 40Mhz, 20Mhz, 10Mhz and other lower freQuencies for use in the
s~stem. The 80Mhz clock allows for a screen displa~ of 1088 pixels horizontall~
by 864 pixels vertically.
Communication with the host cpu (VAX11/7xx) is thru a fiber optic cable
af UP to 300 meters in len~th, which connects to the Unibus Window Module (UBW)
located in the VAX unibus backplane.
The fiber.optic interface operates at a
10Mhz rate. All transmissions across the fiber optic cable are initiated by the
DPM's 68000 cpu or by the BBA module. Transmissions to the VAX cpu are 54 bits
in len~th (16 data bits, 16 crc bits, 18 address bits, 1 control bit, 3 spare
bits). Recieved data from the VAX cpu is 24 bits in lensth.(16 data bits, 1
control bit and 7 spare bits). Data is transfered across the fiber link in
a BI-PHASE l encodin~ scheme. All data transmissions are sent with a
16 bit CRC checksum.
cpu,pro~ram

dis?la~

ram,pro~ram

The DPM also contains:
a proSrammable CRTC controller for
siSnals for the VR100 monitor

~eneratin~

the necessary

timin~

two pro~rammable USART's for communication with the optional
diSitizins tablet and the LK201Cx keyboard.
A discrete interface for the VS10X-EA hand held mouse
A set of 5 lED's for fault indication. 4 led's are red, and 1 led
is Sreen. The led's are located on the rear of the DPM, and are
viewable from the rear of the multibox.
A power-up self test diasnostic used for testins of all major portions
of the DPM module, the BBA module, the FOT/R module, and the LK201Cx
keyboard. An extended set of tests ar~ provided for user tests of the
VS10X-EA hand held mouse, the VS10X-BA disitizins tablet, and aliSnment
of the VRI00 monitor.
llde loop self test that will run continuoslY after power-up self test
is run, but before the user loSs onto the VAX cpu. Idle self-test
provide a continuous check of the functionalit~ of the VS100.
The Micro-diasnostics also has a MAINTANCE MODE which will enable the
user to run specific tests and to test the 1/0 devices.

5.1.2. BLOCK DIAGRAM,DISPLAY PROCESSOR BOARD

------.-----

--------128Kb

16Kb I

I
I

IPROGRAMI
RAM I

68000

--------IPROGRAMI
ROM I

---- ... -----

CPU
----------I

--------FIBER I
IOPTICS I
ITX/RX 1-----> FIBER OPTIC
IMODULE I
CABLE

---------

I
I

----------------------------------------//-----I
I
--------I I/O
I INTER
I FACE

I BUS
I
I 4M BIT t
I XVCR'SI-------I SCREEN 1----) video out
--------I
I
RAM I
I
----------

---------

------------------------I
I
I
/
/
/
/
/
/

ITABLETI

I MOUSE I

I
t
-----//---I
I
I
I
I

--------------1 BIT BLIT
I

I KYBD I

I ACCELERATOR I
I
MODULE
I

5.1.3. MEMORY MAP
The VS100 has a total of 656kb on board memory, allocated as follows:
PROGRAM RAM

128Kb

PROGRAM ROM

16Kb

SCREEN RAM

512Kb (4.2M bits)

ADDRESS SPACE

000000-07FFFF = PROGRAM RAM
080000-0FFFFF = UNIBUS
100000-17FFFF = FRAME BUFFER RAM
180000-1FFFFF = PROGRAM ROM

The VSI00 can address 256Kb of unibus address space

5.1.4. I/O REGISTERS
The

follo~in~

HC68000

devices are mapped into the I/O space (addr 23

= 1) of the

cPu:
Tablet USART
Keyboard USART
Mouse position re~ister
Crt controller resister
System status resister
test led resister
BBA ISOI f/f
CRT controller resister

The CRT controller provides the necessary timins sisnals to the VR100
monitor, and the address for the start of the visible screen memory that will
be read out seauentially durins refresh of the screen. The CRT controller has
two memory addresses assiSned in the I/O space. The first is a pointer reSister
that is loaded with the value of the reSister that data will be deposited in.
Their are 14 resisters available for use in the CRT controller.
The second resister is the data resister. Any data deposited in the data
resister will be transfered to the resister pointed to by the address resister.
eTRC ADDRESS REGISTER

= 8000AO (HEX)

write only

CRTC DATA REGISTER
address
BOOOA4 (HEX)

read/write

address

BIT
I

6
I

4
I

3
I

1
I

REFER TO DEC. SPEC. A-PS-16963-00 FOR MORE DETAILED INFORMATION

The reauired parameters for proper operation of the VR100 monitor at a screen
resolution of 1088 Horz x 960Vert pixels are:

= 4S
= 37
= 74
= 72
R8 = 00
RiO = 00
R12 = 00
R14 = 00
RO
R2
R4
R6

= 34
= 06
RS = 05
R7 = 72
R9 = 11
Rl1 = 00
R13 = 00
R1S = 00
R1

DISPLAY PROCESSOR STATUS REGISTER
The DISPLAY PROCESSOR STATUS re~ister is used by the MC68000 CPU to obtain the
status df events the have an effect on the operation of the VS100 system. This
resister is a 'read only' resister.

= 8000CO (HEX)

address
bit

read only
3

I D7 I D6 I D5 I D4 I D3 I D2 I D1 I XX I
bit 7

= mouse pushbuttonfriSht.

losic 1
losic 0
bit 6 = ITIOIJSe pushbuttonfmiddle. losic 1
loSic 0
bit 5 = mOt.Jse pl.Jshbutton f left
loSic 1
loSic 0
bit 4 = 1 i rlk. available
loSic 1
losic 0
bit :3 = 1 irlk error
lOSic 1
loSic 0
bit 2 = norl-e~{ i stant lI,emorY
losic 1

losic
bit "1

= BBA ?resent

bit 0

= mantJf actlJ 1" i nS mode

loSic
losic
losic
losic
logic

(3v)
(Ov)
(3v)
(Ov)
(3v)

= OFF
= ON

= OFF
= ON
(3v) = link is present
(Oy) = link not available
(3v) = link error detected

(Oy)

= rIo 1 irlk error detected
(3v) = the UBW attempted to
access norl-eHistant VAX merr,orY.
Illesable address from the BBA
or the DPM. Used as a status
bit to indicate the reason
for failure to Sain access to
the UNI-BUS.
0 (Ov) = address placed on the
the uni-blJs was a valid address.
0 (Ov) =
1 (3v) = BBA not preser,t
0 (Ov) = BBA present
1 (3v) = not in mar.uf actu r i ns
mode
0 (Ov) = the module is in a
man'Jf actlJ ring ertV i roment.
(Oy)

MOUSE POSITION REGISTER
The MOUSE POSITION reSister is used as a count/direction resister by the 68000
cpu. This reSister will contain the value of increments that the mouse was moved
since the last ·MOUSE POSITION REGread by the 68000 cpu.
address

bit

= 800060 (HEX)

read only
8

I Y7 ---------------------- YO I X7----------------------- XO I
-----------------------------------------------~------ ---------

= Y7

bit 15

The M.S.B. of the Y position reSister. Used to indicate
the direction of mouse movement in the vertical axis (Y axis).
10Sic 1 (3v) =
losie 0 (Ov)
bit 14-8
the value of the mouse movement in the ·Y· direction

bit 7

= X7 The M.S.B. of the X position resister. Used to indicate the
direction of mouse movement in the horizontal axis (X axis).
loSic 1 (3v) =

bit 6-0

loSie 0 (Ov) =
the value of the mouse movement in the ·X· direction.

TEST LEDS REGISTER
The TEST LED's re~ister is used to turn on/off the 4 red led's and 1 ~reen led
located on the rear of the DPM board. These LED's are used by the microdiagnostics to indicate failure of any of the major sections of hardware in
the VSi00 system.
address
BIT

= 800080 (HEX)
6

WRITE ONLY
3

I XX I XX I OK I G5 I R3 I R2 I Rl I RO I
bit 7 = RESERVEII
bit 6 = RESERVED
bit 5 = TEST OK

bit 4

= greer. led

Used in the manufacturing enviroment.Indicates
that the VS100 has SIJccess fu 11 y passed blJrn-in
self test. NOTE self test takes app ro}{ 20 sec.
logic 1 (3'1) = test passed. cleared on power-uP,
reset b~ the host,or e!·~terrlal
irti t.
logic 0 (Ov) = test failed.

logic 1 (3'1)
led off
logic 0 (Ov) = led on indicates the VS100 has
passed power-uP self test

bit 3 = red led 3

logic 1 (3v) = led off
logic 0 (0'1) = led or.

bit 2

= red led 2

losic 1 (3'1) = led off
logic 0 (0'1) = led or.

bit 1

= red led 1

losic 1 (3'1) = led off
losic 0 (0'1) = led on

bit 0

= red led 0

losic 1 (3'1) = led off
losic 0 (0'1) = led on'

REFER TO SECTION 7.5 FOR A COMPLETE DESCRIPTION OF THE TEST LEDS ERROR COIlES

TABLET USART
The TABLET USART re~ister is 4 1/0 mapped locations used to set-up the 2661
USART for proper communications with the optional VS10X-BA di~itizin~ tablet.
The clock to the USART is 5.000Mhz. The normal communications baud rate to the
tablet is 9600 baud
address

= 800020 (HEX)

REAII/WRITE
REAII/WRITE
REAII/WRITE
REAII/WRITE

800022 (HEX)
800024 (HEX)
800026 (HEX)
BIT

I II7 I D6 I II5 I II4 I D3 I D2 I Dl I DO I
REFER TO IIEC.SPEC. A-PS-18623-00 FOR MORE DETAILED INFORMATION
NOTE: The clock input to the USART is 5.000Mhz
KEYBOARII USART
The KEYBOARD USART re~ister is 4 I/O mapped locations used to set-up the 2661
USART for communications with the LK201Cx keyboard. The clock to the USART is
5.000Mhz. The baud rate for the LK201Cx keyboard is 4800 baud •.
address

= 800000

READ/WRITE
READ/WRITE
READ/WRITE
READ/WRITE

800002
800004
800006
BIT
I

7
I

4
I

2
I

REFER TO DEC.SPEC. A-PS-18623-00 FOR HORE DETAILED INFORMATION
NOTE: The clock input to the USART is 5.000 Mhz

5.1.5 I/O CONNECTOR DESCRIPTIONS
The followin~ 1/0 connectors are located on the rear panel of the VS100 DISPLAY

PROCESSOR MODULE.
MONITOR OUTPUT CONNECTORS
The VR100 monitor uses 3 seperate outputs. Thes~ outputs are provided
isolated BNe t~pe 50 ohm connectors. The levels of the outputs are:
video

throu~h

0.Ov-800 my.
black = O.Ov
white = 0.700v

horz.s~nc
vert.s~nc

0.4v-2.4v
0.4v-2.4v

TABLET POWER AND SIGNAL CONNECTORS
The tablet uses 2 connectors. one for power and one for si~nals. The
connectors are industr~ standard D-SUB miniature t~pe connectors, located on
the backpanel of the DPM module.
9 pin power connector (female, D-sub miniature)
pin 1
pin 2
pin 3
pin 4
pin 5
pin 6
pin 7
pin 8
poin 9

+5v
+5v

N.C.
+12v

N.C.
-12v

SroJ.Jrcd
sround
chassis S rOI.Jnd

25 pin sisnal connector (female, D-sl.Jb IJtiniature)

poin 1
pin 2
pirJ 3
pirl 7
pin 12
pin 13
all other poins

safet~ Sround
transmit
receive
s i Srlo 1 Srour.d
reserved (test INIT)
reserved (test OK )
= n.c.

MOUSE POWER/SIGNAL CONNECTOR
15 pin

power/si~nal

pin
pin
pin
Frin
pi r.
pin
pin
pin
?'in
pin
?'in
pin
pin
pirl
pin

5.1.5.4

1
2
3

4
5
6

7
8
9

10
11
12

13
14
15

connector (female, D-sub miniature)

YA
YB
XB
XA
N.C.
+5V D.C.
N.C.
N.C.
GROUND
GROUND
N.C.
RIGHT BUTTON
MIIIDLE BUTTON
LEFT BUTTON
N.C.

KEYBOARD POWER/SIGNAL CONNECTOR
4 pin female telco connector
pin 1
pin 2
pin 3
pin 4

RECEIVE
GROUND
+12v dc

TRANSMIT

RS-423 COMPATIBLE

INTERRUPTS
The MC68000 uP on the DPM has 7 levels of interrupt. Level
7, the hiShest level is non-maskable. Interrupt vector addresses are fixed.
The 7 levels of interrupt are:
level 7

level 6

level 5

level 4

=
level 2 =
level 3

level 1

BBA non-existent memory. Set when the BBA tries to address
non-existent memor~ in the VAX cpu. Cleared by clearins the
BBA 'So' bit.< the BBA will then clear its memor~ reauest,
which will clear the LEVEL 7 interrupt.
VERTICAL SYNC. used as a watchdos timer. Set by VERT. SYNC.
from the CRT controller. Cleared b~ RESET SIX. (read from
address 8000EO (HEX)
LINK TRANSITION. indicates that the Fiber Optic link has had
either LINK ERROR asserted, or that LINK AVAILABLE has
chanSed states. Cleared by either a power-up reset
(hardware) or a read from address 800040 (HEX)
BBA DONE. Used to indicate that the BBA has completed an
operation. Cleared by the BBA when the 68000 uP clears the
BBA 'So' bit
Tablet USART interrupt. Receiver bu~fer full,or transmitter
buffer empty.
Ke~board USART interrupt. Receiver buffer full,or
transmitter buffer empty.
not used

MANUFACTURING MODE
A Jumper has been provided on the DPM module that will allow for
a dynamic functional burn-in of the zebra/bba/fotr in a manufacturins
environment. This Jumper reauires the use of loopback connectors on the
tablet ilo port (DEC. PTt 12-15536-00),and a loopback connector on the
ke~board port (DEC.PTt 12-XXXXX-XX). when in this mode,the micro-diaSnostics
will loop continuouslY on the power-up self test. The unit will halt at the
first occurance of a detected error, and display the test number in the
led indicators.

5.2

UNIBUS WINDOW MODULE

5.2.1

FUNCTIONAL DESCRIPTION

The M7452 module is a standard hei~ht hex size module used as an
interface between the VS100 and the VAX11/7XX cpu. The module connects to
the VAX unibus backplane and recieves its power from the VAX. The M7852 is
connected to the VS100 b~ a 2 channel fiber optic cable. The M7452 has 8-16
bit re~isters used for the transfer of data between the VS100 and the VAX cpu.
The VAX is allowed to address the control/status re~isters onl~.
The VS100 can address either the control/status reSisters or the VAX memory.
The M7452 is an NPR device and is also capable of interrupts to the VAX. The
address ran~e of the module is selected b~ switches. The interrupt vector
addresses are pro~rammable. The Interrupt level is selected b~ a standard
BR chip, set at level BR5.
The unibus module is capable of suPPortin~ one (1) VS100 communications
link The maximum len~th of Fiber optic cable that can used with the VS100 is
300 meters.
MAINTANCE MODE LOOPBACK
The M7452 module is provided with the capability to perform loopback
of data while under program control. This is accomplished on two levels. The
first is an electrical loopback of data that has been encoded into bi-phase L
data at an ECl volta~e level.While in this mode,the XMIT ON bit should be
dis-asserted. this will prevent data from bein~ transmitted to the VS100displa~
processor board. Also,while in this mode, the CRC generator ma~ be disabled.
The second level of loopback is the OPTICAL loopback. this mode reauires
that an optical loopback connector (DEC PT. t 12-~y~~~-zz) be installed on the
fiber optic connectors. While in this mode, the XMIT ON bit must be asserted,
and the CRC generator may be either asserted or de-asserted.
The loopback process is started by first settins the appropriate bits
in CSR O,then loadin~ the data to be looped back into CSR5. LoadinS of data
into CSR5 will initiate the loopback seauence. Data will be loaded into CSR6.
If interrupts are enabled,the unibus module will interrupt the host,with the
vector address that was previously loaded onto CSR7.

5.2.3

SWITCH SELECTABLE BUS ADDRESSES

The base address of the M7852 is selectable throuSh a set of switches
located on the module. The ran~e of addresses is 760000-777760 (BASE 8) The
numberin~ and location of the switches is as ~ollows:
address bit

12
ON

I ON ION, I ON I ON I

OFF
switch ?osition

I ON I ON I

JOFF I
1

UNIBUS
ADDRESS

I ON I

760440(8)

IOFF I

FFE120(16)
9

SOFT VECTOR ADDRESSES
The VECTOR addresses that the VS100 uses to interrupt the host cpu
are loaded b~ the DEVICE DRIVER prior to ucode load. The vector address must
be loaded into CSR 7. The allowable ranse of addresses is OOOOOO-001776(BASE 8)

BLOCK DIAGRAM

IUNIBUS I
I FIBER t
---IXMIT S.R.I---)
,I<--------~------------>I OPTIC 1(-)1
1---------1
IXCVRIS I
I
I XVCR1SI
---IREC S.R. 1<-----------

---------

V
I
I

CONTROL/STATUS
REGISTERS

I
I

-----------

FIBER
OPTIC
CABLE

CONTROL/STATUS RESISTER BIT ASSINGMENTS

15
CSR 0

4 --- 1

I LT I LA I LE I XO I MM I CD I MD IRES.I OWN IRES.I IE I FUMCT I GO ,
BIT 15

Link Transtition
set when:
1. a link error occurs
2. there is a chanse in the state of the link
available bit
cleared b~: The host CPU

BIT 14

Link Available

indicates the status

the fiber cable sauelch

circuitr~

a suf~icient level of liSht is detected
o2="tic receiver
cleared b~: The host CPU

set when:

BIT 13

Link Error
set when:
a CRC error is detected
durins data reception
cleared

BIT 12

b~:

the fiber

the fiber o2="tic receiver

cleared when the host cpu clears bit 15

Xmitter On

used to control the state of the Fiber Optic PIN
transmitter diode
set to 1
lisht on
cleared to 0 = lisht off

BIT 11

controls the state of the U.B.W. module. Allows
data to be looped back internall~ to the module
for testins purposes.
set to a l = maintance Dode enabled
cleared to 0 = normal operation of the module

BIT 10

Crc Disable

Maintance Hode

used b~ diasnostics to disable the Sene ration of
CRC checksums.

set to 1 = disable CRC Seneration
cleared to 0
enable CRe generation

BIT 9

Maintance Done

used to siSnal the end of a maintance mode
c~cle

set to 1 = Iflaintance mode
cleared to 0 =
BIT

done

J;~ESERVED

BIT 7

OWN

BIT 6

I nte r rl.Jpt Erlable

BIT 5

RESERVEII

BIT 4-1 FUNCTION CODE
displa~

BIT 0

c~cle

GO bit

specifies an operation to be' performed
processor.

the

The VS100 micro-code will support the followin~ 3 functions in ROM based
firmware,and the 2 commands associated with the SEND PACKET function.
BIT POSITION
4
3
2
1 t

FUNCTION

I 0 I 0

INITIALIZE

I 1 I

SEND PACKET

CODE

I 0

I 0 I 0 1 0 I 0

I 0

lOt 0

1 I 0 I

START DISPLAY

The ·SEND PACKET· function has two seperate commands that
are suPPorted in the VS100. The~ are:
1.

REPORT STATUS -- this command returns information about the
displa~/s status and addressin~ enviroment to
the host.

MOVE OBJECT
the

this command allows down-line loadinS of
micro-code into displa~ local

displa~

memor~.

5.3

.BIT BlIT ACCELERATOR

5.3.1

FUNCTIONAL DESCRIPTION

The Blit Bit Accelerator (BBA) is used to move data to and from the Display
Processor Screen memor~ at hi~h speed independant of the Display Processor
CPU. The BBA recieves command packets from the Displa~ processor, and can
~odifY,manipulate and move data for the purpose of Guickly chanSins visuall~
displa~ed information.
From a functional viewpoint, the BBA is divided into two sections. One seeton
-interpets commands,computes addresses, and provides control and execution of
alsorithms. The second section is used to process bit data.
The followinS instructions are suPPorted

A.
B.
C.
D.

the.BBA firmware

COpy AREA
PRINT TEXT
VECTOR
HAlFTON~

For a complete description of these instructions, refer to the WORKSTATION

GRAPHIC ARCHITECTURE Vl.0 ,HANK lEVY

5.3.2
to/from

DPM

MARCH 1, 1983

BLOCK DIAGRAM

BBA address bus

23 bits

><------------------------------I
V

ISCRATCHI
PAD ,
, MEMORY'

I ADDRESS

PATH

1-----------------------I .
to/from

DPM

V BBA data bus

16 bits

><--------------------------I

DATA PATH

to all blocks

I MICRO CODE
I 56 bits
I
}~ lk.

5.4

FIBER OPTIC TRANSMITTER/RECEIVER MODULE

(DEC.t 54-16010)

FUNCTIONAL DESCRIPTION
The fiber o~tic transmitter/receiver module is used to drive the fiber
cable. The data in~uts to the module are ECl level sisnals. the data
outputs from the module are Eel level si~nals. Also out~ut from the module is
the link available si~nal, used to indicate that the lisht received is above a
minimum value as determined b~ the sauelch circuitr~.
o~tic

NOTE: the link available sisnal assereted indicates that lisht is beins
received. It does not mean that the fiber optic link is functional.
BLOCK DIAGRAM

FIBER CABLE
-------------------(receive)
----)IPIN
1------)1 h~brid
I diode I
I receiver

1-----------) ECl DATA OUT

1 sauelch
1-----1 link
1-----) link
-----------I available 1
available

ECl DATA IN-----)I driver 1-----)1 L.E.D.

1------)

FIBER CABLE
(trasmit)

the FOT/R has four sections. These are: 1. the h~brid receiver, 2. the
sauelch circuit, 3. the link available circuit and 4. the transmit L.E.D.
driver.
SIGNAL DESCRIPTION

40 pin corlnector, Female
----~-~------~-----------~--~---

pins 1,2,3,4
~irls 5,6,11,12,
29,30,32,33,
34,36,37,38,
40
pins 7,8,9,10
pins 13,14,15,16
pins 17,18,22,
N.C.
23,24,25,26,
27,28
pin 19
pin 20
pin 21
pin 31
pin 35
pin 39

+5v
SNIt.

+12v
-12v

link avail H
link avail L
~<mi t on H
ecl t}~ data l
ecl t>~ data H
ecl bip data l

5.5

FIBER OPTIC CABLE
DEC.PTt 17-00333-01 unterminated
DEC.PTt 17-00343-xx termina~ed (BC25B-xx)

The fiber optic cable used in the VS100 is a two channel cable, that operates
in a ~raded-index mode of operation. the optical fiber is 100nm in diameter,
clad with ~lass that is 140nm in diameter.
5.5.1
The

WEIGHT

wei~ht

5.5.2

of the fiber optic cable is 100 lbs/km nominal,

nominial

COLOR

The color of the outer Jacket of the cable is TAN (per
5.5.3

45k~/km

DEC. 216 , BEIGE)

CABLE LENGHTS

The terminated cable is available in standard

len~ths

of:

DIGITAL PART NO.

DIGITAL OPTION NO.

LENGTH

17-00343-02
17-00343-03
17-00343-04
17-00343-05
17-00343-01
17-00343-06

BN25B15
BN25B30
BN25B60
BN25B90
BN25B150
BN25B300

15M (49 ft.)
30M (98 ft.)
60M (197 ft.)90M (295 ft)
150M (492 ft.)
300M (984 FT.)

(-0~+2~,+30cm.)

The cable is available in the unterminated version onl~ on special order~ The
DEC pt. for unterminated cable is 17-00333-01. All di~ital cable that meets
these purchase specs will have the transmit cable clearl~ identified. The
recieve cable will also be identified. The cable has the following
charactersitcs:
minimum bend radius, fiber cable with outer
)- 3.0 inches,
)- 7.6cm

sheathin~

minimum bend radius fiber cable without outher
)- 1.0 inch,
> 2.54cm

sheathin~

the cable will withstand a crush force of 400LBS./linear inch

5.6

VR100 monitor

The monitor used with the V5100 is a 19in (dia~onal) landscape mode
monochrome cathode ra~ tube(CRT) containin~ all of the necessar~ electronics
for displayin~ hi~h resolution alphanumeric/~raphic video information. It
is AC powered, self contained in a compact plastic enclosure and receives
video and synchronizin~ si~nals thru a 3 conductor cable from the VS100
multibox.
The monitor is eauiped with fault indicatin~ LEDs (normall~ on) and
is intended for mountin~ on a tilt/swivel base. Other key features of the
monitor are:
rear panel mounted controls for brishtness and contrast
self contained power supply
DeLI anti-~lare screen coat ins
noise free operation without a fan
meets class A FCC radiation levels
UL approved
VIEWABLE AREA
FORMAT:
The viewable presentation is a rectan~lular format of
sauare pixels with 1088 pixels acro~s the horizontal
dimension and 864 pixels across th~ vertical dimension.
ACTIVE DISPLAY AREA:
With a solid white screen applied and at a maximum
si~nal level of 40 foot-Iamberts, the active display
size shall be:
Horizontal
354.3mm +- 1.5mm
Vertical
281.4mm +- 1.5mm
screen aspect ratio
1.26:1
5.6.4

PIXEL SIZE:
.325m
Horizcintal
.325mm
Vertical
pixel aspect ratio

13.95in
11.08in

0.0128 in
0.0128 in
1: 1

FAULT INDICATING L.E.D.S
The VR100 monitor is eauiped with 4 fault indicatins LEDs. These LEDs
are normall~ illuminated to indicate the presence of the necessar~
sisnals/voltases for the proper operation of the monitor.
The LEDs indicate the

conditions:

minimum threshold of 300MV reauired
TTL level reBuired
TTL level reauired
80X of reQuired B+ level for no~mal operation
of the monitor is available

VIDEO
HORZ SYNC
VERT SYNC

B+ Volta~e
fi~ure

followin~

of back panel

T.B.S.
POWER REQUIREMENTS
115v @ lamp.
240v @ .Samp
fuse t~pe
3AG (U.S.)
5mm X 20mm (EUROPEAN)

CONTROLS,EXTERNAL
brishtness
contrast
5.6.8

INPUTS

The inputs to the VR100 monitor are SNC
panel of th~ monitor.

t~pe

connectors, located on the rear

5.6.8.1 VERTICAL
V.

V.
V.
V.

width =
sync period
s~nc. Tr
<3ns.
blankins interval
unblank interval
s~rlc

V. f reatJenc~ =

0.1 to 0.5 Msec
16.667 Hsec
Tf = <3ns.
0.775 Hsec
15.912 Hsec
60Hz.

5.6.8.2 HORIZONTAL

s~nc

width =

H. sync. period =
H. sync. Tr

= <3ns.

H. blankinS interval
H. unblank interval
H. freatJenc~ =

2-8 uSEC
18.416 uSEC
Tf = <3ns.
4.804 IJSEC
13.612 uSEe
54.3KHz.

5.6.8.3 VIDEO

=
=
=

Voh
Vol
Tr
Tf =

(white level>
(black level)
-( 3ns.
-( 3ns.

POWER REQUIREMENTS
120v ac @ lamp
240 v ac @ .5 amp
5.6.10

PHYSICAL DIMENSIONS
hei~ht(w/o

width
depth

wei~ht(w/o

5.6.11

tilt/swivel) = 14.75 in. (37.5cm)
in. (45.7cm)
in. (40.6cm)
tilt/swivel)
(45 lb. (20.5 k~)

= 18.0
= 16.0

TILT/SWIVEL BASE
supplied with each unit. customer installed
swivel rarl~e =
tilt ran~e =

360 de~rees <limited
-5 to +15 de~rees

the cables)

5.7
5.7.1

MOUSE

VS10}{-EA

DESCRIPTION

The MOUSE is a hand held pointing device used to select objects on the display
screen. It is attached to the display processor module throu~h a 12ft. cable
with a male 15 pin D-sub miniture connector. Power for the MOUSE is derived
from the displa~ processor module. The MOUSE provides relative position data
to the displa~ processor b~ means of auadu~ature encode signals for each axis
(X and Y). The MOUSE also has 3 buttons used to signal events to the displa~
processor. The mouse buttons are numbered 1 thru 3 from left to ri~ht.
PHYSICAL DIMENSIONS
Height
Len!lith
Width
Weight

= 1.3 in (3.3cltd

= 3.75in (9.5cm)

(7.0cm)
= 2.75in
(280gr.)
<100z.
=
cable length = 12 FT.
cable color = DEC 068 GREY

5.7.3

SIGNAL DESCRIPTION
15 pin D-SUB miniature connector
pin lthru 15
NOTE:

t~pe,male

cable shield is tied to the metal housing of the connector.

ACCURACY
The VS10x-EA is capable of providing 200 pulses/inch. The rate of movement of
the MOUSE is limited to 10 in/sec.
5.7.5

POWER REQUIREMENTS
+5Vdc +/-10% @ <150ma. protected

a circuit board mounted ·pico·fuse.

Note: the ·pico· fuse is not customer serviceable.
OPERATION

5.8

TABLET,

5.8.1

DESCRIPTION

W/5 BUTTON PUCK

DEC. PT. t

30-20037-01

The VS10X-BA di~itizin~ tablet is hi~hly accurate absolute positionin~ device
used to input coordinate data to the displa~ processor board. The digitizing
tablet is connected to the displa~ processor b~ two cables. One is a 9 pin
cable ~sed to suppl~ power to the tablet, and the second cable supplies data to
and from the tablet. The tablet itself is a micro-processor controlled device,
with a hand held puck which has 5 buttons for controlling the operation of the
tablet.
The VS10X-BA is a

di~itizin~

system

TABLET
5 BUTTON CURSOR
12 FT POWER CABLE
12 FT SIGNAL CABLE

consistin~

of the

followin~

components

VS10X-CA
VS10X-DA
17-00341-01
17-00322-06

The di~itizin~ tablet is a computerized input device which sends X-Y
coordinate date to the VSI00 to indicate the position of the cursor on the
surface of the tablet t~ a hi~h level of accurac~

5.8.2

ACCURACY

The accurac~ of the tablet is 1000 Lines/inch at 22
the specified humidit~ and altitude

REPEATABILITY

de~.C

+/- 4 des. C at

+/ - 0.001 inch (with cursor)

COORDINATE ORIGIN: absolute

5.8.3

OPERATION OF THE TABLET

The tablet

ma~

POINT:

be operated in
st~lus

an~

of the followins modes of operation

switch or cursor indicates a

sin~le

X-Y output

CONTINUOUS:
M~ltiple X-V pairs are output as IonS as the stylus
or cursor is in the proximit~ of the tablet. No switch
activation is reauired.
LINE: Multiple X-V pairs are output as Ions as the
switch is held down.

st~lus

or cursor

INCREMENTAL: Movement of the stYlus or cursor of more than 0.01 inch
in line mode initiates output.

5.8.4
5.8.4.1

PHYSICAL DIMENSIONS
DIGITIZING TABLET
heiSht
tilt

VS10X-CA

2.171 in (55mm) in level position
4.203 in (122mm) in tilt position

~nSle

14 des

+/- 2 des.

width

16.75 in (425 mm)

depth

16.75 in (425 mm)

weight
5.8.4.2 USEABLE SURFACE SIZE
The surface is seamless, opaoue
width

acr~lic

plastic

11.0 in (273.4 mm)
11.0 in (273.4 mm)

5.8.5

POWER REQUIREMENTS
5V DC -< 2.0 amp
+12V ItC ( 120ma
-12V DC ( 120ma

5.8.6

SIGNAL DESCRIPTION
I/O cable, 25 pin male, 12ft. (3.7m),DEC 068 sre~
pin

function

1
2

st rOIJnd
transmit data
recieve data
reouest to send
clear to send
data set ready
Sround
carrier detect
data terminal read~
reserved for other functions

3
4

5
6
7
8

20
other pins

POWER CABLE, 9 pin female, 12ft. (3.7m), DEC 068
PIN

FUNCTION

+Sv
+Sv
N.C.

2
3
4

.?
6
7
8
9

shell

+12v DC
N.C.
-12v DC
srour.d
st rOIJnd
n.c.
chassis strolJnd

Sre~

5.8.7

RELIABILITY
The H.T.B.F. shall be

5.8.8

> 10,000 hrs.

DATA FORMAT
figure to be supplied

5.8.9

SWITCH POSITION SETTINGS
figuTe to be supplied

5.9

LK201-CA

KEYBOARD

5.9.1

DESCRIPTION

The ke~board used with the VS100 workstation is the LK201Cx. This
is a product specific variation of the D.E.C. standard LK201 famil~
of ke~boards. For a more detailed description of the LK201 keyboard, refer
to the documents listed in the appendix.
ke~board

5.9.2

MODEL DESIGNATIONS

All LK200 famil~ ke~boards are designated b~ a model number which
describes the ke~switch groups implemented, ke~cap placement,and labeling.
The ke~boards described here are desi~nated LK201Cx
LK201 C x
alphabetic describing keycap labels.
------ alphabetic designating a VS100 specific
MorlEl NO.

KEYBOARD

LEGEND

VS10X-AA

LK201-CA

USA/CANADA

VS10X-AB

LK201-CB

lBELGUIM FLEMISHI

----~-~-----------------------------------------VS10X-AC
LK201-CC
ICANADA (FRENCH) I

VS10X-AD

LK201-CD

DENMARK

VS10X-AE

LK201-CE

IUNITED KINGDOM I

VS10X-AG

LK201-CG

GERMANY

VS10X-AH

LK201-CH

HOLLAND

VS10X-AI

LK201-CI

ITALY

VS10X-AJ

LK201-CJ

'JAPAN KAT AKANA I

VS10X-AK

LK201-CK

ISWISS (FRENCH)

VS10X-AL

LK201-CL

ISWISS (GERMAN)

VS10X-AM

LK201-CM

SWEDEN

VS10X-AN

LK201-CN

NORWAY

VS10X-AP

LK201-CP

FRANCE

VS10X-AS

LK201-CS

SPAIN

------------------------------------------------FINLAND
VS10X-AF
LK201-CF

---------------------------------------------~---

VS10X-AZ

LK201-CZ

I AUSTRALIA

ke~board.

5.9.3

DIMENSION
The hei~ht from the desktop to the finSer contact surface of the home
row of kegs shall be 30mm. +1-1.0 mm.
The overall dimensions for the

ke~board

width
21 inches
depth
6.75 inches
heisht (includins ke~caps) 2.0 inches

are :

53.3cm
17.2cm
5.1cm

The unsculptured ke~s are mounted on a curved base which will produce
a sculptured ke~board profile with unsculptured ke~s.
The weisht of the
5.0 Ibs 2.3ks
5.9.3.1

ke~board

with the

interconnectin~

cable is less than

COLOR
The function ke~s located on the top row of ke~s, the cursor ke~s and
the six ke~s located directl~ above the cursors will be a neutral color
(DEC 217).The color of the remainder of the ke~s and the ke~board are
Sre~ (DEC 068).

5.9.3.2

REFLECTANCE
The

5.9.3.3

ke~caps

reflect less than 457. of the incident liSht.

LEGEND
fisure to be supplied

5.9.3.4

KEYBOARD INTERCONNECT
The ke~board interconnect cable is 16 ft in lensht. In an uncoiled
condition, the cable is 19 ft. The ke~board cable uses a 4 pin male
telephone connector at each end.

5.9.3.5

KEYBOARD OPERATION
The operator uses the ke~board to transmit encoded ke~in~ events to a
buffer in the workstation. A keyins event is transmitted when!
1. an~ key is newl~ pressed
2. an~ of a certain set of ke~s is depressed
3. certain keys are held down and are ~eneratin~
auto repeatkeYins events.
except as allowed above, the release of a key is not an event.
data is transmitted from and recieved by the keyboard at a rate of
4800 baud.
transmitted data is in sin~le byte format for a given
keY, upon receiving a reset command fron the VS100,
the keyboard will perform a power-up self test and then
transmit a 4 byte code to the VS100. The 4 bytes
transmitted at power-up are defined as follows!
first byte

firmware I.D.

second

hardware I.D.

third

b~te

fourth byte

error code or 0 error code can
indicate RAM error,ROM checksum
error or key down condition
indicates specific key down if any

The user must identify the keyboard to the VS100 ie. what natural
langua~e, ~erman,french etc.,either in the set-up mode or through
escape seQuences when switchin~ keycaps or keyboards.

5.9.3.6

N KEY ROLLOVER
The keyboard will transmit the last key down even though other keys are
not released. This will enable the workstation to exibit the N key
rollover feature when:
1. ·phantom key· possibilities do not exists.
2. The bell of the keyboard can be programmed for various volume levels
3. The keyclick indicator can be programmed to an ON or OFF condition.

5.10

POWER SUPPLY - H7865

5.10.1

OPERATION
The H7865 power suppl~ is a sinsle endedfswitch t~pe, re~ulated AC-DC
converter circuit. It utilizes a uni-directional transformer in a half
wave transformer coupled mode. The unit operates at a constant
freQuenc~ and re~ulation is achieved b~ pulse width modulation of the
inverter primar~ current conduction time. Primar~ ener~~ storase is in
the input filter capacitors at approximatel~ 300V DC. Discrete pulses
of known current are provided to the UDT primar~ windins with each
tris~ered period of operation. This current is transformed b~ the UDT
and is available at lower voltase and hi~her current at the secondar~
windinSs of the UDT. B~ increasinS or decreasin~ the pulse width, the
available output voltase is affect~d correspondinSl~. Hence, a
constant output DC yoltase is maintained with var~in~ lines and loads
b~ increasins or decreasins the converter pulse width.

5.10.2 ELECTRICAL SPECIFICATIONS
5.10.2.1 AC INPUT SPECIFICATIONS
5.10.2.2

LINE VOLTAGE
Line voltase input ran~e is selected b~ an operator accessible switch
located near the AC inlet connector. This switch reQuires a small tool,
such as a screwdriver to operate.
120V AC nominal, single phase, 3 wire.
87V AC to 128V AC.
220V AC nominal, sinsle phase, 3 wire.
174V AC to 256V AC.

5.10.3

FREGUENCY

5.10.4

CURRENT

5.10.4.1

6A RMS Maximum (87V AC input for full rated
output)

5.10.4.2

4A RMS Maximum (174V AC input for full rated
output)

5.10.5

POWER FACTOR
The power factor ____ RMS WATTS_______
RMS volts x RMS amps

of the input shall be

than 0.60 at full output power and 120V AC, 60 Hz line.

~reater

5.10.6

INRUSH CURRENT
At the first application of input voltase to the power suppl~, the
stated surSe current ma~ be reached for 1/2 cycle of the input line.
Followins that surSe, there will be repetitive peaks of exponentiallY
deca~ins amplitude for UP to 10 or more c~cles of the line until steadY
state operation is reached.
128V AC: 70Amps (peak)
256V AC: 70Amps (peak)

5.10.7

OVERLOAD PROTECTION

5.10.7.1

An externall~ accessible circuit breaker is provided to protect
the output wirins. The is rated at 6 Amps,250V AC and covers
both input yoltase ranSes.

5.10.72

The start-up transformer is protected aSainst overheat ins
durinS a fault b~ a 1/2 Amp,250V fast blow fuse. This fuse is
mounted on the circuit board and is serviceable only by
aualified personnel.

5.10.8

REAL INPUT POWER
320 watts input maximum at full rated DC output load.

5.10.9

EFFICIENCY
The ratio of DC output power to real input power at full rated
load shall be 0.7 minimum over either input voltaSe ranSe.

5.10.10 LINE VOLTAGE DISTURBANCE
5.10.10.1

UNDER VOLTAGE
UNDERVOLTAGE WITHSTAND
The power supply is capable of withstandinS any undervoltase
condition for an~ duration without ph~sical damaSe or
desradation.

5.10.10.1.2

RIDE THROUGH
The POK siSnal(reset to the VS100 mother board) shall remain
asserted durinS one half c~cle of less than the minimum line
voltase.

HIGH VOLTAGE TRANSIENTS
NOTE:
A spike is defined as a volta~e transient, of either polarity
and of either common or differential mode, with a rise time (10% to 90 X)
of 0.1 microseconds or less and a fall time (to 10%) of 10 microseconds or
more.
The averaSe power of SPikes shall not exceed 0.5 watts.

5.10.10.1.4

LOW ENERGY TRANSIENTS
The suppl~ shall withstand a 300V peak voltaSe spike containin~
not more than 0.2 watt-seconds of enerS~ per spike without
sustainins damaSe or desradation to an~ portion or component
of the suppl~.

HIGH ENERGY TRANSIENTS
The suppl~ shall withstand a 1KV peak voltase SPike containins
not more than 2.5 watt-seconds of eners~ per spike without
sustainins damase or desradation to an~ portion or component of
the suppl~. This is a one-shot, non-repetitive transient.

5.10.11

ELECTROMAGNETIC INTERFERENCE SUSCEPTABILITY
AC POWER LINES

5.10.11.2

CW RF
The power supply shall operate without system desradation with
3 volts RMS superimposed on the AC power interface. (all three
lines, power,neutral and sround).

5.10.11.3

TRANSIENTS
The power supply shall operate without desradation when
transients with an eners~ level of 2.5 watt-seconds are
superimposed on all conductors ( power neutral and sround) of
the power cord For testins purposes, the ave raSe transient
power shall not exceed 0.5 watts.

RF FIELD STRENGTH
The power
followin~

shall operate without de~radation in the
fields,100% amplitude modulated with 1000 Hz sauare

suppl~

wave.
10KHz to 30MHz! 2v/meter
30MHz to 1 GHz: 5v/meter
EGUIPTMENT EMINATIONS
In a s~stem contiSuration, the interference voltaSe on all
connection to commerical AC power shall not exceed 80 db above
1 microvolt @ 10 KHz, decreasin~ with freQuenc~ to 58 db above
1 microvolt @ 150 KHz-450 KHz and 48 db above 1 microvolt from
450 KHz to 30 MHz. The interference field strenSth shall not
exceed the followins levels at 30 meters from the eauiptment:

5.10.12

Freauenc~

level

10 Khz - 30 MHz·
30 MHZ - 16Hz

50uV/m
17uV/m

(34dbuV/m)
(25dbuV/m)

COOLING
Forced air is supplied b~ a sin~le 12V DC fan. Minimum airflow
thru the fan is 27.0 C.F.M., independant of the AC line input
voltaSe.

5.10.13

ACOUSTIC NOISE
At the s~stem level ( complete
devices attached and the power
reauirements are:
-noise power emmission level
-front operator position

s~stem
suppl~

box with all boards,I/O
fan on ), the

< xxxx at zzzzz

a-wei~hted

sound pressure

-no promenient tone or impulse noise
meaasurements shall be made and reported in accordance with
DEC.STD. 102.4, which includes the reQuirements of ANSI Sl.29,
which in turn includes the reauirements of ISO 3741 throu~h
3746 and of ISO 6081 for noise measurements.
5.10.14

ACCESSIBILITY
The power

suppl~

case can be o?ened

o~l~

the use of tools.

5.10.15

INPUT/OUTPUT CONNECTORS

5.10.15.1

AC LINE INPUT INTERFACE
AC line input is directly tinto a line filter, thru a three
pin IEC connector. An 18AWG power cord is reGuired.
AC LINE OUTPUT INTERFACE
A switched AC line output is provided thru a line filter to
provide power to the VR100 monitor that is supplied with the
s~ste~. The switched
AC line output has a maximum ratinS of
1 AMP at 120v AC. Connection to the external device is thru a
three pin IEC female connector.

5.10.16

DC OUTPUT CONNECTOR
The followinS voltases are available at the power supply output
connector.
When viewed from the rear of the power supply,PIN 1 is on the
risht.
PIN

VOLTAGE

DeOK
N/C
POK
-12V de
+12V de
+SV dc
+SV de
+5V de
+SV de
GND
GND
GND
GND
GNII
GND
GND

3
4
5
6
7
8
9

10
11
12
13
14
15
16

5.11

HULTIBOX

5.11.1

The VS100 is

ho~sed

fi~ure

5.11.2

to be suP?lied

PHYSICAL DIMENSIONS
height
width
depth
weight

5.11.3

in a cor?orate standard multibox

=
=
=
=

6.65 in (16.9cm)
19.21 in (48.9cm)
14.31 in (36.4cm)

T.B.5.

COLOR
The color of the multibox is DEC 068

gre~,

with DEC 217

gre~

trim

6.0

FIRMWARE

6.1

ROM RESIDENT
A. SIZE --- 16k
B. INSTRUCTIONS

, 16 bits (word)

3 basic commands
COfr~

area

move object
start display

c. FLOWCHART
T.B.S.
D. OPERATION

T.B.5.
RAM RESIDENT
A. SIZE
T.9.5.
B. INSTRUCTIONS
T.B.5.

c. FLOWCHART
T.B.S.
D. OPERATION

T.B.S.

7.0

MICRO DIAGNOSTICS
OVERALL MICROCODE STRATEGY
The VS100 microcode is defined as the 16.0 kilobyte
powerup/diasnostic packaSe, implemented in Motorola 68000 assembly
lan~uase, and resides in read-onl~ m~mor~ on the Display Processor
Module. The microcode is responsible for down-Ioadins the displa~
fi~mware, but is otherwise invisible to the host.
Host (VAX-l1)
diaSnostics are the property of the Macro Dia~nostic packase, but may
call the Micro Diagnostics via the Reset function.
When the user loSs
in, control ovar the 68000 uP shifts from the microcode to the displa~
firmware.
The microcode is comprised of four major sections;
Powerup, Idle Loop, Command Loop and Maintenance Mode.
The Powerup
code is responsible for testing and initialisins all hardware on the
terminal end of the VS100 system.
The Idle Loop performs a modified
continuing seauence of the Powerup code; and polls between tests for
Host WGA commands, Mou~e Login events, and Kesboard Maintenance Mode
entry events. The Command Loop waits for and processes WGA Commands
until the host sends the Reset Command to return the processor to the
Idle Loop. Maintenance Mode is used primaril~ to test the four
input/outPut devices that may be attached to the VS100 terminal:
1.
2.
3.
4.

DEC LK201 Universal Keyboard
Philips Monochrome 19 a /60Hz P4 Landscape Monitor
Hawles 3-button Mouse Pointins Device
aTeO 11· Disi-Pad Graphic Tablet with 5-button Cursor (optional)

These devices reauire a human interface, although the Kesboard and Table

t
also have self-tests which are called by the Powerup code.

7.0.1

POWERUP SELF-TEST
Tests occur in order of increasins lo~ic complexit~,
in order to maximise error detection and minimise the chance of a
catastrophic s~stem failure.
The 68000 remains at prioritw level
seven (all maskable interrupts disabled) until all liD control chips·
have been tested and initialised.
At this point, the priQrit~ level
is lowered to zero (all maskable interrupts enabled)+
The Power~p code should run less than twenty seconds;
the expected cold-start warm-up time for the monitor.
The Keyboard's
70-millisecond Self-Test runs in parallel, but is under the control
of the Ke~board'$ central processin~ unit.
At the end of Powerup SelfTest, one'of two icons is displa~ed on an otherwise white screen:
1.
2.

House LOSin Icon
S~stem Failure Icon

displa~ed if there were no Poweru? errors.
displayed if there were Powerup errors.

In addition, the ke~board's bell is runS when the Mous~ LOSin Icon is
to let the user know that the terminal is ready for normal
operation.
Lo~ins are disabled if there were errors on Powerup, but
are not disabled if errors are found durins Idle Loop.
Once the user
hits a mouse button to losin, however, there is the chance that the
link may be down or may So down while transmittins the mouse event to
the host.
In this case, the Mouse LoSin Icon is replaced by a third
icon; the Link Down Icon.
Whenever this icon appears on the screen,
it is UP to the host to reinitiate communication with the terminalt
displa~ed,

The Powerup code is structured so that confidence is
built hierarchicall~.
Each procedure first checks the error flas, and
skips over the diaSnostic portion if there were an~ previous errors
(onl~ the first detected error is reported, and further initialisation
functions only to enable entrance to Maintenance Mode).
Tests are
executed in the followins order:
A. SIZE

contained in the F/W roms appr 6kb

B. OPERATION
on power-up of the sYstem, the u-diasnostics will perform a
self test of the mother board, BBA board,FOT/R board,the fiber optic
link and the UBW board. The test cove raSe is )80%. Errors will be
reported b~ means of the leds located on the rear of the mother board,
and reported to the host CPU if possible. on successful completion 01
the power-up tests, the GREEN led on the motherboard will be lit, and
the u diaSnostics will enter IDLE self test until the user presses a
mouse button.

7.0.2

DC POWER SUPPLY
When power is initiallY applied to the Mother Board, an
internal RESET L siSnal provides a lOOms RESET si~nal to initialise the
hardware to a known state.
If the H7862 Power Supply volta~es are not
within tolerances (DC OK neSated), RESET L will be held true; thereb~
preventinS the microcode from startins.
The RESET L sisnal turns all
five Mother Board LED's (1 Green, 4 Red) on, which provides a test of
the LED's themselves.
~t the end of RESET L (nesated), the Pow~~up
code blinks the LED's off and on asain once.
This action also causes
the state seauencers to remap ROM from $000000 to $180000.

7.0.3

MOTOROLA 68000 MICROPROCESSOR

Two checkerboard test patterns ($55 and tAA) are used,
first for b~te path immediate data and next for lonSword path immediate
data, usin~ reSister dO.
Once dO has been verified for immediate addressinS, it
is reloaded with the first checkerboard pattern, $55555555.
This
pattern is then cascaded throu~h all eiSht data re~isters (dO-d7) and
all seven address reSisters (aO-a6).
The routine is then repeated with
dO initialised to the second checker-board pattern, $AAAAAAAA.
This
routine validates reSister RAM space and reSister source and
destination effective addressinS modes.
The third step is to test three loSical instructions;
landi, leor l , and ·or ' • After that, the siSned multipl~ and divide
instructions are verified, and finall~ the left-shift and riSht-rotate
instructions are verified.
The final step is to test bit manipulation usinS the
This is a particularl~ important
step, as the diasnostics rest heavil~ on the functionalit~ of the
bit-oriented instructions to determine their path.

BCLR, BSET, and Sec instructions.

7.0.4

ROM CHECKSUM

The ROM verification routine compares the truncated
a-bit computed checksum aSainst the correct value (stored at the end
of ROM).
This checksum is computed bs a VAX-1I FORTRAN utilit~, and
is inserted into the final b~te of the source file before creatins
the master set of ROM's.

PROGRAM MEMORY

7.0.5

A cursory memory te$t is performed, usin~ 32-bit
lonsword instructions. The test is in three basic sections:

I.
2.
3.

Clear proSram memor~ (wri~e all zeroes). This performs an initial
check on continuity of memor~ addressins.
Restart at the be~innins of memory. Read the current lonSword for
all zeroes, write all ones, read for all ones and pro~ress. to the
next lon~word until end of memor~.
Restart at the beSinninS of memor~+ Read the c~rrent lon~word for
all ones, write checkerboard pattern +1 ($55555555), read to verify,
write checkerboard pattern +2 ($AAAAAAAA), read to verify, clear the
location (write all zeroes), read for all zeroes and proSress to
the next lonswo~d until end of memory.
VECTOR IKITIALISATION

7.0.6

All 256 exception vectors are initialised to point to
code. Unimplemented vectors point to a common
exception handler which cleans UP the stack and, when in Maintenance
Mode, Sene rates an error messaSe indicatins which vector occurred and
what the value of the access address and prOSram counter was.
exception-recover~

7.0.7

MOTOROLA 6845 CRT CONTROLLER

The onl~ read/write resister of the eRTC is the cursor
which we test by writins and immediately verif~ing all data
patterns available; decrementins from SFFFFFF to zero. Upon completion
of the diasnostic, resisters are initialised to define the screen size
as 1088 pixels wide b~ 864 pixels hi~h (sivins a pixel separation of
approximatelY 1/78 inches, or .3256mm); as follows:
re~ister,

RO
Rl
R2
R3
R4
R5
R6
R7
R8
R9

RIO
Rll
R12
R13
R14
R15

(1472/32)-1 = 4S
1088132
34
(1088/32)+3 = 37
(0*16>+6
06
(900/12)-1
74
5
= 05
864112
= 72
(864/12)+1-1 = 72
o
00
12-1
11

total horizontal characters per line -1
displa~ed horizontal characters per line
horizontal sync position in characters
vertical/horizontal s~nc widths in characters
total vertical character rows per screen -1
adJust~ent to vertical sync to force 60-Hz
displa~ed vertical character rows per screen
vertical s~nc position in character rows +1 -1
non-interlaced mode, no skew
scan lines per character row -1

o
o
o
o
o

cursor start
cursor end
start address high bste
start address low byte
cursor high b~te
cursor low byte

=
=

=
=
= 00
= 00
= 00
= 00
= 00
= 00

7.0.8

TABLET PORT

Internal loop-back mode is set on the Tablet USART, and
the same scheme used to test the CRTC Cursor Resister is implemented
here on the data holdins re~ister.
The internal loop-back scheme
reGuires that the mode re~isters be set UP for normal operations, in
order to test the USART as it would normall~ be used.
Therefore, the
Tablet USART is initialised precedins the test, as follows!
Baud Rate (-- 9600
Parit~ Control Disabled
As~nchronous Receive/Transmit Mode
1 Stop Bit
8 Data Bits (Character LenSth)
I/O (-- 16 x Baud Rate
The I/O bit is initialised to 16 times the Baud Rate factor to account
for b~te-Iensth characters. Followins the test, the receiver is
enabled and the transmitter disabled.
The transmitter must be enabled
prior to each transmit operation, as transmit interrupts are cleared by
disabling the transmitter.
7.0.9

KEYBOARD PORT

Internal loop-back mode is set on the Keyboard USART,
and the same scheme used to test the CRTC Cursor ReSisters is implemented
here on the data holdinS reSister.
The internal loop-back scheme reauires
that the mode reSisters be set UP for normal operations, in order to test
the US ART as it would normall~ be used.
Ther~fore, the Ke~board USART is
initialised precedins the test, as follows:
Baud Rate (-- 4800
Parit~ Control Disabled
As~nchronous Receive/Transmit Mode
1 Stop Bit
8 Data Bits (Character LenSth)
I/O (-- 16 x Baud Rate
The I/O bit is initialised to 16 times the Baud Rate factor to account
for b~te-Ie~Sth characters. FollowinS the test, the receiver is
enabled and the transmitter disabled.
The transmitter must be enabled
prior to each transmit operation, as transmit interrupts are cleared by
disablinS the transmitter.

7.0.10

FIBRE OPTICS ELECTRICAL LOOP-BACK

The Fibre Control Register is set for Electrical LoopBack Mode, and two checkerboard patterns ($5555 and SAAAA) are then
written to the Host Control and Status Re~ister individually.
After
writing each pattern, NXM is checked for error status on the packet.
If NXM is oka~, then the pattern is read back from the loop-back
address.
If the packet returns bad information, the data will be
either all ones or all zeroes.
Followin~ this test, the Fibre Control
Register is set for Powerup State and Link_Available is checked.
If
the host's fibre light is on, the Link_Available software flag is set
and the terminal's fibre lisht is set at the end of Powerup (provided
that a Link Transition interrupt is not received in the meantime).
Otherwise, the terminal's fibre lisht remains off until a Link
Transition interrupt occurs.
An~ time the Fibre Control Re~ister is
written to, it must be followed b~ a 1ms timer to allow the host time
to receive the new status.
7.0.11
vs~nc

VSYNC VECTOR TIMEOUT
interru~t

7.0.12

Interrupt are now enabled.
If we do not receive a
within lOOms, a failure is reported.

FRAME BUFFER MEMORY

The same scheme is used as in the ProSram Memor~ test;
thou~h frame buffer memor~ is tested in four Guadrants, for the sake of
speed and modularit~.
Each Guadrant of frame buffer memor~ is the same
size as proSram memor~, so the frame buffer test entails four calls to
the common memor~ test.
7.0.13
the BBA.
1.
2.
3.
4.

BIT-BLOCK TRANSFER ACCELERATOR MODULE
The VS100 status resister is checked for th~ presence of
If the BBA is present, four tests are executed:

Scratchpad RAM -- all 256 words
Cop~area

Halftones
Vectors

7.0.14

KEYBOARD SELF-TEST

A reauest for the keYboard's hardware ID times out after
If the ID is received, we then call the keyboard's self-test.
It is necessary to call the Self-Test a~ain at this point, as the results
the previous Self-Test could not be interpreted b~ the uninitialised
68000.
The results of the current test are reported to the Keyboard
LED's, and to the 68000 via the followin~ four-b~te messa~e:
1 second.

KBID (Firmware)
KBID (Hardware)

The Keyboard ID which is stored in firmware
The Keyboard ID which is read from Jumpers
in the hardware
BYTE 3: ERROR CODE (Self-Test)
No Errors
00
Key down on Powerup
3D
Self-Test Failure, ROM or RAM
3E
BYTE 4: KEY CODE (Powerup)
No keys down on Powerup
00
Code for first key down on Powerup
xx

BYTE 1:
BYTE 2:

If the keyboard does not r~s?ond with the hardware ID after one second,
an error is assumed and reported.

7.1

IDLE LOOP

After successful completion of the Powerup code, the
68000 continuouslY loops on a modified version of the same code until
the user either lo~s in or enters Maintenance Mode.
If Idle Loop fails
a test, it does not do an~ more testins until the next pass.
All errors
are lo~~ed to the host, but onl~ the first error detected is reported to
the Mother Board and Keyboard LED's.
The followinS tests are executed
durin~ Idle Self-Test:

1.
2.
3.
4.
5.
6.
7.

68000 CPU (extended)
ROM Checksum
Pro~ram Memory (truncated)
Vs~nc Vector Time-Out
Frame Buffer Memory (truncated)
BBA Scratchpad Memory
Keyboard ID

Between tests, Idle Loop polls for mouse buttons (in which case the host
is informed), host commands (in which case we branch to the command
loop), and control/shift/f4 (in which case we branch to maintenance
mode).
After a mouse button is hit, we initialise a counter and increment it durin~ ysync for five seconds.
Between tests, we check this
fla~ to make sure the five minuts are not UP.
If we have not received a
command from the host in that time, and link is available, we can assume
the host is dead in the water and put the Link Down icon UP on the
screen.

7.2

COMMAND LOOP
The host

this point.
1.
2.
3.
4.

The

ma~

followin~

reauest the VS100 to perform WGA commands at
commands are defined at microcode level:

Reset (~o to Idle Loop via Powerup diasnostics)
Send_Command_Packet (includes Move_Object and Report_Status Commands)
Start_Displa~_Firmware (transfers control to the displa~ firmware)
Init (initialise CSR's and ~o to command loop)
Init initialises the Control/Status

1•
2.
3.
4.
5.
7.
6.
8.

CSR
CSR
CSR
CSR
CSR
CSR
CSR
CSR

to (Control/Status ReSister)
+1
+2
t3
+4
t5
t6
t7

(Interrupt Reason Resister)
(Peripheral Event Re~ister)
(Function Parameter Low)
(Function Parameter Hish)
(Identification Resister)
(Unused Resister)
(Interrupt Vector Resister)

Re~isters

as follows:

Untouched; taboo!
Bit 1 ( - - Init_Done
Cleared
Unibus_Ram base address low
Unibus_Ram base address hish
Bits 3-5 ( - - hardware ID
Cleared
Untouched; taboo!

CSR's +5/6 are the X and Y Mouse/Tablet Cursor Position Re~isters once the
displa~ firmware has been downloaded.
Refer to the Workstation Graphics
Architecture document for details on the Control/Status Re~isters.
After the first command, we wait in a loop for five
seconds for another command.
If we do not receive another command in
that time, we assume the host is dead in the water, put UP the Link
Down icon, and exit the command loop to re-enter Idle Loop.

7.3

MAINTENANCE MODE

Several tests are available to test the input/outPut
devices, as well as a special test for the fibre link.
All tests in
Maintenance Mode reQuire a human interface.
This mode is entered by
typinS (control/shift/f4> while in Idle Loop, and results in the
followinS menu bein~ printed to the screen:

***** VS100 Maintenance Mode

type function key f4 to exit

Keypad Options:

o
1
2
3
4
5

Jump to Powerup
Test
Mouse Test
Monitor Test
Tablet Test
Optical Loop-Back
Ke~board

TypinS 'f4' exits the menu and returns to the Idle Loop.
KEYBOARD FUNCTIONALITY TEST
Upon enterinS the Keyboard Test, the followins
messaSe is printed to the screen!

***** VS100 Maintenance Mode -- type function

ke~

f4 to exit

Keypad Options:

o
1
2
3
4

Return to Main Menu
Keyboard ID Test
Keyboard Self-Test
Keyboard Loop-Back
Ke~board Button Test

If any of the tests is called and fails, the status is
printed beneath the menu.
The user is advised to execute tests 1-3
(which indirectly tests those keys), then t~pe '4' to select.the Button
Test. A 'Current Keycode: ' prompt will then appear beneath the menu.
Type each of the other keys on the keyboard EXCEPT for the '0' on the
keypad.
Then 'metronome' any key, and type '0' to exit and return to
the main menu.
The ke~code for the ke~ pressed will be sent to the
screen in decimal format, by the 'Current Keycode: 'header. Metronome
also results in a code beinS displayed, as does the release of the shift
or control keys.
The keyboard button test sits in a loop that polls
for keyboard keycodes.

HOUSE FUNCTIONALITY TEST
Upon enterin~ this mode, the
?rinted to the screen:

***** VS100 Maintenance Mode -Ke~pad

o
1
2

t~?e

function

followin~

ke~

messa~e

f4 to exit

Options:

Return to Main Menu
Mouse Button Test
Mouse Cursor Test

There are basicall~ two aspects of the mouse that need
to be tested; directional/ma~nitudinal accurac~ of the cursor, and
communication of mouse button events.
If the Button Test is selected,
a ·Current Button: • prompt appears beneath the menu and records the
number of the button that is currentl~ bein~ held down.
If no button
is depressed, the line contains information on the last button it received. The button test essentiall~ sits on a loop that polls the
VS100 status re~ister for mouse buttons.
If the Cursor Test is selected, the screen is erased
and a 64 x 64 pixel crosshair cursor is masked to the screen.
The
cursor is updated at ever~ frame interrupt to indicate movement of the
mouse, and is initialised to the screen centre.
A 64 x 64 pixel black
peripheral box is masked to each of the four corners of the screen at
an offset of 64 pixels in each direction (to allow passa~e of the
crosshair cursor around the boxes), asainst the standard ~raphics
halftone back~round (halftone 19). The mouse is used to move the
cursor onto, around, and inside each of the boxes; to test ~eneral
directional and masnitudinal correctness.

MONITOR TEST
Upon

enterin~

this test, the

fol10win~

menu is printed

to the screen:

***** VS100 Maintenance Mode --

t~pe

function key f4 to exit

Keypad Options:

o
1
2
3
For

Return to Main Menu
Universal Alisnment Pattern
Stairstep of Halftones
TOSSle Screen Contents
an~

pattern, the screen is preserved until ·0· is hit to exit.

7.3.3.1 TEST PATTERN 11 (Universal Alisnment

Patt~rn)

The first monitor test pattern produces a stationary
diaSram on the screen for adjustments and measurements, in five stases:

1.
2.

PeripherY DiaSram: The first and last pixel of each row and column
are lit in order to define the active display area for centrins
adjustments.
Crosshatch Pattern: Centred at a vertical indentation of 42 pixels
(13.68mm), "and a horizontal indentation of 48 pixels (14.33mm), is
a black-on-white crosshatch pattern, comprised of one-pixel wide
lines at 1/20 pixel spacins (6.513mm).
White Central Outer Box:
A white rectansular box of dimensions 608
pixels hiSh (198.01mm) b~ 448 pixels hish (14S.89mm) is centred at
the screen centre.
The box is solid, and is written directly to the
screen rather than masked onto the crosshatch.
It is only a few
pixels sh~ of beinS tansent to the white peripher~l circle.
Black Central Inner Box:
A black SQuare box of dimension 112 pixels
(36.47mm) is centred at the screen centre. The box is solid, and
is written directly to the screen rather than masked onto the white
box.
Centred Pehripheral Circle:
A white circle is .senerated about the
screen centre utilsins Michener1s adaptation of Bresenham's circle
alsorithm.
The diameter is 768 pixels (250.1mm), so that the
circle is only five pixels shy of beinS tanSent to the crosshatch
peripher~.

7.3.3.2 TEST PATTERN t2 (Stairstep of Halftones)
The second monitor test pattern is a stairstep of 17
halftones, soins from left to riSht.
The fir$t halftone is black, the
last halftone is white, and the fifteen halftones in between are the
standard 05100 halftones. Each halftone pattern spans the screen
heisht and is 64 pixels wide.
7.3.3.3 TEST PATTERN t3 (ToSSle Screen Contents)
ReSardless of which test was executed previously, this
command tossles the entire current screen contents. This effectivel~
doubles the number of screen patterns available.
The pattern can always

be tossled back to what it was

selectin~

this command

a~ain.

TABLET FUNCTIONALITY TEST
Upon enterin~ this mode, the
printed to the screen:

followin~

messaSe

***** VS100 Maintenance Mode -- type function key f4 to exit
Keypad Options:

o
1
2

R~turn to Main Menu
Tablet Button Test
Tablet Puck Test

Similar to the House Test, except that the Tablet has 5
buttons numbered 0-4.
For future adaptabilit~ to 16-button pucks, a
decimal conversion routine is used to report the button number.

FIBRE OPTICS OPTICAL LOOP-BACK TEST
Same as electrical loop-back test in powerup, except the
test is perf~rmed with the fibre lisht on, and a loop-back-is reauired.

EXCEPTIONS & INTERRUPTS
All two-hundred fift~-six 68000 interrupts and
exceptions are suPPorted b~ the microcode, whether or not they can
be expected to occur.
The 68000 provides two kinds of interrupts;
Auto-Vectored and Device-Vectored.
The VS100 utilises the Auto-Vector
system.
All unimplemented interrupts and exceptions result in the
~eneration of an error code/messase.
EXCEPTIONS
Bus_Errors are ~enerated by accessin~ non-existant
Unibus memory (if NXM is set), when the link Soes down while accessin~
le~itimat~ Unibus memor~ (not includin~ CSR's, which are alwa~s
considered to be accessible), or when the retrY counter overflows.
Address_Errors occur when a word or Ions-word operand is accessed at
an odd address.
Other exceptions are initialised even thouSh unused,
in order to insure asainst hardware/firmware/microcode buss. All
exceptions other than bus errors .re recovered from by use of the rte
instruction.

AUTO-VECTOR INTERRUPTS
Seven level$ of interrupts are available on the 68000,
in increasins level of priorit~.
The hiShest level of interrupt is nonmaskable.
The auto-vectors are assisned as follows:

I Level I

Ad~re5s(hex)

I VS100 Device

1-------1--------------1---------------------------------------I
0
I
---------I
No Interrupt
1-------1--------------1---------------------------------------I
1
I
64
I
HOIJse Cursor
1-------1--------------1---------------------------------------I
2
1
68
1
Receive/Transmit
1-------1--------------1---------------------------------------I
3
1
he
I
Tablet
1-------1--------------1---------------------------------------1
4
1
70
1 BBA Command Done
1-------1--------------1---------------------------------------1
5
1
74
1 Link_Tran$ition or Link_Error
Ke~board

I-------I--------------I------------~--------------------------1
6
I
78
I Vertical S'::Inc

l-------I--------------l---------------------------------------7
I
7C
I
BBA Non-Existent UBW
Access

Memor~

1-------1--------------1---------------------------------------Ke~board and Tablet Interrupts occur under two
conditions:
When the USART HoldinS Resister receives a b~te of
information from the device, a receiver interrupt is Senerated.
When the USART HoldinS ReSister transmits a b~te of information to
the device, a transmitter interrupt is Senerated.
Receiver interrupts are cleared by readinS the data from the HoldinS Resist~r.
Transmitter interrupts are cleared b~ disablinS the transmitter.

Vertical S~nc interrupts occur at ever'::l vertical s~nc;
that is, every 1/60 second.
House Buttons are polled durinS vertical
sync handlinS, for the purpose of reportins loSin events to the host.
Vertical S~nc interrupts are cleared b~ performins a read operation
on address $8000E1.
Mouse interrupts occur ever~ time the mouse is moved.
The information is stored and used durins vertical s~nc handlins to
update the mouse cursor when it is attached.
House interrupts are
cleared b~ readinS data from the mouse cursor.
Link_Error Interrupts are iSnored, but Link_Transition
Interrupts are used to determine whether or not to turn on the fibre's
LED driver at the VS100 end of the s~stem.
We store the information of
the current state in memor~, and examine Link_Available to determine
whether to turn the LED on or off.
Link_Transition occurs when the
state of the LED driver at the UBW end of the s~stem chanSes.
Each interrupts sets a flas indicatins that it occurred.
(e.S., levelS sets the Ilink_transitionl flaS).
These flass are all
cleared on powerup.

7.5

ERROR REPORTING

All dia~nostics at all levels of microcode attempt to
report errors in each of three wa~s:
i.

2.
3.

Error code to Mother Board LED's
code to LK201 Ke~board LED's
Error code to Host's Interrupt Reason
E~ror

Re~ister

(CSR il)

The error code is a n~bble (4 bits) code identifyin~ the test that
failed.
The code is the same for all three error code output forms.
POWERUP:
~reen led off, test. in LEDS.
Code set in advance of test.
If error, skip rest of powerup dia~nostics and freeze ·the led code
durin~ idle loop tests.
IDLE LOOP:
~reen led on, test t
in LEDS.
Code set in advance of test.
If error, replace led code with powerup error code; that is, ~reen led
off and test t in leds.
I~nore rest of idle loop, freeze leds, but
start testin~ a~ain at be~innin~ of next idle loop.
Green led on, test i in leds.
MANUFACTURING:
read status for Jumper.
No keyboard leds or reportin~ to host or screen message (that is, loop
before reaching ·process_errors·).
Loop on any test that fails, but
otherwise loop back to the be~inning of powerup (after first lockins
out interrupt and reloading the stack).

LED Number
3

---------~~---~

o I 0 I 0

---1---1--o I 0 1 1

Dia~nostic

Reason

---------~--------~-~---------------~-----------~-------

68000 CPU error

---1---1---------------------------------------------------------o I 0 I 1 0
ROM Checksum error
---1---1---

o I 1

---1---1--o 1 1 I 0

-------------------------------------------------------Pro~ram

RAM error

-------------------------------------------------------CRTC

Re~ister

error

-------------------------------------------------------Tablet Port error

---1---1-----1-------------------------------------------------------Q I 1 I 1
0
Port error
---1---1---------------------------------------------------------o I 1 I 1
1
Fibre Optics Loop-Back error
Ke~board

---1--1 I 0

1 1 0

---1--1 I 0

---1---

-------------------------------------------------------Vs~nc Time-Out error

-------------------------------------------------------Frame Buffer error

-------------------------------------------------------BBA Scratchpad error

-------------------------------------------------------BBA Command error

---1-----1---------------------------------------------------------1 I 1
0 I 0
Tablet ID error
---1-----1---------------------------------------------------------1 I 1
0 I 1
Tablet Self-Test error
---1-----1--- -------------------------------------------------------1 I 1 1 1 I 0 I
ID error
---1---1---1---1-------------------------------------------------------1 I 1 I 1 I 1 I
Self-Test error
Ke~board

Ke~board

___ 1___ 1___ 1___ 1______ -------------------------------- _________________ _

·0· is used to indicate that the LED is turned off; ·1· is used to
indicate that it is on.
The same code is used for the Ke~board LEDS,
Mother Board LEDS and Ho~t Interrupt Reason Re~ister (with bits 14 and
15 turned on to indicate a dia~nostic failure>.
The Mother Board also
has a ~reen LED, which is used to indicate the mode that the machine is
operatin~ under.
Durin~ Powerup, the error code on the Mother Board is
set in advance of each test with the ~reen LED turned off to indicate
that the test failed (in case it does not reach completion).
Once the
Powerup confidence test is done and we enter Idle Loop, the error code
on the Mother Board is set in advance of each test with the ~reen LED
turned on to indicate no errors.
If the test finds a failure, it
repl~ces the same error code with the Powerup error code; i.e., the
~reen LED is turned off to indicate an error condition.
Onl~ the first
error detected is reported to the Hother Board LEDS.
Once an error is
detected, it is reported to the Ke~board LEDS and the Host Interrupt
Reason Re~ister.
Onl~ the first error detected is reported to the
Ke~board LEDS, but all errors are reported to the Host (includin~ bit
14 set to indicate error durin~ Idle Loop yersu~ Powerup failure>.

7.6

MANUFACTURING MODE

Manufacturin~ Mode is entered upon powerup when a Jumper
is in place next to the Mother Board LED's.
In this mode, loop-back
connectors are used at the ke~board and tablet ports for special tests
that are available ONLY when the Jumper is in place and are executed in
place of the normal I/O self-tests.
At the end of the Powerup SelfTest, the microcode Jumps back to a location in ROM (to be determined)
and executes the entire self-test.
This c~cle continues indefinitelw.

Hanufacturin~ Mode is a special mode used b~ the module
facility durin~ burn-in of the VS100 Mother Board.
A
Jumper has been provided which the 68000 reads to determine whether the
module is in a manufacturin~ environment.
When the Jumper is in place,
the normal Powerup seGuence is sli~htl~ modified, and error reportin~
is limited solely to the Mother Board LED's.
For Manufacturin~ Mode to
function properly, the tollowins loop-back connectors must be in place
BEFORE power is applied:

manufacturin~

Tablet I/O
Pin 2 connected to Pin 3
Keyboard I/O
Pin 2 connected to Pin 3
Fibre Optics Optical Loop-Back Connector in Place
The Bit Block Transfer Accelerator Module is optional:
The microdia~nostic checks for presence of the module, and skips the BBA selftest if the module is not present.
The

followin~

tests are modified as follows:

Fibre Optics Loop-BaCK Test
The electrical loop-back test is now followed b~ an optical
loop-back test, which is the same except for that it reQuires
a special Jumper to be in place.

Tablet USART Test
The internal loop-back test is now followed by an external
loop-back test, which is the same except for that it reQuires
a special Jumper to be in place.

Ke~board

USART Test
The internal lOOP-back test is now followed b~ an external
loop-back test, which is the same except for that it reQuires
a special Jumper to be in place.
The followins tests are deleted:

1.
2.

Ke~board
Ke~board

ID Test
Self-Test

7.7

MC68000 MEMORY MAP

Address

(he~<)

FFFFFF

8000EO
8000EO

Ixxxxxxxxxxxxxxxx1
Ixxxxxxxxxxxxxxxxi
Ixxxxxxxxxxxxxxxxi
Ixxxxxxxxxxxxxxxxi

1----------------1
I
CLEAR_VSYNC
I
----------------1
xxxxxxxxxxxxxxxxi

1 word

xxxxxxxxxxxxxxxxi

8000C2
8000CO

----------------1
VS100_STATUS I
----------------1
xxxxxxxxxxxxxxxx

1 word

CRT_CONTROLLER

2 words

8000A4
8000AO

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
800082
1 word

800080

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxx:<
800062

HOUSE_CURSOR
800060

1 word

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxx~<

800042

FIBRE_CONTROL

1 word

800040

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxi

800028
800020

1---------------I
TABLET_USART
1---------------Ixxxxxxxxxxxxxxxx

4 words

Ixxxxxxxxxxxxxxxx

800008
800000

1---------------I KEYBOARD_USART
1---------------Ixxxxxxxxxxxxxxxx

4 words

Ixxxxxxxxxxxxxxxx

4C0002

1---------------HOST_INTERRUPT
1---------------Ixxxxxxxxxxxxxxxx
I

4COOOO

1 word

Ixxxxxxxxxxxxxxxx

4A0002

1---------------I
LOOP_BACK

4AOOOO

1 ______ ----------

1 word.

4AOOOO
Ixxxxxxxxxxxxxxxxi
Ixxxxxxxxxxxxxxxxl

480010

1----------------1
HOST_CSRS
I

480000

---------- ______ 1

8 words

xxxxxxxxxxxxxxxxi
260002
1 word

260000

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
240200

BBA_SCRATCHPAII

256 words

240000

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
184000
8K words

180000

FRAME_BUFFER

256K words

100000

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
OE0002

RETRY_INFINITE

1 word

OEOOOO

xxxxxxxxxxxxxxxx
OC0002

RETRY_FINITE

1 word

OCOOOO

xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
OAOOOO

641< words
080000

xxxxxxxxxxxxxxxx
020000
000000

PROGRAM_RAM

641( words

7.8

VS100 STATUS REGISTER
Here is a

bit

•

7
I
1
I
I
I
I
t

ma~

of the VS100

read-onl~

status reSister:

6 5 4 3 2 1 0
I 1
I ,----- ManlJfacturing Mode (0 = ~es,
1
'--_
..... BBA Present (0 = '::f.es, 1 = no)
I I
I
\
_
....
--no, 1
~es)
NXM (0
I
I I
t
I \_---- RetrY_Overflow (0 = no, 1 = ~es)

1 = no)

..... __ ... Link_Available (0 = no, 1 = ~es)
' .. __ ....... Left HOIJse Button (0 = '!:Ies, 1 = no)
'----- Centre Mouse Button (0 = '::Ies, 1 = no)
,----- Right MOIJse BIJtton (0 = '!:Ies, 1 = no)
I
I

Manufacturins Mode is set when the host is performing an electrical
loop-back on the fibre link at its own end. NXM is set when non-existant
UBW memor~ is accessed from the 68000.
If non-existant UBW memor~ is
accessed from the BBA, a leve17 interrupt is Senerated instead. The 68000
generates a bus error when NXM is set, and it is the dut'!:l of the microcode
to examine this register in the bus error routine to determine the nature
of the bus error.
House buttons Senerate a zero code when de~ressed, but
their status bits otherwise remain hiSh. Link_Available True means that
the LED is lit at the UBW end of the fibre link.

7.8.1

HOUSE CURSOR

The mouse cursor re~ister contains two ei~ht-bit
counters which kee? track of the mouse's horizontal and vertical
moverraer,t:
bit +

15 14 13 12 11 10

1~71~61~51~41~31~21~11~Olx7Ix6ix5Ix4Ix3Ix2IxllxOf

\ __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1 __ 1

MOTHER BOARD LED's
There are five LED's on the Mother Board; four red LED's
and one ~reen LED. The ~reen LED is used to indicate OK status of the
VS100, and the red LED's are used to report error conditions.
bit

•

7 6 5 4 3 2 1 0
Red LED +3
1 I t I I
I \ ......
,---- Red LED +2
I I I I 1
I ,-_ .... - Red LEI' 11

,---- Red LED +0

,---- Green LED

,---- Tied to Pin 4
,---- Unused
,---- Un'Jsed

FIBRE CONTROL
The fibre control re~ister uses three bits.
These are
and are used by the hardware.
XMIT ON causes the
hardware to li~ht the LED at the Mother Board end of the fibre link.
The other two signals are dia~nostic signals.
write-onl~

si~nals,

765 432 1 0

bit t

1 ,----

=
=

Xmit On (0
nO, 1
yes)
,---- Maintenance Mode (0
no, 1
~es)
,---- Force CRC Error (0
no, 1
~es)
,---- Unused
,---- Unused
,---- Unused
,---- Unused
,---- Unused

The followins bit patterns are defined:
Xmit On J Maintenance Hade
I
Purpose
--------I--------------------I--~-------------------o
I
0
I
Powerup State

--------1--------------------1----------------------o
I
1
I
Electrical Loop-Back
--------1--------------------1----------------------1
I
0
I
Normal Operation
--------I~-------------------I----------------------1
I
1
I
Optical Loop-Back
-- ______ 1 ______ -------- ______ 1______ -----------------

7.8.4

USART's (Motorola 2661 EPCI's)

68000.

Each USART has four resisters that are accessible
The map is as followsl

B~te

3
5
7

B~te
B~te

the

Holding ReSister
Status Register
Mode Resisters
Control Resister

The first time one writes to B~te 5, one accesses Mode ReSister O.
Thereafter, an~ reference to B~te 5 refers to Mode Re~ister 1.
B~te 1
refers to the Transmit Holdins Register or the Receive Holding Resister,
dependins on whether one is performing a read or write operation.

7.8.5

CRT CONTROLLER

The CRT Controller is two b~tes.
B~te 1 is the address
pointer.
Byte 2 is the data resister.
You must write the value of the
resister ~ou wish to write to into the address pointer before writins
the desired value of that reSister into the CRTC's data resister.

8.0

SOFTWARE
1. OVERVIEW
W6A/SDA
DESCRIPTION
3. OPERATION
4+ DEVICE DRIVER
2+

The device driver for the VAXSTATION 100 display will
permit a callins prosram to send command and arSument lists to the
VS100 DISPLAY PROCESSOR. In addition to this basic function, the
driver can be instructed to start and stop the displa~ processor,load
the ~rocessor microcode from VAX memor~ or disk, and load character
fonts.

9.0

PERFORMANCE
1. HARDWARE LIMITS
A.

memor~

access cycle time

= 400ns.

B. screen memory access time = 800ns.

c. unibus

memor~

access time

1. fiber optiC'

2. worst case unibus access time
3. vax memory cycle time

2. SOFTWARE OVERHEAD
T.B.D.

10.0

MAINTAINABILITY
RELIABILITY
A. SYSTEM M.B.T.F.
The s~stem goal is 4000hrs
MTTR 2.0 Mrs or less
MTTI 4.0 Mrs or less
B. SUB-ASSEMBLY M.B.T.F.
Calaulated MTBF

ALL VALUES ARE
CALCULATED USEING
MIL SPEC STANDARD

UNIT

hrs X 1000

MOTHERBOARD
U.B.W.
F.O.T/R
B.B.A
H7865
MONITOR
LK201

15.1
91.9
278.0
92.53
23.9
15.5
66.8

( less usea~e than
the PC350)

217 @ G.B.

CABLES
2000.0
MOUSE
35.0
TILT/SWIVEL
n/a
FIBER CABLE
87.71 (300m,at min bend rad.)
Min bend radius = 3.0cm for whole cable
Min bend radius
2.0cm for sub-channel
(check the spec.)

11.0

MAINTAINABILITY

No customer maintainable components. No customer adjustable controls

12.0

HUMAN FACTORS
FLOW CHART OF INTERFACE -- TO BE SUPPLIED

13.0

REFERENCE MATERIAL

DEC. STD. 158

UNIBUS SPECIFICATION

A-PS-17-00333-0-0 CABLE,FIBER OPTIC,TWO CHANNEL,UNTERMINATED
A-PS-17-00343-0-0 CABLE,FIBER OPTIC, TWO CHANNEL,TERMINATED
A-SP-H7865-0-0

POWER SUPPLY, H7865,MULTIPLE OUTPUT,5V,+12V,-12V

A-PS-30-20240-0-0 MONITOR,ALPHA/GRAPHIC VIDEO, 19 INCH, MONOCHROME
A-PS-30-20037-0-0 TABLET, DIGITIZING
A-PS-30-20038-0-1 MOUSE"HAND HELD
A-SP-LK201-A-2 LK201 KEYBOARD DESIGN SPECIFICATION
WORKSTATION GRAHPIC ARCHITECTURE
Driver spec --- latest

cop~

V1.0, 1 MARCH 1983, H LEVY
april 82

firmware spec --- not available
uCode spec
Dia~

spec level 2b