Digital PDFs

MISC-68417873

1986

148 pages

Original

7.9MB

Document:	VAX Hardware Handbook Volume 2
Order Number:	MISC-68417873
Revision:
Pages:	148
Original Filename:

OCR Text

VAX Hardware Handbook
Volume 2 - 1986

Digital believes the information in this publication is accurate as of its publication date; such information is subject to change without notice. Digital is not
responsible for any inadvertent errors.
The following are trademarks of Digital Equipment Corporation:
DEC
DECsystem-lO
DECSYSTEM-20
DECUS
DECmate
DECnet
DECwriter

DJBOL
MASSBUS
PDP
PlOS

Professional
Rainbow
RSTS

RSX
UNJBUS
VAX
VAXBI
VMS
VT

Chapter I-Overview: Digital's Second-generation VAX Systems
New Top-of-the-line Systems ................................... 1-4
lliwer in Compact Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
VAXBI Bus - Forthe New Generation of VAX Systems .............. 1-5
VAXcluster Configurations Increase VAX System Capacity ............. 1-5
Features Common to All VAX Processors Systems ................... 1-6
VAX 8800 High-performance System ............................. 1-8
VAX 8700 System ............................................ 1-9
VAX 8650 System ............................................ 1-9
VAX 8550 and VAX 8500 Systems ............................... 1-10
VAX 8200 and VAX 8300 Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
Mass-storage Extensions ..................................... 1-11
KDB50 Single-host Disk Controller . . . . . . . . . . . . . . . . . . .. . . . . . .. 1-11
HSC70 High-performance Mass-storage SelVer . . . . . . . . . . . . . . . . .. 1-12
TA81 Magnetic Thpe Subsystem .............................. 1-12
TU81-Plus Magnetic Thpe Subsystem .......................... 1-12
Main Memory Extensions ........................... . . . . . . . .. 1-13
How to Order VAX Systems and VAXcluster Systems ............... 1-13
Chapter 2 -VAX 8800 and 8700 Processor Systems
VAX 8800 and VAX 8700 Physical Configuration .................... 2-2
System Expansion Cabinets .................................. 2-3
VAX 8800 and VAX 8700 Processor Organization ................... ,2-4
Console Subsystem ........................................ 2-5
Console Processor ....................................... 2-6
Console Subsystem Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Console Command Language .............................. 2-7
Central Processing Unit ....................................... 2-7
Instruction Box ...................... . . . . . . . . . . . . . . . . . . . . . 2-8
Instruction Buffer ....................................... 2-9
Instruction Decoder ...................................... 2-9
Microsequencer ......................................... 2-9
Control Store ........................................... 2-9
Condition Code and Macrobranch Logic .................... 2-10
Interrupt and Processor Logic ............................. 2-10
- File Address Generator .................................. 2-10
Gateway Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Cache Box .............................................. 2-11
'franslation Buffer. ...................................... 2-11
Data Store Cache ....................................... 2-11
Memory Interconnect Interface ............................ 2-12
Execution Box ........................................ , .. 2-12
Register File ........................................... 2-13
Data File .............................................. 2-13
Program Counter ....................................... 2-13
Arithmetic and Logic Unit ....................... , ........ 2-14
Shifter ............................................... 2-14
Floating-Ibint Support ................................... 2-14
Multiplier ............................................. 2-15
Memory Box ............................................ 2-15
Memory Control Logic Module ............................ 2-16
Array Bus ............................................. 2-16
Memory Arrays ........................................ 2-16
Data Protection ........................................ 2-17
Processor Buses .......................................... 2-18
Memory Interconnect (MI) Bus ............................ 2-18
Visibility Bus .......................................... 2-18
Data-Thth Buses ........................................ 2-19
Ibwer Subsystem ......................................... 2-19
Controller ............................................. 2-20
Ibwer Conditioning (Nbox) ............................... 2-20
Modular Ibwer Supplies ................................. 2-21
Environmental Monitoring Module ......................... 2-21
Battery Backup Unit. .................................... 2-21
Clock Subsystem ......................................... 2-21
Input/Output System ...................................... 2-23
VAX Bus Interconnect ................................... 2-23
VAXBI Bus Adapters ..................................... 2-24
Mass-storage Subsystems ..................................... 2-25
Reliability, Availability, and Maintainability ....................... 2-25
Reliability .................... , .......................... 2-25
Availability ................................ , ....... , ..... 2-26
Maintainability ........................................... 2-26
Chapter 3 • VAX 8650 Processor

VAX 8650 Physical Configuration ................................ 3-3
System Expansion Cabinets .................................. 3-4
VAX 8650 Processor Organization ............................... 3-5
Console Subsystem ........................................ 3-6

Central Processing Unit ....................................... 3-8
Instruction Box Functions ................................... 3-9
Execution Box Functions ................................... 3-11
Floating-point Accelerator Functions .......................... 3-12
Memory Controller Functions ............................... 3-13
Synchronous Backplane Interconnect Functions ................. 3-15
Cache Memory ........................................... 3-16
Environmental Monitoring Module ........................... 3-16
Main Memory ........................................... 3-16
Memory Arrays ........................................ 3-17
Refresh Intetval ........................................ 3-18
Input/Output Subsystems .................................. 3-19
Synchronous Backplane Interconnect Adapter ................ 3-20
Adapters ............................................. 3-21
Reliability, Availability, and Maintainability ....................... 3-22
Battery Backup Unit ....................................... 3-23
Error Checking Code ...................................... 3-23
Error Analysis and Reporting ................................ 3-24
High Availability Design .................................... 3-24
Dynamic Fault Insertion ................................... 3-25
Serial Diagnostic Bus ...................................... 3-25
Microhardcore Context Commands .......................... 3-25
Debug and 'Il:ace Facility ................................... 3-26
Parity Checks ............................................ 3-26
Cache Memory Parity Checks ............................. 3-26
Control Store Parity Checks ............................... 3-26
General Purpose Register Checks .......................... 3-27
Internal Bus Parity Checks ................................ 3-27
Ebox Arithmetic Unit Parity Checks ........................ 3-27
Control Ram Parity Checks ............................... 3-27
Reliability and Maintainability Features ........................ 3-27
Chapter 4 • VAX 8550 and VAX 8500 Processors
VAX 8550 and VAX 8500 Physical Configuration .................... 4-2
VAX 8550 and VAX 8500 Processor Organization ................... 4-4
Main Memory ............................................ 4-6
VAXBI 110 Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
UNlliUS Support for VAX 8500 and VAX 8550 Systems ............. 4-6
Digital Networks and VAXcluster Systems ....................... 4-6
Reliability, Availability, and Maintainability ........................ 4-7

Chapter 5 • VAX 8200 and 8300 Processors

VAX 8200/8300 System Configurations ............. ; ............... 5-3
Console Subsystem ........................................ 5-7
Central Processing Unit ....................................... 5-8
CPU Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
InstructionlExecution (J/E) Chip ............................ 5-9
Memory Interface (M) Chip ............................... 5-10
Floating Ibint Accelerator (F) Chip ......................... 5-11
Control Store ................................. '.' ....... 5-11
Backup 1tanslation Buffer . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 5 -12
Cache Ram ............................................ 5-12
VAXBI Interface Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Ibrt Controller Section ..................................... 5-12
MainMemory ........................................... 5-13
Ibwer Subsystem ............................. '.' .......... 5-13
Input/output Subsystem ................................... 5-14
Mass Storage Subsystems ................................... 5-14
Reliability, Accessibility, and Maintainability ...................... 5-14
Batrery Backup Unit. ...................................... 5-16
Cooling Subsystem Monitoring .............................. 5-16
Error Correction Code ..................................... 5-16
Self-test Routine ........................................... 5-16
Processor Self-test Routine ................................ 5-16
Memory Self-test Routine ................................. 5-17
Zero Insertion Force (ZIF) Connectors ........................ 5-17
Chapter 6 • VAX Privileged Registers

Architectural Processor Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
System Identification Register ............. :.................. 6-2
VAXBI Registers ...................................... "...... 6-3
Device Register. . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . .. . . . . . . . . 6-4
VAXBI Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Bus Error Register .................•....................... 6-5
ErrorInterrupt Control Register ..................... ; . . . . . . . . 6-6
IN1R Destination Register . . .. . .. . . .. . . .. . . .. . .. . . .. . .. . .. .. . . 6-6
IPIN1R Mask Register ....................................... 6-6
Force-bit IPINTRIS10P Destination Register ........•............. 6-6
IPIN1R Source Register .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 6-7
Starting Address Register ................................ , . . . 6"7
Ending Address Register .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

BCI Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Write Status Register ....................................... 6-8
Force-bit IPINTRlS10P Command Register ...................... 6-9
User Interface Interrupt Control Register ....................... 6-9
General Purpose Registers ................................... 6-9
Slave-only Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Receive Console Data Register ............................... 6-10
VAX 8800/8700 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Machine Check Status Register .............................. 6-11
NMI Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-11
NMI FaultiStatus Register .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
NMI Silo Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
NMI Error Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Cache On Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Revision Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Revision Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
NBIA Adapter Control/Status and Vector Registers . . . . . . . . . . . . . . . . . 6-13
Memory Controller Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-15
VAX 8650 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
VAX 8550/8500 Registers ..................................... 6-16
VAX 8300/8200 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Chapter 7 • Mass Storage Systems

Intelligent Mass Storage Controllers ............................. 7-1
HSC50 Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-2
HSC70 Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
KDB50 Controller ......................................... 7-4
Thpe Storage Media Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
TA81 Thpe Storage Device ................................... 7-6
TU81-Plus Thpe Storage Device ............................... 7-8

Appendix A • VAX Processor Specifications
VAX 8200 Processors ......................................... A-I
VAX 8300 Processor .......................................... A-2
VAX 8500 and VAX 8550 Processors ............................. A-3
VAX 8700 Processors ......................................... A-4
VAX 8800 Processors ......................................... A-5

\blume 2 of the VAX Hardware Handbook describes the latest additions to
Digital's VAX family. Included are seven recently introduced VAX systems VAX 8800/8700, VAX 8650, VAX 8500/8550, and VAX 8200/8300 - each consisting of a 32-bit central processor, memory, console subsystem, operating system and system so&ware, storage devices, communications equipment, and
optional hardware and so&ware products.
\blume 2 also describes the newer VAX family mass storage products - the
HSC70 and KDB50 intelligent controllers, and the TA81 and TU81-plus tape
drives.
.
For basic concepts and features of VAX hardware and architecture refer to \blume 1 of the VAX Hardware Handbook and the VAX Architecture Handbook.
For popular system configurations or to configure systems tailored to yoUr
applications, consult your nearest Digital Sales Office and the VAX Systems and
Options Catalog. Other useful references are the VAXBI Options Handbook,
VAX Software Source Book, and the Networks and Communications Buyer's

Guide.

1 • Overview: Digital's ~~;bD<d'alenf:ration
Systems

Digital's VAX computers represent the only fully compatible, integrated, and
fully networked family of computers available in the industry. Spanning a range
from powerful large systems to individual workstations, these secondgeneration VAX systems include the VAX 8800, VAX 8700, VAX 8650, VAX 8600,
VAX 8550, VAX 8500, VAX 8300, VAX 8200, and MicroVAX II systems. These
systems expand users' choices and represent dramatic improvements in price
and performance. All use the same VMS operating system - giving users access
to more than 3,000 applications programs. And all take advantage of the most
extensive computer networking products available in the industry today.
1ltble 1-1 gives a quick overview of the capabilities and options of the VAX systems discussed in the two volumes of the hardware handbook. Note that costeffective upgrade options exist between numerous systems to further protect
your investment.

.....

""•

Table 1-1 • VAX System Comparison Chart

CPU Technology

MicroVAXII,
VAXstation III
VAXstation II1GPX

VAX-1l/780

ZMOS

Bipolar Schottky

VAX 8200
VAX 8300

VAX 8500
VAX 8550

VAX 8600
VAX 8650

VAX 8700
VAX 8800

ZMOS
8200: 1.0
8300: 1.6-1.9*

ECLGate
Array
8500:3
8550:6

ECLGate
Array
8600:42
8650:6

ECLGate
Array
8700:6
8800: 9-12*

256 Kbit
ECCMOS
68Ml3
8600: 4MB
8650: 16MB
16KB

256Kbit
ECCMOS
128MB
32MB

TIL

Mormance x VAX-11/780
MEMORY
Type

0_9

1.0

Maximum Support
Minimum Support

256 Kbit
ParityMOS
16MB
2MB

256 Kbit
ECCMOS
64MB
2MB

256Kbit
ECCMOS
24MB
4MB

256 Kbit
ECCMOS
80MB
20MB

Cache Size

8KB

64KB

Cache Access Tune

200ns

8200: 8KB
8300: 8KBx2
200ns

110 Max. Throughput

3_3 MB/s

13_3 MB/s

13MB/s

16MB/s

45 ns

8600: 80ns
8650: 55 ns
8600: 20 MB/s
8650: 26 MB/s

~~:i!;::.-

~
~

c·

.;r
'~"'
~

8700: 64KB
8800: 64 KB x 2
45 ns
>30MB/s

PROCESSOR OPTIONS
Floating-point Accelerator
Data Types Supported
Extended Range
Floating-point--G, H
Writable Control Store (WCS)
WCSSize

Standard
F,D,G
Standard-G

Optional
F,D
Optional

Standard
F,D,G
Standard

Standard
F,D,G,H
Standard

Optional
F,D,G,H
Standard

Standard
F,D,G,H
Standard

NA
NA

Optional
2 Kword

NA
NA

Standard
16 Kword

Standard
8 Kword

WCS Wlrd Size

99 bits

144 bits

86 bits

Standard
8700: 16 Kword
8800: 1 Kwordx2
144 bits

CONFIGURATION
VAXcluster Support
HSC50/HSC70 Support
VOBuses

NA
NA
1 Q-Bus

Optional
Up to 15
1 SBI 4 UNIBUS 4
MASSBUS

Optional
Up to 15
1 VAXBI 1
UNIBUS

Optional
Up to 15
2 VAXBI 1
UNIBUS

Standard
Up to 15
4 VAXBI
2 UNIBUS

Ethernet Support

Optional

Standard

Optional
Up to 15
2 SBI 7
UNIBUS 4
MASSBUS
Standard

UPGRADE OPTION

None

8200: to 8300
8300: none

8500: to 8550
8550: none

8600: to 8650
8650: none

8700: to 8800
8800: none

Standard

*For multistream applications

.....

1-4 • Overview: Digital's Second-generation VAX Systems

• New Top-of-the-line Systems
The top-of-the-line VAX 8800, Digital's highest performance system, delivers
9 to 12 times the power of the standard VAX-11/780 system for both computeintensive and interactive/multiuser environments.
Applications such as simulation, analysis, design, and complex modeling run
extremely well on the VAX 8800. Similarly, users with the broad mix of applications found in the finance, service industries, manufacturing, education, and
business also benefit from the performance of the VAX 8800.
The VAX 8800 design has been optimized for multiprocessing and includes up
to 128 Mbytes of fully sharable ECC memory, two 64 Kbyte caches, very high
bus bandwidths, and an intelligent console subsystem. The VAX 8800 uses
Digital's new VAXBI bus architecture as its I/O bus system. With expansion to
four VAXBI channels and greater than 50 Mbytes/s CPU/Memory bandwidth,
the VAX 8800 sets new standards for flexibility and performance.
The VAX 8700 is an expandable uniprocessor system that provides future
growth to the larger VAX 8800 multiprocessor. A single VAX 8700 CPU has all
the design attributes of the larger VAX 8800 processor and provides about onehalf the performance. Both the VAX 8700 and the VAX 8800 can access up to
four VAXBI channels and up to 128 Mbytes of memory.

• Power in Compact Packages
The other computers discussed in this volume - the VAX 8650, the VAX 8550
and VAX 8500, plus the VAX 8200 and VAX 8300 - deliver large-system functions with midrange pricing and packaging.
The VAX 8650 CPU provides up to six times the performance of the VAX-111
780. Like the VAX 8600 (described in Volume 1), the VAX 8650 is a high-performance, general purpose VAX system designed for use in traditional data
processing applications. The VAX 8650 computer uses advanced internal
processor structures to overlap processing of multiple instructions. Its interconnect structure allows the choice of CI, UNIBUS, or MASSBUS adapter products.
The VAX 8500 and VAX 8550 are excellent choices for applications where cost
per user is paramount, and where high performance is required in limited
space. The VAX 8500's performance is three times that of the standard VAX-111
780, while the VAX 8550 delivers up to six times the performance of the VAX11/780. Housed in compact packages that occupy only 5.6 square feet of floor
space, VAX 8500/VAX 8550 systems address all technical and commercial
applications.

1-5

The VAX 8200 brings full VAX functionality and the performance of the
VAX-ll/780 in one-fourth the footprint. The VAX 8300 has up to 1.9 times the
power of the VAX 8200 and like the VAX 8800, it provides improved price!
performance in many multistream applications such as in engineering, laboratory, realtime, and interactive multiuser environments. The VAX 8200NAX
8300's 24 Mbytes (maximum) of main memory and low price make these systems the first choice for general purpose applications in office, manufacturing,
commercial, and scientific applications. The VAX 8200NAX 8300 complement
the MicroVAX II wherever applications call for large system functions, such as
VAXcluster support, large memory capacity, high system 1/0 performance, wide
selection of peripherals, and broad configuration flexibility.

• VAXBI Bus - For the New Generation of VAX Systems
The VAX Bus Interconnect (VAXBI) is the new 32-bit synchronous bus for
Digital's new generation of midrange and high-end VAX systems. Designed for
high performance and high reliability, the VAXBI bus serves as the I/O bus for
the VAX 8800, VAX 8700, VAX 8500, and VAX 8550 systems; and both the system and 110 bus for the VAX 8200 and VAX 8300 systems.
The VAXBI is a clocked synchronous bus with a 200-nanosecond cycle time. It
supports 30-bit physical addressing, multiple processors, and up to 16 total
nodes. A standard one-chip interface implements all bus protocols. This VAXBI
interface incorporates into a single chip the contents of 2.5 printed circuit board
assemblies - considerably reducing the power requirements, size, and cost of
the second-generation computer systems.
With an increased aggregate throughput, the VAXBI bus provides substantial
gains in communication speed within the system, while simplifying design
efforts for developers of peripheral devices and for OEMs who incorporate the
new VAX computers into their products. Destined to dramatically change the
way computer interfaces are designed and used, the VAXBI reduces product
development cycles and cuts design costs.
To protect customers' investments in existing equipment, Digital also offers a
VAXBI-compatible UNIBUS adapter. This adapter makes it possible to continue
using many standard and specialized peripherals currently supported by
UNIBUS-based VAX computers.

• VAXcluster Configurations Increase VAX System Capacity
From the VAX 8800 to the VAX 8200, all Digital's high-end and midrange VAX
computers can serve as part of a VAXcluster System.

1-6 • Overoiew: Digital's Second-generation VAX Systems

VAXclusters link the computers and one or more shared mass-storage subsystems to form Digital's highest-capacity VAXcluster Systems. A VAXcluster port
is standard on the VAX 8800 and is optional on all other systems. An Ethernet
port for connecting to local area networks is included in all base configurations.
VAXclusters with multiple VAX 8800 computers and storage subsystems provide mainframe computing power and capacity. VAXcluster Systems can be created with more than 100 times the power of a VAX-ll/780 system and more
than 100 Gbytes of storage. And all of this power and capacity is available to
every user.

• Features Common to All VAX Processors Systems
Processor Specific Features - All VAX processors implement the 32-bit VAX
architecture, an extensive instruction set with numerous data types, and a 32-bit
bus structure for high data throughput. This is coupled with a virtual address
space of up to 4 Gbytes (2 Gbytes user accessible), sixteen 32-bit general purpose registers, twelve addressing modes, and thirty-two interrupt levels that
together provide a versatile and efficient processor system.

Console Subsystem - All VAX systems employ a microprocessor-based console
subsystem that allows the user, system manager, or service engineers to communicate with the system through the console terminal.
In console mode, the processor can be started or halted, self-tested, initialized
to a known state, and single-stepped through instructions. Information in memory, storage locations, and internal registers can be examined and data can be
deposited into these locations. Diagnostic maintenance and bootstrap programs can be loaded from the console load device and controlled by the console
terminal.
When the remote diagnostic service is included as part of a Digital Field Service
contract, the diagnostic testing can also be controlled through the console subsystem from a remote Digital test facility.

VMS Operating System - VAX system hardware is complemented by the VMS
operating system, which is continually being -enhanced to provide more capabilities and more efficient system operation. VMS is a powerful multiprogramming operating system capable of supportirig many users in realtime, interactive
timesharing, and multistream batch applications. It also provides support for
online program development.

1-7

VAXELN Realtime Software Toolkit - For applications requiring realtime code
development, the VAXELN Toolkit provides the resources. A VMS layered
product, the VAXELN Toolkit generates tight execution code for a dedicated
realtime processor on which the VAXELN kernel controls the use of shared system resources. At the same time, running on a VAX or MicroVAX system, the
VAXELN Toolkit gives access to the rich software development resources of the
VMS environment. Refer to your Digital sales representative for availability.
ULTRIX-32 Operating System Option - The UL1RIX-32 operating system has
been added to the VAX system family to provide users with a commoditysoftware base for 32-bit systems. The UL1RIX-32 system is Digital's enhanced
native-mode UNIX operating system. It offers the standard set of UNIX languages and utilities. Check with your local Digital sales representative for
availability.
VAXcluster System Configurations - The VAXcluster architecture enables up to
16 VAX processors or HSC50/HSC70 intelligent mass-storage servers to be connected together through the SC008 Star Coupler unit to form a single highperformance system. Through the VAXcluster, the processing power of many
VAX processors becomes available and each processor is allowed access to a
common data file.
The HSC50 and HSC70 intelligent-mass storage va servers optimizes the system data throughput by controlling the operation of disk drives or tape drives
and formatters. The SCOO8 Star Coupler unit forms the common connection
point for the cables from the processors and intelligent servers.
By providing common access to data files, the cost of development software and
support of multiple databases when a system is expanded is significantly
reduced. When more processing power is required, the VAX system selected
can be tailored to the new system requirements without adding unnecessary
hardware or software.

Communication Capabilities - The full capabilities of the VAX hardware and
software are further enhanced by the Digital Network Architecture (DNA).
DNA enables communication between VAX systems and other Digital systems
and between Digital systems and systems developed by other manufacturers.
Digital offers extensive capabilities that permit the linking of computers and
terminals into flexible network configurations to increase the efficiency and
cost-effectiveness of data processing operations. DECconnect is the integrated
communications solution that brings ThinWrre Ethernet and other communication options to the office. And Ethernet is Digital's high-speed local area communications network that enables computer systems and terminals, whether
located centrally or at remote sites, to exchange information and to share
resources.

1-8 • Overview: Digital's Second-generation VAX Systems

Digital Storage Architecture (DSA) - DSA is Digital's framework of standardized interfaces that permits the addition of new products and technologies that
operate with different host systems without the need to develop new controllers
and device drivers. DSA allows an expanding group of mass-storage products,
including disk and magnetic tape drives, to be implemented into an intelligent
mass-storage subsystem that provides a high standard of data integrity, fast data
throughput, and many reliability features.
The following sections describe the new VAX systems and indicate the configurations available for each. Block diagrams of the system hardware are located in
the processor chapters.

• VAX 8800 High-performance System
Digital's VAX 8800 computer system is the highest performance member of the
VAX family of computers. These high -performance systems implement the VAX
architecture, continuing complete software compatibility with all other VAX
systems. VAX 8800 systems are tightly coupled multiprocessing systems comprising two CPUs that share up to 128 Mbytes of memory.
The VAX 8800 CPU features virtual memory management, bootstrap loader,
standard instructions for packed decimal, floating (D, F, G, and H data types)
and fixed-point arithmetic, character, and string manipulations, two 64-Kbyte
direct-mapped write-through cache memories, high-precision programmable
realtime clock, time-of-year clock with battery backup, and two 16-Kword
(144-bit words) writable control stores. The CPU also includes the memory
controller and memory battery backup for a full 128 Mbytes of memory capacity. Standard with all VAX 8800s is a VAXcluster port, Ethernet port, and two
VAXBI channels. The CPU also includes a console subsystem based upon a J-11
chip set with videoterminal, 30-Mbyte Wmchester disk, RX50 floppy disk, and
remote diagnostic port.
VAX 8800 systems are available with a VMS operating system that provides a
reliable, high-performance environment for the concurrent execution of multiuser timesharing, batch, and realtime applications.
The following VAX 8800 System Building Block configurations are available:
• VAXcluster System Building Blocks
• VMS System Building Blocks

1-9

• VAX 8700 System
The VAX 8700 and VAX 8800 are similar systems_ The VAX 8700 System can be
transformed to a VAX 8800 by adding an upgrade kit. See Figure 1-2 _The major
difference between the two systems is- that the VAX 8700 contains one processor
and the VAX 8800 contains two. Also, the VAX 8700 contains one VAXBI 110
bus (with eleven usable slots) as a standard feature while the VAX 8800 has two
(with five usable slots each) .

• VAX 8650 System
The VAX 8650 computer system is a UNIBUS-based high-performance member
of the VAX family. It is functionally identical to the 8600 but offers 44 percent
more performance.
The VAX 8650's central processor uses 32-bit architecture with 4 Gbytes of virtual addressing space. It features virtual memory management, bootstrap
loader, standard instructions for packed decimal, floating (D, F, G, and H data
types) and fixed-point arithmetic, character and string manipulations, 16-Kbyte
write back cache memory, high-precision programmable realtime clock, timeof-year clock with battery backup, and 8 Kwords (86-bit words) of writable
control store. The CPU also includes the memory controller and battery backup
for 68 Mbytes of memory.
Standard with the VAX 8650 is a DF112 modem for remote diagnosis. The CPU
also includes a console subsystem with an RL02 disk drive, DCTll microcomputer, console terminal, and remote diagnostic port. (The console terminal is
not included. It must be selected from the menu_)
VAX 8650 systems can be ordered with the VMS or ULTRIX-32 operating
system. VMS provides a reliable, high-performance environment for the concurrent execution of multiuser timesharing, batch, and realtime applications.
The ULTRIX-32 operating system is a reliable, demand-paged, virtual-memory,
timesharing native UNIX operating system.
The following VAX 8650 System Building Block configurations are available:
• VAXcluster System Building Blocks
• VMS System Building Blocks
• ULTRIX-32 System Building Blocks

1-10 • Overoiew: Digital's Second-generation VAX Systems

• VAX 8550 and VAX 8500 Systems
Digital's VAX 8500 and VAX 8550 computer systems are gateways to Digital's
high-end VAXBI systems. These high-performance systems implement the VAX
architecture, .continuing complete software compatibility with all other VAX
systems. The control processor uses 32-bit architecture with 4 Gbytes of virtual
addressing space.
The VAX 8500NAX 8550 CPUs feature virtual memory management, bootstrap
loader, standard instructions for packed decimal, floating (D, F, G, and H data
types) and fixed-point arithmetic, character and string manipulations, a
64-Kbyte direct-mapped write-through cache memory, high-precision
programmable realtime clock, time-of-year clock with battery backup, and a
16-K word (144-bit words) writable control store. The CPU also includes the
memory controller for 80 Mbytes of memory capacity. Standard with all systems is an Ethernet port, and one VAXBI channel. The CPU also includes a console subsystem based upon a J-11 chip set with videoterminal, 30-Mbyte
Wmchester disk, RX50 floppy disk, and remote diagnostic port.
VAX 8500 and VAX 8550 systems can be ordered with a VMS operating system.
VMS provides a reliable, high-performance environment for the concurrent
execution of multiuser timesharing, batch, and realtime applications.
The following VAX 8500 and VAX 8550 System Building Block configurations
are available:
• Preconfigured System Building Blocks
• VAXcluster System Building Blocks
• VMS System Building Blocks

• VAX 8200 and VAX 8300 Systems
Digital's VAX 8200 and VAX 8300 computer systems are midrange members of
the VAX family of computers that use the VAXBI as both a system and 110 bus.
These high-performance systems implement the VAX family architecture, making them software compatible with other VAX systems. The VAX 8200 is a single-processor system. VAX 8300 systems are tightly coupled multiprocessors,
consisting of two VAX 8200 CPUs accessing up to 24 Mbytes of shared memory.
The central processors use 32-bit architecture with 4 Gbytes of virtual addressing space.

1-11

Both the VAX 8200 and VAX 8300 CPUs feature virtual memory management,
bootstrap loader, standard instructions for packed decimal, floating (D, F, G,
and H data types) and fixed-point arithmetic, character and string manipulations, two 8-Kbyte for the VAX 8300 and 8-Kbyte for the VAX 8200 directmapped write-through cache memories, programmable realtime clock, and
time-of-year clock with battery backup_ The CPU also includes a console subsystem with an RX50 floppy disk.
Systems can be ordered with a VMS operating system_ VMS provides a reliable,
high-performance environment for the concurrent execution of multiuser
timesharing, batch, and realtime applications_
The following VAX 8300 and VAX 8200 System Building Blocks are available:
• Preconfigured System Building Blocks
• VAXcluster System Building Blocks
• VMS System Building Blocks
• ULTRIX-32 System Building Blocks (VAX 8200)

• Mass-storage Extensions
Mass-storage extensions are based on the Digital Storage Architecture (DSA), a
carefully designed framework that provides the advantages of easy, incremental
system growth, fine-tuned 1/0 performance, high data integrity, and file
compatibility. DSA eliminates the need for the VMS operating system to support
every unique storage device with its own driver. To optimize disk operation, the
operating system communicates with an intelligent disk controller using Digital's standard Mass Storage Control Protocol (MSCP) to optimize disk operation. The controller can support several devices. When you want to add more
storage, you simply plug in an additional device.

KDB50 Single-host Disk Controller
The KDB50 is a high-performance microprocessor-based VAXBI disk controller
that has been designed for fast, reliable, and optimum RA-disk throughput on
the new VAXBI systems.
Providing a usable, sustained transfer rate of over 1 Mbyte/s, the KDB50 connects up to four RA-series SDI disks to the VAXBI bus. Each RA-series disk drive
ranges in capacity from 121 Mbytes to 456 Mbytes for a total capacity of over
2.8 Gbytes per KDB50.
The KDB50 connects directly to the VAXBI, providing the fast burst data rates
(up to 3 Mbytes per second) needed to support high-throughput requirements.
With improved 1/0 performance, VAXBI systems can respond to requests more
quickly and move on to the next task. The result is better overall systems performance, higher user satisfaction, and improved CPU utilization.

1~ 12 • Overview. Digztal's Second~generation VAX Systems

HSC70 High-performance Mass-storage Server
The newest member of the HSC family of intelligent storage servers, the HSC70
enhances HSC50 performance with greater drive connectivity, I/O command
handling performance, operational convenience, and reliability.
The HSC70 server offloads all disk management functions from the host sys~
terns and provides host ~ independent sharing of common data among a network
of locally connected VAX~ 111750 and larger processors. It connects both disk
and tape drives to all of the host computers in the VAXcluster and supports a
combination of eight disk and tape data channels. Each disk data channel sup~
ports four drives over the standard disk interface (SDI). Each tape data channel
supports four tape formatters over the standard tape interface (STI) and,
depending upon which formatter is used, from one to four tape transports can
be supported by each formatter.
The HSC70 connects to one or more host computers by means of the 70 Mbit~
per~second dual~path computer interconnect (CI) bus. The CI can accommo~
date up to 16 nodes or connected devices. Therefore, a single microprocessor~
controlled HSC70 server can provide storage services for as many as 15 VAX
host computers and as many as 32 mass~storage devices.

TA81 Magnetic Jape Subsystem
Midrange in price and performance, the TA81 conforms to the ANSI standard
for Group Code Recording (6,250 bits per inch) and for phase encoded (PE)
recording (1,600 bits per inch) on half~inch, nine~track tape. Read~after~write
verification ensures that each bit written is verified immediately after it is
recorded. Vertical parity is checked, character~by~character, when reading and
writing. The TA81 uses error correction code (ECC) and cyclic redundancy
check (CRC) when in group code recording (GCR) mode to make both single~
and double~track error correction without CPU intervention.
rU81-Plus Magnetic Jape Subsystem
The TU81~plus can store up to 140 Mbytes on a standard 8~Kbyte, 2,400~foot
reel. It is the only native~mode industry~cQmpatible tape drive offered for
Digital's new VAXBI systems in stand~alone configuration. A 256~Kbyte cache
buffer significantly improves tape streaming performance on most VAX
systems.
With streaming tape technology and high-speed operation via prefetching of
commands and data, the TU81~plus is ideal for applications involving sustained
tape input such as disk backup, data archiving, or recording data from high~
speed test equipment. It also uses traditional start/stop technology for shorter
data transfers of the type associated with journaling, transaction processing, and
classical data processing.

1-13

• Main Memory Extensions
Main memory for VAX 8200 and VAX 8300 Systems is available in 2-megabyte
and 4-megabyte boards to provide easy, cost-effective memory expansion. Each
of these boards implements an advanced, highly intelligent design that encompasses data, address, error correcting code, and control logic.
Main memory for the VAX 8500/8550/8700/8800 systems is available in two
types of memory boards. One type is a 4-megabyte board; the other is a
16-megabyte board that uses double-sided, surface-mount technology to provide larger memory per size of cpu. The MS86 memory board applies to the
VAX 8650 and the MS88 for the VAX 8700/8800 systems. Refer to Table 1-1 for a
listing of the maximum capacity of each of the processors discussed. Detailed
description of the memory extensions are contained in each processor chapter.

• How to Order VAX Systems and VAXcluster Systems
The desired hardware configurations of the standard VAX systems and VAXcluster Systems are obtained by using the system building block menus contained in the current version of the VAX Systems and Options Catalog. The
menus allow the user to select a basic system consisting of a VAX cpu, main
memory, and software operating system license, and to add the required interfaces and devices. From the system menu, the user can select the system storage
and load devices, communication interfaces, console terminals and operating
system documentation, and software media. Using the system building blocks,
VAX systems and VAXcluster configurations can be selected for specific applications without the purchase of unneeded hardware and software. The VAX
Systems and Option Catalog can be obtained at any Digital sales office or from a
Digital sales representative.

The VAX 8800 and VAX 8700 Processor Systems are the highest performance
VAX Systems offered by Digital Equipment Corporation. These systems are
general purpose, scalar computers suitable for nearly all computing environments. Their very high processor data rates coupled with the VAXBI input/output subsystem provide the highest VAX performance available in nearly all
environments. The VAX 8700 can be readily upgraded to a VAX 8800.
The VAX 8800 and 8700 offer the same degree of software compatibility found
in other members of the VAX product family. In these processors, a new highspeed internal bus plus integral highly accelerated floating-point operations
contribute to overall performance. Both systems incorporate a new generation
of input/output architecture-the VAX Bus Interconnect (VAXBI). The VAXBI
bus provides the high-performance 110 subsystem. The VAXBI bus incorporates extensive reliability and data integrity features such as bus parity, transmit
checking, and receive acknowledge, implemented in VLSI interface circuitry.
Currently, the VAX 8800 offers the highest multistream throughput of any VAX
and is faster than any competitive system in its price range. Running multiple
applications, the VAX 8800 provides ten to twelve times the performance of the
VAX-lln80, while the VAX 8700 provides six times that of a VAX-lln80.
Much of the performance is the product of sophisticated, custom, solid-state
components, and high-speed bus architectures. The performance characteristics and data for both processors are listed in Appendix A. Some attributes of
these systems are:
• Highest-performance VAX systems ever offered.
• Fastest VAX 110 throughput, delivering balanced CPU and 110 performance
in all applications.
• Ten to twelve times the performance of the VAX-unBO in the same 15.5
square feet of floorspace.
• Cost-effective incremental growth with VAXcluster configurations.
• Incremental CPU, 110, and memory growth.

2-2 • VAX 8800 and 8700 Processor Systems

Figure 2-1 • VAX 8800 Processor Unit

• VAX 8800 and VAX 8700 Physical Configuration
VAX 8800 and VAX 8700 processor subsystems occupy the same space as the
VAX-lln80 or VAX 8650 processor - 15.5 square feet of floor space. The
environmental requirements are the same as those of earlier VAX models so that
there is no need to renovate your computer room. Both processors are aircooled. The clean internal design and airflow patterns contribute to their
noticeably low noise level.

2-3

The VAX 8800 and VAX 8700 processors are housed in an H9650 cabinet. The
cabinet contains the power system, the cooling system, backplane (module card
cage), and input/output bulkhead. A front-end cabinet houses the power sysl
tern input transformer and battery backup unit. Expansion cabinets are available to house more VAXBI buses extending the VAX 8800/8700 Systems
support to four VAXBI channels with up to two optional UNIBUS channels. Figure 2 -2 shows the cabinet and locations of the components in the cabinet. Physical dimensions of the processors are listed in Appendix A.

BLOWER

•

TS3

,-T-T-T-T-T-T-TsT-T-,

I MOD I MOD I MOD I MOO I
I MOD I MOD I P I MOD II MOD I
I H I f I , I , I 'MM I 0 I 0 I A I C
• I
I
I
I
I
I
I
I
I
I
I R I
f--_.1._.1._.1. _
J. _.1. _J..~ 1- _ J. _~
1
MPS BACKPLANE NO.1

V~., .,

,
MP5 BACKPLANE NO.2

S C
. P l
I A
0
A R C

PROCESSOR

PROC'SSORIM'MORYI

•

TS1
I/O BULKHEAD

[

N.OX

LEGEND

= TEMPERATURE SENSOR
AFS = AIR FLOW SENSOR
TS

EMM"'ENVIRONMENTAL MONITORING
MODULE

Figure 2-2 • VAX 8800 Processor Configuration
System Expansion Cabinets
The H9652-ECIED cabinet, shown in Figure 2 -3, provides space for any combination of up to two BA32-BNBB VAXBI expansion boxes or BAll-AW/AX
UNIBUS expansion boxes. The cabinet includes 37 panel units.

2-4 • VAX 8800 and 8700 Processor Systems

I/O
Connection -

Panel

f--

2·Inch Blank
Panel Insert

Space for
BAII-AorBA32-B

I/O
Connection

- c--

Panel

Space (or

BAll-Aor BA32-B

I/O
Connection

Panel

-V
.&

VAX 8800 Expansion Cabinet
H9652·EC(ED)

Figure 2-3 • H9652-Ec/ED VAXBI and UNIBUS Expansion Cabinet

• VAX 8800 and VAX 8700 Processor Organization
The VAX 8700, shown in Figure 2-4, has one processor. The VAX 8800, shown
in Figure 2-5, has two processors. The VAX 8800 and VAX 8700 processors
share common implementations and functions. In the following descriptions,
unless a difference is identified, the implementation is identical for .both
processors.
A single console subsystem controls either the VAX 8800 or the VAX 8700.

2-5

r---"---l

~ BUS INTERFACE ~

I
I

I (OPTIONAL) I
L _____ J

r--.l.--l

r--..L--..,

r--..L---,

VAXBI

I/O BUS

(OPTIONAL)

I
I
I

L __

__ J

1
I
I

(OPTIONAL)

4,.- "r'"

VAXBI
I/O BUS
(OPTIONAL)

: 4:

":,,./~.,

'"V/

"r'

: 3:

L,.

I
I
I

L ____ --..J

- ::,'~'~, -

: 2[
....J

VAXBI

VA BUS

"'~,..,,~1

Figure 2-4 • VAX 8700 System Configuration

r---"---l
I
BUS
I

i1
I

INTERFACE
L _____ ..l

,-_-1._--,
I

I
I

VAXBI
I/O BUS
(OPTIONAL)

r---1.---,

I
I

VAXBI

vA BUS
(OPTIONAL)

-:-_..J

L_~~,~_-.I

L_-:,~...

", r1o.
:3 t

.. ,

"~'v,~,.

I
I

rio

: 4:
,<~"./~,.

Figure 2-5 • VAX 8800 System Configuration

Console Subsystem
The console subsystem controls the initialization and general operation of the
VAX 8800 and VAX 8700 Computer Systems. The VAX Hardware Handbook
Volume 1 contains information that is basic to all VAX Console Subsystems.
Please refer to that handbook for general information on VAX console subsystems. See Figure 2-6 for a block diagram of the VAX 8800 and VAX 8700 Console Subsystems.

2-6 • VAX 8800 and 8700 Processor Systems

--L-----;-----L------,- SERIAL

IPROGRAMMABLE

~I:I~

I ~~~~:F~~~l

__ L__

-:l
I
I
I
I
I

----'

Figure 2-6 • Console Subsystem Block Diagram
• CONSOLE PROCESSOR
The console processor consists of a J-11 chip-based CPU with a Wmchester disk
and two diskette drives. Communication between the console processor and
the CPUs is done by transferring data to and from the console interface on the
clock module. The console processor contains an I/O option called the Realtime Inter/ace (RTI). The RTI provides the physical communications path
between the console and the console interface. The RTI provides the console
device processor with several I/O ports including a programmable peripheral
interface (PPI) and two serial-line units (SLU).
The programmable peripheral interface (PPI) contains three 8-bit ports for
transferring data, address, and control signals between the console and its interface. One of the SLUs is connected to the environmental monitoring module
(EMM) in the power supply subsystem. TheSLU connects the console processor with the EMM giving the console processor the ability to monitor and control the electrical power and environmental parameters of the processor system.
• CONSOLE SUBSYSTEM OPTIONS
Two options are available for the console subsystem - a printer and a remote
diagnostic link. The console processor contains a serial printer port. The
remote diagnostic link is a service offered by Digital that permits a 15-minute
response by qualified Digital service personnel and allows for remote fault isolation. Contact Digital Field Service for details.

2-7

• CONSOLE COMMAND LANGUAGE
The VAX 8800 and VAX 8700 Console Subsystem uses a superset of the Console
Command Language_ The VAX Hardware Handbook Volume 1 contains details
of the console command language. Other sources of information on the language are the VAX 8800/8700/8550/8500 Console User's Guide and the VAX

8800/8700 System Hardware User's Guide.

• Central Processing Unit
The VAX 8800 and VAX 8700 processors are logically divided into functional
boxes that receive power from a power subsystem. The division is logical, not
physical: that is, there are no physical barriers such as partitions. Standard Field
Service procedures have been developed specifically for these systems.
Each processor consists of three functional units and related buses. The functional units are the instruction (I) box, the execution (E) box, and the cache (C)
box. There are five buses in the processor - the cache!ALU bypass bus, the
cache data bus, the instruction buffer data bus, the virtual address bus, and the
write data bus. Figure 2-7 shows a block diagram of the VAX 8800 and VAX
8700 processor configuration.

BOX

LEGEND
C/A-B BUS= CACHE!ALU BYPASS BUS
IBD BUS= INSTRUCTION BUFFER DATA BUS
VA BUS = VIRTUAL ADDRESS BUS
WD BUS
WRITE DATA BUS

Figure 2-7 • VAX 8800 and VAX 8700 Processor Block Diagram

2-8 • VAX 8800 and 8700 Processor Systems

Instruction Box
The instruction (I) box is the microcode store and control center. It contains the
writable control store (WCS), the decoder module, and the microsequencer
module. The !box
• Buffers the prefetched VAX instruction stream data received from the cache
box.
• Decodes and controls microinstruction execution.
• Monitors and services microtraps, interrupts, and exceptions.
• Supplies instruction stream embedded data.
• Provides an interface between the console module and the rest of the
processor.

As shown in Figure 2-8, the !box contains:
• An instruction buffer.
• An instruction decoder.
• A microsequencer.
• A writable control store.
• Condition code and microbranch logic.
• Interrupt and processor register logic.
• File address generator.
• Console gateway control.

CACHE DATA BUSJ'---r----ci"

CONTROL

INTERRUPT PENDING

Figure 2-8 • Instruction Box Block Diagram

2-9

• INS1RUCTION BUFFER
The instruction buffer is a 4-longword, shott-term memory device. It receives
instruction stream data from the cache box and loads the received data into the
specified write address. The buffer read/write operations are controlled by the
instruction buffer manager. The buffer outputs the opcode byte, the current
operand specifier, the general processor register number of the current specifier, and the specifier extension bytes.

• INS1RUCTION DECODER
The instruction decoder consists of a 4K by 17-bit writable random access
memory and a special address encoder. The address encoder is composed of
discrete priority encoders and multiplexers. The dynamic RAMs perform three
major functions.
• They supply the microsequencer with part of the entry point address for
opcode and specifier microroutines.
• They assist the instruction buffer manager in controlling the instruction
buffer.
• They indicate which memory data register in the Ebox is to receive the data
from memory for those specifiers requesting data.

• MICROSEQUENCER
The microsequencer determines which one of several sources will supply the
address of the next microword to be executed. The 14-bit-wide address is
stored in micro-PC latches and is presented to the control store. lbssible
sources of the next microword to be executed include the following:
• Next microaddress field possibly modified by branches.
• Decoder entry point microaddress.
• Execution or Cbox microtrap vector.
• Machine check microtrap vector.
• napped micro-PC from a micro-PC silo.
• Microsubroutine return address from a microstack.
• Console-supplied address.

• CON1ROL SlORE
The microcode control store is a storage area of 16K by 144 bits and resides on a
set of 16K by I-bit writable RAMs. The RAMs are loaded during system initialization from the console subsystem by way of the gateway controller. Approximately 15 Kbits are used for processor control while approximately 1 Kbit is
available for user-written code.

2-10 • VAX 8800 and 8700 Processor Systems

• CONDmON CODE AND MACROBRANCH LOGIC
The condition code and macrobranch logic maintains the processor status
word's condition code bits and seven processor state bits. Raw condition codes
from various Ebox operations are used in the generation of microbranch conditions based on the raw condition codes and the size of the data being processed.
These conditions are tested by the microsequencer's microbranch logic. The
raw condition codes can also be compared to the current condition code bits to
effect a macrobranch instruction or be stored as the new processor status
longword condition code bits.
The processor state bits are microprogramming aids that provide firmware
writers with a method of controlling microcode flow. The bits can be set or
cleared in a microroutine. Then the bits may be tested as conditions in later
routines.

• INTERRUPT AND PROCESSOR LOGIC
The interrupt and processor logic contains the priority interrupt hardware and
the four internal processor registers. The interrupt portion of the logic monitors
all hardware interrupts, encodes the level of the highest pending request, and
compares it with the current priority leveL If the encoded level is higher than
the current level, the interrupt logic requests an interrupt. Interrupts are
requested by asserting an interrupt pending signal.
The internal processor registers control and supply data to the interrupt logic,
rnicrosequencer, and the memory management in the cache box.

• FILE ADDRESS GENERAlDR
The file address generator performs the following three functions:
• It supplies addressing for the Ebox's register and slow data file.
• It stores general register numbers that are referenced by operand specifiers.
• It records changes made to the general registers in autoincrement and
autodecrement operations .

• GATEWAY CONTROL
The gateway control logic controls the data paths between the processor and
the console interface. It controls the loading of the control store RAMs and
rnicromatch register, and the loading of the decoder and cache control RAMs.

2-11

Cache Box
The cache box includes a 64-Kbyte physical indexed, direct mapped, and
write-through cache memory. The cache box speeds address translations and
provides a communication path for the processor to the memory interconnect
bus. The cache box consists of a translation buffer, 64-Kbyte data store, and a
memory interconnect interface. Figure 2-9 contains a block diagram of a cache
box.

• FROM EXECUTION BOX

t FROM INSTRUCTION BOX

Figure 2-9· Cache Box Block Diagram
• TRANSLATION BUFFER
The translation buffer is a 1 Kbyte cache of virtual to physical address translations. The buffer consists of a tag store and data store. The buffer is organized
into 512 process translation slots and 512 system region translation slots.
The tag store uses a portion of the virtual addresses to access a RAM array and
compares the contents of the RAM with the remaining virtual address bits.
When the comparison results are equal and the translation buffer's valid bit is
set, the address is said to have hit and the contents of the data store are valid for
that address.
The data store uses a portion of the virtual address. If the tag store comparison
results in a translation buffer hit, the page frame number concatenated with
virtual address bits 0 through 8 is used as the physical address .
• DATA STORE CACHE
The data store cache is a hardware mechanism that provides fast access to frequently used data. The cache is addressed by a physical address. If required
read data is in the cache, that data is extracted and no memory request is
required. If the required read data is not in the cache, a memory request for that
data is initiated. The data from memory is passed to the requester and is also
placed in the cache for subsequent use.

2-12 • VAX 8800 and 8700 Processor Systems

• MEMORY INTERCONNECT INTERFACE
The memory interconnect interface provides the processor(s) with a communications path for control and data sigrtals. When a cache read request misses, the
interface uses tlie missed address to build a command!address transaction. The
transaction is sent to the memory subsystem. This procedure allows the translation buffer and the cache to be free to process other processor requests until the
requested data arrives from memory. When the requested data arrives, the
interface assumes control of the cache and loads the new data into the cache's
data store.

Execution Box
The execution (E) box receives data from the !box and the Cbox, processes the
data and returns the data to the Cbox. Figure 2-10 shows a block diagram of the
Ebox.

Figure 2-10· Execution Box Block Diagram

2-13

The Ebox
• R:rforms all processor-required arithmetic, logical, and bit-shift operations.
• Maintains the program counter and general registers.
• Maintains the processor registers.
• Controls data transfers between the Cbox, !box, and clock module registers.
• Provides condition code information to the instruction box microsequencer.
The Ebox consists of the following elements:
• A register file

• A data file
• Program counter logic
• Main arithmetic and logic unit
• Shifter
• Floating-point support logic
• Multiplier
The major elements of the Ebox are located on the data slice modules (SLCD
and SLC1) and the shifter module.

• REGISTER FILE
The register file consists of 32 high-speed 36-bit registers. The registers hold 32
bits of data and 4 parity bits. There are 15 general registers, 9 temporary registers, and 8 memory data registers. The temporary registers serve as microcode
scratchpad registers while the memory data registers store the data received
from the cache.
• DAThFILE
The file consists of 256 36-bit registers. The 36-bit registers contain 32 bits of
data and 4 parity bits. Data file registers consist of processor registers, data-path
constants, and diagnostic test patterns.

• PROGRAM COUNTER
The program counter maintains the VAX program counter, the program
counter incrementer, backup and trap program counters, and the virtual
address file register. The program counter components perform the following
functions.

2" 14 • VAX 8800 and 8700 Processor Systems

• The program counter incrementer updates the program counter by adding
an increment value equal to the size of the instruction stream data being
processed. The increment value is from 0 to 6 and is supplied by the program
counter increment generator in the Ibox.
• The backup program counter saves macroinstruction opcode addresses and
restores the program counter if the instruction causes a macro exception. Saving the opcode allows a SeMce routine to examine the opcode of a failing
instruction and SeMce the fault.
• The trap program counter maintains a history .of recent program counter
activity and provides microtrap SeMce routines with the active program
counter at the time a microtrap occurs.
• The virtual address file stores a copy of each virtual address sent to the cache.
This copy is used as a backup if the address causes a microtrap.

• ARITHMETIC AND LOGIC UNIT
The arithmetic and logic unit (ALU) is a 32-bit adder. It processes integer, floating-point, binary coded decimal data. The ALU performs addition and subtraction (carries propagated), and logical AND, OR, and Exclusive OR operations.
In addition, the ALU
• Multiplexes data received by the Data Slice Modules.
• Supplies memory and register data to the cache.
• Supplies virtual address to the cache translation buffer.
• Routes data to and from the shift module.
• Provides carry and condition codes to the instruction box.

• SHIFfER
The shifter provides additional macro cell array and arithmetic logic unit operators that perform shift/rotate and multiply/divide operations on integer or
floating-point data and manipulate the signed exponent of a floating datum.
The shifter handles data in all formats in integer, floating-point, and binarycoded decimal modes of operation.

• FLOATING-POINT SUPPORT
This system processes the sign and exponent fields of floating-point data.
Inclu:ded in the floating-point support logic are the shift count ALl), a priority
encoder, and an exponent ALU.

2-15

• MULTIPLIER
The multiplier is a 64-bit multiplier that enhances the speed of both integer and
floating-point multiplication. It contains an 8-bit-at-a-time multiplication
algorithm that generates 8 result bits per cycle, and a 1-bit-at-a-time division
algorithm that generates 1 quotient bit per cycle. It also produces or generates
the correct two's complement results for integer data.
Memory Box
The memory subsystem (M) box consists of a memory control logic module,
from one to eight memory array boards, and a memory array bus. See Figure
2-11 for a block diagram of the Mbox with one array board.
The fully sharable 256 Kbyte ECC memory subsystem is suitable for both single
and dual processors. Two types of memory array boards provide convenient
memory subsystem configuration and easy expansion to a full 128 Mbytes for
both the VAX 8800 and the VAX 8700 systems. The 4-Mbyte and 16-Mbyte
memory array boards provide easy memory subsystem configuration, expansion, maintenance, and service. The 16-megabyte memory array board uses
double-sided, surface-mount technology.

M'EiViORYCoNTROL -,

I
I

_---1

I-I

I
I

LARRAY~~ _ _ _ _ _ _ _ ~

Figure 2-11 • Memory Box Block Diagram

2-16 • VAX 8800 and 8700 Processor Systems

The memory control logic (MCL) module is located in the card cage. The
8-s10t backplane can hold eight4-megabyte memory array boards or eight
16-megabyte memory array boards. Early production (January to November, 1986) VAX 8800NAX 8700 processors may require field backplane
}upgrade to reach 128 Mbytes. See the Systems and Options Catalog for
ddails.
All VAX 8800 and V:AX 8700 memory and memory controllers are shared and
usable by system and user programs. Memory, processors, and the 110 subsystem occupy the same cabinet. The large memory provided in these VAX systems
accommodates large working sets, many processes, and reduces page faulting.
The memory controller optimizes memory reads and writes with three-way
interleaving, further allowing large blocks of data to move freely within the
machine. Running at nearly 60 Mbytes per second, the memory, interconnect
bus ensures that processor-to-memory traffic operates with a minimum of delay
or contention. Wait states are minimized and the system is nearly always doing
meaningful work. To further protect data, a battery-powered backup power
supply for the memory subsystem is a standard feature. It takes 10 minutes to
perform a minimum battery backup .

• MEMORY CONTROL LOGIC MODULE
The memory control logic (MCL) module provides control and a communications interface between the memory interconnect bus and the memory array
boards. The single MCL module can control up to eight array boards, and can
monitor operations on three arrays simultaneously.

• ARRAYBUS
The memory array bus, or array bus, performs the transfer of data between the
MCL module and the array boards at a data rate of 60 Mbytes a second. The
array bus carries board select, command/address signals, and data between the
MCL module and the memory arrays. There are separate data lines on the. array
bus for read data and write data.

• MEMORY ARRAYS
Two types of memory array boards are available, 4-Mbyte (MS88-AA) and
16-Mbyte (MS88-CA). The MS88-AA memory array board has 156 total
dynamic RAMs and 256K by 1 MOS RAMs. The MS88-CA memory array board
has 624 total dynamic RAMs (arranged in four banks of 156 dynamic RAMs) for
16 megabytes of data storage. Each dynamic RAM chip has an effective 512 by
512 matrix array providing 256K (262,144) one-bit locations and 4 megabytes
by 39 bits of storage. Dynamic RAMs are 150-nanosecond-access-time devices
packaged in plastic leadless chip carriers (PLCC).

2·17

To achieve the 16-megabyte density, 256K by 1 dynamic RAMS are double-side,
surface mounted on 33-inch-by-4.8-inch cards and connected to the L-series
logic card with 44 pin connectors. These double-sided memory cards are called
Standard Memory Units (SMUs). The MS88-CA array contains eight SMU cards.
Logic card components include emitter-coupled logic and fast transistor-totransistor logic devices. The MS88-CA is designed to mix with the MS88-AA
array in a VAX 8800 or VAX 8700 backplane in any desired combination.

• DATA PROTECTION
Data protection is provided in four areas - parity checking, error correction
code, error logging, and battery backup.

ERROR CORRECTION CODE (ECC) - The memory subsystem has 7 check
bits for every 32 data bits to provide single-bit error correction and full doublebit error detection. The memory error correction code (ECC) automatically corrects single-bit errors and detects double-bit memory errors. The code also
detects greater than double-bit errors if an even number of bits in error are
detected. The ECC provides protection from nonrepeating errors by automatically correcting data. Detections and corrections are noted in the error log as a
preventive maintenance aid.
ERROR LOGGING· An integral part of the VMS operating system, error logging software records information related to the state of the system at the time
of error. Error logging is useful for the efficient maintenance of hardware by
providing a repott that can help diagnose impending or persistent hardware
problems. Some of the errors that are detected and logged include memory
single· and double-bit errors, machine check traps for control store parity error,
and cache parity error.

BAITERY BACKUP MODE - The battery backup unit (BBU) supplies the
power system with dc power during an ac power failure, The BBU provides
power for the memory modules during shott -term power losses. Battery mode
is automatically entered when an interruption occurs in normal power. While in
battery mode, the object is to save data in the arrays until normal power is
restored. Consequently, only refresh cycles are allowed - command operations
(writes and reads) are inhibited. To reduce the power drain on the battery, normal refresh sequences are suspended and battery mode refreshes are executed.
Battery mode refreshes only the barest minimum of logic thereby making lower
power demands on the battery. When normal power returns, the battery mode
signals are removed and normal operation is resumed. The battery backup unit
is described later in this chapter.

2-18 • VAX 8800 and 8700 Processor Systems

Processor Buses
Seven buses are ill the processor subsystem. Two buses participate in controlling or connecting the processor components. The remaining buses are data
.
paths between the processor's components.

• MEMORY INTERCONNECT (MI) BUS
The high-speed memory interconnect (MI) bus is a synchronous backplane bus
that interconnects the major system components of the processor, memory controller, and liD adapters to provide a path that transfers data between the connected units. The MI bus supports the following functions:
• Memory read/write operations (allows the processors and liD adapters to
access memory through bus read/write transactions).

> Write transactions support longword, masked quadword, and octaword
writes).

> Read transactions support longword, octaword, and hexword reads.
• liD space read/write operations (allows the processors to access memory
controller, liD adapters, and BI liD device registers through bus read/write
transactions.
• Interrupt handling (transmits interrupt requests generated by the memory
controller and liD adapters to both processors).
• System initialization (allows the console to initialize all adapters connected to
theMIbus).
• Ibwerfail warning (provides alternating current low (ACLO) and direct current low (DCLO) signals to all devices connected to the MI bus).

• VISIBILl1Y BUS
The visibility bus (V bus) is a slow-speed data bus that allows the console subsystem to access internally latched data in the CPU modules. The V bus has
sixteen data lines and two control lines. The console operator can read internally latched data in the processor's modules during the execution of
microdiagnostics and during system initialization. The V bus can be used only
when the system clocks are stopped. The V bus
• Monitors the state of the CPU(s) during microdiagnostic execution or in
response to commands entered at the console during system debug
procedures.
• Verifies CPU module installation and revision during system initialization.
• Detects write control store parity errors when loading microcode during system initialization.

2-19

Two registers (V bus control and V bus access) located in the clock module
console interface allow the console subsystem to control and read the V bus.
These registers
• Select the V bus input channel.
• Step the clocks that operate the V bus.
• Send serial V bus addresses to the CPU modules.
• Halt the operarion of the V bus address shift register.
• Allow the console to read data from the V bus .
• DATA-PATH BUSES
There are five data-path buses in VAX 8800 and VAX 8700 processors. All five
buses provide a data path between the components within the processor. The
buses are identified in the following list.

• ALU bypass bus that carries bypass register data scheduled to be written.
• Cache data bus that provides a data path from the cache subsystem to the
execution subsystem and instruction parser.
• Instruction buffer data bus that provides a data path for transfer to the execution subsystem. The data is byte, word, longword address displacements,
absolute addresses, and immediate data. Branch displacements and literals
are also transferred over this bus.
• Virtual address bus transfers virtual addresses from the execution subsystem
to the cache subsystem.
• Write data bus transfers write data from the execution subsystem to the cache
subsystem.

Power Subsystem
The power subsystem provides the electrical power in proper voltages to operate the processor. The power subsystem is divided into five functional groupsa controller, an Nbox (multifunction power converter assembly) port conditioner, module power supplies, an environmental monitoring module, and a
battery backup unit. Figure 2-12 contains a simplified block diagram of the
power subsystem.

2-20 • VAX 8800 and 8700 Processor Systems

----...-.

TO
VAXBI
BUS

TO
--5.2 vae
BUS
TOCLK

• FOR 50 Hz ONLY

&2
NBIA

+5.0 voq

Figure 2-12· Power Subsystem Block Diagram
• CON1ROLLER

The controller requires input power to be 220-V, 3-phase, and A, B, C rotation
sensitive. The controller module receives power from the main circuit breaker
and distributes that power to three other modules in the power subsystem and
to the air mover module. The output power from the controller module is distributed to four subsystems. The Nbox receives unswitched single-phase and
switched three-phase ac power. The battery backup unit receives unswitched,
single-phase, country power. The console subsystem receives unswitched singlephase 120 Vac. The air mover subsystem receives three-phase unswitched 120
Vac.
• POWER CONDmONING (NBOX)

The Nbox is a multifunction power converter assembly having five sections.
Two sections convert three-phase 208 Vac power into 300 Vdc. An Interface
Logic Module provides a logic signal interface for the environmental monitoring module and other power system components and controls battery backup
operation. A control and startup power module converts single-phase 120 Vac
to logic-level dc voltages and supplies the interface logic and environmental
monitoring modules. A new box translator module converts logic signals for
startup and initialization procedures.

2-21

• MODULAR POWER SUPPLIES
The modular power supplies (MPS) consist of a group of dc power modules and
a backplane. The modular power supplies regulate dc power for the CPU,
memory subsystem, and I/O adapter modules. They are housed in the processor cabinet above their respective card,cages.

• ENVIRONMENTAL MONIIDRING MODULE
The environmental monitoring module (EMM) is a microprocessor-based,
dual-function device. Its first function is to monitor the power, temperature,
and airflow conditions within the processor cabinet reporting through the console subsystem. Its second function is to protect the system from damage from
extremes in environmental conditions. The EMM responds to console subsystem commands during powerup and powerdown sequencing, initialization,
and battery backup operations. The EMM also responds to the console subsystem during normal operation when it is routinely polled from the console. The
EMM forces emergency shutdown outside of programmable limits.

• BATTERY BACKUP UNIT
The battery backup unit (BBU) provides the power subsystem with 300 Vdc
during utility ac-power outages. It can supply the dc power for memory refresh
for a minimum of 9 minutes with 32 megabytes of memory composed of eight
4-megabyte arrays. It also supplies power for 128 megabyte arrays. The unit
contains a 48-volt battery pack, a charging circuit, and a dc-to-dc converter.

Oock Subsystem
The clock subsystem generates, controls, and distributes timing signals to all the
components of the processor system. The clock contains a console subsystem
interface, an oscillator, a phase generator, clock control logic circuits, and clock
signal distribution logic circuits. Figure 2-13 illustrates the clock subsystem and
the signals it generates.

2-22 • VAX 8800 and 8700 Processor Systems

NMI SLOW CLOCK ENABLE-----Iol '"

'+---MICAOMATCH------~

' + - - - - - S T E P B CLOCK
' - - - - - - C O N S O l E DATA
' - - - - - - C l O C K STATUS ----I~

CONSOLE
INTERFACE

L - - - - - - - - - C L O C K PERIOD - - - - I o l
'---------INTERVALSyNC

- - - L__-.J

Figure 2-13 • Clock Subsystem Block Diagram
The oscillator is the basic source of timing for the clock subsystem. It generates
a reference signal that is sent to and used by the phase generator to produce two
nonoverlapping clock phases.
Clock generation logic is controlled by the console subsystem with operatorinitiated commands. Three registers in the clock logic are used for control of the
system clocks by the console. A fourth register provides status information for
the console operator. The clock control, clock period, and burst count registers
control the clock. The timeout and status register provides the status information. The clock subsystem is controlled from the console. Using console commands, you can perform

• Start and stop the clocks.
• Burst the clocks; that is, cycle the clocks on and off for a specified number of
cycles.
• Single-step the clocks; that is, increment instructions in bursts of one cycle.
• Enable a clock stop operation on a micromatch.
• Enable a clock trap operation on a micromatch.
• Change the clock period.
• Disable clock stalls~
• Control the timeout clock (MI Slow Clock Enable).

2-23

Input/Output System
The va subsystem communicates with devices outside the processor. Typical
devices include disk and tape drives, printers, terminals, communications
devices, and VAXcluster interconnects. The bus that handles va for the VAX
8800 and VAX 8700 processors is the VAX Bus Interconnect (VAXBI) .

• VAX BUS INTERCONNECT
The VAX Bus Interconnect (VAXBI) is a 32-bit synchronous bus that serves as
the va bus for the processor system. VAXBI buses are connected to the processor system through MI-to-BI adapters as shown in Figure 2-14.
The DB88 adapter serves as an interface between the memory interconnect (MI)
and VAXBI bus_ It is the va path to mass storage devices, Digital networks,
communications devices, and other peripherals.

DB88 includes a minimum of 1 NBIA module, 1 NBlli module, and two cables.
The NBIA, an extended hex module mounted in the CPU backplane, contains
the memory interconnect port and DB88 transaction buffers. The NBIB module, located in the VAXBI backplane, contains two VAXBI user ports. The MI
port communicates directly with the MI bus_ The VAXBI user ports communciate with the VAXBI bus.
VAX 8800 and VAX 8700 systems can be configured with up to 4 VAXBI channels. See the VAX Systems and Options Catalog and VAXBI Options Handbook
for configuration details_

Figure 2-14 • I/O Bus Block Diagram

2-24 • VAX 8800 and 8700 Processor Systems

Note

In Figure 2-14 (above), the NBIB adapter is shown installed at
VAXBI Node Addtess o. The drawing depicts a typical location.
The NBIB adapter may be installed at any location with one exception. If a DWBUA UNIBUS adapter is in the configuration, it must
be installed at VAXBI Node Address o.
The VAXBI bus supports up to 16 VAXBI nodes with each adapter havmg a
unique node identification value from 0 through 15. Node identification is
determined by an identification plug that is inserted in the backplane. The
VAXBIbussupports
• Memory read!write operations (allows direct memory access (DMA) transfers
between an VO device on the VAXBI bus and the memory subsystem through
bus read!write transactions).
• 1/0 register read!write operations (allows the processors to access the VO
registers in VO devices on the VAXBI bus through VO space read!write transactions originated by the processors).

• Interrupt handling (enables VO devices on the VAXBI bus to interrupt the
processors through bus interrupt transactions directed to the NBIB node).
• System synchronization (provides NBI-generated clock signals to all nodes
connected to the VAXBI bus).
• System initialization or reset (allows nodes to assert a reset line and initialize a
simulated VAXBI bus powerfail sequence. Also halts and reboots both
processors) .
• Fbwerfail warning (provides alternating current low (ACLO) and direct current low (OCLO) signals to all VAXBI nodes) .

• VAXBI BUS ADAPTERS
Numerous types of adapters are available to connect a variety of devices to the
VAXBI bus. Adapters are available to connect new devices as well as existing
devices to the VAXBI bus. A VAXBI adapter. to Digital's UNIBUS also exists.
With appropriate adapters, the VAXBI bus can support existing and future
peripheral equipment made by Digital.
For details on the adapters and for configuration guidelines, refer to the current
VAX Systems and Options Catalog~ Technical description are given in the VAXBI

Options Handbook.

2-25

• Mass-storage Subsystems
The mass-storage subsystems for VAX 8800 and VAX 8700 Computer Systems
are varied. The KDB50 disk controller for the VAXBI is described briefly in
Chapter 7 of this handbook and in the VAXBI Options Handbook.

• Reliability, Availability, and Maintainability
The VAX 8800 and VAX 8700 Systems have an enhanced Reliability, Availability,
and Maintainability Program (RAMP) and diagnostic features in addition to the
other VAX family features. The new features include:
• Environmental and power monitors (EMM) to protect the system should
temperatures or power levels exceed safe limits.
• Automatic verification of hardware, firmware, and software revision
compatibility.
• Electrically keyed modules and module slots. Different modules have different power requirements (voltages) at different contacts. The keys prevent
improper installation and the possibility of applying a voltage that can damage the circuitry.
• System is reconfigurable to one CPU if the other CPU fails (VAX 8800 Processor Systems only).
• Automatic electrostatic discharge (ESD) provision to protect modules during
installation.
Existing features in the VAX family of processors are:
• Error correction code (ECC) on main memory.
• Parity checking on internal RAMs.
• Memory Interconnect bus protocol checking, bus silo, and parity.
• Timing and voltage margining.
• Remote diagnostics package.

Reliability
Both processor subsystems are designed for high reliability through the maximum use of highly integrated semiconductor devices, a 22-layer printed circuit
backplane, zero-insertion-force (ZIF) connectors, and nine-layer printed circuit
logic modules. Extensive parity and data integrity protection has been implemented throughout the system. The remote diagnostics capability, extensive
integral diagnostics, and high-reliability components all contribute to Digital's
ability to offer a 12-month warranty on the CPU kernel. The VAXBI bus also
enhances system reliability with its error detection and error logging logic.

2-26 • VAX 8800 and 8700 Processor Systems

Availability
Both the VAX 8800 and VAX 8700 Systems contain high availability features.
System powerup, diagnostics, monitoring and control are performed efficiently
by way of a realtime interface to the processor subsystem. An environmental
monitoring module (EMM) constantly monitors temperatures and voltages
throughout the processor subsystem. The EMM subsystem constantly reports
status and conditions on the console.

Maintainability
The console subsystem contains a remote diagnostic port. The port allows an
operator at a Digital Diagnostic Center to connect the malfunctioning system to
a diagnostics engine at the center. Within seconds after the connection, the malfunctioning system is tested and a report made. All printed circuit boards are
installed with zero-insertion-force connectors. This affords safe and easy
removal of malfunctioning boards while maintaining installed signal integrity.

The VAX 8650 (Figure 3-1) is a high-performance system that provides the
speed and power needed for single and multiuser large scale processing applications. Its high-performance mainframe computing is 44 percent faster than
that of the powerful VAX 8600 system. If you already use VAX systems, all of
your investments in equipment, training, and software are protected.
Conforming to the VAX architecture, the VAX 8650 processor is compatible
with all other VAX processors. It supports the VMS operating system with its
associated layered software products, and the ULTRIX-32 operating system.
Ideal for extensive scientific, engineering, and realtime applications - including artificial intelligence, simulation, and computer-aided design - the VAX
8650 also provides the va capacity for large timesharing applications in government, commercial, administrative, and academic environments.
The VAX 8650 processor incorporates customized emitter-coupled (ECL) gatearray logic and four-stage instruction pipeline processing. The customized ECL
logic allows more components to be included on a module and provides a significant increase in processing speed. The pipeline processing of instructions
enables the processor to operate on several instructions simultaneously, thereby
reducing the number of cycles required for each instruction. The 16-kilobyte
cache is a writeback memory used to decrease the access time of memory
references.
The VAX 8650 processor includes virtual memory management; a bootstrap
loader; standard instructions for packed decimal, floating point data types, and
fixed-point arithmetic; and character and string manipulations. Also included
are the 16-kilobyte write-back cache memory, high-precision realtime programmable clock, time-of-year clock with battery backup, and 8 kilowords (86-bit
words) of writable control store.
The VAX 8650 processor includes a synchronous backplane interconnect (SBI)
adapter. A second SBI adapter can be added to expand the va capabilities of
the system. The communications path between the processor and main memory is through an internal memory bus, which effectively decreases the memory
access time. The SBI is used only for communications between devices and
memory and therefore the speed and efficiency of the I/O transfers are
increased.

3-2 • VAX 8650 Processor

Some of the features and benefits of the VAX 8650 systems are:
• High-performance mainframe computing - 6 times the performance of the
VAX-11I780.
• Up to 68 Mbytes of memory for large applications.
• Large-system CPU performance for VAXcluster Systems.
• Easy upgrade from the VAX 8600 system with the VAX 8650 Upgrade Kit.
• Proven, high-speed throughput in scientific and technical applications.
• Increased performance and reliability through customized emitter-coupled
(ECL) gate-array logic and four-stage instruction pipeline processing.
Refer to Appendix A for performance specifications and related data for the
VAX 8650 processors. For positioning relative to other systems, see the comparison chart (Thble 1-1).

Figure 3-1 • The VAX 8650 Processor

3-3

• VAX 8650 Physical Con6.guration
The VAX 8650 processor and console, shown in Figure 3-2, are contained in a
CPU cabinet and an attached front-end cabinet The CPU cabinet contains the
processor, console logic, floating-point accelerator, space for up to 68
megabytes of main memory, an SBI adapter bus backplane, and an I/O adapter
backplane_ The modular power supplies, regulators, and power distribution
network are above the logic area_
At the bottom of the CPU cabinet is the power control unit, which receives the
system line power and the battery backup unit that supplies power to the memory in the event of a power failure. A blower unit at the top of the cabinet provides cooling for the power supplies and logic modules. The switches and
indicators that monitor and control the system operation are on the panel at the
top of the CPU cabinet. The signal cables between the cabinets and the communication and storage devices connect to I/O connector panels located at the rear
of the cabinets. The connector panels have plates that can be removed to mount
cable connectors.
The front-end cabinet includes the RL02 disk drive (a lOA-megabyte, removable media, console load device), a UNIBUS backplane mounted in a BAll-A
box for communication devices, and a step-down power transformer that is
supplied when 50-hertz main power is used. The step-down transformer has
voltage taps to ensure line power compatibility.
A UNlliUS expansion cabinet can be added to expand the system UNIBUS. A
synchronous backplane interconnect (SBI) expansion cabinet can be added to
extend the SBI interface, which is included in the main cabinet, and two SBI
expansion cabinets can added when a second SBI adapter is used.

Power Supply

RL02

I Power Supply

Master Power Supply

BA11-AL

I 4MB
MS86

EKpanslon
Spa~efor

Arldilional
64MB

CPU

Memory

Console
Memory Controller

:IiCl
S
~

'~"

Figure 3-2 • VAX 8650 Processor Configuration

3-4 • VAX 8650 Processor

System Expansion Cabinets
The expansion cabinets are available for mounting additional UNIBUS interfaces and for mounting a second SBI adapter. The H9652-F series ofUNlliUS
expansion cabinets is shown in Figure 3-3. The H9652-FA (-FB) cabinet
includes a BAll-A mounting box and provides space for adding a second BAllA mounting box. The H9652-FC (-FD) cabinet includes two BAll-A mounting
boxes. No expansion boxes are mounted in the H9652-FE(-FF) cabinet. The
BAll-A box contains a power supply and allows installation ofDDll-CK (fourslot) andDDll-DK (nine-slot) for a total of six system units. Forty option panel
spaces are available at the rear of the cabinets for mounting the VO device
connectors.

2-Inch Blank
Panel Insert

I/O
Connection
Panel

I/O
Connection

Panel

I/O
Connection

Panel

--.

rl~
SPACE FOR
BAll·A

II II II I
I I

- r--:

SPACE FOR
BAll·A

-r
UNIBUS Expander
H9652-FA(FB) (One BAl1-A)
H9652.FC(FD) (Two BAl1.A)

Figure 3-3 • UNIBUS Expansion Cabinet Configuration
The H9652-CA (-CB) is a SBI expansion cabinet and is shown in Figure 3-4. The
SBI expansion cabinet contains an SBI backplane and power supply. It provides
four option panel spaces and space for an additional power supply.

3-5

w
<..l

<..l

'"
W

'"-"

...J

~
11.

COOLING

FRONT VIEW

Figure 3-4 • SBI Expansion Cabinet Configuration

• VAX 8650 Processor Organization
The functional organization and bus structure of the VAX 8650 processor are
shown in Figure 3-5. The processor contains four main logic subsystem blocks:
the instruction execution logic (Ebox), the instruction/data fetch logic (Ibox),
and the memory control logic (Mbox), and the floating-point accelerator logic
(Fbox). A system of internal buses form the addtess, data, and control signal
paths within the CPU logic. The consol~ subsystem connects to the Ibox
through the C bus. The synchronous backplane adapter connects to the Mbox
and provides the SBI bus for communication with the external devices.

00
e;;

<:>

:Jl

EVA

e,;
0
~

<:I

~
<:>

...

~<:>
~

1:>'

·OPTIONAl

A !:
Bus

IVA

I II i;i

1
~

3-7

TO CPU
E BOX

Figure 3-6 • VAX 8650 Console Subsystem Components
(A)nsoIeSU~ED

The VAX 8650 console subsystem is a programmed interface between the VAX
8650 processor and the console terminal, console disk drive, remote diagnostic
port, and the system environEDental monitoring module_ See Figure 3-6_ The
console subsystem is controlled by a T-ll microprocessor that supports a subset
of the LSI-ll instructions_ The console subsystem includes a 256-kilobyte, parity-assisted dynamic RAM, an 8-kilobyte PROM, three programmable serial-line
interfaces and a time-of-year (IDY) clock The three serial-line interfaces transmit information to and receive information from the console terminal, remote
diagnostic line, and environEDental monitoring module (EMM)_

3-8 • VAX 8650 Processor

Note
The VAX 8650 console subsystem is the same as the VAX 8600 console subsystem. Differences between the systems are noted here.
The console software resides in the 256-kilobyte RAM and the 8-kilobyte
PROM. The 8-kilobyte PROM storeS the program executed by the T-ll during
the powerup sequence. This program self-tests the microprocessor, performs
hardware initialization, and loads the console· software into the 256-kilobyte
RAM from the console load device. The console software includes the diagnostic console program (DCON), macrocOde control program (MCP), and the diagnostic control program (DC).
The console subsystem
• Includes a system clock control and time-of-year clock with battery backup.
• ~rforms the system power sequences and monitors the system environment.
• Includes EIA-compatible, serial-line interfaces for the console terminal,
remote diagnostic port, and environment monitoring module.
• Includes the system and processor diagnostics programs.
• Provides memory storage for bootstrap and diagnostic programs.
• Provides self-diagnostic testing during system initialization.
• Includes powerup configuration programming.
In addition to the standard capabilities provided by all VAX processor subsystems, the VAX 8650 console subsystem provides local diagnostic testing in the
diagnostic control mode, a mode to test the microcode, and a debug-trace test
facility..
For detailed information on the VAX 8650 console subsystem, refer to the

VAX Hardware Handbook Volume 1-1986.

• Central Processing Unit
The main logic dements in the CPU are the instruction/data fetch (!box), the
instruction execution (Ebox), the memory control (Mbox), and the floatingpoint accderator (Fbox). Each dement contains a copy of the sixteen generalpurpose registers to ensure immediate access to the general-purpose register
data and system status information. See Figure 3-7 for the VAX 8650 System
Configuration and the current VAX Systems and Options Catalog for configuration requirements.

3-9

FLOATING POINT
ACCelERATOR
(FPAj

EMM
CONSOLE TERMINAL
REMOTE
DIAGNOSTIC SERVICE

RL02 DISK
DRIVE

----

WRITABLE
CONTROL
STOREtWCS)

ECC MOS
MEMORY
68 MB TOTAL

VAX 8650

CPU
CONSOLE
SUBSYSTEM
8ATTERY BACKUP UNIT

SBIAD
UBA

MBA

001

UBA

3
2
0
A
T
A

A
S
S
B
U
S

CIA

:10.

U
N
I
B
U
S

L
I
N
E
S

" :;.

CACHE MEMORY
SBIA1

U
N
I
B
U
S

MBA

~
M
A
S
S
B
U
S

001

CIA

;>.

,t.
3
2
0
A
T
A
L
I
N
E
S

Vvv

STANDARD OPTIONAL OPTIONAL OPTIONAL OPTIONAL OPTIONAL OPTIONAL OPTIONAL

3
OPTIONAL

Figure 3-7· VAX 8650 System Hardware Configuration

Instruction Box Functions
The instruction box (!box), consisting of the instruction and data prefetch
logic, is the interface between the Ebox and Fbox execution units and memory_
It contains the following logic functions:
• 8-byte FIFO instruction buffer
• Dispatch RAM
• Memory data path
• Control store RAM
• General purpose register @e and an R-Iog @e
• Address and memory data path
• Write latch

3-10 • VAX 8650 Processor

All data transfers to and from the execution logic is through the !box, which
receives the instruction stream of bytes from memory. From the memory information, the !box determines the information to retrieve and the activity to initiate in the Ebox. The Ibox performs the first three stages of the four stages
required for instruction execution. It prefetches the instruction stream, decodes
the instruction opcodes and specifiers, calculates the required address, fetches
the operands, and initiates the read and write cycles. The execution of the
instruction is then performed by the Ebox or the Fbox while the Ibox begins
processing the next instruction.
The instruction buffer is an 8-byte buffer that stores a copy of the bytes
fetched from memory. The primary function of the buffer and its associated
logic is to prefetch instruction stream bytes and to align them contiguously.
More than one instruction is usually contained in the instruction buffer;
therefore, the next opcode and specifier will be available when the current
instruction is completed. It also is used to fetch and align decimal-string
operands.
The dispatch RAM contains a table of dispatch addresses for every macroinstruction and provides control information to the lbox and address data
paths. The address data path and associated control logic perform address calculations and branch displacements, and controls the start of the instruction
buffer. Using the opcode in the instruction buffer as an address, the dispatch
RAM sends a dispatch address to the Ebox control store.
The memory data path logic controls the data transferred between the Mbox
and the !box. The data is aligned by a rotator in the data path before transfer to
the execution units or to the instruction buffer.
The IboX control store is a 256-bit by 52-bit RAM that processes the operand
specifiers and branch instructions, updates the register (R-Iog) file, responds to
specific Ebox commands and master reset, and assists in performing the
microdiagnostics.
The general purpose register file contains the same information that is stored in
the general purpose register files of the Mbox and Fbox. The file provides
accessibility to the register data for addressing modes.
The R-Iog file stores the register information that may change during the
instruction execution. The typical information stored in the R-Iog can be the
current program counter values, the general purpose register address, the
amount of change to a register, and whether the change was added to or subtracted from the register. This information is required during memory management faults to return the processor to the state prior to the condition that
caused the fault.
The address data path performs address calculations and branch displacements, and initializes the IBUF. It also provides a backup file for the general
purpose register and macro-Ievd diagnostics.

3-11

A write latch is used to align the data and to store the resulting data from the
Ebox and Fbox to be written to cache memory.

Execution Box Functions
The execution box performs logical, arithmetic, and other operations required
to execute the instruction. The results are then transferred to the Ibox through
the W bus, to be written into memory when required. The Ebox controls the
system operation during system initialization and during console mode functions by executing the VAX instruction set and by processing both external and
internal interrupts and exceptions. The Ebox includes the following logic
elements:
• Data path logic
• Control store RAM
• Microsequencer logic
• Console interface
• Maintenance logic
The data-path logic includes a 32-bit binary arithmetic logic unit (ALU), shifter
and data packer/unpacker logic, two scratchpad locations that contain copies
of the general purpose registers, a virtual memory queue register, and a W bus
register. The ALU performs arithmetic and logical operations and provides special functions to decrease the processing time for division, decimal arithmetic,
and compare operations. The shifter and data/packer logic is used to pack and
unpack floating-point data, to translate decimal data formats, to shift and rotate
arithmetic data, and to perform other bit manipulations.
When an external interrupt and internal interrupt occur simultaneously, the
internal request is processed first. External interrupts, sampled from the 110
adapters and received by the SBI adapters, are sent to the Ebox. The Ebox
scans the SBI adapters to determine the highest priority request pending for
each interrupt source. The internal interrupts are received from the console
terminal, from the Mbox, and internally from the Ebox. Information is written into the control store RAM when the Ebox clocks are disabled or stalled.
The microsequencer logic accesses the RAM in response to console operations and microprogram subroutines, traps, stalls, and subroutines. The
console interface provides the path to initialize the control store during the
program loading and startup sequence. It also allows·the console to enable
or disable the maintenance logic and to correct errors.

3-12 • VAX 8650 Processor

The control store is an 8-kilobitby 92-bit RAM that receives information when
the Ebox docks are stalled or disabled. The microsequencer accesses the control store information in response to microprogram control, instruction dependent dispatching, microprogram subroutines, microtraps, machine stalls,
console operations. and microstore-related error conditions. The control store
is initialized by the console interface during a system cold start and allows the
console to enable or disable the maintenance logic and perform error correction
operations. The maintenance functions are implemented through the dock
logic hardware, console software, and the Ebox microword.
The Ebox control consists of context logic, memory port logic, and abort logic.
The context logic generates data size information for the Ebox data path and
references for the Ebox memory port and controls W bus transactions. The
memory port logic performs functions associated with issuing and requeuing
memory commands that are used for branch conditioning and memory management microcode. The Ebox initiates microtraps and creates microtrap vectors from the status information received from the Mbox. Abort logic cancels
nonrecoverable operations caused by errors that are detected but do not result
in a stall condition. Errors are recovered through the fault process and the
processor is returned to the beginning of the microinstruction. The stall logic
determines if an input or output stall condition exists in the Ebox microcyde.
The Ebox contains interrupt logic to process internal and external interrupt
requests and to determine their priority. The internal interrupts are generated
by the console subsystem, the Ebox, and the Mbox. The external interrupts are
sampled from the 110 adapters through the A bus.
The Ebox contains two dual-ported scratchpad memories, each consisting of
256 32-bit registers. The scratchpad memories are used as internal temporary
storage for the microcode and to store copies of the general purpose registers
and constants. They are also used by the memory management and operation
system.
A virtual-memory queue register provides physical and virtual addresses to
the Mbox. 'Ibe W bus registers are accessed by microcode through the
Wbus.
The maintenance functions are implemented through the dock logic hardware,
console software, and the memory array modules and 110 adapters.

Floating-point Accelerator Functions
The floating-point accelerator (Fbox) decreases the time to perform floatingpoint instructions and some. integer instructions. The Fbox logic contains 16
general purpose registers, and adder and multiplier logic.

3-13

Operands received from the adder are multiplied by the multiplier logic and the
product is returned to the adder for rounding and normalization. During floating-point operations, the multiplier operates on the fractions and the adder
operates on the exponent. During integer operations the entire two's complement number is multiplied.
The adder logic performs addition, subtraction, and division and handles the
exponents for all the basic operations. The adder contains the logic to unpack
the floating-point numbers, to align fractions, and to round and normalize the
results. The operands are received from the OP bus and returned to the W bus.
The Fbox receives general purpose register updates and Ebox data, and
accesses some Fbox registers through the W bus.
Memory Controller Functions

The memory controller (Mbox) contains the logic for controlling memory
operations and for communicating with the VO subsystems and devices. The
main logic elements of the Mbox are:
• 16-kilobyte cache memory.
• 512-location translation buffer.
• Error detection and correction logic.
• Ibrt control logic.
• Memory arrays.
• Mbox control store.
The Mbox is the interface to the main memory arrays, to the SBI adapters, to the
Ibox, and to the Ebox and Fbox. The Mbox connects to the memory through
the memory array bus and to the SBI adapter through the A bus. Its function is
to store memory write data and to supply memory read data in response to
requests by the Ebox and Ibox and in response to direct memory access (DMA)
requests. It also stores VO write data and supplies va read data in response to
requests by the Ebox. During DMA requests from an SBI adapter, the Mbox
stores memory write data and supplies memory read data to the SBI. The virtual-to-physical address translation is performed by the translation buffer. The
physical address memory mapping (EAMM) selects memory array modules and
va adapters being accessed and is enabled by the PAMM logic in the Mbox.
The cache memory provides fast access to the memory data.
The translation buffer is a 512-location cache memory used for storing 256
system-page-table entries and 256 process-page-table entries. During Ebox
and Ibox references, the translation buffer is used to decrease the virtual-tophysical translation process. During normal operation the translation buffer
is loaded from the page tables in memory by the microcode; during diagnostic operations, loading is through the SD bus.

3-14 • VAX 8650 Processor
The ffiMM is a 1-kilobit by 5 -bit RAM that maps the physical address space and
is addressed by the high-order bits of the physical address. The output is
decoded and used to select the array slot or 110 adapter being accessed. The
ffiMM is loaded during the system initialization through the SD bus and by system-level programs.
The 16-kilobyte cache is a writeback memory used to decrease the access time
of memory references. The cache is arranged in two groups of 8 kilobytes each
and provides byte parity and error correction code (ECC) on each longword.
The Mbox control store is a 256-bit by 80-bit RAM that controls the Mbox
operations including port read and write functions, error recovery, cache refill
and writeback operations, A bus transactions, register read and write operations, and the diagnostic functions. The control store is loaded from the SD bus
during system initialization.
The port control logic provides arbitration during instruction operand fetching
of the !box and read and write operations by the Ebox. The control functions
of the Mbox include special byte-write logic that decreases the time to insert
the bytes into longwords. It also includes the memory refresh logic for the
256-kilobyte MOS RAM integrated circuits in the memory array.
Each memory array module contains 4 megabytes of error correction code
(ECC) MOS memory storage and the timing and control logic to refresh memory when the main power to the system fails. During read operations, the physical address from the memory controller is sent to an array together with a start
command. The array loads four longwords with ECC from memory into a shift
registerlbus transceiver. The memory controller then shifts the data, one
longword for each cycle, from the register to the A bus. The memory controller
performs error correction on each longword it receives. During write operations, the memory controller sends the address and data to the array through
the A bus. The data is loaded to the shift register on the memory array and the
memory controller issues a start command to write the data in memory. The
memory controller can then initiate a cycle in another array while the data is
being written..

3-15

Synchronous Backplane Interconnect Functions
The synchronous backplane interconnect adapter (SBI adapter) is the interface
between the SBI bus and the A bus. The SBI adapter provides the functions
required to control MASSBUS and UNIBUS 110 operations. It establishes the
protocol, provides the timing, and assembles the data for transmission in either
direction. The SBI adapter contains the following logic elements:
• Buffer control and A bus logic
• Register file
• Clock logic
• SBI bus interface

• Interrupt control logic
• Data latches
The SBI adapter provides the processor and memory nexus functions to the SBI
bus and generates the SBI clock signals. The nexus is a physical connection to
the SBI bus. Command and address data are exchanged between the SBI
adapter and the Mbox through the A bus. Interrupt information and interrupt
polling are exchanged between the SBI adapter and the Ebox. The A bus and
buffer control logic control the reading and writing of the SBI adapter register
files, notify the Mbox when CPU or SBI adapter transactions occur, receive and
buffer the timing signals for the A bus synchronous logic, and notify the Ebox
when an interrupt condition is detected.
The register file stores the 110 data transferred through the SBI adapter. It is a
dual-port 16-line by 32-bit register that operates synchronously with both the
A bus and the SBI bus.
The interrupt logic notifies the CPU of errors detected during DMA transactions, fault conditions detected on the SBI bus, and programmed maintenance
procedures. It also passes interrupt requests from SBI devices to the CPU.
The clock logic generates the timing signals for the SBI operations.
Data latches are used to hold or convert infonnation transferred to or from the
SBI bus. Infonnation from the SBI bus is converted to the A bus fonnat. The SBI
adapter contains 35 registers that are accessed through the CPU transaction
buffer. The registers are used to condition the SBI adapter during bootstrap
operations, to record error infonnation, to store vector addresses during the
servicing of interrupts, and to establish maintenance and diagnostic functions.

3-16 • VAX 8650 Processor

The SBI bus interface logic samples the data transfer lines of the SBI during
each cycle and transfers the results to the SBI bus protocol logic and to the
data latches_ It also transmits information to tht! SBI bus from the data
latches_ The SBladapter protocol logic provides protocol checking and verifies the commands and data received by the SBI adapter_

Cache Memory
The cache memory provides the central processor with highcspeed data access
by storing frequently referenced addresses, data, and instruction items in the
secondary memory_ The cache memory significantly reduces the processor's
effective memory access time. The cache memory in some of the VAX systems
includes an instruction buffer that enables the processor to fetch and decode
the next instruction while the current instruction completes execution.

An address translation buffer also is used to eliminate extra memory accesses
during virtual-to-physical address translations. The buffer contains frequently
used address translations.

Environmental Monitoring Module
The VAX 8650 processor includes a microprocessor-controlled environmental
monitoring module (EMM) in the modular power supply area of the cabinet.
The module samples and controls the environmental conditions in the processor and optional system cabinets. The module monitors and controls the dc
regulator voltages and checks the regulator error status. It also monitors the
cabinet air flow, cabinet air temperatures, and ac ground currents for excessive
current flow. The functions of the EMM are monitored and controlled by console commands from the console subsystem. By controlling the dc regulator
voltages from the console terminal, marginal voltage conditions can be established to help detect intermittent logic errors. For details of the operation of this
module refer to the VAX Hardware Handbook %lume 1-1986.
Main Memory
VAX 8650 processors offer a choice of two high-reliability main memory arrays,
a 4-megabyte (MS86-AA) array and the new 16-megabyte (MS86-CA) array.
Both arrays can be used on the same system at the same time. The VAX 8650
uses a total of ten backplane slots in the processor cabinet. Two slots are
reserved for the memory control logic. Eight slots are reserved for the memory
storage arrays. Each extended-hex module slot provides power to the memory
logic and electrical connection to a dedicated, high-speed 110 adapter bus. The
bus provides a data transfer rate of up to 34.3 megabytes per second. All memory operations - addressing, data read, and data write - are pipelined in the
VAX 8650. A cache reference can be completed during every cycle. Battery
backup for main memory is a standard feature on VAX 8650 processors.

3-17

The VAX 8650 processor features convenient and flexible main memory
expansion up to 68 megabytes. Current VAX 8650 memory storage and
expansion options are shown in Thble 3-1.
Thble 3-1 • VAX 8650 Storage and Expansion Options

SBB*

Minimum

Maximum

Expansion Arrayst

VAXcluster

32MB

68MB

MS86-AA and/or MS86-CA in
increments of 4 and 16 Mbytes

VMS

16MB

68MB

MS86-AA and/or MS86-CA in
increments of 4 and 16 Mbytes

* SBB = System Building Block
t The maximum numbet of slots available on tbe VAX 8650 memory backplane is eight.
Each 4-megabyte MS86-AA array uses one slot, each 16-megabyte MS86-CA arrayoccupies two slots except for tbe rightmost MS86-AA array that takes only one slot.

Other features of the memory arrays are:
• Up to 68 megabytes of main memory providing room for growth and support
for the largest applications.
• Choice of 4 megabyte or 16 megabyte 256-kilobit dynamic MOS RAM memory expansion arrays for configuration flexibility and planned incremental
expansion.
• Reduced memory access time as a result of a dedicated memory bus, pipelined references, and a greater cache hit rate.
• Use of premium quality, high-density memory components means greater
reliability and lower maintenance costs.
• Standard Error Correction Code (ECC) offers exceptional reliability, data
integrity, and lower service costs .
• MEMORY ARRAYS
Two models of memory array boards, the "MS86-AA and the MS86-CA, are
available. MS86-CA boards have a greater storage capacity than the MS86-AA
boards. Functionally, there is no difference between the boards. The boards are
described in detail in the following paragraphs.

3-18 • VAX 8650 Processor

MS'86-AA MEMORY ARRAY - The MS86-AA memory array board provides 4
megabytes of information per board for a total memory capacity of 32
megabytes. Each MS86-AA board contains 156 dynamic MOS RAM devices.
Each RAM device has 256-kilobit by I-bit capacity. The I50-nanosecond RAM
devices are organized into four memory banks of 39 devices each forming an
array matrix of 1 megabyte by 39 bits. Parity is 7-bits ECC per 32-bit longword.
Each MS86-AA board can store 1,048,536 individual 32-bit longwords of data.
With all eight of the VAX 8650 backplane memory slots occupied, the system
attains a total physical memory capacity of 32 megabytes in 4-megabyte
increments.

MS'86-CA MEMORY ARRAY - The MS86-CA memory array consists of a
mother board containing the control logic and eight daughter boards each
holding 2 megabytes of memory. Double-sided surface mounting permits the
attachment of 624 MOS RAM memory chips to the daughter boards. Each chip
has a 256-kilobit capacity. This permits 16 megabytes in the space previously
occupied by two 4-megabyte boards and gives the MS86-CA board at least four
times the capacity of other memory array boards.
The memory chip is a single-voltage (5 V), 256 kilobit by 1, 150-nanosecond
dynamic MOS RAM in a surface-mount package with a multiplexed row and
column address. The array matrix is 4 megabytes by 39 bits (32 data bits, and
7 ECC).
Each MS86-CA board requires two of the eight available backplane memory
slots. This limits the maximum memory configuration to four I6-megabyte
boards and one 4-megabyte board for a total of 68 megabytes .

• REFRESH INTERVAL
The refresh interval is approximately 13 microseconds or about one cycle in 36
(worst case). Refreshes are performed in one of two ways. In normal operation,
refresh cycles are timed by the cycle timing chain. When in battery mode, the
cycle is timed on a delay line. In both instances, the interval is timed and a
refresh request is generated.
In normal operation, refresh request is synchronized to the system clock. Then
arbitration occurs, and the refresh must wait if a memory cycle is pending or is
in progress. The memory cycle must wait if a refresh is pending or is in progress.
When operating in battery mode, column address strobe (CAS) is shut off and
the refresh addresses are chosen. No memory cycles are permitted. The refresh
operation can be disabled. This prevents refreshes in normal operation but not
in battery mode.

3-19

Input/Output Subsystems

The VAX 8650 uses the Synchronous Backplane Interconnect (SBI) bus as the
input/output channel for the system. The SBI bus is the data path that connects
both the CPU and main memory to the VO subsystem adapters. All UNIBUS,
MASSBUS, CI bus, and DDI bus devices communicate with the processor
through the SBI bus. Figure 3-8 shows the basic configuration of the devices
and adapters to the SBI.
For the details of the SBI bus, refer to the VAX Hardware Handbook Volume 11986. See the section on VAX 8600 VO Subsystems for detailed information.
For details of the adapters available for the SBI bus, see the section entitled
Large VAX Processor UNIBUS Subsystem.

UNIBUS
ADAPTERS
MASS BUS
ADAPTERS

CI ADAPTERS

001
ADAPTERS

Figure 3-8 • VAX 8650 SBI Bus Basic Configuration

3-20 • VAX 8650 Processor

• SYNCHRONOUS BACKPLANE INTERCONNECT ADAPTER
The synchronous backplane interconnect (SBI) adapter is the interface betweer
the SBI bus and the adapter bus. The SBI adapter provides the functions
required to control MASSBUS and UNIBUS va operations. It establishes the
protocol, provides the timing, and assembles the data for transmission in either
direction. The SBI adapter contains the following logic elements:
• Buffer control and adapter bus logic
• Register file
• Clock logic
• SBI bus interface

• Interrupt control logic
• Data latches
The SBI adapter provides the processor and memory nexus functions to the SBI
bus and generates the SBI clock signals. The nexus is a physical connection to
the SBI bus. Command and address data is exchanged between the SBI adapter
and the Mbox through the adapter bus. Interrupt information and interrupt
polling are exchanged between the SBI adapter and the Ebox. The adapter bus
and buffer control logic controls the reading and writing of the SBI adapter
register files, notifies the Mbox when processor or SBI adapter transactions
occur, receives and buffers the timing signals for the adapter bus synchronous
logic, and notifies the Ebox when an interrupt condition is detected.
The register file stores the va data transferred through the SBI adapter. It is a
dual-port, 16-line by 32-bit register that operates synchronously with both the
adapter bus and the SBI bus.
The interrupt logic notifies the processor of errors detected during DMA transactions, fault conditions detected on the SBI bus, and programmed maintenance procedures. It also passes interrupt requests from SBI devices to the
processor. The clock logic generates the timing signals for the SBI operations.
Data latches are used to hold or convert information transferred to or from the
SBI bus. Information from the SBI bus is converted to the adapter bus format.
The SBI adapter contains 35 registers that are accessed through the processor
transaction buffer. The registers are used to condition the SBI adapter during
bootstrap operations, to record error information, to store vector addresses
during the servicing of interrupts, and to establish maintenance and diagnostic
functions.

3-21

The SBI bus interface logic samples the data transfer lines of the SBI during
each cycle and transfers the results to the SBI bus protocol logic and to the
data latches. It also transmits information to the SBI bus from the data
latches. The SBI adapter protocol logic provides protocol checking and verifies the commands and data received by the SBI adapter.
The I/O subsystems connect to the processor through the DB86 synchronous
backplane interconnect adapters (SBI adapter 0 and SBI adapter 1). SBI adapter
ois included with the system and SBI adapter 1 can be added in the processor
cabinet. The SBI adapter 0 bus can be extended from the processor cabinet into
an SBI expansion cabinet. A DW780 UNIBUS adapter (UBA) is included with
the system and connects to SBI adapter 0, and one UBA option and an RB86 can
be added within the processor cab to SBI adapter O. The CI780 computer interconnect adapter (CIA) is optional and can also be connected to SBI,adapter 0 for
VAXcluster configuration.

• ADAPTERS
UNIBUS, MASSBUS, CI, and DDI adapters can be installed on either SBI adapter
1 or O. A maximum offour UBA options, four optional RH780 MASSBUS adapters (MBAs), four optional DR780 DR32 adapters (DDIs), or two CIA options can
be installed on SBI adapter 1. A maximum of two CI780 interconnects per system can be installed. The combination ofUBA, MBA, CIA, and DDI options on
the SBI adapters depends on the total number and type of adapters installed.

DISK DRIVE ADAPTERS - One UDA50 universal disk controller can be
installed on the UNIBUS to control up to four disk drives from the RA family.
The UDA50 is an intelligent controller designed for use with single processor
systems that operate within the Digital Storage Architecture.
A maximum of 16 high-speed lineprinters can installed, including LP25, LP26,
and LP27lineprinters. These printers provide hardcopy output: the LP25 prints
at 300 lines per minute, the LP26 prints at 600 lines per minute, and the LP27 at
1,200 lines per minute. The printers connect to the system through the DMF32
printer port or through a separate controller that mounts on the UNIBUS.
The UNIBUS also supports up to four RL02 (lOA-megabyte) removable-disk
drives and a maximum of four TU81 magnetic tape drives. A total of eight disk
drives or eight magnetic tape formatters can be connected in any combination
to each MBA. The devices include the RM05 (256-megabyte) removable-disk
drive and the TE16, TU77, and TU78 magnetic tape units.

VAXCLUSTER ADAPTERS - The VAX 8650 processors are available in VAXcluster configurations. Each system includes the VAX 8650 processor, 32
megabytes of ECC MOS memory, the CD80 or DW780 adapter and connecting
cables, and the DELUA Ethernet communications controller.

3-22 • VAX 8650 Processor

The Cl780 computer interconnect (CI) adapter is a microprocessor controlled, high-speed interface that connects the SBI bus to the dual-path CI
bus. Information is transferred at 70 megabits per second between the VAX
8650 and the VAXcluster components. The Cl780 adapter cables connect to
the SC008 Star Coupler unit through two receive and two transmit coaxial
cables, each with a maximum length of 45 meters (147.6 feet). Through the
VAXcluster, the overall system efficiency is greatly increased by sharing the
processor loads and by providing access to common mass-storage facilities.
The DR780 DR32 device interconnect (DDI) is a high-performance, general
purpose interface that permits communication between VAX processors and
between VAX processors and user devices. It connects to the SBI bus and provides a 32-bit paralld data path and an 8-bit control path. The DDI transfers
blocks of sequential data to and from memory at rates up to 6.67 megabytes per
second through direct menlory access (DMA) transfers.

ETHERNET ADAPTER - The DELUA (replacement product for the DEUNA)
is a high-performance synchronous communication controller used in local area
network applications. The DELUA connects to the UNIBUS and allows communication through the Ethernet network with Digital's systems and terminals and
systems devdoped by other manufacturers. Used in four out of six system configurations, the DELUA permits data transfer rates of up to 10 megabits per
second between processors or between processors and devices .

• Reliability, Availability, and Maintainability
In addition to the features included in all VAX processors, the VAX 8650 system
incorporates many other features to ensure reliable operation, high system
availability, ease of maintenance, and maximum performance. The hardware
and software of the VAX 8650 incorporate the latest design techniques to assure
efficient operation and maximum system dependability.
Approximatdy 15 percent of the logic circuits in the system are used to verify
the operation of the system and the integrity of the data. More than 3,000 logic
points on the processor backplane are available for analysis through the serial
diagnostic (SD) bus and the console tetnlinal.
Online diagnostic programs can be performed concurrently with the user mode
of the VMS operating system without interrupting normal processor operations.
If errors occur during the system operation, they are recorded and logged. The
processor is restarted automatically and allowed to continue processing the
instruction. Some of the rdiability, availability, and maintenance features are:

3-23

• High availability design.
• Processor signal levels that can be monitored through the console terminal.
• Error correction code (ECC) implemented on memoty, cache, and processor
microprocessor control logic.
• Online diagnostics for the VAXlVMS operating system.
• System-error detection and logging.
• Autodiagnostic and remote diagnostic capabilities.
• Special maintenance capabilities provided by the console processor
functions.

Battery Backup Unit
During short-term utility power interruptions, the contents of cache and the
general purpose registers are written into main memoty. The standard battery
backup unit preserves main memory contents, so there is no memory or context
loss when utility power is restored within the life of the battery backup. The
battery backup unit is monitored by the processor. The processor provides a
warning if the battery is discharged or otherwise faulty before it is needed.
Both boards are designed to survive temporary power failure (for a maximum
of ten minutes) by providing battery mode operation. All circuits needed to
maintain data are supplied power by the battery. All emitter-coupled logic and
most unnecessary transistor-to-transistor logic are not supplied power in this
mode. With the proper sequencing of signals, the array puts itself into battery
mode when power is restored, then turns over to normal operation. There is an
orderly conversion to battery and warm start. When in battery mode, the array
ignores the timing chain and performs refreshes only and not memory cycles.

Error Checking Code
Automatic error checking and correcting of main memory and cache memory
data eliminates many types of errors without interrupting the system operation.
The memory's error correcting code (ECC) -automatically corrects single-bit
memory errors and detects double-bit memory errors. The ECC provides protection from nonrepeating errors by automatically correcting data and also
detects greater than double-bit errors if an even number of errors is detected.

3-24 • VAX 8650 Processor

There is parity checking at RAMs and buses, and parity continuity is carried
through all major data paths. Parity is kept not only for data but also for
physical addresses and the microcode. Address parity and bad-data flags are
folded into the ECC. Thus, storage words also contain information about
error sources. Error detections and corrections are noted in the error log as
an aid to preventive maintenance. Because there are separate selects to each
memory array board, the control logic for storage selection is all in one
place, and faults can be isolated to a single board.
Extensive parity checks and other fault checkers in the Mbox make it highly
likely that errors will be detected and corrected, thus limiting their impact. IT a
transient error occurs, instruction execution pauses and the machine state is
saved in memory for processing by an error-analysis program. That program
provides information to Field Service for quick fault isolation.

Error Analysis and Reporting
The standard package of error analysis and reporting (SPEAR) program allows
system maintenance to be deferred until a more convenient time. The program
is based on the number of errors that occur and the customer is automatically
notified when error rates exceed a specified value. The SPEAR program is a
software maintenance tool that contains algorithms that analyze the machine
check data collected by the processor. Intermittent failures that allow the
processor to recover and continue operation are stored in an error file. The file
is examined by the SPEAR program to determine the cause of the malfunction.
The program detects specific patterns related to one error or to a series of
errors.
High Availability Design
The VAX 8650 processor incorporates high availability design features that
allow the system to recover rapidly from system errors by:
• Monitoring status information related to the error.
• Recording the information in an error log.
• Re-initiating the instruction in process when the error occurred.
When an error is detected that results in a machine check, up to 88 bytes of
error status information can be recorded. Because most errors that occur on
processors using LSI logic components are a result of intermittent failures, the
processor is allowed to continue operating after the error information is stored.
IT the error is repeated, the stored information can be evaluated later and maintenance can be performed at the convenience of the customer.

3-25

Dynamic Fault Insertion
Dynamic fault insertion allows the fault detection logic to be checked while the
VMS software is operating. Intermittent faults can be simulated by selecting the
desired timing of the processor clock, and by inserting and removing a fault at
the proper interval during one or more cycles. This is used to verify that the
recovery logic in the processor is being executed correctly.

Serial Diagnostic Bus
The serial diagnostic (SD) bus is a network data path between the console subsystem and the processor that connects to the major logic elements in the
processor. 1be bus verifies the system operation, diagnoses and isolates processor hardware faults, and provides a path from the console subsystem to control
the operations of the processor. The SD bus and interface allow internal signal
levels and signal levels transferred between modules through the system backplane to be accessed and displayed on the console terminal. This eliminates the
need for the special test equipment normally required to monitor processor
logic levels during maintenance.
The SD bus includes independent clocking and control, thereby enabling the
console software to initialize the processor hardware, step the processor clock,
monitor the state of various processor logic signals, and serially transfer data to
the console where it can be verified. By stepping the processor clock, the console software is allowed to follow the progress of the processor operation and
verify the logic response through the SD bus.
The SD bus consists of 24 serial data paths that connect to 24 separate visibility
control channels included with the Fbox, Ebox, Ibox, and Mbox. A visibility
channel in a processor module consists of an 8-bit visibility register and a multiplexer that selects internal logic information to be loaded into the visibility register. The console program reads a visibility channel by stopping the processor
clock and by shifting an 8-bit address code to select a multiplexer channeL The
register information is then transferred serially from the visibility register to the
console subsystem and displayed on the console terminal.

Microhardcore Context Commands
The microhardcore is a diagnostic program used to verify the proper operation
of the microhardcore (MCH) programs in the processor. The MCH program
consists of 98 subtests that are grouped into eight processor-logic function test
areas within the processor. The tests reside on the load media and the MCH
program does not create or modify the files in the load device. One test group
or all of the tests groups may be selected by the operator after the console diagnostics have been performed successfully. Only the selected tests are loaded
into memory. Messages from the MCH program are displayed on the console or
remote terminals.

3-26 • VAX 8650 Processor

The MCR context is entered by typing MCR in response to the diagnostic
console prompt (»». Once the program is initiated, the version name
and number is displayed and the microhardcore prompt (MC» is displayed. A test group or help file may then be selected.

Debug and 'Irace Facility
The debug and trace facility is used to modify and interrogate the hardware
state of the processor. The facility is enabled from the diagnostic context or the
macrohardcore context by the debug command. A hexadecimal debugger
(HEX) command set is included to allow the operator to modify and interrogate
the state of the processor. When it is enabled, an additional angle bracket (»
is added to the normal console command prompt displayed on the console
terminal. The REX command set is described in detail in the VAX

Hardware Handbook Volume 1-1986.

Parity Checks
The validity of the data and control information transferred between the
processor elements is ensured by parity checks and a comparison of the stored
information with information stored in another location. Most critical information has a parity indicator appended to it during the transfer. The checks performed on the VAX. 8650 processor elements include cache memory parity
checks, control store parity checks, general purpose register checks, internal
bus parity checks, Ebox arithmetic parity checks, and control RAM parity
checks. Each of the checks is described in the following paragraphs .
• CACHE MEMORY PARI1Y CHECKS
When single-bit errors are detected during data transfers from the cache memory, the data is transferred with an indicator specifying that the data contains an
error. A cache correction cycle is initiated to correct the single-bit error and to
rewrite the corrected data into the cache memory. The logic element that
requested the data issues a processor-interrupt request and a machine-check
stack frame is generated. The instruction is re-executed and the corrected data
is then accessed .
• CONTROL STORE PARI1Y CHECKS
Single-bit errors associated with the control store logic of a controlling
microprocessors in the processor can be corrected. When a control store parity
error is detected, the processor is halted and the data containing the error is
transferred to the console subsystem and corrected by the console ECC
software. Then the microword is rewritten into the control store location and
the instruction is automatically reissued without causing a fatal halt condition of
the processor. \X'hen an Mbox parity error is detected, the bit in error is identified and recorded. However, the processor does not recover and resume
operations.

3-27

• GENERAL PURPOSE REGISTER CHECKS
Single-bit parity errors associated with the general purpose registers (GPRs) are
correctable. Because of the multiple sets of GPRs in the VAX 8650, if an error is
detected in the information stored in one GPR set, a copy of the information
from a valid GPR is written into the GPR that contains the error.
• INTERNAL BUS PARI1Y CHECKS
Parity is generated on the information transferred through the internal processor buses. The parity is produced and checked on 8-bit bytes and on 32-bit
words on some of the buses.
• EBOX ARITHMETIC UNIT PARI1Y CHECKS
The Ebox contains three sets of arithmetic logic units (ALUs) that receive the
same inputs and perform the same functions. If the outputs of the·three ALUs
are not the same, a failure is recorded and the instruction is executed again.
• CONTROL RAM PARI1Y CHECKS
Parity checks are performed on the outputs of the control RAM to ensure that
the control functions are not in error.

Reliability and Maintainability Features
The design of the processor hardware includes many reliability and maintenance features such as:
• Socket-mounted RAMs - The RAM integrated circuits used on the VAX 8650
modules are mounted in sockets for easy removal and replacement. This feature eliminates the need to replace the entire module when a defective RAM is
located, resulting in lower maintenance costs and faster repair.
• Logic Partitioning - Logic functions are grouped together on modules so
that when a module is replaced due to a suspected failure, all the logic associated with that function is replaced.
• Cabinet Cooling - The processor cabinet allows conditioned air, ducted
through a raised floor, to enter through the bottom of the cabinet. The air
passes through the modules and the modular power supplies and is expelled
through a plenum at the top rear of the cabinet. The plenum chamber is muffled to keep the overall noise level within the acoustic limits of 60 decibels per
ampere.
• Multilayer printed circuit technology - Up to six layers of wiring are
required to interconnect the devices mounted on a printed circuit board. This
wiring is maintained at controlled impedance to guarantee signal integrity.
The backplanes contain 16 layers of printed wiring in a laminated structure.

The VAX 8550 and VAX 8500 processors share the same advanced design technologies as the top-of-the-line VAX 8800. Both the VAX 8550 and VAX 8500
offer cost-effective processing power in a compact package. While the VAX
8500 defines a new standard for midrange VAX computing, the VAX 8550
extends this standard to high-performance VAX computing in the same compact footprint.
The VAX 8500, VAX 8550, VAX 8700, and VAX 8800 are all implemented with
the VAXBI I/O subsystem and high-speed internal memory (MI) bus. The key
attribute of the VAX 8550 and VAX 8500 systems is that they offer more CPU
performance in less space than other systems offered by Digital.
The VAX 8550NAX 85OO's power, processor, memory, and primary I/O subsystems all fit in a 27-by-30-inch wide footprint. This efficient and cost-effective
packaging includes the processor and integral hot floating point, a single highspeed VAXBI I/O channel, and 20 Mbytes of main memory that can be
expanded to a total of 80 Mbytes. The second VAXBI channel and a VAXcluster
interface can be configured in an I/O expander cabinet.
Continuing the tradition that made VAX systems the standard for 32-bit
computing, VAX 8500 provides three times the performance of the VAX-11/780
and VAX 8550 performance is six times that of a VAX·1I/780. The VAX 8550
and VAX 8500 are designed for all compute environments not requiring the
more extensive expansion of the VAX 8700. The VAX 8500 also provides a
lower-cost entry with future upgrade to VAX 8550 as requirements expand.
Some of the features and benefits of these systems are:
• Fbwerful performance in compact packaging.
• Advanced VAX technology, including high-speed VAXBI I/O.
• Low-cost multiuser solution across a wide variety of applications.
• Cost -effective, incremental growth with VAXcluster configurations.
• Full networking capabilities with standard Ethernet port.
• Full VAXlVMS software compatibility.
Figure 4-1 identifies the VAX 8550NAX 8500 processors. Refer to Table 1-1 to
compare these systems to other Digital VAX and Micro VAX systems.

4-2 • VAX 8550 and VAX 8500 Processors

Figure 4-1 • VAX 8550 and VAX 8500 Processors

• VAX 8550 and VAX 8500 Physical Configuration
The VAX 8550NAX 8500's full complement of main memory, CPU modules,
one VAXBI channel and Ethernet port require only 5.6 square feet of floorspace.
These systems require less input power (57%), dissipate less heat (51%), and
take up less space (66% ) than the VAX-1l1780. A new 22 layer backplane, innovative power supply distribution methods, and simplified internal cabling make
the VAX 8550NAX 8500 processors one of the most reliable and easy to maintain systems in their class. These air-cooled systems are based on a clean internal
design with airflow patterns contributing to their noticeably low noise level.
Figure4-2 shows the physical dimensions of the VMS version of both processor
cabinets. Figure 4-3 shows a stand-alone configuration of the processors, and
Figure 4-4 shows the VAXcluster configuration.

4-3

152 em
(60 in)

.........
Figure 4-2 • VAX 8550 and VAX 8500 Cabinet Dimensions

Cooling Assembly

Power Supply

CPU

Memory
Controller

::;

. ~(
~

't:

Space for
additional

VAXBI
adapters

~t~
~..c:~

~ L- LC

L--

Power

Power
Controller

Input

Figure 4-3· VAX 8550 and VAX 8500 Processor VMS Stand-alone Configuration

4-4 • VAX 8550 and VAX 8500 Processors

COOLING ASSEMBLY

CI PORT
POWER SUPPLY

SPACE FOR

n
~PU

MEMORY

~w u~

>CONTROLLER Z

p-~

I-

ADDITIONAL

VAXBI
ADAPTERS

tli ....

"' z ~

~ ti:i~ >~

SPACE FOR
BA11-ADA
BA32-B

POWER

INPUT

CONTROLLER

Figure 4-4 • VAX 8550 and VAX 8500 Processor VAXcluster Configuration

• VAX 8550 and VAX 8500 Processor Organization
The VAX 8550 and VAX 8500 procesSors are functionally identical to the VAX
8700 processor_ Therefore, descriptions of the VAX 8700NAX 8800 processors
in Chapter 2 are rdevant for the VAX 8550NAX 8500 processors_
The major differences between the systems are:
• VAX 8550NAX 8500 have a smaller footprint than the VAX 8800NAX 8700_

• The VAX 8550NAX 8500 have a five-slot memory backplane; the VAX 8800/
VAX 8700 have an eight-slot memory backplane.
• The VAX 8550NAX 8500 have one NBIA module supporting a maximum of
two VAXBIs; the VAX 8800NAX 8700 have two, supporting four VAXBIs.

4-5

The similarities between the systems are:
• The console subsystem hardware is identical.
• All systems use the same tools and test equipment.
• Console code differences are transparent, contained in the same set of
software.
• The modular power supplies (MPS) are identical.
Figure 4-5 is a block diagram of the VAX 8550 and VAX 8500 Processors. It may
be compared to the VAX 8700 and VAX 8800 system configurations shown in
Figures 2-4 and 2-5, respectively.

MEMORY
14 MB CARDS)
VAX
PROCESSOR
ISTANDARD)

HIGH-SPEED MEMORY INTERCONNECT BUS

----,
1
1

r--- L --,
BAXBI
I/O BUS
ISTANDARD)

VAXBI
'
'
I/O BUS
I
: 10PTIONAL) :
L __ """,", __ J
I
I

L,' ~
121
I I
~ '-7
v

, ,

Figure 4-5 • VAX 8550 Processor Configuration

4-6 • VAX 8550 and VAX 8500 Processors

Main Memory
The VAX 8550NAX 8500 systems have 20 Mbytes ofECC memory composed of
256-bit dynamic RAM chips arranged in 4-Mbyte arrays. The memory is totally
contained in the CPU cabinet and has a three-way interleaving controller with a
memory array bus that provides a bandwidth of over 50 Mbytes per second.
Individual4-Mbyte and 16-Mbyte memory boards can be added up to a system
maximum of 80 Mbytes.

VAXBI I/O Subsystem
The VAX 8550NAX 8500 systems use the VAXBI bus for liD. One VAXBI channd with five usable slots is standard with an option to expand to a maximum of
two channels. With each channd capable of usable data rates of up to six times
the UNffiUS, it is possible for the VAX 8550NAX 8500 systems to achieve aggregate data rates of up to 16 Mbytes-per-second using two VAXBI channels. The
high liD bandwidth, rdiability features, and inherent programmable features of
the VAXBI make it ideally suited for high-performance peripherals and liD
intensive applications.
Many liD devices on the VAX 8550 and VAX 8500 connect directly to the
VAXBI. Native VAXBI interfaces include:
• Ethernet Ibrt (standard)
• VAXcluster Ibrt
• Disk Adapter (KDB50)
• Thpe Adapter (TU81-plus)
• Multifunction Communications Controller (DMB32)

UNIBUS Support for VAX 8500 and VAX 8550 Systems
The optional VAXBI to UNffiUS adapter (DWBUA) is available on both the VAX
8500 and VAX 8550 to aid in the migration of traditional UNffiUS devices. This
option is available for new system orders and for fidd upgrades to existing VAX
Systems.

Digital Networks and VAXcluster Systems
The VAX 8550NAX 8500 systems include a VAXBI-to-Ethernet port as a standard feature. Ethernet is the recommended terminal and workstation communications method because its high-performance and extensive connectivity
complements the performance capabilities of the VAX computers. Ethernet terminal servers should be used to attach terminals to the VAX 8550NAX 8500s.

4-7

The VAX 8550 and VAX 8500 VAXcluster building blocks offer a standard VAXcluster port and the required adjacent expander cabinet. This allows the VAX
8550NAX 8500 to be confJ.gured immediately into VAXcluster Systems, bringing to VAXclusters compact high-performance compute nodes. Check with
your Digital sales representative for stand-alone VAX 8500 and VAX 8550 system upgrades to VAXcluster Systems.

• Reliability, Availability, and Maintainability
The VAX 8550 and VAX 8500 systems share all of the maintainability and reliability features of the top-of-the-line VAX 8800 system. ECL machines operating
at cycle time of 45 nanoseconds, the VAX 8550NAX 8500 are the fastest systems
in their class. The memory subsystem is served by a technology-independent
memory controller that eliminates the need for controller changes when new
memory technologies become available.
The VAX 8550NAX 85OO's highly intelligent console system is a J-11 chip minicomputer with video interface, 1 Mbyte of memory, 30-Mbyte Winchester
Disk, 800-Kbyte floppy disk drive and a remote diagnosis port. System
powerup, diagnostics, monitoring, and control can be performed quickly and
efficiendy via a realtime interface to the CPU. An environmental monitoring
subsystem within the CPU cabinet monitors temperatures in voltages throughout the CPU and continuously reports status conditions via the console. Electronically keyed modules allow the console to perform automatic hardware and
software revision compatibility checks as well as checks for correct module
placement.
Designed for high reliability, both systems use custom and semicustom semiconductor devices, a 22-layer backplane, ZIF (Zero Insertion Force) connectors, and 9-layer logic modules. Extensive parity and data integrity protection
has been implemented throughout the various buses, cache memory, data buffers, and RAMs.
The VAXBI also enhances system reliability through the following features:
• All of the bus interface logic is compressed into a single integrated circuit, the
VAXBI Interface Chip (BIIC).
• Because there are no cables on any VAXBI modules, maintenance is simplified
and reliability is enhanced.
• BIIC contains complete self-test capabilities.
• Extensive error detection and logging logic is included in the VAXBI.
• Reliability has been proven by complete specification, simulation, and verification of the whole VAXBI.

The VAX 8200 and VAX 8300 processors are the kernels of Digital's midtange
VAX Systems. These processors combine the latest developments in custom
MOS VLSI (Metal Oxide Semiconductor, Very-Large Scale Integrated) circuit
technology with the high-speed performance and multiprocessing capabilities
of the VAXBI bus.
VAX 8200/8300 systems are distinguished by their ability to provide large system performance and functions at midrange processor prices. The VAX 8200
delivers VAX-Iln80 performance at approximately half the price. It can be easily upgraded to a VAX 8300. The VAX 8300, with nearly twice the computational
power of the VAX 8200, is especially appropriate for applications that are computationally intensive. With two processors, it offers a more cost-effective solution than the single processor VAX 8200 system for most applications
demanding as little as 30 to 40 percent performance improvement. And, of
course; both systems offer VAXduster and UNIBUS support.
VAX 8200 systems support two general purpose, timesharing operating systems
- VMS and ULTRIX-32. VAX 8300 systems support VMS only. Some of the features and benefits of the VAX 8200/8300 systems are:
• Big-system features in a small footprint.
• Economical additions to your VAXduster System.
• High VO throughput based on the VAXBI bus for balanced processor and Vo
performance.
• Higher compute performance with the complete VAX instruction set in
advanced VLSI circuitry.

• PDP-ll compatibility as an option in the form of VMS-layered emulation
software.
• Easy expansion from the VAX 8200 (one central processor, 8-Kbyte cache) to
the VAX 8300 (two processors, total of 16-Kbytes of cache).

5-2 • VAX 8200 and 8300 Processors

Figure 5-1 • VAX 8200 and VAX 8300 Processors

In the following sections differences between the VAX 8200 and VAX 8300 are
noted and explained. For performance specifications refer to Appendix A and
the system comparison chart in Chapter 1 (Figure 1-1).

5-3

• VAX 8200/8300 System Configurations
VAX 8200 and VAX 8300 systems are housed in a cabinet that contains the
VAXBI bus and the components that plug into the it - processors, memories,
and 110 adapters. See Figure 5-2. The processor cabinet also contains its power
subsystem, a 5.25-inch diskette drive, standard corporate bulkhead connector
panels, and space for the memory's battery backup option. The cabinet can
hold twelve VAXBI modules and has one power supply.
VAX 8300

RX'i(j
Load
Device

VAXIl]
Backplane

1I!\I l·!\\X'u\X)

UNIBUS Expansion
Cabinet

VAX 8300 CPU
Cabinet

r
panel
I-- One
Unit

~~=
-;7
'rI/

'rI

r-'

'rI

Power controller

(Rear View)

Figure 5-2 • Processor Cabinet

'It

Power
controller

5-4 • VAX 8200 and 8300 Processors

UNIBUS support for VAX 8200 and VAX 8300 systems includes a BAll-&!/AZ
expander box mounted in an adjacent cabinet shown in Figure 5-3. The VAXcluster interface is also mounted in a similar but separate cabinet.

Space For
BA11-K or

BA11-A

One
Panel Unit

(Rear View)

Power
Controller

Figure 5-3 • UNIBUS Expander Cabinet

5-5

VAX 8200/8300 systems are also available in the rackmount box shown in Figure 5-4. This box provides technical OEMs the most versatile VAX packaging yet
for embedded applications.

Figure 5-4 • VAX 8200 and VAX 8300 Rackmount Box

The VAX 8200 System has one processor. The VAX 8300 System has two. Otherwise, both systems are functionally identical. Figures 5-5 and 5-6 give an overview of VAX 8200/8300 systems. The systems contain a processor, ECC memory
modules, a second processor (with the VAX 8300), and a VAXcluster adapter or
a disk adapter.
The processors are connected to memory by the VAXBI bus that also serves as
the input/output bus for communications and storage peripherals. These are
connected to the VAXBI bus with a variety ofVAXBI adapters and interfaces.
An Ethernet adapter is standard with both systems. Optional adapters are available for a TU81-plus magnetic tape drive and a multifunction adapter with synchronous and asynchronous serial lines and a printer port. Additional functions
are provided by UNIBUS peripherals.
The console subsystem includes a serial-line interface for the console terminal,
control panel, and an interface for the console load (diskette) device.

5-6 • VAX 8200 and 8300 Processors

-r----'-_-< RX50

r--

VAXcluster

PORT

l _____ --l
FOR

VAXcluster
SYSTEMS

Figure 5-5 • VAX 8200 System Configuration

--< RX50

r--

VAXcluster

PORT

l _____ --l
FOR
VAXcluster
SYSTEMS

Figure 5-6 • VAX 8300 System Configuration

5-7

The configurations attainable with the VAX 8200 and VAX 8300 Systems are
many and cannot be described here for practical reasons. There are a multitude
of considerations when configuring a system - number of disk and tape drives,
connections to local area networks, connections to wide area networks, and
VAXclusters. Your local Digital representative has the information needed to
configure a system best suited for your unique application.
The configurations attainable with the VAX 8200 and VAX 8300 Systems are
many and cannot be described here for practical reasons. There are a multitude
of considerations when configuring a system - number of disk and tape drives,
connections to local area networks, connections to wide area networks, and
VAXclusters. Your local Digital representative has the information needed to
configure a system best suited for your unique application.
Console Subsystem
The console subsystem, included with each system, enables the system user,
manager, and maintenance engineer to communicate with the processor
through the console terminal and console command language. Console subsystem design is governed by the Vl';X Architecture. Both the architecture and the
console subsystem are described in the VAX Hardware Handbook Volume 1 1986. \blume 1 also includes an overview of VAX console subsystems and the
Console Command Language.

Processor microcode emulates the control-panel lights and switches of traditional computer systems with an ASCII console. The console subsystem functions are compatible with those of other VAX consoles. They allow you to
• Bootstrap the system.
• Examine and deposit data in registers and in memory.
• Run stand-alone programs without use of the operating system.
• Single step through VAX macrocode.
• Start and stop the processor.
• Test the hardware with the self-test microcode and macrodiagnostic
programs.
The console subsystem performs these functions from a hardcopy terminal.
Both processors of the VAX 8300 are controlled by a single console subsystem.
The console is always in one of three states when power is on - Program I/O
mode, Console mode, or Halted with Console Disabled.

5-8 • VAX 8200 and 8300 Processors

• Central Processing Unit
The KA820 processor module is Digital's densest VLSI processor design to date.
Equivalent to the 24-module VAX-lln80 processor, the KA820 is implemented
on a single module with 8 custom VLSI chips that are the design equivalent of
over 1.3 million transistors. Integral acceleration of D, F, and G floating-point
instructions processing is standard.
Additional processor features include an asynchronous serial line for the console terminal, three low-speed serial lines for general use, and the interface to
the console load device.

CPU Section
The block diagram of the KA820 module, shown in Figure 5-7, depicts the
functional division of the CPU, VAXBI Interface, and Ibrt Controller sections.
Three chips carry out processor functions according to 40-bit microinstructions
stored in the control store chips. The InstructionlExecution chip is used for
instruction decoding and execution. The Memory Interface chip is used for
memory management, processor registers, and four serial-line units. The F chip
is the floating point accelerator.
An onboard translation buffer caches address translation data (called page
table entries or PTEs) for 512 pages of memory. The backup translation buffer
parallels the minitranslation buffer in the lIE chip. And an onboard data cache
holds data from the most recently accessed locations in memory.
SERIAL-LINE 0

SERIAL-LINE 1

CONTROL
STORE

CPU ClK
OSCILLATOR

SERIAL-LINE 2

SERIAL-LINE 3

Figure 5-7 • KA820 Processor Block Diagram

5-9

• INSTRUCTIONIEXECUTION (lIE) CIllP
The instruction/execution (IIE) chip is divided into four areas - instruction
buffer, microsequencer, execution unit, and minitranslation buffer.

INSTRUCTION BUFFER - The instruction buffer is a silo that holds up to
eight bytes of prefetched VAX instructions. The CPU can execute sequences of
instructions rapidly without waiting for memory read cycles to fetch instructions. The hardware tries to keep the instruction buffer full. The instruction
buffer initiates a read function when it is not full and there is no other activity on
the DAL bus that takes precedence. In addition, the instruction buffer sends
information it gathers from decoding VAX instructions to the execution unit
and the F chip.

MICROSEQUENCER - The microsequencer determines the address of the
next microinstruction to be executed (with two exceptions - at the beginning
of a VAX instruction, and when the first part done flag is set following an interrupt or exception). When a new VAX instruction is being decoded, the
microaddress generator determines the entry point of the microroutine to be
executed. During the first half of the CPU clock cycle, the IIE chip drives the
microaddress over the microinstruction bus. During the second half of the CPU
clock cycle, the control store sends the addressed microinstruction word on the
MIB bus to the execution unit. This prefetch function assures that the execution
unit never waits for a microinstruction. A new microinstruction is available at
the beginning of each 200-nanosecond CPU clock cycle.

EXECUTION UNIT - The execution unit contains 16 general purpose registers
(RO--R15), the arithmetic and logic units, the shifter, and data paths. It executes
the microinstructions needed to implement the macroinstructions in the
instruction buffer; move data and addresses to and from the registers; and
move data and addresses on the DAL bus to the F and memory interface chips,
backup translation buffer, cache, and port controller. When the execution unit
derives a virtual address to be accessed, it sends that address to the minitranslation buffer for translation to a physical address.

5-10 • VAX 8200 and 8300 Processors

MINITRANSLATION BUFFER - The minitranslation buffer (MTB) caches
physical address translations for five pages of virtual memory - four datastream pages and one instruction-stream page. The information for each
address translation is called a page table entry (PTE). Each MTB location contains a tag and a page table entry. The tag tells whether there is a valid page table
entry in the MTB for a given virtual address. The page table entry includes a
21-bit page frame number identifying the 512-byte page of physical memory to
be used on references to the virtual address. With valid page table entries, the
MTB generates the physical address from the valid entry and make the physical
address available on the DAL bus without delay.
• MEMORY INTERFACE (M) CHIP
The memory interface (M) chip functions complement the instruction/execution (VE) chip functions. They include
• Backup translation buffer tag store.
• Cache tag store.
• Internal processor register (IPR) implementation.
• Interrupt handling.
• Memory management.
• Processor clock generation.
• Serial-line unit implementation.
• Ibrt controller interface.
The four RS423-compatible serial-line units on the memory interface chip connect tenninals directly to the processor. Signal lines from the serial-line units are
converted to the standard RS232 fonnat off the module. You can set the baud
rate of each serial-line unit separately by writing a location in the EEPROM or by
writing to the appropriate transmit control and status (TXCS) register.
The baud rate on serial-line unit 0 can be changed, when the primary processor
is in the console mode, by pressing the <BREAK> key on the console terminal.
Available baud rates range from 150 to 19,200.
Each of the four serial-line units is implemented in a universal asynchronous
receiver/transmitter (DART) in the memory interface chip. Each DART makes
four privileged processor registers available to software - the Receive Control
and Status Register, the Receive Data Buffer, the transmit Control and Status
Register, and the transmit Data Buffer.
The serial-line units are full duplex. They transmit and receive data simultaneously. When interrupts are enabled, character transfer occurs one byte at a time.
And each serial-line unit interrupts the processor at interrupt priority level (IPL)
14(hex) every time it receives or transmits a character.

5-11

• FLOATING POINT ACCELERA1DR (F) CHIP
The floating-point accelerator (F chip) increases the arithmetic efficiency of the
processor by speeding up execution of the integer and floating point arithmetic
instructions:
• ADD (F, D, G)

• CMP (F, D, G)
• CVTL (F, D, G)

• DN (F,D,G)
• EDN
• EMUL
• MUL (F, D, G)
• POLY (F, D, G)
• SUB (F, D, G)

The accelerator chip operates in parallel with the instruction/execution chip.
The instruction/execution chip makes decisions concerning the instruction
being executed. The accelerator chip performs the calculations required for the
instruction being executed.
The microinstruction bus supplies the accelerator chip with VAX opcodes and
microinstructions. The opcodes come from the instruction/execution chip and
microinstructions from control store. The data address line bus carries operand
data between the accelerator chip and memory or the instruction/execution
chip's general purpose registers .

• CONTROL S1DRE
Control store is an onboard memory that is used to store microcode that
• Controls VAX instruction execution.
• Invokes processor initialization, bootstrapping, and console functions.
• Ferforms processor self-test.
Control store consists of a 15-Kword by 40-bit ROM plus a I-Kword by 40-bit
ROM implemented in five ROMIRAM chips and protected by parity. The RAM
stores microcode patches, making microcode changes as simple as software
changes. Control store and the processor chip set are connected by the microinstruction bus (MIB) that is protected by parity checking.

5-12 • VAX 8200 and 8300 Processors

• BACKUP TRANSLATION BUFFER
There are two translation buffers - the minitranslation buffer described above
and the backup translation buffer. The minitranslation buffer caches five physical address translations called page table entries while the backup translation
buffer caches 512 page table entries. A cache hit in the minitranslation buffer
incurs no delay, while a cache miss in the minitranslation buffer, which leads to
a cache hit in the backup translation buffer, incurs a 200 nanosecond delay.
The backup translation buffer has two storage locations. The memory interface
chip is the tag storage location, and the backup translation buffer RAMs store
the page table entries .

• CACHERAM
The cache memory is a direct-mapped write-through design. It consists of an
8-Kbyte array divided into 128 blocks of 64 bytes each. The cache RAM stores
copies of data from main memory. A large and fast cache RAM helps increase
system performance when processing large jobs. The CPU uses the portions of
main memory stored in cache RAM to reduce response time.
Like main memory, the cache RAM uses physical addresses to access the data.
The cache tag store contains 128 tags - one for each block of data. Each tag
includes 16 bits of a physical address with a parity bit and 4 valid bits with a
parity bit. The 4 valid bits apply to the four octawords within a block of cache
data.

VAXBI Interface Section
The VAXBI interface consists of the 32-bit, parity-protected BCI bus and the bus
interconnect interface chip (Bile). The BIlC implements the VAXBI bus protocol including a distributed arbitration scheme and bus error checking facilities.

Port Controller Section
The port controller and dedicated port controller interface (PCI) bus devices
make up a third section of the KA820 module. The port controller buffers the
transfer of addresses and data between the CPU and the PCI bus devices as well
as between the CPU and the VAXBI interface.
The EEPROM is a 16 Kbyte nonvolatile memory on the PCI bus. It stores
choices for KA820 options, VAX bootstrap macrocode, and the patches for control store microcode. A write protection circuit prevents the stored data from
being changed accidentally. Microcode copies the bootstrap macrocode to an 8
Kbyte boot RAM on the PCI bus at the beginning of the boot process.
The electrically erasable programmable read-only memory (EEPROM) on the
PCI bus contains 16 Kbytes of information defining options, the physical configuration, microcode patches, and VAX boot code. The data in the EEPROM
remains valid if power is removed. When power is restored, EEPROM data is
used by the microcode to initialize the processor and boot the system.

5-13

Digital distributes updates for the EEPROM with software and microcode
patches on diskettes. The EEPROM utility is used to load update data into the
EEPROM.
The PCI bus also runs off the KA820 module to connect to the battery-backedup watch chip and the RX50 disketted drive controller (RCX50). The watch
chip keeps the time of year for up to 100 hours without system power. The
RX50 diskette drive is used to install software and microcode updates.
Main Memory
Main memory for VAX 8200 and VAX 8300 Systems is available in 2- or
4-megabyte boards. Both implement an advanced design that encompasses
data, address, error correction and control logic within three complex CMOS
(VLSI) gate arrays on the memory array board. Easy, cost-effective memory
expansion is available in 2 Mbyte or 4 Mbyte increments.
Onboard memory logic eliminates the need for a separate memory controller.
Operating on the VAXBI bus as a slave only, MS820 memory modules interface
by way of the onboard BITe. Onboard logic provides an aggregate I/O write
bandwidth of up to 13.3 megabytes per second, an aggregate 1/0 read
bandwidth of up to 10.0 megabytes per second, and up to 11.4 megabyte per
second single device write bandwidth. Internal onboard interleaving between
the two memory banks on the MS820 memory module improves system
throughput and performance.
The 4-Mbyte MS820-B memory array uses the latest double-sided surfacemount technology. It uses 256 kilobit plastic leaded chip carrier (PLCC)
dynamic RAMs mounted on both sides of a single VAXBI module. The 2-Mbyte
MS820-A memory array uses 256 kilobit dual-inline-package (DIP) dynamic
RAMS. Both modules use error correction code (ECC) to detect double-bit
errors and to correct single-bit errors.
Maximum memory size in the 12-slot processor cabinet or in the rackmount
box is 24 Mbytes. Maximum memory size in the 24-slot processor cabinet is 24
Mbytes with battery backup, or 48 Mbytes without battery backup. Memory in
a VAX 8300 system is fully sharable between the two processors.
The H7231 battery back-up option provides protection from a temporary
power outage by maintaining the contents of main memory for about ten
minutes.

Power Subsystem
The VAX 8200 power supply is a high-frequency, hybrid, switching power supply. The unit contains nine regulated outputs for a total output power of 593
watts. The power supply has three main modules. Each module plugs into a slot
on the power distribution board. The power supply has a volume of approximately 803 cubic inches and weighs 15 pounds.

5-14 • VAX 8200 and 8300 Processors
One power supply is used in the processor cabinet and in the rackmount box.
Input power can be 120 ~c at 60 hertz or 240 ~c at 50 hertz. The power
supply is UL recognized, CSA certified, and VDE compliant.

Input/output Subsystem
VAX processors connect to peripheral devices, nerworks, and other VAX processors through the input/output (I/O) subsystems. These subsystems electrically
connect the devices to memory, permitting fast and reliable transfer of
information.
Both the VAX 8200 and the VAX 8300 use the VAXBI bus for I/O. For a technical
description of the bus and the variety of disk, communication, network, and
cluster adapters available as options, please refer to the VAXBI Options

Handbook.
Mass Storage Subsystems
Digital offers a complete line of intelligent mass storage subsystems and storage
devices designed specifically to operate with VAX processors and VAXcluster
architecture. These subsystems and devices allow a user to select the mass-storage requirements that best suit the system application and to add storage capabilities when application requirements increase.
.
Chapter 7 of this volume includes a brief description of the KDB50 Disk
Adapter and the HSC70 Intelligent I/O Server. The KDB50 is more fully
described in the VAXBI Options Handbook. The VAX Systems and Options
Catalog also provides detailed device descriptions, configuring information,
and ordering codes.
Architectural information on mass storage subsystems can be found in VAX
Hardware Handbook Volume 1 - 1986 and the Storage Systems Handbook.

• Reliability, Accessibility, and Maintainability
The VAX 8200 and VAX 8300 are the most reliable and maintainable midrange
VAX systems ever offered.
Central processor features that provide fault tolerance, error detection and
diagnostics include
• 5 Kwords of self-test microcode
• Cache and translation buffer parity
• Microinstruction retry
• Microcode check sum
• Microcode parity

5-15

At the processor-component level, maximum use of VLSI circuit technology
results in considerably fewer parts. For example, the VAX 8200 processor is
mounted on one module as opposed to 24 on the VAX-1l/780. Many electronic
components are preconditioned prior to insertion to preclude the malfunctioning of an uncured component. And ECC memories and most VAXBI devices are
implemented on single modules to increase system reliability_
The carefully-engineered power supply and packaging enhance the inherent
reliability of VAX 8200 and VAX 8300 systems. Important features include
• The new VAXBI ZIF (Zero Insertion Force) connectors that provide easy
insertion and removal of modules.
• Air flow monitoring.
• Ibwer supply thermal monitoring.
• Module and control panel LEDs for self-test reporting.
• Backplane slot independence.
• All cable and intermodule connections by way of the backplane (no cables
attached to modules).
The integrity of data and processes are protected by checking extensively for
• Parity errors
• VAXBI transaction errors

• Unforeseen microcode conditions
• Interrupts occurring at unexpected levels
The machine-check function is invoked following detection of a hardware
error. The machine check passes control to appropriate exception-handling
software. This lets the software evaluate the situation and respond appropriately. In addition, the KA820 module uses a microcode-based ASCII console
and provides a serial-line unit that connects the console terminal to the KA820.
The KA820 module contains a self-test microcoded program. The program can
be invoked manually or automatically. A console command is used to invoke it
manually. When power is applied to the system, the program is invoked
automatically.

5-16 • VAX 8200 and 8300 Processors

Battery Backup Unit
The battery backup unit (BBU) option preseJ;Ves memory content during a public utility power failure. The BBU is capable of supporting the memory modules
for about ten minutes from a fully charged battery. It is intended to provide
power for the memory modules during short-tertn power losses that occasionally occur. Battery mode is entered automatically when public utility power is
interrupted. When system power is restored, normal operation is resumed.

Cooling Subsystem Monitoring
The processor cabinet is equipped with an air filter and an air-flow sensor. The
sensor is mounted behind the backplane interconnect cage and in front of the
power supply modules. The signal from the air-flow sensor is delayed by the
sensor before going high if no air flow is detected. This allows the VAX to
powerup. If no air flow is detected, the ac circuit breaker in the power supply is
ttipped, safely shutting down the VAX.

Error Correction Code
MS820 main memory has 7 check bits per 32 data bits to provide single-bit error
correction and full double-bit error detection. The memory error correction
code (ECC) automatically corrects single-bit errors and detects double-bit
memory errors. Detections and corrections are noted in the error log as a preventive maintenance aid.

Se1f-test Routine
In order to ensure the system is functioning properly, a self-test routine runs
automatically whenever you apply power or when a command is entered from
the console. The routine verifies that the CPU hardware and the VAXBI nodes
are functioning.
Two basic areas of the system are tested - the processor and the nodes on the
VAXBI bus. The VAXBI bus connects each processor to options such as va controllers, bus adapters, memory arrays, and other processors. Each of these
VAXBI options has its own self-test routine.
• PROCESSOR SELF-TEST ROUTINE
The self-test routine has two speeds - nortnal and fast. Speed is selected by the
initiator or user. In most situations, the normal test is used. The test takes 10
seconds and gives maximum coverage to system hardware. The fast self-test
takes 025 second but checks only the cache memory and the F chip. The fast
self-test is intended for realtime applications during recovering from a public
utility power failure.
Characters printed on the console terminal, the FAULT light on the conttol
panel, and lights in the processor cabinet indicate the status of the self-test.
When the self-test routine begins, all indicators report simultaneously.

5-17
As each section of the CPU hardware passes the test, a letter appears on the
terminal. A different letter is assigned to each section of the CPU. Each CPU
module has a red light that is on while the CPU self-test routine is running. The
light turns off if the CPU passes the test. It the CPU fails the test, the red light
stays on.
• MEMORY SELF-TEST ROUTINE
The MS820 memory array module performs a self-test on powerup. During selftest, the MS820 tests the BIIC, ECC logic, address and control gate array, datapath gate arrays, and the MOS RAMs. Initialization is performed at the conclusion of the self-test for a cold powerup, but initialization is not performed for a
warm restart. Initialization clears memory.
Self-test and initialization takes about 5 seconds on the MS820-B module and
about 3 seconds on the MS820-A module. Self-test without initialization, performed from a warm powerup, takes less than 0.25 seconds for either module.

Zero Insertion Force (ZIF) Connectors
System modules are connected to the VAXBI backplane by ZIF (Zero Insertion
Force) connectors that are surface mounted to a backplane. ZIF connectors are
keyed to ensure that backplane interconnect modules cannot be inserted
upside down and also that the modules are positively seated. This ensures
proper installation and prevents damage to both the module and the other
components.

The VAX processor register space provides access to CPU control and status
registers such as memory management base registers, processor status
longword, and multiple stack-pointer registers. The VAX privileged registers are
accessible only by move to processor register (M1PR) and move from processor
register (MFPR) instructions, which are controlled by the kernel executive in the
VMS operating system. The operating system manages these registers for the
user; however, they are available to system programmers, operators, and maintenance personnel.
This chapter highlights the architecturally defined registers common to all VAX
systems, the VAXBI registers, and the processor specific registers for the VAX
8800/8700, 8650, 8550/8500, and VAX 8300/8200 systems. Note that references to Volume 1 in the text refer to the VAX Hardware Handbook Volume 1 -

1986.

• Architectural Processor Registers
Thble 6-1 lists the architectural processor registers by name, abbreviation, and
address. Format for the system identification (SID) register and bit values for
the VAX 8800/8700, 8650, 8550/8500, and 8300/8200 are shown in the figures
below. Formats for the other VAX architectural registers are found in \blume 1,
Chapter 10.

Thble 6-1 • VAX Architectural Processor Registers
Register Name

Abbreviation

Kernel Stack Ibinter
Executive Stack Ibinter
Supervisor Stack Ibinter
User Stack Ibinter
Interrupt Stack Ibinter
PO Base
PO Length
PI Base
PI Length
System Base
System Length
Process Control Block Base
System Control Block Base

KSP
ESP
SSP
USP
ISP
POBR
POLR
PIBR
PILR
SBR
SLR
PCBB
SCBB

Address
00

01
02
03
04
08
09
OA
OB

OC
OD
10
11
(continued on next page)

6-2 • VAX Privileged Registers

Table 6-1· VAX ArchitecturalProcessor Registers (Cont.)·
Register Name

Abbreviation

Address

Interrupt Priority Level
Asynchronous System 'llap Level
Software Interrupt Request
Software Interrupt Summary
Interval Clock Control/Status
Next Interval Count
Interval Count
Time-of-year
Console Receive Control/Status
Console Receive Data Buffer
Console 'llansmit Control/Status
Console 'llansmit Data Buffer
Machine Check Status
Memory Management Enable
'llanslation Buffer Invalidate All
'llanslation Buffer Invalidate Single
Ferformance Monitor Enable
System Identification
'llanslation Buffer Check

IPL
ASTLVL
SIRR
SISR
ICCS
NICR
ICR
IDDR
RXCS
RXDB
TXCS
DmB
MCSTS
MAPEN

12
13
14
15
18
19

TElA

TBIS
PME
SID
TBCHK

1B
20
21
22
23
26
38
39
3A
3D
3E
3F

System Identification Register
The system identification (SID) register specifies the VAX processor type and the
hardware and software revision levels used in a particular processor. These values are included in the error log. The type field may be used by software to
distinguish processor types.
Figure 6-1 shows two SID registers - one for the VAX 8800/8700 and 8550/
8500 systems, and one for the VAX 8300/8200 systems. The VAX 8650 uses the
VAX 8600 SID register format shown in Volume 1, page 10-3.

242322

16 15

PROCESSOR TYPE

LEFTIRIGHT PROCESSOR
PROCESSOR REVISION

SYSTEM SERIAL NUMBER

Figure 6-1 • VAX 8800/8700 and VAX 8550/8500 SID Register Format

6-3
31

2423

PROCESSOR TYPE

1918

PROCESSOR REVISION CODE

98 7

MICROCODE PATCH REVISION LEVEL
SECONDARY PATCH BIT
CONTROL STORE ROM/RAM REVISION LEVEL

Figure 6,2 • VAX 8300/8200 SID Register Format

• VAXBI Registers
Each VAXBI node is required to implement a minimum set of registers contained in specific locations within the node's nodespace. Table 6-2 lists the
VAXBI registers and their addresses. All but the Slave-only Status register and
the Receive Console Data register are on the BIle.

Thble 6-2 • VAXBI Registers
Register N arne

Abbreviation

Address

Device
VAXBI Control and Status
Bus Error
Error Interrupt Control
Interrupt Destination
IPINTRMask
Force-bit IPINTRlS1DP Destination
IPINTR Source
Starting Address
Ending Address
BCI Control and Status
Write Status
Force-bit IPINTRlS1DP Command
User Interface Interrupt Control
General Purpose Register 0
General Purpose Register 1
General Purpose Register 2
General Purpose Register 3
Slave-only Status
Receive Console Data

D1YPE
VAXBICSR
BER
EINTRCSR
INTRDES
IPINTRMSK
FIPSDES
IPINTRSRC
SADR
EADR
BCICSR
WSTAT
FIPSCMD
UINTRCSR
GPRO
GPR1
GPR2
GPR3
SOSR
RXCD

bb + 00"
bb + 04
bb + 08
bb + OC
bb + 10
bb + 14
bb + 18
bb + 1C
bb + 20
bb + 24
bb + 28
bb + 2C
bb + 30
bb + 40
bb + FO
bb + F4
bb + F8
bb + FC
bb + 100
bb + 200

"The abbreviation bb refers to the base address of a node; that is, the address of the first
location of the nodespace.

6-4 " VAX Privileged Registers

Device Register
The device register contains a device type field and a device revision field. The
device revision field identifies the revision level of the device. The device type
field identifies the type of node.

bb+O

~r_l

16~1~1_5

______D_EV_I_CE
__
RE_V_IS_IO_N_______

O~I

_______D_E_V_IC_E_TI_P_E________

Figure 6-3 " Device Register
VAXBI Control and Status Register
The VAXBI control and status register provides control and status information
about the VAXBI bus. Control information output to this register can enable
interrupts, change the arbitration mode, or perform a desired function. Status
information input from this register includes the type and revision level of the
primary interface to the VAXBI bus, error and error type, and read for or done
with operation information.

2423

bb + 41
VAXBI INTERFACE REVISION
VAXBIINTERFACE TIPE

1111111 1111

161514131211109876543

HARD ERROR SUMMARY
SOFT ERROR SUMMARY
INITIALIZE
BROKE
SELF-TEST STATUS
NODE RESET
UNLOCK WRITE PENDING
HARD ERROR INTR ENABLE
SOFT ERROR INTR ENABLE
ARBITRATION CONTROL
NODE 10

Figure 6-4" VAXBI Control and Status Register

ITtd=
~

3130292827262524232221201918171615

bb + 8

101 1111111 1111

II II

4 3 2 1

11111

~ ~~
~ IT ~
g. ~ J:

!:3

NO ACK TO MULTI-RESPONDER COMMAND RECEIVED

;:;." c:.

n
:>;"" '"
~- '"
tTl
..., :I ::!

.......
('D

a.... ~
....

~
v;-

MASTER TRANSMIT CHECK ERROR
CONTROL TRANSMIT ERROR

8....
O'
....
(1)
'"~
:;::

MASTER PARITY ERROR
INTERLOCK SEQUENCE ERROR
TRANSMITIER DURING FAULT
IDENTVECTOR ERROR
COMMAND PARITY ERROR

IT
(1)

SLAVE PARITY ERROR

g..

READ DATA SUBSTITUTE

(1)

RETRY TIMEOUT
STALL TIMEOUT

USER PARITY ENABLE

BUS TIMEOUT

ID PARITY ERROR

NONEXISTENT ADDRESS

CORRECTED READ DATA

ILLEGAL CONFIRMATION ERROR

NULL BUS PARITY ERROR

i=!

....

(1)
(1)

....

8....

'"5-

HARD ERROR BITS <30:16>

Figure 6-5' Bus Error Register

SOFT ERROR BITS <2:0>

0
....
00

6-6 • VAX Privileged Registers

Error Interrupt Control Register
The error interrupt control register controls the operation of interrupts initiated
by a BIlC-detected bus error (which sets a bit in the bus error register) or by the
setting of a force bit in this register.
21 0

bb+ C

INTR COMPLETE
INTRSENT
INTR FORCE
LEVEL<7:4>
VECTOR

Figure 6-6 • Error Interrupt Control Register

INTR Destination Register
The INlR destination register indicates which nodes are to be selected by INlR
commands. The destination is sent out during the INlR command and is monitored by all nodes so that they may determine whether or not to respond.
31

bb+10

1615

~1__________o_s__________~I_____I_N_TR_D_E_~_IN_A_T_IO_N______~1
Figure 6-7· INTR Destination Register

IPINTR Mask Register
The IPINlR mask register indicates which nodes are permitted to send IPIN1Rs
to this node. If a bit in the IPINlR mask field is a 1, IPIN1Rs directed at this
node from the corresponding node will cause selection (assuming the IPINTREN bit in the Bel control and status register is set). If the bit is a 0, IPIN1Rs
directed to this node will not cause selection.
31

1615

~+14~1________IP_IN_TR_M_~__K______~__________os__________~1
Figure 6-8 • IPINTR Mask Register

Force-bit IPINTRISTOP Destination Register
The force-bit IPINTRISIDP destination register indicates which nodes are to be
targeted by force-bit IPINlR or SIDP commands sent by this node.
31

16 15

bb+18 LI_ _ _ _ _ _ _ _ _ _o_s__________

~I_F_O_RC_E_-B_IT_I_PI_NT_~__T_OP_D_E_~_I_NA_T_IO_N~I

Figure 6-9 • Force-bit IPINTRISTOP Destination Register

6-7

IPINTR Source Register
The IPINTR source register is used by the BIle to store the decoded ID of a
node that sends an IPINTR command to the node. Each bit corresponds to one
node on the VAXBI bus.
31

_P_N_TR_s_o_u_Rc_E

bb + 1 C LI_ _ _ _

1615

_ _ _..L._ _ _ _ _o_s_ _ _ _ _...J1

Figure 6-10 • IPINTR Source Register
Starting Address Register
The starting address register defines the beginning of storage blocks in either
memory or input/output space. If the starting address register is set to a value
greater than or equal to the contents of the ending address register, no address
will be recognized.
313029
bb + 20

1010

1817

STARTING ADDRESS

Figure 6-11 • Starting Address Register
Ending Address Register
The ending address register defines the end of storage blocks in either memory
or input/output space. If the starting address is set to a value greater than or
equal to the contents of the ending address register, no addresses will be
recognized.

bb+24IL:~I:~1~29

1_8~11_7

_ _E_N_D_'N_G_A_D_DR_E_SS
__

_ _ _ _ _0_s_ _ _ _ _ _

Figure 6-12· Ending Address Regzster

6-8 • VAX Privileged Registers

BCI Control and Status Register
The BCI control and status register provides control and status information
about the BIle. Control information output to this register can enable the BIle
to initiate VAXBI transactions, assert VAXBI signal lines, and output signal confirmation and event codes.
31
bb + 28

181716151413121110,98 7 6 5 4 3 2

IIIII IIII II III II

BURST ENABLE
IPINTA/STOP FORCE
MULTICAST SPACE ENABLE
BDCST ENABLE
STOP ENABLE
RESERVED ENABLE
IDENT ENABLE
INVAL ENABLE
WRITE INVALIDATE ENA8LE
USER INTERFACE CSR SPACE ENABLE
BIIC CSR SPACE ENABLE
INTR ENABLE
IPINTR ENABLE
PIPELINE NXT ENABLE
RTO EV ENABLE

Figure 6-13 • BCI Control and Status Register
Write Status Register
The write status register indicates which general purpose registers have been
written to by a VAXBI transaction.

3130292827
bb + 2C

l III

I IL----7GE=N~E=R7AL~P=U~R=P=OS=E~R=E=G~IS=T=ER~1
GENERAL PURPOSE REGISTER 0

GENERAL PURPOSE REGISTER 2
GENERAL PURPOSE REGISTER 3

Figure 6-14 • Write Status Register

6-9

Force-bit IPINTRISIDP Command Register
The force-bit IPINTRISIDP command register indicates the 4-bit command
code for either an IPINTR or SIDP transaction that is initiated by setting the
IPINTRISIDP force bit. It is also used to determine whether the master's ID is
transmitted during the command/address cycle of a transaction initiated by setting the IPINTRISIDP force bit.
31
bb + 30

Figure 6-15 • Force Bit IPINTRJSWP Command Register
User Interface Interrupt Control Register
The user interface interrupt control register controls the operation of interrupts
initiated by the user interface.
31
bb+ 4

INTRABORT<7:4>
INTR COMPLETE<7:4>

2827

2423

2019

16151413

11°1

2 1

1°1°1

INTR SENT<7:4>
INTR FORCE<7:4>
EXTERNAL VECTOR

VECTOR

Figure 6-16 • User Inter/ace Interrupt Control Register
General Purpose Registers
The use of the general purpose registers is implementation specific. Whenever
one of these registers is written, a bit is set in the write status register to indicate
which register was written.

bb = FO

GENERAL PURPOSE REGISTER

bb = FA

GENERAL PURPOSE REGISTER 1

bb = FB

GENERAL PURPOSE REGISTER 2

bb = FC

GENERAL PURPOSE REGISTER 3

Figure 6-17 • General Purpose Registers

6-10 • VAX Privileged Registers
Slave-only Status Register

The slave-only status register, which is outside BIlC CSR space, is used by slaveonly nodes to implement a broke bit. This register must be implemented by
nodes that have a device type code with zeros in bits 8 through 14.
o
bb + 100

Figure 6-18· Sf4ve-only Status Register
Receive Console Data Register
The receive console data register, which is implemented by VAXBI nodes that
have a console on the VAXBI bus, is used to receive data from other consoles.

b b + 200

3130 2827

2423

II I

~
NOOE 102
CHARACTER 2

161514 1211

II I
OS

8 7

BUSY 1
NODE 10 1
CHARACTER 1
OPTIONAL <31:16>

REQUIRED < 15:0>

Figure 6-19 • Receive Console Data Register

• VAX 8800/8700 Registers
In addition to the VAXBI registers there are three additional groups of registers
that are of interest in VAX 8800 and VAX 8700 systems. The first group consists
of the registers specific to the VAX 8800/8700 processors. The second group
consists of the registers associated with the VAX 8800/8700 NBIA adapter, and
the third group consists of the registers associated with the VAX 8800/8700
memory controller. Table 6-3 lists the processor-specific registers.

6-11

Table 6-3 • VAX 8800/8700 Processor-specific Registers
Register Name

Abbreviation

Address (Hex)

Machine Check Status
NMI Interrupt Control
Interrupt Other Processor
NMI Fault/Status Register
NMI Silo Data Register
NMI Error Address Register
Cache On Register
Revision Register 1
Revision Register 2
Clear Timeout Status
Flush Write Buffer

MCSTS
NICTRL
INOP
NMIFSR
NMISILO
NMIEAR
COR
REVR1
REVR2
CLRlOSTS
FLUSHWB

26
80
81
82
83
84
85
86
87
88
89

Note that there are no bit digrams for INOP, CLRlOST, and FLUSHWB registers in the figures that follow. Data written to these registers is ignored. The bit
diagrams in this chapter use the following conventions:
• 0 on read is treated as a zero.
• 0 on write means that software must supply zeros. Microcode does not force
zeros or check for errors. These bits are read back as written.
• X on write is ignored.
Machine Check Status Register
The following is the read version of this register.
31

Os
MACHINE CHECK ENTERED VIA AN INTERRUPT
MACHINE CHECK IN PROGRESS
ABORT BIT

Figure 6-20 • MCSTS Register
NMI Interrupt Control Register
This write-only register enables the types of interrupts taken by the processor.

8 7 6 54

31
Os
DEVICE 0 INTERRUPT ENABLE
DEVICE 1 INTERRUPT ENABLE
MEMORY INTERRUPT AND NMI FAULT ENABLE

Figure 6-21 • NICTRL Register

I III

6-12 • VAX Privileged Registers

NMI Fault/Status Register
This register keeps a summary of faults and timeouts on the memory
interconnect.
o
82

BUF ID<O>
ADDRESS DATA PARITY ERROR
CONTROL PARITY ERROR
READ SEQUENCE ERROR
TRANSMITIER DURING
TIMEQUT STATUS<2>
TIMEOUT STATUS< 1 >
TIMEOUT STATUS<O>

Figure 6-22 • NMIFSR Register

NMI Silo Data Register
This read-only silo stores up to 256 transactions on the memory interconnect. It
is initialized to lock on faults. Every read pops one value of a locked silo.
31
83

28272625242322212019

1615

11109 8 7

II III II II

II I

AFTER FAULT

DIAG SILO MARKER
MEMORY BUSY
I/O 0 ARB
I/O 1 ARB
MEMORY ARB
LEFT CPU ARB
RIGHT CPU ARB
NMIIDMASK
NMI FUNCTION
NMI ADDRESS/DATA
NMI CONFIRMATION

Figure 6-23 • NMISILO Register

NMI Error Address Register
This register holds the address of a processor-memory transaction that has
timed out on the memory interconnect.
o

NMI ADDRESS

Figure 6-24 • NMlEAR Register

6-13

Cache On Register
This read/write register controls the use of the cache memory.
31

L - I_

--4111
1

°, _ _

CACHE ON

FIg,ure 6-25· COR RegIster

Revision Register 1
This is a read-only register.
86

2827

2423

2019

1615

1211

8 7

SLC1

SLCO
ADP
CCS
DEC
SEQ
WCS

Figure 6-26 • REVRl Register

Revision Register 2
This is also a read -only register.
31

2423

1615

MICROCODE REVISION
USER MICROCODE REVISION
CONSOLE REVISION
BACKPLANE
CLOCK

FIgure 6-27· REVR2 RegIster

• NBIA Adapter ControVStatus and Vector Registers
Thble 6-4 lists the VAX 8800/8700 NBIA adapter registers. The registers are
accessed by the processor by means of memory interconnect read/write
(longword) transactions. The two reserved registers are not currently used.
Note: In the address column, the X stands for 0 (NBIA 0) or 4 (NBIA 1).

6-14 • VAX Privileged Registers

Table 6-4 • VAX 8800/8700 NBIA Adapter Registers
Register Name

Abbreviation

Address

Control/Status Register 0
Control/Status Register 1
Reserved
Reserved
BR4 Vector Register
BR5 Vector Register
BR6 Vector Register
BR7 Vector Register

CSRO
CSRI
RSVDO
RSVDl
BR4VR
BR5VR
BR6VR
BR7VR

2X080000
2X080004
2X080008
2X08000C
2X080010
2X080014
2X080018
2X08001C

The NBIA has two control/status registers.
313029282726252423222120191817161514

109 87

11 I1 LIDS Il°ll II

2X08 0000
DATA PARITY FAULT

CONTROL PARITY FAULT
READ SEQUENCE FAULT
WRITE SEQUENCE FAULT
TRANSMITIER DURING FAULT

TIMEOUT<2>
TIMEOUT<1>
TIMEOUT<O>

NBIINTERRUPT ENABLE

FLIP 29/22
FORCE DMA BUSY

FORCE NBIA PARITY ERROR
BIIC LOOPBACK

NBJ DATA PARITY ERROR
NBI VECTOR OFFSET

ADAPTER CODE

Figure 6-28 • CSRO NBIA Adapter Register
31
2X08

0004

N81A MODULE REVISION
FRC NBIB PARITY ERROR
NBIA WRAPAROUND

1615

1211109876543210

loll \oJ III III

Bll POWER UP
BIO POWER UP
NBIA FUNCTION PARITY ERROR
NBIB 811 PARITY ERROR
NBIB B 10 PARITY ERROR
811 PRESENT
BIO PRESENT
ADAPTER I N IT

Figure 6-29 • CSRl NBIA Adapter Register

6-15

The NBIA has four read-only vector registers. When the NBIA is making a
processor interrupt request at some level (BR4, BR5, BR6, or BR7), processor
microcode reads the interrupt vector from the corresponding vector register. All four vector registers use the bit format shown in Figure 6-30.
31
2X08

15 14

I______o_s_ _ _ _ _-'-_ _ _ _-,-_ _ _ _--II

001A ...

VECTOR

Figure 6-30 • Format for BR4VR, BR5VR, BR6VR, and BR7VR Registers

• Memory Controller Register
'Thble 6-5 lists the control/status registers in the VAX 8800/8700 memory
controller.
Table 6·5 • VAX 8800/8700 Memory Controller Registers
Register Name

Address

Control/Status Register 0
Control/Status Register 1
Control/Status Register 2
Control/Status Register 3
Control/Status Register 4
Control/Status Register 5
Control/Status Register 6

3EOO 0000
3EOO 0004
3EOO 0008
3EOO OOOC
3EOO 0010
3EOO 0014
3EOO 0018

The first four registers are physical registers. The remaining registers are pseudo
register addresses that perform specific functions.
3130292827262423

3EOO

0000

OATA PARITY FAULT

I 11 1 II
jI
0

2019

1615

8 7

CONTROL PARITY FAULT
WRITE SEQUENCE ERROR
TRANSMITIER DURING FAULT
TIMEOUT CODE
REVISION CODE
AOAPTER CODE

Figure 6-31 • CSRO Memory Controller Register

6-16 • VAX Privileged Registers
313029
3EOO

00041 Xs

2221 20

987

III
I

READ ONLY DECODE RAM ADDRESS FIELD

DECODE RAM WRITE ENABLE

5432

III I

DECODE RAM PARllY
DECODE RAM DATA
DECODE RAM ADDRESS FIELD
DECODE RAM SO PRESENT DATA

DECODE RAM DATA

Figure 6-32 • CRSl Memory Controller Register
3130292827

3EOO

ODDS

III II

RDS HIGH ERROR RATE

2423222120191817161514

1111

876

'II

RDS
CRD
FORCED DBE DETECTED
DIAGNOSTIC MODE ENABLE

DISABLE ERROR CORRECTION
ENABLE SUBSTITUTE CHECK BITS
PARITY ERROR FORCE
ENABLE LOQPBACK
CH ECK BIT SELECT
CHECK BITS
ERROR SYNDROME

Figure 6-33 • C5R2 Memory Controller RegIster
31

3EOO

OOOC

INTERRUPT ENABLE FIELD

282726252423

I'-T1-'-r-1Y;-J-l-----.------'
I II !xl
I

UNUSED
COLD START
INTERNAL ERROR
MEMORY ARRAY CARD SIZE AND PRESENCE

FIgure 6-34 • C5R3 Memory Controller RegIster

• VAX 8650 Registers
The VAX 8650 registers are the same as the VAX 8600 registers. See Volume 1,
Chapter 10 .

• VAX 8550/8500 Registers
The VAX 8550/8500 registers are the same as the VAX 8800/8700 registers
described above.

• VAX 8300/8200 Registers
See the VAXBI Registers section at the beginning of this chapter.

Chapter 7 • Mass Storage Systems

Digital offers a complete line of intelligent mass-storage subsystems and storage
devices designed specifically to operate with VAX processors and VAXcluster
architecture. These subsystems and devices allow a user to select the mass-storage requirements that best suit the system application and to add storage capabilities when the application requirements increase. The storage subsystems
and devices operate with the VAXBI, Q-Bus, UNIBUS, and VAXclusters to provide fast and reliable access to information. The interaction of the VAX processors normally required to access and manage data has been reduced by
allocating many of the data tasks to the mass-storage subsystem and devices.
Digital Storage Architecture (DSA) is the framework governing the design and
manufacture of an expanding group of mass-storage devices and intelligent
controllers. The DSA provides leadership data reliability and integrity features.
It allows efficient performance and ease of maintenance for all Digital storage
subsystems and devices. New systems and devices that are developed by Digital
can be easily added to the system without the need to replace existing storage
devices or to generate new software.
Some of the features provided by DSA and storage subsystem design are:
• Advanced data integrity techniques.
• High-capacity, mass-storage devices.
• Intelligent controllers that provide error detection and improved throughput.
• Easy migration to new Digital mass storage products.
• Integrated host processor and storage subsystem engineering.
• Dual-access drive capabilities

• Intelligent Mass Storage Controllers
The HSC50, HSC70, and KDB50 intelligent mass storage controllers perform
many of the functions required to effectively manage and control the storage
and transfer of information. The HSC50 controller is a special-purpose storage
controller that operates as a node in a VAXcluster. The HSC70 is the newest
member of the HSC family of intelligent mass storage controllers. The HSC70
controller is designed to operate with multiple systems that must share information locally or where systems or applications require high-speed disk and tape
vo. The KDB50 controller is a new, high-performance microprocessor-based
VAXBI disk controller designed for fast, reliable, and optimum RA-disk
throughput performance on the new VAXBI-based computer systems.

7-2 • Mass Storage Systems

HSC50 Controller
The HSC50 is an intelligent controller that performs many of the functions
required to effectively manage and control the storage and transfer of information. The HSC50 is a special purpose storage controller that operates as a node
within the VAXcluster architecture and coordinates the activities of up to 24
mass-storage devices including disk and magnetic tape drives. The HSC50 controller can serve several host processors connected to the VAXcluster CI bus.
The HSC50 is housed in a stand-alone cabinet, is independently powered, and
electrically isolated from the CPUs and drives that it serves. It provides highperformance VO throughput using a PDP-II-based microprocessor in conjunction with multiple, high-speed bit slice microprocessors. The HSC50 server
offloads all disk management functions from the host systems and provides
host-independent sharing of common data among a network of locally connected midrange and larger processors. Refer to the VAX Hardware Handbook,
Volume 1-1986 for more details on this controller.

HSC70 Controller
The HSC70 controller is a multichannel controller that connects both disk and
tape drives' to all of the host computers in a VAXcluster. The HSC70 supports a
combination of eight disk and tape data channels. Each disk data channel supports four drives over the Standard Disk Interface (SDI). Each tape data channel supports four tape formatters over the Standard Tape Interface (STI) and,
depending upon which formatter is used, from one to four tape transports can
be supported by each formatter.
The HSC70 connects to one or more host computers by means of the 70-Mbitper-second dual path Computer Interconnect (CI) bus. A CI can accommodate
up to 16 nodes or connected devices, so a single HSC70 server can provide storage services for as many as 15 VAX host computers and as many as 32 devices. A
fully configured HSC70 can provide attachment to over 14.5 Gbytes of mass
storage. Any node can be a VAX or an HSC, so CPUs and HSC70 and HSC50
servers can be mixed in any combination to service any required balance of
computing power and 1/0 bandwidth or connectivity.
Individual microprocessors control disk and tape operations and communications with host computers. In addition, a PDP-ll-based microprocessor manages all of the internal work flow, performance optimizations, and error
recovery.
The HSC70 architecture exceeds the HSC50 architecture with:

Greater Drive Connectivity - The HSC70's extended backplane can accommodate up to 8 HSC5X-BA data channels for a total drive connectivity of 32
compared to the HSC50's 24. (Ali 32 drives may be RA-series disk drives, or up
to 16 of them may be TA-series tape formatters.)

7-3

Greater I/O Command Handltng Performance - The HSC70 Master Control
Microprocessor Module is based on theJ-lI chip used in the PDP-1I173. (The
HSC50 is based on the F-ll chip used in the PDP-ll/23 +.) The increased
command processing capability is supported by expanded program, control
and data memories in the HSC70. Maximum I/O handling capability is approximately twice that of the HSC50. (Maximum steady data throughput remains the
same at approximately 4.2 Mbytes/second.)
Greater Operational Convenience - Ease of use is improved through greatly
shortened boot times with the use of an RX33 double-sided floppy disk drive as
the load medium rather than the HSC50's TU58. An improved operator interface uses a combination of a VT220 and LA50 instead of the HSC50's LAI2.
Ease of use is further improved via improved operator handling, console terminal help, and improved installation and operational documentation.
Greater Reliability - Manufacturing process improvements and testing procedures have resulted in improved reliability for both the HSC70 and the HSC50.

With an I/O request rate up to twice that of the HSC50, depending on request
size, the HSC70 is the ideal storage server for midrange to high-end cluster configurations and for stand-alone VAX 8650 and VAX 8800 processors, while the
HSC50 remains the storage server of choice for low-range to midrange VAX
processors and clusters. Table 7-1 compares the general specifications of these
I/O servers.
Table 7-1· Comparison of HSC70 and HSC50 VO Servers
HSC70 I/O Server

HSC50 I/O Server

Connectivity:
Data Channels
Devices

Up to 8
Up to 32

Upto6
Up to 24

Memory Size:
Data Memory
Program Memory
Control Memory

256 Kbytes
1,024 Kbytes
256 Kbytes

128 Kbytes
256 Kbytes
128 Kbytes

Processor fbwer

J-11 Processor

F-ll Processor

Bootlreboot Time
(approximate)

1 minute

6 minutes

Auxiliary fbwer

Integral

Optional

7-4 • Mass Storage Systems

The HSC70 controller performance specifications are as follows:
• CI port bandwith: 8.8 Mbytes/s (maximum)

• VO request/second: up to 650
• Disk data-channel bandwidth:3.125 Mbytesls (maximum each channel)
• Internal data bus: 13.3 Mbytesls (maximum)

KDB50 Controller
The KDB50 single-host controller is the only method of connecting disk drives
directly to the VAXBI bus. The KDB50 is mounted in two adjacent slots in the
BI-Bus cage box and consists of two BI-modules and represents one BI-Bus
interface. Up to four RA-series disk drives may be radially connected to each
KDB50 controller. Currently, each RA-series disk drive can range in capacity
from 121 Mbytes to 456 Mbytes for a total capacity of over 1,800 Mbytes per
KDB50. Because the KDB50 disk controller is compatible with all DSNSDI disk
drives, both present and future generation disks will plug and play on the
KDB50.
The KDB50 communicates with the disk drives using the SDI bus and SDI protocol and with the host using the VAXBI bus and the Mass Storage Control
Protocol (MSCP). Two BI modules make up the KDB50 - the Standard Disk
Interface (SDI) module and the processor module. The Standard Disk Interface
module is the communication interface between the KDB50 processor module
and the disk drives. The processor module contains a dual microprocessor and
a Control Store Read Only Memory (CROM).
The KDB50 DSA performance optimizations make it ideal for use in many highperformance environments. Contained in microcode, these performance
optimizations include:

Seek Ordering - The KDB50 uses its command buffer to look ahead into each
disk drives workload and select the outstanding request that will result in the
optimal seek from the disk drive's current position. In a heavily loaded subsystem, seek ordering can result in performance improvements of up to 35
percent.

Overlapped Seeks - To maximize parallel drive operation, the disk port driver
initiates all requested seeks before initiating any data transfers. This feature
effectively results in more efficient utilization of the subsystem and higher overall throughput. It is not necessary to wait for one drive to seek, transfer, and
release the channel before giving another drive a seek command. The result is
that multiple drives are placed on cylinder and on track, and are prepared to
transfer data.

75
Rotational Optimization - As with conventional controllers, the KDB50 has
one drive-to-controller data-transfer channel. Unlike conventional controllers,
however, the KDB50 dynamically allocates this channel to the on-cylinder drive
whose targeted starting sector is closest to the read/write heads. This feature,
when combined with overlapped seeking, minimizes average rotational latency
in multidrive subsystems and sustains effective and efficient throughput.

The KDB50 connects directly to the VAXBI providing the fast burst data rates
needed to support high-throughput requirements. High I/O throughput applications run over 33 percent faster than on a comparably configured VAX-U/
750 with a UDA50. With improved I/O performance, VAXBI systems can
respond to requests more quickly and move on to the next task. The result is
better overall systems performance, higher user satisfaction, and improved CPU
utilization.
Device integrity and protection against loss of data is achieved via bad block
replacement,'" automatic revectoring to replaced blocks, the industry's most
extensive error correction code (ECC) and error detection code (EDC). (The
KDB50's l70-bit Read-Solomon ECC can correct up to eight lO-bit bursts in a
single sector, compared to the single II-bit burst correction power of more
commonly used ECC. A unique feature of all SDI subsystems, EDC verifies ECC
computation logic and the ECC correction process, checks controller data
paths, and indicates a forced error in the rare event that an uncorrectable media
error causes sector replacement.) The KDB50's extensive data protection capabilities also include multiple sector headers to verify read/write head position
prior to data transfers, single point failure detection, and extensive self-testing
capabilities.
The KDB50 disk controller performance spea/ications are as follows:
• Instantaneous transfer rate: 3.0 Mbytes/s maximum
• Steady state throughput: 1.0 Mbytes/s sustained
• Multiple controller throughput: 2.0 Mbytes/s sustained (2 x KDB50)
• Number of drives supported: 4

;, The replacement blocks are not part of the total user-accessible disk capacity, so no
shrinkage of available disk occurs because of bad blocks. This feature requires operating system support. Check appropriate Software Product Descriptions for versions and
releases.

7-6 • Mass Storage Systems

• Thpe Storage Media Devices
Digital provides a complete series of industty-compatible magnetic tape devices
to operate with the UNIBUS, Q-bus, and VAXBI bus on VAX systems and with
the HSC50 and HSC70 intelligent controllers in VAXcluster Systems. The magnetic tape devices provide reliable medium- and high-density backup storage
for Digital's disk storage devices.

TA81 Thpe Storage Device
Offering midrange price and performance, the streaming tape TA81 is one of
Digital's two dual-density HSC-based magnetic tape subsystems. The other
is the high-performance, top-of-thc-line TA78 system described in the VAX
Hardware Handbook Volume 1-1986. TheTA78 and theTA81 can be mixed on
the same interface module, both acting as shared resources, available to users
anywhere in the cluster.
Efficient design allows the TA81 with its integrated formatter to be compactly
packaged in a single waist-high (41.6 inches high by 21.3 inches wide by 30.0
inches deep) cabinet with room for a disk drive in the same cabinet for a fully
integrated disk and tape subsystem. An HSC5/5X-CA interface can support
fourTA81s.
The TA81 conforms to the ANSI standard for group code recording (6,250 bits
per inch) and for phase-encoded recording (1,600 bits per inch) on half-inch,
nine-track tape. It's engineered for high reliability and offers outstanding data
integrity. Read-after-write verification ensures that each bit written is verified
immediately after it is recorded. Vertical parity is checked, character-by-character, when reading and writing. Data integrity is ensured further by recording
error correction code (ECC) and cyclic redundancy check (CRC) characters on
the tape when in GCR mode. The TA81 tape system uses this information to
make both single- and double-track error correction without CPU intervention.
With its streaming tape technology, the TA81 is ideal for applications involving
sustained input/output such as high-capacity disk backup, or recording from
high-speed test equipment. In backup mode, the TA81 tape system performs up
to 50 percent faster than TU81s. Under VMS BACKUP, selection of optimized
switch settings can provide up to 100 percent performance improvement over
BACKUP performance using default settings when recording in GCR mode.
The TA81 tape drive can also use traditional start/stop technology for slower
data transfers. However, heavy transaction processing applications are better
served by the high-speed TA78 subsystem.

7-7

Designed for simplified maintenance and ease of service, the TA81 has built-in
diagnostic software and allows rapid access to all field-replaceable modules.
The TA81 requires no adjustment or preventive maintenance except for routine, customer-performed head cleaning. At powerup, the tape subsystem runs
self-test diagnostics and reports any detected problem so that it can be corrected before the drive is needed. In the unlikely event of unrecoverable error,
the TA81 subsystem alerts the HSC Server. Run offline without CPU involvement, diagnostic software in both the TA81 and the HSC can be used to locate
the problem with minimal impact on cluster operation.
For ease-of-use, the TA81 has a short (13-inch) tape path for fast manual loading, and all operator controls are conveniently located on the front panel.
The TA81 tape storage device performance speafications are as follows:
• Read/write speeds:

> Streaming - 25 and 75 ips
> Startlstop- 25 ips
• Data transfer rate: 468 Kbytes/s (maximum)
• Rewind speed: 192 ips (average)
• Rewind time (2400-foot tape): 150 seconds
The media speCifications are as follows:
• Recording medium: O.5-in magtape (ANSI Standard)
• Number of tracks: 9
• Recording method:

> GCR-ANSI Standard X3.54-1976
> PE-ANSI Standard X3.39-1973
• Recording density:

> GCR-6,250 bpi
> PE-1,600 bpi
• Capacity:

> GCR-140 Mbytes
> PE-40 Mbytes
• 1l-ansports: includes transport and formatter (no slave drives are supported)

7-8 • Mass Storage Systems

TU81·Plus Jape Storage Device
The TU81-plus is the only industry-compatible tape drive offered for Digital's
new VAXBI-based systems running in native mode. A 256-Kbyte cache buffer
significantly improves tape streaming performance on most VAX systems.
Because both commands and data are buffered, the TU81-plus operates at peak
streaming speed more often, while reducing the frequency of reposition hits
caused within the command reinstruct process. When the software selectable
buffer is in operation, data is read into and out of the cache, allowing both the
host processor and the tape drive to optimize their individual data transfer
rates. Further optimizing performance, the TU81-plus automatically selects
speeds of 25 and 75 inches per second for streaming operations, and up to 25
inches per second for start and stop operations.

Efficient design allows the TU81-plus and an RA-series disk drive to be packaged in a single waist -high cabinet. This disk/tape drive combination provides a
compact, quiet, and fully integrated storage subsystem. The tape subsystem easily connects to a VAX processor through a shielded cable and a bus adapter.
Mounting requires one quad slot. Two versions, a BI -Bus version and a UNIBUS
version, are available.
The dual-density TU81-plus conforms to the ANSI standard of 6,250 bits per
inch for group coded recording (GCR) and 1,600 bits per inch for phase encoding (PE) on O.5-inch, nine-track tape. The TU81-plus can store up to 140
Mbytes on a standard 8-Kbyte, 2400-foot reel. The TU81-plus requires no
adjustments or preventive maintenance except for normal head cleaning. A
simple 13-inch tape path for fast manual handling, and a membrane control
panel with touch-sensitive switches also help to make the TU81-plus convenient
and easy to use.
With streaming tape technology and high-speed operation via prefetching of
commands and data, the TU81-plus is ideal for applications involving sustained
tape input such as disk backup, data archiving, or recording data from highspeed test equipment. It also uses traditional start/stop technology for shorter
data transfers of the type associated with journaling, transaction processing, and
classical data processing.
The TU81-plus offers exceptional reliability through a microprocessor-based
servosystem, air bearings, gentle tape handling, and fewer mechanical parts.
Character-by-character vertical parity at both densities, read-after-write verification, and automatic two-track error detection and correction (in GCR mode)
during operation ensure data integrity. Self-test and diagnostics automatically
check the drive and the controller for proper functioning each time the TU81plus is powered on and during rewind and, if a malfunction occurs, the TU81plus has extensive diagnostics for prompt failure isolation and identification.

7-9

The performance specifications of the TU81-plus are as follows:
• Read/write Speeds:

> Streaming-75 and 25 ips
> Start-stop-25 ips
• Data transfer ratc: 468 Kbytcs/s (maximum)
• Capacity:

> GCR-140 Mbytes
> PE-40 Mbytes (8 Kbyte size)
• Rewind speed: 192 ips
• Rewind time: 150 seconds
• Cache buffer: 256 Kbytes, software selectable
TI1e media specifications are as follows:
• Recording method:

> 'TI-acks--9
> GCR-ANSI Standard X3.54-1976
> PE-ANSI Standard X3.39-1973
• Recording medium: OJ-in ANSI Standard magnetic tape
• Recording Density:

> GCR-6,250 bpi
> PE-1,600 bpi
• Record length: variable to 64 Kbytes

Appendix A • VAX Processor Specifications

• VAX 8200 Processors
Processor Type
Cycle time
Control store size

Internal data path
Instruction buffer size
Maximum system I/O rate
Cache memory
VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Number of priority interrupt levels
Number of addressing modes
Data types supported

Main Memory
Virtual address capacity
Physical expansion capacity
Error correcting code
Memory cycle times
Octaword (128 bits) read
Octaword write
Longword (32 bits)read
Longword write
Operating Environment
Temperature
RX50 disk drive not in use
RX50 disk drive in use
Relative humidity
RX50 disk drive not in use
RX50 disk drive in use
Maximum altitude
Maximum heat dissipation

200ns
15 Kwords by 40 bits ROM, plus 1
Kword by 40 bits RAM
32 bits
8-byte lookahead
13.3 Mbytes/s
8 Kbytes
16
304
32
9
Integer, floating point (D, F, G, and
H), packed decimal, character string,
variable bit fields, and numeric strings
4 Gbytes
24 Mbytes in 2- and 4-Mbyte
increments
7 bits/longword
1.6 fLS
1.2 fLS
1.0 fLS
600ns

10°C to 40°C (50°F to 104°F)
15°C to 32°C (59°F to 90°F)
10 to 90% noncondensing
20 to 80% noncondensing
2,438 m (8,000 ft)
6.08 MJlh (5.76 kBtulh)

Appendix A-2 • VAX Processor Specifications

Processor Power Requirements
Line voltage
60Hz
50Hz
Phases
Maximum ac power consumption
Surge current
Physical Characteristics
W:ight (maximum)
Height

Width
Depth
Area

120V
240 V
1
1.69kW
100 A
250 kg (550 lb)
106 cm (42 in)
54 cm (22 in)
81 cm (32 in)
0.44 m 2 (4.89 ft2)

• VAX 8300 Processor
Processor Type
Cycle time
Control store size

Main Memory
Virtual address capacity
Physical expansion capacity
Error correcting code
Memory cycle times
Octaword read
Longword write

200ns
15 Kwords (40-bits/word) of ROM
per processor, plus 1 Kword
(40-bits/word) of RAM per processor
32 bits
8-byte lookahead/processor

13.3 Mbytes/s
8 Kbytes/processor
16/processor
304
32

9
Integer, floating point ( D, F, G, and
H), packed decimal, character string,
variable bit fields, and numeric strings
4 Gbytes
24 Mbytes in 2- and 4-Mbyte
increments
7 bits/longword
1,600 ns
600ns

Appendix A -3
Operating Environment
Temperature
Relative humidity
Maximum altitude
Maximum heat dissipation
Processor Power Requirements
Line voltage
60Hz
50Hz
Phases
Maximum ac power consumption
Surge current
Physical Characteristics
\Xeight (maximum)
Height
Width
Depth
Area

15°C to 32°C (59°F to 90°F)
20 to 80% noncondensing
2,438 m (8,000 ft)
6.08 MJlh (5.76 kBtulh)

120V
240 V
1
1.69 kW
100 A
260 kg (572lb)
106 cm (42 in)
54 cm (22 in)
81 cm (32 in)
0.44 m2 (4.89 ft2)

• VAX 8500 and VAX 8550 Processors
Processor Type
Cycle time
Writable control store size
User accessible control store
Internal data path
Instruction buffer size
Maximum system 1/0 rate
Cache memory
VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Number of priority interrupt levels
Number of addressing modes
Data types supported

Main Memory
Virtual address capacity
Physical expansion capacity
Error correcting code
Memory cycle times
Hexword (256 bits) read
Octaword (128 bits) write
Longword (32 bits) write

45 ns
16 Kwords (144-bits/word)
1 Kword (144-bits/word)
32 bits
16-byte lookahead
16 Mbytes/s
64 Kbytes
16
304
32
9
Integer, floating point (D, F, G, and
H), packed decimal, character string,
variable bit fields, and numeric strings
4 Gbytes
80 Mbytes
7 bitsllongword
Max. 1260 ns, min. 495 ns
Max. 540 ns, min. 270 ns
Max. 495 ns. min. 135 ns

Appendix A -4 • VAX Processor Specifications

Operating Environment
Temperature
Relative humidity
Maximum altitude
Maximum heat dissipation
Processor Power Requirements
Line voltage
60Hz
50Hz
Frequency tolerance
60Hz
50Hz
Phases
Maximum ac power consumption
Physical Characteristics
\Xeight
Height
Width
Depth
Area

15°C to 32°C (59°F to 90°F)
10 to 90% noncondensing
2,438 m (8,000 ft)
12.66 MJlh (12.00 kEtulh)

208 V
240V
59 to 61 Hz
49 to51 Hz
3 (A,B,C)
3.2kW
295 kg (650 lb)
152 cm (60 in)
68.5 cm (27 in)
76.2 cm (30 in)
0.5 m2 (5.6 ft 2 )

• VAX 8700 Processors
Processor Type
Cycle time
Control store size
User writable control store
Internal data path
Instruction buffer size
Maximum system I/O rate
Cache memory
VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Number of priority interrupt levels
Number of addressing modes
Data types supported

45 ns
16 Kwords (144-bits/word)
1 Kwords (144-bits/word)
32 bits
16-byte lookahead
30 Mbytes/s
64 Kbytes
16
304
32
9
Integer, floating point (D, F, G, and
H), packed decimal, character string,
variable bit fields, and numeric strings

Appendix A-5
Main Memory
Virtual address capacity
Physical expansion capacity
Error correction code
Memory cycle times
Hexword (256 bits) read
Octaword (128 bits) write
Longword (32 bits) write
Operating Environment
Temperature
Relative humidity
Maximum altitude
Maximum heat dissipation
Processor Power Requirements
Line voltage
60Hz
50Hz
Frequency tolerance
60Hz
50Hz
Ibwer consumption
Surge current
60Hz
50Hz
Physical Characteristics
\XCight"
60Hz
50Hz
Height
Width
Depth
Area

4 Gbytes
128 Mbytes
7 bits/longword
Max. 1260 ns, min. 495 ns
Max. 540 ns, min. 270 ns
Max. 495 ns, min. 135 ns
15°C to 320C (59°F to 90°F)
10 to 90% noncondensing
2,438 m (8,000 ft)
13.29 M}/h (12.60 kBtulh)

208 V
440 V
59 to 61 Hz
49 to51 Hz
3.7kW

500 A
250A

668 kg (1474lb)
802 kg (1769lb)
152 em (60.5 in)
188.0 em (74.0 in)
76.2 cm (30.0 in)
1.4 m2 (15.5 ft2)

• VAX 8800 Processors
Processor Type
Cycle time
Control store size
User control store
Internal data path
Instruction buffer size
Maximum system I/O rate
Cache memory

45 ns
16 Kwords (144-bits/word)
1 Kword (144-bits/word)
32 bits
16-byte lookahead
30 Mbytes/second
64 Kbytes/proeessor

Appendix A -6 • VAX Processor Specifications
VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Number of priority interrupt levels
Number of addressing modes
Data types supported

Main Memory
Virtual address capacity
Physical expansion capacity
Error correction code
Memory cycle times
Hexword (256 bits) read
Octaword (128 bits) write
Longword (32 bits) write
Operating Environment
Temperature
Relative humidity
Maximum altitude
Maximum heat dissipation (kernel)
Processor Power Requirements
Line voltage
60Hz
50Hz
Frequency tolerance
60Hz
50Hz
Phases
Maximum ac power consumption
Surge current
60Hz
50Hz
Physical Characteristics

16
304
32
9
Integer, floating point (D, F, G, and
H) , packed decimal, character string,
variable bit fields, and numeric strings
4 Gbytes
128 Mbytes
7 bits/longword
Max. 1260 ns, min. 495 ns
Max. 540 ns, min. 270 ns
Max. 495 ns, min. 135 ns
15°e to 32°e (59°F to 90°F)
10 to 90% noncondensing
2,438 m (8,000 ft)
28.22 MJlh (26.75 kEtulh)

156 to 220 Vrms
360 to 443 Vrms
59to 61 Hz
49to51 Hz
3
6.2kW
500A
250 A

~ight"

60Hz
50Hz
Height
Width
Depth
Area

705 kg (15551b)
836 kg (1849Ib)
152 cm (60 in)
188 cm (74 in)
76.2 cm (30 in)
1.4 m2 (15.5 ft2)

"~t is that of the FE and CPU cabinets and internal components only. The shipping
container and console subsystem weight is not included.

A
adapters
Synchronous Backplane Interconnect
(SBI) adapter, 3-1, 3-3, 3-15-3-16,
3-19-3-21
for VAX 8200 and VAX 8300 systems,
5-5
in VAX 8650 systems, 3-21-3-22

address data path, in VAX 8650 systems,
3-10

architectural processor registers, 6-1-6-2
arithmetic and logic unit (ALU)
in VAX 8650 systems, 3-11
in VAX 8800 and VAX 8700 systems,
2-14

array bus, in VAX 8800 and VAX 8700
systems, 2-16
availability
of VAX 8200 and VAX 8300 systems,
5-14-5-17
of VAX 8550 and VAX 8500 systems,
4-7
of VAX 8650 systems, 3-22-3-27
of VAX 8800 and VAX 8700 systems,
2-26

B
backup translation buffer, in VAX 8200
and VAX 8300 systems, 5-12
battery backup unit (BBU)
for VAX 8200 and VAX 8300 systems,
5-16

for VAX 8650 systems, 3-23
for VAX 8800 and VAX 8700 systems,
2-17,2-21

Bel control and status register, 6-8

bus error register, 6-5
buses
in VAX 8800 and VAX 8700 systems,
2-18-2-19