Digital PDFs

MISC-6841784E

1986

660 pages

Original

37MB

Document:	VAX Hardware Handbook Volume 1
Order Number:	MISC-6841784E
Revision:
Pages:	660
Original Filename:

OCR Text

VAX Hardware Handbook
Volume 1-1986

momoama

Digital believes the information in this publication is accurate as of its publication date; such information is subject to change without notice. Digital is
not responsible for any inadvertent errors.
The following are trademarks of Digital Equipment Corporation:
DEC
DECmate
DECsystem-lO
DECSYSTEM-20
DECUS
DECwriter
DIBOL
MASSBUS

MicroPDP-ll
MicroFbwer/Pascal
PDP

P/OS
Professional
Q-BUS
Rainbow
RSTS

RSX
RT
ULTRIX
UNIBUS
VAX
VMS
VT
'Xbrk Processor

Chapter 1 • Introduction

VAX Processor Features .................................
VAX System and VAX cluster Building Blocks. . . . . . . . . . . . . . .
MicroVAX 1 Microcomputer System. . . . . . . . . . . . . . . . . . . . . .
VAX-ll/725 Open-Office System. . . . . . . . . . . . . . . . . . . . . . . .
VAX-ll/725 Basic System. . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX-ll/725 Package System Configuration ..............
VAX-ll/730 Low-End UNIBUS System ...................
VAX-ll/730 Basic System. . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX-ll/730 System Building Block Config. ..............
VAX-ll/730 Packaged System Configuration .............
VAX-ll/750 Midrange System ..........................
VAX-ll/750 Basic System. . . . . . . . . . . . . . . . . . . . . . . . . . . •
VAX-ll/750 System Building Block Config. ..............
VAX-ll/750 VAX cluster Configurations. . . . . . . . . . . . . . . . .
VAX-ll/780 Original VAX System .......................
VAX-ll/780 Basic System Configuration ................
VAX-ll/780 System Building Block Config. ..............
VAX-ll/780 VAX cluster Configuration .................
VAX-ll/782 Attached-Processor System. . . . . . . . . . . . . . . . . . .
VAX-ll/782 System Building Block Config. ..............
VAX-ll/785 Extended-Performance System. . . . . . . . . . . . . . . .
VAX 8600 High-Performance System. . . . . . . . . . . . . . . . . . . . .
VAX 8600 Basic System .............................
VAX 8600 VAXcluster Configuration. . . . . . . . . . . . . . . . . . .
VAX System Characteristics ..............................
Ease of Use ......................................, . . .
Installation and Maintenance ...........................
Long-Term Investment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture Overview ...... '. . . . . . . . . . . . . . . . . . . . . . . . . .
VAX Instructions and Data 1ypes .. . . . . . . . . . . . . . . . . . . . .
General Registers and Stacks .........................
Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMS Operating System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ULTRIX-32 Operating System ........................

1-2
1-3
1-5
1-5
1-6
1-7
1-8
1-8
1-11
1-11
1-12
1-12
1-15
1-16
1-16
1-17
1-20
1-20
1-21
1-21
1-23
1-23
1-25
1-28
1-29
1-29
1-30
1-30
1-30
1-31
1-33
1-33
1-33
1-36

VAX. System Overview ............... ,................
Cache Memory. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Management... ... .... .. .. ..... ...... ... .. .
Console Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX. System Dependability. . . . . . . . . . . . . . . . . . . . . . . . . .. .. . .
Consistency and Error Checking ........................
Error Analysis and Recovery Features ....................
Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Aids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX.-ll/725 and VAX-ll/730 System Features .... . . . . . . . . . .
Customer Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Hardware ................................
VAX-ll/750 System Features ...........................
Remote Diagnostic Service. . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Hardware ................................
VAX-ll/780,VAX.-ll/782, & VAX-ll/785 System Features. . . . .
Remote Diagnostic Service . . . . . . . . . . . . . . . . . • . .. . . . . . .
Processor Hardware ................................
VAX 8600 System Features ........ : . . . . . . . . . . . . . . . . . . . .
Fault-Tolerant Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Faultlnsertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Diagnostic Bus ...............................
Environmental Monitoring. . . . . . . . . . . . . . . . . . . . . ... . . .
Error Analysis and Reporting ......................... '
Parity Checks .....................................
Processor·Hardware ................................

1-37
1-37
1-38
1-39
1-38
1-39
1-39
1-40
1-40
1-43
1-45
1-46
1-47
1-48
1-49
1-49
1-49
1-50
1-50
1-51
1-51
1-52
1-53
1-53
1-53
1-54
1-54
1-54
1-55

Chapter 2 • VAXcluster and Network Architecture

VAXcluster Systems ............. '. . . . . . . . . . . . . . . .. . . . . . .
Computer Interconnect ................. " . . . . . . . . . . . . . .
SC008 Star Coupler Unit ..............................
HSC50 Intelligent Mass Storage Server ...................
Communication Networks ...............................
Network Environments ...............................
Ethernet Local Area Networks. . . . . . . . . . . . . . . . . . . . .. . . . .
Ethernet on Broadband .................... ,........
Ethernet Communication Controllers. . . . . . . . . . . . . . . . . . .
H4000 Ethernet Transceiver .............• : . . . . . . . . . . .
Ethernet Communication Servers ......•.... : . . . . . . . . . .
UNIBUS Communication Interfaces and Devices ............
UNIBUS Asynchronous Interfaces . . . . . . . . . . . . . . . . . . . . . .

2-2
2-3
2-5
2-8
2-10
2-11
2-11
2-13
2-17
2-18
2-23
2-30
2-31

Synchronous Communication Devices ..................
Terminal Concentrators and Multiplexers . . . . . . . . . . . . . . . .
DMF Series of Statistical Multiplexers ..................
Modems and Multiple Modem Enclosures ...............

2- 38
2-48
2- 50
2-55

Chapter 3 • VAX.11/725 and VAX· 11/730 Processors

VAX-11/725 Processor System ............................
RC25 Disk Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX-11/730 Processor System ............................
VAX-ll/730 Disk Controller~ and Drives. . . . . . . . . . . . . . . . . .
VAX-11/730 Processor Organization. . . . . . . . . . . . . . . . . . . . . .
Internal Bus Structure ..............................
Writable Control Store Functions . . . . . . . . . . . . . . . . . . . . . .
Data Path Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . .
Main Memory Subsystem. . . . . . . . . . . .. . .. . . . . . . . . . . . .
Memory Control and Status Registers ..................
Processor Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2
3-5
3-5
3-7
3-8
3-10
3-11
3-12
3-13
3-14
3-16
3-19

Chapter 4 • VAX.11/750 Processor

VAX-11/750 Processor System ............................
VAX-11/750 System Configuration. . . . . . . . . . . . . . . . . . . . . . .
VAX-11/750 Processor Organization. . . . . . . . . . . . . . . . . . . . . .
Internal Bus Structure ..............................
Processor Logic Elements ...................... . . . . . .
Main Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Control and Status Registers ..................
Processor Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3
4-4
4-7
4-7
4-9
4-11
4-12
4-12
4-14
4-17

Chapter 5 • VAX.11/780 and VAX· 11/785 Processors

VAX-11/780 Processor System ............................
VAX-11/785 Processor ..................................
VAX-11/780 and VAX-ll/785 System Configuration . . . . . . . . . .
UNIBUS and CPU Expansion Cabinets . . . . . . . . . . . . . . . . . . . .
VAX-11/780 and VAX-ll/785 Processor Organization
Console Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Bus Structure ..............................
Processor Logic Elements ............................
Processor Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Memory Subsystem.. .. .. . ... .. . .. .. .. .. . .. . . . .
Basic Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-3
5-3
5-5
5-7
5-8
5-10
5-12
~-13

5-16
5-16
5-19

Memory Configuration Registers ......................
MA 780 Shared Memory Configuration . . . . . . . . . . . . . . . . . .
Shared Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-22
5-24
5-27

Chapter 6 • VAX-ll/782 Attached-Processor System
VAX-11/782 Processor System Configuration. . . . . . . . . . . . . . . . .
VAX-11/782 Upgrade Package. . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX-11/782 System Operation. . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Initialization ................. . . . . . . . . . . . . .
Attached Processor States . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiprocessing Interrupt Communications

6-3
6-6
6-6
6-7
6-8
6-9

Chapter 7 • VAX 8600 Processor
VAX 8600 Physical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
System Expansion Cabinets ............................
VAX 8600 Processor Organization .........................
Console Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Environmental Monitoring Module ....................
Instruction Box Functions ...........................
EBOX Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-Point Accelerator Functions ...................
Memory Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Backplane Interconnect Functions . . . . . . . . . . .

7-3
7-5
7-7
7-7
7-11
7-13
7-15
7-17
7-17
7-19

Chapter 8 • VAX Console Subsystems

Console Subsystem Description ...........................
Console Modes of Operation ...........................
Console Commands ..................................
Console Terminal Prompts .............................
Console Halt Codes ..................................
Console Command Language ...........................
Control Characters ............ . . . . . . . . . . . . . . . . . . . . . . .
Errors and Illegal Characters ...........................
System Restart and Reboot Sequence . . . . . . . . . . . . . . . . . . . . .
VAX-11/725 Console Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Control Characters ............................
Console Commands ..................................
Console Command Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Loading Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Restart Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1
8-2
8-3
8-4
8-4
8-7
8-9
8-9
8-9
8-10
8-11
8-11
8-14
8-14
8-17
8-18
8-19

VAX-ll/730 Console Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Modes ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Control Characters ............................
Console Commands ..................................
Console Command Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Loading Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Restart Procedures .............................
VAX-ll/750 Console Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Control Characters ............................
Console Commands ..................................
Console Command Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Loading Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Restart Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX-ll/780 Console Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Modes ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Panel .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Control Characters ............................
Console Help Files and Commands ......................
Console Commands ..................................
Console Command Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Bootstrap Procedure .........................
Bootstrap Loading Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Restart Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX-ll/782 Console Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Panels ................................
Console Control Characters ............................
Console Commands ..................................
Console Command Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Loading Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Restart Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Bootstrap Command Procedure. . . . . . . . . . .. . . . . . . .
VAX-ll/785 Console Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Modes ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Panel ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Control Characters ............................
Console Command Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Loading Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Bootstrap Command Procedure . . . . . . . . . . . . . . . . .
VAX 8600 Console Subsystem ............................
VAX 8600 Console Modes .............................

8-20
8-20
8-20
8-22
8-22
8-22
8-22
8-22
8-23
8-23
8-24
8-27
8-27
8-30
8-30
8-32
8-33
8-34
8-34
8-36
8.-38
8-38
8-43
8-48
8-49
8-50
8-51
8-51
8-51
8-51
8-51
8-51
8-52
8-52
8-52
8-53
8-53
8-53
8-53
8-53
8-53
8-54
8-55
8-56

System Control Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Software Programs ............................
Console Software Organization .......................
Console Command Syntax .............................
General Command Set ................................
Macro Context Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Context Commands .........................
Microhardcore Context Commands ......................
Debug and Trace Facility ..............................
VAX 8600 System Initialization .........................
Power System Initialization ..........................
Macro Context Initialization .........................
CPU Initialization .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-58
8-61
8-62
8-63
8-64
8-70
8-73
8-77
8-78
8-83
8-85
8-85
8-85

Chapter 9 • Computer Bus Interconnects

CPU/Memory Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMI Signal Lines ....................................
Transfer Format .....................................
CMIOperation ..................................... '.
CMI Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Backplane Interconnect . . . . . . . . . . . . . . . . . . . . . . .
SBI Signal Lines .....................................
SBI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBI Physical Address Space ............................
Information Transfer .................................
Parity Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tag Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identifier Field ....................................
Mask Field .......................................
Function Field ....................................
Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-1
9-2
9-3
9-5
9-6
9-6
9-7
9-12
9-13
9-13
9-14
9-15
9-16
9-17
9-18
9-19

Chapter 10 • VAX Privileged Registers

Architectural Processor Registers ........................
Process Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Address Space . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
System Space .....................................
Program Interrupts ...................... : . . . . . . . . ..
System Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Terminal Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAX-ll/725 and VAX-ll/730 Processor-Specific

10-1
10-4
10-7
10-10
10-12
10-15
10-18
10-22

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TU58 Console Storage ..............................
FP730 Floating-Point Accelerator. . . . . . . . . . . . . . . . . . . . ..
VAX-11/750 & VAX-11/751 Processor-Specific
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TU58 Console Storage ..............................
Bus Registers .....................................
Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
VAX-11/780,VAX-11/782, & VAX-11/785 ProcessorSpecific Registers ....................................
Micro Control Store .... . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Backplane Interconnect Bus. . . . . . . . . . . . . . ..
FP780 Floating-Point Accelerator. . . . . . . . . . . . . . . . . . . . . .
VAX 8600 Processor-Specific Registers. . . . . . . . . . . . . . . . . . ..
Memory Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Diagnostic Registers ................................
Console Subsystem Interface .........................
Console Block Storage ..............................
FP86 Floating-Point Accelerator. . . . . . . . . . . . . . . . . . . . . ..

10-25
10-26
10-29
10-30
10-30
10-30
10-32
10-36
10-37
10-39
10-47
10-49
10-50
10-60
10-63
10-77
10-80

Chapter 11 • VAX Input/Output Subsystems

I/O Subsystem Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UNIBUS Subsystem. :. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MASSBUS Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Computer Interconnect Subsystem . . . . . . . . . . . . . . . . . . . . . . .
DR32 Device Interconnect Subsystem ....................
I/O Subsystem Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
UNIBUS Subsystem Functions ..........................
UNIBUS Signal Lines ...............................
UNIBUS Adapter Operation. . . . . . . . . . . . . . . . . . . . . . . . ..
Communication and Control. . . . . . . . . . . . . . . . . . . . . . . . ..
Address Translation ................................
Priority Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Paths .......................................
Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Initialization and Power Failure. . . . . .. ... . . .. ... . . ....
Small and Medium VAX Processor UNIBUS Operation . . . . . . ..
Large VAX Processor UNIBUS Subsystem. . . . . . . . . . . . . . . . ..
SBI-to-UNIBUS Transfers ............................
UNIBUS-to-SBI Address Translation. . . . . . . . . . . . . . . . . . ..
UNIBUS-to-SBI Address Translation . . . . . . . . . . . . . . . . . . ..
UBA Data Transfer Paths ............................
Data Transfers to Memory ...........................
Data Transfers from Memory. . . . . . . . . . . . . . . . . . . . . . . ..

11-1
11-3
11-6
11-8
11-9
11-10
11-11
11-11
11-13
11-13
11-14
11-14
11-16
11-17
11-17
11-17
11-25
11-26
11-30
11-31
11-33
11-34
11-36

Longword-Aligned 32-Bit Random Access Mode ......... . 11-39
Interrupt Requests ................................ . 11-41
UBA Register Assignments .......................... . 11-44
SBI Addressable UBA Registers ....................... . 11-45
MASSBUS Subsystem Functions ........................ . 11-58
MASSBUS Signal Lines ............................. . 11-59
MASSBUS Adapter Operation ........................ . 11-61
Virtual to Physical Address Translation ................ . 11-65
MBA Registers ................................... . 11-66
Configuration/Status Register ........................ . 11-75
Computer Interconnect Subsystem Functions ............. . 11-76
CI Adapter Operation .............................. . 11-77
Llimk Interface ................................... . 11-77
Data Packet Buffer ................................ . 11-79
Data Path ....................................... . 11-79
CI Registers ..................................... . 11-79
Packet Formats ................................... . 11-91
DR32 Device Interconnect Subsystem Functions ........... . 11-93
DDI Adapter Operation ............................ . 11-93
DDI Signal Lines .................................. . 11-95
Command Chaining ............................... . 11-97
Data Chaining .................................... . 11-98
Programming Interface ............................. . 11-99
DDI Adapter Registers ............................. . 11-101
Device Control Register ............................ . 11-101
Chapter 12 • Mass Storage Subsystems and Devices

Intelligent Mass Storage Controllers . . . . . . . . . . . . . . . . . . . . . . . .
HSC50 Intelligent Mass Storage Server ...................
UDA50 Intelligent Disk-Drive Controller. . . . . . . . . . . . . . . . . .
DSA Disk-Drive Subystems ..............................
RA60 Removable-Media Disk Drive . . . . . . . . . . . . . . . . . . . . . .
RA80 Fixed-Media Disk Drive .. . . . . . . . . . . . . . . . . . . . . . . . .
RA81 Fixed-Media Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . . .
UNIBUS Disk-Drive Subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . .
RL02 Cartridge Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC25 FixedfRemovable Disk Drive ......................
MASSBUS Disk-Drive Subsystems .........................
RM05 Removable-Media Disk Drive .......... :..........
RP07 Fixed-Media Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . ..
Magnetic Tape Subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TU80 Magnetic Tape Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TU81 Magnetic Tape Unit. . . . .. . . . . . . . . . . . .... . . . . . . . ..
TA78 Magnetic Tape Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

12-2
12-2
12-3
12-4
12-5
12-6
12-8
12c 9
12-9
12-11
12-12
12-13
12-14
12-16
12-16
12-17
12-19

TU77 Magnetic Tape Drive. . . . . . . . . . . . . . . .. . . . . . . . . . . ..
TU78 Magnetic Tape Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TS05 Magnetic Tape Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12-20
12-22
12-23

Appendix A • VAX Processor Specifications ................................... A-I
Glossary ............................................................................ Glossary-l
Index ... ................................................................................. Index-l

Through the years Digital's VAX system hardware and software have proven
to be a valuable asset to businesses and institutions of all sizes. The versatility
and reliability of VAX systems, coupled with a worldwide network of
dependable training and service facilities, has produced many satisfied customers. The continuing improvements in software functionality and hardware design have opened many new areas for VAX system application. VAX
systems are available for small dedicated applications in office areas, laboratories, and manufacturing sites, and for large distributed data processing
applications where data and processing power is shared between many systems over a wide geographical area.
Digital's consistency of purpose is to design VAX systems that are both hardware compatible and software compatible and to provide a comprehensive
network by which these systems and other manufacturers' systems can effectively communicate to share resources and processing power. By adhering to
the standards of the VAX hardware and software architecture, programs can
be developed on the large VAX systems and for operation on the smaller VAX
systems. Application programs developed for one system can be migrated to
other VAX systems without revisions.
In addition to the general purpose VMS operating systems and extensive layered software that has provided VAX users with a reliable, high-performance
software environment for many years, most of the VAX systems now operate
with the ULTRIX-32 operating systems. ULTRIX-32 software is Digital's supported native UNIX'· operating system that provides complete UNIX functionality enhanced especially for the VAX systems.
Digital has recently developed many new hardware products to extend the
capabilities of existing VAX systems and to allow VAX processors to be used
for new applications. Several new processors and terminals have been added
to satisfy the need for additional small, medium, and large systems. Highcapacity, mass-storage devices and intelligent controllers now provide the
user with the solution to the ever-expanding data storage requirements. New
communication products have been developed to enhance the existing
product line and allow the efficient expansion of network capabilities. A
high-speed computer interconnect was designed to permit the integration of
VAX processors, intelligent mass storage facilities and communication networks into VAXcluster configurations.

Digital Network Architecture (DNA) is a comprehensive framework of hardware and software products to satisfy all communicatidn needs for Local
Area Networks (LANs) and distributed data processing. These products
include DECnet, Ethernet, SNA Gateway and a series of communication
servers. The continued development of communications products ensures
efficient inform'ation transfers between systems and devices.
Digital's Storage Architecture (DSA) is a combination of hardware and software that complements the new and existing VAX systems ~y enabling intelligent mass-storage controllers to perform many of the data storage functions usually assigned to the processor. This sophisticated system increases
data integrity and security and provides faster and more flexible access to
the stored information.

VAX Hardware Handbook
This handbook provides general technical information for the VAX hardware product line to help you evaluate your system requirements. It includes
descriptions and specifications for the VAX processors, data storage systems
and devices, VAXcluster configurations and communication products. Additional information on the VAX system hardware is available from Digital
sales offices. This handbook is part of the VAX handbook set which includes
the following:
VAX Architecture Handbook - Detailed descriptions of the VAX architecture
including virtual address, data representations, instruction formats, addressing modes, interrupt schemes, and memory management.
VAX Software Handbook- Description of the software capabilities of VAX!
VMS operating systems, the Digital Command Language (DeL), programming languages, and data communications.

The VAX system family is composed of Digital's 32-bit VAX processors and
devices that are used for a wide range of applications in the technical,
commercial, academic, and research environments. More than 30,000 VAX
systems installed throughout the world have proven VAX computing to be
a reliable and efficient system for a variety of applicatio.ns. Because of the
many types of VAX processors and devices that are available, the VAX systems can be tailored for specific applications and to conform to many
budgets constraints. All VAX system family members are compatible with
each other because they include the proven VAX architecture and operate
with the same VMS virtual memory operating system. Software developed
for one VAX system performs equally well on any other VAX system. Systems can be easily expanded to fulfill increased processing requirements
without the cost of adding noncompatible software and hardware.
The new members of the VAX system family include the MicroVAX I, a
low-cost, small and compact microcomputer developed for dedicated
applications; the VAX-ll/725 system, which is a low-noise, specially configured version of the VAX-lU730 system designed specifically for the openoffice environment; the VAX-ll/785 system, which is a more powerful
single-processor system than the VAX-ll/780 system; and the VAX 8600, a
high-performance system that provides the speed and power needed for
large-scale, single and multiuser processing applications.

In some of the chapters of this handbook, the VAX processors are referred
to as small, medium, and large, based on their size and processing power.
These references are defined as follows unless otherwise noted in the individual chapters:

Reference

VAX Processor

Small
Medium
Large

VAX-ll/725 and VAX-1l/730
VAX-ll/750
VAX-ll/780, VAX-ll/782, VAX-ll/785, and VAX 8600

1-2' Introduction

. VAX Processor Features
All VAX processors implement the 32-bit VAX architecture, an extensive
instruction set with numerous data types, and a 32-bit bus structure for
high data throughput_ This is coupled with a virtual address space of up to
4 Gbytes, sixteen 32-bit general purpose registers, 12 addressing modes,
and 32 interrupt levels-which together provide a versatile and efficient
processor system_
Common to all VAX systems is a microprocessor-based console subsystem
that allows the user, system manager, or service engineers to communicate
with the system through the console terminal_ In console mode, the processor can be started or halted, self-tested, initialized to a known state, and
single-stepped through instructions_ Information in memory, storage locations, and internal registers can be examined and data can be deposited
into these locations_ Diagnostic maintenance and bootstrap programs can
be loaded from the console load device and controlled by the console terminal_ When the remote diagnostic service is included as part of a Digital
Field Service contract, the diagnostic testing can also be controlled through
the console subsystem from a remote Digital test facility.
VAX system hardware is complemented by the VMS operating system,
which is continually being enhanced to provide more capabilities and more
efficient system operation. VMS is a powerful multiprogramming operating
system capable of supporting many users in realtime, interactive
timesharing, and multistream batch applications. It also provides support
for online program development.
The ULTRIX-32 operating system has been added to the VAX system family
and provides users with a commodity-software base for 32-bit systems. The
ULTRIX-32 system, Digital enhanced native-node UNIX* operating system,
offers the standard set of UNIX languages and utilities. When a high level
implementation language is desirable for limited or dedicated functions,
the VAXELN Toolkit is available for the small and medium VAX processors
running on a current VMS software version.
The full capabilities of the VAX hardware and software are further
enhanced by the VAXcluster architecture, Digital Network Architecture
(DNA), and the Digital Storage Architecture (DSA).
The VAXcluster architecture enables up to 16 VAX processors or HSC50
intelligent mass-storage servers to be connected together through the
SC008 Star Coupler unit to form a single high-performance system.

* UNIX is a trademark of AT&T Bell Laboratories

1-3

Through the VAXcluster, the processing power can be shared by several
VAX processors and each processor is allowed access to data of a common
data file. The HSC50 is an intelligent-mass storage 110 server that optimizes
the system data throughput by controlling the operation of up to 24 disk
drives or tape drives and formatters. The SC008 Star Coupler unit forms
the common connection point for the cables from the processors and intelligent servers. By providing common access to data files, the cost of development software and support of multiple databases when a system is
expanded is significantly reduced. When more processing power is
required, the VAX system selected can be tailored to the new system
requirements without adding unnecessary hardware or software.
The DNA enables communication between VAX systems and other Digital
systems and between Digital systems and systems developed by other manufacturers. Digital offers extensive capabilities that permit the linking of
computers and terminals into flexible configurations to increase the efficiency and cost-effectiveness of data processing operations. Ethernet is
Digital's high-speed local area communications network that enables computer systems and terminals, whether located centrally or at remote sites, to
exchange information and to share resources.
DSA is Digital's framework of standardized interfaces that permit the addition of new products, and technologies that operate with different host
systems without the need to develop new controllers and device drivers.
DSA allows an expanding group mass storage products, including disk and
magnetic tape drives, to be implemented into an intelligent mass-storage
subsystem that provides a high standard of data integrity, fast data
throughput, and many reliability features.

VAX System and VAXcluster Building Blocks
The desired hardware configurations of the standard VAX systems and
VAXcluster systems are obtained by using the system building block (SBB)
menus that are described in the current version of the VAX Systems and
Options Catalog. The menus allow the user to select a basic system consisting of a VAX CPU, main memory, and software operating system license,
and to add the required interfaces and devices. From the system menu, the
user can select the system storage and load devices, communication interfaces, console terminals and operating system documentation and software
media. Using the system building blocks, VAX systems and VAXcluster configurations can be selected for specific applications without the purchase of
unneeded hardware and software. The VAX Systems and Options Catalog
can be obtained at any Digital sales office or from a Digital sales representative. Figure 1-1 shows a typical system building block diagram for the
VAX 8600 VAXcluster system.

1·4· Introduction
Components

Order Code

VAX· 11/730 CPU

730XAAE(AJ)

2·Mbyte ECC MOS memory
Dual TU58 Cassette
VAXjVMS license and warranty

Afully·supported system requires a system device, load device, communications device
and console terminal. If your order does not include the appropriate devices, it may
not be maintainable. In this case you should contact your local Field Seroice branch
office.
SYSTEM
DEVICE

LOAD DEVICE,
Disk/Tape (PE ~ 1600 b/in, GCR ~ 6,250 b/in)
RA60
205MB
(Rem Disk)

TU80
MAGTAPE
(PE)

TU81
MAGTAPE
(PE,GCR)

RA80 121 MB
(Fixed Disk)

RUA80·AA(AD)
RA60·CA(CD)

RUA80·
AA(AD)
TU80·AA(AB)

RUA81·
AA(AD)
TU81·AA(AB)

RA60205MB
(Rem Disk)

RUA60·
CA(CD)
RA60·AA

RUA60·
CA(CD)
TU80·AA(AB)

RUA60·
CA(CD)
TU81·AA(AB)

RA81456 MB
(Fixed Disk)

RUA81·
AA(AD)
RA60·CA(CD)

RUA81·
AA(AD)
TU80·AA(AB)

RUA81·
AA(AD)
TU81·AA(AB)

RA811,368
MB
(3.Fixed Disks)

RUA81·
EA(ED)
RA60·CA(CD)

RUA81·
EA(ED)
TU80·AA(AB)

RUA81·
EA(ED)
TU81·AA(AB)

Communication Devices

Order Code

Multipurpose communications interface

DMF32·LP

8·line EIA asynchronous serial communications interface

DZ11·DP

8·line 20·mA asynchronous serial communications interface

DZ11·HP

16·line EIA asynchronous serial communications interface with
modem control

DHU11·AP

24·line EIA asynchronous serial communications interface with
modem control

DMZ32·AP'"

24·line EIA asynchronous serial communications interface with·
out modem control

DMZ32·DP"

UNIBUS to Ethernet controller

DEUNA-AA

1-5

Console Terminals

Order Code

Hardcopy terminal

LA120-DA

Tabletop terminal

LAIOO-BA

Stand (option)

LAIOX·SL

Tabletop terminal

LA12-DB

Stand (option)

LA12XSL

Purchase of media and documentation or a System Startup Service Package is
required for the first VAX system of each CPU type. System Startup Service Pack·
ages include media and documentation for VMS and all dependent products purchased. See Software Services Section. Complete software order codes with aJ
for RA60 or a M for Magtape.
Software Options

Order Code

VAX/VMS media and documentation (H-kit)

QCOOI-H

SSSP LEVEL I

QCOOl-5

SSSP LEVEL II

QCOOl-7

SSSP LEVEL III

QCOOI-B

"cRemote device only-see Options Section for details

Figure 1-1 • Typical VAX System Building Block Menu

Micro VAX I Microcomputer System
The MicroVAX I microcomputer system is the smallest and least expensive
of the VAX systems. It is engineered to perform dedicated realtime functions, including workstation applications, office automation, and small
business data processing. Because the MicroVAX uses the extended Q-bus,
many inexpensive interface options developed for PDP-ll computer systems can be easily implemented into the MicroVAX I. The MicroVAX I is
described in detail in the MicroVAX I Handbook (document number EB25156-47), which is available from any Digital sales office.

VAX-1l/725 Open-office System
The VAX-1l/725 system is a compact and quiet processor system designed
specifically for the open-office environment and for single-user and multiuser work stations. The system operates with the VMS (virtual memory
system) and provides the power and reliability of the VAX-U/730 processor in a small pedestal cabinet. The VAX-U/725 has been specially reconfigured to reduce noise levels and heat dissipation. It operates efficiently
and quietly in a normal office environment and can be conveniently positioned beneath a desk or table.

1-6· Introduction

• VAX-II1725 BASIC SYSTEM
The VAX-1l/725 contains a VAX-1l/730 CPU, up to 3 Mbytes of main
memory, a dual, TU58 tape cartridge drive as the console load device, and
the RC25 mass-storage disk drive subsystem. The RC25 subsystem uses
Winchester technology and contains an intelligent controller, 26 Mbytes of
data storage on an 8-inch fixed disk, and 26 Mbytes of disk storage on a
removable £artridge. The RC25 contains onboard diagnostic tests to insure
reliable operation and facilitate maintenance. The exec;:ution time of
floating-point instructions and some integer instructions can be decreased
by the addition of the FP730 floating-point accelerator option. Figure 1-2
shows the components included with the basic system.

'Floating Point
Accelerator
(FPA)
DualTU58
Tape Drives
VAX-1l1730
CPU

Console
Subsystem

~_kJ
Tenninal

UBA

D
B
U
S

ECCMOS
Memory
3MB Total

I
Disk
Controller
(RC25)

<=>

RC25
Disk
Drive

"
No External UNIBUS Extension
'Optional

Figure 1-2· VAX-1l1725 System Hardware Configuration

1-7

The console subsystem is a microprocessor-controlled, intelligent interface
that communicates with the console terminal and with the remote diagnostic facility. The console terminal is a communications device for the user,
system manager and service engineer; together with the console command
language it provides a valuable tool for debugging programs and performing maintenance functions. Each console terminal has a standard keyboard.
The VT100 or VT200 series of video display terminals or the LA100 or
LA12 printers can be selected as the console device. Two TU58 cartridge
tape drives communicate with the console subsystem and are used to load
the system microcode and to operate microlevel and macrolevel diagnostic
programs. The TU58 drives can be used to bootstrap load the operating
system, to load files into physical memory, and to store files. The switches
and indicators on the control panel are monitored and controlled by the
console subsystem.
Many standard UNIBUS interfaces are either included with the system or
available as options. The UNIBUS cannot be expanded outside the system
cabinet. The interfaces include the DMF32 multifunction communication
controller and the DZll asynchronous serial-line interfaces. The DMRll
option allows synchronous high-speed communication with remote systems and terminals through common-carrier telephone lines.
The DEUNA is a high-performance synchronous communication controller
used in local area network (LAN) applications. The DEUNA connects to the
UNIBUS and allows Digital systems and terminals and systems developed
by other manufacturers to communicate through the Ethernet network.
Ethernet permits data transfer rates of up to 10 Mbits per second between
processors or between processors and devices.
The VSlOO adapter is an option that provides high performance and highresolution text and graphic features in a workstations environment .
• VAX-l 11725 PACKAGE SYSTEM CONFIGURATION
The VAX-1l1725 is available in the following three systems configurations
to meet specific customer applications. Each system contains the VAX-ll/
730 CPU, ECC MOS memory, an RC25 controller, and two TU58 cartridge
tape drives as standard components.
Package A is an entry level system that includes the VAX-1l1730 CPU and
1 Mbyte of ECC MOS memory. One slot is dedicated to memory expansion and one slot is available for memory expansion or for a UNIBUS
interface option. The remaining four slots are available for UNIBUS interface options. Six panel units locations at the rear of the cabinet are available for external cable connectors.

1-8' Introduction

• Package B includes the VAX-1uno CPU, 2 Mbytes ofECC MOS memory,
and a DMF32 multifunction communication controller. One slot is available for memory expansion or for a UNIBUS option, and three backplane
slots are available for UNIBUS interface options. Two connector panel
units at the rear of the cabinet are available for external cable
connectors .
• Package C contains the VAX-1uno CPU, 2 Mbytes ofECC MOS memory,
an FP730 floating-point accelerator, a DMF32 multifunction controller,
and a DEUNA Ethernet controller. One backplane slot is available for
memory or UNIBUS expansion. One panel unit location at the rear of the
cabinet is available for an external cable connector.
VAX-ll/730 Low-end UNIBUS System
The VAX-1uno processor system is an expandable low-end member of
the VAX family that can extend VAX capabilities to almost any environment. It provides up to 24 users with the large program capacity and highperformance features of the larger VAX systems while incorporating
bit-slice and programmed array logic for low power consumption and efficient operation. Space is included in the main cabinet for a variety of
device interfaces and communication options. The VAX-ll/730 system is
contained in a low-height, single-width cabinet that can be placed within
an existing office or laboratory space. As a result, the VAX versatility and
performance can be located at a project or section level within a company.
• VAX-ll/730BASIC SYSTEM
The basic VAX-ll/730 computer system contains the VAX-ll/no CPU, up
to 3 Mbytes of ECC MOS memory, and two TU58 cartridge tape drives as
the console load devices. When I/O device expansion is required, the internal UNIBUS expansion backplane can be used, or a UNIBUS expansion
cabinet the same size as the CPU cabinet can be added externally to the
system. To increase the mass storage capabilities of the VAX-1uno system,
several disk and tape drive controllers are available for addition to the
system cabinet or for mounting in a UNIBUS expansion cabinet. The
UDA50 universal disk adapter can be added to support a combination of
high-capacity disk drives. The execution time of floating-point instructions
and some integer instructions can be decreased by the FPnO floating-point
accelerator option, which mounts within the system cabinet. The basic system components are shown in figure 1-3.

1-9

'Floating Point
Accelerator
(FPA)
Dual russ
Tape Drives

VAX-UI730
CPU

Console
Subsystem
'Battery Backup Unit

C~~ 0

UBA

ECCMOS
Memory
5MB Total

Terminal

·Remote
Diagnostic
Se{Vice

U
N
I
B
U

External UNIBUS Extension
·Optional

Figure 1-3 • VAX-1l1730 SBB System Hardware Configuration

The console subsystem is a microprocessor-controlled, intelligent interface
that communicates with the console terminal and the remote diagnostic
facility. The console terminal is a communications device for the user, system manager, or service engineer and together with the console command
language it provides a valuable tool for debugging programs and performing maintenance functions. The console terminals available with the VAX11/730 are the LAl20 freestanding printer, and the LAlOO and LAl2
tabletop printers. The printers include a standard keyboard. The remote
diagnostic port enables diagnostic maintenance to be performed on the
system from a host processor located at a remote Digital facility. The
remote diagnostic service is supplied with a Digital Field Service contract.

1-10· Introduction

Two TU58 cartridge tape drives communicate with the console subsystem
and are used to load the system microcode and to perform microlevel and
macrolevel diagnositic programs. The TU58 drives can be used to bootstrap load the operating system, to load mes into physical memory, and to
store files that describe and execute bootstrap procedures that are used on
a specific system. The switches and indicators on the control panel operate
through the console subsystem and are used to monitor and control the
operation of the system.
Many standard communication interfaces can be installed on the UNIBUS,
including the DMF32 multifunction communication controller and the
DHUll, DMZ32, and DZll asynchronous serial-line interfaces. The
DMP11,DMR11, and DUP11 options also can be included to allow synchronous high-speed communication with remote systems and terminals
through common-carrier telephone lines. Up to 24 asynchronous communication lines can be connected to the basic system to provide local or
remote terminal access.
The DEUNA is a high-performance synchronous communication controller
used in local area network (LAN) applications. The DEUNA connects to the
UNIBUS and allows communication through Ethernet with Digital systems
and terminals and systems developed by other manufacturers. It permits
data transfer rates of up to 10 Mbits per second between processors or
between processors and devices.
The LP25 and the LP26lineprinters are available to provide hardcopy output from the system. The LP25 prints at 300 lines per minute and the LP26
at 600 lines per minute. The printers connect to the system through the
DMF32 printer port or through a separate controller that mounts on the
UNIBUS.
Th,e UDA50 universal disk adapter can be installed on the UNIBUS and
allows control of up to four disk drive devices, including the RA80 (121Mbyte) and RA81 (456-Mbyte) fixed disk drives, and the RA60 (205Mbyte) removable disk drive in any combination. The UDA50 is an
intelligent controller designed for use with single-CPU systems operating
within the Digital Storage Architecture.
Up to four RL02 (lO.4-Mbyte) disk drives, the RC25 (52 Mbyte) fixed- and
removable-disk drive and the TU80 and TU81 magnetic tape drives are
available to operate with the VAX-ll17 30 processor.
The H9642 general purpose UNIBUS expansion cabinet provides space to
mount the BAll-K expander box into which the DDll UNIBUS backplane
can be installed.
The H7750 memory battery backup unit can be included with the VAX-lli
730 processor to maintain the integrity of the data in memory in the event
of a power failure.

1-11

• VAX-1l1730 SYSTEM BUILDING BLOCK CONFIGURATION
The VAX-1l1730 processor is provided in several VMS and ULTRIX-32
operating system packages that can be configured for specific customer
applications. The system is available with either a VMS operating software
license and warranty or a license for up to 16 users of the ULTRIX-32
operating software. The basic packaged system includes the VAX-ll/no
CPU, 1 Mbyte of ECC MOS memory, an integrated disk controller, and the
DMF32 multifunction communications controller for which a variety of
add-on options are available. The VAX-1l1730 VMS and ULTRlX-32 systems are packaged with an R80 (121-Mbyte) fixed-disk drive and an RL02
(lOA-Mbyte) removable-cartridge disk drive mounted in the CPU cabinet,
or with a R80 disk drive and the TS05 magnetic tape transport mounted in
the CPU cabinet .
• VAX-111730 PACKAGED SYSTEM CONFIGURATION
The VAX-1l1730 is available in the following package system configurations that operate with both VMS and ULTRlX-32 software. Each system
includes the VAX-1l1730 CPU, 1 Mbyte of memory, and a mass storage
subsystem. An I/O connection panel at the rear of the cabinet contains the
cable connector for the console terminal and space for mounting additional connector panel units .
• The VAX-1l1730 R80/TSU05 system includes one R80 fixed-disk drive
system device connected to the REno integrated disk controller, one
TSU08 (48-Mbyte) streaming magnetic tape drive used as a backup load
device, and a DMF32 multifunction communications controller. The system is contained in a single cabinet and includes an LAlOO console
printer terminal. The CPU backplane has prewired designated slots for an
additional 3 Mbytes of main memory and for an FPnO floating-point
accelerator module .
• VAX-111nO R80/RL02 system includes the R80 fixed disk system device,
an RL02 (lOA-Mbyte) removable-disk drive as a backup load device, and
the DMF32 controller. Both disk drives connect to the REno integrated
disk controller. The system is contained in a single cabinet and includes
an LA12 or LAlOO console terminal. The CPU backplane has prewired
designated slots for four additional Mbytes of memory and for the FPno
module.

1-12 • Introduction

VAX-11/750 Midrange System
The VAX-ll/750 processor system is the midrange member of the VAX
family and incorporates many innovations designed to increase performance and to reduce the overall cost to owners. The VAX-ll/750 system
supports up to 64 users and is the smallest VAX member that can be part of
the VAXcluster architecture_ It also operates with Digital's intelligent disk
controllers to offload the disk management functions from the host processor. The VAX-111750 is enclosed in a low-height, extended-width cabinet
and implements custom gate-array technology. The gate arrays are bipolar
LSI Schottky logic designed by Digital specifically for this system to reduce
the number of components to lower power consumption .

• VAX-U/750 BASIC SYSTEM
The basic VAX-ll/750 system configuration is shown in figure 1-4. It contains the VAX-1l/750 CPU, up to 8 Mbytes of ECC MOS memory, and a
TU58 cartridge tape drive as the console load device. A 4-Kbyte bipolar
cache memory with parity is included to improve the processor performance. A 1-Kbyte user writable control store (WCS) option provides customers with the capability of executing application-specific microroutines.
The execution time of floating-point instructions and some integer instructions can be decreased by adding the FP750 floating-point accelerator
option, which mounts within the system cabinet. In addition, the KU750
extended-range G and H floating-point data type option can be added to
further enhance floating-point operations. When 1/0 device expansion is
required, the internal UNIBUS expansion backplane can be used or a lowheight, single-width UNIBUS expansion cabinet can be added.
To increase the mass storage capabilities of the VAX-ll/750 system, several
disk and tape drive controllers are available and can be included in the
system cabinet or in the UNIBUS expansion cabinet. The UDA50 universal
disk adapter supports a combination of high-capacity disk drives.

1-13

'Floating Point
Accelerator
(FPA)

Writable
Control
Store (WCS)
1 KB

TU58
Tape Drive

VAX-ll/750
CPU

ECCMOS
Memory
8MB Total

'Battery Backup Unit

Cache Memory

Console
Subsystem

I
I
I
*console~ A/'A

Memory Interconnect (CMI)

UBA

MBA

DDI

U
N
I
B
U
S

M
A
S
S
B
U
S

3
2

CIA

Terminal

Remote
Diagnostic
Service

D
A
T
A
L

I
N
E
S
7

Standard

Optional

'Optional

Figure 1-4· VAX-111750 System Hardware Configuration

1-14' Introduction

The console subsystem is a microprocessor-controlled, intelligent interface
that communicates with the console terminal and with the remote diagnostic facility. The console terminal is a communications device for the user,
system manager, or service engineer and together with the console command language it provides a valuable tool for debugging programs and
performing maintenance functions. Console terminals that are available for
the VAX-ll/750 are the LA120, LA100, and LA12 printers, each with a
standard keyboard. The remote diagnostic service is an option that allows
diagnostic programs to be performed on the system from a host processor
at a remote Digital facility. The remote diagnostic service is obtained under
a Digital Field Service contract. The TU58 cartridge tape drive, which is
part of the console subsystem, is used to load the system microcode and to
perform microlevel and macrolevel diagnositic programs. The TU58 is also
used to bootstrap load the operating system, to load files into physical
memory, to update software, and to store files that describe and execute
bootstrap procedures used with a specific system. The switches and indicators on the control panel operate through the console subsystem and are
used to monitor and control the operation of the system.
A DW750 UNIBUS adapter (UBA) is included with the processor and a
second UBA can be added to the system. Up to three RH750 MASSBUS
adapter (MBA) options can be added, provided only one UBA is installed,
or two MBA options can be added when two UBA options are installed. The
MBA provides fast data access to the mass storage devices.
Many standard communication interfaces can be installed on the UNIBUS,
including the DMF32 multifunction communication controller and the
DHUl1, DMZ32, and DZll asynchronous serial-line interfaces. The
DMPll, DMRll, and DUPll options can also be included to allow synchronous high-speed communication with remote systems and terminals
through common-carrier telephone lines. Up to 24 asynchronous communication lines can be implemented to the basic system to provide local or
remote terminal access.
The DEUNA is a high-performance, synchronous communication controller used in local area network applications. The DEUNA connects to the
UNIBUS and allows communication through Ethernet with Digital systems
and terminals and systems developed by other manufacturers. It permits
data transfer rates of up to 10 Mbits per second between processors or
between processors and devices.
A maximum of four high-speed printers can be installed, including LP25
and LP26 lineprinters. These printers provide hardcopy output: the LP25
prints at 300 lines per minute and the LP26 at 600 lines per minute. The
printers connect to the system through the DMF32 printer port or through
a separate controller that mounts on the UNIBUS.

1-15

The UDA50 universal disk adapter can be installed on the first UNIBUS and
two UDA50 options can be installed on the second UNIBUS. Each UDA50
controls up to four disk drive devices in any combination, including the
RA80 (121-Mbyte) and the RA81 (456-Mbyte) fixed-disk drives, and the
RA60 (205-Mbyte) removable-disk drive. The UDA50 is an intelligent controller designed for use with single-CPU systems operating within the
Digital Storage Architecture.
The UNIBUS supports up to four RL02 (lO.4-Mbyte) removable-disk
drives, one RC25 (52-Mbyte) fixed- and removable-disk drive, and two
TU80 or two TU81 magnetic tape drives.
A total of eight disk drives or eight magnetic tape formatters, in any combination, can be connected to each MBA. The devices include the RM05 (256Mbyte) removable-disk drives, and the RP07 (516-Mbyte) fixed-disk drive,
which is supported only as a data storage. The magnetic tape drives include
the TE16, TU77, and TU78 and units.
The CI750 Computer Interconnect adapter (CIA) is a microprocessorcontrolled, high-speed interface between the memory interconnect of the
CPU and the dual-path CI bus. It allows information to be transferred at 70
Mbits per second between the VAX-111750 and the VAXcluster components. The CI750 adapter connects to the SC008 Star Coupler through four
coaxial cables with a maximum length of 45 meters (147.6 feet).
The DR32 device interconnect (DDI) is a high-performance general purpose interface that enables communication between VAX processors and
between VAX processors and user devices. It connects to the internal CPU/
memory-interconnect (CMI) bus and provides a 32-bit parallel data path
and an 8-bit parallel control path. The DDI transfers blocks of sequential
data to and from memory at rates up to 6.67 Mbytes per second through
direct memory access (DMA) transfers.
The H7112 memory battery backup unit is available to maintain the integrity of the data in memory in the event of a power failure.
The H9642 general purpose UNIBUS expansion cabinet provides space to
mount the BAll-K expander box in which the DDll UNIBUS backplane
can be installed .
• VAX-1 11750 SYSTEM BUILDING BLOCK CONFIGURATION
The VAX-111750 processor is provided in two basic system
configurations-one that includes the VAX-1l1750 CPU with VAX!VMS
operating software license and one with the VAX-1l1750 CPU and an
ULTRIX-32 operating software license for up to 16 users. The mass storage
devices, communication interfaces, and console devices options are
selected from the System Building Block Menus. The operating so&ware
media and documentation are selected from the menu according to the
mass storage media.

1-16· Introduction

Each basic system contains the VAX-11/750 processor and 2 Mbytes of
ECC MaS main memory. The total memory can be expanded to B Mbytes.
An H9642 general purpose UNIBUS expansion cabinet is available with the
basic system to allow expansion of the system 110 capabilities. The mass
storage devices include system and load devices that are selected from the
menu to conform to the system mass storage requirements. The system
storage devices include the RA60, RABO, RAB1, and RM05 disk drives. The
system load devices are the TU77, TU7B, TUBO, and TUB1 magnetic tape
units and the RA60 disk drive. The communication interfaces and controllers are the DMF32, DZ11, DHU 11 , DMZ32, and the DEUNA options .
• VAX-11/750 VAXCLUSTER CONFIGURATIONS
The VAX-ll/750 VAX!VMS systems are available in a VAXcluster system
building block (SBB) configuration and a VAXcluster upgrade configuration. These systems are designed to operate within the VAXcluster architecture. Each system includes the VAX-11/750 CPU, 4 Mbytes of ECC MaS
memory, a CI750 adapter and connecting cables, the VAXlVMS operating
system license and warranty, and the DECnet software license.
The VAX-ll/750 VAXcluster SBB configuration contains the VAXcluster
hardware, including the SCOOB Star Coupler unit and an HSC50 intelligent
mass-storage server unit, to which other VAX systems and mass storage
devices can be connected. The system storage devices that can be selected
from the menu include RA60, RABO, and RAB1 disk drives. The communication interfaces and controllers on the menu are the DMF32, DZll,
DHUll, DMZ32, and the DEUNA options.
The VAXcluster upgrade configuration is designed to attach to the existing
VAXcluster architecture through the CI750 adapter and cables. The system
storage devices that can be selected by menu are the RA60, RABO, and RAB1
disk drives. The communication interfaces and controllers on the menu are
the DMF32 , DZ11, DHUl1, DMZ32, and the DEUNA options.

VAX-1l/780 Original VAX System
The VAX-lI/7BO computer system is the original VAX system developed to
meet the needs of users with large databases and extensive processing
requirements. This high-performance system uses proven Schottky TTL
(transistor-transistor logic) technology and can support more than 100
active users. The processor is contained in a full-height, double-width cabinet and provides space for device interfaces and controllers and,for communication options. The VAX-lI/7BO system supports a complete line of
peripheral devices and is compatible with Digital Network Architecture,
Digital Storage Architecture, and VAXcluster architecture.

1-17

• VAX-11/780 BASIC SYSTEM CONFIGURATION
The basic VAX-11/780 system is shown in figure 1-5 and contains the VAX11/780 CPU, up to 16 Mbytes of ECC MaS main memory, an RX01 console
load device and I/O expansion capabilities. The H9652 full-height, singlewidth, UNIBUS expansion cabinet also is included with the system. An
additional 16 Mbytes of ECC MaS memory can be added to the system by
including the H9652-H optional CPU expander cabinet. The execution
time of floating-point instructions and some integer instructions can be
decreased by the addition of the FP750 floating-point accelerator option in
the CPU backplane. The KU780 option is a 2-Kbyte user-control-store
option that also mounts in a dedicated slot of the CPU backplane and
provides control store space for the KE780 extended-range G and H
floating-point data type option and the QE109-CY microprogramming
tools option.

'Floating Point
Accelerator
(FPA)
RXOl Disk
Drive

VAX-ll/780
CPU

Console
Subsystem

VAX-ll/780 or

User
Writable
Control
Store (WCS)

V~l1DD
ECC MOS
Memory

*MA780
Multiport
Memory
32 MB Total 8 MB Total
Cache
Memory

'Battery Backup Unit

I I
~,7O:~) r / "IA A

Memory Interconnect (SBI)

'RemoteJ
Diagnostic
Service

UBA

MBA

DDI

U
N
I
B
U
S

M
A
S
S
B
U
S

3
2

CIA

D
A
T
A
L
I
N
E

,
'Optional

Standard

" S .,

Optional

Figure 1-5· VAX-111780System Hardware Configuration

1-18· Introduction

The console subsystem is a microprocessor-controlled, intelligent interface
that communicates with the console terminal and with the remote diagnostic facility. The console terminal is a communication device for the user,
system manager, or service engineer. Together with the console command
language it provides a valuable tool for debugging programs and performing maintenance functions. The console terminals available for the VAX11/780 system are the LA120 freestanding printer and the LAlOO tabletop
printer. The terminals include a standard keyboard. The remote diagnostic
service is an option that allows diagnostic programs to be performed on the
system from a host processor at a Digital facility. The remote diagnostic
service is obtained by Digital Field Service contract. The RXOI disk drive is
part of the console subsystem and is used to load the system microcode and
to perform microlevel and macrolevel diagnostic programs. The RXOI disk
drive also is used to bootstrap load the operating system, to load flies into
physical memory, to update software, and to store files that describ~ a specific system and execute bootstrap procedures that are used on a system.
The switches and indicators on the control panel operate through the console subsystem and are used to monitor and control the operation of the
system.
A DW780 UNIBUS adapter (UBA) is included with the processor and three
UBA options can be added to the system. A total of four MASSBUS adapter
(MBA) options can be included when only one UBA is installed. When two
UNIBUS adapters are installed, two MBA options can be included. The
MBA provides fast access to the data on the mass storage devices.
Many standard communication interfaces can be installed on the UNIBUS,
including the DMF32 multifunction communication controller and the
DHUll, DMZ32, and DZll asynchronous serial-line interfaces. The
DMPll, DMR11 , and DUP11 options can also be included to allow synchronous high-speed communication with remote systems and terminals
through common-carrier telephone lines. Up to 24 asynchronous communication lines can be connected to the basic system to provide local or
remote terminal access.
The DEUNA is a high-performance synchronous communication controller
used in local area network (LAN) applications. The DEUNA connects to the
UNIBUS and allows communication through the Ethernet network with
Digital systems and with terminals and systems developed by other manufacturers. The DEUNA permits data transfer rates of up to 10 Mbits per
second between processors or between processors and devices.

1-19

A UDA50 universal disk adapter (UDA) can be installed on the first
UNIBUS and two UDA50 options can be installed on each of the three
UNIBUS options. Each UDA50 can control up to four disk drive devices,
including the RA80 (121-Mbyte) and the RA81 (456-Mbyte) fixed-disk
drives, and the RA60 (205-Mbyte) removable-disk drive in any combination. The UDA50 is an intelligent controller designed for use with single
CPU systems that operate within the Digital Storage Architecture.
A maximum of 16 high-speed line printers can installed, including LP25
and LP26 lineprinters. These printers provide hardcopy output: the LP25
prints at 300 lines per minute and the LP26 prints at 600 lines per minute.
The printers connect to the system through the DMF32 printer port or
through a separate controller that mounts on the UNIBUS.
The UNIBUS also supports up to four RL02 (10.4-Mbyte) removable-disk
drives, one RC25 (52-Mbyte) fixed- and removable-disk drive, and two
TU80 or two TU81 magnetic tape drives.
Disk drives or magnetic tape formatters in any combination totaling eight
can be connected to each MBA. The devices include the RM05 (256-Mbyte)
removable-disk drives, and the RP07 (516-Mbyte) fixed-disk drive, which is
supported only as a data storage. The magnetic tape drives include the
TE16, TU77, and TU78 unit.
The CI780 Computer Interconnect adapter (CIA) is a microprocessorcontrolled, high-speed interface between the synchronous backplane interconnect (SBI) of the CPU and the dual-path CI bus. It allows information to
be transferred at 70 Mbits per second between the VAX-1I/780 and the
VAXcluster components. The CI750 adapter connects to the SC008 Star
Coupler through four coaxial cables with a maximum length of 45 meters
(147.6 feet). Through the VAXcluster network, the overall system efficiency
is greatly increased by sharing the processor loads and by providing access
to common mass storage facilities.
The DR32 device interconnect (DDl) is a high performance generalpurpose interface that permits communication between VAX processors
and between VAX processors and user devices. It connects to the SBI bus
and provides a 32-bit parallel data path and an 8-bit parallel control path.
The DDl transfers blocks of sequential data to and from memory at rates
up to 6.67 Mbytes per second through direct memory access (DMA)
transfers.
.
One H71I2 memory battery backup unit is required for each memory controller on the VAX -11/780 VAXIVMS system to maintain the integrity of the
data in memory in the event of a power failure.

1-20· Introduction

• VAX-111780 SYSTEM BUILDING BLOCK CONFIGURATIONS
The VAX-lll7 80 processor is provided in two basic system
configurations-one that includes the VAX-1l1780 CPU and a VAX!VMS
operating software license and warranty, and one with a VAX-111780 CPU
and an ULTRIX-32 software license for up to 16 users. Mass storage
devices, communication interfaces, and console devices options are
selected from the System Building Block Menus. The operating software
media and documentation are selected from the menu according the type
of mass storage media selected.
Each basic system contains the VAX-1l1780 processor,2 Mbytes of ECC
MOS main memory, and an H9652 UNIBUS expansion cabinet. The total
memory can be expanded to a maximum of 8 Mbytes. The mass storage
devices include a system device and load devices that are selected from the
menu to conform to the mass storage requirements. The system storage
devices include the RA60, RA80, RA81, and RM05 disk drives. The system
load devices include the TU77, TU78, TU80, and TU81 magnetic tape units
and RA60 disk drive. The communication interfaces and controllers are the
DMF32, DZ11, DHUl1, DMZ32 , and the DEUNA options .
• VAX-1l1780VAXCLUSTERCONFIGURATION
The VAX-111780 VMS systems are available in a VAXcluster system building block (SBB) configuration and a VAXcluster upgrade configuration.
These systems are designed to operate within the VAXcluster architecture.
Each system includes the VAX-111780 CPU, 4 Mbytes of ECC MOS memory, a CI750 adapter and connecting cables, an H9652 UNIBUS expansion
cabinet, a VAX!VMS operating system license and warranty, and a DECnet
software license.
The VAX-1l1780 VAXcluster SBB configuration contains the VAXcluster
hardware, including the SC008 Star Coupler unit and the HSC50 intelligent
mass-storage server unit, to which other VAX systems and mass storags
devices can be connected. System storage devices that can be selected from
the menu include the RA60, RA80, and RA81 disk drives. The load devices
are the TU78 magnetic tape unit and RA60 disk drive. The communication
interfaces and controllers on the menu are the DMF32, DZll, DHUll,
DMZ32, and the DEUNA options.
The VAXcluster upgrade configuration is designed to attach to an existing
VAXcluster configuration through the CI750 adapter and cables. System
devices that can be selected from the System Building Block Menu are the
RA60, RA80, and RA81 disk drive. The communication interfaces and controllers on the menu are the DMF32 , DZll, DHUll, DMZ32 and the
DEUNA options.

1-21

VAX -111782 Attached-processor System
The VAX-111782 attached-processor system is a tightly coupled, asymmetrical multiprocessor system based on a MA 780 multiport shared memory.
The system can provide up to 1.8 times the performance of the VAX-111
780 system. The VAX-1l1782 consists of two VAX-1l1780 processors and a
4-Mbyte MA780 shared main memory mounted between the VAX CPU cabinets. The main memory can be expanded to 8 Mbytes by adding a second
MA780 multiport memory cabinet containing 4 Mbytes of memory. One
VAX-111780 CPU, designated the primary processor, contains 256 Kbytes
of local ECC MOS memory for diagnostics programs, a shared memory
interface, and a DW780 UNIBUS adapter. All I/O devices and peripheral
devices connect to the primary processor. The second CPU is designated
the attached processor and contains 256 Kbytes of local memory for diagnostic testing and a shared memory interface. The attached processor does
not support I/O devices.
The UNIBUS and MASSBUS adapters and the CI and DDI adapters available
for the primary processor are the same as those used with the single VAX111780 processor system. The mass storage devices available for the primary processor are also the same as those used with the single VAX-1l1780
processor system. The VAX-111782 processor system cannot be connected
to VAXcluster components. A UNIBUS expansion cabinet can be added to
the VAX-111782 system. The FP782 floating-point accelerator option can
be added to each VAX-111780 processor to decrease the execution time of
the floating-point operations and some of the integer arithmetic operations. Figure 1-6 shows the hardware configuration of the VAX-111782
system .
• VAX-1l1782 SYSTEM BUILDING BLOCK CONFIGURATION
The VAX-111782 attached processor system operates with VMS operating
software to provide a reliable high-performance environment for the
shared processor operations. The basic system includes two VAX-111780
processors, 4 Mbytes of ECC MOS shared memory, an H9652 UNIBUS
expansion cabinet with a BAl1-K expansion box, and DD11-DK backplane.
The total shared memory can be expanded to 8 Mbytes. Mass storage,
communication, and console devices and interface options can be added to
the basic system from the System Building Block Menus. They are the same
as those listed on the VAX-111780 VAXIVMS System Building Block Menu.

"Floating
Point
Accelerator

(FPA)

User

"Floating

User

Writable
Control
Store (WCS)

Point
Accelerator

Writable
Control
Store (WCS)

(FPA)

...

RXOl Disk
VAX-ll/780
CPU

Drive

Primary Processor

ECCMOS
Memory
256KB Total

Battery Backup Unit"

Cache Memory

Console
Subsystem

c=o":1

Terminal

*Remote
Diagnostic
Service

Memory Interconnect (SBI)
UBA

I MBA

DDI

/'-

U
N
I
B
U
S

M
A
S
S
B
U
S

3
2

'.I

SharedECC
MOSMemory
8MB Total

VAX-ll/780
CPU
Attached Processor
"Battery Backup Unit

R
ECCMOS
Memory
256KB Total
Cache Memory

Memory Interconnect (SBI)

I CIA I

D
A
T
A

L
I
N
E
S
. .1

4
1
1
1
Standard Optional Optional Optional
3
Optional
"Optional

Figure 1-6' VAX-1l1782 Attached-processor System Hardware Configuration

1-23

The operating software media and documentation is also selected from the
menu according to the mass storage devices selected. The UNIBUS expansion cabinet is included with the basic system to allow expansion of the
system 1/0 capabilities. The mass storage devices include both a system
device and load devices that are selected from the menu to conform to the
system data storage requirements. The system storage devices include the
RA60, RA80, RA81, RM05, and RP07 disk drives and the system load devices
include the TU77, TU78, TU80, TU81 magnetic tape units and the RA60
disk drive. The communication interfaces and controllers are the DMF32,
DZlI, DHUlI, DMZ32, and DEUNA options.
VAX-ll/785 Extended-performance System
The VAX-ll/785 extended-performance system was designed with Fairchild Advanced Schottky Technology FAST* and improved logic circuits
to provide up to 1.5 times the performance of the VAX-ll/780 processor.
The system is available in the same basic system configurations as the
VAX-ll/780 processor shown in figure 1-5. It includes VMS and ULTRIX-32
operating systems and the VAXcluster and VAXcluster upgrade configurations. The VAX-ll/785 processor contains the standard instructions for
packed-decimal floating- (G and H data types) and fixed-point arithmetic,
character, and string manipulations. It also includes RAM-based microcode, 8 Kbytes of writable-control-store, 48-Kbyte console memory,
and a 32-Kbyte two-way set-associative cache memory. The FP785
floating-point accelerator option can be added to the VAX-ll/785 processor to decrease the execution time of the floating -point operations and some
of the integer arithmetic operations. The system is also available as a replacement CPU module set; for a small increase in cost, the improved CPU
logic modules can be installed in an existing VAX-ll/780 or VAX-ll/782
system to provide more processing power, higher throughput, and the ability to support more users. All other system hardware and software configurations are the same as described the VAX-ll/780 system.

*FAST is a trademark of Fairchild Camera and Instrument Corporation.
VAX 8600 High-performance System
The VAX 8600 processor is the most powerful member of the VAX family
and is the first VAX system designed for large-scale VAX computing. The
VAX 8600 processor provides up to 4.2 times the performance of the industry standard VAX-ll/780 processor 'and has the power; performance and
capacity required for the high-speed processing of large applications. It
conforms to the VAX architecture, making it compatible with other VAX
processors.

1-24· Introduction

The VAX 8600 system supports extensive scientific, engineering, and
realtime applications, including artificial intelligence, simulation, and
computer-aided design. It also supports large, general purpose timesharing
applications in government, commercial, administrative, and academic
environments. It provides the performance required for large, complex
multiuser applications and the I/O capacity for large timesharing applications. It provides VAX customers with a means of expanding PDP-11, VAX11/725, VAX-11/nO, VAX-111750, VAX-111780, VAX-111782, VAX-111785,
DECsystem-lO, and DECSYSTEM-20 systems to meet new application
requirements.
The VAX 8600 processor incorporates the latest in proven technological
advancements, including customized emitter-coupled (ECL) gate-array
logic and four-stage instruction pipeline processing. The customized ECL
logic allows more components to be included on a module and provides a
significant increase in processing speed. The pipeline processing of instructions enables the processor to operate on four instructions simultaneously,
thereby reducing the number of cycles required for each instruction. A 16Kbyte write-back cache memory maintains the processing speed by updating the main memory during memory access operations.
The VAX 8600 processor includes virtual memory management, a bootstrap loader, standard instructions for packed decimal, floating (F, D, G,
and H data types) and fixed-point arithmetic, and character and string
manipulations. Also included is a 16-Kbyte write-back cache memory,
high-precision realtime programmable clock, time-of-year clock with battery backup, and 8 Kwords (86-bit words) of writable control store.
The VAX 8600 processor includes a synchronous backplane interconnect
adapter (SBIA) and a second adapter SBIA can be added to expand the I/O
capabilities of the system. The communications path between the CPU and
main memory is through internal memory bus, which effectively decreases
the memory access time. The SBIA is used only for communications
between devices and memory; therefore, the speed and efficiency of the
I/O transfers are increased.
The dependable performance of large program applications is ensured by
extensive self-diagnostic and maintenance features incorporated in the
VAX 8600 system. The automatic error checking and correcting of main
memory and cache memory data eliminates many types of errors without
interrupting the system operation. When a problem exists, an internal diagnostic bus, connected to all main logical elements, can be used to sample
data and isolate the failing logic.
Environmental sensors monitor the physical environment of the VAX 8600
system and provide a warning when the environmental conditions are not
acceptable.

1-25

• VAX 8600 BASIC SYSTEM
The basic configuration of the VAX 8600 processor is shown in figure 1-7.
Up to 32 Mbytes of ECC MOS main memory can be included in each processor. Each memory array contains 4 Mbytes of storage implemented with
256-Kbit integrated circuits (ICs). The FP86 floating-point accelerator
(FPA) is included with the processor and operates with the CPU to substantially decrease the instruction execution time of all floating-point arithmetic instructions, floating-point data types, and some of the integer
arithmetic operations.

Floating Point
Accelerator
(FPA)
RL02Disk
Drive

Writable
Control
Store (WCS)

VAX 8600
CPU

ECCMOS
Memory
32MB Total

Console
Subsystem
Battery Backup Unit

Cache Memory

SBIAO

::o!J

UBA

I CIA

SBIA 1
UBA

/"; A

U
N
I
B
U
S

Terminal

Remote _ _
Diagnostic
Service

I MBA I DDI I CIA

U
N
I
B
U
S

M
A
S
S
B
U
S

3
2
D
A
T
A
L
I
N
E
S

"
Standard

Optional

optional

Optional

Figure 1-7 • VAX 8600 System Hardware Configuration

1-26· Introduction

The console subsystem is an intelligent microprocessor-controlled interface for the console terminal, console load device, environmental monitoring module circuits, remote diagnostic port, and control paneL The LAlOO
tabletop printer is used as the console terminal and includes a standard
keyboard_ The console load device is an RL02 disk drive providing lOA
Mbytes of storage on a removable disk. The RL02 drive is used to load the
system microcode, to perform microlevel and macrolevel diagnostic programs, to bootstrap load the operating system, to load files into physical
memory, and to store ftles that describe and execute bootstrap procedures
that are used with a specific system_ The environmental monitoring module
,checks and controls the internal temperature, cooling air flow, power supply voltages and other conditions within the main system cabinets. The
remote diagnostic port connects to a Digital remote diagnostic service center, which can perform diagnosic tests on the VAX 8600 system. A DF1l2
modem is supplied for remote port communications with systems installed
in the United States and Canada. The switches and indicators on the control panel are monitored and controlled by the console subsystem.
The 110 subsystems connect to the CPU through the DB86 synchronous
backplane interconnect adapters (SBIA 0 and SBIA 1). SBIA 0 is included
with the system and SBIA 1 can be added in the CPU cabinet. The SBIA 0
bus can be extended from the CPU cabinet into an SBI expansion cabinet.
A DW780 UNIBUS adapter (UBA) is included with the system and connects
to SBIA 0, and two UBA options can be added to SBIA O. The CI780 computer interconnect adapter (CIA) is optional and can also be connected to
SBIA 0 for VAXcluster configuration.
UNIBUS, MASSBUS, CI, and DDI adapters can be installed on SBIA 1. A
maximum of four UBA options, four optional RH780 MASSBUS adapters
(MBAs), four optional DR780 DR32 adapters (DDIs), or two CIA options
can be installed on SBIA 1. The combination of UBA, MBA, CIA, and DDI
options on the SBIAs depends on the total number and type of adapters
installed.
Several standard UNIBUS communication interfaces may be included with
the system and many are available as options. These interfaces include the
DMF32 multifunction communication controller and the DHUll, DMZ32,
and DZll asynchronous serial-line interfaces. The DMPll, DMRll, DRll,
and DUPll options can also be included to allow synchronous high-speed
communication with remote systems through common-carrier telephone
lines.

1-27

The DEUNA is a high-performance synchronous communication controller
used in local area network applications. The DEUNA connects to the
UNIBUS and allows communication through the Ethernet network with
Digital's systems and terminals, and systems developed by other manufacturers. The DEUNA permits data transfer rates of up to 10 Mbits per second between processors or between processors and devices.
One UDA50 universal disk controller can be installed on the UNIBUS to
control up to four disk drives, including the RA60 (205-Mbyte) removabledisk drive, the RA80 (l21-Mbyte) fixed-disk drive, and the RA81 (456Mbyte) fixed-disk drive, in any combination. The UDA50 is an intelligent
controller designcd for use with single-CPU systems that operate within the
Digital Storage Architecture.
A maximum of 16 high-speed line printers can be installed, including
LP25, LP26, and LP27 lineprinters. These printers provide hardcopy output: the LP25 prints at 300 lines per minute, the LP26 prints at 600 lines
per minute, and the LP27 at 1,200 lines per minute. The printers connect to
the system through the DMF32 printer port or through a separate controller that mounts on the UNIBUS.
The UNIBUS also supports up to four RL02 (1OA-Mbyte) removable-disk
drives and a maximum of four TU81 magnetic tape drives.
Disk drives and magnetic tape formatters in any combination up to a total
of eight can be connected to each MBA. The devices include the RM05
(256-Mbyte) removable-disk drive and the TEI6, TUn, and TU78 magnetic tape units.
The CI780 computer interconnect adapter (CIA) is a microprocessorcontrolled, high-speed interface that connects the SBI bus to the dual-path
CI bus. Information is transferred at 70 Mbits per second between the VAX
8600 and the VAXcluster components. The CI780 adapter cables connect
to the SC008 Star Coupler unit through two receive and two transmit coaxial cables, each with a maximum length of 45 meters (147.6 feet). Through
the VAXcluster, the overall system efficiency is greatly increased by sharing
the processor loads and by providing access to common mass-storage
facilities.
The DR780 DR32 device interconnect (DDI) is a high-performance, general
purpose interface that permits communication between VAX processors
and between VAX processors and user devices. It connects to the SBI bus
and provides a 32-bit parallel data path and an 8-bit control path. The DDI
transfers blocks of sequential data to and from memory at rates up to 6.67
Mbytes per second through direct memory access (DMA) transfers.

1-28· Introduction

The H7112 battery backup unit is included with the VAX 8600 processor to
maintain the integrity of up to 32 Mbytes of data in memory in the event of
a power failure.
The H9652 UNIBUS expansion cabinet provides the space for mounting
two BA11-A UNIBUS expansion boxes that contain the UNIBUS
backplanes.
The H9652 SBI expansion cabinet provides space for mounting additional
SBI interfaces, including DW780 UNIBUS adapters, RH780 MASSBUS
adapters, CI780 adapters, and DR780 adapters .
• VAX 8600 VAXCLUSTERCONFIGURATION
The VAX 8600 systems are available in two VAXcluster configurations: the
VAX 8600 VAXcluster system building block (SBB) and VAX 8600 VAXcluster upgrade. Each system includes the VAX 8600 CPU, 12 Mbytes of ECC
MOS memory, the FP86 floating-point accelerator, the CI780 adapter and
connecting cables, the DMF32 multifunction communication controller,
four DMZ32-M asynchronous multiplexers, and the DEUNA Ethernet communications controller. The systems are supplied with a VAX/VMS operating software license and a DECnet-VAX full-function license. The main
memory of each configuration can be expanded in 4-Mbyte increments to a
total of 32 Mbytes.
The VAX 8600 VAX cluster SBB system includes all the VAXcluster components needed to connect the VAX 8600 to other VAX systems and HSC50
intelligent mass-storage servers in a VAXcluster configuration. The system
includes an SC008 Star Coupler unit, an HSC50 intelligent I/O mass storage
server unit, and connecting cables. The system storage devices available are
the RA60, RA80, and the RA81 disk drives. The load device is the TA78
magnetic tape unit. The type of software media, software support documentation and the level of software service is selected from the menu. The
LAlOO is used as the console terminal.
The VAX 8600 VAXcluster upgrade system is designed to be connected to
existing VAX cluster configuration and includes the CI780 adapter and
required interconnecting cables. No system or load devices are offered
from the SBB menu. The LAlOO is used as the console terminal.

1-29

. VAX System Characteristics
The VAX system hardware and software are combined to ensure efficient
and reliable system operation. The VAX hardware architecture and the
VMS or ULTRIX-32 operating systems and layered software and languages
provide the compatibility required between VAX systems. To give VAX systems their impressive performance, the architecture incorporates 32-bit
addressing, up to four billion bytes of virtual memory, an address translation and prefetch instruction buffer, an optional floating-point accelerator,
and the powerful VAX instruction set. All VAX systems provide an attractive cost-performance ratio that makes the systems ideal for applications
tailored for specific tasks. The high computational ability and large program size mean that VAX systems can handle tough realtime applications.
The VMS operating system provides extensive facilities for good batch
performance, including job control, multistream, spooled input and output, operator control, conditional command branching, and accounting
functions. A choice of options - additional physical memory, user-controlstore, additional peripheral equipment interfaces and others-allow even
greater flexibility in configuring systems to optimize performance for specific applications.
Ease of Use

VAX systems are user-oriented and designed for easy operation. The Digital
Command Language (DCL) used by the VAXIVMS system is easy to learn
and suitable for both interactive and batch environments. The software
compatibility of VAX systems allows software developed for one VAX system to run on another VAX system without modification. Because VAX
systems use the same instruction set, users can take full advantage of
another VAX system's capabilities. VMS provides extensive system management facilities, giving system managers and operators the tools necessary to
control the system configuration and the operations of system users for
maximum efficiency. Extensive help commands are available and the systems include complete multiuser security. Except for the MicroVAX, the
VAX family of processors also implement a PDP-ll compatibility mode,
which recognizes most of the PDP-ll instructions. With few exceptions,
this allows users to execute code written for the PDP-ll. The VAX console
subsystem also contributes to the ease of use with a separate console terminal and a carefully designed console command language that lets the users
perform such operations as examines and deposits, or bootstrap load the
system program using simple commands. The console terminal also provides a hardcopy of console transactions. Switches on the front panel of the
CPU can be set to reboot the system automatically, without operator intervention, in the event of a power failure or interrupted operation.

1-30· Introduction

VAX systems are designed to facilitate rapid, low-cost applications development. With the complete set of VMS and ULTRIX-32 development tools,
file system features, optional information management products, and other
software packages, applications are easier to develop and require less
debugging time. Digital's extensive educational services are also available
to train and assist users in exploiting the wide and varied capabilities of
VAX systems.
Installation and Maintenance

The VAX systems are easily tuned and adapted, so additional peripherals
and options can be interfaced at any time. The VAXcluster network capability insures that the system will never be outdated because of limited
processing power and mass data storage requirements. Customers may
choose a wide variety of peripherals and packaging options to configure a
VAX system to suit their requirements, whether the site is an office, a laboratory, or an industrial setting. Once the system is installed, extensive reliability, availability, and maintainability features in both the hardware and
the software ensure data integrity and increase system uptime. Features
such as ECC (error correction code) memory, online error logging, and a
complete range of online and stand-alone diagnostics verify system integrity and help ensure proper system operation. The remote diagnosis option
allows VAX system to be directly linked to a Digital diagnostic center for
diagnosis of hardware and software failures. For smaller VAX systems, the
diagnostics can be performed by a system user to verify proper hardware
operation and quickly isolate system failures at the subsystem or device
level. The. remote support option, using remote diagnosis technology, gives
the Digital service engineer a further level of technical resources.
Long-term Investment

The features of the VAX systems hardware and software, combined with the
VAXcluster architecture and complete series of VAX processors, devices,
and options, assure Digital's commitment to the continued development
and support of VAX computers. These systems can be tailored to individual
application requirements and they can be easily expanded or reconfigured
if those needs should change in the future, an important consideration for
customers involved in long-term projects and implementations.
Architecture Overview
The VAX family archite,cture is characterized by a powerful and complete
set of 304 instructions, a wide range of data types, an efficient set of
addressing modes, complete demand-paging memory management, and a
large virtual address space of over 4 billion bytes.

1-31

• VAX INSTRUCTIONS AND DATA TYPES
VAX instructions and data vary in length and may begin at odd or even byte
addresses without being aligned on longword boundaries in physical memory. Instructions not requiring arguments use only one byte, and other
instructions may require up to 54 bytes, depending on the number of arguments and their addressing modes. The advantage of byte alignment is that
instruction streams and data structures can be stored in less physical memory. Because the VAX instruction set is so flexible, most functions require
fewer instructions and less storage than on other processors. The result is
more compact and efficient programs, faster program execution, faster
context switching, more precise and faster math functions, and improved
compiler generated code.
The VAX native instruction set is an extension of the PDP-ll instruction set
and can be grouped into classes based on their functions and uses:
• Arithmetic and Logical Data Types- These include integer, floating point,
packed decimal, character string, and bit field. The data type identifies
the number of stored bits to be considered as a unit and the method of
interpreting the unit. Integer, floating point, packed decimal, and character data are stored starting on an arbitrary byte boundary. Bit and bit field
data start on an arbitrary bit boundary. A collection of data structures can
be packed together to use less storage space. The following data types
maybe used.

- Integer are byte (8 bits), word (16 bits), longword (32 bits), and
quadword (64 bits).
-Floating point are 4-byte F _floating, 8-byte D _floating, 8-byte
G _floating, and 16-byte H _floating.
- Packed decimal are strings of up to 31 decimal digit bytes with two
digits per byte.
-Character strings are up to 64 Kbytes interpreted as a string of character codes. A numeric string is a character string of codes for decimal
numbers up to 31 digits.
-Bits and bit-field are arbitrary field lengths defined by the programmer
as from 0 to 32 bits.
• Special kinds 0/ data- These instructions are used extensively by the VMS
operating system and include queue manipulation instructions that insert
and remove queue entries, address manipulation instructions, and userprogrammed general register load and save instructions.
• Basic program /low- These instructions include branch, jump, and case
instructions, subroutine call instructions, and procedure call instructions.

1-32' Introduction

• Special operating system /unctions- These instructions provide rapid and
efficient rescheduling of the operating system functions. They include
process control instructions such as context switching, which allows process context variables to be loaded and saved using one instruction for
each operation. The find-first instruction allows the operating system to
locate the highest-priority executable process.
• High-level language constructs-During the design of the VAX architecture, special attention was given to implementing frequently used, highlevel language constructs as single VAX instructions. These instructions
contribute to decreased program size and increased execution speed.
Some of the single VAX instructions include:

- The FORTRAN-computed GOTO statement that translates into the case
instruction.
- The loop construct such as add, compare, and branch that translate into
the ACB instruction.
- An extensive call facility that aligns the stack on a longword boundary,
saves user-specified registers, and cleans up the stack on return. The
call facility is used for compatibility among all native-mode languages
and operating system services.
• Addressing modes- The VAX processors offer several addressing modes,
many of which use the general registers to identify the operand location
as PDP-11 addressing modes do. The modes are

-Register
- Register deferred
- Autoincrement
- Autoincrement deferred
- Autodecrement
- Byte, word, and longword displacement
- Byte, word, and longword displacement deferred
-Indexed
-Literal

1-33

• GENERAL REGISTERS AND STACKS
The VAX processors provide sixteen 32-bit general registers that can be
used for temporary storage, or as accumulators, index registers, and base
registers. Registers RO through R11 can be used as general purpose registers
and the remaining four have special functions depending on the instruction
being executed. The registers are R12 (argument pointer), Rl3 (frame
pointer), R14 (stack pointer) and R15 (program counter). Stacks are associated with the processor's execution state. The processor may be in one of
four process context modes-kernel, executive, supervisor, or user modeor in the systemwide interrupt service context. A stack pointer is associated
with each of these states. Whenever the processor changes from one state
to another, register 14 is updated accordingly.
Software Overview
The VMS operating system and the ULTRlX-32 operating systems provide
the basic system management and control. The operating systems organize
and allocate the system resources and files to insure the protection of data
and the efficient system operation .

• VMS OPERATING SYSTEM
The VMS system is a general purpose multiuser, multifunction operating
system that is compatible with all VAX processors and provides reliability
and high-performance for the concurrent execution of multiuser
_timesharing, batch, and time-critical applications. VAXNMS features
include the following:
• Virtual memory management for executing large programs.
• Event-driven priority scheduling.
• Shared memory, file, and interprocess communication data protection
based on ownership and application groups.
• Programmed system services for process and subprocess control and
interprocess communication.
The VAX memory management features allow swapping, paging, protection, and sharing of both code and data. Memory is allocated dynamically
and applications can control the amount of physical memory allocated to
executing processes, to the protection of pages, and to swapping. These
controls can be added after the application is implemented.
CPU time and memory residency are scheduled on a preemptive priority
basis. Therefore, time-critical processes do not compete with lower-priority
processes for scheduling services. Scheduling rotates among processes of
the same priority.

1-34· Introduction

The VMS includes system services to control processes and process execution, time-critical response, and scheduling; and to obtain information.
Process control services allow the creation of subprocesses as well as independent detached processes. Processes can communicate and synchronize
using mailboxes, shared areas of memory, or shared files. A group of processes can also communicate and synchronize, using multiple commonevent flag clusters.
Memory access protection is provided between and within processes. Each
process has its own independent virtual address space, which can be
mapped to private pages or shared pages. VMS uses the four processoraccess modes to read-protect and write-protect individual pages within a
process. Protection of files, shared pages of memory, and interprocess communication facilities such as mailboxes and event flags, are based on user
identification codes that are assigned individually to accessors of data.
A complete program development environment is offered and supported
by the VAXlVMS system. It includes the native assembly language, VAX
MACRO, and the following high-level programming languages: VAX APL,
VAX BASIC, VAX BLISS-16, VAX BLISS-32, VAX C, VAX COBOL,
VAX CORAL 66, CORALIVAX to RSX Cross Compiler, VAX DIBOL,
VAX FORTRAN, VAX PASCAL, VAXPLlI,FORTRAN IVIVAXto RSX
Cross Compiler, VAX LISP, and VAX RPG II. It provides the tools necessary to write, assemble, compile, and link programs, as well as to build
libraries of source, object, and image modules.

In/ormation Management- The VMS operating system supports a set of
software tools that provides a full range of information management capabilities. These information management products can be used to organize,
maintain, retrieve, and manipulate data quickly and easily. They include the
following:
VAX ACMS product set provides tools to develop and control complex
online transaction processing applications.
VAX Common Data Dictionary provides a single, logical data dictionary
as a common source and contain descriptions for language and information management tools, including VAX DATATRIEVE and VAX ACMS.
VAX DATATRIEVE is a multifaceted data management facility that can
store, update, and retrieve information and generate reports.
VAX DBMS is a CODASYL-compliant database management system for
creating, maintaining, and updating databases .
• VAX DSM is a multiuser data management system and a high-level interpretive language for Digital Standard MUMPS (DSM).

1-35

• VAX PAis is a forms management system with interactive and languagecallable video forms.
VAX Rdb/VMS is a full-function, relational database management system
for local and remote database applications operating under VMS
software.
VAX Rdb/ELN is a highly functional, relational database management
system designed for the VAXELN operating environment.
VAX-ll RMS is a record management facility for sequential, relative, and
multikey ISAM (indexed sequential access method) file organizations.
VAX TDMS is a terminal data management system and a programming
tool for form-intensive applications operating with the VAXNMS operating system.
The VMS on-disk structure provides a multiple-level hierarchy of named
directories and subdirectories. Files can extend across volumes and can be
as large as the volume set on which they reside. Volumes are mounted to
identify them to the system. VAXNMS also supports multivolume ANSIformat magnetic tape files with transparent volume switching.

Communications- The variety of communications interfaces supported by
the VMS operating system allows VAX systems to be connected to other
VAX systems, other Digital systems, and other manufacturers' computer
systems.
Synchronous, point-to-point, and multipoint connections are supported
for interprocessor communication. For terminal-to-host communications,
asynchronous connections are supported.
Using DECnet communications software, various types of computer system
networks can be constructed to facilitate remote communications, resource
sharing, and distributed computation. DECnet-VAX Phase IV software
offers adaptive routing, task-to-task communications, network file transfer,
network command terminals, and network resource sharing and network
management capabilities. DECnet-VAX also supports the connection of
Digital's systems and terminals to local area networks (LANs) including
Ethernet and to other manufacturers' systems through Internet applications. With DECnet/SNA Gateway software and hardware, communications can be established to IBM SNA networks. DECnet Router/X.25 Gateway connects DECnet nodes on an Ethernet to DECnet nodes on an X.25
packet-switched data network using the data-link mapping capability of
the Gateway software. The VAX X.25/X.29 Extension Package allows
remote terminals to access the host VAX processor on the Ethernet by
"dialing in" through a network packet assembler/disassembler. It also
allows access to the protocol level of X.25 traffic. The DECnet communication software supported by VMS includes:

1-36' Introduction

• VAX-ll 2780/3780 is a protocol emulator for transferring data between a
VAX system and an IBM or other manufacturer's system by means of
remote job-entry protocols.

• VAX-ll 3271 is a protocol emulator for an interactive program-toprogram link to an IBM host running CICS or IMS.

• MUX200/VAX is an emulator for communication with a CDC6000,
CYBER series, or other host computer system capable of using 200 UT
mode 4A communications protocol.

• VAX PSI is a packet system interface that allows a VAXIVMS system to
connect to packet-switching data networks conforming to CCITT recommendation X.25.

• IECll-V is a device driver that allows programs written in MACRO-32,
FORTRAN, or BASIC to communicate with IEEE Standard 488 devices
connected to IEC 11-A and IEC 11-B.
• LAT-ll is a special-purpose software system that enables a PDP-l1 processor to be used as a local area terminal server on Ethernet .
• ULTRIX-32 OPERATING SYSTEM
The ULTRIX-32 operating system is a Digital-supported native UNIX operating system and provides complete UNIX functionality, enhanced especially for the VAX systems. The ULTRIX-32 software is an interactive,
timesharing operating system derived from the fourth Berkeley software
distribution (4BSD) technology developed at the University of California at
Berkeley. ULTRIX-32 takes advantage of the VAX virtual memory architecture with demand paging and provides enhanced performance for applications requiring large amounts of memory.
In addition to features and performance comparable to 4BSD, Version 4.2,
ULTRIX-32 provides the following benefits:
• Serviceability enhancements and reliability features.
• Repackaged technical documentation.
• Ability to install and tailor the system kernel for specific configurations
without the need for sources.
• Support for VAX-11/780, VAX-111750, and VAX-l1/no systems.
Some of the more familiar UNIX system tools for software development
and text processing provided by ULTRIX-32 include:
• UNIX Version 7 Bourne and C Shells.
• Line and screen editors.
• File transfer capability.

1-37

Ethernet support.
Remote login.
• Remote job execution.
• Electronic mail.
• Text processing utilities.
Programming languages, including C, FORTRAN 77, PASCAL,
FransLISP, and UNIX Assembler.
VAX System Overview

VAX computer systems consist of the central processing unit, a console
subsystem, the main memory subsystem, and the input/output (I/O) subsystems. The VAX processors are 32-bit, high-speed, microprogrammed
computers that execute the normal instructions in native mode and nonprivileged PDP-II instructions in compatibility mode.
Each VAX processor includes memory management hardware, sixteen 32bit general registers, 32 interrupt priority levels, and a console subsystem
linked directly to the processor. A cache memory is included with all the
processors except for the MicroVAX I, VAX-1l1725, and VAX-ll/730 systems. A high-performance floating-point accelerator (FPA) is available or
supplied with the VAX processors. The FPA operates in parallel with the
basic processor to execute the standard floating-point instruction set. The
FPA decreases instruction execution time of floating-point arithmetic and
of some integer arithmetic operations .
• CACHE MEMORY
The cache memory provides the central processor with high-speed data
access by storing frequently referenced addr~sses, data, and instruction
items in the secondary memory. The memory cache significantly reduces
the processor's effective memory access time. The cache memory in some
of the VAX systems includes an instruction buffer, which enables the CPU
to fetch and decode the next instruction while the current instruction completes execution.
An address translation buffer also is used to eliminate extra memory
accesses during virtual-to-physical address translations. The address translation buffer contains frequently used virtual-to-physical address
translations.

1-38· Introduction

• CLOCKS
The VAX systems include a programmable realtime clock used by system
diagnostics and by the VMS operating system for accounting and scheduling, and a time-of-year clock, which ensures the correct time of day and
date are used_
• MEMORY MANAGEMENT
The VAX memory management hardware enables the VMS operating system to provide a flexible and efficient virtual memory programming environment_ Hardware memory management and the operating system
provide both paging with user control and swapping_ The memory management hardware facilitates program and data sharing, and allows larger
program size and increased performance.
• CONSOLE SUBSYSTEM
The console subsystem allows the user to access the system and programs
through the switches on the control panel, a console keyboard and printing
terminal, the console command language, and an internal mass storage
device. Simple console commands, entered through the console terminal,
provide access to registers and operational control, which includes bootstrap program loading, initialization, and self-testing. The console subsystem and the console command language also facilitate the loading of
diagnostics programs and software updates from the mass storage device.
The console terminal is available to authorized users for normal system
operations, thereby eliminating the need for a separate user terminal.
The console subsystem also enables the remote diagnostic facility to communicate with the VAX processor. The remote diagnostic option allows the
CPU to be connected through a modem to the Digital Diagnostic Center
for fault detection or preventive maintenance. This option can significantly
lower maintenance costs and contribute to the system's availability and
maintainability.
• MEMORY SUBSYSTEM
The main memory subsystem consists of a memory controller and memory
array modules that use both 64-Kbyte and 256-Kbyte metal oxide semiconductor (MOS) RAM integrated circuits (ICs) for data storage. Each array
module contains either I Mbyte or 4 Mbytes of memory. The error correcting code (ECC) allows the correction of all single-bit errors and the detection of all double-bit errors, ensuring data integrity. In the VAX-I 11780 and
VAX-1l1785 systems, two memory controllers with equal amounts of memory can be interleaved to improve VO throughput. In the VAX-1l1782 system, the local memory is used only for stand-alone diagnostics.

1-39

The MA780 multipart memory option is available for the VAX-111780 and
VAX-111785 systems and can contain a maximum of2 Mbytes of ECC MOS
memory. Two MA780 multiport memory options can be included with each
processor, for a total of 4 Mbytes of memory. The multiport memory information is accessed by each system much as main memory is accessed and
can be shared by up to four VAX-111780 processors to providing common
data access, high throughput, and increased availability in a multicomputer
system.
The MA780 multipart memory with 4 Mbytes is part of a standard VAX111782 system configuration and is shared by the two VAX-111780 processors. An additional MA780 multiport memory can be added to expand the
main memory capacity to 8 Mbytes. The local memory provides only resident diagnostic programs .

• INPUT/OUTPUT SUBSYSTEMS
The input!output subsystems are the main communications paths between
the VAX processors and terminals, mass storage devices, communication
interfaces, VAXcluster devices, and customer-developed equipment. The
UNIBUS is an asynchronous, bidirectional bus that provides the signal and
control lines for connecting medium- and low-speed peripheral devices to
the CPU. The MASSBUS consists of high-speed lines that permit the CPU to
communicate with dedicated mass-storage devices. The computer interconnect (Cl) is a UNIBUS adapter and controller that provides the local
network connection between VAX processors and between VAX processors
and intelligent shared-data storage devices through the VAXcluster networks. Redundant transmit and receive lines provide extremely fast and
reliable information transfers between the CPU and storage systems connected to the VAXcluster network. The Digital Data Interconnect (DDI) is
a high-speed, 32-bit, parallel data path and control path that allows direct
access to the CPU memory from Digital or customer-developed devices.

1-40' Introduction

. VAX System Dependability
Extensive reliability, availability, and maintenance features are an integral
part of VAX systems. They ensure dependable operation of the systems and
facilitate repairs when a failure occurs. With better system reliability, optimal system availability, and easier maintenance, uptime is increased and the
overall cost of ownership is reduced.
During normal system operation, the system is continually monitored by
both software and hardware to detect errors or malfunctions in the system
operation. Depending on the type of error, the error can be either corrected by the hardware or software or reported to the operator. The VMS
operating system records and reports errors to the operator through the
console terminal.
Consistency and Error Checking

The continual checking of the consistency of instruction and information
prevents errors from being repeated through a system database. These
checks detect abnormal instruction uses, transient and permanent hardware errors, and illegal arithmetic conditions. Some of the specific checks
include the following:

• Ari'thmetic Traps-These traps occur when overflow, underflow, and
divide-by-zero arithmetic conditions are detected. The hardware detection of these error conditions is used by high-performance software.
Overflow and underflow traps may be enabled or disabled by setting
flags in the processor status longword, allowing the arithmetic exception
conditions to be ignored if appropriate.
• Limit Checking Traps- The decimal string instructions have length limit
checks (0 to 31 decimal digits) performed on the output strings to ensure
that instructions do not overwrite adjacent data.
• Reserved Operand Traps- These are fields and opcodes that are reserved
to customers and to Digital Equipment Corporation to ensure that the
customer extensions to the VAX architecture that include user-defined
instructions or data structures do not conflict with future Digital
expansions.
• Special Instruction Checks- The call and return instructions have
hardware-implemented register save/restore and consistency checking.
These instructions provide a standard, identical interface for user routine
calls and system calls. The cyclic redundancy check (CRC) instruction
provides block-checking error code calculations that are important in
communications applications.

1-41

The VMS operating system uses internal consistency checks to determine
when data is not valid. These checks determine the validity of the system
control information. System malfunctions cause a trap to an exception handling routine and the appropriate information is recorded in the error log
file. The consistency checks include:
• Exception Handling- When any of the consistency checks detect a failure, the VMS software uses a uniform condition-handling facility to manage the hardware or software exception. Because the exception-handling
facility is uniformly consistent within the VAX system design, operation is
more predictable and reliable.
• Error Correcting Code- The memory error correcting code (ECC) automatically corrects single-bit memory errors and detects double-bit memory errors. The code will also detect greater than double-bit errors if an
even number of errors are detected. The disk error correcting code
detects most errors and corrects errors in a single error burst of up to 11
bits. The ECC provides protection from nonrepeating errors by automatically correcting data. Detections and corrections are noted in the error
log as a preventive maintenance aid.
• Mass Storage Veri/ication- The 1/0 verification for mass storage peripherals is supported by the VMS device drivers. The hardware compares each
block for equivalence immediately after the block is read from or written
to the device. The checking may be performed on all read or write operations to a file or volume, or for only a single read or write operation. This
capability increases reliability of the read or written data.
• System Verz/ication- The VMS operating system contains the user environmental test package (UETP), an automated collection of verification
software. The UETP controls the comprehensive and systematic testing of
peripheral devices and software components by performing most of the
VMS utillties and language translators; by calling most of the VMS system
services and I/O services, each of which has a wide range of parameters;
and by comparing the results to known answers. During the execution,
the system reports errors to the error log and to the console terminal. The
UETP is a means of validating the installation and functioning of a VAX
system. A user can execute the UETP to check system functions, to perform preliminary diagnosis, or to demonstrate system capability.
• System Exerciser- The system exerciser diagnostic program tests subsystems in a user environment operating under VMS software. It verifies
hardware integrity or indicates subsystems that may be failing or undergoing deteriorating performance. This testing is performed automatically
using online diagnostic programs. The system exerciser is part of an
extensive hardware reliability verification procedure.

1-42· Introduction

• Automatic Online E"or Logging-Error logging, a software tool used
to monitor error occurrences, is an integral part of the VMS operating
system. The operating system accepts signals from the hardware and
records CPU, memory, 110, and software errors in an online log file. The
error logger records information related to the state of the system at the
time of an error. If no errors occur during a period of time, the time of
day is recorded in the log file to indicate that the error logging process is
operating. For ECC-corrected memory errors, if the error rate exceeds a.
threshold value, the ECC log entries are suspended for a period of time. A
utility program is available to convert the log file into a format and summary that can be printed for later evaluation. Error logging is useful for
the efficient maintenance of the hardware by providing a report that can
help diagnose impending or persistent hardware problems. It detects
trends in fault occurrences and helps to identify the specific subsystems,
which can then be examined using diagnostics.
• Machine Checks- Machine checks are hardware errors detected by th~
processor and reported to the VMS operating system. The VMS software
categorizes the error and takes appropriate action. The instruction in
error is retried, and if the error is transient, the operation continues. If
the instruction retry fails, the software attempts to limit the effects of
the error to a single process. If the VMS executive is executing when
the machine check occurs, the system is automatically rebooted. Machine
checks are caused by cache, translation buffer, or control store parity
errors or by failure of the 110 or memory subsystems to respond to CPU
requests.
• System Identification Register- The system identification (SID) is a hardware register that maintains information pertinent to the system processor type and revision number. This information may be examined during
the software error logging process to determine the engineering status of
the processor.
• Application E"or Detection-The VMS software, together with the
optional software products, provides extensive checking for errors in
application software. The parameters passed to the system services are
checked before the service is attempted, thereby preventing the operating
system and the application from being vulnerable to incorrectly coded
programs. Tools such as the macro assembler and the linker provide a
high level of error detection to minimize the creation of erroneous application software. This includes the detection of program syntax errors,
corrupted files such as system libraries and user files, and inconsistency
between separately compiled programs.

1-43

• Deadlock Detection - The VMS software provides lock manager services
for the synchronization of multiple processes and for the queuing of
processes depending on the availability of resources required. A critical
problem can occur in a deadlock when each process is waiting for the
completion of another process. The lock manager can detect this condition and prevent the application from being unusable.
Error Analysis and Recovery Features

The VAX system hardware and software determine the source of an error
and the extent and impact on the user's operation. The system can often
correct the error or mask its effects. Some of the analysis and recovery
features are as follows:

• System Dump Analyzer- The system dump analyzer (SDA) is a VAXIVMS
utility that helps to determine the cause of an operating system failure.
When an internal error interferes with normal operations, the operating
system writes information concerning its status at the time of failure to a
predefined system dump file. The SDA examines and formats the content
of this file. With the help of the SDA commands, a user can display parts
of the formatted system dump file on a video display terminal, or can
create a hardcopy listing. In addition to analyzing the system dump file,
the SDA can perform operations on a system without interrupting system
operation.
• Error Log Reporting Program- The system error analyzer is a VAXIVMS
utility program that is available to convert the error log file into a format
and summary that can be printed for analysis.
• Instruction Retry- When a hardware error, such as a machine check,
interrupts the execution of an instruction, the system may reexecute the
instruction. If the error is transient, then normal operation will continue.
If the instruction cannot be retried or if the retry fails, the VMS software
attempts to limit the failure to the user process currently being executed.
If the operating system is executing, the system is automatically
rebooted.
• Non/atal Bugchecks- When an error condition is detected by hardware 01;
software and VMS software determines that only a single process is
affected, that process is removed from the system without affecting normal operation of the executive or other processes. The error is logged in
the system error log .
• Automatic Stack Expansion- The VMS operating system automatically
extends user stack space as needed.

1~44' Introduction

• Unattended Automatic System Restart- The automatic system restart
facility returns the system to an operating condition after a power inter~
ruption or a fatal software error. If the battery backup unit has preserved
the contents of memory during the power interruption, the time~of~year
clock allows the VMS software to recover the correct date and time of the
power recovery. A special memory configuration register indicates to the
recovery software whether data in memory was lost. Following a power
failure, all 110 operations in progress before the failure occurred are
restarted. The powerfail asynchronous trap facility may be used to initiate
image~specific powerfail recovery processing. If the battery backup
option is not installed or if the time of the power failure is longer than the
battery backup can sustain the memory data, the system is rebooted when
the power is restored. Following a system failure, unprocessed error log
entries are written to the error log file and the contents of physical mem~
ory is written to the disk for later analysis. A switch on the control panel
of the VAX processor enables the system operator to select automatic or
manual restart of the system after a power failure .
• Automatic Recon/iguration- The VMS operating system allows the sys~
tem to continue operating after some of the hardware components have
failed. The system can be manually or automatically reconfigured at the
startup time so that the system continues operation until the mainte~
nance is performed. Some of the reconfiguring methods are as follows:

- If the program~loading device has failed, the program can be boot~
strapped from a system disk on which the file can be loaded.

- If memory pages are defective, the memory is configured by the VMS
system so that the defective pages are not referenced and are trans~
ferred to a bad~page list. This occurs during bootstrap loading and
continues dynamically while the system is operating. A set of physical
addresses is not required to bootstrap the system.

-If excessive cache errors are detected in the medium~ and large~VAX
processors, the cache memory can be dynamically disabled by the VMS
software.
- The VMS operating system automatically determines the presence of
peripherals on the processor at bootstrap time and flags nonresponding
devices and memory as being unavailable.
- Software spooling allows the data output to be routed to an alternate
device using system operating commands when the designated device is
not available.

1-45

• Dynamic Bad-block Handling-Bad blocks of data may be generated
when there is a failure of the disk drive that performed the data transfer.
When the hardware detects a bad block during an I/O operation, the
VMS operating system marks the header of the file in which the error
occurred. When the file is deallocated, the system checks the file header
for bad blocks and designates this information as permanently in use and
not available for use by other files.
• Mass-storage Error Recovery- The operating system attempts recovery
from nonfatal disk and tape errors. If a hardware error occurs during an
I/O operation, the I/O operation is reinitiated by the software using the
available hardware recovery mechanisms.
Redundant Recording 0/ Critical Disk In/ormation - Critical disk information, such as the home block and the index file header, is duplicated to
allow its recovery when it is accidentally destroyed.
• Selective Hardware Disabling- Several hardware elements, including the
memory management logic, cache memory, translation buffer, and
floating-point accelerator, can be disabled by the diagnostics program to
help in isolating hardware failures. The translation buffer and cache
memory are also dynamically disabled by the VMS program to allow the
system to continue to operate at a reduced level of performance.
Data Integrity

The VMS operating system prevents interference between processes that
contain critical system data. This is accomplished by the following hardware access protection and software enforced privileges:

• Memory Management Hardware- The memory management hardware
assigns priorities to the kernel, executive, supervisor, and user modes of
operation. The critical software components of the VMS software are run
in the most privileged kernel and executive modes. Access to these modes
is allowed only to authorized users; therefore, the integrity of the information is ensured.
Quotas and Privileges- The VMS software uses a system of quotas to protect shared system resources, such as dynamic memory and .page file
space. Quotas are assigned on a per-process basis so a process cannot
stop normal system operation by depleting shared resources. Hardware
access protection and a set of software enforced privileges prevent user
processes from affecting each other or the operating system. When a
process violates the protection rules, the error is reported so that appropriate recovery actions can be taken without affecting the remaining
system.

1-46· Introduction

• Access Control to Files and Volumes- The VMS operating system provides
protection on a per-file basis. Users can be assigned read or write access
to other users' data and files by limited authorization on a volume-wide
basis.
Disk Volume Protection- The VMS file system allows the system manager
to specify the amount disk space assigned to a user. This prevents a user's
application from using all the available data storage. When a volume is
mounted, the file structure is checked and any inconsistencies that exist
are corrected automatically. This feature is useful when a system failure
occurs while the files are in use. When a power failure to the system or
disk drive occurs, the VMS file system checks to ensure that the volume in
use at the time of the failure is the one to be reinstated. This prevents the
accidental corruption of a different volume.
Maintenance Aids

The VAX system hardware packaging and diagnostic tools reduce the time
necessary to diagnose and repair the system, thus increasing system availability. Some of these features are as follows:
• Improved System Packaging- The VAX systems components are designed
for reliability and are easily accessible for repair. Most internal cables and
assemblies are permanently mounted and accessible from the front or
rear of the cabinet. This prevents damage that could be caused when
assemblies mounted on slides are repaired.
Environmental Conditions- The ac and dc power conditions, cabinet
temperatures and internal cabinet air flow are monitored by sensors to
detect abnormal environmental conditions. This prevents equipment
damage and helps to determine the cause of failure.
Online Functional Diagnostics-Many functional diagnostics can be performed online under control of the VMS operating system. This enables
the isolation of malfunctions while the system is operating. The following
functional diagnostics are implemented.

-Character printers, line printers, card readers, and terminals.
- Synchronous link and bus interaction.
- Disk formatter and disk and tape reliability.

1-47

• Fault-isolation Diagnostics-Once the functional diagnostics have isolated
faults in a particular subsystem or device, fault-isolation diagnostics can
be performed to localize the failure to the smallest possible element.
Fault-isolation diagnostics operate independently offline and are used to
isolate problems to a field-replaceable unit. This minimizes the cost of
replaceable parts and reduce; the time of repair. Microdiagnostics can be
performed by a Digital remote station when the remote diagnostic service
has been contracted.
• Online Software Update and Maintenance- The system operator can perform so&ware updates and maintenance activities while the system is
actively performing operations. So&ware updates are distributed in
machine-readable form on disk or tape media. During normal system
activities, software modules on disks can be updated using patches and
replacement modules, and so&ware maintenance and disk backup
procedures can be performed. This increases system availability and
maintainability.
• Automatic Updates and Patches- The VMS so&ware implements a system
of automatic updates and patches. If a power interruption occurs when
so&ware updates are performed, the operation can be resumed when the
system is restarted. Each patch automatically checks for previous patches
and updates the current revision number. The patches are distributed
and applied in machine-readable form, which eliminates errors that can
occur during transcription.
• High Resolution Interval Clock- The VMS so&ware and the interval clock
are used by diagnostics programs to test time-dependent functions;
therefore, machine-specific timing loops in programs are not required.
• Maintenance Registers- These registers contain specific maintenance
information that can be examined when an error occurs to help determine the cause of the failure.

VAX-1l/725 and VAX-1l1730 System Features
The VAX-1l1725 and VAX-lllnO systems contain several features that
facilitate maintenance and ensure maximum availability of the system. The
system includes diagnostic programs that can be performed by the customer to verify the operation of the system. Microverify routines are performed automatically during the powerup sequence, when the program is
bootstrap loaded, or when the reset switch on the control panel switch is
activated. These routines test the data paths, and the successful execution
of the routines indicates that the system will bootstrap properly. Parity
checking is performed on words read from the writable control store
(WCS) before execution.

]-48' Introduction

• CUSTOMER DIAGNOSTICS
Diagnostic programs can be initiated by the user to verifying that the hardware is operating properly and to isolate hardware failures when they
occur. The error information provided by the diagnostics can be analyzed by Digital service personnel and spare parts and tools can be provided to repair the failure. Most failures can be corrected by one visit to
the customer.
The user diagnostics provide error information in the following three
modes of operation:
• The autolest mode is used to verify the operation of the CPU, the VMS
system disk, and the diagnostic load disk. It can be used to determine the
cause of a nonbootable system and is invoked by the test command in
response to a console mode prompt. Messages are displayed during the
test to indicate test progress. The offline menu mode is initiated after the
successful completion of autotest.
• The offline menu system allows a user to verify the operation of any
device on the system. The concise menu format provides a simple interface for users that are unfamiliar with VAX diagnostics. All standard
VAX-111725 and VAX-11/no system options and devices are supported.
When necessary, the user is prompted to supply necessary device
preparation.
• The online menu system allows the user to verifying the operation of a
device while operating under the VMS program. Device testing is performed without disturbing other users or processes on the system. Terminals, lineprinters, and other peripheral devices that do not affect the
overall operation of the VMS program can be tested using the online
menu mode. Devices that have both online and offline support should be
checked with both menu modes for total device verification.
Remote Diagnostic Service- DECservice is Digital's field service operation
for customers. Remote technical support is provided when necessary to the
Digital service engineer at a customer site. DECservice customers also have
the added benefit of a service feature called remote hardware monitoring
(RHM). Under RHM, Digital Field Service will determine a schedule with
the customer for performing periodic remote hardware checks of the system. This program allows Digital to identify potential problems and schedule preventive maintenance before a critical situation can occur.

1-49

• PROCESSOR HARDWARE
The CPU contains the following hardware features to enhance the reliability and maintenance of the system:

• Module Replacement- The system memory arrays, CPU modules,
tloating-point accelerator module and 110 interface modules can be easily
removed and replaced.
• Modular Power Supply- The power supply for the systems contain three
modules: a power controller and two power regulators. These modules
can be replaced in a short time. Status lights on the supply indicate the
condition of the supply voltage.
Dual TU58 Tape Drives- If one of the TU58 tape drives is inoperative, the
remaining drive can be used to load the program information.
• Air Flow Sensors- Sensors are included to detect the movement of cooling air through the cabinet. Changes in the air flow are sensed and
reported.
VAX-1l/750 System Features
The VAX-1l1750 system includes many hardware and software features
that increase the system reliability and ensure efficient maintenance.
Microverify routines are automatically performed during the powerup
sequence, when the program is bootstrap loaded, or when the reset switch
on the front panel is activated. These routines test the data paths, the 16
general-purpose registers, most internal CPU registers, the instruction prefetch buffer, parity logic of the cache memory, the translation buffer, and
the cache memory. The successful execution of the microroutines indicates
that the operating system can be properly loaded.

Parity checks are performed on MASSBUS data, control and address translation, UNIBUS address translation, memory cache data and address,
address translation buffer transactions, microcode, and user control store
information .
• REMOTE DIAGNOSTIC SERVICE
Remote diagnostic service is available to customers in North America and
parts of Europe. When the service is contracted, a remote Digital diagnostic center can test the operation of the system and an experienced staff can
analyze the system problems. These services are available seven days a
week, and 24 hours a day. The center has a host diagnostic computer that
aids in localizing system failures. After a call is received from a customer, a
technician at the center makes contact with the customer's computer and

1-50· Introduction

logs onto the system. A series of tests and diagnostic procedures are performed from the service center to examine memory locations and the error
log file. If servicing is necessary, the repair time is substantially reduced
because the service engineer will have the required part when arriving at
the site. Some of the programs can be executed while the system is processing customer information. Preventive maintenance is also offered through
remote diagnosis centers and can be scheduled for convenient off-peak
periods.
A diagnostic console is included with the remote diagnosis service and can
access the processor's major buses and key control points through a special
internal diagnostic bus. The console enables the operator to initiate the
diagnostics programs using simple keyboard commands. The diagnostic
console can also serve as an operator console and as a user terminal. The
diagnostic console includes a cartridge tape drive and hardcopy terminal.
• PROCESSOR HARDWARE
The CPU contains the following hardware features to enhance the reliability and maintenance of the system:

• Module Replacement- The system memory arrays, CPU modules,
floating-point accelerator module, and 1/0 interface modules can be
easily removed and replaced.
• Modular Power Supply- The power supply for the systems contain three
modules: a power controller and two power regulators. These modules
can be replaced in a short time. Status lights on the supply indicate the
condition of the supply voltage.
• Improved Air Flow and Design-Air is drawn into the top of the cabinet
by the blower, passed through the modules and power supplies, and is
exhausted at the bottom rear of the cabinet. The blowers operate well
below their maximum ratings, which significantly extends their operating
life. The cooling air flow is adequate when the cabinet doors are open,
thereby allowing the online servicing of the units.
VAX-1l/780, VAX-ll/782, and VAX-ll/785 System Features
Many features are included with the VAX-lI/780, VAX-lI/782 and VAX111785 processors to ensure reliable operation of the system and to make
them easy to maintain. A complete set of diagnostic programs is available
to test the main functions of the processor logic, memory arrays, 1/0 subsystems and devices.

1-51

When the UNIBUS adapter detects certain error conditions on the UNIBUS,
the conditions are reported in the error log. If the conditions persist, the
UNIBUS is reinitialized and the I/O operations currently in progress on
the UNIBUS are restarted. The power to the UNIBUS adapter and to the
UNIBUS peripheral cabinet can be removed and applied without affecting
the normal system operation. This allows the replacement of faulty devices
without interrupting the processor operation. The operations in progress
on other UNIBUS devices are restarted automatically when the UNIBUS
powered is restored.
The synchronous backplane interconnect (SBI) includes a 16-level silo register that monitors the central bus activity and records the status and parity
check information of the 16 most recent cycles of bus activity. If an error or
predetermined special condition occurs, the silo stops operating and the
contents of the silo and can be examined to determine the cause of the
failure.
The clock rate of the central bus can be varied by commands issued from
the console terminal. This feature helps service engineers to diagnose intermittent hardware failures.
Parity checks are performed on MASSBUS data, control and address translation, UNIBUS address translation, memory cache data and address,
address translation buffer transactions, microcode, and user-control-store
information .
• REMOTE DIAGNOSTIC SERVICE
Remote diagnostic service is available and provides the same features as
those described for the VAX-111750 systems. The diagnostic console,
included with the systems, can access the central processor's major buses
and key control logic through a special internal diagnostic bus. Through
the console, the operator can initiate diagnostic operations using simple
keyboard commands. The diagnostic console also can be used as an operator console and a:s a user's terminal. It includes an LS1-11 microcomputer,
floppy disk drive, and hardcopy terminal. A watchdog timer in the LS1-11
detects a stalled processor condition such as a failure to fetch an
instruction .
• PROCESSOR HARDWARE
The CPU contains the following hardware features to enhance the reliability and maintenance of the system:

• Module Replacement-Memory arrays, CPU modules, floating-point
accelerator modules and I/O interface modules can be easily removed
and replaced.

1-52· Introduction

• Modular Power Supply- The power supplies for the system are modular
and can be easily removed and installed. Spaces are provided within the
cabinet for six power supplies; four are part of the basic cabinet requirements and the remaining two are installed with the floating-point accelerator option and with ,the MASSBUS adapters option .
• Improved Air Flow- Three blowers, mounted at the top of the processor
cabinet, provide the cooling air for the processor. The fans draw air into
the top of the cabinet, pass it through the modules and power supplies,
and exhaust it from the bottom rear of the cabinet. Because the air is
supplied from the top of the cabinet, the air is not contaminated with dirt
particles from the floor. The blowers operate below their maximum ratings, which significantly extends their operating life. The cooling air flow
is adequate when all cabinet doors are open to enable the online servicing
of internal units.
VAX 8600 System Features
In addition to the features included in all VAX processors, the VAX 8600
system incorporates many other features to ensure reliable operation, system availability, ease of maintenance, and maximum performance. The
hardware and software of the VAX 8600 incorporate the latest design techniques to assure efficient operation and maximum system dependability.
Approximately 15 percent of the logic circuits in the system are used to
verify the operation of the system and the integrity of the data. More than
3,000 logic points on the CPU backplane are available for analysis through
the serial diagnostic (SD) bus and the console terminal. Online diagnostic
programs can be performed concurrently with the user mode of the VMS
operating system without interrupting normal CPU operations. If errors
occur during the system operation, they are recorded and logged. The
CPU is restarted automatically and allowed to continue processing the
instruction. Some of the salient reliability, availability, and maintenance
features are:

• Fault-tolerent design.
• CPU signal levels that can be monitored through the console terminal.

• Error correction control (ECC) implemented on memory, cache, and CPU
microprocessor control logic.
Online diagnostics for the VMS operating system.
System-error detection and logging.
• Autodiagnostic and remote diagnostic capabilities.
Special maintenance capabilities provided by the console processor
functions.

1-53

• FAULT-TOLERANT DESIGN
The VAX 8600 processor incorporates a fault-tolerant design that allows
the system to rapidly recover from system errors by monitoring status
information related to the error, by recording the information in an error
log, and by reinitiating the instruction in process when the error occurred.
When an error is detected that results in a machine check, up to 88 bytes of
error status information can be recorded. Since most errors that occur on
processors using LSI logic components are a result of intermittent failures,
the processor is allowed to continue operating after the error information is stored. If the error is repeated, the stored information can be evar
uated later and maintenance can be performed at the convenience of the
customer.
• DYNAMIC FAULT INSERTION
Dynamic fault insertion allows the fault detection logic to be checked while
the VMS software is operating. Intermittent faults can be simulated by
selecting the desired timing of the CPU clock, and by inserting and removing a fault at the proper interval during one or more cycles. This is used to
verify that the recovery logic included with the CPU is being executed
correctly.
• SERIAL DIAGNOSTIC BUS
The serial diagnostic (SD) bus is a network data path between the console
subsystem and the CPU that connects to the major logic elements in the
CPU. The SD bus is used to verify the system operation, diagnose and isolate CPU hardware faults, and provide a path from the console subsystem
to control the operations of the CPU. The SD bus and the SD bus interface
allow internal signal levels and signal levels transferred between modules
through the system backplane to be accessed and displayed on the console
terminal. This eliminates the need for the special test equipment normally
required to monitor CPU logic levels during maintenance. The SD bus
includes independent clocking and control, thereby enabling the console
software to initialize the CPU hardware, step the CPU clock, monitor the
state of various CPU logic signals, and serially transfer data to the console
where it can be verified. By stepping the CPU clock, the console software is
allowed to follow the progress of the CPU operation and verify the logic
response through the SD bus. The SD bus consists of 24 serial data paths
that connect to 24 separate visibility control channels included with the
Fbox, Ebox, Ibox, and Mbox. A visibility channel in a CPU module consists
of an 8-bit visibility register and a multiplexer that selects internal logic
information t<;? be loaded into the visibility register. The console program
reads a visibility channel by stopping the CPU clock and by shifting an 8-bit
address code to select a multiplexer channel. The register information is
then transferred serially from the visibility register to the console subsystem and displayed on the console terminal.

1-54 • Introduction

• ENVIRONMENTAL MONITORING
The VAX 8600 processor includes a microprocessor-controlled environmental monitoring module (EMM) in the modular power supply area of the
cabinet that samples and controls the environmental conditions in the CPU
and optional system cabinets_ The module monitors and controls the dc
regulator voltages and checks the regulator error status_ It also monitors
the cabinet air flow, cabinet air temperatures, and ac ground currents for
excessive current flow_ The functions of the EMM are monitored and controlled by console commands from the console subsystem. By controlling
the dc regulator voltages from the console terminal, marginal voltage conditions can be established to help detect intermittent logic errors.

• ERROR ANALYSIS AND REPORTING
The standard package of error analysis and reporting (SPEAR) program
allows system maintenance to be deferred until a time is convenient for the
customer. The program is based on the number of errors that occur and
the customer is automatically notified when error rates exceed a specified
value. SPEAR is a software maintenance tool that contains algorithms used
to analyze the machine check data that is collected by the processor over a
period time. Intermittent failures that allow the processor to recover and
continue operation are stored in an error file and the file is examined by
SPEAR to determine the cause of the fault. The program detects specific
patterns related to one error or to a series of errors.

• PARITY CHECKS
The validity of the data and control information transferred between the
processor elements is ensured by parity checks and a comparison of the
stored information with information stored in another location. Most critical information has a parity indicator appended to it during the transfer.
The checks performed on the VAX 8600 processor elements include the
following:
• Cache Memory Parity Checks- When single-bit errors are detected during

data transfers from the cache memory, the data is transferred with an
indicator specifying that the data contains an error. A cache correction
cycle is initiated to correct the single-bit error and to rewtite the corrected data into the cache memory. The logic element that requested the
data issues a processor-interrupt request and a machine check stack
frame is generated. The instruction is reexecuted and the corrected data
is then accessed.

1-55

• Control Store Parity Checks- Single-bit errors associated with the control
store logic of a controlling microprocessor in the CPU can be corrected.
When a control store parity error is detected, the CPU is halted and the
data containing the error is transferred to the console subsystem and
corrected by the console ECC so&ware. The micro word is then rewritten
into the control store location and the instruction is automatically reissued without causing a fatal halt condition of the CPU. When an Mbox
parity error is detected, the bit in error is identified and recorded; however, the CPU will not recover and resume operations.
• General Purpose Register Checks- Single-bit parity errors associated with
the general purpose registers (GPRs) are correctable. Because of the multiple sets of GPRs in the VAX 8600, if an error is detected in the information stored in one GPR set, a copy of the information from a valid GPR is
written into the GPR that contains the error.
• Internal Bus Parity Checks-Parity is generated on the information transferred through the internal processor buses. The parity is produced and
checked on 8-bit bytes and on 32-bit words on some of the buses.
• Ebox Arithmetic Unit Parity Checks- The Ebox contains three sets of
arithmetic logic units (ALUs) that receive the same inputs and perform
the same functions. If the outputs of the three ALUs are not the same, a
failure is recorded and the instruction is executed again.
• Control RAM Parity Checks-Parity checks are performed on the outputs
of the control RAM to insure that the control functions are not in error.

• PROCESSOR HARDWARE
The design of the CPU hardware includes many reliability and maintenance
features including the following:
• Socket-mounted RAMS-The RAM integrated circuits used on the VAX
8600 modules are mounted in sockets for easy removal and replacement.
This feature eliminates the need to replace the entire module when a
defective RAM is located, resulting in lower maintenance costs and faster
repair.
• Logic Partitioning-Logic functions are grouped together on modules so
that when a module is replaced due to a suspected failure, all the logic
associated with that function is replaced.
• Cabinet Cooling-The CPU cabinet allows conditioned air, ducted
through a raised floor, to enter through the bottom of the cabinet. The air
passes through the modules and the modular power supplies and is
expelled through a plenum at the top rear of the cabinet. The plenum
chamber is muffled to keep the overall noise level within the acoustic
limits of 60 decibels per ampere.

An important consideration in choosing a computer system is its ability to
be expanded to support new users and applications. It may be necessary,
initially or later on, to add main memory, increase the processing power,
add mass storage devices, or extend communication with other systems
and terminals. System expansion should be economical, without requiring
costly changes in the processor architecture and software.
Digital's unified VAX computer architecture, network architecture, and
mass-storage architecture provide the means for system growth to meet
present or future expansion requirements. VAX computer architecture
ensures that existing and new VAX processors are compatible and will
operate effectively without extensive changes to software or hardware.
VAXcluster and network architecture offers extensive capabilities for connecting computers and terminals-located in the same areas or dispersed to
locations around the world - into efficient and flexible communication networks. Computing power, storage capacity, and system availability can be
easily and economically increased. As new computers and devices are
developed, they can be incorporated into the existing VAX systems without
the need to replace software or equipment.
The VAXcluster architecture enables the high-speed interconnect function
of the Digital Storage Architecture (DSA), implemented by the Computer
Interconnect (CI) and the VMS software, to share computer resources
among the cluster nodes, to increase system performance, and to ensure the
availability and integrity of the system data. When system expansion is
necessary, the CI provides the most efficient and cost effective means of
adding CPU power and mass-storage devices. The expansion is accomplished easily and incrementally as the system requirements evolve.
Through the DSA, intelligent controllers, I/O servers disk and tape drive
can be added to a system. One system is designed to be used with a single
VAX processor and the remaining subsystem is for multiple-processor systems. Each subsystem contains a mass storage control and management
functions are performed by the intelligent controllers. The UDA50 subsystem controller is used with the RA60, RA80, and RA81 disk drives, and the
HSC50 intelligent mass storage server is used with the same disk drives and
with the TA78 tape drives. Each controller is microprocessor-based and
coordinates. the activities of all storage drives that are connected to the

- ------- --

--.--------~-

---_._------------------ - - - - - _.

------

2-2· VAxcluster and Netw9rk Architecture

controller. The controllers are responsible for optimizing data throughput
between its drives and the host processor. It optimizes each 110 request
based on the positioning of the drive heads to effect the most efficient data
transfers. The controller enhances data integrity by validating each transfer
and performing error recovery when necessary without assistance from the
host processor. A sophisticated error correction code is used to correct
extensive data errors, thereby substantially reducing the loss of data when
an error occurs .

. VAXcluster Systems
VAXcluster systems provide a means for VAX customers to increase computing power, storage capacity, and system availability. A VAXcluster system
can include one or more VAX-1l1750, VAX-1l1780, VAX-1l1785, and VAX
8600 processors and intelligent mass storage servers connected to a common distribution unit (SC008 Star Coupler) by the Computer Interconnect
(CI) bus as shown on figure 2-1. VAXcluster configurations are fully supported by the VMS operating system. Processors and intelligent mass storage subsystems are connected into a loosely coupled local network that
enables the sharing of processing power and data resources. VAXclusters
are implemented by the high-speed, dual transmission CI path for the
transfer of information between the processors and the HSC50 mass storage servers.

SO)08
PATH A
VAX·1l
750
CPU
(NODE I)

C
I
7
5
0

S~An:OUPLER

PATH A
HSC50
DISK/TAPE
SERVER
(NODE 9)

PATHS
PATHE

PATH A
VAX·1l
780
CPU(NODE 2)

··
··
VAX-8600
CPU
(NODE 8)

C
I
7
S

PATH A
HSC50
DISK/TAPE
SERVER
(NODE 10)

PATHS
PATHS

PATH A

y
7
8
0

PATH A
PATHS

j~,

PATHS

C
I
A
D
A
P
T
E
R

··
··

VAX-Il
CPU
EXPANSION
(NODE 16)

Figure 2-1 • VAXcluster System Configuration

DISK
AND/OR
MAGTAPE
UNITS

2-3

The features and benefits of the VAXcluster systems are as follows:
• Processing power and data storage capacity can be added incrementally
to the system.
• The choice of VAX processors and mass storage facilities is based on
individual system requirements.
• Each VAX processor operates independently to increase the total system
reliability and availability.
High-speed message-oriented transmission is provided.
Intelligent mass storage servers and VMS facilities ensure data integrity
and file sharing.
• Dual-path computer interconnect provides intelligent, high-performance
redundant lines.
Common access from any VAX system is provided to information stored
in data files.

Computer Interconnect

The Computer Interconnect (CI) is a dual-path, 70-Mbits-per-secondbandwidth, logically multidropped link used to transfer serial data between
local VAXcluster nodes. The CI can connect up to 16 nodes and a node can
be a VAX processor or an HSC50 mass storage server. Interprocessor communication is controlled by new system-level protocols. The physical connection to the VAX systems is through the CI interconnect adapters and
coaxial cables. The adapters are microprocessor-controlled, intelligent
interfaces that perform the functions of fully buffered communication
ports. Messages are transferred in blocks of data between the CPU memory
and other nodes within the VAXcluster by the VMS and DECnet-VAX software. By providing the necessary data buffering, address translation, and
encoding and decoding, the CI adapters significantly reduce the amount of
overhead processing required to complete high-level intercomputer communication. The CI consists of an adapter and two transmit and two
receive coaxial cables that attach to the SC008 Star Coupler unit. Information can be transferred simultaneously on either of the two transmit or
receive lines. Two CI adapters can be installed on the VAX-1l1750, VAX-ll/
780, VAX-1l1785 and VAX 8600 processors to increase performance and
ensure reliable data transmission in the event of a failure in ~ CI adapter.

2-4· VAxcluster and Network Architecture

The CI750 adapter is the interface between the CPU/memory interconnect
(CMI) of the VAX-111750 processor and the dual-path CI bus. The CI750BA or CI750-BB is mounted in a cabinet 101.6 centimeters (40.0 inches)
high and contains three extended-length hex-height modules, backplane
mounting unit, and power supply for an input of 120 volts (ac) or 240 volts
(ac). The CI750 connects to the VAX-1l1750 through a hex-height interface
module that mounts in the processor backplane. The CI750-SA or CI750-SB
consists of two CI750-BA or CI750-BB options, cables, and SC008 Star
Coupler unit for operation with two VAX-1l1750 processors. Figure 2-2
shows the CI750 cabinet.

Figure 2-2 • CI750 Computer Interconnect Adapter Unit

The CI780 adapter is the interface between the synchronous backplane
interconnect (SBI) bus of the VAX-111780 series of processors or the VAX
8600 processor and the dual-path CI bus. The CI750-AA or CI780-AB
options can be installed in the CPU cabinet of the processors or in a CPU
expansion cabinet. It consists of four extended-length, hex-height modules, backplane mounting unit, and power supply for an input of 120 volts
(ac) or 240 volts (ac). The CI780-SA or CI780-SB consists of two CI780-AA,
-AB options, coaxial cables, and the SC008 Star Coupler unit for operation
with one processor or with two separate processors. Figure 2-3 shows the
CI780 option hardware.

Figure 2-3 • CU80 Computer Interconnect Adapter Hardware

SC008 Star Coupler Unit
The SC008 Star Coupler unit, shown in figure 2-4, is the common connection point for all the coaxial cables from the VAXcluster nodes. It terminates and electrically isolates the serial-data lines and distributes the data to
and from the individual nodes. The Star Coupler is an RF, transformercoupled, dual-path, passive unit that can connect with up to 16 CI nodes.
The maximum length of the coaxial cables that connect a node to the
SC008 unit is 45 meters (147.6 feet).

2-6· VAXcluster and Network Architecture

Figure 2-4 • SC008 Star Coupler Unit

The Star Coupler cabinet is 101.6 centimeters (40.0 inches) high and provides mounting space for up to four connecting panels as shown in figure
2-5. Each panel has eight transmit and eight receive coaxial connectors and
six modularity coaxial connectors used to connect the panels together. Up
to eight nodes can be connected to the two-panel configuration and up to
16 nodes can be connected to the four-panel configuration. Nodes may be
added or removed without interrupting the operation of the other nodes.
The coaxial cables are routed through the rear of the cabinet.

2-7

c:::::;:=::::> STAR COUPLER
8-TRANSMIT
LINES

PANEL A

8-RECEIVE
LINES

C==::> STAR COUPLER ~==>
8-TRANSMIT
LINES

PANEL B

8-RECElVE
LINES

8 NODE DUAL-PATH (SC008-AC)
I

:> STAR COUPLER
PANEL A

8-TRANSMIT
LINES
I

> STAR COUPLER

PANEL A

8-TRANSMIT
LINES

:> STAR COUPLER
PANELB

8-TRANSMIT
LINES

> STAR COUPLER

8-RECElVE
LINES

PANELB

8-TRANSMIT
LINES

8-RECElVE
LINES

16 NODE DUAL-PATH (SC008-AC) AND (SC008-AD)

Figure 2-5 • SCDD8 Star Coupler Terminating Panel Configuration

2-8· VAXcluster and Network Architecture

HSC50 Intelligent Mass Storage Server

The HSC50 (Hierarchical Storage Controller), shown in figure 2-6, is an
intelligent mass st~rage I/O server that connects the VAX processors in a
VAXcluster to a group of mass storage disks or tape drives_ The HSC50
server and drives form a node on the VAXcluster system_ Operating with
VAX/VMS software, it supports up to 24 Digital Storage Architecture (DSA)
devices including the RA60 205-Mbyte removable-disk drive, the RA80
121-Mbyte fixed-disk drive, the RA81 456-Mbyte fixed-disk drive, and the
TA78 magnetic tape subsystem. The disk drives contain two communication ports and each port can connect to a HSC50 server. Communication
between the HSC50 server and the mass storage devices is through the
standard disk interfaces (SDI) and the standard tape interfaces (STI). Highspeed, I/O throughput is performed under control of a PDP-ll processor
operating with a multiple high-speed bit-slice microprocessors. By adding
multiple HSC50 servers in a VAXcluster system, higher data throughput
and system performance can be achieved.

Figure 2-6 • HSC50 Intelligent Mass-storage Server Unit

2-9

The HSC50 server performs many disk management functions, including
volume shadowing, volume image copying, and image backups from the
host, thereby reducing the load of the host VAX processor. The database is
shared between the VAX processors connected to the VAXcluster architecture. The HSC50 server manages the physical activities of the drives, optimizes the system throughput, detects and corrects errors and performs
local functions such as diagnostic test execution without the intervention
of the VAX processor. Data is transferred between the HSC50 server and
the host VAX processor using a series of communication protocols, all conforming to the MSCP (Mass Storage Control Protocol) of DSA. Its internal
bus structure allows read and write operations to be performed simultaneously to the disk drives. The HSC50 server includes a comprehensive set of
diagnostic programs and redundant logic to ensure reliable performance
and to facilitate maintenance. The capabilities provided by the HSC50
server and devices are as follows:
Command queue stores up to 120 host processor I/O requests
Provides data buffering of up to 128 Kbytes for 256 disk sectors to optimize data flow
Self-contained diagnostic test programs
Offline utilities provide volume backup and restore as well as disk formatting and format verification
~ Dual-ported disk drives can connect to two HSC50 servers for higher

availability
• Multiple VAX processors can read from or write to the shared files.
The HSC50 server includes controller logic, two TU58 cartridge tape
drives, and a power supply mounted in a cabinet 101.6 centimeters (40.0
inches) high. One TU58 tape drive is accessible from the front of the cabinet and one is in the cabinet. A distribution panel mounted at the rear of
the unit is used to connect the cables from the disk and tape drives.
The configuration of the HSC50 server and devices is shown in figure 2-7.
It connects to the SC008 unit through the CI coaxial cables and to the tape
formatters and disk drives through six data channels.

2-10· VAxcluster and Network Architecture

DUAL TU58
TAPE DRIVE

CIBUSA

CI BUS B

<
<:
<:

XMIT
RECV
XMIT
RECV

>
>
>
>

TA78TAPE
DRIVE 2

···

C
A
B
L
E
!

CONTROL PANEL

--+ LOCAL

HSC50 INTELLIGENT MASS
STORAGE SERVER

TAPEDATA
CHANNELl

*DUAL PORT FOR
SECOND HSC50

I....

DISK DATA
CHANNEL 6

.......
';

TAPE FORMATTER

TERMINAL

C
A
B
L
E
6
'-

RA60,RA80
ORRA8!
DISK DRIVE

TA78 TAPE DRIVE 1

Figure 2-7· HSC50 Mass Storage Server Configuration

. Communication Networks
Digital offers extensive capabilities to link computers and terminals into
network configurations. Networks can increase the efficiency and costeffectiveness of data processing by allowing computer systems and terminals to share resources and to exchange information files and programs.
Applications can be expanded by adding computers and terminals to the
networks as required. Through the use of networks, small computers can
have access to the capabilities of larger, more powerful systems and the
large systems can have access to the information processed by the dedicated applications of the smaller systems.
Communication networks can be installed within a building, or within a
site between buildings. By the use of a common carrier of dedicated telephone lines, the communication facilities can be extended to remote locations throughout the world.

211

The Digital Network Architecture (DNA) is the framework for all Digital
network products. It is a comprehensive set of hardware and software used
to control the communication functions of the networks. The Digital System Interconnect (DSI) strategy provides the process that allows VAX processors operating with VMS software to communicate with mass storage
devices, terminals, and communication links. The DNA is closely based on
the International Standards Organization (ISO) architecture for open system communication. These industry standards allow systems developed by
different manufacturers to be compatible. The DNA offers the flexibility of
adding new hardware and software technology to a network while retaining the compatibility of the previous technology.
Network Environments
The Digital communication network environments allow information to be
transferred between Digital systems and equipment, and between Digital
systems and systems and equipment developed by other manufacturers.
Network communication between Digital systems is facilitated by DECnet
software and hardware, which is a Digital developed network protocol that
permits fast and efficient data communications between Digital's products.
For local and remote communications between Digital systems and syslcms
developed by other manufacturers, Digital provides Internet and Packetnet
products.

Digital offers a complete range of network products for the basic point-topoint and multipoint communications links to complete network communication facilities, including sophisticated network hardware and software
for complex applications. These products include single modems and multiple modem enclosures, single and multichannel, synchronous and asynchronous interfaces, communication multiplexers and controllers, and
terminal servers.
Ethernet Local Area Networks
A local area network (LAN) is a privately owned data communication subsystem that provides high-speed communication channels between terminals, devices, and data processing equipment within a local area. The communication network can be. routed internally in a building, or between
buildings that are confined to a local area or site. Local area networks
permit information and data processing resources to be shared locally and
with remote sites through gateway and router server devices.

2-12· VAXc!uster and Network Architecture

Digital's Ethernet local area network is supported by DECnet software and
provides an economical 'means of communication, Systems and devices are
easily connected to the network and network expansion is facilitated without interruption of the network operation, The DECnet software, through
the Digital Network Architecture (DNA), defines the standards for protocols, interfaces, and communication functions. The DNA provides a flexible
communication system based on communication layers. Each layer performs a specific set of functions and services and the interaction of the
layers control the operation of the network.
Ethernet can be implemented on either baseband or broadband cable.
With baseband, a single network cable replaces the many cables normally
used for data networks and Ethernet is the only channel on the cable.
Ethernet on broadband is an extension of baseband and allows video,
voice, and other data communications to be transferred through one or
two cables. This information can be shared with other independent channels. Some of the features provided by Ethernet are as follows:
Simplified network design allows easy installation of new devices without
interrupting communications between existing devices.
Single or dual network cables replace many cables typically used in network applications.
Cable segments can be added to expand networks.
High-speed communication between nodes can be up to 10 Mbits per
second.
• Remote locations have fast access to data.
• Allows special purpose peripheral devices, including high-speed printers,
large-capacity storage devices, and high-resolution graphics packages to
be shared by users,
• Transfers text, electronic mail, facsimile data, video and audio signals.
• Enables the connection to other manufacturers' equipment.
Figure 2-8 shows a typical Ethernet baseband network configuration. Host
processors, personal computers, terminal servers, gateway routers, and
repeaters connect to the Ethernet cable through the H4000 Ethernet transceivers. The communications controller in the host is connected to the
H4000 transceiver through a four-twisted-pair wire cable.

2-13

Figure 2-8 • Typical Ethernet Baseband Configuration

• ETHERNET ON BROADBAND
Ethernet broadband is a high-speed communications network that provides the same capabilities as baseband plus capabilities that allow the
transfer of audio and video information. The broadband Ethernet transceiver implements DEC net Phase IV software and the same controllers are
used as with baseband. Broadband networks also use the same terminal
and communication servers, concentrators, DEC net routers, and gateways
as the baseband network except that network repeaters are not required.
Broadband operates with a single coaxial cable or with dual coaxial cables.
The coaxial cables are RG-59-U type, and the same type of cable connectors, signal splitters and amplifiers that are used for cable TV can be used
with the broadband equipment. Figure 2-9 shows a typical Ethernet broadband network configuration. The communications controller in the host
processor connects to the DECOM transceiver through a four-twisted-pair
wire cable and the DECOM transceiver connects to a tap in the broadband
network cable through a broadband coaxial drop cable. The twisted-pair
cable is the same type used with the H4000 transceiver on the baseband
network.

2-14· VAXcluster and Network Architecture

Broadband Tap

Broadband Cable

<III

Broadband Drop
Cable

<III

Transceiver Cable

DEUNA

VIIX
PROCESSOR

Figure 2-9 • Typical Ethernet Broadband Configuration

DECOM Ethernet Broadband Transceiver- The DECOM Ethernet broadband transceiver, shown in figure 2-10, is a tabletop unit and is the physical
and electrical interface to the broadband coaxial cable. The transceiver
transmits signals to and receives signals from the connected systems and
detects message collisions. Two types of DECOM transceivers are available,
one for the single-cable broadband network and one for a dual-cable
broadband network.

The single-cable transceiver (DECOM-BA) transmits 54 to 72 megahertz
signals and receives 210.25 to 228.25 megahertz signals. This transceiver
requires a frequency translator (DEFTR) at the headend of the network to
convert the Ethernet signals from their transmit to their receive
frequencies.
The dual-cable transceiver (DECOM-AA) transmits and receives the
Ethernet signals at the same frequencies-from 54 to 72 megahertz.

2-15

Figure 2-10 • DECOM Ethernet Broadband Transceiver

The features and benefits of the DECOM transceivers are:
Transceiver can be located close to other Digital products.
Channel transmissions are within assigned bandwidths, eliminating channel interference.
Diagnostic indicator lights verify correct configurations and provide an
aid for servicing the unit.
Internal self-test and loop back capabilities allow fast diagnosis and fault
isolation.
Redundant protective circuits insure reliability and confine failures to a
single transceiver, preventing loss of the entire nerwork.
Message collisions are reported to all transceivers to allow the Ethernet
to be monitored at any transceiver location.

2-16' VAXc!uster and Network Architecture

DEFTR Ethernet Broadband Frequency Translator- The DEFTR frequency
translator is used to enable bidirectional communication transfers on a
single-cable Ethernet system. It receives all Ethernet signals transmitted by
the systems connected to DECOM transceivers, translates them, and
retransmits the signals at the appropriate DECOM receive frequencies. The
unit is installed at the headend of the network as shown in figure 2-11. It
contains front panel monitors to aid in isolating both headend transceiver
problems. Two DEFTR units can be connected in parallel to increase the
reliability of the Ethernet communication.

ETHERNET CONTROLLER";;'

~t:::::::::;

Headend
//- / /

Transmit at Low Frequency
(54 to 72 MHz)

OEfTR-AA -..- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .JI

I
I

----- - - -----R~c~i~e~i-HighFr~q~~~y------- ___
'-,__ Translates
Low to High

(210.25 to 228.25 MHz)

Single-Cable broadband networks

Headend
~---------

///""--

Transmit & Receive
at Same Frequencies

\,,'~~~~~~~(5~4~to~72~M~H~Z,,;,)~~~~~~~~~<=:::F~~~~~

---

Dual-Cable broadband networks

Figure 2-11 • DEFTR Ethernet Broadband Frequency Translator

2-17

Some of the features of the DEFTR unit are:
Two DEFTR translators and a swit"ching unit are available as an option to
enable information on the Ethernet to be automatically switched from
one DEFTR unit to another if a failure occurs in one unit.
Front panel monitors assist in the diagnosis and isolation of headend and
transceiver failures.
Allows constant access to the Ethernet channel.
• ETHERNET COMMUNICATION CONTROLLERS
The Ethernet communication controller (DEUNA) is an intelligent highperformance synchronous interface that mounts on the VAX. processor
UNIBUS and allows communication with either the baseband or broadband Ethernet network. The controller consists of two hex-height modules
that are installed in the UNIBUS backplane and connect to the H4000
transceiver in the baseband network or to the DECOM transceiver in the
baseband network. The controller, which is supported under DEC net
Phase IV software, provides the Ethernet data link layer functions and part
of the physical channel functions. The DEUNA allows communication of
up to 1,023 addressable devices on the Ethernet network. Figure 2-12
shows the DEUNA controller, the H4000 transciever, and cable connections.

1/0 DISTRIBUTION

PANEl.
j(ONNECTOR
PANEL

VAX PROCESSOR

/'..
U
N
I
B

U
S

(:)

DEUNA
ETHERNET
CONTROLLER
MODULE

r
~r-

...,

~ ~

FLAT CABLE

I lJ

BNE3 CABLE

r~
L

H4000
ETHERNET
TRANSCEIVER

ETHERNET _ /
COAXIAL CABLE

Figure 2-12 • DEUNA Controller and H4000 Transceiver Connections

2-18· VAXcluster and Network Architecture

• H 4000 ETHERNET TRANSCEIVER
The H4000 Ethernet Transceiver, shown in figure 2-13, includes the interface circuits and hardware to connect the network nodes to the baseband
Ethernet coaxial cable. It operates with the Ethernet communications controllers to transmit signals to the cable, to receive signals from the cable,
and to detect message collisions that may occur. The Ethernet communications controller mounts in the UNIBUS backplane of the VAX processor
and connects to the H4000 unit through a cable up to 50 meters (164 feet)
long. The cable transfers the information and supplies the power to the
H4000 interface circuits. The Ethernet cable segment can be up to 500
meters (1,640 feet) long or longer through the use of Ethernet repeaters.

Figure 2-13 • H4000 Baseband Ethernet Transceiver Unit

The H4000 transceiver contains a logic module and includes a unique
cable clamp that makes contact with the internal cable conductor and
holds the cable in place. A special installation kit is available to prepare the
cable for installation. The cable can be installed or removed from the unit
without interrupting the network operation. The H4000 unit contains
redundant protective circuits and self-testing functions and provides high
noise immunity to the signals transferred through the cable. A continuous
message loopback feature simplifies fault isolation to reduce maintenance
time and cost. The unit electrically connects to the controller through the
transceiver cable that attaches to the end of the housing, as shown in figure
2-12.

2-19

Local and Remote Ethernet Repeaters - The Ethernet repeaters (DEREP) are
tabletop, stand-alone units that connect separate segments of the baseband
Ethernet coaxial cables together, thereby increasing the effective length of
a single cable. The repeaters connect to each of the two cables through the
H4000 transceiver and extend the coaxial cable beyond the single cable
length of 500 meters (1,640 feet). Up to 99 H4000 transceivers can be
connected to each cable segment. The repeaters contain an internal power
supply and logic to retime, amplify, and repeat the signals it receives from
the H4000 transceiver. The features of the repeater unit are as follows:

• Increases the"effective length of the Ethernet coaxial cable and the number of devices supported.
• Installed without interrupting network operation.
• Contains self-test features to reduce maintenance cost and increase
reliability.
• Remote-repeater fiber optic cable can be installed underground or in a
harsh environment.
• Detects faulty signals insuring integrity of data transmissions.
• Contains diagnostic lights to assist in network troubleshooting.
• Redundant repeaters can be installed in a network to increase reliability
of transmissions.

Both local and remote repeaters are available; they connect to the Ethernet
cable segments through the H4000 transceiver and transceiver cables. The
local repeater connects two coaxial cable segments that are separated by a
distance of up to 100 meters (328 feet); the remote repeater connects two
cable segments up to a distance of 1,000 meters (3,280 feet) apart. The
local and remote repeaters are shown in figure 2-14.

2-20. VAxcluster and Network Architecture

Local Ethernet Repeater

Remote Ethernet Repeater

Figure 2-14· Ethernet Network Repeater Units

2-21

The local repeater is a single unit that provides the transmission path
betweeen the two cable segments through the H4000 transceiver. The
remote repeater consists of two local repeater units that are connected by a
fiber optic cable. The total distance between the Ethernet cables can be
1,000 meters (3,280 feet). A fiber-optic logic interface module is available
as an option and can be added to a local repeater unit to perform as one of
the remote repeater units. The network configuration of the local and
remote units is shown in figure 2 -15 .

H4000
Terminator

Ethernet Coaxial Cable

Ethernet Coaxial Cable
H4000

Terminator

Figure 2-15 • Ethernet Network Repeater Configuration

Local Network Interconnect- The device local network interconnect
(DELNI) is a low-cost, tabletop, concentrator unit that allows up to eight
processors, servers, or other Ethernet-compatible devices, except terminals, to be connected together or to be connected through the DELNI and
H4000 transceiver to an Ethernet cable. The unit contains a power supply
and can be placed at any convenient location where ac power is available.
The DELNI operates either as a stand-alone unit not connected to an
Ethernet cable or in a network configuration connected to a cable. Because
up to eight processors or Ethernet units can be connected, the cost of
adding servers and processors to the network can be reduced using the
DELNI instead of the Ethernet hardware normally required. The DELNI
unit, shown in figure 2-16, provides the following features:

2-22· VAXcluster and Network Architecture

• Reduces the cost of multiple connections to the Ethern.et coaxial cable.
Connects Ethernet compatible devices in small networks, thereby
eliminating the need for coaxial cable and H4000transceivers.
• Contains a mode switch to allow the unit to be changed from stand-alone
to connected configuration.
• Permits more than 100 devices to be connected to a single coaxial cable
segment.

Figure 2-16· DELNI Local Network Interconnect Unit

In the stand-alone configuration, two DELNI units can be connecteq
together to increase the total number of devices. The distance between the
DELNI units can be up to 50 meters (164 feet). Figure 2-17 shows the
DELNI stand-alone configuration.

DELNI

DEUNA

VAX 8600

VAX-11I7S0

Figure 2-17 • DELNI Stand-alone Configuration

In the network configuration, the DELNI connects to the H4000 transceiver through the transceiver cable and up to eight devices can be connected to the DELNI unit as shown in figure 2-18. The transceiver cable
can be a direct connection to the H4000 transceiver or can be connected
through the Etherjack wallplate.

H4000

Terminator

Ethernet Coaxial Cable

[)Elil\,-\

VAX 8600

VAX-ll/lSO

VAX-II/730

MICRO/
PDP-lI

Figure 2-18· DELNI Network Configuration

• ETHERNET COMMUNICATION SERVERS
Ethernet communication servers are microprocessor-controlled, specialpurpose units that connect terminals to an Ethernet network or connect an
Ethernet network to other Ethernet and local area networks (LANs)
through communication lines. All communication servers connect to the
Ethernet LAN through the H4000 transceiver and cable. The Ethernet
communication servers are programmable units that perform dedicated
communication functions. They contain maintenance operation protocols
to enable the operating and diagnostic software to be loaded into the server
memory from the Ethernet host processor. In the event of a software malfunction, the server will attempt to transfer the memory information to the
host processor for evaluation and will reload the software again into memory. All Ethernet communication servers are the same size and have a similar physical col1figuration, as shown in figure 2-19.

2-24· VAXcluster and Network Architecture

Figure 2-19 • typical Ethernet Communication Server

Four communication servers are available for operation with the Ethernet
network: the Terminal Server, the DECnet Router Server, the DECnet
Router/X.25 Gateway Server, and the DEC net Router/SNA Gateway
Server. These units provide multiple CPU access and full modem control,
and the software can be downline loaded from the host processor. Each
unit contains power supplies, a PDP-ll/24 processor, an Ethernet-toUNIBUS communication controller, console/bootstrap terminators, up to
one Mbyte of memory, protocol assist modules, line protocol firmware, and
special function software that is optionally available. Each server is dedicated to perform a specific function; however, when communication
requirements change, the server can he adapted to the new functions by
replacing the line protocol firmware and the software. The features of the
communication servers are as follows:
• Provides resource sharing among multiple processor systems within an
Ethernet LAN
• Performs communication processing, eliminating CPU involvement
• Server operation is checked by automatic diagnostic tests performed during system startup
• Line cards can be tested online to reduce maintenance time and to minimize disruption of communications
• Changes in communication functions are easily implemented in the unit

2-25

Terminal Server- The Terminal Server provides a cost-effective and flexible means of connecting nonintelligent terminals to an Ethernet network.
Each connected terminal can access any host processor operating with
VAX/VMS or RSX software on a network of remote DECnet nodes. Access is
through DECnet router servers connected to the same Ethernet network.
Terminal access to the DECnet Router/X.25 Gateway or DECnet/SNA
Gateway Server is through the VAXIVMS host system that contains the
appropriate access routines. The features and benefits of the Terminal
Server are as follows:
Provides terminal access to multiple local hosts on the same Ethernet
network
Performs I/O processing functions normally performed by the host CPU
• Same Terminal Server software operates with a 16- or 32-line hardware
configuration
• Ability to access multiple host processors reduces the number of terminals connected to individual host processors
• Increases reliability and redundancy by allowing terminals logically connected to a failed host processor to access other host processors on the
Ethernet network
Up to 32 asynchronous terminals can be connected to the Terminal Server
locally through null modem cables or remotely through modems and dialup lines. Through simple commands, the user establishes a logical connection to a system and has access to the standard commands and utilities
supported by the node. The Terminal Server supports the simultaneous
operation of the terminals at full-duplex rates of from 50 to 19,200 bits per
second to local Ethernet host processors that implement the local area host
(LAH) protocol. The Terminal Server controls and monitors the communication from the terminal to the host processor through a single Ethernet
interface resulting in a lower cost per line than with the traditional data
switches. The unit allows split-speed terminal operation and provides
modem control and monitoring, and automatic line-speed detection. The
Terminal Server supports EIA standard RS-232-C and CCITT standard V.28
for data transmission. A typical Ethernet network configuration with terminal servers is shown in figure 2-20.

2-26· VAXcluster and Network Architecture

Host
Processor

Figure 2-20 • Terminal Server Network Configuration

DECnet Router Server- The DECnet Router Server performs the routing
functions to permit the host VAX processors on an Ethernet network to
communicate with local or remote DECnet networks. The DECnet Router
implements DECnet Phase IV protocols and network management functions and can communicate with processors using DECnet Phase III or
Phase IV software. Using the DECnet Router, the computer netWorks can
consist of up to 63 areas, each with up to 1,023 nodes. The DECnet Router
connects to the Ethernet through the H4000 Transceiver and receives and
forwards messages between the DECnet network and Ethernet networks.
Figure 2-21 shows a typical DECnet Router network configuration.

2-27

Termlnat<)r

H4000

Ethernet Coaxial Cahle

Host
Processor

Host

Ethernet Coaxial Cable

Figure 2-21 • DEenet Router Network Configuration

The DECnet Router supports the direct connection of up to eight lowspeed, single-line, synchronous ErA standard RS-232-C or CCITT standard
V.28 interfaces operating at full-duplex transfer rates of up to 19,200 bits
per second or up to eight high-speed synchronous devices at full-duplex
transfer rates of up to 56,000 bits per second. The unit optionally supports
a single 500-Kbit-per-second synchronous line or a two 250-Kbit-persecond connection through a CCITT V.35 standard line interface. A DECnet Router is not required if the end nodes connected to the Ethernet
network communicate only with each other. The network management
functions of the router are performed by the Ethernet load host and
include the control and monitoring of the router operation and the fault
analysis of network problems.

2-28' VAXcluster and Network Architecture

DECnet RouterlX.25 Gateway Server- The DECnet Router/X.25 Gateway
connects DECnet nodes on an Ethernet network to DECnet nodes on an
X.25 packet-switched data network (PSDN) using the data link mapping
(DLM) capability of the Gateway software. The DECnet RouterlX.25 Gateway connects to an Ethernet through the H4000 Transceiver and to a
remote DECnet network through a modem and a telecommunication line.
The unit supports six lines at data rates up to 56 Kbits per second, 16 and
32 lines at rates up to 19.2 Kbits per second, two lines at 250 Kbits per
second, and one line at 500 Kbits per second. The features and benefits of
the DECnet/X.25 Router are as follows:
• Allows communication between applications being performed on VAX
systems and other manufacturers' systems.
• Allows an X.25-compatible PSDN to be used as the communication
. medium for DECnet, non-DECnet, and Digital-to-non-Digital data
traffic.
• Permits communication between remote terminals and VAX host proces,
· sors on the Ethernet network using the X.3, X.28, and X.29 protocols.
, Shares the PSDN access among the systems on the Ethernet network.
The unit includes the same function as the DECnet Router as well as additional functions. Host VAX processors on the Ethernet network that contains a VAX X.25/X.29 Extension Package have access to the facilities
offered by the PSDN to which the router is connected. This allows remote
terminals to access the host VAX processor by dialing in through the network packet assembler/disassembler (PAD), which is included in the extension package. Local terminals that are directly connected to the VAX
processor or are logically connected through the Terminal Server can
access other systems connected to the PSDN by dialing out through the
PAD facility. The extension package also allows access to the packet level of
the protocol software so that the VAX system user can design utility so&ware for.task-to-task communication between the VAX system and systems
developed by other manufacturers. The Ethernet network configuration,
including the router, is shown in figure 2-22.

2-29
Terminator

H4000

Ethernet Coaxial Cable

Host
Processor
Modem and

Host
Processor
DECnet/E (Phase III)

Host
Processor

Ethernet Coaxial Cable

Engineering

(Los Angeles)

Figure 2-22 • DECnet RouteriX.25 Gateway Network Configuration

DECnetiSNA Gateway Server- The DECnet!SNA Gateway server allows the
Ethernet network to communicate with remote IBM® System Network
Architecture (SNA). The unit connects to the Ethernet network through
the H4000 Transceiver and to the SNA network through the internal
modem and telecommunication line. The unit supports data transfer rates
of six lines at up to 56 Kbits per second, eight lines at up to 9.6 Kbits per
second, seven lines at 19.2 Kbits per second, two lines at a rate of 9.6 Kbits
per second, and one line at 256 Kbits per second. The features and benefits
of the DECnetiSNA Gateway are as follows:

®IBM is a registered trademark of International Business Machines Corporation.

2-30· VAxcluster and Network Architecture

• Provides the complementary features of both Digital and IBM network
environments.
• Provides 3270-terminal emulation, remote job entry, and user application
interface functions of the SNA.
• Includes gateway management software for control and maintenance.
The DECnet/SNA Gateway Server implements the SNA Gateway protocol
and is used with the appropriate VAXlVMS gateway-access software. Figure
2-23 shows the network configuration using the DECnet/SNA Gateway
Router.

Host
Processor
Access Routines -4-----

Remote Job Entry

Host
Processor

3270 Terminal Emulation
User Applications Interface

Ethernet Coaxial Cable

IBM
Host
Processor
Telephone Line - - - - - - '

Figure 2-23 • DECnet/SNA Gateway Network Configuration

UNIBUS Communication Interfaces and Devices
Digital provides a series of UNIBUS interfaces and devices that enable communication between processors and between processors and terminals.
The processors and terminals can be confined to the same site or located at
different sites. Communication between the remote sites is facilitated
through the use of private or public telecommunication lines. The interconnection of local and remote equipment is through a network configuration. A network is a flexible configuration of interconnecting terminals,
computers and other intelligent devices that are defined as nodes. The
communication hardware and software allow data transmission between
Digital's processors and equipment, and between Digital's processors and
other manufacturers' equipment. The transmission methods or protocols
that are required depend on the type of processors and devices that are
communicating with each other.

2-31

Asynchronous transmission uses a character orienter protocol and is primarily intended for intermittent low-speed data transmissions between terminals and their host computer. The transmission is controlled by the start
and stop elements of the character and the time intervals between character transmission is variable.
Synchronous transmission is used primarily for high-speed data transfers
between computers. It uses a block-oriented protocol and the data is transferred in one interval as a group or block of characters. The data characters
and bits are transferred at a fixed rate and the transmitter and receiver are
synchronized.
The digital signals that are transferred through most telephone lines are
converted to analog signals by a modem. The modem also reconverts the
analog signals to digital signals upon reception. Computers and devices
connect to the modems through standard interfaces that provide the
proper signal levels and characteristics. The interfaces are designed according to standards from the Electronic Industries Association (EIA) and from
the International Consultative Committee on Telephony (CCITT). Some of
these standards for telephone equipment in data transmission are EIA RS232-C/CCITT V28, EIA RS-422/CCITT Vll, EIA RS-423 IV. 10 and CCITT
V35. All Digital communication interfaces that conform to the industry
standards can be used to connect Digital systems to private branch
exchanges (PBXs) through modems .
• UNIBUS ASYNCHRONOUS INTERFACES
Single and multiline asynchronous interfaces are provided for communication between the VAX processors and terminals. The interface selection is
based on the number of lines, transmission speed and characteristics, and
the modem control requirements. These interfaces allow point-to-point
communication and multipoint communication between the nodes on the
network. The interfaces include the following:
• DMF31- A multifunction communication controller that provides an
eight-line asynchronous multiplexer, a single-line asynchronous interface,
and a general purpose parallel interface
• DMX32-A 24-line asynchronous multiplexer with DMA capabilities on
transmit lines and program-selectable split-speed transmit and receive
rates
• DZll-An eight-line asynchronous multiplexer with program selectable
transmit and receive rates
• DHUll-A 16-line asynchronous multiplexerwith DMA capabilities and
program-selectable transmit and receive rates

2-32' VAxcluster and Network Architecture
DMF32 Multi/unction Communication Controller-The DMF32, shown in

figure 2-24, is an intelligent multifunction communication controller that
permits modems and terminals to be connected to the UNIBUS. The
DMF32 consists of an eight-line asynchronous multiplexer, a single-line
asynchronous interface, and a general purpose parallel interface. It is
supported by VMS operating software, DECnet-VAX networking softw~re,
and VAX PSI communications software. Some of the features and benefits
of the controller are:
• Allows concurrent operation of the three controllers on one module
• Provides two asynchronous channels with full modem control and individually selectable transmit and receive baud rates
• Enables six local terminal connections
• Provides a parallel interface for DMA or SILO mode operation with a user
device or intelligent DMA line printer controller
• Performs control of 1/0 transfer operation, eliminating the processor
intervention

Figure 2-24 • DMF32 Multi/unction Communication Controller

2-33

The eight-line asynchronous multiplexer provides full-duplex operation at
speeds up to 19,200 bits per second. The data transmission can be in DMA
mode or first-in, first-out SILO mode. Two of the lines provide full modem
control and split transmission- and reception-speed capabilities. Six lines
are dedicated to local terminals and nd modem control is included. The
single-line synchronous interface operates at speeds up to 19,200 bits per
second in the DMA mode and provides full modem control and support for
both bit- and byte-oriented protocols. The general purpose parallel interface operates with either a line printer in DMA mode or with a user device
in DMA or SILO mode. The DMF32 is compatible with Digital's family of
modem devices and mounts in one hex slot of the UNIBUS backplane.
Figure 2-25 shows the configuration of the controller and the 110
connections.

DMFJ2 CONTROLLER

VAX
CENTRAL
PROCESSOR

'"
:0

'"~

EIGHT LINE
ASYNCHRONOUS
MULTIPLEXER

<==:::>
<==:::>
<==:::>

··
·
<==:::>

EXTERNAL MODEM (LINE 0)
EXTERNAL MODEM (LINE I)
LOCAL
TERMINALS (I.INES 2-7)
f.xHRNAL MODEM

SYNCHRONOUS
LINE INTERFACE

<==:::> [g~~~~?C~~IONS

I.INE PRINTER
OR
USER DEVICE
PARALLEL
INTERFACE

USER'S DEVICE
~ OR
(OUTPUT)

LP32 LINE PRINTER

<==:J~~~~~)DEVICE

Figure 2-25 • DMF32 Multi/unction Controller Configuration

DMZ32 24-Line Asynchronous Multiplexer- The DMZ32, shown in figure
2-26, is a 24-line asynchronous multiplexer that provides full modem control and direct memory access (DMA) capability on the transmit lines. It
enables the interconnection of remote terminals that conform to EIA RS232-C/CCITT V.28 to the host VAX processor through a modem. The
DMZ32 operates at full- or half-duplex transmission speeds up to 19,200
bits per second. The operating speed and line characteristics are selected
by the program. Split-speed transmit and receive rates are supported on
each of the 24 lines. The features and benefits of the DMZ32 are:

• Provides full modem control and split-speed capabilities on 24 lines
• Distribution panel can be mounted separately from the host processor in
any 48.26-centimeter (19 .O-inch) rack of cabinet
• Transmission rates are program-selectable

2-34· VAXcluster and Network Architecture

Figure 2-26 • DMZ32 24-line Asynchronous Multiplexer

The distribution panel connects to the single UNIBUS interface module
through a T1 cable that can be up to 1,524 meters (5,000 feet) long. The
panel can be mounted in the H9646 modem cabinet or any 48.26centimeter (19.0-inch) cabinet. The modem cabinet allows a combination
of modem devices, including the DFIOO series of modem enclosures and
the DMZ32 distribution panel, to be contained in the same cabinet. Figure
2-27 shows the configuration and cables associated with the DMZ32 multiplexer.

2-35

HOST PROCESSOR

U
N

~C)

DMZ32
INTERFACE
MODULE

Lt------'----fI "1!-_ _ _ _---!r

I I

..J

L f-l

T1 TWISTED-PAIR

'DMZ32
DISTRIBUTION
PANEL

SHIELDED CABLE

Lr-r1L_...l
L
I
N

'CAN BE REMOTELY MOUNTED OR IN CPU

•••

L
I
N

2
4

'-"

........

24 ASYNCHRONOUS
LINES TO MODEMS
OR LOCAL DEVICES

Figure 2-27 • DMZ32 24-line Asynchr(mous Multiplexer Configuration
DZll Eight-line Asynchronous Multiplexer-The DZll option, shown in
figure 2-28, is a low-cost, eight-line, asynchronous multiplexer that enables
local and remote communication between VAX processors, other Digital
processors, and terminals. It provides communication for both RS-232-C/
CCITT V.28 standard lines and 20-milliampere lines. The DZll provides
buffering for full-duplex operation at program-selectable speeds from 50
to 9,600 bits per second and limited modem control. Some of the features
of the option are:

• Low-cost, eight-line multiplexer
• Program-selectable transfer rates for each channel
• Compatible with Digital modems and BellI 00 and 200 series modems

2-36' VAxcluster and Network Architecture

Figure 2-28' DZll Eight-line Asynchronous Multiplexer

The DZll consists of a hex-height module that mounts in the UNIBUS
backplane, an interconnecting cable, and an I/O connection panel with 16
connectors for external lines. Figure 2-29 shows the DZll hardware
configuration.

HOST PROCESSOR

U
N

DZll
INTERFACE
MODULE

8- ASYNCHRONOUS
LINES TO MODEMS
OR DEVICES

1/0 CONNECTOR.---.

PANEL

Figure 2-29 • DZH Eight-Line Asynchronous Multiplexer C01i/iguration

2-37

DHUll 16-Line Asynchronous Multiplexer- The DHUll, shown in figure
2-30, is a 16-line asynchronous multiplexer that allows direct-memoryaccess transfers for the devices connected to the lines. It can be used for
local or remote communication between Digital's computers and intelligent terminals through EIA RS-232-C/CCITT V.28, or EIA RS-423-A/CCITT
V.1O standard interfaces. The DHUll provides half- or full-duplex operation at program selectable speeds of up 38,400 bits per second. Full
modem control and split-speed transfer and receive rates are included on
all lines. The features and benefits of the DHU 11 option are the following:
• Allows DMA transfers with devices on all lines
• Provides full modem control on all lines
• Program-selectable transfer rates up to 38,400 bits per second

Figure 2-30· DHUll 16-1ine Asynchronous Muliplexer

The DHUll option consists of a hex-height module that mounts in a slot
on the UNIBUS backplane, the internal cables and the I/O connection panel
with 16 mounted connectors. The configuration of the DHUll hardware is
shown in figure 2 -3 1.

2-38· VAxcluster and Network Architecture

HOST PROCESSOR

U
N

DHUll
INTERFACE
MODULE

16- ASYNCHRONOUS
LINES TO MODEMS
OR DEVICES

110 CONNECTOR_
PANEL

Figure 2-31 • DHUll16-line Asynchronous Multiplexer Configuration

• SYNCHRONOUS COMMUNICATION DEVICES
In addition to the DEUNA Ethernet communications controller previously
described in this chapter, Digital provides a complete series of synchronous
interfaces that permit high-speed data transfers between local and remote
processors and intelligent terminals. These options provide point-to-point
and multipoint communication with the nodes that operate with the Digital Data Communications Message Protocol (DDCMP) and other bit- and
byte-oriented protocols for fast and reliable data transfer. The synchronous
communication devices included are:
• DMPll- A high-performance, microprocessor-controlled, single-line synchronous interface for DMA transfers using DDCMP byte-oriented protocols in DECnet point-to-point and multipoint configurations
DMRll- A high-performance, microprocessor-controlled, single-line synchronous interface for DMA transfers using DDCMP byte-oriented protocols in DECnet point-to-point configurations
• DUPll-A high-performance, single-line, programmable synchronous
interface for byte- or bit-oriented protocols
• KMSll-B-An eight-line, microprocessor-controlled programmable synchronous controller for DMA transfers using Packnet System Interface
(PSI) network software, bit- or byte-oriented protocol, and X.25
protocol
• KMSll-P-A single-line, microprocessor-controlled, programmable synchronous communication controller for DMA transfers using Packnet
System Interface (PSI) network software and X.25 protocol

2-39

DMPll Single-line Synchronous Controller- The DMPll, shown in figure
2-32, is a single-line, high-performance, microprocessor-controlled, synchronous controller that allows local or remote connection between PDP11 and VAX processors and other computer systems. The DMPl1 provides
multi-CPU access that enables a message to be sent directly to one or more
processors without routing through another processor. The communication is through EIA RS-232-C/CCITI V.28, CCITT V.35, EIA RS-422/CCITT
V.ll, EIA RS-449, or EIA RS-423/CCITT V.1O standard interfaces. The
DDCMP is implemented in the controller microcode to insure maximum
thoughput and minimum processor intervention. The DMPll allows DMA
transfers in DECnet point-to-point or multipoint configurations. It operates
at a transmission speed of one Mbyte per second for half-duplex transfers
and performs half- and full-duplex transfers for all other speeds. The
DMPll option includes full modem control. The features and benefits of
the interface are:

• Point-to-point or multipoint operation
• Supports up to 32 tributaries in multipoint configurations
• Intelligent controller and hardware-implemented DDCMP reduces host
processor hardware and software intervention
• Communicates with any other DDCMP devices
• Supports DMA data transfers and provides full modem control with
many standard interface lines

Depending on the operating system and layered software, the DMPll can
support a maximum of 32 tributaries. In multipoint configurations, these
tributaries can be DMPll, DMVll, or DMF32 interfaces. In point-to-point
configurations, the DMPll can communicate with any other synchronous
interface that implements the DDCMP Version 3.1 or 4.0. The DMPll
option consists of two hex-height modules that mount in the UNIBUS
backplane, 1/0 connector panel inserts, and an interconnecting cable. Figure 2-33 shows the hardware configuration of the controller.

2-40' VAXcluster and Network Architecture

Figure 2-32 • DMPll Single-Line Synchronous Multipoint Synchronous
Controller

2-41

I
DMPII/DMVIl
CONTROL
STATION CPU

TRIBUTARY
STATION CPU

DMP11IDMVll

DMPlllDMVIl

TRIBUTARY
STATION CPU

MULTIPOINT COMMUNICATIONS NETWORK

::0

ADDRESS/DAB

TO RS232-C
MODEM
OR
TO RS42.l-A
MODEM

MICROPROCESSOR
MODULE

::0

'MODEM CABLE NOT
,..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--, SUPPLIED WITH OPTION
DMPII-AB SYNCHRONOUS
LINE CONTROLLER

ADDRESS/DATA

MICROPROCESSOR
MODULE

TO CCITTV..lS
MODEM

DMPII-AE SYNCHRONOUS

MICROPROCESSOR
MODULE

rr"LL---.J'--~

TO RS422-A
MODEM

"MODEM CABLE NOT
SUPPLIED WITH OPTION

Figure 2-33 • DMPll Synchronous Controller Configurations

2-42' VAXcluster and Network Architecture

DMRll Single-line Synchronous Inter/ace- The DMRll, shown in figure 234, is a high-performance, microprocessor-controlled, single-line, synchronous interface that allows local and remote connections between VAX
systems and other Digital systems. The communication is through EIA RS232-C/CCITT V.28, CCITT V.35, EIA RS-422/CCITT V.24, EIA RS-422/RS449, or EIA RS-423/CCITT V.24 standard interfaces. The DMRll
implements DDCMP protocols in hardware and ~upports direct memory
access data transfers and DECnet point-to-point configurations. It provides
half- and full-duplex operation at transmission speeds of 1 Mbyte per second and includes full modem control. The features and benefits of the
interface are as follows:

• Intelligent controller and hardware-implemented DDCMP reduces host
processor hardware and software intervention
• Communicates with any other DDCMP device
• Supports DMA data transfers and provides full modem control with
many standard interface lines

Figure 2-34 • DMRll Single-Line Synchronous Inter/ace

2-43

The DMRII option consists of two hex-height modules that mount in the
UNIBUS backplane, an I/O connector panel insert, and an interconnecting
cable. The DMRll option is available ",ith different interfaces, depending
on the line requirements of the modem. It is compatible with Digital's
family of modems and with Bell 200 series modems, Bell 500a L1I5 modem
or the equivalent. Figure 2-35 shows the hardware configuration of the
interface.

HOST PROCESSOR

/'U
N
I
B
U
S

DMRll
INTERFACE
MODULES

I
..J

I I
Lf-J

SYNCHRONOUS LINE

MODEM OR
~ TO
LOCAL DEVICE

110 CONNECTION_
PANEL
-

Figure 2-35 • DMRll Synchronous Interface Configuration
DUPll Single-line Synchronous Programmable Interface- The DUPl1,
shown in figure 2-36, is a high-performance, single-line, programmable
interface that allows communication between PDP-ll and VAX systems
and other computer systems. Communication is through EIA RS-232-C/
CCITT V.28 standard interfaces and provides half- or full-duplex operation
at transfer rates of up to 9,600 bits per second. The unit provides full
modem control and is programmable for byte-oriented Digital data communications message protocol (DDCMP), byte-oriented binary synchronous communications protocol, bit-oriented synchronous data link control
(SDLC), or bit-oriented high-level data link control (HDLC). The DMPll
interface can be used for remote batch and remote job entry applications
and is compatible with Digital's family of modems or Bell 200-series
modems and their equivalents. Some of the features and benefits of the
DUPll follow:
Programmable for bit- or byte-oriented protocols
Provides full-modem control
Double character-buffered receive and transmit
• Provides CRC check for DDCMP protocols

2-44' VAxcluster and Network Architecture

BC02C-l

MALE CINCH

BC05C-25
REQUIRED FOR
MODEM CONNECTION

DUPll-DA
SINGLE LINE ASYNCHRONOUS INTERFACE

Figure 2-36 • DUPll Single-line Synchronous Programmable Interface

The DUPll consists of one hex-height module that mounts in the UNIBUS
backplane, an 110 connector panel insert, and an interconnecting cable.
Figure 2-37 shows the hardware configuration of the interface.

HOST PROCESSOR

/'...
U
N
I
B

U
S

DUPll
INTERFACE
MODULE

r-,

i-J

IL-lI

SYNCHRONOUS LINE

MODEM OR
~ TO
LOCAL DEVICE

110 CONNECTION_
PANEL
-

Figure 2-37' DUPll Synchronous Programmable Interface Configuration

2-45

KM511-B Eight-line Synchronous Programmable Controller- The KMSll-B
controller, shown in figure 2-38, is an eight-line programmable communiclltions processor that operates with the host processor and performs many
of the communication functions normally performed by the processor. The
KMSll includes a 4-Kword RAM that can be programmed to perform
many dedicated communication operations between PDP-ll and VAX systems and other systems. The communication is through EIA RS-,232-C/
CCITT V.28, MIL-188-144 unbalanced, or CCITT V.35 standard interfaces.
The KMSll-B provides half- or full-duplex operation at transfer rates of up
to 56,000 bits per second with full modem control. The KMSll-B supports
DMA transfers, the VAX PSI software package and the CCITT standard
X.25, HDLC, bit-synchronous and byte-synchronous protocols. The CCITT
X.25 link-level software is currently warranted for four lines at 56,000 bits
per second or eight lines at 19,200 bits per second. Some of the features of
the KMSll-B follow:

Contains a high-speed LSI microprocessor and 4-Kbyte programmable
RAM for user applications programs
Suitable for customer-developed device interface requirements
Provides DMA data transfers for information on all eight lines
Separate line units available for specific line requirements

Figure 2-38 • KM511-B Eight-line Synchronous Programmable Controller

2-46· VAXcluster and Network Architecture
A software tools package is available to aid in the development and debugging of user programs for special communication applications. The software tools include utility programs to load the RAM from a file and
programs that enable the programmer to examine and modify the contents
of internal registers and memory.
The KMSl1-B consists of three hex-height modules: the microprocessor
module and memory, an eight-line modem control module, and an eightline multiplexer terminator module. The modules can be installed in an
existing UNIBUS backplane or in the DD 11-DK UNIBUS backplane that can
be included with the option. It also includes an eight-line 110 connection
panel unit and internal cables. The hardware configuration of the KMSll-B
is shown in figure 2-39.

HOST PROCESSOR

KMSll·B
CONTROLLER
AND INTERFACE
MODULE

8- ASYNCHRONOUS
LINES TO MODEMS
OR DEVICES

110 CONNECTION---.
PANEL

Figure 2-39 • KMSll-B Eight-Line Synchronous Programmable Controller
Configuration
KMSll-P Single-line Programmable Controller-The KMSll-P, shown in

Figure 2-40, is a single-line programmable communications processor that
operates with the host processor and performs many of the communication
functions normally performed by the processor. The KMS II-Pis similar to
the KMS11-B and includes a 4-Kword RAM that can be programmed to
perform many dedicated communication operations between PDP-ll and
VAX systems and other systems. The communication is through EIA RS232-C/~CITT V.28, EIA RS-423-AlCCITT V.1O, CCITT V.35, or EIA RS-422AlCCITT V. 11 standard interfaces. The KMS11-P allows half- or full-duplex
operation at a maximum transfer rate of64,OOO bits per second with full
modem control. The KMSll-P supports DMA transfers, the VAX PSI software package and the CCITT standard' X.25 protocol. Some of the features
of the KMS 11-P follow:

2-47

• Contains a high-speed LSI microprocessor and 4-Kbyte programmable
RAM for \:Iser applications programs
Suitable for customer-developed device interface requirements
Provides DMA data transfers
Separate line units available for specific line requirements

Figure 2-40 • KMSII-P Single-line Synchronous Programmable Controller

The KMSll-P consists of two hex-height modules: the microprocessor
module and memory, and a line terminator module. The modules can be
installed in an existing UNIBUS backplane. It also includes an I/O connection panel insert and an internal cable. The hardware configuration of the
KMS 11-P is shown in figure 2 -41.

2-48· VAxcluster and Network Architecture

HOST PROCESSOR

/'.
U
N
I
B

U
S

KMSlJ-P
CONTROLLER
AND INTERFACE
MODULES

I
--1

IL--1I

SYNCHRONOUS LINE
MODEM OR
S TO
LOCAL DEVICE

~~~~NNECTION _ _

Figure 2-41 • KM511-P Single-line Synchronous Programmable Controller
Configuration

• TERMINAL CONCENTRATORS AND MULTIPLEXERS
The DMF series of intelligent communication processors and the DZS11
terminal concentrator and statistical multiplexer provide the communication links to increase the number of terminals in a local network configuration and to increase the efficiency of the system's remote communications
facilities.
DZ511 Terminal Concentrator and Multiplexer- The DZS11 is a terminal
concentrator and statistical multiplexer. The DZSll receives low-speed
asynchronous communication from a maximum of eight VTlDO-AA or
VT100-AB video terminals and transfers the information to the host
processor through a synchronous line and interface. The information can
be from local VT100 terminals or from remote terminals through
modems. The maximum transfer rate from the UNIBUS to the terminals
through the DMZ 11 unit is 9,600 bits per second. The DZS11 option allows
up to eight local or remote VT100 terminals to be connected to the statistical multiplexer through a 19,200-bit-per-second synchronous link and
divides the communication line capacity according to the user's needs. The
asynchronous lines to the terminals conform to ErA RS-232-C/CCITT
V.28 standards. The features of the DMS 11 option are:

Increases the communication speed to local and remote terminals from
the host processor
Decreases the connecting lines from terminals to the host processor
Dynamically distributes the communication information according to the
user requirements
• Allows two terminal concentrators to be connected to the DZSll unit

2-49

The DZSll option consists of a terminal concentrator module and 110
connector panel that mount on the VT100 terminal and a hex-height statistical multiplexer interface module that mounts in the UNIBUS backplane.
Up to seven VT100 terminals can be connected to the terminal concentrator module, which mounts into the backplane of a single VT100 terminaL A
connector panel at the rear of the VT100 transfers the information from the
attached terminals and routes the information through the terminal concentrator and to the synchronous interface installed in the host system
UNIBUS backplane. The DZS11 synchronous line consists of a hex-height
module that mounts into the UNIBUS backplane, an 110 connection panel
insert, an 1/0 connection panel and an internal connecting cable. The cable
connectors for the cable that connects the host processor to the VT100
terminal are supplied. Figure 2-42 shows some of the possible DZSll configurations.

HOST PROCESSOR

~o
II

DZSI1-EA

INTERFACE
MODULE

..,

I I

..J

~:~~~~NNECTION ------.. L....--

MODEM OR LOCAl
CONNECTION
LINE 1

I
L

f--'

VT\OOTERMINAL

Y-IIXX-EB

X-CHANNEl

MULTIPLEXER
MODULE

~
MODEM OR LOCAL
CONNECTION _____
VT100 TERMINAL

~
L

VTiXX·EB

8·CHANNEl
...r MULTIPLEXER

MODULE

• ...r
.~

Figure 2-42 • DZSll Terminal Concentrator/Multiplexer Network
Configuration

2-50· VAxcluster and Network Architecture

• DMF SERIES OF STATISTICAL MULTIPLEXERS
The DMF series of statistical multiplexers are intelligent communication
processors that concentrate data from multiple low-speed communication
lines into a single high-speed line. The DMF units support DMA transfers,
asynchronous or synchronous data communication, optional integral
modems, and expansion of from 4 to 16 lines. The modem transfer rates
are 4,800 and 9,600 bits per second. The unit includes automatic speed
detection, speed and flow control conversion, local and remote echo, flyback character control, and dialup support on EIA standard RS-232-ci
CCITT V.28 lines. A switched and contention feature allows a logical
connection to be established between a user's terminal and other compatible devices connected to the ends of the network. Asynchronous speeds are
from 50 to 9,600 bits per second with autobaud above 150 bits per second.
The concentrated link speeds are from 1200 to 19,200 bits per second. The
synchronous channels include 16-bit error detection with automatic
retransmit when an error is detected. Autodial is supported on the EIA
lines. The DMF unit is shown in figure 2-43. Some of the unit features are:
Increases the communication speed to local and remote terminals from
the host processor
Decreases the connecting lines from terminals to the host processor
Dynamically distributes the communication information according to the
user requirements
Provides extensive management and control
Easy expansion through the addition of line modules and integral
modems

Figure 2-43 • DMF Statistical Multiplexer Unit

2-51

The DMF series of multiplexers are separate units that can be placed on a
tabletop or mounted into a cabinet 48.26 centimeters (19.0 inches) wide.
The DMF units are available with 4, 8, 12, or 16 data channels and include a
power supply and communication processor. The communication lines
connect to the rear of the unit and the front cover provides access to the
communication line modules. A hex-height synchronous parallel interface
module that mounts into the UNIBUS backplane, an I/O connection panel,
and internal cable are supplied with the option and provide the connection
from the processor to the DMF unit. Some of the possible DMF multiplexer
hardware configurations are shown in figure 2-44.

HOST PROCESSOR

U
N
I
B
U
S

DFM
INTERFACE
MODULE

r-,

I I

-.J

L-.J

1/0 CONNECTOR--+
PANEL
-

DFM
STATISTICAL
MULTIPLEXER

L;-,JL;-...l
L
I
N
E
1

L.--

...

L
I
N
E
1
6

L.--

4-16 SYNCHRONOUSI
ASYNCHRONOUS
PRIVATE LINES

Figure 2-44 • DMF Statistical Multiplexer Configuration
PCL11-B Parallel Communications Link- The PCLll-B unit, shown in figure 2-45, is a parallel communications interface that allows multipoint connection of up to 16 processors in a local distributed network. The
processors can send or receive messages or blocks of data to or from any
other processors in the network. Communication occurs in a DMA block
transfer mode through the time division multiplexed (TDM), 16-bit differential, parallel bus. The TDM bus allows all 16 processors to communi• cate concurrently using DMA transfers. The PCLll-B provides full-duplex
operation at transfer rates of up to 1 Mbyte per second. The features of the
PC Lll-B are as follows:

• Provides efficient parallel DMA communication between up to 16 VAX
processors in a local area
• High system availability and data transfer rates
• Adjustable TDM bandwidth allocations among CPU nodes

2-52' VAxcluster and Network Architecture

Figure 2-45 • PCL11-B Parallel Communications Interface

The PCLll-B unit consists of four hex-height modules and one quadheight module that mount in a DDll-DK double system unit backplane
supplied with the option. The unit connects to the I/O connection panel
through an input and output cable, which is also supplied. External BCl7U
and BC17C cables are included. The maximum cable length is 91.5 meters
(300 feet). Figure 2-46 shows a typical network configuration consisting of
three computers and the PCL1l-B communications interface.

Figure 2-46 • PCIl I-B Parallel Communications Inter/ace Network
Configuration

253

DT07-xx UNIBUS Interface Switch Series- The DT07-xx UNIBUS interface
switch is available as a series of options that permits UNIBUS devices to be
shared by up to four PDP-ll or VAX processors. The UNIBUS section and
associated devices are switched between the processors to provide highdata availability and the dynamic sharing of the data stored on devices. The
DT07 is provided in three different configurations depending on the number of processors to be implemented and on mounting configuration
requirements. The switching may be performed manually or under control
of the program. The interface contains a timer that disconnects the
UNIBUS when the controlling CPU has halted or the program is invalid and
reconnects the backup processor. The features of the DT07 follow:

Provides high data availability and sharing of data resources by up to four
processors
Switching performed manually or under control of the software
DT07 -xx options tailored to specific applications and expandable for
future applications
The DT07-xx options are supplied in many different configurations. The
basic option consists of a hex-height UNIBUS repeater module that mounts
in a separate UNIBUS backplane and connects to the UNIBUS cables from
the processor. The DT07 -xx can be supplied in a mounting box with
UNIBUS backplane, UNIBUS repeater and terminator modules, switching
panels, and other configurations, depending the number of attached processors and the system mounting requirements. Figure 2-47 shows a typical
DT07 switching configuration.

HOST PROCESSOR

CONTROL PANEL

/'..
U
N
I
B
U
S

UNIBUS
INTERFACE
MODULE

r-,

I I

-J

I/O CONNECTOR_
PANEL
-

DT07-XX
UNIBUS
SWITCH

r
UNIBUS 1-'

•••

L-J

UNIBUS 4

I
L

Lr-,.JL_-.J

i...----

..-v-

PERIPHERAL DEVICES

Figure 2-47· DT07 UNIBUS Switch Configuration

2-54' VAxcluster and Network Architecture

fEPCM Front-End Communication Processor- The FEPCM option, shown
in figure 2-48, is a powerful user-programmable, front-end PDP-1l123PLUS or PDP-11124 processor that can perform sophisticated control functions for many communications applications, thereby off-loading the
communications handling from the host VAX processor. Because a PDP-ll
processor is used, many different types of communication devices and
interfaces developed for the PDP-ll are available. Through the use of the
PDP-ll instruction set, a variety of existing software programs for general
purpose communications applications are also available and specialpurpose applications can be produced using the PDP-ll program development software. Unlike other communication processors, the FEPCM can
perform the communication functions using disk storage devices, printers,
and other types of interfaces, including AID converters. The FEPCM provides an efficient means to significantly improve the communication
performance of a VAX processor. The features and benefits of the FEPCM
option are as follows:

Provides the powerful performance and software of the PDP-ll for
sophisticated communication applications
Easily programmed for special-purpose applications
Simplifies VAX processor communication tasks
• Provides multifunction capabilities

Figure 2-48' FEPCM PDP-11123-PLUS Front-end Communications Processor

The FEPCM communication processor is available mounted in the H9642
cabinet or can be mounted in a standard cabinet or rack 48.26 centimeters
(19.0 inches) wide. It contains the PDP-1l/23-PLUS or PDPll-24 microproccessor and memory, UNIBUS backplane, and power supply. It connects
to the VAX processor UNIBUS through a UNIBUS backplane connector and
attached cable. Figure 2-49 shows the FEPCM and VAX processor
configuration.

2-55

,---

HOST PROCESSOR

U
N
I
B

1J
S

"""

<=>

UNIBUS
INTERFACE
MODULE

f-l

I
L

f-l

1/0 CONNECTOR----+

PANEL

'---

FEPCM
PDP-11/23 PLUS
OR
PDP-11114
PROCESSOR

COMMUNICATIONS
INTERFACES

L_-1L,-,..-l

---

l.,....-

DEVICES OR
MODEMS

Figure 2-49 • FEPCM Communication Processor Configuration

• MODEMS AND MULTIPLE MODEM ENCLOSURES
Digital's modems are reliable communication devices that are used to
transfer information between Digital's systems, terminals, and devices and
many systems and terminals of other manufacturers through public or private leased telephone lines. The modems convert the digital data to analog
signals for transmission through the lines and convert the analog signals to
digital data at the remote location upon reception. The selection of a
modem is determined by the transmission speed requirements, the type of
data transmission and data characteristics, and the interface signals standards. Digital provides a complete series of modem units and modem
enclosures for a variety of applications. The modem units are small tabletop devices that can be conveniently located and the modem enclosures
enable many modems to be mounted in a single location. Figure 2-50
shows a typical local and remote system configuration using Digital's
modems. Some of the modem features are:
Small and reliable units fully supported by Digital's service organization
Provide effective communications between many types of transmission
devices
Available for full- and half-duplex transmission
FCC approved for direct connection to telephone lines

r--------,
SITE A

I
I

IL _________ .JI

ASYNC
LINES

r----

I 2 ASYNC
I

LINES WITH
MODEM
CONTROL

r----------------,

f- - - - -

s;:
~

PRINTER
INTERFACE

DFOJ·RA MODEM
OFOJ-RC MODEM
OF03-RC MODEM
~

DF03-RA MODEM

II"PTO

12 PSTN

TELEPHONE
LINES

I
I
I
I'

;;.

"'~."
~

DF100-RM

DF03·RA MODEM
FUTURE USE
FUTURE USE
FUTURE USE
DFOJ-RA MODEM
DF03·RC MODEM
DF03-RA MODEM

f
::.,.

IL ___
;;:~~FACE
_
I

~
~

6 LOCAL

L..'- - ' - - _ - - " ' -. . . .

I
I

L __ _

_ ___ ..J
SITE C

Figure 2-50' Typical Modem Network Configuration

2-57

DF02 and DF03 Modem Units-The DF02 and DF03 modems are small
reliable units that can be conveniently positioned on a desk or table and
provide full-duplex transmission through unconditioned dialup of twowire leased lines. The units contain a power supply and connect directly to
the telephone lines through a cable and RJl1C connector. An RJl1C receptacle located at the rear of the unit enables the unit to be connected to a
standard telephone for both voice and data communication. Also mounted
at the rear of the unit is a standard EIA connector, which permits the units
to be connected to a computer or device that conforms to EIA standard RS232-C. These connectors allow the units to be easily installed and removed.
Both modems contain a row of push switches to select the transmission
requirements and indicator lights that display the modem status. The
modems are available with or without the automatic call unit (ACU) feature
that permits calls to be initiated without dialing manually on a telephone.
DF02 modems permit full-duplex, asynchronous transmission at switch
selectable data rates up to 300 bits per second. It includes local and remote
test capabilities, and calls can be originated and answered manually or
automatically under the control of the computer or device. It is compatible
with all Digital asynchronous data communications controllers that support EIA RS-232-C standard interfaces. When used with a standard telephone, the DF02 offers alternate voice and data capabilities. The DF02 is
physically similar to the DF03 modem and is compatible with the DF03
modem and with BelllD3J and 212J data sets at rates up to 300 bits per
second. The DF02 modems are available in two configurations: the DF02AA and the DF02-AC. The units contain the same features except that the
DF02-AC contains the ACU and uses an asynchronous ASCII input format
at data rates of 110, 300, and 1,200 bits per second and can store up to 16
digits for dialing and redialing.
The DF03 modem, shown in figure 2-51, allows full-duplex, asynchronous
or synchronous transmissions at data rates up to 300 bits per second or at
1,200 bits per second. At the low speed rate, up to 300 bits per second, the
data transferred is asynchronous, and at 1,200 bits per second the data can
be either character asynchronous or bit synchronous. The DF03 modem is
compatible with the BelllD3J data sets at low speeds, with the Bell 212A
data sets at the 1,200 bits per second rate, and with all Digital communication controllers that support EIA RS-232-C standard interfaces and dialup
modem control. The DF03 modem is available in two configurations: the
DF03-AA and the DF03-AC. Both units contain the same features except
that the DF03-AC includes the additional functions described for the
DF02-AC modem.

2-58· VAXcluster and Network Architecture

Figure 2-51 • DF03 Modem Unit
DFlOO Multiple Modem Enclosure-The DFlOO modem enclosure, shown
in figure 2-52, can be positioned on a table or installed into a standard
cabinet or rack 48.26 centimeters (19.0 inches) wide and occupies a vertical mounting space of 26.7 centimeters (10.5 inches). Up to 12 single-card
modem modules can be installed into the enclosure and modems can be
added to expand the communication facilities. The DFlOO unit eliminates
the cables normally required for individual modem units. The DFlOO
includes a power supply that provides power to the modem modules and
includes space for a redundant power regulator that assumes the power
load if the standard regulator becomes defective. The modem modules are
installed from the front of the cabinet and the connectors for the device
and telephone lines are located at the rear of the unit. The features of the
DFlOO multiple modem enclosure follow:

• Houses up to 12 modem modules and contains internal power supply
and optional power regulator
• Allows modules to be easily installed and removed for service or modem
expansion
• Simplifies cabling requirements
• Allows selection of modem module types

2-59

Figure 2-52· DFlOO Multiple Modem Enclosure
A complete series of modem modules are available for specific communication requirements. The following modules are available for either a public
switched telephone network (PSTN) or private leased telephone network
(PLTN).
• DF112-AM-Provides full-duplex, asynchronous or synchronous operation at transfer rates of up to 300 bits per second and at 1,200 bits per
second. Contains integral auto-dialer and operates with dialup PSTN lines
and two-wire leased line and multitype telephone service capabilities.
Compatible with Bell 212A data sets and with CCITT V.22 standard
interfaces.
• DFI26-AM-Provides half-duplex, asynchronous, or synchronous operation at transfer rates of 2,400 bits per second and is compatible with Bell
20lB data sets and with CCITT V.26 standard interfaces. Contains
manual-originate/ auto-answer or auto-originate/auto-answer capabilities.
Also available for full-duplex operation through four-wire, leased-line
applications.
• DFI27-AM-Provides half- or full-duplex, synchronous operation at
transfer rates of 4,800 bits per second through PLTN lines. Compatible
with Be1l20lB data sets and with CCITT V.26 standard interfaces. Contains auto-originate and auto-answer capabilities. Assumes a transfer rate
of 2,400 bits per second if the integral power supply fails.

2-60· VAXcluster and Network Architecture

• DF129-AM-Provides full-duplex, synchronous operation at transfer rates
of 9,600 bits per second through PLTN lines. Compatibl~ with CCITT
V.27 standard interfaces and provides auto-originate and auto-answer
capabilities. Assumes a transfers rate of 2,400 bits per second if integral
power supply fails.

The VAX-1l/725 and the VAX-l1lnO central processing units (CPUs) are
32-bit, microprogrammed computers that execute the VAX instruction set
in native mode and support the VMS operating system. The VAX-l1l730
processor also supports ULTRIX-32 software, which is Digital's supported
native UNIX'" operating system. Both processors execute nonprivileged
PDP-ll processor instructions in the compatibility mode, allowing existing
user-mode PDP-ll programs to run without modification.
The CPUs perform the logic and arithmetic operations requested by the
computer system user. They use 32-bit addresses which provide access to
4.3 Gbytes of virtual address space. The processor's memory management
hardware translates virtual addresses to physical addresses. The processor
contains sixteen, 32-bit registers that can be used for temporary storage, as
accumulators, index registers, and base registers. The native instruction set
includes integer, packed decimal, character-string bit field, floating-point,
and program control instructions and special instructions. The CPU can
process the same data types as the larger-VAX processors, including bits,
bytes, words, longwords, and quadwords. The floating-point accelerator
option can be installed in either the VAX-1l1725 or VAX-Ulna processor
to decrease the instruction execution time of floating-point instructions
and some integer arithmetic operations. The main features of the processors are:
," UNIX is a trademark of AT&T Bell Laboratories.
32-bit microprogrammed VAX processor.
Soft control store, which allows loading of microcode revisions and
microdiagnostics.
Programmed array logic (PAL), which increases logic density and reduces
cost.
PDP-U compatibility mode.
Optional floating :point accelerator.
Dual TU58 cartridge tape drives as console ioading devices.
Small CPU packaging.

3-2· VAX-IlI725 and VAX-1l1730 Processors

. VAX-1l1725 Processor System
The VAX-1l1725 is Digital's smallest and least expensive VAX system and
includes the UNIBUS for 110 communications. It is a VAX-1l1730 system
specially packaged in a small cabinet 62.23 centimeters (24.5 inches) high,
which includes an RC25 disk drive subsystem. The VAX-1l/725 is designed
for single-user workstation applications or economical multiuser systems.
The unit is shown in figure 3-1 and includes the following features:
• Low heat dissipation and power requirements
• Small cabinet that can be positioned under a desk or table in an open
office or similar environment
• Special power wiring and air conditioning not required
• Cabinet mounted on casters for easy relocating
• Hardware and documentation for customer installation
• Reliable mass-storage subsystem contained in CPU cabinet

Figure 3-1 • VAX-1l1725 Processor Unit

3-3

The standard components included with the system are:
VAX-luno CPU and power system
1 Mbyte of ECC MOS main memory
Two TU58 tape cartridge drives
RC25 , 52-Mbyte, fixed and removable media disk subsystem
• Pedestal cabinet with rollers
• VAXIVMS operating system license
The CPU system backplane provides slots for UNIBUS option expansion;
however, the UNIBUS cannot be expanded outside the system cabinet. One
backplane slot is assigned to the floating-point accelerator (FPA) option
module.
Figure 3-2 shows the VAX-1l/725 cabinet dimensions and the 110 connector panel configuration at the rear of the unit. Seven spaces are available for
mounting connector panel units, a console terminal connector, and a
remote diagnostic connector. One of the panel units is dedicated to the
cable connector for the VSlOO graphics workstation terminal. The console
terminal and remote diagnostic service modem are options.

3-4· VAX-lll725 and VAX-lll730 Processors

Cabinet Front View

-l.I-+-II--PANEL UNIT

PANEL UNIT--l-I-+--IiilPANEL UNIT--I-I-HoI-

-l.I-+-II--PANEL UNIT

-lJ-~--P1\NEL UNIT
-I4-'---'--P1\NEL UNIT

~~--P1\NEL UNIT

SYSTEM CONSOLE
CONNECTION

POWER
INPUT"---H--

REMOTE
DIAGNOSTIC
CONNECTION

11111111111111111111111111111111111111111111111
Cabinet Rear View

Figure 3-2 • VAX-1l1725 Processor Unit Configuration

3-5

RC25 Disk Subsystem
The RC25 disk subsystem is a reliable, 52-Mbyte, disk drive that uses Winchester technology and provides the flexibility of both fixed and removable
disks. Twenty-six Mbytes of storage are confained on a nonremovable
8-inch disk and 26 Mbytes are stored on an 8-inch removable disk cartridge. A total of 50 Mbytes is available to the user. The RC25 subsystem
includes an intelligent controller, microdiagnostics programs for automatic
self-tests, and remote diagnostic testing. The subsystem provides most
Digital Storage Architecture (DSA) capabilities and has the highest performance and capacity of any disk drive ~th fixed and removable disks .

. VAX-11/730 Processor System
The VAX-11/730 is the smallest of the VAX systems that permit full
UNIBUS device and mass storage expansion capabilities. It is designed for
general purpose, realtime, and time sharing applications. The system is
enclosed in a cabinet 53.9 centimeters (21.25 inches) wide, and 106.7 centimeters (42.0 inches) high. It contains two standard backplanes, one for the
CPU, main memory and option~ modules and one assigned specifically to
UNIBUS expansion. A VAX-11/730 packaged system is shown in figure 3-3.
It features:
• A CPU and mass storage devices contained in a single-width, low-height
system cabinet to reduce floor space and cable requirements.

• An integrated disk controller that operates with one R80 fixed-media and
three RL02 removable-media disk drives.
• Memory expansion up to 3 Mbytes.
• A UDA50 disk controller for connecting up to four disk drives.

3-6· VAX-1l1725 and VAX-1l1730 Processors

Figure 3-3 • VAX-UlnO Processor Unit

A variety of CPU, mass storage, communications, and I/O options can
be installed within the VAX-ll/730 CPU cabinet or in a separate
UNIBUS expansion cabinet. The standard system includes the following
components:
• The CPU and power system
• 2 Mbytes of ECC MOS memory

• A mass storage device
• VAX/VMS software license

3-7

VAX-ll/730 Disk Controllers and Drives
The REno integrated disk controller (IDC) mounts in a slot in the CPU
backplane and controls the operation of an R80 disk drive and from one to
three RL02 disk drives. It also can be connected to a total of four RL02 disk
drives when the R80 disk drive is not included. Data is transferred between
the IDC and CPU through the accelerator bus and is controlled in part by
dedicated microcode in the CPU. During a read or write transaction, 32-bit
longwords of disk data are transferred following the generation of a microlevel (fast) processor interrupt request by the IDe. Silo registers in the IDC
provide up to I Kbyte of data buffering for both read and write data. The
IDCs can also be connected to the UNIBUS for device inter.rupts other than
the fast interrupts generated for disk data transfers. When connected to the
UNIBUS, the IDC monitors the system's powerfail state.
The UDA50 is a microprocessor-based disk controller that operates with
the UNIBUS and allows a total of four RA60, RA80, or RA81 disk drives to
be connected in any combination. It provides Digital Storage Architecture
(DSA) capabilities.
Figure 3-4 shows the cabinet dimensions and equipment configuration of
VAx-l1/nO packaged system.

53.9cM _ _ 1

21.25 IN.
RL02 DISK
DRIVE

c::J
I

RL02 DISK
DRIVE

I
CPU
VAX-11/730

II
100.3CM
39.5 IN.

CPU
VAX-11J730

III

III DDJ

=1
RBO DISK
DRIVE

RBO DISK DRIVE

106.7 eM
42 IN.

ASYNCHRONOUS
DEVICES

TSUDa

REMOTE
DIAGNOSTIC

SYNCHRONOUS

DEVICE

CONSOLE
TERMINAL

DRORLP
DEVICES

POWER
CONTROLLER

~U
FRONT VIEW

REAR VIEW

Figure 3-4 • VAX-1l1730 Packaged System Configuration

3-8- VAX-1l1725 andVAX-1l1730 Processors

VAX-ll/730 Processor Organization
The VAX-ll1730 CPU logic consists of three hex-height modules: the data
path (DAP) module, writable control store (WCS) module, and memory
controller (MCT) module. The WCS module contains the console subsystem logic. A floating-point accelerator (FPA), contained ort a hex-height
module, is available and mounts in a dedicated slot of the CPU backplane.
Programmed array logic (PAL) used in the CPU increases the logic density
and reduces costs. It consists of high-density logic arrays contained on an
integrated circuit (IC) and manufactured with TTL Schottky bipolar logic
and fusable-link technology. The PALs are programmable AND circuits
connected to fixed OR circuits. The circuit is configured by disconnecting fusable links within the Ie. Figure 3-5 shows the organization of the
, VAX-111725 and VAX-ll/730 processor logic and internal bus structure.
The CPU microc;ntroller consists of a writable control store memory, a
control store register, and a microsequencer. The writable control store is a
programmable read or write- memory that is loaded from the TU58 tape
drive during the system bootstrap operation and provides storage for up to
20K microinstructions. The basic control store is a 16K by 24-bit dynamic
RAM array and contains the microinstructions for the native-mode and
PDP-ll compatibility-mode instructions. A 4K by 24-bit RAM array can be
installed to support the integrated disk controller for user microcode. Each
microinstruction is 24 bits long and contains several fields that control
specific CPU functions. The microsequencer determines the sequence in
which the microinstructions are read from the control store and loaded
into the control store register for processing.
The CPU data path performs the arithmetic and logical operations necessary to execute the instruction set. The principal data path components are
4-bit processor slices. Eight of these slices are connected in parallel to give
an arithmetic and logical processing element 32-bits wide. The data path
also contains a 256 by 32-bit local storage RAM that includes the general
registers and several of the architecturally defined privileged processor registers. The data path is controlled by the microcode that is executed in the
CPU's microcontroller.
An address translation buffer contains frequently used virtual address
translations. It significantly reduces the CPU time required for repetitive
address translations. The buffer contains 128 virtual-to-physical page
address translations consisting of 64 system space translations and 64
process-space translations. Each of these sections includes parity on each
entry for increased data integrity.

r -=RC2SOiSK - -,
SUBSYSTEM
ACCELERATOR

(FPAI

RC25
FIXEDI
REMOVABLE
DISK DRIVE
52MBYTE

CONSOLE
SUBSYSTEM

tMBYTEECC
MOSMEMORY

=:~!
TERMIN~dJ II

OORB730
INTEGRATED

REMOTE
TERMINAL

1/'-'\

DISK
CONTROLLER
(IDC)

2TU58 T;;:AP:E===::J
DRIVES <0

~
W

R80
AND

RC25
DISK
CONTROLLER

r ::"TsU05 TAPE --,
SUBSYSTEM

---,1
TSU05
MAGNETIC

1
I

!Z~B~~:E

TSU05
TAPE
CONTROLLER

RL02
DISK
DRIVES

1
1
1
1
1
1

1
1
1
1

r--------,......-.8-ASYNCHRONOUS
nDMF32
LINES
I-SYNCHRONOUS
MULTIFUNCTION
LINE
COMMUNICATION
CONTROLLER

<=:>

l-PARALLEL LINE

----r
UNIBUS

"INCLUDED WITH VAX-t1l725 ONLY
nINCLUDED WITH VAX-1l/730 PACKAGED SYSTEMS ONLY
...... INCLUDED WITH VAX-1l1730 R80/TSU05 PACKAGED SYSTEM

Figure 3-5· VAX-111725 and VAX-1U730 Processor Organization

3-10· VAX-1l1725 and VAX-1l1730 Processors

A one-Iongword prefetch instruction buffer allows the next instruction to
be fetched while an instruction is executing. The control logic continuously
fetches data from memory to keep the longword buffer full. In native
mode, the variable length instructions are stored in contiguous byte positions in memory and are aligned on byte boundaries. In compatibility
mode, the PDP-ll instructions are 16 bits long, occupy two contiguous
bytes, and are aligned on word boundaries.
The VAX-ll/730 processor contains an interval timer and a time-of-year
clock. The interval timer is used to measure small time intervals and the
time-of-year clock is used by software to perform various timekeeping
functions .
• INTERNAL BUS STRUCTURE
Communications between the main logic elements in the CPU is through
the internal bus structure, which consists of a memory control (Me) bus,
memory array bus, console bils, FPAlport bus, and IB bus. External communication to the peripheral devices is through the UNIBUS.
The MC bus is bidirectional and connects to the WCS, DAP, and MCT module. It has 32 lines that transfer data and address information during memory and UNIBUS reference by the CPU. The data and address information is
transferred during separate bus cycles. The MC bus is also used as part of
the data path during nonprocessor request (NPR) transfers between a
UNIBUS device and the memory array.
The memory array bus connects the MCT module to the memory array
modules. One of five bus lines is enabled to select one of the five array
modules, and fifteen bus lines are used to select the referenced memory
location in the array. Two bank select lines are used to select a 64K location
within the selected module.
The FPA/port bus connects the FPA module and the integrated disk controller (IDC) module to the CPU. The bus consists of 32 data lines, and the
remaining lines provide data strobe and synchronizing signals to control
the bus transfers.
An eight-line console bus is a buffered extension of the AD bus of the
8085A console microprocessor. It transfers 8 bits of data between the console processor on the WCS module and the data path logic on the DAP
module.
The IB bus, which is part of the instruction processing logic on the DAP
module, is an eight-line bus that connects to the FPA module. It allows the
FPA to sample the 8-bit opcode data during the CPU's class decode
operation.

3-11

• WRITABLE CONTROL STORE FUNCTIONS
The execution of the system-level instructions and operations is sequenced
and controlled by the microprogram contained in the writable control
store (WCS) module. The WCS also contains the console subsystem, which
is the main operator and maintenance interface. The WCS consists of the
following logic:
• Console subsystem
• CPU control store logic
• Clock generator and interval timer
• UNIBUS data transceivers

Console Subsystem- The console subsystem, shown in figure 3-6, consists
of the front panel switches and indicators, the console terminal port,
remote diagnostic port, two TU58 tape cartridge drives and interface, and
the console-CPU interface logic. The 8085A microprocessor executes
the console program that controls the console and terminal functions.
A 4-Kbyte or 6-Kbyte ROM contains the resident portion of the program
and a 16-Kbyte RAM stores the main part of the console program. The
6-Kbyte ROM is used when the remote diagnostic service option is included. The RAM, which is loaded from the TU58 drive during the
system bootstrap operation, stores the microdiagnostic and microdiaghostic monitor program. The console terminal, remote diagnostic line, and
TU58 tape drives each connect to the console subsystem through universal
synchronous/asynchronous receivers and transmitters (USARTS).
Data and address information is multiplexed and transferred within the
console subsystem through the AD bus. An 8-b"it console write register and
an 8-bit console read register, which are on the DAP module, are used to
transfer the data between the console subsystem and the CPU.
A clock generator and interval timer provide the basic timing signals and
timing intervals for the system operation. The interval timer is controlled
by the microprocessor and provides the basic timing for console interrupts,
power fail functions, and the time-of-year clock. The interval timer permits
measurement of small time intervals. The time-of-year clock is used by
software to perform various timekeeping-functions.

3-12· VAX-1l1725 and VAX-lll730 Processors

RESIDENT ROM
4K16K

16K

SYSTEM
CONTROL PANEL

SERIAL LINE
INTERFACE

INTERVAL
TIMER

CPU/CONSOLE
INTERFACE

0
IMIC;~~~~:SSOR K. . .

BOOTSTRAP RAM

A/DBUS

---=---------c=---------,,;:-----'

CONSOLE
TERMINAL_
TWO TU58
DRIVES

REMOTE
DIAGNOSTIC
SERVlCE_

Figure3-6 • VAX-111730 Console Subsystem

• DATA PATH FUNCTIONS
The data path logic on the DAP module performs the arithmetic and logical
operations necessary to execute the instruction set. The logic consists of
• Data path processor slices
• Instruction and interrupt processing logic
• CPU microsequencer

• Console registers
The data path consists of eight 4-bit processor slices connected in parallel
to provide a 32-bit processing element. The data path also contains a 256
by 32-bit RAM that includes general registers and several architecturally
defined priviliged registers. The instruction and interrupt-processing logic
is controlled by the microcode executed in the CPU micro controller, which
consists of the microsequencer and the soft control store on the WCS module. The one-Iongword prefetch instruction buffer is part of the instruction
processing logic and allows the next instruction to be fetched while an
instruction is executing. The control logic continuously fetches data from
memory to keep the longword buffer full. In native mode, the variable
length instructions are stored in contiguous byte positions in memory and
are aligned on byte boundaries. In compatibility mode, the PDP-ll instructions are 16 bits long and occupy two contiguous bytes aligned on word
boundaries.

3-13

The console registers are an 8-bit read register and an 8-bit write register
and are used to transfer data, one bit at a time, between the console processor and the CPU data path .

• MEMORY CONTROLLER FUNCTIONS
The memory controller (MCT) module contains the memory and UNIBUS
control logic. The memory control logic controls data transfers to and from
the main memory array modules over the array bus. The UNIBUS control
logic controls transfers to and from the peripheral devices over the
UNIBUS. The memory control contains the following logic elements:
• Address translation buffer
• UNIBUS map and arbitrator

• Data rotator and substituter
• Microsequencer and control store
• Error correction logic (ECC)
Data transfers are initiated by the CPU data path under the control of the
CPU microcode, or by the UNIBUS devices when direct data transfers are
made between the devices and memory. The translation buffer converts
virtual addresses to physical addresses. The physical addresses are then
applied to the memory array modules. The address translation buffer contains frequently used virtual address translations. It significantly reduces
the amount of time that the CPU requires for the repetitive task of dynamic
address translation. The buffer contains 128 virtual-to-physical page
address translations-64 system-space translations and 64 process-space
translations. Each of these sections includes a parity check on each entry to
ensure the data integrity.
The UNIBUS map converts 18-bit addresses to physical memory addresses.
The UNIBUS arbitrator regulates activity on the UNIBUS and assigns the
memory controller to the CPU if the controller is not being used by a
UNIBUS device.
A 32-bit longword of data is always retrieved from the memory; however,
the requested byte may not be in the proper position for transfer. The data
rotating and substituting network aligns the memory data in the proper
order.

3-14'; VAX-1l1725 and VAX-lll730 Processors

The control store RAMs'and associated logic supply 72-bit microwords that
control operations within the memory controller. The memory microsequencer selects each subsequent 72-bit microword. The ECC logic detects
and corrects single-bit errors when a longword is read from the memory
array.
• MAIN MEMORY SUBSYSTEM
The main memory in the VAX-11/730 processor consists of from one to five
I-Mbyte memory array modules. A memory array contains four banks and
each bank is composed of 39 64K by I-bit metal oxide semiconductor RAM
integrated circuits (ICs). Memory data is transferred over the array bus as a
32-bit longword (4 bytes) and seven associated ECC bits. Single-bit errors
are corrected and double-bit errors are detected but not corrected. All
errors are reported back to the CPU, where they may be recorded for use in
preventive and corrective maintenance operations.
Basic Memory Operations-The physical address space contained in the
memory controller is grouped into 15 Mbytes of physical memory addresses and 1 Mbyte of I/O device addresses. A physical address location
is selected by 24 address bits to enable access to a total of 16 Mbyte locations. During CPU or I/O transfer operations, the system performs a
read or a write operation to the addressed location. The hexadecimal address assignments of the physical address space are shown in figure 3-7.

HEXADECIMAL
ADDRESS

- - - - - - - - ,..------------,""

____ ~ ;:~ _ 1-_-'-I/_O_SP_'A_C_E
_ _---1I{} 1 MB
EF FFFF

MEMORY
SPACE

15MB

____ ~~o~ _ '---_ _ _ _ _ _ _ _v

Figure 3-7 • Memory Controller Physical Address Space

3-15

The error correction code (ECC) logic generates seven check bits from the
32-bit longword and appends these bits to the longword before it is stored
in memory. Data read from memory is examined by the ECC logic to determine if an error has occurred. The ECC logic generates seven syndrome bits
from the 39 retrieved bits to indicate no error, a single-bit error, or
multiple-bit errors. The single-bit errors in the data are corrected using the
seven syndrome bits and the CPU is informed that the data has been corrected. If a multiple-bit error is detected, the CPU is informed that the
transferred data contains errors.
During a read operation, the physical address on the array bus selects a
me{Ilory module and a location on the module. The addressed longword
and its seven associated check bits from the specified location are placed
onto the array bus. The ECC logic examines the longword and check bits
for data errors. If a data error is found, the error is corrected and the
corrected read data bit is set in the control and status register (CSRl). If
the error cannot be corrected, the cycle is aborted and the read data substitute bit is set in CSRl. The ECC logic returns the longword to the array bus
for the data rotator. The data is aligned, if necessary, and then sent to the
MC bus.
When the CPU reads data from memory, the longword is sent to the CPU.
When the CPU reads information from a UNIBUS device, the device data
that was read is taken from the UNIBUS data lines, transferred to the MC
bus through the writable control store transceivers, sent to the data rotator,
and then transferred to the CPU. If a UNIBUS device initiates the read operation, a byte or word of data is transferred to the data lines of the UNIBUS.
When the CPU writes data, the data to be written is placed on the MC bus
by the CPU and then sent to the data rotator. If the data is to be written to
memory, the data. rotator sends the data to the array bus. If the data is to be
written to a UNIBUS device, the rotator sends the data back to the MC bus,
which then places it on the data lines of the UNIBUS. When a UNIBUS
device writes data to memory, the data is placed on the MC bus, sent to the
data rotator, and then placed onto the data lines of the array bus. The ECC
logic accesses the write data from the array bus and generates seven ECC
check bits. The data and check bits are then returned to the array bus. The
data and associated check bits are taken from the array bus and written in
the selected array module.

3-16· VAX-1l1725 and VAX-11/730 Processors

• MEMORY CONTROL AND STATUS REGISTERS
Three control· and status registers in the main memory subsystem provide
control signals to the memory controller and report status information to
the cpu. The control and status registers are CSRO, CSRl, and CSR2.
Memory ControllStatus Register 0- Memory controllstatus register 0
(CSRO) is a read-only register that contains the ECC check bits. The cpu
reads the check bits to determine if a data error has occurred. Figure 3-8
shows the format of the CSRO.
31

8 7 6

16 15

2423
I

I I I I

0
I

I I I I

ERRsYND

NOkUsED

Figure 3-8 • Memory ControllStatus Register 0 Format

Bit
31-7

Function
Not used.

6-0

ERR SYND (Error syndrome) - These bits are syndromes if a
correctable error occurred during a CPU-to-memory transaction,
or are check bits if a non correctable error occurred.

Memory ControllStatus Register 1- Memory control/status register 1
(CSRl) is a read-write register. The cpu writes control bits into CSRI for
maintenance functions and to regulate the operations of the memory controller. Errors relating to a transfer between the cpu and memory are
sensed by the error logic and error bits are set in the CSRI to inform the
cpu of the error condition. Figure 3-9 shows the format of the CSRI.

31 30 29

lJ
DATA
ERR
IND

16 15 14 13

2423

I ~I
CNTL

I~ I
TRANS ERR

8 7 6

I J I
I

NOT USED

0
I

Iy I I

DIAGCHK

Figure 3-9 • Memory ControllStatus Register 1 Format

3-17

Bit
31:30

Function
DATA ERR IND (Data error indicators) - Set to indicate the following errors:
Bit 31 Read data substitute - Set when an uncorrectable data error
is detected during a CPU read-memory operation.
Bit 30 Corrected read data-Set when a single-bit error has been
detected and corrected during a CPU read-memory operation.

29:25

CTRL (Control)-Set to cause the following functions:

Bit 29 Translation buffer parity diagnostic- When this bit is set, a
parity error will occur during an access to the translation buffer.
Bit 28 Inhibit reporting of corrected read data - Set to inhibit the
reporting of corrected read-data errors. When this bit is set, the
detected errors will be corrected by the ECC logic and syndromes
will be logged in bits 6 and 0 of the CSRO; however, the corrected
read data (bit 3~) will not be set.
Bit 27 Memory management enable - Set to enable address translations in the translation buffer. When cleared, the CPU address will
be mapped directly into physical memory. The UNIBUS map is
always enabled.
Bit 26 Diagnostic check - Set to indicate that the memory controller is in the diagnostic mode.
Bit 25 Disable ECC - Set to disable the ECC function of memory.
24

Not used.

23: 14

TRANS ERR (Transactional error)-Set to indicate that an error has
been detected during a read or write transaction as follows:

Bit 23 Modify reference - Set to indicate that the modify bit was
not set when an entry, referenced with a write-check-protection
request, was made in the translation buffer.
Bit 22 Access referenced - Set to indicate that the access requested
by the CPU was not allowed when memory management is enabled. This bit is ignored if the translation buffer parity error (bit
15) is set.
Bit 21 Translation buffer miss- Set to indicate that the translation
buffer tag and bits 30: 15 of the virtual address register (VAR) did
not match or that the byte offset bit of the VAR was not set.
Bit 20 Illegal UNIBUS operation-Set by an operation error to indicate that the CPU attempted to perform a memory operation in
compatibility mode that was illegal or that the CPU attempted an
illegal UNIBUS reference.

3-18· VAX-lll725 and VAX-lllnO Processors

Bit

Function
Bit 19 Write-across-page error-Set if a CPU write operation with a
write check attempts to write across a page boundary.
Bit 18 Adapter register select-Set to indicate that the physical
address of a memory reference is located in the 768-Kbyte UNIBUS
adapter space.
Bit 17 UNIBUS busy- Set to indicate that a CPU has initiated a
UNIBUS transaction and the UNIBUS is busy.
Bit 16 Nonexistent memory- Set to indicate that the memory
select decoder has referenced a memory address that does not
exist.
Bit 15 Translation buffer parity error- Set to indicate that a CPU
access to the translation buffer resulted in a parity error.
Bit 14 Translation buffer valid - Set to indicate that the TB entry
valid bit is not set during a CPU access to the translation buffer.

13-7

Not used.

6-0

DIAG CHK (Diagnostic check bits) - Used to check the ECC logic.

Memory Control/Status Register 2- Memory control/status register 2
(CSR2) is a read-only register. Errors relating to a transfer between the
UNIBUS and memory are sensed by the error logic and the appropriate bits
are set in CSR2. When the error logic causes a timeout on the UNIBUS, the
CPU reads the error bits in CSR2. Figure 3-10 shows the format of CSR2.

17 16 15 14 13

NOT USED
UB READ DATA SUB

LUL

8 7

NO't USED

WR NOT VALID
UB TB PAR ERR
UB NON EXIST MEM

Figure 3-10 • Memory ControllStatus Register 2 Format

3-19

Bit
31

Function
UB READ DATA SUB (UNIBUS read data substitute) - Set to indicate that an uncorrectable error was detected during a UNIBUS
read-to-memory transaction.

30: 17

Not used.

-----.-.------------------.~---

UB NON EXT MEM (UNIBUS nonexistent memory)-Set to indicate that a UNIBUS request referenced a nonexistent memory
location.

UB TB PAR ERR (UNIBUS translation buffer parity error) - Set to
indicate that a TB parity error was detected during a UNIBUS
to memory transaction.

WR NOT VALID (Write not valid)-Set during a two-cycle operation to indicate that an attempt to write into a memory page
occurred and that the translation buffer did not contain a valid
entry for the page.

13:0

Not used .

• PROCESSOR OPTIONS
The main memory of the VAX-1l/725 and VAX-11/730 processor can be
expanded by adding MA730 memory arrays modules. Each MA730 array
module contains 1 Mbyte of ECC MOS memory.
The FP730 floating-point accelerator is a hardware option that operates
with the VAX-1l1725 and VAX-1l/730 processors to execute the standard
floating-point instruction set. Floating-point representation permits a
greater range of number values than is possible with a 32-bit integer. The
FP730 is a single, hex-height module that is easily installed in the CPU
backplane. It is functionally transparent to the user. The use of the FP730
does not require hardware and software modifications; however, the CPU
microcode must be reloaded from the TU58 tape drive.
The FP730 receives an opcode from the CPU and decodes the information
into a starting microaddress. The control store RAM outputs control the
arithmetic operations and data path logic. The FP730 option executes addition, subtraction, multiplication, and division instructions, which operate
on single-precision (32-bit), double-precision (64-bit), extended-range
double-precision (64-bits), and extended-range quadrupled-precision
(128-bits) operands. It executes extended multiply (EMOD) and polynomial evaluation (POLy) instructions, and converts data between integer
and floating-point formats and between single- and double-precision
floating-point formats. The FP730 also executes integer multiplication and
division instructions. The floating-point instructions performed by the
FP730 are listed in table 3-1.

3-20· VAX-1l1725 and VAX-lJl730 Processors

Table 3·1· FPA Floating, Double, and Integer Instructions
Opcode

Mnemonic

Opcode

Mnemonic

40
41
60
61
40FD
41FD
60FD
61FD
42
43
62
63
42FD
43FD
62FD
63FD
44
45
64
65
44FD
45FD
64FD
65FD
46
47
66
67
46FD
47FD
66FD
67FD
48
68
48FD
68FD
49
69
49FD
69FD

ADDF2
ADDF3
ADDD2
ADDD3
ADDG2
ADDG3
ADDH2
ADDH3
SUBF2
SUBF3
SUBD2
SUBD3
SUBG2
SUBG3
SUBH2
SUBH3
MULF2
MULF3
MULD2
MULD3
MULG2
MULG3
MULH2
MULH3
DIVF2
DIVF3
DIVD2
DIVD3
DIVG2
DIVG3
DIVH2
DIVH3
CVTFB
CVTDB
CVTGB
CVTHB
CVTFW
CVTDW
CVTGW
CVTHW

4BFD
6AFD
6BFD
56
99FD
98FD
76
32FD
33FD
56FD
F6FD
F7FD
76FD
4C
6C
4CFD
6CFD
4D
6D
4DFD
6DFD
4E
6E
4EFD
6EFD
51
51FD
71FD
54
54FD
74FD
55
55FD
75FD
71
74
75
C4
C5
C6

CVTRGL
CVTHL
CVTRHL
CVTFD
CVTFG
CVTFH
CVTDF
CVTDH
CVTGF
CVTGH
CVTHF
CVTHD
CVTHG
CVTBF
CVTBD
CVTBG
CVTBH
CVTWF
CVTWD
CVTWG
CVTWH
CVTLF
CVTLD
CVTLG
CVTLH
CMPF
CMPG
CMPH
EMODF
EMODG
EMODH
POLYF
POLYG
POLYH
CMPD
EMODD
POLYD
MULL2
MULU
DIVL2

3-21

Opcode

Mnemonic

Opcode

Mnemonic

4A
4B
6A
6B
4AFD

CVTFL
CVTRFL
CVTDL
CVTRDL
CVTGL

C7
4F
6F
4FFD
6FFD

DIVU
ACBF
ACBD
ACBG
ACBH

The VAX-ll/750 processor, shown in figure 4-1, is a midrange member of
the VAX family. It implements the VAX architecture and operates with
VAXIVMS operating system and associated layered software or with
ULTRIX-32, a Digital enhanced UNIX-based operating system. The VAX11/750 is an efficient processing system that is designed for the concurrent
operation of many users in performing timesharing or batch processing, or
for realtime applications. Some of the features of the VAX-ll/750 systems
follow:

Provides full VAX power in a relatively small cabinet
Operates with UNIBUS and MASSBUS devices
Can include up to 8 Mbytes of main memory
• Incorporates custom gate array technology to reduce the physical size
and power consumption of the CPU and increase system reliability
• Provides 4 Kbytes of direct mapped memory to improve memory cache
access time and increase overall performance
• Offers a user-control-store option to increase throughput by allowing the
user to create routines in microcode tailored to specific applications
• Offers a floating-point accelerator option to decrease time required for
floating-point arithmetic and for some integer-arithmetic operations

4-2' VAX-1l1750 Processor

Figure 4-1 • VAX-1l1750 Processor Unit

4-3

. VAX·11/750 Processor System
The VAX-1l1750 processor is a 32-bit, synchronous microprogrammed
computer that executes variable-length instructions in native mode and
nonprivileged PDP-ll instructions in compatibility mode. Execution of
logic and arithmetic operations is controlled by the program. The use of
32-bit virtual addresses allows access to over 4 gigabytes of virtual address
space. The processor's memory management hardware translates virtual
addresses into physical addresses. The processor includes sixteen 32-bit
registers that can be used for temporary storage and as accumulators, index
registers, and base registers.
The native instruction set is highly versatile and bit efficient. It includes
integer, packed-decimal, character string, bit field, and floating-point
instructions; and program control and special instructions. The instructions and data can vary in length and can start on any byte boundary or, in
the case of bit fields, at any arbitrary bit in memory.
The CPU processes data in the form of bits, bytes, words, longwords, and
quadwords. It also processes 32-bit, single-precision and 64-bit, doubleprecision floating-point data; packed-decimal data up to 31 digits; and
character-string data of up to 64 Kbytes. The standard components
included with the processor are
• CPU control store

• Internal data paths
• 4-Kbyte direct-mapped memory cache
• 512 -entry address translation buffer
• 8-byte prefetch instruction buffer
• Time-of-year clock and programmable realtime clock
• Optional floating-point accelerator
• Optional 10K by 80-bit user-control-store memory
Most of the logic circuits in the VAX-1l1750 CPU consist of custom LSI
(large-scale integration) gate arrays. Gate arrays are high-density logic circuits that use low-power Schottky technology. The circuits are configured
by Digital during manufacture to conform to the circuit requirements.
Compared with conventional circuits, gate arrays increase the speed and
decrease the physical size and power consumption of the logic circuits.
Because fewer components are necessary to implement the same functions,
the system reliability is significantly increased.

4-4· VAX-1l1750 Processor

VAX-ll/750 System Configuration
The VAX-1l1750 processor is contained in cabinet 106.7 centimeters (42.0
inches) high and 76.3 centimeters (29.0 inches) wide. The cabinet, shown
in figure 4-2, is on casters and can be easily moved. The control panel and
TU58 cartridge tape drive are on the front of the cabinet for easy access.
The cabinet contains a CPU and memory backplane and a UNIBUS backplane. The CPU and memory backplane provides space for installing up to
eight I-Mbyte memory modules, a remote diagnostic module, a floatingpoint accelerator module, and a writable-control-store module. Three
spaces are available for I/O expansion and can include UNIBUS adapters
and MASSBUS adapters. The UNIBUS expansion backplane has seven slots
in which I/O device adapters and interface modules can be installed. The
CPU cabinet also includes a space for the memory battery backup unit and
an I/O connection panel area at the rear of the unit for mounting I/O
device connectors.

Two H9642 UNIBUS expansion cabinets, shown in figure 4-3, are available
to extend the UNIBUS from the system cabinet. Both UNIBUS cabinets are
106.7 centimeters (42.0 inches) high and 53.9 centimeters (21.25 inches)
wide. An RL02, R80, or R81 disk drive and BAll-K mounting box can be
mounted in the H9642-FA (120-volt) and H9642-FB (240-volt) expansion
cabinets and a BAll-K mounting box can be installed in the H9642-FC
(120-volt) and H9642-FD (240-volt) expansion cabinets. The DDll-CK and
DDll-DK UNIBUS backplanes can be installed in the BAll-K mounting
box.

4-5

_ _ _ _ _ _ _ 73.6 CM _ _ _ _ _-I.~I
29 IN.

~oooOOO

...

MEMORY AND

CONTROLLER

UNIPUS

~~~~~~
(DOll·0K)

106.6 CM
42 IN.

POWER SUPPLIES

CON~~LLER

SPACEFOA

MEMORY

BAC~~~~~ION
(H11121

(fRONT VIEW)

~
c:
o

~c:
c:

• •

[I]
(REAR VIEW)

Figure 4-2 • VAX-111750 Processor Cabinet Configuration

4-6' VAX-ll17 50 Processor

H9642-FA(FB)

H9642-FC(FD)

Space For
Disk

Space For
BA11-K

One
Panel Unit

Space For
BA11-K

I
II v Controller
Power

One
Panel
Unit

lfit;f

-j.-

Power

T
J

(Rear View)

~
T

(Rear View)

Controller

41_8'

""1
Figure 4-3 • H9642 UNIBUS Expansion Cabinet Configuration

4-7

VAX·111750 Processor Organization

The VAX-ll/750 CPU logic is contained on the data path (DAP) module,
the UNIBUS interconnect module, the memory interconnect (MIC) module,
the memory controller (MCT) module, and the CPU control store module,
shown in figure 4-4. The UNIBUS interconnect module includes the console subsystem and asynchronous serial-line interfaces for the TU58 cartridge tape drive and console terminal. The remote diagnostic module
(RDM) and the floating-point accelerator (FPA) module are optional.
The CPU operations are controlled by a programmable read-only memory
(PROM), which contains the native-mode and PDP-ll compatibility-mode
instruction sets. A high-speed cache memory stores a copy of frequently
selected information from the main memory for fast access to instructions
and data. The processor includes an address translation buffer that contains frequently used address translations to reduce the time required for
dynamic address translation. An 8-byte prefetch instruction buffer
improves the CPU performance by accessing longword data in the instruction stream and storing the instructions prior to their actual use.
The VAX-ll/750 also contains a programmable realtime clock and a timeof-year and data clock. The time interval of the realtime clock permits the
measurement of finely resolved variable intervals. The time-of-year clock is
used by the software to perform timekeeping functions and provide the
correct time to the system in the event of a power failure or halt condition .
• INTERNAL BUS STRUCTURE
Communication between the main logic elements of the processor is
through the internal bus structure, which consists of the W bus, M bus,
memory-array bus and CMI bus. The CMI bus transfers information internally and externally to the 1/0 interfaces.
Under control of the microcode, information is transferred through 32 data
lines of the W bus. The W bus connects to the UNIBUS interconnect logic
and to the DAP logic, MIC logic, FPA logic, and remote diagnostic logic.
The M bus, consisting of 32 data lines, transfers information among the
DAP, MIC, and FPA logic under control of the microcode.
The CMI bus provides 45 bidirectional lines for transfers of address, data,
and priority arbitration information among all the logical elements of the
CPU.

"'00"
WBUS

:;;:

~
.....

t::::

~
c
c~
16

UNIBUS
INTERCONNECT
TU58 TAPE
DRIVE
CONSOLE
TERMINAL

DATA PATH
(DAP)

MEMORY
INTERCONNECT
(MIC)

"FLOATING
POINT
ACCELERATOR
(FPA)

SERIAL LINE
INTERFACES

UNIBUS
INTERFACE

ADAPTER
(MBA)

ADAPTER
(UBA)
"EXTENDED
RANGE
FPA(KU750}

"OPTIONAL HARDWARE

MASSBUS STORAGE
DEVICES

Figure 4-4 • VAX-ll/750 Processor Configuration

"REMOTE
DIAGNOSTIC
(RDM)

MEMORY
CONTROLLER
(MCT)

~...

4-9

• PROCESSOR LOGIC ELEMENTS
The VAX-ll/750 processor consists of the following logic elements contained on separate modules:
• Data path module-An extended-length, hex-height module that
includes arithmetic logic, rotator logic, microsequencer logic, scratchpad
registers, and interval timer.
• UNIBUS interface module-An extended-length, hex-height module that
contains the TU58 tape drive and console terminal interface, interrupt
logic, time-of-year clock, and UNIBUS interface.
• Memory controller module-An extended-length, hex-height module
that contains the address logic, translation buffer, execution buffer, cache
memory, and data routing and alignment circuits.
• CPU control store-An extended-length, hex-height module that contains
the control store PROMs. The writable control store (KU750 option)
mounts on this module.
Data Path Functions- The data path logic includes a microsequencer that
provides an address to the control store PROMs for selecting the microinstruction to be performed. It performs the arithmetic and logic functions of
the CPU. In addition to the microsequencer, the data path contains scratchpad memory, rotator logic, and an arithmetic logical (ALU) processor.
The scratchpad memory is composed of sixty-four 32-bit locations that are
used for the general purpose registers (GPRs), the internal processor registers, and temporary storage registers. The scratch pad memory includes
address control logic to enable access to the register information. Data is
written into the scratchpad locations from the W bus.
The rotator logic receives a 64-bit input from and provides a 32-bit output
to an internal DAP bus. The rotator performs field extractions, rotates and
shifts data on the M bus and internal bus, and packs and unpacks floatingpoint data.
The ALU performs arithmetic or logical operations on binary and binarycode-decimal (BCD) 32-bit data.
CPU Control Store Functions- The CPU control store microcode, contained
in ROMs, is used to sequence the CPU operations. The information is stored
in six banks, each containing lK 80-bit locations. One of the six banks is
enabled by the bank select decoder, which receives information from the
DAP logic. The control store RAMs receive information from the CMI bus
and transfer control signals to the DAP, MIC, and UBI modules.

4-10· VAX-1l1750 Processor

UNIBUS Interconnect Functions- The UNIBUS interconnect (UBI) logic
contains the interfaces for the TU58 tape drive and console terminal, the
interrupt control logic, a time-of-year clock, and a UNIBUS interface. Information is transferred to and from the UNIBUS interconnect through the W
bus and CMI bus.

The interface for the console terminal and TU58 tape drive each contain an
asynchronous EIA serial-line that operates under control of the microcode
to transfer information between the console registers and the CPU and
memory. The primary path for the data exchange is through the W bus.
The interrupt logic controls all hardware and software interrupts generated
by the system. The interrupt logic stores sections of the processor status
longword (PSL), including the interrupt priority level, the interrupt stack
flag, and the current mode information. It also contains the asynchronous
system trap (AST) level and returns this information to the system through
the W bus under control of the microcode. The logic controls the UNIBUS
arbitration by encoding the highest priority interrupt that is pending.
The functional elements of the UNIBUS interface include the UNIBUS data
path and control, the address data path, the control store, and the UNIBUS
arbitrator. The interface controls the UNIBUS and CMI bus protocols and
monitors and controls the data transmissions between these buses. The
control store consists of a 256 by 24-bit PROM that executes and directs
the interface operations. A 512 by 19-bit address map RAM is loaded by the
software and allows UNIBUS devices to access noncontiguous pages in
main memory during DMA transfers. The timing and synchronization functions of the interface are provided by the CPU clock signals.
The time-of-year clock is a crystal-controlled, 32-bit binary counter that
provides the correct time to the system for scheduling system operations.
The correct time is initially entered by the operations system service and no
operator intervention is required thereafter. The time is monitored by the
software during timekeeping functions. The clock is equipped with a battery to insure that the correct time is maintained if the power fails.
Memory Interconnect and Control Functions- The memory interconnect
and control (MIC) logic is the interface between the W bus, M bus, and the
CPU interconnect (CM!) bus. The MIC module contains address control
logic, a translation buffer, and cache memory, and performs the routing and
alignment of memory data.

The address control logic contains the program counter and virtual address
registers that store addresses for operand and instruction stream references
and logic for address manipulations.

4-11

The translation buffer is a cache memory that stores 512 frequently used
virtual-to-physical address translations, thereby reducing the time required
by the CPU to perform these translations. The translation buffer is divided
into 256 system-space page translations and 256 process-space page translations. It is two-way associative and parity is assigned on each entry to
increase data integrity. The page table entries for virtual-to-physical
address translations are stored by memory management microroutines.
The translation buffer information is contained in an address field and a
data field. The address field contains virtual address translations and the
data field contains the physical page frame number for each page table
entry.
Cache memory is a high-speed memory that maintains a copy of frequently
selected portions of main memory for faster access to instructions and data.
The cache memory is loaded by memory management and the processor
examines the data in cache before accessing main memory. If the data is
found in cache, the time for access is reduced. The cache is a 4-Kbyte,
direct mapped, write-through memory that receives all memory information, including addresses and instructions. The cache data is longwordaligned with the CMI bus data, and the rotation for the data path alignment
is performed by the memory data routing and alignment logic. The writethrough feature protects the integrity of the memory information by updating the memory contents immediately after the CPU performs a write
operation. For increased integrity, the cache includes byte parity for both
data and addresses.
Main Memory Subsystem
The main memory subsystem consists of from one to eight I-Mbyte memory array modules, the memory array bus, and the memory controller module. The memory modules contain dynamic 64-Kbit array MOS memory
devices connected to the system through an error-correcting controller.
The memory subsystem communicates with the CPU, UNIBUS, and MASSBUS through the internal CMI bus. The features of memory subsystem are
as follows:

Error correcting enhances data availability and reliability by correcting
single-bit errors and detecting double-bit errors within the memory
system.
The subsystem permits write operations to any combination of bytes
within an aligned longword.
Boot ROMs allow bootstrapping from devices, including the integral
TU58 cartridge tape drive.
Optional battery backup maintains power to preserve data in 8 Mbytes of
memory for a minimum 10 minutes.

4-12' VAX-11/750 Processor

• MEMORY CONTROLLER FUNCTIONS
The memory controller (MCT) contains the logic that is the interface
between the main memory and the system. The memory controller module
contains addressing logic, refresh control circuits, and error correcting
code (ECC) logic. The memory subsystem includes diagnostic features that
are controlled by the software.
The ECC logic corrects single-bit memory errors, detects double-bit errors,
and detects errors greater than double-bit errors if there is an even number
of errors. If a single-bit error is detected, the ECC logic corrects the error.
The ECC logic detects multibit errors but no correction is performed. An
uncorrectable error is a word containing an error that maps to an invalid
syndrome. The address and syndrome of an uncorrectable error will overwrite the address and syndrome of a correctable error. Detections and corrections of errors are reported to the CPU, where they can be recorded for
analysis.
The controller contains three longword registers that are accessible in the
VO space. The program monitors these registers to determine the memory
size, record the address of failing memory locations, isolate the error to an
individual memory circuit, and verify the operation of error-correcting
logic. Memory performance is optimized through longword read and write
operations. The memory controller also is designed to allow write operations to any combination of bytes within an aligned longword.
The memory controller can include four 256-Kbyte ROMs that contain the
bootstrapping programs for up to four devices. The CPU reads the data
from the ROMs into main memory and executes the program during the
bootstrap loading operations. Each ROM contains a checksum of the
ROM's contents to allow verification of proper operation and associated
logic. One ROM always contains the bootstrap program for the TU58 tape
cartridge and the remaining ROMs contain programs for other various system devices used to boot the system. The ROMs are selected by the boot
switch on the control panel.
• BASIC MEMORY OPERATIONS
The physical address space contained in the memory controller is divided
into memory addresses and 1/0 addresses. Figure 4-5 shows the combined
areas. The three types of memory cycles used to address this space are read,
longword-write, and byte and word write.

4-13
24-BIT
MIADDRESS

- - - - - - - - r---------..,
000000

MEMORY
SPACE

CONTROLLED BY
1 CONTROLLER
/
/

/
/
/

/
/
/
/

ADDRESS 16

- - - - - - - -1-----------1/

ADDRESS 1i;

I/O
SPACE
-

16
- -ADDRESS
- - - - - '-----------', ,

Figure 4-5 • Memory Controller Physical Address Space

During a read cycle, the device requesting the data transfers address and
control information to the memory controller. The memory controller initiates the memory-cycle timing, transfers the memory data to the ECC logic,
and notifies the device that information is available. If a correctable error is
detected by the ECC logic, the corrected data is sent to the device and an
interrupt is generated to notify the system that an error has occurred. If an
uncorrectable error is detected, the unmodified data is sent to the device
together with an error message. When the read reference is from an IIO
adapter, the adapter records the error message. When it is from the CPU,
the CPU will generate a machine check abort.
During a longword write cycle, the device requesting the longword write
operation transfers address and control information to the memory controller. The memory controller initiates the memory-cycle timing, generates
seven check bits, and transfers the bits and the 32-bit longword to
memory.

4-14· VAX-1l1750 Processor

During a byte- and word-write cycle, the device requesting the write operation transfers the address and control information to the memory controller and the controller initiates the memory-cycle timing. The memory
controller forms the new 32-bit data word and transfers the longword and
check bits into memory. If a correctable error is detected by the ECC logic,
the error will be corrected. If the error is in a byte or word that is being
written, the error will be ignored. When an uncorrectable error is detected
by the ECC during the read portion of the cycle, the originallongword will
be rewritten into memory without any changes. The error will be reported
during a subsequent read operation to this location .
• MEMORY CONTROL AND STATUS REGISTERS
Three control and status registers provide information for recording correctable and un correctable errors, for aiding the verification and diagnostics of the error checking hardware, and for indicating memory size and
configuration. The registers are CSR 0, CSR 1, and CSR 2.
Memory ControllStatus Register O-Memory control/status register 0 (CSR
0) is a read-only register that contains information to allow the recording of
both correctable and un correctable errors. The CSR 0 register format is
shown in figure 4-6.

31 30 29 28

16 15

24 23
I

NCr!

I I

ERR SYND

USED

Figure 4-6 • Memory ControllStatus Register 0 Format

4-15

Bit

Function

UNCORR ERR FLAG (Uncorrectable error flag) - Set to indicate that

an uncorrectable error has been detected and can be cleared only
when UNCORR ERR LOST (bit 30) is cleared or if both bits are
cleared during the same write operation.
30

UNCORR ERR LOST (Uncorrectable error lost) - Set to indicate that
an uncorrectable error has occurred with the UNCORR ERR FLAG
bit 31 previously set. The second uncorrectable error-page address
will not overwrite the first uncorrectable error-page address. It is
cleared by writing a one to this bit.

CORR ERR FLAG (Correctable error flag) - Set when a correctable
single-bit error occurs during a read operation. A single-bit error
that occurs during the read portion of a byte-write cycle will have no
effect on the flag. Cleared by writing a one to this bit.

28:24

Not used.

23:9

ERR ADDR (Error address)-A hexadecimal address that identifies

the page on which an error occurred during a memory read cycle.
The page address corresponds to the first error that occurs, except
that the page address of an uncorrectable error will overwrite the
page address of a correctable error. The page address of an uncorrectable error is not overwritten by a more recent uncorrectable
error.
8:7

Not used.

6:0

ERR SYND (Error syndrome) - Read-only bits that indicate the error

syndrome of the detected error.

Memory ControllStatus Register 1- Memory controVaddress register 1
(CSR 1) is a read-write register that aids in the verification and diagnosis of
the error correcting hardware. The format of CSR 1 following a powerup
sequence is shown in figure 4-7.

LJ IIII I.,
31 30 29 28 27 26 25 24 23

~~1 ~~UUL

16 15

"I",

8 7 6

I",

NOT USED PAGU.TOI)E AI)I)R

, I , !

NOT
USED

CHK BITS

ECC DISBL MODE
DIAG CHK MODE
PAGE MODE
ENB REPT CORR ERR

Figure 4-7 • Memory ControllStatus Register Format

4-16" VAX-11/750 Processor

Bit

Function

31:29

Not used.

ENB REPT CaRR ERR (Enable reporting correctable errors) - Set to
enable the reporting of correctable single-bit errors and cleared to
inhibit the reporting of single-bit errors. The errors will be corrected
in either state.

PAGE MODE (Page model-Set to allow the ECC disable mode or
the diagnostic-check mode to operate on a 512-byte page whose
address is contained in CSR 1 (bits 23:9). The diagnostic-check
mode operates in the page mode. The ECC disable mode can operate on a page or on the entire memory, depending on whether page
mode is selected.

DIAG CHK MODE (Diagnostic check mode) - When set, the check
bits 6:0 are substituted for the check bits that come from memory
during a read operation. The correct check bits are transferred to
memory during a write cycle. The diagnostic check mode is confined
to a single page whose address is stored in the page mode address,
bits 23:9. While operating in the diagnostic check mode, read errors
that occur in other pages of memory will not be logged into CSR o.
The ECC disable mode and diagnostic check mode cannot be
selected at the same time.

ECC DSBL MODE (ECC disable mode) - Set to disable the following:
the detection of un correctable errors, the detection and correction
of single-bit errors, the error logging in CSR 0, and the reporting ~f
errors on the status lines. During a read operation, the generated
check bits that are written into memory are also stored in CSR o. The
ECC can be disabled for a 512-byte page or for the entire memory,
depending on whether the page-mode bit 27 is selected. The ECC
disable mode and diagnostic-check mode cannot be selected at the
same time.

Not used.

23:9

PAGE MODE ADDR (Page mode address)-In the page mode, this
field contains the address of the 512-byte page to which the diagnostic check mode or the ECC disable mode will be applicable.

8:7

Not used.

6:00

CHK BITS (Check bits)-In the diagnostic check mode, these bits
are substituted for the check bits from the memory during a read
operation. In ECC disable mode, these seven check bits are read
from memory.

4-17

Memory ControllStatus Register 2- Memory control/status register 2 (CSR
2) is a read-only register that provides memory size and configuration
information. The format of the register information is shown in figure 4-8.

24 23

, , I

17 16 15

I",I"JI
II

STAid ADDR

MEMPRESMAP

BATT BACK FAIL

Figure 4-8 • Memory ControllStatus Register 2 Format

Bit

Function

31 :24

Not used.

23: 17

START ADDR (Starting address) - The starting address for the mem0ry selected by jumper leads on the module.

BATT .BACK FAIL (Battery backup failure) - Set on a powerup

sequence if the memory battery backup unit voltage is not within the
required value. Cleared by a longword write to any location in
memory.
15:0

MEM PRES MAP (Memory present map)- These bits indicate the

amount of memory available and their locations in the memory in
the backplane. The map is divided into eight pairs of two bits .
• PROCESSOR OPTIONS
Several processor options can be added to improve the processor performance and extend the 1/0 capabilities.
The MS750 memory modules contain 1 Mbyte of ECC MOS memory and
can be installed to increase the main memory to a total of 8 Mbytes.
The H7112 memory battery backup unit can be installed in the CPU cabinet to protect the contents of the MOS memory during power failures for a
minimum of 10 minutes.
The KU750 writable control store (WCS) is an extended-range G and H
data type option supported in KU750 loadable microcode. The module
contains 1 K by 80-bit storage and attaches to the resident control store
(CCS) module. It enables microroutines to be generated for user
applications.
The remote diagnostic option is an extended-length, hex-height module
that installs in the CPU backplane and allows diagnostic programs to be
performed under control of Digital's Remote Diagnostic Service centers.

4-18· VAX-1l1750 Processor

The FP750 floating-point accelerator option operates in conjunction with
the VAX-1l1750 processor to execute standard floating-point instructions.
Floating-point representation permits a greater range of number values
than is possible with a 32-bit integer. The FP750 is a hex-height module
and is easily installed in the CPU backplane. It is functionally transparent to
the user and hardware and software modifications are not required. The
FP750 receives an opcode from the CPU and decodes the information into
a starting microaddress. The outputs of the control store ROM control the
arithmetic operations and data path logic. The FP750 executes addition,
subtraction, multiplication, and division instructions, which operate on
single-precision (32-bit) and double-precision (64-bit) data. It executes
extended multiply (EMOD) and polynomial evaluation (POLY) instructions, and converts the data between integer and floating-point formats and
between single- and double-precision floating-point formats. The FP750
also executes integer multiplication instruction. The floating-point instructions performed by the FP750 are listed in table 4-1.

Table 4-1 • FPA Floating, Double, and Integer Instructions
Opcode
(Hexadecimal)

Mnenomic

Opcode
(Hexadecimal)

Mnemonic

40
41
42
43
44
45
46
47
48
4A
4B
4C
4D
4E
51
54
55
56
84
85
60
61

ADDF2
ADDF3
SUBF2
SUBF3
MULF2
MULF3
DIVD2
DIVF3
CVTFB
CVTFL
CVTRFL
CVTBF
CVTWF
CVTLF
CMPF
EMODF
POLYF
CVTFD
MULB2
MULB3
ADDD2
ADDD3

62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
71
74
76
7A

SUBD2
SUBD3
MULD2
-MULD3
DIVD2
DIVD3
CVTDB
CVTDW
CVTDL
CVTRDL
CVTBD
CVTWD
CVTLD
CMPD
EMODD
CVTDP
EMUL
MULW3
MULW3
MULL2
MULL3

A4
A5
C4
C5

The VAX-1l1780 and VAX-1l1785 processors are high-end members of the
VAX processor family. The VAX-1l1780, the original high-performance
VAX member, has become an industry standard. The VAX-1l1785 processor includes the same features as the VAX-1l1780 but performance has
been increased. Both the VAX-1l1780 and the VAX-1l1785 are microprogrammed, 32-bit processors that operate with the VMS operating system or
with ULTRIX-32 operating system software. The VMS system provides a
reliable, high-performance multiuser environment for time-sharing functions, for batch processing, and for realtime applications. The ULTRIX-32
system, a virtual-memory operating system with complete UNIX functionality, includes demand paging and enhanced performance for applications
that require large memory storage. Figure 5-1 shows the VAX-1l1780 processor unit. The VAX-11/780 and VAX-1l1785 processor cabinets are physically similar except for the name plate designations.
The central processing unit (CPU) performs the logic and arithmetic operations and controls the transfer of information to devices. It executes a large
set of variable-length instructions in native mode, and nonprivileged PDP11 instructions in compatibility mode. The 32-bit addressing and data
capability of the processors permits direct access to four billion bytes of
virtual address space, The processor's memory management hardware
translates a virtual address to a physiCal address under operating system
control. The processor offers a variety of addressing modes that use the
general purpose registers to identify instruction operand locations, including an indexed addressing mode that provides true post-indexing
capability.
The processor's instruction set includes integral decimal, character string,
and floating-point instructions, as well as integer, logical, and bit field
instructions. Floating-point instruction execution can be enhanced by an
optional floating-point accelerator.

5-2. VAX-1l1780 and VAX-1l1785 Processors

Figure 5-1 • VAX-1l1780 Processor Unit

5-3

. VAX-1l/7S0 Processor System
The VAX-ll/780 processor is the lowest priced VAX processor that allows
the full implementation of I/O subsystems and devices available for the
VAX processor family. It offers the reliability and performance that has been
established and proven over many years in a variety of applications. The
continued developments in VO interfaces and devices, mass storage facilities, VAXcluster configurations, and networking applications have enhanced
the VAX-ll/780 system performance.
The VAX-ll/780 processor includes virtual memory management, bootstrap loader, standard instructions for packed decimal, floating- and fixedpoint arithmetic functions, and character and string manipulations. It also
contains 8 Kbytes of bipolar cache memory with parity, a high-precision
programmable realtime clock, a time-of-year clock with battery backup,
and 2 Kwords (99-bit words) of writable-control-store memory. The CPU
contains a console subsystem that includes the RXOI floppy-disk drive and
an L5I-11 microcomputer to control the console subsystem operation.
Some of the processor features are:
• 8-Kbyte, two-way associative cache memory improves main memory
l:\ccess time to increase overall system performance.
• Compatibility mode allows the programs developed for the PDP-ll to
operate with the VAX processors.
• 2 Kwords of writable-control store increases throughput by allowing the
user to create routines in microcode tailored for specific applications.
• Optional high-performance floating-point accelerator decreases instruction execution time of floating-point arithmetic and some integer arithmetic operations.
• CPU memory can expand up to 32 Mbytes.
• Up to 8 Mbytes of multiport shared memory is available .

. VAX-1lI7S5 Processor
The VAX-ll/785 is an increased-performance processor that operates more
than 50 percent faster than the VAX,11/780 while using the same power
and packaging. The VAX-ll/785 supports the same VO bus structures as
the VAX-ll/780, thereby allowing the standard VAX interfaces and devices
to operate with the system. Because of its increased speed, most of. the
performance improvement is in CPU processing operations; however, the
performance of VO-intensive applications is also improved because of
faster interrupt response time.

5-4· VAX-llll80and VAX-llll85 Processors

The VAX-ll/785 processor uses advanced Schottky technology to decrease
the logic switching time and includes a cycle time that is 50 percent faster
than the VAX-ll/780 cpu. The accelerated cycle time results in higher
data throughput and faster response time, and provides the ability to support additional users.
The cache memory of the VAX-ll/785 processor has been increased to 32
Kbytes from the 8 Kbytes included with the VAX-ll/780 processor. This
allows the cache to store more data, thereby increasing the probability that
the data required by the processor will be found in cache memory.
The microcode of the VAX-ll/785 processor is stored in RAMs, which
increases the performance of the cpu and allows revisions to be easily
incorporated.
The console memory in the VAX-ll/785 processor provides 48 Kbytes of
storage, compared to the 16 Kbytes of memory included with the VAX-ll/
780. The increased memory size improves the console subsystem performance and allows the RAM-based microcode to be easily implemented.
The VAX-ll/785 processor includes virtual memory management, bootstrap loader, standard instructions for packed decimal, floating-point (G
and H data types) and fixed-point arithmetic functions, and character and
string manipulations. It also contains 32-Kbyte, two-way set-associative
cache memory with parity,. a high-precision programmable realtime clock,
a time-of-year clock with battery backup, and 8 Kwords (99-bit words) of
writable-control-store memory. The cpu contains a console subsystem that
includes the RXOI floppy-disk drive and an LSI-ll microcomputer to control the console subsystem operation. Some of the processor features are
• 32-Kbyte cache memory improves main memory access time to increase
overall system performance.
• Compatibility mode allows the programs developed for PDP-ll to operate with the VAX processors.
• 8 Kbytes of writable-control store increases throughput by allowing the
user to create routines in microcode for specific applications.
• Optional high-performance floating-point accelerator decreases instruction execution time of floating-point arithmetic and some integer arithmetic operations.

• cpu memory can expand up to 32 Mbytes.
• Up to 8 Mbytes of multiport shared memory is available.

5-5

. VAX·111780 and VAX·11/785 System Configuration
The standard components included with the VAX-111780 and VAX-1l1785
processors are
• CPU cabinet and power supplies

• 2 Mbytes of ECC MOS memory
• RXOI floppy disk console subsystem
• PDP-Il103 console microprocessor
• H9652 UNIBUS expansion cabinet
• VAXIVMS license and warranty or ULTRIX-32 user license for up to 32

users
The VAX-111780 and VAX-111785 processors are contained in a cabinet
153.0 centimeters (60.25 inches) high and 181.1 centimeters (46.5 inches)
wide. The cabinet, shown in figure 5-2, is on casters. Double doors on the
ftont and rear of the cabinet allow easy access to the processor components. The right side of the unit contains the memory controller and memory modules, two option panel spaces for mounting adapters, the memory
power supply, and the RX01 floppy disk subsystem. The CPU modules are
mounted in the backplane located on the left side of the unit, which also
contains space for mounting three system unit (SU) backplanes. The left
side contains the console interface, backplane and modules for the DW780
UNIBUS adapter, and reserved space for the FP780 (VAX-1l/780) or FP785
(VAX-111785) floating-point accelerator. Two power supplies are included
for the CPU and space is available for mounting the power supply provided
with the optional floating-point accelerator. Blower units located in both
sides of the cabinet provide cooling for the logic and power supplies.

5-6· VAX-1l1780 and VAX-1l1785 Processors

~Il i i i\i i i i i i il il il i: : :l i
153cm

(60.2 in.)

!IIIIIIIIIIIII
111111111111111

1111111
1111111

>-'
0.
W

u
11:
II:

I-

;;::;
W

...J

(J)

....
::::J

(!J

z
~

II:
W

(J)

LtS'

II:

ILl:.
0

-0:

::::J

~
0

II:

W
II:

....

(J)

SPACE FOR
FLOAT PT.
POWER
SUPPLY

POWER
SUPPLY
FOR CPU

GO
....

::::J
!Xl
0
GO

II:

(J)

CPU

IL
0

II:

w
(J)
w

U
~

II:~
00.

2MB
MEMORY AND
CONTROLLER

Ii:
-0:

EXPANSION SPACE
FOR ADDITIONAL
14MB

iii

it
X
w

POWER
SUPPLY
FOR CPU

COOLING

MEMORY BATTERY BACKUP
TIME-OF-YEAR CLOCK BATTERY

RXOl
FLOPPY DISK SUBSYSTEM

11/03 MICROCOMPUTER CONSOLE

CABINET FRONT VIEW

Figure 5-2· VAX-111780 and VAX-1l1785 Processor Configuration

5-7

UNIBUS and CPU Expansion Cabinets
The H9652-M UNIBUS expansion cabinet allows the UNIBUS to be
extended from the CPU cabinet. The cabinet, shown in figure 5-3, is 153.0
centimeters (60.25 inches) high and 69.21 centimeters (27.25 inches) wide
and contains castors and leveling feet. The H9652-M cabinet is included
with the VAX-l 11780 and VAX-111785 system. It contains a BAll-K expansion box and space for mounting a second BAll-K box. The BAll-K box
that is included contains a DDll-DK UNIBUS backplane for UNIBUS interface and controllers. Two disk drive units, each with vertical height of
26.67 centimeters (10.5 inches), can be installed in the cabinet if the second
BAll-K unit is not included. The DDll-DK backplane provides space for
mounting seven hex-height modules and two quad-height modules. The
connector panels at the rear of the cabinet can be removed when device
connectors are installed.

!.!.!.!!.
1/0

Connection
Panel

-.
BAl1-K
UNIBUS
Expansion Box

1/0
153 em
(602 in} Connection

Panel

-. V
Space For

BAll-K

1/0

Connection
Panel

r•

69.2cm
(2725 in}

REAR VIEW

--....

Figure 5-3 • UNIBUS Expansion Cabinet Configuration (H9652-M)

5-8· VAX-1l1780 and VAX-1l1785 Processors
The H9652-H CPU expansion cabinet is used to extend the synchronous
backplane interconnect (SBI) bus from the CPU cabinet. The cabinet,
shown in figure 5-4, is 153.0 centimeters (60.25 inches) high and 69.21
centimeters (27.25 inches) wide and contains castors and leveling feet. The
H9652-H cabinet provides space for four SBI options panels. The options
that can be installed are memory modules, DW780 UNIBUS adapter modules, DR780 DDI adapter modules, RH780 MASSBUS adapter modules, and
CI780 Computer Interconnect adapter modules. The cabinet includes a
power supply and provides space for two additional power supplies, for the
H7112 memory battery backup unit, and for a power control panel.

<.)

'"
...J
W

153cm
(60.2 in.)

<.)

'"
...J
W

<.)

'"
...J
W

t
0

..J

~
0

COOLING

FRONT VIEW

69.2cm
127.25 in.)

Figure 5-4 • CPU Expansion Cabinet Configuration (H9652-H)

VAX-ll/780 and VAX-ll/785 Processor Organization
The VAX-ll/780 and VAX-ll/785 processors each consist of 22 hex-height
modules that perform the arithmetic and logical operations of the CPU and
control the transfer of information to the system devices. The floatingpoint accelerator option is contained on five additional hex-height modules. The optional control store logic is contained on a single hex-height
module. Figure 5-5 shows the processor components and the interconnecting bus structure.

CONTROL
STORE AND
MICROSEQUENCER

TRAPS AND
INTERRUPT
ARBITRATION

CPU
CLOCK

Figure 5-5 • VAX-l1!780 and VAX-l1!785 Processor Components

"'"

5-10' VAX-1l1780 and VAX-1l1785 Processors

• CONSOLE SUBSYSTEM
The console subsystem controls the communication between the CPU and
the console terminal, RXOI disk drive, control panel, and remote diagnostic
port. The console subsystem, shown in figure 5-6, consists of an LSI-ll
microprocessor and RAM memory, a console/CPU interface, a DLVll-E
console terminal interface, an RXOI floppy disk drive and RXVll drive
interface. An optional DLVll-E forms the diagnostic port interface. The
console subsystem monitors and controls the switches and indicators of
the control panel.
The LSI-ll microprocessor and memory control the console subsystem
operation. Communication between the LSI-ll microprocessor and subsystem components is through 16 lines that share both address information
and data and 14 control signal lines of the Q-bus.
The RXOI floppy disk drive is an inexpensive and reliable device that stores
microdiagnostics and system software initiated both locally and remotely. It
simplifies system bootstrapping and initialization, and improves software
update distribution. The unattended restart feature of the CPU enables the
system to restart or reboot itself from the RXOI after a recovery from a
power failure or system halt condition.
The main communication path between the console subsystem components and the CPU is through the console/CPU interface module. The interface contaips a 4K by 16-bit ROM that contains the core of the LSI-ll
console operating system, including the power up routines and the terminal
and fl~ppy disk drivers. The console interface module communicates with
the CPU through the internal data (ID) bus and through the diagnostic (V)
bus. The console interface provides the clock control signals to the processor clock module to synchronize the processor operations and serves as a
time base for processing functions. The LSI-ll begins executing instructions in the ROM when power is applied to the system. It contains the
interfaces f{)r the console subsystem bus structures, including the registers
accessible to each bus, the hardware necessary to implement the console
functions, and a 4K by 16-bit ROM, which provides the core of the console
LSI-ll software.
The DLVll-E is an EIA communications interface that allows industrycompatible communications.
Switches and indicators on the control panel monitor and select the system
operations through the console subsystem.

CONTROL
PANEL

RAM MEMORY *

lSI-ll
MICROPROCESSOR

/".

"I'"

...

QBUS

D
DlVll
CONSOLE
INTERFACE

.
~

RXVll
FLOPPY DISK
INTERFACE

.. "';0.

'8 KBYTES (VAX-ll/780)
40 KBYTES (VAX-ll/785)
colOlE
TERMINAL

,!:O-

CONSOLE/CPU
INTERFACE

• 4KX16BITROM
MEMORY

VBUS

IDBUS
CLOCK

... ..... ~
DlVll
REMOTE
DIAGNOSTIC
INTERFACE

REMOTE SERVICE
LINE

RXOIFlOPPY
DISK DRIVE

Fzi,ure 5-6 • Console Subsystem Components

5-12· VAX-IIll80 and VAX-IIll85 Processors

• INTERNAL BUS STRUCTURE
The internal data bus (ID) is a high-speed data path that connects the
console subsystem to the major functional areas of the central processor. It
transfers data between the instruction buffer data paths, floating-point
accelerator, and console subsystem. The ID bus is controlled by the console
interface logic during maintenance operations and- allows access to
writable-control-store information and information in internal registers.
The ID bus consists of 32 data lines, six address lines, and one write control
line. The address lines specify the internal register that has been selected
as the source or destination of the data. The write control line indicates
whether the internal register is to receive or transmit the data.
The visibility (V) bus is used to isolate CPU failures during diagnostic
maintenance. The V bus consists of eight serial-data lines, a load signal line,
a clock signal line, and a self-test line. Each of the CPU modules that connect to the V bus contains one or more V bus shift registers. The data input
lines to the shift registers monitor test points on the modules. The test
point information is loaded in parallel into the shift register and the clock
signal transfers the data serially onto the V bus and into a console register,
where it can b~ monitored by the console software.
The physical address (PA) bus is a 28-bit bidirectional bus that transfers the
translated physical address from the translation buffer to the cache memory and the SBI controller.
The synchronous backplane interconnect bus is a bidirectional information path that supports the communication protocol for the data exchanges
between the CPU, memory controller, and 1/0 adapters. The SBI bus provides parallel information exchanges that are checked and synchronized
with the system clock.
The control store (CS) bus provides the path for the transfer of each microword field to the CPU logic areas. The CS bus consists of 96 data bits and
three parity bits, one for each 32-bit data segment. The microword is
grouped into fields, each of which provides control of an area of the
processor.
The memory data (MD) bus is a bidirectional path for longword-aligned
data exchanges. The MD bus connects the data path of the CPU and the
instruction buffer to the cache and SBI controller. The bus consists of 32
data lines, four parity lines, and four mask lines. The parity lines provide
the parity for each of the four data bytes. The mask bits are also associated
with each of the four bytes and indicate which bytes are to be read or
written.

5-13

• PROCESSOR LOGIC ELEMENTS
The VAX-11/780 and VAX-l 11785 processors consist of the following logic
elements:
• A control store that contains the VAX-11 instruction set, writable control
store, and optional user control store information.
• A microsequencer that generates the microword address.
• A data path that provides the arithmetic and logic functions of the
processor.
• An address translation buffer that contains frequently used virtual-tophysical address translations.
• A primary cache memory for the data transferred from memory.

• An instruction buffer that decodes and stores instructions for evaluation
by the processor.
• A processor clock that provides the system timing functions.
• An interrupt control that evaluates interrupts and exceptions.

Control Store Functions-The basic microprogram of the VAX-11/780 is
contained in a 4K by 99-bit PROM control store (PCS). The system also
includes a 2K by 99-bit writable diagnostic control store (WDCS) that contains diagnostic microprogram routines and updates to the basic microprogram. In the VAX-ll/785 the microcode is stored in eight 256K by 99-bit
ROMs, allowing the microcode to be easily modified and increasing the
performance of the CPU. The microcode controls the operation and
sequencing of the processor and includes the native mode, PDP-11 compatibility mode, and floating-point instruction sets. A microword consists of
96 data bits and 3 parity bits, one for each 32-bit segment. It is addressed
by the micro sequencer or the instruction decode logic. The control store
also contains a 96-bit buffer that enables it to execute one microword while
simultaneously fetching the next. Parity is checked on each microword
read from the PCS or WDCS, and one parity bit corresponds to each 32-bit
section.
Microsequencer Functions - The micro sequencer contains the logic
required to generate the microword address. The microsequencer monitors
the console operations and processor conditions, selects the proper address
for the control store word, and transfers the address to the PCS or WDCS.
The microsequencer controls the entry into the microprogram during normal program flow and during the powerup and powerdown sequence, console operations, microtraps, changes in the microcode, and program stalls.

5-14' VAX-1l1780 and VAX-1l1785 Processors

Data Path Functions- The data path logic contains four functional sections:

address, arithmetic, data, and exponent. Each section operates independently and is capable of processing data and addresses in parallel with
operations being performed in other sections. The data path operations are
defined by the 96-bit words of the microprogram. The execution of each
microinstruction causes a sequence of operations to be performed in the
data path logic.
The arithmetic section performs arithmetic and logic operations, bit mask
and constant generation, and data shifting operations. It also provides the
temporary storage for data and addresses. The data and address information is transferred between other sections of the data paths through the
arithmetic logic unit (ALU) of the arithmetic section.
The address section contains the virtual address (VA) register, instruction
buffer address register (VIBA), and the program counter (PC). The VA register stores the virtual address that is to be translated into· a physical
address of a memory location. The VIBA stores the address of the instruction stream data that will be loaded into the instruction buffer. The PC
stores the address of the instruction opcode each time a new instruction
sequence is started.
The data-shift-and-rotate section packs, unpacks floating-point and decimal string data, and shifts and byte aligns the operand data. The data section contains two .32-bit registers that are used as temporary storage of
operand data. It is an interface for the transfer of data to and from memory
through the memory data bus and between the internal registers through
theID bus.
The exponent and sign section processes the exponent value of the
floating-point numbers while the processing of the fractions is performed
in the arithmetic and data sections.
Address Translation Bu/fer- The address translation buffer is a cache of

physical address translations. It significantly reduces the amount of time
required by the CPU to perform the repetitive tasks of dynamic address
translation. In the VAX-ll/780 processor, the cache contains 128 virtual-tophysical page address translations, which are divided into equal sections:
64 system-space page translations and 64 process-space page translations.
In the VAX-U/785 processor, the cache contains 512 virtual-to-physical
address translations, which are divided into 256 system-space translations
and 256 process-space translations. Each of these sections is two-way associative. Byte parity is assigned on each entry to increase the integrity of the
data.

5-15

Instruction Buffer and Decode Functions- The instruction buffer improves
the system performance by prefetching data in the instruction stream. Data
from memory is continually loaded into the 8-byte instruction buffer to
eliminate the CPU time required to perform two memory cycles when the
bytes of the instruction stream cross 32-bit longword boundaries. The
-instruction buffer also processes operand specifiers before execution and
then routes them to the CPU. The opcode of the instruction is stored in the
first byte and the remainder of the operand specifier and extensions are
stored in the remaining bytes. The instruction decode logic evaluates the
instruction stream data stored in the first two bytes of the instruction register and generates the lower 8-bits of each successive micro address.
Interrupt and Exception Functions - Interrupts and exceptions cause tpe
processor to transfer control from the executing program to a routine that
can service the interrupt or exception. The interrupt and exception logic is
contained on the interrupt control module that receives input information
from the CS bus and transfers information through the ID bus. A priority of
service is assigned to both interrupts and exceptions and the priority is
decoded by the interrupt control module. The priority encoder logic, contained on the interrupt control, selects the highest interrupt level requested
and generates an interrupt-Ievel-active code. This code generates an interrupt vector, which is the address in memory used to select the interrupt or
exception service routine.
Interrupts are the notification of events that are independent of the current
instruction execution and are normally assigned a priority level higher than
exception. Interrupt requests can be received from devices, controllers, and
the processor.
Exceptions are usually assigned the lowest priority, occur during the execution of an instruction, and are serviced in the context of the process that
produced the exception. Exceptions caused by conditions that could result
in a system failure, however, are assigned the highest priority.

Cache Memory Functions - The cache memory is the primary cache system
for all data coming from main memory, including addresses, address translations, and instructions. The cache is two-way set associative and contains
8 Kbytes in the VAX-ll/780 processor and 32 Kbytes in the VAX-111785
processor. The memory cache reduces the average time the processor waits
to receive memory data by reading eight bytes at a time from main memory,
and transferring four bytes to the CPU data paths or instruction buffer.
Since the remaining four bytes are already available, the memory cache also
provides prefetching. The cache memory system carries byte parity for
both data and addresses to increase data integrity. Cache locations are allocated when data is read from memory. When both locations of the cache
are filled with data, the data in one location is replaced.

5-16· VAX-1l1780 and VAX-1l1785 Processors

Processor Clock Functions-The processor contains a programmable
realtime clock and a time-of-year clock. The interval or realtime clock is
used by the software to measure small time intervals that are identified
by interrupts. It contains a crystal-controlled oscillator with an accuracy
of 0.01 percent, and a resolution of one microsecond. The time-of-year clock
is used by the software to perform timekeeping functions such as providing
the correct time to the system after power failure or system interruption.
It provides the powerfail sequencing, generates the SBI timing signals,
and distributes and decodes the SBI signals to the processor logic.

• PROCESSOR OPTIONS
The FP780 (VAX-llI780) and FP785 (VAX-llI785) are floating-point
accelerator options that operate with the processor to execute addition,
subtraction, multiplication, and division instructions. The floating-point
accelerators operate on· single- and double-precision floating-point operands, including the special EMOD and POLY instructions in both singleand double-precision formats. The floating-point accelerator also enhances
the performance of 32-bit integer multiply instructions.
The KU780 user writable-control-store option is available with the VAX111780 processor. It provides control store space for the KE780 extendedrange floating-point option and for the QE109-CY microprogramming
tools option. The KU780 is a hex-height module that contains 2K by 99-bit
word locations. Each word consists of 96-bits plus three parity bits. If the
KE780 is not included, these locations are available for user microcode.
The KE780 option provides G and H floating-point microcode. It is used
for applications that require extended decimal digit precision. The optional
G-floating (double precision) and H-floating (quadruple precision) data
points provide up to 33-decimal digit accuracy. The KE780 option attaches
to the KU780 module .

• MAIN MEMORY SUBSYSTEM
The main memory subsystem of the VAX-111780 and VAX-111785 processors consists of dynamic MOS (metal oxide semiconductor) RAM modules,
a memory array bus, and memory controller modules. The memory subsystem contains a 20-s10t backplane and connects to the SBI bus through an
SBI interface. Two types of memory subsystems are available. The MS780-E
subsystem contains 64K by I-bit MOS RAM technology and the MS 780-H
subsystem contains 256K by I-bit MOS RAM technology. The MS780-E
subsystem enables up to 16 Mbytes of memory to be installed in a single
backplane using 1-Mbyte array modules and two controllers. A second
backplane can be installed in the H9652-H CPU cabinet to increas·e the
total memory capacity to 32 Mbytes. The MS780-H memory subsystem
allows up to 64 Mbytes of memory to be installed in a single backplane
using 4-Mbyte array modules and two controllers.

5-17

The memory subsystem supports data transfers up to 13.3 Mbytes per
second and contains error correction control (ECC) logic. Eight ECC check
bits are stored with each 64-bit quadword and are accessed with the data to
determine its integrity. The memory is capable of random-access read and
write operations to a single 32-bit longword or extended 64-bit quadword.
It also is capable of random-access write operations to an arbitrary byte,
to series of contiguous bytes, and to a series of noncontiguous bytes. The
memory array modules are organized to optimize 8-byte read or write
access. The features of the memory subsystem are as follows:
Memory configurations are expandable.
ECC logic enhances data availability and reliability by correcting single-

bit errors and detecting double-bit errors within the memory system.
Subsystem permits write operations to any combination of bytes within
an aligned longword.
Interleaving with two
throughput on the bus.

controllers

improves

memory

subsystem

Optional battery backup unit preserves data in memory during a power
failure.

Memory Interleaving- The memory subsystem is capable of operating with
two memory controllers in the interleaving mode or two-way interleaved
mode, improving the memory subsystem throughput on the bus.

In a single-memory controller system, the starting address is assigned by
the ROM bootstrap. The size of the memory is encoded from the number of
memory array modules installed in the backplane. When two memory controllers are used and each contains an equal amount of memory, the memory access time can be decreased by interleaving. Most memory operations
are performed on consecutive memory locations. When one controller is
accessing data, the other controller is available to decode an address for the
next operation. The two memory controllers access alternate quadwords.
With an interleaved memory system, both controllers operate with the
same array size and starting address.

In the two-way interleaved mode, four controllers can be used. The second
interleaved memory system would have a starting address that is one location greater than the address of the first interleaved set.

5-18· VAX-1l1780 and VAX-1l1785 Processors

Memory Controller Functions-The memory controller forms the nexus
from rriain memory to the SBI and buffers commands, addresses, and data
to improve memory throughput. The controller examines the command
and address lines of the SBI for each SBI cycle. To initiate and complete a
memory-write-masked, interlock-write-masked, or extended-write-masked
transaction, the controller must recognize a command/address and data in
two or three SBI cycles. To perform a read-masked, extended-read, or
interlock-read-masked operation, the controller must recognize only an
appropriate command/address. The controller provides the necessary timing and control to complete all memory transactions. It informs a commander of a successful write operation, and contends and arbitrates for SBI
bus control to transmit information during a read-masked, extended-read,
or interlock-read operation. Before the controller initiates a memory cycle
operation, it checks for bus transmission parity errors and other fault conditions and reports any of these conditions to the commander, conforming
to the SBI protocol.

The memory controller provides powerup initialization logic and refresh
control logic for the dynamic MOS memory devices. The dynamic MOS
memory cell is a capacitor in which the stored charge represents a data bit.
Because the stored charge tends to diminish, each cell requires a refresh
cycle every 2 microseconds to retain the charge.
Data transfers to and from main memory are protected by ECC logic, which
performs single-bit error detection and correction and double-bit error
detection logic to improve system reliability. This is accomplished by
storing eight check bits with the 64 data bits in each memory location.
Each check bit is generated by checking the parity of selected groups of
data bits in a quadword. When parity is checked during a read, an incorrect
bit will be detected by the parity checking logic and will develop a unique
8-bit syndrome that will identify the bit in error. Error correction logic may
correct the bit in error. There are 72 unique syndromes related to individual bits in the coded quadword.
Error reporting provides an early warning to protect the system from
performance degradation. The system error logging feature requires that
single-bit errors and uncorrectable errors be tagged and stored in the memory controller during memory read transmission from the memory· subsystem. The memory controller also stores syndrome bits for the first
memory-read error and error addresses for error logging and servicing. The
memory controller retains this information until the first error is serviced.
Ten bits in register B are used for ECC diagnostics only.

5-19

When a two-controller interleaved memory configuration is used, the
memory controllers must have consecutive SBI bus arbitration lines (TR).
The interleave bit of the memory configuration register A will be cleared
during powerup and must be set in each controller. Each controller must
have the same array size and be issued the same starting address.
When two, two-way interleaved memory systems having four controllers
are used, the second interleaved memory system is assigned a starting
address that is one location above the final address of the first. The proper
starting address will be written into the memory configuration register B
from the SBI bus.
A 4-Kbyte programmable read-only memory (ROM) used to bootstrap the
operating system is on the memory controller. The ROM is assigned a 4Kbyte I/O address space and can be addressed through the SBI interface
during system initialization. The address, timing, and control logic to read
.the information from the ROM for booting the system also is contained in
the subsystem .
• BASIC MEMORY OPERATIONS
The memory subsystem operates synchronously with the SBI clock cycles .
. The physical address space of the SBI is divided into two equal areas. memory address space and 1/0 address space. Figure 5-7 shows the SBI
physical address space assignments.
The 28-bit SBI longword address field allows access to up to 512 Mbytes of
main memory. The hardware supports a maximum of 64 Mbytes of main
memory. Physical memory operations are performed when bit 27 of the SBI
addresses is zero; 1/0 operations occur when bit 27 is one. The operation
field identifies one of the six transactions to be performed by the memory
subsystem: read masked, extended read, interlock read masked, write
masked, extended write masked, and interlock write masked.
A write masked operation transfers from 1 to 4 bytes of data to memory
and a read masked operation transfers 4 bytes of data from memory. An
extended read is executed to transfer 8 bytes of data (2 longwords) from
memory to a requesting nexus. An extended-write-masked operation provides a byte-selectable transfer of up to 8 bytes to memory. Interlock-readmasked and interlock-write-masked operations perform a function similar
to that of read masked and write masked operations but they also provide
process synchronization.

5~20' VAX~11/780and VAX~11/785 Processors

1144---

A<27,00>

-----.,.~I

LONG~ORD ADDRESS

PHYSICAL
MEMORY
ADDRESSES

;t-----i 512 MB
1/0
ADDRESSES

......._ _ _...J

1,000 MB

SB! PHYSICAL
ADDRESS SPACE

Figure 5~7 • Memory Controller Physical Address Space

During a read cycle, 32 bits of data are accessed from the addressed loca~
tion in the memory, with the memory controller checking for single~ or
double~bit errors. Single~bit errors are corrected and rewritten into the
memory in a subsequent memory cycle. When a double~bit error is
detected, the same data and check code that was read is rewritten to ensure
that error will recur on subsequent read operations. An indication of the
error condition is tagged and transmitted to the requester with the cor~
rected data or uncorrectable bad data during the next available bus cycle.
The data word is transferred with the proper tag and identification (ID)
code of the commander that requested the data.

5-21

A commander arbitrates and gains control of the bus to initiate a read
cycle to a memory subsystem. The commander then transmits a command
or address tag and identification code (ID), which is decoded by all the
subsystems on the bus. If the address corresponds to the memory subsystem and no faults are detected, the memory subsystem initiates a memory
cycle. If a memory cycle is being executed, the command is stored in the
queue until the cycle is complete and the memory notifies the commander
that the message has been received. The address is fetched from the memory while the memory controller is requesting, arbitrating, and gaining control of the bus for the transfer of data and commander's ID code. Read
cycles with single-bit errors require an additional bus cycle to correct the
error. In this case, the' controller rerequests the bus and transmits the data
after gaining control of the bus.
The extended read cycle is similar to the read cycle except that 64 bits of
data are accessed from the addressed location. The data is transmitted on
the SBI in two successive bus cycles. The lower 32 bits are transmitted
before the upper 32 bits. If a single-bit error occurs, the data transmission
is delayed until the memory controller again requests the bus and gains
control.
The write masked function instructs the addressed memory controller to
modify the bytes as specified using data transmitted in the succeeding
cycle. This is accomplished by initiating a read cycle followed by a write
cycle. During the read portion of the cycle, the 64-bit word is retrieved, the
error code is checked, and the appropriate bytes are modified in the upper
or lower half of the word. New check bits are then encoded and the modified word is written into the memory. Single-bit errors that occur during
the read portion of the cycle are corrected. Uncorrectable errors are rewritten into the memory with an erroneous check code and the new data is not
used. Up to four bytes in the upper or lower word can be modified in a
write masked cycle.
The extended write masked function instructs the memory controller to
first modify the bytes specified by the mask field in the low 32 bits of the
addressed storage element, using data transmitted in the succeeding cycle.
The controller then modifies the bytes of the high 32-bit storage element as
specified by the mask field of the first data-word cycle, using data transmitted in the next cycle. The mask field in the second data word transmission
is ignored. This cycle is similar to write masked except that from 1 to 8
bytes of an address can be modified in the upper and lower word. An
extended write masked function that specifies modification of all 8 bytes
unconditionally writes the new 64 bits and 8 check bits to the designated
address.

5-22· VAX-1l1780 and VAX-1l1785 Processors

The interlock cycles, which are special memory cycles used for process
synchronization, consist of the interlock read cycle and the interlock write
cycle. Each interlocked cycle is a pair of cycles, an interlock read masked
followed within an arbitrary number of cycles by an interlock write
masked. Interlock read and write cycles are 32-bit operations. An interlock
line on the SBI is used to coordinate activity between memory controllers.
An interlock timer starts with the acceptance of an interlock write. If the
interlock write is not found after 512 bus cycles, the interlock line is
cleared.
Implementation of the interlock read masked cycle is similar to that of the
read masked cycle, except that a special function code is decoded by the
memory controller. The memory controller also monitors the interlock line
on the bus for interlock activity. If the interlock line is not asserted, the
addressed memory controller acknowledges the cycle and sets its interlock
line on the SBI until a valid interlock write has been received. If single-bit
errors are detected, the controller corrects the data and transmits the data
with the proper tag. If an uncorrectable error occurs, the read data substitute tag and the erroneous data are transmitted and the memory rewrites
the erroneous data and ECC. Every commander on the SBI that can issue an
interlock command asserts the interlock line on the bus for one cycle
immediately following the interlock read mask command. This ensures the
cooperation among memory controllers that respond to interlock reads
without ambiguity.
The interlock write masked cycle is similar to the write masked cycle
except that the interlock line is monitored to verify the integrity of the
command before acknowledging and implementing the cycle.

• MEMORY CONFIGURATION REGISTERS
The memory controller contains three memory configuration registers that
provide memory configuration and error information to the operating
system and diagnostic software. Descriptions of the read-write registers
follow.

5-23

Memory Configuration Register A - Memory configuration register A contains information on SBI fault status, power status, and memory configuration_ The format of the register information is shown in figure 5-8_
31

987

16 15
,.

•

SBI FAULT STAT

NOT PWR
USED STAT

NOT USED

MEM SIZE

543 2 1 0

MBZ

MEM N o j
TYPE USED

INTLV WR ENB

INTLV

Figure 5-8 • Memory Configuration Register A Format

Memory Configuration Register B - Memory configuration register B provides file pointer, starting address, and ECC control information. The information format is shown in figure 5-9.

FILE IN PNTR
FILE OUT PNTR
MEM START ADDR ENB
MEM INIT STAT
NOT USED

JUUl

SUB ECC
ECC BYPAS
FORCE ERR
REFR IND

Figure 5-9 • Memory Configuration Register B Format

Memory Configuration Register C - Memory configuration register C contains a summary of the ECC error information. The register fortnat is shown
in figure 5-10.
31 30 29 28 27

IIIIII

uuut

2423
I

16 IS
I

I I I

•
ERRADDR

8 7

I I

•

ERRSYND

ERR LOG REQ FLAG
HIGH ERR RATE
INHCRD
NOT USED

Figure 5-10 • Memory Configuration Register C Format

5-24· VAX-ll/780 and VAX-ll/785 Processors

Shared Multiport Memory

The MA780 multiport memory option is a shared memory subsystem that
enables up to four VAX-111780 or VAX-ll/785 processors to access a common bank of ECC MOS memory. The information stored in the multiport
memory is accessed at random by any of the processors the same way as
a single processor accesses its local memory. Two MA780 subsystems can
be connected to each processor and each subsystem can contain up to 2
Mbytes of multiport memory. The features of the MA780 shared memory
system are:
• Fast interprocessor communications
• Expanded physical address space up to a system total of 12 Mbytes
• Parallel or sequential MA 780 configurations allow exceptionally fast
processing
• Access to shared memory that is transparent to the user
• Invalidation logic that permits access of shared memory data through
cache memory
• Memory interlock capability to prevent shared memory from being read
by one processor while being updated by another processor
• Individual memory port control that permits high overall system uptime
The VMS operating system fully supports MA780 configured systems.
Applications built around multiple cooperating processes can be reconfigured to run on a multi-CPU system without program modification. Processes in. shared memory can be moved from one processor to another
without affecting the programs involved. The VMS system provides support for MA780 configurations in the areas of interprocessor communications, including the sharing of data regions and code, VMS mailboxes, and
common event flags. Each CPU in the multiport system operates independently using its own copy of the VMS operating system stored in its local
memory.
• MA780 SHARED MEMORY CONFIGURATION
The MA780 multiport memory can be mounted in an existing CPU expansion cabinet or is available in a separate cabinet that attaches to the
CPU cabinet. The cabinet of the attached version is the same size as the
H9652-H CPU expansion cabinet previously described. It includes a port
interface, memory controller, and power supply, and has space for up to
2 Mbytes of memory and a memory battery backup unit. Figure 5-11 shows
a system configuration using the MA 780 shared memory subsystem.

""'";l
""'

UO.ZIV.ln'8.zjuoJ UtalslS .lossaJo.ld Ivna 08LVW. r r-{ a.tn'8.z:l

5-26· VAX-ll1780 and VAX-ll1785 Processors

The MA780 includes 256 Kbytes of ECC MOS memory with the initial configuration. Additional memory can be added in 256-Kbyte increments up
to a maximum of 2 Mbytes. The VAX-ll/780 system will support two
MA780 subsystems, thus increasing the total addressable physical memory
to 68 Mbytes per system.
The MA780 shared memory includes two interface ports to allow communication between a VAX-ll/780 or VAX-ll/785 processor and a second
processor. Additional interface port options that mount in the MA780 permit access to a third and fourth CPU. The port options mount in the MA780
subsystem. Systems that contain three or four MA780 interface ports
should also include a selective cache invalidate option.
The MA780 cabinet contains power supplies, cables, and memory array
modules as shown in figure 5-12. Adequate space is provided in the cabinet
to,accommodate a second MA780. The memory battery backup option can
be installed in the MA780 cabinet and is capable of supporting 2 Mbytes of
memory for a minimum of 10 minutes. Smaller amounts of memory are
supported for longer periods of time.

MA780
CONTROLLER
AND 2MB
TOTAL MEMORY

SHARED
MEMORY
POWER
SUPPLY

I
I
I
I
I
I
MA780
I
CONTROLLER
I
AND 2MB
I
I TOTAL MEMORY
I
I
I
I
I

SHARED
MEMORY
POWER
SUPPLY
COOLING

MEMORY BATTERY BACKUP
MEMORY BATTERY BACKUP

POWER CONTROL
Front View

Figure 5-12 • MA780 Shared Memory Cabinet Configuration

5-27

• SHARED MEMORY OPERATION
The MA780 has a maximum throughput rate of 11 Mbytes per second for
64-bit quadword (8-byte) data transfers. Smaller sized transfers result in
lower throughput. The throughput rate is a function of the number of
cache hits and the I/O and SBI traffic. The high throughput rate is achieved
through the use of a separate buffer in each interface port for commands
and data. Each port is serviced on a demand basis that allows first-in
requests to be serviced first; therefore, inactive p'orts do not have to be
polled. A port gains access to the shared memory within three memory
cycles.
The MA780 allows parallel or sequential (pipeline) processing. In parallel
processing, a task is shared berween rwo or more processors, thereby
reducing the total processing time. Sequential processing can increase the
system throughput by allowing data to be exchanged berween processors
that are handling sequential parts of an application. Each processor is dedicated to a specific portion of the total application and, upon completion of
that portion, passes the results to the next processor. Figure 5-13 shows the
parallel and sequential processing configurations.

Parallel Processing

Sequential Processing

Figure 5-13 • MA780 Parallel and Sequential Processing Configuration

5-28· VAX-1l1780 and VAX-1l1785 Processors

The shared memory includes error correcting code (ECC) to correct singlebit errors and detect double-bit errors during memory read and write
transactions. Parity error checking is included on internal buses.
During a processor transaction with shared memory, all other processors
are prevented from accessing the memory until the first processor has completed its transaction. After data has been written to a shared memory
location, the MA780 sends an invalidate signal and address to each processor. The processor checks the cache to determine if that address is present
and marks the contents as invalid. During subsequent read operations, the
processor is required to access the new information from shared memory.
A selective cache invalidation option is available for multiprocessor systems that maintain a high rate of SBI transactions. In systems with three or
four processors, the MA780 sends invalidate signals only to the processors
that· have accessed a given location in shared memory. The invalidation
map has one entry for each 64-bit quadword in shared memory. This entry
contains four bits, one for each processor. When a processor reads a 64-bit
quadword, the MA780 controller sets the bit in the correct invalidation
map entry. When a processor writes into that 64-bit quadword again, the
MA780 controller notifies the processors whose bits have been set in the
invalidation map. The bits are then cleared, except in the processor that is
performing the write operation. Overall traffic on all SBls and the cache
activity is therefore minimized while data integrity is maintained.
The MA780 supports a failsoft capability, which is the ability of the system
to operate when certain elements in the system are failing. The system
diagnostics can access the MA780 through anyone of its memory access
ports, and any processor connected in the system can read the multip~rt
status register. Each port can be separately controlled and a defective processor can be disabled. This permits the system to be serviced when an interface port or processor is malfunctioning. The MA780 generates interrupts
to notify a port of a power failure or an error condition. The VMS operating
system logs the detected errors for evaluation.

The VAX-1l1782 attached-processor system is a high-end member of the
VAX family and is software-compatible with other VAX systems because of
the VAX architecture. Its tightly coupled, asymmetrical, dual-processor system is based on the MA780 shared-memory subsystem. The system contains two VAX-1l1780 processors: a primary processor and a secondary
(attached) processor. Each processor shares the same data structures and
up to 8 Mbytes of data in the MA780 multiport memory. All kernel-mode,
interrupt-code, and 110 operations are executed by the primary processor,
which also schedules the operations of the attached processor. The
attached processor communicates with the primary processor through the
shared memory and provides additional computational power. Because the
attached processor is free from 110 activities, its time can be scheduled
entirely for data processing activities. The processors execute the same
copy of the VAXIVMS operating system code; therefore, only one copy of
the operating system has to be maintained.
A VAX-1l1782 upgrade package (782UP-F) is available to enable owners of
VAX-1l1780 processors to convert their system to the higher performance
VAX-1l1782 dual-processor configuration.
Figure 6-1 shows the system configuration of a typical VAX-1l1782
attached-processor system.
The VAX-1l1782 system provides up to an 80 percent performance
improvement over the VAX-111780 single processor system. It is suitable
for both commercial and technical applications, including experimental
data r~duction, structural analysis, electronic and mechanical design 'with
interactive graphics, high-energy physics, and quantum mechanics
research. With the VAX-1l1782 system, many users have access to largescale databases for econometric modeling, forecasts and business simulation, and statistical processing applications.

6-2· VAX-1l1782 Attached-processor System

Figure 6-1 • VAX-1l1l82 Attached-processor System

6-3

The VAXIVMS operating system scheduler dynamically allocates computeintensive functions to the attached processor. Functions that require I/O
transfers are assigned to the primary processor. The VAXIVMS software
system supports the operation of MA780 subsystems, and applications
developed for individual VAX systems will operate on the VAX-1I1782 system with no program modification. Some of the system features are:
• As a high-performance VAX system, it can run demanding applications.
• Existing VAX-1I1780 systems can be upgraded to VAX-1I1782 systems.
• Up to 8 Mbytes of main memory can be shared berween processors.
• Processor interaction is transparent to the user.
• Improved dynamic load leveling provides optimal use of system
resources.
• Applications can be transferred from a single processor to an attachedprocessor system without modification.
• Only one copy of the VMS operating system has to be maintained .

. VAX-1l1782 Processor System Configuration
The VAX-lI1782 attached-processor system consists of rwo VAX-1I1780
processors and cabinets, one MA780 shared-memory subsystem cabinet,
and one UNIBUS expansion cabinet. The primary processor includes the
VAX-lI1780 CPU local memory for diagnostics programs only, a sharedmemory interface, and a DW780 UNIBUS adapter. All I/O devices connect
to the primary processor. The secondary (attached) processor includes a
VAX-lI1780 CPU, local memory for diagnostic programs, and a sharedmemory interface. The shared-memory cabinet in the basic system contains
2 Mbytes of ECC MOS memory and a memory battery backup unit. The
same version of the VAXlVMS operating system and microcode is used for
each processor and is included with the basic system. Figure 6-2 shows the
system configuration.
The MA780 cabinet contains the H7112 memory battery backup units that
maintain data in memory during a power failure. Processor options
installed in the primary processor, such as the floating-point accelerator,
must also be installed in the attached processor.
Communication berween the processors and shared memory is through the
port interfaces, which are in the processor SBI backplane. The interfaces
connect by cable to the MA780 shared memory unit. Figure 6-3 shows the
VAX-l)/780 system components and bus-configuration.

~
~

~
.....

~
?3
~

0:-

VAX -11/780 Attached
Processor

MA780

Multiport
Memory

(CPU and 256 KB Local Memory)

VAX -11/780 Primary
Processor

H7112BBU

(H9652-M)

H7112BBU

"*tl~

(CPU and 512 Local Memory)
(4MB Total)

Console Terminal

Unibus
Expansion
Cabinet

I
Console Terminal

Figure 6-2· VAX-1l1782 Attached-processor System Configuration

"Ii'-

6-5

VAX-111780
PRIMARY
PROCESSOR

SBI BUS

MA780PORT
INTERFACE

<}
MA780MULTIPORT SHARED
MEMORY

<}
MA780PORT
INTERFACE

VAX-U/780
ATTACHED
PROCESSOR

<}
SBI BUS

Figure 6-3· VAX-1l1l82 System Components

6-6· VAX-1l1782 Attached-processor System

VAX-111782 Upgrade Package
Single VAX-1l1780 processor systems can be converted to a VAX-1l/782
attached-processor system by adding the VAX-111782 upgrade package.
This option includes a VAX-1l1780 processor, MA780 multipart memory
subsystem, cache invalidate option, 1 Mbyte of ECC MOS memory, and .
LA120 console terminal. If the single VAX-1l1780 processor contains an
FP780 floating-point accelerator option or a KE780 extended range G and
H floating-point data type option, the attached processor must contain the
same options. The multipart memory subsystem includes two port interfaces that connect to VAX-11/780 processors. Figure 6-4 shows the VAX111782 upgrade system configuration.

I
VAX -11/780 ATIACHED
PROCESSOR

MA780
MULTIPORT
MEMORY

(CPU AND 256 KB LOCAL MEMORY)
(4MB TOTAL)
H7112BBU

I
CONSOLE TERMINAL

H7112BBU

Figure 6-4· VAX-111782 Upgrade Package Configuration

VAX-111782 System Operation
The operation of the VAX-1l1780 processor and the MA780 shared memory subsystem is described in "Chapter 5, VAX-1l1780 and VAX-1l1785
Processors." The VAX-111782 system provides a maximum throughput
rate of 11 Mbytes per second with 64-bit quadword (8-byte) data transfers.
The actual throughput rate is dependent on the number of cache hits
encounted and the number of I/O-device and SBI-bus transfers in process.

6-7

The cache invalidation option (MA780-D), included with the attachedprocessor system, is used to minimize data transfers and cache activities
while maintaining the integrity of the data. The cache invalidate option
allows systems with a high rate of transfer on the SBI bus to send invalidate
signals to the CPU that has accessed a location in the MA780 multiport
memory. An invalidation map contains one entry for each 64-bit quadword
in shared memory and an entry contains four bits, one for each CPU. When
a CPU reads a 64-bit quadword from shared memory, the MA780 controller
sets a bit in the correct invalidation map entry. When a processor writes
into that 64-bit quadword, the MA780 controller notifies the processor that
has the bits set in the validation map and clears the remaining bits.
Applications designed for multiple cooperating processes can be reconfigured to run on a multiprocessor system without program modification.
Processes running on a VAX-111782 attached-processor system will execute on one processor and then the other, all transparent to the programs
involved.
Process scheduling in the VAX-ll/780 processor is performed similarly to
that of a single VAX-ll/780 processor system, with the highest-priority
transaction executed first. The attached processor, however, will not be
preempted by a higher priority process and will not execute transactions in
kernel mode. The primary processor performs the scheduling for the system by scheduling the attached processor first and then scheduling itself.
When a process cannot be performed on the attached processor, the primary will execute a process and cause an asynchronous system trap interrupt to occur when the process leaves kernel mode. The interrupt causes
the primary processor to reschedule the process to run on the attached
processor.

• PROCESSOR INITIALIZATION
The primary processor is initialized before the attached-processor. A standard bootstrap loading procedure loads the operating system in the primary processor and the multiprocessing code into nonpaged pool. A
Digital Command Language (DCL) command loads the multiprocessing
code and is usually incorporated into the startup command file at each site
by the system manager. A new system control block (SCB) is initialized for
the attached processor and the primary SCB is modified to include the
multiprocessing scheduling code and MA780 interrupt communication.
The operating system is then loaded in the attached processor and it interrupts the primary processor to request a process to execute. The primary
processor is responsible for scheduling itself and the attached processor.

6-8· VAX-1l1782 Attached-processor System

• ATTACHED PROCESSOR STATES
Figure 6-5 shows the transition states of the attached processor. The
attached processor is initialized by the primary processor when the multiprocessing code is loaded. After initialization, the attached processor
becomes idle until the next rescheduling operation is performed by the
primary processor. The primary processor initiates the scheduling and
assigns tasks for the attached processor, which enters the busy state. The
attached processor checks the state, performs a load-process context, and
sets its state to execute. The attached processor will continue to execute its.
current process until the time allocated for the process is exceeded or the
process requests an action to be performed in kernel mode. When this
occurs, the attached processor saves the processor context, enters the drop
state, and notifies the primary processor that it is available for rescheduling. After receiving the process from the attached processor, the primary
processor sets the attached processor state to idle. The stop state, used to
disable the attached processor, is initiated by the system manager with a
DCL command or by the primary processor during operations such as bugchecks. The attached processor can be enabled by another DCL command
or by rebooting.

PRIMARY

ATTACHED

PRIMARY

ATTACHED

ATTACHED
PRIMARY

Figure 6-5 • VAX-ll/782 Attached Processor States

6-9

• MULTIPROCESSING INTERRUPT COMMUNICATIONS
The multiprocessing code uses MA780 interprocessor interrupts. The primary processor interrupts the attached processor to request an invalidate
of a system space address, to indicate that an asynchronous system trap has
occurred for the process currently being executed in the attached processor, or to request a bugcheck. The attached processor interrupts the primary processor to request a reschedule event, to log an error, or to request
a bugcheck.
Many of the fault-handling features of VAXNMS are included with a VAX111782 system. These include a powerfail, bugcheck, machine check, automatic restart, and error logging. When the attached processor loses power,
the process that is executing on the attached processor is transferred to the
primary processor, where the process continues to run. If the power to the
primary processor fails, the attached processor waits for the primary processor to be restarted. A bugcheck can be initiated by either processor, stopping the execution of both processors. The processors will synchronize
during the bugcheck and both processors can be set to reboot automatically. Machine checks and error logging are performed the. same as with a
single VAX-1l1780 processor system. The error log entries include the system ID to identify the processor that made the entry.

The VAX 8600 is a powerful, high-performance computer system designed
for engineering, technical, commercial, and special applications. It implements the VAX architecture and is supported by the VMS operating system
with its associated layered software products. It also supports the ULTRIX32 operating system, Digital's native-mode UNIX software, which has been
functionally enhanced to operate with VAX virtual-memory computers.
The plug-compatible VAX 8600 system can replace most VAX-based systems and can be used as a small mainframe system or as a high-end minicomputer for realtime, interactive, and distributed processing applications.
The VMS operating system provides compatibility between the VAX 8600,
other VAX processors, and the PDP-ll family of processors, thereby allowing owners of these systems to upgrade to the new, more powerful VAX
8600 processor. The VAX 8600 system incorporates the latest technological
advancements and diagnostic functions to provide a fast, efficient, and reliable system for many applications. Figure 7-1 shows the VAX 8600 processor. Some of the features and benefits of the system are
• High performance and increased reliability through the use of EeL gate
arrays and advanced processor design.
• Comprehensive diagnostic and maintenance features that ensure reliable
operation, system availability, and ease of maintenance.
• Main memory expansion up to 32 Mbytes using 256-Kbit MOS RAM integrated circuits.
• Flexible I/O configurations that permit UNIBUS, MASSBUS, CI bus, and
DR32 Digital data-interconnect devices to be implemented easily on new
and existing VAX 8600 systems.
• An efficient microprocessor-controlled console subsystem with RL02
removable cartridge disk drive for diagnostics, microcode loading, and
automatic remote testing.
• Quiet operation through the use of acoustical mufflers.

7-2· VAX 8600 Proce$$or

Figure 7-1 • VAX 8600 Processor Unit

7-3

. VAX 8600 Physical Configuration
The VAX 8600 processor and console, shown in figure 7-2, are contained in
a CPU cabinet and an attached front-end cabinet. The cabinet is 186.0
centimeters (73.25 inches) wide and 153.0 centimeters (60.25 inches) high.
The CPU cabinet contains the processor, console logic, floating-point accelerator, space for up to 32 Mbytes of main memory, an SBI adapter bus
backplane, and an 1/0 adapter backplane. Th'e modular power supplies,
regulators, and power distribution network are above the logic area. At the
bottom of the CPU cabinet are the power control unit, which receives the
system line power, and the battery backup unit, which supplies power to
the memory in the event of a power failure. A blower unit at the top of the
cabinet provides cooling for the power supplies and logic modules. The
switches and indicators that monitor and control the system operation are
on the panel at the top of the CPU cabinet.
The front-end cabinet includes the RL02, a lO.4-Mbyte removable-media
console load device; a UNIBUS backplane mounted in a BA11-A box for
communication devices; and a step-down power transformer that is supplied when 50-Hertz main power is used. The step-down transformer has
voltage taps to ensure line power compatibility.
A UNIBUS expansion cabinet can be added to expand the system UNIBUS.
A synchronous backplane interconnect (SBI) expansion cabinet can be
added to extend the SBI interface, which is included in the main cabinet,
and two SBI expansion cabinets can be added when a second SBI adapter is
used.
The signal cables between the cabinets and the communication and storage
devices connect to I10connector panels located at the rear of the cabinets.
The connector panels have plates that can be removed to mount cable
connectors.

7-4· VAX 8600 Processor

153.0 em
(60.25 in.)

Blower Units

RL02 Console
Disk Drive

~erls~p~Ii~S

BA11-A
Expansion Box

aidl Dijtr/bfii n

~ID

0::;;

E",

Processor
Logic
Console
Interface
Memory
Controller

Power
Transformer
Memory
Battery Backup

e !
u

-8
<C

iii

:i."*

ex>

Input!
Output
Slots

CI)

D-

Power
Controller

Figure 7-2 • VAX 8600 Processor Configuration

7-5

System Expansion Cabinets
The expansion cabinets are available for mounting additional UNIBUS
interfaces and for mounting a second SBI adapter.

The H9652-F series of UNIBUS expansion cabinets, shown in figure 7 -3, are
153 centimeters (60.25 inches) high and 69.2 centimeters (27.25 inches)
wide. The H9652-FA (-FB) cabinet includes a BAll-A mounting box and
provides space for adding a second BAll-A mounting box. The H9652-FC
(-FD) cabinet includes two BAll-A mounting boxes. No expansion boxes
are mounted in the H9652-FE (-FF) cabinet. The BAll-A box contains a
power supply and allows installation ofDDll-CK (four-slot) and DDll-DK
(nine-slot) UNIBUS backplanes. Forty option panel spaces are available at
the rear ofthe cabinets for mounting the 1/0 device conneCtors.

1111 111111111111111

I!!!!!
I/O
Connection
Panel

fBA11-K
UNIBUS

Expansion Box

I/O
153 em
160.2 in) Connection
Panel

...

V
Space For
BA11-K

I/O
Connection
Panel

•

---

69.2cm
127.25 in.)

REAR VIEW

•

--..

Figure 7-3 • H9652-FA (-FB) UNIBUS Expansion Cabinet Configuration

7-6· VAX 8600 Processor

The H9652-CA (-CB) is a SBI expansion cabinet 153 centimeters (60.25
inches) high and 69.2 centimeters (27.25 inches) wide. The SBI expansion
cabinet contains an SBI backplane and power supply. It provides four
option panel spaces and space for an additional power supply. The configuration of the H9652-CA (-CB) SBI expansion cabinet is shown in figure 7-4.

1£
rJl

--'

1£

rJl

--'
UJ

--'
w

1£

ii:0

SPACE
FOR
POWER
SUPPLY
COOLING

FRONT VIEW

69.2cm
(27.25 in.)

--'
UJ

153cm
(60.2 in.)

--...

Figure 7-4 • SBI Expansion Cabinet Configuration

Ii:
0

7-7

. VAX 8600 Processor Organization
The functional organization and bus structure of the VAX 8600 processor
are shown in figure 7-5. The processor contains four main logic subsystem
blocks: the instruction execution logic (Ebox), the instruction/data fetch
logic (Ibox), the memory control logic (Mbox), and the floating-point
accelerator logic (Fbox). A system of internal buses form the address, data,
and control signal paths within the CPU logic. The console subsystem connects to the Ibox through the C bus. The synchronous backplane adapter
(SBIA) connects to the Mbox and provides the SBI bus for communication
with the external devices.
Console Subsystem
The console subsystem is a microprocessor-controlled interface between
the CPU and console terminal, remote diagnostic service port, environmental monitoring module (EMM), and console storage device. It consists of an
LAlOO console terminal, an RL02 disk drive mounted in the front-end cabinet, and the console interface module located in the CPU backplane assembly. Some of the features and functions of the console subsystem are
Provides system time-of-year clock
Performs the system power sequencing and environmental monitoring
Includes a serial line interface for remote diagnostic service or automatic
program testing
• Includes the system and CPU diagnostic programs
• Provides memory storage for bootstrap and diagnostic programs
• Provides self-diagnostic testing during initialization
• Includes powerup configuration programming
The console interface is program-controlled by a Tll microprocessor
(PDP-lll, and the software in a 256-Kbyte dynamic RAM and a 4-Kbyte
PROM. It contains three asynchronous serial-line interfaces, two bus interfaces that communicate with the CPU, and an interface for the RL02 disk
drive and the system control panel as shown in figure 7-6.

'7"
00

CONSOLE
PROGRAM
PROM
(8KX 8 BIT)

CONSOLE
LOAD DEVICE
RAM
(256K X 9 BIT)

TIME-OF-YEAR
CLOCK
(TOY)

><:

8
c~

R
Tll
MICROPROCESSOR
AND SUPPORT
LOGIC

MICROPROCESSOR BUS

SERIAL
LINE
INTERFACE

CONSOLE
BUS
INTERFACE

DATAlADDRESS LINES

QBUS
ADAPTER
(QBAl

SERIAL
DIAGNOSTIC
BUS INTERFACE
(SDB)

TERMINAL

(LAlOO)
REMOTE
DIAGNOSTIC II
SERVICE

'USA AND CANADA ONLY
RL02
DISK DRIVE

Figure 7-5 • VAX8600 Processor Components

SDBUS

TO CPU

TO CPU
EBOX

~...

MEMORY
EXPANSION
ECCMOS
MEMORY
ARRAY
4MBYTE
EVA

iO
~

..,'"'"

MDBUS

TO E BOX .. INTERRUh

(SBIAl)

• OPTIONAL

Figure 7-6 • Console Subsystem Components

7-10· VAX 8600 Processor

The console terminal communicates with the console interface through a
serial-line interface and serves as an operator's system terminal or as a
diagnostic console terminal. As a system terminal, it provides control of the
system for initialization, bootstrapping, and updating of the software. The
terminal also provides access to the operating system to load system
devices and transfer information to EIA serial-line terminals. During the
diagnostic function, the terminal can be used to initiate diagnostic programs, to examine and deposit data into the internal processor registers
and memory, and to control the processor operation during maintenance.
The remote diagnostic serial-line interface alIows diagnQstic programs to
be"loaded and monitored from Digital's remote diagnosis centers. The
interface can be connected through a modem to the remote location over
standard dialup telephone lines.
The environmental monitoring module (EMM) is located in the power supply area of the CPU cabinet and receives inputs from sensors distributed
throughout the system cabinets. The EMM monitors and controls the dc
voltages and ground currents within the CPU cabinet, and monitors the
environmental conditions, including the cabinet air flow, and cabinet temperatures. The functions of the EMM are controlled by the console interface through the EMM serial-line interface.
The console module contains bus interfaces for communication with the
CPU, RL02 disk drive, and system control panel. Information is transferred
between the RL02 disk drive and console module through the Q-bus and
the Q-bus adapter. The Q-bus connects to the RL02 drive through the
RLV12 disk drive controller. The RL02 drive and controller are mounted in
the front-end cabinet.
The state of the logic levels in the CPU is monitored by the console interface through the serial diagnostic bus (SDB). Module control bits can also
be loaded into the CPU through the SDB. The SDB connects to alI major
logic elements in the CPU and to the SDB adapter in the console module. It
provides 24 visibility/control channels through which the console software
can initialize the CPU hardware, increment the CPU clock, sample the state
of the CPU logic, and shift the information to the console subsystem for
evaluation. Each visibility channel in the CPU contains an 8-bit visibility
register that can be shifted serialIy or loaded in parallel by the channel's
clock. The logic levels are selected by the paralIel outputs from the visibility register. Parallel data is loaded into a visibility register from the diagnostic terminator network in the CPU module under control of the console
subsystem. Serial data is loaded into the visibility register from the console
and transferred to the console from the register. The console program
reads a visibility channel by stopping the CPU clock and by shifting the

7-11

selected bits from the diagnostic terminator network into the visibility register under control of the SDB clock. The progress of the CPU operations
can be followed by the continual stepping of the CPU clock and monitoring
the results.
The console subsystem also communicates with the CPU through the console bus (C bus). The C bus interface in the console module contains a 32byte dual-port RAM and three external8-bit registers. One port in the RAM
has direct access to the console software and one port has direct access to
the microcode running in the Ebox of the cpu. The RAM locations and the
external registers in the C bus interface communicate with the time-of-year
clock, the system identity registers, the local and remote terminals, and the
RL02 console load device. The interface also contains transmit and receive
data buffer locations used by the console-support microcode in the CPU
when communicating with the console software .
• ENVIRONMENTAL MONITORING MODULE
The environmental monitoring module (EMM) unit is mounted in a dedicated space of the power supply area and monitors the environment in
which the system operates. The EMM unit contains a logic module and a
front panel that provides visual indicators. The primary function of the
EMM unit is to monitor the dc voltages of the modular power supplies and
the outputs of the temperature sensors. The secondary function of the
EMM is to measure the flow of air in the CPU cabinet and the current in the
grounding lines of the system. Circuits are included to detect when a CPU
module is not installed in the backplane or is installed in the wrong location. These conditions are indicated by lights on the front panel of the
EMM unit. Indicators are also included to identify a power supply regulator
whose thermal switch has been activated.
The EMM contains a 16-channel analog multiplexer, 8-bit digital-to-analog
(AID) converter, analog voltage comparator and a multiprocessor to measure the regulator voltages. Thermistors are used to sense the temperatures,
and limit detectors provide outputs that set fault flags when a temperature
limit has been exceeded. Voltages and flags are monitored in sequence until
a fault is detected. The encoded fault data and an 8-bit AID value are
transferred to the console subsystem. Commands can be issued from the
console subsystem to logically disable the regulator output voltage or to set
the regulator outputs within specified margins. The system software normally controls the action to be performed when a fault is detected or when
a margin is not within the limits. If a thermal switch exceeds 42 degrees
Celsius or the logic temperature exceeds 20 degrees Celsius, a warning
message will be issued and the system power will be removed if the condition is not corrected within 5 minutes.

7-12· VAX 8600 Processor

Internal Bus Structure - Communication between the logic elements of

the CPU is through the internal bus structure consisting of the write
bus (W bus), operand bus (OP bus), Ebox virtual-address bus (EVA), Ibox
virtual-address bus (IVA), memory data bus (MD bus), and adapter bus
(A bus). The Mbox transfers data, address, and select information to
memory through the array bus. The console bus (C bus) is a data bus that
connects from the console interface to the Ebox. The serial diagnostic bus
(SDB) is a serial data path between the console subsystem and the CPU
logic elements. Communication between external devices and the CPU
is through two SBIA buses that connect to the synchronous backplane
interconnect adapters.
The W bus transfers 32 bits of information between the Fbox, Ebox, and
Ibox. It is used to update the information in the general purpose registers
(GPRs). Whenever a GPR is updated by the Ebox, the resulting data is
transferred through the W bus to update the information in the GPR files
of the Fbox and the Ibox. The W bus is also used to transfer the data
results from the Fbox and Ebox and to store the results in memory
through the Ibox. New instruction stream addresses from the Ebox to the
Ibox are also sent through the W bus.
The operand bus (OP bus) transfers 33 bits of operand information and
CPU register data from the Ibox to the Ebox and Fbox.
Read and write data transfers between main memory and the Ibox, is
through the memory data (MD) bus. The MD bus transfers 36 bits of information between the Mbox and the Ibox. The data to the Ebox and Fbox is
first transferred through the Ibox.
During read and write operations, the virtual addresses of the data in memory is transferred from the Ibox through the 32-bit IVA for translation by
the Mbox. The EVA is used by the Ebox to send virtual addresses to the
Mbox for translation during memory read and write operations. It is also
used to fill the translation buffer.
During memory read and write operations, the memory address and select
information is sent to memory from the Mbox through the memory array
bus. The address data is also transferred through this bus.
The C bus is the data path between the data path and the console. It
provides the Ebox access to the register file and other control bits in the
console. It also passes the ASCII characters between the operators console
terminal and the CPU under VMS.

7-13

The SDB is used to verify the CPU operation, diagnose and isolate CPU
hardware failures, and to transfer information between the console subsystem and the CPU. The SDB consists of 24-bit serial data paths to the CPU
logic and each data path contains a module interface, which provides a
clock control and data return path to the console. The SDB lines for each
channel consist of a clock line, a data line, and three control lines. The
control lines consist of a shift line for the visibility channel and two lines
used to select the channel.
Processor Logic Elements
The main logic elements in the CPU are the instruction/data fetch (Ibox),
the instruction execution (Ebox), the memory control (Mbox), and the
floating-point accelerator (Fbox). Each element contains a copy of the 16
general purpose registers (GPRs) to ensure immediate access to the GPR
data and system status information .

• INSTRUCTION BOX FUNCTIONS
The instruction box (Ibox), consisting of the instruction and data prefetch
logic, is the interface between the Ebox and Fbox execution units and
memory. It contains the following logic functions:
• 8-byte FIFO instruction buffer
• Dispatch RAM
• Memory data path
• Control store RAM
• GPR file and an R-Iog file
• Address and memory data path
• Write latch
All data transfer to and from the execution logic is through the Ibox, which
receives the instruction stream of bytes from memory. From the memory
information, the Ibox determines the information to retrieve and the activity to initiate in the Ebox. The Ibox performs the first three stages of the
four stages required for mstruction execution. It prefetches the instruction
stream, decodes the instruction opcodes and specifiers, calculates the
required address, fetches the operands, and initiates the read and write
cycles. The execution of the instruction is then performed by the Ebox or
the Fbox while the Ibox begins processing the next instruction.

7-14· VAX 8600 Processor

The instruction buffer is an 8-byte buffer that stores a copy of the bytes
fetched from memory. The primary function of the buffer and its associated logic is to prefetch instruction stream bytes and to align them contiguously. More than one instruction is usually contained in the instruction
buffer; therefore, the next opcode and specifier will be available when the
current instruction is completed. It also is used to fetch and align decimalstring operands.
The dispatch RAM (DRAM) contains a table of dispatch addresses for every
macroinstruction and provides control information to the Ibox and
address data paths. The address data path and associated control logic
perform address calculations and branch displacements, and control the
start of the instruction buffer. Using the opcode in the instruction buffer as
an address, the DRAM sends a dispatch address to the Ebox control store.
The memory data (MD) path logic controls the data transferred between
the Mbox and the Ibox. The data is aligned by a rotator in the data path
before transfer to the execution units or to the instruction buffer.
The Ibox control store is a 256 by 52-bit RAM that processes the operand
specifiers and branch instructions, updates the register (R-Iog) file,
responds to specific Ebox commands and master reset, and assists in performing the microdiagnostics.
The GPR file contains the same information that is stored in the GPR files
of the Mbox and Fbox and provides accessibility to the register data for
addressing modes.
The R-Iog file stores the register information that may change during the
instruction execution. Information typically.stored in the R-Iog are current
program counter values, the GPR address, the amount of change to a register, and whether the change was added to or subtracted from the register.
This information is required during memory management faults to return
the processor to the state prior to the condition that caused the fault.
The address data path performs address calculations and branch displacements, and initializes the IBUF. It also provides a backup file for the GPR
and macrolevel diagnostics.
A write latch is used to align the data and to store the resulting data from
the Ebox and Fbox to be written to cache memory.

7-15

• EBOXFUNCTIONS
The Ebox performs logical, arithmetic, and other operations required to
execute the instruction. The results are then transferred to the Ibox
through the W bus, to be written into memory when required. The Ebox
controls the system operation during system initialization and during console mode functions by executing the VAX instruction set and by processing both external and internal interrupts and exceptions. The Ebox
includes the following logic elements:
• Data path logic
• Control store RAM
• Microsequencer logic
• Con$ole interface
• Maintenance logic
The data path logic includes a 32-bit binary arithmetic logic unit (ALU),
shifter and data packerlunpacker logic, two scratchpad locations that contain cppies of the GPRs, a virtual memory queue register, and a W bus
register. The ALU performs arithmetic and logical operations and provides
special functions to decrease the processing time for division, decimal
arithmetic, and compare operations. The shifter and data/packer logic is
used to pack and unpack floating-point data, to translate decimal data formats, to shift and rotate arithmetic data, and to perform other bit manipulations. When an external and internal interrupt occur simultaneously, the
internal request is processed first. External interrupts, sampled from the
1/0 adapters and received by the SBIAs, are sent to the Ebox. The Ebox
scans the SBIAs to determine the highest priority request pending for each
interrupt source. The internal interrupts are received from the console terminal, from the Mbox, and internally from the Ebox. Information is written into the control store RAM when the Ebox clocks are disabled or
stalled. The microsequencer logic accesses the RAM in response to console
operations and microprogram subroutines, traps, stalls, and subroutines.
The console interface provides the path to initialize the control store during the program loading and startup sequence. It also allows the console
to enable or disable the maintenance logic and to correct errors.

7-16· VAX 8600 Processor

The control store is an 8K by 92-bit RAM that receives information when the
Ebox clocks are stalled or disabled_ The microsequencer accesses the control store information in response to microprogram control, instruction
dependent dispatching, microprogram subroutines, microtraps, machine
stalls, console operations, and microstore-related error conditions. The con~
trol store is initialized by the console interface during a cold system start,
and allows the console to enable or disable the maintenance logic and
perform error correction operations. The maintenance functions are
implemented through the clock logic hardware, console software, and the
Ebox microword.
The Ebox control consists of context logic, memory port logic, and abort
logic. The context logic generates data size information for the Ebox data
path and references for the Ebox memory port, and controls W bus transactions. The memory port logic performs functions associated with issuing and
requeuing memory commands that are used for branch conditioning and
memory management microcode. The Ebox initiates microtraps and creates
microtrap vectors from the status information received from the Mbox.
Abort logic cancels nonrecoverable operations caused by errors that are
detected but do not result in a stall condition. Errors are recovered through
the fault process and the processor is returned to the beginning of the
microinstruction. The stall logic determines if an input or output stall condition exists in the Ebox microcycle.
The Ebox contains interrupt logic to process internal and external interrupt
requests and to determine their priority. The internal interrupts are generated by the console subsystem, the Ebox, and the Mbox. The external interrupts are sampled from the I/O adapters through the A bus.
The Ebox contains two dual-ported scratchpad memories, each consisting
of 256 32-bit registers. The scratchpad memories are used as internal temporary storage for the microcode and to store copies of the GPRs and constants.
They are also used by the memory management and operation system.
A virtual-memory-queue register provides physical and virtual addresses
to the Mbox. The W bus registers are accessed by microcode through the
Wbus.
The maintenance functions are implemented through the clock logic hardware, console software, and the memory array modules and 110 adapters.

7-17

• FLOATING-POINT ACCELERATOR FUNCTIONS
The floating-point accelerator (Fbox) is used to decrease the time to perform floating-point instructions and some integer instructions. The Fbox
logic contains the following functions:
• Adder and multiplier logic
• 16 general purpose registers
Operands received from the adder are multiplied by the multiplier logic
and the product is returned to the adder for rounding and normalization.
During floating-point operations, the multiplier operates on the fractions
and the adder operates on the exponent. During integer operations the
entire two's complement number is multiplied.
The adder logic performs addition, subtraction, and division and handles
the exponents for all the basic operations. The adder contains the logic to
unpack the floating-point numbers, to align fractions, and to round and
normalize the results. The operands are received from the OP bus and
returned to the W bus. The Fbox receives GPR updates and Ebox data,
and accesses some Fbox registers through the W bus .
• MEMORY CONTROLLER FUNCTIONS
The memory controller (Mbox) contains the logic for controlling memory
operations and for communicating with the 110 subsystems and devices.
The main logic elements of the Mbox are
16-Kbyte cache memory
512-10c:ation translation buffer
Error detection and correction logic
Port control logic
• Memory arrays
• Mbox control store
The Mbox is the interface to the main memory arrays, to the SBIAs, to the
Ibox, and to the Ebox and Fbox. The Mbox connects to the memory
through the memory array bus and to the SBIA through the A bus. Its
function is to store memory write data and to supply memory read data in
response to requests by the Ebox and Ibox, and in response to direct memory access (DMA) requests. It also stores 110 write data and supplies 1/0
read data in response to requests by the Ebox. During DMA requests from
an SBI adapter, the Mbox stores memory write data and supplies memory
read data to the SBI. The virtual to physical address translation is performed by the translation buffer. The physical address memory mapping

7-18· VAX 8600 Processor

(PAMM) selects memory array modules and 1/0 adapters being accessed
and is enabled by the PAMM logic in the Mbox. The cache memory provides fast access to the memory data.

The translation buffer is a 512-location cache memory used for storing 256
system-page-table entries and 256 process-page-table entries. During Ebox
and Ibox refetences, the translation buffer is used to decrease the virtualto-physical translation process. During normal operation the translation
buffer is loaded from the page tables in memory by the microcode; during
diagnostic operations, loading is through the SD bus.
The PAMM is a lK by 5-bit RAM that maps the physical address space and
is addressed by the high-order bits of the physical address. The outP~t is
decoded and used to select the array slot or 1/0 adapter being accessed.
The PAMM is loaded during the system initialization through the SD bus
and by system-level programs.
The 16-Kbyte cache is a writeback memory used to decrease the
access time of memory references. The cache is arranged in two groups of
8 Kbytes and provides byte parity and error correction code (ECC)
on each longword.
The Mbox control store is a 256 by 80-bit RAM that controls the Mbox
operations, including port read and write functions, error recovery, cache
reftll and writeback operations, A bus transactions, register read and write
operations, and the diagnostic functions. The control store is loaded from
the SD bus during system initialization.
The port control logic provides arbitration during instruction operand
fetching of the Ibox and read and write operations by the Ebox. The control functions of the Mbox include special byte-write logic that decreases
the time to insert the bytes into longwords. It also includes the memory
refresh logic for the 256-Kbyte MOS RAM integrated circuits in the memory array.
Each memory array module contains 4 Mbytes of ECC MOS memory storage and the timing and control logic to refresh memory when the main
power to the system fails. During read operations, the physical address
from the memory controller is sent to an array together with a start command. The array loads four longwords with ECC from memory into a shift
registerlbus transceiver. The memory controller then shifts the data, one
longword for each cycle, from the register to the A bus. The memory controller performs error correction on each longword it receives. During
write operations, the memory controller sends the address and data to the
array through the A bus. The data is loaded to the shift register on the
memory array, and the memory controller issues a start command to write
the data in memory. The memory controller can then initiate a cycle in
another array while the data is being written.

7-19

• SYNCHRONOUS BACKPLANE INTERCONNECT FUNCTIONS
The synchronous backplane interconnect adapter (SBIA) is the interface
between the SBI bus and the A bus. The SBIA provides the functions
required to control MASSBUS and UNIBUS I/O operations. It establishes
the protocol, provides the timing, and assembles the data for transmission
in either direction. The SBIA contains the following logic elements:
• Buffer control and A bus logic
• Register file
• Clock logic
• SBI bus interface
• Interrupt control logic
• Data latches
The SBIA provides the processor and memory nexus functions to the SBI
bus and generates the SBI clock signals. The nexus is a physical connection
to the SBI bus. Command imd address data are exchanged between the
SBIA and the Mbox through the A bus. Interrupt information and interrupt polling are exchanged between the SBIA and the Ebox. The A bus and
buffer control logic control the reading and writing of the SBIA register
files, notify the Mbox when CPU or SBIA transactions occur, receive and
buffer the timing signals for the A bus synchronous logic, and notify the
Ebox when an interrupt condition is detected.
The register file stores the I/O data transferred through the SBIA. It is a
dual-port, 16-line by 32-bit register that operates synchronously with both
the A bus and the SBI bus.
The interrupt logic notifies the CPU of errors detected during DMA transactions, fault conditions detected on the SBI bus, and programmed maintenance procedures. It also passes interrupt requests from SBI devices to the
CPU.
The clock logic generates the timing signals for the SBI operations.
Data latches are used to hold or convert information transferred to or from
the SBI bus. Information from the SBI bus is converted to the A bus format.
The SBIA contains 35 registers that are accessed through the CPU transaction buffer. The registers are used to condition the SBIA during bootstrap
operations, to record error information, to store vector addresses during
the servicing of interrupts and to establish maintenance and diagnostic
functions.
The SBI-bus interface logic samples the data transfer lines of the SBI during
each cycle and transfers the results to the SBI bus protocol logic and to the
data latches. It also transmits information to the SBI bus from the data
latches. The SBIA protocol logic provides protocol checking and verifies
the commands and data received by the SBIA.

The console subsystem, which is included with each VAX processor,
enables the system user, system manager, and maintenance engineer to
effectively communicate with the processor through the console terminal
and console command language. The console subsystem is a versatile tool
used to initiate the loading of the system operating program and diagnostic
programs, to control the system operations, and to perform diagnostic
maintenance. It controls the transfer of information to and from the console terminal, the remote diagnostic port, the console disk or tape drive,
and the processor control panel. The console subsystems of all VAX processors provide similar basic functions: however, additional cap,abilities are
included with some VAX processor types. Refer to the specific section of
this chapter for detailed information related to the console subsystem of
each VAX processor. The main features of the console subsystems are as
follows:
Allows the console terminal to functions as an operator's terminal or as a
diagnostic maintenance terminal
Allows communication with the processor through a simple and efficient
console command language
Permits a system to be tested through the remote diagnostic port from a
remote Digital facility
Provides fast and reliable communication with the console disk or tape
drive for program loading and updates
• Allows the customer to initiate diagnostics programs
Enables unattended rebooting of the system program after a power
failure

. Console Subsystem Description
The console subsystem is microprocessor-controlled and includes a serialline interface for the console terminal, remote diagnostic port, and control
panel, and an interface for the console load device. The console subsystem
can be used to load and update the CPU microcode, to load the operating
system programs and diagnostic test programs, and to initiate self-test
operations. The console subsystem can be used to halt the processor operation, examine the contents of registers, and load information into any of the
registers that are accessible to the user.

8-2· VAX Console Subsystems

The console terminal operates as a user's terminal during normal system
operation and as a maintenance device when the processor is not executing
instructions. The console terminal is an EIA-compatible ASCII device that
enables communication with the processor through the console command
language. The console can be a video display or printing terminal and
includes a keyboard.
The VAX processor cabinet contains a control panel that operates with the
console subsystem. The control panel contains switches and indicators to
select the processor operating modes and to indicate the operating status of
the system.
The console load device is a disk or magnetic tape drive, depending on the
VAX processor type, and is used to load bootstrap programs, processor
microcode, and to initiate the loading of the operating system software,
software revisions, and diagnostic programs. It also provides a convenient
data storage facility for personal system information.
The remote diagnostic port is included with the console subsystem of all
VAX processors. The port allows diagnostic evaluation to be performed on
the VAX processor system from a remote Digital field service facility. The
remote diagnostic service is included with the VAX 8600 system and is
optionally available with the other VAX processor systems. The use of this
option can significantly decrease the time required to detect malfunctions
and to perform routine system maintenance.
In the larger VAX systems, critical environmental conditions are continuously monitored and the information is transferred to the console subsystem for program evaluation and control.
Console Modes of Operation
The console subsystems operate in program I/O mode, in console I/O
mode, or in remote diagnostic (RD) mode. One mode is always enabled
when the power is applied to the processor.

In program I/O mode, the characters typed on the console terminal are
transferred to the processor program and information from the processor
is displayed on the console terminal. The console terminal communicates
with the operating system program and the CPU interprets instructions,
services interrupts and exceptions, and initiates input/output data
transfers.

8-3

In console 1/0 mode, the characters typed on the console ·terminal control
the operation of the CPU. Normal CPU operations are suspended and the
processor performs operations in response to instructions or commands
from the console or remote terminal. Direct memory access (DMA) transactions that are in process between devices and memory when the console
mode is initiated will continue to be processed; however, interrupt requests
will not be serviced.
RD mode operations are selected by a switch on the control panel of the
CPU. When the remote diagnostic service is included, the console subsys-

tem connects to a host computer at a Digital diagnostic center through a
modem. Fault detection and preventive maintenance can be initiated by the
remote facility. In some VAX processor systems, a microprocessor on the
RD module interprets the commands typed from the console terminal or
from a terminal at the remote service location.
Console Commands
In console I/O mode, a console command causes a series of events to be

performed. When the events are completed, a new command may be
entered or the processor may return to program 1/0 mode. Console commands that are indigenous to specific VAX processors, are defined in the
section of this chapter that contains the processor information. The basic
console commands enable the following operations to be performed:
• Load the operating system and start the CPU
• Initialize the CPU and begin processing
• Execute a console command a specified number of times
• Examine and deposit information in registers or memory locations
• Restart a halted program
• Halt the CPU operation
• Adjust and control the CPU clock
• Insert a comment in a command
• Read or transfer files from the console loading device
• Deposit data in a console relocation register
• Initiate verification routines
• Invoke an indirect command file
• Specify console command defaults

8-4· VAX Console Subsystems

Console Terminal Prompts
Four types of console prompts can be displayed on the terminal to indicate
the mode of operation. The prompt indicates to the operator that the program is waiting for a command. When the RD mode is in effect, the RD
indicator is lighted on the control panel of the processor. The prompt characters are listed and defined in table 8-1.

Table 8-1· Console Prompt Characters
Prompt

Description

The CPU is in the run mode and the console subsystem is in the
tonsole Vo mode.
The CPU is in the halt mode and the console subsystem is in the
console VO mode.

ROM)

The bootstrap loading sequence for the console subsystem is not
able to load the console program.

MIC)

l'he micromonitor program is in control of the console
subsystem.

Console Halt Codes
The processor enters console VO mode as a result of the processor operation or by commands initiated from the console terminal. When console
mode is entered, the console terminal displays the address contained in the
program counter, a code that identifies the halt condition, and a console
prompt symbol 0»). Table 8-2 defines the halt codes and indicates whether
a code is relevant to specific VAX processors.

8-5

Table 8-2' Console Halt Codes

VAX Processors
Small Medium Large

Code

Definition

A halt or single-step command was
entered from the console terminal.

A test command was successfully initiated
from the console terminal.

Ctrl-Pwas typed on the console
terminal.

The interrupt stack is not valid
or the system control block (SCB) was
unable to be read.

A CPU double-bus write-error halt has
occurred.

A halt instruction was executed
when the processor was in the kernel
mode.

A halt instruction was executed and
the processor status longword (PSL)
indicated the native mode.

An invalid SCB vector.

SCB vector bits 1:0 is equal to 3.

SCB vector bits 1:0 is equal to 2 and
the user-control store does not exist.

A change mode (CHMx) instruction was
issued from the interrupt stack.

A change mode (CHMx) instruction was
issued while on the interrupt stack.

A change mode (CHMx) instruction was
issued to the interrupt stack.

A change mode (CHMx) instruction was
issued with the SCB vector bits 1:0
not equal to zero.

An SCB physical read error was detected.

8-6· VAX Console Subsystems

VAX Processors
Small Medium Large

Code

Definition

During the powerup sequence, the
restart parameter block was not
located, or the switch that selects
the restart is not in the restart
position.

During the powerup sequence, the
warm-start flag is false or the restart
switch is not enabled.

During the powerup sequence, 64 Kbytes
of valid memory was not located.

During the powerup sequence, a defective
boot ROM existed or the boot ROM is not
installed.

During the powerup sequence, the
cold-start was flag set.

The CPU has halted during the powerup
sequence because of the control panel
switch position.

The console microverify test has failed.

8-7

Console Command Language

The console commands are English-language entries or their acceptable
abbreviations, entered by the operator at the console terminal. The commands are statements typed on the console terminal when the console subsystem is in console I/O mode. A basic command language is used with all
VAX processors. Some commands are restricted to specific processors and
some commands perform slightly different operations with each processor.
The commands are entered into the system by typing a single character in
response to the console prompt. Only one character is necessary to constitute a valid command; however, several commands include qualifiers,
addresses, and count values to define the operation of the command. The
commands that are restricted to a specific processor are defined in separate
sections of this chapter.
Several symbols are used in the command syntax to specify command functions. These symbols enclose numeric values, address locations, data, and
other control functions. They are listed in table 8-3. The uppercase functions within the symbols specify the actual typed characters and the lowercase functions specify a selected value. The leading zeros of address, count,
and data values can be omitted.

Table 8·3· Console Command Symbols
Symbol

Function

[ ]

Brackets surrounding part of an expression indicate that
part of an expression is optional.

{}

Braces surrounding part of an expression indicate that one
or several of the options listed may be selected.

(Sp)

One typed space (space bar).

(count)

A 32-bit hexadecimal count.

(address)

An addressed memory or register location.

(data)

A numeric data value.

(qualifier)

A command modifier that is defined for each command.
All qualifiers are preceded by a slash (I).

(qualifier-list)

More than one qualifier may be typed.

(CR)

Carriage return. A line feed (LF) performs the same
function.

The basic command language is listed and defined in table 8-4.

8-8' VAX Console Subsystems

Table 8-4' Console Command Language
Symbol Command

Operation

Boot

Loads the operating or diagnostic software
into the system from the specified device.

Continue

Continues the program execution after a program halt.

Deposit

Deposits data in a specified register or memory location.

Examine

Examines data from a specified register or
memory location.

Find

Initiates a search of the main memory for
64 Kbytes of valid memory or for the restart
parameter block.

Halt

Stops the processor from executing macroinstructions after completing the current
instruction.

Initialize

Initializes the processor by setting registers
and counters to a specified state.

Load

Loads data from the specified file into
memory.

Microstep

Executes the specified number of
microinstructions.

-----------

Executes the specified number of
macroinstructions.

Repeat

Executes and displays the specified
command.

Start

Starts the execution of a program from a
specified address.

Set

Sets the console parameter to the specified
value.

Test

Executes a self-test program of the console
subsystem.

Unjam

Initializes the system bus.

Binary load/unload Transfers data to or from the specified memory locations (Digital use only).

Indirect

Reads and executes commands from the
specified file.

8-9

Control Characters
In console I/O mode, several control characters on the console keyboard

are used to control the console operation. These control characters are
entered by holding down the Ctrt key and typing a character. The control
characters and their functions are listed in table 8-5.

Table 8-5·· Console Control Characters
Console Character Function

Ctrl-C, Ctrt-P

Initiates the console I/O mode and halts the processor.

Ctrl-U

Ignores all characters typed after the last carriage
return.

Rubout

Deletes the previously typed character.

Ctrl-R

Displays the contents of the input buffer.

Ctr/-O

Terminates the output from the console terminal until
the Ctrl-O character is retyped.

Ctrl-S

Stops the console printer.

Ctrl-Q

Restarts the console printer.

ESC

Reexecutes the last command typed on the console
terminal.

Return

Terminates the typed line.

Errors and Dlegal Characters

Errors and illegal characters typed in the console command string can be
corrected using the delete key on the console terminal keyboard. When the
delete key is pressed, the console displays a backslash (""-) together with
the character being deleted and also displays a (""-) between the last deletion and the next input character. When a command error is detected, the
console responds by typing the following message: ?nn (nn being a code
defining the type of error).
System Restart and Reboot Sequence

All VAX console subsystems can automatically restart the processor or can
reload the operating system software when power is restored after an interruption or when certain conditions occur in the processor operation. The
CPU restart sequence is defined as a "warm-start" and is an attempt to
restart the previously loaded operating system. The bootstrap loading
sequence is defined as a "cold-start" and is an attempt to reload the operating system software from the system load device. If the restart sequence
fails, the bootstrap loading sequence can be automatically initiated.

8-10· VAX Console Subsystems

. VAX·11/72.5 Console Subsystem
The VAX-1l/725 console subsystem allows the user to communicate with
the processor using the console terminal and console command language.
The console subsystem includes a microprocessor-controlled interface that
executes a program that controls the console functions, a console terminal,
two TU58 tape cartridge drives, and a control panel. The console subsystem also includes the following:
• A remote diagnostic (RD) option that enables diagnostic testing of the
system through the remote diagnostic port
• A ROM-resident self-test program that can be invoked at powerup and by
console command
Voltage monitoring circuits that check the dc voltages
Monitoring circuits to test the UNIBUS AC LO signal
User initiated console diagnostics test
• Circuits to automatically reboot the operating system when power is
restored after a power failure
The console interface contains a microprocessor and ROM that stores the
resident part of the console program. It also contains a RAM that stores the
console-based microdiagnostic program and the microdiagnostic monitor
which is loaded from the TU58 tape drive during the diagnostic
operations.
The console terminal can be selected from a series of standard Digital
devices, including the VT100 series and VT200 series of video terminals
and the LA 100 and LA12 printing terminals.
Two TU58 tape cartridge drives are used to load the CPU microcode, boot
the system, load files into physical memory, load the diagnostic software,
and update the operating system software. They also can be used to store
site-specific bootstrap procedures. Both TU58 drives connect directly to
the console subsystem. One TU58 drive is located on the front of the processor cabinet and the remaining TU58 drive is located within the cabinet.
The control panel contains switches and indicators used to select operating
modes and to display the operating conditions of the processor.
The remote diagnostic port allows the testing of the processor operation
from a remote Digital location when the remote diagnostic service has been
purchased.

8-11

Console Modes
The VAX-1l1725 console subsystem operates in program VO mode or in
console I/O mode. In program I/O mode, the console terminal operates the
same as other users' terminals connected to the processor, and characters
typed on the terminal are transferred to the program. When the CPU is not
executing instructions it is halted and the console subsystem is in console
I/O mode. Direct memory access (DMA) transactions can occur in the console I/O mode; however, interrupt requests are not serviced. This prevents
the loss of data during the DMA transaction when the CPU halts. In program I/O mode, the TU58 drive can be used for data storage and retrieval.
System Control Panel
The VAX-1l1725 control panel, located at the front of the CPU cabinet,
contains two switches and three indicators lights as shown in figure 8-l.
Table 8-6 lists the functions of the switches and indicators.
The local/remote switch is a six-position rotary key switch used to control
the power to the processor and to select local or remote mode of
operation.
The auto restart switch is a three-position switch that allows the processor
to be manually or automatically restarted during the powerup sequence.
The three indicator lights provide processor operating information, remote
service information, and dc power status.

Run

DC On

RID

Auto Restart
On
Off

Boot

VAX

11/725

Local

Local
Disable

Standby

Remote
Disable

Off

Remote

Figure 8-1 • VAX-111725 Control Panel

8-12· VAX Console Subsystems

Table 8-6· VAX-ll/725 Control Panel Functions
Switch/Indicator

Function

Local/remote switch Off-Removes power from the processor.
Standby - Disables the processor operation; however,
power is applied to maintain the data in the console,
writable-control store, main memory, and time-ofyear clock.
Local:- In console I/O mode, the console terminal
commands control the system operation. In program
I/O mode the console terminal operates as a user's
terminal and all characters except for Ctrl-P are
passed to the program. The remote service port is
disabled.
Local disable-In console I/O mode, all characters are
ignored. In program I/O mode, all characters are
passed to thS! program. The remote line is disabled.
Remote disable - In console I/O mode, all characters
are ignored. The local terminal is disabled and the
remote line is enabled. In program I/O mode, the
remote line is enabled so the remote terminal can
operate as a user's terminal and all characters are
passed to the program.
Remote- In console I/O mode, the local terminal is
disabled when the remote service connection is established. The local terminal can be enabled by commands from the remote service. The console accepts
and interprets commands from the remote terminal.
In program I/O mode, all characters except Ctrl-P are
passed to the program from the remote terminal or
from the local terminal when it is enabled.

8-13

Switch/Indicator

Function

Auto restart switch

all- The console subsystem halts after loading the
microcode. The processor remains halted after a halt
instruction is executed or power is restored.
On - The console subsystem loads the microcode and
executes a command file that loads the operating system. If a halt condition occurs or if power is restored
after a power failure, the console subsystem will
attempt to restart the operating system except when a
Ctrl-C command causes the halt.
Boot (momentary) - In console I/O mode, the console
subsystem executes the boot command file to load
the operating system.

Run indicator

Lighted when the CPU is in program I/O mode and is
running the main memory program.
Not lighted when the main memory program is halted
and the CPU is in console I/O mode.

DC on indicator

Lighted when all the dc power supply voltages are
within the operating limits.
Lighted intermittently when one or more of the dc
voltages is not within the operating limits.

RID indicator

Lighted when the system is connected to the remote
diagnostic service.
Lighted intermittently during the remote diagnostic
service.

8-14· VAX Console Subsystems

Console Control Characters

The control characters used with the VAX-1l1725 console subsystem are
the same as those listed in table 8-5.
Console Commands

In addition to the console commands available with all VAX processors, the
VAX-111725 includes the microstep command and the directory command.
The unjam, set, and indirect commands are not used. The console commands and command syntax are described as follows:
• Binary load command - The binary load command causes the console to
load binary data into physical memory starting at the specified location.
The console processes the command and, if the checksum information is
correct, a prompt is issued to the console terminal followed by the binary
data requested. A new checksum value is then calculated and processed.
This command is specified when bit 31 of the count value is zero. The
remaining bits specify the number of bytes to be transferred.

Syntax: X(SP)(address)(SP)(count)(CR)
(checksum)
-address: the starting address of the load sequence.
-count: the number of bytes to be transferred.
-checksum: the two's complement checksum of the command string or
binary data
• Binary unload command- The binary unload command causes the console to unload the binary data from a specified location in physical memory starting at the specified location. This command is specified by a
count value with bit 31 set. The remaining bits specify the number of
bytes to be transferred.

Syntax: X(SP)(address)(SP)(count)(CR)
(checksum)
- address: the starting address of unload sequence.
-count: the binary number of bytes to be transferred plus one byte.
-checksum: the two's complement checksum of the command string or
binary data.
• Boot command - The boot command causes a boot command file to be
read from one of the TU58 console drives, loads the file into a 64-Kbyte
block of memory, and executes the bootstrap operation. The boot command is used to load the operating system software and diagnostic programs from the mass storage device.

8-15

Syntax: BOOT[ <SP)<device-select)] [<SP)<device-name)<CR)
-device-select: DDO = external TU58 drive. DDI = internal TU58 drive.
If not specified, the device is the TU58 drive previously used to load the
microcode.
-device-name: DQn = the unit number of the R80 or RL02 disk drive
that contains the system disk. If not specified, the DEFOO.CMD file is
read from the specified device and executed .
• Continue command - The continue command restarts the execution of a
halted program at the address currently contained in the program
counter if the CPU clock is operating. If it is not operating because of a
microcode break in program I/O mode, the clock is started and the console enters program I/O mode.

Syntax: CONTINUE<CR)
• Deposit command-The deposit command enables data to be written into
a specified memory or register address. If an address or a data qualifier is
not specified, the address and data values from the previous examine or
deposit command are used.

Syntax: DEPOSIT[ <qualifier-list) ]<SP)<address)<SP)<data)<CR)
-qualifier-list (data length): IBYTE = one byte, IWORD = two bytes,
ILONG = four bytes.
-qualifier-list (repetition): In:(count) (the number of locations to be
examined plus one).
-qualifier-list (address): IVIRTUAL = virtual memory, IPHYSICAL =
physical memory, IINTERNAL = internal processor registers,
IGENERAL = general purpose registers RO through Rll, ICONTROL
= writable-control-store (WCS) location, IMACHINE = machine
dependent internal registers, IUCODE = console microprocessor
memory.
-address (The symbolic address at which the data will be deposited):
nnnnnnnn = a hexadecimal address, PSL = processor status
longword, PC = program counter, SP = stack pointer, Rn = a general
register, + = the location following the last referenced location in an
examine or deposit command, - = the location preceding the last location referenced in an examine or deposit command, * = the location
last referenced in an examine or deposit command, (@) = the location
addressed by the last location referenced in an examine or deposit
command.
-data: nnnnnnnn = from one to eight hexadecimal digits to be deposited at the specified address.

8-16· VAX Console Subsystems

• Examine command- The examine command enables the contents of a
specified memory location or register to be examined. If an address is not
specified, the address from the previous examine or deposit command is
used.
Syntax: EXAMINE[(qualifier-list)](SP)(address)(CR)
- qualifier-list: the same as described for the deposit command.
-address: a hexadecimal or symbolic address from which the data will be
examined. (Refer to the deposit command.)
• Directory command - The directory command displays the directory of
the specified TU58 tape drive.
Syntax: DIRECTORY(SP)(device-select)(CR)
-device-select: DDO = TU58 tape drive 0, DDl = TU58 tape drive 1.
• Halt command - The halt command resets the console default conditions
after the CPU is halted by the halt codes defined in table 8-2.
Syntax: HALT(CR)
• Initialize command - The initialize command starts the microcode, initializes the TU58 controller and processor, and loads the starting address
of the 64-Kbyte block of memory into the stack pointer.
Syntax: INITIALIZE(CR)
• Load command - The load command enables data to be written into a
memory location from a specified file. If a qualifier is not specified, the
data is loaded into physical memory starting at address zero.
Syntax: LOAD[(qualifier-list)](SP)(filename)(CR)
-qualifier-list: IS = the starting address of the memory location, Ie
writable control store, IP = physical memory.
- filename: the abbreviation of the filename.
• Microstep command-The microstep command causes the processor to
execute the specified number of microinstructions. If a count is not specified, one microinstruction will be executed.
Syntax: MICROSTEP[ (SP)(count) ](CR)
- count: a decimal count of the number of instructions to be performed.
Next command- The next command causes the processor to execute the
specified number of macroinstructions. If a count is not specified, one
macroinstruction will be executed.
Syntax: NEXT[(SP)(count)](CR)
- count: a decimal count of the number of instructions to be performed.

8-17

• Repeat command - The repeat command causes the specified command
to be repeated until manually stopped by a typing a Ctrl-C, Ctrl-P, or a
Break character on the console terminal.

Syntax: REPEAT(SP)(command)(CR)
- command: a deposit, examine, or initialize command .
• Start command- The start command initiates the execution of programs
that do not require the operating system or the diagnostic supervisor.
These programs are previously loaded into main memory. If an address is
not specified, the current PC address is used.

Syntax: START[ (SP)(address) HCR)
-address: the hexadecimal address of the program.
Test command- The test command initiates the diagnostic test by locating the ENKAA.EXE program on TU58 drive 0 or drive 1 and by loading
the program into memory.

Syntax: TESTICR)
Console Command Errors
Console commands that are entered and cannot be processed will be
ignored by the console subsystem and an error code will be displayed on
the console terminal. The error code consists of two digits preceded by a
question mark (?nn). The condition causing the error must be corrected
before the command can be reissued. Table 8-7 lists the console command
errors codes and their definitions.
Table 8-7 • Console Command Error Codes
Code

Description

?1O

An illegal general-purpose register number.

? 11

An illegal access of an internal processor register.

?19

Reference to the next location was preceded by an examine or
deposit command to an internal processor register or to the processor status longword.

?20

An access control violation, translation-not-valid fault, or machine
check occurred during a read or write operation.

?30

A binary transfer checksum error.

?33

Unrecognized bootstrap loading device.

- - - - - - -

8-18· VAX Console Subsystems

Bootstrap Loading Sequence
The bootstrap loading sequence is controlled by the console subsystem and
is used to load the operating system into the CPU. The bootstrap loading
sequence initializes the CPU and executes a bootstrap command file to load
the operating system into processor memory from the specified mass storage device. The sequence is initiated by the following conditions:

• By setting the auto restart switch to the boot position
• During a powerup sequence when the auto restart switch is in the on
position
• By entering the boot command while in console 1/0 mode
• By executing a halt instruction when the processor is in kernel mode and
the auto restart switch is in the on position
• By executing a move to processor register (MTPR) instruction to the console register that invokes the bootstrap sequence
• When the restart procedure fails and the auto restart switch is in the on
position
During the bootstrap sequence, the console subsystem checks the bootstrap flag, initializes the CPU, loads the address plus a value of 200 of the
64-Kbyte block of valid memory into the stack pointer, determines the CPU
options that are installed, and executes the default bootstrap command file
(DEFBOO.CMD). The default file loads the operating system from the specified mass storage device. If the bootstrap flag is set during the powerup
sequence or when the boot command is executed, the flag will be cleared
and then set. If the bootstrap flag is set during the remaining conditions
that initiate the bootstrap operation, the CPU normally will halt. The bootstrap sequence is manually initiated by the following procedures.
1. Install the tape cartridge containing the bootstrap program into the
TU58 tape drive
2. Apply power to the console terminal
3. Set the auto restart switch to the on position
4. Set the local/remote switch to the local or local disable position
The terminal then displays the following message:
CONSOLE
VERSION XX.XX

8-19

• SYSTEM RESTART PROCEDURE
When the console subsystem gains control of the VAX-1l1725 processor
following a power restoration or CPU halt condition, it examines the state
of the auto restart switch. If the switch is in the off position, the console
remains in console I/O mode with the processor halted. If the auto restart
switch is set to the on position, the console searches through physical memory, starting at location zero, for a valid restart parameter block (RPB). If
the auto restart switch is in the off position, the console awaits further
commands.
A valid RPB consists of four longwords that start on a page boundary. The
first longword contains the address of the RPB. The second longword contains the address of the restart routine. The third longword contains a
checksum value of the restart code. And the fourth longword contains
status information.

If a valid RPB exists, the console examines bit 0 of the fourth longword.
When bit 0 is set, it indicates that a restart attempt was previously initiated
and failed. The console subsystem then executes the default command file
(DEFBOO.CMD) to reboot the system. If bit 0 is clear, the console subsystem sets the bit and loads the RPB address plus a value of 200 into the stack
pointer. It also loads general purpose register R12 with a value that indicates the cause of the restart. The restart routine, located at the address
specified by the second longword, is then initiated.

8-20· VAX Console Subsystems

. VAX-1l1730 Console Subsystem
The VAX-11/730 console subsystem performs similar functions and
includes the same console hardware as the VAX-lll725 console
subsystem.
The VAX-1l/730 processor includes two TU58 tape cartridge drives. One
drive is located on the front of the prQcessor cabinet and the remaining
drive is in the cabinet. Both TU58 tape drives are directly connected to the
console subsystem and can be used to perform microlevel and macrolevel
diagnostics when some system components are not operating properly.

Console Modes
The operation of the console subsystem of the VAx-1l1730 processor in
console I/O mode and program 1/0 mode is the same as the VAX-1l/725
console subsystem.
System Control Panel
The VAX-l1/730 control panel, shown in figure 8e2, is on the front of the
CPU cabinet and contains the two switches and four indicators used to
monitor and control the system operation. The functions of the switches
and indicators are listed in table 8-8.
The locallremote switch is a six-position rotary key switch used to control
the power to the unit and to select the local or remote modes of
operations.
The auto restart switch is a three-position slide switch that controls the
automatic restart of the system and the manual bootstrap loading
functions.
Three red indicator lights provide information on the processor operation,
dc power status, and remote diagnostic service.

(

RUN

De ON

BATT

RID

(
)

(

AUTO RESTART
OFF

CJD

BOOT

VAX 11/730

LOCAL

LOC DSBL

~ ~.REMDSBL
OFF

Figure 8-2 • VAX-1l1730 Control Panel

REMOTE

8-21

Table 8-8' VAX-1l1730 Control Panel
SwitchlIndicator

Function

Local/remote switch Off-Removes power from the processor.
Standby - Disables the processor operation; however,
power is applied to maintain the data in the console,
writable-control store, main memory, and time-ofyear clock.
Local- In console 1/0 mode, the console terminal
commands control the system operations. In program
1/0 mode, the console terminal operates as a user's
terminal and all characters except for Ctrl-P are
passed to the program. The remote service port is
disabled.
Local disable - In console VO mode, all characters are
ignored. In program Vo mode, all characters are
passed to the program. The remote line is disabled.
Remote disable-In console Vo mode, all characters
are ignored. The local terminal is disabled and the
remote line is enabled. In program 1/0 mode, the
remote line is enabled and the remote terminal can
operate as user's terminal and all characters are
passed to the program.
Remote - In console I/O mode, the local terminal is
disabled when the remote service connection is established. The local terminal can be enabled by commands from the remote service. The console accepts
and interprets commands from the remote terminal.
In program 1/0 mode, all characters except Ctrl-P are
passed to the program from the remote terminal or
from the local terminal when it is enabled.
Auto restart switch

Off-The console halts after loading the microcode.
The processor remains halted after a halt instruction
is executed or power is restored.

On - The console subsystem loads the microcode and
executes a command file that loads the operating system. If a halt condition occurs or if power is restored
after a power failure, the console subsystem will
attempt to restart the operating system except when a
Ctrl-C command causes the halt.
Boot (momentary) - In the console 1/0 mode, the console subsystem executes the boot command file to
load the operating system.

8-22· VAX Console Subsystems

Run indicator

Lighted when the CPU is in program va mode and is
running the main memory program.
Not lighted when the main memory program is halted
and the CPU is in console va mode.

DC on indicator

Lighted when all the dc power supply voltages are
within the operating limits.
Lighted intermittently when one or more of the dc
voltages is not within the operating limits.

RID indicator

Lighted when the system is connected to the remote
diagnostic service.
Lighted intermittently during the remote diagnostic
service.

Batt indicator

Reserved (no operation).

Console Control Characters

The control characters used with the VAX-1l/730 console subsystem are
the same as those listed in table 8-5.
Console Commands

The console commands used with the VAX-1l/730 console subsystem are
the same as those described for the VAX-1l/725 console subsystem.
Console Command Errors

Console commands that are entered and cannot be processed will be
ignored by the console subsystem and an error code will be displayed on
the console terminal. The error code consists of two digits preceded by a
question mark (?nn). The condition causing the error must be corrected
before the command can be reissued. Table 8-7 lists the console command
errors codes and their definitions.
Bootstrap Loading Sequence

The bootstrap loading sequence of the VAX-1l/730 processor is initiated
by the same conditions and performs the same operations as described for
the VAX-1l1725 processor.
System Restart Procedures

The system restart procedures for the VAX-lU730 processor are the same
as those described for the VAX-1l1725 processor.

8-23

. VAX-1l1750 Console Subsystem
The VAX-1l1750 console subsystem includes an LAl20 console terminal, a
remote diagnostic port, a TU58 cartridge tape drive used as a system bootstrap loading device, and a control panel. The control panel is on the front
of the processor unit- The VAX-1l1750 console subsystem operates with a
subset of the console command language used with the larger VAX
systems.
The console interface contains a microprocessor that allows the testing of
the system components by console-based microdiagnostics or through a
remote testing facility. Some of the diagnostic aids related to the console
subsystem are as follows:
• A remote diagnostic (RD) option that allows diagnostic testing of the
processor from a remote Digital facility
• ROM-resident self-test that can be invoked at powerup or by console
command
• Voltage monitoring circuits that check dc voltages
• Monitoring circuits to check the UNIBUS AC LO signal
• Allows user-initiated diagnostic programs to be performed
The TU58 tape cartridge drive is on the front of the processor cabinet. In
console I/O mode, the TU58 drive can be used to load the microcode, to
load files in physical memory, and to load diagnostic software and updates
to the operating system. It also can be used to store site-specific bootstrap
procedures.
Console Modes
The VAX-l1l750 console subsystem operates in three separate modes: program 1/0 mode, console I/O mode, and remote diagnostic (RD) mode. One
mode will always be enabled when power is applied to the processor. In
program I/O mode, the console terminal operates as a user's terminal and
characters typed on the terminal are passed to the processor. In console 1/0
mode, the console subsystem interprets the commands typed on the console keyboard and performs the functions specified by the commands. In
the remote diagnostic mode, the remote terminal controls the processor
operations.

8-24· VAX Console Subsystems

System Control Panel

The VAX-1l1750 control panel, located on the front of the processor cabinet, contains four switches and seven indicator lights. The switches are
used to select the operating modes and to control the console operation,
and the lights indicate the state of the processor and the remote diagnostic
service. Figure 8-3 shows the location of the switches and indicators and
table 8-9 lists their functions.
The local/remote switch is a five-position rotary key switch used to control
the system power and to select the local and remote modes of operation,
depending on the mode of operation of the console subsystem.
The power on action is a four-position rotary switch that controls the CPU
on a powerup sequence. The switch can be set to restart the system automatically when the power is-restored after a power failure.
The boot device switch is a four-position rotary switch that is used to select
one of four devices from which the system will be bootstrap loaded. The
VAX-111750 CPU can contains up to four ROMs, each containing the code
required to bootstrap a device. The switch selects which of the four ROMs
that will be used to bootstrap a device.
The auto restart switch is a three-position switch that controls the system
during the powerup sequence by enabling the automatic boo~strap loading
function.
The remote diagnostic indicators are operative only on systems with the
remote diagnostic option. The back-lighted words are illuminated during
the remote diagnostic procedures.

REMOTE 0
RD TEST

RD FAULT
RD CARRIER

Figure 8-3 • VAX-ll/750 Control Panel

8-25

Table 8·9· VAX·ll/750 Control Panel Functions
Switch/Indicator

Function

Local/remote switch

all- Removes the power from the CPU. Battery
backup power to the memory and the time-ofyear clock is present.
Secure-Disables the console commands. The
remote diagnosis unit and the reset switch functions are disabled.
Local- The CPU responds to console commands and the remote diagnosis unit is
disabled.
Remote secure- The console commands are
ignored. The remote line replaces the console
terminal, and the functions of the reset switch
are disabled. The remote diagnosis module
cannot be used to identify the source of system
failures.
Remote- The console functions are enabled
and can be activated only from the remote line;
however, the remote line cannot return control
to the local terminal.

Power on action switch

Boot - Initiates the bootstrap loading sequence
from the device selected by the boot device
switch.
Boot restart- The system checks for a valid
restart parameter block. If a valid block is
found, a restart sequence is initiated. If the
restart sequence is not successful, a bootstrap
sequence is invoked.
Halt - Halts the processor operation when in
console mode.
Halt restart- The system checks for a valid
restart parameter block. If a valid block is
found, a restart sequence is initiated. If a valid
block is not found or the restart sequence is
unsuccessful, the system halts.

8-26· VAX Console Subsystems

SwitchlIndicator

Function

Boot device switch

A - Initiates the bootstrap loading sequence
from the TU58 cartridge tape drive.

B - Initiates the bootstrap loading sequence
from the RK07 disk drive.
C - Initiates the bootstrap loading sequence
from the RL02 disk drive.
D- Initiates the bootstrap loading sequence
from a MASSBUS device.

Reset switch (momentary) Activates a system powerdown sequence followed by a powerup sequence unless the local/
remote switch is set to the secure position. The
system comes up in the state selected by the
power on action switch. The reset switch is used
if the system does not respond to console
commands.
Power indicator

Lighted green to indicate that the de power is
applied to the CPU.

Run indicator

Lighted green to indicate that the CPU is in program VO mode.

Error indicator

Lighted red brightly to indicate that the CPU is
stopped because of an unrecoverable, controlstore parity error. Because console commands
are ignored, the reset switch must be used to
clear the error.
Lighted red dimly to indicate that the CPU is
functioning normally.

Remote D indicator

Lighted green to indicate that the local/remote
switch is set to one of the two remote positions.

RD Carrier indicator

Lighted green to indicate that the remote diagnostic center has established connection with
the console subsystem.

RD Test indicator

Lighted amber to indicate that diagnostic tests
are in progress.

RD Fault indicator

Lighted red to indicate that a fault has been
detected in the remote diagnosis module.

8-27

Console Control Characters

The VAX-1l1750 console subsystem responds to the Ctrl-P, Ctrl-U, and
Ctrl-D control characters. When the Ctrl-P character is typed, the console
subsystem enters the console 1/0 mode, the CPU halts, and a halt message is
displayed on the console terminal. Typing the Ctrl-P character when the
console subsystem is in console 110 mode causes the console default to be
reinitialized and displays the halt message on the console terminal. When
the Ctrl-U character is typed, the console subsystem ignores all characters
typed since the previous carriage return. A Ctrl-D character typed on the
console terminal causes the console subsystem to enter the remote diagnostic mode, if the remote diagnostic module is installed.
Console Commands

The VAX-1l1750 console subsystem uses the basic console command set
except for the load,find, set, repeat, and unjam commands. It also includes
a test command that initiates the microverify routine and initializes the
processor.

• .Binary load command-The binary load command causes the console to
load binary data into physical memory starting at the specified address. A
count value with bit 31 cleared specifies the binary load command, and
the remaining bits specify the number of bytes to be transferred. When
the console has accepted the command, the number of bytes specified by
the count value plus one byte is sent. The last byte is a two's complement
checksum of all the data transferred and is calculated by the console. If
the checksum information is correct, a prompt is issued to the console
terminal, followed by the binary data requested. A new checksum value is
calculated and processed.
Syntax: X(SP)(address)(SP)(count)(CR)(
checksum)
- address: the starting hexadecimal address of the load sequence.
-count: the number of bytes to be transferred plus one byte.
-checksum: the two's complement checksum of the command string or
binary data.

8-28' VAX Console Subsystems

• Binary unload command - The binary unload command causes the console to unload the binary data from physical memory starting at the specified address. A count value with bit 31 set specifies the binary unload
command and the remaining bits specify the number of bytes to be transferred. The console subsystem processes the command and checksum
value . .If the checksum value is correct, a prompt is issued to the console
terminal followed by the number of bytes requested. A second checksum
value is then calculated. An error in the checksum value results in an
error message sent to the console terminal.

Syntax: X(SP)(address)(SP)(count)(CR)
(checksum)
-address: the starting hexadecimal address of the unload sequence.
-count: the binary number of bytes to be transferred.
-checksum: the two's complement checksum of the command string or
binary data.
• Boot command - The boot command loads the operating system and
diagnostic software into memory from the specified mass storage device.
The microverify test program normally is performed at the beginning of
the bootstrap loading sequence. At the completion of the bootstrap
sequence, the console subsystem enters program 1/0 mode.

Syntax: BOOT[(qualifier-list)](SP)[(device-name,channel,num)](CR)
-qualifier-list: IX = inhibit the microverify test, In = a hexadecimal
number that specifies the boot control flags.
-device-name (a device code that specifies the device from which the
program will be loaded): DL = RL02 disk drive, DM = RK06 or RK07
disk drive, DB = RP04, RP05, RP06, RP07, or RM03 disk drives, DD =
TU58 tape drive.
-channel (an 1/0 channel adapter): A = 1/0 channel A, B = 110 channel B, C = 110 channel C.
- num: the number assigned to the device
• Continue command - The continue command restarts the execution of a
halted program at the address currently contained in the program
counter if the CPU clock is operating.

Syntax: CONTINUE(CR)

8-29

• Deposit command - The deposit command enables data to be written into
a specified memory or register address. If an address or data qualifier is
not specified, the address and data values from the last examine or deposit
command are used.

Syntax: DEPOSIT[ (qualifier-list) ](SP)(address)(SP)(data)(CR)
-qualifier-list (data size): /BYTE = one byte, /WORD = two byte~,
/LONG = four bytes.
-qualifier-list (address space): /VIRTUAL
virtual memory,
/PHYSICAL = physical memory, /INTERNAL = internal processor
registers,/GENERAL = general purpose registers RO through R15.
-address (the symbolic address at which the data will be deposited):
nnnnnnnn = from one to eight hexadecimal digits, P = processor
status longword, * = the address referenced in the previous deposit or
examine command, + = the address following the address referenced
in the previous deposit or examine command.
-data: nnnnnnnn = from one to eight hexadecimal digits.
• Examine command- The examine command permits reading of a specified memory location or register. If an address or data-length qualifier is
not specified, the physical address and data length value of the previous
deposit or examine command are used.

Syntax: EXAMINE[(qualifier-list)](SP)(address)(CR)
-qualifier-list: (refer to the deposit command).
-address (the symbolic address from which the data will be examined):
(refer to the deposit command).
• Halt command- The halt command resets the console default conditions
after the CPU is halted by a halt code (defined in table 8-2).

Syntax: HALT(CR)
• Initialize command - The initialize command initializes the processor to a
specified condition, clears and enables the cache memory and translation
buffer, clears the .program counter, and enters the value of 041FOOOO
(hexadecimal) into the program counter.

Syntax: INITIALIZE(CR)
• Next command- The next command causes the processor to execute one
interrupt stack pointer (ISP) level instruction.

Syntax: NEXT(CR)

8-30· VAX Console Subsystems

• Start command- The start command initiates the execution of programs

that do not require the operating system or diagnostic supelVisor. The
programs start at the address specified, or at the current program counter
address if no address is entered.
Syntax: START(SP)(address)(CR)
-address: from one to eight hexadecimal digits.
• Test command- The test command initiates the microverify program and

initializes the processor. If an failure is detected, a single-error character
is displayed on the console terminal and the processor halts in console
110 mode. An error and halt code is then dispayed on the console
terminal.
Syntax: TEST(CR)

Console Command Errors
Console commands that are entered and cannot be processed will be
ignored by the console subsystem and an error code will be displayed on
the console terminal. The error code consists of two digits preceded by a
question mark (?nn). The condition causing the error must be corrected
before the command can be reissued. Table 8-7 lists the console command
errors codes and their defmitions. Error codes 10 and 19 are not used in
the VAX-1l1750 console subsystem and an additional error code 34 is used
to indicate an illegal channel adapter.
Bootstrap Loading Sequence
The bootstrap loading sequence is controlled by the console subsystem and
is used to load the operating system into the cpu. The bootstrap loading
sequence initializes the cpu and executes a bootstrap command me to load
the operating system into processor memory from the specified mass storage device. The bootstrap loading sequence is initiated by one the following conditions:
• When power is initially applied or when power is restored after a power
failure and the power on action switch is in the boot position
• By pressing the reset pushbutton with the power on action switch in the
boot position
• By entering the boot command while in console 1/0 mode
• By executing a halt instruction when the processor is in kernel mode and
the power on action switch is in the boot position
• By executing a move to processor register (MTPR) instruction to the console register that invokes the bootstrap operation
• By a failure of the restart sequence when the power on action switch is in
the boot restart p<'>sition

8-31

During the bootstrap sequence, the console subsystem initializes the CPU,
locates a 64-Kbyte block of good memory, and transfers the address of that
memory to the device ROM. Block zero of the bootstrap code from the
device specified is then transferred to the first page of memory under control of the device ROM. The bootstrap code uses the device ROM as a
callable driver for the device and the ROM transfers the files required to
start the system operation.
The bootstrap sequence is initiated manually by the following procedures:
1. Apply power to the console terminal.
2. Set the power on action switch to halt position. The following message
will be displayed on the console terminal:

%%
0000000016

»)
3. Check that the operating system disk pack is in drive 0 and the ready
indicator on the drive is lighted.
4. Set the boot device switch to the position corresponding to the system
device.
5. Set the power on action switch to boot restart position.
6. Press the restart switch
During the bootstrap sequence, the console subsystem performs the following operations. The first two steps of the sequence will not be performed during a powerup condition or when the restart pushbutton is
pressed and the power on action switch is in the boot position.
• Clears the cold-start flag and performs the microverify test.
• Initializes the processor status longword.
• Locates a 64-Kbyte block of unused memory.
• Initializes the UNIBUS.
• Loads and validates the first 128 UNIBUS map registers to address the 64Kbyte block of memory.
• Loads the contents of the boot ROMs into memory.
• Transfers the address of the memory location to the device ROM.
• Checks the cold-start flag. If the flag is set, the operation halts. If the flag
is clear, the program sets the flag.
• Loads the input arguments to be used by the device ROM code and operating system.
• Selects the boot ROM indicated by the boot device switch.

8-32· VAX Console Subsystems

• SYSTEM RESTART PROCEDURE
When the console subsystem gains control of the VAX-1l1750 processor
following a power restoration, activation of the reset switch, or CPU halt
condition, it examines the state of the power on action switch. If the switch
is set to either the halt restart or boot restart position, the console subsystem searches for a valid restart parameter block (RPB) and attempts to
restarts the CPU. If the RPB is not located, the console subsystem- either
halts or performs a bootstrap operation, depending on the position of the
power on action switch.
A valid RPB consists of four longwords that start on a page boundary. The
first longword contains the address of the RPB. The second longword contains the address of the restart routine. The third longword contains a
checksum value of the restart code. And the fourth longword contains
status information.

If the RPB is located, the console examines bit 0 of the fourth longword.
When bit 0 is set, the console subsystem will halt or perform a bootstrap
loading sequence, depending on the position of the power on action switch.
If bit 0 is clear, the console subsystem sets bit 0 and loads the RPB address
plus a value of 200 into the stack pointer. It also loads general purpose
register R12 with a value that indicates the cause of the restart. The restart
routine, located at the address specified by the second longword, is then
initiated.

8-33

. VAX-11/780 Console Subsystem
The VAX-l 11780 console subsystem is controlled by an LSI-11 microprocessor and is the interface between the CPU and the console terminal,
remote diagnostic port, control panel, and the RXOI console load device.
The console subsystem allows the user to communicate with the processor
through the console terminal and console command language. The microprocessor performs diagnostic tests and simplifies the bootstrap operations
and system initialization. Some of the features of the console subsytem are
as follows:
• The console terminal is a standard ASCII device that can be used as an
operator console or user's device.
• The console command language is a powerful, easy-to-use, debugging
tool.
• The subsystem allows diagnostics programs to be performed to from a
remote Digital service facility.
• The subsystem allows unattended restart of the CPU after a power
interruption.
The console subsystem includes an LSI-11 microprocessor, a console interface, a console terminal, a remote diagnostic port, an RXOI floppy disk
drive, and a control panel. The subsytem also includes two serial-line
interfaces-one for the console terminal and one for the remote diagnostic
port.
The LSI-11 microprocessor together with a 4K by l6-bit RAM controls the
console subsytem operation. The console interface includes a 4K by l6-bit
ROM and controls the transfer of information between the CPU and the
devices connected to the console subsystem. It also monitors and controls
the operation of the switches and indicators on the control panel.
The console terminal is an LA120 send and receive printing terminal with
keyboard. The terminal can be used as a diagnostic terminal or as an operator's terminal during normal system operation. The RXOI is an 8-inch,
floppy-disk drive that serves as a console load device for console and diagnostic programs.
The remote diagnostic port enables diagnostic maintenance to be performed on the system from a remote Digital field service location when the
remote diagnostic option is include.

8-34' VAX Console Subsystems

Console Modes
The VAX-1l1780 console subsystem operates in program 110 mode or console command mode. In program 1/0 mode, the characters typed on the
console tertninal are passed to the VAX-1l1780 software and information
from the software is transferred directly to the console terminal. In console
command mode, the console subsystem interprets the console commands
and characters and performs diagnostic and maintenance functions.

The VAX-ll/780 processor can be either operating or halted during the
two console modes. When operating, the processor executes instructions
and processes program and device interrupts. When halted by an internal
system error or by a halt command from the console terminal, the processor responds to commands issued from the console terminal.
The functions of the console subsystem for each mode are as follows:

· In program 1/0 mode with the processor operating, characters from the
console terminal are transferred through the console subsystem to the
processor for interpretation and processor information is transferred
directly to the console terminal. The console terminal operates as a user's
terminal.

· In console command mode with the processor operating, the microprocessor interprets some console characters and commands from the console
terminal to stop or continue the processor operation or to change the
console mode.

In program 1/0 mode with the processor halted, no system functions can
be performed.

· In console 1/0 mode with the processor halted, the console commands
from the console terminal control the system operation. Commands can
be used to start and stop the operating system, to modify and display
memory and internal register information, to control the processor clock
!,lnd to initiate diagnostic programs.
.
System Control Panel
The VAX-1l1780 control panel, located on the front of the CPU cabinet,
contains three switches and four indicator lights used to monitor and control the processor operation. The functions of the switches and indicators,
shown in figure 8-4, are listed in table 8-10.

The local/remote switch is a five-position rotary key switch used to control
the power and to select the mode of system operation.
The boot switch is a momentary switch that initiates the bootstrap program
to load the operating system into main memory.

8-35

The auto restart switch controls the automatic restart of the processor after
a power failure or when an internal error condition has halted the
processor.
The four indicator lights display the operating conditions of the processor,
the status of the power supply, and the status of remote diagnostic service.

CONSOLE CONTROL PANEL

AUTO
RESTART

OOFF~
-

LOCAL

LOCA~ REMOTE

DISABLE

OFF

REMOTE

BOOT

Figure 8-4· VAX-ll/780 Control Panel

Table 8-10· VAX-1l1780 Control Panel Functions
SwitchlIndicator

Function

Local/remote switch

o/!- Removes the power from the CPU. The
battery backup power for the time-of-year clock
and memory is operating.
Local disable - Disables console VO mode and
the remote diagnostic access. CPU does not
respond to commands from the console
terminal.
Local- Enables the console 1/0 mode, and the
CPU responds to commands from the console

terminal. The remote diagnostic access is
disabled.
Remote disable-Enables console 1/0 mode,
and the CPU responds to commands from the
console terminal. The remote diagnostic access
is enabled.
Remote-Enables console 1/0 mode and the
remote diagnostic access. The CPU responds to
commands from a remote terminal and console
commands are ignored.

8-36· VAX Console Subsystems

Auto restart switch

On-The CPU is restarted automatically following a power failure or error halt condition.
Off-Disables the automatic restart of the CPU
and the console prompt is displayed on the console terminal following a power failure or error
halt condition.

Boot switch (momentary) Off-Disables the console bootstrap sequence.

On - When pressed, the operating system is
bootstrapped and the console enters program
I/O mode.
Attn indicator

Lighted red to indicate that CPU is halted and
the console subsystem is in console I/O mode.

Run indicator

Lighted green to indicate that the console subsystem is in program I/O mode and the CPU is
running.

Power indicator

Lighted green to indicate that the + 5 V dc
power is applied to the CPU and the local/
remote switch is not in the all position.

Remote indicator

Lighted red to indicate that the CPU is halted
and access to the remote diagnostic port is
enabled.

Console Control Characters

When the console subsystem is in console I/O mode, special characters
typed on the console terminal will control the functions of the console I/O
mode. The processor states, console modes, and interaction of the software
are shown in figure 8-5.

8-37
VAX-ll/780
CPU

CIB

VAX-ll
SOFTWARE

PASSING ASCII CHARACTERS

LSI
PROGRAM
110
MODE

"SET
TERMINAL
PROGRAM"

"CONTINUE"
"HALT"

CTRL-P

HALT STATE
(CONSOLE
COMMAND MODE
CONSOLE WAIT
LOOP)

I~"--------------I.~I

CONSOLE COMMAND LANGUAGE
(e.g. EXAMINE)

CONSOLE
110
MODE

Figure 8-5 • VAX-111780 Operating Mode Interactiol)

The console command mode can be entered from the program I/O mode
by typing Ctrl-P on the console terminal. The program 1/0 mode can be
entered from console command mode by the set terminal program command. When the CPU is executing instructions, a subset of console commands is recognized and executed. The functions that the console can
perform are limited to those that do not require a direct response from the
CPU, except for the halt instruction. The console software will not transfer
commands to the executing CPU software and will not accept output from
the executing CPU software. The console commands that can be used are
clear, done, examinelV bus, halt, help, set, show, and wait. When the CPU is
halted and the microprocessor is in console I/O mode, all the functions of
the console command set are available and the following operations can be
performed:
• Initiate and terminate the execution of the CPU software.
• Display and modify memory elements including main memory, input/
output, general purpose register, and process register address space.
• Control the CPU clock to provide single-step clock modes for use in basic
hardware or program development.
• Initiate macrodiagnostics and microdiagnostics.

8-38' VAX Console Subsystems

Console Help Files and Commands
Three online help files are included with the console subsystem software
and provide a convenient reference for the user. A description of the help
files follows:

• A help file, which contains a description of all console commands.
• An abbreviation help file, which contains a list of abbreviations and rules
for the console command !,mguage.
• An error help file, which contains a list of all error messages for the
console command language.
The following commands are used to clear errors, display default conditions, and halt the execution of the command file.
• The quad clear command clears uncorrectable error correction codes.
• The show command displays the default settings of the data length,
address type, radix, and data inputs and outputs. It is also used to display
the terminal fill character count and CPU status including the run and
halt states and the current clock mode setting.
• The wait command is used to halt the execution of the command file
until the program running in the CPU is completed. The' console then
resumes execution of the command file. If the CPU program is halted
before completion, the remainder of the command file is not executed.
Typing the Ctrl-C character halts the execution of the remainder of the
command file.
Console Commands
The command set used with the VAX-l1/7BO console subsystem is as
follows:

• Boot command - The boot command initiates the bootstrap sequence to
load the operating system program or the diagnostic program into memory from a mass storage device.

Syntax: BOOT[(device-name}](CR}
-device-name: DDn = a device designator consisting oftwo letters and a
number assigned to the mass storage device that contains the program
to be loaded.
Continue command - The continue command restarts the execution of a
halted program at the address currently contained in the program
counter and enters program lIO mode.

Syntax: CONTINUE(CR}

8-39

• Deposit command - The deposit command enables data to be written
into a specified memory location or register. If qualifiers are not specified, the data and address values of the set default command are used.
Syntax: DEPOSIT [(qualifier-list) ](SP)(address)(SP)(data)(CR)
-qualifier-list (data length): IBYTE = one byte, IWORD = two bytes,
ILONG = four bytes, IQUAD = eight bytes.
-qualifier-list (address space): !VIRTUAL
virtual memory,
IPHYSICAL = physical memory, IINTERNAL = internal processor
register, IGENERAL = general purpose registers RO through PC, I
IDBUS = ID bus register, IVBUS = V bus register.
-address (the symbolic address at which the data will be deposited): PSL
= processor status longword, PC = program counter, SP = stack
pointer, Rn = general purpose register, + = the location following the
last location referenced in a deposit or an examine command, - == the
location preceding the last location referenced in a deposit or an examine command, * = the location last referenced in a deposit or an examine command, @ = the address represented by the last location
referenced in a deposit or an examine command.
-data: a hexadecimal value to be deposited at the specified address.

• Examine command - The examine command enables the contents of a
specified memory location or register to be read and displayed on the
console terminal. If an address qualifier is not specified, the address from
the set default command is used.
Syntax: EXAMINE [(qualifier-list) ](SP) [(address) ](CR)
-qualifier-list: the same as the deposit command.
-address (a symbolic address from which the data will be examined): the
same as the deposit .command.
• Halt command - The halt command stops the operation of the CPU and
completes the execution of the instruction in process when the halt command was entered.
Syntax: HALT(CR)
• Indirect command- The indirect command causes the console to access a
specified file a~d to begin executing console commands from the file.
Syntax: @ (filename)(CR)
-filename: a unique abbreviation assigned to the file to be accessed.

8-40· VAX Console Subsystems

• Initialize command - The initialize command initializes the processor to a
specified condition, clears the cache memory and translation buffer, and
sets the proper values in the program counter and processor status
longword.
Syntax: INITIALIZE(CR}

• Help command - The help command accesses and displays a command
file that contains a description of all commands and their uses.
Syntax: HELP(CR}

• Abbreviation help command - The abbreviation help command accesses
and displays a command file containing a list of abbreviations and rules
for the console commands.
Syntax: ABBREV.HLP(CR}

• Error help command - The error help command accesses and displays a
file containing a list-of error messages for the console commands.
Syntax: ERROR.HLP(CR}

• Load command - The load command is used to read or transfer file data
from a console floppy disk to main memory or to the writable-controlstore location. If a qualifier is not specified, data is loaded into physical
memory at address zero.
Syntax: LOAD [(qualifier-list} ](SP}(filename}(CR}
-qualifier-list: /START:(address> = the starting address where the data
will be transferred, /WCS = writable control store, /PHYSICAL =
physical memory.
-filename: the abbreviation assigned to the file.

• Next command- The next command is used to step the CPU clock a
number of events. The type of step is specified,by the previous set step
'command, If the CPU is in the normal clock mode, it will enter the singlestep mode for the duration of the command count.
Syntax: NEXT[(SP}(count}](CR}
- count: the decimal value of the number of clock steps to be
performed.

• Quad clear command - The quad clear command clears an uncorrectable
quadword error at the specified physical address.
Syntax: QCLEAR(SP}(address}(CR}
-address: the physical memory address.

8-41

• Repeat command - The repeat command causes the specified console
command to be repeated until manually stopped by a Ctrl-C character
typed on the console terminal.

Syntax: REPEAT(command)(CR)
-command, imy console command except the repeat command.
• Set default command - The set default command establishes the default
conditions for the address, data length, and terminal I/O radix for console commands that do not contain a qualifier.

Syntax: SET(SP)(DEFAULT)[(SP)(default-option)](CR)
-default-option (address): VIRTUAL = virtual memory, PHYSICAL
physical memory, GENERAL = general purpose registers Rl through
R15, IDBUS = console ID bus, VBUS = console V bus.
-default-option (data): BYTE = one byte, WORD = two bytes, LONG
= four bytes, QUAD = eight bytes.
-default-option (radix): HEX = hexadecimal, OCTAL = octal
• Set step command- The set step command sets the CPU clock modes as
follows:

Syntax: SET(SP)STEP[(SP)(step-option) ](CR)
-step-option: INSTRUCTION = a single-instruction step mode, BUS = a
single SBI-cycle step mode, STATE = a single SBI time-state step mode.
• Set terminal fill command - The set terminal fill command specifies the
number of spaces that are transmitted to the console terminal after a (CR)
or line feed control.

Syntax: SET(SP)(TERMINAL FILL)(count)(CR)
- count: the hexadecimal number of counts.
• Set terminal program command- The set terminal program command sets
the console terminal to console 1/0 mode.

Syntax: SET(SP)TERMINAL(SP)(PROGRAM)(CR)
• Set clock command - The set clock command establishes the operating
speed of the CPU clock.

Syntax: SET(SP)CLOCK[(SP)(speed)](CR)
-speed: SLOW = slow speed, NORMAL = normal speed, FAST = fast
speed.

8-42' VAX Console Subsystems

• Set stop on microbreak match coinmand- The set stop on microbreak
match command· stops the CPU clock when the contents of the
microbreak-matchregister in the console interface is the same as the
contents of the CPU micro-pc.

Syntax: SET(SP}(SOMM}(CR}
• Set relocation command - The set relocation command deposits data into
the console relocation register. The data value is added to the effective
address of the virtual and physical memory during the examine or the
deposit commands.
.

Syntax: SET(SP}RELOCATION(data}(CR}
- data: the value of the data to be deposited.
• Show command - The show command causes the console terminal to display the data inputs and outputs, the default values for the data length,
address type, and radix, the terminal fill character count, the CPU status
including the run or halt state, and the current clock mode.

Syntax: SHOW(CR}
• Start commands- The start command performs two functions. The first
format initializes the CPU, deposits an address in the program counter
(PC), and issues a continue instruction to the CPU. The second format
deposits an address into the micro-pc and starts the CPU clock in the
normal mode of operation.

Syntax: START[(SP}(address}](CR}
- address: the PC address to be deposited.
• Syntax: STARTIWCS(SP}(address}(CR}
-address: the micro-pc address.
• Test command- The test command initates the operation of the microdiagnostic monitor program. Microdiagnostic execution begins immediately if a /COM qualifier is not entered. If the /COM qualifier is entered,
the microdiagnostic monitor enters its command mode and waits for an
operator command. If the microdiagnostic test is successfully completed
and no errors are detected, the console I/O mode is reentered. A microdiagnostic floppy must be loaded in the RXOI disk drive.

Syntax: TEST[(/COM}J(CR}
- /COM: enter the command mode
• Unjam command- The unjam command clears the fault conditions from
the SBI adapter.

Syntax: UN]AM(CR}

8-43

• Wait command- The wait command is executed from an indirect command file. The execution of the command file is susPended until one of
the following occurs: the program running in the ·CPU is completed,
@EXIT is displayed on the console terminal, or the Ctrl-C character is
typed on the console terminal. The execution of the remainder of the
console command file is aborted if the CPU halts and the executing program is not completed.
Syntax: WAIT(SP)(DONE)(CR)
Console Command Errors

Error messages are displayed on the console terminal when console commands are not valid, when improper command syntax is used, or when
error conditions are detected. The console subsystem uses microcode routines in the CPU's control store to perform console functions. Failures in
the microroutines are also reported. All console error messages are prefixed by a question mark to distinguish them from informational messages.
table 8-11 lists and defines the error messages. When user interaction is
required, the steps appear in parentheses following the respective error
description.
Table 8·11· VAX·111780 Console Error Messages
Message

Syntactic Errors
Description

?(TEXT-STRING)
IS INCOMPLETE

The text string is not a complete
console command.

?(TEXT-STRING)
IS INCORRECT

The text string is not recognized as
a valid command.

? FILE NAME ERR

The filename given with a command is
invalid.

?IND-COM ERR

The console has detected an error in the
format of an indirect command file. The
two possible errors are: more than 80
characters in an indirect command line
and an indirect command line did not
end with a CR or line-feed character.

8-44 • VAX Console Subsystems

Message

Command Generated Errors
Description

?FILE NOT FOUND

The filename included with a load or @
command does not match a file on the
currently loaded floppy disk. This error
is also generated when a help or boot
command is issued and the help or boot
file cannot be located, and by an attempt
to load the writable-control store (WCS)
when the WCS file is missing from the
floppy disk.

?NO CPU RESPONSE

The specified time interval for the console to wait for a response from the CPU
was exceeded. A retry may indicate a
possible CPU-related hardware fault.

?CPUNOTIN
CONSOLE WAIT LOOP,
COMMAND ABORTED

A console command that required
assistance from the CPU was issued
while the command was not in the console service loop. The CPU must be
halted and the command reissued.

?CPUCLOCK
STOPPED,COMMAND
ABORTED

A console command that requires the
CPU clock to be running was issued
with the clock stopped. The step mode
must be cleared and the command
reissued.

CANT DISABLE BOTH
FLOPPY'S, FUNCTION
ABORTED

An attempt was made to disable both
the remote and local floppy.

8-45

Message

Microroutine Errors
Description

?MIC-ERRON
FUNCTION

A microerror occurred in the CPU
while servicing a console request. The
SBI adapter error registers are cleared
after this message is printed. The resultant action depends on the error.

?INT-REG ERR

A microerror occurred while attempting
to reference a CPU internal processor
register. An illegal address will cause this
error.

?MICRO-ERROR,
CODE=X

An unrecognized microerror occurred.
The code returned by the CPU is not in
the range of recognized error codes. X is
the code returned by the CPU.

?MEM-MAN FAULT,
CODE=XX

An examine or deposit command to a
virtual memory location caused an error
in the memory management microroutine. XX is a one-byte error code returned
by the routine, with the following bit
assignments:
Bit 0 = Length violation (bits numbered
from right).
Bit 1 = Fault was on a page-table-entry
reference.
Bit 2 = Write or modify intent.
Bit 3 = Access violation.
Bits 4-7 = Ignored.

8-46· VAX Console Subsystems

Message

CPU Fault-generated Error Messages
Description

?INT·STACK INVALID

The CPU has halted because the inter·
rupt stack is marked invalid.

?CPU DOUBLE·ERR
HALT

A machine check has occurred before a
previous machine check had been com·
pleted. This causes the CPU to execute a
double·error halt. The cause of the
machine check can be determined by
examining ID registers 30-3F
(hexadecimal).

?ILL lIE VECTOR

The CPU has detected an illegal interrupt
or exception vector.

?NOUSRWCS

The CPU has detected an interrupt or
exception vector to a nonexistent user's
WCS.

?CHMERR

A change mode instruction has been
attempted from the interrupt stack.

INTPENDING

An error was pending when a console·
requested halt was performed. A con·
tinue command must be issued to clear
the interrupt.

?MICRO·MACHINE
TIMEOUT

Indicates that the microprocessor has
failed to service an interrupt within a
specified time period.

8-47

Message

Messages Generated by Floppy Disk Errors
Description

The RXOI driver has detected an
error. The codes are printed in hexadecimal radix as follows:

?FLOPPY
ERROR,CODE = X

x = I-Floppy hardware error (CRC,
parity, etc.).
X = 2 - File not found.
X = 3 - Floppy-driver queue overfull.
X = 4-Console software requested an
illegal sector number.
?FLOPPY NOT READY

The console floppy drive was not ready
when a bootstrap was attempted. The
bootstrap operation must be performed
again.

?NO BOOT ON
FLOPPY

The console has attempted to boot from
a floppy disk that does not contain a
valid boot block.

?FLOPPY ERROR ON
BOOT

A floppy disk error was detected while
attempting a console boot.

Message

Version Compatibility Messages
Description

?WARNING-WCS &
FPLA VER MISMATCH

The microcode in the WCS is not
compatible with the floating-pointaccelerator option. This message is
printed with each start or continue command from the interrupt-stack pointer.

?FATAL-WCS & PCS
VER MISMATCH

The microcode in the programmablecontrol store is not compatible with the
microcode in the writable-control store.
The start and continue commands of the
interrupt stack pointer are disabled by
the console.

?REMOTE ACCESS NOT
SUPPORTED

The console local/remote switch is
set to the remote position and the remote
support software is not included in the
console.

8-48· VAX Console Subsystems

Message

Console Generated Errors
Description

?TRAP-4, RESTARTING
CONSOLE

The console subsystem is restarting after
a time-out sequence has occurred.

?UNEXPECTED TRAP
MOUNT CONSOLE FLOPPY
THENTYPEAC

The console is trapped by an unused
vector. The console will reboot when
Ctrl-C is typed on the console terminal.

?Q-BLKD

The output queue of the console output
queue is blocked. The console will reboot
when the condition is eliminated.

If the auto restart switch is in the on position and a valid RPB block is
located, the console subsystem examines bit 0 of the fourth longword in
the RPB. If bit 0 is set, the program halts. If bit 0 is clear, it sets the bit and
starts the execution of the restart routine. If a valid memory block is not
located, the console subsystem attempts to reboot the system .
• DEFAULT BOOTSTRAP PROCEDURE

The VAX-IU780 contains a default bootstrap command file
(DEFBOO.CMD) that is used during normal system operation for the following conditions:
• When a boot command that does not specify the device containing the
bootstrap program is executed
• During a powerup sequence when the auto restart switch is in the on
position
• During a powerup sequence when the boot switch is in the on position
• When a move to processor register· (MTPR) instruction is issued to the
console that invokes the bootstrap program

8-49

Bootstrap Loading Sequence
The bootstrap loading sequence is controlled by the console subsystem and
is used to load the operating system into the CPU. The bootstrap loading
sequence initializes the CPU and executes a bootstrap command me to load
the operating system into processor memory from the specified mass storage device.

The bootstrap sequence can be initiated manually by the operator or automatically by the default bootstrap command procedure. For the manual
procedure, the operator first invokes the console program by the following
procedure:
1. Insert the console bootstrap diskette into diskette drive O.
2. Set the auto restart switch on the control panel to the off position.
3. Set the local/remote switch on the control panel to local position.
4. When power is applied, bootstrap the console diskett, causing display of
the console prompt 0»).
5. If the power is already applied, type the Ctrl- P character for display of
prompt.
6. Enter the boot command to reboot the console subsystem.
When the boot command is entered, the boot command procedure on the
console floppy disk is loaded into the console subsystem and the following
operations are performed:
• The CPU is halted and initialized.
• The synchronous backplane interconnect is unjammed.
• The address of the system control block is deposited.
• The general registers are loaded with the information of the device that
contains the system program and with the software control flags.
The console subsystem then initiates the program stored in ROM, which
results in the following:
• Tests the condition of the CPU and checks for a valid memory
configuration.
• Locates a 64-Kbyte block of memory that does not contain uncorrectable
errors.
• Loads the address plus a value of 200 (hexadecimal) into the stackpointer.
The console subsystem then loads the primary bootstap program, transfers
control to the program, and enters program I/O mode.

8-50· VAX Console Subsystems

• SYSTEM RESTART PROCEDURE
After a failure, the console subsystem attempts to restart the CPU when
power is restored if the memory information is valid and if the auto restart
switch is in the on position. The restart procedure is also initiated when a
halt instruction is executed or when a machine error halt condition has
occurred and the auto restart switch is in the on position. The console
subsystem loads the console program and microcode from the console
floppy.

If the auto restart switch is in the off position, the console subsystem issues
a console prompt 0»).
If the auto restart switch is in the on position, the console program identifies the type of halt condition and the time of the halt and stores this
information in the general purpose registers. It then invokes the restart
command file (RESTAR.CMD) on the console floppy disk, which performs
the following operations:
Deposits the ROM address of the system control block (SCB) in the SCB
base processor register when the processor is halted and initialized.
Clears the unused general purpose registers (GPR) and deposits the boot
device adapter number in GPR (R3). The ROM program then searches
memory for a valid restart parameter block.
Initiates the ROM program that searches for a valid restart parameter
block.

8-51

. VAX-111782 Console Subsystem
The VAX-1l1782 system consists of a primary VAX-1l1780 processor and
an attached, secondary VAX-1l1780 processor_ Each processor connects to
an MA780 shared memory through a memory controller_ The local memories of the processors are used only for diagnostic functions. The operation
of each processor is controlled by the VAXIVMS operating system. The
functions of the console subsystem of the primary and attached processor
are similar to those described for the VAX-1l1780 pocessor; however, the
primary processor controls many of the attached processor operations.
Console Modes

The console subsystem of the primary and attached processor can operate
in console I/O mode or program I/O mode. Refer to the console mode
descriptions for the VAX-1l1780 console subsystem for the detailed information about console I/O mode operation.
System Control Panels

The primary processor and the attached processor each have a control
panel on the front of the CPU cabinet. The function of the switches and
indicators are the same as those described for the VAX-1l1780 processor.
Console Control Characters

The control characters used with the console subsystem of the primary and
attached processors are the same as those described for the VAX-1l1780
processor.
Console Commands

The console command language, as described for the VAX-1l1780 processor, can be used with the primary and attached processor of the VAX111782 system. Refer to the user's documentation for detailed information
about the commands and their functions.
Console Command Errors

The error messages reported when illegal commands are entered on the
console terminal are described in table 8-11.

8-52· VAX Console Subsystems

Bootstrap Loading Sequence

The bootstrap loading sequence for the primary processor is similar to a
single VAX-1l1780 processor system. The bootstrap loading sequence for
the attached processor in the VAX-11l782 system, however, is different
from the single VAX-111780 processor system.
In the VAX-1l1782 primary processor, the MA780 shared memory is used
during the bootstrap command procedure instead of the local memory.
The memory configuration registers are initialized by the command procedure. The MA780 memory controller does not contain a boot ROM to load
the system program. The first 64-Kbyte block of shared memory is accessed
at physical address zero and the primary bootstrap code file (VMB.EXE) is
located at physical address 200.
In the VAX-1l1782 attached processor, the bootstrap command procedure
initializes the memory registers and then executes a self-branch instruction
in the reboot parameter block (RPB) located at physical address zero. After
the primary processor is booted, a console command is executed to load
the mutiprocessing code. This command also modifies the self-branch
instruction in the RPB to point to the attached processor's multiprocessing
initialization code.
System Restart Procedure

The restart procedure for the primary processor is similar to the procedure
described for the VAX-1l1780 single processor except that the boot ROM
does not exist in the memory controller and the shared memory is used.
The restart command file (RESTAR.CMD) loads the address of the RPB plus
a value 200 into the stack pointer.
The restart procedure of the attached processor is the same as that
described for the attached processor bootstrap procedure. In the event of a
power failure the attached processor returns the current process information to the primary processor.
Default Bootstrap Command Procedure

The VAX-1l1782 system uses a modified default bootstrap command file
(DFBOO.CMD). A memory ROM is not used to load the stack pointer; and
the command file contains a deposit command and initialize command for
the memory registers.

8-53

. VAX-ll/785 Console Subsystem
The console subsystem of the VAX-ll/785 processor is similar to the VAX11/780 console subsystem. The VAX-ll/785 console subsystem provides
improved console performance and includes 48 Kbytes of RAM memory
that is used to load the system microcode.
Console Modes

The console subsystem of the VAX-ll/785 processor operates in the same
modes as the VAX-11/780 processor.
System Control Panel

The control panel for the VAX-ll/785 processor is the same as the VAX11/780 processor. Refer to table 8-10 for the functions of the switches and
indicators on the control panel.
Console Control Characters

The control characters used with the console subsystem of the VAX-11/785
processor are the same those for the VAX-11/780 processor.
Console Command Errors

Error messages are displayed on the console terminal when invalid console
commands are entered, when improper command syntax is used, and when
error conditions are detected. The console subsystem uses microcode routines in the CPU's control store to perform console functions. Failures in
the micro routines are also reported. All console error messages are prefixed by a question mark to distinguish them from informational messages.
Table 8-11 lists and defines the error messages. When user interaction is
required, the steps appear in parentheses following the respective error
description.
Bootstrap Loading Sequence

The bootstrap loading sequence can be initiated manually by the operator
or automatically by the default bootstrap command. The initialization of
the VAX-11/785 system is similar to the VAX-11/780 system except for the
differences described in the following paragraphs.

8-54 • VAX Console Subsystems

Except for the default bootstrap file, the bootstrap command procedure's
file names for the VAX-1l1785 are different from those for the VAX-1l1780
system. The file names do not contain unit numbers of the devices. When
the indirect command file is used to initiate the bootstrap operation, the
device unit number must first be entered into the general purpose register
R3 before the @ command is issued.
When the boot command is used to initiate the bootstrap operation, the
. console subsystem examines the device-name parameter of boot command
and performs the action based on the specified parameter. For example, if a
device number is not specified or is in the range of 0 through 7 for a BOOT
DU2 command, the device number is ignored and the DUBOO.CMD command file is used. If a device number exceeds 7, the device number must be
entered into R3 before the boot command is initiated. Device unit numbers
that are not specified are considered to be zero .
• DEFAULT BOOTSTRAP COMMAND PROCEDURE
The default bootstrap command procedure file (DEFBOOT.CMD) is contained on the console floppy disk. The bootstrap command file contains a
sequence of bootstrap commands used to initialize the system and to load
the operating system software into the CPU during normal system
operation.
Alternate bootstrap command files can be used in place of the default
bootstrap procedure; however, the command files must be edited to
deposit the appropriate device unit number in general purpose register R3
before the DEFBOO.CMD file is stored on the console floppy disk. The
default procedure is used for the following conditions:
• When a command procedure is not specified during bootstrap
operations
• When power is restored after a power failure and the system is in console
1/0 mode with the auto restart switch in the on position
• When the boot switch is pressed

8-55

. VAX ~600 Console Subsystem
The VAX 8600 console subsystem is a programmed interface between the
VAX 8600 processor and the console terminal, console disk drive, remote
diagnostic port, and the system environmental monitoring module. The
console subsystem is controlled by a T-ll microprocessor that supports a
subset of the LSI-ll instructions. The console subsystem includes a 256Kbyte, parity-assisted dynamic RAM, an 8-Kbyte PROM, three programmable serial-line interfaces and a time-of-year clock. The three serial-line
interfaces transmit information to and receive information from the console terminal, remote diagnostic line, and environmental monitoring module(EMM).
The console software resides in the 256-Kbyte RAM and the 8-Kbyte
PROM. The 8-Kbyte PROM stores the program executed by the T-ll during the powerup sequence. This program self-tests the microprocessor, performs hardware initialization, and loads the console software into the
256-Kbyte RAM from the console load device. The console software
includes the diagnostic console program (DCON), macrocode control program (MCP), and the diagnostic control program (DC).
Some of the features and functions of the console subsystem are as
follows:
• Includes a system clock control and time-of-year clock with battery
backup.
• Performs the system power sequences and monitors the system
environment.
• Includes EIA compatible serial-line interfaces for the console terminal,
remote dillgnostic port, and environment monitoring module.
Includes the system and CPU diagnostics programs.
Provides memory storage for bootstrap and diagnostic programs.
• Provides self-diagnostic testing during the system initialization.
• Includes powerup configuration programming
In addition to the standard capabilities provided by all VAX processor subsystems, the VAX 8600 console subsystem provides local diagnostic testing
in the diagnostic control mode, a mode to test the microcode, and a debugtrace test facility.

8-56· VAX Console Subsystems

VAX 8600 Console Modes
The console program is loaded from the RL02 disk drive under control of
the PROM code during the powerup initialization process. The RL02 is a
lO.4-Mbyte cartridge-disk drive mounted in the front-end cabinet that is
attached to the CPU cabinet. It consists of an RL02 disk drive and disk
drive controller and combines the reliability and convenience of a cartridge
disk in a medium-capacity storage device. After the program is loaded and
in operation, the console program controls the console subsystem. Both a
console diagnostic program and an RL02 diagnostic program are contained on the the console disk.
The console subsystem operates in console I/O mode and program I/O
mode. In console I/O mode, the processor is halted and the console subsystem processes the commands issued by an operator from the console terminal. In program I/O mode, the processor is under control of the operating
system and the console terminal responds only to requests issued from the
processor. Requests .from the CPU are serviced by the console subsystem
and the console subsystem provides special system monitoring functions.
The general features of the console subsystem are as follows:
• Allows independent character transfer between the CPU and the local or
remote terminal ports.
• Controls the transfer of information between the CPU and the EMM.
• Controls the logical console requests from the CPU.
•. Provides CPU access to the console load device.
• Detects and controls the recovery of CPU error halts, keep-alive failures,
and power failures.
• Provides time-of-year information to the cpu.
• Controls the front panel indicators.
Figure 8-6 shows the events required to select the VAX 8600 operating
modes. Console I/O mode is entered when the CPU halts and by the following conditions:
• During system powerup and after initialization is completed, if the boot/
halt switch is in the halt position and if the local/remote switch is in the
local position.
• When an attempt to boot or restart the system fails.

8-57

• When console subsystem is in program I/O mode and a Ctrl-P character,
typed on the console terminal, is allowed by the setting of the control
panel switches_ If the hexadecimal (HEX) debugger command set of console I/O mode is enabled, the processor will continue to execute instructions and the console program will service the operator requests. If it is
not enabled, the Ctrl-P character will halt the processor.
Program I/O mode is entered by the following conditions:
• From the macro context of console I/O mode when a start or continue
command is issued.
• At the completion of the console reboot procedure or after the console
program initialization, if an attempt is made for a warm-start or coldstart.

CONSOLE-------<~I

REBOOT/SOFlWARE
INITIAliZATION

EXIT: CPU HALT/(CfRL-P) STARTICONTINUE
COMMANDS
HEX DEBUG ENABLED·
CPU PROGRAM RUNS
HEXDEBUG DISABLED:
CPUHALTS

CONSOLE 110 MODE

MACRO CONTEXT
DIAGNOSTIC CONTEXT
MICROHARDCORE
CONTEXT

Figure 8-6 • VAX 8600 Operating Mode Selection

8-58· VAX Console Subsystems

The macro context, diagnostic context, or microhardcore context can be
selected in console 1/0 mode. A general command set is available for all
console mode contexts and each context has a specific function and command set. A microcode!hardware debugger command set is also available
for two of the three contexts. The console subsystem includes local diagnostics in the diagnostics control mode, a mode to test the microcode, and
a debug-trace facility. In addition to performing the console terminal I/O
operations and processing the commands during console 1/0 mode, the
console subsystem controls the following functions:
• Reporting of unsolicited warning messages from the EMM
• Reporting of the CPU control-store parity errors
• Operation of the front panel switches and indicators

System Control Panel
The VAX 8600 control panel, shown in figure 8-7, is on the front of the CPU
cabinet and communicates with the console subsystem through the serial
diagnostic (SD) bus. The console subsystem monitors the state of the
switches and controls the indicators on the control panel. The position of
the switches on the control panel and the existing console mode control
the response of the console subsystem to the external inputs. The control
panel contains two rotary switches and four status-indicator lights.
The local/remote switch is a five-position rotary switch used to control the
power to the system and to select access to the console terminal or to the
remote terminal by the operating program. When it is in the local disable
position, the functions of the boot/halt switch are disabled.
The boot/halt switch is a four-position rotary switch that controls the console program during the console software initialization and in response to a
CPU program halt or power failure. When the local/remote switch is in the
local disable position, the boot/halt switch is assumed to be in the restart
boot position. Table 8-12 lists the functions of the switches and indicators
on the control panel.

---------------

VAX

REMOTE

STATE

ENABLE

ACTIVE

RESTART RESTART

ALERT

BOOThHALT

0- 0- 0- 0- BOOT~HALT
Figure 8-7 • VAX 8600 Control Panel

8-59

Table 8-12 • VAX 8600 Control Panel Functions
Switch/Indicator

Function

Local/remote switch

0/1- The dc power is removed from the CPU and
the battery backup unit is disabled. The cooling
fans and blowers are not operating.
Local disable-During the console program initialization, the console program performs an
automatic restart bootstrap initialization. In console 1/0 mode, the console subsystem accepts
commands from the console terminal and the
remote diagnostic port is disabled. In the program 1/0 mode, the Ctrl-P character typed on the
console terminal, is not serviced.
Local- During console program initialization, the
position of the boot/halt switch determines the
console operation. In console VO mode, the console subsystem accepts commands from the console terminal and the remote diagnostic port is
disabled. In program 1/0 mode, the Ctrl-P character typed on the console terminal will halt the
CPU and the console subsystem will enter console 1/0 mode.
Remote disable-During console program initialization, the position of the boot/halt switch determines the console operation. In console VO
mode, the console subsystem accepts commands
from the console terminal and the remote diagnostic port is disabled. In program VO mode, the
console subsystem allows the operation of
remote diagnostic service. The Ctrl-P character
typed on the console terminal will have no
effect.
Remote-During console program initialization,
the position of the boot/halt switch determines
the console operation. In console 1/0 mode,
access to the remote diagnostic port is enabled
and the console subsystem accepts commands
from both the console terminal and remote diagnostic terminal. In program VO mode, access to
the remote diagnostic port is enabled and the
Ctrl-P character, typed on the console terminal,
will halt the CPU and the console subsystem will
enter the console VO mode.

8-60· VAX Console Subsystems

Boot/halt switch

Boot- When the console software initialization is
completed and the lo.cal/remote switch is not in
the local disable position, the console will
attempt to bootstrap the operating system from
the default device location specified by the boot
command. If the bootstrap attempt fails, console
I/O mode is entered and the CPU waits for a
command from the console terminal. In program
1/0 mode, if the local/remote switch is not in the
local disable position and the CPU halts, the bootstrap sequence will also be initiated.

Restart boot- The console subsystem attempts to
restart the operating system at the completion of
the console software initialization if the local/
remote switch is not in the local disable position.
If the restart fails, the bootstrap sequence is initiated. If the bootstrap fails, the console program
enters console I/O mode and waits for a command from the console terminal. If the CPU halts
in program I/O mode and the local/remote
switch is not in the local disable position, then the
bootstrap sequence is initiated.

Restart halt- The console subsystem attempts to
restart the operating system at the completion of
the console software initialization if the local/
remote switch is not in the local disable position.
If the restatt attempt fails, the console program
enters console 1/0 mode and waits for a command from the console terminal. In program I/O
mode, if the CPU halts as a result of an error and
the local/remote switch is not in the local disable
position, then the console subsystem will enter
console 1/0 mode and wait for a command from
the console terminal.

Halt - At the completion of the console software
initialization, the console subsystem enters console 1/0 mode and waits for a command from the
console terminal if the local/remote switch is not
in the local disable position. In program I/O
mode, if the CPU halts and the local/remote
switch is not in the local disable position, a program recQvery is not attempted.

8-61

VAX State indicator

Lighted green intermittently to indicate that the
CPU is executing instructions. Not lighted when
the CPU is not executing instructions or when
the console program is not in program I/O
mode.

Remote Enable indicator Lighted green to indicate the remote diagnostic
access is enabled. This condition exists when the
local/remote switch is in the remote disable position and the console program is in program I/O
mode.
Remote Active indicator Lighted green to indicate that the remote terminal is connected and the line is active.
Alert indicator

Lighted red to indicate that the environmental
monitoring module has detected a potential failure of an environmental condition in the CPU
cabinet.
Lighted intermittently to indicate that the internal temperature of the CPU cabinet has exceeded
a specified limit or that a problem exists with the
cooling air flow. A system failure will result if the
condition indicated on the console terminal display is not corrected.

Console Software Programs

The console subsystem performs a complete initialization sequence in
response to a console reboot request from the CPU, when a reboot command is issued from the console terminal while in console I/O mode and
when the ac power is restored after a power interruption. The initialization
sequence begins with the execution of the console PROM code and ends
with the initialization of the macro context.
The macro context initialization is automatically performed following the
console program initialization. It is initially entered by the console program
during the powerup sequence, during a console reboot sequence or when
the macro command, from the general command set, is issued from the
console terminal. The macro context is also entered when a program
reboot or restart sequence is initiated and the CPU is halted. It provides a
superset of the VAX console commands to initialize the processor and to
allow the macrocode to operate while the console subsystem is functioning
as an interface for the console terminal and EMM inputs.

8~62· VAX Console Subsystems

The diagnostic context provides the commands necessary to support the
loading and operation of the microdiagnostic programs. This context,
together with the microdiagnostic programs, is used as an aid to processor
verification and maintenance a&er the'microhardcore context has been
successfully performed.

In the microhardcore context, a group of 98 diagnostic tests can be initiated to check the functions of the VAX 8600 processor hardware. The
microhardcore programs are used to verify the operation of the Ebox,
Fbox, Ibox, and Mbox logic.
A subset of the general commands set can be used in all contexts to change
the existing contexts and to control the basic console functions. The Ctrl-C
and Ctrl-P control characters are also used to abort most command lines
and all levels of command files. A superset of debug commands can be
enabled in console and diagnostic control mode to provides state and clock
stepping and monitor, trace, and breakpoint support for hardware and
so&ware debugging.

• CONSOLE SOFTWARE ORGANIZATION
The console software includes several utility programs used to bootstrap
the console so&ware and to initiate and control the diagnostic functions.
The console program is loaded from the RL02 disk by the PROM code
during the console initialization process. The console so&ware ~onsists of
three levels of programs: the diagnostic console (DCON) program, the
macro control program (MCP), and the hexadecimal (HEX) debugger program. Figure 8-8 shows the console so&ware organization.

RT-ll OPERATING SYSTEM
(DCL)

[
[

DIAGNOSTIC CONSOLE
PROGRAM (DCON)
DIAGNOSTIC
CONTROL
PROGRAM
(DC)

MACRO
CONTROL
PROGRAM
(MCP)

HEXADECIMAL DEBUGER
PROGRAM (HEX)

]
]

1ST LEVEL

2ND LEVEL

3RDLEVEL

Figure 8-8 • VAX 8600 Console Software Organization

8-63

The RT-ll operating system provides the console program with the general
system software requirements including a disk file structure, console terminal port services, timer functions, and disk 1/0 control and bootstrap
loading.
The DCON program is an RT-ll based console operating system that is
loaded in the T-ll console microprocessor RAM during the system
powerup initialization. The program controls the microprocessor and provides a base to load other software programs. It monitors the power and
environmental inputs from the system, operates and controls the console
terminal and remote terminal, and the RL02 console disk drive, and services the hardware interrupt requests. It also maintains the checksum of
the microprocessor memory and provides a runtime library for other software programs.
The MCP is a subset of the DCON program and is part of the software that
communicates with the macro ISP machine. The MCP operates with the
console support microcode (CSM) in the Ebox to provide the console program with access to various address spaces in the cpu.
The diagnostic control (DC) program is used with the MCP to load, execute, and monitor the results of each microdiagnostic test. The diagnostic
support microcode (DSM) is a microprogram in the Ebox and is used with
the DC program to link the console to main memory and to the Ebox
scratchpad memories.
The hexadecimal (HEX) debugger is a command set that provides predefined visibility registers used to trace the machine states and other functions of the CPU that do not use the console support or diagnostic support
microcode.
Console Command Syntax

The syntax of the console subsystem commands of the VAX 8600 processor
is similar to the syntax of the other VAX processors. Some of the console
commands, however, require additional symbols, qualifiers, switches, and
keywords to further define the command. The symbol { } surrounding part
of an expression indicates that one selection must be entered from the list
of available items. The command syntax can include one or more of the
following entries.
• Command - The first item on a command line that defines the command

• Iswitch-A qualifier used to select an option associated with the
command
• Iswitch:number- A numerical argument associated with the switch
• Keyword-An argument to a command
• Keyword:argument-A numeric or symbolic argument associated with
the keyword

8-64· VAX Console Subsystems

General Command Set

The commands in the general command set are available for all console 1/0
mode contexts and include commands to change the current context, to
control the console operation, and to display the contents of files and registers throughout the system. The commands are also used to initialize the
EMM modular power system, to reboot the console software, and to reset
the CPU.

• Debug command - The debug command allows the command set of the
hexadecimal debugger to be concatenated to the command set of the
macro and diagnostic context. This command is not available in the
microhardcore context. The CPU clock must be halted before this command can be entered.
Syntax: DEBUG(SP)[switch) l(CR)
-switch: IV start the octal debugger (ODT) program. If ODT is not
present, the hex command set is enabled.

• Diagnose command - The diagnose command changes the console program to the diagnostic context. (Refer to the diagnostic context mode
section for the command syntax).
• Load command - The load command loads the specified file from the
system disk to the specified control store or RAM location. If a filename is
not specified, the default system microcode file for that control store will
be loaded.
Syntax: LOAD(SP){ switch}(SP)[filename[ .BPN]] (CR)
-switch: I ACCESS, ICONTEXT, ICYCLE, IECS, IFBACS, IFBMCS,
IFDRAM, IICS, IIDRAM, IMCF, IMCS.
- filename: the name of the .BPN file to be loaded.
-default filename: Access = ACCESS.BPN, Context = CTX.BPN, Cycle
= CYCLE.BPN, ECS = VENUS.BPN, FBACS = FADD.BPN, FBMCS =
FMUL.BPN, FDRAM = FADD.BPN, ICS = IBOX.BPN, IDRAM =
VENUS.BPN, MCF = MCF.BPN, MCS = UCODE.BPN.

• LUPC command- The'LUPC ~ommand causes the specified microsequencer to be loaded into the specified control-store address.
Syntax: LUPC(SP)(switch)(SP)(hex-addr)(CR)
- switch: IECS = Ebox,/ICS = Ibox, MCS = Mbox,IFBACS = Fbox AI
FBMCS = Fbox M.
- hex-addr: the address of the control-store location.

• Macro command - The macro command changes the console I/O mode to
the macro context. Refer to the macro context commands for the command format and functions.

8-65

• MCH command-The MCH (microhardcore) command changes the
console 1/0 mode to the microhardcore context. Refer to the microhardcore context commands for the command format and functions.
• Reboot command - The reboot command reloads the console software. If
the CPU is operating normally when the console program is entered, the
console enters program I/O mode. If the CPU is not in normal operation,
the function of the command depends on the system state.

Syntax: REBOOT(CR)
• Repeat command - The repeat command allows most console commands
to be repeated, except for the commands listed.

Syntax: REPEAT(SP)[hex-num](CR)
-hex-num: a hexadecimal number that specifies the number of times the
command will be repeated.
-nonrepeatable commands are deposit/mark, deposit/CSPE, repeat, next,
start,'microstep, T micro, trace define, continue, statestep, T state, trace
delete.
• Reset command - The reset command initializes the CPU logic by setting
the CPU clock and related signals to a specified condition.

Syntax: RESET(CR)
• Restart command - The restart command restarts the console software
initialization. When the initialization is completed, the console program
enters the macro context.

Syntax: RESTART(CR)
• RT exit command-The RT exit command transfers console control to
the RT-ll monitor and then to the console PROM code.

Syntax: RTEXIT(CR)
• Set base command-The set base command causes a base value to be
added to the address for all examine or deposit commands that are issued
to virtual memory. If the memory map is disabled, the base value is
ignored and the virtual access defaults to a physical memory access.

Syntax: SET(SP)BASE[hex-num](CR)
- hex-num: a 32-bit value to be added to the specified address.

8-66· VAX Console Subsystems

• Set clock frequency command - The set clock frequency command allows
.
the selection of the CPU clock frequency source.

Syntax: SET{SP)CLOCK{SP)FREQ{SP){state}){CR)
-state: dec-num-a decimal number of the clock frequency from 40 to
64 megahertz, NORMAL-nominal frequency, HIGH-high margined
frequency, QUIET -suppresses the reporting of the not locked condition of the variable-control oscillator.
• Set clock speed command - The set clock speed command selects the operating speed of the clock frequency determined by the set clock frequency
command.

Syntax: SET{SP)CLOCK{speed}{CR)
-speed: FULL = the speed set by the set frequency command, ONEFIFTH = one-fifth of the full frequency set by the set frequency command, DEFAULT -establishes the last selected frequency and rate as
the new defaults for all subsequent INIT/CLOCK commands.
• Set /lag command- The set /lag command controls the setting of the software and hardware flags in the console subsystem.

Syntax: SET{SP){flag){SP){state}{CR)
-flag: ABORT provides limited control of the error handling within a
command file, ABUS controls the enabling of the A bus, BBU controls
the operation of the battery-backup unit, COLD inhibits the repeated
unsuccessful attempts to reboot the CPU, EXTI controls the enabling of
the external interrupts to the console subsystem, FBOX controls the
action of the initialize command to enable or disable the floating-point
accelerator, IOSAFE controls the software write-protect feature of console storage device transfers from the CPU, MEMENA controls the state
of the console signal that enables the memory bus, SNAP allows the
console subsystem to perform a snapshot operation when the the CPU
stops executing macro instructions, QUIET provides control of the
command-echoing function of the command file processor and control
of the output generated by verify, T micro, and T state commands,
WARM inhibits repeated unsuccessful attempts to restart the CPU.
-state: ON, OFF.
• Set power command - The set power command performs the initialization
of the EMM module and the modular power system.

Syntax: SET{SP)POWER{CR)

8-67

• Set somm command - The set somm command controls the enabling and
disabling of the micro-mark breakpoint detection in the CPU clock
module.
Syntax: SET(SP>SOMM(SP>[switches](SP>{state}(CR>
- switches: IECS, IICS, IMCS, IFIELD.
-state: ON, OFF.

• Set terminal command - The set terminal command sets the characteristics of the console terminal and remote diagnostic (RD) terminal ports of
the console subsystem.
Syntax: SET(SP>TERMINAL(SP>(switch>(CR>
-switch: IBAUD:nnnn = the transmit and receive baud rate of console
terminal porti', lRECEIVE:nnnn = the receive rate of the RD terminal
porc",/TRANSMIT:nnnn = the transmit rate of the RD terminal porti"
IPASSWORD[Password] = the login password for RD port access,
I[NO]DSRS = the data set rate select for low or high modem speed of
the RD terminal port, I[NO]PARITY enables or disables the parity generation of the RD terminal port, I[NO]SCOPE = type of terminal
device connected to the terminal port; IODD, IEVEN = parity type for
RD terminal port.
-" nnnn = baud rate 50, 75, 110, 134, 150,200, 300; 600, 1200, 1800,
2000,2400,3600,4800,9600, or 19,200.

• Show clock command - The show clock command displays the current
state of the CPU and system clock. It indicates that the CPU and system
clocks are operating or disabled, and shows the frequency of the CPU
clock source.
Syntax: SHOW(SP>CLOCK(CR>

• Show file command - The show file command locates the specified file on
the RL02 disk drive and displays the content of the file on the console
terminal in a binary dump (default) format or in an ASCII format.
Syptax: SHOW(SP}[filename](CR>
-filename: [.DAT](SPHiASClI]

• Show flags command - The show flags command displays the current
state of the console-program control flags. The flags are controlled by the
set flag command.
Syntax: SHOW(SP>FLAGS(CR>

8-68· VAX Console Subsystems

• Show panel command - The show panel command displays the setting of
the control panel switches and indicators.
Syntax: SHOW(SP)PANEL[switchJ(CR)
-switch: iTEST verifies the read function of the control panel logic.
• Show power command - The show power command displays the status of
the EMM values, the power system, and the system cabinet environmental
conditions. This include dc regulator voltages, temperature measurements, air flow sensors, and battery backup unit availability.
Syntax: SHOW(SP)POWER(CR)
• Show terminal command - The show terminal command displays the
state of the console terminal interface and remote diagnostic port of the
console subsystem. This includes the state of the EIA signals, scope flag,
parity flag, and transmit and receive baud rates of the remote-diagnostic
port.
Syntax: SHOW(SP)TERMINAL(CR)
• Show ucode command - The show ucode command displays the state of
the control-store locations and RAMs. The information includes the current .BPN filename, the .BPN filename for the control-store locations, the
revision number of the microcode, and the RAM status.
Syntax: SHOW(SP)UCODE(CR)
• Show version command- The show version command displays the revision information for the CPU hardware, console program, system microcode, console and EMM PROM code, and various software addresses.
Syntax: SHOW(SP)VERSION(CR)
• Start CPU-clock command - The start CPU-clock command starts the CPU
clock. If the system clock is stopped, the command will start the system
clock before starting the CPU clock. If the SBIA visibility module IS
present, the command will also start the SBIA clock.
Syntax: START(SP)CPU-CLOCK(CR)
• Stop CPU-clock command - The stop CPU-clock command stops the CPU
clock but will not affect the operation system clock. If the SBIA visibility
module is present, the command will also stop the SBIA clock.
Sfntax: STOP(SP)CPU-CLOCK(CR)
• Start system-clock command- The start system-clock command starts the
system clock at the frequency selected by the last set clock frequency
command.
Syntax: START(SP)SYSTEM-CLOCK(CR)

8-69

• Stop system-clock command- The stop system-clock command stops the
system clock and the SBIA clock if the SBIA visibility module is present. If
the CPU clock is operating, this command stops the CPU clock before
stopping the system clock.
Syntax: STOP(SP>SYSTEM-CLOCK(CR>
Unhang command-The unhang command performs an unhang reset
sequence that stops and then restarts the CPU clock. It does not clear the
error status of the CPU or affect the cache memory.

Syntax: UNHANG(CR>
Vterm command - The Vterm command provides an aid to isolate faults
in the visibility terminator and visibility control logic by configuring the
logic to select the specified bit.
Syntax: VTERM(SP>[symbol-name, hex-id](CR>
-symbol-name: the V$ symbol assigned to the serial diagnostic bus
(SDB) visibility register bit by the SDB CAD (.CDF) files.
-hex-id: a 16-bit SDB ID code assigned to a visibility signal.
Wait command - The wait command prevents the console subsystem
from processing commands and from performing other activity for a
specified number of 20-millisecond intervals.
Syntax: WAIT(SP>[hex-countj(CR>
-hex-count: a hexadecimal number between 00 and FF that specifies the
number of 20-millisecond intervals .

• X command - The X command is used to read from and write to the main
memory during the automatic communication between the console and
other systems. The X command protocol is defined by the Digital specification DEC STD 032.
Syntax: X(SP>(hex-addr>(SP>(hex-count>(CR>
-hex-addr: a hexadecimal address of main memory where data is to be
transferred.
-hex-count: the nl1mber of bytes to be transferred from the specified
address.
@ command - The @ command causes the command input to be taken
from the file indicated by the filename. The outputs generated from the
commands in the command file are displayed on the console terminal.

Syntax: @(SP>[filenameJ(CR>
-filename: the filename extension is normally .COM; however, other
filenames can be specified.

8-70· VAX Console Subsystems
Macro Context Commands

The macro context commands are used when the console subsystem is·in
macro context mode to initialize the VAX 8600 processor and to allow
access to the program I/O mode of processor operation. This context is
initially entered by the console program during the powerup sequence and
when the macro command is entered from the other console modes. Many
of the functions of the macro commands use the console support microcode (CSM).

• Boot command - The boot command initiates the bootstrap loading of
the timesharing code into the VAX 8600 processor from the specified
device.
Syntax: BOOT(SP)[switches](SP)[device](CR)
-switches: IR5:hex-num = a hexadecimal number to be loaded into the
R5 register,/NOSTART = do not start the operating system at the completion of the boot command me.
-device: a one to three character device mnemonic to which is automatically appended the corresponding BOD. COM suffix.

• Continuf? command - The continue command performs two separate
functions, depending on the state of the CPU. If the CPU is executing
macro instructions, it enters program I/O mode. If the CPU is not executing macro instructions, this command causes the instruction execution to
begin at the current PC address.
Syntax: CONTINUE(CR)

• Clear memory command - The clear memory command clears the physical
memory as specified by the last initialize or physical address memory map
(PAMM) command.
Syntax: CLEAR,SP)MEMORY(CR)

• Deposit command - The deposit command allows data to be deposited
into the specified address spaces in the CPU and console subsystem. The
data length can be from one to four bytes and the same data can be
deposited into successive locations.
Syntax: DEPOSIT(SP)[addr](SP)[!NEXT:hex-num](SP)[data-type]
(SP){hex -addr, reg -name}(hex-data)(CR)
-addr: IESCRATCH = Ebox scratchpad RAM, /GENERAL = general
purpose register (GPR) , IINTERNAL = internal processor registers
(IPR),/PAMM == physical address memory map, IPHYSICAL = physical memory, IV = T-ll microprocessor RAM address, IVIRTUAL
virtual memory space.

8-71

-hex-num: the next successive location where the same data will be
deposited.
-data-type: IBYTE = one byte, IWORD = two bytes, ILONG = four
bytes.
-hex-addr (the numeric address of the register to be deposited or one of
the following locations): ,', = the last specified address, + = the
address following the last specified address, - = the address preceding the last specified address, @ = the address specified by the contents of the last specified address.
-reg-name: the name of a valid internal processor register, general purpose register, or a miscellaneous register in the processor.
-hex-data: the hexadecimal data to be deposited in the specified address
space .

• Examine command- The examine command allows the contents of several address spaces to be examined. The switch and keywords used in the
command syntax are the same as those defined for the deposit command,
except that (hex-data) information is not used.
Syntax: EXAMINE(SP)[addrl[/NEXT:hex-numHSP)[spaceHSP)
[data-typel(SP){hex-addr,reg-name}<CR)

Find command - The find command causes a search of the main memory,
starting at location zero, for a valid page-aligned 64-Kbyte block of physical memory or for the restart parameter block (RPB). The contents of
main memory, accessed during the search operation, are destroyed. The
findlMEMORYcommand is used primarily in a boot command file to
load the operating systems bootstrap code. ThefindlRPB command initiates a search for the RPB that is used to restart the operating system.
Syntax: FIND [{switch} HCR)
-switch: IMEMORY = a page-aligned 64-Kbyte block of valid physical
memory,/RPB = the restart parameter block.

Halt command - The halt command stops the CPU from processing
instructions when console 110 mode is entered and the HEX debugger
program is in process. If the HEX debugger program is not operating, a
halt condition occurs when a Ctrl-P character is typed on the console
terminal.
Syntax: HALT(CR)

8-72' VAX Console Subsystems

• Initialize command- The initialize command is used to initialize various
software and hardware functions of the VAX 8600 processor.

Syntax: INITIALIZE(SP)[switch](CR)
-switch: /CLOCK initializes the system clock to operate at 40 megahertz
(full speed), /CPU initializes the console support microcode (CSM),
/ESCRATCH loads the Ebox scratchpad registers with the values
required to start the CPU, /MICRO initializes the microcode, /PAMM
configures the PAMM according to the physical memory and the number and type of I/O adapters included with the system, /SDB sets the
control channels of the serial diagnostic bus for normal operation.
• Load main memory command - The load main memory command is used
to load the main memory with the binary data from a specified file.

Syntax: LOAD(SP)[!START:hex-addr](SP)filename[.exe](CR)
- hex -addr: the address where the data will be transferred.
-filename: the abbreviated name of the file to be accessed.
• Start command - The start command operates like the continue command
except that if a (hex-addr) value is specified, it is used as the current
program counter (PC) address to start the processor. If the CPU is running when the command is issued, the processor will reenter program 1/0
mode.

Syntax: START(SP)[hex-addr](CR)
-hex-addr: the hexadecimal address at which the processor will start
operations.
• Next command-The next command will single-step the processor the
specified number of macroinstructions.

Syntax: NEXT(SP)[hex-count](SP)
-hex-count: the hexadecimal number of macroinstructions ,to be
performed ..
• Unjam command- The unjam command clears the unjam register of one
of more SBI adapters. If a keyword i& not entered, all SBI unjam registers
will be cleared.

Syntax: UNJAM[{adapter}](CR)
-adapter: 10AO = SBIO adapter, 10Al
adapter,IOA3 = SBI3 adapter.

SBIl adapter, IOAl

SBI2

8-73

• Verify command - The verify command verifies the contents of anyone or
all control-store locations by comparing the data read from the location
with the contents of the .BPN file. If a switch is not specified, all controlstore locations will be verified.
Syntax: VERIFY(SP)[switch](CR)
-switch: I ACCESS, ICONTEXT, ICYCLE, IECS, IFBACS, IFBMCS,
IFDRAM, IICS, IIDRAM, IMCF, IMCS, IPAMM.
Diagnostic Context Commands

The diagnostic context provides commands to support the loading and
operation of the microdiagnostics. This context, together with the microdiagnostic programs, is used to verify the processor operation and for
maintenance purposes. The diagnostic context is used after the microhardcore context has been successfully performed, to verify the operation of the
processor hard core.
The diagnostic context is entered in response to the diagnose command.
The diagnostic support microcode (DSM) monitors and controls the microdiagnostic program.
The three control characters used with the diagnostic context are as
follows:
• The Ctrl-P character interrupts the microdiagnostic program being performed and returns control to the console terminal. Console commands
can then be entered to modify the diagnostic environment.
• The Ctrl-C character deletes the current console command and returns
control to the console terminal.
• The Ctrl-T character causes information related to the current diagnostic
program to be displayed without interrupting the program operation.
Errors that occur during the performance of the diagnostic context are
displayed on the console terminal. The amount of information included in
the report depends on the setting of the remote/local switch on the control
panel and can include the following information:
• Diagnostic name- the test name of the diagnostic program
• First test-the number of the first test performed
• Last test - the number of the last test performed
• Loop goal- the number of passes entered
• Pass count-the number of passes performed
• Ebox scratchpad data - the data and parameters specified by the set data
command
• Fault detected in test - the number of test that detected the fault

8-74. VAX Console Subsystems

The commands used when operating in the diagnostic context are as
follows:
• Clear data command - The clear data command dears the table of the
pointers defined by the set data command and is used to define a new set
ofEbox scratchpad locations for error reporting.

Syntax: CLEAR(SP)DATA(CR)
• Continue command - The continue command allows the currently loaded
microdiagnostic to resume test execution after being halted by the set
switch command or by typing the Ctrl-P control character.

Syntax: CONTINUE(CR)
• Deposit command - The deposit command allows the modification of the
Ebox scratchpad RAM, the system cache, or the W bus RAM.

Syntax: DEPOSIT(SP){switch}(SP)(hex-addr)(SP)(hex-data)(CR)
- switch: /CACHE, /ESCRATCH, /WBUS.
- hex -addr: the location where the data is to deposited.
- hex~data: the 32-bit hexadecimal data.
• Examine command - The examine command allows the contents of the
specified Ebox scratchpad locations, cache memor,y locations, or W bus
locations to be examined.

Syntax: EXAMINE(SP){switch}(hex-addr)(CR)
- switch: /CACHE, /ESCRATCH, /WBUS.
-hex-addr: the hexadecimal address where the data is to be examined.
• Step command- The step command causes the next test in the currently
loaded microdiagnostic program to be immediately executed.

Syntax: STEP(CR)
• Run command - The run command initiates the execution of a command
file, provided that the command file does not exceed 80 characters. The
switch keywords are described in the set switch command.

Syntax: RUN(SP)[switch](SP)(filename)(CR)
-switch: /BELL: [ON, OFF]; /FAULT: [ISOLATE, LOOP, PAUSE, CONTINUE, IGNORE]; /MODE: [BRIEF, VERBOSE]; /NUMBER: FIRSTTEST, [LAST-TEST]; /PASSES:n (n = number of passes desired)*;
/TRACE: [ON, OFF]
-filename: [.COM].
* n = the number of times that each test in a diagnostic is performed
before the pass is completed.

8-75

• Start command - The start command performs a function similar to that
of the run command except that the microdiagnostic program must have
been previously loaded. The switch selections can be any combination of
the keywords listed in the set switch command description. The command line is limited to 80 characters.
Syntax: START(SP)[switch](CR)
-switch: IBELL: [ON, OFF]; IFAULT: [ISOLATE, LOOP, PAUSE, CONTINUE, IGNORE]; IMODE: [BRIEF, VERBOSE]; INUMBER: FIRSTTEST, [LAST-TEST]; IPASSES:n (n = the number of passes desired)*;
ITRACE: [ON, OFF]
* n = the number of times each test in a diagnostic is performed before
the pass is completed.
• Set data command - The set data command allows a symbolic name to be
assigned to a location in the Ebox scratchpad RAM. This command is
normally used in the command files that control the loading of the microdiagnostic code and the setting of the diagnostic control parameters.
Syntax: SET(SP)DATA(SP)(escratch-addr)(SP)(data-name)(CR)
-escratch-addr: a hexadecimal address of the Ebox scratchpad RAM
from 00 to FE
-data-name: a character string of from 1 to 30 characters, to be associated with the Ebox scratchpad data.
• Set default command - The set default command allows control of the
default switch setting that governs the behavior of the diagnostic context
and diagnostic support microcode. The switch keywords are described in
the set switch command.
Syntax: SET DEFAULT(SP)[switch]
-switch: IBELL {ON, OFF}; IFAULT {ISOLATE, LOOP, PAUSE, IGNORE};
IMODE: {BRIEF, VERBOSE}; INUMBER: FIRST-TEST, [LAST-TEST]; I
PASSES:n (n = number of passes desired)*; ITRACE {ON, OFF}

* n = the number of times each test in a diagnostic is performed before
the pass is completed.
• Set name command - The set name command allows the name of the
currently loaded diagnostic to be included as part of a fault report.
Syntax: SET(SP)NAME(md-filename)(CR)
- md-filename: a microdiagnostic filename of the command procedure.

8-76· VAX Console Subsystems

• Set switch command - The set switch command allows control of the
default switch settings that determine the functions of the diagnostic control program and the diagnostic support microcode.

Syntax: SET(SP)SWITCH(SP)[switch](CR)
-switch: IBELL [ON, OFF]-controls the audio signal from the console
terminal when a fault is detected.
- switch: IFAULT [ISOLATE] - The tests. within the diagnostic are performed as many times as is specified by the PASSES:n switch for the
default condition or as specified by the run and start commands. When
an error is detected, an error report is generated and the test
continues.
- switch: IFAULT [LOOP] - The test is performed a specified number of
times until a fault is detected and an error report is generated.
- switch: IFAULT [PAUSE] - The test is halted after the fault is detected
and the error report is generated. The test is resumed by issuing a continue or a step command.
-switch: IFAULT [CONTINUE]-The tests are performed as many times
as is specified by the PASSES:n switch. When an error is detected, an
error report is generated and the test continues until all the passes have
been completed.
- switch: IFault [IGNORE] - When an error is detected, the error report
is not generated.
-switch: IMODE [BRIEF, VERBOSE]-controls the amount of information included in an error report.
-switch ITRACE [ON, OFF]-controls the enabling (ON) and disabling
(OFF) of the test trace facility.
• Show switches command-The show switches command causes-the current switch keyword selections of the set switch command to be displayed
on the cqnsole terminal.

Syntax: SHOW(SP)SWITCHES(CR)
• Show data command - The show data command causes the symbolic
names and associated data to be displayed on the console terminal.

Syntax: SHOW(SP)DATA(CR)

8-77

Microharocore Context Commands

The microhardcore is a diagnostic program used to verify the proper operation of the microhardcore (MCH) programs in the CPU. The MCH program consists of 98 subtests that are grouped into eight CPU-logic function
test areas within the CPU. The tests reside on the load media and the MCH
program does not create or modify the files in the load device. One test
group or all of the tests groups may be selected by the operator after the
console diagnostics have been performed successfully. Only the selected
tests are loaded into memory. Messages from the MCH program are displayed on the console or remote terminals.
The MCH context is entered by typing MCH in reponse to the diagnostic
console prompt 0»). Once the program is initiated, the version name and
number will be displayed and the microhardcore prompt (MC) will be
issued. A test group or help file, in the format listed as follows, may then be
selected.
The microhardcore commands select the microhardcore tests or the help
file. Typing a Ctrl-C character will stop the diagnostic program at the completion of a subtest. The START(x) command tests are performed in one
pass and the "(MH)" prompt is displayed. The LOOP(x) command tests
are performed repeatedly and are terminated when a Ctrl-C character is
typed at the end of a subtest.
Syntax: Command(SP)(switch}(CR)
-Command: DIAG-return to the diagnostic context
-Command: HELP-display the MHC commands and definitions
-Command: MACRO-return to the macro context
-Command: START or LOOP-perform all tests in the normal verify
mode
-Command: STARTQ or LOOPQ-perform all tests in the quick-verify
mode
-Command: STARTC or LOOPC-perform all clock tests
-Command: STARTE or LOOPE-perform all Ebox tests
- Command: STARTF or LOOPF - perform all Fbox tests
- Command: STARTI or LOOPI - performs all Ibox tests
-Command: STARTL or LOOPL-perform all multibox access tests
-Command: STARTM or LOOPM-perform all Mbox tests
-Command: STARTR or LOOPR-perform only the Ebox MCF-CTX RAM
tests and the basic microcode tests
-Command: STARTS or LOOPS-perform only the Ebox SDB and the
Ebox E/S tests

8-78· VAX Console Subsystems

-Command: STARTU or LOOPU-perform only the Ebox expanded
microcode tests
- switch: BRIEF-display the error report in the short form
-switch: VERBOSE-display the error report in the long form
-switch: QUIET -disables the audio response and permits the error
report to be typed on the console terminal
Debug and Trace Facility
The debug and trace facility is used to modify and interrogate the hardware
state of the cPU. It can be enabled from the diagnostic context or the
macrohardcore context by the debug command and includes a hexadecimal debugger (HEX) command set to allow the operator to modify and
interrogate the state of the cpu. When it is enabled, an additional bracket
0) is added to the normal console command prompt displayed on the
console terminal. The commands provided in the HEX command set are as
follows:

• Clear break command - The clear break command clears the specified
breakpoint from the appropriate table.

Syntax: CLEAR{SP){table}(SP){ident}(CR)
-table: ABREAK = the and-break table, OBREAK = the or-break table.
-ident: V$xxxx = a visibility symbol name, REG = a visibility register
name, hex-id = a 16-bit hexadecimal number as defined in the
examinelSDBcommand, ALL = removes all breakpoints from the specified table.
Clear count command - The clear count command initializes the stepcounter to zero. The counter records the number of machine steps (micro
or state) since it was last cleared.

Syntax: CLEAR{SP)COUNT{CR)
• Deposit command - The deposit command is used to modify the contents
of control store and RAM locations in the cPU.

Syntax: DEPOSIT{SP)[/NEXT:hex-numl{SP){switch}(SP){hex-addr) (hexdata)(CR)
-/NEXT:hex-num-the number of successive deposits of the same data
into consecutive locations.
-switch: IACCESS, ICONTEXT, ICYCLE, IECS, IFBACS, IFBMCS,
IFDRAM, IICS, IIDRAM, IMCF, and IMCS.
-hex-addr (a hexadecimal number or one of the following symbols): " =
the last specified address, + = the address following the last specified
address, - = the.address preceding last specified address.

8-79

-hex-data: a hexadecimal number within the range of the specified control store RAM.
• Deposit channel command - The deposit channel command deposits the
the specified data into the SD bus control channel.

Syntax: DEPOSIT/CHANNEL(SP)(hex-chnl)(SP)(hex-data)(CR)
-hex-chnl (one of the following channel numbers): 00 = FDA, 09
EBE,Ol = FBM,OA = MCC, 03 = IBC,OD = EBC,05 = ICA, OE =
CSB,08 = EDP,lO = VBA (SBIA visibility module).
- hex-data: a 16-bit hexadecimal value to be deposited.
• Deposit/CSPE command - The deposit/CSPE command allows a microword containing a parity error to be deposited into a control-store location. The CPU clock must be stopped before this command can be
entered.

Syntax: DEPOSITICSPE(SP){ switch}(SP)(hex -addr)(CR)
- switch: IECS, IFBACS, IFBMCS, /FDRAM, IICS, IIDRAM and IMCS.
-hex-addr (a hexadecimal number or one of the following symbols): * =
the last specified address, + = the address following the last specified
address, - = the address preceding the last specified address.
• Deposit/mark command- The deposit/mark command allow,s the control
store mark bit to be set or cleared.

Syntax: DEPOSIT/MARK(SP){switch}(SP)(hex-addr)(SP){state}(CR)
- switch: IECS, IICS, IMCS.
- hex -addr (a hexadecimal number or one of the following symbols): * =
the last specified address, + = the address following the last specified
address, - = the address preceding the last specified address.
-state: ON, OFF
• Examine CSAS command-The examine CS'AS (control-store-address
space) command allows the contents of any control-store RAM location
to be examined.

Syntax: EXAMINE(SP)[!NEXT:hex-num](SP){switch}(SP)(hex-addr)(CR)
-INEXT:hex-num (the hexadecimal number of deposits). Used with
other Iswitch keywords to examine any number of successive
locations.
-switch: I ACCESS, ICONTEXT, ICYCLE, IECS, IFBACS, /FBMCS,
IFDRAM, /ICS, /IDRAM, /MCF, and IMCS.
- hex -addr (a hexadecimal number or one of the following symbols): * =
the last specified address, .+ = the address following the last specified
address, - = the address preceding the last specified address.

8-80· VAX Console Subsystems

• Examinelchannel command-The examine/channel command causes the
visibility bits in the specified channel to be displayed on the console
terminal.
Syntax: EXAMINEICHANNEL(SP)(hex-chnl)(cR)
-hex-chnl (the SD bus channel number as follows): 00 = FBA,OI =
FBM, 02 = MCD, 03 = IBC, 04 = IDP, 05 = ICA, 06 = ICB, 07 =
CLK,08 = EDP,09 = EBE,OA = MCC,OB = MAP,OC = EBD,OD =
EBC,OE = CSB, OF = CSA, 10 = IOAO, 11 = IOA1, 12 = IOA2, 13 =
IOA3,14 = MTM .

• Examine/SDB command- The examine/SDB (serial diagnostic bus) command causes the name and state of a visibility signal or a visibility register
tt'> be displayed on the console terminal.
Syntax: EXAMINElSDB(SP)[ident](CR)
-ident: V$xxxx = a symbol assigned to a visibility signal or register, reg
= a visibility register name, hex-id = a 16-bit hexadecimal number of
the hardware visibility-bit address or a software defined numerical tag
for the visibility register.

• Exit command - The exit command disables the HEX command set.
Syntax: EXlT(CR)

• Microstep command - The microstep command causes the specified number of microinstructions to be executed at the system clock speed. If the
SBI adapter visibility module is present, the SBI clock will be set at onehalf the CPU clock speed.
Syntax: MICROSTEP(SP)[hex-num](CR)
- hex-num: a hexadecimal step count from 1 to 100.

• Report command - The report command reads and displays on the console terminal the visibility data in accordance with the current trace list
options set by the trace command.
Syntax: REPORT(CR)

• Set break command - The set break command sets a break condition in
the and-break table or the or-break table. Up to four breakpoints can be
set in each table.
Syntax: SET(SP){table}(SP){ident}[param](CR)
-table: ABREAK = and-break table, OBREAK = or-break table,

8-81

-ident: V$xxxx = a symbol assigned to a visibility signal or register, reg
= a visibility register name defined within HEX debugger or specified
by the trace define command, hex-id = a 16-bit hexadecimal number of
the hardware visibility-bit address or a software-defined numerical tag
for the visibility register.
-param: SPAN causes a break condition to Qccur when the signal or
register state is different from the state at the start of the trace,
VALUE:val causes a break condition to occur when the specified signal
or register equals the value specified.
• Set margin command - The set margin command enables the voltage output levels of the power supply to be varied. This command is used during
maintenance functions to detect hardware fault conditions.

Syntax: SET(SP)MARGIN(SP){value}(SP)[{reg-mar}](CR)
-value: HIGH = 5 percent above normal voltage, NORMAL = normal
voltage, LOW = 5 percent below normal voltage.
-reg-mar (selects the power-supply regulator outputs as follows): A =
regulator A, B = regulator B, C = regulator C, DE = regulator D and
E, FH = regulator F and H, ALL = all regulators.
• Show break command - The show break command causes the contents of
the and-break table and the or-break table to be displayed on the console
terminal.

Syntax: SHOW(SP)BREAK(CR)
• Show define command-The show define command causes the symbol
names used to construct the visibility register to be displayed on the
console terminal.

Syntax: SHOW(SP)DEFINE(SP){reg-name, hex-id}(CR)
-reg-name: the name of the visibility register defined within the HEX
command set or by the trace define command.
-hex-id: a 16-bit hexadecimal number of the hardware visibility-bit
address or a software defined numerical tag for the visibility register.
• Show name command - The show name command displays the V$xxxxx
symbol of the register, id, or signal name. If a register name is specified,
the size of the register (number ofV$ terms defined) is also displayed.

Syntax: SHOW(SP)NAME(SP){ident}(CR)
-ident: symbol-name = the V$xxxx visibility symbol assigned by the
appropriate .CDF data file, reg-name = the name of a register within
the HEX command set or by the define trace command, hex-id = 16-bit
SD bus or register ID, "signal-name" = the name of a visibility signal.

8-82· VAX Console Subsystems

• Show register command - The show register command provides a console
display of all the visibility registers that are defined.

Syntax: SHOW(SP>REGISTER(CR>
• Show trace command - The show trace command provides a console display of the registers and signals currently selected for tracing and the
current breakpoint options. The trace list can be altered by the trace
command.

Syntax: SHOW(SP>TRACE(CR>
• Statestep command-The statestep command causes the CPU clock to
step a specified number of CPU clock cycles. If the SBI adapter visibility
module is included, the statestep command will attempt to step the SBI
clock one-half the number of cycles specified for the CPU clock.

Syntax: STATESTEP(SP>[hex-numJ(CR>
-hex-num: a hexadecimal number of desired clock cycles to be executed
;in the range of 1 to 400.

J' micro command - The T micro command initializes the trace facility
and causes one CPU clock cycle to be performed until a trace breakpoint
condition occurs or until the step-count expires. The state of the CPU is
tHen displayed on the console terminal in accordance with the current
trace settings. If the SBI adapter visibility module is included, this command will attempt to step the SBI clock along with the CPU clock.
Syntax: TMICRO(SP>[hex-numJ(CR>
- hex-num: a hexadecimal number of the clock steps to be executed.
T state command - The T state command initializes the trace facility and
ca\lses one CPu-clock phase to be performed until a trace breakpoint
condition occurs or until the step-count expires. The state of the CPU is
then displayed on the console terminal in accordance with the current
trace settings. If the SBI adapter visibility module is included, this command will attempt to step the SBI clock along with the CPU clock.

Syntax: TSTATE(SP}[hex-numJ(CR>
-hex-num: a hexadecimal number of the clock phases to be executed.
Trace add command - The trace add command is used to enter additional
information to the register lists and signal trace lists. The register names
and symbols can be intermixed in the command. The items in the command line are separated by spaces and the line cannot exceed 80
characters.

Syntax: TRACE(SP>ADD(SP>[itemJ(CR>
-item: reg-name = the names of the registers to be entered, symbol
the V$nnnn symbol that identifies the signal to be entered.

8-83

• Trace define command- The trace define command is used to define visibility registers in addition to those previously defined.

Syntax: TRACE(SP)DEFINE(SP)(reg-name)(CR)
-reg-name: the name assigned to the user visibility register.
• Trace delete command - The trace delete command is used to delete userdefined visibility registers that were established by the trace define
command.

Syntax: TRACE(SP)DELETE(SP)(reg-name)(CR)
- reg-name: the name of the previously defined user visibility register.
Trace remove command - The trace remove command allows register and
signal information to be removed from the trace lists. The list of items in
the command line to be removed must be separated by spaces and the
line cannot exceed 80 characters including spaces.

Syntax: TRACE(SP)REMOVE(SP)(item)(CR)
-item: R" removes all registers from the list, S* removes all signals from
the list, reg-name = the name of the register to be removed, V$nnnn =
the symbol of the signal to be removed.
Trace restore command - The trace restore command restores the default
trace lists, including the visibility registers and signals.

Syntax: TRACE(SP)RESTORE(CR)
VAX 8600 System Initialization
Before the VAX 8600 can be used to perform the customer's application,
both the console subsystem and the CPU must be properly initialized. After
the initialization sequence is started, the actions that occur depend on the
position of the local/remote switch and boot/halt switch on the control
panel. The console subsystem initialization process is initiated by one of the
following events:
• When power is initially applied and the operator sets the local/remote
switch to any position except the off position
• When power is restored after a system power failure
• When the processor initiates a reboot request to the console subsystem
• When the operator executes a reboot command
During a reboot command from the CPU or operator when the boot/halt
switch is in the halt position, the following message will be displayed on the
console terminal.

8-84· VAX Console Subsystems

»)reboot
VAX 8600 Console V(n) (see note 1)
Initializing
Initializing power system
Initializing CPU
Total memory available is (nn) megabytes (see note 2)
)) )

note 1: (n) is the version number of the console subsystem software.
note 2: (nn) is the value of the total number of Mbytes. The message that
follows this message indicates the number of Mbytes in each array that is
installed in the eight CPU memory slots, and the status and revision level
of the SBIA adapters that are installed in the system.
Control is then transferred to the console subsystem PROM by any of the
events that caused the system initializing process. The console PROM code
executes a series of self-tests, loads the bootstrap program from the RL02
disk drive, and allows the console microprocessor to execute the bootstrap
program. The bootstrap program loads the console bootstrap program
(EDOAA) into the microprocessor RAM, which then performs the following
operations:
Initializes the console subsystem and power system
Initializes the macro context in the console subsystem
Initializes the CPU to perform the macrocode
• Monitors the status of the control panel switches
• Console Program Initialization
The console program controls the operation of the console subsystem and
the CPU. The following functions are performed during the console program initialization:
• The console program banner and revision number are displayed.
• The microprocessor vectors and internal data structures are initialized.
• The microprocessor is initialized and allowed to access the 256-Kbyte
RAM.
• The Initializing message is displayed on the console terminal to indicate
the initializing sequence is in process.
• The SD bus signal name tables and the console subsystem microcode are
loaded from the RL02 disk drive into console subsystem RAM.

8-85

The power system is initialized and the Initializing power system message
is displayed on the console terminal.
The clocks in the CPU are initialized.
The console subsystem is initialized to the macro context.

• POWERSYSTEM.INITIALIZATION
The power system initialization, performed during the console program
initialization, sets the power supply regulators to the proper output voltages and enables the environmental monitoring module (EMM) to report
environmental conditions to the console subsystem. During the power system initialization, the following operations are performed:
The proper parameters are set in the console subsystem serial-line interface that communicates with the EMM.
The communication of the EMM channel is verified.
The temperature and voltage parameters are loaded in the EMM.
The EMM functions are enabled.
The power supply regulators are enabled and their operation is verified.
The EMM magnetic disk display is reset to clear any error indications.

• MACRO CONTEXT INITIALIZATION
The macro context initialization is automatically performed following the
console program initialization. During the initialization sequence, control is
transferred to the macro control program overlay, which initializes the CPU
and provides control to the macro command set.
• CPU INITIALIZATION
When the console subsystem enters the macro context, the console program has access to the macro command set to initialize the CPU for microcode operation. The console program submits the LOAD.CMD and the
ULOAD.COM indirect command files internally. These files contain the
commands necessary to initialize the CPU by loading the control RAMs in
the processor from files on the RL02 drive. When the CPU initialization has
been completed, the console program tests the state of the boot/halt switch
on the control panel to determine if a warm-restart or cold-restart process
is to be performed. A message is displayed on the console terminal indicating which process is being performed.

8'86· VAX Console Subsystems

If the boot/halt switch is in the restart boot or restart halt position, or the
local/remote switch is in the local disable position, a warm-restart can
occur. The Attempting System Restart message is displayed, the general
purpose registers in the CPU are initialized, the warm-start flag in the
restart parameter block (RPB) is set, and the CPU begins operation at the
restart address specified by the RPB. When the CPU initialization is completed, the console subsystem enters program 110 mode.

If the boot/halt switch is in the restart boot or boot position and the local/
remote switch is not in the local disable position, a cold restart will be
initiated. The Attempting System Initialization message is displayed, the
operating system is reloaded from the system disk and self-started, and the
program 110 mode is enabled. The cold-start procedure is controlled by
the DEFBOO.COM command me on the RL02 disk drive. The me initializes
the CPU and 110 adapters, locates a block of valid memory, and loads the
VBM program from the RL02 drive. The VBM program loads the operating
system from the system disk drive, initiates the program operation, and
transfers control to program 1/0 mode. If a failure occurs during the coldstart procedure, the console program enters the macro context in console
110 mode.

If the boot/halt switch is in the halt position, the macro context of the
console 1/0 mode is entered after the macro context initialization is
performed.

The input/output (110) subsystems of the VAX-ll/750 processor, VAX11/780 series processors, and VAX 8600 processor connect to an internal
bus structure, which forms the communication path between the CPU and
memory, and between the CPU and devices connected to the I/O subsystems. The internal bus is a fast and reliable synchronous path for the transfer of information. The bus structure for VAX-ll/750 processor is the
CPU/memory interconnect (CMI). For the VAX-ll/780 series and VAX
8600 processors, the bus structure is the synchronous backplane interconnect (SBI). Bus information is transferred to all the units on the bus that are
designated as a nexus. Each nexus can initiate information transfer by
decoding the bus information to determine the type of transaction
required. The computer bus interconnects transfer address, data, and control information between the processor and devices, perform priority arbitration among the CPU and devices, and translate the addresses between
the processors, memory, and devices. Some of the features and functions of
the computer bus interconnects are as follows:
• Transactions are interleaved to allow several simultaneous operations to
be performed during the transfer process.
• Priority arbitration logic monitors the arbitration lines of each nexus.
• Failure of one nexus does not inhibit the operation of the remaining
units.
Parity and protocol checking of the information transferred through the
interconnects insures that the data received is the same as the data transmitted. Errors in the protocol of a transaction are recorded.
• Transactions performed during the most recent bus cycles are recorded
and stored for analysis .

. CPU/Memory Interconnect
The CPU/memory interconnect (CMI) is the internal bus for the VAX11/750 processor. It is a synchronous, interlocked, backplane bus that connects the internal logic of the processor to the main memory and to the 110
subsystem through the processor backplane. The CMI is also the internal
processor path for the remote diagnostic logic, UNIBUS interface logic,
writable control store logic, and the memory interconnect and controller.

9-2' Computer Bus Interconnects

CMI Signal Lines
The CMI bus consists of 45 bidirectional lines used to transfer address,
data, control, status, and priority arbitration signals. A unidirectional bus
clock line provides the signals used to synchronize the transfer of information. A master/slave relationship exists between the units on the CMI so
that the nexus that has control of the bus is considered the master and the
receiving nexus is designated as the slave. Figure 9-1 shows the CMI signal
lines and table 9-1 lists their functions.

D/A31:D/AO (Data/Address)

•

NEXUS

··
<
<
•

DBBY (Data Bus Busy)
HOLD

WAlT
ARB7:ARBl (Arbitration)
STAl:STAO (Status)
BCLK

··•

NEXUS

>
.

Figure 9-1 • CMI Signal Lines

Table 9·1' CMI Signal Line Functions
Line

Description

D/A31 :D/AO

Data/address - Multifunction lines used to transfer
address, data, and control information between the CPU
and a nexus.

DBBZ

Data bus busy- Asserted by the master to specify that an
address is contained on the lines D/A31:D/AO.

Hold

Asserted to temporarily suspend the activity on the CM!.

Wait

Asserted by an I/O subsystem to initiate a processor
interrupt.

9-3

Line

Description

ARB7 :ARB 1

Arbitration - The priority arbitration lines assigned to the
I/O subsystems as follows:
Line* 110 Subsystem
ARB7 Remote diagnostic module (RDM)
ARB6 Reserved
ARBR Reserved
ARB5 UNIBUS adapter 0
ARB4 UNIBUS adapter 1
ARB3 MASSBUS adapter 0
ARB2 MASSBUS adapter 1
ARBl MASSBUS adapter 2
* Line ARB7 has the highest priority and the CPU, which has no
line, is assigned the lowest priority.

STAl:STAO

Status- Two lines that transfer signals by the slave to indicate the following status conditions to the master.
Status Line Condition
1
0
o 0
No response-Master attempted to access
nonexistent memory for a read or write
operation

Data returned to master contains an uncorrectable error

Data transmitted is corrected

1
B CLK L

Data transmitted is correct

Timing - A timing signal generated by the CPU to synchronize the system activities.

Transfer Format
Information is transferred on the data and address lines in two operations.
A master gains access to a slave by transmitting the physical longword
address of the slave and by asserting the data-bus-busy signal for one busclock cycle. A longword is then transferred to or from the slave. If the slave
is not ready to accept the information, it asserts the data-bus-busy line until
it is ready. Figure 9-2 shows the CMI address format and figure 9-3 shows
the CMI data format.

9-4" Computer Bus Interconnects

I , I
BYTE
MASK

FUNC
CODE

I , !

PHYS LN~WD ADDR

[

RSVD

Figure 9-2" CMI Address Format

Bit

Function

31 :28

BYTE MASK - Set to designate which bytes are valid for transfer as

follows:
Bit Valid
31
30
29
28

27 :25

BYTE 0
BYTE 1
BYTE 2
BYTE 3

FUNC CODE (Function code) - An octal value used to designate

the operation being performed by the master as follows:
Value Operation
o
Read
Read lock
2
Read with modify intent
3
Undefined
4
Write
5
Write lock
6
Write vector
7
Undefined
24

RSVD (Reserved).

23:2

PHYS LNGWD ADDR (Physical longword address) - The physical
longword address of data to be read or written.

1:0

RSVD (Reserved).

----------------------

24 23
I

I I

BYTE 3

16 15
I

I
¥
BYTE 2

8 7
I

I
¥
BYTE 1

Figure 9-3 " CMI Data Format

I
¥
BYTE 0

1
I

9-5

Bit

Function

31:24

BYTE 3 - Contains the byte 3 value of the data

23: 16

BYTE 2 - Contains the byte 2 value of the data

15:8

BYTE 1- Contains the byte 1 value of the data

7:0

BYTE O-Contains the byte 0 value of the data

----------------------------

eMIOperation
A minimum duration of three clock cycles is normally required to transfer
one longword of data during a CMI read or write operation. The time
required for a transfer depends on when a slave device returns data or
status information. The cycles used during a transfer are the arbitration
cycle, the CMI address cycle, and the CMI data cycle. During the arbitration
cycle, the CMI is idle and the data-bus-busy and hold signals are not
asserted. During the address cycle, the CMI address and the data-bus-busy
signal are asserted by the master. During the CMI data cycle, the data-busbusy signal is asserted by the slave if it is not ready to complete the transactions. If a slave is ready to receive data, it does not assert a data-bus-busy
signal; therefore, only two cycles are required for the transaction.
The data cycle can be a read or write transaction. In a read transaction, the
slave asserts the data-bus-busy signal and then transmits the requested data
and data status information. In a write transaction, the slave clocks the
data, deasserts the data-bus-busy signal, and returns status information.
A nexus can assert its arbitration signal at any time. Arbitration occurs
when the data-bus-busy and hold signals are not asserted. The nexus with
the highest priority arbitration level asserted inhibits the lower priority
subsystems from gaining access to the bus. On the next positive transition
of the clock cycle, the new master asserts both the physical longword
address of the slave and the data-bus-busy signal. All other units recognize
that an address longword is on the CMI, and the addressed slave responds
accordingly.

9-6· Computer Bus Interconnects

eMI Physical Address Space
The assignment of the physical addresses space for the CMI is shown on the
physical address map in figure 9-4. The address space ine1udes map registers, internal and external MASSBUS and UNIBUS registers, and control and
status registers.

000000

OJFFFF

040000
07FFFF
080000
OBFFFF

Deaooa
FFFFF
100000
DFFFf
140000
17FFFF
180000

IBFFFF
ICOOOO
IFFFFF

FO()()OO

256KB
512KB
768 KB
1024 KB
1280 KB
1536 KB
1892 KB
2048 KB
MAXIMUM FULLY POPULATED ARRAYS

10 KB USER CONTROL STORE

-1I0SPACE

F10000
F20000

n0004

nooos
Fl0400
FI050( }
FI06(}{ }

F20700

f28000
1'28400
F288QO

FIAOQO
FIA400

FlAgOO
FlCOQ 0

F2C400

neRO

FJQOOO-(

F,0800
F,lOFFf
F12000-(

B2S00
F.HFFF
F80000
fBFFf F

FUKlO 0
FFFFF F

MEMORY CONTROL/STATUS REG. 0
MEMORY CONTROL/STATUS REG. 1
MEMORY CONTROL/STATUS REG. 2
BOOTSTRAP ROM A
BOOTSTRAP ROM B
BOOTSTRAP ROM C
BOOTSTRAP ROM D
MASSBUS ADAPTOR 0 INT. REGISTERS
MASSBUS ADAPTOR 0 EXT. REGISTERS
MASSBUS ADAPTOR 0 MAP REGISTERS
MASSBUS ADAPTOR lINT. REGISTERS
MASSBUS ADAPTOR 1 EXT. REGISTERS
MASSBUS ADAPTOR 1 MAP REGISTERS
MASSBUS ADAPTOR 2 INT. REGISTERS
MASSBUS ADAPTOR 2 EXT. REGISTERS
MASSBUS ADAPTOR 2 MAP REGISTERS
UNIBUS 0 DATA PATH CONTROL & STATUS
UNIBUS 0 MAP REGISTERS
UNIBUS/DATA PATH CONTROL & STATUS
UNIBUS/MAP REGISTERS
UNIBUS 1 MEMORY SPACE \31 KW
UNIBUS 0 MEMORY SPACE 131 KW

Figure 9-4 • CMI Physical Address Space

. Synchronous Backplane Interconnect
The synchronous backplane interconnect (SEI) bus is the data path that
connects both the CPU and main memory of the large VAX systems to the

9-7

110 subsystem adapters. All UNIBUS, MASSBUS, CI bus, and DDI bus
devices communicate with the processor through the SBI bus. Figure 9-5
shows the basic configuration of the devices and adapters to the SBI. In the
VAX-1l1780 series processors, the memory controllers connect to the SBI
bus and all memory transactions are performed on the SBI. In the VAX
8600 processor configuration, the SBI adapters connect to the Mbox

through the A bus and the Mbox communicates with the main memory.
The SBIA 0 adapter is included with the processor and the SBIA 1 adapter
can be added to the system as an option. The SBI bus provides the following features:
• Transfers 64-bit data in two consecutive cycles .
• Permits a throughput rate of up to 13.3 million bytes per second and a
bus cycle time of 200 nanoseconds.
Performs distributed arbitration to increase transfer speed.
Includes a 16-level silo register that monitors the SBI operations and
maintains a history of the 16 most recent cycles of bus activity.
Includes maintenance registers to help in determining the cause of busspecific errors.

SBI Signal Lines
The SBI bus contains 84 signal lines that connect to each nexus. The bus
consists of arbitration, information, response, interrupt, and control lines as
shown in figure 9-6. The maximum physical length of the SBI bus is 3
meters (9.8 feet). Table 9-2 lists the signals on the lines and defines their
function.

Table 9·2 • SBI Signal Line Functions
Line

Description

TR15:TRO

Transfer Request-Sixteen arbitration lines that establish a
fixed priority to each nexus. Line TRO is the highest priority
and line TR15 is the lowest. Line TRO is used during the
SBI unjam operations. For the VAX 8600 CPU, line TR1 is
asserted to indicate that a DMA transfer from memory to a
device is requested and line TR2 is the CPU priority. The line
assignments are as follows:
Line Function
o
Hold (SBI unjam)
1
Memory controller 1 (VAX 8600: DMA data request
from memory)

9-8· Computer Bus Interconnects

Line

Description
Line Function
2
Memory controller 2 (VAX 8600: CPU priority)
UNIBUS adapter 1
3
UNIBUS adapter 2
4
UNIBUS adapter 3
5
6
UNIBUS adapter 4
Reserved
7
MASSBUS adapter 1
8
MASSBUS adapter 2
9
MASSBUS adapter 3
10
MASSBUS adapter 4
11
12-15 Reserved

B31:BO

Information - Multifunction lines that contain the address,
data, or function information.

Pl:PO

Parity- These lines provide even parity for detecting single
bit errors as follows:
Line Function
PO
Parity for the tag, identifier and mask fields
PI

-------

Parity for the information field

TAG2:TAGO

These lines contain an octal code from the transmitting
nexus to define the type of information on the information
lines as follows:
Value Definition
o
Read data
3
Command address
5
Write data
6
Interrupt summary read

ID4:IDO

Identifier- These lines contain a source or destination
code that identifies the logical source or destination of the
information contained on lines B31 :BO. The ID codes are
assigned to a commander or responder nexus and the identifying code is the same as defined for priority assignments
of the TR15 :TRO lines.

M3:MO

Mask - These lines are encoded by the transmitter to specify
the conditions and operations of the information on lines
B31:BO.

Fault

This line is asserted by a nexus to indicate that an error has
been detected in the SBI protocol or that a malfunction has
occurred in the information path.

9-9

Line

Description

CNFl:CNFO

Confirmation-A binary code that informs the transmitter
of the condition of the information received as follows:
Code Definition
o
No response to a commander's selection
1
A positive acknowledgement to a transfer
2
The busy response to a command/address transfer
from a nexus that is presently unable to execute the
command
3
The error response to a command/address transfer
from a nexus that cannot perform the command

Unjam

This line is asserted by the console to initialize all of the
nexuses to a defined state.

Fail

This line is asserted when the power supply AC LO signal to
the nexus is asserted and inhibits the CPU from initiating a
powerup service routine.

Dead

This line is asserted by the CPU clock module or terminating
networks to indicate that a power failure is impending and
prevents invalid data from being received by a nexus when
the bus is in an unstable state.

Interlock

Except for the VAX. 8600 processor, this line is asserted
by a memory controller during an interlock read mask or
interlock write mask function to insure exclusive access to
a specific memory location.

Clock

Six lines from the CPU clock module that provide clock
signals to synchronize the information transfers on the SBI.

REQ7 :REQ4

Request - Four lines assigned to each nexus that is capable
of interrupting the processor. The lines are priority-encoded
in an ascending order, with REQ4 as the highest priority.

Alert

This line is asserted by each nexus that does not have interrupt capability and informs the processor of a change in
status, power conditions, or operating environment.

MP12

Not used.

9-10' Computer Bus Interconnects

<r------"s:..:Y~N:..oC"'H:.:.R::.::O::.:N.:..:O"_U::::S::..:B::.:A..::C::.:K.::P..::L::.:ANE::=..::INf:..:..:..:E::.:R7<C:::O:::.:NNE..:.:..::::::C,,_T,-------,)

1 UNIBUS 1

ADAPTER

~
VAX-ll/780 Processor Series

'--------.:----.-J< ARRAY BUS >1 M~~Y 1

----,.0->
B

<-o,.,.-------=-=AB~US

8:0~::::R ~ ~ :~;~:s
~

1 '.,-,/ ADAPTERS
~CI

~ADAPTERS

~DDI

'.,-,/ ADAPTERS
VAX 8600 Processor

Figure 9-5' SBI Basic Bus Configuration

9-11

ARBITRATION
TR<15:oo>

INFORMATION TRANSFER

<
<
<

P<1:0> (PARITY)
TAG <2:0> (TAG)
ID<4:0> (IDENTIFIER)
M<3:0> (MASK)

B<31:oo> (INFORMATION)

TRANSMIT/
RECEIVE
NEXUS

•

RESPONSE
FAULT

>
>
>

>
>
>
•

(CNF<1:0> (CONFIRMATIONV
CONTROL

•
•
•

UNJAM
FAlL

DEAD
INTLK (INTERLOCK)
CLOCK (6 LINES)

TRANSMIT/
RECEIVE
NEXUS

··
•

)

INTERRUPT REQUEST

( REQ<7:4> (REQUEST) >
•

(

ALERT
MP1-2

SPARE (2 LINES)

)

Figure 9-6 • SBI Signal Lines

Sixteen transfer request lines (TR15 through TROO) are included to establish the access priority and one line is assigned to each nexus. Line TRO is
assigned the highest access priority and TR15 is the lowest. To acquire
control of the information path, a nexus asserts its transfer request line at
the beginning of the cycle. At the end of the cycle, the nexus examines the
state of all the transfer request lines that are assigned a higher priority. If a
higher priority nexus is not requesting control, the operating nexus
removes its request and asserts the information summary signals. In the
VAX-11/780 series processors, the CPU is assigned the lowest priority and
does not require a transfer line.
The information transfer group consists of 46 lines used to exchange
command/address and summary information. They include the parity,

9-12· Computer Bus Interconnects

information tag, source and destination identity, mask function and information lines. Each exchange consists of from one to three transfers.
The response group consists of three lines that contain error information
and information related to the coridition of the data transferred.
The control group consists of 10 lines that control the information transfer
operations. Six of the lines contain the clock signals used to synchronize
the information transfers. The control lines synchronize the system activities and provide specialized system communications. The lines provide initialization, powerfail, and restart functions for the system. In addition, a
path is provided for coordinating memories to assure access to shared
structures. The clock signals provide a universal time base for all nexus
operations. All SBI clock signals are generated on the CPU clock module
and have a 200-nanosecond cycle.
The interrupt request group consists of four interrupt reEIuest lines that are
assigned to each nexus and an alert line that indicates a change in status
power conditions or operating environment.
SBI Operation
Each\ nexus can transmit information to the SBI and receive information
from it. It also performs priority arbitration to gain access to the SBI. The
communication protocol allows the information path to be timemultiplexed so that up to 32 data exchanges can occur simultaneously. The
SBI provides checked, parallel information transfers that are synchronized
to the system clock. A nexus can perform interconnect arbitration and
information transfer during each clock period or cycle of 200 nanoseconds
to achieve a maximum transfer rate of 13.3 Mbytes per second. The nexus
can perform the following functions:
• As a commander, it transmits command and address information.
• As a responder, it recognizes command and address information directed
to it and responds to that information.
• As a transmitter, it controls the signal lines.
• As a receiver, it samples and examines the signal lines.
When the CPU issues a read command, the CPU assumes command
because it issues command/address information to the SBI. It also operates
as a transmitter because it controls the signal lines. When the device acting
as a responder returns the requested data, the CPU performs the function
of a receiver because it examines the signal lines.
Except for the VAX 8600 processor, when a memory read transfer occurs,
the memory is the responder and receiver because it recognizes and
responds to command/address information and examines the signal lines.
When memory returns the requested data, it operates as a transmitter. In

9-13

the VAX 8600 processor, the memory subsystem communicates through
the A bus and the SBIA performs all the necessary nexus functions for the
SBIbus_
Two or three successive SBI cycles are required for a write operation and
two successive cycles are used for the extended read operation and for an
interrupt read summary exchange.
To acquire control of the SBI bus, a nexus asserts its transfer request line at
the beginning of a clock cycle. At the end of a cycle, the nexus examines the
state of all the transfer request lines that have a higher priority. If a nexus
with a higher priority is not arbitrating for control of the SBI bus, the
controlling nexus removes its transfer request signal and asserts the information line signals. The CPU is assigned the lowest priority for line arbitration and does not require a transfer request signal. It gains control of the
SBI bus by default when no other nexus is arbitrating.

SBI Physical Address Space
The user has access to the SBI physical address space through a 30-bit
physical byte address. Because device registers are accessible only as
longword addresses, the 30-bit physical byte address is converted to a 28bit SBI longword address through a translation buffer. The process is
shown in fIgure 9-7. The 28-bits of the address'defines a longword address
space in the SBI that is grouped into a memory space and liD register
space. Bits 1 and 0 are used to align the data on a read operation. Figure 98 shows the SBI address space assignments; both physical and SBI
addresses are provided.
Information Transfer
Command/address, data, or interrupt summary information is transferred
during the information transfers. During write operations, the commander
uses two or three successive SBI cycles, depending on the number of data
words to be written in the exchange. For one data word, the commander
transmits the command!address in the first cycle and a data word in the
second cycle. For a two-word transfer, the commander transmits the
command!address in the fIrst cycle, the first data word in the second cycle,
and the second data word in the third cycle. Figure 9-9 shows the formats
of the information transferred.

9-14· Computer Bus Interconnects
VIRTUAL ADDRESS FOR OPERAND OR INSTRUCTION REFERENCE
313029
9 8

2 I 0

III

o 0 -PO
o I -PI

I 0 -SYS
I I - RESERVED

TRANSLATED FROM
TRANSLATION BUFFER
31 30

\
\

2726 25

___

L.~.~

~L.

21 20
0
IrV"I~p-RO-T-"-'rIM::';Ir---~rl::..----PA-G-E-F-RA-M-E-N-UM-BE-R------.:;'
~

______________

r---:==-=--=rT 1
2\ 1 0

/~/.~----~-L"

/ /"
/./.,,-/

//"/"

V'/

I-,-,

ADDRESS} 29'
91.
2 "\ 0
ON CPU
I I
P~~6~E~;
·L-_ _ _ _ _ _ _ _ _ _ _ _ _ _L _ _ _ _ _..J.._:_~
BUS

\
\

ARE USED TO
ALIGN DATA
READ BACK,
BUT ARE NOT

MEMORY IS
CONCERNED

ADDRESS}
ONSBI

BITS ONE
AND ZERO

~:~~~ANT AS

\
\

VIRTUAL ADDRESS
\ BITS 8,2 ARE
\ ALWAYS PHYSICAL
\ ADDRESS BITS \
\
\ <8,2>

L ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~.

BIT 29 BECOMES BIT 27 ON SBI BECAUSE MEMORY IS LONGWORD
ORIENTED AND FETCHES ARE QUADWORDS

Figure 9-7· Physical to SBI Address Translation

Read commands are also initiated with a command/address transmitted
from the commander. Because the data originates at the responder, the
request data may be delayed by the characteristic access time of the responder. As in a write operation, the read operation transmits data using one or
two successive cycles, depending on whether one or two data words were
requested.
An interrupt summary exchange is the response to a device-generated
interrupt to the CPU. The exchange is initiated with an interrupt-summaryread transfer from the CPU. The exchange is completed two cycles later
with an interrupt-summary-response transfer containing the interrupt
information .
• PARITY FIELD
The parity field provides even parity for detecting single-bit errors in the
information. A transmitting nexus generates parity for the tag, identifier,
and mask fields and parity for the information field. The PO and PI signals
are generated as the sum of all logical one bits, including the parity bit in
the checked field. When the SBI bus is idle, it assumes an all-zero state.

9-15
28-BIT SBI
LONGWORD
ADDRESSES

30-BIT
PHYSICAL BYTE
ADDRESSES

0000000

0000 0000

1-4MBYTE

MEMORY CONTROLLER 1

1-4MBYTE

MEMORY CONTROLLER 2

MEMORY

ADDRESS
SPACE

7FF FFFF
8000000

IFFF FFFF
20000000

TRO

8KBYTES

8000800

20002000

TRI

8KBYTES

8001000

20004000

TR2

8KBYTES

800 1800

20006000

TR3

8KBYTES
I
I
I
I
I
I
I

800 7000

2001 hoo

TR14

8KBYTES

8007800

2001 EOOO

TR15

8KBYTES

ADAPTOR OR
NEXUS REGISTER
ADDRESS SPACE
A TOTAL OF
128KBYTES

}

128K RESERVED
ADDRESS SPACE

8040000

20100000

UNIBUS 0 ADDRESS SPACE

8050000

2014 0000

UNIBUS 1 ADDRESS SPACE

8060000

20180000

UNIBUS 2 ADDRESS SPACE

8070000

210C 0000

UNIBUS 3 ADDRESS SPACE

FFF FFFF

3FFF FFFF

}

THE UNIBUS ADAPTOR
CAN ADDRESS ANY
ONE OF THESE
ADDRESS SPACES

Figure 9-8 • SBI Physical Address Assignments

• TAG FIELD
The transmitting nexus asserts the tag field to specify the type of transaction to be performed and to determine the interpretation of the information on lines B31:BO and the identifier field_ The tag field is also used in
conjunction with the mask field to define special read and write data conditions_ The command!address tag specifies that the data lines contain a
command/address word and that the identifier field contains a unique
code to identify the source (commander) of that command_ During a write
command, the identifier field indicates the source of the data and the

9-16' Computer Bus Interconnects

INFORMATION FIELD

P<I,O>

TAG < 2,0>

ID < 4,Q7 >

;

8<31,00>
1\
COMMAND FORMAT

M < 3,0>

FUNCTION
FIELD

I.
"

F <3,0>

ADDRESS
FIELD

A<27,OO>

Figure 9-9 • Information Transfer Formats

address information specifies the location where the data is to be written.
For a read command, the identifier code represents the destination of the
data at the location specified in the address lines. The octal code of the tag
field and the type of data being transmitted are defined in table 9-3_

Table 9-3' Tag Field Assignments
Code
000
001
010
011
100
101
110
111

Transaction
Read data
Reserved
Reserved
Command or address
Reserved
Write data
Interrupt summary read
Reserved

• IDENTIFIER FIELD
The identifier (ID) field contains a hexadecimal code that identifies the
logical source or destination of the information contained in the lines
B31:BO. The code corresponds to the priority assignments on the TR15-TRO
lines. For example, code 01 is assigned to memory controller 1. For the VAX
8600 processor, code 01 indicates that the memory is requesting the SBI
bus for a DMA transfer to a device. The VAX 8600 requests the SBI bus by
asserting line TR2; however, code 16 is used to specify the request. The
identifier field assignments are listed in table 9-4.

9-17

Table 9-4· Identifier Field Assignments
Code
00
01
02
03
04
05
06

07
08
09

10
11
12

13
14
15
16

Assignment
Hold
Memory controller 1 (VAX 8600: DMA request from memory)
Memory controller 2 (not assigned on the VAX 8600)
UNIBUS adap,ter 1
UNIBUS adapter 2
UNIBUS adapter 3
UNIBUS adapter 4
Reserved
MASSBUS adapter 1
MASSBUS adapter 2
MASSBUS adapter 3
MASSBUS adapter 4
Reserved
Reserved
Reserved
Reserved
CPU

• MASK FIELD
The functions performed by the mask field depend on the type of transaction that was selected. The mask is used with the read data, write data, and
command/address information as specified by the tag field. During a
command/address or write data operation, the mask field specifies the
number of bytes on lines B31 :BO to be interpreted. During a read data
operation, the mask field indicates the status of the data on lines B31 :BO.
The mask field contains all zeros to indicate an information-summary read
operation. Figure 9-10 shows the mask field formats for the command/
address or write data operations and the status format for a read data
operation. The mask field values are described in the command described
in the following paragraphs.

9-18' Computer Bus Interconnects
1 0
I PAR I

8
Z

4
0
"'::1- m - ' : ; I

3
13 1

+101 ~I
tl
~
0

'"""BYTE-3""""'I-B-YT-E-Z""--BYTE-1--r-B-Y T-E 0-"::'1

SELECT BYTE 0
SELECT BYTE 1
SEI,l!CT BYTE Z
SELECI' BYTE 3

Command!Address or Write Data Format

1 0
I PARI

r'4_ _-.::.,0

8 I

r"31'--_ _ _ _ _ _ _ _ _ _ _...::.,0

~ 1
...____D_A1:_A_L_O_N_GW_O_R_D_ _ _--'1
READ DATA
STATUS

Read Data Format

Figure 9-10 • Mask Field Formats

• FUNCTION FIELD
The command/address format contains a byte mask, function code field,
and a 28-bit physical address. The function codes are provided by information lines B31:B28 and are listed in table 9-5. If line A27 of the address
information is cleared, the address is in main memory, and if line A27 is set,
the address is in the I/O space.

Table 9-5 • Command!Address Function Codes
Function Command
Code *
0001
Read masked
0010
Write masked
Interlocked read masked
0100
Interlocked write masked
0111
Extended read (write mask ignored)
1000
Extended write masked
1011

* All other function codes are reserved and the write mask is ignored.

9-19

• TRANSFER FORMATS
The four basic types of information transfers are read data, command!
address, write data, and interrupt summary. The type of transfer is specified
in the tag field of the command information.

Read Data Tag A read data transfer is specified by a tag field value of 000
and indicates that the information field (B31 :BO) contains the data
requested by a previous command. The status of the retrieved data can be
one of three types-read data, corrected read data, or read data substituteand is identified by the mask field. The read data normally contains no
errors; however, if an error is detected, the condition of the data is identified. The destination of the data is specified by the identifier field. Figure 911 shows the format of the read data information and table 9-6 lists the
mask codes and read data status.

1 0

El [TG .I
~

4
ID

I~ I

DATA

DESTINATION

READ DATA
STATUS

INFORMAiION B3HO

Figure 9-11 • Read Data Formats

Table 9-6 . Read Data Mask Assignments
.Status
Mask
M3 M2 Ml MO
0
0
0

0
0
0

0
0
1

0
1
0

Data is correct
Data has been corrected
Data has uncorrectable error

Command/Address Tag A command!address transfer is specified by a tag
field value of 011 and indicates that the data lines contain a command/
address word. Six types of command!address transfers can be performed:
three read transfers and three write transfers. The information field
(B31:BO) contains a 4-bit function identifier (F3:FO) that specifies a read or
write sequence and an address location (A27:AO) that indicates where the
data will be read or written. The identifier field contains the logical destination of the data for a read data transfer and the logical source of the data
for a write data transfer. The contents of the mask field depends on the

9-20· Computer Bus Interconnects

type of transaction being performed. Figure 9-12 shows the format of the
information for command/address transfer. Table 9-7 defines the transfer
for each function code.
4

1 0

I PARI

8TI I
~

TAG

0
MASK

I I.

2827
FUNCTION

....

F3,FO

0
ADDRESS

A27,AO -

LOGICAL SOURCE/DESTINATION

Figure 9-12· Command/Address Format

Table 9-7 • Command!Address Functions
Mask

Function
F3 F2 FI FO

Transfer

Number of bytes

Read masked format - Data is
read at the specified address

Number of bytes

Interlock read masked format
- Data is read at the specified
address

All zeros

Extended read format - Data is
read at the specified address

Write data longword

Write masked format - Data is
written to the specified address

First write data

Interlock write masked longword format - Data is written
at the specified address

First write data

Extended write masked format
longword - Data is written at
the specified address

Bits A27 :AO define the longword address ~pace, which is grouped into two
sections. Addresses 0 through 7FFFFFF (hexadecimal) are reserved for primary memory and 8000000 through FFFFFFF (hexadecimal) are reserved
for device addresses. Each nexus is assigned a 2,048, 32-bit longword
address spaces for control and status. The addresses assigned are determined by the TR field, which specifies one of the address space block for

9-21

one of the 16 nexuses. Figure 9-13 shows the format of control address
space information.
31

28 27

ADDRESS

~I I

27 26

111

FUNCTION

15 14

MBZ

11 10

TR NO

.-..,.-

ADDRESS SPACE BLOCK

Figure 9-13 • Control Address Space Format

Write Data Tag A write data transfer is specified by a tag field value of
101 and indicates that the information on lines B31:BO contains the data to
be written at the location specified by the address field of the previous
write command. The data is asserted in the SBI cycle immediately following
the command! address cycle. The mask field is defined in table 9-8 and is
used to select one or more bytes of data in the information field that are to
be written. The ID field designates the commander that initiated the data
transfer. The format for the write data operation is shown in figure 9-14.

1 0

IpARI

EEG
~

0
ID

MASK

0
BYTE 3

BYTE 2

BYTE 1

COMMANDER

Table 9·8 • Write Data Mask Assignments
M3
M2
Ml
MO

Byte3 of the information (B31:B24)
Byte 2 of the information (B23:B16)
Byte 1 ofthe information (B15:B8)
Byte 0 of the information (B7:BO)

DATAB31oB0

Figure 9-14· Write Data Format

Bit Selection

BYTE 0

9-22· Computer Bus Interconnects.

Interrupt Summary Tag The interrupt summary sequence consists of a
transaction indicating the interrupt level being serviced and an identifying
response from the requesting device. The format of the interrupt request
and response is shown in figure 9-15. The interrupt request is specified by
a tag field value of 110 and indicates that the information on lines B7:B4 is
an interrupt level mask for the interrupt-summary read command. The
interrupt level mask specifies the interrupt level being serviced as a result
of the interrupt request. The ill field identifies the CPU as the commander.
A tag field value of 000 is the response that identifies the device that is
requesting the interrupt. The starting address of the service routine is
determined by the identity and interrupt level. The vector generating pair
of bits (B16 and BO) specifies the TR level of the nexus that requested the
interrupt. Two bits are used to insure that the parity is even. The service
routine is determined by the identity of the device and the interrupt level.
The ill field specifies the destination of the response. All other tag values
ate reserved.

1 0

I PARI

8 7

4 3

~ (MBZ I ,IL.--_MB_Z ---!I-L-+-'
--LI1I-:f-OI _MBZ---,I
--,,SOURCE

INTERRUPT
REQUEST LEVEL

Interrupt Request Level
1 0

I PAR

4
I
,

3
ID

~31~________~17TI~6r-__________T;0

I I MBZ I I~----------~~----------~
101

10 1

DEsmtATION
216

2 16

VECTUR GINERATING
BIT PAIR

Device Response

Figure 9-15 • Interrupt Summary Format

Read Masked Function The sequence of the SBI read transaction is shown
in figure 9-16. When a commander gains control of theSBI, it asserts the
information lines. The command!address format instructs the addressed
nexus to retrieve the addressed data word and to transfer it to the destination specified in the identifier field. Two SBI cycles after the assertion of the
command!address, the addressed nexus responds to the transfer with an
acknowledge message if it can perform the command.

SBI
ACTIVITY

--------ARBITRATION

INFORMATION
TRANSFER

EVENTS
----- ----------- ----

1---·

--------

-----

COMMANDER
I ACQUIRE
CONTROL

MEMORY
ACQUIRE
CONTROL

COMMAND
ADDRESS
(READ
MASK)

DATA
(TO A)

_ _ _ _ _ _ _ _ _ _ _ _ _ _ - ' -_ _ _L

-,-------,r- - CONFIRM
(BY
MEMORY)

CONFIRMATION

I
I"

CONFIRM
-(BY A)

---- ----

ZOO nsec

SBI CYCLE

----

•

Figure 9-16 • SBI Read Transaction

t;
w

9-24· Computer Bus Interconnects

Write Masked Function The write masked function is used to modify
stored data. It instructs the responder to modify certain bytes using data
transmitted in the succeeding cycle. The bytes to be modified are specified
by the mask signal. The memory or 1/0 address space is selected by line
B27. The timing sequence for both a single SBI write transaction and two
SBI write transactions is shown in figure 9-17.
Interlock-read-masked Function The interlock-read-masked function is
used with the interlocked-write-mask command to insure exclusive access
to a particular memory location. It causes the addressed nexus to retrieve
and transmit the addressed data in a similar operation as the read masked
function. The addressed memory controller asserts the interlock line and
the nexus responds with a busy confirmation to interlock the read-masked
commands. The interlock is cleared when the interlock-write-masked function is initiated.
Interlock-write-masked Function The interlock-write-masked function
instructs the addressed nexus to modify the bytes specified by the mask
field using the data transmitted in the succeeding cycle.
Extended Read Function The extended read function instructs the
addressed nexus to retrieve the 64 bits of data selected by address bits
A27:AO and to transmit the data to the nexus specified by the identifier
field in the command. The functions performed during this operation are
similar to the read masked transfer functions. The responder transmits the
data in two successive cycles with the low 32 bits preceding the high 32
bits. The mask code value transmitted from the commander is 0000. Figure
9-18 shows the extended read transactions to nexus A and B for the VAX11/780 processor series. A single and dual memory controller system is
shown. The separate memory controllers are designated Ml and M2. In the
VAX 8600 processor, the operation is similar except that the SBI communicates with the SBIA. The SBIA then communicates with the Mbox which
controls the memory.

9-25

Extended Write Masked Function The extended-write-masked function
instructs the addressed nexus that 64 bits of data are to be written. Bits
A27:AO indicate the low 32-bit address. The data to be written is transmitted in two 32-bit words. The first word corresponds to AO = 0 and the
second word corresponds to AO = 1. The mask field that accompanies the
command address transmission indicates the number of bytes to be written
in the first data word. The mask field that accompanies the first write data
word transmission indicates the nurrjber of bytes to be written in the second write data word. The mask field of the second data word cycle is
ignored by receivers but must be transmitted as zeros. The assertion of a
particular mask bit signifies that the byte corresponding to that mask bit is
to be modified. The component implementing the extended write masked
function must implement all com'binations of the mask signal.

~
0\

SBI
ACTIVITY

EVENTS

-----------------------------

--------ACQUIRE
CONTROL

ARBITRATION

HOLD

;:;;-

---------

-----------------------WRITE
MASK
COMMAND
ADDRESS

INFORMATION
TRANSFER

DATA

(CIA)

--------------

---------CONFIRM

CONFIRMATION

(CIA)

CONFIRM
(DATA)

--------------

------------------------

TIME

------l
~

I..

•

' - - 200 osee

r- SBI CYCLE

SBI TRANSACTION

Single Write Transaction
Figure 9-17 • SBI Write Transaction

a.~

SBI
ACTIVITY

EVENTS

--------------ARBITRATION

HOLDA

HOLDB

---------INFORMATION
TRANSFER

-----

WRITE
MASK
COMMAND
ADDRESS
A

DATA
A

WRITE
MASK
COMMAND
ADDRESS
B

CONFIRM
(CIA-A)

CONFIRMATION

DATA
B

CONFIRM
(DATA-A)

CONFIRM
(CIA-B)

CONFIRM
(DATA-B)

--------------TIME

I
----1
~

~ 200 osee
rSBI CYCLE

•

Dual Write Transaction
Figure 9-17 • SBI Write Transaction
'P

SBI
ACTIVITY

EVENTS

---

----

------_.

tl:l

E:;
ARBITRATION

MEMORY

MEMOR\'

HOLD

EXT
READ
CIA
A

INFORMATION
TRANSFER

HOLD

DATA

EXT
READ
CIA
B

8;:t

-----

DATA
2

DATA

DATA
2

(TO A)

(TO B)

;:t

'"
S

--CONFIRM
(TO A)

CONFIRMATION

CONFIRM
(BY A)

CONFIRM
(TO B)

CONFIRM
(BY A)

----

--------

I -II

CONFIRM
(BY B)

----

I TIME ~
'-------- 200 nsee

~SBICYCLE

Single Memory Controller
Figure 9-18' Extended Read Transactions

SBI
ACTIVITY

EVENTS
- - . - - - . - -..

------------------------------~-

--ARBITRATION

------Ml

HOLD

.M2

HOLD

Ml
DATA
1
(TO A}

Mj
DATA
2
(TO A}

M2
DATA
1
(TO B)

M2
DATA
2
(TO B)

CON·
FIRM
(BY A)

CONFIRM
(BY A)

EXT
READ
CIA
A

INFORMATION
TRANSFER

-----

EXT
READ
CIA
B

._CON·
FIRM
(TO A}

CONFIRMATION

CON·
FIRM
(TO B)

--------

CONFIRM
(BY B)

----

I -II

TIME

•

200nsec
SBI CYCLE

Two Memory Controllers
Figure 9-18· Extended Read Transactions
\0

,:",
\0

The VAX processor register space provides access to many types of CPU
control and status registers such as memory management base registers,
processor status longword, and the multiple stack-pointer registers. The
VAX privileged registers are accessible only by move to processor register
(MTPR) and move from processor register (MFPR) instructions, which are
controlled by the kernel executive in the VAXNMS operating system. The
operating system manages these registers for the user; however, they are
available to system programmers, operators, and maintenance personnel.
The VAX processor register space includes architecturally defined registers
that may be implemented in any VAX processor and registers that are
included only in a specific type of VAX processor.
Architectural Processor Registers
Table 10-1 is a list of the architectural processor registers, the register
address and type, and the VAX processors where the register is located.

Table 10-1" VAX Architectural Processor Registers
Register Name

Acronym Address Type* VAX**
Processor

Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer
PO Base
PO Length
PI Base
PI Length
System Base
System Length
Process Control Block Base
System Control Block Base
Interrupt Priority Level
Asynchronous System Trap Level
Software Interrupt Request
Software Interrupt Summary
Machine Check Status
Interval Clock Control/Status
Next Interval Count

KSP
ESP
SSP
USP
ISP
POBR
POLR
PIBR
PILR
SBR
SLR
PCBB
SCBB
IPL
ASTL
SIRR
SISR
MCSR
ICCS
NICR

RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW

14
15
17
18
19

RIW
R
RIW
RIW

01
02
03

04
08
09
OA
OB.
OC
OD
10

1
1
1
1
1
2
1
1
2
2
2
2
1
1

10-2· VAX Privileged Registers

Acronym Address Type* VAX**
Processor

ICR
Interval Count
TODR
Time-of-year
RXCS
Console Receive ControVStatus
RXDB
Console Receive Data Buffer
TXCS
Console Transmit ControVStatus
TXDB
Console Transmit Data Buffer
CAER
Cache Error
ACCS
Accelerator ControVStatus
MAPEN
Memory Management Enable
TBIA
Translation Buffer Invalidate All
Translation Buffer Invalidate Single TBIS
PMR
Performance Monitor Enable
SID
System Identification
TBCHK
Translation Buffer Check

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

20
21
22
23
27
28
38
39
3A
3D
3E
3F

W
W
R/W

R
W

1
1
1
1
1
1
1
1
2
2
2
2
1
1

* R/W is read or write, R is read-only, and-W is write-only
** (1) All VAX processor types
(2) All VAX processor types except VAX-11/725 and VAX-111730
• SYSTEM IDENTIFICATION REGISTER
The system identification (SID) register is a read-only constant register that
specifies the VAX processor type and the hardware and software revision
levels contained in the processor. The values in the SID register are
included in the error log. The type field may be used by software to distinguish processor types. Figure 10-1 shows the information format in the SID
register.

8 7

16 15

,I,
TYPF

TYPE SPEC

Figure 10-1 • System Identification Register Format

Bit

Function

31:24

TYPE-A binary number that identifies the model of the VAX
processor as follows:
Type
Assignment
o
Reserved for Digital Equipment Corporation

10-3

Bit

Function

2
3
4
5-127
128-255
23:0

VAX-ll/780 or VAX-11/785 processor as specified by
bits 23:22
VAX-11/750 processor
VAX-11/730 processor
VAX 8600 processor
Reserved for Digital Equipment Corporation
Reserved for Digital's Computer Special Systems (CSS)
group and customers

TYPE SPEC (Type specific)-Binary numbers used to identify the
microcode version and hardware revision levels assigned to the
system. The following bits are assigned to the processor types.

VAX-11/725 and VAX-111730 Processors:
Bits 23: 16- Not used
Bits 15:8-The software revision level of the CPU microcode
Bits 7:0- The revision level of the CPU hardware

VAX-1l/750 and VAX·l1l751 Processors:
Bits 23: 16- Not used
Bits 15:8 - The software revision level of the CPU microcode
Bits 7:0- The revision level of the CPU hardware

VAX·111780 and VAX· 111785 Processors:
Bits 23:22- The type of VAX processor where 1 is the VAX-11/780
processor and 0 is the VAX-11/785 Processor
Bits 21: 18 - The revision level of the CPU hardware
Bits 17: 15 - The letter assigned to the system revision level
Bits 14: 12 - The number assigned to the Digital Equipment
Corporation facility where the CPU was manufactured
Bits 11:0-The serial number assigned to the CPU

VAX-111782 Processor:
Bits 23: 16 - The engineering revision level of the CPU hardware
Bits 15: 12 - The number assigned to the Digital Equipment
Corporation facility where the CPU was manufactured
Bits 11:0-The serial number assigned to the CPU

VAX 8600 Processor:
The same configuration as the VAX-11/782 processor

10-4· VAX Privileged Registers

• PROCESS CONTROL BLOCK
The process control block, shown in figure 10-2, comprises locations in
memory used to store register information that is required by a process. A
process is the basic scheduled entity that is executed by the processor. The
process consists of an address space and both hardware and software context. The hardware context of the process is defined by the process control
block (PCB), which contains images of the general purpose registers, processor status longword (PSL), program counter (PC), per-process stack
pointers, and process virtual memory, which is defined by the base and
length registers. During the process execution, the contents of the PCB is
moved into the internal registers, where the hardware context is continually updated. When no process is executing, the PCB stores the contents of
the registers for future use.

Kernel mode stack pointer
Executive mode stack pointer
Supervisor mode stack pointer
User mode stack pointer
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
Processor Status Longword
Program Region Base Register
I Program Region Length Register
Control Region Base Register
I Control Region Length Register
0
22121

Figure 10-2 • Process Control Block Structure

10-5

Kernel Stack Pointer Register The kernel stack pointer (KSP) is a readwrite register that contains the address of the kernel-mode program used
when the current access-mode field in the PSL is zero and the interrupt
stack equals zero. Figure 10-3 shows the format of the KSP register.

g 7

16 15

24 23

I
I

KSP DDR

Figure 10-3 • KernelStack Pointer Register Format

Bit

Function

31:0

KSP ADDR (Kernel stack pointer address)-Contains the stack
pointer address of the kernel-mode program.

Figure 10-4 • Executive Stack Pointer Register Format
Bit

Function

31:0

ESP ADDR (Executive stack pointer address) - Contains the stack
pointer address of the executive-mode program.

Bit

Function

31:0

SSP ADDR (Supervisor stack pointer address) -Contains the stack
pointer address of the supervisor-mode program.

Figure 10-5 • Supervisor Stack Pointer Register Format

Figure 10-6· User Stack Pointer Register Format
Bit

Function

31:0

USPADDR (User stack pointer address)-Contains the stack
pointer address of the user-mode program.

Bit

Function

31:0

ISP ADDR (Interrupt stack pointer address) - Contains the last
address of the process routine in memory prior to the interrupt.

Figure 10-7· Interrupt Stack Pointer Register Format

10-6· VAX Privileged Registers

Executive Stack Pointer Register The executive stack pointer (ESP) is a
read-write register that contains the address of the executive-mode program selected when the current access-mode· field in the PSL register is
equal to zero. Figure 10-4 shows the format of the ESP register.

16 15

(

8 7

,I,

Figure 10-4 • Executive Stack Pointer Register Format

Supervisor Stack Pointer Register The supervisor stack pointer (SSP) is a
read-write register that contains the address of the supervisor-mode program selected when the current access mode field in the PSL register equals
two. Figure 10-5 shows the format of the SSP register.

8 7

2423

,I,
SSPADDR

Figure 10-5' Supervisor Stack Pointer Register Format

User Stack Pointer Register The user stack pointer (USP) is a read-write
register that contains the address of the user-mode program selected when
the current access-mode field in the PSL equals three. Figure 10-6 shows
the format of the USP register.

24 23

,I,

16 15

,~ ,

8 7

,I,

USPDDR

Figure 10-6 • User Stack Pointer Register Format

Interrupt Stack Pointer Register When the processor changes states from
the process context to the interrupt service context, the address information in general register R14 is loaded into the interrupt stack pointer (ISP)

10-7

register. This is a read-write register that insures a continuation of the process after the interrupt has been serviced. Figure 10-7 shows the format of
the ISP.
24 23

8 7

16 15

I II
ISP ADDR

Figure 10-7 • Interrupt Stack Pointer Register Format

• VIRTUAL ADDRESS SPACE
The virtual address space is a linear array of 4 Gbytes of memory separated
into 512-byte units called pages. The virtual address space has two parts,
the per-process space and the system space, as shown in figure 10-8. The
per-process space is the lower addressed half and is separated into the
program region and the control region, each consisting of 1 Gbyte of memory. The system space consists of a system region and a reserved region,
each containing 1 Gbyte of memory. The privileged registers used to select
the memory locations are described in the following paragraphs.

00000000
PO REGION
PAGE LENGTH
PO PROGRAM REGION
PO GROWTH REGION

3FFFFFFF

40000000

PERPROCESS
SPACE

PI GROWTH REGION
PI CONTROL REGION
PI REGION
PAGE LENGTH

7FFFFFFF
80000000

SYSTEM REGION
PAGE LENGTH
SYSTEM REGION
SYSTEM GROWTH
REGION

BFFFFFFF
COOOOOOO

RESERVED REGION

FFFFFFFF

Figure 10-8 • Virtual Address Space Allocations

SYSTEM
SPACE

10-8· VAX Privileged Registers

Per-Process Space Each process in the per-process space has a separate
translation map; therefore, processes may not be contiguous. The program
and control regions are defined by the following registers.
PO Base Register The PO program region of the virtual address space is
mapped by the PO page table (POPT), which is defined by the PO base
register (POBR) and by the PO length register (POLR). The POBR is a readwrite register containing the virtual address of the program region that is
the base address of the POPT. Figure 10-9 shows the format of the POBR.

31 30 29

2423

16 15
I

1 I

2 1 0

8 7
I

I 1

SYST VIRT L GWD ADDR

MHZ

JJ
MHZ

Figure 10"9 • PO Base Register Format

Bit

Function

31:30 MBZ(Mustbezero).
29:2

SYST VIRT LNGWD ADDR (System virtuallongword address)Contains the base address of the PO program region in virtual
memory.

1:0

MBZ (Must be zero).

PO Length Register The PO length register (POLR) is a read-write register
that specifies the number of longwords in the POPT. Figure 10-10 shows
the format of the POLR.

16 15
I

I 12.7(6. . 24 2322(1

•
M\Z

1
1
~'t
NOT

MBZ

8 7

II
PO REGN LNGTH

USED

Figure 10-10 • PO Length Register Format

10-9

Bit

Function

31:27

MBZ(Mustbezero).

26:24

Not used.

23:22

MBZ (Must be zero).

21:0

PO REGN LNGTH (PO region length) - The length of the PO region
in longwords.

Pi Base Register The PI region of the address space is mapped by the PI
page table (PIPT), which is defined by the PI base register (PIBR) and the
PI length register (PILR). The PIBR is the read-write base register for the
page table that describes the process virtual address. Figure 10-11 shows
the format for the PIBR.
31

24 23
I

16 15

I I

1
I

VIRT LNGWD ADDR

2
I

1 0

IJ
MBZ

Figure 10-11 • Pi Base Register Format

Bit

Function

31:2

VIRT LNGWD ADDR (Virtuallongword address) - The base
address of the PI control region in memory.

1:0

MBZ (Must be zero).

Pi Length Register The PI length register (PILR) is a read-write register
that contains the length of the PI control region in pages. The PI space
expands toward the smaller addresses; therefore, the PILR contains the
number of nonexistent page table entries (PTEs). Figure 10-12 shows the
format of the PILR.

10-10· VAX Privileged Registers
31 30

24 23 22 21

It"!,,, I, I 'ft
MBZT

8 7

16 IS

I •

~ • I.

PI REGION LENGTH

IGNR/RTNO

Figure 10-12· Pl Length Register Format

Bit

Function

IGNRlRTN 0 (Ignore/return as zero) - Ignored on a wri~e
instruction and returned as zero on a read instruction to the
register.

30:22

MBZ (Must be zero).

21;0

PI REGN LNGTH (PI region length)-A binary number that is the
length of the PI region in longwords .

• SYSTEM SPACE
The system virtual address space is defined by the system page table (SPT),
which is a vector of page table entries (PTEs). The SPT is located in the
physical address space. The base address of the SPT is also a physical
address and is contained in the system base register (SBR). The size of the
SPT in longwords is contained in the system length register (SLR).
System Base Register The system base register (SBR) is a read-write regis-

ter that contains the base address of the SPT and points to the first PTE in
the table. The PTEs contain the mapping information or point to mapping
information in the global page table. Figure 10-13 shows the format of the
SBR.
31 30 29

8 7

2423

I II

Ltd",I,
PHYS LNGWD ADDR
IGNR/IITN o·

Figure lO-13 • System Base Register Format

MBZ

10-11

Bit

Function

31:30

MBZ (Must be zero).

29:2

PHYS LNGWD ADDR (Physicallongword address) -Contains the
base address of the SPT in memory.

1:0

MBZ (Must be zero).

System Length Register The system length register (SLR) is a read-write
register that contains the length of the system region in pages which is the
length of the SPT in longwords. Figure 10-14 shows the format of the SLR.
8 7

24 23 22 21

! . · I . 1.
SYST REGN LNGTH

MBZ

Figure 10-14 • System Length Register Format

Bit

Function

31:22

MBZ (Must be zero).

21:0

SYST REGN LNGTH (System region length) - Contains a binary
number that specifies the length of the system region in
longwords.

Process Control Block Base Register The process control block base
(PCBB) is a read-write register that contains the physicallongword address
of the current executing process in the PCB. Figure 10-15 shows the format
of the information in the register.
31 30 29

24 23

GI·

.I.

MBZ

8 7

16 15
,

•• I

.I.

PHYS LNG"'WD ADDR

Figure 10-15 • Process Control Block Base Register Format

2 1 0

LJ
MBZ

10-12 • VAX Privileged Registers

Bit

Function

31:30

MBZ (Must be zero).

29:2

PHYS LNGWD ADDR (Physicallongword address) -Contains the
physicallongword address of the PCB.

1:0

MBZ (Must be zero).

System Control Block Base Register The system control block (SCB) is a
page containing the vector addresses by which the exceptions and interrupts are dispatched to the appropriate service routines. The system control block base (SCBB) is a read-write register that contains the physical
address of the SCB, as shown on figure 10-16.

31 3029

[J,

24 23
1

16 15
1 1

I 1 1 1
¥

PHYS SCB PAGE ADDR

MBZ

9 8 7

11 I

0
1

MBZ

Figure 10-16 • System Control Block Base Register Format

Bit

Function

31 :30

MBZ (Must be zero).

29:9

PHYS SCB PAGE ADDR (Physical SCB page address) - A binary
number that specifies the physical address of the system control
block.

8:0

MBZ (Must be zero) .

• PROGRAM INTERRUPTS
The processor services interrupt requests between instruction processing
and at specific points during the execution of long interactive instructions.
Fifteen priority-interrupt levels are assigned to software and all levels must
be lower than the current processor-interrupt priority level.

10-13

The interrupt priority level (IPL) is a
read-write register that enables the processor priority to be monitored or
changed. During write operations to the IPL, the priority level from 19
through 1D (hexadecimal) can be selected and will be loaded into the
processor status longword (PSL) bits 20 through 16. During read operations, the current priority level from the PSL is read from the IPL. Figure
10-17 shows the format of the IPL register.

Interrupt Priority Level Register

24 23

I•

16 15
I

I I I I

8 7

5 4

I L

LOTAD
CPU PRIOR

IGNRiRTN 0

Figure 10-17 • Interrupt Priority Level Register Format

Bit

Function

31:5

IGNRlRTN 0 (Ignore/return as zero)- This field is ignored on a
write instruction and returned as all zeros on a read instruction to
the register.

4:0

LOAD CPU PRIOR (Load CPU priority) - A hexadecimal number
from 19 to 1D (hexadecimal) that selects the interrupt priority
level to be assigned to the processor level.

An asynchronous system trap (AST)
is a software-simulated interrupt used to notify a process of events that are
not synchronized with its execution and to initiate the processing of AST
routines that service the event. A program can request an AST routine after
an I/O operation is completed, when the time interval expires, when power
is restored after a failure, and after other events. The asynchronous system
trap level (ASTL) is a read-write register (ASTLR) containing the number of
the most privileged access mode for which the AST is pending, as shown in
figure 10-18.

Asynchronous System Traps Register

2423

16 15
I

IGNR/RTNO

320

AST
LEVEL

Figure 10-18 • Asynchronous System Trap Level Register Format

10-14· VAX Privileged Registers

Bit

Function

31:3

IGNRlRTN 0 (Ignore/return as zero)-This fidd is ignored on a
write instruction and returned as all zeros on a read operation.

2:0

AST LEVEL (Asynchronous system trap levd)- The binary number
that indicates the AST levd of the access mode pending are as
follows:

Value Mode
Kernd
1
Executive
2
Supervisor
3
User
4
No AST pending
5-7
Reserved for Digital Equipment Corporation

Software Interrupt Request Register The software interrupt request register (SIRR) is a write-only register used for making software interrupt
requests. One of 15 interrupt request levds can be specified during a write
operation to register bits 3 through o. The format of the SIRR is shown in
figure 10-19.

2423

I.. ,

8 7

16 15

IGNR

I,
SFTWINT
REQ

Figure 10-19' Software Interrupt Request Register Format

Bit

Function

31:4

IGNR (Ignored) - These bits are ignored.

3:0

SFIW INTR REQ (Software interrupt request) - A hexadecimal
number from 01 to OF used to sdect a software interrupt levd.

10-15

The software interrupts levels
that are pending are recorded in the software interrupt summary register
(SISR). The format of this read-write register is shown in figure 10-20.

Software Interrupt Summary Level Register

2423

8 7

16 15

MBZ

1 0

SFTW [NT PEND

MBZ:J

Figure 10-20 • Software Interrupt Summary Register Format

Bit

Function

31:16 MBZ (Must be zero).
15: 1

SFTW INT PEND (Software interrupts pending) - Fifteen bit
positions, 1 through F (hexadecimal), with each position set to
indicate the level of the pending software interrupt and 0 as the
lowest inter;upt priority.

MBZ (Must be zero) .

• SYSTEM CLOCKS
The VAX systems contain two clocks: a time-of-year clock and an intetyal
clock. The time-of-year clock is used by the operating system to measure
the duration of a power failure, to restart the system after a power loss, and
to reinitialize the time and date after power has been restored. The time-ofyear clock also is used to time-stamp user and operating system programs.
The interval clock is used for accounting, for time-dependent events, and
to maintain the software date and time.
Time-of Year Register The time-of-year function is implemented by a
read-write longword register (TODR) that forms an unsigned 32-bit binary
counter and is driven by a precision clock source. The clock is accurate
within 65 seconds per month (0.0025 percent); the range varies with ambient temperature and the charge on the battery backup unit. The battery
backup will supply power for a maxmmm of 100 hours of operation after a
power interruption and is recharged automatically. The clock count is continuous during transition to or from standby power. The least significant
bit of the counter represents a resolution of 10 milliseconds. The counter
cycles to zero after approximately 497 days. If the battery failure disrupts

10-16' VAX Privileged Registers

the clock, the register is cleared on powerup and remains at zero until the
time is reset by software. In the VAX-1l1780 series processors, if the software initializes the clock to a value corresponding to a large unit of time
such as a month, it can determine the length of downtime by checking the
difference between the clock reading and the actual time that the power is
restored. In the VAX-1l1750 processor, the register remains cleared until a
value is entered and the count then is initiated. The is TODR shown in
figure 10-21.

8 7

2423

, I,

, I,
TOY CLOCK

Figure 10-21 • Time-of Year Register Format

Bit

Function

31:0

TOY CLOCK (Time-of-year clock) - A 32-bit binary counter

incremented at every lO-millisecond interval.

The interval clock provides an interrupt at IPL 24 at programmed intervals. The counter is incremented at one-microsecond intervals, with a typical accuracy of 0.01 percent or 8.64 seconds per day. The
accuracy will vary slightly with ambient temperature changes. The clock
interface consists of three registers: the interval count register (ICR), the
next interval count register (NICR), and the interval clock controVstatus
(ICCS) register.

Interval Clock

The interval .count register (ICR) is a read-only
register that is incremented once every microsecond. It is automatically
loaded from the NICR when a carry bit (bit-31 overflow) occurs. A carry bit
also causes an interrupt request at IPL 24 if the interrupt is enabled. Figure
10-22 shows the ICR format.

Interval Count Register

2423

, I,

16 15

8 7

, I,

INTVLCNT

Figure 10-22 • Interval Count Register Format

10-17

Bit

Function

31:0

INTVL CNT (Interval count) -Contains the interval count, which is

incremented at one millisecond intervals.

Next Interval Count Register The next interval count register (NICR) is a
write-only register that holds the value to be loaded into the ICR when the
ICR overflows. The value is retained when the ICR is loaded. The NICR can
be loaded regardless of the values contained in the ICR and ICCS. Figure
10-23 shows the format of the NICR.

2423

16 15
I

8 7

NEXT INTVL CNT

Figure 10-23 • Next Interval Count Register Format

Bit

Function

31:0

NEXT INTVL CNT (Next interval count) - Contains the next
interval count value loaded by software.

Interval Clock ControllStatus Register The interval clock control/status
(ICCS) is a read-write register that contains control and status information
for the interval clock. The format of the information in the register is
shown in figure 10-24.

31 30

ERRJ'

2423
I

I II

16 15
I

I ,

I II

8 765 4 3

II Jill

MBZ]
Figure 10-24 • Interval Clock ControllStatus Register Format

1 0

10-18· VAX Privileged Registers

Bit

Function

ERR (Error) - Set to indicate that one or more clock counts have
been. missed. This bit is set if INT (bit 7) is set when an ICR
overflow occurs. An attempt to set this bit by the MTPR instruction
will clear ERR.

30:8

MBZ (Must be zero).

INT (Interrupt) - Set by hardware when the ICR overflows. If the
INT ENB (bit 6) is set, an interrupt is generated. An attempt to set
this bit by the MTPR instruction will clear INT and reenable the
clock count interrupt if INT ENB (bit 6) is set.

INT ENB (Interrupt enable) - When this bit is set, an interrupt
request at IPL 24 is generated every time the ICR overflows. When
this bit is clear, no interrupt is requested. If INT is already set and
the software sets this bit, an interrupt is generated. This bit is
cleared during the bootstrap loading sequence.

SGL (Single) - This is a write-only bit. If the RUN (bit 0) is clear
when this bit is set, the ICR is incremented by one.

XFR (Transferred) - This is a write-only bit. Each time this bit is
set, the value in the NICR is transferred to the ICR.

3: 1

MBZ (Must be zero).

RUN - When set, the ICR is incremented every microsecond. When
this bit is clear, the ICR does not increment automatically. At
bootstrap loading time, this bit is cleared .

• CONSOLE TERMINAL REGISTERS
The console terminal is accessed through four internal registers. Two registers, the C'onsole receive control/status (RXCS) and console receive data
buffer (RXDB), are used for receiving information from the console. The
console transmit control/status (TXCS) register and the console transmit
data buffer (TXDB) register are used for writing information to the console
terminal. The functions and type of console registers vary, depending on
the VAX system. Refer to the register description of each VAX processor for
details on console register functions.

Console Receive ControllStatus Register The console receive control/
status (RXCS) is a read-write register that.is cleared during hardware initial-,
ization. Figure 10-25 shows the format of the RXCS and describes the bit
assignments.

10-19
24 23

(

16 15
I

765

I ~ I

MBZ

INTENB~

DONE]

Figure 10-25 • Console Receive Control/Status Register Format

Bit

Function

31:8

MBZ (Must be zero).

DONE- A read-only bit that is set by the console when data is
received by the RXDB and cleared when the MFPR instruction is
performed with RXDB as the destination.

INT ENB (Interrupt enable) - When set by software, an interrupt is
generated on the interrupt priority line (IPL 20) when DONE (bit
7) is set. If the DONE bit has been previously set and the software
sets this bit, an interrupt is also generated.

5:0

MBZ (Must be zero).

Console Receive Data Buffer Register The console receive data buffer
(RXDB) is a read-only register that receives information from the terminal
for transmission to the processor. Figure 10-26 shows the format of the
RXDB and the bit assignments.

2423

MBZ

t ~mz

DATA

ERR-.J

Figure 10-26 • Console Receive Data Buffer Register Format

10-20· VAX Privileged Registers

Bit

Function

31:16 MBZ (Must be zero).
15

ERR (Error) - Set if the received data contains an error such as
overrun or loss of connection.

14: 12

MBZ (Must be zero).

11:8

ID (Identification) - A hexadecimal number that identifies the
source or function of the data (bits 7 :0) received by the console
subsystem.
ID = 0: console terminal
ID = 1 through F: implementation dependent

7:0

DATA - The data received from the console subsystem device.

Console Transmit ControllStatus Register The console transmit controV
status (TXCS) is a read-write register that contains the console transmit
control and status information. Except for the RDYbit, the register is
cleared during hardware initialization. Figure 10-27 shows the format of
the TXCS register.

[

2423
I

16 15
I

~ I
MHZ

8 7 6 5
I

II( I
RDyJJ
I

MBZ

INTENB

Figure 10-27 • Console Transmit ControllStatus Register Format

Bit

Function

31:8

MBZ(Mustbezero).

RDY (Ready) - A read-only bit set during bootstrap loading and
when the console transmitter is not busy. Cleared when the MTPR
instruction is executed with the TXDB register designated as the
source.

10-21

Bit

Function

INTENB (Interrupt enable)-A read-only bit set by software to
generate an interrupt request priority line (IPL 20) when the RDY
(bit 7) is set. If the RDY bit is already set and the INT ENB bit is set
by software, an interrupt is also generated. This bit is cleared when
an MTPR instruction is executed with the TXDB register designated
as the source.

5:0

MBZ (Must be zero).

Console Transmit Data Buffer Register The console transmit data buffer
(TXDB) is a write-only register that receives the data from the processor for
transmission to the console terminal. Figure 10-28 shows the format of the
TXDB register and describes the bit assignments.

16 15

2423
I

I ; I
I

1211
I

MBZ

8 7

0
I

DATA

Figure 10-28 • Console Transmit Data Buffer Register Format

Bit

Function

31:12

MBZ (Must be zero).

11:8

ill (Identification) - A hexadecimal value used as a select code to

identify the. console terminal, console storage device, or
communication function, as follows:
Select
Device
Data Field
code (In)
o
Console terminal
ASCII data (0 through 7F
hexadecimal)
1

Console drive 0

Binary data (0 through FF
hexadecimal)

Function complete
complete

Status

Protocol error

Ignored

10-22 • VAX Privileged Registers

Bit

Function
. Drive 0 command
command

o = read sector
1 = write sector
2 = read status

3 = write deleted
data sector
4 = cancel function
5 = protocol error error
Miscellaneous
communication

o = no operation
1 = software done
2 = boot CPU
3 = clear restart flag
4 = clear bootstrap flag

* Sent by the console when a load device command is issued before a
previous command is completed or the console receives a select code 1
when expecting a command.
7:0

DATA - The data, status, or function information of the device
selected by the ID (bits 11:8) .

• MEMORY REGISTERS
Several memory registers are available to control the memory management
function and the translation of physical addresses to virtual addresses.

Memory Management Enable Register The translation of a virtual address
to a physical address is controlled by the memory management enable register also called the map enable register (MAPEN). This read-write register
is cleared during the processor initialization. Figure 10-29 shows the format of the MAPEN register.

(

1615

2423
I

8 7
I

1 0

I
MEMMAPENBJ

Figure 10-29 • Memory Management Enable Register Format

10-23

Bit

Function

31:1

MBZ (Must be zero).

MEM MAP ENB (Memory map enable) - Set to enable the memory
management control.

Translation Buffer Invalidate All Register The translation buffer invalidate all (TBIA) is a write-only register used to invalidate the process pages
in the translation buffer when the software changes a system page-table
entry. The format of the TBIA is shown in figure 10-30 and writes all zeros
into the translation buffer.
31

2423

8 7

16 15

MBZ

Figure 10-30 • Translation Buffer Invalidate All Register Format

Bit

Function

31:0

MBZ(Mustbezero).

Translation Buffer Invalidate Single Register The translation buffer invalidate single (TBIS) is a write-only register used to move a virtual address
into the translation buffer when the software updates any part of a valid
page table entry for the system or a current process region. The format of
the address information is shown in figure 10-31.

2423

8 7

16 15

VIRTADDR

Figure 10-31 • Translation Buffer Invalidate Single Register Format

10-24 • VAX Privileged Registers

Bit

Function

31:0

VIRT ADDR (Virtual address) - The virtual address of the current

memory reference.

Translation Buffer Check Register The translation buffer check (TBCHK)
is a write-only register available for checking the presence of a valid translation in the translation buffer. Figure 10-32 shows the format of the information in the register.

2423

8 7

, 1 ,

,.1 ,

VIRTADDR

Figure 10-32 • Translation Buffer Check Register Format

Bit

Function

31:0

VIRT ADDR (Virtual address) - The virtual address to be checked
in the translation buffer. If a valid translation is performed for the
virtual page, the condition code V bit is set.

Machine Check Status Register' The machine check status register (MCSR)
is a read-only register used with the machine check error status (MCESR)
-register to provide additional information about bus errors and translation
buffer errors that caused a machine check. The register is cleared during
the bootstrap loading sequence. The format of the information in the
MCSR is shown in figure 10-33 and the bit assignments are described.

31'

2423
I

J J
MBZ

MEMDSBL
RDLOCKTMO

TB GRP ERR

MBZ r

HIT/MIS.J

Figure 10-33 • Machine Check Status Register Format

BUS ERR

10-25

Bit

Function

31:17

MBZ (Must be zero).

MEM DSBL (Memory disable) - A read-only by software bit that is
set to allows only the cache memory to be read from or written to
and main memory cannot be referenced or modified. This results
in a failure of the cpu.

15:13

MBZ (Must be zero).

RD LOCK TMO (Read lock timeout) - A software read-only bit that
is set by a read lock timeout and defines the interpretation of the
bus error (bits 3 :0).

11:8

TB GRP ERR (Translation group errors) -Read-only bits that define
the type of translation buffer group parity error and are cleared
when TB error (bit 2) of the MCESR is reset.

7:5

MBZ (Must be zero).

HIT/MIS (HitiMiss)-A read-only bit that is set when the
. microcoded reference results in a hit or a miss.

3:0

BUS ERR (Bus error) - Read-only bits that are set to define the type
of bus error. They are also cleared when bus error (bit 3) of the
MCESR is cleared. The function of the bits when set are as follows:

Bit 3 - Indicates that the memory location addressed does not exist
or that a read-lock timeout has occurred.
Bit 2 - Indicates that an uncorrectable data error has occurred.
Bit 1-Indicate that a bus error has occurred and was not
corrected.
Bit O-Indicates that the data error has been corrected.

VAX·111725 and VAX·111730 Processor-specific Registers
In addition to the architectural processor registers, the VAX-1l1725 and
VAX-1l1730 processors contain the specific registers defined in this section
and listed in table 10-2. Table 10-2 lists the register acronym, the hexadecimal processor address, and the register type.

10-26· VAX Privileged Registers

Table 10-2· VAX-1l1725 and VAX-ll/730 Processor-specific Registers
Register Name

Acronym

Address

Type*

Console Storage Receive/Status
Console Storage Receive Data
Console Storage Transmit/Status
Console Storage Transmit Data
Accderator Control/Status

CSRS
CSDR
CSTS
CSTD
ACCS

lC
ID

R/W
R/W
R/W
R/W
R/W

1E
IF

* RIW is read or write

• TU58 CONSOLE STORAGE
The TU58 console tape-cartridge subsystem is accessed through four internal registers. The console storage receive status (CSRS) and the console
storage receive data (CSRD) registers are associated with receiving information from the TU58 drive for transmission to the processor. The console
storage transmit status (CSTS) and the console storage transmit data
(CSTD) registers are associated with writing information on the tape from
the processor.

Console Storage Receive Status Register The console storage receive status
(CSRS) is a read-write register used to control receive operations and to
transmit receive-status information to the processor. Figure 10-34 shows
the format of the assigned bits in the register.

2423

,I,

16 15

8 7 6 5

,l ' , I ,
M8Z

INTEN8~

DONE]

!'
MBZ

Figure 10-34 • Console Storage Receive Status Register Format

10-27

Bit

Function

31:8

MBZ (Must be zero).

DONE- A read-only bit set by the TU58 tape drive whenever a byte
of data is received by the TU58 from the CSRD register. It is cleared
during hardware initialization whenever a MFPR instruction is
executed with the CSRD register as the destination.

INT ENB (Interrupt Enable 0) - Set by software to enable an
interrupt to be generated on the priority line (IPL 23). If the DONE
bit already has been set and the IE bit is set by the software, an
interrupt is generated. This bit is cleared during hardware
initialization.

5:0

MBZ (Must be zero).

Console Storage Receive Data Register The console storage receive data
(CSRD) is a read-only register that receives the information from the TU58
tape drive for transfer to the processor. Figure 10-35 shows the format of
the CSRD register.

2423

16 15
I

MBZ

8
I

0
I

DATA

Figure 10-35 • Console Storage Receive Data Register Format
Bit

Function

31:8

MBZ(MustBezero).

7:0

DATA- This field contains a byte of data received from the TU58
tape subsystem.

10-28· VAX Privileged Registers
Console Storage Transmit Status Register The console storage transmit
status (eSTS) is a read-write register that provides the control and status
for the TU58 transmit operations. The format· for the eSTS register is
shown in figure 10-36.

2423

,I , , l ' , I ,

MBZ

1 0

8 765

16 15

, ,

,I I I I , , I I

l~i~J

MBZ

L1NEBRK

Figure 10-36· Console Storage Transmit Status Register Format

Bit

Function

31:8

MBZ(Mustbezero).

RDY (Ready) - A read-only bit that is set during bootstrap loading,
and when the TU58 tape drive is not busy.

INT ENB (Interrupt enable) - Set by software to generate an
interrupt at IPL 23. If the RDY (bit 6) already has been set, an
interrupt request will be generated when this bit is set.

5:1

MBZ(Mustbezero).
LINE BRK (Line break) - A write-only bit set to generate a line
break.

Console Storage Transmit Data Register The console storage transmit data
(eSID) is a write-only register that contains the data to be transferred to
the TU58 drive from the processor. Figure 10-37 shows the format of the
information in the eSID register.

2423

I II

16 15

t I II
I

MBZ

8 7

I II
n

DATA

Figure 10-37 • Console Storage Transmit Data Register Format

10-29

Bit

Function

31:8

MBZ(Mustbezero).

7:0

DATA - Contains the data for transfer to the TU58 tape drive .

• FP730 FLOATING-POINT ACCELERATOR
The FP730 floating-point accelerator option contains an internal read-write
accelerator control/status (ACCS) register that indicates whether an FP730
option is installed, controls whether it is enabled, identifies its type, and
reports errors and status. During hardware initialization, the type and
enable values are set and any error indications are cleared. Figure 10-38
shows the format of the information in the ACCS register.

16 15 14

24 23

MBZ

ENB~

I I
T

MBZ

1 !
I

1
I

[YPE

Figure 10-38 • FP730 Accelerator Control/Status Register Format

Bit

Function

31:16

MBZ(Mustbezero).

ENB (Enable) - A read-only bit that specifies whether the
accelerator is enabled. This bit is set if the accelerator is installed
and functioning.

14:8

MBZ (Must be zero).

7:0

TYPE- A read-only binary number that specifies the accelerator
type as follows:

o = No accelerator
1 = Floating-point accelerator
2 through 127 = Reserved for Digital Equipment Corporation
128 through 255 = Reserved to Digital's CSS group customers

10-30· VAX Privileged Registers

VAX-1l/750 and VAX-1l/751 Processor-specific Registers
In addition to the architectural processor registers, the VAX-1l1750 and
VAX-ll1751 processors contain the specific registers defined in this section
and listed in table 10-3. Table 10-3 lists the register acronym, the hexadecimal processor address, and the register type.

Table 10-3· VAX-1l1750 and VAX-ll/751 Processor-specific Registers
Register Name

Acronym

Address

Type*

CMIError
Console Storage Receive/Status
Console Storage Receive Data
Console Storage Transmit/Status
Console Storage Transmit Data
Translation Buffer Disable
Cache Disable
Machine Check Error Summary
Accelerator Control/Status
Initialize UNIBUS
Translation Buffer Data
Accelerator Control/Status

CMIER
CSRS
CSDR
CSTS
CSTD
TBDR
CADR
MCESR
ACCS
IORESET
TBDATA
ACCS

17
lC

IE
IF
24
25
26
40
37
59
28

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

W
R/W
R/W

* R/W is read or write, W is write-only

·TU58CONSOLESTORAGE
The TU58 console tape-cartridge subsystem is accessed through four internal registers that are identical in format and function to the TU58 registers
previously described for the VAX-ll1725 and VAX-ll/730 privileged processor registers .
• BUS REGISTERS
The status of the CMI bus is monitored and the UNIBUS initialization is
controlled by the processor registers described in the following
paragraphs.

eMI Error Register The computer memory interconnect error register
(CMIER) is a read-only register that contains the bus error status information to enable correction of the indicated error. Figure 10-39 shows the
format of the register and describes the function of the bits.

10-31

M~Z

t SA~~~)L>E MBZ- t rBLRPERR MHZ] IIUSEKR

CMIDSBl~

RDlOCKTMO~

TBHIT

Figure 10-39· eMI Error.Register Format
Bit

Function

31:21

MBZ (Must be zero).

CM! DSBL (CM! disable)-Set to disable the CM! references.

19: 16 SAVE MODE REG (Saved mode register) - Indicates the processor
access mode for the last memory reference as follows:
Bit 19-not used
Bit 18-0 is virtual memory, 1 is physical memory
Bits 17: 16-processor access mode 1 through 4
15:13

MBZ (Must be zero).

RD LOCK TMO (Read Lock Timeout) - Set to indicate that a
read-lock timeout has occurred.

11:8

TB GRPERR (Translation buffer group error)-These bits are setto
indicate a data or tag error, as follows:
Bit 8 - TB group 0 data error
Bit 9- TB group 1 data error
Bit 10- TB group 0 tag error
Bit 11-TB group 1 tag error

7:5

MBZ (Must be zero).

TB HIT (Translation buffer hit) - Set to indicate that a translation
buffer hit occurred on the last reference.

3:0

BUS ERR (Bus error)-Set to indicate that the action performed on
the error condition is as follows:
Bit O-corrected data error
Bit I-lost error
Bit 2 - uncorrectable data error
Bit 3 - nonexistent memory

10-32· VAX Privileged Registers

Initialize UNIBUS Register The initialize UNIBUS register (IUR) is a
write-only register used for the software initialization of the UNIBUS. The
format of the IUR information is shown in figure 10-40.

16 15

24 23

1 0

8 7

I I I

MBZ
INITUBJ

Figure 10-40 • Initialize UNIBUS Register Format

Bit

Function

31: 1

MBZ (Must be zero).

INIT UB (Initialize UNIBUS) - Set to initialize the UNIBUS memory

and registers .

• MEMORY REGISTERS
Several memory registers are available to control the memory management
function and the translation of physical addresses to virtual addresses.
Translation Buffer Disable Register

The translation buffer disable register

(TBDR) is a read-write register that controls the enabling and disabling of

the translation buffer and determines which half of the buffer is replaced.
The buffer is cleared during the bootstrap loading sequence. The format
for the TBDR is shown in figure 10-41 and the bit assignments are
described.

2423
I

16 15

43210
II

J IIII

MBZ

RPLCJUUU
GRPRPLC
DISB GRP 1
DISB GRP 2
Figure 10-41 • Translation Buffer Disable Register Format

10-33

Bit

Function

31:4

MBZ(mustbezero).

RPLC (Replace) - When set, the GRP RPLC (bit 2) selects the half of

GRP RPLC (Group replace)- When the RPLC (bit 3) is set and this

the translation buffer that is replaced.
bit is cleared, group zero will be replaced. When bit 3 is set and
this bit is also set, group one will be replaced.
DISB GRP 1 (Disable group 1) - Set to disable group one of the
translation buffer.

DISB GRP 0 (Disable group 0) - Set to disable group zero of the
translation buffer.

Translation Buffer Data Register The translation buffer data (TBDA) is a
read-write register used to read data and write data to locations in the
translation buffer. This capability is important for diagnostic purposes. The
MTPR and MFPR instructions are two-operand instructions. One operand
specifies a longword source or destination and the other operand specifies
the IPR number of the TBDA. A third operand is required for accessing the
translation buffer. It is the virtual address of the translation buffer location
to be referenced. For MTPR instructions, the POBR contains the virtual
address whose PTE (taken from the source operand) is to be written into
the translation buffer. For MFPR instructions, the POBR contains the virtual
address whose PTE is to be read from the translation buffer into the destination. Memory management must be disabled to perform these operations. Figure 10-42 shows the format of the information contained in the
TBDA.

8 7

16 15

2423

TB LOC ADDR

Figure 10-42 • Translation Buffer Data Register Format

10-34' VAX Privileged Registers

Bit

Function

31-0

TB LOC ADDR (Translation buffer location address) -Contains the
address of the data to be read or written into the translation buffer.

Cache Disable Register The cache disable register (CADR) is a read-write
register used to disable the cache memory. The CACH DSABL (bit 1) is
cleared on powerup. Figure 10-43 shows the format of the information in
theCADR.
31

2423

I I

8 7

16 15
I

1 0
I

I I I

MHZ

CACHDSBL:J

Figure 10-43' Cache Disable Register Format

Bit

Function

31:1

MBZ (Must be zero).

CACH DSABL (Cache disable) - A read-write bit that is set to
disable the cache memory.

Cache Error Register The cache error register (CAER) is a read-write register that logs information related to cache parity errors. All bits are cleared
during the bootstrap loading sequence. This register format is shown in
figure 10-44 and the bit assignments are described.
31

2423
I

16 15

~ I
I

MBZ

8 7

4 3 210

Jill I

tuu

DATAERR~

TAGERRJ

LOST ERR
HIT/MIS

Figure 10-44 • Cache Error Register Format

10-35

Bit

Function

31:4

MBZ(Mustbezero).

TAG ERR (Tag error) - Set to indicate that the parity error was in
the tag portion of the cache.

DATA ERR (Data error) - Set to indicate that the parity error was in
the data portion of the cache.

LOST ERR (Lost error)-Set to indicate that there were multiple
cache errors.

HT/MIS (Hit/Miss) -Cleared to indicate that the last microcode
reference resulted in a miss. Set to indicate that the last
microcoded reference resulted in a hit.

"Machine Check Error Summary Register The machine check error summary register (MCESR) is a read-write register that logs information pertaining to the causes of a machine check, such as a bus error. The register is
cleared during the bootstrap loading sequence. The register format is
shown in figure 10-45.

2423

, I,

16 15

~' I
MBZ

8 7

432 1 0

I " , 111/1

tuu

TBERR~

BUSERRJ

MBZ
EXEC BUF ERR

Figure 10-45 • Machine Check Error Summary Register Format

Bit

Function

31:4

MBZ(Mustbezero).

BUS ERR (Bus error) - Set when a machine check occurs as a result
of either a read operation to a nonexistent memory location or
when an error in the data read is uncorrectable.

10-36· VAX Privileged Registers

Bit

Function

TB ERR (Translation buffer error)-Set when a machine check
occurs as a result of a translation buffer error. It is cleared by
writing a one to this bit position.
MBZ (Must be zero).

EXEC BUF ERR (Execution buffer error) - Set when an error is
detected while trying to use data from the execution buffer. It is
cleared by writing a one to this bit position.

FP750 Floating-point Accelerator The FP750 floating-point accelerator
option includes an accelerator controVstatus (ACCS) register used to control and monitor the FPA operations. The functions and register format of
the FP750 are the same as those previously described for the FP730
floating -point accelerator.

VAX-ll/780, VAX -11/782, and VAX -111785 Processor-specific
Registers
In addition to the architectural processor registers, the VAX-1l1780, VAX111782, and VAX-ll/785 processors contain the specific registers defined
in this section and listed in table 10-4. Table 10-4 lists the register acronym,
the hexadecimal processor address, and the register type.

Table 10-4· VAX-111780, VAX-111782,and VAX-111785
Processor-specific Registers
Register Name

Acronym

Address

Type*

Accelerator ControVStatus
Accelerator Maintenance
Writable Control Store Address
Writable Control Store Data
SBI Fault/Status
SBI Silo Data
SBI Silo Comparitor
SBI Maintenance
SBI Error
SBI Timeout Address
SBI Quadword Clear
Microprogram Breakpoint

ACCS
ACCR
WCSA
WCSD
SBIFS
SBIS
SBISC
SBIMT
SBIER
SBITA
SBIQC
MBRK

28
29
2C
2D
30
31
32
33
34
35
36
3C

R/W
R/W
R/W
R/W
R/W

* R/W is read or write, R is read-only, and W is write-only.

R
R/W
R/W
R/W

R
W
R/W

10-37

• MICRO CONTROL STORE
Three registers are provided for control and status of the processor microcode: the writable control store address (WCSA) register, the writable controlstore data (WCSD) register, and the microprogram breakpoint address
(MBRK) register.
Writable Control Store Address Register The writable control store
address (WCSA) is read-write address register that contains the address of
the writable control store (WCS) locations to be read or written, a counter,
and a parity indicator. Figure 10-46 shows the format of the WCSA
information.

24 23

16 15 14 13 12

8 7

J C~TR

WCSADDR

III,JLJI

MHZ

PARINV

I, ,,
y

Figure 10-46 • Writable Control Store Address Register Format

Bit

Function

31:16

MBZ (Must be zero).

PAR INV (Parity inverted) - When set, the data written to the WCS
includes an inverted parity indicator.

14:13

CNTR (counter)-A binary counter that is incremented as each
32-bit word is written and is cleared at the count of three as the
WCS address is incremented.

12:0

WCS ADDR (Writable control store address) - Contains the address
of the WCS location being written into.

Writable Control Store Data Register The WCSD is a read-write register
that contains the data to be written or indicates the control store addresses
that are available for user microcode. Figure 10-47 shows the format of the
information in the WCSD.

10-38· VAX Privileged Registers
31

2423

8 7

1615
I

DATA (write)
31

2423
I

8 7

16 15
I

I)N~

ADDRPRSNT

Figure 10-47 • Writable Control Store Data Register Format

Bit

Function

31:0

DATA-Contains the data to be written into the WCS location
during a write operation.

31:8

RTN 0 (Return as zero) - During a read operation, these bits are all
zeros.

7:0

ADDR PRSNT (Addresses present) - During a read operation, the
address is a binary number that indicates the addresses presently
being used.

The WCSD register is read to indicate which control store addresses are
available for writing. If the addresses present (bits 7:0) of the WCSD contain a number (n), then addresses n to the power of 1024 through zn to the
power of 1024 + 1023 are available for writing microcode. The field
defined by the number 4 is reserved for Digital Equipment Corporation.
The remaining numbers define fields where blocks of microcode can be
written by customers or by Digital. Each word of control store contains 96
bits plus 3 parity bits. An MTPR instruction to the WCSD register will write
32 bits and increment the counter (bits 14:13) of the WCSA. When the
count is three, it is automatically cleared and the writable control store
address is incremented. When a microword with bad parity is executed, a
machine check will result. During bootstrap loading, the contents of the
WCSA register are unpredictable.

10-39

Microprogram Breakpoint Address Register The microprogram breakpoint address (MBRK) is a read-write register that contains a breakpoint
address. Whenever the microprogram PC address is the same as the contents of the MBRK register, a signal is asserted. If the console has enabled a
stop on microbreak, then the processor clock is stopped when this signal is
asserted. This signal is available as a diagnostic test point. During the bootstrap loading, the contents of the MBRK register are unpredictable. Figure
10-48 shows the format of the MBRK register information.

M~Z

1312

16 15

24 23

8 7

I I

MICRO ROG CNT

Figure 10-48 • Microprogram Breakpoint Address Register Format

Bit

Function

31:13

MBZ(Mustbezero).

12:0

MICRO PROG CNT (Microprogram count) - A binary address that
causes a microprogram break when the address is the same as the
address in the microprogram counter.

. SYNCHRONOUS BACKPLANE INTERCONNECT BUS
All communication with I/O devices is through the synchronous backplane
interconnect (SB!) bus and adapter. Several registers are provided to monitor and control the SBI functions during normal operations and during
maintenance. The function of the registers are described in the following
paragraphs.
SBI Fault/StatuI Rep/ltcr The SBI fault/status (SBIFS) is a read-write register that provides fault and status indications of the SBI adapter. Figure 1049 shows the format of the information in the register.

10-40· VAX Privileged Registers

31 30 29 28 27 26 25 24 23

III' [,

, ('

:~dJU~~~~ Mh ~uuc
"

8 7

20 19 18 17 16 15

UNEXPRD
DATAFLT

MLTX~~zFLT

I I

SILO FLT LOCK
SIG FLT
INTFLTENB
LATCHFLT
<

XMTFLTCYC
NEST ERR

Figure 10-49 • SBI FaultlStatus Register Format

Bit

Function

PAR FLT (Parity fault) - A readconly bit set to indicate that a parity
fault has been detected.

MBZ (Must be zero).

UNEXP RD DATA FLT (Unexpected read data fault) - A read-only
bit set to indicate that a read data fault has been detected.

MBZ (Must be zero).

MLT XMIT FLT (Multiple transmitter fault) - A read-only bit ~et to
indicate that a multiple transmitter fault has been detected.

XMIT FLT CYC (Transmitter during fault cycle) - A read-only bit
set to indicate that a transmitter attempted to send data during a
fault condition.

NEST ERR (Nested error).

24:20

MBZ (Must be zero).

LATCH FLT (Fault latch) - A write control bit set to latch a fault
condition.

INT FLT ENB (Fault interrupt enable) - Set to enable a program
interrupt on a fault condition.

SIG FLT (Fault signal) - A read-only bit set to indicate that the fault
signal has occurred.

SILO FLT LOCK (Fault silo lock) - A write control bit set if the silo
register is locked because of a fault condition.

15:0

MBZ (Must be zero).

10-41

SBI Silo Data Register The SBI silo data (SBIS) is a read-only register that
records the state of the indicated SBI signals for the preceding 16 bus
cycles. The silo is updated every cycle until the fault line of the SBI is
asserted or an SBI silo comparator match occurs. Figure 10-50 shows the
format of the silo data register.

SBtID

SBI TAG

SBI B/M

CONF
CODE

5BI XMIT IRCV

SBIINTLK
FIRST AFT FLT CLR

Figure 10-50 • SBI Silo Data Register Format
Bit

Function

FIRST AFT FLT CLR (First entry after fault cleared) - Set to indicate

that the silo has received the first entry after the fault condition has
cleared.
30

SBIINTLK (SBI interlock)-Set to indicate that the silo is

interlocked.
29:25

SBI ID (SBI identifier)-A binary number used to identify the

logical source of data during a write command or the logical
destination of the data during a read command.
24:22

SBI TAG- A binary number that indicates the type of transmitted

data on the information lines as follows:
Bit Bit Bit Function
24 23 22
o 0 0 Read data
o
1
Command address
0
1
Write data
1
1
1
0
Interrupt summary read
21: 18

SBI B/M (SBI M3 :MO or B31 :B28) -Contains information field bits
B31 :B28 or mask field bits M3 :MO when the tag field specifies a

command address tag.

10-42· VAX Privileged Registers

Bit

Function

17 :16

CONF CODE (Confirmation code) - A code that indicates the
status of the confirmation lines in response to information transfers
as follows:

Code Definition
00
01
10

No response to a commander's selection
A positive acknowledgement to a transfer
The response to a command/address transfer indicating
the succesful selection of a nexus that is presently unable to
execute the command
The response to a command / address transfer that
indicates the selection of a nexus that cannot execute the
commamd

15:0

SBI XMITIRCV (SBI transmit/receive) - Contains the information
contained on the address/data lines during receive and transmit
operations.

SBI Silo Comparitor Register The SBI silo comparator (SBISC) is a readwrite register that allows the SBI informationto become locked when specified conditions are detected. Both conditional and unconditional lock
modes are provided. Figure 10-51 shows the format of the information in
the register.

8 7
!

~~~

OCK

CaMP
COND CMD/MSK
CODE

COMP
TAG

CNT FLD

•

MBZ

LOCKUNCND
INTENB
CaMP SILO LOCK

Figure 10-51 • SBI Silo Comparator Register Format

10-43

Bit

Function

COMP SILO LOCK (Compare silo lock) - Set to indicate that a silo
lock has occurred; cleared on a write to the SBISC register.

INT ENB (Interrupt enable) - Set to enable a program interrupt
when the silo is locked.

LOCK UNCND (Lock unconditional) - Set to cause an
unconditional lock of the silo information.

28:27

LOCK COND CODE (Conditional lock codes).

26:23

COMP CMD/MSK (Compare command/mask).

22 :20

COMP TAG (Compare tag).

19: 16

CNT FLD (Count field).

15:0

MBZ (Must be zero).

SBI Maintenance Register The SBI maintenance (SBIMT) is a read-write
register that allows error conditions to be simulated for diagnostic maintenance functions. Figure 10-52 shows the format of the information in the
SBIMT register.

31 30 29 28 27

24 23 22 21 20

17 16 IS 14 \3 12 11 10 9 8 7

I I I I I , , , I I I I , , , I I I I I I I I I I , , ,! ' ,

~~ eMAI~TIDJf~~J~ ~~~~UUt \.

SBI PO
REV
WR SEQ
FLT
UNEXP RD
DATA FLT

PAR FLD

li MLT XMIT

FLT
INVLD SBI
ENB SBIINVLD

CA~~~~S~~~~~p I

L FORCE TMO
MBZ RD

GRP 0 MATCH
GRP I MATCH
SBI PI REV

CA~~~~ti~~~l~ I

Figure 10-52 • SBI Maintenance Register Format

10-44· VAX Privileged Registers

Bit

Function

SBI PO REV (SBI PO reversal)-Set to cause a reversal in the parity of
the SBI PO parity bit.

WR SEQ FLT (Write sequence fault) - Set to cause a write sequence
fault to occur.

UNEXP RD DATA FLT (Unexpected read data fault) - Set to cause
an unexpected read data fault.

MLT XMIT FLT (Multiple transmitter fault).

27:23

MAINTID (Maintenance ID)-Set to a binary number to cause
faults and used as a silo comparator.

INVLD SBI (Invalidate SBI) - Set to cause an SBI write invalidate to
cache.

ENB SBI INVLD (Enable SBI invalidate)-Set to enable an SBI
invalidate.

20: 17

REV CACH PAR FLD (Reverse cache parity field) - Set to reverse
the parity field of the cache memory.

CACH MISS GRP 0 (Cache miss group 0) - Set to cause a cache miss
groupO.

CACH MISS GRP 1 (Cache miss group 1) - Set to cause a cache miss
group 1.

CACH RPLC GRP 0 (Cache replacement group 0) - Set to cause a
cache replacement group o.

CACH RPLC GRP 1 (Cache replacement group 1) - Set to cause a
cache replacement group 1.

DSBL SBI CYC (Disable SBI cycles)-Set to disable the cycles of the
SBI bus.

SBI PI REV (SBI PI reversal) - Set to cause a reversal in the parity of
the SBI PI parity bit.

GRP 1 MATCH (Group 1 match) - Set to cause a group 1 match.

GRP 0 MATCH (Group 0 match) - Set to cause a group 0 match.

FORCE TMO RD (Forced timeout on read) - Set to cause a timeout
on a read operation.

7:0

MBZ (Must be zero).

10-45

SBI Error Register The SBI error (SBIER) is a read-write register used to
monitor and control error conditions. Figure 10-53 shows the register
information format.

24 23

JBZ CRD/RDS

16 IS 14 \3 12 11 10 9 8 7 6 5 4 3 2 I

IN~i~:JJU~ 7£~~~ ~
RDSRTN
CPUTMO

MBZ
CPu/SBI CONF ERR
IB RD DATA SUB
IBTMOIB/SBI CONF ERRMLTCPUERRINTFC NOT BUSYMBZ-

Figure 10-53' SBI Error Register Format

Bit

Function

31:16 MBZ (Must be zero).
15

CRDIRDS INT ENB (CRD/RDS interrupt enable) - Set to enable a
corrected read data or read data substitute command.

CRD RTN (CRD returned)-Awrite control bit set when the
corrected read data is returned to the CPU.

RDS RTN (RDS returned) - A write control bit set when the read
data substitute is returned to the CPU.

CPUTMO (CPU timeout)-Awrite control bit set to indicate that
the CPU has timed out.

11: 10

CPU TMO STAT (CPU timeout status) - Read-only bits.

MBZ (Must be zero).

CPUlSBI CONF ERR (CPUlSBI confirmation error) - A read-only
bit set to indicate that the error between the CPU and SBI has been
confirmed.

IB RD DATA SUB (IB read data substitute) - A write control bit set
to cause a read data substitute.

10-46' VAX Privileged Registers

Bit

Function

IB TMO (Information bus timeout) - A write control bit.

5:4

IB TMO STAT (IB timeout status)-A read-only field.

IB/SBI CONF ERR (IB/SBI confirmation error) - A read -only bit set
to confirm that an error has occurred between the information bus
and the CPU.

MLT CPU ERR (Multiple CPU error)-A read-only bit set to
indicate that several CPU errors have occurred.
INTFC NOT BUSY (Interface not busy) - A read-only bit set to
indicate that the SBI interface is not performing a transaction.

MBZ (Must be Zero).

SBI Timeout Address Register The SBI timeout address (SBITA) is a readonly register that stores the physical address sent on the SBI bus when a
timeout occurs. Figure 10-54 shows the format of the information in the
register.
31 30 29 28 27

24 23

lilli, " I,

~UL~o~~~

16 15

I,~ ,I

8 7

, I,

PHYS ADDR

MODEOREF
MODE 1 REF

Figure 10-54 • SBI Timeout Register Format
Bit

Function

MODE 1 REF (Mode 1 reference).

MODE 0 REF (Mode 0 reference).

NO PROT CHK (Protection not checked).

MBZ (Must be zero).

27:0

PHYS ADDR (Physical address) - A binary number that is the
physical address sent to the SBI when the timeout occurred.

10-47

SBI Quadword Clear Register The SBI quadword clear (SBIQC) is a writeonly register that contains the physical quadword address. Figure 10-55
shows the format of the register information.

31 30 29

2423

MBZ

16 15

I I I

8 7

I I I

3 2

I-LJ

PHYS QlIADWD ilDDR

MIIZ

Figure 10-55· SBI Quadword Clear Register Format

Bit

Function

31:30 MBZ(Mustbezero).
29:3

PHYS QWDWD ADDR (Physical quadword address) - A binary
number that is the physical quadword address.

2:0

MBZ (Must be zero) .

• FP780 FLOATING-POINT ACCELERATOR
The FP780 floating-point accelerator option contains two internal registers
that monitor and control the accelerator operation: the accelerator
control/status (ACCS) register and the accelerator maintenance (ACCR)
register.

Accelerator ControllStatus Register The ACCS is a read-write register that
indicates whether the accelerator option is installed. It controls when it is
enabled, identifies its type, and reports errors and status functions. Figure
10-56 shows the format of the information in the ASSC register.
313029282726

_2423

IIlIlllll

16 15 14
I

I , ,
T
MHL

TYPE

Figure 10-56 • FP780 Accelerator ControllStatus Register Format

10-48· VAX Privileged Registers

Bit

Function

ERR (Error) - A read-only bit set to indicate that one of the error
bits (bits 30:27) is set.

MBZ (Must be zero).

UNDFL (Underflow) - A read-only bit set to indicate that the last
instruction had an underflow caused by an exponent that was too
small.

OVRFL (Overflow) - A read-only bit set to indicate that the last
instruction resulted in an overflow caused by an exponent that was
too large.

RESV (Reserved) - A read-only bit set to indicate that the last
instruction had a reserved operand.

26:16

MBZ(Mustbezero).

ENB (Enabled) - A read-write bit set during the bootstrap loading
sequence to indicate that the accelerator is installed and enabled.

14:8

MBZ (Must be zero).

7:0

TYPE-A read-only field that specifies the FPA type as follows:
O-No accelerator
1-Accelerator installed
2 through 127 - Reserved for Digital Equipment Corporation
125 through 255 - Reserved for Digital's CSS group customers

The ACCR is a read-write register that
controls the accelerator's microprogram counter (PC). The content of the
register during bootstrap loading sequence is unpredictable. Figure 10-57
shows the format of accelerator maintenance register.

Accelerator Maintenance Register

Ie- ' ',' ,,I ' , ,; , , t '"
31 30

24 23

MBZ

ENB TRAP ADDR LOAD

16 15 14 13

IRAP AD))R

9 8 7

MBZ

MICRO

h: ADDR

MICRO PC MATCH
ENB MICRO PC LOAD

Figure 10-57 • FP780 Accelerator Maintenance Register Format

10-49

Bit

Function

ENE TRAP ADDR LOAD (Enable trap address load) - A write-only
bit set to cause bits 23: 16 to be loaded into the FPA trap address

MEZ (Must be zero).

23: 16

TRAP ADDR (Trap address) - A read-write field used by the main

processor to force the accelerator to a specified micro location.
15

ENE MICRO PC LOAD (Enable micro PC load) - A write-only bit
set to cause bits 8:0 to be loaded into the accelerator's micro PC

match register.
14

MICRO PC MATCH (Micro PC match)-A read-only bit that is set
whenever the accelerator's micro PC matches the micro PC match
register.

13:9

MEZ (Must be zero).

8:0

MICRO PC ADDR (Micro PC address) - During a read operation,
this field contains the next micro PC address to be executed.
During a write operation, if EML (bit 15) is set, this value updates
the micro PC match register.

VAX 8600 Processor-specific Registers
In addition to the architectural processor registers, the VAX 8600 processor
contains the specific registers defined in this section and listed in table 105. Table 10-5 lists the register acronym, the hexadecimal processor address,
and the register type.

Table 10-5· VAX 8600 Processor-specific Registers
Register Name

Acronym

Address

Type*

Physical Address Memory Access
Physical Address Memory Location
Cache Sweep
Mbox Data ECC
Mbox Error Enable
Mbox Data Control
Mbox MCC Control

PAMACC
PAMLOC
CSWP
MDECC
MENA
MDCTL
MCCTL

40
41
42
43
44
45
46

R!W
R!W
RlW
RlW
RlW
R!W
R!W

" R!W is read or write, R is read-only, and W is write-only.

10-50· VAX Privileged Registers

Acronym

Address

Type*

Mbox Error Generator
Console Reboot
Diagnostic Fault Insertion
Error Handling Status
Storage Transmit Control/Status
Storage Transmit Data Buffer
Ebox Scratchpad Address
Ebox Scratchpad Data

MERG
CRBT
DFI
EHSR
STXCS
STXDB
ESPA
ESPD

47
48
49
4A
4C
4D
4E
4F

R/W

W
W
R/W
R/W
R/W

W
R

,', R/W is read or write, R is read-only, and W is write-only.

• MEMORY REGISTERS
Several registers are provided to monitor information, to control the access
to information in the cache and main memory, and to report errors when
they occur. These registers are described in the following paragraphs.

Physical Address Memory Map Registers Two physical address memory
map (PAMM) registers are included to allow information to be read from or
written to the physical memory map locations: the physical address memory access (PAMACC) register and the physical address memory location
(PAMLOC) register.
Physical Address Memory Access Register The physical address memory
access (PAMACC) register is used to write to the memory locations and
contains both the address of the location to be loaded and the data to be
stored. Figure 10-58 shows the format of the data in the PAMACC register.

31 30 29

24 23

2019

16 15

II I I I I ! I I I I I I I. I
n

STZ

PAMMADDR

MBZ

5 4

I I I IJ I I.,I I J
CONFCODE

Figure 10-58 • Physical Address Memory Access Register Format

10-51

Bit

Function

31:30

STZ (Set to zero).

29:20

PAMM ADDR (Physical address memory map address) -Contains
the PAMM address, which is the Ebox virtual address (EVA) bus
(bits 29:20).

19:5

MBZ (Must be zero).

4:0

CONF CODE (Configuration code) - A hexadecimal code used to
define the memory array card, adapter code, or nonexistent
memory address as follows:

Code

Configuration

00 through 07 Internal array slot 0-7 respectively
18 through 1B 110 adapter 0 through 3 respectively
1F
Nonexistent address

',Physical Address Memory Map Location Register The physical address
memory map location (PAMLOC) is a read-write register that specifies the
location in the physical memory where the data will be read. When reading
a location, PAMLOC is used to identify the location to be read and PAMACC
is used to access the information. The data is returned in the same format
as specified by the configuration code (bits 4:0) of the PAMMAC register.
Figure 10-59 shows the information contained in the PAMLOC register.

31 30 29

I I

I
I
~'
STZ

24 23
I

I
¥

2019
I

PAMMADDR

f\:,

16 15
I

8 7
I

I
¥

0
I

MBZ

Figure 10-59 • Physical Address Memory Map Location Register Format

10-52 • VAX Privileged Registers

Bit

Function

31:30

STZ (Setto zero).

29:20

PAMM ADDR (Physical address memory map address) -Contains
the PAMM address, which is the Ebox virtual address (EVA) bus
(bits 29:20).

19:0

MBZ (Must be zero).

Cache Sweep Register The cache sweep (CSWP) is a read-write register
used by the macro code to monitor and control the state of the cache memory. During a powerup condition when the system is initialized, a cache
sweep and invalidate operation are performed. During a powerdown condition, a validate operation is performed to write the cache information
into memory. During the initialization procedure, the cache information is
invalidated by clearing the data and valid bits. When half of the cache
memory is disabled because of an error or when the state of the cache is
accessed, the cache information is validated by copying the written cache
locations into memory as specified by the cache-enable bits of the CSWP.
The cache state can be changed by executing a MTPR instruction with the
cache-control field value set to the required function. The current cache
state can be obtained be executing a MFPR instruction and monitoring bits
1 and 0 of the CSWP register. The format of the register information is
shown in figure 10-60.

2423

31
I

8 7

16 15
I

4 3
I

MTB7

Figure 10-60 • Cache Sweep Register Format

0
I

CACH LNTL

10-53

Bit

Function

31:4

MBZ (Must be zero).

3:0

CACH CNTL (Cache control)- The cache control field is defined as
follows:

Bit 3 - When set, the information in both halves of the cache
memory will be cleared, including the written and valid bits,
without updating memory. The cache-access mode is then enabled
to select one or both of the halves of the cache memory as
determined by the C1 ENB and co ENB bits.
Bit 2 - When set, a copy of the information in one or both cache
memory halves, as specified by the C 1 ENB and CO ENB bits, is
written to memory. The cache-access mode is then enabled to
select one or both of the halves of the cache memory, as
determined by the C1 ENB and co ENB bits.
Bit 1-Set to enable the operation the C1 half of the cache memory.
Bit 0 - Set to enable the operation the co half of the cache memory.

Mbox Data ECC Register The Mbox data ECC (MDECC) is a read-write
register that contains the error flags related to the error correction code
(ECC) and syndrome indicators that are used to correct single-bit errors in
the cache or main memory. The register also contains other syndrome indicators and are used by the diagnostic programs and the macrocode to
verify the system error-handling procedures. Figure 10-61 shows the function of the bits in the MDECC register.

I I
ERR lLA(;

RTN]
STZ

DATA
SYNDREG

[CHK

RTN 0
DATA LNGWD PAR INVT

Figure 10-61 • Mbox Data ECC Register Format

~T INV

10-54 • VAX Privileged Registers

Bit

Function

31:23

MBZ (Must be zero).

22: 19

ERRFLG (Error flags)-Set to indicate a single-bit cache or
memory error has occurred. The bits are described as follows:
Bit 22 - A read-only bit set to indicate that incorrect data has been
written into the cache or memory array from an external source.
Bit 21- A read-only bit set to indicate that the data read from the
cache or main memory has a single-bit error. The DATA SYND REG
(bits 14:9) contain the syndrome indication of this error.
Bit 20- A read-only bit set to indicate that the data word read from
cache or main memory has a double-bit error or a detectable
multiple-bit error.
Bit 19-A read-only bit set to indicate that the word fetched from
memory was written to or read from the wrong location.

18: 17

RTN 1 (Returned as one).

STZ (Set to zero).

DATA LNGWD PAR INVT (Data long parity inverted) - A read-only
bit, set to indicate that the longword parity generated by the ECC
logic is inverted.

14:9

DATA SYND REG (Data syndrome register) - Read -only bits; the
syndrome generated by the ECC logic for the word in error.

RTN 0 (Returned as zero).

7: 1

CHK BIT INVT (Check bits inverted) - Read-modify-write bits used
when the ENB INV REG (bit 9) of the MDCTL register is set, to
initiate ECC errors and A bus parity errors. These bits are set by the
diagnostic program to perform the following functions:
Bit 7 - The check parity bit 0 is inverted.
Bits 6: I-Check bits 6 through 1 respectively are inverted.
Bit O-A write-only bit that is set to invert the longword parity,
generated on the memory array bus, when the ECC logic is in the
check mode.

10-55

Mbox Error Enable Register The Mbox error enable (MENA) is a readwrite register used to enable the reporting of the Mbox error status bits.
The associated traps and errors that are reported will still occur. This register is normally initialized by the console subsystem during the bootstrap
sequence and is used for diagnostic and error-handling verification. Figure
JO-62 shows the format of the information in the MENA register.

2423

,! ' , I
H

MilL

8 7

16 15
!

! ' , I , ,!

Mel' STAT RF<; A
REPTENB

I I

AOOR STAT RF.c;
REPT ENB

Figure 10-62 • Mbox E"or Enable Register Format

Bit

Function

31:24

MBZ (Must be zero).

23: 16 MCC STAT REG AREPT ENB (MCC status register A reporting
enable) - A hexadecimal value (F8) used to enable the reporting of
an error in the Mbox cache control status register, as follows:
Bit 23 - Set to indicate that a CPR parity error B has occurred.
Bit 22 - Set to indicate that a CPR parity error A has occurred.
Bit 21- Set to enable the reporting of an A bus data parity error.
Bit 20 - Set to indicate that an A bus control parity error has
occurred.
Bit 19-5et to indicate that an A bus address parity error has
occurred.
Bits 18:16-Not used.
15:8

ADDR STAT REG REPT ENB (Address Status Register Reporting
Enable) - A hexadecimal number (OF) used to enable the reporting
of errors in the address status register in the Mbox, as follows:
Bits 15: 12 - Not used.
Bit 11- Set to indicate that a TB valid error has occurred.
Bit 10- Set to indicate that a PTE B parity error has occurred.
Bit 9 - Set to indicate that a PTE A parity error has occurred.
Bit 8 - Set to indicate that a TB tag parity error has occurred.

10-56' VAX Privileged Registers

Bit

Function

7:0

MB DATA ERR (Mbox data error) - A hexadecimal value (F9) used
to enable the reporting of Mbox data errors, as follows:
Bit 7 - Set to indicate that a write-byte-3 parity error has occurred.
Bit 6-Set to indicate that a write-byte-2 parity error has occurred.
Bit 5 - Set to indicate that a write-byte-1 parity error has occurred.
Bit 4-Set to indicate that a write-byte-O parity error has occurred.
Bit 3 - Set to indicate that a cache data parity error has occurred.
Bits2:1-Not used.
Bit 0- Set to indicate that cache-to-processor byte-write-data
parity error has occurred.

MBox Data Control Register The Mbox data control (MDCTL) is a readwrite register that is used by the diagnostic program to verify system errorhandlli).g procedures. Figure 10-63 shows the format of the information in
the MDCTL register.

I, , .,

MUMUUUW987

,1", 'jJJJlllL~
I"

Figure 10-63 • Mbox Data Control Register Format
Bit

Function

31:16 MBZ (Must be zero).
15

STZ (Set to zero).

INH DATA PAR ERR CHK (Inhibit data parity error check) - When
set, the MD bus write parity errors and the cache data parity errors
will not be detected or reported by the Mbox.

DIAG CHK RAM RD (Diagnostic check RAM read) - When set, the
bits from the selected cache RAMs will be read.

10-57

Bit

Function

Not used.

INH BAD DATA FLG (Inhibit bad data flag) - When set the the bad
data code check bits will not be generated as described in the
MDECC register.

DSBL ECC ON DATA (Disable ECC on data) - When set, no error
correction on the data will occur. Error information will be logged
and reported, unless inhibited by the MERG register.

ENB INVT REG (Enable invert register) - When set, the data stored
in the data-cheek-bit invert register complements the check bits
generated on the write.

ENB CACH BTYE PAR ERR (Enable cache byte parity
error) - When set, the bad-byte parity will be written into cache
from a CPU request as determined by the ENB CACH PAR ERR (bits
3:0).

7:4

STZ (Setto zero).

3:0

ENB CACH PAR ERR (Enable cache parity error)- When set in
conjunction with the EN CACH BYTE PAR ERR (bit 8) even parity
will be generated on bytes 3:0 and written into the cache during
CPU write operations. These bits are also used to generate single
longword failures during A bus write operations.

Mbox Memory Cache Control Register The Mbox memory cache control
(MCCTL) is a read-write register used by the diagnostic programs and the
macro code for error-handling verification. Figure 10-64 shows the format
of the information in the register.

24 23
I

16 15 14 13
I

t D1AAGB~TL

NOTUSED~
STZ]

8 7

2 1 0

STZ.J

REPT ARRY ACSS MODEJ
INH MEM OVRLP

Figure lO-64 • Mbox Memory Cache Control Register Format

10-58· VAX Privileged Registers

Bit

Function

31:16 MBZ (Must be zero).
15

STZ (Set to zero).

Not used.

13:8

DIAG CNTI. ABUS (Diagnostic control A bus) - Used for
maintenance when the Mbox is using the A bus in diagnostic mode.
The bits stored in these locations are substituted for the normal
data length/status bits and command/mask bits when writing to
the I/O adapter register fIle. The bit assignments are as follows:
Bits 13: 12 - Data length!status bits 1 and 0 are set.
Bits 11:8-Command/mask bit 3 through 0 are set.

7:2

STZ (Setto zero).

REPT ARRY ACSS MODE (Repeatable array access mode- When
set, the memory access time from the array is repeatable and slower
than the normal access time plus the refresh time.

INH MEM OVRLP (Inhibit memory overlap) - When set, the data
from a memory array cannot be read before the previous data read
from memory has been extracted from the array register fIle.

Mbox Error Generator Register The Mbox error generator (MERG) is a
read-write register used by the diagnostic programs and the verification
macrocode to cause errors and verify the correction process. The VMS
software can affect the error reporting process by setting appropriate bits
in this register when error rates are exceeded. Figure 10-65 shows the bit
assignments in this register.
31

24 23

16 15

13 12 11 10 9 8 7 6 5 4 3 2 1 0

,1"",,,I,,IIIIIIJIIIIII
Miz

f'7z""'JUU~~ STJ~

INHDMAREQ
GEN ABUS CMD/MSK EVEN PAR
INH ARRY CORR ERR REPT
DlAG CNTL ABUS ENB
MEMMNGTENB
ADDR RAM DlAG
GEN TB TAG EVEN PAR
GEN TB VALID ERR
GEN WR PAR ERR
GEN DATA TAG EVEN PAR
GEN PHYS AODR EVEN PAR

Figure 10-65 • Mbox Error Generator Register Format

10-59

Bit

Function

31:16

MBZ (Must be zero).

15: 13

STZ (Set to zero).

INH DMA REQ (Inhibit DMA request) - When set, the DMA
requests from the SBI adapter will not be serviced.

GEN ABUS CMD/MSK EVEN PAR (Generate A bus command/mask
even parity)-Set to cause the A bus command and mask to be sent
with even parity.

INH ARRY CORR ERR REPT (Inhibit array correctable error
reporting) - Set to prevent the reporting of correctable errors when
reading the main memory. The errors are corrected by the logic.

DIAG CNTL ABUS ENB (Diagnostic control enable) - When set, the
diagnostic-control A bus information (bits 13:8 of the MCCTL
register) is used on the A bus.

MEM MNGT ENB (Memory management enable) -Set to enable
the memory management function that allows the virtual addresses
to be translated by the translation buffer. When cleared, all
memory references will be recognized as physical and the parity
error checking of the translation buffer will be disabled.

7:6

STZ (Set to zero).

ADDR RAM DIAG (Address RAM diagnostics) - Set to cause special
events to occur in the Mbox depending on the type of cycle, as
follows:
Write TB- The translation buffer RAMs that contain the physical
address (bits 12: 9) are selected by the IVA bus to be written instead
of by the EVA bus.
Read TB - The contents of the translation buffer RAMs containing
physical address bits (12:9) are selected by the IVA bus to be read
instead of the EVA bus.
Diagnostic read cache tag address- The written bit, written parity
valid bit, and cache tag parity will be read instead of the cache tag
address bits.

GEN TB TAG EVEN PAR (Generate TB tag even parity) -When set,
data written to the TB will include a TB tag with even parity. A
parity error will be indicated when a read data command specifies
this location.

10-60' VAX Privileged Registers

Bit

Function

GEN TB VALID ERR (Generate TB valid error) - When set, both

stored valid bits will be written to the same value.
2

GEN WR PAR ERR (Generate written parity error)- When set, the
written parity bit in the cache tag is complemented before being
written into cache.

GEN DATA TAG EVEN PAR (Generate data tag even parity) - When
set, the cache data address tag is stored with even parity. The
normal parity is the odd parity generated on the stored tag address
and the four valid bits.

GEN PHYS ADDR EVEN PAR (Generate physical address even
parity) - When set, the cache data address tag included in the
data-path-check bit generation is complemented and written either
into cache or into the storage array.
.

• DIAGNOSTIC REGISTERS
Two registers are provided for use by the diagnostic programs and error
handling macrocode to verify processor errors. These registers are
described in the following paragraphs.

Diagnostic Fault Insertion Register The diagnostic fault insertion (DFI) is
a write-only register used by the diagnostic program and the macrocode to
verify the handling of errors. Figure 10-66 shows the format of the DFI
register.

(, , ,

2726

CNTRCNTL

, I,

16 IS 14

11 10

1 :"'-

8 7

I, , , I

Mill:

LOAD PTE-.J

Figure 10-66 • Diagnostic Fault Insertion Register Format

10-61

Bit

Function

31:27

CNTR CNTL (Counter control) - Used to select the operating
conditions of the DFI register as follows:
Bit 31- Set to specify that the fault insertion is enabled and
controlled by the hardware associated with this register.
Bit 30:28 - These bits form the count mode 0-2 for the event
counter increment enable as described:
Bit Bit Bit Event
30

0
0
0
0

0
0

0
1
0
1
0
1
0

1
1

1
0
0

No count
Count
-Estall
-Istall
Ebox Umark + Ibox Umark
Ebox Umark * -Estall + Ibox Umark" -Istall
IRD * - stall

Bit 27 - When set, the microcode mark is overridden as one of the
conditions included to insert the fault.
26:16

MBZ (Must be zero).

LOAD PTE (Load page-table entry) - When set, the page-table
entry in general purpose register R1 is loaded into the TB location
corresponding to the virtual address in register RO and all other
bits in this register are ignored.

------------------------------------

~----

14:11

MBZ (Must be zero).

10:0

EVENT CNTR (Event counter) - A binary counter that specifies the
count value of from one to 1,047 cycles. The count value~ are
selected by bits 30:28 and generated by Ebox and Ibox microcode
mark bits with and without stalls, IRD cycles not stalled, or an
external event until the event counter overflows.

Error Handling Status Register The error handling status register (EHSR)
is a read-write register used by the error-handling microcode (EHM) and
macrocode for the synchronization and control of the machine-check
exception processing. This register i:; part of the reason code field of the
machine-check exception stack frame. Figure 10-67 shows the format of
the information in the register.

10-62· VAX Privileged Registers
16 15

31
I

•

I ,

CNTRSTORE
CORRREQ

•

MIIZ

,y
\

~ I

ERR HNDL STA:l

Figure 10-67 • Error Handling Status Register Format

Bit

Function

31 :25

CNTL STORE CORR REQ (Control store correction.
required) - Read-only bits set to indicate the request that was
generated by the EHM to the console as follows:
Bit 31- Set to indicate that a correction is required to the Fbox
multiplier control store microcode.
Bit 30- Set to indicate that a correction is required to the Fbox
adder control store microcode.
Bit 29 - Set to indicate that a correction is required to the Fbox
DRAM microcode.
Bit 28 - Set to indicate that a correction is required to the Ibox
DRAM microcode.
Bit 27 - Set to indicate that a correction is required to the the Ibox
control store microcode.
Bit 26-Set to indicate that the correct copy of the Mbox error
address is contained in the Mbox scratchpad memory;
Bit 25 - Set to indicate that the error-handling microcode has
determined that an unrecoverable error has occurred and the
operating system will be automatically reloaded.

24:8

MBZ (Must be zero).

7:0

ERRHNDL STAT (Error handling status)-Indicatesthe status of
the error-handling routine as follows:
Bit 7 - Set to indicate that the EHM has been notified by the
interrupt and exception microcode to service an Mbox error.
Bit 6-Set to indicate that the EHM has been entered.
Bit 5 - Set to indicate that the program count of the machine check
exception handler has been transferred to the VMS operating
system.
Bit 4 - Set to indicate that EHM has been informed of an Fbox
hardware error. The EHM will perform a control store or GPR
correction if required.

10-63

Bit

Function
Bit 3 - Set to indicate that the EHM routine attempted to correct
the error with the Fbox GPR RAMs.
Bit 2 - Set to indicate that the EHM attempted to correct the error
with the A side of the Ebox scratchpad RAMs.
Bit 1-Set to indicate that the EHM attempted to correct the error
with the B side of the Ebox scratch pad RAMs.
Bit O-Set to indicate that the EHM attempted to correct the error
with the Ibox GPR RAMs .

• CONSOLE SUBSYSTEM INTERFACE
The console subsystem interface contains registers used to transfer information between the VAX 8600 CPU and the external devices that connect
to the console subsystem. Two console transmit registers transfer information from the CPU to the devices and two console receive registers transfer
information from the devices to the CPU. The console reboot register
enables the VMS operating system to reboot the console program after a
console failure. The external devices that communicate with the CPU are
the console terminal, remote diagnostic port, environmental monitoring
module (EMM), and RL02 console load disk drive.

Console Reboot Register The console reboot (CRBT) is a write-only register controlled by software to reboot the console processor only. The register contains the reboot code and address supplied by the microcode.
Figure 10-68 shows the format of the information in the register.

{

2423

16 15

NOT USED

8 7

JI I

RBTLOUE

RBT ADUR

Figure 10-68 • Console Reboot Register Format

10-64· VAX Privileged Registers

Bit

Function

31:16

Not used.

15:8

RBT CODE (Reboot code)- The reboot code is 80 (hexadecimal).

7:0

RBT ADDR (Reboot address)- The reboot address is 33
(hexadecimal) and causes a bootstrap loading of the console
processor~

Console Receive ControllStatus Register The console receive control!
status (RXCS) is a read-write register used with the console receive data
buffer register (RXDB) to transfer information from the console subsystem
iriput to the cpu. Figure 10-69 shows the format of the information in the
RXCS register.

2423

16 15

8 765

,I, , , ,I,
~

MBZ

DTR

MBZ

-tt-

,I
?

MBZ

DONE~ LINT ENB

Figure 10-69 • Console Receive ControllStatus Register Format

Bit

Function

31:24

MBZ (Must be zero).

23:16

DTR (Data terminal ready)-Read-write bits set by cpu to indicate
that the cpu is ready to accept characters from the modem.
Cleared to indicate that the cpu is ready to disconnect from the
modem. The DTR assignments are as follows:
Bits 23 :20 - Reserved
Bit 19 - Logical console subsystem data
Bit 18-EMM data line
Bit 17 - Remote services port
Bit 16-Console terminal

15:8

MBZ (Must be zero).

10-65

Bit

Function

DONE - A read-only by CPU bit set to indicate that data is available
from the console subsystem and that the data and the source
identification (ID) is available in the RXDB register.

INT ENB (Interrupt enable) -A read-write bit set by the CPU to
allow an interrupt request to be generated if the DONE (bit 7) is
also set.

5:0

MBZ (Must be zero).

Console Receive Data Buffer Register The console receive data buffer
(RXDB) is a read-only register that receives data from the console subsystem for transfer to the cpu. It is initialized by the console subsystem
according to the CPU control panel switch settings and the devices connected to the console subsystem. Figure 10-70 shows the format of the
information in the register.

16~f
MBZ

CARR

MBZ

ID FLD

IDFLD-2
EMM EXCEPTION REPORT

7
IDFLD-2
EMM REQUEST RESPONSE

6 5

1aI1xI11III
.
,
ASD

OPC6DElD

Figure 10-70 • Console Receive Data Buffer Register Format

10-66· VAX Privileged Registers

Bit

Function

31:24

MBZ (Must Be zero).

23: 16

CARR (Carrier)-A CPU read-only field that is initialized by the
console subsystem to a value based on the state of the
corresponding DTR bit in the RXCS register.

15:12

MBZ(Mustbezero).

11:8

ID FLD (Identification field) - A CPU read-only field that contains
a hexadecimal value to identify the source of data in this register, as
follows:
Value 0- The data in bits 7:0 of this register is from the console
terminal.
Value 1-The data mbits 7:0 of this register is from the remote
diagnostic line.
.
Value 2- The data in bits 7:0 of this register is an opcode from the
EMM.
Value 3 - The data in bits 7:0 of this register is related to the logical
console line.
Value 4 through OE- Reserved for Digital Equipment
Corporation.
Value OF-CARR (bit23:16) has changed.

7:0

DATA- The data/status information as specified by the ID
(bits 11 :8).

Console terminal (ID FLD = OJ-Console terminal data is specified by an
identification field value of O. The data received on the console terminal is
contained in the data byte (bits 7 :0) of the RXDB.
Remote services port (ID FLD = 1) - Remote service port data is specified
by an identification field value of 1. The data received on the remote services port is contained in the data byte (bits 7:0) of the RXDB.
Environmental Monitoring Module (ID FLD = 2) - The environmental
monitoring module data is specified by an identification field value of 2.
The RXDB data byte (bits 7:0) contains an opcode from the environmental
monitoring module (EMM) that defines the information in the data byte
that follows the opcode. The two types of information that can be transferred are unsolicited exception reports from the EMM and responses from

10-67

·the EMM as a result of requests. The opcode formats for the EMM data,
shown in figure 10-70, are defined as follows:

• EMM exception reports- These reports are contained in a single opcode
byte followed by a single data byte. The format of information in the
opcode byte is described as follows:
Bit 7 - Set to specify an EMM exception report.
Bit 6-Set to indicate that total system power shutdown is pending.
Bit 5 - Not used.
Bits 4:0 (Opcode ID)-A hexadecimal number that identifies the type of
information in the data byte.
-Power supply status- The power supply voltage regulators in the CPU
are monitored by the EMM. The status of the regulators' output voltage
is indicated by the opcode ID (bits 4:0) values that follow. The data byte
(bits 7 :0) following the opcode byte indicates the present condition of
the regulator voltage.

Data byte
value

Status

Voltage is normal
Voltage is not within specifications

OpcodeID

Regulator

Voltage

1
2
3
4
5
6
7
8
9
A

B
C
D

+5V
+5V
+5V
-2V
-2V
-5.2V
-5.2V
+12V
-12V
+15V
-15V

E
F
H
L
L

K
K

- Temperature status-The temperatures in the CPU cabinet are monitores by sensors. The status of the temperature is indicated by the
opcode ID (bits 4:0) values that follow. The data byte (bits 7:0) following the opcode byte indicates the present condition of the
temperature.

10-68· VAX Privileged Registers

Data byte
value

Status

Temperature is within normal range
Temperature is in yellow zone
Temperature is in red zone and power will be removed from
the system if condition is not corrected.
Temperature is below normal range

1
2
3

Opc:ode ID Temperature
B

Tl
T2
T3
T4
T2-Tl delta change
T3 -Tl delta change
T4-Tl delta change

D
E
F

10
11

- Air flow status - Sensors in the CPU cabinet monitor the flow of cooling
air. The status of the air flow is indicated by the opcode ID (bits 4:0)
values that follow. The data byte (bits 7:0) following the opcode byte
indicates the present condition of the air flow.

Data byte
value

Status

o
1

Air flow is normal
Air flow is not within specifications and power will be
removed from the system if condition is not corrected.

Opcode ID

Sensor

12
13

1
2

- Battery backup status- The battery backup unit (BBU) provides power
to the memory and other critical functions in the event of a power
interrup~ion:. The status of the battery backup indicated by the opcode
II) (bits 4:0) value that follows. The data byte (bits 7:0) following the
opcode byte indicates the present condition of the BBU.

10-69

Data byte
value

Status

o
1

BBU is available
BBU is not available

Opcode ID

Status

BBU available status

- EMM status- The status of the EMM is monitored and failures in the
module operation are reported. An EMM failure is indicated by the
opcode ID (bits 4:0) value that follows. The data byte (bits 7:0) following the opcode byte indicates the type of EMM failure.

Data byte
value

Status

A
B

Failed to restart
Detected an EMM RAM parity error
Detected an illegal instruction
Detected an unknown trap to zero
Detected an unexpected trap interrupt
Detected an unexpected 6.5 interrupt
Excessive collision on the EMM bus
No transport acknowledge from the EMM
No response from EMM
Negative response from the EMM
No EMM buffers available
Console to EMM message transmit timeout

Opcode ID

Status

EMM failure

1
2
3
4
5
6
7
8
9

- Transmit read time-out- The ready (bit 7) in the TXCS register is monitored for a timeout condition. If the bit is not set by the console within
two seconds, the transmit operation that was in process is terminated.
The timeout condition is indicated by the opcode byte (bits 4:0) value
that follows. The data byte (bits 4:0) following the opcode byte indicates the timeout condition.

10-70- VAX Privileged Registers

Data byte
value

Status

o
1
2
3

Local terminal operation is aborted
Remote services port operation is aborted
EMM operation is aborted
Logical console operation is aborted

Opcode ID

Status

Transmit ready timeout

• EMM Request Response- EMM responses that are solicited can vary in
length. The first data byte contains the opcode that defines the information. The second data byte defines the number of data bytes that will
follow. The two types of responses that are available are the EMM status
response and the EMM environmental response. The format of the EMM
request opcode byte follows:
Bit 7 -Cleared to specify an EMM request response.
Bit 6-Set to indicate total system power shutdown is pending.
Bit 5 - Not used.
Bits 4:0 (Opcode ID)-A hexadecimal number that indicates the type of
information contained in the EMM status response or an EMM evironmental response.

-EMM status response-An EMM status response returns the status of
the EMM unit and is specified by an opcode ID (bits 4:0) value of O. The
first data byte following the opcode byte has a value 8 indicating the
number of data bytes that will follow. The status information contained
in the individual bits of the data bytt:s (bits 7 :0) are:

Byte 1- Power control register
Bit

Regulator

Status

1
2
3
4
5
6
7

C
D
E
F
H

0 = off ( + 5 V BBU)
0 = off ( + 5 V SBIA)
0 = off ( -'-2 V ECL)
(follows state of bit 2)
0=off(+5.2VECL)
(follows state of bit 4)
Not used
Disable status (0 = enabled)

J
BBU

10-71
Byte 2 - Margin Enable register
Bit

Regulator

Status

0
1
2
3

0= nominal
0= nominal
0= nominal
0= nominal
(follows bit 3)
0= nominal
(follows bit 5)
0= nominal

4
5
6
7

B
C
D
E
F
H

Byte 3 - Margin select register
Bit

R~gulator

Status

0
1
2
3

o = low, 1 = high
o = low, 1 = high
o = low, 1 = high
o = low, 1 = high

4
5
6
7

c
D
E
F
H

(follows bit 3)

o = low, 1 = high
(follows bit 5)

o = low, 1 = high

Byte 4-Least significant byte of the MODOK register
Bit

Regulator

Status

0
1
2
3

(OK) 1 = OK
(OK) 1 = OK
(OK) 1 = OK
(OK) 1 = OK
(OK) 1 = OK
.(OK) 1 = OK
(OK) 1 = OK
(OK) 1 = OK

4
5
6
7

B
C
D
E
F
H

Byte 5 - Most significant byte of the MOOOK register
Bit

Regulator

Status

0
1
2
3

K
L
K
L

1 = OK
1 = OK
(ac low) 1 = OK
(ac low) 1 = OK

4
5
6
7

} EMM unit n=btt

Key override circuit

10-72· VAX Privileged Registers

Byte 6-Miscellaneous hardware status register
Bit

Function

Status

Air flow 1 sensor

1
2
3
4
5
6
7

BBU

1 = fault
1 = failure
1 = crobar
1 = fault
1 = ac low
1 = dc low
1 = OK
0 = OK

- 2 V crobar signal
Air flow 2 sensor
Latched ac low signal
Latched dc low signal
Parity checker
Parity error

Byte 7 - Miscellaneous software status register
Bit

Function

Extended output signal 1 = asserted
Default mode enable 1 = asserted
Auto shutdown
1 = active
5.5 interrupt disable
1 = disabled
Unused

1
2
3
4:7

Status

Byte 8 - Integer value of the EMM PROM version

-EMM environment response-An EMM environment response returns
all measured environmental information and is specified by an opcode
ID (bits 4:0) value of 1. The first data byte following the opcode byte
has a value of 32 indicating the number of data bytes that will follow.
The voltage values are digitized and must be converted to the actual
value before being displayed or interpreted. The conversions apply to
the regulator and thermistor voltages bytes that follow:
(1) Volts = 0.0276 f1 magnitude
(2) Milliamperes = 70 + (2.8 f1 magnitude)
(3) Volts = 0.0762 f1 magnitude
(4) Volts = 0.0691 f1 magnitude
(5) Degrees Celsius = 16 + (0.3333 f1 magnitude)

}{egulator voltage-Data byte 1 through 24 are regulator voltage bytepairs. The first data byte of a pair indicates the voltage magnitude. In
the second data byte, bits 0:6 are reserved and bit 7 indicates the voltage polarity; 1 = positive, 0 = negative. The regulators assignments
are:

10-73

Byte

Regulator

Conversion

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A(+5VTTL)
A (polarity)
B (+5 VBBU)
B (polarity)
C (+5VSBIA)
C (polarity)
D(-2VECL)
D (polarity)
E (-2 V ECL)
E (polarity)
F (-5.2 V ECL)
F (polarity)
H (-5.2 V ECL)
H (polarity)
Ground current voltage
Ground current polarity
L (+ 12 V TTL)
L (polarity)
L (-12 V TTL)
L (polarity)
K (+ 15 V TTL)
K (polarity)
K (+ 15 V TTL)
K (polarity)

(1)
(1)

(1)
(1)
(1)
(2)
(3)
(4)
(4)
(4)

Thermistor voltage-Data byte 25 through 32 are thermistor voltage
byte-pairs. The first data byte of a pair indicates the voltage magnitude.
In the second data byte, bits 0:6 are reserved and bit 7 is 0 indicating a
positive voltage polarity. The thermistor assignments are:
Byte

Thermistor

Conversion

25
26
27
28
29
30
31
32

'II (input)
T1 (polarity)
T2 (input)
T2 (polarity)
T3 (output)
T3 (polarity)
T4 (output)
T4 (polarity)

(5)
(5)
(5)
(5)

10-74' VAX Privileged Registers

Logical Console Data (ID FLD = 2) -:- Logical console data is specified by an
identification fidd value of 3. The data byte (bits 7:0) of the RXDB can
indi.cate any of the following:
• Data byte = 1O-0ne byte of data will follow, indicating the status of the
warm-start flag: 0 = warm flag cleared, 1 = warm flag set.
• Data byte = 11-One byte of data will follow, indicating the status of the
cold-start flag: 0 = cold flag cleared, 1 = cold flag set.
• Data byte = 12 - Two bytes of data will follow, indicating the microcode
version number: byte 1 is the least significant 8-bits and byte 2 is the most
significant 8-bits.
• Data byte = 20 - Indicates that the console has successfully completed
the the execution of the console command string.
• Data byte = (30)-One byte of data will follow indicating the condition
of the snapshot files as follows:
Bit 0 (0) - SNAPl.DAT file invalid
Bit 0 (l)-SNAPl.DAT HIe valid
Bit 1 (0)-SNAP2.DAT HIe invalid
Bit 1 (l)-SNAP2.DAT HIe 2 valid
Bits 7:2-Not used
• Data byte = 40 - Indicates that the console has been sucessfully
rebooted by VMS.
• Data byte = 82 - Indicates that the console detected an error while
executing th~ console command string, that the console command string
exceeded the byte buffer space, or that console is disabled because of the
.
control pand switch positions.

Console Transmit ControllStatus Register The transmit control/status
(TXCS) is a read-write register that operates with the transmit data buffer
(TXDB) register to transfer information from the CPU to the console interface devices. The register is cleared by the processor during initialization ..
Figure 10-71 shows the format of the TXCS register information.

, ~ , .'
MBZ

XMIT ENB MASK
WT MASK NOW

MBZ

ID Fill

MBZ

ROY

INT ENB

Figure 10-71 • Console Transmit ControllStatus Register Format

10-75

Bit

Function

31:24

MBZ (Must be zero).

23: 16

XMIT ENB MASK (Transmit enable mask) - A read-write field
where each bit is set to enable the transfer of information between
the processor and a device, as follows:

Bit 23 :20 - Reserved for additional console-resident interfaces
Bit 19 - Logical console subsystem data
Bit 18- EMM module data
Bit 17 - Remote services port
bit 16-Console terminal
15

WT MASK NOW (Write mask now) - A CPU and console read-write

bit, set by the CPU to allow the microcode to write to the transmit
enable mask field (bit 23: 16). The console reads this bit to
determine the operation that caused the console interrupt.
14: 12

MBZ (Must be zero).

11:8

ID FLD (Identification field) -A hexadecimal value that is read by
the CPU to identify the line responsible for the interrupt and is
ready to transmit data, as follows:
Value O-Console terminal
Value 1-Remote services port
Value 2 - EMM data
Value 3 - Logical console data
Value F-No lines currently enabled

RDY (Ready}-A CPU read-only bit set to indicate that the line
identified in the identification field (bits 11:8) is ready to transmit
data when the transmit enable mask field (bits 23: 16) is not zero.

INT ENB (Interrupt enabled) - A CPU read-write bit set to enable

an interrupt request from the device selected when the ready (bit
7) is also set.
5:0

MBZ (Must be zero).

10-76· VAX Privileged Registers

The console transmit data buffer

Console Transmit Data Buffer Register

(T~mB) is a write-only register that receives the data to be transferred from

the CPU to the selected device. Figure 10-72 shows the format of the register information.

2423
!

16 15
!

!
!

~
MZ

!
!

8 7
!

1 !
!

!
I

DATA

Figure 10-72 • Console Transmit Data Buffer Register Format

Bit

Function

31:8

MBZ(Mustbezero).

7:0

DATA - A CPU write-only byte of data for transmission to the
sele~ted console line as specified by the ID FLD (bits 11:8) of the
TXCS register. The data and ID field values are as follows:
ID value 0- Data bytes for the console terminal line
ID value 1-Data byte for remote services port
ID value 2 - Data byte for the EMM line to anyone of the following
hexadecimal values:
Byte 1 value Function
o
Request for EMM status information
1
Request system environment information
3
Set regulator margins normal
4
Set regulator margins low
5
Set regulator margins high
11
Cancel current and queued EMM requests
ID value 3 - Data bytes for the logical console line; may contain any
one of the following hexadecimal values:
Byte 1 value Function
2
Initiate system reboot sequence
3
Clear the console copy of the warm-start flag.
4
Clear the console copy of the cold-start flag.
10
Request the value of the console's copy of the
warm-start flag.
11
Request the value of the console's copy of the
cold-start flag.
12'
Request the 16-bit value of the system microcode
version being executed.

10-77

Bit

Function
Byte 1 value

Function

Begin accepting a console commmand string. Used
for error-handling verification.
Request the console return the status of two
snapshot files.
Request the console to invalidate SNAPl.DAT file
after processing SNAP2.DAT file.
Request the console to invalidate SNAP2.DAT file
after processing.
Cancel all current and queued logical console
requests .

31
32

. CONSOLE BLOCK STORAGE
The console subsystem contains two registers used to implement the data
transfers between the CPU and the RL02 console disk drive. The CPU initiates the read and write operation and monitors the console status during
the console block storage data transfers.
Storage Transmit ControllStatus Register The storage transmit control!
status (STXCS) is a read-write register used to monitor and control the
transfer of information between the CPU and RL02 disk drive. It contains
the logical block address of the disk where the data will be read or written.
It also defines the read or write function and returns status to the processor
during the transaction. Figure 10-73 shows the format of the information in
the STXCS register.

24 23
I

;

STAT

16 15

DISK ADDR

876543

. tu

MU DiSK FUNe

RDy.J
INT ENB

Figure 10-73 • Storage Transmit ControllStatus Register Format

10-78· VAX Privileged Registers

Bit

Function

31 :24

STAT (Status) - A CPU read-only field containing a hexadecimal
value that specifies the status of the current transfer as defined:
Value 1- Indicates that the console or the CPU has completed the
data transfer operation.
Value 2 - Set by the console or CPU to indicate that the entire block
of data has not been transferred.
Value 3 - Set by the console to indicate that the requested transfer
has been aborted.
Value 4-Set by the CPU during a transfer operation to request
status information from the console through the STXDB register.
Value 80 - Set by the CPU during a transaction to indicate that a
protocol error has occurred.
Value 81-Set by the CPU to indicate that a hardware error has
been detected during the transaction.

23:8

DISK ADDR (Disk address) - A CPU write-only field that contains
the hexadecimal address of the block number of the RL02 disk for
the current transfer.

RDY (Ready) - A CPU read-only bit set to indicate that the register
is ready for a transaction.

INT ENB (Interrupt enable) - A CPU write-only bit set to enable a
data transfer to occur when the RDY (bit 7) is set.

5:4

MBZ (Must be zero).

3:0

DISK FUNC (Disk function) - A CPU write-only field that specifies
the disk function to be performed, as follows:
o = No operation
1 = Not assigned
2 = Reset and return device status
3 = Abort current transaction
4 = Read device status
5 = Write block data
6 = Read block data

10-79

Storage Transmit Data Buffer Register The storage transmit data buffer
(STXDB) is a read-write register that contains the data to be read from or
written to the console storage disk drive. The format of the information in .
the register is shown in Figure 10-74.

24 23

16 15

JZI

: 1

; ...

8 7
I

DATA
'"

Figure 10-74 • Storage Transmit Data Buffer Register Format

Bit

Function

31:16

MBZ(Mustbezero).

15:0

DATA - Contains the data to be transferred.

Ebox Scratchpad Registers The Ebox contains two dual-ported scratchpad memories that are accessed by the Ebox scratchpad registers. The
Ebox scratchpad address (ESPA) register and the Ebox scratch pad data
(ESPD) register are used by VMS machine check code to access Mbox status information when single-bit errors are processed in the memory array.
The status information is saved by the error-handling microcode in the
Ebox scratchpad memory locations 25 through 2B (hexadecimal).
Ebox Scratchpad Address Register The ESPA is a write-only register that
contains the address of an Ebox scratchpad memory location to be
accessed. Figure 10-75 shows the format of the register information.

24 23
I

16 15
I

~ I

NOT USED

8 7

I~II
SCRCH PAD ADDR

Figure 10-75 • Ebox Scratchpad Address Register Format

10-80' VAX Privileged Registers

Bit

Function

31:8

Not used.

7:0

SCRCH PAD ADDR (Ebox scratchpad address) - Contains the
address from 25 to 2B (hexadecimal) of the Ebox scratchpad
location to be accessed.

Ebox Scratchpad Data Register The ESPD is a read-only register that contains the error status information in the Ebox scratchpad memory. Figure
10-76 shows the format of the data in the register.

16 15

2423

[

8
I

SCRCH PAD DATA

Figure 10-76 • Ebox Scratchpad Data Register Format

Bit

Function

31:0

SCRCH PAD DATA (Ebox·scratchpad data) -Contains the error
status information saved in the Ebox scratchpad memory.

• FP86 FLOATING-POINT ACCELERATOR
The FP86 floating-point accelerator option contains an internal register to
control and monitor the accelerator operation as described.
The accelerator controVstatus (ACCS)
is a read-write register that controls the operation and provides status
information on the FP86 floating-point accelerator option (Fbox). Figure
10-77 shows the format of the information in the register.

Accelerator ControllStatus Register

10-81

(

8 7

24 23
I

I I

...

MBZ

REt NO

I I

•

TYPE

FBOX ENB-.l

Figure 10-77 • FP86 Accelerator Control/Status Register Format

Bit

Function

31:24

Not used.

23:16

REV NO (Revision number)- The revision number of the FP86 or
the floating terminator module (FJM) and floating jumper module
(FJM) when the accelerator is not installed.

FBOX ENB (Fbox Enable) - Enables the Fbox to allow the
execution of floating-point instructions.

14:8

Not used.

7:0

TYPE-A value that specifies the type of accelerator as follows:
Value 1- FP86 installed
Value 0 - FP86 not installed

The VAX processors connect to devices, networks, and other VAX processors through the input/output (1/0) subsystems. These subsystems electrically connect the devices and processors to memory through the internal
processor bus of each VAX processor. Several 110 subsystems are available.
The number and type of subsystems that can be used depends on the VAX
processor type, communication speed, and the peripheral devices or systems to be connected. The subsystems permit fast and reliable transfer of
information. This chapter describes the general functions and operation of
each subsystem.
To simplify the reference to VAX processors in this chapter, the processors
are grouped into categories by physical size and computing power, as
follows:

Processor Type

System

Small
Medium
Large

VAX-ll/725 and VAX-1l1730.
VAX-1l1750.
VAX-ll/780,VAX-ll/782,VAX-ll/785,
and VAX 8600 .

. 110 Subsystem Allocations
Four 1/0 subsystems are available for implementation with VAX processors. They are the UNIBUS subsystem, the MASSBUS subsystem, the Computer Interconnect (eI) subsystem, and the DR32 Device Interconnect
(DDI) subsystem.
The UNIBUS subsystem consists of a UNIBUS adapter (UBA) and an asynchronous, bidirectional bus. It can communicate with many different
types of intelligent and nonintelligent interfaces and devices. The subsystem supports a large number of standard Digital devices developed for
both PDP-ll processors and VAX processors. It permits low- and mediumspeed data transfers with the connected devices. Through the use of direct
memory access (DMA) capability of the UNIBUS subsystem, blocks of data
can be transferred to memory quickly and efficiently.

11-2· VAX Input/Output Subsystems

The MASSBUS subsystem consists of the MASSBUS adapter (MBA) and a
high-speed, synchronous communication link between mass storage
devices and the host processor. Blocks of data are transferred to the processor memory through the MASSBUS subsystem without the intervention of
the processor at rates of up to 2 Mbytes per second. The MASSBUS device
.registers are addressed the same way as processor memory locations.
The Computer Interconnect (CI) subsystem consists of a CI adapter and a
high-speed, dual-path, communication link between VAX processors and
between VAX processors and intelligent mass storage subsystems. The CI
subsystem operates with the VAXcluster architecture to allow sharing of
processing facilities and mass storage resources. Data is transferred in
packets through high-speed, dual-path coaxial cables. The CI subsystem
allows VAX processors to be added to the VAXcluster architecture when
required and data can be shared by any of the processors.
The DR32Device Interconnect (DDI) subsystem is a high-speed, 32-bit,
parallel, data communication path between Digital- or customer-developed
devices. The DDI consists of an interface adapter and DDI bus and permits
transfer of high-resolution information at rates of up to 6.67 Mbytes per
second. Both command and data chaining are used to enable multiple 110
operations to occur without software intervention.
Table 11-1 lists the type and quantity of 110 subsystems that can be implemented on each VAX processor. The UNIBUS 110 subsystem is proviqed
with all VAX processors and the subsystem communicates directly with the
processor logic.

TABLE 11-1 • VAX Processor 110 Subsystem Allocations
Processor

UNIBUS

VAX-1l1725
VAX-1l1730
VAX-1l1750

I-standard
I-standard
I-standard
I-optional
I-standard
3-optional
I-standard
3-optional
1-standard
3-optional

VAX-1l1780
VAX-1l1782
VAX-1l1785

I/O Subsystem
MASSBUS
CIBus

DDIBus

none
none
3-optional'

none
none
I-optional

none _
none
I-optional

4-optionaP

I-optional

4-optional2

I-optional

none

4-optional2

1-optional

11-3

Processor

UNIBUS

VAX 8600:
SBIAO
(standard)
SBIA l'
(optional)

I-standard
2-optional
4-optional

110 Subsystem
MASSBUS
CIBus

DDIBus

none

I-standard

none

4-optional

2-optional4

4-optional4

Notes: (1) The number of MASSBUS subsystems is reduced to two when
the optional UNIBUS subsystem is installed.
(2) The number of MASSBUS subsystems is reduced by one for each
optional UNIBUS subsystem installed.
(3) The optional SBIA 1 can include up to eight I/O adapters in any
combination, provided that the 13.3, Mbyte-per-second SBI
aggregate bandwidth is not exceeded.
(4) Two CI780 adapters or two DR780 adapters may be installed on
SBIA 1, or one CI780 adapter and one DR780 adapter may be
installed.

UNIBUS Subsystem
The UNIBUS subsystem, included with all VAX processors, allows low- and
medium-speed, asynchronous, bidirectional data transfers with many types
of terminal, data storage, and network devices. VAX-1I1725 and VAX-Ill
730 processors contain a single UNIBUS subsystem. The VAX-1l1750 processor includes a UNIBUS subsystem, and one UNIBUS subsystem can be
added by installing the DW750 UNIBUS adapter (UBA). The VAX·1I1780
series of processors contains a UNIBUS subsystem and three can be added.
Each additional UNIBUS requires a DW780 adapter. The VAX 8600 processor includes a UNIBUS subsystem on the first SBIA and two can be added
by installing a DW780 UNIBUS adapter for each subsystem. A total of four
UNIBUS subsystems can be connected to the optional second SBIA.
The UBA connects the processor logic to the data, address, and control
lines of the UNIBUS. It performs address translation and device priority
arbitration, and permits tl,Je processor to access device registers. Figures
11-1 through 11-3 show the configuration of the UNIBUS subsystem for the
VAX processors. The UNIBUS offers the following features and functions:

11-4· VAX Input/Output Subsystems

• Permits direct memory access (DMA) transfers at high data transfer rates
without CPU intervention.
• Simplifies 110 programming by allowing UNIBUS device registers to be
accessed using the same addressing scheme used to access main memory.
• Allows data to be directly transferred between devices without CPU
involvement.
• Supports many types of standard Digital devices and non-Digital
devices.
• Permits direct-vectored hardware interrupts to service routines, thereby
eliminating polling tasks of the processor.
• Contains buffered data paths to increase data throughput rates.

UNIBUS

I/"

~~R_ ~r--_=-_....;UNI=B;;;,;U::":S'--D-::;:---'>
UNIBUS

UNIBUS

INTERFACE
OR ADAPTER
(1)

INTERFACE
OR ADAPTER

NETWORK
OR DEVICE

(N)*

NETWORK
OR DEVICE

*Total number of adapters depends on adapter type and system configuration.

Figure 11-1· Small-VAX Processor UNIBUS Subsystem

11-5

UNIBUS
ADAPTER
LOGIC
(INTERNAL)

C
M
I
B
U
S

<=>

UNIBUS
ADAPTER
(DW750)

<
UNIBUS
INTERFACE
OR ADAPTER

UNIBUS
INTERFACE
OR ADAPTER

(1)

(N)*

NETWORK
OR DEVICE

UNIBUS (OPTIONAL)

UNIBUS
INTERFACE
OR ADAPTER
(1)

NETWORK
OR DEVICE

*Total number of adapters depends on adapter type and system configuration.

Figure 11-~ • Medium-VAX Processor UN/BUS Subsystem

UNIBUS
ADAPTER
(DW780)

<'---D-"---=:-=:=:"---Z:-->
UNIBUS

S
B

I
B
U

UNIBUS
INTERFACE
OR ADAPTER

UNIBUS
INfERFACE
OR ADAPTER

(1)

(N)*

NETWORK
OR DEVICE

*Total number of adapters depends on adapter type and system configuration.

Figure 11-3· Large-VAX Processor UN/BUS Subsystem

11-6· VAX Input/Output Subsystems

MASSBUS Subsystem
The MASSBUS subsystem, an optional I/O subsystem for medium- and
large-VAX processors, permits synchronous data transfer to high-speed
mass storage devices at rates of up 2 Mbytes per second. Devices that
operate with the MASSBUS include large-capacity disk drives and magnetic
tape devices. The MASSBUS subsystem includes diagnostic programs that
allow online testing of MASSBUS devices. The RH750 MASSBUS adapter
(MBA) is used with the VAX-111750 processor and the RH780 MBA is used
with large VAX processors. The MBA connects the processor logic to the
MASSBUS data, address, and control lines. The MBA performs address
translation and priority arbitration and allows the processor to access the
registers in the devices connected to the MASSBUS. Figures 11-4 and 11-5
show the configuration of the MASSBUS subsystem for medium- and largeVAX processors. The features of the MASSBUS subsystems are as follows:
Permits synchronous data transfers at rates of up to 1.3 Mbytes per
second.
Allows direct memory access (DMA) transfers without processor
intervention.
Contains a 32-byte silo to buffer data transferred between main memory
and MASSBUS devices.
Contains internal diagnostic features that allow online diagnosis of the
MASSBUS subsystem and tape and disk drives .
• Allows MASSBUS device registers to be addressed in the same manner
that main memory is addressed.
Maps virtual addresses to physical addresses.
Transfers interrupts from mass storage devices to the SBI.

11-7

~~~~ <'------:-MA-;-c-;S"'"SB""'U-,-;S:---------')

(RH750)
C
M
I

B
U

DISK DRIVE
OR MAGNETIC
TAPE
FORMATTER
(1)

DISKDRlVE
OR MAGNETIC
TAPE
FORMATTER
(8)

40R8TAPE
TRANSPORTS

40R 8 TAPE
TRANSPORTS

* 4 tape transports for TU?? magnetic tape formatter.
8 tape transports for TE 16 magnetic tape formatter.

Figure 11-4 • Medium-VAX Processor MASSBUS Subsystem

<=> ~~~~
(RH780)

S
B
I

B
U

MASSBUS

,--------,~-==..:::.::...----,D;;;;::--

DISKDRlVE
OR MAGNETIC
TAPE
FORMATTER
(1)

DISKDRlVE
OR MAGNETIC
TAPE
FORMATTER
(8)

40R8TAPE
TRANSPORTS

* 4 tape transports for TU?? magnetic tape formatter.
8 tape transports for TE 16 magnetic tape formatter.

Figure 11-5· Large-VAX Processor MASSBUS Subsystem

11-8· VAX Input/Output Subsystems

Computer Interoonnect Subsystem

The Computer Interconnect (CI) subsystem is an option for medium- and
large-VAX systems that permits high-speed, serial-data transfers between
VAX processors and between VAX processors and intelligent mass storage
subsystems. The CI subsystem consists of a CI adapter and two transmit
and two receive coaxial cables. Data can be exchanged at rates of up to 70
Mbits per second. The dual-path capability ensures the dependable transfer of data and control information. The CI750 adapter is used with the
VAX-111750 processor and the CI780 adapter is used with the large-VAX
processors. The CI adapter is the interface between the internal processor
bus and the coaxial cables that connect to the SC008 Star Coupler unit.
The SC008 unit is common connecting point for up to'16 VAX systems or
mass storage subsystems. The CI adapter performs address translation and
data formatting, and transposes the information during both transmission
and reception. Figures 11-6 and 11-7 show the confIguration of the CI
subsystems, which Qffer the following features:
• Contains a dual7path, serial-line interface that enables high-speed and
efficient information transfers.
• Easily installed to facilitate local network expansion of existing VAX systems or expansion of storage subsystems in a VAXcluster.
• Permits simultaneous operation of dual transmission paths to increase
data throughput rates and the reliability of transmission.
• Eliminates control-line functions by transferring packet-oriented
information.
• Contains buffered communication ports to increase data transfer rates.
• Reduces system overhead by optimizing communication and by performing error checking and bus contention functions.

C
CONWUTER
M
I ~ INfERCONNECT 1_-.:.XMI=:.:.T-=2:..::;U;::NES=.::_ SCOO8
'\,-,I
ADAPTER
RECV 2 liNES
STAR
(CI750)
COUPLER

e
S

Figure 11-6 • Medium-VAX Processor CI Subsystem

11-9

M
COMPUTER
I /'-"\ INTERCONNECT 1__2--=XMI=-=-.:::;cT=--L::;:I::. .NE-=-.S_
'\r-v'
ADAPTER
2 RECV LINES
(CI780)

SC008
STAR
COUPLER

Figure 11-7 • Large-VAX Processor CI Subsystem

DR32 Device Interconnect Subsystem
The DR32 Device Interconnect (DDI) is a high-performance, general purpose subsystem that enables bidirectional data communication between
VAX systems and user-developed devices or between VAX processors. The
subsystem connects to the eMI bus of the VAX-11/750 processor and to the
SBI bus of the large VAX processors. It permits continuous streams of 32bit parallel data to be transferred to or from memory at rates of up to 6.67
Mbytes per second. The DR32 consists of a DDI adapter and bus. The
DR750 DDI adapter is used with VAX-11/750 processor and the DR780
DDI adapter is used with the VAX-11/780 series processors and the VAX
8600 processor. The DDI adapter is an intelligent interface that formats
data and controls data transfer. The DDI is fully supported by the VMS
operating system with a simple, easy-to-use I/O driver routine and a library
of high-level language support routines. The function and configuration
information of the DR32 are defined in the Digital DR32 interface
specification.

The DDI subsystem configuration for the VAX-11/750 processor is shown
in figure 11-8 and the VAX-111780 series processors and the VAX 8600
processor are shown in figure 11-9. The features of the DDI are as follows:
• Permits communication between VAX processors and between VAX
processors and Digital- or customer-developed devices.
• Contains 32 parallel data lines for high resolution and 8 control lines for
versatile device configurations.
• Allows I/O transfer rates up to 6.7 Mbytes per second.
• Permits the chaining of commands so that multiple I/O operations can be
performed without software intervention.

11-10· VAX Input/Output Subsystems

• Allows user-generated command packets to be processed without the
intervention of the operating system.
• Permits data chaining to allow continuous streams of data to be transferred to and from memory.

GENERAL
PURPOSE
32-BIT PARALLEL
INTERFACE 1\ DATA LINES
(DR750)

USER DEVICE
OR
VAXSYSTEM*

*VAX-111750, VAX-111780, VAX-11/782, VAX-1I1785 or VAX 8600.

Figure 11-8· Medium-VAX Processor DDI Subsystem

S
B

I<=>

B
U

GENERAL
PURPOSE II 32-BIT PARALLEL
INTERFACE 1\ INTERFACE BUS
(DR780)

USER DEVICE
OR
VAXSYSTEM*

S
*VAX-11I750, VAX-111780, VAX-111782, VAX-11I785 or VAX 8600.

Figure 11-9· Large-VAX Processor DDI Subsystem

·110 Subsystem Operation
Each I/O subsystem performs similar functions when operating with a VAX
processor; however, the method of subsystem implementation may vary
depending on the processor. The following paragraphs describe the general
I/O subsystem operation, register formats, and the functional differences
between processors. The operation of the eMI bus of the VAX-ll/750
processor and the SBI bus of the large VAX processors is described in
Chapter 9, "VAX Computer Bus Interconnects."

11-11

AOO-AI7 (ADDRESS)
DOO-D1S (DATA)

COO-COl (CONTROL)
MSYN (MASTER SYNC)

UNIBUS
DEVICE

SSYN (SLAVE SYNC)
PA-PB (PARITY)
BR4-BR7 (BUS REQUEST)
BG4-BG7 (BUS GRANT)
NPR (NONPROCESSOR REQUEST)
NPG (NONPROCESSOR GRANT)
SACK (SLAVE ACKNOWLEDGE)

UBA

INTR (INTERRUPT)
BBSY (BUS BUSY)
INIT (INITIALIZE)
AC LO (AC LINE LOW)
DC LO (DC LINE LOW)

Figure 11-10 • UNIBUS Signal Lines

UNIBUS Subsystem Functions
The UNIBUS subsystem is the communication path that connects low- and
medium-speed devices and networks to the VAX processors. A complete
series of standard and special devices has been developed to operate with
the UNIBUS. A UNIBUS subsystem can be added to an existing VAX system
by installing a UBA adapter module and cable. The DR750 adapter is used
with the VAX-ll/750 processor and the DR780 adapter is used with the
VAX-ll/780 series processors and the VAX 8600 processor.

• UNIBUS SIGNAL LINES
The 56 lines of the UNIBUS transfer data, address, and control signals
between the UBA and devices as shown in figure 11-10. The data information is transferred through 16 lines, and the address information is transferred through 18 address lines. The remaining lines provide status,
control, and voltage monitoring functions. Table 11-2 lists the functions of
the UNIBUS lines.

11-12· VAX Input/Output Subsystems

TABLE 11-2· UNIBUS Line Functions
Line

Function

AOO-Al7

Address-Transfers memory or device register addresses. Line
AOO specifies the transfer of a byte or word of data: 1 = byte
and 0 = word.

DOO-Dl5

Data-Transfers data information.

COO-COl

Control-Determines the data transfer operation as follows:

COl COO Operation

DATI (Data in) - Transfer a word or byte from slave

to master.

DATIP (Data-in-pause) - Transfer a word or byte

from master to slave. This is followed by either a

DATO or DATOB transaction.
DATO (Data out) - Transfer a word from master to

DATOB (Data-out-byte) - Transfer a byte from

slave.
master to slave. Bit AOO specifies the byte to be
written, as follows: 0 = low byte (D07-DOO) and
1 = high byte (Dl5-D08).
MSYN

Master synchronization - Asserted by the master device to
indicate that valid address and control information is on the
UNIBUS.

PA-PB

Device parity - Indicates the parity of the device information as
follows: PA is not used, PB when true indicates a device parity
error.

BR7 -BR4

Bus requests - Asserted by peripheral devices to request
control of the bus.

BG4-BG7

Bus grant-Asserted by UBA in response to a bus request.

NPR

Nonprocessor request-Asserted by a device to request an NPR
transfer.

NPG

Nonprocessor grant - Asserted in response to an NPR request.

SACK

Slave acknowledge-Asserted by a device in response to
receiving a bus grant.

BBSY

Busy - Asserted by the bus master to indicate that the bus data
lines are in use.

INIT

Initialize - Asserted by the UBA to initialize the bus devices
after DC LO line is asserted.

11-13

Line

Function

ACLO

ac line low - Asserted to indicate that the ac voltage is below
the acceptable standards; initiates the UNIBUS powerfail
sequence or terminates the device operation.

DCLO

dc line low - Asserted to indicate that the dc voltage is below
the acceptable standards .

• UNIBUS ADAPTER OPERATION
The UNIBUS adapter (UBA) is the data path for the transfer of information
between the processor and UNIBUS devices. It enables access to device
data and control information by translating internal bus "addresses from the
processor into addresses of the UNIBUS and device registers. It also translates the UNIBUS addresses into physical memory addresses during DMA
transfers, which are performed through fully buffered ports. The UBA provides priority arbitration among the UNIBUS devices that request the use of
the bus. Direct-vectored interrupt capability is performed for both program and functions and for I/O device operations. The UBA also initiates a
powerfail sequence when a power failure occurs or when it is directed by
the program .
• COMMUNICATION AND CONTROL
A master-slave relationship exists during communication between any two
devices on the UNIBUS. During a bus operation, the device in control of the
bus is the bus master and the device being addressed is the slave. A processor or peripheral device can be bus master and also can access information
from another device as a slave. The processor may transfer bus control to a
disk drive, which can then communicate with the processor memory as a
slave. When two or more devices contend for bus master, a priority scheme
determines which device will obtain bus control. All control signals are
interlocked so that a signal issued by the bus master must be acknowledged
by a reply signal from the slave. The four types of data transactions that can
be initiated between master and slave are described as follows:
• Data in (DATI)- Transfers a word or byte from slave to master.
• Data in, pause (DATIP) - Initiates a read-from-slave or write-to-slave
transaction during a single bus cycle. This command is followed by a
DATa or DATOB transaction to the same location to complete the
sequence.

11-14· VAX Input/Output Subsystems

• Data out (DATa) - Transfers a word of data from master to slave .
• Data out, byte (DATOB) - Transfers a byte of data from master to slave .

• ADDRESS TRANSLATION
The UBA contains a UNIBUS map that translates device-generated
addresses into physical memory addresses. It also identifies UNIBUS transfer:>- so that other features, such as odd-byte addressing, can be appropriately used.
rThe 18 UNIBUS address lines can select addresses of 256 Kbytes. The UBA
map is grouped into two regions, a lower address region consisting of 248
Kbytes and an upper 8-Kbyte region. The lower region is assigned to the
device memory locations and the upper region to the addresses of the
device control and status registers.
The address space is sectioned into 512 pages, each consisting of 512 bytes.
Addresses that are contiguous in the virtual address space may be noncontiguous in the physical address space of the 512-byte boundaries. Because
UNIBUS devices often use sequential addresses, the UBA breaks the
sequential addresses to select the proper 512-Kbyte block. The upper 9
bits of the address are decoded in the UBA map to provide the page frame
number (PFN) of the physical memory address. This information is concatenated with the word or byte location within a page that is decoded from
the remaining 9 bits of the address information. The map also specifies
whether the address should be incremented by one to select an odd memory location and whether the direct data path or one of the three buffered
data paths should be used .
• PRIORITY ARBITRATION
Two types of data transmissions can be performed on the UNIBUS subsystem: bus request (BR) transfers and nonprocessor request (NPR) transfers.
The BR interrupts the processor operation and directs the processor to
perform a device routine to service the requesting device. The interrupting
device sends the processor a vector address that is a location in memory
containing the address of a service routine. The NPR allows the transfer of a
word or byte of information from a direct memory access (DMA) device
directly to memory without intervention of the processor.
The priority arbitration logic is contained in the processor and in the UBA.
The priority structure, shown in figure 11-11, includes priority levels NPR
and BR7 through BR4, which are assigned during the installation of the
system. The NPR line is the highest priority level and the BR4 line is the

11-15

lowest. Each request line has an associated bus grant line, NPG for the NPR
line and BG7 through BG4 for the BR7 through BR4 lines. These lines are
distributed serially through each device that is positioned at the same level.
Devices that are assigned a high priority level will be granted the bus use
ahead of devices with a lower prioriry level. When devices are assigned the
same priority level, the device that is electrically closest to the processor has
precedence over more distant devices. If the processor has control of the
bus and more than one device with higher priority than the processor
request control, the processor will grant the bus to the device with the
highest prioriry. If the requesting devices are of the same priority, the reply
signal from the processor will be transferred through the priority line to the
nearest requesting device, passing through nonrequesting devices in the
process. The requesting device then takes control of the bus, executes one
or more bus transactions and relinquishes the bus. The next device on the
priority line will then be granted control. When all requests have been
granted, the control of the bus is returned to the processor. The processor
is rypically assigned a lower priority than devices performing time-critical
functions such as realtime process control where data loss can be critical.

DEVICE
REQUEST
LINE

CP
PRIORITY

-NPR--~-_---~-_---~---<_-----

- - --

~~~
-

BR7--~-_---~-_---------- -

BR6--~-_---~-_---------- -

BR5--~-_---~-_---~-_----- -

G:J

~ ~

C£!::J ~ ~
-

•
•
•o

i
el

-diJ---1

BR4-[f]-HSR-C£]----<H-SP- C E - - K B

"""- TP

INCREASING PRIORITY

Figure 11-11 • UNIBUS Priority Assignments

11-16· VAX Input/Output Subsystems

Priority is assigned according to the operating speed of the device, the ease
of data recovery, and the service requirements. Disk and tape storage
devices are usually assigned a higher priority than line printers because of
their faster transfer rates. Printers normally operate at slower speed than
storage devices and the data is available for a longer period of time. The
processor priority level is programmable and consists of up to 32 levels,
with levels 14 through 17 (hexadecimal) corresponding to UNIBUS levels
BR4 through BR7.
.
• DATA PATHS
A direct data path and three buffered data paths are included in the UBA.
The direct data path is used for devices that interrupt the processor for
each bus transaction, and the buffered data' paths are used for devices
capable of NPR transfers that do not require the control of the processor.
Using the direct data path, 2 bytes of data are transferred between the
memory and the device during each transaction. The UBA ensures that
each UNIBUS transaction results directly in a memory transaction when the
data is transferred.
The buffered data paths are used with direct memory access (DMA) trans• fers to optimize the use of memory and to increase the transfer speed. Each
buffered data path operates as a cache and contains an address register and
a 4-byte buffer register. The data is assembled into a 4-byte longword
before each transaction with memory. A memory cycle is required only
when the cache is not able to accept a request. If more than one NPR device
is performing address transfers, the addresses that arrive at the UBA will
not be sequential. During most DMA transactions, the memory locations
are sequentially accessed and processor action is not necessary. Because
requests are processed in a buffer before a memory access can occur, the
buffered data paths improve UNIBUS access time. A memory cycle is
required only when a request cannot be accepted from the cache. The
three buffers ensure that the addresses are sequential when more than one
NPR device is transferring information at the same time. The address
received by the UBA will not be sequential.
The VMS operating system supplies standard system routines to allocate
and release the buffered data paths and blocks of map registers. Standard
routines also set up the allocated map registers for a transfer and convert
the buffer address to a UNIBUS space address for loading into the device
buffer address register. Addresses are provided in 110 space for loading the
map and controlling the buffered data paths when VAXlVMS software is
not used.

11-17

• DEVICE REGISTERS
The transfer of data and status information through the UNIBUS is controlled by the device and device-control unit registers. The device registers
are assigned addresses similar to the addresses assigned to memory locations and can be accessed by word-type memory-referenced instructions
such as MOVW or BITW instructions. Control and status functions are
assigned to the bits within the addressable register. The device service
operations are controlled by setting and clearing the bits in these registers.
Internal device status can be loaded into the registers and retrieved when a
program instruction addresses the register. The entire register or the individual bits within a register can be read from or written to, or both read
and written, depending on the register configuration. The functions of the
device registers are defined in the user documentation. The functions of
the UNIBUS registers are described in the sections that follow.
• INITIALIZATION AND POWER FAILURE
The UBA controls powerfail, powerup, and initialization operations of the
UNIBUS. The UNIBUS remains in a powered down state when the UBA is
powered down. When the system power is applied, the UBA initiates a
powerup sequence and when completed, the UNIBUS issues an interrupt
request to the processor. The powerup sequence initializes the registers
and functions of the UBA. When a power failure is detected, the UBA initiates a powerfail sequence resulting in an interrupt request to the processor.
The UNIBUS remains in a powered down state until the power is restored
and the UNIBUS powerup sequence is completed. A powerfail condition
can be initiated by the program to induce the powerfail sequence when
required to test the initialization procedure.

Small- and Medium-VAX Processor UNIBUS Operation
The operation of the UNIBUS is similar in the small- and medium-VAX
processors. The VAX-1l1725, VAX-ll/nO, and VAX-1l1750 processors
include one UNIBUS subsystem. An additional UNIBUS subsystem can be
installed on the VAX-111750 processor.
Interrupt requests are generated by devices, contmIIers, and memory and
cause the processor to change its operation from the normal instruction
execution to a service routine. The interrupting device supplies a vector
address, which directs the processor to a memory location that contains the
starting address of the interrupt service routine. When servicing the interrupt, the processor raises its priority to the level of the interrupting device.
Interrupt requests from devices on the UNIBUS are directly addressed
through the system control block (SCB) in the processor. In small-VAX
processors, the address of the UNIBUS device routine is determined by
adding a 200 (hexadecimal) value along with the vector value to the system

11-18· VAX Input/Output Subsystems

control block base (SCBB) address. In medium-VAX processors,
where service routines for the first UNIBUS device are determined in the
same way as for the small-VAX processors, 400 (hexadecimal) is added to
the SCBB and the vector value for devices on the second UNIBUS. The
device vectors assigned are the same as for PDP-II processor UNIBUS.
During DMA transfers, the UBA performs the address translation to separate the sequential addresses transferred from the NPR device into noncontiguous 5I2-byte boundaries of the main memory. No restrictions are
imposed on the alignment of the data in memory; however, the data words
must be transferred on even addresses only. Because the UNIBUS devices
can address a maximum of 256 Kbytes of memory, the address translation
process of the UBA gives the devices access to the full range of physical
address space. The UBA contains three buffered data paths to enable the
UNIBUS devices to access the data in 4 bytes, thereby providing efficient
transfers.
Processor access with a physical address of FCOOOO through FFFFFF (hexadecimal) maps directly to UNIBUS addresses 0 through 777777 (octal). In
the VAX-ll/750 processor, the optional second UNIBUS has a physical
address range of F800000 through FBFFFFF (hexadecimal). Internal
devices, other than the processor, that reference the second UNIBUS
address range will cause the device to receive a nonexistent memory error
confirmation. When this occurs in the VAX-1l/725 or VAX-1l1730 processor, the device receives a timeout error.
The UBA responds to byte- or word-aligned transactions. The types of
operations are:

Transaction

Operation

Read
Read and modify
Read lock
Write
Write unlock

DATI
DATIP
DATIP
DATO or DATOB
DATO or DATOB

The information on the UNIBUS address lines is a pointer to the UNIBUS
map location, which then provides the physical memory address. Address
bits A17:A09 are used to address a 5I2-byte by 23-bit memory location in
small-VAX processors and a 5I2-byte by I9-bit location in the mediumVA.,X processors. In the small-VAX processors, the map data field is grouped

11-19

into three sections consisting of the page-frame number, the byte offset,
and the valid bit. In medium-VAX processors the map data field also
includes a data path number. The format of the map data fields are shown
in figure 11-12.

31 30

26 25 24 23

16 15 14

11,11 ,.Ill , , J ' , , II

VALID

NOTtSED·

DATA PATH

8 7
I

PACE FR~ME NO

BYTE OFFSET--1

Figure 11-12 • UBA Map Data Field Format

Bit

Function

VALID-Set to indicate that the information from the UNIBUS map
is valid.

30:26

Not used.

BYTE OFFSET - Set to indicate that the UNIBUS reference is an
odd byte location.

24: 15

DATA PATH NO (Data path number) - A binary number that
selects one of the four data paths as follows:
VAX-11/725 and VAX-11/730 processors: Not used.

VAX-11/750 processor: 0 = direct data, 1-3 = buffered data path
1 through 3.
14:00

PAGE FRAME NO (Page frame number)-Selects the physical
memory location.

In the VAX-11/750 processor, if the valid bit (bit 31) is set, the integral
UNIBUS adapter will process the transaction as described. When it is
cleared, the integral UNIBUS adapter ignores the UNIBUS requests. The
valid bit is cleared for map entries that correspond to sections of UNIBUS
address space containing slave devices that are expected to respond to
transactions originating on the UNIBUS. Transactions from the CPU that
result in a UNIBUS transaction are always ignored by the integral UNIBUS
adapter and can never wrap back through the UNIBUS adapter to memory.

11-20· VAX Input/Output Subsystems

If the byte offset (bit 25) is set, the address supplied by the DMA device is
incremented by one to allow devices that generate only even-byte addresses
to access buffers on odd-byte boundaries. A transaction that causes a word
to cross page boundaries because the offset bit is set must have the same
data path number, offset bit, and valid bit in both map entries. If the transaction is a DATI, DATIP, or DATa and the two bytes of UNIBUS data cross a
longword boundary, two memory cycles will occur.
The data path numbers (bits 22:21) select the direct data path for the BR
requests and the buffered data paths for the DMA transfers. A data path
number of 0 is the direct data path and numbers from 1 to 3 select buffered data paths 1 to 3 respectively. Each of the three data paths consists of
4 bytes of data storage, a 16-bit address, and 5 flag bits. These registers and
flags are not accessible to the software.
UNIBUS transactions to ascending or descending sequential addresses or to
nonsequential addresses require only one data memory transfer for every
two UNIBUS transfers. During UNIBUS-initiated transactions that cause a
memory read or write cycle to occur, the map PFN is concatenated with
UNIBUS address (bits A8:AO) to form a 24-bit physical address. Figure lID shows this address translation process.

UNIBUS ADDRESS

UBAMEMORY
(SI2-BYTE)

PFN

9 8

...J'LL.J.?_NJ..~...J'j'-0..L~D-L.,....l'-ll

PHYSICAL ADDRESS LI.J.'-L'...J''--'.'-L.'....l,_PFJ..,N..J'L....J.'-L'...J''--'.'-L.'....ll-L'

Figure 11-13 • UNIBUS-to-Physical-Address Translation

11-21

The map is accessible for reading and writing. Each entry uses a longword
address of from F30800 to F30FFC (hexadecimal) for the first UNIBUS and
F32800 to F32FFC (hexadecimal) for the optional second UNIBUS. A
longword must be sent to the map address during a write transaction or the
contents of the written map location will be unpredictable.
Buffered Data Path Operation- The buffered data path can be loaded from
the UNIBUS or from the memory and its contents can be transferred to the
UNIBUS or memory. One or two bytes at a time can be loaded into the
buffer from the UNIBUS; four bytes at a time are loaded from memory.

Five flags in the data path indicate the status of the data buffer. If the CD
flag is set, the buffer has 4 bytes of data from memory and flags BF3
through BFO are cleared. If the CD flag is cleared, flags BF3 through BFO
indicate which bytes in the data buffer have valid UNIBUS data. If the
buffer is empty, then all flags are cleared.
Each buffered data path contains a 16-bit address register that can be
loaded from UNIBUS addresses lines (A17:A2). The stored address is
compared with the address on the UNIBUS for the same value. The
address held in the register is the UNIBUS longword corresponding to the
data in the data buffer. The following operations are described for each
transaction:
• DATI and DATIP- The UBA performs similar operations during the DATI
and DATIP transactions, as determined by the contents of the data and

address buffers. These transactions allow a device to use a buffered data
path to perform a sequence of transfers in either direction using any
address sequence. A device that performs repeated transfers within the
same longword, however, will not cause memory cycles to occur. If the
buffer is empty or contains memory data but the address in the address
register is not the same as the UNIBUS address, the following transactions
occur: The UBA reads the memory data and transfers it to the buffer and
to the UNIBUS, loads the UNIBUS address into the address register, sets
the flags to indicate that data is in the buffer, and transfers the data to the
requesting UNIBUS device. If the buffer contains data, the UBA first
writes the stored data into memory at the location indicated by the stored
address and the byte flags as the byte mask. If the buffer contains data
and if the address in the address register is the same as the UNIBUS
address, then data is transferred to the UNIBUS .
• DATI and DATIP with byte offset-If the map specifies a byte offset, the

operation depends on whether the transaction crosses a longword
boundary. If the boundary has not been crossed, then the response is
identical to that described for DATIP. If a longword boundary has been
crossed, the UBA performs one memory read operation at the given
UNIBUS address and a second memory read operation at the same

11-22· VAX Input/Output Subsystems

address but incremented by two. The two memory reads are assembled to
form the UNIBUS data word. The data buffer and address register hold
the information from the second read at the end of the transaction.
• DATO or DATOB- The contents of the buffer determine the UBA opera-

tion. Whether the buffer is empty or contains data, the UBA transfers the
UNIBUS data to the data buffer, loads the UNIBUS address into the
address register, sets the appropriate status flags to indicate the amount
of data in the buffer, and informs the UNIBUS device when the transaction is completed. If the buffer has UNIBUS data and the address in the
address register is the same as the UNIBUS address, then the operation
depends on whether the UNIBUS data, combined with the data in the
buffer, form a longword; If a longword does not exist, the same operation
occurs as if the buffer were empty or had memory data. If the data forms
a longword, the data will be written into memory and the data path flags
will be cleared to indicate that the buffer is empty. If the buffer has
UNIBUS data and the addresses are not the same, then the data is written
into memory and the data path flags are cleared to indicate that the
buffer is empty. The UBA will then perform the same operations as it
would with the buffer empty.
• DATO with byte offset - If this transaction crosses a longword boundary,

the UBA performs two one-byte writes. If it does not cross a boundary,
the UBA performs the same operation as with a DATO or DATOB
operation.
• DATOB with byte offset-If this transaction does not cross a longword
boundary, the same transaction is performed as with the DATO or DATOB

and the address is incremented by one. If a longword boundary is crossed,
a DATOB operation is performed in the next longword and the same
addresses are forced to become different.

Control and Status Registers- Small-VAX processors have a single data path
for the UNIBUS transfer operations. This data path has an associated readonly controVstatus register (CSR2) that provides pertinent information to
the operating system to ensure the satisfactory transfer of data. Figure 1114 shows the format of information in the register.

11-23

31 30

UBRD

NO::J~:N

JJtu

NOT USED

EXIST MEM
UB TB PAR ERR
WRNOTVALlD

Figure 11-14· Small-VAX Processor UNIBUSCSR2 Format

Bit

Function

UB RD (UNIBUS read) - Set to indicate that an uncorrectable data
error has occurred during a UNIBUS read to memory.

30:17

Not used.

UB NON EXIST MEM (UNIBUS nonexistent memory) - Set if a
UNIBUS request references a nonexistent memory array.

UB TB PAR ERR (UNIBUS/memory transaction parity error) - Set to
indicate that the UNIBUS/memory transaction resulted in a parity
error.

WR NOT VALID (Write not valid)-Set during a two-cycle
operation if an attempt is made to write to a page that does
not have a valid entry in the translation buffer.

13:00

Not used.

Medium-VAX processors contain three separate control/status registers,
one for each buffered data path. These registers are used by the software
when intervention with the buffered data paths is required. When a device
and memory have completed a series of transactions, data may be left in a
data buffer if the transfer did not end on an even longword boundary. The
corresponding UNIBUS address of the data will be contained in the address
register. If the contents of the map are changed before the data is removed,
the association between address and data in the buffer will not be correct.
The software must therefore initiate the action to write this data to memory
and clear the buffer. Figure 11-15 shows the format of control/status register and the bit assignments.

11-24· VAX Input/Output Subsystems
31 30 29 28

24 23

IIIII " , I ,
ERR

16 15

,I,

8 7

,I,

1 0

I "

J UC

UNCORR ERR
UB NON EXIST MEM

Figure 11-15 • Buffered Data Path ControllStatus Register Format

Bit

Function

ERR (Error)-Set if either the UB NON EXISTMEM (bit 30) or the
UNCORR ERR (bit 29) are set.

UB NON EXIST MEM (UNIBUS nonexistent memory) - Set
when the UNIBUS references a nonexistent memory location. No
response is received on the UNIBUS and all future UNIBUS
transactions through the buffered data paths are ignored until the
bit is cleared by writing a one to it.

UNCORR ERR (Uncorrectable error) - Set when an uncorrectable
error status is received from memory. The parity error (PB) line is
asserted and the data is sent back to the UNIBUS device on the first
read from that location. This bit is not asserted on subsequent read
operations from this buffered data path and can be cleared by
writing a one to this bit.

28: 1

Not used.

PURGE-A read-write bit set to perform a transaction that depends
on the contents I')f the buffer. If the buffer contains UNIBUS data,
the data is written into memory and the flags indicate that the
buffer is empty. If the buffer contains memory data, then the flags
indicate that the buffer is empty. This bit is monitored by software
to indicate when the memory write operation is completed.

11-25

Large VAX Processor UNIBUS Subsystem
The UNIBUS subsystems of the VAX-ll/780 series processors and the VAX
8600 processor connect to the synchronous backplane interconnect (SBI)
bus through the DW780 UNIBUS adapter (UBA). Each VAX-ll/780 series
processor includes one UNIBUS subsystem and can accommodate three
more. The VAX 8600 processor can be installed with two SBI buses, one
supplied with the processor (SBIA 0) and one SBI bus (SBIA 1) available as
an option. One UNIBUS subsystem is supplied with SBIA 0 and two can be
added. Up to four UNIBUS subsystems can be installed on SBIA 1. Each
UNIBUS subsystem includes a UBA interface connected between the asynchronous UNIBUS and the synchronous SBI bus. The UBA provides access
to UNIBUS device registers from the SBI, translates UNIBUS addresses to
SBI addresses during DMA transfers to the processor memory, and performs priority arbitration among the UNIBUS devices. It includes a data
transfer path to enable devices to access random SBI memory addresses
and to permit high-speed data transfers to be performed to consecutive
memory addresses from UNIBUS devices. Detailed information on the
operation of the SBI is contained in chapter 9.

VAX system hardware supports a UNIBUS adapter in one of fOJlr physical
address spaces. In the VAX 8600 processor, four physical address spaces arc
provided for the standard SBI bus and four for the optional SBI bus. The
UBA maintains two independent spaces within the SBI I/O address space.
The first area of addressable space is reserved for the internal registers of a
nexus such as a memory controller, MBA, UBA, or CI adapter. Each register
address space of each nexus occupies 8 Kbytes (16 pages each with 512
bytes) and contains the control and status registers of the UBA, registers
required for UNIBUS interrupt requests, and registers required for mapping the UNIBUS device transfers to SBI address space. The second space is
the UNIBUS address space associated with the UBA. It occupies a total of
256 Kbytes (512 pages each with 512 bytes). Figure 11-16 shows the assignments of the SBI I/O address space.

11-26' VAX Input/Output Subsystems

CONFGREG
STATUS REG
CONTROL REG
DIAG CONT. REG
FMER
FUBAR
BRRVRS
BRSVRS
DATA PATH REG'S
MAP REG'S

SBIMEMORY
ADDRESS SPACE
OTHER ADAPTER
REGISTERS
UBA INTERNAL
REGISTERS
SRI ADDRESS
/
SPACE CONTROLLED
RYTHEUBA

OTHER ADAPTER
REGISTERS

\
UNIBUS 1/0
ADDRESS SPACE AND
UNIBUS MEMORY ADDRESS
SPACE
OTHER
I/O ADDRESS
SPACE

000000
UNIBUSMEM
ADDRESS SPACE
757777(8)

760000(8)
UNIBUS 110
ADD!1.ESS SPACE
777777(8)

Figure 11-16' SBI I/O Address Space Assignments

• SBI-TO-UNIBUS TRANSFERS
UNIBUS address space consists of 248 Kbytes of physical memory space
and 8 Kbytes of device register space and is part of the SBI I/O address
space. The UBA translates SBI commands and address information into
UNIBUS commands and addresses and enables the so&ware to read and
write to UNIBUS device registers using word-type memory reference
instructions such as the MOVW or BITW instructions.

Device registers are assigned I/O addresses within the UNIBUS space from
760000 to 777777 (octal) or from 201XEOOO to 201XFFFF (hexadecimal).
The hexadecimal digit 3, 7, B, or F is substituted for the X value within the
physical address, depending upon which one of the four address spaces is
assigned to the UBA. During processor-initiated transfers, the SBI translates
the command into the follo\\[ing functions. The UBA becomes the highest
priority UNIBUS NPR device.

11-27

Transaction

Function

DATI

Read masked word or byte from device.

DATO or DATOB

Write masked word or byte to device.

DATIP then
DATO or DATOB

Interlock read-masked then interlocked write-masked.

• SBI-TO-UNIBUS ADDRESS AND FUNCTION TRANSLATION
Each SBI longword address is composed of two 16-bit UNIBUS word
addresses. In addition to decoding the SBI address, the SBI function and
byte mask is decoded to determine if a word or byte is to be accessed. This
translation of the SBI mask and function values into UNIBUS control values
is performed by the UNIBUS control and byte address encoder, as shown in
figure 11-17.

LONG WORD ADDRESS

UBA UNIBUS
ADDRESS DECODE

UNIBUS ADDRESS SPACE
UNIBUS ADDRESS SPACE 1
UNIBUS ADDRESS SPACE 2
UNIBUS ADDRESS SPACE 3
UNIBUS
CONTROL
AND
BYTE ADDRESS
ENCODER

UNIBUS
CONTROL
ADDRESS
17

2
UNIBUS ADDRESS BITS

17,02

C<H>

Figure 11-17· SBI-to-UNIBUS Control Address Translation

11-28' VAX Input/Output Subsystems

The SBI mask and function fields are translated into UNIBUS control and
address fields. TabJe 11-3 shows the UNIBUS control values translated from
the SBI function and mask values. Only the combinations shown on the
table are valid; other values will cause an error confirmation. The UNIBUS
address space will respond only to word or byte SBI references. Extended
transfers cannot occur to either the UNIBUS address space or to the
UNIBUS adapter registers.

TABLE 11-3' SBI-FunctioniMask-to-UNIBUS Translation
SBI

Function
<3:0>

UNIBUS

Mask
3,2 I 0

Control
C<I :0>

Address
UA<I:O>

Read Mask

0
0
0
0
I
I

0
I
I
0
0
0

I
I
0
0
0
0

DATI
DATI
DATI
DATI
DATI
DATI

0
0
0
I
I
I

Write Mask

0 0 0
0 0 I
0 I 0
I 0 0
0 0 I
I I 0

I
0
0
0
I
0

DATOB
DATOB
DATOB
DATOB
DATO
DATO

0 0
0 I
I 0
I I
0 0
I 0

Interlock Read Mask
(Sets Interlock
Flip Flop for
DATIP-DATO
Sequence)

0 0 0
0 0 I
0 I 0
I 0 0
0 0 I
I I 0

I
0
0
0
I
0

DATIP
DATIP
DATIP
DATIP
DATIP
DATIP

0 0
0 0
I 0
I 0
0 0
I 0

Interlock Write Mask

0 0
0 0
0 I
I 0
0 0
I I

I
0
0
0
I
0

DATOB
DATOB
DATOB
DATOB
DATO
DATO

0
0
I
I
0
I

0
0
0
I
I
0

0
I
0
0
I
0

0
0
0
0
0
0

0
I
0
I
0
0

When the software initiates a read or write transaction to a UNIBUS device
register, the UBA recognizes that the address is within the UNIBUS address
space and transfers the lower 16 SBI address bits through to the UNIBUS as
address bits A17:A2. The UBA generates UNIBUS address bits A1:AO and
control bits C1:CO by decoding the SBI mask and function bits. Table 11-4
shows the relationship of the UNIBUS space controlled by the UBA to the
SBI address space.

TABLE 11-4· UNIBUS and SBI Address Space

System
Address Space
(not to scale)

30 bit
Physical Byte Address
(Hex)

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Memory
Address
Space

Other
Adaptor
Registers
Unibus
Adaptor
Registers

20100002
20100006
2010oo0A
2010000E
20100002

Adaptor
Registers

110
Address Space

,,
,,

00000
00004
00008
OOOOC
00010

000002
000006
000012
000016
000022

000000
000004
000010
000014
000020

Unibus
Memory
Address
Space

2013DFF6
2013DFFA
2013DFFE

2013DFF4
2013DFF8
2013DFFC

3DFF6
3DFFA
3DFFE

3DFF4
3DFF8
3DFFC

757766
757772
757776

757764
757770
757774

2013E002
2013E006
2013EOOA

2013EOOO
2013E004
2013E008

3E002
3E006
3EOOA

3EOOO
3E004
3E008

760002
760006
760012

760000
760004
760010

Expansion
(496 pages)

1"page - 512 bytes
Unibus

110
Address

+. _'".
Space

2013EOI3

Other

00002
00006
ooOOA
OOOOE
00012

For

I
I

Unibus
110
Address Space

20100000
20100004
20100008
20lOoo0C
20100010

Reserved

Other

18 bit
Unibus Address Space
(Octal)

18 bit
Ur-ibus Address Space
(Hex)

2013EOf2

2013E011

2013EOI0

3E013

3E012

3E011

3EOI0

760023 760022

760021 760020

DATOB

Upp" 4 K (10)
16 bit words

Note: These addresses refer to UBAO.

2013FFF6
2013FFFA
2013FFFE

2013FFF4
2013FFF8
2013FFFC

3FFF6
3FFFA
3FFFE

3FFF4
3FFF8
3FFFC

777766
777772
777776

777764
777770
777774

.....
.....

11-30· VAX Input/Output Subsystems

During a read sequence to the UNIBUS address space, if data is received
from the device with a device parity error, then the data will be sent to the
SBI as a read data substitute. If an access is made to the UNIBUS address
space and the transfer is not completed on the UNIBUS because of a nonex·
istent device, the following events will occur:
• All zeros will be sent as data for a read transfer.
• UNIBUS address (bits A17:A2) will be stored in the failed UNIBUS
address register (FUBAR).
• The bit indicating the cause of the failure (UBA select timeout or slave
sync timeout) will be set in the UBA control/status register. During a
write transfer to the UNIBUS, the error bit is set after the command is
issued and acknowledged by the UBA .
• UNIBUS·TO·SBI ADDRESS TRANSLATION
UNIBUS·initiated transfers to UNIBUS device addresses are mapped by the
UBA·to·SBI addresses on a page·by·page basis. This allows data to be trans·
ferred to noncontiguous pages of SBI memory. The SBI uses a 3D·bit
address and a 32·bit data path, and the UNIBUS uses an 18·bit address and
a 16·bit data path. The SBI operates synchronously and supports as many
as 16 nexus nodes. The UNIBUS operates asynchronously and supports
many devices.
The UBA accepts hardware· generated interrupts and DMA data transfers
from the UNIBUS. The input transfer from a terminal is an interrupt pro·
cess in which the terminal interface initiates an interrupt sequence. The
interrupt service routine for the terminal driver will accept and process the
data that results from the terminal input sequence. Some terminal inter·
faces are designed for DMA transfers, with the interface controlling the
input DMA process. This process is an indirect memory transfer. Once the
process is initiated by the software, a disk drive can transfer data directly to
or from SBI memory through the UBA without processor intervention. The
DMA transfer may be a random access of noncontiguous addresses or a
sequential access of sequentially increasing addresses. The UNIBUS adapter
can channel data through anyone of 16 data paths for UNIBUS devices
performing DMA transfers. The UBA provides a direct data path to allow
UNIBUS transfers to random SBI addresses. Each UNIBUS transfer through
the dire~t data path is mapped directly to an SBI transfer, allowing the
transfer of only one word of information during an SBI cycle. The UBA
provides 15 buffered data paths, each of which allows a sequential access to
the memory locations from a device on the UNIBUS. Each path stores data
for the UNIBUS so that four UNIBUS transfers are performed for each SBI
transfer. The UBA can support high· speed, DMA block·transfer devices
through the buffered data paths and allows a UNIBUS device to operate on
random longword·aligned 32·bit data.

11-31

• UNIBUS-TO-SBI ADDRESS TRANSLATION
In the VAX-111780 series of processors, DMA transfers from the UBA to
main memory are through the memory controllers connected to the SBI. In
the VAX 8600 processor, the DMA transfers to memory are through the A
bus that connects to the Mbox and communicates with the memory. The
UBA translates UNIBUS memory addresses into SBI addresses and UNIBUS
memory page addresses into SBI page addresses through an address translation map containing 496 hardware map registers. Each map register is
assigned an SBI longword address, and each contains the SBI page address
and the data path required to transfer data between the UNIBUS and the
SBI.
The UBA is mapped to an SBI address in three sections: the SBI page
address, with one page equal to 512 bytes; the longword within an SBI
page, with one longword equaling four bytes; and the word or byte within a
longword. As shown in figure 11-18, the UNIBUS-to-SBI page map translates UNIBUS memory page addresses to SBI page addresses. The map
allows the transfer of data to noncontiguous pages of SBI memory and
translates the UNIBUS address (bits A17 :A9) to the SBI page address (bits
B27:B7).

CONTROL

ADDRESS

17
I

2 I

MAP REG NUMBER

BYTE WITHIN PAGE

MAP
REG
NUM

-I

UNIBUS TO SBI
ADDRESS
TRANSLATION
MAP

I
2
3
4
5

- SBI PAGE ADDRESS (PAGE FRAME
NUMBER)
(21 BITS)

H494
495

I
3

FUNC
MASK
ENCODE

~ 01 31 ~

I I I
MASK FUNC

SBI COMMAND ADDRESS

SBI PAGE ADDRESS (PFN)

LONG WORD ADD

Figure 11-18· UNIBUS-to-SBI Address Translation

11-32' VAX Input/Output Subsystems

The 496 map registers map the entire UNIBUS memory address space at
the same time, and each map register corresponds to the UNIBUS page that
is to be mapped. The map registers can be accessed by the software as part
of the SBI 110 address space. UNIBUS address bits A8:A2 select the
longword within a page and become SBI address bits B6:BO. These 7 bits
are concatenated with the mapped SBI page address to form the 28-bit SBI
address.
The two low-order UNIBUS address bits (AI:AO) and the two control bits
(CI and CO) determine the SBI function bits (FI and FO) and the byte mask
(M3:MO).
The mask field points to either one or two bytes within the longword
address. The function field selects either a read or write operation and
includes the associated qualifier. The translation values are listed in table

11-5.

TABLE 11-5' UNIBUS and SBI Field Translation Values
UNIBUS Field
Control

Address
Al AO

SBIField
Function

Mask
M3
M2

DATI

0
1

0
0

Read mask

0
I

0
1

1
0

DATO

0
1

0
0

Write mask

0
1

1
0

DATOB

0
0
I
I

0
1
0
I

Write mask

0
0
0
I

0
0
I
0

0
I
0
0

1
0
0
0

DATIP*

0
1

0
0

Interlocked
read mask

0
I

I
0

DATO

0
I

0
0

Interlocked
0
write mask I

0
I

I
0

DATOB

0
0
I
I

0
1
0
I

Interlocked
0
write mask 0
0
I

0
0
1
0

0
1
0
0

I
0
0
0

* DATIP is followed by a DATO or DATOB

11-33

• UBA DATA TRANSFER PATHS
Data is transferred between the UNIBUS and the SBI through the direct
data path and 15 buffered data paths of the UNIBUS adapter. The data path
to be used by a particular device is assigned by the software when the map
registers are defined. DPO is the direct data path and DPI through DP15 are
buffered data paths 1 through 15. One or more transferring devices can be
assigned to DPO; however, only one transferring device can be assigned to a
buffered data path at one time. During a DMA transfer, if the UNIBUS
address points to an invalid map register or to a map register that has a
parity error within the high-order 16 bits, the UNIBUS transfer will be
aborted and the bit indicating the condition will be set in the UBA control!
status register. For this implementation, the low-order 16 bits of the map
register are accessed only when an SBI transfer is required and only at that
time is parity checked on the low 16 bits of the map register.
The direct data path translates each UNIBUS data transaction directly into
an SBI function for each UNIBUS word or byte transfer, thereby transferring data between SBI memory and a UNIBUS device in 16-bit quantities.
The direct data path will respond to all UNIBUS data transactions. The
UNIBUS transfer is complete when the SBI transfer is completed. The SBI
address, function, and byte mask are mapped directly from the UNIBUS
address and control lines and from the state of an internal interlock during
a DATIP or DATO sequence. The direct data path is easy to program
be~ause only the map registers are accessed when initiating a UNIBUS
transfer. The DDP is used by devices executing an interlock sequence
(DATIP-DATOIDATOB) to the SBI, by devices transferring to consecutive
increasing addresses, or by devices that mix read and write functions. The
maximum data throughput rate is approximately 425 Kwords per second
for write operations and 316 Kwords per second for read operations; however, the rates will decrease when more than one transfer is in process
simultaneously. Table 11-6 lists the transfer operations that can be performed through the direct data path.

TABLE 11-6' Direct Data Path Transfer Functions
UNIBUS
Function

Transfer
Direction

SBI Function

DATI

UBA to device

Read mask (16 bits)

DATO or DATOB

Device to UBA

Write mask (8 or 16
bits)

DATIP and DATO or
DATOB

UBA to device,
then device to DBA
write-mask

Interlock read-mask
then interlock

11-34' VAX Input/Output Subsystems

The buffered data paths enable the fast and sequential block transfers
between physical memory and the UNIBUS devices through the SBI. Each
of the 15 buffered data paths stores the data from a device as words or
bytes and then transfers 64 bits to SBI memory, except for the VAX 8600
processor, which does not use the SBI memory. During output transfers,
one quadword from memory is stored and then transferred to the device as
a word or byte. The buffered data paths will respond to all UNIBUS data
transactions except the DATIP function. These data paths also allow a
UNIBUS device to operate on random 32-bit longword-aligned data and
enable word-aligned block transfer devices to begin and end on an odd
byte of SBI memory. A UNIBUS device can operate on random longwordaligned 32-bit data from SBI memory so that all 32 bits of the longword are
read or written at the same time. The buffered data path is selected by
software when the map registers are formatted. Only one active transfer is
assigned to the data path at one time.
A block is greater than or equal to one byte, and transfers within a block
must be to consecutive increasing addresses. All transfers within a block
must be of the same function type, such as a memory read (DATI) or a
memory write (DATa or DATOB) .
• DATA TRANSFERS TO MEMORY
After the device addresses the last byte or word of a physical quadword,
the UBA completes the data cycle and performs an extended write operation to transfer the stored bytes of data. The SBI transfer is completed
before additional transfers can be performed. The controVstatus register
indicates to the program whether valid data is contained in the buffer. The
format of the information in a buffer data path is shown in figure 11-19.
Four 16-bit data words are transferred. The last transfer initiates an
extended write transfer of all 64 bits to memory. The buffer stores the
UNIBUS addresses of the data it contains so that the remaining bytes can be
transferred to memory at the end of a block transfer. The buffer also
records the type of function and the state of each stored byte in the data
buffer. This information is transmitted as the SBI mask bits during write
cycle to allow only the correct bytes to be written into memory.

11-35
BDPBYTES
UNIBUS TRANSFERS
DATA TO ADDRESS
(HEX)

DATOXXXXO
16 BITS

DATOXXXX2
16 BITS

DATOXXXX4
16 BITS

BNESTATE

WO~DO
WO~DO

WO~D1
WO~D1

EMPTY

WOlD 2
WORD 0

SBI EXTENDED WRITE
TO MAPPED UNIBUS
ADDRESS (MEMORY)

DATOXXXX6
16 BITS

')
0

DATO'XXXX8
16 ~ITS

DATOXXXXA
16 BITS

DATOXXXXC
16 BITS

WO~D5
WO~D5

64 BITS

EMPTY

WO~D4
WO~D4
wot6
WORD 4

DATOXXXXE
16 BITS

EMPTY

SBI EXTENDED WRITE
TO MAPPED UNIBUS
ADDRESS (MEMORY)

0
1

Figure 11-19· UNIBUS Data Transfers to Memory

64 BITS

11-36· VAX Input/Output Subsystems

• DATA TRANSFERS FROM MEMORY
During data transfers to memory, the UBA logic monitors the state of the
data buffers. If the buffers are empty, an extend read operation to memory
will be initiated. The data for the current cycle will be transferred and the
cycle completed, the remaining bytes will be stored in the buffers, and the
"buffer not empty" condition will be indicated. If the data for the current
cycle is available in the data buffers, then the buffer will pass the data to the
UNIBUS and complete the cycle. The buffer prefetches the next quadword
of data using an extended read transfer after each UNIBUS access to the last
word of a quadword-aligned group. The "buffer not empty" condition is
cleared before the prefetch action and set when the data is read. Since the
prefetch action would allow a page boundary to be crossed into nonexistent memory, a timeout condition could occur. This is prevented by the
software allocation of an additional map register following a block. The
map register therefore must be invalidated. When a page boundary is
crossed to the invalid map register, the prefetch will be aborted before a
timeout occurs. The UBA does not record any UBA or SBI errors that occur
during the prefetch operations. If an error occurs, the prefetch will be
aborted and the buffer will remain empty. If the same buffer is again
accessed by the device, then the read operation will be initiated and any
errors that occur will be logged. Figure 11-20 shows the buffered data path
transfer from memory to the UNIBUS.
Devices that begin transfers on word boundaries and transfer an integral
number of words can begin and end a block transfer at an odd byte of SBI
memory. The byte offset bit of the map registers must be set by software
during the devices transfer. This effectively increases the SBI memory
address by one byte. The data on the UNIBUS is the byte or word indicated
by the UNIBUS address. The data on the SBI is increased by one byte. The
UBA will distribute the data and adjust the SBI address and byte mask so
that the data will be transferred to the correct memory location. The device
does not intervene in this process. Figure 11-21 shows the relative position
of data transferred between a device and SBI memory.

11-37
BNE
DATI
ADDRESS XXXXO

731
.

26 1
.

51
1.

WO~D 1

;~DO

41.
SBI
.
READ

BIT
(EMPTY)

L--W---'OU.t-D-3--'"IL---W---!.o.Lt-D-2----..!!I°I)~

DATILXXXX0---J:

DATA

WORD 0

~____W_O_t~D__3 __~~___W_O~t~D__2 __-4

DATI

WO~D 1

XXXX2" - - - - -

WO~D 0

WORD~I-J==~W~O~R~D~2~---L----~~~--~

~~i:X4~1---:-:+~-:-:--+-==-=---:-:-+r-D-:---I
WORD 3

~ ~----~----~----~----4

~~~X6

1
.

WOrD 3
WORD 1

WO
2
WORD 0

LAST DATA WORD
TRANSFER CAUSES
NEW SBI READ

.. SBI
READ

~~~X8~L---:-:~~-D-:--~---~---JI~

BNE
WORD 7

DATI
XXXXA

WORDS

~~~X~~--:-:+~-D-:--~--:-:~~-:-:---I
DATI--XXXXE

WORDS

WOlD 6
WORD 4
SBI

~----+------r----~------~-READ

(PREFETCH)

Figure 11-20' UNlBUS Data Transfers from Memory

BIT

11-38· VAX Input/Output Subsystems
UNIBUS
ADDRESS
SPACE

SBIMEM
ADDRESS
SPACE

k
i

:-1,--B_~_~~_~_O-,~

10
C

WITHOUT BYTE OFFSET

k
i

:-1L_B_~_~~_~_l-,~

SB! ADD ~ UNIBUS
ADD

1 BYTE

10
n

WITH BYTE OFFSET

Note: Each box represents one byte of data.
Figure 11-21 • Relative Position 0/ UNIBUS and SBI Data

The buffered data paths are cleared of information and the registers are
initialized by the software at the completion of a device transfer to memory. Bytes of data that remain in the buffer will be transferred to memory.
The UBA will then indicate that the buffer is empty. If an error occurs
during this transfer, the error will be indicated in the data path register
indicating an unsuccessful transfer. The software must clear this bit before
the buffer is again available for transfer. If no data remains in the buffer at
the end of the operation, then the buffer is left in its initialized state. During read operations from memory the UBA initializes the buffers by indicating that the buffers are full.

11-39

• LONGWORD-ALIGNED 32-BIT RANDOM ACCESS MODE
Data can be transferred between a device and memory using longwordaligned 32-bit quantities in a random access mode. A buffered data path
selected by the map register is used for this mode. A UNIBUS device first
transfers the low-order word of the longword, then the high-order word.
This is performed with a read from memory (DATI), write to memory
(DATO), or a read/write (DATI/DATO) operation. The UBA operation for
this mode is determined by the transaction and address received from
the UNIBUS and the state of the buffer. The DATIP function code is not
valid for these transfers. No prefetch operation will be performed when
this mode is enabled. The initialization operation at the completion of
the transfer is not performed when the device transfers both words of
the longword in the specified order. Maximum throughput in this
mode is approximately 1.7 Mbytes per second in the sequence shown
in figure 11-22.

FIRST WORD TO BDP

SECOND WORD TO BDP TO SBI

1 - - - 800 ns ------<~.----- 2.6 US MIN. - - - - - 1
REC
MSYN

REC
MSYN

3.4 US MIN. PER WORD (4 BYTES) ~ 1.17 MBYTE/SEC. MAX.

Figure 11-22 • Random Access Mode Throughput

The SBI read operations will occur when a DATI operation is received and
the buffered data path is empty. If the buffer contains data, the data will be
returned to the device. The "buffer not empty" condition will be reported
at the completion of a transfer of the low-order word and cleared after the
high-order word is transferred.
The "buffer not empty" condition is indicated during a DATO or DATOB
operation. The data from the device is stored in the buffer and the byte
mask bit is set within the data path register to indicate the bytes or words
that have been written by the device. The DATO operation is performed on
the high-order word or when a DATOB operation occurs to the high-order
byte. The bytes or words that have the byte mask bits set are written into
main memory. The "buffer not empty" bit is cleared after a SBI write
operation.
Table 11-7 lists the UBA operations for each UNIBUS transaction.

11-40· VAX Input/Output Subsystems

TABLE 11·7" UBA Operations for UNIBUS Transactions
UNIBUS
Transaction

Address
Al
AO

DATI

X
X

DATO

DATOB

DATIP

0
1

X
X

0
1

X
X

0
1

X
X

0
0

1
0
0
1
1

0
1
0
1
0
1

UBA Operation

BNEState
Before
After

SBI read, return low
word, store data
SBI read, return high
word
Return low word
Return high word

1
1

1
0

Store low word
Store high word, SBI
write
Store low word
Store high word, SBI
write

0
0

1
0

Store byte 0
Store byte 1
Store byte 2
Store byte 3, SBI write
Store byte 0
Store byte 1
Store byte 2
Store byte 3, SBI write
UBA does not respond
(nonexistent memory
to UNIBUS device); no
change
UBA does not respond
(nonexistent memory
to UNIBUS device); no
change

0
0
0
0
1
1
1
1
0

1
1
1
0
1
1
1
0
0

1
0

11-41

Figure 11-23 shows the map registerbit assignments required to program
the UBA for the longword-aligned random access mode.

8 7

16 IS

I, , I

DESIG
LNGWD ACCES ENB
BYTE.oFFSET
MAP REG VALID

Figure 11-23 • Longword-aligned Map Register Format

Bit

Function.

MAP REG VALID (Map register valid) - Set to indicate that the map
register information is valid.

30:27

MBZ (Must be zero).

LNGWD ACCES ENB (Longword access enable) - Set to initiate the
longword-aligned random access operation.

BYTE OFFSET -Cleared to indicate that the byte is not offset.

24:21

DATA PATH DESIG (Data path designators) - A binary value used
to select the buffered data path, as indicated:
o = direct data path
1-15 = buffered data paths 1 through 15

20:0

PAGE FRAME NO (Page frame number) - SBI page address.

• INTERRUPT REQUESTS
The SBI interrupts requests are initiated from the UNIBUS subsystem by a
device or by the UBA on one of the four UNIBUS bus request (BR) lines.
The UBA level is selected by a backplane jumper lead. The UBA contains
one request sublevel and requires 4 of the 64 possible SBI interrupt vectors,
one for each of the four required levels. Each of the four vectors selects a
UBA service routine corresponding to an interrupt request level. Each UBA
service routine reads and tests the BR receive vector register (BRRVR 7-4)
that corresponds to the level of interrupt (7-4). The UBA service routine
determines whether the interrupt was generated from within the UBA status register, from the UNIBUS device, or from both. The UBA service routine services the interrupt as specified by the contents of the BRRVR. Figure
11-24 shows the bit assignments of each register.

11-42· VAX Input/Output Subsystems
8 7

2423

31 30

,1,

I [" , I,

y
VECTFLD

LSERVREQ
Figure 11-24· BR Receive Vector Register Format

Bit

Function

SERV REQ (Service required) - Together with the vector value (bits
15-0), specifies the type of service that is required, as follows:

Bit
31

Bits
15-0

o
o

Operation
No service required.
UNIBUS service as indicated by vector (V)
routine.
UBA service as specified by the configuration and
status register.
UBA and UNIBUS service required. Save the
vector, perform the service as specified by the
configuration and status registers, and perform
the routine as defined by the vector.

30: 16 MBZ (Must be zero).
15:0

VECT FLD (Vector fidd) - Specifies a vector fidd or a null

vector (0) ..

The UBA translates the UNIBUS interrupts to UBA interrupts, and the
assertion of an SBI request line will initiate the interrupt transaction as
specified by the vector address. The UBA checks to validate that the BR line
corresponding to the BRRVR value is asserted, and that the BRRVR does
not contam a previous vector. The UBA will then issue the UNIBUS bus
grant and complete the UNIBUS interrupt transaction. The BRRVR is
loaded with the interrupt vector at the successful completion of the interrupt transaction.
The device vector received during the transaction is transferred to the
BRRVR by a read command. If a UBA interrupt is active, the vector is a
negative quantity. The BRRVR is cleared by the successful completion of the
SBI read data cycle or the vector is saved and the BRRVR remains full.

11-43

If the BRRVR value and the BR line do not correspond or the BRRVR contains a previous valid vector, then the contents of the BRRVR (either the
stored vector from a previously failing SBI read data cycle or zero) are
transferred by the read data operation. If a UBA interrupt is active, then the
vector is sent as a negative value. The UNIBUS device interrupt sequence is
performed in the following order.
1. A bus request line is asserted by the UNIBUS device.

2. The UBA asserts the SBI request line corresponding to the UNIBUS BR
line, to initiate the interrupt transaction in the cPU.
3. When the interrupt summary read command that corresponds to the
request level is detected by the UBA, the UBA asserts the request sublevel assigned to the UBA.
4. The cPU will transfer control to the UBA interrupt service routine.
5. The UNIBUS interrupt service routine executes a read to the BRRVR
corresponding to the level of interrupt.
6. The UNIBUS adapter issues the UNIBUS bus grant (BG) corresponding
to the level of the interrupt being serviced, providing the UBA interrupt
is not pending; the BR line corresponding to the BRRVR is asserted; and
the BRRVR does not contain a previous vector.
7. The UNIBUS interrupt transaction is then completed, the vector is
loaded into the corresponding BRRVR and sent to the UNIBUS interrupt
service routine by a read data operation, and the BRRVR is cleared when
the confirmation is received.
8. The UNIBUS interrupt service routine will then transfer to the UNIBUS
device service routine or service the UBA as indicated by the received
interrupt vector.

If a device initiates but fails to complete an interrupt transaction, the interrupt vector will not be transferred into the interrupt vector register. When
reading the interrupt vector tegister, the UNIBUS interrupt service routine receives a zero vector, which is the idle state of the BRRVR, and causes
an error condition if desired. This terminates the service routine.
When the BRRVR is successfully loaded, it maintains the interrupt vector
until a confirmation to the BRRVR read data sequence has been received or
a UBA initialize sequence occurs. If the confirmation is not received, subsequent reads to the BRRVR result in the stored vector being returned for the
data read.
When the UBA initiates an interrupt, it asserts the request line, resulting in
an interrupt-summary read operation. The request sublevel assigned to the
UBA is sent to the cPU as an interrupt summary response. Using the level
and request sublevel, the cPU can dispatch the service rOjltine, which reads
the BRRVR corresponding to the level of interrupt. The BRRVR will contain

11-44· VAX Input/Output Subsystems

a negative value, and the service routine detects the value and branches to a
routine that reads the configuration register and status register to determine the service requited. The request line remains asserted until the bits
of the UBA status register are cleared by the software.
• DBA REGISTER ASSIGNMENTS
The UBA registers occupy 16 pages (512 bytes per page) of SBI address
space. The address location of the UBA is determined by the transfer
request priority number assigned to the adapter. The transfer request number is selected by the position of jumper leads on the backplane. Table 11-8
lists the physical base address and SBI base address for a nexus assigned to
anyone of the SBI transfer request numbers. The VAX 8600 processor
includes the SBIA 0 adapter; the SBIA 1 adapter is optional.

TABLE 11-8· Transfer Number Address Assignments
SBI Request
TR level

Physical Base Address (hexadecimal)
First SBI (SBIA 0)
Second (SBIA 1)

1
2
3
4
5
6

20002000
20004000
20006000
20008000
2000AOOO
2000COOO
2000EooO
20010000
20012000
20014000
20016000
20018000
2001AOOO
2001COOO
200lEOOO

8
9

10
11

12
13

14
15

22002000
22004000
22006000
22008000
2200AOOO
2200COOO
2200EOOO
22001000
22012000
22014000
22026000
22018000
2201AOOO
2201COOO
220lEOOO

Table 11-9 lists each of the UBA registers and its associated physical
address offset. The base address of the configuration register is the physical
base address listed in table 11-8.

11-45

TABLE 11·9' UBA Register Address Offset
UBA Register

Byte Offset (hexadecimal)

Configuration
Control
Status
Diagnostic Control
Failed Map Entry
Failed UNIBUS Address
Failed Map Entry
Failed UNIBUS Address
Buffer Selection Verification 0
Buffer Selection Verification 1
Buffer Selection Verification 2
Buffer Selection Verification 3
Buffer Receive Vector 4
Buffer Receive Vector 5
Buffer Receive Vector 6
Buffer Receive Vector 7
Data Path 0
Data Path 1-14
Data Path Register 15
Reserved
Map 0
Map 1-494
Map 495
Reserved

000
004
008
OOC
010
014
018
01C
020
024
028
02C
030
034
038
03C
040
044-078
07C
080-7EC
800
804-EB8
EBC
ECO-EFC

• SBI ADDRESSABLE UBA REGISTERS
The UBA registers occupy eight pages of the SBI I/O address space. These
registers are map registers, data path registers, interrupt vector registers,
and control and status registers. The UBA registers are 32-bit registers and
can be written only as longwords; however, they will respond to byte or
word read commands. They also respond to the interlock-read/interlockwrite sequence but will not affect the interlock of the SBI.

Configuration Register- The configuration register (CNFGR) contains
the SBI fault bits, the UBA and UNIBUS environment status bits, and the
UBA code. This register interfaces with the SBI. Figure 11-25 shows the
format of the information in the register.

11-46" VAX Input/Output Subsystems

262S 24 23·22 21

SBI~LTS

tu
-.J

MB~.

MBZ

lIBA PWR ON
UBA PWR UP

19 18 17 16 IS

uutL-

Rtvn

UBACOOE

UB INIT CMPL
lIB PWR ON
UB INIT AS.SRT

Figure 11-25" Configuration Register Format

Bit

Function

31:26

SBI FLTS (SBI faults)- These bits are set when the UBA detects
fault conditions on the SBI. The bits assignments are as follows.
When bits 31 :26 are set, the UNIBUS adapter asserts the fault signal on the SBI.
Bit 31 (Parity fault) - Set when the UBA detects an SBI parity error.
Bit 30 (Write-sequence fault) - Set when the UBA receives a writemasked, extended-write-masked, or an interlock-write-masked
command that is not immediately followed by the expected data.
Bit 29 (Unexpected read-data fault) - Set when the UBA receives
data for which a read-masked, extended-read, or interlock-readmasked command has not been issued.
Bit 28 (Interlock sequence fault) - Set when an interlock-writemasked command or a UNIBUS address space is received by the
UBA without a previous interlock-read-masked command.
Bit 27 (Multiple-transmitter fault) - Set when the IB bits transmitted by the UBA to the SBI are not the same as those received from
the SBI.
Bit 26 (Transmit fault) - Set if the UBA was the transmitter during a
detected fault condition.

25:24

MBZ (Must be zero).

UBA PWR DOWN (Adapter powerdown) - Set when the ac voltage
of the UBA power supply is below the specified value; cleared
by writing a one to the bit location or when the adapter powerup
(bit 22) is set.

UBA PWR UP (Adapter powerup) - Set when the ac voltage of the
UBA power supply is normal; cleared by writing a one to the bit
location or by setting the adapter powerdown (bit 23).

21:19

MBZ (Must be zero).

11-47

Bit

Function

UB INIT ASSRT (UNIBUS initialize asserted) - Set by the assertion
of the UNIBUS INIT signal; cleared when the UNIBUS initialization
complete (bit 16) is set or by writing a one to this bit location.

UB PWR DOWN (UNIBUS powerdown) - Set when UNIBUS AC LO
signal is asserted and indicates that the UNIBUS has initiated a
power down sequence. Cleared when the UNIBUS initialization
complete (bit 16) is set or by writing a one to this location.

UB INIT CMPL (UNIBUS initialization complete) - Set by a successful completion of a powerup sequence on the UNIBUS.

15:8

RSVD (reserved).

7:0

UBA CODE- These bits define the code assigned to the UBA as follows: Bits 1 and 0 are determined by backplane jumpers and indicate the starting address of the UNIBUS address space associated
with the UBA, and the value of 001010 is in bits 7 through o.
Bits

Address Space (hexadecimal)
UNIBUS Starting

o1
o0
o1

0
1
2

1 0
1 1

20100000
20140000
20180000
201COOOO

UBA Control Register- The UNIBUS adapter control register (UACR)
enables the software to control operations on both the UNIBUS adapter
and the UNIBUS. All bits except the adapter initialize (bit 0) are set by
writing a one and cleared by writing a zero to the bit location. Bit 0 is set
by writing a one to the bit location. Figure 11-26 shows the bit format of
theUACR.

26 25 24 23

MBZ

I,I,

,
MA#REG
DSABL

16 15

876543210

, I "1,,,111111111

JJU~~~~

REQ
INT ENB
INTUB
FLD
SWTCH
UB TO SBI ERR FLD INT ENB
SBI TO UB ERR FLD INT ENB
CNFG INT ENB
UB PWR FAIL
UBAINIT

Figure 11-26· Control Register Format

11-48· VAX Input/Output Subsystems

Bit

Function

MBZ (Must be zero).

30:26 MAP REG DSABL (Map register disable) - Five read/write bits that
disable map registers in groups of 16 according to the binary value
contained in the field. The disable bits prevent the double addressing of UNIBUS memory. DMA transfers to addresses controlled by
disabled map registers are not recognized by the UBA, and no error
bits are set and no transfers are initiated. The SBI, however, has
access to disabled map registers. This field is initialized to zero and
all map registers are enabled.

Bit
30

0
0
0
0
1
1

Bit
29

Bit
28

Bit
27

Bit
26

UNIBUS Memory
Kwords

0
0
0
0
0
1
4
0
0
0
1
0
8
0
0
1
1
12
0
0
(sequence continues to:)
1
1
1
0
120
1
1
1
1
124

Map Register
Disabled
none
0-15
0-31
0-47

0-480
0-495

25:7

MBZ (Must be zero).

INT FLD SWTCH (Interrupt field switch) - Set to pass an int~rrupt
from a device to the SBI, provided the BR interrupt enable (bit 5) is
set. When cleared the interrupt is ignored.

UB REQ INT ENB (UNIBUS request interrupt enable) - Set by software to allow the UBA to pass interrupts from the UNIBUS to the
CPU. This bit and bit 6 must be set to receive device interrupts.

UB TO SBI ERR FLD INT ENB (UNIBUS to SBI error field interrupt
enable) - Set to enable an interrupt request to the CPU when any of
the UNIBUS status register (UASR) bits (bits 10:9 or bits 7:3) are set
during a DMA transfer.

SBI TO UB ERR FLD INT ENB (SBI to UNIBUS error field interrupt
enable) - Set to allow the UBA to generate interrupt requests when
one of the two UNIBUS timeout bits (0 or 1) is set in the UNIBUS
status register (UASR).

CNFG INT ENB (Configuration interrupt enable) - Set at powerup
and by program to allow the UBA to generate an interrupt request
to the CPU when anyone of the environmental status bits (bits
23:22 or bits 18:16) of the configuration register are set.

11-49

Bit

Function

UB PWR FAIL (UNIBUS powerfail) - Set to initiate a powerfail
sequence on the UNIBUS; used by the software to initialize the
UNIBUS. The UNIBUS remains powered down until this bit is
cleared.

UBA INIT (UBA initialize) - Set to initialize the UBA and UNIBUS.
The map registers, data path registers, status register, and control
register will be cleared. The control logic will also be initialized and
a powerfail sequence will occur on the UNIBUS. Only the configuration register and the diagnostic control register can be read from
and only the configuration register, the diagnostic control register,
and the control register can be written to during the adapter initialization sequence.

UBA Status Register- The UNIBUS adapter status register (UASR) is a
read-only register that contains program status and error information
used by the program during UNIBUS 110 operations. Figure 11-27 shows
the register format. The register bits are defined as follows:

16 15
!

MBZ

BRRVR STAT

11 10 9 8 7 6 5 4 3 2 1 0

I 111111111111

M~ZRDDATATMO:JUUU~~~

RDDATA SUB
CORRRDDATA
COMD XMIT ERR
CMDXMITTMO
DATA PATH PAR ERR
INVLD MAP REG
MAP REG PAR FAIL
LOST ERR
UBSEL TMO
UB SLAVE SYNC TMO

Figure 11-27· UBA Status Register Format

11-50· VAX Input/Output Subsystems

Bit

Function

31:28

MBZ (Must be zero).

27 :24

BRRVR STAT (Buffer receive vector register status) - Indicates the
status of the four SBI addressable buffer receive vector registers
(BRRVR). Each bit is set when the interrupt vector is loaded into
the corresponding BRRVR during a UNIBUS interrupt transaction,
providing that the SBI processor is acknowledging device interrupts. Cleared by the successful completion of a read data transmission following a read BRRVR command. The bit positions are
assigned as follows:
Bit 27 = BRRVR 7 full
Bit 26 = BRRVR 6 full
Bit 25 = BRRVR 5 full
Bit 24 = BRRVR 4 full

23:11

MBZ (Must be zero).

READ DATA TMO (Read date timeout) - Set by the UBA when a
device has initiated a DMA read transfer, after the following events
have occurred: the UBA has successfully transmitted a read command to the SBI, the SBI memory has not returned the requested
data within the specified interval, and the device has not timed out.

READ DATE SUB (Read data substitute) - Set if a read data substitute is received in response to a UNIBUS-to-SBI DMA read transfer.
No data will be sent to the device, a device timeout occurs, and the
nonexistent memory bit will be set in the device.

CORR READ DATA (Corrected read data) - Set by the UBA when it
receives corrected read data in response to an SBI read command
during a DMA read transfer.

COMD XMIT ERR (Command transmit error) -Set by the UBA
when it receives an error confirmation in response to an SBI command transmission during a DMA transfer.

COMD XMIT TMO (Command transmit timeout) - Set when no
response is received from a command for a UNIBUS-to-SBI data
transfer, for a buffered-data-path-to-SBI write operation, or for a
purge operation.

DATA PATH PAR ERR (Data path parity error) - Set when a parity
error occurs in the buffered data path during either a DATI transfer
from the UNIBUS to the buffered data path, a buffered-data-pathto-SBI write operation or during the purge operation.

11·51

Bit

Function

INVLD MAP REG (Invalid map register) - Set by the UBA during a
DMA transfer or clear-and-initialize operation when the UNmus
address points to a map register that has not been validated by the
software or when the DMA transfer crosses an SBI page boundary
for which the map register has not been validated.

MAP REG PAR FAIL (Map register parity failure) - Set when a
UNIBUS address is being mapped to an SBI address on a DMA
transfer operation or during a purge operation.

LOST ERR (Lost error) - Set by the UBA if the locking error field is
locked and another error within this field occurs. The lost error bit
does not initiate an interrupt request.
UB SEL TMO (UNIBUS select timeout) - Set by the UBA if it cannot
gain access to the UNmus within 50 microseconds during the execution of a software-initiated SBI-to-UNIBUS transfer. This condition indicates the presence of a hardware failure on the UNIBUS.

UB SLAVE SYN TMO (UNmUS slave synch timeout) - Set when a
response is not received for SBI-to-UNmus software-initiated
transfer during the data transfer cycle on the UNIBUS. This condition indicates a transfer failure when a nonexistent memory or
device on the UNIBUS is addressed.

Diagnostic Control Register- The diagnostic control register (DCR) is a
read-write register that provides control and status information to aid in
testing and diagnosing the UBA during maintenance functions. Figure
11 -28 shows the bit format of the DCR.

31 30 29 28 27 26

24 23

111111"1,,,\

~~UUL:::SEQOK

8 7

16 15

I ,

SAME JCNFGR

DEFT DATA PATH PAR
DEFT MAP PAR
DISBLINT
NOT USED

Figure 11 -28· Diagnostic Control Register Format

11-52' VAX Input/Output Subsystems

Bit

Function

Not used.

DISBL INT (Disable interrupt) - Set to prevent the UBA from recognizing interrupts on the UNIBUS. Used for testing the response
of the UBA to the passive release condition during a UNIBUS interrupt transaction. Set by writing a one and cleared by writing a zero
to the bit location.

DEFEAT MAP PAR (Defeat map parity) - A read-write bit set to
prevent the parity bits of the map registers from entering the mapregister parity checkers. The map register parity generator checkers
generate and check parity on 8-bit quantities. Each parity field is 8
data bits and 1 parity bit and the total number of ones in the parity
field is always an odd number.

DEFEAT DATA PATH PAR (Defeat data path parity) - Set to inhibit
the parity bits of the data path RAM from entering the parity
checkers. The data path parity generator checkers generate and
check parity on 8-bit data units. The total number of ones in the
parity field is always an odd number. When the integrity of the parity generator checkers is to be tested, the total number of ones in at
least one of the bytes of data must be even. With the parity bit disabled, a data path parity failure will result during a DMA transfer
via that buffered data path.

MICRO SEQ OK (Microsequencer OK) - A read-only bit that indicates that the UBA microsequencer is in the idle state after it has
completed the initialization sequence or once it has completed a
UBA function. This bit can be used by diagnostics to determine
whether the microsequencer has completed a successful powerup
sequence or remains in a loop.

26:24

MBZ (Must be zero).

23:0

SAME AS CNFGR - Same function as bits 23:0 of the configuration
register shown in figure 11-25.

Failed Map Entry Register- The failed map entry register (FMER) is a readonly register that contains the map register number used for either a DMA
transfer or a purge operation that has resulted in the setting of one of the
following error bits of the status register: INVLD MAP REG, MAP REG PAR,
DATA PATII PAR ERR, COMM XMIT ERR, COMM XMIT ERR, RD DATA SUB,
and RD DATA TMO. This register is locked and unlocked by the UNIBUS-to-

11-53

SBI data transfer error field of the UASR. The contents are valid only when
the register is loaded. The software can read this register to obtain the map
register number associated with the failure and to read the contents of the
map register to determine the number of the data path that failed. Figure
11-29 shows the format of the information in the register.

2423

16 15

I
¥

J. I

MBZ

I I I

MAP REG NO

Figure 11-29 • Failed-Map-Entry Register Format

Bit

Function

31:9

MBZ (Must be zero).

8:0

MAP REG NO (Map register number) - These bits contain the

number of the map register in use at the time of a failure. They correspond to bits 17:9 of the UNIBUS address.

Failed UNiBUS Address Register- The failed UNIBUS address register
(FUBAR) is a read-only register that contains the upper 16 bits of the
UNIBUS address translated from an SBI address during a previous software-initiated data transfer. The UB SEL TMO and UB SLAVE SYNC
TMO errors of the UNIBUS status register will lock this register. When the
error bit is cleared, the register will be unlocked. Figure 11-30 shows
the bit format of the register.

2423

.., I

I
¥

MBZ

8 7

16 15

,,,,"

I I I I

FAIL UB TO SB! ADDR

Figure 11-30' Failed-UNiBUS-Address Register Format
i·
I

11-54' VAX Input/Output Subsystems

Bit

Function

31:16

MBZ (Must be zero) ..

15:0

FAIL UB TO SBI ADDR (Failed UNIBUS to SBI address) - These bits
correspond to UNIBUS address bits A17:A2

Buffer Selection Verification Registers- The buffer selection verification
registers (BRSVR) are four read-write registers tha( provide the diagnostic
software access for testing the integrity of the data path RAM. Four locations in the data path RAM have been assigned to these registers. Writing
and reading the BRSVR has no effect on the UBA. The BRSVR bit configuration is shown in figure 11-31.

I..

8 7

16 15

2423
I

f ..

MBZ

[

0
I

READ/WRITE

Figure 11-31 • Buffer-Selection-Verification Register Format

Bit

Function

31:16

STZ (Set to zero).

15:0

TEST DATA - Read/write test data.

BR Receive Vector Registers- The BR receive vector registers (BRRVR) are
four read-only registers, BRRVR 7 through BRRVR 4. They correspond to
UNIBUS-interrupt bus request levels 7 through 4 respectively. Each BRRVR
is a read -only register and contains the interrupt vector of a UNIBUS device
interrupting at the corresponding BR level. The BRRVR is read by the software during the UBA interrupt service routine. The contents of the BRRVR
are used by the software to detennine if a UBA interrupt is pending. Figure
11-32 shows the format of the register.

11-55
24 23

I.,

16 H

DEV INT VEeT FlO

MBZ
LUBAINTREQ

Figure 11-32· BR Receive Vector Register Format

Bit

Function

UBA INT REQ (Adapter interrupt request indicator) - Set to indicate a UBA interrupt is pending.

30:16

MBZ (Must be zero).

15:0

DEV INT VECT FLD (Device interrupt vector field) - Contains the
device interrupt vector loaded by the UBA during a UNIBUS interrupt transaction.

Data Path Registers- The UBA contains 16 data path registers (DPRO
through DPR15), which are used to transfer the information through the
UBA. Each register corresponds to one of the 16 data paths. The DPRs are
32-bit read-write registers and the bit assignment of the register information is shown in figure 11-33.

31 30 29 28

24 23

8 7
I

t"
L

NOT tSED { '

BUF trATE

BUF UB""ADDRS

DATA PATH FUNC
BUF XFERERR
BUF NOT EMPTY

Figure 11-33 • Data Path Register Format

11-56· VAX Input/Output Subsystems

Bit

Function

BUF NOT EMPTY (Buffer not empty) - Set to indicate the buffer
status, as follows:

o = buffer is empty or does not contain valid data
1 = buffer contains valid data bit
30

BUF XFER ERR (Buffer transfer error) - Set by the UBA to indicate
that a failure has occurred during a DMA write transfer or during
a purge operation. Also set when a data path parity failure has
occurred during a DMA read transfer. Any additional DMA transfers through this buffer will be aborted until the bit is cleared by
the software. If a UNIBUS parity error occurs during a DMA read
transfer, the UNIBUS PB signal line will be asserted to enable the
device to abort the transfer. The purge operation does not clear
this bit.

DATA PATH FUNC (Data path function) - A read-only bit that indicates the function of the DMA transfer as follows:
0= DMAread
1 = DMAwrite

28:24

Not used.

23:16

BUF STATE (Buffer state)-Used by the diagnostic program and
indicate the state of each of the eight buffers of the associated data
path during a DMA write transfer. The UBA generates the SBI mask
bits from these bits during a DMA write transfer or purge operation. The bits are set as each byte is written from the UNIBUS and
cleared during the SBI write operation. They specify the following:

o = buffer empty
1 = buffer full
15:0

BUF UB ADDR (Buffered UNIBUS address) - If the transfer is in the
byte offset mode and the last UNIBUS transfer has entered into the
next quadword, these bits contain the upper 16 bits of the UNIBUS
address (A17 :A2) asserted during the DMA transfer through the
data path. This is the UNIBUS address from which the SBI address
will be mapped if a purge operation occurs before the next
UNIBUS transfer.

11-57

Map Registers- The UBA contains 496 read-write map registers (MRO
through MR495), one for each UNIBUS memory page address. The register
assignments for each offset are as follows:

The upper nine address bits (A17 :A9), asserted by the device during a DMA
transfer, select the map register that was set up by the software. The map
register tests the validity of the current UNIBUS transfer, selects one of the
16 data paths for the transfer, determines if the transfer will occur in the
byte-offset mode, and maps the UNIBUS page address to an SBI page
address. Figure 11-34 shows the map register bit configuration.

31 30

27 26 25 24 23

21 20

[~rz-Ut~'
L

16 15

1211

, I ,

, I

PAGE FRAME NO

LNGWD ACCES ENB
BYTE OFFSET
MAP REG VALID

Figure 11-34· Map Register Format

Bit

Function

MAP REG VALID (Map register valid) - Controlled by the software
to indicate the status of the map register contents. This bit is monitored each time the UNIBUS memory page is accessed. When
set, the UNIBUS transfer is allowed to continue. When cleared, the
UNIBUS transfer is aborted, a nonexistent memory error is indicated to the device, and the invalid map register bit is set in the
UBA status register.

11-58· VAX Input/Output Subsystems

Bit

Function

30:27

MBZ (Must be zero).

LNGWD ACCES ENB (Longword access enable) - When set, and
the map register selects a buffered data path, then the longwordaligned 32-bit random access mode is enabled. This bit is cleared
during the UBA initialization.

BYTE OFFSET - When set, and when the UNIBUS memory page
corresponding to this register is using one of the buffered data
paths and the transfer is to an SBI memory address, then the
UNIBUS adapter will perform a byte offset operation on the current UNIBUS data transfer. In the VAX 8600 the condition of a
transfer to the SBI memory address is not required. The software
can interpret this operation as an increase in the physical SBI memory address, mapped from the UNIBUS address, by one byte. This
allows word-aligned UNIBUS devices to transfer to odd-byte memory addresses. This bit is cleared during the UBA initialization.

24:21

DATA PATH DESIG (Data path designator) - A binary number,
selected by software that indicates the data path to be used by the
UNIBUS memory page. More than one UNIBUS transfer can be
assigned to the direct data path and only one active transfer is
assigned to a buffered data path. The designator bits are cleared
during UBA initialization and the values are assigned as follows:
Value

Data Path

Direct data path
Buffered data paths 1 through 15

1-15
20:0

SBI PAGE ADDR (SBI page address) - The SBI page address (or
page frame number) to which the UNIBUS memory page will be
mapped. These bits perform the UNIBUS-to-SBI page address
translation. When an SBI transfer is initiated, the contents of SBI
page address (SPA 27: 7) are concatenated with UNIBUS address
bits (bits A8:A2) to form the 28-bit SBI address.

MASSBUS Subsystem Functions
The MASSBUS subsystem is a dedicated communications path that allows
high-performance mass storage devices including disk drives and magnetic
tape transports to be interfaced with medium- and large-VAX systems. The
subsystem includes an RH750 MASSBUS adapter (MBA) for the VAX-lli
750 processor and an RH780 MBA for the VAX-ll1780 series processors

11-59

and the VAX 8600 processor. Included with the MBA is the MASSBUS,
which forms the data and control path for the devices. The MBA is the
hardware link between the internal processor bus and the MASSBUS lines.
In the VAX-111750 system, the adapter connects to the computer memory
interconnect (eMI) bus within the processors; in large VAX processors the
adapter connects to the synchronous backplane interconnect (SBI) bus of
the processor. The MASSBUS adapters perform similar functions with both
medium- and large-VAX processors; however, the methods used to implement these functions can vary, depending on the adapter.>

• MASSBUS SIGNAL LINES
Figure 11-35 shows the signal lines that connect the devices with the MBA.
Table 11-10 lists each of the lines and defines their function. The MASSBUS
consists of 54 signal lines, including asynchronous control path and synchronous data path lines.

MASSBUS CONTROL BUS
COO-IS (CONTROUSTATUS)
CPA (CONTROL BUS PARITY)
DSOO-02 (DRIVE SELECT)
RSOO-04 (REGISTER SELECT)
CTOD (TRANSFER DIRECTION)
DEM (DEMAND)
TRA (TRANSFER)
MASSBUS
ADAPTER

MASSBUS
DEVICE

ATTN (ATTENTION)
INIT (INITIALIZE)

DATA BUS
DOO-15 (DATA)

DPA (DATA BUS PARITY)
SCLK (SYNC CLOCK)
WCLK (WRITE CLOCK)
RUN (START, CONTINUE, STOP)

EBL (END OF BLOCK)
£XC (EXCEPTION)
OCC (OCCUPIED)

Figure 11-35 • MASSBUS SignalLines

11-60' VAX InputlOutpulSubsystems

TABLE 11-10' MASSBUS Line Descriptions
Line

Description

COO-CI5

Control and status- Transfers 16 parallel control or status
bits to or from the device.

CPA

Control bus parity~ Transfers odd control bus parity to or
from the device. The parity is simultaneously transferred
with control bus data.

DSOO-DS02

Device select- Transfers a 3-bit binary code from the MBA
to a select controller. The device responds when the unit
select switch in the controller corresponds to the transmitted
binary code.

RSOO-RS04

CTOD

Controller-to-device- Indicates the direction of information
transfer on the control bus. For a controller-to-device transfer, the MBA asserts CTOD, and for a device-to-controller
transfer, the MBA negates CTOD.

DEM

Demand - Asserted by the MBA to indicate that a transfer
will occur on the control bus. For a controller-to-drive transfer, the line is asserted by the MBA when data is present. For a
drive-to-controller transfer, the line is asserted by the MBA to
request data and is negated when the'data has been received
from the control bus. The RS, DS, and CTOD lines are
asserted before the assertion of this line.

TRA

Transfer-Asserted by the device in response to the assertion
of the DEM line. For a controller-to-drive transfer, the TRA
line is asserted when the data is strobed, and negated when
the DEM line is negated. For a drive-to-controller transfer,
TRA line is asserted when the data is asserted on the bus and
negated when the DEM line is negated.

ATTN

Attention - This line is connected to all devices on the MASSBUS and asserted by the device to inform the MBA of any
change in device status or of an abnormal condition. This
line is asserted when the ATA status bit of a device is set and
may be asserted by more than one device at a time.

INIT

Initialize-Asserted by the MBA to initialize all devices on the
bus. This signal is transmitted whenever the MBA receives an
initialize command.

11-61

Line

Description

FAIL

Fail- Asserted to indicate that a powerfail condition has occurred in the MBA or that the MBA is in maintenance mode.

DOO-D15

Data - Bidirectional lines that transfer 16 bits of parallel data
between the MBA and devices.

DPA

Data bus parity- Transfers an odd parity bit to or from the
device simultaneously with the data on the data lines.

SCLK

Sync clock - Asserted by the device during a read operation
to indicate that the data is to be strobed by the MBA. During
a write operation, SCLK is asserted to the MBA to indicate the
rate at which data on the data lines would be presented by
the MBA on the data bus.

WCLK

Write clock - Asserted by the MBA to indicate that the data
on the data lines is available for the device.

RUN

Run - Asserted by the MBA to initiate the data transfer command execution. During a data transfer, the device samples
the line at the end of each sector and, if it is asserted, the
drive continues the transfer into the next sector. If RUN is
negated, the device terminates the transfer.

EBL

End-of-block - Asserted by the device at the end of each sector. For certain error conditions when the operations must be
terminated immediately, this line is asserted prior to the normal time and the transfer is terminated before the end of the
sector.

EXC

Exception - Asserted by the device or MBA to indicate that
an error condition has occurred during a data transfer command. This line remains asserted until the trailing edge of the
last end-of-block signal occurs.

acc

Occupied - Indicates acceptance of a valid data transfer
command .

• MASSBUS ADAPTER OPERATION
The MASSBUS adapter (MBA) consists of an SBI/MBA interface, internal
registers, control paths, and data paths. Figure 11-36 is a simplified diagram of the MBA. An internal bus connects the SBI module to the internal
registers, control paths, and data paths, and provides for the passage of
data to the various functional blocks.

11-62' VAX Input/Output Subsystems

1-------MAs~SIDAITffi-------1

I
I
I

I
I

<__ >
I

S_BI_B_US_ _

INTERFACE

L _____________________

I
I
I
I
I
I
~

Figure 11-36 • MASSBUS Adapter Configuration

The MBA accepts and executes commands from the GPU ahd reports status
changes and fault conditions to the cpu. The MBA transfers register data or
blocks of data to or from mass storage devices. A 256 by 32-bit RAM in the
MBA is a map register that stores the physical page addresses of the block
of data to be transferred. Information can be transferred to or from contiguous or noncontiguous memory locations. Memory data is transferred
through the SBI to the MBA as a 64-bit quadword and between the MBA
and a device as eight 16-bit words. The MBA can transfer data to or from a
device at a rate of 16 bits per microsecond. The MBA controls the transfer
of data between the device and the SBI and contains a 32-byte buffer used
to store the data for transfer. Four MASSBUS transfers of 16 bits each are
therefore required for each memory transfer. The MBA accepts longwordaligned read and write transactions to the internal registers.
The control path is used for the transfer of control information to and from
the MASSBUS devices. Sections of the MBA address space sdect registers
physically located within MASSBUS devices. The MASSBUS control path is
used to communicate with these data path registers.
The data path controls the data transferred to and from the MASSBUS
device and the SBI. The 32-bit SBI data word is divided into 16-bit segments. When performing a read operation from a MASSBUS device, the
data path assembles the two 8-bit bytes from the MASSBUS into the 32-bit
SBI format. A silo and input/output data buffer are used to increase the
data transfer rate. The data path also contains a write check circuit, which
can be used under program control to verify the accuracy of the data transfer function.

11-63

Each SBI device is a nexus and is assigned an 8-Kbyte control address
space that is accessible as part of the SBI I/O longword address space. The
command/address formats used to access the medium- and large-VAX system MBA registers is shown in figure 11-37.

28 27

25 24 23

16 15 14 13 12 11 10 9 8 7

1".1,,1[ .. ,,,.IJJI.l.I,,~,.
=~J
FUNC

MBA\DDR

MBZ

Jt'

/ MB
SEL

NOT

MBZ

REG/MAP SEL

~SED

J
•

Medium VAX System MBA
24 23

17 16 15

13 12 11 10 9 8 7

. I I .. I I . I . I .. ~ I •
MBZ

NOT [
USED

!~J
REQNO

VALID

MBZ

NOT USED

REG/MAP SEL

Large VAX System MBA
Figure 11-37· Command/Address Word Format

Medium VAX System MBA
Bit

Function

31:28

BYTE MASK.

27:25

BUS FUNC (Bus function).

MBZ (Must be zero).

23:15

MBAADDR (MBA address)-Ahexadecimal value (IEI5) used to
select the MBA address space.

14: 13

MBA SEL (MBA Select) - A binary value that selects the MBA
addressed.

MBZ (Must be zero).

11: 10 REG/MAP SEL (Register or map select)-A binary value that selects
one of the following I/O address spaces:

11-64· VAX Input/Output Subsystems

Bit

9:0

Function
Bit 11

Bit 10

Selection

MBA internal register
Bits 9:5 must be zero
Bits 4:2 register select offset

MBA external register
Bits 9:7 device select
Bits 6:2 register select

MBA map
Bits 9:2 map address

Invalid - No response to address

Not used.

Large VAX System MBA
Bit

Function

31:30

Not used.

VALID-Must be set to 1.

28: 17

MBZ (Must be zero).

16: 13

XFER REQ NO (Transfer request number).

MBZ (Must be zero).

11: 10

REG/MAP SEL (Register or map select) - A binary value that selects
one of the following I/O address spaces:

Bit 11

Bit 10

Selection

MBA internal register
Bits 9:5 must be zero
Bits 4:0 register select offset

MBA external register
Bits 9:7 device select
Bits 6:0 register select

MBA map
Bits 9:0 map address
Invalid - No response to address

9:0

Not used.

11-65

• VIRTUAL TO PHYSICAL ADDRESS TRANSLATION
The virtual address register (VAR) and the 256 map registers are used to
transform the virtual addresses from memory into the physical addresses of
the registers and storage locations of the MBA and devices on the MASSBUS. The virtual address is loaded into the VAR hefore the data transfer is
initiated. The register stores the address information from the SBI and uses
it to access the data in the map register file. The address translations performed between medium and small systems are similar. Figure 11-38 shows
the translation process for medium-VAX processors and figure 11-39 shows
the process for large-VAX processors.

1615

31
RESERVED

PFN

9 H

1716

M BA 31

VIRTUA~I

ADDRESS
REGISTER

MAP POINTER

MBZ

INDEX INTO MAP REGISTERS

MAP REG ISTERS

3130

'--

1.0N(;WORD

DIRECT
TRANSFER

1514
PHYSICAL PAGE ADDRESS

RESERVED
I

/''''''''

TRANSH.R

i
PHYSICAL
ADDRESS

..
23

....

9 8
PHYSICAL PAGE ADDRESS

•

0
LONG WORD

L.._ _ _ _ _ _ _ _ _ _- ' - .- - : -_ _ _ _- - - ' .

Figure 11-38 • Virtual-to-Physical Address Translation (Medium- VAX Processor)

11-66' VAX Input/Output Subsystems

VIRTUAL
ADDRESS
REGISTER

17 16

INDEX INTO MAP REGISTERS

9 8
MAP POINTER

LONG WORD

MAP REGISTERS

31 30

t--

21 20

vi RESERVED I PHYS. PAGE ADDRESS

frm

DIRECT
TRANSFER

TRANSFER

.
,27
,
:v
7 6
0
SBI
I
PHYSICAL
PAGE
ADDRESS
ADDRESSL__________________________________J -__________ I
~

Figure 11-39 • Virtual-to-Physical Address Translation (Large- VAX Processors)

• MBA REGISTERS
The MBA address space contains internal and external registers. The internal registers are located in the MBA, and the external registers are drive and
drive-controller registers located in the MASSBUS devices. The internal reg·
isters, including the 256 by 32-hit map registers, monitor the status condi·
tions and control the adapter operation and data transfers between the SBI
and the devices. These functions include maintaining a byte count to
ensure that all of the data to be transferred has been accounted for, and
converting virtual addresses to physical addresses for referencing data in
memory. The number of internal registers depends on the type of MBA.
Table 11-11 lists the internal MBA registers.

11-67

TABLE 11·11 . MBA Internal Registers
Register Name

Control register (CR)
Status register (SR)
Byte count register (BCR)
Diagnostic register (DR)
Command/address register (CAR)
Virtual address register (VAR)
Configuration register (CSR)*
Selected map register (SMR)*
*Contained in MBA for large-VAX processors only

Virtual Address Register-The map-select and byte-offset values of the
virtual address register (VAR) are used to assemble a physical SBI address
to be sent to memory. The VAR is incremented by eight after every memory read or write operation. Figure 11-40 shows the format of the register
information.

2423

17 16 15

.. I

,."

MBZ

8 7

9
I

I I

MAP SELECT

0
I

I I

I ,

LNGWD

Figure 11-40 • Virtual Address Register Format

FIGURE 11·40' Virtual Address Register Format
Bit

Function

31:17

MBZ (Must be zero).

16:9

MAP SELECT - A binary value used to select one of 256 MBA map
registers.

8:0

LNGWD - A binary value used to select the byte offset into the
page of the current data byte.

11-68· VAX Input/Output Subsystems

Control Register- The control register (CR) is a read-write register with a
byte offset value of four and is used to control the operations of the MBA.
Figure 11-41 shows the CR bit configurations. The bit functions are decribed as follows:
31

2423

I..

. I.

1615

, ,

87543210

111111.111111111

MODEJUU~~

MBZlIGNR BYTE CNT
MAINTMODE
INTENB
ABORT
MBAINIT

Figure 11-41 • Control Register Format

Bit

Function

31:5

MBZ(Mustbezero).

MBZ (Must be zero for large-VAX processors).

IGNR BYTE CNT MODE (Ignore byte count mode) - For the VAX11/750 processors, this bit is set to prevent the termination of a
data transfer as a result of a byte counter overflow. The data transfer is terminated when a signal informs the MBA that the last byte
has been transferred. It is cleared by writing a zero to this bit or by
MBA initialize.

MAINT MODE (Maintenance mode) - Set to select the maintenance mode for the MBA operation. This mode allows the diagnostic program to exercise and examine the MASSBUS without the use
of MASSBUS devices. The current MASSBUS operation must be
completed before this mode can be initiated.

INT ENB (Interrupt enable) - Set to allow the MBA to interrupt the
CPU when specific conditions occur.

ABORT - Set to stop the data transfer operations and will cause an
interrupt to the processor if the INT ENB (bit 2) is set.

MBA INIT (MBA initialize) - A write-only bit set to initialize the
MBA by clearing specific registers within the MBA, by canceling the
commands pending, and by aborting data transfers.

11-69

Status Register~ The status register (SR) is a read-write register that contains the status of the MBA and can be monitored by the processor or
devices. The functions of the SR for medium- and large-VAX processors
are similar. The differences are listed in the bit descriptions. Figure 11-42
shows the assignments of the bits in the register.
DWDD

MDll

111111,,11

~~t"L

Miz

mDUVMU~UU"W98

76543210

111111111111111111111

~JtU~~J~

CORR RD PROG ERR
DATA NON EXIST DRIVE
NOT USEDI MB CTRL PAR ERR
NO RESP CONF
ATTN
DATA XFER BUSY
MBZ
MBZ/SILO PAR ERR
DATA XFER COMPDATA XFER ABORTWR CHK UPPER ERR WR CHK LOWER ERR MISS XFER ERR MBEXCEPMB DATA PAR ERR PAGE FRAME MAP PAR ERRINVLDMAPERRCONFRDDATASUBINTFC SEQ TMORDDATATMO-

Figure 11-42 • Status Register Format

Bit

Function

DATA XFER BUSY (Data transfer busy) ~ Set when a data transfer
command is received and cleared when the transfer has been
completed.

Not used with VAX-11/750 processor.

NO RESP CONF (No response confirmation) ~ In large VAX processors, this bit is set when no response confirmation is received by
the MBA for a read or write command or when write data is sent to
the SBI. Setting this bit will cause the command to be reissued. The
bit is cleared by writing a one and by the MBA initialize sequence.

CORR READ DATA (Corrected read data) ~ Set when the data

received by the MBA from memory has been corrected;
cleared by the sub~equent receipt of a valid data transfer command, by writing a one to this bit, or by the MBA initialize
sequence.
28:20

MBZ (Must be zero) ~ For large-VAX processors.

11-70· VAX Input/Output Subsystems

Bit

Function

28:24

MBZ (Must be zero)-For VAX-ll/750 processor.

CNTL BUS HUNG (Control bus hung) - Set on the VAX-ll/750
processor to indicate that the transfer line (TRA) has been asserted
for 1.5 microseconds after the MBA has received a read or write
command to an external register, and that any previous external
register operations are complete. No data transfer operations can
be initiated until this bit is cleared by writing a one to this bit or by
the MBA initialize sequence.

22:20

MBZ (Must be zero).

PROG ERR (Programming error)-Set when the MBA is performing
a data transfer and the program attempts to initiate a transfer; to
load the map register, VAR, or BAR; or to select the maintenance
mode. Setting this bit will initiate a program interrupt if the INT
ENB bit of the CR is set. It is cleared by writing a one to this bit or
by the MBA initialization sequence.

NON EXIST DRIVE (Nonexistent drive) - Set when a device fails to
assert the transfer (TRA) line within 1.5 microseconds after the
assertion of the demand (DEM) line. Setting this bit will cause all
zeros to be sent to the SBI and will interrupt the processor if the
INT ENB (bit 2) of the CR is set. Cleared by writing a one to this bit
or by the MBA initialization sequence.

MB CNTL PAR ERR (MASSBUS control parity error) - Set when a
MASSBUS control parity error occurs; cleared by writing a one to
this bit or by the MBA initialization sequence.

ATTN (Attention) -Set when the attention line is asserted; causes a
program interrupt if the INT ENB (bit 2) of the CR is set.

15:14

MBZ (Must be zero)-For large-VAX processors.

MBZ (Must be zero) - For the VAX -11/750 processor.

SILO PAR ERR (Silo parity error) -Set on the VAX-ll/750 processor when a silo parity error occurs during a data transfer; stopping
the transfer. This results in a processor interrupt if the INT ENB
(bit 2) of the CR is set. It is cleared when the MBA subsequently
receives a valid data command, by writing a one to the bit, or by
the MBA initialize sequence.

DATA XFER COMP (Data transfer complete) - Set when the data
transfer is completed normally or because of an error. It is cleared
when the subsequent valid data command is received, by writing a
one to this bit, or by the MBA initialization sequence.

11-71

Bit

Function

DATA XFER ABORT (Data transfer aborted) - Set by the signal on
the end-of-block (EBL) line when the data transfer has been
aborted. An interrupt request is initiated if the INT ENB (bit 2) of
the CR is set. It is cleared by writing a one to this bit or by the MBA

initialization sequence.
11

DATA LATE- Set by the write-clock signal when the data buffer is

empty during a write-data or write-cheek-data transfer, or by the
sync-clock signal when the data buffer is full during a read data
tl'ansfer. This will abort the data transfer. It is cleared by writing a
one to this bit or by the MBA initialization sequence.
10

WR CHK UPPER ERR (Write check upper error) - Set when a compare error is detected in the upper byte of data while the MBA is

performing a write check operation; cleared by writing a one to
this bit, or by the MBA initialization sequence.
9

WR CHK LOWER ERR (Write check lower error) - Set when a compare error is detected in the lower byte of data while the MBA is

performing a write check operation; cleared by writing a one to .
this bit or by the MBA initialization sequence.
8

MISS XFERERR (Miss transfer error) -Set when the sync-clock or
occupied signal is not received within 500 microseconds after data
transfer busy (bit 31) is set. This initiates an interrupt request if the
INT ENB (bit 2) of the CR is set. It is cleared by writing a one to this
bit or by the MBA initialization sequence.

MB EXCEP (MASSBUS exception) - Set when the exception signal
is received from the MASSBUS on the EXC line and results in the
termination of the data transfer.

MB DATA PAR ERR (MASSBUS data parity error) - Set when a
MASSBUS data parity error is detected during a read data transfer

operation and results in the termination of the data transfer;
cleared by writing a one to this bit or by the MBA initialization
sequence.
5

PAGE FRAME MAP PAR ERR (Page frame map parity error) - Set
when a parity error is detected on the page frame number that was
read from the page frame map. This results in the termination of
the data transfer. It is cleared by writing a one to this bit or by the
MBA initialization sequence.

INVLD MAP (Invalid map) - Set when the valid bit of the next page
frame number is zero, and will terminate the data transfer operation; cleared by writing a one to this bit or by the MBA initialization sequence.

11-72· VAX Input/Output Subsystems

Bit

Function

ERR CONF (Error confirmation) - Set when the MBA receives an
error confirmation for a read or write command, resulting in the
termination of the data transfer operation; cleared by writing a one
to this bit or by the MBA initialization sequence.

RD DATA SUB (Read data substitute) - Set when the tag of the data

read from memory indicates a read data substitute, resulting in the
termination of the data transfer operation; cleared by writing a one
to this bit or by the MBA initialization sequence.
INTFC SEQ TMO (Interface sequence timeout) - Set when no
response is received within 102.4 microseconds after the SBI

sequence has begun and one of the following conditions has
occurred. This results in the termination of the data transfer
operation.
- An acknowledge is received for a command or addressttransfer
that specifies a read operation.
- An acknowledge is received for a command address transfer that
specifies a write operation; an acknowledge is also received for
each transmission of write data.
- An error confirmation signal is received for a command or
address transfer.
RD DATA TMO (Read data timeout) - Set when the time between
the initiation of the read command and the reception of the data by
the requesting nexus has exceeded 102.4 microseconds.

Byte Count Register- The byte count register (BCR) is a read-write register that contains the number of bytes to be transferred during a read
or write data sequence. Figure 11-43 shows the location of the byte count
information of the BCR.

24 23
,

8 7

T
MBBYTECNTR

,,,I,
SBI

BY~E CNTR

Figure 11-43 • Byte Count Register Format

11-73

Bit

Function

31: 16

MB BYTE CNTR (MASSBUS byte counter) - Read-only bits loaded
by the MBA serve as the counter for the number of bytes transferred through the SBI interface.

15:0

SBI BYTE CNTR (SBI byte counter) -Read-write bits that contain
the two's complement of the number of bytes to be transferred
during the read or write operation.

Diagnostic Register- The diagnostic register (DR) is a read-write register
used during the maintenance mode of operation. The register allows error
conditions to be programmed into the MBA and the results to be evaluated to determine the location of failures. Figure 11-44 shows the configuration of the bits in the diagnostic register.

-=
~~~~u

31 30 29 28 27 26 25 2423 22 21 20 19 18 17 16 15

13 12

;;;~I~iL

MAINT UP/LOW MDIB

LMAINTCTOD
MAINTEXC
MAINTWRCLK
MAINTRUN
MB FAIL
SIM EXCP
'--- INV SILO PAR GEN
'--- MAINT MB DATA BUF SEL
'---SIMATTN
'---SIMOCCUP
'---SIMEOB
'--- SIM SYNC CLK
'--- BLOCK SEND COMM
INV MAP PAR CHK
'--- INV MB CNTL PAR GEN
'--- INV MB DATA PAR GEN

Figure • 11-44

Bit

Function

INV MB DATA PAR GEN (Invert MASSBUS data parity generntor)Set to invert the data parity generator bit.

INV MB CNTL PAR GEN (Invert MASSBUS control parity
generator) - Set to invert the control parity generator bit.

INV MAP PAR CHK (Invert map parity checking) - Set to invert the
map parity check bit.

11-74' VAX Input/Output Subsystems

Bit

Function

BLK SEND COMM (Block sending command) - Set during a data
transfer to cause a data late (bit 11) of the SR to beset and a program interrupt to occur.

SIM SYNC CLK (Simulate sync clock) - Writing a one to this bit
simulates the assertion and writing a zero simulates the negation of
the synchronize clock line when the maintenance mode (bit 3) of
the CR is set.

SIM EOB (Simulate end of block) - Writing a one simulates the
assertion and writing a zero simulates the negation of the end-ofblock line when the maintenance mode (bit 3) of the CR is set.

SIM OCC (Simulate occupied) - Writing a one to this bit simulates
the assertion and writing a zero simulates the negation of the occupied line when the maintenance mode (bit 3) of the CR is set.

~~~~

SIM ATTN (Simulate attention) - Writing a one to this bit simulates
. the assertion and writing a zero simulates the negation of the attention line when the maintenance mode (bit 3) of the CR is set.

MAINT MB DATA BUF SEL (Maintenance MASSBUS data buffer
select) - Determines the information to be sent from bits 15:8 of
this register. It is set to select the upper byte (hits 15:8) of this register and is cleared to select the maintenance drive and register
select information.

INV SILO PAR GEN (Invert silo parity generator) - Invert the silo
parity generator bit.

SIM EXC (Simulate exception) - Writing a one to this bit simulates
the assertion and writing a zero simulates the negation of the
exception line when the maintenance mode (bit 3) of the CR is set.

MB FAIL (MASSBUS fail) - Set when the maintenance mode (bit 3)
of the CR is set.

MAINT RUN (Maintenance run).

MAINT WR CLK (Maintenance write clock).

MAINT EXC (Maintenance exception).

MAINT CTCm (Maintenance controller to drive).

15: 13

MAINT DEV SEL (Maintenance device select).

12:8

MAINT REG SEL (Maintenance register select).

7:0

MAINT UP/LOW MDIB (Maintenance upper/lower information
bus).

11-75

Diagnostic Register Format
Selected Map Register- The selected map register is a read-only register
that has the same format as the map register and is valid only when the data
transfer busy (bit 31) of the status register is set.
• CONFIGURATION/STATUS REGISTER
The configuration/status register (CSR) is a read-write register that provides status and configuration information of the MBA installed in large
VAX systems. Figure 11-45 shows the format of the information in the
register.
31

16 15

26 25 24 23 22 21 20

t ' , ! I , JI III
FAULT

ST:::JUJ~~

1 1

ADAPT CODE

NOT USED
ADAPT PWR DOWN
ADAPT PWR UP
OVER TEMP

Figure 11-45 • Configuration/Status Register Format

Bit

Function

31 :26

FLT STATUS (Fault status) - Indicates the following fault status
conditions that result in the assertion of a fault line of the SBI.

Bit 31 (SBI parity error) - Set when an SBI parity error has been
detected. Cleared by a power failure or a negation of the fault
signal.
Bit 30 (Write data sequence) - Set when write data is not received
following a write command. Cleared by a power failure or by the
negation of the fault signal.
Bit 29 (Unexpected read data) - Set when the data read is received
and not expected. Cleared by a power failure or the negation of the
fault signal.
Bit 28 (Must be zero).
Bit 27 (Multiple transmitter) - Set when the source identifier field
(ID) of the SBI is different from that transmitted by the MBA while
the MBA is transmitting information on the SBI. Cleared by a
power failure or by the negation of the fault signal.

11-76· VAX Input/Output Subsystems

Bit

Function

Bit 26 (Transmit fault) - Set when an SBI fault is detected on the
second cycle after the MBA transmits information to the SBI.
Cleared by a power failure or by the negation of the fault signal.
25

MBZ (Must be zero).

Not used.

ADAPT PWR DOWN (Adapter powerdown) - Set when the MBA
receives an ac low-voltage condition by the assertion of the AC LO
signal and results in a program interrupt. Cleared by the assertion
of the INIT, UNJAM, DC LO, or by writing a one to this bit.

ADAPT PRW UP (Adapter powerup) - Set when the MBA receives
the deassertion of the AC LO signal and results in a processor interrupt. Cleared by the assertion of INIT, UNJAM, DC LO, or by writing a one to this bit.

OVER TEMP (Over temperature)-Must be zero.

20:8

MBZ (Must be zero).

7:0

ADAPT CODE (Adapter code)-A unique code that identifies the
MBA (00100000).

Computer Interconnect Subsystem Functions
The computer interconnect (Cl) subsystem is a high-speed, dual-path data
bus and adapter used to locally connect medium- and large-VAX processors, and intelligent mass storage servers into a VAXcluster configuration.
The CI750 adapter is used with the VAX-11/750 processor and the CI780
adapter is used with the VAX-11/780 series processors and with the VAX
8600 processor. The adapters mount in the processor backplane and connect to the CI bus, which consists of four coaxial cables: one transmit and
one receive cable for each path. Data can be transferred simultaneously on
each of the two paths at a rate of 70 Mbits per second. The cables from the
Cl adapter in the processor connect to the SC008 star coupler unit, which
forms the cable termination and distributes the information to the nodes
in VAXcluster network. A typical VAXcluster configuration is shown in
figure 11-46.

11-77

R
STAR
COUPLER A

VAX
111780

CI
780

VAX
8600

VAX
111780

CI
780

STAR
COUPLERB

CI
780

750

.....=::= T

VAX
111750

TK·6152

Figure 11-46· CI Adapter VAxcluster Configuration

• CI ADAPTER OPERATION
The CI adapter is an intelligent high-performance interface that operates as
a buffered communications port. It transmits information using a queue
structure provided with the VAXlVMS operating system. Messages and data
are transferred in blocks between the host system's memory and other
nodes within the VAXcluster. The CI adapter provides the data buffering,
address translation, and serial encoding and decoding functions to reduce
the software normally required to perform these functions. The CI adapters
used with the intelligent mass storage subsystems are included with the
subsystem logic. Figure 11-47 shows the hardware functions that are
included with the interface .

• LINK INTERFACE
The link interface module connects to four communication lines: path A
transmit and receives line, and path B transmit and receive lines. Each line
is a coaxial cable and a pair of lines form a high-speed communications bus
to the VAXcluster configuration. The module is functionally separated into
a transmit channel and a receive channel that share a cyclic redundancy
check (CRC) function. The link interface logic can serve both paths simultaneously; however, information can be tranferred through only one CI path
at a time because of the common CRC logic. This logic generates four CRC

11-78· VAX Input/Output Subsystems

-< -<

o:l

~ ~ ~ ~
~

~ ~ ~ ~

II
~

~o-l
~:>

~~§§
::l~::E3

I-<~~

'§-

....

u~Oo

~o:l~§

:::;:t

.<;p

d
....t

''""I:j

~
:>",

t<jg;§;:;
oi1i::E3

Oil
V>

"'"t
......
.......
~

;:t

~o~

~
Os
v>_::Eo-l

·D

11-79

bytes that are appended to the data packet and are used for error checking at
the packet destination. The link transmitter converts the data packet information to a serial format, and the Manchester encoder combines the serial
data with a bit-rate clock to produce a modulated carrier for transmission
through the CI bus .
• DATA PACKET BUFFER
The data packet buffer provides the buffering of the data packets transferred through the CI interconnect. There are two transmit buffers and two
receive buffers, each with a storage capacity of 1 Kbyte. The transmit buffers receive data from the SBI through the data path logic for transfer to the
line. The receive buffers receive data from the line through the link interface and transfer the information to the SBI. The buffer contains a 3-Kbyte
RAM/PROM that stores the microcode to control and regulate the operations of the CI adapter.
• DATA PATH
The data path converts the SBI's data packet information from longwords
to bytes for transmission through the lines and converts bytes of information from the lines to longwords for transmission to the SBI. The data from
the SBI is loaded as a longword into a 32-bit transmit register and the
register transfers the information as four bytes. Th~ received data bytes are
assembled in the 32-bit receive register and transferred as a longword to
the SBI. The data path module contains a 256 by 32-bit RAM used to store
software status and registers associated with the port software architecture.
A 256 by 16-bit RAM provides storage for the virtual circuit descripter
table used to store CI node parameters, and an arithmetic logic unit (ALU)
is included to perform general purpose arithmetic and logical operations .
• CI REGISTERS
The CI adapters contain the following four registers that can be accessed
by the software for maintenance purposes.
• Configuration register
• Port maintenance control!status register
• Maintenance address register
• Maintenance data register

Configuration Register-The configuration register (CNFGR) is a readwrite register that contains SBI faults bits, port status bits, error bits, and
the adapter code for the CI interface. Only a longword can be written into
this register and information is read from the register as a byte, word, or
longword reference. Any other access mode results in an error confirmation.

11-80· VAX Input/Output Subsystems

The f6rmatof the register information for both the CI750 and CI780
adapters is shown in figure 11-48.

UDUllWWUVMUHUUUW987

J 1",1-'";'1I~I.....
;;!;;;;;'~I;;:;;;;:';;;;;;'r:
1 1",1......
1 1...
1.....
1 1...
1 ......
1 I.;;;;;,;;;;:;;''~~':;;;;;;';!;;JJ

CI750 .....
1,

:"=~JJ~1~~~ ~~~1~L~ki~;~"~;
NON EXIST MEM
RD LOCK XFER TMO
RAZ
UNCORR DATA ERR RESP
CORR RD DATA

CI780

1 1 1 1 1 1 IJ
RAZ

RAZ
NO CIPA
CIPATMO
DIAG ENB
CIPA PAR ERR

1111111 1

~~~l

[ 1 1 [ '"
R;Z

UUC

ADAPi CODE

PWR FAIL DSABL
XMITDEAD
XMITFAIL

CORR RD DATA
WT SEQFLT
RD DATA SUB
COMM XFER ERR
-RDDATATMO
- CMD XMIT TMO
-RAZ
- PWR UP, PWR DOWN
-XMITFLT
- MULT XMIT FLT
'--RAZ
~ UNEXP RD DATA FLT
~WTSEQFLT

L.-pARFLT

Figure 11-48 • Configuration Register Format

Bit

Function

31 :24

RAZ (Read as zero) - For the CI750 adapter.

PAR FLT (Parity fault) - Set to indicate that the CI has detected an
SBI parity error in the CI780 adapter.

WR SEQ FLT (Write sequence fault) - Set when the CI receives a
write-mask or interlock-write-mask command that is not immediately followed by the expected write data in the CI780 adapter.

UEXP RD DATA FLT (Unexpected read data fault) - Set when the
CI adapter received read data and had not issued a read-mask command, extended-read-mask command, or interlock-read-mask
command in the CI780 adapter.

11-81

Bit

Function

RAZ (Read as zero).

MULT XMIT FLT (Multiple transmitter fault) - Set when the CI
adapter is transmitting information to the SBI and the source/
destination (ID) bits transmitted are not the same as the ID bits
received in the CI780 adapter.

XMIT FLT (Transmit fault) - Set when the CI780 adapter asserts the
SBI fault line.

25 :24 RAZ (Read as zero) - For the CI780 adapter.
23

PWR DOWN (Powerdown) - Set by the microcode control or by
the assertion of the AC LO signal when the CI adapter is in the
uninitialized state to indicate that it has powered down; cleared by
writing a one to this bit or when the powerup (bit 22) is set.

PWR UP (Powerup) - Set by the negation of the AC LO signal to
indicate that the CI has powered up; cleared by writing a one to
this bit or when the powerdown (bit 23) is set.

RAZ (Read as zero).

CMD XMIT TMO (Command transmit timeout) - Set when a confirmation is not received within 512 cycles or 2,048 SBI cycles for a
SBI command issued by the CI780 adapter.

NON EXIST MEM (Nonexistent memory)-Set to indicate that no
response was received from a CMI operation initiated by the CI750
adapter.

RD LOCK XFER TMO (Read lock transfer timeout) - Set to indicate
that a CMI read-lock function could not be initiated by the CI750
adapter for a duration of 1,024 B-clock cycles.

RD DATA TMO (Read data timeout) - Set when the CI780 adapter
initiates an SBI read command and does not receive data within
512 SBI cycles (102.4 microseconds).

RAZ (Read as zero) - For the CI750 adapter.

CMD XFER ERR (Command transfer error) - Set when the CI780
adapter receives an error confirmation for an SBI command initiated
by the CU adapter.

UNCORR DATA ERR RESP (Uncorrectable data error response)Set to indicate that the response to a CMI operation, issued by the
CI750 adapter, contained an uncorrectable data error tag.

RD DATA SUB (Read data substitute) - Set when the CI780 adapter
response to a read command contains a read data substitute tag.

11-82· VAX Input/Output Subsystems

Bit

Function

CORRRDDATA (Corrected read datal-Set when the CI adapter

response to a read command contains a corrected read data tag.
15: 11

RAZ (Read as zero) - For the CI780 adapter.

CIPA PAR ERR (CIPA parity error)-Set when a parity error is
detected on the CIPA bus in the CI750 adapter.

DIAG ENB (Diagnostic enable)-Set to enable access to the internal diagnostic mode registers in the CI750 adapter.

CIPATMO (CIPA timeout)-Set when an unsolicited CMI bus read

or write command is not completed within 10 microseconds in
the CI750 adapter.
12

NO CIPA -Cleared to indicate that the CIPA is present, powered
up, and initialized in the CI750 adapter.

RAZ (Read as zero) - For the CI750 adapter.

XMIT FAIL (Transmit fail) - Set by microcode and is the input to
the SBI fail driver in the CI780 adapter.

XMIT ACLO (Transmit ac low)-Set as an input to the UNIBUS
ACLO driver on the CCI module in the CI750 adapter.

XMIT DEAD (Transmit dead) - Set by microcode and is an input to
the SBI dead driver in the CI780 adapter.

XMIT DCLO (Transmit dc low) - Set as an input to the UNIBUS
DCLO driver in the CI750 adapter.

PWR FAIL DSABL (Power fail disable) -Set to disable the fail or
dead indicators to the SBI on the CI780 adapter. Set to disable the
AC LO or DC LO signals from being sent to the CMI on the CI750

-----------------

adapter.
7:0

ADAPT CODE (Adapter code) - A hexadecimal value (38) assigned
to the CI adapter.

Port Maintenance Control/Status Register- The port maintenance control!
status register (PMCSR) is a read-write register that contains the port
hardware error flags and the interrupt and port initialization control bits.
The format of the information in the register is shown in figure 11-49.

11-83
31

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

6 5 4

3 2

1 0

~IIIIIIIIIIIIIIIIIIIIIIII

DOWNJUU~~~~

RAZ/PWR UP
RAZ/:::
RAZ
RAZ/NON EXIST MEM
RAZ/RD LOCK XFER TMO
RAZ
RAZ/UNCORR DATA ERR RESP
RAZ/CORR RD DATA
PAR ERR
CONT STORE PAR ERR
LOCAL STORE PAR ERR
RCV BUF PAR ERR
XMIT MULT PAR ERR
IN PAR ERR
OUT PAR ERR
BUF PAR ERR
UNINIT STATE
PROG START ADDR
NOT USED
WRONG PAR
MAINT INT FLAG
MAINT INT ENB
MAINT TIMER DSABL
MAINTINIT

Figure 11-49 • Port Maintenance Control/Status Register Format

Bit

Function

31: 16

RAZ (Read as zero)-For the CI780 adapter.

31:24

RAZ (Read as zero)-For the CI750 adapter.

PWR DOWN (Powerdown) - Set to indicate that the CI750 adapter
is powering down.

PWR UP (Powerup) - Set to indicate that the CI750 adapter is
powering up.

RAZ (Read as zero)-For the CI750 adapter.

NON EXIST MEM (Non-existent memory) - Set when no response
is received for a CI750-adapter-initiated CMI bus operation.

RD LOCK XFER TMO (Readlock transfer timeout) - Set when
the CI750 adapter cannot initiate a CMI read-lock function for
1,024 B-clock cycles.

RAZ (Read as zero)-For the CI750 adapter.

UNCORR DATA ERR RESP (Uncorrectable data error response)Set when the CI750 adapter initiates a CMI bus operation and the
response contains an uncorrectable data error tag.

11-84· VAX Input/Output Subsystems

Bit

Function

CORR RD DATA (Corrected read data) -Set when the CI750
adapter initiates a read command and the response contains a corrected read data tag.

PAR ERR (Parity error) - Set when a parity error is detected on the
CIPA bus of the CI750 adapter and if any of bits 8 through 14 are
set in the CI780 adapter.

CNTL STORE PAR ERR (Control store parity error) - Set by microcode when a parity error is detected in the control store RAM or
PROM. Not used when the control store is accessed from the SBI
(CI780 adapter) or from the CMI (CI750 adapter).

LOCAL STORE PAR ERR (Local store parity error) - Set by microcode when a parity error is detected in the local store or virtual
circuit descriptor table RAMs. Not used when the local store is
accessed from the SBI (CI780 adapter) or from the CMI (CI750
adapter).

RCV BUF PAR ERR (Receive buffer parity error) - Set when a parity
error is detected while reading a receive buffer or transmit buffer
of the packet buffer module.

XMIT MULT PAR ERR (Transmit multiple parity error) - Set when a
parity error is detected in the data being transmitted.

IN PAR ERR (Input parity error) - Set when a parity error is
detected on a data transfer from the SBI to the CI780 adapter or
from the CMI to the CI750 adapter.

OUT PAR ERR (Output parity error)-Setwhen a parity error is
detected during a data transfer from the CI780 adapter to the SBI
or from the CI750 adapter to the CM!.

XMITBUF PAR ERR (Transmit buffer parity error)-Set when a
parity error is detected on the link module transmit buffer of the
CI780 adapter or on the packet buffer module of the CI750 adapter
during transmission.

UNINIT STATE (Uninitialized state) - Set when the microcode has
stopped operation and the CI adapter is not initialized.

PROG START ADDR (Programmable starting address) -Set to start
the microcode at the address selected by the maintenance address
register (MADR), when bit 0 is set in the port initialize control register (PICR), or when a bootstrap sequence timeout occurs. When
cleared, the microcode will start at address 000.

Not used.

11-85

Bit

Function

WRONG PAR (Wrong parity) - Set to check the even parity on the

data path module.
3

MAIN INT FLAG (Maintenance interrupt flag) - Set by a condition
in the CI adapter that causes an interrupt to occur when the contents of the PSR register are valid. Allows the diagnostic program to
operate the adapter with the interrupts to the SBI (CI780 adapter)
or the CMI (CI750 adapter) disabled.

MAJNT INT ENB (Maintenance interrupt enable) - Set by writing a
one to this bit or by the DC LO signal to enable the interrupts.
Cleared by writing a zero to this bit, by setting the MAINT INIT
(bit 0), or by the SBI unjam signal.

MAINT TIMER DSABL (Maintenance timer disabled) - Set to disable the boot and sanity timers in the CI adapter, thereby prevent-

ing an interrupt.

MAINTINIT (Maintenance initialize) -Set to generate an initialize
signal to clear the CI adapter port errors. This bit is always read as a
zero. The CI adapter is uninitialized and the MAINT ENB (bit 2) is

cleared.

Maintenance Address Register- The maintenance address register (MADR)
is a read-write register that is accessible when the CI adapter is in the
uninitialized state. The address loaded into the MADR is used as a pointer
to locations in the control store RAM. The format of the register information is shown in figure 11-50.
16 IS

, I

13 12 11 10 9

RAZ

BANK
SEL

CaNT STORE SEG SEL

WORD SEL

Figure 11-50 • Maintenance Address Register Format

11-86' VAX Input/Output Subsystems

Bit

Function

31: 13

RAZ (Read as zero).

CNTL STORE SEG SEL (Control store segment select) -Selects a
segment of the control store word as follows:
0= bits 31:0
1 = bits 47:32

11: 10

9:0

BANK SEL (Bank Select) -A binary value that selects a bank within
the control store as follows:

Value

Bank (hexadecimal)

o
1
2
3

0 (000 - 3FF)
1 (400 - 7FF)
2 (800 - BFF)
3 (COO - FFF reserved)

WORD SEL (Word select)-A binary number used to access a word
within the bank selected.

Maintenance Data Register- The maintenance data register (MDATR) is a
read-write register used to access the contents of the control store location selected by the MADR and is used to initially load the microcode. The
register is valid only when the CI adapter is in the uninitialized state. The
format for the MDATR is shown in figure 11-51.

24 23

[

16 15
I

8 7
I

0
I

CaNT STORE DATA

Figure 11-51 • Maintenance Data Register Format

Bit

Function

13:0

CaNT STORE DATA (Control store data) - The contents of the
control store location specified by the MADR.

11-87

Port Status Register- The port status register (PSR) is a read-only register
that contains status flags to indicate the cause of an interrupt generated
by the CI interface. Figure 11-52 shows the format of the status information
in the register.

31 30

24 23

1111 I

, I,

16 15

I , ,
T

RAZ
LMAINTERR

876543210

, I, 11111,111111111

TIME~'ExpJUU~~~~

SANTY MEM SYS ERR
DATA STRUCT ERR
PORT INIT COMP
PORT DSABL CaMP
MESG FREE QUE
RESP QUE AVAIL

Figure 11-52· Port Status Register Format

Bit

Function

MAINT ERR (Maintenance error) - Set to indicate that the CI
adapter port has detected an internal hardware failure. When set
the CI enters the unitialized state, the microcode is halted and an
interrupt request is generated. The error is determined by the
information in the PMSCR or CNFGR.
'

30:7

RAZ (Read as zero).

SANTY TIMER EXPIR (Sanity timer expiration) - Set when the sanity or boot timer has expired and the CI adapter port has entered
the initialized maintenance state.

MEM SYS ERR (Memory system error) - Set when the CI adapter

has detected uncorrectable data or a nonexistent memory error
while accessing SBI memory (CI780 adapter) or CMI memory
(CI750 adapter). The PFAR contains additional information related
to this error.
4

DATA STRUCT ERR (Data structure error) - Set when an error is
detected in the port data structure. The PFAR contains additional
information related to the error.

PORT INIT COMPL (Port initialization complete) - Set when the

port has completed internal initialization and is in the disabled or
disabled/maintenance state.

11-88· VAX Input/Output Subsystems

Bit

Function

PORT DSABL COMPL (Port disable complete) - Set when the port
ceases to process the command queues and to respond to incoming
transmissions except for the maintenance class. The port is in the
disabled or disabled/maintenance state.

MESG FREE QUE (Message free queue) - Set when the port
attempts to access an entry from a message free queue.

RESP QUE AVAIL (Response queue available) - Set when the port
has inserted an entry in an empty response queue.

Port Failing Address Register-The port failing address register (PFAR) is
a read-only register that contains the memory address at which a failure
occurred after a memory system or data structure error or after a response
that includes a buffer-memory-system error status. This register may
contain the failing address, an address in the same page as the failing
address, or an address in part of the data structure. Figure 11-53 shows the
format of the information in the register. The register is used by the port
driver software when the microcode is operating.

I
,

16 15

24 23

I I

8 7

FAiLADDR

Figure 11-53· Port Failing-Address Register Format

Bit

Function

31:0

FAIL ADDR (Failing address) - Contains a physical address for
memory system errors (MSE) and buffer memory system errors.
Contains a virtual address or offset value for data system errors
(DSE). ThePESR may contain additional information related to the
contents of this register for DSE interrupts.

11-89

Port Error Status Register- The port error status register (PESR) is a readonly register that identifies the type of error that caused the data structure
error. This register is used by the port driver so&ware and is valid when
the microcode is operating. The register format is shown in figure 11-54.
Error indications are listed in table 11-12.

I
,

8 7

16 15

24 23
I

..,

DSEERR TYPE

Figure 11-54 • Port Error Status Register Format

Bit

Function

31:0

DSE ERR TYPE (Data structure error type) - A hexadecimal code
specifying the data structure error.

TABLE 11-12 . PASR Error Codes

Code

PFAR Contents*

Illegal system virtualaddress format
Nonexistent system
virtual address
Invalid system PTE
Invalid buffer PTE
Nonexistent system
global virtual address
Nonexistent buffer global
virtual address
Invalid system global PTE
Invalid buffer global PTE
Invalid system global PTE
mapping
Invalid buffer global PTE
mapping
Queue interlock retry
failure

3
4
5
6
7
8
9

1
1
2
1
2
1
2
1
1

11-90· VAX Input/Output Subsystems

Code

PFAR Contents*

illegal queue offset
alignment
illegal PQB format
Register protocol violation

D
E

4
5

* 1 = Virtual address
2 = PTE virtual address
3 = Queue head virtual address
4 = PQB field offset in bytes
5 = Register byte offset from device base address

Port Parameter Register- The port parameter register (PPR), a read-only

register, is loaded by the microcode during the CI adapter initialization
process and is not valid in the uninitialized state. The register indicates the
number selected by the CI adapter module switches. Figure 11-55 shows
the register format.
2423

I '~

LNGTH

16 15

8 7

I ,! '

fit.

RAZ

I , , l' ,

PORT NO

Figure 11-55 • Port Parameter Register Format

Bit

Function

SIZE-Initialized to zero and set to indicate that the 16 (maximum)
CI adapter nodes are contained in the system;

30:28

RAZ (Read as zero).

27: 16 LNGTH (Length) - Indicates the size of the internal buffers and is
preset to 3F9 (hexadecimal).
15:8

RAZ(Readaszero).

7:0

PORT NO-Indicates the hexadecimal value of the CI adapter node.

11-91

Port Initialize Control Register- The port initialize control register (PIeR)
is a write-only register that is initialized by the CI adapter software driver to
start the execution of the microcode. The format of the register is shown in
figure 11-56.

2423

,I,

I. ,

16 15
I

8 7
I

1 .0

I , , I " II
PORTINITJ

Figure 11-56 • Port Initialize Control Register Format

FIGURE 11-56· Port Initialize Control Register
Bit

Function

31:1

MBZ (Must be zero).

PORT INIT (Port initialize) - Set to initialize the CI adapter .

• PACKET FORMATS
Information is transferred between the host memory and other nodes connected to the CI adapter in blocks consisting of sequential bytes arranged
in packets. The two types of packets used, the information packet and the
acknowledgement packet, are shown in figure 11-57. Each packet consists
of synchronization bytes, packet description bytes, source and destination
information, the message body, and the trailer bytes.
In/ormation Packet- The information packet can transfer messages or data
through the CI adapter, and some of the control information is appended
by the CI adapter. The first five bytes provide bit synchronization and
include four bytes written with alternate zeros and ones to activate the
carrier detect circuits and to synchronize the Manchester decoder. The last
byte is the character synchronization, which indicates the start of packet
information. The packet-typellength (high) byte specifies an information
packet type or an acknowledge packet type and contains the upper four
bits of the packet length word. Information packets are variable in length
up to 1 Kbyte. The packet length (low) byte contains the low eight bits of
the packet length. Two destination bytes (true and complement) provide an
8-bit address of the CI node to which the packet is to be transmitted. The

11-92· VAX Input/Output Subsystems

o
BIT SYNC (55 HEX)
BIT SYNC (55 HEX)
GENERATED
OR USED
BY LINK

LOADED OR
READ BY
PORT
PROCESSOR

GENERATED
OR USED
BY LINK

BIT SYNC (55 HEX)

FIRST
BYTE
TRANSMITTED

o
BIT SYNC (55 HEX)
BIT SYNC (55 HEX)

FIRST
BYTE
TRANS·
MITTED

BIT SYNC (55 HEX)

CHAR SYNC (96 HEX)

PACKET TYPE/,.LENGTH (HIGH)

PACKET TYPE/LENGTH (HIGH)

PACKET LENGTH (LOW)

DESTINATION [[RUE)

DESTINATION (TRUE)

DESTINATION (COMPLEMENT)

SOURCE

BODY

CRC·O

CRC-O

CRC·1

CRC-l

CRC·2

·CRC-2

CRC·3

CRC-3

TRAILER (00 HEX)

B. ACK/NACK PACKET

A. INFORMATION PACKET

TK·8599

Figure 11-57· CI Subsystem Packet Configuration

true byte is the actual address value of the node that is. to receive the
information and the complement byte is the logical complement of the true
address. The source byte is an 8-bit address of the node that is sending the
message. The body bytes follow and contain data and port-processed protocol. The body can be as many bytes as required, provided that the total
packet size does not exceed 1 Kbyte. Following the body bytes are four
cyclic redundancy check bits (eRe) that provide a unique code representing the information in the packet to ensure that information is not lost or in
error during the transmission. The trailer consists of six bytes written
entirely with zeros to identify the end of a transmission and to prevent the
node from disengaging before the last data bytes are processed.

Acknowledge - N egative/Acknowledge Packet - The acknowledge-negative/
acknowledge packet is sent by the receiving node to inform the transmit-

11-93

ting node that the packet arrived without data loss or data collisions caused
by simultaneous data transmissions. If the receiving node successfully
accepts the packet, an acknowledge packet is returned to the sender indicating a successful transmission. If the receive buffers in the CI contain information when the information arrives, the negative acknowledge packet is
sent to inform the transmitting node that the packet was successfully
received but not accepted and the transmitter is required to retransmit the
packet.

DR32 Device Interconnect Subsystem Functions
The DR32 device interconnect (DDI) is a microprocessor-controlled, highperformance, I/O subsystem that allows users' devices or medium- and
large-VAX processors to be connected through the DDI 32-bit parallel data
bus. The DR750 adapter is used with the VAX-11/750 processor and connects to the CMI bus. The DR780 adapter is used with the VAX-11/780
series processors and with the VAX 8600 processor and connects to the SBI
bus. Direct memory access (DMA) communications is established between
the processor memories or between processor memory and devices, and
data can be transferred at rates of up to 6.67 Mbytes per second.
The DDI subsystem is software supported by the VAXIVMS operating system with a simple, easy-to-use 1/0 driver and a library of high-level language support routines. Data verification is performed by parity checking
on both control and data transfers. Error detection and logging, address
range checking on data transfers and online diagnosis are included with the
DDI subsystem .

• DDI ADAPTER OPERATION
The DDI adapter consists of four modules and a connecting bus. Figure
11-58 shows the configuration of the DDI adapter modules and the SBI and
I/O bus connections. The DDI adapter consists of an SBI control module
(DSC) that connects to the SBI bus and transfers the information between
adapter and SBI, performs the address translation, and provides the control
function for sequencing the information to and from the SBI bus. The
control board (DCB) performs the internal control function to sequence
the information internally within the adapter. The microprocessor and
microcode (DUP) module perform the intelligent operations required to
format and control the information for DMA transfer, thereby eliminating
the operations normally performed by the processor. The silo module
(DSM) assembles the data, address, and control bytes into packets during
the reception and transmission.
The 32-bit DDI bus is a synchronous path for transferring the data to and
from the interconnecting systems or devices. The data transfer rate is

11-94· VAX Input/Output Subsystems

synchronized by an internal clock or by an external clock provided
by the device. Transmission rates depend on the configuration of the system. The characteristics of the DDI bus are defined by the Digital DR32
specification.

UJ
~,,-..

fSffi

'z"

<'"

I I

'"
'~"
OJ

0'""'

''z""
0

'""'

;:,~

~o°::E

C:::-lO<.n

otn::E8

'":;J

;:;; I - - -

§'"

I--;:;; I - - 00
~

~g~
~g:§;

:;J

o ::t8

0'""'

N
ii5~~~ '"

"'z<~

cs8~~

0'""'

~ !Zu
c:::-ov>
oB;u8

i!l f---

D
<_ _
ms

I---

:E I - - -

11-95

• DDI SIGNAL LINES
Figure 11-59 shows the signal lines that connect to the device or processor.
The DDI is a bidirectional bus for transferring data and control signals.
Control signals are asynchronous and interlocked, and data transfers are
synchronized with clock signals. A processor or a device can initiate the
transfers. The DDI provides point-to-point connection and consists of 32
parallel data lines and 8 control lines. The control lines allow the DDI to
address up to 256 individual registers. These registers can be used for
buffer descriptor commands or status information of the user process.

...

031:00 (Data)

DP (Data p a r i t y ) -

CKAB (Clock A to B ) - CKBA (ClockB to A) -

RCVR (Receiver) - - RCVR RDY (Receiver ready)SEND 1
SEND 2
SEND 3

DDI
ADAYfER

CD? :CDO (Control Data)
-

CDP (Control data parity) -

TOSV (Transfer to slave) -

COMPlJfER
OR
DEVICE

I - RSEL (Register select) - - MSTR (Master strobe)- - - SSTR (Slave strobe) MSEL (Master select)- - - ISEL (Inhibit select) - - -

DSABL (Disable) - - -

Figure 11-59· DDI SignalLines

Data transfers can be synchronized with the clock that is included with the
DDI adapter or with an external clock provided by the user. Transfer rates
from 0.156 to 6.67 Mbytes per second can be selected by program. Table
11-13 lists the signal lines and defines their functions.

11-96· VAX Input/Output Subsystems

TABLE 11-13· DDI Signal Line Functions
Line

Description

D31:DO

Data - Bidirectional lines that contain the data for all
transactions.

Data parity - A bidirectional line that indicates the parity
of the information on the D31:OO lines.

CKAB

Clock A to B - A unidirectional line used to synchronize
the data and control information from device A to B.

CKBA

Clock B to A - A unidirectional line used to send data from
device B to A.

RCVR

Receive - A bidirectional line asserted by the clock signals
on lines CKAB or CKBA when the receiver is ready to
receive data.

RCVR READY

Receiver ready - A bidirectional line asserted by the clock
signal on the CKAB or CKBA line only if the RCVR·line is
asserted.

SEND 1,2,3

Three bidirectional lines from the sender that contain a
binary code for the type of function and the information to
be transferred, as follows:

Code

Bytes

Function

0
0
0
0
4
1
2
3

0
1
1
1
1
1
1
1

1
2
3
4
5
6
7

Data Positions
Send
Data
0
0
0

0
1
1
1
1

none
none
none
none
DATA 31:0
DATA 7:0
DATA 15:0
DATA 23:0

CD07:CDO

Control data - Bidirectional lines asserted by the master
for a write operation or by a slave for a control interconnect read operation.

CDP

Control data parity - A bidirectional line asserted as the
parity bit for the CD07 :COO data lines.

TOSV

Transfer to slave- A bidirectional line asserted by the
master to indicate that the direction of transfer is from
the master to the slave.

11-97

Line

Description

RSEL

Register select - A bidirectional line asserted to indicate
that the information on CD07:CDO is to be loaded into the
address register of the device if the TOSV line is asserted.
The contents of the address register are to be placed on
CD07 :CDO if the TOSV line is not asserted. It is also
asserted by the slave to indicate that the device cannot
complete the transfer.

MSTR

Master strobe- A bidirectional line asserted by the master
to indicate that the information on the CD07 :CDO, CDP,
TOSV, and RSEL lines are stable.

SSTR

Slave strobe - A bidirectional line asserted by the slave to
indicate that data has been received during a write
sequence and data has been sent during a read sequence.

MSEL

Master select - A unidirectional line asserted by the device
or processor selected as the arbitrator. When it is not
asserted, the remaining processor or device assumes the
arbitration function.

ISEL

Inhibit select - A bidirectional line asserted by either the
processor or device to indicate to the arbitrator that the
current level on the MSEL line should be maintained.

DSABL

Disable - A unidirectional line asserted by the processor or
device to direct the receiver to ignore the contents of the
DDI lines .

-------------------------------------

• COMMAND CHAINING
The DDI permits a series of commands to be executed without intervention
of the software for each command. Commands can be chained together in
a command queue and executed in succession. After the command
sequence is initiated, the process continues until the transfer. is halted by a
command packet that contains a halt command or by an error. The DDI
option can perform dynamic command chaining so that commands can be
added or deleted from the command queue while the DDI adapter is operating. Four of the features provided by command chaining are as follows:
• Enables commands to be continuously fetched from main memory by the
microprocessor. The microprocessor requests command information and
transfers data continuously from the virtual memory of the user's process
without program intervention.

11-98· VAX Input/Output Subsystems

• Enables direct communication through queues between the processor
and the user's process. This allows the process to directly control the DDI
adapter and the same I/O driver software to be used in a wide range of
applications. Since the user's process builds command packets, the 1/0
drivers perform only privileged tasks for the user process, such as supplying the DDI adapter with the address range of operation, fielding interrupts, and aborting the current operation.
• Includes dynamic memory mapping to allow continuous data transfers
of arbitrary length to be performed without reloading address translation
map registers. Data transfers are specified as virtual addresses that the
DDI adapter dynamically translates to physical address locations, thereby
eliminating the need for mapping of registers. The DDI buffer size is
limited only by the amount of physical memory available. The DDI uses
the same page-table entries as the CPU.
• Allows concurrent data and command transfer by the use of separate and
independent data and control lines. The subsequent command sequence
can be established while a current data transfer is being completed .
• DATA CHAINING
Command packets can specify data chaining, allowing several main memory buffers to appear to the device as one large buffer and the transfers to
be a continuous stream of data. Chained buffers can be aligned by byte and
can be any length greater than 32 bits up to the maximum physical memory size. The device or host processor can initiate data transfers in a random access mode. This mode is used when two DDI subsystems are connected to form a processor-to-processor link. Random access consists of
data transfers to or from the memory without notification of the processor
and can be discontinued by either specifying a command packet with random access disabled or by an abort from either the controlling process or
the device.

If a power failure occurs on the DDI but not on the system, the 1/0 driver
aborts the active data transfer and returns a status code in the 1/0 status
block. If a system power failure occurs, the driver completes the active data
transfer when power is recovered and ~eturns a powerfail status code.
The DDI can interrupt the I/O driver when an abort, a powerdown, or a
powerup sequence occurs, when an unsolicited control message has been
sent to the DDI, when the DDI enters the halt state, or by using a command
packet that specifies an unconditional interrupt.

n99

• PROGRAMMING INTERFACE
Direct communication between the controlling process and the DDI is enabled by the commands from user-constructed command packets located in
main memory. Command packets contain commands that specify the direction of transfer or the messages to be sent. The controlling process builds
command packets and manipulates the three queues, using the four
instructions. Figure 11-60 shows the contents of a command packet.

INPUT QUEUE FORWARD LINK (INPTQ HEAD)
INPUT QUEUE BACKWARD LINK (INPTQ TAIL)
TERMINATION QUEUE FORWARD LINK (TERMQ HEAD)
TERMINATION QUEUE BACKWARD LINK (TERMQ TAIL)
FREE QUEUE FORWARD LINK (FREEQ HEAD)
FREE QUEUE BACKWARD LINK (FREEQ TAIL)

4
12
16
20

COMMAND PACKET SPACE

TK·4606
31

2423

,1~liJl USED
NOT

PKT
CNTRL u:1 0

0 807

1615

SELF RELATIVE FORWARD LINK
SELF RELATIVE BACKWARD LINK

I I
III

COMMAND
CONTROL

LENGTH OF
LOG AREA

I LENGTHOF

DEVICE MESSAGE

BYTE COUNT
VIRTUAL ADDRESS OF BUFFER
RESIDUAL MEMORY BYTE COUNT
RESIDUAL DDT BYTE COUNT
DR32 STATUS LONG WORD
DR-DEVICE MESSAGE
LOG AREA
TK-460S

Figure 11-60 • DDI Subsystem Packet Configuration

The DDI subsystem is supported by a device driver and a high-level language procedure library of support routines. After the driver initializes the
DDI, application programs can communicate directly by inserting command packets into queues. This direct link between the application program and the DDI provides faster communication by eliminating the use of
the I/O driver.

11-100· VAX Input/Output Subsystems

The DDI is accessed by the queue I/O (QIO) driver and a set of support
routines. Application programs are used to build and insert command
packets into the DDI queues. The set of support routines provides procedures for building and manipulating command packets and performing
housekeeping functions such as maintaining command memory. The DDI
program interface contains input, termination, and free queues that control
the flow of command packets to and from the DDI interface. The application program builds a command packet and inserts it onto the input queue;
the DDI adapter removes the packet, executes the specified command, and
inserts the command packet into the termination queue. Unsolicited input,
such as a control message from the user device, is placed in packets
remove~ from the free queue and inserted into the termination queue for
later processing. Figure 11-61 shows the flow of command packets as they
are moved to the three queues.

DDIADAPTER

HEAD

FREE
QUEUE

INPUT
QUEUE

TAIL

'--_ _ _ _--L_ _

, - - - - ' - - - , TAIL
TERMINATION
QUEUE

'---"T""---' HEAD

CONTROLLING PROCESS

1------'1
TK-4615

Figure 11-61 • DDI Command Packet Flow

The application program interfaces with memory through the command
block and the buffer block. The command block contains the headers for
the three queues that provide the communication path between the DDI
and the application program and space for the command packets to be
built. The buffer block defines the area of memory that is accessible to the
DDI for the transfer of data between the user device and the DDI. If a
command packet is inserted into an empty input queue, the application
program must notify the DDI adapter; the packets are processed until the
queue is empty.
Unsolicited control messages from devices can be accepted by the DDI but
are not synchronized to the application program command flow. The application program inserts a number of empty command packets into the free

11-101

queue to allow the external device to transmit the control messages. If a
control message is received from the device, the DDI removes an empty
command packet from the head of the free queue, fills the device message
field of this packet with the control message, and inserts the packet into
the bottom of the termination queue. The device message field in this
command packet must be able to contain the entire message. or a length
error will occur. The application program then removes the packet from
this queue .

• DDI ADAPTER REGISTERS
The DDI adapter contains several registers that are accessible to the program or to the user through the console terminal. The;se DCR control registers and the user-control registers are accessible by program during normal
operation of the DDI adapter. The remaining registers can be accessed only
when the DDI adapter is in the halt state .
• DEVICE CONTROL REGISTER
The device control register (DCR) is a read-write register that provides
control and status information during read or write operations. Figure 1162 shows the register format for the read operation and figure 11-63 shows
the register format for the write operations.

31 302928272625 24 23 22 21 2019 18 17 16 15 14 13 12 11 10 9

8 7

1111111111111111111111111,"

~~~~UUL

,,,I

1 '" ADAPT TtPE CODE '

ERR CONF 102
RD DATA EXP TMO 102
COMM/ADDR TMOlO2
DATA INTERCONN STALL
ERRCONF 101
RD DATA EXP TMO 101
COMM/ADDR TMO 101
-RDDATASUB
~ CORR RD DATA
-HALT
- ABORT DATA XFER
'--PACK INT
'--INTENB
'--NOT USED
'--PWR UP
'--PWRDOWN
'-- EXT ABORT
-NOT USED
-XMITFLT
- MULT XMIT FLT
-NOT USED
- UNEXP RD DATA
-WTSEQFLT
-PARFLT

Figure 11-62 • Device-Control Read Register Format

11-102' VAX Input/Output Subsystems

Bit

Function

PAR FLT (Parity fault) - Set when a parity fault has been detected
during a data transfer.

WT SEQ FLT (Write sequence fault) -Set when a fault has occurred
during the write sequence.

UNEXP RD DATA (Unexpected read data) - Set when the DDI
adapter has received a read command before it had completed the
preceding transaction.

Not used.

MULT XMIT FLT (Multiple transmitter fault) - Set when the identifier field (ID) of the SBI is different from the ID transmitted by the
DDI adapter.

XMIT FLT (Transmit fault) - Set when an SBI fault is detected after
the DDI adapter transmits information to the SBI bus.

Not used.

EXT ABORT (External abort) - Set when the DDI adapter operation is halted by an external function.

PWR DOWN (Powerdown) - Set when the DDI adapter is powered
down.

PWR UP (Powerup) - Set when the DDI adapter has powered up to
request a processor interrupt.

Not used.

INT ENB (Interrupt enable) - Set to allow the DDI adapter to
initiate an interrupt request.

PACK INT (Packet interrupt) - Set to initiate an interrupt request
when instructed by the information in a data or command packet.

ABORT DATA XFER (Abort data transfer) - Set to initiate an abort
sequence to stop data transfers.

HALT.

CaRR RD DATA (Corrected read datal -Set when the SBI response
to a read command cont~ins a corrected-read data mask.

RD DATA SUB (Read data substitute) - Set when main memory has
an uncorrectable error on a read operation.

COMMIADDR TMO IDI (Command/address timeout IDl)-,-Set

when time allowed between the initiation of a command or address
and the acknowledge of the command has been exceeded.

11-103

Bit

Function

RD DATA EXP TMO IDI (Read data expected timeout IDl)-Set
when the time allowed between the initiation of a read command
and the receipt of the data by the requesting device is exceeded.

ERR CONF ID 1 (Error confirmation ID 1) - Set when main memory
cannot perform the command from the DDI adapter.

DATA INTRCONN STALL (Data interconnect stall).

COMMIADDR TMO ID2 (Command/address timeout ID2) - Set
when the time allowed between the initiation of a command or
address and the acknowledgement of the command is exceeded.

RD DATA EXP TMO ID2 (Read data expected timeout ID2) - Set
when the time allowed between the initiation of a read command
and receipt of the data by the requesting device is exceeded.

ERR CONF ID2 (Error confirmation ID2) - Set when the DDI
receives an error confirmation for a read or write command.

7:0

ADAPT TYPE CODE (Adapter type code) - A hexadecimal value
(30) that specifies the type of DDI adapter in the system.

24 23

16 15 14
I

MBZ

(

121110

8 7

I I'-.-"I I-.,-'I
I

CNTJ CNTL

FLD A

I I

MBZ

FLD B

MBZ

Figure 11-63 • Device-Control Write Register Format

Bit

Function

31:15

MBZ (Must be zero).

14:12

CNTL FLDA (Control field A)-A binary number used to select the
following control functions.

o = No operation- The DDI adapter ignores the current command and continues to the next command.
1 = Clear corrected read data - Clear the corrected read data
(bit 16).
2 = Set abort- Used by the 1/0 driver to set the abort (bit 18) and
start the abort sequence.

11-104· VAX Input/Output Subsystems

Bit

Function
3 = Clear packet interrupt-Clears the packet interrupt (bit 19) to
prevent the DDI adapter from interrupting the processor.
4 = Reset - Resets the DDI adapter to a known state.
5 = Set out of sequence- Used for diagnostic maintenance.
6 = Clear out of sequence- Used for diagnostic maintenance.
7 = No operation - The DDI ignores the current command and
continues to the next command.

11
10:8

MBZ (must be zero).

------------------------------------CNTL FLD B (Control field B)-A binary number used to select the

following control functions.

o = No operation- The DDI adapter ignores the current command and continues to the next command.
1 = Clear adapter powerup-Clears the powerup (bit 22) to prevent a processor interrupt.
2 = Clear adapter powerdown - Clears the powerdown (bit 23) to
prevent a processor interrupt.
3 = No operation - The DDI adapter ignores the current command and continues to the next command.
4 = Clear abort interrupt and read data substitute-Clears the
abort (bit 18) and the read data substitute (bit 15).
5 = Clear interrupt enable-Clears the interrupt enable (bit 20) to
prevent the generation of an interrupt request after the command
packets have executed.
6 = Set interrupt enable - Sets the interrupt enable (bit 20) to
allow the DDI adapter to initiate an interrupt request.
7 = Clear halt- Used by the va driver to clear the internal halt
(bit 17) and allow the DDI adapter to process commands.
7:0

MBZ (Must be zero).

11-105

Utility Register- The utility register (UTR) is a read-write register that contains miscellaneous status information from the DDI adapter. Figure 11-64
shows the format of the register information.

12 11 10

111111111,,11,,111 111,,1"1111 I

~~~~UUL

::z

FORCE CI PAR
FORCE DI PAR ERR
ENB PAR ERR ABORT
WCS PAR ERR
CIPAR ERR
DI PAR ERR
PAR ERR

t•

'-.,-;'

MBZ

DAT;RATE

LWCSVALID

Figure 11-64 • Utility Register Format

Bit

Function

PAR ERR (parity error) - Set when a parity error is detected on the
control or data information on the DDI bus, or on the writable control store.

DI PAR ERR (Data interconnect parity error) - Set when a parity
error is detected on the data interconnect information.

CI PAR ERR (Control interconnect parity error) -Set when a parity
error is detected on the control interconnect.

WCS PAR ERR (Writable control store parity error) - Set when a
writable-control-store RAM error is detected.

ENB PAR ERR ABORT (Enable parity error abort) - Set to cause the
DDI adapter to abort the data transfer and to initiate an interrupt
request.

FORCEDI PAR ERR (Force a DI parity error)-Set by the diagnostic
program to test the operation of the parity circuits for the data
interconnect.

FORCE CI PAR ERR (Force a CI parity error) - Set by the diagnostic
program to test the operation of the parity circuits for the control
interconnect.

24:12

MBZ(Mustbezero).

WCS VALID-Set to allow the microprocessor to operate and
cleared to cause the DDI adapter to abort the data transfer.

11-106· VAX Input/Output Subsystems

Bit

Function

10:8

MBZ (Must be zero).

7:0

DATA RATE-Selects the rate at which the data is transferred
through the DDI adapter. This number is the two's complement
of the count derived from the following equation.
40 data rate (Mbytes per second) = 256 (data rate in bytes)

WCS Address Register- The writable-control-store address register
(WCSAR) is a write-only register that is used to address the WCS memory
for loading the microprogram into the microprocessor. The address format
of the WCSAR is shown in figure 11-65.
31

24 23

16 15

8 7

WCSADDR

Figure 11-65· WCSAddress Register Format

Bit

Function

31:0

WCS ADDR-Contains the address of the WCS for the location in
the WCS memory where the data is to be transferred.

WCS Data Register- The writable-control-store data register (WCSDR) is a
write-only register that is used to hold the data for transfer to the WCS
memory at the address indicated by the WCSAR. The format of the data is
shown in figure 11-66.

2423

,I,

16 15

, I,

8 7

,I,

y
WCSDATA

Figure 11-66 • WCS Data Register Format

11-107

Bit

Function

31:0

WCS DATA-Contains the data to be loaded into the WCS memory
at the address specified by the WCSAR.

Address Register- The address register (ADR) is a read-write register that is
loaded by the microprocessor with the physical memory address for the
transfer of data in response to a command packet. This register is accessed
only when the DDI adapter is in the halt state. Figure 11-67 shows the
format of the information in the register.

24 23

,I,

16 15

,I,

Figure 11-67 • Address Register Format

Bit

Function

31:0

PHYS MEM ADDR - Contains the physical memory address for the
transfer of data from the DDI adapter.

SBI Byte Count Register- The SBI byte count (SBIBC) is a read-write register loaded by the microprocessor and used to monitor the number of bytes
transferred to the SBI bus. Figure 11-68 shows the register format.

16 15

. 24 23

.,I I I I

8
I

SBI BYTE COUNT

Figure 11-68 • SBI Byte Count Register Format

Bit

Function

31:0

SBI BYTE COUNT - Contains the count of the number of bytes to
be transferred from the DDI adapter to the SBI bus during the
transaction.

11-108· VAX Input/Output Subsystems

DDI Byte Count Register- The DDI byte count (DDIBC) is a read"write
register loaded by the microprocessor and used to monitor the number
of bytes transferred to the DDI adapter. Figure 11-69 shows the register
format.

;/423

16 15
I

8
I

DOl BYTE COUNT

Figure 11-69· DDI Byte Count Register Format

Bit

Function

13:0

DDI BYTE COUNT - Contains a count value of the number of bytes
to be transferred to the DDI adapter during the transaction.

User Control Register- The user control register (UCR) is a write-only register used to enable the microprocessor operation and start executing command packets. Figure 11-70 shows the format of the register information.

24 23

16 15
I

..I

8 7
I

0
I

STARTXFER

Figure 11-70 • User Control Register Format

Bit

Function

31:0

START XFER (Start transfer) - Set to initiate the execution of the
command packets.

Digital offers a complete line of intelligent mass storage subsystems and
storage devices designed specifically to operate with VAX processors and
VAX cluster architecture. These subsystems and devices allow a user to
select the mass storage requirements that best suit the system application
and to add storage capabilities when the application requirements increase.
The storage subsystems and devices operate with the UNIBUS, MASSBUS,
and VAXclusters to provide fast and reliable access to information. The
interaction of the VAX processors normally required to access and manage
data has been reduced by allocating many of the data tasks to the mass
storage subsystem and devices. Refer to the VAX Systems and Options Catalog for detailed device descriptions, configuring information, and ordering
codes of the devices available.
Digital Storage Architecture (DSA) is the standard for the design and manufacture of storage subsystems and devices and is a framework for an
expanding group of mass storage products and intelligent controllers. The
DSA provides data reliability and integrity and allows efficient performance
and ease of maintenance for all Digital storage subsystems and devices.
Within the DSA framework, the disk drives, magnetic tape units, and intelligent controllers are compatible with each other, allowing any of the
devices to operate with any intelligent controller. New systems and devices
that are developed by Digital can be easily added to the system without the
need to replace existing storage devices or to generate new software.
Some of the features provided by the DNA and storage subsystem design
are
Advanced data integrity techniques.
High-capacity mass storage devices.
Intelligent controllers that provide error detection and improved
throughput.
Easy migration to new Digital mass storage products.
Integrated host processor and storage subsystem engineering .
• Dual-access drive capabilities.

12-2· Mass Storage Subsystems and Devices

. Intelligent Mass Storage Controllers
The HSC50 and the UDA50 are intelligent controllers that perform many of
the functions required to effectively manage and control the storage and
transfer of information. The HSC50 is a special-purpose storage controller
that operates as a node within the VAXcluster architecture and coordinates
the activities of up to 24 mass storage devices, including disk and magnetic
tape drives. The HSC50 controller can serve several host processors connected to the VAXcluster CI bus. The UDA50 controller is designed for
single processor VAX systems and connects up to four disk drives to the
UNIBUS.
HSC50 Intelligent Mass Storage Server
The HSC50 is an intelligent mass storage controller that operates in a VAXclusterconfiguration. It allows VAX systems to share data stored in the
devices connected to the HSC50 controller. The HSC50 controller, shown
in figure 12-1, is contained in a cabinet 106.7 centimeters (42 inches) high,
and 53.9 centimeters (21.25 inches) wide. The HSC50 includes a power
system and is electrically isolated from the processors on the VAXcluster CI
bus. It provides high-performance and fast 1/0 data throughput using a
PDP-ll control processor and high-speed bit-slice microprocessors. An
internal high-speed bus permits simultaneous read or write operations to
the disk drives at a sustained transfer rate of up to 4 Mbytes per second.
The HSC50 offloads all disk management functions from the host processor and provides the independent sharing of the database with the processors on the VAXcluster. The controller stores up to 120 transfer requests
and provides buffering for 128 Kbytes of data. Self-contained diagnostics
software is included in the HSC50 controller to facilitate maintenance functions. Storage devices that operate with the HSC50 unit are the RA60, RA80,
and RA81 disk drives and the TA78 magnetic tape unit.

The performance specifications of the HSC50 controller are
• CI port bandwidth: 8.8 Mbytes per se.cond (maximum).
• Disk data-channel bandwidth: 3.125 Mbytes per second (maximum)
each channel.
• Internal data bus: 13.3 Mbytes per secohd (maximum).
• Request processing overhead: 1.6 milliseconds per request.

12-3

Figure 12-1 • HSC50 Intelligent Mass Storage Controller
UDA50 Intelligent Disk-drive Controller
The UDA50 is an intelligent disk-drive controller that operates with the
UNIBUS of the VAX systems and supports up to four disk-drive devices.
The UDA50 controller, shown in figure 12-2, is contained on two hexheight modules that are installed into any two adjacent UNIBUS backplane
slots. The modules provide the UNIBUS interface and disk control functions for communication between the disk drives and the host processor.
Two microprocessors are included to control the routing of data in and out
of the memory buffers located on the controller. A command queue stores
up to 20 transfer requests from the processors and a speed-matching buffer
provides the buffering for up to 52 disk sectors. Blocks of sequential data
are transferred to memory by direct memory access (DMA) requests
through the UNIBUS. The UDA50 contains diagnostic software for maintenance functions. Fault conditions are indicated by lights on the module and
by a register that can be monitored by the host processor. A last-fault register contains the last fault detected and stored in an error register. Up to
four disk drives - RA60, RA80, or RA81 disk drives in any combination - can
operate with the UDA50 controller. Figure 12-2 shows the UDA50 controller module set.

12-4' Mass Storage Subsystems and Devices

Figure 12-2 • UDA50 Intelligent Disk-drive Controller
The performance specifications for the UDA50 controller are
• Disk data transfer rates: 3.125 Mbytes per second (maximum).
• UNffiUS data transfer rates: 1.2 Mbytes per second (maXimum).

• Capacity: 1.S Gbytes per controller.

. DSA Disk-drive Subsystems
The disk-drive subsystems that operate with the HSC50 and UDA50 controllers can be mounted in several different conftgurations. Three RA60,
RASO, or RAS1 units can be installed in a single, low-height, standard-width
Digital cabinet or a single disk drive can be mounted in a cabinet together
with the TUSO magnetic tape unit. The RASO and RAS1 disk drives include
Winchester technology for reliable ftxed-data storage, and the RA60 disk
drive provides removable storage media. Up to four disk drives in any
combination can operate with either an HSC50 or UDA50 controller. The
RA60, RASO, and RASl disk drives contain dual ports and an intelligent
controller can be connected to each port. When a second UDA50 controller
is included, the disk information can be shared between the controllers.
The simultaneous access to the data in a drive through the dual ports,
however, is not supported by Digital's operating systems or diagnostic
software.

12-5

RA60 Removable-media Disk Drive
The RA60 is a medium-capacity disk drive that stores up to 205 Mbytes of
formatted data on a removable disk cartridge. The RA60 drive is available
mounted in a cabinet or as a separate unit to be mounted in a standard
cabinet 48.26 centimeters (19.0 inches) wide. The unit requires a vertical
mounting space of 26.7 centimeters (10.5 inches) and a cabinet depth of
91.4 centimeters (36.0 inches). When installed with slide mounts, up to
three disk drives can be installed in a Digital cabinet. The media is loaded
and removed from the top of the unit. The RA60 incorporates new recording methods, microprocessor-controlled diagnostics, enhanced servo technology, 170-bit error correcting code and modular design. It also contains
dual-access ports, which allow operation with two intelligent controllers.
Figure 12-3 shows the RA60 unit mounted at the top of a cabinet.

Figure 12-3 • RA60 Removable-media Disk Drive

12-6· Mass Storage Subsystems and Devices

The performance speczfications of the RA60 disk drive are
• Formatted capacity: 205 Mbytes.
• Peak transfer rate: 198 Mbytes per second.
• Access time: 50 milliseconds (average).
• Seek time: 41.7 milliseconds (average).
• Track-to-track seek time: 6.7 milliseconds.
The media specifications of the RA60 disk drive are
• Rotational speed: 3,600 revolutions per minute.
• Disk surfaces: 6 data and 4 protective.
• Tracks per surface: 1,600.
• Sectors per track: 43 (16-bit words).
• Bytes per sector: 512.

RA80 Fixed-media Disk Drive
The RA80 is a medium-capacity disk drive that incorporates Winchester
drive technology and provides up to 121 Mbytes of formatted fixed-data
storage. The RA80 drive is available mounted in a cabinet or as a separate
unit to be mouhted in a standard cabinet 48.26 centimeters (19.0 inches)
wide. The unit requires a vertical mounting space of 26.7 centimeters (10.5
inches) and a cabinet depth of 91.4 centimeters (36.0 inches). Up to three
RA80 units can be installed in a cabinet 106.7 centimeters (42 inches) high.
The RA80 incorporates a rotary positioner motor, computer-designed positioner arms, and lightweight Winchester head suspension. It also contains
dual-access ports to allow operation with two intelligent controllers. Figure
12-4 shows two RA80 units mounted in a cabinet.

12-7

Figure 12-4 • RA80 Fixed-media Disk Drive

The performance specifications for the RA80 disk drive are
• Formatted capacity: 121 Mbytes.
• Peak trans(er rate: 1.2 Mbytes per second.
• Access time: 33.3 milliseconds (average).
• Seek time: 25 milliseconds (average).
• Track-to-track seek time: 6 milliseconds.
• Latency time: 8.33 milliseconds (average).
The media specifications ~re
• Rotational speed: 3,600 revolutions per minute.
• Disk surfaces: 7 data and 1 servo.
• Tracks per surface: 1,092.
• Sectors per track: 31 (16-bit words).
• Bytes per sector: 512.

12-8· Mass Storage Subsystems and Devices

RAS1 Fixed-media Disk Drive
The RA81 is a high-capacity disk drive that incorporates Winchester drive
technology and provides up to 456 Mbytes of formatted fixed-data storage.
The RA81 drive is available mounted in a cabinet or as a separate unit to be
mounted in a standard cabinet 48.26 centimeter (19.0 inches) wide. The
unit requires a vertical mounting space of 26.7 centimeters (10.5 inches)
and a cabinet depth of 91.4 centimeters (36.0 inches). Up to three RA81
units can be installed in a cabinet 106.7 centimeters (42 inches) high. The
RA81 disk drive incorporates an encoding/decoding scheme in the readwrite system that permits more storage on a disk than on drives using
conventional encoding techniques. It also features 170-bit error correction
codes and more than 17,000 spare sectors for dynamic defect relocation.
The RA81 contains dual-access ports to allow operation with two separate
intelligent controllers. Figure 12-5 shows three RA81 units mounted in the
standard Digital cabinet.

Figure 12-5· RA81 Fixed-media Disk Drive

12-9

The performance speCIfications for the RA81 disk drive are
• Formatted capacity: 456 Mbytes.
• Peak transfer rate: 2.2 Mbytes per second.
• Access time: 36.3 milliseconds (average).
• Seek time: 28 milliseconds (average).
• Track-to-track seek time: 6 milliseconds.
• Latency time: 8.33 milliseconds (average).
The media speCIfications are
• Rotational speed: 3,600 revolutions per minute.
• Disk surfaces: 7 data and 1 servo.
• Tracks per surface: 2,496.
• Sectors per track: 51.
• Bytes per sector: 512 .

. UNIBUS Disk-drive Subsystems
The RL02 and RC25 are low-cost disk drives that operate with the UNIBUS
of the VAX processors and can be conveniently installed into a standard
Digital low-height cabinet. The RC25 disk drive is also available as a tabletop unit. The units are attached to the processor through a UNIBUS controller and up to four RL02 drives and two RC25 drives can operate with
each controller. The RL02 disk drive is not supported as a system disk but
is used as a data file residency device for transferring data to and from
other Digital systems.

RL02 Cartridge Disk Drive
The RL02 is a low-cost disk drive that stores 10.4 Mbytes of formatted data
on a removable-disk cartridge. The RL02 drive is available mounted in a
cabinet or as a separate unit to be mounted in a standard cabinet 48.26
centimeters (19.0 inches) wide. The unit requires a vertical mounting space
of 26.7 centimeters (10.5 inches) and a cabinet depth of 76.2 centimeters
(30 inches). The disk cartridge is loaded and removed from the top of the
unit. The RA60 incorporates an imbedded closed-loop servopositioning
system that improves the integrity of the data by continually sampling the
servo information with the same head that is used to read and write the
data. A cyclic redundancy check is also performed on the data transfers
between the drive and controller. Reliable reading and recording is performed by a phased-locked clock and frequency modulation techniques.
Data is transferred to the processor UNIBUS though sequential block direct
memory access (DMA) transfers. Figure 12-6 shows the RL02 unit and
removable-disk cartridge.

12-10· Mass Storage Subsystems and Devices

Figure 12-6 • RL02 Removable-Media Disk Drive

The performance specifications for the RL02 disk drive are
• Formatted capacity: lOA Mbytes.
• Peak transfer rate: 512 Kbytes per second.
• Access time: 67.5 milliseconds (average).
• Seek time: 55 milliseconds (average).
• Track-to-track seek time: 15 milliseconds.
The media specifications are
• Rotational speed: 2,400 revolutions per minute.
• Disk surfaces: 2 data.
• Tracks per surface: 512.
• Sectors per track: 40.
• Bytes per sector: 256.

12-11

RC25 Fixed/Removable Disk Drive
The RC25 is a small and compact disk subsystem that provides 52 Mbytes
of formatted data storage. It operates with the UNIBUS on VAX processor
systems and contains 26 Mbytes of storage on fixed-disk media and 26
Mbytes on removable-disk media. The RC25 is available as a tabletop unit
or as a unit that can be mounted in a standard cabinet or rack 48.26 centimeters (19 inches) wide. The tabletop unit is 25.4 centimeters (10 inches)
wide, 25.4 centimeters (10 inches) high, and 50.8 centimeters (20 inches)
deep. The RC25 incorporates Winchester technology for the fixed-disk
media and an intelligent controller and microdiagnostics for maintenance
functions. The RC25 is available with or without a controller. A maximum
of two drives can be operated with each controller. Reliable operation and
error-free transmission is ensured by 170-bit error detection and correction
code, by automatic retry and vectoring, by an embedded servo control, and
by the replacement of bad data blocks. The RC25 is compatible with
Digital Storage Architecture by using the mass storage control protocol.
The RC25 tabletop unit is shown in figure 12-7.

Figure 12-7· RC25 Fixed/Removable Disk Drive

12-12 • Mass Storage Subsystems and Devices.

The performance specifications of the RC25 disk drive are
• Formatted capacity: 56 Mbytes total.
• Peak transfer rate: 1.25 Mbytes per second.
• Access time: 45.5 milliseconds (average).
• Seek time: 10 milliseconds (average).
• Track-to-track seek time: 35 milliseconds (average).
• Rotational latency: 10.5 milliseconds (average).
• Rotational speed: 3,633 revolutions per minute.
The media specifications of the RC25 disk drive are
• Disk surfaces: 16 data and 1 servo.
• Tracks per surface: 1,260 data and 4 diagnostic.
• Sectors per track: 50 (16-bit format).
• Bytes per sector: 512 (16-bit format) .

. MASSBUS Disk-drive Subsystems
The RM05 and RP07 are high-capacity disk subsystems designed for intensive 110 applications run on VAX-1l1750 processors and VAX-1l/780 series
processors. The subsystems consist of the mass storage device, disk-drive
controller and MASSBUS adapter (MBA). The MBA is a high-speed controller module that mounts in the computer's bus-interconnects backplane,
allowing up to eight disk drives or magnetic tape formatters to operate with
the system.

12-13

RM05 Removable-media Disk Drive

The RM05 is a removable-media disk storage subsystem that operates with
the MASSBUS on VAX-1l/750 processors and VAX-U/780 series processors. It is designed for intensive data-transfer applications berween the host
processor and the disk drive, providing 256 Mbytes of formatted storage
on the removable disk. The RM05 is contained in rwo cabinets 92.0 centimeters (36.25 inches) high, one containing the drive and controller and one
utility cabinet that contains the RM05 adapter. Space is included in the
utility cabinet to mount an additional adapter. Up to eight disk-drive units
can be operated with each controller. The storage media is loaded from the
top of the drive cabinet. High-level data throughput is achieved by overlapping the seek operations with the simultaneous transfer of control information and data on the MASSBUS. That permits mid-transfer seek operations
that automatically address the next data block on the same or next higher
cylinder and allows data to be transferred in blocks. Data is transferred
from sequential blocks on the device to memory using direct memory
access (DMA) operations. The RM05 disk subsystem includes dual ports for
operation with rwo separate controllers; however, the dual-port capability
is not supported by Digital. The subsystems can be statically shared by rwo
processors or connected to one processor through rwo controllers. The
disk subsystem and removable disk media are shown in figure 12-8.

Figure 12-8 • RM05 Removable-media Disk Drive

12-14' Mass Storage Subsystems and Devices

The performance specifications for the RM05 disk drive are
• Formatted capacity: 256 Mbytes.
• Peak transfer rate: 1,200 Kbytes per second.
• Access time: 38.3 milliseconds (average).
• Seek time: 30 milliseconds (average).
• Track-to-track seek time: 6 milliseconds.
• Latency time: 8.3 milliseconds (average).
The media speczfications for the RM05 disk drive are
• Rotational speed: 3,600 revolutions per minute.
• Disk surfaces: 19 data and 1 servo.
• Tracks per surface: 823.
• Sectors per track: 32 (16-bit format).
• Bytes per sector: 512 (16-bit format).

RP07 Fixed-media Disk Drive
ne RP07 is a high-capacity disk-drive subsystem that operates with the
MASSBUS on the VAX-ll/750 processor and VAX-ll/780 series processors.
It incorporates Winchester drive technology and provides up to 516 Mbytes of formatted fixed data storage. The RP07drive and controller are
contained in a cabinet 117 centimeters (46.1 inches) high. Up to eight drive
units can be operated from one controller, The RP07 unit includes a microprocessor for controlling the major drive functions, and fault-isolation
diagnostic. programs to facilitate maintenance. The disk media and servo
heads are contained in a sealed, contaminant-free disk assembly that
ensures error-free data. High data throughput is achieved by overlapping
the seek operations with the simultaneous transfer of control information
and data on the MASSBUS. That permits mid-transfer seek operations that
automatically address the next data block on the same or next higher cylinder, allows implied seek operations, and permits transfers data in blocks.
Data is transferred in sequential blocks from the device to memory using
direct memory access (DMA) operations. The disk subsystem has dual ports
for operation with two separate controllers. The RP07 -D option is required
for a 2.2-Mbyte transfer rate on VAX-11/780 systems. The RP07 disk unit is
shown in figure 12-9.

12-15

Figure 12-9 • RP07 Fixed-media Disk Unit
The performance specifications for the RP07 disk drive are
• Formatted capacity: 516 Mbytes.
• Peak transfer rate: 1.3 Mbytes per second (2.2 Mbytes per second
optional).
• Access time: 31.3 milliseconds (average).

• Seek time: 28 milliseconds (average).
• Track-to-track seek time: 5 milliseconds.
• Latency time: 8.33 milliseconds (average).
The media specifications for the RP07 disk drive are
• Rotational speed: 3,633 revolutions per minute.
• Disk surfaces: 16 data and 1 servo.
• Tracks per surface: 1,260 data and 4 diagnostic.
• Sectors per track: 50 (16-bit format).
• Bytes per sector: 512 (16-bit format).

12-16· Mass Storage Subsystems and Devices

. Magnetic Tape Subsystems
Digital provides a complete series of industry-compatible magnetic tape
subsystems to operate with the UNIBUS and MASSBUS on VAX systems and
with the HSC50 intelligent controller in a VAXcluster system. The magnetic
tape units provide reliable medium- and high-density backup storage for
the Digital disk drives.
TU80 Magnetic Tape Unit
The TU80 is a single-density, dual-speed, 9-track tape subsystem that operates with the UNIBUS and is compatible with phase encoding (PE) ANSI
industry standards. The TU80 tape drive, controller, and power system are
contained in a cabinet 106.7 centimeters (42 inches) high. The tape drive is
horizontally mounted at the top of the unit. Space is available within the
cabinet for mounting an RA80 or RA81 disk drive subsystem. The TU80
incorporates streaming tape technology and automatically selects speeds of
25 or 100 inches per second for streaming operations and up to 25 inches
per second, depending on the data transfer rates, for start/stop operations.
The controller automatically selects the speeds, based on the type of data
transfer. The tape subsystem is connected to the VAX processor through a
shielded cable and a UNIBUS adapter module. The TU80 conforms to the
ANSI standard for phase encoding (PE) with 1,600 bits per inch on 112_
inch, 9-track tape. The TU81 uses the software protocol of the Digital Storage Architecture to prefetch commands and data for high-speed operation.
The TU80 unit is shown in figure 12-10.

Figure 12-10 • rU80 Magnetic Tape Unit

12-17

The performance and media specifications for the· TUSO magnetic tape unit
are
• Read/write speed: 25 and 100 inches per second (streaming) and 25
inches per second (maximum start/stop).
• Data transfer speed: 160 Kbytes per second maximum.
• Rewind speed: 192 inches per second.
• Rewind time: 2.5 minutes per 2,400-foot (731.5-meter) reel.
• Tape tracks: 9.
• Recording method: PE conforms to ANSI standard X3.39-1973.
• Recording density: 1,600 bits per inch (PE).
• Capacity: 40 Mbytes (PE).
• Magnetic tape: Ih-inch,9-track, conforms to ANSI standard X3.40-19S1.

TU81 Magnetic Tape Unit

The TUSI is a dual-density, dual-speed, 9-track tape subsystem that operates with the UNIBUS and is compatible with the ANSI standard for group
code recording (GCR) and phase encoding (PE). The TUSI tape drive, controller, and power system are contained in a cabinet 106.7 centimeters (42
inches) high. The tape drive is mounted horizontally at the top of the unit
and space is available within the cabinet for mounting an RASO or RASI
disk-drive subsystem. The TU81 incorporates streaming tape technology
and automatically selects speeds of 25 and 75 inches per second for streaming operations, and up to 25 inches per second for start/stop operations,
depending on the data transfer rates. The controller automatically selects
the speed that is appropriate for the type of data transfer. The tape subsystem connects to the VAX processor through a shielded cable and a UNIBUS
adapter module. As a dual-density drive, the TU81 conforms to the ANSI
standard for group code recording (GCR) with 6,200 bits per inch and for
phase encoding (PE) with 1,600 bits per inch on lh-inch, 9-track tape. The
TU81 used the software protocol of the Digital Storage Architecture, which
enables high-speed operation by the prefetching of commands and data.
The TU81 unit is shown in figure 12-11.

12-18· Mass Storage Subsystems and Devices

Figure 12-11 • TU81 Magnetic Tape Unit

The performance and media spect/ications for the TU81 magnetic tape unit
are as follows:
• Read/write speed: 25 and 75 inches per second (maximum streaming)
and 25 inches per second (maximum start/stop).
• Data transfer speed: 468 Kbytes per second.
• Rewind speed: 192 inches per second.
• Rewind time: 2.5 minutes per 2,400-foot (731.5-meter) reel.
• Tape tracks: 9.
• Recording method: GCR conforms to ANSI standard X3.54-1976 and PE
conforms to ANSI standard X3.39-1973.
• Recording density: 6,250 bits per inch (GCR) and 1,600 bits per inch
(PE).
• Storage capacity: 140 Mbytes (GCR) and 40 Mbytes (PE).
• Magnetic tape: liz-inch, 9-track, conforms to ANSI X3.40-1981.

12-19
TA78 Magnetic Tape Unit
The TA78 is a dual-density, 9-track tape subsystem that operates as a MASSBUS storage device with the VAX-111750 processor, VAX-1l1780 series
processor, or with the HSC50 intelligent controller in a VAXcluster configuration. The TA78 transport conforms to the IBM and ANSI industrystandard recording density of 6,250 bits per inch for group code recording
(GCR) and 1,600 bits per inch for phase encoding (PE). The recording
density is selected by program. The TA78 is contained in a cabinet 153
centimeters (60.2 inches) high and contains a vertically mounted tape
drive, a tape formatter and a power system. The tape is automatically
threaded through the transport. Up to three separately housed TU78 transports can be operated with one tape formatter. The TA78 performs self-test
diagnostics during startup and when data is not being transferred to the
drive. A video terminal can be connected to the unit to facilitate the diagnostic and fault isolation. The tape subsystem connects to the VAX processor through a shielded cable and a MASSBUS adapter module. The TA78
contains dual ports to allow the unit to be controlled by two HSC50 server
units. The TA78 magnetic tape unit is shown in figure 12-12.

Figure 12-12 • TA78 Magnetic Tape Unit

12-20' Mass Storage Subsystems and Devices

The performance and media specifications for the TA78 magnetic subsystem
are as follows:
• Read/write speed: 125 inches per second.
• Data transfer rate: 200 Kbytes per second (PE) and 781 Kbytes per second(GCR).
• Rewind speed: 440 inches per second.
• Rewind time: 65 seconds per 2,400-foot (731.5-meter) reel.
• Tape tracks: 9.
• Recording method: GCR conforms to ANSI standard X3.54-1976 and PE
conforms to ANSI standard X3.39-1973.
• Recording density: 6,250 bits per inch (GCR) and 1,600 bits per inch
(PE).

• Storage capacity per 2,400-foot reel: 140 Mbytes at 6,250 bits per inch
and 40 Mbytes at 1,600 bits per inch.
• Magnetic tape: liz-inch conforms to ANSI standard X3.40-1981.

TU77 Magnetic Tape Drive
The TU77 is a dual-density, 9-track tape subsystem that operates with the
MASSBUS on a VAX-ll/750 processor or VAX-ll/780 series processor. The
TU77 transport conforms to the industry standard recording density of
1,600 bits per inch phase encoding (PE) and 800 bits per inch nonreturn to
zero (NRZ). The recording density is selectable by the program. The TU77
is contained in a cabinet 153 centimeters (60.2 inches) high and provides a
vertically mounted tape drive, a tape formatter, and a power system. The
tape is automatically threaded through the transport. Up t<!J four separately
housed transports can be operated with one TU77 tape formatter. The
TU77 contains self-test features, online diagnostics, and fault isolation diagnostics to facilitate maintenance and ensure reliable operation. The tape
subsystem connects to the VAX processor through a shielded cable and a
MASSBUS adapter module. The TU77 magnetic tape unit is shown in figure
12-13.

12-21

Figure 12-13 • TU77 Magnetic Tape Unit

The performance and media specifications for the TU77 magnetic tape unit
are as follows:
• Read/write speed: 125 inches per second.
• Data transfer speed: 200 Kbytes per second.
• Rewind speed: 440 inches per second.
• Rewind time: 70 seconds per 2,400-foot (731.5-meter) reel.
• Tape tracks: 9.
• Recording method: PE conforms to IBM standards and ANSI standard
X3.39-1973.
• Recording density: 1,600 bits per inch (PE) or 800 bits per inch (NRZ).
• Storage capacity per 2,400-foot reel: 40 Mbytes with 8-Kbyte blocks at
1,600 bits per inch and 20 Mbytes with 8-Kbyte blocks at 800 bits per
inch.
• Magnetic tape: liz-inch, conforms to ANSI standard X3.40-1981.

12-22· Mass Storage Subsystems and Devices

TU78 Magnetic Tape Unit
The TU78 is a dual-density, 9~ttack tape subsystem that operates with the
MASSBUS on a: VAX-ll/750 processor or VAX-lI/780 series processor and
with the HSC50 intelligent controller in a VAXcluster configuration. The
TU78 transport conforms to the ffiM and ANSlindlistry-standard recording density of 6,250 bits per inch forgrOltp code recording (GCR) and
1,600 bits per inch for phas~ encoding (PE). The TU78 is contained in a
cabinet 153 centimeters (60.2 inches) high and contains a vertically
mounted tape drive, a tape formatter, and a power system. The tape is
automatically threaded through the transport. Up to four separately
housed transports can be operated with one tape formatter. The TU78
contains self-test features, online diagnostics, and fault isolation diagnostics
to facilitate maintenance and ensure reliable operation. The tape subsystem
connects to th~ VAX processor through a shielded cable and a MASSBUS
adapter module. The TU78 provides dual port capabilities as an option to
enable the drive to operate with two controllers. The TU78 magnetic tape
unit is shown in figure 12-14.

Figure 12-14 • TU78 Magnetic Tape Unit

12-23

The performance and media specifications for the TU78 magnetic tape unit
are as follows:
• Read/write speed: 125 inches per second.
• Data transfer rate: 781 Kbytes per second.
• Rewind speed: 440 inches per second.
• Rewind time: 70 seconds per 2,400-foot (731.5-meter) reel.
• Tape tracks: 9.
• Recording method: GCR at 6,250 bits per inch and PE at 1,600 bits per
inch.
• Recording density: 6,250 and 1,600 bits per inch.
• Storage capacity per 2,400-foot (731.5-meter) reel: 145 Mbytes at 6,250
bits per inch.
• Magnetic tape: liz-inch conforms to ANSI standard X3.40-1981.

TS05 Magnetic Tape Unit
The TS05 is a small, dual-speed magnetic tape subsystem that conforms to
the ANSI industry standard for 1,600-bits-per-inch phase encoding (PE).
The device connects to the UNIBUS of the VAX processors through an
interface and cable. The TS05 magnetic tape unit occupies a vertical
mounting space of 22 centimeters (8.7 inches) in a Digital cabinet or standard cabinet or rack 48.26 centimeters (19 inches) wide. The transport
speed can be preset to 25 inches per second or 100 inches per second. The
subsystem consists of the tape transport drive and tape formatter and an
interface/controller module that installs in the UNIBUS backplane slot. The
TS05 is a high-performance subsystem that incorporates streaming tape
technology and automatically threads the liz-inch tape in the transport.
The TS05 magnetic tape unit is shown in, figure 12-15.

12-24· Mass Storage Subsystems and Devices

Figure 12-l5 • TS05 Magnetic Tape Unit

The performance and media specifications for TS05 magnetic tape subsystem are as follows:
• Read/write speed: 25 or 100 inches per second (preset by user).
• Data transfer rate: 40 Kbytes or 160 Kbytes per second.
• Rewind speed: 180 inches per second (maximum).
• Rewind time: 2.8 minutes per 2,400-foot (731.5-meter) reel.
• Recording method: PE conforms to ANSI standards.
• Recording density: 1,600 bits per inch.
• Storage capacity per 2,400-foot reel: 40 Mbytes using 8-Kbyte blocks.
• Magnetic tape: liz-inch.

· VAX-111725 Processor
Processor Type

Microcontrol store instruction time
Control store size
Internal data path
Instruction buffer size

270ns
16-KB (24-bit word) ROM
32 bits
4-byte lookahead.

VAX Instruction Set

Number of 32-bit registers
Number of basic operations
Optional instructions
Number of priority interrupt levels
Number of addressing modes
PDP-ll compatibility
Data types

304
56 with FP730 floating-point
accelerator
32
9
Integer, floating-point, packed decimal, character string, variable-bit
fields, numeric strings, and queues

Main Memory
Virtual address space
Physical address space
Address lines
Parity
Memory cycle time

4GB
16 MB (total)
24 bits
7 -bit error-correcting code
(ECC) per 32-bit longword
810 ns per 32-bit read or write

CPU Address Translation Buffer

Size

128 address translations

CPU Clocks
Realtime clock
Time-of-year clock

Programmable, crystal controlled,
0.01 % accuracy, 1 f.Ls resolution

A-2· VAX Processor Specifications

Console Subsystem
Microprocesser
Load device
Capacity per cartridge
Bit density
Tape length
Transfer rate
Access time
Tape speed

8085A
Two TU58 cartridge tape drives
256 KB (512 records of 512 bytes
each)
800b/in
140ft
19.2 KB/s
9.3 s (avg)
28 s (max.)
30 in!s read/write
60 in!s search

RC25 Disk Subsystem
Disk type
Formatted capacity
Performance
Access time including latency
Data transfer rate .

8-in Winchester
26 MB fIxed disk, 26 MB
removable disk
35 ms seek time
(20 ms in long request queues)
45.5 ms (avg)
1,250 KB/s peak

UNIBUS Adapter
I/O transfer rate
Interrupts

1.5 MB/s (max.)
Directly vectored

CPU Options
Memory expansion
Communication interfaces

FP730 floating-point accelerator

1 MB increments (64-KB chip)
8-, 16-, and 24-line asynchronous
interfaces, multifunction controller,
and Ethernet controller
Single- and double-precision, G
and H floating-point, and POLY,
EMOD, and MULL instructions

A-3
Operating Environment
Temperature
Relative humidity
Altitude
Heat dissipation (estimated)
Acoustics level (estimated)

woe to 400 e (50°F to 104°F)
10% to 90% (noncondensing)
2,400 m (8,000 ft) max.
492 kcaVh (1952 Btu/h) max.
55 dB

Processor Power Requirements
ac line voltage tolerance
Line frequency tolerance
Phases
Surge current
Steady-state current
ac power consumption

90 to 128 V, 60 Hz
180 to 256 V, 50 Hz
47 to 63 Hz

1
17 A at 93 Vrms
8.5 A at 180 Vrms
7.1 A at 93 Vrms
3.6 A at 180 Vrms
575 W (max.)

Physical Characteristics
Weight
Height
Width
Depth

93 kg (205 lb)
62.2 cm (24.5 in)
44.5 cm (17.5 in)
72.4 cm (28.5 in)

Typical Power and Thermal Dissipation

Option
FP730 floating-point accelerator

Watts
51

DMF32 communication controller

DEUNA Ethernet controller

Heat Dissipation
43 kcaVh
(172 Btu/h)
47kcaVh
(188 Btu/h)
60kcallh
(239 Btu/h)

A-4· VAX Processor Specifications

. VAX-11/730 Processor
Processor Type
Microcontrol store instruction time
Control store size
Internal data path
Instruction buffer size

270ns
16-KB (24-bitword) ROM
17 Kwords with IDC
32 bits
4-byte lookahead

VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Optional instructions

Number of priority interrupt levels
Number of addressing modes
PDP-ll compatibility
Data types

16
304
90 instructions accelerated with
FP730 floating-point accelerator
option
32
9
Integer, floating-point, packed decimal, character string, variable-bit
fields, numeric strings, and queues

Main Memory
Virtual address space
Physical address space
Address lines
Parity
Memory cycle time

4GB
3 MB total
24 bits
7-bit error-correcting code (ECC)
per 32-bit longword
810 ns per 32-bit read or write

CPU Address Translation-Buffer
Size

128 address translations

CPU Clocks
Realtime clock
Time-of-year clock

Programmable, crystal controlled,
0.01 % accuracy, 1 f.Ls resolution

A-5

Console Subsystem
Interface
Console device
Capacity per cartridge
Bit density
Tape length
Transfer rate
Access time
Tape speed

8085 A microprocesser-controlled
Two TU58 cartridge tape drives
256 KB (512 records of 512 bytes
each)
800 blin
140 ft
19.2 KB/s
9.3 s (avg)
28 s (max.)
30 inls read/write
60 in!s search

UNIBUS Adapter
1/0 transfer rate

Interrupts

1.5 MB/s (max.)
Directly vectored

CPU Options
Memory expansion
Communication interfaces

H7750 memory battery backup
FP730 floating-point accderator

TU80 magnetic tape controller
RUC25 disk controller

1 MB increments (64-KB chip)
8-, 16-, and 24-line asynchronous
interfaces, multifunction controller,
and Ethernet controller
One per memory controller
Single- and double-precision,
G and H floating-point, and POLY,
EMOD, and MULL instructions
One per system
One per system

A-6' VAX Processor Sped/ications

R80/RL02 System

R80 disk drive
Formatted capacity
Peak transfer rate
Average access titne
Average seek time
Average latency time
RL02 disk drive
Formatted capacity
Peak transfer rate
Average access titne
Average seek time
Average latency time

Fixed media
121MB
1.2 MB/s
33.3 ms
25ms
8.33 ms
Removable media
10.4MB
512 KB/s
67.5 ms
55ms
12.5 ms

R80ITSU05 System

R80 disk drive
TSU05 magnetic tape drive
Recording density
Read/write speed
Capacity per 2,400 ft reel
Data transfer speed
Rewind speed
Rewindtitne

Refer to RBO/RL02 system
lh-in removable media
1,600b/in
25/100in/s
40 Mbytes with 8K blocks at
1,600b/in
40/160 b/s (max.)
180 in/s (max.)
2.8 min. per 2,400-ft reel

Operating Environment
Temperature
RBO/RL02 system
R80/TSU05 system
Relative humidity
RBO/RL02 system
RBO/TSU05 system
Altitude

woe to 40°C (50"F to 104"F)
15°C to 32°C (59°F to 90"F)
10% to 90% (noncondensing)
20% to 80% (noncondensing)
2,400 m (8,000 ft) max.

A-7
Processor Power Requirements

ac line voltage
Line frequency
Phases
R80/RL02 System
Steady-state current
Surge current
Heat dissipation
ac power consumption
R80/TSU05 System
Steady-state current
Surge current
Heat dissipation
ac power consumption

90 to li8 V, 60 Hz
180 to 256 V, 50 Hz
47 to 63 Hz

1
15 A at 90 Vrms (120 V)
7 A at 180 Vrms (240 V)
32 A at 90 Vrms (120 V)
12 A at 180 Vrms (240 V)
1,037 kcallh (4,109 Btu/h) (max.)
1,205W
17 A at 90 Vrms (120 V)
9 A at 180 Vrms (240 V)
34 A at 90 Vrms (120 V)
14 A at 180 Vrms (240 V)
1,119 kcallhr (4,433 Btulhr)
(maximum)
1,300W

Physical Characteristics

Weight
CPU and cabinet only
R80/RL02 system
R80/TSU05 system
Height
Width
Depth

45.4 kg (100 lb)
249.7 kg (550 lb)
290 kg (639Ib)
106.2 cm (41.8 in)
73.7 cm (29 in)
76.2 cm (30 in)

A-8· VAX ProcessorSpeci/ications

Typical Power and Thermal Dissipation

Option

Watts

Heat Dissipation

Fully-configured general-purpose
expansion cabinet (H9642-F)
FP730 floating-point accderator

1,224
51

DMF32 communication controller

DEUNA Ethernet controller

UDA50 disk controller

H7750 memory battery backup

1,054 kcallh
(4,173 Btu/h)
43 kcallh
(172 Btu/h)
47 kcallh
(188 Btu/h)
60kcaVh
(239 Btu/h)
77.5 kcallh
(307 Btu/h)
22 kcallh
(85 Btu/h)

. VAX-1l1750 Processor
Processor Type
Microcontrol store instruction time
Control store size
Internal data path
Instruction buffer size
Memory cache
System data transfer rate

320ns
6 Kwords (80-bit words) ROM
32 bits
8-byte lookahead
4-KB direct-mapped
5 MB/s (max.)

VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Number of priority interrupt levds
Number of addressing modes
Data types

16
304
32
9

Integer, floating-point, packed decimal, character string, variable-bit
fidds, numeric strings, and queues

A-9

Main Memory
Virtual address space
Physical address space
Parity
Memory cycle time

4GB
8MBtotal
7 -bit error-correcting code (ECC)
per 32-bit quadword
800 ns per 32-bit read, 640 ns per
32-bit write, 400 ns (effective) with
cache

CPU Address Translation Buffer
Size
Typical hit ratio

512 address translations
98% to 99%

CPU.Qocks
Realtime clock
Time-of-year clock

Programmable, crystal controlled,
0.01% accuracy, l ....s resolution
Includes battery backup for more
than 100hours

Console Subsystem
Interface
Console device
Capacity per cartridge
Bit density
Tape length
Transfer rate
Access time
Tape speed

Integral (VIM module)
TU58 cartridge tape drive
256 KB (5l2 records of5l2 bytes
each)
800 b/in
140 ft

19.2 KB/s
9.3 s (avg)
28 s (max.)
30 inls read/write
60 inls search

A -10 • VAX Processor Specifications

CPU Options
Memory expansion
Communication interfaces

DR750 general purpose interface
DW750 UNIBUS adapter
H7112 memory battery backup
FP750 floating-point accelerator

KU750 floating-point option
CI750 adapter

I-MB increments (64-KB chip)
8-,16-, and 24-line asynchronous
interfaces, multifunction controller,
and Ethernet controller
One per system; 32-bit parallel data
interface
One per system
One per memory controller
Single- and double-precision, F and
D floating-point and POLY, EMOD,
and MULL instructions
G and H extended-range floatingpoint data types
Computer interconnect for
VAXcluster

Operating Environment

Temperature
Relative humidity
Altitude
Heat dissipation

10°C to 40°C (50°F to 104°F)
10% to 90% (noncondensing)
2,400 m (8,000 ft) max.
1,460 kcaIlh (5,800 Btu/h) (max.)

Processor Power Requirements

ac line voltage tolerance

Line frequency tolerance
. Phases
Steady-state current
Surge current
ac power consumption

104 to 128 V, 60 Hz
191 to 233 V,50 Hz
208 to 254 V, 50 Hz
47 to 63 Hz
Single
30 A at 90 Vrms (120 V)
15 A at 180 Vrms (240 V)
100 A
1700 W (max.)

A-ll

Physical Characteristics
Weight
Height
Width
Depth

182 kg (400 lb)
106.2 cm (41.8 in)
73.7 cm (29 in)
76.2 cm (30 in)

Typical Power and Thermal Dissipation
Option
Fully configured CPU cabinet

Watts
1,700

Fully configured general-purpose
expansion cabinet (H9642-F)
RH750 MASSBUS adapter

1,224
77

DW750 UNIBUS adapter

CI750 computer interconnect

DR750 general purpose interface

100

FP750 floating-point accelerator

KU750-A user writable control store

DMF32 communication controller

DEUNA Ethernet controller

H7112 memory battery backup

Heat Dissipation
1,460 kcallh
(5,797 Btu/h)
1,054 kcallh
(4,173 Btu/h)
67 kcallh
(262 BtU/hr)
67 kcallhr
(262 Btu/h)
49 kca1!h
(191 Btu/h)
86kcallh
(341 Btu/h)
78kcallh
(307 Btu/h)
16kcallh
(62 Btu/h)
47 kcallh
(188 Btu/h)
60kcallh
(239 Btu/h)
22 kcallh
(85 Btu/h)

A-12· VAX Processor Specifications

• VAX-111780 Processor
Processor Type
Microcontrol store instruction time
Control store size
Internal data path
Instruction buffer size
Memory cache

200
6-KB (99-bit words), 4 Kword ROM
and 2 Kword writable control store
32 bits
8-byte lookahead
8-KB, 2-way set associative

VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Number of priority interrupt levels
Number of addressing modes
Data types

-304
32
9
Integer, floating-point, packed decimal, character string, variable-bit
fields, and numeric strings

Main Memory
Virtual address space
Physical address space
Parity
Memory cycle time

4GB
16 MB total (64-KB chip memory),
32 MB total (256-KB chip memory)
8-bit error-correcting code (ECC)
per 64-bit quadword
800 ns per 64-bit read (1,300 ns
with single-bit errors), 1,400 ns per
64-bit write

CPU Address Translation Buffer
Size
Typical hit ratio

128 address translations
97%

A-13

CPUOocks
Realtime clock
Time-of-year clock

Programmable, crystal controlled,
0.01% accuracy, 1 ....s resolution
Includes battery backup for more
than 100 hours

Console Subsystem
Interface
Console drive
Disk size
Storage capacity

Transfer rate

LSI -11 microprocessor-controlled
RX01 floppy-disk drive
8in
256 KB per disk
3 KB per track
128 KB per sector
50KB/s

CPU Options
CPU memory expansion

Communication interfaces

MA780 multiport memory
DR780 general-purpose interface
DW780 UNIBUS adapter
H7112 memory battery backup
FP780 floating-point accelerator

KE780 floating-point
KU780 user writable control store
CI780 adapter
MASSBUS adapters

2-MB increments (64-KB chip memory), 8-MB increments (265-KB chip
memory)
8-,16-, and 24-line asynchronous
interfaces, multifunction controller,
and Ethernet controller
Two subsystems per CPU
(4MB total)
32-bit parallel data interface
4 total
One per memory controller
Single- and double:.precision
floating-point instructions and
POLY, EMOD, and MULL
instructions
G andH exterided-range floatingpoint microcode
2 KB (99-bit words)
Computer interconnect for
VAXcluster
4 total; up to 8 high-speed disks or
tapes per adapter

A-14· VAX Processor Specifications

Operating Environment
Temperature
Rdative humidity
Altitude
Heat dissipation

WC to 32°C (59"F to 90"F)
20% to 80% (noncondensing)
2,400 m (8,000 ft)
5350 kcallh (21,230 Btu/h) (max.)

Processor Power Requirements
ac line voltage tolerance

Line frequency tolerance
Phases
ac power consumption

104-128 V,60 Hz
191-233 V,50 Hz
208-254 V, 50 Hz
59-61 Hz (60 Hz)
49-51 Hz (50 Hz)

3
6,225W

Physical Characteristics
Weight
Height
Width
Depth

498 kg (1,100 lb)
153.7 cm (60.5 in)
118.1 cm (46.5 in)
76.2 cm (30 in)

Typical Power and Thermal Dissipation

Option

Watts

Heat Dissipation

Fully configured CPU cabinet

6,225

Fully configured CPU expansion cabinet
(H9602~HA, -HB)
Fully configured UNIBUS expansion
cabinet (H9652-MF, -MH)
Fully configured multiport memory
cabinet (MA780-JA, -JB)
. RH750 MASSBUS adapter

2,000

UNIBUS adapter (DW780-AA, -AB)

300

CI78() computer interconnect

242

DR780 general-purpose interface

226

5,350 kcallh
(21,230 Btu/h)
1,720 kcallh
(6,820 Btu/h)
1,720 kcallh
(6,820 Btu/h)
1,550 kcallh
(6,140 Btu/h)
130kcaI/h
(512 Btu/h)
260 kcallh
(1,024 Btu/h)
210 kcallh
(833 Btu/h)
194kcallh
(771 Btu/h)

2,000
1,800
150

A-15
Option
FP780 floating-point accelerator

Watts
300

KU780-A user writable control store

100

DMF32 communication controller

DEUNA Ethernet controller

H7112 memory battery backup

Heat Dissipation
260kcaVh
(1,025 Btu/h)
86kcaVh
(341 Btu/h)
47kcaVh
(188 Btu/h)
60kcal/h
(239 Btu/h)
22 kcal/h
(85 Btulh)

. VAX-111782 Dual-Processor
The CPU specifications apply to both processors.
Processor Type

Microcontrol store instruction time
Control store size
Internal data path
Instruction buffer size
Memory cache

200ns
6-KB (99-bit words), 4 Kword ROM
and 2 Kword user control store
32 bits
8-byte lookahead
8 KB, 2-way set associative

VAX Instruction Set

Number of 32-bit registers
Number of basic operations
Number of priority interrupt levels
Number of addressing modes
Data types

Local memory

16
304
32

9
Integer, floating-point, packed decimal, character string, variable-bit
fields, and numeric strings
265 KB used for diagnostic programs only

A-16· VAX Processor Specifications

Shared Memory

Virtual address space
Physical address space
Parity
Memory cycle time

4GB
4MB
8-bit error-correcting code (ECC)
per 64-bit quadword
800 ns per 64-bit read (1,300 ns
with single-bit errors), 1,400 ns per
64-bit write

CPU Address Translation Buffer

Size
Typical hit ratio

128 address translations

97%

CPU Clocks
Realtime clock
Time-of-year clock

Programmable, crystal-controlled,
0.01 % accuracy, 1j.Ls resolution
Includes battery backup for more
than 100 hours

Console Subsystem

Interface
Console drive
Disk size
Storage capacity

Transfer rate

LSI-II microprocessor controlled
RXOl floppy, disk drive

8 in
256 KB per disk
3 KB per track
128 bytes per sector
50 KB/s

A-17

CPU Options
Memory expansion
Communication interfaces

H7112 memory battery backup
FP782 floating-point accelerator

KE780 floating-point
UNIBUS and MASSBUS adapters

4 MB (16-KB chip memory) with
second MA 780 cabinet
8-,16-, and 24-line asynchronous
interfaces, multifunction controller,
and Ethernet controller
One per memory controller
Two accelerators; single- and
double-precision, F and D floatingpoint instructions and POLY,
EMOD, and MULL instructions
One per CPU; G and H extendedrange floating-point microcode
4 total per system; up to 8 highspeed disks or tapes per adapter

Operating Environment

Temperature
Relative humidity
Altitude
Heat dissipation

15°C to 32°C (59°F to 90°F)
20% to 80% (noncondensing)
2,400 m (8,000 ft)
5,350 kcallh (21,230 Btulh) (max.)

Processor Power Requirements

ac line voltage tolerance

Line frequency tolerance
Phases
ac power consumption

104 to 128 V, 60 Hz
191 to 233 V, 50 Hz
208 to 254 V, 50 Hz
59 to 61 Hz (60 Hz)
49 to 51 Hz (50 Hz)
3
6,225 W (max.)

Physical Characteristics*

Weight
Height
Width
Depth

1,315 kg (2,900 Ib)
153.7 cm (60.5 in)
301.6 cm (118.75 in)
76.2 cm (30 in)

*Includes two processors and shared-memory cabinet

A -18· VAX Processor Specifications

Typical Power and Thermal Dissipation

Option
Fully configured primary CPU cabinet

Watts
6,225

Fully configured attached CPU cabinet

5,000

Fully configured multiport memory cabinet
(MA780-KA, -KB)
Fully configured CPU expansion cabinet
(H9602-HA, -HB)
Fully configured UNIBUS expansion cabinet
(H9652-MF, -MH)
RH780 MASSBUS adapter

1,800
2,000
2,000
150

UNIBUS adapter (DW780-AA,-AB)

300

FP782 floating-point accelerator

300

H7112 memory battery backup

Heat Dissipation
5,350 kcallh
(21,230 Btu/h)
3,964kcaVh
(15,700 Btu/h)
1,550kcaVh
(6,140 Btulh)
1,720 kcallh
(6,820 Btu/h)
1,720 kcal!h
(6,820 Btulh)
130kcaVh
(512 Btu/h)
260kcaVh
(1,024 Btulh)
260kcal!h
(1,025 Btulh)
22 kcaVh
(85 Btulh)

. VAX-1l1785 Processor
Processor Type

Microcontrol store instruction time
Control store size

Internal data path
System 1/0 transfer rate
Instruction buffer size
Memory cache

133 ns
8 Kwords (O.5-KB ROM and 7.5-KB
read-write) - including lKB for user
control store (99-bit words)
32 bits
13.3 MB (max.)
8-byte lookahead
32 KB,2-way set associative

A-19

VAX Instruction Set
Number of 32-bit registers
Number of basic operations
Number of priority interrupt levds
Number of addressing modes
Data types

16
304
32
9
Integer, floating-point (G and H),
packed decimal, character string,
variable-bit fidds, and numeric
strings

Main Memory
Virtual address space
Physical address space
Parity
Cycle time

4GB
32 MB total (64-KB chip memory),
64 MB total (256-KB chip memory)
8-bit error-correcting code (ECC)
per 64-bit quadword
600 ns per 64-bit read (700 ns
with single-bit errors), 700 ns per
64-bit write

CPU Address Translation Buffer
Size
Typical hit ratio

128 address translations

97%

CPU Clocks
Realtime clock
Time-of-year clock

Programmable, crystal-controlled,
0.01 % accuracy, 1 fLS resolution
Includes battery backup for more
than 100 hours

Console Subsystem
Interface
Console drive
Disk size
Storage capacity

Transfer rate

LSI-ll microprocessor-controlled
RX01 floppy-disk drive
8 in
256 KB per disk
3 KB per track
128 bytes per sector
50KB/s

A-20· VAX ProcessorSpecijications

.CPU Options

Memory expansion

MA780 multiport memory
FP785 floating-point accelerator

DW780 UNIBUS adapter
MASSBUS adapters
DR780 general purpose interface
Communication interfaces

H7112 memory battery backup
UDA50 disk controller

2-MB increments (64-KB chip
memory), 8-MB increments (256-KB
chip memory)
Two per system (4 MBs total)
Single- and double-precision
instructions plus POLY, EMOD, and
MULL instructions
4 total
4 total; up to 8 high-speed disks or
tapes per adapter
32-bit parallel data interface
8-,16-, and 24-line asynchronous
interfaces, multifunction controller,
and Ethernet controller
One per memory controller
One on first UNIBUS
Two per each additional UNIBUS

Operating Environment

Temperature
Relative humidity
Altitude
Heat dissipation (max)

we to 32°e (59°e to 90°F)
20% to 80% (noncondensing)
2,400 m (8,000 ft)
2,116 kcallh (8,350 Btulh)

Electrical Power Requirements*

ac line voltage tolerance

Line frequency tolerance
Phases
ac power consumption

104 to 128 V, 60 Hz
191 to 233 V, 50 Hz
208 to 254 V, 50 Hz
59 to 61 Hz (60 Hz)
49 to 51 Hz (50 Hz)
3
2,500 W (max.)

Physical Characteristics*

Weight
Height
Width
Depth

498 kg (1,100 lb)
153.7 cm (60.5 in)
118.1 cm (46.5 in)
76.2 cm (30 in)

*Includes CPU, one DW780, 2-MB memory (MS780-E)

A-21

Typical Power and Thermal Dissipation

Option
Fully configured CPU expansion cabinet
(H9652-HA, -HB)
Fully configured UNIBUS expansion cabinet
(H9652-MF, -MH)
Fully configured multiport memory cabinet
(MA780-JA, -JB)
RH780 MASSBUS adapter

Watts
2,000

UNIBUS adapter (DW780-AA, -AB)

300

CI780 adapter

226

FP785 floating-point accelerator

300

KU780-A user writable control store

100

DR780 general purpose interface

226

DMF32 communication controller

DEUNA Ethernet controller

H7112 memory battery backup

2,000
1,800
150

Heat Dissipation
1,722 kcallh
(6,820 Btulh)
1,720 kcallh
(6,820 Btu/h)
1,550 kcallh
(6,140 Btulh)
130kcaVh
(512 Btu/h)
260kcallh
(1,024 Btulh)
194kcaVh
(771 Btu/h)
260kcallh
(1,025 Btulh)
86kcaVh
(341 Btu/h)
194kcallh
(771 Btu/h)
47kcaVh
(188 Btulh)
60kcaVh
(239 Btulh)
22kcaVh
(85 Btu/h)

. VAX-8600 Processor
Processor Type

Microcontrol store instruction time
Control store size
Internal data path
Instruction buffer size
Memory cache
Translation buffer

80ns
8 KB (86-bit words)
32 bits
8~byte lookahead
16 KB, 2-way set associative
512 locations (one-way set
associative)

A-22· VAX Processor Sped/ications

VAX Instruction Set
Number of 32-bit register~
Number of basic operations
Number of priority interrupt levels
Number of addressing modes
Datil types

16
304
32
9
Integer, floating point (F, D, G,
and H), packed decimal, character
string, variable-bit fidds, and
numeric strings

Main Memory
Virtual address capacity
Capacity
Parity
Cydetime

4GB
32 MB max. (256-KB chip)
7-bit error-correcting code (ECC)
per 32-bit longword
500 ns per 12S-bit read

Console Subsystem
Interface
Console device
Formatted capacity
Transfer rate
Access time
Seek time
Tracks per surface
Sectors per track
Bytes per sector

Tll microprocessor-controlled
RL02 disk drive
10.4MB
512 KB/s (max.)
67.5 ms (avg)
55 ms (avg)
512
40
256

CPU options
Memory expansion
DB86 second SBI adapter
DW780 UNIBUS adapter
Communication interfaces

4-MB increments
(256-KB chip memory)
One per system
Two per CPU cabinet total
8-, 16-, and 24-line asynchronous
interfaces, multifunction controller,
and Ethernet controller

A-23
Operating Environment

Temperature
Relative humidity
Altitude
Heat dissipation

WC to 32°C (59°P to 900 P)
20% to 80% (noncondensing)
2,400 m (8,000 ft)
5,555 kcal!hr (22,000 Btuihr)

Processor Power Requirements *

ac line voltage tolerance
Line frequency tolerance
Line current
Phases
ac power consumption

156 to 222 Vrms, 60 Hz
380 to 440 Vrms, 50 Hz
47 to 63 Hz
30 A at 156 Vrms
15 A at 312 Vrms

3
6,500 w/lO kVA

Physical Characteristics

Weight
Height
Width
Depth

782.1 kg (1,725Ib)
153.7 cm (60.5 in)
186 cm (73.25 in)
76.2 cm (30 in)

Typical Power and Thermal Dissipation

Option

Watts

Heat Dis,sipation

Fully configured UNIBUS expansion cabinet
(H9652-MP, -MH)
Fully configured SBI expansion cabinet
(H9652-CA, -CB)
DB86 second SBI adapter
RH780 MASSBUS adapter

2,000

1,720kcaVh
(6,820 Btuih)

150

UNIBUS adapter (DW780-AA, -AB)

300

130kcaVh
(512 Btu/h)
260kcal!h
(1,024 Btu/h)

abort:
An exception that occurs in the middle of an instruction and potentially leaves
the registers and memory in an indeterminate state, such that the instruction
cannot necessarily be restarted.
absolute indexed mode:
An indexed addressing mode in which the base operand specifier is addressed
in absolute mode.
absolute mode:
In absolute mode addressing, the PC is used as the register in autoincrement
deferred mode. The PC contains the address of the location containing the
actual operand.
access control:
The mechanism in a node for screening inbound connect requests and verifying them against a local system account file. Access control is an optional Session Control function.
access mode:
1. Any of theJc;mr processor access modes in which software executes. Processor access modes are, in order from most to least privileged and protected:
kernel (mode 0), executive (mode 1), supervisor (mode 2), and user (mode 3).
When the processor is in kernd mode, the executing software has complete
control of, and responsibility for, the system. When the processor is in any
other mode, the processor is inhibited from executing privileged instructions.
The Processor Status Longword contains the current access mode fidd. The
operating system uses access modes to define protection levds for software
executing in the context of a process. For example, the Executive runs in kernd and executive mode and is most protected. The command interpreter is
less protected and runs in supervisor mode. The debugger runs in user mode
and is no more protected than normal user programs. 2. See record access
mode.
access type:
1. The way in which the processor accesses instruction operands. Access types
are: read, write, modify, address, and branch. 2. The way in which a procedure accesses its arguments. 3. See also record access type.
access violation:
An attempt to reference an address that is not mapped into virtual memory or
an attempt to reference an address that is not accessible by the current access
mode.

G-2 • Glossary
account name:
A string that identifies a particular account used to accumulate data on a job's
resource use. This name is the user's accounting charge number, not the user's
VIC.

address:
A number used by the operating system and user software to identify a storage
location. See also virtual acfdress and physical address.
address access type:
The specified operand of an instruction is not directly accessed by the instruction. The address of the specified operand is the actual instruction operand.
The context of the address calculation is given by the data type of the operand.
addressing mode:
The way in which an operand is specified; for example, the way in which the
effective address of an instruction operand is calculated using the general registers. The basic general register addressing modes are called: register, register deferred, autoincrement, autoincrement deferred, autodecrement,
displacement, and displacement deferred. In addition, there are six indexed
addressing modes using two general registers, and literal mode addressing.
The PC addressing modes are called: immediate (for register deferred mode
using the PC), absolute (for autoincrement deferred mode using the PC), and
branch.
address space:
The set of all possible addresses available to a process. Virtual address space
refers to the set of all possible virtual addresses. Physical address space refers
to the set of all possible physical addresses sent out on the SBI.
allocate a device:
To reserve a particular device unit for exclusive use. A user process can allocate a device only when that device is not allocated by any other process.
alphanumeric character:

An upper or lower case letter (A-Z, a-z), a dollar sign ($), imunderscore U, or
a decimal digit (0-9).
alternate key:
An optional key within the data records in an indexed file, used by VAX-ll
RMS to build an alternate index. See key (indexed files) and primary key.
American Standard Code for Information Interchange (ASCII):
A set of 8-bit binary numbers representing the alphabet, punctuation,
numerals, and other special symbols used in text representation and communications protocol.

G-3

Anclliary Control process (ACP):
A process that acts as an interface between user software and an I/O driver.
An ACP provides functions supplemental to those performed in the driver,
such as file and directory management. Three examples of ACPs are the Files11 ACP (F11ACP), the magnetic tape ACP (MTACP), and the networks ACP
(NETACP).
area:
Areas are VAX-11 RMS maintained regions of an indexed file. They allow a
user to specify placement and/or specific bucket sizes for particular portions
of a file. An area consists of any number of buckets and there may be from 1 to
255 areas in a file.
Argument Pointer:
General register 12 (RI2). By convention, AP contains the address of the base
of the argument list for procedures initiated using the CALL instructions.
ASCII:
American Standard Code for Information Interchange. ASCII is a seven-bitplus-parity code established by the American National Standards Institute tu
achieve compatibility among different computers and terminals.
assign a channel:
To establish the necessary software linkage between a user process and a
device unit before a user process can transfer any data to or from that device.
A user process requests the system to assign a channel and the system returns
a channel number.
asynchronous record operation:
A mode of record processing in which a user program can continue to execute
after issuing a record retrieval or storage request without having to wait for
the request to be fulfilled.
Asynchronous System Trap:
A software-simulated interrupt to a user-defined service routine. ASTs enable
a user process to be notified asynchronously with respect to its execution of
the occurrence of a specific event. If a user process has defined an AST routine
for an event, the system interrupts the process and executes the AST routine
when that event occurs. When the AST routine exits, the system resumes the
process at the point where it was interrupted.
Asynchronous System Trap level (ASTL VL):
A value kept in an internal processor register that is the highest access mode
for which an AST is pending. The AST does not occur until the current access
mode drops in priority (raises in numeric value) to a value greater than or
equal to ASTLVL. Thus, an AST for an access mode will not be serviced while
the processor is executing in a higher priority access mode.
authorization file:
See user authorization file.

G-4· Glossary

autodecrement indexed mode:
An indexed addressing mode in which the base operand specifier uses
autodecrement mode addressing.
autodecrement mode:
In autodecrement mode addressing, the contents of the selected register are
decremented, and the result'is used as the address of the actual operand for
the instruction. The contents of the register are decremented according to the
data type context of the register: 1 for byte, 2 for word, 4 for longword and
floating, 8 for quadword and double floating.
autoincrement deferred indexed mode:
An indexed addressing mode in which the base operand specifier uses autoincrement deferred mode addressing.
autoincrement deferred mode:
In autoincrement deferred mode addressing, the specified register contains
the address of a longword which contains the address of the actual operand.
The contents of the register are incremented by 4 (the number of bytes in a
longword).lf the PC is used as the register, this mode is called absolute mode.
autoincrement indexed mode:
An indexed addressing mode in which the base operand specifier uses autoincrement mode addressing.

autoincrement mode:
In autoincrement mode addressing, the contents of the specified register are
used as the address of the operand, then the contents of the register are incremented by the size of the operand.
balance set:
The set of all process working sets currently resident in physical memory. The
processes whose working sets are in the balance set have memory requirements that balance with available memory. The balance set is maintained by
the system swapper process.
base operand address:
The address of the base of a table or array referenced by index mode addressing.
base priority:
The process priority that the system assigns to a process when it is created.
The scheduler never schedules a process below its base priority. The base priority can be modified only by the system manager of the process itself.
base register:
A general register used to contain the address of the first entry in a list, table,
array or other data structure.
binding:
See linking.

G-5

bit string:
See variable-length bit fieldblock:
1. The smallest addressable unit of data that the specified device can transfer
in an I/O operation (512 contiguous bytes for most disk devices). 2. An arbitrary number of contiguous bytes used to store logically related status, control, or other processing information.

block I/O:
The set of VAX-ll RMS procedures that allow you direct access to the blocks
of a file regardless of the organization.
bootstrap block:
~ block in the index file on a system disk that contains a program that can
load the operating system into memory and start its execution.
branch access type:
An instruction attribute which indicates that the processor does not reference
an operand address, but that the operand is a branch displacement. The size of
the branch displacement is given by the data type of the operand.
branch mode:
In branch addressing mode, the instruction operand specifier is a signed byte
or word displacement. The displacement is added to the contents of the
updated PC (which is the address of the first byte beyond the displacement),
and the result is the branch address.

bucket:
A storage structure, consisting of from 1 to 32 blocks, used for building and
processing relative and indexed files. A bucket contains one or more records
or record cells. Buckets are the unit of contiguous transfer between VAX-ll
RMS buffers and the disk.
buffered I/O:
See system buffered I/O.

bug check:
The operating system's int6rnal diagnostic check_ The system logs the failure
and crashes the system.
byte:
A byte is eight contiguous bits starting on an addressable byte boundary_ Bits
are numbered from the right, 0 through 7, with bit 0 the low-order bit. When
interpreted arithmetically, a byte is a 2's complement integer with significance increasing from bits 0 through bit 6. Bit 7 is the sign bit. The value of
the signed integer is in the range -128 to 127 decimal_ When interpreted as an
unsigned integer, significance increases from bits 0 through 7 and the value of
the unsigned integer is in the range 0 to 255 decimal. A byte can be used to
store one ASCII character.

G-6· Glossary

cache memory:
A smaIl high-speed memory placed between slower main memory and the processor. A cache increases effective memory transfer rates and processor speed.
It contains copies,of data recently used by the processor, and fetches several
bytes of data from memory in anticipation that the processor will access the
next sequential series' of bytes.
Carrier Sense Multiple Ac:c:ess With Collision Detection (CSMA/CD):

-A distributed channel-allocation procedure in which every station can receive
the transmissions of all other stations. Each station awaits an idle channel
before transmitting, and each station can detect overlapping transmissions by
other stations.
CCITT:
The International Telegraph and Telephone Consultative Committee, the
technical committee of the International Tdecommunications Union (lTV),
which is responsible for the development of recommendations regardiI}g telecommunications, including data communications.

cell frame:
See stack frame.
cell instructions:
The processor instructions CALLG (Call Procedure with General Argument
List) and CALLS (Call Procedure with Stack Argument List).
cell stack:
The stack, and coilVentional stack structure, used during a procedure call.
Each access mode of each process context has one cell stack, and interrupt
service context has one cell stack.
channel:
A logical path connecting a user process to a physical device unit. A user process requests the operating system to assign a channel to a device so the process can transfer data to or from that device.
character:
A symbol represented by an ASCII code: See al~o alphanumeric character.
character string:
A contiguous set of bytes. A character string is identified by two attributes,
an address and a length. Its address is the address of the byte containing the
first character of the string. Subsequent characters are stored in bytes of
increasing addresses. The length is the number of characters in the string.
character string descriptor:
Aquadword data structure used for passing character' data (strings). The first
word of the quadword contains the length of the character string. The second
word can contain type information. The remaining IOngWord contains the
address of the string.

G·7
cluster:
1. A set of contiguous blocks that is the basic unit of space allocation of a
Files·ll disk volume. 2. A set of pages brought into memory in one paging
operation. 3. An event flag cluster. 4. A system configuration typically consisting of more than one VAX processor and one or more hierarchical storage controllers. To the user, the cluster appears as though it were one computer
system.
command:
An instruction, generally an English word, typed by he user, at a terminal or
included in a command file which requests the software monitoring a terminal
of reading a command file to perform some well-defined activity. For example, typing the COpy command requests the system to copy the contents of
one file into another file.
command file:
A file containing command strings. See also command procedure.
command interpreter:
Procedure-based system code that executes in supervisor mode in the context
of a process to receive, syntax check, and parse commands typed by the user at
a terminal or submitted in a command file.
command parameter:
The positional operand of a command delimited by spaces, such as a file specification, option or constant.
, command procedure:
A .file containing commands and data that the command interpreter can
accept in lieu of the user typing the commands individually on a terminal.
command string:
A line (or set of continued lines), normally terminated by typing the carriage
return key, containing a command and, optionally; information modifying the
command. A complete command string consists of a command, its qualifiers,
if any, and its parameters (file specifications, for example), if any, and their
qualifiers, .if'any.
common:
A FORTRAN term for a program section that contains only data.
common event flag cluster:
A set of 32 event flags that enables cooperating process to post event notification to each other. Common event flag clusters are created as they are needed.
A process can 9;ssociate with up to two common event flag clusters.

G-8 • Glossary

compatibility mode:
A mode of execution that enables the central processor to execute non-privileged PDP-ll instructions; The operating system supports compatibility mode
execution by providing an RSX-llM programming environment for an RSX11M task image. The operating system compatibility mode procedures reside
in the control region of the process executing a compatibility mode image. The
procedures intercept calls to the RSX-11M Executive and convert them to the
appropriate operating system functions.
condition:

An exception condition detected and declared by software. For example, see
failure exception mode.
condition codes:
Four bits in the Processor Status Word that indicate the results ofpreviously
executed instructions.
condition handler:
A procedure that a process wants the system to execute when an exception
condition occurs. When an exception condition occurs, the operating system
searches for a condition handler and, if found, initiates the handler immediately. The condition handler may perform some action to change the situation
that caused the exception condition and continue execution for the process
that incurred the exception condition. Condition handlers execute in the context of the process at the access mode of the code that incurred the exception
condition .
. condition value:
A 32-bit quantity that uniquely identifies an exception condition.
context:
The environment of an activity. See also process context, hardware context,
and software context.
context indexing:
The ability to index through a data structure automatically because the size of
the data type is known and used to determine the offset factor.
context switching:
Interrupting the activity in progress and switching to another activity. Context switching occurs as one process after another is scheduled for execution.
The operating system saves the interrupted process' hardware context in the
hardware process control block (PCB) using the Save Process Control instruction, and loads another process' hardware PCB into the hardware context
using the Load Process Context instruction, scheduling that process for execution.

G-9

continuation character:
A hyphen at the end of a command line signifying that the command string
continues on to the next command line.
console:
The manual control unit integrated into the central processor. The console
includes an LSI-11 microprocessor and a serial line interface connected to a
hard copy terminal. It enables the operator to start and stop the system, monitor system operation, and run diagnostics.
console terminal:
The hard copy terminal connected to the central processor console.
control region:
The highest-addressed half of per-process space (the PI region). Control
region virtual addresses refer to the process-related information used by the
system to control the process, such as: the kernel, executive, and supervisor
stacks: the permanent I/O channels, exception vectors, and dynamically used
system procedures (such as the command interpreter and RSX -11M programming environment compatibility mode procedures). The user stack is also normally found in the control region, although it can be reallocated elsewhere.
Control Region Base Register (PIBR):
The processor register, or the equivalent in a hardware process control block,
that contains the base virtual address of a process control region page table.
Control Region Length Register (PILR):
The processor register, or its equivalent in a hardware process control block,
that contains the number of non-existent page table entries for virtual pages
in'a process control region.
copy-on-reference:
A method used in memory management for sharing data until a process
accesses it, in which case it is copied before the access. Copy-on-reference
allows sharing of the initial values of a global section whose pages have read/
write access but contain pre-initialized data available to many processes.
counted string:
A data structure consisting of a byte-sized length followed by the string.
Although a counted string is not used as a procedure argument, it is a convenient representation in memory.
current access mode:
The processor access modes of the currently executing software. The Current
Mode field of the Processor Status Longword indicates the access mode of the
currently executing software.
cylinder:
The tracks at the same radius on all recording surfaces of a disk.

G-IO· Glossary

D_ floating (point) datum:
A floating point datum consisting of 8 contiguous bytes (64 bits) starting on
an arbitrary byte boundary. The value of the D_ floating datlim is in the
approximate range (+ or -) 0.29 x 10-}8 to 1.7 x 10 }8. The precision is
approximately one part in 255 or typically sixteen decimal digits.
data base:

1. All the occurrences of data described by a data base management system. 2.
A collection of related data structures.
data structure:

Any table, list, array, queue, or tree whose format and access conventions are
well-defined for reference by one or more images.

data type:
In general, the way in which bits are grouped and interpreted,. In reference to
the processor instructions, the data type of an operand identifies the size of
the operand and the significance of the bits in the operand. Operand data
types include: byte, word, longword, and quadword integer, floating and double floating, character string, packed decimal string, and variable-length bit
field.
deferred echo:

Refers to the fact that terminal echoing does not occur until a process is ready
to accept input entered by type ahead.

delta time:
A time value expressing an offset from the current date and time. Delta times
are always expressed in the system as negative numbers whose absolute value
is used as an offset from the current time.
demand zero page:

A page, typically of an image stack or buffer area, that is initialized to contain
all zeros when dynamically created in memory as a result of a page fault. This
feature eliminates the waste of disk space that would otherwise be required to
store blocks (pages) that contain only zeros.
descriptor:

A data structure used in calling sequences for passing argument types,
addresses and other optional information. See character string descriptor.
detached process:

A process that has no owner. The parent process of a tree of subprocesses.
Detached processes are created by the job controller when a user logs on the
system or when a batch job is initiated. Th~ job controller does not own the
user processes it creates; these processes are therefore detached.

G-ll
device:
The general name for any physical terminus or link connected to the processor
that is capable of receiving, storing, or transmitting data. Card readers, line
printers, and terminals are examples of record-oriented devices. Magnetic
tape devices and disk devices are examples of mass storage devices. Terminal
line interfaces and interprocessor links are examples of communications
devices.
device interrupt:
An interrupt received on interrupt priority level 16 through 23. Device interrupts can be requested only by devices, controllers, and memories.
device name:
The field in a file specification that identifies the device unit on which a file is
stored. Device names also include the mnemonics that identify an I/O
peripheral device in a data transfer request. A device name consists of a mnemonic followed followed by a controller identification letter (if applicable), followed by a unit number (if applicable), and ends with a colon (:).
device queue:
See spool queue.
device register:
A location in device controller logic used to request device functions (such as 1/
o transfers) and/or report status.
device unit:
One drive, and its controlling logic, of a mass storage device system. A mass
storage system can have several drives connected to it.
diagnostic:
A program that tests logic and reports any faults it detects.

direct I/O:
An I/O operation in which the system locks the pages containing the associated buffer in memory for the duration of the I/O operation. The I/O transfer
takes place directly from the process buffer. Contrast with system buffered 1/

o.
direct mapping cache:
A cache organization in which only one address comparison is needed to locate
any data in the cache because any block of main memory data can be placed in
only one possible position in the cache. Contrast with fully associative cache.
directory:
A file used to locate files on a volume that contains a list of the names (including type and version number) and their unique internal identifications.

G-I2· Glossary

directory name:
The field in a file specification that identifies the directory file in which a file
is listed. The directory name begins with a left bracket ([ or <) and ends with
a right bracket or ».

displacement deferred indexed mode:
An indexed addressing mode in which the base operand specifier lises displacement deferred mode addressing.
displacement deferred mode:
In displacement deferred mode addressing, the specifier extension is a byte,
word, or longword displacement. The displacement is sign extended to 32 bits
and added to a base address obtained from the specified register. The result is
the address of a longword which contains the address of the actual operand. If
the PC is used as the register, the updated contents of the PC are used as the
base address. The base address is the address of the first byte beyond the specifier extension.
displacement indexed mode:
An indexed addressing mode in which the base operand specifier uses pisplacement mode addressing.
displacement mode:
In displacement mode addressing, the specifier extension is a byte, word, or
longword displacement. The displacement is sign extended to 32 bits and
added to a base address obtained from the specified register. The result is the
address of the actual operand. If the PC is used as the register, the updated
contents of the PC are used as the base address. The base address is the
address of the first byte beyond the specifier extension.
drive:
The electro-mechanical unit of a mass storage device system on which a recording medium (disk cartridge, disk pack, or magnetic tape reel) is mounted.
driver:
the set of code that handles physical I/O to a device.
dynamic access:
A technique in which a program switches from one record access mode to
another while processing a file.
echo:
A terminal handling characteristic in which the characters typed by the terminal user on the keyboard are also displayed on the screen or printer.
effective address:
The address obtained after indirect or indexing modifications are calculated.

G-13

end node:
A topological description of a non-routing node (one that cannot forward
packets intended for other nodes). An end node supports only a single active
line.
entry mask:
A word whose bits represent the registers to be saved or restored on a subroutine or procedure call using the call and return instructions.
entry point:
A location that can be specified as the object of a call. It contains an entry
mask and exception enables known as the entry point mask.
equivalence name:
The string associated with a logical name in a logical name table. An equivalence name can be, for exampl~, a device name, another logical name, or a logical name concatenated with a portion of a file specification.
error logger:
A system process that empties the error log buffers and writes the error messages into the error file. Errors logged by the system include memory system
errors, device errors and timeouts, and interrupts with invalid vector
addresses.
escape sequence:
An escape is a transition from the normal mode of operation to a mode outside
the normal mode. An escape character is the code that indicates the transition
from normal to escape mode. An escape sequence refers to the set of character
combinations starting with an escape character that the terminal transmits
without interpretation to the software set up to handle escape sequences.
Ethernet:
A local area network protocol using a carrier sense multiple access with collision detection (CSMA/CD) scheme to arbitrate the use of a 10 megabits-persecond baseband coaxial cable.
event:
A change in process status or an indication of the occurrence of some activity
that concerns an individual process or cooperating processes. An incident
reported to the scheduler that affects a process' ability to execute. Events can
be synchronous with the process' execution (a wait request), or they can be
asynchronous (I/O completion). Some other events include: swapping; wake
request; page fault.
event flag:
A bit in an event flag cluster that can be set or cleared to indicate the occurrence of the event associated with that flag. Event flags are used to synchronize activities in a process or among many processes.

G-14· Glossary

event flag duster:
A set of 32 event flags which are used for event posting. Four clusters are
defined for each process: two process-local clusters, and two common event
flag clusters. Of the proCess-local flags, eight are reserved for system use.
exception:

An event detected by the hardware (other than an interrupt or jump, branch,
case, or call instruction) that changes the normal flow of instruction execution. An exception is always caused by the execution of an instruction or set of
instructions (whereas an interrupt is caused by an activity in the system independent of the current instruction). There are three types of hardware exceptions: traps, faults, and aborts. Examples are: attempts to execute a privileged
or reserved instruction, trace faults, compatibility mode faults, break-point
instruction execution, and arithmetic faults such as floating point overflow,
underflow, and divide by zero.

exception condition:
A hardware- or software-detected event other than an interrupt or jump,
branch, case, or cali instruction that changes the normal flow of instruction
execution.
exception dispatcher:
An operating system procedure that searches for a condition handler when an
exception condition occurs. If no exception handler is found for the exception
or condition, the image that incurred the exception is terminated.
exception enables:
See trap enables.
exception vector:
See vector.
executable image:
An image that is capable of being run in a process. When run, an executable
image is read from a file for execution in a process.
executive:
The generic name for the collection of procedures included in the operating
system software that provides the basic control and monitoring functions of
the operating system.
executive mode:
The second most privileged processor access m,.ode (mode 1). The record management services (RMS) and many of the operating system's programmed service procedures execute in executive mode.

G-15
exit:

An image exit is a rundown activity that occurs when image execution terminates either normally or abnormally. Image rundown activities include deassigning I/O channels and disassociation of common event flag clusters. Any
user- or system-specified exit handlers are called.
extended attribute block (XAB):
An RMS user data structure that contains additional file attributes beyond
those expressed in the file access block (FAB), such as boundary types (aligned
on cylinder, logical block number, virtual block number) and the protection
information.
extension:
The amount of space to allocate at the end of a file each time a sequential
write exceeds the allocated length of the file.
extent:
The contiguous area on a disk containing a file or a portion of a file. Consists
of one or more clusters.

F_ floating (point) datum:
A floating point datum consisting of 4 contiguous bytes (32 bits) starting on
an arbitrary byte boundary. The value of the F_ floating datum is in the
approximate range (+ or -) 0.29 x 10-38 to 1.7 X lQ-". The precision is
approximately one part in 223 or typically seven decimal digits.
failure exception mode:
A mode of execution selected by a process indicating that it wants an exception condition declared if an error occurs as the result of a system service call.
The normal mode is for he system service to return an error status code for
which the process must test.
fault:
A hardware exception condition that occurs in the middle of an instruction
and that leaves the registers and memory in a consistent state, such that elimination of the fault and restarting the instruction will give correct results.
field:
1. See variable-length bit field. 2. A set of contiguous bytes in a logical record.
file:
An organized collection of related items (records) maintained in an accessible
storage area, such as disk or tape.
file access block (FAB):
An RMS user data structure that represents a request for data operations
related to the file as a whole, such as OPEN, CWSE, or CREATE.
•

G-16' Glossary

file header:
A block in the index file describing a file on a Files-11 disk structure_ The file
header identifies the locations of the file's extents_ There is a file header for
every file on the disk
file name:
The field preceding a file type in a file specification that contains a 1- to 9character logical name for a file_
filename extension:
See file type.
file organization:
The physical arrangement of data in the file. You select the specific organization from those offered by VAX-ll RMS, based on your individual needs for
efficient data storage and retrieval. See indexed file organization, relative file
organization, and sequential file organization.

FILES-ll:
The name of the on-disk structure used by the RSX-ll, lAS, and VAX[VMS
operating systems. Volumes created under this structure are transportable
between these operating systems.

file specificlftion:
A unique name for a file on a mass storage medium. It identifies the node, the
device, the directory name, the file name, the file type, and the version number under which a file is stored.
file system:
A method of recording, cataloging, and accessing files on a volume_
file type:
The field in a file specification that is preceded by a period or dot (.) and consists of a zero- to three-character type identification. By convention, the type
identifies a generic class of files that have the same use or characteristics, such
as ASCII text files, binary object files, etc.
fixed control area:
An area associated with a variable length record available for controlling or
assisting. record access operations. Typical uses include line numbers and
printer format control information.
fixed.length record format:
Property of a file in which all records are of the same size. This format provides simplicity in determining the exact location of a record in the file and
eliminates the need to prefix a record size field to each record.

G-17
floating (point) datum:
A numeric data type in which the number is represented by a fraction (less
than 1 and greater than or equal to Ih) multiplied by 2 raised to a power_
There are four floating point data types: F_ floating (4 bytes), D_ floating
(8 bytes), G_ floating (8 bytes), and IL- floating (16 bytes).
foreign volume:
Any volume other than a Files-11 formatted volume which mayor may not be
file structured.
fork process:
A dynamically created system process such as a process that executes device
driver code or the timer process. Fork processes have minimal context. Fork
processes are scheduled by the hardware rather than by the software. The
timer process is dispatched directly by software interrupt. I/O driver processes are dispatched by a fork dispatcher. fork processes execute at software
interrupt levels and are dispatched for execution immediately. Fork processes
remain resident until they terminate.
frame pointer:
General register 13 (R13). By convention, FP contains the base address of the
most recent call frame on the stack.
fully associative cache:
A cache organization in which any block of data from main memory can be
placed anywhere in the cache. Address comparison must take place against
each block in the cache to find any particular block. Contrast with direct mapping cache_

G_ floating (point) datum:
A floating point datum consisting of 8 contiguous bytes (64 bits) starting on
an arbitrary byte boundary. The value of the G_ floating datum is in the
approximate range (+ or 1) 0.56 x 10-308 to 0_9 X 10308 • The precision is
approximately one part in 2 n or typically fifteen decimal digits.
gateway:
A module, or set of modules, that transforms the conventions of one network
into the conventions of another.
general register:
Any of the sixteen 32-bit registers used as the primary operands of the native
mode instructions. The general registers include 12 general purpose registers
which can be used as accumulators, as counters, and as pointers to locations in
main memory, and the Frame Pointer (FP), Argument Pointer (AP), Stack
Pointer (SP), and Program Counter (PC) registers.
generic device name:
A device name that identifies the type of device but not a particular unit, a
device name in which the specific controller and/or unit number is omitted.

G-18· Glossary

giga:
Metric term used to represent the number 1 followed by nine zeros.
global page table:
The page table containing the master page table entries for global sections.
global section:
A data structure (e.g., FORTRAN global common) or shareable image section
potentially available to all processes in the system. Access is protected by privilege and/or group number of the me.
global symbol:
A symbol defined in a module that is potentially available for reference by
another module. The linker receives (matches references with definitions)
global symbols. Contrast with local symbol.
global symbol table (GST):
In a library, an index of strongly defined global symbols used to access the
modules defining the global symbols. The linker will also put global symbol
tables into an image; For example, the linker appends a global symbol table to
executable images that are intended to run under the symbolic debugger, and
it appends a global symbol table to all shareable images.
group:
1. A set of users who have special access privileges to each oth~r's directories
and files within those directories (unless protected otherwise), as in the context "system, owner, group, world," where group refers to all members of a
particular owner's group. 2. A set of jobs (processes and their subprocesses)
who have access privileges to a group's common event flags and logical name
tables, and.may have mutual process controlling privileges, such as scheduling,
hibernation, etc.
group number:
The first number in a User Identification Code (mc).
" - floating (point) datum:
A floating point datum consisting of 16 contiguous bytes (128 bits) starting on
an arbitrary byte boundary. The value of the H_ floating datum is in the
approximate range (+ or -) 0.84 x lQ-4932 to 0.59 X 104932 • The precision is
approximately one part in 2112 or typically 33 decimal digits.

G·19

hardware context:
The values contained in the following registers while a process is executing
the Program Counter (PC), the Processor Status Longword (PSL), the 14 gen·
eral registers (RO through R13), the four processor registers (POBR, POLP,
PIBR, and PILR) that describe the process virtual address space, the Stack
Pointer (SP) for the current access mode in which the processor is executing;
plus the contents to be loaded in the Stack Pointer for every access mode other
than the current access mode. While a process is executing, its hardware con·
text is continually being updated by the processor. While a process is not exe·
cuting, its hardware context is stored in its hardware PCB.
hierarchical network:
A computer network in which computers perform process·control functions at
several levels. The computers at each level are specially suited to perform the
functions of that level. In a laboratory application, for example, computers at
the lowest level collect data, which they transmit to the computers at th next
highest level. Here, the collected data is reduced for analysis, and sent up to
th next level of the hierarchical configuration.
hardware process control block (PCB):
A data structure known to the processor that contains the hardware context
when a process is not executing. A process' hardware PCB resides in its pro·
cess header.
hibernation:
A state in which a process is inactive, but known to the system with all of its
current status. A hibernating process becomes active again when a wake
request is issued. It can schedule a wake request before hibernating, or
another process can issue its wake request. A hibernating process also
becomes active for the time sufficient to service any AST it may receive while
it is hibernating. Contrast with suspension.
home block:
A block in the index file that contains the volume identification, such as vol·
ume label and protection.
image:
An image consists of procedures and data that have been bound together by
the linker. There are three types of images, executable, shareable, and system.
image activator:
A set of system procedures that prepare an image for execution. The image
activator establishes the memory management data structures required both
to map the image's virtual pages to physical pages and to perform paging.
image exit:
See exit.

image I/O segment:
That portion of the control region that contains the RMS internal file access
blocks (IFAB) and I/O buffers for the image currently being executed by a process.
image name:
The file name of the file in which an image is stored.
image privileges:
The privileges assigned to an image when it is linked. See process privileges.
image section (isect):
A group of program sections (isects) with the same attributes (such as readonly access, read/write access, absolute, relocatable, etc.) that is the unit of
virtual memory allocation for an image.
immediate mode:
In immediate mode addressing, the PC is used as the register in autoincrement
mode addressing.
index:
The structure which allows retrieval of records in an indexed file by key value.
See key (indexed files).
index file:
The file on a Files-11 volume that contains the access information for all files
on the volume and enables the operating system to identify and access the volume.
index file bit map:
A table in the index file of a Files-11 volume that indicates which file headers
are in use.
index register:
A register used to contain an address offset.
indexed addressing mode:
In indexed mode addressing, two registers are used to determine the actual
instruction operand: an index register and a base operand specifier. The contents of the index register are used as an index (offset) into a table or array.
The base operand specifier supplies the base address of the array (the base
operand address or BOA). The address of the actual operand is calculated by
multiplying the contents of the index register by the size (in bytes) of the
actual operand and adding the result to the base operand address. The addressing modes resulting from index mode addressing are formed by adding the suffix "indexed" to the addressing mode of the base operand specifier: register
deferred indexed, autoincrement indexed, autoincrement deferred indexed
(or absolute indexed), autodecrement indexed, displacement indexed, and displacement deferred indexed.

G-21

indexed file organization:
A file organization which allows random retrieval of records by key values and
sequential retrieval of records in sorted order by key value_ See key (indexed
files).
indirect command file:
See command procedure.
input stream:
The source of commands and data. One of: the user's terminal, the batch
stream, or an indirect command file.
instruction buffer:
A buffer in the processor used to contain bytes of the instruction cutrently
being decoded and to pre-fetch instructions in the instruction stream. The
control logic continuously fetches data from memory to keep the buffer full.
interleaving:
Assigning consecutive physical memory address alternately between two memory controllers.
interlocked:
The property of a read followed by a write to the same datum with no possibility of an intervening reference by a second processor or I/O device. Examples
are the Branch on Bit interlocked and Add Aligned Work Interlocked instructions.
interprocess communication facility:
A common event flag, mailbox, or global section used to pass information
between two or more processes.
interrecord gap:
A blank space deliberately placed between data records on the recording Sutface of a magnetic tape.
interrupt:
An event other than an exception or branch, jump, case, or call instruction
that changes the normal flow of instruction execution. Interrupts are generally external to the process executing when the interrupt occurs. See also
device interrupt, software interrupt, and urgent interrupt.
interrupt priority level (IPL):
The interrupt level at which the processor executes when an interrupt is generated. There are 31 possible interrupt priority levels. IPL 1 is lowest, 31
highest. The levels arbitrate contention for processor service. For example, a
device cannot interrupt the processor if the processor is currently executing at
an interrupt priority level greater than the interrupt priority level of the
device's interrupt service routine.
interrupt service routine:
The routine executed when a device interrupt occurs.

G-22 • Glossary

interrupt stack:
The system-wide stack used when executing in interrupt service context. At
any time, the processor is either in a process context executing in user, supervisor, executive or kernel mode, or in system-wide interrupt service context
operating with kernel privileges, as indicated by the interrupt st,ack and current mode bits in the PSL. The interrupt stack is not context switched.
interrupt stack pointer:
The stack pointer for the interrupt stack. Unlike the stack pointers for process context stacks, which are stored in the hardware PCB, the interrupt stack
pointer is stored in an internal register.
interrupt vector:
See vector.
I/O driver:
See driver.

I/O function:
An I/O operation that is interpreted by the operating system and typically
results in one or more physical I/O operations.

I/O function code:
A 6-bit value specified in a Queue I/O Request system service that describes
the particular I/O operation to performed (e.g., read, write, rewind).
I/O function modifier:
A lO-bit value specified in a Queue I/O Request system service that modifies
an I/O function code (e.g., read terminal input no echo).
I/O lockdown:
The state of a page such that it cannot be paged or swapped out of memory
until any I/O in progress to that page is completed.
I/O rundown:
An operating system function in which the system clears up any I/O in progress when an image exits.
I/O space:
The region of physical address space that contains the configuration registers,
and device control/status and data registers.
I/O status block:
A data structure associated with the Queue I/O Request system service. This
service optionally returns a status code, number of bytes transferred, and
device- and function-dependent information in an I/O status block. It is not
returned from the service call; but filled in when the I/O request completes.

G-23

ISO Reference Model:
The International Standards Organization Reference Model for Open System
Interconnection, ISO draft proposal DP7498. A proposed international standard for network architectures that defines a seven-layer model, specifying
services and protocols for each layer.
job:
1. A job is the accounting unit equivalent to a process and the collection of all
the subprocesses, if any, that it and its subprocesses create. Jobs are classified
as batch and interactive. For example, the job controller creates an interactive
job to handle a user's requests when the user logs onto the system and it creates a batch job when the symbiont manager passes a command input file to it.
2. A print job.
job controller:
The system process that establishes a job's proces~ context, starts a process
running the WGIN image for the job, maintains the accounting record for the
job, manages symbionts, and terminates a process and its subprocesses.

job queue:
A list of files that a process has supplied for processing by a specific device,
for example, a line printer.
kernel mode:
The most privileged processor access mode (mode D). The operating system's
most privileged services, such as 1/0 drivers and the pager, run in kernel
mode.
key

indexed files: A character string, a packed decimal number, a 2- or 4-byte
unsigned binary number, or a 2- or 4-byte signed integer within each data
record in an indexed file. You define the length and location within the
records; VAX-ll RMS used the key to build an index. See primary key, alternate key, and random access by key value.
relative files: The relative record number of each data record in a data file;
VAX-ll RMS uses the relative record numbers to identify and access data
records in a relative file in random access mode. See relative record number.
lexical function:
A command language construct that the command interpreter evaluates and
substitutes before it performs expression analysis on a command string. Lexical functions return information about the current process, such as VIC or
default directory; and about character strings, such as length or substring locations.
librarian:
A program that allows the user to create, update, modify, list, and maintain
object library, image library, and assembler macro library files.

G-24 • Glossary

library file:
A direct access file containing one or more modules of the same module type.
limit:
The size or number of given items requiring system resources (such as mailboxes, locked pages, I/O requests, open files, etc.) that a job is allowed to have
at anyone time during execution, as specified by the system manager in the
user authorization file. See also quota.
line number:
A number used to identify a line of text in a file processed by a text editor.
linker:
A program that reads one or more object files created by language processors
and produces an executable image file, a shareable image file, or a system
image file.
linking:
The resolution of external references between object modules used to create
an image, the acquisition of referenced library routines, service entry points,
and data for the image, and the assignment of virtual addresses to components
of an image.
literal mode:
In literal mode addressing, the instruction operand is a constant whose value
is expressed in a 6-bit fidd of the instruction. If the operand data type is byte,
word, longword, quadword, or octaword, the operand is zero-extended and
can express values in the range 0 through 63 (decimal). If the Operand data
type is F _, D_, G_, or II-- floating, the 6-bit fidd is composed of two 3bit fidds, one for the exponent and the other for the fraction. The operand is
extended to F_, D_, G_, or II-- floating format.
locality:
See program locality.
local symbol:
A symbol meaningful only to the module that defines it. Symbols not identified to a language processor as global symbols are considered to be local symbols. A language processor resolves (matches references with definitions) local
symbols. They are not known to the linker and cannot be made available to
another object module. They can, however, be passed through the linker to
the symbolic debugger. Contrast with global symbol.
locate-mode:
Technique used for a record input operation in which the data records are not
copies from the I/O buffer. See move mode.
locking a page in memory:
M~ing a page in' an image indigible for either paging or swapping. A page
stays locked in memory until it is specifically unlocked.

G-25

locking a page in the working set:
Making a page in an image ineligible for paging out of the working set for the
image_ The page can be swapped when the process is swapped. A page stays
locked in a working set until it is specifically unlocked.
logical block number:
A number used to identify a block on a mass storage device. The number is a
volume-relative address rather than the physical (device-oriented) address or
its virtual (file-relative) address. The flocks that constitute the volume are
labeled sequentially starting with logical block o.
logical I/O function:
A set of I/O operations (e.g., read and write logical block) that allow restricted
direct access to device level I/O operations using logical block addresses.
logical name:
A user-specified name for any portion or all of a file specification. For example, the logical name INPUT can be assigned to a terminal device from which a
program reads data entered by a user. Logical name assignments are maintained in logical name tables for each process, each group, and the system. A
logical name can be created and assigned a value permanently or dynamically.
logical name table:
A table that contains a seat of logical names and their equivalence names for a
particular process, a particular group, or the system.
logical I/O functions:
A set of I/O functions that allow restricted direct access to device level I/O
operations.
logical record:
A group of related fields treated as a unit.
longword:
Four contiguous bytes (32 bits) starting on an addressable byte boundary. bits
are numbered from right to left, 0 through 31. The address of the longword is
the address of the byte containing bit o. When interpreted arithmetically, a
longword is a 2's complement integer with significance increasing from bit 0
through bit 30. When interpreted as a signed integer, bit 31 is the sign bit.
The value of the signed integer is in the range -2,147,483,658 to
2,147,483,647. When interpreted as an unsigned integer, significance
increases from bit 0 to bit 31. The value of the unsigned integer is in the range
othrough 4,294,967,25/5.
macro:

A statement that requests a language processor to generate a predefined set of
instructions.

G-26 • Glossary

mailbox:
A software data structure that is treated as a record-oriented device for general interprocess communication. Communication using a mailbox is similar
to other forms of device-independent I/O. Senders perform a write to a mailbox, the receiver performs a read from that mailbox. Some system-wide mailboxes are defined: the error logger and OPCOM read from system-wide
mailboxes.
main memory:
See main memory.
mapping window:
A subset of the retrieval information for a file that is used to translate virtual
block numbers to logical block numbers.
mass storage device:
A device capable of reading and writing data on mass storage media such as
disk pack or a magnetic tape reel.
member number:
The second number in a user identification code that uniquely identifies that
code.
memory management:
The system functions that include the hardware a page mapping and protection and the operating system's image activator and pager.
Memory Mapping Enable (MME):
A bit in a processor register that governs address translation.
modify access type:
The specified operand of an instruction or procedure is read, and potentially
modified and written, during that instruction's or procedure's execution.
module:
1. A portion of a program or program library, as in a source module, ob;ect
module, or image module. 2. A board, usually made of plastic covered with an
electrical conductor, on which logic devices (such as transistors, resistors, and
memory chips) are mounted, and circuits connecting these devices are etched,
as in a logic module.
Monitor Console Routine (MCR):
The command interpretelC in an RSX -11 system.
mount a volume:
1. To logically associate a volume with the physical unit on which it is loaded
(an activity accomplished by system software at the request of an operator). 2.
To load or place a magnetic tape or disk pack on a drive and place the drive
online (an activity accomplished by a system operator).

G-27

move mode:
Technique used for a record transfer in which the data records are copied
between the I/O buffer and your program buffer for calculations or operations
on the record. See locate mode.
multiplex:
Simultaneously transmit or receive two or more datastreams on a single channel.
mutex:
A semaphore that is used to control exclusive access to a region of code that
can share a data structure or other resource. The mutex (mutual exclusion)
semaphore ensures that only process at a time has access to the region of code.
name block (NAM):
An RMS user data structure that contains supplementary information used in
parsing the specifications.
native image:
An image whose instructions are executed in native mode.
native mode:
processor's primary execution mode in which the programmed instructions
are interpreted as byte-signed, variable-length instructions that operate on
byte, word, longword, quadword, and octaword integer, F_, D_, G_, and
IL floating format, character string, packed decimal, and variable-length
bit field data. The instruction execution mode other than compatibility mode.
network:
A collection of interconnected individual computer systems.
nibble:
The low-order or high-order four bits of a byte.
node:
An individual computer system in a network.
null process:
A small system process that is the lowest priority process in the system and
takes one entire priority class. One function of the null process is to accumulate idle processor time.
numeric string:
A contiguous sequence of bytes representing up to 31 decimal digits (one per
byte) and possibly a sign. The numeric string is specified by its lowest
addressed location, its length, and its sign representation.
object module:
The binary output of a language processor such as the assembler or a compiler,
which is used as input to the linker.

G-28' Glossary

object time system (OTS):
See Run Time Procedure Library.
octaword:
Sixteen contiguous bytes (128 bits) starting on an addressable byte boundary.
Bits are numbered from right to left, 0 to 127. An octaword is identified by
the address of the byte containing the low-order bit (0).
offset:
A fixed displacement from the beginning of a data structure. system offsets
for terms within a data structure normally have an associated symbolic name
used instead of the numeric displacement. Where symbols are defined, programmers always reference the symbolic names in a data structure instead of
using the numeric displacement.
opcode:
The pattern of bits within an instruction that specify the operations to be performed.
operand specifier:
The pattern of bits in an instruction that include the addressing mode, a register and/or displacement, which, taken together, identify an instruction operand.
operand specifier type:
The access type and data type of an instruction's operand(s). For example, the
test instructions are of read access type, since they only read the value of the
operand. The operand can be of byte, word, or longword data type, depending
on whether the opcode is for the TSTB (test byte), TSTW (test word), or TSTL
(test longword) instruction.
Operator Communication Manager (OPCOM):
A system process that is always active. OPCOM receives input from a process
that wants to inform an operation of a particular status or condition, passes a
message to the operator, and tracks, the message.
operator's console:
Any terminal identified as a terminal attended by a system operator.
owner:
In the context "system, owner, group, world," an owner is the particular member (of a group) to which a file, global section, mailbox, or event flag cluster
belongs.
owner process:
The process (with the exception of the job controller) or subprocess that created a subprocess.

G-29

packed decimal:
A method of representing a decimal number by storing a pair of decimal digits
in one byte, taking advantage of the fact that only four bits are required to
represent the numbers 0 through 9_
packed decimal string:
A contiguous sequence of up to 16 bytes interpreted as a string of nibbles.
Each nibble represents a digit except the low-order nibble of the highest
addressed byte, which represents the sign. The packed decimal staring is specified by its lowest addressed location and the number of digits.
packet:
A unit of data to be routed from a source node to a destination I:).ode. When
stripped of its route header and passed to the End-to-End Communication
Layer, a packet becomes a datagram.
packet level:
Level 3 of the CCITT X.25 recommendation, which defines the packet format
and control procedures for the exchange of packets.
page:
1. A set of 512 contiguous byte locations used as the unit of memory mapping
and protection. 2. The data between the beginning of file and a page marker,
between two markers, or between a marker and the end of file.
page fault:
An exception generated by a reference to a page which is not mapped into a
working set.
page fault cluster size:
The number of pages read in on a page fault.
page frame number (PFN):
The address of the first byte of a page in physical memory. The high-order 21
bits of the physical address of the base of a page.
page marker:
A character or characters (generaIIy a form feed) that separates pages in a file
that is processed by a text editor.
pager:
A set of kernel mode procedures that executes as the result of a page fault. The
pager makes the page for which the fault occurred available in physical memory so that the image can continue execution. The pager and the image activator provide the operating system's memory management functions.

G-30· Glossary

page table entry (PTE):
The data structure that identifies the location and status of a page of virtual
address space. When a virtual page is in memory, the PTE contains the page
frame number needed to map the virtual page to a physical page. When it is
not in memory, the page table entry contains the information needed to locate
the page on secondary storage (disk).
paging:
The action of bringing pages of an executing process into physical memory
when referenced. When a process executes, all of its pages are said to reside in
virtual memory. Only the actively used pages, however, need to reside in physical memory. The remaining pages can reside on disk until they are needed in
physical memory. In this system, a process is paged only when it references
more pages than it is allowed to have in its working set. When the process
refers to a page not in its working set, a page fault occurs. This causes the
operating system's pager to read in the referenced page if it is on disk (and,
optionally, other related pages depending on a cluster factor), replacing the
least recently faulted pages as needed. A process pages only against itself.
parameter:
See command parameter.
per-process address space:
See process address space
physical address:
The address used by hardware to identify a location in physical memory or on
directly addressable secondary storage devices such as a disk. A physical memory address consists of a page frame number and the number of a byte within
the page. A physical disk block address consists of a cylinder or track and sector number.
physical address space:
The set of all possible 3D-bit physical addresses that can be used to refer to
locations in memory (memory space) or device registers (I/O space).
physical block:
A block on a mass storage device referred to by its physical (device-oriented)
address rather than a logical (volume-relative) or virtual (file-relative) address.
physical I/O functions:
A set of I/O functions that allow access to all device level I/O operations except
maintenance mode.
physical memory:
the memory modules connected to the SBI that are used to store: 1) instructions that the processor can directly fetch and execute, and 2) any other data
that a processor is instructed to manipulate. Also called main memory.

G-31

position-dependent code:
Code that can execute properly only in the locations in virtual address space
that are assigned to it by the linker.
position-independent code:
Code that can execute properly without modification wherever it is located in
virtual address space, even if its location is changed after it has been linked.
Generally, this code uses addressing modes that form an effective address relative to the PC.
primary key:
The mandatory key within the data records of an indexed file, used by VAX11 RMS to determine the placement of records within the file and to build the
primary index. See key (indexed files) and alternate key.
primary vector:
A location that contains the starling address of a condition handler to be executed when an exception condition occurs. If a primary vector is declared,
that condition handler is the first handler to be executed.
private section:
An image section of a process that is not shareable among processes. See also
global section.
privilege:
See process privilege, user privilege, and image privilege.
privileged instructions:
In general, any instructions intended for use by the operating system or privileged system programs. In particular, instructions that the processor will not
execute unless the current access mode is kernel mode (e.g., HALT, SVPCTX,
LDPCTX, MTPR, and MFPR).
procedure:
1. A routine entered via a Call instruction. 2. See command procedure.
process:
The basic entity scheduled by the system software that provides the context
in which an image executes. A process consists of an address space and both
hardware and software context.
process address space:
See process space.
process context:
The hardware and software contexts of a process.
process control block (PCB):
A data structure used to contain process context. The hardware PCB contains
the hardware context. The software PCB contains the software context,
which includes a pointer to the hardware PCB.

G-32' Glossary

process header:
A data structure that contains the hardware PCB, accounting and quota information, process section table, working set list, and the page tables defining
the virtual layout of the process.
.
process header slots:
That portion of the system address space in which the system stores the process headers for the processes in the balance set. The number of process
header slots in the system determines the number of processes that can be in
the balance seta at anyone time.
process identification (PID):
The operating system's unique 32-bit binary value assigned to a process.
process I/O segment:
That portion of a process control region that contains the process permanent
RMS internal file access block for each open file, and the I/O buffers, including the command interpreter's command buffer and command descriptors.
process name:
A 1- to 15-character ASCII string that can be used to identify processes executing under the same group number,
processor register:
A part of the processor used by the operating system software to control the
execution states of the computer system. The include the system base and length registers, the program and control region base and length registers, the
system control block base register, the software interrupt request register,
and many more.
Processor Status Longword (PSL):
A system programmed processor register consisting of a word of privileged
processor status and the PSW. the privileged processor status information
includes: the current IPL (interrupt priority level), the previous access mode,
the current access mode, the interrupt stack bit, the trace fault pending bit,
and the compatibility mode bit.
Processor Status Word (PSW):
The low-order word of the Processor Status Longword. Processor status information includes the condition codes (carry, overflow, zero, negative), the
arithmetic trap enable bits (integer overflow, floating underflow), and the
trace enable bit.
•
process page tables:
The page tables used to describe process virtual memory.

G-33

process priority:
The priority assigned to a process for scheduling purposes_ The operating system recognizes 32 levels of process priority, where 0 is low and 31 high_ Levels
16 through 31 re used for time-critical processes. The system does not modify
the priority of a time-critical process (although the system manager or process
itself may). Levels 0 through 15 are used for normal processes. The system
may temporarily increase he priority of a normal process based on the activity
of the process.
process privileges:
The privileges granted to a process by the system, which are a combination of
user privileges and image privileges. They include, for example, the privilege
to affect other processes associated with the same group as the user's group,
affect any process in the system regardless of VIC, set process swap mode,
create permanent event flag clusters, create another process, create a mailbox,
and perform direct I/O t<.> a file-structured device.
process section:
See private section.
process space:
The lowest-addressed half of virtual address space, where per-process instructions and data reside. Process space is divided into a program region and a
control region.
Program Counter (PC):
General register 15 (R15). At the beginning of an instruction's execution, the
PC normally contains the address of a location in memory from which the processor will fetch the next instruction it will execute.
program locality:
A characteristic of a program that indicates how close or far apart the references to locations in virtual memory are over time. A program with a high
degree of locality does not refer to many widely scattered virtual addresses in
a short period of time.
programmer number:
See member number.
program region:
The lowest-addressed half of process address space (PO space). The program
region contains the image currently being executed by the process and other
user code called by the image.
Program region Base Register (POBR):
The processor register, or its equivalent in a hardware process control block,
that contains the base virtual address of the page table entry for virtual page
number 0 in a process program region.

G-34· Glossary

Program region Length Register (POLR):
The processor register, or its equivalent in a hardware process control block,
that contains the number of entries in the page table for a process program
region.
program section (psect):
A portion of a program with a given protection and set of storage management
attributes. Program sections that have the same attributes are gathered
together by the linker to form an image section.
project number:
See group number or account number.

pure code:
See re-entrant code.
quadword:
Eight contiguous bytes (64 bits) starting on an addressable byte boundary.
Bits are numbered from right to left, 0 to 63. A quadword is identified by the
address of the byte containing the low-order bit (bit 0). When interpreted
arithmetically, a quadword is a 2's complement integer with significance
increasing from bit 0 to bit 62. Bit 63 is used as the sign bit. The value of the
integer is in the range _263 to 2 63 -1.
qualifier:
A portion of a command string that modifies a command verb or command
parameter by selecting one of several options. A qualifier, if present, follows
the command verb or parameter to which it applies and is in the formal "/
qualifier option." For example, in the command string "PRINT filename/
COPIES:3," the COPIES qualifier indicates that the user wants three copies of
a given file printed.
queue:
1. n. A circular, doubly-linked list. See system queues. v. To make an entry in
a list or table, perhaps using the INSQUE instruction. 2. See job queue.
queue priority:
The priority assigned to a job placed in a spooler queue or a batch queue.
quota:
The total amount of a system resource, such as CPU time, that a job is allowed
to use in an accounting period, as specified by the system manager in the user
authorization file. See also limit.
random access by key:
Indexed files only: Retrieval of a data record in an indexed file by either a
primary or alternate key within the data record. See key (indexed files).

G-35

random access by record's file address:
The retrieval of a record by its unique address, which is provided to the program by RMS_ This method of access is the only means of randomly accessing
a sequentially organized file containing variable length records.
random access by relative record number:
Retrieval of a record by its relative record number. See relative record number. For relative files, random access by relative record number is synonymous
with random access by key. See random access by key (relative files only).
read access type:
An instruction or procedure operand attribute indicating that the specified
operand is only read during instruction or procedure execution.
record:
A set of related data that your program treats as a unit.
record access block (RAB):
An RMS user data structure that represents a request for a record access
stream. A RAB relates to operations on the records within a file, such as
UPDATE, DELETE, or GET.
record access mode:
The method used in RMS for retrieving and storing records in a file. One of
three methods: sequential, random, and record's file address.
record blocking:
The technique of grouping multiple records into a single block. On magnetic
tape, an IRG is placed after the block rather than after each record. This technique reduces the number of I/O transfers required to read or write the data,
and, in addition (for magnetic tape), increases the amount of usable storage
area. Record blocking also applies to disk files.
record cell:
A fixed-length area in a relative file that can contain a record. The concept of
fixed-length record cells lets VAX-ll RMS directly calculate the record's
actual position in the file.
record format:
The way a record physically appears on the recording surface of the storage
medium. The record format defines the method for determining record length.
record length:
The size of a record; that is, the number of bytes in a record.
record locking:
A facility that prevents access to a record by more than one record stream or
process until the initiating record stream or process releases the record.

G-36· Glossary

Record Management Services:
A set of operating system procedures that are called by programs to process
files and records within files. RMS allows programs to issue READ and
WRITE requests at the record level (record I/O) as well as read and write
blocks (block I/O). RMS is an integral part of the system software. RMS ptocedures run in executive mode.
record-oriented device:
A device such as a terminal, line printer, or card reader, on which the largest
unit of data a program can access in one I/O operation is the device's physical
record.
record's file address:
The unique address of a record in a file, which is returned by RMS whenever a
record is accessed, that allows records in disk files to be accessed randomly
regardless of file organization. This address is valid only for the life of the file.
If an indexed file is reorganized, then the RFA of each record will typically
change.
re-entrant code:
Code that is never modified during execution. It is possible to let many users
share the same copy of a procedure or program written as re-entrant code.
register:
A storage location in hardware logic other than main memory. See also general
register, processor register, and device register.
register deferred indexed mode:
An indexed addressing mode in which the base operand specifier uses register
deferred mode addressing.
register mode:
In register mode addressing, the contents of the specified register are used as
the actual instruction operand.
relative file organization:
The arrangement of records in a file where each record occupies a cell of equal
length within a bucket. Each cell is assigned a successive number, called a relative record number, which represents the cell's position relative to the beginning of the file.
relative record number:
An identification number used to specify the position of a record cell relative
to the beginning of the file, used as the key during random access by key mode
to relative files.
remote node:
to a node, any other network node.

G-37

resource:
A physical part of the computer system such as a device or memory, or an interlocked data structure such as a mutex. Quotas and limits control the use of
physical resources.
resource wait mode:
An execution state in which a process indicates that it will wait until a system
resource becomes available when it issues a service request requiring a
resource. If a process wants notification when a resource is not available, it
can disable resource wait mode during program execution.
return status code:
See status code.

RMS-ll:
A set of routines which is linked with compatibility mode programs, and provides similar functional capabilities to VAX-ll RMS. The file organizations
and record formats used by RMS-11 are identical to those of VAX-11 RMS.
route through:
the process by which one or more intermediary node in the path between a
source node and a destination node directs packats from the source node to
the destination node. Routing nodes permit route-through Also called
packet switching.
Run Time Library Procedure:
The collection of procedures available to native mode images at run time.
These library procedures (such as trigonometric functions, etc.) are common
to all native mode images, regardless of the language processor used to compile
or assemble the program.
scatter/gather:
The ability to transfer in one I/O operation data from noncontiguous pages in
memory to contiguous blocks on disk, or data from contiguous blocks on disk
to noncontiguous pages in memory.
secondary storage:
Random access mass storage.

secondary vector:
A location that identifies the starting address of a condition handler to be executed when a condition occurs and the primary vector contains zero or the
handler to which the primary vector points chooses not to handle the condition.

G-38· Glossary

section:
A·portion of process virtual memory that has common memory management
attributes (protection, access, cluster factor, etc.). It is created from an image
section, a disk file,or as the result of a Create Virtual Address Space system
service. See global section, private section, image section, and program section.
self-relative queue:
A circularly linked list whose forward and backward links use the address of
the entry in which they occur as the base address for the link displacement to
the linked entry. Contrast with absolute addresses used to link a queue.
sequential file organization:
A file organization in which records appear in the order in which they were
originally written. The records can be fixed length or variable length.
sequential record access mode:
Record storage or retrieval which starts at a designated point in the file and
continues in one-after-the-other fashion through the file. That is, records are
accessed in the order in which they physically appear in the file.
server:
a module or set of modules in a layer that performs a well-defined service, like
remote file access or gateway communication, on behalf of another module.
shareable image:

An image that has all of its internal references resolved, but which must be
linked with an object module(s} to produce an executable image. A sharable
image cannot be executed. A shareable image file can be used to contain a
library of routines. A shareable image can be used to create a global section by
the system manager.
shell process:
A predefined process that the job initiator copies to create the minimum context necessary to establish a process.
signal:
1. An electrical impulse conveying information. 2. The software mechanism
used to indicate that an exception condition was detected.
slave terminal:
A terminal from which it is not possible to issue commands to the command
interpreter. A terminal assigned to application software.
small process:
A system process that has no control region in its virtual address space and has
an abbreviated context. Examples are the working set swapper and the null
process. A small process is scheduled in the same manner as user processes,
but must remain resident during its execution.

G-39
software context:
The context maintained by the operating system that describes a process_ See
software process control block (PCB)_
software interrupt:
An interrupt generated on interrupt priority level 1 through 15, which can be
requested only by software.
software process control block (PCB):
The data structure used to contain a process' software context. The operating
system defines a software PCB for every process when the process is created.
The software PCB includes the following kinds of information about the process: current state; storage address if it is swapped out of memory; unique identification of the process, and address of the process header (which contains the
hardware PCB). The software PCB resides in system region virtual address
space. It is not swapped with a process.
software priority:
See process priority and queue priority.

spooling-Output spooling: The method by which output to a low-speed
peripheral device (such as a line printer) is placed into queues maintained on a
high-speed device (such as a disk) to await transmission to the low-speed
device. Input spooling: The method by which input from a low-speed
peripheral (such as the card reader) is placed into queues maintained on a
high-speed device (such as a disk) to await transmission to a job processing
that input.
spool queue:
The list of files supplied by processes that are to be processed by a symbiont.
For example, a line printer queue is a list of files to be printed on the line
printer.
stack:

An area of memory set aside for temporary storage, or for procedure and interrupt service linkages. A stack uses the last-in, first-out concept. As items are
added to ("put on") the stack, the stack pointer decrements. As items are
retrieved from ("popped off") the stack, the stack pointer increments.
stack frame:
A standard data structure built on the stack during a procedure call, starting
from the location addressed by the FP to lower addresses, and popped off during a return from procedure. Also called call frame.

G-40 • Glossary

stack pointer:
General register 14 (R14). SP contains the address of the top (lowest address)
of the processor-defined stack. reference to SP will access one of the five possible stack pointers (kernel, executive, supervisor, user, or interrupt) depending on the value in the current mode and interrupt stack bits in the Processor
Starus Longword (PSL).
state queue:
A list of processes in a particular processing state. The scheduler uses state
queues to keep track of process' eligibility to execute. They include: processes
waiting for a common event flag, suspended processes, and executable processes.
status code:
A longword value that indicates the success or failure of a specific function.
For example, system services always return a status code in RO upon completion.
store through:
See write through.
strong definition:
Definition of a global symbol that is explicitly available for reference by modules linked with the module in which the definition occurs. The linker always
lists a global symbol with a string definition in the symbol portion of the map.
The librarian always includes a global symbol with a strong definition in the
global symbol table of a library.
strong reference:
A reference to a global symbol in an object module that requests the linker to
report an error if it does not find a definition for the symbol during linking. If
a library contains the definition, the linker incorporates the library module
defining the global symbol into the image containing the strong reference.
subprocess:
A subsidiary process created by another process. the process that creates a subprocess is its owner. A subprocess receives resource quotas and limits from its
owner. When an owner process is removed from the system, all its subprocesses (and their subprocesses) are also removed.
supervisor mode:
The third most privileged processor access mode (mode 2). The operating system's command interpreter runs in supervisor mode.
suspension:
A state in which a process in inactive, but known to the system. A suspended
process becomes active again only when another process requests the operating system to resume it. Contrast with hibernation.

G·41

swap mode:
A process execution state that determines the eligibility of a process 'to be
swapped out of the balance set. If process swap mode is disabled, the process
working set is locked in the balance set.
swapping:
The method for sharing memory resources among several processes by writing
an entire working set to secondary storage (swap out) and reading another
working set into memory (swap in). For example, a process' working set can be
written to secondary storage while the process is waiting for I/O completion on
a slow device. it is brought back into the balance set when I/O completes. Con·
trast with paging.
switch:
See (command) qualifier.
symbiont:
A full process that transfers record-oriented data to or from a mass storage
device. For example, an input symbiont transfers data from card readers to
disks. An output symbiont transfers data from disks to line printers.
symbiont manager:
The function (in the system process called the job controller) that maintains
spool queues, and dynamically creates symbiont processes to perform the nec'~ssary I/O operations.
symbol:
See local symbol, global symbol, and universal global symbol.
Synchronous Backplane Interconnect (SBI):
The part of the hardware that interconnects the processor, memory controllers, MASSBUS adapters, and the UNIBUS adapter.
synchronous record operation:
A mode of record processing in which a user program issues a record read or
write request and then waits until that request is fulfilled before continuing to
execute.
system:
In the context "system, owner, group world," the system refers to the group
numbers that are used by the operating system and its controlling users, the
system operators and system manager.
system address space:
See system space and system region.
System Base Register (SBR):
A processor register containing the physical address of the base of the system
page table.

G-42 • Glossary

system buffered I/O:
An I/O operation, such as terminal or mailbox I/O, in which an intermediate
buffer from the system bUffer pool is used instead of a process-specified
buffer. Contrast with direct I/O.
System Control Block (SCB):
The data structure in system space that contains all the interrupt andexception vectors known to the system.
System Control Block Base register (SCBB):
A processor register containing the base address of the system control block.
system device:
The random access mass storage device unit which the volume containing the
operating system software resides.
system dynamic memory:
Memory reserved for the operating system to allocate as needed for temporary
storage. For example, when an image issues an I/O request, system dynamic
memory is used to contain the I/O request packet. Each process has a limit on
the amount of system dynamic memory that can be allocated for its use at one
time.
System ldentification Register:
A processor register which contains the processor type and serial number.
system image:
the image that is read into memory from secondary storage-when the system is
started up.
.
System Length Register (SLR):
A processor register containing the length of the system page table in longwords, that is, the number of page table entries in the system region page
table.
System Page Table:
The data structure that maps the system region virtual addresses, including
the addresses used to refer to the process page tables. The system Page Table
(SPT) contains one Page Table Entry (PTE) for each page of system region virtual memory. The physical base address of the SPT is contained in a register
called the SBR.
system process:
A process that provides system-level functions. Any process that is part of he
operating system. See also small process, fork process.
system programmer:
A person who designs and/or writes operating systems, or who designs and
writes procedures or programs that provide general purpose services for an
application system.

G-43

system queue:
A queue used and maintained by operating system procedures. See also state
queues.
system region:
The third quarter of virtual address space. The lowest-addressed half of system space. Virtual addresses in the system region are shareable between processes. Some of the data structures mapped by system region virtual addresses
are system entry vectors, the System Control Block (SCB), the System Page
Table (SPT), and process page tables.
system services:
Procedures provided by the operating system that can be called by user processes.
system space:
The highest-addressed half of virtual address space. See also system region.
system virtual address:
A virtual address identifying a location mapped by an address in system space.
system virtual space:
See system space.
task:
An RSX -II/lAS term for a process and image bound together.

terminal:
The general name for those peripheral devices that have keyboards and video
screens or printers. Under program control, a terminal enables people to type
commands and data on he keyboard and receive messages on the video screen
or printer. Examples of terminals are the LA36 DECwriter hard-copy terminal and VT100 video display terminal.
time-critical process:
A process assigned to a software priority level between 16 and 31, inclusive.
The scheduling priority assigned to a time-critical process is never modified
by the scheduler, although it can be modified by the system manager or process itself.
timer:
A system fork process that maintains "the time of day and the date. It also
scans for device timeouts and performs time-dependent scheduling upon
request.
transfer address:
The address of the location containing a program entry point (the first instruction to execute).

G-44· Glossary
translation buffer:
An internal processor cache containing translations for recently used virtual
addresses.
trap:
An exception condition that occurs at the end of the instruction that caused
the exception. The PC saved on the stack is the address of the next instruction
that would normally have been executed. All software can enable and disable
some of the trap conditions with a single instruction.
trap enables:
Three bits in the Processor Status Word that control the processor's action on
certain arithmetic exceptions.
two's complement:
A binary representation for integers in which a negative number is one greater
than the bit complement of the positive number.
two-way associative cache:
A cache organization which has two groups of directly mapped blocks. Each
group contains several blocks for each index position in the cache. A block of
data from main memory can go into any group at its proper index position. A
two-way associative cache is a compromise between the extremes of fully associative and direct mapping cache organizations that takes advantage of the features of both.
typeahead:
A terminal handling technique in which the user can enter commands and
data while the software is processing a previously entered command. the commands typed ahead are not echoed on the terminal until the command processor is ready to process them. they are held in a type ahead buffer.
unit record device:
A device such as a card reader or line printer.
universal global symbol:
A global symbol in a shareable image that can be used by modules linked with
that shareable image. Universal global symbols are typically a subset of all the
global symbols in a shareable image. When creating a shareable image, he
linker ensures that universal global symbols remain available for reference
after symbols have been resolved.
unwind the call stack:
To remove call frames from the stack by tracing back through nested procedure calls using the current contents of the FP register and he FP register contents stored on the stack for each call frame.

G-45

urgent interrupt:
An interrupt received on interrupt priority levels 24 through 31_ These can be
generated only by the processor the for the interval clock, serious errors, and
power faiL
user authorization file:
A file containing an entry for every user that the system manager authorizes
to gain access to the system. Each entry identifies the user name, password,
default account, User Identification Code (VIC), quotas, limits, and privileges
assigned to individuals who use the system.
user environment test package (UETP):
A collection of routines that verify that the hardware and software systems are
complete, properly installed, and ready to be used.
User File Directory (UFD):
See directory_
User Identification Code (UIC):
The pair of numbers assigned to users and to files, global sections, common
event flag clusters, and mailboxes that specifies the type of access (read and/or
write access, and in the case of files, execute and/or delete access) available to
the owners, group, world, and system_ It consists of a group number and a
member number separated by a comma.
user mode:
The least privileged processor access mode (mode 3)_ User processes and the
Run Time Library procedures run in user mode.
user name:
The name that a person types on a terminal to log on to the system.
user number:
See member number.
user privileges:
The privileges granted a user by the system manager. See process privileges.
utility:
A program that provides a set of related general purpose functions, such as a
program development utility (an editor, a linker, etc.), a file management utility (the copy or file format translation program), or operations management
utility (disk backup/restore, diagnostic program, etc_).
value return registers:
The general registers RO and R1 used by convention to return function values_
These registers are not preserved by any called procedures_ They are available
as temporary registers to any called procedure. All other registers (R2, R3, ... ,
Rll, AP, FP, SP, PC) are preserved aCross procedure calls.

G-46· Glossary

variable-length bit field:
A set of 0 to 32 contiguous bits located arbitrarily with respect to byte boundaries. A variable bit field is specified by four attributes: 1) the address A of a
byte, 2) the bit position P of the starting location of the bit field with respect
to bit 0 of the byte at address A, 3) the size, in bits, of the bit field, and 4)
whether the field is signed or unsigned.
variable-length record format:
A file format in which records are necessarily the same length.
variable with fixed-length control record format:
Property of a file in which records of variable-length contain an additional
fixed control area capable of storing data that may have no bearing on the
other contents of the record. Variable with fixed-length control record format
is not applicable to indexed files.
VAX-ll Record Management Services (VAX-ll RMS):
The file and record access subsystem of the VAX/VMS operating system for
VAX. VAX-l1 RMShelps your application program process records within
files, thereby allowing interaction between your application program and its
data.
vector:
1. A interrupt or exception vector is a storage location known to the system
that contains the starting address of a procedure to be executed when a given
interrupt or exception occurs. The system devises separate vectors for each
interrupting device controller and for classes of exceptions. Each system vector is a longword. 2. For exception handling, users can declare up to two software exception vectors (primary and secondary) for each of the four access
modes. Each vector contains the address of a condition handler. 3. A onedimensional array.
version number:
1. The field following the file type in a file specification. It begins with a
period (.) and is followed by a number which generally identifies it as the latest file created of all files having the identical file specification but for version
number. 2. The number used to identify the revision level of program.
virtual address:
A 32-bit integer identifying a byte "location" in virtual address space. The
memory management hardware translates a virtual address to a physical
address. The term "virtual address" may also refer to the address used to identify a virtual block on a mass storage device.
virtual address space:
The set of all possible virtual addresses that an image executing in the context
of a process can use to identify the location of an instruction or data. The virtual address space seen by the programmer is a linear array of 4,294,967,296
(2 32 ) byte addresses.

G-47

virtual block:
A block on a mass storage device referred to by its file-relative address rather
than its logical (volume-oriented) or physical (device-oriented) address. The
first block in a file is always virtual block 1.
virtual I/O functions:
A set of I/O functions that must be interpreted by an ancillary control process.
virtual memory:
The set of storage locations in physical memory and on disk that are referred
to by virtual addresses. From the programmer's viewpoint, the secondary storage locations appear to be locations in physical memory. The size of virtual
memory in any system depends on the amount of physical memory available
and the amount of disk storage used for non-resident virtual memory.
virtual page number:
The virtual address of a page of virtual memory.
volume:

Disks: An ordered set of 512-byte blocks. The basic medium that carries a
Files-ll structure.

Magnetic tape: A reel of magnetic tape, which may contain a part of a file, a
complete file, or more than one file.

volume set:
A collection of related volumes.
wait:
To become inactive. A process enters a process wait state when the process
suspends itself, hibernates, or declares that it needs to wait for an event,
resource, mutex, etc.

wake:
To activate a hibernating process. A hibernating process can be awakened by
another process or by the timer process, if the hibernating process or another
process scheduled a wake-up call.
weak definition:
Definition of a global symbol that is not explicitly available for reference by
modules linked with the module in which the definition occurs. The librarian
does not include a global symbol with a weak definition in the global symbol
table of a library. Weak definitions are often used when creating libraries to
identify those global symbols that are needed only if the module containing
them is otherwise linked with a program.

G-48 • Glossary

weak reference:
A reference to a global symbol that requests the linker not to report an error or
to search the default library's global symbol table to resolve the reference if
the definition is not in the modules explicitly supplied to the linker. Weak
reference'S are often used when creating object modules to identify those
global symbols that may not be needed at run time.
wild card:
A symbol, such as an asterisk, that is used in place of a file name, file type,
directory name, or version number in a file specification to indicate "all" for
the given field.
window:
See mapping window.
word:
Two contiguous bytes (16 bits) starting on an addressable byte boundary. Bits
are numbered from the right, 0 through 15. A word is identified by the
address of the byte containing bit O. When interpreted arithmetically, a word
is a 2's complement integer with significance increasing from bit 0 to bit 14. If
interpreted as a signed integer, bit 15 is the sign bit. The value of the integer
is in he range -32,768 to 32,767. When interpreted as an unsigned integer,
significance increases from bit 0 through bit 15 and the value of the unsigned
integer is in the range 0 through 65,535.
working set:
The set of pages in process space to which an executing process can refer without incurring a page fault. The working set must be resident in memory for the
process to execute. The remaining pages of that process, if any, are either in
memory and not in the process working set or they are on secondary storage.
working set swapper:
A system process that brings process working sets into the balance set and
removes them from the balance set.
world:
In the context "system, owner, group, world," world refers to all users, including the system operators, the system manager, and users both in an owner's
group and in any other group.
write access type:
The'specified operand of an instruction or procedure is written only during
that instruction's or procedure's execution.
write allocate:
A cache management technique in which cache is allocated on a write miss as
well as on the usual read miss.

G-49

write back:
A cache management technique in which data from a write operation to cache
are copied into main memory only when the data in cache must be overwritten. This results in temporary inconsistencies between cache and main memory. Contrast with write through.
write through:
A cache management technique in which data from a write operation are copied in both cache and main memory. Cache and main memory data are always
consistent. Contrast with write back.

A
accelerator control/status register
(ACCS)
for FP730, 10-29
for FP750, 10-36
for FP780, 10-47-10-48
for FP86, 10-80-10-81
accelerator maintenance register
(ACCR), 10-48-10-49
access
to files and volumes, 1-46
protection for, 1-34
to shared resources, quotas and
privileges for, 1-45
acknowledge-negative/acknowledge
packet, 11-92-11-93
addresses
translation between synchronous
backplane interconnect and
UNIBUS of, 11-27-11-32
virtual to physical translation
of, in MASSBUS, 11-65-11-66
addressing modes, 1-32
address register (ADR), 11-107
address space
in CPU/memory interconnect, 9-6
in synchronous backplane
interconnect, 9-13
system space, registers for,
10-10-10-12
in UNIBUS, 11-14, 11-27
in VAX-11/780 and VAX-11/785
systems, 5-19
virtual, registers for, 10-7-10-10
address translation
in UNIBUS operation, 11-14
virtual to physical, in
MASSBUS, 11-65-11-66

address translation buffers
in VAX-11/730 systems, 3-8, 3-13
in VAX-11/750 systems, 4-7, 4-11
in VAX-11/780 and VAX-11/785
systems, 5-14
applications
DR32 Device Interconnect
interface with, 11-100
error detection in, 1-42
of VAX 8600 systems, 1-24
arbitration
in CPU/memory interconnect, 9-5
in UNIBUS, 11"14-11-16
architectural processor registers,
10-1-10-2
console terminal, 10-18-10-22
memory, 10-22-10-25
process control block, 10-4-10-7
for system clocks, 10-15-10-18
system identification, 10-2-10-3
for system space, 10-10-10-15
for virtual address space,
10-7-10-10
architecture, 1-30-1-37
for communications, 2-11
of VAXclusters, 1-2-1-3
arithmetic data types, 1-31
arithmetic traps, 1-40
asynchronous communications, 2-31
asynchronous interfaces, 2-31-2-37
asynchronous multiplexers
DHU11,2-37
in DMF32 multifunction
communication controller,
2-32-2-33
DMZ32,2-33-2-34
DZ11,2-35-2-36
asynchronous system traps registers
(AST), 10-13-10-14

automatic online error logging, 1-42
automatic rebooting, 1-29
automatic reconfiguration, 1-44
automatic restarts, 1-44,5-10,8-9,
8-19
automatic stack expansion, 1-43

B
BA11-A mounting box, 7-5
BA11-K expansion box, 5-7
backplanes
DD11-K UNIBUS backplane, 5-7
in VAX-11/725 systems, 3-3
in VAX-11/730 systems, 3-5
in VAX-11/750 systems, 4-4
in VAX-11/780 and VAX-11/785
systems, 5-5
bad-block handling, dynamic, 1-45
baseband, Ethernet on, 2-12
DEREP repeaters for, 2-19
DEUNA communication
controllers for, 2-17
H4000 transceivers for, 2-18
battery backups
for MA780 multiport shared
memory, 5-26
unattended automatic system
restarts and, 1-44
for VAX-11/730 systems, 1-10
for VAX-11/750 systems, 1-15,4-17
for VAX-11/780 systems, 1-19
for VAX-11/782 systems, 6-3
for VAX 8600 systems, 1-28
bootstrap loading sequence, 8-9
in VAX-11/725 systems, 8-18
in VAX-11/750 systems, 8-30-8-31
in VAX-11/780 systems, 8-49
in VAX-11/782 systems, 8-52
in VAX-11/785 systems, 8-53-8-54
broadband, Ethernet on, 2-13-2-17
broadband frequency translator
(DEFTR),2-16-2-17

BR receive vector register
(BRRVR), 11-41-11-44,
11-54-11-55
buffer block, 11-100
buffered data paths, 11-16,
11-21-11-22
control/status registers for,
11-23-11-24
in UNIBUS, 11-33-11-34, 11-39
buffers
in cache memory, 1-37
data packet, in Computer
Interconnect, 11-79
in DR32 Device Interconnect, 11-98
in UNIBUS, 11-34, 11-36, 11-38
in VAX-11/730 systems, 3-8,
3-10,3-13
in VAX-11/750 systems, 4-7, 4-11
in VAX-11/780 and VAX-11/785
systems, 5-14, 5-15
in VAX 8600 systems, 7-14, 7-18
buffer selection verification
registers (BRSVR), 11-54
buses, 9-1
CPU/memory interconnect,
9-1-9-6
parity checks of, 1-55
Q-bus, 1-5
registers for, 10-30-10-32
synchronous backplane
interconnect, 9-6-9-29
in VAX-11/730 systems, 3-10
in VAX-11/750 systems, 4-7
in VAX-11/780 and VAX-11/785
systems, 5-8, 5-12
in VAX 8600 systems, 7-10,
7-12-7-13
see also I/O (input/output)
subsystems; MASSBUS; UNIBUS
bus request (BR) lines, 11-41
bus request (BR) transfers, 11-14
byte count register (BCR),
11-72-11-73

for PeL 11-B parallel
communications link, 2-52
for SC008 Star Coupler, 2-5

cabinets
for CI750 adapter, 2-4
CPU expansion, 5-8"
DFI00 multiple modem
enclosure, 2-58
for HSC50.inte!ligent mass
storage server, 2-9
for MA 780 multiport shared
memory, 5-26
MA780 multiport shared
memory mounted in, 5-24
for RA60 removable-media disk
drive, 12-5
for RA80 fixed-media disk drive,
12-6
for RA81 fixed-media disk drive,
12-8
for RC25 fixed/removable disk
drive, 12-11
for RL02 cartridge disk drive,
12-9
for RM05 removable-media disk
drive, 12-13
for RP07 fixed-media disk drive,
12-14
for SC008 Star Coupler, 2-6
for TA78 magnetic tape unit, 12-19
for TS05 magnetic tape unit, 12-23
for TU77 magnetic tape drive, 12-20
for TU78 magnetic tape unit, 12-22
for TU80 magnetic tape unit, 12-16
for TU81 magnetic tape unit, 12-17
UNIBUS expansion, 5-7
for VAX-11/725 systems, 3-2
for VAX-11/730 systems, 3-5
for VAX-11/750 systems, 4-4
for VAX-11/780 and VAX-11/785
systems, 5-5
for VAX 8600 systems, 7-3-7-6

cache disable register (CADR), 10-34

cables
baseband, Ethernet on, 2-12
broadband, Ethernet on, 2-13-2-17
DEREP repeaters for, 2-19-2-21
for H4000 Ethernet transceivers,
2-18

cache error register (CAER),
10-34-10-35
cache invalidation option
(MA780-D),6-7
cache memory, 1-37
parity checks of, 1-54
in VAX-11/750 systems, 4-11
in VAX-11/780 and VAX-11/785
systems, 5-15
in VAX-11/785 systems, 5-4
cache sweep register, 10-52-10-53
C bus, see console bus
CCITT (International Consultative
Committee on Telephony), 2-31
chaining, in DR32 Device
Interconnect, 11-97-11-98
CI750 Computer Interconnect
adapter (CIA), 1-15,2-4,
11-8, 11-76
CI780 Computer Interconnect
adapter (CIA), 1-19,
1-27,2-4, 11-8, 11-76
CI adapters, 11-77
registers for, 11-79-11-86
clocks, 1-38
for DR32 Device Interconnect,
11-94, 11-95
high resolution interval, 1-47
registers for, 10-15-10-18
in VAX-11/730 systems, 3-10, 3-11
in VAX-11/750 systems, 4-7, 4-10
in VAX-11/780 and VAX-11/785
systems, 5-16
CMI bus, see CPU/memory interconnect
CMI error register (CMIER),
10-30-10-31
coaxial cables, 2-13
for Comp:uter Interconnect, 11-76
DEREP repeaters for, 2-19-2-21
cold starts, 8-9
command/address transfers, in SBI,
9-19-9-21

command block, 11-100
command chaining, in DR32
Device Interconnect,
11-97-11-98
command packets, 11-99-11-100
commands, console, 1-38,8-3
console command language,
8-7-8-8
in VAX-11/725 systems, 8-14-8-17
in VAX-11/750 systems, 8-27-8-30
in VAX-11/780 systems, 8-38-8-43
in VAX 8600 systems, 8-62-8-83
communication controllers (DEUNA),
2-17
communication devices, 1-4
communication interfaces, in VAX11/780 systems, 1-18
communications
between console subsystem and
CPU in VAX-11/780 and
VAX-11/785 systems, 5-10
between console terminal and
CPU, 8-2
DF112 modem for, 1-26
networks for, 2-10-2-60
packet formats for, 11-91-11-93
in UNIBUS operation, 11-13-11-14
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/782 systems, 6-3
VAX/VMS operating system
support for, 1-35-1-36
communication servers, 2-23-2-30
compatibility
across VAX systems, 1-1
with PDP-11 systems, 3-1
between VAX 8600 systems and
other VAX systems, 7-1
of VAX system software, 1-29
components
in VAX-11/725 systems, 3-3
in VAX-11/730 systems, 3-6
in VAX-11/750 systems, 4-3
in VAX-11/780 and VAX-11/785
systems, 5-5

Computer Interconnect (Cl), 1-39,
2-1, 11-2, 11-8-11-9,
11-76-11-79
packet formats for, 11-91-11-93
registers for, 11-79-11-91
in VAXcluster systems, 2-2-2-4
configuration .
automatic reconfiguration and, 1-44
of Computer Interconnect,
11-8-11-9
of DDI adapter, 11-93-11-94
of DECnet Router Server,
2-26-2-27
of DEC net Router/X.25 Gateway
Server, 2-28-2-29
of DELNI local network
interconnects, 2-22-2-23
of DF02 and DF03 modems, 2-57
of DMF series of statistical
multiplexers, 2-51
of DMP11 single-line synchronous
controller, 2-39
'of DR32 Device Interconnect,
11-9-.,11-10
of DT07-xx UNIBUS interface
switch series, 2-53
of DUP11 single-line synchronous
programmable int!:rface, 2-43
of DZSll terminal concentrator and
multiplexer, 2-49
of Ethernet network repeaters, 2-21
of HSC50 intelligent mass storage
server, 2-9
of KMSll-B eight-line synchronous
programmable controller, 2-46
of KMS11-P single-line programmable
controller, 2-47-2-48
of MA780 multiport shared memory,
5-24-5-26
of MASSBUS subsystem, 11-6-11-7
of networks, 2-30
of Computer Interconnect,
11-76-11-77
of PCLll-B parallel
communications link, 2-52
of UNIBUS subsystem, 11-3-11-5
of VAX-ll/725 systems, 1-7-1-8
of VAX-ll/730 systems, 1-11
of VAX-11/750 systems, 1-12,

1-15-1-16,4-4
of VAX-11/780 systems,
1-17-1-20,5-5-5-8
of VAX-ll/782 systems,
1-21-1-23,6-3-6-9
of VAX-11/785 systems, 5-5-5-8
of VAX 8600 systems, 1-25-1-28,
7-3-7-6
of VAXclusters, 2-2
configuration register (CNFGR),
11-45-11-47,11-79-11-82
configuration/status register (C5R),
11-75-11-76
console block storage registers, in
VAX 8600 systems, 10-77-10-80
console (C) bus
in VAX-ll/730 systems, 3-10
in VAX 8600 systems, 7-11,.7-12
console command errors
in VAX-11/730 systems, 8-22
in VAX-11/750 systems, 8-30
in VAX-11/780systems, 8-43-8-48
in VAX-11/785 systems, 8-53
console command language, 8-7-8-8
console command mode, in
VAX-11/780 systems, 8-34

in VAX-11/780 systems, 8-33
in VAX-11/782 systems, 8-51
in VAX 8600 systems, 8-56-8-58
console prompts, 8-4
console reboot register (CRBT),
10-63-10-64
console receive control/status
register (RXCS),
10-18-10-19, 10-64-10-65
console receive data buffer register
(RXDB), 10-19-10-20,
10-65-10-74
console software, in VAX 8600
systems, 8-61-8-63
console storage receive data
register (CSRD), 10-27
console storage receive status
register (C5RS), 10-26-10-27
console storage transmit data
register (C5TD), 10-29-10-29
console storage transmit status
register (CSTS), 10-28
console subsystem interface
registers, in VAX 8600
systems, 10-63~10-77

console memory, in VAX-11/785
systems, 5-4

console subsystems, 1-2, 1-29, 1-38,
8-1-8-9
console terminals for, 1-5
for VAX-11/725 .systems, 1-7,
8-10-8-19
for VAX-11/730 systems, 1-9,
3-11,8-20-8-22
for VAX-ll/750 systems, 1-14,
8-23-8-32
for VAX-ll/780 systems, 1-18,
5-10,8-33-8-50
for VAX-11/782 systems,
8-51-8-52
for VAX-11/785 systems, 5-10,
8-53-8-54
for VAX 8600 systems, 1-26,
7-7-7-11,8-55-8-86

console modes
in VAX-11/725 systems, 8-11
in VAX-11/730 systems, 8-20
in VAX-11/750 systems, 8-23

console terminals, 8-2
registers for, 10-18-10-22
in VAX-11/725 systems, 8-10
in VAX 8600 systems, 7-10

console commands, 8-3
in VAX-11/725 systems, 8-14-8-17
in VAX-11/750 systems, 8-27-8-30
in VAX-11/780 systems, 8-38-8-43
in VAX 8600 systems, 8-62-8-78
console control characters, 8-9
in VAX-ll/750 systems, 8-27
in VAX-11/780 systems, 8-36-8-37
console halt codes, 8-4-8-6
console I/O mode, 8-3
console command language in, 8-7
in VAX-ll/725 systems, 8-11
in VAX-11/750 systems, 8-23
in VAX 8600 systems, 8-56, 8-58

console transmit controVstatus
register (TXCS),
10-20-10-21,10-74-10-75
console transmit data buffer
register (TXDB),
10-21-10-22, 10-76-10-77
control and status registers, in
UNIBUS, 11-22-11-24
control board (DCB), 11-93
control characters, 8-9
in VAX-11/780 systems, 8-36-8-37
see also console control characters
controllers, 2-1-2-2
HSC50 intelligent mass storage
server, 12-2
UDA50 intelligent disk-drive
controller, 12-3-12-4
see also UDA50 universal disk
adapter
control lines, in DR32 Device
Interconnect, 11-95
control messages, in DR32 Device
Interconnect, 11-100-11-101
-control panel
on VAX-11/725 systems, 8-11-8-13
on VAX-11/730 systems, 8-20-8-22
on VAX-11/750 systems, 8-24-8-26
on VAX-11/780 systems, 8-34-8-36
on VAX-11/782 systems, 8-51
on VAX 8600 systems, 8-58-8-61
control paths, in MASSBUS adapter,
11-62
control RAM, parity checks of, 1-55
control register (CR), 11-68
control signals, for DR32 Device
Interconnect, 11-95
controVstatus register (CSR2),
11-22-11-23
control store
Ebox and, 7-15-7-16
parity checks of, 1-55
in VAX-11/780 and VAX-11/785
systems, 5-13
in VAX 8600 systems, 7-18
control store (CS) bus, 5-12

CPU control store, 4-9
CPU expansion cabinet (H9652-H), 5-8
CPU/memory interconnect (CM!),
4-7,9-1-9-6
CI750 adapter for, 2-4
DR32 Device Interconnect connected
to, 11-9
MASSBUS adapter connected
to, 11-59
register for, 10-30-10-31
CPUs (central processing units)
initialization of, in VAX 8600
systems, 8-85-8-86
MASSBUS adapter communications
with, 11-62
in VAX-11/725 systems, 1-49,
3-1-3-5
in VAX-11/730 systems, 1-49,
3-1,3-5-3.21
in VAX-11/750 systems, 1-50,
4-1-4-18
in VAX-11/780 systems,
1-51-1-52,5-1-5-4
in VAX-11/782 systems, 5-1-5-4
in VAX-11/785 systems, 1-51-1-52,
5-1-5-4
in VAX 8600 systems, 1-55
see also processors
customized emitter-coupled (ECL)
gate-array logic, 1-24
cycle time, in VAX-11/785 systems,
5-4
cyclic redundancy check (CRC),
1-40, 11-77-11-79
in packet transfers, 11-92

D
data
integrity of, 1-45-1-46
packet formats for, 11-91-11-93
protection for, 1-46
data buffers, in UNIBUS, 11-36, 11-38
data chaining, in DR32 Device
Interconnect, 11-98
data latches, 7-19

data lines, in DR32 Device
Interconnect, 11-95
data packet buffer, 11-79
data path registers (DPRO-DPR15),
11-55-11-56
data paths
in Computer Interconnect, 11-79
in MASSBUS adapter, 11-62
in UNIBUS, il-16, 11-33-11-34
in VAX-11/730 systems, 3-12-3-13
in VAX-11/750 systems, 4-9
in VAX-11/780 and VAX-11/785
systems, 5-14
data transfers
in Computer Inter<:onnect, 2-3,
11-8, 11-76
in CPU/memory interconnect,
9-3-9-5
on DECnet Router Server, 2-27
on DECnet/SNA Gateway
Server, 2-29
DF02 and DF03 modems for, 2-57
in DMF series of statistical
multiplexers, 2-50
in DMP11 single-line synchronous
controller, 2-39
in DMR11 single-line synchronous
interface, 2-42
in DR32 Device Interconnect,
11-2, 11-9, 11-93-11-95
in DUP11 single-line synchronous
programmable interface, 2-43
in DZS11 terminal concentrator
and multiplexer, 2-48
in HSC50 intelligent mass storage
server, 12-2
Ibox for, 7-13
in KMS11-B eight-line
synchronous programmable
controller, 2-45
in KMS11-P single-line
programmable controller, 2-46
longword-aligned 32-bit random
access mode for, 11-39-11-41
in MA780 multiport shared memory,
5-27
in MASSBUS, 11-2
in MASSBUS adapter, 11-62

packet formats for, 11-91-11-93
paths for, in UNIBUS adapter,
11-33-11-34
in PCL11-B parallel
communications link, 2-51
in synchronous backplane
interconnect, 9-12-9-14,
9-19-9-25
between synchronous backplane
interconnect and UNIBUS,
11-26-11-27
between UNIBUS and memory,
11-34-11-41
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-18,
1-19,5-18
in VAX-11/782 systems, 6-6
in VAX-11/785 systems, 5-18
in VAX 8600 systems, 1-28
data types, 1-31-1-32
DATI data transactions,
11-21-11-22
DATIP data transactions,
11-21-11-22
DATOB data transactions, 11-22
DATa data transactions, 11-22
DB86 synchronous backplane
interconnect adapter (SBIA), 1-26
DD11-DK UNIBUS backplane, 5-7
DOl adapter, 11-9, 11-93-11-95
registers for, 11-101
DOl byte count register (DDIBC),
11-108
deadlock detection, 1-42
debug and trace facility, in VAX
8600 systems, 8-78-8-83
DECnet, 1-35-1-36; 2-11
DECnet Phase III, 2-26
DEC net Phase IV, 2-13, 2-26
DEC net Router Server, 2-26-2-27
DECnet Router/X.25 Gateway, 1-35
DECnet Router/X.25 GateWay Server,
2-28
DECnet/SNA Gateway, 1-35

DECnet/SNA Gateway Server,
2-29-2-30
DECnet-VAX Phase IV, 1-35
DECOM Ethernet broadband
transceiver, 2-13-2-15
default bootstrap procedures
in VAX-11/780 systems, 8-48
in VAX-11/782 systems, 8-52
in VAX-11/785 systems, 8-54
DEFI'R Ethernet broadband
frequency translator, 2-16-2-17
DELNI local network interconnect,
2-21-2-23
dependability of VAX systems
consistency and error checking
in, 1-40-1-43
data integrity in, 1-45-1-46
error analysis and recovery
features in, 1-43-1-45
maintenance aids in, 1-46-1-47
of VAX-11/725 and VAX-11/730
systems, 1-47-1-49
of VAX-11/750 systems, 1-49-1-50
of VAx-11/780, VAX-11/782,
and VAX-11/785 systems,
1-50-1-52
of VAX 8600 systems, 1-52-1-55
DEREP Ethernet repeaters, 2-19-2-21
DEUNA synchronous communication
controller, 2-17
in VAX-11/725 systems, 1-7
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-18
in VAX 8600 systems, 1-27
device control register (DCR),
11-101-11-104
device registers, in UNIBUS, 11-17
DF02 modem, 2-57
DF03 modem, 2-57
DF100 multiple modem enclosure,
2-58
DF112-AM modem module, 1-26,
2-59
DF126-AM modem module, 2-59
DF127-AM modem module, 2-59

DF129-AM modem module, 2-60
DHU1116-line asynchronous
multiplexer, 2-37
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-18
in VAX 8600 systems, 1-26
diagnostic console (DCON) program,
8-63
diagnostic context, 8-58, 8-62
commands for, 8-73-8-76
diagnostic control (DC) program,
8-63
diagnostic control register (DCR),
11-51-11-52
diagnostic fault insertion register
(DFI), 10-60-10-61
diagnostic registers
in MASSBUS, 11-73-11-75
in VAX 8600 systems, 10-60-10-63
diagnostics
console subsystems for, 1-38
controlled by console, 1-2
fault-isolation, 1-47
for MA 780 multiport shared
memory, 5-28
online, 1-46
remote, 1-30
remote, for VAX-11/780 systems,
8-33
remote, port on console subsystem
for, 8-2
in VAX-11/725 systems, 1-47-1-48
in VAX-11/730 systems, 1-9,
1-47-1-48
in VAX-11/750 systems, 1-14,
1-49-1-50,4-17
in VAX-11/780 systems, 1-18, 1-51
in VAX-11/782 systems, 1-51
in VAX-11/785 systems, 1-51
in VAX 8600 systems, 1-24,
1-26, 1-52, 1-53,7-10-7-11,
8-56,8-62
diagnostic support module (DSM), 8-63
Digital Command Language (DCL),
1-29

Digital Data Communications Message
Protocol (DDCMP), 2-38
Digital Data Interconnect (DDI), 1-39
Digital Network Architecture (DNA),
1-3,2-11
for local area networks, 2-12
Digital Storage Architecture (DSA),
1-3,2-1, 12-1
disk drive subsystems under,
12-4-12-9
Digital System Interconnect (DSI),
2-11
direct data paths, in UNIBUS, 11-33
direct memory access (DMA)
in DR32 Device Interconnect, 11-93
UDA50 intelligent disk-drive
controller for, 12-3
in UNIBUS, 11-1, 11-16, 11-30,
11-31
in VAX 8600 systems, 7-17
disk drives, 1-4, 12-4
HSC50 intelligent mass storage
server for, 2-8, 12-2
RA60 removable-media, 12-5-12-6
RA80 fixed-media, 12-6-12-7
RA81 fixed-media, 12-8-12-9
RC25 fixed/removable,
12-11-12-12
RL02 cartridge, 12-9-12-10
RM05 removable-media,
12-13-12-14
RP07 fixed-media, 12-14-12-15
UDA50 intelligent disk-drive
controller for, 12-3-12-4
in VAX-11/725 systems, 3-5
in VAX-11/730 systems, 1-10,3-7
in VAX-11/750 systems, 1-15
in VAX-11/780 systems, 1-19
in VAX 8600 systems, 1-27
disks, volume protection for, 1-46
dispatch RAM (DRAM), 7-14
DLV11-E console terminal interface,
5-10
DMF32 multifunction
communication controller,
2-32-2-33

in VAX-11/725 systems, 1-7
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-18
in VAX 8600 systems, 1-26
DMF series of statistical
multiplexers, 2-50-2-51
DMP11 single-line synchronous
controller, 2-39
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-18
in VAX 8600 systems, 1-26
DMR11 single-line synchronous
interface, 2-42-2-43
in VAX -11/725 systems, 1-7
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-18
in VAX 8600 systems, 1-26
DMZ32 24-line asynchronous
multiplexer, 2-33-2-34
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-18
in VAX 8600 systems, 1-26
DR11 option, 1-26
DR32 Device Interconnect (DDI),
11-2, 11-9-11-10, 11-93-11-94
command and data chaining in,
11-97-11-98
programming interface of,
11-99-11-101
registers for, 11-101-11-108
signal lines for, 11-95-11-97
in VAX-11/750 systems, 1-15
in VAX-11/780 systems, 1-19
in VAX 8600 systems, 1-28
DR32 Device Interconnect adapter,
11-93-11-95
registers for, 11-101
DR750 DDI adapter, 11-9, 11-93
DR780 DDI adapter, 11-9, 11-93
DT07-xx UNIBUS interface switch
series, 2-53

DUPll single-line synchronous
programmable interface,
2-43-2-44
in VAX-ll/730 systems, 1-10
in VAX-ll/750 systems, 1-14
in VAX-ll/780 systems, 1-18
in VAX 8600 systems, 1-26
DW750 UNIBUS adapter (UBA), 1-14
DW780 UNIBUS adapter (UBA),
1-18, 1-26, 6-3, 11-3, 11-25
dynamic bad-block handling, 1-45
dynamic fault insertion, 1-53
DZll eight-line asynchronous
multiplexer, 2-35-2-36
in VAX-ll/725 systems, 1-7
in VAX-ll/730 systems, 1-10
in VAX-ll/750 systems, 1-14
in VAX-ll/780 systems, 1-18
in VAX 8600 systems, 1-26
DZSll terminal concentrator and
multiplexer, 2-48-2-49

E
Ehox, 7-12, 7-15-7-16
registers for, 10-79-10-80
Ehox arithmetic unit, parity checks
of, 1-55
Ehox scratchpad address register
(ESPA), 10-79-10-80
Ebox scratchpad data register
(ESPD), 10-80
Ebox virtual-address bus (EVA), 7-12
ECL (customized emitter-coupled)
gate array logic, 1-24
Electronic Industries Association
(EIA),2-31
enclosures, see cabinets
environment, 1-46
for networks, 2-11
environmental monitoring module
(EMM) , 1-26, 1-54, 7-10
data on register for, 10-66-10-73
initialization of, 8-85

Error Correcting Code (ECC),
• 1-38, 1-41
in MA780 multiport shared memory,
5-28
in VAX-ll/730 systems, 3-15
in VAX-ll/750 systems, 4-12
in VAX-ll/780 and VAX-11/785
systems, 5-17, 5-18
error handling status register
(EHSR), 10-61-10-63
error log file, 1-41-1-44
error logging, 1-42
in VAX-ll/780 and VAX-11/785
systems, 5-18
in VAX-ll/782 systems, 6-9
error log reporting program, 1-43
error messages, in VAX-ll/780
systems, 8-43-8-48
errors
analysis and recovery features
for, 1-42-1-45
analysis and reporting of, in VAX
8600 systems, 1-54
checking for, 1-40-1-43
errors, console command, 8-9
in VAX-ll/725 systems, 8-17
in VAX-ll/730 systems, 8-22
in VAX-ll/750 systems, 8-30
in VAX-ll/780 systems, 8-43-8-48
in VAX-ll/785 systems, 8-53
Ethernet, 1-3, 1-7, 1-10,2-11-2-12
on broadband, 2-13-2-17
communication controllers (DEUNA),
2-17
communication servers, 2-23-2-30
repeaters (DEREP), 2-19, 2-21
transceiver (H4000), 2-18-2-23
VAX 8600 systems in, 1-27
exception handling, 1-41
exceptions, in VAX-ll/780 and
VAX-ll/785 systems, 5-15
executive stack pointer (ESP)
register, 10-6
expansion cabinets, for VAX 8600
systems, 7-5-7-6
extended read cycles, 5-21

extended read function, in SBI, 9-24
extended write masked function,
5-21,9-25

F
failed map entry register (FMER),
11-52-11-53
.

failed UNmus address register
(FUBAR), 11-53-11-54
fault-isolation diagnostics, 1-47
Fbox, 7-17
FEPCM front-end communication
processor, 2-54
files, access control for, 1-46
floating-point accelerator (FPA)
in VAX-11/725 systems, 3-1
in VAx-11/730 systems, 1-8, 3-1,
3-8, 3-19, 10-29
in VAX-11/750 systems, 1-12,
1-17,4-18,10-36
in VAX-11/780 systems, 5-16,
10-47-10-49
in VAX-11/782 systems, 1-21
in VAX-11/785 systems, 1-23,5-16
in VAX 8600 systems, 1-25,7-17,
10-80-10-81
FP730 floating-point al:celerator, 1-8,
3-19
register for, 10-29
FP750 floating'point accelerator, 1-12,
1-17,4-18
register for, 10-36
FP780 floating-point accelerator, 5-16
register for, 10-47-10-49
FP782 floating-point accelerator, 1-21
FP785 floating-point accelerator, 1-23,
5-16
FP86 floating-point accelerator, 1-25
register for, 10-80-10-81
FPA/port bus, 3-10
front-end communication processor
(FEPCM),2-54

G
general purpose registers (GPRs), 1-33
parity checks of, 1-55
in VAX 8600 systems, 7-12

H
H4000 Ethernet transceiver,
2-18-2-23
H7112 memory battery backup unit
in VAX-11/750 systems, 1-15,4-17
in VAX-11/780 systems, 1-19
in VAX-11/782 systems,6-3
in VAX 8600 systems, 1-28
H7750 memory battery backup
unit, 1-10 .
H9642 general purpose UNIBUS
expansion cabinet, 1-10
H9652-CA (-CB) SBI expansion
cabinet, 7-6
H9652-F UNmus expansion cabinet,
7-5
H9652-H CPU expansion cabinet,
5-8,5-24
H9652-M UNmus expansion
cabinet, 5-7
H9652 UNIBUS expansion cabinet,
1-17
halt codes, 8-4-8-6
hardware
automatic reconfiguration after
failures of, 1-44
errors in, machine checks for,
1-42
memory management, 1-45
selective disabling of, 1-45
see also processors
help files, 8-38
hexadecimal (HEX) debugger, 8-63
HSC50 intelligent mass storage
server, 1-2, 1-3, 12-2
in VAX-11/750 VAXcluster
configurations, 1-16

in VAXcluster systems, 2-8-2-9

I
IB bus, in VAX-11/730 systems, 3-10
IBM systems, DECnet/SNA Gateway
Server for communications with,
2-29-2-30
Ibox,7-13-7-14
Ibox virtual-address bus (IVA), 7-12
identification (ID) code, 5-20-5-21
IEC11-V device driver, 1-36
information
packet formats for, 11-91-11-92

see also-data
information management, in VAX/VMS
operating system, 1-34-1-35
initialization
of UNIBUS, 11-17
of VAX 8600 systems, 8-83-8-86
initialize UNIBUS register (IUR), 10-32
installation, 1-30
instruction box (Ibox), 7-13-7-14
instruction buffer, 5-15, 7-14
instruction buffer address register
(VIBA),5-14
instructions and instruction sets,
1-31-1-32
FP730 floating-point accelerator
for, 3-19-3-21
FP750 floating-point accelerator
for, 4-18
retrys of, 1-43
in VAX-11/725 and VAX-11/730
systems, 3-1
in VAX-ll/750 systems, 4-3
in VAX-11/780 and VAX-11/785
systems, 5-1
intelligent mass storage contrgllers
HSC50 intelligent mass storage
server, 12-2
UDA50 intelligent disk-drive
controller, 12-3-12-4

interfaces
between console subsystem and
CPU in VAX-11/780 and
VAX-11/785 systems, 5-10
link, for VAxclusters,
11-77-11-79
in MA780 multiport shared
memory, 5-26
programming, in DR32 Device
Interconnect, 11-99-11-101
synchronous, 2'38-2-47
UNIBUS, in VAX-11/725 systems,
1-7
UNIBUS asynchronous, 2-31-2-37
UNIBUS communication, 2-30-2-31
for VAX-11/730 systems, 1-10
for VAX-11/780 systems, 1-18
for VAX-11/782 systems, 6-3
for VAX 8600 systems, 1-26
interleaving, 5-17, 5-19
interlock cycles, 5-22
interlock-read-masked function, in
SBI,9-24
internal data (ID) bus, 5-12
International Consultative Committee
on Telephony (CCITT), 2-31
International Standards Organization
(ISO), 2-11
interrupt priority level register
(IPL), 10-13
interrupts
registers for, 10-13-10-15
in UNIBUS, "11-17,11-30,
11-41-11-44
in VAX-11/750 sy~tems, 4-10
in VAX-11/780 and VAX-ll/785
systems, 5-15
in VAX-11/782 systems, 6-9
in VAX 8600 systems, 7-19
interrupt stack pointer (ISP)
register, 10-6-10-7
interrupt summary sequence, in SBI,
9-22
interval clock control/status
register (ICCS), 10-17-10-18

interval clocks, 1-47, 10-16
in VAX-11/730 systems, 3-10, 3-11
in VAX-11/780 and VAX-11/785
systems, 5-16
interval count register (ICR),
10-16-10-17
invalidation maps, 5-28, 6-7
I/O (input/output) subsystems,
1-39,9-1, 11-1-11-3
Computer Interconnect,
11-8-11-9, 11-76-11-93
DR32 Device Interconnect,
11-9-11-10, 11-93-11-108
MASSBUS, 11-6-11-8,
11-58-11-76
UNIBUS, 11-3-11-5,
11-11-11-58
see also buses
UNIBUS, in VAX-11/725
systems, 1-7

K
KE780 extended-range floating-point
data type option, 1-17,5-16
kernal stack pointer (KSP) register, 10-5

supported by VAX/VMS
operating system, 1-34
LAT-11, 1-36
leased lines, DF02 and DF03 modems
for, 2-57
limit checking traps, 1-40
lineprinters
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-19
in VAX 8600 system~, 1-27
link interface, 11-77-11-79
local area networks (LANs)
Ethernet for, 1-3,2-11-2-30
VAX-11/725 systems in, 1-7
VAX-11/730 systems in, 1-10
VAX-11/780 systems in, 1-18
see also Ethernet
local Ethernet repeaters (DEREP),
2-19-2-21
local network interconnect
(DELNI), 2-21-2-23
logical data types, 1-31
longword-aligned 32-birrandom
access mode (UNIBUS),
11-39-11-41

KMS11-B eight-line synchronous
programmable controller,
2-45-2-46

longword-aligned map register, 11-41

KMS11-P single-line programmable
controller, 2-46-2-47

LP26 lineprinter, 1-10, 1-14, 1-19,

KU750 extended-range floating-point
option, 1-12

LP25 lineprinter, 1-10, 1-14, 1-19,
1-27
1-27
LP27 lineprinter, 1-27
LSI-11 microprocessors, 5-10, 8-33

KU750 writable control store (WCS),
4-17
KU780 user writable-control-store
option, 1-17,5-16

M
MA730 memory array modules, 3-19

L
LA120 console terminal, 8-23, 8-33
languages
high-level language constructs
for, 1-32

MA780-D cache ipvalidation option,
6-7
MA780 multiportshared memory,
1-21, 1-39, 5-24-5 c28
in VAx-H/782 systems, 6-1, '6-3,
8-52

machine check error summary register
(MSESR), 10-35-10-36
machine checks, 1-42
machine check status register
(MCSR),10-24-10-25
macro context, 8-58, 8-61
commands for, 8-70-8-73
initialization of, 8-85
macro control program (MCP), 8-63
magnetic tape formatters, in VAX
8600 systems, 1-27
magnetic tape subsystems
TA78, 12-19-12-20
TS05, 12-23-12-24
TU77,12-20-12-21
TU78, 12-22-12-23
TU80, 12-16-12-17
TU81,12-17-12-18
main memory subsystems, 1-38-1-39
in VAX-11/730 systems, 3-14-3-15
in VAX-11/750 systems, 1-16, 4-11
in VAX-11/780 and VAX-11/785
systems, 5-16-5-19
in VAX 8600 systems, 1-25, 1-28
maintenance, 1-30
aids for, 1-46-i-47
maintenance address register (MADR),
11-85-11-86
maintenance data register (MDATR),
11-86
maintenance registers, 1-47
map enable register (memory
management enable register;
MAPEN),10-22-10-23
map registers
longword-aligned, 11-41
for MASSBUS adapter, 11-62
in UNIBUS, 11-~1-11-33,
11-57-11-58
MASSBUS, 1-39, 11-2, 11-6-11-7
disk drive subsystems under,
12-12-12-15
functions of, 11-58~11-59
operation of, 11-61-11-64
registers for, 11-66-11-76
signal lines in, 11-59-11-61

virtual to physical address
translation in, 11-65-11-66
MASSBUS adapter (MBA), 11-2,
11-58-11-59
operation of, 11-61-11-64
registers for, 11-66-11-75
signal lines for, 11-59-11-61
in VAX-11/780 systems, 1-18
mass-storage error recovery, 1-45
mass storage server (HSC50), see
HSC50 intelligent mass
storage server
mass storage subsystems, 12-1
DSA disk-drive subsystems,
12-4-12-9
intelligent mass storage
controllers, 12-2-12-4
magnetic tape subsystems,
12-16-12-24
MASSBUS disk-drive subsystems,
12-12-12-15
UNIBUS disk-drive subsystems,
12-9-12-12
mass storage verification, 1-41
Mbox, 7-12, 7-17-7-18, 9-7
Mbox control store, 7-18
Moox data control register (MDCTL),
10-56-10-57
Mbox data ECC register (MDECC),
10-53-10-54
Mbox error enable register (MENA),
10-55-10-56
Mbox error generator register (MERG),
10-58-10-60
Mbox memory cache control register
(MCCTL), 10-57-10-58
M bus, 4-7
memory
cache, 1-37,5-15
data transfers between UNIBUS and,
11-34-11-41
MA780 multiport shared memory,
5-24-5-28
see also mass storage subsystems
memory array bus, in VAX-ll/730
systems, 3-10

memory configuration registers,
5-22-5-24
memory control (Me) bus, in VAX11/730 systems, 3-10
memory controller
Mbox, 7-17-7-18
in VAX-ll/730 systems, 3-13-3-14
in VAX-ll/750 systems, 4-12-4-14
in VAX-ll/780 and VAX-ll/785
systems, 5-18-5-19
memory control/status registers
in VAX-ll/730 systems, 3-16-3-19
in VAX-ll/750 systems, 4-14-4-17
memory data (MD) bus, 5-12, 7-12,
7-14
memory interconnect and control
(MIC), in VAX-ll/750 systems,
4-10---,-4-11
memory interleaving, 5-17, 5-19
memory management, 1-33, 1-38
hardware for, 1-45
memory management enable register
(map enable register; MAPEN),
10-22-10-23
memory registers, 10-22-10-25
in VAX-ll/750 and VAX-ll/751
systems, 10-32-10-36
in VAX 8600 systems, 10-50-10-60
memory subsystems, see main
memory subsystems
messages
carried in information packets, 11-91
control, in DR32 Device
Interconnect, 1-100-11-101
error, in VAX -11/780 systems,
8-43-8-48
microcontrol store registers,
10-37-10-39
microhardcore context, 8-62
commands for, 8-77-8-78
microprocessor and microcode
module (DUP), 11-93
microprogram breakpoint address
register (MBRK), 10-39
microsequencer, 5-13

MicroVAX I systems, 1-1, 1-5
microwords, 5-13
modems, 2-31, 2-55-2-60
DF112, 1-26
DMRll compatibility with, 2-43
modes of operation, of consol<c
subsystems, 8-2-8-3
MS750 memory modules, 4-17
MS780-E main memory subsystem,
5-17
MS780-H main memory subsystem,
5-17
multifunction communication
controller (DMF32), 2-32-2-33
multiplexers
DHUll 16-line asynchronous
multiplexer, 2-37
in DMF32 multifunction
communication controller,
2-32-2-33
DMZ32 24-line asynchronous
multiplexer, 2-33-2-34
DZ eight-line asynchronous
multiplexer, 2-35-2-36
DZSll terminal concentrator and
multiplexer, 2-48-2-49
statistical, DMF series of,
2-50-2-51
multiprocessing, in VAX-ll/782
systems, 6-9
MUX200/VAX protocol emulator, 1-36

N
networks, 2-10-2-11
DMF statistical multiplexers for,
2-50-2-54
Ethernet, 2-11-2-30
modems and modem enclosures for,
2-55-2'60
synchronous communication devices
for, 2-38-2-47
terminal concentrators and
multiplexers for, 2-48-2-49

UNIBUS communication interfaces
and devices for, 2-30-2-37
next interval count register (NICR),
10-17

PI base register (P1PT), 10-9
PI length register (P1LR),
10-9-10-10
packaging, 1-46

nexuses, 9-1

packets, 11-91-11-93

nodes, 2-30
HSC50 intelligent mass storage
server as, 2-8
information transfered between
in packets, 11-91
SC008 Star Coupler for, 2-5, 2-6

packet-switched data networks
(PSDNs), 2-28

nonfatalbugchecks,1-43
nonprocessor request (NPR)
transfers, 11-14

page frame number (PFN), 11-14
pages, in UNIBUS, 11-14, 11-30
parallel communications link
(PCL11-B),2-51-2-52
parallel processing, 5-27
parity checks, in VAX 8600 systems,
1-54-1-55
patches, to software, 1-47

PCL11-B parallel communications
link, 2-51-2-52

online diagnostics, 1-46

PDP-11/23-PLUS processor, 2-54

operand (OP) bus, 7-12

PDP-11/24 processor, 2-54

operating systems, 1-2
ULTRIX-32; 1-36-1-37
VAx/yMS, 1-33-1-36
see also ULTRIX-32 operating system;
VAx/yMS operating system
options
MA780 multiport shared memory,
1-39, 5-24-5-28
with VAX-11/725 systems, 1-7,
3-19
with VAX-11/730 systems, 1-10,
3-19
with VAX-11/750 systems, 1-14,
4-17-4-18
with VAX-11/780 systems, 1-18,
5-16
VAX-11/782 upgrade package, 6-6
with VAX-11/785 systems, 5-16
with VAX 8600 systems, 1-26

p
PO base register (POPT), 10-8
PO length register (POLR),
10-8-10-9

PDP-11 compatibility mode, 1-29, 3-1
per-process space, 10-8
physical address (PA) bus, 5-12
physical addresses
translation to virtual addresses,
in MASSijUS, 11-65-11-66
see also addresses
physical address memory access
register (PAMACC), 10-50-10-51
physical address memory map location
register (PAMACC), 10-51-10-52
physical address memory mapping
(PAMM),7-17-7-18
physical address memory map
registers (PAMM), 10-50
pipeline (sequential) processing, 5-27
port error status register (PESR),
11-89-11-90
port failing address register (PFAR),
11-88
port initialize control register (PICR),
11-91
port maintenance control/status
register (PMCSR), 11-82-11-85

port parameter register (PPR), 11-90
ports
in MA 780 multiport shared memory,
5-26
for remote diagnostics, 8-2
see also interfaces
port status register (PSR),
11-87-11-88
power failures
automatic rebooting after, 1-29,
1-44
battery backup for VAX-11/730
systems for, 1-10
battery backup for VAX-li/750
systems for, 1-15
battery backup for VAX-11/780
systems for, 1-19
battery backup for VAX 8600
.systems for, 1-28
in DR32 Device Interconnect,
,11-98
in UNIBUS, 11-17

in VAX-11/725 systems, 1-49,
3-1-3-5
in VAX-11/730 systems, 1-49,
3-1, 3-5-3-21
.
in VAX-11/750 systems, 1-50,
4-1-4-18
in VAX-11/780 systems, 1~51-1-52,
5-1-5-4
in VAX-11/782 systems, 1-51-1-52,
6-1,6-7-6-9
in VAX-11/785 systems, 1-51-1-52,
5-1-5-4
in VAX 8600 systems, 1-55,
7-7-7-19
see also CPUs
program counter (PC), 5-14
program interrupts
registers for, 10-13-10-15
see also interrupts

power supply, environmental
monitoring module for, 7-11

program I/O mode, 8-2
in VAX-11/725 systems, 8-11
in VAX-11/750 systems, 8-23
in VAX-11/780 systems, 8·34
in VAX 8600 systems, 8-56

power system initialization of VAX
8600 systems, 8-85

programmed array logic (PAL)
in VAX-11/7 30 systems, 3~8

prefetch instruction buffers, 4-7

programming interface, in DR32
Device Interconnect,
11-99-11-101

printers
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-14
in VAX-11/780 systems, 1-19
in VAX 8600 systems, 1-27

prompts, console, 8-4
PROMs (programmable read-only
memory),4-7

priority levels
in CPU/memory interconnect, 9-5
for interrupts, register for, 10-13
in synchronous backplane
interconnect, 9-11
in UNIBUS, 11-14-11-16
privileged registers, see registers

protection
for disk volumes, 1-46
in VAX/VMS operating system, 1-34

privileges, for shared resources, 1-45
process control block, 10-4-10-7

Q-bus, 1-5
in VAX 8600 systems, 7-10

process control block base register
(PCBB),10-11-10-12

QEI09-CY microprogramming tools
option, 1-17

processors
features of, 1-2-1-3
small, medium, and large, 1-1

queue I/o (QIO) driver, 11-100

quotas, for shared resources, 1-45

R
RA60 removable-media disk drive,
12-5-12-6
supported by HSC50 intelligent
mass storage server, 2-8
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-15
in VAX-11/780 systems, 1-19
in VAX 8600 systeins, 1-27
RA80 fixed-media disk drive,
12-6-12-7
supported by HSC50 intelligent
mass storage server, 2-8
in VAX-11/730 systems, 1-10
in VAX-11/750 systems, 1-15
in VAX-11/780 systems, 1-19
in VAX 8600 systems, 1-27
RA81 fixed-media disk drive,
12-8-12-9
supported by HSC50 intelligent
mass storage server, 2-8
in VAX-11/730 systems, 1-10
in VAX-ll/750 systems, 1-15
in VAX-11/780 systems, 1-19
in VAX 8600 systems, 1-27
RAM (random access memory)
in Computer Interconnect, 11-79
dispatch RAM (DRAM), 7-14
in MASSBUS adapter, 11-62
in VAX-11/730 systems, 3-14
RB730 integrated disk controller
(IDC),3-7
RC25 fixed/removable disk drive,
1-6, 1-10, 3-5, 12-11-12-12
RD (remote diagnostic) mode, 8-3
read cycles, in VAX-11/780 and
VAX-ll/785 systems, 5-20-5-21
read data transfers, in SBI, 9-19
read masked function, in SBI, 9-22
realtime clocks, 1-38
see also clocks
reconfiguration, automatic, 1-44
recovery from errors, 1-43 -1-45

redundant recording of critical disk
information, 1-45
register (R-log) file, 7-14, 7-19
registers, 1-33
address translation, in MASSBUS,
11-65
architectural processor,
10-1-10-25
for Computer Interconnect,
11-79-11-91
configuration/status, for MASSBUS,
11-75-11-76
control and status, in UNIBUS,
11-22-11-24
device, in UNIBUS, 11-17
for DR32 Device Interconnect,
11-101-11-108
longword-aligned map, 11-41
maintenance, 1-47
map, for MASSBUS adapter,
11-62
map, for UNIBUS, 11-31-11-33
for MASSBUS adapter,
11-66-11-75
memory configuration,
5-22-5-24
parity checks of, 1-55
R-log file of information in, 7-14
specific to VAX-ll/725 and
VAX-11/730 systems,
3-16-3-19, 10-25-10-29
specific to VAX-11/750 and
VAX-11/751 systems,
4-14-4-18, 10-30-10-36
specific to VAX-11/780, VAX11/782, and VAX-11/785
systems, 5-14, 10-36-10-49
specific to VAX 8600 systems,
10-49-10-81
system identification, 1-42
in UNIBUS, 11-26, 11-41-11-58
visibility, 7-10-7-11
remote diagnostics, 1-30, 1-38
port on console subsystem for, 8-2
for VAX-11/725 systems, 1-48,
8-10
for VAX-11/730 systems, 1-48
for VAX-11/750 systems,

1-49-1-50,4-17,8-23
for VAX-11/780 systems, 1-51,8-33
for VAX-11/782 systems, 1-51
for VAX-11/785 systems, 1-51
for VAX 8600 systems, 7-10
remote Ethernet repeaters (DEREP),
2-19-2-21
repeaters (DEREP), 2-19-2-21
reserved operand traps, 1-40
resources, shared, quotas and
privileges for, 1-45
restart parameter block (RPB),
8-19,8-32
restarts
automatic, 1-44, 8-9
in VAX-11/725 systems, 8-19
in VAX-11/750 systems, 8-32
in VAX-11/780 systems, 8-50
in VAX-11/782 systems, 8-52
RH750 MASSBUS adapter (MBA),
1-14, 11-6, 11-58
RH780 MASSBUS adapter (MBA),
11-6, 11-58-11-59
RL02 cartridge disk drive, 1-15,
1-26, 12-9-12-10
in VAX 8600 systems, 1-27,8-56
RL60 disk drive, 1-10
R-log (register) file, 7-14, 7-19
RM05 removable-media disk drive,
1-19, 1-27, 12-13-12-14
ROM (read-only memory), in VAX11/780 and VAX-11/785
systems, 5-19
Router Server, 2-26-2-27
RP07 fixed-media disk drive, 1-19,
12-14-12-15
RX01 floppy disk drive, 1-18,5-10 _
RXCS (console receive control/status
register), 10-18-10-19,
10-64-10-65
RXDB (console receive data buffer
register), 10-19-10-20,
10-65-10-74

s
SBI byte count register (SBIBC),
11-107
SBI control module (DSC), 11-93
SBI error register (SBIER),
10-45-10-46
SBI fault/status register (SBIFS),
10-39-10-40
SBI maintenance register (SBIMT),
10-43-10-44
SBI quadword clear register (SBIQC),
10-47
SBI silo cOl11paritor register (SBISC),
10-42-10-43
SBI silo data register (SBIS),
10-41-10-42
SBI timeout address register (SBITA),
10-46
SC008 Star Coupler, 1-2, 1-3
CI adapter connected to, 11-76
Computer Interconnect connected
to, 11-8
in VAX-11/750 VAXcluster
configurations, 1-16
in VAXcluster systems, 2-5-2-7
scheduling, in VAX-11/782 systems,
6-1, 6-3, 6-7
sequential (pipeline) processing, 5-27
serial diagnostic bus (SDB), 1-53,
7-10, 7-12,7-13
shared multiport memory (MA780),
1-21, 1-39,5-24-5-28
in VAX-11/782 systems, 6-1, 6-3,
8-52
signal lines
for CPU/memory interconnect,
9-2-9-3
for DR32 Device Interconnect,
11-95-11-97
for MASSBUS adapter,
11-59-11-61
for synchronous backplane
interconnect, 9-7-9-12
for UNIBUS, 11-11-11-13

silo module (DSM), 11-93
single-user systems, VAX-11/725
systems as, 3-2
SNA (System Network Architecture;
IBM),2-29-2-30
software, 1-33-1-37
compatibility of, 1-29
compatibility across VAX systems
of,I-1
console, in VAX 8600 systems,
8-61-8-63
instructions and data types,
1-31-1-32
with KMS11-B eight-line
synchronous programmable
controller, 2-46
System Startup Service Packages,
(SSSPs), 1-5
updates and maintenance of, 1-47
software interrupt request register
(SIRR), 10-14
software interrupt summary level
register (SISR), 10-15
special instruction checks, 1-40
spooling, automatic reconfiguration
of, 1-44
stacks, 1-33
automatic expansion of, 1-43
standard disk interfaces (SDI), 2-8
standard package of error analysis
and reporting (SPEAR), 1-54

synchronous backplane interconnect
(SBI), 9-1, 9-6-9-29
addressable by UNIBUS adapter
registers, 11-45-11-58
address and function translation
between UNIBUS and,
11-27-11-32
CI780 adapter for, 2-4
data transfers between UNIBUS
and, 11-26-11-27
DDI adapter connected to, 11-93
DR32 Device Interconnect
connected to, 11-9, 11-93
error detection by, 1-51
MASSBUS adapter connected
to, 11-59
MASSBUS connected to, 11-61
UNIBUS connected to, 11-25
UNIBUS interrupt requests on,
11-41-11-44
synchronous backplane interconnect
adapter (SBIA), 7-19
in VAX 8600 systems, 1-24
synchronous backplane interconnect
(SBI) bus
registers for, 10-39-10-47
synchronous backplane interconnect
(SBI) expansion cabinets, 7-3
synchronous backplane interconnect
(SBI) bus, 5-12
address space in, 5-19

standard tape interfaces (STI), 2-8

synchronous communication
controller (DEUNA), 2-17

statistical multiplexers, DMF series
of,2-50-2-51

synchronous communications, 2-31
devices for, 2-38-2-47

status register (SR), 11-69-11-72

system base register (SBR),
10-10-10-11

storage subsystems, see mass storage
subsystems
storage transmit controVstatus
register (STXCS), 10-77-10-78
storage transmit data buffer
register (STXDB), 10-79
supervisor stack pointer (SSP)
register, 10-6
switches, DT07-xx UNIBUS interface
switch series, 2-53

system building block (SBB) menus,
1-3
system clocks
registers for, 10-15-10-18
see also clocks
system control block base (SCBB)
address, 11-18
system control block base register
(SCB), 10-12

system control block (SCB),
11-17-11-18
system control panel
on VAX-11/725 systems, 8-11-8-13
on VAX-11/730 systems, 8-20-8-22
on VAX-11/750 systems, 8-24-8-26
on VAX-11/780 systems, 8-34-8-36
on VAX-11/782 systems, 8-51
on VAX 8600 systems, 8-58-8-61
system dump analyzer (SDA), 1-43
system exerciser, 1-41
system identification register
(SID), 1-42, 10-2-10-3
system initialization, of VAX 8600
systems, 8-83-8-86
system length register (SLR), 10-11
System Network Architecture
(SNA; IBM), 2-29-2:30
system restarts
automatic, 1-44, 8-9
in VAX-11/725 systems, 8-19
in VAX-11/750 systems, 8-32
in VAX-ll/780 systems, 8-50
in VAX-11/782 systems, 8-52
system services, in VAXjVMS
operating system, 1-34
system space; registers for,
10-10-10-12
System Startup Service Packages
(SSSPs), 1-5
system traps, register for,
10-13-10-14
.system verification, 1-41

T
T4.1 microprocessors, 8-55
TA78 magnetic tape unit, 2-8
TA81 magnetic tape unit,
12-19-12-20
tape subsystems, see magn~tic tape
subsystems
TE16 niagnetic tape unit, 1-27
telephone lines, 2-31

DF02 and DF03 modems for, 2-57
temperature, environmental
monitoring module for, 7-11
terminal concentrators and
multiplexers, 2-48-2-49
Terminal Server, 2-25
time-of-year clocks, see clocks
time-of-year register (TODR),
10-15-10-16
transceivers
DECOM Ethernet broadband,
2-13-2-15
H4000 Ethernet, 2-18-2-23
transfers, see data transfers
translation buffer check register
(TBCHK), 10-24
translation buffer data register
(TBDA), 10-33-10-34
translation buffer disable register
(TBDR), 10-32-10-33
translation buffer invalidate all
register (TBIA), 10-23
translation buffer invalidate single
register (TRIS), 10-23-10-24
translation buffers, 7-18
see also address translation
buffers
transmissions, asynchronous and
synchronous, 2-31
traps, 1:40'
TS05 magnetic tape unit,
12-23-12-24
TU58 tape cartridge drive
in HSC50 intelligent mass
storage server, 2-9
registers for, 10-26-10-30
in VAX-11/725 systems, 1-7, 8-10
in VAX-11/730 systems, 1-8, 1-10,
3-11,8-20
in VAX-ll/750 systems, 1-14, 8-23
TU77 magnetic tape drive, 1-27,
12-20-12-21
TU78, magnetic tape unit, 1-27,
12-22-12-23

TU80 magnetic tape unit, 1-10,
12-16-12-17
TU81 magnetic tape unit, 1-10,
1-27,12-17-12-18
TXCS (console transmit
controVstatus register),
10-20-10-21, 10-74-10-75
TXDB (console transmit data
buffer register),
10-21-10-22, 10-76-,-10-77

u
UBA control register (UACR),
11-47-11-49
UBA status register (UASR),
11-49-11-51

operation of, 11-10
on small and medium VAX
processors, 11-17-11-24
UDA50 intelligent disk-drive
controller used with, 12-3
in VAX-11/725 systems, 1-7,3-3
in VAX-11/750 systems, 1-15
in VAX-11/780 systems, 1-19
UNIBUS adapter (UBA), 11-1,
11-3, 11-13
address translation in, 11-30
data paths in, 11-16
data transfers paths in,
11-33-11-34
interrupt requests on,
11-41-11-44
registers in, 11-44-11-58
UNIBUS arbitrator, in VAX-11/730
systems, 3-13

UDA50 intelligent disk-drive
controller, 2-1-2-2, 12-3-12-4
in VAX-11/730 systems, 1-8,
1-10,3-7
in VAX-11/750 systems, 1-12,
1-15
in VAX-11/780 systems, 1-19
in VAX 8600 systems, 1-27

UNIBUS asynchronous interfaces,
2-31-2-37

ULTRIX-32 operating system, 1-2,
1-36-1-37
on VAX-11/725 systems, 3-1
on VAX-11/730 systems, 1-11,3-1
on VAX-11/750 systems, 1-15,4-1
on VAX-11/780 systems, 1-20,5-1
on VAX-11/785 systems, 5-1
on VAX 8600 systems, 7-1

UNIBUS map, 3-13, 11-14,
11-18-11-19, 11-21

unattended restarts, 1-44,5-10,
8-9,8-19
UNIBUS, 1-39, 11-1, 11-3-11-5
communication interfaces and
devices, 2-30-2-60
disk-drive subsystems under,
12-9-12-12
error conditions detected by, 1-51
functions of, 11-11-11-17
initialize UNIBUS register for,
10-32
on large VAX processors,
11-25-11-58

UNIBUS expansion cabinets, 4-4,
5-7,7-5
UNIBUS interconnect (UBI), 4-10
UNIBUS interface switch series
(DT07-xx),2-53

UNIX operating system, 1-2, 1-36
see also ULTRIX-32 operating
system
updates, for software, 1-47
upgrades, from VAX-11/780 to
VAX-11/782, 6-1, 6-6
user control register (UCR), 11-108
user environmental test package
(UETP), 1-41
user stack pointer (USP) register, 10-6
user writable control store (WCS),
1-12
see also control store
utility register (UTR),
11-105-11-106

v
VAX-l1 2780/3780 protocol emulator,
1-36
VAX-l1 3271 protocol emulator, 1-36
VAX-11/725 systems, 1-1, 1-5-1-8
console subsystem for, 8-10-8-19
dependability features of,
1-47-1-49
processors in, 3-1-3-5
registers specific to,
10-25~10-29

UNIBUS in, 11-3, 11-17
VAX-11/730 systems, 1-8-1-11
console subsystem for, 8-20-8-22
dependability features of,
1-47-1-49
processors in, 3-1, 3-5-3-21
registers specific to,
10-25-10-29
UNIBUS in, 11-3, 11-17
VAX-11/725 systems and, 1-6,3-2
VAX-11/750 systems, 1-12-1-16
CI750 adapter for, 2-4
Computer Interconnect in, 11-76
console subsystem for, 8-23-8-32
CPU/memory interconnect for,
9-1-9-6
dependability features of,
1-49-1-50
DR32 Device Interconnect in,
11-9, 11-93
MASSBUS in, 11-6, 11-58, 11-59
processors in, 4-1-4-18
registers specific to, 10-30-10-36
RM05 removable-media disk
drive in, 12-13
RP07 fixed-media disk drive in,
12-14
TA 78 magnetic tape unit in, 12-19
TU77 magnetic tape drive in, 12-20
TU78 magnetic tape unit in, 12-22
UNIBUS in, 11-3, 11-17,
11-18-11-20
, VAX-11/751 systems, registers
specific to, 10-30-10-36

VAX-11/780 systems, 1-16-1-20
CI780 adapter for, 2-4
Computer Interconnect in, 11-76
configuration of, 5-5-5-8
console subsystem for, 8-33-8-50
dependability features of,
1-50-1-52
DR32 Device Interconnect in,
11-9, 11-93
MA 780 multiport memory
option for, 1-39
MASSBUS in, 11-58
memory controllers in, 1-38
processors in, 5-1, 5-3, 5-8-5-28
registers specific to, 10-36-10-49
RM05 removable-media disk
drive in, 12-13
RP07 fixed-media disk drive in,
12-14
synchronous backplane
interconnect in, 9-7
TA78 magnetic tape unit in, 2-19
TU77 magnetic tape drive in,12-20
TU78 magnetic tape unit in, 12-22
UNIBUS in, 11-3, 11-25, 11-31
upgrading to VAX-11/782 from, 6-6
in VAX-11/782 systems, 1-21,
6-1,6-3
VAX-11/780 VAXdusters, 1-20
VAX-11/782 systems, 1-21-1-23,
6-1-6-9
console subsystem for, 8-51-8-52
dependability features of,
1-50-1-52
MA780 multiport memory
option in, 1-39
registers specific to, 10-36-10-49
VAX-11/782 upgrade package, 6-6
VAX-11/785 systems, 1-1, 1-23
configuration of, 5-5-5-8
console subsystem for, 8-53-8-54
dependability features of,
1-50-1-52
MA780 multiport memory option
for, 1-39
memory controllers in, 1-38
processors in, 5-1, 5-3-5-4,
5-8-5-28

registers specific to, 10-36-10-49
VAX-l1 RMS, 1-35
VAX 8600 systems, 1-1, 1-23-1-28,
7-1
CI780 adapter for, 2-4
Computer Interconnect in, 11-76
configuration of, 7-3-7-6
console subsystem for, 8-55-8-86
dependability features of,
1-52-1-55
DR32 Device Interconnect in,
11-9, 11-93
MASSBUS in, 11-59
processor organization of,
7-7-7-19
registers specific to,
10-49-10-81
synchronous backplane
interconnect in, 9-7
UNIBUS in, 11-3, 11-25, 11-31
VAX ACMS, 1-34
VAXclusters, 1-2-1-3,2-1-2-10
Computer Interconnect in,
11-76-11-77
Computer Interconnect used
with,11-2
HSC50 intelligent mass storage
server in, 12-2
link interface for, 11-77-11-79
TA78 magnetic tape unit in, 12-19
TU78 magnetic tape unit in, 12-22
VAX-11/750 systems in, 1-12, 1-16
VAX-11/780 systems in, 1-20
VAX 8600 systems in, 1-27, 1-28
VAX Common Data Dictionary, 1-34
VAX DATATRIEVE, 1-34
VAX DBMS, 1-34

VAX systems, 1-29-1-39
dependability of, 1-40-1-55
VAX TDMS, 1-35
VAX/VMS operating system, 1-2,
1-29, 1-33-1-36
consistency checks in, 1-41-1-43
data integrity in, 1-45-1-46
error analysis and recovery
features in, 1-43-1-45
MA780 multiport shared
memory supported by, 5-24
on VAX-11/725 and VAX-11/730
systems, 3-1
on VAX-11/750 systems, 4-1
on VAX-11/780 and VAX-11/785
systems, 5-1
on VAX-11/782 systems, 6-1, 6-3,
6-9
on VAX 8600 systems, 7-1
VAXcluster configurations
supported by, 2-2
VAX privileged registers
controlled by, 10-1
VAX X.25/X.29 Extension Package,
1-35,2-28
VIBA (instruction buffer address
register), 5-14
virtual addresses
translation to physical addresses,
in MASSBUS, 11-65-11-66
see also addresses
virtual address registers
for MASSBUS (VAR), 11-65, 11-67
in VAX-11/780 and VAX-11/785
processors (VA), 5-14
virtual address space registers,
10-7-10-10

VAX DSM, 1-34

visibility (V) bus, 5-12

VAXELN Toolkit, 1-2

visibility registers, 7-10-7-11

VAX .FMS, 1-35

VMS operating system, see
VAX/VMS operating system

VAX privileged registers, see
registers
VAX PSI packet system interface,
1-36
VAX Rdb/ELN, 1-35
VAX Rdb/VMS, 1-35

volumes, access control for, 1-46
VS100 adapter, 1-7
VT100 terminals, 2-48-2-49

w
warm starts, 8-9
W (write) bus, 4-7, 7-12
WCS address register (WCSAR), 11-106 •
WCS data register (WCSDR),
11-106-11-107
writable control store (WCS), 3-8,
3-11
see also control store
writable control store address
register (WCSA), 10-37
writable control store data register
(WCSD), 10-37-10-38
write (w) bus, 4-7, 7-12
write data transfers, in SBI, 9-21
write masked function, 5-21, 9-24

x
X.25, DECnet Router/X.25 Gateway
Server for, 2-28

VAX Hardware Handbook
Volume 1-1986
Reader's Comments
Your comments and suggestions will help us in our continuous effort to
improve the quality and usefulness of our handbooks.
What is your general reaction to this handbook? (format, accuracy, completeness, organization, etc.)

What features are most useful? __________________

Does the publication satisfy your needs? ______________

Whaterrorshaveyoufound? ___________________

Additional comments _____________________

Name
Title
Company

Dept.

Address
City

State

Zip

(staple here)

(please fold here)

IIIII
BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO. 33

MAYNARD, MASS.

POSTAGE WILL BE PAID BY ADDRESSEE

Digital Equipment Corporation
Corporate Communications Group
CFO 1.2/M92
200 Baker Avenue
West Concord, MA 01742

No Postage
Necessary if
Mailed in the
United States