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MISC-684176F5

1986

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Document:	Supermicrosystems Handbook
Order Number:	MISC-684176F5
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Pages:	324
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OCR Text

Supermicrosystems

Handbook

Features

MicroVAX IT
MicroVAX I

.,~~ .

MicroPDP-ll/83
MicroPDP-ll/73
MicroPDP-ll/23

Supermicrosystems Handbook

Features

MicroVAX II
MicroVAX I

mamaama

MicroPDP-ll/83
MicroPDP-ll/73
MicroPDP-ll/23

Digital Equipment Corporation makes no representation that the interconnection of its products in the manner described herein will not infringe on existing or future patent rights, nor do the descriptions contained herein imply the
granting of license to make, use, or sell equipment constructed in accordance
with this description.
Digital believes the information in this publication is accurate as of its publication date; such information is subject to change without notice. Digital is not
responsible for any inadvertent errors.
The following are trademarks of Digital Equipment Corporation: All-In-One,
COMPACTape, Correspondent, CTS-300, DATATRIEVE, DATATRIEVE-ll,
DDCMP, DEC, DECdataway, DECform, DECgraph, DECmail-ll, DECmailer, DECmate, DECmate II, DECmate III, DECnet, DECnet/E, DECservice, DELNI, DIBOL-83, the Digital logo, DMS-300, FMS, FMS-ll,
Internet, J-ll, LAIOO, LA12, LAl20, LA2l0, LA50, Letterprinter, Letterwriter, LN03, LQP03, MicroPDP-ll, MicroPower/pascal, MicroPower/pascal-RSX, MicroPower/Pascal-VMS, Micro/RSTS, Micro/RSX, MicroVAX,
MicroVMS, Packetnet, PDP-ll, P/OS, Professional,Q-bus, Rainbow, ReGIS,
RSTS, RSTS/E, RSX-llM, RSX-llM-PLUS, RSX-llS, RT-ll, RTEM-ll,
ULTRIX, ULTRIX-ll, ULTRIX-32m, UNIBUS, VAX, VAX/VMS, VAX APL,
VAXCDD, VAXDATATRIEVE, VAXDEC/CMS, VAXDECgraph, VAX DEC/
MMS, VAX DECOR, VAX DECslide, VAX DEC/Test Manager, VAX DIBOL,
VAX FMS, VAX GKS/Ob, VAX VTX, VAX-ll DECmail, VAXELN, VMS,
VT100, VT200, VT240, VT24l, VT52, WPS-8.
Ada is a registered trademark of the United States government.
Apple is a trademark of Apple Computer, Inc.
IBM is a registered trademark of the International Business Machines Corporation.
Macintosh trademark is licensed to Apple Computer, Inc.
MUMPS is a registered trademark of Massachusetts General Hospital.
Tektronix is a registered trademark of Tektronix, Inc.
UNIX is a registered trademark of AT&T Bell Laboratories.

Preface
Chapter 1 • Supermicrosystem Overview

Definition of a Supermicrosystem ...................................................... 1-1
Markets/Applications .................................................................. 1-1
NumberofUsers ........................................................................ 1-1
Commonalities among the Supermicrosystems ..................................... 1-2
Q-bus ...................................................................................... 1-2
System Hardware ....................................................................... 1-2
System Options ......................................................................... 1-3
Networks .................................................................................. 1-3
Differences among the Supermicrosystems ......................................... 1-3
Central Processing Units ............................................................. 1-4
System Software ........................................................................ 1-4
Chapter 2 • System Hardware

Introduction ................................................................................. 2-1
CPU Modules ................................................................................ 2-1
KA630 CPU Module .................................................................... 2-3
KD32-AA CPU Module Set ........................................................... 2-4
KD]ll-BFCPU Module ................................................................ 2-5
KD]ll-BB CPU Module ............................................................... 2-6
KDF11-BF CPU Module ............................................................... 2-7
System Enclosures ......................................................................... 2-8
Floorstand Enclosure ................................................................ 2-10
Pedestal, Tabletop, and Rackmount Enclosures .............................. 2-16
Cabinet Enclosure .................................................................... 2-21
Ruggedized Enclosure ............................................................... 2-27
Configurations ............................................................................ 2-27
Standard Systems ..................................................................... 2-28
System Building Blocks ............................................................. 2-28
Packaged Systems ..................................................................... 2-28
Base Systems ........................................................................... 2-28
Information Kits ...................................................................... 2-28
Additional Documentation ............................................................ 2-29

Chapter 3 • System Options
Introduction ................................................................................. 3-1
Memory Options ........................................................................... 3-1
MS630 Memory ......................................................................... 3-1
MSV11-J Memory ....................................................................... .3-1
MSV11-Q Memory ..................................................................... 3-2
MSV11-PMemory ...................................................................... 3-2
Performance Options ..................................................................... 3-3
KEF11-AA Floating-point Processor .............................................. 3-3
FPF11 Floating-point Accelerator .................................................. 3-3
KEF11-BB Character-string Instruction Set ..................................... 3-3
Storage Options ............................................................................ 3-3
RQDX3, RQDX2, and RQDX1 Disk Controllers ............................... 3-4
KDA50 Disk Controller ............................................................... 3-5
RX50 Flexible Disk. .................................................................... 3-6
RD53, RD52, andRD51 FixedDisks .............................................. 3-7
RA81 Fixed Disk ........................................................................ 3-8
RA60 Fixed Disk ........................................................................ 3-9
RC25 Fixed/Removable Disk ...................................................... 3-11
TK50 and TK25 Cartridge Tapes ................................................. 3-12
TSV05 Streaming Tape .............................................................. 3-14
CD Reader andCDROM ............................................................. 3-15
Communications Options .............................................................. 3-17
DZQ 11 Asynchronous Interface .................................................. 3-17
DHV11 Asynchronous Interface .................................................. 3-17
DLVJ1 Asynchronous Interface ................................................... 3-18
DLVE1 Asynchronous Interface .......................... : ...................•... 3-18
DEQNA Synchronous Interface ........................... '" .............. , ...... 3.-18
DMV11 Synchronous Interface ............................................... , ... 3-19
DPV11 Synchronous Interface .................................................... 3-19
KMV11 Synchronous Interface .................................................... 3-20
DRV11-JP Realtime Interface ................................................. : .... 3-20
DRV11-WA Realtime Interface .................................................... 3-20
AAV11 Realtime Interface ......................................................•... 3-20
ADV11 Realtime Interface ......................................................... 3-20
AXV11 Realtime Interface ................. : .........................•.•..... , ..... 3-21
KWV11 Realtime Interface ................................. : .... : .................. 3-21

Terminals, Printers, and Modems ............................... ; .................... 3-21
VT220 Video Terminal .............................................................. 3-23
VT240 and VT241 Graphics Terminals ......................................... 3-23
LA210 Printer .......................................................................... 3-25
LQP03 Letter-quality Printer ...................................................... 3-28
LA120 Printing Terminal ........................................................... 3-30
LA100 Printing Terminal ........................................................... 3-31
LA50 Printer ........................................................................... 3-31
LA12 Printing Terminal ............................................................. 3-32
LN03 Laser Printer ................................................................... 3-33
LCPO 1 Color Printer ................................................................. 3-34
LP25 and LP26 System Printers ................................................... 3-35
DFl12 Modem ......................................................................... 3-36
DF124 Modem ......................................................................... 3-36
DFlOO Modem Enclosure ........................................................... 3-38
Additional Documentation ............................................................ 3-39
Chapter 4 • System Software and Layered Products

Introduction ................................................................................. 4-1
MicroVAX Operating and Development Systems ................................. 4-1
MicroVMS Operating System ....................................................... 4-1
ULTRIX-32m Operating System .................................................... 4-3
VAXELN Development Toolkit ..................................................... 4-4
MicroPDP-11 Operating and Development Systems ............................. 4-8
RSX-11 Family of Operating Systems ............................................. 4-8
RSTS Family of Operating Systems .............................................. 4-10
MicroPowerfPascal Development Toolkit ...................................... 4-12
ULTRIX-ll Operating System .................................................... 4-13
RT-11 and CTS-300 Operating Systems ......................................... 4-15
DSM Operating Systems ............................................................ 4-17
High-level Languages .................................................................... 4-21
BASIC .................................................................................... 4-21
C ........................................................................................... 4-21
COBOL. .................................................................................. 4-22
CORAL-66 .............................................................................. 4-23
DIBOL-83 ............................................................................... 4-24
FORTRAN .............................................................................. 4-24
MUMPS .................................................................................. 4-25

Pascal ..................................................................................... 4-23
VAX Ada ................................................................................. 4-24
VAXAPL ................................................................................ 4-24
VAX BLISS-32 .......................................................................... 4-24
VAXPL/I ................................................................................. 4-24
VAX RPG II ............................................................................. 4-25
Information-management Software ................................................. 4-27
DATATRIEVE .......................................................................... 4-27
DECgraph ............................................................................... 4-27
DECmail-11 ............................................................................ 4-27
FMS (Forms Management System) ............................................... 4-28
INDENT ................................................................................. 4-28
RMS (Record Management System) .............................................. 4-28
VAX ACMS (Application Control and Management System) .............. 4-28
VAX CDD (Common Data Dictionary) .......................................... 4-29
VAX DECslide .......................................................................... 4-29
VAX PRODUCER ..................................................................... 4-29
VAX Rdb/ELN (Relational Database Management System) ............... 4-29
VAX TDMS (Terminal Data Management System) ........................... 4-30
VAX VTX (Videotex) ................................................................. 4-30
Programmer Productivity Tools ...................................................... 4-30
ADE ....................................................................................... 4-30
MENU-II ............................................................................... 4-31
VAX DEC/CMS (Code Management System) .................................. 4-31
VAX DEC/MMS (Module Management System) .............................. 4-31
VAX DEC/Shell ........................................................................ 4-31
VAX DEC/Test Manager ............................................................. 4-32
VAX DECOR ........................................................................... 4-32
VAX GKS/Ob (Graphics Kernel System) ........................................ 4-32
VAX Language-Sensitive Editor ................................................... 4-32
VAX Performance and Coverage Analyzer ..................................... 4-33
Communications Software ............................................................. 4-33
Additional Documentation ............................................................ 4-33

Chapter 5 • Networks
Introduction ................................................................................. 5-1
Types of Systems ........................................................................... 5-1
Stand-alone Systems ................................................................... 5-1
Network-connected Systems ........................................................ 5-3
Digital Network Architecture .......................................................... 5-4
DNA Structures ......................................................................... 5-5
Typical Network Configurations ....................................................... 5-6

Types of Links .................................. ............................................ 5-9
Ethernet Link .............................. ............................................. 5-9
Asynchronous Links .................................... .......... .................... 5-13
Synchronous Links ................................................................... 5-16
Network Software .............................. .......................................... 5-20
DECnet Communications ........................................................... 5-21
Internet Communications .......................................................... 5-21
Packetnet System Interface ........................................................ 5-22
Digital PC Connection ............... ............................... .................... 5-24
IBM and Apple PC Connection ........................................................ 5-24
Additional Documentation .......... ....... ........................................... 5-25
Chapter 6 • Architecture Summary

Introduction ......... ......................................................... ............... 6-1
MicroVAX I Architectural Characteristics ...................................... 6-4
MicroPDP-11 Architectural Characteristics ..................................... 6-5
Address Space and Memory ............................................................. 6-6
Physical-address Space ........................................ ........................ 6-7
Virtual-address Space ... ....................................... ........................ 6-8
Memory Management ...... ................................ ........................... 6-8
Memory Protection ................................................................... 6-10
Registers and Stacks ..................................................................... 6-12
MicroVAX Registers ................................................................. 6-12
MicroVAX Program Counter ...................................................... 6-13
MicroVAX Stack, Argument, and Frame Pointers ............. .............. 6-14
MicroVAX Processor Status Longword .......................................... 6-15
MicroPDP-11 Registers .............................................. ................ 6-15
Processor Status Word ..................... ............................. ............. 6-16
Addressing Modes ........................................................................ 6-17
MicroVAX Addressing Modes ...... ................ ............................... 6-17
MicroPDP-11 Addressing Modes ................................................. 6-19
Exceptions and Interrupts ....................................... ...................... 6-20
Exception and Interrupt Vectors ................................................. 6-21
Processor-priority Levels ............................................... ...........'.. 6-22
Context Switching .... ................................. ............................... 6-22
Processor Operating Modes ........................................................... 6-22
MicroVAX Operating Modes ...................................................... 6-23
MicroPDP-11 Operating Modes .................................................. 6-24

Data Types ................................................................................. 6-25
Instruction Sets ........................................................................... 6-28
MicroVAX Instruction Set .....................................................•.... 6-28
MicroPDP-11 Instruction Set ...................................................... 6-29
Instruction Set Summary ........................................................... 6-31
Additional Documentation ............................................................ 6-58

AppendixA • Q-bus ..................................................................... A-1
Appendix B • Site Preparation and Installation ................................ B-1
AppendixC • Customer Services ................................................... C-1
AppendixD· Documentation .............................................. ·.......... D-1
Glossary ............................................................................ Glossary-1
Index .................................................................................... Index-1

This Supermicrosystems Handbook is a concise reference for Digital's 16-bit
and 32-bit supermicrosystems. It describes the functions of each member of
this group-the MicroVAX II, MicroVAX I, MicroPDP-ll/83, MicroPDP-ll/
73, and MicroPDP-ll/23-and their related options and software.

Chapter 1 provides an overview with sections describing the similarities and
differences among the various supermicrosystems.
Chapter 2 outlines the basic hardware components for each supermicrosystem
along with the types of configurations that are available.
Chapter 3 explains each of the system options that are available. These include
memory, performance options, storage devices, communications devices, terminals, and printers.

Chapter 4 outlines basic system software products for the supermicrosystems,
including operating systems, high-level languages, information management
products, productivity tools, and communications software.
Chapter 5 describes the Digital Network Architecture and how the supermicrosystems implement the architecture with such products as DECnet,
Ethernet, Internet, and Packetnet.
Chapter 6 summarizes the VAX and PDP-ll architectures and how they are
implemented in the MicroVAX and the MicroPDP-ll supermicrosystems.
Appendix A gives a technical description of the 22-bit Q-bus that is the backbone of the supermicrosystems.

Appendix B provides help with the preparation for the supermicrosystem installation and gives some configuring guidelines.
Appendix C covers Digital's extensive Customer Services programs.
Appendix D lists additional reference documentation for MicroVAX and
MicroPDP-ll hardware and software.
Your comments and suggestions will help us in our continuous effort to
improve the quality and usefulness of this handbook. Please complete and
return the Reader Comment Sheet that can be found at the back of this book.

• Definition of a Supermicrosystem
Digital's supermicrosystems are a family of low-cost, medium- to high-performance, 16- and 32-bit computers that are designed for realtime, timesharing,
and batch applications. They each offer a choice of operating systems, highlevel languages, information management software, and programmer productivity tools. The five supermicrosystems described in this handbook are the
32-bit MicroVAX I and MicroVAX II and the 16-bit MicroPDP-ll/23,
MicroPDP-ll/73, and MicroPDP-ll/83.
The MicroVAX I and II implement the 32-bit VAX architecture and a modular
version of the VAX/VMS operating system. This allows them to be compatible
with larger VAX systems and to run programs that have been developed on
these systems.
The MicroPDP-ll/23, MicroPDP-ll/73, and MicroPDP-ll/83 implement the
16-bit PDP-ll architecture and all of the PDP-ll operating systems. This
enables the MicroPDP-ll supermicrosystems to be compatible with larger
Q-bus and UNIBUS PDP-ll systems and to run programs that have been developed on these systems.
Markets/Applications
The supermicrosystems serve the technical customer who requires data processing for a variety of applications in the laboratory, factory, medical, educational, and engineering markets. They also serve the commercial customer
who requires data processing for such applications as small business, office,
banking, legal, insurance, and administration. And because they are fully compatible with software developed for either the VAX or PDP-ll, the supermicrosystems offer Digital's existing customers easy growth and expansion
capabilities.

These supermicrosystems allow users to build distributed processing networks entirely from Digital's systems and components. Each one can be easily
integrated into distributed processing environments with other Digital system products via DECnet or into local area networks with Ethernet.
Number of Users
The number of users that can concurrently share each supermicrosystem is
based upon the type of application that each is running, and on the configuration that is being used.

1-2· Supermicrosystem Overview

The MicroVAX II can accommodate over 30 concurrent, active users
depending on the configuration and application.
• The MicroVAX I can accommodate up to four concurrent, active users
depending on the application.
• The MicroPDP-ll/83 can accommodate over 30 concurrent, active users
depending on the configuration and application.
• The MicroPDP-11/7 3 can accommodate up to 12 concurrent, active users
depending on the application.
• The MicroPDP-11/23 can accommodate up to four concurrent, active users
depending on the application.

• Commonalities among the Supermicrosystems
All of the supermicrosystems use many of the same components. These components include the Q-bus internal data path, several enclosures, some memory
options, storage devices, communications devices, video and printing terminals, and modems. Because they are common components, they allow for easy,
cost-effective migration from one supermicrosystem to another as the customer's application requires. Many times there is no need for reinvestment in
new packaging or options when the processing requirements grow.
Q-bus
The 22-bit Q-bus (or the Q22 bus) is implemented in each of the backplane
assemblies of the supermicrosystems. The Q22 bus is the common communications path for the data, address, and control information that is transferred
between the CPU, memory, and device interfaces. The Q22 bus features fourlevel interrupts and block-mode, direct-memory access addressing for as many
as 4 Mbytes of physical memory on the'MicroPDP-lls and the MicroVAX l,
and as many as 9 Mbytes on the MicroVAX II.
System Hardware
The supermicrosystems are available as complete systems in various types of
configurations. There are five types of supermicrosystem enclosures-floorstand with casters, pedestal, tabletop, rackmount, and a cabinet. Each enclosure contains all of the internal components necessary to start building a
supermicrosystem. These components include either an 8-, 12-, or 14-slot
backplane, dc power supplies, a control panel, an I/O distribution panel, and
two or three cooling fans. These choices vary depending on the enclosure that
is selected. These enclosures can also accommodate a variety of mass-storage
devices.

1-3

System Options

In addition to the basic system hardware, a large assortment of system options
are available for the supermicrosystems. These include memory and performance options, storage devices, communications devices, video and printing
terminals, and modems. All are Q22-bus-compatible.
Because the supermicrosystems share the same bus, most of the options that
are available for one supermicrosystem are also compatible with the others.
This makes system migration and software interchange easier and very economical.
Networks
Digital's Network Architecture (DNA) defines an overall approach to networking and includes a set of software and hardware protocols to support a
range of requirements.

The supermicrosystems and other Digital computers can use DECnet to share
files, programs, and resources. Systems can communicate over traditional
interconnects and over Ethernet for high-speed, local communication. Digital's Ethernet program provides high-level software and advanced hardware
to enable high-speed communications between computer systems and servers
in Local Area Networks (LANs).
By emulating the protocol of other manufacturers' devices, the supermicrosysterns coupled with Internet software can communicate with other vendors'
equipment. IBM batch (2780/3780), interactive (3271), and SNA protocols
are supported, as are those from CDC and UNIVAC.
The supermicrosystems can interface with Digital's Packetnet system for communications through a public packet-switched network (X.25) with other systems, regardless of the manufacturer.
The Professional 300 series, DECmate II and III, and the Rainbow 100 series
of single-user systems can also be connected to the supermicrosystems for file
transfer and terminal emulation.

• Differences among the Supermicrosystems
The MicroVAX and the MicroPDP-ll supermicrosystems are based on different, but related, architectures. Although there are many architectural
similarities between the VAX and PDP-ll system designs, there are some differences as well. Both share such characteristics as use of physical-address
space, some virtual-address space, memory management, general registers,
addressing modes, interrupts, and instruction sets. The designs differ in the
size and type of these characteristics.

1-4 • Supermicrosystem Overview

For example, the MicroVAX supermicrosystems are based on 32-bit word
size, and the MicroPDP-lls are based on 16-bit word size. They each use virtual-address space, but each can address varied sizes of this space. For a more
detailed description of the two supermicrosystem architectures, refer to Chapter 6- Architecture Summary.
Central Processing Units
In order to implement each of the two architectures, the supermicrosystems
each have a unique central processing unit (CPU). All of these CPU models
utilize the Q22 bus, which provides compatibility for all of the supermicrosystem's options. These CPU models represent a wide range of performance and
features. When a supermicrosystem is being selected, the central processor is
an important part of the customer's decision.
System Software
The MicroVAX and MicroPDP-11 supermicrosystems each have system software and layered software products designed specifically for their architectures. They each are supported by a wide range of proven operating systems,
high-level languages, information management products, productivity tools,
and networking products. In fact, many of the same types of system software
have been developed for each of the supermicrosystems. An example of this is
VAX DATATRIEVE for the MicroVAX II and I, and DATATRIEVE-11 for the
MicroPDP-11/83, -11/73, and the -11/23. Refer to Chapter 4-System Software and Layered Products for descriptions of Digital's system software products for the supermicrosystems.

• Introduction
The basic system hardware that each supermicrosystem requires to be a functional system is a CPU, enclosure, memory, communications device, and mass
storage. This chapter discusses the CPU modules, the enclosures, and their
components. This chapter also covers configuring so that the appropriate system and options can be planned and ordered in the easiest and most convenient manner. For detailed configuring information for all of the
supermicrosystems, refer to the VAX Systems and Options Catalog and the
PDP-II Systems and Options Catalog. Ordering information for these publications is provided in Appendix D-Documentation.

• CPU Modules
Each supermicrosystem has a unique central processing unit.
• The KA630 module is the 32-bit MicroVAX II central processing unit.
• The KD32-AA module set is the 32-bit MicroVAX I central processing
unit.
• The KDJll-BF module is the 16-bit MicroPDP-ll/83 central processing
unit.
• The KDJll-BB module is the 16-bit MicroPDP-ll/73 central processing
unit.
• The KDFll-BF module is the 16-bit MicroPDP-ll/23 central processing
unit.
These CPU modules all use the Q22 bus. Coupled with the VAX or PDP-ll
architectures, these CPU modules represent a wide range of performance and
capabilities. Refer to Table 2-1 for a concise listing of each CPU module's functions.

~
...
~

i!I

Table 2·1· CPU Module Features

CPU
Module

V"lrtual
Address
Space

KA630

4 Gbytes

Physical
Address
Space
1 Gbyte

KD32·AA

4 Gbytes

KDJll·BF

Relative
Bootstrap/
Performance Diagnostic
ROM

Serial Lines Cache
Memory

CIS

Floating
Point*

1.00

64 Kbytes

Not required Emulated in D,F,G,H
software

8 Mbytes

0040

8 Kbytes

Emulated in D,F or F,G
software

64 Kbytes

4 Mbytes

0.75

32 Kbytes

8 Kbytes

D,F

KDJll·BB

64 Kbytes

4 Mbytes

0.55

32 Kbytes

8 Kbytes

N/A
N/A

KDFll·BF

64 Kbytes

4 Mbytes

0.25

8 Kbytes

None

Optional

D,F

* Not all floating-point instructions reside in hardware. Refer to Chapter 6, Architecture Summary, for a detailed discussion on the location of
floating-point instructions.

2-3

KA630 CPU Module
The KA630 is a quad-height processor module that is implemented in the 32bit MicroVAX II. It is designed for use in very high-speed, realtime applications and for large multiuser, multitasking environments_ It has three times
the relative performance of the MicroVAX I KD32-AA module set.
The KA630 module provides
• The MicroVAX 78032 microprocessor chip that implements the VAX architecture, including the basic instruction set, demand-paged memory management and translation buffer, and a 32-bit internal/external data path.
• The MicroVAX 78132 floating-point chip that implements 32-bit floatingpoint performance.
• 40-Megahertz clock rate.
• 1 Mbyte of onboard memory.
• Q22-bus interface that supports block-mode DMA transfers and as much
as 16 Mbytes of physical memory (systems are currently limited to 9
Mbytes).
• Q22-bus input/output (I/O) map for DMA transfers.
• 10-millisecond interval timer.
• Time-of-year clock with battery-backup capability.
• One console terminal serial-line unit.
• 64-Kbyte bootstrap/diagnostic read-only memory (ROM).
The KA630 executes a subset of the VAX instruction set. The remainder of
the instructions are emulated in software or on the floating-point chip. Full
22-bit memory management is provided for both instruction and data references (I&D space) in four protection modes-kernel, executive, supervisor,
and user.
Most of the VAX data types are supported by the KA630 including byte,
word, longword, quadword, character string, variable-length bit field,
F_ floating, D_ floating, and G_ floating point data.
The KA630 CPU communicates with mass storage and peripherals via the
Q22 bus. It also communicates with the memory modules through a 10Mbyte/second local memory interconnect in the CD rows of backplane slots
one through three, and through a cable between the CPU and the memory
modules.

2-4· System Hardware

Sdf-diagnostic, light-emitting diodes (LEDs) are provided on the KA630 connectors that indicate the status of the module and system when the module is
powered. The LEDs aid in troubleshooting module failures. The LEDs also
appear on the I/O distribution pando
The KA630 supports all of the MicroVAX operating systems.

KD32-AA CPU Module Set
The 32-bit MicroVAX I processor logic is contained on two quad-height modules-the data-path module (DAP) and memory controller module (MCT).
The data-path module and the memory controller module are electrically connected by a flat cable. These two modules implement the MicroVAX I architecture and are designated as the KD32-AA MicroVAX I CPU. The KD32-AA
module set was designed for use in moderate-speed, realtime applications and
for multiuser, multitasking environments.
The KD32-AA CPU module set provides
• MicroVAX I CPU functions.
• Q22-bus interface that supports block-mode, direct-memory access (DMA)
transfers and as many as 4 Mbytes of physical memory.
• 8-Kbyte, direct-mapped cache memory.
• lO-millisecond interval timer.
• One console terminal serial-line unit.
• 8-Kbyte bootstrap programmable read-only memory (PROM).
The main functions of the data-path module are:
• Decoding and executing macroinstructions.
• Controlling microinstruction flow.
• Processing program interrupts.
• Communicating with the console terminal.
• Communicating with the memory controller module.

2-5

The memory controller module performs the following functions:
• Generates clock signals.
• Controls the memory controller microinstruction flow.
• Translates virtual addresses.
• Accesses the data cache.
• Communicates with the Q22 bus.
The KD32-AA module set supports all of the MicroVAX operating systems.

KDJll-BF CPU Module
The KDJll-BF is a quad-height processor module that is implemented in the
16-bit MicroPDP-ll/83. It is designed for use in very high-speed, realtime
applications and for large multiuser, multitasking environments. It has almost
two times the relative performance of the I6-bit MicroPDP-ll/73 KDJll-BB
module.
The KDJll-BF module provides
• J-II (DCJII) microprocessor chipset including an I8-MHz clock.
• Floating-point accelerator (FPJII) that is standard in hardware, and a floating point instruction set in microcode.
• Complete PDP-ll instruction set including the Extended Instruction Set
(EIS).

• 8-Kbyte, direct-mapped cache memory.
• Q22-bus interface that supports block-mode DMA transfers and as many
as 4 Mbytes of physical memory.
• Line-frequency clock.
• Four levels of interrupts.
• Powerfail/autorestart.
• Console emulator in microcode.
• One console terminal serial-line unit.
• 32-Kbyte bootstrap/diagnostic read-only memory (ROM).

2-6' System Hardware

The KDJll-BF executes the complete PDP-ll integer and floating-point
instruction sets. Full 22-bit memory management is provided for both instruction and data references (I&D space) in three protection modes-kernel, supervisor, and user. The KDJll-BF is fully downward compatible with older PDPlIs that have 18-bit memory management.
The module interfaces with the Q22 bus and can address as many as 4 Mbytes
of main memory. Block-mode DMA transfers are included, which are standard on the Q22 bus. The Q22 bus is fully downward compatible with the
standard 18-bit Q-bus_
The KDJll-BF supports console emulation (micro octal debugging tool or
ODT). This allows users to interrogate and write to main memory, CPU registers, and I/O devices.
The module contains an 8-Kbyte, write-through, direct-mapped cache. The
cache is transparent to all programs and acts as a high-speed buffer between
the processor and main memory. The data stored in the cache represents the
most active portion of main memory being used. The processor accesses main
memory only when data is not available in the cache.
Self-diagnostic LEDs are provided on the KDJll-BF and indicate the status of
the module and system when the module is powered. The LEDs aid in troubleshooting module failures. The LEDsaiso appear on the I/O distribution panel.
TheKDJll-BF module supports all of the MicroPDP-ll family operating systems.

KDJll-BB CPU Module
The KDJll-BB is a quad-height processor module that is implemented in the
16-bit MicroPDP-11/7 3. It is designed for use in high-speed, realtime applications and for multiuser, multitasking environments. It has three times the relative performance of the MicroPDP-ll/23 KDFll~BF module.
The KDJll-BB module provides
• J-ll (DCJll) microprocessor chipset including a 15-MHz clock.
• Floating-point instruction set that is standard in microcode.
• Complete PDP-ll instruction set including the Extended Instruction Set
(EIS).

• 8-Kbyte, direct-mapped cache memory.
• Q22-bus interface that supports block-modeDMA transfers and as many
as 4 Mbytes of physical memory.

2-7

• Line-frequency clock.
• Four levds of interrupts.
• Powerfail/autorestart.
• Console emulator in microcode.
• One console terminal serial-line unit.
• 32-Kbyte bootstrap/diagnostic read-only memory (ROM).
The KD]11-BB and KD]11-BF CPU modules are basically very similar, but do
have a few very important differences. The KD]11-BB runs at a clock rate of
15 megahertz while the KD]11-BF runs at a clock rate of 18 megahertz. This
18-MHzJ-11 chip, coupled with a fast floating-point accderator chip and the
new private memory interconnect, provide system throughput that is three
times faster than the MicroPDP-11/73 KD]11-BB CPU module.
The KD]11-BB executes the complete PDP-11 integer and floating-point
instruction sets. Full 22-bit memory management is provided for both instruction and data references (I&D space) in three protection modes-kernd, supervisor, and user. The KD]11-BB is fully downward compatible with older PDP11s that have 18-bit memory management.
This module interfaces to the Q22 bus and can address as many as 4 Mbytes
of main memory. Block-mode DMA transfers are included, which are standard on the Q22 bus. The Q22 bus is fully downward compatible with the
standard 18-bit Q-bus.
The KD]11-BB supports console emulation (micro octal debugging tool, or
ODT). This allows users to interrogate and write to main memory, CPU registers, and I/O devices.
The module contains an 8-Kbyte, write-through, direct-mapped cache. The
cache is transparent to all programs and acts as a high-speed buffer between
the processor and main memory. The data stored in the cache represents the
most active portion of main memory being used. The processor accesses main
memory only when data is not available in the cache.
Self-diagnostic LEDs are provided on the KD]II-BB and indicate the status of
the module and system when the module is powered. The LEDs aid in troubleshooting module failures. The LEDs also appear on the I/O distribution pando
The KD]11-BB supports all of the MicroPDP-11 operating systems.

KDFll·BF CPU Module
The KDFII-BF is a quad-height processor module that is implemented in the
16-bit MicroPDP-11/23. It is designed for use in moderate-speed, realtime
applications and for multiuser, multitasking environments.

2-8 • System Hardware

The KDF11-BF module provides
• F-ll microprocessor chip_
• Complete PDP-11 instruction set including the Extended Instruction Set
(EIS).
• Floating-point and commercial instruction sets (optional).
• Q22-bus interface that supports block-mode DMA transfers and as many
as 4 Mbytes of physical memory.
• Line-frequency clock.
• Four levels of interrupts.
• PowerfailJautorestart.
• Console emulator in microcode.
• Two serial-line units-one for use as a console terminal and the other for
use with a user terminal or serial printer.
• 8-Kbyte bootstrap/diagnostic read-only memory (ROM).
The KDFll-BF module supports up to 256 Kbytes of memory on an 18-bit Qbus backplane or up to four Mbytes of memory on a Q22-bus backplane.
When used with the Q22 bus, the KDFll-BF uses four-level interrupt protocol. The 22-bit memory management is provided for both instruction and
data references (I&D space) in two protection areas-kernel and user. The
KDFll-BF is fully downward compatible with older PDP-lls that have 18-bit
memory management.
The KDFll-BF supports console emulation (micro octal debugging tool, or
ODT). This allows users to interrogate and write to main memory, CPU registers, and I/O devices.
Self-diagnostic LEDs are provided and indicate the status of the module and
system when the module is powered. The LEDs aid in troubleshooting module
failures. The LEDs also appear on the I/O distribution panel.

The KDFll-BF module supports all of the MicroPDP-ll operating systems.

• System Enclosures
The supermicrosystems are available in a choice of five different system enclosures, as shown in Figure 2-l. Each can accommodate a system chassis, logic
modules, and a choice of integrated mass-storage drives. Most of them are
designed to operate in open-office environments. For detailed information on
any of these enclosures, refer to the VAX Systems and Options Catalog and to
the PDP-II Systems and Options Catalog.

2-9

Floorstand

Rackmount

Cabinet

Figure 2-1 • System Enclosures

2-10 • System Hardware
Floorstand Enclosure

The £loorstand enclosure houses a chassis, shown in Figure 2-2, that includes a
12-slot backplane, 460-watt power supply, control panel, 1/0 distribution
panel, three fans, and shelves for four mass-storage devices. The enclosure
frame is covered by removable panels on the front, right, and left sides. There
are three doors-a control panel door on the front, an I/O distribution panel
door at the rear, and a backplane door inside the right side panel. The four
casters on the bottom of the enclosure allow it to be moved easily. The
MicroVAX II and the MicroPDP-ll/83 are offered in this £loorstand enclosure.

Figure 2-2 • Floorstand Enclosure Chassis
• 12-slot Backplane
The logic modules for the £loorstandenclosure are installed into a 12-slot backplane assembly. This assembly consists of four rows by 12 slots of prewired
connectors and a mounting frame that allows quad- or dual-height logic modules to be easily inserted and removed. There is an additional slot that is
reserved for cable management. The Q-bus is not implemented in this slot. A
card guide permits the latches on the quad-height modules to hold securely
onto the backplane.

2-11

The backplane incorporates the Q22-bus wiring in rows A and B of connector
slots one through twelve and in rows C and D of connector slots five through
twelve. The Q22 bus supports an interrupt and DMA grant-continuity
scheme for the logic modules installed in the backplane. Table 2-2 shows the
assignment for each module in the backplane, and Figure 2-3 shows the Q22bus wiring throughout the backplane.
Four 120-0 resistor packs between backplane slots 12 and 13 are used to terminate the Q22 bus. Refer to Appendix A-Q-bus for detailed information on
120-0 termination on the backplane.
There are threeJ connectors on the backplane.J1 andJ2 are 18-pin connectors
that receive dc power and signals from the two independent regulators in the
power supply. The backplane balances the load on each of the power supply's
two regulators. Regulator A connects to J1, supplying the odd-numbered slots
and the resistor packs. Regulator B connects to J2, supplying the even-numbered slots. The third connector, J3, is a 10-pin connector for a cable to the
CPU console board. The backplane supports a maximum of 38 ac loads and 20
dcloads.

Table 2·2 • 12·slot Logie.module Assignments
Slot

Row

MieroVAXII

MieroPDP.ll/83

ABCD

CPU

PMImemory

ABCD

One-quad-height or one
Additional PM! memory
dual-height memory module.
Dual-height module should
be installed into CD rows.

ABCD

See Slot 2.

CPU

ABCD

Two dual-height options or
one quad-height option.

ABCD

See Slot 4.

ABCD

See Slot 4.

ABCD

See Slot 4.

ABCD

See Slot 4.

ABCD

See Slot 4.

ABCD

See Slot 4.

ABCD

See Slot 4.

ABCD

See Slot 4.

2-12· System Hardware

022

f-- SLOT 1

022

f-- SLOT 2

022

f-- SLOT 3

022

f-- SLOT 4

022

f-- SLOT 5

022

f-- SLOT 6

022

I
I
I

022

I
I
I

022

I
I
I

022

f-- SLOT?

022

I
I
I

022

SLOTa

022

I
I
I
I
I

022

SLOT 9

022
022

I
I
I
I
I

022

SLOT 10

022

I
I
I

022

SLOT 11

022

I
I

022

SLOT 12

022

I
I

Figure 2-3 • Q22-bus Wiring Flow
• 460-WQtt Power Supply

The 460-watt power supply, shown in Figure 2-2, is included with the floorstand enclosure chassis. It consists of two regulators. Each regulator supplies
230 watts, for a total of 460 watts, to one-half of the slots in the backplane, to
the mass-storage devices inside the system chassis, to the control-panel
switches and indicators, and to the three dc fans.

2-13

Features of the 460-watt power supply include
• Universal power supply with switchable inputs for 88-128 V RMS at 120
V/60 Hz and 176-256 V RMS at 240 V/50 Hz.
• Two separate output circuits provide power to the two dc fans that are
external to the power supply, and to the temperature sensor above the
backplane.
• Line voltage conditioning.
• Connector at rear for retnote control of power.
• Circuit breaker at rear for protection of input power.
• Internationally adaptable ac input connector.
• 5 Vdc power rating of 4.5 A minimum to 36 A maximum per regulator.
• 12 Vdc power rating of 0 A minimum to 7 A maximum per regulator .

• Control Panel
The system control panel switches, pushbuttons, and indicator lights are
located at the front of the floorstand enclosure chassis. These controls allow
the user to apply and remove ac power, to stop and start the current program
operation, and to protect the data stored on the disk drives. Refer to Figure 24 for an illustration of the floorstand enclosure control panel.

• I/O Distribution Panel
The I/O distribution panel, located at the rear of the system chassis, is used to
connect the cables from the console terminal, printing terminal, and other
external devices that connect with the system. The I/O distribution panel contains areas to mount connectors for these devices, and also provides signal filtering and shielding against electromagnetic and radio frequency interference
(EMI/RFI). Each module that sends a cable outside the chassis also has a panel
insert that mounts in the I/O distribution panel. The external cable attaches
to a connector on this panel. Panel inserts come in two standard sizes: 1 by 4
inches (Type A) and 2 by 3 inches (Type B). The I/O distribution panel on the
floorstand enclosure chassis has cutouts for four Type A inserts and six Type
B inserts, or seven Type A inserts and four Type B inserts (two of the Type B
inserts can be converted to three Type A inserts).

2-14· System Hardware
With this I/O distribution panel, use of one of the Type B panel inserts is
predefined. This panel insert has one 25-pin EIA connector for the console
terminal. It also includes a rotary switch for selection of the baud rate of the
console device. Two seven-segment LED indicators are used to display an
error code and its location during the self-test diagnostic program and bootstrap routine. The remaining cormeetor panels on this chassis provide 25-pin
EIA connectors to be used when additional device interfaces have been
installed in the unit. Refer to Figure 2-5 for an illustration of the fIoorstand
enclosure I/O distribution panel.

RX50

HALT

WRITE
PROTECT

DCOK
RESTART

RX50

WRITE
PROTECT

WRITE
'----t::::::=::H-PROTECT
~==:::HI-- READY

Figure 2-4 • Floorstand Enclosure Control Panel

2-15

TYPE

"
~

TYPE

DO
[J~[J
,
" "B

--- ~~u~
~

'" '" .

Figure 2-5· Floorstand Enclosure I/O Distribution Panel
• Fans
The floorstand enclosure chassis provides three brushless fans to draw air in
from the top of the enclosure, as shown in Figure 2-2. The flow of air travels
under the backplane, behind the control panel, and then inside the power supply. A printed circuit board above the backplane contains two temperature
sensors. One sensor regulates the speed of the backplane fan at the minimum
level required to maintain a constant temperature within the backplane. The
other sensor shuts down the system at high temperature. If the proper temperature within the backplane cannot be maintained, even at maximum fan
speed, the over-temperature sensor will cause the system to shut down. The
system also shuts down if the backplane fan fails. Power for the fans is provided by the power supply.

2-16 • System Hardware

Pedestal, Tabletop, and Rackmount Enclosures
The pedestal and tabletop enclosure houses a chassis, shown in Figure 2-6,
that includes an 8-slot backplane, 230-watt power supply, control panel, I/O
distribution panel, two fans, and space for two mass-storage devices. The
enclosure comprises an outer shell and includes a front cover and rear I/O distribution panel cover. The pedestal version includes a base that attaches to the
bottom. The MicroVAX II, MicroVAX I, MicroPDP-ll/73, and MicroPDP11/23 are offered in these enclosures.
The rackmount enclosure houses the same chassis as the pedestal and tabletop
enclosures and can be installed into a 19-inch-wide (48.26-centimeter) rack or
cabinet and contains a front cover and chassis cover. The mounting hardware
for installation into the rack is also included. The MicroVAX II, MicroVAX I,
MicroPDP-ll/73, and MicroPDP-ll/23 are offered in this rackmount enclosure.
Q·BUS MODULES

1/0 DISTRIBUTION PANEL INSERT

BACKPLANE
SIGNAL DISTRIBUTION BOARD

RD-SERIES
DISK

FANS

RX50

CONTROL PANEL

Figure 2-6 • PedestalrrabletopfRackmount Enclosure Chassis
• 8-slot Backplane
The logic modules for the pedestal, tabletop, and rackmount enclosures can be
installed in the 8-slot backplane assembly. This assembly consists of four rows
by eight slots of prewired connectors and a mounting frame that allows quador dual-height logic modules to be easily inserted and removed. A card guide
also permits the latches on the quad-height modules to hold securely onto the
backplane.

2-17

The backplane incorporates the Q22-bus wiring in rows A and B of connector
slots one through eight and in rows C and D of connector slots four through
eight. The Q22 bus supports an interrupt and DMA grant-continuity scheme
for the logic modules installed in the backplane. Table 2-3 shows the assignment for each module in the backplane, and Figure 2-7 shows the Q22 bus
wiring throughout the backplane.
This backplane provides 240-0 far-end termination for the MicroVAX II,
220-0 far-end termination for the MicroVAX I, and 120-0 far-end termination for the MicroPDP-ll systems. Refer to Appendix A-Q-bus for detailed
information on bus termination on the backplane.
Four connectors on the backplane, Jl throughJ4, receive voltages and signals
from the power supply and provide signals and voltages to the front control
panel of the system unit. This backplane supports a maximum of 30 ac loads
and 20 dc loads.

....'00:->

Table 2-3 • 8-slot Logic-module Assignments
Slot Row
1
2

ABCD
ABCD

MicroVAXI

MicroPDP-ll/73

MicroPDP"11/23

CPU

CPU
CPU

CPU

Memory

a..

One quad-height
or one dual-height
memory module.
Dual-height module
should be installed
into CD rows.

~
~

ABCD

See Slot 2.

ABCD

Additional memory
Two dual-height
options or one quad- or communications
option.
height option.

ABCD

See Slot 4.

Two dual-height
See Slot 4.
options or one quadheight option.
RQDXl if it is the
last-used slot.

See Slot 4.

ABCD
ABCD
ABCD

See Slot 4.

See Slot 5.

See Slot 4.

See Slot 5.

See Slot 4.

See Slot 5.

See Slot 4.

~
..,

MicroVAXn

Memory

Additional memory
or communications
option.

Two dual-height
Two dual-height
options or one quad- options or one quadheight option.
height option.

2-19

I
I

022

,,I

022

,,
I

022

,,
,
,
I
,

022

,
,

022

,,
,
,,,

022
022

ROW

I
I

022

,,I

022

022
022
022
022
022
022

,
,,,
,,,
,,

,,
,
,
I
,
,

I
I

022

,
I
,
,,

022

,
,I
,,

I
I

-f-- SLOT 1

-r- SLOT 2

-r- SLOT 3

022

,-r- SLOT 4

022

-f-- SLOT 5

022

-f-- SLOT 6

022

I-r- SLOT 7

022

:-r- SLOTS

022

,
,

022

I
I

,
,
,I

Figure 2-7 • Q22-bus Wiring Flow
• 230-watt Power Supply
The 230-watt modular power supply, shown in Figure 2-6, is included with
the pedestaljtabletopJrackmount enclosure (hereafter referred to as the pedestal enclosure) chassis. It drives 230 watts of power to the logic modules
mounted in the system backplane, to the disk-drive units, to the control-panel
switches and indicators, and to the two dc fans.
Features of the 230-watt power supply include
• Universal supply with switchableinputs for 88-128 V RMS at 120 V/60 Hz
and 176-256 V RMS at 240 V/50 Hz.
• Separate output circuit for the two dc fans.
• Line voltage conditioning.
• Q22-bus compatible power sequencing signals.
• 5 Vdc power rating of 4.5 A minimum to 36 A maximum.
• 12 Vdc power rating of 0 A minimum to 7 A maximum.

2-20 • System Hardware

Additional 230-watt power supply features include thermal shutdown, overvoltage and overcurrent protection, ac input transient supression, and three
signals for Q22-bus operation .

• Control Panel
The system control switches, pushbuttons, and indicator lights are located on
the control panel at the front of the pedestal enclosure chassis. These controls
allow the user to apply and remove ac power, to stop and start the current
program operation, and to protect the data stored on the disk drives. Refer to
Figure 2-8 for an illustration of the pedestal enclosure control panel.

~D~DDmD

0
R,"
Halt

DC OK

•

Restart

~~
[§I] ~
FlxedOlskO

WnleProtecl

Removable Disk

Wnte

Protect

Ready

• •
1

Figure 2-8 • Pedestal Enclosure Control Panel
• I/O Distribution Panel
For a functional description of the I{O distribution panel, refer to the floorstand enclosure.
A specific feature of the I{O distribution panel that is found in the pedestal
enclosure is that it has cutouts for two Type A inserts andfourType B inserts,
orfive Type A inserts and two Type B inserts (two of the Type B inserts can
be converted to three Type A inserts).

2-21

With this I/O distribution panel, one of the Type B panel inserts is
predefined. On all of the supermicrosystems, except for the MicroPDP-ll/23,
this panel insert has one 25-pin EIA connector for the console terminal. It also
includes a rotary switch for selection of the baud rate of the console device.
Two seven-segment LED indicators are used to display an error code and its
location during the self-test diagnostic program and bootstrap routine. The
MicroPDP-ll/23 has two 25-pin EIA connectors for the console terminal and
a video or printing terminal. The remaining connector panels on the system
chassis provide 25-pin EIA connectors to be used when additional device interfaces have been installed in the units. Refer to Figure 2-9 for an illustration of
the pedestal enclosure I/O distribution panel.
MicroPDP-ll 123
I/O DISTRIBUTION PANELS

MicroVAX II, MicroVAX I, and MicroPDP·11/73
1/0 DISTRIBUTION PANELS

OPTION 1

01
/

, 10

1':1

I~i

.
oc::J

lo~

~ol

OPTION 2

:0 •

,, ,,

050,
,, ,

•

I
I
I
I

I
I

I
I
I
I

(:[

\I~ I

Figure 2-9· Pedestal Enclosure I/O Distribution Panel
• Fans
Two brushless fans within the pedestal enclosure provide a flow of air from
left to right (side-to-side) to cool the internal assemblies and modules as shown
in Figure 2-6. Power for the fans i~ provided by the power supply.

2-22 • System Hardware

Cabinet Enclosure
The MicroVAX II and MicroPDP-ll/83 ate also available in a 42-irtch-high
(106-centimeter) cabinet. The cabinet enclosure houses a chassis, shown in
Figure 2-10, that includes two of the 8-slot backplanes for a total offering of
14 backplane slots (two slots are not operational), two 230-watt power supplies, two control panels, one large I/O distribution panel, four fans, and space
for four 5.25-inch storage devices and two 14-inch'storage devices.
a-BUS MODULES
1/0 DISTRIBUTION PANEL INSERT

BACKPLANE
SIGNAL DISTRIBUTION BOARD

RD-SERIES
DISK

RX50
FANS

CONTROL PANEL

Figure 2-10· Cabinet Enclosure Chassis
• Dual Backplanes
The logic modules for the cabinet enclosure can be installed into the dual 8slot backplane assembly. This assembly consists of two sets of four rows by
eight slots of prewired connectors and a mounting frame that allows quad- or
dual-height logic modules to be easily inserted and removed. A card guide on
each backplane permits the latches on the quad-height modules to hold
securely onto it.

2-23

Each backplane incorporates the Q22-bus wiring in rows A and B of connector slots one through eight and in rows C and D of connector slots four
through eight. The Q22 bus supports an interrupt and DMAgrant-continuity
scheme for the logic modules installed in the backplane. Table 2-4 shows the
assignment for each module in the backplane, and Figure 2-11 shows the
Q22-bus wiring throughout the backplane.
The CD rows of slots one through three in the upper 8-slot backplane implement a MicroVAX II local memory interconnect. These slots should only be
used for the KA630 CPU module and MS630 memory modules.
The PMI memory module in the MicroPDP-11/83 must reside in the first slot
of the upper 8-slot backplane. The MicroPDP-11/83 CPU module must follow
the PMI memory module in the second slot. If an additional PMI memory is
added, it must reside in the second slot, followed by the CPU in the third.
The dual backplanes provide 240-0 far-end termination for the MicroVAX II
and 120-0 far-end termination for the MicroPDP-ll/83. Refer to Appendix
A-Q-bus for detailed information on bus termination on the backplane.
Four connectors on each backplane, ] 1 through] 4, receive voltages and signals
from the power supplies and provide signals and voltages to the front control
panel of the system unit. The dual backplanes support a system tOlal of ;4 ae
loads and 20 dc loads. dc loads should be balanced between the two backplanes.

2-24 • System Hardware

Table 2-4 • 14-slot Logic-module Assignments
Slot

Row

MicroVAXn

MicroPDP-ll/83

ABCD

CPU

PMImemory

ABCD

One quad-height or one PMlmemory
dual-height memory
module_
Dual-height module
should be installed into
CD rows.
CPU

ABCD

See Slot 2.

ABCD

TSV05 tape controller or TSV05 tape controller or
one quad-height or two one quad-height or two
dual-height options.
dual-height options.

ABCD

One quad-height or two One quad-height or two
dual-height options.
dual-height options.

ABCD

See Slot 5.

ABCD

See Slot 5.

Reserved

ABCD

M9404 Interconnect
Module

Reserved

ABonly M9505 Interconnect
Module

M9504 Interconnect
Module

ABCD

KDA50 disk controller
or one quad-height
option or two dualheight options.

KDA50 disk controller
or one quad-height
option or two dualheight options

ABCD

KDA50 disk controller
or one quad-height
option or two dualheight options.

ABCD

See Slot 5.

ABCD

See Slot 5.

ABCD

See Slot 5.

ABCD

See Slot 5.

ABCD

See Slot 5.

Refer to the MicroVAX and MicroPDP-ll Technical Manuals for further
configuration guidelines. Ordering information for these manuals is provided in Appendix D, Documentation.

2-25

--"'-

022

ROW

022

f- SLOT 3

022

f- SLOT 4

022

f- SLOT 5

022

f- SLOT 6

022

f- SLOT 7

022

f-- SLOT 8

.---"'--

ROW

022

f- SLOT 1

022

f- SLOT 2

022

f- SLOT 3

022

f-- SLOT 4

L--

0
I

SLOT 1

C- SLOT 2

022

t- SLOT 5

022

t- SLOT 6

022

t- SLOT 7

022

t- SLOT 8

Figure 2-11 • Q22-bus Wiring Flow
• Power Supplies
Two 230-watt power supplies, shown in Figure 2-10, are included with the
cabinet enclosure. For a functional description of the 230-watt power supply,
refer to the pedestal enclosure.

2-26 • System Hardware

• Control Panels
The system control switches, pushbuttOns, and indicator lights are located on
the two control panels at the front of the cabinet enclosure. These controls
allow the user to apply and remove ac power, to stop and start the current
program operation, and to protect the data stored on the disk drives. Refer to
Figure 2-12 for an illustration of these control pands.
MAIN
CONTROL
PANEL

Hall

lGJ [G]
Ready

~
EXPANSION
CONTROL
PANEL

~DmDDmD

Fixed Disk 0
Write Protect

Run

MicroVAX

Restart

De OK

Fixed Disk 1
Write Protect

lGJ
Ready

OeOK

Figure 2-12· Cabinet Enclosure Control Panels
• I/O Distribution Panel (H3490)
For a functional description of the I/O distribution pand, refer to the floorstand enclosure.
A specific feature of the I/O distribution panel that is found in the cabinet
enclosure is that it has cutouts for six Type A inserts and 11 Type B inserts.
With this I/O distribution pand, one of the Type B pand inserts is
predefined. This pandinsert has one 25-pin EIA connector for the console
terminal. It also includes a rotary switch .for sdection of the baud rate of the
console device. Two seven-segment LED indicat9rs are used to display an
error code and its location during the sdf-test diagnostic program and bootstrap routine. The remaining connector panels on this I/O distributionpand
provide 25-pin EIA connectors to be used when additional device interfaces
have been installed in the unit. Refer to Figure 2-13 for an illustration of the
cabinet enclosure I/O distribution panel.

2-27

.I"l'r-W- I ' I I T"n\ffi

~~~~
~D+ ~D+ ~
~'
+

:DH!lE
+

•

~ ~'",~----""''---' ;IL___----..JIlt)

"---------'I@;'-I----"I@;LI___-<8;'-I___-"I@
Figure 2-13 • Cabinet Enclosure I/O Distribution Panel (H3490)
• Fans
Four brushless fans within the cabinet enclosure draw air from the cabinet's
left-side panel, into the two system chassis, and out to the rear of the system
chassis through the cabinet's right-side panel. Power for the fans is provided
by the two 230-watt power supplies.
Ruggedized Enclosure

The MicroPDP-ll/73 and MicroPDP-ll/23 are also offered in an enclosure
for use in harsh manufacturing or industrial environments. This ruggedized
enclosure is resistant to the effects of airborne particles, temperature and
humidity, mechanical shock, and vibration. They can be installed on or under
a bench, table, or shelf to create local information centers on the manufacturing floor. And these systems can be configured to accommodate a wide variety
of manufacturing applications. Refer to Appendix D-Documentation for literature on this special MicroPDP-ll configuration.

• Configurations
Each of the supermicrosystems is available in a variety of configurations. This
section briefly describes each of the configuring methods. Detailed configurating information can be found in the VAX Systems and Options Catalog and the
PDP-ll Systems and Options Catalog. Copies of these publications can be
obtained from your local Digital sales representative or by ordering them
direct from Digital. Refer to Appendix D for information on how to order
dOC\.lmentation.

2-28· System Hardware

Standard Systems
The standard system is a very simple method to select a hardware and software supermicrosystem configuration. Standard systems are available for the
MicroVAX II, MicroPDP-11/83, and the MicroPDP-11/73. A standard system
includes the CPU module, memory module, enclosure, power cord, documentation, diagnostics, mass-storage device, load device, and communications
device. Each of the remaining components that a supermicrosystem requires
may be selected from optional menus. Menu categories include operating-system license, additional memory, additional communications, a console terminal, user terminals, printers, and cables.
System Building Blocks
The system building block is also a very simple way to select a hardware and
software supermicrosystem configuration. System building blocks are available for the MicroVAX II, MicroVAX I, MicroPDP-ll/83, and the MicroPDP11/73. A system building block starts with a kernel, which includes a CPU
module, memory module, and an enclosure. Each of the remaining components that a supermicrosystem requires must be selected from its own specific
menu. The menu categories are mass-storage device, load device, communications device, power cord, documentation, diagnostics, operating-system
license, console terminal, terminals, printers, and cables. System building
blocks are flexible because they offer a wide range of components, are customer-tailorable, and also make configuring very easy.
Packaged Systems
The packaged system allows MicroPDP-11/23 customers to choose a preconfigured hardware and software configuration. Each packaged system includes
a CPU module, memory module, enclosure, main-storage device, load device,
and communications device. The operating system must be ordered separately.
Base Systems
The base system is a method of selecting a MicroPDP-11/73 and MicroPDP11/23 system with a preconfigured CPU module, memory module, enclosure,
mass-storage device, and load device.
Information Kits
User documentation and customer-runnable diagnostics come in an information kit. These information kits are only available in standard systems.
Consult your Digital sales representative or refer to the VAX Systems and
Options Catalog or PDP-II Systems and Options Catalog for specific information kit ordering details on documentation and diagnostics that are not packaged in information kits.

2-29

• Additional Documentation
The supermicrosystem hardware documentation must be ordered by type of
enclosure. The following list breaks down the manuals by enclosure.
F100rstand Version

Micro VAX II Technical Manual
Micro VAX II Owner's Manual
MicroPDP-ll System TechnicalManual

AZ-FE09A-TN
AZ-FEOSA-TN
AZ-FEOIA-TC

MicroPDP-ll Owner's Manual

AZ-FEOOA-TC

Pedestal, Tabletop, and Rackmount Versions

Micro VAX II Technical Manual

AZ-FE06A-TN

Micro VAX II Owner's Manual
Micro VAX I CPU Technical Description
Micro VAX I CPU Owner's Manual

AZ-FE05A-TN
EK-KD32A-ID
EK-KD32A-OM

MicroPDP-ll System TechnicalManual
MicroPDP-ll System Owner's Manual

EK-MIC11-TM
EK-MIC11-0M

Cabinet Version

Micro VAX II Technical Manual
Micro VAX II Owner's Manual
MicroPDP-ll System TechnicalManual

AZ-GMBAA-MN
AZ-GMCAA-MN
AZ-GNIAA-MC

MicroPDP-ll Owner's Manual

AZ-GN2AA-MC

2-30 • System Hardware

Chapter}'- System Options

• Introduction
Once a basic supermicrosystem configuration is selected, the hardware
options that best suit the application must also be chosen. These options
include memory, options which enhance the system's performance, storage
devices, communications devices, terminals, printers, and modems. Most of
these options are compatible with every supermicrosystem. All of the options
required to complete or expand a supermicrosystem are described in this chapter.

• Memory Options
There are several memory options that are available for the supermicrosysterns-the MS630 series for the MicroVAX II and the MSVll series for the
MicroVAX I and MicroPDP-ll systems. These memory options can often
improve system performance. Each provides the capability to perform directmemory access. During direct-memory access operations, data is transferred
without processor intervention using block-mode transfers. As many as 16
words or 36 bytes of information can be transferred by specifying a starting
address.
MS630 Memory
The MS630 series is a set of random-access memory (RAM) modules supporting the local memory interconnect of the MicroVAX II processor. The following are the main features of the MS630 series:

• Offers 1 Mbyte of MOS memory on a single, dual-height module (MS630AA), or 2 or 4 Mbytes (MS630-BA, MS630-BB) on a single, quad-height
module.
• Uses 256-Kbyte MOS RAM integrated circuits.
• Supports 24-bit addressing for as many as 16 Mbytes of physical memory
(systems are currently limited to 9 Mbytes).
• Supports block-mode DMA transfers.
MSVll-J Memory
The MSVll-J is a single, quad-height memory module supporting the private
memory interconnect of the MicroPDP-ll/83 KDJll-BF processor. The following are the main features of the MSVll-J series:

3-2 • System Options

• Offers 1 Mbyte (MSVll-JD) or 2 Mbytes (MSVll-JE) of PMI ECC MOS
memory on a single, quad-height module.
• Uses 256-Kbyte RAM integrated circuits.
• Supports 22-bit addressing for as many as 4 Mbytes of physical memory.
• Supports block-mode DMA transfers.
• Has LEDs for parity-error indication.

MSVII-Q Memory
The MSVll-Q series is a set of random-access memory (RAM) modules. The
following are the main features of the MSVll-Q series:
• Offers 1,2, or 4 Mbytes (MSVll-QA, -QB, -QC) of Mas memory on a
single, quad-height module.
• Uses 64-Kbyte (MSVll-QA) or 256-Kbyte (MSVll-QB, -QC) MOS RAM
integrated circuits.
• Supports 22-bit addressing for as many as 4 Mbytes of physical memory.
• Supports block-mode DMA transfers.
• Has LEDs for parity-error indication.

MSVll-P Memory
The MSVll-P series is a set of random-access memory (RAM) modules. The
following are the main features of the MSVll-P series:
• Offers 256 Kbytes (MSVll-PK) or 512 Kbytes (MSVll-PL) of Mas memoryon a single, quad-height module.
• Uses 64-Kbyte Mas RAM integrated circuits.
• Supports 18-bit or 22-bit addressing for as many as 4 Mbytes of physical
memory.
• Supports block-mode DMA transfers.
• Has LEDs for parity-error indication.

3-3

• Performance Options
Three options are available to enhance the performance of the MicroPDP-ll/
23. A floating-point processor and floating-point accelerator are available for
applications that require a great deal of calculation. The MicroPDP-ll/83 and
MicroPDP-ll/73 have floating-point instructions in microcode, and the
MicroPDP-ll/83 has additional floating-point instructions in hardware.
A character-string instruction set (Commercial Instruction Set) is also offered
for business applications.
KEFll-AA Floating-point Processor
KEFll-AA is a single- and double-precision floating-point option. This option
expands the capability of the MicroPDP-ll/23 by adding the microcode to
implement PDP-II floating-point instructions. The microcode resides in two
chips in one 40-pin package that mounts directly on the CPU module. It perf Jrms operations on 32-bit and 64-bit floating-point numbers and provides up
:0 17 digits of precision. KEFll-AA also provides integer to floating-point
conversions.
FPFll Floating-point Accelerator
FPFll is a single-precision and double-precision fast floating-point hardware
option that executes instructions approximately six times faster than the
KEFll-AA. This option is a single, quad-height module for the MicroPDP-ll/
23 and mounts adjacent to the CPU. FPFll performs hardware operations on
32-bit and 64-bit floating-point numbers and provides up to 17 digits of precision. Like the KEFll-AA, it provides integer to floating-point conversions.
KEFll-BB Character-string Instruction Set
The KEFll-BB implements a set of 27 commercial instructions on a variety of
data types, including character-string, packed-decimal, and numeric formats.
Because these data types closely resemble those used in COBOL, they are
referred to as the Commercial Instruction Set (CIS). KEFll-BB mounts
directly on the MicroPDP-l1/23 CPU board.

• Storage Options
Many storage options are available for the supermicrosystems. These options
are offered in several different technologies so that the correct choice can be
made for the storage application. Whether storage is being added for media
backup, for loading software, for main storage, or for software interchange
with another system, Digital has the appropriate storage device for the task.

3·4 • System Options

RQDX3, RQDX2, and RQDXl Disk Controllers
The RQDX series is a set of intelligent controllers that provide data transfers
between the Q22 bus and the RX50 flexible-disk drive and the RD· series of
fixed-disk drives. These controllers contain logic that provides the necessary
data buffering and control to allow direct·memory access (DMA) transfers
using the Mass Storage Control Protocol (MSCP).
A flat cable attaches to a 50-pin connector mounted at the edge of the module
and to the signal distribution board located near the Q22-bus backplane. Sig·
nals and data are then transferred from the connectors on the distribution
board to the disk-drive assemblies. Four LED indicators are also mounted
near the edge of the module to display octal codes during the self-test program
operation.
The following are the main features of the RQDX series:
• Controls up to four logical disk-drive units-one flexible-disk drive and up
to two fixed·disk drives or a total of four fixed-disk drives (RQDX3 and
RQDX2 only).
• Supports block-mode DMA data transfers.
• Quad-height module size for the RQDXl and RQDX2. Dual.height module size for the RQDX3.
• Has maintenance self·test programs.
• Uses LEDs for parity-error indication.
Refer to Table 3-1 for a concise listing of the RQDX series features.
The RQDX3 and the RQDX2 are supported on the MicroVAX II and the
MicroPDP-ll systems. The RQDXl is supported on the MicroVAX I.

3-5

Table 3-1 • RQDX Series Features

RQDXl

RQDX2

RQDX3

Buffered Seeks

y
y

Physical Sector Skew

Maximum Number of Logical
Units

Maximum Number of Hard
Disks

RX50 Disk Support

RD51 Disk Support

RD52 Disk Support

RD53 Disk Support

y
y

Quad

Dual

Feature

Elevator Seek Algorithm

Module Size
Required to be in Last Slot of
Backplane

KDA50 Disk Controller
The KDA50 is an intelligent controller that interfaces up to four RA- series
disk drives with the MicroVAX II and the MicroPDP-ll/83. Two quad-height
modules, the Standard Disk Interconnect (SDI) module and the processor
module, make up the KDA50. The SDI module is the communications interface between the KDA50 processor module and the disk drives. The processor
module is the control portion of the KDA50.

Two flat cables attached to a 40-pin and 50-pin connector tie together the two
modules. An internal SDI cable connects the KDA50 modules to the signal
distribution board located near the Q22-bus backplane. Signals and data are
then transferred from the connectors on the distribution board to the diskdrive assemblies. Four LED indicators are also mounted near the edge of the
module to display octal codes during the self-test program operation.
The following are the main features of the KDA50:
• Controls as many as four RA- series (RA81, RA60) disk drives in a radial
connection.
• Supports block-mode DMA transfers.
• Has maintenance self-test programs.
• Uses LEDs for parity-error indication.

3-6 • System Options

RX50 Flexible Disk
Programs and data can be moved in and out of the supermicrosystems through
the RX50 flexible-disk drives (shown in Figure 3-1). The RX50 is a single unit
that contains two separate drives. Each·of the two drives in the RX50 operate
with a 5.25-inch flexible disk and provide a storage total on both disks of as
many as 819.2 Kbytes of formatted data. Access to the drive is through the
two doors located at the front of the drive unit.
The RQDX controller module, located in the Q22-bus backplane, provides
the interface between the Q22 bus and the RX50 flexible-disk drive. The controller implements the required MSCP protocol and controls the DMA data
transfers. The RX50 operates with dc power supplied from the power supply.
The following are the main features of the RX50:
• 819.2 Kbytes total formatted capacity (409.6 Kbytes formatted capacity
per diskette) .
• Two surfaces on a single spindle.
• 250 Kbits/second (31.25 Kbytes/second) average transfer rate.
• 164 milliseconds average seek time.
• Available in integrated, tabletop, and rackmount models.

Figure 3-1 • RX50 Flexible-disk Drive

3-7

RD53, RD52, and RD51 Fixed Disks
The RD53, RD52, and RD51 fixed-disk drives are compact, Winchester disk
drives (the RD53 is shown in Figure 3-2) that provide reliable mass-data storage for the supermicrosystems. The drives contain double-sided, 5.25-inch,
nonremovable disks enclosed in a sealed assembly. A microprocessor within
each of the units controls the data transfers.
The RD53 has 2.3 times the capacity and 33 percent faster average access
times than the RD52, making it possible to support larger applications and/or
more users. The RD53 can store up to 71 Mbytes of formatted data. It
requires an RQDX3 or RQDX2 controller module. The RD52 disk drive can
store as many as 31 Mbytes of formatted data, and the RD51 disk drive can
store as many as 11 Mbytes of formatted data. Each requires either an
RQDX3, RQDX2, or RQDXl controller module.
The RQDX series controller module, located in the Q22-bus backplane, acts
as the interface between the Q22 bus and the disk-drive units. The controller
module establishes the required MSCP protocol to allow direct-memory access
between the CPU, memory, and the disk-drive units. The RD53, RD52, and
RD51 units operate from the dc power of the power supply.
The following are the main features of the RD53:
• 71 Mbytes formatted capacity.
• Eight recording surfaces (heads) on a single spindle.
• 5 Mbits/second (625 Kbytes/second) peak transfer rate.
• 30.0 milliseconds average access time.

• Available in integrated, tabletop, and rackmount models.
The following are the main features of the RD52:
• 31 Mbytes formatted capacity.
• Eight recording surfaces (heads) on a single spindle.
• 5 Mbits/second (625 Kbytes/second) peak transfer rate.
• 53 milliseconds average access time.
• Available in integrated, tabletop, and rackmount models.

3-8 • System Options

The following are the main features of the RD51:
• 11 Mbytes formatted capacity.
• Four recording surfaces (heads) on a single spindle.
• 5 Mbits/second (625 Kbytes/second) peak transfer rate.
• 93.3 milliseconds average access time.
• Available in integrated, tabletop, and rackmount models.
• Available on MicroPDP-11 and MicroVAX I only.

Figure 3-2 • RD53 Fixed-disk Drive
RA81 Fixed Disk
The RA81, shown in Figure 3-3, is a high-capacity (456 Mbytes formatted),
rackmounted, Winchester fixed-disk drive for the cabinet enclosure. It is
known for its outstanding data reliability characteristics, including an industry-leading 170-bit error-correction code (ECC). It requires the KDA50 controller module set.

3-9

The following are the main features of the RA81:
• 456 Mbytes formatted capacity_
• Read/write system employing an encoding/decoding scheme that yields
one-third more storage capacity than drives using conventional encoding.
• Dual ports.
• 2.2 Mbytes/second peak transfer rate.
• 36.3 milliseconds average access time.

Figure 3-3 • RA81 Fixed-disk Drive
RA60 Removable Disk
The RA60, shown in Figure 3-4, is a high-capacity (205 Mbytes formatted),
rackmounted, removable-disk drive for the cabinet enclosure. The RA60 disk
drive uses enhanced servo technology to elminate the need for alignment
packs. It also incorporates new recording methods, microprocessor-controlled
diagnostics, a 170-bit error-correction code, and a modular design for easy
maintenance.

The following are the main features of the RA60:
• 205 Mbytes formatted capacity.
• Enhanced servo technology-eliminates the need for alignment packs.
• Dual ports.
• 1.98 Mbytes/second peak transfer rate.
• 50.3 milliseconds average access time.

3-10· System Options

Figure 3-4· RA60 Removable-disk Drive

3-11

RC2S Fixed/Removable Disk
The RC25, shown in Figure 3-5, is a 26-Mbyte, Winchester fixed-disk unit
combined with a 26-Mbyte, sealed removable-cartridge disk unit for a total of
52 Mbytes. It is intended for use as a data storage device only. The RC25 contains its own intelligent controller and onboard microdiagnostics for maintenance. The removable-cartridge portion of the disk provides a one-to-one
backup ratio. A second RC25 can be added to give the subsystem a total of
104 Mbytes of storage. The second RC25 does not require a controller.
Exceptional data reliability and integrity features include a powerful 170-bit
error detection and correction code, automatic retry and revectoring, embedded servos, and bad-block replacement.
The following are the main features of the RC25:
• 52 Mbytes formatted capacity.
• Four surfaces on a single spindle.
• 1,250 Kbytes/second peak transfer rate.
• 45.5 milliseconds peak access time.
The RC25 is available for the MicroPDP-11s in a tabletop model, and for the
MicroVAX II in a tabletop model or as a field-installed rackmount model.

Figure 3-5· RC25 Fixed/Removable-disk Drive

3-12· System Options

TK.50 and TK2.5 Cartridge Tapes
The TK50, shown in Figure 3-6, is a 95-Mbyte, 5.25-inch, streaming-cartridge tape drive for the MicroVAX II, MicroPDP-l1/83, and MicroPDP-ll/
73 systems. It is also available as an add-on device on the MicroPDP-ll/23. It
is a compact and convenient backup, bootstrap, and distribution device that
complements the supermicrosystem's disk drives. The TK50 will serially
record up to 95 Mbytes on a O.5-inch by 600-foot tape that is enclosed in a
COMPACTape cartridge.
The following are the main features of the TK50:
• Up to 95 Mbytes formatted capacity (operating-system dependent).
• Industry-leading data integrity and reliability.
• 62.5 Kbytes/second peak transfer rate (45 Kbytes/second for user data).
• 75 inches/second tape speed.
• 22 tracks on aO.5-inch COMPACTape.
• 6,667 bits/inch recording density.
• Available in integrated, tabletop, and rackmount models.
The TK25, shown in Figure 3-7, is a 60-Mbyte, 8-inch, cartridge-tape drive
packaged in a stand-alone tabletop enclosure. It is designed for fast backup of
the RD51 and RD52 fixed disks on MicroPDP-ll systems only. The TK25 will
serially record up to 60 Mbytes on a 0.25-inch tape that is enclosed in a
DC600A cartridge. The TK25 cartridge-tape drive also comes with its own
universal power supply with cooling and a quad-slot Q22-bus controller mod-

ule.
The following are the main features of the TK25:
• 60 Mbytes formatted capacity.
• 55 Kbytes/second peak transfer rate.
• 55 inches/second read/write speed.
• Ten tracks on 0.25-inch tape cartridge (DC600A).
• 8,000 bits/inch recording density.

3-13

Figure 3-6 • TK50 Streaming-cartridge Tape Drive

Figure 3-7 • TK25 Cartridge-tape Drive

3-14· System Options

TSV05 Streaming Tape
The TSV05, shown in Figure 3-8, is an industry-standard, 9-track, magnetictape drive for the MicroVAX II and MicroPDP-ll systems. It includes a tape
transport with an integral formatter and a single; quad-height controller module. It features a storage capacity of 40 Mbytes (using 8-Kbyte blocks) and 28
Mbytes (using 2-Kbyte blocks) on a 10.5"inch reel, 25/100 inches/second
streaming-tape backup, and front-loading automatic tape threading. The
TSV05 supports industry-standard 1,600 bits/inch phase-encoded format
(ANSI-compatible). The tape transport occupies only 8.7 inches (22 centimeters) in a 42-inch-high (106-centimeter) cabinet enclosure, and without the
cabinet for system integrators.
The following are the main features of the TSV05:
• 40 Mbytesformatted capacity (using 8-Kbyte blocks) and 28 Mbytes formatted capacity (using 2-Kbyte blocks).
• 10.5-inch by 2,400-foot reel.
• Front loading.
• Automatic tape threading.
• 40 or 160 Kbytes/second peak transfer rate.
• 25/100 inches/second read/write speed (preset by user).
• 1,600 bits/inch recording density.

3-15

Figure 3-8 • TSV05 Streaming-tape Drive

CD Reader and CDROM
The CD Reader, shown in Figure 3-9, is Digital's newest storage technology.
CD Reader is a data-oriented, read-only optical disk drive. The optical disk,
called CDROM (Compact Disk Read-Only Memory) is a 4. 7-inch (12-centimeter) platter that can hold as many as 600 Mbytes of data. That is the equivalent of 200,000 single-spaced, typewritten pages or 1,600 flexible disks. Text,
data, graphics, and images can all be distributed on CDROM disks. CDROM
and CD Reader systems are an excellent vehicle for distributing relatively stable information such as catalogs, reference libraries, design drawings, software
and documentation, computer-based instruction, and financial data to a large
number of users.
The CDROM uses two interleaved error-correction codes so that any errors are
detected and quickly corrected. The CD Reader comes with its own dualheight controller module that can support two drives.
The following are the main features of the CD Reader and CDROM:
• 600 Mbytes formatted capacity .
• High data integrity.

3-16· System Options

• Recording format conforms to the worldwide Philips/Sony standard.
• 1.5 seconds average access time.
• 150 Kbytes/second average transfer rate.
• Quiet and very easy to use.
The CD Reader and CDROM is available only for the MicroVAX II.

Figure 3-9 • CD Reader and CDROM

3-17

• Communications Options
The communications capability of each of the supermicrosystems can be
expanded by communications interface options. These options enable asynchronous, synchronous, and realtime data transfers between two or more systems, and also between a host system and its user terminals, modems, and
other external devices. Each option consists of an interface module, internal
cables, and a panel insert. The interface module installs into a slot in the Q22bus backplane, and the device connector panel insert is mounted in the I/O
distribution panel at the rear of the supermicrosystem chassis. Refer to the
Microcomputer Products Handbook for detailed information on the following
communications options. Appendix D has the ordering information for this
handbook.
Asynchronous Interfaces

-DZQll
The DZQll is a four-line, asynchronous multiplexer that provides local or
remote interconnection between the supermicrosystem and EIA RS232-Cj
CCITT V.lO terminals or other systems. The DZQll operates at programselectable speeds up to 9,600 bits/second at full-duplex with limited-modem
control on each line.
The DZQll is a single, dual-height module. It is compatible with Digital's
family of modems and with the Bell 100 and 200 series of modems and their
equivalents.

-DHVll
The DHVll is an eight-line, asynchronous, direct-memory access multiplexer
that provides local or remote interconnection between the supermicrosystem
and EIA RS232-CjCCITT V.28 terminals or other systems. Direct-memory
access reduces system overhead for terminal-intensive applications. The
DHVll operates at program- or jumper-selectable speeds up to 38,400 bits/
second at full-duplex with full-modem control on each line. Split-speed transmit and receive rates are supported on each line making more efficient use of
communications facilities by reducing the software demand for the receive
line.
The DHVll is a single, quad-height module. It is compatible with Digital's
family of modems and with the Bell 100 and 200 series of modems and their
equivalents.

3-18' System Options

• DLV]l
The DLVJl is a four-line, asynchronous interface that provides local or remote
interconnection between the MicroVAX II and MicroPDP-ll systems and
EIA RS232-C/CCITT V.28, EIA RS422/CCITT V.ll, and EIA RS423/CCITT
V.lO terminals. The DLVJl acts .as four separate devices, making program
operations more convenient than they are with a multiplexer. The DLVJl operates at program- or jumper-selectable speeds from 150 to 38,400 bits/second
at full duplex with limited-modem control. Split-speed transmit and receive
rates are supported on each line making more efficient use of communications
facilities by reducing the software demand for the receive line.
The DLVJl is a single, dual-height module. It is compatible with Digital's family of modems and with the Bell 100 and 200 series of modems and their equivalents .

• DLVEl
The DLVEI is a single-line, asynchronous interface that provides local or
remote interconnection between the MicroVAX II and MicroPDP-ll systems
and EIA RS232-CjCCITT V.28 terminals. The DLVEI operates at programor jumper-selectable speeds from 50 to 19,200 bits/second at full duplex with
limited-modem control. Split-speed transmit and receive rates are supported
making more efficient use of communications facilities by reducing the software demand for the receive line.
The DLVEI is a single, dual-height module. It is compatible with Digital's
family of modems and with the Bell 100 and 200 series of modems and their
equivalents.
Synchronous Interfaces

oDEQNA
The DEQNA is a high-performance, synchronous, communications controller
that connects the supermicrosystem to an Ethernet Local Area Network
(LAN). The DEQNA complies fully with the Ethernet specification and operates at 10 Mbits/second.

3-19

The DEQNA provides Ethernet data-link layer functions and a portion of the
physical channel functions. The DEQNA is supported under DECnet Phase
IV software. Digital also provides documentation and device drivers so that
users can write their own higher-level protocols for specialized applications
and communications in multivendor environments. The DEQNA allows communications with up to 1,023 addressable devices on an Ethernet. It physically and electrically connects to the Ethernet coaxial cable via Ethernet
transceiver cables and an H4000 Ethernet transceiver, or a Local Area Interconnect (DELNI). The Physical Address ROM (DEXMR) is required to downline load software to a diskless Ethernet node with a DEQNA.
The DEQNA is a single, dual-height module.
"DMVll
The DMV11 is a single-line, synchronous, microprocessor-controlled interface
that provides local or remote interconnection between the supermicrosystem
and other computer systems with EIA RS232-C/CCITT V.28, or RS423/
RS449 interfaces. The DMVll implements DDCMP in hardware and supports direct-memory access data transfers, DECnet point-to-point or multipoint configurations, and full-modem control. It operates at speeds from
19,200 bits/second to 56,200 bits/second (depending on the version selected)
at half- or full-duplex.

Depending on the operating system and layered software, the DMV11 can support up to 12 tributaries. In multipoint configurations, these tributaries can
be other DMVlls or DMPlls. In point-to-point configurations, the DMVll
can communicate with other DMV11s, DUP11s, DMR11s, or DMP11s.
The DMV11 is a single, quad-height module. It is compatible with Digital's
family of modems and with the Bell 200 series of modems and their equivalents.
" DPVll
The DPVll is a single-line, synchronous, programmable interface that provides local or remote interconnection between the supermicrosystem and
other computer systems with EIA RS232-C/CCITT V.28 or EIA RS232-Cf
CCITT V.11 interfaces. It operates at speeds as great as 56,000 bits/second at
half- or full-duplex with full-modem control. The DPV11 is programmable for
either byte-oriented protocols (DDCMP or BISYNC) or bit-oriented protocols
(SDLC or HDLC). The DPVll is suited for interfacing to medium-speed synchronous lines for remote batch and remote job-entry applications.

The DPV 11 is a single, dual-height module. It is compatible with Digital's family of modems and with the Bell 200 series of modems and their equivalents.

}-20· System Options

-[(MVl1
The KMVll is a highcperformance, direct-memory access, single-line, programmable, communications contl"Qller that provides local or remote interconnection between the MicroVAX II and MicroPDP-ll systems and other
computer systems with EIA RS232-C/CCITT V.2S, EIA RS422/CCITT V.1,
or EIA RS423/CCITT V.10 interfaces. It is capable of communications speeds
as great as 64,000 bits/second. The KMVll utilizes the MICRO/Tll processor to perform user-defined communications functions, thereby freeing the
host to do. more applicatioo·computations.
The KMVll can be programmed in synchronous or asynchronous modes. It is
implemented as a single, quad-height module. The KMVll also provides fullmodem support for Digital's family of modems, the Bell 200 series of modems
or their equivalents, and European-PPT-approved modems.
Realtime Interfaces

• DRVll-JP
The DRVll-JP is a general purpose, program-controlled, parallel-line interface. It contains 64 bidirectional input/output lines configured as four 16-bit
ports. It is also bit interruptible on as many as 16 lines. Interrupt vectors may
have fixed or rotating priorities. The DRVll-JPis a single, dual-height mod-

ule.

-DRVll-WA
The DRV11-WA is a general purpose, direct-memory access, parallel-line, interface with 22-bit addressing capability. It permits block-mode DMA data transfers at rates as great as 250 Kwords/second in single-cycle mode, and as great
as 500 Kwords/second in burst mode. The DRVll-WA is a single, dual-height
module.

·AAVll
The AAVll is a four-channel, digital-to-analog (D/A) converter module for
MicroPDP-ll systems that includes control and interfacing circuits. It has
four D/A converters, a dc-to-dc converter that provides power to the analog
circuits, and a precision voltage reference. Each channel has its own holding
register that can be addressed separately and provides 12 bits of resolution.
The AAV11 is a single, dual-height module and is available as an.add-on option
.
only.

-ADVll
The ADVll is Ii 12-bit, successive approximation, analog-to-digital (A/D) converter module for MicroPDP-11 systems that samples analog data at specified
rates and stores the digital equivalent value for processing. A multiplexer section can accommodate .as many as 16 single-ended or eight quasi-differential

3-21

inputs. The converter section uses a patented auto-zeroing design that measures the sample data with respect to its own circuitry offset and, therefore,
cancels out its own offset error. The ADVll is a single, dual-height module
and is available as an add-on option only .

• AXVll
The AXVll is an analog input/output module for MicroPDP-ll systems that
accepts up to 16 single-ended inputs or as many as eight differential inputs,
either unipolar or bipolar. The AXVll also has two separate digital-to-analog
(D/A) converters. Each D/A converter has a write-only register that provides
12-bit input data resolution. On receiving the data, the AXVll changes it to
an analog output voltage. The AXVll is a single, dual-height module and is
available as an add-on option only .

• KWVll
The KWVll is a 16-bit, programmable clock counter for MicroPDP-ll systems only that provides a variety of means for determining time intervals or
counting events. It can be used to generate interrupts to the processor at predetermined intervals, or to synchronize the processor ratios between input
and output events. It can also be used to start the ADVll analog-to-digital
converter either by clock counter overflow or by firing the Schmitt trigger.
The KWV11 can be operated in any of four programmable modes-single
interval, repeated interval, external event timing, and external event timing
from zero base. The KWV11 is a single, dual-height module and is available as
an add-on option only.

• Terminals, Printers, and Modems
Digital offers a complete line of videoterminals, printers, and modems for the
supermicrosystems. A terminal or device can be selected that incorporates the
features that the application requires. A detailed description of all the
videoterminals, printers, and printing terminals can be found in the Terminals and Printers Handbook. Refer to Appendix D for ordering information
on this handbook.
Videoterminals
Videodisplay terminals use a cathode-ray tube (CRT) screen for output and a
typewriterlike keyboard for input. Alphanumeric videoterminals are capable
of displaying letters, numbers, and special characters in a fixed format.
Graphics videoterminals can individually manipulate picture elements on the
display screen and can represent graphs, charts, and pictures. Usually a
graphics terminal can also emulate an alphanumeric terminal. Table 3-2 is a
comparison chart of the alphanumeric and graphics videoterminals.

Table 3-2 • Videoterminal Features

Model

Universal VT100 Keyboard
Family Features

Advanced Vn:leo
Features

VT220

ANSI
Numeric

VT240

ANSI
Numeric

VT241

ANSI
Numeric

Graphics Printer Port Local Echo Asynchronous
Communications

Modem
Control

Integral
Modem

Full Duplex

Optional

Full Duplex

Optional

Full Duplex

Optional

3-23

• VT200 Videoterminal Series
The VT200 series is Digital's newest offering of videoterminals. The VT200
terminals include all of the universal features of the VT100 series of videoterminals. The VT200 units are smaller in size than the VT100 units and include
low-profile packaging. A series of setup menus simplifies tailoring the terminal to the application.
• VT220
The VT220, a monochromatic, text-only, videodisplay terminal (shown in Figure 3-10) incorporates full VT100 functionality. The terminal features a 12inch nonglare screen, low-profile packaging, and an adjustable monitor. The
VT220 terminal includes VT52 terminal emulation, advanced-video features,
a built-in printer port, and U.S.A.jEuropean modem controls. Its international capabilities include a multinational character set, universal power supply, and both 20-milliampere and EIA interfaces. A plain-language setup
menu, programmable function keys, and a selective-erase feature combine to
make the VT220 terminal easy to use. Operator-oriented features such as split
screen, bidirectional smooth scrolling, double-height and double-width characters, and reverse video allow the VT220 terminal to be used for many
applications.

Figure 3-10· VT220 Videodisplay Terminal
• VT240 and VT241
The VT240 is a monochromatic, text and graphics videodisplay terminal. It
incorporates all the features of the VT100 family and the VT220 terminal, is
completely self-contained, and requires no upgrading.

3-24 • System Options

The VT240 terminal supports the industry's graphics standards by generating
full bit-mapped graphics in both ReGIS and Tektronix 4010/4014 emulation.
ReGIS is Digital's general purpose graphics descriptor. It allows pictorial data
to be created and stored very easily. By connecting this terminal to a graphics
printer, such as the LA210, the contents of the display can be reproduced.
The VT240 terminal consists of the same keyboard that is used for the VT220
terminal, a monitor, and a system box. The system box contains the power
supply, control-circuit board, and electrical connectors.
The VT241 terminal offers all the capabilities of the VT240 terminal and
includes a color monitor for four-color text and graphics output. Both the
VT240 and the VT241 are shown in Figure 3-11.

Figure 3-11 • VT240 and VT241 Video- and Graphics-display Terminals

3-25

Printers and Printing Terminals

Several printers and printing terminals are available for operation with the
supermicrosystems. These devices include large, free-standing units and
small, desktop units. Table 3-3 provides a comparison of the features available
on the printers and printing terminals .

• LA210 utterprinter
The LA2lO Letterprinter, shown in Figure 3-12, is a microprocessor-driven,
medium-speed, wide-carriage, receive-only (RO), multimode printer that
offers similar functionality to the LA100 personal-computer model plus the
addition of IBM personal-computer compatibility. The LA210 uses conventional impact dot-matrix printing technology. Dot formations may be of
either letter quality (lower speedfhigher density), draft quality (higher speedf
lower density) and a binary-print mode that allows the host computer to
define all dots printed (graphics mode). The three basic modes of printer operation cover a wide range of applications. The LA210 has been designed with
the following standard capabilities:
• 240 characters/second draft printing speed.
• 40 character/second letter-quality printing speed.
• Compatibility with Digital and most IBM bit-map graphics printing applications.
• Compatibility with IBM-PC, IBM-XT, and IBM-AT personal computers and
with many IBM personal-computer emulators.
• Equipped with Courier-10 font with over 30 optional font cartridges available.
• Prints in ten languages plus VT100 line-drawing characters.
• Wide carriage prints up to 217 characters on 15-inch paper.
• Styled for the office environment.
• Forms-handling tractor with acoustic shield.
• 2,000-character input buffer.
• Equipped with EIA RS232-C interface.
500-million character laminated printhead delivers exceptional print
quality.

'"
~

Table 3-3 • Printer and Printing-terminal Features

..-

Model

Print Speed and
Quality

Graphics

Parts per Form

Paper Feed

Special Features

Interface

LA210

240 chIs draft
40 chI s letter

Tractor
Sheet optional

IBM PC-compatible
DEC PC-compatible
10 languages

EIARS232-C
IBM
Parallel optional

Optional

Friction
Sheet optional
Tractor optional

DEC PC-compatible
Full-character
printing

EIARS232-C

Tractor

High-volume
printing

EIARS232-C

Friction
Tractor
Sheet optional
Roll optional

DEC PC-compatible
Plug-in fonts

EIA RS232-C

Friction

DEC PC-compatible

EIARS232-C

80 chIs memo
optional
LQP03

27 chIs letter

LA120

180 chIs draft

LA100

240 chIs draft
30 chIs letter
80 chIs memo
optional

LA50

100 chIs draft
50 ch/s memo

Low tear-off
Tractor

Table 3·3 • Printer and Printing. terminal Features (Cont.)

Model

Print Speed and
Quality

Graphics

Parts per Form

LA12

150 chis draft
80 ch/s memo

LN03

8 pages/min

LCP01

.5 page/min

LP25

64-character
band: 300 Vmin
96-character
band: 445 Vmin

LP26

64-character
band: 600 Vmin
96-character
band: 800 Vmin

Paper Feed

Special Features

Interface

Friction
Pin
Roll
Tractor optional

Dual thro~ the
keyboard modem
and/or acoustic
coupler

Modem
EIARS232-C

Cutsheet

High-resolution
printing
Downlineloadable fonts

EIARS232-C

Cutsheet
Transparency

Color ink-jet
printing
Protocolprocessing
graphics

EIARS232-C
EIARS422
20mA

Tractor

High-volume band
printing

Short-line parallel
Long-line parallel

Tractor

High-volume band
printing

Short -line parallel
Long-line parallel

t.....,

3-28' System Options

Figure 3-12' LA210 Letterprinter
• LQP03 Letter-quality Printer
The LQP03 letter-quality printer, shown in Figure 3-13, is a desktop, fullcharacter, impact printer especially designed for use with all of Digital's supermicrosystems. The LQP03 includes an expanded character set contained on a
single, 130-petal daisywheel. The daisywheel allows use of all of Digital's multinational characters on one wheel, and provides scientific, mathematic, or
other special characters on another.
The printer produces graphics such as pie charts, bar charts, and line graphs
with the Daisy-Aids* software package. An optional bidirectional forms tractor is customer-installable and handles a variety of fanfold paper including continuous preprinted forms. It permits the paper to be scrolled forward or
backward while printing. The single-tray cutsheet feeder option is designed to
automatically feed precut paper to the LQP03 in either portrait or landscape
fashion_
The LQP03 runs on a variety of Digital's operating systems and layered software products, plus software packages from other manufacturers. Depending
on the software support, the LQP03 can also perform overprinting, boldfacing, underlining, subscripting, and superscripting. The LQP03 includes a standard serial interface for compatibility with existing Digital printers.

*Daisy-Aids is a trademark of Escape Computer Software, Inc.

3-29

Figure 3-13 • LQP03 Letter-quality Printer

3-30· System Options

• LA120 DECwriter III Printer
The LA120 freestanding printing terminal, shown in Figure 3-14, is a sturdy,
high-performance device with a reputation for reliability. It prints on multiple-copy, tractor~fed paper from 3 inches to 14.8 inches wide, at a maximum
speed of 180 characters/second - enough to print a typical one-page memo in
20 seconds. Because of its lOOO-character buffer, bidirectional printing, and
ability to skip quickly across spaces, the LA120 printer maximizes printing
throughput.
The standard LA120 printer character set is U.S.A.fUnited Kingdom. Character sets for Europe or the APL programming language are optional. Characters
can be printed in eight sizes and in six choices of vertical-line spacing_ Characters are formed by an impact dot-matrix printhead in a 7 by 7 dot format.
Both keyboard send/receive (KSR) and receive-only (RO) versions are
available.

Figure 3-14· LAl20 DECwriter III Printer

3-31

• LA 100 (Letterprinter 100 and LetteIWriter 100)
The LA100 printing terminals (Letterprinter 100 shown in Figure 3-l5) provide flexibility in a tabletop unit. The Letterwriter 100 is a keyboard send/
receive (KSR) terminal, and the Letterprinter 100 is receive-only (RO). Both
can print on friction-fed paper or on optional tractor-fed paper.

The impact dot-matrix printer offers a choice of print quality and speed. In
draft mode, it prints 240 characters/second maximum with a 7 by 9 print
matrix, and letter-quality mode outputs a 33 by 18 print matrix at 30 characters/second. In between these modes is the optional memo-quality mode with
its 33 by 9 print matrix and 80 characters/second. Standard fonts included
with the LA100 are Courier-lO and Orator-lO. Optional fonts include
Gothic-lO, Symbol-lO, Courier-12, and many others. Fonts can be selected
by the system or from the keyboard.

Figure 3-15 • LAlOO (Letterprinter 100)
• LA50 Personal Printer
The LA50, shown in Figure 3-16, is a low-cost, tabletop printer. Its impact
dot-matrix mechanism prints 7 by 9 matrix characters at 100 characters/second in draft mode, 13 by 9 characters at 50 characters/second in memo mode,
as well as bit-map graphics.

3-32· System Options

Characters can be printed at pica (10) or elite (12) pitch, as well as compressed
(16.5) for 132 characters on a line. Each pitch can also be printed in doublewidth characters. The LA50 has 250 printable characters, including
• The standard 96-character ASCII set.
• VT100 terminal special-character set.
• 8-bit multinational-character set.
• 11 national-character sets .

Figure 3-16 • LA50 Personal Printer
• LA12 Correspondent
The LA12 Correspondent, shown in Figure 3-17, is a high-quality, portable,
printing terminal, with an integral modem and an acoustic coupler. The LA12
includes 9 by 9 print dot-matrix characters at a maximum of 150 characters/
second, as well as bit-map graphics. Unlike most portable teleprinters, the
LA12 uses plain (not thermal) paper. Character sets and formatting features
are similar to those of the LA120 and LA100 printers.

3-33

Figure 3-17· LA12 Correspondent
• LN03LAser Printer
The LN03, shown in Figure 3-18, is an eight-page/minute laser printer that
can be used as a shared resource for supermicrosystem users and as a remote
printer for local area networks.
The LN03 is a compact printer, packaging the print engine and the controller
in one tabletop unit. With resolution of 300 dots by 300 dots/inch, the print
quality of the LN03 is outstanding on both cutsheet paper and transparencies.
The input paper capacity of the LN03 is 250 sheets, complemented by a paper
path that automatically collates the pages in a 250-sheet output tray. In addition to the 16 fonts resident in the LN03, a wide variety of optional fonts will
be offered in both host media and cartridge formats. This flexibility reflects
the LN03's capability to accept two ROM (Le., precoded typefaces) and/or
RAM cartridges, the latter being used to receive fonts or forms that can be
downline-Ioaded from a host.

Figure 3-18· LN03LAser Printer

3-34 • System Options

• LCPOl Color Printer
The LCP01, shown in Figure 3-19, is a color, ink-jet, graphics printer that produces high-quality presentation graphics on paper and transparencies_ The
LCPO 1 is an intelligent printer that contains its own graphics processor that
handles the display file processing from the CPU _This feature decreases processing time and frees the host CPU for other tasks_
The LCP01 can store up to five fonts in local memory and offers brilliant output from more than 200 colors. It supports ReGIS, GIDIS, NAPLPS, and BIT
MAP IMAGE (Color Sixel format) protocols. It is compatible with VAX DECslide, VAX DECgraph, DATATRIEVE, VAX VTX, and many third-party
graphics generation packages.
The following are the main features of the LCPO 1:
• Print speed: less than 2 minutes per copy.
• Print resolution: 154 dots/inch.
• Colors: 216.
• Image size: A size (7.5-9.5) and A4 (7.27-9.95).
• Print image resolution: 1,536 x 1,152 dots (maximum).
• Print colors: yellow, magenta, cyan, red, green, blue, black, and white.
• Tabletop model.
• Quiet (less then 58 db).
• Interface is EIA or 20 mAo

3-35

Figure 3-19· LCP01 Color Printer
• LP25 and LP26 System Printers
The LP25 and LP26 (the LP26 is shown in Figure 3-20) are band printers for
medium-duty printing workloads in a one-shift environment_ They were
designed for applications such as data processing, commercial, scientific,
industrial, and educational_ The LP25 and LP26 operate at medium speedsup to 300 and 600 lines per minute.

3-36' System Options

Figure 3-20 • LP26 System Printer
Modems
Digital provides several modem units to enable the supermicrosystems to communicate with remote terminals and systems over standard telephone lines.
These units can be placed on a desk or table or mounted into a cabinet or rack.

• DFl12 Modem
The DF112 modem connects directly to a modular tdephone jack and provides both synchronous and asynchronous communications over dialup and
privatefleased tdephone lines. The DF112 unit is comparable in operation to
Bdl103/21A modems.
Over dialup lines, it provides synchronous communication at 1,200 bits/second (full duplex) and asynchronous communication at 300 or 1,200 bits/second (full duplex). Over private/leased lines, the DF112 provides synchronous
and asynchronous communication at 1,200 bits/second (full duplex). The
DF112 can be used with any standard telephone for manual-call origination or
is available with serial asynchronous autodial capability that can be controlled
by a computer system or terminal connected to the EIA port.

3-37

The following are the main features of the DF112:
• Dual application modem-supports 0 to 300 and 1,200-bit/second asynchronous operation, or 1,200-bit/second synchronous operation.
• Conforms to FCC Part 15 requirements.
• Approved for direct connection to Public-Switched Telephone Network by
FCC Part 68.
• Quick and easy installation, maintenance, and operation.
• Automatic originate, answer, and disconnect capabilities.
• Single, serial-data port for both automatic dialing with autocall feature
and normal data.
• Multiple-modem modules certified for operation in Canada by the Department of Communication.
• Multiple-modem modules support EIA cables up to 200 feet .

• DF124 Modem
The DF124 modem, shown in Figure 3-21, connects directly to a modular telephone jack and provides both synchronous and asynchronous communications
over dialup and private/leased telephone lines. The DF124 is comparable in
operation to the CCITT V.22 bis and Bell 212A modems.
Over dialup lines, it provides synchronous and asychronous communication at
1,200 or 2,400 bits/second (full duplex). Over private/leased lines, the DF 124
again provides synchronous and asynchronous communication at 1,200 or
2,400 bits/second (full duplex). The DF124 can be used with any standard
telephone for manual-call origination or is available with serial asynchronous
autodial capability that can be controlled by a computer system or a terminal
connected to the EIA port.
The following are the main features of the DF124:
• Dual application modem-supports 1,200-bit/second or 2,400-bit/second
synchronous and asynchronous operation
• Compatible with the CCITT V.22 bis modem at 2,400 bits/second. Compatible with the Bell 212A modem at 1,200 bits/second.
• All other features of the DF112.

3-38' System Options

Figure 3-21 • DF124 Modem Unit
• DF1 00 Modem Enclosure
The DF100 modem enclosure, shown in Figure 3-22, houses up to 12 DF100series modules and can be installed into a 19-inch (48.3-centimeter) cabinet or
rack. Can connect to either the Public Switched Telephone Network (PSTN)
or the Private/Leased Telephone Network (P/LTN).
The following are the main features of the DF100:
• Houses as many as 12 modem modules for cost reduction and space
savings.
• Single, complete unit that is easily installed in a cabinet or rack.
• Contains internal power supply and provides space for optional power regulator.
• Permits easy servicing with online replacement of modem modules.
• Device and communication line cables are easily connected by the user.

3-39

Figure 3-22 • DFlOO Modem Enclosure

• Additional Documentation
VAX Systems and Options Catalog

ED-27973-46

PDP-ll Systems and Options Catalog

ED-27981-41

Networks and Communications Buyer's Guide

ED-28055-42

Microcomputer Products Handbook

EB-26078-41

Terminals and Printers Handbook

EB-26291-56

3-40' System Options

• Introduction
Software is the collection of written procedures and rules that control computer operations. The system software always includes an operating system,
which is the "intelligence" of the computer system. Layered products are
made up of high-level languages, information management products, programmer productivity tools, and communications software products, that all work
in conjunction with a specific operating system.
Although the MicroVAX and MicroPDP-ll supermicrosystems :u-e architecturally similar in many respects, they each have softw:u-e designed specifically
for their architectures. This chapter will briefly describe the many operating
systems and layered products that run on each of the supermicrosystems.

• Micro VAX Operating and Development Systems
The full capabilities of the MicroVAX supermicrosystems can be reached
through the MicroVMS operating system, the ULTRIX-32moperating system,
and the VAXELN development toolkit.
The MicroVMS and ULTRIX-32moperating systems organize and allocate system resources and files, protect data, and monitor system operations. A large
set of programming languages, utilities, and application software is available
to support these operating systems. The VAXELN development toolkit helps
the programmer to develop dedicated applications for the MicroVAX.
The key attributes of these systems are summarized in Table 4-1.

Micro VMS Operating System
MicroVMS is a general purpose, virtual-memory operating system for the
MicroVAX II and MicroVAX 1. It simultaneously supports realtime, batch,
and interactive timesharing applications. Through virtual memory, the hardware and software interact to allow the physical memory of the system to be
extended onto disk space. Some of the advantages of this system are
• The 32-bit architecture supports 4 Gbytes of virtual address space to permit large programs to be created and executed.
• Paging and swapping enable more programs to be executed than can be executed in systems with physical memory only.

4-2 • System Software and Layered Products

• Efficient memory management selects stored programs to be mapped into
physical memory as required.
• Extensive system management capabilities control program behavior to
minimize disk access and maximize program performance .

• Micro VMS Features
The MicroVMS operating system provides the same native-mode runtime
environment offered by the VAXfVMS operating system. All of the basic
VAX/VMS operating system features are included except for support of the
PDP-ll compatibility mode, which is provided on MicroVAX II by the
optional software product, VAX-ll RSX. There is no support for clustering.
MicroVMS is a multifunction, virtual-memory system with extensive VAX/
VMS system capabilities in file organization and access, program development, and information management, as well as the basic system utilities and
the Digital Command Language. A wide range of applications and operational
environments can be accommodated. Program development is fast and simple
and virtually unlimited room exists for growth or migration to larger VAX/
VMS systems.
All native-mode, nonprivileged VAX/VMS applications will execute on
MicroVAX systems without modification. Compatibility mode applications
will continue to run on MicroVAX II systems under the VAX-ll RSX optional
software product. Many of the Digital-supplied language compilers, productivity tools, information management products, and communications products
are available as optional products with MicroVMS software. Applications can
easily coexist with, and migrate between, MicroVMS and VMS systems so
that the user's investment in applications development and support is protected.
The MicroVMS operating system and optional communications hardware and
software products provide extensive communications capabilities for the
MicroVAX systems. These capabilities include remote system and local area
network communications. Data access to any VAX system in the network,
including clusters, is possible. When used with the VAX/VMS operating system, these facilities form a fast and efficient means of transferring information in large commercial and technical applications .

• Micro VMS Program Development
MicroVMS program development support is provided by Digital's high-level
languages. These languages use the Common Language Environment (CLE)
that makes them conform to a specific set of standards. CLE allows each
MicroVMS language to interact easily with system services, libraries, and
applications written in other MicroVMS languages.

4-3

VAX RMS (Record Management System) provides a standard for I/O for all
languages_ This allows files written by one application to be read and used by
another application, even if it is written in a different language. Use of the
VMS Runtime Library (RTL) provides an integrated, functional base for all
MicroVMS languages. A symbolic debugger is included with MicroVMS that
can be used to debug programs written in any MicroVMS language. Unique
devices can also be interfaced to the system by writing a driver to support the
device.
Many application programs written by Digital and third-party vendors are
available for program development as well .

• Micro VMS PDP-II Compatibility Mode
Digital's commitment to supporting coexistence between 16- and 32-bit systems and to provide migration paths between these systems is extended to the
MicroVAX II system through the use of the MicroVMS optional software product, VAX-ll RSX. In the absence of compatibility mode hardware in the
MicroVAX II system, VAX-ll RSX provides users with a PDP-ll instruction
set software emulator.
Using VAX-ll RSX, MicroVMS users can run-without modification-many
RSX-based programs originally developed for PDP-lls. In addition, they can
use their MicroVAX II system to continue to do program development for target PDP-ll and MicroPDP-ll processors running any of the RSX operating
systems. While the software emulator's performance cannot match that of the
compatibility mode hardware in larger VAX processors, VAX-II RSX provides
a valuable tool for PDP-ll compatibility mode operations in the absence of
similar hardware in the MicroVAX II.

ULTRIX-32m Operating System
ULTRIX-32m is Digital's enhanced native-mode UNIX* operating system for
the MicroVAX systems. This software product is derived from the UNIX Version 4.2 from the University of California at Berkeley. The ULTRIX-32moperating system is compatible with the ULTRIX-32 operating system for larger
VAX processors. The product is complementary to MicroVMS and VAXELN
and addresses the needs of users seeking a commodity operating system on
low-end 32-bit systems.

* UNIX is a trademark of AT&T Bell Laboratories.

4-4 • System Software and Layered Products

Although no UNIX system standard yet exists in the industry, the Berkeley
implementation is widely recognized as the premier UNIX system adaptation
on 32-bit systems_Because the Berkeley system was specifically developed to
take advantage of the virtual architecture of VAX systems,. it optimizes the
hardware so that it performs more efficiently than other versions of the UNIX
system.
The ULTRIX-32m system is a repackaging, not a subset, of the full ULTRIX32 product for larger VAX processors. It is designed to provide the complete
set of ULTRIX -32 operating system capabilities for the smaller MicroVAX systems .

• ULTRIX-32m Features
The ULTRIX-32m operating system offers a wide range of programmer productivity tools and networking capabilities.
The Bourne and C shells serve as the command-language interfaces into the
system. Both of them are programmable and thus allow for a tailorable user
environment.
The ULTRIX-32m system provides a hierarchy of named directories and subdirectories. The number of levels is limited only by physical space. Utilities
that aid in system and file maintenance include line and screen editors, file
interchange, a print spooler, and system installation and maintenance.
The C programming language interfaces with ULTRIX-32m and the UNIX system in the same manner. As a result, ULTRIX-32m or UNIX system applications that are written in C can be easily moved from one UNIX machine to
another. ULTRIX-32m can also be programmed in assembly language.
ULTRIX-32m's communications facilities include TIP (remote login), UUCP
(phone network), mail, and Ethernet. DECnet ULTRIX V1.0 is offered as a
separate layered product providing communication between ULTRIX and
VMS environments.
VAXELN Development Toolkit
The VAXELN Toolkit is a VMS layered product for the development of dedicated, realtime VAXELN systems that run on VAX superminicomputers and
MicroVAX supermicrosystems. The development tools run on a host VAX or
MicroVAX processor under the VAX/VMS or MicroVMS operating system. A
finished VAXELN system runs directly on a target VAX processor, without
the presence of another operating system.

4-5

Typical VAXELN applications are ones in which individual processors have
dedicated or otherwise predetermined functions and are not needed simultaneously for general computing, program development, or other uses for which
a general operating system, such as MicroVMS, is more appropriate. Examples
include industrial automation, workstations designed for a particular profession, Ethernet server networks, and robotics.
VAXELN is especially well suited, although not limited, to creating realtime
applications. These are applications in which the system's response to external
events is critical. Such applications include the typical scientific and industrial
data processing situations in which the computer's operation has to be precisely synchronized with machines and special input/output devices.
The VAXELN software simplifies the design and implementation of such applications by offering
• High-level implementation languages (Pascal and C).
• A conceptually simple and small kernel executive that manages resources,
processes, and data.
• Pregenerated optionally included service programs and device drivers that
implement a file system, network communication facilities, and I/O-device
handling .

• VAXELN Features
VAXELN provides multitasking in Pascal or C programs. In addition, multiprogramming is supported so that entire programs, including multitasking
programs, can be scheduled concurrently on the same cpu.
VAXELN systems can run on autonomous VAX or MicroVAX computers or,
with the networking software provided in the toolkit, they can be connected
in an Ethernet local area network. The network may include VAX/VMS nodes
or other nodes using DEC net-VAX services and protocols. Once written,
VAXELN programs can be redistributed among the nodes in a network without changing their code.
Finished VAXELN systems can be loaded onto portable storage volumes and
booted from them on the MicroVAX. If the user has the optional DECnetVAX license and Ethernet hardware, VAXELN software can be downlineloaded from the development computer to the MicroVAX system(s).
VAXELN system images can also be stored in and booted from read-only memories (ROMs) .

• VAXELN System Development
For the development of VAXELN systems, the toolkit cari be used on any VAX
computer running a current version of the VAX/VMS operating system.

4-6 • System Software and Layered Products

Together with other software modules, the user receives thefollowing development utilities (VAX/VMS program images) in the VAXELN toolkit:
• VAXELN Pascal compiler.
• VAXELN debugger.
• VAXELN system builder.
Although previously existing VAX programming languages can be used in
VAXELN system development, the VAXELN Pascal compiler is provided in
the toolkit. VAXELN Pascal is a highly optimizing, native-mode compiler
extended to eliminate the need for other programming languages, including
assembly language. It provides a consistent Pascal language for all system programming problems, including the writing of interrupt-service routines and
blocks for concurrent processes. It is the primary implementation language of
the VAXELN toolkit.
User programs are written with the aid of the usual VAX/VMS text editors and
utilities and then compiled. The compiled code is linked, using the standard
VAX/VMS Linker, to a special runtime library also supplied with the toolkit.
The runtime libraries provide special support for VAXELN Pascal and VAX C
I/O operations, the standard Pascal routines such as SIN, the standard C routines commonly associated with UNIX, such as PRINTF, and certain procedures used in system programming. The libraries are provided both in objectlibrary and shareable-image forms in the toolkit. Only those shareable images
containing code called by applications programs are included in the finished
VAXELN system. This makes a finished system with a minimal amount of
unused code while still maintaining maximum ease of use in program development.
The VAXELN debugger is used to debug programs in a developed, executing
VAXELN system. It can be used to debug a VAXELN system locally using the
target computer's console terminal. If the user has the optional DECnet-VAX
license and Ethernet hardware, the debugger can be used remotely to debug
VAXELN systems running on Ethernet nodes from a programmer's terminal
on a VAX/VMS node.
The VAXELN system builder combines program images, the VAXELN kernel
image, and runtime routines to produce an image of the finished VAXELN system. The program images can be any user-written programs developed in
VAXELN Pascal or C, or any of the images supplied with the toolkit. The program images can also be the routines written in other VAX languages provided
that they do not call VAX/VMS system services or language-specific runtime
routines, such as. I/O.

4-7

Also included in the toolkit are a number of program images ready for inclusion in the user's VAXELN system.
The VAXELN kernel is included in every VAXELN system. It manages the system's processes and data, providing the controlled sharing of the system's
resources. The operations of the kernel are reflected in VAXELN programs by
special procedure calls, almost all of which are predeclared in the language.
For C programming, these kernel procedures are contained in an included
module.
The VAXELN file service supports I/O operations from VAXELN PASCAL programs to file-storage devices such as disks, as well as remote file access to and
from other DECnet nodes. I/O requests from the user's programs are interpreted by the file service and performed by the appropriate device-driver program. The file service and the toolkit's disk-driver programs use the Digital
Data Access Protocol (DAP) Version 7.0 for all low-level I/O operations. Userwritten drivers can run combined with the file service, and programming
tools are supplied in the toolkit for this purpose.
The VAXELN network service provides completely transparent network communications between VAXELN nodes in a local area network, and between
VAXELN nodes and other DECnet nodes. In network applications, each
VAXELN node runs its own VAXELN system, and each system is built including the network service. Given such a configuration, the network locations of
VAXELN applications programs are completely invisible to each other. A program can communicate with a program on another node using precisely the
same statements as if both programs were on the same node.
High-performance device drivers are supplied for the commonly used
UNIBUS (VAX) and Q22-bus (MicroVAX) devices. All are implemented in
VAXELN PASCAL and are supplied both in source form and in image (binary)
form. The driver sources can be used as templates for user-written drivers.
A variety of other programming aids is supplied, such as template-device
drivers, declarations of Data Access Protocol (DAP) interfaces, and declarations of exception arguments .

• VAXELNAda
VAXELN Ada is a VAX/VMS layered product that, together with VAX Ada
and the VAXELN Toolkit, allows you to develop Ada applications to run in the
VAXELN environment. Each VAXELN Ada task is a separate VAXELN process, permitting a combination of Ada and non-Ada code in the same application. A Digital-supplied package of declarations makes it easy to call VAXELN
kernel services and utility routines from VAXELN Ada programs. Device
drivers and their interrupt handlers can be written in Ada.

4-8 • System Software and Layered Products

• MicroPDP-ll Operating and Development Systems
The MicroPDP-11 family has been able to take advantage of the broad base of
PDP-ll software. The MicroPDP-ll provides a very easy and direct migration
path from other Digital products by supporting existing PDP-ll software.
The long list of PDP-ll system software allows the MicroPDP-ll to address
tasks found in realtime, multiuser timesharing, and batch environments. The
MicroPDP-ll is supported by eleven operating systems, of which two were
devdoped exclusivdy for the MicroPDP-ll family. All of these make the
MicroPDP-ll suitable for both devdopment and applications environments.
The key attributes of these systems are summarized in Table 4-1.

RSX-ll Famlly
The RSX family comprises four compatible, realtime multiprogramming operating systems. They are the industry's leading multiuser realtime operating systems. Designed for minimum size and overhead, this family of operating
systems can be used in a wide variety of hardware and application environments-from small dedicated laboratory and industrial control systems to
large multiuser information management systems.
Micro/RSX, the family member designed specifically for the MicroPDP-ll,
expands these environments even further by providing a small and easy-to-use
operating system that is customer-installable and, in most cases, allows for
complete transportability of applications from other RSX family members.
Once considered primarily a tool for technical applications, users are now discovering that RSX systems are ideal for such commercial applications as office
automation, banking, airline reservation systems, and stock exchanges.
The RSX family of operating systems provides reliable, high-performance
response to realtime demands, as well as to less time-critical activities such as
program devdopment. They are designed to execute multiple programs concurrently. A program is allowed to execute (use the CPU as a resource) until its
immediate need for the CPU is completed or until an external event with a
higher-priority program takes its place. If the higher-priority program needs
memory space, the lower-priority program is swapped out to a disk. This ability to respond rapidly to external events makes the RSX family of operating
systems an ideal choice where realtime reaction is important. When tasks of
equal priority are eligible to execute, a round robin scheduler rotates their
sdection so that all receive an equal share of CPU time.
RSX systems provide intertask communication facilities for sharing data, synchronizing execution, and sending messages. The sharing of memory areas and
the use of shared resident libraries of software routines result in significant
memory savings and increased performance.

4-9

RSX operating systems are not limited to realtime tasks. Micro/RSX, RSX11M-PLUS, and RSX-11M also provide users with a complete multiuser program development environment. Software development tools provided with
the systems include a choice of comprehensive command languages (including
DCL, the Digital Command Language); a choice of editors; Record Management System (RMS) supporting sequential, random, relative, and multikeyed
indexed sequential processors; debugging aids; system libraries; and a wealth
of additional program development and maintenance utilities.
Micro/RSX, RSX-llM-PLUS, and RSX-llM offer unsurpassed software compatibility. All nonprivileged tasks that run on RSX-IIM and RSX-IIS can run
on RSX-llM-PLUS and Micro/RSX without change or reassembly. Privileged
tasks usually require little or no change. Micro/RSX and RSX-I1M-PLUS also
provide significant support for migrating applications to VMS environments.
By using VAX-ll RSX, VMS and MicroVMS users can run RSX applications,
often without modification, on their VAX and MicroVAX II systems .
• Micro/RSX
Micro/RSX is an extended subset of the multiuser, multitasking RSX-llMPLUS operating system. As the newest member of the RSX -11 family, Micro/
RSX was designed for use with the MicroPDP-ll and is a customer-installable, easy-to-use system for both realtime and timesharing environments.

Micro/RSX is offered in two packages. The Base Kit provides the full RSX11M-PLUS executive, appropriate utilities and device drivers, support for
user-mode program development in high-level languages, and a user documentation kit. The Advanced Programmer's Kit is an add-on to the Base Kit and
includes the software and documentation necessary for MACRO-II and privileged program development. This includes a MACRO assembler, a librarian,
an online debugging tool, and system libraries specifically designed to support
privileged programming. The Advanced Programmer's Kit also includes the
data terminal emulator and file transfer utility which allows for easy file transfer between a Micro/RSX system and any other RSX, VMS, or PIOS system.
Communications among any of these systems is established through a terminal
line.
Micro/RSX also has Professional 350 diskette-exchange capability. With the
use of the Professional Tool Kit, it allows programs to be developed for use on
the Professional 350. Like RSX-llM-PLUS, Micro/RSX also provides a migration path directly to VMS .
• RSX-llM-PLUS
RSX-11M-PLUS provides the optimal multiuser system software for Digital's
newest processors in the PDP-11 family. As the superset member of the RSX
family of operating systems, RSX-I1M-PLUS offers all of this family's capabilities.

4-10 • System Software and Layered Products

RSX-11M-PLUS takes advantage of the expanded addressing capabilities of
Digital's newest PDP-11 processors while retaining the superior reliability
and the successful architecture of RSX-11M. RSX-11M-PLUS uses hardware
features in these PDP-11 processors that are not available in other members of
the PDP-11 family. With the use of supervisor-mode library routines and separate user-mode instruction and data space, an RSX-11M-PLUS task can
address as many as 196 Kbytes of memory. In addition, RSX-llM-PLUS supports multistream batch, system accounting, dynamic dual-ported disks,additional memory management capabilities, and more simultaneous tasks and
terminals than RSX-11M .

• RSX-IIM
The RSX-llM operating system is the original member of the RSX family. It
offers a large portion of the capabilities contained in RSX-llM-PLUS. RSX11M excels in performance on small- and medium-size PDP-11 systems. It is
designed to support factory automation, laboratory data acquisition and control, graphics, process monitoring, process control, communications, and
other applications that demand immediate response. Its multiprogramming
capabilities permit realtime activities to execute concurrently with such activities as program development, text editing, and data management .

• RSX-llS
RSX-11S is a memory-resident subset of RSX-11M. As a result, a file system is
not supported on RSX-11S. RSX-11S is used as an extremely efficient executeonly system. RSX-llS is generally used under conditions in which a disk cannot safely operate, such as on the floor of a manufacturing plant.
RSX-llS provides excellent online process control. Because all programs are
memory-resident, response is extremely fast. Tasks for an RSX-11S system are
developed on computers running the RSX-llM, RSX-11M-PLUS, or VAX/
VMS operating system. Such tasks are then loaded into the RSX-llS system
by using a supplied host utility, the RSX-11S Online Task Loader (OTL), or by
downline loading if both the host and the RSX-llS system have DECnet or
DECdataway support.

RSTS Family
Thousands of users, from financial institutions and schools to manufacturers,
insurance companies, and airlines find RSTS/E to be a system that answers
their computing needs. It provides what is important to the commercial and
administrative environment-reliability, security, consistency, low cost per
user, and an efficient base for building and running commercially oriented
applications.

4-11

These features, in the course of over a decade, have led to the creation and
availability of a wealth of applications suited to all dimensions of the commercial and administrative marketplaces. These applications range from general
use products, such as word processing, sreadsheets, inventory control, and
accounting to specialty products, such as golf handicapping, chromatography
graphics, and legal analysis.
The RSTS family includes two members-RSTS/E and Micro/RSTS. RSTS/E
is designed for people who need the maximum flexibility in system configuration, a complete powerful program development environment, and a full range
of user management and program development documentation.
Micro/RSTS is designed for the MicroPDP-ll supermicrosystems and meets
the needs of people whose primary use of the system will be running RSTSbased applications. Almost all applications that run on RSTS/E and the
MicroPDP-ll hardware will also run unmodified on Micro/RSTS. Micro/
RSTS includes the BASIC-PLUS language and is offered at a lower cost than
RSTS/E, but does not include many of the powerful development tools and the
configuration flexibility that are standard features of RSTS/E .

• RSTS/E
RSTS/E is a multiuser, general purpose timesharing system. It provides interactive timesharing, batch processing, indirect command file processing, program development using a variety of languages and tools, and a wide variety of
special purpose applications. As many as 127 concurrent terminal users in
both local and remote locations, through multiterminal services, can interact
with applications tasks. Without multiterminal services, the maximum number of users is limited to 63. Tasks can share computational, storage, and
input/output services provided by the RSTS/E system. Each one of the multiple users can count on an almost immediate response to requests for access to
programs, utilities and data, and transactions in process.
The user is associated with a job and interacts with that job through a terminal. A timesharing job scheduler allows the job to execute until its immediate
need for the CPU is completed, or until an allocated period of time expires.
The eligible job with the highest priority will then be executed. If several eligible jobs have the same priority, a round robin scheduler rotates their selection
so each gets an equal share of CPU time. For example, a batch job can also be
submitted to run at a future time after working hours and the batch processor
job will supervise its execution in the submitter's absence.
Each individual's files and file directory can be protected from unauthorized
access by other users. Each user can specify who can read a file and who is
allowed to modify or update it.

4-12 • System Software and Layered Products

Communications with the operating system are accomplished through the
easy-to-use Digital Command Language (DCL). Individual installations can
add their own commands with the Concise Command Language (CCL). And
with optional MENU-ll, customized menus can be built as a command interface for novice or infrequent users. BASIC-PLUS is also included with the
RSTS/E operating system.
Because RSTS/E can migrate from one PDP-ll processor to another, system
growth is easy. In addition, distributed processing networks can be built using
DECnet/E for Digital-only networks and Internets for connection to other
vendor's systems .

• Micro/RSTS
Micro/RSTS is a pregenerated subset of RSTS/E and supports all RSTS/E system calls. Micro/RSTS was designed primarily for use with the MicroPDP11s, and is a customer-installable, easy-to-use system that can support as
many as 20 jobs on the MicroPDP-11/83 and MicroPDP-11/7 3 and as many as
10 jobs on the MicroPDP-11/23. It can also support as many as 14 terminals in
a timesharing environment.
Micro/RSTS consists of two separate kits. The Base System Kit is required for
all users, and the Application Development Kit is optional. The Base System
Kit includes software and documentation for the Micro/RSTS runtime system, for device support, and for BASIC-PLUS program development. BASICPLUS is included with the kit. The Application Development Kit includes software and documentation to support native MACRO-ll and high-level language program development. MACRO-ll is included with the Application
Development Kit_
Micro/RSTS supports programs developed on any RSTS/E system. Host development requires that files be transferred to and from the Micro/RSTS system.
This can be done by using any transfer medium that is available on both systems.
MicroPowerjPascal Development Toolkit
MicroPower/Pascal is an advanced software toolkit for developing Q-busbased microcomputer applications. It includes a high-performance Pascal compiler, a modular executive, and a variety of tools to create concurrent, realtime
application programs.

4-13

• MicroPower/Pascal Features
MicroPower/Pascal has two system environments to accomplish this development. The host system creates and builds the software. The target system executes the software. Each application is custom-designed for its target system
and includes the appropriate set of operating system services. The host, using
the symbolic debugger, controls the execution of the target application during
development.
There are four MicroPower/Pascal products-MicroPower/pascal-RT,
MicroPower/pascal-Micro/RSX, and MicroPower/Pascal-RSX to develop
applications using a PDP-ll host system. MicroPower/Pascal-VMS develops
applications using the VAX family.
The host development environment for each of these products includes an
extended, realtime Pascal compiler, a symbolic debugger, several build utilities, and a MACRO-II interface. The target environment includes a library of
software modules for process synchronization, communications, scheduling,
exception and interrupt handling, timer services, and device and file I/O.
The application program is created and linked with the appropriate runtime
software in the host system. It is then transported to the target system by one
of three methods-writing it into read-only memory, downline-loading it over
a serial line, or recording it onto removable storage media such as a flexible
disk or tape cartridge and then bootstrapping it on the target system.
MicroPower/pascal is very compact and can reside in as little as 8 Kbytes of
memory for small application programs. For complex applications, Micro
Power/Pascal can address as much as 4 Mbytes of memory.

ULTRIX-ll Operating System
ULTRIX-II is Digital's enhanced native-mode UNIX system software for
PDP-lis, providing a flexible, interactive programming environment for multiple users. It is an enhanced version of the UNIX Timesharing System, Seventh Edition (V7) by AT&T Bell Laboratories .

• ULTRIX-ll Features
ULTRIX-II includes all of the features found in Version 7, such as the Bourne
shell, C shell, shell scripts, pipes, the C compiler, and the Assembler. In addition, it includes a hierarchical file system that can provide a directory of files.
Subdirectories can also be created to manage groups of similar files. Input/
output can be performed by reading or writing into a special file that is associated with an I/O device. This makes file and device I/O similar for ease of
programming. It also allows a program to accept either a file or device without
changes, and extends the file protection mechanism to the I/O. The creator of
a file can permit or deny read, write, and access protection to other users.

4-14 • System Software and Layered Products
Digital has written many enhancements for ULTRIX-ll to provide better performance and maintainability_ These enhancements include
• TCPjlP networking_
• Source-level compatibility with System V_
• System performance improvements_
• Improved fault tolerance_
• Disk bad-block replacement_
• Automated installation and system generation_
• System tuning_
• Processor and peripheral device support_
• VI full-screen editor_

• Terminal Enabling Editor (TED).
• Overlay kernel for CPUs with combined instruction and data space.
• Special files.
• File-system table.
• Crash-dump analyzer.
• System-management commands.

• C shell.
• Kernel floating-point simulator.
• TIP remote login and file transfer.
• Source code control system with job control.
• Certain System V features.
• Certain University of California at Berkeley Version 2.9 features.
The ULTRIX-ll operating system is interfaced through the Bourne or C shell
command-line interpreter. Shell commands create processes that can communicate through pipes, create subsidiary processes, and synchronize the offspring processes. These interfaces permit users to create commands for
individualized routines that can be run in an interactive environment. This
means that they can produce their own command lines and command files to
assign symbolic names, evaluate numeric and logical expressions, accept
parameters, communicate with interactive users invoking the shell script, and
perform conditional and branching logic

4-15

ULTRIX-lllanguages include
• C-FORTRAN-77 and RATFOR-adds a C-type control structure to FORTRAN.
• BASIC-like interpretive language.
• Programmable desk calculator.
Software tools include a compiler writing system, document preparation programs, information handling routines, and graphics support. The customer
can easily install ULTRIX-ll and also run the System Exerciser Package to
verify that it is functioning properly.
RT-ll and CTS-300 Operating Systems
RT-ll is an operating system for realtime, single-user applications. It is well
suited for such applications as laboratory and factory instrument control, manufacturing process control, flight management, mapping, and numerous other
technical jobs. CTS-300 is a complete, multiuser software environment layered on top of RT-l1. It is designed to support commercial applications. CTS300 includes DIBOL, a programming language designed for writing business
applications .
• R T-ll Features
RT-ll uses the Digital Command Language (DCL). This makes access to operating system services as easy as typing English-like commands. Instead of having to manage system calls directly, services can be called through DCL
commands that will prompt for any missing parameters and will offer help if a
problem or question arises.

The keypad editor, KEDjKEX, is specially designed for a wide range of
videoterminals and takes advantage of all their advanced features. Screen-oriented editing immediately points out any editing problems and makes quick
changes to correct errors or to accommodate altered program needs.

4-16 • System Software and Layered Products

RT-ll systems offer a choice of three different operating-system monitors to
accommodate a range of RT-11 users. Digital supplies the system with a single-job monitor, a foreground/background monitor, and an extended-memory
monitor. A single-job monitor, called S], organizes the system for single-user,
single-program conditions. The foregroundfbackground monitor, called FB,
takes advantage of the fact that much central processor time is spent waiting
for external events such as I/O transfer or realtime interrupts. In the FB monitor, this waiting time is put to good use by allowing the CPU to be used for
other jobs while the principal (foreground) job is pausing. The extended-memory monitor, XM, allows both foreground and background jobs to extend their
effective logical program space beyond the 64-Kbyte space imposed by 16-bit
addresses on PDP-11 computers. The XM monitor contains all the features of
FB plus the capability of accessing as many as 4 Mbytes of memory.
There are three communications utilities that come with RT-11. VTCOM (Virtual Terminal Communications) allows RT-11 to connect to any host system
via a serial line and transfer Ascn files between the two systems. TRANSF
(Binary File Transfer) uses VTCOM and allows binary files to be transferred
between RT-11-based (RT-ll, CTS-300, RTEM-ll) systems via a serial line.
Ethernet Handlers for DEQNA allow users to write their own software to communicate over Ethernet hardware.
RT-11 provides even more tasks to make the system accessible to both novice
and experienced users alike. RT-11 offers an automatic-installation procedure
that installs the operating system simply by conducting an interactive dialog
with the user.
Programs can be written without explicitly identifying the output device. For
example, the device selection can be deferred until the program is run so that
printer output can be directed to the disk. When a new device is added to the
system, any old programs can be adapted easily.
RT-ll programs can also be developed as one of the tasks on an RSX-ll system using RTEM-11. Programs developed with RTEM-ll can execute on
appropriately configured RT-11 systems in the same manner as if they had
been developed on RT-11. Most programs developed on RTEM-ll can be
debugged and tested on RTEM -11. The execution environment supplied with
RTEM-11 is foreground/background (FB).
Although RT-11 supports only one command terminal, multiterminal support
capability allows programs to control up to 16 additional terminals .

• CTS-300 Features
CTS-300 is designed to support commercial applications. It consists of the RT11 operating system, described before, plus DIBOL (Digital's Business-Oriented Language), and a number of utilities. Most RT-11-dependent software
products can also be run on CTS-300.

4-17

CTS-300, like RT-ll, is a single-user system in the sense that there can be only
one system command terminal. However, multiple terminals running multiple
DIBOL jobs or developing multiple DIBOL programs are supported under the
three DIBOL runtime systems-single-user DIBOL (SUD), timeshared DIBOL
(TSD), and extended-memory timeshared DIBOL (XMTSD).
DIBOL is an easy-to-Iearn and easy-to-use language that allows commercial
applications to be developed in minimal time. DIBOL has a Data Division and
a Procedure Division, like COBOL, and provides the ability to manipulate
data, evaluate arithmetic expressions, redefine records, call other programs,
spool output, and access files.
Utilities included with CTS-300 are
• DEC form-defines video screen formats, checks entered data for range
and type, and totals and validates entered fields. It also supports additions,
inquiries, changes, and verifications to DMS-300 files.
• DMS-300-a data management utility that supports sequential access, random access, and keyed access to ISAM files.
• SORT/MERGE-a data management utility that permits users to easily
define the parameters for sorting and merging data files.
• Line Printer Spooler Utility-queues and manages files for printed output.

DSM (Digital Standard MUMPS)
DSM is a complete, multiuser system environment with data management
capability and the interactive, high-level language, MUMPS. With DSM, programs can be quickly written, tested, debugged, or modified to establish a
working application.
The MUMPS language, originally developed at Massachusetts General Hospital, has syntax and semantics oriented toward solving database-related applications. A novice programmer can very quickly produce useful working code,
although using the full range of MUMPS capabilities does require some programming experience.
MUMPS' text-handling capabilities allow the inspection of any data item for
content (such as particular keywords) or for format (letters, numbers, or punctuation characters in a string of text). The capabilities are useful for online
data-entry checking and correction.
The DSM hierarchical file structure allows data files to be designed to suit the
needs of a particular environment. Dynamic file storage simplifies expansion
or modification of the database. The database handler maintains an in-memory cache of disk data for high-performance data access and data sharing.

4-18 • System Software and Layered Products

DSM implements an extension of the 1983 ANSI Standard MUMPS language.
DSM allows a MUMPS application to define independent error handlers for
each execution level. A MUMPS debugger allows the DSM programmer to set
or clear breakpoints, single-step through MUMPS commands, and trace program execution .
• DSM-ll Features
DSM-ll is a complete multiuser operating system for the MicroPDP-ll systems that includes the MUMPS language interpreter and a powerful, high-performance data management capability. DSM-ll supports the following
features on the MicroPDP-ll:

• Mountable volume sets.
• Interjob communications.
• Memory-resident applications.
• Magnetic-tape streaming.
• IBM binary synchronous communications.
• Autoconfiguration.
• Unattended backup.
• System-level, transparent journal of database modifications can be maintained on either disk or magnetic tape.
• Output to devices (such as a printer) can be spooled.
• Bad-block management for all disk media.
• Online, high-speed database backup, disk-media preparation, and tape-totape copying.
• Hardware device-error reporting, system patching utility, and an executive
debugger for system maintenance.
• System installation and generation procedures.

4-19

• VAX DSM Features
VAX DSM is an implementation of Digital Standard MUMPS for VMS and
MicroVMS. VAX DSM includes the MUMPS language and a high-performance
database handling capability. VAX DSM includes all of the features of DSM11, plus has some specific VAX-related features. Additional VAX DSM features include
• Use of VMS facilities (batch, spooling, backup).
• Access to VMS I/O capabilities (sequential, relative, and indexed files, mailboxes, and DECnet).
• External call interface to nonMUMPS procedures ($ZCALL function).
• Transparent journal of database modifications.
• Mapping of DSM routines in virtual memory.

Table 4-1 • Operating-system Summary
Feature

User Interface
Shell
DCL
MCR
CCL
User-written
Text Editors
Keypad
Line
Screen
Batch Processing
File Management
Multikey ISAM
Single-key ISAM
Sequential
Relative
Random

Micro ULTRIX Micro/
VMS
-32m
RSX

RSX
-l1MPLUS

RSX11M

RSXl1S

MicroRSTS

RSTS/E

ULTRIX
-11

RT-11

CTS-

DSM

300*

.g.,

[

..
~

X
X

X
X
X
X

* Includes RT-ll, DIBOL-83, and DECform.

;:t

X
X

X
X
X

X
X
X
X
X

X
X

X
X
X

X
X
X
X
X
X

X
X
X
X
X

X
X

X
X
X

S'
i"

~
~
l:i'

4-21

• High-level Languages
Most operating systems need additional software, such as programming languages, to perform more specialized tasks than the operating system can perform alone. The supermicrosystem's programming languages are well-suited
to the needs of industry, science, education, and business. They are typically
developed in response to specific functional needs. Some languages, such as
FORTRAN, were originally intended for processing enormous amounts of
numerical data through complicated formulas at high speeds. Others, such as
COBOL and DIBOL, were developed for commercial applications in which
data management played a major role. And still others, like BASIC, were
invented for use by students who were unfamiliar with computers and needed
a simple, easy-to-learn language related to everyday speech. The descriptions
in this section attempt to show the special strengths of each Digital-supplied
language in satisfying specific application needs.
Table 4-2 summarizes the languages supported by each operating system.

BASIC
Four versions of BASIC are available for the supermicrocomputers. All four
versions use simple English commands, understandable abbreviations, and
familiar symbols for mathematical and logical operations. They are readily
accessible to programmers who are not computer specialists. They are used
extensively in education, small businesses, laboratories, and for personal use.
VAX BASIC is an interactive, shareable language processor for the MicroVMS
operating system. VAX BASIC takes full advantage of the VAX-ll floating
point, decimal, and character instructions.
BASIC-PLUS-2 is an extended BASIC compiler that runs under the Micro/
RSX, RSX-llM-PLUS, RSX-llM, Micro/RSTS, and RSTSjE operating systems. It takes full advantage of the PDP-11 floating-point and integer instruction sets.
BASIC-PLUS and BASIC-11 are conversational programming languages developed at Dartmouth College that use simple English-like statements and familiar mathematical notations to perform operations. BASIC-PLUS is an integral
part of the RSTSjE operating system, and is also available for the RT-11 operating system. BASIC-11 is optional for the CTS-300 operating system.
C
C is a concise, expressive, structured programming language designed by
AT&T Bell Laboratories for program development on UNIX systems. It is
included with ULTRIX-ll for the MicroPDP-ll family.

VAX C is an extended implementation of the C programming language developed by AT&T Bell Laboratories and is available as an option on MicroVMS.

4-22 • System Software and Layered Products

COBOL
COBOL is an industry-standard, data-processing language used extensively
for business applications because of its orientation toward character, string,
and file processing. Digital provides two versions of COBOL that are based on
the 1974 ANSI COBOL standard and implement many items from the proposed ANSI standard.
COBOL-81 runs on the MicroPDP-ll family under Micro/RSX, RSX-llMPLUS, RSX-llM, Micr/RSTS, and RSTSjE. COBOL-81 is a subset of VAX
COBOL. Performance can be improved by using COBOL-81 with the optional
KEF 11-BB Commercial Instruction Set option.
VAX COBOL is a fully featured COBOL compiler that meets the highest level
of federal requirements. It runs on MicroVAX systems that have MicroVMS.
Because COBOL-81 is a subset of VAX COBOL, COBOL-81 programs can, in
most cases, be compiled and executed on a MicroVAX or VAX without sourcecode changes.

CORAL-66
CORAL-66 is a block-structured language developed by the British government for realtime and process-control applications. The language is designed
to replace assembly-level programming in modern industrial and commercial
applications. It is used for long-life products where ease of maintenance and
flexibility are required. CORAL-66 is available only on MicroPDP-ll systems
with RSX-llM-PLUS, RSX-llM, or RSX-llS.

DlBOL-83
DIBOL-83 (Digital Interactive Business-Oriented Language) is a high-level,
procedural language designed specifically for interactive business data processing. DIBOL-83 is based on the DIBOL Standards Organization definition.
It is represented in two segments-a data division and a procedure division.
The data division defines the data that is used by the program. The procedure
division contains the executable statements. DIBOL-83 is available on
MicroPDP-ll systems under Micro/RSX, RSX-llM-PLUS, RSTSjE, and as
part of CTS-300. It is also available for MicroVAX systems running
MicroVMS.

FORTRAN
FORTRAN is the most widely used programming language for developing programs dealing with scientific applications. Three FORTRAN compilers are
available for the supermicrosystems:

4-23

• VAX FORTRAN for MicroVMS_
• PDP-11 FORTRAN-77 for Micro/RSX, RSX-11M-PLUS, RSX-11M, RSX11S, Micro/RSTS, and RSTS/E systems. FORTRAN-77 is available for RT11 from the Digital Classified Software Library.
• FORTRAN IV for RSX-11M-PLUS, RSX-11M, RSTS/E, and RT-11 systems.
VAX FORTRAN ccnforms at the full-language level to the ANSI FORTRAN
X3.9 1978 standard and is upward compatible from PDP-11 FORTRAN-77.
PDP-11 FORTRAN-77 combines the efficient numeric computation for which
FORTRAN is known with access to sequential, relative, and indexed files.
This makes PDP-11 FORTRAN-77 ideal for writing software that must manipulate and perform calculations on structures of numeric data, as in accounting
or statistical packages. PDP-11 FORTRAN-77 is built on an ANSI subset of the
ANSI FORTRAN X3.9 1978 standard.
FORTRAN IV is a fast, one-pass, optimizing compiler that implements an
extended superset of the ANSI X3.9 1966 standard for FORTRAN. FORTRANIV works efficiently in small-memory environments and is capable of
producing absolute binary code for stand-alone MicroPDP-11 systems or for
loading into ROM or PROM memory.

MUMPS
MUMPS is a language oriented toward database applications. It is an integral
part of DSM and is described in the DSM section.

Pascal
Pascal is a block-structured language that contains English-like commands
and logical grammar. There are two versions of Pascal for the supermicrocomputers-PDP-11 Pascal/RSX and VAX Pascal.
PDP-11 Pascal/RSX provides all standard Pascal features as well as extensions
that are designed to improve the productivity of the Pascal programmer.
These extensions make it simple to divide programs into easily managed problem sections and to enhance the computing power of the language. PDP-11 PascalfRSX is available as an option on Micro/RSX, RSX-11M-PLUS, and RSX11M.
VAX Pascal generates optimized, shareable code that takes full advantage of
the VAX hardware floating point and character instruction sets and the virtual memory capabilities of MicroVMS. VAX Pascal is available for MicroVAX
systems running MicroVMS.

4-24 • System Software and Layered Products

VAXAda*
VAX Ada is Digital's implementation of the government-validated compiler
called Ada for VAX systems_ VAX Ada is suitable for systems, computation,
general purposes, and in particular for realtime applications and multitasking
applications. Aside from government applications, VAX Ada is also strong in
the industrial and educational areas as well. VAX Ada fully· conforms to the
ANSI-83 Ada standard. VAX Ada is available for MicroVAX systems running
MicroVMS.

VAXAPL
VAX APL (A Programming Language) is a concise programming language that
simplifies the handling of numeric and character data organized as lists and
tables. VAX APL is a native-mode, shareable, reentrant interpreter that is
available on MicroVAX systems running MicroVMS. It provides a built-in
function editor, debugging aids, system communication facilities, and a file
system. VAX APL can execute lines of code immediately or store the code for
later execution.

VAX BLISS·32
VAX BLISS-32 is a high-level systems implementation language for VAX systems only. VAX BLISS-32 supports development of modular software according to structured programming concepts by providing an advanced set of
language features. VAX BLISS-32 provides access to most of the hardware features of the VAX to facilitate programming of realtime and/or hardwaredependent applications. It is especially intended for the development of operating systems, compilers, runtime system components, database file systems,
communications software, and utilities. VAX BLISS-32 is available for
MicroVAX systems running MicroVMS.

VAXPL/I
VAX PL/I is a block-structured, comprehensive programming language that
supports scientific computation, commercial data handling and organization,
and extensive string manipulation capabilities. VAX PL/I is available for
MictoVAX systems running MicroVMS.

* Ada is a registered trademark of the U.S. government.

4-25

VAX RPG II
VAX RPG II is an extended implementation of the RPG II language developed
by IBM as a problem-oriented language for commercial applications. VAX RPG
II includes extensions for integration with the VAX architecture. It provides a
convenient means of preparing a wide variety of reports and other commercial
data processing applications. VAX RPG II is available for MicroVAX systems
running MicroVMS.

-10.

Table 4-2 • High.Level Language Availability
Language

Micro
VMS

BASIC

COBOL

ULTRIX Micro/
-32m
RSX
X

RSX
-l1M·
PLUS

RSX·
11M

DlBOL-83

X
X

VAX Ada

VAXAPL

VAX BLISS-32

VAXPL/I

RSTS/E

* Includes RT-ll, DIBOL-83, and DECform.

ULTRIX
-11

RT.11

CTS·
300*

DSM

-§.,
~

FORTRAN

Pascal

Micro·
RSTS

CORAL-66

MUMPS

RSX·
11S

ii.....

'"~
.....

X
X

~
1:l-

X
X

4-27

• Information Management
Information management software ensures users and programmers that they
have an integrated system of data management capabilities to help them organize their data. Information management products help users do more for
themselves and give programmers more time to plan and develop new applications. Some of these products aid the programmer by reducing development
time and costs. This section briefly describes each of the information management products that are available on each of the supermicrosystems.

DATATRIEVE
DATATRIEVE is an interactive, query, report generation and data maintenance system designed for the less experienced computer user. DATATRIEVE
provides facilities for selective data retrieval, sorting, formatting, updating,
and report generation without the need for programming. VAX DATATRIEVE
is available for MicroVAX systems running MicroVMS. DATATRIEVE-ll is
available on MicroPDP-ll systems running Micro/RSX, RSX-llM-PLUS,
RSX-llM, and RSTS/E.

DECgraph
DEC graph is an interactive, menu-driven tool for generating graphs from
data. It is designed to be used by experienced computer users and novices
alike, offering a wide spectrum of capabilities for producing professional quality graphs. VAX DECgraph is available for MicroVAX systems running
MicroVMS. DECgraph-ll is available for MicroPDP-ll systems running
Micro/RSX, RSX-llM-PLUS, Micro/RSTS, and RSTS/E.

DECmail·ll
DECmail-ll is an electronic-message system that can create, edit, send, and
process messages, as well as store, search for, and retrieve messages held in
user folders. DECmail-ll is command-driven and includes an online help facility that provides the user with information that covers most normal situations. DECmail-ll can be used in a network environment. The Message
Router is an optional product for a network environment and provides a storeand-forward transport mechanism between RSTS/E, RSX-llM-PLUS, and
VAX/VMS nodes in a network. It can also communicate with DECmail/VAX
and with the ALL-IN-l office software system for VAX. DECmail-ll is available on the MicroPDP-ll systems running Micro/RSX, RSX-llM-PLUS,
Micro/RSTS, and RSTS/E. VAX-ll DECmail is available for MicroVAX systems running MicroVMS.

4-28 • System Software and Layered Products

FMS (Forms Management System)
FMS is designed to aid in the development of application programs that use
video forms. FMS manages the forms for application programs that use the
VT100 and VT200-compatible terminals. FMS provides the forms creator
with character attributes of reverse video, boldface, blinking, and underline.
It provides line attributes of double width, double height, and scrolling.
Screenwide attributes such as 80 or 132 column lines and reverse video are
included. Alternate character sets including the VT100 special graphics character set for line drawing are supported. FMS-11 is available for MicroPDP-11
systems running Micro/RSX, RSX-11M-PLUS, RSX-11M, RSTS/E, and RT-11.
It also is available for MicroVAX systems running MicroVMS.

INDENT
INDENT is a data-entry and forms management product for commercial applications written in DIBOL, COBOL, or BASIC-PLUS-2. INDENT provides
reverse video, boldface, underline, 132-column lines, scroll, split-screen,
reverse screen, and the line-drawing character set. INDENT form definitions
are created using a text editor. Data from a form is returned to the application
program when an entire form is completed or when an individual field is completed. INDENT is available for MicroPDP-ll systems running RSTS/E.
RMS (Record Management System)
RMS is a straightforward method of creating, updating, and modifying files
using sequential, relative, or multikey indexed access methods. RMS is an integral part of Micro/RSX, RSX-llM-PLUS, RSX-llM, Micro/RSTS, and RSTS/
E on MicroPDP-ll systems. It is also an integral part of MicroVMS on
MicroVAX systems.

VAX ACMS (Application Control and Management System)
VAX ACMS provides tools for the development and control of complex online
applications. These tools can reduce application development and maintenance time by replacing significant amounts of control and application code
with definitions stored in the VAX Common Data Dictionary (CDD). A wide
range of transaction processing and other complex online applications can be
developed and controlled with VAX ACMS, including inventory control, order
administration, and accounting applications. VAX ACMS is available on
MicroVAX systems running MicroVMS.

4-29

VAX CDD (Common Data Dictionary)
The VAX Common Data Dictionary provides a single, logical data dictionary
for MicroVAX systems running MicroVMS. This dictionary is built from one
or more physical dictionary files. Within this dictionary, the CDD maintains a
hierarchical directory of the user's data descriptions. CDD can contain definitions for VAX DATATRIEVE, VAX TDMS, VAX COBOL, VAX BASIC, VAX
DIBOL, and VAX PL/l. VAX CDD is prerequisite software for these products
and must be installed prior to their installation.
VAX DEC slide
VAX DECslide is a menu-driven text and graphic representation tool that creates slides. A combination of symbols and text is used in the menu selection.
VAX DECslide uses an interactive interface so that diagrams and text are displayed as they are entered. Editing functions allow changes to slides as they
are created or after they have been saved. A text menu and message area at the
bottom of the screen displays user options, help messages, and operation
status. A directory feature lists the slides, including the date and time of creation, slide name, and comments. VAX DECslide can incorporate lines, triangles, polygons, arcs, circles, ellipses, squares, and rectangles. It can merge two
created slides together to create a third illustration. And objects can be
increased or decreased in size, rotated, moved, copied, or printed. After slides
are created, they can be colored with available color palettes. They can be
printed in a single-size or double-size format, saved, copied, exported,
changed, or deleted. VAX DECslide is available for MicroVAX systems running MicroVMS.
VAX PRODUCER
VAX PRODUCER is a software package that allows users to create visually
based, interactive programs such as Computer Based Instruction (CBI), pointof-purchase demonstrations, marketing demonstrations, or information
retrieval systems. VAX PRODUCER is available on MicroVAX systems running MicroVMS.
VAX Rdb/ELN
VAX Rdb/ELN is a relational database management system designed for dedicated applications on systems running in the VAXELN application environment. VAX Rdb/ELN applications are developed using the VAXELN
development toolkit on a host VAX!VMS system. The resulting VAXELNbased Rdb/ELN application is then moved to the VAXELN target system
using disk media or an Ethernet local area network link. The application program executes on the target system as a dedicated database system. The network link to the host development system may be used for remote debugging.
VAX Rdb/ELN is available for MicroVAX systems running MicroVMS.

4-30· System Software.and Layered Products
VAX TDMS (Terminal Data Management System)
VAX TDMS is a product designed for the implementation of interactive,
forms-intensive applications running on MicroVAX systems that have
MicroVMS. VAX TDMS replaces applications program logic specific to terminal interactions with definitions that are external to the program. As a terminal subsystem, VAX TDMS can reduce applications development and
maintenance effort.
VAX VTX (Videotex)
VAX VTX is an interactive information update and retrieval product that
allows users to retrieve information from a local or distributed information
database. It is particularly well suited for office environments where there is a
need for a more efficient method of distributing information. Used along with
VAX VALU, it can provide access to other interactive applications such as electronic mail, transaction processing, and database queries. VAX VTX is available on MicroVAX systems running MicroVMS.

• Program Development Tools
Productivity tools allow program developers to simplify their programming
and information-management processes. By eliminating extensive maintenance and documentation tasks, more time is left for creating new applications
or changing existing ones. This section briefly describes each of the productivity tools that are available on each of the supermicrosystems.
ADE (Application Development Environment)
ADE is a software package for the non-programmer who develops small, simple applications requiring the processing of alphabetic, numeric, and data-oriented data such as personnel records, order processing, department budgets,
financial/forecasting models, mail lists, and telephone lists. ADE provides
easy-to-use facilities and functions for users to create their own databases;
add, change, or delete data; produce simple bar graphs; and write reports without waiting for formal programming and report generation. It features total
interaction between terminal and user, absence of technical jargon, use of
acronymns, easy transfer to and from more powerful application software
packages, full-screen handling, user prompts after each input, extensive
"HELP" messages to explain all commands, user protection of data, and automatic sorts, alphabetically, numerically, or chronologically. ADE is available
on MicroVAX systems running MicroVMS and on MicroPDP-ll systems running Micro/RSTS and RSTS/E.

4-31

MENU-U
MENU-ll provides the applications developer with the ability to present a
simple, menu-driven interface to the user on a videoterminal for both system
and application functions. MENU-ll accepts and executes commands related
to the menu items, to perform specific functions, without extensive user training in the Micro/RSTS or RSTS/E operating system. Three types of commands
provide screen formatting, program execution, and security access. These commands allow the developer to format the menu screen for the user's terminal
and to control the interfacing of the user with the system. MENU-ll is available on MicroPDP-ll systems running Micro/RSTS and RSTS/E.

VAX DEC/CMS (Code Management System)
VAX DEC/CMS is a program library for use as an aid in program organization,
development, and maintenance. It is a tool that allows programmers to manipulate information relating to their software project. Each CMS command
invokes a certain function, such as reserving a file for modification or obtaining a report listing development status. VAX DEC/CMS is available for
MicroVAX systems running MicroVMS.

VAX DECfMMS (Module Management System)
VAX DEC/MMS is a software tool that automates and simplifies the building
of software systems. It can determine what components in a described software system have changed and rebuild the system according to these changes.
When some modules of a software system are modified, dependent modules
may need to be recompiled. VAX DEC/MMS determines which modules need
to be recompiled, and performs the appropriate actions to ensure that the software system is recompiled and linked with all the latest changes. VAX DEC/
MMS is available for MicroVAX systems running MicroVMS.

VAX DEC/Shell
VAX DEC/Shell is a command language that provides a means of communicating with the VMS and MicroVMS operating systems. It is similar to the user
interface on a UNIX Version 7 system. It appears to its users as the Bourne
Shell and enables them to perform many of the same tasks done on a UNIX
Version 7 system.
VAX DEC/Shell consists of two parts-the command interface and the Shell
programming language. It also provides many of the most common UNIX utilities and commands and treats most files as stream files, a type of organization
that is familiar to UNIX users.

4-32· System Software and Layered Products

VAX DEC/Test Manager
VAX DEC/Test Manager is an automated regression testing system_ It allows
the programmer to organize tests, select tests for execution, and verify and
review the test results_ With VAX DEC/Test Manager, one can describe a set
of tests, classify the tests by assigning them to groups, and choose the combination of tests and/or groups to be run. The selected tests are executed and the
results compared with the known correct output. During the execution of a
test, VAX DEC/Test Manager provides a summary of a test's status. It also
allows the programmer to view the test results interactively, evaluate the test
run, and use the results to make modifications to the code being tested. VAX
DEC/Test Manager is available for MicroVAX systems running MicroVMS.
VAX DECOR
VAX DECOR is a graphics subroutine package that provides an interface
between the application program and other graphics devices. The interface is
device-independent and supports user-developed device handlers, as well as
those supplied with VAX DECOR. The package includes commonly required
device handler routines and detailed documentation designed to guide and
assist in the development of user-specified device handlers.
VAX DECOR is based on the ACM/SIGRAPH Graphics and Standard Planning Committee's 1979 NCore Graphics Proposal. VAX DECOR is available
for MicroVAX systems running MicroVMS.
H

VAX GKS/Ob (Graphics Kernel System)
VAX GKS/Ob is a subroutine library packaged as a VAX/VMS shareable image,
which implements the ISO and ANSI GKS standard for two-dimensional
device-independent graphics. VAX GKs/Ob conforms to level Ob of the GKS
standard. VAX GKS/Ob is a development tool that application programmers
can use to produce computer generated pictures. Any VAX/VMS language that
supports the VMS calling convention can call VAX GKS/Ob. VAX GKs/Ob is
available on MicroVAX systems running MicroVMS.

VAX Language-Sensitive Editor
The VAX Language-Sensitive Editor is a multilanguage, multiwindow, screenoriented editor specifically designed for program development and maintenance. The editor is Nlanguage.sensitiveH in that it provides users with VAX
language-specific information. This information enables both new and experienced programmers to develop programs faster, with fewer errors, through
VAX language-specific construction completion and error detection/correction
facilities. VAX Language-Sensitive Editor is available on MicroVAX systems
running MicroVMS.

4-33

VAX Performance and Coverage Analyzer
The VAX Performance and Coverage Analyzer is a tool to help MicroVMS
users analyze the execution behavior of their application programs_ The VAX
Performance and Coverage Analyzer has two functions-it can pinpoint execution bottlenecks and other performance problems in applications programs,
and it provides test coverage by measuring what parts of a user program are
executed or not executed by a given set of test data. This product is available
on MicroVAX systems running MicroVMS.

• Communications Software
After all of the necessary network hardware is set up, communications software makes the network functional within the Digital Network Architecture
(DNA) framework. Digital's network software is broadly divided into three
categories:
• DEe net-for communications among Digital systems.
• Internet-for communications with other manufacturers' equipment.
• Packetnet-for communications with other participants in public packetswitched networks.
For more detailed information on these communications software areas, refer
to Chapter 5-Networks. For descriptions of the software that is available in
each of these areas, refer to the Networks and Communications Buyer's Guide.

• Additional Documentation
VAXjVMS Technical Summary (includes MicroVMS)
VAX/VMS System Software Handbook

EJ-26070-48
EB-25966-48

VAX/VMS Information Management Handbook
VAXELN Technical Summary
PDP-II Software Handbook

EB-25780-44
EJ-30083-47
EB-25398-4I

RSX-II Handbook (includes Micro/RSX)
RSTS/E Handbook (includes Micro/RSTS)
ULTRIX Software Guidebook

EB-25742-4I
EJ-23534-I8
EJ-26I53-20
ED-28055-42
EB-26I25-46
EB-27333-4I

Networks and Communications Buyer's Guide
VAX Software Source Book
PDP-II Software Source Book

4-34 • System Software and Layered Products

• Introduction
Digital offers extensive capabilities that permit the linking of computers and
terminals into flexible configurations called networks. Networks increase the
efficiency and cost-effectiveness of data-processing operations.
Networking allows computer systems and terminals, whether located around
a facility or around the world, to share resources and exchange information,
files, and programs. The smaller computers in a network have access to the
powerful capabilities of larger systems, while the larger computers can take
advantage of smaller dedicated systems chosen for specific application environments.
Distributed processing is the general term used to describe the physical placement of computers where they are needed. As organizations become more complex and develop more sophisticated demands for computer resources, the
ability to network processors and share computing resources becomes increasingly important.

• Types of Systems
Two general types of systems can be implemented for most processing functions-the stand-alone system and systems connected by a network. With the
stand-alone system, all data is entered manually at the system by an operator
or from locally connected machines or instruments. In a network-connected
system, information can be entered locally or transferred to or from other systems through an electrically connected network link.
Stand-alone Systems
A single-user stand-alone system, shown in Figure 5-1, can process information received from several sources. Data can be entered from the console terminal keyboard, read from a diskette in the disk drive, or received from an
external machine or instrument. Only one user at a time can operate the
system.

5-2 • Networks
DISKETTE

TERMINAL
SUPERMICROSYSTEM

::: GEl:
MACHINE OR
INSTRUMENT

Figure 5-1 • Single-user Stand-alone System
A multiuser stand-alone system, an expansion of the single-user system, allows
several users to concurrently share a single processor. Several terminals can be
connected to the processor and the processing is timeshared between users as
shown in Figure 5-2. Data is entered from the same sources as the single-user
system.

USERA

DISKETTE

TERMINAL

SUPERMICROSYSTEM

:::GEl:

TERMINAL

MACHINE OR
INSTRUMENT

Figure 5-2 • Multiuser Stand-alone System
For realtime or runtime applications requiring that information be shared
between systems, there are several methods of communications.
As shown in Figure 5-3, Departments A and B of a small company both need
sales figures, and Department B also needs the inventory-level information of
Department A. Normally each department would be required to enter the
sales figures from the terminal keyboard of each system. Department B would
also be required to read the display of Department A and to enter the information manually into the Department B system from the keyboard.

5-3
INVENTORY LEVELS

SUPERMICROSYSTEM

DEPARTMENT A

DEPARTMENT B

Figure 5-3 • Manual Data Entry
A more efficient method of communications is shown in Figure 5-4. Department A manually enters the sales figures, processes the information, and
records both the sales figures and inventory levels onto the diskette. No manual entry would be required by Department B. Once the diskette is received
by Department B, the information can be processed.
e SALES FIGURES
elNVENTORY LEVELS

DISKETTE

TERMINAL
SUPERMICROSYSTEM

DEPARTMENT A

DEPARTMENT B

Figure 5-4 • Recorded Data Entry
Network-connected Systems
Two or more stand-alone systems can be electronically connected together by
a network. The network enables the efficient transfer of information between
systems (shown in Figure 5-5).
SALES FIGURES
e SALES FIGURES

~~_____e_IN_V_E_NT_OlR~Y_L_EV_E_L_S____-1~
TERMINAL

TERMINAL
SUPERMICROSYSTEM

SUPERMICROSYSTEM
DEPARTMENT B

DEPARTMENT A

Figure 5-5· Two-system Network

5-4 • Networks

Networks also enable systems located in different cities to communicate with
each other as shown in Figure 5-6. Through the use of modems, information is
transferred between offices in different locations over the standard telephone
lines.

SUPERMICROSYSTEM

CINCINNATTI SALES OFFICE

DEPARTMENT A

DEPARTMENT B

MAIN OFFICE

SUPERMICROSYSTEM

KANSAS CITY SALES OFFICE

Figure 5-6 • Remote Communications Network

• Digital Network Architecture
Digital Network Architecture (DNA) is a set of hardware and software networking capabilities that support communications between Digital's systems,
and between Digital's systems and other manufacturers' systems.
Digital-to-Digital communications are permitted through protocols, or rules,
that are defined by the DNA. DNA protocols are based on the architectural
models for open systems interconnection created by the International Standards Organization (ISO). These rules govern the format, control, and
sequencing of message exchange among Digital computers.
Internet products provide a means for Digital's systems to communicate with
systems built by other manufacturers. These products emulate common communications protocols and are data transfer facilitators rather than hardware
emulators.

5·5
DNA Structures
The lowest layer of the DNA structure, shown in Figure 5-7, is the physical
link layer. This layer governs electrical and mechanical transport of informa·
tion between systems that are connected. Computer systems can be physically
connected by cables, fiber optic lines, microwave transmissions, or switched
networks such as telephone lines. In addition to the physical connection, the
electrical signals on the lines must be properly defined. The signal characteristics and data rates are all defined by the hardware comprising the interface
module and the transmission link.
ISO SEVEN LAYERS

DNA LAYERS
USER

APPLICATION
NETWORK MANAGEMENT
PRESENTATION

NETWORK APPLICATION

SESSION

SESSION CONTROL

TRANSPORT

END COMMUNICATIONS

NETWORK

ROUTING

DATA LINK

PHYSICAL

PHYSICAL LINK

DNA FUNCTIONS
FILE TRANSFER
REMOTE RESOURCE ACCESS
DOWN LINE SYSTEM LOAD
REMOTE COMMAND FILE
SUBMISSION
VIRTUAL TERMINALS
TASK TO TASK
ADAPTIVE ROUTING

rl;1

DDCMP
POINT TO POINT X.25 ETHERNET
MULTIPOINT

Figure 5-7 • Digital Network Architecture Structure
The next highest layer of the DNA structure is the data litik layer. The data
link layer can prepare messages for transmission according to a specified proto·
col, check the integrity of received messages, and manage access to the channel. The data link is usually implemented by hardware and software. For a
simple asynchronous interface, the hardware contribution to the data link is
minimal. With other devices, such as the DEQNA Ethernet interface, almost
all of the data link layer is implemented in hardware.
Because of the data link layer, the routing layer can rely on error-free connection to adjacent nodes. It addresses messages, routes them across intervening
nodes, and controls the flow of messages between nodes. The routing layer
and higher layers are implemented in software.
Because the routing layer establishes the path, the end communications layer
can address the end machine without concern for route, and can perform end·
to-end error recovery.
The session control layer manages the system-dependent aspects of a communi·
cations session. For instance, when the end communications layer reliably
delivers a message from another manufacturer's system in the network, the
session control layer interprets that message for acceptance by the system soft·
ware.
The network application layer converts data for display on terminal screens
and printers.

5-6 • Networks

The network management layer monitors network operations by logging
events and collecting statistical and error information. It also controls network operations by tuning network parameters and testing .nodes, lines,
modems, and interfaces.
The user layer provides services that directly support the user and application
tasks such as resource Sharing, file transfers, and remote file access.

• Typical Network Configurations
Systems can be interconnected in a network in many different configurations.
Some of these configurations are described in this section.
Each of the participating systems in a network is called a node. Two nodes
communicate through a link or connection. Figure 5-8 shows supermicrosystem nodes linked in a network.

NODEC

NODEE

Figure 5-8 • Nodes Linked in a Network
The physical links can be cables, fiber optic lines, microwave transmissions,
and other conductors that form the data paths between two nodes such as
Node A and B. Logical nodes exist whenever two nodes can communicate
through a· physical link or through another node such as between· Node A
andD.
Node C is· required to route and transfer the message. This configuration
increases the transmission time between nodes but decreases the cost because
fewer physical links are required. As the number of physical links increase in a
fiilly connected network, the resulting costs increase. Figure 5-9 shows the
relationship of the number of nodes to the physical links.

5-7

3 NODES
3 PHYSICAL LINKS

4 NODES
6 PHYSICAL LINKS

5 NODES
10 PHYSICAL LINKS

6 NODES
15 PHYSICAL LINKS

Figure 5-9· Fully Connected Network Nodes
One method of reducing the number of physical links is the multidrop or multipoint network shown in Figure 5-10. More than two nodes can be connected
to the same physical link. Each node is required to determine which of the
messages are dedicated to that node and to manage access to the links thus
avoiding conflict between nodes.
In a network with centralized control, one node such as a mainframe computer is required to determine which of the remaining nodes can send messages, where the messages will be sent, and the length of the messages. In a
network with distributed control, each node recognizes a procedure that
allows the node to access the network independently.
In a star network, as shown in Figure 5-10, one node is designated as the central node and all other outlying nodes are physically connected to it. This network is efficient because most of the communications are between the central
node and one outlying node, such as a timesharing network or a shared word
processor system. Because all messages must be transferred through the central node, it must process many transactions when the message rate is high. If
the central node fails, all transactions halt. In some networks, distributed control may be implemented, thereby decreasing the load on the central node.
In a ring network, each node is physically linked to two adjacent nodes, as
shown in Figure 5-10. Messages circulate around the ring and each node
retransmits the messages not addressed to itself. This method is less complex
than the generalized routing method because each node is required to transmit the message only to the adjacent node.
Distributed control in a ring network may be implemented through token passing. A special token message circulates around the ring and a node can claim
access to the network by receiving the token message as it passes through.

5-8' Networks

MULTIPOINT-NETWORK LINK

~ OUTLYING NODE

AENTRALNODE

STAR NETWORK

RING NETWORK

r r r r
BUS NETWORK

UNCONSTRAINED NETWORK

Figure 5-10 • Network Configuration Types
The bus network, shown in Figure 5-10, is similar to a multidrop link. Messages placed on the shared physical link reach all nodes, and the intended
receiver must recognize the message's address in order to receive the transmission. None of the nodes, however, have to route or retransmit messages
intended for other nodes. A bus network typically uses distributed control.
There is no single point of failure. The Ethernet local area network is a bus
configuration.

5-9

An unconstrained network is shown in Figure 5-10. The placement of physical
links is usually determined by the cost of the physical connections, by the number of messages to be transferred, and by the network reliability requirements. Some of the nodes in this network may have the capability to route
messages to other nodes. Long-distance packet-switched networks are often
unconstrained.

• Types of Links
Several interface options are provided for the supermicrosystems to support
the implementation of the physical and data link levels of the DNA.
Ethernet Link
As computer systems such as word processors, workstations, personal computers, and departmental systems become more numerous and accessible, an
integrated communications network can increase productivity and reduce
data processing costs.

Ethernet provides local area network technology through a hardware and software combination to create a physical communications channel between systems. This allows large amounts of data to be exchanged at high rates between
systems located within limited distances.
Figure 5-11 shows the physical links and the DNA layers that perform the networking functions of Ethernet. The DEQNA is the interface module that provides the internal connection to the Q22 bus of the supermicrosystems. The
hardware elements include the DEQNA Ethernet interface, the transceiver
cable, and the H4000 Ethernet transceiver and coaxial cable. The coaxial
cable can be in lengths of up to 500 meters (1,640.5 feet). The transmission
rate can be as many as 10 Mbits per second.

5-10' Networks
MICROSYSTEM NODE

DNA LAYERS

DATA ENCAPSULATION

USER
NETWORK MANAGEMENT
NETWORK APPLICATION
SESSION CONTROL
END COMMUNICATIONS
ROUTING
DATA LINK

LlJKDJA~A~:~~WIONI--_ _-+_-i
COLLISION HANDLING
ENCODE/DECODE
TRANSMIT/RECEIVE
COLLISION DETECT
CARRIER SENSE

PHYSICAL LINK

ETHERNET
COAXIAL CABLE

H4000 TRANSCEIVER

Figure 5-11 • Ethernet Physical Link and Data Link Layers
Figure 5-12 shows a small-scale Ethernet configuration using a single coaxial
cable. Each cable segment can include up to 100 transceivers or nodes.

A transceiver cable, which can be up to 50 meters (164 feet) in length, connects the H4000 transceiver to the DEQNA Ethernet interface.
COAXIAL CABLE SEGMENT
(500M MAX)
SUPERMICROSYSTEM NODE

Q22BUS

NODE

Figure 5-12 • Small-scale Ethernet Configuration

5-11

A medium-scale Ethernet configuration is shown in Figure 5-13 and includes
a repeater that connects two cable segments. Each coaxial cable can be a maximum of 500 meters (1,640.5 feet) in length and can operate with up to 100
transceivers, including the repeater transceiver.
SUPERMICROSYSTEM
NODE

NODE

Figure 5-13 • Medium-scale Ethernet Configuration
A large-scale Ethernet configuration is shown in Figure 5-14 and consists of
five coaxial cable segments. The segments are connected by repeaters and can
attach up to 1,024 nodes. Each segment is connected by remote repeaters
with up to a maximum distance of 1,000 meters (3,281 feet) between
repeaters.

Figure 5-14 • Large-scale Ethernet Configuration
The H 4000 transceiver and tap can be installed on an operating cable with no
disruption of the system operations. The transmit, receive, carrier sense, and
collision-detection functions of the physical link layer are implemented in the
H 4000 transceiver.
The access control method used by Ethernet is called Carrier Sense-Multiple Access with Collision Detection (CSMA/CD). To transfer a message, a
node monitors the transmissions on the cable to sense a pause between the
data packets. The node continues to sense the data while initiating the transmission. If another node transmits simultaneously, both nodes will stop transmission and wait for a random interval of time before initiating another
transmission.
The DEQNA Ethernet interface encodes and decodes the data exchanged
with the H4000 transceiver. In addition, it implements the functions of the
data link layer by encapsulating and de-encapsulating messages, handling collisions, and filtering received messages. The DECnet software provides the
remaining functions of the message transfer such as routing, end communications, and session control.

5-13

Up to eight Ethernet nodes can be connected to a single H4000 transceiver
using the DELNl Ethernet concentrator as shown in Figure 5-15. These nodes
can include Q-bus processors with the DEQNA interface, or UNIBUS PDP-ll
or VAX processors with the DEUNA Ethernet interface. For localized connections, up to eight processor nodes can be interconnected using the DELNl concentrator without physical connection to the H4000 Ethernet transceiver.
SUPERMICROSYSTEM
NODE

NODE

TRANSCEIVER
CABLE

ETHERNET COAXIAL
CABLE

H4000 TRANSCEIVER

Figure 5-15 • Ethernet Node with DELNI Concentrator
Asynchronous Links
The nodes in a network can be connected by asynchronous links when highspeed transfers and efficiency are not required. Data transmitted through the
link is character-oriented. The characters can be five to eight bits in length,
preceded by a start bit, and followed by stop bits. The time interval between
the stop bits of one character and the start bit of the next character can vary,
thereby reducing the efficiency of the data communications. The electrical
and mechanical characteristics of the signals and interfaces are defined by
standards created by the Electrical Industries Association (ElA) and the International Consultative Committee on Telegraphy and Telephony (CCITT).

5-14' Networks
The physical link can take one of two forms:
• EIA Standard Signals, Remote Connection-Communications between
computer systems and devices over long distances can be implemented
using modems and telephone lines as shown in Figure 5-16. The modems
convert the system and device signal levels into signals acceptable by the
telephone lines. The telephone lines can be private, leased, or part of the
public-switched network. The remote device can be a terminal or any asynchronous interface of another computer system. The modems of each node
must be of a compatible type .
• EIA Standard Signals, Local Connection-For local communications in
the same area or within the same building, computer systems and terminals
can be connected by EIA null modem cables as shown in Figure 5-17. The
null modem cable transfers the serial EIA data and control signals between
the nodes. The local device can be a terminal or an asynchronous interface
of another computer system.

5-15
SUPERMICROSYSTEM NODE

REMOTE
DEVICE

Figure 5-16' Remote Connection, Asynchronous Link

5-16· Networks
SUPERMICROSYSTEM NODE

EIA
NULL
MODEM
CABLE

LOCAL
DEVICE

Figure 5-17 • Local Connection, Asynchronous Link
For descriptions of optional asynchronous interface modules, refer to Chapter
3-System Options_
Synchronous Links
Synchronous links are used for communicating where speed and efficiency are
important. Synchronous communications send a block of characters enclosed
in a frame. The contents of the frame vary from one protocol to another, but
they typically consist of text, identification of the beginning and the end of
the frame, and information ensuring reliable reception of the text. Because
the amount of extra information needed to complete the frame is fixed, the
efficiency of synchronous transmission increases as the size of the textblock
increases.

5-17

Some synchronous protocols, such as Digital's DDCMP and IBM's BISYNC,
require the length of the text to be an integral number of characters or bytes.
These are called character-oriented protocols. Others, including IBM's SDLC
and the International Standards Organization's HDLC, allow the text length
to be any number of bits. These are referred to as bit-oriented protocols.
The physical line can take one of three forms:
• Modem Connection, Remote Connection-For synchronous communications over long distances, the interface module is connected to a modem as
shown in Figure 5-18. The modem connection can be specified by one of
the EIA standards (RS232-C, RS422, or RS423) or by a CCITT standard
(V.24, V.28, or V.35). The modem connects to a private line, a leased telephone line, or to the public-switched telephone network. The choice of
modem and the line connecting the modems will depend on the speed of
the data communications.
• Modem Eliminator, Local Connection-Connecting two local synchronous devices that interface via the EIA or CCITT standards requires a
modem eliminator as shown in Figure 5-19. The distance between devices
can be from several hundred feet to a few miles, depending on the speed of
transmission and other factors.
• Integral Modem, Local Connection-The DMVll series of synchronous
interface modules contains an integrated modem that is compatible with
the Digital DDCMP protocol. These interfaces can be used for point-topoint or multidrop-network configurations. Figure 5-20 shows the connections to the local-device interfaces.

5-18· Networks
SUPERMICROSYSTEM NODE

REMOTE
DEVICE

Figure 5-18· Remote Connection, Synchronous Link

5-19
SUPERMICROSYSTEM NODE

EIA
CABLE

LOCAL
DEVICE

Figure 5-19 • Local Connection, Synchronous Link

5-20 • Networks

SUPERMICROSYSTEM NODE

DDCMP INTEGRAL
MOOEMCABLE

LOCAL DEVICE
DMV11
DMR11
DMP11
DUP11

Figure 5-20 • DDCMP Local Connection, Synchronous Link
For descriptions of optional synchronous interface modules, refer to Chapter
3-System Options_

• Network Software
After the network links are established, communications software makes the
network functional within the DNA framework.
Digital's network software is broadly divided into three categories-DECnet,
for communications among Digital systems; Internet, for communications
with other manufacturers' equipment; and Packetnet, for communications
with other participants in public packet-switched networks.

5-21

DECnet Communications
DECnet software supports communications among Digital computer systems.
Data on the physical links is independent of system type, and the DECnet software converts the received data into formats that the operating system is prepared to accept. DECnet allows full use of the network by providing higherlevel network functions. The following are the key elements:

• Task-to-task communications allow programs that are executing in different systems, under different operating systems, and written in different
languages, to exchange information.
• File transfer supports the exchange of files between different operating systems.
• Remote file access allows the user to read, write, or modify files on another
system.
• Remote command file submission and execution allow one computer system
to direct another to execute commands that are resident on the remote system or sent as part of the request.
• Downline loading allows programs developed on a system with appropriate
peripherals and resources to be transmitted to another system such as a
small, memory-only system, for execution.

• The network virtual terminal gives a terminal user logical connection to a
remote system with the same operating system; the terminal operates as if
it were directly connected to the remote system.
• Network management provides the tools for monitoring and controlling network operation in a distributed environment.

Refer to Table 5-1 for a complete comparison of DECnet products.
Internet Communications
Digital's supermicrosystems can communicate with another vendor's equipment through software that emulates a protocol supported by that vendor.
Although the name of the protocol may correspond to a specific device made
by another manufacturer, the supermicrosystems emulate only the communications protocol used by that device and not the capabilities of the device.

Supermicrosystem nodes in an Ethernet link can also communicate with IBM
systems through a Systems Network Architecture (SNA) gateway. The SNA
gateway is an Ethernet node solely responsible for interfacing to an IBM system using IBM's System Network Architecture. Figure 5-21 shows the SNA
gateway connections.

5-22 • Networks

IBM
SYSTEM

SNA
GATEWAY

SNA
NETWORK

ETHERNET COAXIAL
CABLE

L-l

L....J

NODE

DEONA

.r-.

Q22BUS

"
SUPERMICROSYSTEM
NODE

Figure 5-21 • Ethernet to SNA Gateway Node
Packnet System Interface
Public packet-switched networks can be an alternative to leased or dialup telephone lines for long-distance communications.

The charge is based on the volume of data transmitted rather than the fixed
charge of a leased line. Access, speed, and reliability are better than that provided by a dialup line. The network also compensates for differences in transmission speeds between nodes and may offer services in addition to
communications.
The Packnet System Interface (PSI) software can coexist with, or operate as a
layered product under, DECnet software. This allows DECnet facilities to be
used between nodes connected through the packet-switched network and
through leased or dialup lines. PSI makes communications possible with any
other system (Digital or non-Digital) connected to the packet-switched network. PSI software supports task-to-task communications and remote terminal access to the supermicrosystems.
The communications protocol, part of the data link layer, is implemented in
the hardware of some interface modules. For other interface modules, this protocol is provided by communications software.

Table 5-1 • DECnet Products and Features
Feature

DECnet-llM DECnet-llS
DECnet·
11M·PLUS

DECnet/E

DECnet·
ULTRIX

DECnet·RT

X2 J

DECnet·VAX

DECnet·
Micro/RSX

Task·to-task
communications

File transfer

Remote file access

Remote command
file submission

Remote command
file execution

Downline loading

Network virtual
terminal

Network
management

X' 2

Offers local users network access to remote file systems. Does not allow users on remote systems to access local files.

Requester-only function.

J DECnet-llS does not support connection from remote virtual terminals.

'"t;

5-24 • Networks

• Digital PC Connection
The Professional 300 series and the Rainbow 100 series can be connected to
the supermicrosystems with DECnet. However, the DECmate II and III must
be connected to the supermicrosystems over an asynchronous line.
Two modes of communications are supported:

• File transfer supervises the transmission of an entire file between the DECmate series and a supermicrosystem without operator intervention. The
supermicrosystem must have DX/11M running under RSX-11M or RSX11M-PLUS, DX/RSTS running under RSTS/E or Micro/RSTS, or DX!VMS
running under VMS. DECmate must have the WPS-8 Communications
Package.

• Terminal emulation provides character-by-character communications that
looks to the supermicrosystem like a terminal. DECmate, with the WPS-8
Communications Package, emulates an alphanumeric terminal (VT100 or
VT52).

• mM and Apple PC Connection
The IBM PC and the Apple Macintosh can now communicate with the
MicroVAX II system. This connection allows customers to get more use out of
their personal computers in a number of areas. They may want to use applications, tools, and programming languages that are on the MicroVAX. They may
also want to network to VAXes in other departments, perhaps communicating
with the corporate mainframe through VAX systems to give them access to
corporate databases. There are several products designed to connect the IBM
and Apple personal computers to the MicroVAX II.
• VTerm II, which allows an IBM PC to emulate a VT100 terminal.
• poly-com 220 and poly-com 240, which allow an IBM PC to emulate VT220
or VT240 terminals.
• DECnet-DOS, which allows an IBM PC to function as an end node in a
DECnet network.
• Apple's MacTerminal package, which lets a Macintosh emulate a VT100
terminal.
Please consult your Digital sales representative for more information on any of
these software products.

5-25

• Additional Documentation
Networks and Communications Buyer's Guide

ED-28055-42

Networks Handbook

EB-26013-42

Networks Guidebook

EB-27241-42

Microcomputer Products Handbook

EB-26078-41

5-26 • Networks

• Introduction
Computer architecture is defined as the characteristics of the computer that
are observed by the operator and programmer at the assembly-language level.
These characteristics, which exist in both the VAX and PDP-llarchitectures,
include instructions sets, data types, addressing modes, registers, address
space, and memory management. This chapter discusses the similarities of
and differences between these architectural characteristics.
Multiple system implementations of common computer architectures have
allowed Digital's customers to continue to upgrade and expand, at the lowest
possible cost, as their needs have changed. Within each of the VAX and PDP11 families, customers can move to other computers without reinvesting in
software, peripherals, communications devices, or training. Common computer architectures ensure computer compatibility.
For a simple overview listing of the architectural characteristics of these two
families, refer to Table 6-1. For detailed descriptions of the VAX and PDP·ll
architectures, refer to the VAX Architecture Handbook and to the PDP-ll
Architecture Handbook. Ordering information for these books is provided in
Appendix D-Documentation.
Table 6-1 • Architectural Characteristics Overview
Characteristic

MicroVAX

Physical Address 1 Gbyte on MicroVAX II
Space
8 Mbytes on MicroVAX I

MicroPDP-ll

4 Mbytes

Virtual Address
Space

4 Gbytes total instruction
and data space

64 Kbytes data space

64 Kbytes instruction space

I/O System

Memory-mapped

8 Kbytes I/O space

6-2 • Architecture Summary

Table 6-1 • Architectural Characteristic~Overview (Cant.)
Characteristic

MicroVAX

Operand Types

Bit-field

MicroPDP-ll

8-bit byte

16-bitword

32-bit longword
32-bit floating!

32-bit floating

64-bit floating!

64-bit floating

64-bit floating with different precision l
128-bit floating!
Registers

16 general

16 general for MicroPDP11/83 and MicroPDP-ll/73
8 general for MicroPDP11/23

CPU Execution
State

32-bit processor status
longword

16-bit processor status word

Addressing
Modes

Register2

Autoincrement

Autoincrement-deferred

Index

Index (MicroPDP-11/83
and MicroPDP-ll/73 only)

Displacement-deferred
Literal
Interrupt
System

1 May

Automatically vectored
interrupts
16 hardware levels

4 hardware levels

16 software levels

4 software levels

be emulated in some implementations

2 Indexed vatiations

Automatically vectored
interrupts

6-3

Table 6-1 • Architectural Characteristics Overview (Cont_)
Characteristic

MicroVAX

MicroPDP-ll

Operating
Modes

Kernel

Executive
Supervisor

Supervisor

User

Data Types

Bit-field (MicroPDP-ll/23
only)
Byte

Byte

Word

32-bit longword
64-bit longword
128-bit longword '
Instruction Sets Integer arithmetic

Character (MicroPDP-ll/23
only)
Integer arithmetic

Integer logical

Floating point

Byte string!

Byte string (including decimal byte string)

Basic flow control (branch, Basic flow control (branch,
jump)
jump)
Basic call

Basic call

Enhanced flow control (do
loops)
Queue management
Polynomial (Taylor Series)
Enhanced procedure call
Instruction
Length

Emulated

I- n bytes

2,4, or 6 bytes (CIS instructions longer-applies to
MicroPDP-ll/23 only.)

6-4 • Architecture Summary

Table 6·1 • Architectural Characteristics Overview (Cont.)
Characteristic

MicroVAX

MicroPDP·ll

Floating Point

D, F, G standard in hardware of MicroVAX II
H is emulated in software
on MicroVAX II

D and F standard in hardware and in microcode on
MicroPDP-ll/83
D and F standard in microcode on MicroPDP-ll/73
D and F optional on
MicroPDP-ll/23

D and F or F and G are
standard on MicroVAX I
CIS

Optional on
MicroPDP-ll/23

Micro VAX Architectural Characteristics
The MicroVAX architecture includes the following characteristics:

• 4-Gbyte virtual-address space.
• I-Gbyte physical-address space on the MicroVAX II; 8-Mbyte physicaladdress space on the MicroVAX I.
• 32-bit word size.
• Memory management.
• Sixteen 32-bitgeneral registers.
• Multiple addressing modes.
• 32 processor-priority levels.
• Vectored hardware and software interrupts
• Variable instruction size.
• Subset of the VAX instruction set.
• Emulation support for the unimplemented VAX instruction set except for
PDP-ll compatibility mode.
• Subset of the VAX privileged registers.
• Subset of the VAX data types.
The MicroVAX instruction set uses 32-bit addressing that enables the processor to address up to four billion bytes of virtual-address space. The processor's
memory-management hardware includes mapping registers used by the operating system that provide page protection by operating mode.

6-5

The MicroVAX provides sixteen 32-bit general registers that can be used for
high-speed, temporary storage or as accumulators, index registers, or base registers_ One of these registers is a program counter and three registers provide
procedure call instructions_
The processor also offers a variety of addressing modes, including an indexedaddressing mode, that use the general registers to identify instruction operand
locations_
The instruction set includes character-string and floating-point instructions,
as well as integer, logical, queue, and bit-field instructions. Instructions and
data can start at any arbitrary byte boundary in memory or, in the case of bit
fields, at any arbitrary bit in memory.
For further reference, the sections "KA630 CPU Module" and "KD32-AA
CPU Modules" in Chapter 2-System Hardware describe the MicroVAX II
and MicroVAX I CPUs, respectively, as implementations of the VAX architecture.
MicroPDP·ll Architectural Characteristics
The MicroPDP-ll architecture includes the following characteristics:
• 64-Kbyte virtual-address space.
• 4-Mbyte physical-address space.
• 16-bit word size.
• Memory management.
• One or two sets of eight 16-bit general registers.
• Multiple addressing modes.
• Eight processor-priority levels.
• Variable instruction size.
• Full set of PDP-II privileged registers.
• Full set of PDP-II data types.
• Full set of PDP-ll instructions.
The MicroPDP-ll instruction set uses 16-bit addressing that provides a
directly addressable virtual-address space of 65,536 (64 K) bytes. Actual memory capacity in the MicroPDP·ll is 4,096,000 (4M) bytes. Memory management translates the 16·bit virtual addresses into the full 22-bit physical
addresses needed to address 4 Mbytes. The processor's memory-management
hardware includes mapping registers used by the operating system that pro·
vide page protection by operating mode.

6-6 • Architecture Summary

The MicroPDP-11/23 provides eight 16-bit general registers that can be used
for high-speed, temporary storage or as accumulators, index registers, or base
registers. Two registers with special purposes are the program counter and the
stack pointer. The MicroPDP-ll/83 and MicroPDP-ll/73 have a second set of
eight 16-bit general registers with a program counter and stack pointer.
The MicroPDP-ll processors offer a variety of addressing modes, including
an indexed-addressing mode, that uses the general registers to identify instruction operand locations.
Floating-point instructions are standard on the MicroPDP-ll/83 in hardware
and in microcode, and on the MicroPDP-ll/73 in microcode, and available as
an option on the MicroPDP-ll/23. Character-string instructions are offered
as a hardware option on the MicroPDP-ll/23 only.
For further reference, the sections "KDJll-BF CPU Module", "KDJll-BB
CPU Module", and "KDF11-BF CPU Module" in Chapter 2-System Hardware describe the MicroPDP-ll CPUs as an implementation of the PDP-ll
architecture.

• Address Space and Memory
MicroVAX systems use the 8-bit byte for addressing. MicroVAX instructions
use a 32-bit virtual address to identify these byte locations. It is called a virtual address because it is not the real address of a physical-memory location. It
is translated into a real address by the processor under operating-system control. A virtual address, unlike physical-memory addresses, is not a unique
address of a location in memory. Two programs using the same virtual address
might refer to two different physical memory locations, the same physical
memory location, or the same physical memory location using different virtual
addresses. The set of all possible 32 -bit virtual addresses is called virtualaddress space.
The MicroPDP-11 also uses the 8-bit byte for addressing. PDP-11 instructions
use a 16-bit virtual address to identify a byte location. Memory management
translates 16-bit virtual addresses into the 22-bit physical addresses needed to
address 4 Mbytes of memory.
MicroVAX and MicroPDP-ll instructions can address memory using either
direct addressing or indirect (deferred) addressing. With direct addressing,
the address in one of the general registers points directly to the data in memory (Figure 6-1). With indirect addressing, the address in a general register
points to an address stored in memory, which in turn points to the data (Figure 6-2).

6-7

DATA
REGISTER

MEMDRY

Figure 6-1 • Direct Addressing

'-------'

ADDRESS

DATA

MEMORY

Figure 6-2 • Indirect or De/erred Addressing
MicroVAX and MicroPDP-ll memory locations and peripheral-device (1/0device) registers are addressed in the same manner. The first 8 Kbytes of physical-address space are reserved for I/O-device addressing. Other physical-memory locations have been reserved for interrupt and trap handling.
Physical-address Space
Physical-address space is a contiguous series of word-addressable hardware
locations used to define memory and I/O-device registers.

A physical address in the MicroVAX system is 30 bits long and provides a physical-address space of 1 Gbyte. Of these, 512 Mbytes are in memory space and
512 Mbytes are in I/O space. The I/O space is largely empty usually utilizing
only the first 8 Kbytes.
The MicroPDP-ll architecture specifies that physical addresses may be up to
22 bits long and provides a physical-address space of 4 Mbytes. As in the
MicroVAX, the first 8 Kbytes are used for I/O-device addressing.

6-8 • Architecture Summary

Virtual-address Space

Through the MicroVAX and MicroPDP-ll memory-management hardware,
the operating system provides an execution environment in which users can
write programs without having to know where the programs are loaded in
physical memory. In this environment, users can write programs that are too
large to £it into the allocated physical memory. This environment is called virtual-address space.
A virtual address is a 16-bit or 32-bit integer that a program uses to identify a
storage location in virtual memory. Virtual memory may be the set of all physical-memory locations in the system plus the set of disk blocks that the operating system designates as extensions of physical memory.
A program written for a MicroVAX processor sees a 32-bit address space that
references up to four billion bytes. This 4-Gbyte window is known as the program's virtual-address space. Each MicroVAX program's virtual-address
space begins with address 0 and can extend upward to a maximum of 4
Gbytes.
A program written for a MicroPDP-ll processor sees a 16-bit address space
that references up to 64 Kbytes of memory. This 64-Kbyte window is known
as the program's virtual-address space. Each MicroPDP-ll program's virtualaddress space begins with address 0 and can extend upward to a maximum of
64 Kbytes.
Memory Management

Memorymanagement enables the operating system to map virtual addresses
into physical addresses. This physical address is then used to specify a location
in the storage device.
The MicroPDP-ll system has to convert a fairly small virtual address to a
large physical address. This allows the 16-bit MicroPDP-ll processor to
access a very large physical memory a little at a time. Figure 6-3 shows the
MicroPDP-ll translating the 16-bit virtual addresses into the 22-bit physical
addresses.

6-9
000

OOOa

000

002e

000

0046

000

006 s

000

010 e

177

7728

177

7748

177

776 8

:::-

VIRTUAL
ADDRESS
SPACE

000
000

0 02 6

000

004.

000

006 8

777

766.,

777

770 8

777

7728

777

7748

777

776 8

MEMORY
MANAGEMENT

II ,

0008

00
00

\
PHYSICAL
ADDRESS
SPACE

Figure 6-3 • MicroPDP-ll Memory Management

Micro VAX memory management is almost exactly the reverse of the process
for the MicroPDP-ll. The MicroVAX processor can express virtual addresses
over a 4-Gbyte range, yet no real memory exists that can hold such a program.
A scheme must be used to allow the physical memory to contain only those
parts of the virtual-address space that are currently in use.
A combination of MicroVAX microcode and operating-system software creates this memory-management environment. Initially, none of the user's program is in physical memory. Instead, it is all on the storage device. As the
user's program references its virtual-address space, the necessary "pages" of
the user's program are brought into physical memory and the user's virtual
addresses are mapped (pointed or translated) to the appropriate physical
addresses. Eventually, physical memory becomes full and the operating system must create space for new pages. The oldest pages are kicked out of physical memory (Le., copied back out to the storage device) allowing the newest
pages to fit in. This entire process is called demand paging and is central to
how the MicroVAX can run programs that are much larger than the existing
physical memory. Figure 6-4 shows the MicroVAX translating the 32-bit virtual addresses into the 24-bit physical addresses.

6-10 • Architecture Summary
MicroVAX
VIRTUAL
ADDRESS
SPACE

0.----'-----,

PROGRAM
REGION

1 GBYTE = 230

MICROVAX
PHYSICAL ADDRESS
SPACE

INSTALLED
MEMORY
CONTROL
REGION
MEMORY
ADDRESS SPACE
BEYOND
INSTALLED
MEMORY

MEMORY
MANAGEMENT

PHYSICAL
MEMORY
ADDRESSES

4 MBYTES

\
SYSTEM
REGION

RESERVED

Q22-BUS
110 SPACE

I/O
SPACE
ADDRESSES

RESERVED

4 GBYlES ~ 232

Figure 6-4 • Micro VAX Memory Management
Memory Protection
The MicroVAX and MicroPDP-ll memory management provides a second
important feature beyond managing where the code and data should go_ Memory management also controls who may have access to the code and data. This
is important if a multiuser system is to protect the operating-system software
from the users as well as protect individual programs from one another.

6-11

The view that each running program has of physical memory is completely
controlled by the operating system. To the program, sections of physical memory can be labeled read/write, read-only, or invisible. For example:
• The program code should be marked read-only if the programmer has written pure code that does not modify itself.
• Fixed program data can also be marked read-only so that it cannot be damaged.
• Variable program data is marked read/write.
• Sections of memory the program has no need to know about are made invisible.
Both the MicroVAX and the MicroPDP-ll families assign these protection
attributes on a per-page basis.

6-12· ArchitectureSummary

• Registers and Stacks
A register is a location within the processor that can be used for high-speed,
temporary data storage and addressing, or as an accumulator during computation.
The MicroVAX has sixteen 32-bit general registers available for use with the
native instruction set. Twelve of these registers are for general purposes. The
rest of these registers have special purposes. One of these special purpose registers is designated as the program counter and contains the address of the
next instruction to be executed. The other three special purpose registers are
designated for use with procedure call instructions. They are the stack
pointer, argument pointer, and frame pointer.
The MicroPDP-ll/23 uses one set of eight 16cbit general registers. Six of
these are general purpose registers and the remaining two are special purpose
registers. The special purpose registers are the program counter and the stack
pointer. The MicroPDP-ll/83 and MicroPDP-ll/73 use two sets of eight 16bit general registers. Each set has the six general purpose registers, a program
counter, and a stack pointer.
A stack is an array of consecutively addressed data items that are referenced
on a last-in, first-out basis using a register. Data items are added to and
removed from the low address end of the stack. A stack grows toward lower
addresses as items are added and shrinks toward higher addresses as items are
removed.
A stack can be created anywhere in the user's program address space. Any
register can be used to point to the current item on the stack. The operating
system, however, automatically reserves portions of each process address
space for stack data structures. User software references its stack data structure, called the user stack, through a general register designated as the stack
pointer. When the user runs a program image, the operating system automatically provides the address of the area designated for the user stack.

Micro VAX Registers
The sixteen 32-bit general registers in the MicroVAX (shown in Figure 6-5)
are labeled RO through R15 (in decimal). Registers can be used for temporary
data storage, or as accumulators, base registers, or index registers. A base register contains the address of the base of a software data structure such as a
table, and an index register contains a logical instruction into a data structure.

6-13
31

R1
R2
R3
R4
R5
R6
R7
RS
R9

• temporary storage locations
• accumulators
• pointers
• index registers

R1D
R11

R12
R13
R14
R15

R12
A,gumentPointe,(AP)
R13 f--'-'F:;!,a:::m:::'e"'"PO"-in'-'te:::',"-(F"-P"-)"-'---1
R14 f -___S_ta_ck_p_O_in_te_'.:...(S_P)'--_--i
R15~_P_'O~g_ffi_m_C_Ou_n_te_'.:...(P_C.:...)~

Figure 6-5· Micro VAX Registers
Some registers have special significance, depending on the instruction being
executed. Registers RI2 through RI5 have special significance for many
instructions and subsequently have special labels. These registers are
described below.

• Program counter (PC or R15) contains the address of the next byte to be
processed in the instruction stream.

• Stack pointer (Sp or R14) contains the address of the top of a stack maintained for subroutine and procedure calls.

• Frame pointer (FP or R13) contains the address of the base of a software
data structure stored in the stack.

• Argument pointer (AP or R12) contains the address of the base of a software data structure called the argument list .

• Micro VAX Program Counter
A MicroVAX native-mode instruction has a variable-length format and instructions are byte-aligned. A variable-length format not only makes code more
compact but it also can easily extend the instruction set. The opcode for the
operation is either one or two bytes long and is followed by zero to six operand
specifiers, depending on the instruction. An operand specifier can be one or
several bytes long, depending on the addressing mode. Figure 6-6 illustrates
the representation of an instruction as a string of bytes. Just before the processor begins to execute an instruction, the program counter contains the address
of the first byte of the next instruction. The way in which the program counter is updated is totally transparent to the programmer.

6-14· Architecture Summary
MOVE LONG INSTRUCTION
AUTODECREMENT MODE, MOVL-(R3),R4
MACHINE CODE: (ASSUMED STARTING LOCATION 00003000)

..~""" ~ -oeco",ro,~, w~~,~
00003001

-AUTO DECREMENT MODE, REGISTER R3

00003002

-REGISTER MODE, REGISTER R4

------------------------------BEFORE INSTRUCTION EXECUTION
SOURCE OPERAND

GENERAL REGISTER
R3 I 00001018 I-STARTING
LOCATION

='"" ; \
00001015

00001016

00001017

R4 I 00000000 I-REG, CONTENT

----------------1------------GENERAL REGISTER
AFTER INSTRUCTION EXECUTION
R3

00001014

I- LOCATION

DECREMENTED
ADDRESS

R4 I CE543210 l_cosrg~~6EOF
OPERAND

Figure 6-6· Micro VAX Instruction Representation
• Micro VAX Stack Pointer, Argument Pointer, and Frame Pointer
The stack pointer is a register specifically designated for use with stack structures. The stack pointer can place items on, or remove items from, the stack.
The argument pointer is used to pass the address of the argument list to a
called procedure, and the frame pointer is used to keep track of the nested call
instructions.
An argument list is a formal data structure containing the arguments required
by the procedure being called. Arguments can be actual values, addresses of
data structures, or addresses of other procedures.
The call instructions always keep track of nested calls with the frame pointer
register. The frame pointer contains the address on the stack of the items
pushed on the stack during the procedure call. The set of items pushed on the
stack during a procedure call is known as a call frame or stack frame.

6-15

• Micro VAX Processor Status Longword
A processor register in the MicroVAX called the processor status longword
(PSL) determines the execution state of the processor at any time. The loworder 16 bits of the processor status longword constitute the processor status
word available to the user process. The high-order 16 bits provide privileged
control of the system. The fields can be grouped together by function to control the operating mode of the current instruction, and the interrupt processing. Figure 6-7 shows the processor status longword.
31

15
PROCESSOR STATUS WORD

IIITTI

INTERRUPT PRIORITY LEVEL
PREVIOUS ACCESS MODE
CURRENT ACCESS MODE
EXECUTING ON THE INTERRUPT STACK
INSTRUCTION FIRST PART DONE
TRACE PENDING

Figure 6-7 • Processor Status Longword
MicroPDP·ll Registers
The MicroPDP-11 registers can be used as operands for arithmetic and logical
operations or for addressing in memory. Register operations are internal to
the processor and do not require bus cycles (except for instruction fetch). All
memory and peripheral device data transfers require bus cycles and longer execution time. Thus general purpose registers used for processor operations
result in faster execution times.
D

15
RD

GENERAL PURPOSE

PROC. STACK POINTER

PROGRAM COUNTER

PSW

I PROCESSOR STATUS I

I
D

Figure 6-8 • MicroPDP-ll Registers
The program counter (PC or R7) contains the address of the next instruction
to be executed. Normally, the PC is used only for addressing and not for arithmetic or logical operations.

6-16 • Architecture Summary

When an interrupt or trap occurs, the processor status word (PSw) and the
program counter are saved on the processor stack. The stack pointer (SP or
R6) contains the address of the top of this stack in memory_ The PSW and PC
contain all the information needed for the processor to resume execution
where it left off. The last-in, first-out stack allows orderly processing of interrupts and traps even when the processor is already processing.
Processor Status Word
The processor status word (PSw) is a special processor register found in the
MicroVAX and MicroPDP-ll that is used to check a program's status and to
control synchronous error conditions. The processor status word, shown in Figure 6-9, contains two sets of bit fields-condition codes and trap enable flags.

15
NOT USED

FLOATING UNDERFLOW EXCEPTION ENABLE
INTEGER OVERFLOW TRAP ENABLE

J J

TRACE FAULT ENABLE --;;;-:=========~~
NEGATIVE CONDITION CODE

CODE~~~~===========~=~_J

ZERO CONDITION
OVERFLOW
CONDITION CODE
CARRY (BORROW) CONDITION CODE

Figure 6-9' Processor Status Word
The condition codes indicate the outcome of a particular logical or arithmetic
operation. The branch-on-condition instructions can be used to transfer control to a code sequence that handles the condition.
There are two kinds of exceptions that concern the user process-trace faults
and arithmetic exceptions. The trace fault is used to debug programs or evaluate performance. Arithmetic exceptions include
• Integer or floating-point overflow, in which the result was too large to be
stored in the given format.
• Integer or floating-point divide-by-zero, in which the divisor supplied was
zero.
• Floating-point underflow, in which the result was too small to be
expressed in the given format.
When an exception occurs, the processor immediately saves the current state
of execution and traps to the operating system. The operating system automatically searches fora procedure that wants to handle the exception.

6-17

• Addressing Modes
The processor's addressing modes allow almost any operand to be stored in a
register or in memory, or as an immediate constant. Table 6-2 summarizes the
addressing modes.

Table 6-2 • Addressing Modes
Address Mode

MicroVAX

MicroPDP-ll

X plus indexed
variation!

X plus indexed
Autoincrement
variation!
(General purpose register contains
address of data. After access, GPR is
incremented to point to next address
of data.)

Autoincrement-deferred

X plus indexed
variation!

Autodecrement

X plus indexed
variation!

x
x

Autodecrement -deferred
Displacement
(MicroPDP-11 Index)

X plus indexed
variation!

Displacement-deferred
(MicroPDP-ll Index-deferred)

X plus indexed
variation!

Second register (multiplied by data size) is added to address.

Micro VAX Addressing Modes
There are seven basic MicroVAX addressing modes that use the general registers to identify the operand location. They include

• Register mode (mode OJ-the register contains the operand.
• Register-deferred mode (mode I}-the register contains the address of the
operand.

6-18' Architecture Summary

• Autodecrement mode (mode 2)-the contents of the register are first decremented by the size of the operand and then used as the address of the operand_ The size of the operand (in bytes), given by the data type of the
instruction operand, depends on the instruction. For example, the clear
word instruction uses a size of two, because there are two bytes per word.

• Autoincrementmode (mode 3)-the contents of the register are used as the
address of the operand, and then incremented by the size of the operand.
If the program counter is the specified register, the mode is called immediate mode.

• Autoincrement-deferred mode (mode 4)-the contents of the register are
used as the address of a location in memory containing the address of the
operand and then are incremented by four (the size of the address). If the
program counter is the specified register, the mode is called absolute
mode.

• Displacement mode (mode 5)-the value stored in the register is used as a
base address. A byte, word, or longword signed constant is added to the
base address, and the resulting sum is the effective address of the operand.

• Displacement-deferred mode (mode 6)-the value stored in the register is
used as the base address of a data structure. A byte, word, or longword
signed constant is added to the base address, and the resulting sum is the
address of the location that contains the actual address of the operand.
The autoincrement and autodecrement modes enable automatic stepping
through tables. The displacement mode enables the generation of offsets into
a table, with a choice of either short or long displacements. The deferred
modes enable the user to maintain tables of operand addresses instead of the
operands themselves. The indexed-addressing modes allow indexing into
tables with a step size automatically determined by the operand. All except
register mode can be modified by indexed addressing.
The MicroVAX processor also provides literal mode, in which an unsigned
six-bit field in the instruction is interpreted as an integer or floating-point constant.
The MicroVAX processor's addressing modes allow considerable flexibility in
the arrangement and processing of data structures. A data structure's design
does not have to be tied to its processing method to be efficient. The variety
of addressing modes enables the assembly language programmer to write, and
high-level language compilers to produce, very compact code. For example, literal mode is a very efficient way to specify small constants.

6-19

MicroPDP-ll Addressing Modes
There are eight basic PDP-ll addressing modes that use the general registers
to identify the operand location_

• Register mode (mode OJ-contains the operand in the register.
• Register-de/erred mode (mode I)-contains the address of the operand in
the register.

• Autoincrement mode (mode 2)-interprets the contents of the register as
the address of the operand in memory and, in addition, increments the contents of the register by 2 (word instructions) or by 1 (byte instructions)
after the operand is accessed in memory. This leaves the register pointing
to the next consecutive word or byte and makes stepping through a list of
operands easier. Because both R6 (stack pointer) and R7 (program counter) normally contain addresses, they are always autoincremented by 2.

• Autoincrement-de/erred mode (mode 3)-uses the contents of the register
as a pointer to the address of the operand. The pointer in the register is
then incremented by 2 after the address is located. Where mode 2 steps
through a list of sequential operands, mode 3 steps through a list of sequential addresses that in turn point to operands stored anywhere in memory.

• Autodecrement mode (mode 4)-decrements the contents of the register
by 2 (word instructions) or by 1 (byte instruction) before using the register
as the address of an operand in memory. Where mode 2 steps through a list
of operands at ascending addresses, mode 4 does the same by descending
addresses.

• Autodecrement-de/erred mode (mode 5)-interprets the contents of the register as the address of a word in memory, which in turn points to the operand. The register is decremented by 2 before accessing the address in
memory. Where mode 3 steps through a list of addresses in ascending memory order, mode 5 steps through the list in descending memory order.

• Index mode (mode 6)-adds the contents of the word immediately following the instruction to the contents of the register, and uses the resulting
sum as the address of an operand in memory. This allows you to specify the
starting address of a list independently of the offset of an entry in the list.
By changing the starting address but not the index, you can move the fifteenth entry in list A to the fifteenth entry in list B. By changing the index
but not the starting address, you can move from the fifteenth entry in list
A to the twentieth entry in list A. The starting address can be specified in
the register and the offset in the word following the instruction, or vice
versa.

6-20 • Architecture Summary

• Index-deferred mode (mode 7)-adds the word follo~i~ the instruction to
the register in the same way as mode 6, but the resulting sum is used as the
address of a word in memory that in turn points to the operand. Where
mode 6 accesses operands stored in a list or table, mode 7 uses addresses
stored in a list or table to access operands stored anywhere in memory.
Modes 2, 3, 6, and 7 can be particularly useful in conjunction with the program counter. The resulting addressing will be independent of where in memory the instruction is executed. Each time the processor implicitly uses the
program counter to tetch a word from memory, the program counter is automatically incremented by 2 after the fetch is completed.
PC immediate mode is a special case of mode 2, using the program counter
(R7) as the register. It accesses die word immediately following the instruction and is a filst way to read a constant operand.
PC absolute mode is a special case of mode 3, where an absolute address (Le.,
constant regardless of where in memory 'the instruction is executed) is stored
in the word immediately following the instruction. This absolute address is
used as a pointer to the operand.
PC relative mode is a special case of mode 6, using the program counter (R 7) as
the register. The updated contents of the program counter (instruction
address + 4) are added to the contents of the word immediately following the
instruction (the offset) and the sum is used as Ii pointer to the operand in memory. The offset and the position of the operand relative to the instruction are
independent of where they are located in memory, so PC relative mode is helpful in writing position-independent code.
PC relative-deferred mode is a special case of mode 7, using the program counter as the register. The word following the instruction (the offset) is added to
the updated program counter (instruction address + 4), and the resulting
sum is used as a pointer to a location which in turn contains the address of the
operand.

• Exceptions and Interrupts
While running one process, the processor executes instructions and controls
data flow to and from peripherals and main memory. To share processor, memory; and peripheral resources among many processes, the processor provides
two arbitration mechanisms called exceptions and interrupts.· Exceptions are
events that occur synchronously with respect to instruction execution; interrupts are external events that occur asynchronously.

6-21

The flow of execution can change at any time. The processor distinguishes
between changes in flow that are local to a process and those that are of systemwide context and independent of any particular process. Process-local
changes occur as the result of a user software error or when user software calls
operating-system services. Process-local changes in program flow are handled
through the processor's exception-detecting mechanism and the operating system's exception dispatcher.
Systemwide changes in flow generally occur as the result of interrupts from
devices or interrupts generated by the operating-system software. Interrupts
are handled by the processor's interrupt-detection mechanism and the operating system's interrupt-service routines (systemwide changes in flow may also
occur as the result of severe hardware errors; these are handled either as special exceptions or high-priority interrupts).
Systemwide changes in flow generally take priority over process-local changes
in flow. The processor uses a priority system for servicing interrupts. To arbitrate between all possible interrupts, each kind of interrupt is assigned a priority, and the processor responds to the highest-priority pending interrupt. For
example, interrupts from realtime I/O devices would take precedence over
interrupts from mass-storage devices, terminals, lineprinters, and other less
time-critical devices.
The processor services interrupts between instructions or at well-defined
points during the execution of long iterative instructions. When the processor
acknowledges an interrupt, it switches rapidly to a special systemwide context
so that the operating system can service the interrupt. Systemwide changes in
the flow of execution are handled in a way that makes them totally transparent
to individual processes.
Exception and Interrupt Vectors
The processor can automatically initiate changes in the normal flow of program execution. The processor recognizes two kinds of events that cause it to
invoke conditional software-exceptions and interrupts. Some exceptions,
such as arithmetic traps, affect an individual process only. Others affect the
system as a whole, such as a machine check. Interrupts include both device
interrupts, such as those signaling I/O completion, and software-requested
interrupts, such as those signaling the need for a context-switch operation.

The processor knows which software to invoke when an exception or interrupt occurs because it references specific locations, called vectors, to obtain
the starting address of the exception or interrupt dispatcher. Each vector tells
the processor how to service the event.

6-22 • Architecture Summary

Processor-priority Levels
To arbitrate between interrupt requests that can occur simultaneously, the
MicroVAX processor recognizes 32 processor-priority levels. The highest 16
processor-priority levels are reserved for interrupts generated by hardware,
and the lowest 16 processor-priority levels are reserved for interrupts
requested by software.
The MicroPDP-ll processors recognize eight processor-priority levels. The
highest four processor-priority levels are reserved for interrupts generated by
hardware, and the lowest four levels are reserved for interrupts requested by
software.
Context Switching
In the multiprogramming environment, several individual streams of code can
be ready to execute at the same time. Instead of allowing each stream to execute one at a time, the operating system can intervene and switch between the
streams of code that are ready to execute. The stream of code the processor is
executing at anyone time is determined by its hardware context.

The hardware context contains the information that is loaded in the processor's registers that identify where the stream of instructions and data are
located, which instruction to execute next, and what the processor is doing
during execution.
The process is the stream of instructions and data defined by the hardware
context. Each process has a unique identification in the system. The operating
system switches between processes by requesting the processor to save one process hardware context and load another.

• Processor Operating Modes
In a high-performance, multiprogramming system, the processor must provide the basis for protection and sharing among the processes competing for
the system's resources. The basis for protection in the system is the processor's operating mode. The operating mode in which the processor executes
determines
• Instruction-execution privileges-which instructions the processor will
execute.
• Memory-access privileges-which locations in memory the current instruction can access.
At anyone time, the processor is either executing code in the context of a particular process, or it is executing code in the systemwide interrupt-service context.

6-23

Kernel mode allows execution of all instructions_ In a multiprogramming environment, the most privileged functions of the operating system-physical I/O
operations, resource management, and job scheduling-are implemented in
code that runs in kernel mode_ The access-control provisions of memory management protect these elements from tampering by programs running in less
privileged modes_
Executive mode allows Record Management Services (RMS) and many of the
operating system's programmed service procedures to execute_
User mode prohibits the execution of instructions, such as halt and reset, that
would allow one program in a multiprogramming environment to harm the system as a whole_ Each user's virtual-address space permits writing only into its
own areas in memory_
Supervisor mode has the same level of privilege as user mode and can be useful
for programs being shared among users but still requiring protection_
Table 6-3 shows both the MicroVAX and MicroPDP-ll processor operating
modes_

Table 6-3 • Processor Operating Modes
Operating Mode

MicroVAX

MicroPDP-ll
X

Kernel

Executive

Supervisor

User

Micro VAX Operating Modes
In the MicroVAX context of a process, the processor recognizes four operating modes-kernel, executive, supervisor, and user_ Kernel is the most privileged mode, and user, the least privileged_ When in interrupt-service context,
the processor recognizes only kernel mode_
The processor spends most of its time executing in user mode_ When user software needs the services of the operating system-whether for acquisition of a
resource, for I/O processing, or for information-the processor executes those
services in the same operating mode or in one of the more privileged operating
modes_

6-24' Architecture Summary

To execute code in one of the more privileged modes, the system manager
must grant access and the operating system controls the operation. The memory protection that the privileged mode gives is enforced by the processor. In
general, code executing in one mode can protect itself and any portion of its
data structures from read and/or write accesses by code executing in any less
privileged mode. This memory-protection mechanism provides the basis for
data structure integrity.

MicroPDP·ll Operating Modes
In the MicroPDP-ll context of a process, the processor recognizes three
access modes-kernel, user, and supervisor.

6-25

• Data Types
The data type of an instruction operand determines the number of bits of storage to be treated as a unit and what the interpretation of that unit is. Each
supermicrosystem's instruction set operates on integer, floating-point, and
character-string data types. For each of these data types, the selection of an
operation immediately tells the processor the size of the data and its interpretation.
The MicroVAX instruction set can also manipulate variable-length bit fields
where the user defines the size of the field and its relative position. There are
several variations of these primary data types. Table 6-4 provides a summary
of the data types available.
Integer data is stored as binary values in either byte or word formats on a
MicroPDP-ll, and in byte, word, longword, quadword, or octaword formats
on a MicroVAX. A byte is 8 bits, a word is 2 bytes, a longword is 4 bytes, a
quadword is 8 bytes, and an octaword is 16 bytes. The supermicrosystem
interprets an integer as either a signed value or an unsigned value. The sign in
signed values is determined by the high-order hit.
Floating-point values are stored using a signed exponent and a binary, normalized fraction. Floating-point data types can represent positive and negative
numbers with a much greater absolute value than integer data (as large as 1.7
x 1,038), or with a fractional value (as small as 0.29 x 10- 38 ). PDP-ll-based
systems use F_ floating-point and D_ floating-point data types. The
MicroPDP-ll/83 supports F_ and D_ floating-point in hardware and in
microcode. The MicroPDP-ll/73 supports F_ and D_ floating-point in
microcode only. MicroVAX II uses F_ floating-point, D_ floating-point,
and G_ floating-point data types in hardware and supports the IL- floating-point data type in software. MicroVAX I is available with a combination of
D_ and F_ floating-point in hardware, or F_ and G_ floating-point in
hardware.
• Single-precision F_ floating-point data is 4 bytes long with an 8-bit
excess 128 exponent. The effective 24-hit fraction yields approximately
seven decimal digits of precision.
• Double-precision D_ floating-point data is 8 bytes long with an 8-bit
excess 128 exponent. The effective 56-bit fraction yields approximately 16
decimal digits of precision.
• G_ floating-point data is 8 bytes long with an ll-bit excess 1,024 exponent. The effective 53-bit fraction yields approximately 15 decimal digits
of precision.

6-26 • Architecture Summary

• fL floating"point data is 16 bytes long with a 15-bit excess 16,384 exponent. The effective 1l3-bit fraction yields approximately 33 decimal digits
of precisiOn.
<

Table 6·4'* nata Type Representation
nata Type

Mic:roVAX

Mic:ropnp,ll

Integer (byte)

8 bits

- 128 to + 127 signed

oto 255 unsigned

oto 255 unsigried

16 bits

- 32768 to + 32767
signed.

- 32768 to + 32767
signed

oto 65535 unsigned

Integer (word)

Integer Oongword)

32 bits
- 2 31 to + 2'1 - 1
signed

oto 2
Integer (quadword)

32 -

1 unsigned

64 bits'
_26' to +26'_1
signed

oto 2
F _ floating point

D_ floating point

G_ floating point

64 -

1 unsigned

4 bytes

7 decimal digits of
precision

8 bytes

16 decimal digits of
precision

16 decimal digits of
precision'

8 bytes
15 decimal digits of
precision

fL floating point

16 bytes
33 decimal digits of
precision

Character string

oto 65535 bytes

One character per byte One character per byte

6-27

Table 6-4 • Data Type Representation (Cont.)
Data Type

MicroVAX

MicroPDP·ll

ot031 bytes

Decimal string

One digit per byte
Bit field

Ot032bits
Dependent on
interpretation

Queue

:2: 2 longwords per
queue entry

Floating-point instructions are standard in the hardware of the MicroVAX I,
MicroVAX II, and the MicroPDP-ll/83. They are standard in microcode on
the MicroPDP-ll/73. Optional floating-point units, FPFll and KEFll-AA,
are available for the MicroPDP-11/23. These units implement 46 microcoded
instructions that perform arithmetic, logical, and conversion operations, and
operate six to ten times faster than equivalent software routines. For more
information on the FPFll and the KEFll-AA, refer to Chapter 2-System
Hardware.
Character data are strings of bytes containing any binary data such as ASCII
codes. Various standards, the most common of which is ASCII, assign an interpretation to some or all of the 256 different codes that can be represented by
this data type.
The first character in the string is stored in the first byte, the second character is stored in the second byte, and so on in ascending order. An 8-bit character is stored at any addressable byte in memory or in the low-order byte of a
general register.
A character-string is a sequence of up to 65,535 bytes in memory which can
be located in two consecutive registers or two consecutive words in memory.
The first word is the length of the character string (unsigned integer format),
and the second word is the address of the most significant character (MSC).
Subsequent characters through the least significant character (LSC) are stored
in ascending memory locations.
Several kinds of decimal-string data formats are used in business applications
where their correspondence to COBOL data types, keypunch codes, or printable characters is used. Decimal-string data formats are only available on the
MicroPDP-ll systems. All represent numbers consisting of 0 to 31 decimal
digits, with an implied decimal point to the right of the least significant digit
(LSD). All are stored in memory as contiguous bytes.

6-28· Architecture Summary

There are separate .instructions for packed-decimal string operations and
zoned-numeric string operations, and for the decimal conversions between the
two.

The address of any data item is the address of the first byte in which the item
resides. All integer, floating-point, and character-string data can be stored
starting at any address in memory. A bit field, however, does not necessarily
start at a byte boundary in memory. A bit field is simply a set of contiguous
bits between 0 and 32 bits in length. The starting bit location is identified
relative to a given byte address or register. The instruction set can interpret a
bit field as a signed or unsigned integer.

The MicroVAX processor also provides for two types of queue data. These
consist of circular double-linked lists. A queue entry is specified' by its
address. Each queue entry is linked via a pair of longwords. The first longword is the forward link; it specifies the location of the succeeding entry. The
second longword is the backward link; it specifies the location of the preceding entry. Two queue tpes are differentiated according to the nature of the
links-absolute and self-relative. An absolute link contains the absolute
address of the entry that it points to. A self-relative link contains a displacement from the address of the queue entry. Also, the instructions for use on a
self-relative queue are interlocked_

• Instruction Sets
An instruction consists of an operation code (opcode) and zero or more operands that are described by a data type and addressing mode. The supermicrosystem instruction sets are based on over 100 different kinds of
operations, each addressable in several ways.
To choose the appropriate instruction, it is necessary only to become familiar
with the operations, data types, and addressing modes. For example, the ADD
operation can be applied to any of several sizes of integer or floating-point
operands, and each operand can be addressed directly in a register, directly in
memory, or indirectly through pointers stored in registers or memory locations.
Micro VAX Instruction Set
The MicroVAX instruction set is a subset of the VAX .instruction set. The
remainder are emulated in software. It executes a large set of variable-length
instructions, recognizes a variety of data types, and uses 32-bit general registers. The opcodes can be grouped into classes based on their function and use.

6-29

Instructions used to manipulate the MicroVAX data types include
• Integer and logical instructions.
• Floating-point instructions.
• Character-string instructions.
• Bit-field instructions.
• Queue instructions.
• Address-manipulation instructions.
• General-register manipulation instructions.
Instructions that provide basic program flow and enable the user to call procedures are
• Branch, jump, and case instructions.
• Subroutine call instructions.
• Procedure call instructions.
• Additional miscellaneous instructions.
The section called "Instruction Set Summary" lists these basic instruction
operations.

MicroPDP-ll Instruction Set
The MicroPDP-ll also executes a large set of variable-length instructions, recognizes a variety of data types, and uses eight 16-bit registers. The following
are the groupings of instructions:
• Load, store, and move instructions copy data between registers, memory,
and I/O devices.
• Arithmetic instructions perform operations that interpret the numeric
data, such as add, multiply, and negate.
• Shift and rotate instructions manipulate data within its original location.
• Data conversion instructions translate one data type to another.
• Logical instructions perform operations that manipulate bits and compare
operands.

6-30· ArchitectureSummary

• Program control instructions redirect the flow of execution.
• Miscellaneous instructions include all of the remaining instructions.
Most instructions, other than floating-point and string-data instructions, use
one of three basic formats-single operand, double operand, and branch. The
single operand for instructions such as CLR (clear) and NEG (negate) is specified by the destination-address field, and the result is left in the same location.
Instructions such as ADD and SUBtract use two operands specified by the
source address and the destination address as input. These instructions leave
the result at the destination address.
A user program can test the outcome of an arithmetic or logical operation. The
processor provides a set of condition codes and branch instructions for this
purpose. The condition codes indicate whether the previous arithmetic or logical operation produced a negative or zero result or whether there was a carry,
borrow, or overflow. There is a variety of branch-on-condition instructionsthose for overflow and carry or borrow, and those for signed and unsigned
relational tests.

6-31

Table 6-5 • Instruction Set Summary
Instruction

MicroVAX

MicroPDP-ll

ABSD

Take absolute value of
D_ floating

ABSF

Take absolute value of
F_floating

ACBB

Add, compare, and branch to
byte (H)

ACBD

Add, compare, and branch to
D_ floating (F, ES)

ACBF

Add, compare, and branch to
F _ floating (F, EH)

ACBG

Add, compare, and branch to
G_ floating (F, EH)

ACBH

Add, compare, and branch to
l L floating (ES)

ACBL

Add, compare, and branch to
longword (H)

ACBW

Add, compare, and branch to
word (H)

ADAWI

Add aligned word interlocked
(H)

ADC

Add carry bit to word

ADCB

Add carry bit to byte

ADD

Add

ADDB2

Add byte 2-operand (H)

ADDB3

Add byte 3-operand (H)

ADDD

Add D_ floating

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AA CPU.

6-32' Architecture Summary

Table 6-S • Instruction Set Summary (Cont.)
Instruction

MicroVAX

ADDD2

Add D.... floating 2-operand
(p, ES)

ADDD3

Add D_ floating 3-operand
(P,ES)

MicroPDP-ll

Add F_ floating

ADDF
ADDF2

Add F_ floating 2-operand
(F, EH)

ADDF3

Add F_ floating 3-operand
(F, EH)

ADDG2

Add G_ floating 2-operand
(F, EH)

ADDG3

Add G_ floating 3-operand
(P,EH)

ADDH2

Add H.... floating 2-operand
(ES)

ADDH3

Add IL floating 3-operand
(ES)

ADDL2

Add longword 2-operand (H)

ADDU

Add longword 3-operand (H)

ADDN(I)

Add numeric decimal
strings

ADDP(I)

Add packed decimal
strings

ADDP4

Add packed decimal4-operand
(A, ES)

ADDP6

Add packed decimal6-operand
(A, ES)

ADDW2

Add word 2-operand (H)

H = Instruction implemented in hardware by the MicroVAX II 78032 'CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hatdware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardWare assist, by
the MicroVAX I KD32-AA CPU.

6-33

Table 6-5 • Instruction Set Summary (Cont.)
MicroPDP-ll

Instruction

MicroVAX

ADDW3

Add word 3-operand (H)

ADWC

Add with carry (H)

AOBLEQ

Add one and branch less than or equal (H)

AOBLSS

Add one and branch less than
(H)

ASH

Arithmetic shift register

ASHC

Arithmetic shift two combined registers

ASHL

Arithmetic shift longword (H)

ASHN(I)
ASHP

Arithmetic shift numeric
decimal string
Arithmetic shift and round
packed decimal string (A, ES)
Arithmetic shift packed
decimal string

ASHP(I)
ASHQ

Arithmetic shift quadword (H)

ASL

Arithmetic shift word left

ASLB

Arithmetic shift byte left

ASR

Arithmetic shift word
right

ASRB

Arithmetic shift byte
right

Branch on bit

BBC

Branch on bit clear (H)

6-34 • Architecture Summary

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

BBCC

Branch on bit clear and clear
(H)

BBCCI

Branch on bit clear and clear
interlocked (H)

BBCS

Branch on bit clear and set (H)

MicroPDP-ll

BBS

Branch on bit set (H)

BBSC

Branch on bit set and clear (H)

BBSS

Branch on bit set and set (H)

BBSSI

Branch on bit set and set interlocked (H)

BCC

Branch if carry bit is clear (H)

Branch if carry bit is clear

BCS

Branch if carry bit is set (H)

Branch if carry bit is set
Branch if equal to zero

BEQ
BEQL

Branch if equal (H)

BEQLU

Branch if equal unsigned (H)
Branch if greater than or
equal to zero

BGE
BGEQ

Branch if greater than or equal
to (H)

BGEQU

Branch if greater than or equal
to unsigned (H)
Branch if greater than
zero

BGT
BGTR

Branch if greater than (H)

BGTRU

Branch if greater than unsigned (H)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAXII 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AA CPU.

6-35

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

MicroPDP-ll

BHI

Branch if higher

BHIS

Branch if higher or same

BIC

Bit clear word

BICB

Bit clear byte

BICB2

Bit clear byte 2-operand (H)

BICB3

Bit clear byte 3-operand (H)

BICL2

Bit clear longword 2-operand
(H)

BICL3

Bit clear longword 3-operand
(H)

BICPSW

Bit clear processor status word
(H)

BICW2

Bit clear word 2-operand (H)

BICW3

Bit clear word 3-operand (H)
Bit set word

BIS
BISB

Bit set byte

BISB2

Bit set byte 2-operand (H)

BISB3

Bit set byte 3-operand (H)

BISF2

Bit set F_ floating 2-operand

BISG2

Bit set G_ floating 2-operand

BISL2

Bit set longword 2-operand (H)

BISL3

Bit set longword 3-operand (H)

BISPWS

Bit set processor status word
(H)

BISW2

Bit set word 2-operand (H)

6-36· Architecture Summary

Table 6·5 • Instruction Set Summary (Cant.)
Instruction

MicroVAX

BISW3

Bit set word 3-operand (H)

MicroPDP·ll

Bit test word

BIT
BITB

Bit test byte (H)

BITL

Bit test longword (H)

BITW

Bjt test word (H)

BLBC

Branch on low bit (H)

BLBS

Branch on low bit set (H)

Bit test byte

Branch if less than or
equal to zero

BLE
BLEQ

Branch if less than or equal to
(H)

BLEQU

Branch if less than or equal
unsigned (H)
Branch if lower

Bill

Branch if lower or same

BillS
BLSS

Branch if less than (H)

BLSSU

Branch if less than unsigned

BLT

Branch if less than zero

BMI

Branch if minus

BNE

Branch if not equal to
zero

BNEQ

Branch if not equal (H)

BNEQU

Branch if not equal unsigned
(H)

BPL

Branch if plus

6-37

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

MicroPDP-ll

BPT

Breakpoint fault (H)

Breakpoint trap

BR
BRB

Branch with byte displacement

Branch (unconditional)
(H)

BRW

Branch with word displacement
(H)

BSBB

Branch to subroutine with byte
displacement (H)

BSBW

Branch to subroutine with word displacement (H)

BUGL

VMS bugcheck

BUGW

VMS bugcheck

BVC

Branch if overflow bit clear (H) Branch if overflow bit
clear

BVS

Branch if overflow bit set (H)

CALLG

Call procedure with general
argument list (H)

CALLS

Call procedure with stack argument list (H)

CASEB

Case on byte (H)

CASEL

Case on longword (H)

CASEW

Case on word (H)

Branch if overflow bit set

CCC

Clear all condition codes

CFCC

Copy floating condition
codes

CHME

Change mode to executive (H)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.

F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.

ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AA CPU.

6-38· Architecture Summary

Table 6·5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

CHMK

Change mode to kernel (H)

CHMS

Change mode to supervisor (H)

CHMU

Change mode to user (H)

MicroPDP·ll

CLC

Clear carry condition
code

CLN

Clear negative condition
code

CLR

Clear word
Clear byte (H)

Clear byte

CLRD

Clear D_ floating (ES)

Clear D_ floating

CLRF

Clear F_ floating (EH)

Clear F _ floating

CLRG

Clear G_ floating (EH)

CLRH

Clear ~ floating

CLRB

CLRL

Clear longword (H)

CLRO

Clear octaword

CLRQ

Clear quadword (H)

CLRW

Clear word (H)

CLV

Clear overflow condition
code

CLZ

Clear zero condition code

CMP
CMPB

Compare word
Compare byte (H)

CMPC(I)
CMPC3

Compare byte
Compare character
strings

Compare characters 3-operand
(A)

6-39

Table 6·.5 • Instruction Set Summary (Cont.)
Instruction

CMPC5

MicroVAX

MicroPDP.l1

Compare characters 5·operand
(A)

CMPD

Compare D_ floating (F)

Compare D_ floating

CMPF

Compare F_ floating (F)

Compare F_ floating

CMPG

Compare G_ floating (F)

CMPH

Compare R.- floating

CMPL

Compare longword (H)

CMPN(I)

Compare numeric decimal
strings

CMPP(I)

Compare packed decimal
strings

CMPP3

Compare packed decimal3-oper- and (A)

CMPP4

Compare packed decimal4-oper- and (A)

CMPV

Compare field (H)

CMPW

Compare word (H)

CMPZV

Compare zero-extended field
(H)

COM

Take one's complement of
word

COMB

Take one's complement of
byte

CRC
CSM

Calculate cyclic redundancy
check (A)
Call supervisor mode

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point

chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AACPU.

6-40 • Architecture Summary

Table ~·5" Instruction Set SUDimary (Cont.)
Instruction

CVTBD

Convert byte to D_ floating
(F)

CVTBF

Convert byte to F_ floating (F) -

CVTBG

Convert byte to G_ floating
(F)

CVTBH

Convert byte to IL floating

CVTBL

Convert byte to longword (H)

CVTBW

Convert byte to word (H)

CVTDB

Convert D_ floating to byte
(F,ES)

CVTDF

Convert D_ floating to
F_ floating (F, ES)

CVTDH

Convert D_ floating to
IL floating. (ES)

CVmL

Convert D_ floating to long- word(F, ES)

CVTDW

Convert D_ floating to word
(F, ES)

CVTFB

Convert F_ floating to byte
(F,EH)

CVTFD

Convert F_ floating to
D_ floating (F, ES)

CVTFG

Convert. F_ floating to
G_ floating (F, EH)

CVTFH

Convert F_ floating to
IL floating (ES)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point

chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software. .
.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I :im32-AA CPU.

6-41

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

CVTFL

Convert F _ floating to longword (F, EH)

CVTFW

Convert F _ floating to word

CVTGB

Convert G_ floating to byte
(F, EH)

CVTGF

Convert G_ floating to
F_ floating (F, EH)

MicroPDP-ll

(F, EH)

CVTGH

Convert G_ floating to

IL- floating (ES)

CVTGL

Convert G_ floating to long- word (F, EH)

CVTGW

Convert G_ floating to word
(F, EH)

CVTHB

Convert IL- floating to byte
(ES)

CVTHD

Convert IL- floating to
D_ floating (ES)

CVTHF

Convert IL- floating to
F_ floating (ES)

CVTHG

Convert IL- floating to
G_ floating (ES)

CVTHL

Convert H_ floating to long- word (ES)

CVTHW

Convert IL- floating to word
(ES)

CVTLB

Convert longword to byte (H)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point

6-42 • Architecture Summary

Table 6·; • Instruction Set Summary (Cont~)
Instruction

MiaoVAX

CVTLD

Convert longwold to D_ float- ing(F, ES)

CVTLF

Convert longword to F_ float- ing(F, EH)

CVTLG

Convert longwordto G_ float- ing(F, EH)
.

CVTLH

Convert longword to I L float- ing (ES)

CVTLN

Convert long integer to
numeric decimal
Convert longword to packed dec- Long integer to packed
imal (A, ES)
decimal

CVTLP
CVTLW

MiaoPDP·ll

Convert longword to word (H)

CVTNL

Convert numeric decimal
to long integer

CVTNP

Convert numeric decimal
to packed decimal
Convert packed decimal to lon- Convert packed decimal
gword (A, ES)
to long integer

CVTPL
CVTPN.
CVTPS

Convert packed decimal
to numeric decimal
Convert packed decimal to load- ing separate (A, ES)

CVTPT

Convert packed decimal to trail- ing (A, ES)
.

CVTRDL

Convert rounded D_ floating
to longword (F, ES)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAX II 78032CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AA CPU.

6-43

Table 6·,5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

CVTRFL

Convert rounded F_ floating
to longword (F, EH)

CVTRGL

Convert rounded G_ floating
to longword (F, EH)

CVTRHL

Convert rounded IL floating
to longword (ES)

CVTSP

Convert leading separate to
packed decimal (A, ES)

CVTTP

Convert trailing to packed decimal (A, ES)

CVTWB

Convert word to byte (H)

CVTWD

Convert word to D_ floating
(F,ES)

CVTWF

Convert word to F_ floating
(F,EH)

CVTWG

Convert word to G_ floating
(EH)

CVTWH

Convert word to IL floating
(ES)

CVTWL

Convert word to longword (H)

DEC

MicroPDP·ll

Decrement word

DECB

Decrement byte (H)

DECL

Decrement longword (H)

DECW

Decrement word (H)

DIV

Decrement byte

Divide

DIVB2

Divide byte 2-operand (H)

DIVB3

Divide byte 3-operand (H)

6-44 • Architecture Summary

Table 6·5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

MicroPDP·ll
Divide D_ floating

DIVD
DIVD2

Divide D_ floating 2-operand
(F, ES)

DIVD3

Divide D_ floating 3-operand
(F, ES)
Divide F_ floating

DIVF
DIVF2

Divide F_ floating 2-operand
(F,EH)

DIVF3

Divide F_ floating 3-operand
(EH)

DIVG2

Divide G_ floating 2-operand
(F, EH)

DIVG3

Divide G_ floating 3·operand
(EH)

DIVH2

Divide IL- floating 2-operand
(ES)

DIVH3

Divide H_ floating 3-operand
(ES)

DIVL2

Divide longword 2-operand (H)

DIVL3

Divide longword 3·operand (H)

DIVP

Divide packed decimal strings
(A, ES)

DIVP(I)

Divide packed decimal
strings

DIVW2

Divide word 2-operand (H)

DIVW3

Divide word 3-operand (H)

6-45

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

EDITPC

Edit packed decimal to character string (A, ES)

EDIV

Extended divide (H)

EMODD

Extended modulus D_ floating (F, ES)

EMODF

Extended modulus F_ floating (F, EH)

EMODG

Extended modulus G_ floating (F,EH)

EMODH

Extended modulus lL floating (ES)

EMT

MicroPDP-ll

Emulator trap

EMUL

Extended multiply (H)

ESCD

EscapeD

ESCE

EscapeE

ESCF

EscapeF

EXTV

Extract field (H)

EXTZV

Extract zero-extended field (H)

FFC

Find first clear (H)

FFS

Find first set (H)

HALT

Halt (H)

Halt

Increment byte (H)

Increment byte

INC
INCB

Increment word

INCL

Increment longword (H)

INCW

Increment word (H)

INDEX

Computer index (H)

6-46 • Architecture Summary

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

INSQHI

Insert entry in queue at head
interlocked (H)

INSQTI

Insert entry in queue at tail
interlocked (H)

INSQUE

Insert entry in queue (H)

INSV

Insert field (H)

lOT

MicroPDP-ll

Input/output trap

JMP

Jump (H)

JSB

Jump to subroutine (H)

Jump

JSR

Jump to subroutine

LDCDF

Load and convert
D_ floating to F_ floating

LDCFD

Load and convert
F_ floating to D_ floating

LDCID

Load and convert integer
to D_ floating

LDCIF

Load and convert integer
to F_ floating

LDCLD

Load and convert long
integer to D_ floating

LDCLF

Load and convert long
integer to F_ floating

LDD

Load D_ floating

LDEXP

Load exponent

LDF

Load F_ floating

6-47

Table 6-.5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

LDPCTX

Load process context (H)

WCC

Locate character (A, EH)

MicroPDP·ll

WCC(I)

Locate character

L2D

Load two string descriptors

L3D

Load three string descriptors

MARK

Facilitates stack cleanup

MATC(I)

Match character string

MATCHC

Match character string (A, ES)

MCOMB

Move complemented byte (H)

MCOML

Move complemented longword
(H)

MCOMW

Move complemented word (H)

MFPD

Move from previous data
space

MFPI

Move from previous
instruction space

MFPR

Move from processor register
(H)

MFPS

Move from processor
status word

MFPT

Move from processor type

MNEGB

Move negated byte (H)

MNEGD

Move negated D_ floating
(F, ES)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point

6·48 • Architecture Summary

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

MNEGF

Move negated F _ floating
(F, EH)

MNEGG

Move negated G_ floating
(F, EH)

MNEGH

Move negated ~ floating
(ES)

MNEGL

Move negated longword (H)

MNEGW

Move negated word (H)

MicroPDP-ll

MODD

Multiply and separate
integer and D_ floating

MODF

Multiply and separate
integer and F _ floating
Move word

MOV
MOVAB

Move address of byte (H)

MOVAD

Move address of D_ floating
(ES)

MOVAF

Move address of F _ floating
(EH)

MOVAG

Move address of G_ floating
(EH)

MOVAH

Move address of ~ floating
(ES)

MOVAL

Move address of longword (H)

MOVAO

Move address of octaword (ES)

MOVAQ

Move address of quadword

MOVAW

Move address of word (H)

MOVB

Move byte (H)

Move byte

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.

A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AACPU.

6-49

Table 6-' • Instruction Set Summary (Cont.)
Instruction

MicroVAX

MOVC(I)

Move character string

MOVC3

Move character 3-operand (H)

MOVC5

Move character 5-operand (H)

MOVD

Move D_ floating (F, ES)

MOVF

Move F_ floating (F, EH)

MOVG

Move G_ floating (F, EH)

MOVH

Move 1-L- floating (ES)

MOVL

Move longword (H)

MOVO

Move octaword (ES)

MOVP

Move packed decimal (A, ES)

MOVPSL

Move from processor status
longword (H)

MOVQ

Move quadword (H)

MOVRC(I)
MOVTC

MicroPDP-ll

Move reverse-justified
character string
Move translated character
string.(A, ES)

MOVTC(I)

Move translated character string

MOVTUC

Move translated until character
(A, ES)

MOVW

Move word (H)

MOVZBL

Move zero-extended byte to
longword (H)

MOVZBW

Move zero-extended byte to
word (H)

6-50· Architecture Summary

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

MOVZWL

Move zer-extended word to
longword (H)

MicroPDP-ll

MTPD

Move to previous data
space

MTPI

Move to previous instructionspace

MTPR

Move to processor register (H)

MTPS

Move to processor status
word
Multiply

MUL
MULB2

Multiply byte 2-operand (H)

MULB3

Multiply byte 3-operand (H)
Multiply D_ floating

MULD
MULD2

Multiple D_floating 2-operand (F, ES)

MULD3

Multiple D_ floating 3-operand (F, ES)
Multily F_ floating

MULF
MULF2

Multiply F_ floating 2-operand (F, EH)

MULF3

Multiply F_floating 3-operand(F, EH)

MULG2

Multiply G_ floating 2-operand(F, EH)

MULG3

Multiply G_ floating 3-operand(F, EH)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAXII 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AA CPU.

6-51

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

MULH2

Multiple IL- floating 2-operand (ES)

MULH3

Multiply IL- floating 3-operand (ES)

MULL2

Multiply longword 2-operand

MicroPDP-l1

(H)

MULL3

Multiply longword 3-operand

MULP

Multiply packed decimal strings
(A, ES)

(H)

MULP(I)

Multiply packed decimal
strings

MULW2

Multiply word 2-operand (H)

MULW3

Multiply word 3-operand (H)

NEG

Negate (take 2's complement) of word

NEGB

Negate (take 2's complement) of byte

NEGD

Negate D_ floating
Negate F_ floating

NEGF
NOP

No operation (H)

POLYD

Evaluate polynomial D_ floating (F, ES)

POLYF

Evaluate polynomial F_ floating (F, EH)

POLYG

Evaluate polynomial G_ floating (F, EH)

No operation

6-52· Architecture Summary

Table 6-5· Instruction Set Summary (Cont.)
Instruction

. MicroVAX

POLYH

Evaluate polynomiallL floating (ES)

POPR

Pop registers from stack (H)

PROBER

Probe read access (H)

PROBEW

Probe write (H)

PUSHAB

Push address of byte (H)

PUSHAD

Push address of D_ floating
(ES)

PUSHAF

Push address of F_ floating
(EH)

PUSHAG

Push address of G_ floating
(EH)

PUSHAH

Push address of IL floating
(ES)

PUSHAL

Push address of longword (H)

MicroPDP-ll

PU~HAO

Push address of octaword (ES)

PUSHAQ

Push address of quadword (H)

PUSHAW

Push address of word (H)

PUSHL

Push longword on stack (H)

PUSHR

Push registers on stack (H)

REI

Return from exception or interrupt (H)

REMQHI

Remove entry from queue at
head interlocked (H)

REMQTI

Remove entry from queue at tail interlocked (H)

H = Instruction implemented inhardwl!re by the MicroVA:l!,: II 78032 CPU chip.
F= Instruction implel;Ilented in hardware by the MicroVAX II 78132 Floating Point
.
.
chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implementedin hardware by the MicroVAX I KD32_AA CPU.
ES = Instruction implemented in software, or in softwl!re with a hardware assist, by
the MlcroVAX I KD32-AA CPU.
-

6-53

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

REMQUE

Remove entry from queue (H)
Reset bus

RESET
RET

MicroPDP-ll

Return from procedure (H)

ROL

Rotate register word left

ROLB

Rotate register byte left

ROR

Rotate register word right

RORB

Rotate register word right

ROTL

Rotate longword (H)

RSB

Return from subroutine (H)

RTI

Return from interrupts

RTS

Return from subroutine

RTT

Return from interrupts

SBC

Subtract carry bit from
word

SBCB

Subtract carry bit from
byte

SBWC

Subtract with carry (H)

SCANC

Scan characters (A, EH)

SCANC(I)

Scan character string

SCC

Set all condition code bits

SEC

Set carry condition code

SEN

Set negative condition
code

SETD

Set D_ floating mode

SETF

Set F_ floating mode

H = Instruction implemented in hardware by the MicroVAX U 78032 CPU chip.
F = Instl'QCtion implemented in hardware by the MicroVAX U 78132 Floating Point
chip.
A = Instl'QCtion implementedin microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instl'QCtion implemented in hardware by the MicroVAX I KD32-AA CPU.
ES =.I~truction implemented in software, or in software with a hardware assist, by
the MicroVAXI KD32-AACPU.

6-54 • Architecture Summary

Table 6-5 • Instruction Set Summary (Cont;)
Instruction

MicroVAX

MicroPDP-ll

SETI

Set floating for integer
mode

SETL

Set floating for long integermode

SEV

Set overflow condition
code
Set zero condition code

SEZ
SKPC

Skip character (A, EH)

SKPC(I)

Skip character string

SOBGEQ

Subtract one and branch greater than or equal to (H)

SOBGTR

Subtract one and branch greater than (H)

SPANC
SPANC(I)

Span characters (A, EH)
Span character string

STCDF

Store and convert
D_ floating to F_ floating

STcm

Store and convert
D_ floating to integer

STCDL

Store and convert
D_ floating to long integer

STCFD

Store and convert
F_ floating to D_ floating

STCFl

Store and convert
F_ floating to integer

6-55

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

STeFL

MicroPDP-ll

Store and convert
F_ floating to long integer

STD

Store D_ floating

STEXP
STF

Store exponent
Store F_ floating

STFPS

Store floating-point program status word

STST

Store floating-point status

SUB

Subtract word

SUBB2

Subtract byte 2-operand (H)

SUBB3

Subtract byte 3-operand (H)
Subtract D_ floating

SUBD
SUBD2

Subtract D_ floating 2-operand(F,ES)

SUBD3

Subtract D_ floating 3-operand(F, ES)
Subtract F_ floating

SUBF
SUBF2

Subtract F_ floating 2-operand (F, EH)

SUBF3

Subtract F_ floating 3-operand (F, EH)

SUBG2

Subtract G_ floating 2-operand(F,EH)

SUBG3

Subtract G_ floating 3-operand(F,EH)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32.AA CPU.
ES = Instruction implemented in software, or in software with a hardware assist, by
the MicroVAXI KD32-AACPU~

6-56 • Architecture Summary

Table 6·'- Instruction Set Summary (Cont.)
Instruction

Mic:roVAX

SUBH2

Subtract IL- floating 2-operand (ES)

SUBH3

SubtractIL-floating 3-operand (ES)

SUBL2

Subtract longword 2-operand
(H)

SUBL3

Subtract longword 3-operand
(H)

Mic:roPDP.ll

SUBN(I)

Subtract numeric decimal
strings

SUBP(I)

Subtract packed decimal
strings

SUBP4

Subtract packed 4-operand

(A, ES)
SUBP6

Subtract packed 6-operand

(A, ES)
SUBW2

Subtract word 2-operand (H)

SUBW3

Subtract word 3-operand (H)

SVPCTX

Save process context (H)
Swap bytes in word

SWAB
SXT

Sign extend

TRAP

Trap

TST

Test word

TSTB

Test byte (H)

Test byte

TSTD

Test D_ floating (F, ES)

Test D_ floating

TSTF

Test F_ floating (F, EH)

Test F_ floating

H = Instruction implemented in hatdware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MictoVAXII 78132 Floating Point
chip.
A = Instruction implemented in microcode by the MicroVAX II 78032 CPU chip. This
.
instruction is emulated by system software.
EH = Instruction implemented in hardware by the MicroVAX I KD32-AA CPU.
ES =. Instruction implemented in software, or in software with a hardware assist, by
the MicroVAX I KD32-AA CPU.

6-57

Table 6-5 • Instruction Set Summary (Cont.)
Instruction

MicroVAX

TSTG

Test G_ floating (F, EH)

TSTH

Test IL- floating (ES)

TSTSET

MicroPDP-ll

Test word, set low bit

TSTL

Test longword

TSTW

Test word (H)

WAIT

Wait for interrupt

WRTLCK

Read/lock destination,
write/unlock RO

XFC

Extended function call (H)

XOR

Exclusive OR word

XORB2

Exclusive OR byte 2-operand
(H)

XORB3

Exclusive OR byte 3-operand
(H)

XORL2

Exclusive OR longword 2-operand (H)

XORL3

Exclusive OR longword 3-operand (H)

XORW2

Exclusive OR word 2-operand
(H)

XORW3

Exclusive OR word 3-operand
(H)

H = Instruction implemented in hardware by the MicroVAX II 78032 CPU chip.
F = Instruction implemented in hardware by the MicroVAX II 78132 Floating Point
chip.

6-58· ArchitectureSummary

• Additional Documentation
VAX Architecture Handbook
PDP-ll Architecture Handbook
Micro VAX 630 CPU Module User's Guide
Micro VAX! CPU Technical Description
KDJll-A CPU Module User's Guide
KDFll-BA CPUModule User's Guide
DCJll Microprocessor User's Guide

EB-19580-20
EB-23657-18
EK-KA630-UG
EK-KD32A-TD
EK-KDJ1A-UG
EK-KDFEB-UG
EK-DCJ11-UG

• Introduction
The Q-bus is the common communications path for the data, address, and control information that is transferred between the CPU, memory, and device
interfaces. Each of the supermicrocomputers use only the Q-bus for these communications.
The 22-bit Q-bus consists of 42 bidirectional and two unidirectional signal
lines that are built into the backplane assembly. Logic modules are installed in
the backplane and connected to these signal lines with backplane connectors.
The signal lines are defined as follows:
• Sixteen multiplexed data/address lines (BDAL< 15:00».
• Twomultiplexed address/parity lines (BDAL< 17:16».
• Four nonmultiplexed extended address lines (BDAL<21:18».
• Six data transfer control lines (BBS7, BDlN, BDOUT, BRPLY, BSYNC,
BWTBT).
• Six system control lines (BHALT, BREF, BEVNT, BINIT, BDCOK, BPOK).
• Ten interrupt control and direct memory access control lines (BIAKO,
BIAKI, BIRQ4, BIRQ5, BIRQ6, BIRQ7, BDMGO, BDMR, BSACK,
BDMGI).
In addition to the data, address, and control signal lines, a number of power,
ground, and spare lines h~ been defined for the 22-bit Q-bus (hereafter
referred to as the Q22 bus). For a detailed description of these lines, refer to
Table A-I.

• Bus Communications

are

All cOmmunications on the bus
performed asynchronously to allow some
devices to transfer at data rates greater than those of other devices. The bus
operates' with' master and slave relationship . When more than one device
requests the use of the bus, the device with the highest priority gains access.
It becomes the bus master and controls the data transfers until it releases the
bus. In performing the transfers, it addresses another device that is designated as a slaVe. .

AppendixA-2· Q-bus

The current data cycle is overlapped with the arbitration for the next cycle,
enhancing the system performance. The upper eight Kbytes of address space
are reserved for 110 devices. Some of the addresses are fixed within this space,
and others are allowed to float, depending on the system configuration.
The bus transactions consist of initialization, arbitration, data transmission,
and miscellaneous:
.
• The initialization lines of the bus provide the information required to start
the processor after powering up and cause an orderly shutdown of the processor during power failures. In addition, they allow the processor to reset
the 110 subsystem.

• Thearbttrationlines control access to the data transmission portion of the
bus.

• The data transmission lines allow words or bytes to be moved about on the
bus. Transmission of data is always accomplished with one device acting as
master and the other acting as slave. The master controls the direction and
length of transmission.
• The miscel14neous lines provide other functions, including processor controland memory refresh.

Master/Slave Relationship
A master/slavetelationship exists throUghout each bus transaction. At any
time, one device has control of the bus andj~ term~ the bus master, and the
other device is termed the slave. The bus master, which is typically the processor or a direct-memory access (DMA) device, initiates a bus transaction. The
slave device responds by acknowledging the transaction in progress and by
receiving data from, or transmitting data to, the bus master. The bus control
signals transmitted or received by the bus master or the bus slave device must
rompletethe sequence according tobus protocol. .
The processor controls bus arbitration to determfue which de~i~ beComes
bus master at any given time. A typical example of this relationship is the processor, as master, fetching an instruction from memory, which is always a
slave. Another example is a disk-drive device as master ttansfetting data to'
memory as slave. Communications on the bus are interlocked so that, £01' certain control sigrials issued by the ffil!ster device, there must be ~respo~from
the slave in <:>i:lJer to complete the, transfer. Iti$.the mastirlslave'5ig~ protocol tiult prec1ude~ the n~ for .syndll'pnizingClOck ~s. . . .
Since bus-cycle completion by the bus master requires response from the slaVe
device, each bus master includes a time-out error circuit that will abort the
bus cycle if the slave device does not respond to the bus transaction within 10
microseconds.

A-3

Bus Signals and Pin Assignments
The connectors on the backplane assembly and the logic modules have corresponding pin and signal assignments. Table A-I lists the signal and pin designations for the data/address, control, power/ground, and spare lines. All Q22bus signals are asserted low and negated high, except BPOK and BDCOK,
which are asserted high. Most signals are bidirectional, and transactions on
the bus are performed asynchronously so that devices can exchange data at
their own rates and the same interfaces can be used for different devices. The
data and address lines are time-multiplexed.

Table A-I • Bus Signals and Pin Assignments
Data and Address
Signal

Signal

BDALO

AU2

BDALll

BR2

BDALI

AV2

BDALl2

BS2

BDAL2

BE2

BDAL13

BT2

BDAL3

BF2

BDALl4

BU2

BDAL4

BH2

BDALl5

BV2

BDAL5

BJ2

BDALl6

ACI

BDAL6

BL2

BDALl7

AD!

BDAL7

BDALl8

BCI

BDAL8

BM2

BDALl9

BDI

BDAL9

BN2

BDAL20

BEl

BDALlO

BP2

BDAL21

BFI

Data Transfer Control
Signal

Signal

BDOUT

AE2

BSYNC

BRPLY

AF2

BWTBT

AJ2
AK2

BDIN

AH2

BBS7

AP2

Signal

Interrupt Control
Signal
BIRQ7

BPI

BIRQ4

BIRQ6

ABI

BIAKO

AN2

BIRQ5

AAI

BIAKI

AM2

Appendix A-4 • Q-bus

Table A-I -Bus Signals and Pin Assignments (Cont.)
Direct Memory Access Control
Signal

Signal

BDMR

ANI

BDGMO

AS2

BSACK

BN1

BMDGI

AR2

Signal

BHALT

API

BINIT

AT2

BREF

AR1

BDCOK

BA1

BEVNT

BR1

BPOK

BB1

Voltage

+ 5B (battery) .

AS1

-12

BB2

+ 12B (battery)

AS1 (not supplied GND
by Digital)

AC2

+ 12B

BS1

GND

AJ1

+5B

AV1

GND

AMI

AA2

GND

AT!

BA2

GND

BC2

BV1

GND

BJ1

+ 12

AD2

GND

BM1

+ 12

BD2

GND

BTl

Signal

SSparel

AE1

MSpareB

ALl

SSpare3

AH1

MSpareB

BLl

SSpare8

BH1

PSparel

AU1

SSpare2

AFl

ASpare2

BUl

MSpareA

AK1

System Control

Power and Ground
Voltage

Spares
Signal

A-5

• Data Transfer Bus Cycles
Seven types of data transfer operations can occur and are listed in Table A-2.
During the bus cycle, executed by the bus master, 8-bit bytes or 16-bit words
can be written or read. In block mode, multiple words can be transferred to or
from sequential word addresses, starting from a single bus address. The bus
signals used for the data transfer operations are listed in Table A-3.
Table A.2 • Data Transfer Operations
Mnemonic

Description

Bus Master Function

DATI

Data word input

Read

DATO

Data word output

Write

DATOB

Data byte output

Write byte

DATIO

Data word input/output Read-modify-write

DATIOB

Data word input/byte
output

Read-modify-write byte

DATBI

Data block input

Read block

AppendixA-6' Q-bus

Table A-3 • Bus Signals for Data Transfers
Mnemonic

Description

BDAL<21:00> L

22 data/address lines BDAL<15:00> Lareusedfor
word and byte. transfers.

Function

BDAL < 17: 16 > L are used for
extended addressing, memory
parity error (16), and memory
. parity error enable (17) functions.
BDAL<21:18> Lare used for
extended addressing beyond
256 Kbytes.
Indicates bus transaction in progress.

BSYNCL

Bus-cycle control

BDINL

Data-input indicator Indicates bus transaction in progress.

BDINL

Data-input indicator Strobe signal

BRPLYL

Slave's acknowledg- Strobe signal
ment of bus cycle

BWTBTL

Writefbyte control

Control signal

BBS7L

I/O device select

Indicates address is in the I/O
page.

Data transfer bus cycles can be reduced to five basic types- DATI, DATO(B),
DATIO(B), DATBI, and DATBO. These transactions occur between the bus
master and one slave device selected during the addressing portion of the bus
cycle.

Bus-cycle Protocol
Before initiating a bus cycle, the previous bus transaction must have been completed (BSYNC L negated) and the device must become bus master. The bus
cycle can be divided into an addressing portion and a data transfer portion.
During the addressing portion, the bus master outputs the address for the
desired slave device, memory location, or device register. The selected slave
device responds by latching onto the address bits and holding this condition
for the duration of the bus cycle until BSYNC L becomes negated. During.the
data transfer portion, the actual data transfer occurs.

A-7

Device Addressing

The device-addressing portion of a data transfer bus cycle ~mprises an
address setup and deskew time and an address hold and deskew time. During
the address setup and deskew time, the bus master performs the following:
• Asserts BDAL<21:00> L with the desired slave-device address bits.
• Asserts BBS7 L if a device in the I/O page is being addressed_
• Asserts BWTBT L if the cycle is a DATO(B) or DATBO.
During this time, the received address BBS7 Land BWTBT L signals are
asserted at the slave-bus receiver for at least 75 nanoseconds before BSYNC
goes active. Devices in the I/O page ignore the nine high-order address bits
BDAL<21:13> and instead decode BBS7 L along with the 13 low-order
address bits. An active BWTBT L signal during address setup time indicates
that a DATO(B) or DATBO operation will follow, while an inactive BWTBT L
indicates a DATI, DATBI, or DATIO(B) operation will follow.

The address hold and deskew time begins after BSYNC L is asserted. The
slave device uses the active BSYNC L bus receiver output to clock BDAL
address bits, BBS 7 L, and BWTBT L into its internal logic. BDAL< 21 :00 > L,
BBS 7 L, and BWTBT L will remain active for 25 nanoseconds minimum after
BSYNC L bus receiver goes active. BSYNC L remains active for the duration of
the bus cycle. Memory and peripheral devices are addressed similarly except
for the way the slave device responds to BBS7 L Addressed peripheral devices
do not decode address bits on BDAL<21:13> 1. Addressed peripheral
devices may respond to a bus cycle when BBS7 L is asserted (low) during the
addressing portion of the cycle. When asserted, BBS7 L indicates that the
device address resides in the I/O page (the upper 4,000 bytes of address
space). Memory devices generally do not respond to addresses in the 1/0 page;
however, some system applications may permit memory to reside in the I/O
page for use as DMA buffers, read-only memory bootstraps, or diagnostics.
DATI BusCyde
The DATI bus cycle, shown in Figure A-I, is a read operation. During DATI,
data is input to the bus master. Data consists of 16-bit word transfers over the
bus. During the data transfer portion of the DATI bus cycle, the bus master
asserts BDIN Lfor 100 nanoseconds minimum after BSYNC,L is asserted. Figure A-2 shows the DATI bus cycle timing. The slave device responds to.BDIN
L active as follows:

AppendixA-8· Q-bus

• Asserts BRPLY L for 0 nanoseconds minimum (8 microseconds maximum
to avoid bus timeout) after receiving BDIN L for 125 nanoseconds maximum before BDAL bus driver data bits are valid_
• Asserts BDAL< 17:00> Lon the MicroVAX andBDAL<21:00> Lon the
MicroPDP-11 with the addressed data and error information for 0 nanoseconds minimum after receiving BDIN and 125 nanoseconds maximum after
assertion of BRPLY.

When the bus master receives BRPLY L, it does the following:
• Waits at least 200 nanoseconds deskew time and then accepts input data at
BDAL< 17:00> L bus receivers. BDAL< 17:16> L are used for transmitting parity errors to the master.
• Negates BDIN L for 200 nanoseconds minimum to 2 microseconds maximum after BRPLY L goes active.

The slave device responds to BDIN L negation by negating BRPLY Land
removing read data from BDAL bus drivers. BRPLY L must be negated 100
nanoseconds maximum prior to removal of read data. The bus master
responds to the negated BRPLY L by negating BSYNC L.
Conditions for the next BSYNC L assertion are as follows:
• BSYNC L must remain negated for 200 nanoseconds minimum.
• BSYNC L must not become asserted within 300 nanoseconds of 'previous
BRPLY L negation.
NOTE
Continuous assertion of BSYNC L retains control of the bus
by the bus master, and the previously addressed slave device
remains selected. This is done for DATIO(B) bus cycles where
DATO orDATOB follows a DATI without BSYNC L.negation
and a second device addressing operation. Also, a slow slave
device can hold off data transfers to itself by keeping BRPLY
L asserted, which will cause the master to keep BSYNC L
asserted.

A-9
BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
• ASSERT BDAL <21 :00> L WITH
ADDRESS AND
• ASSERT BBS 7 IF THE ADDRESS
IS IN THE 110 PAGE
_
• ASSERT BSYNC L

____

---

- - . DECODE ADDRESS
• STORE "DEVICE SELECTED"
OPERATION

~------

REQUEST DATA
• REMOVE THE ADDRESS FROM
BDAL <21 :00> L AND NEGATE
BBS7L
• ASSERT BDIN L

-------

-INPUT DATA
• PLACE DATA ON BDAL <15:00> L

~-----

TERMINATE INPUT TRANSFER
• ACCEPT DATA AND RESPOND
BY NEGATING BDIN L
-

----.

• ASSERT BRPLY L

OPERATION COMPLETED
• NEGATE BRPLY L

Figure A-J • DATI Bus Cycle

AppendixA-IO· Q-bus

T/ADAl.

~--~~~ ~------~-)------ ~--"-~-~--~)(~----~~~~)----~---

TSYNC

DIN

R APLY

=Jl50nSMIN
T

B87"

TWT~

~~______~

I')

~________~;(~___________________I'_)______~__~______________
TIMING AT MASTER DEVtCE

AITDAL

RSVNC

A DIN

-RPLV

a BS1
,R~

~~__________________~I~~_________________________
TIMING AT $4.AYE DEVtCE

NOTES
1 Timing shown at Master and Slave Device Bus Oriver inputs and Bus Receiver Outputs
2 Signal nameprefixes are defined below
T "" Bus Driver input
R = Bus Receiver Output
3 Bus Driver Output and Bus Receiver input signal names include a "8" prefix
4 Don't care condition

Figure A-2 • DATI Bus-cycle Timing

DATO(B) Bus Cycle
The DATO(B) bus cycle, shown in Figure A-3, is a write operation. Data is
transferred in 16-bit words (DATO) or 8-bit bytes (DATOB) from the bus master to the slave device. The data transfer output can occur after the addressing
portion of a bus cycle when BWTBT L has been asserted by the bus master, or
immediately following an input transfer part of a DATIO(B) bus cycle.

A·ll

The data transfer portion of a DATO(B) bus cycle comprises a data setup and
deskew time and a data hold and deskew time.
During the data setup and deskew time, the bus master outputs the data on
BDAL < 15 :00> L at least 100 nanoseconds after BSYNC L is asserted. If the
transfer is a word transfer, the bus master negates BWTBT L at least 100 nanoseconds after BSYNC L assertion. BWTBT L remains negated for the length of
the bus cycle. If the transfer is a byte transfer, BWTBT L remains asserted. If
the transfer is the output of a DATIOB, BTWBT L becomes asserted and lasts
the duration of the bus cycle.
During a byte transfer, BDAL<OO> L selects the high or low byte. This
occurs while in the addressing portion of the cycle. If asserted, the high byte
BDAL< 15:08> L is selected; otherwise, the low byte BDAL<07:00> Lis
selected. An asserted BDAL16 L at this time will force a parity error to be
written into memory if the memory is a parity-type memory. BDAL17 L is not
used for write operations. The bus master asserts BDOUT L at least 100 nano·
seconds after BDAL and BWTBT L bus drivers are stable. The slave device
responds by asserting BRPLY L within 10 microseconds to avoid bus timeout.
This completes the data setup and deskew time.
During the data hold and deskew time the bus master receives BRPLY Land
negates BDOUT 1. BDOUT L must remain asserted for at least 150 nanoseconds from the receipt of BRPLY L before being negated by the bus master.
BDAL < 17 :00 > L bus drivers remain asserted for at least 100 nanoseconds
after BDOUT L negation. The bus master then negates BDAL inputs.
During this time, the slave device senses BDOUT L negation. The data.are
accepted, and the slave device negates BRPLY 1. The bus master responds by
negating BSYNC 1. However, the processor will not negate BSYNC L for at
least 175 nanoseconds after negating BDOUT 1. This completes the DATO(B)
bus cycle. Before the next cycle, BSYNC L must remain unasserted for at least
200 nanoseconds. Figure A-4 shows DATO(B) bus·cycle timing.

AppendixA-12· Q-bus
BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
• ASSERT BDAL <21 :00> L WITH
ADDRESS AND
• ASSERT BBS71FTHE ADDRESS
IS IN THE 1/0 PAGE
• ASSERT BWTBT L (WRITE
CYCLE)

-------

• ASSERT BSYNC L

. OUTPUT DATA
k'" ...• REMOVE THE ADDRESS FROM
BDAL <21 :00> L AND NEGATE
BBS 7 LAND BWTBT L
• PLACE DATA ON BDAL <15:00> L
• ASSERT BDOUT L

...- ...-

----./

---.. DECODE ADDRESS

• STORE "DEVICE SELECTED"
...- ...- OPERATION

...- ...-

---.. TAKE DATA
• RECEIVE DATA FROM BDAL
LINES
• ASSERT BRPLY L

...-

TERMINATE OUTPUT TRANSFER k'"
• NEGATE BDOUT L (AND BWTBT
L IF A DATOB BUS CYCLE) _
• REMOVE DATA FROM BDAL
__
<15:00>L
___

------

TERMINATE BUS CYCLE
• NEGATE BSYNC L

...... OPERATION COMPLETED
• NEGATE BRPLY L

...-------

Figure A -3 • DATO or DATOB Bus Cycle

A-13

CAL

SYNC

DOUl

APLY

B57

WTBT

t- 'SO"'

l~MIN ~

_MIN

OnsMIN

:¥.r----T-D-AT-A---->r<~_ _~---,-.)-------

lADeR

lDD ",

r ~Xx 1

::1 '1.1,,' ~-

I--

"'",MIN

-----11oons MIN
TIMING AT MASTER DEVICE

~_ _ _R_DA_~_ _ _ _~~-._------'-4)-----~

SYNC

DOUl

APLY

857

25nsMIN

lOOnsMIN

--+

--~---+---.,.'_+,_--------,t:= 25nsMIN
A

150nsMtN--+

WTST

TIMING AT SLAve DEVICE

NOTES

1 Timing shown at Master and Slave Device Bus Driver inputs and Bus Receiver Outputs
2 Signal nameprefixes are defined below
T = Bus Driver input
R = Bus Receiver Output
3 Bus Driver Output and Bus Receiver input signal names include a '8" prefix
4 Don't care condition

Figure A-4 • DATO or DATOB Bus-cycle Timing

DATIO(B) Bus Cycle
The protocol for a DATIO(B) bus cycle is identical to the addressing and data
transfer portions of the DATI and DATO(B) bus cycles; it is illustrated in Figure A-5. After the bus addresses the device, a DATI cycle is performed; however, BSYNC L is not negated. BSYNC L remains active for an output word or
byte transfer DATO(B). The bus master maintains at least 200 nanoseconds
between BRPLY L negation during the DATI cycle and BDOUT L assertion.
The cycle is terminated when the bus master negates BSYNC L, as described
for DATO(B). Figure A-6 shows DATIO(B) bus-cycle timing.

AppendixA-14· Q-bus
BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY' OR DEVICE)

ADDRESS DEVICE MEMORY
• ASSERT BDAL <21:00> L WITH
ADDRESS
• ASSERT BBS71F THE ADDRESS
IS IN THE 1/0 PAGE
• ASSERT BSYNC L

--- ---

----------..
-----_

DECODE ADDRESS
• g~~~T~~ICE SELECTED"

REQUEST DATA
• REMOVE THE ADDRESS FROM
BDAL <21:00> L
• ASSERT BDIN L

INPUTDATA
• PLACE DATA ON BDAL <15:00> L
• ASSERT BRPLY L

TERMINATE INPUT TRANSFER
• ACCEPT DATA AND RESPOND BY
TERMINATING BDIN L
-_

--....

--- --

COMPLETE INPUT TRANSFER
• REMOVE DATA
• NEGATE BRPLY L

OUTPUT DATA
• PLACE OUTPUT DATA ON BDAL
<15:00>L
• (ASSERT BWTBT L IF AN OUTPUT
BYTE TRANSFER)
• ASSERT BOOUT L

---

__ TERMINATE OUTPUT TRANSFER _
.·REMOVE DATA FROM BDAL
UiliES
• NEGATE BDOUT L

-- ------

TERMINATE BUS CYCLE
• NEGATE BSYNC L
(ANDBWTBT L IF IN
A DATIOB BUS CYCLE)

TAKE DATA
• RECEIVE DATA FROM BDAL
LINES
• ASSERT BRPLY L

OPERATION COMPLETED
• NEGATE BRPLY L

Figure A-5 • DATIO or DATIOB Bus Cycle

A-15

TIMING AT MASTER DEVICE

AfT OAl

ROATA

X
t "",M'N

~--------'
R SYNC

R DOur

DIN

T RPLY

BS7

TIMING AT SLAVE DEVICE

NOTES
1. Timing shown at Requesting Device Bus Driver inputs and Bus Receiver Outputs.
2. Signal name prefixes are defined below:
T = Bus Driver Input
R = bus Receiver Output
3. Bus Driver Output and Bus Receiver input signal names include a '8" prefix
4. Don't care condition

Figure A-6 • DATIO or DATIOB Bus-cycle Timing

(4)

Appendix A-16· Q-bus

• Direct Memory Access
The direct memory access (DMA) capability allows direct data transfer
between I/O devices and memory. This is useful when using mass storage
devices such as disk drives that move large blocks of data to and from memory .. A DMA device needs only the starting address in memory, the starting
address in mass storage, the length of the transfer, and whether the operation
is read or write. When this information is available, the DMA device can transfer data directly to or from memory. Because most DMA devices must per.form data transfers in rapid succession or else lose data, they are provided the
highest priority.
DMA transfer is accomplished after the processor (normally bus master) has
passed bus mastership to the highest-priority DMA device that is requesting
the bus. The processor arbitrates all requests and grants the bus to the DMA
device located electrically closest to it. A DMA device remains bus master
indefinitely until it relinquishes its mastership.

The following control signals are used during bus arbitration:
BDMGIL

DMA grant input

BDGMOL

DMA grant output

BDMRL

DMA

BSACK

Bus grant acknowledge

DMA Protocol
A DMA transaction can be divided into three phases:

• Bus mastership acquisition phase.
• Data transfer phase.
• Bus mastership relinquish phase.
During the bus mastership acquisition phase, a DMA device requests the bus
by asserting BDMR L. The processor arbitrates the request and initiates the
transfer of bus mastership by asserting BDMGO· L. The maximum time
between BDMR L and BDMGO L assertion is DMA latency. This time is processor-dependent. BDMGO L/BDMGI L is one signal that is daisychained
through each module in the backplane. It is driven out of the processor on the
BDMGO L pin, enters each module on the BDMGI L pin, and exits on the
BDMGO L pin. This signal passes through the modules in descending order of
priority until it is stopped by the requesting device. The requesting device
blocks the output of BDMGO L and asserts BSACK L. If BDMR L is continuously asserted, the bus will be jammed.

A-17

During the data transfer phase, the DMA device continues asserting BSACK L
The actual data transfer is performed as described earlier_
The DMA device can assert BSYNC L for a data transfer 250 nanoseconds minimum after it receives BDMGI L and its BSYNC L bus receiver becomes
negated_
During the bus mastership relinquish phase, the DMA device relinquishes the
bus by negating BSACK L This occurs after completing (or aborting) the last
data transfer cycle (BRPLY L negated). BSACK L can be negated up to a maximum of 300 nanoseconds before negating BSYNC L. Figure A-7 shows the
DMA protocol and Figure A-8 shows DMA request/grant timing.

NOTE
If multiple data transfers are performed during this phase,
considerations must be given to the use of the bus for other
system functions, such as memory refresh (if required).

AppendixA-18· Q-bus
PROCESSOR
(MEMORY IS SLAVE),

BUS MASTER
(CONTROLLER)

-----

REQUEST BUS
• ASSERT BDMR L

GRANT BUS CONTRO~
• NEAR THE END OF THE
CURRENT BUS CYCLE
(BRPLY L IS NEGATED)
_
ASSERT BDMGO LAND
INHIBIT NEW PROCESSOR
GENERATED BYSNCL FOR
THE DURATION OF THE
DMA OPERATION

w---

_ _ ---.

-..-----

TERMINATE GRANT
SEQUENCE
• NEGATE BDMGO LAND
WAIT FOR DMA OPERATION
TO BE COMPLETED

-------

..-------

RESUME PROCESSOR
OPERATION
• ENABLE PROCESSOR
GENERATED BSYNC L
(PROCESSOR IS BUS
MASTER) OR ISSUE
ANOTHER GRANT IF BDMR
L IS ASSERTED

ACKNOWLEDGE BUS
MASTERSHIP
• RECEIVE BDMG
• WAIT FOR NEGATION OF
BSYNC LAND BRPLY L
• ASSERT BSACK L
• NEGATE BDMR L

EXECUTE A DMA DATA
TRANSFER
• ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS
OF DATA AS DESCRIBED
FOR DATI, OR DATO BUS
CYCLES
• RELEASE THE BUS BY
TERMINATING BSACK L
(NO SOONER THAN
NEGATION OF LAST BRPLY
L) AND BSYNC L

WAIT 4 Jls OR UNTIL
ANOTHER AFO TRANSFER
IS PENDING BEFORE
REQUESTING BUS AGAIN

Figure A-7· DMA Protocol

A-19

SECOND
REQUEST
DMA LATENCY

A DMG

SACK

RIT

SYNC

onsMINi

~ OnsMIN
~ OnsMiN

TDAL
(ALSO BS7,
WTBT, REF)

il00nSMAX

____________________J;(~___AO_O_R___')(========O=M=A======~_,,~________
NOTES
1. Timing shown at Requesting Device Bus Driver inputs and Bus Receiver Outputs
2 Signal name prefixes are defined below
T = Bus Driver Input
R ,= bus Receiver Output
3, Bus Driver Output and Bus Receiver input signal names include a' B" prefix
4. Don't care condition

Figure A-8· DMA Request/Grant Timing

Appendix A-20 • Q-Bus

Block Mode
For increased throughput, block mode can be implemented on a device. In a
block-mode transaction, the starting memory address is asserted, followed by
data for that address and data for consecutive addresses. By eliminating the
assertion of the address for each data word, the transfer rate is almost doubled.

DATBI Bus Cycle
The device-addressing portion of the DATBI bus cycle is the same as previously described for other bus cycles. The bus master gates BDAL < 21:00 >,
BBS7, and the negation of BWTBTonto the bus. Figure A-9 shows the DATBI
bus-cycle timing.
SIGNALS AT BUS MASTEA

Times are mll'~. except where " ... denotes max.

TBS7

AiT DAL

T SYNC

XXXXX

XXXXXX

--~~~~----~~~~~~~~~-----

-+---i 100

T DIN

\ 12 \ 14

A APLY

t5
16

\ 14\

A AEF

•1

address to T SYNC 150ns MIN .

address hold

IOOnx min

T SYNC to T DLN

lOOns min

T DIN to A RPLY

T (drive + T (prop) + T (receive) + T (delay)
+ T (drive) + T (receive)

R RPLY to data

200nx max

R RPLY to T DIN

200nx min

T DIN to R RPLY
T (drive) + (prop) + T (receive) + T (delay)
+ T (drive) + T (prop) + T (receive)

R RPL to data

R RPLY to T DIN

150nsmin

.4 +.6 +.7 + .9

-since, must be > .5 for master
10 have valid data and.9 > .8

Tcell

Onsmin

Figure A-9 • DATBI Bus-cycle Timing

Appendix A -21

The master asserts the first BDIN 100 nanoseconds after BSYNC and asserts
BBS7 a maximum of 50 nanoseconds after asserting BDIN for the first time_
BBS7 is a request to the slave for a block-mode transfer. BBS7 remains
asserted until a maximum of 50 nanoseconds after the assertion of BDIN for
the last time. BBS7 can be gated as soon as the conditions for asserting BDIN
are met.
The slave asserts BRPLYa minimum of 0 nanoseconds (8 milliseconds maximum to avoid bus timeout) after receiving BDIN. It asserts BREF concurrently with BRPLY if it is a block-mode device capable of supporting another
BDIN after the current one. The slave gates BDAL < 15:00> onto the bus a
minimum of 0 nanoseconds after the assertion of BDIN and 125 nanoseconds
maximum after the assertion of BRPLY.
The master receives the stable data from 200 nanoseconds maximum after the
assertion of BRPLY until 20 nanoseconds minimum after the negation of
BDIN. It negates BDIN a minimum of 200 nanoseconds after the assertion of
BRPLY.
The slave negates BRPLY a minimum of 0 nanoseconds after the negation of
BDIN. If BBS7 and BREF are both asserted when BRPLYis negated, the slave
prepares for another BDIN cycle. BBS7 is stable from 125 nanoseconds after
BDIN is asserted until 150 nanoseconds after BRPLY is negated. The master
asserts BDIN a minimum of 150 nanoseconds after BRPLY is negated, and the
cycle is continued as before (BBS7 remains asserted, and the slave responds to
BDIN with BRPLY and BREF). BREF is stable from 75 nanoseconds after
BRPLY is asserted until a minimum of 20 nanoseconds after BDIN is negated.

If BBS7 and BREF are not both asserted when BRPLY is negated, the slave
removes the data from the bus 0 nanoseconds minimum and 100 nanoseconds
maximum after negating BRPLY. The master negates BSYNC a minimum of
250 nanoseconds after the assertion of the last BRPLY and a minimum of 0
nanoseconds after the negation of that BRPLY.

DATBO Bus Cycle
The device-addressing portion of the DATBO bus cycle is the same as
described earlier. The bus master gates BDAL<21:00> ,BBS7, and the assertion of BWTBTonto the bus. Figure A-lO shows the DATBO bus-cycle timing.

AppendixA-22· Q-Bus
SIGNAL AT BUS MASTER

Times are mon. except where ..... denotes max.

~~'--_ __

TBS7

T DAL

DATA

address

DATA

150+100
T SYNC

T DOUT
tl

R RPLY
R REF

address to T SYNC

150nxmin

address hold

lOOns min

data to T DOUT

lOOns min

.4·

T DOUT to R RPLY
T (drive) + T (prop) + T (receive) + T (delay)
+ T (drive) + T (prop) + T (receive)

R RPLY to T DOUT

150nsmin

T DOUT to R RPLY
T (drive) + T (prop) + T (receive) + T (delay)
+ T (drive) + T (prop) + T (receive)

.7
Tcell

R RPLY to T DOUT

lOOns min

.3 +.4 +.5 +.6 +.7

-since.3<.7

Figure A-lO • DATBO Bus-cycle Timing
A mmunum of 100 nanoseconds after BSYNC is asserted, data on
BDAL< 15:00> apd the negated BWTBT are put onto the bus. The master
then asserts BDOUT a minimum of 100 nanoseconds after gating the data.

The slave receives stable data and BWTBT from a' minimum of 25 nanoseconds before the assertion of BDOUT to a minimum of 25 nanoseconds after
the negation of BDOUT. The slave asserts BRPLY a minimum of 0 nanoseconds after receiving BDOUT. It also asserts BREF concurrently with BRPLY if
it is a block-mode device capable of supporting another BDOUT after the current one.

AppendixA-23

The master negates BDOUT 150 nanoseconds minimum after the assertion of
BRPLY_ If BREF was asserted when BDOUTwas negated, and if the master
wants to transmit more data in this block-mode cycle, then the new data is
gated onto the bus 100 nanoseconds minimum after BDOUT is negated. BREF
is stable from 75 nanoseconds maximum after BRPLY is asserted unti120 nanoseconds minimum after BDOUT is negated. The master asserts BDOUT for
100 nanoseconds minimum after gating new data onto the bus and 150 nanoseconds minimum after BRPLY negates. The cycle continues as before.

If BREF was not asserted when BDOUT was negated, or if the bus master does
not want to transmit more data in this cycle, then the master removes data
from the bus a minimum of 100 nanoseconds after negating BDOUT. The
slave negates BRPLYa minimum of 0 nanoseconds after negating BDOUT. The
bus master negates BSYNC a minimum of 175 nanoseconds after negating
BDOUT and a minimum of 0 nanoseconds after the negation of BRPLY.

DMA Guidelines
• Bus masters that do not use block mode are limited to four DATI, four
DATO, or two DATIO transfers per acquisition.
• Block"mode bus masters that do not monitor BDMR are limited to eight
transfers per acquisition.

• If BDMR is not asserted after the seventh transfer, block-mode bus masters that do monitor BDMR can continue making transfers until the bus
slave fails to assert BREF or until they reach the total maximum of 16 transfers. Otherwise, they stop after eight transfers.

• Interrupts
The interrupt capability of the Q22 bus allows any I/O device to temporarily
suspend (interrupt) current program execution and divert processor operation
to service the requesting device. The processor inputs a vector address from
the device to start the service routine (handler). Like the device-register
address, the device vector is set by the hardware at locations within a designated range below location 001000 (octal).
The interrupt vector in the MicroVAX is determined by adding 200 (hex) to
the vector supplied by the device and using this as a longword offset into the
system-control block (SCB). This process yields the starting physical address
of the Q22-bus device interrupt routine.

AppendixA-24' Q-Bus

The interrupt vector in the MicroPDP-ll indicates the first of a pair of
addresses. The content of the first address is read by the processor and is the
starting address of the interrupt handler. The content of the second address is
a new processor status word .. The. new processor status word can raise the
interrupt priority level, thereby preventing lower-level interrupts from breaking into the current interrupt service routine. Control is returned to the interrupted program when the interrupt handler is ended. The original
interrupted program's address and its associated processor status word are
stored on a stack. The original program address and processor status word are
restored by a return-from-interrupt instruction at the end of the handler. The
use of the stack and the Q-bus interrupt scheme can allow interrupts to occur
within nested interrupts, depending on the processor status word.
Interrupts can be caused by Q22-bus options or by the CPA. Interrupts that
originate from within the processor are called traps. Traps are caused by programming errors, hardware errors, special instructions, and maintenance features.
The Q22-bus signals used in interrupt transactions are
BIRQ4

Interrupt request priority level 4

BIRQ5

Interrupt request priority level 5

BIRQ6 L

Interrupt request priority level 6

BIRQ7 L

Interrupt request priority level 7

BIAKIL

Interrupt acknowledge output

BIAKOL

Interrupt acknowledge output

BDAL<21:00> L

Data/address lines

BDINL

Data input strobe

BRPLYL

Device Priority
The MicroPDP-ll on the Q22 bus supports the following two methods of
device priority. MicroVAX systems, however, use distributed arbitration
only.

• Distributed Arbitration-priority levels are implemented on the hardware. When devices of equal priority level request an interrupt, priority is
given to the device electrically closest to the processor .
• Position-Defined Arbitration-priority is determined solely by electrical
position on the bus. The closer a device is to the processor, the higher its
priority is.

AppendixA-25
Interrupt Protocol
The interrupt protocol has three phases:

• The interrupt request phase.
• The interrupt acknowledge and priority arbitration phase.
• The interrupt vector transfer phase.
Figure A-II shows the interrupt request/acknowledge sequence and Figure A12 shows the interrupt protocol timing.
The interrupt request phase begins when a device meets its specific conditions
for interrupt requests, such as when the device is ready , done, or an error has
occurred. The interrupt enable bit in a device status register must be set. The
device then initiates the interrupt by asserting the interrupt request line(s).
BIRQ4 L is the lowest hardware priority level and is asserted for all interrupt
requests. The level at which a device is configured must also be asserted. A
special case exists for level 7 devices which must also assert level 6. This is
described in the following four-level interrupt discussion:
Interrupt Level

Lines Asserted by Device

BIRQ4L

5
6

BIRQ4 L, BIRQ5 L

BIRQ4 L, BIRQ6 L, BIRQ7 L

BIRQ4 L, BIRQ6 L

AppendixA-26· Q-Bus
DEVICE

'--

PROCESSOR
STROBE INTERRUPTS
• ASSERT BDIN L

INITIATE REQUEST
• ASSERT BIRQ L

~~~~~~ ~I~~E~RUPT SENDING"

.---

I
I

~--

IN DEVICE

GRANT'REQUEST
• PAUSE AND ASSERT BIAKO L

------.

-,----

RECEIVE BIAKI L
• RECEIVE BIAKI L AND INHIBIT
BIAKO L
",
• PLACE VECTOR ON BDAL 0-15 L
• ASSERT BRPLY L
• NEGATE BIRQ L

RECEIVE VECTOR & TERMINATE , . REQUEST
'
• INPUT VECTOR ADDRESS
• NEGATE BDIN LAND BIAKO L _

--~

.--

PROCESS THE INTERRUPT
• SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK

-- --

COMPLETE VECTOR TRANSFER
• REMOVE VECTOR FROM BDAL
BUS
• NEGATE BRPLY L

• LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION
• EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE

Figure A-ll • Interrupt Request/Acknowledge Sequence

Appendix A-2 7

--,
T

IRQ

DIN

IAKI

INTERRUPT LATENCY
MINUS SERVICE TIME

J r-

T RPLV
125,..M... )(

DAL

(4)

R SYNC

(UNASSERTEO)

(UNASSERTED)

. .,

t--

VECTOR

1oon.MAX

NOTES
1. Timing shown at Requesting Device Bus Driver inputs and Bus Receiver Outputs.
2. Signal name prefixes are defined below:
T ;;; Bus Driver Input
R '" bus Receiver Output
3. Bus Driver Output and Bus Receiver input signal names include a "B" prefix
4. Don't care condition

Figure A-12 • Interrupt Protocol Timing
The interrupt request line remains asserted until the request is acknowledged_
During the interrupt acknowledge and priority arbitration phase, the processor
will acknowledge interrupts under the following conditions:
• The device interrupt priority is higher than the current interrupt priority
level.
• The processor has completed instrUction execution and no additional bus
cycles are pending.
The processor acknowledges the interrupt request by asserting BDIN Land,
150 nanoseconds minimum later, asserting BIAKO 1. The device electrically
closest to the processor receives the acknowledgment on its BIAKI L bus
receiver.
The two types of arbitration are discussed separately. If the device that
receives the acknowledgment uses the four-level.interrupt scheme, the followingoccurs:

Appendix A-28' Q-Bus

• If not requesting an interrupt, the device asserts BIAKO L, and the
acknowledgment propagates to the next device on the bus.

• If the device is requesting an interrupt, it checks that no higher-level
device is currently requesting an interrupt. This is done by monitoring
higher-level request lines. The following table lists the lines that are monitored by devices at each priority level.

Device Priority Level

Line(s) Monitored

BIRQ5, BIRQ6

5
6

BIRQ6
BIRQ7

7
In addition to asserting levels 7 and 4, level 7 devices must assert level 6. This
is done to simplify the monitoring and arbitration by level 4 and 5 devices. In
this protocol, level 4 and 5 devices need not monitor level 7 since level 7
devices assert level 6. Level 4 and 5 devices will become aware of a level 7
request because they monitor the level 6 request. This protocol has been optimized for level 4, 5, and 6 devices, because level 7 devices seldom are used.

• If no higher-level device is requesting an interrupt, the acknowledgment is
blocked by the device (BIAKO L is not asserted). Arbitration logic within
the device uses the leading edge of BDIN L to clock a flip-flop that blocks
BIAKOL.

• If a higher-level request line is active, the device disqualifies itself and
asserts BIAKO L to propagate the acknowledgment to the next device along
the bus.
Signal timing must be considered when implementing four-level interrupts.
Note Figure A-12.

If a single-level interrupt device receives the acknowledgment, it reacts as follows:

Appendix A-29

• If not requesting an interrupt, the acknowledgment is blocked using the
leading edge of BDIN L, and arbitration is won_ The interrupt vector transfer phase begins_

• If the device was requesting an interrupt, the acknowledgment is blocked
using the leading edge of BDIN L, and arbitration is won. The interrupt
vector transfer phase begins.
The interrupt vector transfer phase is enabled by BDIN Land BIAKI 1. The
device responds by asserting BRPLY L and its BDAL< 15:00> L bus driver
inputs with the vector address bits. The BDAL bus-driver inputs must be stable within 125 nanoseconds maximum after BRPLY L is asserted. The processor then inputs the vector address and negates BDIN Land BIAKO 1. The
device then negates BRPLY Land, 100 nanoseconds maximum later, removes
the vector address bits. The processor then enters the device's service routine.
NOTE
Propagation delay from BIAKI L to BIAKO L must not be
greater than 500 nanoseconds per Q-bus slot. The device
must assert BRPLY L within 10 microseconds maximum after
the processor asserts BIAKI L.
Four-level Interrupt Configurations
High-speed peripheral devices can attain better software performance using
the four-level interrupt scheme. Both position-independent and positiondependent configurations can be used.

The position-independent configuration is shown in Figure A-U. This allows
peripheral devices that use the four-level interrupt scheme to be placed in the
backplane in any order. These devices must send out interrupt requests and
monitor higher-level request lines, as described. The level 4 request is always
asserted by a requesting device regardless of priority. If two or more devices
of equally high priority request an interrupt, the device physically closest to
the processor will win arbitration. To function properly, devices that use the
single-level interrupt scheme must be modified or placed at the end of the bus
for arbitration.

)..

~
~

ff
)..
\..
c

~
.....

~
....

PROCESSOR

BIAK (INTERRUPT ACKNOWLEDGE)

i
~

<§.,

ti·

t·

BIRQ 4 (LEVEL 4 INTERRUPT REQUEST)
BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)
BiRQ 7 (LEVEL 7 INTERRUPT REQUEST)

LEVEL 4
DEVICE

LEVEL 6
DEVICE

LEVEL 5
DEVICE

LEVEL 7
DEVICE

Appendix A-31

The position-dependent configuration, shown in Figure A-14, is simpler to
implement. A constraint is that peripheral devices must be inserted with the
highest-priority device located closest to the processor and the remaining
devices placed in the backplane in decreasing order of priority, with the lowest-priority devices farthest from the processor. With this configuration, each
device has to assert only its own level and level 4. Monitoring higher-level
request lines is unnecessary. Arbitration is achieved through the physical positioning of each device on the bus. Single-level interrupt devices on level 4
should be positioned last on the bus.

:g::..

""'"

~
~

~
.....
-I:.

..,~

PROCESSOR

BIAK (INTERRUPT ACKNOWLEDGE)

LEVEL 7
DEVICE

LEVEL 6
DEVICE

LEVEL 5
DEVICE

LEVEL 4
DEVICE

g:
~

BIRQ 4 (LEVEL 4 INTERRUPT REQUEST)

'1>
~

BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)

BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)

BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)

....

s.,
i:1

~.
~

AppendixA-33

• Control Functions
The following Q22-bus signals provide control functions:
BREFL

Memory refresh also (also block
mode)

BHALTL

Processor halt

BINITL

Initialize

BPOKH

Power OK

BDCOKH

dc power OK

BREF
The BREF signal is used as a control signal issued by memory devices for block
mode transfers.

Halt
Assertion of BHALT L for at least 25 microseconds interrupts the processor,
which stops program execution and forces the processor unconditionally into
console mode.
Initialization
Devices along the bus are initialized when BINIT L is asserted. The processor
asserts BINIT L as a result of executing a powerup or powerdown sequence or
after detection of a G character in console mode (MicroPDP-ll) or an S character (MicroVAX).
Power Status
Power-status protocol is controlled by two signals, BDCOK Hand BPOK H.
These signals are driven by some external device (usually the power supply) .

• BDCOK H-'-When asserted, this signal indicates that dc power has been
stable for at least 3 milliseconds. Once asserted, this line remains asserted
until the power fails. It indicates that only 5 microseconds of dc power
reserve remains .
• BPOK H-When asserted, this signal indicates that there is at least an 8millisecond reserve of dc power and that BDCOK H has been asserted for
at least 70 milliseconds. Once BPOK H has been asserted, it must remain
asserted for at least 3 milliseconds. The negation of this line, the first event
in the powerfail sequence, indicates that power is failing and that only 4
milliseconds of dc power reserve remain.

AppendixA-34· Q-Bus

Powerup/powerdown Protocol
Powerup protocol begins when the power supply applies power with BDCOK
H negated. This forces the processor to asSertBINIT L. When the de voli:ages
are stable, the Power supply orotherexternal device asSerts BDCOK H. BINIT
L is negated as a result of BDCOKH being asserted. The processor continues
to test for BPOK H until it is asserted. The power supply asserts BPOK H 70
milliseconds minimum after BDCOK H is asserted. The processor then performs its powerup sequence. Normal power must be maintained at least 3 mil~
liseconds before a powerdown sequence can begin.
A powerdown sequence begins on.MicroVAX systems when the power supply
negates BPOK H. A powerfail interrupt is initiated if'the current interrupt
priority level is less than 1E (hex).
No later than 3 milliseconds after BPOK H negates, the processor asserts
BINIT L for 8 to 20 microseconds. The power supply must negate BDCOK H
no sooner than 4 milliseconds after the negation of BPOK H. This allows massstorage devices to protect themselves against erasures and erroneous writes
during a powerJailure.

The processor asserts BINIT L again no lilter than 1 microsecond after the
negation of BDCOK H. The dc power must remain stable for a minimum of 5
microseconds after BDCOK H negates. BDCOK H must remain negated for a
.
minimum of 3 milliseconds.

A powerdown sequel)ce begins on the MicroPDP-llwhen the power supply
nc;gateslWOK H. When the current instruction is CQmpleied, the p~esso~
traps' to a powerdown routine at location 24 8 • The end of the routineis ternunated with a HALT instruction to avoid any possible memory corruption as
the dc voltages decay.

When the processor executes the HALT instruction, it tests the BPQK Hsig,
nal. If BPOK H is negated, the processor enters thepowerup sequence. It
clears internal registers, generates BINIT L, and continues to check for the
assertion ofBPOK H. If it is asserted and dc voltages are still stable, the processor will.perform the. rest of·the powerup sequence. Figure A-15 illustrates
powerup/powerdown·timing;

NORMA
POWER

NOTE
Once a power down sequence is started, it must be completed before a power·up sequence is started.

Figure A-15· PowerupJPowerdown Timing

Appendix A -35

• Bus Electrical Characteristics
The electrical specifications for the signals on the Q22 bus are as follows:
Input Logic Levels
TTL logical low:

0.8 Vdc maximum

TTL logical high:

2.0 Vdc minimum

Output Logic Levels
TTL logical low:

0.4 Vdc maximum

TTL logical high:

2.4 Vdc minimum

Load Definition
The ac loads are the maximum capacitance allowed per signal line to ground.
A unit load is defined as 9.35 pF (picofarads) of capacitance. The dc loads are
defined as maximum current allowed with a signal-line driver asserted or unasserted. A unit load is defined as 210 microamperes in the unasserted state.

120-0hmBus
The electrical conductors interconnecting the bus-device slots are treated as
transmission lines. A uniform transmission line, terminated in its characteristic impedance, will propagate an electrical signal without reflections. Since
bus drivers, receivers, and wiring connected to the bus have finite resistance
and nonzero reactance, the transmission line impedance is not uniform and
therefore introduces distortions into pulses propagated along it. Passive components of the bus, such as wiring, cabling, and etched signal conductors, are
designed to have a nominal characteristic impedance of 120 n.
The maximum length of interconnecting cable excluding wiring within the
backplane is limited to 4.88 meters (16 feet).

Bus Drivers
Devices driving the 120-n bus must have open collector outputs and meet the
following specifications:

• dc Specifications
• Output low voltage when sinking 70 milliamps of current: 0.7 V maximum.
• Output high leakage current when connected to 3.8 V dc: 25 microamperes
(even if no power is applied, except for BDCOK Hand BPOK H)

AppendixA-36· Q-Bus

These specifications must be met at worst-case supply voltage, temperature,
and input-signal levels_

• ac Specifications
• Bus-driver output-pin capacitive load: Not to exceed 10 picofarads_
• Propagation delay: Not to exceed 35 nanoseconds.
• Skew (difference in propagation time between slowest and fastest gate):
Not to exceed 25 nanoseconds.
• Rise/Fall Times: Transition time (from 10-90 percent for positive transition, and from 90-10 percent for negative transition) must be no faster
than 10 nanoseconds.
Bus Receivers
Devices that receive signals from the 120-0 022 bus must meet the following
requirements:

• dc Specifications
• Inputlow voltage (maximum): 1.3 V.
• Input high voltage (minimum): 1.7 V_
• Maximum input current when connected to 3.8 Vdc: 80 microamperes
(even if no power is supplied).
These specifications must be met at worst-case supply voltage, temperature,
and output-signal conditions.

• ac Specifications
• Bus-receiver input-pin capacitance load: Not to exceed 10 picofarads.
• Propagation delay: Not to exceed 35 nanoseconds.
• Skew (difference in propagation time between slowest and fastest gate):
Not to exceed 25 nanoseconds.
Bus Termination
The 120-0 bus must be terminated at each end by an appropriate terminator,
as shown in Figure A-16. This is a voltage divider with its Thevenin equivalent equal to 1200 and 3.4 Vdc nominal. The MicroVAX and MicroPDP-ll
processor terminations are provided by the processor and backplane.

AppendixA-37

+5V

1780
1%

3300
2200

1200

BUS LINE
TERMINATION

3830
1%

6800

Figure A-16· Bus Terminations

Each of the bus signals starting with the letter B must see an equivalent network with the following characteristics at each end of the bus:
Input impedance (with respect
to ground)

120 ± 0 + 5%, -15%

Open circuit voltage

3.4 Vdc + 5%

Capacitance load

Not to exceed 30 pF
NOTE

The resistive termination can be provided by the combination of two modules (that is, the processor module supplies
220 0 to ground. This, in parallel with another 220-0 module, provides 120 0). Both ofthese terminators must be physically resident within the backplane.

• Bus Interconnect Wiring
The electrical characteristics of the wiring that connects the slots on the Q22bus backplane must conform to certain requirements. These requirements
ensure the proper operation of the installed modules.
Backplane Wiring
The wiring that connects all device interface slots on the backplane must meet
the following specifications:

• The conductors must be arranged so that each line exhibits a characteristic
impedance of 120 0, measured with respect to the bus common return.

• Crosstalk between any two lines must be .no greater than 5 percent .. Note
that worst-case crosstalk is manifested by simultaneously driving all but
one signal line and measuring the effect on the undriven line.
• The dc resistance of the sigpal path, as measured between the near-end terminator module and the far-end terminator module (including all intervening connectors, cables, backplane wiring, or connector module) must not
exceed20.

• The dc resistance of the common return path, as measured between the
near-end terminator module and the far-end terminator module (including
all intervening connectors, cables, backplane wiring, or connector module)
must not exceed an equivalent of 2 0 per signal path. Thus the dc resistance of the composite-sigpal return path must not exceed 2 0 divided by
40 bus lines (or 50 milliohms). Although this common return path is nomi"
nally at ground potential, the conductance must be part of the bus wiring.
The specified low-impedance return path must be provided by the bus wiring as distinguished from the common system or power ground path.

Intrabackplane Wiring
The wiring that connects the bus connector slots within one contiguous backplane is part of the overall bus transmission line. Because of implementation
constraints, the nominal characteristic impedance of 120 0 may not be achievable. Distribtited wiring capacitance in excess of the amount required to
achieve the nominal 120-0 impedance may not exceed 60 picofarads per signalline.

Power and Ground
Each bus interface slot has connector pins assigned for the following dc voltages. The maximum allowable current per pin is 15 amperes. + 5 Vdc must
be regulated to ± 5 percent with a maximum ripple of 100 mV pp. + 12 Vdc
must be regulated to ± 3 percent with a maximum ripple of 200 mV pp.

• + 5 Vdc-Threepins (45 amperes maximum per bus device slot).

• + 12 Vdc-Two pins (3.0 amperes maximum per bus device slot).
• Ground-Eight pins (shared by power return and signal return).

• Bus-system Configurations
Before configuring any system, three characteristics for each module in the .
system must be known. These characteristics are:

AppendixA-39

• Power consumption- + 5 Vdc and + 12 Vdc current requirements.
• ac bus loading-the amount of capacitance a module presents to a bus signalline. ac loading is expressed in terms of ac loads; one ac load equals 9.35
picofarads of capacitance.
• dc bus loading-the amount of dc leakage current a module presents to a
bus signal when the line is high (undriven). dc loading is expressed in terms
of dc loads; one dc load equals 210 microamperes (nominal).
Power-consumption, ac-loading, and dc-loading specifications for each module are included in the VAX Systems and Options Catalog and the PDP-ll Sys-

tems and Options Catalog.
NOTE
The ac and ddoads and the power consumption of the processor module and backplane must be included in determining
the total loading of a backplane.

Single-backplane Configurations
The following rules apply to the use of single-backplane systems:
• When using the MicroVAX II with 240-U processor termination, or the
MicroVAX I with 220-U processor termination, the bus can accommodate
modules that have up to 20 ac loads total before additional termination is
required. If more than 20 ac loads are included, the other end of the bus
must be terminated with 120 U, and then up to 35 ac loads may be present.
• When using the MicroPDP-ll systems with 120-U processor termination,
up to 35 ac loads can be used without additional termination. If 120-U bus
termination is added, up to 45 ac loads can be configured in the backplane.
• The bus can accommodate modules for up to 20 total dc loads.
• The bus signal lines on the backplane can be up to 35.6 centimeters (14
inches) long.

Appendix A-40' Q'Bus

BACKPLANE WIRE
35.6 CM (14 IN) MAX

1
ONE
UNIT
LOAD

12000R
2200

+
3.4 V

)

ONE
UNIT
LOAD

,
20 de LOADS

PROCESSOR

Figure A -17 • Single-backplane Configuration
Dual-backplane Configurations
The following rules apply to the use of dual backplanes in MicroVAX and
MicroPDP-ll cabinet configurations:
• As illustrated in Figure A-l8, two backplanes may make up the system.
• The signal lines on each backplane can be up to 25.4 centimeters (10
inches) long.
• Each backplane can accommodate modules that have up to a total of 22 ac
loads. Unused ac loads from one backplane may not be added to the other
backplane if the second backplane loading will exceed 22 ac loads. It is
desirable to load backplanes equally, or with the highest ac load in the first
backplane.

Appendix A -41

• dc loading of all modules in both backplanes cannot exceed 20 loads total.
• Both ends of the bus must be terminated with 240 0 on the MicroVAX II,
2200 on the MicroVAX I, and with 1200 on the MicroPDP-l1.
• The cable connecting the two backplanes must be 61 centimeters (2 feet)
or greater in length.
• The cable used must have a characteristic impedance of 120 O.

12000R
2400
+
3.4V

22 AC LOADS MAX

PROCESSOR

CABLE

BACKPLANE WIRE

f - - - - 25 .4 em (10 in) M A X - - - - l

12000R
2400
+
3.4V

22 AC LOADS MAX
TERM

Figure A-18· Dual-backplane Confi?JIration

AppendixA-42· Q-Bus
Power Supply Loading
Total power requirements for each backplane can be determined by obtaining
the total power requirements for each module in the backplane. Obtain separate totals for + 5 Vand + 12 V power. Power requirements for each module
are specified in the VAX Systems and Options Catalog and PDP-II Systems

lmd Options Catalog.
Module Connector Pin Identification
The supermicrosystems use both dual-height and quad-height modules. The
convention used to identify the pin connectors on the modules and backplane
is shown in Figures A-19 and A-20. A dual-height module has two rows of
connector pins, A and B, as shown in Figure A-19. A quad-height module has
four rows labeled A, B, C, and D, which are shown in Figure A-20.

Each row has two sides. The side of the module where the components are
located is designated as Side 1. The opposite, or soldered side, is designated as
Side 2. Each row on each side consists of 18 contacts, for a total of 36 contacts
per row. The contact designations are A through V, excluding G, I, 0, and Q.
The positioning notch between the two rows of pins mates with a protrusion
on the connector block for correct module positioning. Examples of typical
pin identifications on a module are shown in Figures A-19 and A-20.
BE2
MODULE OR
BACKPLANE
ROW IDENTIFIER
(ROW B)

MODULE OR
BACKPLANE SIDE
IDENTIFIER
(SIDE 2-S0LDER SIDE)
CONTACT PIN
IDENTIFIER

(PIN E)

PINAA1

PINAA2

V
ROW A

PINAV,

'-J

'1
PINBAl

SIDE 1
COMPONENT SIDE

SIDE 2
SOLDER SIDE

ROWB

PINBVl

PIN BV2

Figure A-19· Dual-height Module Contact Finger Identification

AppendixA-43
BE2
MODULE OR
BACKPLANE
ROW IDENTIFIER
(ROW B)

-II

MODULE OR
BACKPLANE SIDE
IDENTIFIER
(SIDE 2-S0LDER SIDE)

I
CONTACT PIN
IDENTIFIER

(PINE)

II (PI;;-'
AA2
ROW A
AV2

V
,/
BA2

BAl
ROWB

(

fl (-

1 (I
ROWC
CV2

('
SIDE1
COMPONENT SIDE

DA2

SIDE2
COMPONENT SIDE

ROWD
DV1

""-.J

DV2

Figure A-20· Quad-heightModule Contact Finger Identification

AppendixA-44· Q-Bus

Table A-4 • Bus-pin Identifiers .
Bus Pin

Mnemonics

Description

AAl

BIRQ5L

Interrupt Request Priority level 5

ABI

BIRQ6L

Interrupt Request Priority Level 6

ACI

BDALl6L

Extended-address bit during addressing protocol; memoty-error data line
during data transfer protocol.

ADl

BDALl7L

Extended-address bit during addressing protocol; memory-error logic
enable during data transfer protocol.

AEI

SSPAREI
(Alternate + 5B)

Special Spare-Not assigned or
bused in Digital's cable or backplane
assemblies; available for user connection. Optionally, this pin can be used
for + 5 V battery ( + 5B) backup
power to keep critical circuits alive
during P9Wer failures. A jumper is
required on some bus options to disconnect the + 5B circuit in systems
that use this line as SSPARE1.

AFI

SSPARE2

Special Spare-Not assigned or
bused in Digital's cable or backplane
assemblies; available for user interconnection. In the highest-priority
device slot; the processor can use this
pin for a signal to indicate its RUN
state.

AHI

SSPARE3 (SRUN
simultaneously)

Special Spare-Not assigned or

bused in Digital's cable or backplane
assemblies; available for user interconnection. An alternate SRUN signal
may be connected in the highest-priorityset.

AJI

GND

Ground-System signal ground and
dcreturn.

AKI

MSPAREA

Maintenance Spare-Normally connected together on the backplane at
each option location (not a bused connection).

ALl

MSPAREB

Maintenance Spare-Normally connected together on the backplane at
each option location (not a bused connection).

Appendix A-45

Table A-4 • Bus-pin Identifiers (Cont.)
Bus Pin

Mnemonics

Description

AMI

GND

Ground-System signal ground and
dcreturn.

ANI

BDMRL

Direct Memory Access (DMA)
Request-A device asserts this signal
to request bus mastership. The processor arbitrates bus mastership
between itsdf and all DMA devices
on the bus. If the processor is not bus
master (it has completed a bus cycle
and BSYNC L is not being asserted
by the processor), it grants bus mastership to the requesting device by
asserting BDMGO L. The device
responds by negating BDMR L and
asserting BSACK L.

API

BHALTL

Processor Halt-When BHALT L is
asserted for at least 25 microseconds,
the processor responds by halting normal program execution and entering
console mode.

ARI

BREFL

Memory Refresh-Asserted by a
DMA device. This signal forces all
dynamic MOS memory units requiring bus refresh signals to be activated
for each BSYNC L/BDIN L bus transaction. It is also used as a control signal for block mode.
CAUTION

The user must avoid multiple DMA
data transers (burst or "hog" mode)
that could dday refresh operation if
using DMA refresh. Complete refresh
cycles must occur once every 1.6 milliseconds if required.
ASI

+ 12Bor + 5B

+ 12 Vdc or + 5 V battery backup
power to keep critical circuits alive
during power failures. This signal is
not bused to BSI in all of Digital's
backplanes. A jumper is required on
all bus options to disconnect the
backup circuit from the bus in systems that use this line at the alternate
voltage.

Appendix A-46· Q-Bus

Table A-4 • Bus-pin Identifiers (Cont.)

Bus Pin

Mnemonics

Description

ATl

GND

Ground-System signal ground and
dc return.

AUl

PSPARE1

Spare (not assigned; customer usage
not recommended). Prevents damage
when modules are inserted upside
down.

AV1

+5B

+ 5 V Battery Power-Secondary
+ 5 V power connection. Battery
power can be used with certain
devices.

BAI

BDCOKH

dc Power OK-Power supply-generated signal that is asserted when
there is sufficient dc voltage available
to sustain reliable system operation.

BB1

BPOKH

Power OK-Asserted by the power
supply 70 milliseconds after BDCOK
is negated (when ac power drops
below the value required to sustain
power; approximately 75 percent of
nominal). When negated during processor operation, a powerfail trap
sequence is initiated.

BC1

SSPARE4
Special Spare-Not assigned. Bused
BDAL 18L (22-bit only) in cable and backplane assemblies;
available for user interconnection.

BDl

SSPARE5
Special Spare-Caution-these pins
BDAL 19L (22-bit only) can be used as test points in some
options.

BEl

SSPARE6
BDAL20L

These bused address lines are address
lines <21:18> and are used only
during the address portion of the bus
operation.

BF1

SSPARE7
BDAL21L

These bused address lines are address
lines <21:18> and are only used
during the address portion of the bus
operation.

BHl

SSPARE8

Special Spare-Not assigned or
bused in Digital's cable and backplane assemblies; available for user
interconnection.

Appendix A-47

Table A-4 • Bus-pin Identifiers (Cont.)
Mnemonics

Description

BJI

GND

Ground-System signal ground and
dcretum.

BKI
BLl

MSPAREB
MSPAREB

Maintenance Spare-Normally connected together on the backplane at
each option location (not a bused connection).

BMI

GND

Ground-System signal ground and
dcreturn.

BNl

BSACKL

This signal is asserted by a DMA
device in response to the processor's
BDMGO L signal, indicating that the
DMA device is bus master.

BPI

BIRQ7 L

Interrupt Request Priority Level 7

BRI

BEVNTL

External Event Interrupt RequestWhen asserted, the processor
responds by entering a service routine
via vector address 1008. A typical use
of this signal is a line time-clock interrupt. This signal is not used in the
MicroVAX I processor.

BSI

+ 12B

+ 12 V dc battery-backup power (not
bused to ASI in all of Digital's backplanes). Not supplied by Digital.

BTl

GND

Ground-System signal ground and
dcretum.

BUI

PSPARE2

Power Spare 2-Not assigned a function. Not recommended for use. If a
module is using - 12 V (on pin AB2),
and if the module is accidentally
inserted upside down in the backplane, - 12 Vdc appears on pin BUl.

Bus Pin

Appendix A-48 • Q-Bus

Table A-4 • Bus-pin Identifiers (Cont.)

Bus Pin

Mnemonics

Description

BV1

+ 5 V Power-Normal + 5 Vdc systern power.

AA2

+ 5 V Power-Normal + 5 Vdc systern power.

AB2

+ 12

- 12 V Power- - 12 Vdc (optional)
power for devices requiring this
voltage.
NOTE
Modules that require negative voltages contain an inverter circuit on
each module that generates the
required voltages(s). The - 12 V
power is not required with Digitalsupplied options.

AC2

GND

Ground-System signal ground and
dc return.

AD2

+ 12

+ 12 V Power- + 12 Vdc system
power.

AE2

BDOUTL

Data Output-BDOUT, when
asserted, implies that valid data is
available on BDAL<O:15> Land
that an output transfer, with respect
to the bus-master device, is taking
place. BDOUT L is deskewed with
respect to data on the bus. The slave
device responding to the BDOUT L
signal must assert BRPLY L to complete the transfer.

AF2

BRPLYL

Reply-BRPLY L is asserted in
response to BDIN LOR BDOUT L
and during IAK transactions. It is generated by a slave device to indicate
that it has placed its data on the
BDAL bus or that it has accepted output data from the bus.

Appendix A-49

Table A-4 • Bus-pin Identifiers (Cont.)
Bus Pin

Mnemonics

Description

AF2

BDINL

Data Input-BDIN L is used for two
types of bus operations:
When asserted during BSYNC L
time, BDIN L implies an input transfer with respect to the current bus
master, and requires a response
(BRPLYL).
BDIN L is asserted when the master
device is ready to accept data from a
slave device.

AH2

BDINL

Data Input-BDIN L is used for two
types of bus operations:
When asserted during BSYNC L
time, BDIN L implies an input transfer with respect to the current bus
master and requires a response
(BRPLY L). BDIN L is asserted when
the master device is ready to accept
data from a slave device.

When asserted without BSYNC L it
indicates that an interrupt operation
is occurring. The master device must
deskew input data from BRPLY 1.

AJ2

BSYNCL

Synchronize-BSYNC L is asserted
by the bus-master device to indicate
that it has placed an address on
BDAL < 0: 17 > 1. The transfer is in
process until BSYNC L is negated.

AK2

BWTBTL

Write/Byte-BWTBT L is used in
two ways to control a bus cycle:
It is asserted at the leading edge of
BSYNC L to indicate that an output
sequence is to follow (DATO or
DATOB), rather than an input
sequence.
It is asserted during BDOUT L, in a
DATOB bus cycle, for byte
addressing.

AppendixA-50' Q-Bus

Table A-4 • Bus-pin Identifiers (Cont.)

Bus Pin

Mnemonics

Description

AL2

BIRQ4L

Interrupt Request Priority l.evel4

AM2
AN2

BIAKIL
BIAKOL

Interrupt Acknowledge-In accordance with interrupt protocol, the processor asserts BIAKO L to acknowledge receipt of an interrupt. The bus
. transmits this to BIAKI L of the
device electrically closest to the processor. This device accepts the interrupt acknowledgment under two
conditions:
The device requested the bus by
asserting BIRQXL.
The device has the highest-priority
interrupt request on the bus at that
time_

If these conditions are not met, the
device asserts BIAKO L to the next
device on the bus. This process continues in a daisychain fashion until
the device with the highest interrupt
priority receives the interrupt
acknowledge signal.
AP2

BBS7L

Bank 7 Select-The bus master
asserts this signal to reference the
I/O page (including that portion of
the I/O page reserved for nonexistent
memory). The address in
BDAL<O:12> LwhenBBS7 Lis
asserted is the address within the
I/O page.

Appendix A-51

Table A-4 • Bus-pin Identifiers (Cont.)

Bus Pin

Mnemonics

Description

AR2
AS2

BDMGIL
BDMGOL

Direct Memory Access Grant-The
bus arbitrator asserts this signal to
grant bus mastership to a requesting
device, according to bus mastership
protocoL The signal is passed in a
daisychain from the arbitrator (as
BDMGO L) through the bus to
BDMGI L of the next priority device
(electrically closest device on the
bus). This device accepts the grant
only if it requested to be bus master
(by a BDMR L). If not, the device
passes the grant (asserts BDMGO L)
to the next device on the bus. This
process continues until the requesting
device acknowledges the grant.
CAUTION
DMA device transfers must not inter-

fere with the memory-refresh cycle.
AT2

BINITL

Initialize-This signal is used for system reset. All devices on the bus are
to return to a known, initial state.
That is, registers are reset to 0, and
logic is reset to state O. Exceptions
should be completely documented in
programming and engineering specifications for the device.

AU2
AV2

BDALOL
BDALl L

Data/address Lines-These two lines
are part of the 16-line data/address
bus over which address and data
information are communicated.
Address information is first placed on
the bus by the bus master device.
The same device then either receives
input data from, or outputs data to,
the addressed slave device or memory
over the same bus lines.

BA2

+ 5 V Power-Normal + 5 Vdc systempower.

AppendixA-52' Q-Bus

Table A·4 • Bus-pin Identifiers (Cont.)
Bus Pin.

Mnemonics

Description

BB2

-12

- 12 V Power- - 12 Vde (optional)
power for devices requiring this voltage. Voltages normally not supplied
by Digital.

Be2

GND

Ground-System signal ground and
de return.

BD2

+ 12

+ 12 V Power- + 12 V system
power.

BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

BDAL2L
BDAL3L
BDAL4L
BDAL5L
BDAL6L
BDAL7L
BDAL8L
BDAL9L
BDALlOL
BDALllL
BDALl2L
BDAL13L
BDAL14L
BDAL15L

Data/address Lines-These 14 lines
are part of the 16-line data/address
bus previously described.

• Additional Documentation
VAX Systems and Options Catalog
PDP-ll Systems and Options Catalog

ED-27973-46
ED-27981-41

Before the supermicrosystem arrives, adequate planning and preparation of
the area where the system will be located will simplify the installation and
ensure the reliable operation of the system. The considerations are
• Space to install the system.
• Proper environmental conditions.
• Correct power outlets and adequate power.

• Space
Sufficient space must be provided around the system unit and terminals to
allow access to the unit, and to enable the proper circulation of air through the
unit. The surroundings should be comfortable for the operating personnel,
and the area should be free from traffic and spills. The system unit should be
positioned to allow the operator access to the control panel and flexible-disk
drives located at the front of the unit.
Table B-1 shows the overall dimensions of the system units.
System
The supermicrosystems are available in floorstand, cabinet, pedestal, tabletop, and rackmount versions. The floorstand and pedestal versions are
designed to fit under a standard 30-inch (76.2-centimeter) desk or table. The
floorstand model comes with four casters on the bottom for easy maneuvering
of the system should it be required. The pedestal system unit can easily be
converted to a tabletop version by removing the pedestal mount. The rackmount version is designed to be installed into a 19-inch-wide cabinet such as
the H9642. And the cabinet model stands 42 inches (106 centimeters) high
and should be installed in a computer room that has the proper air conditioning and power.

Appendix B-2· Site ~on antilnstllilation

Table B·l • System~unit Dimensions
DimensiOn F100rstand Pedestal. Tabletop Raclanount Cabinet
Height

245 in
62.2cm

24.5 in
62.2cm

6.0
15.2cm

5.25 in
13.3cm

41.7 in
106.0cm

Width

13.0 in
33.0cm

10.0 in
25.4cm

22.25 in 19.0 in
56.5cm 48.3cm

25.7 in
65.6cm

Depth

27.5 in
69.8cm

285 in
72.4cm

285
72.4cm

255 in
64.8cm

36.0 in
91.4cm

Weight

1331b
60 kg

70lb
32 kg

55lb
25 kg

358-6851b
163 - 311 kg
(dependent on
mass storage
selected)

Console Terminal
The console terminal is usually positioned close to the system operator. The
console terminal keyboard is movable and can be placed in front of the display
or close to the terminal.

Printers
Printers require space for the paper supply and for access to load the paper
into the printer. The space requirements depend on the type of paper used
(stationery or fanfold), and the location of the trays. The printer unit can be
positioned·i1t any location in the area that isconvenient to the operator.

Cables
The power cord and the signal cables that connect the units in a system should
be routed away from where the operator will be or from areas of traffic. No
heavy objects should be placed on the cables and the cables should be long
enough to prevent strain on the cable connectors. Sharp cable angles should
also be avoided.

Appendix B-3

• Environment
All of the supermicrosystems (with the exception of the MicroVAX II and the
MicroPDP-ll/83 systems with RA- series disks which generate more heat and
noise) will operate in most normal working environments that provide comfortable surroundings for the operator. These areas include offices, schools,
hospitals, or manufacturing areas that have controlled environments. There
are, however, certain environmental conditions that may not be suitable for
system operation. Areas that are subject to extreme temperature and humidity changes, areas of high contamination in the air, and areas with electrical
interference conditions are not recommended. In situations such as these,
ruggedized versions of the systems are better suited.

Temperature and Humidity
Table B-2 lists the acceptable temperature ranges and humidity levels for operating each of the supermicrosystems. These conditions are specified for the
operation of the system unit, storage devices, console terminal, and printing
devices that are manufactured by Digital. These conditions may not apply to
devices and equipment supplied by other manufacturers.
Table B-2 • Operating Temperature and Humidity
F100rstand
Temperature Range
Relative Humidity

59-90°F
15 - 32°C
20-80%*

Pedestal

Cabinet

59 -90°F
15 -32°C
20-80%*

20-80%*

* Noncondensing
NOTE
Some Field Service contracts require specific temperature
and humidity limits that may differ from those listed.

Air Contiunination
Dust and dirt particles that are suspended in air can block the air filters and
prevent the proper circulation of air through the system unit and the system
devices. Disk drives and other mechanical devices may also be adversely
affected by dust and dirt. To prevent these conditions, the system area should
be kept reasonably clean by· periodic vacuum cleaning. Where possible, the
area in·whlch·the system is operating should be environmentally separated
from other areas that produce contaminants.

Appendix B-4 • Site Preparation and Installation
Electrical Interference
Digital's supermicrosystems, terminals, and cables are provided with shielding and electrical filters to limit the effects of electrical interference. Electrical interference can be transmitted through power lines or through the air.
High levels of interference from electrical power equipment, x-ray equipment, or radio devices can adversely affect the system operation. If any of
these conditions exist at the operating site, additional filters and shielding
may be necessary for reliable system operation.

Room Lighting
Reduced lighting levels in the area where the videodisplay terminals (VDTs)
are operated can prevent excessive reflection from the display screen. Light
levels can be varied by electrical dimming controls or by shielding the direct
light.

NOTE
Electrical dimming controls are frequendy the cause of electrical noise. Dimming devices that are designed only for computer applications should be used.
Screen filters for the VDTs are available to reduce reflections and to improve
the contrast of the characters on the display.

Shock and Vibration
Digital's supermicrosystems are designed to withstand the normal shock and
vibrations that occur duriDg shipment and under normal operation. If the system will be subjected to excessive shock or vibration conditions, Field Service
should evaluate the location before the system is installed.
Static Electricity
Static electricity, generated in the area in which the system equipment is operating, can result in data loss, program errors, and other system failures. Static
electricity is usually caused by a low humidity level and carpeted floor surfaces. A static charge occurs when people walk on the carpeted surface or
when they move in vinyl- or fabric-covered chairs. The static electricity is discharged when a person comes in contact with the equipment, which is
grounded by the power cord line or other leads.

Static electricity can be reduced by keeping the relative humidity levels at 40
percent or greater, and by using special antistatic carpeting. If carpeting
exists in the area in which the equipment will be installed, special antistatic
pads are recommended and can be placed close to the equipment where the
operators will be located.

Appendix B-5

• Power
The supermicr:osystems will operate with the following ac line voltages and
frequency variations.
F100rstand

Pedestal

Cabinet

120 Vac Tolerance

90 - 128 VRMS

88 - 128 VRMS

90 - 128 VRMS

240 Vac Tolerance

176 - 256 VRMS 176 - 256 VRMS 176 - 256 VRMS

120 Vac Frequency 47 - 63 Hz

47 - 63 Hz

49-51Hz*

240 Vac Frequency 47 - 63 Hz

47 -63 Hz

49-51Hz*

*With an RA81 disk.

The ac power cord that supplies power to the system unit and terminals
should be a separate line dedicated only to the system and terminals.
ac Power Quality
The quality and reliability of the ac power can vary depending on the location.
Some sites may require that the user provide power conditioning equipment
to ensure that the proper power tolerances and filtering are maintained.
ac System Power
The ac power source should be adequate to supply the original system and
allow for system expansion. A dedicated branch circuit from the power distribution panel is recommended for each system. This circuit must meet all
national and local standards that apply to it. It must provide a good system
ground, be stable, and free from electrical noise.

NOTE
Do not connect other equipment, such as air conditioners,
office copiers, or coffeepots, on the same circuit with the system.
Table B-3 lists the maximum ac current requirements, wattage, and heat dissipation for the system units. When other devices, such as console and printing
terminals, are used, the additional ac current requirements must be included
in the total.

Appendix B-6 • Site Preparation and Installation

Table B-3' System Power
Floorstand

Pedestal

Cabinet

120 Vac
Current

6.9 amperes

4.4 amperes

16.4 amperes

240Vac
Current

3.83 amperes

2.2 amperes

8.6 amperes

120V
Input Power

579 watts

345 watts

1,722 watts

Heat
Dissipation

1,978 BTU/k

1,177.40 BTU/k

5,87.2 BTU/k

• Acoustics
The following chart lists the acoustics levels of each system.
Floorstand

Pedestal

Cabinet

Acoustics per
ISO 7779

120V 240 V

120 V 240V

120V 240 V

LNPE
LPA

6.0B

6.1 B

7.1 B* 6.7 B*

45 dB 45 dB

48 dB

57 dB* 55 dB*

*With an RA81 disk.

• Storage
Adequate storage facilities should be provided for the equipment, software,
paper supplies, and accessories.
Systems and Peripherals
If it becomes necessary to store the system units, add-on storage devices, or
tertninals for extended periods, the equipment should be enclosed in plastic
covering and placed in the original containers. It is recommended that the system be stored in a safe area not subjected to rapid or extreme temperature
changes or high hutnidity levels.
Supplies
The system supplies, including flexible disks, printer paper, and ribbons,
should be stored in a cabinet or containers that will protect them from damage
or contaminants. The storage facilities should be located close to the system
for easy accessibility.

Appendix B-7

• Installation Considerations
Before an option can be added to a supermicrosystem, the following questions
should be answered:
• Does the system have sufficient dc power to support the additional option?
• Does the Q22 bus have adequate ac loads available for the module?
• Is space available in the backplane(s) for the module installation?
• Is space available on the I/O distribution panel for the connector panel
insert?
• Have the modules been properly configured for installation?
Disk-drive Installation
The RQDX series of controllers can communicate with up to four logical diskdrive units. The RX50 is considered to be two units because it contains two
separate diskette drives in one mechanical assembly. The RD53, RD52, and
RD51 disk drives are each considered to be a single unit. Detailed information
on the removal and installation procedures is contained in each of the supermicrosystem owner's manuals. The RQDX1 must reside in the last-used slot of
the backplane. The RQDX2 and RQDX3 must reside in the upper backplane
in a MicroVAX II or MicroPDP-ll/83 cabinet system.
The KDA50 disk controller modules control and communicate with up to four
RA-series disk-drive subsystems. Each disk drive is considered to be one unit.
Two RA-series drives can be installed into a cabinet enclosure. Two additional
RA-series drives can be installed into an expansion disk-drive cabinet. The
KDA50 module set must reside in the first two slots of the lower backplane in
a MicroVAX II or MicroPDP-ll/83 cabinet system.
All of the controller modules are preset during manufacturing and require no
adjustments or wiring before installation.
Backplane Assembly Layout
Backplane assemblies for the supermicrosystems are available in 8-, 12-, and
14-slot versions. The 14-slot version comprises two 8-slot backplanes, with
two slots reserved. Figure B-1 shows each of these backplane layouts. The system and option modules can be quad height or dual height. A quad-height
module occupies all four rows-A, B, C, and D-A dual-height module
occupies only two rows-A and B or C and D. Some of the backplane slots are
dedicated to particular system modules. Option modules are installed in the
remaining slots according to their priority.

Appendix B-B • Site Preparation and Installation

Slots 1 through 3 of the MicroVAX I backplane are dedicated to the CPU
(occupies two slots) and main memory (one slot). Slots 1 and 2 of the
MicroVAX II and MicroPDP-ll backplanes are dedicated to the CPU and
main memory (one slot each).

If the 8-slot single backplane or the 14-slot dual backplane is selected, then
the Q22-bus signals will travel through rows A and B of connector slots one
through eight, and in rows C and D of connector slots four through eight in
each backplane.
If the 12-slot backplane is selected, the Q22-bus signals will travel through
rows A and B of connector slots one through twelve, and in rows C and D of
connector slots five through twelve.
Rows C and D of all the backplanes provide an interconnection with each
other. This interconnection is referred to as the CD bus.

Appendix B-9
MicroVAX II
---------------------ROWS-------------------SLOTS

]

KA630 CPU MODULE
MS630 MEMORY MODULE
O-COSlot

022 Bus

1 quad-height
or

022 Bus

2 dual-height

,
,

022 Bus

O-COSlot

:
:

022 Bus

MODULE SIZE
2 quad-height

022 Bus
022 Bus

,,
,

!
,,

12 L__________________________________________________ .;, _____________________ J,( I
Viewed from module insertion side

MicroVAX I
,---------------------ROWS---------------------A

SLOTSl

M7136 MEMORY CONTROLLER MODULE

M7135 DATA PATH MODULE

O-COSlo!

022 Bus

]

MODULE SIZE
2 quad-hei.f.lht
-KD32-A

O·COSlot

,
,
,

022 Bus
1 quad-height
or
2 dual-height

022 Bus
022 Bus

022 Bus

Viewed from module Insertion side

MicroPOP II

i---------------------- ROWS - - - - - - - - - - - - - - - - - - - - SLOTS!

10
11

KDJ11-BB

MSV11 MEMORY MODULE

KDJ11-BF

O-CDSlot

O-COSlot

022 Bus

,
:

PMI MEMORY

]
,

1 quad-height
or

2 dual-height

022 Bus

Q22 Bus

12.L ________________________________________________________________________ J.
Viewed from module insertion side

Figure B-1· Backplane-slot Assignments

MODULE SIZE
2 quad-height

Appendix B~ 10 • Site Preparation and Installation

Power and Loading Requirements
The System Configuration Worksheets, Figure B-2, can be used to determine
the power consumption and bus load requirements· of the options to be
installed. The worksheet includes 5 Vdc current, 12 Vdc current, and the ac
bus loads.
To calculate the power and loading, enter the current values of the options
that have previously been included in the system and the values of the options
to be added. These are entered in the option column.
The current (amperes) column lists the total current available from the 5 Vdc
and the 12 Vdc outputs of the power supply in the "available" columns. The
VAX Systems and Options Catalog and the PDP-II Systems and Options Catalog lists the specifications of all the system modules, options modules, and storage devices. Enter the current requirements in the "used" column of Figure
B-2 for each option included or to be installed and subtract that value from
the previous "available" column. Enter the new value in the "available" column next to the value entered into the "used" column. When all the values
have been entered on the worksheet, perform the total wattage calculation
shown on the bottom of Figure B-2.
The power supply in the pedestal enclosure provides a maximum of 230
~atts-up to 36 amperes at 5 V (180 watts) and up to 7 amperes at 12 V (84
watts). This total is 264 watts and exceeds the 230-watt maximum allowable
total of the power supply. Therefore, the total wattage for the 5 Vdc and 12
Vdc must be calculated separatdy to prevent exceeding the total power supply
voltage. The RX50, RD53, RD52, and RD51 disk drives also require power
from the power supply and must be included in the power calculations.
The power supply in the £loorstand enclosure provides a maximum of 260
watts-up to 36 amperes at 5 V (180 watts) and up to 7 amperes at 12 V (84
watts) for each regulator. Again, this totals to 264 watts and exceeds the 230watt maximum per regulator. The total wattage must be calculated separatdy
to prevent exceeding the total power-supply voltage.
The power supplies in the cabinet enclosure are the same as for the. pedestal
enclosure except that there are two of them.
The ac bus loading is calculated in.a manner similar to the de bus loading.
Each bus load is entered into the "used" column and subtracted from the previous "available" value. When the value is less than 1, the total bus loading
has been exceeded.
For complete power and loading requirements for each of the supermicrosystems and their options, refer to the VAX Systems and Options Catalog and the

PDP-II Systems and Options Catalog.

CURRENT (amps)
OPTION

~
~

+5V
used

Maximum

slot

available

used

36.0

LOADS

available

1 quad

KA630·AA

6.2

29.8

0.14

6.86

1 quad

MS630·

1.0

28.8

0.0

6.86

•

1 quador

DZQll

1.0

27.8

0.36

6.5

1 quad or
2 dual

~
~

1 quad or

1b-

iii!

::t.
0

used

7.0

PANEL INSERTS

aeBUS
+12V

available

2x3
used

available

1 x4
used

2.7
1.5

available
20r5

29.0
26.3

20r5

26.3

20r5

24.8

2 dual

----- ----

20r5

L .!£K~O_ J _~9_ J _ ..?~9__ 1_03_1_...!'~ __ 1_2:2 _1_ ~2...!' __ L _--.:. _L __2___ L _-_ -'__2..?~_
L !l£D!3_ J _~4~ J _ ..?~4~ _1_03~ 1_ ...!'~4__ 1_1:2 _1_ ~1...!' __ L _1.... _ L __1___ 1__-_ -' __2..?r~_

2 dual

1 quad or
2 dual

,~----~---~-----.---.-----~---~-----~---~--------------

1 quad or
2 dual

' ~----~---~-----.---------~---~-----~------------------

;:t

!S~
I:!'

1 quader

2 dual

~----~---~--------------------------------------------

diskettedriveunitl

4.64

disk drive unit 2

2.14
58.32
76.65
134.97

IwaUsat + 12V
I waUsat + 5V

I(~t~~:'ba~I~30 or less)

~
~

If
~
.....

Appendix B-12 • Site Preparation and Installation
Module Space Requirements
After the power and ac load values have been calculated, the location of the
module in the backplane must be determined_ The backplane slot where the
module will be installed is determined by the number of existing modules
installed and by the interrupt priority level of the additional modules. Modules with the highest priority should be closest to the CPU module(s). Figure
B-3 shows several different module configurations that can be implemented in
the backplanes. The following summary provides some specific guidelines for
the module locations:

• The MicroVAX I CPU modules always occupy slots 1 and 2. The
MicroVAX II and MicroPDP-ll CPU modules occupy slot 1 only.
• The memory module(s) is always installed starting with the next slot after
the CPU module(s).
• The DZQll (or DHVll) module installs in the slot following the last memorymodule.
• The DEQNA module installs in the slot following the last memory module.

• If both the DZQll (or DHVll) and the DEQNA modules are present, the
DEQNA is installed in the next highest slot following the last memory module and the DZQll (or DHVll) follows in the next slot after the DEQNA.
• The DLVJl module installs in the slot following the DEQNA or DZQll
module.
• The RQDXl module installs in the next highest quad slot following the last
option installed. If this last option has an open dual slot, a G7272 grantcontinuity module must be mounted in row A or C of that slot. In a 14-slot
backplane, the RQDX2 and RQDX3 must reside in the upper backplane.
And the KDA50 module set must reside in the first two slots of the lower
backplane.

• If only one dual-height module is installed in a slot between two quadheight modules, the G7272 must be installed in row A or row C of the
same slot.

• In the 8-slot backplane, if only one dual-height module is installed in slot 8,
it must be installed in rows A and B. If only one dual-height module is
installed in slot 7, and slot 7 is the last-used slot, the module must be
installed in rows C and D.

Appendix B-13
ROW

ROW
SLOTS

SLOTS

KA630
KD32-AA

MS630BA

MSV11-0A

3
G7272

G7272 :

MSV11-0A

DEONA

DZV11

RODX3

DEONA

RODX1

ROW

ROW
SLOTS

SLOTS

KDJ11-BB

DZV11

RODX2

KDF11-BF

MVS11-0A
G7272 :

DEONA

MVS11-0A

G7272 :

DEONA

DZV11

RODX2

7
8

ROW
SLOTS

ROW

SLOTS

MSV11-JD

MS630-BA

DEONA

DHV11

TOK50

RODX3

7
8

KA630

KDJ11-BF
G7272 :

G7272 :

I
DHV11
TOK50
RODX3

Figure B-3' Sample Module Assignments

DEONA

Appendix B-14 • Site Preparation and Installation

I/O Distribution Panel Inserts
Each option that requires an external connection toa device includes a panel
insert that mounts on the I/O distribution panel. All models are shown in Figure B-4. The I/O distribution panel inserts are 1 by 4 inches and 2 by 3 inches.
Blank panel covers are mounted where rio panel insert·is installed. The panel
covers can be removed and the 1/0 distribution panel inserts installed;
PANEL A
CONSOLE
PANEL
INSERT

PANEL B INSERT
(OPTIONAL)

PANELC
INSERT
(OPTIONAL)

REMOVABLE PLATES

- ..

TV PE
B

00
OI]

-~~~~8

TYPE
A

-.!....

•

Figure B-4 • I/O DistrilJUtion Panel Inserts

PANEL 0
INSERT
(OPTIONAL)

Appendix B-15

• Additional Documentation
The supermicrosystem hardware documentation must be ordered by type of
enclosure. The following list breaks down the manuals by enclosure.
F100rstand Version

Micro VAX II Technical Manual
Micro VAX II Owner's Manual
MicroPDP-ll System TechnicalManual

AZ-FE09A-TN
AZ-FE08A-TN

MicroPD P-II Owner's Manual

AZ-FEOOA-TC

AZ-FEOIA-TC

Pedestal, Tabletop, and Rackmount Versions

Micro VAX II Technical Manual

AZ-FE06A-TN

Micro VAX II Owner's Manual
Micro VAX I CPU Technical Description
Micro VAX I CPU Owner's Manual

EK-KD32A-TD
EK-KD32A-OM

MicroPD P-ll System Technical Manual
MicroPD P-II System Owner's Manual

EK-MICII-TM
EK-MICll-OM

AZ-FE05A-TN

Cabinet Version

Micro VAX II Technical Manual
Micro VAX II Owner's Manual
MicroPDP-ll System TechnicalManual
MicroPDP-11 Owner's Manual

AZ-GMBAA-MN
AZ-GMCAA-MN
AZ-GNIAA-MC
AZ-GN2AA-MC

Miscellaneous

VAX Systems and Options Catalog

ED-300I2-46

PDP-II Systems and Options Catalog
Terminal and Printers Handbook

ED-27980-4I
EB-2629I-56

Appendix B-16 • Site Preparation and Installation

Like all of Digital's products, the supermicrosystems and their system software have been designed for reliability and manufactured to strict quality control standards that ensure that each unit meets its design goals. Digital's
customer services organization is ready to follow up with quality support if it
is required. Digital is the complete service vendor and has the products and
tools to back its commitment to customer satisfaction.

• Field Service
Digital's Field Service is committed to customer satisfaction through quality
delivery of a complete range of service products. The service organization complements Digital's hardware offerings and makes a significant contribution to
Digital's position as an industry leader.
The Digital Field Service organization includes over 20,000 service engineers
who are backed by more than 3,500 administration and support personnel.
Backing each service engineer are resources and support programs that help
each engineer to meet customer needs more effectively. Some of these
resources and programs are a computerized logistics network, formalized
training programs, an automated call-handling system, remote diagnosis,
remote support, the site-management guide, and an action planning and problem escalation program.

The OEM Portfolio
For OEM purchasers of supermicrosystems, Digital offers a comprehensive
service program called the OEM Portfolio. This program is designed to meet
the needs of OEMs whether they require full-service contract protection or
backup maintenance support.
The OEM Portfolio gives OEMs a choice between the Blue Chip Program,
which provides full service from Digital, or the Partnership Program, which
provides qualified, backup maintenance support for OEMs who do their own
maintenance.

The Blue Chip Program is directed toward OEMs who sell Digital's services
directly to their customers, or buy our services in volume and then resell them
to their end users as part of a total package. The Blue Chip Program lets these
OEMs choose from a product menu which includes DEC service, Basic Service,
Full System Service for personal computers, or Carry-In service contracts
through our Digital Servicenters.

Appendix C-2 • Customer Seroices
With the Blue Chip Program; OEMs who wish to sell our services directly to
their customers can earn commissions. They receive an enrollment kit that contains all the materials they need to begin selling Digital services. OEMs who
buy our services in volume can resell them as part of a total package sold to
their end users. This may entitle them to a volume dollar discount based on an
annual performance review.
OEMs enrolled in the Blue Chip Program.can also choose from the following
business options:
• Fixed price deinstallation and reinstallation when moving systems to end
user's sites.
• New, improved trade show support.
• DECompatible Service for systems incorporating designated non-Digital
hardware.
• Option to buy service in 30-day increments;
• OEM installation support.
The Partnership Program is for OEMs who buy Digital hardware components
and maintain their systems and/or their end user's systems. The Partnership
Program offers a wide range of onsite ahd offsitesuppert. This progtam
includes
• Telephone technical support by senior engineers,
• Guaranteed onsite response by a senior engineer (when dispatched by telephone support).
.
..
• Emergency parts exchange service at designated Digital Servicenters.
OEMs in the Partnership Program can also choose from a variety of mai1~in
services, maintenance support tools, and educational serviCes to maintain Digital hardware themselves.
.
.
:.",'

Appendix C-3

Onsite Services
Onsite contract services are available for all of the supermicrosystems, subject
to minimum hardware configurations_ These services provide corrective maintenance, preventive maintenance, and all applicable engineering changes to
ensure that the systems and their options are operational and kept completely
up-to-date. In addition to priority service, contractual maintenance allows
Digital's customers to budget for their annual maintenance needs. The
monthly contract charge covers all travel, labor, and materials. Users have a
choice of tailored service agreements. In addition to basic coverage, extended
hours are available to customers with critical applications that require special
attention.

• DECseroice
The DEC service agreement is Digital's most comprehensive onsite service
product. It provides committed response time including a 4-hour service
response if your system is located within 100 miles of a Digital service location. DEC service also provides continuous repairs until the problem is solved,
a program of preventive maintenance, installation of the latest engineering
changes, and automatic escalation for complex problems. DEC service also
offers the customer a choice of coverage hours-up to 24 hours, seven days
per week.

• Basic Seroice
The Basic Service agreement is the best alternative for customers whose
requirements do not demand a fixed response time to calls for remedial maintenance, or for continuous work to resolve system-down situations outside coverage hours. Basic Service offers economical, yet full-service coverage. Calls for
service receive priority status, second only to DEC service calls. It also provides preventive maintenance, installation of the latest engineering changes,
and the guarantee that complex problems will be resolved by highly qualified
service engineers. The hours of coverage are during first-shift business hours.

• Per Call Seroice
Per Call Service is a noncontractual, time and materials service. It is available
on an onsite and offsite basis. Onsite service is available Monday through Friday during standard business hours, from 8:00 A.M. to 5:00 P.M. Offsite Per
Call Service is available through mail-in board replacement and carry-in system repairs.

Appendix C-4 • Customer Services

• Shared Maintenance Service
Shared Maintenance Service is a product that combines onsite and offsite services_ It is offered to qualified customers who perform their own preventive
and remedial maintenance provided that they meet certain prerequisites_ The
onsite support provided by Digital is similar to a DEC service agreement
except that customers, after paying a fixed monthly fee (a percentage of the
DEC service maintenance charge), pay only for labor (at the local Per Call rate)
and materials as they are required. Shared Maintenance Service features
include onsite repairs, committed response, branchtdephone support (technical), emergency access to branch logistics, extended coverage (optional), and
remote diagnosis (optional where available) .

• DECompatible Service
DECompatible Service is a product that provides standard onsite services to
sdected non-Digital hardware products that are attached to Digital systems.
DECompatible Service is provided under DECservice, Basic Service, or
Carry-In agreements, depending on the particular device. The levd of service
and response time under this program is the same quality service as that available for Digital's hardware products.

• Recover-All Service
Recover-All Service provides full product repair and/or replacement to Digital's hardware products that have been damaged due to accidents or incidents
not covered under the other service agreements. Recover-All service expands
the customer's service agreement to cover fire, water damage, natural disasters, power failure, sprinkler leakage, and theft. Recover-All also provides
reimbursement for the cost of movement of equipment to a safe place,
returning equipment to the site when safe conditions have been restored,
removal of damaged equipment, transportation and installation of replacement equipment, replacement of fire protection chemicals, restoration of damaged Digital system software and customer data from backup disks and tapes,
and data processing at a temporary location.

Offsite Services
·Customers who do not require onsite services can take advantage of the Digital's offsite services that include Digital's Servicenters and DECmailer.

Appendix C-5
• Servicenters
The Digital Servicenter is a carry-in repair center for Digital's terminals and
supermicrosystems_ The Servicenter offers low-cost repairs at over 160 convenient locations. At the Servicenter, the same quality service is provided that is
given to offsite service calls. The Servicenter guarantees 2-day turnaround
time. The customer may select from a variety of service offerings-contract,
per call, or parts exchange. All Servicenter service and parts come with a 90day warranty .

• DECmailer
DECmailer is a return-to-factory replacement service for customers who maintain their equipment at the module or subassembly level. It provides 5-day
turnaround, free return shipping, 90-day warranty on service and parts, 24hour emergency service, monthly billing, and quarterly activity reports.

• Sohware Services
Digital's Software Services are available to support customers during any
phase of their system analysis, software devdopment, or implementation
efforts. These services start with the personal attention of a Digital software
specialist and continue as long as the customer owns the system.
A Digital software specialist often works with a Digital sales representative to
evaluate a prospective user's needs prior to purchase, in order to recommend
hardware/software solutions appropriate to the customer's requirements. A
full range of services is available to assist customers throughout the planning,
implementation, and production phases of their systems.

Startup Service Packages
Software Product Services offers three comprehensive Startup Service Packages for support of the operating system. Each package provides media and
documentation and one year of service for the operating system and for qualified layered products on that system. Each service package also allows customers to take advantage of several levels of training developed by Digital's
Software Services and Educatioruil Services organizations. Training materials
and information are available upon purchase of the package.

• Startup Service Package-Level III
Level III includes onsite software support when needed for critical situations

and for more comprehensive training. Level III provides

Appendix C-6 • Customer Services

• DEC support Service.
• Media and documentation for the operating system and the most dependent software purchased concurrently.
• Installation and DECstart-PLUS.
• Training .
• Startup Seroice Package-Level II
Level II is appropriate for a technical staff that can support the new system
after Digital has trained the staff, insta1led the product, and oriented the
staff concerning system operation. Level II provides

• Basic Service.
• Media and documentation for the operating system and the most dependent software purchased concurrently.
• Installation and DECstart.
• Training .
• Startup Seroice Package-Level I
Level I is appropriate for a technical staff requiring minimal training and having the skill to install and support the new system, using the Basic Service's
telephone-support service to maintain the software at its most current level.
Level I provides:

• Basic Service.
• Media and documentation for the operating system and most dependent
software purchased concurrently.
• Training.
DECstart Service

DECstart consists of two levels of fixed-price consulting services with a
proven combination of direct assistance, documentation review, discussion,
and hands-on experience provided at the customer's site by a Digital software
specialist. The DECstart services are conducted over a 90-day period to assure
mastery of the system. Programmers and system managers are taken step by
step through the techniques required to operate their system effectively.

Appendix C-7

To supplement the DEC start Service, additional services are priced on a timeand-materials basis. An estimate can be given for any consultation that a customer may be considering. In addition, a Digital software specialist can draw
up a Customer Support Plan to help the user determine any further areas in
which additional services might be beneficial.
Installation Service
The purchase of installation as a separate service is appropriate in those
instances in which there is no need to purchase a Startup Service Package or a
need to have add-on dependent products installed. Installation Service
ensures that customers have received all of the proper distribution materials,
and that the system generation process for the operating system and/or
dependent software products is completed.
Network Planning and Design Service
Digital's Networking Planning and Design Service provides a network-based
solution to customers' information requirements. Each network design is
based on a customer's business needs, organizational structure, and operational procedurc;s. This is accomplished through interviews by highly trained
Digital software specialists. These specialists gather network traffic and systems data, business and performance requirements, and growth expectations.
The information is then carefully analyzed. From the analysis a recommended
Digital network solution is developed. The solution consists of a network topological map and network cost estimates. This design will meet the customer's
network performance parameters in relation to system load, growth and flexibility constraints, throughput and response-time constraints, and cost constraints.

The Network Planning and Design Service approaches network design from a
set of business needs. These requirements are transformed into a networkbased technological solution capable of meeting the customer's immediate and
long-term networking needs.
Service for Software Agreements
For most applications, resources are available to install software and provide
support to assure that the purchased software products perform according to
Digital's commitments. Software support is assured through a variety of services that offer customers the opportunity to keep their software up to date
and running smoothly through the life of the computer system.

These services include startup services, installation services, and ongoing ser-

vice agreements to assist the customer during and after the installation of
their software.

Appendix C-8 • Customer Seroices

• DECsupport Service fOT Software
DEC support is· the most comprehensiVe software product service available.
DECsupport includes all of the elements of Basic Service, plus onsite assistance and software support for critical situations.

• Basic Service for Software
Basic Service is appropriate for users who do not require onsite support, and
includes all of the elements of Self-Maintenance Service, telephone-support
service, plus online support via the Digital Software Information Network
(DSIN) for usage and remedial software questions. DSIN enables customers to
receive software information and solutions to software problems by computer
access to a Digital Customer Support Center. Currently, DSIN is available
only in the United States and Canada.

• Self-maintenance Service fOT Software
Self-maintenance Service enables users to maintain their own system software

and provides tools that include media and documentation updates, formal software problem-reporting mechanisms, arid newsletters and dispatches containing information about new software developments and enhancements.

Supplementary Service Options
Software Services provides supplementary options for supermicrosystems
a1readyunder a service agreement.

• Media Update Service
The Media Update Service is a subscription service that provides Software
Product Services customers with a means of obtaining additional copies of
machine-readable media for most operating systems and dependent products.
Customers may choose from a variety of distribution media. A prerequisite
for the service is that customers have a DEC support, Basic, or Self-maintenance agreement with Digital.

• Documentation Update Service
The Documentation Update Service supplies service customers with the documentation-only portion of a Software Product Services agreements. The documentation delivered with this service is the portion of the document that was
changed or revised since the last release.

• Service Right-to-Copy
This option allows customers with a Software Product Services agreement to
automatically copy the updates to the product under agreement onto a single,
additional CPU.

Appendix C-9

• Additional Telephone Support Center Contact Service
This service allows customers who have a Basic or DEC support agreement to
add names to the list of people entitled to call the Digital Telephone Support
Center.

• Additional Software Dispatch Subscription Service
Customers who have a Software Product Services agreement can obtain an
additional copy of the dispatches and technical newsletters supplied under the
agreement.

• Software Revision Right-to-Copy
The Software Revision Right-to-Copy option allows customers to copy a single update to the product onto a single, additional CPU.

• Educational Services
Educational Services offers a complete range of training programs and services to support the supermicrosystem software and hardware.
Training facilities are located in Japan, Australia, Great Britain, Germany,
France, the Netherlands, Sweden, Italy, Canada, and throughout the United
States. Services are centered around fully equipped regional education centers. These centers provide a staff of educators dedicated to providing quality
education and training, and a variety of instructional formats that supports
the learning pace of individuals as well as classrooms of individuals learning
together.
Digital's Educational Services publishes a Digest every three months that
includes a description and 6-month schedule of all software courses and a 9month schedule of all hardware courses. It also includes the ordering information for the self-paced instruction material. The Digest may be ordered by contacting your sales representative or your nearest Digital Training Center.
Courses are regularly scheduled classes offered at training centers. They cover
the student range from first-time user to those needing highly specialized
training on the theory of operation. Most catalog courses include extensive
hands-on laboratory time, and all incorporate the use of a wide range of student workbooks, reference manuals, and other instructional materials.
Specialized training is available for users with unique applications or training
situations. This training is designed to give the student the maximum relevant
material for specific applications, while minimizing extraneous information.
The customized courses are tailored to the individual customer's schedule and
typically are presented in a series. The customized courses can be modified
from existing courses or can be entirely new programs based on mutually
agreed-upon objectives.

Appendix C~lO' Customer Services
Customers with a group of individuals to train may find it more economical to
have Educational Services conduct courses at the users' home sites. Onsite
instruction of bOth catalog and customized courses eliminates travel and other
expenses incurred by students attending classes at training centers. This
method of instruction further enhances training by allowing Digital instructors to emphasize points of particular value to the students' applications and
operations.
By taking advantage of the latest in text-based, computer-based, audiovisualbased, and IVIS-based techniques, Educational Services has developed a
series of courses that offers self-paced instruction (SPI). These courses are convenient, self-contained, and modular. SPI format allows students to progress
at their own rate, to study when and where they wish, and to "play back" or
reread modules for review. SPI course Iilaterial is available in several formscomputer media (such as magtape and flexible disk), videotape, videocassette,
audio/filmstrip cassette, and text-all supported by student guides and workbooks. Computer-based instruction (CBI) refers to courses that students take
at their own pace at their terminal.'CBI course material is available on 1,600bits/inch tape and TU58 cassette tape, as well as on flexible disk for use
online.
Selected courses on MicroVAX II will soon be available.

Training Centers·
The Digital Training Centers located in the United States are listed as follows. For additional information on courses, training materials, or other training center locations, call the following customer support number in
Massachusetts: (617) 276-4373 .

• California
Los Angeles Training Center
4311 Wilshire Boulevard, Suite 400
Los Angeles, California 90010-3779
Telephone: (213) 937-3870
Santa Clara Training Center
2525 Augustine Drive
Santa Clara, California 95051-7576
Telephone: (408) 748-4048

Appendix C-ll
• Colorado
Denver Training Center
8085 South Chester Street
Englewood, Colorado 80112-1478
Telephone: (303) 649-3000

• Illinois
Chicago Training Center
5600 Apollo Drive
Rolling Meadows, Illinois 60008-4063
Telephone: (312) 640-5520

• Massachusetts
Boston Training Center
12 Crosby Drive
Bedford, Massachusetts 01730-1493
Telephone: (617) 276-4380

• Michigan
Detroit Training Center
37735 Interchange Drive
Farmington Hills, Michigan 48018-1270
Telephone: (313) 640-5520

• New Mexico
Los Alamos Training Center
1900 Diamond Drive
Los Alamos, New Mexico 87544
Telephone: (502) 662-6905

• New York
New York Training Center
One Penn Plaza
. New York, New York 10119-0031
Telephone: (212) 971-3545

Appendix C-12· Customer Services

• Texas
Dallas Training Center
12100 Ford Road, Suite.200
Dallas, Texas 75234-7288
Telephone: (214) 888-2500

• Washington, D.C.
Washington, D.C. Training Center
8100 Corporate Drive
Landover, Maryland 20785-2231
Telephone: (301) 577-4300

Appendix D • Documentation

The MicroVAX and MicroPDP-ll systems and software are supported by a
comprehensive set of documents dedicated to their operation, programming,
and maintenance. These manuals are periodically updated to include new
developments and equipment and can be ordered through Digital's Publishing
and Circulation Services. The following lists contain the titles and associated
Digital order numbers of documents that apply to the MicroVAX and
MicroPDP-ll supermicrosystems.
To order these documents, write to the following address:
Digital Equipment Corporation
Publishing and Circulation Services
10 Forbes Road
Northboro, Massachusetts 01532-2597

Micro VAX Hardware Manuals
Micro VAX 630 CPU Module User's Guide
Micro VAX II Technical Manual

EK-KA630-UG

Floorstand Version
Pedestal, Tabletop, and Rackmount Versions
Cabinet Version

AZ-FE09A-TN
AZ-FE06A-TN
AZ-GMBAA-MN

Micro VAX II Owner's Manual
Floorstand Version
Pedestal, Tabletop, and Rackmount Versions
Cabinet Version
Micro VAX I CPU Technical Description
Micro VAX I Owner's Manual

AZ-FE08A-TN
AZ-FE05A-TN
AZ-GMCAA-MN
EK-KD32A-TD
EK-KD32A-UG

VAX Architecture Handbook
VAX Hardware Handbook
Microcomputer Products Handbook

EB-19850-20
EB-2171 0-20
EB-26078-41

Appendix D-2 • Documentation

Micro VAX Software Manuals

VAX/VMS Technical Summary (includes MicroVMS)

EJ-30083 c41

VAX/VMS Information Management Handbook
VAX/VMS System Software Handbook

EB-25780-44

VAX/VMS Language and Tools Handbook
VAXELN Technical Summary
VAX Software Handbook
VAX Software Source Book (Volumes 1 and 2)

EB-25966-48
EB-27240-48
EJ-30083-41
EB-21812-20
EB-26I25-46

MicroPDP·ll Hardware Manuals

KDJll.A CPU Module User's Guide
KDFII·B CPU Module User's Guide

EK-KDJIA-UG
EK-KDFEB-UG

DCJII Microprocessor User's Guide
MicroPDP-ll System TechnicalManual
Floorstand Version

EK-DCJ11-UG

Pedestal, Tabletop, and Rackmount Versions
Cabinet Version

AZ-FEOIA-TC
EK-MICII-TM
AZ-GNIAA-MC

MicroPDP-ll Owner's Manual
Floorstand Version
Pedestal, Tabletop, and Rackmount Versions
Cabinet Version

AZ-FEOOA-TC.
EK-MICI1-0M
AZ-GN2AA-MC

Microcomputer Products Handbook

EB-26078-4I

MicroPDP·ll Software Manuals
RSX-II Handbook (includes Micro/RSX)

EB-25742-41

RSTS/E Handbook (includes Micro/RSTS)
ULTRIX Software Guidebook
PDP-II Software Handbook

EJ-26153-20
EB-25398-41

PDP-II Software Source Book (Volumes 1 and 2)

EB·27333-41

EJ-23534-18

Appendix D-3
Miscellaneous

VAX Systems and Options Catalog

ED-27973-46

PDP-11 Systems and Options Catalog

ED-27981-41
ED-27352-42

Networks and Communications Buyer's Guide
Networks Handbook
Networks Guidebook
Terminals and Printers Handbook
MicroPDP-11/SV Information Sheet
RT950 Information Sheet
Rugged Microsystems for Manufacturing Environments
Brochure

EB-26013-42
EB-27241-42
EB-26291-56
ED-27034-72
EB-27642-54
EA-26790-49

Appendix D- 4 • Documentation

absolute-indexed mode: An indexed-addressing mode in which the baseoperand specifier is addressed in absolute mode.
absolute mode: Autoincrement-deferred mode in which the program counter
is used as the register and contains the address of the location containing the
actual operand.
access mode: Any of the four processor access modes in which software executes. Processor access modes are, in order from most to least privileged and
protected-kernel, executive (MicroVAX I only), supervisor, and user. When
the processor is in kernel mode, the executing software has complete control
of, and responsibility for, the system. In any other mode, the processor is
inhibited from executing privileged instructions.
access type: The way in which the processor accesses instruction operands or
a procedure accesses its arguments.
address: A number used by the operating system and user software to identify a storage location.
address-access type: The specified operand of an instruction is not directly
accessed by the instruction. The address of the specified operand is the actual
instruction operand. The context of the address calculation is given by the
data type of the operand.
addressing mode: The way in which an operand is specified.
address space: The set of all possible addresses available to a process.
ANSI: American National Standards Institute.
application: A specific program or task to which a computer solution can be
applied.
application program: A computer program designed to meet specific user
needs (Le., a program that controls inventory or monitors a manufacturing
process).
architecture: Computer architecture refers to the design or organization of
the central processing unit (CPU).
argument pointer: It contains the address of the base of the argument list for
procedures initiated using the call instructions.

G-2 • Glossary

ASCII (American Standard Code for Information Interchange) A' code
that assigns a binary number to each alphanumeric character and several nonprinting characters used to control printers and communication devices.
ASCII characters are seven or eight bits long and may have an additional parity
bit for error detection.
asynchronous transmission: Transmission in which time intervals between
transmitted characters may be of unequal length.
autodecrement-indexed mode: An indexed-addressing mode in which the
base-operand specifier uses autodecrement-mode addressing.
autodecrement mode: The contents of the selected register are decremented,
and the result is used as the address of the actual operand of the instruction.
The contents of the register are decremented according to the data type context of the register.
autoincrement-deferred indexed mode: The specified register contains th~
address of a longword that cootains the address of the actual operand. The
contents of the register are incremented by four which are the number of
bytes in a longword. If the program counter is used as the register, this mode
is called absolute mode.
autoincrement-indexed mode: An indexed-addressing mode in which baseoperand specifier uses autoincrement-mode addressing.
a';toincrement mod~: The contents of the specified register are used as the
address of the operand; then the contents of the register are incremented by
the size of the operand.
"
automatic-dialing unit: 'A device capable of a9tomatically generati~ dialing
digits.
automatic-calling unit: A dialing device supplied by the ~1l)1Ilunications
common carriers that permits a business machine to dial calIs' automatically
over the communications networks.
base-operand address: The address of the base of a t~ble or ~r~y reference
by indexed-mode addressing.
base-operand specifier: The register used to calculate the base-operand
address of a table or array referenCed by indexed-mode 'addressing.
base register: A general register that contains the address of the first entry in
a list, table, array, or other data structure.
BASIC (Beginners AIl-purpose Symbolic Instruction C()de): A\viclely used
interactive programming language developed by Dartmouth College that is
especially well suited to personal computers and beginning users.
batch processing: The techniqueofeiecuting a set of computer programs
without human interaction or direction during its execution.

G-3
baud: A unit of data transmitting/receiving speed, approximately equal to a
single bit per second_
bidirectional printing: A printing terminal technique to increase printing
throughput by printing every other line from right to left, thus saving the carriage return time_
binary digit (bit): In binary notation either of the characters 0 or 1. "Bit" is
the commonly used abbreviation for binary digit_

BISYNC: IBM's 1968 Binary Synchronous Communications Protocol (BSC)_
bit: Abbreviation for binary digit.
bit complement (also called one's complement): The result of exchanging
Os and 1s in the binary representation of a number. The bit complement of the
binary number 11011001 is 00100110. Bit complements are used in place of
their corresponding binary numbers in some arithmetic computations in computers.
bit-map graphics: A technology that allows control of individual pixels on a
display screen to produce graphic elements of superior resolution, permitting
accurate reproduction of arcs, circles, sine waves, or other curved images that
block-addressing technology cannot accurately display.
bit string: See variable-length bit field.
bit-transfer rate: The number of bits transferred per unit of time, usually
expressed in bits per second.

block: A group of bits transmitted as a unit. A coding procedure is usually
applied for synchronization or error-control purposes.
branch access type: An instruction attribute that indicates that the processor does not reference an operand address, but that the operand is a branch
displacement. The size of the branch displacement is given by the data type of
the operand.
buffer: A place where data can be stored temporarily. Terminals can store
data in a buffer if data is received faster than it can be processed or displayed.
bus: A group of parallel electrical connections that carry signals between computer components or devices.
byte: Eight contiguous bits starting at an addressable byte boundary.
cache memory: A small, high-speed memory placed between slower main
memory and the processor. A cache increases effective memory-transfer rates
and processor speed. It contains copies of data recently used by the processor
and fetches several bytes of data from memory in anticipation that the processor will access the next sequential series of bytes.
.
call frame: See stack frame.

G-4· Glossary

call instructions: The processor instructions CALLG (can procedure with
general argument list) and CALLS (call procedure with stack argument list) on
the MicroVAX I.
call stack: The stack, and conventional stack structure, used during a procedure call. Each access mode of each process context has one call stack and
interrupt-service context has one call stack.
carrier: A continuous frequency capable of being modulated or impressed
with a signal.
CCITT (Commite Consultatif International de Telegraphie et Telephonie):
An international consultative committee that sets international communicatiqns usage standards.
character: A symbol represented by an ASCII code. A single, printable letter
(a throughz), numeral (0 through 9), or symbol (%) (.) ($) (,) used to represent
data .
.Character printer: A printer, similar to a typewriter, that prints one character at a time.
Character string: A contiguous set of bytes. A character string is identified
by two attributes-an address and a length. Its address is the address of the
byte containing the first character of the string. Subsequent characters are
stored in bytes of increasing addresses. The length is the number of characters
in the string.
COBOL (Common Business-Oriented Language): A high-level programming language that is well suited to business applications involving complex
data records and large amounts of printed output.

c~mand: An instruction, typed by the user at a terminal or included in a
command file, that requests the software monitoring a terminal or reading a
command file to perform some well-defined activity.
command procedure: A file containing commands and data that the command int~rpreter can accept in lieu of the user's typing the commands individually on a terminal.
communications link: The physical connection, typically a phone line,
between a terminal and a computer or another peripheral device.
compatibility: The ability of an instruction, source language, or peripheral
device to be used on more than one computer;
compatibHity mode: A mode of execution that enables the central processor
to execute nonprivileged PDP-11 instructions.
computer network An interconnection of computer systems, terminals, and
communications facilities.

G-5

concentrator: A communications device that provides communications capability between many low-speed, asynchronous channels and one or more highspeed, synchronous channels.
condition: An exception condition detected and declared by software.
condition codes: Four bits in the processor status word that indicate the
results of previously executed instructions.
condition handler: A process that requests the system to execute when an
exception condition occurs.
console terminal: The terminal connected to the central processor used to
control the computer system.
context: Also called process state. See hardware context.
context indexing: The ability to index through a data structure automatically because the size of the data type is known and is used to determine the
offset factor.
context switching: Interrupting the activity in progress and switching to
another activity. Context switching occurs as one process after another is
scheduled for execution.
CPU (Central Processing Unit): Commonly called a computer. A set of electronic components that control the transfer of data and perform arithmetic
and logic calculations.
CRC (Cyclic Redundancy Check): An error-detection scheme in which the
check character is generated by taking the remainder after dividing all the serialized bits in a block of data by a predetermined binary number.
CRT terminal: Another name for a video terminal.
current-access mode: The processor access mode of the currently executing
software. The current-mode field of the processor status longword (PSL) indicates the access mode of the currently executing software.
cursor: A distinctive mark on a video terminal screen, such as a flashing
square or underline, that indicates where the next character will be displayed.
D_ floating data: Eight contiguous bytes starting on an addressable-byte
boundary, that are interpreted as containing a floating-point number.
daisywheel: A printhead that forms full characters rather than characters
formed of dots. It is shaped like a wheel with many spokes, with a letter,
numeral, or symbol at the end of each spoke.
data communications: The interchange of data messages from one point to
another over communications channels.
data type: The way in which bits are grouped and interpreted. In reference
to the processor instructions, the data type of an operand identifies the size of
the operand and the signficance of the bits in the operand.

G-G· Glossary

DDCMP (Digital Data Communications Message Protocol): A uniform disciplinefor the transmission of data between stations in a point-to-point or multipoint-data communications system. The method of physical-data transfer
used may be parallel, serial synchronous, or serial asynchronous.
DECnet: Digital communications networks.
device interrupt: .An interrupt received on processor-priority levels. Device
interrupts can be requested only by devices, controllers, and memories.
device name: The field in a file specification that identifies the device unit in
which a file is stored.
device register: A location in device controller logic used to request device
functions such as I/O transfers and/or to report status.
device unit: One drive, and its controlling logic, of a mass storage device system. A mass-storage system can have several drives connected to it.
diagnostic: A program that tests logic and reports any faults it detects.
direct-mapping cache: A cache organization in which only one address comparison is needed to locate any data in the cache because ady block of mainmemory data can be placed in only one possible position in the cache.
diskette: A flexible, flat, circular plate permanently housed in a paper envelope with magnetic coating that stores data and software.
displacement mode: The specifier extension is a byte, word, or longword displacement. The displacement is sign extended to 32 bits and added to a base
address obtained from the specified register. The result is the address of the
actual operand.
displacement-deferred mode: The specifier extension is a byte, word, or longword displacement. The displacement is sign-extended to 32 bits and added
to a base address obtained from the specified registers. The result is the
address of a longword that contains the address of the actual operand.
displacement-deferred indexed mode: An indexed-addressing mode in
which the base-operand specifier uses displacement-deferred mode addressing.
displacement-indexed mode: An indexed-addressing mode. in which the
base-operand specifier uses displacement-mode addressing.
distributed-data processing: A computing approach in which an organization uses computers in more than one location, rather than one large computer
in a single location.
DMA (Direct Memory Ac~ess): A facility that permits I/O transfers directly
into or out of memory without passing through the processor's general registers; performed either independently of the processor or on a cycle-stealing
basis.

C-7

DNA (Digital Network Architecture): A hardware and software scheme for
interconnecting Digital's computers in a network. It is composed of three elements-Data Access Protocol (DAP), Network Services Protocol (NSP), and
Digital Data Communications Message Protocol (DDCMP). See also
DDCMP.
dot-matrix printing: A printing technique that forms characters from a twodimensional array of dots.
double-floating data: See D_floating data.
draft-quality printer: A printer that produces characters that are readable,
but of less than typewriter quality.
drive: The electromechanical unit of a mass-storage device system on which a
recording medium (disk cartridge, disk pack, or magnetic-tape reel) is
mounted.
EBCDIC (Extended Binary Coded Decimal Interchange Code): An 8-bit
character code used primarily in IBM equipment. The code provides for 256
different bit patterns.
editor: A program that interacts with the programmer to enter new programs into the computer and edit them as well as modify existing programs.
Editors are language-independent and can edit anything in alphanumeric representation.
effective address: The address obtained after indirect- or direct-indexing
modifications are calculated.
EIA (Electronic Industries Association): A standards organization specializing in the electrical and functional characteristics of interface equipment.
error: Any discrepancy between a computed, observed, or measured quantity and the true, specified, or theoretically correct value or condition.
event: A change in process status or an indication of the occurrence of some
activity that concerns an individual process or cooperating processes. An incident reported to the scheduler that affects a process's ability to execute.
event flag: A bit in an event flag cluster that can be set or cleared to indicate
the occurrence of the event associated with that flag. Event flags are used to
synchronize activities in a process or among many processes.
exception: An event detected by the hardware (other than an interrupt or
jump, branch, case, or call instruction) that changes the normal flow of instruction or set of instructions. There are three types of hardware exceptionstraps, faults, and aborts.
exception condition: A hardware- or software-detected event other than an
interrupt or jump, branch, case, or call instruction that changes the normal
flow of instruction execution.
exception enables: See trap enables.

G-8 • Glossary

exception vector: See vector.
executive mode: The second most privileged processor-access mode. The
Record Management Services (RMS) and many of the operating system's programmed-service procedures execute in executive mode.
F _ floating data: Four contiguous bytes starting on an addressable byte
boundary. The bits are labeled from right to left 0 to 31. A two-word floatingpoint is identified by the address of the byte containing bit o.
fanfold paper: A continuous sheet of paper whose pages are folded accordionstyle and separated by perforations.
fault: A hardware-exception condition that occurs in the middle of an instruction and that leaves the registers and memory in a consistent state.
field: (1) See variable-length bit field. (2) A set of contiguous bytes in a logical
record.
file: A collection of logically related records or data treated as a single item. A
file is the means by which data is stored on a disk or diskette so it can be used
at a later date.
floating (point) data: See F_floating data.
floppy disk: See diskette.
font: A complete set of letters, numerals, and symbols of the same typestyle
of a given typeface.
formfeed: A device that automatically advances a roll of fanfold paper to the
top of the next page or form when the printer has finished printing the previous form.
FORTRAN (Formula Translation): A widely used high-level programming
language well suited to problems that can be expressed in terms of algebraic
formulas. It is generally used in scientific applications.
frame pointer (FP): FP contains the base address of the most recent call
frame on the stack.
full-duplex: Describes a communications channel on which simultaneous
two-way communications are available.
function key: A key that causes a computer to perform a function such as
clearing the screen or executing a program.

G_ floating data: Eight contiguous bytes starting on an arbitrary-byte
boundary. The bits are labeled from the right 0 through 63. AG_ floating
data is specified by its address A, the address of the byte containing bit o.
general register: Any of the registers used as the primary operands of the
.
native-mode instructions.
graphics: The use of lines and figures to display data in contrast with the use
of printed characters.

G-9

half-duplex: A communications channel on which only one-way communications are permitted at a time. The line can be "turned around" to allow data to
flow the other way. Some half-duplex links provide a special "reverse channel" in the direction opposite to the flow of data that permits transmission of
control signals only.
hardcopy: Hardcopy refers to paper printout, as opposed to video displays
that cannot be saved.
hardware context: The values contained in the following registers while a
process is executing-the program counter, the processor status longword,
the general registers, the processor registers that describe the process virtualaddress space, the stack pointer for the current-access mode in which the processor is executing, plus the contents to be loaded in the stack pointer for
every access mode other than the current-access mode.

Hertz (Hz): A unit of frequency equal to one cycle per second. Cycles are
referred to as Hertz in honor of the physicist Heinrich Hertz.
host computer: A computer attached to a network that provides such services as computation, database access, or special programs or programming
languages.
I/O (Input/Output): Pertaining to devices that accept data for transmission
to a computer system (input) and that accept data from a computer system for
transmission to a user or process (output).
image: Procedures and data that have been bound together by the. linker_
There are three types of images-executable, shareable, and system.
immediate mode: Autoincrement-mode addressing in which the program
counter is used as the register.
indexed-addressing mode: Two registers are used to determine the actual
instruction operand-an index register and a base-operand specifier. The contents of the index register are used as an index (offset) into a table or array.
The base-operand specifier supplies the base address of the array (called the
base-operand address or BOA).
index register: A register used to contain an address offset.
input stream: The source of commands and data. One of either the user's
terminal, the batch stream, or an indirect-command file.
instruction: A command that tells the computer what operation to perform
next.
instruction buffer: An 8-byte buffer in the processor used to contain bytes of
the instruction currently being decoded and to prefetch instructions in the
instruction stream. The control logic continously fetches data from memory to
keep the 8-byte buffer full.

G-lO· Glossary

integral modem: A modem built into a terminal rather than packaged sepa·
rately.
integrated circuit (IC): A complete electrical circuit on a single chip.
interface: An electronic assembly that connects an external device, such as a
printer, to a computer.
interleaving: Assigning consecutive physical memory addresses alternately
between two memory controllers.
interrupt: An event other than an exception or branch, jump, case, or call
instruction that changes the normal flow of instruction execution. Interrupts
are generally external to the process executing when the interrupt occurs.
interrupt-service routine: The routine· executed when a device interrupt
occurs.
interrupt stack: The systemwide stack used when executing in interrupt-service context. At any time the processor is either in a process context executing
in user, supervisor, executive, or kernel mode, or in systemwide interrupt-service context operation with kernel privileges, as indicated by the interrupt
stack and current mode bits in the processor status longword. The interrupt
stack is not context-switched.
interrupt-stack pointer: The stack pointer for the interrupt stack. Unlike
the stack pointers for process-context stacks, the interrupt stack pointer is
stored in an internal register.
interrupt vector: See vector.
kernel mode: The most privileged processor access mode. The operating system's most privileged services, such as 1/0 drivers and the pager, run in kernel
mode.
.
letter-quality printer: A printer that produces printing comparable in quality to that achieved by a typewriter.
.
linefeed: The printer operation that advances the paper by one line.
literal mode: The instruction operand is a constant whose value is expressed
in a 6-bit field of the instruction.
local: Hardwired connection of a computer to another computer, terminal, or
peripheral device, such as in a local area network.
longitudinal redundancy check (LRC): An error-checking technique based
on an accumulated exclusive-OR of transmitted characters.
longword: Four contiguous bytes starting on an addressable byte boundary.
Bits are numbered from right to left 0 through 31. The address of the longword is the address of the byte containing bit o.
main memory: See physical memory.

G-ll

mass-storage device: A device capable of reading and writing data on massstorage media such as a diskpack or a magnetic-tape reel.
memory management: The system functions that include the hardware's
page mapping and protection and the operating system's image activator and
pager.
mnemonic: A short, easy-to-remember name or abbreviation.
modem (Modulator/Demodulator): A device that converts digital data from
a terminal or CPU into analog signals for transmission over telephone lines and
convert the receiver data back to digital format.
MOS (Metal-Oxide Semiconductor): The most common form of LSI technology.
multiplexer: A device for connecting a number of communications lines to a
computer.
multiprogramming: A scheduling technique that allows more than one job to
be in an executable state at anyone time, so even with one CPU more than one
program can appear to be running at a time because the CPU is giving small
slices of its time to each executable program.
native mode: The processor's primary execution mode.
network: A group of computers that are connected to each other by communications lines to share information and resources.
node: An end point of any branch of a network, or a junction common to two
or more branches of a network.
numeric string: A contiguous sequence of bytes representing up to 31 decimal digits (one per byte) and possibly a sign.
octaword: A set of 16 contiguous bytes starting at an arbitrary-byte boundary.
offset: A fixed displacement from the beginning of a data structure.
one's complement: See bit complement.
opcode: The pattern of bits within an instruction that specifies the operation
to be performed.
operand specifier: The pattern of bits in an instruction that indicates the
addressing mode, a register, and/or displacement, that taken together identify
an instruction operand.
operand-specifier type: The access type and data type of an instruction operand(s).
operating system: A collection of computer programs that control the overall
operation of a computer and perform such tasks as assigning places in memory
to programs and data, processing interupts, scheduling jobs, and controlling
the overall input/output of the system.

G-12· Glossary

packed decimal: A method of representing a decimal number by storing a
pair of decimal digits in one byte.
packed-decimal string: A. contiguous sequence of up to 16 bytes interpreted
as a string of nibbles. Each nibble represents a digit, except the low-order nibble of the highest-addressed byte, which represents the sign.
packet switching: A data transmission process that utilizes addressed
packets in which a channel is occupied only for the duration of transmission of
the packet.
page: A set of 512 contiguous byte locations used as the unit of memory mapping and protection or the data between the beginning of file and a page
marker, between two markers, or between a marker and the end of a file.
paging: The action of bringing pages of an executing process into physical
memory when referenced. When a process executes, all of its pages are said to
reside in virtual memory.
parity: A common technique for error detection in data transmission. Paritycheck bits are added to the data so that each group of data bits include an even
number of "ones" for even parity and an odd number for odd parity.
peripheral: A device that is external to the CPU and main memory (Le.,
printer, modem, or terminal), but connected to it by appropriate electrical connections.
physical address: The address used by hardware to identify a location in physical memory or on a directly addressable secondary-storage device such as a

disk.
physical-address space: The set of all possible physical adresses that can be
used to refer to locations in memory space or I/O space.
physical memory: The memory contained in the CPU memory modules.
pixels: Definable locations on a display screen that are used to form images on
the screen. For graphics displays, Screens with a large number of pixels gener.
ally provide higher resolution.
point-to-point connection: A network configuration in which a connection
is established between two terminal installations.
polling: A technique for determining the order in which nodes take turns
accessing the network. This is done so that access collision can be avoided.
port: A location on the CPU where physical connection is made between the
central computer and a terminal, printer, modem, another computer, or a communications line.
position-dependent code: Code that can execute properly only in the locations in virtual~address space that are assigned to it by the linker.
position-independent code: Code that can execute properly without modification wherever it is located in virtual-address space.

G-13

printhead: The element in a printer that forms a printed character.
printout: An informal expression referring to almost anything printed by a
peripheral device; any computer-generated hardcopy.
printwheel: See daisywheel.
privileged instructions: Any instruction intended for use by the operating
system or privileged-system programs.
procedure: A routine entered via a call instruction. See also command proce-

dure.
process: The basic entity scheduled by the system software that provides the
context in which an image executes. A process consists of an address space
and both hardware and software contexts.
process address space: See process space.
process context: The hardware and software contexts of a process.
process space: The lowest-addressed half of virtual-address space, where process instructions and data reside. Process space is divided into a program
region and a control region.
processor: The functional part of the computer system that reads, interprets,
and executes instructions. See also central processing unit.
processor register: A part of the processor used by the operating system software to control the execution states of the computer system.
processor status longword (PSL): A system-programmed processor register
consisting of a word of privileged-processor status and the processor status
word.
processor status word (PSW): The low-order word of the processor status
longword.
program: A complete sequence of instructions and routines needed to solve a
problem or to execute directions in a computer.
program counter (PC): At the beginning of an instruction's execution, the
program counter normally contains the address of a location in memory from
which the processor will fetch the next instruction it will execute.
program disk: A disk containing the instructions of a program.

programming language: The words, mnemonics, and/or symbols, along with
the specific rules allowed in constructing computer programs. Some examples
are BASIC, FORTRAN, and COBOL.
protocol: A formal set of conventions governing the format and relative timing of message exchange between two communicating processes.
PSTN (Private Switched Telephone Network): Generic term for European
telephone carriers.

G-14 • Glossary

quadword: Eight cootiguous bytes (64 bits) starting at an addressable-byte
boundary.
queue: (n.) A citcular, doubly linked list. (v.) To make an entry in a list or
table.
RAM (Random Access Memory): Memory that can both be read, and written into (i.e.;' altered) during normal operation. RAMis th~ type of memory
used in most computers to store the instructions of programs currently being

run.
read-access type: An instruction- or procedure-operand attribute indicating
that the specified operand is only read during instruction or procedure execution.
realtime: Refers to computer systems or programs that perform a computation during the actual time that a relatedphysical process transpites.
ReGIS (Remote Graphics Instruction Set): Digital's graphics command
interface to terminals for putting Shapes on the terminal screen.
register: A storage location in hardware logic other than main memory. See

also general register; processor register; device register.
register-deferred indexed mode: Anindexed-addressing mode in which the
base-operand specifier uses register-deferred mode addressing.
register-deferred mode: In register-deferred mode addressing, the contents
of the specified register are used as the address of the actual instruction operand.
register mode: In register-mode addressing, the contents of the specified register are used as the actual instruction operand.
remote: Communications between computer and terminals via switched
lines such as telephone lines.
reverse video: A feature on a display unit that produces the opposite cOmbination of characters and background from that which is usually employed,
that is, white characters on a black screen, if having blackchar~ters on a
white screen is normal.

data

ROM (Read-only Memory): Memory containing fiXed
or instructiotis
that is permanently loaded during the manufacturing proc~ss.
scrolling: When a video terminal's screen is full, a new line of data cart be
displayed by adding it at the bottom of the screen and Shifting all the' previous
lines upward, discarding the top line. When the upward movement is continuous rather than in line steps, it is called smooth scrolling.
serial transmission: A method of information transirtissioo'inwhich each bit
of information is sentsequential1y on a single path rather than simultllneously
as in parallel transmission.

G-15

SNA (System Network Architecture): A network architecture of IBM.
software: A set of computer programs, procedures, rules and associated documentation concerned with the operation of network computers (i.e., compilers, monitors, editors, utility programs).
software interrupt: An interrupt generated on processor-priority levels that
can be requested only by software.
stack: An area of memory set aside for temporary storage or for procedureand interrupt-service linkages.
stack frame: A standard data structure built on the stack during a procedure
call, starting from the location addressed by the frame pointer and going to
lower addresses, and popped off during a return from procedure. Also called
call frame.
stack pointer (SP): A general register that contains the address of the top
(lowest address) of the processor-defined stack. Reference to stack pointer
will access one of the five possible stack pointers-kernel, executive, supervisor, user, or interrupt-depending on the value in the current mode and interrupt stack bits in the processor status longword.
status code: A longword value that indicates the success or failure of a specific function.
supervisor mode: The third most privileged processor access mode. The operating system's command interpreter runs in supervisor mode.
synchronous: A technique in which data bits are sent at precisely timed intervals. Synchronous channels are capable of higher data rates than asynchronous ones, often running at 56,000 bits per second.
system-address space: See system space.
system space: The higher-addressed half of virtual-address space.
system-virtual address: A virtual address identifying a location mapped by
an address in system space.
system-virtual space: See system space.
terminal: The general name for those peripheral devices that have keyboards
and video screens or printers.
timesharing: A mode of data processing that allows many terminal users to
utilize a computer's resources to perform a variety of tasks simultaneously.
tool kit: The software and hardware components, including documentation,
that are manufactured by Digital to help software developers create application programs that can be fully intergrated into computers.
tractorfeed: An attachment used to move paper through a printer. The roller
that moves the paper has sprockets on each end that fit into the fanfold
paper's matching pattern of holes.

G-16' Glossary

translation buffer: An internal processor cache containing translations for
recently used virtual addresses.
trap: An exception condition that occurs at the end of the instruction that
caused the exception. The program counter saved on the stack is the address
of the next instruction that would normally have been executed. All software
can enable and disable some of the trap conditions with a single instruction.
trap enables: Bits in the processor status word that control the processor's
action on certain arithmetic exceptions.
two's c:omplement: A binary representation for integers in which a negative
number is one greater than the bit complement of the positive number.
typeface: See font.
user mode: The privileges granted a user by the system manager.
variable-length bit field: A set of 0 to 32 contiguous bits located arbitrarily
with respect to byte boundaries.
vector: An interrupt or exception vector is a storage location that contains
the starting address of a procedure to be executed when a given interrupt or
exception occurs. The system defines separate vectors for each interrupting
device controller and for classes of exceptions.
virtual address: A 16-bit or 32-bit integer identifying a byte location in virtual-address space. The memory-management hardware translates a virtual
address to a physical address. The term virtual address may also refer to the
address used to identify a virtual block on a mass-storage device.
virtual-address space: The set of all possible virtual addresses that an image
executing in the context of a process can use to identify the location of an
instruction of data.
virtual memory: The set of storage locations in physical memory and on disk
that are referred to by virtual addresses.
virtual-page number: The virtual address of a page of virtual memory.
word: Two contiguous bytes (16 bits) starting at an addressable-byte boundary.

A
AAV11 realtime interface, 3-20
absolute links (in queue data), 6-28
ac power, B-5-B-6
ACMS, VAX, 4-28
acoustics, B-6
Ada, VAX (language), 4-24
address space, 6-6-6-11
addresses, for data items, 6-28
ADE (Application Development
Environment),4-30
ADV11 realtime interface, 3-20-3-21

argument pointer, 6-14
arithmetic exceptions, 6-16
asynchronous communications
with DECmate II and III, 5-24
interfaces for, 3-17-3-18
links for, 5-13-5-16
on Q-bus, A-I
autodecrement-deferred mode,
6-17-6-20
autodecrement mode, 6-17-6-20
autoincrement-deferred mode,
6-17-6-20
autoincrement mode, 6-17-6-20
AXV11 realtime interface, 3-21

Advanced Programmer's Kit (Micro/
RSX),4-9
air contamination, B-3
analog input/output module, AXV11,
3-21
APL, VAX, 4-24

B
backplane assembly (8-slot), 2-16-2-17,
2-19

Apple PC connection, 5-24

layout of, B-7-B-9

Application Development Kit
(Micro/RSTS),4-12

module space requirement for,
B-12-B-13

applications, see software
architecture

wiring of, A-37-A-38
backplane assembly (12-slot), 2-10-2-12

of addressing modes, 6-17-6-20

layout of, B-7-B-9

data types in, 6-25-6-28

module space requirement for,
B-12-B-13

exceptions and interrupts in, 6-21
instruction sets in, 6-28-6-57
of memory and address space,
6-6-6-11
of MicroPDP-11 systems, 6-5-6-6
of MicroVAX systems, 6-4-6-5

wiring of, A-37-A-38
backplane assembly (14-slot), 2-22-2-23
layout of, B-7-B-9
module space requirement for,
B-12-B-13
wiring of, A-37-A-38

processor operating modes in,
6-22-6-24

Base Kit (Micro/RSX), 4-9

of registers and stacks, 6-12-6-16

base registers, 6-12

of supermicrosystems, 1-3

Base System Kit (Micro/RSTS), 4-12

Index 2

base systems (configuration), 2-28

BASIC, 4-21
BLISS-32, VAX, 4-24
block mode, A-20
Blue Chip Program, C-1-C-2
Bourne shell, 4-4, 4-13, 4-31
BREF signal, A-33
buffers
for KDJll-BB CPU module, 2-7
for KDJll-BF CPU module, 2-6
bus (Q-bus; Q22_bus)

C,4-21
in ULTRIX-ll, 4-13
in ULTRIX-32m, 4-4
cabinet enclosure, 2-21-2-27
cables
connected to I/O distribution panel,
2-13
space for, B-2
cache memory

communications on, A-1-A-4

on KD32-AA CPU module set, 2-2

configurations of, A-38-A-43

on KDJll-BB CPU module, 2.-7

control functions on, A-33-A-34

on KDJll-BF CPU module, 2-6

data transfer cycles on, A-5-A-15
electrical characteristics of,
A-35-A-37

Carrier Sense-Multiple Access with
Collision Detection (CSMAjCD)
access method, 5-12

interconnect wiring on, A-37-A-38

cartridge tape drives

interrupts on, A-23-A-32
pin identifiers on, A-44-A-52

see Q-bus

TK25,3-12-3-13
TK50,3-12-3-13
CD Reader, 3-15-3-16

bus drivers, A-35-A-36

CD ROM, 3-15-3-16

bus mastership acquisition phase,
A-16-A-17

CDD, VAX (Common Data Dictionary),
seeVAXCDD

bus mastership relinquish phase,
A-16-A-17

central processing units (CPUs)
KA630-AA CPU module, 2-3-2-4

bus networks, 5-8

KD32-AA CPU module set, 2-4-2-5

bus receivers, A-36

KDFll-BF CPU module, 2-7---'2-8

bus termination, A-36-A-37

KDJll-BB CPU module, 2-6-2-7

bytes, 6-25

KDJll-BF CPU module, 2-5-2-6
character sets
on LA100, 3-31
on LA12, 3-32---'3-33
on LA120, 3-30
on LA210, 3-25, 3-28
on LA50, 3-31-3-32
on LN03, 3-33
on LQP03, 3-28-3-29
character-string data, 6-26-6-27

Index 3

chassis
for cabinet enclosure, 2-21-2-27

compatibility
of KDFll-BF CPU module, 2-8

for fIoorstand enclosure, 2-10-2-15

of KDJll-BB CPU module, 2-7

for pedestal enclosure, 2-16-2-21

of KDJll-BF CPU module, 2-6

for rackmount enclosure, 2-16-2-21

Concise Command Language (CCL), 4-12

for system enclosures, 2-8

condition codes, 6-16

for tabletop enclosure, 2-16-2-21

configurations
of base systems, 2-28

clock, KWVll programmable
clock/counter, 3-21

of Ethernet, 5-10-5-13

COBOL,4-22

of network, 5-6-5-9

Code Management System (VAX DEC/
CMS), see VAX DEC/CMS

of Q-bus, A-38-A-43
for Q-bus interrupts, A-29-A-32

color

of packaged systems, 2-28

on LCPOl color printer, 3-34-3-35
on VT241 graphics terminal, 3-24
Common Data Dictionary (VAX CDD),
see VAX DEC/CMS
Common Language Environment (CLE),
4-2
communications
asynchronous, 5-13-5-16
asynchronous interfaces for,
3-17-3-18
DECnet, 5-20-5-21, 5-23
Ethernet for, 5-9-5-13
Internet, 5-21-5-22
modems for, 3-36-3-38
options for supermicrosystems,
3-1-3-39
Packetnet, 5-22
on Q-bus, A-I-A-4
realtime interfaces for, 3-20-3-21
in RT-ll, 4-16

of standard systems, 2-28
of system building blocks, 2-28
console emulation
on KDFll-BF CPU module, 2-8
on KDJll-BB CPU module, 2-7
on KDJll-BF CPU module, 2-6
console terminal, space for, B-2
context switching, 6-22
control functions on Q-bus, A-33-A-34
control panels
on cabinet enclosure chassis, 2-22,
2-26
on fIoorstand enclosure chassis, 2-10,
2-13-2-14
on pedestal enclosure chassis, 2-16,
2-20
on rackmount enclosure chassis, 2-16,
2-20
on tabletop enclosure chassis, 2-16,
2-20

software for, 4-33

CORAL-66, 4-22

in standalone systems, in networks,
5-1-5-3

CTS-300, 4-15
customer services

synchronous, 5-16-5-20

Educational Services, C-9-C-12

synchronous interfaces for,
3-18-3-20

Field Service, C-1-C-5

see also networks
comparison, of KDJll-BB and KDJll-BF
CPU modules, 2-7

Software Services, C-5-C-9

Index 4

D
daisywheel printer, LQP03, 3-28-3-29
database management system, VAX.
Rdb/ELN,4-29
data dictionary, VAX CDD (Common
Data Dictionary), 4-29
data link layer (DNA), 5-5
data-path module (DAP), 2-5
data terminal emulator, in Micro/RSX,
4-9
data transfer bus cycles, A-5-A-15
data transfer phase, A-16-A-17
data transmission, see communications
DATATRIEVE, 4-27
data types, 6-26-6-28
DATBI bus cycle, A-20-A-21
DATBO bus cycle, A-21-A-23
DATI bus cycle, A-7-A-1O
DATIO(B) bus cycle, A-13-A-15
DATO(B) bus cycle, A-I0-,-A-13
debuggers
in MicroVMS, 4-3
for VAXELN, 4-6
DEC/CMS (Code Management System),
VAX, see VAX DEC/CMS
DECgraph, 4-27
decimal-string data, 6-27
DECmail-ll,4-27
DEC/MMS (Module Management
System), VAX,see VAX DEC/MMS
DECnet
communications software for,
5-20-5-21
Packetnet System Interface used
with,5-22
DECOR, VAX, see VAX DECOR
DEC/Shell, VAX, see VAX DEC/Shell
DECslide, VAX, see VAX DECslide
DEC/Test Manager, VAX, see VAX
DEC/Test Manager
DELNI Ethernet concentrator, 5-13

DEQNA Ethernet interface, 3-18-3-19
development tool kits
MicroPower/pascal,4-12
VAXELN,4-4-4-7
device addressing, by Q-bus, A-7
device drivers
in MicroVMS, 4"3
in VAXELN, 4-5, 4-7
device priority, A-24
DFI00 modem enclosure, 3-38-3-39
DFI12 modem,. 3-36-3-37
DF124 modem, 3-37
D floating-point data type, 6-25-6-26
DHVll asynchronous interface, 3-17
DlBOL, see DlBOL-83
DlBOL-83, 4-22
dictionary, VAX CDD (Common Data
Dictionary), see VAX CDD
Digital Command Language (DCL)
in MicroVMS, 4-2
in RSTS/E, 4-12
in RSX-ll family of operating
systems, 4-9
in RT-ll, 4-15
Digital Network Architecture (DNA)
communications software for, 4-33
DEQNA interface for, 5-5
network software for, 5-20-5-22
see also networks
Digital PC connection, 5-24
Digital Standard MUMPS (DSM), 417-4-19
digital-to-analog converter, AAVll, 3-20
direct-memory access (DMA)
DMA protocol for, A-16, A-19
guidelines for, A-23
on Q-blis, A-16-A-23
directories
in ULTRIX-ll, 4-13
in ULTRIX-32m, 4-4

Index 5

disk controllers

documentation

KDA50,3-5

for architecture, 6-58

RQDX1,3-4-3-5

for hardware, 2-29

RQDX2,3-4-3-5

for networks, 5-25

RQDX3,3-4-3-5
disk drives
installation of, B-7
KDA50 controller for, 3-5
RA60, 3-9-3-10
RA81,3-8-3-9

for software, 4-33
for Q-bus, A-52
for site preparation and installation,

B-15
for system options, 3-39
dot-matrix printers

RC25,3-11

LA 100, 3-31

RD51,3-7-3-8

LA12,3-32-3-33

RD52,3-7

LA120, 3-30

RD53,3-7

LA210, 3-25, 3-28

RQDX1 controller for, 3-4-3-5
RQDX2 controller for, 3-4-3-5
RQDX3 controller for, 3-4-3-5
RX50, 3-6
displacement-deferred mode, 6-17-6-20
displacement mode, 6-17-6-20
displays
on VT220 video terminal, 3-23
on VT240 graphics terminal, 3-233-24
on VT241 graphics terminal, 3-233-24
,distributed arbitration, A-24
distributed processing, 5-1
DLVE1 asynchronous interface, 3-18
DLVJ1 asynchronous interface, 3-18
DMA protocol, see also direct-memory
access
DMV11 synchronous interface, 3-19

LA50, 3-31-3-32
double-precision D floating-point data,
6-26
DPV11 synchronous interface, 3-19
DRV11-JP realtime interface, 3-20
DRV11-WA realtime interface, 3-20
DSM (Digital Standard MUMPS), see
Digital Standard MUMPS (DSM)
DZQ 11 asynchronous interface, 3-17

Index 6

E
editor, KED/KEX, 4-15

F
fans

Educational Services, C-9-C-12

for cabinet enclosure, 2-22, 2-27

EIA standard signals, 5-13-5-16

for floorstand enclosure, 2-10, 2-12,
2-15

electrical characteristics
of Q-bus, A-35-A-37
of interconnect wiring, A-37-A-38

for pedestal enclosure, 2-6, 2-19,
2-21

Electrical Industries Association (ElA),
5-13

for rackmount enclosure, 2-6, 2-19,
2-21

electrical interference, B-14

for tabletop enclosure, 2-6, 2-19,
2-21

electromagnetic shielding, 2-13
electronic mail, DECmail-ll, 4-27
enclosures
cabinet enclosure, 2-21-2~27
DF100 modem enclosure, 3-38-3-39
floorstand enclosure, 2-10-2-15.
pedestal enclosure, 2-16-2-21
rackmount enclosure, 2-16-2-21
tabletop enclosure, 2-16-2-21
end communications layer (DNA), 5-5
environment, site preparation of,
. B-3-B-4
Ethernet

F floating-point data type, 6-25-6-26
Field Service, C-1-C-5
file management
in Digital Standard MUMPS, 4-17
inUITRIX-ll,4-13
in ULTRIX-32m, 4-4
file transfer utility, in MicrojRSX, 4-9
fixed-disk drives
RA81, 3-8-3-9
RD51,3-7-3-8
RD52,3-7-3-8
RD53,3-7-3-8

DEQNA synchronous interface for,
3-18-3-19

fixed/removable-disk drive, RC25, 3-11

links for, 5-9-5-13

floating point

RT-ll handlers for, 4-16
exceptions, 6-20-6-22
executive mode, 6-23

flexible-disk drive, RX50, 3-6
data in, 6-25-6-26
FPF11 floating:point accelerator for,
3-3
KEF11-AA floating-p6intprocessor
for, 3-3
in MicroPDP-11 systems, 6-25~6-26
in MicroVAX systems, 6-25-6-26
floorstand enclosure, 2-1, 2-10, 2-15
FMS (Forms Management System), 4-28
fonts, see character sets
Forms Management System (FMS), see
FMS
FORTRAN, 4-22-4-23
FPF11 floating-point accelerator, 3-3
frame pointer, 6-14

Index 7

G
general registers
MicroPDP-ll addressing modes for,
6-19-6-20
MicroVAX addressing'modes for,
6-17-6-18

see also registers
G floating-point data type, 6-25-6-26
graphics

I
IBM systems
communications with, 1-3
Digital PC connection with, 5-24
Internet communications with,
5-21-5-22
INDENT, 4-28
index-deferred mode, 6-17-6-20
index mode, 6-17-6-20

DECgraph for, 4-27
kernel system (VAX GKS/Ob) for,
4-32

indicator lights, on control panel,
2-13,2-20,2-26
information management software

on LCP01, 3-34-3-35

DATATRIEVE, 4-27

on VT240 graphics terminal,
3-23-3-24

DECgraph, 4-27

on VT241 graphics terminal,
3-23-3-24

H
H4000 Ethernet transceiver, 5-9-5-13
fL\LTfunction,l\-33
hardware

DECmail-ll,4-27
FMS (Forms Management System),
4-28
INDENT, 4-28
RMS (Record Management System),
4-28
VAX l\CMS (l\pplication Control
and Management System), 4-28

central processing units, 2-1 ~2-8

VAX CDD (Common Data
Dictionary),4-29

communications interfaces,
3-17-3-21

VAX PRODUCER, 4-29

configurations of, 2-27-2-28
of Digital Network J\rchitecture,
5-5-5-6
documentation for, 2-29
enclosures, 2-8-2-27

Vl\X DECslide, 4-29
VAX Rdb/ELN (Relational Database
Management System), 4-29
VAX TDMS (Terminal Data Management System), 4-30
VAX VTX (Videotex), 4-30

memory options, 3-1-3-2

initialization function, 1\-33

modems, 3-36-3-39

installation

printers and printing terminals,
3-25-3-26
storage of, B-6
storage options, 3-3-3-16
video and graphics terminals,
3-23-3-24
H floating-point data type, 6-25-6-26
high-level languages, see languages
humidity of environment, B-3

of hardware, B-1-B-14
of software, C-5-C-9
instruction-execution privileges, 6-22

Index 8

instructions and instruction sets

for floating-point data, 6-25-6-27
KEFl1-BB character-string instruction set, see KEFll-BB
MicroPDP-ll systems, 2-5, 2-6, 2-7,
2-8, 6-25-6-27
MicroVAX, 2-3, 6-25-6-27
integer data, 6-25-6-28
interconnect wiring, for Q-bus,

A-37-A-38
interfaces
asynchronous, 3-17-3-18
DEQNA,5-9-5-13

KA630-AA CPU module, 2-1, 2-2, 2-32-4
KDA50 disk controller, 3-5
KD32:AA CPU module set, 2-1, 2-2,
2-4-2-5
KDFll-BF CPU module, 2-1, 2-2, 2-72-8
KDJll-BB CPU module, 2-1, 2-2, 2-62-7
KDJll-BF CPU module, 2-1, 2-2, 2-52-6

Packetnet, 5-22

KED/KEX keypad editor, 4-15

realtime, 3-20-3-21

KEFll-AA floating-point processor, 3-3

synchronous, 3-19-3-20

KEFll-BB character-string instruction

see also Q-bus
International Consultative Committee on
Telegraphy and Telephony (CCITT),
5-13

set, 3-3
kernel mode, 6-23
KMVll synchronous interface, 3-20
KWVll realtime interface, 3-21

International Standards Organization
(ISO),5-4
Internet, 4-33

interrupts
processor, 6-21
on Q-bus, A-23-A-32
I/O distribution panel

LA100 (Letterprinter 100 and
Letterwriter 100), 3-31
LA12 Correspondent printer, 3-32-3-33

for cabinet enclosure, 2-10,
2-26-2-27

LA120 DECwriter III printer, 3-30

for floorstand enclosure, 2-10,
2-13-2-14

LA50 personal printer, 3-31-3-32

for pedestal enclosure, 2-16,
2-20-2-21
for rackmount enclosure, 2-16,
2-20-2-21
for tablerop enclosure, 2-16,
2-20-2-21
inserts on, B-14

LA210Letterprinter, 3-25-3-28

Index 9

languages

<available for MicroVMS, 4-2
'BASIC, 4-21
C,4-22
COBOL,4-15
CORAL-66, 4-22
DIBOL-83,4-22
FORTRAN,4-22-4-23
MACRO-11, 4-9, 4-12
MUMPS, 4-23
Pascal, 4-23
VAX Ada, 4-7, 4-24
VAX APL, 4-24
VAX BLISS-32, 4-24
VAX PL/I, 4-24
VAX RPG II, 4-25
laser printer, LN03, 3-33
LCP01 color printer, 3-34-3-35

MACRO-11, 4-9, 4-12
maintenance
for hardware, C-1-C-5
for software, C-5-C-9
markets for supermicrosystems, 1-1
master/slave relationship, on Q-bus, A-2
memory-access privileges, 6-22
memory
in KA630-AA CPU module, 2-3
in KD32-AA CPU module, 2-4-2-5
in KDF11-BF CPU module, 2-8
in KDJ11-BB CPU module, 2-6-2-7
in KDJ11-BF CPU module, 2-5-2-6
options for, 3-1-3-2
storage options for, 3-3-3-16
memory management

Letterprinter 100 (LA 100), see LA 100

in MicroPDP-11 systems, 6-8

letter-quality printers

in MicroVAX systems, 6-9-6-10

LQP03,3-28-3-29
Letterprinter 100 (LA100), 3-31
Letterwriter 100 (LA100), see LA100
lighting of environment, B-4
lights, on control panel, see indicator
lights
links in networks
asynchronous, 5-13-5-16
Ethernet, 5-9-5-13
synchronous, 5-16-5-20
LN03iaser printer, 3-33
Local Area Networks (LANs)
DEQNA synchronous interface
for, 3-18-3-19
Ethernet for, 5-9-5-13
logic modules, 2-8, 2-10, 2-11, 2-16,
2-18,2-22,2-24
longwords, 6-25
LP25 system printer, 3-35
LP26 system printer, 3-35-3-36
LQP03 letter-quality printer, 3-28-3-29

memory controller module (MCT),
2-4-2-5
memory options for supermicrosysterns, see memory
MENU-H,4-31

Index 10
MicroFDP:ll/23
addressing modes in, 6-17, 6-19.-6-20

MicroPDP-ll/83

\ addressing modes in, 6-17, 6-19-6-20

address space in, 6-6-6-8

architecture of, 6-1-6-58

configurations of, 2-28

data types on, 6-25-6-28

data types on, 6-25'-:6-28

documentation for, D-1-D-J

documentation fOl; D-1-D-3

enclosure for, 2-16

enclosures for, 2-10, 2-21

instruction set for, 6-29-6,57

instruction set for, 6-29-6-57

KDFll-BF CPU module for, 2-1, 2-2,
2-7-2-8

KDJll-BF CPU module for, 2-1, 2-2,
2-5-2-6

memory management in, 6-8-6-9

operating modes of, 6-22-6-24

performance options for, 3-3

processor-priority levels on, 6-2, 6-22

processor-priority levels on, 6-2,
6-22

registers in, 6-12, 6-15-6-16
software, 4-8-4-33

registers in, 6-12, 6-15-6-16

MicroPower/Pascal, 4-12-4-13

software for, 4-8-4-33

Micro/RSTS, 4-12

MicroPDP-ll/73
addressing modes in, 6-17, 6-19-6-20
address space in, 6-6-6-8
architecture o( 6-1-6-58
configurations of, 2-28

Micro/RSX, 4-9
microsystems, see supermicrosystems
MicroVAX argument pointer, see argument pointer

data types on, 6-25-6-28

MicroVAX frame pointer, see frame.
pointer

documentation for, D-1-D-3

MicroVAXI

enclosure for, 2-16

addressing modes in, 6-17-6-18

instruction set for, 6-29-6-57

address space in, 6-6-6-8

KDJll-BB CPU module for, 2-1, 2-2,
2-6-2-7

architecture of, 6-1-6-58

memory management in, 6-8-6-9

data types on, 6-25-6-28

operating modes of, 6-22-6-24

documentation for, D-1-D-3

processor-priority levels on, 6-2, 6-22

enclosure for, 2-16

registers in, 6-12, 6-15-6-16

instruqion set for, 6-28-,--6-57

software for, 4-8-4-33

KD32-AA CPU inoduleset for, 2-1,
2-2,2-4-2-5

configurations of, 2-28

memory management in, 6-8-6-10
operating modes of, 6-22-6-24
processor-priority levels on, 6-2, 6-22
registers in, 6-12-6-15
software for, 4-1-4-33

Index 11

MicroVAXII

MSVll-Q memory modules, 3-2

78132 floating-point chip, 2-3

multidrop (multipoint) networks,
5-7-5-8

addressing modes in, 6-17-6-18

multiplexers, 3-17-3-18

address space in, 6-6-6-8

multitasking applications

78032 microprocessor chip, 2-3

architecture of, 6-1-6-58

KA630-AA CPU module for, 2-3

configurations of, 2-28

KD32-AA CPU module set for, 2-4

data types on, 6-25-2-28

KDFll-BFCPU module for, 2-7

documentation for, D-l-D-3

KDJll-BB CPU module for, 2-6

enclosures for, 2-10, 2-16, 2-21

KDJll-BF CPU module for, 2-5

instruction set for, 6-28-6-57

MicrofRSTS for, 4-12

KA630-AA CPU module for, 2-1, 2-2,
2-3-2-4

Micro/RSX for, 4-9
multiuser applications

memory management in, 6-8-6-10

CTS-300 for, 4-15-4-17

operating modes of, 6-22-6-24

DSM (Digital Standard MUMPS) for,
4-17-4-18

processor-priority levels on, 6-2, 6-22
registers in, 6-12-6-15
software for, 4-1-4-33
MicroVAX processor status longword
(PSL), see processor status longword

KA630-AA CPU module for, 2-3
KD32-AA CPU module set for, 2-4
KDFll-BF CPU module for, 2-7
KDJll-BB CPU module for, 2-6

MicroVAX program counter, see program
counter

KDJll-BF CPU module for, 2-5

MicroVAX stack pointer, see stack pointer

Micro/RSX for, 4-9

MicroVMS operating system, 4-1-4-3

RSTS/E for, 4-11
RSTS family for, 4-10

modems

Micro/RSTS for, 4-12

DF100 modem enclosure, 3-38-3-39

RSX-llM-PLUS for, 4-9-4-10

DF112,3-36-3-37

in standalone systems, in networks,
5-2-5-3

DF124,3-37-3-38
inLA12,3-32-3-33
in networks, 5-4
for synchronous links, 5-17-5-20
module connector pin identification,
A-42-A-43
Module Management System (VAX
DEC/MMS), see VAX DEC/MMS
module space requirements,
B-12-B-13
monitors (in operating systems) in
RT-ll,4-16
MS630mernory modules, 3-1
MSVll-J memory modules, 3-1-3-2
MSVll-P memory modules, 3-2

MUMPS
DSM-ll (Digital Standard MUMPS),
4-17-4-18
as language, 4-23
VAX DSM (Digital Standard
MUMPS),4-9

Index 12

N
network application layer (DNA), 5-5
network-connected systems, 5-3-5-4
network management layer (DNA),
5-5-5-6
networks
communications software for, 4-33
configurations of, 5-6-5-9
on two or more connected systems,
5-3-5-4
Digital Network Architecture for,
5-4-5-6

operating systems
CTS-300,4-15-4-17
DSM (Digital Standard MUMPS),
4-17-4-19
memory management by, 6-8-6-10
MicroPower/Pascal,4-12-4-13
Micro/RSTS, 4-11, 4-12
Micro/RSX, 4-9
MicroVMS,4-1-4-3
RSTS/E,4-11-4-12
RSTS family of, 4-10-4-11
RSX-11 family of, 4-8-4-9
RSX-11M,4-1O

links for, 5-9-5-20

RSX-11M-PLUS,4-9-4-10

Network Planning and Design
Service for, C-7

RT-11,4-15-4-16

RSX-11S,4-10

single-user system interconnections
in, 5-24

ULTRIX-11,4-13-4-15

software for, 5-24

VAX DEC/Shell for, 4-31

of standalone systems, 5-1-5-3

ULTRIX-32m,4-3-4-4

nodes, 5-6-5-9

VAXELN,4-4-4-7
operation code (opcode), 6-28

numbers, data types of, 6-25-6-28

options
communications, 3-17-3-21

o
octawords, 6-25
OEM Portfolio Program, C-1-C-2
offsite services, C-4-C-5
onsite services, C-3-C-4
operating modes, 6-22-6-24

memory, 3-1-3-2
modems, 3-36-3-39
performance, 3-3
printers and printing terminals,
3-25-3-36
storage, 3-3-3-16
video and graphics terminals,
3-21-3-24

p
packaged systems (configuration), 2-28
packed-decimal string operations, 6-27
Packetnet System Interface (PSI), 5-22
pages (memory), 6-9
Partnership Program, C-2
Pascai, 4-23
PC absolute mode, 6-20

Index 13
PC connection, Digital
to Apple systems, 5-24
to Digital systems, 5-24
to IBM systems, 5-24
PC immediate mode, 6-20
PC relative-deferred mode, 6-20
PC relative mode, 6-20
PDP-ll compatibility mode on
MicroVAX II, 4-3
PDP-ll systems
KDFll-BF CPU module compatibility with, 2-8
KDJll-BB CPU module compatibility with, 2-7
KDJll-BF CPU module compatibility
with,2-6
MicroPDP-ll operating systems and,
4-8

power supply
in cabinet enclosure,
2-21-2-22,2-25
in floorstand enclosure,
2-10,2-12-2-13
in pedestal enclosure,
2-16,2-19-2-20
in rackmount enclosure,
2-16,2-19-2-20
in tabletop enclosure,
2-16,2-19-2-20
powerup/powerdown protocol, A-34
printers and printing terminals
LA 100, 3-31
LA12,3-32-3-33
LA 120, 3-30
LA21O, 3-25, 3-28
LA50, 3-31-3-32

pedestal enclosure, 2-16-2-21

LCP01,3-34-3-35

performance, options for, 3-3

LN03,3-33

peripherals, see hardware

LQP03,3-28-3-29

physical-address space, 6-7

LP25,3-35-3-36

physical link layer (DNA), 5-5

LP26,3-35-3-36

physical links

space for, B-2

asynchronous, 5-13-5-16

priority levels

Ethernet, 5-9-5-13

for processor interrupts, 6-22

synchronous, 5-16-5-20

on Q-bus, for devices, A-25

pin assignments for Q-bus, A-3-A-4
pin identifiers for Q-bus, A-44-A-52
PL/I, VAX, see VAX PL/I
position-defined arbitration, A-25
power
loading requirement of, B-1O-B-ll
in site preparation, B-5-B-6
power-status function, A-33

processor HALT function, see HALT
processors
exceptions and interrupts on,
6-20-6-22
KA630-AA CPU module, 2-1, 2-2,
2-3-2-4
KD32-AA CPU module set, 2-1, 2-2,
2-4-2-5
KDFll-BF CPU module, 2-1, 2-2,
2-7-2-8
KDJll-BB CPU module, 2-1, 2-2,
2-6-2-7
KDJll-BF CPU module, 2-1, 2-2,
2-5-2-6
operating modes in, 6-22-6-24
processor status longword (PSL), 6-15

Index 14

processor status word (PSW), 6-16
PRODUCER, VAX, see VAX
PRODUCER
productivity tools

protocols
bus-cycle, A-6
in Digital NetworkArchitecture,
5-4-5-6

ADE (Application Development
Environment) ,4-30

in Internet, 5-21

MENU-11,4-31

in Packetnet System Inte~face, 5-22

VAX DEqCMS (Code Management
System),4-31

powerup/powerdown, A-34

VAX DEC/MMS (Module Management System), 4-31

synchronous, 5-16-5-20

DMA, 3-1, A-16:--A-23

for Q-bus interrupts, A-25-A-29

VAX DEC/Shell, 4-31
VAX DEC/Test Manager, 4-32

VAX DECOR, 4-32
VAX GKS/Ob (Graphics Kernel
System),4-32
VAX Language-Sensitive Editor, 4-32
VAX Performance and Coverage
Analyzer, 4-33

Q-bus (Q22,bus), 1-2
backplane assembly for, 2-11, 2-17,
2-19,2-22-2-23,2-25
communications on, A-1-A-4
configurations of, A-38-A-43

program counter, 6-13, 6-15, 6-20

control functions on, A-33-A-34

program development, in MicroVMS,
4-2-4-3

data transfer cycles on, A-5-A-15

programming languages, see languages

electrical characteristics of,
A-35-A-37

programs

DEQNA interface for, 5-9-5-13

in virtual-address space, 6-8

interconnect wiring on, A-37-A-38