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EK-VAXV2-HB-002

March 1983

347 pages

Original

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Document:	VAX Maintenance Handbook VAX-11/780
Order Number:	EK-VAXV2-HB
Revision:	002
Pages:	347
Original Filename:

OCR Text

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V
~

~..:.

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EK-VAXV2-HB-002

VAX

Maintenance
Handbook
VAX-11/780

1983 Edition

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, August 1982
Second Edition, March 1983

Copyright© 1982, 1983 by Digital Equipment Corporation
All Rights Reserved
The material in this manual is for informauonal purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:
DEC
DECnet
DECsystem-I 0
DECSYSTEM-20
DECwriter
DIBOL

~amanmo

EduSystem
IAS
MINC-I I
OMNIBUS
OS/8
PDP
PDT

RSTS
RSX
TOPS-IO
UNIBUS
VAX
VMS
VT

CONTENTS

CHAPTER 1

INTRODUCTION

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
VAX-11n8o Hardware Manuals . . . . . . . . . . . . . . . . . . . . . . . . . .4
CHAPTER 2

HARDWARE DIAGRAMS

V AX-11 n80 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
KA780 CPU Module Utilization Chart . . . . . . . . . . . . . . . . . . . . . . 8
KA780 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SBI Control Low Bits (SBL) Block Diagram . . . . . . . . . . . . . . . . . 10
SBI Control High Bits (SBH) Block Diagram . . . . . . . . . . . . . . . . . 11
Cache Address Matrix Block Diagram . . . . . . . . . . . . . . . . . . . . . 12
Cache Data Matrix Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 13
Translation-Buffer Data-Matrix Block Diagram . . . . . . . . . . . . . . . 14
Translation-Buffer Address-Matrix Block Diagram . . . . . . . . . . . . . 15
Instruction Buffer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 16
Instruction Decode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 17
Data Path Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Writable Control Store (WCS) Block Diagram . . . . . . . . . . . . . . . . 20
PROM Control Store (PCS) Block Diagram . . . . . . . . . . . . . . . . . . 21
Microsequencer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 22
Console Interface Board Block Diagram . . . . . . . . . . . . . . . . . . . . 23
Floating-Point Accelerator (FPA) Block Diagram . . . . . . . . . . . . . . 24
KA780 TR and System ID Register Jumpers. . . . . . . . . . . . . . . . . 25
KA780 WCS Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

iii

CHAPTER 3

MICROCODE

Control Store Field Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Microcode Routines That Support Console Software
Starting Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Microcode Branch Enable Functions . . . . . . . . . . . . . . . . . . . . . . 31
Microtrap Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Microcode Memory Control Functions . . . . . . . . . . . . . . . . . . . . 34
Scratch Pad Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Control ROM Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 36
System Microcode Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FPA Control Word Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
FPA Control ROM Field Definitions . . . . . . . . . . . . . . . . . . . . . . 74
CHAPTER 4

CONSOLE

CIB 0-Bus Registers (Lower) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CIB 0-Bus Registers (Upper) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Explanation of Version Numbers for Console Booting .......... 87
Console Help File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Console Abbreviation Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Error Message Help File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Console Remote Access Help File . . . . . . . . . . . . . . . . . . . . . . . . 94
Microdebugger Help File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LSl-11 Console ODT Commands . . . . . . . . . . . . . . . . . . . . . . . . 97
Console Subsystem Configuration . . . . . . . . . . . . . . . . . . . . . . . . 99
KD11-F Module Jumper Configuration . . . . . . . . . . . . . . . . . . . 100
MSV-11B Module Jumper Configuration . . . . . . . . . . . . . . . . . . 101
M9400-YE Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . 102
DLV11 Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 103
DLV11-E Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . 104
0-Bus Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Console Boot/Troubleshooting Flow . . . . . . . . . . . . . . . . . . . . . 108

CHAPTER 5

INTERNAL REGISTERS

Processor Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Processor Register Bit Configurations . . . . . . . . . . . . . . . . . . . . 118
ID-Bus Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ID-Bus Register Bit Configurations . . . . . . . . . . . . . . . . . . . . . . 133
Silo Register Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Microcode Machine Check Error Logout . . . . . . . . . . . . . . . . . . 159
Double Error Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
V-Bus Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 161
V-Bus Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
CHAPTER 6

SYSTEM BACKPLANE INTERCONNECT (SBI)

SBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
SBI Parity Field Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 184
SBI Information Transfer Formats . . . . . . . . . . . . . . . . . . . . . . 185
SBI Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
SBI 1/0 Register Addressing and Interrupt Vector Generation .... 189
SBI Faults (Adapter Configuration Register) . . . . . . . . . . . . . . . . 190
SBI Configuration Rules for TR Selection . . . . . . . . . . . . . . . . . 191
SBI Signals, Backplane Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
CHAPTER 7

SBINEXUS

Memory Configuration Register A . . . . . . . . . . . . . . . . . . . . . . 197
Memory Configuration Register B. . . . . . . . . . . . . . . . . . . . . . . 198
Memory Configuration Register C. . . . . . . . . . . . . . . . . . . . . . . 199
Memory Array Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
MS780 Configuration for Rev H Backpanel . . . . . . . . . . . . . . . . 201
MS780A Module Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 202
MS780C Module Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Memory 1/0 Data Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
UBA Address Space and C/A Format . . . . . . . . . . . . . . . . . . . . 207
UBA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
DW780 (UBA) Backpanel Jumper Configuration . . . . . . . . . . . . . 211

SBI to UNIBUS Control Address Translation . . . . . . . . . . . . . . . 212
UNI BUS to SBI Address Translation . . . . . . . . . . . . . . . . . . . . . 213
Addresses and Vectors for UNI BUS Devices . . . . . . . . . . . . . . . . 214
Floating Vectors and Floating Addresses . . . . . . . . . . . . . . . . . . 215
UNI BUS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
DW780 (UBS) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 218
Simplified Flow of Major Control Functions Within the UBA .... 219
Standard and Modified UNI BUS Pin Assignments . . . . . . . . . . . . 220
UNI BUS Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 221
DW780 Module Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MBA Registers - Base Addresses and Bit Configurations ........ 224
RH780 (MBA) Backpanel Jumper Configuration . . . . . . . . . . . . . 228
MASSBUS Disk Drive Register Address Calculation Chart ....... 229
MASSBUS Signal Cable Pin Assignments . . . . . . . . . . . . . . . . . . 230
RH780 Module Utilization Chart . . . . . . . . . . . . . . . . . . . . . . . 232
MBA (RH780) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 233
MA780 Multi port Memory Registers . . . . . . . . . . . . . . . . . . . . . 235
MA780 Array Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
MA780C Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
MA780A Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
MA780 Backplane Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
M8210 Memory Array Card Mnemonics . . . . . . . . . . . . . . . . . . . 242
M8212 Data Path/ECC Card Mnemonics . . . . . . . . . . . . . . . . . . 244
MA780 Multiport Memory Block Diagram . . . . . . . . . . . . . . . . . 246
MA780 Multiport Memory Interface Module (M8258)
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
MA780 Multiport Memory Controller Module (M8259)
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
MA780 Multiport Memory Array Timing and Control Module
(M8260) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
MA780 Multi port Memory Synchronizer Module (M8261)
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
MA780 Multi port Memory Invalidate Map Data Path
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
MA780 Multiport Memory Interlock Arbiter Block Diagram ..... 252
MA780 Multiport Memory Data Path/ECC Module (M8212)
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

DR780 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
DR780 TR Arbitration Jumper and Wirewrap Selection . . . . . . . . 256
DR780 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
DR780 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
SBI Control (DSC) M8296 . . . . . . . . . . . . . . . . . . . . . . . 259
Control Board (DCB) M8297 . . . . . . . . . . . . . . . . . . . . . . 260
Microprocessor (DUP) M8298 . . . . . . . . . . . . . . . . . . . . . 261
Silo Module (DSM) M8299 . . . . . . . . . . . . . . . . . . . . . . . 262
Cl780 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Cl780 Backplane Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Cl780 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
CHAPTER 8

PROCESSOR-SPECIFIC DIAGNOSTICS

Microdiagnostic Monitor Commands . . . . . . . . . . . . . . . . . . . . . 271
Mlcrodiagnostic Pseudo-Instruction Definitions . . . . . . . . . . . . . . 278
Microdiagnostic Control ROM Field Definitions . . . . . . . . . . . . . 290
CHAPTER 9

MISCELLANEOUS

VAX-11/780 Integrated Circuit Diagrams . . . . . . . . . . . . . . . . . 335
25S10 Four-Bit Shifter Chip with Tristate Output ........ 335
26S10 Bus Transceiver Chip . . . . . . . . . . . . . . . . . . . . . . 336
74LS181 ALU Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
74182 Lookahead Carry Chip . . . . . . . . . . . . . . . . . . . . . 338
74LS670 4 X 4 Register File Chip . . . . . . . . . . . . . . . . . . 339
82S23, 82S123 256-Bit Bipolar PROM Chip . . . . . . . . . . . . 340
85S68 64-Bit Edge-Triggered D-Type Register File Chip
with Tristate Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
DEC 8646 Four-Bit Tristate Backplane Interconnect
Transceiver Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
93406 1024-Bit ROM Chip . . . . . . . . . . . . . . . . . . . . . . . 343
9403 Fl FO Buffer Chip . . . . . . . . . . . . . . . . . . . . . . . . . 344
DC101 Arbitrator Chip. . . . . . . . . . . . . . . . . . . . . . . . . . 345
DC003 Interrupt Chip . . . . . . . . . . . . . . . . . . . . . . . . . . 348
DC004 Protocol Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
DC005 Transceiver Chip . . . . . . . . . . . . . . . . . . . . . . . . . 350

vii

CHAPTER 1

INTRODUCTION

CHAPTER2

HARDWARE DIAGRAMS

CHAPTER3

MICROCODE

CHAPTER4

CONSOLE

CHAPTERS

INTERNAL REGISTERS

CHAPTER&

SYSTEM BACKPLANE INTERCONNECT

CHAPTER7

SBINEXUS

CHAPTERS

PROCESSOR-SPECIFIC DIAGNOSTICS

CHAPTER9

MISCELLANEOUS

CHAPTER 1
INTRODUCTION

INTRODUCTION

The purpose of the VAX Maintenance Handbook is to provide a
compact, quick-reference source of troubleshooting, maintenance,
operating, and programming information that is frequently
referenced by DIGITAL field service, manufacturing, training, and
engineering personnel.
This second volume of the VAX Maintenance Handbook is
exclusively to information on the VAX-11/780 processor.

devoted

VAX-11/780 HARDWARE MANUALS

Title

Document Number

VAX-11/780 Power System Technical Description

EK-PS780-TD-001

VAX-11/780 System Installation Manual

EK-SI980-IN-001

DS780 Diagnostic System User's Guide

EK-DS780-UG-001

DS780 Diagnostic System Technical Description

EK-DS780-TD-002

FP780 Floating-Point Processor Technical
Description

EK-FP780-TD-001

REP05/REP06 Subsystem Technical Documentation

EK-REP06-TD-001

VAX-11/780 Central Processor Technical
Description

EK-KA780-TD-001

VAX-11/780 Memory System Technical Description

EK-MS780-TD-00

DW780 UNIBUS Adapter Technical Description

EK-DW780-TD-001

KC780 Console Interface Technical Description

EK-KC780-TD-001

VAX-11/780 Software Handbook

EB08126

VAX-11/780 Architecture Handbook

EB07466

VAX-11/780 Multiport Memory Subsystem

E7-MA780-TD-001

DR780 General Purpose Interface User's Guide

EK-DR780-UG-001

VAX-11/780 TB, Cache, SBI Control Technical
Description

EK-MM780-TD

VAX-11/780 RH780 Technical Description Manual

EK-RH780-TD

VAX Diagnostic System User's Guide

EK-VXllD-UG-001

Hardcopy manuals can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
Attention: Printing and Circulation Services (NR2/Ml5)
Customer Services Section
For information concerning microfiche libraries, contact:
Digital Equipment Corporation
Micropublishing (E46)
12 Crosby Drive
Bedford, MA 01730

CHAPTER 2
HARDWARE DIAGRAMS

VAX-11/780 BLOCK DIAGRAM

CENTRAL PROCESSING UNIT

I CPU

I WITH FULL

I FLOATING POINT,
WCS I DECIMAL, AND
I CHARACTER STRING
_
CONSOLE
SUBSYSTEM

I
I
FPA I
I

.1..l!!:>~U.:!~N~ _

CACHE MEMORY

-----..--..----- - j

PORT FOR

LSl-11

MEMORY

REMOTE

MICRO-

CONTROLLER

DIAGNOSIS

COMPUTER

Ir---, r--,
iii
V)

r--1 256KB

; MEMORY

--!CONTROLLER~-~ ECC Mos I
L _ _ _ _J
L __ j

I
L --- --- - - ---

rvomsrus -- -- ---.
I1
( 1.5 MB/sec)

UNIBUS
ADAPTOR

(2.0 MB/sec)

(13.3

MASS BUS

MB/sec)

FPA=FLOATING POINT ACCELERATOR
WCS= WRITABLE CONTROL STORE

UNIBUS

ADAPTOR

L_ _

MASSBUS

I
I
J

KA780 CPU MODULE UTILIZATION CHART

MODULE UTILIZATION KA780
29

M8236

M8289

CIB
FCT

M8288

FAD

M8287

FML

M8286

FMH

M8285

FNM

M8235

USC

M8234

PCS

M8233 or M8238

wcs

M8233 or M8238

ocs
CLK

•
•
•
•
•

21
20
19
18

•

17
16

M8232

M8231

ICL

M8230

CEH

M8229

OAP

M8228

DCP

M8227

DDP

M8226

DEP

M8225

DBP

M8224

IRC

M8223

IDP

M8222

TBM
COM

M8221

M8220

CAM

M8219

SBH

M8218

SBL

M8237

TRS

NOT INSTALLED USE
• WHEN
BLANK MODULE 7014103
TK-8346

.....

TRANSLATION -----P-'-A'-"B-'-US'-

r-------'S::::B.:...I- - - - - - - - - - , , / TO/FROM MEMORY

(")

BUFFER
REQUEST LEVELS

"ti

(")

");:c
C)

3::
GRD

c.o

VBUS

SBI

SYNCHRONOUS BACKPLANE INTERCONNECT
VIRTUAL ADDRESS LINES

PA BUS

PHYSICAL ADDRESS BUS

MD BUS

MEMORY DATA BUS

ID BUS

INTERNAL DATA BUS

CS BUS

CONTROL STORE BUS

V BUS

VISIBILITY BUS

UPC· MICROPROGRAM COUNTER
GRD

GENERAL REGISTER DATA

FROM

en
~

TBMK 111 091

SBLf
SBLA TRANS DATA 115 00)

SBLE RECEIVE DATA ~15 00)

SBI
XCEIV

BUS SBI 8 (~5 00)

0
rr0

BYTE 1 0 PAA

BUS PA 117 12 08 021

:!!

SBLV

ARB

....::Jlz

ARB OK

LOGIC
TA SEL 8 4 2 1

....~

c;;

m
!:
m

READ DATA

";:0

SBLB J TIMEOUT ADAS l 1 7 02)

SBLN PARITY REG ( 1 5 00)

::Jl

(MISC MAINTENANCE CONDIT!ONSJ
(MISC ERROR CONDITIONSl
SBLN

SBI
ERROR
REGISTER

COM1CAM !Gl GO) BYT(2 0) PAA 00

FROM
CACHE
FROM

COM/CAM (G1GOl183 BOJPAA ODO
TBMN BUF UAOS UFS ,--~..;;.__~
TBMN BUF UMCT ~3 0)
µ.CODE
CONTROL

SBLF ID RECEIVE ( 15 001

SBLS 10 BUFF 115 001

MAINHNANCE
REG1STE R

CACHE
PARITY ERUOR
REGISTER

>
s:

UFS
UADS
FROM TBMN BUFF UMCT 13 01
TB

SSHD
SSHC TRANS DATA 131 161
BUS SBI B 131 161

SBHB

SBI
XCEIV

BUS SBI M 13:01

BUS PA 129 1Bl

SBHA TIMEOUT ADAS 129 161

"
BUS PA 129 181

SBHK

BUS MD 131 161

SBHE

BUS MD BYTE 13·0) MASK

P(10i
FAULT
BUS SBI ID 14:0)

SBHD

ALERT
TAG 1201
UNJAM

BUS MD 131 161

BUS MD BYTE 13 21 PAR
BUS MD BYTE 13.01 MASK

MD
BUS
DRIVER

IWC ADA!

- - - - - - - - - - - - - ! =~~~~~;A l e - - + - - - - - - - - - - '

TO INTERRUPT

' - - - - - - - - - + CONTROL LOGIC

SBHA TIMEOUT ADAS 129: 181
SBHK SILO DATA 128181

REC 17 41 A

llCLI

BUS ID (31 161

58HF
ICU ID RIGHT ADDA 15 01
ICU ID RIGHT WRITE

SBHP

MAINTENANCE
REGISTER
SBHP ID BUFF 131 161

S8HF,K
COMPARATOR
REGISTER

SBHF
FAULT/STATUS
REGISTER
•LOW BITS ARE LOCATED ON TAM

PA
BUS
LATCH

CAMC PA LA.,.CH (11 3)

BYTE
PARITY
CHECK

BUS PA IB 31

CAML GO BYT (2 0) PAR EV OD

TO V BUS ANO
SBI CONTROL

TO CACHE

O JN
CAM6

D OUTl--l----'-------'C"-'A"'-M-"GO::__Tc;.;A:::._G.;.=12.::._8c.:;12"--1CAME VALID 0

c
c

::>
:,

COKPARATOR

>-+~-~--- DATA MATRIX ANO
SBI CONTROL

:lJ

s::

BUS PA 129 121

-4
:lJ

CAM F, HJ

FROM
SBI

>----+~-----

TO CACHE
DATA MATRIX ANO

0
BYTE
CAML G1 BYT (2·0) PAR EV,00
PARITY
CHECK

"'l>c

G')

:lJ
SBHF REV
PAR 12 01

DECODER

USED TO FORCE READ
PARITY ERRORS DURING
DIAGNOSTICS

FROM

SBI cx:M"ROl
{

SBHF REV
PAR 3
CAMS BLOCK WRITE L

CP LECL TJ TO L. H

CLOCK
LOGIC

CAMM CPT (3 0) L H

s::

CDMU

CDMA

CDMO,F,J,K

CDMC

PA
BUS
LATCH

CDMH ADDA LATCH 111 021

SBI CONTROL
LOGIC
DOUT
WP

FROM

t----------- TO V BUS AND

CDMC ADDA LATCH (1 l 02)

CAMP GO WRITE EN H

COMB GO BYTE 13 01 WP L

CACHE
ADDRESS CAMP G1 WRITE EN H
MATRIX

CDMB G1BYTE13 OJ WP L

l>
l>
3::
l>

CDM RD BYTE PAR GO 13 01

-I

BUS MD 131 00)
BUS MD BYTE 13 01 PAR

-I

:::0

x
CD

COME

CDMA G1 (BJ.BO! PAR EVEN. ODD
COME ADDA LATCH 111 021

~~IVC~~~:;~ ~
LOGIC

0
0

;i::

G')

CDMA
CDMA BYTEIJ OJ PAR
CDMA WRITE DATA (31 001
CDMA MASK 13 01 H

CDMU

CP LEG IT3 TOI

CLOCK
LOGIC

CDMU (CPT3 CPTOI

BUS MD BYTE 13 OJ PAR
MD
BUS MD 131 001
DATA
LATCH _ _ _
Bu_s_M_D_B_Y_TE_l3_0_l_M_AS_K_ _ _ _ ____,

:::0

l>
3::

-t

::u
z
Cl)

TO TB CONTROL
I-------~-'--+ LOGIC ANO

TBMK PA MUX SH 0
TBMO VIRT AORS BUFF A

THE SBI CONTROL

TBMA VA MUX (29 141 BUFF
BUS PA ~29 12)

(2912)

~
0

(29 12)

m
.,,c.,,

TBML IPA DATA IN (29 09~

TBMP GRP 0 DATA (29 09)

::u
PA

TO V BUS LOGIC
TBMH G1PAR12 11 EV

c)>

-t

TBMM IPA !29 09!

IPA

-t

TBMR SRP1 DATA 129 09f

::u
x
CD

SBLB SBI PA ( 11 09)

TBMK SH !PA
CAMU TB GAP 0 MATCH
CAMU TB GAP 1 MATCH
VA (08 02J
FROM DATA PATH

TBMN BUS PA 108 02)

FROM

TB ADDRESS _ _ _~'--'---.+
fM.TRIX

FROM
PSL

~"-=---"-=-=--"-=--=~"----.TO PROTECTION
,,___ _ _ _ _ _ CODE LOGIC

TBMC NOT SBI CYCLE
TBMK SH IPA

r0
0

,i;

)>
G'>

::u
)>

VAMX 131

-I
::0

CAMS GO AD PAR
12 01 EV. OD

TBMF GAP 0 WP L

TO V BUS
f-------'"----- LOGIC ANO
TB REGISTER 0

13:91

FROM
DATA
PATHS

CAMU

l-'-"CA~M=S~G=R'--P-=-0-'-'PA-"'R'-"12'-'0'"'-1----icoMPARATOR

~
::!

CAMU TB GAP 0 MATCH

CAMU TB PAR 11 01

Co
c:

DEP VAMX 130 141

'"T1
'"T1

m
CAMV PROTECT 13 01
TBMA VA MUX 130 151 BUFF

TO
TB
DATA
MATRIX

::0

c
c

::0

CAMU

CAMT
t-C,.-A_M_TG~R_P_l_PA_R~l2~0"-I_ _ _ COM PA AA TOA H-'C"-'AM"'-U=-:..:TB:...:G'-"R"'"-P-'--1-"'M;..:.;ATc::.C:_:_H- -

DIN

CAMT GAP 1 ADAS 130 151
G1

DOUT
t-H.,----~---

CAMP

i~
REG

TBMT FORCE ERR 12.01

CAMP DISABLE GO IA2 AOI

TOTS

CAMP DISABLE Gl IA2 AO!

:~~~~S

TBMF GAP 1 WP L

en
en

3::

-I
::0

xca

8
~

;

G')

::0

-t

::XJ

(")

c.,,

.,,

m
::XJ

....

CJ)

(")
~

BUFFER
REGISTER
'--~--.---'"-"-'--~-.-~---~~-.-~~~~-.-~~"'-~--...~~"'-~--...~~~~-....~~~~---.,--~

>
C)

::XJ

IBA 1

IBA 0

1-3

Y1
Y2
MEMORY DATA BYTE SHIFTER (25S10)
1-2
1-1
10
I 1
I2

(/)

-I

:::0

c
::!

IBUF EN 107 00)
!CALL= 31

BUS UPC
07 00

IRCC
IRCE

VAX DECODE 7 O
IRCC
EXECUTION
POINT
COUNTER

SEL EXEC

STALL
TRAP
INTERRUPT.
TB MISS

EXC CT 2 0

INSTRUCTION
BUFFER
REGISTER

..------L-l~D.:,..:PA.;,,_~----1._.:.:IR.:,:C:::;,C_
BYTE 1

BYTE 0

TO
MICROSEQUENCER

cm
n
0
cm
ClJ

r
0

CM DECODE 7 0
CM MODE IVAX)

____ _J

----~s

)>
C)

:::0
)>

SAC MODE

DST MODE

SEL SAC

-t

.,,

)>
)>

-t
J:

C')

,;:

c
)>
C)

:::D

,---

-------1

1 $81 CLOCK

...-'-'OS~C_4X_F_H_ _ _ _ _ _ _~---___;-----------~
TP {ll H

I
I
I
I
I
I

FREQUENCY
GENERATION

OSC2XF1 H
1-0::..:S:.:::C2:_cXc._F1:_:L'-------.i START/STOP/STEP I-=---...< SEOUF:.NCE

t - - o - - o - - + - . - - - - - SBITP L
t - - o - - o - - t - t - , . - - - - + SBIPCLK H

ICLKNI

'<t

ICLKSI

POCLK (0) H

b10 ~0

BRKMAT L ----+->----+--+-----~
FROM MICROSEOUENCER

PROSYNC 111 H
STSSYNC IOI H

'-----v---' '-----v---'
OCLO

ACLO

---

- . C;;;;;ER ;;;:-;-QUENCER

I
SBITP H
SBITP L
SBIPCLK H

SBIPCLK L
SBIPDCLK H
SBIPDCLK L

I
I
I

I
I
I
I
I
I

---1
II

FROM POWER SUPPLIES

I
I
I

SBITP H

POCLK 111 H

ICLKMI

EXT DSC H
EXTERNAL OSCILLATOR

PCLK (1) H

GE NE RATO R 1----l-'-"PC:.e.LK"-"'-IOlc:.H~

._o_sc...c2_x_F2_L_ ___, CONTROL

SELECTION

1--o--o--~-----

TP (0) H

t - - - - - C P U DCLO L

CNSL RESET L OBUS ACLO L

POWER FAIL 1 - - - - • C P U ACLO L
SEQUENCER 1 - - - - + P FAIL INT 111 H
ACLO OR FAIL H

BAT DCLO H
ACK PWA FAIL L

(CLKK, CLKL)

1----•svs INIT H
1----+UPROG INIT H

::::TE::::.l -- -- -- -- -- J

(")

(")
~

3::

c
c:

m
r0

(")
~

C>
:::D

3::

:e:rJ
=i

)>
Cl

. - - - - - - ' - - . - - - - - - - . wcs

E.F.H,J

-4

WCSA

:rJ

0
r-

. - - - - - - - . ! DATA
.-------<SELECTOR

(/)

-4
0

:rJ

WCS ADAS 12 ---+-+-+-+-+4-+-+----_,
WCS ADAS 11 ---t--t-H--H--t--+-----'
WCS ADAS 10 ---+-+-+-+-+4-+-+-------J
WCSA

CS WR 195 641

CS WR rnJ 32)

CS WR l31 001

WCS AORS
09 00

!e
Cl

BUS UPC 11 - - + - - BUS UPC 10--+--~
CLK D E L A Y E D - - + - - - -

"'2

)>
C)

:rJ

3::
J3

"'t7
:::J:J

s:
(")

0
2
-4

BUS CS UPAA 2 0

:::J:J

0
r-

(1)

-4

0
m

:::J:J
32 DATA

~
(")

BUS UPC 12

!'.)

......

BUS UPC 11
BUS UPC 10

32 DATA

!!?
m

DATA
SELECTOR

32 DATA

(")

CLK DELAYED

32 DATA

"2
)>

C)
:::J:J

n
l:J

CS BUS

PROM
CONTROL STORE
IPCS)

WRITABLE
CONTROL STORE

_1w_cs_1_ __,

m
2
(")

V BUS
SERIAL OUTPUT

V BUS CHANNEL 0

SHIFT REGISTER

l:J

I""
VARIOUS
{
CPU
CONDITIONS

USCF

'-----..,--'
MICROSEOUENCER
INPUTS

- - t __ _ ____J

~
c

;;
C>
l:J

DECISION

UPC BREAK REG

uscc
wcs
ADDRESS

CONTROL
USUB REG

ID BUS

- - - - - - - CNSL RESET

- - - - - - R O M NOP, UPC12

0
rm

-I

.,,

::c
)>

O::J

::c

O::J

"52

)>
C)

::c
)>

FAD

FCT M8289 SLOT 28

M8288 SLOT 27

FMH/FM L MB2861M8287 SLOT 251SLOT 26

FNM M8285 SLOT 24

FRACTION MULTIPLIER

FRACTION NORMALIZER

FRACTION ADDER

FPA CONTROL. SIGN PROCESSOR
EXPONENT PROCESSOR

.,,

r
0

>
z
C)

.;,
Q
z
-I

>
0
0

m
r

:J:1

>
-I
0

:J:1

I
I
---~---1

SYSTEM ID BUS

31 00

BUS DFMUX

31 00 ·IT.SI

KA780 TR AND SYSTEM ID REGISTER JUMPERS

vv
Jle

Jll

jj
hh

I
uu

Jl2

Jl3

System ID Register
Remove Jumper to Assert Bit
TR Arbitration Level

Signal
Name

TR
SEL
8

TR
SEL
4

TR
SEL
2

TR
SEL
1

TRI

Jlll
J

Jlll
F

Jlll
D

Jlll
B

Wire Wrap
Fll2M2 to
Fll2Cl
F112Dl
Fll2El
Fll2F2
Fll2H2
Fll2Jl
Fll2J2
Fll2Ml
Fll2Nl
Fll2Pl
Fll2P2
Fll2S2
F02T2
F02Ul
F02U2

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15
16

SYSTEM IDENTIFICATION REGISTER (SID)

NUMBER

LETTER

Bit

Jumper

II
1
2
3
4
5
6
7
8
9
111
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
311
31

Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl3
Jl2
Jl2
Jl2
Jl2
Jl2
Jl2
Jl2
Jl2
Jl2
Jl2
Jl2
Jl2

Signal

VY
TT
RR
NN
LL
JJ
FF
DD
BB

z
x
v
T
R

D
B

TT
RR
NN
LL
JJ
FF
DD
BB

z
x
v

SYSTEM
SERIAL
NUMBER

I
I

MFG
PLANT
ID

}

CPU
CLUSTER
ECO
LEVEL

}

SYSTEM
TYPE
111-11/780
112=?
113=?

KA780 WCS JUMPERS

wcs

Optional WCS
Slot 18
Jll

Slot 20
Jll

0-lK
l-2K
2-3K
3-4K
4-5K
5-fiK
6-7K
7-8K
PCS
Slot 22
Jl2

0-4K

NOTES:
1.
2.

Addresses 0-4K are reserved for PCS.
M8233 starting addresses are in lK increments.
M8238 starting addresses are in 2K increments and begin on
even boundaries only.

CHAPTER 3
MICROCODE

CONTROL STORE FIELD MAP

•
•
06 05 04: 03 02 01 00 I
·--+---.--:-+---·---+-+-+---•--+---+-+--•---+---+---+--•
l
EALU
:
JMP
I
·--+---+--+---•-+---+---+---•---+--+--+---•--+---+---+--•
: 15

•

12: 11

08: 07

•: 31 30 29 2e: 21 26 2s 24: 23 22 21 20:• 19 1e 11 161
·---+---+--+---·---+---+---+---•---+---+···-+---•--+---+---+---·
: IEK :
MSC
:vAKlFEK:scK:
CCK
: EBMX : SMX I
·---+---+---+---•---+---+---+---•---+--+---+---•--+---+---+---·
•
•
34 33 32:
·---+---+--+---·---+--+---+---•--+---+---+---•--+---+---+--•
:Aos:
MCT/CIO
: FSl
SPO
:
PCK
I
·---+---+---+---·---+---+--+---•---+---+---+---•---+---+---+--•
•

: 47

•

: 6J

•

44: 43

so: 59

•

40: 39

36l 35

56l ss

52: s1

761 75

12: 71

68l 67

92: 91

ea: e1

B41 Bl

•

481

64:

eo1

·---+---+--+---•---+---+-+---•--+---+---+---•---+---+---+---•
I
KMX
:
SI/ACM I
OK
:
SGN
l
•---+---+---+---·---+---+---+---·---+---+---+--•---+---+---+---·
•

I 79

•

!I'

•

·---+---+---+---•---+--+---+---•--+---+---+---•---+---+---+---•
:
OT :RMXl
BEN
l ACF I
ALU
: SUB l
•---+---+--+---•---+---+---+---•--+--+---+---•---+---+---+---·
•

: 95

•

·---+---+---+---•---+---+---+---•---+---+---+---•---+---+---+---•
l
IBC
l
DK
:
SHF
I
BMX
I AMX I
•---+---+---+---•
·---•-+---+---+---•---+---+---+-•

MICROCODE ROUTINES THAT SUPPORT CONSOLE SOFTWARE
STARTING ADDRESSES

"CONSOLE MICRO-CODE"

; MICRO-CODE ROUTINES TO SUPPORT CONSOLE SOFTWARE.
;ROUTINES EXPECT DATA IN RX:>B. AND IN ID(T1].ID[T2)
;AND THEY RETURN DATA IN TXDB. STATUS IN ID(D.SV].
;AND ADDITIONAL INFORMATION IN ID[T3].
;PC IS USED WHENEVER R15 IS REFERENCED.
;NO EFFORT IS MADE TO SAVE INTERNAL REGISTERS,
;INFORMATION AND PARAMETERS NHDED FROM THE CONSOLE,
;ARE LOADED IN ID[RXCSJ AND ID[T1J,ID[T2).
;RESULTING DATA IS LO~DED IN ID[TXDB] AND ID[T3].
;AND STATUS INFORMATION IS LOADED IN ID[D.SV].
ROUTINE:

ST ART-ADDRESS:

PARA,\1E T ERS: I• MEANS SUPP LI ED BY CONSOLE)

EXAMINE MEMORY

120

ID[T1 )=BYTE/WORD/LONG-PARAMETER •
ID[RXDB)=VIRTUAL ADDRESS •
ID[ TXDB) =r.:c~:JRY DATA
ID(T3)=PHIS!CAL ADDRESS
ID( D. SV] =ST A TUS-CODE

DEPOSIT MEMORY 121

ID[T1 ]=BYTE/WORD/LONG-PARAMETER •
ID(RWB]=VIRTUAL ADDRESS •
ID[T2j=MEr/ORY DATA •
ID[ TXDB) =PHYSICAL ADDRESS
ID[D. SV] =STATUS-CODE

EXAM.GEN. REG.

122

ID[RX:>B)=REG!STER NUMBER •
ID[TXDB] =REGISTER DATA

DEPO.GEN.REG.

123

ID[RXD8)=REG!STER NUMBER •
ID(T2 )=REGISTER DATA •

EXAM.PROO.REG.

124

ID[RXDB]=REGISTER NUMBER•
ID(TXDB]=f<EGISTER DATA

DEP.PROC.REG.

125

ID(RXDB]=REG!STER NUMBER•
ID(T2]=REGISTER DATA•

CONTINUE

127

QUAD-CLEAR

129

SB I-UNJAM

12A

ID[RXDB]=QUAD-ADDRESS •

BEN

Name

UPC<rll2>

UCP<rlll>

LA<Qll>

PSL<C>

UPC<rllrll>

NOP
ALU
ROR

LA<Qlrll>

:x:i

ALU C31

C31
I RC.ROM

I RC.ROM
IB.O

IB.O

ACCelerator

ACC UB2

s:
(")

I RC.ROM

IRC.ROM

ACC UBl

ACC UBQI

0
0

(")

cm
CD

:x:i

)>
DATA TYPE
VAX
8

Normal
Q + D

2 = Field Src
3= Addr Src

END DPl

-11

Read +
Modify

ASRC +
VSRC

ASRC +
Q + D

Read +
Modify

D Class

Class +
DM27

9
VAX

IR2-l

IR<2>

IR<l>

PC Modes

SM or DM
47 + 57

Dst R
.eq. PC

(")

:J:

)>
CD

-11

REI

IB TEST

TB Miss
Error

Stall
Data OK

-I
IB
running

IB ERROR +
DATA VALID

MUL

SC.ne.QI

D<fll>

D<00>

SIGNS

Q<31>

D.ne.0

D<31>

INTERRUPT

AC Low

Internal
Interrupt

Interrupt
Request

D<7:0>
30-39

D<3:0>=
08 + 0D

Decimal

'T1

(")

Mode . l t .
ASTLVL

0
2

(I)

BEN

Name

UPC<03>

UPC<02>

UCP<flll>

UPC<fllfll>

uTrap vector

uVECT<3>

uVECT<2>

uVECT< l>

uVECT<fll>

Last
Reference

-PSL<FPD>

Nested
Error

Wr Chk*
-Intlk

-Read+
Intlk

EALU CC

EALU N

EALU Z

SC.ne.0

Sign Src

"-.>

:s:

n
:c

0
n
0

0 = Zero
1 = Neg

ALUl-0 (previous cycle)

SC<9:8>
.ne.0

SC.gt.0

SC<9:5>
.ne.0

Rlog
Empty

ALU<l:0>
.eq.0

ALU<01>

ALU<00>

:c
m

STATE7-4

STATE<?>

STATE<6>

STATE<S>

STATE<4>

STATE3-fil

STATE<3>

STATE<2>

STATE<l>

STATE<0>

D Bytes

D< 31: 24 >
.ne.0

D<23:16>
.ne.0

D<l 5: 8>
.ne.0

D<7:0>
.ne.0

03-0

D<fil3>

D<02>

D<01>

D<00>

1-31
.gt.31

.,,m
c:

PSL

PSL<N>

PSL<Z>

PSL<V>

PSL<C>

ALU cc

ALU N

ALU

IR<0>

ALU C31

BEN

Name

UPC<04>

UPC<03>

UPC<02>

UPC<01>

UPC<fllfll>

n
0

PSL Mode

-VAMX<31>

-VAMX<30>

-Console
Mode

-PSL<IS>*
-PSL<CM>

Kernel
Mode

.:!

Translation
Test

PTE
-Valid

Data
Aligned

TB Miss +
Access Viol.

TB Miss +
1st Modify

lE
lF

MICROTRAP VECTORS

Number

Function

100
101
102
103
Hl4

System Initialization
Unaligned Data Trap
Page Trap
Modify Bit
Protection Violation
Translation Buffer Miss
Reserved Floating Operand
Translation Buffer Parity Error
Cache Parity Error
Reserved
Reserved
Reserved
RDS Error
Timeout or Error Confirm
Odd Address Error
Control Store Parity Error

105
106

107
108

109
10A
10B

10C
100

10E
10F

MICROCODE MEMORY CONTROL FUNCTIONS

---

trap on
0

:T A

u: c: :s c xp A

T
5:
B c
H: S :M c
? p 0'
E: A: I E A
A A R:
G G
c: v: s
K: E: S
'- N r1 R R p ;:i:

y = ut rap on ::on:Ji ti on
ut ~ap on cond ·ti on uni ess ~.~s c I
SE,:DND. REF or RETRY .NO. TRAP
N = do not ut rap en condition
ha""'dwar-e be'iav1our undefined.
ucode must p:--event condition

s
3210 s
s
N:
--------+-+--+--+-+-----------------+-------------------F I

~CT

0: v:
0: v:
0010 0: v:
0011 0: :

R: N: N N N
N N y N ~:
N N N ri:
: N:N N N t<
N: N N N N N N y N N'

0000
0001

01 00 0:
0101
W'
0110 0: v:
0111 0: V: IW:

o:v:

: N: y N

w: w~ y: y y
:N:- -

- - N - y N y:
y

TEST. RCHK
\;fM. NOP
TEST.WCHK

"RITE.V.NOCHK
l'.R!TE.V.WCHK
L'.JCKllRITE.V.XCHK

N y y y y: RE-"D. V. RCHK
o:v: R' R: y: y y
0: v: R' :N:Y N - - N - y y y' READ. V. NOC HK
y y y y y: READ. V .WCHK
0: v: R: w: y: y y
0: v: R: I B: Y: Y y y y y y y y y: fi ~AD. V. I BCHK
1100 0: v: R' R: N: N N N N N y N N N' READ. V. NEW PC
1101 0: V: IR:
: N: y N - - N - y y y' LCICKREAD. V. NOCHK
1110 0: V: IR: w: y: y y - - y - y y y: LGCKREAD. V. WCHK
1111 0: :
:

1000
1001
101 c
1011

1 0000 0: : HOLD : N: N N
N N N N N N'
OCJ1 0: : UNJAM: N: N N
N N N N N:
001 (j c:P:INVAL:N;N N r, N N N N
N:
1 0011
VAL : N: N N N N N N N
N:

0: p:

1 0100 o:P:ExTwR:N:N N N N N N N N y:
1 0101
\<:
l N: N N N N N N N N
0110 0:
0111
IW
N N N N N N N

0: P:
0: P:

SB! .HOLD
SB!. HCLD+UNJAM
INVALIDATE
v.:.LIDATE
EXTWRITE.P

y:
TE. P
y: LOCKWRITE. P

:N: N

O.~I

1 1000 0:
1 1001
1010 0:
1011

0: p:
; Ni N N N N N N N y y: READ.P
0: p: ISR : N: N N N N N N N N y' READ. INT. SUM

1
1
1
1

1100 0' '
1101
1, 10 0' '
1111 0: I:

0: p:

xx xx 1:
xx xx 1:1:
Abort

: N:N N N N N N N y y: LOCKREAD.P
:N: N N N N N N N N N: ALLOW. IB. READ
:

:N N

:N:N N

Ref on Trap? A A A

N: ND MEMORY OPERATION

N N
N N N'
A A A

DEFAULT:

A ( A=any,

ALLOW

R=read)

18 READ

USPO Field
Hex
value

(")

BUS cs
39
38

::c
37

Scratch Pad Operation

00-05

No operation

0'i

Load LC

;Address = SC03:00

Write RC, RB

;Address = SC03:00

08-0F

Load LA, LB

;Address determined
by ACN value
;Address = General
Register (R0-R7)

Write RA, RB

;Address determined
by ACN value

Load LC

;Address = Temporary
Register (T0-TF)

Write RC

;Address = Temporary
Register (T0-TF)

Load LA,

;Address = General
Register (R0-RF)

Write RA, RB

;Address = General
Register (R0-RF)

Load LA, LB

;Address = General
Register (Rl)
;Address = Temporary
Register (T0-TF)

18-lF

20-2F

30-3F

40-4F

50-5F

fiCJ-fiF

and Write RC
70-7F

Load LC
Write RA,
RB

-t

Load LA

10-17

(")

;Address = Temporary
Register (T0-TF)
;Address = General
Register (Rl)

"'tJ
)>

"'tJ

::c

:j
0

• TOC

Machine definition

ACF,

ACI",

ADS,

ALU,

AMX"

(')

ACF'/:< 71: 70>,. DEHIULT:O
NOP=O
SYNCz 1
TRAP1:2
CONTROL::)

1 ACCHERATOR CONTROL

1ACCELLfRATOR•DEPENDENT CCJNTROL FUNCTION

0
r-

ACM/::<57: 55>
PliR. UP::O
ABORT=l
POLY .DONF=6

; ACCELERATOR MISCFLLANEOUS CONTROL

::0

AOS/:<47:47>
VA=O
IBA=l

I ADDRESS SELECT

ALU/::<b9:bf», .DEF'AULT=Of'
A•B::OO
A•B.RLOG=01
A•B•1=02
JNST.DEP==03
A+B+ 1 =04
A+B=05
A+f'. RLQG::Of>
ORNOT:07
XOR=O ~
ANDNOT=09
NOTA=OA
A+B+PSL. C=OB
Ufi=OC
AIW=OD
B=OE
A:Of

; ALU CONTROL f'UNCTIONS

AMX/:<81 :80>
LA=O
RAMX=l
RAMX .SXT=2
l<AMX .OXT=3

-I

: RETURh

ACCEL TO MONITORING IRD

.,,3:
m

e
c

.,,m

; INSTRUCTION DEPENDENT

;A .GR • • NOT. B

;A .XOP. B
;A 0 AND 0
1. NOT. A

NOT.

; A .OR. I!
;A .AND. B

; AMX TO ALU

;RAMX SIGN EXTENDICD ACCORDING TO DT
1RA"X ZERO EXTENDED. OXT(L)=O

.TOC

Machine definition

BEN/:<76: 72>, • DEFAULT=O
NOP•O
Z•1
ROR=2
C31=3
IRC.ROM=4
IB.0:5
ACCEL•6
DATA.TYPE=&

END.DP1•8
IR2-1•9
PC.MODESs9
REI•OA
SRC.PC•OA
18 • TEST=OB
J\llUL=OC
SIGNS•OD
lNTERRUPTsOE
DECIJ\llAL:OF'
UTRAP=10
LAST. REF= 11

EALU=12
SC=14
ALU1-0•1S
STATE7-4=16
STATE3-0• 17
D.BYTES=18
D3-0• 19
PSL.CCs1A
ALUs18
PSL."IODE•1C
TB.TEST=1D

8"1X/s<84: 82>
MASK•O
PC.OR.LB=!
PACI< ED. FL•2
LBs3
LC•4
PC=5
KJ\llX=6
R6MX=7

BEN,

BMX"

;BRAllCH ENABLE
I NO BRANCH
I ALU Z
ILA<1>, PSL<C>, LA<O>
I ALU C31, 0
;OUTPUT OP' EXTENDED IRC-ROJ\11
JIB 0 READY ?
;CODE FROM ACCELERATOR
;CVAX MODE)
ASRC+VSRC, ASRC+O+D
1
O--NORMAL, 1--0UAD OR DOUBLE
;
2--FIELD,
3--ADDRESS
I C-11 J\llOOE)
0 CLASS, J CLASS+Oll27
;(VAX J\llODE) *• IR<2:1>
I C-11 MODE) •, SM47+SM57+DM47+DJ11157, DST R=PC
l(VAX MODE) !o!OOE.LSS.ASTLVL, '•
I C-11 MODE) SRC R•PC
1 O--TB MISS, 1--ERROR
I 2--STALL, 3--DATA 01<
;SC 0 NE 0 0, D<1:0>
;0<31>, D.NE.O, 0<31>
I AC LOW, INTERNAL INTERRUPT, INT REO
;o, D BYTE 0 VALID DIGIT, 02-0 N~:G SIGN
1 Jlil lCROTRAP DISPATCH VECTOR
;-FPD, NESTED ERROR, LOW TWO BITS I
I O--l<EAD INTERLOCK, 1--RE.AD, READ CHK
I 2--WRITE, 3--READ, WRITE CHK
;EALU N, EALU Z, SC.NEO.O, SS
;SC<9:8>.NE.O, sc.GT.O, SC<9:5>.NE.0
;RLOG E"IPTY, ALU<1 :0>•0, ALU<1>, ALU<O>
I (ALU BITS FROM PREVIOUS STATF:l
;STATE <7:4>
ISTATE <310>
lllYTES 3, 2, 1, 0 OF D.NF.O
;D<3:0>
;N,Z,V,C OF PSL
;ALU N, ALU Z, lR<O>, ALU C31
l-VA<31 :30>, -CONSOLE, IS+CJlll, KERNEL
;PTE VALID, ALIGNED, ou•o, +
I O--TRANSLATION OK, 1--WR CHI< AND M:O
1 2--ACCESS VIOLATION, 3--TB J\lllSS

::c

*•

!!
m
r-

I BMX TO ALU
; A 0 I" THE bl! SELFCTF:D BY SC<4: O>
I LB UNLESS R:PC, THEN PC
1 PACKED FLOATING

::c

0
r-

*•

;D OR

0
2
-t

s::

"Tl

30
2

Cl>

c=;
0
2

TOC

Machlne def 1n1t1on

CCK/=<22:20>, .O~fAULT=O

CCK,

CID,

DK,

DT"

;CONDITION CODES
;~ote

•

= RESERVlO OPERATION,

"ALU SIGN"

AND

"AMX SIGN"

ARE SIZE DEPENDENT

;-------------------------------------+------------------------------------------+
NATIVE MOOE PSL

COMPATIBILITY MODE PSL

;----------+------------------+--+- - -+---------- + -- - -- -- - -- - - --- - - -+- - - +-- - - - --- +
I V I C I
I V I
C
; - - - - - - - - - -+- --- - -- - - -- - -- - - - - +- -- +- -- +-- - - - -- - -- +- - -- - --- - - -- - - -- - - +- - - +- - - - - - - - +

NOP=O
LOAD.UBCC=t
I
SET.V=2
,.VALIDI'IY=<VI>;
N-A"'X.Z-1ST. vc_vc=3
;
ROR=4
, • VALIDITY=<VO>I
NZ-ALU. vc_ozs
;
NZ-ALU. vc_vc=6
,.VALIDITY=<Vl>;
C-AMXO=b
, • VALIDITY=<VO>;
INST .DEP=7

A"X SIGN

z
z
z.and. (ALU.eq.O)

ALU SIGN
ALU SIGN

ALU.eq.O
ALU.eq.O

•

I
I
I
I v
I
I

I
I
I
I
I
I
I
I

DKl=<91 :88>, .DEfAU[,T:O
NOP•O
LEF'T2=1
RIGHT2=2
DIV=4
LEF'T•S
RIGHT=6
SHf'z8
SHF'. F'L=9
ACCEL:m:OA
BYTE.SWAP:OB
Q:OC
DAL. SC=OD
DAL.SV•OE
CLR=OF'
DT/:<79:78>, .DEF'AULT=O

LONG=O
WORD=!
BYTE=2
INST. DEP=3

;CONSOLE & ID BUS CONTROL I f F'S/1
;DEFAULT, ALLOW AUTO IB READ
;SET CONSOLE ACKNOWLEGE FLAG
; CLEAR CONSOLE MODE
I READ ID BUS REG SELECTED BY SC
;READ ID BUS REG SELECTED BY UK"X
;WRI1E REG SELECTED BY SC
;WRITE REG SELECTED BY UK"X

;DEFAULT, HOLD
;DOUBLE SHIFT LEFT
;DOUBLE SHIFT RIGHT
I IF' r.oT ALU Cl<Y, SHIFT LEFT
I ELSE LOAD f POl'I SHf
ISHUT LEFT
;SHU'I RIGHT
;LOAD SHF' MUX, INTEGER F'ORMA'l
;LOAD SHF' MUX, UNPACKED FLOATING FORMAT
;LOAD ACCELERATOR DATA FROM or BUS
;REFLECT BYTES AROUND BIT 16
; LOAD Q THRU DAL
I LOAD DAL CSCJ
;LOAD DAL[SHF' VAL]
I LOAD ZEROS
;DATA TYPE
;CONTROLS AMX SIGN/ZERO EXTENDER, SHF' AMOUNT,
;CONDITION CODE SETTING, Ar.D ME"'ORY REFERENCES
;D£F'AULT

; INSTPUCTION DEPENDEr.T ; ANY OF' ABOVE, OR QUAD/DOUl!LE

•
I Al'IX SIGN
I

I ALU SIGN
I ALU SIGN
I
I
I
I
Instruction dependent

; - - - - - - - -- - + --- - - -- - - - - -- ---- - +-- -+CID/=<45:42>
NOP=!
ACK:S
CONT•7
READ. SC=9
READ 0 IOH=O!l
WRITE.SC=oo
WRI'IE.KMX=or

I
I

I
I
I
I
c
I A~X<O>
0
I
I
I AMX<O>

•

z. and. CALU. eq. o)
ALU,eq.O
ALU.eq.O

--+----------+------------· -----+- - - • - - - -- - - - +

(")

z
-t
:c

"T1

z
::!
0
z
(/)

c=;
0

.roe

Machine definition

~ALU,

EALU/=<15:13>
AZO
OR=l
ANDNOT=2
E\=3
A+B=4
A•B=5
A+1=6
f\ABS.A•ll=7

; 1:.XPuNEN'f ALU

EBMX/=<19:1R>
FE=O
l\MX=I
AMX. EXP=2
SHf. VAL=J

;l::BMX TU E.ALU
; DEFAULT

EBMX, FEK, rs,

IFK,

ll:<C"

(")

2
-t

::u
r::u

0
;•AllSCA•B)

s::

:!!
m
r-

;SHlfT VALUE

FEK /=<24: 24>,. DEFAULT=O
NOP=O
LOAD=l

;FE HGISTER CONTROL
;DEFAULT, HOLD

FS/=<42: 42>
MCT=O
CID=l

;FUNCTION SELECT FOR 43•46
; ENABLE MEMORY CONTROL
;ENABLE ID BUS AND CONSOLF CUNTllOI.

IEl\/:<31:30>
NOP:O
JSTR=1
IACK=2
EACK=3

; lNT~~kRUPT AND EXCEPTION ACKl<OWLEDGE

IBC/=<95 I 92>,. DEFAULT=O
NOP:O
STOP= I
FLUSH=2
START=3
CLR.0.1=4
CLR.2.3:5
BDE.ST=7
CLR. OzOC
CLR. l=OD
CLR. O•l=OF
CLR. 1-s. COND=Or

; IBUF CONTROL FUNCTIONS
;DEi' AULT

'"T1

;STROBE INTERRUPT REQUESTS
I INTERRUPT ACKNOWLEr>GE
I EXClPTION ACKNOWLEDGE

;FLUSH IB AND LOAD IBA
;CLEAR BYTES 0,1 C•ll OPCODE)
;CLEAR BYTES 2,3 (•11 !STREAM DATA)
;TRANSFER BRANCH DISPLACEMENT
;CLEAR BYTE 0 CVAX OPCnDEl
;CLEAR BYTE 1 CVAX SPECIFIER)
;CLEAR BYTES 0•3 (•11 OP ' DATA)
;CLEAR BYTES 1•5 CONDITIONALLY
I f THERE IS NO SPECIFIER EVALUATION,
CLEAR NOTHING.
JF' A SELF'•CONTAINED
I SPECIFIER, CLEAR IT.
I f Il'MECIATE,
ABSOLUTE, OR DISPLACEMENT, CLEAR THE
I ISTkEAl'I LIURAL.

2
-t

0
2

C'n

n
0
2

::!

.roe

Mach 1 ne de t1n1t1 on

ID.ADDR/=<63:58>
I RUf:O
DAY.TIME=!
SYS.10=3
RXCS=4
RXOB::5
TXCS=6
TXDB=7
00=8
NXT.PER:9
CLK.CS=OA
INTEROL=OB
CES=OC
VECTOR=OD
SIR=OE
PSL=OF'
TBUf:: 10
TBER0:12
TBER1=13
ACC.0=14
ACC.1=15
ACC.2=16
ACC.CS=l 7
SILO=l 8
SB1.EHR=19
TIME.ADDR=lA
fAULT=lB
COMP:lC
MAINT=ID
PARITY=IE
USTACK=20
Ul:lkEAK=21
wCS. ADDR=22
WCS.DAfA=23

ID.AODR,

; ID BUS ADDRESS
; RO
;SPECIFIER/LITE:RAL DATA fRCIM lB
;HD+io~
;CURRENT TIME OF' DAY •••
MUST READ UNTIL STOPS CHA.NGING
; RD
;SYSTE~ IDENTiflCATIUN
; RD+wP
;CONSOLE RF:CIEVE cor.TROL/S1'ATUS
;CONSOLE RECIEVF: DATA BUffE:R
I RD
(T0-10 RF.:GISTERl
;CONSOLE TRANSMIT CONTROL/STATUS
;CONSOLE TRANSMIT DATA BUff'ER
; (fROM-ID REGISTl'Rl
;DATA PATH 0/0 REGISTERS OIAINT ONLY)
WR
;INTE~VAL CLOCK NEXT PEFIIOC• REGISTER
RDHili
; INTERVAL CLOCK CONTROL/SUTUS
RD
;CUllllENT INTERVAL COUNT
RO+loR
;CPU ERPOR/STATUS
RD+wR
;EXCEPTION & INTERRUPT CONTROL
RD+loR
;SOfTWARE INTERRUPT REGISTE:R
H!J+wl!
; PROCESSOR STATUS LOl'<GwORD
; TRANSLATION BU f f ER DATA
;TB EHROR/STATUS 0
;TB ERROR/STATUS 1
;ACCELERATOR REGISTER 10
I ACCELERATOP REGISTER I I
; ACCELERATOR REGISTEI! 12
; ACCELERATOR CONTROL/STATUS
; NEXT ITEM FROM SBI HISTORY
;SBI ERROR REGISTF:R
;SBI TIMEOUT ADDRESS
ff AULT/STATUS
;SB! SILO COMPARATOR
JSBI MAINTENANCE
;CACHE PARITY
I MICROSTACK
; MICRO BREAK
; WHITING

WCS COUNTS ADDRESS

(")

0
z
-t
:2:1

:2:1

.,,:s::
m
r-

.,,cm
z
-t

0
z

n
0
z

.::!

;ID BUS AOOHESSES CONT I NUED.
POBR=24
P1BR=25
SBR:26
t<SP=28
ESP=29
SSP=2A
USP=2B
ISP=2C
FPDA=2D
D.SV=2E
a.sv=2F
TO:JO
Tl =31
T2:32
13=33
T4=34
T5=35
T6=3b
T7:37
T8=38
T9=39
PCBB=lA
SCflB=31.>
POLR=3C
Pl LR=3D
SLR=3E

ADDRESSES 24•3F ARE RAM LOCATIONS
; PROCESS SPACE 0 BASE REGISTER
I PROCESS SPACE l BASE REGISTER
;SYSTEM SPACE AASE REGISTER
; KERNEL STACI< POINTE~
; EXEC STACK POINTER
; SUPERVISOR STACK POINTER
; USER STACI< POINTFR
I INTERRUPT STACI< POINTER

• NOCHEF

0
2

-f

::0

;GENE!< AL TE!o\PS

c
cm
; PROCESS CONTROL BLOO BASE
;SYSTEM CONTl<OL BLOCK BASE
; PROCESS 0 LENGTH REGISTER
; PRUCESS l LENGTH REGISTER
;SYSTEM LENGTH REGISTEP

.CREF
J/=<12: O>, • ~EXTAODRESS

(')

;NnT MICRO wORO ADDRESS

""2
-f

Cl>

n
0
2

:::!

Machine definition

• TOC
KMX/:<63:5~>

• 8=0
.1 =l
• 2=2
• 3=3
• 4=4
SP! .CON=5
SP2 .CON=6
ZER0=6
sc=7

.14=8
• A0:9
• 34=0A
• 28:08
• 40=0C
.50=0D
• H"rO:OE
• Er=or
• 80=10
• 8000=11
.rr=12
.rroo=13
• I E=l 4
• 3f=15
• 7f=16
• 7=17
• r=1 s
.10=! 9
.rFE8=1A
.rrro=1s
• rrra=1c
.20=1D
• 30=1E
.1a=1r
• 3ff=20
.C=21
.D=22
.1F=23
• 1 rooa24
• B0=25
.E003=26
.7C=27
.Ff'E0=28
• 60=29
SPARE=2A
• DFCF=2B
.4000=2C

KMX"

ICONSTANTS OR I fROM FK
; 18 FROM FK
111 FROM f'K
I 12 f'ROM FK
113 fROM f'K
114 FROM f'K
:SPECifJER 1 CONSTANT
ISECil'IER 2 CONSTANT (•11 MODE)
; OR ZFROS CVAX MODE)
ISCC9:0J fROM f'K
18 • 3f: CONSTANTS (1 CYCLE SETUP I f ALU IN ARITH MODE)
IDECIMAL VALUE Of CONSTANT
120
(AF ,JL,MH)
1160
(AF,JL)
I 52
(AF)
: 40
(AF')
;64
(Al',JL,MH,H")
;80
CAF',MH)
;?
CTf) •H•MACHINE•DEPENDENT!!!
;239
(JL)
;128
CAf,JL,l"H,Tfl
:•32768 CAFl
1255
(l"H,'!f)
;•256
CMH,AF,JL)
130
(AF)
;63
(l'IH,Af,Tf)
;127
CAF, MH)
:1
CMH,Cl~,Af,TF)
I 15
CMH,AF ,JL,Tfl
116
(MH,Tf)
;-24
CCM,JL,Tf,MH)
;-16
(CM,TF ,MH)
1-8
CCM,JL,MH,TF)
132
(CM,AF ,MH,TF)
148
CMH,Af ,TF)
: 24
: 1023
CC"'l
CCM,JL,TF,MH)
:12
;13
CT f l
CAF,JL,MH,TF'l
131
CJL, MH)
:793!>
(ll'H)
; 176
CCII')
:
(AF)
:124
;-32
CJL)
CTF l
196
: 7

CJL)
CTFl****MACHINE•DEPENDENT! !

(')

0
z
-t
:l:J
0

:l:J

.,,3:
m

re
c

.,,m
!

-t

sz
en

n
0
z

.::1

.FFF1=2D
.19=2E
.FFF9•2F
• F'FFF•30
• 88=31
• 3030=32
.FO=ll
.C0•34
.6=35
.9o:36
.FF'f'6:37
.FF'f'5:38
.1A•39
, 24=3A
.18•38
• F'F'FC•3C
.A=3D
, 7E•3E
SPAREz3F

1-15
I 25
1-1
;-1
I 136
I 1

;240
; 192
J6
79
1-10

1-11
726
136
, 27
1-4

710
1126

(AF) nnMACHINE-DEPENDENT ! I
(AF')
CAF')
(MH,JL,TF')
(AF')
CTF')
CTF>
CTF, MH)
CCM,JL,TF)
CCM)
CCM)
CCM)
CCM,AF,TF)
CCM,MH)
CCM,AF ,TFl
CCM,TF,MH)
CAF ,MH)
CAF ,1·r)

n
0

....
:D
0
r-

.,,31:
m
r-

e
cm
:?!

=t
0
z
en

n
0
z

::!

,TOC

"'•chine definition

MCT /:s<4 7: 42>,, DEFAULTzlE
TEST, RCHll•OO
MEM, NOP&02
TEST, WCHll•04
WR l TE, V, t.OCHK=OA
WRITE, V, WCHll•OC
LOCKlllRin;, V, XCHll=OE
READ, V .RCHK•10
READ, V,NOCHK•12
REAO,V,WCHl(s14
READ,V,IBCHK•16
READ, V, NEWPC• 18
LOCllREAO, V, hOCHK•lA
LOCK READ, V, llCHK=lC
SBl, HOLD=20
SBI, HOLO+UNJAM•22
INVAL10ATE=24
VALIOATEs:26
EXTl>RITE,P•28
WRITE,Pz2A
LOClllllRITE,P=2E
REAO.P=l2
READ, INT. SU,u:l6
LOCKREAO.P=lA
ALLOW, I B, READ=lE
MSC/=<29: 21»,, DEFAULT=O
NOP=O
CHll.CHM:Ol
CHK. FLT .OPl<=02
CHI( ,ODO. AOOR•Ol
IR0:04
LOAD.STATEz05
LOAO,ACC.CC:Ob
REAO,RLOG=07
CLR. fP0:08
SET. f P0•09
CLR. NEST, ERR=OA
SET. hEST. ERR•OB
SECUNO, REf:OC
RETRY, NO. TRAP=OD
RETRY. TRAP•OE
I NH. CM, ADDRzOF

I MCT, MSC"
1 l'!EMORY CONTROL
ITEST TBUF WITH READ CHCK
!NEITHER CPU NOR IB GfTS MEiii CYCLE
ITEST TBUF llITH llRITE CHECK
; wRITE, INHIBIT TRAPS
lllRITE, NORMAL VARIETY
11Ntt:RLOCK llRITE, VIRTUAL ADDRESS
IREAO, NORMAL VARIETY
IREAO, Il'IHIBIT TRAPS
IREAD fOR JlllODlfY
I READ, CHECK CONTl<OLLED BY l01JFFER
;BEGIN NEW INSTllUCTION STREAM
I DATA GOES TO INSTRUCTION BUFFER
7INTERLOCK READ, INHIBIT CHECll
I INTERLOCK READ, NOR"AL VARIETY
ISTOP ALL Sill ACTIVITY
JRESEl SBI
ICLEAR CACHE ENTRIES
IMICl<OOIAGNOSTIC FORCE VALID
IEXTF.NDED WRITE TO CLEAR MOS ERRORS
JIORIIE, PHYSICAL
IINTERLOCK WRITE, PHYSICAL
IREAO, PHYSICAL
7INTERRUPT SUMllARY READ
11t<TERLOCK READ, PHYSICAL
IGIVE IB A CYCLE IF IT wANTS ONE

n
0

-4
::0

,...0

::0

.,,s:

m
,...
c
cm

!
:::!
0

c;
IDEFAULl'
!CREATE NEii PSL fOR CHJlll
IUTRAP IF ALU<15>•1, ALU<14:7>•0
;THIS STATE IS INSTRUCTION DECODE
ITAllE CONDITION CON.S FROM ACCF.LERATOR
IC ANO POP RLOG STACI()
ICLEAR PSL<FPD> BIT
I SET SAME
ICLR NESTED ERROR FLAG IN CPIJ STATUS
;SE.T SAME
;or 1.JIOLIGNED DATA REFERENCE
; APPLY SAVED CONTEXT, INHIBIT TRAPS
;APPLY SAVED CONTEXT TO THIS R£f
'ALLOW USE or FULL 32-BIT ADDRESS

::!

.roe

Machine definition

PCK /z<34: 3 2>, • DEf AULT=O
NOP=O
PC-VA=l
PC-IBA=2
VA+4=3
PC+l:s4
PC+2=5
PC+4•6
PC+N•7
QK/=<54151>, .DEfAULT=O
l'IOP=O
LEfT2= 1
RIGHT2=2
LEfT:S
RIGHT=&
SHf=8
SHf .fL=9
IJEC.CON:OA
ACCEL=OB
D=OC
ID:OE
CL Rs Of
RAl'X/=<77:77>, .DEfAULT=O
[)a::O

PCK,

OX,

RAMX,

IHlMX"

I ADIJRESS COUNT CONTROL
I DEFAULT

-4

::c

IVA-VA+4
7PC-PC+1
I PC-PC+2
I PC-PC+4
1 PC-PC+N,

::c

t; IS DETERMINED BY

INSTR BUF'P'!:R

:llEfAULT, HOLD
;DOUBLE SHifT LEFT 2
;DOUBLE SHlfT RIGHT 2

!!
~

MIXER TO AMX

IDATA PATH MIXER TO BMX.

e
cm
:::!

JLOAD IO BUS
I LOAD ZERO

0=1
RB,.X/=<77: 77>
QzO
D=l

.,,31:
m
r-

;LOAD SHf, INTEGER FORMAT
I LOAD SHF, U"PACKEO FLOATING fOFIMAT
;DECIMAL CONSTANT : 6'S Jt; EACH NJBl!LE
;FOR wHJCH ALU CRY OUT IS FALSE
I LOAD ACCELERATOR DATA FROM D•· BUS

;DATA PATH
I DH AULT

SAME BIT AS RAMX

n
0

z
::i

• roe

'°'achine definition

SCK,

SGN,

SHf", SI, SMX"

0
z
-t

SCK/=<23:23>, .Dt.fAULT=O
f.OP=O
LOAD=l

I SC IH.GISTER CONTROL
I DEF AULT 1 HOLD
ILUAD S"1X<09:00>

SGN/:<50: 48> 1 • O!Cf" AULT=O
NOP:O
LOA!J.SS=l
SS. flWM. SD=2
NOT .SD:3
SD. f"RO~. SS=4
SS. XOR. ALU=5
ADD.SUB:6
CLI<. SD+SS=7

I SIGN CONTROLS
IDEf"AULT
I SS.ALU< 15>
:ss.sD
; SD."'OT SD
;SD.SS
;so.ALU<15>, SS.SS.XOR.ALU<l!»
; SD-ALU< 15>, SS-SS. XOR. ALU< 15>, XOR. IR< 1>
; CLEAR BOTH

SHf /:<87: 85> I . DEf"AULT=O
ALU=O
LEfT=l
RIGHT=2
ALU. DT=3
RIGHT2:4
LEf'l 3:5

;ALU SHif"TER CONTROLS
I DEf"AULT I SHF"-ALU
;SHF"-ALUCL1) 1 INSERT SI CNTL
;SHF"-ALUCR1), INSERT SI CNTL
ISHF"-ALUCOTI LO,L1,L2,L3), INSEJIT 0
ISHF-ALUCR2) 1 INSERT SI CNTL
ISHF"-ALUCL3)

SI/1:<57155> 1 • DEF" AULT=l

;SHlf"T INPUT CONTROLS
I
SHf
D
I
PSL<N>
Q31
ALU 31
QO
0
0
0
0

DIVDsO
ASHR=l
ASHL=2
ZERO=l
SPARE=4
DIV=5
MUL+=6
MUL•=7
SMX/=<17: H»
EALU=O
n:=1
ALU=2
ALU• EXP=3

Q31
0

1
;MIXER TO SC
;EALU <9:0>
;FE<9:0>
I ALU<09: 00>
IALU<14107>

,..

:a
0

.,,3:
m

cm
:!!

0
ALU CJ!
Qll
D31

Q31
ALU Cl 1
ALU O,! 0
ALU O, 1 1

n
0
z
::!

Machine definition

,TOC

SPO, SPO,AC,

SPO,ACN, SPO,ACN11,

SPO,AC/1:<41138>
LOAD,LAB=l
LOAD,LA=2
WRITE,RAB=3

14 FUNCTION BITS OF SPO FIELD
ILOAO LA, LB FROM RCACN)
I LOAD LA-RN, HOLD LB
IWRITE RA, RB CACN)

SPl ,SPl=O
SP2,SP2=1
SP2,SP1=2
PRN=3
PRN+1•4
SC:S
SP1+t=6
SPO. ACN111=<37: 35>
SRC, SRC=O
OST,OST:1
DST, SRC=2
SRC,SRC=3
SRC,OH.1•4

sc=s
SPO, R/=<41: 39>
LOAD. LC=2
WRITE,RCa3
LOAD,LAB=4
WR I TE, RAB•S
LOAD, LAB1, WRITE, RC=6
LOAD, LC, WRITE, RAB1•7

I AC NUMBER IN SPO FIELD
;VAX MOOE
RA
10
SP1 R
11
SP2 R
12
SP2 R
13
PRN
14
PRN+l
15
SC<03:00>
16
SPl P+1
SP1

.....

RP.
SP1
SP2
SPl
PRN
PRN+1
SC<03100>
R+l

IAC NUMBER IN SPO FIELD •• 11 MOOE
RB
1•11 MOOE
RA
SRC R
SRC R
I
0
OST R
DST II
1
2
OST R
SRC R
3
SRC R
SRC R
4
SRC R ,OR, 1
SRC R ,OR, 1
SC<03: 00>
s
SC<03100>
;SCRATCH PAD FUNCS WITH LOW 4 EIITS
ILOAO LC, AOR•&PO,RN
I wRITE RC
;LOAD LA, LB
IWRITE RA, RB
ILOAD LA, LBCRlJ, AND WRITE RCCRN)
TLOAD LCCRN), AND WRITE RA, Rl!CRll

I SCRATCH PAD UPC ODE 1 7 8 ITS
I DEFAULT
ILOAO LC, AOR•SCC03100J
IWRITE RC, AOlo:SCC03:00J

SPO,ACN/:<37135>

SPO,R•

SP0/:<41135>, ,DEFAULT•O
NOP•O
LOAD, LC, SC=6
WRITE,RC,SC•7

or SP AS ADR

0
r-

""m

e
cm

""z
=4
0
z
en

n0
z

::!

.roe

Machine definition

SPO • RAB/c< 38: 35>
RO:O
R1=1
R2c2
R3:3
R4=4
RScS
R6=b
R7=7
AP=OC
FP11:0lJ
SP=OE
Rl!'>sOF
SPO.RC/=<38135>
TOsO
Tlsl
T2.:2
T3sl
T4:4
T5=5
Tf>z6
T7=7
LC.SVs8
VA.SV=9
PTE.VA=OA
PTE.PA•OB

: SPO,RAB, SPO,RC, SUB, YAK"

IRA/RB LOCATIONS

RET•2

VAK/=<25125>,, DEFAULTsO
NOP•O
LOAD=l

z
:c
r-

0
IR12 1: ARGUMENT LIST POINTER
JRll z STACK FRAME POINTEll
IR14
STACK POINTER
IR 15 • PC, TO SOFTWARE, SCRATCH TO UCO DE
IRC LOCATIONS

:s:

-n
m

e
c
m
!!
~

.....

I MEiii MGMT SAVES LC HERE

0
z
en
0
0

z
.::!

VA,REP'=OE
MBIT, VA=OF
PTE, IOSK=OP'

SPEC:sl

.....
0

Pc.svsoc
sc.sv:soo

SUB/=<65: 64>,, DEFAULT=O
NOPsO
CALLcl

I SUBROUTINE CONTROL
I DEFAULT
I PUSH UPC OF THIS MICROINSTRUCTION
I ONTO USTACK
1 "0R" TOP OF USTACI< TO UPC
I AND POP USTACI<
I REPLACE LOW 8 BITS OP' NEXT
I UPC WITH SPECIFIER DECODE FRO"
I INSTRUCTION BUFFER
I DEFAULT
ILOAD VA

.roe

Machine definition

Validity cheCICI"

en
<
en
-t
m
3:
~

Reqions•

:::0

•SET /VO=<. NOT C<NAT I VE> J >
.SET/Vl=<NATIVE>

.roe

Macro definition

+-------+----·---------------------+
I

I
.SET/WCSR1L•1000
.SET/llCSR1H=113F

I
I
I
I
I
I
I

I
I
I to
I
I
I
I 41C

4095

.SET/~CSR2H=17FF

PCS

l>
0

:::0

---·----+--------------. ------+

+- -- I
4096 I 41C I
I

I
I to
I
I 61C

I
I DEC'S WCS reqion
I
I

I
I
6143
I +• .......... • +• • ••+ •• ........ •••• .. •• ••••••• •+

.SET/WCSR3L=1800

6144

61C

I
I to I User or G'H \llCS

I
.SET /loCSR 3H=1 BFF'
I

1COO
I

1 FF'F

I
.SET/llCSR2L=1200

7167 I ?IC I
+•••••••+••••+•••••••••••••••••••••+
716ij
7k I
I
I
I
I
I to I user \ljcs
I
I
I
I
8191 I Bk I
I
+•••••••+••••+•••••••••••••••••••••+

t.ote

1140 to 11P'F 11
the f'PLA trap
address reqion

• roe

(11

ALU--1
ALU-0 CA l
ALU-O+D
ALU-0+0+ 1
ALU-O+K Cl
ALU-O+K Cl+ 1
ALU-O+LB+l
ALU-O+LC
ALU_O+LC+ 1
ALU-O+MASK+l
ALU-0+0
ALU-0+0+ 1
ALU-0-D
ALU-O-D-1
ALU-0-K [ l
ALU-0-K [ l -1
ALU-0-LB
ALU-0-LC
ALU-O-LC-1
ALU-0-0
ALU_o-0-1
ALU-0 Cl D
ALU-OCJLC
ALU-D
ALU-DCB)
ALU-D+K [ l
ALU-D+KCJ+l
ALU-D+K [ l . RLOG
ALU-D+LB
ALU-D+LC
ALU-D+LC+ 1
ALU-D+LC+PSL.C
ALU-D+O
ALU-D+O+ 1
ALU-D+O+PSL.C
ALU-D+RLOG
ALU-D-K Cl
ALU-D-K {) -1
ALU-D-LB
ALU-D-LB.RLOG
ALU-D-LC
ALU-D-LC-1
ALU-D-0
ALU-D-0-1
ALU-D.OXTCJ
ALU-D.OXTCJ+Kll
ALU-D.OXTCJ+LC
ALU-D.OXTCJ+O
ALU-D • OXT Cl -K []

Macro definition

: Register transfer macros•
"AMX/RAl'X. OX'I, DT /LONG, ALU/NOTA"
• AMX/RAMX. OXT, DT /LONG, ALU/ A"
"AMX/RAMX • OXT, OT/LUNG, RBMX /D, l!"X /RBMX, ALU/A+B"
• AllX/RAMX. OXT, OT /LONG, RBPIX/D, Bl'X /RBMX, ALU/ A+B+ 1"
"KMX/(11, BMX/KMX, Al'X/RAl'X. OXT, llT /LONG, ALU/ A+B"
• KMX /(11, BMX/K MX, AMX/R A MX. 0 XT, DT /LONG, ALU/ A+B+ 1"
• AMX/RAMX. OXT, OT /LONG, fll'IX /LB, ALU/ A+B+ 1"
• AMX/RAI' X • 0 XT, DT /LONG, BM X/ LC, ALU I A+B"
• AMX/RAMX. OXT, DT /LONG, BMX/LC, ALU/ A+B+ 1"
"AMX/IUl'X • OXT, OT /LONG, B"X/MASK, ALU/A+ll+ 1"
"AllX/ k AMX. OXT, OT /LONG, R BMX /0, Hl'X /RBMX, A LU/ A+B"
• AMX /RAtoiX. OXT, DT /LONG, RBI' X /0, Bl'X /R BMX, ALU/ A+B+ 1"
•A MX/R AMX • 0 X T, OT /LONG, R RMX /D, BMX /ABM X, ALU/ A-8"
•AM X /RAIO• 0 X T, OT /LONG, R BMX /D, Ill' X /Rl!llX, ALU/ A-B-1"
• AMX/llAMX. OXT, OT /LONG, KMX/li 1, Bl'X/IOIX, ALU/ A-fl"
"K MX/U, BMX /K MX, AM X/R A"' X. OXT, DT /LONG, ALU/ A-B-1"
"AMX/RAMX. OXT, OT /LONG, 8MX/LB, ALU/A-B"
"AMX/RAMX • OXT, OT /LONG, BMX/LC, ALU/ A-B"
"AMX/RAl'X. OXT, OT /LO'lG, l!MX/LC, ALUf A-B· 1"
"A l'IX/R Al'X. OXT, DT I LONG, RBl'X/O, Bl'IX /RBMX, ALU/ A•B"
"AMX/kAMX. OXT, OT/LONG, RF!MX/O, llMX/RBMX, ALU/ A"'B• l"
"ALU /li 1, AMX /R AMX. OX T, LONG, BMX/FI eM X, RBMX ID"
"ALU/li 1, AMX/RAMX • OXT, LONG, B"1X/LC"
"RAMX/O, AMX/RAMX, ALU/ A"
"RBMX/D, BMX/Rl:!MX, ALU/B"
"RAMX/D, AMX/FIAMX, KMX/li 1, 8MX/KMX, ALU/ A+B"
"l<AMX ID, AMX/ RAMX, KMX I 111, BMX/KM X, ALU/ A+B+ 1"
"AMX/FI AMX, RAMX /D, K MX/!11, BMX /I< "X, ALU/ A+B. RLOG"
• RAMX/O, AMX/RAMX, BMX/Lll, ALU/ A+B"
• RAMX ID, AMX/RA"X, B"X I LC, ALU/ A+B"
"RAMX/D, AMX/RAMX, Bl'X/LC, ALU/ A+fl+ 1"
• t<AMX ID, .l "X/R AM X, l!M X/ LC, ALU/ A+ll+PSL. C"
"RAMX/ D, A "X /RAMX, RB"X /Q, BMX /R B"X, ALU I A+B"
• RAMX/D, AMX/RAMX, RBMX/O, BMX/RllMX, ALU/ A+B+ 1"
"ALU/ A+B+PSL • C, AMX/RAMX, l\l'X/l<Bl'X, RBMX/0, RAMX/D"
• AL\J/ A+B, A"XIRAMX, RAMX/D, BMX/0, "SC/kEAD. RLOG"
"RAMX/D, AMX/R.l MX, K"X/il 1, FIMX/KMX, ALU/ A•B"
"RAMX /0, AMX /RA MX, l<MX/U 1 BMX /11 l'X, ALU I A•B• 1"
"R AMX /D, AMX /RA MX, BMX/LB, ALU/ A•B"
"!<A"X ID, AMX I RAMX, BMX /LB, ALU/ A•B. RLOG"
"RAMX/D, AMX/kA"X, llMX/LC, ALU/ A•B"
"kAIO ID, AMX /RAMX, BMX/LC, ALU/A•B•l"
• R AMX ID, AM X /RA MX, RBMX /0, BM X/RBMX, A LU/ A•B"
"RAMX/D, AMX/RAMX, RBMX/Q, B"X/llBMX, ALU/ A•B•l"
"RAMX/D, AMX/RAMX .O XT, DT /lil ,ALU/ A"
"RAMX/D, A!o!X/l<AMX • OXT, DT/lil, KMX/~2, BMX/KMX, ALU/ A+B"
"ALU/ A+I:!, AMX/RAll!X. OXT, DT/• 1, RAl'X /D, BMX/LC"
"ALU I A+B, A MX /RAMX • OXT, OT /@11, RA!o! X /D, BMX/RBMX, RBMX/Q"
• RAMX /D, AMX/R AM X. OXT, OT /lil, KMX/li 2, BMX/K MX, ALU I A•B"

rn
<
rn

.....
m
3:
~
n
l:I

g
0
0

m
3:

l:I

n0
z

ALU-D. OXT Cl -a
ALU-D.OXTCl .AND.K [J
ALU-D.OXT[l .A"DNDT.K Cl
ALU-D 0 0XTCl .DR 0 Q
ALU-D.AND.K Cl
ALU-D. AND. MASK
ALU-D. ANDNOT. K Cl
ALU-D. ANDNOT. MASK
ALU-D 0 ANDNOT.C
ALU-D.DR.KCl
ALU-D. OR. LC
ALU-D.OR.C
ALU-D.Ol~.kCCJ

ALU-D. OR NOT. MASK
ALU-D.SXTCl
ALU-D.SXT Cl +K Cl
ALU-0. SXT Cl+"'
ALU-D.SXTCJ .ANDNDT.K Cl
ALU-D.SXTCl .AND.K Cl
ALU-D.XOR.K Cl
ALU-D. XOR. LC
ALU-D.XOR.C
ALU-D. XOR• HC Cl
ALU-D.XOR.RCl
ALU-DC l K Cl
ALU-D []LB
ALU-DC l LC
ALU-DC JC
ALU-K Cl
ALU-LA
ALU-LA+K [ l
ALU-LA+KCl+l
ALU-LA+K Cl. RLOG
ALU-LA+LB
ALU-LA+LC
ALU-LAHC+l
ALU-LA+LC+PSL. C
ALU-LA+C
ALU-LA•D
ALU-LA•D•l
ALU-LA·K Cl
ALU-LA•K Cl• 1
ALU-LA-KC l . RLOG
ALU-LA•LC
ALU-LA-Q
ALU-LA•C•l
ALU-LA 0 AND.K Cl
ALU-LA. AND .LC
ALU-LA. ANDNOT. KC J
ALU-LA. ANDNOT. MASK

"RAMX ID, AMX /RAM X. OXT, OT/ lil , RBl'X /Q, BMX I RBMX, ALU/ A-B"
"HAMX/D, AMX/RAMX. OXT, OT /l' 1 1 KMX/!12, t!MX/KMX, ALU/ AND"
"ALU/ A ND NOT 1 AMX /RAMX. OX T, OT/ l' 1, R AMX/D, !IM X/KMX, K MX/ll2 •
"RAl'.X/D, AMX/RAMX. OXT, DT /111, BMX/RBMX, ALU/OR•
"RAMX/D, AMX/RAMX, KMX/ll l , BMX/KMX, ALU/ AND"
"HAMX/D, AMX/RAMX, llMX/MASK 1 ALU/ A"D"
• f<AMX ID, AMX/ RAMX, K MX /ll 1, BMX/ K MX, A LU/ ANDNOT"
"kA MX /D, AM X /RA MX, BM X /MASK 1 ALU/ AN DNOT •
"RAM X ID, AM XI RA MX, !<BM X/Q, BMX /RllMX 1 ALU/ ANDNOT"
"RAMX/D, AMX/RAMX, KMX/!11, BMX/KMX, ALU/OR"
"RAl'X/D, AMX/R AMX, BMX/LC, ALU/UR"
"RAMX/D, AMX/RAMX, RBMX/O, BMX/RBMX, ALU/OR•
"RAMX/D, AMX/RAMX, SPO. R/LOAD. LC, SPO. RC /111, BMX/LC, ALU/OR"
"RAMX/D, AMX/RAMX, BMX/MASK, ALU/ORNOT"
"RAMX/D, AMX/RAMX. SXT, OT /l' 1, ALU/ A•
"RAMX ID, AMX /RAM X. SXT, OT /"'1 , K MX 1112, BMX/K MX, ALU I A+B•
"RAMX/0, AMX/RAMX. SXT, OT /!I 1, BMX/RBMX, ALU/ A+B"
"RAMX/D, AMX/RAMX. SXT, OT /111, ALU/ ANDNOT, BMX/KMX, KMX/f 2"
"RAMX/D, AMX/RAl'X .SXT, OT /!I 1, KlllX/!12, BMX /KMX, ALU/ AND"
"RAMX/D, AMX/RAMX, KMX /U, E'"'XIKMX, ALU/XOR"
"RAMX/D, AMX/RAMX, BMX/LC, ALU/XOH"
"R AMX/ 0 1 AMX /RA MX, RBMX/O, BMX/ RBMX, ALU I XOR"
• ~AMX /D, AMX/RAMX 1 SPO. R/LOAD. LC, SPO. RC/Ill, RMX /LC, ALU/XOR"
• RAMX ID, AMX/ RAMX, SPO. RI LOAD. LAB, SPO • R AB/ll l , BMX/Lll, ALU/ XOR"
"RAMX/D, AMX /RA,.X, KMX/ll2, BMX/KMX, ALU/[11"
"ALU/!ll ,AMX/RA,.X,RAMX/D,BMX/Lll"
"RAMX/D, AM X/ R AMX, llMX /LC, ALU /[11"
"RAMX/D, AMX/RAMX, RBMX/0, llMX/RBMX 1 ALU/(il I"
"KMX/l' 1, BlllX/K"'X, ALU/B •
"AMX/LA,ALU/A"
"AMX/LA, KMX/!11, BMX/K MX 1 ALU/ A+B"
"ALU/ A+B+ 1, AMX/LA, l\MX/KMX, K"X/111"
"AMX/LA, KMX/l' 1, BMX/KMX, ALU/ A+B • RLOG"
"AMX /LA, BMX/ LB, A LU/ A+B •
"ALIJ/ A+B, AMX/LA, BMX/LC"
"ALU/A+B+l ,AMX/LA,B"IX/LC"
"ALU/ A +B+PSL. C, A 111 X /LA, BMX/LC"
•ALU/ A+B, Al"X/LA, BMX/RBMX, RBMX/C"
"AMX/LA, l<Br.X/D, BMX/RBMX, ALU/ A•B"
• AMX/LA, RBMX/D, BMX /RBMX, ALU/ A-B-1"
"AMX/LA, KMX/@11 1 BMX/KMX, ALU/ A•B"
"AMX/LA,KMX/!11,BMX/KMX,ALU/A•B-1"
"AMX/ LA, KM X/ !I 1, BMX/104X, ALU I A•B. RLOG"
"ALU/ A•B, AtoX/LA, BMX/LC"
•ALU/ A-B, AMX/LA, BMX/RBMX 1 RBMX /O"
•ALU/ A•B-1, AMX/LA, BMX/RBlllX, RBMX/0"
"AMX/LA, llMX/!11, BMX/KMX, ALU/ AND"
•ALU/ AND, AM X /LA, BMX/LC"
• AMX/LA ,KMX/@I 1, BMX/KMX, ALU/ ANON OT"
"AMX/LA, BMX/MA5K, ALU/ ANDNOT"

en
-<
en
-f
m
3:

:::D

0
0
cm

3:
l>

:::D

n
0
2

::!

ALU-LA.OR.Kil
ALU-LA. XOR• LC
ALU-LA Cl D
ALU-LA [ l LB
ALU-LAllO
ALU-LB
ALU-LC
ALU-NOT. D
ALU-NOT.Kil
ALU-NOT.RC[]
ALU-PACK.f"P
ALU-PC
ALU-0
ALU-0 (ll)
ALU-O+K Cl
ALU-O+K Cl +1
ALU-O+LB
ALU-O+LB+l
ALU-O+LC
ALU-O+LC+l
ALU-O+LC+PSL. C
ALU-O+MASK
ALU-O•D
ALU-0•0•1
ALU-O•K Cl
ALU-O•LB
ALU-O•LC
ALU-O•MASK• 1
ALU-0.0XTIJ
ALU-0.0XT!l+D
ALU-0.0XT Cl +D+l
ALU-0.0XTCJ +K Cl
ALU-0. OXT [ l •D
ALU-0.0XT!l ·K Cl
ALU-0.0XT!l .ANDNOT.K []
ALU-0.0XTCJ .OR.K[J
ALU-0.0XT!l.OR.D
ALU-0.AND.D
ALU-0.AND.K CJ
ALU-0. ANDNOT. K [ l
ALU-0. AN Oh OT. MASK
ALU-0. ANONOT. R [ l
ALU-0.0R.K Cl
ALU-0.0R.LC
ALU-0.0RNOT.K[J
ALU-0.SXT[J
ALU-0.SXT [] +K Cl
ALU-0.SXT Cl +LB
ALU-0.SXTll+LB+l
ALU-0.SXT!l+PC

•ALU/OR, AMX/LA, BMX/KMX, KMX/111 •
• AMX/LA, BMX/LC, ALU/XOR"
• AMX I LA, RBMX/ D, BMX/RBMX, ALU /Ii 1"
• AMX/LA, BMX/LB, ALU/111"
"AMX/LA, RBMX/O, BMX/ RBMX, ALU /Ii 1"
"BMX/LB, ALU/B"
"llMX/LC,ALU/B"
• ALU/NOTA, AMX/ RAM X, RAMX ID"
"BMX /J< MX, KMX/ fill, ALU /OR NOT, AMX I RAM X • OXT, OT /LONG•
• SPO • R/LOAD. LC, SPO •RC/fill, BMX I LC, AMX /RAM X • 0 XT, OT /LONG, ALU/ORNOT •
• BMX/PACKE.D. f"L, ALU I B"
• BMX/PC, ALU/B"
"RAMX/O, AMX/RAMX, ALU/ A•
"RBMX/Q, BMX/RBMX, ALU/B"
• RAMX/0, AMX/RAMX, KMX/I! 1, BMX/KMX, ALU/ A+B"
"ALU/ A+B+ 1, AMX/RAMX, RAMX/Q, BMX/KMX, KMX/I! 1"
• RAMX /0, AMX /RAMX, BMX /LB, A LU I A+B"
• RAMX/O, AMX/RAMX, BMX/LB, ALU/ A+B+l"
• RAMX /Q, AMX/R AM X, B"'X/LC, A LU/ A+B"
•ALU/ A+B+ 1, AMX /RAMX, RAMX/Q, BMX/LC"
•ALU/ A+B+PSL. C, AMX /RAMX, RAMX /Q, BMX/LC"
"ALU/ A+B, AMX/RAMX, RAMX/0, BMX/l'ASK •
"RAMX/O, AMX/RAMX, RBMX/D, B"X/RB"X, ALU/ A•B"
•ALU/ A•B•l, AMX/RAMX, RAMX/O, llMX/RBMX, RBMX/D"
"RAMX/O, AMX/RAMX, KMX/@11, BMX/KMX, ALU/ A•B"
"RAMX/Q, AMX/RAMX, llMX/LB, ALU/ A•B"
• RAMX/Q, AMX/RAMX, BMX/LC, ALU/A•B"
"ALU/ A•B•l, AMX/RAMX, RAMX/O, Bl'X/MASK •
"RAMX/0, AMX/RAMX • OXT, DT /f!l 1, ALU/ A•
•ALU/ A+B, AMX/RA"'X. OXT, DT /Ii 1, BMX/RBMX, RB"X/D, RAMX/O"
•ALU/ A+B+ 1, AM X/RAMX • OXT, OT/ 1!1, BMX I RBMX, RAMX/O, RBMX/D"
"ALU/ A+B, AMX/RA"'X. OXT, OT Ifill, RAMX/O, BMX/KMX, KMX/1!12 •
"ALU/ A•B, RAMX/O, AMX/RAMX. OXT, DT /Ill, BMX/RBMX"
"ALU/ A•B, AMX/RAMX. OXT, DT /!ill, ~AMX/O, BMX/KMX, KMX/1!2"
•ALU/ ANON OT, AMX/RAMX. OXT, OT /Iii 1, RAMX/Q, BMX/KMX, KMX/112"
"ALU/OR, AMX/RAMX • OXT, OT /Ii 1, RAMX/Q, BMX/KMX, KMX/1!12 •
•ALU/OR, AMX/RAMX. OXT, OT /fl.1, RAMX/O, BMX/RBMX, RBMX/O"
"AMX/RAMX ,RAMX/Q, BMX/RBMX, RBMX/D, ALU/ ANO"
• RAMX /0, AMX/ RAMX, K MX/111, BMX/ K MX, ALU I ANO"
"RAMX/O, AMX/RAMX, KMX/li 1, B/llX/KMX, ALU/ ANDNOT"
• RAMX/0, AMX/RAMX, BMX/MASI<, ALU/ ANDNOT"
"ALU I ANO NOT, AMX I RA MX, RAI' X/Q, BMX/LB, SPO. R /LOAD• LAB, SPO. RAB/till"
"RAMX/O, AMX/RAMX, KMX/tll, BMX/KMX, ALU/OR"
"RAMX/O, AMX/RAMX, BMX/LC, ALU/OR"
"ALU/ORNOT, AMX/RAMX, RAMX/0, B"X/KMX, K"X/!i 1"
"ALU/ A, AMX/RA"X. SXT, DT /IH, RAMX/0"
"RAMX/0, AMX/RAMX. SXT, DT /Ii 1, KMX/fa2, BMX/IO•X, ALU/A+B"
"RAMX/Q, AMX/RAMX. SXT, DT/IH, ~MX/l.8, ALU/ A+B"
• RAMX/O, AMX/RAMX. SXT, DT /~ 1, B~X/LB, ALU/ A+B+l"
• RAMX/Q, AMX/RAMX. SXT, DT /Ii 1, B"XIPC, ALU/ A+B•

....~
m
3::
3::

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n0
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I•

ALU-0.SXTCJ .ANONOT.K Cl
ALU-0 •XOR. 0
ALU-0.XOR.K CJ
ALU-0. XOR. LC
ALU-0.XOR.RCCJ
ALU-0 Cl D
ALU-II COST)
ALU-RC SC) .ANONO'f.K Cl
ALU-RCSPl )+K Cl .RLOG
ALU-RCCSC)
ALU-RC[)
ALU-RLOG
ALU-R II
ALU-RCl-KCl
ALU-R CJ .ANO.K CJ
ALU-R ll .ANO.LC
ALU-RI l . ANON OT• K CJ
ALU-RCJ .ANONOT.MASK
ALU-RCJ.OR.KCJ
ALU-R[J .ORNOT.K Cl
ALU-R CJ .XOR.KC J

"ALU/ AND NOT, AMX /RAJlllX • SXT, RAM X/0, BM X/ K MX, KMX/@12, OT
1•
"RAMX /0, AMX/RAMX, BMX/RBMX, RBIOX/D, ALU/XOR"
"RAMX/0, AMX/RAMX, IO~X/ll 1, BMX/KMX, ALU/XOR"
"RAMX /0, AMX /kAfl'X, BMX I LC, A LU/ XOR"
• RAMX /0, AMX/ RAMX, SPO • R /LOAD. LC, SPO. RC/'1 , BMX/LC, ALU/ XOR•
"RAMX /0, AMX/RA MX, RBM X/ D, BMX /RBMX, ALU/IH"
"SPO. AC/LOAD• LAB, SPO. ACN 11 /DST. OST, AMX/LA, ALU/A•
"SPO. AC/LOAD• LAB, SPO. ACN I SC, AMX I LA, K"' X/ll 1, BMX/KMX, ALU/ AND NOT"
"SPO. AC/LOAD. LAB, SPO. ACN/SP 1 .SPl ,AMX/LA, KMX/111, BMX/KMX, ALU/A+B. RLOG"
"SPO/LOAO. LC. SC, BJlllX/LC, ALU/B"
"SPO. R/LOAD •LC, SPO. RC/'1, BMX/LC, ALU/B"
• BMX /0, ALU /B, MSC /READ. RLOG"
"SPO. R/LOAD. LAB, SPO • RAB/U, AMX/LA, ALU/ A"
• SPO. RI LOAD. LAB, SPO. RA B/tll, A"X /LA, KM XI• 2, B'4X/KMX, ALU/ A-B"
"SPO. R /LOA 0. LAB, SPO. RAB/Ii 1, A MX I LA, KMX/112, BMX/KMX, ALU/ ANO"
"SPO. RI LOAD. LAB, SPO. RAB/fill, A MX/LA, BMX/LC, ALU/ AND"
"SPO. R/LOAD •LAB, SPO. RAB/ii 1, AMX/LA, KMX/ll2, BMX/KMX ,ALU/ANDNOT"
"SPO. RI LOAD• LAB, SPO. RAB/ii 1, A MX /LA, BMX/MASK, ALU/ ANON OT"
"SPO. R /LOAD. LAB, SPO. RAB/ ill , A MX /LA, K MX/•2, BMX/K MX, ALU/OR"
"ALU/OR NOT, A,.X /LA, BM X /K MX, SPO. R /LOAD. LAB, SPO •RAB/ill, KMX/ll2"
"SPO • R /LOAD. LAB, SPO. RAB/@11, AMX/LA, KMX/@12, BMX /KMX, ALU/XOR"

CACHE.P-DCJ
CACHE CJ -D
CACHE-DCOUAO)
CACHE-D. INST. DEP
CACHE-D CJ
CACHE-D Cl •LI\
CACHE-0 CJ. NOCHK

"YAK/NOP, MCT /wR !TE. P, OT /@11, DK/NOP"
"YAK/t.OP ,MCT /WR !TE. Y. wCHK, MSC/Ii 1, DK /NOP"
"MCT /EXTWRITE. P, LONG, YAK/NOP, DK/NOP"
"YAK/NOP, MCT /WRITE• Y. WCHK, OT /INST• DEP, DK/NOP"
"YAK/NOP,MCT/WRITE.V .WCHK ,DT/lll ,DK/NOP"
"YAK/l<OP, JlllCT /LOCK WRITE. Y. XCHK, OT /@11, DK/NOP"
"YAK/l<OP, MCT /WRITE. Y. NOC HK, DT /111, DK/NOP"

D&O-D+Q
D&RC Cl-PC
D&YA-ALU
D&YA-D+LC
O&YA-D+Q
D&YA-0-K[J
06. VA-LA
D&VA-LB
O&VA-0
D&YA-O+LB.PC

"RAMX/D, AMX/RAMX, RBMX/O, BMX /llBMX, ALU/ A+B, SHF' I ALU, DK/SHF, OK/SHF"
"BMX/PC ,ALU/B ,SHF I ALU, DK/SHf ,SPO. R/WRITE. RC, SPO. RC/ill"
"YAK/LOAD, SHf I ALU, DK/SHF"
"RAMX/O, AMX/RAMX, BMX/LC, ALU/ A+P., YAK/LOAD, SHF /ALU, DK/SHF"
"D-D+O, YAK/LOAD"
"RAMX/D, AMX/RAMX, KMX /ii 1, BMX/KMX, ALU/ A-B, YAK/LOAD, SHF /ALU, DK/SHF"
"AMX/LA, ALU I A, YAK/LOAD, SHf I ALU, DK/SHF"
"BMX/LB, ALU/B, YAK /LOAD, SHF I A LU, DK I SHF"
"RAMX/0, AMX/RAMX, ALU/ A, YAK/LOAD, DK/0"
"RAMX /0, A MX /R AMX, BMX /PC. OR. LB, ALU I A +B, YAK /LOAD, SHF I ALU, DK/SHP'"

D Cl-CACHE
DCl-CACHE.IBCHK
DCJ-CACHE.LI\
DC] _CACHE. l<OCHK
DCl-CACHE.P
DC J -CACHE. wCHK

"YAK/NOP, MCT/READ. Y. RCHK, OT /lll, DK/NOP"
"YAK/NOP, MCT /READ. Y. I BCHK, DT/1111, DK/NOP"
"VAK/NOP, MCT I LOCK READ. Y. WCHK, DT I til, DK I NOP"
" YAK IN 0 P , MC TIRE AD • V • N0 CH K , D T /Ii 1 , DK IN OP"
"VAK/NOP, MCT /READ. P, OT /111, DK/NOP"
"VAii/NOP, MCT /READ. Y. WCHK, OT /Ill, DK/NOP"

(I)

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::0

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o_o
D-O+Kll+l
D-O+LC+ 1
o_o-o
D-O·K CJ
o_o-o
0_0-0-1
D-ACCE L&.SYNC
D-ALU
D-ALU (FR AC l
D-ALU.LEfT
D-ALU. LEFT2
D-ALU.LEfT3
D-ALU. RIGHT
D-ALU.1-!IGHT2
D-BLANK
D-CACtff. BST. Dl::P
D-CACHr.• LK [J
o_cACHE. WCHK ( l
D-CACHF l l
D-DCHACl
U-DHCJ
D-D+K ll +1
D-D+LB
D-D+LC
D-D+LC+PSL.C
D-D+O
D-D+O+ I
D-D·Kl]
D-D·LC
D-D·a
D-D·O·I
D-D.OXT Cl
D-D.OXTCJ+KCJ
D-D.OXT[J+a
o_o.OXTCJ+a+l
lJ.D.OXTl) .ANDNOT.K[)
o_o.OXT(J .OR.a
D-D.OXT(l .XOR.a
D-D.OXT[) .XOR.RC[]
D-D.AND.Kll
D-D.AND.K l l .LEFT2
o_o.oo.K [).RIGHT
D-D.AND.LC
0-D.A~O.MASK

ll-D. AND. 0
D-D.AND.RC[)
D-D.ANONOT.KCI
D-D. ANONOT. LC
D-D. ANON OT. PSoZ
D-D.Al'jQNOT.a

"DK/CLR"
• AMX/RAMX. OXT, OT /LONG, KMX/lil 1, BllX/KMX, ALU/ A+B+l, SHF I ALU, DK/SHF"
• AMX/RA~X. OXT, 01 /LO"G, BMX/LC, ALU/ A+B+ 1, SHF I ALU, DK/SHF"
• A"X/RAIO. OXT, DT /LONG, RBMX/D, B .. X/PBMX, ALU/ A•B, SHF I ALU, DK/SHF"
• AMX/l<A"X, OXT, DT /LONG, KMX/111, BMX/KMX, ALU/ A•B, SHF I ALU, DK/SHF"
"AMX/RAMX. OXT, DT /LONG, Rfl~ Xia, BMX/RBMX, ALU I A-B ,SHF I ALU, DK/SHF"
"ALU_o-o-1,D-ALU"
"DK/ ACC'EL, ACF I SYNC"
"SHI' I ALU, DK/SHF"
"SHI' I ALU, DK/ SHF, FL"
"SHf/LEfT,DK/SHF"
"SHF I ALU. DT, DT /LONG, DK/SHF"
"SHF /LEFT3, DK/SHf"
"SHF /RIGHT, DK/ SHF"
• SH FIR I GH12 , DK IS H ~· "
"D-K C.201"
• VAK/NOP, MCT /l<EAD, V. I BCHK, DT I INST. Dt.P, DK /NOP•
"V AK /NOP, MCT I LOCK READ. V. wCHK, "SC /ii 1, DK/NOP"
"VAK It.OP, MCT /READ. V. WCHK, MSC/ill, DK/NOP"
"VAK/NOP, MCl /RE,.D. V. RCHK, MSC/1!11, OK/NOP"
"RAMX/D, AMX/R AMX, ALU/ A, SHF I ALU, OK/SHF. FL"
"RAMX/D, AMX/RAMX, KMX/1!11, BMX/Kl'IX, ALU/ A+B, SHF I ALU, DK/ SHF •
"RAMX/D, AMX/l<AMX, KMX/{11, BMX/KMX, ALU/ A+B+ 1, SHF / ,t,LU, DK/SHF"
"RAMX/D 1 AMX/PAMX, BMX /LB, ALU/ ,t,+e, SHF I ALU, DK/SHF •
"RAMX/D, AMX/RAMX, BMX/LC, ALU/ A+B, SHF I ALU, OK/SHF"
• RAMX/D, AMX/RAMX, BMX/LC, ALU/ A+IHPSL. C, SHF I ALU, DK/SHF"
"RAMX/D, AMX/RAMX, RBllX/0, EIMX/Rf MX, ALU/ A+B, SHF I ALU, OK/SHF"
• RAMX/D, AMX/RAMX, RBMX/O, BMX/RBMX, ALU/ A+B+ 1, SHF I ALU, OK/SHF"
• RAMX/D, AMX/R.lMX, KMX /li I, FlMX/K MX, ALU/ A•B, SHF I ALU, OK/SHt•
• RA"1X/O, AMX/RAMX, BMX /LC, ALU/ A•B, SHf I ALU, DK/SHI'"
• RAMX /0, AMX/RAMX, RBMX/O, B"1X/R B"X, ALU/ A•B, SHF I ALU, DK/SHf"
• R AMX ID, AMX/ R AMX, RBMX /0, BMX/ RB" X, ALU/ A-B-1, SHF I ALU 1 DK/ SHF"
"l<AMX/O, AMX/RAMX. OXT, OT I "1, ALU/ A, SHF I ALU, DK/SHF"
"RAMX /D, AMX/RAMX. OXT, OT /Ii 1, KMX/lil2 1 BMX/KMX, ALU/ A+ll ,SHF I ALU, OK/SHF"
•ALU/ A+B, AMX/RA"IX. OXT, OT /{11, B"1X/RBMX, RBMX/Q, D-ALU"
"RAMX/D, AMX/RAMX. OXT, OT /fi 1 1 BMX/PBMX, ALU/A+B+ 1, D-ALU •
• RAMX /0, AMX/RAMX. OXT, OT 1!11, K"X/{12, BMX/KMX, ALU/ ANO NOT, SHF I ALU, DK/SHI'"
•RA" XI 0, A MX/R AMX. OXT, OT/ !11, RBMX /0, BMX/RBMX, ALU /OR, SHF I ALU, DK/SHF"
•DK I SHF, ALU I XOP, SHf' I ALU, Af'IX /R AMX. OX T, RA MX/D, OT /Ill, RBMX/Q, BMX/RBMX •
• RAMX/D, AMX/RAMX. OXT, DT /Ii 1, SPD 0 1< /LOAD. LC, SPO, RC/t2, BMX/LC, ALU/XOR, SHI' I ALU, Dt<ISHF"
"RAMX/0, Al'IX/RAMX, KMX/111, BMX/K"'X, ALU/ AND, SHF I ALU, OK/SHF"
"RAMX/D, AMX/l<AMX, K"Xltl 1, BMX/KMX, ALU/ AND, SHF I ALU, LlT, OT /LONG, DK/SHF"
"l<AMX/ D, AMX/RAMX, KMX/fi 1, BMX/KMX 1 ALU/ ANO, SHF /RIGHT, OK/SHI'•
"R AMX ID, AMX /RAMX, BMX /LC, ALU/ A NO, SHF I ALU, OK/SHF"
"RAMX/D, AM X/RAMX. FlMX l"ASI<. ALU/ ANO, SHF I ALU, OK /SHF"
"f'AMX/D, AMX/RAMX, RRMX/a, BMX/RBMX, ALU/ AND, SHF I ALU, DK/ SHf •
• RAMX/O, AMX/PAMX, SPO, R/LOAO. LC, SPO. RC/lil 1, BMX/LC, ALU/ ANO ,SHF I ALU, DK/SHF"
"RAMX/D, AMX/l<AMX, KMX /lil I, BMX/J<MX, ALU/ ANON OT, SHF I ALU, DK/SHF"
"RA"'X /0, AMX/RAMX, BMX/LC, ALU/ ANDNOT, SHF I ALU, DK/SHF"
• DK/SHF, ALU/ ANON OT, AMX/RAMX, RAMX/D, BMX/KMX, KMX/, 4, SHI' I ALU"
• RAMX/0, AMX /RAMX, RBMX /a, B"XIRBMX, ALU/ ANDNOT, SHF I ALU, 01</SHF"

(I)

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o_o. ANO NOT. RC [ J
D-D.LEFT
o_o.LEFT2
o_D.OR.ASCll
D-D.OR.K[l
D-D.OR.PSwC
D-D.OR.PSWV
D-D.OR.Q
o_D.oR.RClJ
D-D.OR.R!l
D-D. OR NOT. l'ASK
D-D.RIGHT
o_O.RIGHT[BJ
D-D.RIGHT2
o_o.SWAP
o_o.SXTCJ
D-D.SXTCJ .RIGHT
D-D.XOR.KCJ
o_o. XOR .LC
D-D.XOR.o
D-DAL •NORM
D-DAL.SC
o_o CJ
J
o_o Cl MASK
D-DlJQ
D-INT 0 SUP<
D-K CJ
D-KlJ.RIGHT
D-K [) .RIGHT2
D-LA
D-LACFRACJ
D-LA+D+PSL.C
D-LA-0
D-LA-K!J
D-LA.AND.KCJ
D-LA •RIGHT
D-LB
D-LB.PC
D-LC
D-LCCFRAC)
D-NOT. 0
o_NOT.KCJ
D-NOT .MASK
o_NOT .Q
D-t<OT.R CJ
D-PACK.FP
D-PACK. P'P. LEP'T
D-PC
D-PC.LEFT
o_o

0'1
0'1

"RAMX/0 1 AMX/ R AMX, SPO. RI LOAD. LC, SPO • RC/@11, BM X/LC 1 ALU/ ANON OT 1 SHF I ALU 1 OK/ SHF"
"DK/LEFT"
"DK/LEFT2"
"D-D.OR.K!.30J"
"RAMX/D, AMX/RAMX, KMX/fl 1, BMX/KMX 1 ALU/OR, SHF I ALU, DK/SHF"
"DK /SHF, ALU/OR 1 AMX/RAMX, PAMX/0 1 BMX/KMX 1 KMX/ .1 1 SHF I ALU"
"OK/ Slff, ALU/OR, AMX/RAMX, RAMX ID 1 BMX/K MX 1 KMX/•21 SHF I ALU"
"RAMX/D I AMX/RAMX I RRMX/Q I l\MX/RBMX I ALU/OR I SHF I ALU I DK/SHF"
• RAMX/D I AMX/RAMX I SPO. R/LOAD. LC I SPO. RC/Iii 1 I BMX/LC I ALU/OR I SHF /ALU I OK/SHP'"
"ALU/OR 1 AMX IRA MX 1 RAMX/O, BMX/LB 1 SPO. R /LOAD• LA 8, SPO. RABI• 1, DK/ SHP'"
"RAMX /0, AMX/RA MX, BMX/ MASK, ALU /OR NOT, SHF I ALU, DK/ SHF"
"DK/RIGHT"
"RBMX/D, BMX/ RBMX, ALU I B, SHF /R l(;HT 1 OK/ SHF"
"DK/RIGHT2"
"DK/BYTE.SWAP"
"RAMX/D ,AMX/RAMX. SXT, OT /II 1, ALU/A, SHF I ALU, DK/SHF"
"RAMX /D, AMX/ RAlllX. SXT 1 DT /IH, ALU/ A, SHF /RIGHT 1 DK/ SHF"
"RAMX/D, AMX/RAMX, KMX/111, BMX/KMX, ALU/XOR, SHF I ALU, OK/SHP'"
"RAMX/D I AMX/RAMX I BMX/LC I ALU/XOR. SHF I ALU I DK/SHP'"
"R AMX /0, AMX/RAMX 1 RBMX/O, BMX /RBI' X, ALU/XOR, SHF I ALU, OK/ SHF"
"DK/DAL.SY"
"DK/DAL.SC"
"RAMX/D, AMX/ RAMX, K MX 1112, BMX/KM X, ALU/Ii 1 1 SHP' I ALU 1 OK/SHF"
"RAMX /0 1 AMX/RAMX, BMX/M ASK, ALU/ IH 1 SHF I ALU, OK/ SHF"
"RAM X/O, AMX/RAMX, RBMX /0 1 BMX/RBMX, ALU /(11, SHF I ALU, DK/ SHF"
"MCT /READ. INT. SUM, DK/NOP"
"KMX/111, BMX/IOU, ALU/B, SHF I ALU, OK/SHF"
"K MX/"1, BMX/KMX, ALU/8, SHF /RIGHT, DK /SHF"
"K MX/fl 1, BMX/KMX, ALU /B, SHF /II 1GHT2, OK/ SHF"
"AMX/LA 1 ALU/ A, SHP' I ALU 1 OK/ SHF"
"AMX/LA, ALU/ A, SHP' /ALU, DK/SHF •FL"
"AlllX/LA, RBMX/D, BMX/RBlllX, ALU/ A+B+PSL. C, SHF/ ALU, DK/SHF"
"011/SHF, ALU/ A-B, AMX/LA, BMX/RBMX, RBMX/O, SHF /ALU"
"AMX/LA 1 KMX/(11, BMX/KMX, ALU/A-8 ,SHF/ALU ,DK/SHP'"
"AMX/LA, KMX/'1, BMX/KMX, ALU/ A NO, SHP' I ALU 1 DK/ SHF"
"AMX/LA 1 ALU/ A, SHP' /RIGHT, DK/SHF"
"BMX/LB, ALU/B 1 SHP' /ALU 1 DK/SHP'"
"BMX/PC. OR. LB 1 ALU/8 1 SHF I ALU 1 DK/SHF"
"BMX/LC, ALU/B, SHP'/ ALU, OK/SHF"
"l\MX/ LC, ALU/8 1 SHP' I ALU, OK/SHF. FL"
"RAMX/D, AMX/RAMX, ALU/NOTA, SHF I ALU, DK /SHP'"
"KMX/il 1 1 BMX/KlllX, AMX/RAMX • OXT, OT/LONG ,ALU/ORNOT, SHF I ALU, OK/SHF"
"BMX/MASK, AMX/RAMX • OXT, OT /LONG 1 ALU/ORNOT, SHF I ALU, DK/SHF"
"RAMX/Q, AMX/RAMX, ALU/NOTA, SHF I ALU, DK/SHF"
"LA-RA CU l ,AMX/LA I ALU/NOTA. D-ALU"
"BMX/PACKED .FL 1 ALU/B,SHF I ALU, DK/SHF"
"BMX/PACKED.FL, ALU/B ,SHF /LEFT, DK/SHF"
"BMX/PC, ALU/B, SHP' /ALU, DK /SHP'"
"BMX/PC 1 ALU/B, SHF /LEFT, DK/SHF"
"DK/Q"

(I)

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0
0

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o_ocrRACl
D-0+0
D-O+K Cl
o_o+LB
D-O+PC
o_o-o
o_a-0-1
D-O·K [ l
D-O•KCl•l
D-O•PCSV
o_O,OXTCJ
o_a,AND.11 CJ
o_a,AND.LC
o_o. AND. MASI\
0_0,AND,RCCl
D_O,ANDNOT,D
0_0,ANONOT,K[J
D.O, Al'.iDllOT, l'ASK
D-0, At.ON OT, PSIOC
o_O,ANDllOT,PSWN
o_o. ANON OT. PSlliZ
o_a,LEFT
o_a. OR. K []
o_O,OR,PSWC
O_O,OR,RCCl
o_o. OR NOT. MASI\
O_O,RIGHT
o_O,RIGHT2
D-0,SXT [ l
o_o,xoR.RCCJ
o_o CJ o
D-OCJll Cl
D-OCJMASI\
D-RCPRll+l l
D-RCSC)
D-RCSP1+1)
D-RC CSC)
D-RCCl
D-RLOG
D-RLOG,RIGHT
D-R Cl
D-RCJCFRACl
D-RCJ ,AN0,11 Cl
D-R Cl , OR, KC l
D-RCl ,ORNOT,K Cl

"RAMX/Q, AMX/RAMX, ALU/ A, SHr I ALU, DK/SHF. rL"
"RAMX/Q, AMX/RAMX, RBMX/D, BMX/RBMX, ALU/ A+B, SHF /ALU, DKISHF"
"RAMX/O, AMX/RAMX, K MX/(i 1, BM X /KMX, ALU/ A+B, SHF I ALU, OKI SHF"
• RAMX/Q, AMX/RAMX, BMX/LB, ALU/ A+B ,SHF I ALU, OK/SHF"
"RAMX/O, AMX/RAMX, BMXIPC, ALU/ A+B, SHr I ALU, OK/SHF"
"RAMX/O, AMX/RAMX, RBMX/D, BMX/RBMX, ALU/ A•8, SHF' I ALU, OK/SHr"
"RAMX/O, AMX/RAMX, RBMX/D, BMX/~BMX, ALU/ A•B• 1, SHF I ALU, OK/SHF"
• RAMX/O, AMX/RAl'X, KMXI~ 1, BMX/KMX, ALU/ A•B, SHF I ALU, DKISHF"
"RAMX/O, AMX/RAl'X, KMX /till, BMX/Kl'X, ALU/ A•B• l , SHF/ ALU, DK/SHr"
"RAMX 10, AMX/R AMX, BMX/ 0, MSC/READ, RLOG, A LU I A•B, SHr I ALU, OK/SHF •
"RAMX/O, AMXIRAMX, OXT, OT 1111, ALU/ A, SHF I ALU, DK/SHF"
"RAMX/0, AMX/RAMX, KMX/U, BMX/KMX, ALU/ AND, SHF I ALU, DK/SHF"
"RAMX/O, AMX/RAl'X, BMX/LC, ALU/ ANO, SHF I ALU, DKISHF •
"R AMX/Q, Ai'\ XI fl AMX, t!MX I MASK, ALU I AND, SHr I ALU, DK/ SHF'"
"RAMX/Q, AMXIRAMX, SPO, R/LOAO, LC, SPO, RC/Ill, BMX/LC, ALU/ AND, SHF I ALU, DK/SHF"
"RAMX/Q, AMX/RAMX, RBMX/D, BMX/FIBl'X, ALU/ ANDNOT, SHF I ALU, 01\/SHF"
"RAMX/0, AMX/RAMX, KMX/@11, BMX/J(MX, ALU/ ANONOT, SHF I ALU, OK/SHF'"
"RAM X/Q, AMX/ RA MX, BMX/ MASK, ALU I ANO NOT, SHF I ALU, DK/ SHF"
"DK I SHF, ALU/ ANON OT, AMX /R AMX, RAMX IQ, BMXIK MX, KMX/, 1, SHF I ALU"
"Dl\/S11F, ALU/ ANDNOT, AMX/RAMX, kAl'X IQ, BMX/KMX, KMX/, B, SHr I ALU"
"OK/SHf', ALU/ ANON OT, AMX/RAMX 1 RAl'X IQ, BMX/KMX, KMXI, 4, SHF I ALU"
"RAMX /Q, AMX IR AMX, ALU/ A, SH F' /LEFT, DK/ SHF"
"R AMX/Q, A MX/ RAMX 1 PIX /(11, BM XIKM X, ALU/OR, SHF' I ALU, DK I SHF"
"DKISHF', ALU/OR, AMX/RAMX, RAMX/0, BMX/KMX, KMX/, 1, SHF' I ALU"
"HAMX/Q, AMX/RAMX 1 SPO, R/LOAO, LC, SPO, RC/111, BMX/LC, ALU/OR 1 SHF I ALU, OKISHF'"
"RA MX/Q, AMX/ RAM X, BMX I MASK, ALU I OR NOT, SHF' I ALU, OKI SHF"
"RAMX/Q, AMX/RAMX, ALU/ A, SHF' /RIGHT, OK/SHF'"
"RA MX IQ, AMX /R AMX, ALU/ A, SHF IR IGHT2, OKI SHF"
"RAMXIO, AMX/RAMX, SXT, OT Ital, ALU/ A, SHF /ALU, DKISHF"
"RAMX/O, AMX IRAMX, SPO, RI LOAD, LC, SPO, RC/ii 1, BMX/LC, ALU/ XOR ,SHF I ALU, DK/SHF"
• HAMX /0, AMX I RAMX, RBMX/D, BMX /RB MX, ALU/ 1!11, SHF' I ALU, OK I SHr"
"ALU/till, SHf' I ALU, DK/SHF, 8MX/KMX, KMX/li2, AMX/RAMX, RAMX/O"
"RA MX 10, AMX/R AMX, BMX /IOASK, ALU 1111 , SHF I ALU, OKI SHF"
•spa. AC/LOAD. LAB, SPO. ACN/PRN+ 1, AMXILA, ALU/ A, SHP' I ALU, OK/SHF'"
"SPO. AC/LOAD. LAB, SPO. ACN/SC, AMX/LA, ALU/ A, SHr I ALU, 01\I SHr"
"SPO •AC/LOAD, LAI!, SPO, ACN/SP 1+1, AM XI LA, ALU/ A, SHF I ALU, OK/SHr"
"SPO/LOAD, LC, SC, BMX/LC, ALU/B, SHI' I ALU, OK/SHF"
"SPO. R/LOAO, LC, SPO, RC/f!ll, BMXILC, ALUIB, SHf I ALU, DK/SHr"
"8MX/0, MSC/Rf.AD, RLOG, ALU/B, SHr I ALU, OK/SHF"
"BMX/O, MSC/READ, RLOG, ALUIB, SHr /R 1 GHT, DK/ SHF'"
"SPO, RI LOAD, LAB, SPO, RAB/tll, AMX/LA, ALU/ A, SHr I ALU, OK/SHr"
•spo. RI LOAD. LAB ,SPO. RAB/lil, AMX/LA, ALU/ A, SHF I ALU, OKISHF'. rL"
"SPO, RI LOAD, LAB, SPO. RAB/ill, AMX/LA, KMX/1!2, BMX/KMX, ALU/ ANO, SHP' I ALU, DK/SHF"
•spa. R/LOAO. LAB, SPO. RAB/ii 1, AMX/LA, KMX/1!12, BMX/KMX, ALU/OR, SHr I ALU, DK/SHF"
"LAB.R [I! 1 l , AMX /LA, BMX /K MX, KMX I (i2, ALU /OR NOT, D-ALU"

EALU-DCEXP)
EALU-rE
EALU-K Cl
EALU-R Cl CEXPl

• RAMX/0, AMX/RAMX, EBMX/ A"X, EXP, EALUIB"
• EBMX/FE, EALU/B"
"KMX/(11,EBMX/KMX,EALU/8"
• SPO, R /LOAD, LAB, SPO. RAB/lit, A"X I LA, EBMX/ AM X, EXP, EALUI B"

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EA LU-SC
EALU-SC+FE
EALU-SC+K Cl
EALU-SC•FE
EALU-SC•K l l
EA LU-SC, ANDNOl, Kl l
EALU-STATE

"EALU/A"
"EBMX/FE, EALU/ A+B"
"KMX/l!l 1, EBMX/K MX, EALU/ A+B"
"EBMX /FE, EALU/ A•B"
"l<MX/l!l 1, EBMX/KMX, EALU/ A•B"
"l<MX/l!l 1, EBMX/l<MX, EALU/ ANON OT"
"EALU/ A, MSC/LOAD, STATE"

FE'5C-K CJ
FE-OCA)
FE-DC EXP)
FE-EALU
FE-I< Cl
FE-LAC EXP)
FE-NABS (SC•FE)
FE-NABS CSC•LA (EXP J J
P'E-OCEXPl
FE-R[](l!:XP)
FE-SC
FE-SC+l
FE-SC+P'E
P'E-SC+I< Cl
FE-SC+LA(EXP)
FE-SC•FE
FE-SC•K(l
FE-SC•LACEXP)
FE-SC•SHF, VAL
FE-SC, ANDNOT, FE
FE-SC, ANDNOT, I< Cl
P'E-SC,OR,K Cl
FE-SHF, VAL
FE-STATE

"l<MX/l!ll, EBMX/l<MX, EALU/B, FEK/LOAD, SMX/EALU, SCl</LOAD"
"AMX/RAMX, OX T, OT /LONG, EB"!X I AMX, EXP, EALU /B, FEl</LOAD"
"RAMX/D, AMX/RAMX, EBMX/ AMX, EXP, EALU/B, FEK/LOAD"
"FEK/LOAD"
"l<MX/il 1, EBMX/KMX, EALU/B, FEl</LOAD"
"AMX/LA, EBMX I AMX, EXP, EALU/ B, F t:K/LOAD"
"EALU/NABS ,A•B, EBMX/FE, FEK/LOAD"
"AMX/LA, EBMX/ AMX, EXP, EALU/NABS, A•B, !'EK/LOAD"
"RAMX/Q, AMX/RAMX, EBlllX/ AMX, EXP, EALU/B, FEK/LOAD"
"SPO,R/LOAD ,LAB, SPO, RAB/l!l 1, AMX/LA, EBMX/ AMX ,EXP, EALU/B, FEK/LOAD"
"EALU/ A, FEK/LOAD"
• EALU/ A+ 1, FEK/LOAD"
• EBMX/FE, EALU I A+B, FEK/ LOAD"
"KMX/IH, EBMX/KMX, EALU/ A+B, FEK/LOAD"
• AMX/LA, EBMX/ AMX, EXP, EALU/ A+B, FEK/LOAD"
"EBMX/FE, EALU/ A•B, FEK/LOAD"
"KMX/111, EBMX/KMX, EALU/ A•B, FEK/LOAD"
• AMX/LA, EBMX/ AMX, EXP, EALU I A•B, FEI< /LOAD"
• EBMX/ SHF', YAL, EALU/ A•B, FEK /LOAD"
"EBMX/FE, EALU/ Ar.DNOT, FEK/LOAD"
"KMX/l!ll, EBMX/KMX, EALU/ A ND NOT, F EK /LOAD"
• EALU/OR, EBMX/K MX, KMX/il 1, f EK/LOAD"
• EBMX/ SHF, VAL, EALU/B, P'EK/LOAD"
"MSC/LOAD, STATE, EALU/ A, FEK /LOAD•

lDCSC>-D
lDCl-D
10-DUO,SYNC
ID-D,SYNC

"CID/llRITE,SC"
"CID/llRITE ,KMX, ID, ADDR/l!ll"
"CID/WRITE, KMX, ADS/I BA, KMX/SPl ,CON"
"CID/IORITE, KMX, ADS/IBA, KMX/SP 1 ,CON, ACF /SYNC"

KCl

"KMX/ill"

LAB-RC DST)
LAB-RCPRNl
LAB-RCPRN+ll
LAB-RCSCl
LAB-RCSPl l
LAB-RCSP1+1 l
LAB-R 1'RC Cl-0
LAB-R1'RC Cl-O+LC+1
LAB-RlUCCl-0•0
LAB-R1'RC l l-ALU

"SPO, AC/LOAD, LAB, SPO, ACN 11 /DST, DST"
"SPO, AC/LOAD, LAB, SPO, ACN /PRN"
•spa. AC/LOAD. LAB, SPO. ACN/PRN+ 1 •
•spa. AC/LOAD. LAB, SPO. ACN/SC.
•spa. AC/LOAD. LAB, SPO. AC'-/SP 1. SP1.
•spo, AC/LOAD. LAB, SPO. ACN/SP1+1"
"ALU.OCAJ ,LAB-R1'RC[lill-ALU"
•ALU/ A+S+l, AMX/RAMX, OXT, OT/LONG, B"X/LC, SPO, R/LOAD, LA Bl, WRITE, RC, SPO, RC/lill, SHf' I ALU"
•spa. R/ LOAD. LAB 1. WR I TE. RC, SPO. RC /ill, ALU/ A•B, AMX/RAMX. OXT, DT /LONG, BMX/RBMX, RBMX/D, SHP' /ALU.
•spa. R/LOAD. LA Bl. WRITE. RC ,SPO. RC/U, SHF I ALU"

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LAB-R1'RC ll-ALU.RIGHT2
LAB-R 1'RC [ l-D+LC
LAB-R1'RC tl-D. OXT [ l +K tl
LAB-Rl&RC tl-O·K tl
LAB-Rt l
LA-R (OST) 6.LB-R ( SRC)
LA-R ( SP2) 6.LB-R (SP1 l
LA-RA(]
LC-RC(SC)
LC-RC t l
LC-RC(] &R 1-C LA+LB). LEFT
LC-RC Cl &R 1-C LA+LB+PSL. C). LEFT
LC-RC(] &R 1-C LA+LB. RLOG). LEP'T
LC-RC t l&R 1-C LA•LB). LEFT
LC-RC ( l &R 1-C LA•LB, RLOG) .LEFT
LC-RC (J&Rl-ALU
LC-RC tl&Rl-D
LC-RC t J &R 1-LA+K t l
LC-RC Cl &R 1-LA•K l J
LC-RC t l&R 1-LB
LC-RC[J&Rl-0

(J'1

"SPU, R/LOAD. LAB1, WRITE, RC, SPO, RC/til, SHF /RIGHT2"
"ALU-D+LC, LAB-R 1&RC (111 l-ALU"
• ALU-D, OXT Clil2l +I< [1!13 l , LAB-R l&RC [till] .ALU"
"ALU-O•K [1112], LAB-R 1&RC [ 111 l .ALU"
"SPO, R/LOAO, LAB, SPO, RAB/111"

•spa ,AC/LOAD. LAB. SPO. ACN 11/DST. SRC"
"SPO, AC/LOAD. LAB, SPO. ACN/SP2 .SP1"
•spa. AC/LOAD. LA. SPO. RAB/@!.
"SPO/LOAD,LC,SC"
"SPO, H/LOAD. LC, SPO, RC/!11"
• AMX/LA, BMX/LB, ALU/ A+B, SHF /LEFT, SPO, R/LOAD, LC, WRITE, RAB1, SPO • RC/lll"
• Al'!X/LA, BMX/LB, ALU/ A+B+PSL, C, SHF /LEFT, SPO, R/LOAD. LC, WRITE. RAll1, SPO, RC/'1"
• AMX/LA, BMX/LB, ALU/ A+B. RLOG ,SHF /LEF'T ,SPO .RILOAD ,LC. WRITE .RAB1 ,SPO.RC/U •
"AMX/LA, BMX/LB, ALU/ A·B, SHF /LEFT ,SPO, R/LOAD. LC• WRl TE, RA81, SPO • RC/1111"
• AMX/LA, BMX/LB, ALU/ A•B • RLOG, SHF /LEFT, SPO. R/LOAD, LC, WRITE. RAB1, SPO. RC/lll"
"SPO. R/LOAD, LC, WRITE. RABI, SPO. RC/lll, SHF I ALU"
"ALU.D, LC-RC Cfill l &R 1.ALU"
"SPO, R/ LOAD, LC, WRITE, RAB1, SPO. RC/111, SHF I ALU, ALU/ A+B, AMX/LA, BMX/KMX, KMX/112"
"ALU.LA•K [1!121 ,LC.RC[lll]li.Rl-ALU"
"ALU.LB, LC-RC [1!11] &R 1-ALU"
"SPO, R/LOAD, LC, WRITF. RAB1, SPO. RC/lH, SHF I ALU, ALU/ A, AMX/RAMX, RAMX/Q"

N&Z-ALU
N&Z-ALU. V&C-0
N_AMX.Z-TST
PC& VA-ALU
PC& VA-D
PC& VA-D+I< [ l
PC& VA-D•K ( l
PC& VA-D·PC
PC&VA.D.OXT []
PC&VA-D.OXT ll +PC
PC&VA-D.SXTll+PC
PC&VA-K[J
PC&VA.PC
PC&VA-0
PC&VA.O+PC
PC&VA.O·D
PC&VA.O•I< []
PCli.VA.O.SXT[J+PC
PC& VA.RC Cl
PC&VA.R [] .ANDNOT.K Cl

"CCK/NZ-ALU. vc.vc•
"CCK/NZ-ALU. VC.O •
• CCKI N_AMX. Z-T ST. vc_ vc.
"YAK/LOAD, PCK/PC-VA"
"RAMX/D, AMX/RAMX, ALU/ A, VAi< /LOAD, PC!</ PC.VA"
"RAMX/D, AMX/RAMX, KMX/lil 1, BMX/KMX, ALU/ A+B, YAK/LOAD, PCK/PC-YA"
"RAMX/D, AMX/RAMX, KMX/lil 1, BMX/KMX, o\LU/ A•B, V o\K/LOAD, PCK/PC-YA"
• RAMX /D, AMX/RAMX, BM X/ PC, ALU I A•B, V AK/LOAD, PCK /PC-YA"
"RAMX/D, AM X/RAMX. OXT, DT /(il1, ALU/ A, V o\K/LOAD, PCK /PC-VA•
"RAMX/D, AMX/RAMX, OXT, DT/111, BMX/PC, ALU/ A+B, YAK/LOAD, PCK/PC.VA"
"R AMX ID, AMX/RAMX. SXT, OT/ lil, BMX/PC, ALU/ A+B, YAK/LOAD, PCK /PC. VA"
"KMX/ Iii 1, BMX/KMX, ALU/B, VA K/ LOAD, PCK I PC-YA"
"BIO/PC, ALU/I!, YAK/LOAD, PCK/PC-VA"
"RAMX /0, AMX/RAMX, ALU/ A, V AK /LOAD, PCK /PC-YA"
"RAMX/Q, AMX/RA MX, BMX /PC, ALU I A+B, V AK/L'OAO, PCK/PC-VA"
"RAMX /Q, AMX/RAMX, RBMX /D, BMX /RBM X, ALU/ A•B 1 V o\K/LOAD, PCK/PC. VA"
"RAMX /Q, AMX /R AMX, KMX I fill, BMX /K" X, ALU/ A•B 1 YAK/LOAD 1 PCK /PC-YA"
"RAMX /Q, AMX /RAMX, SXT, OT /Iii 1, BMX/PC, ALU/ A+B, V AK/LOAD, PCK/ PC-YA•
"SPO. R/LOAD. LC, SPO. RC/Ii 1, l!MX/LC, ALU/B, YAK/LOAD, PCK/PC-YA"
"SPO, R /LOAD. LAB 1 SPO. RAB/Iii 1 , AMX I LA, KMX /@12, BMX/K MX, ALU/ ANDNOT, V AK I LOAD, PCK /PC-VA"

PC-PC+ 1
PC-PC+2
PC-PC+4
PC.PC+N
PC.O+PC
PC.VA

"PCK/PC+l"
"PCK/PC+2"
"PCK/PC+4"
"PCK/PC+N"
• ALU/ A+ B. v AK/ LOAD, PCK I pc_ v A, BMX/ PC. AMX/R AMX, RA MX/O.
"PCK/PC-VA"

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PC_VJBA
PSL<C>-AMXO

"PCK/PC-IBA"
"CCKIC-AMXO"

O&VA-ALU
O&VA-D
O&VA-D+LC
O&VA-LA
O&VA-O+LB.PC

"VAK/LOAD, SHF I ALU, OK /SHF"
"RAMX/D, AMX/RAMX, ALU/ A, VAK/LOAD, SHF I ALU, QK/SHF"
"RAMX/D, AMX/RAMX, BMX/LC, ALU/ A+B, VAK/LOAD, SHF I ALU, QK/SHF"
"AMX/LA, ALU/ A, V AK/LOAD, SHF I ALU, QK / SHF"
"RAMX/Q, AMX/ROX, BMX/PC. OR. LI', ALU/ A+B, VAK/LOAD, SHF I ALU, QK/SHF"

oo_( O+LB) D. R IGHT2
00_( O+LC) D. RIGHT2
OD-CO•LB l 0. RIGHT2
0D-CO-LClD.RIGHT2
ao_ao.RIGHT2

"ALU-O+LB ,a-ALU• RIGHT2, D-D. RIGHT2"
"ALU-O+LC ,Q_ALU. RIGHT2, D-D. RIGHT2"
"ALU-O•LB, 0-ALU. R IGHT2, D-D. R IGHT2"
"ALU.Q•LC, 0-ALU. RI GHT2, D-D. R IGHT2"
"ALU-0, 0-ALU • R IGHT2, D-D • R IGHT2"

o_o
o_O+LC+ 1
a_o+MASK+ 1
a_O+PC. RLOG
a_o-o
0-0•1\ []
a_O•LC
o_o-o
0-ACCEL&SYNC
0-ALU
0-ALUCFRAC)
O_ALU •LEFT
0-ALU.LE:FT2
O-ALU 0 LEFT3
0-ALU. RIGHT
O-ALU.RIGHT2
o_o
0-DCFRACl (Bl
0-D+I< l l
0-D+l<Cl+l
0_0+1< [ l • LEf.T
0-D+LC
0-D•K Cl
0-D•LC
o_o-o
o_o.oxnJ
O_D.OXT(J+K[] .LEFT
O_D.OXT(l .OR.PACK.FP
O_D.AND.K Cl
o_o.At4D.K (].RIGHT
O_D.AND.K Cl .RIGHT2
Q_D.At.D.RC[]
a_o. ANDNOT. RC ( l
a_o. LEFT 3
o_o. OR. K [ l

"ClK/CLR"
"ALU/ A+B+ 1, AMX/RAMX. OXT, OT/LONG, SHF I ALU, OK/SHF, BMX/LC"
"AMX/RAMX. OXT, DT /LONG, BMX/MASK, ALU/ A+B+ 1, SHF I ALU, OK/SHF"
"AMX/RAMX. OXT, DT /LONG, BMX/PC, ALU/ A+B. RLOG, SHF I ALU, QK/SHF"
"AMX/RAMX. OXT, DT /LONG, RBMX/D, BMX /RBMX, ALU I A•B, SHF I ALU, QK/SHF •
"AMX/ R AMX. OXT, DT /LONG, KMX/il 1 , llMX /KMX, ALU/ A•B, SHF I ALU, QK/ SHF •
• AMX/RAMX. OXT, DT /LONG, RMX/LC, ALU/ A•B, SHF I ALU, QK/SHF"
• AMX/ R AMX. OXT, DT I LONG, RBMX/Q, BMX /RBMX, ALU/ A•B, SHF I ALU, OK/ SHF •
"OK/ ACCEL, ACF /SYNC"
"SHF/ALU,OK/SHF"
"SHF I ALU ,OK/SHF •FL"
• SHF I LEFT, QK/ SHF •
"SHF I ALU. DT, OT/LONG, OK/SHF"
• OK/SHF ,SHF /LEFT3"
• SHF /RIGHT, OK/SHF"
"SHf /RIGHTi ,QK/SHF"
"OK/D"
"RBMX/D, BMX/RBMX, ALU/B, SHF I ALU, OK/SHF. FL"
"RAMX /D, AMX /RA MX, KM X /Ii 1 , l!MX /KMX, ALU/ A+B, SHF I ALU, ClK / SHF"
"RA MX ID, AMX /RA MX, K"'X /Ii 1, BMX/KMX, ALU/ A+B+ 1, SHF I ALU, OK/ SHF"
"RAMX/D, AMX/RAMX, KMX/il 1, BMX/Kl'X, ALU/ A+B, SHF /LEFT, QK/SHF"
"RAMX/D, AMX/RAMX, BMX/LC, ALU/ A+B, SHF I ALU, OK/SHF"
• RAMX/D, AMX/RAMX, KMX/li 1, BMX/Kl'X, ALU/ A•B, SHF I ALU, OK/SHF"
"RAMX ID, AMX/RA MX, BMX /LC, ALU/ A•A, SHF I ALU, QK/ SHF"
"RAM XI D, AMX /RAMX, R8'4 X /Q, BMX/RBMX, ALU/ A•B, SHF I ALU, OK/ SHF"
• RAMX/D, AMX/RAMX. OXT, DT /(a 1, ALU/ A, SHF I ALU, OK/Slff"
• RAMX /D, AMX /RAMX. oxi:, DT /il 1, IOo\X /(a 2, BMX/KMX, ALU/ A+B, SHF I LEFT, QK/ SHF.
• RAMX /D, AMX /RA MX. oxi:, OT /ii 1, BMX I PACKED. FL, ALU/OR, OK/ SHF"
"RAMX/D, AMX/RAMX, KMX /(a 1, BMX/KMX, ALU/ AND, SHF I ALU, OK/SHF"
"RAMX/D, AMX/RAMX, KMX/ Ii 1, BM X /KM X, ALU/ A ND, SHF /RIGHT, QK/SHF"
"RAMX/D, AMX/RAMX, KMX/il 1, BMX/KMX, ALU/ AND, SHF /RIGHT2, QK/SHF"
"RAMX/D, AMX/RAMX, SPO. R/LOAD. LC, SPO. RC/I! 1, BMX/LC, ALU/ AND, SHF I ALU, QK/SHF"
"RAMX/D, AMX/RAMX, SPO. R /LOAD.L°C, SPO. RC/I! 1, BMX/LC, ALU/ ANDNOT, SHF I ALU, QK/SHF"
"RAMX /D, AMX/RAMX, ALU I A, SHF /LEFT 3, QK I SHF"
"RAMX/D, AMX/RAMX, KMX/I! 1, BMX/KMX, ALU/OR ,SHF I ALU, QK/SHF"

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Q_D,Ok,RCCJ
u_D, PIGHT
a_D.RIGHT2
Q_D,SXT [ l
Q_D,XOR,Q
0-DEC, CON
a_IB, BDFS1
a_IB.DATA
Q_JDCSC)
a_IDCl
Q_K []
Q_K [ l +I
O_K Cl ,CTX
O_K[l,RIGHT
a_K [J ,RIGHT2
O_LA
a_LAH Cl
0-LA+O
0-LA-K [ l
o_LA,AND,K Cl
0-LA, AND~UT, RC Cl
o_LB
0-LC
O_NOT,Q
O_NOT,P CJ
O_PACK, FP
o_Pc
o_OCFRACJ
o_OCFRAC) CB)
o_o+o
o_o+K c1
o_O+K[J+l
o_o+LC
a_a+PC
o_o-o
0_0-0-1
o_o-K c1
a_o-K 1 l - t
0-0-LC
0-0-LC-1
a_O-MASK-1
o_O,OXT!J-KCl
o_O,OXTCJ ,LEFT
o_a,OXT[l ,OR,D
Q_O,AND,K []
O_Q,AND,K CJ ,RIGHT2
0_0,AND,K CJ ,RIGHT
0-0,AND,R []
Q_O.A~D.RC Cl
0_0,ANDNOT,D
a_O,ANDNOT,K [ l

"RAMX/D, AMX/PAMX, SPO, R/LDAD, LC, SPO, RC/!H, BlllX/LC, ALU/DR, SHF I ALU, OK I SHF"
"RAMX/D, AMX/RAMX, ALU I A, SHF /RIGHT, OK/ SHF"
"RAfolX/D, AMX/RAMX, ALU/ A, SHF /R l(,HT2, OK/ SHF"
"RAMX/D, AMX/RAMX, SXT, OT /ti I, ALU/ A, SHF I ALU, OK/SHF"
"QK/SHf, ALU/XOR, AMX/RAMX, RAMX /D, BMX/RBMX, RBMX/Q, SHF I ALU"
"OK/DEC ,CON"
"I BC/BDEST, OK I IO, MCT I ALLOw, IB, Rf AD"
"OK/ID, MCT/ ALLOW, IB, READ"
"CID/READ, SC, OK I ID"
"CID/READ,K"IX,JD,ADOR/!Oil ,OK/ID"
"IOIX/li 1, BMX /Kl"X, ALU/B, SHF I ALU, OK /SHF"
"Alo!X/RA"X, OXT, OT /LONG, KM X/ll 1, BMX /K MX, A LU/ A+B+ 1, SHF I ALU, QK/SHF"
"KMX/ll 1, BMX/KMX, ALU/B, SHF I ALU, OT, DT I INST, DEP, OK/ SHF"
"KMX /ti 1, BMX/K MX, ALU/B, SHF /RIGHT, OK I SHF"
"100/tl 1, BMX /K"'X, ALU/B, SHF /R IGHT2, OK I SHF"
"AMX/LA, ALU/ A, SHF I ALU, QK/ SHF"
"AMX/LA, KMX/tl 1, BMX/KMX, ALU/ A+H, SHF I ALU, OK/SHF""
"AMX/LA, RB"'X/0, Bfo\X/RBMX, ALU/ A+B, SHF I ALU, OK/ SHF"
"AMX/LA, KMX/111, B'°'X/K MX, ALU/ A-B, SHF I ALU, OK/SHF"
"AfolX/LA, KMX/I! 1, BMX /KMX, ALU/ AND, SHF I ALU, QK/ SHF"
"AMX/LA, SPO, R /LOAD, LC, SPO, RC/IOI I, BMX/LC, ALU/ ANDNOT, SHF I ALU, OK/SHF"
"l\MX/LB, ALU/B, SHF I ALU, OK /SHF"
"BMX/LC, ALU/B, SHF I ALU, QK/SHF"
"RAMX/0, AMX/RAMX, ALU /NOTA, SHf' /ALU, OK/SHF"
"LA-RA [till ,AMX/LA,ALU/NOTA ,0-ALU"
"BMX/PACKED, FL, ALU/!\, SHF I ALU, OK /SHF"
"llMX/PC, ALU/B, SHF I ALU, QK /SHf"
"RAIH/O, AMX /RAMX, ALU/ A, SHF I ALU, QK/SHF, FL"
"RllMX/O, BMX/RBMX, ALU/!\, SHF" I ALU, OK /SHF, FL"
"RAMX/O, AMX/RAfolX, RBfolX/D, Sp.IX /RBMX, ALU/ A+B, SHF I ALU, OK/ SHF"
"RAMX/Q, AMX/RAMX, KMX/li 1, Bp.!X/KJo!X, ALU/ A+B, SHF I ALU ,OK/SHF"
"RAMX/O, AMX/RAMX, K MX /Ii' 1, Bl<X/K"1X, ALU/ A+B+ 1, SHF I ALU, OK/SHF"
"l<Afo!X /Q, AMX/RAMX, BMX/LC, ALU/ A+B, SHF I ALU, OK/SHF"
• RAMX/O, AMX /l<AMX, BMX/PC, ALU/ A+B, SHF I ALU, OK/SHF"
"RAMX/O 1 A"lX/RAMX, RBMX /D, BMX/RP"X, ALU/ A-B, SHF I ALU, OK/ SHF"
"RAJo!X/O, AMX/RAMX, RBMX/D, BMX/RB"1X, ALU/ A-B-1, SHF I ALU, QK/SHF"
"RAMX/0, AMX/RAMX, KMX/li 1, B"X/KMX, ALU/ A-B, SHF I ALU, OK/SHF"
"RAMX/O, AMX/RAMX, l<MX/il 1, EIMX/KMX, ALU/ A-B-1,SHF /ALU ,OK/SHF"
"RAMX/Q, AMX/RAMX, BMX/LC, ALU/ A-B, SHF I ALU, OK/SHF"
"RAMX/O, AMX/RAMX, BMX /LC, ALU I A-8-1, SHF I ALU, QK/SHF"
"RAMX/Q, AMX/llAMX, BMX/~ASK, ALU/ A-B-1, SHF I ALU, OK /SHF"
"RAMX/Q, AMX/R AMX, OXT, DT/I! 1, K MX/!12, BMX/KMX, ALU/ A-B, SHf I ALU, OK/SHF"
"RAMX /Q, AMX/RAMX, OXT, DT /ii 1, ALU/ A, SHF /LEFT, OK/SHF"
"RAMX/O, AMX/RAMX, OXT, DT /!I 1, RBMX/D, BMX/RBMX, ALU/Oi<, SHF I ALU, OK/SHF"
"RAMX/O, AMX /RAMX, KMX/lil, BMX/KMX, ALU/ AND, SHF I ALU ,Oii/ SHF"
"RAMX/0, AMX/RAMX, KMX/!I I, P.MX/IOIX, ALU/ AND, SHF /R IGHT2, OK/SHF"
"RAJo!X/O, AMX/RAMX, Kfo\X/!11, BMX/KMX, ALU/ AND, SHF /RIGHT, OK/ SHF"
"RA,.X/O, AMX/RAMX, SPD, R /LOAD, LAB, SPO, RAB/!11, B"IX/Lll, ALU/ AND 1 SHF I ALU, OK/SHF"
"kAMX/Q, AMX /RAMX, SPO, R /LOAD, LC, SPO, RC/Ii 1, BMX /LC, ALU/ AND, SHf I ALU, OK I SHF"
"RA"IX /Q, AM X/RAMX, RBMX/D, BMX /RBMX, ALU I AND NOT, SHF I ALU 1 OK /SHF"
"RAMX /0, A MX/RAMX, KM XI !11, Bl'X/~ MX, ALU I ANON OT, SHF I ALLJ, OK/SHf"

en
-<
en
-t
m
3:
3:
("')

J:J

("')

J:J

n0
2

o_o. ANON OT. RC c J
o_O.LEFT
o_o.LEfT2
o_o.OR.KCJ
o_o. ORN OT. MASK
o_O.RIGHT
o_O.RIGHT2
0-0.SXTCl
o_o.xoR.K CJ
0-RCPRl'<l .ANDNOT.O
0-RCPRN+l)
0-RCPRN+l).Ar.o.o
0-RCSC)
0-R CSRC ! 1) .AND.K Cl
Gl-RCCSC)
0-RC CJ
0-RCCl CFRACJ
0-RCJ
0-R Cl CFRAC)
0-R CJ .AND.II CJ
0-RCl .AND.K [J .RIGHT
0-RCJ 0 ANDNOT 0 K[l
0-R [ J • OR.KC J
0-SHF

"RA"X/Q, AMX/RAMX, SPO. R /LOAD. LC, SPO. RC/lil 1, BMX/LC, ALU/ ANDNOT 1 SHF I ALU, QK I SHF"
"OK/LEFT"
"OK/LEFT2"
"RAMX/Q, AMX/RAl'X, KMX /Iii 1, Hl'X/K MX, ALU/OR, SHf I Al,U, 01\/SHF"
"RAMX/O, AMX/RAMX, BMX /MASK, ALU/ORNOT, SHF I ALU, OK /SHf"
"OK/RIGHT"
"OK/RIGHT2"
"RAMX/O, AMX/RAMX. SXT, OT /ii 1, ALU/ A, SHF I ALU, OK/SHF"
"RAMX /0, AMX/RAMX, KMX/fi I, BMX/KMX, ALU /XOR, SHF I ALU, Ql(/Slff"
"SPO. AC/LOAD• LAB, SPO. ACN /PR~, A~ X /LA, R llM X/O, BMX IR fl ·~X, ALU I ANO NOT, SHf I ALU, OK I SHF"
"SPO. AC/LOAD. LAB, SPO. ACN/PRN+ I , AMX/LA, ALU/ A, SHF I ALU, GIK/SHF"
"SPO. AC/LOAD. LAB, SPO. ACN I PRN + 1, AM XI LA, RBMX /0, BMX/ RllMX, ALU/ AND, SHF I ALU 1 OK/ SHF"
"ALU/ A, SHF I ALU, AMX/LA, SPO. AC/LOAD. LAB, SPO. ACN/SC, VK/ SHF"
"SPO .AC/LOAD, LAl'>,SPO. ACNl I /SRC .OR. I ,AMX/LA, KMX/fil ,BMX/KMX, ALU/AND, SHF/ALU ,OK/SHF"
"ALU/B, SHF I ALU, BMX/LC, SPO/LOAD. LC. SC, OK/SHF"
"SPO • R/LUAD. LC, SPO. RC/Ii 1, BMX/LC, ALU/B, SHF I ALU, QK/SHF"
"SPO. R/LOAD. LC, SPO. RC/Ii 1, BMX/LC, ALU/B, SHF I ALU, OK/ SHF. FL"
"SPO. R/LOAD. LAB, SPO. RAB/Ii 1, AMX/LA, ALU/ A, SHF I ALU, Ql\/SHF"
"SPO. R/LUAD. LAB, SPO. RAB/(111, AMX/LA, ALU/ A, SHF I ALU, VK/SHF. FL"
"SPO. R/LOAO •LAB, SPO. RAB/ti 1, AMX/LA, K MX/(il2, BMX/KMX, ALU/ AND, SHF I ALU, OK/SHF"
"SPO. R /LOAD• LAB, SPO. RAB/ fill , A MX /LA, ALU I AND, BMX /K MX, KMX/P2, SHf' /RIGHT, OK I SHF"
"SPU. R/LOAD. LAB, SPO. RAB /fill, AMX/LA, K MX/ (il 2, BM X/KMX, ALU/ AND NOT, SHF I ALU, OK/ SHF"
"ALU/OR, AMX /LA, SPO. R /LOAD. LAB, SPO. RAB/ ti 1, BMX/KMX, K MX/fll2, OK I SHF"
"ALU/B, BMX/KMX, KMX/SC, SHF I ALU, QK/ SHF"
"01\/SHF"

RCDSTJ-ALU
R(DST)-D
RCDST)-D.SXTCJ .RIGHT

"SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN 11 /DST. DST"
"RAMX/0, AMX/RAMX, ALU/ A, SHf I ALU, SPO. AC/ •RI TE. RAR, SPO. ACN 11 /0ST. OST"
"RAMX/D, AMX/RAMX. SXT, OT /(il, ALU/ A, SHF /RIGHT, SPO. AC /WRITE. RAB, SPO. ACN 11 /DST• DST"

RCPRN)-0+0,RLOG
R(PRN)-ALU
RCPRNJ-D
RCPRNl-D+K Cl .RLOG
R ( PRN l-D·K [ J. RLOG
RCPRNJ-D.OR.O
RCPRNl-DClO
R(PRNl-K CJ
R(PRNJ-LA+K CJ 0 RLOG
R(PRN)-LA+O
RCPRN)-LA•KCl .RLOG
RCPRNl-LA[]MASK
RCPRNl-LC
R(PRN)-PACK.FP
RCPRN)-0
RCPRNl-O+KCl ,RLOG
RCPRNl-O•K Cl .RLOG
R ( PRN+ 1 l-ALU
RCPRN+ll-D
R(PRN+l l-D.OR.O

"ALU/ A+B. RLOG, BMX/RBMX, RBMX/D, AMX/RAMX. OXT, OT /LONG, RC PRN >-ALU"
"SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/PRN"
"RAMX /D, AMX/RAMX, ALU/ A, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/PRN"
"RAMX/D, AMX/RAMX, KMX/il 1, BMX/KMX, ALU/ A+B. RLOG, OT/LONG, RC PRN l-ALU"
"RAMX/D, AMX/RAMX, K MX /U, BM X /KM X, ALU/ A•B. RLOG, DT /LONG, RC PRN l-ALU"
"RAMX/D, AMX/l<AMX, Rfl14X/Q, BMX/RllMX, ALU/OR, R ( PRN l-ALU"
"RAMX/D 1 AMX/RAMX, RBMX/O, BMX/RBMX, ALU/ti 1, R ( PRN l-ALU"
"KMX/!i 1, BMX/l<MX, ALU/B, SHF I ALU, SPO. AC/WRITE, RAB, SPO • ACN/PRN"
"AMX/LA 1 KMX/flll, BMX/KMX, ALU/ A+B. RLOG, OT/LONG, R ( PRN l-ALU"
"AMX/ LA, RBMX/0, BMX /RBMX, ALU/ A+EI, SHF I ALU, SPO. AC/ WR l TE. RAB, SPO •A CN /PR N"
"AMX/L'A, KMX/flll, BMX/KMX, ALU/ A•B. RLOG, OT/LONG, R ( PRN l-ALU"
"AMX/LA, BMX/MASK, ALU/ti 1, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/PRN"
"BMX/LC, ALU/B, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/PRN"
"BMX/ PACKED. FL, ALU /B, SHF I ALU, SPO •AC/WR I TE.RAB, SPO. ACN/PRN"
"RAMX/O, AMX/RAMX, ALU/ A, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/PRN"
"RAMX/O, AMX/RAMX, KMX/ll 1, BMX/KMX, ALU/ A+B. RLOG, OT /LONG, RC PRN >-ALU"
"RAMX/Q, AMX/RAMX, KMX/IH, BMX/KMX 1 ALU/ A•B. RLOG, OT/LONG 1 R ( PRN l-ALU"
"SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/PRN+l"
"RAMX/D, AMX/RAMX, ALU/ A, SHF I ALU, SPO. AC/WRITE• RAB, SPO • ACN/PRN+ 1"
"RAMX/D, AMX/RAMX, RBMX/O, BMX/RBMX, ALU/OR, SHF I ALU, SPO. AC/WRITE• RAB, SPO • ACN/PRN+ 1"

o_sc

Cl)

-t
m

3:
~

n
0

0
Cl)

n
0
2

en
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en
-4
m

RCPRN+l>-KCJ
RCPRN+1l-LA
RCPRN+1 l-LC
RCPRN+ll-0

"l<MX/U, BMX/l<MX, ALU/B, SHF I ALU, SPO. AC/WRIT!!:. RAB, SPO • ACN/PRN+ 1"
"AMX/LA, ALU/ A, SHF I ALU, SPO. AC /~RITE. kAR, SPO • ACN/PHN+l"
"BMX/LC, ALU/B, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/PkN+l"
• RAMX/O, AMX /RAMX, ALU/ A, SHF /ALU, SPO. AC /WRITE• RAB, SPO • ACN/PRN+ 1"

RCSCl-ALU
RCSCl-D
RCSCl-K CJ
RCSCl-LA
RCSCl-LA+D
RCSCl-LA•D
RCSCl-LC
RCSCl-0

"SHF I ALU, SPO •AC/WRITE. RAB, SPO • ACN/SC"
• RAMX/D, AMX/RAMX, ALU/ A, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/SC"
• KMX/li'i, BMX I KM X, ALU/B, SHF I ALU, SPO •AC/WRITE. RAB, SPO. ACN/ SC"
• AMX/LA, ALU/ A ,SHF I ALU, SPO. AC/WRITE• RAB, SPO • ACN/SC"
• AMX/LA, RBMX/O, BMX /RBMX, ALU I A+B, SHF I ALU, SPO. AC/WR l TE. RAB, SPO. ACN I sc•
• AMX/LA, RBMX/O, BPllX /RBMX, ALU/ A•B, SHF I ALU, SPO. AC/WR lTE •RAB, SPO. ACN/SC•
"ALU.LC, RC SC >-ALU"
"RAMX/O, AMX/RAMX, ALU/ A, SHF I ALU, SPO .AC/WRITE. RAB ,~PO. ACN/SC"

R(SPl l-ALU
RCSPl l-D
RCSP1 l-K CJ
R(SPll-PACK.FP
RCSPll-0
R(SP1+1 l-LC
R(SPl+ll-0

"SHF I ALU, SPO •AC/WR tTE. RAB, SPO. ACN/SPl .SP 1"
"RAMX/D, AMX/RAMX, ALU/ A, SHF I ALU, SPO •AC/WRITE. RAB, SPO. ACN/SPl • SPl"
"KMX/111, BMX/KMX, ALU/B, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/SPl. SP1 •
• BMX/PACl<EO. FL, ALU/B, SHF /ALU, SPO. AC/WRITE. RAB, SPO. ACN/SPl. SP 1"
"RAMX/O, AMX/RAMX, ALU/ A, SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN/SP1 0 SPl •
• BMX/LC, ALU/B, SHF I ALU, SPO .AC/WRITE. RAB, SPO. ACN/SP 1 +1"
"RAMX/O, AMX/RAMX, Al,U/ A, SHF' I ALU, SPO. AC/WRITE• RAB, SPO. ACN/SPl +1"

R(SRC!ll-ALU
RCSRC!ll-DCBJ
R(SRCl-ALU
RCSRCl-D
RCSRCl-DCBJ
R(SRCl-D+KCl .RLOG
R(SRCJ-O•K Cl .RLOG
R(SRCl-LC
RCSRCl-0

"SHF' I ALU, SPO •AC/WRITE• RAB, SPO. ACN 11 /SRC. OR .1"
"RBMX/0, BMX/RBMX, ALU/R, SHf I ALu, SPO. AC/WRITE. RAB, SPO. ACN 11 / SRC .OR .1 •
"SHF /ALU ,SPO .AC/WRITE .RAB, SPO .ACN 11 /St<C. SRC"
"RAMX/D, AMX/RAMX, ALU/ A 1 SHF I ALU, SPO. AC/WRITE. RAB, SPO. ACN 11 /SRC • SRC"
• RBMX/D, BMX/RBMX, ALU/B, SHF /ALU, SPO. AC/WRITE. RAB, SPO. ACN 11 /SRC • SRC"
• RAMX/D, AMX/RAl'4X, KMX/1!11, BMX/KMX, ALU/ A+B. RLOG, OT /WORD ,RC SRC )_ALU•
"RAMX/O, AMX/RAMX, KMX/@11, BMX /KMX, ALU/ A•B. RLOG, OT /WORD, R ( SRC l-ALU"
"BMX/LC, ALU/B, RC SRCl-ALU"
"RAMX/Q, AMX/RAMX, ALU/ A, SHF I ALU, SPO. AC/lllRITE. RAB ,SPO. ACN 11 /SRC .sRC"

R6-D+K [ l • RLOG
R6-LA+K CJ .RLOG
R6-LA•I< [] .RLOG

"SPO. R/WRl TE. RAB, SPO. RAB/Ro, RAMX /D, AMX/RAMX, KMX/1!11 1 BMX/KMX, ALU/ A+B. RLOG, SHF I ALU"
• AMX/LA, BMX/KMX, K"X/1!11, ALU/ A+B. RLOG, OT/WORD 1 SHF I ALU, SPO. R/WRITE. RAB, SPO. R•BIR6 •
"AMX/ LA, BMX /KM X, KMX /lill, ALU/ A•B. R LOG, OT /WORD, SHf I ALU, SPO. R/ WRITE. RAB, SPO. R AB/R6"

RCCSCl-O•LC
RCCSCl-ALU
RCCSCl-ALU.RIGHT
RCCSCl-D
RCCSCl-0

• ALU-O•LC, RC (SC )_ALU"
"SHF I ALU, SPO/WRITE. RC. SC•
"SPO/WR ITE. RC. SC, SHF /RIGHT"
• ALU-D, RC (SC l-ALU"
"ALU.Q, RC CSC >-ALU"

RCC1'VA-D+O
RCCl-0
RC[J_O+KCJ+l
RC Cl-O+LC+l
RC[J_O+MASK+l
RCCl-O+MASK+l .lllGHT2
RC[J_O-D
RC CI .ALU

"RAMX/O, AMX/RAMX, RBMX/Q, BMX/RB"X, ALU/ AH\, VAK/LOAO, SHF I ALU, SPO. R/WR ITE. RC, SPO. RC/II I"
• AOIX/l'IAMX. OXT, OT /LONG, ALU/ A, SHF I ALU, SPO. R/lllR ITE. HC, SPO. RC/@11"
"AMX/RAMX. OXT, OT/LONG, KMX/@12, B"X/KMX, ALU/ A+B+ 1, SHf I ALU, SPO •RI WRITE• RC, SPO. RC/f 1"
"AMX/RAMX. OXT, OT /LONG, BNX/LC, ALU/ A+B+1, SHF I ALU, SPO. R/WRITE •RC, SPO. RC/111"
"AMX/RAMX. OXT 1 OT /LONG, BMX/MASK, ALU/ A+B+l, SHF I ALU, SPO. R/WRITE. RC, SPO. RC/111"
"Al4X /RAMX. OXT, OT /LONG, BMX/MASK, ALU I A+I'+ 1 , SHF /R IGti'f 2, SPO. R/WR ITE. RC, SPO. PC/@11"
• AMX/RAMX. OXT, OT /LONG, RBMX/D, BMX/RBMX, ALU/ A•l:I, SHf I ALU, SPO. R/OIR ITE. RC, SPO. RC/•1"
"SHF I ALU, SPO. R/WRITE. RC, SPO. RC/li 1"

::
~

n
:c
0
n
0

::
)>

n0
z

RC Cl -ALU. LEFT
RC Cl -ALU. LEFT2
RCCl-ALU.LEFTl
RC Cl-ALU.RIGHT
RC Cl -ALU. R IGHT2
RCCl-D
RCCl-DCBJ
RCCl-D+K Cl
RCCl-D•KCl
RCCl-D.OXTCl
RCCl-D.AND.I< Cl
RCCl-D.AND.MASK
RCCl-D.ANDNOT.Q
RCCl-D.CTX
RC C1-D. LEFT
RCC1-0.LEFT3
RCCl-0.0R.KCl
RCCl-0.0R.Q
RCCl-D.ORNOT.l<C)
RCCl-0.SXTll
RCCl-K CJ
RCCl-K Cl+l
PCCl-1< [) .LEFT2
RCCl-1< Cl .LEFTl
RCCl-1<[J.RIGHT2
RC Cl-LA
RCCJ-LA+LB.CTX
RCCl-LA•I< Cl
RC[l-LA.ANO.KCJ
RCCl-LA.CTX
RC Cl-LB
RCCl-LB.LHT
RC Cl-LC
RCCl-NOT 0 Q
RCCl-PACK.FP
HCll-PC
RCCJ_O
RCCl-0+1
RCCl-O+K Cl
RC Cl-O+LC
RC Cl -O+PC
RCCl-O+PC+l
RCll-O•KCl
RC CJ _O•LC
RCCl-O·MASK•l
RCCl-0.0XTll
RCCl-0.ANO.KCl
RCCl-0.ANONOT.KCJ
RCCl-0.LEFT
RCll-0.LEFTl

"SHF /LEFT, SPO. R/WRITE. RC, SPO. RC/II 1"
"SPO. R/WRITE. RC, SPO. RC/U, SHF I ALU. OT, OT/LONG"
"SPO • R/WRITE •RC ,SPO • RC/fil 1, SHf /LEFTJ"
"SHF /RIGHT, SPO. R/WRITE. RC, SPO • RC/llll"
"SHF /RlGHT2, SPO. R/wRITE. RC, SPO. RC/II 1"
"RAMX/O, AMX/RAMX, ALU/ A, SHF I ALU, SPO. R/WRITE. RC, SPO. RC/@11"
"RBMX/O, BMX/RBMX, ALU/B, SHF I ALU, SPD. R/WRITE. RC, SPO. RC/'1"
"RAMX/O, AMX /RAMX, BMX /~I' X, KI' X/ ~2, ALU/ A+B, SHF I ALU, SPO. R/WRITE. RC, SPO • RC/t 1"
"RAMX/O, AMX/R A14X, BMX /KMX, Kl'X I 112, ALU/ A•B, SHF I ALIJ, SPO. R/ WRITE• RC, SPO •RC/ii 1"
"RAMX/O, AMX/RAMX • OXT, OT /fil2, ALU/ A ,SHF I ALU, SPO • R/WRl TE .RC, SPO. RC/'1"
"RAMX/O, AMX/RAMX, BMX/K MX, KMX /112, ALU I ANO, SHF I ALU, SPO. R/WR ITE •RC, SPO • RC/1111"
"RAMX/O, AMX/RAMX, BMX/MASI<, ALU/ ANO ,SHF I ALU ,SPO. R/WHITE. RC, SPD. RC/fill"
"RAMX/O, AMX/RAMX, RBMX/O, BMX/RBMX, ALU/ ANONOT, SHF I ALU, SPO. R/WRITE •RC, SPO • RC/@I 1"
"R AMX/O, AM X/RAMX, ALU/ A, SHF I ALU. OT, OT I INST. OEP, SPO. R/WRITE •RC, SPO. RC/411"
"RAMX/O, AMX/RAMX, ALU/ A, SHF /LEFT, SPO. R/WRITE 0 llC, SPO •RC/ii 1"
"RAMX /0, AMX/RAMX, ALU/ A, SHF /LEfT3, SPO • R /WRITE. RC, SPO •RC/ii 1"
"RAMX/O, AMX/RAMX, KM X/ 112, BMX/K MX, ALU/OR, SHF I ALU, SPO. R/wR I TE• RC, SPD •RC/fill"
"RAMX/O, AMX/RAMX, RBMX/O, BMX/RBMX, ALU/OR, SHF I ALU, SPO • R/WRITE •RC, SPO .RC/@11"
"SPO. RC/fill, SPO. R/WR !TE. RC, ALU /OR NOT, AMX/RA MX, RAMX/ 0, BMX/KMX, KMX/il2, SHF I ALU"
"RAMX/O, AMX/RAMX • SXT, OT/il2, ALU/ A, SHF I ALU, SPO • R/WRlTE. RC ,SPO. RC/@I 1"
"KMX/ll2, BMX/Kf14X, ALU/B, SHF I ALU, SPO .R/WRITE. RC, SPO. RC/tll"
"AMX/RAMX • OXT, OT /LONG, KMX/ll2, BMX/KMX, ALU/ A+B+ 1, SHF I ALU ,SPO. R/WRITE. RC ,SPO. RC/lit"
"KMX/ll2, BMX/KMX, ALU/fl, SHF I ALU .OT, OT/LONG, SPO. R/WRITE .RC ,SPO • RC/'1"
"KMX/ll2, 8MX/K14X, ALU/B, SHF /LEFT3, SPO. R/WRITE. RC, SPO. RC/U"
"l<MX/ll2, BMX/KMX, ALU/B, SHF /RIGHT2, SPO. R/WRITE. RC, SPO • RC/U"
"AMX/LA, ALU/ A, SHF I ALU, SPD. R/ilRITli:. RC, SPO. RC/1111"
"AMX/LA, BMX/LB, ALU/ A+B ,SHF /ALU. OT, OT /INST• DEP, SPO. R/ilRITE •RC, SPO .RC/'1"
"AMX/LA, l<MX/ll2, BMX/KMX, ALU/ A•B, SHF/ ALU ,SPO. R/WRin;. RC, SPO. RC/lit"
"ALU-LA.ANO.l<C112l ,RCCl!lll-ALU"
"AMX/LA, ALU/ A, SHF I ALU. OT, OT/INST .OEP, SPO. R/WRITE. KC ,SPO • RC/t 1"
"BMX/LB, ALU/8, SHF I ALU, SPO. R/WR ITE. RC, SPO. RC/111"
"BMX/LB, ALU/B, SHF /LF:FT, SPO • R/WRITE •RC, SPO. RC/lll"
"BMX/LC, ALU/B, SHF I ALU, SPO. R/WRITE. RC ,SPO. RC/lit"
"RAMX/O, AMX/RAMX, ALU/NOTA, RC CtH l-ALU"
"BMX/PACl<EO.FL, ALU/B, SHf I ALU, SPO. R/WRITE. RC, SPO. RC/lit"
"l!l'IX/PC, ALU/B, SHF I ALU, SPO. R/wRITE. HC, SPO. RC/lll"
"RAMX/O, AMX/RAMX, ALU/ A, SHF I ALU, SPO. R/WRITE. RC, SPO. RC/U"
"ALU-0+0+1,RCClltl-ALU"
"RAMX/O, AMX/RAMX, BMX/ KMX, K l'X/112, ALU/A+l:l, SHF I ALU, SPO. R/i-RITE. RC, SPO. RC/@11"
"ALU/ A+B, RAMX/Q, AMX/RA"X, Bl'X/LC, SPO. R/WR ITE. RC, SPO •RC/ii 1"
"RA"'X /Q, AMX/RAMX, BMX/PC, ALU/ A+B, SHF I ALU, SPO. R/WRl TE• RC, SPO • RC/t 1"
"RA/olX/0, AMX/RAMX, BMX/PC, ALU/ A+B+ 1, SHF I ALU, SPO. R/WRITE. RC ,SPO. RC/U"
"RAMX/O, AMX/RAMX, BMX/K MX, I< MX / i 2, ALU/ A•B, SHF I ALU, SPO • R/ WRITE• RC, SPO • RC/i 1"
"ALU/ A•B, RAMX/O, AMX/ROX, BMX/LC, SPO. R/WRITE. RC, SPO. RC/lll"
"RA MX/O, AMX/RAMX, BMX/ MASK, ALU/ A•B• 1, SHF I ALU, SPO. R/WR ITE. RC, SPO. RC/1!11"
"RAMX/O, AMX/RAMX • OXT, OT /1!12, ALU/A, SHF /ALU, SPO • R/WRITE .RC, SPO • RC/111"
"RAMX/Q, AMX/RAMX, BMX/KMX, KMX/1!12, ALU/ ANO, SHf I ALU, SPO • R/llRITE. RC, SPO. RC/lit"
"RAM X/0, A MX/RAMX, Biol XI KMX, KlolX/112, ALU I ANDNOT, SHF I ALU, SPO. R/IOR ITE •RC, SPO •RC/ill"
"RA MX /0, AMX /fl AMX, ALU I A, SHf /LEFT, SPO. R/i-R ITE. RC, SPO. RC/lll"
"l<AMX/Q, AMX/RAMX, ALU/ A, SHf /LEl'T3, SPD. R/WRITE. RC, SPO • RC/1!11"

en
-<
en
-I

:J:J

0
c
m

:J:J

n0
z

::!

RC[]_Q,RIGHT
RCCJ_Q,RIGh12
RC[J_Q,SXT[]
HCCl-kLOG,IHGHT

"RAMX/Q, AMX/RAMX, ALU/ A, SHF' /RIGHT, SPO, R/WRITE, RC, SPO, RC/li 1"
"ALu_a. SHF' /RIGHT2. SPO. R/WRI'IE: .RC. SPO. RC/lit.
"RAMX/Q, AMX/RAMX. SXT, IJT /li2, ALU/ J., SH~'/ ALU, SPO. R/WRI TE.. RC, SPO. RC/!11"
"l!MX/0, MSC/READ, RLOG, ALU/B, SHF' /RIGHT, SPO, R/WRITE, kC, SPO, RC/111"

R[]&VA-LA+K[J
R [ l &VA-LA-KC 1
R(J&VA-LA-K(J ,HLOG
HC]&VA-0-K[J
RC J _O
R []_O+Ll'\+1
R [ 1-0-1
R (J_O-D
R [J_O-K ll
R Cl-0-Lfl
RCJ_o-o
R Cl-ALU
R Cl-ALU,LEF"T
R(]_ALU.LEF'T3
RCl-ALU,RIGHT
R(]_ALU.RIGHT2
R Cl-D
RCl-D+K[J
RCl-D+O
Rll-D+O+l
Rll-D-K[]
R Cl-D-LC-1
R c1 _o-o
R (J_D,AND,K Cl
RCJ_D,01<,LC
R [J_D,01<,PACK,F'P
R [J_D,OR.Q

"AMX/LA, KMX/!12, BMX/K MX, ALU/ A+b, VAK/LOArJ, SHF' I ALU, SPO, R/WRITE, RAB, SPO, RAB/ti 1"
"AMX/LA, KMX/n, BMX/KMX, ALU/ A-B, VAK/LOAD, SHF' I ALU, SPO, R/WRITE, RAB, SPO, IUB/111"
"AMX/LA, KMX/!12, BMX /KMX, ALU/ A-B. RLOG, DT /LONG, VAK/ t.UAD, SHF' I ALU, SPO. R/\llRITE, RAB, SPO, IUB/'1"
"RAMX/Q, AMX/RAMX, KMX /i'2, BMX/K "X, ALU/ A-B, VAK/LOAD, SPO, R/WRITE, RAB, SPO, RAB/t t •
"SPO, fl /WRITE, RAB, SPO, RAB/ii 1, AMX/RAMX, OXT, OT/LONG, ALU/ A, SHF' I ALU"
• AMX/RAMX. OXT, DT /LONG, BMX/LB, ALU/ A+B+ 1, SHF' I ALU, SPO, R/wRITE, RAB, SPO, RAB/111"
"AMX/RAMX, OXT, DT/LONG, BMX/KMX, K"X/ .1, ALU/ A-B ,SHF' I ALU ,SPO,R/WRITE ,RAB, SPO, RAB/•1"
• AMX/RA~X, OXT, DT /LONG, RB~X ID, B"X /RBMX, ALU/ A-B, SHF' I ALU, SPO, P/\llR ITE, RAB, SPO, RABI• t •
• AMX/ RAMX, OXT, DT /LONG, KMX /@2, B"X /KMX, ALU I A-B, SHF' I ALU, SPO, R/\llRITE, RAB, SPO, RABI• t •
"AMX/RAMX, OX!, DT /LONG, BMX/LA, ALU/ A-B, SHf I ALU, SPO, H/WRl TE, RAB 1 SPO, PA!l/111"
• A"XIRAMX, OXT, DT /LONG, RBMX/Q, BMX /RBMX, ALU/ A-B, Stil' I ALU, SPO, R/\llR ITE. RAB, SPO, RAB/111"
"SHF I ALU ,SPO, R/WRITI':, RAB ,SPO. RA!\/lil"
"SPO, R /WR! TE, RAB, SPO, RAB/@ 1, SHF /LEF'T"
"SPO, R /oRI TE, RAB, SPO, R AB/fal, SHF' /LEF'T 3"
"SHF' /fl JGHT, SPO, R/WR I TIC, RA A, SPO, RAB/@ 1"
"SPO, R /WRITE, !<AB, SPO, HA B/I01, SHF' /RIGHT2"
"SPO, R/oRITE, RAB, SPO, RAB/Ii 1, HA,..X ID, A"X/R AMX, ALU/ A, SHF' I ALU"
• SPO, R/WRITE, RAB, SPO, PAB/li 1, RA MX/D, AMX/RAMX, KMX/(12, BMX/KMX, ALU/ A+B, SHF' I ALU•
• SPO, R /WRITE, RAB, SPO, RAR/li't, RAMX/D, AMX/RAMX, RBMX/Q, BMX/RBMX, ALU/ A+B 1 SHF' I ALU"
"SPO, R /WRITE, RAB, SPO, RAB/lH, RA,..X/D, AMX/RAMX, RBMX/U, BMX/RBMX, ALU/ A+B+ I, SHF' I ALU"
"SPU, ~ /oRI TE, RAB, SPO, R AB/!11, RA"X/D, AMX/RAMX, KMX/ti2, BMX/l\MX, ALU I A-B, SHF' I ALU"
"ALU-IJ-LC-1,R(il1 l-ALU"
• SPO, R /wRI TE, RAB, SPO. RAB/Ii 1, RA MX/D, AMX/RAMX, RBMX/Q, BMX/RBMX, ALU/ A-B, SHF' I ALU"
"SPO, R /WRITE, RAB, SPO, RAB/Ii 1, ALU/ A~D, AMX/RAMX, RAMX/D, BMX/KMX, KMX/!12, SHF I ALU"
"SPO, R /w PI TE, RAB, SPO, RAB/ta 1, ALU /OR, AMX/RAMX, RAMX/D, BMX/LC, SHF' I ALU"
"SPO, R /WR I TE, RAil, SPO, RAB/ta 1, ALU /OR, AMX/RAMX, RAM X/D, BMX/PACKED, F'L, SHf I ALU"
• SPO, !</WR I Tt:. RAB, SPO, RAB/I;! 1, ~A" XID, A"XIRAMX, RAMX/Q, BMX/RBMX, ALU/OR, SHF' I ALU"
• BMX /KMX, KMX/@2, ALU/ll, SHF/ ALU, SPO, R/wR I TE, RAB, SPO, RAB/fil 1"
• SPO. R /wRITE, RAB, SPCJ, RAB/@1, AMX /LA, ALU/ A, SHf I ALU"
"AMX/LA, RBMX/D, BMX/RBl<IX, ALU/ A+E, SHF' I ALU, SPO, R/WR ITE, RAB, SPO, RAB/!11"
• AMX/LA, RBMX /D, BMX/RBMX, ALU/ A+B+1, SHF' I ALU, SPO, R /WRITE, RAB, SPO, RAB/U"
• AMX/LA, B"X/KMX, KMX/ta2, ALU/ A+B, SH~· I ALU, SPO. R/WR 1 TE, RAB, SPO, RAB/(i 1"
• AMX/LA, BMX/K MX, K"X/fi2, Al.U/ A+B+ 1, R ((all -ALU"
"Al<iX/LA, BMX/K MX, KMX/fi2, ALU/ A+B, RLOG, DT /LONG, SHF' I ALU, SPO, R/llRITE, RAB, SPO, RAB/U"
"AMX/LA, BMX/LC, ALU/ A+B, SHf I ALU, SPO, R/WR ITE, RAB, SPO, RAB/(11"
• A"X/LA, BMX/MASK, ALU/ A+B+ 1, RC !111-ALU"
• AM x IL A , RB Mx I a , BM x IR BM x. AL u I A+ B, s Hr I AL u. s PO.RI" RITE.RAB. s PO.RAB I (11 •
• A"X/LA, RBMX/D, BMX/RB"X, ALU/ A-B, SHF' I ALU, SPO, R /WR I TE, RAB, SPO, RAB/111"
• AMX/LA, BMX/K MX, KMX /@2, ALU/ A-B, SHf I ALU, SPO, R/WR ITE, RAB, SPO, RAB/ti 1"
• AMX/ LA, BMX/KMX, P4X/ta2, ALU/ A-I!, RLOG, OT /LONG, SHF' I ALU, SPO, R/WR ITE, RAB, SPO, RAB/111"
"ALU/ A-B-1, AMX/LA, BMX/MASK ,SPO, R/WRITE, RAB, SPO, RAB/~ 1,SHF'/ALU"
• AMX/LA, RBMX/O, BMX/RBMX, ALU/ A-B, SHF' I ALU, SPO, R/WR I TE, !<AB, SPO, RAB/@11"
• AMX /LA, BMX/KMX, K~X/@2, ALU/ A~D, SHF' I ALU, SPO, R/WRITE:, RAB, SPO, RAB/(11"
• AMX/LA, RB"IX/D, BMX/RBMX, ALU/OR, SHF' I ALU, SPO, R /WR ITIC, RAB, SPO, RAB/~ 1"
• AMX/LA, BMX/l'ASK, ALU/ORNOT, SHr I ALU, SPO, R/WRITE, RAB, SPO, R~B/111"

R (] _K []
R []_LA

Rll-LA+D
R ll-LA+D+l
R ll-LA+K []
R[J_LA+K[]+I
IHl-LA+KCJ ,RLOG
RCl-LA+LC
R ll-LAOASK+l
RCl-LA+Q
Rll-LA-D
R(]_LA-K []
Rll-LA-K CJ ,RLOG
R Cl-LA-MASK-I
RCl-LA-0
R (J_LA,A~D.K [J
Rll-LA,OR,D
R[J_LA,ORlllOT,MASK

(I)

-4

m
3:
~

n
::c
0
n
0

cm
3:

n
::c
0

(I)

n
0
2

::i

R Cl-Q.RIGHT.1
R [ l -RLOG. RIGHT .1

"bMX/Ll:I, ALU/B, SHf I ALU, SPO. R/ld< l TE.RAB, SPO •RAB/II 1"
"BMX/l,C, ALU/!! 1 SHf I ALU, SP(l, R/~ll ITE. RAB, SPO. RAB/ii 1"
"BMX/LC, ALU/B, sHr 1R IGHT, sPo. R/wll IT<:. RAB, sPo. RAB/ti 1 •
"AMX/RAMX. OXT IDT/LONG I ALU/NOTA IR[~ 1] _ALU"
"RAMX/D I AMX /RAMX I ALU/NOTA IR [II 1 J _ALU.
• BMX/MASK I AMX/RAMX. OXT IDT /LONG I ALU/ORNOT I sHr I ALU I SPO. R/WR ITE. RAB I SPO. RAB/111"
• RAMX/O I AMX /RAMX I ALIJ/NOTA IR [!11 J _ALU.
"BMX/PACKED • fL, ALU/B, SHF I ALU, SPO, R/WR I TE. RAB 1 SPO. RAB/ti 1"
"SPO. R /WRITE, RAB, SPO. RAB/ti I, l<Af" X/Q, A"XIRAMX, ALU/ A, SHf I ALU"
"ALU-O+Q+l ,R [~I l-ALU"
"SPO. R/WR lTE. PAB, SPO. RAB/Ii!, ALU/ A+l:I+ 1, BMX/KMX 1 KMX/, 4, AMX/RAMX 1 RAMX/0, SHf I ALU"
"SPO. R/WR ITE. RAB, SPO, RAB/@ 1, RA~X /Q, AMX/RAMX, BMX/KMX, KMX/!12 1 ALU/ A+B 1 SHf /ALU"
"SPu. P /WRITE, RAB 1 SPO. RAB/ti 1 1 ALU/ A+B, AMX/RAMX, BMX/LB 1 RAMX/0, SHf I ALU"
• SPO. R/WRITE. RAB I SPO. RAB/ta!, RAMX / Q I AMX/RAMX I BMX/LC, ALU/ A+B I sHr I ALU.
"SPO. R/ WRITE. RAil, SPO. RAB/Ii 1, RAf"X/O, AMX/RAMX, RBMX/D, BMX/RBMX, ALU/ A·B, SHf I ALU"
"SPO. R/WR ITE, RAB, SPO. RAB/@ 1, ALU/ A•B• 1, AMX/RAMX, RAMX/Q 1 BMX/RBMX 1 RBMX/D, SHf /ALU"
"SPO. Ii/WRITE, RAB, SPO. RAB/~ I, RAMX/Q, AMX/Rf\MX 1 BMX/KMX 1 KMX/1!12 1 ALU/ f\•B, SHF / f\LU"
"RAMX/Q 1 f\MX/RAMX, BMX /KM X, KMX/!12 1 ALU/ A•B. RLOG, OT/LONG 1 SHf /f\LU, SPO. R/WRITE •RAB 1 SPO, RABI• 1"
"SPO. R /WRITE. RAB, SPO. RAB/@ 1, RAMX/Q, AMX/RA"IX, BMX/LC 1 ALU/ A•B 1 SHf I ALU"
•ALU/ AND, SPO. R /WRITE.RAB, SPO. R AB/Ol 1 1 AMX/RAMX, RAMX/Q 1 BMX/KMX 1 KMX/•2"
"SPO • R/WRI TE• RAB, SPO • R AB/tal, ALU/ ANDNOT, AMX/RAMX, RAMX/c.l 1BMX/KMX 1 KMX/!12 1 IS Hf I ALU"
"SPO. R /WRITE• RAP, SPO. RAB/ii 1, ALU/OR, AMX/RAMX 1 RA'IX/Q, BMX/RBMX 1 RBMX/D 1 SHF I ALU"
"SPO .R /wR ITE. RAB, SPO •RAB/!' 1, RAl'X/Q, AMX/RAMX 1 BMX/KMX 1 KMX/1!12 1 ALU/ORNOT ,SHF I ALU•
"ALU_O, SHf /RIGHT, SPO. R/WR ITE. RAB, SPO. RAB/l;J 1"
"BMX/O 1 MSC/READ. RLOG, ALU/B, SHf /RIGHT, SPO. R/WRITE. RAB 1 SPO, RAB/1!11"

SC,STATE-STATE·R CJ CEXPJ
SC-OCAl
sc_o-K c J
SC-ALU
SC-ALUCEXP)
SC-D
SC-DC EXP)
SC-DCEXPJ CAJ
SC-DC EXP) CB)
sc_o-K c J
SC-D.OXTCJ•KCJ
SC-D.OXTCJ .xoR.K CJ
SC-D,AND.K CJ
SC-D,OR,K lJ
SC-D,SXT[J
SC-EALU
sc_rE
SC-K CJ
SC-KCJ,ALU
SC-LA
SC-LA,AND,K Cl
SC-LCCEXP)
SC-NABS csc-rE)
SC-PSLADDR

"LAB-I< Cf' 1 l 1 AMX/LA 1 EBMX I Al'X. EXP, MSC/LOAD, STATE, EALU/ A•B 1 SMX/EALU 1 SCK/LOAD"
"AMX/ RAMX. OXT, DT /LONG, EBMX/ AMX, EXP, EALU /B, SMX/EALU, SCK/LOAD"
"BMX/K MX 1 KMX/!11, AMX/HAMX. OXT, DT /LONG, ALU/ A•B, SMX/ ALU, SCK/LOAD"
"SMX/ ALU 1 SCK/LOAD"
"SMX/ ALU, EXP 1 SCK/LOAD"
"RAMX/D, AMX/RAMX 1 ALU/ A, SMX I ALU, SCI< /LOAD"
"RAMX/D, AMX/RAMX, ALU/ A, Sl'X/ ALU. EXP, SCK/LOAD"
"RAMX/D 1 AMX/RAMX, FBMX/ AMX. EXP, EALU/B, SMX/EALU, SCK/LOAD"
"HBMX/D 1 BMX/RBMX, ALU/B, SMX/ ALU. EXP, SCK/LOAD"
"RAMX/D, AMX/RAMX 1 KMX/IH 1 Bl'X/KMX, f\LU/ A•B, SMX/ ALU, SCK/LOAD"
"RAMX/O, AMX/RAMX. OXT, OT /Ii 1, KMX/!12 1 BMX/KMX, ALU/ A•B 1 SMX/ ALU, SCK/LOAD"
"RAMX/D, AMX/RAMX, OXT, OT /f;J 1 1 BMX/K MX, KMX/!'2 1 ALU/XOR 1 SC-ALU"
"RAMX/D, AMX/RAMX 1 KMX /Ii 1, oMX/KMX 1 A LU/ A ND, SMX/ ALU, SCK/LOAD"
"RAMX/D, AMX/RAMX 1 KMX/IH 1 BMX /KMX, ALU/OR, SMX/ ALU 1 SCK/LOAD"
"RAMX/D, AMX/RAMX, SXT, DT /Ii 1, ALU/ A, SMX/ ALU, SCK/LOAD"
"SM XI EA LU, SCI< I LOAD"
"SM X/ f E, SCK/ LOAD"
"K MX/@1, EBMX/KMX, EALU/B 1 S~X/1:.ALlJ, SC~/LOAD"
"KMX/!i 1, BMX/Kl'X, ALU/H, SMX/ALU, SCK/LOAD"
"AMX/LA, ALU/ A, SMX/ ALU, SCK/LOAD"
• AMX/LA, KMX/l;J 1, llMX/K ~x, ALU/ AND, SMX/ ALLI, SCK/LOAD"
"BMX/LC, ALU/B 1 SMX/ ALU. EXP, SCI< /LOAD"
"EBI' X / f E 1 EALU /NA BS, A•A, SM X/ EA LU 1 SCK /LOAD"
•sMX/EALU, EBMXIKMX, scK;LoAD, 1<1<x1. r, EALUIB"

IHl-LB
R []_LC
R []_LC.RIGHT
RCJ_NOT.O
RCl-NOT.D
R Cl-NOT.~AS~
RCl-NOT.O
R []_PACK. f P
R Cl-0
RC J _0+1
R Cl-0+5
R Cl-Q+K Cl
RCJ_Q+Lll
R [J_Q+LC
R Cl-Q•D
R [ 1-Q-D•l
R Cl-O•K ll
R [J_Q•K Cl .RLOG
R [] -O·LC
R [J_Q 0 AND.K CJ
R CJ_Q 0 ANDNOT 0 K Cl
R Cl-0.0R.D
RCl-0.0R~OT.KCJ

O'>
(11

(I)

-I

s:
s:
n

:JJ

n
0

:JJ

(I)

c=;
0

::i

O'>
O'>

sc_a
SC-OCEXP)
SC-QC EXP) CB)
SC-OH CJ
sc_a-K CJ
sc_a.AND.K CJ
SC-Q.OR.K CJ
SC-Q.SXTCJ
SC-RC ( J
SC-RC CJ (EXP)
SC-R CJ
SC-R CJ CEXP)
SC-RCJ .AND.K CJ
sc_sc+ 1
SC-SC-tEXP ( Q) CA l
sc_sc+rE
SC-SC+K CJ
sc_sc+SHF. VAL
SC-SC-FE
SC-SC-K ( J
sc_sc-sHF. v AL
sc_sC.AND"OT.H
SC-SC.ANDNOT.K CJ
SC-SC.DR.I< CJ
SC-SHF. VAL
SC-STATE
SC-STATE. ANDNOT. K [ J
SC-STATE.OR.Kil
SD-NOT. SD
sD_ss
ss_o,sD_o
SS-ALU 15
ss_sD
SS-SS. XOR• ALU 15,SD-ALU 15
STATE-OCA)
STATE-OX.EXP
STATE-DCEXPJ
STATE-FE
STATE-FIRST
STATE-lNNEROBJ
STATE-INNERSRC
STATE-K CJ
STATE-OUTER
STATE-PREDEC
STATE-Q(EXP)
STATE-SC.VIA. KMX
STATE-SKPLONG
STATE-STATE+1
STATE-STATE+FE
STATE-STATE+K [ l

"RAMX/Q, AMX /RA MX, ALU I A, SMX/ A LU, SCI< /LOAD"
"RAMX/Q, AMX/fi AMX, EB MX I A MX. EXP, EA LU/ B, SM X IF.ALU, SCK/ LOAD"
"RBMX /Q, BMX/RBMX, ALU I B, SM X/ A LU. EXP, SCK /LOAD"
"RAMX /Q, AMX/ PAMX, BMX /KM X, KM X/ lH, A LU/ A+B, SMX/ ALU, SCI</ LOAD"
"RAMX/Q, AMX/RAMX, BMX/KMX, KMX/il 1, ALU/ A-B, SMX/ ALU, SCK/LOAD"
"PAMX /Q, AM X/R AMX, BMX/ K MX, I04X I ii 1, ALU I AND, SMX I ALU, SCK/ LOAD"
"RA MX /Q, AMX/RAMX, BMX/ KMX, KMX I U, ALU /OR, SMX/ ALU, SCK/ LOAD"
• RAMX/Q, AMX/RAMX. SXT, OT /ii 1, ALU/ A, SMX/ ALU, SCK/LOAD"
"SPO. R/LOAD. LC, SPO. RC/li 1, BIO /LC, ALU/B, SMX/ ALU, SCK/LOAD"
"SPO. R/LOAD. LC, SPO. RC/Iii 1, BMX/LC, ALU/B, SMX/ ALU. EXP, SCK/LOAD"
"SPO. R/LOAD. LAB, SPD. RAB/lil, A"X /LA, ALU/ A, SMX/ ALU, SCK/LOAD"
"SPO. R/LOAD. LAB, SPO. J<AB/lil, AMX/LA, ALU/ A, SMX/ ALU• EXP, SCK/LOAD"
"ALU/ AND, AMX/LA, SPO. R/LOAD. LAB, SPO. RAB/111, BMX/KMX, KMX/il2 ,SMX/ ALU, SCK/LOAD"
"EALU/ A+ 1, SMX/EALU, SCK/LOAD"
"EAL U I A+B, EBM XI AMX. EXP, SMX /EALU, SCI< /LOAD, A MX /RAMX, RAMX/Q"
• EBMX I f"E, EALU/ A+B, SMX IE ALU, SC K /LOAD"
"KMX/[11, EBMX/KMX, EALU/ A+B, SMX/EALU, SCK/LOAD"
"EALU/ A+B, EBMX/SHf". VAL, SMX/EALU, SCK/LOAD"
"EBMX /f"E, EALU I A-B, SMX /EA LU, SCI< /LOAD"
"KMX/ ii 1, EBMX /KMX, EA LU/ A•B, SM X/EA LU, SCK /LOAD"
"EBMX I SHf" •VAL, EALU I A•B, SMX/ EAL U, SCK /LOAD"
"EBMX I f"E, EALU/ ANON OT, SMX /EALU, SCK /LOAD"
"KMX/111, EB"X/KMX, EALU/ ANDNOT, SMX/EALU, SCK/LOAD"
"KMX/(i 1, EBMX/KMX, EALU/OR, SMX/EALU, SCK/LOAD"
• EBMX/ SHf". VAL, EALU /B, SMX/EALU, SCK /LOAD"
"EALU/ A, MSC/LOAD. STATE, SM X/ EA LU, SCKI LOAD"
"EALU/ AND NOT, EBMX/KMX, MSC/LOAD. STATE, SMX/EALU, SCK/LOAD, KMX/U"
"EA LU/OP, EBM XI KMX, MSC/LOAD. STATE, SMX/EA LU, SCK/LOAD, KMX/ lit"
"SGN/NOT.SO"
"SGN/SD.f"ROM.ss•
"SGN/CLR.SD+SS"
"SGN/LOAD.ss•
"SGN/SS. f"ROM. so•
"SGN/SS.XOR.ALU"
"AMX/RAMX. OXT, OT /LONG, EBMX/ AMX. EXP, EALU/B, MSC/LOAD.STATE"
• EBMX I AMX .'EXP, EALU I B, MSC/LOAD. STATE"
• RAMX/ D, AMX/RA"X, EBM X/ AMX. EXP, EALU I B, MSC /LOAD. STATE•
"EBMX I f"E, EALU/B, MSC/ LOAD. STATE"
"STATE-I< CZEROJ •
JEOITPC STATES
"STATE-KC.ll"
IMATCHC STATES
"STATE-KC. 31 •
"K MX I li 1, EBMX/K MX, EALU/B, MSC/LOAD. STATE"
"STATE-K !ZERO]"
"STATE-K(.80J"
"RAMX/Q, AMX/RAMX, EBMX/ AMX. EXP, EALU/B, MSC/LOAD. STATE"
"MSC/LOAD. STATE, EALU /B, EBMX I I< MX, KMX/ SC"
"STATE-KC.4l"
JSKPC STATES
• EALU/ A+ 1, MSC/LOAD. STATE•
• EBMX /f"E, EALU I A+B, MSC/LOAD. STATE•
"l<MX/(!11, EBMX/l<MX, EALU/ A+B, MSC/LOAD. STATE"

en
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en
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'.I

STATE-STATE•n:
STATE-STATE•K CJ
STATE-STATE, AN ,SKPLONG
STATE-STATE, AN, 5TOO
STATE-STATE, AN, 6T04
STATE-STATE, AN, DESTDBL
STATE-STATE, AN, NOTPREDEC
STATE-STATE, AN, PREDECZE:RO
STATE-STATE, AND1'0T, FE
STATE-STATE, ANDNOT, KC J
STATE-STATE, AND!IOT, SHF, VAL
STATE-STATE ,QR ,FE
STATE-STATE ,OR, KC J
STATE-STATE, 01!, ADJ I NP
STATE-STATE ,OR, DEST
STATE-STATE, OR, DESTDBL
STATE-STATE.OR, FILL
STATE-STATE ,OR, FLOAT
STATE-STATE, OR, MOVE
STATE-STATE.OR, PATTl
STATE-STATE, OR, PATT2
SWAPD

• EBMX I f E, EALU/ A•B, MSC /LOAD, STATE•
"KMX/(I 1, EBMX/KMX, EALU/ A•B, MSC/LOAD, STATE"
"STATE-STATE, ANDNOT, KC, 4l •
•STATE-STATE ,ANDNOT ,KC. 3FJ"
"STATE-STATE, ANDNOT, KC, 7FJ •
"STATE-STATE, ANDNOT, KC. 6J •
"STATE-STATE ,ANDNOT, KC, 7FJ •
"STATE-STATE, ANDNOT. KI, CO l •
"EBMX/FE, EALU/ AfllDNOT, MSC/LOAD, STATE"
"KMX/til 1, EBMX/KMX, EALU/ANDNOT, II SC/LOAD ,STATE"
"MSC/LOAD, STATE, EBMX/SHF. VAL, EALU/ ANDNOT"
• EALU/OR ,·EBMX/FE ,MSC/LOAD .STATE"
"KMX/111,EBMX/KMX, EALU/OR, MSC/LOAD• STATE"
"STATE-STATE,OR.KC.31"
•STATE-STATE. OR.KC. 41"
"STATE-STATE,OR,K C.61"
"STA'l'E-STATE,OR,K [, 71"
"STATE-STATE, OR, KC, 60] •
"STATE-STATE,OP,K C,50]"
"STATE-STATE, OR, KC .1 l "
"STATE-STATE, 011. KC, 21"
"DK/BYTE,SWAP"

VA-ALU
VA-D
VA-D+KCl
VA-D+LC
VA-D+O
VA-D.OXT [J+O
VA-D.ANDNOT.KCJ
VA-K CJ
VA-LA
VA-LA+D
VA-LA+K CJ
VA-LA+K [ l+ 1
VA-LA+PC
VA-LA+O
VA-LA•D
VA-LA·K CJ
VA-LA·KCJ•l
VA-LA•O
VA-LA.AND.LC
VA-LA.ANDNOT.K!J
VA-LB+D • OXT
VA-PC
VA-0
VA-O+D
VA-O+K[J
VA-O+LB
VA-O+LB.PC

"VAK/LOAD"
"RAMX/D, AMX/RAMX, ALU/ A, VAK/LOAD"
• RAMX/D, AMX/RAMX, KMX/tl 1, BMX/KMX, ALU/ A+B, VAK/LOAD"
• RAMX/D, AMX/RAMX, BMX I LC, ALU/ A+B, V AK/ LOAD"
"RAMX/D, AMX/RAMX, RBMX/0, BMX/RBMX, ALU/ A+B, VAK/LOAD"
• RAMX /D, AMX/RAMX, OX T, DT /tll, BMX/R 8MX, ALU I A+B, V AK/LOAD"
"RAMX/D, AMX/RA MX, BMX/K MX, KM X / 1!11, ALU I ANDNOT, V AK /LOAD"
"KMX/111, BMX/K MX, ALU/B, V AK /LOAD•
"AMX/LA, ALU/ A, YAK/LOAD"
• AMX/LA, RBMX/D, BMX/RBMX, ALU/ A+B, VAK/LOAD"
"AMX /LA, BMX/K MX, KMX /(I 1 , ALU/ A+B, V AK/LOAD"
• AMX/LA, BMX/KMX, KMX/tl 1, ALU/A+B+l, VAK/LOAD"
"AMX/LA, BMX/PC, ALU/ A+8, VAK/LOAD"
"AMX/LA, RBMX/O, 8MX/RBMX, ALU/ A+8, VAK/LOAD"
• AMX/LA, R8MX/D, 8MX/RBMX, ALU/ A•8, VAK/LOAD"
"AMX/LA, BMX/ KMX, KMX /tll, ALU I A•8, V AK /LOAD"
"AMX I LA, 8MX/KMX, KMX/!11, ALU I A•8• 1, YAK /LOAD•
"VAii/LOAD, ALU/ A•8, AMX/LA, 8MX/RBMX, RBMX/O, SHF I ALU"
"AMX/LA, BMX/LC, ALU/ A ND, V AK /LOAD"
"AMX/LA, BMX/K"'X, KMX/111, ALU/ANPNOT, VAK/LOAO"
"8MX/L8, ALU/ A+B, AMX/RAMX. OXT, OT/BYTE, VAK/LOAD"
• BMX/PC, ALU/8, YAK/LOAD"
"RAMX /0, AMX/R AMX, ALU/ A, VA K/LOA D"
• VAK/LOAD, ALU/ A+B, A MX /RAMX, BMX/R8"1X, RAMX /0, R8M X/D 1 SHF I ALU"
"RAMX/O, AMX/RAMX, KMX/111, BMX/KMX, ALU/ A+8, VAK/LOAD"
"RAMX /0, AMX /RAMX, 8MX/L8, ALU/ A+e, YAK/ LOAD"
"RAMX/O, AMX/RAMX, 8MX/PC. OR ,Le, ALU/ A+B, YAK/LOAD"

(I)

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0

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"RAl'X/Q, AMX/RAl'X, BMX/LC, ALU/ A+B, VAK/LOAD"
"RAMX /0, AMX/RAMX, BMX /PC, ALU/ A+B, VAK/LOAD"
"RAMX/Q, AMX/RAMX, KMX/lil 1, BMX/KMX, ALU/ A•B, VAK/LOAD"
• RAMX /0, AMX/ RAMX, BMX I LA, ALU/ A•B, VAK/LOAD"
• RAMX/Q, AMX/RA"X, KMX /U, BMX/KMX, ALU/ ANDNOT, VAK/LOAD"
"SPO, R /LOAD, LC, SPO, RC/Ii 1, BMX/Lr, ALU/B, VAK/LOAD"
"SPO, R/LOAD, LAB, SPO, RAB/Ii 1, AMX/LA, ALU/ A, VAK/LOAD"
"PCK/VA+4"

VA-O+LC
VA-O+PC
VA-O•K CJ
VA-O•LB
VA-0,ANONOT,K[]
VA-RC Cl
VA-R Cl
VA.VA+4

• roe

CJ)

~aero

definition

: Non-transfer macros•

B,F"ORK
BYTE

"LAB.R (SP 1), OK/ID, CLR, IB, COND, PC-PC+N, SUB/SPEC, JIB, FORK"
"DT/BYTE"

C, f"ORK
CACHE, INVALIDATE
CALL
CALL CJ
CHK, FLT, OPR
CHK, 000, ADDR
CLK, UBCC

"SUB/ SPEC, J/C, FORK"
"MCT /I NV ALI DATE, VAK/NOP"
"SUB/CALL"
"CALL,J/U"
"MSC/CHK,fLT,OPR"
• l'SC/CHK, ODD, ADDR"
"CCK/LOAD,UBCC"

CLR, F'PO
CLR, IB,COND
CLR, IB,OPC
CLR,JB,SPC:C
CLR,IBO•l
CLR, IB0•3
CLR,IB2•3
CLP, 182•5
CLR, NEST, ERR
CLR, SD&SS

"MSC/CLR ,fPD"
"IBC/CLR, 1-~, COND"
"I BC/CLR, 0, IEK /ISTR"
"IBC/CLR, 1"
"IBC/CLR,O, I ,IEK/ISTR"
"IBC/CLR,0·3"
"IBC/CLR, 2, 3 •
"IBC/CLR, 1•5,COND"
"MSC/CLR, NEST, ERR"
"SGN/CLR, SD+SS"

E, F'ORK
EXCEPT, ACK

"SUB/SPC:C, J/E, FORK"
"IEK/EACK"

Cl>

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3:
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n
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0
n
0

m
3:

::n
0

Cl>

n0
:DISCARD •11 INSTR & OPERAND
: 11 MODI'" DISCARD !STREAM OPERAND
12ND ~ART OF. Q/D IMMEDIA1E

F'LUSH,lB

"lBC/fLUSH, \AK/LOAD, I C:K/ lSTR"

G ,F'ORK

"SUB/ SPEC, JIG, FORK"

INHll\lT.lB
l NTRPT. ACK
I NTRPT, STROBE
I RD
!RD, 11
lt<DO
IRDl

"MCT/MEM,NOP"
"IEK/lACK"
"IEK/ISTR"
"Il~DO ,CLK, UBCC, lRDl, SUf\/SPE"C, J/A, !'"ORK"
• LA_R COST) &Li:l.R (SPC), D-LB. PC, VAK/LOAD, a_rn, DATA, sc_K [. 1 OJ, PCK/PC+N, !llSC/IRO, SUB/SPEC ,J/DPO"
"LA_R ( SP2 l &LB.P (SP I l, D& VA-LB, SC-ALU (EXP), fE-LA (EXP), SS-ALU 15"
"MSC/I RD, OK/ID, MCT I ALLOW, 18, READ, IBC/CLR, 1 •5, CONO, PCK/PC+N"

::!

LOAD.ACC.CC
LOAD.IS
l.OAD.IB.11
[,ONG

"MSC/LOAD. ACC .CC"
"VAK/l;OP, MCT /READ. V. NEW PC"
"VAK /NOP, 1'.CT /READ. V. l;E wPC"
"DT/l.ONG"

O!EMOR~. NOP

O!Ul..1XT
MULM. DONE
MUl.P. DON!'.:

"OICT/MEM.NOP"
"SI /fol U l. + , SC -S C-K C • 1 I , Bf NIM U[, "
"SI /MU[,-, sc_sc-1< [ .1 I , BfN/MUl..
"D-D. RIGHT2, SI /MU[,-, IlllTPPT. STROBE"
"D-D. R IGHT2, SI /MUL+, IN TR PT. STROBE"

POLY .DONE

"ACF /CONTROL, ACM/POLY. DONE"

RETURNO
REl URN 1
RETURN10
RETURN 100
RETURl;10C
RHURN10E
RETU!<N12
RETUPN 18
RETURN1f
RETURN2
RETURN20
RETURl;24
RETURN)
RETURN4
PETURN40
RETURN60
RETUR11161
RETURNS
RETURN9
RETURNf
RETURN Cl

"SUB/kET ,J/0"
"SUB/RET,J/1"
"SUB/RET ,J/10"
"SUB/RET,J/100"
"SUB/RET,J/10C"
"SUl!/RET ,J/10E"
"SUl!/REl·,J/12"
"SUB/RET,J/18"
"SUA/RET,J/11'"
"SUB/RET ,J/2"
"SUB/RET ,J/20"
"SUB/PET ,J/24"
"SUB/kET,J/3"
"SUB/RET ,J/4"
"SUl:l/RET ,J/40"
"SUB/PET ,J/bO"
"SUB/RET ,J/61"
"SUB/PET ,J/8"
"SUH/RET, J/9"
"IWB/RET ,J/Of"
"SUB/RET ,J/!11"

~UL.OXT

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:j,

SET.CCCBYTE)
SET.CC( INS'!)
SET.CCCLONG)
SET.CCCROR)
SET.CCC WORD)
SET.FPO
SET. NEST. fRR
SE'I.PSL.C(AMX)
SET. V
SPEC
SP ECG
START.IB
STOP.IS

"CCK/ INST• DEP, DT /BYTE"
"CCK/ INST. DEP, DT /INST. DEP"
"CCK/ INST. DEP, DT /LONG"
"CCK/ROR"
"CCK/ INST. DEP, DT /WORD"
"MSC/SET.FPO"
"MSC/SET. NEST• ERR"
"CCK/C_A"XO"
"CCK/SET. V"
"LAB-RCS Pl l, O_l B, DATA, CLR, IB .COND, PC-PC+N, MCT I ALLOW, IB, READ, SUB/SPEC 1 JIC, FORK"
"LAB-RCS Pl l, O_IB. DATA, CLR, JB. COND, PC-PC+N, MCT I ALLOW, IB, READ 1 SUB/SPEC ,JIG, FORK•
"I BC I STA RT"
"IBC/STOP"

TEST.Tt!,RCHK
TES'!, Ttl, WCHK
TRAP.ACCCJ

"MCT/TEST, RCHK, V Al< /NOP"
"MCT /TEST, WCHK, VAK/>jOP"
"ACF/TRAP,ACM/1!11"

WORD
wRITE,DEST
WRITE.G.DEST

"OT/WORD"
"LAB-RCS Pl l, QK I ID, CLR, 18 ,COND, PC-PC+N 1 SUB/SPEC, J/wRD"
"LAB_R CS Pl), OK/ID ,CLR, IB. COND, PC-PC+N 1 SUB/SPEC, J/WRG"

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--.J

~aero

definition

Branch enable macros"

AC,L01j?
ACC,SYNC?
ACCEL?
ALIGNED?
ALU, N?
ALU1•0?
ALU?

"BEN/INTERRUPT" I ,J3/3"
"BEN/ACCEL"
; ,J3/3"
"BEN/ACCEL"
"BEN/TB, TEST"
; ,JS/17"
"BEN/ ALU"
; ,J4/07"
"BEN/ALUl•O"
"BEN/ALU"

BCDSGN?

"BEN/DECIMAL"

CH?
CONSOLE, MODE?

"BEN/C31"
"BEN/PSL,MODE"

0(1)?
D,80?
D.81?
0,82?
D,BYTES?
D,NE,O?
00?
02-01
D2?
03-0?
031?
Dl?
DATA.TYPE?
DBL?

"BEN/MUL"
"BEN/D,BYTES"
;,J4/0E"
"BEN/D,8YTES"
I ,J4/0D"
"BEN/D,BYTES"
I ,J4/0B"
"BEN/O, BYTES"
"BEN/SIGNS"
;,Jl/5" ; PllEFERED F'ORM
"BEN/03•0"
;,J4/0E"
"BEN/03•0"
; ,J4/08"
"BEN/03•0"
J ,J4/0B"
"BEN/03·0"
"flEN/SIGNS"
;,Jl/6"
"BEN/03•0"
; ,J4/07"
"BEN/DATA.TYPE"
"BEN/DATA,TYPt:"

EALU,N?
EALU,Z?
EALU?
END,DPl?

"BEN/EALU"
"BEN/EALU"
"llEN/EALU"
"BEN/END,DPl"

; ,J4/07"
I ,J4/01\"

FPO?

"BEN/LAST.REF"

J ,J4/07"

IB, TEST?
I NT?
INTERRUPT,REQ?
IRO,C31?
IRO?
IRl?
1R2•1?

"BEN/lB, TEST•
"BEN/ INTERRUPT"
"BEN/INTERRUPT" I ,J3/5"
"BEN/ALU"
"BEN/ALU"
7,J4/0D"
"BEN/IR2·1"
; ,J3/6"
"llEN/1R2•1"

LAST, REF?

"BEN/LAST.REF"

MODE,LSS.ASTLVL?
MUL?

"8EN/RFI"
"BEN/!o!UL"

I ,J2/2"

; ,JS/lB"

I ,J3/3"

(/)

-4

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0
(")
0
0

(")

::n
0

(/)

n0
2

:::!

"-J

NEST.ERi!?

"BEN/LAST. REF"

PC. MODES?
PSL .C?
PSL.CC?
PSL, MODE?
PSL,N?
PSL • V?
PSL. Z?
PTE,VALIIJ?

"BEN/PC.fl.ODES"
"BEN/PSL,CC"
"BEN/PSL,CC"
"BEN/PSL,MODE"
"BEN/PSL.CC"
"BEN/PSL.CC"
"BEN/PSL.CC"
"BEN/TB, TEST"

031?
QUAD?

"BEN/SIGNS"
I ,Jl/ 3"
"BEN/DATA, TYPE"

RLOG.EMPTY?
ROR?

"BEN/ALUl-0"
"Bl::N/llOR"

sc.GT.O?
SC.NE.O?
SC?
SIGNS?
SRC.PC?
SS?
STATE C1)?
STATEO?
STATEl-0?
STATEl?
STATE2?
STATEl-0?
STATEl?
STATE4?
STATES?
STATE&?
STATE7•4?

"BEN/SC"
"BEN/MUL"
"BEN/SC"
"BEN/SIGNS"
"BEN/SRC.PC"
"BEN/EALU"
"STATE 7-4?"
"BEN/STATE3•0"
"l:IEN/STATEl•O"
"BEN/STATEl-0"
"B'EN/STATEl-0"
"BEN/STATEl-0"
"BEN/STATEl-0"
"BEN/STATE7•4"
"BEN/STATE7-4"
"BEN/STATE7-4"
"BEN/STATE7-4"

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I ,J4/0B"
; ,J4/0F"

m
3:
3:

I ,J4/7"
I ,J4/0D"
; ,J4/0B"
I ,JS/OF"

c:;

::n
0
n
0

I ,J4/7"

m
3:

1,Jl/l"
;COMP MOOE, BEN ON SRC R
I ,J4/0E"
; ,J4/0E"
I, J4/0C"
; ,J4/00"
; ,J4/0B"
1 ,J4/07"

TB. TEST?

"BEN/TB.TEST"

VAll-30?
VA31?

"EIEN/PSL,MODE"
"BEN/PSL.MODE"

; ,JS/07"
;,JS/OF"

Z?
ZONED?

"BEN/Z"
"BEN/DECIMAL"

1 ,J2/1"

n
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0
en

n0
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::!

FPA CONTROL WORD FIELDS

I I I I I I I I I I I I I I I I
~L_

NEXT ADDRESS

'-----r---'
EALU
CONTROL

BUS A- BUS B
DATA SOURCE

EALU B
INPUT

18 17

MISCELLANEOU~lSCRATC~

EXPONENT
PROCESSOR
CONTROL

MCTL

FPSYNC

EALU A
INPUT

BRANCH
ENABLE

CONTROLS
WAIT

PAD
NORM.
CONTROL
REGISTER

SIGN LATCH
CONTROL

FRACTION
PROCESSOR
CONTROL

MULTIPLIER
OPERAND
CONTROL

REMAINDER
REGISTER
CONTROL
TK-0513

"T1

;FIELDS ARRANGED FROM HI TO LO ORDER BITS

.fHOL

(")

.roU,AC:':CP.1AL

NAD/=0,9,39,+

;NEXT AD~K~SS DEFAULT IS THE FOLLOWING
;MICRO WCF-.'.)

SEN/=C,3,36,D

; BRANCH EtiASLE

:OE:'; 1=1

0
r-

;DEFAULT
;SEE TABLE FOR EXPLANATION

c,:::r<2= 2

3::
::!!

s~~'~'=J

e::N~=4

B::C'iS=S
5E'.\.c.=5

:J::;:;--;'/=7
A'\1~C/=2, '2, 34, D

z
:c

-t

"T1

; Eid.U A

l NPJT

-t

L8=1

PR=:;:·
CO~W= 3

BMXC/=0,2,3./:,D

:SEL L~ :o c .A ~U
;SEL LB '.J f.:A:..U
; Sf::.L PR -:-o E .~ :..U
;ADD. CO'C': I I CN.A l
;EALU B HOP ..iT
;~c:.1

NCR'·:,:..rZATION CGt<STAtJT

tJL.;:Q
>-!i= 1
ti SJ= 2

;R~STCRE

LS'-'3

;Sc:... LC :·-.::

EA LUC/ =O. 2, :.oO, ::.:-

; ': ; E G I S ' :'. R

; !:ALU

~>:~ss
E.:.~u

co·.-: ;:::;·_s

30(16) NOTATION

0
z

~=0

A-5=i

.,,

D.\SS M/'_·>\
,\MX r,1lN~·5"

A:-..:x P LU:;

B',1;(
~

r.:.;z

n
0
z
-I
::c

EALU=3Ff
FPSYNC/=0,1,:29,D
'\C!Pco C
F ?S= 1

; SY NC T 0

:.. '-' ~J

; ASSERT

F ::: 3 \ ~•C

0
r-

::c

MCTL/=0,1,28,D

e
cm

~~ :J ~ = 0

......

(.Tl

C.", T = 1

; START ,\

l.'~LTIPL.Y

EAC/=0,4,;'.4,D

;EXPONENT

~RC:ESSOR

CONTROLS

NCJP=Cl
LDX;:;=1
LC>';:=2

POLY

Pk.l\R=3

LOAD
LB

XR.LSc.5

PR.LE=l3
PR.XR.LS=7

LDA=B
~R.LA=9

PR.LA=O,.\
PR. XR. L,.\=OB
XR • .'..3=0D

PR . .'.\EC='.lE
LC.ALL=OF

ARG

PRO~UCT

P"i

GETS

EXP REG GETS EALU
EXP REG GETS EALU
AR

:i<

e.:..;s

6:..5, XR GETS EALU
LB_BUS, "'R_EA LU
LB_BUS, C?~.XR EALU
LB GET~

LA_BUS A
LA_ BUS. >:R
LA_ BUS, PR

::_,\LU
::.1-. L'.J

LA_BUS

1-.,

·rn EALU
S SJS 8

LA_BUS
LA BUS

4,
A,

s aus a,

LA_BlJS.

Pr;

B_BUS

XR_EALU
PR EALU

:::!
0

Cl>

c;
0

.,,

WAIT /=O I 1. 23 ID

~
C')

NOP=O

\~AI1=1

-4

MSC/=C,3,20,D

;MISCELLA\EOUS CONTROLS

:a
0

::a

NJ>'ocO

P.ADiJ=1
MC=2
R~.0=3

CC=.;
LDSX=5
IR0=6
I P.1=7

;POLY AD~ FOP SI:N ?RO~ESSOR
;SET ERR:~ BLT FDR RESRVD OPND
;CLE/'.\R R_
:·.:iER REGISTER
;ERROR co~~!TlONS
;LOAD SIG'., C'" X FOR POLY
;INSTRUCTIJ~ 3RANCH 0
;INSTRUCTIJN BRANCH 1

.,,3:

;NDRMALI:ER REGESTER

......

(J)

NRC/=3,2,18,D

e
0

.,,m
z

NQP='.?1
SL=2
LD=O

;SHIFT LEFT ,NORMALIZE)
;LOAD BUS A, BUS B

SCR/=0,2,16,D

;FPA SCRAfCH DAD CONTROLS

CPU=O
DPR.R=1
R.R=2
DP=3

; DATA

BSC/=8,4,12,D
HJTH=3
NL=4
NH=5
PQ=6
INTL=7
10=8
LR=9
ID.RB=OA
R=OB
FAL.X=OC
F~~.LH=OD

FAL.!-'.L=CE
FADC/=OC,4,8,D

SO~RCE

FOR BUS A AND BUS B

;INTEGER PRODUCT HI TO BUS A
;NSHFL TO BUS A, BUS A TO BUS 8
;NSHFH & ~X? TO 9US A, A :O 8
;PROD/QUOTH TQ BUS A, P/QL TO BUS B
;INTEGER P~C:~ TO BUS A
;ID BUS TC ELS A, B
;IBUF DA-~ REGISTER TO BUS
;ID TO B~~ ~. RS TO BUS B
;RA TO BUS A, RB TO BUS B
;HARDWARE DETER~!NED
;FALUL TQ 3JS A, FALUH TO BGS B
;FALUH TC SUS A, FALUL TO BUS B
;FRACTIOh CRQCESSOR CONTROLS
;LOAD AR 1 , ARO
;LOAD BR1

AR1~2

;LCAD ARi

R1=3
5R=4
ER0=5
AR0=6

; LOAD AR~, 81:?1
; LOAD BR:, SRO
;LOAD BR:;
; LOAD AR.}

RC=7

;LCAD BRJ,

LD=S
A.2=0A

; LOAD A.R. S=i
;HARDWARE DETER~INED ADD/SUB
;OUTPUT t.R
;OUTPUT BF\

LD::3
A.S
A.R

1
=2
::3

i3i.JS A ( 1::)

;.,:

r:lJ

3::

:!!

:::!
0

;_qo

SIGN LAT HES

No;;~o

....:lJz

:!!

;SIGN LA-CH ::NTROLS

SGNC/=0,3,5,D

C')

AR=O
s~ 1=1

A=CC
3=0D

'Tl

UNSHA~GED

s;..

IF SUB,
A<- r~OT SA ; ELSE SA <- SA
RESULT S G~~ TG Sh

n
0
z

::!

DSB~4

; BUS B ( 1 ':.i :

DScS
. E:" b

;BUS A(15; TO SA
;SE TQ SA
;SA XOR A TJ SA

.XOR.X=7

.,,

'T1

BuS 3( ~5) TO SB

("')

LRR :0,'.,4,'.J

;REMAIN8E~

RLGISTER CONTROLS

t,,JOP =O

; LOAD REr:;. I NJER REG! ST ER

L::>. ~f;': 1

;MULTIPLIER OPERAND CONTROLS

OPLD/=6,4,0.D

;LO.l-D MUUlPLIC::>t;o
;LOAD UP~~S rlALF OF MULTIPLICAND
;LOAD DP LO~ ~ALVES
;LOAD LO~~~ HALF OF MULTI~LICAND
;LOAD ALL ~o~ R-q
;LOAD M'C~~D INTE3EC&~ULTIPLIER HIGH FRACTION
;LOAD MU~l!~~!C~\D !NTEGER
;LOAD MULT1,::·LIEi'<
;LOAD LO~~q rlALF OF MULTIPLIER
;LOAD MULTiP_!EP, HIGH FRACTION
;CONTROL !~l~IA~IZATION

MC=1

i,1( 1 =2
~-1c.ro=4
~.i::: 0

LSR. ~: :::8

.....i

rJJ

s::

'T1

NCP=o

~/C:l.",'P1=0A

~'.,~loOB

MP=OC
~11PO = 0 D
MP 1 =0 E

! NIT "OF

e
cm
'T1

z
~

0
z

Cl>

n
0
z

:::!

BEN TABLE

UADRS<1>

: BEN

l NCJP)

F!..GAT H

I RBR1

.,,

(OPCODE BRANCH)

""D

SwR H

SWR H

S"-R rl

(\CC~ALIZAT!ON

RSV H

B=O H

A=O

(ZEROES A\0 RESERVED OPERANDS)

SHIFT WITHIN RANGE)

POLY DONE L

CPSYNC H

FLOAT H (SYNCriRGNIZATION WITH CPU)

(.A OR 6)=0 H

SUS*ED<2 H

S~31'.)0'J8LE*ED>8

«~~L/DIV

DONE H

[PR=O+PR<9>] L

p;'8> H

(OVER/U~D~RFLOW

(EXP. DIFF.)

c.o

"BSC/PQ, Ft.~1C/AR"
11
:.1SC/!R1 ,t.'.~O '100,WAIT/WAIT"

IN POLY)

CFLJ_~.NSH

"S~XC/NK.3SC NH,AMXC/PR,EALUC/A
"BMXC /NK. s~~C/N L. Ar1:xc I PR. EA LUC/ A))

iR0
L. .:&f-R_L B
L~l;'R_PR-K

AMXC/PR.~AL~C1A

"AMXC/PR,S~XC;XR,EALUC;A-B"
" t<;j

s c .1 cc ))

NAD/OA3.~ALJC/3,F~DC/LD.SGNC/A.RES,BSC/NH,OPLD/INIT,MSC/RR.O"
11
BS C/ i\ H , 1" r: .Y. C,' L3 , E." l. UC I A , ::_AC/PR • L,\ "
"AMXC/PR.Eh~u:,~-6.5~~C/u80,BSC/NH,EAC/PR.LA"

L,',.::SA_O

"EALUC/K~FF,f:xc

L.~_O

"EA LUC/K:; c"'. ['," :<.C, '.·.1'. BSC; ~~, •• EAC/ UJA. AMXC/PR II
" .1\1\1 x c IL B ... : ':\;: . f'. ' ::: t I_ i.) c /A . SS c /NH . EA c IL OA II

l:~

!_B

"AMXC/PR.~~L0C

L5_J

"EA L.uc/K 0 =•'. ~: i'

LB_t:"1

"~M\C/PR,~AL~C

::D

.,,3:
m
r-

::!
0

(I)

"SCRjR.R.FADC/R1 ,MSC/!RO,ESC/R,SGNC/LDS,OPLD/LOR.R.EAC/LOAB"
"FF'SYNC/F=s·

LA_PR
LA_Pl'+ri
LA_P ',--K

0
r-

.,,

"BSC/NL,EA~JC/K3FF,AMXC;PR"

-I
::D

e
c
m

AR_PROD
BFOr\K
BLiS_O
CPU_At.SL
EALU_PR
Et.LU_PR-XR
ERCH
F:•,~. I RD
F"S!NC

"TRANSFER MACRO DEFINlTICN'.3 11

......i

C')

NK,SSC/~H.EAC/LDA,SGNC/A.RES,AMXC/PR"

~.B~XC/LB,GSC;NH.EAC/LDA"

Ar.1 x c / PR , ;:: ·, ~ :_. c :.. -.- 6 . U." x c / " ::: o • Bs c / NH . EA CI LDA "

A~XC/PR.~~~LC

A-B,S~iCjaSO,BSC/NH,EAC/LDA"

:.: "NK, ssc;e. 1_, EAC/ LOB, SGNC/ LDSB 11
A,B~XC/LB,5SC/NH.EAC/LDB"

0
0

::!

LB_f' :;-K
LGAJ. t10
LCA!:I .•~ 1

LO.AC.b
LOA::J. 80

LCAD.01
LOA'.).COEFH
LOt.D.COEFL
LCAD. »1R
LOA).2'.::>B
MCO_NSHFL
MC 1 _~·;SHFH

"AMXC/PR.~AL_UC/A-8,BMXC;•BO,BSC/NH,EAC/LOBM

FADC/ A.R:i, J? :..c-.·r.oco"
"FADC/ AR 1 , E'\~i:..: A, SGNC/ LDSA, OPLD/ LOR. R"

"FADC/BR,El~ LC2.SG~C/LDSB,OPLD/MP"
"FADC/SRJ.C~-~/~DO"
"F ADC/ SR 1 • EA:.: i LDE., SGNC / LC•SB, OP LD/MC I. MP 1 "
"BSC/lD, =~::,.:: BR; ,EAC/LOS,SGNC/LDSB"

SUM
NR_AR
NR_9R
NR r :.D

00
0

::zJ

"ESC/NL,C;::L_C· ·r.1co"
"BSC/NH,O~:..o

~Cl"

83C/FAL.~L,FADC/B,OPLD/MC

::!!

0PLD/lNl".'"
"BEN/O 1•
EAC/ LOP
2(.',C, A. RES. SSC/NH' MSC/CC EA LUC/ A+B' AMXC/PR' BMXC/NK M
"EAC/ LOP R, .C.'.;';C /A. RES. ESC/ l•H, MSC/P. ADD, EA LUC/A+B, AMXC/PR, BMXC/NK •
II

.l'

FADC/A,i~S1_

".4L.,..,L.~;RC/LD·'

"3SC/PQ, ·;-.:

:..J •

~P_Q:_iCT

LJ"

:::.::LY. AC'D

"MSC/P.AJ
"AMXC/LEl,

PD _CC,~,D

FR_K

P::?_'..A

LA+f"
Ud LA

11
II

8SC/PQ.~.;:-·~:

EJ'..'.XC / h8)

'ct.>._',

PR i..E

Al\lXC/ '..8. "-

/kJFF, E,OC iLOPR"

E,EALUC/A•S,EAC/LDPR

~.~~LUCIA-B,EAC/LDFR"

·~

A, EAC/LDf'~··

c;
0

~+S,S~XC/t80,EAC/LDPR"

"i<MXC/LA,
Af•IXC/ LA.

?R_L.~•r-.<ROM

;l,=t.C/LDPR"

AfliXC/LA.
AMXC/ Lt..

=t
0

E.EALUC/A-8,EAC/LOPR"
:;, ~. EAC/LC'~R"

A~.ixc/co~

e
c
m
::!!

"FADC/B,65'.:, F~L.HL,NRC;LD'
"FADC/A.9,CS::FAL.X.NRC/LD"

NR_p;::,)

P;>

z_,.

::zJ

0
r-

BRO''

~OR:Vl.

"SSNC/LD3, ~A::JC/R1 ,EAC/LDAB,OPLD/LDR.R"

·~.1.:T L/CtF

NC'<Vl.PQ

(")

"BSC/R,SC~. J~~.R.FADC/RO"

"BSC/ID.~,\[;C

NOP

.,,

TRANSFER

MACRO

-n

DEFINITIG~~s

" ;.J/: XC/ LB . E~. L C/A+B,5~XC/#EO,EAC/LDPR"

PR_LB+K
PR_LG-K
PR __ LB-XR
PR_F::i~11,

PR_cR+:.JROM
~R_r•M+XR

"f...MXC/LS. '-'.4:.. C 1 A-E,EMXC/P80,EAC/~DPR 11
~R.EALUC/A-B,EAC;LDPR"
"Al\1XC/ LB.~.'..~.<
"Ar11XC/PR. ];,:,.
'P60,EALUC/A+B,EAC/LDPR"
''A~v:)'.C/PR. l·'",
~~.EALUC/A+O,EAC/LDPR"
"J•fi.XC/ PR. :;;;· .
'X~ 1 EALUC/A+B,EACILDPR"

t.r:.xc; pq. ::.:.1.1. /~BJ,EALLlC/A-B,EAC/LDPR"

PR_FR-K

PP _UtJDi\

"C:AC/L!)PC(,~~

FR_,t;;+LS

~ .. ~C/ LDP ':"I •.•~\,

'.JC/k.3FF"
C/i..B,E~XC/X~.EALUC/A+Bn

LF<F':/LD.Rc:."
"MSC/r.:o"

f;R_';~

RSJ

SJ:.._SA.XGR.SUB
SA_:3A.XCR.SX
SA_SS
S.A._SR

SG.NC/A. S'~r\ 11

"SGNC/ A. !.·:J2. X"
"SGNC/A. '.:; ·
"SGNC/A.C:~S"

sx_sA

"MSC/ LOS~"

wA IT
XR_LA

"WA IT/WA I T ''
"AMXC/LA,EAL..~..:/A,EAC/LDXR"

"BRANCH

MACRO DEFINITIONS"

il.Qq.6).0?

"8EN/5"

CDSY~.c"

DIV.:J:J•,E?

"8EN/6"

ERR:JO?
EX.t'.DIFF?
F'..JAT?
fJ!UL.. COt>;E?
cccciDE?

BE~J/7 II

3EN/5"

11
11

BEt-:/4"
BEN/6"

"BEN/1 ''
II

ZERJES"
POLY.DONE?

BE~/4"

BEN/2"

"BEN/3"

"BEN/4"

~
n

0
z
-I
:::c
0
r
:::c
0

3::
-n
m
r

c
c
m
:!!

z
=t
0z

n
0
z
.::!

CHAPTER 4
CONSOLE

CIB 0-BUS REGISTERS (LOWER)

ID BUS
GBUS
ADDRESS ADDRESS

173000

ROMO

173002

ROM 1

173004

SPARE

ROM 0 DATA <15:0>

ROM 1 DATA <15:0>

ID DATA LO

SPARE

'TIMEOUT
0

ID DATA <15:0>

ID DATA HI

173012

SPARE

173014

RX DONE lo

173016

TX READY lo

IR/0
0

I
I

173010

IR/O
0

I
I

173006

IR/O

ID DATA <31 :16>

ts
SPARE

l~~EI o

l~~vl 0
BASE ADDRESS ON M8236:
Wl INSTALLED - 1730XX
Wl REMOVED - 1630XX

IR/O

TIMEOUT

0
ol R/W
0
olR/W

CIB 0-BUS REGISTERS (UPPER)

ID BUS
ADDRESS

OBUS
ADDRESS
()()

15
(05)

173020

TO ID <15:0>

TO ID LO
15

(05)

TO ID HI

173022

TOID<31·16>

173024

FM ID LO

FM ID <15:0>

R/O

()()

15
(07)

173026

FM ID HI

173030

ID C/S

FMID<31:16>
15

RIW

()()

(07)

RIW

()()

RIO

14
RCV ID ADDRS <5:0>
INVERTED AND READ ONLY

RIW

ID ADD RS <5:0>

RCV
WRITE

0 BUS
ADDRESS
173032

00
RIW

HLT
REO

15
173034

MCA

UPC12

SBC

FREQ
<O->

CLK
STPD

ROM
NOP

()()

MCS

RIW

REMOTE

15
173036

V-BUS

V BUS SER CHNL <7:0>

RIW

CPT
0

CPT

LOAD

EXPLANATION OF VERSION NUMBERS FOR CONSOLE BOOTING

When WCS has been reloaded,
revision status, for example:
VER:

the

console

terminal

PCS=01 WCS=0E-10 FPLA=0E CON=V07-00-L

prints

out

KE780 PRESENT

The PCS code refers to the revision number of the programmed
control store (ROM).
The WCS (writable control store) code
contains two numbers.
The primary version number (in this case,
0E) refers to the FPLA number that is required for this WCS
version.
The secondary version number (in this case, 10) refers
to the version of WCS that has been loaded.
The FPLA (field programmable logic array) code refers to the FPLA
chip revision that is currently installed in the VAX-11/780 CPU.
This chip causes the microprocessor to retrieve microwords from
WCS instead of from PCS when specific locations are addressed.
The CON (console) code refers to the rev1s1on number of
console software that has been loaded into the LSI-11 memory.

the

Two types of mismatch may occur.
If the WCS revision does not
match the FPLA revision, the console program issues a warning.
If
the WCS revision does not match the PCS revision, however, the
mismatch is fatal.

CONSOLE HELP FILE

REV.

VAX·-111780 CONSOLE HELP FI LE
SYNTAX:

March 29,

1982

ALL COMMANDS ARE TERMINATED BY CARRIAGE RETURN.
, EXAMINE, AN[•
'/P'

, DEPOSIT' :·QUAL ... SWITCHES FDR ADDRESS SPACE
PHYSICAL MEMORY <THE DEFAULT>
VIRTUAL MEMORY
'/I'
INTERNAL< PROCESSOR> REGISTERS
'/G'
GENERAL REGISTERS 0 THRU F (RO THRU PC>
'/VB'
VBUS REGISTERS
'/ID'
J[IBUS REGISTERS
'EXAMINE' AND 'DEPOSIT' <GUAL> SWITCHES FOR DATA-LENGTH
'/B'
BYTE <8 BITS>
'/W'
WORD <2 BYTES>
'/L'
LONGWORD <2 WORDS>
'IQ'
= QUADWORD (4 WORDS>
,·ADDR·,. IS A .-:·NUMBER>• OR ONE OF THE FOLLOWING SYMBOLIC ADDRESS
'RO,R1 ,R2,,, •• ,. ,R11 •AP,FP,SP,PC'
<GENERAL REGISTERS>
'PSL'
PROCESSOR STATUS WORD
'*'
LAST ADDRESS
't'
= ADDRESS FOLLOWING 'LAST'<*> ADDRESS
= ADDRESS PRECEEDING 'LAST' ( * > ADDRESS
'@'
'" USES LAST EXAMINE/DEPOSIT DATA FOR ADDRESS
··NUMBER·· = STRING OF [1IGITS IN CURRENT DEFAULT RADIX•
OR ~;H\ING OF DIGITS PREFIXED WITH A DEFAULT RADIX
OVERRIDE o:o FOR OCTAL, 7.X FOR HEX>.

'IV'

=
=

'B(IOT'
'BOOT .,·DEVNAW

'CLEAR STEP'
'CLEAR SOMM'

'CONTINUE.
·DEPOSIH/·:SWlTCH<ES>
·ENABLE Ill(l:'

J <ADDfC··

::DATA.'

'EXAMINE[l<SWITCH<ES>>J <ADDR>
'EXAMINE IR'

'HALT'
··HELP'
'INITIALIZE'
'LINK'

'LOAD[/START: <ADDR> J <FILENAME>'
'LOAD/WCS <FILENAME>·'
'NEXT "NUMBER>'

-BOOTS THE CPU FROM DEFAULT DEVICE
-TAKES THE FrnST THREE ALPHANUMERIC
CHARS OF ...-DEVNAM>, AND EXECUTES THE
INDIRECT FILE '<.DEVNAM>BOO. CMD'
-ENABLE NORMAL (ND STEP> MODE
·-Cl EAR 'srnP ON MICRO-MATCH' ENABLE.
NOTE! ID REGISTER 21 IS THE
MICRO-MATCH REGISTER.
··ISSUES A CONTINUE TO THE ISP
-DEPOSIT <DATA> TO <ADDREss·· ..
-ENABLES CONSOLE SOFTWARE TO ACCESS
FLOPPY DRIVE 1 ON THOSE SYSTEMS WITH
DUAL FLOPPIES.
-DISPLAY CONTENTS OF ·:ADDRESS>
·EXAMINE INSTRUCTION REG<IR>. DISPLAYS
OP-CODE, SPECIFIER, EXECUTION POINT
COUNTER
-HAL TS THE ISP
-PRINTS THIS FILE
-INITIALIZES THE CPU
-CAUSES CONSOLE TO BEGIN COMMAND
LINK I NG, CONSOLE PRINTS REVERSED
PROMPT TO INDICATE LINKING. ALL
COMMANDS TYPED BY USER WHILE LINKING
ARE STORED IN AN INDIRECT COMMAND
FILf FOR l ATfR EXECUTION. CONTROL-·C
TERMINATES LINl\ING. <SEE PERFORM>

-LOAD FILE TO MAIN MEMORY, STARTING AT
ADDRESS 0, OR <ADDR> IF SPEC IF I ED
-LOAD FILE SPECIFIED TO WCS
·<NUMBER.> STEP CYCLES ARE DONE, TYPE

CONSOLE HELP FILE (CONT)

'PERFORM'

'OCLEAR <ADDRESS>'

'REBOOT'
'REPEAT <ANY-CONSOLE-COMMAND>'

'SET
'SET
'SET
,.SET

CLOCK SLOW'
CLOCK FAST'
CLOCK NORMAL'
DEFAULT <OPTION>[,,,,,<OPTIOW,]'

'SET RELOCATION:<NUMBER>'

'SET
'SET
'SET
'SET
'SET

SOMM'
STEP BUS'
STEP INSTRUCTION'
STEP STATE'
TERMINAL FILL:<NUMBER·:,

,.SHOW'
'SHOW VERSION'

'START <ADDRESS:·
'TEST'
'TEST/COM'
'UNJAM'
'WCS'

'WAIT DONE'

'~p' <CONTROL-P)

'@<FILENAME>'

OF STEP DEPENDS ON LAST 'SET STEP'
COMMAND
-EXECUTE A FILE OF LINKED COMMANDS
PREV IOU SLY GENERATED VI A A 'LINK'
COMMAND.
-DOES A QUAD CLEAR TO <ADDRESS>,WHICH
IS FORCED TO A QUAD WORD BOUNDARY,
(CLEARS ECC ERRORS)
-CAUSES A CONSOLE SOFTWARE RELOAD
-CAUSES THE CONSOLE TO REPEATEDLY
EXECUTE THE <CONSOLE-COMMAND>' UNTIL
STOPPED BY A CONTROL-C <~c),
-SET CPU CLOCK FREQ TO SLOW,
-SET CPU CLOCK FREQ TO FAST
-SET CPU CLOCK FREQ TO NORMAL
-SET CONSOLE DEFAULTS
NOTE: <OPTIONS> ARE:
OCTAL, HEX, PHYSICAL, VIRTUAL, INTERNAL
GENERAL, VBUS, I DBUS, BYTE, WORD, LONG, QUAD
·-PUT <NUMBER> INTO CONSOLE RELOCATION
REGISTER. RELOCATION REGISTER IS
ADDED TO EFFECTIVE ADDRESS OF
PHYSICAL AND VIRTUAL EXAMINES AND
DEPOSITS.
--SET 'STOP ON MICRO-MATCH' ENABLE
-ENABLE SINGLE BUS CYCLE CLOCK MODE
·-ENABLES SINGLE INSTRUCTION MODE
--ENABLE SINGLE TIME STATE CLOCK MODE
-SET FILL COUNT FOR t OF BLANKS
WRITTEN TO THE TERMINAL AFTER <CRLF>
-PUT CONSOLE TERMINAL INTO 'PROGRAM
I/O' MODE
-SHOWS CONSOLE AND CPU STATE
-SHOWS VERSIONS OF MICROCODE AND
CONSOLE
-INITIALIZES THE CPU, DEPOS ITS<ADDREss·:,
TO PC, ISSUES A CONTINUE TO THE ISP.
--RUNS MICRO-DIAGNOSTICS
--LOADS MICRO-DIAGNOSTICS, AWAITS
COMMANDS
-UNJAMS THE SB!
-CALLS MICRO-DEBUGGER, WCS MICRODEBUGGER FLOPPY MUST BE INSERTED
IN CS1, ELSE, 'FILE NOT FOUND' ERROR.
<FOR DEBUGGER HELP. INSERT WCS DEBUG
FLOPPY, THEN TYPE '@WCSMON, HLF")
-WHEN EXECUTED FROM AN INDIRECT
COMMAND FILE, THIS COMMAND WILL CAUSE
COMMAND FILE EXECUTION TO STOP UNTIL:
A> A 'DONE' SIGNAL IS RECEIVED FROM
THE PROGRAM RUNNING IN THE VAX
<COMMAND FILE EXECUTION WILL
CONTINUE), QR
B > THE VAX-11 /780 HAL TS, OR OPERATOR TYPES A CONTROL-C ( ~c :
COMMAND FILE EXECUTION WILL
TERMINATE>.
-PUT CONSOLE TERMINAL INTO 'CONSOLE
I/0' MODE
<UNLESS MODE SWITCH IN 'DISABLE'>
-PROCESS AN INDIRECT COMMAND FILE

CONSOLE ABBREVIATION RULES

VAX--l l /780 CONSOLE ABBREV I AT ION RLJl_ES
REV- 6
12--APR·-79
THIS FILE SHOWS THE SHORTEST UNIQUE COMMAND AND QUALIFIER STRINGS.
COMMAND
'BOOT'
'CLE1~R

SDMM'
'CLEAR STEF''
'CIJNTINLJE'
'DEPOSIT
ADDRESS"· :DATA:·
'ENABLE DXl:'
'EXAMINE ::ADDRESS ..
'HALT'
'HELF''
'INITIALIZE'
'LINK'
'LOAD <FILENAME·'
'NEXT '·NUMBER.>'
·PERFORM'
'QCL EAR <ADDRESS::'
'REBOOT'
'REPEAT
CONSOLE-COMMAND·
'SET CLOCK FAST'
'SET CLOCK SLOW'
'SET CLOCK NORMAL'
'SET RELOCATION! ·"NUMBER>
'SET SOHM'
'SET STEP BUS'
'SET STEP STATE'
'SET STEP INSTRUCTION'
'SEl TERMINAL FILL: <NUMBER>'
'SEl TERMINAL PROGRAM'
'SET DEFAULT <OPTION-LIST>'
'SHOW'
'SHOW VERSION'
'ST Mn <.ADDRESS:·,.'
'TEST'
'UNJAM'
'WAIT DONE'
'WCS'
'@<F ILENAML''
QUALIFIERS
/BYTE
/WORD
/LONG
/QUAD
/OCTAL
/HEX
/PHYSICAL
/VIRTUAL
/INTERNAL
/GENERAL
/VBUS
/IDBUS
/WCS
/NEXT: <NUMBER'·
/COMMAND
/START: <ADDREss·-.

SHORTEST ABBREVIATION RECOGNIZED
'B'
'CL SO'
'CL S'
'C,
'D ·'ADDRESS".. <DATA>'
'EN DXl:'
'E : ADDRESS:
'H'
'HE'

, I,

'LI'
'L .,:FILENAME'>'
'N -CNIJMBER>'

'P'
'Q <ADDRESS>'
'REB'
'R <CONSOLE-COMMAND>'
'SE C F'
'SE C S'
'SE C N'
'SE R: <NUMBER ..
'SE SO'
'SE S B'
'SE S S'
'SE
I'
'SE
F: :NUMBER>'
'SE
PR'
'SE D ,·OPTION-LIST>'
'SH'
'SH V'
'S ·:ADDRESS",

'T'
'U'
'WA D'
'W'
'@<FILENAME'>'
SHORTEST ABBREVIATION RECOGNIZED
/B
/W
/L
IQ
10
/H

/P
/V
II

IG
/VB
/ID
/WC

IN: <NUMBER>
/C
/S: ·:·ADDRESS>

ERROR MESSAGE HELP FILE

VAX-111780 ERROR MESSAGE HELP FILE
REV-4
12-AR-79
THIS FILE LISTS ALL THE POSSIBLE CONSOLE ERROR MESSAGES, INDICATING
CAUSE, AND POSS IBLE CORRECTIVE PROCEDURES CIF NOT SELF-EXPLANATORY)
SYNTACTIC ERRORS :
?'<TEXT-STRING>' IS INCOMPLETE

THE <TEXT-STRING> IS NOT A COMPLETE
CONSOLE COMMAND

? '<TEXT-STRING>' IS INCORRECT

THE <TEXT-STRING> IS NOT RECOGNIZED
AS A VALI[I COMMAND

?FILE NAME ERR

A <FILE-NAME> GIVEN WITH A COMMAND
CAN NOT BE TRANSLATED TO RAD50,
<<FILE-NAME> IS INVALID,)

?IND-COM ERR

THE CONSOLE DETECTED AN ERROR IN THE
FORMAT OF AN INDIRECT COMMAND FILE.
POSSIBLE ERRORS ARE: 1) MORE THAN 80
CHARACTERS IN AN INDIRECT COMMAND LINE
OR 2) A COMMAND LINE nm NOT END
WITH A CARRIGE RETURN AND LINE FEED.

COMMAND-GENERATED ERRORS :
?FILE NOT FOUND

A <FILE-NAME> GIVEN WITH A 'LOAD'
OR '@' COMMAND DOES NOT MATCH ANY
FILE ON THE CURRENTLY LOADED FLOPPY
DISC, CAN ALSO BE GENERATED BY
'HELP',' BOOT', OR AN ATTEMPTED WCS
LOAD IF HELP FILE, BOOT FILE, OR WCS
FILE IS MISSING FROM FLOPPY,

?NO CPU RESPONSE

CONSOLE TIMED-OUT WAITING FOR A
RESPONSE FROM CPU. CRETRY. INDICATES
POSSIBLE CPU-RELATED HARDWARE FAULT.>

?CPU NOT IN CONSOLE WAIT LOOP,
COMMAND ABORTED

A CONSOLE COMMAND REQUIRING ASSISTANCE
FROM THE CPU WAS ISSUED WHILE THE CPU
WAS NOT IN THE CONSOLE SERVICE LOOP.
CHAL T CPU; RE-ISSUE COMMAND.)

?CPU CLK STOP, COMMAND ABORTED

A CONSOLE COMMAND THAT REQUIRES THE
CPU CLOCK TO BE RUNNING WAS ISSUED
WHILE THE CLOCK WAS STOPPED.
(CLEAR STEP MODE; RE-ISSUE COMMAND.)

?CANT DISABLE BOTH FLOPPIES,
FUNCTION ABORTED

AN ATTEMPT WAS MADE TO DISABLE BOTH
THE REMOTE AND LOCAL FLOPPY.

FLOPPY-GENERATED ERRORS :
?FLOPPY ERR, CO[IE=X

THE CONSOLE FLOPPY DRIVER DETECTED
AN ERROR, CODES ARE AS FOLLOWS:
<CODES ALWAYS PRINTED IN HEX RADIX>
CODE=l
FLOPPY HARDWARE ERROR
<CRC •PARITY, ETC>
CODE=2 FILE NOT FOUND
CODE=3 FLOPPY DRIVER QUEUE OVERFLOW
CODE=4 CONSOLE SOFTWARE REQUESTED
AN ILLEGAL SECTOR NUMBER

ERROR MESSAGE HELP Fl LE (CONT)

'>FLOPPY NOT READY

THE CONSOLE FLOPPY DRIVE FAILED TO
BECOME READY WHEN BOOT I NG. <RETRY, )

'>NO BOOT ON FLOPPY

CONSOLE ATTEMPTED TO BOOT FROM A
FLOPPY THAT DOES NOT CONTAIN A VALID
EcOOT BLOCK. <CHANGE FLOPPY DISK.)

'>FLOPPY ERROR ON BOOT

A FLOPPY ERROR WAS DETECTED WHILE
ATTEMPTING A CONSOLE BOOT. <RETRY l

MICRO-ROUTINE ERRORS :
'>MIC-ERR ON FUNCTION

A MICRO-ERROR OCCURRED IN THE CPU
WHILE SERVICING A CONSOLE REQUEST.
SBI ERROR REGISTERS ARE DUMPED AFTER
THIS MESSAGE IS PRINTED.
<ACTION DEPENDANT ON ERROR.>

?INT-REG ERR

A MICRO-ERROR OCCURRED WHILE ATTEMPTING TO REFERENCE A CPU INTERNAL
<PROCESSOR l REGISTER, AN ILLEGAL
ADDRESS WILL CAUSE THIS ERROR.

'>MICRO-ERRr CODE=X

AN UNRECOGNIZED MICRO-ERROR OCCURRED.
THE CODE RETURNED BY THE CPU IS NOT IN
THE RANGE OF RECOGNIZED ERROR CODES.
'X' IS THE CODE THAT WAS RETURNED BY
THE CPU.

'>MEM--MAN FAULT, CODE=XX

A VIRTUAL EXAMINE OR DEPOSIT CAUSED
AN ERROR IN THE MEMORY MANAGEMENT
MICRO-ROUTINE, 'XX' IS A ONE BYTE
ERROR CODE RETURNED BY THE ROUTINE,
WITH THE FOLLOWING BIT ASSIGNMENTS:
BIT 0
LENGTH VIOLATION<BITS NUMBERED
FROM RIGHT>
BIT 1 = FAULT WAS ON A PTE REFERENCE
BIT 2 = WRITE OR MODIFY INTENT
BIT 3 = ACCESS VIOLATION
BITS 4 THRU 7 SHOULD BE IGNORED

CPU FAULT-GENERATED ERRORS :
'>INT-STK INVLD

THE CPU HAL TED BECAUSE THE INTERRUPT
STACK WAS MARKED INVALID.

'>CPU DBLE-ERR HL T

A MACHINE CHECK OCCURRED BEFORE A
PREVIOUS MACHINE CHECK HAD BEEN
HANDLEDr CAUSING THE CPU TO EXECUTE
A 'DOUBLE ERROR' HALT. <EXAM I NE ID REG
30-3F <HEX>; DATA INDICATES CAUSE OF
MACHINE CHECK • )

'>ILL I /E VEC

THE CPU DETECTED AN ILLEGAL INTERRUPT I
EXCEPTION VECTOR.

?NO USR WCS

CPU DETECTED AN INTERRUPT /EXCEPT ION
VECTOR TO USER WCS AND NO USER WCS
EXISTS.

'>CHM ERR

A CHANGE MODE INSTRUCTION WAS ATTEMPTED FROM THE INTERRUPT STACK,

ERROR MESSAGE HELP FILE (CONT)

INT PENBING

THIS IS NOT ACTUALLY AN ERROR, BUT
INBICATES THAT AN ERROR WAS PENBING
AT THE TIHE THAT A CONSOLE-REQUESTE[I
HALT WAS PERFORHE[I, CONTINUE CPU TO
CLEAR INTERRUPT.

?HICRO-HACHINE TIHE OUT

INBICATES THAT THE VAX-11/780 HICROHACHINE HAS FAILE[I TO STROBE INTERRUPTS WITHIN THE HAXIHUH TIHE PERIO[I
ALLOWED.

VERSION HISHATCH ERRORS :
?WARNING-WCS & FPLA VER HISHATCH

THE HICROCODE IN WCS IS NOT COHPATIBLE
WITH THE FPLA, THIS HESSAGE IS PRINTED
ON EACH ISP START OR CONTINUE, BUT NO
OTHER ACTION TAKEN BY CONSOLE.

'?FATAL-WCS & PCS VER HISHATCH

THE HICROCO[IE IN PCS IS NOT COHPATIBLE
WITH THAT IN WCS. ISP START AN[I CONTINUE ARE BI SABLED BY CONSOLE.

?REHOTE ACCESS NOT SUPPORTED

PRINTE[I WHEN CONSOLE HO[IE SWITCH
ENTERS A 'REHOTE' POSITION, AN[I THE
REHOTE SUPPORT SOFTWARE ROUTINES ARE
NOT INCLU[IE[I IN THE CONSOLE,

CONSOLE-GENERATED ERRORS :
THE CONSOLE TOOK A TIHE-OUT TRAP.
CONSOLE WILL RESTART.

"TRAP-4, RESTARTING CONSOLE
?UNEXPECTE[I TRAP
HOUNT CONSOLE FLOPPY, THEN TYPE
?Q-BLK[I'

~c !

CONSOLE TRAPPED TO AN UNUSE[I VECTOR.
CONSOLE REBOOTS WHEN ~c TYPED.
CONSOLE' S TERHINAL OUTPUT QUEUE IS
BLOCKE[I, CONSOLE WILL REBOOT.

CONSOLE REMOTE ACCESS HELP FILE

\JAX· 11 /780 CONSOLE

REMOTE ACCESS HELF' FI LE REV-02 26-JUL--78

'ENABLE TALK'

-ESTABLISH TERMINAL TO TERMINAL COMMUN I CAT ION
BETWEEN LOCAL ANfl REMOTE TERMINAL. KEYS
STRUCK ON ONE TERMINAL ARE F'RINTED ON THE
OTHER. CONTROL-F' TERMINATES TALK.
'ENABLE. ECHO'
-CAUSES CHARAC fERS TYF'ED IN TALK MODE TO BE
ECHOED BACK TO THE ORIGINATING TERMINAL.
'ENABLE_ LOCAL COPY'
--CAUSES THE LOCAL TERMINAL TO GET A COPY OF
OF OUTPUT BEING SENT TO REMOTE TERMINAL.
'ENABLE LOCAL CONTROL '-ALLOWS LOCAL TERMINAL TO CONTROL. SYSTEM WHEN
CONSOLE SWITCH IS IN REMOTE POSITION(S). DISABLED BY A CONTROL --P FROM THE REMOTE TERMINAL.
'ENABLE CARRIER tRROR '-CAUSE CONSOLE TO PRINT '?CARRIER LOST' WHEN A
LOSS OF CARRIER IS DETECTED AT REMOTE INTERFACE,
'DISABLE ECHO'
-INHIBITS ECHO OF CHARACTERS TYPED IN TALK MODE.
'flISABLE LOCAL COPY'
-DISABLE LOCAL TERMINAL FROM RECEIVING COPY OF
OUTPUT TO RE.MOTE TERMINAL.
'DISABLE CARRIER ERROR'-CAUSES CONSOLE TO INHIBIT PRINTING OF CARRIER
LOST MESSAGE WHEN LOSS OF CARRIER DETECTED.
, ENABLE LOCAL FLOPF'Y,
- (AF FEC rs PRO rocoL OPERATION ONLY) ON AN ATTEMPT
TO OPEN A FILE, THE DIRECTORY OF LOCAL FLOPPY
WILL BE SEARCHED FIRST. IF FILE IS NOT FOUND,
'REMOTE' FLOF'F'Y'S DIRECTORY IS SEARCHED FOR FILE.
'[I I SABLE LOCAL FLOF'PY ' - (AFFECTS PROTOCOL OP ER AT ION ONLY) ON AN ATTEMPT
TO OPEN A FILE• THE FILE IS SEARCHED FOR ON
THE 'REMOTE' FLOPPY ONLY.
'DISABLE REMOTE FLOPF'Y '--ON AN ATTEMPT TO OPEN A FILE, ONLY THE DIRECTORY
OF THE LOCAL FLOPPY WILL BE SEARCHED.
THIS COMMAND
ANfl 'DI SABLE LOCAL FLOF'PY' ARE MU TUA LL Y EX CL US I VE.
'ENABLE REMOTE FL.O~'F'Y' ··ALLOWS THE fl lRECTORY OF THE 'REMOTE' FLOPPY TO BE
SEARCHED ON AN ATTEMPT TO OPEN A FILE.

MICRODEBUGGER HELP FILE

MICRO-DEBUGGER HELP FILE

REV 2.0, APril 13• 1982

DEBUGGER COMMANDS <ALL TERMINATED BY CARRIAGE RETURN>
'E/P <ADDRESS>'

-EXAMINE PHYSICAL MEMORY

'E/ID <ADDRESS>'

-EXAMINE ID BUS REGISTER

'E <ADDRESS>'

-EXAMINE WCS LOCATION, DISPLAY ALL FIELDS

'E <ADDRESS> <FIELDNAME-1> ,.,SIELDNAME-D·,,, •<FIELDNAME-N>
EXAMINE WCS LOCATION, DISPLAY ONLY FIELDS
THE FIELDS SPECIFIED.
NOTE: <FIELDNAMES>
ACF, ACM, ADS, ALU, BEN, BMX, CCK, CID· DK, DT, EAL
EBM,FEK' FS' IBC, IEK, UJM ,KMX ,MCT, MSC, PCK, OK
RMX, SCK, SGN, SHF, SI, SMX, SPO, USU, VAK
'E RA <ADDRESS>'

-EXAMINE AN RA REGISTER

'E RC <ADDRESS>'

-EXAMINE AN RC REGISTER

'E <SYMBOLIC-NAME>'

-EXAMINE ONE OF THE SYMBOLICALLY NAMED
REGISTERS
DR, FER, IBA, LA, LB, LC ,Q, RL, SC, SR, UPC

NOTE: <SYMBOLIC-NAMES>

'D/P <ADDRESS> <DATA>' -DEPOSIT <DATA> TO PHYSICAL MEMORY
'[I/ID <ADDRESS> <DATA>'

-DEPOSIT <DATA> TO ID BUS REGSITER

'D <ADDRESS> <FIELDNAME-L> <DATA-L" <FIELDNAME-2> <DATA-2>,, • , • , •• ,
-DEPOSIT TO WCS LOCATION, PUTTING <DATA--1>
INTO <FIELDNAME-L" ETC. UNSPECIFIED FIELDS
ARE UNCHANGED,
NOTE: THE 'IZ' QUALIFIER MAY BE USED TO CAUSE ALL UNSPECIFIED
FIELDS TO BE CLEARED.
'[I RA <ADDRESS> <DATA>'

-DEPOSIT <DATA> TO AN RA REGISTER

'D RC <ADDRESS> <DATA>'

-DEPOSIT <DATA> TO AN RC REGISTER

'D <SYMBOLIC-NAME·,. <DATM

-DEPOSIT <DATA> TO ONE OF THE SYMBOLICALLY
NAMED REGISTERS<SEE LIST ABOVE).
NOTE: DEPOSITS TO THE RLOG STACK <RL> ARE NOT SUPPORTED,

'CONTINUE'
'START <ADDRESS>'
'HALT'

-RESUME MICRO-INSTRUCTION EXECUTION AS
SPECIFIED BY CONTENTS OF MICRO-PC <UPC>
-START MICRO-SEQUENCER AT <ADDRESS>,
-HALT THE MICRO-SEQUENCER

'SET SOMM'

-SET THE 'STOP ON MICRO-MATCH' ENABLE

'CLEAR SOMM'

-CLEAR THE 'STOP ON MICRO-MATCH' ENABLE

'SET STEP'

-ENABLE SINGLE MICRO-INSTRUCTION STEP MODE.
START OR CONTINUE WILL ALLOW ONE MICRO-INSTRUCTION TO EXECUTE, THEN HALT THE
MICRO-SEQUENCER.

'CLEAR STEP'

-DISABLE SINGLE MICRO-INSTRUCTION STEP MODE,

MICRODEBUGGER HELP FILE (CONT)

'OPEN

FILENAME

-OPEN SPECIFIED FILE ON FLOPPY DRIVE 0

'OPEN DXl :<FILENAME
-OPEN SPECIFIED FILE ON FLOPPY DRIVE 1
NOTE:
'OPEN' IS USED TO SPECIFY A FILE CONTAINTNG THE MICRO-CODE
CURRENTLY LOADED IN THE IJCS PORT ION OF THE CONTROL SI ORE,
<ADDRESSES 1000<16) & UP IN THE CONTROL STORE)
THIS FILE IJILL BE USED FOR ALL EXAMINES OF THE IJCS,
SINCE THE IJCS IS NOT DIRECTLY READABLE,
'RETURN'

-RETURN TO THE CONSOLE PROGRAM,

+------------------·-------------------------+
[10 NOT USE THE RETURN COMMAND
UNLESS THE CONSOLE FLOPPY IS IN CS1,

+--- - --- - -------- - -- -- - - ---- - -- - -- -- ·- - - -· --- -+
'
I

TO RETURN TO THE CONSOLE PROGRAM, REMOVE
THE IJCS DEBUG FLOPPY, INSERT THE CONSOLE
FLOPPY, THEN TYPE 'RETURN <CR>',

'
I

+--------------------------·-------------·-·--+

LSl-11 CONSOLE ODT COMMANDS

Format

Description

RETURN

Close opened location and accept next command.

LINE FEED

Close current location;
location.

Open previous location.

or -

Take contents of
opened location
location.

open next sequential

opened location, index by
plus 2, and open that

Take contents of opened location as
absolute address and open that location.
r/

Open location r.

Open last location.

Sn or Rn

Open general
register).

r; G or rG

Go to location
start program.

Execute bootstrap loader using n as device CSR
address.

(0-7)

initialize

the

(PS

bus,

and

;P or P

Proceed with program execution.

RUBOUT or
DELete

Erase previous character.
Response is a
backslash \ (134) each time RUBOUT is entered.

Maintenance.
Display of an internal CPU
register follows the M command. Only the last
digit displayed is significant, indicating how
the CPU entered the Halt (ODT) mode, as
follows:
Last
Digit

Halt Source

0 or 4

HALT instruction
signal asserted.

1 or 5

Bus error occurred while getting
device interrupt vector.

BHALT

L bus

LSl-11 CONSOLE ODT COMMANDS (CONT)

Last
Digit
2 or 6

Halt Source
Bus error occurred
memory refresh.

while

doing

Double bus error occurred (stack was
nonexistent value).
Reserved instruction trap occurred
(nonexistent
micro-PC
address
occurred on internal CPU bus).
7

CTRL-SHIFT-S

A combination
occurred.

and

For manufacturing tests only.
Escape this
command function by typing NULL and @ (000 and
HHl).

CONSOLE SUBSYSTEM CONFIGURATION

IDBUS~---

- - - - - • CLOCK CONTROL

V BUS

MICROSEQUENCER

CONSOLE/CPU
INTERFACE

:--;,( __ _
I

CONTROL
PANEL

ROM

Q-BUS

LSl-11

4KMEM

RXV11
FLOPPY
CONTROLLER

DLV-11

DLV-11
(OPT)

RX01

TERMINAL

EIA CONNECTION
FOR REMOTE
TERMINAL

TK-0192

JUMPER
W1

W2
W3
W4
W5
W6
W7&W8

W9
W10
W11

IN/OUT

RESULT
RESIDENT MEMORY AT A BANK 0
RESIDENT MEMORY AT A BANK 0
LTC INTERRUPT ENABLED
MEMORY REFRESH ENABLED
POWER UP AT 173000
POWER UP AT 173000
PRECONFIGURED*
ENABLE REPLY FROM RESIDENT MEMORY
DISABLE REPLY FROM RESIDENT MEMORY DURING REFRESH
ENABLE ON BOARD MEMORY SELECT

--.",,
c

c
c

rm
c...

.,,

m
::D
(")

.,,

*W7

r-------1---w1
r-------1---W2

r-------1---w11

::D

:::!
0
2

W5
W6

W9
M7264 ETCH REV. E (AND LATER )
*FACTORY CONFIGURED DO NOT CHANGE (W7 & W8)
TK-0700

MSV-118 MODULE JUMPER CONFIGURATION

JUMPER

IN/OUT

RESULT

MEMORY BANK
SELECT 1

W2
W3
W4

(20000-37776)
ENABLES BRPL Y
DURING REFRESH

W2
W1

TK-0702

101

Backpanel

M9400-YE
BCOSL-10

eg
0

Jl------------------J8
Red Stripe
Left, Smooth

Red Stripe
Down, Ribbed

BCOSL-10
Side Up

(')

Side to Backpanel

J2------------------J7

2
2

(')

j
0
2

(I)

Configuration of RXV-11
Should be preconfigured for:
Address: 177170-177172
Vector: 264
Ribbon cable should be installed with
red stripe toward center of module.

(M7946)

DLV11 JUMPER CONFIGURATION

JUMPER

RESULT

IN/OUT

NP
2SB
NB2
NBl
PEV
FEH
EIA
FR3
FR2

NO PARITY
1 STOP BIT
B DATA BITS
B DATA BITS
DON'T CARE PARITY EVEN/ODD
NO HALT ON FRAMING ERROR
NO EIA OPERATION
SELECTS 300 BAUD
SELECTS 300 BAUD
SELECTS 300 BAUD
20 MA ACTIVE XMIT. & RECEIVE

FRl
CL4-CLO

VECTOR JUMPERS SET TO 60-64
V7=1, V6=1, V5=-, V4=1, V3=1
ADDRESS JUMPERS SET TO 177560-177566
A12=-, Al 1=-, A10=-, A9=-, AB=-,
A7=1, A6=-, A5=-, A4=-, A3=1

CL 1

CL2

CL3

CL4

FRO

TPl

FRl

FR2

FR3
TP2

PEV
V3
NBl
NB2
2SB

FEH

V6
V5

A12

All

A4
A5

AlO
TK-0701

103

DLV11-E JUMPER CONFIGURATION

DLV llE
R3 R2 R1 RO
I

T3 T2 T1 TO
I

A 12 A 11 A 10 A9 AB A 7 A6 A5 A4 A3
I

VB V7 V6 V5 V4 V3
-

1 2 P -E PB BG C C1
------11
S S1 H -B B -FR -FD RS
- -

I -

FB M M1

['--------/) ii iif

FB
RS
SI

-FR

-FD

-E

V3-B

m=I

-B
H

M~I

A3-12

104

0-BUS SIGNAL DESCRIPTION

1/0 Transfer Control Signals
Name

Description

BSYNC L

Synchronize - The bus master (LSI- I I processor) asserts BSYNC L to indicate that it has placed an address on BOAL < 15:00> L. The transfer is in
progress until BSYNC L is negated.

BOIN L

Data Input - The LSI-I I asserts BOIN L for two types of operations:

BDOUT L

When it is asserted during BSYNC L time, BOIN L
specifies an input transfer with respect to the processor. It requires BRPL Y L as a response. The processor asserts BOIN L when it is ready to accept data
from the slave device.

When the processor asserts BOIN L without BSYNC
L, it is requesting an interrupt vector from an interrupting device.

Data Output - When the LSI-I I processor asserts BDOUT L, valid data is
on the bus for an output transfer from the processor to an 1/0 slave device.
The slave device deskews BDOUT L (pauses) before latching the data. The
slave device responding to the BDOUT L signal must assert BRPL Y L to
complete the transfer.

105

0-BUS SIGNAL DESCRIPTION (CONT)

I/O Transfer Control Signals
Name

Description

BWTBT L

Write/Byte - The LSI-I I processor uses BWTBT L to control bus cycles in
two ways:

BRPLY L

The processor asserts BWTBT L on the leading edge
of BSYNC L to indicate that an output sequence
(DATO or DATOB) is to follow.

The processor asserts BWTBT L together with
BDOUT L, on a DATOB cycle. for byte addressing.

Reply - A slave device asserts BRPL Y L in response to BOIN L and
BDOUT Lon data transfers and in response to BIAKO L during interrupt
transfers. BRPL Y indicates that the slave has asserted input data on the bus,
accepted output data from the bus, or asserted an interrupt vector on the
bus.

Interrupt Control Signals
BIRQ L

BIAKO L
and BIAKI L

Interrupt Request - A device asserts this signal when its interrupt enable and
interrupt request flip-flops are set. BIRQ L informs the processor that a
device has data to send to the processor (input) or that the device is ready to
accept output data from the processor. If the processor's PS word bit 7 is 0.
the processor responds by acknowledging the request, asserting BOIN Land
BIAKO L.
Interrupt Acknowledge Output and Interrupt Acknowledge Input - The processor asserts this signal in response to an interrupt request (BIRQ L). The
processor asserts BIAKO L which is routed via the Q bus to the BIAKI L pin
of the first device on the bus. If this device is requesting an interrupt (asserting BIRQ L), it will block the passing of BIAKO L to the next device and
then place the interrupt vector on the bus. At the same time the device will
negate BIRQ Land assert BRPL Y L. If the device is not asserting BIRQ L, it
passes BIAKI L to the next device via its own BIAKO L pin and the BIAKI
L pin of the lower priority device.

Address and Data Signals
BOAL < 15:00> L

These 16 lines form the data/address path. Address information is first
placed on the bus by the bus master (processor). The processor then either
re~eive~ input data from or transmits output data to the addressed slave
device or memory location over the same 16 bus lines.

BBS7 L

Bank 7 Select - The bus master asserts BBS7 L when an address in the upper
4K bank (address in the 28K-32K range) is placed on the bus. BSYNC L is
then asserted, and BBS7 L remains active for the duration of the addressing
portion of the bus cycle.

106

0-BUS SIGNAL DESCRIPTION (CONT)

Initialization, Power Fail Signals
Name

Description

BPOK H

Power OK - The power supply asserts this signal when primary power is
normal. If BPOK H is negated during processor operation, the processor
initiates a power fail trap sequence.

BDCOK H

DC Power OK - The power supply asserts this signal when there is sufficient
de voltage available to sustain reliable system operation.

BINIT L

Initialize - The processor asserts BINIT L to initialize or clear all devices
connected to the Q bus. The signal is generated in response to a power up
condition (the negated condition of BDCOK H).
Halt and Refresh Signals

BHALT L

Processor Halt - When BHAL T L is asserted, the processor responds by
halting normal program execution. External interrupts are ignored, but
memory refresh interrupts are enabled if W4 on the processor module is
removed. When the processor is in the halt state, it executes the ODT microcode, invoking console device (terminal) operation.

BREF L

Memory Refresh - This signal can be asserted by a processor microcodegenerated refresh interrupt sequence (when enabled) or by an external device.
BREF L forces all dynamic MOS memory units to be activated for each
BSYNC L/BDIN L bus transaction.

107

CONSOLE BOOT/TROUBLESHOOTING FLOW

If the console program does not start and run properly when the
VAX-11/780 system is powered up, and a problem in the console
subsystem is suspected, proceed as follows.
Response

Action
Turn
Turn
Push
down

de off.
ac off.
HALT/ENABLE switch
(HALT).

Turn ac on.
DC ON (LED on LSI-11 control panel)
173000
@ (printed on terminal)
RUN (light flashes)

Turn de on.

If the responses are incorrect, go to the Console DC ON Flowchart.
Examine location 173000
(type 17 3000/) •

173000/000137

Examine location 037776
(type 037776/).

037776/XXXXXX

If the response
Flowchart.

not

correct,

the

Examine

173000

Push HALT/ENABLE switch
up (ENABLE) •
Ensure that diskette ZZ-ESZAB
is installed properly in the
floppy disk drive.
Type 140200G.

BOOT

This command executes the ROM resident quick check console
subsystem diagnostics.
On successful completion of these tests,
the ROM code boots the console program from the floppy disk.
If
the boot fails, go to the 140200G Console Boot Failure Flowchart.
The program listing for the ROM resident diagnostics (ESKAA.DOC)
should be referenced when using this flowchart.

108

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)

CONSOLE DC ON FLOWCHART
DC ON, RUN LIGHT FLASH,
AND/OR 173000 PRINTOUT DID NOT OCCUR
@.WAS PRINTED
CPU JUMPER IS WRONG OR CPU IS BAD

PRINTOUT GARBLED. CHECK BDALO
ASSERTED ANO GO TO TERMINAL FLOW

NO. GO TO POWER FLOW

IS DC ON LED ONI

rBoMR L
BREF L
BSACK L

:~~~T LL

YES WHAT WAS

ONE OF THE FOLLOWING
SIGNALS IS ASSERTED

BOIN L

PRINTED?

[

BSYNC l

~~;~~~NTED

YES. 010 THE
RUN LIGHT FLASH?

BPOK H IS NOT ASSERTED

BOMG o L
\..BOAL 1 L

LGO TO TERMINAL FLOW
NO. REMOVE M9400-YE. DOES

NO. CHECK POWER SUPPLY TO
BACKPLANE CABLE

~~Nl~I~~~ ON? ;.:;TE::.;;RM:::.;l"'NA.:.:.L.:..;PR:::.;IN.:..:.T_;.1:..:73:::.:000=0Nc:_P:.,::Oc:..:W.::,:ER:..,:U:.;..Pl:___---1i,::~:::.:~S:::,;R::.:H~!:!~;:_B_D_co_K_H_N_OT-NO. CPU IS BAO
YES. CABLING IS INCORRECT
YES. THE HALT SWITCH IS
NOT ASSERTING BHALT L

YES. WAS

YES. CPU IS BAO

PROMPT PAINTED?
NO. REMOVE M9400-YE
POWER UP. DID
PRINTOUT OCCUR?

YES. CIB IS BAD

YES. CABLING OR CIB IS BAO
NO. CHECK JUMPER
CONFIGURATION AGAINST
KC7BO PRINT SET

NOBOAL7 l. BOAL 15 l
BINIT LOR BDMGO L
IS ASSERTED

EXAMINE 173000 FLOWCHART
LOCATION 173000 OR LOCATION 037776
DID NOT RESPOND CORRECTLY
RESPONSE

INTERPRETATION

173000/1

1 THE CABLES ARE NOT CORRECTLY MOUNTED.

I OR THE CIB IS NOT WORKING

I THERE IS A BAUD RA TE PROBLEM BETWEEN THE
I TERMINAL AND THE OLV11 INTERFACE

GARBLED RESPONSE

I
I

WHAT WAS RESPONSE?

I
NO RESPONSE

03777611
{!.

~~E~!E1 ~e"R~~~=~~~~:;~~~~l ~j;~~l~:e~MINAL TO

: THE TOP OF MEMORY BANK 1 DOES NOT RESPOND
I CHECK JUMPER CONFIGURATION AGAINST KC780
PRINT SET

109

OLV11 I

DEVICE DID NOT BOOT WHEN 140200 WAS TYPED

'141236
(tj,"

'140332
(<!,"

OR 141262
@"
"141076
TO@"

R2 CONTAINS FAILING ADDRESS
R3 CONTAINS EXPECTED DATA

VERIFY THAT REFRESH
IS WORKING CORRECTLY AT
FAILING LOCATION

THE CPU TEST FAILED.
REPLACE THE CPU

WORKING.

REPLACE FAILING
MEMORY (NOTE
CPU MAY BE BAO)

NOT CLOSED.

"FLOPPY ERROR'

NOTHING PRINTED

HALT CPU,
WHAT WAS PRINTED

WHAT WAS PRINTED'

CORRECT PROBLEM

NO, THE DRIVE IS BROKEN, RUN DZRXA AND DZRXB DIAGNOSTICS

NOTHING PRINTED

"000104
(tj,"

"140216
@'

"000002
@"

{:,~"'

(I)

z
en

.-0m

0
0

DOES ITJ
BOOT>

THE FLOPPY CAME READY.
BUT DID NOT READ
A BLOCK

g
0

CHECK
CONFIGURATION

YES. THE FIRST DISKETTE IS EITHER BAD OR THE WRONG ONE
TRY ANOTHER
"NO BOOT ON VOLUME" DISKETTE.

n
NOT WORKING.

J
1

(")

CLOSED. THE DRIVE IS BROKEN. RUN DZRXA AND DZRXB DIAGNOSTICS
VERIFY THAT FLOPPY
DOOR IS CLOSED

"FLOPPY NOT READY"

...

BAD CPU

BAD CPU
OR BAD CIB

SEE LISTINGS IESKAA DOC)
XXXXXX = CURRENT LOCATION + 2

THE LTC SWITCH IS ON.
OR BEVNT LIS NOT CLAMPED LOW BY THE LTC SWITCH

BHALT LIS STILL ASSERTED
OR BOAL 9L OR BOAL 10 IS ASSERTED

.,,

-I

!!
.-

,,cm

.,,
in
.~

,,
)>

-I

0
r

m
co
0
0

-I
-I

:c
0
c

co
m
(I)
:::c
r

0
0

:::!
z

.,,G')

r
0

n0
z

::t
"173000
@;"

A DOUBLE BUS ERROR HAS OCCURRED. SET R6 TO
1000. TYPE 173000G. AND THEN REENTER THIS TROUBLESHOOTING PROCEDURE

'XXXXXX

BAD CPU
OR CIB

0:·

SEE LISTINGS IESKAA DOC), XXXXXX = CURRENT LOCATION + 2

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)

CONSOLE POWER TROUBLESHOOTING FLOWCHART
CONSOLE DC POWER FAILURE
NO. CORRECT THE FAULT
IS AC PRESENT
AT POWER SUPPLY?

YES. ONE MODULE IS SHORTING DC. REPLACE
MODULES UNTIL THE BAD ONE IS LOCATED
NO. CORRECT THE FAULT

YES. IS THE BOX WIRED
CORRECTLY FOR AC?
YES. REMOVE THE MODULES
FROM THE BOX IS DC ON?

YES. BAD POWER SUPPLY
NO, ARE VOLTAGES
CORRECT AT
BACKPLANE?

YES, DISCONNECT THE POWER
SUPPLY-TO- BACKPLANE

YES. BAD BACKPLANE

CABLES IS DC PRESENT>
ARE CABLES CONNECTED FROM POWER
SUPPLY TO FRONT PANEL AND BACKPLANE?

NO. BAD POWER SUPPLY

NO. CORRECT THE FAULT

CONSOLE TERMINAL TROUBLESHOOTING FLOWCHART
CONSOLE TERMINAL FAILURE
NOT
REMOVE DLV11
COMPATIBLE. CORRECT FAULT
AND ENSURE THAT
BAUD RATE IS
COMPATIBLE WITH LA36
NO. REPAIR TERMINAL
_ _ _ _ _ ___,COMPATIBLE
WILL TERMINAL
WORK IN LOCAL?

YES. IS TERMINAL 20MA CURRENT LOOP?

NO IEIAI.
WHILE CYCLING DC ON
IS THERE ACTIVITY ON
THE DLV11 BERG PIN f?

NO. BAD TERMINAL
OR CABLE
YES. WHILE PRESSING A KEY ON THE TERMINAL
IS THERE ACTIVITY ON THE CABLE PIN Ml
YES. BAD TERMINAL.
FORMAT BUAD RATE
NO. BAD DLV11

YES. WHILE CYCLING DC ON
IS THERE ACTIVITY ON
THE WHITE WIRE?

NO. BAD DLV11 OR CABLE LOOP
NO. REPAIR TERMINAL
OR CABLE LOOP

YES. BAD BAUD RATE
FORMAT TERMINAL

111

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)

If using the flowcharts fails to help locate a
RXDP package diagnostics (diskette AS-F824C-MC).

problem,

Program Name

Function

VDVA
VDVC
VKAA
VKAB
VKAE
VKAF
ZKMA
ZLAC
ZRXA
ZRXB

DLV-llE Test
DLV-llF Test
LSI-11 CPU Test
LSI-11 EIS Instruction Test
DLV-11 Test
DRVll Test
Memory Test
LA36 Test
RXll Disk Exerciser
RXll Interface Tests

run the

The following figure shows the flow of events in the LSI-11
sequence.

112

boot

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)

LSl-11 BOOT AT 173000 FLOWCHART, PART 1
START

START

(200)*

REVERSE
TERMINAL
ADDRESSES

ADDRESS+
140.000

(216)

(204)

(1234)*
GOOD DATA R3
BAD DATA (R2)

.........

~~--.~~~~

.........

(1260)*
GOOD DATA R3
BAD DATA (R2)

CHECK BYTE
SINGLE OP
INST DEST
MODE 0

~~~~~~~

TEST 2

(372)

CHECK SOURCE
MODE DOUBLE
OP WORD
INST DEST MOOE 0

TEST 3

CHECK BYTE
DOUBLE OP
INST DEST
MODE 0

TEST 6

(436 1

*ADDRESSES OFFSET
FROM 140,000

113

(600)

START

BOOT LSI
BUT NOT
VAX-11/780

IREBOOTJ

TEST 7

0
0

1752)

(13301

-I
SET PWR-UP/
CRASH FLAG

)>
'B-110
ERROR"
OISPLAY

TEST 8
11046)

-I

.........,

TEST 9

L---~---

1074=JSR
1116 = RTS

"T1

TEST 10. 11

.-t
"C
)>

SET

-I
N

(")

(/)

0
rm
CD

0
0

::c
0

(/)

:I:

0
0

G')
'Tl

:1:

CONSOLE
PROGRAM

c=;
0

z
:::!.

CHAPTER 5
INTERNAL REGISTERS

PROCESSOR REGISTER ADDRESSES

HEX

DEC

00
01
02
03
04
05
06
07
08
09
OA
OB

2
3

KSP
ESP
SSP
USP

ISP

5
6
7
8
9
10
11

OD
OE
OF
10
11
12

13
14
15

19
20
21
22

16
17
18

19
lA

24
25
26

lE
lF
20
21

30
31
32
33

22
23

24
25
26
27
28

29
2A

28
2C

35
36

37
38
39
40
41

42
43

44
45

2E
2F
30

46
47
48

31
32
33

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

34
35
36

37
38
39
3A

38
3C
30

3E
3F

reserved
reserved
reserved
POBR
POLR
Pl BR
PILR
SBR
SLR
reserved
reserved
PCBB
SCBB
IPL
ASTR
SIRR
SISR
reserved
reserved

recs
NICR
ICR
TOOR
reserved
reserved
reserved
reserved
RXCS
RXDB
TXCS
TXDB
reserved
reserved
reserved
reserved
ACCS
ACCR
reserved
reserved
WCSA
WCSD
reserved
reserved
SB IFS
SBIS
SB I SC
SB I MT
SB I ER
SB I TA
SB I QC
reserved
MME
TBIA
TBIS
reserved
MBRK
PMR
SID

Kernel stack pointer
Executive stack pointer
Supervisor stack pointer
User stack pointer
Interrupt stack pointer

PO base register
PO length register
Pl base register
Pl length register
System base register
System length register
Process control block base
System control block base
Interrupt priority level
AST level register
Software interrupt request register
Software interrupt summary register
Interval clock control/status
Next interval count register
Interval count register
Time of day register

Console
Console
Console
Console

receive control/status
receive data buffer
transmit control/status
transmit data buffer

WO
RO

RO
WO

Accelerator control/status
Accelerator reserved
Writable control store address
Writable control store data
SBI fault/status
SBI silo
SBI silo comparator
SBI maintenance
SBI error register
SBI timeout address
SBI quadword clear

RO
WO

Memory management enable
Translation buffer invalidate all
Translation buffer invalidate single

WO
WO

Microprogram breakpoint
Performance monitor register
System identification

reserved

117

PROCESSOR REGISTER BIT CONFIGURATIONS

REG"'
DEC. HEX NAME IDti
0

KSP

ESP

SSP

USP

ISP

KERNEL STACK POINTER
EXECUTIVE STACK POINTER
2A SUPERVISOR STACK POINTER
28 USER STACK POINTER
2C INTERRUPT STACK POINTER
28

31
VIRTUAL ADDRESS OF TOP OF STACK

POBR

PO BASE REGISTER
RESERVED OPERAND FAULT IF VLA < 2••31

PlBR

25 Pl

BASE REGISTER

RESERVED OPERAND FAULT IF VLA < 2 .. 31

2 .. 21

02 01 00
VIRTUAL LONGWORD ADDRESS

POLR

PO LENGTH REGISTER

Pl LR

Pl LENGTH REGISTER

I I
MBZ

LENGTH OF POPT IN LONGWORDS

2 .. 21 ·LENGTH OF PlPT IN LONGWORDS
13

SLR

SYSTEM LENGTH REGISTER
LENGTH OF SPT IN LONGWORDS
RESERVED OPERAND FAULT IF MBZ *O
31

22 21
MBZ

LENGTH IN LONGWORDS

118

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

~~~: ~EX NAME ID*
16

PCBB

PROCESS CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ *- 0.
02 01 00

3130 29
MBZ

scss 38

PHYSICAL LONGWORD ADDRESS OF PCB

MBZ

SYSTEM CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ *- 0.
313029
jMszj

IPLR

PHYSICAL PAGE ADDRESS OF scs

INTERRUPT PRIORITY LEVEL REGISTER
31

0504
MBZ

ASTR oc

IPSL<20:

16>1

AST LEVEL REGISTER
RESERVED OPERAND FAULT IF NOT VALID I.E., MBZ *-0.
31

I
12

SBR

MBZ

SYSTEM BASE REGISTER
RESERVED OPERAND FAULT IF MBZ *- 0.
31 3029
IMszl

PHYSICAL LONGWORD ADDRESS

TK.0711

119

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
DEC. HEX NAME ID#
24

1ccs

INTERVAL CLOCK CONTROL/STATUS

RUN
wc{ERR
IE

XEGR}
SGL CLK W/O

BITS 4, 5 ARE 11/780 SPECIFIC
25

NICR

NEXT INTERVAL COUNT REGISTER
31

00
NEXT INTERVAL (1 MICROSECOND INCREMENTS, TWO'S COMPLEMENT)
WRITE ONLY

ICR

INTERVAL COUNT REGISTER
RESERVED OPERAND FAULT IF WRITE
31

INTERVAL COUNT (1 MICROSECOND INCREMENTS)
READ ONLY

TODR 01

TIME OF DAY REGISTER
31

00
TIME OF DAY (10 MILLISECOND INCREMENTS)

SOFTWARE INTERRUPT REQUEST REGISTER

SIRR

RESERVED OPERAND FAULT IF READ
31

MBZ

0403

00
SIRL

WRITE ONLY

SISR

SOFTWARE INTERRUPT SUMMARY REGISTER
31

1615
0100
SOFTWARE INTERRUPT REQUEST
F EDCBA98765 4321

MBZ

120

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
DEC HEX NAME ID#
32

Rxcs 04 CONSOLE RECEIVE CONTROL/STATUS
31

08070605

0807

MBZ

RXDB

CONSOLE RECEIVE DATA BUFFER
RESERVED OPERAND FAULT IF WRITTEN
24 23

I
34

TXCS

BYTE 3

1615
BYTE 2

BYTE 1

READ ONLY

BYTE 0

CONSOLE TRANSMIT CONTROL/STATUS
08 070605

MBZ

READY
35

TXDB

CONSOLE TRANSMIT DATA BUFFER
RESERVED OPERAND FAULT IF READ
31
2423
1615

BYTE 3

BYTE2

WRITE ONLY

121

0807
BYTE 1

00
BYTE 0

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
DEC HEX NAME

ID#

ACCS

ACCELLERATOR CONTROL/STATUS
3130

ERR

RES QPR

ACC ENA

16 1514

2827 26

ACC TYPE

MICRO BREAK (WRITE)
CURRENT ADDRESS (READ)
MIC MAT

wcsA

WRITEABLE CONTROL STORE ADDRESS
31

1615141312
MBZ

WCSADDRESS

P1lv I

MOD3

CTR
45

WCSD

WRITEABLE CONTROL STORE DATA
WRITE: WCS DATA
READ: WCS PRESENT
31

wcs PRESENT
0706050403020100

122

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

F TME OUT

GO MAT
REV F
SBI
UNEX
PO
RD

Gl MAT
REV SBI Pl
DSBL SBI

R/O

123

}RIO

CYC

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
DEC HEX

NAME

ID#

SBIER

SBI ERROR REGISTER
16151413121110 0908 07 060504030201 ()()

RDS CRD INT EN

~~~

we{

CP TIME OUT
RIO{CP TIME OUT STATUS-----'
MBZ-------'
RIO{ CP SBI ERR CNF-----~
18 RDS
WC { 18 TIME O U T - - - - - - - - - '
18 TIME OUT STATUS
18 S81 ERR CNF---------~

R/O

MLTERR----------~

{

NOT8SY--------------'
M8Z-------------'

S81TA

IA SBI TIMEOUT ADDRESS
RESERVED OPERAND FAULT IF WRITE
313029 28 27

PHYSICAL ADDRESS< 29:2>
READ ONLY
PROT
CHK

S8IOC

SBI QUAD CLEAR
RESERVED OPERAND FAULT IF READ
RESERVED OPREAND FAULT IF M8Z ;t0
3130 29
IM871

PHYSICAL QUADWORD ADDRESS
WRITE ONLY

124

0302

I I
M8Z

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
DEC HEX NAME ID#
56

MEMORY MANAGEMENT ENABLE

MME

WRITE 1 ALSO CAUSES MICROCODE TO INVALIDATE TB.
01 ()()

MME

TRANSLATION BUFFER INVALIDATE ALL

TBIA

RESERVED OPERAND FAULT IF READ
31

()()

MBZ
WRITE ONLY

TRANSLATION BUFFER INVALIDATE SINGLE

TBIS

RESERVED OPERAND FAULT IF READ
31

()()

VIRTUAL ADDRESS
WRITE ONLY

MBRK

MICROPROGRAM BREAKPOINT
31

PMR

1312

()()

MICRO PROGRAM ADDRESS

oc PERFORMANCE MONITOR REGISTER
RESERVED OPERAND FAULT IF >1
31

01 ()()
MBZ

PME

SID

SYSTEM IDENTIFICATION
RESERVED OPERAND FAULT IF WRITE
31
2423
1514
SYSTEM TYPE

ECO LEVEL

1211
00
MFG
SYSTEM SERIAL NUMBER
PLANT

READ ONLY

125

REG.NAME

REG.ID NO.

IBUF

INT.REG.NO.

J1/15

J0/14

29/1J

28/12

27/11 26/10

Data Byte 3
29
28
27

Time Byte J
29
28
27

Time Byte 1
12
13
11

0 3 - I J J1

Type
28

Plant
13
12

25/09
25

24/08
24

2J/07
23

22/06
22

19/0J

21/05 20/04

Data Byte 2
21
19
20

Data Byte 1
12
11

Data Byte 0
4

Time Byte 2
19
21
20

18/02 17/01

16/00

(I)

O:J
18

s:)>
'"tJ

DAY.TIME

1B TODA
Jl

SYS.ID

" -l

O'>

ECO
Level
15
RXCS

RXDB

Data Byte 2
19
20

Time Byte 0
4

ECO Level
20

Serial Number
6
5

21 RXDB
31
15

Data Byte J
28
27

Data Byte 1
13
12
11

26
10

Done

lntrpt
Enable

Data Byte 0
4

REG. NAME

REG. ID NO. INT. REG. NO.

TXCS

22 TXCS

31/15

30/14

29/13

28/12

0
TXDB

NXT. PER

23 TXDB

24/08

23/07

22/06

l 30 l 29 l 28 l 27 l 26 l 25
l 14 l

l
l

lAICR
31
15

l 10

L 10 l

lntrpt
Enable

21/05 20/04
0

19/03

18/02 17/01

16/00

:ta

l 22 l 21 20 19 l 18 l 17 l 16
Data Byte 0
0
2 l
1 l
5 l 4 l
3 l
7 l
6 l

l 8

D(ref) o(write)
9
8
7

Byt12

1 22 l 21 l 20 1 19 l 18 l 17 l 16
l 6 l 5 l 4 l 3 l 2 l 1 l 0

Next Interval

l 29 l 28 l 27 l 26 J 25 l 24 l 23 l 22 j 21 l 20 l 19 l 18 l 17 l 16
Nit Interval
14
l 13 l 12 l 11 l 10 l 9 8 l 7 l 6 l 5 l 4 l 3 l 2 l 1 l 0

0
0

lntrpt
Req

11 110 1

lntrpt Single
Enable Clock

Count (microtonds)
23

l 22 l 21

;ounl (m~rorn~s)

J l

l 30 l 29 l 28 1 27 l 26 l 25 l 24

1 l

Cl)

D(rJd) O(wlte)
24
23

rta Byte 1
12
11

Ready

l 14 l 13

Error

INTERVAL

25/09

19 NICR

18 ICCS

l 30 l 29 r B28y r 27 l 26 l 25 l 24

CLK.CS

27/11 26/10

Xfer

Run

l 20 l 19 l 18 l 17 1 16

1 1
1

s:)>
'"ti

n0
z

.::i

REG. NAME

CES

REG. ID NO.

INT. REG. NO.

13 ASTA
30 PME

31/15

28/12 27/11 26/10

30/14 29/13
0

Control Store Parity Er'lr
Summary
2
1

VECTOR

SIR

PSL

ALU
N

ALU

ALU
C31

EALU EALU
N

I'.;)

oa 1

18/02 17/01 16/00

Arithmetic
Trap Code

Pert
Mon En

J D _l c l

Comp at
Mode

Trace
Pend

FPO

r t ; a ' i ln~errr ~egt 6

lntrpt
Stack

Interrupt Priority Level
Active

Modify

1 4 _L

Protection Code

Decmal Float
lntger
Ovrflo Undflo Ovrflo

141 13

12 111

~ag~r:e ru~berJ

0
6

Interrupt Priority Level

Previous
Mode

Current
Mode

-T

CoJition Cjdes
Z
~C-

lage19 l 18 l 17
Frame Number

9
CD
c:
(/)
3:
l>

AST Level

Number of Ones

10
Valid

Nested
Error

1 06 1 05 JV~orj 03 l 021 01 l 00

15SISR

12 IPL

19/03

20/04

Priority

TBUF

21/05

22/06

""D

Prior
Valid

25/09 24/08 23/07

l 4 l

l 16

l 2 1 l 0
1

REG. NAME

REG. ID NO. INT. REG. NO.

TBERO

31/15

30/14 29/13

0
FS

TBER1

l ADS l

ODO

N
<O

Ace.cs

SILO

SBl.ERR

26/10 25/09
0

Last Reference
MCT 31 MCT ~MCT 11 MCT Ol1BWCHK

24/08 23/07 22/06 21/05

l AR

20/04

TBlit
G1
GO

18/02

17/01 16/00

Replace
GO

Force TB Misc
G1
GO

Force TB
Parity Error

102

CP TB
PE

Last
TPWrp

Bad
IPA

Mem
Man En

Write Micro
µBreak Match

Error

Resrvd
Op rand

Accel
Enable

After
Fault

SBI
lntlk

l 3 1 2 l 1 l 0

lB~Tt 0

114

113

RDS

CP
TO

l 12 J 11 l

10 1

CP TO
ST1

CP TO
STO

0
Acilergtor Jpe

SBI
SBI
M3/B31M2/830lM1/B291 M0/828 CNF 1JcNF 0

l 3 l

34 SBIER

RDS
Int En

CAD

CP Err IB
CNF RDS

IB
TO

IB TO
ST1

IB TO
STO

IB Err
CNF

Mult
Error

Not
Busy

.,,

=:!

Micro-break (write)
Current Address (read)

1 ss~ T_i 7 l

s:
)>

JProt EjAuto L

SBI ID

IPA

l PE

Miss

m
c

TB Parity Error Bits
1101
1100
002 1 OD1

Trap Address
0

28 ACCS

31 SBIS

l 1A2 la1AParitJError
~{sOA2
1
1AO
1 OA1 lOAO

Write
TrpAd

19/03

Replace Force
Both
GI

13
0

ACC. MN

28/12 27/11

REG.NAME

REG. ID NO. INT. REG. NO.

TIME.ADA

31/15

1Mr

17
FAULT

COMP

30/14

~:rr
:r~r~

28/12 27/11 26/10 25/09

29/13

35 SBITA

Prot
Check

j 28 j

l 13 l 12 l

27 j

22/06 21/05

24/08 23/07
26 1 25

11 ry~i~al ~t~esst

J 6 l

Unexp
RD

Mult
Xmit

Xmit
Fault

EFP

Spare

Silo
Lock

Silo
Int En

Lock
Uncond

Rev
PO

WrSeq
Fault

Unexp
RD

Mult
Xmit

l 3 ~r~Tel~ l 0

Force
MissG1

Force
Rep GO

Force
Rep Gl

Disabl
SBI

Rev
Pl

G1
GO
Match Match

Any
Error

CP
Error

Gl 80

Fault Fault Fault Fault
Latch Int En Signal Lock
0

Compare
Tag

Compare
Command or Mask
0

l 21 J 20 l 19 110

Parity
Fault

Cond Lock
Code

19/03 18/02 17/01 16/00

20/04

LPhysict
Addrj5
24
23
22

Count

Force Enable
SBI Invalid

0
Force

Rierse Cihe Paly

Miss GO

Force
TO

Data Parity OK
G1 BljG1 B2jG1 B3jGOB°l GOB1j_G0821 GOB3 GO 80

Address Parity OK
GO Bll GO 821G1801G181Gl82

REG. NAME

REG. ID NO.

UST ACK

INT. REG. NO.

31/15

30/14

29/13 28/12
0

0
12

UBREAK

WCSADDR.

26/10

25/09

l 11 l 10 l

24/08 23/07
0

22/06 21/05
0

Cltrol Store AddJss
8
7
6

l 5 l

20/04

19/03

18/02 17/01
0

1 11 l 10 l

9 Cro~ S r ~dJess 6

l 5 l

1 21 1 l

2DWCSD

l Control
Store Addresl
4
8
7 l
6 l
5

1J l

l 1 l

l 10 l

n0
z

s:
)>
""C

2C WCSA
ModJ
Counter

16/00

JC MBRK

Invert
Parity
WCS DATA

27/11

Data
Jl

Data
JO

Data
29

Data
28

Data
27

Data
26

Data
25

Data
24

Data
2J

Data
22

Data
21

Data
20

Data
19

Data
18

Data
17

Data
16

Data
15

Data
14

Data
lJ

Data
12

Data
11

Data
10

Data
9

Data
8

Data
7

Data
6

Data
5

Data
4

Data
J

Data
2

Data
1

Data
0

::!

ID-BUS MAP (CONT)

Scratch Pad Locations
Name

Addr

IR No.

Symb

Name

Addr

POBR
Pl BR
SBA
KSP
ESP
SSP
USP
ISP
FPDA
D. SV
O.SV
TO
Tl

24
25
26
28

POBR
Pl BR
SBA
KSP
ESP
SSP
USP
ISP

T2
T3
T4
T5
T6

32
33

29
2A
2B
2C
20
2E
2F
30
31

00
01
02

03
04

1457
1458

T7
TB
T9
PCBB
SCBB
POLA
P1LR
SLR

39
3A
3B
3C
30
3E

132

Symb

10
11

PCBB
SCBB
POLA
Pl LR
SLR

34
35
36
37

.BIN

IR No.

09
08
OD

ID-BUS REGISTER BIT CONFIGURATIONS

ID#: 00

NAME: IBUF

Bit Fields
<31: 00>

Description
Data in Instruction Buffer
Bytes <3:0>
Read Only
Located on M8223

ID#: 01

NAME: TIME OF DAY

Bit Fields
<31:00>

Description
32 bit counter
100 Hertz rate
Read/Write
Located on M8224

ID#: 03

(IDPL)

(IRCN)

NAME: SYSTEM ID
Description

Bit Fields
<31:24>

System Type

<23:15>

ECO Level

<14:12>

Manufacturing Plant

<11:00>

System Serial Number

lill=VAX-11/780

Read Only
Selected by jumpers on backpanel
Read from M8236 CIBC,D,E
ID#: 04

NAME: RXCS

Bit Fields
<07>

Description
Done
Set by console software signifying
data available in RXDB
Read Only

<06>

Interrupt Enable
Allows interrupt when Done set
Read/Write
Located on M8236 (CIBE)

133

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

IDI: 05

NAME: RXDB
Description

Bit Fields
<31:0>

Data from Console Subsystem
Read Only
Located on M8236

(CIBC,D,E)

NAME: TXCS
Bit Fields
<07>

Description
Ready
Set by console to indicate ready to
receive data
Read Only

<06>

Interrupt Enable
Allows interrupt when Ready set
Read/Write
Located on M8236 (CIBE)

IDI: 07
Bit Fields
<31:0>

NAME: TXDB
Description
Data to console subsystem
Write Only
Located on M8236

ID#: 08
Bit Fields
<31:1-'H'l>

(CIBC,D,E)

NAME: DQ
Description
Read: D Register
Write: Q Register
Read/Write
Located on:
<7:00> M8228 (DCPC)
<15:08> M8227 (DDPC)
<31:16> M8226 (DEPL,M)

134

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#: 09

NAME: NEXT INTERVAL COUNTER

Bit Fields
<31:00>

Description
Data loaded into interval counter
on overflow or XFER bit in CLK CONTL REG
Write Only
<31: 16> M8230 (CEHP)
<15:00> M8231 (ICLS)

ID#: 0A

NAME: INTERVAL CLOCK STATUS

Bit Fields
<15>

Description
Error
Over run second overflow before first
serviced.
Read/Write

<fll7>

to clear

Interrupt Request
Set when counter overflows
Read/Write 1 to clear

<06>

Interrupt Enable
Enables interrupt on overflow
Read/Write

<05>

Single CLK
Advance counter on step
Write Only

<04>

XFER
Forces next interval to counter
Write Only
RUN
Allows counter to increment at 1 microsecond
rate
Read/Write
Located on M8231 (ICLS)

135

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

!DJ: 0B

NAME: INTERVAL COUNTER
Description

Bit Fields
<31:00>

32 Bit Up Counter
At 1 microsecond rate
Read Only
<31: 16> M8230 (CEHP)
<15:00> M8231 (ICLS)

IDt:

NAME: CPU ERROR STATUS (CES)
Description

Bit Fields
<16>

Nested Error
Used by Memory Management Microcode
Read Only
Located on M8230

<15>

(CEHP)

Control Store Parity Error Summary
"OR" of Control Store Parity Error Bits
Read Only
Located on M8231

<14:12>

(ICLS)

Control Store Parity Error Bits
<14>=Group 2
<13>=Group 1
<12>=Group 0
Read Only
Located on M8231

<11>

E ALU N

<HJ>

E ALU

<09>

ALU N

<08>

ALU

<07>

ALU C31
Read/Write
Located on M8231

136

(ICLS)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<06:04>

Arithmetic Trap Code
7=Decimal Divide by 0
6=Decimal Overflow
S=Float Underflow
4=Float Divide by 0
3=Float Overflow
2=Integer divide by 0
l=Integer Overflow
0=No Trap Pending
Read/Write
Located on M8231

<03>

(ICLS)

Performance Monitor Enable
Loaded or read by microcode
Read/Write
Located on M8231

<02:01>

(ICLS)

AST Level
Used to deliver AST SIR during RET
Read/Write
Located on M8231

ID#: 0D
Bit Fields
<25>

(ICLS)

NAME: VECTOR
Description
Prior Valid
Indicates at least one bit was set in last
priority field
Read Only
Located on M8230

<24:21>

(CEHP)

Priority
Priority encoded value of bits <31:16> of
bit mask last written into vector register
Read Only
Located on M8230

<20:16>

(CEHP)

Number Of Ones
Number of ones last written
into vector register
Read Only
Located on M8230

137

(CEHP)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<08:00>

Vector
Hardware generated vector
Read Only
Located on M8231

!DI: 0E

Bit Fields
<20:16>

(CEHJ)

NAME: SOFTWARE INTERRUPT REGISTER
Description
Interrupt Priority Level Pending
Level of highest interrupt active
at last interrupt strobe time
Read Only
Located on M8230

<15:01>

(ICLS)

Software Interrupt Register
Pending software interrupt flags
Read/Write
Located on M8231

ID#: 0F
Bit Fields
<31>

(ICLS)

NAME: PROCESSOR STATUS LONGWORD
Description
Compatibility Mode
CPU executing PDP-11 mode instructions
Read/Write
Located on M8230 (CEHP)

<30>

Trace Pending
At end of an instruction and if trace pending
equal a trace trap is initiated
Read/Write
Located on M8230 (CEHP)

<27>

First Part Done
Microcode sets this bit at defined points
within certain instructions, stating that
instruction may be restarted from that point
if an interrupt of instruction occurs.
Read/Write
Located on M8230

138

(CEHP)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<26>

Interrupt Stack
Indicates CP operating on interrupt stack
Read/Write
Located on M8230 (CEHP)

<25:24>

Current Mode
Current operating mode of software
3=USER
2=SUPERVISOR
l=EXECUTIVE
0=KERNEL
Read/Write
Located on M8230 (CEHP)

<23:22>

Previous Mode
Previous operating mode (before change
mode instruction)
3=User
2=Supervisor
l=Executive
l/l=Kernel
Read/Write
Located on M8230 (CEHP)

<20:16>

Interrupt Priority Level
Current interrupt priority level of CPU
Read/Write
Located on M8230

<07>

Enable decimal overflow exceptions

<06>

Enable floating underflow exceptions

<05>

Enable integer overflow exceptions
Read/Write
Located on M8231 (ICLS)

<04>

T bit
Results in setting Trace Pending

<03>

N bit

<02>

z bit

<01>

v bit

139

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<00>

c bit
Read/Write
Located on M8231 (ICLS)

IOI: 10

NAME: TRANSLATION BUFFER DATA REGISTER

Bit Fields
<31>

Description
Valid
Allows TB hits with VA<l3:9> and 31
used as index and address<30:14>
equals VA MUX<30:14>
Write Only
Located on M8220 (CAMV)

<30: 27>

Protection Code
Define Protection of Address
Kernel
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
111!10
1011
1100
1101
1110
1111
R/W
R0

Exec

Unpredictable
R/W
*
R0
R/W
R/W
R/W
R/W
R/W
Rl1l
R0
R0
R/W
R/W
R/W
R/W
R/W
R0
R0
R0
R/W
R/W
R/W
R/W
R/W
Rl1l
Rl1l
R0
No access
Read/Write
Read

Write Only
Located on M8220 (CAMV)
<26>

Modify
Notes a modified page
Write Only
Located on M82211l (CAMV)

140

Super

user

*
*

R/W

*
*
*

*
*
*
*

R/W
Rl1l
R0
R0
R/W
R0
R0
R0

R0
R0
R0
R0

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<20:0>

Page Frame Number
When translation occurs these bits become
page numbers, i.e., PA<29:09>
Write Only
Located on M8222

IDJ: 12
Bit Fields
<20:18>

(TBME)

NAME: T BUFF REG 0
Description
Force Replace
Directs TB writes to defined groups
20=Write Both
19=Force Replace Group 1
18=Force Replace Group 0
Read/Write
Located on M8222 (TBME)

<17:16>

Force Miss
Force TB miss on defined group
17=Group 1
16=Group 0
Read/Write
Located on M8222 (TBME)

<15:08>

Last Reference
Data on last non-nop memory reference
<15> Status of uFS bit
<14> Status of uADS bit
<13:10> Status of uMCT field
<09> 1 means IB WCHK existed on an IB reference
<08> 1 means reference delayed one cycle by IB
auto reload
Read Only
Located on M8222 (TBME)

<'117:06>

TB Hit
Indicate which group was a TB hit
7=Group 1
6=Group 0
Read Only
Located on M8222 (TBME)

141

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<04: 01>

Force TB Parity Error
Allows bad parity to be generated
0
1
2

No errors
No errors
Group Ill Data By;e Ill
3
Ill
1
"
4
Ill
2
Ill
5
1
6
1
1
7
1
2
8
Ill
Address Byte Ill
9
Ill
" 1
A
2
flJ
B
1
Ill
1
c
1
D
1
2
E No errors
F No errors
Read/Write
Located on M8222 (TBME)
<00>

MME
Enable Memory Management
Read/Write
Located on M8222 (TBME)

IDI: 13

NAME: TBUFF REG 1

Bit Fields

Description

<2fll: 09>

TB Parity Error Status
20=1 Group 1
19=1
1
"
18=1
1
17=1
0
16=1
Ill
15=1
l1J
14=1
1
13=1
1
12=1
1
11=1
flJ
lfll=l
Ill
9=1
Ill

Data Byte 2
" 1
Ill

2
1
Ill

Address

By~e

Ill

2
1
Ill

Read/Any Write Clears
Located on M8222 (TBME)

142

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<08>

CP TB Parity Error
Indicate TB microtrap has been requested
Read/Any Write Clears
Located on M8222 (TBME)

<06>

Last TB Write Pulse
Indicates which TB group was last written
0=Group 0
l=Group 1
Both - Unpredictable
Read Only
Located on M8222 (TBME)

<04>

Bad IPA
Contents of IPA are not meaningful
Read Only
Located on M8222

<03:00>

(TBME)

IPA Info
Status of last load from IPA
3=1 TB miss on load
2=1 TB parity error
l=l Protection violation or miss
0=1 Automatic hardware initiated load
Read Only
Located on M8222 (TBME)

IDI: 16

Bit Fields
<31>

NAME: ACCELERATOR MAINTENANCE
Description
Write Trap Address
When set clocks trap address register
Write Only
Located on M8286

<23:16>

(FMHR)

Trap Address
Use to form ROM address on
ACC trap
Read/Write
Located on M8286

143

(FMHR)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<15>

Write Micro Match
Setting clocks micro match register from
bits <8:0> of this register
Write Only
Located on M8287

<14>

(FMLP)

Micro Match
Indicates a micro match has occured
Read Only
Located on M8287 (FMLP)

<08:00>

Micro Break/Current Address
Writes micro break register
Reads current micro program counter
Read/Write
Located on M8287 (FMLP)

IDI: 17

NAME: ACCELERATOR CONTROL STATUS

Bit Fields
<31>

Description
Error
Read/Any write to this register will clear
Located on M8286 (FMHR)

<27>

Reserved Operand
Minus zero error
Read Only
Located on M8286

<15>

(FMHR)

Accelerator Enable
!=Enable Accelerator
0=Disable Accelerator
Read/Write
Located on M8287 (FMLP)

<03:00>

Accelerator type
0l=FPA
Read Only
Located on M8287

144

(FMLP)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

NAME: SILO
Bit Fields

Description
16 location SILO used to store SB! activity

<31>

After Fault
First entry after fault cleared
Read Only
Located on M8219 (SBHJ)

<30>

SB! Interlock
Read Only
Located on M8219 (SBHJ)

<29:25>

SB! ID<4:0>
Read Only
Located on M8219 (SBHJ)

<24:22>

SB! TAG<2:0>
Read Only
Located on M8219 (SBHJ)

<21:18>

SB! MASK<3:11J> or SBI<B3l:B28>
Silo written with SBI<B3l:B28> when SB! TAG
equals command address. Otherwise SB! <M3:M0>
are written
Read Only
Located on M8219 (SBHJ)

<17:lfi>

SB! CNF<l:l/J>
Read Only
Located on M8219 (SBHJ)

<15: 01/J)

SB! TR<l5:00>
Read Only
Located on M8237 (TRSF)

IDI: 19

Bit Fields
<15>

NAME: SB! ERROR REGISTER
Description
RDS Interrupt Enable
Enable interrupt for RDS errors
Read/Write
Located on M8218 (SBLH)

145

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<14>

CRD
Received corrected read data from memory
Read/Write 1 to clear
Located on M8218 (SBLH)

<13>

RDS
Received read data substitute from memory
Read/Write 1 to clear
Located on M8218 (SBLH)

<12:10>

CP Timeout Status
12=1 Timeout for CP requested cycle
11
0
0
1

10
0
1
0

No device response
Device busy
Waiting for read data
Impossible code

12 - Read/Write 1 to clear
Also clears bits<ll:l0>, 08, 02
<11:10> Read Only
Located on M8218 (SBLH)
<fl>

CP SBI Error Confirmation
Set when CP requested cycle receives error
confirmation to command address transfer
Read Only
Write 1 to bit 12 to clear
Located on MR218 (SBLH)

<07>

IB RDS
Read data substitute for IB data
Read/Write 1 to clear
Located on M8218 (SBLF)

<06:04>

IB Timeout Status
06=1 Timeout for IB requested cycle
05

0
0

0
1

No device response
Device busy
Waiting for read data
Impossible code

6 - Read/Write 1 to clear
Also clears bits<5:3>
05:04 - Read Only
Located on M8218 (SBLE)

146

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<03>

IB SB! Error Confirmation
Set when IB requested cycle receives error
confirmation
Read Only
Write 1 to bit 6 to clear
Located on M8218 (SBLF)

<02>

Multiple CP Error
Set with pending CP timeout or CP SB! error
confirmation not serviced
Read Only
Write 1 to bit 12 to clear
Located on M8218 (SBLF)

Oll>

SB! Not Busy
Read Only
Located on M8218

ID#: lA

(SBLF)

NAME: TIMEOUT ADDRESS

Bit Fields

Description
Latches physical address on SB! timeout; will
not latch for IB data timeouts
Read Only
Latched until CP timeout
Error bit (SB! ERR REG bit 12)=1

<31:30>

Mode
31 30
0
0 1
1 0
1 1

Kernel
Executive
Supervisor
user

Located on M8219
<29>

(SBHJ)

Protection Check
Equal 0 for references not subject to
hardware protection check
Located on M8219

<27:00>

(SBHJ)

Physical Address
<27:00>=PA<29:02>
Located on <27:16> (SBHH,J)
<16:00> (SBLF,H)

147

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

IDt:

NAME: SBI FAULT STATUS REGISTER

Bit Fields
<31>

Description
Parity Fault
SBI Parity Fault
Read Only
Located on M8219 (SBHJ)

<29>

Unexpected Read Data Fault
Read Only
Located on M8219 (SBHJ)

<27>

Multiple Transmitter Fault
Read Only
Located on M8219

<26>

(SBHJ)

Transmitter During Fault
Read Only
Located on M8219 (SBHJ)

<25>

Error First Pass
Set by microcode first time through fault
handling code; used to note double errors

<24>

<19>

Read/Write
Located on M8219

(SBHJ)

Read/Write
Located on M8219

(SBHJ)

Spare

Fault Latch
Set from SBI fault
Read/Write 1 to clear
Located on M8219 (SBHH)

<18>

Fault Interrupt Enable
Interrupt on SBI fault enable
Read/Write
Located on M8219 (SBHH)

<17>

SBI Fault Signal
Read Only
Located on M8219 (SBHH)

148

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<16>

Fault Silo Lock
Indicates SB! Silo locked from SB! fault
Read Only
Write l to bit 19 to clear
Located on M8219 (SBHH)

ID#: lC

NAME: SILO COMPARATOR

Bit Fields

Description
Allows lock of silo on predetermined data other
than fault

<31>

Comp Silo Lock
A.

Lock unconditional (see bit 29)
Locks when counter (bits 19:16) equals F

Conditional lock
Lock
when
certain
conditions
exist.
Comparator looks at SB!. When match, compare
signal is generated which allows counter to
increment.
When counter equals F, silo will lock
Unlock by writing number equals F into
counter
Read Only
Clear by writing number not equal F to
counter
Located on M8219 (SBHJ)

<30>

Silo Lock Interrupt Enable
Read/Write
Located on M8219 (SBHJ)

<29>

Lock Unconditional
Enables silo lock when counter equals F
Read/Write
Located on M8219 (SBHJ)

<28:27>

Conditional Lock Codes
28 27
0
0
l
1

0
1
0
l

No compare
ID only
ID TAG
ID TAG, command function or mask

Read/Write
Located on M8219 (SBHJ)

149

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<26:23>

Compare Command or Mask<3:0>
Read/Write
Located on M8219

<22:20>

(SBHJ)

(SBHH)

Compare Tag<2:0>
Read/Write
Located on M8219 (SBHH)

<19:16>

Count Field<3:0>
When equals F, allows silo lock
Read/Write
Located on M8219 (SBHH)

IDI: lD
Bit Fields
<31>

NAME: MAINTENANCE REGISTER
Description
Force P0 Reversal on SBI
Read/Write
Located on M8219 (SBHJ)

<30>

Force Write Sequence Fault
Read/Write
Located on M8219 (SBHJ)

<29>

Force Unexpected Read Data Fault
Causes transmit of SBI TAG=0, Maintenance
ID, Undefined Data, good parity for
unexpected read data in a selected nexus
Read/Write
Located on M8219 (SBHJ)

<28>

Force Multiple Transmitter Fault

<27:23>

Maintenance ID<4:0>
Used to force unexpected read data faults
Read/Write
Located on M8219

<22>

(SBHJ)

(SBHH)

Force SBI Invalidate
Forces writes done by CPU on SB! to
become cache invalidates
Read/Write
Located on M8219

150

(SBHH)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<21>

Enable SB! Invalidate
Allows SB! writes to invalidate cache
Must be =l for normal operation
Read/Write
Located on M8219

<20:17>

Reverse Cache Parity
20
0
0
0
0
0
0

19
0
0
0
0
1
1
1
1
0

0
1
1

17
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
1
0
0
1
1
0

0
0
1
1
1
1

1
1
0
0
1
1

Read/Write
Located on M8219
<16:15>

(SBHH)

Reverse Parity
No P
Group 1 Byte A Address
Group 1 Byte B Address
Group 1 Byte c Address
Group 0 Byte A Address
Group 0 Byte B Address
Group 0 Byte c Address
Unused
Group 1 Byte 3 Data
Group 1 Byte 2 Data
Group 1 Byte 1 Data
Group 1 Byte 0 Data
Group 0 Byte 3 Data
Group 0 Byte 2 Data
Group 0 Byte 1 Data
Group 0 Byte 0 Data
(SBHH)

Force Cache Miss
16 15
0 0
0

1
1

No miss forced
Force miss Group 1
Force miss Group 0
Force miss Groups 0,1

Read/Write
Located on <16> M8219 (SBHH)
<15> M8218 (SBLH)
<14:13>

Cache Replacement
14
0
0
1
1

13
0
1
0

Random
Group 1 always
Group 0 always
Undefined

Read/Write
Located on M8218

151

(SBLH)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<12>

Disable SBI
When set, no SBI cycles will be started
Read/Write
Located on M8218

<11>

Read/Write
Located on M8218
<Hl:09>

(SBLH)

Force Pl Reversal on SB!
(SBLH)

Cache Match
10=1 Group
09=1 Group

cache match
cache match

Read Only
Located on M8218 (SBLH)
<08>

Force Timeout
Forces read timeouts
Read/Write
Located on M8218

ID#: lE

NAME: CACHE PARITY ERROR REGISTER

Bit Fields
<15:14>

(SBLH)

Description
Error
Bit Bit
15
14
No error

IB read reference caused error
CP read reference caused error

Read/write 1 clears entire
located on M8218 (SBLH)

Read only.

152

Located on M8218

(SBLH)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<13:06>

Data Parity O.K.
If set, parity O.K., bit 15 must be set for
meaningful information
13
12
11

Parity

CDM

Group
1
1
1
0
0
0
0

9
8
7
6

Byte 0
1
2
3
0
1
2
3

Read Only
Located on M8218 <13:8> (SBLH)
<7:6> (SBLF)
<05:00>

Address Parity O.K.
If set, parity O.K., bit 15 must be set for
meaningful information
5
4
3
2
1
0

Parity

Read Only
Located on M8218
ID#: 20
Bit Fields
<15:00>

CAM

Group

0
0
0
1
1
1

Byte 0
1
2
0
1
2

(SBLF)

NAME: USTACK
Description
Reading pops top address from micro stack
Writing pushes address on micro stack
<15:00>

= Control Store Address<l5:00>

Read/Write
Located on M8235 (USCD)
ID#: 21
Bit Fields
<12:00>

NAME: UBREAK
Description
Data used to compare micro PC for scope sync
or stopping system clock when SOMM set
Read/Write
Located on M8235

153

(USCD)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#: 22

NAME: WCS ADDRESS

Bit Fields
<15>

Description
Invert Parity
When set inverts WCS parity
Read/Write
Located on M8235 (USCD)

<14:13>

Modulo 3 Counter
Counter used to point to which 32 bit
quantity of WCS is to be written
Read/Write
Located on M8235

<12: 00>

(USCD)

Control Store Address
Use to address WCS for writing
Read/Write
Located on M8235

ID#:

(USCD)

NAME: WCS DATA

Bit Fields

Description

<31: 00>

Data

<07: 00>

Number of WCS Boards Present

Used to write data into WCS

0=1
l=
2=
3=
4=
5=
fi=
7=

0-lK
l-2K
2-3K
3-4K
4-5K
5-6K
6-7K
7-8K

Present

<31:8>Write Only
<7:0>Read/Write
Located on M8233 (WCSB)

154

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#

Name

24
25
26

P08R
Pl8R
SBR

28
29
2A
28
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
38
3C
30
3E

KSP
ESP
SSP
USP
ISP
FPDA
D.SY
Q.SY
T0
Tl
T2
T3
T4
TS
T6
T7
T8
T9
PC88
SC88
P0LR
Pl LR
SLR

All Registers <31: 00>
<31:24>
<23: Hi>
<15:08>
<07:00>

M8230
M8230
M8231
M8231

CEHN
CEHM
ICLR
!CLP

ID registers 24 through 2F are
stored in A temps on CEHK, ICLL

ID registers 30 through 3E are
stored in 8 temps on CEHK, ICLL

All registers are Read/Write

155

SILO REGISTER INTERPRETATION

The SBI silo is a read only register file that provides temporary
storage of various SBI signals for the last 16 SBI cycles.
The assertion of fault by any nexus locks the silo, sets fault
silo lock in the fault register, and makes the data available
through the silo register.
The silo may also be locked through
the use of the SBI comparator register, but comp silo lock will
set in the comparator register rather than fault silo lock.
Examining the silo register when the
result in all zeros being returned.

silo

not

locked

will

Following is a breakdown of the silo register and a description of
the various fields.
AFTER Fault
(31)

Set for first entry after fault clears.

SBI Interlock
(INTLK 30)

The
interlock line
is asserted by the
commander nexus when issuing the interlock
read and then by memory when asserting the ACK
confirmation.

Identifier Field

Identifies the logical source or destination
of information, depending on the TAG type.

(ID 29:25)

TAG Field
(TAG 24:22)

TAG Type

Command address
Write data
Interrupt summary read
Read data

Source
Source
Source
Destination

ID code corresponds to
the device operates.

the TR line at which
TR

ID Code

Device

00001
"10011
01000
01001
10000

Memory Adapter 1
UNIBUS Adapter 1
MASSBUS Adapter 1
MASSBUS Adapter 2
Processor

Defines
types.

the

transmit

receive

1
3
8

16
information

TAG Type
000
011
101
110

Read Data
Command Address
Write Data
Interrupt Summary Read

156

SILO REGISTER INTERPRETATION (CONT)

Function Field
(F 21:18)

Mask Field
( M 21: 18)

Used with command address TAG to specify the
command type.
Silo bits 21:18 are written
with function bits B3l:B28 when the SB!
specified a command address, otherwise SB!
mask bits are written here.
Function
Code

Function
Definition

01HJ0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Reserved
Read Masked
Write Masked
Reserved
Interlock Read Masked
Reserved
Reserved
Interlock Write Masked
Extended Read
Reserved
Reserved
Ex tended Write Maskked
Reserved
Reserved
Reserved
Reserved

Primary function:
Specify particular data
bytes
of an addressed
location
for
an
operation.
Mask

Byte

0001
0010
0100
1000

Second function:
Specify particular read data
types during a read.

Confirmation Code
(C 17:16)

Mask

Data Type

0000
0001
0010

Read Data
Corrected Read Data
Read Data Substitute

00
01
11
10

No response
Acknowledge
Error
Busy

(N/R)
(ACK)
(ERR)

or unasserted

NOTE:
No response is normal when there
activity on SBI.
Arbitration Field
(TR Lines 15:00)

Indicates the TR devices that are
access to and control of the SBI.

157

is no

requesting

SILO REGISTER INTERPRETATION (CONT)

Example of Interpreting a Deposit Byte:
D/B 500 AA
The following would appear in the silo register if it was locked.

R E/ID 18
Cycles

Silo

Bit Breakdown

ID00000018 20C80001

ID = CPU, TAG
MASK, TR = HOLD

ID00000018 21440000

ID00000018 00010000

CNF

ACK

ID00000018 00010000

CNF

ACK

ID = CPU,

C/A,

WRITE

FUN

TAG = WRITE DATA,

= BYTE 0

These cycles correspond to the following figure.

~~~~~ms r - - c o - - - i - - c 1 - - - i - - c 2 - - - i i . - - - - - c 3 - - i - - - - - c 4 - - - - - - j
TRANSMITTER
NEXUS
I INFORMATION)

TRANSMITTER
NEXUS
!INFORMATION)

RECEIVER
RECEIVER
NEXUS
NEXUS
!CONFIRMATION) (CONFIRMATION!

STROBES
ACK INTO
LATCHES

ASSERTS
DATA

STROBES
ACK INTO
LATCHES

SBI
T2

ASSERTS

STROBES
CIA INTO
LATCHES

RESPONDER

SBI LINE
SAMPLING

RECEIVER
NEXUS
!INFORMATION)

I CIA ACK
STROBES
DATA INTO
LATCHES

RECEIVER
NEXUS
llNFORMATIONI

158

ASSERTS
DATA ACK

TRANSMITTER
TRANSMITTER
NEXUS
NEXUS
!CONFIRMATION! ICONFIRMATIONI

MASK

MICROCODE MACHINE CHECK ERROR LOGOUT

At any machine check, the error handling microcode attempts to
log out the following information.
Ordinarily, it appears on the
stack as shown, but if a double error halt occurs, the operator
can find the same information in the ID-bus temporaries.
This
information is VAX-11/780 specific, of course, and does not apply
to other members of the family.
Data

Memory
Location

ID
Location

Byte Count
Summary Parameter
CPU Error Status
Trapped UPC
VA/VIBA
D register
TB ERR 0
TB ERR 1
Timeout Address
Parity
SBI Error
PC
PSL

(SP)
(SP) +4
(SP)+8
(SP) +12
(SP)+l6
(SP) +20
(SP) +24
(SP)+28
(SP)+32
(SP) +36
(SP)+40
(SP) +44
(SP)+48

None
10 (30)
Tl (31)
T2 (32)
T3 (33)
T4 (34)
TS (35)
T6 (36)
T7 (37)
TB (38)
T9 (39)
None
None

Notes
40(dec) = 28 (hex)
See below
See CES register format
Microcode error location
Virtual address
See TBER0 format
See TBERl format
Physical addr/4
See PARITY format
See SBI.ERR format

The summary parameter is a longword.
Byte 1 is a flag, which is
nonzero if a CP timeout or CP error confirmation interrupt was
pending at the time the machine check occurred.
The interrupt, if
any, has been cleared.
Byte zero indentifies the type of machine
check:
00 02 03 05 0A 0C 0D 0F Fl F2 F3 F0 FS F6 -

CP Read Timeout or Error Confirmation Fault
CP Translation Buffer Parity Error Fault
CP Cache Parity Error Fault
CP Read Data Substitute Fault
IB Translation Buffer Parity Error Fault
IB Read Data Substitute Fault
IB Read Timeout or Error Confirmation Fault
IB Cache Parity Error Fault
Control Store Parity Error Abort
CP Translation Buffer Parity Error Abort
CP Cache Parity Error Abort
CP Read Timeout or Error Confirmation Abort
CP Read Data Substitute Abort
Microcode "not supposed to get here" abort

"IB" refers to memory reads generated by the instruction buffer in
the process of prefetching the instruction stream.
In these
cases, the address stored at (SP)+l6 is from VIBA.
"CP" refers to
memory references explicitly requested by microcode and whose
address comes from VA.

159

DOUBLE ERROR HALT

The CPU will halt i f it finds
microcode that EFP is set.

entry

the

error

handling

The information on the first error will be in !0(30-39] and
Unpredictable on CS parity
U-STACK (trapped microaddresses).
errors.
The information on the
error/status registers.

second

The CPU will be halted after
ID(D.SV] = ID(2E).

error

will

the

associated

leaving a double error halt code in
ID No.

SUMMARY PARA.
CES
TRAPPED UPC
VA/VI BA
D-REG
TBER0
TBERl
TIME.ADDR
PARITY
SBI.ERR

T0
Tl
T2
T3
T4
T5
T6
T7
TB

160

30
31
32
33
34
35
36
37
38
39

V-BUS CHANNEL CONFIGURATION

RELATED
MODULES

V BUS
CHANNEL
~

[] ~
[] [g
[] ~ B
[] ~ ~ r;J
[] ~ ~
[] ~ ~
[] ~ ~
[] I I
5

RESERVED

TK--0703

161

V-BUS DIRECTORY

•qr

CMA'-'

(l'CTALl

1 '~ ,1

,, ....

id(ll

''·'"''
i.' 2

fll0

r "" 3

"'"'

""'

00
id0
k'l0

1"0
ltl0
kllil
"10
id0
"10
00
00

1"(11
idli!
1'10
li:l0

Ill"

,,,~

;\ ~~

~"~~~ ~ 1
I}. ..}1 ~-\ ,1

,, IVI A 3

i:~r;

M!'JDL'L E

r •s•

SIG~AL

uSCF
l!SCF
'JSC F'
USCF'

"'8235
"'llt'35
M/12 35
"'112 35

(PT I'
(PT"'

USCF
USCF
llSCF
USCF

UPCSV
UPCSV '11
UPCSV 02
IJPCSV 03

11•;c· F'

~PT"'

""' ..

M
M

11~CF

"''.17

,,i-.w. 1 1

"'8235
"'823'i
"8235
M823'i

( P TC'
CPTf'
(PT.>
CPTl1'

USCF
USCF
USCF
USCF

IJPCSV I'll!
UPCSV 05
UPCSV 0b
UPCSV 07

M
H

11SCF
11SCF

11·,•v'I\

t.1111" I~

V''l'I\

SC F'
.ISCF'
U5CF
IJSCF

"'ll2 35
Me2J..,
M/l235
"'1123'5

(PT c>
CPTl'I
CPTl'I
(PT;'!

USCF
USCF
USCF
USCF

UPCSV
IJPCSV M
UPCSV 1"1
UPCSV 11

M
H

IJSCF
SCR
IJSCB
1• 1SC J

"'11235
Mllc?J'S
Mll23'5
"'ll23'5

(P Tl•

CPTlC
CPTX
CPTX

IJSCF
USCA
USCf'
USCJ

UPCSv 12 M
STALL M
UT PAP H
ECO i'.'ISPATCM 0b

"'823'5
M8235
Ml\2V;
MA23'5

C"TI
(PT3
(PT3
CPT3

USCE
USCE
USCE
USCE

"'ll2 35
"823'5
"823'5
Mll.?3'5

CP TlC
C"TI

IJSCE
USCE
FCTX
USC"

ol'.I:> II
4 ~A I)

",1 r~ q

~VV-1•U
~-/~A 'I

-. .'I"
~~

;1 cl A

.•·1'1:1<'

(11,1-\

"f'.A I 3

~-- '~

\,. c

•AV'~11 ~

(,'·A,,IF

11.1,115
t6
,.,,.,I 7

.,.,.,;.

}V•-'2r

lkH11'1

Vl''i"E

"H;

?'JI!
VI 11 <'

,, 1 >"21

SCE
11sc E

Vl'l:t12?

USCE.

''''1 3

C'C"l"23

USCE

<1.1 \II

"'·'f'<'ll

USCE
IISCE
IJSC' L

(I[' 1 '5

<iv' lb

1"11\ 7
~''I A

1hl! Q

00
01'!
li:l0
00

"''IC

"''2:"
1'1'21

Vo' 1 A
"'''I "I

r,>;•2'5

"'""'"b
t•v'r>.27
,. ·'"' 3:'1
1<1,'113 \
?;•.- 32

1_1

U~C"'

USC"liSC ''

use"

,,..,, .. 3 3

use,,

1'<''1311
1'01'3'5
'1>'03ti

1_1SC \i
tlSC'J

l'f1 IE

111:" IF

:"l/111137

USC'-'

r,• ID

Vv'l'Ul/I

'10>!11 I

use"'
11SC"'

use"'
use•:

"l:l23'5
"8235
"1'1235
"'823'5
"1123'5
M8235
'11123'5
'1823'5
"1123'5
'1823'5
'1823'5
M/123'5

lil0

1/1.., .. 3

l/IL1(jij2
,1,• .. 113

00
ltl0
"10
111(11

"''211
"'''25

~i'/ll!U

use•:

.~ Jl/l <1 '5

USC"

11!;126
l'ii'27

>WO' ati
,i;111u1

use"'

USC'J

Mf12J'5
M/123'5
M823'5
"'ll23'5

v.1211
"'"'2q

"lli!5r
"11/11151
•'"l"'ic?
•11111'53

USCN
USCN
USCN
iJSC "-

"11235
"'823'5
"8235
"823'5

"10
00
01/J
00

(PT~

'-'A"E

~~).ii~

1.l

fll0
id0
li:l0

"'01/J"'

... )()

id0
ltl0

00
1!0
id(ll

'-l

(

l'/122

lt'<l2A
11!02~

USC>.i

162

(PT)(

CPTX
CPD
CPTX

"" ...

ID 8lJS XC VII
lllP c 3\ 1Cl!ll!)

""'

wcs •R CV CLE M
i.cs
AVAIL L
ACC "'""'
DVfPPIDE L
JBUF FN ( li!7 I <'111!l

ICLK ALU z Cll
DCPA l,,AIW ...

CP TX

CPTX

CPTX
(PTV

F
ACCA UR>'
J

CPD

(PTX

CE><A PSL
ICL~ ALU

CPTx
C"TX
(PTX

('.PTX
('OTX

C"TX
C'"TX

ri:>T X
C~TX

(PTX

A!T M
Cll

Are A UBI

DCP A LH'I

L
H

cs "R (b3t32) ...
cs wP (q'Slbll) H

en x

CPTX

V-BUS DI RECTORY (CONT)

111121
1110
1110
00

002c
Al-12')
002E
li11i'?F

00
1110
1110
00

1i1;1130
>111'131
l'lli132
0033

"'"'"'b"'
l!l(.'lli1b1

M"1'5tl

USClll
USCN
USClll
USC'<

"'"21'5
M8235
M823'5
"'8235

CPTX
CPTX
CPTX
CPH

ACCA UB2 M
CEME UTRAP VECT 0 M
TBMD LAST REF CODE 1 M
l'lAPD SSC l) M

1~01-'b

>'"10b2
3

USCN
USC'USClll
IJSC'i

M823'5
M823S
M@23'5
M8235

CPTX
(PT)(
CPTX
CPTX

CEME UTRAP VECT 1 M
TBMD LAST REF CODE P M
DDPS SC 111,E, 0 H

1"0!3U
01!135
003fl
003'7

Oli>Abtl
00H5
rll1110flfl
000b7

USCN
USCN
USCN
USCN

fo'!lllS
M!l35
M8l35
M8235

CPTX
CPTlt
CPTX
CPTX

JJ
CEHE UTRAP VECT 2 M
CEMF NESTED E.RR C1) M
ICLI< EALU Z (1) M

ee
ee
00

0038

00n
003A

1111

003111

001117121
00071
0007l
00073

USCN
USCN
USCN
USCN

M8l35
M8l35
M8l35
MIJZ35

CPTX
CPTX
CPTX
CPTX

CEHE UTRAP VECT 3 M
CHtH FPO !.IIT L
ICLI< EALU N C1) M

ee
ee
e0
e0

003C
0030
11103E
003F

1!10074
00075
0007b
1110877

USCN
USCN
USClll
USCN

M8235
M8l35
M8l]5
M8235

CPTX
r;PTX
CPTX
CPTX

usc;N REN EN C1811'1) M
USClll BEN EN C1Fl1C) M
USCN BEN EN c 13110) H

~0U0

0'11111
00t12
'110113

0111100
1110101
001"12
et0U3

USCN
USCN
USCP
USCP

M8235
"48235
M8235
M8235

CPTX
CPTX
CPT)t
CPTX

USCN BEN EN Ci11710lll) M
USCN BEN EN Cl!IF108) M
USCP 8ABIT!llCtF11C) M
ICLE BR8IT0C1Bl111) H

10
II
II

0'111111
00t15
004fl
0047

00104
00111'5
01:llelb
00U7

USCll
USCP
USCP
USCP

'48235
MB235
M8235
M8235

CPTX
CPTX
CPTX
CPTX

ICLE 8RIHT0C0F11!18)
USCP BR BIT t C1FI t C)
ICLE BABIT1C18114)
ICLE BABIT1C0F108)

M
H
H
H

00118

1110
ee
ee

0011A
0048

1111"110
0"11t1
1210112
00113

USCP
USCP
USCP
USCP

M8235
MIJl]5
"4!1235
MIJ235

CPTX
CPTX
CPTX
CPTX

USCP 8RBIT2C1F11C)
ICLE BRBIT2C tF.11111)
ICLE BABIT2C0Fllll8)
USCP BRBITJC tF 11C)

H
M
H
H

00
fill
file

0il4C
1/10110
0011E
004F

11101111
1110115
0011b
111111117

USCP
USClt
USCM
USCJ

M8235
M8235
M8l35
M8235

CPTX
CPTX
CPT'J
CPT0

ICLE BRBIT3CHl114) ~
USCP BRBIT4( lF 11Cl H
USCH SYNC PULSE H
CIBlll D MAINT RTN M

file
li'l111
file
ee

0050
0051
11111152
0053

1/1!11120
00121
1110122
IH'!l23

USCJ
USCJ
USCJ
USCJ

M823'5
MB235
MIJ235
M823'5

CPTX
ClllTX
CPTX
CPTX

USCJ INIT Ctl M
USCJ STALL C1) H
USCJ UTR•P ( l) M
USCJ UECO Cl) H

llH'J'Sll

0!111211

0055
005fl
001§7

~'112'5

USCJ
USCJ
USCJ
USCJ

M8235
M8235
M!!235
M823'5

CPTX
CPU
CPTX
CPTX

USCJ MAI NT RET ( 1) M
USCJ PRIOR 0 L
USCJ PRIOR 1 L
USCJ PRI011 2 L

10
10

ee
ee
ee

.,,

111111

flll!I
fll111

file
flllll

00tl~

kH."VJSS

ll"10Cjb
0!~057

00l2fl
121'H27

163

V-BUS DIRECTORY (CONT)

0'1111

USC"'
USC"'
USCM
USC"'

M8235
M8235
MnJ5
Mll215

CPT2
CPT2
CPT2
CPT2

USC"' BUF UPC 0~ M
USC"' BUF UPC 01 M
USC"' BUF UPC P2 H
USC"' BUF UPC 03 H

USCM
USCM
USCM
USC"'

M!215
"'1!!235
"'8235
M8235

CPT2
CPT2
CPT2
CPT2

USCM RUF UPC irlll M
USC"' BUF IJPC ~c; H
USC"' BUF UPC 0b H
USC"' BUF UPC 1'!'7 H

Ill

005!
005q
005•
0059

Ill
Ill

005C
fl05D

Ill

00'i!

005F

flll!t 111
P0115
0013&
00111

Ill
il0

00b0
00&1
00b2
00&3

11101110
01111111
1111111112
001113

USC"'
USCM
USC"'
USCM

M8235
M8215
"48215
M8235

CPT2
CPT2
CPT2
CPT2

USC"' BUF UPC 1'8 M
USCM RUF UPC 111q M
USC"' BUF UPC 10 I'
USCM BUF' UPC II t

00
80

00bll

Ill

01"bb

00b7

001114
0111145
P014b
011l1ll'7

USC"'

0Cllb5

1118215
M!2J5
"411235
f'l8235

CPT2
CPTX
CPTX
CPTX

USCM BUF UPC 12 H
RfSEi:!VED
RESERVED
RESERVED

81
81
Ill

lilt
Ill

0111110
0~111
0~112

uscx

us cw

USCX

164

V-BUS DI RECTORY (CONT)

CHAN
lrlt
lrlt

01
lrlt

BIT
(Mfll)

8IT
COCUL>

OWG

MODULE

T1 S 1

SIGN•L NAME

111000!

11!0i'100
001!01
flllt"eA2
A011!A3

CEl-IE
CEHE
CEHE
CEME'

"48231'1

M8230
M82311!
M8230

CPTX
CPT)(
CPTll
CPTlC

PCSC FIAR ERR
PCSC PAR ERR
PCSC PAR ERR
SALP PAR ERR

CEHF.:
CEH'
CEHF
CEMF

Mll23ill
M823fl
M823A
Mll230

CP TX
CPTll
CPTX
CPTll

T!!'Milll PROT UTRAP L
CEHF IRD STATE H
CEH' READ RLOG H
CEM' LOAD STATE H

M8230
M!230

CPTlt
CPH
CPTX
CPTX

CEHF CLR UlllORD C1) H
ICLS EN ID XCEIV L
l')EPM 8MlC31 l
OOFID BMX15 L

1111111!'1
lllAP.2
1'1003

(95164) M
(63132) H
( 31100) M
TRAP L

ill
ill
fill

0it!1114
111005

11100~4

0~06

lihlfll"fl

01111117

00007

1111

01iHHI
A009
0AIU
0A08

0illllll0

0111011
0111012
0A013

CEMF
Cf MP
CEHA
CEM4

0it!lll14
1111111111'5
0lilOl1e
00017

CEHA
CEH4
Cf MA
CEIH

M8231il
M8230
M823A

CPTX
CPTW
CPTX
CPf)(

DCPD
DEPD
!'lOP!!'
DCPD

BMX1117 L
AMX31 L
AMX15 L
AMX07 L

M8230
M8230
M8230
MB23lll

CPT)I'
CPTX
CPTit
CPTX

DEPI<
DCPL
DCPL
OCPL.

4LU BUFF31 L
ALU C4RRY31 L
ALU CARRY15 L
ALU C4RRY07 L
•LU BUFF 17 L
ALU !IU,,lfl L
ALU RUFF15 L
4LU BUFF07 L

ill

01
01

lll0i'IA'5

'1Bl3lll

M8230

1111
01

000c
e000

lilt

liH'IM

11!00F

ill

01
01

11111110
011111
111012
02'13

0'1102111
0,3021
111111022
11'~023

CEHA
CEMA
CEHA
CEMA

1111
01
01
01

01l114
'1it!15
001&
0017

01t"ill24
0111025
01102&
l!'fllOl27

CEH4
CEHA
CEH4
CEHA

M8230
M8230
"18230
M8239

CPTlt
CPTlc
CPTll
CPTX

CEH4
CEH4
CEM4
CEHA

00111

1111'103111
00A31
001!32
00033

CEMA
CEHA
CEMA
CEiotA

"1lll30

11101 A
fllll1A

M8230
"48230
M8230

CPTlt
CPTX
CPTX
CPTX

DEPN ALUC3011B)•0 L
DOPF ALUC15108)•0 L
DCPF ALUCA71fll0)•0 L
BUS ALU 8YTE2,3 A•B M

01
1111

11101C
0;110
1'101E
0A1F

001il34
00035
'111'111136
0"'037

CEM4
CEHA
CEMB
CEMB

M8231'1
148230
148231'1
M8230

CPTX
CPTX
CPTX
CPTX

01
01
11
01

01112(11
0021
0022
Hlll23

00011111

8(11041
00042
0ill0113

CEMB
CEHC
CEHC
CEMC

M8230
M8230
M8230
"18230

CPTX
CPTX
CPTX
CPTX

OAPB AUALU•A MINUS B L
OOPN EALU0CJ M
DOFIN EALU08 H
ACCX NOATA H

11
11
01

00211
0025
0021>
0027

0!11!944
1'1£'111145
0ill'1111b
01'.40117

CEMC
CEMC
CEMC
CEHD

M!230
M8231'1
M!23'11
M8230

CllTX
CPTX
CPTl(
CPTX

•ccx ZDATA H
ACCX VOAU H
ACCX COAU M
CEHD SECOND REF H

01
11
01
11

(111'128
00l21J
01'12A
002ll

01'1050
00051
0(11052
001'153

CEMD
CEMO
Cf M"
CEHD

"48230
"18230
M8230
M82]i,ii

CPTX
CPTX
CPTX
CPTX

S8LT STALL L
IRCJ DQ CO"'IT H
IRCJ FLOAT M
IstCJ WORD CONT H

ill

01
01
01
lrlt

lilt

l'll'llQ

MBt']lil

165

BUS ALU BYTE1 UB M

eus ALU 8YTE0 A•B H

OCPA OIX01'1 L
OAPB AUALUO PLUS B L.

V-BUS DI RECTORY (CONT)

01
01
"'1
01
ld1
1<11
1111
1111

i.>Ol2C
1"1120
Ol02E
111~12F

Ql~l

t'1'5 ll

Qll~rl'55

Olli't'l'H1
OIVl0'5'7

CEMO
CEMD
CEME
CEME

"'1123"
"'11230
Mll231'1
Mll2H

CPTX
CPTX
CPTX
CPTX

IRCJ BYTE CONT M
T8MW SAVE CONTEXT M
OOPS FLOAT NURO M
USCB CLR UTRAP L

"'11231'1

1.H,~~

O!OIPIMl

\A;l]\

1111-rntit

CEHR
CEMR

M823111

CPTX
(PT)'

0!1'132

00l(.'lf,2
0'41:'1&]

CEM~

M~230

(PT)(

0033

CEME

M82]1!

CPTlC

DCPM VA02(1) M
DCPJ VA0l ( l) M
DCPJ VUOl(l) M
T!'IMW EN CMOOAORS M

01
"'l
1111
1111

00]11
0035

000&11
000&'5

00H

Oh~l:'I&&

01!137

0011167

CEME
CEME
CEl-IE
CEl-IE

Mll23(.'I
Mi-2311'
Mll230
"'8210

CPTX
CPTX
CPTX
CPTX

a MN PAGE EDGE M
T,,_MW EN UNALJGN TRAP M
SFIL"' TIMEOUT TRAP L
SBLR ROS TRAP L

01
1111
1111
01

00311
003q
003'
11103!'1

00070
{.110071
00072
00071

CEl-IE
CEME
CEME
CEl-IE

M8230
Mll230
MB230I
Mll230

CPTX
CPTX
CPTX
CPTX

TRMW
T!!Mlol
T8'"W
CEME

01
01
01

003C
0010
0'113E

000711
00075
0007b

111

~0311'

llllll077

CEMX
CEMX
CEl-IX
CEMX

""11231<"
Mll230
Mll230
M82l0

CPTX
CPTX
CPTX
CPTX

RfSERVEO
RESERVED
PESEPVED
RESERVED

166

TB PAR UTIHP
MISS UTRAP L
MBJT UTRAP L
CS Pf TRAP M

V-BUS DIRECTORY (CONT)

CHAN

BIT
(HEX)

BIT
(OCTAL)

DWG

"'DDULE

T,S,

SIGNAL NA"'E

12
112
12
112

11100111
001111
0002
001113

1110111111111
011U!J01
08002
11111U!J03

OAPA
OAPA
DAPA
DAPA

14822CJ
14U2CJ
MU2CJ
MB22CJ

CPTX
CPTX
CPTX
CPTX

IRCF OPCil H
!ACF OPCl H
IRCF OP Cl M
IRCP' OPCl M

112
12
112
112

0fi'l04
1005
000b
lfll01

IHJ1011
111011105
elil00b
'90107

DAPA
DAPA
DAPA
DAPA

MB22CJ
MB22CJ
MB22CJ
MB22CJ

CPTX
CPTX
CPTX
CPTX

IRCF OPC4 M
IRC' OPC5 H
IRCF OPCb H
IRCF OPC7 H

12
192
192

fi'IHB
000•
00U

IHJ011!1
1110011
1110912
0A013

DAPX
DAPX
DAPX
OAPC

MB22CJ
MB22CJ
MB22CJ
MB22CJ

CPTX
CPTX
CPTX
CPTX

CEHD MfMA!F IH•F.! H
CEHD MfMREI" DT•LFDG M
RESERVED
RESERVED

111119014

OAPC
DAPC
OAPC
OAPO

MB22CJ
MB22CJ
14822CJ
MB22CJ

CPTX
CPTX
CPTX
CPTX

IRCE AVTE CONT H
IRCE WORD CONT M
IRCE LFOQ CONT M
IRCH PC REG M

'4B2lCJ
MB22CJ
"'B22CJ
M~22CJ

CPTX
CPTX
CPTX
CPTX

RESERVED
IRCE SPl CON2 M
IRCE SP1 CONl M
IACE SP! CON!.'! M

192
192
112
frl2
192
lil2

0008

01110c

0000
000E
000F

!~H15

0P1111b
1119017

112

0011
011112
011113

00023

OAPF
OAP,
OAPF
OAP,-

12
lil2
192
02

IH'l14
0015
01<'1lb
0017

01.'!11124
00025
001itlb
0111027

OAPX
DAPD
OAPF
DP"

MB22CJ
MB22CJ
Me22CJ
MUZCI

CPTX
CPTX
CPTX
CPTX

OAPB RLOG UPDATE M
CEH' READ RLOG M
RESERVED
RESERVED

12
12

0018
lllt111'

1112

11101•
0018

1110030
0fi'l0Jl
l.'!0032
0011133

OAPX
OAPX
OAPW
OAPL

14822•
M822CJ
14822•
M822CJ

CPTX
CPTX
CPTX
CPTX

RESERVED
RESERVED
RESERVED
IDPN SPl AOR0 L

12
frl2
112
112

01'llC
0010
001E
001F

00111311
00035
000lb
00037

OAPL
OAPL
OAPL
OAPL

MB22CJ
M822CJ
MB22CJ
MB22CJ

CPTW
CPT)(
CPTX
CPTlC

IOPN SPl
IOPN SPt
IDPN SP!
IOPN SP2

12
112
12
112

0020
0021
0022
0023

0004111
00041
001/!42
0'110113

OAPL
DAPL
OAPL
DAPL

M822CJ
MB22CJ
14822•
14B22CJ

CPTX
CPTX
CPTX
CPTlC

IDPN SP2 AORl L
IOPN SP2 AOR2 L
IOPN SP2 AORl L
IOPN PAN 0 L

12
112
112
1112

0024
0025
002b
002'7

000114
111111045
00f114b
00047

OAPL
OAPL
OAPL
OAPX

MB22CJ
M822CJ
MB22CJ
f'4B22CJ

CPTX
CPTW
CPTX
CPTX

IOPN PAN l L
l[lPN PRN 2 L
IOPN PRN 3 L
RESERVED

1'2

0010

1110020
00021
00322

167

AORl L
AOR2 L
AORl L
AOR0 L

V-BUS DIRECTORY (CONT)
CHAN

BIT
COCTAI.)

OlllG

"'ODULE

T0 S 0

SIGNAi. NAME

1!02A
0028

1110050
0fllll51
00152
00053

ICl.T
ICU
ICl.A
ICLA

M8231
M8231
M823t
"'8231

CPTX
CPTX
CPTX
CPTX

•CSC lllCS EVEN PAR M
SBI."' TIMO CNF INTR L
SBHL FAUi. T PHR M
'BHE SBI ALERT R M

H2C
1020
H2E
90211'

10054
11011155
00056
00057

ICU
ICU
ICl.A
ICLA

M823t
MBZ31
148231
148231

CPTX
CPTX
CPTX
CPTX

SBl.M CRO RDS INTR
SBHI< COMP INTR M
SBHE SBI REQ7 R H
SBHE SBI REQ6 R M

0030

00060
00061
00062
0011163

ICl.A
ICl.A
ICLB
ICl.8

M823t
Ml!Z3t
M8231
148231

CPTX
CPTX
CPTX
CPTX

SBHE SBI
SBHE SBI
ICl.B IPL
ICl.B IPI.

M823t
M823t
""8231
M823t

CPTX
CPTX
CPTX
CPTll

ICl.B IPL ACT 2 M
ICl.8 IPI. ACT 1 M
ICl.B IPI. ACT 0 M
CEHJ PRIOR 3 M

BIT
('4Ell)

12
ll

12
12
•2
ll
•2
•2
12
112

•z
•2

0028

euCJ

0031
0032
0033

REQS R H
REQll R H
ACT II H
ACT 3 H

•2
02
02
02

00311
01:135
Altl3b

eeeu

lhl37

0flA67

"'"'"'""

ICl.8
ICLl3
ICLl3
ICLC

02
"2
02
02

111038
111~38

00070
l'!ftl071
''11'072
l'\011173

ICl.C
ICLC
ICl.C
ICl.C

"'8231
M823!
M8231
M8231

CPTX
CPTll
CPTX
CPTX

CEMJ PRlOR l M
CEHJ PRIOR 1 H
CEHJ PIUOR 0 H
CEMR INTR REQ

02
112
02
02

1:11tl3C
003D
003E
00311'

000711
"'0075
1il"1'0711
11101117'7

ICl.C
ICLC
ICLD
ICLO

M82ll
M8231
M8231
"'8231

CPTX
CPTX
CPTX
CPTX

CISS CNSI. RCV INTR H
CIBS CNSL XMIT INTR M
CEHC TRAP CODE2 ( 1) H
CEHC TRAP coon <1> M

02
02
02
02

00110
0Alll
00112
00113

1110100
0\H01
0<'1102
l"lfll1 il3

ICl.D
ICLD
ICLO
ICLD

M8231
M82JI
"'8231
M8231

CPTX
CPTX
CPTll
CPTX

CEHC TRAP COOEl!l ( 1) H
CEHP I030 M
IRCE STAl.L+SVC I.
CIBN HALT REQ H

02
02
112
02

001111
0All5

0i!1011
0!010'5
111111106
01H07

ICLO
ICl.E
ICLE
ICLE

Ml!231
M8231
M8231
"'11231

CPTX
CPTX
CPTX
CPTX

RESERVED
OOPS 8R•NCM3
O!IPV BR BIT3 M
OOPS BRANCH2 H

001113

111111110
00111
00112
M113

ICLE
ICLE
ICLE
!CLE

"'8231
"'"231
M82ll
"'11231

CPTX
CPTW
CPTX
CPTX

OBPV BR BIT2 H
ODPS BRANCHl H
OBPV 13R BITl M
')QPS IHUNCM0 "'

02
"2

01"4C
i,,i/1110
liN4E
001111'

P1' 1111
00115
l"0l lb
1"0117

!CLE
IC Lt
ICU
ICLE

Ml!2J1
Me231
Me231
M@231

CPTX
CPTX
CPTX
CPTX

OBPV BR BIT0 H
IRCl'f 8RC1 M
IRCH BRC0 M
IRCF OPC 0 H

02
02
112
112

0050
00'51
01il52
00'53

00120
00121
00122
00123

ICL?
ICL?
ICLE
f!:LE

"'e211
M!l231
Me231
M!l231

CPTX
CPTX
CPTX
CPTX

TRCH READ OP H
RESfRVEO
ICLE REM B!MX S2 H
ICLE REM S!MX 81 H

•2
02
e2

•z

02
IOZ

"103~
0~3A

fi101H1

0"1117
0~118

0011'1
lt!ll!llA

0Alllb5

168

V-BUS DIRECTORY (CONT)

12
112
lil2
1112

0111511
01'1'55
005b
1111115'7

001211
111111125
0111126
11111112'7

ICLE
ICLM
ICUot
ICLM

M8231
"18231
M8231
'48231

CPTX
CPTX
CPTX
CPTX

ICLE REM BEMX 90 H
ICLM IO TO P9L M
ICLH IO TO VECT L
ICLI< IO TO CE9 M

lil2
lill
12
lil2

0111'58
0f115q
00'5A
0"'1'5R

0111131'1
1'10131
0iau2
1'10133

ICLM
ICLM
ICLM
ICLH

'48231
"18231
Mtl231
"18231

CPTY
CPTX
CPTX
CPTX

ICL""
ICLH
ICLH
JCLH

lil2
lil2
1112
lil2

005C
iH!5E
005F

el'l1311
11111113'5
0ol!l36
{'Ill 13'7

ICLM
ICLJ
ICLJ
ICLJ

"18231
M8231
1118231
M8231

CPTX
CPTX
CPTX
CPTX

ICLH IDM 90 L
DOPA 9C05 <1> M
DOPA 9C011 <1 > H
DOPA 9C03 (1) H

lill
1112

0Pl6A
01'1&1
0111&2
00b3

Pftllllfll
001111
01111u2
1111111.13

ICLJ
JCLJ
ICLJ
JCLJ

'48231
'48231
"18231
'48231

CPTW
CPTJC
CPTX
CPTX

DOPA 9C02 (1) H
DOPA 9C01 (1) H
DOPA 9Cfll0 ( 1) M
ICLJ 0 TO ID L

lil2
!02
1112
liJ2

fll(!!eU
00&5
00&&
11ltl!b'7

111011.11.1
111011.15
A0111e
1'101U'7

ICLJ
ICLI<
ICLI<
ICLX

"18231
"18231
M8231
M8231

CPTX
C:PTX
CPTX
C:PTX

ICLJ ID TO Q L
DOPN EALU0"1 M
DDPN EALU•lll L
RESERVED

111~5"

169

IO TO ATMP L
ID TO BTMP L
IDM 92 L
IDM 91 L

V-BUS DI RECTORY (CONT)

CHAN

1< IT
(HfX)

BJT

l"C>IV':"

'"'lllillll

IOJ

1'1''11

03
1!13

~!i!\'12

.-1"1>11" I
N"l"fl2
\i!i'M1 3

Ill

vh'l"ll

03
1113
03

1"1""5

v1"1iH'4
01:•0<''5

k!M'b

(/l{i1(.ll,>llJ

!.'Cl'ill1

1"1-1111~1

01"1"8

l!l"l"\I"

vlOllMI

111•1"11
<'111'>11?
011013

03
lil3
03
lll3

lll3
03
03
03

""'~3

i'V'!i!A
l">l(/IR

~·:·l"c

0NH)
~l"'lf_

!?IMF

"'"11114

"'~"'' c;

Me.ti>
l"-"1'17

03
03
!03
03

lllil\1
<'11"12

OICl(/121"
l">'t"21
il'l-'1122

''"I 3

l"l'lN'3

03
lll3
lll3
lll3

0<i'14
11111115
0"l1 IJ
01" I 7

W"l"i?ll
('10025

03
lil3
lll3
I03

"'"I B

1-1~'1'130'

03
03
03
kl3

1/1>'11
vi01n

03
03
03
03

"'3
143
03
03

"'"'Ill

t:'!l""'i?o
0il027

1-101 q
CIC't A
1111"1 B

"'"033

14 ~P311

"'"'lE
llli'\F

(>('035
0;l03t>
00031

C>IA20

l~'1041'1

~'121

!"004 I
0>111142
l'lC>!/143

'~\1122

r.J23

PC'\24

('1111G

"'0DUU

T, S,

SIGNAL

Te"'rJ
T8"D
T 8"'1'l
TAMS

"18222
M8222
MP.?22
M8222

(PTX
CPTX
('PTX
(PT{'

TRMD
TO "0
Tl"MD "A51( T 0 "r'.\ L
Tl"Ml'l EN Tr' DFITVERS
TAMS CPTlll l

Hl"IF
TBMF
TR"'C
T8MC

M8222
M8222
M8222
"111222

(PTX
CPTX
(PTl(
CPTX

TAMF
TRMF
CAMU
CAMU

T 8"'U
TBl'U
TR"'"'
T8MX

M8?2?
M822?
M82?2
MB222

CPTX
CPTX
CPTX
CPTlt

CEHE. CMODC AORS TIHP
CEHE PAGE TRAP H
Cf HE CS PAR ERR H
RESERVED

Tf<MN
TRMN
T8"')(
T!l"'U

Mn2?

CPTX
CPTX
CPTX
(PTX

USCR ABORT CYCLE
JPCH IF! lllRJTE CHK H
RESERVED
TBl'U CANCEL

HIMK
TBMK
TR"IK
TBl'C

"'8222
Mll222
l'R22?

CPTX
(PTX
(PTX
CPTX

SBLB
S8L8
SRLR
TRMC

TR"IX
TBMX
TBMX
TRMlll

""B22i?
M822i?
""8222
MB222

CPTX
(PTX
C:PTX
CPTX

RESERVED
RESERVED
SRLS IB EAR LTH H
SBL T STALL L

TBMX
TB"'X
T8"'X
TBMC

Mll2i?2
M8222
"'8222
"'e2n

CPTX
CPTlt
CPTX
('.PT X

RESERVED
RESERVE I'
RESERVED
CA"'V MODIFY

T8"'8
TBMB
TB"'B
T9MB

"'~2Z2

Mll222
M82?;:i
M8222

CPTX
C:PT X
CPTX
CPTX

CAMV
CAMV
CAMV
CAMV

PROTECT
PROTECT
PROTECT
PROHCT

!DPA
IOPA
IOPA
IOPA

148223
M8223
1'18223
r.18223

CPH'
CPTI"
CPT0
CPT0

IOPA
IOPA
IOPA
IOPA

AUF
BUF
RUF
BUF

80•7(1)
BOl•IJC 1)
B\ll•SC 1) H
B0•4(1)

IOPA
IOPA
IOPA
IOPA

M8223
1118223

CPT0
CPTl'I
CPU
CPT0

IOPA
IDPA
IOPA
IOPA

BUF
BUF
BUF
8UF

Blll•3C 1) H
60•2(1) H
B0•1(1) H
B0•fll( 1) M

~A "'f

(OCTAL)

0'1"031
01"1"32

"'~?'5

1"1'1044
P!/11'145

l/IJ2b
(11'127

"'"'"'lib
P'1041

"'8222
"'8222
"18222

"'8222

~8223

M8223

170

GRP "' .. p
GRP I oiP
TB GRP 0
TB GPP 1

L
MATCH "'
"'ATCH H

SBI PA
SBI PA
SBI P4
ENABLE

Olq
10
11
I•

CODE
CME
CODE
CODE

0 l
1 L
2 L
3 L

"'"'
"'

V-BUS DIRECTORY (CONT)

1"3
03
03
il3
il3
il3
03
il3

,w2~

1"1'1"'51"

VI(~ 2<1

1-'"i?A

l'fl'1''51
vWl'l'52

flfl?I'!

"10l'53

l'"J?C

\A{Al"'Sll

kl>'121)
ll'r12E

l"C'rl'5'5

11vi"1'5e

P~',?F

l"Mf'l'57

ill
ill

l'il'J"'

lcl3

"'~' 3 2
l<l"'B

il3

(>,131

•'""~00

11,·re 1
"'''002
QIC"lilb'J

Il)P A
IOPA
IOPA
IOPA

148223
M8223

CPT0
CPT0
CPHl
CPH"

I (IPA
IOPA
IOPA
JDPA

JDPA
IOPA
IOPA
IDPA

M8223
Mi1223
M8223
148223

CPT0
CPT0
CPTI'
CPTl'I

IOPA BUF A1•3( 1)
IOPA BUF Bt•2C 1) ""
IOPA BUF Bl•! Cl l '"'
IDPA 8UF 81•0( l) ""

!DPM
IDPM
IDPM
JDPM

M8223
"18223
M8223
'48223

CPT0
CPTlil
CPTI"
CPHI

IDPM rec lC 1) M
lOPM IBC 2( l)
IDPM IBC 1(1) '"'
IC'PH IBC 0( 1 l '"'

148223
~8223

BUF B 1•7( 1)
8UF Bt•eCt> '"'
BUF 111•5( 1) '"'
"'
BUF Bl•'I( l) 'M

'"'

1113

i-1''1311

r;>l'flbU

JDPM

IOPM CLll 0 L

0035
0036
0037

00065
00066
00067

IDPH
Irlf'A
IDPA

148223
M8223
1'18223
148223

CPTX

03
03
03

CPTX
CPTO
CPTX

IRCE SAVE H
IDPA VAX H
IDPA DST R MODE H

03
03
03
03

0038
0039
003A
0038

00070
00071
00072
00073

IDPJ
IDPX
IDPJ
IDPJ

M8223
M8223
M8223
M8223

CPTX
CPTX
CPTO
CPTX

SBLR IB READ DATA L
RESERVED
IDPJ COUNT H
IDPJ FLUSH L

03
03
03
03

003C
003D
003E
003F

00074
00075
00076
00077

IDPJ
IDPJ
IDPJ
IDPJ

M8223
M8223
M8223
M8223

CPTX
CF'TX
CPTX
CPTX

IDPJ
IDPJ
IDPJ
IDPJ

B5
B4
B3
B2

03
03
03
03

0040
0041
0042
0043

00100
00101
00102
00103

IDPJ
IDPM
IDPM
IDPM

M8223
M8223
M8223
M8223

CPTX
CPTX
CPTX
CPTX

IRCD
IRCD
IRCD
IRCD

PC MODE H
SEL LONG L
SEL WORD L
SEL BYTE H

03
03
03
03

0044
0045
0046
0047

00104
00105
00106
00107

IDPM
IDPM
IDPL
IDPX

M8223
M8223
M8223
M8223

CPTX
CPTX
CPTX
CPTX

IRCE CTX 3 L
IRCE CTX 2 L
IDPL ID BUS XCVR EN L
RESERVED

03
03
03
03

0048
0049
004A
004B

00110
00111
00112
00113

IDPM
IDPM
IDPM
IDPM

M8223
M8223
M8223
M8223

CPTX
CPTX
CPTX
CPTX

IDPM
IDPM
IDPM
IDPM

8 DELTA PC 2 H
16 BIT 8 DEST L
8 DEST H
B DELTA PC 1 rl

03
03
03
03

004C
004D
004E
004F

00114
00115
00116
00117

IDPM
IDPM
IDPM
IDPM

M8223
M8223
M8223
M8223

CPTX
CPTX
CPTX
CPTX

IDPM
IDPM
TBMX
TBMX

VAX SL L
B DELTA PC 0 H
VA 01 H
VA 00 H

03
03
03
03

0050
0051
0052
0053

00120
00121
00122
00123

IRCH
IRCH
IRCC
IRCX

M8224
M8224
M8224
M8224

CPTX
CPTX
CPTX
CPTX

TBMX TB ERR L
TBMX TB MISS L
CEHH FPD BIT L
RESERVED

171

VAL<l>
VAL.<1>
VAL<O>
VAL<O>

H
H
H
H

V-BUS DIRECTORY (CONT)

CHAN

BIT
<HEX>

BIT
<OCTAL>

DIJG

MODULE

T.S.

03
03
03
03

0054
0055
0056
0057

00124
00125
00126
00127

IRCE
IRCJ
IRCJ
IRCM

M8224
M8224
M8224
M8224

CPTX
CPTX
CPTX
CPTX

IRCE
IRCJ
IRCJ
IRCM

IB ADVANCE H
SP2 CON 1 H
SP2 CON 0 H
DATA EN L

03
03
03
03

0058
0059
005A
005B

00130
00131
00132
00133

IRCE
IRCE
IRCE
IRCE

M8224
M8224
M8224
M8224

CF'TO
CF'TO
CF'TO
CF'TO

ICLD
ICLD
ICLD
ICLII

SERVICE
SERVICE
SERVICE
SERVICE

03
03
03
03

005C
005[1
005E
005F

00134
00135
00136
00137

IRCC
IRCC
IRCC
IRCX

M8224
M8224
M8224
M8224

CF'TO
CPTO
CPTO
CPTO

IRCC EXEC CT 0 H
IRCC EXEC CT 1 H
IRCC EXEC CT 2 H
RESERVED

172

SIGNAL NAME

H
BIT 0 H
BIT 1 H
BIT 2 H

V-BUS DI RECTORY (CONT)

CHAN

BIT
P~EW)

1114

OiolG

MODULE

T.S 0

SIGNAL NAME

CA14P
CAMP
CAMP
CA148

"4822111
M8220
"49220
M9221il

CPTX
CPTX
CPTX
CPTX

TBMX FORCE ERR 2 L
TBMX FORCE ERR l L
TBMX FORCE ERR e L
S8HF REV PAR FIELD 3 H

1114
1114

0003

1'1011100
0111001
01'llil02
0011103

1114
1114
04
04

011104
0005
000ft
1!111107

001!11114
0011105
001!11!17
111011107

CAMA
CAMB
CAMB
CAMS

M8220
M9220
'49221!1
M8220

CPTX
CPTX
CPTX
CPTX

S8HF REV PAR FIELD 2 H
SBHF REV PAR 'IELD 1 H
S!HF REV PAR FIELD e H
CAMS Ge AOR PAR 2 OD H

114

1111111118
00M
01110'
01408

011111110
1110011
001!1tl
001!113

CAMS
CA114S
CAMT
CAHT

'48220
M82l0
M822A
M82_2l4

CPTX
CPTX
CPTX
CPTX

CAMS Ge ADR PAR l OD H
CAMS Ge AOR PAR Ill OD H
CAMT Gl ADJ! PAR 2 OD H
CAMT Gl ADR PAR l OD H

1114
1114
1114
1114

11100c
1!101!10
00111E
001!1ff

00014
0001'5
00016
111111017

CA14T
CAMV
CAMU
CAMU

M822A
M8220
14922111
M8220

CPTX
CPTX
CPTX
CPTX

CAMT G1 ADR PAR e OD H
CAMV T8 PAR 2 H
CAMU T8 PAR 1 H
CAMU T8 PAR 0 H

00P"

"4
04

0011
011112
0013

00020
00021
Wlli>022
A0P2]

CAMI(
CAMI<
CAMP
CAMP

M822C
M822P
M8221"
M8220

CPTX
CPTX
CPTX
CPTX

CAHI< Gl MATCH H
CAMI< Giii MATCH H
HLN SBI MISS DATA Gl H
SBLN SBI HISS DATA Giii H

04
04
"4
1114

14014
0015
11'01ft
0017

00024
00025
001!2ft
1'1111021

CAMM
CAMM
CAMM
CAMM

M8220
M8220
M822A
M8220

CPT3
CPT2
CPTI
CPT1

CAMM CPT3 B H
CAMM CPT2 B H
CAMM CPTl 8 L
CAMM CPTl 8 H

1114
1114
1114

00111
0019
001 A
01'118

00030
0011131
0011132
01!111133

CAMP
CA14P
CAMP
CAMP

M8220!
MB220
H822l'I
"48221!'

CPTX
CPTX
CPTX
CltTX

CAHP G1 WRITE ENABLE H
CA14P Gl!I WRITE ENABLE H
SBHN 'ORCE 14IU Gl H
118HF FORCE MISS Gl!I H

04
1114
011
1114

001c
0010
1!1'1!1E
001F

01!1034
1!101l135
1!114036
1!10031

CAHX
CAMS
CAM)(
CAMB

M822e!
M822P
M8ZZ0
148220

CPTX
CPTX
CltTlC
CPTX

RESERVED
CAMB LATCH VALID BIT H
TBMX FORCE ERR 3 L
SBHF REV PAR FIELD 3 L

01!!20
011121

1110040
E!001il

0~22

111~04l

01!123

00043

CAML
CAML
CAML
CAML.

M8220
M8220
148220
148220

CPTX
CPTX
CPTX
CPTX

CAML Gl
CAML. Gl
CA14L Gt
CAHL Gt

0111l4
0025
00lb

000114
00111115
ll!001ift
0011147

"4822~

CPTX
CltTX
CPTX
CPTX

CAHL Gl BYTE 0 PAR OD H
CAML. Gt BYTE l!I PAR EV H
OD H
CAML Giii BYTE 2
CAHL Gl!I BYTE 2 PAR EV H

11114

84
"4

lil4

1114
1114
04

04
04
"4
1!14

01!100
01'11111
0002

BIT
fOCUL)

""'l1

CAML.
COIL
CO~L

CAHL

148l2(11
"48220
H822l'I

173

BYTE 2 PAR OD H
BYTE 2 PAR EV H
BYTE 1 PAlf OD H
BYTE 1 PAR EV H

""'

V-BUS DI RECTORY (CONT)

~HAN

BIT
(M[)()

UT
COCTAL)

DWG

MODULE

T,S,

SIGNAL NA"'E

lil4

00211
i'I0!2CJ
002A

CAML
CA"'L
CAML
CAML

MB22'l
MB22r/I

~021'!

0'111150
0AA51
00052
0111053

MB22fll

CllTlC
CPTlC
CPTX
CPTX

CAML G0 BYTE 1 llAR OD
CAML Giii BYTE 1 PAR EV
CA"'L G0 BYTE 0 PAR OD H
PAR EV M
CAML G0 BYTE

002c
Afi'2D
0<12E
002F

900511
0ill05'5
0fll05&
00!057

CAM"
CAM8
CAMI!
CA"'B

M822"'
M822P'
M!l22fll
"1!122V'

CPTlC
CPTlC
CPTlC
CPT1

CAMB UG PAR 2 EVEN H
CAMB UG PAR 1 EVEN M
CAMB TAG PAR 0 EVEN H
CAMB PA LATCH 12 H

fllfll3QI
0031
l'lr/132
r/1033

000&1'1
01'10&1
M0&2
0!'10&3

CAMI!
CAMB
CA"IB
CA"IB

Mn2P
l"n2A
M8221o'
M822111

CPT1
CPT1
CPT1
CPT1

CAMB PA LATCH
CAMB PA LATCH
CAMB PA LATCH
CAMB PA LATCH

04
04
11!4

til034
111035
A03&
0"137

01t10011
AV'0&5
00!'11&&
000e.7

CA"'!'!
CAMB
CAMB
CAMB

M82?fll
MB22rll
M822fll
M8221'!

CPT1
CPTt
CPT1
CPT1

CAMS PA LATCH 11 H
CAMB PA LATCH 18 M
CA"IB PA LATCH tCJ M
CAMI! PA LATCH 20 H

14
1114
14
14

H3'

ene
eeu

101711
11!11!171
111!172

111038

00073

CAMB
CU4B
CAM!!
CAMB

M8220
M8220
M!l220
M8220

CPT1
CPT1
CPT1
CPT1

CU4B PA LATCM 21 H
CA"IS PA LATCH 22 H
CAMS PA LATCH 23 H
CA"IB PA LATCH 211 H

enc
eeu

CAMB
CAMB
CAMB
CAMB

M8220
M8220
M8221'1
148220

CPTt
CPT1
CPT1
CPTl

CAMB PA LATCH 25
CAMB PA LATCH 2&
CAMll PA LATCH 27
CAMB PA LATCH 28

"'II

lilll
llJ4
lilQ
ill

1"4
011

811
011

011
11111
l1IQ

14
14
1114

11!130

0H74
1110075

1114

0031'

001/!h
0011J77

14
1114

M822~

13 H
111 H
15 H
1& H

H
H
H
H

Ht!IJ0

0041
00112
0043

001" 1
00102
0011113

CDMX
CDMlC
CDMlC
CDMU

M8221
148221
MU21
M8221

CPTlC
ClllTlC
CPTX
CPT2

RESERVED
RESERVED
RESERVED
CDMU CPT2 H

14
114
14
14

eeu

9111104
9111105
0010&
00107

COMU
CDMU
CDMU
COMU

M8221
M8221
"18221
148221

CPTl
CPT1
CPT1
CPT1

RESERVED
RESERVED
COMU CPTt A L
CDMU CPT1 A H

114
1114
14
11111

0048
e04q
00118

IHH11
01rl111
Ht tz
00113

COMT
COMS
COMS
CO"IS

M8221
M822t
"48221
MB221

CllTX
ClllTlC
CPTX
CPTX

TBMO EN CD"' DAU L
CC\MS G1 Bl PAR ODO H
CDMS G1 83 PAR EVEN H
CDMS G1 B2 PAR ODD 11

004C
0040
li!04E
0"'41'

001111
1'10115
0911&
00117

CDMS
COMS
COMS
COMS

"48221
M8221
M822t
148221

CPTlC
CPT)(
CPTX
CPTX

COMS G1 82 PAR EVEN H
CD"IS G1 Bl PAR ODO H
CflMS Gl 81 PAR EVEN H
CDMS G1 BP PAR 000 H

14
114
1114
14

0045
0011&

0111117

174

V-BUS DIRECTORY (CONT)

1051
11051
lil052
0953

0111120
1111121
01H22
00123

CD'4S
CDMlt
CDMA
CDMA

Ml!22 t
'48221
M8221
M822t

CPTX
CPTX
CPTX
CPTX

CDMS Gt 80 PAR EVEN M
CDMll G0 83 PAR ODO H
CDMA G0 83 PAR EVEN M
CDMA G0 82 PAR 000 M

0111511
H55
00511
005'7

'101211
@0125
01111211
00 t 2'7

COMA
COMA
CDMlt
CDMA

M822t
M822t
Ml!22t
M8221

CPTlC
CPTX
CPTlt
CPTlC

COMA G0 82 PAA EVEN M
C[IMA G0 Bl PAA ODO M
CDMA Giii 81 PAA EVEN M
COMA G0 80 PAR ODD M

0058
0054'
005A
0051!

00tl0
1110131
00132
llJllll:U

CDMA
CD'4lC
CDMlC
COMM

M82lt
M8221
M8221
M8221

CPTlC
CPTlC
CPTX
CPTt

CDMA G0 80 PU EVEN M
RESERVED
RESERVED
COMM ADDA LATCM t t M

enc

lilll

01115D
005!
005,

llHH311
0111135
001U
0111137

CDMM
CDMM
CDMM
COMM

M8221
'48221
'48221
M8221

CPTt
CPT1
CPTt
CPTt

CDMM AD011 LATCM t0 M
COMM ADDA LATCM q M
COMM ADDA LAT CM 8 M
COMM ADDA LATCM 1 M

lil4

01116111

'"'"lil4

1111111110
001111
001112
00143

CD'4M
COMM
COMM
C0"1M

M~22l

00111
0'11112

M8221
M822t
M822t

CPTt
CPT1
CPT!
CPTI

COMM ADDll LATCM II M
COMM ADDA LATCH 5 M
COMM AODll LATCM II M
COMM AODll LATCH 3 M

0011111
IHH45
00tllll
Hl 117

COMM
COMB
C0'41!
CDMB

M822t
148221
Ml!22t
M8221

CPTJ
CPTlC
CPTX
CPTlC

CDMM ADDA LATCH 2 M
SBMF REV PAR 3 L
SBHF REV PAR 2 L
SBMF REV PAR t L

00150
00151
11111Jl52
00153

C01'41!
CDM!I
CD'4B
COMX

M822l
148221
Ml!22 l
M8221

CPTX
CPTl
CPTl
CPTX

SBMF REV PAR Ill L
CAMP Gt 111RITE ENABLE M
CAMP Giil itlRITE ENABLE H
RESERVED

00t54
00155
001511
00t5'7

CDMA
CDMA
CDMA
CDMA

"'8221
M8221
M822t
M822t

CPT2
CPT2
CPT2
CPT2

COMA MASK
CDMA MASK
CDMA MASK
CDMA MASI<

'"14
Ill

lilll

'"'"

lilll

14
lil4
Ill

'"
lil4

'"'"

lilll

lil4
lil4

1110113

00114
011115
000

"'11117

•11

00118
llJlll•

14
1114

HllB

lil4
lil4
lil4

0011C
00110

lilll

RHE

0011,

175

3 M
2 M
I H
0 M

V-BUS DIRECTORY (CONT)

CHAN

BIT
( MElC)

BIT
COCTAL)

OliG

MODULE

T,S,

SIGNAL NAlil!

SBLH
SBLF
SBLF
SBLE

"'8218
M8218
M!ll 18
!118218

CPTX
CPTX
CPTX
CPTll

SBHP EN IO DRIVERS
SBHP IO AOOA 2 L
SBHP ID AOOR 1 L
TBMC ENABLE IA H

es
BS
BS
B5

111003

001111110
0011""1
001hl2
00003

BS
B5
e5
BS

IH!011
1'101115
001rH1
11100'7

illilllil011
000fd5
0000b
0000'7

SBLS
SBLS
SBLP
SBLF

Ml!Z18
M!ll 18
M8218
M8218

CPTX
CPTlC
CPTX
CPTX

SBLS AORS LATCH 2• H
IOPJ IB AEQ H
SBLP MO TO 0 L
SBHP IO ADDA 0 L

es
es
BS
B5

0008
000•
l'IOl0A
0008

001111111
Blt'li!!11
0011112
00013

SBLM
SBLP
SBLP
SBLP

M8218
M8218
M8218
M8218

CPTX
CllTX
CPTX
CPTX

SBHN CAD L
TBMN BUF UMCT e L
T8MN 8UF UMCT 1 L
TBMN BUF UMCT 2 L

05
es
BS
0S

Ol0111C
qllt'li.110
11100E
'-"00F

(110014
000u
lil~01 '7

SBLll'
SBLll'
SBLll'
S~L"'

M8218
M8218
M8218
M8218

CPTll
CPTX
CllTX
CPTX

T8MN BUF UMCT 3 L
TBMN BUF UADS L
TBMN BUF UFS L
SBHN ROS L

BS
0S
es
BS

1<'111110

POl020

1110!11

0012
0013

"'~021

1110022
@0023

SBLA
SBLE
SBLL
SBL!

M8218
"'8218
M8218
M8218

CPTX
CPTX
CPTX
CPTX

SBHM SET INVALID L
SBHM S!T Sf.II CYCLE H
SBHR SEND DATA H
SBHM ANY READ DATA

0S
es
BS
0S

1110111
01:11S
00lb
0~1 '7

1'100211
111111025
01:11112&
111~02'7

SBLK
SBLO
S8LW
SBLR

M8218
M8218
M8218
M8Z18

CPTX
CPTX
CPTX
CPTX

SBLIC LATCH TIMO REG L
TBMU CANCEL L
CLl<L SYS !NIT B L
SBLA l'OACE SBI L

lrlS
0S
es
e5

01418
01111•
001'
0018

0011130
11101'131
00!032
1110033

SBLX
SBLX
SBLC
SBLC

M8218
M8218
M8218
M8218

Cll'TX
CPTX
CPTX
Cll'TX

RESERVED
RESERVED
SBLC WRITE DATA H H
SBLC WAITE DATA 11 H

ros
0S
0S
0S

111fl1C
l:l11110
0111lE
11101F

11100311
011103'5
0003b
111003'7

SBLC
SBLC
SBLC
SBLC

M8218
M8218
M8218
M8Zl8

CPTX
CPTX
CPTX
CPTX

SBLC WIUTE DATA ez H
SBLC WAITE DATA n H
SBLC WAITE DATA eo H
SBLC wRITE DATA B5 H

es
es
0S
1115

0020
M21
011122
!0023

l.H'10110
01/!111111
0111042
11100113

SBLC
SBLC
SBLC
SBLC

M8218
M8218
M821ll
M8218

CPTX
CPTX
CPTX
CPTX

SBLC WRITE DATA h H
SBLC WRITE DATA B7 H
SBLC WAITE DATA H H
SBLC WAITE DATA H H

lilS
es
0S
0S

l/!~211

01112'5
002b

0001111
0111011s

"'8218
M8218
M!ll 18
1'8218

CPTX
Cll'TX
CPTX
CPTX

SBLC wFUTE DATA 1111 H
SBLC WRITE DATA 11 H
SBLC WRITE DATA 12 H
HLC WAITE DAU l l H

M8218
M8218
MB218
Mei! 18

CPTX
Cll'TX
CPTX
CPTX

S!ILC WAITE DAU 111 H
SBLC WRITE OAU 15 H
TBMO EN SBI DATA L
BUS MO BYTE B 'AA H

111<'1ill111

0001
1111iHll2

~H"01'5

0~27

00047

SBLC
SBLC
SBLC
SBLC

ros
es

~C.Jlll

.. 021

00050
00051
00052
11101/!53

SBLC
SBLC
SBLC
SBLC

~rnzq

01/'28

0~011b

176

V-BUS DI RECTORY (CONT)

05
il5
05
05

i!i.'12E
11102F

0fil0!54
0011155
111005b
liHH115'7

SBLC
S8LS
S8LA
S8LA

lil82U
H82l8
148218
H82l8

CPTX
CPTX
CPTX
CPTX

BUS MD BYTE l PAA H
SBLS SELECT SBI ADA L
ICLB IPL ACT 111 L
ICLB IPL ACT l L

05
05
05
05

11103111
M3l
0032
011133

Ol00b111
0i'l0U
000b2
000u

SBMB
SBM8
SBMB
SBMB

"48219
M82t9
M82l9
fll82l9

CPT3
CPT3
CPT3
CPT3

SBHB WAITE DAU lb H
SBH8 WAITE DAU 17 H
SBHB WAITE DAU l8 H
88M8 WAITE DAU 1' H

05
115
e5
115

0itllll
0035
01113b
003'7

01110b4

SBHB
S8HB
SBHB
SBHB

H82l9
H8219
M82l9
M8219

CPT3
CP"fl
CPT3
CPT3

8BH8 WAITE DAU H H
SBH8 WRITE DATA 21 M
SBHB WRITE DAU 22 M
SBHB lliRITE DAU 23 M

il5
es
"5
05

003!!
11111139
003A
01113B

0111071
000'72
0iHJ73

SBHB
SBMB
SBHB
SBHB

"48219
H8219
M8219
HU19

CPTl
CPT3
CPT3
CPT3

SBHB WRITE DATA 211 H
SBHB WRITE DAU 25 M
SBHB WRITE DATA 2b M
SBHR WRITE DAU 27 M

"S
ilS
05
e5

003C
1110lD
003E
11103F

09074
0111075
011ll!lh
11100'77

SBHB
SBHB
SBHB
SBM!!

M8219
M8219
H8219
"'8219

CPT3
CPT3
CPT3
CPT3

SBHB lliAITE. DATA
SBHB WRITE DATA
SBMB WRITE DAU
SBHB WRITE DATA

05
e5
05
0S

0040
0041

00100
1110101
00102
0010]

SBHB
SBHB
SBHB
SBHB

H8219
MBZU
M8219
M8219

CPT1
CPTt
CPTt
CPT1

SBHB RECEIVE MASK 0 M
SBMB RECEIVE MASK 1 M
SBMR RECEIVE MASK 2 M
S8M8 RECEIVE MASK l M

115
lil5
"5
0S

1!1044

0045
004b
02147

!110104
011ll0S
0Gllt0b
00107

S8HD
SBHO
SBHA
Sl!HL

M8219
M8219
M8219
H8219

CPTX
CPTX
CPTX
CPTX

BUS MO RYTE 2 PAR M
BUS MO BYTE l PAR M
SBHA BUFFER FULL L
SBLE LATE EXPECT RO

liJ5
05
05
05

0048
00119
0011A
004B

001 U
1110111
00112
0011]

SBHE
SBHE
SBHE
Sl!IME

M8219
M8219
M8219
M8219

CPh
CPTX
CPTX
CPTX

SBLE REC PAR 111 H
SBLE REC PAR I M
SBLE REC PAR 2 M
SBLE REC PAR 3 M

e5
lilS
e5
es

0011C
0040
0011E
004F

0~114

0111115
00llb
Hll7

SBMH
Sl!IMH
SBHM
SBHM

M8219
M82l9
M8219
M82U

CPTX
CPTX
CPTX
CPTX

TR SEL t L
TR SEL 2 L
TR SEL II L
TR SEL 8 L

lil5
lil5
15
15

011150
0051
0052
l!IB5l

lll0l20
0i!lll1
1110122
0012]

SBHR
SBMR
S8HR
SBMR

M8219
M8219
148219
H82l9

CPTX
CPTX
CPTX
CPTX

T!IMN BUF UMCT 0 L
TBMN BUI" UMCT 1 L
TBMN RUF UMCT 2 L
TBHN BUI" UHCT 3 L

es
lil'S
111'5
111'5

00'54

Hl24
111112'5
Hl2b
00127

&BHR
SBHR
SBHM
SBHR

M82l9
H8219
M8219
H82l9

CPTX
CPTX
CPT0
CPTll

TBMN BUF UADS L
TBMN BUF UFS L
SBHM SELECT SRI ADAS L
SBMR TRANS ENABLE L

0""2C
i.!1'120

111042

0043

0055

005b
0057

l!l01i!b5
01111lh
01111110
0l4071l

177

28 M
29 H
30 H
31 M

V-BUS DIRECTORY (CONT)

CHAN

"IT

(MEX)

BIT
(OCTAL)

O~G

MODULE

T,S,

SIGNAL NAME

1115
1115
1115
115

IH!15q
005A
11058

00130
01H31
00132
0Hl33

HMO
SBME
SBHR
SBMM

M821q
"'B21q
"'821'
Me21q

CPTX
CPTX
CPTX
CPTX

TBMO EN Siil OATA L
Sf!'ILE TRANS PAR l
SBLL TRANSMIT CA M
CEMM CUR "'ODE 0 M

1115
15
1115
95

11105C
011150
11105E
lil05F

001311
00135
0013b
lillill37

SBMS
S8M"'
SBHM
S8MX

M821q
M821q
M821'
M&Ztq

CPTX
CPTX
CPTX
CPTX

CLl<L SYS JNIT 8
CEHM CUR MODE 1 M
TP.MN DIS PROT L
RESERVED

1115
15
15
1115

0~U

001110
11101111
1110142
00143

SBMX
SBMX
SBHX
SBHX

M821'
M821q
M821q
Mez1q

CPT>C
CPTX
CPTX
CPTlt

RESERVED
RESERVED
RESERVED
RESERVED

ll'l1411
111111145
H146
00141

SSMX
SBHX
SBHX
SBHX

M821q
M821q
Meztq
M821q

CPTX
CPTX
CPTX
CPTX

RESERVED
RESERVED
RESERVED
RESERVED

0111159
00151
1!1015Z
0111153

SBMX
SBHX
S8HX
SBHX

"'1121 q
M8l1q
Mez1q
M821q

CPTX
CPTX
CPTX
CPTX

RESERVED
RESERVED
RESERVED
RESERVED

HflC

001511

00flE

H155
Ht5fl
01!115'7

SBHX
SBHX
SBHX
SBMX

M8Z1q
MBZ1'
MU1q
MB21'

CPTX
CPTX
CPTX
CPTX

RESERVED
RESERVED
Rf SERVED
RESERVED

•5
115
15
95
115
1115
1115
1115
115
15
15
15

~11158

lill!IU

0063

111111ft4

8065
1!100

0067

111168

00n
HU

0068

0HD
HU'

178

V-BUS DIRECTORY (CONT)

CHAN

'HT
(HEX)

BIT
(OCTAL)

DwG

MODULE

T,S,

SIGNAL NAME

ilo

(111111'10

Ill&
Ill&
0&

1''1"' I

(/1(1'1101'1
01'101111
"'"'"'('12
11\l!llHH

FCTP
FCTP
FCTC
FCTH

M82&9
118289
148289
M8289

CP TX
CPTX
CPTX
CPTX

DAPL •cc RA CONTEXT il ...
DAPL ACC RA CONTEXT 1 M
FCTC CLR RR L
FCTM CP SYNC: M

fll'irl011
l'll'l01l5
0001'1&
"1111007

FNME
FC:TJ
FCTC
FCTC

M8289
M8289
M8289
~8289

CPTX
C:PTX
CPTX
CPTX

nJME BUS ... EXP L
FCTJ ACC: N DATA 1-f
FCTC ACC l DATA M
FCTC ACC V DATA H

OIOll'l!QI
0!111011
01Ai/112
00013

FNMT
FNMT
F"iMT
FNMT

M8289
M8289
M8289
M8289

CPT3
CPT3
C:PB
CPT3

FCTO RA
FCTO RA
FC:TD RA
FCTD RA

ADRS 3
ADRS 2
ACIRS 1
ADRS (/I

Oll<l01il
"1111015
0001&
00017

FlllMT
FlliMT
FlllMT
FlliMT

M8289
M8289
'48289
M8289

C:PT3
CPT3
CPT3
C:PT3

FCTP RB
FCTP RB
FC:TP RB
FCTP RB

ACIRS 3 L
ADRS z L
ADRS 1 L
ADRS 0 L

CPTX
C:PTX
CPTX
CPTX

RESERVED
RESERVED
EALU C: 0 L
FCTE COMPL L

~8289

CPTX
CPTX
CPTX
CPTX

FADA SPC (A) M
Ft.iMS EALU CIN L
FCTC SEL NORM M
RESERVED

FNMT
FNMT
FN"1T
lfNMT

M8288
M8288
M8288
M8288

CPT2
CPT2
CPT2
CPTl

FCTN LOAD
FCTN LOAD
FCTN LOAD
l'CTN LOAD

01'11113&
1"111037

FNMT
FNMT
FNMT
FNMT

M8288
M8288
M8288
M8288

CPT2
CPT0
CPTX
CPTX

FCTN LOAD BR0 M
FADS BUS..,FAD L
RESERVED
RESERVED

FNMT
FNMT
,NMT
FNMT

M8288
M8288
M8288
M82118

CPT1
CPTl
CPT]
CPTl

FCTN FAMX EN 0 L
FCTA A GT B M
FCTN SHF "1UX EN1
'CTN SMI' MU)( EN0

ffN"4T
ffNMT
lfNMT
FNMT

M8288
M8289
M8298
M8288

CPT!
CPTl
CPTt
CPT1

FCTN FALU FUNC sn 2 M
FCTN ff ALU ffUNC SEL 1 M
l'CTN FALU FUNC SEL 0 M
!'CTN ~AMX SEL 1 M

;ilkj(/lfl

1.1,rn:s

0&
Ill&

\llill0il

ioo

11111106
f'1(/lltl7

0e
lrl&
0&
0&
00
h

0e
Ill&
ii&
111&

Irle
0&
0&

0&
"&
ii&

lrlo
00

0~iil'5

11111108
11101"Q

r.10PA
(/lc;1"18
"'~"'c

0<rnD
0~(/IE

1,'!0IOIF
01111'1
(llClll

IA012
0'11J
~rn

11.1

tl"l'S

0u10
l"kll 7

illi'l"121l
"1111021

)( )(X)(

(/lt-1\ll22

FNMT
FN"'T

"'"'"'23
0kl02il
0(1102'5
0klOl2o
''h'I01&!7.

11!111"130
00031

ilO

0018
1110u
0111 A
0018

Irle
lrlo
Ill&
0&

001C
i101 D
001E
0'711F

00031.1

111&
0&
l!o

1110!20
illll21
01/l22

0~1'132

00033

0(111!]'5

0~23

000i10
P!A01.11
01HH12
0il0il3

0021.1
0P2'5
00;?0
0027

0001111
000il'5
01/llllilb
000117

0&
ii&

X)(

FNMT
FNMT
FN"'T
FNMT

M8289
~8289

'18289
M8289

M8289
M8289
M8289

179

AR0 M
AR1 M
AR)( M
BR! M

V-BUS DI RECTORY (CONT)

.,.
h

"•
"•116

,...

011128
00211

flf1115e
111011151

11102'

0111052
01'1P53
1110054

0111213

002c
1:'1021'.1
002E

01112F

01d0'§5
0fl!e56
00051

'NMT
'N'-'T
'NMT
'NMT
FlilMT
FNMT
'NMT
'lilMT

MU29
M9i!28
M8U8
M8228
M822S
1'18228

MSUS
MUH

180

CPT3
CPT3
CPT3
CPT3
CPT3
CPU
CPU
CPTt

'CT' IMF COUNT 5 M
FCTF SHF COUNT 4 M
FCTF SHF COUNT 3 M
FCTF SHF COUNT l M
M
FCTF SH' COUNT
FCTF SHF COUNT
M
'CTN FALU CARRY IN H
FCTN FA!o!ll SfL 0 H

CHAPTER 6
SYSTEM BACKPLANE
INTERCONNECT

SBI CONFIGURATION

ARBITRATION
TR <15:00>
INFORMATION TRANSFER
P < 1 :O> (PARITY)
TAG <2:0> (TAG)
ID <4:0> (IDENTIFIER)
M <3:0> (MASK)

B <31 :OO> (INFORMATION)
RESPONSE
FAULT
TRANSMIT/
RECEIVE
NEXUS

CNF <1:0> (CONFIRMATION)
CONTROL

TRANSMIT/
RECEIVE
NEXUS

UNJAM
FAIL
DEAD
INTLK (INTERLOCK)
CLOCK (6 LINES)
INTERRUPT REQUEST
REQ <7:4> (REQUEST)
ALERT
MP1-2
SPARE (2 LINES)

TK-0077

183

SBI PARITY FIELD CONFIGURATION

l, l

Pl
PO
PARITY
FIELD

ITAGl

\...._...--)
P <1:0>

\...._...--)
TAG <2:0>

MASK
FIELD

~
~

ID <4:0 >

M <3:0>

INFORMATION FIELD

B <31:00>
COMMAND FORMAT

SBI CONFIRMATION
CONF1 CONF2

FUNCTION
FIELD

CONDITION

NO RESPONSE

ACK

BSY

ERR

ADDRESS
FIELD

~'---~~--~~--'

F <3:0>

A <27:00>

TK-0166

184

SBI INFORMATION TRANSFER FORMATS

READ DATA FORMAT
TAG

MASK
ID

JooooJ

DATA BITS

CORRECTED READ DATA FORMAT

MASK
DATA BITS

0 0 0 1j

READ DATA SUBSTITUTE FORMAT
TAG
ID

MASK

0 0 1 0

DATA BITS

INTERRUPT SUMMARY RESPONSE FORMAT
TAG

MASK
DATA

DATA

COMMAND ADDRESS FORMAT FOR READ MASKED
MASK

FUNCTION
ADDRESS BITS

COMMAND ADDRESS FORMAT FOR WRITE MASKED
TAG

MASK

FUNCTION

l· .. .Joo oJ

ADDRESS BITS

185

SBI INFORMATION TRANSFER FORMATS (CONT)

COMMAND ADDRESS FORMAT FOR INTERLOCK READ MASKED
TAG

MASK

FUNCTION
ADDRESS BITS

COMMAND ADDRESS FORMAT FOR INTERLOCK WRITE MASKED
TAG

MASK

FUNCTION
ADDRESS BITS

COMMAND ADDRESS FORMAT FOR EXTENDED READ
MASK

l-- - -

FUNCTION

o o oj

ADDRESS BITS

COMMAND ADDRESS FORMAT FOR EXTENDED WRITE MASKED
TAG

IP 1 Polo 1 1 j

MASK

FUNCTION

I· ·l o j
1

ADDRESS BITS

1 1

WRITE DATA FORMAT
MASK

TAG

I· ·I

BYTE 3

BYTE 2

BYTE 1

BYTE 0

INTERRUPT SUMMARY READ FORMAT
MASK

TAG
ID

0000

000000000000000000000000

0 0 0 0
'--y--'
REQ <7:4>

186

SBI FIELD DESCRIPTION

Field

Description

Arbitration Group
Arbitration Field
[TR (15:00)]

Establishes a fixed priority among nexus for access to
and control of the information transfer path.

Information Transfer
Group
Information Field
[B (31:00)]

Bidirectional lines that transfer data, command/address, and interrupt information between
nexus.

Mask Field
[M (3:00)D]

Primary function: encoded to indicate a particular byte
within the 32-bit information field [B (31 :00)].
Secondary function: in conjunction with the tag field,
indicates a particular type of read data.

Identifier Field
[ID (4:0)]

Identifies the logical source or destination of information contained in B (31:00).

Tag Field
[TAG (2:0)]

Defines the transmit or receive information types and
the interpretation of the content of the ID and information fields.

Function Field

[F (3:0)]

Specifies the command code, in conjunction with the tag
field. This field is part of the 32-bit information field.

Parity Field
[P (1:0)]

Provides even parity for all information transfer path
fields.

Response Group
Confirmation Field
(CNF(l:O)]

Encoded by a receiving nexus to specify one of four response types and indicate its capability to respond to the
transmitter's request.

Fault Field
(FAULT)

A cumulative error line to the CPU that indicates one of
several errors stored in the transmitting nexus fault register, and the associated SBI cycle in which the error
occurred.

187

SBI FIELD DESCRIPTION (CONT)

Field

Description

Interrupt Request
Group
Request Field
(REQ (7:4)j

Alert Field
(ALERT)

Allows a nexus to request an interrupt to service a condition requiring CPU intervention. Each request line
represents a level of nexus request priority.
A cumulative status line that allows those nexus not
equipped with an interrupt mechanism to indicate a
change in power or operating conditions.

Control Group
Clock Field
(CLOCK)

Six control lines that provide the clock signals necessary
to synchronize SBI activity.

Fail Field
(FAIL)

A single line from the restart nexus to provide a restart
signal to the CPU to initiate a system restart operation.

Dead Field
(DEAD)

A single line to the CPU to indicate an impending clock
circuit or SBI terminating network power failure.

Unjam Field
(UNJAM)

A single line from the CPU to attached nexus that initiates a restore operation.

Interlock Field
(INTLK)

A single line that provides coordination among nexus
responding to certain read/write commands to ensure
exclusive access to shared data structures.

188

CONSOLE
(PHYSICAL ADDRESS)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

SBI ADDRESS

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

I1 I 0
TRI
(Base HI)

SBI
Address
(Hex)

20000000

8000000

20002000

8000800

20004000

8001000

2001116000

8001800

20008000

8002000

2000A000

800281110

200111c000

8003000

Physical
Address
(Hex)

2000E000

8003800

20010000

8004000

2001200('1

8004800

20014000

800511100

2001600111

8005800

20018000

8006000

2001A000

8006800

2001c000

8007000

2001E000

8007800

TR#I

x x

en
<
m !:E
0

-t .::::.
0 0

:a :a
C)

z
m tii

-t
:a m
l> :a
:::! l>

z cc

SBI Device vector Generation

0
11
LEV
LEV
LEV
LEV

REQ/BR
LEVEL
0 0

TR NO.

I I

l>
01

-t
m

:a
:a

c"ti
-t

SBI FAULTS (ADAPTER CONFIGURATION REGISTER)

NEXUS TYPE CODE

WSO ISO XMT
FLT FLT FLT
31
30
29
28
27
26

PARITY FAULT

WRITE SEQUENCE FAULT
UNEXPECTED READ DATA FAULT
INTERLOCK SEQUENCE FAULT
MULTIPLE TRANSMITTER FAULT
TRANSMITTER DURING CYCLE THAT

CAUSED FAULT
POWER DOWN

22
21

POWER UP
OVER TEMPERATURE

0 0 0 X X X X X MEMORY
0 0 1 0 0 0 0 0 MBA
0 0 1 0 1 0 0 0 UBA 0
00101001
1
00101010
2
00101011
3
OlOOOOYY* MA780
0 0 1 1 0 0 0 0 DR 780

*YY =PORT NUMBER

TK-0695

190

SBI CONFIGURATION RULES FOR TR SELECTION

The following rules are suggested for selecting TR levels for
NEXUS on the SBI.
They apply to VAX-11/780 and VAX-11/782
systems.
These rules are guidelines; deviation may be desirable
and, in some cases, necessary.
1.

The TR level of a device determines its relative priority in
competing for SB! access.
High TR levels mean low priority.
TR 1 is the highest priority and TR 15 the lowest to which any
NEXUS (other than the CPU) may be assigned.

The standard order of assigning devices to TR levels is:
0

0
0
0
0
0
0

All MS780s
All MA780-Cs
All DW780s
All RH7B0s
DR780
CI780
CPU

The default
are:

assignments

currently

First MS780
First MA780 port
First DW780
First RH780 (for disks)
Second RH780 (for tapes)
DR780
CI780
CPU

TR
TR
TR
TR
TR
TR
TR
TR

used

manufacturing

2
3
8
9

13
14
16 (the implied TR level)

These defaults should cover most VAX-11/780 systems.
systems, as well as some applications, will require
changes to TR levels.

Large
field

When selecting TR levels for complex systems, you should try
to minimize latency effects (such as data lates) in memory
access.
Therefore, always give memory controllers the lowest
TR levels and assign the CPU to TR 16.
RH780s and DW780s for
peripheral devices should be assigned TR levels based on the
sensitivity of the devices (or device controllers) to memory
latency.
3.

One to two MS780s per system.
Interleaving with MS780s
requires consecutive TR levels as well as equal amounts of
memory in the even/odd pair; consecutive TR levels are
strongly suggested even without interleaving.
When a MS780-A
and MS780-C controller reside on the same system, the MS780-C
should be assigned the lowest TR level.

Zero to four MA780-Cs per system.
TR levels must be
consecutive.
A given MA780 must have the same TR on all SBis.
MS780 memory controllers should always have lower TRs than
MA780-C memory ports.

One to four DW780s per system.

191

SBI CONFIGURATION RULES FOR TR SELECTION (CONT)

Zero to four RH780s per system.
In general, RH780s used for
dis ks should have higher priority than RH780s used only for
tapes.
The main criterion for allocating devices to RH780s
and RH780s to TRs is the relative sensitivity of the device to
memory latency.
Since the RH780 has less than one disk sector
of buffering, the memory latency requirement is determined
(slightly pessimistically) by the device data rate:
RP07 at 2.2 Mbyte/sec
RP07 at 1. 3
RM03, RM05, RM80
RP04/5/6
TU78 at 6250 BPI
TU77 at 1600 BPI
TE16 at 1600 BPI

3.64 microsec/quadword
6.15 microsec/quadword
6.67 microsec/quadword
10.00 microsec/quadword
10.24 microsec/quadword
40.00 microsec/quadword
>100.00 microsec/quadword

These figures define the average response time requirement as
seen from the device.
Due to RH780 buffering, RH780 devices
can withstand an occasional memory response time of nearly
three times the average figure just given without causing a
data late.
The RP07 at 2.2 megabytes per second requirement is high
enough that only interleaved MS780 memory can be used.
It is
not expected to function on a VAX-11/782 or a VAX-11/780 with
MA780 unless the application prevents RP07 I/O from accessing
the MA780 address space.
In determining the TR level for RH780s with more than one type
of device, only the memory response time requirement of the
fastest device on the RH780s needs to be considered.
7.

Zero to one DR780 per system.
It is suggested that DR780
pairs that are used to interconnect VAX-11/780 systems use the
same TR assignment in each VAX-11/780.
The data rate of the DR780 may be set as low as 156 kilobytes
per second or as high as 8 megabytes per second depending on
the attributes of the connected device.
156 kilobytes per
second is slower than a TU77, while 8 megabytes per second is
faster than any current VAX-11/780 memory will support.
Since the DR780 is synchronous and not fully buffered, it may
experience data !ates.
The only solutions are faster
(interleaved) memory, prevention of concurrent I/O from other
devices on the SB! (usually not practical), and decreasing the
DR780 data rate setting.

One CI780 per system.
It is suggested that for a CI network,
the same TR level be assigned to each CI780.
The CI780 is synchronous and fast (8. 75 megabytes per second
peak), but it is fully buffered.
Therefore, CI780 should have
the highest TR number (lowest priority) of any device other
than the CPU.

One CPU.
Only one CPU per SB! is supported, and it must be at
(implied) TR 16.

192

SBI CONFIGURATION RULES FOR TR SELECTION (CONT)

HJ. These

TR selection rules are mainly useful when configuring
VAX-11/7812! and VAX-11/782 systems with many fast peripheral
devices.
On systems with little I/O activity, the SBI and
memory will be so lightly loaded that TR selection has little
importance. On the other hand, when the memory demand greatly
exceeds the capacity of the SBI and the memory, TR selection
will not make the memory cycle faster.
TR selection is important for any system with aggregate
bandwidth of concurrently active DMA devices above two
megabytes per second.

11. If you run out of TR levels, you need another VAX-11/7812!.
12. The following example illustrates these guidelines for a large
VAX-11/7812! system consisting of:
two MS7812!-Cs, two MA7812!-Cs,
two DR7812!s, three RH7812!s, and one CI7812!.
Device
MS7812!-C
MS7812!-C
MA7812!-C
MA7812!-C
DW7812!
DW78f2!
RH7812!
RH7812!
RH7812!
CI7812!

TR
2
3

4
5
6

8
9

112!
14

193

.i::.

Al
A2
Bl
B2
Cl
C2
Dl
D2
El
E2
Fl
F2
Hl
H2
Jl
J2
Kl
K2
Ll
L2
Ml
M2
Nl
N2
Pl
P2
Rl
R2
Sl
S2
Tl
T2
Ul
U2
Vl
V2

+ 5 v
BUS SB! BOO L

+ 5 v

BUS SB! BOl L
GND
BUS SB! B02 L

+ 5 v
BUS SB! B20 L

BUS SB! DEAD L
+ 5 v
BUS SB! MO L

+ 5 v
BUS SB! REQ4 L

BUS SBI INTLK
+ 5 v
BUS SBI TROO

BUS SB! B21 L
GND
BUS SB! B22 L
BUS SB! B23 L

BUS SB! Ml L
GND
BUS SB! M2 L
BUS SB! M3 L

BUS SB! REQ5 L
GND
BUS SB! REQ6 L
SB!
REQ7 L
BUS

BUS SBI TROl
GND
BUS SBI TR02
+12 v
BUS SBI TR03

BUS SBI B03 L

GND

BUS SB! Bl2
GND
BUS SB! Bl 3
BUS SBI Bl4
BUS SB I Bl 5

L
GND
L
L
L

+12 v
BUS SBI BOB L
GND
BUS SBI B09 L
BUS SBI BlO L
BUS SBI Bll L
+ 5 v

BUS SBI TP H
BUS SB! TP L
GND
BUS SB I PCLK H
BUS SBI PCLK L
BUS SB I PDCLK H
- 5 v
BUS SB! PDCLK L

BUS SB I TR04
GND
BUS SBI TR05
BUS SBP TP06
BUS SBI TR07

z
)>
r-

.en

(")
~

-0

m
~

BUS SB! TAGO L

BUS SBI MPl L

BUS SBI TR08

GND

BUS SBI B25 L
GND
BUS SBI B26 L
BUS SBI B27 L

BUS SBI TAGl L
GND
BUS SBI TAG2 L
BUS SB I IDO L

BUS SBI MP2 L
GND
BUS SBI UNJAM L
BUS SBI ALERT L

BUS SBI TR09
GND
BUS SBI TRlO
BUS SB I TRll

BUS SBI Bl6 L
GND
BUS SBI Bl7 L
BUS SB I B18 L
BUS SBI Bl9 L
+ 5 v

BUS SBI B28 L
GND
BUS SBI B29 L
BUS SB I B3 0 L
BUS SBI B31 L
+ 5 v
BUS SBI FAIL L

BUS SBI IDl L
GND
BUS SBI ID2 L
BUS SB I ID3 L
BUS SBI ID4 L
+ 5 v

BUS SBI CNFO L
GND
BUS SBI CNFl L
BUS SBI FAULT L

BUS SBI TR12
GND
BUS SBI TR13
BUS SBI TR14
BUS SBI TRl 5
+ 5 v

+ 5 v

BUS SB! B24 L

BUS SBI B04 L
BUS SBI BOS L
GND
BUS SBI B06 L
BUS SB I B07 L

BUS SB I PO L
GND
BUS SB! Pl L
BUS SB! SPARE
BUS SB! SPARE

CHAPTER 7

SBINEXUS

&
CONSOLE ADDRESS

20002000

3:
m
3:
0

FAULT CONDITIONS

:J:I

(")

BUS PARITY ERROR
INTERLEAVE STATUS (WRITABLE)
1000= NON-INTERLEAVED
001 =TWO-WAY INTERLEAVED)

WRITE DATA SEQUENCE FAULT
TRANSMIT FAULT (SET TO A "1" IF MEMORY----+--+-'
WAS A TRANSMITTER DURING A FAULT)
MULTIPLE TRANSMITTERS ON BUS
INTERLOCK SEQUENCE FAULT

POWER UP ALERT
("1" INDICATES POWER UP;
WRITE "1" TO CLEAR THIS BIT)

INTERLEAVE ENABLE.
(WHEN WRITING TO INTERLEAVE
BITS <00:02>, THIS BIT MUST BE
SET TO "O"; FOR AN SBI DATA
TRANSFER, IT IS SET TO "1".)

POWER DOWN ALERT
("1" INDICATES POWER DOWN ALERT;
WRITE "1" TO CLEAR THIS BIT)
TABLE A 4K CHIP

.....

11
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

09
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

MEMORY ARRAY SIZE
64K BYTE
12BK BYTE
192K BYTE
258K BYTE
320K BYTE
364K BYTE
448K BYTE
512K BYTE
576K BYTE
640K BYTE
704K BYTE
768K BYTE
832K BYTE
896K BYTE
960K BYTE
1024K BYTE

& SINGLE CONTROLLER WITH TR LEVEL= 1
& THESE BITS ARE USED ONLY BY MEMORY
CONTROLLERS NOT HAVING A ROM BOOTSTRAP
MEMORY TYPE
0

0
1
1

1
0
1

ERROR CONDITION; NO ARRAY
BOARDS PLUGGED INTO BACKPLANE
4K MOS
16K MOS
ERROR CONDITION; BOTH 4K AND 16K
BOARDS PLUGGED INTO BACKPLANE

TABLE B 16K CHIP
14
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

13
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

12
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

MEMORY ARRAY SIZE
256K BYTE
512K BYTE
768K BYTE
1024K BYTE
1280K BYTE
1536K BYTE
1792K BYTE
2048K BYTE
2304K BYTE
2560K BYTE
2B16K BYTE
3072K BYTE
3328K BYTE
35B4K BYTE
3840K BYTE
4096K BYTE

0
2

"Tl
C)

:J:I

:::!
0
2

:J:I

(ii
-f

:J:I

s:
s:

:xJ

(")

WRITABLE STARTING ADDRESS
FOR THE MEMORY CONTROLLER
CONSOLE ADDRESS

20002004

! ii~~~

COUNTER
FILE
WHEN WRITING INTO BITS <27 15>
READ
BIT 14 SHOULD BE A "1" DURING
COUNTER SBI DATA TRANSFER INTO
THE MEMORY

ENABLE WRITE TO
STARTING ADDRESS-------------~

~i;;~~~~AYS 0

&
13

1
0

1
1

o er

"Tl
G')

:xJ

)>
' - - - - - - - - E C C BYPASS BIT
WRITE "1" TO BYPASS ECC
WRITE "O" TO CLEAR THIS BIT
~-------FORCE ERROR AT A PREDEFINED ADDRESS
WRITE "1" TO FORCE ERROR
WRITE "O" TO CLEAR THIS BIT
~--------REFRESH BIT

:j
0

:xJ

G')

en
m

~~~l~~iz1NG

-I

& BATTERY
BACKUP STATUS

:xJ
CXJ

INIT. STATUS
COLD START
IN_z._IN PROGRESS
INZ COMPLETE
VALID DATA
IN MEMORY
ILLEGAL STATE

& STARTING
ADDRESS IS ON 64K BYTE
BOUNDARIES
*MUST BE 0 FOR MS780C

35:
m
35:
0
:c

MEMORY ADDRESS IN ERROR
CONSOLE ADDRESS
2000200B

ARRAY BANK IN ERROR
"O" LOWER BANK
"1" UPPER BANK

WORD IN ERROR
"O" LOWER WORD
"1" UPPER WORD

::!
0

ERROR LOG SERVICE-----'
REQUEST FLAG
"1" SERVICE REQUEST
ARRAY BOARD
WRITE "1" TO CLEAR
IN ERROR
27
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

z.,,

HIGH ERROR RATE IN
MEMORY FLAG
"1" HIGH ERROR RATE
INDICATION
WRITE "1" TO CLEAR THE
FLAG

co
co

4K CHIP ADDRESS IN ERROR
(SEE NOTE 5 FOR 16K CHIP
MEMORY ADDRESS IN ERROR)

INHIBIT CRD (CORRECTED READ
DATA) PASS
WRITE "1" TO INH CRD TAGS
WRITE "O" TO CLEAR THIS BIT

26
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

25
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

24
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

BOARD
BOARD 1
BOARD 2
BOARD 3
BOARD 4
BOARD 5
BOARD 6
BOARD 7
BOARD B
BOARD 9
BOARD10
BOARD 11
BOARD12
BOARD13
BOARD14
BOARD15
BOARD16

& EVEN# SYNDROME BITS; DBE
ODD# SYNDROME BITS; SBE
THE ERROR SYNDROME BITS ARE INVALID
UNLESS THE ERROR LOG SERVICE REQUEST BIT
(BIT 2B, REG 0) IS SET TO A "1".

& REGISTER C, BITS <22:09> ARE

16K CHIP ADDRESS IN ERROR.
BIT <23> IS THE ARRAY BANK
IN ERROR (0 IS LOWER BANK & 1
IS THE UPPER BANK)
THE MEANING FOR ALL OTHER
BITS IN REGISTER C IS SAME FOR
4K & 16K CHIPS.

NOTE: WHEN INSTALLING AN MS7BOA & MS7BOC
ON THE SAME 11/780, THE MS7BOC SHOULD
HAVE THE LOWEST TR.

m
C)

(I)

-t
m

MEMORY ARRAY ADDRESSES

Array

M8211
Size

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

64
128
192
256
320
384
448
512
576
640
704
768
832
896
960
1024

K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

Address Range

M82llll
Size

0- FFFF
101'100-lFFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
5001'10-5FFFF
60000-fiFFFF
70000-7FFFF
80000-8FFFF
90000-9FFFF
A0000-AFFFF
80000-BFFFF
C0000-CFFFF
00000-DFFFF
E0000-EFFFF
F0000-FFFFF

256
512
768
1024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096

Address Range
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

Memory Starting Address Jumpers
Boundary Address
0
4 MEG

8 MEG
12 MEG

000000
400000
800000
C00000

200

0- 3FFFF
40000- 7FFFF
80000- BFFFF
C0000- FFFFF
100000-13FFFF
140000-17FFFF
180000-lBFFFF
1C00 0 0- lFFFFF
200000-23FFFF
240000-27FFFF
280000-2BFFFF
2C0000-2FFFFF
300000-33FFFF
340000-37FFFF
380000-3BFFFF
3C0000-3FFFFF

b
W6

d
c

n
m

v
u

bb
aa

dd
cc

ff
ee

IRD

nn
mm

rr
pp

tt
SS

vv
uu

MS780 Configuration
for REV A Backpanel

TR8

TR 1

(I)

.....

W9 Wl0 Wll Wl2

SAl
Wl

Configuration for
REV -- Backpanel

0
2

"T1

Wl0 Wll Wl2

:::D

TR Arbitration
Level

(\.)

Inhibit ROM
Decode

Signal
Name

TR
SEL
8

TR
SEL
4

TR
SEL
2

TR
SEL
1

TRt

Wl0

Wll

Wl2

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15

:::::!
0
2
"T1

0
Wire Wrap
F20 K2 to
F20
F20
F20
F20
F20
F20
F21il
F20
F20
F20
F20
F20
F20
F2fl
F20

Cl
Dl
El
F2
H2
Jl
J2
Ml
Nl
Pl
P2
S2
T2
Ul
U2

W8=I

W8=--

No response 2
confirmation
for Read to ROM
Address Space
1
Read to ROM
Address Space
receive Normal
confirmation

NOTES:
When installing an MS780A
1.
and MS780C on the same VAX-11/780
system, the MS780C should be the
first memory (i.e. I have the
lowest TR) •
The memory with the ROM boot2.
strap must be at TRl.

:::D
:::D

<
::c

IXJ
)>

"ti

Starting Address

w
0
4 Mega Byte
8 Mega Byte
12 Mega Byte
Wl-W5 Spare

- Standard for Memory
- Standard for Memory 2

MS780A MODULE UTILIZATION

Mfl214 MSB

M8213 MCN

M8212 MDT

M8211 MAY

M8211 MAY
M9040 TRM

* When not installed,

use blank module 7014103.

202

MS780C MODULE UTILIZATION

M8214 MSB

M8213 MCN

M8212 MDT

M8210 MAY

M8210 MAY
M8210 MAY
M8210 MAY

M8210 MAY

*
*
*
*
*
*
*
*
*
*
*
*
*
*

M9040 TRM

*
* When not installed, use blank module 7014103.

203

MSBA, P,U
SBI TRANCEIVERS

MSBU REC
TAG (2o01

FROM
MCNT

MSBP

MSBD DST ROM,
MSBA BIT REC 127101
FROM
CNFG
REG B

CNFG REG, ARY

COMMAND
FILE

MSBU L REC MSK 13001
MSBU L REC BIT 131 001

BUS FL INF 131 001. MSK 13001
MSBU L DST ROM, CNFG·REG, ARY
MSBA REC BIT 127 001

MSB REC BIT 131 161
MSBD MUX REC BIT 1150001

MSBU L WR, EXT

MCNP ST ADR 120 141

MSBF,P

BUS AC/DC LO

BUS SBI PCLK, TP
MAY IN 1150001 FROM
----MEMORY
ARRAY

BUS SBI TR 115 001
BUS TR
TR SEL B,4,2,1

MSBM

DRIVERS

TO
MEMORY
TIMING &
CONTROL
LOGIC

....

MDTD,P
TAG

MDTD XMT TAG 110)

TAG
GEN

MCNE ARY ADA I 15•01)

MCNEARY ADA 119•15)
MCNM,N

BUS FL INF

i'J

MDT
A,B,C

BUS FL INF

MEMORY
ARRAY

BUS MOS DAT IC7:COI

U'1

BUS MOS DAT
I U31: UDO, L31: LOOI

BUS FL INF

BUS FL INF 13UJOI

BUS FL INF 131 :00)
BUS MOS DAT IL31:LOOI

MEMORY 1/0 DATA LOGIC

BUS FL INF 131 001
CJ)

MCNB MUX EN 1 L

~
z

;:
<(

CNFG
REG

~,___ _B_U_S_F_L_IN_F~----

u::
CNFG
REG

l/ODATAMUX
STB
CNFG
REG

CNFG REG C

STATUS-------SIGNALS

FROM
MCNE MEM ADR 19 0)
AO DRESS
REGISTER

BOOTSTRAP MCNL ROM DAT (3100)
ROM
ENB

MCNA ROM EN L

206

OUTPUT
REGA
REG B
REG C
ROM BOOT

UBA ADDRESS SPACE AND C/A FORMAT

SBI C/A Format for UBA Register Access

10
MASK

FUNC

<30>

<3 O>

Base A ddresses
TR
Num
Base 10
I

2
3
4
5
6
7

Base
Address
(Physical
hex)

SBI
Address
(hex)

TR
Num
Base IO

Base
Address
(Physical
hex)

SBI
Address
(hex)

20002000
20004000
20006000
20008000
2000AOOO
2000COOO
2000EOOO

8000800
8001000
8001800
8002000
8002800
8003000
8003800

8
9
10
II
12
13
14
15

20010000
20012000
20014000
20016000
20018000
2001AOOO
2001COOO
2001EOOO

8004000
8004800
8005000
8005800
8006000
8006800
8007000
8007800

llBA
Reg
CNFGR
UBACR
UBASR
DCR
FMER
FU BAR
FMER
FU BAR
BRSVRO
BRSVR I
BRSVR2
BRSVR 3
BRRVR4
BRRVR5
BRRVR6
BRRVR 7
DPRO
DPR I

Byte
Address
(Physical
hex)
000
004
008

ooc

010
014
018
OIC
020
024
028
02C
030
034
038
03C
040
044

SBI
Address
(hex)
000
001
002
003
004
005
006
007
008
009
OOA
OOB

ooc

OOD
OOE
OOF
010
011

207

llBA
Reg

Byte
Address
(Physical
hex)

SBI
Address
(hex)

DPR 14
DPR 15
Reserved

078
07C
080

OIE
OIF
020

Reserved
MRO
MR I

7EC
800
804

IFF
200
201

MR494
MR495
Reserved

FB8
FBC
FCO

3EE
3EF
3FO

Reserved

FFC

3FF

UBA REGISTERS

UBA STATUS REGISTER, BIT CONFIGURATION
31

27262524

10 9 8 7 6 5 4 3 2 1 0

BRRVR 6 FULL
BRRVR 5 FULL
BRRVR 4 FULL
READ DATA TIMEOUT
READ DATA SUBSTITUTE
CORRECTED READ DATA
COMMAND TRANSMIT ERROR
COMMAND TRANSMIT TIMEOUT
DATA PATH PARITY ERROR
INVALID MAP REGISTER
MAP REGISTER PARITY FAIL
LOST ERROR BIT
UNIBUS SEL TIMEOUT
UNIBUS SSYN TIMEOUT
TK-0121

UBA DIAGNOSTIC CONTROL REGISTER, BIT CONFIGURATION
UNUSED

SPARE

UNUSED

,A--...

UNUSED

~
8 7
1615

SAME AS CONFIGURATION REGISTER BITS <23:00>
MICROSEQUENCER OK

DISABLE DEFEAT
INTERRUPT DATA
PATH
PARITY
DEFEAT
MAP
PARITY

TK-0055

208A

UBA REGISTERS

UBA CONFIGURATION REGISTER, BIT CONFIGURATION

313029282726

76543210

2322

UNIBUS ADAPTOR CODE
UNIBUS INIT COMPLETE
UNIBUS POWER DOWN
UNIBUS INIT ASSERTED
ADAPTOR POWER UP
ADAPTOR POWER DOWN
TRANSMIT FAULT
MULTIPLE TRANSMITIER FAULT
INTERLOCK SEQUENCE FAULT
UNEXPECTED READ DATA FAULT
WRITE SEQUENCE FAULT
PARITY FAULT
TK-0119

UBA CONTROL REGISTER, BIT CONFIGURATION

31 3029282726

6 5 4 3 2 1 0

4 3 2 1 0

'--v---1

MAP REGISTER
DISABLE BITS

INTERRUPT FIELD SWITCH
BR INTERRUPT ENABLE
UNIBUS TO SBI ERROR INTERRUPT ENABLE
SBI TO UNIBUS ERROR INTERRUPT ENABLE
CONFIGURATION INTiERRUPT ENABLE
UNIBUS POWER FAIL
ADAPTOR INIT
TK-0120

208

UBA REGISTERS (CONT)

UBA FAILED MAP ENTRY REGISTER, BIT CONFIGURATION

9 8

UNUSED

MAP REGISTER NUMBER
TK-0056

UBA FAILED UNIBUS ADDRESS REGISTER, BIT CONFIGURATION

16 15

UNUSED

FAILED UNIBUS TO SBI ADDRESS
UNIBUS ADDRESS BITS <17:02>
TK-0057

UBA BUFFER SELECTION VERIFICATION REGISTER, BIT CONFIGURATION

16 15
UNUSED

TEST DATA
TK-0054

NOTE:
THE INFORMATION FOUND IN THESE REGISTERS
IS MEANINGFUL ONLY IF A CORRESPONDING
ERROR BIT IS FOUND IN THE UBA STATUS
REGISTER.

209

UBA REGISTERS (CONT)

UBA BR RECEIVE VECTOR REGISTER, BIT CONFIGURATION

31 30 29 28 27 26 25 24 23 22 212019 18 17 16 1514 13 12 1110 09 08 07 06 0504 03 02 01 00

1~1111111111111111111111111111111
ADAPTOR INTERRUPT REQUEST INDICATOR
UNIBUS DEVICE INTERRUPT VECTOR

UBA DATA PATH REGISTER, BIT CONFIGURATION

2423

16 15

UNUSED

BUFFER DATA
NOT
PATH
EMPTY FUNCTION

BUFFER STATE BITS

BUFFERED UNIBUS ADDRESS (2-17)

BUFFER
TRANSFER
ERROR
TK-0053

UBA MAP REGISTER, BIT CONFIGURATION

27 26 2524

3130

212019

S Bl PAGE ADDRESS
AND
ZERO
MAP
REGISTER
VALID BIT

BYJT
OFFSET
BIT
DATA
LONGWORD
PATH
ACCESS
DESIGNATOR
ENABLE
ADDRESS
BIT 27
1/0 DESIGNATOR
TK-0052

210

b
Wl

d
c

j
h

n
m

v
u

bb
aa

dd
cc

ff
ee

11
kk

jj
hh

nn
mm

rr
pp

tt
SS

DW780 Configuration
for REV A Backpanel

vv
uu

CIO
0
Configuration for
REV -- Backpanel

Signal
Name

I'..)

TR#

UNIBUS Address
Space Select

USIC
TR
SEL
A
L

USIC
TR
SEL
B
L

USIC
TR
SEL
L

USIC
TR
SEL
D
L

1
2

:-et:-3

4
5
6
7
R
9

11
12
13
14
15

"ti

Signal
Name
Wire Wrap
D01R2 to
F01Cl
F01Dl
FIZll El
F01F2
F01H2
F01Jl
F01J2
F01Ml
F01Nl
F01 Pl
F01P2
F01S2
F01T2
F01Ul
F01U2

Adapter#

USID
Adapter
0
L

USID
Adapter
1
L

m
r-

c...

s:
"ti

::c

"T1
C)

Interrupt Level
Selection
Signal Name

!SR#

* Normal for first DW780

m
)>

wrn Wll Wl2 Wl3 Wl4

TR Arbitration
Level

:E
....

wrn Wll Wl2 Wl3 Wl4 WlS

4
5
6
7

::c

UAIF
SB!
PR!
JMP
0
L

UAIF
SB!
PR!
JMP
l
L

aU , ;: ;. ri),io
J~·-t:::h /()..~.
\I

~
0

SBI TO UNIBUS CONTROL ADDRESS TRANSLATION

SBI COMMAND ADDRESS FORMAT
3

0 31
MASK
<3:0>

0
LONG WORD ADDRESS
UBA UNIBUS
ADDRESS DECODE
UBA NUMBER
b a

UNIBUS
CONTROL
AND
BYTE ADDRESS
ENCODER

UBAO - - 0
UBA 1 - - 0
__ 1
UBA 2
__ 1
UBA 3

0
1
0
1

CONTROL
1 0

UNIBUS
ADDRESS
17

c <1:0>

2 1 0

UNIBUS ADDRESS BITS <17:02>

UA <17:00>

J
TK-0049

212

UNIBUS TO SBI ADDRESS TRANSLATION

UNIBUS CONTROL ADDRESS

BYTE WITHIN PAGE

MAP REG NUMBER

MAP
REG

r-----------. NUMBER
UNIBUS TO SBI
ADDRESS
TRANSLATION
MAP

0
1

2
3
4
5
6

-SBI PAGE ADDRESS-..-----'
(PAGE FRAME NUMBER)
(21 BITS)
494

495

SBI COMMAND ADDRESS

27
MASK

FUNG

SBI PAGE ADDRESS (PFN)

213

0
LONG WORD ADD

ADDRESSES AND VECTORS FOR UNIBUS DEVICES

UBA No.

Device

UNIBUS
Address
(Octal)

VAX-11/780
Physical Address
(Hex)

CRll
DRllB/DRllW
DMCll/DMRll
DZll
KMCll
LPll 0
LPll 1
LPll 2
LPll 3
LP All
RK711
RL211

777160
772410
Float
Float
Float
777514
764004
764014
764024
770460
777440
774400

2013FE70
2013F508

Floating
NOTE:
convention.

addresses

230
124
Float
Float
Float
200
170
174
270
Float
210
160

2013FF4C
2013E804
2013E80C
2013E814
2013Fl30
2013FF20
2013F900

and

vectors

214

are

Vector
(Octal)

according

PDP-11

FLOATING VECTORS AND FLOATING ADDRESSES

Floating vectors
(Start at 300 and Proceed Upwards)
Device

Vector Size

DCll
DLll-A,-B
DPll
DMll-AA
DNll
DMll-BB
DRll-A
DRll-C
PA611 Reader
PA611 Punch
LPDll
DTll
DXll
DLllC,D,E
DJll
DHll
GT40
LPSll
DQll
KWll-W
DUll
DUPll
DVll-Data
DVll-Modem Control
LKll-A
DWUN
DMC-11
DZll
DWR70
LPPll
VMV21
VMV31
VTV01
KMCll
RLll/RLVll***
RX02
TSll
LPAll-K
IP11/IP300
DMPll-AD

10
10*
10
10*
4
4
10
10
4
4

10*
10*
10*
10*
10**
HI

30*
10**
10*
10*
10*
10*
4

The vector for the device of this type must always be on a
(10) octal boundary.
(No switch or jumper connection for
vector bit 2.)

The device can have either a M7830 or M7821 interrupt control
module.
However,
it should always be on a
(10) octal
boundary.

*** Only for second or later device.

215

FLOATING VECTORS AND FLOATING ADDRESSES (CONT)

Floating Addresses
(Default Address If Nothing Precedes it)

Rank

Device

Address
(Octal)

2
3
4
5
6
7
8
9
10
11
12
13
14
15

DJll
DHll
DQll
DUll
DUPll
LKll-A
DMC 11/DMR11
DZll
DWR70
LPPll
VMV21
VMV31
KMCll
RLl l/RLVll **
DMPll

760010
760020
760030
760040
760050
760060
760070
760100
760110
760120
760130
760140
760150
760160
760170

VAX-11/780*
Physical Address
(Hex)
2013E008
2013E010
2013E018
2013E020
2013E028
2013E030
2013E038
2013E040
2013E048
2013E050
2013E058
2013E060
2013E068
2013E070
2013E078

This address applies to the UBA at TR3.

** Only for second or later device.
NOTE:
Floating register space begins at address 760010.
One
8-byte (10 octal) gap must be left for every device type with
floating registers that is not present.
In addition, an 8-byte
gap must be left after the registers for each device type that is
present.
Register alignment requirements must be preserved.

216

UNIBUS CONFIGURATION

K
K;
~

i.~

DEVICE

~
~

A00-17 (ADDRESS)

D00-15 (DATA)

....

CO-C1 (CONTROL)
MSYN (MASTER SYNC)

SSYN (SLAVE SYNC)
PA-PB (PARITY)
~

UBT

UBA
--

BR4-7 (BUS REQUEST)
BG4-7 (BUS GRANT)

l"9'"

NPR (NONPROCESSOR REQUEST)
NPG (NON PROCESSOR GRANT)
l"9'"

SACK (SELECTION ACKNOWLEDGE)
~

....

INTR (INTERRUPT)
BBSY (BUS BUSY)

INIT (INITIALIZE)

AC LO (AC LINE LOW)
DC LO (DC LINE LOW)

TK-0085

217

UMDM8272

USI M8270
REO <7 4>
RCV MASK
SBI B <31 00>
SBI MASK <3 O>
SBI TAG <2 O>
SBI ID <4 O>
SBI TR <15 OO>
SBI REO <3.0>
SBI UNJAM
SBI DEAD
SBI INTERLOCK

SBI OEAD
UNJAM

( X)

U BAITSEL
UBA
MICRO
OMA ATT SEL
CONTROL
LOGIC
SBI DEAD. UNJAM ' - - - - - - '
SB SEL

UCB MB271

OMA
OPERATION
DECODE
UNIBUS OCLO

SBI

-f !:!?
:I:

UNIBUS
INTERFACE

INTERFACE

.,,

m 3:

c !:

DMA TRANSFER
FROM A
UNIBUS DEVICE
SBI
RECEIVE
LOGIC

MAP REGISTER STATE

"T1

BDP STATE
(UMD)

TRANSMIT
CONFIRMATION
LOGIC

1---------~~~~TENTIONI-'------,
FAULT
LOGIC

CD
)> "T1

IUAI)

DMA ATTENTION
LOGIC
(UCB)
UNIBUS

"T1

PRE FETCH
ATTENTION
(PFRD RCVDI

c..

::XJ

MICROSEOUENCER 1----~'\I
BRANCH LOGIC
(UCB)

(")

-f
RECEIVE
CONFIRMATION
LOGIC

MICROSEOUENCER
(UCB)

::XJ

0
r-

"T1

ARBITRATION
LOGIC

(")

z
(I)
:E

:I:

-Pin
AA!
AA2
AB!
AB2
AC!
AC2
ADI
AD2
AEI
AE2
AF!
AF2
AHi
AH2
AJI
AJ2
AKI
AK2
ALI
AL2
AMI
AM2
AN!
AN2

(/)

Standard
Signal
INIT L
+5 v
INTR L
GROUND
DOOL
GROUND
D02 L
DOI L
D04 L
D03 L
D06 L
DOS L
008 L
D07 L
D!O L
DOq L
012 L
OJI L
Dl4 L
Dl3 L
PAL
DIS L
GROUND
PB L

Modified
Signal
INIT L
+5 v
INTR L
TEST POINT
DOOL
GROUND
D02 L
DOIL
D04 L
D03 L
D06 L
DOS L
D08 L
D07 L
010 L
009 L
012 L
DI IL
Dl4 L
013 L
PAL
DIS L
Pl*
PB L

*Pin.., u . . et.1 by panty control moJuk

API
AP2
ARI
AR2
AS!
AS2
AT!
AT2
AUi
AU2
AV!
AV2
BAI
BA2
BBi
BB2
BC!
BC2
BDI
BD2
Bl' I
BE2
BF!
BF2

Standard
Signal
GROUND
BBSY L
GROUND
SACK L
GROUND
NPR L
GROUND
BR7 L
NPG II
BR6 L
BG7 II
GROUND
BG6 II
+5 v
BG5 II
GROUND
BR5 L
GROUND
GROUND
BR4 L
GROUND
BG4 II
ACLO L
DCLO L

Modified
Signal
PO*
BBSY L
BAT BACKUP +15 V
SACK L
BAT BACKUP+ISV
NPR L
GROUND
BR7 L
+20V
BR6 L
+20V
+20V
SPARE
+5 v
SPARE
TEST POINT
BRS L
GROUND
BAT BACKUP +S V
BR4 L
INT SSYN*
PAR DFT*
ACLO L
DCLO L

Standard
Signal

Modified
Signal

BHI
BH2
BJ I
BJ2
BKI
BK2
BL!
BL2
BM!
BM2
BNI
BN2
BPI
BP2
BR!
BR2
BSI
BS2
BT!
BT2
BUI
BU2
BVI
BV2

AOI L
AOO L
A03 L
A02 L
AOS L
A04 L
A07 L
A06 L
A09 L
A08 L
Al IL
AIO L
Al3 L
Al2 L
Al5 L
Al4 L
Al7 L
Al6 L
GROUND
Cl L
SSYN L
COL
MSYN L
GROUND

AO! L
AOO L
A03 L
A02 L
A05 L
A04 L
A07 L
A06 L
A09 L
A08 L
Al IL
AIO L
Al3 L
Al2 L
Al5 L
Al4 L
Al7 L
Al6 L
GROUND
CI L
SSYN L
COL
MSYN L
-5 v

-t
l>

0
l>

:::c

0
l>

0
3:
0
0

"T1

(/)

3:
m

-t

(/)

UNIBUS SIGNAL DESCRIPTIONS

Signal Line

Description

Data Transfer Group
Address Lines
[SA (17:00)]

These lines are used by the master device to select the
slave (actually a unique memory or device register address). SA (17:01) specifies a unique 16-bit word; SAOO
specifies a byte within the word.

Data Lines
[D (15:00)]

These lines transfer information between master and
slave.

Control (Cl. CO)

These signals are coded by the master device to control
the slave in one of the four possible data transfer operations specified below. Note that the transfer direction is
always designated with respect to the master device.

CJ co
0 0

Data In (DA TI): a data word or byte transferred into
the master from the slave.
Data In Pause (DATIP): similar to DATI except that it
is always followed by a DA TO /B to the same location.
Data Out (DATO): a data word is transferred out of the
master to the slave.
Data Out Byte (DATOB): identical to DA TO except a
byte is transferred instead of a full word.

Parity A-B (PA, PB)

These signals transfer Unibus parity information. PA is
currently unused and not asserted. PB, when true, indicates a device parity error.

Master
Synchronization
(MSYN)

MSYN is asserted by the master to indicate to the slave
that valid address and control information (and data on
a DATO or DA TOB) is present on the bus.

Slave
Synchronization
(SSYN)

SSYN is asserted by the slave. On a DATO it indicates
that the slave has latched the write data. On a DA TI/P
it indicates that the slave has asserted read data on the
Unibus.

Interrupt (INTR)

This signal is asserted by an interrupting device, after it
becomes bus master, to inform the UBA that an interrupt is to be performed, and that the interrupt vector is
present on the D lines. INTR is negated upon receipt of
the assertion of SSYN by the UBA at the end of the
transaction. INTR may be asserted only by a device that
obtained bus mastership under the authority of a BG
signal.

Priority Arbitration
Group
Bus Request (BR 7-BR4)

These signals are used by peripheral devices to request
control of the bus for an interrupt operation.

Bus Grant (BG7-BG4)

These signals form the CPU and UBA response to a bus
request. Only one of the four will be asserted at any
time.

221

UNIBUS SIGNAL DESCRIPTIONS (CONT)

Signal Line

Description

Priority Arbitration
Group (Cont)
Nonprocessor Request
(NPR)

This is a bus request from a device for a transfer not
requiring CPU intervention (i.e., DMA).

Nonproa:ssor Grant

This is the grant in response to an NPR.

(NPG)

Selection Acknowledge
(SACK)

SACK is asserted by a bus-requesting device after having received a grant. Bus control passes to this device
when the current bus master completes its operation.

Bus Busy (BBSY)

BBSY indicates that the data lines of the bus are in use.
It is asserted by the Unibus master.

Initialization Group
Initialize (INIT)

This signal is asserted by the terminator board (UBT)
when DC LO is asserted on the Unibus, and it stays
asserted for 10 ms following the negation of DC LO.

AC Line Low (AC LO)

This is an anticipatory signal that warns of an impending power failure. AC LO initiates the power fail trap
sequence and may also be issued in peripheral devices to
terminate operations in preparation for power loss.

DC Line Low (DC LO)

This signal is available from each system power supply
and remains clear as long as all de voltages are within
the specified limits. If an out-of-voltage condition occurs, DC LO is asserted.

222

DW780 MODULE UTILIZATION CHART

TYPICAL
CONFIGURATION

B
L
A
N

A
I

0
D

[

M
8

2
7
3

2
7
2

2
7
1

2
7
0

TK-8357

223

MBA REGISTERS

MBA Register Base Address
as a Function of TR Number
TR
Num
Base 10
1
2
3
4
5
I)

7
8
9

10
11
12
13
14
15

Base
Address
(Physical
Hex)

SBI
Address
(Hex)

20002000
20004000
20006000
2111008000
2000A000
2000C000
2000E000
20010000
20012000
20014000
20016000
20018000
2001MJ00
2001C000
2001E000

8000800
8001000
8001800
8002000
8002800
8003000
8003800
8004000
8004800
8005000
8005800
8006000
8006800
8007000
8007800

MBA CONFIGURATION/STATUS REGISTER

00
SBI PARITY ERROR
WRITE DATA
SEQUENCE ERROR
UNEXPECTED READ
DATA ERROR

ADAPTOR POWER DOWN

MULTIPLE
TRANSMITTER----~

~----TRANSMITTER

DURING FAULT

ERROR

MBA CONTROL REGISTER
31

0000

0000 0000 0000
MAINTENANCE MODE
INTERRUPT ENABLE
ABORT
INITIALIZE

NOTE

ALL BITS ARE READ/WRITE EXCEPT INITIALIZE WHICH ALWAYS READS AS O

224

MBA REGISTERS (CONT)

MBA STATUS REGISTER

08
DATA TRANSFER
BUSY
NO RESPONSE
CONFIRMATION
CORRECTED
READ DATA

MASSBUS CONTROL
WRITE ERROR
MASSBUS ATTENTION
DATA TRANSFER COMPLETE--------'
DATA TRANSFER ABORT------~
DATA TRANSFER LATE------~
WRITE CHECK-UPPER ERROR-------~
WRITE CHECK-LOWER ERROR--------~
MISSED TRANSFER---------~
MASSBUS EXCEPTION----------~

MASSBUS DATA PARITY E R R O R - - - - - - - - - - - - - - '
MAP PARITY ERROR-----------~
INVALID MAP------------~
ERROR CONFIRMATION-------------~
READ DATA SUBSTITUTE-------------~
INTERFACE SEQUENCE TIMEOUT--------------~
READ DATA TIMEOUT---------------~
NOTE

WRITE 1 TO CLEAR BITS IN
THIS REGISTER EXCEPT BITS 31
AND 16, WHICH ARE READ ONLY.

MBA VIRTUAL ADDRESS REGISTER

~l:_,_0__0 _2:~l-~__0_0_2_:~l-~3-0__0_2_~.l~_9_0__0~,-6~r-5____,_2l~,_,__09~l~oa~l-07----04........l0_3____oo.....loc
MAP POINTER

PHYSICAL PAGE BYTE
ADDRESS
TK-0696

225

MBA REGISTERS (CONT)

MBA BYTE COUNT REGISTER

~'-1------------2-4_1 _23~~. . . .~~-1-6_r_5~~--''--~-0-8_1_0_7~----~~.....i 10
MASSSUS BYTE COUNTER
(READ ONLY)
NOTE: DATA WRITTEN INTO THE
SBI BYTE COUNTER IS COPIED
INTO THE MASSBUS BYTE
COUNTER.

SBI BYTE COUNTER
(READ/WRITE)
2's COMPLEMENT OF THE NUMBER
OF BYTES TO BE TRANSFERRED

TK.Q697

MBA DIAGNOSTIC REGISTER
08 07

00
14

INVERT MASSBUS
DATA PARITY
INVERT MASSBUS
CONTROL PARITY

(READ ONLY)

INVERT MAP PARITY

MASSBUS REGISTER SELECT
(READ ONLY)

BLOCK SENDING - - - - - - '
COMMAND TO SBI
SIMULATE SCLK - - - - - -

SELECTED MDIB (READ ONLY)

SIMULATE EBL - - - - - - -

(VALID DURING MAINTENANCE

SIMULATE OCC ------~

MODE ONLY)

SIMULATE ATTN-------~
MDI 8 SELECT--------~
MASSBUS FAIL (READ ONLY)------~
MASSBUS RUN (READ O N L Y ) - - - - - - - MASSBUS WCLK (READ ONLY)-------~
MASSBlJS FXC: !REA[) ONLY)--------~
MASSBUS CTOD (READ ONLY)---------~

226

NOTE: BITS 21 AND 22 ARE READ/WRITE
FOR DIAGNOSTIC TEST PURPOSES
ONLY

MBA REGISTERS (CONT)

MBA MAP REGISTER

PHYSICAL PAGE FRAME NUMBER
TK~715

COMMAND/ADDRESS REGISTER (CAR)

28 27

~l_F_u_N_c_T~l_____________________A_o_o_R_E_s_s__________________...-11C
*The CAR is read-only, and is only valid when DT BUSY is set.
This register contains the value of bits 31 through 00 of the SBI
during the command/address portion of the MBA's next data
transfer.

227

b
a

d
c

j
h

n
m

t
s

v
u

W9 Wl0 Wll Wl2

bb
aa

dd
cc

jj
hh

11
kk

nn
mm

rr
pp

tt
SS

RH780 Configuration
for REV A Backpanel

vv
uu \

:c
::c

......

co
0

~
Configuration
for REV -- Backpanel
Wl

CD
)>

W9 Wl0 Wll Wl2

(')

TR Arbitration
Level
Signal
Name

...,
...,
CX>

TRI

MBA
TR
SEL
D
Wl

MBA
TR
SEL

MBA
TR
SEL
B
W3

MBA
TR
SEL
A

11
12
13
14
15

Signal
Name
Wire Wrap
Bus SBI TRXX L
from F02Fl to

5
6
7
8

Interrupt Level
Selection

F02Cl
F02Dl
F02El
F02F2
F02H2
F02Jl
F02J2
F02Ml
F02Nl
F02Pl
F02P2
F02S2
F02T2
F02Ul
F02U2

* Normal for

BRf

MBA
In tr
Code
1
H

MBA
INTR
Code
0
H

3::

4
6
7

2
m

(')

0
2

"T1

:c
)>

-t

W7 - Wl2 SPARES

first RH780

0
2

MASSBUS DISK DRIVE REGISTER ADDRESS CALCULATION CHART

1ST MBA BASE ADDRESS - 20010400 (TAB)
2ND MBA BASE ADDRESS - 20012400 (TR9)
REGISTER
NUMBER

HEX

OCTAL

0
1
2
3
4

D
E
F

0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17

CSI
OS
ER1
MR
AS
DA
OT
LA
SN
OFF
DCA
CCA
ER2
ER3
ECCPOS
ECCPAT

.. .

DRIVE NUMBER

TYPE

DRIVE
RP
(DISK)

6
7
8
9
A
B

3RD MBA BASE ADDRESS -20014400 (TR10)
4TH MBA BASE ADDRESS - 20016400 (TR11)

RM
(DISK)

TE
(TAPE)

RMCS1
AMOS
RMER1
RMMR1
AMAS
AMOA
RMDT
RMLA
RMSN
RMOF
RMOC
RMNR
RMMR2
RMER2
RMEC1
RMEC2

CS1
OS
ER
MR
AS
FC
OT

0
4
8

10
14
18
1C
20
24
2B
2C
30
34
3B
3C

8B
BC
90
94
9B
9C
AO
A4
AB
AC
BO
B4
BB
BC

100
104
10B
10C
110
114
11B
11C
120
124
128
12C
130
134
13B
13C

1BO
1B4
1B8
18C
190
194
198
19C
1AO
1A4
1A8
1AC
1BO
1B4
1B8
1BC

200
204
208
20C
210
214
218
21C
220
224
228
22C
230
234
23B
23C

2BO
2B4
28B
28C
290
294
298
29C
2AO
2A4
2AB
2AC
2BO
2B4
2BB
2BC

300
304
308
30C
310
314
318
31C
320
324
328
32C
330
334
33B
33C

3BO
3B4
388
38C
390
394
398
39C
3AO
3A4
3A8
3AC
3BO
3B'
3B8
3BC

17C

1FC

27C

2FC

37C

3FC

ex
SN
TC

.. .. .. .. .. .. .. ..
. . . . . . . .

MBA BASE PHYSICAL ADDRESS TRANSLATION
16

I I

OS
M
OS
RS

MAP REG SELECT
SET IF EXTERNAL REGISTER
DRIVE SELECT#
REGISTER SELECT

ZERO

229

BYTE

MASSBUS SIGNAL CABLE PIN ASSIGNMENTS

Musbus Signal Cable Designations

Musbus Signal Cable Designations
Pin•

Cable
Massbus
Cable A

A
B

c
D
E
F
H

Polarity

I
2
3
4

6
7
8
K
9
L
10
M
II
N
12
p
13
14
R
s IS
16
T
u 17
v 18
w 19
x 20
y
21
22
l
AA 23
BB 24
cc 2S
DD 26
EE 27
FF 28
HH 29
JJ
30
KK 31
LL 32
MM 33
NN 34
pp
3S
RR 36
SS 37
TT 38
uu 39
J

+
+
-

Designation

Cable

MASS DOO

Massbus
Cable B

MASS 003

MASS D04

+
+

MASS DOS
MASS COO
MASS CO I

+
+
-

MASS C02
MASS C03
MASSC04

+
+

MASS COS

MASS SCLK

+
+
+

MASS RS3
MASS ATTN
MASS RS4

+
MASSCTOD
+
+

MASSWCLK

MASS RUN

I
2
3
4

SPARE
GND

Note: Massbus cables are to be installed per markings on the cable.

230

MASS D06

+
+

MASSD07
MASS D08

6
7
8
9

II
12
p
13
14
R
s IS
16
T
u 17
v 18
w 19
x 20
y
21
22
AA 23
BB 24
cc 2S
DD 26
EE 27
FF 28
HH 29
JJ
30
KK 31
LL 32
MM 33
NN 34
pp
3S
RR 36
SS 37
TT 38
uu 39

•Altt"rnatt> pin de'§ig:nahon ..chemt:"i

Desipation

Polarity

D
E
F
H
J
K
L
M
N

+
+

A
B

MASS DOI
MASS 002

+
+

Pin•

MASS D09
MASSDIO
MASS DI I

MASSC06
+

MASS C07

+
+

MASSC08

+
+

MASSC09
MASSCIO
MASS Cl I
MASS EXC

+
+

MASS RSO
MASS EBL
MASS RSI

+
MASS RS2

+
+

MASS !NIT

MASS SPI

SPARE
GND

MASSBUS SIGNAL CABLE PIN ASSIGNMENTS (CONT)

Massbus Signal Cable Designations

Mass bus
Cable C

Designation

Pin*

Polarity

I
2
3
c
D
4
E
5
6
F
H
7
J
8
K
9
L
10
M
II
N
12
p
13
14
R
s I5
16
T
17
u
v 18
w 19
x 20
y
21
z 22
AA 23
BB 24
cc 25
DD 26
EE 27
FF 28
HH 29
JJ
30
KK 31
LL 32
MM 33
NN 34
pp 35
RR 36
SS 37
TT 38
uu 39
vv 40

MASSDJ2

+
+

MASSDl3

Cable

+
+

MASSDl4

+
+

MASS Dl6

MASS DIS

MASSDl7

+
+
+
+

MASS DPA
MASSCl2
MASS Cl3
MASS Cl4
MASSCl5

+
+
+
+
+

MASS CPA
MASSOCC
MASS DSO
MASSTRA
MASSDSI

+
+
+
+
H

•Alternate pin designation schemes

231

MASS DS2
MASS DEM
MASS SP2
MASS FAIL
GND

RH780 MODULE UTILIZATION CHART

TYPICAL
CONFIGURATION

L
A
N
K

M
0
D

M
D
p

I
R

M
0
D

M
8

2
7

2
7
7

M
I

TK-8356

232

MBAjSBI INTERFACE
M8275 SLOT I

MBA INTERNAL REGISTERS
INT BUS
DRIVERS
!TRI-STATE I
MSI

TAG

ADDRESS/

DECODE

C/A

FUNCTION

MSI

R/W CMD

------~-----

CHECK
MSI

SBI

RED OK

ISR DATA

M8276 SLOT 2
INTERNAL BUS (TRI-STATE)

MASSBUS DATA PATHS
M8277 SLOT 3

MASSBUS CONTROL PATHS
M8278 SLOT 4

PORT CONFIGURATION REGISTER 2000XOOO MPI
31

02
0

SBI SBI
PTY WRT
FLT SEQ
FLT

SBI
SBI
PORT
INTLK MULT XMT
SEQ
XMT DUR
FLT
FLT
FLT

3::

.....
()()

PORT NO

MA7BO NEXUS
IDENT (ALWAYS
IS 010000)

3::
r-

.,,

::!

SBI FAULT STATUS

::D

-i

3::
m
3::

PORT INTERFACE CONTROL REGISTER 2000X004 MPI
31

23
RAM
OV

801
RAM
PTY
PAR
FLTON
ERR
OUTPUT
(MPI)
801
IVDT
IVDT
PTY
LOST
ACK
FLT ON
ON
NOT
INPUT
BDI
REC
(MPCI

MRK
TMO

2
1
0
RAM COUNT

MRK
REQ

INPUT
BDI
PTY
INV

INHB
RAM
ARB

OUTPUT
BDI
PTY
INV

MARK
INLK
IP

::D

MSTR
INTR
EN

::D

m
C>

Pl
ERR
INTR
EN

;;
-i

::D

en
PORT CONTROLLER STATUS REGISTER 2000X008 MPC
27

MULT
XMTR
FLT

FAULT
ADMI
WRTH
GRNT
RD L
PAR ERR
ADMI
829 H

ARR H
1/0 L
ADMI
827 L

NOC/AON
ADMIWHEN
REQSTD

IVDT
DATA
LOST
IN
MPC

ARY
INIT
IN
PROG

INLK
GRNT
ACPTD

INVAL
DIS

FORCE
ADMI
MULT
XMTR
FLT

TR. NO.

ERR
INTRPT
EN

X•

PORT INVALIDATION CONTROL REGISTER 2000XOOC MPC
31

27
26

24
23 22 21
20
19
18
STARTING ADDRESS <26: 16>

19
17

16
0

15
ARRAY SIZE

ID
15

ID
14

ID
13

ID
12

ID
11

CACHED
FORCED
BIT

ID
ID
ID
1098

07
ID

l>
.....

ID ID ID
ID ID
ID
543210

CACHE DEVICE IDENT.

c:
r-

"":::D

ARRAY ERROR REGISTER 2000X010 MAT
31

127

~ 23

I I I I II I I I : : : : :

~ 19

~ 15

-t

s:m
s:

IVDT INH HI
ERR
MAP CRD ERR LOG
PTY TAG RATE REQ
ERR

:::D

CONFIGURATION STATUS REGISTER 0 2000X014 MAT
31

PORT OFF LINE

07
PORT ERROR

(ii

PORT POWER
DOWN STATUS

-t

ARRAY
INIT
STATUS 4K ARRAY
CHIP
ARRAY
ERR

:::D

(/)

n0
z

::j
CONFIGURATION STATUS REGISTER 1 2000X018 MPS
31
27
23

19
0

PRT PRT PRT PRT
3
2
0

PRT 3

03
PRT 2

PRT 1

PORT TYPE/PRESENCE

MUL T FORCE SLOW
INLK
INLK ARB
ACPTD

00
PRT 0

TR. NO.

X•

MAINTENANCE CONTROL REGISTER 2000X01C MAT

.....

00
0

SUBSTITUTE ECC BITS (07:00)

:::!

"ti

::1:1

....

s:m

INTERPORT INTERRUPT REQUEST REGISTER 2000X020 MPS
31
27
23
FROM PAT 3

FROM PAT 2

FROM PAT 1

15
TO PAT 3

FROM PAT 0

07
TO PAT 2

03
TO PAT 1

::1:1

TO PAT 0

TO TO TO TO TO TO TO TO TO TO TO TO TO TO TO TO
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
PAT PAT PAT PAT PAT PAT PAT PAT PAT PAT PAT PAT PAT PAT PAT PAT
PAT 2
PAT 0
PAT 2
PAT 0
PAT 2
PAT 0
PAT 2
PAT 0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
PAT 3
PAT 1
PAT 1
PAT 3
PAT 1
PAT 3
PAT 1

::1:1

en
....m
::1:1
en

0
0
2

.::!
INTERPORT INTERRUPT ENABLE REGISTER 2000X024 MPS
31
27
23
TO PAT 3
FROM
FROM
PAT 3
FROM
PRT 2

TO PRT 2

TO PRT 1

15
TO PRT 0

FOR PAT 3

07
FOR PRT 2

FOR PRT 1

00
FOR PRT 0

FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
PRT 1
PRT 3
PAT 1
PAT 3
PRT 1
PRT 3
PRT 1
PRT 3
PAT 1
PRT 3
PAT 1
PRT 3
PAT 1
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
FROM
0 •n 0
PRT 2
PRT 0
PRT 2
PRT 0
PAT 2
PRT 0
PRT 2
PRT 0
PRT 2
PRT 0
PRT 2
PAT 0

MA780 ARRAY ADDRESSES

Array

M8210

Address Range

256K

3FFFF

512K

40000

7FFFF

768K

80000

BFFFF

1024K

C0000

FFFFF

1280K

100000

13FFFF

1536K

140000

17FFFF

1792K

180000

lBFFFF

2048K

1C0000

lFFFFF

238

MA780C JUMPERS

Wlll Wll Wl2 Wl3 Wl4 WlS Wl6 Wl 7 Wl8 Wl9 W21l

D
D

SBI TR Level Jumpers
Optional Port Interface Slots 1 and 2

Standard Port Interface Slots 3 and 4
TR
Level

Wl7

Wl8

Wl9

Jumper

Wire Wrap

Jumper
W21l

Fll3Cl
Fll3Dl
Fll3El
Fll3F2
Fll3H2
Fll3Jl
Fll3J2
Fll3Ml
Fll3Nl
Fll3Pl
FllJ3P2
Fll3S2
Fll3T2
Fll3Ul
Fll3U2

1
2
3

4
5
6
7
8
9

lll
11
12
13
14
15

Fll3Hl to

Wire Wrap
Wl

F82Hl to
Fll2Cl
Fll2Dl
Fll2El
Fll2F2
Fll2H2
Fll2Jl
Fll2J2
Fll2Ml
Fll2Nl
Fll2Pl
Fll2P2
Fll2S2
Fll2T2
Fll2Ul
Fll2U2

The memory that contains the ROM bootstrap must be at TR 1.
Ml>.781! (s)
MS781l (s)
DW781l(s)
RH781l (s)

must
have
have
have

have the
the next
the next
the next

next highest SBI priority, that is, lowest TR number.
highest.
highest.
highest.

If a MS781l con ta ins the ROM bootstrap, i t must be at TR 1.
If MS781l memories are on
the system and are to be interleaved, the second MS781l must be at the next even TR
number past the last Ml>.781! TR.

Interrupt Level JIDlpers

Interport Interrupt
Level

Error Interrupt
Level

I = Jumper inserted.

- = No jumper.
* = Standard configuration.

239

Standard Port
Slots 3 and 4

Optional Port
Slots l and 2

W16

MA780A JUMPERS

Wl0 Wll Wl2 Wl3 Wl4 WlS Wl6 Wl? Wl8 Wl9 W20

Memory Starting Address Jumpers
(Used Only on Power-Up)
Strap
Name

Port
SA23

0
SA22

Port 1
SA23
SA22

Port
SA23

2
SA22

Port
SA23

3
SA22

Jumper

Wl9

W21'1

WlS

Wl6

Wll

Wl2

0MB
16MB
2'1MB
24MB

Multi port Number Jumpers
(Number Visible on Control Panel)
Signal
Jumper

Set Multi port 1
Wl

Set Multiport 0
W2

Jumper inserted.
No jumper.
Standard configuration.

240

T
T

V
V

MA780 BACKPLANE DATA

PORT3
INTERFACE BACKPLANE
(OPTIONAL)
7014103 BLANK MODULE
M9040 SBI TERMINATOR
M8258 MULTIPORT INTERFACE
,-4
1 M8210 MAY

1.75-2M BYTE

OPTIONAL

2 M8210 MAY

1.5-1.75M BYTE

OPTIONAL

3 M8210 MAY

1.25 - 1.5M BYTE

OPTIONAL

4 M8210 MAY

1.0 - 1.25M BYTE

OPTIONAL

PORT2
INTERFACE BACKPLANE
I OPTIONAL)

7014103 BLANK MODULE

5 M8210 MAY

756 - lOOOK BYTE

OPTIONAL

6 M8210 MAY

512 - 756K BYTE

OPTIONAL

M9040 SB/ TERMINATOR

7 M8210 MAY

256-512K BYTE

OPTIONAL

M8258 MU LT/PORT INTERFACE

B M8210 MAY

0-256K BYTE

9 MB210 MAP

SELECTIVE CACHE MAP OPTIONAL
MULT!PORT PORT SYNCHRONIZER

MEMORY DATA PATH

11 M8212 MDT
12 M8260 MAT

MUL TIPORT ARRAY TIMING

13 M8259 MPC

MUL TIPORT PORT CONTROL PORT 3

OPTIONAL

~:: :~~T ~O~LCT~~~:~:~=~~O:ETAR~L p~:T~~NA~PTIONAL

M9~5

PORT 2 BDI CONNECT FROM REAR

17 MB259 MPC

M9~5

OPTIONAL

PORT 1
INTERFACE BLANKPLANE

µ:

7014103 BLANK MODULE

:::~ ~~:~,:~~~~:~:RFACE

PORT 1

~:.___M9_~_5_P_OR_T_1_BD_1_co_N_NE_c_T_FR_o_M_RE_A_R

__,

MUL Ti PORT PORT CONTROL PORT 1

PORT 1 BO/ CONNECT FROM REAR

19 MB259 MPC

MUL T/PORT PORT CONTROL PORT 0

20 M9045 PORT 0

BO/ CONNECT FROM REAR

PORTO
INTERFACE BACKPLANE
(SEE NOTE 31
1

NOTES
1

PORT 2

r-4 .__M_904_5P_O_RT_2_a_o_1c_oN_N_Ec_T_F_RO_M_R_EA_R_ __,

10 MB261

MPS

PORT 3

M9045 PORT 3 BO/ CONNECT FROM REAR

SEE NOTE 2
INSERT BLANK MODULES 7014103 IN ALL FRONT
SLOTS CORRESPONDING TO M9045 BO/ CONNECTIONS

THE SB/ TERMINATOR IM9040l IS REMOVED IF THE
SB/ CONTINUES BEYOND THE PORT INTERFACE
BACKPLANE

EACH PORT INTERFACE BACKPLANE MOUNTS INTO
A DIFFERENT CPU CABINET.

IF ADDITIONAL MEMORY STORAGE IS TO BE ADDED
TO THE MA7BO. IT MUST BE CONTIGUOUS WITH THE
EXISTING MA7BO MEMORY. FOR EXAMPLE' IF A
256K BYTE BOARD (MB210) IS ADDEO TO A 512K
BYTE SYSTEM, THE NEW BOARD MUST BE LOCATED
IN SLOT 6 AS THE 512 ~ 756K BYTE. IF THE MEMORY
STORAGE BOARDS ARE MISCONFIGUREO, A RED
LEO ILLUMINATES ON THE M8260 MODULE IN SLOT
12

M7~SBI TERMINATOR

MB258 MULTIPORT PORT INTERFACE

M9045 PORT 0 BO/ CONNECT FROM REAR

SEENOTEr_/

241

7014103 BLANK MODULE

2
3

PORT 0

M8210 MEMORY ARRAY CARD MNEMONICS

The following table shows the cross-correJation between the
mnemonic when the card is used in the MS780 main memory and the
The
MA780 multi port memory subsystem of the VAX-11/780 system.
M8210 array card, in addition to its identical memory storage
function in both memories, is used (one card) as the invalidate
map of the multiport memory.

As Array Card in MS780
Main Memory
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS

ENAB ARRAY OUT H
MOS DAT C00 H
MOS DAT C01 H
MOS DAT C02 H
MOS DAT C03 H
MOS DAT C04 H
MOS DAT Clil5 H
MOS DAT C06 H
MOS DAT C07 H
MOS DAT llil0 H
MOS DAT l01 H
MOS DAT l02 H
MOS DAT l03 H
MOS DAT l04 H
MOS DAT l05 H
MOS DAT ll:l6 H
MOS DAT U'l7 H
MOS DAT l08 H
MOS DAT L09 H
MOS DAT lll:l H
MOS DAT Lll H
MOS DAT ll2 H
MOS DAT ll 3 H
MOS DAT Ll4 H
MOS DAT ll5 H
MOS DAT ll6 H
MOS DAT l l 7 H
MOS DAT llB H
MOS DAT ll9 H
MOS DAT l21:l H
MOS DAT l21 H
MOS DAT l22 H
MOS DAT l23 H
MOS DAT l24 H
MOS DAT l25 H
MOS DAT l26 H
MOS DAT l27 H
MOS DAT l28 H
MOS DAT l29 H
MOS DAT l31:l H
MOS DAT l31 H
MOS DAT Ul:llil H
MOS DAT Ulill H
MOS DAT U02 H
MOS DAT Ul:l3 H
MOS DAT Ull4 H
MOS DAT U05 H
MOS DAT U'16 H
MOS DAT U(17 H
MOS DAT Uf'IB H
MOS DAT U09 H
MOS DAT Ul0 H
MOS DAT Ull H

As Array Card in MA780
Multi port Memory
Pin

As Invalidate Map in MA780
Multiport Memory
Pin

ELl MATJ ARY OUT EN H

Ell
AJl
AH2
AFl
A El
Dll
EBl
DP2
DR2
ANl
AMl
All
AKl
BAl
AV2
AUl
AR!
BEl
BDl
BCl
BBl
BKl
BJ!
BH2
BF!
BPl
BNl
BMl
Bll
BV2
BU2
BSl
DR!
CK2
CJ2
CMl
CKl
BH2
CF2
CE2
CD2
DV2
DU2
DT2
DS2
EDl
EEl
EF2
EH2
EJ2
EK2
El2
EM2

242

MPSK INVAl OUT EN
BUS INVAl DAT P00
BUS INV Al DAT PIH
BUS INVAl DAT P02
BUS INV Al DAT P03
BUS INVAl DAT P04
BUS INV Al DAT P05
BUS INV Al DAT P06
BUS INVAl DAT P07
BUS INVAl DAT B00
BUS INVAl DAT B01
BUS INV Al DAT B02
BUS INV Al DAT B03
BUS INVAl DAT B04
BUS INV Al DAT Bl:l5
BUS INV Al DAT Bl:l6
BUS INVAl DAT Bl:l7
BUS INVAl DAT Bl:lB
BUS INV Al DAT Bl:l9
BUS INVAl DAT Bll:l
BUS INV Al DAT Bll
BUS INVAl DAT Bl2
BUS INV Al DAT Bl3
BUS INVAL DAT Bl4
BUS INV Al DAT Bl5
BUS INVAl DAT Bl6
BUS INV Al DAT Bl7
BUS INVAl DAT BlB
BUS INVAl DAT Bl9
BUS INVAl DAT B20
BUS INVAl DAT B21
BUS INVAl DAT B22
BUS INVAl DAT B23
BUS INVAl DAT B24
BUS INV Al DAT B25
BUS INVAL DAT B26
BUS INVAl DAT B27
BUS INVAl DAT B28
BUS INVAl DAT B29
BUS INVAl DAT B31:l
BUS INV Al DAT B31
BUS INVAl DAT B32
BUS INV Al DAT B33
BUS INVAl DAT B34
BUS INV Al DAT B35
BUS INVAl DAT B36
BUS INVAl DAT B37
BUS INVAl DAT B38
BUS INV Al DAT B39
BUS INV Al DAT B41:l
BUS INV Al DAT B41
BUS INVAl DAT B42
BUS INV Al DAT B43

H
H
H
H
H
H

l
l
l
l
l
l

l
l
l
l

l
l
l
l
l
l
l
l
l

l
l

M8210 MEMORY ARRAY CARD MNEMONICS (CONT)

As Array card in MS781l
Main Memory
BUS MOS DAT Ul2 H
BUS MOS DAT Ul3 H
BUS MOS DAT Ul4 H
BUS MOS DAT Ul 5 H
BUS MOS DAT Ul6 H
BUS MOS DAT Ul 7
BUS MOS DAT Ul!l
BUS MOS DAT Ul9 H
BUS MOS DAT U21l H
BUS MOS DAT U21 H
BUS MOS DAT U22 H
BUS MOS DAT U23 H
BUS MOS DAT U24 H
BUS MOS DAT U25 H
BUS MOS DAT U26 H
BUS MOS DAT U27 H
BUS MOS DAT U28 H
BUS MOS DAT U29 H
BUS MOS DAT U30 H
BUS MOS DAT U31 H
BUS OUT SEL L
MAY CHIP 16K L
MAY CHIP 4K L
MAY IN 15 L
MCNB CAS L
MCNB INIT H
MCNB MUX CNTRL H
MCNB READ H
MCND ARY EXT H
MCND ARY ADR 01 H
MCND ARY ADR 02 H
MCND ARY ADR 03 H
MCND ARY ADR 04 H
MCND ARY ADR 05 H
MCND ARY ADR 06 H
MCND ARY ADR 07 H
MCND ARY ADR 08 H
MCND ARY ADR 09 H
MCND ARY ADR 10 H
MCND ARY ADR 11 H
MCND ARY ADR 12 H
MCND ARY ADR 13 H
MCND ARY ADR 16 H
MCND ARY ADR 17 H
MCND ARY ADR 18 H
MCND ARY ADR 19 H
MCND ARY CS L
MCND RAS L
MCND REF CYC H

As Array Card in MA781l
Multiport Memory
Pin

CDl
FRl
FSl
FB2
CJl
DBl
CLl
DL2
DAl
DB2
CV2
DJ2
DH2
CT2
DK2
DFl
DF2
CR2
CS2
DDl
DEl
DM2
CM2
CP2
CL2

GND
BUS 16K CHIP L
BUS 4K CHIP L
BUS PRES BIT ll7 H
MATJ ARY CAS L
MATR INIT H
MATJ ARY MUX CNTRL H
MATJ ARY READ H
MATA ARY ADR 14 H
MATA ARY ADR 01 H
MATA ARY ADR 02 H
MATA ARY ADR 03 H
MATA ARY ADR 04 H
MATA ARY ADR 05 H
MATA ARY ADR 06 H
MATA ARY ADR 08 H
MATA ARY ADR 09 H
MATA ARY ADR 10 H
MATA ARY ADR 11 H
MATA ARY ADR 12 H
MATA ARY ADR 13 H
MATA ARY ADR 15 H
MATA ARY ADR 16 H
MATA ARY ADR 17 H
MATA ARY ADR 18 H

DCl
CPl
DJl

MATA ARY ADR 07 H
MATJ ARY RAS L
"IATK REF CYC H

243

As Invalidate Map in MA781l
Multiport Memory
Pin
ER2
ES2
EP2
EFl
EV2
EUl
EU2
ET2
FJ2
FH2
FF2
FE2
FP2
FPl
FM2
FL2
FU2
FV2
FT2
FS2
CDl
FRI
FSl
FB2
CJl
DBl
CLl
DL2
DAl
DB2
CV2
DJ2
DH2
CT2
DK2
DFl
DF2
CR2
CS2
DDl
DEl
DM2
CM2
CP2
CL2
CNl
DCl
CPl
DJl

BUS INV AL DAT B44 L
BUS INVAL DAT B45 L
BUS INV AL DAT B46 L
BUS INVAL DAT B47 L
BUS INV AL DAT B48 L
BUS INVAL DAT B49 L
BUS INV AL DAT B50 L
BUS INV AL DAT B51 L
BUS INV AL DAT B52 L
BUS INV AL DAT B53 L
BUS INV AL DAT B54 L
BUS INVAL DAT B55
BUS INV AL DAT B56
BUS IN VAL DAT B57 L
BUS INV AL DAT B58 L
BUS INVAL DAT B59 L
BUS INV AL DAT B61l L
BUS INV AL DAT B61
BUS INV AL DAT B62
BUS INVAL DAT B63 L
GND
BUS 16K CHIP L
BUS 4K CHIP L
INVAL MAP PRES L
MPSK INVAL CAS L
MATR INIT H
MBSK INVAL MUX CNTRL L
MPSK INVAL READ H
MATA ARY ADR 14 H
MATA ARY ADR 01 H
MATA ARY ADR 02 H
MATA ARY ADR 03 H
MATA ARY ADR 04 H
MATA ARY ADR 05 H
MATA ARY ADR 06 H
MATA ARY ADR 08 H
MATA ARY ADR 09 H
MATA ARY ADR 10 H
MATA ARY ADR 11 H
MATA ARY ADR 12 H
MATA ARY ADR 13 H
MATA ARY ADR 15 H
GND
GND
GND
GND
MATA ARY ADR 07 H
MPSK INVAL RAS L
MPSK INVAL REF CYC H

M8212 DATA PATH/ECC CARD MNEMONICS

The following
table of signal mnemonics for the M8212 data
path/ECC shows the cross-correlation between the mnemonic when the
card is used in the MS780 main memory and the MA780 multi port
memory subsystem of the VAX-11/780 system.
The M8212 serves an
identical function in both memories.
As Used in MS780
Main Memory

As Used in MA780
Multiport Memory

MCNA ARY RD EN H
MCNA CLR L
MCNA ECC EN G
MCNA RD DAl EN L
MCNA RD LO SEL L
MCNA WR EN LO H
MCNA WR EN UP H
MCNB ARY DAT CK H
MCNB CHK BIT DAT CK H
MCNB CHK DAT CK H
MCNB !NIT H
MCNB MSK CLR L
MCNB RD EN H
MCNB READ H
MCNB TAG CLK L
MCNB UNCOR ERR CLK L
MCNB XMT DAT CK H
MCNE CRD !NH L
MCNE DIAG EN L
MCNL FRC CHK 0 H
MCNL FRC CHK 1 H
MCNL FRC CHK 2 H
MCNL FRC CHK 3 H
MCNL FRC CHK 4 H
MCNL FRC CHK 5 H
MCNL FRC CHK 6 H
MCNL FRC CHK 7 H
MDTC SYN 2 H
MDTE FULL WR EN H
MSBH ADR 0 BUS L
MSBH DAT 0 BUS L
MSBJ FL EXT H
MSBJ FL WR H
BUS CMD ARY H
BUS FL INF 00 H
BUS FL INF 01 H
BUS FL INF 02 H
BUS FL INF 03 H
BUS FL INF 04 H
BUS FL INF V'IS H
BUS FL INF 06 H
BUS FL INF 07 H
BUS FL INF 08 H
BUS FL INF 09 H
BUS FL INF 10 H
BUS FL INF 11 H
BUS FL INF 12 H
BUS FL INF 13 H
BUS FL INF 14 H
BUS FL INF 15 H

DUl
EBl
FUl
ED2
ECl
EJl
EFl
DMl
DD2
DD2
DB2
DF2
ELl
DJl
DFl
DE2
EAl
EMl
FSl
FRl
FPl
FNl
FMl
FLl
FK2
FKl
FJl
FDl
DJ2
CMl
CLl
DRl
DPl
DSl
AAl
AB2
AD2
AE2
AF2
AJ2
AK2
AL2
AM2
AR2
AV2
BAl
BB2
BD2
BE2
BK2

244

MATK ARY RD EN H
MATJ CYC CLR L
MATJ ECC EN H
MATK RD DAT EN L
MATK RD LO SEL L
MATJ WR EN LO H
MATJ WR EN UP H
MATJ ARY DAT CK H
MATJ CHK BIT DAT CK H
MATJ CHK BIT DAT CK H
MATR !NIT H
MATJ MSK CLR L
MATJ RD EN H
MATJ GEN ECC L
MATJ TAG CLK L
MATJ UNCORR ERR CLK L
MATJ XMT DAT CK H
MATF CRD !NH L
MATE DIAG EN L
MATD FRC CHK 0 H
MATD FRC CHK 1 H
MATD FRC CHK 2 H
MATD FRC CHK 3 H
MATD FRC CHK 4 H
MATD FRC CHK 5 H
MATD FRC CHK 6 H
MATR FRC CHK 7 H
MDTA SYN 2 H
MATH ADR
MATH DAT
BUS ADM!
BUS ADM!
SUB ADM!
BUS ADM!
BUS ADMI
BUS ADM!
BUS ADM!
BUS ADMI
BUS ADMI
BUS ADMI
BUS ADMI
BUS ADM!
BUS ADMI
BUS ADM!
BUS ADMI
BUS ADM!
BUS ADMI
BUS ADM!
BUS ADMI

ON BUS L
ON BUS L
EXT H
B29 H
B29 H
B00 H
B01 H
B02 H
B03 H
B04 H
B05 H
B06 H
B07 H
B08 H
B09 H
Bl0 H
Bll H
Bl2 H
Bl3 H
Bl4 H
Bl5 H

M8212 DATA PATH/ECC CARD MNEMONICS (CONT)

As used in MS780
Main Memory

As used in MA780
Multiport Memory

BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS

BM2
BP2
BR2
BS!
BV2
CAI
CB2
CE2
CF2
CH2
CJ2
CK2
CL2
CM2
CR!
CR2
DM2
DLl
DK2
DL2
DKl

FL INF 16 H
FL INF 17 H
FL INF 18 H
FL INF 19 H
FL INF 20 H
FL INF 21 H
FL INF 22 H
FL INF 23 H
FL INF 24 H
FL INF 25 H
FL INF 26 H
FL INF 27 H
FL INF 28 H
FL INF 29 H
FL INF 30 H
FL INF 31 H
FL MSK 0 H
FL MSK 1 H
FL MSK 2 H
FL MSK 3 H
X PAR 1 H

245

BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!
BUS ADM!

Bl6 H
Bl7 H
Bl8 H
Bl9 H
B20 H
B21 H
B22 H
B23 H
B24 H
B25 H
B26 H
B27 H
B28 H
B29 H
B30 H
B31 H
MSK 0 H
MSK 1 H
MSK 2 H
MSK 3 H
Pl H

SBI TO CPU A

SBI TO CPU B

SBI TO CPU C

SBI TO CPU D

MB25B
MULTIPORT
INTERFACE
MODULE IMPI)
(RESIDES IN CPU
A CABINET)

MB25B
MULTIPORT
INTERFACE
MODULE IMP!)
(RESIDES IN CPU
B CABINET)

MB25B
MULTIPORT
INTERFACE
MODULE IMP!)
(RESIDES IN CPU
C CABINET)

M825B
MULTIPORT
INTERFACE
MODULE IMPll
I RESIDES IN CPU
D CABINET!

BIDIRECTIONAL INTERCONNECT IBDI)
15 FEET OF CABLE
SEPARATES THESE
MODULES

13 COMMAND AND STATUS LINES
15 COMMAND AND STATUS LINES
43 BIDIRECTIONAL LINES IFOA
COMMAND/ADDRESS. MASK,
ID, 4ND PARITY)
MB259
MULTI PORT
CONTROLLER
MODULE IMPC)

~-.....__._.........

MB259
MULTI PORT
CONTROLLER
MODULE IMPC)

MB259
MULTI PORT
CONTROL LEA
MODULE IMPC)

ADDRESS/DATA
CONTROL
PANEL

4 INFORMATION LINES

25 COMMAND LINES

-------

MEMORY CONTROL SECTION

....... ~~___.~"'--~
DATA PATH TIMING

~....._-""__...

M8210
INVALIDATE
MAP
IOPTION4U

MEMORY ARRAY
INTERCONNECT IMAI)
19 ADDRESS LINES

72 DATA LINES
9 CONTROL LINES -,_~-+-+...,---------i
8 PRESENCE BIT LINES
11 PEA BOARD)
M8210
ARRAY
CARD
NO. 1

MB210
ARRAY
CARD
N0.2

ALL MODULES EXCEPT M8258 MULTIPORT INTERF4CE MODULES
llN CPU CABINET) PLUG INTO MULTIPORT CONTROLLER BACKPLANE
2
3.

E4CH MB210 ARRAY CARD STORES 32.768 72 BIT WORDS 1256 K BYTES).
MULTIPORT CONTROLLER CAN ACCOMMODATE UP Tl B MB210 MEMORY
ARRAY CARDS, PROVIDING A TOTAL MAXIMUM STORAGE CAPACITY OF
2 MEGABYTE.S

MB210
ARRAY
CARD
NO. B

BUSSBI TAG<2:0>

BUS SBI RE0<7:4>

l
J
l

BUS SBI FAULT

BUS SBI CONF<1 :O>

t
J

SBI PARITY
CHECK

MPID

[ MARK CONTROL
AND TIMEOUT
LOGIC

TAG
LOGIC

1
INTERRUPT
LOGIC

l
l

MPIB,N,M,P,R

MPIJ,K

FAULT
LOGIC

MPIB,F

SBI
CONFIRMATION

1 LOGIC

PARITY
LOGIC

~
...
BUS SB! DEAD

DEAD

l
BUS SBI 10<4:0>

e;) -I

s:: ~
-I
s::m
s::

CONTROL INFO

BUS BDI P<l :O>

BDI

<
-I

DATA PATH
LOGIC
MPIA,E,F ,H,K,L,R,S

,,:D
l>

(")

J
J

)

BUS BDI B<31 :00>

]

MPIB,J

BUFFERED ECL CLKS

MPIB,H,M

SB!
ARBITRATION
LOGIC

m S::

5~
~!
c s::
-c
l> r:D
l> -""C

MPIC

FAIL AND
J PWR
UNJAM LOGIC

MPIP,R

BUS SBI TR<15:00>

BDI
RECEIVERS

[ RAM ADDRESS
AND
CONTROL LOGIC

BUS SBl<31 :00>

BUS SBI UNJAM

CONTROL INFO

MPIM

MPIB,F

CLOCK
LOGIC

1
J

BDI
DRIVERS

BUS BDI TAG<l :O>

MPCB,C,D,M,N,P,T

SBI
BUS SBI (T, PD, POI CLKS

MPIH

INVALIDATE
LOGIC

s::

MPIH

ID LOGIC

BUS BDI 10<4:0>

MPIB,F,L,M,N,P,U

m
~
co

BUS SB! M<3:0>

MASK LOGIC

}

MPIA,M,N,P,U

BUS BDI MSK<J:O>

~
!!

m 3::

r l>
0...,
(") 00

2 3::
c:

)>
C) ~
::c
)> -.,,

TAG LOGIC
MPCB,L,P
BDI TO MPC AND ADMI
DATA PATH LOGIC

3:: ~
-t

MPCA,B,D,E,J

AOMI AND MPC TO BDI
DATA PATH LOGIC

3::
m
3::

::c

BDI

(")

CLOCK
LOGIC

MPCT

MASK AND PARITY
LOGIC
MPCB,F,H,P,R

-t

::c

0
r
r
m
~

3::

ID LOGIC
MPCB,E

~
00

:s: )>:s:

READ SEL,
RD DATA EN

READ DATA RETURN FLAGS

c ...
cr- co
0

10 DATA READY

m :S:

~~
READ
DATA
EXPECTED

END OF
REFRESH

REWRITE CORRECT
DATA CLOCK

co
~

:::!

-t

"'C

EO
::D
r-

:s:

n :S:
"c ::D
0

; -<

ECC CHECK CLOCK

C) )>

::D ::D
)> ::D
END OF WRITE

:s: )>

:::!

:s:
z

'--------'=-----! (MATB,R)
REFRESH
&
REFRESH
INIT
RE OU EST
ADDRESS
GENERATION
REFRESH
&
GRANT
TIMING
' - - - - - - - ' +5V BAT

BITS0-31
MASK 0-3

INIT STATUS
EVEN PARITY 0,1

2 BIT
LATCH
(MATCI

INIT IN PROGRESS

C)
)>

c
n
0

-t

::D

m 3::

MAT

MPC

MAP

MPC

MAT

MAP

5~
~~
c 3::
>~
C> -I

MAT

ADR ON BUS
DAT ON BUS
RD DAT TO ADMI
REG WRITE CLK

MAP
MAP
PTY
ERR

MAP PTY DISABLE

INVALIDATE MAP
TIMING & CONTROL

::D -

)> -a

3:: ~

INVALIDATE MAP DATA PATH
r - - - - - - i / I MPSL,M

ADDRESS ON BUS

MPSJ

MPSF,H,K

-I

MPSA,B,C,D,E

BACKUP MODE
LOGIC INIT

3::
3::
0

....,..,_..,..=..,,.,,....,

COLD INIT
Al/1----D

::D

LATCH BIT<7:0>
RECV PTY BIT

M l'X1..._...__..__.._--I

READ DATA
MULTIPLEXER
BUS RECV ADMI

'--~=-'~""+MAT,MPC
'----~"--'--'--+MAT

MPSP,R

<B31:800>
READ SELECT 1

74L5253
74LS240

CLK REQST REG
CLK ENAB REG

INTERPORT INTERRUPT REQUEST REGISTE
745373

MPSS,T
INTERLOCK ARBITER
MPSR,V,W,X

MAT
MPC

INTERRUPT

eu""sR--E"'"cv-A'""D,_.M-1<-B-31-:e"""oo'-' INTERPORT INTERRUPT ENABLE REGISTER
REQUEST

UNJAM

MPC
MPC

MPCMPC MPC
PORT TYPE MAP PRESENT
GRANT ACCEPTED

::D

3::

CLK CONFG REG

BUS RECV ADMI <B15:B12

:I:
::D

4:1 MUX
(16 BITS)
READ SELECT 0
EN READ DATA

<
z<

____
IN_LK_G_R_AN_T_E_R_R_,.4...._MPC

L .........,.!~~---""------'-IV;..:D;.;.T.;..;A~CK'----;•~ MPC

c:
r-

~
00

~
....

m 3::
r- )>
.....
n co

0
64

"
64 BIT LATCH
MAP DATA LATCH
MPSA
745373

3::

l>?
C> :::!

:a ""C
0
3:: :a

-t

3::
m
3::

e)>

-t
m

BUS INVAL DAT<P07 POO> L B

3::

""C

-t

REFRESH CYCLE H

AECV ADDA A27 H
MPSC

-t

::c

,.-----

PATO INLK REG

~
]_.1

PAT1 INLK REG

FIRST
LATCH

m S:
r l>

.....I

1---SECOND
LATCH

1----

TIE·BAEAKEA
ROM

D--

~
~

4X4

PENDING
PAT2 INLK REG

;=u

H
MPSV

MPSV

ARB INPUT CLK2
LAST GNT Bl

LAST
GNT BO

L___.

FILE WAITE CLK

J'r""'"""""'

PENDING

L.,
~

t=D-

_....;

1----

~NPU:J;

GRANT
FILE

1----

PATJ INLK REG
MPSV

,-------,

INPUT
TIMING
CHAIN

MPSV

FILE

READ/WAITE
POINTERS
GRANT

ENABLE

MPSW

1---

1--

~ PENDING STATUS
[____. AND
LAST GRANT

1--

i-I--CLEAR

~G
PENDING CLK

.....I
MPSV

PJ PENDING

PO PENDING

1---

111 '""'

PENDING

I--I---PRTO ACPT INLK

PRT1 ACPT INLK
PRT2 ACPT INLK

PATl INLK GNT

PRT2 INLK GNT

,i:;: 0

c s:
c
)> r-4
lJ e;')

)>
PRT31NLK GNT

.....

(') 00

"ti

s: ~
-4
s:
m
s:
0

PRTO INLK GNT

OUTPUT
TIMING
CHAIN

PRTJ ACPT INLK
MPSX

-4

(')

,i:;:

m
-4

m S:

n co

c 0s:
-c
l> r-

"
8 SYNDROMES TO CONFIGURATION REG 'C' IMB213)------~

2 TAG LINES

BUS ADMI
B (3L00)

MASK
CONTROL
LOGIC

DATA
CORRECTIONl4--------i
LOGIC
64 CORRECTION FLAGS

TRANSMIT

8 MASK CONTROL

s: ~
-f
s:
m
s:

64 CORRECTED
DATA BITS
MDTH~R

l> "'O

MDTD.F

SIGNALS
MOTE

N
U1

C> -f

:::c -

SYNDROME
DECODE
&
ERROR
FLAGS

- - - - B U S MOS DATA UPPER
WAITE
WORD<Jl ,00>
DATA
LATCH
!UPPER
WORD)
MDTH,K,
M,P

BUS MOS DATA XX
UPPE R<3LOO>
LOWEA<Jl ,00>

MOTH.A

64 DAT A BITS

:::c

-<
c

ECC
CHECK
LOGIC

MDTA,B,C

-f

WRITE
DATA
LATCH
(LOWER
WORDI
MDTJ,L
N,A

64 ARRAY
BUS MOS DATA
LOWER WORD
<31,00>

DATA LINES

REC
MOS
ARRAY
REC
DATA
LATCH

REC
MOS
ARRAY
CHECK
BIT
DATA

CHECK BITS
TO MOS
ARRAY

MOTH.A

MDTB

MDTC,T

SCHECK BITS
FROM MOS ARRAY

MEMORY ARRAY INTERCONNECT

::c

n
n

8 CHECK BITS TO MOS ARRAY

s:
0

c
rm
~
()()

....N

t:!

DR780 REGISTERS

OCR ADDRESS REGISTER
313029282726 25242322212019181716

111

13121110 09 08

+1+1+Jo1+1+1+1 N0.1+1 I
TR

00
REG. ADDRESS

I
PAGE SELECT

OCR READ REGISTER

2001BOOO

BIT
31
30
29
2B
27
26
25
24
23

22
21
20
0

FUNCTION

BIT

PARITY FAULT
WRITE SEQUENCE FAULT
UNEXPECTED READ DATA
UNUSED
MULTIPLE TRANSMITTER FAULT
TRANSMITTER DURING FAULT
UNUSED
EXTERNAL ABORT
POWER DOWN
POWER UP
UNUSED
INTERRUPT ENABLE

FUNCTION

PACKET INTERRUPT
19
ABORT
1B
HALT
17
1;:;
CORRECTED READ DATA
READ DATA SUBSTITUTE
15
14
COMMAND/ADDRESS TIME OUT IDl
13
READ DATA EXPECTED TIME OUT ID1
12
RECIEVED ERROR CONFIRMATION IDl
11
DATA INTERCONNECT STALL
10
COMMAND/ADDRESS TIME OUT ID2
9
READ DATA EXPECTED TIME OUT ID2
RECIEVED ERROR CONFIRMATION ID2
B
7 ~ 0 30 (16) ADAPTER TYPE CODE

DCB =CONTROL CODE

254

DR780 REGISTERS (CONT)

OCR WRITE REGISTER
31

1514

121110

0807

1.~-----

20018000 ...

CONTROL
FIELD B CONTROL
FIELD A

0
0
0
0
1

0
0
1

0
1
0
1
0

10
NO OPERATION
CLEAR CORRECTED READ DATA
SET EXTERNAL ABORT
CLEAR PACKET INTERRUPT
RESET
SET OUT OF SEQUENCE TEST
CLEAR OUT OF SEQUENCE TEST
NO OPERATION

0
0
0

0
1

NO OPERATION
CLEAR POWER UP
CLEAR POWER DOWN
NO OPERATION
CLEAR ABORT INTERRUPT AND READ
DATA SUBSTITUTE
CLEAR INTERRUPT ENABLE
SET INTERRUPT ENABLE
CLEAR HALT

DR780 UTILITY REGISTER
08 07

'------y---.-/
WCS
VAL

DATA RATE
FF THAU FC ARE NOT VALID

TK-4607

255

DR780 TR ARBITRATION JUMPER AND WIREWRAP SELECTION

Signal
Name

TR
SELD
L

TR
SELC
L

TR
SELB
L

TR
SELA
L

TR No.

Wirewrap
F02L2
To

F02Cl
F02Dl
F02El
F02F2
F02H2
F02Jl
F02J2
F02Ml
F02Nl
F02Pl
F02P2
F02S2
F02T2
F02Ul
F02U2

2
3
4
5
6

7
8
9
10
11

12
13
14
15
Hi

TR Level Jumper - TR arbitration level jumpers for the first DR780
are W4 and W3, for a TR number of 13.
TR arbitration level
jumpers for the second DR780 are W4, W3, and Wl, for a TR number
of 14.
TR Wirewrap - Wirewrap BUS SBI TRXX L for the first DR780 from
F02L2 to F02T2. Wirewrap BUS SBI TRXX L for the second DR780 from
F02L2 to F02Ul.
DI Clock Jumper Select - If the DR780 is to be the clock source
for the DI, then jumper WB on the backpanel should be installed
anywhere from W9 through Wl2 (these jumpers not used by the
DR780).
If the customer's device is to be the source of the DDI
clock, then install the jumper on WB.
MSEL Jumper Select - Install the jumper at W7 if the DR780 is not
going to perform DDI arbitration, or be its master.
If the DR780
is to be the master device, the jumper should be installed on any
pins from W9 through Wl2.

256

DR780 BACKPLANE

•••••••••••••••
• • • • • • • • • • • • • • •

J10

J11

J15 J14 J13
1
l!I
2
lil*m·m
03
0

GND

+5V
*PIN 1
(REAR VIEW)
TK-5157

257

DR780 BACKPLANE (CONT)

M8296

M8297

M8298

DSC

DCB

DUP

M8299
DSM

6
M9046
DDIP

(VIEW FROM SIDE 2)
TK-8348

258

DR780 BLOCK DIAGRAMS

SBI CONTROL (DSC) M8296

PARITY CHK, GEN;

SBI
XMIT
XCVR
8646
DSCB

MASK CHK,
GEN;
FUNCTION
DECODE;
IDCOMP,
XMIT
DSCC, H,L,M

CMND
REG
DSCN

DCl02

745194

MISC
OCR WRITE
DECODE

DSCJ

DI
CLK

XCVR XMIT.._-~--~~<

8646
DSCA

REC

32
SBUS REC

745573
DSCT
32

259

DR780 BLOCK DIAGRAMS (CONT)

CONTROL BOARD (DCB) M8297

CONTROL
RAM

SBI ADRS
LOOK AHEAD
REG
74LS377
DCBC

BYTE COUNT
LOOK AHEAD
REG
74LS377
DCBA

85S68
DCBB

74LS377
74LS169
DCBC

S BUS
REC
74S373
DCBA
S BUS
TK-8353

260

DR780 BLOCK DIAGRAMS (CONT)

MICROPROCESSOR (DUP) M8298

CONTROL INTERCONNECT

FLAG 0, 1
STATE REG
DUPU

BUS D<29:02> +2

LOCAL
STORE
8-93422
256 x 32
DUPD

LS<31 :00>

(/)

iii
0

WCS RAM
1K X 40
DUPE

3-2909
µSEQ
DUPN

S BUS

261

DR780 BLOCK DIAGRAMS (CONT)

SILO MODULE (DSM) M8299

DATA INTERCONNECT

B
DI CONTROL
DSMP,R,S,T

I RCVR LATCH

XMIT REG

DSMH

1IJ)

::::>
CXI

74LS161
DSMC

LOW
BANK
B5S68

HIGH
BANK
85568

DSME

DSMF

a:
IJ)

::::>

I-

CXI

IJ)

::::>

REQ 1

CXI

RE02
SBC

STALL
DDIREQ

DSMM,N,P

BYTE ROTATORS
25510
DSMK

BYTE
ROTATORS
25510 DSMB

SBUS
TK..&355

262

Cl780 REGISTERS

CONFIGURATION
2001COOO

MXT
FLT

!ill
31
30
29
27
26
23
22

BIT
15
14
13
12
11
10
09
08

RDTO
FUNCTION
PARITY FAULT
WRITE SEQUENCE FAULT
UNEXPECTED READ DATA FAULT
MULTIPLE TRANSMITTER FAULT
TRANSMIT FAULT
ADAPTER POWER DOWN
ADAPTER POWER UP

~
PARITY ERROR
CONTROL STORE PARITY ERROR
LOCAL STORE PARITY ERROR
RECEIVE BUFFER PARITY ERROR
TRANSMIT MULTIPLE PARITY ERROR
INPUT PARITY ERROR
OUTPUT PARITY ERROR
TRANSMIT BUFFER PARITY ERROR

!!.!!

FUNCTION

20
19
1B
17
16
10
09
08
07:00

COMMAND TRANSMIT TIMEOUT
READ DATA TIMEOUT
COMMAND TRANSMIT ERROR
READ DA TA SUBSTITUTE
CORRECTED READ DATA
TRANSMIT FAIL
TRANSMIT DEAD
POWER FAIL DISABLE
ADAPTER CODE (38 HEX)

XBPE
BIT

FUNCTION

07
06
05
04
03
02
01
00

UNINITIALIZED STATE
PROGRAMMABLE STARTING ADDRESS
RESERVED
WRONG PARITY
MAINTENANCE INTERRUPT FLAG
MAINTENANCE INTERRUPT ENABLE
MAINTENANCE TIMER DISABLE
MAINTENANCE INITIALIZE

3130 292B2726 2524 23222120191B171615 141312 1110090807060504030201 00

jojojojojojojojojojojojojololojolololol 1 ; ; : 1 1 1 1 1 1 ~~bNR~~~ico14
MAINTENANCE CONTROL STORE ADDRESS <12:00>

II I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
3130 292B2726 25242322212019lB17161514 1312 1110 090807060504030201 00
MAINTENANCE CONTROL STORE DATA <31 :00>

NOTES:
1. ADDRESSES SHOWN ARE FOR A Cl780 AT TR14.

263

MAINTENANCE DATA
2001C01B

Cl780 REGISTERS (CONT)

POAT STATUS
2001C900

MSE PIC MFOE

fill
31
06
05
04
03
02
01
00

FUNCTION
MAINTENANCE ERROR
MAINTENANCE TIMER EXPIRATION
MEMORY SYSTEM ERROR
OATA STRUCTURE ERROR
POAT INITIALIZATION COMPLETE
POAT DISABLE COMPLETE
MESSAGE FREE QUEUE EMPTY
RESPONSE QUEUE AVAILABLE

~~~~~~~~~~~~~~~~~~~~~~~~

POAT OUE UE BLOCK BASE
2001C904

3130 29 28 2726 2524 23222120191817161514 1312 111009 08 0706050403 02 01 00

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
FAILING ADDRESS <31 :00>

II I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I

PORT FAILING ADDRESS
2001C938

31 30 29 282726 25242322212019 181716151413 12 1110090807 06 0504030201 00

ERROR CODE <31 :00>

PORT ERROR STATUS
2001C93C

POAT PARAMETER
2001C940
PNOO
PNOl
PN02

3130 292827 26 2524232221201918 1716151413 121110 09 08070605040302 0100

lolnJoJoloJnjoJoloJololololololoJoloJololololololololololololol I ONE BIT REGISTERS
2001C908
2001C90C
2001C910
2001C914
2001C918
2001C91C
2001C920
2001C924
2001C928
2001C92C
2001C930
2001C934

PORT COMMAND QUEUE 0 CONTROL
POAT COMMAND QUEUE 1 CONTROL
PORT COMMAND QUEUE 2 CONTROL
PORTCOMMANDQUEUE3CONTROL
PORT STATUS RELEASE CONTROL
PORT ENABLE CONTROL
PORT DISABLE CONTROL
PORT INITIALIZE CONTROL
PORT DATAGRAM FREE QUEUE CONTROL
PORT MESSAGE FREE QUEUE CONTROL
PORT MAINTENANCE TIMER CONTROL
PORT MAINTENANCE TIMER EXPIRATION CONTROL

264

CNTL
BIT

£?
.....
OQ

DETAIL D
SCALE NONE

++++++++++++++++++++
+ ++ + + + + + + + + + + + + + + + + +

~~~EE~RUPT PRIORITY

BOOT TIMER

WlO

1
1
1
1
1

W13
0
0
0
0
1
1
1
1
0
0
0
0
1

1
1

g
0
0
0
0

W12

TIME

IWsiwsl LEVEL

"'---'-'~'--'-~~--=JUMPER OUT

l'i----+.+--+-i1.___--l1 =JUMPER IN

0300
05
0700

oaoo
1000
1)][

T2liil"
1400

0
1

JUMPER IN
JUMPER OUT

TR LEVEL

W2
0
0
0
0
0
0
0
0
1
1
1
1
1

-i3
g
0
1
1
1
1
0
0
0
0
1

W7
0
0
1
1
0
0
1
1
0
0
1

W4
0
1
0
1
0
1
0
1
0
1
0
1
0

TA LEVEL

1
2
3
4
5
6
7
B
9

)>
0 =JUMPER OUT
1 =JUMPER IN

:r
12

THE SELECTED TA LEVEL MUST MATCH
THE LEVEL CHOSEN BY THE Ct780 TR
ARBITRATION JUMPER

"l>

"ti

2
m

c..

s::"ti

~OTA ARBITRATION

TRl
TR2

(")

C01-57 TO C01 53 (BUS TR L
C01-63

COi 1

NOTES
1
THE SELECTED TR LEVEL MUST
MATCH THE TR LEVEL SELECTED
BY W2, W3, W4, W7
2
~~N~ IS RESERVED AS THE HOLD

LT JUMPER (Wt)
IN= 2048 SBI CYCLE BEFORE CXTMO
OUT= 512 SBI CYCLE BEFORE CXTMO
PANIC MOOE JUMPER (W8)
JN= PANIC MODE DISABLED
OUT= PANIC MODE ENABLED

DISABLE ARBITRATION (W14)
IN= NO ARBITRATION ON Cl BEFORE TRANSMISSION
OUT= NORMAL Cl ARBITRATION
EXTEND HEADER/TRAILER (W15)
IN= EXTENDS HEADER!TRAlLER
OUT= NORMAL HEADER/TRAILER
(IF W15 IS IN, W17 MUST ALSO BE IN)
Al TEA DEL TA TIME (W16)
IN= LONG DEL TA TIME
OUT= SHOAT DEL TA TIME
EXTEND ACK TIMEOUT (W17)
IN= LONG TIME OUT
OUT= SHOAT TIME OUT

BACKPLANE
MATEN LOK CONNECTIONS
SIGNAL NAME

BACKPLANE
CONNECTOR

mm ~l ~

J15

NcTNcT1 T '

J14

1T2TNcJ3

J13

1 T2 TNcT3

J16

NcT Ncl

"2T 3•4

NOTES
1 CONN J1-J6 ARE SBI BUS OUT CONN
2 CONN J7 J12 ARE SBI BUS IN CONN
3 EXTRA JUMPERS, ITEM 30, TO BE
SHIPPED IN ITEM 42, PLASTIC BAG

::c
en

DATA PATH (IDP,L0102)

SBI INTERFACE (ISi :LOI04)

PARITY
GEN/CHK

DATA
XCVRS

(BUS IB)

2901
32
32

LATCH
(DATA)

(IB IN)

BOOT
l
JUMPERS,(

DATA
PATH
CNTL

----

+5v---.,...,...

CLOCKS
ENABLES

{

BRANCH
CONDITIONS

BRANCH
REG.

NOTES: r- INDICATES A TRISTATE OUTPUT

PACICET BUFFERS (IPB•LOIOI)

+5V

NOTES'

; - INDICATES A TRISTATE OUTPUT

CHAPTER 8
PROCESSOR-SPECIFIC
DIAGNOSTICS

MICRODIAGNOSTIC MONITOR COMMANDS

Description

Command/Flag

DIAGNOSE

Initializes
and

the

program

control

starts microdiagnostic

flags,

execution

"It

test number one.

Valid qualifiers are:

/TEST:

<NUMBER> -- Dispatch to

number

specified

prior

tests)

(do

and

not

loop

the

test

execute

any

the

test

indefinitely.

/SECTION:

Dispatch

section number specified
any

prior

sections)

the

(do not execute

and

loop

the

section indefinitely.

/PASS:

Execute

diagnostics

the

passes before

returning

specified

If the number

is -1,

the

micro-

number
the

console.

execute the micro-

diagnostics indefinitely.
/CONTINUE -- This switch is used with the
or

/SECT

switch

continue

/TEST

after

the

section has been reached.

271

automatically

specified

test

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

/TEST:

<N>

execute

<M> -- Dispatch to
tests

<N>

test

through

(inclusive), and returnn to command mode.

/SECT:

<N>

<N>,

execute

<M>

Dispatch

sections

<N>

section

through

<M>

{inclusive), and return to command mode.

NOTE
In

the

•/TEST.

above
and

variations

•/sECTIOH.

the

qualifiers,

the

value of <N> must be less than or equal
to <M>. If <M> is less than <N>, testing
will

start at

<N>

and

continue

the

end.

NOTE
/TEST

and

/SECT

cannot

specified

simultaneously.

Examples:

DIAG/TEST: 2F
Dispatch to test number 2F and execute it
indefinitely.

DIAG/SECT:B
Dispatch to section number B and execute
it indefinitely.

DI AG/PASS: -1
Execute

all

indefinitely.

272

the

micro

diagnostics

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

DIAG /TEST: 2F /CONT
Dispatch to

test

2F and

start execution

of the remaining tests.

CONTINUE

Conti nu es

microd iagnost i c

without

changing

the

program

execution

clears)

the

Halt

Error

the

Halt

Error

control

flags.

Set and Clear Flags

SET/CLEAR FLAG HD

Sets

(or

Detection flag.

SET/CLEAR FLAG HI

Sets

(or

clears)

Isolation flag.

SET/CLEAR FLAG LOOP

Sets (or clears)

SET/CLEAR FLAG NER

Sets

(or

the Loop on Error flag.

clears)

the

Error

Report

flag.

SET/CLEAR FLAG BELL

Sets (or clears)

the Bell on Error flag.

SET/CLEAR FLAG ERABT

Sets (or clears) the Error Abort flag.

CLEAR FLAG LS

Clears the Loop on Special Section flag.
(Note that this flag cannot be set.)

CLEAR LT FLAG

Clears

the

Loop

Special

Test

(Note that this flag cannot be set.)

273

flag.

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

SET/CLEAR FLAG ALL

Sets

(or

clears)

all

the

flags.

SET/CLEAR SOMM

Sets (or clears)

the Stop on Micro Match

bit.

SET/CLEAR SOMM:<ADDRESS> Loads
and

address
sets

into

(or

Micromatch

clears)

the

stop

into

FPA micro sync

Micromatch bit.

SET/CLEAR FP:<ADDRESS>

Loads

the

SET STEP STATE

Sets the CPU clock to single time state.

SET STEP BUS

Sets the CPU clock to single bus cycle.

Both the SET STEP STATE and SET STEP BUS
commands cause the monitor to enter step
mode.

Step mode types the current clock

state

the

UPC

terminal input.

value,

triggered

value

typed
is

waits

for

If a space is typed, the

clock

character

and

the

current

out.

any

entered,

step

UPC

other

mode

exited.

SET STEP INSTRUCTION

Sets the hardware Single Instruction flag
and

returns

hardcore

the

monitor.

tests

are

invoked,

value of the Test PC (TPC)

274

When
the

the

current

is typed.

The

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

monitor waits for

terminal

space

the

typed,

input.

cur rent

If a
pseudo

instruction is executed and

the current

value of the TPC is typed.

If any other

character is typed, step mode is exited.

SET CLOCK FAST

Sets

the

CPU

clock

speed

the

fast

CPU

clock

speed

the

slow

margin.

SET CLOCK SLOW

Sets

the

margin.

SET CLOCK NORMAL

Sets the CPU clock speed to normal.

SET CLOCK EXTERNAL

Sets

the

CPU

clock

for

external

oscillator.

Examine Commands

The following examine commands cause the
current

microinstruction

executed

before the examine is performed, if it is
the

first

examine

since

entering

the

monitor

command

mode.

All

successive

examines

execute

any

additional

Bus

registers

not

microinstructions.

Tl-TS are destroyed during the examines,
except for the ID Bus and VBus examines.
All of the
Bus,

following

advance

the

clock

executing the command.

275

examines,
to

except V

CPTO

before

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

EXAMINE ID:<ADDRESS>

Displays the contents of the ID BUS
Register specified by <ADDRESS>.

EXAMINE VBUS:<CHANNEL>

Displays

the

VBUS

channel specified by <CHANNEL>.

Bit

the

contents

the

right

side

the

contents

the

display.

EXAMINE RA:<ADDRESS>

Displays

Scratch Pad specified by <ADDRESS>.

EXAMINE RC:<ADDRESS>

Displays

the

contents

the

Scratch Pad specified by <ADDRESS>.

EXAMINE SBI:<ADDRESS>

Displays

the

contents

the

SBI

the

contents

the

contents

the

contents

the

use

address

address.

EXAMINE LA

Displays
Latch

EXAMINE LC

Displays
Latch.

EXAMINE DR

Displays
Register.
when

(Do

not

examining

use

EXAMINE DR command.)

EXAMINE QR

Displays
Register.

276

the

contents

the

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

EXAMINE SC

Displays

the

contents

the

contents

the

contents

the

EXAMINE FE

Displays
Register.

EXAMINE VA

Displays
Register.

EXAMINE PC

Registers

the

contents

Program Counter.

Deposit Command

The deposit command

is the same as

the examine command, except that the
data

deposited

supplied by the user.

DEPOSIT

ID: <ADDRESS> <DATA>

DEPOSIT RA: <ADDRESS> <DATA>
DEPOSIT RC: <ADDRESS> <DATA>
DEPOSIT LA: <DATA>
DEPOSIT LC: <DATA>
DEPOSIT DR: <DATA>
DEPOSIT QR: <DATA>
DEPOSIT SC: <DATA>
DEPOSIT FE: <DATA>
DEPOSIT VA: <DATA>
DEPOSIT PA: <DATA>
DEPOSIT SBI: <DATA>
REPEAT <COMMAND STRING>

277

must

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS

BLKMIC

Move

the

<SCR ADDRESS>,

[SCR INDEX), <WCS ADDRESS>,

<WORD COUNT>,

[<WCS ADDRESS INDEX>)

number of 96-bit microwords from

the

<SCR

ADDRESS>,

indexed

<SCR

<WCS

ADDRESS>,

indexed

by <WCS ADDRESS INDEX>.

INDEX>,

the

WCS

starting

If an

specified, the <SCR ADDRESS> is indexed by six PDP-11 words (i.e.,
96 bits).

the

<WCS

ADDRESS>

Otherwise,

For

ADDRESS>

is used

* 6)

starts
a

with

pointer

to a

alpha

table

character,

the

<WCS

LSI-11 memory.

it is used as a physical WCS address.

example,

INDEX>

the current value of

the

index

14 8

(<SCR

would be added to the <SCR ADDRESS> to find the first

96-bit microword to load into the WCS.

CHKPNT

CHKPNT [<PASS ADDRESS>],

the error

flag,

instructions),

[<FAIL ADDRESS>]

set during a
zero,

go to

COMPARE

instruction

the <PASS ADDRESS>.

flag is not zero, go to the <FAIL ADDRESS>.

(see CMPXXX
If

the error

If neither a pass or

fail address is specified, go to the next instruction in line.

The

address of

the

instruction

appear on the typed line named TRACE:.

278

typed.

These

addresses

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

CLOCK <TIMES>

Step the system clock <TIMES> number of single time states.
<TIMES>

evenly

divisible

four,

single

bus

cycles

are

executed for each four <TIMES>.

CMPC A

CMPCA [<MODE>], <REGISTER>, <DST ADDRESS>,

(<DST ADDRESS

INDEX>]

Compares
<REGISTER>
ADDRESS>,

the

contents

with

the

console

contents of

the

location

specified

<DST

the

indexed by <DST ADDRESS INDEX>.

<MODE>

argument

false,

set

the

error

flag.

<MODE> argument is not specified, it defaults to EQUAL.

If the <REGISTER> argument is specified as IDREGLO or IDREGHI, the
register used in the compare is the ID Bus register that was read
in the most recent READID instruction.

279

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

CMPC AD

CMPCAD [<MODE>], <REGISTER>, <DST ADDRESS>, [<DST ADDRESS
INDEX>]

Compare

the

contents

and

<REGISTER>+2 with

the

console

registers

the contents of

specified by <DST ADDRESS> and <DST ADJRESS>+2,

specified
the

registers

indexed by <DST

ADDRESS INDEX>.

the

<MODE>

argument

false,

set

the

error

flag.

the

<MODE> argument is not specified, it defaults to EQUAL.

If the <REGISTER> argument is specified as IDREGLO or IDREGHI, the
register used in the compare is the ID Bus register that was read
in the most recent READID instruction.

CMPC AM

CMPCAM [<MODE>), <REGISTER>, <MASK ADDRESS>, [<MASK ADDRESS
INDEX>), <DST ADDRESS>, [<DST ADDRESS INDEX>)

Take the contents of the console register specified by <REGISTER>,
mask it with the contents of the <MASK ADDRESS>, indexed by <MASK
ADDRESS INDEX>, and compare it with the contents of <DST ADDRESS>,
indexed by <DST ADDRESS INDEX>.

the

<MODE>

argument

false,

set

the

error

flag.

<MODE> argument is not specified, it defaults to EQUAL.

280

the

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

If the <REGISTER> argument is specified as IDREGLO or IDREGHI, the
register used in the compare is the ID Bus register that was read
in the most recent READIN instruction.

The mask is performed by taking the contents of <MASK ADDRESS>,
indexed

by <MASK ADDRESS

INDEX>,

complimenting

it,

and

bit

clearing the contents of <REGISTER> with it.

CMPC MD

CMPCMD [<MODE>], <REGISTER>, <MASK ADDRESS>, [<MASK ADDRESS
INDEX>), <DST ADDRESS>, [<DST ADDRESS INDEX>)

Take the contents of the console registers specified by <REGISTER>
and <REGISTER>+2, mask it with the contents of <MASK ADDRESS> and
<MASK ADDRESS>+2, indexed by <MASK ADDRESS INDEX>, and compare it
with the contents of <DST ADDRESS> and <DST ADDRESS>+2, indexed by
<DST ADDRESS INDEX>.

the

<MODE>

argument

false,

set

the

error

flag.

the

<MODE> argument is not specified, it defaults to EQUAL.

If the <REGISTER> argument is specified as IDREGLO or IDREGHI, the
register used in the compare is the ID Bus register that was read
in the most recent READIN instruction.

The mask is performed by taking the contents of <MASK ADDRESS> and
<MASK ADDRESS>+2,

indexed by <MASK ADDRESS INDEX>,

complementing

it, and bit clearing the contents of <REGISTER> and <REGISTER>+2.

281

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

CMPPCSV

CMPPCSV <DST ADDRESS>, [<DST ADDRESS INDEX>]

Compare the contents of the PC Save register with the contents of
the location specified by <DST ADDRESS>,
INDEX>.

indexed by <DST ADDRESS

If the contents are not equal, set the error flag.

ENDLOOP

ENDLOOP <INDEX NAME>

Add the increment value of <INDEX NAME> (see LOOP instruction)
the current value of the index specified by <INDEX NAME>.
the

current

instruction).

value with

the

last

value

(specified

Compare

the

LOOP

If the current value is less than or equal to the

last value, go to the instruction following the most recent LOOP
instruction.

Otherwise, go to the next sequential instruction.

ERR LOOP

Save

the

address

the

instruction.

error

detected, and the Loop or Error flag is set (ref. subsection 4.5),
execution

is restarted at

this saved address after

instruction is executed.

282

the

IFERROR

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

FETCH

FETCH <WCS ADDRESS>, [<WCS ADDRESS INDEX>), [<WCS ROM NOP>)

If <WCS ADDRESS> is a numeric string, execute a maintenance return
to

the

location

specified

ADDRESS

INDEX>.

execute

<WCS

maintenance

return

ADDRESS>,
is

the

indexed

alpha-numeric

location specified

<WCS

string,
by

the

contents of <WCS ADDRESS>, indexed by <WCS ADDRESS INDEX>. If <ROM
NOP>

is specified,

clear

bit> of

the MCR

the

maintenance return.

FL TONE

FLTONE <DST ADDRESS>, <INDEX NAME>

Generate a 32-bit word of all zeros.

Insert a logic one in the

bit postion specified by the current value minus one of <INDEX
NAME>,

and

load

this word

into

the

location specified

by <DST

ADDRESS> and <DST ADDRESS>+2.

FLTZRO

FLTZRO <DST ADDRESS>, <INDEX NAME>

Generate a 32-bit word of all logic ones.

Insert a zero in the

bit position specitied by the current value minus one of <INDEX
NAME>,

and

load

this word

into

the

ADDRESS> and <DST ADDRESS>+2.

283

location

specified

<DST

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

IFERROR

IFERROR [<MESSAGE NUMBER>], [<FAIL ADDRESS>]

If the error flag is nonzero, type the PC of this instruction, the
test number, subtest number, and the good and bad data.
to <FAIL ADDRESS>

if the HALTD flag

is not set

(ref.

Then, go
subsection

4. 6).

If the error flag is zero, or the <FAIL ADDRESS> is not specified,
go to the next instruction.

INITIALIZE

Set

and

clear

the

CPU

the

single

Initialize
time

cycle bit, set the ROM NOP bit,

bit

the

Machine

state

bit,

set

the

Control

single

and set the Proceed bit

bus

in the

Machine Control register.

KMXGEN

KMXGEN <SRC ADDRESS>, <INDEX NAME>

Generate the KMUX address specified by the current value minus one
of

<INDEX

NAME>

and

load

into

the

microinstruction specified by <SRC ADDRESS>.

284

KMUX

field

the

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

LDIDREG

LDIDREG <REGISTER>, <SRC ADDRESS>, [<SRC ADDRESS INDEX>)

Load the ID Bus register specified by <REGISTER> with the contents
of the locations specified by <SCR ADDRESS> and <SCR ADDRESS>+2,
indexed by <SRC ADDRESS INDEX>.

If <REGISTER> is the microstack, microbreak, or WCS address,
contents of <SCR ADDRESS> is taken to be 16 bits.

the

Otherwise, it

is taken to be 32 bits.

LOADCA

LOADCA <REGISTER>, <SRC ADDRESS>, [<SRC ADDRESS INDEX>)

Load

the

console

specified

contents of the location specified by <SRC ADDRESS>,
<SRC ADDRESS INDEX>.

with

the

indexed by

This instruction loads 16 bits of data.

LOOP

LOOP <INDEX NAME>, <START>, <END>, [<SIZE DEPENDENT>)

Initialize the loop parameter specified by <INDEX NAME>
value specified by <START>.
the ENDLOOP instruction.

the

Save the value specified by <END> for
Calculate and save the increment value

for the ENDLOOP instruction with the following algorithm:

If <START> is less than or equal to <END>, set
the increment value to +l; otherwise, set it
to -1.

285

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

If <END> is an <INDEX NAME>, save the current value of that index
name as the <END> value of this index name.

If <SIZE DEPENDENT> is specified, divide the larger of <START> and
<END>

two

there

only

one

WCS

module

the

system.

Otherwise, leave them unchanged.

MASK

MASK <DST ADDRESS>, <MASK ADDRESS>

Take the contents of location <MASK ADDRESS>, complement it, and
bit clear the contents of location <DST ADDRESS> with it.

MOVE

MOVE ,SRC ADDRESS., [<SRC ADDRESS INDEX.[, <DST ADDRESS>

Move the contents of <SRC ADDRESS INDEX>

(indexed by <SRC ADDRESS

INDEX>) to the location specified by <DST ADDRESS>.

NEWT ST

NEWTST <TEST NAME>, [<TEST DESCRIPTION>], [<LOGIC
DESCRIPTION>],

[<ERROR DESCRIPTION>], [<SYNC POINT

DESCRIPTION>]

This instruction creates a test header document for the specified
arguments.

It clears the error flag, and saves the PC of the next

instruction for looping on test.

286

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

READ IN

READID <REGISTER>

Reads the ID Bus register specified by <REGISTER> and loads the
contents of it into locations IDREGLO and IDREGHI.

RESET

Executes an <LSI-11 reset instruction>.

REPORT

REPORT <MODULE NAME STRING>

Types out the module numbers of the modules specified by <MODULE
NAME

STRING>.

the

HALTI

flag

set,

return

the

Microdiagnostic Monitor.

TSTVB

TSTVB <SRC TABLE ADDRESS>, [<SRC TABLE ADDRESS INDEX>)

Load and read the VBus.

Compare the contents of the data at <SRC

TABLE ADDRESS>,

by <SRC TABLE ADDRESS

indexed

V Bus data just read.

INDEX>,

with

the

The (SRC TABLE> has the following format:

287

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

1$:

.WORD

VB USG

<CHANNEL NUMBER>,

<BIT NUMBER>,

<EXPECTED BIT

VALUE>

2$:

.WORD

<CHANNEL NUMBER>,

VB USG

<BIT NUMBER>,

<EXPECTED BIT

VALUE>

The following is an example of the <SRC TABLE ADDRESS INDEX>:

TSTVB

1$,I

If the current value of the <SRC TABLE ADDRESS INDEX> is 2,
and the <SRC TABLE> looks like the above table, the physical
<SRC TABLE ADDRESS> would be 2$.

SETPSW

SETPSW <DATA>

Load the LSI

processor

status word with

the value specified by

<DATA>.

SETVEC

SETVEC <VECTOR ADDRESS>

Set

the

LSI-11

address

specified

expected trap routine.

288

<VECTOR

ADDRESS>

the

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

SKIP

SKIP [<DST ADDRESS>]

Go to the <DST ADDRESS>.
the next test.

If <DST ADDRESS> is not specified, go to

If <DST ADDRESS> starts with the alpha character

S, go to the next subtest.

SUBTEST

Increment the subtest counter.

TYPSIZE

Use the contents of location BADDATA to determine the WCS module
configuration and type a message and
that will be tested.

the number of WCS modules

If any of the following conditions exist,

the test stream is aborted and the NER (No Error Report)
set:

WCS module count is zero

bits 3-0 are nonzero

5th K of WCS is not present

289

flag is

;FIELDS

ARRA~GED

ALFHA6ETICALLY

ACF/=0,2,70,D

;ACCELERATCR CONTROL

(")

1•JD:O

SYNC=1
TRAP=2
CONTROL:.:3
ACM/=0,3,55
P.'JP. LJP=O
A3CRT=1
PCLY.C.GNE=6
ADS/=0,1 ,47
VA=O
IBA=1

:::0

;ACCELLERAT8R-DEFENDENT CONTROL FUNCTION
;ACCELE~ATCR

MISCELLANEOUS CONTROL

;RETURN ACCEL TO MONITORING !RD

C>
2
0

(/)

:::!
(")

;ADDRESS SELECT

(")

0
2

-I

ALU/=OF,4.65,D

:::0

;ALU CONTROL FUNC7IOJS

A-3=00

A-3.RLC'..::=01
A-3-1.,C2
INST.GEF=03
A+S+1=C4
A+B=D5
A+3.RLOG=06
ORNJT=07

:::0

;INSTRUCTION DEPENDENT

"T1

: A . JR.

x:J:=,=08

A:\'.Y'<OT =O'J
l\oOT ~=CA
A<:+::>SL.C=OB
OR=:lC
Al\ID=OD
E.=OE
A=OF

m
r-

. NOT. B
; A . >.:JR. B
; A . .l.N'.:. • NOT. B
; . NOT. A

e
cm

; A . OF.. B
; A • J.!\u. B

"T1

-I

0
2

(/)

AMX/=0,2,80

; ;..MX TO ALU

l_A=O
c;..rt.x= 1
RA:~x.sx,.~2

;R~~\

t;A~X.CX1=3

;f<,'...'''

sr:::N EXTENDED ACCORDING TO cOXT(L)=O

:t.RO EXTEr·,DED.

BEN/•0,5,72,D
l'\OP=O
Z=1

ROR•2
C31a3
ACCEL=6
DATA. TYPEsS

;BRANCH ENABLE

;NO oRANCH
; A LL' Z
;LA<1>, PSL<C>,
; Al.i.J C3 I,

~--Fl~LD,

END.CP1s8
IR2-1=9
PC.MODES=S
REI=OA
SRC.PC=CA
IB.TEST=OB
MUL=OC
SlGNS=OD
INTERRU?T=OE
DECIMAL=OF
UTRAP=10
LAST.REF=11
EALU=~2

SC=14
ALU1-0=15
STATE7-4=16
STATE3-0=i7
D.BYTES=18
03-:>=19
PSL.CC=1A
ALU:s1 B
PSL.MODE=1C
TB.TEST=1D

LA<O~

;COJE FROM ACCELERATOR
;(\'A) ~COE) *• ASQC•VSRC, ASRC+OTJ
C--~G~MAL, 1--0UA~ OR COUBLE
3--A~DRESS

;(-11 MODE) •, 0 CLASS, J CLASS+C~27
;i,VAX ·;~CDE) "'• !R<2:1>
;(-i1 ~~OE) •, SM47+SMS7+DM47+DMS7, DST R=°C
;iVAX ~~OE) MODE.LSS.ASTLVL, •, •
; 1-11 ~'~DE) SRC R=PC
; c--TS Ll:Ss. 1--[~ROR
; 2--ST~LL, 3--DArA CK
; SC . ~~ E. C • D< 1 : C>
::i<31>, O.NE.O, D<31>
;AC !...'.J',.., INTERNAL INTERRUPT, INT ::E.Q
;O, C 8YTE 0 VALID DIGIT, 02-0 NEG SIGN
:~ICR~T~AP DISPATCH VEC70R
;-FP~. ~ESTED ERROR,
LCW T~O BIT5:
; O--R~~D INTERLOCK, 1--READ, REAC CH~
; 2--~RITE, 3--~EAD, ~RITE CHK
;EALJ N, EALU Z. SC.NEQ.0, SS
;SC<9:8>.NE.O, SC.GT.O, SC<9:5>.~E.O
:RLC3 E~PTY, ALU<1:0>=0, ALU<1>, ~LW<O>
; (ALU SITS FROM PREVIOUS STATE)
1

; 5 TAT!:: < 7: 4>

;ST.!lE <3:0>
;S~TES 3, 2, 1, 0 OF D.NE.O
; :i<:,: ~>

;N.Z,V.C OF PSL
;ALU N, ALU Z, lK<O>, ALU C31
;-VA<31:30>, -co~SOLE, IS+c~. KE~~EL
;PTE V~~ID, ALIGNED, CWAO, +
c--T;;A.NSLATION OK, 1--l'JR CH\( M;:) M=O
; 2--AC~ESS VIOLATION, 3--TB MlSS

~
n
:::c

0
-t

(I>

n
0
2

-t

:::c

0
r-

:::c
0

!::

.,,
m

.,,

m
2

=i
0
2

(I>

c=;
0

::!

BMX/=0,3,82

; B~1X TO ALU
A 0 !N THE BI'. SELECTED BY SC<4:0>
LB ~NLESS R=PC, THEN PC
PAC.-;ED FLOATING

V.:..St<=O
PC.OR.LB=1
PACKED.FL=2
LB=3

::D

LC=4
PC=5

KMX=6

R!3MX=7
CCK/z0,3,20,D

(")

; D OR .:;

; CONDIT ICN CODES

(I)

~;OP=O

;JCFAU!..7

1.0AD.U~C:C=1

ALU & EALU C~~JIT:ONS
;FCRCE V. ~O EFFECT ON N, Z, C

(")

;CLR

(")

;~~~~LE

SET.V.,,2
T3T.Z=3

; SET

z IF l·.Lu.--:~.o,
~

FROM

;SET N & Z

ROP=4
N+Z_ALu=S

A~X[~DT]

F~CLl

ALU, C FROM AMX CJ

;SET N AND Z F;Q~ ALU[~DT]
;CT-iEF\5 UN.:..FFECTED

C_A•U0=o

INST.DEP=7
ClD/z0,4,42
NOP=1

ACK=5
CONT=7
READ.SC=9
REAo.;-,:.•x=OB
l.\RITE.SC=OD
WR! TE. K:\lX= OF

;CONSOLE & ID

BUS CCNT~OL
; :J E F ;. LI L T ,

A lJ T 0

! 6 PE A J

:SET CS~SOLE ACKNO~LEGE FLAG
;CLE'R CONSOLE ~0DE
;RE~D :o BUS REG SELECTED BY SC
;READ ID B~S f\EG SELECTED SY ~KM~
;~RITE REG SELECTED BY SC
;~R!lE REG SELECTED BY U~MX

OK/•0,4,88,D

NOP=O
LEFT2z1
RIGHT2=2
OIV=4

LEFT=S
RIGl-iT=6
SHF=8
SHF.FL=9
ACCEL=OA
BYTE. SWAP=OB

::D

0
r::D

IF FS/1
A '- LC :1

;DEFAULT, HOLu
;~OUBLE SHIFT LEFT
;DOUBLE SHIFT RIGHT
;IF ~07 ALU CRY, SHIFT LEFT
; ELSE LO~D FROM SHF
;SHIFT LEFT
;SHIFT RIGHT
;LOA::J ~F MUX, INTE::;ER FORMAT
;LOA~
HF MUX, UNPA:KED FLOATING FORMAT
;LC~C
CCELERATOR DATA FROM OF BuS
;REcLE 7 BYTES AROUND BIT 16

0
3:

:!!

e
c
m

.,,

=i
0
z

(I)

n0
z

::i

LOAD 0 THRU DAL
LOAD DAL[SC]
LOAD DAL[SHF VAL)
i...OAD ZEROS

Q•OC
OAL.SCaOO
OAL.SV•OE
CLR•OF
OT/•0,:Z,78,0
LONG=O
llllORO=t
BYTE=2
INST.DEPaJ

DATA TYPE
CONTROLS AMX SIGN/ZERO EXTENDER, SHF AMOUNT,
CONDITION CODE SETTING, AND MEMORY REFERENCES
;CE FAULT
;I~STRUCTION DEPENDENT -;ANY OF ABOVE, OR QUAD/DOUBLE
;EX~ONENT ALU

EALU/•0,3,13
A=O
OR=t
ANDNOT=:Z
B=3
A+a=4
A-B=S
A+1=6
NABS.A-B=7

c:;

::XJ

;

2
0
en
-t

c:;
(")

0
2
-t

::XJ

r
;-ABS(A-B)

::XJ

;DEFAULT

:!!

;SHIFT VALUE

c
cm

EBMX/•0, 2, 18
FE=O
KMX=1
AMX.EXP=2
SHF.VAL=J

;EBMX TO EALU

FEK/•0,1,24,D
NOP=O
LOAD=1

;FE REGISTER CONTROL
;DEFAULT, HOLD

FS/•0,1,42
MCT=O
CID=1

;FUNCTION SELECT FOR 43-46
;ENABLE MEMORY CONTROL
;ENACLE ID BUS AND CONSOLE CONTROL

IEK/•0,2,30
NOP=O
ISTR=1
IACK=2
EACK=3

;INTERRUPT AND EXCEPTION

ACKNO~LED~E

ST 2SE INTERRUPT REQUESTS
IN E~;uPT ACKNOWLEDGE
EX E~TION ACKNOwLECGE

:!!
2
~

2
en

0
0
2

;IBUF CONTRO!.. F:...!l;CT!C•:::.
IBC/•0,4,92,D
; :;;Ee AU'-. T
MOP=O
STOP=1
;FLUS~ !6 AND LOAD IBA
FLUSH=2
START=3
CLE~.f.< SYTES 0,1 (-11 OPCODE)
CLR.0.1=4
CLEA?. SYTES 2,3 (-11 !STREAM DATA)
CLR.2.3=5
TRA~SFER BRANCH DISPLACEMENT
BOEST=7
C~EAR BYTE 0 (VAX OPCODEl
CLR.O•OC
CLEAR BYTE 1 (VAX SPECIFIER)
CLR.1•0D
CLEAR BYTES 0-3 (-11 OP & DATA)
CLR.0-3=0E
CLEAR BYTES 1-5 CONDITIONALLY
CLR.1-5.COND::OF
IF THERE IS NO SPECIFIER EVALUATION,
CLEAR NOTHING.
IF A SELF-CONTAl~ED
SPECIFIER, CLEAR IT.
IF IMMEDIATE,
ABSOLUTE, OR DISPLACEMENT, CLEAR THE
ISTREAM LITERAL.

!\.,)

ID.AODR/s0,6,58
IBUf::O
DAY.TI..,E•1

;ID BUS ADDRESS
;RD
;RD+WR

SYS.IDs3
RXCSs4
RXDB=S

;RD
;RD+WR
;RD

TXCS=6
TXDB=7

;RDHrlR
;WR

DQ:s8
NXT.PC:R=9
CLK.CS=OA
INTERVAL=uB
CES=OC
VECTO~=OD

SIR•OE
PSL=OF
TBUF=10
TBER0=12
TBER1=13
ACC.0=14

\~R

RC+WR
RD
RO+-..R
Ro ... wR
RD•WR
RDH~R

SPECIF!ER/LITERAL DATA FROM IB
TIMC: OF DAY ..•
~UST READ UNTIL STOPS CHANGING
SYS~f~ IDENTIFICATICN
CC~SCLE RECIEVE CONTROL/STATUS
CONS:LE RECIEVE DATA BUFFER
(TO-ID REGISTER)
CCNSCLE TRANSMIT CONTROL/STATUS
CCNSOLE TRANSMIT DATA BUFFER
(FRO~-ID REGISTER)
DATA PATH D/0 REGISTERS (MAINT ON~Y)
INTERVAL CLOCK NEXT PERIOD REGISTER
INTEK\AL CLOCK CONTROL/STATUS
CG~RENT INTERVAL COUNT
CF-U ER:JOR/STAT:.JS
EXCEPTION & INiERRUPT CONTROL
SOFTWA~E INTERRUPT REGISTER
PRCCESSOR STATUS LONGWORD
TRANSLATION 8~FFER DATA
TB ERROR/STATUS 0
TB ERROR/STATUS 1
ACCELE~ATOR REGISTER NO
CUR~ENT

!!
n

::l:J

z
0

....

n
0

....::l:Jz
....0
::l:J

~
.,.,

....m
c
c

m
.,.,

c=;
0

::!

ACC. 1=15
ACC.2=16
ACC.CS=17
SIL0=18
SBI.ERR=19
TIME.ADDR=1A
FAi.JLT=lB
cort.P= 1 c
MAINT=10
PARITY=1E
USTACl\=20
US;;>EAK=21
wcs. i'.0)~=22
WCS.DATA=23
;ID BUS ADDRESSES CONTINUED.
PCBR=24
P1BR=25
SBR=26
KSP=28
ESD:29
SSP=2A
USP=28
ISP=2C
FPDA=2D
D.<;V:2E
Q.SV=2F
T0=3:J
T1=31
T?=32
T3=33
T4=.'34
T5=c35
T6=36
T7=37
T8=33
T9=3"1
PCBS=3A
SC8B=3B
?0LR=3C
P1LR=3D
SLR=3E

;ACC

REClSTER #1
LERATOR REGISTER N2
LERATOR CG~TRJl;STATUS
;NU
IiEM mo;~ SBI '"tISTORY
;SEI ER~CR REG:STER
;S:31 T:·.'EOUT ADDRESS
; FAU~ T, STt.TUS
;S8i SILO COYPARATOR
L~RATOR

;A:~

;~CC

;581

~~iNTENANCE

C')

::c

2
0

;C~Ct-CE ;>ARITY
;M!c.c:cSTACK
; [;~ l C ;.; .J '~ R EA K

:::!

C')

;WR
ADDRESSES

WCS COLNTS AD~RESS
NRE RA~ LOCATIONS

;wPJ7;~~

2~-2F

SPACE 0 B~SE QEG STER
;P;G:ESS SPACE 1 3ASE QEG STER
;sv::;-t_:; SPt-C:E 8.'.>SE REG!ST R
;k:O' . ~;::L STACK PCPiTE~
;P~J~lSS

;EX~~

~iACK

POl~TER

POINTER

;SL?E~V:SOR

ST~Ck

;~SL~

PQ!~TER

STAC~

;!NTER~UPT

STACK POINTER

2
-t

::c
0

s::
.,,

r;GE'\i:Q.t,:.,

TEMPS

e
c
m

:!!
2
-t

0
2

en
CONTROL 8~0CK BASE
CONTROL GLOCK BASE
0 LENGTH REGISTER
~RO ESS 1 LENGT~ REGIS!ER
SYS E~ LENGTH REGISTER
PRrc~ss

svs-E~

PRO

~~S

0
0

2
~

J/=0,13,0,+
KMX/s:0,6,58
.8=0
. 1=1
.2=2
.3=3
.4=4
SP1.CON=5
SP2.CON=6
ZEOCJ=6
SC=7
.14=8
.A0=9
.34=0A
.28=03
.40=0C
.50=00
.3000=0E
.EF=OF
.6U=t0
.8000=11
.FF=12
.FF00=13

NEXT MICRO WORD ADDqESS, DEFAULT IS THE
FOLLO~ING MICRO WCPD
SYMBOLS ARE CEFINED BY •:•
CONSTANTS OR # FRO~ FK
; ,,9 FRO~ FK
;1r1

FR,J\"

;"2

F'l.:::~1

; ff 3

F ;.;-=,1'.

i'K

; #4

FRC\1

;SP~CIF:ER 1 CONSTANT
;SECIFIER 2 CONSTANT {-11 MODE)
; Q~ ZEROS {VAX MODE)
;SCl9:0} FROM FK
;8 - 3F: CONSTA~TS (1 CYCLE SETUP IF ALU IN ARITri f,10DE)
;DECIMAL VA~~E OF CONSTANT
;20
(AF,JL,MH)
; 160
{AF ,JL)
;52
(AF)
;40
(AF)
;64
{AF,JL,MH,TF)
;80
(AF ,MH)
;12288 (JLJ
; 239
( J'._)

; 1 2 [?
;-32":'68
;25:,

{MH, TF)
(MH,~~.JL)

.3F=15
.7F=16
. 7=1 7
. F= 18
. 1O=19
.FFE8=1/,
.FFF0=18
.FFF8=1C

;63
; l 27

.2C=1D

.30=1E
.18=1F
.3•F=20

z
0

Cf)

....

n
n
0

....z

:JJ

0
r-

:JJ

s:
"T1

(AF)
{MH,AF,TF)

;-1 G

m
r-

;30

;-8

(AF, J L, r.:H, T F)

;-256

; 16
;-24

(AF)

• 1E=14

;7
;~5

:JJ

c
c
m
"T1

(AF,MH)

(MH,CM,AF,TF)
(MH,AF,JL,TF)
r.~H, TF)

CM, J L, TF , Mi-i)
CM,TF,r:H)
C\1, J L, Mh, T F)

CM,AF,t>1H,TF)

( r.'H , AF , T F)

023

(CM)

z
=i
0
z
Cf)

n
0
z
::i

.C=21
.0=22
.1F=23
.1F00=24
.80=25
.E003=26
.7C=27
.FFE0=28
.60=29
SPARE=2A
.DFCF=2B
.FFEF=2C
.FFF1=2D
.19=2E
.FFF9=2F
KMX DEFINITION CONTINUED
.FFFF=30
.88=31
.3030=32
.F0=33
.C0=34
.6=35
.9=36
.FFF6=37
.FFF5=38
.1 A=39
.24=3A
.1 B=3B
.FFFC=3C
.A=3D
.7E=3E
;
SPt.RE=3F
MCT/=02,6,42,D
TEST. RCHK=OO
ME'll.N0?~02

TEST.~JCH~=04

WRITE.V.NJCHK=CA
WR I TE. V. wCHf<.=CC
LOCKWR!TE.V.XCHK=OE

12
13

31
7936
176
124

-32
96
;?

;-17
;-15
;25
;-7

(CM, J L , TF , MH)
(TF)

(AF,JL,MH,TF)
(JL,MH)
{ !\~t-l)

~
:a

(CM)
(AF)
( JL)

>
G')

(TF)

(JL)
(AF)
(AF)
(AF)
(AF)

~
0

-I

;-1

; 136
;240
; 192
;6
:9
;-10
;-11
;26
;36
;27

;-4
; 10
; 126

(MH,JL,TF)
(AF)
( TF)

0
r-

::a

(TF)

( TF ,MH)
(CM,JL,TF)
(CM)
(CM)
(CM)
(CM,AF,TF)
(CM,MH)
(CM,AF, TF)
(CM,TF,MH)
(AF,MH)
(AF,TF)

.,,
m

e
cm

.,,

z
-I

; MEMORY CONTROL
;TEST T8UF WITH READ CHECK
;NEITHEQ CPU NOR 19 GETS MEM CYCLE
;TEST TSUF WITH WRITE CHECK
;~_.RITE,
INHIBIT TRAPS
;~RIT~.

NORMAL VARIETY

;INTERLOCK

~RITE,

VIRTUAL ADDRESS

0
z

n0
z

Vt.,R!ETY
;NHIBIT TRAPS

t,CJR(.~AL

R AD.V.:; hf\=10

;RE_,,

R :.o.v.'.; :HK"12

;;E D,

R AD.'J ..~ .... ~.=1-l

;RO. ) FOR ~~OD!F'Y
;RE J, CHECK CO~TRD~LED

R AD. 1; . • : H'< = 1 6
K AD • '! . N ,; r:: (, 1 3

l~~

~.EW

INSTr<~CTIO'J

LOC~~EA).J.~:C~~=1A

;!3E
; 0
;If'..

o~<.:Cr<

READ,

LOCK R '.: .l '.) .'.· ••~ ._:. H.<. = 1 C

;It<'~R.CCh

i<UD,

7A ~DES

(")

ev IBUFF~R
STREAM

l~STR~CTlON

BUFFE~

l"JH13li' CHECK
VARIETY
ALL 381 ACTIVITY

;s:~?

"J;:1A.L

I N'J AL'.:; A - ;: = 2 4

;?.ES'.:T ~B!
;CLEAR :ACHE ENTRIES

VALI:.l.~C.=~5

:M::..~:~lAGNQSTIC

EXTwt;;T:0.;:>=25

;EX~~~:~D

S8I.h:"~·~~JAM=22

!;;

~RITE

FORCE

;,,, iTE,

LOCK'l.fi!TE. P=2E

;!~Tl~LSC~

READ."=3~

;P~t.C;,

TO CLEAR MOS

READ. r·,~ ..~'...'!.=36
LOCKRi:..:.J.c=3A

: ::,-:-:;;;~,PT

ALLOiN.!8.r<EAD=3E

;GI~E

W~ITE,

ERR~~S

:C~EAT=

CH'<. ~LT .:Pq=02

;UiRA~

:c
0
r:c

-I

NEW ~SL FOR CHM
lF ALU<15>=1, ALU<14:7>=0

c~~.o:.:.ASDM.'-'03

;THIS s;ATE IS INSTRUCTION

IRD=04

DECOD~

LDAD.ST:.~E.=25

CLR. FPO=C

CJNDIT!ON CODES FROM ACCELERA-CR
r~p RLOG STACK)
:~LE~R 0SL<FPD> BIT

SET. F;:::.:C

; SET

;TA~E

LQAD. A'...C. '.'..C=06
REAJ.=<LCC. 07

CLR.NEST.

~.;:i=CA

SET.NEST.

"M.=OC:!

SEC:J'•[;.;:,E

=OC

RETR1.!1.C.

RAP=OJ

:(A~D

ERROR FLAG IN CPU STATlS
S.:.'.'E
;OF '_;,;!.LIGNE'.J DATA REFEPENCE
;APPLY SA~ED CONTEXT, INHIB:T TR~~S
;A?P~y SAVED cc~~EXT TO THIS REF
;A_LQ~ ~SE OF FULL 32-BIT ADDRESS
;CL~

RETRY. i~;.. =CE

INH.C'V1.AD R=OF
FCKi=0,3,32,D
NOi'=O

S.:. ~.~ E
~ESTED

; SET

;ADDRESS CCJNT

CCNT=iC~

; '.;E:.F~.U ~ T

::!
(")
0

MSCi=0,4,26,D
,:f-_ff,ULT

2
0

RE!..:>

READ. PHYSICAL
13 A CYCLE IF IT WANTS ONE

NOP=O

C')

(")

;:~:E~~CCK

CHK. CHr,,= 01

FHYSlCAL

::HYS!C.!.L
St..:~·~~ARY

(I)
VA~:D

PriYSICAL

V<RITE..F=24

s:
"T1

m
r0
0

m
"T1

0
2

(I)

0
0
2

::!

PC_'vA=1
PC IBA=2
VA+4=3
PC+1 =4
PC+2=5
PC+4=6
PC+N=7

PC_t.-C•1
PC_~·C+2

N IS DETERMINED BY

IN~T~

9~FFER

:O:CFt.L.:i..";, r'OLD
;DO~GLE SHIFT LEFT 2
;DO~BLE SHIFT R!GHT 2
; LC.r.D SHF, INTE.:.ER FCRMAT
;LClC S~F. UN?ACKED FLOATING FOR
;~ECIM~L CO~STA~T = 6'S IN EACH ~;53~E
; FOR ~w!CH ALU CRY OUT IS FALSE
;LDlC .:.ccELERATOR DATA FROM DF B~S

ACCEL=OB
O=OC
IO=OE
CLlhOF

SGN/•0,3,48,D
NOP=O
LOAO.SS=1
SS. F~ ..::..1. 50=2
NOT.SC=3
SO.FRCM.55=4
SS.XGR.A:..'.J=S
ADD • .S1.;S=6
CLR.so ... SS=7

P:::_PC .. 4
PC_PC+N,

QK/•0,4,51,D
NOP=O
LEFT2=1
RIGHT2=2
LEFT=5
RIGHT=6
SHF=S
SHF.FL=9
DEC.CON=OA

RAMX/•0,1,77,0
C=O
0=1
RBMX/•O, 1, 77
Q=O
0=1
SCK/•0,1,23,0
NOP=O
LOAD=1

3::

n
:::D

v:.._v:..+~

;DATA PATH ~IXER

; :..O.:.i:.

r D BUS

; L.C.\u

;::ERO

;D~r·;.;...·LT,

-t
:::D

3::

SAME EIT AS RAMX

HOLD

S~X<09:00>

;DU l.J:..T

;SD_ L~<15>.
;CLE: R GOTH

I""

c
cm
'Tl

z
=i
0
en

; s:_ ~:

~~<15>,

L0'15>

; SS .. D
;SJ_ CT SD
;3~_

(')

'Tl

;SIGN CONTRO!..S
:SS

-t

CQ~T~CL
;LC~D

I""

;DEFAU:..T

;SC REGISTER

)>
G)

:::D

A~X

;DATA PATH ~!XER TO SMX.

ss_sS.XOR.ALU<15>
SS_SS.XOR.ALU<15>.X~~.IP<1>

n
0
z

::!

SHF/z0,3,85,D
ALU=O
LEFT=l
RIGHT=2
ALU.DT=3
RIGHT2=4
LEFT3=5

;ALU SHIFTER CONTROLS

SI/•3,3,55,D

;SHIFT INPUT CONTROLS

;:J[Ft,i.;i..T' SHF ALU
;SHF _A'-U( L1), INSEqT SI CNTL
;SHF_ALU(Rl), INSERT SI CNTL
;SHF_ALU(DT: LO, L1 , L2, L3) , INSERT 0
;3HF _ALU(R2), INSERT SI CNTL
;SHF_ALU(L3)

SMX/ = 0 , 2 , 1 6
EALU=O
FE=1
ALU=2
ALU.EXP=3
SP0/=0,7,35,D
NOP=O
LOAD.LC.SC=6
WRITE.RC.SC=7

;

;MIXER TO SC

SHF

PSL<N>
ALU 31
0
0

031
00
0
0

ALU C31
Q31
D31
0

n
n

031
0

ALU C31
031
ALU 0' 1 0
ALU 0, 1 1

:JJ

en
~

-f

r
:JJ

;EALU <9:0>
;FE<9:0>
;Ali..!<09:00>
;ALU<14:Q7>

!!
m
r

;SCRATCH PAD OPCODE, 7 BITS

0
0

;DEFAULT

;LOAD LC, ADR=SC[03:oo]
; \~RI TE RC, ADR=SC[03:00]

SPO.AC/=0,4,38
LOAD.LAB=1
LOAD.LA=2
WRITE.RAB=3

;4 FUNCTION BITS OF SPO FIELD
;LOAD LA, LB FROM R(ACN)
;LOAD LA_RN, HOLD LB
; wR I TE RA, RB (ACN)

SPO.ACN/=0,3,35

;AC NUMBER IN SPO FIELD
RA
;VAX MOCE
SP1 R
;0
;1
SP2 R

SP1. SP1 =0
SP2.SP2=1

0
0
C>

DIVD=O
ASHR =1
ASHL=2
ZERD=3
SPARE=4
DIV=5
MUL+=6
MUL-=7
0

n
:JJ

3
0

RB
SP1 R
SP2 R

n
0
z

SP2.SP1=2
PRN=3
PRN+1=4
SC=S
SP1+1=6
SPO.ACN11/=0,3,35
SRC.SRC=O
DST.DST=1
DST.SRC=2
;SRC.SRC=3
SRC. OR .1 =4
SC=S

2
3
4

5
6

SP2 R
PRN
PRN+1
SC<03:00>
SP1 R+1

;AC NUMBER IN SPO FIELD -- 11 MODE
RA
;-11 MODE
;O
SRC R
;1
DST R
;2
DST R
;3
SRC R
;4
SRC R .OR.
SC<03:00>
;S

SP1 R
PRN
PRN+1
SC<03:00>
SP1 R+1
RB
SRC R
DST R
SRC R
SRC R
SRC R .OR. 1
SC<03:00>

;SCRATCH PAD FUNCS WITH LOW 4 BITS OF SP AS ADR
;LOAD LC, ADR=SPO.RN
;WRITE RC
; LOAD LA, LB
;~RITE RA, RB
;LOAD LA, LB[R1]. AND WRITE RC[RN]
LUA~.LAb1.WRITE.RC=6
;LOAD LC[RN], AND WRITE RA, RB[R1]
LOhD.LC.~RITE.RAB1=7
SPO.RAB/=0,4,35
;RA/RB LOCATIONS
RO=O
R1=1
R2=2
R3=3

SPO.R/=0,3,39
LOAD.LC=2
~RITE. RC=3
LOAD.LAB=4
WRITE.RAB•S

R4=4

R5=5
R6=o
R7=7
AP=OC
FP=OD
SP=OE
R15=0F
SPO.RC/=0,4,35
TO=O
T1=1
T2=2
T3=3

0
:::D

;

-4

n
0

0
2
-4

:::D

r:::D

.,,3::
m
r-

e
c

.,,

m
; R1 2
; R13
;R14
;R15
; RC LO CAT IOr-.;S

LIST POINTER
FRAME POINTER
STACK P:JINTER
PC, TO SOFTWARE, SCRATCH TO UCODE

ARGL~ENT
STAC~

n0
2

::!

T4=4
TS=S
T6=6
T7=7
LC.S\/=8
VA.SV=9
PTE.VA=OA
PTE.PA=OB
PC.S\/=OC
SC.SV=CO
llA.REF=OE
MBI T. VA=Cr
PTE.MASK=OF

~
n

:a
:MEM MGMT SAVES LC HERE

(I)

n
n
0

CONTROL
;GEFAU:..T

;PUSH

OF TrlIS MICROINSTRUCTIC~
; C"• fO UST f\CK
;'GR" TCP OF USTACK TO UPC

RET•2

;

AND

~=c

~QP

~STACK

;REPLACE LGW 8 BITS OF NEXT
; UPC ~!TH SPECIFIER DECODE FROM
; I~STKwCTION B~FFER

SPEC=3

:a
0

....

:ti

3J:

VAK/=0, 1,25,0
NOP=O
LOA0=1

;D!:.FAULT
;L.CAD VA

....m

c
c
m

.,,

;ALU_O .•. THRU ALU_D.ANO ...
ALU_O(AI
ALU_O(]O
AL.U_O-D
ALU_0-0-1
ALU_O+O
.UU_O-K[ J
ALU_O-K[ ]-1
ALU_O+K[]
ALU_O+K[ ]+~

;SUBRO~T!NE

SUB/•0,2,64,0
NOP=O
CALL=1

"AMX;RAMX.OXT,DT/LC~G.A:..~/A"

"ALi.J,'@1 .AMX;RAMx.ox; .LC'IG.B~>\X;REMX,F<BMX/0"
"A MX, Rt.MX. 0 XT, DT / LO~~G, R3~~.( /), B~.1X / RBMX, ALU/ A-B"
"AMX;RAMX.OXT,OT/LO~G.R3Mi/D,8~X/RBMX,ALU/A-B-1N
"Ar.ix/ ~MAX. OXT. DT ,' LC~:G. R2\1X/~. !;'.'.'X/ Ro'..lX 'ALU/ A+B.
"A~X RA~X.OXT.DT;LONG ~~X/~1 ,s:x/KMX,ALU;A-B"
"K~X ~1.SMX/KMX,AMX,R ~X.OXT,01/LONG,ALU/A-B-1"
"K~X

@1.B~X/KMX,AMAIR

MX.CXT,DTILQNG,ALU/A•B"

"VMX

@1 .B~X/KMX,A~X!~

~X.OXT,DTILONG,ALU/A+B+1"

=i
0
z

(I)

n0
z

::!

ALU O+LB+1
"AMX
ALU:O+LC
"AMX
ALU_O-LC
"AMX
ALU_O+LC+1
"~MX
ALU 0-LC-1
"AMX
ALU:O+MASK+1
"AMX
ALU_O+Q
"AMX
ALU_o-o
"AMX
ALU_O-Q-1
"AMX
ALU_0+0+1
"AMX
ALU -1
"AMX
ALU:O
"RAM
ALU_O.OXT[)
"RAM
ALU_D. OXT [].AND. K[ l

RAMX.OXT,DT/LONG,EMX L5,ALU/A+B+1"
RAMX.OXT,DT/LGNG,6MX LC,ALU/A+B"
RA~X.OXT,DT/LONG,e~x LC,ALU/A-B"
RA~X.OXT,DT/LONG.2~X LC,ALU/A+B+1"
nA~X.OXT,0T/l0NG.3~X 'LC,ALU/A-B-1"
RAMX. OXT, OT/ LG:;-:;, E~1IX /','A SK, ALU/ A+B+ 1"
RAMX.OXT,OT/LC~G.RB~X/~,6MX/RaMX,ALU/A+B"
R~MX.OXT,DT/LONG,RB~X/Q,B~X/RE~X.ALU/A-B"
RA~X.OXT,OT1LO~G,RS~X Q.B~X/RBMX,ALU/A-B-1N
~AMX.CXT,OT/LONG.RS~X/Q,B~X/RBMX,ALU/A+B+1"
RAMX.OXT,OT/LO~G.ALU/NOTA"

/D,AMX/RAMX,ALU/A"
/0,AMX/RAMX.OXT,DT/@1,ALU'A"
"RAMX/D. AMX,'RA'l1X. ex T. DT ,'@11. KMX/~2. 6MX/KMX. ALU/ AND"

A~U_D.OXT[).AN~NJT.K[)

"ALU/A~~NOT,AMX!RAMX.OXT,DT/Ol,RA~X/D,BMX/KMX,KMX;S2"
"R A:\1X,'D. ;.,,~x/RAMX. Q,l{f. OT/'.?' 1 • K~.1x; ~2. BMX/l\MX. ALU/ A+S"

ALU_D. ox T [ l +K [ l
ALU_D.OXT[]-K[] "RA~x/D.~~X/RA~X.OXT,CT/~1,kMX1'2,SMX/KMX,ALU/A-B"
ALU_D.OXT[]+LC "ALU/A~6,A~X/RA~X.OXT,JT;A1 ,Rh~X/0,B~X/LC"
ALU_D. OXT [ J+Q
"A:..:.;/ A+9, A~•'X/RAiv'l(. '.'JX T, OT,'? 1 , "A'.1</D, SMX/RBMX, RBMX/Q"
ALU_D.OXT[]-Q
"~A~X/~.AMX/RA~X.OXT,DT. 1 ~1 ,RSMX,Q,OMX/RBMX,ALU/A-B"
ALU_D.ANO.K[]
"~A¥X/C,AMX/RA~X.KMA 1 ~1 ,B~X.K~X,ALU/AND"
ALU_O.AND.MASK
"RAMX/D,A~X/~AMX,8MX/~AS~.ALJ 1 A~D"
ALU_D.ANDNOT.K[)
"RAMX/D,A~X/R~MX,~MC S1 .B~X/KMX,ALU/ANDNOT"
ALU_D.ANDNOT.MASK
"RAMX/D,AMX;RA~X.6~X,WASK,ALU/A~DNOT"
ALU_D.A~DNOT.Q

"RAMX/D,AMX/RAMX,RBMX/0,BMX/R~MX,ALU/ANDNOT"

;ALU_D(B) ... THRU ALU_D.XOR ..•
ALlJ_D( B)

ALU_D( ]K()
ALU_D+K(]
ALU_D-K()
ALU_D+K[]+1
ALU_D-K( )-1
ALU D-LB
ALU=D[]LC
ALU_D+LC
ALU_D-LC
ALU_D-LC-1
ALU_D+LC+PSL.C
ALU_D.O!LK[)
ALU_D.OR.LC

"RBMX/D.BMX/RB~X.ALU/B"
"RA~X/D,AMX/RAMX,KMX/~2.9~\;kMX,ALU/@1"

"R l\'.iX/D. A.MX; RA~.1~' KlllL<; g.1 'B!l.X. Kr.~x. Al..U/A+B"
"RA~X/D,AMX/RAMX,K~X/~1,BMX KM,,ALU/A-B"
"RA~X/D,A~X;RAMX,KMx,:•1.evx,~YX,ALU/A+B+t•
"RAMX/D,A~X/RA~~.K~X/@1,S~X,~~(,ALU/A-B-1N

"RA~x,o.~~X/PAMX,6~X/L8,ALU/~-e·

"RA\'X/D. A'.v'IX/RA:.ix. e·.: ..; /LC. AL'.J, f 1"
"RA~X/D.AMX/RA~~.S~X/LC,Al..U A+S"
"RAMX/D,ArJ:X/RAMX, 2MXiLC,,,!..U, ~-i3"
"RA~X/O,AMX/RAMX,El/X/LC,ALL,A-B-1"

"R M11X/D, A!l.~X/RA"ilX, 5:/.{ / !..C, ALU,'',\,.S+PS L. C"
• RA'.'X/D. AMX/RA~11:,. K'.::</~1 . s~1x,1 kM I(. ALU/OR"
"RA~X/D,AMX/RAMX,8~X/LC,ALU;CR"

3::

c:;
:::D

5>
C)
z
0
en

-I
:::D

r:::D

,,3::
m

e
c
m

,,
z

0
z

0
0
z
:'.!

ALU_D.ORNOT.WASK
"RAMX/D,A~X, RAMX,5MX,'MASK,ALU/ORNOT"
ALU_D.OR.Q
"RAMX/D,A~X/RA~X.R3MX;Q,3MX;RB~X,ALU/0R"
ALU_D[)Q
"RA~X/D,AMX/RAMX,R8MX/Q,B~Xi~9MX,ALU/@1"
ALU_D+Q
"RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX,ALU/A+B"
ALU_D-Q
"RAMX/D,AMX/RAMX,RGMX,'Q,BMX/RSMX,ALU/A-B"
ALU_D+Q+1
"RAMX!D,AMX/RAMX,RB~X/Q,BMX RSMX,ALU/A+B+1"
ALU_D-Q-1
"RAMX/D,AMX/RAMX,R3~X/Q,B~X:RB~X,ALU/A-B-1"
ALU_D+Q+PSL.C
"ALU/A+B+PSL.C,A~X/RAMX,BMX,RBLlX,RBMX/Q,RAMX/0"
ALU_D.SXT[]
"RAMX;D,AMX/RAMX.SXT,DT1~1,ALU/A"
ALU_O.SXT[).AND.K[)
"RAMX/D,AMX RAMX.SXT,DT/@1,KMX/P2,BMX/KMX,ALU/AN0"
ALU_D.SXT[)+K() "RAMX/~.A~X/RAMX.SXT,DT/@1,K~X,~2.BMX/KMX,ALU/A+B"
ALU_D.XOR.K[)
"RA~X;D,AMX/RAMX,K~X/@1 ,BMX:KMX,ALU/XOR"
ALU_D.XOR.LC
"RAMX/D,AMX/RAMX,B~X/LC,ALU/XJR•
ALU_D.XOR.Q
"RAMX/D,AMX/RAMX,RE~X/Q.BMX/RBMX,ALU/XOR"
ALU_D.XOR.R[)
"RA~X/D,AMX/RAMX,SPO.R/LOAD.LAB,SPO.RAB/@1,BMX/LB,ALU/XOR"
ALU_D.XOR.RC[]
"RAMX/D,AMX/RAMX,SFO.R/LOAD.LC,SPO.RC/~1,BMX/LC,ALU/XOR"
;ALU_K ... THRU ALU_PC ...
ALU_K[)
"KMX/@1,BMX/KMX,ALU/8"
ALU_LA
"AMX/LA,ALU/A"
ALU_LA.AND.K[J
"AMX/LA,KMX/@1,BMX/~MX,ALU/AND"
ALU_LA.ANDNOT.K[]
"AMX/LA,KMX/@1 ,BMX/KMX,ALU/ANDNOT"
ALU_LA.ANDNOT.MASK
"AMX/LA,BMX/MASK,ALU/ANDNOT"
ALU_LA.XOR.LC
"AMX/LA,BMX/LC,ALU/XCR"
ALU_LA[)D
"AMX/LA.R8MX/D,6MX/RB~X,ALU/P1"
ALU_LA-D
"AMX/LA,RBMX/D,BMX/RBMX,ALU/A-8"
ALU_LA-D-1
"AMX/LA,RBMX/D,BMX/RBMX,ALU/A-3-1"
ALU_LA+K[)
"AMX/LA,KMX/@1,BMX/KMX,ALU/A+B"
ALU_LA-K[]
"AMX/LA,KMX/~1,BMX1KMX,ALU/A-B"
ALU_LA+~[)+1
"ALU 1 A+5+1,AMX/LA,BMX/KMX,KMX/@1"
ALU_LA+K[].RLOG "AMX/LA,KMX/~1 .s~x/~MX,A~U/A+B.RLOG"
ALU_LA-K[].RLOG "AMX/LA,KMX/~1,BMX/KMX,ALU/A-B.RLOG"
AL~_LA[)LB

"AMX 1 LA,E~X/LB,ALU/~1"

ALU_LA+LC
ALU_LA(]Q
ALU_LA+Q
ALU_LA-Q
ALU_LA-Q-1
ALU_LB
ALU_LC

"ALU/A+B,AMX/LA,BMX'LC"
"AMX;LA,RB~X/Q,B~X/RSMX,ALU/@1•

"ALU!A+8,AMX/LA,BMX/RBMX,RBMX/Q"
"ALU/A-B,AMX/LA,BMX/RBMX,RBMX/Q"
"ALU/A-6-1 ,AMX/LA,BMX/RBMX,RBMX/Q"
"BMX/LB,ALU/8"
"BMX/LC,ALU/B"

~
n
~

~
Q

n
0

c
c

m
~

30
z

n0
z

ALU_NOT.D
"ALU. i~CiTA,AMX/RAMX,RAMX/D"
ALU_NOT.RC[)
"SPO.R;LOAD.LC,SPO.RC/@1 ,BMX/LC,AMX/RAMX.OXT,DT/LONG,ALU;ORNOT"
ALU_PACK.FP
"BMX/PACKED.FL,ALU/B"
ALU_PC
"SMX/PC,ALU/B"
;ALU_Q •.. THRU CACHE_ ..•
ALU_Q
"RAMX/Q,AMX/RAMX,ALU/A"
ALU_Q.OXT[)
"RAMX/Q,AMX/RAMX.OXT,DT/@1,ALU/A"
ALU_Q.OXT().ANDNOT.K[)
"ALU/ANDNOT,AMX/RAMX.OXT,DT/@1,RAMX/Q,BMX/KMX,KMX/@12"
ALU_Q.OXT[].OR.K[]
"ALU/QR,AMX:RAMX.OXT,DT/@1,RAMX/Q,BMX/KMX,KMX/•2"
ALU_Q.QXT[].OR.D
"ALU/OR,AMX/RAMX.OXT,DT/@1,RAMX/Q,BMX/RBMX,RBMX/D"
ALU_Q.OXT(]+D
"ALU/A+B,AMX/RAMX.OXT,CT/@1 ,BMX/RBMX,RBMX/D,RAMX/Q"
ALU_Q.OXT[]+D+1 "ALU/A+B+1,AMX/RAMX.OXT,DT/~1,B~X/RBMX,RAMX/Q,RBMX/0"
ALU_Q.OXT[]+K() "ALU/A+B,AMX/RAMX.OXT,DT.'@1,RA~X/Q,BMX/KMX,KMX/@2"
ALU_Q.OXT[]-K[) "ALU/A-8,AMX/RAMX.OXT,DT/~1.RAMX/Q,BMX/KMX,KMX/@2"
ALU_Q.AND.K()
"RAMX/Q,AMX/RAMX,KMX/@1,BMX;KMX,ALU/ANO"
ALU_Q.ANDNOT.MASK
"RAMX/0,AMX;RAMX,BMX,WASK,ALU/ANDNOT"
ALU_Q.ANDNOT.K[]
"RAMX/Q,AMX'RAMX,KMX/@1,BMX/KMX,ALU/ANDNOT"
ALU_Q(B)
"RBMX/Q,BMX/RBMX,ALU/6"
ALU_Q[)D
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/RBMX,ALU/@1"
ALU_Q-O
"RAMX/Q,AMX/RAMX,RBMX/D,BMX;RBMX,ALU/A-B"
ALU_Q-0~1
"ALU/A-B-1 ,AMX/RAMX,RAMX/Q,BMX;RBMX,RBMX/D"
ALU_Q+K()
"RAMX/Q,AMX/RAMX,KMX/@1,BMX/KMX,ALU/A+B"
ALU_Q-K[]
"RAMX/Q,AMX/RAMX,KMX/@1,BMX/KMX,ALU/A-B"
ALU_Q+K()+1
"ALU/A+B+1,AMX/RAMX,RAMX/Q,BMX/KMX,KMX/•1"
ALU_Q+LB
"RAMX/Q. AMX/RAMX, Bi>lX/LB, ALU/ A+B"
ALU_Q-LB
"RAMX/Q,AMX/RAMX,BMX/LB,ALU/A-8"
ALU_Q+LB+1
"RAMX/Q,AMX/RAMX,8MX/L3,AL~/A+B+1"
ALU_O+LC
"RAMX/Q,AMX/RAMX,B~X/LC,ALU/A+B"
ALU_O-LC
"RAMX/Q,AMX/RAMX,BMX/LC,ALU;A-8"
ALU_O+LC+1
"ALU/A•9+1 ,AMX/RAMX,RAMX/Q,BMX/LC"
ALU_Q+MASK
"ALU/A+B,AMX/RAMX,RAMX/Q,BMA/MASK"
ALU_Q-MASK-1
"ALU/A-9-1,AMX/RAMX,RAMX Q,BMX/MASK"
ALU_Q.OR.K[)
"RAMX/Q,AMX/RAMX,KMX/@1,8MX;KMX,ALU/0R"
ALU_Q.OR.LC
"RAMX/Q,AMX/RAMX,BMX/LC,ALU/OR"
ALU_Q.ORNOT.K[) "ALU/ORNOT,AMX/~AMX,RAMX/Q,BMX/KMX,KMX/~1"
ALU_Q.SXT[)
"ALU/A,AMX/RAMX.SXT,DT/~1.RAWX;Q"
ALU_Q.SXT().ANONOT.K[]
"ALU/ANDNOT,AMX/RAMX.SXT,RAMX/Q,BMX/KMX,KMX/@2,0T/@1"
ALU_Q.SXT[)+K[] "RA~X/Q,AMX/RAMX.SXT,DT/©1,KMX/@2,BMX/KMX,ALU/A+B"
ALU_Q.SXT[)+LB "RA~X/Q,A~X/RAMX.SXT,DT/@1 ,EMX/LB,ALU/A+B"

s::

c:;

:;
C)

2
0
en
-t

c:;
n
0
2

-t

s::
'Tl

m
r

c
c

m
'Tl

=i
0

2
en

c=;
0
2

.::!

ALU_Q.SXT[)+PC "RA~X/C.AMX RA~X.SXT,DT 1 ~1.5~X PC,ALU/A+B"
ALU_Q.XOR.D
"RAVX1Q.AMX RAMX,8~X:RS~X.RB~X.D,ALU/XOR"
ALU_Q.XOR.K[)
"RAMX/Q,AMX RA~X,K~X/Jl,B~X1KM~.ALU/XOR"
ALU_Q.XOR.LC
"RAMX/Q,AMX RA~l.X,8V~/LC,ALU. XCR"
ALU_R[)
"SPO.R1!..0A::l.LA6,SPJ.RA8/•§.1,AMX/LA,ALU/A"
ALU_R[).AND.K[] "SPO.R;LCAD.LAB.S~O.RAS1@1,A~X LA,KMXl@2,B~X/KMX.~LU/AND'
ALU_R[).ANDNOT.MASK
"5~0.R/LOAD.LA9.SPO.RA3!01,AMX/LA,BMX/MASK,ALU/AN:~OT"
ALU_R(03T)
"SPO.AC/l0AD.LAB,SDG.AC~ 1 1/DST.DST,AMX/LA,ALU/A"
ALU_R[ ] . OR. K[ j
"SPO. R/ LOAD. LAB. SJ:-J. RAE' .P:1 , AMX, LA, KMX/@2, 9MX/KMX, ALU/OR"
AL:.J_R[ ) • ORNOT. K() "A LU/ORNOT, AMX/ LA, 8~11X,'hl\'X, SPO. R/ LOAD. LAB, SPO. RAa/©>1 , KM>.,· -""2"
ALU_R[] .XOR.K[) "SPQ.R/LOAD. LAB,SPJ.R.:.3:~'-1 ,.:..',;x, LA,KMX/~2,BMX/K"llX,ALU/XOR"
ALU_RC[]
"SPO.R/LOAD.LC,SPQ.qC/iil1.3~11X/LC,ALU/B"
ALU_RC(SC)
"SPO/LCAD.LC.SC.BMX1 LC.ALU/3"
ALU_R(SP1)+K(].RLOG
"SPO.AC:LOAD.LAE,SPO.ACN/SP1.SP1,AMX/LA,KMX/@1,B~X/~MX,ALU/A+8.RLOG"
CACHE_D[]
"VAK/NOP,MCT/WRITE.V.~CriK,DT,~1 .DK/NOP"
CACHE[]_D
"VAK/NOP,MCT/WR!TE.V.WCH~.~sc:~1 ,DK:No 0 •
CACHE_O.INST.DE?
"VAK/NOP,MCT/WRITE.V.~CHK,DT/INST.DEP,DK/NOP"
CACHE_D[).NOCHK "VA~/NOP,MCT/WR!TE.V.N:CHK,DT,~~ ,DK/NOP"
CACHE.c_o[J
"VAl<./NCP,MCT/WRITE.P,::JT/!Pi1,DK/NwP'
CACHE_D[].LK
"VAK/NOP,MCT/LOCKWRITE.V.XCHK,DT/@1,DK/NOP"
;D_O .•• THRU O_CACHE ...
o_o
D 0-0
o:o+K[J+1
D O+LC+1
0-0-Q
D=ACCEL&SYNC
O_ALU
D_ALU.LEFT
D_ALU.LEFT2
D_ALU.LEFT3
D_ALU.RIGHT
D_ALU.RIGHT2
D_ALU(FRAC)
D BLANK
Dfl_CACHE
D_CACt-iE ()
D[ ]_CACriE. IBCHK

"DK/C LR"

"AMX/R~MX.OXT,DTILONG.R8MX/D.dMX/RBMX,ALU/A-S,SHF/ALU,DK'SrlF"
"AMX 1 R.:.~.~X. OXT. DT / LCNG, 14.MX. ·~~ , B~•~X/!(MX, ALU/ A+B+ 1 , SHF /A LU, DK• S;-';:"
"AMX/RA~X.OXT,DT/LC~G.8~X·LC,AL~/A+B+1,SHF/ALU,DK/SHF"
"AMX,RAMX.OXT,OT/LC~G.RS~x,o.sMX/RSMX,ALU/A-B,SHF/ALU,DK/SrlF"
"DK;ACCEL,ACF/SY~C"

"SHF/A-U,DK,'SHF"
"SHF,'LEFT,DK/SHF"
"S~F

ALU.DT,DT/LONG,D~/SHF"

"SHF
"SHF
"SHF
"SHF
"D_K
"VAK
"VAK
"VAK

LEl"T3,CK 'SHF"
RIGHT .DK/SHF"
RIGHT2,QK/SHF"
ALU.DK/SHF.FL"
.20]"
t·;'.:t:,\1CT/READ.V.RC~i<..:H f>.1,8:-\/NOP'·
NCP,!\'CT/REAu.·:.RCl-'K,".~s::.Pi .DK/NOP"
NCP.~.~CT/RE!.J.V. !8C:-f'\.DL~1.Db;/f'.<OP·'

~
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0

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0

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c:;
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::c
0

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c
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0
z

D_CACHE.l~ST.DEP
"VAK/NOP,MCT/READ.V.IBCHK,DT/INST.DEP,DK/NOP"
D_CACHE.LK(J
"VAK/NOP,MCT/LOCKREAO.V.WCHK,MSC/@1,DK/NOP"
D(]_CACHE.LK
"VAK/NOP,MCT/LOCKREAD.V.WCHK,DT/~1 ,DK/NOP"
D[]_CACHE.NOCHK "VAK/NOP.MCT/READ.V.NOCHK.DT/~1.DK/NOP•
D[]_CACHE.P
"VAK/NOP,MCT/REAO.P,DT/•1.D~/NCP•
D[]_CACHE.WCHK "VAK/NOP,MCT/REAO.V.~CHK,DT/@1,DK/NOP"
D_CACHE.WCHK[]
"VAK/NOP,MCT/REAO.V.WCHK,MSC/•1 ,OK/NOP"
;O_OAL ••• THRU o_o .•.

D_DAL.t40RM
"DK/DAL.SV"
D_DAL.SC
"DK/DAL.SC"
D_O.OXT[]
"RAMX/0,AMX/RAMX.OXT,DT/@1,ALU/A,SHF/ALU,DK/SHF"
D_O.OXT[].ANONOT.K[]
"RAMX/0,AMX/RAMX.OXT,DT/@1,KMX/~2,BMX/KMX,ALU/ANDNOT,SHF/ALU,DK/SHF"
D_O.OXT[]+K[]
"RA~X/D.AMX/RA~X.OXT,OT/~1,h~X,02,BMX/KMX,ALU/A+B,SHF/ALU.D~/SHF'
o_o.OXT[].OR.Q "RAMX/D.AMX/RAMX.OXT,DT/@1 ,RBMX Q,BMX/REMX,ALU/OR,SHF/ALU.GK/SHF"
D_O.OXT[]+O
"ALJ/A•9,AMX/RAMX.O<T.DT,©1,8MX/RBMX,RSMX/Q,O_ALU"
o_o. OXT [ ]+0+1
"RAMX/D. Ml.X/RAMX. ox T. DT •@l1 • sr.'.X/ REiMX' ALU/ A+S+1 • D_ALU"
D_D.OXT[].XQ~.Q

"CK/SHF,ALU/XQR,SHF/ALU.~~X;~A~X.OXT,RAMX/D,DT/@1,RB~X/Q,S~X/R9MX"

O_D.OXT[].XQR.RC[]
"RAMX/0,AMX!RA~X.JXT,DT.~1,SPO.R/LOAD.LC,SPO.RC/@2,BMX/LC,ALU/XOR,SHF/ALU,OK/SHF"
D_O.ANO.K[]
"RAMX/D,AMX/RAMX,KMX/~1.B~X/~~X.ALU/ANJ,SHF/ALU,OK/SHF"
D_D.ANO.K[].LEFT2
•RAMX/0,AMX/RA~X,KMX;P1 .BMX/KMX,ALU/AND,SHF/ALU.DT,OT/LO~G.DK/SHF"
D_O.ANO.K[].RIGHT
"RAMX/D,AMX/RAMX,KMX;~1.B~X/KMX,ALU/AND,SHF/RIGHT,DK/SHF"
D_D.AND.LC
"~A~X,D.AMX/RAMX,8~X/LC,A~U1AND,SHF/ALU,DK/SHF"
O_D.ANO.MASK
"RAMX/D,AMX/RAMX,B~X/MAS~.ALU/A,D,SHF/ALU,DK/SHF"
D_D.AND.Q
"RAMX/D.AMX/RAMX,RS~X/0,BMX.RS~X,ALU/AND,SHF/ALU,DK/SHF"
0_0.AN~.RC[]

D_D. ANON:JT. K(]
D_D.ANCNOT.LC
D_~.ANONOT.PS~Z

"RA~X!C,AMX/RA~X,SPO.R/LOAD.LC.SPO.RC/©1,8MX/LC,ALU/AND,SHF/ALU,DK/SHF"
"R AY.X,'D. Af.~X/RAMJ(. K:VX /@1 , 8:\,X, "i~'.<. ALU/ ANONOT, SH F /ALU, OK/SH F ''
"RA~X/D,AMX/RAMX,8MX/LC,ALU, ANJNOT,SHF/ALU,DK/SHF"
"DK/SHF.ALU/ANDNOT,AMX/RAMX,RA~X/D,BMX/KMJ(,KMX/.4,SHF/ALU"
"RA'~X,' D. AMX/RAMX, R8','X/ ~, 8\~X, RR~.!X, ALU/ ANDNOT, SHF /ALU, DK/SHF"
"RA~X D,AMX/RAMX,S~:.R/LO~D.LC,SPO.RC/@1,BMX/LC,ALU/ANDNOT,SHF/ALU,DK/SHF"
"RA~X D.A~X/qAMX,ALU/A.SHF/!LU,JK/SHF.FL"
"RA~X D.~~X/RAMX,KMX/@2,B~X ~MX.ALU/~1,SHF/ALU,DK/SHF"
"RA~X D.A~X/RAMJ(.~VX •1 ,BMX:K~X.ALU/A+B,SHF/ALU,DK/SHF"
;t R :."lX
D. Al\'.X/RA.r.:x. K~ix /~1 . B.,1X/KMX. ALU/ A-B. SHF I ALU. DK/SHF"
"RA~X D.A~X/RA~X,KMX/~1,S~X/K~~.ALU/A+B+1,SHF/ALU,DK/SHF"
"RA~X D.AMX/RA~X.BMX/LB,ALU, ~+B,SHF/ALU,OK/SHF"
"RA~X D,AVX/RA~X,8MX,LC,ALU1A•S,SHF/ALU.DK/SHF"

O_D. ANDNOT. Q
D_D.ANONOT.RC(]
D_D(FRAC)
O_D[]K[]
O_D+K()
D_D-K []
D_D+K(J+1
D_D+LB
D_D+LC
D_D-LC
"RAMX D,AMX/RAMX,BMX/LC,ALU;A-8,SHF/ALU,DK/SHF"
D_D+LC+PSL.C
"RAMX D,AMX/RAMX,BMX/LC,ALU;A+B+PSL.C,SHF/ALU,DK/SHF"

(")

::0

c
5>
G)

2
0
en
-4

n
(")

0
2
-4

::0

0
r-

::0

.,,s:
m
r-

e
c
m

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2

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0

2
en

0
0

::!

D_D.LEFT
D D.LEFT2
D=D[ )MASK
D_D.OR.ASCII
D_D.OR.K[)
D_D.ORNOT.MASK
D_D.OR.PSWC
D_D.OR.PSWV
D_D.OR.Q
D_D.OR.RC[]
D_D[ )0
D_D+O
D_D-Q
D_iJ+Q+1
D_D-Q-1
D_D.RIGHT
D_D.RIG:-1T2
D_D.RI3'-iT{B)
D_D.SWAP
D_D.SXT[)

D_D.SXT[].RIGHT
D_D.XOR.K[)
D_D.XOR.LC
D_D.XOR.O

"DK/LEFT"
"DK,LEF"'."2"

3::

"RA~X/0,AMX/RAMX,B~X/MASK,ALU/@1

,SHF/ALU,DK/SHF"

"D_D.OR.K[ .30]"
"RA~X/J,A~X/RAMX,KMX/~1 .SMX. K~X.ALU/OR,SHF/ALU,DK/SHF"
"RA~X,D.AMX/RA~X.S~X/MAS~.A~u.c;~oT,SHF/ALU,DK/SHF"
"D~;SHF,ALJ/OR,AMX'RAMX,RA~'· C.?MX/KMX,~MX/.1,SHF;ALU"
"C~/SHF,ALU/OR,AMX

"RA'.~

QA~x.~;~x

D.~~X/K~X.KMX/.2,SHF/ALU"

x.. D. A'! x.' RM,1X ' R ~r. .<; 0 'sr.~x: ~, s:. \ . ALU/':.~ . SH FI ALU' DK/ SH F"
1

"R ~c,· )-'/Cl. !:..': </ RA'.~A 's ;,o. ".

LS;. ~..l. L c. s PO. RC/? 1 • s:l!X/ LC' ALt.:/O R. s.., F: ALU. OK/SH F"

"R A!V X. C, A'i \ / RA\1X . R C!i' X. Q, c~ .1,,; /;; C',1X,ALU/@l1 , Sri F/A LU, DK/SH F"
"R A'.~X I D. ;is x / R .i.:.1x. "c;,-,; <' 0. '.O: (. "~~11 x • A ;_u /A ... B' SH FI A LU' DI\/ SH F"
"q A'.i X; '.),AV X/RA \1X , RS1,1 X. Q, S\".f. ": l:"' .<,A LU/ A-6, SHF /A LU, Df\/SHF ''
" R .i. ~. ~ ' i C • A. i X,' R I\ ',1 x , R . ." .1 Xi <;. , 8 V. X; r! 8 •« , ALU I A+ S + 1 , SH F /A LU , DK IS HF "
"RA~~·J.A~X/RAMX,RB~X.Q.~~X,RS~X,ALU/A-B-1,SHF/ALU,DK/SHF"

"'.::f<, qGHT"
"R~~X;J,S~X/QB~X,ALU/3,SHF;RlGHT,DK;SHF"

~ >'\
y T ~ • -~A p
" R :. ... xI :::; • A"\~ x/RA'.' x . s ! r . :n ,' ·1• 1 • :. Lu I A • s HF I A Lu • Dr\/ s:, F "
"RAMX/~.A~X/RA~x.sx·.cT,~1 ,:LJ ,,SHF/RISHT,CK/SHF"
'RAMX/D,A,1lX/R:.i'.~X.K"i;x,1;;1 ,2".'X ,_r,·1:<,ALU/X:JR,SHF/ALU,DK/SHF"
"RA'·1X/~, A'\IX/RA\1X, Bf¥ x, L.:::, A :..u, XOR, SHF /A LiJ. DK/SHF"
II

"RAMX/D,AMX;RAMX,RE~X;Q,B~X/~BMX,ALU/XOR,SHF/ALU,DK/SHF"

n
:::D
0

C>
2

(I)

-I

c;
n
0
2

-I
:::D

r:::D

3::

;D_INT.SUM ... THRU D_PC ...
D_INT.SUM
D_K[]
D_K[).RIGHT
D_K[).RIGHT2
D LA
D=LA.AND.K[]
D_LA+D+PSL.C
D_LA-D
D_LA(FRAC)
D_LA-K []
D_LA.RIGHT
D_LB
D_LB.PC

"MCT/READ.INT.S~M.D~/NCP"

"Kf1~X /@l 1 • s:.~x I KM
A :..J ,' 8. -IF/ t. L J. Dt< I SH F"
"Ki.~X @1,J:,1x/KViX,ALG/8,S'1>'.'RJC.HT ,01\/SHF"

"Kr1'.X @1,B".1X/KM\, A:..U.'B,S:-i"/f~lGH""2,DK/SHF"
"AMXILA,ALU/A,SriF/ALU.~;{!Sh="

"AMX/LA,KMX/@ll .BMX/KMX,ALU/AND,SHF/ALU,DK/SHF"
"AMX, LA,RB~X/0,S~X!~BMX,ALU/ATB+PSL.C,SHF/ALU,DK/SHF"
" D K i SH F , A ~ U / A- B • AM X / LA . I>" </ 'b \ 1 X , R BM X / D , SH F /A LU "
"AM X /LA , ALU/ A, Sr< F ,'ALU, Dr\: SH::-. ~ L"
"Ar,;x/ LA' K~.1X/@1 • BMX,' KMX 'A -.'J/ !,-8. SHF I ALU. DK/SHF"

"AMX; LA.ALU/A,SHF/RIGrT ,L:..;/::,HF"
"B~x,~s.A~U;B.SHFiA~U.:k;SHF"

"31.1 ></PC. 0 R. LB, A:.. J,.. 6, SH F;:. L '_;,DI\ i SH F"

e
c

.,,

m
2

0
2

(I)

n0
2

::!

D LC
D=LC(FRAC)
D_NOT. D
D_NOT.K[]
D NOT.MASK
D=NOT.Q
D_NOT.R[]
D_?ACK.FP
D_PACK.FP.LEFT
D_PC
D_PC. LEFT
;D_Q .••

"BMX/LC.ALU/B,SHF/ALU.DK/SHF"

D Q
D=Q.OXT[]
D_Q.AND.K[]
D_Q.AND.LC
D_Q.AND.MASK
D_Q.ANDt-,jQT.D
D_Q.ANONOT.K[]
D_Q.ANDNOT.MASK
D_Q.ANDNOT.PSWC
D_Q.AND"JOT.PSWN
D_Q. A:'-.IDNOT. PSWZ
D_Q.AND.RC[]
D&Q_D+Q
D_Q+D
0 Q-D
0-0-0-1
D=O[ ]D
D Q(FRAC)
D=Q+K[J
D_Q-K[]
D_O-K[]-1
D O+LB
D=Q[ ]MASK
D Q.LEFT
D=Q.OR.K(]
D_Q.ORNOT.MASK
D_Q.OR.PSWC

"DK/0"

"B~X;LC,ALU/B,SHF/ALU,DK/SrlF.FL"

"RA~X/D,AMX/RAMX,ALU;NOT~.SHF/A~U,DK/SHF"
"KMX 1 @1,B~X/KMX,AMX/RAMX.OXT,DT/LONG,ALU/ORNOT,SHF/ALU,OK/SHF"
"BMX/MASK,AMX/R~MX.OXT,DT/LONG,ALU/ORNOT,SHF/ALU,OK/SHF"

"R A','.X/Q, AMX/RA'AX, AL'-' /l\:G TA, .SH F/A LU, DK/SHF"

~
n

:::D

;

"LA_RA[~1],AMX/LA,ALU;~JTA,D_ALU"

"BMX, ?ACKED.FL,ALU,B,SHF/ALU,DK/SHF"
"BMX/PACKED.FL,ALU/B,SHF/LEFT,DK/SHF"
"BMX!PC,ALU/B,SHF/ALU,DK/SHF"
"BMX/PC.ALU/8,SHF/LEFT,DK/SHF"

G')

0
(I)
-t

n
"RAMX/Q.AMX/RAMX.OXT,DT/~1,ALU/A,SHF/ALU,OK/SHF"

"RAMX/Q,AMX/RAMX,KM!(/•1,BMX/KMX,ALU/AND,SHF/ALU,OK/SHF"
"RA~X/Q,AMX/RAMX,B~X;LC.,LU;A~D.SHF/ALU,DK/SHF"
"RA~;'..CQ' A~.~X/RAMX. s:.1x /MASI-\' ALU,' A~D. SHF /ALU. DK/SHF"
"RAMX/Q,AMX/RAMX,RB~X/C,B~X. ~e~x.ALU/ANDNOT,SHF/ALU,DK/SHF"

"RAMX/0. M1X/RAM!(. Kr.1,1 / ?1. 9•,1x,- I'\:;::._. ALi.J/ At,JJ'.:JT. SHF I ALU' DK/SHF"

n
0
z

-t
:::D

"RA~X/Q,AMX/RA~X.B~X/~AS~.ALU/A~DNOT,SrlF/ALU,DK/SHF"

:::D

"DK/ SHF,:.. LU I AN ON:J T,:. MX; R :.;v;x, RA ".iX/Q, BMX/KMX, KMX/. 1 , SHF /ALU"
"DK/SHF, ALU/ ANDNOT. AM:(/;:iM,1X, ~ M'X/Q, 8~>1X /KMX, KMX/. 8, SHF / AL:.J"
"DK/ SHF. ALU/ AND~DT.,.. V.X/i-< A::.x. ;;.•\:v1X /Q. BMX/KMX. KMX/. 4. SHF I AL~"

.,,3::

"RAMX/C.AMX/RA~x.sµo,;:;, ~JA0.LC,SPO.RC/@1,BMX/LC,ALU/AND,SHF/ALU,DK/SHF"
"R:..MX/D,A~X/RA~X.R3~X/0.S~X RB~X,ALU/A+B,SHF/ALU,DK/SHF,JK'SrlF"
"RA~X/Q.A~X/RA~X,R~~X,~,SMX ;~MX,ALU/A+B,SHF/ALU,DK/SHF"

"RA~X,Q.AMX/RA~X,R3~X,D.B~X. R5~X,ALU/A-8,SHF/ALU,DK/SHF"

"R AV:X /J. AMX/ RA".1X. RB\lX, D. 2'>r.x, Rs·:·(. ALU/ A-B-1. SHF I ALU' OK/SHF"
"RA~X/Q,A~X/RAMX,R2~X,D,SMX,RS~X.ALU/?1,SHF/ALU,DK/SHF"
"RA~X/0.AWX/RA~X.ALL/A,SHF/ALU.~K/SHF.FL"

"R Al\~ X/:), A'.' X/ RA MX , K:.ix / 1!'-1 , ':'MX; r· :v'iX, A~ U /A+ B, SHF /A LU, DK/ SH F"
"RAVX;C,A~X/RAMX,K~!/P1 .B~X,~MK,ALU/A-B,SHF/ALU,OK/SHF"

"RA~X/Q,A~X/RA~X.KMX/~1 .E~X. ~~~.ALU/A-B-1

,SHF/ALU,DK/SHF"

";:; ,:.'tX/ 0, A~!( /R Ai.1X, g:,1x / L6, ALU/ A1 0, SHF /A LU, DK/SH F"

,$HF/ALU,DK/SHF"
"RAM X/ .:; . M.~x /RAM X , A Lt.;/ A, Sri F / c. E.f T , OK/ SH F"
"~A~X,Q,AMX/RA~X,KMX/~1 .~~~ KMX,ALU/OR, HF/ALU,OK/SHF"
•;:; A'i'J..,'r~ . .:..i'l:X/RA',1X, 5'. x /WASI".. A t.u.·oqNQT, SH F ALU, DK/ SHF"
"DK; SHF, ALU/OR, AMX;' RAMX, RA::.:._ ,'Q, EiMX/KMX, MX/. 1 , SHF /ALU"
"RA~X/Q.~~X/RAMX,B~X;MASV,ALU,~1

.,,m
z

:::!
0

(I)

n0
z

::i

"R~~x,o.~~X/RA~x.s;:.~;LD~~-LC,S~O.~C,@1 .S~X/LC,ALU/OR,S~F'~LU,DK/SHF"
D_Q.OR.RC[]
"R ;.,,, X .·;:;, .l '. X /RA '.1.-: . g~· .'< 1;::.:: , .: ~ L , :. ... 3. SH i:- /A LU, Ok/ SH F"
D_Q+PC
"RA~X. ~.;.~,;RA~X.b~x;o.~SC;~E~~.RLOG,ALU/A-B,SHF/ALU,OK/S~~·
;)_Q-PCSll
"R t..:t.X/Q, A:, X/RAr/:X, A;,,,U/ A. SHF.1'< ~ G•1 T, Dr\/ St-: F '·
D_Q.RIGf1T
"RAMX;Q,AMX/R-MX,AL~/A,SHF/R!GhT2,DKiSHF"
D_Q.RIGHT2
"R A'\'1X/Q, AMX/RAMX. SXT, OT /@11 , ALU/ A, SHF /ALU, DK/SHF"
O_Q.SXT[J
"RA'\'1X/Q,AMX/RAMX,SPO.R/LOAD.LC,SPO.RC/~1,BMX/LC,ALU/XOR,SHF/ALU,OK/SHF"
O_ Q. XOR. RC [ ]
;O_R ... THRU O&VA_ ...
1

"SPO.R:LOAD.LA8,SPO.RA3/S1,A~X/LA,ALU/A,SHF/ALU,OK/SHF"
D_R[]
"5PJ.R/L0AD.LAB.S?O.RA3/@1,A~X:LA,~MX/@2,BMX/KMX,ALU/ANO,SHF/ALU,OK/SHF"
D_R[].AND.K[]
O_R[].ORNOT.K(] "L AS_R [ '§ll ] , AMX/ LA, B:: X, ~C~X, K\1X/~2, ALU/ORNOT, D_ALU"
"SPO.R!LOAD.LC,SPO.RC/@1
.SMX;LC.ALU/8,SHF/ALU,DK/SHF"
D_RC[]
"BMX;PC.ALU/B,SHF/ALU.O~;SHF,SP~.R/~R!TE.RC,SPO.RC/•1•
D&RC[ ]_PC
"SPCILOAD.LC.SC,BMX. LC,ALU 1 B,S~F/ALU,DK/SHF"
D_RC(SC)
"S?O.R/LOAD.LA2.SPO.RA3/~1 ,A~X/LA,ALU/A,SHF/ALU,DK/SHF.F~"
O_R [ ]( FRAC)
" 3 r.1 X/ 0 , :.'!SC / RE AD. R LC u , A LU. B , SH F / A LU , DK/SH F "
D_RLOG
"BMX/O.MSC/READ.~LGG,ALU'B,ShF 1 RIGHT,01'(/SHF"
D_RLOG.RIGHT
"5 PO. AC/ LOAD. LAS, S 0 0. ACN,' ;:.Rf\+ 1 , Ar~X/ LA, ALU/ A, SHF /A LU, DK/SHF"
D_R( PRN+1)
"SPO.AC/LOAD.LAB,S?J.ACN,SC,AM~·LA,ALU/A,SHF/ALU,DK/SHF"
D_R(SC)
"S?O.AC/LOAD.LAB,S~O.ACN;S?1+1,AMX/LA,ALU/A,SHF/ALU,OK/SHF"
O_R(SPl+1)
"VAl'(/LOAO,SHF/ALU,D~/SHF"
O&VA ALU
"RAMX/D,AMX;RAMX,K~X;~l,B~X/KMX,ALU/A-6,VAK/LOAD,SHF/ALU,D~/S~F"
D&llA=D-K[]
"RAMX/0,A~X/RA~X,BMX/LC,ALU/A+B,VAK/LOAD,SHF/ALU,DK/SHF"
D&VA D+LC
"D_D+Q,VAK,"LOAD"
D&'v'A=D+'~
"A:v1X/
LA, ALJ/A, '..JAr:/ LOAC, Sf-'.F /A LU, DK/SHF"
O&VA_LA
"BMX/LB.ALU/5,~AK/LCA:,SHF/A-U,DK/SHF"
D&.VA_LS
"RA~X/Q,A~X/RAMX,ALU/A,VAK/LOA~.DK/Q"
D&VA_Q
"RAMX:Q,A~X/RAMX,5~X/?C.OR.LB,ALU/A+B,VAK/LOAD,SHF/ALU,DK/5HF"
D&VA_Q+LB.PC
;E.ALU_ ... T!-IRU FE_ ...

EALU_D( EXP)
"RA~"X/C. A'ViX/RA'..':X. E6~~x. AMX. Exr-. EALU/B"
EALU FE
"EBMX/FE,E.ALU/B"
EALIJ=K[]
"KMX 1 :?\1,EB".1X/l',;,•x,EA~U;B"
EALU_R[](EXP)
•soo.R;LDAD.LAB,SPO.RAS;@1,AMXILA,EBMX/AMX.EXP,EALU/B"
EALU_SC
"EALU/A"
EALU_SC.ANDNOT.K[]
"KMX/@1,EBMX/KMX,EALU/ANONOT"
E'LU_SC+FE
"EB~X/FE,EALU/A+B"
EALU_SC-FE
"ESMX/FE,EALU/A-B"
EALU_SC+K []
"l'<MX/@1. EBMX/KMX, EALU/ A+B"

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EALU_SC-K[)
EALU_STATE

"KMX/~1.EBMX/KMX,EALU/A-B"

"EALU/A.~SC/LOAD.STATE"

FE_O(A)
"AMX/RAM~.OXT,DT/LC~G.EBMX/AMX.EXP,EALU/B,FEK/LOAD"
FE_DlEXP)
"RAMX/D,AMX/RAMX,E9MX;AMX.EXP,EALU/B,FEK/LOAD"
FE_EALU
"FEK/LDAD"
FE_K()
"KMX/@1,EBMX/KMX,EALU/S,FEK;LOA~"
FE_LA(EXP)
"A~X/LA,EBMX/A~X.EXP,EALU/B,FE~/LQAD"
FE_NABS(SC-LA(EXP)) "AMX/LA,EB~X/A~X.EXP.EALU/~ASS.A-B,FEK/LOAD"
FE_Q(EXP)
"RAMX/Q,AMX/RAMX,EB~X/A~~.EXP,EALU/B,FEK/LOAD"
FE_R[)(EXP)
"SPO.R/LOAD.LAB,SPO.RA~/~1,A~X/LA,EBMX/AMX.EXP,EALU/B,FEK/LCAD"
FE_SC
"EALU/A,FE~/LOAJ"
FE_SC.ANDNOT.FE
"EBMX/FE,EA~U;ANDNOT,FEK/LOAD"
FE_SC.ANDNOT.K[]
"KMX/~1.E8MX:/KMX,EALU/ANONOT,FEK/LOA0"
FE_SC+1
"EALU/A+1,FEK/LJAD"
FE_SC+FE
"EBMJl./FE,EALU/A+i3,FEK,'LOAC"
FE_SC-FE
"EBMX/FE,EALU/~-~.FEK/LOAD"
f E&SC_K [)
"KMX /@1 , EBMX/ K'.1X, E~. LlJt B, Ft:::~:. ;_Q.:..D, SMX/ EALU, SCK/ LOAD"
FE_SC+K[]
"KMX/~1.EE~X/KM!,E•LUIA+S,FEK/LOAD"
FE_SC-K[]
"KMX/,1,EB~X/K~X.EALU;A-8,FE~/LCAD"
FE_SC+LA(EXP)
"AMX/LA,EBMX/A~X.EX?,EALU/A~B,FEK/LOAD"
FE_SC-LA(EXP)
"AMX/LA,EB~X/AMX.EXP,EALU/A-S,FEK/LOAD"
FE_SC.OR.K[]
"EALU/OR,EBMX/K~X,KMX/~1 ,FEK/LOAD"
FE_SC-SHF.VAL
"EBMX/SHF.VAL,EALU/A-3,FEK/LOAD"
FE_SHF.VAL
"EBMX/SHF.VAL,EALU/B,FEK/LOAD"
; ID_ ••• THRU LC_ ...
ID[LD
ID_D&NO.SYNC
ID_D.SYNC
ID(SC)_D
K[)

"CID/WRITE.KMX,ID.AODR/~1·

•c1o;wRITE.KMX,ADS/IBA,KMX/SP1.CON"

"CID/WRITE.KMX,ADS/IBA,~MX/SP1.CON,ACF/SYNC•

"CID/WRITE. SC"
"KMX/01"

LA RA(]
"SPO.AC/LOAO.LA,SPO.RAB/~1"
LA:R(OST)&LB_R(SRC)
"SPO.AC/LOAO.LA6,SPO.ACN11/0ST.SRC"
LA R(SP2J&LB R(SP1)
"S?O.AC/LOAO.LAB,SPO.ACN/SP2.SP1"
LAB_R1&RC[ LO
"ALU_O(A). LAB_R1&RC[Gii1 ]_ALU"
LAB_R1&RC[]_ALU "SPO.R/LOAD.LAB1.WRITE.RC,SPO.RC/~1,SHF/ALU"

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LAB_R1&RC[]_ALU.RIGHT2 "SPO.R;LOAD.LAS1.WRITE.RC,SPO.RC/@1 ,SHF/RIGHT2"
LAB_R1&RC[]_D.OXT[ ]+K[] "ALU_O.OXT[@2]+Kr@3],LAB_R1&RC[@1]_ALU"
LAB_R1&RC[]_D+LC
"ALU_O+LC,LAS_R1&RC[@1]_ALU"
LAB_R1&RC[ ]_Q-K[]
"ALU_Q-K[@2j, LAB_Rt&RC[f.1 ]_ALU"
LA9_R1&RC[]_o-o "SPO.R/LOAD.LAB1 .WRITE.RC,SPO.RC/@1 ,ALU/A-B,AMX/RAMX.OXT.DT/LONG,BMX/RBMX,RBMX/0,SHF/ALU"
LAB_R1&RC[]_O+LC+1
"ALU/A+B+1 ,AMX;RAMX.OXT,DT/LONG,BMX/LC,SPO.R/LOAD.LAB1.WRITE.RC,SPO.RC/01 ,SHF/ALU•
LAB_R[]
"SPO.R/LOAD.LAB.SPO.RAB/@1"
LAB_R(DST)
"S?O.AC/LOAD.LAB,SPC.ACN11/DST.DST"
LAB_R(SC)
"SPO.AC/LOAD.LAS,SPO.ACN/SC"
LAB_R(SP1)
"SPO.AC/LOAD.LAB,SPO.ACN1SP1.SP1"
LC_RC[]
"SPO.R/L0AD.LC,SPO.RC;~1"
LC_RC[ ]&R1_D
"ALU_D, LC_RC[@1 ]&R1_ALU"
LC_RC[ ]&R1_LA-K[]
"ALU_L.A-K[@2], LC_RC[@1 ]SR1_ALU"
LC_RC(SC)
"SPO/LOAD.LC.SC"
LC_RC[]&R1_ALU "SPO.R/LOAD.LC.~RITE.RAB1 ,SPO.RC/@1,SHF/ALU"
LC_RC[]&R1_(LA+LBJ.LEFT "A~X/LA,BMX/LB,ALU/A+B,SHF/LEFT,SPO.R/LOAD.LC.WRiTE.R~S1,SPO.RC/@1"
LC_RC[J&R1_(LA-LB).LEFT "AMX/LA,BMXIL8,ALU/A-B,SHF/LEFT,SPO.R/LOAD.LC.WRITE.~AB1 ,SPO.RC/@11"
LC_RC( ]&R1_LA+K[]
"SPO.R/LOAD. LC.WRITE..RAB1 ,SPO.RC/@1,SHF/ALU,ALU/A.,.g,.,i.1X,'LA,BMX/KMX,KMX/l'2"
LC_RC[]&R1_LB
"ALU_LB.LC_RC[~t]&~l_ALU"
LC_RC[]&Rt_Q
"SPO.R/LOAD.LC.WRITE.RA91 ,SPO.RC/@1,SHF/ALU,ALU/A,AMX/RAMX,RAMX/Q"
; PC_ ••• THRU PC&VA_ ..•
PC PC+1
"PCK/PC+1"
Pc:Pc+2
"PC~/PCT2"
PC PC+4
"PCK/PC+4"
PC:PC+N
"PCK;PC+N"
PC_Q+PC
"AL0;A+S,VAK/LOAD,PCK/PC_~A,SMX/PC,AMX/RAMX,RAMX/0"
PC_VA
"PC~/DC VA"
PC&VA_ALU
"VAK 1 LOiC,PCK/PC_VA"
PC&.!/A D
"RAilil.X/D, AMX/RAMX, ALU/ A, VAK/ LCAD, PCK/PC_VA"
PC&VA:D.OXT[]
"RAMX/D,AMX/RAMX.OXT,DT @'.,ALU·~.VAK/LOAD,?CK/PC_VA"
PC&VA_D.OXT[]+PC
"RAMX/D,AM~/PAY<.CXT,DT ~1 ,BMX/PC,ALU/ATS,VAK/LO~J.P~K/PC_VA"
PC&VA_D.SXT[]+PC "RA~X/D,A~XIRAMX.SXT,DT 1 ~1 .s~x·PC,ALU/A+8,VAK/LCAD,PCK/~:_VA"
PC&VA_D+K[]
"R.:,~X/D,AMX/RA~X,KMX.~1.SMX ~~X.ALU/A+B,VAK/LOAD,PCK/PC_VA"
PC&VA_D-K [ J
"RA'.1X, D. A'.':X/RA!.L\, KMX / @1 , 8~.'X, PIX, ALU/ A-8. VAK/ LOAD, PCK/PC_'J A"
PC&VA_D-PC
• ;A~X/0,A~X/RA~X.2:.~;PC,ALU;A-8,VAK/LOAD,PCK/PC_VA"
PC&VA_K []
"~~.".X/~1 • 8\'·X/K~,x. t.L'~ / 8. 'v A'-\, LCt,:J. PCK/PC_v.:,•
PC&VA_PC
"B~X/PC,ALU/S,V~K/LCAO,?C~;~C_VA"
PC&VA_Q
"RAMX/Q,A~X/RAMX,AL~;A.~A~;~SA8,PCK/PC VA"
PC~VA_Q-D

·~A~X;Q.A~X/R:Mx,R3~X,D.~~x. ~5~X.ALU/A:6,VAK/LDAD.PCK/PC_\A"

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PC&VA_Q-K []
·' RA:V:X/0, :i.MX/RAMX, r\MX / @l1 , 6\'.X.1 KMX, ALU/ A-3, VAK/ LC~.J, PCK/ PC_ V,:."
PC&VA_Q+PC
"RAMX;Q,AMX/RAMX,S~X/~C,A_~/A+B.VAK/LOAD,PCK/PC_VA"
PC&VA_Q.SXT[]+PC
'RAMX/Q,AMX;qAMX.SXT,DT @1,BMX/PC,ALU/A~B.VAK/LO~D,PCK/PC_VA"
PC&VA_R[].ANDNOT.K[] "SPO.R/LOAD.LAB,SPC.RAB:~1 ,AMX/LA,KMX/@2,BMX/KMX,ALL/AN)\OT,VAK/LOAD,PCK/PC_VA"
PC&VA_RC [)
"SPO. R/ LOt.D. LC, SPO. RC/@l1 , BMX/ LC, ALU/B, VAK/ LOAD, PCK/ PC_VA "·
PC_VIBA
"PCK/PC_IBA"
:o_o ••• THRU o_o .•.

w
w

0 0
"OK CLR"
0 0-0
"AMX;RA~X.OXT,DT/LCNG,QB~X/D,BVX/RBMX,ALU/A-B,SHF/ALU,QK/SHF"
o:o-K[]
"AMX/R~~X.OXT.DT;LONG,K~X,@1,BVX/KMX,AL~/A-9,SHF/ALU,QK/SrlF"
Q_O-LC
"AMX;RAMX.OXT,DT/LO~G.S~X. LC,ALU/A-B,SHF/ALU,QK/SHF"
Q O+MASK+1
"AMX;R:i.Mx.cxT,DT/LO~G.S~~;V:i.s~.ALU/A+B+1,SHF/ALU,QK/SHF"
Q O+PC.RLOG
"AMx;qA~X.OXT.DT/LO~G.S~X/PC,ALU/A+B.RLCG,SrlF/ALU,QK/SHF"
o:o-Q
"AMX/RA~X.OXT,DT/LONG,RBMX/Q,B~X/RBMX,ALU/A-8,SHF;ALU,OK;SHF"
O_ACCEL&SYNC
"QK/ACCEL.ACF/SYNC"
Q ALU
"SHF 1 ALU,CK/SHF"
Q_ALU. LEFT
"SHF; LEFT ,QK/SrlF"
O_ALU.LEFT2
"SHF,ALU.DT,DT/LCNG,QK/SHF"
Q_ALU.RIGHT
"SHF/RIGHT,QK/:YF"
Q_ALU.RIGHT2
"SHF/RIGHT2,0K;SHF"
O_ALU(FRAC)
"SHF/ALU,QK/SHF.FL"
Q D
"QK/D"
o:o(FRAC)(B)
"RB~X/D.BMX/RBMX,AL0/8.SHF/ALU.C~/SHF.FL"
Q_ D . 0 XT[ ]
" RA~~ X/ D, A~'. X/ RA·~ X. 0 XT , DT/ 011 , A- U .~ , SH F/ ALI..' , QI<./ SH F "
Q_D.OXT[]+K[].LEFT "RA~X;D,AMX/R~MX.OXT,DT/81 ,•~X/P2,BMX/~MX,ALU/A+B,SHF/LEcT,QK/SHF"
Q_D.AN~.K[]

"~A~X;D,AMX/RAMX,K~t;'l .E~X

O_D.AND.K[] .RIGHT
Q_D. AND. K[]. RIGHT2
Q_D.ANONOT.RC(] "RA~X
Q_D.ANO.RC[]
"RA~X
Q_DEC.CON
"Ql</D
Q_D+K(]
"~A~X
Q_D+K[].LEFT
"RAYX
Q_D-K[]
"RAMX
O_D+LC
"RAMX
Q_O-LC
"~AMX
Q_D.LEFT3
"RA~X
Q_D.OR.K[]
"RAMX

~M(,ALU/AND,SHF/ALU,QK/SHF"

"RAMX/Cl,AMX RA:11x,Kr.~:<. ?:'. .8f1"X;fl.\~X.ALU/AND,SHF/RIGHT ,Q
"R i;MX/ u. Ai,lX,' RAi•:X. ~i.'.X/ ,_ ~ • SM/Z/:.;:.~x. ALL:/ Ar,o' SHF /R IGH"' 2.
D,AMX/RA~X.SPO.R/LCAD.LC,SPO.RC/~1,BMX;LC,ALU/ANDNJ~.
D,AMX/RAMX,SPO.R/LOAD.~C.SPO.RC/@1,8MX/LC,ALU/AND,SrlF

C.CO!'J"
D,AMX/RAMX,KMX/@1 .8~~. K~X.ALU/A+B.SHF/ALU,QK/SHF"
D.A~X/RAMX,K~X/~1 .E~X,K~X.ALU/A+B,SHF/LEFT,QK/SHF"
D.A~X/RA~X.K~C/~1 .s~x. r\~X.ALU/A-B,SHF/ALU,OK/SHF"
D.A~X'RA~x.s~x/LC,ALU/A+B,SHF/ALU,QK/SHF"
J,A~X

RA~~.B~X/L~.AL~,A-B.SHF/ALU,QK/SHF"

D,AMX
D,AMX

RA~X.ALU/A,SHF;LEFT3,QK/SHF"
RA~X.KMX/~1 .e~x K~X.ALU/OR,SHF/ALU,OK/SHF"

51-:F"
S'i::"
I

~;ALU,QK/SHF"

LU,QK;SHF"

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"RAMX; J. Ar,1X/ RA'i!X, SPO R,' t..O.:.D. LC, S?O. RC/@11 , 8MX/ LC, ALU/OR, SrlF.' Ai..U, OK/SHP
O_D.OR.RC[]
"RA~X/D.AMX;RAMX,RS~ /0,E~X/~5MX,ALU/A-B,SHF/ALU,QK/SHF"
0 D-0
0-D.RIGHT
"RA~'X/D,Ar:ix;;.A:~x.ALJ A,SHF/f\IG•1T,0K/SHF"
"RAMX/D,A~X;RA~C,ALU A,SHF;RIGHT2,QK;SHF"
O_D.RIGHT2
" R AM X / D • AM X / r? t.r., X • S .X T , D T /:? 1 , A i.. U i A , SH FI A LU , QI</ SH F 11
O_D.SXT[]
"OK/SHF,ALU/XOR,AMX:RA~X,RAMX/D,BMX/RBMX,RBMX/Q,SHF/ALU"
O_D.XOR.O
;O_lB .•. THRU Q_PC ...
0_1B.BDEST
"IBC/BJESr,QK/lD,MCT/ALLOw.IB.READ"
0_16.DATA
"OK/ID.MCT/ALLC.41.IS.READ"
O_ID[]
"CID/READ.KM,:, !D.A'.J:.~/'1 ,QK; ID"
O_ID(SC)
"CID/READ.SC.OK/ID"
O_K[)
"t'MX, 1~1.BMX/KMX.ALU/6,Si-1F/ALU,QK/SHF"
Q_K[).crx
"KMx,•1.s~x/K~X.ALU16.SHF/ALu.cT,DT/INST.DEP,OK/SHF"
O_K[).RIGHT
"K~X;~1.B~X/KMX,ALU'8,SrlF 1 RIGHT.QK/SHF·
O_K[).RIGHT2
"K~X/@1 .B~X/KMX,ALU·3.S~F/RI~H~2.0K/SHF"
Q LA
"A'~X/LA,ALU/A,S"iF/Ai..U.C.'\·SHF"
o:LA.AND.K[]
"AMX/LA,K~X/@1 ,S~\.'•MX,AL~;A~D.SHF/ALU,OK/SHF"
Q_LA. AN:JNOT. RC [)
"~'.iX/ LA. SPO. R, LOA'.). LC, sea. RC/@11 . ~~,rU t..C, ALU/ ANDNOT, SrlF I Al.U, OK/SHF"
Q_LA+K[]
"AWX/l.A,KWX/@>1 ,B~X;nMX,ALU/A+B,SHF/ALU,Q~;SHF"
Q_LA-K ()
"Aili>., :..A. KrtX/@>1 , B~.'.X, !".'v~.\, /. -_'J/ A-S, SHF /ALU, QK/SHF"
O_LA+O
"A~X/LA,ReMx/o.a~x,2BMx,ALU/A+B,SHF/ALU,QK/SHF"
Q_LB
"6~X;L8,ALU/8,SrlF/~~u.QK. SHF"
O_l.C
"8~.1X:'LC,ALU/S,ShF/AL'J,QK,'5HF"
o_NOT.Q
"Ra~x/Q,A~X/RA~X.ALU/NDTA,SHF/ALU,QK/SHF"
O_NOT.R[]
"LA_RA[@1 j ,AMX/:.A,ALU/NOTA,O_ALU"
Q_PACK.FP
"BMX/PACKED.FL,ALU/B,SHF/ALU,QK/SHF"
0 PC
"SMX/PC,ALU/B,SHF/ALU,QK/SHF"
;Q_Q ••• THRU Q&VA_ ...
Q_Q. OXT [ ]-K[)

"RAMX/0, AMX/RAMX. OXT, DT /~1, KMX/:?2, BMX/KMX, Al.U/ A-B, SHF /ALU, OK,'SHF"

Q_Q.OXT[).l.EFT "RAMX/0,AMX/RAMX.OXT,OT;~1,A:.U/A,SHF/l.EFT,OK/SHF"
O_Q.OXT[).OR.D "RAMX/0,AMX/RAMX.OXT.DT/~1.RSMX,D,BMX/RBMX,ALU/OR,SHF/ALU,QK/SHF"
O_O.ANO.K[]
"RAMX/0.A~X/RAMX,K~X/~1.3MXt~MX,ALU/ANO,SHF/Al.U,0K/SHF"
Q_Q.ANO.K[).RIGHT
"RAMX/Q,AMXiRAMX,K~X/P1.BMX/KMX,ALU/AN0,SHF/RIGHT,QK/SHF"
Q_Q.ANDNOT.0
"RA~X/Q,AMX/RAMX,RB~X,O,B~X:RSMX,ALU/ANCNOT,SHF/ALU,QK/SMF"
Q_Q.ANONOT.K[]
"RAMX/Q,A~X/RAMX,K~A/~1,BMX/Kl/X,Al.U/ANDNOT,SHF/ALU,QK/SH="
Q_O.ANO.RC[]
"RAMX/0.AMX/RAMX,SPO.R/LC~D.LC,SPO.RC/@1,BMX/LC,ALU/ANO,SHF/ALU,QK/SHF"
o_o-o
"R AMX,'0. AMX/RAMX. R8 ..1X/ D. BMX/f; 5•.~.( 'A LU/ A-B' SHF I ALU. QK/SHF"
Q_O+D
"RAMX/0.AMX/RAMX,R3MX;0,5~X/R8MX,ALU/A+B,SHF/ALU,QK/SHF"

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0 O-D-1
o:o(FRAC)
O_O(FRAC)(S)
O_O+K[)
O_Q-K[J
O_Q-K[]-1
O_O+LC
O_Q-LC
O_Q-LC-1
O_Q.LEFT
0 Q-MASK-1
o:o.oR.K[]
0_0.DRNOT.MASK
O_O+PC
0_0.RIGHT
0 Q.RIGHT2
y:o.sxT[]
Q_R[)
Q_R[).AND.K[)

"RAMX/Q,A~X/RA~X,RB~X/0,B~X/RS~X,ALU/A-B-1,SHF/ALU,QK/SHF"

"RAMX/Q,AMX/RAMX,ALL/A,SH~/ALU,QK/SHF.FL"

"R8MX/Q,0¥X/RSMX,ALU/8,SHF/ALU,QK/ShF.FL"

:ti

"RAMX/0,A~X/RAMX,KMX/~1 ,BMX/~~X.ALU/A+S,SHF/ALU,QK/SHF"
"RAMX/0.AMX/RAMX,KMX/~1.BMX;KM~.ALU/A-6.SHF/ALU,QK/SHF"
"RAMX/0.AMX/RA~X.KMX/@1 .B~X/KMX.ALU/A-B-1,SHF/ALU,QK/SHF"

"RA~X/Q.A~X/RAMX,8~~/LC,ALU/A-5,SHF/ALU,QK/SHF"

"R A~1X/Q, A'JIX/RAMX, B~.1X /LC, ALU/ A-9-1 , SHF I ALU, OK/ SHF"
"OK/LEFT"

"RAMX/Q,AMX/RAMX,BMX/LC,ALU/A+S,SHF/ALU.QK/SHF"

Cl>

"RAMX/0.A~X/RA~X.5MX/MASK,ALU/A-B-1,SHF/ALU,QK/SHF"

:!
n

"RAMX/Q,A~X/RA~X.KMX/~1 ,BMX/KMX,ALU/OR,SHF/ALU,QK/SHF"

"RAMX/Q,AMX/RAMX,BMX/MASK,ALU/ORNOT,SHF/ALU,QK/SHF"
"RAMX:O.A~X/RAMX,BMX/PC,ALU/A+B,SHF/ALU,QK/SHF"

"OK/RIGHT"
"OK1RIGHT2"

-4

·~A~X/Q.A~X/RAMX.SXT,OT/@1 ,ALU/A,SHF/ALU,QK/SHF"

:ti

"SPO.R/LO~D.LAB.SPC.RA5/~1,AWXILA,ALU/A.SHF/ALU,QK/SHF"
"SPO.R/LOAD.LAB,SPO.RA8;@1,1MX:LA,KMX/~2,6MX/KMX,ALU/AN0,SHF
Q_R[).AND.K[].RIG~T
"SPO.R/LDAD.LAB,SPO.~AS @1,AMX;LA,ALU/AND,BMX/KMX,~M
O_R[).ANDNOT.K[J
"S?O.R/LOAD.LAB,SDC.RAS,@1,AMX/LA,KMX1@2,~~X/KMX,ALU

Q_RC [ ]
Q_RC[](FRAC)
O_R[](FRAC)

ALU,QK/SHF"
/P2,SHF/RIGHT,QK/SHF"
A~DNOT,SHF/ALU,QK/S~F·

"s PQ. R: LOAD. LC. s PO. RC/@., . srv'X/ LC. ALU/B. SHF I ALU. OK/ SH F"

"SPO.R/LOAO.LA8,SPO.RAB/01,A~X/LA,ALU/A,SHF/ALU,0K/SHF.FL"
Q_R(PR~).ANONOT.Q
"SPO.A~/LCAD.LAS.SPO.AC~/PRN,AMX/LA,RBMX/O,BMX/R~~X,ALU/ANDNOT,SHF/ALU,QK/SHF"
O_R(PRN+1)
"SPO.AC/LGAD.LAB,S~O.ACN;PR~+l,A'VIX/LA,ALU/A,SHF/ALU,QK/SH~"
Q_R(PRN+1).ANO.Q
"SPO.AC/L0AJ.LAS.SPO.ACN/PRN+1,A~X/LA,RBMX/Q,BMX/RSMX,ALU/AND,SHF/ALU,QK/SHF"
O_R(SRC!1).AND.K[]
"SPO.AC/LOAD.LAB,SPO.ACN11/SRC.OR.1,AMX/LA,KMX/~1 .BMX·K~X.ALU/AND,SHF/ALU,QK/SHF"

"VAK/LCAD,SHF/ALU,QK/SHF"

Q~VA_D

"RA~X/D.AMX'RAMX,ALU/A,VAK/LOAD.SHF/ALU,QK/SHF"

"ALU/8,8~X/KMX,KMX/SC.SHF/ALU,QK/SHF"

"SPO.R1WRITE.RAB SPO.RAJ'•: ,AMX/RAMX.OXT

q l )_0-D

"A~X!RAMX.OXT.DT

R[ )_0-K[)

"A\'!X/ RA'.';'iX. OXT. DT

R[]_O-LB

"Af'•'X:R.O:.MX.OXT,DT

LCNG,RB~~:o.s~x/RBMX,AL
LC~;G. K~.1.<, ·)~.
K'l~X. A;..u
LO~.G.e~X. L8,AL:J/A-B,SHF

e:•x/

OTILONG,ALU/A,S~F
/A-8,SHF/ALU,SP:.~

A-S. SHF /ALU. SPO.;:.'
ALU,SPO.RhJRITE.~.~

m
r

.,,m
=t
0
z

Cl>

L "
~

O&VA_D+LC
"RAMX/D,A~X/RA~X.8MX/LC,ALU/A+B,VAK/LCAO,SHF/ALU,OK/SHF"
Q&VA_LA
"AMX/LA,ALU/A,VAK/LOAD,SH~/ALU.~K/SHF"
00.VA_O+LB. PC
"R A'VIX /0, A~'X/RAMX, Bl\iX /PC. OR. L5, ALU/ A+B, VAK/ LOAD, SHF /A LU, QK/SHF"
;R[)_O •.. THRU R()_PACK.FP
R[ )_O

"SPO.R/LCAD.LC,SPO.RC/~1.BMX;LC,ALU/B,SHF/A~U.OK/SHF.FL"

o_sc
O&VA_ALU

:ti

E.RAB,SPO.RAB/@1"
. RAS. SP:J. RAB/tll1"
.RA6/C?1"

n0
z

::!

....
en
w

R [ l - 0 + LB+ 1
" A M x ! R ;. p; . 0 x T • 0 T / L c ~; :::; • B ~-. ' ~ '2 ' :. ' I_, I A + B + 1 • s H F / A Lu • s p 0 • RI wR I ~ E . '· .), 13 • s p •J • R A '.:! / 9l 1 "
R [ ]_O-Q
"A'~ X /;,,Arv'/... 0 X T, OT! L'J!'o<G, RB·.: 'IQ, S\1 X / RB!V'X, A LU/ A-B, SHF /A ~U, SPJ. R ,'~.~IT E. RAB, S PO. R A3/fl1"
R [ ] _ O- 1
"A,•;; x I R;,v. x . 0 x T • D TI LCr• G. E ~.. x r-:n • I• v x I . 1 • A LU I A-B' SH FI A LU ' s PO . R / \~ R l TE . R,:. 9' s p 0. RAB/ fl), •
R[]_ALU
"SHF;ALU.SPO.R/WRITE.RA~ srO.RAB/@1"
R[)_ALU.LEFT
"SPO.R,..:K!TE.RA8,SPO.RA3 •:0.1,SHFoLEFT"
R[]_ALU.RIGHT
"SHF/RIGHT,SPO.R/WR!TE.RAS.S~O.RAB/@1"
R[)_D
"5PO.R/~RITE.RA3,SPO.RAB/~1.~AMx/D,AMX/RAMX,ALU/A,SHF/ALU"
R [ ]_D. AND. K [ l
"s ;JQ. R /WR: TE.RA e. SPO. RAB:•§> 1 • A LU I AND. AMX/ RAMX. RMv~X/D. BMX/" ·1x. "''~ '< /~2. SHF I A LU"
R[]_D+K(]
"SPO.R!WRITE.R~B.SCJ.RA3 01 ,RA~X/0,AMX/R~MX,KMX/@2,BMX/K~\,A~~:ATB,SHF;ALU"
R [ LD-K [ ]
"5 PO. RI WRITE.RAB. Sf-J. R "5 '~ 1 'R:, -.1x/D' AMX/ R.:.Mx. ~' \1X/@.2. BMX/K:. > • A l..·J/ A-B. SH FI ALU"
R6_D+K []. R LOG
"5 P:J. R,'1>.';::> I TE. R:. B, SPJ. RAB, R6, P.Ar~X/D, AMX/RAMX. KMX/@11 , 8fAX/K~·.;, A Li.J/ A+S. R LOG, SHF /ALU"
R[ LD-LC-1
"ALU_O-LC-1 ,R[';J1 ]_Ac.U"
R[]_D.OR.LC
"SPO.R,1>.RITE.RAB,SPJ.RA3 @1.ALU,OR,AMX/RAMX,RAMX/O,Bl'v~X/LC.SdF.'ALU"
R [ ]_D. OR. PACK. FP
"s DO.RI\\ R: TE.RA s. 5::00. RA B/Q:l1 • "LU/ OR. Ar. :x./ RA.:.1x. RA\~X D. e:.'.( /? :.CKED. FL. SHF I ALU ..
R [ ]_D. OR. 0
"s PO. R,'WR IT E. RAB. s PO. R:>. s ') 1 • RA0.,1\ /D' Ar.IX/ RAMX. R s:.~X/Q. BMX/R J\"'. A LU/ o;. SHF /A LU"
R [ ]_ 0+ Q
" S P'.) . R /WR I T E . R :>. 9 , S P0 . ;; A 8 ,' © 1 • R A'1 i:x / D , M' X / R AM X , R Br" X i 0 , BM X / R :: '. '. X , A _ U ,' A+ B , SH F / A LU "
R[ ]_D-Q
"SPO.R,''iiR!TE.RAB,S"J.PAS,.'l1.f"lA.ix;o,AMX;RAMX,;;B'·1>-/0,BMX/RJ'l','(,.'.._U/A-8,SHF/ALU"
R[ ]_i)+Q+1
"SPO.R;'l.R!TE.RAB,SPC.R.~3/(.:.l1 ,R! .. X/i),AMX,'RAMX,RB\iX/Q,8MX/Ror:,.(,ALU/A+B+1,SHF/ALU"
R[ )_K[ J
"BMX/KMX.KMX;@l2.ALU 1 8,S'1F.'ALU,S;:,O.R/'1!RITE.RAB,SPO.RAB/@l1"
R [ L LA
" s p 0 • RI ..., R I T E • R :. '3 • s p :J . P. A 8 / '.?: 1 ' A tv1 x LA ' A Lu I A ' s H F / A !.. u "
R[]_LA.AND.K[]
"AMX/LA,B~X/KM(.KMX ~2.ALL/~ND,SHF/ALU,SPO.R/WRITE.RAB,S~:.;A8 1 ©1"
R[]_LA+D
"A~X/LA,RBMX/0,3~X:RB~X.ALU/A+B,SHF/ALU.SPD.R,WRITE.RAB,s;:.c.~AS,~1"
R [ ] _LA+D+ 1
"M~X; LA, R CIV.X/ D, S~!X. 'R 81\'.X, A LU / A.,. 2+ 1 , SHF /A LU, SPO. R /l,o;R IT E. RA:.>. S ;oJ. RA 9 /@l1 "
R[
LA -- D
" A Mx I LA • R 8 :11 x / D • 6 '11 x ' ;:; 5 ~ ~ )( • A Lu A- 8 • s H FI A Lu • s p 0 . R / \~ R I T E . RAB • s :, J . R A 5; -" 1 ,,
R [ ]_LA+K [ ]
"AMX' LA. 6'.1l(;KMX. K~,,~ r;.;.2. A LU/ A .,.9. SH FI A LU. SPO. R/WR IT E. RAS. s ;cs. R.:.. S: G> 1 "
R[ ]_LA+K[ ]+1
"A1\1X/LA,B'.~X/KMX,hr.~x r,:~.ALu/A+B+1 ,R[>ii>1 ]_ALU"
R(]_LA-K[]
"AMX;LA.6~X/KMX.KM~1~2.A~U;A-B,SHF/ALU,SPO.R/WRITE.RAB,SrQ.R\5 @1'
R [ )_LA+K [ ] • R LOG "Ai,iX/ LA. 8''.X,1 r\M x. KM< 'i'2, A L'.J /A+ 8. R LOG, OT/ LON::;. SH F /A LU, SPO.:;: tJ~ I: E. RAB, S PO. RA.B/C1'1 •
R[]_LA-K[].RLOG "A~X LA.B~X/KMX,kMX 1 ~2.ALU/A-B.RLOG,DT/LO~G,SHF/ALU,SPO.R;~RITE.RAB.SP0.RAB/~1"
R6_LA+K[].RLOG
"AMX;LA,BJX,1KMX,hMX'@1 ,ALU/~•G.RLOG,DT/~ORD,SHF/ALU,SPO.~ ~~lTE.RA5,SPO.RAB/R6"
R6_LA-K[],RLOG
")MX'LA.3~X/KMX,t\MX ?1 ,A~U/A-8.RLOG,DT/~ORD,SHF/ALU,SPO.c, NR!TE.RAB.SPO.RAB/R6"
R [ }_LA+ 1.. C
" A:~ i< LA , B 'vl X / LC , A LL•/ ,i, + 3 , ; HF/ .'.. l U , S P0 • R /'AR IT E • RAS , S PO • RA 3 /@ 1
P [ ] _LA +MA SK+ 1
" A lv'1 X / LA , 5 V1 X /MA S '\ , A LU / A + B + 1 , R [ @l 1 ]_A LU "
R[ ]_LA-MASK-1
"ALU;A-B-1 .A~JIX,,LA,[;.1x/~.1ASK,SPO.R/WRITE.RAB,SPO.RAB/@1,SH"':AL.LJ"
R[ ]_LA.OR.D
"AMX/LA,R8MX/D.B~X. RBMX,ALU OR,SHF/ALU,SPO.R/WRITE.RAB,S ~.RA3/~1"
R[ ]_LA.ORNOT.MASK
"t.\iXiLA.BM..<. ~1AS'\ ALU;OR'.;OT,ShF/ALU,SPO.R/WRITE.R ::,s;:ic.RA8/@1"
R[]_LA+Q
"A~X/LA.RBMX/Q,BMXJ~B~X.
~U;A+B,SHF/ALU,SPO.R/~~ITE.RAB,
~J.~AB Pl"
R[)_LA-Q
"..\'.1.X/LA,RB\'X/Q,5'.1 X,' s::x, ~U,.A-2,SHF/,'.;LU,SPO.R/WRITE.RAB, ?C.RAB/@1"
R[]_LB
"B~X/LB,ALU/B,SHF/A u.s~
.R. •RllE.RAB,SPO.RAB , , ..
R[]_LC
"8'."1X,'LC,ALU/B,SH"'/A u.s;::> .R/~;R:TE.RAS,SPO.RAB,@1"
I

3:
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0

z
0

-4

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-4

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0
3:
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m
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en

n0
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R[]_LC.RIGHT
"BMX, LC,ALU/S,S~F;RIGHT,S?O.R/WRITE.RAB,SPO.RAB/~1"
R[]_NOT.O
"A~X;RAMX.OXT,DT;LG~G.ALU,NCTA,R[P1]_ALU"
R[]_NOT.0
"RA~X/D.AMX/RAMX,ALU/NOTA,R[~1]_ALU"
R[]_NOT.MASK
"BMX;MASK,AMX!RAMX.OXT,DT/LONG,ALU/ORNOT,SHF/ALU,SPO.R/W 0 ITE.RA6,SPO.RAB/@1"
R[]_NOT.Q
"RAMX/Q,AMX/RAMX,ALU/NDTA,R[@1]_ALU"
R[]_PACK.FP
"BMX/PACKED.FL,ALU/B,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/•1"
; R[ ]_Q. • • THRU R[ )_R LOG ...
R[]_Q
"SPO.R/WRITE.RA8,SPO.RAS/@1,RAMX/Q,AMX/RAMX,ALU/A,SHF/ALJ"
R[ ]_Q+1
"ALU_O+Q+1 ,R[li)l ]_ALU"
R[]_Q+5
"SPO.R/WRITE.RAB,SPG.RAB/~1 ,ALU/A+B+l,BMX/KMX,KMX/.4,AMX/RAMX,RAMX/Q,SHF/ALU"
R[]_Q-D
"SPO.R/WRITE.RAB,S 0 ~.RA8'?1 ,RA~X/Q,AMX/RAMX,R8MX/D,6MX/R6~X.ALU/A-B.SHF/ALU"
R[ LO-D-1
• s PO. R: WRITE.RA 8. SP J. PA B "~1 . Al'-l , A-B-1 • A~.1X/RA~.1X. RAMX/0. B~llX IR s:-.~x. RBMX/D. SHF I ALU.
R[]_Q+K(]
"5PO.R;wRITE.RAB.~PO.RA3 ~1 ,;~~X/Q,AMX/RAMX,BMX/~~X,KMX/~2.ALU/A+B,SHF/ALU"
R[]_Q-K[]
"SPQ.R,'wRITE.RA3,SP:J.PAS '.?1,RA:,1x;o,AMX/RAMX,5MX/~~·.~X.KMX/i'2,AL.U/A-B.SHF/ALU"
R[]_O-K[].RLOG "RA~X/Q,A~X/RA~X.S~X;KVX.K~X.~2.ALU/A-B.RLOG,DT/LONG,SHF·ALLJ,SDO.R/WRITE.RAB,SPO.RAB/01"
R[]_O+LB
"SPO.R,WRITE.RAB,SPO.RAB,~1 ,ALU A+B,AMXIRAMX,BMX/LB,RAMX;Q,SHF/ALU"
R[]_Q+LC
"SPO.R;WRITE.RAB,StJ.RA9:@1 ,RAMX/Q,AMX/RAMX,B~X/LC,ALU/ATB,S~F/ALU"
R[]_Q-LC
"SPO.R/WQITE.R~B.SPO.RA8'@1 .R~MX/Q,AMX/RAMX,B~X/LC,ALU/A-S.S~F/ALU"
R[ )_Q. AND. K[ ]
"A LU/ A\JD, S PO. R.''.\RITE.PI\ 3, SPO. f<A 5/@l 1 , Al'tX/RAMX, RAMX /0, BMX/ '.'. X, Kf,1X/@12"
R[]_Q.ANDNOT.K[]
"SPO.R/~RITE.RA8,SP0.RA9/~1,ALU/ANDNOT,AMX/RAMX.~A0X'Q,BMX/K~:.,KMX/•2,SHF/ALU"
R[]_O.OR.D
"SPO.R/~RITE.R~B.SPC.~AB.~1 ,ALU/OR,AMX/~AMX,R~MX/O,BMX/R~··~.RBMX'C.SHF/ALU"
R[)_Q.ORNOT.K[) "SPO.R/WRITE.RAB,SPO.RAS'~1 ,RAMX/0,AMX/RAMX,BMX/KMX,KMX/~2,ALU/ORNOT,SHF/ALU"
R[]_Q.RIGHT.1
"AlU_O,SHF/R!GHT,SPO.R;WPITE.RlB,SPO.RAB/01"
R[]_RLOG.RIGHT.1
"BMX/O,MSC/READ.RLCG,ALU/B,SHF/RIGHT,SPO.R/WRITE.RAB,SPO.RAB/@1"
;RC[]_o .•• THRU RC[]_O ...
RC[)_O
"AMX/RAMX.OXT.DT/LONG,ALIJ/A.SHF/ALU.SPQ.R/WRlTE.RC.SPO.RC::l!>l"
RC[)_O-D
"AMX/RAMX.OXT,DT/LONG,RBMX/D,BMX/RBMX,ALU/A-B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/•1•
RC[)_O+K[)+1
"AMX/RAMX.OXT,DT/LONG,KMX/~2,BMX/KMX,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/•1"
RC[)_O+LC+1
"AMX/RAMX.OXT,OT/LONG,BMX. 1 LC,ALU/A+B+1,SHF/ALU,SPQ.R/WRITE.RC,SPO.RC/~1"
RC[)_O+MASK+1
"AMX/RAMX.OXT,OT/LONG,BMX/MASK,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/01"
RC[)_O+MASK+1.RIGHT2
"AMX/RAMX.OXT,DT/LONG,BMX/MASK,ALU/A+B+1,SHF/RIGHT2,SPO.R/WRITE.RC,SPO.RC/01•
RC[)_ALU
"SHF/ALU,SPO.R/WRITE.RC,SPO.RC/P1"
RC[)_ALU.LEFT
"SHF/LEFT,SPO.R/WRITE.RC,SPO.RC/~1"
RC[)_ALU.LEFT2 "SPO.R/WRITE.RC,SPO.RC/•1 ,SHF/ALU.DT,DT/LONG"
RC[)_ALU.LEFTJ "SP0.R/WRITE.RC,SPO.RC/@1,SHF/LEFT3"
RC[)_ALU.RIGHT "SHF/RIGHT,SPO.R/~RITE.RC,SPO.RC/@1"
RC[]_O
"RAMX/D.AMX/RAMX,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/01"
RC [ )_O. OXT []
• RAMX/ D, AMX/RAMX. OXT, OT ;'@2, ALU/ I\, SHF ! AL:.J, SPO. R/WR IT E. RC, SPO. RC/@1"
RC[]_D.AND.K[]
"RAMX/D,AMX/RAMX,BMX/KMX,KMX/@2,ALU/AND,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"

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RC[]_D.AND.~ASK "RAMX D.AMX/RA'~X,B~X/~ASK,ALU/AND,SHF/ALU,SPO.R/WRITE.RC.SPO.RC/~1"
RC[]_D.ANONOT.Q "RAMX D,AMX/RAMX,R2~X!Q,BMX;RB~X,ALU/ANDNOT,SHF/ALU,SPO.R,'WRITE.RC.SPO.RC/01"
RC[)_D(8)
"R5'M<. D,S'•1(/RBC.1X,ALU/3,SHF/ALU,SPO.R/WRITE.RC.SPO.RC/llli1"
RC[]_D.CTX
"RA~X o,nMx/RA~X.ALU/A,SHF/ALU.DT,DT/INST.DEP,SPO.R/WRITE.RC.SCQ.RC/@1"
RC[]_D+K[]
"RA~~ D,AMX/RAMX,BMX/K~X.K~X1P2.ALU/A+B,SHF/ALU,SPO.R/WRITE.RC.SPO.RC/~1"
RC[]_D-K[]
"RAMX O,AMX;RA~X.BMX/KMX.KMX/~2.ALU/A-B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/~1"
RC[]_D.LEFT
"RA~X D.~WX/RA~X,ALU'A,SHF/LEFT,SPQ.R/WRITE.RC,SPO.RC/@1"
RC[]_D.LEFT3
"RA~X D.A~X/RAMX,ALU/A,SHF/LEFT3,SPO.R/WRITE.RC,SPC.RC/~1"
RC[]_D.OR.K[]
"RAMX D,AMX/RA~X.K~X/@2,6MX/KMX,ALU/0R,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/~1"
RC[]_D.OR.O
"RA~X D.AMX/RA~X.R3~X/Q,e~x/RBMX,ALU/OR,SHF/ALU,SPO.R/WRITE.RC,s~a.RC/@1"
RC[]_D.ORNOT.K[]
·s~o.RC;~1.SPO.Ri~RITE.RC,ALU/ORNOT,AMX/RAMX,RAMX/D,BMXiKMX,KMX/@2,SHF/ALU"
RC[]_D.SXT[]
"RAMX/D,AMA/RAMX.SXT,DT;@2,ALU1A,SHF/ALU,SPQ.R/WRITE.RC,SPO.RC/~1"
;RC[]_K ... THRU RC[]iVA_ ...

RC[]_K[]
"KMX/@2.BMX/KMX,ALU:B,SHF/ALU,S~O.R/WRITE.RC,SPO.RC/•1"
RC l ]_K [ l +1
"AMX,' RAMX. OXT. OT I LO!'.G. K'V.X, <[. 2' sn./KMX. ALU/ A+B+ 1 • SHF I ALU. s CQ. R/'vJR IT E. RC. SPO. RC/•1.
RC[]_K[].LEFT2 "KMX,@2.BMX/KMX,Alt' B,Sric;ALU.CT,DT/LONG,SPO.R/WRITE.RC.SPO.RC/D1"
RC[)_K(].RIGHT2 "KMX;@2,B~X/KMX.ALU;B.SHc;R!GHT2,SPO.R/WRITE.RC,SPQ.RC/@1"
RC[]_LA
"AMX/LA,ALU/A,SHF/ALU.SPO.R/W~ITE.RC.SPO.RC/@1"
RC[l_LA.AND.K[]
"ALU_LA.AND.K[~2].R...::[~1)_ALU"
RC[]_LA.CTX
"AMX/LA,ALU/A.SHF/ALU.DT,DT;INST.OEP,SPO.R/WRITE.RC,SPO.~C/P1"
RC [ ]_LA-K (]
"AMX/ LA. V.'tx/@:12. 8MX/~:M.X, ALU/ A-B. SHF /A LU, SPO. R/\llRITE. RC, SP2. RC,'@1"
RC[]_LB
"B~X/LS.ALU/B,SHF;AL~.SP~.R;~RiTE.RC,SPO.RC/@1"
RC[]_LB.LEFT
"B~X/LS.ALU/B.SHF/LEFT,s~c.R,WRITE.RC,SPO.RC/~1"
R c [ ]_ L c

" 9 ~-1 x / L c . A L CJ/ B • sH F /A Lu • s p 0 . R / \\ h r T E • R c • s pa • Rc / ~ 1 "

RC[]_NOT.Q
"RAMX/Q,AMX/RAMX,AL~/NOTA.RC[•1J_ALU"
RC[]_PACK.FP
"B~X/P~CKED.FL,ALU/8,SHF/ALU,SPJ.R/WRITE.RC,SPO.RC/~1"
RC[]_PC
"B~X/PC,ALU/B,SHF/ALU.SPO.R/WR:TE.RC,SPO.RC/@1"
RC[]_Q
"RAMX/Q.A~X/RAMX,ALG/A,Srlc/A~U.SPO.R/WRITE.RC,SPO.RC/~1"
RC [ ]_ 0 . 0 XT ( )
" RAM X/ 0 , A:~ X/RA i'.1 X. 0 XT DT/@2 , ALU/.\ , SH"'/ ALU , S PQ • R/WR IT E . RC , S ViJ • RC/~ 1 "
RC[)_O.AND.K[]
"RA~X10.A~X/RAMX,B~X k~X.K~X!F2,ALU/AND,SHF/ALU,SPO.R/WR!-E.RC,SPJ.RC/@1"
RC[)_Q.ANDNOT.K[]
"RAMX/Q,A~X. A~X.BMX;KMX,KMX/@2,ALU/ANDNOT,SHF/ALU,SFO.R/\llRITE.RC.SPO.RC/•1"
RC[]_Q+1
'ALU_O+·J+1,RC(P1]_AL"
RC[]_Q+K(]
"RA~X/0,A~X/RAMX,BV~ K~X.K~(/P2.ALU/A+B.SHF/ALU,SPO.R/~R:-E.QC.SPO.RC/@1"
RC[]_Q-K[]
"RA~X.Q,A~X/PA~X,B~~ K~X.KMXi~~.ALU/A-B,SHF/ALU,S?O.R/WR!TE.FC,SPO.RC/@1"
RC[]_Q.LEFT
"RA~X Q.~~X!RA~X.Al~ A,SHC;LEFT.SPO.R/WRITE.RC,SPO.RC/@1
RC[l_O.LEFT3
"RM,'X c.i.r;.-x/RA:.1x,Au.: A,SHF', L[FT3,SPO.R/'IJRITE.RC.SPO.RC/@li"
RC(]_Q-MASK-1
"RA~X Q.A~(/RA~X.BMX ~ASK,ALU/A-B-1 ,SHF/ALU,SPO.R;WRITE.~ .SPC.RC/@1"
RC[]_Q+PC
"Rf.,c,'A O.A~'.X/RA\~X.6'.;1;( ?C:,A:.U;t..+2,SHF,'ALU,S?O.R/v!RITE.RC.s: .RC,':?1"
RC[]_O+PC+1
'RAr.:x Q.:.r\IX/RAf,1X,!3:•'"< i='C,ALU,A+B+1,SHF/ALU,SPO.R/wRITE.RC, ",J.RC/@1"

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RC[)_O.RIGHT
-RAMX/Q,AMX/RAMX,ALU/A,SHF/RIGHT,SPO.R/WRITE.RC,SPO.RC/01"
RC[)_Q.SXT[)
"RAMX/Q,AMX/RAMX.SXT,DT/,2,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"
RC [ )_R LOG. RIGHT "BMX/0 I MSC/READ. RLOG' ALU/BI SHF /RIGHT' SPO. R/WR ITE. RC' SPO. RCi\El1"
RC[)&VA_D+O
"RAMX/D,AMX/RAMX,RC~X/0,BMX/R~MX,ALU/A+S,VAK/LOAD,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/~1"
RC(SC)_ALU
"SHF/ALU,SPO/WRITE.RC.SC"
;R(DST)_ ••• THRU R[]&VA_ ...
R(DST)_ALU
"SHF/ALU,SPD.AC/WRITE.RAB,SPO.ACN11/DST.DST"
R(DST)_D
"RA~X/0,AMX/RA~Y,ALU/A,SMF/ALU.SPO.AC/WRITE.RAB,SPO.ACN11/DST.OST"
R(DST)_O.SXT[].RIGhT
"RAMX/0,AMX!RAM~.SXT,DT/@1,ALU/A,SHF/RIGHT,SP0.AC;~R1TE.RAB,SPO.ACN11/DST.OST"
R(PRN)_ALU
"SHF/ALU,SPO.AC;WRITE.qA8.SPC.ACN/PRN"
R(PRN) D
"RAMX/D,A~X/~AMX,ALU/A,SHF/AL~.SPO.AC/WRITE.RAB,SPO.ACN/PR~"
R(PQN):O.OR.Q
"RA~X/J,A~X/RAMX,RB~X/0,5~X,RB~X,ALU/0R,R(PRN)_ALU"
R(PRN)_D[]O
"RA~X/C,A~X/RA~X.RS~x:o.s~x,RS~X,ALU/@1,R(PRN)_ALJ"
R(PRN)_D+K[].RLOG "RAMX/0,AMX/RA~X.~~X 1 ~1 .s~x:~~X.ALU/A+6.RLOG,DT/LDNG,R ~~Nl_ALU"
R(PRN)_D-K[).RLOG "RAMX/O,AMX/R~Mx.~Mx:p1,S~X/~VX,AL~/A-B.RLOG.DT/LONG,R,PRNJ_ALU"
R(PRN)_K[)
"KMX/@1.B~X/KMX,AL~;B.SHF/AL~,S~O.AC/WRITE.RAB,SPO.ACN/P~~·
R(PRN)_LA+K[].RLOG
"AMX/LA,KMX.·@1 .B~X;K~X.ALU/A•B.RLOG,DT/LO~G.R(PR:i)_ALU"
R(PRN)_LA-K[).RLOG
"A~X/LA,KMX:'~1,BMX/k~X.ALU/A-B.RLOG,DT/LONG,R(PR~)_ALW"
R ( P RN ) _ LA [ ] MASK " Ar.1 X/ LA , B,,, X/MA S K , AL~ / P. 1 , S '°' F/ ,:., LU , SP 0 . AC/ WR IT E . RAB , SP 0 . AC N · :: R'\ "
R(PRN)_LA+O
"A~X/LA,RS~X/0,E~X.~SMX,ALU/A+S,SHF/ALU,SPO.AC/WRITE.RAB,S?J.ACN/PRN"
R(PRN)_PACK.FP "BMX/PAC~ED.FL,ALU/3,S~F/ALU,SPO.AC/WRITE.RAS,SPO.ACN/PR~"
R(PRN)_O
"R~~X/0.A~X/RAMX,AL~IA,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/~RN"
R(PRN+1)_D
"RA~X/D.A~X/RAMX,ALU/A,SHF/ALU,SPO.AC/~RITE.RAB,SPC.ACN/P~N+~·
R(PRN+1)_0.QR.0 "RA~X/D,A~X/RA~X.R8~X,Q,9~X,R5~X,ALU/JR,SHF/ALU,SPO.AC/WR:TE.RA9,SPQ.ACN/PRN+1M
R(PRN+1)_LC
·e~X/LC.ALU/9.SHF/ALU,SP:.AC;wR!TE.RAB,SP0.ACN/PRN+1"
R(PRN+1 )_0
"RAMX;Q,~~X/RA~X,AL~/A,SHF/ALU,5PO.AC/WRITE.RAB,SPO.ACN/~;N•1"
R(SC)_ALU
"SHF/ALU,3P0.A~/WRITE.~A3,SPO.ACN/SC"
R (SC) _D
"RA'vlXiD. /-.SX/RA:U., A"...U /A, 511= I ALL:. SPO. AC/WRITE. RAB, SPC. ACN/S~"
R(SC)_LA+D
"A~X/LA,RSMX/D,S~X.'~2~X,ALG/A~5.SHF/ALU,SP0.AC/WRITE.RAB,S?O.ACN/SC"
R(SC)_LA-D
"Al/X/LA.~SMX/D,S~X'RS~X.ALU/A-B,SHF/ALU,SPO.AC/WRITE.RAB,S~O.ACN/SC"
R(SC)_L:
"ALU_LC,R(SC}_ALU"
R\SC)_O
"RA~ /0,A~X/RAMX,ALU/A,ShF/ALU,5PO.AC/~RITE.RAB,SPO.ACN/3C"
R(SP1+1)_LC
"B~X LC,ALU/B,SHF/A~U,5~0.AC:~RITE.RA9,SP0.ACN/SP1+1"
R ( S P 1+ 1 ) _0
" RM1 . 'C , Af\i X/ RA; 11 X, ALU /A , SH F,/ ALU , 5 P0 . AC/ WRl TE . RAB , SP 0 . AC N/ S 0 1 + 1 "
R(SP1)_ALU
"SHF ALU,SP0.AC/,.,RITE.R!\5,SPC.ACN/SP1.S?1"
R(SP1)_D
"RA~ ;O,A~X/RA~X,ALU/A.SHF/ALU.SPO.AC/WRITE.RAB,S?O.ACN/5~1. ?1"
R(SP1 )_K[]
"KMX ~1. gr.~X/K~.,x ALU '6,S'-iF AL'J,Sr>Q.AC/~·IR!TE.RAa.sPa.ACN/5?1 .s 1"
R(SP1)_PACK.FP "BMX P~ChEJ.FL. LU a,SHF;ALW,SPJ.AC/WRITE.RAB,S?O.ACN/SP1 .SP"
R(SP1)_Q
"RA~ /0,A~X/RAM ,ALU/A,SHF/ALU.SPO.AC/WRITE.RA3,SPO.ACN/SP1. P1"
R(SRC)_ALU
"SHF ALJ.SPO.AC ~RI7E.RAS.S?J.~CN11/SRC.S~C"

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R(SRC) D
"RAMX, D,Ari,X/RAMX,ALU/A,SHF/AL ,SPO.AC/1t;RITE.RAB,SPO.ACN11, 5-1 .SRC"
3::
RlSRC)=D(B)
"RBVIX/D,B~i'X/RBrJl)l,ALU/B,SHF/Al ,SP0.AC/WRITE.RAB,SPO.ACN11, :>~ .SRC"
R(SRC)_D+K[].RLOG "RAMX/D,AMX/RAMX.~.MX/El1,BMX KMX,ALU/A+B.RLOG,DT/WORD,R(S;rc A ... U"
(')
R(SRC)_O-K[].RLOG "RAMX/D,AMX/RAMX,KMX1@1 ,B~X K~X,ALU/A-B.RLOG,DT/WORD,R(SRC ALU"
~
R(SRC)_LC
"BMX;LC,ALU/B,R(SRCl_ALL.!"
0
R(SRC)_O
"RAMX/Q,AMX/RA~t.X,ALU/A,SHF/ALU,SPO.AC,lwRITE.RAB,SP0.ACN11,'SRC.SRC"
R(SRC!1)_ALU
"SHF/ALU,SP0.AC/WRITE.!\AB,SPO.A:N11/SRC.OR.1"
)>
R(SRC! 1 )_0(8)
"RBMX/D,B:VX/RBMX,ALU/B,SH"/ALU,SPO.AC/WRITE.RAB,SPO.ACl'.11 5RC.. wR.1"
G')
R[)&VA_LA+K[]
"AMX/LA,KMX/~2,B~X;KMX,ALU/A+B,VAK/LOAD,SHF/ALU,SPO.R/WR!TE.RAB,SPO.RAB/@1"
Z
R[ l &VA_LA-K []
"Ari.Xi LA. Kri:X/•2' BMX/f<MX. A:..u; 4-8. \'AK/ LOAD. SHF I ALU. SPO. R/WR l TE. ~:.B' SPO. R:.a/@1.
0
R[]&VA_LA-K[].RLOG
"AMX/LA,KMX1@2,B~X/~MX,ALU/A-B.RLOG,DT/LCNG,VAK/~O~D.SHF/ALU,SFJ.R/WRITE.RAB,SPO.RAB/•1•~
R[]&VA_Q-K[]
"RAMX/Q.AMX/RAMX,KMX/D2,BWX/KMX,ALU/A-B,VAK/LOAO,SPO.R/WRITE.RAB,SPO.RA6/91"
~
;SC_ •.•
(')

sc_O( A)
"AMX/ RAM.X. OXT. OT i LONG. EB'~X/ AMX. EXP. EALU/B. SMX/EALU. SCK/ LC:.:.D ,,
SC_O-K[]
"9MX/KMX,KMX/@1 ,AMX/RAMX.OXT,OT;LONG,ALU/A-B,SMX/ALU,SCK/L8hD"
SC_ALU
"SMX/ALU,SCK/LOAD"
SC_ALU(EXP)
"SMX/ALU.EXP,SCK/LOAD"
sc_o
"R Mft.X,'D. Ar.1x.IRA'!iX. ALU/ A. S~.1l(/ ALU. SCK/ LOAD"
sc_o. OXT [ ]-K [ l
"RAl'l:X/D. :.NX; RAMX. ox T. DT I ~1 • lo\MX, c"2. BM>'./ Kr.ix. ALU/ A-B. Sr.1X/ ALd. SC"./ LOAD"
SC_O.OXT[).XOR.K()
"RAMX/D,AMXiRAMX.OXT,DT;@l ,BMX/K!ViX,KMX/@2,ALU/XOR,SC_ALU"
sc_o. ANO. K[]
.. RA~.IX/D. Ar-.~x/RAMX. Krrx /~1 • SMX/KMX. ALU/ A!\;D. SMX/ ALU. SCK/ LOAD"
sc_D(EXP)
"RAMX/0,AMX/RAMX,ALU/A,S~X/ALU.EXP,SCK/LOAD"
SC_O(EXP)(A)
"RAMX/0,AMX/RA~X,EB~X/AMX.EXD.EALU/6,SMX/EALU,SCK/LOAD"
sc_o(EXP)(B)
"RBMX/D,BMX/RBMX,ALU/B,SMX/ALU.EXP,SCK/LOAD"
sc_o-K [ 1
• RAMX/D. AM.X/RAMX. KrlX/~1 • Brt.X/KMX. ALU/A-BI SMX/ ALU. SCK/LDAD"
sc_O.OR.K[]
"RAMX/0,AMX/RAMX,KMX/•1.BMX/KMX,ALU/OR,SMX/ALU,SCK/LOAD"
sc_D.SXT[]
"RAMX/D,AMX/RAMX.SXT,DT/~1,ALU/A,SMX/ALU,SCK/LOAD"
SC_EALU
"SMX/EALU,SCK/LOAD"
sc_FE
"SMX/FE,SCK/LOAD"
SC_NABS(SC-FE)
"EBMX/FE,EALU/NABS.A-B,SMX/EALU,SCK/LOAD"
SC_K(]
"KMX/•1,EBMX/KMX,EALU/B,SMX/EALU,SCK/LOAD"
sc_K[].ALU
"KMX/•1.BMX/KMX,ALU/B,SMX/ALU,SCK/LOAD"
SC_LA
"AMX/LA,ALU/A,SMX/ALU,SCK/LDAD"
SC_LA.AND.K[]
"AMX/LA,KMX/•1,BMX/KMX,ALU/AND,SMX/ALU,SCK/LOAD"
SC_LC(EXP)
"BMX/LC,ALU/B,SMX/ALU.EXP,SCK/LOAD"
sc_PSLADDR
"SMX/EALU,EBMX/KMX,SCK/LDAO,KMX/.F,EALU/B"
sc_o
"RAMX/Q,AMX/RAMX,ALU/A,SMX/ALU,SCK/LOAD"
sc_Q.ANO.K[]
"RAMX/Q.AMX/RAMX,BMX/KMX,K~X/@1,ALU/AND,SMX/ALU,SCK/LOAD"
sc_Q(EXP)
"RAMX/Q,AMX/RAMX,EBMX/AMX.EXP,EALU/B,SMX/EALU,SCK/LOAD"

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"RBMX;Q,BMX/RBMX,ALU/B,SMX/ALU.EXP,SCK/LOAD"
SC_Q+K[}
"RAMX/Q,AMX/RAMX,BMY/KMX.~MX/•1,ALU/A+B,SMX/ALU,SCK/LOAD"
sc_Q-K[)
"RAMX/O.AMX/RAMX,BMX/KMX,KMK/~1.ALU/A-B,SMX/ALU,SCK/LOAD"
SC_Q.OR.K[)
"RAMX/Q,AMX/RAMX,BMX/KMX,KMX/fl1,ALU/OR,SMX/ALU,SCK/LOAD"
SC_Q.SXT[)
"RAMX/Q,AMX/RAMX.SXT,OT/~1,ALU/A,SMX/ALU,SCK/LOAD"
sc_R[)
"SPO.R/LOAO.LAB.SPO.RAB/•1,AMX/LA,ALU/A,SMX/ALU,SCK/LOAO"
SC_RC[]
"SPO.R/LOAD.LC,SP0.RC/@1 ,BMX/LC,ALU/B,SMX/ALU,SCK/LOAD"
sc_R[].AND.K[] ·ALU/ANO,AMX/LA.SPO.R/LOAD.LAB,SPO.RAB/~1 ,BMX/KMX,KMX/•2.SMX/ALU,SCK/LOAD"
sc_R[](EXP)
"SPO.R;LOAD.LAS,S?O.RAB/@1,AMX/LA,ALU/A.SMX/ALU.EXP,SCK/LCAD"
SC_RC[)(EXP)
"SPO.R/LOAD.LC,SPO.RC/~1.BMX/LC,ALU/B,SMX/ALU.EXP,SCK/LOAD"
sc_sc+1
"EALU/A+1,SMX/EALU,5CK/L0AD"
sc_SC.ANDNOT.FE "EBMX/FE,EALU/ANDNOT,SMX/EALU,SCK/LOAD"
sc_SC.ANDNOT.K[]
"KMX/fl1 ,EBMX/KMX,EALU/ANDNOT,SMX/EALU,SCK/LOAD"
sc_sc+FE
"EBMX/FE,EALU/A+B,SMX/EALU,SCK1LDAO·
sc_SC-FE
"EBMX/FE,EALU/A-B,SMX/EALU,SCK/LOAD"
sc_sc+K[]
"KMX/•1.EBMX/KMX,EALU/A+B,SMK/EALU,SCK/LOAD"
sc_sC-K[]
PKMX/~1.EBMX/KMX,EALU/A-B,S~X/EALU,SCK/LOAD"
SC_SC.OR.K[)
"KMX/@1,EBMX/KMX,EALU;OR,SMX/EALU,SCK/LOAD"
sc_SC-SHF.VAL
"EBMX/SHF.VAL,EALU/A-B,SMX/EALU,SCK/LOAD"
sc_SHF.VAL
"EBMX/SHF.VAL,EALU/8,SMX/EALU,SCK/LOAD"
sc_STATE
"EALU/A,MSC/LOAO.STATE,SMX/EALU.SCK/LOAD"
SC_STATE.ANONOT.K[]
"E~LU/ANDNOT,ESMX/KMX,MSC/LOAD.STATE,SMX/EALU,SCK:LDAO,KMX/@1"
SC&STATE_STATE-R[](EXP) "LAB_R[@1],AMX/LA,EBMX/AMX.EXP,MSC/LOAD.STATE,EALU/A-B,SMX/EALU,SCK/LOAD"
; so_ .•. THRU VA_ ...
SC_Q(E~P)(B)

SD_NOT.SD
•SGN/NOT.SD"
so_ss
"SGN/SO.FROM.SS"
ss_o&so_o
"SGN/CLR.SD+SS"
SS_ALU15
"SGN/LCAO.ss·
ss_so
"SGN/SS.FROM.SD"
ss_ss.xoR.ALU15&SO_ALU15
"SGN/SS.XOR.ALU"
STATE_O(A)
"AMX/RAMX.OXT,DT/LONG,E9MX/AMX.EXP,EALU/B,MSC/LOAO.STATE"
STATE_AMX.EXP
"EBMX/AMX.EXP,EALU/B,MSC/LQAO.~TATE"
STATE_O(EXP)
"RAMX/0,AMX/RAMX,EBMX/AMX.EX~.EALU/B,MSC/LOAD.STATE"
STATE_FE
"EBMX/FE, EALU/B, MSc....· LOAD. ST ATE"
STATE_K[]
"KMX/@1,EBMX/KMX,EALU;B,MSC/LCAD.STATE"
STATE_Q(EXP)
"RAMX/Q,AMX/RAMX,EB~X/A~X.EXP,EALU/B,MSC/LOAO.STATE"
STATE_SC.VIA.KMX
·~SC/LOAD.STATE,EALU/B,EBMX/KMX,KMX/SC"
STATE_STATE+1
"EALU/A+1,MSC/LOAO.STATE"
STATE_STATE.AND~OT.FE

"EBMX/FE,EA~U/A~D~OT.MSC/LOAD.STATE"

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STATE_STATE.Ar-.::.·;~T.f\(:
"h\'iX/(?l1, 3:t.</i-'.!': ,EAL:.: t.!\DNOT,MSC/LOAO.STATE"
STATE_STATE+FE "E3~'X/FE,::.LU/At ,',loC/l .i.:.sr TE"
STATE_STATE-FE "EEr,1x!FE.EALU/A- ,\::c:L A).::.T TE"
STATE_STt.TE+K[] ·'KM\'Jl1,E:''!iX/Kr,i>:,E,'..L.U/A 9,MSC. LJAD.STAiE"
STATE_STATE-K(] "KMX/•1.E3MX/KMX,EALU/A-8,USC;~GAO.STATE"
STATE STATE.OR.FE
•EALU/OR,EB~X/FE,MS:/LOAD.STATE"

STATE:sr~TE.DR.K(]

"K~X/~1.ES~X/KMX,EALU/OR,MSC/LOAD.STATE"

;S1'\PC STATES
STATE_SKPLONG
"STATE_K[.4]"
STATE_STATE.AN.SKPLONG "STATE_STATE.AN)NQT.K(.4)"
;EDlTPC STATES
STATE FIRST
"STATE_K[ZE;O]"
STATE=P'<EDEC
"STATE_K[ .8~·;"
STATE STATE.AN.STOO
"STATE_STATE.A~J,CT.K[.3F)"
STATE-STATE.AN.6T04
"STATE_STATE.ANJNJT.K~.7F)"
STATE:STATE.AN.J:sr:BL "STATE_STATE.A~J~CT.~l .6]"
STATE STATE.AN.NDT~~EDEC
"STATE_ST.l.TE.ANJNOT.K[.7F)"
STATE:srATE.AN.D~EDECZERO

"STATE_ST.l.TE.A~CNOT.K[.CO]"

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STATE_STATE.OR.AC~:NP

"STATE_STATE.O~.K[.3)"

STATE_STATE.OR.CEST
STATE_STATE.OR.DESTDBL
ST ATE ST ATE . CR . F ! i.. L

"STATE_5TATE.OR.K(.4]"

::0

STATE:STATE.O~.F~CAT

"SlATE_STAfE.GR.~[.6]"
"ST ATE_ S; ATE . 0 '< • k [ .~7 ) "

3:
!!

"STATE_STAT~.OR.K[.60]"

STATE_STATE.OR.MOVE
"STATE_STATE.OR.KC.SO!"
STATE_STATE.GR.PATT1
"STATE_STATE.O~.K[.1]"
STATE_5TATE.OR.PATT2
"STATE_STATE.CR.K[.2]"
;1'.:ATCHC STATES
STATE INNEROBJ "STATE_K[ .1]"
STATE:!N"JERSRC "STATE_K[ .3]"
STATE_OUTER
"STATE_K[ZERO]"
SWAPD
VA_ALU
'JA D
vA=D.0.XT[]+Q
\'A_D. ANDNOT. K[]
VA_D+K[)
'/A_D+LC
VA_D+O

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,E.',"X/R8:\1X
"RA\~X: C·. A'.'>-. RA'.'X. a~.n /i\'.~ \. H;. ( :~1. ALU
"R:.·.~x·D,l'.:,•x ?:.'M(,h',1K.,1.sr:x.
'/X,ALU
"R.'\.;X1D, .,-;x PA\'..\,6 1 .1 ; L:.A:..u
+3,VAK
"Ri:~.'.\,'O.!t!l RAr..1x,RS'."•:, ~.S'.~":3'.'X,AL
"R:.'.~XoC,A','.X

RA~.:x.Q'.T ,CT;·.iio1

At..'J/A+9,VAK/LCAD"
A~;Dr·;DT. VAt</LDAD"
A+B,VAK/LOAD"
LOAD"
/A+B,VAK/LOAD"

Cl)

n0
z

VA~K[]
""C.'.X @-1,B'.'>:/KM:<,ALJ•B.VAK;LCAD"
VA_LA
"A~X LA.~LU/A,VAK/L2AC"
VA_LA.AND.LC
"A~X LA,3~X/LC,ALU ~NC,VA~/LOAD"
VA_LA.ANDNOT.K[)
"!.~X/LA.EMX K~X,K~X.~t.ALU/ANONOT,VAK/LOAD"
VA_LA+O
"AMX/LA,R8~X/0,C~X·R3~X,A~U;A+3,VAK/LOAD"
VA_LA-D
",:.,',1X/ LA. !'.;':".~X/i). t:.~:x 1c; :;:.1x. ALu/ A-3. VAK/ LCAD"
VA_LA+K[)
"A~X:LA.~~~/KMA.~~< 91,ALU/A+S,VAK;LOAD"
VA_ l A- K[ )
" AMX . LA , G',1 X/KM .< , K ·,1 X . (.:. 1 , A;_:.; / A- 6 , VA K/ L0 A() "
VA_LA+K [] +1
"Ai\I)( /LA. e·:x /f'.MX. KMX , . ;;.'. • ALU/ ,~ ... c+" • VAi~/ LOAD"
VA_lA-K(]-1
"A~X. LA,S~X/KMX,~~~ 01,A~J/~-S-1,VAK/LOAO"
VA_LA+~C

VA_LA+Q
VA_LA-Q
VA_LB+D.OXT
VA_PC
VA_ Q
VA_Q.A~D~OT.K[]

w
N
w

"A~A,LA.B~X/PC,ALU A~B,VA~;LCAD
"AMX/LA,R5~X/Q,8~X ~EMX,ALU;A+3,VAK/LOAD"
"VAK;LOAD,ALU/A-a.~~X;LA.EMx,R~~X.RJ~X/Q,SHF/AlU"
·e~x. L8,ALU/A+B.A~X:RA~x.:xT,DT•BYTE,VAK/lOAD"

"6i.1X, ?:,.~UJ/B,\/AK . LC:A2"
" R A fl': X i Q , !, '.·• .< / RA "\1..: , A '. L: / A , 11 AK/ LC •\ ::0
"RA~x;c.~:~;qA~X.~~X/~1 .:~x,KMX,ALU/ANDNCT,VAK/LOAD"

VA O+D
"VAK/LOAD.ALU/A•B,AVX/R~~x.~~x ~~MX,RA~X/Q,RBMX/O,SHF/AL~"
VA=Q+K [ ]
"R A\d. Q, AV'!-./ RA~·iX, I\~.:" /<?-1 , 3•; ~ ,' ;.,i.: <.A LU/ A-t-S, \'AK/ LC:AD"
VA_Q-K[]
"RA~X/Q,A~X/FA~X.K~A/~1,3~~ ~M(,ALU/A-8,VAK/LOAD"
VA_Q+LC
"RA~\;Q h~X1RA~X,S~l!LC,ALL .. A+8.VAK/LOAD"
VA_Q+LB
"RA~X.~.~~X/RA~X.2~~;LB,ALU,A+S,VAK/LOAD"
VA_Q-LB
"PA~X/0.~~X/RA~X,8~~/Le,A~U A-S,VAK/LOAD"
VA_Q+LB.PC
"RA~X:~.AMX/QAMX,S~X/PC.OR.LB,ALU/A+B,VAK/LOAO"
VA_Q+PC
"RAMX/Q,A~X/RAMX,BMX/?C,Al~/A+S,VAK/LOAD"
VA_R[]
"SPO.R/LOAD.LAB,SPO.RAB/~1,AMX/LA,ALU/A,VAK/LOAD"
VA_RC[]
"SPO.R/LOAD.LC,SPO.RC/•1,BMX/LC,ALU/8,VAK/LOAD"
VA_VA+4
"PCK/VA+4"
•Non-transfer Functions"
8.FORK
"LAB_RISP1),QK/ID,CLR.IB.COND,PC_PC+N,SUB/SPEC,J/B.FORK"
BYTE
"DT/5YTE"
CACHE.INVALIDATE
"MCT/INVALIDATE,VAK/NOP"
CALL
"SUB/CALL"
CALL[]
"CALL,J/@11"
C.FORK
"SUB/SPEC,J/C.FORK~
CHK.OOD.ADDR
"MSC/CHK.ODJ.ADDR"
CHK.FLT.OPR
"MSC/CHK.FLT.OPR"
CLK.UBCC
"CCK/LO~D.UBCC"
CLR.FPD
"MSC/C~R.FPD"
CLR.IB0-1
"IBC~CLR.0.1,IEK/ISTR"

(")

);:

fl)

(")

-4

0
r

!!
m
r

!!
z

fl)

n0
z

::!

CLR.IB0-3
CLR.192-3
CLR.192-5
CLR.IB.SOND
CLR.IB.OPC
CLR.IB.SPEC
CLR.NEST.ERR
CLR.SD&SS
EXCEPT. ACK
FLUSH. IS
IN>ilBIT.IB
li'HRPT. ACK
INTRPT.STROBE
IRD
IRDO
IRD1
IRD.11
LOAD.IS
LOAD.18.11
LONG
POLY.001\lE
RETURN(}
RETUR"lO
RETURN1
RETURN2
RETURN3
RETURNS
RETURN9
RETURNF
RETURN10
RETURN12
RETURN18
RETURN1F
RETURN20
RETURN24
RETURN40
RETURN60
RETURN61
RETURN1CO
RETURN10C

DISCARC -11 I~STR & OPERAND
"I6C/CLR.0-3"
11 MODE DISCARD !STREAM OPERAND
"IBC/CLR.2.3"
2ND PART OF Q/D IMMEDIATE
"IBC/CLR.1-5.COND"
" I 8 C CL R . 1 - 5 • Cm; D"
":BC/CLR.O,IEK/ISTR"
"IBC/CLR.1"
"MSC/CLR.NEST.ERR"
"SGNrCL.R.SD+SS"
"IEK.'EACK"
"IBC/FL.JSH,VAK/LOAD,IEK/ISTR"
"MCT/MEM.NOP"
"IEK/IACK"
"IEK/!STR"
" I RD 0 , C:.. '°' . UBC C , I RD 1 , SU 5 /SP E. C , J A.FORK"
"LA R(SP2l&LB RtSP1 ',D&v'A Lf3,S _ALU(EXP),FE_LA(EXP),SS_A~L15"
"MSE/IRD,QK/16,MCT;~LLO~.iB.RE J,IBC/CLR.1-5.CCND,PCK/PC~,.
"LA R(CSTl&LB ~ISRC),D LB.PC,~ K/LOAD,Q_IB.DATA,SC_K[.10].~CK/PC+N,MSC/IRD,SUB/SPEC,J/DPO"
"VA~:NO~.MCT/~EAD.V.NE~~c·
"VAK,NOP,MCT/READ.V.NE~~c·

"DT;LONG"
"ACF/CO~TROL,ACM/POLY.OONE"

"SL.'8/RET, J/@1"
"SUG/RET,J/O"
"SUB; RET ,J/1"
"SUB;RET,J/2"
"SUB 1 RET. J/3"
"SUBiRET,J/8"
"SUS 1 RET ,J/9"
''SUB/RET .J/OF"
•I

s u B ,,, ~ E T ' J / i 0 u

"SJB, RET,J/12"
"Sl.'8 RET,J/18"
"Slii3/RET,J.'1F"
"SUB. RET,v/:20"
''S·J3/RET, ·J 1 24"
'' S i... 3, R E T , J i 4 0 "
"SUS, R:;:T, J,-60"
"SUB. RET ,-.! ·61"
"S" 8 · RE T . J / 1 00 ''

"SUB

~E7",J/10C"

(")

)>
C)

z
0

(/)

::!
(")
(")

-i

r:D

s::

.,,m
z

(/)

n
0

z
::!

"->
C1I

RETURN10E
SET.CC(INST)
SET.CC(LONG)
SET.CC(ROR)
SET.FPO

·sua;RET,J/10E"
"CCK/!NST.DEP,DT/INST.DEP"

SET.N.AN~.z

·cc~;TST.Z"

SET.NEST.ERR
SET.N&Z
SET.PSL.C(AMX)
SET.V
START.IS
STOP.IS
TEST.TB.RCHK
TEST.TB.WCHK
TRAP.ACC[]
'.I/ORD
WRITE.DEST
"Branch

"MSC;SET.NEST.ERR"
"CCK!N+Z_ALU"

ACCEL?
ACC.SYNC?
AC.LOW?
ALIGNED?
ALU?
ALU.N?
ALU1-0?
BCDSGN?
C31?
CONSOLE.MODE?
80?
::; ( 1)?
Ci2?
02-0?
03?

1n-n

D31?
DATA TYPE?
D.80
D.81

D.62

"CCK/I~ST.DEP,DT/LONG"

"CCK/ROR"
"MSC/SET.FPO"

)>
G)

"CCK/C_A~XO"

"CCK/SET.V"
"IBC1START
"lBC/STDP"
"MCT/TEST.RCHK,VAK/NOP"
"MCT/TEST.WCHK,VAK/"IOP"
"ACF/TRAP,ACM/@1"
"DT/\\ORD"
11

"LAB_R(SP1J,0K/!D,CLR.!B.CO~D.PC_PC+N,SUB/SPEC,J/WRD"

Enable M3cro Definiticns"
"BEN,'ACCEL"
s E"I,' Ac c E L,,
; t J3/3"
"SEN/INTERRUPT" : 'J3/3 11
"BE~J/TS. TEST"
; t J5/17"
"BEN/A:..U"
; • J4/07"
"BEN-' ALU"
"BE'll;ALU1-0"
"BE~;/DEC IMAL"
: 'J2/2' 1
II

"BE~<,c31•
11

8!:"-.:1 PSL..T,1QOE"

BE~/D3-0"

BENil\;L,:_"
"8i:N:D3-0"
"SEN'D3-0"
"SEN 03-0"
BEN, J3-0''

,;5/1 B"
;,u4/GE"
;

'8~r-.4/SIG~JS

"Bf:~J/D.:i.TA.
YPE"
"8 ~ N. D , 3 \' T s·
"6 E~~ :>.an S"
6 E ,.~ / J . B Y T S"
0

en
~

n
n
0

:lJ

0
r-

:IJ

0
3::

:!!

e
c

.,,

: ,J4/08"
; , J-<; OB"
; ,J4/07"

3
0

J3;6"

II
1

:lJ

;

,J4 OE"
,J4 OD"

,J4 OB"

0
0
z
:i

DBL?
O. BYTES?
D.NE.O?
<:ALU?
=.ALU.N?
EALU.Z?
END.DP1?
FPO?
IS.TEST?
INT?
INTERRUPT.REQ?
r:rn?
ir.:O.C31?
! R1?
ir2-1?
i..AST.REF?

"6EN/DA-/J..• TYPE"
" 5 EN.- D. 9 .,. TES "
11

BEN, SIG:'45 11

"BE~, EALU"
"9E~.' EA:..U"
" 8 Et,; ' EA LU "
It

~
en

;Pl<EFERED FORM

:lJ

: , J4/C7' 1

; • J4/08"

9:. ~~ / E., J. D p 1 II

G'>

; ,J4/C7"
"3:::'</LAST.REF"
"SEN/ IB. TEST"
"8 E~•.' INTER RUN"
"9::'' l!>TE.RRUPT" ; • J1/5"
5~\. 'A.'._Ull
; ,J.!/00"

.. 8 ~~' 'A LU II
"BEN. l R2-1"
"5E~~-' rr::2-1

(')

; '1..3/6 11

0
z
-t

"BEN/L~ST.r>E~··

: ,J3,'~"

"SEN/REI"

~CDE.LSS.ASTLVL?

f;1:.J:..?
NEST.ERR?
PC.W.ODES?
PSL.C?
PSL..CC?
?SL. MODE?
?SL.N?
PSL.V?
PSL.Z?
PTE. VALID?
QUAD?
031?
RLOG.EMPTY?
ROR?
SC?
SC.GT.O?
SC.NE.O?
SIGNS?
SRC.PC?
SS?
STATEO?
STATE1?
STATE1-0?
STATE2?

31::

;,J3/5"

:lJ

0
r-

"BEN, N'L.J:.."
II

a=~~

•1 SE~,

,, on.
II

SS~.

L.AS1.REF"
PC .r.iGDES''
PSL..CC"
PSL. C'.:"
PS1...MODE"
PSL.CC"
PSL.CC"
PSL.CC"
TB.TEST"
JATA.TYPE"
SIGNS"
Ai..U1-0"
ROR"

''BE:\
"SEN
"BE"l
"BEN
"BEN
"BEN
"BEN
"BEN
"BEN
"BEN SC''
"BEN SC"
"BEN M'.JL"
"BEN SIGNS"
"BEN s~c.Pc·
"BE'li EAi..U"
"BE~ STATE3-0"
"BE:-. STATE3-0"
"BEN STATE3-0"
"BEN STA TE3-0"

; , J4/0B"

:lJ

; ,J4/0E"

.,,31::

: • ~4/7"
; , J4/0D"
; , J4/0B"
; , JS/OF"

m
r-

; ,J3/3"
; ,J4/7"

c
c

; ,J3/3"
COMP !VODE, BEN ON SRC R
,J4/CE"
,J4/0E"
,J4/0D"
,J4/0C"
,J4/0B"

0
z
en

-n
0
z

Si ATE3?
STATE3-0'?
STATE4?
STATES?
r,TATE6?
STAiEl7)?
STATC:7-4?
TB.TEST?
VA31?
V·~.31-30?

ZONED?
ALEG_D
ALEG_LA
ALEG LAB
ALEG=Q
ALU_OfK)
ALU_QTD+1
ALU_D. A!'J'.:). Q
ALU D.OR.MASK
ALU=D[]LB
ALU_O[)MASK
ALU_D[]RC[J
ALU_D[]R[)
A LU_D-1\ ( j
ALU_LA-LC

s::

; ,u4/07"

"8 ·;, ST A TE3-0"
~-.·s-.:.TE7-4"

~/STAT:07-4"

~/ST.l.TE7-4"

(")

:ti

'5TA'7"E7-4?

"8:0:\/57ATt:_7-4"
" BP<, T 8 . T EST ''

G')

"3E'\/PSL.~.~CJDE"

;,JS/OF"

"8EN,'PSL.MODE''
"8 E'<, Z"

; ,JS/07"

"9E~'DEC!MAL"

;.~2/1"

2
0
en
-t

"t¥X/RA~X,R.l.MX/D"

"AMX/LA"
•t..r.~X/ LA"

(")

"A~X/RAMX,RAMX/J"
"K~X/ZER0,9~X/K~X.ALU/8"
"A~X;RA~X.OXT,DT/LO~G.RBMX/D,B~X/RBMX,ALU/A+B+1"

0
2
-t

:ti

"RAMX/D,AMX'RA~X.B~<:MASK,ALU/OR"

0
r-

"RAMX/0,A~~

RA~X.5~~1LB.ALU/@1"

"RAMX/D,AMX

RA~X.EMX•~.\SK,ALU/@1"

"RAMX '0, AM(/ RA'>'lX, RE?'.'~ /Q. B:1~X/RBMX, ALU/ AN:>"

::tl

s::

"A~X/RA~X,RAMXD.LC_R:[~2),6~X/LC,ALU/@1"
"AMX/RAVX,R~MX;~.LA6_R'.~2]rBMX/LB,ALU/@1"
"8:•1X/ R 3'.';t,, R 3~1iX/:), :..AS_R [ :i'-1], AMX/ LA, ALU/ A-B"

"AMX/ LA, BriJ,' LC, .\~Ji :,-B"

ALU=LA[]K[)

ArJ1X/ LA, B~.1.:< . LC, A LG 1 A!\!D 11
"t..MX/LA.B~X 'K~X.~MX,~2.ALU/@1"

ALU_LA~]LC

"A~X/LA,B~X'LC,ALU/~1"

ALU_~ASK

·s~x1MASK,A~U;S"

A LU

LA. A~D. LC

"8 >.;:STATEJ-0"
"B

ALU M~SK+1
"A~X;RAMX.OXT,~T ~:~G.B~X/MASK,ALU/A+B+1"
A LU=NO T. K [ l
~\1X/R .\MX. o,, T. '.)T / LCNG' l\'.'.X/@1. B:V:X/KMX. ALU/ORNOT
ALU NCT.LA
"A~X/LA,ALU ~OTA"
ALU-NO'i.MASK
•,:.~x/RA~X.GXT,DT;~C 3,5~X/~ASK,ALU/ORNOT"
ALU-NOT.Q
"RAMX/Q,A~M t:!:.·u.;,t._ .NC:A"
ALU=Q+D "'lA:-llX/Q,4'.'..X 'RA1.1X,E'~.'.</P.B\~X.;. L•/A+B"
ALu_o-sc
''.._;ix; sc, s·~x: t<. 1.1x. r; ,u.1 .· o. Ar.1x; RArtx, ALU/ A-B
ALU_Q[J1..8
"RAMX/0.AMX R.:.~,•x,5:,~ ':.B.ALU/Cil1"
II

ALU_Q[]~ASK

"RAMX/0,A~~

~A~X.5~

.~lS~,ALL/•1"

ALU_Q.A~C.MASK

"RAMX/Q,A~X

R~~X.E~

. VASK,ALU/A~D"

.,,m
II

2
en

n
0
2

::!

ALU_Q.OR.MASK

"RAMX/Q,AMl:RA~X.91/~

ALU_Q.O~~OT.MASK

"RA~X/Q,A~X;RA~X.BMX;MASK,ALU/ORNOT"
"LC_RC[~1 ],;..MX/RA~X.RA~X/Q,BMX;LC,ALU/XOR"
"LAB~R(SC) .B~X/LB.AM~/RAMX,RAMX/Q,ALU/XOR"

ALU_Q.XOR.RC[]
ALU_Q.XOR.RlSC)
ALU_Q[ Jo<[]
ALU_Q[]LC
ALU_Q[)~C[]

ij
00

"RAMX/Q,A'~X,

MASK.ALU/OR"

;.;,i,Mx,1<.:11.·.:.,;;;2,BMX/KMX,ALU/@1 11

"RAMX/~.A~X RA~X,3~X/LC,ALU/@1"
"AMX/RAMX,~;~X/0.LC_RC[~2],BMX/LC,ALU/@1"
"A~X/R,J,~X.RJ~X/J.LAS_R[~2],BMX/LS,ALU/,1"
"SPO.AC/LOAO.~AS,SPO.ACN/SC,AMX/LA,ALU/A"

ALU_Q[]R[)
ALU_R{SC)
ALU_RLOG
"MSC/READ.QLOG,ALU;B"
ALU_R[].ANO.MASK
•SDO.R/L0AD.LAS,SPO.RA8/~1.AMX/LA,6MX/MAS~.ALU/AND"
ALU_R[].OR.MASK "SPO.R/LOAC.LA8,S?O.~A9,@1,AMX/LA,BMX/MASK,ALU/OR"
ALU_R [ J • OR"-407. MASK
"SPC. R/ LO.:.D. LAB, SPO. RA3/©lt • .AMX/ LA, er.ix/MA SK.;.. LU/CR:-.or •
ALU_R[]-K(]
"SPO.R/~OAD.LAB,SPO.RAB/@1,AMX/LA,KMX/02,BMX/KMX,ALU;A-B"
ALU_R[]+K[]
"SPO.R/LCAD.LAB,5?0.RAB/@1 ,AMX/LA,KMX/~2.BMX/KMX,ALU/A+B"
ALU_SC
"K~X/SC,SMX/KMX,ALL/B"
BLEG_D
"B~X/R8~X,R3MX/D"
BLEG_LB
"8MX/LB"
BLEG_LC
"8MX/LC"
BLEG_Q
"8MX/RB~X,R5MX/Q"
CPSYNC
"ACF/SYNC"
DELAY
"CALL[ DELAY]"
O_O-K[]
"AMX/R~MX.OKT,KMX/~1,BMX/KMX,ALU/A-B,D_ALU"
O_ACC
"CK/ACCEL"
DD-LB
"PAr'l.X/L::,AMX 'RAMll.. ST,'X/LS.ALU/A-B,!:' ALU"
D=D[ ]RC[]
"ALU_D[~1 Ji<:[:a2J .C_-"LU'
O_D.A~D.~[]
-cSMX/D.5MX RB~\,5PQ.R/LOAD.LA9,SPO.RAB/~1,AMX/LA,A~U;AND,D_ALU"
D D LEFT ~
-~~,L~FT
51 r•v•
oq. R ( j
·
6~.~.; 'RS\~x. s 0 o. R/ LOAD. LAB. SPO. RA3/~1 , AMX/LA. A. u:; CR, o_~Ll.i"

o:o:

Rt::;u/o.

n
:D
0

;

0
-t

n
0

-t
0
r:D

O_O.SXT[]+~[]
o_o.xa~.R:[]

"PAMXl~ 1 AMX/R~~X.SXT,OT,@1 ,K~X/@2,6MX/KMX,ALU/A+~.D_AL~"
"RAMX/0,AMX!RA~X.SPO.R/LOAD.LC.5PO.RC/@1,6MX/LC,ALJ/~JR,D_A~U"

0 LA+D
0-LA.OR.D
0-MASK
0 - MASK+1
0-NOT.RC[J
0-Q.OR.O
0-MD
0-R[J.LEFT
o:R[].OR.D

"AMX/LA,R8MX/D,8MX'RSMX,ALU/A+B,D_ALU"
"AMX/LA,R8MX/D.BMX/R5MX,ALU/OR,D_ALU"
"BMX/MASK,ALU/6,D_ALU"
"AMX/RAMX. OX T, B~v'IX,'MASK, ALU/ A+B+1 , D_A LU"
"AMX/RAMX.OXT,SPJ.R/LOAD.LC,SPQ.RC/@1,BMX/LC,ALU/ORNOT,O_ALU•
11
"RAMX/Q,AMX/RAMX,ALU;OR,SHF/ALU,DK/SHF,BMX/RBMX,RSMX10
"DK/NC?"
,

=t
0
z

"SPO.R/LC•D.LAB,SPO.RAS/@1,AMX/LA,ALU/A,SHF/LEFT,J~/SHF"
"SPO.R/LOAD.LA6.SPO.RAB!~1,AMX/LA,RBMX/D,BMX/RBMX,ALU/0R,O_ALU•

n
0
z

::!

O_R[J.ORNOT.MASK "SPO.R/LOAD.LAB,SPO.RA3/@1,AMX/LA,BMX/MASK,ALU/ORNOT,O_ALU"
o_sc
"KMX/SC,9MX/KMX,ALUIB,S~F/ALU,DK/SHF"
EALU_STATE-K[J
"E9MX/KMX,KMX/~1 ,MSC/LDAD.STATE,EALU/A-B"
EBMX_K()
"l".MX/11>'1, EBMX/KMX"
ENDOVR "SUB/CALL,J/SCOPE"
ERLOOP "SUB/CALL,J/ERLDOP"
ERROR1
"SUB/CALL.J/ERROR1"
ERROR2 "SUB/CALL.J/ERROR2"
LAB_R(PRN)
"SP0.ACILOAD.LA6,SPO.ACN/PRN"
LAB_R(PRN+1)
"5P0.AC/LOAD.LA9,SPO.ACN/PRN+1"
LAB_RISP1+1)
"SPO.AC/LDAD.LAB,SPO.AC~/SP1+1"
LAB_R(SRC!1)
"SPO.AC/LO~D.LA9,SPO.ACN11/SRC.OR.1•
LAB_RISP2)
"S?O.AC/LOA).LA3,SPJ.ACN/SP2.SP2•
LAB_R(SP2.SP1) "5PO.AC/LO~D.LAB,SPO.ACN/SP2.SP1•
MESSAGE1
"D_K[ZERO],CALL;~SGCDM)"
MESSAGE2
"D_K[.1],CALL(M5GCOM)"
MESSAGE3
"D_K(.2},CALL[~SGCOM)"
MESSAGE4
"D_K[.3],CALL[MSGCC~]"
MESSAGES
"D_K[.4],CALL[MSGCOM)"
MESSAGE7
"D_K[.6],CALL[~SGCCM]"
MESSAGES
"D_K[.7).CALL[MSGCO~]"
MESSAGE9
"D_K[.8],CALL[MSGCO~j"
MESSAGE10
"D_K[.9],CALL[MSGCDM)"
NE~TST
"SUB/CALL,J/SCOPE"
NEwTST[]
"NEwrs·.·.~c[OF]_K[~1]"
NOP
"DK/NOP"
Q_ACC
"OK/ACCEL"
O_D[ ]Q
"RAMX/D. AMX,'RAMX. sr.,X-'RG"1X. RBiv'IX/Q, ALU/@1 ,Q_ALU"
O_D[]RC[]
"RAMX/D,A~K;RA~X.SPO.R;LDAD.LC,SPO.RC/~2.BMX/LC,ALU/@1,Q_ALU·
Q_K(SP1)
"KMX/SP1.CO~.BMX/k~X,ALU/B,Q_ALU"
Q_MASK+1
"AMX/RAMX.OXT.BMX MASK,ALU/A+B+1,Q_ALU"
Q_not.mask
•amx/ra~x.Oct,bm<.~~sk,~lu/ornot,Q_alu"
Q_Q.AND.LC
"RAMX/Q,AM~ RAWX,SMX/LC,ALU/AND,Q_ALU"
Q_Q. AND. MASK
"RA!VIX/0, A~,,X. RA~.'.X. 3~ -<:MASK, ALU/ AND, O_A LU"
Q_O. AN.:>. Rl)
"RSMX/0, 5:,i:.·.. · ?.8"1X, SPQ. R/ L.OAD. LAB, SPO. RAB/11il1, AMX/LA, ALU,' A!'<D, Q_ALU"
Q_Q. M4DNOT. RC [) '' RAMX/0. AMX. RAM.<, SPO. R/ LOAD. LC, SPO. RC/@1, B~1X/LC, ALU/ ;.t,ONOT ,Q_ALU"
O_O.LEFT~
"OK/LEFT2"
o_o. XOR. D
"R AMX/0. A~,1.<: RA~)(. ClC';lX/D. SMX/RBMX. ALU/XOR' D_A LU"
o_o.xc~.R[)

RC[]_O-K[]

"OK/SHF,A~~·R~~X.RA~X;Q,BMX/LB,ALU/XOR,LA8_R[01]"
·~MX/RAM(.CXT.KM( ~2.B~X/KMX,ALU/A-B,RC[~1J_ALU"

n
:0
0

);

n
n
0

-4

r:0

::!!

::!!
z
~

0z
en

n0
z

:::!

RC[]_O+O
"RAMX/0,AM~.·RA~X.RBMX/0,BMX/RSMX,ALU/A+B,RC[01]_ALU"
RC[]_O.AND.LA
"RBMX/D.BMX'RBMX,AMX/LA,ALU/ANO,RC[01]_ALU"
RC[)_O.ORNOT.MASK "ALU_O.O~NOT.MA3K,RC[@1]_ALU"
RC[]_O.XOR.LAB "ALEG_O,BLEG_LB,ALU/XOR,RC[~1]_ALU"
RC(]_O.xOR.LC
"ALEG_O,BLE3_LC,ALU/XOR,RC[@1]_ALU"
RC(]_O+MASK+1
"RAMX/D,A~X/RAMX,BMX;MASK,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPO.RC;01•
RC(]_LA+D
"AMX/LA,RBMX/D,8MX;R5MX,ALU/A+B,RC[01]_ALU"
RC(]_LAB.XOR.LC "ALEG_LA,BLEG_LC,ALU/XOR,RC[01]_ALU"
RC(]_MASK
"ALU_MASK,RC(@1]_ALU"
RC[]_NOT.O
"AMX/RAMX.OXT,DT/LONG,ALU/NOTA,RC[01]_ALU"
RC[)_NOT.D
"ALU_NOT.D,RC[•1]_ALU"
RC[]_NOT.MASK
"BMX/MASK,A~X/R~MX.~XT,OT/LONG,ALU/ORNOT,RC[01]_ALU"
RC[]_O+LC
"RAMX/Q,AMX/RAMX,eMX/LC,ALU/A+B,RC[01]_ALU"
RC[]_Q.ANO.LA
"RSMX/Q,BMX/RBMX,AMX/LA,ALU/AND,RC(01]_ALU"
RC(]_Q.OR.SC
"RAMX/Q,AMX!RAMX.KMX!SC.BMX/KMX,ALU/OR,RC(@1]_ALU"
RC[]_Q+MASK
"RAMX/Q.AMX/RAMX,BMX 1 MASK,ALU/A+B,RC[~1]_ALU"
RC[]_Q+MASK+1
"RAMX/Q,AMX/RA~X,6MX:MA3K,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/01•
RC(]_Q.XOR.LAB "ALEG_Q,BLE3_La,ALU/XO~.RC(~1]_ALU"
RC(]_Q.XOR.LC
"ALEG_Q,BLEG_LC,ALU/XCR,RC[01]_ALU"
RC(]_SC
"ALU_SC.RC(~1]_ALU"
RC(]_SHF
"SPO.R/~R!TE.RC.SPO.RC/~1"
R[]_ALU.RIGHT2 "SHF/RIGHT2,SPO.R;~RITE.RAB,SPO.RAB/@1"
R(]_O.AND.Q
"RAMX/D,AMX,'RAMX,BMX/RS~X.ALU/ANO,SPO.R/WRITE.RAS.SPO.RAB/01"
R[]_O.ANO.RC[] "RAMX/O,AMX/RAM~.sro.R;LCAD.LC,SPO.RC/@~.BMX/LC,ALU;ANO,R[@1]_ALU"
R[]_O.ANDNOT.MASK "RAMX/0,A~X/RAMX,B~X;~ASK,ALU/ANDNOT,R[@1)_ALU"
R[]_D.ANONQT.Q "RAMX/0,AM~/R~MX,RBMX/Q.BMX/RBMX,ALU/ANDNOT,R(@1 ]_ALU"
R[]_D.LEFT
"RAMX/0,AMX/RAMX,ALU/A,SHF/LEFT,SPO.RAB/01,SPO.R/~RITE.RAB"
R[]_O.OR.K[]
"RAMX/O,AMX,RAMX,KMX/~2.8MX/KMX,ALU/OR,R[@1]_ALU"
R[]_D.ORNOT.MASK "RAMX;D,AMX;RA~X.BYX/MASK,ALU/ORNOT,R[@1]_ALU"
R[]_O.XOR.LAB
"ALEG_D,BLEG_LB,ALU1'XOR,R[~1 ]_ALU"
R[]_O.XOR.LC
"ALEG_O,BLEG_LC,ALU;XOR,R[~1]_ALU"
R[]_LA.OR.K(]
"R[~1]_ALU,AMX/LA,SMX;KMX,KMX/~2,ALU/0R"
R[]_LAB.XOR.LC "ALEG_LA,BLEG_LC,ALU/XOR,R[@1]_ALU"
R[]_NOT.LA
"AMX/LA,ALU/~OTA,SPO.R/wRITE.RAB,SPO.RAB/@1"
R[]_Q.XOR.LAB
"ALEG_Q,BLEG_La,ALU/XOR,R[~1]_ALU"
R[]_Q.XOR.LC
"ALEG_Q,BLEG_LC,ALU/XOR,R[@1]_ALU"
R[]_SHF
"SPO.R/WRITE.RAB,SPO.RAB/@1"
RETUR~4
"SUS/RET,J/4"
SC sc-1
"KMX/.1,EBMX/K~X.EALU/A-B,SMX/EALU,SCK/LOAD"
SEiMCR[]
"R[OA]_K[~1],CALL,J/SETMCR"

~
n
~

0
0

n
n
0
2

~
~

c
c

m
~

2
~

0
2

2
~

SETRCF[]
"SC_Kp1 ,('"LL,J,'SEH:C
SETRXCS[]
"R[OA]_K ~lj,CA~L.J;SE RXCS"
SETTXCS[]
"R[OA]_K @1] ,CAL.L,J/SE iXCS"
SUBTEST "CALL,J/SUBTST"
TRAP.FPA
"ACF/CONTROL,AC:.1j7"
VA_O.OXT[]
"ALU_O.OXT[~l],VA_ALU"
VA_O.OXT[ ]+K(]
"ALU_O.OXT[,~1 ]+~~·:=:>2] ,VA_ALU"
VA_R[]+K[}
"SPO.R;LOAD.LAB,S?O.~A21@1 ,KMX/P2,BMX/KMX,AMX/LA,ALU 'A+B,VA_ALU"

::l:J

)>
G')

0
BRANCH DEFINITIONS
ALU. Z?
ALU.C?
01-0?

"BEN/Alu"
"BEN/ALU"
"BEN/03-0"

NOTE J/XXB NESSECARY

n
n
0

::l:J

0
,...
::l:J

,...m

c
c

.,,

m
2

0
2

n
0
2

::!

CHAPTER 9
MISCELLANEOUS

LOGIC SYMBOL
3

UI
Cl>

....c

Vee= PIN 16

"T1

GND =PIN 8
13

1-3

1-2

~
0

Cl>

-I

1-1

"T1

-f

-f
::J:J

(ii
-f
)>

-f

"ti

-f

lo i.1121.3 Y3 Y2 Y1 Yo

HXX

XXXXXXXZZZZ

H =HIGH

X =DON'T CARE

L =LOW

Z =HIGH IMPEDANCE STATE

DJD2D1Do x x

x D3D2D1 Do

Dn AT INPUT In MAY BE EITHER HIGH OR LOW AND OUTPUT

xD2D1DoD.1x

xD2D1DoD1

Y m WI LL FOLLOW THE SELECTED Dn INPUT LEVEL.

x x D1DoD.1D2x D1DoD1D.2

x DoD.1D2D.3 DoD.1D.2D.3

::D

-I

TRUTH TABLE

:j
:::c

13 12

n
:g

::J:J

OE S1

LOGIC DIAGRAM

::J:J

Q
::D

n
c:

-I

)>
G)

::D
)>

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

26S10 BUS TRANSCEIVER CHIP

OUTPUTS

INPUTS

8 z

H =HIGH
L= LOW
X = DON'T CARE
Y =VOLTAGE OF BUS
(ASSUMES CONTROL BY
ANOTHER BUS TRANCEIVER)
IC·26S10

336

VAX-11nso INTEGRATED CIRCUIT DIAGRAMS (CONT)

74LS181 ALU CHIP

OUTPUTS
CARRY
GENERATE

COMPARATOR

A=8

COUT

20
21

A2
74181

FUNCTION
OUTPUTS

01
02

CARRY
PROPAGATE
17
15

WORD
INPUTS

CARRY
16

AO
S3 S2
03

M CIN
VCC=PIN24
GND=PIN12

04 05 06 OB

MODE
CARRY
INPUT

FUNCTION
SELECT
INPUTS
74181

74181

TABLE OF LOGIC FUNCTIONS
Functtons.tect

L
L
L
L
L
L
L
L

L
L
L
L

L
L

H
H
H
H
H
H
H
H

H
H

TABLE OF ARITHMETIC OPERATIONS

Output function
Positiwelogic
N•tiwelotfc:

•A

f ·i
f•A+i
t •AB

f ·ll
f •i+B

f • LOl'Q4 1

f1tLotM:lilD

f ..

L
H

L
L
L
L

L
L

f •A®B

H
H

I •B

L
L

L
H

H
H

f .. A+B
f•lotiealO
f •Ai
f •AB

• ..... a

H
H
H
H

I •A

L
L
H
H

•A+i
•iB

With moch con"l IMI hith: Cin irr•vant
Forpo51tiwelogie· logicall•hifhvolbge

·i

Hiltl Lewtl Act""'1

t•A8minus1

f•A+B

t•Aiminus1

f•A+i
f•miftul1(2'scomplllmend
f .. AplusAi

f•ApklsB
l•A"iplus (A+B)
fsA+B
f•ApM;At

f• {A+B) plus Ai
f•Aminul8minus1
f .. Aimtnust
f•AplusAB
f•Aplu58
f• (A+iJ plusAB
f•ABminus1
f•AplusAt

f =A+i

f•ABplusA

f • (A+B) plusA

t •A+B

f•AiptusA

f• [A+il pMA

f =A©B

f•Aminus8minus1

I •Al

f•A+i

1 =i+e
f "'A@B

f•Aplus (A+B)

f :sLogieal 1

f•AminUl1

With mode control (Ml ...,.. cin 1ow
t Each btt is shifted to the Mxt more signthc:ant pGSition.

~O•lowvolt•

For neptive Jotic:

Outputf...aion
Low Levels Active

f•minus1 l2'1comp..,,_.tl
fsAplus [A+il
f•ABplus (A+il

I •A+B
f .. j
f zA\£18

H
H
H
H

FunetionSetec:t
52
S1
SO

totfcal 1 •low volt•
logicalO•hithwolt•

337

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

74182 LOOKAHEAD CARRY CHIP
PIN DESIGNATIONS
Designation

Pin No.

GO, Gl, G2, G3
PO, Pl, P2, P3
CIN
COUTX,COUTY,COUTZ
GOUT
POUT

Function
ACTIVE-LOW CARRY GENERATE INPUTS
ACTIVE-LOW CARRY PROPAGATE INPUTS
CARRY INPUT
CARRY OUTPUTS
ACTIVE-LOW CARRY GENERATE OUTPUT
ACTIVE-LOW CARRY PROPAGATE OUTPUT
SUPPLY VOLTAGE
GROUND

3, 1, 14, 5
4, 2, 15, 6
13
12, 11, 9
10
7
16
8

Vee
GND

GOUT

POUT

CO UTZ

74182

COUTY

COUTX

74182

P2
14

CIN

74182

VCC= PIN 16
GND= PIN 08
IC-74182

338

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

74LS670 4 X 4 REGISTER FILE CHIP

D1
D2
D3

}DATA INPUTS

WA
WB
GW
GR

OUTPUT

}READ SELECT

}WRITE SELECT

WRITE ENABLE

READ ENABLE

vcc

GND

TRUTH TABLES
WRITE FUNCTION TABLE
(SEE NOTES A, B, AND C)

WRITE INPUTS

READ FUNCTION TABLE
(SEE NOTES A AND D)
READ INPUTS

WORD

OUTPUTS

O=D

WOB1

WOB2 WOB3

WOB4

O=D

Ga
Ga
Ga

Ga
Oo

W1B4

Ga
Ga
Ga
Oo

Ga
Ga

W1B1

W1B2 W1B3

W2B1

W2B2 W2B3

W2B4

O=D

W3B1

W3B2 W3B3

W3B4

A. H =HIGH LEVEL, L =LOW LEVEL, X =IRRELEVANT, Z =HIGH IMPEDANCE (OFF)
B. (0 = D) =THE FOUR SELECTED INTERNAL FLIP-FLOP OUTPUTS WILL ASSUME THE STATES
APPLIED TO THE FOUR EXTERNAL DATA INPUTS.
C. Oo =THE LEVEL OF 0 BEFORE THE INDICATED INPUT CONDITIONS WERE EXTABLISHED.
D. WOB1 =THE FIRST BIT OF WORD 0, ETC.
IC-74LS670

339

VAX-11nso INTEGRATED CIRCUIT DIAGRAMS (CONT)

82S23. 825123 256-BIT BIPOLAR PROM CHIP

32 x 8 ARRAY

THE 82S23 USER OPEN COLLECTOR OUTPUTS.
THE 82S123 USER TRISTATE OUTPUTS.

Vee= ( 16)
GND = (8)
(N) = DENOTES PIN NUMBERS
IC-82523
825123

340

VAX-11nso INTEGRATED CIRCUIT DIAGRAMS (CONT)

85S68 64-BIT EDGE-TRIGGERED D-TYPE REGISTER FILE CHIP WITH
TRISTATE OUTPUTS

AO
A1
A2
A3

6
4

}ADDRESS

OUTPUT{ 10

WRITE ENABLE

01
02
03
04

D1
D2

}DATA INPUT

D3
D4
OS

OUTPUT STORE

OUTPUT DISABLE
WRITE CLOCK
14
WC

vcc 18
GND9
TRUTH TABLE
OD

WE CLK OS

MODE

OUTPUTS

L
H
H

x
x
x

OUTPUT STORE
WRITE DATA
READ DATA
OUTPUT STORE
OUTPUT DISABLE

DATA FROM LAST ADDRESSED LOCATION
DEPENDENT ON STATE OF OD AND Os
DATA STORED IN ADDRESSED LOCATION
Hi-Z
Hi-Z

x
H
L
H

IC-85568

341

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

DEC 8646 FOUR-BIT TRISTATE BACKPLANE INTERCONNECT
TRANSCEIVER CHIP

BUS 4 PIN 16
BUSJ PIN 14
TRANS
PARITY
PIN 10

PARITY GEN

BUS2 PIN 6

CKT
REC
DATA 1

PIN 3

PIN 7
PIN

TRANS 1
REC
DATA2
TRANS 2
REC
DATA 3
TRANS 3

REC
DATA 4

TRANS4

TRANS
PIN 11 ENABLE L
TRANS
CLK H

PIN 19 --~n

REC
PARITY
CHECK
>-----~

342

PIN 2

PIN 8

PIN 12

PIN 18

PIN 9

VAX-11nflAJ INTEGRATED CIRCUIT DIAGRAMS (CONT)

93406 1024-BIT ROM CHIP

5
6
7
4
ADDRESS

3
2

Al
A2
A3

OUTPUT

A4
As
A5

Cs1 Cs2
CHIP SELECT

343

Vee

GND

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

9403 FIFO BUFFER CHIP

0 05----------~
Parallel Data Inputs
Sana!Oata Input
Parallalloadlnput
Sat1allnputClock(Oparatason

Q.,
CPS1

eG)ITT-

Negat111a·GomgTrans1t1on)

Senallnpu1Enabla(Act111aLOWl

TT5

Transfer to Stack Input (Act1ve LOWI

0E$

Serial Output Enable Input
1Act1vaLOWl

TOS

Transfer Out Serial Input
(Act11111LOWI

Master R~ I Active LOW)

£0

Output Enable (Act111a LOW)

CP$o

Serial Output Clock Input
(Operatesonl\lagat111•·GomgTran11tmn)

SenalDat.IOutput

lnputReg1starFullOutput
(Ac1111aLOWI

OutputR9911terEmptyOutpu1
(Active LOW)

(0ro-------a

344

00c-fi)

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

DC101 ARBITRATOR CHIP, PART 1

---+---

~:::~:}NEXUS

~--+----+---..,.TR SEL 2
- - + - - - + - - - ' -- -

TR#
JUMPER SELECTED

TR SE L 1

LSD 3SD 2SD MSD

BUSTR15L
BUS TR 14 L
BUS TR 13 L
BUSTR12L

BUS TR L

ARB OK L OUTPUT TO
NEXUS LOGIC

OUTPUT TO SBI
(YOUR BUS TR L)

BUSTR11L

INPUT
FROM SBI

BUS TR 10 L

DC101

BUS TR 9 L

E143

BUS TR 8 L
BUS TR 7 L
BUS TR 6 L
BUS TR 5 L
BUS TR 4 L
BUS TR 3 L
BUS TR 2 L
BUS TR 1 L
BUS TR 0 L
R CLK H

14
16

CONTROL {
SIGNALS

T CLK H
SEND TR H
SEND HOLD H

10
IC-DC-101 A

345

~AH
TR SELS L

+VCC

~SH
TRSEL4L

m
=i

~CH

~DH
TR SEL1 L

RCLKL

K""
-R2H

TRSEL2L

..R

...,.

n
%
_:;;
P2 H

,..,,
:D

-f

!
i

"'...>

m
0
s::?

:D
(")

+VCC

::;
52
>
G)
:D

H
H

Pl H

+VCC

....R
0

>
:II

•=t
~

d
:a

BUS TR12 L

•
%

,-------,I

...:IIw

Rl H

~
......
+VCC

<
>

......~
-;:i

z-4

0
:D

~
m

;;
n
c

=t
2
>

n
i

::1

g
w

•VC:C~

RCSTA H
ENDATA H

ENACLK H

-4

VECTOR H

::0
::0

0-E~J----

c"'C

VECRrJSTB H

s--

ENAST H
ENADATA H
BINIT L

:I:

ENBCLK H

::0

§----+--n

-----0BIAKO L

BOIN L

§v--------------==~=----1----+---+---

FNBDATA H

0--

ENBCl_K H

@}---

ROSTB H

§--

-4

ENACLK H

ROS TB H

BIAKI L

----------~ ENAS1 H

------§!BIRO L

--§VECRClSTH fl

0
0

.,,

.,::.

+VCC

::0

0-vcc

-I

(§-GND

DECODER

0
r-

n
:c

=ti

<
)>
~

-..J

-t

m
C>

:::c
)>

-t

BDALl L 03:1-------l----1

I > - - - - - - - - - - - - - - - - < 13 OUTHB L

VECTOR H

vcc

BDAL2 L

ENB H

BDALl L

RXCX H

BDALO L

SEL6 L

BWTBT L

SEL4 L

DC004

BSYNC L

SEL2 L

BDIN L

SELO L
OUTHB L

BRPL Y L

OUTLB L
GND

n
:::c

-t

:::c
)>

(/)

n
0
2

<
>

I... ..
~

~
'"
<
'"
~

2:;

;::r

8
i

-4

"'::DQ

>
-4
"'c

D
::D

c:
=i
c

;;
Q

::D

0-vcc

~GND

I
c:;
i