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EK-RH780-TD-1

March 1979

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Document:	VAX-11/780 RH780 Massbus Adapter Technical Description
Order Number:	EK-RH780-TD
Revision:	1
Pages:	139
Original Filename:

OCR Text

EK-RH780-TD-OO1

RH780 Massbus Adapter
Technical Description

digital equipment corporation • maynard, massachusetts

First Edition, March 1979

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC

PDP
DEC US
UNIBUS

DECsystem-IO
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
IAS

CONTENTS

Page

CHAPTER 1

INTRODUCTION

1.1
1.1.1
1.1. 2
1. 2
1. 2. 1
1. 2. 2
1. 3
1. 3. 1
1. 3. 2
1. 3. 3
1. 3. 4
1. 4
1. 4. 1
1. 4. 2
1. 4. 3
1. 4. 4
1. 5
1. 5. 1
1. 5. 2
1. 5. 3
1. 5. 4

GENERAL
Scope
Related Documentation
MASS STORAGE SUBSYSTEMS
Synchronous Backplane Interconnect
Massbus
MAS SB US ADAPTER
MBA/SBI Interface
MBA Internal Registers
Control Path
Data Path
MBA SBI OPERATIONS
Write to Internal Registers
Write to External Registers
Read Internal Registers
Read External Registers
MASSBUS DATA TRANSFERS
Write to Massbus Device
Write Check Data Transfer
Read From Massbus Device
Data Transfer Rate

CHAPTER 2

MASSBUS AND SYNCHRONOUS BACKPLANE INTERCONNECT

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.4
2.4.1
2.4.2
2.5
2.6

MASSBUS
DATA BUS
Parallel Data Paths
RUN
Occupied (OCC)
End of Block (EBL)
Except i on ( E XC )
Sync Clock (SCLK), Write Clock (WCLK)
CONTROL BUS
Pa r a 11 e 1 Cont r o 1
Drive Select (DS<02:00>)
Controller to Drive {CTOD)
Register Select (RS<04:00>)
Demand (DEM)
Transfer (TRA)
Attention (ATTN)
Initialize (INIT)
FAIL
COMMAND INITIATION
Nondata Transfer Commands
Data Transfer Commands
READING AND WRITING REGISTERS
DATA TRANSFER
iii

(SBI)

1-1
1-1
1-1
1-2
1-2
1-4
1-4
1-'-;

1-5
]-7

1-7
1-8
1-8
1-8
1-9
1-9
1-9
1-10
1-12
1-12
1-12

2-1
2-2

2-2
/-2
2-2
2-2
2-2
2-3
2-3
2-1
2-3
2-3
2-3
2-3
2-3
2-4
2-4

2-5
2-5
2-5
2-5

2-n

2-6

CONTENTS (Cont)
Page
2.7
2.8
2.8.1
2.8.1.1
2.8.1.2
2.8.1.3
2.8.1.4
2.8.2
2.8.3
2.8.4
2.8.4.1
2.8.4.2
2.8.4.3
2.8.4.4
2.8.5
2.8.5.1
2.8.5.2
2.8.5.3
2.8.5.4
2.8.5.5
2.8.6
2.8.6.1
2.8.'5.2
2.8.6.3
2.8.7
2.8.7.1
2.8.7.2
2.8.7.3
2.8.7.4
2.8.7.5
2.8.8
2.8.8.1
2.8.8.2
2.8.8.3

MASSBUS PHYSICAL DESCRIPTION
SYNCHRONOUS BACKPLANE INTERCONNECT DESCRIPTION
Interconnect Synchronization
Derived Time States
Transmit Data
Receive Data
Single Time States
SBI Summary
Arbitration Group Functions and Assignments
Information Transfer Group Description
Parity Field
Tag Field
Identifier Field
Mask Field
Response Group Description
Confirmation Codes
Response Handling
Successive Cycle Confirmation
SBI Sequence Timeouts
Fa u 1 t De t e ct ion
Interrupt Request Group Description
Interrupt Operation
Status Register Alert Flags
Alert Flag Operation
Command Code Description
Read Masked Function
Extended Read Function
Write Masked Function
Extended Write Masked Function
Interlock Function Description
Control Group
DEAD Function
FAIL Function
UNJAM Function

CHAPTER 3

PROGRAMMING DEFINITIONS AND SPECIFICATIONS

3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.h

GENERAL
DEFINITIONS
PROGRAMMING NOTES
INTERRUPT CONDITIONS
TERMINATION OF DATA TRANSFERS
MBA REGISTERS
Configuration Status Register {CRS)
Control Register {CR)
Status Register (SR)
Virtual Address Register (VAR)
Byte Count Register (BCR)
Diagnostic Register (DR)
iv

2-7
2-11
2-11
2-11
2-11
2-11
2-11
2-13
2-16
2-17
2-17
2-18
2-21
2-22
2-23
2-23
2-23
2-24
2-24
2-25
2-25
2-28
2-29
2-29
2-32
2-32
2-33
2-35
2-38
2-42
2-41
2-43
2-43
2-43

3-1
3-1
3-2
3-2
3-3
3-3
3-5
3-8
3-9
3-15
3-16
3-16

CONTENTS

(Cont)

Page

3.6.7
3.6.8
3.6.9
3.7

Selected MAP Register (SMR)
Command/Address Register (CAR)
MAP Registers
DRIVE REGISTER CALCULATIONS

CHAPTER 4

MBA FUNCTIONAL/LOGIC DESCRIPTION

4.1
4.2
4.2.1
4.2.2
4.2.3

GENERAL
MBA/SBI INTERFACE
SBI Decoding and Validating (Overview)
Timing (MSIR)
SB! Control and Data Transceivers (MSIA,
MSIB)
Parity Error Checking (MSIC)
TAG Decoding (MSID)
Address Validation (MSID)
Function Decoding (MSID)
MBA BUSY Generation Logic (MSIE)
Confirmation Logic (MSIJ, MSIM)
Response Generation (MSIM)
Confirmation Check (MSIJ)
Interface Fault Assertion
Request Logic (MSIK)
Timeout Logic (MSIH)
Command/Address Generation (MSIM)
MASK Decoding
Internal Bus and Interrupt Summary Read
Logic
MBA INTERNAL REGISTERS
Internal Bus Receivers
Internal Register Control
Configuration, Control, Status, Diagnostic
and Command/Address Registers
Virtual Address Registers
MAP Registers
Command/Address Generation
Byte Counter Register
Output Data Multiplexers
MBA DATA PATHS
Command Condition (MDPA)
Internal Bus Receivers/Buffers
Data Input Buffer Enable (MDPD)
Silo and Control Logic (MDPF, MDPH)
Data Output Buffer and Control Logic
(MDPJ, MDPM)
Internal Bus Output Multiplexers (MDPR,MDPS)
Massbus Output Multiplexers and
Parity Generator
Write Check Logic

4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.9.1
4.2.9.2
4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
4.2.15
4.3
4.3.1
4.3.2
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.3.4
4.3.4
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8

3-19
3-19
3-19
3-19

4-1
4-1
4-1
4-5
4-5
4-7
4-8
4-8
4-10
4-10
4-11
4-12
4-13
4-13
4-14
4-14
4-16
4-19
4-19
4-21
4-21
4-21
4-21
4-24.
4-24
4-26
4-27
4-29
4-32
4-32
4-34
4-34
4-37
4-39
4-39
4-42
4-42

CONTENTS (Cont)
Page

4.5
4.5.1
4.5.2
4.5.3
4.5.4

MBA CONTROL PATH
Internal Bus Receivers (MCPA)
Data Transfer Control Logic (MCPB)
Massbus Receiver/Drivers
End Data Transfer Logic (MCPA)

4-44
4-44
4-44
4-50
4-51

FIGURES

Figure No.

Title

Page

1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
3-1
3-2
3-3
3-4
3-5
3-6
3-7

Typical Mass Storage Subsystem
MBA Block Diagram
Virtual Address Translation
Massbus Interface
SBI Time and Phase Relationships
Transmit Data Path
Receive Data Path
SBI Configuration
Parity Field Configuration
Command/Address Format
Control Address Space Assignment
Read Data Formats
Write Data Format
Interrupt Summary Formats
Mask Field Format
Fault Status Flags
Fault Timing
Confirmation and Fault Decision Flow
Request Level and Nexus Identification
Interrupt Operation Timing and Flow
Alert Status Bit
SBI Command Codes
Read Masked Function Format
Read Masked Timing Chart
Extended Read Function Format
Extended Read Timing Chart and Flow
Write Masked Function Format
Write Masked Timing Chart and Flow
Extended Write Masked Function Format
Extended Write Masked Timing Chart and Flow
Configuration/Status Register (CSR)
Control Register (CR)
Status Register (SR)
Virtual Address Register (VAR)
Byte Count Register (BAR)
Diagnostic Register (DAR)
MAP Registers

1-3
1-5
1-10
2-1
2-12
2-13
2-13
2-16
2-17
2-18
2-19
2-19
2-20
2-21
2-22
2-26
2-26
2-27
?.-28
2-30
2-31
2-32
2-32
2-34
2-35
2-36
2-38
2-39
2-40
2-41
3-5
3-8
3-10
3-15
3-16
3-17
3-19

FIGURES

(Cont)

Figure No.

Title

Page

4-1

MBA Block Diagram
MBA/SBI Interface
Internal Timing
Parity Check (MSIC)
Tag Decoding (MSID)
Address Validation Simplified Block Diagram
Functioning Decoding {MSID)
MBA BUSY Generation
Response Generation
Confirmation Check
Request Logic (MSIK)
Timeout Logic (MSIH)
Mask Generation (MSIM)
Tag and ID Generation (MSIM)
Mask Decoding
Internal Bus Drivers and Interrupt Summary
Read Data Logic
MBA Internal Registers
Internal Bus Receivers
Internal Register Control
Virtual Address Register
MAP Registers
Command/Address Format
Byte Counter Register
Output Multiplexers and Select/Enable Logic
MBA Data Paths
Internal Bus Receivers/Buffers
Data Input Buffer Enable
MBA Silo
Data Output Buffer and Control Logic
Internal Bus Output Multiplexers
Massbus Output Multiplexers and Parity
Generator
Write Check Logic
MBA Control Paths
Data Transfer Control Logic
Internal Bus Data Register and Massbus Parity
Generator
Massbus Control Path Data Registers and Parity
Check (Received Massbus Data)
End Data Transfer Logic

4-2

4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33

4-34
4-35
4-36
4-37

VII

4-4

4-n
4-7

4-9
4-9
4-10

4-11
4-12
4-lLl
4-15
4-15

4-16
4-18
4-19

4-20
4-22
4-23
4-2~

4-25

4-2t)
4-27

4-28
4-10
4-31
4-3 5
4-36
4-37

4-40
4-41
4-4 3
4-43
4-4 5
4-tl 6

4-48
4-49
4-51

TABLES
Page

Table No.

Title

1-1

Related Documentation
Massbus Signal Cable Designations
SBI Field Summary
Read Data Types
Confirmation Code Definitions
MBA Registers
MBA Base Addresses
Register Byte Offsets
Configuration/Status Register (CSR) Bit
Assignments
Control Register (CR) Bit Assignments
Status Register {SR) Bit Assignments
Diagnostic Register (DR) Bit Assignments
Drive Address Conversion
Internal Bus Output Multiplexer
Data Input Buffer Enable
Function and Direction Select
Massbus Transmit Enable Signals

2-1
2-2

2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4

viii

1-1
2-8

2-14
2-22
2-23
3-4
3-4
3-5
3-6
3-8
3-11

3-17
3-20
4-31
4-36
4-47
4-50

CHAPTER 1
INTRODUCTION
1.1

GENERAL

The RH780 Massbus Adapter (MBA) is the interface between the
Synchronous Backplane Interconnect (SBI) and Massbus storage
devices (disk and tape). The RH78QJ is used with the VAX-11/780
processor to transfer data between mass storage devices and main
memory. The processor can accommodate up to seven MBAs. Each MBA
can be used with up to eight drives.
1.1.1

Scope

This manual is intended to be used as a training resource and as a
field reference guide for the RH780 MBA.
1.1.2

Related Documentation (Cont)

Title

Document Number

VAX-11/780 System
Installation Manual*

EK-SI780-IN

VAX-11/780 Diagnostic
System User's Guide*

EK-DS780-UG

TE16/TE10W/TE10N
DECmagtape Transport
Maintenance Manual+

EK-TE16-MM·

TE16/TE10W/TE10N
DECmagtape Transport
User Manual*

EK-TE16-0P

TU45A Magnetic Tape
Subsystem Maintenance Manual+

EK-TU45A-TM·

TM03 Magnetic Tape
Formatter Technical Manual+

EK-TM03-TM

TM03 Magnetic Tape
Formatter User's Manual*

EK-TM03-0P

RM03 Disk Drive
Technical Manual+

ER-RM03-TM

RM03 Disk Drive
Maintenance Print Set+

ER-RM03-MP

* Hard copy only.
+ Microfiche and hard copy.
1.2
MASS STORAGE SUBSYSTEMS
Figure 1-1 illustrates a typical mass storage subsystem. It is
beyond the scope of this manual to discuss, in detail, the various
configurations (tape and disk) that can be used with the MBA to
store data. Throughout this manual a Massbus device is defined as
a mass storage device (drive) and its associated Drive Control
Log i c ( DC L ) o r format t in g i n t e r faces . An exp 1 an at ion of the bas i c
components in the subsystem is presented in subsequent paragraphs.
1.2.1
Synchronous Backplane Interconnect (SBI)
The SBI is a bidirectional information path for data exchanges
between the central processor (CPU), memory, and adapters of the
VAX-11/780 system. The SBI provides checked, parallel information
exchanges synchronous with a common system clock.

1-2

MEMORY

CPU

SYNCHRONOUS BACKPLANE INTERCONNECT

MASSBUS
ADAPTER

MASSBUS

DRIVE
0

DRIVE *

*NOTE: UP TO EIGHT
DRIVES MAY BE
USED PER MBA
MA-1735

Figure 1-1

Typical Mass Storage Subsystem

A communications protocol allows the information path to be time
multiplexed such that several data exchanges can be in progress
simultaneously. In each clock period (or cycle) the next cycle's
interconnection arbitration, or information exchange, and transfer
confirmation about information exchange two cycles ago can occur
in parallel.
Every 200 ns SBI signals are clocked into data latches. All
checking and subsequent decision making is based on these latched
signals. Error checking logic in every SBI device detects and
reports single bit failures in the information path.

1-3

The SBI has the following characteristics:
Distributed arbitration
200 ns bus cycle time
32-bit data width
28 bits of physical address space
13.3 megabyte maximum data transfer rate
The following
operations:

terms

are

defined

for

SBI-specific

units

and

Nexus -- a physical connection to the SBI capable of any
or all of the functions described in b -- e.

Commander
information.

Responder -- a nexus that recognizes command and address
information which is directed to it and requires a
response.

Transmitter -- a nexus that drives the signal lines.

Receiver
lines.

a nexus that transmits command and address

a nexus that

sampl~s

and examines the signal

1.2.2
Massbus
In the VAX-11/780 system the Massbus connects the drive to the
MBA. The Massbus is composed of two separate, independent buses:
control bus and data bus. These independent buses allow for the
exchange of control information and data between the MBA and its
drives.

The data bus provides a bidirectional, parallel data path (16 bits
plus 1 parity bit) between the MBA and its drives. Data is
transferred synchronously, using a clock generated in the drive.
Only one drive can transfer data at any one time, with the data
rate being drive dependent, and the data bus dedicated to a single
d r i v e f o r th e d u r a t i o n o f a d a t a t r a n s f e r o p e r a t i o n • Th e
asynchronous control bus provides the parallel control and status
path ( 16 bi ts p 1 us 1 par i t y bi t ) • The cont r o 1 bus i s used to read
and write registers within the drives and to command the drives to
transfer data over the data bus.
1.3
MASSBUS ADAPTER
The MBA is the interface between the SBI and the high-speed
Massbus device (disk and tape). It consists of an SB I/MBA
interface board, an internal registers board, a control path
board, and a data path board. Figure 1-2 is a simplified block
diagram of the MBA. A tristate internal bus connects the SBI
interface to the other boards and provides for the passage of data
between them.

1-4

fMASBus ADAPTER
CONTROL
PATH

Cf)

CJ)

INTERFACE

DATA
PATH

CJ)
Cf)

<(
~

I-

INTERNAL
REGISTERS

- - - - - - - _J
Figure 1-2

MA-1736

MBA Block Diagram

The MBA accepts and executes commands from the CPU and reports the
necessary status changes and fault conditions to the CPU. The MBA
will accept a CPU command to read or write a register within the
MBA or within a drive. The MBA always monitors the data written to
drive registers, thereby knowing when to begin a data transfer and
what kind of a transfer it is.
Special diagnostic features are built into the hardware to allow
on-line diagnosis of the MBA and Massbus drives. The following are
features of the MBA.
1.

The MBA handles a Massbus drive with
transfer speed of 1 us per 16 bits.

The Massbus data path is 16-bits wide;
handled by the MBA.

A silo
(32-byte deep data buffer)
smoothes out
transfers between the SBI and the Massbus drives.

The MBA can be exercised, through
with no drives on the Massbus.

1-5

maximum

data

18-bit data is not

diagnostic

data

features,

1.3.1
MBA/SBI Interface
The MBA examines the information on the SBI for every SBI bus
cycle. It checks the parity of the data, decides if the MBA is the
receiving nexus, and acts accordingly. The SB I interface board
contains logic to accomplish preliminary SBI command/address
decoding and generation of internal timing signals from the timing
sources on the SBI.
1.3.2
MBA Internal Registers
There are two sets of registers in the MBA address space: internal
and ex t e r n a 1 . The MB A i n tern a 1 reg i st er s a r e the reg i st e rs th a t
are physically located in the MBA. The external registers are
located in the Massbus drives and are drive dependent.
There are eight internal registers and a 256 X 3 2-bi t RAM. The
primary function of the internal registers is to control the MBA
and monitor operating status conditions. The internal registers
also control certain phases of data transfers between the SBI and
the Massbus device, such as maintaining a byte count to ensure
that all of the data to be transferred has been accounted for, and
converting virtual addresses to physical addresses to read or
write data in memory.
The eight internal registers are listed as follows:
RS
RS
RS
RS
RS
RS
RS
RS

= 00
= 01
= 02
= 03
= 0, 4
= 05
= 06
07

MBA Configuration/Status Register (CSR)
MBA Control Register (CR)
MBA Status Register (SR)
MBA Virtual Address Register (VAR)
MBA Byte Count Register (BCR)
MBA Diagnostic Register (DR)
MBA Selected Map Register (SMR)
MBA Command Address Register (CAR)
NOTE
Registers 06 and 07 are read-only
registers and are valid only during data
transfers.

The MBA contains a 255 X 32-bit RAM (bits 21--30 read as 0) that
maps virtual addresses from the virtual address register into SBI
physical addresses. The mapping registers allow transfers to or
from contiguous or noncontiguous physical memory.

1-6

1.3.3
Control Path
The control path handles the transfer of control data to and from
the Massbus devices. It contains logic to select the Massbus
device and device register and to perform the register transfer
and determine the data transfer function (if any) to be performed
(read, write, write check). The control path also coordinates the
control data function with other MBA and SB! activity.
1.3.4
Data Path
The data path controls the manner in which data is transferred to
and from the Massbus device and the SBI. These circuits divide the
32-bit SB! data word into 16-bit (2 bytes) segments required as
input by the Massbus and its devices when per forming a write
function. When performing ~ read from a Massbus device, the data
path assembles the two 8-bi t bytes from the Massbus into the
32-bi t SBI format. A silo and I/O data buffer provide the means
for smoothing the data transfer rate. The data path also contains
a write check circuit that allows the user to verify the accuracy
of a preceding data transfer function.

1-7

1.4
MBA SBI OPERATIONS
An SB I wr i t e ope rat i on i s spec i f i e d a s a d a ta t rans f e r f r om the
SBI to the MBA or Massbus device. This data transfer requires two
SBI cycles. The first cycle contains the command/address; the
second cycle contains the data word.
An SBI read operation is specified as a data transfer from the MBA
or Massbus device to the SBI. An SBI read operation requires two
SBI cycles. The first cycle is a command/address to the MBA
specifying a read operation. The MBA then accesses the requested
register contents. Several SBI cycles later, the MBA will
arbitrate for use of the SBI and send the requested data back to
the CPU.
The MBA only accepts aligned longword (32 bits) register reads and
writes. The following paragraphs provide a basic description of
the various functions the MBA supports. These functions will be
described in more detail later in this manual.

1.4.1
Write to Internal Registers
SBI data is constantly checked by the MBA. When a valid
command/address (one whose address is within the range recognized
by the MB A) i s decoded , i t i s 1 at ch e d i n the SB I /MB A i n t e r fa c e
transceivers. The MBA decodes a section of the address range which
selects registers internal to the MBA. If the function to be
performed is a write, and the MBA's SBI interface is not busy, the
command will be accepted. The selected register address is latched
in the internal register board. The next SBI cycle will contain
the data to be written. It is then passed through the internal bus
to the internal register board and written into the selected
register or map. Certain registers can be written when the MBA is
processing a data transfer; however, most registers cannot. Any
attempt to write to a register that is not allowed will set the
Programming Error {PGE) bit in the status register. The MBA will
not modify the intended register and the data transfer in progress
will continue.
A confirmation signal informs the transmitting device that
command/address has been decoded and validated and the data
been received correctly.

the
has

1.4.2
Write To External Registers
Receipt and initial processing of the command/address for an
external write function is the same as that for a write to
internal registers, except the address specifies a register within
a Massbus device. The MBA will not accept another SBI command
until the write to external register function is complete. All
command/ address and data words a re applied to the inte rna 1 bus
drivers as they are latched in the SBI interface transceivers. The
address is made available to the internal registers, control
paths, and data paths via the internal bus. Following receipt of
the command/address (assuming the decoding and validation process
is performed satisfactorily), the command/address is loaded into
the control path internal bus receivers, then latched into the
1-8

control path address storage registers and applied to the Massbus
cont r o 1 path add res s 1 i n es • Data i s 1 o a de d i n to the cont r o l path
lines. When the proper protocol between the MBA and the drive is
exchanged, the drive has accepted the data. The MBA busy logic is
then cleared and the write to external register function is
completed. The MBA is now ready to accept another SBI command.
1.4.3
Read Internal Register
The command/address, after decoding and validation, is loaded into
the MBA to select the internal register or map from which data is
to be read. The decoding process instructs the MBA to retrieve the
addressed data word and transfer it to the specified destination.
The MBA then saves the destination information, issues a
comand/address acknowledge to the SBI, and accesses the requested
register's content. Before the MBA can transfer data to the
re q u es t er , i t must f i rs t a r bi tr ate f o r cont r o 1 of the SB I • On c e
the MBA gains control of the SBI, data is then transferred to its
destination.
1.4.4
Read External Registers
If the command/address received from the SBI is one that selects a
r eg i s t e r i n a d r iv e , the add res s i s sent to the cont r o 1 path ,
which selects the device and the register withi~ the device from
wh i ch data i s to be read • Dur in g th i s t i me a con f i rm at ion s i g n a 1
is sent to the SBI indicating that the command/address has been
received by the MBA. After the proper Massbus protocol has taken
place, the requested data is strobed into the Massbus control path
receivers. Data is then transfer red to the in terna 1 bus and the
MBA will arbitrate for control of the SBI. When the MBA gains
control of the SBI, the requested data can be transferred to its
specified destination.

1.5
MASSBUS DATA TRANSFERS
In order to initiate a data transfer, specifi9 registers within
the MBA and the selected drive must be loaded (the programmer's
handbook provides further details). The last register to be loaded
within a device is the control register. The loading of a drive's
control register with a valid command will cause both the drive
and the MBA to prepare for a transfer. The drive will seize the
data bus for the duration of the transfer and the MBA will prepare
to move data between the device and memory. The MBA buffers the
data and transfers eight bytes at a time to and from memory (this
eight byte quantity is a quadword). Three SBI cycles are needed to
transfer a quadword: one for the command/address, one for the
first four bytes of data, and one for the last four bytes of data
of the quadword. Once the specified number of bytes have been
tr an sf er red, the MB~?\ informs the drive that the transfer has
terminated. At this time the drive disconnects from the data bus
and the MBA may interrupt the CPU to inform it that the transfer
has been completed.

1-9

1.5.1
Write To Massbus Device
The MBA constantly monitors data sent to the drives via the
Massbus control path. If the MBA sees a write command to a drive,
it will initialize itself in preparation for the transfer (data
path c 1 eared ) • The v i rt u a 1 address supp 1 i e d by the program i s
translated, via the MAPs, into a physical address. Virtual
addressing makes data storage appear as if all of the information
transferred from memory is stored in successive fashion
(contiguous pages).
Virtual address translation is transparent to the user and takes
place under system control. Figure 1-3 illustrates the virtual
address translation process.

VIRTUAL ADDRESS

918

17l 16

L31

MAP POINTER

3i 2

l QUADWORD I

1 0~
BYTE

J
MAP REGISTERS

311
~

}

120
RESERVED ALL O's

DIRECT
TRANSFER

PHYSICAL PAGE ADDRESS
DIRECT
TRANSFER

LVALID·BIT

256
SBI COMMAND/ADDRESS

•

l 31130129128127

[1lol I1J
~

PHYSICAL PAGE ADDRESS

116

QUAD WORD

11 OJ

I 0]

INDICATES EXTENDED FUNCTION
INDICATES THE FUNCTION IS NOT INTERLOCKED
SPECIFIES READ OR WRITE
MA-1737

Figure 1-3

Virtual Address Translation

1-10

Bits 9 through 16 of the virtual address specify one of 25~ MAP
registers in the MBA. The MAP register contains the physical page
address of the data and a valid bit (bit 31) that indicates the
integrity of the information in this register. The valid bit must
be set in order to use this register. Bi ts 3 through 8 of the
virtual address specify the address of the quadword in the
physical memory page pointed to by the MAP register. This value is
directly transferred to bits 1 through 6 of the physical address.
Bits 0 through 3 of the virtual address specify the next byte of
the quadword to be loaded into or from the internal silo.
Virtual address translation is checked to ensure that map
information is valid and that there are no parity errors. Invalid
map information or parity errors will cause the transfer to be
aborted.
Once the MBA sees a write command issued to the control regist~r
of a drive, it will clear its data path and begin prefetching the
data from memory. The prefetched data is then loaded into the
MBA's silo.
The MBA requests data by sending a command/address to memory
instructing it to transfer a quadword (eight bytes) from the
specified location to the MBA. Memory will respond to the
command/address by issuing one of four confirmation outputs.
No Response (NR)

Command/address
will
be
retransmitted to memory until an MBA
timeout occurs.

Busy ( BSY)

Command/address
will
be
retransmitted to memory until ACK is
received.

Error

Transfer aborted.

(ERR)

Acknowledge (ACK)

Indicates memory has received
command/address correctly.

the

When memory has accessed the requested data, arbitrated, and
obtained the SBI, the data will be transferred to the MBA with the
proper identification and status codes. The MBA will then transfer
the data through its silo onto the Massbus (two bytes at a time)
and begin another SBI transfer to obtain the next eight bytes of
data from memory. Eventually the byte counter within the MBA will
go to zero and the transfer will be complete.

1-11

1.5.2
Write Check Data Transfer
The write check function is used to verify the integrity of data
that has been written to a drive. During a write check, the data
from the drive is compared with the data in memory. On the MBA,
the write check function is essentially the same as a write
function, except data is clocked into a write check buffer instead
of the Massbus drivers. This is then compared with the Ma ssbus
data received from the drive. If a mismatch occurs, an error bit
is set and the write check function will be aborted.

1.5.3
Read From Massbus Device
The command specifying the initiation of a read from a Massbus
device is processed in the same manner as described in Paragraph
1 • 5 • 1 • I f the co mm and/ add res s i s processed sat i s facto r i l y , the
data path circuit will be cleared and data will be read from a
Massbus device. Device selection and the location within the
device from which data is to be read is specified by previous
writes to the MBA and the drive. Data from the Massbus will then
be loaded in to the Massbus input data buff er s and a silo input
operation will be initiated. Data from the Massbus data input
buffers is loaded into the silo one byte at a time. As data is
being loaded into the silo from the Massbus, other data may be
transferred from the silo to the output buffer registers. After
the eight bytes are loaded into the output buffer register, the
MBA will initiate a write to memory operation. Virtual addresses
are translated into physical address as described in Paragraph
1.5.1. When the proper confirmation signals are received, the
output buffer is cleared and more data will be loaded to be
transferred to memory. Once the byte count register goes to 0, the
data transfer operation is terminated and the MBA will be ready to
accept the next data transfer command.
1.5.4
Data Transfer Rate
The data transfer rate from the drive is determined by a clock in
the Massbus device. The memory transfer rate depends on cycle
arbitration time and memory cycle time. The MBA can handle
transfer rates of up to 1 us/word.
MBA Specifications
Packaging

Four extended hex board
backplane plus one paddle
for cable connection

Power Requirements

+5 Vdc, 35 A, 175 W
-5 Vdc, 1 A, 5 W
Total wattage < 180 W

Operating Configuration

The minimum operating configuration
consists of a CPU, a memory, and at
least one Massbus device. (A special
diagnostic feature enables the Massbus
to be checked with no Massbus device.)

1-12

slots of
card slot

CHAPTER 2
MASSBUS AND SYNCHRONOUS BACKPLANE INTERCONNECT
2.1

MASSBUS

The Massbus provides the interface between the MBA and the Massbus
drives (Figure 2-1). The total external Massbus cable can be up to
49 m (160 ft) in length; up to eight drives can be connected in a
daisy-chain configuration. The Massbus consists of two sections: a
data bus and a control bus. These buses are described in the
following paragraphs.

K
--

DATA BUS
D <17:00> {DATA)
DPA (DATA BUS PARITY)

RUN (START, CONTINUE, STOP)

~
-~

--.....---

OCC (OCCUPIED)
EBL (END OF BLOCK)
EXC (EXCEPTION)
SCLK (SYNC CLOCK)
WCLK (WRITE CLOCK)

>
__.,

MBA

i<;

CONTROL BUS
C <15:00> (CONTROL STATUS)

CPA (CONTROL BUS PARITY)

__.,
~

DS <02:00> DRIVE SELECT
CTOD (TRANSFER DIRECTION)

MASSBUS
DRIVE

>
--

RS <D4:00> REGISTER SELECT : )
DEM (DEMAND)

......
~

TRA (TRANSFER)

...-

ATTN (ATTENTION)
INIT (INITIALIZE)
~

FAIL

__.,

TK-1109

Figure 2-1

Massbus Interface
2-1

2.2
DATA BUS
The data bus section of the Massbus consists of a 17-bit (16 data
bi ts pl us parity bit) parallel data path and six control 1 ines
( Fig u re 2 -1 ) • The cont r o 1 1 in es a re des c r i bed in the following
paragraphs.
2.2.1
Parallel Data Paths
The parallel data path consists of an 18-bit plus parity bus. The
data path is bidirectional and employs odd parity. Data is
transmitted synchronously, using a clock generated in the drive.
The MB A on 1 y transfer s 16 bi ts at a t i me ; th us , the d r iv e must
have its 16-bit format bit set in the drive control logic. Bits 17
and 18 are always unasserted.

2.2.2

RUN

After a data transfer command has been written into the control
register of a drive, the drive connects to the data bus. The MBA
asserts the RUN line to initiate the function. At the end of each
sector, on the trailing edge of the EBL (End of Block) pulse, RUN
is strobed by the drive. If it is still asserted, the function
continues for the next sector; if negated, the function is
terminated.
2.2.3
Occupied (OCC)
This signal is generated by the drive to indicate "data bus busy."
As soon as a valid data transfer command is written into a drive,
the drive asserts OCC. Various errors can prevent a drive from
executing a command. The controller wi 11 timeout in these cases,
due to no assertion of OCC or of SCLK (Sync Clock), and the MXF
(Missed Transfer) error will be set in the controller. OCC is
negated at the trailing edge of the last EBL pulse of a transfer.
2.2.4
End of Block (EBL)
This signal is asserted by the drive for 2 us at the end of each
sec to r ( a ft e r the 1 as t SC L K p ul s e) • Fo r cert a i n er r o r co nd i t i on s ,
where it is necessary to terminate operations immediately, EBL is
asserted prior to the normal time for the last SCLK. In this case,
the data transfer is terminated prior to the end of the sector.
2.2.5
Exception (EXC)
This signal is asserted by the drive or the MBA when an abnormal
co nd i t ion o cc u rs d u r i ng a data trans fer • The d r iv e asserts th i s
signal to indicate an error during a data transfer command (read,
write, or write check). EXC is asserted at, or prior to, assertion
of EBL and is negated at the negation of EBL.

2-2

2.2.6
Sync clock (SCLK), Write Clock (WCLK)
These signals are the timing signals used to control the strobing
o f the data in the cont r o 11 er and Io r the d r iv e • Dur i ng a read
operation, the MBA strobes the data lines on the negation of SCLK
and the drive changes the data on the assertion of SCLK. During a
write operation, the controller receives an SCLK and echoes it
back to the drive as WCLK. On the assert ion of WCLK, the drive
strobes the data lines; on the negation of WCLK, the controller
changes the data on the data lines.
2.3
CONTROL BUS
The control bus section of the Massbus consists of a 17-bit (16
bits plus parity) parallel control and status data path and 14
control lines (Figure 2-1), which are described in the following
paragraphs.

2.3.1
Parallel Control
The parallel control path consists of a 15-bit parallel data path
designated C<l5:00> and an associated parity bit (CPA). The
control lines are bidirectional and employ odd parity.
2.3.2
Drive Select (DS<02:0B>)
These three lines transmit a 3-bit binary code from the MBA to
select a particular drive. The drive responds when the selected
(unit) number in the drive corresponds to the transmitted binary
code.
2.3.3
Controller to Drive (CTOD)
This signal is generated by the MBA and indicates the direction in
which control and status information is to be transferred. For a
cont r o 11 er to d r iv e trans f e r , the cont r o 11 e r asserts CT OD • Fo r a
drive to controller transfer, the controller negates this signal.
2.3.4
Register Select (RS<04:0B>)
These five lines transmit a 5-bit binary code from the controller
to the s e 1 e ct e d d r iv e . The binary cod e s e 1 e ct s one o f the d r iv e
registers.
2.3.5
Demand (DEM)
This signal is asserted by the controller to indicate that a
transfer is to take place on the control bus. For an MBA to drive
transfer, DEM is asserted by the MBA when data is present and
settled on the control bus. For a drive to controller transfer,
DEM is asserted by the MBA to request data and is negated when the
data has been strobed off the control bus. In both cases, the RS,
DS, and CTOD 1 ines are generated and allowed to settle before
assertion of DEM.
2.3.6
Transfer (TRA)
This signal is asserted by the selected drive in response to DEM.
For an MBA to drive transfer, TRA is asserted after the data has
been strobed and is negated after DEM is negated. For a drive to
controller transfer, TRA is asserted after the data has been gated
onto the bus and negated after the negation of DEM is received.
2-3

2.3.7
Attention (ATTN)
This line is shared by all eight drives attached to an MBA; it may
be asserted by any drive as a result of an abnormal condition or
status change in the drive. An At tent ion Active (ATA) stat us bit
in each drive is set whenever that drive is asserting the ATTN
line. ATTN can be asserted due to any of the following conditions.
1.

An error occurring while no data transfer is taking place
(asserted immediately).

Upon completion of a data transfer command if an error
occurred during the data transfer (asserted at the end of
the data transfer).

Upon completion of a mechanical motion
recalibrate, etc.) or a search command.

As a result of the Medium On Line (MOL) bit changing
states (except in the unload operation). In the dual MBA
configuration, a change in state of MOL will cause the
assertion of ATTN to both MBAs.

command

(seek,

The ATA bit in a drive can be cleared by the following actions.
1.

Asserting INIT on the Massbus (affects all eight drives).

2•

Wr i t i ng a l i n to the a t tent i on summary reg i st e r ( in the
bi t po s i t ion f o r th i s d r iv e) • Thi s c 1 ea rs the AT A bi t ;
however, it does not clear the error.

3•

Wr i t in g a v a 1 i d co mm and ( wi th the GO bi t ass e rte d ) into
the control and status register if no error occurs. Note
that clearing the l~.. TA bit of one drive does not always
cause the ATTN line to be negated, because other drives
may also be asserting the line.

NOTE
There are three cases in which ATA is
not reset when a command is written into
the control and status register (with
the GO bit set): 1) if there is a
control bus parity error in the write,
2) if an error was previously set, or 3)
if an Illegal Function (ILF) code is
written.
2.3.8
Initialize (INIT)
This signal is asserted by the MBA to perform a system reset of
all drives. It is asserted when a 1 is written into the INIT bit
(bit 01 of MBA CR). When a drive receives the INIT pulse, it
immediately aborts the execution of any current command and
performs all actions described for the drive clear command.

2-4

NOTE
In the dual-MBA configuration, a drive
will honor an INIT pulse only from the
MBA that has seized the drive, or from
either controller if the drive is in the
unseized state.
FAIL
2.3.9
When asserted, this signal indicates that a power-fail condition
has occurred in the MBA or the MBA is in the maintenance mode.
While FAIL is asserted, the drive inhibits reception of the INIT
and DEM signals at the drive.
2.4
COMMAND INITIATION
To initiate a command in a drive via the Massbus, the MBA (or the
CPU via the MBA) writes a word into the control register. The
function code and GO bit are transferred to the selected drive. If
the co mm and spec i f i e d i s v a 1 i d and the G O bi t i s a s s er t e d , the
selected drive executes the command.
Commands are of two types: nondata transfer commands (su~h as
drive clear, seek, etc.) and data transfer commands (such as read,
write, and write check) . The command function code bi ts (05--00,
including GO in the control register)
are 01--37 for nondata
transfer commands and 29--3F for data transfer commands (not all
are valid functions.)
2.4.1
Nondata Transfer Commands
Nondata transfer commands only affect the state of the drive. The
MBA me rely writes the command word (with GO bit set) into the
drive's control register. At the completion of the command
execution, the drive typically asserts the ATTN line to signal its
completion.
If the nondata transfer command code written into the drive is not
recognized by the drive as a valid command, the drive will
immediately signal an error by asserting the ATTN line. The ILF
error is set.
2.4.2
Data Transfer Commands
When any data transfer command code (with the GO bit set) is
written into the drive's control register, the MB~. expects data
transfer on the data bus to beg in soon thereafter. The MBA sets
its DT BUSY bit as soon as the data transfer command code is
written into a drive. The drive normally responds by asserting the
ace line. The MBA asserts RUN and then data is transferred to or
from the specified drive, after the proper address (sector, track,
cylinder) is found.
If an error occurs in a drive during a data transfer command, the
drive asserts the EXC line. This line remains asserted until the
trailing edge of the last EBL pulse. The MBA always negates the

2-5

RUN line when it detects EXC asserted, so that the data transfer
is terminated at the end of the sector in which the error was
signaled.

2.5
READING AND WRITING REGISTERS
The process of reading or writing drive registers is accomplished
via the asynchronous (control bus) portion of the Massbus (Figure
2-1). The MBA initiates the action by selecting a drive DS<02:00>,
selecting a register RS<04: 00> in that drive, selecting a
direction of transfer (CTOD), and either reading or writing the
register via the 17 bidirectional control lines (C<l5:00> and
CPA). After a deskew delay to allow the control lines to
stabilize, the MBA asserts DEM. The drive, upon receiving the DEM
assertion, checks the CTOD line to ascertain whether a read or
write is to occur.
If a register read operation is specified, the drive will gate the
contents of the specified register onto the control bus and issue
TRA. When the MBA receives TRA, it will gate the control lines
onto the SB!. After a deskew delay, the MBA negates DEM. The
negation of DEM causes TRA to be negated and completes the
ope rat ion • The MBA wi 11 then a r bi tr ate for the SB I and trans f e r
the Massbus data to its destination.
NOTE
Since Massbus drive registers are 16
bi ts wide, the MBA appends bi ts 31--16
of its status register to create the
longword to be sent to the requester.
If a register write operation is specified, the MBA gates the
cont r o 1 data onto the cont r o 1 bus when i t i s sues DEM • Th e d r i v e
will transfer the data from the control bus into the specified
drive register and assert TRA, which causes DEM to be negated. The
negation of DEM causes TRA to be negated to complete the
operation.
The Massbus structure allows a register read operation while a
data transfer (on the asynchronous data bus) is taking place. Any
attempt by the MBA to write a register in a drive performing a
data transfer operation (except for the maintenance and attention
summary registers) will cause the drive to set the Register
Modification Refused (RMR) error bit.
2.6
DATA TRANSFER
Before a data transfer takes place, the selected unit, desired
sector/track address, cylinder address, bus address, and word
count are specified by the program. The program then transfers the
read or write data transfer command (with the GO bit asserted) to
the control register. Upon receipt of the data transfer command,
the drive will assert OCC, indicating that the data bus is busy.
The MBA logical 1 y connects to the Massbus data bus by asserting
RUN and then wa i t s f o r SC L K p u 1 se s f r om the d r i v e • Fo r a wr i t e

2-6

data transfer, each WCLK pulse causes a word to be written into a
data register in the drive logic; for a read data transfer, each
SCLK pulse causes a word to be transferred to the Massbus. When a
sector of words has been written onto or read from the disk, the
disk sends an EBL pulse to the MBA. If the RUN line is still
asserted at this time, the next sector of data words is
transferred. If the RUN line is negated, the data transfer is
terminated.
2.7
MASSBUS PHYSICAL DESCRIPTION
The Massbus consists of 5 6 signal 1 ines, including· data, contra 1,
status, and parity. These signal lines are routed externally to
the cabinet that contains the MBA(s) via three BC06-R Massbus
cables.
At the cabinet (containing the first MBA), the BC06-R cable plugs
into the AD-7015145 connector panel, which is mounted at the lower
rear of the cabinet. This connector panel has cutouts for four
receptacle housing assemblies to accommodate up to four MBAs and
associated cabling. The other side of the receptacle housing
assembly accepts three BC06-S round Massbus cables. To accommodate
additional MBAs, the BC06-R cables plug into the 7013678 cabinet
to cabinet connector panel, which is mounted between the cabinet
verticals on the right end of the cabinet.
Table 2-1 lists
assignments.

the

Massbus

signals

2-7

and

their

associated

Table 2-1

Pin*

Cable
Mass bus
Cable A

Massbus Signal Cable Designations

A
B

c
D
E
F
H

K
L

M
N
p
R

u
v

x
y
z
AA
BB

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
15
17
18
19
20
21
22
23
24

DD
EE

25
26
27

KK
LL
MM
NN

31
32
33
34
35
36
37
38
39
40

RR
SS
TT

uu
vv

Polarity

Designation

+
+
+
+

M.'l\SS D00
MASS D01
MASS D02
MASS D03

+
+
+
+

MASS D04

+
+
+
+
+
+
+
-

MASS C02

MASS RS4

MASS D05
MASS C00
MASS C01

+
+
+
+
-

MASS C03
MASS C04
MASS C05
MASS SCLK
M}\SS RSJ
MASS ATTN

MASS CTOD
MASS WCLK
MASS RUN
SPARE
GND

2-8

Table 2-1

Massbus Signal Cable Designations (Cont)

Cable
Massbus
Cable B

Pin*

Polarity

Designation

MASS

MASS D07

D
E

3
4
5

+
+

MASS D08

".)

+
+

MASS D09

MASS Dl0

+
+

MASS Dll

H
J

9
10
11
12
13
14
15

L
M
N
p

v
w

x
y

z
AA
BB

DD
EE

FF
HH
JJ

KK
LL
MM

NN
pp

RR
SS
TT

uu
vv

D0~

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
35
37
38
39

MASS C06

+
+

MASS C07

MASS C08

+
+

MASS C09

MASS Cl0

MASS Cll

MASS EXC

+
+

MASS RS0

MASS EBL

MASS RSl

MASS RS2

MASS INIT

+
-

MASS SPl
SPARE
GND

2-9

Table 2-1

Massbus Signal Cable Designations (Cont)

Cable
Mass bus
Cable C

Pin*
A

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

c
D
E
F

H
J

K
L
M
N
p

x
y

z
AA

cc
DD
EE
FF
HH
JJ

KK
LL

MM
NN
pp

RR
SS
TT

Polarity

Designation

+
+
+
+
+
+
+
+
-

MASS Dl2

+
+
+
+

MASS Dl3
MASS Dl4
MASS Dl5
MASS Dl6
MASS Dl7
MASS DPA
MASS Cl2
MASS Cl3
MASS Cl4
MASS Cl5
MASS CPA

occ

+
+
+

MASS

+
+
+
+
-

MASS DSl

MASS DS0
MASS TRA

MASS DS2
MASS DEM
MASS SP2
Ml\ SS

FAIL

GND

* Alternate pin designation schemes
NOTE
Massbus cables are to be
markings on the cable.

2-10

installed per

2.8
SYNCHRONOUS BACKPLANE INTERCONNECT DESCRIPTION
The
SBI
is
the
backplane
of
the
VAX-11/780
system.
It
interconnects the CPU with the memory system and all adapters in
the system. The following paragraphs describe all interconnect
lines and their associated communication protocol.
2.8.1
Interconnect Synchronization
Six control group lines are clock signals that are used as a
universal time base for all nexus connected to the SB I. Al 1 SB I
clock signals are generated on the CPU clock module and provide a
200 ns clock period.
The clock signals, in conjunction with the standard nexus clock
logic, provide the derived clocks within an attached nexus to
synchronize SB I activity. Two clock signals (TPH and TPL) produce
the ba s i c nexus t i me states • The rem a i n in g four , (PC L KH, PC LKL ,
PDCLKH, and PDCLKL) are phased clocks and help compensate for the
clock
distribution
skew
due
to
cable,
backplane,
and
driver/receiver propagation delays.
2. 8 .1.1 Derived Time States
The derived clocks (within the
nexus) define four, 50 ns (nominal) time states in one clock
period.
The time states
(T0, Tl, T2, and T3) determine the
transmit, propagate, and receive times on the SBI, with T0
representing the start of a particular clock period. Figure 2-2
illustrates the phase and timing relationships required to
generate the individual derived time states. Note that T0 internal
to the CPU (CPT0) is not the same as SBI T0. CPT0 corresponds to
SBI Tl. All nexus need a minimum of T0 and T2 for SBI transmit and
receive functions.
2.8.1.2 Transmit Data
Information to be transmitted is
asserted on the SBI at T0. Immediately prior to TQJ a transmitting
nexus enables its transmit enable inputs to the SBI transceivers.
Figure 2-3 is a basic block diagram for one SBI information path
line.
2.8.1.3 Receive Data -- In the case of receive data, the nexus
receiver latches are opened at T 2 and latched at T 3. Figure 2-4
shows the basic one-line receiver latch logic. Note that the
information may be considered undefined between T2 and T3; only
after T3 is information considered valid.
Nexus checking,
decoding, and subsequent decision making are then based on these
latched signals.
2.8.1.4 Single Time States
In single time states, the time
between any T0-Tl, Tl-T2, T2-T3, and T3-T0 may vary from 50 ns
(nominal) to an indefinitely long period of time. SB! operation
and protocol will proceed normally. Nexus that implement the SB!
timeout functions do so by counting SBI cycles. Memory nexus
operation must be normal even though the timing may be different.
Nexus that derive timing from an external source (e.g., a mass
storage device)
set data late and overrun error bits as
appropriate. However, the SBI operation of these nexus remains
normal.
2-11

TPH

TPL

PCLKH

==t

100 NS

I
I
I
f.---200 NSEC~
I
I___
PDCLKH _ - - 1
PCLKL - ,_ _ _ _

PDCLKL

TPL

PCLKL

1___

: TRANSMITTER NEXUS
ENABLES SBI.
'
DRIVERS

TO (DERIVED)

TPH

PDCLKL

Tl (DERIVED)

----

TPL

PCLKH

j
:

T2 (DERIVED)

: ALL NEXUS OPEN

r---7i""" RECEIVER
I / I LATCHES

-----

TPH

PDCLKH

T3 (DERIVED)

n ----

ALL NEXUS CLOCK
~RECEIVER
V I LATCHES

-------

TK-0165

Figure 2-2

SBI Time and Phase Relationships
2-12

TRANSMIT DATA

TRANSMIT
DATA
BUFFER

ENABLED PRIOR
TOTO

1 - - - -....

SBI
TRANSMIT
DATA

CLOCKED AT TO
TK-0162

Figure 2-3

SBI
RECEIVE
DATA

Transmit Data Path

RECEIVER 1-----. RECEIVE
DATA
LATCH
DATA

OPENED AT T2
LATCHED AT T3
TK-0163

Figure 2-4

Receive Data Path

2.8.2
SBI Summary
Table 2-2 summarizes the signal fields associated with each
functional group. Figure 2-5 shows the SBI configuration. The
following paragraphs provide detailed descriptions of the
individual group field layouts and functions.
2-13

Table 2-2

Description

Field
ARBITRATION GROUP
Arbitration Field (TR <15:00>)

INFORMATION TRANSFER GROUP
Information Field (B<31: 00>)

Mask Field

SBI Field Summary

Establishes a fixed priority among
nexus for access to and control of
information transfer path.
Bidirectional lines that transfer
data,
command/address,
and
interrupt
information
between
nexus.
Primary
function:
encoded
to
indicate a particular byte within
the
32-bit
information
field
(8<31:00>).

(M<3: 0>)

Secondary function: in conjunction
with the tag field, indicates a
particular type of read data.
Identifier Field

Tag Field

(ID<4:0>)

(TAG<2:0>)

Function Field

Parity Field

(F<3: 0>)

(P<l:0>)

RESPONSE GROUP
Confirmation Field

(CNF<l:0>)

Identifies the 1 og i cal source or
destination
of
information
contained in 8<31:00>.
Defines the transmit or receive
information
types
and
the
interpretation of the content of
the ID and information fields.
Specifies the command code, in
conjunction with the tag field.
This field is valid as part of the
32-bit information field only when
the tag equals command/address.
Provides
even parity for
all
information transfer path fields.
P (0) is generated as parity for
the information field. P(2) is
generated as parity for the tag,
ID, and mask fields.
Asserted by a receiving nexus to
specify one of four response types
and indicate its capability to
the
transmitter's
respond
to
request.

2-14

Table 2-2
Field
Fault Field

SB! Field Summary (Cont)
Description

(FAULT)

A cumulative error line to the CPU
that indicates one of several
errors, stored in the transmitting
nexus fault register, and the
associated SB! cycle in which the
error occurred.

INTERRUPT REQUEST GROUP
Request Field

Alert Field

(REQ<7:4>)

(ALERT)

Allows a nexus to request an
interrupt to service a condition
requiring CPU intervention. Each
request lines represents a level
of nexus request priority.
A c um u 1 a t i v e s t a t u s 1 i n e t ha t
allows those nexus not equipped
with an interrupt mechanism to
indicate a change in power or
operating conditions.

CONTROL GROUP
Clock Field

(CLOCK)

Six control lines that provide the
clock
signals
necessary
to
synchronize SB! activity.

Fail Field (FAIL)

A single line from the restart
nexus to provide a restart signal
to the CPU to initiate a system
restart operation.

Dead Field

(DEAD)

A single line to the CPU to
indicate
an
impending
clock
circuit or SB! terminating network
power fa i 1 ure.

Unjam Field

(UNJAM)

A single line from
attached nexus that
restore operation.

Interlock Field

(INTLK)

the CPU to
initiates a

A single
line
that
provides
coordination
among
nexus
responding to certain read/write
commands
to
ensure
exclusive
access to shared data structures.

2-15

ARBITRATION
TR <15:00>
INFORMATION TRANSFER
P < 1 :O> (PARITY)
TAG <2:0> (TAG
ID <4:0> (IDENTIFIER)
M <3:0> (MASK)
B <31 :OO> (INFORMATION)
RESPONSE
FAULT
TRANSMIT/
RECEIVE
NEXUS

CNF

<H» (CONFIRMATION)
CONTROL

TRANSMIT/
RECEIVE
NEXUS

UNJAM
FAIL
DEAD
INTLK (INTERLOCK)
CLOCK (6 LIN ES)
INTERRUPT REQUEST
REQ <7:4> (REQUEST)
ALERT
MP1-2
SPARE (2 LINES)

TK-0077

Figure 2-5

2.8.3

SBI Configuration

Arbitration Group Functions and Assignments

The arbitration lines (Transfer Request TR<l5:00>) allow up to 15
nexus to arbitrate for the information lines (information transfer
group). One arbitration 1 ine is assigned to each nexus to
establish the fixed priority access. Priority increases from TR15
to TR00, where TR00 is the highest. The lowest priority level is
reserved for the CPU, and it requires no actual TR signal line.
The other 15 nexus are assigned TR15 through TR01.

2-16

The highest priority level, TR00, is reserved for those nexus that
require more than one successive SBI cycle. TR00 may only be used
by nexus that require:
a.
b.
c.

Two or three adjacent cycles for a write type exchange.
Two adjacent cycles for an extended read exchange.
Adjacent cycles for interrupt summary read exchanges and
restore operations.

A nexus requests control of the information path by asserting its
assigned TR line at T0 of an SBI cycle. At T3 of the same SBI
cycle, the nexus examines (arbitrates) the state of all higher
priority TR lines.
If no higher TR lines are asserted, the
requesting nexus assumes control of the information path at T0 of
the following SBI cycle. At this T0 time state, the nexus negates
its TR line and asserts command/address or data information on
B<31:00>. In addition, if a write type exchange is specified, the
nexus asserts TR00 to retain control of adjacent SBI cycles.
If higher priority TR lines are asserted, the requesting nexus can
not gain control of the information path. The nexus keeps its TR
line asserted and again examines the state of higher priority
lines at T3 of the next SBI cycle. As before, if no higher TR
lines are asserted, the nexus assumes information path control at
T0.
2.8.4
Information Transfer Group Description
Each information group field
is described
in detail
in the
following paragraphs. However, the information field (B<31: 00>) is
described in the context of the other information group fields.
2.8.4.1 Parity Field -- The parity field (P<l:0>) provides even
parity for detecting single bit errors in the information group
(Figure 2-6).

PARITY
FIELD

rTAGI

IDENTI Fl:ER FIEL

INFORMATION FIELD

~
TAG <2:0>

'---..,---)
ID <4:0 >

B <31 :OO>

P < 1 :O>

COMMAND FORMAT
FUNCTION
FIELD

ADDRESS
FIELD

------.......,-----'l___________.
F <3:0>

A <27:00>
TK-0166

Figure 2-6

Parity Field Configuration
2-17

A transmitting nexus generates P0 as parity for TAG<2:0>, ID<4:0>,
and M<3:0>. The Pl parity bit is generated for 8<31:00>. P0 and Pl
a re genera t e d such t ha t the sum o f a 11 1 og i c one bi ts i n the
checked field, including the parity bit, is even. With no SB!
transmissions, the information transfer path assumes an all zeros
st a t e ; th us , P < 1 : 0 > sh o u 1 d a 1 wa y s c a r r y even pa r i t y • An y
transmission with odd parity is considered an error.
2.8.4.2 Tag Field Formats -- The tag field (TAG<2:0>) is asserted
by a transmitting nexus to indicate the information type being
transmitted on the information lines. The tag field determines the
interrelation of the ID and 8 fields. In addition, the tag field,
in conjunction with the mask field, further defines special read
and write data conditions. The following paragraphs describe each
information type, tag code, and associated field content.
Command/Address Tag -- A tag field content of 011 indicates that
the content of 8<31:00> is a command/address word. ID<4:0>,
asserted at this time, is a unique code identifying the logical
source (commander) of the command. As shown in Figure 2-7,
8<31:00> is divided into a function field and an address field to
specify the command and its associated address.
In a write type command, the ID field code represents the logical
source and the address field specifies the logical command
destination. For a read type command, the addressed nexus holds
the transmitted ID for transmission with the requested data. The
ID is sent with the read data to indicate destination.
The 2 8 b i ts o f the S8 I add res s f i e 1 d def in e a 2 6 8 , 4 3 5 , 4 5 '5
longword address space, which is divided into two sections.
Addresses 0--7FFFFFF h are reserved for primary memory. Addresses
8000000 --FFFFFFF 1 ·are reserved for device control registers.
16
Generally,
primary16memory begins at address 0; the address space
is dense and consists only of storage elements. The control
address space is sparse with address assignments based on device
type. Each nexus is assigned a 2048, 32-bit longword address space
for control. The addresses assigned are determined by the TR
n umber as shown in Figure 2-8.
B <31 :OO>

81.

TAG <2:0>

ID <4:0>

M <3:0>

_F_u_N_c_T_io_N______
A_D_D_R_E_s_s_

F <3:0>

___.

A <27:00>

TAG <2:0> = 011 = COMMAND/ADDRESS FORMAT
ID <4:0> = LOGICAL COMMAND SOURCE
M <3:0> = COMMAND DEPENDENT
F <3:0> = COMMAND CODE
A <27:00> = READ/WRITE. ADDRESS OF INTENDED NEXUS
TK-0167

Figure 2-7

Command/Address Format
2-18

SPECIFIES ONE OF THE
2048 LOCATIONS
ASSIGNED TO EACH NEXUS

SPECIFIES ONE
OF 16 NEXUS

~,,..--~~~_,,.....--~~--

27 26

1514

1110

MUST BE ZERO

TR# (ADDRESS
SPACE BLOCK)

A <27:00>
TK-0168

Figure 2-8

Control Address Space Assignment

~LOGICAL

ERROR-FREE DATA

TAG <2:0>

M <3:0>

B<31:00>

r-::::1 LOGICAL

r::::-1

CORRECTED DATA

TAG <2:0>

M <3:0>

B <31 :OO>

r:::-1 LOGICAL

r:::::-1

UNCORRECTED DATA OR OTHER
MEANINGFUL INFORMATION

TAG <2:0>

M <3:0>

B <31 :OO>

L.::_j DESTINATION ~
ID <4:0>

TK-0169

Figure 2-9

Read Data Formats

Read Data Tag
A tag field content of 000 indicates that
B<31:00> contains data requested by a previous read type command.
In this case, ID<4:0> is a unique code that was received with the
read co mm and and id en ti f i es the 1 o g i ca 1 des t in at ion o f the
requested data. The retrieved data may be one of three types:
read data; corrected read data; or read data substitute, where the
particular type is identified by M<3:0>.
Read data is the normally expected error-free data having M<3:0> =
0000 (Figure 2-9). Note that this tag code is also the idle state
of the tag field and that ID code 0 is reserved. No device will
respond when the tag is 000 and the ID code is 0.

2-19

Corrected read data is data in which an error was detected and
subsequently corrected by the error correction code (ECC) logic of
the device transmitting the read data. In this case, the mask
field flags the corrected data with M<3:0> = 0001.
Read data substitute represents data in which an error was
detected but not corrected. In this case, 8<31:00> will contain
the substitute data in the form of uncorrected data or other
meaningful information. The mask field flags the uncorrected data
with M<3:0> = 0010. As with the other read data types, the ID
field identifies the read commander.
Wr i t e Data Tag
A tag f i e 1 d content o f 1 0 1 i nd i ca t es th a t
B<31:00> contains the write data for the location specified in the
address f i e 1 d o f the pr ev i o us wr i t e co mm and ( Fig u r e 2 -1 0 ) . The
w r i t e data w i 11 be asserted on 8 < 3 1 : 0 0 > in the s BI c ye 1 e
immediately following the command/address cycle. Certain command
codes use M<3:0> to specify particular bytes within 8<31:00>.

LOGICAL
SOURCE

TAG <2:0>

ID <4:0>

WRITE DATA

B <31 :OO>

M <3:0>

TK-0170

Figure 2-10

Write Data Format

Interrupt Summary Tag
A tag field content of 110 defines
B<31:00> as the interrupt level mask for an interrupt summary read
command.
The level mask
(8<07:04>)
is used to indicate the
interrupt level being serviced as the result of an interrupt
request. In this case, the ID field identifies the commander,
which is usually a CPU.
Although unused,
M<3:0> must be
transmitted as zero.
The interrupt sequence consists of two exchanges:
a•

The f i rs t
serviced.

ex ch a ng e

i nd i ca t e s

the

i n t er r up t

b•

The second ex ch an g e i s the res po n s e , whe re
requesting the interrupt identifies itself.

l eve 1

be in g

the

d ev i c e

The interrupt summary read and response formats are illustrated in
Figure 2-11. Note that the interrupt summary response encodes
TAG<2:0> = 000.
Reserved Tag Codes -- TAG<2: 0> -- Tag code 111 is reserved for
d i a g nos t i c p u r poses • Tag code s 0 0 l , 01 0 , and 1 0 0 a re unused and
reserved for future definition.

2-20

FIRST EXCHANGE:
INTERUPT SUMMARY
READ

B31

~ 1~~MMAND-1 ~
TAG<2:0>

ID<4:0>

ICAL
L
DESTINATION

SECOND EXCHANGE:
INTERUPT SUMMARY
RESPONSE

TAG<2:0>

ID<4:0>

M<3:0>

08 07
ZERO

0403

j~~~~~s114-ZERO~
RE0<7:4>

B31

171615

01 00

iol

lol

t f

BIT PAIRS
(BIT PAIRS= B17 AND 801 - 831 AND B15)
TK-0171

Figure 2-11

Interrupt Summary Formats

2.8.4.3 Identifier Field -- The ID field (ID<4:0>) contains a
code that identifies the logical source or logical destination of
the information contained in 8<31:00>. ID codes are assigned only
to commander and responder nexus (i.e., those that issue and
recognize command/address information). Each nexus is assigned an
ID code that corresponds to the TR line that it operates. For
example, a nexus assigned TR05 would also be assigned ID code 5.

More than one ID code may be assigned to a nexus. However, that
nexus must be capable of responding to read type commands for
which the read data returns in an order different from the order
in which the commands were given. For write masked and extended
write masked commands, the mask is transmitted in the cycle
preceding the cycle for the data to which the mask applies.
Nexus using more than one code take the first code from the
standard ID code assignment (0--15). The second code is taken from
the range 17--30 (i.e., first ID code plus 16).

2-21

Certain ID codes are reserved:
ID = 15, unit processors; ID = 31,
diagnostic purposes. ID = 0 is reserved so that the idle state of
the SBI (read data, destination ID = 0) will not cause a nexus
select ion. Note that even tho ugh a nexus is not selected, a 11
nexus are checking for correct SB! parity.

2.8.4.4 Mask
Field
The
mask
field
(M<3:0>)
has
two
interpretations:
primary
and
secondary.
For
the
primary
interpretation, M<3:0> is encoded to specify operations on any or
al 1 data bytes appearing on B< 31: 00 >. The mask is used with the
read masked, write masked, interlock read masked, interlock write
masked, and extended write masked commands. As shown in Figure
2-12, each bit in tne mask field corresponds to a particular byte
on 8<31:00>.
The secondary interpretation is used when TAG<2:0> = 000 (read
data). This interpretation defines the data types as specified in
Table 2-3. All other mask field codes (0011--1111) are reserved
and are interpreted as read data substitute by the receiving
nexus.
Table 2-3

Read Data Types

M<3:9>

Data Type

0000
0001
0010

Read data
Corrected read data
Read data substitute

B<31 :OO>

BYTEO
TK-0172

Figure 2-12

Mask Field Format

2-22

2.8.5
Response Group Description
The three response lines are divided into two fields: Confirmation
(CNF<l:0>), and Fault (FAULT). CNF<l:0> informs the transmitter as
to whether or not the information was received correctly and if
the receiver can process the command. FAULT is a cumulative error
indication of protocol or information path malfunction; it is
asserted with the same timing as the confirmation field.
Either field is transmitted two cycles after each information
transfer. Confirmation is delayed to allow the information path
signals to propagate, be checked, and be decoded by all receivers;
and to allow confirmation generation by the responder. During each
cycle, every nexus in the system receives, latches, and makes
decisions on the information transfer signals. Except for multiple
bit transmission errors or nexus malfunction, one (or more) of the
nexus receiving the information path signals will recognize an
address or I D code . Thi s n ex us then assert s the a ppr op r i a t e
response in CNF.
Any (or all) nexus may assert FAULT after detecting a protocol or
information path failure.
2.8.5.1 Confirmation Codes
codes and their interpretation.
Table 2-4
CNF Code

Table

2-4

lists

the

confirmation

Confirmation Code Definitions
Definitions

00, No Response

(N/R)

The unasserted state; it indicates
response to a commander's selection.

01, Acknowledge

(ACK)

The positive
transfer.

acknowledgment

no
any

10, Busy (BUSY)

The
response
to
a
command/address
transfer
that
indicates
successful
selection of a nexus that is presently
unable to execute the command.

11, Error

The
response
to
a
command/address
transfer that indicates selection of a
nexus that cannot execute the command.

(ERR)

A BUSY
(10) or ERR (11) response to transfers other than
command/address transfers will be considered as no response from
the responder.
2.8.5.2 Response Handling -- The transmitting nexus samples the
CNF and FAULT lines at T3 of the third cycle following
transmission. ACK is the expected confirmation response (i.e.,
command will be executed, or information has been received
correctly) •
2-23

Should a command/address transfer receive a BUSY confirmation, the
commander will repeat the transmission (after a nominal waiting
period) until it is accepted or a timeout occurs.
An N/R confirmation should be treated like BUSY, except that its
occurrence may be flagged in a status bit. ERR confirmation is the
result of a programming error, and should abort the command and
invoke the appropriate recovery routine.
Some nexus may be unable to determine, within two SB I cycles,
whether a function will be completed successfully. For these
cases, the nexus presumes success and responds with ACK
confirmation. If it is later determined that a read type function
cannot be completed, a read data transfer of all zeros is
transmitted and an interrupt requested. If a write type request
cannot be completed, the command is aborted and an interrupt
requested. In either case, the cause of the interrupt is indicated
in a configuration/status register.
2.8.5.3 Successive Cycle Confirmation
Since write masked,
extended write masked, and extended read operations consist of
successive transfers, acknowledgment is more complex.

If the command/address transfer is confirmed with N/R or
BUSY, then no notice will be taken of the data transfer
confirmation and the entire sequence will be repeated.

If the command/address transfer receives ERR, the
sequence is aborted and recovery routines are invoked.

If ACK is not received as confirmation for a write data
command, the command is repeated.

Transmissions of read data are confirmed with ACK by the
receiver of that data. The read data transmitter may
ignore this confirmation, since only commanders execute
retry sequences.

SBI Sequence Timeouts
All commanders implement two
timeout functions: interface sequence timeout and read data
timeout. Bo th t i meo u ts a re spec i f i e d a s 1 0 2 • 4 us ( or 5 1 2 SB I
cycles).
2.8.5.4

The interface sequence timeout determines the maximum time allowed
to complete an interface sequence. The sequence interval is
defined as the time from:
a.

when SBI arbitration is initiated, until ACK is received
for a command/address transfer that specifies read, or

when SBI arbitration is initiated, until ACK is received
for a command/address transfer that specifies write, and
ACK is also received for each transmission of write data,
or
2-24

when
SBI
arbitration
is
confirmation
is
received
transfer.

initiated,
and
an
ERR
for
any command/address

The read data timeout is defined as the time from when an
interface sequence that specifies a read command is completed, to
the time that the specified read data is returned to the
commander. In the case of an extended read function, both
longwords must be retrieved prior to timeout (102.4 us).
If the last command/address transfer prior to an interface
sequence timeout receives an N/R confirmation, it is recorded in a
status bit. Certain nexus may terminate their requests for SBI
control due to an unusual occurrence in those nexus. When this
occurs, both timeouts are cancelled (e.g., when a nexus detects a
data late error).
When a timeout occurs, the commander provides the actual address
or reconstructed address for which the timeout occurred.
In
addition, the commander records the type of timeout received
(i.e., interface sequence or read data).
Either timeout will
terminate a command transmission retry.

2. 8. 5. 5 Fault Detection -- Each nexus is equipped with a 32-bi t
configuration and fault status register (register 0). The fault
status portion of this register contains flags that cause the
assertion of the FAULT line. The fault status portion is described
in Figure 2-13.
A n ex us de t e c t i ng one o f the fa u 1 t co nd i t ions w i 11 ass e r t the
FAULT signal for one cycle. FAULT then causes each nexus on the
system to lack its respective configuration register. The fault
status bits thus latched refer to the cycle during which the fault
occurred. The CPU examines the FAULT signal and latches the signal
on the leading edge of FAULT. The CPU then continues to assert
FAULT until the software has examined the fault bits of all nexus
and has specified the negation of FAULT. Figure 2-14 shows the
timing involved.
Figure 2-15 illustrates the confirmation and
for all responses and error conditions.

2.8.6

fault decision

flow

Interrupt Request Group Description

The interrupt request group consists of four request lines
(REQ<7:4>) and an alert (ALERT) line. Request lines are assigned
to some of the nexus and represent assigned CPU interrupt levels.
The lines used by nexus request that the CPU service a condition
requiring processor intervention. The request lines are priority
encoded in an ascending order of REQ4--REQ7. A requesting nexus
asserts it request lines (or line) asynchronously with respect to
the SB! clock to request an interrupt. Any of the REQ lines may be
asserted simultaneously by more than one nexus, and any
combination of REQ 1 ines may be asserted by the collection of
requesting nexus.
2-25

FAULT STATUS

PWR
FLT

wsa

URD
FLT

ISO
FLT

MXT
FLT

XMT
FLT

FLT

WRITE
SEQUENCE
FAULT

ALERT/INTERRUPT
AND DEVICE STATUS
""

PARITY
FAULT

NOT USED

INTERLOCK
SEQUENCE
FAULT

TRANSMITTER
DURING CYCLE
THAT CAUSED FAULT

UNEXPECTED
READ DATA
FAULT

MULTIPLE
TRANSMITTER
FAULT
TK-0076

Figure 2-13

Fault Status Flags

A NEXUS
DETECTS A
FAULT ON
THE SBI

,,
I

I I I
T3 T'O T1

I I

CPU
LATCHES
FAULT

CYCLE THAT
CAUSES FAULT

I
I

DETECTING
NEXUS
ASSERTS
FAULT

I I

l
I

I
I

ALL NEXUS
LATCH FAULT STATUS
BITS
TK-0098

Figure 2-14

Fault Timing

2-26

SBI FAULT DEFINITIONS
FAULT
DEFINITION
PARITY REPRESENTS AN INFORMATION PATH ERROR GENERATED BY ONE OR MORE NEXUS WHEN THE CALCULATED
PARITY DISAGREES WITH THE RECEIVED PARITY.

SBIT3

WRITE RESULTS WHEN A NEXUS WHICH RECEIVED A WRITE
SEQUENCE MASKED, EXTENDED WRITE MASKED, OR INTERLOCK
WRITE MASKED COMMAND IN THE PRECEDING CYCLE
DOES NOT RECEIVE THE ANTICIPATED WRITE DATA IN
THE CURRENT CYCLE.
PARITY
FAULT

MULTIPLE
XMITTER
FAULT

ACK

WRITE
SEQUENCE
FAULT

N
I
N
-.J

PARITY
FAULT
READ DATA
TAG

C/A
TAG

UNEXPECTED RESULTS WHEN A NEXUS WHICH IS NOT WAITING FOR
READ READ DATA FROM A PREVIOUSLY ISSUED READ
DATA MASKED, EXTENDED READ, OR INTERLOCK READ
MASKED COMMAND RECEIVES A RESPONSE TO A READ
TYPE COMMAND.

N/R

INTERLOCK RESULTS WHEN A NEXUS RECEIVES AN INTERLOCK
SEQUENCE WRITE MASKED COMMAND AND INTERLOCK HAS NOT
BEEN SET BY AN INTERLOCK READ MASKED COMMAND.
MULTIPLE RESULTS WHEN A TRANSMITTING NEXUS DETECTS MULTRANS- TIPLE TRANSMITTERS IN THE SAME CYCLE BY COMMITTER PARING THE RECEIVED ID TO THE TRANSMITTED ID ONE
CYCLE AFTER TRANSMITTING.

INTERRUPT SUMMARY
READTAG

N/R

RESERVED

N/R

ACK

ERR

ACK

INTERRUPT
SUMMARY
RESPONSE

ACK
UNEXPECTED
READ DATA
FAULT

BSY
INTERLOCK
SEQUENCE
FAULT

TK-0086

Figure 2-15

Confirmation and

Fault Decision Flow

The ALERT signal is asserted by nexus that do not implement
interrupt request lines. Its purpose is to indicate to the CPU a
change in the nexus power condition or operating environment.
Nexus tha''t implement the REQ lines report such changes by
requesting an interrupt.
Interrupt Operation
When a nexus requires an
interrupt, it asserts its REQ line on the SBI. At a time judged
appropriate, the CPU will recognize the interrupt request and
issue an interrupt summary read command (TAG<2:0> = 110). The
command will have a single bit set in its interrupt level mask
(B<7:4>), which corresponds to the REQ line being serviced. For
example, B 04 set to a logic one indicates that the REQ4 level is
being serviced. Note that the remaining information path fields
(i.e., B<31:08>, ID<03:00>, and M<3:0>) are transmitted as zero.
2.8.6.1

Nexus receiving the interrupt summary read command without error
and asserting the REQ line specified in the interrupt level mask
will assert a 2-bit code in B<31:00>. This code, which identifies
the requesting nexus, is asserted with the timing of CNF<l: 0>.
However, the responding nexus does not assert any CNF, TR, ID, or
TAG line. Nexus that detect incorrect parity will assert FAULT.
As shown in Figure 2-16, the asserted bits are in corresponding
positions in the upper and lower 16 bits of B<31:00>. The bit pair
uniquely identifies the nexus among those using the particular REQ
1 in e • On 1 y 15 bi t pa i rs in the info rm at i on f i e 1d a re used ( i • e • ,
B3 1 and B1 5 th r o ugh B1 7 and B0 1 ) • Si n c e on 1 y pa i rs o f b i ts are
asserted, parity remains correct regardless of the number of
responding nexus. The two bi ts assserted by the requesting nexus
are equal to the nexus TR number and the nexus TR number plus 16.

INTERRUPT~B_3_1

_____________________________________________o_s__
o1____0~4~03.;___o.,;. ;.o

~~: MARY r-~------------ZER0---------~3~:~EULESTEzER03

831
INTERRUPT
SUMMARY
RESPONSE :,

171615

01 00

Hf
t

lol
f

BIT PAIRS

TK-0164

Figure 2-16

Request Level and Nexus Identification

2-28

While holding control of the SBI with TR00, the CPU waits two
cycles after the interrupt summary read command is transmitted
before latching B<31:00> into an internal register. By encoding
the REQ level and the bit pair received from responding nexus, the
CPU generates a vector unique to that level and nexus. The vector,
in turn, is used to invoke the nexus service routine. The service
routine will take explicit action by writing a device register to
clear the interrupt condition. Clearing the interrupt causes the
nexus to negate the REQ 1 ine, provided that the nexus does not
have any other outstanding interrupts at this level. The negation
of REQ occurs within two cycles of the write data transmission.
Normally, the CPU will service requests in descending order, of
REQ7--REQ4. Similarly, nexus are identified in descending order
beginning with the nexus that asserts bits B31 and BlS and ending
with the nexus that asserts bits Bl7 and Bl. If multiple nexus are
requesting interrupts on the same REQ line, multiple interrupt
summary read commands are issued until all nexus have been
serviced and the REQ line is no longer asserted.
Figure 2-17
operation.

functional

timing

chart

for

the

interrupt

2.8.6.2 Status Register Alert Flags -- As shown in Figure 2-18
each nexus maintains bits in its configuration register to
indicate conditions that cause assertion of ALERT (or the
appropriate REQ line if implemented). Power down and power up
status bits are provided, but additional ALERT status bits are
present if other conditions, such as overtemperature, are
detectable.

The ALERT line is the logical OR of the alert status bits; it is
asserted synchronously to the SB I clock. Alert status bi ts are
cleared when written as logic one; when written as logic zero,
UNJAM signal is received. Note that the UNJAM signal does not
clear these status bits.
2. 8. 6. 3 Alert Flag Operation
A nexus asserts ALERT or an
interrupt request when any of its alert status bits are set. The
bits are set during the following events:

during power fa i1 ure at the nexus when the assert ion of
power supply AC LO is recognized;

during the restoration of power when the negation of AC
LO is recognized;

when
other
environmental
overtemperature, are detected;

2-29

conditions,

such

SBI CYCLESL_co---·l··--CN----.....1·--CN + 1
(CO-CN)

COMMAND ER
(CPU)

RECEIVER
NEXUS
(ARBITRATION)

SBI LINE
SAMPLING

.,J. .

TRANSMITTER
NEXUS
(INTR. SERVICED)

TO T1

DECODES REQ
<7:4>
AND B <31 :01 >

RECEIVER
NEXUS

J..

TO T1

INVOKES
SERVICE
ROUTINE

REQUEST NEXUS
DECODES
INTERRUPT
SUMMARY READ
COMMAND

SBI
CYCLE N+3

CLEAR
INTERRUPT

ID CODE INTO
LATCHES

CPU NEXUS
SELECTS
HIGHEST
PRIORITY REQ
LINE

l
REQUEST NEXUS
ASSERTS CODE
ON B <31:01>
ATTO

1
STROBES
COMMAND
INTO LATCH ES

N
I

SBI LINE
SAMPLING

ASSERTS TROO AND
ISSUES INTERRUPT
SUMMARY READ

ASSERTS
ASSIGNED
REQ LINE

CN + 2-•·l·•-CN + 3--t•...l·--CN + 4 - + LATER
CN + 5 +

(FOR SBI)

REQ LINE
INTO LATCHES

SBI
TIME
FRAMES

SOMETIME

·I·

REQUEST ING
NEXUS

TRANSMITTER
NEXUS
(REQUEST)

SBI LINE
SAMPLING

RECEIVER
NEXUS
(INFORMATION)

ASSERTS ID
NEXUS CODE
B <31:01>
INTERRUPT
SUMMARY RESPONSE

INFORMATION
PATH DECODE

SBI LINE
SAMPLING
NEGATES
REQUEST LINE

CPU
ARBITRATES
FOR CONTROL
OF SBI

CPU NEXUS
STROBES CODE
INTO LATCHES
ATT3

CPU GETS
ARB OK
ATT3

SBI
CYCLE N+4

l
SBI LINE
SAMPLING

START

REQUEST NEXUS
ASSERTS
ASSIGNED
REQUEST LINE
(REQ <7:4>)

SBI
CYCLE N

CPU NEXUS
ASSERTS TROO
AND ISSUES
INTERRUPT
SUMMARY READ
COMMAND AT TO
REQUEST NEXUS
STROBESCMD
INTO LATCHES
ATT3

Figure 2-17 Interrupt Operation
Timing and Flow

j_
ENCODED DATA
PROVIDES
INTERRUPT
VECTOR

I
SBICYCLE
cN+s+x
SOME TIME LATER

LATCH CONTENT
IDENTIFIES REQ
LEVEL BEING
SERVED

SBI
CYCLE N+2

I
CPU NEXUS
ENCODES REQ
LINE AND
B <31:01>

CPU NEXUS
CLEARS
INTERRUPT
INVOKES SERVICE
ROUTINE

TERMINATE
TK-0106

The alert status bits are only set on the transition of the event
that caused them to set.
The power down status bit is set when there is a transition of the
nexus AC LO from the negated to the asserted state. Setting the
power down status bit clears the power up status bit; likewise,
setting the power up bit clears the power down bit. The
overt em per at u re bi t i s set when the re i s a t rans i t i on f r om the
normal to the overtemperature state.
A nexus asserting ALERT, or asserting an interrupt request due to
an alert status bit set, continues to assert ALERT until:
a.

all alert status bits are cleared
one) ,

UNJAM signal is received,

nexus loses de power.

(written with a

logic

The negation of ALERT (or REQ) is synchronous to the SBI clock and
occurs within two cycles of the write data transmission used to
clear the ALERT condition.

ALERT OR
INTERRUPT STATUS
31

1------~~-~-T-L~-S----~1

--~~~~A~~~~-123 22 21 20 1 1 11 1

s a

o!~

v
PlR
DEVICE
OWN TMP DEPENDENT
PV VR
UP

~1-------D-E_P_E_N-~-~-~-~-~-T-A_T_U_S______..,.

TK-0107

Figure 2-18

Alert Status Bits

2-31

2.8.7
Command Code Description
The
operations
executed
over
the
SBI
are
specified
in
command/address format
using the mask, function, and address
fields. Figure 2-19 summarizes the command/address formats and
lists the command codes. Several function codes are unused and
reserved for future use. All nexus must respond to these reserved
codes with an N/R confirmation.
The

2.8.7.1 Read Masked Function
specified in Figure 2-20.

MASK

read

FUNCTION

AOORESS

F <3:0>

A <27:00>

M <3:0>

masked

MASK
USE

FUNCTION
CODE

FUNCTION
DEFINITION

IGNORED
USED
USED
IGNORED
USED
IGNORED
IGNORED
USED
IGNORED
IGNORED
IGNORED
USED
IGNORED
IGNORED
IGNORED
IGNORED

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RESERVED
READ MASKED
WRITE MASKED
RESERVED
INTERLOCK READ MASKED
RESERVED
RESERVED
INTERLOCK WRITE MASKED
EXTENDED READ
RESERVED
RESERVED
EXTENDED WRITE MASKED
RESERVED
RESERVED
RESERVED
RESERVED

function

TK-0083

Figure 2-19

COMMAND/[:]
ADDRESS
011
FORMAT
TAG <2:0>

READ~
000

DATA
FORMAT

TAG <2:0>

SBI Command Codes

LOGICAL
SOURCE

BYTE
COMBINATION

0001

PHYSICAL
ADDRESS

ID <4:0>

M <3:0>

F <3:0>

A <27:00>

DATA
DESTINATION

TYPE
OF
DATA

RETRIEVED DATA

ID <4:0>

M <3:0>

B <31 :OO>
TK-0084

Figure 2-20

Read Masked Function Format
2-32

Prior to issuing the command, the commander arbitrates for SBI
control. When the commander gains control of the SBI, it asserts
the information transfer lines at T0. At T3 of the same cycle,
each nexus strobes the command/address information into its
receiver latches for decoding. The command/address format,
presented on the SBI, instructs the nexus selected by the address
field, SA<27:00>, to retrieve the addressed data word and transfer
it to the logical destination specified in the ID field. The
addressed nexus will respond to the command/address transfer with
ACK (assuming no errors) two SBI cycles after the assertion of
command/address.
The addressed data is retrieved in a time frame that is dependent
on the nexus response time. Following the response delay, the
responding nexus must arbitrate for control of the SB!. After ARB
OK is true for the responder, the information fields are asserted
on the SBI at T0. TAG<2:0> is coded as 000, specifying the read
data format; and ID<4:0> is coded to identify the commander. The
read data is asserted on 8<31:00> and received by the commander as
read data (M<3:0> = 0000), or as corrected read data (M<3:0> =
0001). In the case of uncorrectable read data, the responder
transmits read data substitute (M<3:0> = 0010).
After the assertion of read data, the commander latches the
content of B<31:00> at T3 of the same SBI cycle. At T0 two cycles
later, the commander confirms the successful transfer by asserting
ACK.
Figure 2-21
operation.

functional

timing

chart

for

the

read

masked

2.8.7.2 Extended Read Function -- The extended read function is
simi 1 a r to the read masked function in operation. The function
format is shown in Figure 2-22.
The mask field and bit SA00 of the received command/address word
are ignored. However, the mask field must be transmitted as zero.
In an extended read, 64 bits (two data longwords) are always
transmitted, and thus require two contiguous SBI data transfer
cycles. In this case, F<3: 0> instructs the nexus selected by
SA<27:00> to retrieve the addressed 64-bit data and transfer it to
the commander (specified in the ID field) as in the read masked
function.

2-33

SBI C Y C L E S ! - - c o - - + - c 1
(CO-CN)
COMMANDER

TRANSMITIER
NEXUS
(ARBITRATION)

ASSERTS
TR# ON SBI

TRANSMITIER
NEXUS
(INFORMATION)

RECEIVER
NEXUS
(CONFIRMATION)

SBI LINE
SAMPLING

READ DEVICE
RESPONSE TIME

SBI LINE
SAMPLING

CN+2

RECEIVER
NEXUS
(INFORMATION)

STROBES
CIA ACK INTO
LATCHES

CN+3
SBI LINE
SAMPLING

CN+4---I

TRANSMITIER
NEXUS
(CONFIRMATION)

STROBES
DATA INTO
LATCHES

SBI
CYCLE N+2

ASSERTS
DATA ACK

RESPONDER
ASSERTS DATA
ON INFO LINES
ATTO

l
CIA IS VALID IN
RECEIVER LATCHES

NO HIGHER
TR#
ASSERTED

ASSERTS
CIA ACK

ASSERTS
TR# ON SBI

RESPONDER

CN+1

ASSERTS
CIA

NO HIGHER
TR#
ASSERTED

SBI
TIME
FRAMES

SBI LINE
SAMPLING

RECEIVER
NEXUS
(INFORMATION)

NEXUS DECODE
TIME

TRANSMITTER
READ DEVICE
NEXUS
(CONFIRMATION) RESPONSE TIME

STROBES
DATA ACK
INTO LATCHES

ASSERTS
READ DATA
ON SBI

TRANSMITIER
NEXUS
(ARBITRATION)

TRANSMITIER
NEXUS
(INFORMATION)

SBI
CYCLE 0

COMMANDER
ASSERTS CIA
ON INFO LINES
ATTO

TEST TR LINE
ATT3

RESPONDER
STROBES INFO
LINES INTO
LATCHES AT T3

SBI
CYCLE 2

COMMANDER
SAMPLES AND
RESPONDER
DECODES SBI
LINES

SBI
CYCLE 3

RESPONDER
ASSERTS CIA ACK
ON CONFIRM,
LINES AT TO

COMMANDER
STROBES CIA ACK
INTO LATCHES
ATT3

SBI LINE
SAMPLING

RECEIVER
NEXUS
(CONFIRMATION)

j_
COMMANDER
SAMPLES AND
RESPONDER
DECODES SBI
LINES

SBI
CYCLE N+4

SBI
CYCLE N+1

COMMANDER
ASSERTS DATA
ACK ON
CONFIRM.
LINES AT TO

SBI
CYCLE N

CYCLE N
REPRESENTS
DEVICE RESPONSE
TIME REQUIRED
FOR CMD
EXECUTION

SBI
CYCLE N+3

START
SBI
CYCLE 1

COMMANDER
STROBES DATA
INTO LATCHES
ATT3

TEST TR LINE
AT T3

RESPONDER
STROBES DATA
ACK INTO
LATCHESATT3

TERMINATE

TK-0082

Figure 2-21
Read Masked
Timing Chart
2-34

COMMANDG
ADDRESS
011
FORMAT
TAG<2:0>

0000

LOGICAL
SOURCE

(LOGICALLY
IGNORED)

1000

ID<4:0>

M<3:0>

F<3:0>

PHYSICAL
ADDRESS
A<27:01>
(AOO LOGICALLY IGNORED)

FIRST DATA TRANSFER

READ DATA
FORMATS

G
G

TAG<2:0>

DATA
DESTINATION

TYPE OF
DATA

FIRST 32 BITS OF
RETRIEVED DATA

SECOND DATA TRANSFER
DATA
DESTINATION

TYPE OF
DATA

SECOND 32 BITS OF
RETRIEVED DATA

ID<4:0>

M<3:0>

8<31:00>
TK-0173

Figure 2-22

Extended Read Function Format

When the commander gains control of the SBI, it asserts the
command/address information at T0. At T3 of the same cycle, each
nexus strobes the command/address information into its receiver
latches
for
decoding.
The
addressed
nexus
confirms
the
command/address transfer by returning ACK two cycles after the
assertion of command/address. Following the response delay and
arbitration, the responder asserts the first 32-bit data longword
on B<31:00> (SA00 = 0). The other information fields are coded as
in the read masked operation. The second data longword (SA00 = 1)
is asserted on B<31:00> at T0 of the succeeding cycle. The mask
field describing the data type will be asserted with each read
data longword.
The commander latches 8<31:00> (first data longword) at T3 of the
cycle when it was transmitted.
At T3 of the next cycle, the
commander again latches 8<31:00> (second data longword). Then, at
T0 of the following cycle, the commander confirms the first data
transfer with ACK. The commander confirms the second data transfer
with ACK at T0 of the cycle after that.
Figure 2-23 is a functional timing chart showing the extended read
operation.
2.8.7.3 Write Masked Function -- The write masked function format
is shown in Figure 2-24. F<3:0> instructs the selected nexus to
modify the bytes specified by M<3:0> in that storage element
addressed by SA<2 7: 00 > using data transmitted in the succeeding
cycle.

2-35

SBI CYCLES
(CO-CN)

r---

TRANSMITTER
NEXUS
(ARBITRATION)

COMMANDER

TRANSMITTER
NEXUS
(INFORMATION)

SBI LINE
SAMPLING

RECEIVER
NEXUS
(CONFIRMATION)

READ DEVICE
RESPONSE TIME

STROBES
CIA INTO
LATCHES

CN+2

SBI LINE
SAMPLING

RECEIVER
NEXUS
(INFORMATION)

NEXUS DECODE
TIME

NO HIGHER
TR#
ASSERTED
ASSERTS
TR#TO
SBI

TRANSMITTER
READ DEVICE
NEXUS
(CONFIRMATION) RESPONSE TIME

ASSERTS
READ DATA 1
AND HOLD
TO SBI

TRANSMITTER
NEXUS
(ARBITRATION)

CN+3

STROBES
DATA2 INTO
LATCHES

ASSERTS
READ DATA 2
TO SBI

TRANSMITTER
NEXUS
(INFORMATION)

CN+s--1

ASSERTS
DATA2
ACK

ASSERTS
DATA 1
ACK

CN+4

TRANSMITTER
TRANSMITTER
NEXUS
NEXUS
(CONFIRMATION) (CONFIRMATION)

RECEIVER
NEXUS
(INFORMATION)

SBI LINE
SAMPLING

STROBES
DATA 1 INTO
LATCHES

ASSERTS
C/A ACK

0-.

RESPONDER

CN+1

STROBES
C/AACK INTO
LATCHES

NO HIGHER
TR#
ASSERTED

ASSERTS
C/A

ASSERTS
TR# ON
SBI

SBI
TIME
FRAMES

TRANSMITTER
NEXUS
(INFORMATION)

STROBES
DATA 1 ACK
INTO LATCHES

STROBES
DATA 2 ACK
INTO LATCHES

RECEIVER
RECEIVER
NEXUS
NEXUS
(CONFIRMATION) (CONFIRMATION)
TK-0079A

Figure 2-23 Extended Read
Timing Chart and Flow
(Sheet 1 of 2)

2-36

START

SBI
CYCLEO

COMMANDER
ASSERTS TR
LINE ATTO

TEST TR LINE
ATT30N NEXT
SBI CYCLE

SBI
CYCLE 1

I
COMMANDER
ASSERTS C/A
ON INFO LINES
ATTO

1
N
I

......J

RESPONDER
STROBES INFO
LINES INTO
LATCHES ATT3

l
SBI
CYCLE2

RESPONDER
ASSERTS C/A ACK
ON CONFIRM.
LINESATTO

COMMANDER
STROBES DATA 1
INTO LATCHES
ATT3

RESPONDER
STROBES DATA 2
ACK INTO
LATCHES

COMMANDER
STROBES CIA ACK
INTO LATCHES
ATT3

SBI
CYCLE N+3

TERMINATE

SBI
CYCLE N

COMMANDER
STROBES DATA 2
INTO LATCHES
ATT3

1
SBI
CYCLE N+4

SBI
CYCLE N+1

COMMANDER
ASSERTS DATA 1
ACK ON CONFIRM.
LINES AT TO

RESPONDER
ASSERTS TR
LINE AT TO

1
TEST TR LINE
AT T3 ON NEXT
SBI CYCLE

RESPONDER
STROBES DATA 1
ACK INTO
LATCHES AT T3

SBI
CYCLE N+5
SBI
CYCLE N+2

SBI
CYCLE 3

CYCLE N
REPRESENTS
DEVICE RESPONSE
TIME REQUIRED
FOR CMD
EXECUTION

COMMANDER
SAMPLES AND
itESPONDER
DECODES SBI
LINES

1
RESPONDER
ASSERTS DATA 2
ON INFO LINES
ATTO

RESPONDER
ASSERTS DATA 1
AND HOLD ON
INFO LINESATTO

COMMANDER
ASSERTS DATA 2
ACK ON CONFIRM.
LINES AT TO

TK-00798

Figure 2-23 Extended Read
Timing Chart and Flow
(Sheet 2 of 2)

COMMAND/G
ADDRESS
011
FORMAT

LOGICAL
SOURCE

BYTE
COMBINATION

0010

PHYSICAL
ADDRESS

ID <4:0>

M <3:0>

F <3:0>

A <27:00>

101

LOGICAL
SOURCE

0000
(LOGICALLY
IGNORED)

WRITE DATA

TAG <2:0>

ID <4:0>

M <3:0>

B <31:00>

TAG <2:0>

WRITE~
DATA
FORMAT

TK-0091

Figure 2-24

Write Masked Function Format

When the commander gains control. of the SBI, it asserts the
command/address information at T0. The commander also asserts TR00
at T0 to retain control during the succeeding SBI cycle. At T3 of
the same cycle, each nexus strobes the command/address information
into its receiver latches for decoding. At T0 of the succeeding
cycle, the commander asserts data on 8<31:00>; at T3 of the same
cycle, the selected nexus strobes the data into its receiver
latches. TAG<2:0>, which accompanies the data, is coded 101 (write
data format). The successful command/address transfer is confirmed
by the receiving nexus with ACK at T0 of the succeeding cycle. The
successful data transfer is confirmed by ACK at T0, one eye 1 e
later.
Figure 2-2 5
operation.

functional

timing

chart

for

the

write

masked

2.8.7.4 Extended Write Masked Function
The extended write
masked function format is illustrated in Figure 2-26. F<3:0> is
coded 1011 to specify the extended write masked function. In the
extended write masked transfer, the number of bits written depends
on the mask, but two SBI data transfer cycles are always required.
When the commander gains control of the SBI it asserts the
command/address information at T0. The commander also asserts TR00
to retain control during the succeeding SBI cycle.
At T3 of the
same cycle, each nexus strobes the command/address information
into its latches for decoding. The mask that accompanies the
command/address indicates the bytes to be written in the first
data longword, corresponding to SA00 = 0.
2-38

START

SBI CYCLES
(C0-4)

r--

TRANSMITIER
NEXUS
(ARBITRATION)

COMMANDER

TRANSMITIER
NEXUS
(INFORMATION)

NO HIGHER
TR#
ASSERTED

TRANSMITIER
NEXUS
(INFORMATION)

ASSERTS
DATA

COMMANDER
ASSERTS TR
LINEATTO

RESPONDER
ASSERTS CIA
ACK ON
CONFIRMATION
LINES AT TO

TEST TR LINE
ATT3 ON NEXT
SBI CYCLE

STROBES
ACK INTO
LATCHES

ASSERTS
CIA AND
HOLD
SBI
TIME
FRAME

SBI
CYCLE 3

C4--I

RECEIVER
NEXUS
(CONFIRMATION)

STROBES
ACK INTO
LATCHES

SBI
CYCLEO

SBI
CYCLE 1

l
T2

ASSERTS
CIA ACK
STROBES
CIA INTO
LATCHES

STROBES
DATA INTO
LATCHES

COMMANDER
ASSERTS HOLD
AND CIAON
INFO. LINES AT TO

ASSERTS
DATA ACK

RESPONDER
STROBES INFO.
LINES INTO
LATCHES AT T3

RESPONDER

SBI LINE
SAMPLING

RECEIVER
NEXUS
(INFORMATION)

TRANSMITIER
TRANSMITIER
NEXUS
NEXUS
(CONFIRMATION) (CONFIRMATION)

SBI
CYCLE2

COMMANDER
ASSERTS DATA
WORD ON INFO
LINESATTO

l
COMMANDER
STROBES CIA
ACK INTO
LATCHESATT3

SBI
CYCLE4

RESPONDER
ASSERTS DATA
ACK ON
CONFIRMATION
LINES AT TO

COMMANDER
STROBES DATA
ACK INTO
LATCHES AT T3

TERMINATE

RESPONDER
STROBES DATA
WORD INTO
LATCHES AT T3

Figure 2-25 Write Masked
Timing Chart and Flow

COMMAND/8
ADDRESS
TAG <2:0>

LOGICAL
SOURCE

BYTE
COMBINATION

1011

PHYSICAL
ADDRESS

ID <4:0>

M <3:0>

F <3:0>

A <27:00>

Fl AST DATA TRANSFER

FIRST 32 BITS OF
WRITE DATA

BYTE
COMBINATION

LOGICAL
SOURCE

WRITE DATA
FORMAT
SECOND DATA TRANSFER

TAG <2:0>

0000

LOGICAL
SOURCE

SECOND 32 BITS OF
WRITE DATA

(LOGICALLY
IGNORED)

ID <4:0>

M <3:0>

B <31 :OO>
TK-0081

Figure 2-26

Extended Write Masked Function Format

At T0 of the succeeding cycle, the commander asserts data on
8<31:00> and codes TAG<2:0> as 101 (write data format). At T3 of
the same cycle, the receiver nexus strobes the data into its
latches.
In addition, the commander holds TR00 asserted to retain
SB! control for the second data longword transfer. Note that the
mask that accompanies the first data word indicates the bytes to
be written in the second data word. At the end of this cycle, the
commander negates TR00.
At T0 of the succeeding cycle, the second data word is asserted on
B<31:00>, and TAG<2:0> is coded 101. At the same time (T0) the
receiver nexus confirms the command/address transfer with ACK, if
there i s no er r o r • At T 3 o f the same c y c 1 e , the r e c e iv e r n ex us
strobes the data into its latches. The mask that accompanies the
second data longword is ignored by the receiver nexus. During the
two succeeding cycles, the receiver nexus confirms the two data
transfers with an ACK in each cycle.
Figure 2-27 is a functional
masked operation.

timing

2-40

chart

for

the

extended

write

START

SBI CYCLES
(CO-C5l

COMMANDER

i---co

·I·

C1
TRANSMITIER
NEXUS
(INFORMATION)

TRANSMITIER
NEXUS
(ARBITRATION)

NO HIGHER
TR#
ASSERTED

TRANSMITIER
NEXUS
(INFORMATION)

ASSERTS
DATA 1 AND
HOLD

TRANS/REC
NEXUS
(INFO/CONFIRM)

ASSERTS
DATA2

STROBES
DATA 1 ACK
INTO LATCHES

ASSERTS
C/AACK
STROBES
C/A INTO
LATCHES

STROBES
DATA 1
INTO LATCHES

T11

T3 TO

ASSERTS
DATA 1 ACK

STROBES
DATA2
INTO LATCHES

COMMANDER
ASSERTS TR
LINE AT TO

RESPONDER
ASSERTS DATA 1
ACK ON
CONFIRMATION
LINES ATTO
TEST TR LINE
ATT3 ON NEXT
SBICYCLE

STROBES
DATA2 ACK
INTO LATCHES

ASSERTS
C/AAND
HOLD
SBI
TIME
FRAMES

SBI
CYCLE4

RECEIVER
NEXUS
(CONFIRMATION)

STROBES
C/AACK INTO
LATCHES

SBI
CYCLEO

SBI
CYCLE 1

SBI
CYCLE 5

COMMANDER
ASSERTS HOLD
AND C/AON
INFO. LINES AT TO

J
ASSERTS
DATA2 ACK

RESPONDER
STROBES INFO
LINES INTO
LATCHES AT T3

l
SBI LINE
SAMPLING

RECEIVER
NEXUS
(INFORMATION)

TRANS/REC.
NEXUS
(INFO/CONFIRM)

TRANSMITIER
NEXUS
(CONFIRMATION)

l
COMMANDER
STROBES DATA 1
ACK INTO
LATCHES ATT3

SBI
CYCLE 2

SBI
CYCLE 3

RESPONDER
ASSERTS DATA 2
ACK ON
CONFIRMATION
LINES ATTO

COMMANDER
ASSERTS DATA 2
ON INFO. LINES
ATTO

COMMANDER
STROBES DATA 2
ACK INTO
LATCHES ATT3

COMMANDER
ASSERTS DATA 1
AND HOLD ON
INFO LINES AT TO

RESPONDER
ASSERTS C/A
ACK ON
CON Fl RMATION
LINESATTO

RESPONDER
STROBES DATA 1
INTO LATCHES
ATT3

COMMANDER
STROBES C/A
ACK INTO
LATCHES AT T3

TERMINATE

TK-0078

Figure 2-27 Extended Write
Masked Timing Chart and Flow

2.8.7.S

Interlock Function Description -- The interlock function
is used to provide coordination between memory nexus to ensure
exclusive access to shared data structures. When an interlock
sequence
is addressed
to
the
UBA,
it
indicates that a
Data-In-Pause/Data-Out (DATIP/DATO) sequence is required on the
Unibus. The USA will initiate an interlock sequence when a
Unibus
device has initiated a DATIP/DATO sequence. The interlock
functions operate like the read and write functions with the
additional responsibility of setting and clearing the receiver
nexus
interlock
flip-flop.
This
flip-flop
controls
the
assertion/negation of the receiver's interlock line. However, not
al 1 nexus implement the interlock function. Those nexus that do
not will respond to the interlock read and write masked functions
exactly as they do to read and write masked functions.
All memory nexus implement the interlock functions and cooperate
through the use of this signal. The interlock line is asserted by
the commander nexus which issued the interlock read masked
function for that SBI cycle following the command/address
transfer. The interlock flip-flop is set in the receiving nexus
memory. When the memory nexus confirms the interlock read
function, it asserts the interlock signal in the same cycle as
ACK. With interlock asserted, the nexus responds with a BUSY
confirmation to subsequent interlock read masked commands only.
Interlock Read Masked Function Operation -- The interlock read
masked function format is the same as that shown in Figure 2-20
except that F<3:0> is coded 0100. F<3:0> causes the nexus selected
by SA<27:00> to retrieve and transfer the addressed data exactly
as in the read masked operation. In addition, this function causes
the selected nexus to set its interlock flip-flop. With the
interlock flip-flop set, the nexus will assert the SBI interlock
line at T0 of the ACK confirmation cycle.
The interlock flip-flop is cleared on receipt of an interlock
write masked function. Interlock read masked and interlock write
masked functions are always paired by commanders. If the flip-flop
remains set for more than 102.4 us, the memory assumes that the
comm and er has had a ca ta st r op h i c er r o r • In th i s ca s e , the nexus
will clear the flip-flop at T0 of the next cycle.
Interlock Write Masked Function Operation -- The interlock write
masked function format is the same as that illustrated in Figure
2-22, except that F<3:0> is coded 0111, specifying the interlock
write masked function. F<3: 0> instructs the nexus selected by
SA<27:00> to modify the bytes specified by M<3:0> in the addressed
storage element using data transmitted in the succeeding cycle
with TAG<2:0> = 101. In addition, the write data clears the
interlock flip-flop set by the previous interlock read masked
function.

2-42

2.8.8
Control Group
The control group functions synchronize system activities and
provide specialized system communications.
The clock functions
provide SBI activity synchronization and are described in
Pa rag rap h 2 • 8 . 1 • The inter 1 o ck cont r o 1 , a 1 so one o f the system
commmunication functions, is described in Paragraph 2.8.7. The
remaining
control
lines are described
in the
following
paragraphs.

DEAD Function -- The DEAD signal indicates a de
to the c 1 o ck c i r c u i ts o r bus t e rm i n a t i n g net wo r ks .
will not assert any SB! signal while DEAD is asserted. Thus,
prevent invalid data from being received while the SBI is
unstable state.
2.8.8.1
fa i l u re

power
Ne x us
nexus
in an

The assertion of the power supply DC LO to the clock circuits or
terminating networks causes the assertion of DEAD. DEAD is
asserted asynchronously to the SBI clock and occurs at least 2 -s
before the clock becomes inoperative. With power restart, the
clock will be operational for at least 2 -s before DC LO is
negated. The negation of DC LO negates DEAD.
2.8.8.2 FAIL Function -- A nexus enables the fail (FAIL) signal
asynchronously to the SBI clock, when the power supply AC LO
sign a 1 i s asserted on that n ex us • The ass e rt i on o f FA I L i n h i b i ts
the CPU from initiating a power-up service routine. FAIL is
negated asynchronously with respect to the SB! clock when all
nexus that are required for the power-up operation have detected
the negation of AC LO. The CPU samples the FAIL line following the
po we r-d own routine (assertion of FAIL) to determine i f the
power-up routine should be initiated.

UNJAM
Function
The
unjam
function
restores
(initializes) the system to a known, well-defined state. The UNJAM
signal is asserted only by the CPU or console, and is oetected by
all nexus connected to the SBI. The console asserts UNJAM only
when a console key (or sequence) is selected. The duration of the
UNJAM pulse is a minimum of 15 SBI cycles 2nd is negated at T0.
2.8.8.3

When the console intends to assert UNJAM, the CPU will assert TR00
for a minimum of 15 SBI cycles. The CPU will continue to assert
TR00 for the duration of UNJAM and for a minimum of 15 SBI cycles
after the negation of UNJAM. This use of TR00 ensures that the SBI
is inactive preceding, during, and after the UNJAM operation.

2-43

Each nexus receives UNJAM at T3 and begins a restore sequence. Any
current operation of short duration will not be aborted if that
operation might leave the nexus in an undefined stote. Nexus will
not perform operations using the SB! during the assertion of
UNJAM. In addition, the nexus must be in an idle state, with
respect to SBI activity, at the conclusion of the UNJAM pulse.
While UNJAM is asserted, nexus will not assert FAULT. However, a
nexus asserting FAULT prior to UNJAM must continue to do so to
preserve the content of the nexus configuration/fault status
registers. The restore sequence (UNJAM asserted) should not cause
a nexus to pass through any states that will assert any SBI lines.
All read commands issued before the UNJAM are canceled.
In the event of a power failure during UNJAM, some nexus will
assert FA I L and/ o r DEAD •
The rest o re sequence s ho u 1 d ca use the
nexus to negate ALERT or interrupt requests, but should not clear
any device status bits.

2-44

CHAPTER 3
PROGRAMMING DEFINITIONS AND SPECIFICATIONS
3.1
GENERAL
This chapter describes some of the Massbus signals, clearing
methods, and interrupt conditions; and each bit of the registers
in the MBA.

3.2
DEFINITIONS
Some of the Massbus signals that are used
information are described in this paragraph.

in generating

status

Attention (ATTN) -- The ATTN line is a shared line that
connects from all drives in common to the MBA. Each drive
asserts ATTN (and sets its own ATA bit) whenever it has
an error condition (ERR asserted), has just finished
executing any movement command, or a change in power
condition occurs.
The logical expressions for these statements are:
ATTN= ATA

+ ATA

+ ••• + ATA 7

ATA. = ERR. + completion of a movement command + change
.
i
i d.
.
in
power
con
it1ons.
(i represents the unit select code of a drive, 0--7)
Exception (EXC) -- The EXC line connects from the MBA to
the drive that is performing a data transfer. It is
asserted by the drive if an error occurs during the
transfer. This line is used to distinguish errors in the
drive performing a data transfer from errors signaled by
the ATTN line.
(A drive that is performing a data
transfer never asserts ATTN while the data transfer is
underway.)
End of Block (EBL) -- The EBL line is pulsed by the drive
performing a data transfer at the end of each sector.
Clearing Methods
Bit 00 of the MBA control register is the Initialization
(INIT) bit. The setting (writing a 1) of this bit will:
Clear status bits in the MBA configuration register
Clear abort data transfer on interrupt enable bits in
the MBA control register
Clear MBA status register
Clear MBA byte count register
3-1

Clear the control and status bits of the diagnostic
register
Cancel all pending commands except read data pending
Abort data transfers
Assert Massbus INIT.
3.3
PROGRAMMING NOTES
This paragraph describes miscellaneous features of the RH780. The
tables in subsequent paragraphs describe the other bits of the
MBA. The DT Abort (Data Transfer Abort) bit is located in the MBA
and is associated only with error conditions during data transfers
and error conditions in the MBA. A drive clear command does not
affect the DT Abort bit in the MBA. When DT END clears the DT BUSY
bit in the MBA, it indicates that the MBA is ready for another
data transfer command. To successfully initiate a data transfer
command, DT BUSY must not be asserted and the appropriate drive
ready bit must be asserted. A nondata transfer command can be
issued to a drive any time a drive ready bit is asserted,
regardless of the state of the DT BUSY bit in the MBA.
When a data transfer command is successfully initiated, DT BUSY is
asserted and the drive ready bit is negated. When a nondata
transfer command is successfully initiated, the drive ready bit is
negated but the DT BUSY bit is not asserted.
If any command other than INIT is issued to a drive that has an
error ind i ca tor asserted, the command wi 11 be ignored by the
drive.
If a data transfer command is issued to a drive that has an error
indicator asserted, the drive does not execute the command, the
Missed Transfer Error (MXF, bit 08 of the status register) occurs
in the MBA.
3.4
INTERRUPT CONDITIONS
The MBA generates an interrupt to the CPU due
conditions:

to the

following

upon termination of a data transfer, if the IE bit is set
when the MBA become ready;

upon assertion of ATTN line or the occurrence of an MBA
error, while the MBA is not busy and the IE bit is set;

upon power up.

3-2

3.5

TERMINATION OF DATA TRANSFERS

A data transfer that has been initiated successfully may terminate
in the following ways.

3.6

Normal Termination -- Byte count overflows to 0 and
MBA becomes ready (DT BUSY cleared).

MBA Error -- An error occurs in the MBA status register.
Bit

Error Indication

19
18
17
12
11
10
09
08
07
06
05
04
03
02
01
00

PGE (Program Error)
NED (Non-Existing Device)
MCPE {Massbus Control Parity Error)
DT ABORT (Data Transfer Aborted)
DLT (Data Late)
WCK UP ERR {Write Check Upper Error)
WCK LWR ERR (Write Check Lower Error)
MXF (Missed Transfer Error)
MBEXC (Massbus Exception)
MDPE (Massbus Data Parity Error)
MAPPE (Page Frame MAP Parity Error)
INVMAP (Inv al id MAP)
ERR CONF (Error Confirmation)
RDS {Read Data Substitute)
IS TIMEOUT (Interface Sequence Timeout)
RD TIMEOUT (Read Data Timeout)

the

Drive Error -- An error occurs in the drive.
sets the appropriate error bit in the drive.

The drive

Program-Caused Abort -- By causing !NIT to be asserted,
the MBA aborts all operations and all status and error
information is lost.

MBA REGISTERS

The RH780 contains 8 registers and 256 MAP registers. All
registers in the MBA or in the drives can only be accessed by
longword references and must be longword aligned (on byte 0 of a
given register). An attempt to MOVB or MOVW to or from an MBA
subsystem register will result in a machine check trap. This will
also occur when an attempt is made to MOVL to or from a register
if either bit 0 or bit 1 of the address is a 1. An explanation of
these registers and their functions is provided in subsequent
paragraphs. Table 3-1 lists the various RH780 registers.

3-3

Table 3-1
Massbus
Address
(Hex)

00
01
02
03
04
05
06
07

MBA Registers

I
Register

Mnemonic

Type

Configuration/Status
Control
Status
Vi rtua 1 Address
Byte Counter
Diagnostic
Selected Map
Command Address

CSR
CR
SR
VAR
BCR

Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read only
Read only

SMR
CAR

The eight internal MBA registers contain various configuration,
status, and control information. The addresses of these registers
can be derived from Tables 3-2 and 3-3. Table 3-2 shows the MBA's
base address in respect to its various TR levels. Table 3-3 shows
the byte offset for the registers in the MBA. This byte offset is
added to the MBA's base address to produce a particular register's
address.
Example
The address of the diagnostic register for an MBA with a TR of 8:
Base address from Table 3-2
Byte off set for the DR from Table 3-3
DR address

20010000

~ri11.IT4

Example
The address of the control register for an MBA with a TR of C:
Base address from Table 3-2
Byte off set for the CR from Table 3-3
CR address
Table 3-2 MBA Base Addresses
MBA TR
Level

Console Physical
Base Address

1
2
3
4
5
6
7
8
9
A
B

20002000
20004000
20006000
20008000
2000A000
2000C000
2000E000
20010000
20012000
20014000
20016000
20018000
2001A000
2001C000
2001E000
20020000

D
E
F
10

3-4

20018000
04
200]8004

Table 3-3

3.6.1

Offset from Console
Base Address

Configuration/Status Register (CSR)
Control Register (CR)
Status Register (SR)
Virtual Address Register (VAR)
Byte Counter Register (BCR)
Diagnostic Register (DR)
Selected MAP Register (SMR)
Command/Address Register (CAR)

00
04
08
0C
10
14
18
lA

Configuration/Status Register (CSR)

The configuration/status register is a read/write MBA register
that contains fault status, interrupt status, adapter dependent
status, and adapter code bits. Figure 3-1 illustrates these bits
and Table 3-4 provides an explanation for the various bits in this
register.

322212019

16 15

12 11

08 07

OVER TEMPERATURE
(NOT IMPLEMENTED)

WRITE DATA
SEQUENCE ERROR
UNEXPECTED READ _ ____.
DATA ERROR
MULTIPLE
TRANSMITTER _ _ _ ___,
ERROR

1000 0 0

0 0 0 0 0
SBI PARITY ERROR

04 03

ADAPTOR CODE

---ADAPTOR POWER UP
.__---ADAPTOR POWER DOWN

..._-----TRANSMITTER DURING FAULT
TK-0692

Figure 3-1

Configuration/Status Register

3-5

(CSR)

Table 3-4

Configuration/Status Register (CSR) Bit Assignments

Bit

Set By/Cleared By

Remarks

31 PE
SB! Parity
Error (Fault

Set when an SB! parity error
is
detected.
Cleared
by
power
fail
or
the
deassertion of fault.

The
setting
of
bit
will
this
cause fault to be
asserted on the
SBI for one cycle.

30 ws
Write Data
Sequence
(Fault B)

Set when no write data is
received
(neither
tag =
write data nor ID = write
command
ID)
following
a
write command. Cl eared by
power
fail
or
the
deassertion of fault.

Th e
se t t i ng
of
this
bit
will
ca use fault to be
asserted on
the
SBI for one cycle.

29 URD

Set
when
read
data
is
received and not expected.
Cleared by power fail or the
deassertion of fault.

The
setting
of
this
bit
will
cause fault to be
asserted on the
SBI for one cycle.

Unexpected
Read Data
(Fault C)

Reserved
future use.

28 0
27 MT
Multiple
Transmitter
(Fault D)

Set when the ID on the SB I
does not agree with the ID
transmitted by the MBA while
the MBA is transmitting data
on
the SBI. Cleared by
power
fail
or
the
deassertion of fault on the
SBI.

26 XMTFLT
Transmit
Fault

Set when the SBI fault is
detected at the 2nd cycle
after
the
MBA
transmits
information on to the SBI.
Cleared by power fail or the
deassertion of fault.
3-6

for

The
setting
of
this
bit
will
cause fault to be
asserted on the
SBI.
(The
fault
signal
will
be
asserted
at
the
n
o
r
m
a
1
confirmation time
for one cycle if
the MBA detects
one of the fault
conditions.
The
negation of the
fault
signal
on
the SBI will clear
all
the
fault
status bits. Fault
= Fault A + Fault
B + Fault C +
Fault D.

Table

3-4

Configuration/Status Register
(Cont)

Bit

(CSR)

Set By/Cleared By

25:24 All 0's

Bit

Assignments

Remarks
Reserved
future use.

for

23 PD
Adapter Power
Down

Set when the MBA power goes
down.
Cleared when power
goes up.

The
setting
of
this
bit
will
cause interrupt to
the CPU if IE is
set.

22 PU
Adapter Power
Up

Set when the MBA power goes
up. Reset when power goes
down. Cleared by assertion
o f IN IT, UNJAM , DC L 0 , o r
writing a 1 into this bit.

The
se t t i ng
of
this bit will also
set the IE bit and
interrupt the CPU.

21 OT
Over
Temperature

Al ways 0.

20:08 All 0's

Reserved
future use.

0 7 : 0 0 Ad apter
Code

Each adapter
is
assigned a unique
code identifying
it.
The
MBA
adapter code is:
Bit
<07:00>
=
00100000

3-7

for

3.6.2
Control Register (CR)
The control register is a read/write register that contains the
cont r o 1 bi ts : Inter r up t En ab 1 e , Abo rt , and In i t i a 1 i z a t i on . Thi s
register can put the MBA in the maintenance mode. Figure 3-2
illustrates this register's bits; Table 3-5 provides an
explanation of the bits.

0000

0000 0000

MAINTENANCE MODE
INTERRUPT ENABLE--ABORT-----'
INITIALIZE-----'
NOTE: ALL BITS ARE READNJRITE EXCEPT INITIALIZE WHICH ALWAYS READS AS 0
TK-0693

Figure 3-2

Table 3-5
Bit

Control Register (CR)

Control Register (CR} Bit Assignments

Set By/
Cleared By

Remarks

3 1 : 0 4 Al 1 QJ ' s

Reserved for future use.

03 MM
Maintenance
Mode

The setting of this bit will
put the MBA in the maintenance
mode, which will allow the
diagnostic programmer to
exercise and examine the
Massbus operations without a
Massbus device. When this bit
is set, the MBA will block RUN,
DEM, and assert FAIL to the
Massbus so that all the devices
on the Massbus will detach from
the Massbus. This bit can only
be set if a data transfer is
not in progress.

3-8

Table 3-5

Control Register (CR) Bit Assignments (Cont)
Set By/
Cleared By

Bit

Remarks

02 IE
Interrupt
Enable

Set by writing
a 1 o r power up •
Cleared by
writing 0 or
INIT.

Allows the MBA to interrupt CPU
when certain conditions occur.

01 ABORT
Abort Data
Transfer

Set by writing
l; cleared by
writing 0,
INIT, or UNJAM.

The setting of this bit will
initiate the data transfer
abort sequences that will stop
sending commands and addresses,
and stop the byte counter.
It will also negate RUN, assert
EXC to Massbus, wait for EBL,
set ABORT to 1 at trailing edge
of EBL.
Interrupt CPU if IE bit is 1.

00 !NIT
Initialization

3.6.3

The setting of this bit will:
clear status bits in the MBA
configuration register, clear
ABORT and IE in the MBA control
register, clear MBA stntus
register, clear MBA byte count
register, clear control and
status bits of the diagnostic
registers. It will also Cancel
all pending commands except
read data pending abort data
transfer. Asserts Massbus INIT.

This bit is
self-clearing
(always reads
as 0) •

Status Register (SR)

The status register is a read/write register that contains MBA
status information such as: error indications, timeouts, and busy
indicators. Figure 3-3 illustrates the bit assignments and Table
3-6 describes the functions of the bits in the status register.
All interrupts will occur immediately if there is no data transfer
in progress.
The interrupt will be postponed until the datn
transfer has terminated.

3-9

3130 29

19181716 15

1312 1110 0908 07060504 03020100

0 0
DATA TRANSFER
BUSY
NO RESPONSE
CONFIRMATION

PROGRAMMING
ERROR
NON EXISTENT _ __.
DRIVE

CORRECTED _ _ __,MASSBUS CONTROL _ __
READ DATA
WRITE ERROR
MASSBUS ATTENTION----DATA TRANSFER COMPLETE------DATA TRANSFER A B O R T - - - - - - - DATA TRANSFER L A T E - - - - - - - - WRITE CHECK-UPPER E R R O R - - - - - - - - -......
WRITE CHECK-LOWER E R R O R - - - - - - - - - - - - '
MISSED T R A N S F E R - - - - - - - - - - - MASSBUS E X C E P T I O N - - - - - - - - - - - - - - '
MASSBUS DATA PARITY E R R O R - - - - - - - - - - - - MAP PARITY E R R O R - - - - - - - - - - - - - - - - '
INVALID M A P - - - - - - - - - - - - - - ERROR CONFIRMATION---------------~
READ DATA S U B S T I T U T E - - - - - - - - - - - - - - - - _ _ .
INTERFACE SEQUENCE T I M E O U T - - - - - - - - - - - - - - - - -.......
READ DATA T I M E O U T - - - - - - - - - - - - - - - - - - NOTE: WRITE 1 TO CLEAR BITS IN
THIS REGISTER EXCEPT BIT 31
WHICH IS READ ONLY.
TK-0698

Figure 3-3

Status Register

3-10

(SR)

Table 3-6

Status Register

(SR) Bit Assignments

Bit

Set By/Cleared By

Remarks

31 DTB USY
Data Transfer
Busy

Set when a data transfer
command is received. Cleared
when a data
transfer
is
aborted.

Read only.

30 NRCONF No

Set when the MBA receives a
no-response confirmation for
the read command or write
command and write data sent
to
the
SBI.
Cleared
by
writing a 1 to this bit or
!NIT.

The
setting
of
this
bit
will
cause retry of the
command.

Response
Confirmation

29 CRD
Corrected
Read Data

Set when tag of read data
received from memory is CRD.
Cleared by writing a 1 to
this bit or INIT.
Reserved
future use.

28:20 All 0's

for

19 PGE

Set when one or more of the
following conditions exists.
Program tries to initiate a
data trans fer when the MBA
is currently performing one.
Program tries to load MAP,
VAR, or byte counter while
the MBA is performing a data
transfer operation. Program
tries to set MBA maintenance
mode during a data transfer
operation. Program tries to
initiate
a
nonacceptable
data
transfer
command.
Cleared by writing a 1 to
this bit.

The
setting
of
this
bit
will
cause an interrupt
to the CPU if IE
bit in the control
register is set.

18 NED
Nonexisting
Drive

Set when drive
fails to
assert TRA within 1. 5 us
after
assertion
of
DEM.
Cleared by writing a 1 to
this bit.

The
setting
of
this bit will send
zero
read
data
back to the SB I,
and interrupt the
CPU if IE bit in
the
control
r eg i st er i s set •

3-11

Table 3-6

Status Register (SR) Bit Assignments (Cont)

Bit

Set By/Cleared By

Remarks

17 MCPE
Massbus
Control
Parity Error

Set when Massbus control
parity occurs. Cleared by
writing a 1 to this bit.

Th e
set t i ng
of
this
bit
will
cause an interrupt
to CPU if the IE
bit in the control
register is set.

16 ATTN
Attention
from Massbus

Set when the attention line
in the Massbus is asserted.

The
setting
of
this
bit
will
cause an interrupt
to the CPU if the
IE
bit
in
the
control
register
is set.

1 5 : 14 Al 1 0 ' s

Reserved
future use.

for

13 DT COMP
Data Transfer
Completed

Set when data transfer
completed.
Cleared
writing a 1 to this bit.

is
by

Th e
s e t t in g
of
this
bit
will
cause an interrupt
to the CPU if the
IE
bit
in
the
control
register
is set.

12 DTABT Data
Transfer
Aborted

Set with the trailing edge
data
the
of
EBL
when
transfer has been aborted.
Cleared by writing a 1 to
this bit or !NIT.

Th e
set t i ng
of
this
bit
will
cause an interrupt
to the CPU if the
IE
bit
in
the
control
register
is set.

11 DLT Data

This bit is set : 1) for
either a write data transfer
or
a
write
check
data
transfer providing the data
buffer is empty when WCLK is
sent to the Massbus, 2) for
a
read
data
transfer
providing the data buffer is
full when SCLK is received
from the Massbus.

The
setting
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

Set when a compare error is
detected in the upper byte
while the MBA is performing
a write check operation.
Cleared by writing a 1 to
this bit or INIT.

The
setting
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

Late

10 WCK UP ERR
Write Check
Upper Error

3-12

Table 3-6

Status Register (SR) Bit Assignments (Cont)

Bit

Set By/Cleared By

Remarks

09 WCK LWR
ERR Write
Cheek Lower
Error

Set when a compare error is
detected in the lower byte
while the MBA is performing
a write check operation.
Cleared by writing a 1 to
this bit or INIT.

The
setting
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

08 MXF Missed
Transfer
Error

Set when no OCC or SCLK is
received within 50 us after
data transfer busy is set.
Cleared by writing a 1 to
this bit or INIT.

The
sett in g
of
this
bit
will
cause an interrupt
to the CPU if the
IE
bit
in
the
control
register
is set.

07 MBEXC
Massbus
Except ion

Set when EXC is received
Cleared by
from Massbus.
writing a 1 to this bit or
INIT.

·r h e

06 MDPE
Massbus Data
Parity Error

Set when a
Massbus data
parity error is detected
during a read data transfer
operation.
Cleared
by
writing a 1 to this bit or
INIT.

·rhe
setting
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

05 MAPPE Page
Frame Map
Parity Error

Set when a parity error is
detected on the data read
from the map during a data
transfer. Cl ea red by writing
a 1 to this bit or !NIT.

of
setting
The
this
will
bit
data
cause
the
transfer
be
to
aborted.

04 INVMAP

Set when the valid bit of
the next page frame number
is zero and the byte counter
Cleared by
is not
zero.
writing a 1 to this bit or
INIT.

The
setting
of
will
this
bit
cause
the
data
be
transfer
to
aborted.

Invalid Map

3-13

se t t i ng
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

Table 3-6

Status Register (SR) Bit Assignments (Cont)

Bit

Set By/Cleared By

Remarks

03 ERR CONF

Set when the MBA receives
error confirmation for a
read
write
or
command.
Cleared by writing a 1 to
this bit or !NIT.

of
The
setting
this
bit
will
data
cause
the
transfer
to
be
aborted.

Set when the TAG of the read
data received from memory is
read
data
substitute.
Cleared by writing a 1 to
this bit or !NIT.

Th e
se t t i ng
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

Set
when
an
interface
sequence timeout occurs. An
interface
sequence timeout
is defined as the time from
when arbitration for the SBI
is begun until:
1)
ACK is received for a
command
address
transfer
that specifies read; or
2) ACK is received for a
command/address
transfer
that specifies write and
write data; or
3)
ERR
confirmation
is
received
for
any
command/address
transfer.
The maximum timeout is 102.4
us. Cleared by writing a 1
to this bit or !NIT.

The
setting
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

Set when a read data timeout
occurs. A read data timeout
is defined as the time from
when an interface sequence
that
specifies
a
read
command is completed to the
time that the specified read
data
is
returned to the
commander.
The
maximum
timeout is 102.4 -s. Cleared
by writing a 1 to this bit
or !NIT.

The
setting
of
this
bit
will
cause
the
data
transfer
to
be
aborted.

Error
Confirmation

02 RDS Read
Data
Substitute

01 IS TIMEOUT
Interface
Sequence
Timeout

00 RD TIMEOUT
Read Data
Timeout

3-14

3.6.4
Virtual Address Register (VAR)
Before a data transfer is initiated, the program must load an
initial virtual address (pointing to the first byte to be
transferred) into this register. Figure 3-4 illustrates the bit
assignments for the virtual address register. Bits 09 through ir,
select one of the 256 MAP registers. The contents of the selected
MAP register and the value of bi ts 00 through 08 are used to
assemble a physical SBI address to be sent to memory. Bits 00
through 08 indicate the byte offset into the page of the current
data byte . The v i rt u a 1 add res s reg i st e r may not be wr i t ten into
during a data transfer. An attempt to do so will set PGE, but the
virtual address register will not be modified and the data
transfer will continue.
NOTE
The MBA virtual address register is
incremented by eight after every memory
read or write and will not point to the
next byte to be transferred if the
transfer does not end on a quadword
boundary (it will point eight bytes
ahead). When a write check error occurs,
the virtual address register will not
point to the failing data in memory due
to the preloading of the silo data
buffer. The virtual address of the bad
data may be found by determining the
number of bytes actually compared on the
Massbus (the difference between bits 16
to 31 of the byte count register and
their initial value) and adding that
difference
to
the
initial
virtual
address.

28r7 24i23 20 19

lo o o o o o o o o o o o1o o o

1sr5
MAP POINTER

001
PHYSICAL PAGE BYTE
ADDRESS
TK-0696

Figure 3-4

Virtual Address Register

3-15

(VAR)

3.6.5
Byte Count Register (BCR)
The program loads the 2' s complement of the number of bytes for
the data transfer to bits 15 through 00 of this register. The MBA
hardware will load these 16 bits into bits 31 through 16 and bits
15 through 00 of the byte count register. Bits 31 through 16 serve
as the byte counter for the number of bytes transferred through
the Massbus and bits 15 through 00 serve as the byte counter for
the number of bytes transferred through the SB! interface. The
starting byte count with 16 bits of zeros is the maximum number of
bytes of a data transfer. Figure 3-5 illustrates the byte count
register's bit assignments. The byte count register may not be
modified during a data transfer. An attempt to do so will be
ignored and PGE will be set.

Cl
SBI BYTE COUNTER
(READ/WRITE)

MASSBUS BYTE COUNTER
(READ ONLY)
NOTE: D.ATA WRITTEN INTO THE
SBI BYTE COUNTER IS COPIED
INTO THE MASSBUS BYTE
COUNTER.

Figure 3-5

2's COMPEMENT OF THE
NUMBER OF BYTES TO BE TRANSFERRED

TK-0697

Byte Counter Register

(BCR)

3.6.6
Diagnostic Register (DR)
The diagnostic register is a read/write register that contains MBA
diagnostic information. This register allows diagnostics to be run
without any drives on the Massbus. Figure 3-6 illustrates the bit
assignments, and Table 3-7 describes the function of the various
bits in this register. The diagnostic register may not be written
unless the MBA is in the maintenance mode. An attempt to write the
diagnostic register when not in the maintenance mode will be
ignored. Caution should be exercised when reading this register in
the maintenance mode. The data path used to read bits 00 through
07 may inject invalid data into the silo if the MBA has just read
data from memory.
It is advisable to wait 20 us from the
initiation of a transfer or the deassertion of SCLK before reading
or modifying this resister.
3-16

24 2322 21

16 15

MASS BUS
DRIVE
SELECT
(READ ONLY)

INVERT MASSBUS----'
DATA PARITY
INVERT MASSBUS _ ______.
CONTROL PARITY
INVERT MAP PARITY-----'

MASSBUS REGISTER SELECT
(READ ONLY)

BLOCK SENDING - - - - - COMMAND TO SBI
SIMULATE SCLK

SELECTED MDIB (READ ONLY)

SIMULATE EBL - - - - - - - - - '

(VALID DURING MAINTENANCE

SIMULATE OCC - - - - - - - - - - '

MODE ONLY)

SIMULATE A T T N - - - - - - - - - - '
MDI B SELECT
MASSBUS FAIL (READ O N L Y ) - - - - - - - - - - '
MASSBUS RUN (READ ONLY)
MASSBUS WCLK (READ O N L Y ) - - - - - - - - - - - '
MASSBUSEXC(READONLY)-------------'
MASSBUSCTOD(READONLY)-----------~---'

NOTE: BITS 21AND22 ARE READ/WRITE
FOR DIAGNOSTIC TEST PURPOSES
ONLY
TK-0694

Figure 3-6
Table 3-7
Bit

Diagnostic Register

(DR)

(DR) Bit Assignments

Description

IMDPG

Invert Massbus Data Parity Generator.

IMC PG

Invert Massbus Control Parity Generator.

!MAPP

Invert MAP Parity.

BLKSCOM

Block Sending Command to the SB I. During a
data transfer, the setting of this bit will
eventually cause a DLT bit set and a DT
ABORT.

SIMSCLK

Simulate SCLK. When the MM bit is set,
writing a 1 to this bit will simulate the
assertion of SCLK; writing a 0 to this bit
will simulate the deassertion of SCLK.

3-17

Table 3-7

Diagnostic Register (DR) Bit Assignments (Cont)

Bit

Description

SIME BL

Simulate EBL. When MM bit is set, writing a 1
to this bit will simulate the assertion of
EBL; writing a 0 to this bit will simulate
the deassertion of EBL.

SIMOCC

Simulate OCC. When MM bit is set, writing a 1
to this bit will simulate the assertion of
OCC; writing a 0 t'o this bit will simulate
the deassertion of acc.

SIMATTN

Simulate ATTN. When MM bit is set, writing a
1 to this bit will simulate assertion of
ATTN; writing a 0 to this bit wi 11 simulate
the deassertion of ATTN.

MPIB SEL

Maintenance Massbus Data Input Buffer Select.
When this bit is set to a 1, the upper eight
bits (B<l5:08>) of the MDIB will be sent out
f r om bi ts 0 7 th r o ugh 0 0 of the d i a g nos t i c
register if the diagnostic register is read.
When the bit is 0, the lower eight bits
(B<07:00>) of the MDIB will be sent out from
bits 07 through 00 of the diagnostic register
if it is read.

2 2: 21

MAINT ONLY

Read/write with no effect.
writability of these bits.

Used to test the

MFAIL

Mass bus Fa i 1 ( r ea d on 1 y) •
when MM is set.

Fa i 1

MRUN

Massbus Run (read only).

MWCLK

Massbus WCLK (read only).

MEXC

Massbus

NCTOD

Massbus METOD (read only).

15: 13

MDS

Massbus Device Select (read only).

12:8

MRS

Massbus Register Select (read only).

7:0

U/L MDIB

Maintenance Upper/Lower MDIB.

EXC

(read only).

3-18

ass e rte d

3.6.7
Selected MAP Register (SMR)
This register is read-only and has the same format as a MAP
register {Paragraph 3.6.9) but is valid only when DT BUSY is set.
This is the contents of the MAP register pointed to by bits 16
through 09 of the virtual address register. Figure 3-7 illustrates
the bit assignments of the selected MAP register.
3.6.8
Command Address Register (CAR)
This register is read-only and valid only when DT BUSY is set. It
contains the value of bits 31 through 00 of the SBI during the
command/address part of the MBA's next data transfer.
3.6.9
MAP Registers
The MBA contains 256 MAP registers, each of which may be selected
by address bits 00 to 07. Bit 31 of the MAP registers is a valid
bit, bi ts 30 through 21 are all 0 's {intended for future use) , and
bits 20 through 00 represent the physical page frame number. Bits
09 and 08 are 1 and 0, respectively. MAP registers can only be
written when there is no data transfer operation in progress. A
write to a MAP register while a data transfer is in progress will
be ignored and cause the setting of PGE and interrupt the CPU at
the end of a transfer if IE is set. Figure 3-7 illustrates the bit
assignment of the MAP registers.

PHYSICAL PAGE FRAME NUMBER

VALID BIT

TK-0715

Figure 3-7

MAP Registers

3.7
DRIVE REGISTER CALCULATIONS
The registers within a drive contain various drive information.
The address of a particular register in a drive is dependent on
the drive's unit number and the assigned TR level of the MBA that
controls the drive(s). To calculate the address of a register,
follow the procedure outlined below.
1.

Obtain the base address of the MBA from Table 3-2.

Locate the desired register number and drive number for
the d r i v e reg i st e r from Tab 1 e 3 -8 • The i n t e rs e c t i on o f
the row and column will be the register offset.

Add the MBA base address to the register offset to obtain
the register address.
3-19

Example
To determine the address of register number 02 in drive number 04
with an MBA with a TR level of 08:
MBA base address
Intersection of register and drive number
Register 02 in drive number 04

20010000
608
20010608

Since Massbus drive registers are only 16 bits wide, the following
convention has been adopted.

On writes only, the low 16 bits of the longword will be
written.

On reads, the drive register will supply the low 16 bits
and the MBA's Status Register (SR) will supply the upper
16 bits (8<31:16> of the SR) when a drive register is
read.
Table 3-8

Drive Address Conversion

MBA Base Address + (Value from table below)
Register
00
01
02
03
04

05
06
07
08
09
0A
0B
0C
00
0E
0F

= register address

Drive Number
0
1
2

480
484
488
48C
490
494
498
49C
4A0
4A4
4A8
4AC
480
484
488
48C

580
S84
S88
SSC
S90
S94
S98
S9C
5A0
SA4
SAS
SAC
SB0
S84
S88
SBC

600
604
608
60C
610
614
618
61C
620
624
628
62C
630
634
638
63C

680
684
688
68C
690
694
698
69C
6A0
6A4
6A8
6AC
680
684
688
6BC

700
704
708
70C
710
714
718
71C
720
624
728
72C
730
734
738
73C

780
784
788
78C
790
794
798
79C
7A0
6A4
7A8
7AC
780
784
7B8
7BC

400
404
408
40C
410
414
418
41C
420
424
428
42C
430
434
438
43C

500
504
S08
S0C
Sl0
Sl4
Sl8
SlC
S20
524
528
52C
S30
S34
S38
53C

3-20

CHAPTER 4
MBA FUNCTIONAL/LOGIC DESCRIPTION
4.1
GENERAL
This chapter provides a functional description of the RH780
Massbus Adapter. Logic descriptions are included in subsequent
paragraphs, where necessary, to clarify operation of the MBA. The
chapter is divided into four sections: MBA/SBI interface, internal
registers, data paths, and control paths. The reader should be
familiar with the material in the preceding chapters and the
timing diagrams in the RH780 Field Maintenance Print Set (REV B or
later). The print set will be referenced throughout this
discussion. Figure 4-1 is a block diagram of the RH780 Massbus
Adapter.
4.2
MBA/SB! INTERFACE
The MBA/SBI interface accepts information from the SBI when it
recognizes itself as the intended receiver. Figure 4-2 is a block
diagram of the interface. The various components of the interface
are discussed in the following paragraphs.
4.2.l
SBI Decoding and Validating (Overview)
CPU transfers to or from MBA (or drive) registers require one or
two successive SBI transfer cycles. The first cycle always
contains the command/address. The second contains the data word if
the command was a write.
The command/address placed on the SBI data lines by the CPU at T0
is loaded into the SBI/MBA transceivers between T2 and T3 and
latched at T3. The time lapse between assertion and latching of
the input in the transceivers provides deskew and settling time to
compensate for any propagation delays on the SBI.
The parity of the latched information is then checked and the TAG
field
is
decoded.
If
the
tag
is
determined
to
be
a
command/address, the SBI address B<l4:11> is compared with the
preselected MBA device address to determine if the MBA is the
intended recipient of the SBI command. If the address is not the
MBA's, the information will not be processed, nor will the MBA
issue a conf i rrnat ion (no response). In this case, the inter face
circuits will continue to check the SBI data lines during the
following SBI cycles until a valid command/address is latched.
The MBA only recognizes the following SB! commands: write masked,
interlocked write masked (entire longword only), read masked,
interlocked read masked, and interrupt summary read.
If the MBA recognizes the address and is not performing another
SB! data transfer operation (MBA BUSY is not asserted) and the
mask and function bits indicate a valid command, the MBA will
issue an ACK confirmation to the CPU verifying that the
command/address has been received correctly. Confirmation occurs
two cycles after receipt of the command/address.
4-1

MBA/SBI INTERFACE
M8275 SLOT I

MBA INTERNAL REGISTERS
M8276 SLOT 2

INT BUS
DRIVERS
..------~--~---,----....,.-----,y. (TRI-STATE) 1-----.

Iu
I
II

....______,MSI

MIR

ADDRESS/

CONTROL
STORE
FUNCTION t--R_IW_C_M_D,---------1-"'~ (REG SEL

CHECK
MSI

L.____._

.--

MIR
......-

DRIVE SEL
INT/EXT)
MIR

MSI

SBI
1-XCEi VER/
LATCH

VALID
ISR

ADDRESS t------...
REGISTER

.,i::..
I

REQ OK----t-+

MIR

MSI

L.:J
l

•

MSI

CONFIRM

LOGIC
~NF
(TRANSMIT)

-iBusv

___

i- -

....._---------------+--1-~ (RECEIVE) ~ 1
.....__

VALID ISR

INT BUS

I A___J\.

MUX

I ,..,,.

MSI

INT BUS

M_s_1_~

~RETRY

rKv
I

MIR

MAP

=Jl
___ lJvvvl
I
CMD/ADRS

MUX SEL

[ AND ENAB
MOP

OUTPUT DATA MUX
(8:1 TRI-STATE)

"' z

MIR

1/1-.. ---------------------~--------

v I RECEIVERS ""'

___

MIR

ID
CHECK

..___..

VIRTUAL

--""--STROBE RS I INTERNAL
REGISTER
~ OPERATION

INTERNAL
CONTROL/ - - - - - - - - .
STATUS
REGISTERS t - - - - - - - - .

,-----

REG SEL

...__.,......MSI_,l+-t-

RECEIVERSi-------.

MSI

DECODE

INT BUS

CONTROL
STORE
(R/W,ID)

TAG

INTERNAL BUS (TRI-STATE)

MSI

ISR DATA
Tl(.0719

Figure 4-1 MBA Block Diagram
(Sheet 1 of 2)

MASSBUS DATA PATHS
M8277 SLOT 3

MASSBUS CONTROL PATHS
M8278 SLOT 4

INTERNAL BUS (TRI-STATE)

INT BUS
RECEIVERS

MOP

MASSBUS
DATA IN
BUFFER

MCP

MASSBUS
CONTROL

MCP

MUX
2:1

MOP
~

WRITE
CHECK
COMPARE

MASS BUS
XCEIVERS
(CONTROL
PATH)

XCEi VE RS
(DATA PATH

s:
)>

MCP

MOP

MASS BUS
CONTROL
PATH OUT
MCP

(/)
(/)

l:XI

(/)

SILO

MOP
MASSBUS
OUTPUT
MUX

DATA
OUT
BUFFER

(4 : 1) MOP

MASSBUS
DRIVE/REG
SEL
(TRI-STATE)
MCP

MASSBUS
CONTROL
PATH IN
(TRI-STATE)
MCP

MASS BUS
CONTROL
ENAB
MCP

MOP

OUTPUT DATA MUX
(2:1 TRI-STATE)
MOP

MUXSEL
AND ENAB
MIR

INTERNAL BUS (TRI-STATE)
TK-0720

Figure 4-1 MBA Block Diagram
(Sheet 2 of 2)

DRIVERS 1----+7
_____
.--~~~~.--~~--,-~~-r-~----ir--~-r--~~~~--~,/~
(TRI7
BYTE
INT BUS

110

SAVED ID --+I

ID
CHECK

HARDWIRED ID ---+

MSIF

PARITY

PARITY
CHECK

IDOK
t---

ADRS
CHECK
MSID

MSIC

-c=

1
XMIT
CYCLE
MSIL

FAULT

..----"•'---

FUNCTION

TAG

1----------i~M

XCEIVERS/~

RCONF

1-----------.

MSIA,B
TCLK (MSIR)

,--. FUNCTION
DECODE

DECODE

(MIR) COMMAND READY -

MSIN,P

READ/
WRITE
~

t
ID

MSI CONT~OL STORE

MSIE

MSIE I
VALID CMD

MSIM

i==... SAVED ID
--CLK VALID CMD (MIR)

R/W

r-------r----t----'------t-------------------~WRITEFCN(MIR)

MSID, E i-1------i---r----+------t-C-S_R_E_A_D_/W_R_IT-E-------------CLK EXT CMD (MCP)
C/A
ISR

VALID
ISR

, - - - - - I " - - - - - WO (MIR)

MSIF, L

RD
t--

EXP
WO
0-EXPWD (MIR)
MSIF

WDACK
r--------------------+------_J
EXP
RD
MSIF

~CLKDIB2

r-t-+ CLK DIB1
(MCP)

RD ACK

REQUEST I-- SEND TR
LOGIC
f--+ INT READ REQUEST

CONFIRMATION
LOGIC

f-+ EXT READ REQUEST...__ _ _ _ _ _M_s_iJ__,

~COMMAND REQUEST

----BUSY
OT R/W (MOP)~ CONF
~
CHECK ~RETRY (MIR)

f~---~

(Ml R)
ARB OK--+

READ
DATA
PENDING

v Litr'\r'

MSIF

f-- ACK
!----+ ERROR

..._~-~--~---------------~-~---------------~-~---~~-'SBIXMIT

<..

INTERNAL
BUS

MSIF

INTERNAL READ READY---+!
(MCP) EXTERNAL READ READY-+!

STATE)

REQUEST
CHECK

.---J

.....~..........•..___.[ .....

TAG

SBI

LATCH

BYTE
MASK
CHECK
MSIF

1______1

J LJ

RCLK (MSIR)

MASK

MBA
BUSY

MSIH

IA DRS

-'-

DATAMUX

l,IL---,
ITT__!

~MSIN,PI

'-------------------------------------------------REQINTR(MIR)

INT BUS
RECEIVERS

MSIN,P

ISRDATA

~ (HARDWIRED)
(FROM TR LEVEL)
TK-0786

Figure 4-2

MBA/SB! Interface

If the MBA is busy, a BUSY confirmation signal is sent to the CPU
in response to the valid command/address. The CPU will then
rearbitrate for use of the SB! and repeat the transmission until
the command/address is accepted or until the CPU times out.
It should be noted that there are two busy indications in the MBA,
DT BUSY and MBA BUSY. DT BUSY indicates that a data transfer is in
progress to or from the storage media. While DT BUSY is set, the
MBA registers may be read and some written. MBA BUSY indicates
that the MBA's SB! interface is in use. While MBA BUSY is
asserted, the MBA will respond with a BUSY confirmation to all
commands issued by the CPU. DT BUSY remains asserted for the
duration of a data transfer (typically 10--100 ms). During a data
transfer, MBA BUSY will be set or reset as the MBA uses the SB! to
transfer 8 data bytes to or from memory in an 8-byte burst.
Typically, MBA BUSY will be set for approximately 1 us and will
remain clear until enough data has accumulated to cause another
transfer (approximately 10 us). While MBA BUSY is clear, the CPU
may access MBA registers.
If the MBA recognizes the address but the command is invalid, an
error confirmation will be issued two cycles after receipt of the
command/address causing the CPU to abort the attempted transfer.
After receipt of the command/address, the appropriate MBA BUSY
and/or the expected write data flip-flop is set, depending on the
read/write function to be performed. These functions will be
described later.
Note that the parity checking, decoding, and validation functions
described in the following paragraphs are performed in parallel by
the SB! interface.
4.2.2
Timing (MSIR)
All data transfers between the SBI and the MBA are synchronized by
six timing signals: BUS SB! TP H, BUS SBI TP L, BUS SB! PCLK H,
BUS SB! PCLK L, BUS SB! PDCLK H, and BUS SB! PDCLK L. These timing
signals are generated by the CPU. The MBA uses these timing
signals to derive four SB! time states: T0, Tl, T2, and T3. These
derived time states define an SBI cycle (200 ns). The major MBA
timing signals and their relationship to the SBI timing is
illustrated in Figure 4-3. These signals are used to synchronize
MBA operations with the SB!.
4.2.3
SBI Control and Data Transceivers
(MSIA, MSIB)
Information transferred to and from the MBA is loaded and latched
in the control and data transceivers (Figure 4-2) by TCLKA and
TCLKB (T0, transmit) or RCLKA and RCLKB (T2, receive).
The first longword transferred in any SB I/MBA operation is the
command address. When transmitting a command/address or data
longword, the information is loaded in the control and data
transceivers and transmitted to the SBI at the appropriate time.

4-5

I so NS Iso NS I so NS I so NS I so NS I so NS Iso NS I so NS I so NS I so NS I so NS I so NS I
I
I
I
I
I
I
I
I
I
I
I
I
I
BUSSBI TP H
BUS SBI TP L
BUS SBI PCLK H

SBI
TIMING
SIGNALS

BUS SBI PCLK L --,"-.....:...-_....._,
BUS SBI PDCLK H

__,

BUS SBI PDCLK L
MSIR INT DIF TO CLK H
ECL LEVELS

MSIR INT DIF TO CLK L
I

M~R INTDIFTl CLKH ---~~~-~-~-~~!o--~---~~!o--~~-MSIR INT DIF Tl CLK L

MSIR INT DIF T2 CLK H
MSIR INT DIF T2 CLK L
MSIR INT DIF T3 CLK H
MBA
TIMING
SIGNALS

LJ
I

in
I

1
•

~~~-µ

~---~~'~-

in._____
I

•

µ
I

MSIR INT DIF T3 CLK L
MSIR, MIRV, MDPW, MCPK TOH, MSIR RCLK H
I

MSIR, MIRV, MDPW, MCPK Tl H

r---1

_ _:,...____,!

'"---;.....--~___,

_.n
I
I
.,..,-----I

MSIR, MIRV, MDPW, MCPK T2 H, MSIR RCLK H - - - - - - - '_
MSIR, MIRV, MDPW, MCPK T3 H
MSIR INT BUS OCLK H
MCPK INT BUS ICLK L
MSI R STROBE MAP H

-----~11~
I

TTL LEVELS

_____. . .n"""______n!o-__, ____
l

I
I
I
I
I
.__.;..1_
TO
Tl
T2
T3
TO
Tl
T2
T3
TO
:___sBI CYCLE _ _
.. ...
,' • _ _ SBI CYCLE
I
111
1200 NS
200 NS
1•

II I

_.;..1...1
l
I
Tl
T2
T3
TO
SBI CYCLE__
200 NS
---.,

TK-0781

Figure 4-3

Internal Timing

When a command/address is received, it is checked for parity
errors and decoded to identify the format of the information
transferred, establish the function to be performed (read, write
or
interrupt summary read) ,
and
identify the source and
destination of the data.
4.2.4
Parity Error Checking (MSIC)
The parity check provides a means of detecting single-bit errors
in incoming information. Figure 4-4 shows how the parity bits are
decoded. Each control field is parity checked to produce a single
parity bit; each byte of the address is parity checked to produce
two parity bits. These bits are configured so that the contents of
the control and data fields, plus their parity bits, will always
have an even number of bits (even parity). Any control field or
data longword containing an odd number of bits is assumed to be in
error.
If there are no parity errors I CNTRL PAR OK H and DATA PAR OK H
wi 11 be generated . These s i g n a 1 s , toge the r w i th o the r v a 1 i d a t i on
signals, verify the incoming information and enable other
interface circuits to continue processing the command/address or
data.

RECSBI PARO H - - - - - - - .

TAG
CONTROL .,..__.,. CNTR L PAR ERR H
PARITY
- - - CNTRL PAR OK H
CHECK

ID
MASK

RECSBI PAR 1 H - - - - .
PARITY
FROM
SBI
DATA
RECEIVERS
(4 DATA BITS
PER PARITY BIT)

DATA
PARITY
CHECK

8 BITS

- - - DATA PAR ERR H
- - DATA PAR OK H

TK-0760

Figure 4-4

Parity Check (MSIC)

4-7

If a parity error is detected, the parity check circuit produces a
fault indication CNTRL PAR ERR H or DATA PAR ERR H, depending on
the source of the error. Either signal wi 11 inhibit the tag and
function decoding {preventing the MBA from recognizing the
command) and set the configuration/status register parity fault
f 1 a g ca us in g ass e rt ion of the fa u 1 t 1 in e to the CPU • The CPU
continues to assert fault until the program examines the fault and
negates the condition. (Refer to Translation Buffer, Cache and SBI
Control Technical Description, EK-MM780-TD-001.)
4.2.5
Tag Decoding (MSID)
If no parity errors are detected, the MBA decodes the tag field.
The tag field identifies the type of ihformation transferred over
the SBI and the relationship of the ID and data fields. The tag
field also functions in conjunction with the mask field to define
special read and write conditions.
The decoding of the tag field is accomplished by a 3-to-8 1 i ne
decoder (Figure 4-5). The decoder is enabled provided an MBA
transfer is not in progress (NOT USING SBI L and XCYCLE L are not
asserted) , and there are no parity errors. Tag bi ts <2: 0> are
decoded to produce one of four outputs: READ DATA, WRITE DATA,
CMD/ADRS, and !SR (Interrupt Summary Read). The tag is decoded
{provided a parity error did not occur) during every SBI cycle.
When a command/address is received, the tag decoder generates
CMD/ADRS H. This signal is sent to the confirmation circuit.
Further decoding and validation checks are then performed. If the
decoded tag indicates the read data, write data, or an ISR, the
appropriate output will set the corresponding flip-flop preparing
the MBA for execution of the first data longword during the next
SBI cycle.
4.2.6
Address Validation (MSID)
Address validation determines if the address received from the SB!
corresponds to that assigned to the MBA. Figure 4-6 is a
simplified block diagram of the logic. As seen in this figure,
address validation is accomplished by comparing address bits
<14:11> with the preselected TR level (TR SELA:SELD). TR SELA:SELD
corresponds to the ID code identifying the MBA and represents the
arbitration level.
If address bits <14: 11> and TR SELA:SELD do not compare ('#), the
address is inva 1 id and the MBA wi 11 ignore the command. If the
address bits and the TR bits are equal, the comparator produces a
single output (H). This output produces ADRS OK H when ANDed with
REC SBI B 27 H, REC SBI B<l0,27: lS>H (which must be all zeros),
and VALID ADRS H. VALID ARDS H is generated by decoding the
address register selection bits, REC SBI B<09: 03>H, which select
the internal or external register addressed by this command. ADRS
OK H is sent to the configuration logic along with CMD/ADRS H
described in Paragraph 4.2.3.

4-8

NOT USING
SBI L
XCYCLE L

---~~

CNTRLPARERRH---EN

---

WRITE DATA

DATAPARERRH~~-----\..~

ISR
TAG
REC TAG 2 H - - - - - DECODE ___ CMD/ADRS

REC TAG 1 H

-----11

.,_____,~

READ DATA L, H

RECTAGOH - - - - -

TAG
DATA TYPE

ISR

WRITE DATA

1 0

CMD/ADRS

READ DATA

0
TK-0757

Figure 4-5
REC SBI
B<11 :14>

Tag Decoding

(MSID)

COMPARATOR

REC SBI <27> H - - - - - - - - .
FROM
DATA
XCEi VE RS

REC SBI
B<10, 15:26>
(ALL O'S)

COMB
LOGIC

REC SBI
B<03:09>
(REGISTER_.....,.
SELECT)

COMB
LOGIC

ADRSOKL

- - - - V A L I D ADRS H
- - - - I N T OR EXT REGISTER SELECT
'--~~~~MAPADRS
TK-0761

Figure 4-6

Address Validation Simplified Block Diagram
4-9

4.2.7
Function Decoding (MSID)
Since the MBA will only respond to longword reads or writes, the
mask bits of the command/address from the SBI must be all l's in
order to enable the decoder that generates WRITE FCN H or READ FCN
H, and VALID FCN H or INVALID FCN H. Function bits <31:28> of the
command/address format specify the type of read or write command.
Figure 4-7 illustrates the function decoding process.

If the mask or function bits <31:28> of a command address are not
valid the decoder generates INVALID FCN H, which returns an error
confirmation.
4.2.8
MBA BUSY Generation Logic (MSIE)
MBA BUSY is asserted when the MBA/SBI interface is processing an
SBI command. The busy flip-flop is set upon the successful
completion of the command/address decoding and validation process.
If MBA BUSY is already asserted, a confirmation signal (SEND BUSY
CNF H) is returned and the function is not decoded. Write to
internal register functions complete immediately and do 11ot set
MBA BUSY. MBA BUSY generation logic is illustrated in Figure 4-8.

RECSBI 831 H - - - - - - .

---WRITE FCN H

REC MASK <0:3> H {

1--__,. READ FCN H

DECODE
..--___.. VALi D FCN H
---INVALID FCN H

REC SBI 8 30 H
REC S81829 H - - - - '
REC S81 B 28 H - - - -

DECODED FUNCTION BITS
831

830

829

828

WRITE FCN

READ FCN
READ FCN

0
1

0
TK-0762

Figure 4-7

Functioning Decoding

4-10

(MSID)

REC BUSY CMD H - - J

Tl L

~"1----.--CMD BUSY L

CK
----MBA BUSY H

INIT COND L

RESET
LOGIC

SEND BUSY CNF H

VALID FCN H
CMD/ADRS H
ADRSOKH--

TK-0759

Figure 4-8

MBA BUSY Generation

When a valid command/address is decoded, ACK is sent to the SBI,
followed by the assertion of MBA BUSY. When a read has occurred,
MBA BUSY is cleared after the requested data is put on the SBI or
if the SBI was not granted within a specific time period. When a
write has occurred to a drive register, MBA BUSY is cleared 250 ns
after TRA is received. If TRA is not received after a specific
time period, NED is set and MBA BUSY is cleared.
MBA BUSY is not asserted when there is a parity error and we are
expecting write data (EXP WP H and PAR ERR H asserted) or a write
data error (WD ERR H) occurs. WDERR H is asserted when we are
expecting write data, but do not receive it. SEND BUSY CNF H is
asserted
when
MBA
BUSY
is
asserted
and
the
received
command/address has indicated a valid function is tp be performed.

4.2.9
Confirmation Logic (MSIJ, MSIM)
Confirmation logic in the MBA informs the CPU whether or not an
information transfer has been received correctly and, in the case
of a received command/address, if the MBA can process the command.
CNF0 and CNFl are encoded or decoded (depending upon whether the
function is a read or write) to specify one of four responses:
CNFI

CNF!

Response

L
H

H
H

No Response (N/R)
Acknowledge (ACK)
Busy (BUSY)
Error (ERR)

4-11

ACK is the anticipated response to a successful data transfer. ERR
will cause the data transfer to be aborted, and N/R or BUSY will
cause a retry of the data transfer.
When the MBA is the receiving nexus it generates the response.
When the data transfer is from a Massbus storage device to memory,
memory generates
the
response.
During
a
data
transfer,
synchronization of the confirmation codes with the command/address
or data word is accomplished by the cycle flip-flop.
4.2.9.1 Response Generation {MSIM) -- When the MBA receives data
(read or write) it generates a response to the transmitting nexus.
Acknowledge will be generated
(SEND ACK H asserted)
when
information is received correctly. To acknowledge a received
command/address there must be no errors (CMD/ADRS H, ADRS OK H
asserted), the MBA cannot be processing another command (MBA BUSY
cleared), and the command address must specify a valid function
(VALID FCN H asserted). Acknowledgment of write data occurs when
the function specified was a write and was successful (received
write data and CS WRITE FCN Hand WRITE DATA Hare asserted). The
MBA will acknowledge read data if the read data was received
correctly {ID OK H, READ DATA H, and READ DATA PEND H are
asserted). When the received information is not valid, an error
confirmation will be sent to the transmitting nexus. SEND ERR CNF
H will be asserted when the command/address specifies an invalid
function. XMIT MBA FAULT will also be asserted if there is an
error in the write data (WD ERR H), if the MBA receives unexpected
read data (UNEXPECTED RD H), if a parity error occurs (PAR ERR H),
or if the transmited and received IDs are not equal (XMIT/REC ID
EQ L not asserted). A BUSY confirmation will be generated when MBA
BUSY is asserted indicating that the MBA is processing a data
transfer command. Figure 4-9 illustrates the logic used in
response generation.

1--~•

SEND ACK H ---1~

XMIT CHFO H

SEND ERR CNF H ----1~ ENCODE
RESPONSE
SEND BUSY CNF H _..___..
- - - - XMIT CNF1 H
SEND FAULT H

XMIT MBA FAULT H
CLK

CLR

TIB H
PWRF +UNJAM H
TK-0785

Figure 4-9

Response Generation (MSIM)

4-12

4.2.9.2 Confirmation Check (MSIJ) -- When memory generates a
response to the MBA for received data, the MBA must be able to
interpret the response in order to react to the transfer. If the
data transfer has occurred successfully, WD2 ACK H will be
asserted. If an error in received data was detected by memory, SET
ERROR CNF L will be asserted. The MBA will retry to transfer (SET
RETRY L) data if any one of the following conditions exist:
a.
b.
c.
d.

N/R received from memory
No ACK received for the first longword
Memory is BUSY
No ACK received for the second longword.

The MBA will retry until a timeout occurs or data late is received
from memory.
CLR C/A XCYC L is asserted to clear transfer status within the
MBA. This will occur when a data transfer retry occurs or an error
occurs in the data transfer. One of the following conditions will
assert CLR C/A XCYC L:
a.
b.
c.
d.

ERR occurs during the transfer
Memory is BUSY
N/R received from memory
No ACK received for the first longword.

SET N/R CNF L indicates that no response to the data memory
requested has been received by the MBA. SET N/R CNFL is asserted
when any of the following conditions exists:
a.
b.
c.
d.

No ACK received for the first longword
CPU did not ACK requested data
N/R received from memory
No ACK received for the second longword.

REQ COMPLETE L will be asserted when the data transfer requested
is complete or when a nonrecoverable error occurs. Figure 4-10 is
a simplified diagram of the logic that performs the confirmation
check.
4.2.10
Interface Fault Assertion
Faults that occur during the SBI decoding and validation process,
such as parity and unexpected read data, set a corresponding
interface fault flip-flop. This output sets the appropriate bit in
the configuration/status register and asserts the SBI fault line.
The fault line will remain asserted until the program examines the
fault status bits and negates the fault. Paragraph 3.6.1 provides
an explanation of the various faults.

4-13

REC CNF 1 H

REC CNF OH

_..,

COMBINATIONAL
LOGIC USED
TO DECODE
MEMORY
CONFIRMATION

----_..,

REO COMPLETE L
WD2 ACK H
SET N/R CNF L
SET RETRY L
CLR C/A XCYC L
SET ERROR CNF L

TK-0784

Figure 4-10

4.2.11

Confirmation Check

Request Logic (MSIK)

When requesting control of the SBI to respond to an internal read,
external read, or to transfer data the request flip-flop produces
C URRE NT RE Q H ( ind i cat in g t ha t an SB I ope rat i on i s to o cc u r) ,
wh i ch sets the TR send f 1 i p- flop • It s o u t put , SEND TR H , i s
applied to internal register arbitration logic, which causes the
assertion of the MBA's assigned TR level at T0 of the following
SB! cycle. If the MBA's arbitration line represents the highest
priority, the internal register arbitration logic issues ARB OK,
allowing the MBA to assume control of the SBI. The combination of
SEND TR, ARB OK, and the function requested may initiate many
functions such as setting the read data pending flip-flop,
starting the timeout operation, and control and transfer functions
within the internal registers, control paths, and data paths.
Figure 4-11 is a simplified diagram of the logic used to
ace om pl i sh this.

4.2.12

Timeout Logic (MSIH)

Interface sequence timeouts and read data timeouts on the MBA are
accomplished by the logic shown in Figure 4-12. The counter
consists of two 4-bit counters in cascade.
An interface sequence timeout (SET IS TIMEOUT L) can occur when
the MBA is arbitrating for control of the SBI. The counter wi 11
wait up to 512 SBI cycles after an attempt to get the bus (SEND TR
H) before the timeout occurs. A read data timeout can occur only
during a read data transfer. If the read data is not received
within 512 SBI cycles after memory has accepted the read command
(RDPDl H), SET RD TIMEOUT Lis asserted.

4-14

INT RD REQ H
CS WRITE FCN L

EXT RD REQ H -

~ CMD REQ B H

INT RD READY H

+INT RD RE Q
COMBINATIONAL
LOGIC

EXT RD READY H

REQUEST
GENERATION
LOGIC

:XT OP DONE+ TOH MASTER INIT B L

CMD ROY H

~EXTRDRE Q
~

CMD REGA H

•

CMD REO L
CURRENT REO H

RE OU EST
CURRENT
~
FLIP-FLOP
REQ H
TK-0763

Figure 4-11

Request Logic

(MSIK)

CMDREOBH
T3 H

SETIS
TIMEOUT L

CMD REO B H
SEND TR H
RDPD1 H

COMB
LOGIC

CRY

SET RD
TIMEOUT L

T2 H--+
CUP
COUNTER

T 18 H

READ DATA PEND H
TK-0758

Figure 4-12

Timeout Logic (MSIH)

4- 15

4.2.13
Command/Address Generation {MSIM)
The command/address format that consists of a parity, tag ID,
function, and address fields is used to process data transfers
from the MBA to a receiving nexus {memory) via the SBI.
During the command/address, the mask field is encoded to specify
which bytes of data (read or write) are valid. Figure 4-13 is the
logic associated with the mask bits.

BYTE MASK

<1-3:1-0> H

MASK 1
MUX
ALL 1'S

----XMIT MASK 3 H
XMIT
MASK
MUX

DTREADH--+--~

----XMIT MASK 2 H
----XMIT MASK 1 H
1------.XMIT MASK 0 H

BYTE MASK

<2-3:2-0> H

MASK2
MUX
ALL O'S
T1 L

INT RD REO H

SEND TR H

EXT RD REO H

CMDREOAH

---~

ENAB WDL MUX H
TK-0782

Figure 4-13

Mask Generation (MSIM)

4-16

When INT RD REQ L or EXT RD REQ L is asserted it indicates a read
of an internal or external MBA register. This will cause the mask
bits to be all zeros. During a data transfer, where the MBA will
send .~he read command to memory (indicating a write to device DT
READ H cleared; SEND TR Hand CMD REQ AH asserted), the mask bits
will be all l's. During a write to memory indicating a read from
device, mask bits BYTE MASK 1<3:0>H will be selected. These mask
bits indicate which bytes in the first transferred quadword have
val id data. In this case DT READ H, SEND TR H, and CMD REQ A H
will be asserted. ENAB WDI MUX H indicates transfer of the first
data quadword. When this is asserted, BYTE MASK 2<3:0>H is
selected, which indicates which bytes of the second quadword are
valid. The mask bits of the second quadword will be all zeros. The
mask bits are latched through multiplexer at Tl and applied to the
MBA/SB! control transceivers.
The ID field is the identifier for the MBA. The logic associated
with the ID field is illustrated in Figure 4-14. The ID field can
be derived from either of two sources, depending on the operation
to be performed. The first source is the hardwired MBA ID
(TR SEL
A-D H), which is representative of the MBA priority levels
assigned at system build time. This is always available at the ID
select multiplexer input. The hardwired ID is used by the MBA to
talk to memory. The second ID source is the received ID from the
SBI/MBA control transceivers. This is loaded into the saved ID
latch every time the MBA receives a command/address from the SBI
and is applied to the ID select multiplexer. The saved ID is used
to return data to the CPU. ID selection is determined by the state
of CMD REQ. When requesting memory data, CMD REQ is high and the
hardwired ID (TR SEL A-D H) is transmitted, via the SBI/MBA
transceivers. When the MBA is excepting read data from memory, the
received ID is compared with that of the MBA. If the received ID
and the MBA ID compare, the read data has arrived, assuming that
all
other decoding
and
validation
checks
are
performed
satisfactorily. The MBA also monitors the ID on the SB! while it
is asserting data on the SBI. If the received ID and MBA ID are
not equal, the ID equal comparator issues a fault indication
setting the appropriate configuration/status register fault bit
and assert i ng the SB I fa u 1 t 1 in e • The fa u 1 t i s ass er t e d on 1 y i f
the MBA is putting data on the SB! and the ID on the SB! is not
the same as the one the MBA asserted. As in other fault
situations, the fault can be cleared by !NIT or deassertion of the
fault signal.
The tag field is determined by the state of SEND TR H and select
input CMD REQ B. When TR H is high and CMD REQ is low (the MBA is
responding to a CPU read), the encoded output of the tag
multiplexer represents a read data format.

4-17

SEND TR H
XMIT
TAG
MUX

XMITTAG
<2:0> H

CM D REO BH - - - 4 - - - - - - '

RECID4H--REC ID3 H - - -

ID
LATCH
XMIT
ID
MUX

XMIT ID
<4:0> H

REC ID1 H - - - REC IDO H - - - -

CLK

VALID CMD H-___,

HARDWIRED ID
(TR SEL <D:A>H

OPERATION

SEND TR

CMD REO

NONE

READ DATA

H
H

WRITE DATA

COMMAND/ADDRESS
TK-0783

Figure 4-14

Tag and ID Generation (MSIM)

4-18

Conversely (during a data transfer), the tag field represents a
command/address when SEND TR and CMD REQ are both high. When SEND
TR H is low and CMD REQ is high, the tag field represents a write
data format. The tag field remains latched in the tag multiplexer
until receipt of Tl. At this time the tag field is available to be
loaded
into the control
transceivers for subsequent SBI
transmission. The logic associated with the tag field is shown in
Figure 4-14.
4.2.14
Mask Decoding
As seen in Figure 4-15, when the SBI TAG indicates read data and
the ID is that of the MBA, the mask field received from the SBI
specifies the type of read data the MBA has received. There are
three data types: Read Data Substitute, Corrected Read Data, and
Normal Read Data. RD SUBSTITUTE is data in which an uncorrectable
error has occurred. CORRECTED DATA is data in which an error has
occurred but has been corrected. NORMAL DATA is data in which
there has been no error.
4.2.15
Internal Bus and Interrupt Summary Read Logic
INT BUS O CLK H latches data from the internal bus into the
MBA/SBI interface receivers. This occurs independently of the
decoding and validation process described previously. Multiplexers
select the data to be transferred to the SBI, either internal bus
data or Interrupt Summary Response data (ISR RESP<l5:00>H). Data
is transmitted to the SBI only if T/R ENAB A L is asserted for the
internal bus data or T/R ENAB B L is asserted for the ISR data.
Figure 4-16 is a simplified diagram of the logic associated with
the functions.
READ DATA L
READ DATA PENDL

DE CODE

ID OK H-----...SEL C
SEL B
REC MASK 0 H----+---1 SELA

1---~

.--l'--------.
1
I
COMB I
I LOGIC I
L __ J

CLK DIB1

LATCH

:-----f

CLK DIB2
- - - SET CORRECT RD L
t----. SET RD SUB L

REC MASK 3 H
REC MASK 2 H
REC MASK 1 H
MASK
READ DATA TYPE

RD SUBSTITUTE

x x

CORRECTED DATA

NORMAL DATA

TK-0764

Figure 4-15

4-19

Mask Decoding

RCLK

ISR RESP <31 :OO>H

BUS MBA INT
B<31 :O>H

XMIT SBI B<31 :OO>H

INT BUS 0 CLK H

REC SBI
B<31 :OO>L
SO= L INTERNAL BUS
SO = H ISR RESPONSE

a:
UJ

REC SBI B <7:4>H

I-

~
I

<(
a:i
~

BUS SBI

B<31 :OO>H
TRANSCEIVERS ...,.__ _ _.,.

ENB

(/)

:::::>
a:i

MBA/SB I

INTERNAL
BUS
RECEIVERS

A=B
ISR COND H
INTR REO <7:4>H

TCLK

INTERRUPT CPU L

ISR L

SBI TO INT CLK
TK-0808

Figur~

4-16

Internal

Bus

Drive

and

Logic

Interrupt

Summary Read

Data

4.3
MBA INTERNAL REGISTERS
The MBA internal registers store various control and status
information. A description of each register and their function is
provided in Paragraphs 3.7 through 3.7.9 of this manual. A
functional logic description is provided in the subsequent
paragraphs. Figure 4-17 is a detailed block diagram of the MBA
internal registers.
4.3.1
Internal Bus Receivers
Information received from the SBI is processed by the interface
logic and latched into the internal bus receivers on T0 following
their assertion on the SBI by INT BUS ICLK L. Figure 4-18
illustrates the internal bus receivers.
4.3.2
Internal Register Control
Register control logic decodes the command/address to select one
of the internal registers to perform the specified read or write
function. The logic used to accomplish this is shown in Figure
4-19.
Selection of the control path output registers, MAP registers, or
one of the other six internal registers is accomplished by
decoding bits CS B<09:08> to set a corresponding flip-flop. When
an internal register operation is selected, bits CS 8<00:02> are
applied to decoding logic that selects the appropriate register.
The output of the decoding logic is ANDed
enabling the appropriate register clock.

with

CLK

and

It should be noted that only the control register and diagnostic
register (if enabled) can be read or written during the time the
MBA is processing a data transfer. If an attempt is made to write
any register other than these during a data transfer operation,
the PGE (programming error) bit in the status register will be
set. If an attempt to write the MAP register is made, the MAP
register wi 11 not be modified and the data transfer in progress
will continue unaffected.
4.3.3
Configuration,
Control,
Status,
Diagnostic,
and
Command/Address Registers
The logic associated with the configuration, control, status, and
diagnostic registers is not very complex. Each bit, which is
implemented within one of these registers, is associated with its
own flip-flop. The control logic for these registers is composed
of simple gating networks and is self-explanatory upon examination
of the print sets. Figure 4-17 is a functional block diagram of
these registers. The logic and operation of the virtual address,
byte counter, and MAP registers are not as obvious and are
described in the following paragraphs.

4-21

INTERNAL BUS
INT BUS
INTERNAL BUV

/')..

RECEIVERS I------------~~-----------------------------------------------------------------------,

MIRA

1 J_vr..

WRITE FCN~
(MSI)

CONTROL REG SEL
INTERNAL STROBE
STORE
- REGISTER
(DRIVE SEL, INT/EXT OPERATION RS02
REG SEL,
....
/]STROBE
CLK VALID
INT/EXT)
WRITE RS04
1TO
CMD (MSI)·MIRBl-----1
CLEAR
MIR INT CS

(7:0)~

EXPWD
(MSI)
RECWD
(MSI)
FAULT CONDITIONS
(MSI)

-"'

CON FIG
REG
RSOO

REG
RS02
MIRC,MIRD

RSOO
DATA

STROBE
RS05

RS02
DATA

i--ST_R_O_B_E~--1

STROBE
RS01

BYTE
COUNTER
1--RS04
(SB I/MBA)

• ~
MIRJ

MIRH
RS04
DATA

RS05
DATA

ABORT DT/
INTERRUPT
LOGIC

N
REQ I NTR 4
~-----------i-------t
(MSI)

.....
Y20

I
I
1------J

V32

L---

. . '----....... y

t--

,' /
t"'"'

.._

l<J=r,
2·1

~FL-,

___

MIRF

,. . . -

rviux MIR INT

RS06
DATA

cs (7:0)

VAR CNT

DOWN (MOP)

J---VAR BYTE

c:::::J

D
_l

CONTROL
(MOP)
i+-ADRS 0
(HARDWIRED)
L

CMD/ADRS

.---.----..--....----JL,__---il
L
7
_l HARDWIRED
FUNCTIONS
j-+ABORT MB OT
(MOP)

PHYS
__. CMD/ADRS

OT READ
(MCP)

t----• SBI BYTE CNT=O
(MOP)

8 .-------

11 ~~~~Lt-n (MOP)

II
;+-~ LvAR CNT UP
JL
'-~
r-'r-.I
(MOP)

MAP

VALID

VAR BYTE
CNTR L

11 BITS

14.

DATA

(MCP)

VIRTUAL ADRS REG RS03
11 ~;p~p
r - - I r- - --, r. - --, lJ
MAP
11 LOWER I MASS ;+""' VAR VYTE
I POINTER' I ADRS I I BUS J4-t-g~i~~WN

r-+

MIRE
--.----R-S0-1

I J-

.i:..

,.l. RS03

OT BUSY
(MCP)

CONTROL
REG
RS01

11 STROBE

MAP

DIAG
REG
RS05

L--J

GEN PAR
(MSI)

2
1STATUS

!;--- CLK CPO

l_.....1

RS03
DATA

8:1 MUX

MUX SEL
L - . AND ENAB

(TRI-STATE)
MIRR,MIRS
MIRT,MIRU
TRI-STATE
BUS

L - - - - - - - - - - - - - - - - - - - - - ; DRIVER

V/A....._ _ _ _ _ ___,

Ml RW l\..\.~r----------'
TK-0807

Figure 4-17 MBA Internal
Registers

BUS MBA
INT B<31 :OO>H

REC INT B
<31:00> H

8-BIT
LATCHES

CLK
INT BUS ICLK L
TK-0789

Figure 4-18 Internal
Bus Receivers

WRITE FCN H

MB MAINT MODE H--~

1----cs B <07:03> H
SAVED
ADDRESS 1 - - - LATCHES
CS B<02:00> H

CLK DIAG REG H
LOAD BYTE CNTR H
CLK BYTE CNTR L

REC INT B<09:00> H

CLK VAR REG L

CLK VALID CMD H

ADDRESS
DECODE t - - - - - - - - - - - . . i

COMB
LOGI

CLK STATUS REG H
CLK STATUS REG L
.CLK CONTROL REG L
CLK CONF REG H

t--___,_--CLK IR H
CS B<09:08> H

DECODER 1------;..i

F-F

EXP WO H _ _,..___
WRITE DATA L

CLK

1----• CLK MAP H

TK-0803

Figure 4-19 Internal

4.3.3.1 Virtual Address Register -- The virtual address register
(VAR) (Figure 4-20) consists of five synchronous, up/down, 4-bit
binary counters. Its function is to convert the virtual address,
received from the SBI upon initiation of a data transfer
operation, to a physical address pointing to the location of the
first byte of data to be transferred.
Bits VAR BIT<l6:09>H are the map pointer bits that select the page
frame of one of 256 map locations. The map pointer bi ts are
incremented by one each time the physical byte address crosses a
page boundary during a data transfer.
Bits VAR BIT<08:03> are the physical byte address bits specifying
the location of the quadword address within the page. These bits
are incremented each time VAR CNT H is received from the Massbus
data paths indicating that a successful quadword data transfer to
or from memory operation has been completed. Bits VAR<02:00>H are
used to pack and unpack the quadword into bytes.
Note that the map pointer bi ts are applied to two data select
multiplexers. The multiplexers select either VAR BIT<l6:08>H or CS
B<07:00>H.
The purpose of the multiplexer is to provide a means of selecting
the source of map register information, as required, to support
the transfer operation to be performed. When processing a data
transfer, the data busy flip-flop is set and the map pointer bits
from the virtual address register are selected by the multiplexers
to be sent to the maps. When the data transfer busy flip-flop is
not set, the register select bi ts are sent to the map, allowing
them to be read or written directly.
4.3.3.2
MAP Registers -- The 256 MAP registers map virtual page
addresses from the virtual address register into SB! physical page
addresses. This allows for data transfer to and from contiguous
virtual (noncontiguous physical) memory locations. Virtual address
translation (mapping) is described in Paragraph 1.5.1 of this
manual.
A write to MAP register operation is performed when the write
enable (WE) input is low. CS B<09:08>H, when asserted, produce CLK
MAP H (MIRB). If the MBA is not busy processing a data transfer
(DT BUSY L cleared), STROBE MAP H and CLK MAP H generate the two
MAP register enabling signals, MAP WEIL and MAP WE2L. The data REC
INT B<3 l: 00 >H at the DI input of the RAM is loaded into the
location specified by the address bits RAM ADRS<07:00> from the
virtual address register. The parity bit for this data is also
stored in the MAP registers. This information wi 11 be placed on
the internal bus if selected by the internal bus output
multiplexers. The MAP register can be read when MAP WEIL and MAP
WE2L are not asserted. MAP registers are read to check the
validity of the information stored in them.
Figure 4-21
illustrates the MAP register operation.

4-24

CS B <07 :OO> H
SELECT
COUNTER

DT REV H

MUX

RAM ADRS <7:0> L

VAR BIT <16:09> H

REC INT B <16:00> H

VAR CNT H

DT BOSY L

CLK
DN/UP

VAR BIT <08:00>

TO DATA PATH
,____ _ _,.1/0 BUFFER
VAR BIT <2:0> LOGIC

GR TST L
CLK VAR REG L

TK-0804

Figure 4-20

Virtual Address Register

R/W
MEMORY
DO

GEN MAP PARITY H

t--------- MAP PARITY H

R/W
MEMORY
RAM ADRS<7:0>L - - - - (FROM VIRTUAL
ADDRESS
REGISTER)

DO--~-----

RECINTB31H
(VALID BIT)

MAP VALID H
MAP VALID L

R/W
MEMORY
D 0 1 - - - - - - - - - MAP OUT <20:00>H

DI
REC INT B<20:00> H .....____,w_E_ _
MAPWE1L _ ___,__ _ _ _ _ _ _ ___.
MAP WE2L

Figure 4-21

TK-0790

MAP Registers

4.3.3.3 Command/Address Generation -- CMD REQ L indicates that
the MBA is to perform an SB I data transfer operation (read or
write to memory). When this signal is asserted,
OUT MUX
SE L <0 2 : 0 0 >H a r e asserted (MIR P) • These mu 1 t i p 1 e x e r s e 1 e ct 1 in es
indicate that the D7 input of the internal bus output multiplexers
will be selected. DT READ H, MAP OUT<20:00>H, and VAR BIT<08:00>H
are at the D7 input of the multiplexers. The internal bus output
multiplexers generate MBA INT B<31:00>L. A command/address must be
generated by the MBA to memory in response to a data transfer
command. If the data transfer is a read, the MBA must generate an
extended write command to memory. If the data transfer is not a
read
(i.e., write or write check), the MBA must generate an
extended read command to memory. The format of the command address
is shown in Figure 4-22.

4-26

PAGE NUMBER
BIT 31ALWAYS1 } INDICATES
BIT 30 ALWAYS 0
EXTENDED
FUNCTION

QUADWORD
WITHIN THE PAGE
BYTE WITHIN
THE QUADWORD
(ALWAYSO)
TK-0788

Figure 4-22

Command/Address Format

When DT READ H indicating a data transfer read is asserted, MBA
INT B<29:28>L are not asserted (1). When OT READ His not asserted
indicating a data transfer write or write check, MBA INT B<29:28>L
are asserted (0).
The page number specified by MBA INT B<27:07>L is generated from
the MBA MAP register bits MAP OUT<20:00>H (MIRK,L,M,N). The
address of the quadword within the page specified by MBA INT
B<06:0l>L is generated from the virtual address register bits VAR
BIT<08:03>H (MIRF). Only quadwords can be transferred; therefore,
bit MBA INT B00 L must always be zero for a command/address
generated by the MBA.
4.3.3.4 Byte Counter Register -- The byte counter register (BCR),
shown in Fig u r e 4- 2 3 , i s a 3 2- bi t reg i st e r cons i st in g of eight
4-bit synchronous binary counters. The byte count register
ma int a ins a record o f the n um be r o f byte s o f d at a to be
transferred to and from the SB! and the Massbus.
The byte count e r reg i st er i s divided into
counters. Bits BYTE CNT<31:16>H are used as
counter and bits BYTE CNT<l5:00>H are used
counter.

two 16-bit byte
the Massbus byte
as the SB I byte

The SB! byte counter maintains a record of the number of bytes to
be received from the SBI. When performing a write (write check) to
Massbus device, the SB! byte counter is incremented each time a
byte of data is loaded into the silo from the data input buffer.
When the last byte of data is transferred from the SB! to the
silo, the SBI counter carry output sets the SBI BYTE CNTR=0 L
flip-flop and no further data is loaded.

4-27

.--~~~~~~~~~~~~~~~~~----o

t---- MB BYTE CNTR=O L

COUT
CLK BYTE CNTR L
MB BYTE CNT L
COUNTER
CLR CNTR L

BYTE CNT <31 :16> H

CLR
LO

LOAD BYTE
CNTR L _ _____,
.--~~~~~~~~~~~~---1D

t - - - + - - - - . SBI BYTE CNTR=O L

COUT
~

CLK BYTE CNTR L
VAR BYTE CNT L

N
00

REC INT B <15:00> H
BYTE CNT <15:00> H

CLR CNTRL

CLR
LO
CLR CNTR L
OTGO L

LOAOBYTECNTRL-~~-

TK-0787

Figure 4-23

Byte Counter Register

Each time it is written the SBI byte counter is loaded
automatically into the Massbus byte counter. As each word of data
is transferred to the Massbus device, the Massbus byte counter is
decremented twice until the counter equals 0, indicating that the
last byte of data in the silo has been transferred to the Massbus
device. At this time the carry output from the Massbus counter
sets the Massbus counter = 0 flip-flop, RUN is negated, and the
transfer will be completed when EBL is asserted.
When performing a read from Massbus device, the operation of the
byte counter is reversed. The Massbus byte counter maintains a
record of the number of bytes to be received from the Massbus
device and loaded into the silo, and the SBI byte counter
ma int a ins a r ec or d of the n um be r of byte s trans f e r red f r om the
silo to the data output buffers. The Massbus byte counter goes to
zero as data is transferred into the silo. When the data is
transferred to the SB!, the SBI byte counter goes to zero. When
EBL is received and the SBI byte counter is zero, the data
trqnsfer is complete. To read the byte counter register, CS 809 L
and cs 802 H must be asserted and CS B<01:00>H must be clear.

4.3.4
Output Data Multiplexers
The output multiplexer
consists of 32 8-way multiplexers connected in parallel so that
one bit of each of the internal register outputs or control
signals is applied to each of the multiplexers (Figure 4-24).
Selection of the register or control outputs to be asserted on the
internal bus is accomplished by AN Ding control store select ion
bits CS<09,02:00>H with INT RED REQ (internal read), EXT RD
(ex terna 1 read) , or CMD REQ (command request) , depending on the
function to be performed, to produce OUT MUX SEL<02:00>H. The
o u t put comb i n at i on s and co r respond in g data sour c e s e 1 e ct e d are
provided in Table 4-1.
Once data from the output multiplexers is selected, the internal
bus drivers are enabled by ANDing the internal read or data
transfer command request input with SEND TR. Data is transferred
to the internal bus upon receipt of INT BUS O CLK.

4-29

INTERNAL ..,.__ __
OUTPUT
I NT B<31 :OO>L
MULTIPLEXER$...__ _ _ _ __

BUS
DRIVERS

INTERNAL BUS

MUX SEL 0 H
MUX SEL 1 H
MUX SEL 2 H
TR I EN<31 :20>L
INT BOS 0 CLK 4

COMB
LOGIC

TRI EN <19:16>L
TRI EN <15:00> L

SEND TR H
CMD REG L - - - - - - - '
INT RD REO H
EXT RD REO L

Figure 4-24

TK-0791

Output Multiplexers and Select/Enable Logic

4-30

Table 4-1

Internal Bus Output Multiplexer

CMD
REQ L

EXT RD
REQ L

INT RD
REQ H

cs Bits

889 L

MUX SEL
2 1

Data Source
Register

x x x

Co mm and/ Add res s

x x x

MAP

Diagnostic

Byte Counter

Virtual Address

Status

Control

Configuration

x x x

Status*

X =
* =

Don't care.
Only upper 16
control path.

bits

enabled,

4-31

lower

bits

from

Massbus

4.4
MBA DATA PATHS
The MBA data paths transfer data
device. The data paths con ta in
transfers between the 32-data bit
Figure 4-25 is a block diagram of

between the SB! and the Massbus
the silo that smooths out the
SBI and the 16-data bit Massbus.
the data paths.

4.4.1
Command Condition (MDPA)
COMMAND CONDITION H is asserted when the MBA data paths want to
use the SBI to read from or write data to memory. This will occur
during a data transfer to or from a mass storage device. For a
read from device or a write (write check) to device, the following
conditions must exist:
a.

MBA BUSY
transfer;

BLOCK SEND CMD L cleared,
command to memory;

CMD REQ L cleared, is not yet processing this command.

asserted,

the

MBA

processing

enabling

the

MBA

the
to

data

send

Other conditions must also exist for read from device or write
(write check) to device. These conditions are described in the
following paragraphs.
Read from Device
CMD CONDITION H will
conditions exist:

asserted

any

one

the

following

FULL FWD, the data transfer is a read (DT READ H) in the
forward direction (DT FWD H) and DOB7 is full (BYTE MASK
2-3 H);

FULL REV,
direction

DT END FWD, the data transfer is a read (DT READ H) in
the forward direction •. DT FWD H filled some of the data
output buffers but the SBI byte counter is now 0 (SBI
BYTE CNTR L);

DT END REV, the data transfer is a read (DT READ H) in
the reverse direction. DT REV H filled some number of
data output buffers but the SBI byte counter is now 0
(SBI BYTE CNTR L) •

the data is a read (DT READ H) in the reverse
(DT REV H) and DOB0 is full (BYTE MASK 1-0 H);

If a Massbus exception or parity error occurs (MB EXC +MOPE H),
SILO 0 READY L is not asserted, indicating that the MBA will empty
its silo to transfer all data prior to the error.

4-32

MBA INTERNAL BUS
DIAGNOSTIC REGISTER READ(MIR)TRI-STATE
BUS
DRIVERS
MOPE

MDPV,V

CLK DIB1(MSI)
CLK DIB2 (MSI)

DATA TRANSFER
DIRECTION (MCP)
SILO INPUT RESISTER EMPTY LOAD SILO

SBI BYTE CNT=O (MIR)

SILO INPUT BUS DRIVER ENABLE

COMMAND REQUEST
(MIR)

SI LO OUTPUT RESISTER FULL
MASSBUS
TRANSFER SI LO OUTPUT

WRITE CHECK
FUNCTION (MCP)

WCK ERR (MIR)

LOAD DOB'S

LOW3 BITS
VIRTUAL ADDRESS(MIR)

BYTE
MASKS

MASS BUS
DRIVERS

MDPL
MDPU,V
BYTE MASKS (MSI)

MUX-ENABLE (MSI)

MASSBUS
DRIVER
CONTROL
MDPK

OUTPUT
MUX
CONTROL
MOPS
CLEAR DOB PAI RS
32

TK-0806

Figure 4-25

MBA Data Paths

Write (Write Check) to Device
CMD CONDITION H
will be asserted
exist:

the

following

the data transfer

conditions

DT READ L cleared,
device;

DIB2 FULL L cleared, the second data input buffer
ful 1;

READ DATA PEND L cleared, the MBA is not waiting for data
from memory;

SBI BYTE CNT=0
transferred.

L cleared,

the

is not a

MBA has more

read

data

from

is not

4.4.2
Internal Bus Receivers/Buffers
Data from the internal bus is loaded into four 8-bit latches upon
receipt of INT BUS ICLK from the control path clock circuits.
The MBA input buffer consists of two sets of 32-bit latches. Their
function is to control the manner in which the two 32-bit data
words from memory are loaded into the silo for subsequent transfer
to the Massbus. CLK DIBl latches the first SBI data word into the
first data input buffer (DIBl). CLK DIB2 latches the second data
word into the second data input buffer (DIB2). CLK DIB2 H also
increments a 4-bit counter.
The counter is initialized to four and counts down at CLK DIB2 H
to zero I asserting DT WRITE READY indicating that all data path
buffers are full, and the MBA is ready to begin a write/write
check.
Figure 4-26 is a logic diagram of the internal bus
receivers and buffers.
4.4.3
Data Input Buffer Enable (MDPD)
The output of the data input buffer select is used to enable the
eight data input buffers (Table 4-2). Virtual address register
bits VAR BIT<02: 00>H point to the data buffer where the data is
stored. The virtual address register is incremented by VAR BYTE
CNT L (MDPA). When the function is a write (write check) and the
fill silo operation is initiated (LOAD SILO H), the data input
buffers are enabled sequentially onto the silo data input bus. The
data input b u ff er s a r e d i s ab 1 ed at T 1 wh i1 e VAR B ITS < 2 : 0 > a r e
changing. Figure 4-27 is a diagram of the data input buffer enable
logic.

4-34

INPUT
BUFFER
DIB1

INPUT
BUFFER
OIB1

INTERNAL
BUS
RECEIVERS
BUS MBA
INT
B <31 :24> ~

INTERNAL
BUS
RECEIVERS
INPUT
BUFFER
DIB2

BUS MBA
INT
B <15:08> H

ENA

ENA
DIB2-3 ENA L

DIB2-1 ENA L

INPUT
BUFFER
OIB1

~
I

VJ
Vi

INPUT
BUFFER
OIB1

INTERNAL
BUS
RECEIVERS

INTERNAL
BUS
RECEIVERS
BUS MBA
INT
B <23:16> H

INPUT
BUFFER
DIB2

INPUT
BUFFER
DIB2
ENA
DIB2-2 ENA L

BUS MBA
INT
B <07:00> H

ENA

INPUT
BUFFER
DIB2
ENA
DIB2-0 ENA L
BUS SILO
D <07:00> H
TK-0796

Figure 4-26

Internal Bus Receivers/Buffers

Table 4-2

Data Input Buffer Enable

VAR
BIT 02 H

VAR
BIT 01 H

VAR
BIT 00 H

DT
READ H

*
*

L
L
H

L
L
L
H
H
H
H

H
L
L
H

H
L
H
L

·L

H
H
H
H
H
H

L
L
L
L
L

L
H

Tl L

Input Buffer
Enabled
none
none
DIB 1-0
DIB 1-1
DIB 1-2
DIB 1-3
DIB 2-0
DIB 2-1
DIB 2-2
DIB 2-3

ENA L
ENA L
ENA L
ENA L
ENA L
ENA L
ENA L
ENA L

NOTE
VAR BIT <02:00> H are decoded after
they have been clocked through a
latch by SET SBI SEL H.

DATA INPUT
BUFFER
SELECT
VAR BIT 2

SELA

VAR BIT 1

SEL B

VAR BIT 0

SEL C

DIB2-3 ENA L
DIB2-2 ENA L
DIB2-1 ENA L
DIB2-0 ENA L
DIB1-3 ENA L
DIB1-2 ENA L
DIB1-1 ENA L

DT READ H

DIB1-0 ENA L

Tl L

LATCH

VAR B1T02 H

- - - - - SBI QATA SEL 00 H

VAR BIT 01 H

t-----~ SBI

VAR BIT 00 H

- - - - - SBI DATA SEL 02 H

DATA SEL 01 H

CLK
SET SBI SEL H

Figure 4-27

TK-0802

Data Input Buffer Enable

4-36

4.4.4
Silo and Control Logic (MDPF, MDPH)
The MBA silo is 16-bytes deep by 1-byte wide. Its function is to
prov id e a sou re e of inter i m storage f o r SB I or Mass bus data ,
permitting regulation of the data transfer rate. Figure 4-28 is a
simplified diagram of the silo logic.
When transferring data from the SBI to the Massbus device, the
input buffer and enable circuits divide the two 32-bit data words
into 8-bit bytes. LOAD SILO H loads data into the silo. The data
will be loaded in at T0 if all the following conditions exist
prior to T0:
a.

SBI BYTE CNTR = 0 L cleared, the SBI byte count register
must indicate more bytes to be transferred;

DIB2 FULL H asserted,
full;

DT READ L cleared,
(write check);

SILO FULL L cleared, the silo cannot be full.

second data

the

data

input buffer must

transfer

must

write

STROBE MAP H - - - - LOAD SILO H
DATA
DATA
IN
OUT
ENABLE ENABLE
BUS Sl~O D<07:00>H

DATA IN

SILO OUTPUT
D<07:00>H

ADDRESS

CNTR
CUP CLR
LOAD SILO L

DATA OUT

F3t-----'

F 2 - - -.....

MUX F1 1 - - - - - - - - '
CNTR
CUP CLR

FO-------

SEL

LOAD DOB L
READ/WRITE CYCLE
INIT +OT GOH

TK-0793

Figure 4-28

4-37

MBA Silo

As mentioned previously, the byte counter maintains a record of
the number of bytes to be received from the SB! and the Massbus
byte co un te r ma in ta ins a record of the number of bytes to be
transferred to the Massbus device.
The silo loading function process will continue until the silo is
full or until the SB! byte counter goes to zero indicating that
all of the bytes required to complete the data transfer have been
loaded into the silo.
If the silo is filled and data remains to be transferred from the
SB! to the Massbus, the silo loading process will stop until a
portion of the silo data is transferred to the Massbus. When this
occurs, the silo loading process will continue.
When transferring data from the Massbus device to the SB! (data
tr ans fer read ) , data i s 1 o ad e d , v i a the Ma s s bus rec e iv e rs , into
the Massbus data input buffers (MDPE). If a parity error is
detected in the Massbus input data, the MBA PE bit in the status
register is set and the data transfer operation will be aborted.
The following
function:

conditions

must

exist

enable

the

load

DT READ H asserted, the data transfer must be a read;

MDIB READY H asserted, the Massbus data
must be ready to accept Massbus data;

SILO FULL L cleared, the silo cannot be full.

input

silo

buffers

If there are no parity errors, SCLK from the Massbus device is
received, and the data input buffer ready flip-flop has not been
set previously, the ready and data input buffer full flip-flop
will be set upon receipt of data from the Massbus.
If SCLK were received and the ready flip-flop was already set, a
data overrun would occur. The DLT bit in the status register will
be set, RUN will be cleared, and the transfer operation will be
terminated.
Setting the ready and data input buffer full flip-flops initiates
the silo input operation. Actual silo loading operations are the
same as described for the write to Massbus device operation.
Unlike the write to Massbus device operation, however, the data
transfer begins immediately.
During a DT READ, each time a byte of data is loaded into the silo
the MBA byte counter is bumped. After the data word has been
transferred to the silo, the ready and data input full flip-flops
are reset and the data input buffer is ready to accept the next
Massbus device data word.

4-38

Each time a byte of data is transferred from the silo to the data
output buffer, the SBI byte counter is decremented. The process of
loading the silo and transferring bytes of data, via the output
buffer, to the internal bus continues until the last byte has been
transferred from the silo. At this time both the MB and SBI byte
counters will equal 0 and the data transfer operation will be
terminated upon receipt of EBL from the Massbus device.

4.4.5

Data Output Buffer and Control Logic (MDPJ, MDPM)

The data output buffer consists of eight 8-bit latches that
receive silo data (SILO OUTPUT D<7:eJ>H). Virtual address register
bi ts VAR BIT<0 2: 00 >H a re decoded to produce LOAD DOB<7: 0>H. These
signals are used to enable one of the eight data output latches
(Figure 4-29).
As each data output buffer is enabled, LOAD DOB<7: 0>H set eight
corresponding flip-flops (MDPL) that generate BYTE MASK<l-3:1-0>H,
BYTE MASK<2-3:2-QJ>H, and DOB<7:0>FULL L. DOB SELC H, DOB SELB H,
and DOB SELA H are decoded to produce NEXT DOB FULL L each time a
byte of data is loaded into the output buffer register. If the
next data output buffer already has valid data (byte mask set),
the silo output logic will not load the next byte until the byte
mask is cleared.
LOAD DOB H from the byte mask selection logic is also used to bump
the virtual address register each time a byte of data is loaded
into the output buff er to select the next storage location to or
from which data is to be written or read.

4.4.6

Internal Bus Output Multiplexers (MDPR, MDPS)

The internal bus output multiplexers consist of eight 2-to-l
multiplexers and corresponding
line drivers.
Figure
4-30
illustrates the logic associated with the internal bus drivers.
When a read from Massbus device occurs, data from the data output
buffer is applied to the internal bus output multiplexers, as well
as the Massbus multiplexers. If data is to be asserted on the
internal bus DT READ L, CMD REQ L and ENAB WD2 MUX or ENAB WDl MUX
H must be asserted. Selection of the data word to be asserted is
determined by ENAB WD2 MUX H. When this signal is asserted, DOB
D<37:00>H are selected; when the signal is not asserted, DOB
D<77:40>H are selected. These words are strobed onto the internal
bus by INT BUS OCLK H.

4-39

BYTE MASK 1-0 H
DOBO FULL L

LATCH
ENB

DOB D<77:70>H

LATCH
ENB

DOB D<67:60>H

LATCH
ENB

DOB D<57 :50>H

LATCH
ENB

DOB D<47:40>H

LOAD DOB7 H
BYTE MASK 1-1 H
DOB1 FULL L
BYTE MASK1-2H

LOAD DOB6 H

DOB2 FULL L
BYTE MASK 1-3 H

LOAD DOB5 H

DOB3 FULL L
BYTE MASK 2-0 H
D084 FULL L

SIL OUTPUT D<7:0>H
LOAD DOB4 Ii

BYTE MASK 2-1 H
DOB5 FULL L

~
I

DOB D<37:30>H
LOAD DOB3 H

BYTE MASK 2-2 H
DOB D<27 :20>H

DOB6 FULL L
LOAD DOB2 H
BYTE MASK 2-3 H
D087 FULL L

DOB D<17:10>H
LOAD DOB1 H

DOB SEL CH
DOB SEL B H

LATCH
ENB

DOB SELAH
DECODE

DOB D<07:00> H

LOAD DOBO H
LOAD DOBL
TK-0792

Figure 4-29

Data Output Buffer and Control Logic

DOB D<77:60>H

OUADWD
EN L

DOB D<37 :20>H

ENAB WD2 MUX H - - - - - -

RUN H

BUS MBA
INT B19 H

RECWCLK H

BUS MBA
INT B18 H

REC MB EXC H

BUS MBA
INT B17 H

DIAG INT BUS ENL

BUS MBA
INT B16 H

DIAG REG REO H ----------1
INT BUS OCLK H-------1
DIAG INT
BUS EN H

DOB D<57:40>H
2:1
MULTIPLEXER.,____ __.

MBA INT B<15:00>H

DOB D<17:00>H
STB

ENAB WD2 MUX H----~~
ENAB WD1 MUX H------~

QUAD WD EN L

INT BUS OCLK H - - - - DT READ L
CMD REO L
TK-0800

Figure 4-30

Internal Bus Output Multiplexers

4-41

4.4.7
Massbus Output Multiplexers and Parity Generator
Figure 4-31 illustrates the Massbus output multiplexers and parity
generator.
For a write to Massbus device, data from the output buffer is
1 o ad e d into the Mass bus data mu 1tip1 ex er • The Mass bus data
multiplexer consists of eight dual 4-to-l line multiplexers that
divide the 32-bit words into two 8-bit bytes (16 bits) to comply
with the input requirements of the Massbus device. Byte selection
is determined by DOB BYTE CNTRL 1 and DOB BYTE CNTRL 2, developed
by the data output select logic in response to SCLK from the
Massbus device. The output from the MBA multiplexer is checked to
ensure that the byte transmitted to the Massbus device contains an
odd number of bits. If they do not, the parity generator produces
XMIT MB DPA L to ensure odd parity.
If DT WRITE is asserted and the RUN
the multiplexer is transmitted, via
Massbus.

flip-flop is set, data from
the Massbus drives, to the

4.4.8
Write Check Logic
Write check logic (Figure 4-32) in the MBA verifies the integrity
of wr it e data by co mp a ring the . data from the Mass bus output
multiplexers with that of the data on the Massbus. DT WRITE CHK H
must be asserted in order for the write check ope rat ion to be
valid. A write check operation is performed identical to a write
operation except for the following additional processes. Data from
the Massbus output multiplexers is stored in the write check
buffer memory • Data rec e iv e d f r om the Mass bus i s st o red i n the
Massbus write check buffer memory. This received data should be
identical to the data out of the Massbus output multiplexers. The
data in the two write check memories is compared to test its
validity (each compared bit must be equal). If an inequality
exists in data bits <15: 08>, WCK UPPER ERR H is asserted, if an
inequality exists in data bits <07:00>, WCK LWR ERR H is asserted.
The assertion of either one or both of these signals causes the
data transfer to be aborted.

4-42

DOB D<J7:70, 67:60> H

DOB D<57:50, 47:40> H
XMIT MB DPD
<15:00> H

DOB
MUX
DOB D<37:30, 27:20> H

DOB D<17:10, 07:00> H

DOB BYTE CNTRL2 H--~
DOBBYTECNTRL1 H~~~~~
TK-0801

Figure 4-31

Massbus Output Multiplexers and Parity Generator

WCK UPPER ERR

WCK LWR ERR

TK-0799

Figure 4-32

Write Check Logic
4-43

4.5
MBA CONTROL PATH
A
control
path
data
transfer
is
initiated
when
the
command/address, decoded by the interface logic, specifies a read
or write external register operation. Figure 4-33 is a block
diagram of the MBA control path logic. The control logic has the
following major functions:
derive timing signals from the SBI and Massbus clocks
decode and store function codes for data transfers
decode external register addresses
transfer data to and from external registers
initiate Massbus control path cycles
set certain status and error conditions in the MBA
synchronize SBI and Massbus operations.
The following paragraphs
perform these functions.

describe

the

control

logic

used

4.5.1
Internal Bus Receivers (MCPA)
The control path internal bus receivers consist of two 8-bit
registers. Internal bus data (bits BUS MBA INT B<l5:00>H) is
latched into the receivers, to be processed by the control path
logic upon receipt of INT BUS ICLK L from the control path clock.
4.5.2
Data Transfer Control Logic (MCPB)
The data t rans f e r cont r o 1 1 o g i c i s i 11 us tr ate d i n Fig u r e 4- 3 4 •
When a control path data transfer is to take place, the MBA
asserts a drive address on the three Massbus drive select 1 i nes
(DS<02: 00>) and a register address on the five Massbus register
select lines
(RS<04:00>).
Data transfer commands are only
monitored when the selected register is the control register (R0)
of a drive. If a write to external register function is to be
performed, the MBA also asserts the controller to drive line CTOD
(transfer direction). Assertion of the RS, DS, and CTOD lines is
accomplished in the following manner. The command/address bits REC
INT B<07:00>H and WRITE FCN H from the internal bus and interface
logic are latched into the control store register. DT GO is a 50
ns pulse that int ia 1 i zes the internal logic on the MBA at the
s t a r t o f a d at a t rans f e r ope r a t i on • E XT CM D H c 1 o c ks the
in format ion through these registers to the Massbus transceivers
for assertion on the Massbus. The register select lines of the
control store output (EXT CS BIT<4:0>L) are ANDed with REC INT B00
H (go bit) to enable a 3-to-8 line decoder. Bits REC INT B<05:03>H
are decoded to select the function to be performed. Bits REC INT
B(02:0l>H indicate the direction of the indicated function (Table
4-3) •

4-44

INT BUS
RECEIVERS

DTCMD
STORE

DATA
DT BUSY
TRANSFER OPERATION
DTCMD

MCPC

MASS BUS
CONTROL
PATH CUT

OT BUSY
SET OT COMPLETE

DT READ
MCPD

DTWRITE
DTWCK
..__ _M_C;..P_B_,

DT FWD ;REV

INT/EXT (MSI)

r-+--t--t-~~__;_A~SS~E~R~T~D=E=M.:.:__~~~~~~~~~~~~~--i~EXTERNAL

MASS BUS
RECEIVERS
(CONTROL
PATH)

MCPC
M&A BUSY (MSI)

EXT HEAD
READY

MASS BUS
CONTROL
PATH IN
14--~ (TRI-STATE)

MCPC

MCPJ

EXTERNAL READ READY (MSI)

TK-0798

Figure 4-33

MBA Control Paths

WRITE FCN H - - -.....

1 - - - - - - - E X T CS WRITE (BECOMES CTOD)
LATCH

EXT CS BIT<7:5>H (DRIVE SELECT)

EXT CS BIT<4,3, 1,0>H (REGISTER SELECT)

CLK CLR

CLK EXT CMD H - - - MASTER INIT L - - - - - - - '

COMBINATION
_ _ .J

LL_£GIC

(RO SELECT)

DTCMD H
OT READ H

DT WRITE H

COMMAND
TYPE
DECODER
(COMMAND) REC INT B<5:3>H

SEL

COMMANOl---------l~

TYPE
OT WRITE
REGISTER .,_____
C_H_K_H_ ___

OT BUSY H,
OT BUSY L

DT REV H
DT RWD H
PWRF INIT L - - - - - - - <
CLR DT BUSY L _ _ _ ___,
PGM IN IT L - - - - - - - - '

Figure 4-34

Data Transfer Control Logic

TK-0805

Table 4-3

Function and Direction Select

REC INT Bits
94
93
92

Read
Reverse

Read
Forward

Write
Reverse

Write
Forward

Write Check
Reverse

Write Check
Forward

Function

x
0

X = Don't care.
The decoded output is stored in the corresponding function
flip-flop. REC INT B<07:00>H also produce EXT CS BIT <07:00>H when
clocked through the internal bus latches. EXT CS BIT <07: 05>H
select the drive (8-0) to which data is written or from which data
is read. EXT CS BIT <04: 00>H indicate the source or destination
register (0F-00).
Regardless of the selected valid function, an output from the
function select flip-flops sets the DT BUSY flip-flop. If DT BUSY
is already asserted, the MBA will not accept the new command. When
this flip-flop is set, the MBA is processing a data transfer and
cannot accept a new transfer command until the current transfer is
complete.
The decoder output also produces OT CMD H, which indicates that
the MBA has received a data transfer command. If CLK CPO H is
asserted, indicating a write to external register function, and DT
CMD H is asserted, ASSERT DEM H will be generated if the MBA is
not busy with a data transfer (DT BUSY H cleared). ASSERT DEM H
triggers a one-shot that sets the DEM flip-flop (MCPC). Its
output, XMIT MB DEM H, when asserted on the Massbus demand line,
indicates that the transfer of control path data to or from the
Massbus device is to take place •.

4-47

If a write to external register function is to be performed, the
control data (REC INT B<l5:00>) is stored in a temporary latch
(MCPD) to be transferred, via the control path data output logic,
to the Massbus device. Parity checking is performed to ensure that
this data contains an odd number of bits (odd parity). If the
content of the data word represents an even number of bits, the
parity generation logic produces XMIT CNTRL PAR H, which is
asserted on the Massbus CPA line (Figure 4-35).
Upon receipt of DEM, the addressed Massbus device will
control pat~ data into the selected register.

load

the

It should be noted that there is a 250 ns delay from the assertion
of control data on the data lines to the assertion of DEM to
compensate for skew in the MBA, Massbus cables, drivers, and
receivers.
Once the control path data has been loaded into the selected
register, the Massbus drive will issue TRA 250 ns later. DEM is
negated and the DONE one-shot is ·triggered to indicate that the
write to external register function has been completed. If after
assertion of DEM, TRA is not returned to the MBA within 1.5 us,
the NED {nonexistant device) flip-flop is set, DEM is negated, and
the write to external register function is terminated.

PARITY
GENERATION
~

ODD

REC INT B<15:00>H

BUFFER

XMIT CNTR L PAR

XMIT MB CPD<15:00>H

CLK
CLK CPO H
Tl H
TK-0794

Figure 4-35 Internal Bus Data Register and
Massbus Parity Generator

4-48

If the attention summary register is the destination of the write
operation, TRA will be ignored and NED will not be set. A 1.5 us
timeout will occur followed by the 250 ns delay and DEM will be
negated. When the attention summary register is read, no timeout
will occur.
When a read from external register function is executed, assertion
of the device and register select address and DEM on the Massbus
lines is accomplished in the same manner as described previously
for the write function; however, CTOD is not asserted. Upon
receipt of DEM, the device will load the contents of the selected
register on the C<l5:00> lines for transmission to the MBA and
assert TRA. This data is applied, via the MBA control path
receivers, to data latches. DESKEW DATA L (MCPC) latches the data
in. Parity is checked to ensure that there were no transmission
errors. If a parity error is detected, the MCPE parity error bit
in the status register will be set (Figure 4-36). If no parity
errors are detected, the latches are clocked by DESKEW DATA L. The
output from the data latches is placed on the internal bus upon
receipt of SEND TR H from the interface logic.

REC CNTRL PAR H

~ 1-------------t
ODD
EXT OP DONE H
PARITY
CS RS04 L _ _____.
CHECK
EXT CS WRITE L - - - - '

MASSBUS
CONTROL
PATH
DATA
REGISTERS
CLK

CLR

DESKEW DATA L----SET NED L - - - - - '

SET MCPE L

BUS MBA INT B<15:00>H

INT BUS OCLK H
SEND TR H
EXT RD
REO L _.__.,,
TK-0795

Figure 4-36 Massbus Control Path Data Registers
and Parity Check (Received Massbus Data)

4-49

When the MBA is in the maintenance mode, MB MAINT MODE L (MCPE)
prevents DEM from being asserted on the Massbus. The MBA performs
a write asserting data on the Massbus followed by a read of the
data just put on the Massbus. The MBA uses a timeout to complete
the read. The register select and drive select lines are also read
to ensure that the correct data has been put on these lines. The
diagnostic register is read to check the validity of the
operation.
4.5.3
Massbus Receivers/Drivers
Information is transferred to and from the Massbus via the Massbus
control path receivers and drivers. Massbus information is
summarized in Chapter 2 of this manual. The control path receivers
are always enabled. Transmit enable signals are summarized in
Table 4-4.
Table 4-4

Massbus Transmit Enable Signals

Control Path Signal

Massbus Signal

Enabling Signal

EXT CS BIT<7:5>H

MASS DS<2:0>

(always enabled)

EXT CS BIT<4:0>H

MASS RD<4:0>

(always enabled)

XMIT MB DEM H

MASS DEM

MB MAINT MODE L
OR XMIT MB DEM H

XMIT MB INIT H

MASS !NIT

(always enabled)

XM IT MB CPD'< 1 5 : 0 0 >H

MASS C (1 5 : 0 0 >

EXT CS WRITE L
NAND MB MAINT MODE L

XMIT CNTRL RAR H

MASS CPA

(always enabled)

EXT CS WRITE H

MASS CTOD

(always enabled)

SIMULATE OCC H

MASS OCC

SIMULATE ace H
AND MB MAINT MODE H

XMIT MB EXC H

MASS EXC

(always enabled)

MB FAIL

MASS FAIL

(always enabled)

4-50

4.5.4
End Data Transfer Logic (MCPA)
End data transfer logic is responsible for generating the
appropriate signals at the end of a data transfer. The logic
monitors various signals in the control path and MBA interface to
produce the following:
DT END L

Data transfer complete

CLR DT BUSY L

Clear data transfer busy

BLOCK SEND CMD H

Block sending the command/address

SET DT ABORTED L

Set data transfer aborted

SET DT COMPLETE L

Set data transfer complete

Figure 4-37
functions.

illustrates

the

logic

used

accomplish

these

EOS H

SBI BYTE CTR=O L
OT READ L -~--LAST MB DATA H
MB EXC+MDPE H
SBI ABORT IMM H _ _ _ _ _.----,,.........

T2 H

CLR OT BUSY L

>-------+----+------BLOCKSENDCMDH
SET OT ABORTED L

SET OT COMPLETE

INIT COND L
TK-0797

Figure 4-37

End Data Transfer Logic

4-51

DT END L will be asserted only after the MBA has dropped RUN and
the drive has asserted EBL if one of the following conditions
occur.
1.

The data transfer function was a read {DT READ H), the
SBI byte counter has gone to zero (SBI BYTE CNTR=0 H),
and memory has acknowledged the second data word (WD2 ACK
H) •

The data transfer was a write or write check function (DT
READ L not asserted) and the SBI byte counter has gone to
zero.

The data transfer is to be aborted immediately due to an
error (SET SB! ABORT IMM H).

There has been a
EXC + MOPE H).

Massbus exception or parity error

(MB

DT END L is synchronized with T0. If DT END L has been asserted,
CLR DT BUSY L will be produced at the following T2. Block SEND CMD
L will be asserted as a result of an abort condition, Massbus
exception, or a Massbus data parity error. SET DT ABORTED L will
be asserted at T2 of the SBI cycle if DT END H is asserted, a
Massbus exception or parity error occurs, and there is no
initialize condition (!NIT COND L not asserted). SET DT ABORT L
will also be asserted if a missed transfer error has occurred (SET
MXF L). SET DT COMPLETE L will be asserted at T2 if there is an
initialize condition and DT END H has been asserted.

4-52

RH780 MASSBUS ADAPTER
TECHNICAL DESCRIPTION
EK-RH780-TD-001

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