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EK-DS780-TD-1

February 1979

244 pages

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Document:	VAX 11/780 Diagnostic System Technical Description
Order Number:	EK-DS780-TD
Revision:	1
Pages:	244
Original Filename:

OCR Text

EK-DS780-TD-001

V AX-11 /780 Diagnostic System
Technical Description

digital equipment corporation • maynard, massachusetts

First Edition, February 1979

Copyright © 1979 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC

PDP
DEC US
UNIBUS

D ECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
IAS

8184-15

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1
1. 2
1. 3
1. 4
1. 5
1. 6
1. 6.1
1. 6. 2
1. 7
1. 7 .1
1. 7. 2
1.7.2.1
1.7.2.2
1.7.2.3
1. 8
1. 9
1. 9.1
1. 9. 2
1.9.2.1
1.9.2.2
1.9.2.3
1. 9. 3
1.9.3.1
1.9.3.2
1.9.3.3
1.9.3.4

MANUAL SCOPE
DIAGNOSTIC SYSTEM CAPABILITIES
DIAGNOSTIC SYSTEM OVERVIEW
DIAGNOSTIC SYSTEM EXECUTION ENVIRONMENTS
CONSOLE DIAGNOSTICS
MICRODIAGNOSTIC PROGRAM
Console Adapter and Hardcore Division
Microtest Division
MICRODIAGNOSTIC PROGRAMS
Diagnostic Supervisor
Cluster Diagnostic Program
CPU Cluster Exerciser Package
RH780 (MBA) Diagnostic Program
DW780 (UBA) Diagnostic Program
PERIPHERAL DIAGNOSTIC PROGRAMS
OPERATOR/VAX-11/780 COMMUNICATION
Console Terminal Modes
Console Panel Equivalent Functions
Program Control
Memory Element Display and Modification
Clock Control
Console Control Functions
Default Settings
Status Displays
Command Linking and Repeating
Real-Time Delays

CHAPTER 2

CONSOLE PROGRAM AND CONTROL DESCRIPTION

2.1
2 .1.1
2.1. 2
2 .1. 3
2.1. 4
2.2
2.2.1
2.2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8

CONSOLE PROGRAM OVERVIEW
Command Getter
Parser and Parser Tables
Command Executor Module
Additional Services
COMMAND TERMS AND SYMBOLS
Notation Examples
Command Abbreviations
CONSOLE COMMAND DESCRIPTIONS
Boot Command ( B)
Clear Command (CL)
Continue Command (C)
Deposit Command (D)
Enable DXl: Command
Examine Command (E)
Halt Command (H)
Help Command (HE)

iii

1-1
1-2
1-3
1-8
1-8
1-10
1-12
1-12
1-14
1-14
1-18
1-18
1-18
1-19
1-20
1-20
1-20

1-21
1-21
1-21
1-22
1-22
1-22
1-23
1-23
1-23

2-1
2-1
2-1
2-1
2-2
2-2
2-3
2-4
2-4
2-4
2-5
2-5
2-5
2-6
2-7
2-8
2-8

CONTENTS (Cont)
Page
2.3.9
2.3.10
2.3.11
2.3.12
2.3.13
2.3.14
2.3.15
2.3.16
2.3.17
2.3.18
2.3.19
2.3.20
2.3.21
2.3.22
2.3.23
2.3.24
2.4

2. 5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.8.1
2.7.8.2
2.7.8.3
2.7.8.4
2.7.9
2.8
2.8.1
2.9
2.9.1
2.9.2
2.10
2.11
2.11.1
2.12
2.13
2.14
2.15
2.15.1
2.15.2

In i t i a 1 i ze Comm and ( I )
LINK Command (LI)
Load Command (LO)
Perform Command (P)
Quad Clear Command (Q)
Reboot Command (REB)
Repeat Command (R)
Set Command (SE)
Show Command (SH)
Start Command (S)
Next Command (N)
Test Command {T)
Unjam Command (U)
Wait Command (WA)
Indirect (@) Command
WCS Command (W)
COMMANDS PERFORMED WITH THE
VAX-11/780 CPU RUNNING
COMMENTS WITHIN COMMANDS
CONTROL CHARACTERS AND SPECIAL CHARACTERS
COMMAND QUALIFIERS AND DEFAULTS
Address Type Qualifiers
Address Type Defaults
Data Length Qualifiers
Data Length Defaults
Qualifiers for RADIX
Defaults for RADIX
Local Radix Override
Default Address Facility
Specifying Default Address in a Command
Last Address Notation
Preceding Address Notation
Use of Last Data as an Address Argument
NEXT Qualifier
COMMAND REPEAT FACILITY
Repeating Commands
COMMAND LINK FACILITY
Link Facility Operation
Link Facility Usage
CONSOLE MODE CHANGE
VMS COMMUNICATION WITH CONSOLE FLOPPY DISK
Floppy Function Protocol
MISCELLANEOUS CONSOLE COMMUNICATIONS
COMMUNICATION REGISTER FORMATS AND SELECT CODES
FLOPPY STATUS BYTE DEFINITION
REMOTE CONSOLE ACCESS COMMAND SET
Enable Talk Mode Command
Enable/Disable Echo Command

2-8
2-8
2-8
2-9
2-9
2-9
2-10
2-10
2-12
2-12
2-12
2-13
2-13
2-13
2-14
2-14
2-14
2-15
2-15
2-17
2-17
2-18
2-18
2-18
2-19
2-19
2-19
2-19
2-20
2-20
2-21
2-21
2-21
2-22
2-22
2-23
2-23
2-23
2-241
2-24
2-26
2-27
2-28
2-30
2-30
2-31
2-32

CONTENTS (Cont)
Page

2.15.3
2.15.4
2.15.5
2.15.6
2.16
2.16.1
2.16.2
2.16.3
2.16.4
2.16.5
2.16.6

Enable/Disable Local Copy Command
Enable Local Control Command
Enable/Disable Carrier Error Command
Enable/Disable Local Floppy Command
CONSOLE ERROR MESSAGES
Syntactic Error Messages
Command Generated Error Messages
Microroutine Error Messages
CPU Fault Generated Error Messages
RX01 Error Messages
Miscellaneous Error Messages

CHAPTER 3

DIAGNOSTIC SUPERVISOR AND CONTROL

3.1
3.2
3.2.l
3.2.2
3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7

SUPERVISOR STRUCTURE OVERVIEW
CL! FUNCTIONAL MODULE DESCRIPTION
Image Loader Module
Test Sequence Control Module
Script Processor Module
PG! FUNCTIONAL MODULE DESCRIPTION
Memory Management and Adapter Services
Operator Terminal Services
System Error Handling
SUPERVISOR COMMAND DESCRIPTIONS
Command Terms and Symbols
Command Description Segments
Command Abbreviations
Command Overview
SEQUENCE CONTROL COMMANDS
Lo ad Comm and
Start Command
Restart Command
Run Command
Control Characters and Special Characters
Continue Command
Summary Command
Abort Command
Submit Command
EXECUTION CONTROL COMMANDS
Set Control Flag Command
Clear Control Flag Command
Set Control Flag Default Command
Show Control Flags Command
Set Event Flags Command
Clear Event Flags Command
Show Event Flags Command

2-32
2-32
2-32
2-33
2-33
2-33
2-33
2-34
2-35
2-35
2-36

3-1
3-3
3-3
3-3
3-3
3-3
3-4
3-4
3-4
3-4
3-4
3-6
3-6
3-6
3-6
3-7
3-7
3-8
3-8
3-8
3-9
3-9
3-10
3-10
3-10
3-10
3-12
3-12
3-13
3-13
3-13
3-13

CONTENTS (Cont)
Page
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7

DEBUG AND UTILITY COMMANDS
Set Base Command
Set Breakpoint Command
Clear Breakpoint Command
Show Breakpoints Command
Set Default Command
Examine Command
Deposit Command

CHAPTER 4

MICRODIAGNOSTIC DESCRIPTION

4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.5
4.5.1
4.6
4.6.1
4.6.1.l
4. 6.1.2
4.6.1.3
4.6.1.4
4.6.1.5
4.6.1.6
4.7
4.7.1
4.7.2
4.7.3
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.9
4.9.1
4.9.2
4.9.3
4.9.4

MICRODIAGNOSTIC PROGRAM OVERVIEW
BASIC PROGRAM EXECUTION
BASIC TEST STRATEGY
HARDCORE TEST DESCRIPTION
Hardcore Test Structure
Pseudo Instruction Description
MICROTEST DESCRIPTION
Microtest Structure
MICRODIAGNOSTIC MONITOR CONTROLS
Monitor Control Examples
HD/HI Flags
Loop on Error Flag (LOOP}
No Error Report Flag (NER}
Bell on Error Flag (BELL}
Continue Command (CONT)
Error Abort Flag (ERABX)
MICRODIAGNOSTIC RELATED ERROR MESSAGES
Syntax Error Messages
System Error Messages
Go Chain Monitor Error Messages
PROGRAM LISTING AND ERROR MESSAGE DESCRIPTIONS
Monitor Listing Descriptions
Hardcore Listing Description
Microtest Listing Description
Microdiagnostic Execution
Error Message Format
LISTING/ERROR MESSAGE CORRELATION
No Error Message Situation
Hardcore Loop and Single Step Setup
Microtest Scope Loop Setup
Microtest Single Bus Steps Setup

CHAPTER 5

MACRODIAGNOSTIC PROGRAM DESCRIPTIONS

5.1
5.2
5.3

DEFINITION OF TERMS
OVERVIEW OF THE MACRODIAGNOSTIC PROGRAM
MACRODIAGNOSTIC PROGRAM LISTING DESCRIPTION

3-13
3-13
3-14
3-14
3-14
3-14
3-14
3-15

4-1
4-1
4-2
4-4
4-5
4-6
4-14
4-14
4-16
4-21
4-21
4-21
4-22
4-22
4-22
4-22
4-22
4-23
4-23
4-23
4-24
4-24
4-26
4-28
4-29
4-29
4-32
4-32
4-34
4-34
4-37

5-1
5-2
5-2

CONTENTS

{Cont)

Page
5.4
5.5
5.5.1
5.5.2
5.6
5.6.1
5.6.2
5.7
5.7.1
5.7.2
5.8
5.8.1
5.8.2

DIAGNOSTIC PROGRAM AND SUPERVISION INTERACTION
ANALYSIS OF A SAMPLE TEST: RH780 (MBA)
TEST 3, SUBTEST 1
Listing Column Format Description
Analysis of Typical Lines
RH780 (MBA) DIAGNOSTIC SAMPLE SUBTEST
(Direct I/O)
RH780 Diagnostic Detailed Flow
RH780 Diagnostic Sample Error Message
RP0X/DCL REPAIR DIAGNOSTIC (DIRECT I/O),
SAMPLE SUBTEST
De ta i 1 ed Flow
RP0X/DCL Repair Diagnostic Sample Error
Message
DISK RELIABILITY DIAGNOSTIC (QUEUE I/O)
SAMPLE SUBTEST
Detailed Flow
Disk Reliability Diagnostic Sample Error
Message

CHAPTER 6

CPU CLUSTER EXERCISER PACKAGE

6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.6.1
6.2.6.2
6.2.6.3
6.2.6.4
6.2.6.5
6.2.6.6
6.2.6.7
6.2.6.8
6.2.6.9
6.2.6.10
6.2.7
6.3
6.3.1

CONTROL MODULE
COMMON INSTRUCTION TEST SERVICES MODULE (CITS)
CITS DECODE
CITS-SETUP
CITS-EXECUTE
CITS-CHECK
CITS-SUBTEST
CITS-Error Messages
Message Heading
CITS Subtest Troubleshooting Features
Unexpected Exceptions in CITS
Results Register Errors
Leading or Tra i 1 ing Bae kg round Errors
Data Errors
PSL Errors
Branch Errors
Expected Exception or Trace Traps Errors
Extended Pr in tout
How to NO-OP a Test Case
ESKAX DESCRIPTION
Compatibility Mode Entry/Exit Module
(ESKAX02, Test 1)
First Part Done Test {ESKAX04, Test 2)
Possible First Part Done Failures
First Part Done Test Procedures

6.3.2
6.3.2.1
6.3.2.2

vii

5-6
5-8
5-8
5-10
5-11
5-11
5-17
5-18
5-18
5-22
5-22
5-22
5-32

6-1
6-6
6-6
6-6
6-6
6-6
6-7
6-7
6-7
6-7
6-8
6-8
6-10
6-10
6-12
6-13
6-13
6-14
6-15
6-17
6-17

6-25
6-25
6-25

CONTENTS (Cont)
Page
6.3.3
6.3.3.1
6.3.3.2
6.3.3.3
6.3.3.4
6.3.3.5
6.3.3.6
6.3.3.7
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.5
6.5.1
6.5.1.1
6.5.1.2
6.5.1.3
6.6
6.6.1
6.6.2
6.6.3
6.6.4

APPENDIX A

SB! Verification Module (ESKAX05, Test 3)
SBI Checkout Subtest
UBA Checkout Subtest
MBA Checkout Subtest
SB! Interaction Subtest
UBE Checkout Subtest
MBE Checkout Subtest
Memory Verify (ESKAX06, Test 4}
ES KAY
Internal Timer and Day Clock Verification
Module (ESKAY02, Test l}
Interval Timer Functions
Day Clock Function
Arithmetic, Logic, and Field Instruction
Test Module (ESKAY0 3, Test 2}
Branch, CRC, and Queue Test Module
(ESKAY0 4, Test 3)
Floating-Point Instruction Test Module
{ESKAY05, Test 4; ESKAY06, Test 5}
Operand Specifier Dependent Floating-Point
Test (ESKAY07, Test 6}
Decimal Strings Module (ESKAY08, Test 7}
EDITPC Operators Module {ESKAY09, Test 8}
Character String Instructions Test Module
(ES KAY 1 0, Tes t 9 }
Privileged Instruction Exception Test
(ESKAYll, Test 10}
ESKAZ DESCRIPTION
Memory Management Test Module (ESKAZ03,
Test l}
Memory Management Test, General Flow
Memory Management Te~t, Subsection Flow
Test Reference Execution
COMPATIBILITY MODE INSTRUCTION TEST
{ESKAZ03, TEST 2}
Instructions Tested
Compatibility Mode Test Error Message
Format
Sample Error Message Explanation
Compatibility Mode Instruction Module
Assumptions
GLOSSARY OF DIAGNOSTIC SOFTWARE TERMS

viii

6-32
6-33
6-35
6-35
6-36
6-36
6-37
6-39
6-40
6-40
6-40
6-44
6-46
6-50
6-50
6-57
6-57
6-57
6-60
6-60
6-60
6-60
6-62
6-62
6-62
6-70
6-70
6-72
6-73
6-74

FIGURES
Figure No.

Title

Page

1-1
1-2
1-3

Diagnostic Program Mode, Environment and Levels
VAX-11/780 Diagnostic System Program Hierarchy
VAX-11/780 Diagnostic System, Execution
Environments
Monitor Relationships and Test Sequencing
Hardcore Monitor Residency/Test Flow
Microtest Monitor Residency/Test Flow
Functions of the Diagnostic Supervisor
Environments
Communication Register Formats and Select Codes
Floppy Status Bit Assignments
Basic Diagnostic Supervisor Structure
LSI-11 Memory Program Residency
Simplified Microdiagnostic Test Procedure
Hardcore Test Sequence
Microtest Structure
Monitor Li sting Sample
Hardcor~ Listing Sample
Microtest Listing Sample
Typical Error-Free Terminal Output
Error Message Format
Listing Indexing Example
Loop and Single Example
Microtest Scope Loop Example
Microtest Single Bus Example
Portion of the Program Section Synopsis,
RH780 (MBA) Diagnostic Program
Portion of the Global Symbol Table for the
Absolute PSECT of the Loader File of the RH780
(MBA) Diagnostic Program
Diagnostic Program and Diagnostic Supervisor
Interaction
RH780 (MBA) Diagnostic Program Test 3,
Subtest 1, Listing
RH780 (MBA) Diagnostic Program Test 3,
Subtest 1, Flowchart
DS$BGNSUB Listed in the Symbol Table in the
ESCAA Link Map
DS$BGNSUB Listed in the Symbol Table in the
Supervisor Link Map
DS$BGNSUB Entry Point
RBGNSUB Listed in the Symbol Table in the
Diagnostic Supervisor Link Map
ESRCA Sample Error Listing
ESRCA RP0X/DCL Test 1, Subtest 0, Program
Listing
ESRCA RP0X/DCL Repair Diagnostic Test 1,
Subtest 0, Flowchart

1-5
1-6

1-4
1-5
1-6
1-7
2-1
2-2
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12

1-9
1-11
1-13
1-15
1-16
2-28
2-30
3-2
4-2
4-3
4-5
4-15
4-25
4-27
4-30
4-31
4-31
4-33
4-35
4-36
4-38
5-3
5-5
5-7
5-9
5-12
5-13
5-14
5-15
5-16
5-18
5-19
5-20

FIGURES (Cont)
Figure No.

Title

Page

5-13
5-14

ESRCA Sample Error Message
Disk Reliability (ESRAA) Test 1, Subtest 0,
Error 12 Listing
ESRAA Test 1, Subtest 0, Error 12 Flowchart
I/O Status Block Contents (for disks)
CHECKBLOCK Routine Code
GETBBFSECTOR Routine Code
ESRAA Sample Error Listing
CPU Cluster Exerciser Package Memory Allocation
Execution of a Test Case in ESKAY03
Compatibility Mode Instruction Modul~ Subtest
Structure

5-23

5-15
5-16
5-17
5-18
5-19
6-1
6-2
6-3

5-24
5-25
5-28
5-30
5-31
5-32
6-2
6-9
6-70

TABLES
Table No.

Title

Page

1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
4-1
4-2
6-1

VAX-11/780 System Manuals
Term and Symbol Definition
Deposit Symbolic Addresses
Examine Symbolic Address
Load Command Qualifiers
Set Default Command Options
Set Step Command Options
Control/Special Character Descriptions
Memory Management Error Code Definitions
RX01 Error Message Code Definitions
Term and Symbol Definitions
Control/Special Character Descriptions
Control Flag Descriptions
Qualifier Descriptions
Instruction Symbol/Abbreviation Definitions
Microdiagnostic Command/Flag Descriptions
Summary Parameter, Length Parameter for
Vector 4
Information Pushed on the Stack by the
Exception Handler
Reserved Operand Faults and PSL Bit Settings on
Compatibility Mode Entry
Compatibility Mode Trap Instructions
Compatibility Mode Reserved Instructions
Page Faulting with First Part Done
First Part Done Test Table Entries
First Part Done IDB Format
First Part Done TCB General Format
First Part Done TCB Passed to CITS DECODE

1-1
2-2
2-6
2-7
2-9
2-10
2-11
2-15
2-34
2-35
3-5
3-9
3-11
3-15
4-6
4-17

6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10

6-3
6-5
6-17
6-18
6-19
6-26
6-27
6-27
6-27
6-28

TABLES (Cont)
Table No.

Title

6-11
6-12

Unibus Adapter Map
Compatibility Mode
Compatibility Mode
ESKAZ Test 2
Compatibility Mode

6-13

Page
Register Address Offsets
Instructions Provided by
Hardware and Exercised by
Instructions Not Yet Tested

6-39

6-71
6-71

EXAMPLES
Example No.

Title

Page

6-1
6-2

Unexpected Exception Error Message
Unexpected Exception in CITS, Error Message
Result Register Errors
CITS Detects a Longword Data Error
CITS Detects a Quadword Data Error
CITS Detects a String Data Error
PSL Error
Branch Error
Expected Exception Error
Trace Trap Error
Ex tended Pr in tout
Case 105 SUBD2 Instruction
ESKAX Test 1, Subtest 1, Error 2
ESKAX Test 1, Subtest 1, Error 2
ESKAX Test 1, Subtest 2, Error 3
ESKAX Test 1, Subtest 2, Error 3
ESKAX Test 1, Subtest 2, Error 3
ESKAX Test 1, Subtest 3, Error 4
ESKAX Test 1, Subtest 4, Error 3
ESKAX Test 1, Subtest 4, Error 3
ESKAX Test 1, Subtest 5, Error 4
ESKAX Test 1, Subtest 5, Error 4
ESKAX Test 1, Subtest 6, Error 3
ESKAX Test 1, Subtest 6, Error 3
ESKAX Test 2, Subtest 0, Error 212
ESKAX Test 2, Subtest 0, Error 213
ESKAX Test 2, Subtest 0, Error 207
ESKAY Test 3, Subtest 2, Error 10
ESKAX Test 3, Subtest 3, Error 4
ESKAX Test 3, Subtest 3, Error 4
ESKAY Test 1, Subtest 1, Error 2
ESKAY Test 1, Subtest 2, Error 1
ESKAY Test 1, Subtest 2, Error 2
ESKAY Test 1, Subtest 3, Error 2
ESKAY Test 1, Subtest 4, Error 1
ESKAY Test 1, Subtest 5, Error 1
ESKAY Test 1, Subtest 5, Error 1

6-3
6-8
6-10
6-11
6-11
6-12
6-12

6-3
6-4
6-5

6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15

6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25

6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36

6-37

6-13

6-13
6-14
6-14
6-16
6-18
6-18

6-19
6-20
6-20
6-21
6-21
6-22
6-22
6-22
6-23
6-23
6-28
6-30
6-32
6-38
6-38
6-38
6-40
6-40
6-40
6-41
6-41
6-42
6-42

EXAMPLES (Cont)
Example No.

Title

Page

6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-4 7
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
6-58
6-59

ES KAY Test 1, Subtest 6, Error 1
ES KAY Test 1, Subtest 6, Error 2
ES KAY Test 1, Subtest 7, Error 3
ES KAY Test 1, Subtest 8, Error 2
ES KAY Test 1, Subtest 9, Error 1
ES KAY Test 1, Subtest 10, Error 2
ES KAY Test 1, Subtest 11, Error 1
ES KAY Test 1, Subtest 12, Error 1
ES KAY Test 2, Subtest 2, Error 1
ES KAY Test 2, Subtest 1, Error 31
ES KAY Test 2, Subtest 3, Error 1
ES KAY Test 4, Subtest 1, Error 2
ES KAY Test 4, Subtest 1, Error 7
ES KAY Test 4, Subtest 1, Error 24
ES KAY Test 5, Subtest 2, Error 7
ES KAY Test 5, Subtest 8, Error 100
ES KAY Test 5, Subtest 8, Error 101
ES KAY Test 7, Subtest 2, Error 26
ES KAY Test 8, Subtest 1, Error 48
ES KAZ Test 1, Subtest 1, Error 20212
ES KAZ Test 1, Subtest 1, Error 20213
ES KAZ Compatibility Mode Test Error

6-43
6-43
6-43
6-44
6-44
6-44
6-45
6-45
6-46
6-47
6-49
6-51
6-52
6-53
6-55
6-56
6-56
6-58
6-59
6-64
6-65
6-73

xii

CHAPTER 1
INTRODUCTION
1.1
MANUAL SCOPE
This manual provides a comprehensive description of the functional
and operational characteristics of the VAX-11/780 diagnostic
system. The level of detai 1 presented prov ides a resource for
appropriate branch courses of the field service training program
and for a field reference. Table 1-1 provides a list of related
documents. Note that a glossary of diagnostic software terms is
provided in Appendix A.
Table 1-1

VAX-11/780 System Manuals

Document Title

Control Number

Form

VAX-11/780 Power System
Technical Description

EK-PS780-TD-001

In Microfiche Library

System
Installation Manual

EK-SI780-IN-001

Available in hard copy*

DS780 Diagnostic System
User's Guide

EK-DS780-UG-001

Available in hard copy*

DS780 Diagnostic System
Technical Description

EK-DS780-TD-001

In Microfiche Library

FP780 Floating-point
Processor Technical
Description

EK-FP780-TD-001

In Microfiche Library

REP05/REP06 Subsystem
Technical Description

EK-REP06-TD-001

In Microfiche Library

VAX-11 KA780 Central
Processor Technical
Description

EK-MS780-TD-001

In Microfiche Library

VAX-11 MS780 Memory
System Technical
Description

EK-MS780-TD-001

In Microfiche Library

DW780 Unibus Adapter
Technical Description

EK-DW780-TD-001

In Microfiche Library

KC780 Console Interface
Technical Description

EK-KC780-TD-001

In Microfiche Library

VAX-11/780 Architecture
Handbook

EB07466

Available in hard copy*

~. VAX-11/780

1-1

Table 1-1

VAX-11/788 System Manuals (Cont)

Document Title

Control Number

Form

VAX-11/780 Software
Handbook

EB08126

Available in hard copy*

VAX-11/780 Hardware
Handbook

EB09987

Available in hard copy*

VAX/VMS Primer

AA-D030A-TE

Available in hard copy*

VAX/VMS Command Language
User's Guide
AA-D023A-TE

Available in hard copy*

VAX-11 MACRO User's
Guide

AA-D033A-TE

Available in hard copy*

VAX-11 Linker Reference
Manual

AA-D019A-TE

Available in hard copy*

VAX-11 Symbolic Debugger
Reference Manual
AA-D026A-TE

Available in hard copy*

*These documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
Attn: Printing and Circulation Services (NR2/Ml5)
Customer Services Section
For information concerning microfiche libraries, contact:
Digital Equipment Corporation
Micropublishing Group, PK3-2/Tl2
129 Parker Street
Maynard, MA 01754
1.2
DIAGNOSTIC SYSTEM CAPABILITIES
The VAX-11/780 diagnostic system is a set of software components
integrated as a system to provide a wide range of error detection
and isolation capabilities for the VAX-11/780 hardware. The
diagnostic levels range from system functional tests to dedicated
microprogram techniques capable of identifying a faulty module
(printed circuit board) or group of modules. In addition, the
diagnostic control functions provide substantial selection and
execution options.

1-2

The overall diagnostic strategy satisfies the major field service
goals of:
a.

High quality and efficiency of system installation, by
providing formal installation procedures, automated test
package configurations, and a system exerciser program
that can be configured for specific VAX-11/780 systems.

Reduction of fault isolation and repair times, by
providing high visibility diagnostic programs (programs
accessible to the operator) and procedures keyed to the
field service troubleshooting and repair philosophy.

The diagnostic system is supported by a PDP-ll/V03
(LSI-11)
microcomputer console system. In addition to providing for local
(on-site) diagnostic execution, the diagnostic system allows for
diagnosis from a remote diagnostic center.
1.3
DIAGNOSTIC SYSTEM OVERVIEW
The diagnostic system consists of programs that are organized
hierarchically (from general to specific capabilities)
in six
levels. Each level contains one or more categories, as follows:
Level 1

Operating system
(using queue I/O)

(VMS}

based

diagnostic

programs

System exerciser program
Level 2·--

Diagnostic supervisor--based diagnostic programs that
can be run either under VMS or in the standalone mode
(using queue I/O)
Bus interaction program
Formatter and reliability level peripheral diagnostic
programs

Level 2R --

Diagnostic supervisor--based diagnostic programs that
can be run only under VMS.
Certain peripheral diagnostic programs

Level 3 --

Diagnostic supervisor--based diagnostic programs that
can be run in standalone mode only (using direct I/O)
Functional level peripheral diagnostic programs
Repair level peripheral diagnostic programs
Cluster diagnostic programs

Level 4

Standalone macrodiagnostic programs that run without
the supervisor.
Hardcore instruction test

1-3

Console
Level--

Console-based diagnostics
standalone mode only

that

can

run

the

Mic rod iagno st ics
Console program
Octal Debugging Technique (ODT)
ROM resident power-up tests
LSI-11 diagnostics
The diagnostic programs can be used for preventive maintenance
checks to ensure proper computer operation; or, if system
malfunctions have been detected, specific programs or groups of
programs can be run to isolate the fault.
Figure 1-1 shows the relation of the six levels to four diagnostic
program operating environments. The console environment requires
exclusive use of the VAX-11/780 system (standalone mode). It
includes only the console level programs. In this environment,
program control is exercised by the LSI-11 processor in the
console subsystem.
In the cluster environment, the system environment, and the user
environment, control is exercised in the VAX-11/780 CPU. The
cluster environment supports only standalone diagnostic programs.
It includes level 4 programs and some level 3 programs. The level
3 programs supported are those that test the CPU and the channel
adapters.
The system environment supports peripheral diagnostic
that can run in the standalone mode. These include
programs and level 3 peripheral programs.

programs
level 2

The user environment supports only programs that can be run under
VMS, namely levels 2R, 2, and 1.
In general, the diagnostic system uses a building block approach
to testing (and subsequent fault detection and isolation). When
the diagnostic programs are executed in the standard system
checkout sequence, they will initially test a minimum (basic) set
of logical functions to ensure their proper operation. After these
basic operations are verified, a larger and more complex block is
tested, using the previously tested block as a base. This sequence
is implemented consistently from the ROM resident- f)OWer-up tests
(which check the console) to interactive system tests executed as
user mode tasks under the VMS operating system, as shown in Figure
1-2.
It may be that a diagnostic program will indicate an error in a
hardware component which is more easily diagnosed by another
program. For instance, the bus interaction program may indicate a
failure of a tape drive. The tape reliability program may also
detect the same failure or a related failure, but the problem may
1-4

MODE

OFF-LINE
(STANDALONE)

PROGRAM
ENVIRONMENT

PROGRAM
LEVEL

CONSOLE
ENVIRONMENT

CONSOLE LEVEL

CLUSTER
ENVIRONMENT

LEVEL 4

LEVEL 3
SYSTEM
ENVIRONMENT
LEVEL 2

ON-LINE
(UNDER VMS)

USER
ENVIRONMENT

LEVEL 2R

LEVEL 1

TK-1170

Figure 1-1

Diagnostic Program Mode, Environment and Levels

1-5

1
RPOX/DCL
REPAIR
DIAGNOSTIC
(ES RCA)

STAND ALONE ONLY
(DIRECT 1/0)
REPAIR LEVEL

STAND ALONE ONLY
(DIRECT 1/0)
FUNCTION LEVEL

STAND ALONE
OR UNDER VMS
(QUEUE 1/0)

O'I

LEVEL 2

STAND ALONE
OR UNDER VMS
(QUEUE 1/0)

LEVEL 2R

RK611 MANUAL
INTERVENTION
TESTS
(ESREF)

-l-

LEVEL 3

RK611
DIAGNOSTIC
PARTS A-E
(ESREA- E)

UNDER VMS
ONLY
(QUEUE 1/0)

TAPE DRIVE
FUNCTIONAL
TIMER
(ESMAB)

TAPE
RELIABILITY
(ESMAA)

RM03
FUNCTIONAL
DIAGNOSTIC
(ESRDB)

RPOX
FUNCTIONAL
DIAGNOSTIC
(ESRBA)

DMC
EXERCISER
(ESDBB)

--11RP/RK/RM
DISK
FORMATTER
(ES RAB)

LOCAL TERMINAL
DIAGNOSTIC
(EST AA)

RP/RK/RM
DISK
RELIABILITY
(ESRAA)

MULTITERMINAL
DIAGNOSTIC
(ESTBA)

LINE PRINTER
DIAGNOSTIC
(ESAAA)

BUS
INTERACTION
(ESXBA)

SYSTEM
EXERCISER

TK-0606

Figure 1-2 VAX-11/780
Diagnostic System Program
Hierarchy (Sheet 1 of 2)

LSl-11 DIAGNOSTICS

CONSOLEBASED

STAND ALONE ONLY

DEDICATED
LSl-11
TESTS

POWER UP
TESTS
(IBM RESIDENT)

PROGRAM 1/0 MODE

CONSOLE
PROGRAM

CONSOLE 1/0 MODE

HARDCORE TESTS

MICRODIAGNOSTIC
PROGRAM

MICROTESTS

ODT

MOST BASIC LEVEL

HARDCORE
INSTRUCTION
TEST
(EVKAA)

LEVEL 4

-.J

CLUSTER
EXERCISER
(ESKAX)
STAND ALONE ONLY
(DIRECT 1/0)
LEVEL 3
RH780 (MBA)
DIAGNOSTIC
(ESCAA)

DW780(UBA)
DIAGNOSTIC
(ESCBA)

TK-0607

Figure 1-2 VAX-11/780
Diagnostic System Program
Hierarchy (Sheet 2 of 2)

be on the tape drive controller, the RH780 (MBA), or the KA780
(CPU). Proper use of the six levels of diagnostic programs should
enable the field service engineer to identify the failure quickly
and accurately.
1.4
DIAGNOSTIC SYSTEM EXECUTION ENVIRONMENTS
Most of the diagnostic programs must be run off-line (standalone).
In other words, they require exclusive use of the VAX-11/780
computer system and will not run under the VMS operating system.
Diagnostic programs in levels 3, 4, and the console level are of
this type (Figure 1-2). The diagnostic programs in level 2 can be
run off-line or on-line (under VMS).
Off-line
terminal.

diagnostics

must

run

from

the

console

On-line diagnostics may be run from any terminal on the
system and will share the computer system with other user
mode
programs.
Figure
1-3
shows
the
execution
environments required by the various diagnostic programs.
1.5
CONSOLE DIAGNOSTICS
On power up, a set of ROM resident tests verifies the proper
functioning of the LSI-11 within the console subsystem before the
console program is booted from the floppy disk. If the console
program cannot be booted, the ROM resident tests, together with
ODT, can be used to isolate the fault. For details see the
VAX-11/780 Diagnostic System User's Guide (EK-DS780-UG-001),
Appendix D. In addition, a set of dedicated LSI-11 diagnostics may
be used to perform in-depth tests on each component of the console
subsystem.
The console subsystem,
provides the basis for
functions:

in connect ion with the console program,
the diagnostic system with the following

Traditional lights and switch functions such as EXAMINE,
DEPOSIT, HALT, START, and single instruction
Diagnostic and maintenance functions, including the
capability to load diagnostic microcode into Writable
Control Store (WCS) , control execution, control single
step clock functions, and examine key system points via a
serial diagnostic visibility bus (V Bus), and to deposit
and examine data in locations in the VAX-11/780 main
memory and I/O space
Operator communication with the VAX-11/780 software.
The console program enables the operator to run microdiagnostics,
to load and run the diagnostic supervisor (in the standalone mode)
and the standalone macrodiagnostic programs
(using VAX-11/780
native code), and to boot the operating system.

1-8

UNDER
VMS

STAND ALONE

r - - ---,

r--~=;:--::S::L::-------,

\;~i~

POWER

TESTS -

OOT

\
/

CONSOLE
PROGRAM

LOAD FROM
CON SO LE FLOP PY

MICRODIAGNOSTICS
MONITOR

-'°

DIAGNOSTIC
SUPERVISOR

'I\
I \

LOAD FROM * *
SYSTEM DEVICE

MICRODIAGNOSTICS
HARD CORE TESTS
MICROTESTS
-GO CHAIN
- FAIL CHAIN

\ I

DIRECT 1/0 *

KA-11/780 CPU CLUSTER EXERCISER
RH-780 MBA DIAGNOSTIC
DW780 UBA DIAGNOSTIC
TM03/TEE16-TU77 TAPE DRIVE FUNC TIMER
RP06/FUNCTIONAL DIAGNOSTIC
RK611 DIAGNOSTIC PARTS A-E
RK06/RK07 DRIVE FUNC DIAGNOSTIC
RM03 DISKLESS DIAGNOSTIC
RM03 FUNCTIONAL DIAGNOSTIC
DR11-B DIAGNOSTIC
DZ11 DIAGNOSTIC

VAX/VMS

I ___ CONSOLE

DIAGNOSTIC
SUPERVISOR

HARDCORE
INSTRUCTION
TEST

I
DIAGNOSTIC
SUPERVISOR·

LOAD FROM
SYSTEM DEVICE

II
II

01/0 *

PROGRAM

01/0

TAPE RELIABILITY
RP/RK/RM DISK FORMATTER
RP/RK/RM DISK RELIABILITY
MULTITERMINAL EXERCISER
\
LOCAL TERMINAL DIAGNOSTIC
·
·
LINE PRINTER DIAGNOSTIC
\
BUS INTERACTION
CR11 CARO READER DIAGNOSTIC
\

EXER

L --------------~---------~-*THE NUMBER OF 1/0 DIAGNOSTIC PROGRAMS WILL GROW.

Figure 1-3 VAX-11/780
Diagnostic System,
Execution Environments

TK-0373

Note that when the console program is running in the LSI-11, it
will always be in one of two modes, console I/O mode or program
I/O mode. With the exception of the Control P (AP) command, the
console commands (console command language) listed in the help
files are available only when the console program is in the
console I/O mode.
In the console I/O mode, the console program interprets the
characters typed on the console terminal as console commands. In
the program I/O mode, however, the console program is transparent
to the operator. The console program passes characters from the
console terminal directly to the VAX-11/780 CPU for use by VMS or
the diagnostic supervisor.
Type Control
mode.

P to

switch

from

Type SET TERMINAL
program I/O mode.

PROGRAM

program
switch

I/O mode
from

console

I/O

mode

1.6
MICRODIAGNOSTIC PROGRAM
The microdiagnostic program provides module isolation for logic
failures within the CPU, floating-point accelerator and MOS memory
controllers. The program will detect stuck high/low logic
functions and open or grounded etch and wire interconnections. The
microdiagnostics are organized in a bootstrapping test sequence
(i.e., building blocks) of the console interface, CPU hardware,
cache-translation buffer, I-stream buffer, Synchronous Backplane
Interconnect (SBI), and memory controller and array. All detected
faults result in an error typeout indicating the smallest set of
modules to which the diagnostic can isolate the failure.
The microdiagnost ic program is initiated by one console command
and executed from the CPU cluster test facility. The test facility
consists of the console subsystem, console interface, Writable
Control Store (WCS), and the V Bus.
The microdiagnostic package consists of two major test divisions:
console adapter and hardcore, and microtests. Each test division
is controlled by an associated monitor that provides nondiagnostic
services to that division. Both test division monitors are
serviced by the console-resident microdiagnostic monitor. In
addition to loading the test monitors, the microdiagnostic monitor
retrieves microtest overlays from the floppy disk, loads test
sequences into WCS, performs test dispatching and sequencing,
performs error reporting, and manages fault isolation. The
microdiagnostic monitor also allows the operator microdiagnostic
test selection and execution options (Chapter 4). Figure 1-4 shows
overall monitor relationships and test sequencing.

1-10

MICRODIAGNOSTIC
MONITOR

•

HARDCORE
MONITOR

MICROTEST
MONITOR

TEST
SEQUENCE

• CONSOLE
ADAPTER

• DATA PATHS
• TRANSLATION
BUFFER

• MICRO
SEQUENCER

• CACHE

• wcs

• INSTRUCTION
BUFFER

• DATA PATH
SUBSET

• FPA OPTION
• SBI INTERFACE
• MEMORY
CONTROLLER
• MEMORY ARRAY
TK-0752

Figure 1-4

Monitor Relationships and Test Sequencing

1-11

1.6.1
Console Adapter and Hardcore Division
The adapter and hardcore division microdiagnostic is composed of a
test stream of pseudo-instructions and test data located on the
console floppy disk. Note that the pseudo-instructions are defined
specifically for the test stream. This division tests the console
adapter (CIB module), microsequencer, WCS, and a subset of the
data paths. The hardcore monitor is called into the console memory
by the microdiagnostic monitor. The hardcore monitor, in turn,
retrieves small blocks (+l.SK bytes) of test data from the floppy
into a cons o 1 e buffer , - and then cont r o 1 s exec u t ion • When the
current block has been completed, the hardcore monitor overlays
this block with a new test block. The test data port ion of the
test stream is comprised of data words and lists of VAX-11/780
microinstructions. The microinstructions are loaded into the WCS
and executed in single bus cycle or single time-state modes.
When an error is detected, an error header message is typed. Then,
if the HALTD flag is not set, a trace message is typed and
additional code is executed to isolate the fault. This additional
testing will normally consist of V Bus compare instructions.
Figure 1-5 shows monitor residency and the basic flow of the
console adapter and hardcore tests.
1.6.2
Microtest Division
The microtest division completes testing of the CPU not covered by
the hardcore division, and provides isolation to a failing module.
The microtests, which are executed under control of the microtest
monitor, are divided into two subdivisions: GO chain and FAIL
cha in. The GO cha in consists of m ic retests loaded into WCS and
executed at full speed. The purpose of the GO chain is to detect
an error. If an error is detected, control is passed to the FAIL
chain, which isolates the error and reports the failing module
through the microdiagnostic monitor. Note that the FAIL chain is
executed only on detection of an error.
The GO chain consists of a series of WCS overlays. Each overlay is
approximately lK microwords in length and will contain one or more
microtests. Initially, the microdiagnostic monitor loads the first
over lay into WCS; that overlay is then executed. If no error is
detected, the next overlay is loaded into WCS and executed. This
sequence continues until each test in each overlay has been
executed, or until an error is detected.
When the GO chain detects an error, execution of the microtest
that detected the error is suspended. The error microtest address
is saved and used by the FAIL chain to restart microtest execution
to recreate the conditions that detected the error.
The FAIL chain reenters the failing microtest and begins fault
i sol a ti on. The microtest is clocked a specific number of tic ks
from the error address and then certain V Bus signals are
processed. If the V Bus signals identify the faulty module, an
error report is made through the microdiagnostic monitor. If these

1-12

CONSOLE MEMORY
MICRODIAGNOSTIC MONITOR

CO RESIDENT WITH
MICRODIAGNOSTIC
MONITOR

-------

ERROR
REPORT

LOAD AND
SERVICE CALLS

HARDCORE
MONITOR

L _______ J
SERVICE CALLS

TEST
STREAM

CONSOLE
BUFFER
EXECUTION

ERROR
REPORT

wcs
EXECUTION

YES

EXECUTE
NEW
TEST

Figure 1-5

TK-0753

Hardcore Monitor Residency/Test Flow

1-13

signals do not identify the error, additional V Bus signals are
processed. In the case of an intermittent error which is not
reproduced during FAIL chain execution, a report is printed that
lists the modules involved in the failing GO chain microtest.
Figure 1-6 shows monitor residency and the basic test flow.
1.7
MACRODIAGNOSTIC PROGRAMS
The macrodiagnostic programs are written in VAX-11 MACRO and
assembled in VAX-11 native code. Level 2, 2R, and 3 programs do
not run independently; they must always be loaded and executed
with the diagnostic supervisor.
1.7.1
Diagnostic Supervisor
The diagnostic supervisor provides a framework that supports each
of the macrodiagnostic programs, one at a time. It operates in
three environments and provides two major functions. Two of these
environments, cluster environment
(CE)
and system environment
(SE), constitute the standalone mode. The diagnostic supervisor
operates in the user environment (USE) when it runs under the VMS
operating system. In each of these environments different modules
w i thin the d i a g nos t i c super v i so r are act iv ate d • The f i rs t ma j o r
function of the diagnostic supervisor is the interpretation of the
c ornm and 1 in e typed on the opera to r ' s term in a 1 • The co mm and 1 i n e
interpreter
(CLI) portion of the supervisor performs this
function,
enabling
the
operator
to
control
the
loading,
sequencing, and execution of diagnostic test programs. The program
interface
(PGI) performs the second major function of the
supervisor, providing a set of common services required by some or
a 11 di a g n 0 st i c programs • The PG I services inc 1 ud e operator
interaction routines, error message formatting, memory management,
and I/O request handling. Notice that the operator can communicate
w i th the d i ag nos ti c program on 1 y th r o ugh the c LI and the PG I
message service in the supervisor.
The supervisor supports programs that provide their own device
interfaces (direct I/O) and programs that require I/O services.
The direct I/O diagnostic programs must be run in the standalone
mode
(cluster environment and system environment), since VMS
inhibits direct access to peripheral devices. Programs that do not
directly access the peripheral devices under test rely on queue
I/O system services. Both VMS and the diagnostic supervisor
provide queue I/O system services, so that these programs can run
in either the standalone mode (in the system environment) or the
user mode
(user environment, under VMS). When the diagnostic
programs requiring queue I/O services are run in the user mode,
the supervisor passes the queue I/O requests directly to VMS. When
queue I/O diagnostic programs are run standalone, the supervisor
emulates the VMS operating system, providing the queue I/O system
services. Figure 1-7 shows the functions of the diagnostic
supervisor in the three macrodiagnostic operating environments.

1-14

CONSOLE MEMORY
MICRODIAGNOSTICr---ti---+---- ERROR/TRACE
MONITOR
REPORT
CORESIDENT WITH
MICRO DIAGNOSTIC
MONITOR

LOAD AND
SERVICE CALLS
MICROTEST
MONITOR

I
__ _J
SERVICE CALLS

EXECUTE
NEXT
OVERLAY

GO
CHAIN

wcs
EXECUTION

ERROR
REPORT

FAIL CHAIN
VBUS SIGNAL
EXECUTION

TRACE
REPORT

YES

ADDITIONAL
VBUS SIGNAL
PROCESSING

TK-0738

Figure 1-6

Microtest Monitor Residency/Test Flow

1-15

CL.,USTE R ENVIRONMENT
(CLUSTER EXERCISER
RH780 DIAGNOSTIC
DW780 DIAGNOSTIC)

DIAGNOSTIC
SUPERVISOR

---

DIAGNOSTIC
TEST
PROGRAM

VAX-11/780

----

PGI

----

OPERATOR
TERMINAL

VMS
SERVICES
_iVECTORS)

CPU
CLUSTER

CHANNEL
SERVICES
~---"""""'I

UUT

SYSTEM ENVIRONMENT
(DIRECT 1/0 PERIPHERAL
DIAGNOSTICS, STAND ALONE)

DIAGNOSTIC
SUPERVISOR

--...

VAX-111780

l.-

....

PGI

'--

VMS
SERVICES
(VECTORS)

DIAGNOSTIC
TEST
PROGRAM

....

--...

CHANNEL
SERVICES

OPERATOR
TERMINAL

CPU
CLUSTER

----

..-

-..

UUT
TK-0746A

Figure

1-7

Functions

the Diagnostic
(Sheet 1 of 2)

1-16

Supervisor

Environments

(O 1/0 PERIPHERAL
DIAGNOSTICS,
STAND ALONE)

-DIAGNOSTIC
...._

DIAGNOSTIC
SUPERVISOR

PGI

i.....

..
...

VAX-11/780

- OPERATOR
TERMINAL

.......i

- --

i.....

Q 1/0 DRIVERS

VMS SERVICES

......

f4-,

CPU CLUSTER

TEST
PROGRAM
CHANNEL
SERVICES

::::tJ

UUT

USER
ENVIRONMENT

0 1/0 PERIPHERAL
DIAGNOSTICS
UNDER VMS

DIAGNOSTIC
SUPERVISOR

-DIAGNOSTIC
r-TEST
PROGRAM

PGI

VMS
SERVICES
(VECTORS)

VMS

VAX-111780

---

-..

-- OPERATING
SYSTEM

CPU
CLUSTER

UUT

VMS

OPERATOR
TERMINAL

CHANNEL
SERVICES

TK-07468

Figure

1-7

Functions

the Diagnostic
(Sheet 2 of 2)

1-17

Supervisor

Environments

1.7.2
Cluster Diagnostic Programs
The CPU cluster exerciser, the RH780 (MBA) diagnostic program, and
the DW780 (UBA) diagnostic program test the VAX-11/780 cluster
hardware. They run under the cluster environment portion of the
diagnostic supervisor, in the standalone mode.
1. 7.2.1 CPU Cluster Exerciser Package -- The cluster exerciser
package consists of three diagnostic programs. The package
provides a comprehensive functional test of the CPU cluster,
including the CPU, the Unibus and Massbus adapters, and memory.
The first program (ESKAX) is the quick verify portion of the CPU
cluster exerciser package. The second program (ESKAY) tests the
native mode instruction set of the VAX-11/780. EXKAZ, the third
program in the package, checks memory management and the PDP-11
instruction set (in compatability mode).

The CPU cluster exerciser programs identify failing functions and
failing subsystems. For further fault isolation the operator
should run the microdiagnostic program or restrict the desired CPU
cluster exerciser program to the minimum number of modules which
will detect the failure, through commands to the diagnostic
supervisor.
1.7.2.2 RH780 (MBA) Diagnostic Program
The RH780
(MBA)
diagnostic program tests the majority of the MBA logic regardless
of the type of peripheral device attached to the Massbus. Although
the program does not provide explicit component level fault
isolation, every detectable error
is associated with an
operator-selectable scope loop. Diagnosis of attached devices is
not attempted. Verification of the Massbus transceivers and cables
is possible with a Massbus exerciser (MBE, RHll-TB) attached to
the Massbus. Use of an MBE on the Massbus also allows verification
of the MBA ability to perform high speed block transfers. Note
that either a device or a bus terminator must be attached to the
Massbus to enable program execution. The program tests the MBA at
three levels.
1.

The first level checks basic functions. The functions
tested are those which are necessary for subsequent,
detailed fault detection. The objective is to locate
functional failures prior to testing for explicit bit
failures. Map register access, virtual address register
access, and correct data input buffer byte selection are
tested at this level.

The second level of testing locates bit failures (stuck
high/low). The program toggles bits directly accessible
to the CPU, and it sets and clears bits indirectly by
setting up specific commands and conditions.

1-18

The third level determines the ability of the MBA to meet
system demands. The program performs block transfers
using the MBA wraparound features. These block transfers
are executed in the maintenance mode and ensure that the
MBA will support data transfers typically associated with
system software.
In addition, the program tests the
ability of the MBA to interrupt the CPU under all legal
conditions.

1. 7. 2. 3 DW78f2J (UBA) Diagnostic Program -- Like the RH780 (MBA)
diagnostic program, the DW780 (UBA) diagnostic program tests most
of the UBA logic. Every detectable error is associated with an
operator-selectable scope loop. The program does not at tempt to
test devices attached to the Unibus. However, if a Unibus
exerciser is attached to the Unibus, the program will verify the
integrity of the Unibus transceivers and the ability of the UBA to
respond to device-initiated functions. The program tests the UBA
at seven levels.
1.

The program tests the basic functions necessary for
subsequent fault detection: the addressability of the UBA
registers, their initial states, and whether they can be
read and written.

The program tests the RAM addressing capability of the
UBA logic (accessing map registers, data path registers,
and BRS VRs) .

Power-fail and interrupt functions of the UBA are tested
next.

The program creates and tests all error conditions.

Extensive data transfer tests check the map registers,
the direct data path, the buffered data paths, the data
path registers, the Unibus address and data 1 ines, and
the microsequencer.

The device tests check all types of data transfer on the
Unibus: DATI, DATIP, DATO, DATOB initiated by the UBA and
by the UBE. Interrupts from the UBE to the CPU are also
tested at the four BR levels.

The contention logic test checks for race conditions when
the four microsequencer select lines (UBATT SEL, SB SEL,
DMA SEL, FILE WRITE SEL) are asserted at about the same
time.

1-19

1.8
PERIPHERAL DIAGNOSTIC PROGRAMS
In accordance with the structure of the diagnostic system as a
whole, the peripheral diagnostic programs are organized in a
hierarchy. Repair and functional level programs are designed to
test specific peripheral devices. These programs (with the
exception of the line printer and terminal diagnostics) must be
executed in the standalone mode under the system environment (SE)
s er vi c es of the super v i so r , s i nc e they prov i de the i r own access
(direct I/0) to the devices under test. The diagnostic programs
which rely on VMS, or the supervisor, for access to the uni ts
under test (queue I/O) are each designed to test a range of
peripheral device types. For example, the disk reliability program
(ESRAA) will test all disk drive types supported by the VMS
operating system.
On error detection, the repair level diagnostic programs will call
out both the failing device controller module and the failing
function, dump the contents of relevant registers, and list
expected and received data patterns. The functional level programs
provide register dumps and call out the failing function when an
error is detected. The rel iabi 1 i ty and formatter level programs
provide more detailed information on the failing function in
addition to the register dumps.
The system exe re i ser program tests the integrity of the major
system buses ( i • e • , SB I , Mass bus , Unibus) under heavy I IO
activity, and it highlights any interaction problems that result.
The program should be run as a dedicated process under VMS. No
other program may run concurrently or compete for system
resources, since the program requires the use of all system
resources.
1.9
OPERATOR/VAX-11/780 COMMUNICATION
The operator communicates with the VAX-11/780 computer through the
console subsystem. The console subsystem provides a programmed
interface between the console terminal and the VAX-11/780 hardware
and software, including the diagnostic system. The console
, subsystem hardware consists of an LSI-11 microprocessor (11/03), a
single floppy disk drive and controller, a terminal and two serial
line units, a VAX-11/780 CPU console interface (CIB), and a
control panel on the VAX-11/780 CPU cabinet. The console program
includes a console command language and the software utilities
that provide operator console functions. These functions are
required for VMS and diagnostic support. The paragraphs that
follow introduce the basic console functions. Refer to Chapter 2
for a detailed description of the console command language.
1.9.1
Console Terminal Modes
The console terminal serves as the console program's I/O device
and as a VMS operator terminal. The console program has two
operating modes: console I/O mode and program I/O mode.
In console I/O mode, the terminal serves as the operator interface
to the console panel functions, CPU debug functions, and CPU
kernel test functions. In this mode console terminal input is not
1-20

passed to the VAX ISP-level software. All terminal input is
interpreted by the LSI-11, and appropriate console functions are
invoked.
In program I/O mode the terminal serves as a VMS operator
terminal. All terminal input is passed, character by character, to
the ISP-level software. All validity checking, etc. is performed
by VMS. The console program is transparent to the VAX-11/780
software. All terminal output from the software is passed directly
to the console terminal.
1.9.2
Console Panel Equivalent Functions
The functions in this group are those normally available through a
traditional console panel. These functions include ISP-level
program and CPU clock controls, and display and modification of
memory elements.
1.9.2.1 Program Control -- The console can initialize the CPU by
setting certain logic to a defined state. It can initiate
ISP-level instruction execution at a point specified by the
program counter, as well as terminate instruction execution. In
addition, the console can bootstrap the system by loading memory
with a specific file from the system load device, and initiate
instruction execution at a predefined address after the load. The
console can also stop ISP level instruction execution.
1.9.2.2 Memory Element Display and Modification -- The console
allows display and modification of memory elements in the
VAX-11/780 including main memory, I/O, general, and internal
register addressing space. The address spaces can be accessed,
read, and written in the quantities specified below:
a.

Main memory
quantities

elements:

byte,

CPU general registers (R0--R 13, SP,
register space: longword quantity

CPU processor register space: longword quantity

I/O registers: byte, word, longword quantities depending
on register data length

ID bus registers: longword quantity

VAX-11/780 V Bus (Visibility Bus) channels
displayed (V Bus channels are read-only)

VAX-11/780 main memory and/or Writable Control Store
(WCS) can be loaded from files on the console subsystem
floppy disk.

1-21

word,

longword,

quadword

PC) ,

processor

and

can

1.9.2.3 Clock Control -- The CPU clock can be controlled by the
console to provide single step clock mode for use in hardware or
software debugging. The control modes available include single
instruction step, single SBI bus cycle step, and single SBI time
state step modes.
Single instruction step mode allows ISP-level programs to execute
one instruction at a time. This mode causes the CPU to enter the
halt state after the instruction execution.
Single SBI bus cycle step mode causes the CPU clock to stop each
time SBI time state 0 (T0) is asserted. T0 remains asserted until
a control signal from the console causes the clock to resume
operation. The clock ticks until the next SBI T0.
Single SBI time state step mode causes the CPU clock to assert and
hold a time state (T0, Tl, T2, or T3) until a control signal from
the console causes the next time state to be asserted and held.
1.9.3
Console Control Functions
The console control functions allow control of numeric radices,
addressing modes, and data length, and provide for displaying
console and CPU status. Functions are also provided that repeat
commands and link multiple commands into a single executable
command list. In addition, the console provides a means to control
the number of fill characters to be added after special characters
are sent to the console terminal.
1.9.3.1 Default Settings -- The console allows specification of
defaults for addressing modes, radix of numeric input and output,
and the data length of addressable memory elements. Any default
setting can be overridden within the context of a console command.

The default addressing modes can be set for virtual,
physical, ID Bus, V Bus, general register, or internal
(processor) register.

Default radices for console numeric input and output can
be set to octal, decimal, or hexadecimal radix.

Defaults for memory element data lengths can be set for
byte, word, longword, and quadword.

Power-up defaults -Address Type
Radix
Data Length

=
=
=

1-22

Physical
Hexadec ima 1
Longword (32 Bits)

1.9.3.2 Status Displays
The console provides a means to
display CPU and console subsystem status. The CPU status includes
the stop/run state of the instruction set processor, the current
clock step mode, and the state of the Stop on Microbreak Match
Enable
(SOMM). Console subsystem status includes the current
setting of all console defaults and the number of terminal fill
characters.
1.9.3.3 Command Linking and Repeating -- The console provides a
facility that allows multiple commands to be linked into a single
executable list. Commands to be linked are entered into an
internal console queue. The console operator can specify execution
of the command queue one pass at a time. Or, the queue may be
executed continuously. This facility allows the diagnostic user to
create short routines of console commands for use in hardware
debugging operations.
The console also provides a facility to continuously execute a
single command or list of commands. Once initiated, command
execution continues until terminated by the operator. The repeat
faci 1 i ty allows maintenance personnel to scope the operation of
CPU and subsystem logic invoked by console commands.
1.9.3.4 Real-Time Delays -- The console provides a facility f6r
introducing real-time delays of varying duration between the
execution of console commands linked with the command linking
facility. This function has no effect on the CPU, but only delays
the console' s processing of the next sequential command in the
command queue. The delay facility is provided for use after
console commands that invoke CPU functions which require time to
complete (e.g., initialization).

1-23

CHAPTER 2
CONSOLE PROGRAM AND CONTROL DESCRIPTION
This chapter describes the console command language and associated
command faci 1 i ti es. Where appropriate, examples of command usage
are included. Also included are all applicable console error
messages.

2.1
CONSOLE PROGRAM OVERVIEW
The following paragraphs provide a basic overview of the console
software modules. Note that the services provided by the console
are contained in the LSI-11 4K ROM and BK RAM. The console
provides services for console control, operator interface,
microdiagnostic execution, VMS support functions and remote
diagnosis.
2.1.1
Command Getter
The basic functions of this module are to retrieve a command line
from the console terminal (get a command line routine), and
provide a check point (or wait) loop for the console program
(console null loop).
The program spends the majority of its time in the null loop,
which consists of a series of test points and conditional branches
(e.g., bootstrap initiated, VAX-11/780 CPU halted, etc.). Should
any of these functions be active (i.e. , flag set) the program
performs a branch to the routine required to service the request
initiated by that flag.

2.1.2
Parser and Parser Tables
The parser module decodes the command typed on the console
terminal and provides a pointer to the appropriate routine to
execute the command. The parser manipulates the command line to
condition it for decoding (e.g., discarding leading blanks and
checking for a delimiter in the command input string). The command
is decoded through a set of syntax check trees that provide
pointers to the appropriate execution routine within the command
execution module. Any data required for command execution has been
set up in tables included as part of the parser.
2.1.3
Command Executor Module
The command execution pointer from the parser is passed to the
command execution module entry point. This entry point provides a
pointer (i.e., starting address) to the appropriate command
execution routine (e.g., DO BOOT, PERFORM QUAD CLEAR). The basic
sequence of module action is:
a.
b.
c.

Apply switches or defaults for
data length.
Execute command routine.
Test for repeat function.

2-1

radix, address space, and

If a repeat function is specified, the routine monitors the
console for the control character ( "C) required to terminate the
loop.
The module also supplies the required subroutines to support the
execution functions (e.g., open a file, load a file). Following
command execution, control is passed to the console null loop
within the command getter module.
2.1.4
Additional Services
In addition to the command decoding and execution functions,
console provides several other services.

the

Remote support is provided to allow console access from a remote
terminal or computer. The facility also enables communication
between local and remote operators, as well as transfer of console
control between local and remote operators.
VMS services are also provided. These services include routines
for terminal support and the associated drivers, as well as a file
service for the floppy drive and its associated drivers. The code
for some of these services is contained in the ROM as well as the
RAM. These services are provided through emulator traps.
The console software also includes the basic LSI-11 processor and
memory tests, that are executed on each power-up and bootstrap,
and the primary bootstrap routine for the floppy.
2.2
COMMAND TERMS AND SYMBOLS
Table 2-1 provides a summary of terms and symbols used to describe
the syntax of the console commands.
Table 2-1

Term and Symbol Definitions

Term/Symbol

Definition

< >

Used to denote a category name (label)
e.g., category name <address> represents
a valid address
Used
to
indicate
the
Exclusive
OR
opera t ion ( i • e • , s e 1 e ct ion of par am et er s
within a command 1 ine). For example,
<A>!<B> means either <A> or <B> but not
both is to be selected

)

Used
to
indicate
that
one
of
the
syntactic units of the expression is to
be selected

[ ]

Used
to
indicate
the
part
of
an
expression that is optional e.g., WAIT [
indicates that the wait command takes
an optional count argument

(

2-2

Table 2-1

Term and Symbol Definitions (Cont)

Term/Symbol

Definition

<blank>

Represents one or more spaces or tabs

<count>

Represents a numeric count

Indicates one or more occurrences
the category indicated by XYZ

Represents an address argument

<data>

Represents a numeric argument

Represents a command modifier (switch)

Represents the
string '>>>'

Represents the linking prompt '<<<'

<CR>

Represents
return

<LF>

Represents a console terminal line feed

Delimits a command from its qualifiers

Represents the default address when used
as an address argument in an examine or
deposit command (The default address is
the last address used plus the current
data length in bytes.)

Used as an address argument in an examine
or deposit command and represents the
last address referenced.

2.2.1
Notation Examples
EXAMINE [ <qualifier - list>

console's

console

input

terminal

from

prompt

carriage

[<blank> <address> ]

An examine command explanation follows.
a.

An examine command may optionally contain a
or more qualifiers.

An examine command may optionally contain an address
argument. If the address is specified it must be preceded
by one or more spaces or tabs.

2-3

list of one

Following is a list of valid examine commands:
EXAMINE
EXAMINE/BYTE/VIRTUAL
EXAMINE <space> 123456
EXAMINE <tab> 123456
EXAMINE/WORD <space> 123456
EXAMINE/WORD <space> <tab> 123456
2.2.2
Command Abbreviations
Console command words may be abbreviated by typing only enough
characters to identify each command word. The minimum abbreviation
for each command is specified in parentheses in each command
description paragraph title.
Example
EXAMINE/VIRTUAL/BYTE 1234
may be abbreviated to:
E/V/B 1234

2.3
CONSOLE COMMAND DESCRIPTIONS
Each console command description is divided into three, four, or
five descriptive segments, depending on the particular command.
The descriptive segments are:
a.

Syntax: describes the command structure

Command description: a brief paragraph describing command
operation, general restrictions, or available options

Response: a description of the console program response
to the specified command

Qualifiers: a list of applicable command modifiers

Options: a list of applicable command options.

The descriptive segments use the terms and symbols defined
Tab1e 2-1. Note that every command (or command 1 ine) must
terminated with a <CR>.

in
be

2.3.1
Boot Command (B)
Syntax: BOOT [ <device name> ] <CR>
The boot command initiates a VAX-11/780 system bootstrap sequence.
The command may support bootstrap operations from a set of
alternate system devices.
<device name> has the following format:
two-letter device mnemonic (e.g., DX for
one-digit unit number.
2-4

DDn, where DD
floppy) , and n

is
is

a
a

If no <device name> is given with the boot command, the console
will perform the boo_t sequence for the default system device by
executing an indirect command file named DEFBOO.CMD. This indirect
file contains the necessary console commands to boot from
whichever device is chosen to be the default system device.
If <device name> is given with the command, the
execute an indirect command file named DDNBOO.CMD,
the <device name> given.

console wi 11
where DDN is

Example
BOOT RP0 -- will cause the console to execute an indirect
command file named RP0BOO.CMD {console enters program I/O
mode after executing the command file) •
Bootstraps from devices other than the system default device are
performed by indirect command files containing the console
commands necessary to boot an alternate device. After successful
CPU bootstrap completion, a response from VMS will be displayed on
the console terminal.
2.3.2
Clear Command {CL)
Syntax: Clear<BLANK>(SOMM ! Step)
CLEAR SOMM

The Stop on Microbreak Match {SOMM) enable
the console interface board is cleared
(disabled) •

CLEAR STEP

Any existing clock step mode (single bus cycle,
single time state, single instruction)
is
cleared, and the VAX-11/780 CPU clock will be in
the normal {free-running) mode.

Response: <CR><LF><CONSOLE-PROMPT>
2.3.3
Continue Command (C)
Syntax: CONTINUE <CR>
The continue command causes the VAX-11/780 CPU to begin
instruction execution at the address currently contained in the
CPU program counter (PC). Note that CPU initialization is not
performed. The console enters the program I/O mode after issuing
the continue command.
Response: <CR> <LF> (console enters program I/O mode)
2.3.4
Deposit Command (D)
Syntax: DEPOSIT [ <qualifier <data> <CR>

list> ]

Qualifiers: /BYTE,
/WORD, /LONG,
/QUAD,
/NEXT,
/VIRTUAL,
/PHYSICAL, /V BUS, /INTERNAL, /GENERAL. {Refer to Paragraph 2. 7
for description of defaults.)
2-5

The deposit command writes (deposits) <data> into the address
spec i f i e d • The add res s space used wi 11 depend on the qua 1 i f i er s
specified with the command. If no qualifiers are used, the current
address type default will determine the address space to be used.
Response: <CR> <LF> <input prompt>
The <address> argument may also be one of the symbolic addresses
defined in Table 2-2.
Table 2-2

Deposit Symbolic Addresses

Symbol

Definition

PSL

Deposits to the processor status longword

Deposits to
register F)

the

program

counter

(general

Deposits to
register E)

the

stack

pointer

(general

Deposits to the location immediately following
the last location referenced. For physical and
virtual references the location referenced
will be the last address plus n, where n = 1
for byte, 2 for word, 4 for longword, 8 for
quadword. For all other address spaces, n is
always equal to 1.
Deposits to the location immediately preceding
the last location referenced

Deposits to the location last referenced

Deposits to the address represented
last data examined or deposited.

the

Example:

E SP

Examines stack pointer

D @ <data>

Deposits <data> to the location specified by
the contents of the stack pointer.

2.3.5
Enable DXl: Command
Syntax: Enable DXl:
Qualifiers: None
Enable console
dual floppies.

software

access

2-6

floppy

those

systems with

Response: <CR><LF> <INPUT-PROMPT>
2.3.6
Examine Command (E)
Syntax: EXAMINE [ <qualifier - list>

[ <blank> <address> ] <CR>

Qualifiers: /BYTE'
/WORD,
/LONG'
/QUAD,
/NEXT'
/PHYSICAL, /ID BUS, /V BUS, /INTERNAL, /GENERAL.
Paragraph 2.7 for description of defaults.)

/VIRTUAL,
(Refer to

The examine command reads and displays the contents
specified <address>. If no <address> is specified, the
<default address> is examined.

of the
current

The <address> argument may also be one of the symbolic addresses
defined in Table 2-3.
Table 2-3

Examine Symbolic Address

Symbol

Definition

PSL

Displays the processor status longword

Displays the program counter (general register
F}
Displays

the

stack pointer

(general

Displays the location immediately
the last location referenced.

fnllowing

Displays the location immediately
the last location referenced

preceding

Displays the last location referenced

Displays the location whose <address>
last data examined or deposited.

Response: <CR> <LF> <tab> <address
<data> <CR> <LF> <input prompt>

space

identifier>

Sample responses (console output underlined}
>>> EXAMINE/PHYSICAL 1234
P 00001234
ABCDEF89
>>> EXAMINE/VIRTUAL 1234
p 00005634
01234567
NOTE
The translated physical address
displayed for virtual examines.
>>> EXAMINE/G 0
G 00000000

98765432; GPR 0
2-7

the

2.3.7
Halt Command (H)
Syntax: HALT <CR>
The halt command causes the VAX-11/780 CPU ISP to stop instruction
execution after completing execution of the instruction being
executed, when the console presents the halt request to the
VAX-11/780 CPU.
Response: (VAX-11/780 CPU indicates it has stopped) <CR> <LF>
<tab> HALTED AT <contents of VAX-11/780 CPU PC> <CR> <LF> <input
prompt>
2.3.8
Help Command (HE)
Syntax: HELP <CR>
The console opens an indirect command file that displays a console
help file, CONSOLE.HLP. The help file contains a description of
all console commands and console abbreviation rules, and it lists
the names of all other help files that may be displayed.
Response: Help file printed on console terminal.
2.3.9
Initialize Command (I)
Syntax: INITIALIZE <CR>
This command causes VAX-11/780 CPU system initialization.
Response: <CR> <LF> <tab> INIT SEQ DONE <er> <LF> <input prompt>
2.3.10
LINK Command (LI)
Syntax: Link
Qualifiers: None
Link causes the console to begin command linking. Console prints
reversed prompt to indicate linking. All commands typed by user
are then stored in an indirect command file for later execution.
Control C.terminates linking.
Response: <CR><LF><REVERSE-PROMPT>
(Refer to Paragraph 2.9 for further details.)
2.3.11
Load command (LO)
Syntax: LOAD [<qualifier list>] <blank> <file specification> <CR>
The load command is used to read f i 1 e data from the console' s
floppy disk to the VAX-11/780 main memory, or Writable Control
Store (WCS). The applicable qualifiers are defined in Table 2-4.
If no qualifier is given with the load command, physical main
memory is loaded.

2-8

Table 2-4

Load Command Qualifiers

Qualifier

Definition

/START: <address>

This qualifier specifies a starting
address for
the
load.
If no start
qualifier is given, the console will
start loading at address 0.

/WCS

This qualifier specifies that the WCS is
to be loaded.

2.3.12
Perform Command (P)
Syntax: Perform
Qualifiers: None
The perform command executes a file of linked commands previously
generated by a link command.
Response: <dependent on commands linked>
2.3.13
Quad Clear Command (Q)
Syntax: QCLEAR <blank> <physical address> <CR>
The quad clear command clears the quadword at the <address>
specified. The command is used to clear an uncorrectable ECC
e r r or • The <address> i s a 1 ways interpreted as a physical main
memory location. The <address> given is forced to a quadword
boundary by the unconditional clearing of the three low-order
address bits.
2.3.14
Reboot Command (REB)
Syntax: REBOOT
Qualifiers: None
This command causes a console software reload, without disturbing
the VAX-11/780.
Response: <console start-up display>

2-9

2.3.15
Repeat Command {R)
Syntax: REPEAT <console command> <CR>
A repeat command causes the console to repeatedly execute the
specified <console command> unti 1 execution is terminated by a
Control C ("'C) (Paragraph 2.8). Any valid console command may be
specified for <console command> with the exception of the repeat
command.
Response: Dependent on command specified.

2.3.16
Syntax:

Set Command {SE)
SET <blank> DEFAULT [<blank> <default option>] <CR>
or
SET <blank> STEP [<blank> <step option>] <CR>
or
SET <blank> TERMINAL <blank> {fill: <count>! PROGRAM)
<CR>
or
SET <blank> SOMM <CR>
or
SET <blank> CLOCK [<blank> (SLOW! FAST! NORMAL)] <CR>
or
SET RELOCATION: <data> <CR>

Response: <CR> <LF> <input prompt> (for all commands)
The set default command sets console default for radix of console
numeric input and output, address type, and data length. The
console will apply defaults when a console command does not
explicitly specify radix, address type, or data length. A set
default command with no options specified will set all default
settings to the power-up state. Applicable default options are
listed in Table 2-5.
Table 2-5

Set Default Command Options

Option

Format

Specification

Address Default
Options

Physical
Virtual
General
Internal
ID Bus
V Bus

Sets default addressing mode
as specified

Data Default
Options

Long
Byte
Word
Quad

Sets default data length as
specified

Default Radix
Options

Hex
Octal

Sets default radix for terminal
numeric I/O to radix specified

2-10

The set step command sets the VAX-11/780 CPU processor clock mode
to the mode specified. The applicable modes are listed in Table
2-6.
Table 2-6

Set Step Command Options

Option

Specification

Step Step Instruction

Sets CPU clock mode
instruction _step mode

Set Step Bus

Sets CPU clock mode
cycle step mode

single

SBI

Set Step State

Sets CPU clock mode
time state step mode

single

SBI

single

The set terminal command allows the selection of two parameters.
a.

Set Terminal Fill: <count> = The count specifies the
number of fill characters to be added after special
characters (e.g., prompts) are transmitted to the console
terminal.

Set Terminal Program = The
program I/O mode.

console

terminal

enters

the

The set clock command sets the VAX-11/780 CPU clock to a frequency
specified by one of the arguments (Fast, Slow, Normal) within the
command where:
Fast = 10.525 MHz
Slow= 8.925 MHz
Normal (or no argument) = 10.0 MHz
The set S OMM command sets the Stop on Mic rob r ea k Match ( S OMM)
enable on the console interface board (CIB). When SOMM is set, if
the contents of the VAX-11/780 micro PC ever become equal to the
contents of the microbreak match register (ID register 21), the
CPU clock is stopped.
The set relocation command deposits <data> to the console's
relocation register. The contents of the relocation register are
added to the effective address of all virtual and physical memory
examines and deposits.
Response: <CR><LF><input-prompt>

2-11

2.3.17
Show Command (SH)
Syntax: SHOW <CR>
The show command will cause the console terminal to display:
a.

The current default settings for data length, address
type, and radix of address and data inputs and outputs.

The terminal fill character count.

The VAX-11/780 CPU status including
and current clock mode setting.

the

run/halt

state

2.3.18
Start Command (S)
The two start command formats are described below.
Syntax: START <blank> <address> <CR>
This format performs the equivalent of the following sequence of
console commands:
1.

Performs a VAX-11/780 CPU initialization (>>> INIT).

<address> is deposited
DEPOSIT PC <address>).

A continue function is issued to begin
instruction execution (>>> CONTINUE) •

into

the

VAX-11/780

Response: <CR><LF> (console enters program I/O mode)

(>>>
CPU

(for START)

Syntax: START/WCS <blank> <address>
This format performs the equivalent of the following
commands:
1.
2.

sequence of

<address> is deposited to the VAX-11/780 micro PC.
CPU clock is started in free-running mode.

Response: <CR><LF> <input prompt>

(for START/WCS)

2.3.19
Next Command (N)
Syntax: NEXT [<blank> <count>] <CR>
The next command causes the VAX-11/780 CPU clock to step the
number of times indicated by <count>. The type of step performed
by the clock is determined by the current state of the CPU clock
mode, as set by a previous set step command. A next command issued
while the VAX-11/780 CPU is in normal (free-running) mode will
default to single instruction step mode for the duration of the
command.

2-12

The console enters program I/O mode immediately before issuing the
step, and reenters console I/O mode as soon as the step is
completed. Step-dependent responses are displayed on the console
terminal after the completion of each of the count steps as
specified below.
a.

Single instruction step:
<CR> <LF> <tab> HALTED AT <contents of PC>

Single bus cycle step:
<CR> <LF> <tab> CPT0 UPC = <contents of UPC>

Single time state step:
<CR> <LF> <tab> CPTn (where n = 1, 2, or 3) or
<CR> <LF> <tab> CPT0 UPC = <contents of UPC>

If no <count> is specified, one step is performed, and the console
en t e r s th e spa c e b a r s t e p mod e • Wh i 1 e i n th i s mod e , ea ch
depression of the space bar causes one execution of the step
option currently enabled
(i.e., bus cycle,
time state,
instruction) •
A next command with an argument wi 11 not enable the space bar
feature. For example, NEXT 2 will cause two steps to be executed;
the console will then prompt for another command.
An input of any character except SPACE will cause an exit from the
space bar step mode.
2.3.21
Test Command (T)
Syntax: TEST [/COMMAND] <CR>

This command invokes the microdiagnostic monitor program. If no
/COMMAND qualifier is issued with the command, microdiagnostic
exec u t i on beg i n s i mm e d i ate 1 y • I f mi c rod i a g no s t i c t est i n g i s
completed successfully (i.e., no errors detected) the console
program is invoked automatically.
The COMMAND qualifier is used to cause the microdiagnostic monitor
to enter its command mode and wait for operator input before
initiating microdiagnostic execution.
2.3.21
Unjam Command (U)
Syntax: UNJAM <CR>

This command initiates an SBI unjam operation.
Response: >>>
2.3.22
Wait Command (WA)
Syntax: WAIT <blank> DONE

The wait command has no effect unless it is executed from an
indirect command file. When it is executed from an indirect
2-13

command file, it causes further execution of the command file
be suspended until one of the following occurs:

A DONE signal is received from a program running in the
VAX-11/780 CPU. On receipt of DONE, the console will
resume execution of the command file.

If the VAX-11/780 CPU halts (or if the clock stops) and
no DONE signal has been received, the console prints
<@EXIT> and aborts execution of the remainder of the
command file.

A Control C ( "C)
which causes the
command file.

is entered on the
console to abort

console terminal,
execution of the

Response: <CR> <LF> <input prompt>
2.3.23
Indirect (@) Command
Syntax: @ <filename> <CR> or @ DXl: <filename> <CR>
This command causes the console to open the file specified by
<filename> and begin executing console commands from the file.
Execution continues until one of the following occurs:
a.

A WAIT DONE
2.3.22).

command

read

from

the

f i 1e

The end of the indirect file is reached. In this case the
console prints <@EOF> and prompts for normal command
input.

A "C is entered on the console
execution of the indirect file.

causing

(Paragraph

abort

2.3.24
WCS Command (W)
Syntax: WCS
This command invokes the control store debugger, overlaying the
console program. The console help file, WCSMON.HLP, contains a
summary of control store debugger commands. To print out this
file, type @ WCSMON.HLP.
Response: WCS> (Control store debugger prompt)
2.4
COMMANDS PERFORMED WITH THE VAX-11/780 CPU RUNNING
Most console commands require that the VAX-11/780 CPU be halted to
allow the command to be executed. However, some console commands
do not require interaction with the VAX-11/780 CPU, and may be
executed with the VAX-11/780 CPU running. These commands include:

a.
b.
c.
d.

Show
Help
Set commands
Examine /V Bus

Halt
Clear
Wait Done

g.
2-14

Specifying any other console command while the VAX-11/780 CPU is
running will cause the console adapter to reject the command and
type out the following error message on the console terminal:
<CR> <LF> ? CPU NOT IN CONSOLE WAIT LOOP, COMMAND ABORTED
<CR> <LF> <INPUT PROMPT>
2.5
COMMENTS WITHIN COMMANDS
The console allows comments, preceded by an exclamation mark (!),
to appear in any command line. When the console detects an
exclamation mark, any remaining text in the command line is
ignored.
A comment may begin in any character position within a
line, including the first.

command

Example (console output underlined)
>>> ! THIS IS A VALID COMMENT <CR>
>>> EXAMINE 1234 ! THIS IS ALSO A COMMENT <CR>
2.6
CONTROL CHARACTERS AND SPECIAL CHARACTERS
Table 2-7 contains a description of the control characters
special characters recognized by the console program.
Table 2-7

Control/Special Character Descriptions

Character

Description

CONTROL C ( "C)

Causes the suspension of all
console operations such as:

CONTROL 0 ("O)

and

repetitive

Repeated command executions as
a result of a repeat command

Successive operations as
result of a /NEXT qualifier

Delays resulting
command

Successive steps resulting from
a next command

Aborts further execution of an
indirect command file after
current
instruction
is
completed.

from

wait

Suppresses or enables (on a toggle basis)
console terminal output. Console terminal
output is always enabled at the next
console terminal input prompt.

2-15

Table 2-7

Control/Special Character Descriptions (Cont)

Character

Description

CONTROL U (AU)

AU typed before a line terminator causes
the deletion of all characters typed
since the last line terminator. The
console echoes:

Au <CR> <LF>
RUBOUT

Typing RUBOUT deletes the last character
typed on an input line. Only characters
typed since the last line terminator can
be rubbed out. Several characters can be
deleted in sequence by typing successive
rubouts. The first rubout echoes as a
backslash (\) fol lowed by the character
that has been deleted. Subsequent rubouts
cause only the deleted character to be
echoed. The next character typed that is
not a rubout causes another backslash
(\) to be printed, followed by the new
character to be echoed.

Carriage Return <CR>

Terminates a console command line.

2-16

2.7
COMMAND QUALIFIERS AND DEFAULTS
Qualifiers are used within a command to specify the type of
addressing and the length of data arguments. Defaults are applied
by the console when a command does not contain a qualifier
specifying address-type or data length. An operator can specify
the radix of a numeric argument by the use of a <local radix
override> prefixed to the argument. The console will interpret
numeric arguments in the current default radix when an argument is
not prefixed by a <local radix override>.
Certain commands permit an address argument to be defaulted. The
<default address> used by the console is the next address
following the last virtual, physical, or register address accessed
by an examine or deposit command. Note that the next address is
dependent upon data length, since a byte reference updates the
<default address> by 1, while a longword reference updates the
<default address> by 4.
The /NEXT qualifier allows an examine
operate on more than one address.

deposit

command

2.7.1
Address Type Qualifiers
Address type qualifiers are used within a command line to specify
the type of address argument as virtual, physical, ID Bus, V Bus
or register address. The qualifiers for the respective types are:
/VIRTUAL, /PHYSICAL, /ID BUS, /V BUS, /GENERAL, /INTERNAL.
Virtual addresses that reference nonexistent or nonresident pages
will cause the console to abort execution of the console command
that referenced the virtual address. In each case an appropriate
error message will be typed out on the console terminal.
Example
To examine virtual address 1234, type:
EXAMINE/VIRTUAL 1234 <CR>
Note that since some register addresses have mnemonic names that
are unique and unambiguous, the /GENERAL qualifier need not be
specified when mnemonic addresses such as PC, or SP, are
referenced.
Example
To examine the VAX-11/780 PC, an operator could type either
of the following statements:
EXAMINE/GENERAL PC <CR> or
E PC <CR> or
E GENERAL F <CR>

2-17

2.7.2
Address Type Defaults
The console applies an address type default to any command that
requires an address argument and does not contain an address
qualifier. The default applied can be set by using the set default
command.
Example
The command:
SET DEFAULT VIRTUAL <CR>
will cause the console to default to virtual addressing for
any console command that requires an address argument, but
does not contain an address type qualifier. Thus, the command
EXAMINE 1234 would type out the contents of virtual address
1234.
2.7.3
Data Length Qualifiers
Data length qualifiers are used within a command line to specify
the length of the data quantity associated with the command. Data
length may be specified as either byte, word, longword, or
quadword by means of the /BYTE, /WORD, /LONG, /QUAD qualifiers,
respectively.
Example
The command:
EXAMINE/BYTE 1234 <CR>
will type out the byte at address 1234.
Since VAX-11/780 CPU general and processor registers are longword
quantities, all register references will default to longword data
length, regardless of the current setting of the data length
default.
2.7.4
Data Length Defaults
The console applies a data length default to any command that
references data and does not contain a data length qualifier. The
default applied can be set using the set default command.
Example
The command:
SET DEFAULT WORD <CR>
will cause the console to default to word data length.

2-18

The command:
EXAMINE 1234 <CR>
will then reference
address 1234.

the

word

which

has

its

first

byte

Since all VAX-11/780 CPU general and processor registers are
longword quantities, all register references will default to
longword data length, regardless of the current setting of the
data length default. Word length must be specified when accessing
Unibus device registers.
2.7.5
Qualifiers for RADIX
The radix of console output for a command can be sepcified by a
qualifier
(/OCTAL or /HEX).
The qualifier will override the
current default radix.
2.7.6
Defaults for RADIX
The default radix for console numeric inputs and outputs is
selectable as either HEX or OCTAL via the SET DEFAULT HEX or SET
DEFAULT OCTAL command.
2.7.7
Local Radix Override
It is frequently convenient to specify an address or data argument
in a radix different from the current default radix. The console
allows the current default radix to be overridden by including a
<local radix override> as a prefix to any numeric argument. A
<local radix override> can be any one of the following:
% O (percent O) for octal arguments
% X (percent X)

for hexadecimal arguments

Th e 1 o ca 1 rad i x o v e r r i d e mus t a pp e a r a s th e two 1 e f t mo s t
characters of the numeric argument it modifies, and must not be
separated by spaces or tabs from that argument.
Example
As s um in g th a t the c u r r en t d e fa u 1 t rad i x i s o ct a 1 , the
operator can deposit the octal value 3456 into the
hexadecimal address 12A4 using <local radix override> as
follows:
DEPOSIT %Xl2A4 3456
2.7.8
Default Address Facility
Each time an examine or deposit command is executed, the console
computes the address of the next memory location following the
location referenced by the command. The address of the next memory
location is termed the <default address>, since an examine command

2-19

that does not specify an address will reference the next address
by default. The console computes the <default address> as follows:
<default address> = <address used by last examine or deposit
command> + n, where n is
1 for byte references
2 for word references
4 for longword references
8 for quadword references
The fol lowing example shows a sequence of console commands, and
the value taken by the default address after each command is
executed. Note that the next address is data length dependent,
since a byte reference updates the <default address> by 1, while a
longword reference updates the <default address> by 4.
Example of default address facility (all numbers are hex):
Command

<default address> after execution

EXAMINE/BYTE 2341
EXAMINE/WORD
(uses <default address> 2342)
EXAMINE/LONG
(uses <default address> 2344)
EXAMINE/GENERAL 0
EXAMINE/GENERAL D
EXAMINE PC

2342
2344
2348
general register 1 (Rl)
general register E (SP)
general register 0 (R0)

Note that the <default address> is R0 following a PC reference.
2.7.8.1 Specifying Default Address in a Command -- The symbol (+)
can be used as an address argument in a deposit or examine command
to represent the <default address>. This symbol permits depositing
to (or examining) successive location without typing the address
argument after the first deposit.
Example
To toggle-in a program starting at
following deposit commands can be used:
DEPOSIT
DEPOSIT
DEPOSIT

123456

+
+

address

123456,

the

Each deposit command, after the first, writes the <DATA> into
the next successive memory location.
2.7.8.2 Last Address Notation
The last address referenced
(virtual, physical, or register) by an examine or deposit command
is denoted by an asterisk (*). The LAST ADDRESS may be used as an
argument to an examine or deposit command by typing an asterisk in
place of the address argument.
2-20

Example
The command:
EXAMINE 1234 <CR>
will type out the contents of location 1234.
If the next command issued is
DEPOSIT

* 356 <CR>

the console will deposit the number 356 into location 1234.
Examine and deposit commands to VAX-11/780 CPU general and
processor registers will replace the <last address> with the
register address. Mnemonic register names are translated into
register addresses by the console.
2.7.8.3 Preceding Address Notation -- The symbol - (minus sig-n)
can be used as an address in a deposit or examine command to
specify the location immediately preceding the last location
referenced.
2.7.8.4 Use of Last Data as an Address Argument -- The symbol @
can be used as an <address> in a deposit or examine command. The
last <data> deposited or examined will be used as the address.
2.7.9
NEXT Qualifier
Syntax: SLASH NEXT [:<COUNT>]
The /NEXT qualifier permits examine and
operate on multiple sequential addresses.

deposit

commands

The <count> argument specifies the number of additional executions
of the command to be performed after the initial execution. The
default value for <count> is one.
Example 1
The command:
EXAMINE/BYTE 1230/NEXT:2
is evaluated by the console as follows:
1.

The console initially evaluates the command and applies
any applicable default values.

The command, with applied defaults, is executed.
console types out the contents of location 1230,
updates the <default address> to 1231.

2-21

The
and

3•

The /NEXT s w i t ch i s now e v a 1 u a t e d by the cons o 1 e • The
console repeats the command operation the number of times
indicated by the <count> argument. Each execution uses
the < de fa u 1 t add r e s s > f o r i ts add r e s s a r g um e n t and
updates the <default address> afterwards.
In this
example, locations 1231 and 1232 are successively typed
o u t • The f in a 1 v a 1 u e of the <de fa u 1 t add res s > w i 11 be
1233.

Example 2
If the command:
EXAMINE/NEXT:2 <CR>
is issued following the command in the previous example, the
contents of locations 1233, 1234, and 1235 will be typed out.
Since the examine command does not contain an address
argument, the initial execution of the command will use the
current <default address>, which was 1233, following the
command in the previous example.
Note that when using the /NEXT qualifier to examine or deposit
successive VAX-11/780 CPU general registers, the NEXT register
after the PC is defined to be R0.
Example 3
The command:
EXAMINE/NEXT:S GENERAL D
will type out the contents of Rl3, SP, PC, R0, Rl, and R2,
that order.

2.8
COMMAND REPEAT FACILITY
The command repeat facility is provided to allow commands to be
executed repeatedly so that CPU logic invoked by console commands
can easily be scoped. The following paragraphs describe the repeat
facility commands and capabilities.
2.8.1
Example

Repeating Commands

The command:
REPEAT EXAMINE 1234 <CR>
will continuously
location 1234.

examine

contents

Once initiated, repeated execution continues until terminated
the operator typing Control C (AC) on the console keyboard.

2-22

and

display

the

2.9
COMMAND LINK FACILITY
The console's command link facility allows successive commands to
be linked by the console into a single executable list of
commands. Once a list of linked commands is constructed, the list
can be executed one pass at a time, or executed continuously.
2.9.1
Link Facility Operation
Commands are linked by entering LINK on the console terminal,
causing the console to enter the link mode. LINK is then followed
by the desired commands. The LINK command is entered only at the
beginning of the command string (i.e., at the beginning of the
initial command line}. Commands to be linked must be entered
one-per-1 ine, with each command 1 ine terminated by a <CR>. The
console then returns a link mode prompt (<<<) requesting the next
command. The linking operation is terminated by entering a Control
C on the console.
As the command string is entered on the console, the commands are
stored in dedicated sectors (limit of 10 sectors} on the floppy
disk (RX01). When the command string is executed, the string is
treated as if it were an indirect command file (i.e., command
retrieved, parsed, executed, and the next command retrieved,
etc • ) •
The console does not execute commands being linked until a PERFORM
command is issued. Once the input of a list of linked commands has
been terminated, no further commands can be added to the commands
already linked.
The command string can be executed one pass at a time or
continuously by means of the PERFORM command. If the PERFORM
command is entered after the Control C to terminate the string,
the string will execute only one pass. However, if PERFORM is
entered before the Control C, that command becomes part of the
command list and causes continuous execution of the command list.
Should a linked command be entered incorrectly, the console will
output an appropriate error message when the command containing
the syntactic error is executed. Typing a Control U (AU) while
linking commands will cause the console to reject only the current
command 1 ine.
2.9.2
Syntax:

Link Facility Usage
LINK
COMMAND <CR>
COMMAND <CR>
(AC)

Response: Dependent on command list.
Example
The operator wishes to repeatedly examine the contents of a
device register after VAX-11/780 CPU initialization. Since
2-23

the CPU initialization requires a certain amount of time to
complete, a delay must be inserted between the initialize and
examine commands. The sequence of commands is as follows
(console output is underlined).
>>> LINK INITIALIZE <CR>

LINK causes the console to
enter the link mode and begin
linking.

<<< DELAY 5 <CR>

De 1 a y s five c 1 o ck
a 11 ow
in it i a 1 i z e
complete.

<<< EXAMINE/LONG FFFFABBC <CR>

Examine command is entered into
string.

<<< PERFORM <CR> <AC>

PERFORM is entered
linking termination.

>>> PERFORM <CR>

Initiates execution.

P FFFFABBC
P FFFFABBC

12A00123
12A00123, etc.

Command
string
continuously.

ticks
ti me

prior

to
to

executed

2.11
CONSOLE MODE CHANGE
The console I/O mode escape sequence causes the console to switch
from console to progra~ I/O mode. The escape sequence to program
I/O is:
SET TERMINAL PROGRAM <CR>
In addition, the console commands START, CONTINUE, and NEXT also
enable program I/O mode.
The program I/O mode escape sequence causes the console to switch
from program to console I/O mode. The escape sequence to console
I/O is:

Note that Control P is not recognized by the console if the
console power switch is in either the REMOTE DISABLE position or
the LOCAL DISABLE position.
2.11
VMS COMMUNICATION WITH CONSOLE FLOPPY DISK
VMS must be able to read and write the console subsystem's floppy
disk drive. These functions are available only when the console is
in program I/O mode. The following set of commands are supported
by the console software.
a.

Write sector -- VMS supplies track, sector, and 128 bytes
of data. Console returns status upon completion of write.

2-24

Read sector -- VMS supplies track and sector. Console
returns 128 bytes of data, and status of read operation.

Read floppy status -- Console returns floppy status.

Write sector with deleted data mark -- VMS supplies track
and sector (no data required). Console returns status
upon completion of the write.

Cancel floppy function -- Console aborts
function.

current floppy

The following floppy functions will not be directly available to
VMS: empty silo, fill silo, read error register, initialize.
While VMS initiated floppy functions are in progress, operator
terminal I/O is not disabled. Terminal I/O may be interspersed
with floppy I/O.
Once a floppy function is initiated, no other floppy commands will
be issued by VMS until the function is complete. The only
exception is the command cancel floppy function, which may be
issued at any time.
The floppy functions described in this document will only be
available to VMS when the console is in program I/O mode (i.e.,
the console terminal is being used as the system operator's
terminal).
NOTE
In the following protocols, two hardware
side-effects are implied:

Each time VMS loads the transmit
buffer (TXDB) , the TX ready bit in
the transmit status register (TXCS)
is automatically cleared. TXDB is
only loaded by VMS, and only when TX
ready is set. TX ready is explicitly
set by the console when the console
is ready to accept another transfer
through TXDB.

Each time VMS reads the receiver
buffer (RXDB) , the RX done bit in
the receiver status register (RXCS)
will automatically clear. RXDB is
only read by VMS, and only when RX
done is set. RX done is explicitly
set by the console each time the
console has loaded RXDB with a
character for VMS.

2-25

2.11.1
A.

Floppy Function Protocol
Write sector/write deleted data sector
1.
VMS puts the write sector or the write deleted data
sector command into TXDB.

The console takes
ready in TXCS.

VMS puts a sector number into TXDB.

The console
ready.

VMS puts a track number into TXDB.

The console takes the track number and sets TX ready.

VMS puts a byte of data into TXDB.

The console accepts a byte of data and sets TX ready.
Steps 7 and 8 are done 128 times for write sector.
Steps 7 and 8 are skipped for write deleted data
sector.

The console initiates a floppy write function.

10.

The floppy write is completed.

11.

The console sends a floppy function complete message.
The floppy function complete message consists of
loading RXDB bits 8--11 with a select code of 2, and
bits 0--7 with the floppy status byte.

12.

VMS receives the floppy function completed message.

takes

the

write

sector

command,

number

and

sets

and

sets

Read sector
1.
VMS puts the read sector command into TXDB.
2.

The console takes the read command, and sets TX ready
in TXCS.

VMS puts a sector number into TXDB.

The console
ready.

VMS puts a track number into TXDB.

The console takes the track number and sets TX ready.

The console initiates a floppy read function.

The floppy read is completed.

takes

the

2-26

sector

number

and

sets

The console
The floppy
select code
status byte

sends a floppy function complete message.
fun ct ion complete message consists of a
of 2 in bits 8--11 of RXDB, and a floppy
in bits 0--7 of RXDB.

10.

VMS receives the floppy function completed message.

11.

The console puts one byte of data in RXDB and sets RX
done.

12.

VMS accepts one byte of data from RXDB. Steps 11 and
12 are done 128 times. When the !28th byte is
accepted by VMS, the read is complete.

NOTE
If a floppy error occurs on Step
Steps 11 and 12 will be skipped.
C.

2.12

Read status
1.
VMS puts the read floppy status command in TXDB.
2.

The console takes the read status command and sets TX
ready in TXCS.

The console gets the floppy status from last floppy
function performed.

The console puts a floppy function complete message;
with the floppy status, into RXDB and sets RX done.

VMS reads the floppy status.

Terminate floppy function
1.
VMS puts the cancel floppy function command in TXDB.
2.

The console takes the cancel floppy function.

The console terminates
progress, if any.

The console sets TX ready in TXCS.

the

floppy

function

MISCELLANEOUS CONSOLE COMMUNICATIONS

The console software will support certain additional functional
communications from VMS and the diagnostic supervisor (VMS/DS).
A.

Examine console memory -- VMS supplies an offset from the
console-supplied base address of examinable memory space.
The console returns the examine code and the contents of
the requested byte.
Examinable Console Memory Space

2-27

(Octal Offset from 37600(8) -- FIRSTF)
Warm-start flag
Cold-start flag
APT-load flag
Last setting of remote and disable
Auto-restart flag
PCS version
WCS primary version
FPLA version

+145
+146
+147
+150
+151
+152
+153
+155
B.

Software communication codes
1.
Software done -- VMS issues this code to cause the
console to resume execution of an indirect-command
file that has been suspended due to a wait done
command.
2.

Warm restart boot command -- The console will
the VAX-11/78 0.

boot

Clear warm-start and cold-start flags -- VMS/DS
issues
these
codes
when
the
VAX
has
restarted/rebooted successfully. The console clears
the associated flags.
NOTE
The cold and warm restart flags are used
by the console to prevent infinite loops
when a warm restart results in a
VAX-11/780 error halt.

2.13

COMMUNICATION REGISTER FORMATS AND SELECT CODES

The LSI-11 processor communicates with the VAX-11/780 CPU via two
registers on the console interface board. Figure 2-1 shows the
register formats and select codes.

TXDB
31

2423-

MBZ

16 15 14 131211

MBZ

DATA
FIELD

161514131211
08 07
USED BY SELECT
DL-11
FIELD

DATA
FIELD

MBZ

0807

SELECT
FIELD

RXDB
31

2423

MBZ

TK-0742

Figure 2-1

Communication Register Formats and Select Codes
2-28

Select Field Values (in hex)
Select Code

Device

Data Field Values

Operator's terminal

0 through 7F ! ASCII data

Floppy drive 0 (data)

Floppy function complete

(floppy status)

Examine console memory

Address
address

Floppy drive 0 (command)

0 = read sector
1 = write sector
2 = read status
3 = write deleted data
sector
4 = cancel floppy function
5 = protocol error

Misc. communication

1 = software done
2 = boot VAX-11/780
3 = clear warm-start flag
4 = clear cold-start flag

NOTE
Code 5 (protocol error)
console when one of
occurs:

through FF

offset/contents

is sent by the
the following

Another floppy command (except for
cancel floppy function) is issued
by VMS before a previous command is
completed.

The console gets a floppy drive e
code
(DATA)
when
expecting
a
command.

2-29

binary data

2.r4
FLOPPY STATUS BYTE DEFINITION
The floppy status byte is used by VMS to determine the success or
failure of a read or write operation. The floppy status byte is
sent to VMS at the completion of a read, write, or read status
operation. The select code is always the floppy function complete
(code 2). The status bit assignments are shown in Figure 2-2.

RXDB
MBZ

12 11

1615

MBZ

08 07 06 05

CODE '2'

03 020100

MBZ
CRC ERR
- - - PARITY ERROR

- - - INIT DONE
- - - - - - - D E L E T E D DATA
--------ERROR
TK-0745

Figure 2-2

Floppy Status Bit Assignments

NOTE
The status bit assignments are identical
to
those
supplied
by
the
floppy
controller, except for bit 7. Bit 7
corresponds to bit 15 of the floppy's
RXCS register.
2.15
REMOTE CONSOLE ACCESS COMMAND SET
A spec i a 1 set of co mm ands i s inc 1 ud e d in the cons o 1 e co mm and
language of systems that use the remote diagnostic facility to
faci 1 i tate console access from a remote terminal or computer.
Commands can be initiated only on the terminal in control,
according to the five-position key switch. The remote access
command set provides for:
a.

A talk mode, to allow communication between
remote terminal operators (enable talk).

A copy control, to permit suppressing or enabling typeout
on the local terminal while a remote operator is in
control (enable/disable local copy).

A method of transferring control of the console between
the local and remote operators (enable local control).

2-30

local

and

A method of controlling the echo of characters to the
remote terminal while in talk mode (enable/disable echo).

A method of suppressing lost carrier error messages
caused by a loss of carrier on the remote line
(enable/disable carrier error).

A method of enabling and disabling use of the console
subsystem floppy disk (enable/disable local floppy) •

A method of enabling and disabling use of
floppy disk (enable/disable remote floppy).

the

remote

2.15.1
Enable Talk Mode Command
Syntax: ENABLE <blank> TALK <CR>
The enable talk command puts the console into talk mode. While in
talk mode, characters typed on the remote keyboard are typed on
the local terminal, and vice versa. The console does not echo
characters back to the originating keyboard, unless the talk mode
echo feature has been enabled. No console commands are recognized
while in talk mode.
Talk mode is terminated by typing the console escape character
( ""P) on the terminal in control. When talk mode is terminated,
console mode is enabled.
Entering talk mode causes the console to enable the remote serial
interface and assert the data terminal ready signal to the data
set. All terminal I/O to a program running in the VAX-11/780 CPU
is disabled while the console is in the talk mode.

2-31

2.15.2
Syntax:

Enable/Disable Echo Command
(ENABLE ! DISABLE) <blank> ECHO <CR>

The enable echo command will cause the console to echo characters
typed on either the remote or local keyboards while in talk mode.
The di sable echo command causes the console to suppress echo of
characters typed on both keyboards.
Enable and disable echo are issued while the console is in console
mode, but do not have any effect unti 1 talk mode is entered. A
disable echo is automatically done each time the console keyswitch
is put in the LOCAL/DISABLE position, and on power up of the
console.
2.15.3
Syntax:

Enable/Disable Local Copy Command
(ENABLE ! DISABLE) <blank. LOCAL <blank> COPY

The enable local copy command causes the local terminal to print a
copy of al 1 output directed to the remote terminal. The di sable
local copy command disables the local terminal from getting a copy
of output directed to the remote terminal.
Local copy is automatically disabled each time the console
keyswitch is turned to the LOCAL or LOCAL/DISABLE position and on
power up of the console. Local copy is automatically enabled each
time the console keyswitch is placed in the REMOTE/DISABLE
position.
2.15.4
Enable Local Control Command
Syntax: ENABLE <blank> LOCAL <blank> CONTROL <CR>
An enable local control command, issued by the remote terminal
operator while the console keyswitch is in the REMOTE position,
transfers control of the console to the local terminal operator.
(Normal remote operation locks out the local terminal.) This
allows a local operator to take control of the console and the
VAX-11/780 CPU, while the remote link is maintained. The remote
operator may regain control of the console by typing a Control P
on the remote keyboard.
An enable local control command issued from the local terminal has
no effect. Local control is automatically enabled when the console
keyswitch is placed in the LOCAL or LOCAL/DISABLE position, and
also on console power up.
2.15.5
Syntax:

Enable/Disable Carrier Error Command
(ENABLE ! DISABLE) <blank> CARRIER <blank> ERROR <CR>

The enable carrier error command causes the console to print the
message ?CARRIER LOST each time a loss of carrier on the remote
line is detected. Also, if the console keyswitch is in the LOCAL
or REMOTE position, the console enters talk mode, enabling data
terminal ready on the modem.

2-32

The disable carrier error command causes the console to inhibit
the carrier lost message, and prevents a transition to talk mode.
An enable carrier error is automatically done on console power up,
and whenever the console keyswi tch is placed in the LOCAL or
LOCAL/DISABLE position.
2.15.6
Syntax:

ENABLE/DISABLE LOCAL Floppy Command
(ENable!Disable)<BLANK>Local<BLANK>FLoppy

Enable local floppy will cause the directory of the local floppy
to be searched first, in an attempt to open a file. If the file is
not found, the remote floppy directory is searched. Note that in
terms of the console software, the remote floppy is a virtual
device. It may be a floppy or it may be some other storage device.
Disable local floppy will cause only the directory of the
floppy to be searched in an attempt to open a file.

remote

An enable/disable local floppy command affects protocol operation
only (transmission format).
2.16
CONSOLE ERROR MESSAGES
This paragraph describes all console error message formats and
their interpretation. All console error messages are prefixed by a
question mark to distinguish them from informational messages.
2.16.1
Syntactic Error Messages
?<TEXT STRING> IS INCOMPLETE
The <TEXT STRING> is not a complete console command.
?<TEXT STRING> IS INCORRECT
The <TEXT STRING> is not recognized as part of a console command.
?FILE NAME ERR
A <FILENAME> given with a LOAD or @ command cannot be translated
to RAD 5 0 • One of the characters is not transl a tab 1 e to RAD 5 0 or
the number of characters allowed is exceeded: six characters for
file name, three for extension.
2.16.2
Command Generated Error Messages
?FILE NOT FOUND
A <FILENAME> given with a LOAD or @ command does not match any
file on the current floppy disk. This error can also be generated
by a HELP or BOOT command if the help file or boot file is missing
from the floppy.
?NO CPU RESPONSE
The console timed out while
VAX-11/780 CPU microroutine.

waiting

for

response

from

?CPU NOT IN CONSOLE WAIT LOOP, COMMAND ABORTED
A console command that required the assistance of the VAX-11/780
CPU was issued when the CPU was not in the console service loop.

2-33

?CPU CLOCK STOPPED, COMMAND ABORTED
A console command that requires the CPU clock to
issued with the clock stopped.

?IND-COM ERR
An indirect command
generated if:

This

a.
b.

file

was

error

detected.

running

error

was

An indirect command line exceeds 80 characters.
An indirect command line does not end with <CR> <LF>.

2.16.3
Microroutine Error Messages
The console uses various microcode routines in the VAX-11/780 CPU
control store to perform console functions. The following errors
are generated by microroutine failures.
?MEM-MAN FAULT, CODE = XX
A virtual examine or deposit caused an error in the memory
management microroutine. XX is a one-byte error code supplied by
the memory management routine and defined in Table 2-8.
Bit positions
right.
Table 2-8

NOTE
are numbered

from

the

Memory Management Error Code Definitions

Bit Position

Definition
Length violation

Fault was on a PTE reference

Write or modify intent

Access violation

4--7

Ignored

?MICROMACHINE TIME OUT
This message indicates that the VAX-11/780 micromachine has failed
to strobe interrupts within the maximum time period allowed.
?MIC-ERR ON FUNCTION
An unspecified error occurred in the CPU while serv1c1ng a console
request. Referencing nonexistent memory will cause this error.
?INT-REG ERR
An error occurred while referencing one of the VAX-11/780 CPU
internal (processor) registers. Specifying a register address that
is too large will cause this error.

2-34

?MICROERR, CODE = XX
An unrecognized microerror occurred. The code returned by the CPU
is not in the range of recognized error codes. XX is the one-byte
error code returned by the microroutine.
2.16.4
CPU Fault Generated Error Messages
?INT-STACK INVLD
The VAX-11/780 CPU interrupt stack was marked invalid.
?CPU DBLE-ERR BLT
The VAX-11/780 CPU has done a double error halt.
?ILL I/E VEC
An illegal interrupt/exception
VAX-11/780 CPU.

vector

was

encountered

?NO USR WCS
An interrupt/exception vector to WCS was encountered,
exists.

the

and no WCS

?CHM ERR
A change-mode instruction was attempted from the interrupt stack.
2.16.5
RX01 Error Messages
?FLOPPY ERR, CODE = X
(a part of the console software)
The console floppy driver
detected an error. X is an error code (in hexadecimal) and is
defined in Table 2-9.
Table 2-9
Code

RX01 Error Message Code Definitions
Definition
Floppy
parity,
error) •

hardware
error
(i.e.,
CRC,
or a floppy firmware detected

An open file command failed to find the
specified file.

The floppy driver queue is full.

A floppy sector was
out of the legal
numbers.

referenced that is
range of sector

?FLOPPY NOT READY
The console floppy drive failed to become ready when booting.
?NO BOOT ON FLOPPY
The console attempted to boot from a floppy that does not contain
a valid boot block.
?FLOPPY ERROR ON BOOT
A floppy error was detected while attempting a console boot.
2-35

2.16.6
Miscellaneous Error Messages
INT PENDING
This is not actually an error (note absence of ?) • The message
indicates that an error was pending at the time that a console
requested halt was performed. Type CONTINUE to clear interrupt.
?WARNING-WCS and FPLA VER MISMATCH
The microcode in the WCS is not compatible with the FPLA. This
message is printed on each ISP START or CONTINUE. However, no
other action is taken by the console.
?FATAL-WCS and PCS VER MISMATCH
The microcode in the PCS is not compatible with that in the WCS.
ISP START and CONTINUE are disabled by the console.
?REMOTE ACCESS NOT SUPPORTED
This message is printed when the console mode switch enters a
REMOTE position, and the remote support software is not included
in the console.
?TRAP -4, RESTARTING CONSOLE
The console took a time-out trap. Console will restart.
?UNEXPECTED TRAP
Console trapped to an unused vector. Console reboots when operator
types Control C.
?QB LOCKED
Indicates that the console's output queue is blocked. Console will
reboot.

2-36

CHAPTER 3
DIAGNOSTIC SUPERVISOR AND CONTROL
This chapter describes the basic structure and operating
characteristics of the diagnostic supervisor. In addition,
operator commands and execution control functions are described.
This description is applicable to macro testing, and while many
similarities exist for the micros, this chapter does not include
them (refer to Chapter 4).
3.1
SUPERVISOR STRUCTURE OVERVIEW
The diagnostic supervisor provides operator control and utility
support functions for three diagnostic runtime environments. The
three runtime environments are:
a.

Cluster Environment (CE): This environment supports the
CPU cluster and repair level I/O bus adapter diagnostic
programs. The CE consists of program modules that provide
u t i 1 it y s er vi c es ( i • e • , err o r report in g , scope 1 oops ,
etc.), initialization and test dispatch, and operator
term i na 1 interface • Add i t ion a 1 mod u 1 es provide 1 o ad and
script management.

System Environment (SE): This environment supports the
repair level I/O subsystem diagnostic programs, and the
device functional test programs. The SE provides the same
runtime support functions as the CE. Program modules
provide CPU cluster hardware interface support (i.e.,
real-time clock control, interrupt system control, I/O
bus adapter control, etc.).

User Environment (UE): This environment supports the I/O
subsystem functional level diagnostic programs that run
under the VMS operating system as a privileged user task.

I/O services are provided primarily for functional level programs.
This allows programs that can execute in an operating system
environment, which restricts I/O access, to perform equally well
in a standalone environment.
The three supervisor environments are assembled into a common
executable module that provides all necessary operator and program
services. As shown in Figure 3-1, these services are implemented
in two major functional areas: Command Line Interpreter (CL!) and
Program Interface (PGI).

3-1

OPERATOR
TERMINAL

-- --

COMMAND LINE
INTERPRETER

PROGRAM
INTERFACE

TEST
PROGRAM

J
UNIT
UNDER
TEST

TK-0741

Figure 3-1

Basic Diagnostic Supervisor Structure

The CL! interfaces to an operator (controlling) terminal and
enables the operator to control the loading, sequencing, and
execution of diagnostic test programs. The CL! monitors all
control
information passing between the terminal and the
supervisor. This information consists of supervisor commands from
the operator which control either supervisor or test program
operation. The CL! directs control to the appropriate supervisor
service module according to the command supplied by the operator.
The PG! provides common services required by all diagnostic test
programs. These services include operator interaction, program
control, error message formatting, memory management, and I/O
request handling. Note that the operator can communicate with the
diagnostic program only through a PG! message service or with the
CL! directly.
When the operator initiates diagnostic program execution (through
the CLI), that program assumes control. Once program execution
beg ins, the · PGI handles all test information flowing between the
terminal or the Unit Under Test (UUT)
(i.e., QI/0-I/O driver
interface)
and a functional level program. For repair level
programs, test information flows directly between the UUT and the
diagnostic program (i.e., direct test program access to I/O
registers) •
Test control information flow between the terminal and the
diagnostic program consists mainly of test parameter requests and
responses, while test information flow between the UUT and the
program consists mainly of test stimuli and responses.
The diagnostic program executes until the test sequence is
completed, aborted, or the operator enters the appropriate control
character, at which point control returns to the CL!.
System errors not directly related to the UUT are handled by the
supervisor. Unless the program explicitly requests notification,
these errors are transparent to the program and are reported
directly to the operator.

3-2

3.2
CLI FUNCTIONAL MODULE DESCRIPTION
The CL! consists of a tree-structured command decoder and several
service modules that execute the operator's commands (e.g.,
loading a diagnostic program from the system device; altering the
operational characteristics of the program; or driving the CLI
through a script file). The command syntax is a subset of the
console command language.
Once a command line is interpreted, the CLI dispatches control to
the appropriate service module. After the operator's command has
been completed or aborted, control is returned to the CLI. Certain
CLI service modules pass control to the diagnostic program, rather
than back to the CL!. However, the CLI continues to monitor the
operator's terminal for certain commands (e.g., AC).

3.2.1
Image Loader Module
The image loader allows the operator to specify a load device and
a file name for loading diagnostic programs. Depending on the
environment (i.e., console, system, or user), the device media
will be either the diagnostic load device (console floppy) or the
system load device.
3.2.2
Test Sequence Control Module
The test sequence control module provides the operator with the
capability to control the order in which tests within a program
are executed. This is implemented by specifying test numbers in
the run, start, and restart supervisor commands (Paragraph 3.4).
3.2.3
Script Processor Module
Automatic ~est sequence control is achieved through the use of a
script file. This script file is a line-oriented ASCII file that
contains standard CLI supervisor commands. To allow for commenting
on a command line, any text following a (!) on a line is ignored
by the script processor. Blank lines and extraneous spacing
characters are also ignored.
A script file may contain CLI supervisor commands (Paragraph 3.5)
only, or a combination of commands and program parameter
responses. Generating script or parameter files is performed
off-line using a standard editor system utility.

3.3
PGI FUNCTIONAL MODULE DESCRIPTION
The major function of the PG! module is to handle all information
flowing between the operator's terminal or the UUT and the
functional level I/O program. While a diagnostic program is
executing, that program can call on the supervisor to supply
various services. These services provide the program with the
required common functions (e.g., memory allocation and mapping,
I/O processing, operator terminal interfacing, error message
formatting, and system error handling).
Several of the functions the PG! provides are a subset of the VMS
system services. For example, the supervisor provides the VMS
queue I/O service so that user mode diagnostics may be executed
standalone as well as under VMS.
3-3

3.3.1
Memory Management and Adapter Services
All memory buffer allocation is performed by the diagnostic
supervisor. This ensures system integrity throughout the various
operating environments.
All necessary interfacing between the CPU and UUT will be handled
by the diagnostic supervisor.
Running standalone, the supervisor provides I/O services similar
to those available under VMS. This provides a smaller standalone
environment for running user mode diagnostics. Only a small kernel
subset of VMS system services is provided.
All functional level diagnostics perform device I/O as specified
by the VMS operating system. However, in addition to the normal
queue I/O functions, VMS provides special features that diagnostic
programs can use if executing as privileged processes. On I/O
completion, if requested and privilege permitting, raw status is
de po s i t ed into a buffer spec i fie d by the program • Thi s status
contains all device registers and pertinent channel registers. A
time stamp is also deposited into the status buffer.

3.3.2
Operator Terminal Services
Since the diagnostic programs do not interface directly with the
operator's terminal, the supervisor provides all required operator
communication services for the diagnostic program. The program c~n
perform operator dialogue through a supervisor service to allow
testing of mechanical dev1ces that require operator interaction.
The terminal drivers within the service eliminate the need for the
diagnostic programmer to be aware of the type of terminal
currently used by the operator.
The output to the operator, including error reporting, uses
formatted ASCII output to simplify the program's message-sending
routines. Conversion of binary data to ASCII display is handled by
the diagnostic supervisor instead of the programmer. The formatted
ASCII output syntax is the same as that used by VMS.

3.3.3
System Error Handling
All system errors are intercepted and reported directly to the
operator by the supervisor unless the program explicitly requests
notification of exceptions or interrupts.
3.4
SUPERVISOR COMMAND DESCRIPTIONS
The following paragraphs describe the operator command and
execution control functions provided by the diagnostic supervisor.
Where appropriate, examples of command usage are included.
3.4.1
Command Terms and Symbols
Since the supervisor commands are a subset of the console
commands, many of the console command terms and symbols are used
in the symbolic supervisor command descriptions. The applicable
characters are defined in Table 3-1.
3-4

Table 3-1
Term/Symbol

Term and Symbol Definitions

Definition
Used to indicate the Exclusive OR operation
(i.e., selection of parameters within a
command line)

(

)

Used to indicate that one of the syntactic
units of the expression is to be selected

< >

Used to
program
terminal

[ ]

Used to indicate that part of an expression
is optional; e.g., WAIT [<blank> <count>
]
indicates that the wait command takes an
optional <count> argument

<blank>

Represents one or more spaces

<tab>

Represents one or more tabs

<count>

Represents a numeric count

Indicates one or more occurrences
category indicated by XYZ

Represents an address argument

<data>

Represents a numeric argument

Represents a command modifier (switch)

Represents the console's input prompt string

>>>

Console program input prompt character

DS>

Diagnostic supervisor prompt

<CR>

Represents a console terminal carriage return

<LF>

Represents a console terminal line feed

Delimits a command from its qualifiers

indicate symbolic
functions
to/from

a r g um en ts , o r
the
operator

from

Used as a separator within a list
Used as a separator within a command line.

3-5

the

3.4.2
Command Description Segments
Each supervisor command description is divided into three, four,
or five descriptive segments, depending on the particular command.
The descriptive segments ·are:
a.

Syntax: describes the command structure.

Command description: a brief paragraph describing command
operation, general restrictions, or available options.

Response: a description of the console program response
to the specified command.

Qualifiers: a list of applicable command modifiers.

Options: a list of applicable command options.

The descriptive segments use the terms and symbols defined
Table 3-1. Note that every command (or command line) must
terminated with a <CR>.

in
be

3.4.3
Command Abbreviations
Supervisor command words, switches, and arguments may be
abbreviated by typing only enough characters to uniquely identify
each i tern. For example , the load command can be specified by L,
while the start command requires a minimum entry of ST.
3.4.4
Command Overview
The supervisor operator commands
following groups:

are

divided

into

the

three

Load/test sequence control:
the capability of loading
programs.

Execution control: provides the operator with control of
the operational characteristics of the diagnostic program
and/or supervisor {e.g., looping, error reporting, etc.).

Debug/utility functions: provide the operator with debug
and utility functions such as: breakpoints, examine,
deposit, etc.

prov ides the operator with
and sequencing diagnostic

The supervisors also support operator terminal characteristics
such as width, fill, etc. In addition, all control functions
provided by the console (e.g., Control C) are also supported by
the supervisor.
3.5
SEQUENCE CONTROL COMMANDS
The program/test sequence control commands provide the operator
with the capability of loading and controlling the sequencing of
diagnostic programs, as well as the capability of controlling the

3-6

sequence of test execution within a program. The supervisor also
provides for the execution of a single subtest, and if the pass
count option is used, provides a loop-on-subtest capability.
The submit command allows an entire diagnostic test session to be
predefined by the operator. The supervisor is then capable of
performing the test session without operator assistance.
Note that the symbolic argument <file
following subsection is defined as:

spec>

used

the

dev unit : [UIC] filename • ext
3.5.1
Load Command
Syntax: LOAD <file spec> [/PHYSICAL : <address>]

<CR>

The load command causes the specified file to be loaded into
memory. The supervisor obtains sufficient information from the
program.
After a successful load, the supervisor prints out the
message: Progname-r.p LOADED.

following

Progname is the program name. This is the internal name which
the supervisor extracts from the program header section.
--r.p is the release version
number of the program.

number

and

the

DEPO

(patch)

The optional PHYSICAL switch directs the image loader to attempt
to load the program into physically contiguous memory starting at
< add r e s s > • The < add r es s > a r g um en t
i s no rm a 11 y accepted i n
hexadecimal format by default.
3.5.2
Start Command
Syntax: START [/SEC
<section name>]
[/TEST
<first>]
[:<last> !/SUBTEST : <number>] ] -- [/PASS : <count>] <CR>
The start command causes the program in memory to begin execution.
As execution begins, the supervisor enters into a dialogue with
the operator to determine the program specific parameters. (e.g.,
whi ch un its to t es t) • The co mm and switches and c e rt a in a r g um en ts
are optional.
The SECTION switch is program specific and not available for use
with all programs. When a section is selected, only the tests that
it contains will be executed.
The TEST switch is used in two distinctly different ways.
a.

If the <first> and <last> arguments are specified, the
supervisor sequentially passes control to tests <first>
through <last> inclusively.

3-7

If the <first> argument is combined with the SUBTEST
switch, program execution begins at the beginning of the
<first> test and terminates at the end of SUBTEST
<number>.

If the SUBTEST switch is used in conjunction with the PASS switch,
the operator is provided with a loop-on-subtest capability. If the
optional PASS switch is not specified, a default <count> of one is
assumed.
If the TEST switch is not specified, all tests within the program
are executed. If only the <first> argument is specified with the
TEST switch, the <last> argument is assumed by default to be the
highest numbered test within the program.
3.5.3
Restart Command
Syn tax: RESTART [/SEC: <section name>]
[:<last> ! /SUBTEST : <number>]] -- [/PASS

[/TEST
<first>
<count> ] <CR>

The restart command is similar to the start command; however, the
supervisor does not enter into the parameter retrieval dialogue.
This command requires that the program P-Tables have been
previously setup with a start command. Switch syntax is identical
to the start command switches.
3.5.4
Run Command
Syntax: RUN<file spec> [/SEC: <section-name>]! -- [/TEST
[ : <last>! -- /SUBTEST : <number> ]] [/PASS : <count>]
The run command is
sequence. (Refer to
optional switches.)

<first>

equivalent to a load and start command
Paragraph 3.5.2 for a description of the

3.5.5
Control Characters and Special Characters
Table 3-2 contains a description of the control
characters recognized by the supervisor.

3-8

and

special

Table 3-2

Control/Special Character Descriptions

Character

Description

Control c (AC)

Returns program control to the supervisor
wh i ch en t e rs a co mm and wa i t state • The
operator may then issue any valid supervisor
command.

o (AO)

Suppresses or enables (on a toggle basis)
console terminal output. Console terminal
output is always enabled at the next console
terminal supervisor input prompt. However,
the
supervisor
will
override
Ao and
reinstate an active output status to the
operator terminal when it is servicing
system errors, CL! prompts, or forced
messages.

Control U (AU)

Au typed before a line terminator causes the
deletion of all characters entered since the
last line termination. The console echoes:
AU/<CR><LF>

Rubout

Typing rubout deletes the last character
typed on the input line. Only characters
entered since the last line terminator can
be rubbed out. Several characters can be
deleted in sequence by typing successive
rubouts. The first rubout echoes as a
backs lash (\) fol lowed by the character
which has been deleted. Subsequent rubouts
cause only the deleted character to be
echoed. The next character typed that is not
a rubout causes another (\) to be printed,
followed by the new character to be echoed.

Carriage Return (CR)

Terminates a command line.

Control

3.5.6
Continue Command
Syntax: CONTINUE <CR>
The continue command causes program execution to resume at the
point at which the program was suspended. This command is used to
proceed from a breakpoint, error halt, or Control C situation.
3.5.7
Summary Command
Syntax: SUMMARY <CR>
The summary command causes the execution of the program's summary
report code section which prints statistical reports.

3-9

3.5.8
Abort Command
Syntax: ABORT <CR>
The abort command executes the program's cleanup code and returns
control to the supervisor, which enters a command wait state. At
this. point the operator may issue any command except restart or
continue.
3.5.9
Submit Command
Syntax: SUBMIT <file spec>
<CR>

[/LOG

OFF]

[/CONSOLE

ON! OFF]

The submit command causes the supervisor to read a script file
f r om any f i 1 e -o r i en t e d de v i c e • The super vi so r per f o rm s the
functions outlined in the script file and then returns control to
the operator at the console.
The script file may contain any valid operator commands, including
a submit command. However, a submit command within a script file
is considered a terminal command (i.e., the supervisor will close
the current script and log files and open new ones as specified by
the current command) •
If the LOG switch is specified as ON, a transcript of the indirect
terminal dialogue is maintained in a file of the same filename as
the script file with an extension of .LOG on the device where the
script file is located. The default for this switch is OFF.
If the CONSOLE switch is specified as ON, the terminal dialogue
generated by the script file is printed on the operator's
terminal. The default for this switch is ON.
3.6
EXECUTION CONTROL COMMANDS
This group of commands allows the operator to statically or
dynamically alter the operational characteristics of the
diagnostic program and/or the supervisor. These functions are
implemented by flags that reside in both the supervisor and the
program. The event flags are located within the diagnostic program
and are supported by VMS and the supervisor.
These commands are used to control the printing of error messages,
ringing the bell, halting and looping of the program, etc. Flags
are provided that indicate to the supervisor which type of
dialogue characteristics are desired by the operator. The operator
also has access to a subset of the event flags that are available
to the program.
3.6.1
Set Control Flag Command
Syntax: SET [FLAGS] <argument list> <CR>
This command sets the execution control flags specified by
<argument list>; no other flags are affected. <argument list> is a
string of flag mnemonics separated by commas. The applicable flags
are described in Table 3-3.
3-10

Table 3-3

Control Flag Descriptions

Flag

Description

HALT

Halt on error detection. When the program
detects a failure, with this flag set, the
supervisor enters a command wait state after
all error messages associated with the
fai 1 ure have been output. The operator may
then
continue,
restart,
or abort the
program. This flag takes precedence over the
LOOP flag.

LOOP

Loop on error. When set, this flag causes
the program to enter a predetermined scope
loop on a test or subtest that detects a
failure.
Looping will continue until the operator
returns to the super vi so r by us in g ""C • The
operator may then continue, clear the flag
and continue, restart, or abort the program.

BELL

Bell on error. When set, this flag will
cause the supervisor to output a bell to the
operator whenever the program detects a
failure.

!El

Inhibit error messages at level 1. When set,
this flag suppresses all error messages
except those that are forced by the program
or supervisor.

IE2

Inhibit error messages at level 2. When set,
this flag suppresses basic and extended
information concerning the failure. Only the
header information message (the first three
lines) is output for each failure.

IE3

Inhibit error messages at level 3. When set,
this flag suppresses extended information
concerning the failure. The header and basic
information messages are output for each
failure.

IES

Inhibit summary report. When set, this flag
suppresses statistical report messages.

QUICK

Quick verify. When set, this flag indicates
to the program that the operator desires a
quick verify mode of operation.

3-11

Table 3-3

Control Flag Descriptions (Cont)

Flag

Description

SPOOL

List error messages on line printer. When
set, this flag causes the supervisor to
direct all program messages to the line
pr i nt e r •
In th e
VMS en v i r on men t ,
the
messages are not actually printed but
entered into a file on disk
(not yet
implemented).

TRACE

Report the execution of each test. When set,
this flag causes the supervisor to report
the execution of each individual test within
the program as the supervisor dispatches to
that test.

LOCK

Lock in physical memory. When set, this flag
disables the program relocation function.
Self-relocating programs are then locked
into their current physical memory space.

OPERATOR

Operator present. When set, this flag
indicates to the supervisor that operator
interaction is possible. When cleared, the
supervisor takes appropriate actions to
ensure that the test session bypasses any
tests that require manual intervention.

PROMPT

Display long dialogue. When set, this flag
indicates
to
the supervisor
that the
operator wants to see the limits and
defaults for all questions printed by the
program.

ALL

All flags in this list.

3.6.2
Clear Control Flag Command
Syntax: CLEAR [FLAGS] <argument list> <CR>
The clear command clears the flags specified by <argument list>;
no o the r f 1 ag s are affected • The <a r g um en t 1 is t > i s a st r in g o f
flag mnemonics separated by commas. The supported arguments are
described in Table 3-3.
3.6.3
Set Control Flag Default Command
Syntax: SET FLAGS DEFAULT <CR>
This command returns all flags to their initial default
The default flag settings are OPERATOR and PROMPT.

3-12

status·.

3.6.4
Show Control Flags Command
Syntax: SHOW FLAGS <CR>
This command causes the display of all execution control flags and
their current status. The flags are displayed as two mnemonic
lists: one for set flags, one for clear flags.
3.6.5
Set Event Flags Command
Syntax: SET EVENT [FLAGS] <argument list> ! ALL <CR>
This command sets those event flags specified by <argument list>;
no other event flags are affected. The <argument list> is a string
of flag numbers in the range 1--23, separated by commas. The
optional ALL may be specified instead of <argument list>.
Event re 1 ate d services are prov i d ed by the super vi so r to prov i de
intraprocess synchronization and signaling by means of event
flags. Event flags are located in clusters of 32 flags each.
The supervisor provides two event flag clusters. Event flags are
specified by the numbers 0--63. However, flags 24--31 are
restricted for use by VMS. The operator has the capability to
interactively set and clear flags 1--23.
Note that numbers 32--63 are for program use. Number 0 is used by
the supervisor.
3.6.6
Clear Event Flags Command
Syntax: CLEAR EVENT [FLAGS] <argument list> ! ALL <CR>
This command clears those event flags specified by <argument
list>; no other event flags are affected. The optional ALL may be
specified instead of <argument list>.
3.6.7
Show Event Flags Command
Syntax: SHOW EVENT [FLAGS] <CR>
This command causes
currently set.

the

display

list

the

event

flags

3.7
DEBUG AND UTILITY COMMANDS
This group of commands provides the operator with the ability to
alter diagnostic program code. The supervisor allows up to 15
simultaneous breakpoints within the program. The operator can also
examine and/or modify the program image in memory. Optionally, a
modified image can be written to a load device so that patching
need occur only once.
Another feature allows the operator to unconditionally list any or
all of the program error messages.
3.7.1
Set Base Command
Syntax: SET BASE <address> <CR>

3-13

This command loads the address specified into a software register.
This number is then used as a base to which the address specified
in the set breakpoint, clear breakpoint, examine, and deposit
commands is added. The set base command is useful when referencing
code in the diagnostic program listings. The base should be set to
the base address (see the program link map) of the program section
referenced. Then the PC numbers provided in the 1 i stings can be
used directly in referencing locations in the program sections.
NOTE
Virtual address = physical address
(normally) when memory management is
turned off.
3.7.2
Set Breakpoint Command
Syntax: SET BREAKPOINT <address> <CR>
This command causes control to pass to the supervisor when program
execution encounters the <address> previously specified by this
command. A maximum of 15 simultaneous breakpoints can be set
within the diagnostic program.
3.7.3
Clear Breakpoint Command
Syntax: CLEAR BREAKPOINT <address>

ALL <CR>

This command clears the previously set breakpoint at the memory
location specified by <address>. If no breakpoint existed at the
specified address, no error message is given. An optional argument
of all clears all previously defined breakpoints.
3.7.4
Show Breakpoints Command
Syntax: SHOW BREAKPOINTS <CR>
This command displays all currently defined breakpoints.
3.7.5
Set Default Command
Syntax: SET DEFAULT <argument list> <CR>
This command causes setting of default qualifiers for the examine
and deposit commands. The <argument list> argument consists of a
data length default and/or radix default qualifiers. If both
qualifiers are present, they are separated by a comma. If only one
default qualifier is specified, the other one is not affected.
Default defaults are HEX and LONG. Default qualifiers are:
Data Length: Byte, Word, Long
Radix: Hexadecimal, Decimal, Octal
3.7.6
Examine Command
Syntax: EXAMINE [ <qualifiers>]

[<address>] <CR>

The examine command displays the contents of memory in the format
described by the qualifiers. If no qualifiers are specified, the
default qualifiers set by a previous default command are
implemented. The applicable qualifiers are described in Table 3-4.
3-14

Table 3-4

Qualifier Descriptions

Qualifier

Description

Address points to a byte

Address points to a word

Address points to a longword

Display in hexadecimal radix

Display in decimal radix

Display in octal radix

Display in ASCII bytes

When specified, the <address> argument is accepted in hexadecimal
format unless some other radix has been set with the set default
command. Optionally, <address> may be specified by immediately
preceding the address argument with %D OR %0, respectively.
<Address> may also be one of the following: R0--Rll, AP, FP, SP,
PC, PSL.
3.7.7
Deposit Command
Syntax: DEPOSIT [ <qualifiers> ] <address> <data> <CR>
The command accepts data and writes it into the memory location
specified by <address> in the format described by the qualifiers.
If no qualifiers are specified, the default qualifiers are
implemented. The applicable qualifiers are identical to those of
the examine command and described in Table 3-4.
The <address> argument is accepted in hexadecimal format unless
some other radix has been set with the set default command.
Optionally, <address> may be specified as decimal or octal by
immediately preceding <address> with %D or %0, respectively.

J-15

CHAPTER 4
MICRODIAGNOSTIC DESCRIPTION
4.1

MICRODIAGNOSTIC PROGRAM OVERVIEW

The microdiagnostic programs provide module isolation for logic
failures within the CPU,
floating-point,
and MDS memory
controllers.
All detected failures result in an error printout
indicating the module, or smallest set of modules, to which the
microdiagnostic~ can isolate the failure.
The microdiagnostic package consists of two major test divisions:
console adapter and hardcore, and microtests.
Each test division
is
controlled
by
an
associated
monitor
that
provides
non-diagnostic services to that division.
a.
b.

Hardcore Monitor -- Console Adapter and Hardcore Program
Microtest Monitor -- Microtest Program

Both test division monitors are serviced by the console-resident
microdiagnostic monitor.
In addition to loading the hardcore and
microtest monitors, the microdiagnostic monitor allows the
operator test selection and execution options (Paragraph 4.6).
In
order to reduce the address space required to execute the hardcore
and microtest programs, the common code of both programs has been
incorporated into the microdiagnostic monitor.
That code, which
is unique to either the hardcore tests or microtests, has been
incorporated into the associated monitors.
The microdiagnostics reside on diskettes for the floppy drive.
The basic test sequence is:
1) hardcore tests, 2) microtests.
The hardcore tests verify the operation of the minimum logic
r eq u i red to re 1 i ab 1 y execute the mi c rotes ts •
·The min i mum 1 og i c
consists of the basic hardware elements required for data transfer
and error reporting.
The code, data, and structure required by the microdiagnostics
prohibit them from being resident in the LSI-11 address space at
any one time.
The hardcore tests are executed out of a small
buffer area in the LSI-11 memory.
The microtests are executed out
of the WCS of the VAX-11/780 CPU.

4.2

BASIC PROGRAM EXECUTION

With the console program resident (in LSI-11 memory), the operator
can execute the entire microdiagnostic package by issuing the test
command.
The console program overlays
itself with
the
microdiagnostic monitor from the console floppy.
(However, the
floppy and terminal software drivers are not overlaid since they
provide utility service to each of the monitors.)
In turn, the microdiagnostic monitor transfers the hardcore
monitor into the LSI-11 memory from the floppy.
The hardcore
tests are then executed sequentially out of the buffer in the
LSI-11 memory.
On completion of the hardcore tests, the hardcore
monitor notifies the microdiagnostic monitor. The microdiagnostic
4-1

monitor, in turn, transfers the microtest monitor into the LSI-11
memory (from floppy) •
The microtest monitor then executes the
microtests out of the WCS in approximately lK microword overlays.
On completion of the microtests, control is returned to the
console program.
Fig.ure 4-1 illustrates program residency in the LSI-11 memory.
Note that those items on a horizontal line are exclusive in
memory; e.g., the console program or the microdiagnostic monitor
may be resident, but not both.
As previously mentioned, the
floppy and terminal drivers (and software bootstrap) are always
resident.

4.3

BASIC TEST STRATEGY

The basic test strategy is to transfer data from a test source and
load it into the logic element under test.
The next step is to
retrieve the data from that element and compare it with the
original data loaded.
Depending on the test requirements, logic
element structure, and functional location, the retrieved data may
or may not have a true compare.
In either case, the fail/no fail
dee is ion is based on the expected results.
In some tests, the
same logic is tested using an array of data patterns.

HARDCORE
TEST STREAM
OVERLAYS
MICRO-CODE
BUFFER

i
wcs
DEBUGGER

l
HARDCORE
MONITOR

MICRO-TESTS
MONITOR

CONSOLE

MICRODIAGNOSTIC
MONITOR

FLOPPY &
TERMINAL
DRIVERS
TK-0754

Figure 4-1

LSI-11 Memory Program Residency

4-2

It is essential to the test strategy that the basic load and error
reporting paths are initially tested for reliable operation.
In
an error-free situation, the microdiagnostic can notify the user
when a test is completed.
In the case of error detection, the
microdiagnostic can identify for the user:
the failed module and
test, the data pattern used, and the expected test result.
A simplified test procedure is illustrated in Figure 4-2.
that a true compare is not necessarily the expected result.

START

GENERATE TEST
DATA, WRITE
TO REGISTER

READ REGISTER
COMPARE DATA

DISPLAY:
TEST 1.D.
TEST DATA
RESULTS

YES

HALT
OR
REPEAT TEST
OR
NEXT TEST

NEXT
TEST

TK-0779

Figure 4-2

Simplified Microdiagnostic Test Procedure

4-3

Note

4.4
HARDCORE TEST DESCRIPTION
The hardcore tests are the in i ti a 1 set o f mi c rod i a gn o st i c tests
executed. Paragraph 4.4.1 describes the hardcore test structure.
The hardcore tests initially check the control and data registers
of the Console Interface Board (CIB). This ensures test access to
the VAX ID Bus. After the CIB tests, the clock board is tested.
The clock is turned on and off, single-stepped, and certain clock
function status is retrieved over the Visibility Bus (V Bus).
The next element tested is the microsequencer. For example, data
is transferred onto the microstack and then retrieved. An address
is placed on the microstack. The maintenance return feature is
then used to pop the address off the microstack and load it into
the micro PC. This allows the microaddress paths to be tested in
small segments.
As shown in Figure 4-3, the remainder of the hardcore test
sequence tests WCS, PROM Control Store (PCS), and basic elements
of the data path.
Generally, these are address integrity and
parity checking tests.
The WCS is tested by writing a variety of
address and data patterns to it, and checking for good parity, or
forced bad parity.
The basic elements of the data path are tested by writing data to
certain registers, reading that data back, and comparing the
results.
The data path is tested for its ability to transmit and
retain expected data.
The basic capabilities of the Arithmetic
Logic Unit (ALU) to transfer and compare data are tested.
The
scratch pads are also tested for retaining data; the scratch pads
are used to hold error data in the case of error detection.

4-4

I
I

START/STOP
STATUS

I
I

ADDRESS PAT HS
TRAPS. ECO'S
STACK
MAINT. RETUR N
p

CIB

r--- I - - -

DATA REGS
CONTROUSTATUS
ID BUS
CLOCK CONTROL

wcs
PARITY GEN.
ADDRESS INT EG.
DATA INTEG.

PCS
PARITY CHECK ER
ADDRESS INT EG.

1-----i

ID BUS

Figure 4-3

USC

I
HARDCORE
TESTS

CLOCK

r---1

DATA
PATH

Q& DREGS.
SCRATCH PADS
ALU
ZERO BRANCH
·TK-0751

Hardcore Test Sequence

4.4.1
Hardcore Test Structure
Because of the limited LSI-11 memory address space, the hardcore
tests are _sequentially loaded from the floppy and executed out of
a l.SK byte buffer in the LSI-11 memory.
The hardcore tests are
implemented using special pseudo instructions.
The pseudo
instructions are actually functional statements, where each
statement produces a table of parameters that resemble op codes
and operand addresses.
The hardcore monitor contains a software PC which, in effect, is a
pointer into the tables.
Based on the content of the op codes and
operands, the monitor calls subroutines that are written in PDP-11
code to perform the operation required by a specific test.
Implementing test code in this manner allows a large test
functionality to reside in a small address space.

4-5

4.4.2
Pseudo Instruction Description
The following paragraphs describe the hardcore test pseudo
instructions and their associated statement formats.
Table 4-1
defines the symbols and abbreviations used in describing the
statement formats.
Table 4-1

Instruction Symbol/Abbreviation Definitions

Item

Definition

< >

Used to denote a category name or argument within a
functional statement, e.g., <SCR ADDRESS> represents a
valid source address.

[

Used to indicate that part of a functional statement
that
is
optional,
e.g.,
[<WCS ADDRESS
INDEX>],
represents an address index value that may or may not be
specified depending on the functional statement.

]

Used to separate category names
functional statement.
SCR

Abbreviation for source.

DST

Abbreviation for destination.

I,J,K

Legal index names.

arguments within a

Each pseudo instruction description is divided
into two
descriptive segments.
The format segment describes the statement
format using the symbols defined in Table 4-1.
The instruction
description is a brief paragraph describing general command
operation and the available options. Each instruction description
is preceded by the instruction mnemonic in boldface type.
BLKMIC
BLKMIC

<SCR ADDRESS>, <SCR INDEX>, <WCS ADDRESS>,
<WORD COUNT>, [<WCS ADDRESS INDEX>]

Move the <WORD COUNT> number of 96-bit microwords from the <SCR
ADDRESS>, indexed by <SCR INDEX>, to the WCS starting at <WCS
ADDRESS>, indexed by <WCS ADDRESS INDEX>.
If an <SCR INDEX> is
specified, the <SCR ADDRESS> is indexed by six PDP-11 words (i.e.,
96 bits).
If the <WCS ADDRESS> starts with an alpha character, the <WCS
ADDRESS> is used as a pointer to a table in the test data area of
the test. Otherwise, it is used as a physical WCS address.
For example, if the current value of the index is 2, 14
(<SCR
8
INDEX> * 6) would be added to the <SCR ADDRESS> to find the first
96-bit microword to load into the WCS.
4-6

CHKPNT
CHKPNT [<PASS ADDRESS)],

[<FAIL ADDRESS>]

If the error flag, set during a compare instruction (see CMPXXX
instructions), is zero, go to the <PASS ADDRESS>.
If the error
flag is not zero, go to the <FAIL ADDRESS>.
If neither a pass nor
a fail address is specified, go to the next instruction in line.
The address of the next instruction is typed.
These
appear on the typed line named TRACE (Figure 4-10).

addresses

CLOCK
CLOCK <TIMES>
Step the system clock <TIMES> number of single time states.
<TIMES> is an integral number of four, single bus cycles
executed for each four <TIMES>.

If
are

CMPC A
CMPCA [<MODE>], <REGISTER>, <DST ADDRESS>, [<DST ADDRESS INDEX>]
Compare the contents of the console register specified by
<REGISTER> with the contents of the location specified by <DST
ADDRESS>, indexed by <DST ADDRESS INDEX>. The <MODE> argument is
generally EQUAL. If left blank, the default for <MODE> is EQUAL.
If the comparison is false, set the error flag.
argument is not specified, it defaults to EQUAL.

the

<MODE>

If the <REGISTER> argument is specified as IDREGLO or IDREGHI, the
register used in the comparison is the ID Bus register that was
read in the most recent READID instruction.
CMPCAD
CMPCAD [<MODE>], <REGISTER>, <DST ADDRESS>,

[<DST ADDRESS

INDEX>]

Comp a re the con tents of the console registers specified by
<REGISTER> and <REGISTER>+2 with the contents of the location
specified by <DST ADDRESS> and <DST ADDRESS>+2, indexed by <DST
ADDRESS INDEX>.
If the com par i son i s fa 1 s e , set the error f 1 a g •
argument is not specified, it defaults to EQUAL.

the

<MODE>

If the <REGISTER> argument is specified as IDREGLO or IDREGHI, the
register used in the comparison is the ID Bus register that was
read in the most recent READID instruction.

4-7

CMPCAM
CMPCAM

[<MODE>], <REGISTER>, <MASK ADDRESS>, [<MASK ADDRESS
INDEX>], <DST ADDRESS>, [<DST ADDRESS INDEX>]

Take the content of the console register specified by <REGISTER>,
mask it with the content of the <MASK ADDRESS>, indexed by <MASK
ADDRESS INDEX>, and compare it with the content of <DST ADDRESS>,
indexed by <DST ADDRESS INDEX>.
If the comparison is false, set the error flag.
argument is not specified, it defaults to EQUAL.

the

<MODE>

[<MODE>], <REGISTER>, <MASK ADDRESS>, [<MASK ADDRESS
INDEX>], <DST ADDRESS>, [<DST ADDRESS INDEX>]

Take the content of the console registers specified by <REGISTER>
and <REGISTER>+2, mask it with the contents of <MASK ADDRESS> and
<MASK ADDRESS>+2, indexed by <MASK ADDRESS INDEX>, and compare it
with the contents of <DST ADDRESS> and <DST ADDRESS>+2, indexed by
<DST ADDRESS INDEX>.
If the <MODE> argument is false, set the error flag.
<MODE> argument is not specified, it defaults to EQUAL.

the

If the <REGISTER> argument is specified as IDREGLO or IDREGHI, the
register used in the comparison is the ID Bus register that was
read in the most recent READIN instruction.
The mask is performed by taking the content of <MASK ADDRESS> and
<MASK ADDRESS>+2, indexed by <MASK ADDRESS INDEX>, complementing
it, and bit-clearing the contents of <REGISTER> and <REGISTER>+2.
CMPPCSV
CMPPCSV <DST ADDRESS>, [<DST ADDRESS INDEX>]
Compare the content of the PC save register with the content of
the location specified by <DST ADDRESS>, indexed by <DST ADDRESS
INDEX>.
If the contents are not equal, set the error flag.

4-8

END LOOP
ENDLOOP <INDEX NAME>
Add the increment value of <INDEX NAME> (see loop instruction) to
the current value of the index specified by <INDEX NAME>. Compare
the current value with the last value (specified in the loop
instruction).
If the current value is less than or equal to the
last value, go to the instruction following the associated (I, J,
or K) loop instruction.
Otherwise, go to the next sequential
instruction.
ERRLOOP
ERR LOOP
Save the address of the next instruction.
If an error is
detected, and the loop or error flag is set (Paragraph 4.6),
execution is restarted at this saved address after the IFERROR
instruction is executed (Figure 4-11).
FETCH
FETCH <WCS ADDRESS>, [<WCS ADDRESS INDEX>], [<WCS ROM NOP>]
If <WCS ADDRESS> is a numeric string, execute a maintenance return
to the location specified by <WCS ADDRESS>, indexed by <WCS
ADDRESS INDEX>.
If <WCS ADDRESS> is an alphanumeric string,
execute a maintenance return to the location specified by the
content of <WCS ADDRESS>, indexed by <WCS ADDRESS INDEX>. If <ROM
NOP> is specified, clear bit 7 of the Machine Control Register
(MCR) during the maintenance return.
FLTONE
FLTONE <DST ADDRESS>, <INDEX NAME>
Generate a 32-bi t word of all zeros•
Insert a logic one in the
bit postion specified by the current value minus one of <INDEX
NAME>, and load this word into the location specified by <DST
ADDRESS> and <DST ADDRESS>+2.
FLTZRO
FLTZRO <DST ADDRESS>, <INDEX NAME>
Generate a 32-bi t word of all logic ones.
Insert a zero in the
bit position specified by the current value minus one of <INDEX
NAME>, and load this word into the location specified by <DST
ADDRESS> and <DST ADDRESS>+2.

4-9

IF ERROR
IFERROR [<MESSAGE NUMBER>], [<FAIL ADDRESS>]
If the error flag is nonzero, type the PC of this instruction, the
test number, subtest number, and the good and bad data.
Then, go
to <FAIL ADDRESS> if the HALTD flag is not set (Paragraph 4.6).
If the error flag is zero, or the <FAIL ADDRESS> is not specified,
go to the next instruction.
INITIALIZE
INITIALIZE
Set and clear the CPU initialize bit in the MCR, clear the single
time state bit, set the single bus cycle bit, set the ROM NOP bit,
and set the proceed bit in the MCR.
KMXGEN
KMXGEN <SRC ADDRESS>, <INDEX NAME>
Generate the KMUX address specified by the current value minus one
of <INDEX NAME> and load it in to the KMU X field of the
microinstruction specified by <SRC ADDRESS>. <SRC ADDRESS> points
to a six word table in the test data section of the test that
contains the microinstruction.
LDIDREG
LDIDREG <REGISTER>, <SRC ADDRESS>,

[<SRC ADDRESS INDEX>]

Load the ID Bus register specified by <REGISTER> with the contents
of the locations specified by <SCR ADDRESS> and <SCR ADDRESS>+2,
indexed by <SRC ADDRESS INDEX>.
If <REGISTER> is the microstack, microbreak, or WCS address, the
content of <SCR ADDRESS> is taken to be 16 bits.
Otherwise, it is
taken to be 32 bits.
LO ADC A
LOADCA <REGISTER>, <SRC ADDRESS>, [<SRC ADDRESS INDEX>]
Load the console register specified by <REGISTER> with the
content of the location specified by <SRC ADDRESS>, indexed by
<SRC ADDRESS INDEX>. This instruction loads 16 bits of data.

4-10

LOOP
LOOP <INDEX NAME>, <START>, <END>, [<SIZE DEPENDENT>]
Initialize the loop parameter specified by <INDEX NAME> to the
value specified by <START>.
Save the value specified by <END> for
the ENDLOOP instruction.
Calculate and save the increment value
for the ENDLOOP instruction with the following algorithm:
If <START> is less than or equal to
<END>, set the increment value to +l;
otherwise, set it to -1.
If <END> is an <INDEX NAME>, save the current value of that index
name as the <END> value of this index name.
If <SIZE DEPENDENT> is specified, and there is only one WCS module
on the system, divide the larger of <START> and <END> by two.
Otherwise, leave them unchanged.
NOTE
The tests are written for two WCS
modules. This argument allows the loop
parameters to be modified at run time if
the system only has one module.
MASK
MASK <DST ADDRESS>, <MASK ADDRESS>
Take the content of location <MASK ADDRESS>, complement
bit-clear the content of location <DST ADDRESS> with it.

it, and

MOVE

MOVE <SRC ADDRESS>, [<SRC ADDRESS INDEX>], <DST ADDRESS>
Move the content of <SRC ADDRESS INDEX> (indexed by <SRC ADDRESS
INDEX>) to the location specified by <DST ADDRESS>.
NEWTST
NEWTST

<TEST NAME>, [<TEST DESCRIPTION>], [<LOGIC
DESCRIPTION>], [<ERROR DESCRIPTION>], [<SYNC POINT
DESCRIPTION>]

This instruction creates a test header document for the specified
arguments.
It clears the error flag and saves the PC of the next
instruction for looping on test.

4-11

READ ID
READID <REGISTER>
Read the ID Bus register specified by <REGISTER>
content into locations IDREGLO and IDREGHI.

and

load

the

RESET
RESET
Execute an LSI-11 reset instruction.
REPORT
REPORT <MODULE NAME STRING>
Type out the module numbers of the modules specified by <MODULE
NAME STRING>.
If the HALT I flag is set, return to the
microdiagnostic monitor.

SETPSW
SETPSW <DATA>
Load the
<DATA>.

LSI

processor

status word with the value

specified by

SETVEC
SETVEC <VECTOR ADDRESS>
Set the LSI-11 address
expected trap routine.

specified

<VECTOR

ADDRESS>

the

SKIP
SKIP [<DST ADDRESS>]
Go to the <DST ADDRESS>.
If <DST ADDRESS> is not specified, go to
the next test.
If <DST ADDRESS> starts with the alpha character
S, go to the next subtest.
SUBTEST
SUBTEST
Increment the subtest counter.

4-12

TSTVB
TSTVB <SRC TABLE ADDRESS>, [<SRC TABLE ADDRESS INDEX>]
Load and read the V Bus. Compare the contents of the data at <SRC
TABLE ADDRESS>, indexed by <SRC TABLE ADDRESS INDEX>, with the V
Bus data just read. The <SRC TABLE> has the following format:
1 $:

2$:

.WORD
VB USG

<NUMBER OF BITS TO CHECK>
<CHANNEL NUMBER>, <BIT NUMBER>,
VALUE>

<EXPECTED BIT

.WORD
VB USG

<NUMBER OF BITS TO CHECK>
<CHANNEL NUMBER>, <BIT NUMBER>,
VALUE>

<EXPECTED BIT

VBUSG is a MACRO name that encodes the three arguments
16-bit word as follows:

into one

BITS <07:00> = <CHANNEL NUMBER>
BITS <14:08> = <BIT NUMBER)
BIT <15> = <EXPECTED BIT VALUE>
The following is an example of the <SRC TABLE ADDRESS INDEX>:
TSTVB 1$,I
If the current value of the <SRC TABLE ADDRESS INDEX> is 2,
and the <SRC TABLE> looks like the preceding table, the
physical <SRC TABLE ADDRESS> would be 2$.
TYPSIZE
TYPSIZE
Use the content of location BADDATA, which contains the value of
the WCS data register when it was read, to determine the WCS
module configuration, and type a message and the number of WCS
modules that will be tested.
If any of the following conditions
exist, the test stream is aborted and the NER (No Error Report)
flag is set.
a.
b.
c.

WCS module count is zero
bits 3--0 are nonzero
fifth K of WCS is not present

These conditions mean that the WCS is either configured
incorrectly or the WCS data register cannot be read correctly.

4-13

4.5
MICROTEST DESCRIPTION
On completion of the hardcore tests, the microdiagnostic monitor
overlays the hardcore monitor with the microtest monitor.
Microtest sequencing and execution are then controlled by the
microtest monitor.
The microtest monitor begins to load the microtests from the
floppy into the same buffer area used by the hardcore tests.
However, in the case of microtests, this area is strictly a
buffer. Since the microtests are implemented in system microcode,
the tests are transferred from the buffer and loaded into and
executed out of the WCS.
The monitor references a table that contains the WCS addresses of
the first instruction of every test in the overlay (section) that
was just loaded in order to locate the address of the first test
(first entry in the table). The address is loaded onto the
microstack.
A maintenance return is performed, popping the
address from the microstack into the micro PC and initiating
execution of the first test.
At the end of each test, the
microtest monitor is interrupted.
This allows the monitor to
check that the microtests are being executed in the correct order.
The monitor then initiates the next test with another maintenance
return.
This sequence continues until the original lK microword
overlay has been executed.
At this point, the microtest monitor
loads another lK microword overlay into WCS.
Because of the microtest package size, more than one diskette is
required for storage. When the monitor executes the last test on
a diskette, it determines whether it is the last test of the
entire package.
In the case where it is the last test, the
monitor prints out a message to the operator with instructions to
load the next sequential diskette and enter a command to continue
microtest execution (Paragraph 4.8).
4.5.1
Microtest Structure
The initial microtests complete the data path testing started by
the hardcore tests.
The microtests then begin to test the
Translation Buffer (TB) and cache without using memory. The tests
check the TB and cache for their ability to retain correct address
and data information, and to check parity correctly.
The Instruction Buffer (IB) tests are then executed, again without
using memory.
The IB test data is loaded into cache.
The
microtests cause instruction test patterns to be retrieved from
cache, and check the IB branching functions ·and controls for the
data path.
The interrupt and condition code logic is checked in a similar
manner (i.e., test data loaded into and subsequently retrieved
from cache.)

4-14

The next test segment covers the SB! control logic and its
maintenance functions, and the memory system.
After performing
these tests, the micro tests go back and test those functions of
the TB, cache, and SB! subsystem that depend on retrieving data
from memory (e.g., cache, SB! faults, etc.).
A minimal amount of
testing is performed on the Unibus and Massbus adapters.
These
tests force selected errors on the SBI and determine the adapters'
capability to detect and react to the forced errors correctly.
The floating-point accelerator is tested last.
Figure 4-4 shows the microtest sequence.

DATA PATH

TB, CACHE
W/O MEMORY

18 (W/0 MEMORY)
18 BRANCH
FUNCTIONS,
CONTROLS FOR
DATA PATH
INTERRUPT &
CONDITION
CODE LOGIC
µTESTS
$81 CONTROL
LOGIC,
MAINTENANCE
FEATURES,
MEMORY SYSTEM

TB, CACHE, SBI
FUNCTIONS
PERTAINING
TO MEMORY

MINIMAL UBA,
MBA TESTING

FPA

TK-0778

Figure 4-4

Microtest Structure
4- 15

On completion of the microtests, control is returned through the
microdiagnostic monitor to the console program.
The console
reboots, sends the relevant bootstrap header information to the
console terminal, and prompts for operator input.
4.6
MICRODIAGNOSTIC MONITOR CONTROLS
The following paragraphs describe the operator command execution
control functions provided by the microdiagnostic monitor.
Where
appropriate, examples of command and program control flag usage
are included.
Also included is a description of microdiagnostic
related error messages.
The majority of the commands available in the microdiagnostic
monitor are not used in the normal course of execution. Normally
the operator enters the test command and executes the entire
microdiagnostic package. The command mode is usually used
following error detection.
Following the error message printout,
testing stops and control is returned to the monitor command mode.
At this point, the operator executes those microdiagnostic
commands he decides would be most helpful.
Symbols used in the command syntax a re the comma and < >.
The
comma is used to separate items within a list.
< > denotes an
argument, that is, either an address, pass count value, or a V Bus
channel.
Note that every command (or command line) must be
terminated with a carriage return (CR).
Control C (AC) is the user interrupt control character.
If
Control C is entered during test execution, the current test will
complete, further testing is suspended, and control is returned to
the monitor command mode.
If Control C is entered while a test is
looping on an error, the loop will be suspended and control
returned to the command mode.
Any command may be aborted if a
Control C is entered in that command line.
Table 4-2 describes the monitor commands.
Note that although all
commands, keywords, qualifiers, and flags are spelled out, they
can be abbreviated to the first two characters.
The only
exceptions are the halt on error detection and halt on error
isolation flags, which must be typed HD and HI, respectively.

4-16

Table 4-2

Microdiagnostic Command/Flag Descriptions

Command/Flag

Description

DIAGNOSE

Initializes the program control flags,
and starts microdiagnostic execution at
test number one.
Valid qualifiers are:
/TEST: <NUMBER> -- Dispatch to the test
number specified (do not execute any
prior tests) , and loop on the test
indefinitely.
/SECTION: <NUMBER> -- Dispatch to the
sect ion
numb e r
spec i f i e d
(do
no t
execute any prior sections), and loop
on the section indefinitely.
/PASS: <NUMBER> -- Execute the microd i agnostics and the specified number of
passes before returning to the console.
If the number is -1, execute the microdiagnostics indefinitely.
/CONTINUE
Used with the /TEST or
/SECT switch to automatically continue
after the specified test or section has
been reached.
/TEST: <N> <M> -- Dispatch to test <N>,
execute
tests
<N>
through
<M>
( i n c 1 us i v e ) , and r e t u r n to co mm and
mode.
/SECT: <N> <M> -- Di spat ch to sect ion
<N>, execute sections <N> through <M>
(inclusive), and return to command
mode.
NOTE
In the preceding variations of the
/TEST and /SECTION qualifiers, the value
of <N> must be less than or equal to
<M>. If <M> is less than <N>, testing
will start at <N> and continue to the
end.
/TEST and /SECT
simultaneously.

Examples

cannot

specified

DIAG/TEST:2F
Dispatch to test number 2F and execute
it indefinitely.
4-17

Table 4-2

Microdiagnostic Command/Flag Descriptions (Cont)

Command/Flag

Description
DIAG/SECT:B
Dispatch to section number
execute it indefinitely.
DIAG/PASS:--1
Execute all of
indefinitely.

the

and

microdiagnostics

DIAG/TEST:2F/CONT
Dispatch to test 2F and start execution
of the remaining tests.
CONTINUE

Continues microdiagnostic execution
without changing the program control
f 1 ag s.

Set and Clear Flags
SET/CLEAR FLAG HD

Sets (or clears)
detection flag.

the

halt

error

SET/CLEAR FLAG HI

Sets (or clears)
isolation flag.

the

halt

error

SET/CLEAR FLAG LOOP

Sets
flag.

(or

clears)

the

loop

error

SET/CLEAR FLAG NER

Sets (or
flag.

clears)

the

error

report

SET/CLEAR FLAG BELL

Sets (or
flag.

clears)

the

SET/CLEAR FLAG ERABT

Sets (or clears)

CLEAR FLAG LS

Clears the loop on special section
flag.
(Note that this flag cannot be
set.)

CLEAR LT FLAG

Clears the loop on special test flag.
(Note that this flag cannot be set.)

SET/CLEAR FLAG ALL

Sets (or
flags.

SET/CLEAR SOMM

Sets (or clears)
bit.

SET/CLEAR SOMM:<ADDRESS>

Loads address into the CPU microsync
register, and sets (or clears) the stop
on micromatch bit.
4-18

clears)

bell

error

the error abort flag.

all

the

the stop on micromatch

Table 4-2

Microdiagnostic Command/Flag Descriptions (Cont)

Command/Flag

Description

SET/CLEAR FPA:<ADDRESS>

Loads <ADDRESS> into the FPA microsync
register.

SET STEP STATE

Sets the
state.

SET STEP BUS

Sets the CPU clock to single bus cycle.

CPU

clock

single

time

Both the SET STEP STATE and SET STEP
BUS commands cause the monitor to enter
step mode. Step mode types the current
clock state or the UPC value, and waits
for terminal input.
If a space is
typed, the clock is triggered and the
current UPC value is typed out.
If any
other character is entered, step mode
is exited.
SET STEP INSTRUCTION

Sets the software single instruction
flag and returns to the monitor.
When
the hardcore tests are invoked, the
current value of the Test PC (TPC) is
typed.
The monitor waits for terminal
input.
If a space is typed, the
current pseudo instruction is executed
and the current value of the TPC is
typed.
If any other character is
typed, step mode is exited.

SET CLOCK FAST

Sets the
margin.

CPU clock speed

the

fast

SET CLOCK SLOW

Sets the CPU clock speed
margin.

the

slow

SET CLOCK NORMAL

Sets the CPU clock speed to normal.

SET CLOCK EXTERNAL

Sets the CPU
oscillator.

SHOW

Causes a display of the HD, HI, LOOP,
NER, BELL, ERABT, LS, and LT flags.

LOOP

Clears the HD and HI flags. Sets the
LOOP and NER flags and executes a
continue command.

RETURN

Returns control to the console program.

4-19

clock

for

external

Table 4-2

Microdiagnostic Command/Flag Descriptions (Cont)

Command/Flag

Description

Examine Commands

The following examine commands cause
the current microinstruction to be
executed
before
the
examine
is
performed, if it is the first examine
since entering the monitor command
mode.
All successive examines do not
execute
any
additional
microinstructions. ID Bus registers
Tl--T8
are
destroyed
during
the
exam in es,
except
for
the
V Bus
examines.
All
of
the
following
examines, except V Bus, advance the
clock to CPT0 before executing the
command.

EXAMINE ID:<ADDRESS>

Displays the content of the ID Bus
register specified by <ADDRESS>.

EXAMINE VBUS:<CHANNEL>

Di splays the content of the V BUS
channel specified by <CHANNEL>.
Bit 0
is at the right side of the display.

EXAMINE RA:<ADDRESS>

Displays the content of the RA scratch
pad specified by <ADDRESS>.

EXAMINE RC:<ADDRESS>

Displays the content of the RC scratch
pad specified by <ADDRESS>.

EXAMINE LA

Displays the content of the LA latch.

EXAMINE LC

Displays the content of the LC latch.

EXAMINE DR

Displays the content of the D register.

EXAMINE QR

Displays the content of the Q register.

EXAMINE SC

Displays
register.

the

content

the

EXAMINE FE

Displays
register.

the

content

the

EXAMINE VA

Displays
register.

the

content

the

EXAMINE PC

Registers
counter.

the

program

4-20

content

Table 4-2

Microdiagnostic Command/Flag Descriptions (Cont)

Command/Flag

Description

Deposit Commands

The deposit command is the same as the
examine command, except that the data
to be deposited must be supplied by the
user.

DEPOSIT ID:
DEPOSIT RA:
DEPOSIT RC:
DEPOSIT LA:
DEPOSIT LC:
DEPOSIT DR:
DEPOSIT QR:
DEPOSIT SC:
DEPOSIT FE:
DEPOSIT VA:
DEPOSIT PC:

4.6.l
Monitor Control Examples
The following paragraphs provide usage examples of selected
monitor controls. These descriptions are brief and are intended
only to indicate some of the capabilities of the microdiagnostic
monitor.
4.6.1.l HD/HI
Flags
In
addition
to
testing,
the
microdiagnostics perform two basic functions: error detection and
error isolation. Under normal circumstances, the user would set
the HI flag. Setting the HI flag initiates the following
microdiagnostic sequence:
a.

Error detection

Call isolation routine to identify the error cause

Display an error message identifying the
data pattern used, and the failing modules

Terminate test execution.

failed

test,

In a situation where the user does not require a scope loop, and
wants to halt execution at the error detection point, the HD flag
is set. This flag halts the test before the microdiagnostic calls
the isolation routine overlay (e.g., V Bus compare).
4.6.1.2 Loop On Error Flag (LOOP) -- With this flag set, the
microdiagnostic will revert to a tight program loop after error
detection (assuming the NER flag is set). Note that the loop will
continue even though the error is intermittent; the flag must be
cleared to break the loop.

4-21

4.6.1.3 No Error Report Flag (NER) -- This flag suppresses the
typing of error messages.
The flag is especially useful in the
case of looping on an error. Since the error printout takes time,
the scope sync is lost during typing time. With error reports
suppressed, the loop is tight and produces a reasonable sync.
4.6.·l.4

Bell On Error Flag (BELL)

Hardcore Tests -- When running the hardcore tests, setting this
flag causes the console terminal to ring its bell when an error
occurs.
This flag is useful in a situation where a manual
adjustment could clear the error.
In this situation, the user
would set the LOOP flag and the NER flag, producing a tight loop.
However, with no error report, the user does not have an
indication of where the error cleared during the adjustment.
Setting the BELL flag is a compromise between a reasonably tight
error loop (the BELL flag slows the loop somewhat) and an error
indication during the adjustment.
If a scope were used during the
adjustment, the user would have an error indication without losing
the scope trace.
Microtests
In the microtests, one must loop on test
(DI/TEST:n); then, after the error message has been printed, set
the NER and BELL flags, clear the HI flag, and type CONTINUE.
4.6.1.5 Continue Command (CONT) -- This command allows the user
to proceed from a microdiagnostic halt situation. For example,
suppose that a hardware ECO, which has not been reflected in the
diagnostic system, is incorporated into the computer. When the
microdiagnostic halts following detection of the pseudo error, the
user can bypass the failing test and continue execution at the
next test by entering CONTINUE.
4.6.1.6 Error Abort Flag (ERABT) -- This flag allows the user to
di splay more than one error report in certain hardcore tests
(tests which exercise a particular piece of logic with more than
one data pattern).
For example, consider the situation where the ERABT flag is set,
and the test detects a type 2 error (ERROR2) on one of the initial
data patterns.
If the user were to enter CONTINUE, the flag would
abort the remainder of the test and initiate execution of the next
sequential test.
However, with the flag cleared, CONTINUE will
initiate execution of the same test with the next sequential data
pattern.
4.7
MICRODIAGNOSTIC RELATED ERROR MESSAGES
The following paragraphs describe the microdiagnostic-related
error message formats and their interpretation.
All error
messages are prefixed by a question mark to distinquish them from
informational messages.

4-22

4.7.1
Syntax Error Messages
?USE DIAG COMMAND
Execution of a continue command was attempted before a diagnose
command.
This would only occur if TEST/COM were used to invoke
the microdiagnostics from the console program.
?INVALID COMMAND
The previously entered command was not recognized.
?INVALID KEYWORD
The argument of a command was not recognized.
?NUMBER MUST BE HEX
A non-hexadecimal number was recognized.
4.7.2
System Error Messages
?OPEN FILE: <NUMBER>
An error was detected and identified while trying to open a floppy
file.
Error code is:
<NUMBER> = 1 = Floppy hardware error
<NUMBER> = 2 = File not found
<NUMBER> = 3 = Floppy not ready
?READ SECTOR: <NUMBER>
An error was detected and identified while trying to read a sector
from the floppy.
Error code is:
<NUMBER> = 4 = Sector number out of range
<NUMBER> = 3 = Floppy queue full
<NUMBER> = 1 = Floppy hardware error
?KEYBOARD ERROR: <NUMBER>
An error was detected and
Error code is:
terminal.

identified

while

trying

read

the

<NUMBER> = 5 = Terminal driver busy
<NUMBER> = 7 = Terminal hardware error
?UNEXPECTED TRAP TO 4 PC =
The LSI-11 trapped to 4 at the specified PC.
4.7.3
Go Chain Monitor Error Messages
?TIMEOUT IN TEST ••• UPC =
Indicates that the microcode is hung. The monitor did not receive
a call from the microcode in the last four seconds.
?EXECUTION OUT OF SEQUENCE UPC = SHOULD BE =
The microcode has not executed the tests within
sequential order.

the overlay in

?CLOCK STOPPED UNEXPECTEDLY
The clock stopped and the SOMM bit was not set.
?ILLEGAL MONITOR CALL: <NUMBER>
The microcode made a call to the
which was <NUMBER>.
4-23

monitor

with

bad

argument,

4.8
PROGRAM LISTING AND ERROR MESSAGE DESCRIPTIONS
The following paragraphs describe microdiagnostic program listings
and error message formats. It is beyond the scope of this chapter
to describe the various diagnostic program assemblers and their
associated languages.
4.8.1
Monitor Listing Descriptions
The program listings for the microdiagnostic-associated monitors
(i.e., microdiagnostic, hardcore, and microtest) share the same
listing format. That is, since the three monitors operate out of
the LSI-11, they are coded in MACR0-11 (PDP-11 assembly language)
and are discussed as one in the general description.
Each listing is comprised of three general sections: Table of
Contents, Program Definitions, and Program Code and Descriptions.
Each page in a listing has a title containing the name of the
program, the date the particular listing was generated, the page
number, and a line item that indicates the content of that page
(listing header) (Figure 4-5).
The Table of Contents is a list of the content of the program
listing. The first (left) column contains a hyphenated number. The
number preceding the hyphen specifies the page number of the
listing on which the line appears. The number following the hyphen
is a listing line number. This number specifies the starting line
(within the listing) of the associated listing content contained
in the right column (e.g., definitions, utility routines, test
sections, etc.)
The Program Definition section specifies register address
assignments, bit definitions, module and bus name assignments, and
other constants that are used throu~hout the program.
The remainder of the listing (and the largest section by far) is
the Program Code and Description section (Figure 4-5). The format
is described on a per column basis from left to right. Note that
the address and data radix for all monitor listings is octal.
Column 1, Listing Line Number -- Each line in the listing
is assigned a unique dee imal number to al 1 ow easy
referencing from the Table of Contents.
Column 2, Address -- The address of the instruction.
Column 3, Content of the Address listed in Column 2 -This is usually an instruction (e.g., reference line
number 79 in Figure 4-5). The address is 101020, and its
content is 032767, which is the octal code for a Bit Test
(BIT) instruction.
Column 4 and 5 -- If the instruction is a two-word or
three-word instruction, the second and third words are
specified in columns 4 and 5, respectively (e.g.,
reference line number 79 in Figure 4-5). This BIT

4-24

LISTING
PAGE
HEADER

ITAR MICRO T!IT MONITOR MACRO Mll
'LAG TEST ROUTINE
75
71
77 111775

.slTTL
1~5067

177131

'LAG TEST ROUTINE

'LGTSTI CLR

TIMER

INITIALIZE THE TIMEOUT TIMER

111121 13278
B•llll
177el4
SIT
•c RL
ON ROL c 'LAG E
TEXT
[?I71~l~l~l~l~1!2:::J~~~:!!!!~C:::I!:~!:!::::::l:l:l::::::lU~P!D:AT:!:S~M~R~~~~C::::::J~~~~;s::~!i:i]UJLr.,_~~~FIRST
I ll
HUI
l!Q
111
BRANCH II' NO
REFERENCI
81 111131
12 111135
13 1111•1
e• 1111••
85 llll•S
ea 111152
17 111171
ea 111178
89 111111
91 111111
91 11112•
92 1111•2
93 llllll
t• 111178
95
2 2
91 111288
97 UUU
98 11121•
99 111221

132717
111•13
11•717

11111•

177P5•

112517

177122

132787
1111•1
152737

11111•

177P1•

111211

l83f32

111•12
1111•1

l83P32

11111•

178854

8!T
9!Q
JSR
GETUPC
MOY

LOOP FLAG SET1
BRANCH 1,-~0
STOP THE CLOCK
GET THE CURRE~T UPC
CIP)+,ITMPI
SAVE
CALLMICM~N .
GO TO THE "ICRO MONITOR
91T
·•LOOP,IWR
LOOP FLAG STILL l!TT
9N!
121
, BRANCH IF YES
8IS
•CLRUWRO,f#CONMCR I GOING TO RESTORE MONITOR C•LLS
LOADID •ERlADR,#UICADR I LOAD THE ERROR l ADDRESS
LOAOID #ERlOAT,#UICDAT r RESTORE THE JUMP ADDR!ll
LOADID •ER2ADR,#UICADR I LOAD THE ENROR 2 ADDRESS
LOADID •ERIDAT,•USCDAT I RESTORE THE JUMP ADDRESS
JSR
PC MRETURM
DO MAINTENANC R TUR ON ORIGINAL UPC
R
P R NC
R
HE
TST8
f#TXRDY
MICROCODE
8MI
UIS
BRANC"4 IF
SECOND
JMP
21
BIT
#CLKSTPD,f#CONMCR I DID THE ShR CL.OCI< STOPT TEXT
8NE
31
I BRANCH IF YES
REFERENCE
81T
#L.OOP,S~R
r L.OOP FLAG SEU
8NE
FL.GTST
I BRANCH IF YES
INC
TIMER
I INCREMENT THE TIMEOuT Tl~ER
8NE
U
I 8RAMCH IF NO TIMEOUT VET

113145

UllJ 111228

111231
111238
113 1112•0
l014 1111244
U5
l~l
1~2

1~11

178888

,.THIS CQD! INDICATES THAT THE MICROCODE HAS 8LOwN UP

117

1"8

119
111 u1ue
111 UUH

112 111272
113 1~1310
11• 111312
115 111311

121767

177314

178548

815767
lf5287

17731•

178554

111~14

ue u131•
117 111330
UI Ul3H
119 UU45
ue UUH

TYP!
TYPE
CMP

17858~

111•18
Ill

I' I
~:~~ING
NUMBER

TYPES
•ITSTNM,H!X
TYPE
#SIXSPC
TYPE
#MSG3
JSR
PC,STOPCLK
LOADYBUS
G!TUPC
MOY
CSP)+,ITMPI
TYPES I #ITMPl,H!X
TYPE
#ICRL.F
CALL.MICHON
SUB
I ••,TSTPTR
JMP
RUT

511

MOV
INC
TYPES

#ICRLF
•MSG2
TSTSAVE,STSTNM
51
TSTSAVE,STMPI
JT"PI
#ITMP8,MEX

8NE

121 111372 1~4787 1~281•
122 UU78
811
U3 U1411
12• 111•12 112887 178•89
12s i11•05
111422 I
I 1211
U7 111•3'
ue 111452 t 1e21e1 eHeu f 11n12 1
1291lit••• 111117 177282
131
t
I
I

•LOOP,IWR
Ill
,C,ITOPCLK

1 j '. t 1NsTRL~N
1
1
I

ADDRESS

CONTENT

ADDRESS

MNEMONIC

LABEL
SECOND AND
THIRD WORDS
OF INSTRUCTION

TYPE TIMEOUT ERROR MESSAGE
IN THE FIRST TEST YETT
BRANCH IF YES

TYPE THE TEST NUM8EA
TYPE SU SPACU
TYPE 11 UPC•"
STOP THE STAR CLOCK

READ THE UPC 8AVE REGISTER
SAVE IT
TYPE THE CURRENT UPC
GO TO THE MICRO MONITOR
RESTART AT THE CURRENT TEST

...

COMMENTS

OPERAND
DEFINITIONS

TK-0773

Figure 4-5

Monitor Listing
Sample

4-25

instruction happens to be a three-word instruction, the
second word is 04000 0, and the third word is 177064.
Thus, this instruction is testing bit 14 ( 0 4 0 0 0 0) to
determine if the Control C flag is set at address 177064.
(Note that this flag was defined in the definition
sect ion.)
Column 6, Label -- This symbol is the name used by the
program mnemonics to reference this instruction (e.g.,
reference 1 ine number 9 5 in Figure 4-5) • The 1 abel in
this case is 12$.
Column 7, Instruction Mnemonic -- This is the assembler
language mnemonic for the instruction (e.g., Bit Test
Instruction= BIT).
Column 8, Operand Definitions -- These symbols and
mnemonics are the assembler language mnemonic definitions
for the operands.
Column 9, Comments -- A brief description
semicolon) of the instruction operation.

(fo~lowing

the

·4.8.2
Hardcore Listing Description
The general format of the hardcore listing is similar to that of
the monitors (i.e., Table of Contents, Program Definitions, and
Program Code and Descriptions). The left column of the Table of
Contents con ta ins a hyphenated number. The number preceding the
hyphen specifies the page number of the listing on which the line
appears. The number following the hyphen is the listing line
number, indicating the starting line of the associated listing
contents. The definition section is similar to the monitor
listings,
i.e., address, module and bus assignments, bit
definitions, and other constants used in the program.
The remainder of the listing is the Program Code and Descriptions.
As indicated in the Table of Contents, the hardcore tests are
composed of sections and tests. The section number represents a
l.SK byte segment. The section number is displayed on the console
t e rm i n a 1 d u r i n g ha rd c o r e t es t
ex e c u t i on • The t e s t n um be r
identifies a test on a particular logic area or function. The
subtest number (which is not referenced in the Table of Contents)
identifies a particular portion of a test. For example, Subtest 1
floats a logic one through each bit of a register; Subtest 2
floats a logic zero through the same register.
As shown in Figure 4-6, the program code is preceded by an
outlined test header area. A subtitle statement (.SBTTL) generates
the test number and title above the header area.
The header area consists of five descriptive segments. The first
line within the outlined header repeats the test number and test
title. The test description segment is a brief paragraph
describing the general logic area tested and method of test. The
logic description segment describes the test in more detail.
4-26

MACRO 14U

MJCAO DIAGNOSTIC MARDCORE TEST
TtC
CS BUS DATA INTEGRITY

.SBTTL

2ll•APA•'T7 1 Wtl1

PlG? n
-

CS BUS DATA INTEGRITY

TtC

SUBTITLE
STATEMENT

''********************************************************************
,rTEST
tC
CS BUS DATA INTEGRITY
,
TEST DESCAIPTJO'N
THIS TEST CHECKS TME DATA INTEGRITY OF TME CS BUS BY ~LOATING
A ONE AND A ZERO THRU A MICRO WORD, EXECUTING TH! MICRO
WORD, AND CHECKI~G THE V BUS 'OR PARITY ERRORS.
SUBTST 1 • FLOAT A ZERO THRU THE CS BUS
SUBTST 2 • FLOAT A ONE THAU THE cs eus

TEST
HEADER
AREA

LOGIC DESCRIPTION
TM!S TEST CHECKS THF. ID AUS INTERFACE TO THE WCS MODULES, TME
DATA INTEGRITY OF THE wCS ME~DRY CHIPS AND THE DATA I"NlEGRITV C~
THE CONTROL STOQE (CS) BUS.
ERROR nESCRIPTION
OATAI EXPECTEO V BUS CHANNEL, BIT ANO VALUE
RECEIVED v ~us CHANNEL, BIT AND VALUE
LOOP COUNT • I~DJCATES WHICH BIT IN TME 32 BIT GROUP lS UNDER
TEST, I.E. l•BIT 0, 2•8IT 11 3•8IT z, !TC.
LOOP COUNT • INDICAT!$ WM!CH lZ 8IT GROUP IS UNDER
TEST, J.E. t• ~ITSC3110~, 2•8ITSC63132>1 3•8ITSc~5164>
NOTE• THE EXPECTED ANO RECEIVED v eus CHANNEL INDICATES WHICH 32 BIT
GROUP MAS AAO PARITY IN IT, I.E. 102~•8ITSc31i~~>,
101X•BITS<63132>, ANO l00X•BITScqsa~4>.
r SYNC POI~T DESCRIPTION

SUATST 1 • SYNC4C••TEST PATTERN rs ACTIVE ON THE cs BUS
SU~TST 2 • SYNC4D••TEST PATTERN IS ACTIVE ON TME cs ~us

,..
111011155~

''********************************************************************

T1CI

2530 1.1100554
2535
2536 000556

PHTULlZE
SUBTEST
Jll/llllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll

00P556
2537
2538
253q
2540
2541 011105&0
2542 00111570
2543 el0057b
2544 111006i'6
2545 000614
25"6
2547 01110&20
2548 00111630
2saql 000636
2550 11101/1644
255111110!J646
2552 P00654

T1CS11
t+

,.#IRST FLOAT A ZERO THRl_I THE es BUS
I

LOO,_
J,1,3
LDIDREG USCAOR,TMPl~~
LOOP
1< 1 1 1 3
LntOREG USCOAT,TMPt~2
ENDLOOP I(

LOOP
I,t,32
I LOOP COUNT ,OR THE BtfS IN A BANK
LDIDREG USCAOR,T~Pt00 1 J t LOAD TH~ BANK AnDRESS
FLTZRO ITMPl01 1 I
r GENERAfl" TME T!ST PlTTE~N
ERLnOP
I
LOIOREGIUSCDAT,TMP101
, LOAD INTO TH! SEL!CT!D 8ANl<
'ETCM
leel00
J I EXECUTE T~E MICRO ~ORO

l l l

LISTING
LINE
NUMBER

ADDRESS

LOOP COUNT ~OR T~E 3 BAN~S
SELECT LOCATION ZERO
INITIALIZE THE CONTENTS 0' LOCATION 0

ADDRESS
CONTENT

INSTRUCTION
OPERANDS

COMMENTS

TK-0769

Figure 4-6

Hardcore Listing Sample

4-27

The error description segment specifies test parameters. For
example, in the error description of Figure 4-6, the first line
specifies what is expected during the test; the second line
specifies what is received. The third line indicates which bit in
the 12-bit array is under test; the fourth line indicates the
32-bit group under test. The sync point segment specifies critical
points in the listing around which an error loop or scope loop
might be set up {Paragraph 4.9.2).
Following the test header is the program code.
listings are described on a per column basis below.

The

hardcore

Column 1, Listing Line Number -- Each line is assigned a
unique decimal number to allow easy referencing.
Column 2, Address
instruction.

The

relative

address

(PC)

of the

Column 3, Address Content
Content of the address
listed in Column 2. (Note that the contents are the
pseudo instructions described in Paragraph 4.4.2.)
Columns 4 and 5, Instruction Operands -- The operands are
the instruction source, destination, or index values. The
mnemonics appearing in these columns have been defined in
the definition section of the listing.
Column 6, Co~ments -- A brief descriptive note concerning
the instruction operation.

4.8.3
Microtest Listing Description
The general format of the microtest listing is somewhat similar to
the other microdiagnostic listings, i.e., a Table of Contents,
Program Definitions, and Program Code and Descriptions. However,
since the microtests are executed out of the WCS, they are written
in system microcode and, therefore, are similar to the system
firmware listings. Unlike the hardcore listings that are assembled
in one listing, the microtests are assembled into separate
listings by lK microword test sections and identified by those
section numbers. Note also that the address and data radix for
these listings is hexadecimal.
The Table of Contents is similar to those of the other listings;
i.e., it con ta ins a 1 ine number entry and the corresponding
listing content description. Since the first column does not
contain assembler directives, only the line number appears. The
Pr o g r am De f i n i t i on sec t i on d es c r i be s a 1 r mac r o d e f i n i t i on s
associated with the listing.
The Program Code and Description section format is similar to that
of the system firmware listing. As in the hardcore listing, the
program code is identical to the hardcore format and content
described in Paragraph 4.8.2.

4-28

The microtest listing is described on a per column basis
4-7).

(Figure

Column 1, UPC
This column specifies the address
contained in the UPC at rhat particular microstate.
Co 1 um n 2 , Mi c r o wo rd
Th i s co 1 um n des c r i bes the
microword content of the address specified in column 1.
Column 3, Listing Line Number -- Decimal number assigned
to allow easy referencing.
Column 4, Microstate Ope rat ion -- This column specifies
the ope r at ion du r in g a pa rt i c u 1 a r m i c r o s tat e • The
notations used to describe the operation have been
defined in the program definition section.
Column 5, Comments -- A brief descriptive note concerning
the
microstate
operation.
(A
detailed
firmware
description is provided in the VAX-11/780 Central
Processor Technical Description, e.g., field definitions,
coding conventions, etc.)
4.8.4
Microdiagnostic Execution
The entire microdiagnostic package may be executed by entering
TEST on the console terminal. Other operation options are
described in the detailed diagnostic operating procedures in The
VAX-11/780 Diagnostic System User's Guide
(EK-DS780-UG-00IT:°
Following microdiagnostic identification the monitors initiate
hardcore and microtest execution. Figure 4-8 illustrates typical
console terminal output during error-free microdiagnostic
execution.
The microtests and hardcore tests are numbered sequentially (with
no duplication of test numbers). As shown in Figure 4-8, there is
no
differentiation
between
hardcore
and
microtests.
A
differentiation is required only in the case of an error
(Paragraph 4.8.5).
The monitor loads the test, and the test section number is printed
on the console terminal. Test execution is then initiated. The
section number is printed (in hexadecimal) prior to execution to
allow the operator to identify the exact failing section in the
case of an error.
The entire microdiagnostic package requires two diskettes. As
indicated in Figure 4-8, the microdiagnostic monitor instructs the
operator when to mount the second diskette, and prompts for the
command required to initiate execution of those diagnostics.
4.8.5
Error Message Format
The
general
error
message
format
microdiagnostics is shown in Figure 4-9.

4-29

for

both

types

DWMtea.MCPt499,)262l
DWMl1l.MJC[489,)262l

12115 21•1PR•t9Tl
l41J5 29•lP'•l917

MlCRO J1C241)
Mieroeod• 111•
TEIT AS C!I REGllTER ALU N IJT

•• ,. '

ePlGE
•T!IT 15
C!I 'tGllTIR ALU N BIT•
,
........................................•...............................
UH

1132
1133
105

UH
1839

1849

TEST
HEADER
AREA

1841
1142
110

1++
t HIT

'' TllT DESCRIPTION
THIS TllT CHECKS TH! ALU N llT IN THE CEI R!GllTIR. THIS Ia DONE

''
'

BY SILICTlNG THI lLU TO DO l+I IND A•I, AND ,.,, WITH SPECIFIC
DATA PATTERNS ON TH! AMX AND BMX TO CHECK TH! LOGIC TMAT GENERATES
Tt!U an.

• CHECK TH! OATA PATTERNS THAT REQUIRE THI ALU TO
IE EXECUTING AN l+B TO GET TME CORRECT ALU DATA1
SUITST 2 • CHECK THE DATA PATTERNS THAT REQUIRE TM! ALU TO
8! EXECUTING AN A•I TO GET THE CORRECT •Lu DATA,
S~BTIT J ~ CHECK THE DATA PATTERNS THAT REIUIRE TH! ALU TO
IE EXECUTING ANYTHIN IUT lN l+I OR A•B 1
SUBTST

1844

1846
1841
1848
1849
18!50

LOGIC DESCRIPTION
TMJS TEST CHECKS TH! LOGIC NETWORK ON THE CEH MODUL! THAT GENERATES
Tffl ALU N BIT, AND TH! MULTlPL!XOa ON TH! ICL MODULE THAT FEEDS
TME ALU N BIT IN TH! C!S R!GlsTERe

1851
1852
!8!53

11!54

!RROR D!ICPlPTION
DATll EXPECTED CES 'EGISTER
RECEIVED C!S '!GIITER
LOOP COUNT • INDICATES WHICH DATA PATTERN IS !EING USED,
Cl!! THE OATA AT THE !ND or TH! TEST)

18!55

11!56
18!5'7

18!51

1859
1860
1161

IYNe POtNT D!SeRIPTION
SUITST 1 • ITNCSA••ALU M BIT G!TI LOADED
IUBTIT 2 • SYNCtl••ALU N IIT GETS LOADED
SUBTST l • SYNClC••ILU N BIT G!'TI LOADED

1862
18U

,......•................•...........................•.....................
,
1867 •0
1864
1865
1866

u 1014,

0011.0eJt,0D10.etr1,eee~.1er1

u 1015, 001e,011e,6se0.eaeP,eeee,1e1s
u t01e, ~e~e.00JD,e1e0.e1e0.e0ee.111s
u 1119, 0e1a,00Je,,sae,eA11,ee0e,11t0

u 1140. Pet810eJe,1te0.eA•e,e0ee.11•1
u 1141, 081a,0eJ8,4180,eeee,eeee,1142

u tt42• 01e0.001c.01s0,ea0010eee.114J
u 1141, 0001,ee1c,e110,0At1,ee0e,11••

1868

lC:LTl 1

I u 1us,1 0000. 1111c ,e1u,c10e,eeeei, 1 tH

u 1146, ee01,0eJc,011e,0aae,~e00,11t1

I 1147,,
,,.,, Ae00,a0Jc,e1e0,c800,ee00,11•9
UU

"'100,08lC,018P,0A08,0a00,tt48

MICRO
PROGRAM
COUNTER
(UPC)

MICROWORD
CONTENT

NtwTST t.ll

1ne •e

CILL,J/UNJAM

11'71

~ClJ-IC[,20]

1172

IH2J-K,t.30]

ADDRESS or lMX DITA
CLEAR ANY S!I INT!PRUPTS
ADDREsa or IMX DlTA
ADDRESS or EXP!CT!D ALU N BIT

D.D,LEFT2
R [ll-0

GENERATE MASK FOR N BIT
SAVE

1869

R [8J-K (, 10]

a.JC r;·1e1

117l
' 1174
187!5

1116

u 1144, 001a,0e1a,DS80,etre,eee0,1e1A
u 1e1A, 000e.eelD,e1ee,010e,eee0,1124
u 101&, 00e0.0eJC,A110,0A00,e200.1t45

CEI REGISTER ALU N BIT

1871

s11111111111111111111111111111111111111111111111111111111111111111111111

1878

1879

I+
1 00

1180

THOS! FUNCTIONS REQUIRING TH! ALU TO DO IN l PLUS B

1111

T8111
RCteCJ.KC.6l
•t
SUBTEST
1814 ICLTBLtlVA..RC8l
1815 I
DCBYTE]-CACHE.P
1816
RtSl.D
1881
VA..R[1)
1888
DCBYTEJ-CACHE,P
1112

SET THE LOP COUNT

188)

LINE
NUMBER

MICROSTATE
OPERATION

FETCH lMX DAfl
SAVE
FETCH BMX.DUA

COMMENTS

TK-0771

Figure 4-7

Microtest Listing
Sample
4-30

>>>TEST

FIRST
TEXT
REFERENCE

MOUNT FLOPPY t2

MIC> DI

SECOND
TEXT
REFERENCE

& TYPE

3Br
t MEM CTRLS= 00000001
3Cr3Dr
4K CHIP OOOOOE08
:3Er3l='r
CPU TR= 00000010
40,41,42,43,44,45,46,47,49,49,4A,
CTRL 1 MAX ADR+1= 00080000
4Br
CTRL 1 MAX ADR+1= 00080000
4c,4ri,
END PASS 000001

OPERATOR
INPUT
UNDERLINED

TK-0772

Figure 4-8

Typical Error-Free Terminal Output

ERROR: <PC> TEST: <#>SUBTEST: <#>
DATA:

xxxxxxxx
xxxxxxxx
•
•
•
xxxxxxxx

TRACE:

W.X.Y.Z

FAILING MODULES: (M8269 (S13) ...
NOTE:
PC IS OCTAL FOR HARDCORE TESTS.
OTHERWISE ALL NUMBERS ARE HEX.
TK-0750

Figure 4-9

Error Message Format

4-31

The first line items are ERROR, TEST, and SUBTEST. ERROR is the
address (PC) of the failing test. In the case of a hardcore test
er r o r , the PC i s d i s pl a ye d as a s i x-d i g it o ct a 1 add res s , since
these tests are executed out of the LSI-11. In the case of a
microtest error, the PC is displayed as a four-digit hexadecimal
address since it executes out of WCS.
TEST is the failing test number. Note that this is different from
the section number sent to the console terminal during error-free
execution. SUBTEST is the failing subtest number. These three
first line items are important in referencing the program listings
(Paragraph 4.9.2).
The DATA 1 ine i tern represents data used during the particular
test. The number of data words displayed depends on the particular
test. Generally, in the hardcore tests two words are displayed;
the first word is the expected (or good) data, the second word is
the received (or bad) data. However, as described in Paragraphs
4.8.2 and 4.8.3, the program listings contain a header describing
the data patterns used.
The TRACE 1 ine i tern is involved in the fault isolation procedure
in determining the set of modules responsible for the failure.
The last 1 ine i tern is FAILING MODULES. The output of this i tern
represents the failing module and its backplane slot number. In
some cases, the output will be several module numbers listed in
the order of failure probability. However, in other cases the
output will not be a module number. For example, consider the
situation of a grounded ID Bus bit. The failure could appear to
extend across all boards on the bus. Rather than printing out all
related modul.e numbers, the program would print out ID BUS.
4.9
LISTING/ERROR MESSAGE CORRELATION
This subsection prov ides basic direction in the use of error
message content and its relationship to the program listings. The
examples are included mainly to ill us tr ate basic microdiagnostic
capabilities.
4.9.1
No Error Message Situation
Consider the situation where the operator has
initiated
microdiagnostic execution using the TEST command. For one reason
or another execution stops in the hardcore tests, and an error
message is not printed. As shown in Figure 4-10, execution stops
on test section 04.
The operator has a reasonable index into the hardcore test
listings since section 04 is one of the initial sections executed.
Referencing the section number in the hardcore listing Table of
Contents, the operator finds that the section 04 description
starts on listing line number 777.

4-32

CONSOLE TERMINAL OUTPUT
>>>TEST
MICRO DIAGNOSTIC V.05
01.02.03,
~: OF WCS MODULES = 0001

LISTING TABLE OF CONTENTS

"ICRO DIAGNOSTIC HARDCORE TEST
TAeLE OF CONTENTS
1•
1•
1•
1·

TEST
NUMBER
INDEX

MACRO Ml~

5
5

CMPCA ANO CMPCAM MODE DEFINITIONS
SWITCH ~EGISTER BIT DEFINITIONS
5
CONSOLE AOAPTER REGISTER DEFINITIONS
5
IO eus REGISTER DEFINTTIONS
l•
5
MODULE AND AUS NAME ASSIGNMENTS
1•
b
SECTION NUMBER 01
2• 42
T~1
CONSOLE ADAPTER REGISTER RESPONSE
l• 141
T02
CONSOLE "TO tO" REGISTER DATA INTEGRITY
4• 2Ab
SECTION NUMBER 02
4• 2~6
T03
CONSOLE "MCA" REGISTER DATA INTEGRITY
5• 284
T04
CONSOLE "IDCS" REGISTER DATA INTEGRITY
6• 356
T0~
CONSOLE RXDNF. ANO TXROV REG DATA INTEGRITY
7• 439
T06
TXREADY ANO RXOONE INTERRUPTS
8• 564
SECTION NUMSER 03
8• 5&4
T~7
tD 8US DATA LINES DATA INTEGRITY
' · bbl
T:.118
v eus SELF TEST
PROGRAM
~---~ 1
....l;..;;llJ~·.....7.,;,.7.,;,.7_ ___, s,. ,.E"""C"""T....1...,o....
N_~;,,..;U:;.;M.-.8~E;..,.R~llJ..,;4__,,...,l
- - - - - - - - - - - - - - - - LISTI NG
UJ. 777
TllJ9
COt.ISOLE CLOCI' CONTROL
INDEX
11• 901
T0A
CONSOLE IO CYCLE FUNCTION
12• 975
T~8
CONSL FROM IO REG CL~ CTRL & DATA INTEG
11·1~7~
SECTION NUM~ER 05
ll•107A
T~C
CONSOLE MAINTENANCE RETURN
14•1162
T~D
RXCS REGISTER FRO~ THE ID BUS SIDE
15•t282
SECTION NUMBER 0&
15•1282
T0F.
TXC5 REGISTER ON THE ID BUS
15•1367
SECTION ~UMBER 07
1&•1394
T0F
ID BUS REGISTER ADDRESS INTEGRITY
16•150q
~ECTNO NUMBER 08
17•1535
Tl~
Cl8 l~ITIALIZE FUNCTION
17•1&56
SECT?ON NUMBER 0Q
18•16~7
Tll
CONSOLE REGISTER OUAL ADDRESSING
1Q•t745
Tl2
wcs DATA REGISTER READ
20•1771
T\3
INITIALIZE TME CONTROL STORE
21•1817
SECTION NUMBER ~A
21•1817
T14
WCS ADDRESS REGISTER DATA INTEGRilV
22•1Q0b
Tt5
WCS ADDRESS REGISTER COUNT LOGIC
23•1916
Tt&
MICPO STACK OATA INTEGRITY
24•2061
SECTION NUMBER 08
24•2061
T11
MICRO STACK OUAL AO~RESSING
25•215A
Tt8
MAINTENANCE RETURN DATA INTEGRITY
26•2327
SECTION NUMBER 0C
26•2327
T19
MAINTENANCE PfTURN MICRO STACK f~CA!Mlllf
27•2372
TtA
MICRO STACK WRITE DISABLE
28•2424
TlB
WCS PARITY GF.NERATOR
2Q•253~
TtC
CS BUS DATA INTEGRITY
30•2&21
SECTION NUMBER 0D
30•2621
TlD
PCS PARITY CHEC~ERS
31•2748
TlE
-cs DUAL ADOR~SSING
31•2807
SECTION NUMA.ER 0E
32•2845
TlF
WCS OVNAMIC MEMORY TEST
33•295Q
T20
ueEN FIELD DECODE
34•3060
SECTION NUMBER 0F
34•3060
T2t
USUB FIELD "CALL FUNCTION•
35•3168
T22
USUB FIELD "RETURN"
3&•3229
SECTION NUMBER 10
3b•322Q
T23
USUB FIELD "SELECT SPECIFIER"
37•3365
T24
UJM~ FIELD DATA INTEGRITY
TK-0770

Figure 4-10

Listing Indexing Example
4-33

4.9.2
Hardcore Loop and Single Step Setup
During microdiagnostic execution the error message shown in Figure
4-11 is displayed on the console terminal. Since the error PC is a
six-digit number (000670), it is an octal address and indicates a
hardcore test. Referencing TEST: lC in the hardcore Table of
Contents indicates that the test begins on line 2530. Referencing
the error PC of 000670 in the program code shows the PC to be at
an IFERROR statement on line 2554.
The function of the IFERROR statement (Paragraph 4.4.2) is to
produce an error report if a failure is encountered in the test.
Usually the IFERROR statement is preceded by a check or compare
function (in this case TSTVB). Basically this test is comparing V
Bus signals. In this example, the received data did not match the
expected data; consequently, an error was detected.
Since the hardcore tests execute out of the LSI-11, a scope loop
may be too slow to be of practical use. An alternative is to use
the set step instruction and loop commands of the microdiagnostic
monitor. As indicated in Figure 4-11, the operator sets the single
instruction and loop flags. In this case the loop range is between
the statement following the previous ERLOOP statement (line 2551)
_and the IF ERROR statement ( 1 ine 2554) • As shown in Figure 4-11,
each time the operator types SPACE, the current PC is displayed.
At TPC = 000662 the operator reaches sync point SYNC4C, at which
time the operator could scope the CS Bus data bits in an attempt
to detect the failing bit.
(At this point in the test the
microword has just been fetched from WCS and is driving the CS
Bus.)
The operator can exit from the step mode by typing any character
except SPACE. In the example, Control C has been typed and control
returned to the microdiagnostic monitor command mode.
4.9.3
Microtest Scope Loop Setup
During microdiagnostic execution the error message shown in Figure
4-12 is sent to the console terminal. Note that execution stopped
on test section 3A.
Since the error PC is a four-digit number (101E), it is a
hexadecimal address and indicates a microtest. Using the test
section number of 3A, and referencing the Table of Contents for
that section, test AS starts on line 1832. A look at the PC column
(of the microtest listing) shows that the error PC is on 1 ine
1906.
By scanning back through the microcode, select a sync point, in
this case SYNClA on line 1901. Control is returned to the
microdiagnostic monitor via Control C. The operator enters a CLEAR
SOMM: <1153> command. This command will clear the stop on
micromatch bit, and produce a sync pulse when the UPC equals the
content of the microbreak register (i.e., 1153). The operator then
enters a loop command. This sequence causes the test to beg in
looping and produce a sync pulse each time the UPC = 1153.
4-34

MICRO DIAGNOSTIC HARDCORE TEST
TA~LE OF CONTENTS

>>>TEST
MICRO DinGNOSTIC

v.05

NO. O~ WCS MODULES = 0001
04•05,06,Q7,0i·0910A•OB•OC

1010

28• 4 II

SECTION NUMBER 00
TIO
PCS PARITY CHECKERS
TlE
wCS DUAL ADDRESSING
SECTTON NUM~ER 0E
TlF
WCS DYNAMIC ME~ORY TEST
T20
UBEN FtELO DECODE
SECTION NUM8EA 0F
T21
USUB FIELO •tALL FUNCTION•
T22
USUB FIELD •RETURN•
SECTION NUMBER 10
T23
USUB FIELD •sELECT SPECJ'JER•
T2a
UJ~P FIELD DATA INTEGRITY

a. su

q. bbl
1e. 111
U• 777

0002
TRACE: 000700, 000720
FAILING MODULES: C.S. BUS

ll• CJ01
12· CJ75
13•1071'1
t3·1071l
14• 11 flii?
15·1282
15•1282

MIC>SET STEP INST)
MIC>!:Q£!')
TPC = 000646

(~BAR)

TPC = 000654

(SPACE SAR)

TPC = 000662

t5•13t-T

ANY CHAR. TO RESUME
FULL SPEED.

TEST
NUMBER
INDEX

CONTROL-Cl 0 Hc'rURN TO MONITOR

MiC>

OPE8ATOR
INPUT
UNDERLINED

1h 13CJ11
1hl50CJ
17•1535
17• lbl56
18•lf>77
t'i•t745
2B•l771
21•1817
21•1817
22•1CJ06
23•1CJ7b
24•20111
24•2061
25•215R
211•2327
211•2327
27•2372

PAGE#

MtCAO DIAGNQSTIC HARDCORE TEST
T1C
CS·BUS DATA INTEGRITY

30-2&21
3i'-21121
31·21118
31·2807
32•2845
33•ii?Q5CJ
34•30110
31i•33f>111
35•3lb8
36·322Q
36•3229
]Te33b5

8· 5bll

1011
OOOA

tc -

5
5
5
5
5
II

ii?• 42
3. 141
II• 2011
4· 2011
5. 2811
II· 3511
7. 439

SUBTEST: 1

TEST: 1C

~ACRO ~lP

C~PCA ANO tMPCAM MODE DEFINITIONS
SWITCH REGISTER BIT DEFINITIONS
CONSOLE ADAPTER REGISTER DEFINITIONS
ID aus REGISTER DEFINITIONS
MODULE AND AUS NAME ASSIGNMENTS
SECTION NUMBER 01
T01
CONSOLE AOAPTER REGISTER RESPONSE
T02
CONSOLE •To to• REGISTER DATA INTEGRITY
~fCTION NUMBER 02
T03
CONSOLE •McR• REGISTER DATA INTEGRITY
T04
CONSOLE •toes• REGISTER DATA INTEGRITY
T0~
CONSOLE R-D~E AND TXROV REG DATA INT!G~lTY
T0f>
TXAEADY AND RXDONE INTERRUPTS
SECTION NUMBER 03
T07
TD BUS DATA LYNES DATA INTEGRITY
T08
v eus SELF TEST
SECTION NUMBER 011
T0Q
CONSOLE CLOCK CONTROL
T0A
CONSOLE ID CYCLE FUNCTION
Tl'!~
CONSL FROM ID REG CLK CTRL & DATA INTEG
SECTJON NU~SER 05
T0C
CONSOLE MAINTENANCE RETURN
T~O
RXCS REGISTER FROM TME ID aus SIDE
SECTION NUMBER 06
T0E
TXCS REGISTER ON TME IO BUS
SECTION ~UMBER 07
T0F
ID BUS REGISTER ADDRESS INTEGRITY
~ECTNO NUl"BER 08
TlP
CIB INITIALIZE FUNCTION
SECTION NUMBER ~Q
Tll
CONSOLE REGISTER DUAL ADDRESSING
Tl2
WCS OAT& REGISTER READ
T\3
INITIALIZE TME CONTROL STORE
SECTION NUMBER 0A
Tlll
WCS ADDRESS REGISTER DATA INTEGRITY
TIS
wcs ADDRESS REGISTER COUNT lOGtC
Tl6
MICRO STACK DATA INTEGRITY
SECTION NUMBER 08
Tl1
MICRO STACK OUAL ADDRESSING
Tl8
MAJNTENANCE RETURN OATA INTEGRITY
SECTION NUMBER 0C
Tl CJ
MAINTENANCE PETURN ~!CAO STACK fNCR[Mlf.J~
TlA
MICRO STACK WRITE DISABLE
T B
W PAA T
N AATOR

l•
1·
l•
l•
l•
l•

01.0~.03,

ERROR: 000670

HARDCORE PROGRAM LISTING

LISTING TABLE OF CONTENTS

CONSOLE TERMINAL OUTPUT

.SBTTL

TlC

MACRO Mll!l
CS BUS DATA INTEGRITY

''********************************************************************
t+•

sTEST

CS BUS DATA INTEGRITY

TEST DESCAUtTION

·---·----·-·

TMrS TEST CHECKS THE DATA INTEGRITY O' TME CS BUS BY 'LOATING
A O.,E ~ND A ZERO TMRU A MICRO WO-AD, E"XECUTnn: TR! M!CRD'
-woRl'D, ANO CHECKI"G THE v BUS FOR PARITY !UOA_s. .
SUBTST .l • FLOAT A ZERO TMRU TME CS BUS
SUBTST l • FLO•T A ONE fMllU TM!

-----------

TM!S TEST CHECKS TME ID eus INT!RFAC! TO TH! wcs MODULES, TM!
DATA INTEGRITY OF TME WCS ME'IDRV CHIPS AND TR£ Ifill fWT[l:R?TV v-TME CONTROL STO~E CCS) eus.

ERROR DESCRIPTION
DATAI EXPECTEO V BUS CMANNEL 1 BIT ANO VALUE
RECEIVEO V BUS CM&NNEL 1 BIT ANO VALUE
LOOP COUNT • INDICATES WMICM BIT IN fi;j£ n BIT li'R'OUP n IIND[A
TEST, Io!o l•BIT e, 2•8IT 11 3•8IT 2 1 ETC.
LOOP COUNT • IND IC AT!$ iilMICM- !2 8fT---P-IWPU~r-- - - - TEST, T.£ 0 t• BITSCllll'l>, 2•8ITSC63132>, l•8ITScCJ5164>

TEST
STARTING
LINE
'NUMBER

NOTEa THE ~XPECTEO ANO RECEIVED V BUS CHANNEL INDICATES WHICH 32 BIT
GROUP MAS l!lD PARITY IN n, r.t. UZlf•e·1ncn1n>, l0lUBJTScU132>, AND lHlC!!BIT~c!.'5~~!•_ - - - - - - ___
SYNC POINT DESCRIPTION
SUBTST l • SYNC4C••TEST PATTERN rs ACTIVE ON THE es B~S
SU~TST 2 • SYNC40••TEST PATTERN IS ACTIVE ON TM! cs ~us
·- -

,..

A0A55111
25311 1'!00551'
2535
253b 0005511
01'lei556
2'537
2538
253Q
2541!1
25111 00056111
2'542 0111"570
2'543 011l1115711
25114 1'!00f>l!'f>
2545 1111111111114
254f>
2547 1'!001!1120
2548 0011lb3111
2549 tll!llllf>]
5111 fl0Pf>44
'51

''********************************************************************
TICI
...... - - - - - - - - - - - - - - - YNITTALJZE
SUBTEST
11111111111111111111111111111111111111111111111111111/111111//}ll/lllllf/lll1

TIC St I

-----------

••t #?AST Fl.DAT A ZERO TMRl.1 THE CS BUS

LOOlll
J,l,3
LDIDREG USCAOR,TMPll'IA
LOOP
K,t,3
LntOREG USCOAT,TMPl1!'2
ENDLOOP K

LOOP COUNT FOR .TJ.fE :r B.U.llfS
SELECT LOCATION ZERO
IN!TfALtiE. TME-COlllTENTS O' LOCATION 8
LOOP caut>.1T ·1a11 tHl -nrrn1r1n11r-·
J LOAD THE BA~K ADDRESS
,-"CfijfJi'Tf"""fME TEST PATTERN
LOAD ·rNTO TH! JE(UT!O ~itlle
EXECUTE THE MICRO ~ORD

H~b46

2552 1'100654
ERROR
LOOP
RANGE

SYNC POINT

CHECK THAT THERE WAI NO PARITY ERROR

ERROR
---~~~~~~~~-pc

cs~u-.---

r LOGIC DESCRIPTION

~~~~~~~~~-~~~~~~~~~~~~~~~-~~--~~~-~~~~~~~~~~~-~--~-~l...-!:-!-!!-=-~~~~~~~~~1.:;.ii1~~1..1&.1i.&:~

INDEX

90~112

CSEAR1

REPORT

CCSBUS>

CONTINUE WITH TijE NEXT BIT
CONTINUE WITH THE N!XT BANK
r CS BUS BITCS) STUCK

SUBTEST

90~122

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

1'!1'!1'!122

T1CS21

Figure 4-11

Loop and Single
Example

4-35

MICROTEST PROGRAM LISTING

TABLE OF CONTENTS

CONSOLE TERMINAL OUTPUT

DWM00AoMCPt4t0,l262)
DWM00l 0 MIC[4101J262)

>>>TEST
MIC~O DIAGNOSTIC
V,05
01.02.03,
NO. OF WCS MODULES ~ 0001
04.05.-06.o7.0B.09.0A.OB.oc.0D.OE10F.10.11.12.13,14,15,16.17.
18. 19· lA· lB .1c. 1 [1, lE' lF. 20. 21. 22. ~ 24. 25t26. 27. 28. 29· 2A' 2B, 2c. 2D • 2E'

12115

21•APll•1917

1832 SECTION 3A
TEST A5

ERROR: 101E'

' 1814

1U5

DATA:

--~~~~~~~-LINE

MIC>CLR SOMM: 1153

• CH!CK THE DATA PATTE~NS THaT REQUIRE THE ALU TO
BE EXECUTING AN l+B TO GET THE CORRECT ALU DATA1
IUBTST 2 • CHECK THE DlTl PATTERNS THAT REQUIRE THE ALU TO
81 EXECUTING AN l•I TO GET THE CORRECT -LU DATA,
S~ITIT J ~ CHECK TH! DATA PATTERNS THAT REQUIRE THE ALU TO
8! EXECUTING lNYTM!N BUT AN A+B OR l•8 1

1846

1841
1848

NUMBER

1849

LOGIC DESCRIPTION
THIS TEST CHECKS TH! LOClC NETWORK ON THE CEH MODULE THAT G!N!RAT!
THE ALU N BIT, AND TH! MULTlPLEXOll ON THE ICL MODULE THAT F!EDS
THE ALU N BIT IN TH! CES REGISTER,

1850

(IF SYNC WANTED

1851
1852

AT THAT ADDRESS)

185)

START SCOPE LOOP

1854
1855

CONTROL-C TO STOP LOOP

!RROP DESCRIPTION
DATAI EXPECTED CES REGISTER
RECtIVID C!S ~!GlSTER
LOOP COUNT • INDICATES WHICH DATA PATTERN IS BEING USED,
(I!! THE DAT• AT THE !ND or THE TEST)

1856
1851

MIC>£!!.!~- RETURN TO CONSOLE
>>>

SUBTST

1845
~~~~--~

1851

4 - - CONSOLE PROMPT

1859
UH
1861

OPERATOR
INPUT
UNDERLINED

u 1"!141 Pet1.e019,0Dw0.09r1,0ee0.10r1
u uu, 0e1e,0eJ&,6580,01aP,eee0,101e
u 111Jl 8, ~e00.001D,01a0.0100.e0ee.1tJ5
u 1019, 0e1a,ee11,1510,eA11,0eee,1140
u 1140• 001~.0011.1te0.0At0.00e0.11•1
u 1141. P&1e,001a,41a0,e1ee,e0e0,11•2
u 1142• 0100.001c.~1•0·e•00.~00e.114J
u 110. 0001,0e1c,01a0,0Ata,000e,11••

1862
180
1864
' 1865
1866
186'
1868

1112

t 814

18'5
18'78
1880

~e1s,0011,D5a0,09te,eeee,101A

00ee,1eJD,0180,e10e,eeee,112•
0000.0eJc,~1•0.0Ae0,0200.1t45

NEWTSTC.Jl
11(9J-!Ct,UJ
C•1'L 1 J/UNJAM
R 1lJ-!t C,29J
Rr2J-H, JeJ
D.K [ • 8111]
D.D 0 LEFT2

,.I DO THOS!

r11111111111111111111111111111111111111111111111111111111111111111111111

1881
1882

TBSll

•0

000e,ae1c,0110.ca00,e000,1t46
t

S898
1899

ERROR
INDEX

ru~CTIONS

REQUIRING TH! ALU TO DO AN A PLUS B

RCteCJ-Kt,6l
8U8TEST
ICLTILl IVA.R lel
DflYTEJ.CACllE 0 p
llUl-D
188'7
VA..R U l
IHI
D[BYTEJ.CACH!,P
1119
RCt5J.D
1899
VA.R t2J
1891
DIWORDJ ..CACH!,P
1192
D.D 1llXT tWOflDJ
189)
llCtHl.D
89
•
DLOOP
D

--~~~~~~~~~~~~~~pc

G!N!RaT! MASK rOR N BIT
savE

u11_0

llll

1196
189'7

LOOP
RANGE

lDD11Ess OF AMX DATA
Cl.EAR ANT SBI INT!~RUPTS
ADDRESS or BMX DlTl
ADDRESS or EXP!CT!D ALU " BIT

1884
1815
1816

0e01,0eJc,0180.01A1.00~0.11•'

Pe00,0e1c,011P,0A0e,0200,11•a
0e00,a01c,01e0,c100,0e00,114t

ICLTl 1

18'1

18'79

•e

u
u
u

,..
,.......................................................................

18'1!1

l 8'76
I 18'7'7

u
u
u

SYNC POINT DESCRIPTION
IUBTST 1 • IYMCll••lLU N BIT GETS LOADED
IUITST 2 • SYIC1B••ALU N BIT GETS LOADED
IUITST J • SYNClC••ALU N BIT GETS LOADED

1869

CEI REGIITE~ aLU N BIT

T"'IS BIT•

l844
TEST
STARTING

00000003

UH
18)9

1141
1142
180

00000000

'l'EIT DEICJtIPTION
THia TIST CHICK• TH! lLU N IIT JN THI CEI llEGIITI~. THla I I DONE
BY SELECTING THI ·~u TO DO A+B AND A•B, lND ,.B, WITH IPEC?,lC
DATA PATT!RNI ON THE lMX lND BMX TO CHECK TME LOG?C THAT GENERATE$

1840

00000200

MIC>LOOP}

++
TEIT

lll'J

TEST
NUMBER
INDEX

TEST: A5

••9•

PlGE
CES ~EGllTE~ ALU N BIT•
"T!ST A5
'1i»l ,.......................................................................
,1113
.

2F,30,31,32,33,34,35,36,J7,J8•39,~

FAILING SECTION

MICllO l1C24l)
Mleroeo•• !11•
T!IT 15 C!I ,EG?IT!, lLU N BIT

tun 20•APh19''J

1t00
l 01
1902
190J
1994

C fl!

D.NOT,D
D.D,AND,ll[J]
ID[CEll.DrD.RCt0!]
LAl!l.,rt[5J
LC.ltC[5J
Q..ID tCEll
Q.Q,AND,llUJ
lLU.Q•D,CLl( 1 UBCC

;
~~~~~~~~~~~~~~~~~~~~~~~~~~..,i~~~;.L-..;;~..f...;~~~~~~u..!i!.5!,!!.E..1~~:..._.....Ll-A.1~90E,~..:JK.-~~.£1:~~..U::Jo..i..llLlll..i.-.L-~~~~

SET TH! LOP COUNT

FETCH AMX DAU
UV!
r!TCH BMX DAU
UV!
FETCH EXPECTED N BIT DlTl
SAVE
G!N!RAT! INITIAL VALUE or N BI~
MASIC
INIT TH! CES REGISTER
LATCH lMX AND BMX DATA
EX!CUT! THE TEST
MASIC
CHICK
ALU N BIT FAILED IN CES llEG

r INCREMENT lDR or lMX DATA

1908
1919

lNCllEl«ENT ADR or BMX DATA

19te

TK-0775

Figure 4-12

Microtest Scope Loop Example
4-36

As shown in Figure 4-12, the operator has entered a Control c
followed by a RETURN (RET) command. This sequence breaks the test
loop and returns control to the console program.
4.9.4
Microtest Single Bus Step Setup
During microdiagnostic execution the error message shown in Figure
4-13 is printed on the console terminal. As in the previous
example, execution stopped on test section 3A.

As in Paragraph 4.9.3, the error PC is a four-digit number
indicating a microtest. A look at the section 3A listing indicates
that the error PC is on line 1948. At this point it is decided to
use the single bus step capability.
A scan backward through the microcode indicates a possible loop
between SYNClB (line 1943) and ERLOOP (line 1936). A point in the
loop is chosen to stop the microtest, in this case UPC 116C (line
1940). The operator enters SET SOMM: 116C, which sets the stop on
micromatch bit and loads 116C into the microbreak register. A loop
command is then entered which initiates execution of the loop.
When the loop reaches UPC 116C, the microtest halts and prints the
UPC on the console terminal.
At this point, the operator enters the bus cycle mode (set step
bus command) • Each time the operator types SPACE, a single bus
cycle is executed and the- UPC is displayed on the console
terminal. At any point in the loop the operator may scope the
current conditions.
As shown in Figure 4-13, the operator has exited from step mode by
typing any character other than SPACE. The program control flags
previously set are cleared. The HI flag is set to restore the
normal default case. A CLEAR SOMM is then performed to clear the
stop on micromatch bit and the microbreak register, then a
CONTINUE is performed to begin normal test execution at the next
sequential test (i.e., A6). If the operator feels that the problem
has been cleared, it is probably more practical to start the tests
over rather than to begin at the next test.

4-37

MICROTEST PROGRAM LISTI NG

TEST HEADER AREA

CONSOLE TERMINAL OUTPUT

1832 SECTION 3A
TEST A5

>>>IEST

u 114(:, 01~2.•e1c,011e,0100,111eee,114D
U 114D, tll'l1,1e1c,A1ee,etre,e0ee,1e1c
u u1c. Aeee,001D,0110,e100.111000,1erD
U UtO, 0110,0011,~1e0,0•11,001e,114E
u 114!1 0101.0021,0110,0••0,eiee0.11•P'
u 1!4P', e11c,201•,0110,eA11,e0ee,1159

TEST~ SUBTEST• 2

u 11501 0a1e,0011,1110,1D10,e~e0,11s1

TEST
NUMBER
INDEX

DATA:

u 1151. 000e,001c,e110,eA21,0ee0,11s2
u 11521 000e.001c,0110,e•21,00ee,1ts1
u 1153, ee1e,e014,e110,ea00,ee10,11s4
u 11541 eeee.ee1c,11r0.2c~0.00ee,1ts6
u 1156, 001c,0e14,11ce,e111,ee1e,11sT
u t 15?, 0e10,2011,0111,110e,001e,11s1
u 1151, ee10,111c,e11e,e1ee,ee11,111E
u uu. ee11,2010,0110,0•ra,10ee.1119
u un·, 0111,001c,011e,1Ae~,,,,,,1159
u 1159, Ae11,0014,0s10,0Aee,e0ee.11sA
u 115A, eeee,0e1c,0110,1Ae1,101e,11s1
•e11,e014,esee,e111,e0ee,11sc
u
u 11~. eeee,011c,e11e,0A1e,e01e,11sD
u 1uo, e011,ee14,e990,0Ate,eeee,11sE
u 115!, 0111,ee11,011e,et6e,e010,11sr
u t15P', 011t,1e00,esee,e•r0,0010,1160
u 11u, eeee,e11c,e1ae,0100,eee0,1e2e
u uu, 0100,e11c,0110,010e,0000,101B

u••·

MIC>SET SOMM: 116C
MtC>LOOP
MICROBR.EAK MATCH UPC= 116C
MIC>SET STEP BUS
UPC= 116D

(SPACE BAR)

UPC=116E

(SPACE BAR)

UPC= 116F

(SPACE BAA)

UPC=1170

X +--ANY KEY LEAVES STEP MODE

tc -

u 11u, eei11e, 001c, 01u,Hu,uee.11•1

U 11H, eeee,tt1c,011e,c1ee,1111e1,11•c

MICRO DIAGNOSTIC V.05
01.02.03,
NO, OF WCS MODULES
0001
04,os,06.07.os.09,oA.os.oc.on.oE.oF.10.11.12.13,14,15,16•17•
1s.19,1A.1s.1c.1n.1E.1F.20.21.22.23,24,2s.26.27.2s.29,2A.2a.2c.2n.2E.
2F,30,31,32,33,34,35,36,37,39,39,3A,

ERROR: 1026

U UH, ee11,e01c,01a0,0tA1,e0ee,11tA

•t---~~~~~~~~~-{OPERATOR
INPUT

SIU
1894

1895
1896

1197
1891

119'
1•00

1911

1•n

19U
1984
1915
1906

1901
1901
1919

••

EltltOR21ltC[IDJ.Q
LA8-R[81

LU.,R[lJ
1tr1J..LA+1Ct,1J

1•12

•Ill

1924
1925

1926

MIC>SET FLAG HALTI

RESTORE NORMAL FLAGS

1927

MtC>CLR SOMM)

CONTINUE TESTING

1921

MIC>CONT)

FULL SPEED, NEXT TEST

1929
l9Jfl
19)1

t9J:Z

19J4

LATCH lMX AND 8MX DATA
EXECUTE THE TEST
Mlllt
CK!CIC
ALU N BIT FU LED IN CU 1'!G

INClt!lil!NT lDR or EXPECTED DATA
CK!CK THE LOOP COUNT

JIICLTIL1

CONTilllU!

111111111111111111111111111111111111111111111111111111111111111111111111

TIS21

S!T THE LOOP COUNT

RC(0CJ.J[o2l

SUITIH
ICLTIL21YA..RIPJ
OCBYT!J.CACH! 0 p
R(5].D
VA-Rtl J
OCITTEJ.ClCH! 0 P

•0

!tC (!5).D

VA-PUJ

D[WORD].CACHE,P
D-D,SXTtWORDl

F!TCH AMX DATA
SAVI
F!TCH BMX DATA
SAVf:
FETCH EXPECTED N BIT DATA
I IAVE

..RC.!Hl-D

GENERATE INITIAL VlLU! or N BIT
MASJ
MICROMATCH

INIT TH! CES REGISTER

u
u
u

UBCC1BYT1:

ERROR-~~~~~~~--l1---~~~~~~~~~~~~~~~~~--t..J"'iiU~i"fi~"ifi~~;ifi':~~~ifl~i':j~f;;----!-t9'1t-ii"~~--:iU'i!iii:ii~iiiI:C~~~
U
Elt~OR2,RCCIDJ.Q

--~~~~~~~~~~~~~PC

GUERlTE INITIAL VALUE or Nan
MASK
INIT TH! CES REGIST!R

It t 2J.Ll+l<C, 2J
D.RC CICJ
RC[0CJ-D•Kt,1J,CLK,UBCC,8YTE

1915

aAVE

lNCP!lilENT ADR or BMX DATA

LAl.IH2J

191)
I 1914

FETCH !IP!CT!D N IIT DlTl

INCltEMINT ADR or llMX DATA

It CfH.Ll+IC I. t l

1911

1916
1917
1918

SAVE
I

••t NOW CHECK THOSE PATTERNS REQUIRING THE ALU TO DO AN A MINUS B
1922 ••
192]

THESE 2 STEPS

LOOP
RANGE

RC [5J.D
Yl-U2J
D(WORDJ.ClCHE 0 P
D..D 0 SIT [WOltDJ
RC(HJ-D
EltLOOP
D.RC [fl!]
D.MOT 0 D
D.D 0 lND,1ttJJ
IDCCllJ.D,D.RCtl!J
LAB.Rt5J
LC.RCUJ
1YNCU1 lLU.LA+LC1CLIC 0 UBCC1IYTE
Q,.ID[CEaJ
Q..Q 0 lND 0 1t UJ
lLU..Q•D1CLK,UICC

1•1•

1919
1920
1921

UNDERLINED

CONTROL -C TO GET COMMAND MODE

~>CLR FLAG ALL~

1119
1891
1191
1192

LATCH l~X AND BMX DATA
!X!CUT! THE TEST
NAIK
CHECK
ALU N BI.T FAILED JN CE5 REG

INDEX
TK-0776

Figure 4-13

Microtest Single

Bus Example

4-38

CHAPTER 5
MACRODIAGNOSTIC PROGRAM DESCRIPTIONS
5.1
DEFINITION OF TERMS
Module -- The diagnostic programs are written in a modular format.
Each module (file) is a part of the program assembled separately.
Modular programming allows the development of large programs in
which separate parts share data and routines.
Assembler -- The MARS assembler (which runs on a PDP-11) and the
VAX-11 Macro assembler (which runs on a VAX-11) are programs that
accept one or more source modules written in MACRO assembly
language and produce relocatable object modules and symbol tables.
Linker -- The VAX/VMS linker and the cross linker accept as input
one or more native code object modules produced by the assembler.
Linking consists of three basic operations.
1.

Allocation of virtual memory addresses

Resolution
symbols)

Initialization of the contents of a memory image.

intermodule

symbolic

references

(global

Program Defined Symbols -- Program defined symbols (and labels)
are either internal or external (global) to a source program
module. An internal symbol definition (and reference) is 1 imi ted
to the module in which it appears. Internal symbols used by the
diagnostics are temporary definitions that are resolved by the
assembler.
A global symbol can be defined in one source program module and
referenced by another. Global symbols are preserved in the object
module and are not resolved until the object modules are linked
into an executable program by the linker.
Program Sections -- The assembler creates a number of program
sections (.PSECT) within a module, according to directives by the
program developer. In addition, any code that precedes the first
defined program section is placed in the BLANK program section by
the assembler.
Through program sectioning the program developer controls the
virtual memory allocation of a program. Any program attributes
established by the program section directive are passed on to the
linker. Thus program sections can be declared as read-only,
non-executable, etc. Refer to the VAX-11 MACRO Language Reference
Manual for an explanation of the various program section attribute
functions.
In the diagnostic programs, each test is given a separate program
section.

5-1

5.2

OVERVIEW OF THE MACRODIAGNOSTIC PROGRAM

The macrodiagnostic programs and the diagnostic supervisor are
written in VAX-11 native code. Each of the programs (and the
supervisor) consists of modules. These modules are separate files,
which are assembled separately and then linked by the linker
program. Each module contains one or more program sections. The
program sections and routines are organized according to a common
format and a set of conventions that enable them to interact with
the supervisor. Note that the listings described in this chapter
are those assembled by the MARS assembler and linked by the cross
linker in compatibility mode. The format will change when the
native assembler and linker are used.

5.3

MACRODIAGNOSTIC PROGRAM LISTING DESCRIPTION

This section describes the program listings in general terms.
Illustrations and examples are taken from the MBA RH780 diagnostic
program. The formats of the other listings are similar.
Each program listing begins with user information and a link map
created by the linker program. The separate modules that make up
the program constitute the rest of the listing. The first module,
c a 11 e d the he ad e r , de f i n e s s ym b o 1 s and 1 ab e 1 s and p r o v id e s
routines that are called by other modules. The modules which
follow contain the test routines.
User Information -- The user information, which comes
beginning of the listing, includes the following items.

the

Program identification
Copyright statement
Program abstract
Hardware and software requirements
Prerequisites to running the program
Load and start instructions
Program description
History of program maintenance
Link Map -- The link map shows the virtual memory allocation of
the total program image in the program section allocation
synopsis. Figure 5-1 shows. this synopsis for the MBA diagnostic
listing.
The program section allocation synopsis lists the program sections
according to the order in which they appear in memory. A list of
attributes and the base, end, and length are given for each
program section. The base address is the virtual address of the
first location in each program section assigned at link time. This
number must be added to the relative addresses given in the module
listings to determine the virtual
addresses of specific
instructions because the assembly addresses are all relative to
the base of the program section.

5-2

VIRTUAL MEMORY ALLOCATION OF JMAGf "ESCAA,~XErl"
THIS ALLOCATION ~AS DONE O~ 20•SEP·7~
AT 12143 0Y CROSS LIN~E~ VEPSlON X4.6

. V I~TUAL Mf "'10RV

lii.-1 (.1 ,102 l.., p

LI~ITSI

STACK SIZE COEC, PAGESls
VJPTUAL DISK BLOCK LIMITS COCTALll
lDENTIF IC AT ION I
lhNAMIC MEMORY

AVAILA~LE'

CBVTESlt

~~VIV'~.4 ~~

~@0132

0VlrH 32

V1ti'00!111

5,3
42752
21-1648

DYNAMIC ~EMORY USE'~ CSYTES)t
LARGEST FREE HOLf. SIZEr
NUMBER OF HOLES F~EEI
.47 HOLES OF 4
11 HOLES OF 8
4 HOLE:S OF 12
5 HOLES OF 16

V!rll~f'BSFF

?12'4e.
k1!i'v 1 1q

BYTES
BYTES

BYTES
BYTE'S

MOLES OF 20 BYTES
5 HOLES OF 24 BYTES
1 HOLES OF 32 l;VTES
1 HOLES OF 1 8 vi 13YifS
NUMBER OF P•SECTS DEFINED:
NU~BER OF GL08AL SVM80LS:
4

~1nv.~1.1

~·' r~s 1 !:1:

PROGRAt-1 SECTION ALLOCATIOt-i SYNOPSIS I
NAME
CSABSS> I
CSt-!EAOER>:
csTSTCNT> I
c. ABS ,>1
c. BLANK ,>:
CARGLIST> I
CBUFFERS>1
CCLEANUP>:
<DISPATCl-I> I
CDISPATCl-4..,.X>:
<HEADER...,COOE>:
<ItHTIALIZE>:
<SUMMARY>t
CTf ST ... 001 >'
CT EST ... 002.>'
CTEST ... Ql~3> I
CTfST ... 0~">1
CTEST..,.005>:
CTEST...,00b>s
CTEST.,007>:
CTEST.,008>!1
<Tl:.ST .,0Qlq> I
CT EST .,010> i
CTfST.011>1

CTEST.012>1
CTfST ... 013>:
CTf.ST..,,014>1
CTEST.,,,015>1
CTt.ST .._016)1:
<TE.ST ,,.011>:

ATTRIWTES

ENO

~ASE

L.ENGTH

~~OP IC,

us~,

LCL I ~·JOSHR I

e·n,

WRT

lfl00~P.10~0

P.P-liH11011J00 000000Hl

USR,

CON,
COt..i,

APS,

NOP IC,
NOP IC,
NOP IC,
i..iOPIC,
N('IPTC,
NOP IC,

Pl= I.,

1 NQWRT

000PIV!200

00000281 000flll/!082

.IJ$R,

OVR,

PF.l,

LCL,t-..OSHR 1 NOExf 1
LCL,NOSHR 1 N0E)(f,

IJSR,

co~,

ABS,

LCL,~OSHQ,~QExf,NORD

USR,
IJSR,

CON,
CON,

l<fL,
QEL.

~JS~ I

co~~,

RE:L,

LCL,NOSiHR, Ell E'
LCL,NOSHR, EH:,
LCL, ·~OSl-IR, t-:OE:XF,
l CL, t..:OSH~,
fxr:,

~1 0PIC,

NOP IC,

NnPrc,

f\J(IPIC,
NOP IC,
~OPIC,

IC 1

!JSR,

c o~·J,

I.JSR,

CON,
C Q~• I

us~,

USR,

USP,

usq,

tJSP,
l!SR I

COt.J,
cm.;,

CO"i,

"~ L'
QH,
Pf:'.L,

;./FL,
Pl= LI
RF.L,

QH I

NOP IC,
NOPtC,

USF,

C O~>J,
CON,
CON,
CON,

~JOPIC,

us~.

co~~.

&:.;

Nf:'.'PIC,

co~;,

µ r L,

~JQF>IC,

USR,
USR,

NOP IC,

CO",

>( ~ L '

USR,

~H)P!C,

tlSR,

COM,
C O~J,

NOPICr

USP,
USR,

~JQP

NOP IC,

NOP JC,
NOP IC,
!\l('IP!C,
NOP JC,
"-iOP JC 1
!-..if'IPIC,
·~oPJC,

us~.

"·"t L,

.:. I=. L,
t..l~L,

E1. ,

LCL,NOSHR,
LCL,NOSHR,
L CL, ~JOSHR,

F ltf ,
F.: )( f. ,

L Cl. , ~.1 0 S !-! P ,
LC L, cJOS HR,
I CL, 1·i0SH~,

E JI. E.'
F.H,
Elef,

EXE I

LCL 1 ~JOSHR,

Ex E,

l CL, ~HJSHP.,

LCL, IJQSl-IR,

F. )( E ,
P'f.,

c o~i,

:;;.-EL,
RFI,
DfL,

I Cl 1 NOSHQ,

Eli:E,

LCL 1 NOSHR,

E )( E,

CON,

1-'tl.r

uso,

CON,
CON,

~-:LI

EH,
E • F.,

USR,

CO~i,

R i:.:L'
:;;- r: I. '

l CL, ,'·JDS HI=! 1
LCL,t•OSHQ,
LCL,NOSl-IR,
LCLr''OSHR,

:;)EL.

LCL 1 N05~~,

USR,
!!SR,
•.is~,

us~.

cor11,

co~,

co•.;,

1 l'llOlllRT

RD , ~RT
RO , NO~RT

RD ,
RI)

0etQ!lll00N11 0A0P!el000 P00P.0000
9'000'11288 00001AB8 00001831
tl!~L'lf211ABC

0\1!0~1Eb3

000003A8

lliRT 00f})020~Q.I 000025FF 000(ll060e
iii RT 0!000260" ~1"1""0266F 000!00070

~D , NOwRT
L CL , t-• 0 SH R, N 0 E li E ,
l.Ct, tJ0$HR, ~·Of XE, ··RD , ~!QiailH
RO , NOi-;RT
LCL, ~·iOSHR,
E 1tf,
LCL,MOSHR 1 EXE, ~D
WJH
I.. Cl , f,i 0 S HP ,
RD , WRT
Ex f.,
!(O , N(iWRT
LC'L,~;OSHR,
E: H:,

t L•

i.!~

RO , NOWIH 00000281.1 0A000287 000H004

EXF,

f. -X-E,
F: XE•

00~et2f> 7121 0001i1284F 00111001Ee
00002850 00'1102867 000210018
00002A0G!J 000P12E3A 00000438
,
00"02E3C 000030'H 00000256
000030q4 00003090 111000000A
~0~0321i10 00003355 00000156
RD , NOlllRT i2JQl~031J0"1 ~'"'03698 0000029C
RO , ~-0"-'RT ~0012138C'IL'I 000P3987 00~00188
;.(I) , t..:owR T ~0Pl03ArlJ0 0~00a1s2 00000753
PD , ~lOl\'RT 1"0!1' 01.1200! 000Clt42A7 0001l100A8
RD , ~JOwRT 0N~~/J4010 000045E1 00PIC1101U
RO 1 NOwRT ~C'I010460Pl ~0004773 ·0"0el0174
~D , NOiaiRT 000048"'0 0000SlFC 000009FO
~I)
,NOWRT ~P"'052~1ll ~et005A07 00000808

, ~.JQWRT

V'l00~5Clill"'
'110~Cllfi(i'l0~

k!Ql0~5E0B
Clle'~0o7CJO

0(.ll~H!1~2QIC

RD , •.iOill~H
RD , "'0WRT
RO , ~·01t1RT
"D , t-.;Q~RT

~0~0b800

00~0oA59

0000025A

;110P!li'!bC~r.

,M011.'l~i

~?0!07800

RI)

, t-.1QwRT

00~07C00

~!')

,1~0!"RT

00~0Q00"1

0(ll00oF2F 00000330
00007615 00000616
00007A2E 0000022F
00008FFC 000e l 3FO
0(llOll'jq 158 0000015q

QI'

~001il70~0

0000079E

TK·1118

Figure 5-1 Portion of the
Program Section Synopsis,
RH780 (MBA) Diagnostic Program

5-3

The link map also lists the global symbols and their assigned
values. Note that symbols used as labels point to routines in the
diagnostic supervisor, if their values are over 10000.
Figure 5-2 shows a portion of the global symbol table for the
absolute program section in the header file of the MBA diagnostic
program.
The link map is a part of the listing created by the linker, but
not a part of the actual program in memory. It always precedes the
first file in the macrodiagnostic program listings.
Header Module
Like all of the modules in the
header module begins with a Table of Contents,
Statement, and a Revision History.

program, the
a Copyright

The declarations section in the header module contains global
symbol definitions for register bit names, data pat terns, masks
referenced by the program, and Macro definitions. This section
constitutes the beginning of the program code. The own storage
section in the header module contains program labeled data, such
as drive addresses, and program text and format statements,
containing the ASCII texts of error and status messages.
The header module also contains code that generates the hardware
and software parameter tables, report and print routines,
initialization and clean up routines, and interrupt and exception
service routines.
The assembler prints a symbol table and a program section synopsis
for the entire module following the last program section in the
module.
Test Modules -- The remaining modules in the program contain the
tests, which are the main body of the program. Each module begins
wi th a Ta b 1 e o f Co n t e n ts , Co p yr i g ht St a t em en t , and Pr o g r am
Maintenance
History.
The program code begins with macro
definitions. A symbol table and program section synopsis are
provided by the assembler following the last program section for
each test module. Notice that each test beg ins a new program
section.

5-4

ALIGNMENT
c,

ABS

RYTE

,>1

ENO

BASF

LENGTH

0
GL08AL SVMROLS DEFTNE~:·

SEN\/

et~00~0Ql1

$MO

000~0~"111

A55A

9'00~A55A

AASS

~NllQIAASS

Al)APTf P..,.COOE

0PQl~l'}.02~

ALL...,ONES

000il'lFFFF'

ASP._OFFSET

ALL

~~~-'Plil41 b

ATTENTION

000 Ul00P.

ATT"'
8l I< S Nl"'.a.C ()MD
8R2

0'rn~001

0~H'101f1012

ATA
BCR
f3R0
8R3

000Pl0001
00008000
00000010
00000010

8f:(5
BVTEllJ
PVTE3

~0Ql0Ql~15

8~6

00000013
00000016

0t""4~v1~t,FF

BVTEt

0000FFH

FFl?l!iHH"f{let

@VTE .... COUNT,..MSI<

00~~L.-'V108

0000,FFF

(PF

CSP

~0l/10c;\Ql0Qt

DAT A... XFER..,ABIH

00001000

DEFAULT

oocc

0000000(11

BLl<SCSBI

0tt!A0001C

A~t

0~0PJ0011
~00'11'11~14

BQq

BR7
8YTE2

(21~00001'7

0QIFF0~00

CAR
000~0P'1C
CRTED 4 REAO.._OATA 20000000
OATA 4 XFER..,OONE 0P002000

DISABLE.a.LOG
OPE
ORIVE...,OFFSET
ORV ... INHMASK

DTE

00V4P~H3i;,0

['1"'11')

0~1210\~~(.ll 1

~P.!0A0010

l)P~

00017''1!1 ~~

00089189
00000014

0e000080
0"'001180

DRIVE ... SEL ... ~S!<

Ql~liH"E'1'0QI
~00~~0801

ORV .. ERIHUSI<
OS ... MSI<

0000EH0

l')RY

f)TJ.Al30RT
Er.:il
fRR,..CQNF
FA TL

0~PIC~Cll0£i'2

OT.BUSY

800el'1J000

00004000

0"'0"F00F
C1J00002FF

FORCE 4 ME~fRJ(

0~000004

DA u ... xFER.,.LATf

P'fA.0008Vl0

HPSB 4 BR
HPSB.,TR
HPSQ ... DEVICE'
IM•PP

1 ~Q!~tlll?.091

l00Ql0000

0~0~1000

OVA
ERR
F00F

0FFFF8FF

ENA8LE 4 PS

00000800

00'1!0P0"1A

EXT .. REG .. OFFSET

~0000lU10

FERR

00000004

HPU.._OEVICE

00000018

HPSB ... SLAVE
HPSL.._VECTOR

00000023
0000001C
00000001
0000001,
20000000

00!1'.'!fl:~i~1 A.

HPU ... CHANNE:L

C\0000013
0~Ql0il!O! 14

"'Vl0A002t

.-.i:>~.R..._DRIVE

~'""'17"0Vl?2

Ql000002~

00~~,Cil~24

Ql~0~0000

HP'J.>L ... URVEC
HPH ... '-'EVICE

00000010

I~RCP

"''Hrn0C'.l l E

0~~v000e

ILF

IMBOP

INTER~UPT..,~NBLE

000~0~0/J

INV RT ... M"..a.CPAR
IPLR
MANUAL
MAP 4 0FFSET
MASS.._CNTRL ... PE
MASS ... ECP
MASS.RUN

40!000000

JNT ..,SEQ..._ TIMEOUT VI fl! I~~ OI ~IJ C4 2
I~VRT ... MF; ... DP~R
e00v1000~
LC'~~ tTS.._t.1SK

0V.'(-10V' 1

IO.,..PAGE
MAINT_.,MOOE

20000000

Ql00~0Ql12

"'000000!2

"'iAP .•).,.PATTRN

e()lt~FFFF

MAP.INVALID

00lel00010

&ll~012!'11800

~AP.a.?E"

0Q!frll20ia00

~·Ass

0001FE00
0000Hl40
00100000

. 0"'000080
0£11080000

INVRT .. MAP .. PAR

QIQl~ll'rn~

MAP..,PTP..,MSI<

MASS .... DATA ... PE

MASS,...lttCLI(

A"'f' l l'1V1"''11
@0~2~0£110
AfilfiHl000't1

MASS_...FATL
"90IB... SEL

... cTOD

~~ASS ...

EXCP

MBE

0!0(110!0~03

:4f'.E.ASR

ltHiHH~N~t ~

hlM .. CR 1

M8E..,CR2
MBE ... ER
MSE ... S~
r--OL

0~0~001U

M~E.._01:u~

eH~Hrn ~ ~ 1 c

~0~"0iG1f.l.18

~Bf .1.MR

0~~~PIC:'0C

0:t!A~VJ004

MCLI<

0(.)l.0e~(}l~2

M8E ... OTR
MBE.. PARAM
-.itSSEO..,.XFER

0~"101 Pl0QI

~SR

~Q!01.f!~?.18

MULT.._TX

~EXUS..,OFFSET

t'l~PIQl2000

~'!PBLE"0

0""~''rn~Qlf:"

NJ8BLE1

NI88LE2

~P10Ql0F"'0

~I~~LE3

0et'~F~Hrn

~IBBLEIJ

NIF\RLE5

~~F'00~00

r.. I~l3Lfb

0F'40~~·HH''

NIBBLE7

NON..,XIST ... DRIVE

0,·,040~00

l\J('(')P

0~CH;''Vl'1!~
0ff'IM!2~01!1

NO.RESP ..,CONF

PF .A.hfl')TH

PAGE ... BYTE ... MSK

Ql~0~0015

PGM...,INIT

1:10,,.f.R.,.DOwN

"wer0YJ"'0

POWER..,UP

occ

PF ... FIELD

PIP

~"90Ql0"91 q

~"'0~000Q
0011rn2~ffilOI

OPT

Figure 5-2 Portion of the
Global Symbol Table for the
Absolute PSECT of the Loader
File of the RH780 (MBA)
Diagnostic Program

5-5

00000008

00800000

00000000
00000018
0!0!000087

00000100
rtl80C'l0000

000000F0
ee0F0000
F0000000
4Ql000000

000001FF
00000001
00400000

5.4
DIAGNOSTIC PROGRAM AND SUPERVISOR INTERACTION
Whether a diagnostic program is executed in the user mode or in
the standalone mode, its relation to the diagnostic supervisor is
basically that shown in Figure 5-3. Once a diagnostic program has
been loaded and the diagnostic supervisor has been loaded and
started, program control moves to the boot routine of the
supervisor. This routine clears vector space, flags, mail boxes,
and sets up the processor registers to a known state. The boot
routine checks to determine whether the operator has typed a
Control C and sets up a map of memory and I/O addresses creating
P0 and Pl page tables. It then initializes the system control
block and the process control block, and then calls the beg in
routine.
The begin routine changes the processor mode to kernel and calls
the CL! (the command flag should be set). The CLI types out the
prompt symbol, DS>, indicating that the supervisor is ready for
commands. When the operator types in a command (e.g. START), a
parser routine in the supervisor is activated to decode the
command and call the requisite action routines, clear the command
flag, and then call the dispatch routine.
The dispatch routine forms the heart of the supervisor. It begins
by clearing the error count and setting the pass zero flag and
then calls the initialization routine in the diagnostic program to
be executed •
The initialization routine initializes the unit under test and
sets up conditions in the CPU and on the SB! which are necessary
to the diagnostic program. The initialization routine then
questions the operator concerning the unit to be tested, creates a
hardware parameter table (P Table), tests for end of pass, and
returns control to the dispatch routine in the supervisor.
The dispatch routine then calls the first test. At the end of each
test, control returns to the dispatch routine. At the end of the
last test in the program (or the last test selected by the
operator), the dispatch routine in the supervisor calls the
initialization routine in the diagnostic program. This routine
determines whether or not the end of the current pass has been
reached. If the end of the current pass has not been reached, the
first test routine in the dispatch section of the supervisor is
called, beg inning another test sequence. If the end of the pass
has been reached, the program calls the end of pass routine in the
supervisor.
The end of pass routine in the supervisor determines whether or
not the last pass to be run has been completed. If so, the cleanup
and summary routines in the diagnostic program are called, the CL!
command mode is set, and control passes to the begin routine which
calls the CL!. The CL! prints out the OS> prompt symbol and waits
for operator input.

5-6

DIAGNOSTIC
SUPERVISOR

DIAGNOSTIC

DIAGNOSTIC
PROGRAM

DIAGNOSTIC

PROGRAM

SUPERVIS08

START

BOOTSTRAP
AND SUPER
INIT ROUTINE

CALL SERVICE
ROUTINES

FIRST
TEST

RETURN FROM
SERVICE
ROUTINES

BEGIN
ROUTINE

CALL SERVICE
ROUTINES

TESTN

RETURN FROM
SERVICE
ROUTINES

COMMAND LINE
INTERPRETER
ROUTINE
(CLI)

CLEAN UP

ROUTINE
------SUMMARY
ROUTINE

f'PR0CiRAMiNiTR00r1N'E -

I
I

lnisPA'Tc1i- -

I ROUTINE

FIRST TEST
ROUTINE

BUILD p
TABLES.
INITIALIZE
DEVICE TO BE
TESTED

MODE

11
11
IL-I

YES

- sE-T CoMMAND-

CONTINUE
WITH
INTERRUPTED
TEST ROUTINE

-1
I

NEXT PASS

GO TO BEGIN
ROUTINE TO
INITIALIZE
SYSTEM

I
I

CALL CU

I
I

SERVICE
ROUTINES
(PRINT. ETC.)

_ _ _ _ _ _ _J

--,

YES

NO RETURN TO TEST

I
TK-0607

Figure 5-3 Diagnostic Program
and Diagnostic Supervisor
Interaction

If the last pass has not been completed, the end of pass routine
checks to see whether the operator has typed control C. If the
Control C flag is set, control returns to the CL!. Otherwise, the
end of pass routine calls the begin routine in the supervisor to
initialize the system and initiate the next pass of the diagnostic
program.
Note that when the operator types Control C, he does not cause an
interrupt routine to be called. The Control C merely sets a flag.
The status of the flag is checked periodically when the tests in
the diagnostic program call various service routines and at the
end of a pass.
5.5

ANALYSIS OF A SAMPLE TEST: RH780 (MBA) TEST 3, SUBTEST 1

5.5.1
Listing Column Format Description
Figure 5-4 shows the program listing for the MBA RH780 diagnostic
program (ESCAA), test 3, subtest 1. The sixth column from the left
contains the relative address of each instruction. These numbers
begin at 0 with the beginning of each program section. Note that
the address offset of the program section containing Test 3
(3600 ) , found in the link map, must be added to the relative
addre~~ to find the virtual memory address of the instruction.
The seventh column from the left contains the listing line
numbers. These numbers begin at 0 for each module of the program.
Note that the line number increments for each line of the source
module. The sixth column shows the program counter, containing the
relative address. The relative address increases according to the
amount of memory space required for the instructions and operands.
Line numbers are present only for lines entered by the program
developer. Macro expansions do not have line numbers.
The eighth column from the left
programmer as symbolic addresses.

contains

labels

used

the

The ninth column from the left contains instruction mnemonics and
Macro calls. Note that the Macro calls themselves require no
memory space (the relative address does not change), and that in
the Macro ex pans ion which fol lows, the 1 ine number is not
incremented (line 317). At assembly time, the assembler program
responds to the Macro calls, expanding the Macro according to the
definition listed at the beginning of the file.
Column ten contains operands for those instructions contained in
column nine; and it contains instruction mnemonics and parameters
for the Macro expansions.
The eleventh column from the left contains operands from the Macro
expansions.
Column five contains the op codes
contained in columns seven and eight.

5-8

(hex)

for

the

instructions

.....

RM78111 ... TESTS
TEST 21

INtTIALIZATtON TEST
l-12'1C
Ml!IC
UllC

284 SSBTTL

ll!lllfllA11!01Ht
001C

1111,uc
0DllC
11101C

0111ei01H'l111111

n1c

01111110

rlH"2fll
flill2111

11111122
"'11122
1111122
Ol\1122

vi11122
'11"22
>1P22
~:~22

'-111122
'1111!22
llllll22
1•11122

·1110111111111111111111'EF
0'1I010QlllllllP'EF
llllll0'1IOICHH•'F.F

!'Ill

l"Ol22

rl'llllllCllllllllllllll'EF

{'IE

:•Cll211
'•0!211
'40!111

~01!!

~Oll1'CllOll!IOllll'EF

""'""

Wllllo

IA~(jfl

••lll110
~' Ol 11 fl

llllil?IClllll0ll!Ol'EF
t'fllOIDIOl00IPl'81'

~Olllfl

"'P51

Gii!'

c~
IJA

::1!000"C2

Oii

lllll!Oll'l"C2

1"
54

1119151'
.-111111
Oltllfl8

{'14

~106&

G1100lfQlellilGll"EF

~0flC

~QIVIPACllG'!Ol'EF

DF
00

;i11172

•n

OIDl5&

"'lll!!C

~0AlllOllllQllll'E'

011

~Dl811!

CT Al'

:it0R'7
Qlfll87

OPERAND
SPECIFIER
EXTENSION

21111
211'5 '
2110 '
211'7 t TEST
21111 ,
21111
31110!
3'111

OPERAND

SPE<jlFIER

~--

wRITE ONE'S INTO !ACM BIT, CLEAR VIA THE O•INPUTS
WRITE EACH BIT IN TH! CONTROL REGISTER
REPORT [RADA II' SELECT!D BIT ti NOT SET

MOVL
RH:cuR:ADR,R2
' MOVE RM'7110 ADDRESS TO R2
ERAPREP AMCR~MSG,1,l'MT:coNTRL.REG,SAlll ... ~SG
' PREPARE TO HANDLE ERROR
MOVAL
RHCR~MSG,REG 4 NAME
MOVZBL #t,REG:No
MOVAL
l'MT ...CONTRL ... REG,REG ... STRING

Jll'o

31'1'7 r++
TEST CLEARING VIA D•INPUTS
]All :••
31fll
S8GNSU8
SI ti

JOI!.' :

l lllS I

llOIRil

!NIT
WRITE ONE'S VIA D INPUTS TO CONTROL REGIST
CLEAR VIA D !~PUTS
READ Gll'S ,ROM CONTROL REGISTER
SKIP I' NO ERRORS
t CLEAR EXPECTED RESULTS REGIIT!A
#l1LUN,MIR,PAJNT ... SBE
lilifijf ...H!
MIR
LUN
•t
#SIM, ••DSS!RRHARO
t SCOPE LOOP?
tH, HOHCKLOOll

CALLG

SSS, •#OSl!NDSU"

J12
311

3111

11'5
JU
311

Jl~

2G11St

u:u ... u

~08F

I
LISTING
LINE
NUMBER
(DECIMAL)

ALG~RITM"'I

302 '

"'"8'

TEST ARGUMENT TABLE TERMINATOR •

1'111 ,

3C"ll
3P1'5

PROGRAM
COUNTER
(HEX)

' ENTRY MASK

THIS TEST CHECKS l'OR STUCK AT ZERO BITS IN THE AMTBI CONTROL REGISTER
A CM!CK IS ALSO MADE TO INSURE THAT TH! REGISTER WILL CLEAR VIA
THE O•INPUTS 01' ~HE CONTROL REGISTER l'LIP/l'LOPS 0

;i~1r

INST
OPCODE
(HEX)

OPERAND
SPECIFIER

•fllc>

2CJ'11

P~8F

Ill

WORD

28'7 r++
2M t
28• r TEST OESCRIPTIONt

illi!'T8

• LONG
0

2111

'.•~22

CDEl'AULT,ALL>

TFST .. l!lll!Jii

292
24'3

>'11122

211• Sl.IGNT!ST
D&TA .. HJI

~11122

l'lll"22

cCONTROL REGISTER S&I T!ST>
.SBTT.L T!ST Ji CONTROL R!GIST!R S&I T!IT
ltSSBTTL
eeJ,cCoNTROL REGIST!R SAi T!ST>,clll&G!>
.PS!CT T!n.:ee·J, lllAG!, NOWAT

28'5 , [(J)J

vlll'22

CllOl22

(J)

PlllHAL
PUSHL
PUS ML
CALLI
SCl<LOOP t111S
CAL LG
tENDSU8.
I

INST
MNEMONICS
AND
MACROS

MACRO
EXPANSIONS
AND
OPERANDS

LABELS

OPERANDS
FROM MACRO
EXPANSIONS

COMMENTS

I
9

TK-0736

Figure 5-4 RH780 (MBA)
Diagnostic Program Test 3,
Subtest 1, Listing

5-9

Columns one through four contain the hexadecimal code for the
operands specified in columns ten and eleven. Columns two and four
contain operand specifiers. Columns one and three contain operand
specifier extensions. Numbers followed by an apostrophe (e.g.,
00000000 ') are the machine code for symbolic operands. They are
modified by the linker at ,link time.
(MARS is a one pass
assembler. Forward references, with the exception of branches
within P sections, and global symbols cannot be resolved until
link time.)
The twelfth column contains comments describing the functions of
the instructions. Each comment is preceded by a semicolon.
5.5.2
Analysis Of Typical Lines
Line 311 -- The BISL instruction sets bi ts in the destination
according to the mask provided. #PGM. INIT is the symbol for the
mask. Its value (00000001) can be found in the symbol table at the
end of the module. CR is the symbol for the relative address
(offset from the MBA base register) of the control register of the
MBA under test. Its value (00000004) is also listed in the symbol
table. This value is added to the contents of R2, the base address
of the MBA under test, to produce the physical address of the
control register. The instruction thus sets bit zero of the
control register. The comment, INIT, indicates the function that
setting bit zero performs.
Line 317 -- $ERRHARDS, in line 317, is a Macro call. The symbols
that f o 11 ow it are a rg um en ts to be used in the ca 11 • The five
lines that follow line 317 show the expansion of the Macro. These
i n st r u ct ions push the a r g um en ts on the stack and ca 11 the
DS$ERRHARD subroutine in the supervisor, which sets the error flag
and prints an error message based on the stored arguments.

5-10

5.6

RH780 {MBA) DIAGNOSTIC SAMPLE SUBTEST {Direct I/O)

5.6.1
RH780 Diagnostic Detailed Flow
Each test in a given diagnostic program relies on subroutines
provided by the diagnostic supervisor. The diagnostic program thus
depends on the supervisor for services as well as initialization
and test sequencing functions. The operator should be able to
follow references and subroutine calls back and forth between the
diagnostic program being run and the supervisor in order to use
the listings.
The general strategy used throughout the diagnostic programs
involves writing and then reading back data directly (with MOVE
instructions) in order to exercise the logic circuits or device
functions under test. Data retrieved is compared with data
expected. If the comparison indicates a failure, an error routine
takes appropriate action and sends a message to the operator.
Subroutine 1 of test 3 of the MBA diagnostic is representative of
this strategy. This subtest determines whether the control
register of the MBA under test can be cleared after each bit in
the register has been set.
When the diagnostic supervisor calls test 3 of the MBA diagnostic,
the test initialization code moves the base address of the MBA
under test to general register 2. This register is then used to
index specific MBA registers.
The ERRPREP Macro then stores
information concerning test 3 in a buffer area for use in error
messages.
Subtest 1 begins with a call to the DS$BGNSUB entry point in the
supervisor, as shown in Figure 5-5. In order to find this entry
point, look in the global symbol table in the program 1 ink map
(Figure 5-6). DS$BGNSUB equals 00010030, an address in the
supervisor. Note that the first two characters of the symbol (DS)
indicate that the symbol points into the diagnostic supervisor.
The global symbol table in the link map for the supervisor shows
that the entry module (ESSAAll) defines the symbol (contains the
cod e f o r the en t r y po i n t )
( Fi g u r e 5 - 7 ) • The n am e s o f t he
supervisor modules suggest their functions (e.g., entry, loop,
print) •
The DS$BGNSUB entry point contains only one instruction, a jump to
RBGNSUB, as shown in Figure 5-8. This subroutine is in the loop
module of the supervisor (Figure 5-9). RBGNSUB checks the subtest
sequence for correct order. A discrepancy causes the subroutine to
call a print routine, which displays an error message, and then to
return to the CLI. If the subtest sequence is correct, the RBGNSUB
subroutine calls the KB-CHECK routine to check for Control C. If
the opera tor has typed Control C, control returns to the CLI.
Otherwise, control returns to subtest 1 which, at this point,
begins testing the MBA logic.

5-11

DIAGNOSTIC
SUPERVISOR

ENTRY
MODULE

DISPATCH
ROUTINE

!
f°WsGNsUB- -

1ROUTINE

I
I

DS$CKLOOP

CALL BGNSUB

_ _ _ _ _ _ _JI

II
II

INITIALIZE
THE MBA

WRITE ONES
TO CONTROL
REGISTER (CR)

II
II

ENTRY
MODULEl

VI
I

ERROR
MODULE

CLEAR
CONTROL
REGISTER

DS$ERR
HARD

RERR HARD
SET ERROR FLAG
RING BELL
IF BELL FLAG
SET

STORE ERROR INFORMATION
CALL ERROR ROUTINE
YES

ENTRY
MODULE

DS$PRINTF

PRINT
MODULE

RPRINTF

PRINT
MODULE

RPRINTOUT
PRINT ERROR
MESSAGE

SAVE PC

TEST3
SUBROUTINE
LUN #
MIR MODULE

I
I

CALCULATE
LOOP ADDRESS

I
I

CALL CKLOOP

CLI

RETURN TO SUBTEST

I I
II
II

LOOP
MODULE

COMMAND
LINE
INTERPRETER

ENTRY
MODULE

SETUP
BASE ADDRESS
OF MBA
UNDER TEST

PRINT ERROR
MESSAGE.
CALL CLI

I
I

MBA RH780
DIAGNOSTIC PROGRAM

DIAGNOSTIC SUPERVISOR

ERROR
PREPARATION

1 PRINT
1 MODULE
~

CALL TEST

MBA RH780
DIAGNOSTIC PROGRAM

RETURN TO
BEGINNING OF
::ROUTIN::_

A
REND SUB
SUBROUTINE

II
II
II
II
I
II
:J I

CALL
DS$ENOSUB
TK-0506

Figure 5-5 RH780 (MBA)
Diagnostic Program Test 3,
Subtest 1, Flowchart

MJR ... P40P.~CP_.MSI 001cHllc;,bbE•R
MJR ... MSI.MCP.MDP r.~000704•R
MSI
"451..,MCP.a.MIR,,.~OP

000009A8•R
!iS!l'00fiUB.?•R

"4$ I ... MIR .a.MCP ..,MOP

~e!000A1C•l:i

N0..,U"'lTS
QST ... INIT1
REG...,NO

0t110ei02B3•Jt
Q!QlftJA195J•R
0.0000548•"

RH0

~'1100028D•R

R~l

Rl-l,,.ADQ.a. TA"LE

01i'.10002q9•R
0P.111002A5•R
M0U q 1 O•R
000A1942•R
0'110et0280•R

~H,,.TRLVL

~~0Cl!02AD•R

SFT.,P.,TABLE

0@0P1AB5•R

WAIT ... TI"1E

0~0t'!02EC•R

~Mb

RMCR..,MSG
RHMAPR..,MSG

TI ,..OUT .e:vr ... FLAG 000002E6•R
PAGE

cSTSTCNT>a

LONG

cUBSS>I

BYTE

cSHUDElbl

c.LAST>I

t•.YQ ... >-151
l"JR ... MSJ 4 ,...(IP

000t'1117tl!•R

MST ... ~CP

00((\liH.iASCJ•R

MSJ,,.MJR
~S~ 4 St.JAP

0Ql0i3~CJC3•R

MSI ... MIR .... MCP

9JEJ0ti'02Fltl•R
~~(iH.,~sae.R

Rf C4 MSG

NOOR IVE
PTBASE

00001BFt•R

REG..,NAME

REG,..STRING

0N'l"'lil5UC•R

REPORT...,SUFFER

R"' I
RHIJ
Rt-!7

000~CA2qt•R

0:;,00Ql29D•R

QH2
RH5

Q!~~~V'02A9•~

Ql-t~C~ ... MSG

Rl-!CSR 4 MSG
Rt-jSP 4 ~SG

0~1~W

NIJM9Ek'_.PUFFER

RM~P.RLVL
SA\~\. MSG

SUFFJx.&.PTR
TI MOUT .RET .PC

GLOBAL

SY~80L5

t Q 1 S•R

"1 JR..,.MS I ... MCP
000el0602•R
MIR..,MSI .. MDP .... MCP 012100077l•R
0PCirneA80•R
MS I..,MCP ..,MIR

000009EA•R
000~02E0•R

00000284•R
0001210544•R
00000340•R
00e00295•R

RHDR.&.MSG

0~Vl~~ 1924•R

fHt\I AR.,MSG

0001ril'!?AE•R

00lii1~18CE•R
000~0554•R

SA1...,114SG
TEll'IP

00~irH~2E7•P

UNEXPECTED

... CUR..,AOR

000002Al•R
00001q33•R
0000193B•R
0001i!1192B•R
00000288•R
~0001809•R

01(10e055C•R
0fi'l0018E4•R

DEFINE~•·

DSUBORT

DSUSKAOR

00Vll ~~q(il

osus·n~

DSUSKSTR

0@01NlA~

OSSCNTRLC
OSSELOGOt<J
OSSERROEll

OSl~REAI<

00010fi''S8

DSfCl<LOOP

0~010"'40

00010078

OSICVTREG

0121'11l0@80

'11'11010100

0~'1'1~010

0~0100C8

DS!ENOPASS
OSSERR ... ARD

00010000

OSUSl<DATA
OSSASKVLD

00010080
00010088
00010070
00010168

OSSCANWA IT
DSSCLRVEC
OSSELOGCIFF

0et010U8
0e01003e
00010008

OSSERRSYS
OSSGETMEM

0oi0100ce

DS,ESCAPE

00010~50!

"SSE NO SUB
OSSERRSOFT
OSSGETBUF

0'1010\30

OUGPldRO

001211~018

OSSINITSC8

00010170

OSSINLOOP

0~010048

OSI MMOFF

OSSMOVPMY

0001"! l 5l'

0fl010150

00"10148

DSSMOVVRT

00010ta~

OS$MM0N
OSSPARSE

OSSPRINTB
OSSPRINT>c
OS!SETIPL
OSSSMOCMAN

lil00100E0

DS!PRINTF
DBS fl e: L BIJF

P.0~1~rt11F0

OSSPRJNTS

DSSRELMEM
OSSSETVEC

OSSWAITUS

P.~0;~~6AR•R

SYSSSINTit-4
SYSSCLREF
SYS!GETCHN ·
SYSSQJOIM
SYSSSETIMA

SYSSWFLANO

ei~0l'10E8

000101qfill
0ftl!0100b8

SYSULLOC

0Qllil1'11128
00~1'1118~
0P!iH 0026
000!10238

0~01111258

SVS'-CANCEL

01(1'111026~

0Cil010l98

SVS~DALLOC

00010~C8
~"'010200

SYS$GETT I"'

(210010178

DS$SETMAP
DSJSUM'91ARV

0001Q!208

SYSSOASSGN

000102E0

0fi'l010378
0'1101030"'

SYSSQIO

0900103C8

SVSSSETEF

00010400
00010478

0fi'I~ 104 30

P112101'1'1.1~e

SYShlFLOR

01i'10 t 0aq(i'

cD JSPA.TCM.X> I

LONG

2 •

00010160
0001006111

00010250
00010268

00011U2'11

LONG

00010088
H0100F8
00010138

DSSWA ITMS
SYSUSSIGN
SVSSCOITIM

SYS!Rf A['lfF
SYSSSETPRT

<DISPATCH> I

00010120

sv·sswAITFR

TK-1120

Figure 5-6 DS$BGNSUB Listed
in the Symbol Table in the
ESCAA Link Map

5-13

Me~
ZZ•ESSU•G •~HI
DMA11r1a0,401ESSAA.EXEJ467

Syt180l

••••••

0USUCB2

DRASUC83
DS$U..,8PT 40DR
OSUBORT
DSU80RTWA lT
osuB ... BPTINST
DSl AQ,..SSENO
DSUQ .. SVSSRV
DSUSl(Af)R
DSUSKDAU
DSUSKLGCL
DShSl<STR
DSUSKVLO
osso . . . soFTPce

Ftche 1

DEFINED 13Y

VALUE

·····

'1!0~l84E8•R

00018588•R

0l'l012FD0•R
1'100 tet0Z0•R

P!Q!0 Ult.it70•R

0P.let t2FC0•P
~11101fll7FF•R
~M01020~•R
l'}l~cil 1 PJ0•0•R

00ftl10080•R
0PIQl10~H·R

0PIG'! 10U0•P
1'10fill 1Cll08eaA
f'HHH E10 0 • R

--·-·-···108ASE..,ESSU43
IOBASE..,ESSAA43
DEBUG..,ESSU8
ENTRY ... EU U t 1

nso

ENTRY ....
11
DEBUG ... ESSUS
EN TAY ... ESS U 11
ENTRY ... ESSAA 11
ENTRY .... ESSU 11
FNTRV..,ESSUl 1
ENUY ..,ESSU 11
ENTRY .... ESSAA 11
!NTRY ~e-ssu 11
1<ERNEL...,ESSAA15

S 8 f'.AK
OSICANWAIT
DUCHANt.1EL
05$Cl<LOOP
DSICLI
DSSCLRVEC

aR
0A0100 8•R
000U970•A

°'

Sequence 11
P4GE

REFERENCED BY •••

----·-------·-···
DE\I ICE..,ESSAA9
DEV I CE.ESSAA9
ERROR ... ESS.012
FRl(C TL..,ESO.U 1
PAR AM... ESSAA1 q
ERROP ... ESSO U
1<ERNEL..,ESSAA15
KERNEL,..ESSAA15

START....,ESSAA25
DEVICE 4 ESSOC1
ASS l GN.fSSU.36
CH"'1K.ESSAA4
IOPOST 4 ESSAA52

APT

Fl"eme L1

LINKER u1.20

30•AUG•1978 09131

LOOP
IOSRAM.a.ESSU4b
QIOREQ.a.ESSAA51

SCB.ESSU23
LODMAP..,ESSAA47
SCB..,ESSAA23

LOOP
MfMMGT._ESSAA18

ASTOEL. .. ESSAA t
OASSGN.ESSAA38

CA NCf l ... ESS AA37
DEVALC..,ESS AA40

LOAD 4 ESS--U l &

APT
CLOCK,..ESSAA6

~00U!t81'-1•R

"'001001.Ul•A
00A138B21•R
Qtl)IJH PJ t68•A

OE8UG ... ESSAA8
C~ANNEL ... ESSU3

SCB,..ESSAA23
DEVICE.a.ESSAAc;

UBAINT..,ESSAA55
MEMMGT ... ESSAA18

OEBUG....,ESSAAB

FLAGS....,ESS AA l ta

ERROR....,ESSAA 12

LOOP

ST ART ... ESSU25
0S$CNTRLC
DSSCVTREG

VHHi'1 ~078•R
0Aflt1008P•~

fNTRV .... ESSU 11
!NTRY ... ESSU 11

01SPAT..,ESSAA10

CHANNEL....,ESSUl
sce~ESSAAU

DS$00SUM"1ARV
DSIENOPASS
DS$ENosue
DSSENTAY
DUERROEV
DSIERRHARO
DS$ERRSOFT
DSSE~RSYS

OSSESCAPE
0SSGA._8REAKVt'.C
DSIGA..,BUFPTR
DSIGA._Cl"IKLPPC
DSIGA.CHMl<V!C
OS$GA,..LAST ADA
OSSGA ...LOOftADA
DS$GA,.P8ASE

OSIGA..,TBITY!C

osue.ennu,
DSHETAOD~!SS

DSIGETBUF

DSHETOATA
OsUETLOGtCAL
0SSGET8TRING
DSIG!TVI!LD
DSIGL.BU,CNT
DSIGL..,BUFL!~

00010J028•R
CllOJQI 1f11010•A

0P.81J5H•R

ENTRY ..,ESSU 11
ENTRY ... ES SAA 11
ENTRY ... ESSU 11
YER SI ON~ESSAA. 33
ENTRY .... ESSU 11
ENTRY .... ESS AA 11
E"'ITRY ..,ESSU 11
ENTRY ~ESSU t 1
ENTRY ..,ESSU 11
SCB .... ESSUZ3
l<!~N!L...,ESSA A 15
ICERNH ... ESSU 15
SCB ... ESSAA23
l<!RNEL.ESUA15
K!FH.lfl..,ESSAA 15
PAl'OM.&.ESSAA 19

H81358C•A

SCB~!SSU23

1?1001J1 "!l•A

KEFfNEL...,ESS.U 15
ENTRY 4 ESSU 11
ENTRY ... ESSU 11
ENTRY ....,ESSU 11
ENTRY .&.ESSAA1 t

~010038•FI

00016Ul•R
A~0100C8•A
0Aet100D~•A

OtitJ010008•R
P100100C0•R
000UJ050•R

r.it0013588•R
0Aet1Jt8C•R
0'HlJ13t•0•R
00013584•R
0"'QJ131H•R
000131 U•R

0e.101H•0•R

0011112el•R
0001 lfJ"80•R
0001H•8•R

000tleAl•R
008SHH•R
HISHll•R
009Ulll•R

!NTRY ~EUUt t
ENTRY ... Essu 11
IUfHR...,£SSU2
~!lltN!L.,USU 15

DI SPAT ..,ESSAAH-!
CHMl<.a.ESSAAta
fol£r.A14GT ..,ESS AA 18

LOOP
DEV I CE..,ESU A9

START ..,ESSU25

CONSOLE
PA~AM..,ESSOU

MEMMGT ..,ESSU 18
PAFUM..,Essu1c;
PARA.M..,ESSAA 19
PAIUM..,ESSA.A 1q
PARAM ... ESSAAU
KERNEL ... ESSAA 15
PARAM ...ESSUU

MEMMGT .ESSA.A 18
PRINT
TK-1121

Figure 5-7 DS$BGNSUB Listed
in the Symbol Table in the
Supervisor Link Map
5-14

ZZ•ESUA-4.eui

ENTRV..,.ESSAA11
"6 .. 08

!NTRV POINTS TO THE DIAGNOSTIC SUPERVISOR.
DIAGNOSTIC ANO STARLET SERVICE ENTRY VECTORS,
22•AUG•1978
ENTRY POINTS TO THE DIAGNOSTIC SUPERVISOR.

..., 4.2.l

n030
0930

;;-0 0
0!11 0
0A.3o.t
00~e~0091"EF

001210

~~030

.waRO

it.332

JMP

0038

?~38

N'3A

1@2

'HH10

183

~,~I.IQ.I

1A~

00~0

lr,0U~

Vl~Hl2

~74 l~48

\HHJ8
~Ql48

(1~~~P000•EF

00~0

<'~48

U~l.l.A

PP!5('!
';050
~H'JSO!
~~ ~V01001210 • EF

FFA3•

ltHHH'!(il0ft'~ • EF

0'""54

2Ql2

01.1

~050

2~3

~el5E

21i.1U

21215

1(1~6QI

2~6

~Qlb0
; 4 ?; 62

2~7

!!J07'11
r~~7QI

~l'lli'l00009! • EF

0000
17

~~70
~070

'1~72

""'-'78
21078

0000"
l'i10000002"EF

007~
Cl!~78
~07A

QUAO

IN LOOP ENTRY POitl!T •
ENTRY MASI<

iii~<>

RI NLOOP

ESCAP! ENTRY POINT.
ENTRY MASI<

BREAK FOR OVNA~IC SERVICES.
S~VE NO REGISTERS
CHECK l<EVBOARO

2~0

0111Sf

~07(11

RCKLOOP

QUAD

a06A

CHECI< L.OOP ENRTY POINT,
ENTRY MASI(

~M<>

.ALIGN

19Q

~F-158

QUAD

RE SCAPE

00~0

"'1~b8

ENTRY MASI<

RENOSUB

JfolP

OSSBREAK11
2QI 1
.WORD

0000

END SUBTEST ENT RV .POINT 1

,;;M<>

•Mc>

198

\:1068

BEGIN SUllTUT ENTfltV flOINT,
EN TAY MASI<

R8GNSU8

.wo~D

NJ58

'1Vl68

•

CONTROL SERVICES.

;;;M<>

QUAD

!'05?

9!068

Pao•

QUAD

1q4
.ALIGN
195 DSSESCAPE11

lequertce !19

~iCftt 3
VAX•11 MACRO Xl,J•6

193

1%
191

001?J0
i-~~0~"'01210! • EF

1Qf21 DS!INLOOP 11
1q1
.woRo
JMP
192

tH't5PI

'1"'513

Jto!P

•ALIGN
185 OSSCKLOOP:t
18&
.WORD
Jt-4P
187
1M
189
•All GN

'11000

0058

te0 t'ISSENOSUB11
• illlORO
181

0000

~\il40

l?IQ10Ql0000" EF

.AL

DSSBGNSUB11

~038

Q!r.Jl~~~t2J(llf'.l~"EF

PROGRAM

,,.Hit Jt

08122106

2Q!8
21719
21~

esew
RET

l<B .... CHECK

•ALIGN

QUAD

• l.IJORD
Jt-4P

a~Cllll>

.ALIGN

QUAD

DSSWAITMS11

211 DSSWAITLISI I

.woRo
212
J~P
213
214
215
•ALIGN
216 DSSCANWA I Tl I
217 OSSABORTWATTs I
.1110RD
218
J,..P
219
220
221

9 MC>

.AlIGt-4

WAIT MILLISECONDS ENTRY POINT.
ENTRY MASI<

OSXSWAITMS

WA?T MICROS!CONOS fNTRV POINT,
ENTRY MASI<

MC>

DS>CSWAJTUS
QUAD

CANCEL WAIT ENTRV POINT,
ENTRY MASI<

•tote>

DSX!CANWAIT
QUAD

222 OSSC:NTf:?LC11
.VECTOR OSXSCNT~LC
223
JMP
224
OSXSCNTRLC+2

ili)(10018

TK-1122

Figure 5-8

DS$BGNSUB

Entry Point

5-15

ZZ•ESSAA•4,~4

Mao

0MA11[340,40]ESSAA,EXEsU67

.......

VALLIE

SVf'180L

··---

DEFINED

00P.17170•R

LI Nl<ER

30•AUG•1978 09131

-········-

'f e~• 1

xru, 20

'~•••

•••u•"e•
11
PAI!
16

REFEPENC!O BY ,,,

·--·--·-·······--

rr.rnA!."'A004

LOOP

ENTRY ,...ESSAA 11

l<EFHiEL ... ESSAA 15

ON 0

Rffil?OEV
RERRHARO
RERRSOFT
REfHlSVS
RESCAF'E
RGETAOORfSS
RGETDATA

RGETLOGICAL
RGETSTRING

~~Cil1t.l~bF•R
l'A~~U85q•R

l·HHH aBa 3-R
r,~;it,~1 t.198~•R

~V11~152ac-P

r;HHH SSFE·R
&' '1 ~ 1 '5 4 7 C• R
it.FIHH .:;~A2•1?
~0~1'57H•R

ERROR 4 ESSU 12
ERROR.1.ESSAA 12
fRROR.1.ESSAA 12

ERROR.ESSAA1Z
LOOP
PARAM.1.ESSAA 1 q
PAFUM.ESSAA 1 q

PARAM,,_ESSAA19
PARAM"'"ESSAA1q

RGf.TVIE'LD

l"illi-' 1 '5544•R

RGPt-IAR"

'H.llV115888•R

RJtJLOOP
RPTEADR

0!ll01538C•~

LOOP

@'!!A17Cbl•~

Mf ~MGT ... ESS AA P3

RT'f PE"1SG

i;,11'1.1 t '5 OAb•R

PARA~"'"ESSAA19
PARA~.ESSAA19

QIO ESSAA22

N R ....

A11

ENTQY ,...ES SAA 11
ENTRY ,,_ES SAA 11
ENTRY ,.F-SSAA l 1

ENTRY ,,_ESSAA 11
ENTRY ,,_ESSAA 11
ENTRY .,..ESSAA 11
ENTRY .. ESS AA 11

ENTRY .... ESS U 11
ENTPY.,..ESS.U11
El'!TRY ,...ESSAA 11
F:NT~Y ,...ESSAA 1 t
QJOFl'>T "'ESSAA5P,

DISPAT..,ESSAA10

CLI.1o.ESSAA5
SCB.1o.ESSAA23

SURT .... ESSAA25

SC(j ... BASE
SCij .. I~AGE

M011E80~·R

1<ERNEL,...ESSAA15

sc~~Essun

"'0\ll l t,A0~·~

SCB.1o.E'SSAA23

l<ERNEL .... ESSAA 15

SChUSTOEL
5Ct1Sl'\IEWL Ill

0~~18QF'a-~

ASTOEL.,ESSAAJ
ASTOEL,...ESSAA 1

SCt-!SfilAST

~lA0t8AEA-R

ASTDEL,...tSSU 1

SEC ... TICK

r;t~.wc:'"""'""

CLOCK.ESSAA6
l<ERNEL.,..ESSAA 15
KERNEL .. E' SS AA 15

8Gt·J$C ... I RPC "'T

00018A13•R
~ '110! ~VI "14 ~

SGl>1$GL,,_! RPC i\: T
~~01C3E~•R
SGt~SGL .. ~tP AGi:D v N !iH~~1C3CC•R
SS$ .. ARORT
V''-'~i'i.1·112C

sss .. •ccvto

l<ERNEL.,.F:SSAA 15
SYS VECTOR

~~1:rn~~PC

SVSVECTOR

sss..,eADPARAM
SSS..,8R£AI<
sss .. euFRVTAU

WHWrnql.I

SVSVECTOR

SSS.,CANCEL

~~~0~~830

ssS,..CMODsuPR
S5$..,C""00USER
SSl..,COMPAT

Cll~HW0Q 14

SYSVECTOP

itWWJ~30C

SVSVECTOR
SYS VECTOR
SVSVECTOR
SVSVE'CTOR
SVSVECTOR

~.~0i:,04 t

V'l~~H191424
c;,t~~'~042C

sc~.._ESSAA23

CHf'IK,,_ESSAAtl
C:LOCK,...ESS06

I OPOS T..,ESSAASZ

!('ERNE'L..,ESSAA 15
~EMMGT.ESSAAte

MEMMGT ... ESSH18
""E"1MGT ,...ESSA A 1 e
TMORVR,.ESSU57
ACPFDT ,...ESSU35

DEBUG..,Essue

Q IOREQ.fSSU51

ACPFDT ... ESSA.A35
DE~UG .... ESSU8
D~D.RVP ... ESSAA53
C: ANCEL ... fSSAAH
OEBUG,...ESSAA8
OEEIUG,...ESS ue
OE!;UG,,_ESSAA8
DEAUG,,_ESS ue

SS$..,CONTINUE
sss,,,,coNTROLC

~~~~l'llHH

SYSV~CTOR

~~~h~VJo5 l

CONSOLE

SS$ ...CTRLERR

~'10~"'054

SVSVECTOR
SYSVf CTOR

09DRVR .... ESSAA39
TMDRVR..,ESSAA57

0 MD RV R...ES SAA 5 l

ORDRVR ... ESSAA54

SVSVECTOR

OBDRVA...,ESSU19

Clt-1DRVR ... ESS AA53

ORDRVR ... ESSAA54

DBORVR.ESSAA39
TMORVR ... ESSAA57

OMORVR.ESSAA53

DRDRVR 4 ESSAA5'1

ACPFDT..,fSSU35
T~DRVR ... ESSAA57

IOPOST ...ESSAA52

TMDRVR 4 fSSAA57

SS$,.OATAC...iEC:I(

TMf'H~VR.,..ES SAA 57

SVSVECTOR

sss.oEVNOTMOUNT

00~~~838
0~~~0~b4
0~~~P.~7C

SsS.DEVCFFLINE

~0~~~084

SYSVECTOR
SVSVECTOR

SSS.,OATAOVERUN
SSf .DEVFORE!GN
ss1 ... o~vERR

A~~0""0ec

SsS.ENOOFFJLE
sss.ENOOFT APE

00Wi1087~
~~~H.1!0878

SVSVECTOP
SY SVEC TOR

SVSVECTOR
SVSV~CTOR

TMC'>RVR ... ESSAA57
ACPFDT ..,ESS035

ACPFDT..,ESSAA35

QIOREQ ... ESSAA51

TK-1123

Figure 5-9 RBGNSUB Listed in
the Symbol Table in the
Diagnostic Supervisor Link Map

5-16

Subtest 1 initializes the MBA under test by writing a one to bit
zero of the control register, the initialization bit. The subtest
then writes ones to the control register, writes zeros, and then
reads the register. If zeros are not returned from the control
register, the subtest calls the DS$ERRHARD entry point in the
supervisor. The DS$ERRHARD code is in the supervisor entry module,
ESSAAll (see the supervisor link map). DS$ERRHARD causes a jump to
RERRHARD, which is located in the error module of the supervisor.
RERRHARD sets the error flag, rings the bell if the bell on error
flag is set, and calls the DS$PRINTF entry point. Like the other
DS$ entry points, this one is locate.a in the entry module and
contains only a jump instruction. The jump transfers control to
the RPRINTF routine in the print module (see the supervisor link
map). RPRINTF, in turn, calls the RPRINTOUT routine, also in the
print module. This routine prints out a message on the operator's
terminal indicating the test and subtest numbers, the logical unit
number (LUN) under test, and the failing module name (MIR).
RP.RINTOUT returns control to RPRINTF, which returns control to
RERRHARD, which returns control to ESCAA test 3, subtest 1.
At this point, the testing and error reporting portions of subtest
1 have been completed. The subtest then calls DS$CKLOOP (in the
control module of the supervisor). This entry point causes a jump
to the RCKLOOP subroutine, which is located in the loop module.
Unless the loop and error flags are both set, control returns to
the subtest, which in turn calls DS$ENDSUB in the supervisor to
terminate subtest 1 and start the next subtest.
If the loop and error flags are both set, the loop address is
calculated and the RCLKLOOP routine causes a jump back to the
beginning of subtest 1, at label 10$. Note that if the loop is the
first loop after the error call, the test and subtest numbers are
checked. If one of these numbers is wrong, control returns to the
subtest as if the loop flag were not set. After the first loop,
the subtest will be repeated continually.
5.6.2
RH780 Diagnostic Sample Error Message
The error messages generated by the RH780 diagnostic vary,
depending on the type of error detected and the type of the
failing test. However, in all cases the error message will
identify the failing module (or bus signal) and the nature of the
failure. Expected and received data are printed when meaningful.
For example, if bit 2 (IE) of the MBA control register is set, the
error message printed wi11 look like that shown in Figure 5-10.

5-17

********MAINDEC ZZ-ESCAA-5.0 RH780 DIAGNOSTIC-5.0********
PASS 1 TEST 3 SUBTEST 1 ERROR 1 l-JUN-1978 10:53:30.70
HARE ERROR WHILE TESTING MBA: FAILING MODULE: MIR(M8276}

(RHCR}=00000004
EXPECTED: ZERO
RECEIVED: IE
XOR:

IE
TK-0780

Figure 5-10

ESRCA Sample Error Listing

Use the test, subtest, and error number to look up the relevant
code in the program listing. Notice that test 3, subtest 1, error
1 is the portion of the program discussed in the previous
paragraph. The program sets the maintenance bit in the control
register. It then writes ones to the control register, clears the
register, and reads the register. Since bit 2 is stuck at one, the
received data and the expected data do not match.
After listing the failure, the program continues with the
succeeding tests. The operator may, at this point, shut down the
computer to change the MIR board as directed, or use the
diagnostic supervisor commands to set up a scope loop and monitor
the failure more closely.
5.7

RP0X/DCL REPAIR DIAGNOSTIC (DIRECT I/O), SAMPLE SUBTEST

5.7.1
Detailed Flow
The RP0X/DCL Repair Diagnostic (ESRCA) is representative of the
peripheral diagnostic programs that use direct I/O. Like the
cluster diagnostic programs, the RP0X/DCL repair diagnostic
accesses registers on the unit under test directly, with move and
bit set instructions and the 1 ike. However, the RP0X/DCL repair
diagnostic relies more heavily than the MBA diagnostic on services
provided by the diagnostic supervisor. In particular, it uses the
channel services of the supervisor to perform such functions as
initializing a channel, aborting a function, enabling and
disabling interrupts, setting map registers, defeating parity, and
determining adapter and error status.
For example, when the dispatch routine in the supervisor calls the
first test in the RP0X/DCL repair diagnostic, the test .routine
gets the address of the device under test and then, passing a list
of arguments, calls for channel services through the DS$CHANNEL
entry point in the supervisor.
Figure 5-11 shows the code for
test 1, subtest 0, errors 1-3. Figure 5-12 shows the subtest flow.
DS$CHANNEL calls DSX$CHANNEL, which in turn, calls the BLDCDB
subroutine, which builds a channel data block containing the
5-18

~<lFE

0000001110

OATA...,a01&

"'0H

TEST...,00111

Vil k'2

HHHH'9F
53

0~111Pl"CF

001ii0
00

01!100id000"EF
00
00

7F
DD
DD

1-1113

FB
00

VI 1Zli'

07
0000lill/J00'EF

DD
DO
DD

FED0 CF

011100 'CF
01

H0000H'ifF
H011JHH'9F
H0HIH''F

"°-

Vl
I

HHHH'U

Ii! 111

00000000"EF
01

9F 4F
0188

,DO
OF
DO
DD

FB
DD
FB
FA

\A 119

1:'11l3
0123
Vl1,2fi
tt12B

?'13A

110

MUt
1-11 '12

111

~142
~14'1

k.11"8
~14C

lH'iE
1114E
ii'l 55
~lSB

"1 b2

vllcA

'1lbD

C!C

~174

0fd

DO
OF
DD

Vl17S

~loO

~175

FEBF CF
0000'CF
02

1 lel8

10fi

1n20
LHH

1"'6 1011

taHlF

"l/J01/J~000'EF

0HHllUl'EF

IHU0HPl'·9F
IHl!ll!IHH'EF

~tfl2

k."n"
lill!Ofi

019000H'9F

118

11117F

11181

IH01HH'9F

""1

DO
FB

1:118E

FFU CF

~it

1'.119E
"119£

000U000"EF

0157

11 q

~1188

I~ 1q5

s TEST ARGUMENT UBL£ TERMINATOR

.wORD

.,MC>

s ENTRY MASI<

f GET DUVE'S ADDRHS
PUSMAQ CH ...STATUS
PUSHL
·~
PUSHL.
#CHCS...,INIU
Pl)SHL
DRIVE
CALLS
•4, •#DSSCHANNEL
MOVL
RPCS1(R2) 1 Rl
t GET CONTROL/STATUS
sos ... CHA~NEL ... s
DRIVE,#CHCS ...STATus,,CH...,STATUS
PUS HAQ CH ... STATUS
#Ill
PUSHL
PUSHL
#CHCs ...su TUS
PUSHL
DRIVE
#4, t#DSSCHANNEL
CAL.LS
f CHECK FOR CONTROL BUS
#tHSSV ... M8ACPE,tH ...sTATUS,20s
sac
MOVI.

~·BASE 4 AODRESS,R2

'********************************************************************
r CHECK ,OR NON•EXlSTe DRIVE
#CHSSV ... MBANEO,CH.,STATus,2ss

~· 77
1:117B
'1188

s PARITY ERROR
PUSHL
#0
PUS HAL. w•MsG ... MCPE
W.;;DRIVE
PUSHL
PUSHL
#SER
'"TEST 11 SUBTEST 0, ERROR l
USM, UOSIERRHARD
CALLS
PUSHL
O~IVE
# 11 UDSSSHOCHAN
CAl.L.S
us, UDSSCKl.OOP
CALL.G
EXIT TEST 1
BRW
TEST ... 001.,X

117 2121$1

id 1t!1

11000H0"9F

L0fliG

12~

121

BBC

,W 9 DRIVE,w 6 MSG ... NED
SDS ... ERRHARD ...S
#Id
PUSHI.
PUS HAL w•MsG ... NEO
9
PUSHL
111 DRIVE
PUSHL
UER
TEST 1, SUBTEST 11J, ERROR 2
#SS!'il, UOSSERRHARD
CALl.5
DRIVE
sos ... SHOCHAN..,S
PUSHI.
O~IVE
CAI.LS
1, UDSISHOCHAN
l0S
sus ... CKLOOP
lldS, •#DSSCKLOOP
CAI.LG
TEST
SDS..,EX IT
BRw
t 'EXIT T!ST 1
TEST.,001 4 X

TK-1124

Figure 5-11 ESRCA RP0X/DCL
Test 1, Subtest 0,
Program Listing

ESRCA
RPOYy'DCL REPAIR
TEST I, SUBTEST 0

DIAGNOSTIC SUPERVISOR
START

ENTRY MODULE

+
CHANNEL MODULE
~DC~OUTINE

GET ADDRESS

DISPATCH
ROUTINE

OF DRIVE

l l~S$ CHAN~ -1
~1---11

GET HARDWARE ......
P-TABLE

I
I
I

CALL
DS$CHANNEL
(INIT)

GET
UNIT#

UNDER TEST

I
I
I

BUILD CHANNEL
DATA BLOCK

INDICATE
SUCCESS

I.. __ __ JJ
r---

GET STATUS
OF DEVICE CHAN,
SYSTEM

IL------

SET MBA
INIT

I
I
I
I
I

TK-0747

Figure 5-12

ESRCA RP0X/DCL Repair Diagnostic Test 1, Subtest 0,
Flowchart (Sheet 1 of 2)

5-20

DIAGNOSTIC SUPERVISOR

ESRCA
RPOX/DCL REPAIR
TEST I, SUBTEST 0
READ RPCS1
OF DRIVE

CALL
DS$ CHANNEL
(STATUS)

DS$ERRHARD
(PRINT ERROR
TYPE)

DS$SHOCHAN
(SHOW MBA
REGISTERS)

DS$CKLOOP
(LOOP IF LOOP
FLAG SET)

AND SO ON

DISPATCH
ROUTINE
(CALL NEXT TEST)
TK-0748

Figure 5-12

ESRCA RP0X/DCL Repair Diagnostic Test 1, Subtest 0,
Flowchart (Sheet 2 of 2)

5-21

P-Tabl e address, and the adapter address; clears the flag word;
and determines whether the channel is an MBA or a UBA. When
control returns to the DSX$CHANNEL routine, the function argument
passed from the calling program (ESRCA) is evaluated, activating
one of several function subroutines. In this case, the INITA
subroutine sets the initialization bit in the MBA control
register.
Control then returns to the calling program (ESRCA), which reads
the RPCSl (control status) register of the unit under test with a
MOVE instruction (direct I/O). The test routine then calls
DS$CHANNEL again, this time passing a different function argument
(CHC$ STATUS). The DSX$CHANNEL routine is executed again,
activating the CHC$ STATUS subroutine which stores the unit and
adapter status in the location labeled CH STATUS.
Then when control returns from the DSX$CHANNEL routine to the test
routine, the data in location CH STATUS is compared, bit by bit,
with expected data patterns. If-an error is detected, the test
routine calls a series of supervisor routines (DS$ERRHARD,
DS$SHOCHAN,
DS$CKLOOP, and DISPATCH)
to print out error
information, loop if the loop flag is set, and return to the
dispatch routine if the loop flag is not set.
5.7.2
RP0X/DCL Repair Diagnostic Sample Error Message
Test 1, subtest 0, error 1 of the RP0X/DCL diagnostic identifies
control bus parity failures on the Massbus (Figure 5-11). When the
program detects this failure, the error message identifies the
failure by test, subtest, error, failing unit, and error type. In
addition, the message includes an MBA channel status dump, showing
the contents of the pertinent registers, as shown in Figure 5-13.
Bit 17 of the status
control parity error.

set,

indicating

the

Massbus

Other error message formats display expected and received data and
the contents of relevant registers in the RP0X/DCL, depending on
the error and the failing test.
5.8

DISK RELIABILITY DIAGNOSTIC (QUEUE I/O), SAMPLE SUBTEST

5.8.1
Detailed Flow
The Disk Reliability Diagnostic program (ESRAA) is representative
of the queue I/O diagnostics. Instead of performing move
instructions to read and write peripheral device registers
directly (as the MBA diagnostic does), the program builds an
a r g um en t 1 i st cont a i n i n g d e v i c e and t ran sf e r pa r am e t e r s and
pointing to the data to be transferred and the function to be
performed. The program then calls the queue I/O services of VMS or
the diagnostic supervisor. In this way, the program transfers
information to and from the peripheral device under test without
requiring exclusive use of the device, the channel, or the
computer system. Figure 5-14 shows the listing for ESRAA test 1,
subtest 0, error 12, the first of the data transfer tests. Figure
5-15 shows the program flow for the same routine.
5-22

PROGRAM:

ZZ-ESRCA RP0X/DCL DIAGNOSTIC, REV 4.1, 46 TESTS.

TEST 1: QUALIFICATION TESTS
********
ZZ-ESRCA RP0X/DCL DIAGNOSTIC - 4.1
********
PASS 1 TEST 1 SUBTEST 0 ERROR 2 le-MAR-1978 08:26:20.26
DEVICE FATAL WHILE TESTING DBA0: CONTROL BUS PARITY ERROR DETECTED
MBA CHANNEL STATUS DUMP
MBA CSR: [20010000]
00000020(X);
MBA-CR:[20010004]
00000000(X);
MBA-SR: [20010008]
00020000(X);
MBA-VAR: [2001000C]
00000200(X);
MBA-MAP(80):
00000000(X);
MBA=BCNT:[20010010]
00000000(X);

MCPE

TK~~5

Figure 5-13

ESRCA Sample Error Message

5-23

ZZ•ESRAA•S.2

~SR4A8 6 QA.TESTS
51~

DATA TRANSFER TESTS
QUALIFICATION TESTS Zl•ESRAA•S 0 0
DATA TRANSFER TESTS
1

'3"'5

<1.J115

n21r;
,,3.,~5

,·:3115
1•~(115

f.13';15

l!l31<'15

320

ill]:ll5

321
322

:•3.~5

!'3Vl5

t-131'15

11130'5
.,3;,5
IJH15
l!3\lj5
~!HS
~305

1-)305

56
57
05 AB

Al3

AB
AB
00•eF
0q
0tl

!1305
!:130!5
•t3ill5

qA
qA

it309
\:]00

CJt
12

~311

~1318
~319

?.111F SF

~01"111007F

51.1

33111
331

~i32C

\'.!]I.Ii

31u1

1naa

3115

;13qe.

3116

ec
01

1-132E

Rl0 • CURRENT

NU~BER

,..

S~CTOR

NU~BER

R11 • DEVICE CHARACTERISTICS POINTER

338
339 llHSI
340
341 182H
302 1qn1
Jin

'-'HI

D4
C3

CYLI~DER

Rq s CURRENT TRACI< NUMBER

MOVZWL
MOVZBL
l'IOVZBL
CMPf!
BNEQ
r10Vlol

337

011
00
F3

~)]!&

R8 • CURPENT
J

335
336

::i'.523

:.t3211

REGISTERS USAGE1

332
313
334

\1321

SA
56

3211
325
326
327
328
32q

1215 8F
50
i0000111B4'EF40 A570A570 8F

BEGIN MULTI•SECTOR WRITES,wRITECHECI<, AND READS

323

Slil

ll!lo

Fl"1

(.,

3M
31 ii! ;++

311
312
313
314

315
316
317
318
llCJ

r•3~5

Seq11e"ce l91
l'ege 1Z

Ftche 1 '~•~• 016
VAX•ll MACRO X0 0 3•6

0SMQCl• ... CYLNOR(Rlt),R5
DSMOCl8 ... TRACKCRlll1R6
DSKDCS6 4 SECTORCR11),R1
#RM03,0SkDCSB.TYPE(Rll)

ieu

#LSTSECT ... RM,•
LAST 11'1..,.SEC TtlR
tt'2~

llLST$ECT 6 PP,•
LASUW_..SECTOR
CLRL
""0VL
AOBLEQ

PQI

#PATTERNl,8UFFEP1(R0)
•121,R0, un

PICK UP MAXIMUM.NO 0, CYLINDERS
PICK UP MAXIMUM NUMBER
TRACKS
PICK UP MAXIMUM NUMBER
SECTORS
IS THIS AN RM83T
NOPE
GET LAST SECTOR IN CYLIND!R

0,0,

SKIP
LAST SECTOR FOR RP
CLEAR LONG WORD BUffER INDEX
WRITE PHTERN
WRITE 512 BYTES
CLEAR CURRENT CYLINDER
CLEAR CURRENT SECTOR
BEGIN AT LAST TRACK

CLRL
CLRL
SUBL3

~·3119

MOVL
MOVAL
MOVL
MOVB
MOVB
MOVili
MOVL

QIOPTRLIST(R2J 1 R4
BUFFER1,QI01 6 Pl(R4)

POINTS TO QlO ARGLIST
PUT BUF,ER ADDRESS IN QJO ARGLllT
lllRITE BYTE COUNT
WRITE TRACK VALUE
WRITE SECTOR COUNT
WRITE CYLINDER
WRITE DIAGNOSTIC BUFFER A91HtEll

~l/IQ!lttlilftllll~·EF42

IHI

~3UA

tC A4
20 Al.I

~1000.ilolB4•EF

<t35i!

DE
00

~35A

349

00~"·c1.1

1110'1'0•c11

'.'3b2
''367
.t36C

R9,QIOSA 6 TRACK(Rll)
Rtt11,QIOSB 6 SECTORCR4)
R8,QJOSW ... CYLNORCR4)
352
05k08 6 PTRLISTCR2],•
353
QJ{l'll.._P6(R4)
3'54
EF ... LISTIR2J.QIOl,..EF~(R4) f WRITE EVENT FLAG NU~BER
355
""0VL
#JOf.._WRITEPeLK 1 •
I SET FUNCTION • WRITE
1'56
"'0VB
QIOl.._FUlllC(Rll)
157
358
sos.BREAK
J Cl"ECK FOR "'C
CSP), ••OSIBREAI<
CALLG
SQIOlll ... G CPU]
ISSUE QIO REQUEST
CALLG
(RG),G~SYSSQIOW
360
BLBS
CR3),210S
J BRANCH IF NO ERRRORI
CHECl< ... BLOCKS
R2,R8,Rq,Rl0
361
Cl"ECI< BAD BLOCK FILE
PUSHL
A2
MOV•
R&,•CSP)
MOVe
Rq,•(SP)
~OV8
R10,•(SP)
CALLS
#2,CHECK.BLOCk
J BRANCH IF NOT IN BAD BLOCK FILE
RLBC
R~,205!1
BRW
&OJ
GET NEXT BLOCK
J C!o!ECK FOR •c
sos.Bl!BK
CSP), HDSSBREAI<
CAL LG
!QJow... G (RO)
165
CALLG
CRll),G'SYSSQIOw
BLeS
C~3),2t111S
J BRANCH IF SUCCESS
366
REPORT ErlROf:l
sos.ERRHARO.s
,R2,BLANI<,•
167
(\IJMP ... s T6 TIJS
J DUMP STATUS
"468
PUSHAL OUMP ... STATUS
PUS111oL BLANK
PUSHL
R2
PUSHL
HER
TEST 11 SUSTEST 0, ERROR 12
CALLS
#$$"4, •IDSIERRHARD
I LOOP
SDS.CKLOOP
2051
CALLG
205!, ••OSSCi<LOOP
37~
~Rw
b40$
J GET NEXT 8LOCK
$0S 4 CKL00P
2'115$
371 21~s1
CALLG
205!, ••DSSCl<LOOP

00,H11•c11
30 Al.I

;alila0~21rn

:aPl'l\Hll001i1• EF42

""
Fl!/!
00

:.'371
V.37A

»HA

CJ0

>H3

F•
Fl.
EB

7E
7E
7E
00PJIH!000•EF
ri!3

51J
5q

SA
~2

5'71

"178

90
90
FB
E9
31

t;3ea
•'387

rne1

-lleE
;>!f!E
••395
wi39!!
P.398
1"391

U91'.1
"'3Ae
.J3A3

:>t3U
ll]An
~3~0

FA
FA
El3

'l\lllll"!llfi'0111Ql•EF
•H•i\@~0AA•EF

:'3f.l~

''387
i'3~7

H3eF
:13c1

'13(1
OF
DF

03Ct
'HC7
~1 3Cl'

:'3CF

P301

ii3ot
1•3llll

FA
31
CA AF

'·l3DIJ
••3f'~

L1 3EJ

'tJ3E3

3117
148 2fll0SI
l'S~

3'51

Figure 5-14 Disk Reliability
(ESRAA) Test 1, Subtest 0,
Error 12 Listing
5-24

• '5 ti!, a I os.n <R41

TK-1127

VMS
AND
DIAGNOSTIC
SUPERVISOR

I
I
1

I
I

I
I
COMMAND
LINE

DISK RELIABILITY ESRAA TEST 1,
SUBTEST 0, (ERROR 12) DATA TRANSFER TESTS
START
SET POINTERS
TO CYLINDER 0
SECTOR 0
DETERMINE NUMBER
OF CYLINDERS
TRACKS
SECTORS
DETERMINE DRIVE
TYPE

LAST TRACK

BUILD Q 1/0
ARGUMENT LIST:
BUFFER ADDRESS
BYT~ COUNT
TRACK SECTOR

CYLINDER

WRITE PATTERN 1
(A570A570)
INTO A BUFFER
512 BYTES

DIAGNOSTIC BUFFER
ADDRESS
EVENT FLAG#
FUNC =WRITE

YES

INTERPRETE~

01/0 SERVICES
WRITE PATTERN 1 TO
FIRST CYLINDER
FIRST BLOCK LAST
TRACK
LOAD DIAGNOSTIC
BUFFER
LOAD 1/0 STATUS
BLOCK (IOSB)

ISSUE
Q 110
REQUEST

YES

SUCCESS

I
DS$CKLOOP

I
I

CONTINUE WITH
NEXT PART
OF TEST 1
(READ PATTERN

JUST WRITTEN)
TK-0582

Figure 5-15

ESRAA Test 1, Subtest 0, Error 12 Flowchart
(Sheet 1 of 3)

5-25

ESRAA DISK RELIABILITY

VMS
AND
DIAGNOSTIC
SUPERVISOR

-- -- - - - 1
rI --- ----,
r
I
I
I
I
CHECK BLOCK
ROUTINE

I
I
I

I
I

7ET-;;F
SECTOR
ROUTINE

READ
BAD BLOCK
FILE

L __

I
I

I
I
_J

I
I
I

I
I
NO

COMMAND
LINE
INTERPRETER

VI
I

°'

0 1/0 SERVICES
WRITE PATTERN 1
LOAD IOSB
AND DIAG BUFFER

DS$ERRHARD
DUMP STATUS
PRINT ERROR MSG

GET (NEXT)
WORD FROM
BAD BLOCK
FILE

YES

ADD 2 TO
SECTOR
COUNTER

I
I
I

ISSUE
Ql/O REQUEST
(RETRY)

r -- J

I
I
L--

----

BAD BLOCK
FILE IS
OK

I
..J

DS$CKLOOP

TK·Ol83

Figure 5-15 ESRAA Test 1,
Subtest 0, Error 12 Flowchart
(Sheet 2 of 3)

VMS AND DIAGNOSTIC
SUPERVISOR

ESRAA
DISK RELIABILITY

SET POINTERS
FOR NEXT
BLOCK

YES

STATUS DUMP

PAINT
COMPLETION
TIME

COMMAND
LINE
INTERPRETER

YES

DISPATCH
ROUTINE

I
Figure 5-15

TK-0584

ESRAA Test 1, Subtest 0, Error 12 Flowchart
(Sheet 3 of 3)

5-27

The first test, when it is called by the dispatch routine in the
supervisor, sets up a pointer to the I/O status block and tests
various drive commands (drive clear, seek, recalibrate, NOP,
offset, and reset). Test 1 then performs an oscillating seek test
before beginning the data transfer tests.
In the data transfer tests portion of test 1, the program sets up
a write transfer of a data pattern (A570A570)
to the first block
on the disk pack in the drive under test. The data to be written
to the disk is loaded into a buffer area in memory. The program
then builds an argument list containing the address of the data
buffer, the byte count of the data to be transferred, the location
of the target block on the disk pack (track, sector, cylinder),
the diagnostic buffer address, the event flag number, and the
function to be performed. Then, after checking for Control C, the
program calls SYS$QIOW.
If the program is being run in the user mode (VMS environment),
the call to SYS$QIOW invokes a routine in VMS. If the program is
being run in the standalone mode, the SYS$QIOW call invokes a
similar routine in the supervisor. SYS$QIOW builds an I/O packet
from the parameters passed from the diagnostic program and then
(if in VMS) checks the privilege of the cal 1 ing process (the
diagnostic supervisor) through internal data structures. The
SYS$QIOW routine then places the packet in a queue for processing
by a device driven routine, clears the event flag, and waits for
completion of the I/O function (indicated by the setting of the
event flag). When the driver completes the I/O function, it
examines the controller and drive status registers, formulates a
status message that is stored in the I/O packet, and loads the
d i agnostic buff e r wi th d r iv e and adapter reg i st er contents • The
I/O packet is then inserted into the I/O post queue and a software
interrupt to initiate I/O post processing is requested. The I/O
post routine performs final I/O request processing and status
posting
(IOSB), loads the diagnostic buffer with device and
adapter (on MBA or UBA) register contents, and sets the event
flag.
With the event flag set, the calling program (ESRAA) resumes
control. The diagnostic program then checks the I/O Status Block
(IOSB) to determine whether or not the requested function was
completed successfully. The IOSB has the format shown in Figure
5-16.
00

1615

STATUS

BYTE COUNT

DEVICE-DEPENDENT DATA
TK-0743

Figure 5-16

I/O

Status Block Contents (for disks)

5-28

If the low order bit of the first longword of the IOSB is set,
indicating success, the program does a branch to the next portion
of the test (label 210$), where it tests the loop flag and then
reads the data just written to the disk pack.
If the low order bit of the IOSB is not set, the test calls the
CHECKBLOCK routine (refer to the code in Figure 5-17) , which is
located in the load blocks module (module 6) of the disk
reliability program (refer to the link map). This routine, in
turn, calls the GETBBFSECTOR routine (Figure 5-18) which reads the
load block sector on the disk pack. If the load block file cannot
be read at all, the routine returns control to test 1, where the
queue I/O request is retried. If the load block file has been read
successfully, the routine checks through the item in the file to
see if the address of the block which cannot be writ ten to is
already noted in the load block file. If so, the load block file
is OK, and control returns to test 1, which sets up po inter to
access the next block on the disk, builds a new queue I/O argument
list, and again calls SYS$QIOW, as previously explained, in an
attempt to write the pattern into the next block on the disk.
If the failing block address is not listed in the load block file,
the CHECKBLOCK routine returns control to test 1 which, in turn,
issues a second queue I/O request (after checking for Control C) •
If the request fails again (IOSB status code = 0), the program
calls the DS$ERRHARD routine in the supervisor, which dumps the
status block and diagnostic buffer contents and other error
information. After detecting a failure of this type, the program
checks the loop flag. If the loop flag is set, the program repeats
the queue I/O request indefinitely. Otherwise, the program checks
each block on the disk pack .until it finds one that it can write
into successfully, before going on to check the next function
(read the block just written, beginning at label 210$).

5-29

ZZ•ESRAA•S.2
ESRU& 4 "1AP .&.BB

s.0

SAO BLOCK FILE ROUTINES

~AO

001"i~IH'l00

0FFC
1110
0171
00\10l0030'EF

01
04
5@

00000POIOl'9F
18

°'~PH!
~01710
~i'102

DD
DD

b'111lll

21:-llilb

,~11.;ic

\!@oll:

•11'115

113

1i0t8

Cll"!HHllll00'EF

1•:.otA

08 AC
!Ill

lh'li?f;I

i'.'>323

011

\Hll25

bC
AC

''02C:
llij?C

,,;iJ3
l"t.H7

05 AC
0b AC

3C
0111

!H'3F

1111143

r1!~25

S7
58

'Sb
02

:HW0l10~4 • EF4S

55
00"1!00PC A 'EF
0A

56
02
50

1118
b4
~2

CJA

~'13B

~·'145

1Hl4FI
tttlSVI

158
159
1 blil

FR
EB
91
13
Cfl!
11

tHl54

101
162
161

•H~58

f1l'l5E

11
DD

56
02
50
02

1b4

165

{Hi66

166
167 SCANI
168
16CJ
17111
171
172
173
174

'l'P~8

'IWlbR

l 1 !~71

''ll"7E

175

FFFF 8F

¥"08ti

..,lll~R

176
177
178
17CJ
180

113

S0
50

"1000AOl3ill"FF47

Sic"

08
'52

24
10
51<1

0!1

10
18

81
12

'l'it.'78
~''-'7R

tr'~'!O

ti~9i..t
~l.,92

rMf

i•PA0

(•:uz
A~AI!

0001l1001l10•9F

5l'I

01
13

FB
9A

1•:itF!1

1112,GETSFlF.,SECTOR
RP, SCAN

M(lVZl3L

*B,Rb
20'

#8 1 P6

#2,Rll

n, GETBl'lF .. s~CTOR

SLSC

R0 1 U0$

MOVZ8L

*2 1 R7
•BBF.POINTERfR7],R0
*•l,R~

401
RP', Rll
3~$

#16 1 #8 1 R0 1 P2

•'i/!84

C0
CJ1
111

lll'.,f

rr.ocs

!-IVJC7

'tj;IBb

PICI( UP SECTOR
PICK UP TRACK
PICI( UP CYLINDER
PICK UP LOGICAL UNIT NUM8!R
CLEAR SECTOR COUNTER
INITIALIZE INDEX OFFSET
PICK UP ADDRESS OF DRIVE CHARACTERISTICS

PUSH LUN
PUSH SEC:TOR
READ BAD BLOCK SECTOR
BRANCH IF SUCCESS
HAVE FIRST FIVE SECTORS BEEN READ?
TAKE FAILURE EXIT
J ADO 2 TO SECTOR COUNTER
r CONTINUE READING
:~INITIALIZE SECTOR COUNTER
CHECK BLOCK READ FROM PREVIOUS LOOP
PUSH LUN
J PUSH SECTOR NUMBER
READ NEXT SECTOR
IF FAILURE TRY NEXT BLOCK
IGNORE FIRST TWO LONG WORDS OF THE FILE
PICK UP BAD BLOCK FILE ITEM
CHECK FOR END OF BAD BLOCK FILE
If:" EOF TRY NEXT SECTOR
1 IF CYLINDERS DON'T MATCH
THEN BRANCH
IF SECTORS OON"T MATCH
THEN BRANCM

IF TRAC~S OON"T MATCH
8111EQ
311''
IDS.,RELBUF' ,.S
PUSHL

183

lAU

PUSHAQ

PUSHL
OLLS

·~~AA

I 1
F3

13P13

MOVL
CMPW
8EQL
CMPW
BNEQ
C"1PZV

llH!A~

(II(?

V:~qq

'57

, SUCCESS?
LUN(AP).MSG.,NOMEM

1<0cn

CMECK.&.BLOCllZX

PllSHL
CALLS

ALLOCATE BUFFER

nCJC

#4, •#DSSGETBUF

C"1P13
BEQL
AOOL
l!RB

PUSHL

CJ>

8RF.,POINTER

~"q5

~lll:!l11H1i'l 30 "EF

ill~'10?!f"7F

BUIS

~·1•&3

FB
E9
1U
DP

000000ca"EF

PUSHL
PllSHL
CALLS

PH•

#0
#0

P~,2$

ios .. ERRSYS.,S

h!lb 1

1'~60
~:~'bF

#1,8BF.,POINTER

#0
PUSHL
PUS HAL MSG ... NO"lEM
LUN(AP)
PIJSHL
#$fR
PUSHL
:11 TEST ~. SUBTEST 0, ERROR 1
#!$~, ••DSSERRSYS
CALLS
$05.,ABOPT .
150
CALLG
CAP), ••DSSABORT
SECTORCAP),R2
"10VZEIL
151 2$1
"10VZEIL TRACKCAP),Rl
152
MOVZwL CVLINOERCAPl 1 R4
153
LUNU.P), RS
154
"'OVL
RI!
CUil
155
"40Vl8L 1112,R7
156
MOVQ
DSKl>C.,QWDLIST+4[R5] 1 R~
157

P-052

V."5i'I

BL~S

leQt.iePIC•

•McR2 1 R3,R4 1 PS,Rb,RT,R8,R9,Rl0,R11>

$OS.,GETRUF~S

1118
149

1118
55

CODES
0 PSECT
CHECK.,BLOCK11
.wORO

PUSHL
PUSHL
PUSHAQ
PLJSHL
CALLS

l)D

f'~bfl

144
145
14&
11.17

V130i?

QI!~

00000000'9F
S2

Ftc~e l
F~•~• L1l
VAX•ll MACRO X0.3•6

BLOCKS ZZ•ESRAA•5 0 0
BAD BLOCK FILE ROUTINES
~AP

185
180
187 3il!Si

THEN BRANCH
Iii l 1 IH~F ..,POINTER

BBF ... POilllTER
Iii 1

*31 UOSSRELBUF

MO'/Z!ll

111,R~

INDICATE SUCCESS

BAB
AORLEQ

CMECK ... BLOCkX

ANO EXIT
IF ALL BLOCKS NOT CHECKED INDEX AND LOOP

AOOL
C"'PB

Po,OSKDCSB..,SECTORCR8)

BLSS

1 r/1$

#127,R7r2~S

>ll!'ijl)
,_,~(J

,c:)C7
r;,4

:me CJ
·1t•CCI

Cl-IECK..,BLOCKZ><:
CLPL
C:lifCK..,BLOCKX:
RET

#2,R&

BUMP SECTOR COUNTER SY TWO
CHECK FOR LAST SECTOR
CONTINUE READING IF NOT LAST SECTOR
r ELSE INDICATE F•ILURE

EXIT

v1:1CA
,1~CA

:-li'ICA
r.rn(A

SBTTL
TIC-1126

Figure 5-17
Routine Code

5-30

CHECKBLOCK

~0CA

'53

0~H-lei"10~/J • EF42

5ll

;.rnf?!~000W' EF

,.~oa

272

.WORD
MOVL
MQVQ
MOVAL

"'1

:H~OF

273

SU~B3

•McR2,R3,R4,R5,R6•
LUNCAP),R2
DSl<OC.QWOLIST+4[R2] 1 Rl
ARGUST, IU
#1,0SKOCSB 4 TRACKCR3)1•

vt'"1Et

274

!:.1"'Eb

2715

susw 3

•1,os~ocsw.CYLNORCR3),•

tl~E8

270
277

08 AC

0~00•c1.1

V'i
I

208 GETBBF 4 SECTO~ 11

Al
01

~07C

\-~~CA

26q

'.•~cc

270

f.jiilf)~

0000'C4

'1A A3

lC A4

v.l0~'1Chf3~ • EF

1t1~EO

'1k'F5

MIFR

0~H·rn·c'-'

20 AIJ
04 Atl
5l'I
fr:J8 A4

'~4

'il2et0 8F
OllHJ~tl'-"~Ol·EF42

n1~1

EF 4 2

iJl 0A

00
00

!...·"112

280
28t
21'2

I'! 11 7

283

t 18

28U
285
286

Y'~lA~~~fl!,_,0'

08 Alli

0C A4

0C AlJ

~'0~1Cl!i-l8n~

955
1 r;t A''

~10

v. "0 0 i;, (I! • EF4 2

C8
7E

(Al 23

'''ea

61J

>' t 2F

¥113b
'.' 137

1110000~"'0' GF

278
27q

1?F

287
2~8

2M .SB TTL

PICK UP THE LOGICAL UNIT NU"BER
PICK UP POINT!A TO DRIV! CHA•ACTlRllTICI
R4 C•• POINTER TO LOCAL QIO ARGLIIT

, WRITE TRACI< TO READ
, WRITE CYLINDER TO READ
QJoiw .. cYLNOR(R4)
MOVL
BBF POINTER,QIOS..,P1CR4) , WRITE 8U,F!R ADOR!IS INTO HO ARGLUT
SECTOR(AP),QIOSB..,SECTORCR4) , WRITE SECTOR TO READ IN QIO ARGLllT
, WRITE BVTE COUNT
MOVZWL #c;t2,QIOS..,P2(R4)
~ove

MOVL

MOVL
~OVL

QI0$8.._T~ACk(R4)

WRITE EVENT
,' PICK
UP QIO PTA
, WRIT! ASSIGNED CHANNEL

EF~LIST[R2],QIOS..,EFNCR4)
QJOPTRLIST(R2),~0
QIOS..,CHAN(~0),QIOS 4 CHAN(R4)

~LAG

WRITE R!AD PMVSICAL 'UNCTION COD!
•IO!.RfADP8LK,QIOS..,FUNC(A4)
INHIBIT !RROR LOG
#IOSM.INHERLOG,QIOS.FUNC(R4)
MOVAQ
1 PICK UP IOS8 ADOREll
IOSTATUS.BLOCK[R2J,R5
MOVL
R5,GIOt..,IOSBCR4)
r WRITE IOS8 AODR!SS INTO QJO ARGLIST
sorow.G ( Rll)
1 ISSUE QIO REQUEST
(R4),G.,SYSSQIOw
CALLG
RET
EXIT
PUT 4 8ADBLK ROUTINE
MOVL
~ISL

TK-1125

Figure 5-18

GETBBFSECTOR

Routine Code

5.8.2
Disk Reliability Program Sample Error Message
Test 1, Subtest 0, Error 12 of the disk reliability program
identifies bad blocks, on the disk pack under test, that are not
entered in the bad block file. The message shown in Figure 5-19
identifies the failing test, subtest, and error numbers. The
me~sage
also includes a dump of the channel registers (MBA
registers in this case) and the RM03 registers.
Notice that bits 12 and 15 of the RMERl register are set,
indicating a data check error. The starting cylinder is 0. The bad
block is located in sector 1, on track 4, as shown by the contents
of the RMDA registers.

TEST 1: QUALIFICATION TEST
DRAl QA BEGUN AT 2-FEB-1979 14:26:18.54
********
VAX DISK RELIABILITY TESTS ** ESRAA ** -- 5.2
********
PASS 1 TEST 1 SUBTEST 0 ERROR 12 2-FEB-1977 14:26:20.52
HARD ERROR WHILE TESTING DRAl:
FUNCTION INITIATION SUMMARY:
FUNCTION ATTEMPTED: WRITE DATA
BUFFER ADDRESS RANGE:
FROM: 00000388
ATTEMPTING BYTE COUNT WAS: 512
STARTING DISK ADDRESS:
CYLINDER: 0
TRACK: 4
SECTOR: 0

TO: 00000587

FUNCTION ABORT SUMMARY:
UNDEFINED SYSTEM STATUS VALUE = 00000000
ADAPTER CODE= 20(X)
MBA CSR
00000020
IE
00000004
MBACR
DT COMP
00002000
MBA SR
MAP POINTER= 0l(X), PAGE BYTE ADDRESS= 188(X)
00000388
MBAVAR
MASSBUS BYTE COUNT = 0000 (X) , SBI BYTE COUNT = 0000 (X
00000000
MB AB CR
BIT 31, BIT 7, BIT 6, BIT 5, BIT 2, BIT 1, BIT 0
MBAFMAP
800000E7
BIT 31, BIT 7, BIT 6, BIT 5, BIT 4, BIT 1
800000F2
MBAPMAP
DVA, FUNCTION = WRITE DATA
0830
RMCSl
MOL, DPR, DRY, VV
11C0
RMDS
DCK
RMERl
8000
MWR, MSCLK
0028
RMMR
0000
RMAS
TRACK= 04(D), SECTOR= 0l(D)
RMDA
0401
MOH, DRQ, DRIVE TYPE = RM03
2814
RMDT
SECTOR= 0l(D)
RMLA
0040
SERIAL NUMBER= 8846(X)
8846
RMSN
FMT22, ECCI
1800
RMOF
DESIRED CYLINDER= 00000(D)
0000
RMDC
RMHR
0000
CNT/CYL, BUS IN LINES = lFF(X)
13FF
RMMR2
0000
RMER2
BURST LOCATION = 0836(X)
0836
RMECl
ERROR BURST= 0000(X)
0000
RMEC2
TK-1237

Figure 5-19 ESRAA
Sample Error Listing

5-32

CHAPTER 6
CPU CLUSTER EXERCISER P~KAGE
The CPU cluster exerciser package consists of three separate
programs (ESKAX, ESKAY, ESKAZ). Two modules, the control module
and the common instruction test services module (CITS), are common
to all three programs. ESKAX, the first program, is the quick
verify port ion of the c 1 us t er exerciser package • This program
includes the compatibility mode entry and exit test, the first
part done test, and the SBI exerciser. The second program, ESKAY,
contains the timer and clock tests and the native mode instruction
set tests. ESKAZ contains the memory management test and the
compatibility mode instruction set tests. Figure 6-1 is a map
showing the memory allocations of the three programs.
The cluster exerciser diagnostics will handle three classes of
errors, providing three corresponding types of error messages:
unexpected exceptions or interrupts; test failures; and safe
return halts (resulting from fatal errors). The code for the
cluster exerciser programs is not as easy to follow as the code
for other diagnostic programs. However, the error messages which
the programs generate are detailed and, for the most part,
self-explanatory. The operator should understand the general
structure of each test and the error message formats in order to
use all of the facilities provided by the cluster exerciser
programs.

6.1

CONTROL MODULE

The control module in the cluster exerciser programs serves as the
interface between the programs and the diagnostic supervisor. The
module performs the following functions:
Program initialization and clean up
Execution of all tests twice in one pass
Print out of a module summary message at the end of each
pass, if errors exist
Initialization and reinitialization of pertinent control
variables
Set up of
handling

all

vectors

Proper fielding of all
(expected and unexpected).

for

interrupt

exceptions

and
and

exception
interrupts

When the control module detects an unexpected interrupt or
exception, it prints out an error message as shown in Example 6-1.

6-1

ES KAZ
(MEMORY MANAGEMENT
AND
PDP-11 INSTRUCTIONS)

ES KAY
(NATIVE INSTRUCTIONS)

ESKAXOO
10236
CONTROL

ESKAX01
18000
CITS

MEMORY
MANAGEMENT
10000
ESKAZ02
TEST 01

COMPATIBILITY
INSTRUCTIONS
13500
ESKAZ03
TEST 02

TIMER AND CLOCK TESTS
3822
ESKAY02. TEST 01
ARITHMETIC. LOGIC. AND
FIELD INSTRUCTION
ESKAY 03. TEST 02
BRANCH.CRC.AND
QUEUE
ESKA Y05. TEST 04
BRANCH. CRC. AND
QUEUE
ESKAY06. TEST 05

ESKAX
(QUICK VERIFY)

COMPATIBILITY MODE
ENTRY/EXIT
6534
ES KAX02. TEST 1

FIRST PART DONE
ES KAX04. TEST 2

OPERAND SPECIFIER
FLOATING POINT DEPENDENT
ESKAY 07. TEST 06
DECIMAL STRINGS
ESKAY 08. TEST 07

SBI
VERIFICATION
17155
ESKAX05. TEST 03

EDITPC OPERATORS
ESKAY09. TEST 08
CHARACTER STRING
INSSTRUCTIONS
ESKAY10. TEST 09
PRIVILEGED INSTRUCTION
EXCEPTION. ESKAY11. TEST 10

MEMORY VERIFY
ESKAX06. TEST 04
TK-0737

Figure 6-1

CPU Cluster Exerciser Package Memory Allocation
6-2

********
PASS 1

CPU CLUSTER EXERCISER
TEST 6

SUBTEST 4

9.0

********

ERROR 1

HARD ERROR WHILE TESTING CPU: EXCEPTION SERVICE ROUTINE
UNEXPECTED EXCEPTION
ERROR# 00000001
VECTOR# 00000030
SUBTYPE# 00000006
PSL 83C00000
PC 0000110D
Example 6-1

Unexpected Exception Error Message

Refer to Chapter 2 of the VAX-11 KA780 Central Processor Technical
Description for a discussion of vectors and subtypes. When the
machine check vector is asserted, the exception handler attempts
to log out relevant status registers on the stack before pushing
two longword parameters (summary and length) on the stack (Table
6-1). In addition, the subtypes for vector 4 (machine check) are
listed in Table 6-1.
Table 6-1

Summary Parameter, Length Parameter for Vector 4

Summary Parameter
Subtype

Byte 9

CP Read Timeout/SB! Error Confirmation Fault

CP TBUF Parity Error Fault

CP Cache Parity Error Fault

CP Read Data Substitute Fault

Instruction Buffer TBUF Parity Error Fault

Instruction Buffer Read Data Substitute Fault

Instruction Buffer TBUF Parity Error Fault

Instruction Buffer Read Data Substitute Fault

IB Read Timeout/SB! Error Confirmation Fault

IB Cache Parity Error Fault
6-3

Table 6-1

Summary Parameter, Length Parameter for Vector 4
(Cont)

Summary Parameter
Subtype

Byte 0

CP Read Timeout/SB! Error Confirmation Abort

CS Parity Error Abort

CP TBUF Parity Error Abort

CP Cache Parity Error Abort

CP Read Data Substitute Abort

CP (Not Supposed To Be Here) Abort
Byte 1
This byte will be a nonzero value if a CP timeout
or CP error confirmation interrupt is pending.
Bytes 2 & 3
These two bytes must be zero.

Length Parameter
Byte 0
The number of bytes
this parameter.

logged

out

are

exclusive

Byte 1--3
These three bytes must be zero.
When an unexpected interrupt or exception occurs, information is
pushed on the stack by the exception handler as shown in Table
6-2.

6-4

Table 6-2

Information Pushed on the Stack
by the Exception Handler

Mnemonic

Meaning

SP:

Length Parameter

ID Bus Address

Summary Parameter
CES

CPU Error & Status

Trapped UPC
Virtual Address/
Virtual Instruction
Buff er Address
D

Interface Between
Data Paths and
Memory

08 (Bytes 1 & 3)

TBER0

Translation Buff er
Error Register 0

TBERl

Translation Buff er
Error Register 1

TIME.ADDR

PARITY

Cache Parity Register

SB I.ERR

SB! Error Register

PC
PSL
Note that information on the stack is not saved by the exception
handler. The EIH module must be breakpointed before this data is
accessed.

6-5

6.2
COMMON INSTRUCTION TEST SERVICES MODULE (CITS)
Thi s mod u 1 e cons i st s o f a group o f soft war e rout i n es that
implement a table-driven test method for a majority of the VAX-11
instruction set. CITS interprets the contents of a specially coded
test table and executes tests of VAX-11 instructions. CITS is also
used for tests of the first part done function and memory
management. A copy of each of these test instructions is coded in
register deferred mode
(RN). Before the test instruction is
executed, the test data is placed somewhere in memory, and the
registers are loaded with the addresses of that test data. After
the test instruction is executed, the contents of the registers
and the contents of the test data area of memory are checked.
There are four main routines in CITS that do the work of executing
tests: CITS_DECODE, CITS_SETUP, CITS_EXECUTE, and CITS CHECK.
6.2.1
CITS DECODE
This routine decodes one test table entry, in a table of cases,
and generates directions for the other three routines to use.
These directions are lists of addresses and other variables placed
in the parameter blocks of the CITS data area.
6.2.2
CITS SETUP
CITS SETUP moves the test data from the common data pool into the
operand buffer. The operand buffer is the location of the data
referenced during execution of the test instruction. The locations
to be used for destination data are filled with a standard
background pattern, hexadecimal AS, in each byte. Also, each
operand, whether source or destination, is preceded and followed
by a longword of the background pattern. CITS SETUP loads
registers R0--R6 with the operand addresses to be used by the test
instruction. The initial PC and PSL calculated by CITS DECODE are
pushed on the stack by CITS SETUP along with a return address. The
return address points to a routine to save the result PSL and
registers.
6.2.3
CITS EXECUTE
CITS EXECUTE enables the exerciser's exception handler to react
properly for the current test. It passes the address of a CITS
unexpected exception handler and enables validation of the
except ion of trace trap being tested, if any. CITS EXECUTE then
executes an REI to start the test. A NOP instruction-precedes the
REI and can be used for scope sync if the microbreak address is
set up correctly from the console. When the test instruction
finishes, the test subroutine returns to a result-saving routine.
The PSL and registers R0--R6 are saved in the execution parameter
block, as are the contents of the exception handler Interface Data
Block (IDB). Also saved is an indication of whether the
instruction branched, if it is a branch instruction.
6.2.4
CITS CHECK
CITS CHECK checks the results of instruction execution, and also
checks the source operands and background pattern. It uses the
directions and addresses put into its parameter block by
6-6

CITS DECODE to control checking. It checks branches, the PSL,
exceptions (whether an exception happened and at the right PC),
registers R0--R6, and memory data. When checking memory data,
CITS CHECK also checks the longword before and after each operand
to make sure that the background pattern has not been disturbed.
CITS CHECK keeps a list of all errors found during one test case.
This-complete list will be typed out when the test module using
CITS makes the $DS_ERRHARD call to the diagnostic supervisor.
6.2.5
CITS SUBTEST
CITS_SUBTEST is a common subtest control routine that is used by
most of the tests that call CITS. It processes a complete test
table, calling the preceding four CITS routines in the proper
order and calling the supervisor error reporter when necessary.
6.2.6

CITS Error Messages

6.2.6.1 Message Heading -- A standard diagnostic supervisor
head in g i s typed (by the super vis o r) • That i s f o 11 owed by an
extended error printout that supplies the test, subtest, and error
numbers; the test case number; the op code of the failing
instruction; addresses referenced; operand data; etc. Refer to
Paragraph 6.4.2 for examples and detailed interpretation.
6. 2. 6. 2 CITS Subtest Troubleshooting Features -- SCOPE SYNC -CITS EXECUTE executes a NOP instruction just before the REI to the
test- instruction. Putting the microaddress of SE into ID Bus
register 21 will cause a sync pulse to be generated on the
microsequencer board (M8235) each time a NOP is executed.
To loop on a failure with SCOPE SYNC, perform the following steps:
>>> D /ID 21 SE
>>> START 10000
(DIAGNOSTIC SUPERVISOR STARTUP)
DS> SET !El,LOOPD
DS> START /TEST: N

(WHERE 'N' IS FAILING TEST NUMBER)

ETC.
Halt Before the Failing Test Case -- At the beginning of
the
t es t- case
exec u t in g
1 o op ,
the
case
numb e r
(CITS CASE) is always incremented and compared with the
content of CASE HALT. If these are equal, a HALT is
executed. This feature allows the operator to stop before
execution of a particular case, in order to examine
registers, e.g., deposit the hex case number into
CASE HALT. Run the test unti 1 the halt is executed. (If
needed, use CONTINUE until you get to the right subtest.)
Then either set a breakpoint or deposit a byte of zero (a
6-7

HALT) in CITS SYNC and type CONTINUE to get to that HALT.
You have now- stopped just before the REI to the test
instruction of interest. Use the console to set up
whatever operation you wish to perform and continue as
desired.
Figure 6-2 shows the sequence of events fol lowed by CITS in the
execution of ESKAY03, test 2, the arithmetic, logic, and field
instruction· test module.
6.2.6.3 Unexpected Exceptions in CITS
If an unexpected
exception occurs during a test, CITS will print a header
containing the case number and the error information from the
exerciser exception handler. This printout only occurs while CITS
is handling unexpected exceptions, i.e., only during the execution
of the five instructions before the test instruction and
approximately through the three instructions after it (Example
6-2). If an exception occurs outside of that set of instructions,
then the error typeout is not handled by CITS and will not have a
case number heading.

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 1

ERROR 25

9.0

********

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 25
UNEXPECTED EXCEPTION
ERROR# 00000001
VECTOR# 00000004
SUBTYPE# 00000000
PSL 001F00E0
PC 00000003
Example 6-2

Unexpected Exception in CITS, Error Message

Refer to Example 6-1 (Paragraph 6.1) for
unexpected exception error message format.

an explanation of the

6.2.6.4 Result Register Errors -- If the contents of any of the
registers R0--R6 are not as expected, CITS prints out initial,
expected, and actual values, as shown in Example 6-3.

6-8

ESKAY 03

DIAGNOSTIC
SUPERVISOR
START

CASE=
CASE+ 1

COMMAND LINE
INTERPRETER

DEPOSIT

00 IN CITS
SYNC (HALT)
INIT
CITS DECODE
(DECODE CASE)
DISPATCH
ROUTINE
CITSSETUP

TEST 2

CITSEXECUTE

CITSSUBTEST

STEP
THROUGH
INSTRUCTION

CASE= 0
REI, POP PC,
POP PSL, EXECUTE
INSTRUCTION

RETURN FROM
EXECUTION

CITSCHECK

PRINT
ERROR
MESSAGE

TK-0755

Figure 6-2 Execution of a
Test Case in ESKAY03

6-9

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 4

********

9.0

ERROR 17

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 17
? REGISTER CONTENTS ERROR
INITIAL

EXPECTED

ACTUAL

00005404

00003800

00003880

00005414

00008000

00005418

00000000

00005476

00000000

·RS

00000000

Example 6-3

Result Register Errors

Initial data shows the values
start of the instruction.

loaded

into

the

registers at

the

6.2.6.5 Leading or Trailing Background Errors -- If the longword
before or the longword after an operand is changed during
execution, CITS reports the error. Leading means the longword
before the data (lower address than the data) • Hexadec ima 1
ASASASAS is the standard background pattern.
6. 2. 6. 6 Data Errors -- When CITS detects a data error, part of
the error typeout is an operand number. That is, a number in the
range 1 to 6 corresponding to the left-to-right order of the
operands for the instruction. For example, in a MOVL instruction
the source longword will be called operand 1 and the destination
longword operand 2.
If the incorrect operand is not of a writable or modifiable access
type, then the error message includes the statement: read-only
operand overwritten.
If the incorrect operand is writable or modifiable, then the error
message includes the statement: incorrect result (Example 6-4).

6-10

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 7

ERROR 10

9.0

********

0 ·

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 10
? INCORRECT RESULT OPERAND 2
ACTUAL

EXPECTED

Example 6-4

CITS Detects a Longword Data Error

Example 6-4 shows incorrect longword data. For word and byte data
errors, the format is the same except that a word is typed as four
hex digits, and a byte as two hex digits. In a quadword or
double-floating word typeout, the lowest addressed longword is the
first line of data typed. That is the longword containing the sign
and the exponent for the double-floating case. (In the quadword
case, the sign is in the longword typed on the second 1 ine of
data, Example 6-5.)

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 1

ERROR 91

9.0

********

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 91
? INCORRECT RESULT, OPERAND 2
EXPECTED

ACTUAL
996740D6
86A2E99E
Example 6-5

CITS Detects a Quadword Data Error

Errors in string data (character string,
etc.) are displayed in Example 6-6.

6-11

packed decimal string,

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 1

ERROR 44

9.0

********

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 44
? INCORRECT RESULT, OPERAND 4
EXPECTED

ACTUAL

••• A5A5*39*4E39 •••

0 BYTES FROM START OF STRING

Example 6-6

CITS Detects a String Data Error

Each byte is typed as two hexadecimal digits. The expected data
only shows the good value of the byte that did not compare. The
actual data shows five bytes of the result string. The beginning
of the string is to the left, the end is to the right. The left
hand two bytes (four digits) are good result data; the byte
between asterisks (*) is the one that failed to compare; and the
right two bytes are the start of the rest of the (uncompared)
string. The last line tells how far from the beginning of the
string the bad byte is.
6.2.6.7 PSL Errors
Result PSL errors are typically wrong
condition codes. The condition codes are the right-hand hex digit
of the PSL. The E in the second from right-hand digit indicates
that the decimal overflow, floating underflow, and integer
overflow traps are enabled (Example 6-7). This condition is always
true when the test instruction is being executed.
********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 1

ERROR 50

9.0

********

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 50
? RESULT PSL ERROR
EXPECTED

ACTUAL

001F00E8

001F00El
Example 6-7
6-12

PSL Error

6.2.6.8 Branch Errors
When testing instructions that may
branch, failure to branch when expected or a branch taken when not
expected produces a message like that in Example 6-8.

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 4

ERROR 1

9.0

********

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 1
? EXPECTED BRANCH DIDN'T HAPPEN
Example 6-8
6.2.6.9

Branch Error

Expected Exception or Trace Trap Errors

An error message is produced if an expected exception or
trace trap fails to occur at all.

The PC and PSL of expected exceptions and trace traps are
checked. If an error is detected, a message like that in
Example 6-9 is typed.

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 4

ERROR 2

9.0

********

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR
? ERROR IN TEST CASE NUMBER: 2
? INCORRECT EXCEPTION PC

EXPECTED

ACTUAL

000025FS

00002566

? INCORRECT EXCEPTION PSL

EXPECTED

ACTUAL

001F00E5

001F00E4
Example 6-9

Expected Exception Error

In Example 6-9 both the PC and the PSL were incorrect at the time
of the exception. In Example 6-10 only the PSL was wrong at the
time a valid trace trap occurred.
6-13

********
PASS 1

CPU CLUSTER EXERCISER -- 9.0
TEST 2

SUBTEST 2

ERROR 127

********

HARD ERROR WHILE TESTING KA0: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 127
? INCORRECT TRACE TRAP PSL
EXPECTED

ACTUAL

001F00F0

001F00F8
Example 6-10

Trace Trap Error

6.2.6.HJ
Extended Printout -- If the extended error printout
flag is enabled, the fol lowing additional data will be typed out
on error detection (Example 6-11).

[1.]

INITIAL CONDITIONS:
PC 00004873

PSL 001F00FF

OP CODE -- 74 WITH REGISTER INDIRECT OPERANDS
[2.]

[3.]

INITIAL REGISTERS R0-R6:
R0

0000AC04

0000AC14

000

000 0AC2D

0000AC39

000

00000000

SOURCE OPERAND DATA:
OPERAND 1
FFFE4FFF
FFFFFFFF
OPERAND 2
FF
OPERAND 3
00004080
00000000
Example 6-11

Extended Printout
6-14

Rotes for Example 6-11.

This is the first line of the extended typeout. PC is the
location of the test instruction, which can be examined
if the user wants to see the hex code.
PSL is the value of
executed.

the

PSL before

the

instruction

OP CODE is the hex value of the instruction, which in the
example is 74 = EMODD.
REGISTER INDIRECT OPERANDS means that R0 has the address
of operand l; Rl has the address of operand 2; etc.
2.

The INITIAL REGISTERS typeout tells where the operands of
the test instruction were in memory when the instruction
was executed.

These are the actual contents of the addresses pointed to
by the registers listed above (2).
All source (read or modifiable) operands are typed.

Formats:
Byte
Word
Longword
Quadword

xx
xxxx
xxxxxxxx
XXXXXXXX -- Low Address Longword
XXXXXXXX -- High Address Longword

xx, xx, xx, xx, ... ,xx

Strings

Left side of printout is lowest address byte.
Long strings are printed 16 bytes per line and
are continued for as many lines as needed.
In the preceding example we have the following operands. (Refer to
the VAX-11/780 Architecture Handbook or the instruction card for
further help.)
Operand 1
Operand 2
Operand 3

MULR
MULRX
MULD

(R0)
(Rl)
(R2)

Double
Byte
Double

FFFFFFFF FFFE4FFF
FF
00000000 00004080

The 4th and 5th Operands are Destinations:
Operand 4
Operand 5

INT
FRACT

(R3)
(R4)

Long
Double

6.2.7
How To NO-OP a Test Case
If it is necessary to bypass a test case while waiting
hardware ECO or a microcode ECO, refer to Example 6-12.

6-15

for

°'°'
I

08F09D62
08
01
01

2C9
2C9
2C9
2C9
2C9
2C9
2C9
2C9
2C9
2C9
2C9
2CC
2CD
2CE

946
947
948
949
950
951
952
953
954
955

;CASE 105
;SUBD2 INSTRUCTION
;OPERANDS
;SUB: 0
;DIF: 1. 0
;CONDITION CODES
TB I_SUBD2,
.BYTE
.BYTE
.BYTE
.BYTE

Example 6-12

EXP-DIF:
INITIAL: 1111

1. 0

EXPECTED:

0000

CC NZVC, CC 0, 08 012, 08 02, DP 02
I SUBD2, <-C<I_SUBD2>>, <l6*<CC NZVC&l5>+CC 0&15>>
DP Dl2
DP-D2
DP-D2

Case 105 SUBD2

Instruction

Load ESKAX. EXE
Look up the base address of the PSECT <. BLANK .> in the link
map of this program for the module that has the data for the
test case to be No-Oped.
Set the
VALUE) •

console

base

that

value

(i.e.,

Find the TB line of the right test case and examine
sure you are in the right place (Example 6-12).

it to make

Examination of 2C9 location (E 2C9) should give 08F09D62.
Count the number of single bytes following the line that has three
bytes. That would be 3 for this example.
Deposit a new longword, at the address just examined, made up of
the count from the preceding step followed by 03FC.
In Example
examined.

6-12,

D 2C9

303FC,

where

2C9

the

address

Set the relocation register back to zero when finished
R:

6.3

just

(i.e.,

0) •

ESKAX DESCRIPTION

6.3.1
Compatibility Mode Entry/Exit Module (ESKAX02, Test Bl)
This module tests the conditions generated when the central
processor enters and leaves the compatibility mode. The following
conditions and functions are tested.
ESKAX Test 1, Subtest 1 -- This subtest performs iilegal entries
in compatibility mode expecting and checking for reserved operand
faults. The bit settings in the PSL that will cause reserved
operand faults, on an attempt to enter compatibi 1 i ty mode, are
shown in Table 6-3.
Table 6-3

Reserved Operand Faults and PSL Bit Settings
on Compatibility Mode Entry
PSL Bit/s

Condition

DV<7>
FU<6>
IV<S>
IPL<20:16>
CUR MOD<2 5: 24 >
PRV MOD<23:22>
IS<26>
FPD<27>

Nonzero
Nonzero
Nonzero
Nonzero
Not = 3
Not = 3
Nonzero
Nonzero

The conditions in Table 6-3 are tested one at a time.

6-17

The following two examples are typical of ESKAX test 1, subtest:,
error messages.

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 1

ERROR 2

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

21:25:41.22

EXCEPTION PC FROM CM ILLEGAL ENTRY
INCORRECT

VECTOR

TYPE CODE

EXPECTED PC

ACTUAL PC

PSL ENTRY

MNEMONIC

NONE

00007D74

00007D76

83C00080

Example 6-13

********
PASS 1

ESKAX Test 1, Subtest 1, Error 2
9.0

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 1

ERROR 2

HARD ERROR WHILE TESTING CPU:

********

19-JUN-1977

21:25:53.04

EXCEPTION PC FROM CM ILLEGAL ENTRY
INCORRECT

VECTOR

TYPE CODE

EXPECTED PC

ACTUAL PC

PSL ENTRY

MNEMONIC

NON

00007D74

00007D54

83C00040

Example 6-14

ESKAX Test 1, Subtest 1, Error 2

Interpretation of Example 6-13.

1.
2.
3.
4.
5.

18 is the reserved operand fault vector expected.
There is no type code pushed on the stack.
The state of the PSL to cause the fault was 83C00080.
DV is the PSL bit that was nonzero (Table 6-3).
EXPECTED and ACTUAL PCs are self-explanatory.

ESKAX Test

I, Subtest 2 -- Compatibi 1 i ty mode trap instruct ions
upon a valid entry into compatibility mode (Table 6-4).

Table 6-4

Compatibility Mode Trap Instructions
Op code

Mnemonic

00000 3

BPI

000004

!OT

104000

EMT+0

104400

TRAP+0
6-18

-- Compatibility mode reserved instructions
into compatibility mode {Table 6-5).

Table 6-5

upon

valid

entry

Compatibility Mode Reserved Instructions
Mnemonic
000000

HALT

000001

WAIT

00000 5

RESET

000230

SPL

00640 0

MARK

075000

FADD

075010

FSUB

075020

FMUL

075030

FDIV

170000

FPll

Typical Error Messages

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 2

ERROR 3

9.0

********

19-JUN-1977

21:29:30.40

HARD ERROR WHILE TESTING CPU: EXCEPTION PSL FROM COMPATIBILITY
MODE TRAP INCORRECT
VECTOR

TYPE CODE

EXPECTED PSL

ACTUAL PSL

TRAP

MNEMONIC

83C00000

8 3C00002

0003

BPT

Example 6-15

ESKAX Test 1, Subtest 2, Error 3

6-19

********
PASS 1

9.0

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 2

ERROR 3

HARD ERROR WHILE TESTING CPU:

********

19-JUN-1977

21:29:42.21

EXCEPTION PSL FROM COMPATIBILITY

MODE TRAP INCORRECT
VECTOR

TYPE CODE

EXPECTED PSL

ACTUAL PSL

TRAP

MNEMONIC

83C00000

83C00002

0004

IOT

Example 6-16

********
PASS 1

ESKAX Test 1, Subtest 2, Error 3
9.0

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 2

ERROR 3

HARD ERROR WHILE TESTING CPU:

********

19-JUN-1977

21:29:54.02

EXCEPTION PSL FROM COMPATIBILITY

MODE TRAP INCORRECT
VECTOR

TYPE CODE

EXPECTED PSL

ACTUAL SPL

TRAP

MNEMONIC

83C00000

83C00002

8800

EMT

Example 6-17

ESKAX Test 1, Subtest 2, Error 3

Interpretation of Example 6-16
1.

30 is the compatibility mode TRAP vector expected.

A type code of 2 is pushed on the stack.

Referencing Chapter 6 of the system reference manual
would show that a typecode of 2 indicates an IOT fault.

!OT is shown as well as the hex equivalent of the octal
code (Table 6-4).

EXPECTED and ACTUAL PSLs are self-explanatory.

Subtest 3 -- This subtest tests the T-bit trap by having the T-bit
(PSL<4>) set upon entry into compatibility mode:
a.
b.

for an instruction that does not trap
for an instruction that does trap.
Both a and
NATIVE mode.

NOTE
cases are

6-20

serviced

Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 3

ERROR 4

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

A T-BIT TRAP NOT TAKEN

EXPECTED EXC

VECTOR

TYPE CODE

MNEMONIC

0BC0

NONE

TST R0

Example 6-18

21:32:06.80

ESKAX Test 1, Subtest 3, Error 4

Interpretation of Example 6-18 (this printout is for Case B):
1.

This instruction, which was to execute and then take a
T-bit trap, was 'TST R0' with TRACE PENDING prior to its
execution (PSL<TP>).

The hex equivalent of the octal code for 'TST R0' is BC0.

30 is the vector expected to field the T-bit trap.

No type code is pushed on the stack.

Subtest 4 -- This subtest performs an RTT/RTI instruction with the
T-bi t set in the PSW image on the stack, which is to be popped
from the stack by the RTT/RTI.
Typical Error Messages

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 4

ERROR 3

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

21:33:43.60

PC FROM RTT TRACE TRAP

INCORRECT
VECTOR

TYPE CODE

EXPECTED PC

ACTUAL PC

TRAP

MNEMONIC

NONE

00008508

00008408

000 6

RTT

Example 6-19

ESKAX Test 1, Subtest 4, Error 3

6-21

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 4

ERROR 3

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

21:33:54.70

PC FROM RT! TRACE TRAP

INCORRECT
VECTOR

TYPE CODE

EXPECTED PC

ACTUAL PC

TRAP

MNEMONIC

NONE

00008508

00008408

0002

RT!

Example 6-20

ESKAX Test 1, Subtest 4, Error 3

Interpretation of Example 6-19
1.
2.
3.
4.
5.

30 is the vector expected to field the T-bit trap.
No type code is pushed on the stack.
The RTT instruction was under test.
The hex equivalent of the octal code for RTT is 6.
EXPECTED and ACTUAL PCs are self-explanatory.

Subtest 5 -- This subtest performs checking of Odd Address errors
while in compatibility mode. This is accomplished by executing a
PDP-11 MOV instruction with unaligned SRC and DST operands.
Typical Error Messages

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 5

ERROR 4

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

21:35:17.19

ODD ADDRESS TRAP CAUSED

UNALIGNED SOURCE CONTENTS CHANGE
VECTOR

TYPE CODE

EXPECTED VAL

ACTUAL VAL

TRAP

MNEMONIC

000A

000E

17DF

UNALIGNED

Example 6-21

********
PASS 1

ESKAX Test 1, Subtest 5, Error 4

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 5

ERROR 4

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

21:35:29.58

ODD ADDRESS TRAP CAUSED

UNALIGNED SOURCE CONTENTS CHANGE
VECTOR

TYPE CODE

EXPECTED VAL

ACTUAL VAL

TRAP

MNEMONIC

000A

000E

17DF

UNALIGNED
DST

Example 6-22

ESKAX Test 1, Subtest 5, Error 4
6-22

Interpretation of Example 6-22
1.

30 is the compatibility mode TRAP vector expected.

A type code of 6 is pushed on the stack.

The position of the
caused the failure.

The hex equivalent of the octal code for the instruction
under test is 17DF (this translates to 013737 in PDP-11
code).

EXPECTED and ACTUAL VALUES are self-explanatory.

destination

address

boundary

NOTE
On an Odd Address trap neither SRC nor
DST initial values should change, since
the
instruction should not go to
completion.
Subtest 6
This subtest performs checking
instructions with a register destination, i.e.,

illegal

JMP R4 or
JSR R4, RS
Typical Error Messages

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 6

ERROR 3

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

21:36:32.03

PSL FROM ILLEGAL INSTRUCTION

TRAP INCORRECT
VECTOR

TYPE CODE

EXPECTED PSL

ACTUAL PSL

TRAP

MNEMONIC

83C00000

83D00000

0044

JMP R4

Example 6-23

CPU CLUSTER EXERCISER

********
PASS 1

ESKAX Test 1, Subtest 6, Error 3

TEST 1

SUBTEST 6

ERROR 3

HARD ERROR WHILE TESTING CPU:

9.0

********

19-JUN-1977

21:36:43.64

PSL FROM ILLEGAL INSTRUCTION

TRAP INCORRECT
VECTOR

TYPE CODE

EXPECTED PSL

ACTUAL PSL

TRAP

MNEMONIC

83C00000

83000000

090S

JSR (RS DST)

Example 6-24

ESKAX Test 1, Subtest 6, Error 3
6-23

Interpretation of Example 6-24
1.

30 is the vector expected to field the TRAP.

A type code of 5 is pushed on the stack.

The instruction that failed was the JSR R4, RS.

The hex equivalent for the octal code of this instruction
is 0905.

EXPECTED and ACTUAL PSLs are self-explanatory.

ESKAX02 (test 1) is executed in the user mode for test purposes.
However, the module is serviced in the kernel mode, and control is
returned to the kernel mode on completion of the module.
The operator should note that testing of the T-bit operation with
servicing done in the compatibility mode has not been covered.

6-24

6.3.2
First Part Done Test (ESKAX94, Test 2)
First Part Done (FPO) is the name of 'bit 27 in the PSL. It
provides a facility for interrupting certain potentially long
executing instructions during processing and resuming them later.
Only a few instructions are interruptable in this sense. Most
fnstructions acknowledge interrupts before their execution, or
acknowledge them in mid-operation by backing up to the beg inning
and pretending that they have not yet started. A few instructions,
however, are potentially so lengthy that this is not feasible.
These are the character and dee imal string instructions, POLYF,
POLYD, and CRC. Each of these instructions writes a control block
into the general registers. Should an interrupt be requested
during processing, the current state of the operation (i.e., what
it is doing and how far it has gotten) can be saved in this
control block to be retrieved after the interrupt is processed.
The instruction then sets FPO in the PSL, and acknowledges the
interrupt. Upon return from the interrupt, the FPD bit is set in
the PSL, so that rather than restarting, the instruction restores
its state from the point at which it was interrupted.
6.3.2.1 Possible First Part Done Failures -- The microcode
implementing the FPD capability must be able to correctly save and
restore state anywhere it does a memory reference (which may cause
a fault) and anywhere it checks for interrupts. The state of the
operatioh in some cases is complex, and it is possible that the
microcode does not save or restore everything correctly. If the
instruction is later resumed, the state of the machine e.g., in
the form of contents of general registers, may well have been
changed by the instructions executed in the interim, and will thus
be incorrect. This will cause unpredictable results, most likely
in the form of incorrect data written, wrong lengths and wrong
condition codes, and will be easy to detect.
The instructions may also fail by saving state (perhaps correctly)
and failing to set FPD. This would normally appear when modified
reg i st er s a r e used a s a r g um en ts i n the rest a rt in g o f the
instruction. This condition will be detected in the test by
checking in the interrupt routine to make certain that if FPD is
still clear, the original arguments are unchanged.
6.3.2.2 First Part Done Test Procedures -- The interval timer is
used to generate interrupts during the
testing of each
instruction, in order to check the microcode and the taking of
interrupts. Al though each instruction is interrupted constantly
during execution, it is eventually run to completion.
After having been tested with interrupts, the instruction's
ability to handle page faults is tested. An instruction may have
up to six operands; twelve pages are set up to hold them, allowing
each operand to be placed near an independent page boundary. When
the instruction beg ins execution, each page is invalid. As it
attempts to access its operands, the instruction is repeatedly

6-25

faulted. Each fault validates the page referenced, so that the
instruction progresses, but this alone does not ensure that it is
tested fully. As each page is referenced (and faulted) the first
time, all the other pages holding operands are made invalid. This
process tests all the cases. Since each page has a first reference
only once, the test instruction manages to finish.
As an example, consider the testing of an instruction with two
string operands and one non-string operand in which the
instruction accesses the non-string operand first, and then
processes the strings (e.g., CMP3). First, the non-string operand
is referenced, faulting the page containing it. Upon restart, the
instruction fetches the non-string operand without problem, and
begins processing the strings. Since each operand is located just
before a page boundary, the strings will cross the boundaries. As
the instruction progresses, it will attempt to reference the first
page of the first operand, the first page of the second operand,
the second page of the first operand, and the second page of the
second operand. Because faulting in a page for the first time
signals the test to invalidate all the other pages, however, the
string of references and validations proceeds as shown in Table
6-6.
Table 6-6

Page Faulting with First Part Done

Page 1

Page 2

Page 3

Page 4

I
I
I
I
I
I
I
FAULT

I
I
I
I
I
I
I

FAULT

v
v
I

FAULT

v
v
I
I
I
I

v
v
v
v

I
I
I
I

I
I
FAULT

v
v
v
v

;All the pages start invalid.
;The first page is faulted
;and is made valid.
;The first page of operand 2 is
;faulted in, and the rest out.
; Page 1 is refaulted, and page
;3 is left valid.
;String 1 processing reaches
;page 2, all others faulted.
; Page 1 is not needed now, but
;page 3 still is needed.
;String 2 reaches its second
;page
;faulting page 4 for first
;time.
; Page 2 is still needed, and
;is faulted back in.
;The instruction is completed.

FAULT

v
v

I
FAULT

FAULT

I
I

v
v
v

The first part done test uses the CITS routines to help set
e x e c u t e , and ch e c k the r e s u 1 t s o f i n s t r u c t i o n t e s ts •
instructions to test, and the data with which to test them,
stored in a table. The table entries are of variable length,
they begin as shown in Table 6-7.

6-26

up,
Th e
are
and

Table 6-7
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE

First Part Done Test Table Entries

;the op code of the test instruction
;the op _code's complement
;initial condition codes
;resultant condition codes
;operand specifiers

The faulting section uses the Interface Data Block (IDB) to
communicate with the exception and interrupt handler. The format
of the IDB is shown in Table 6-8.
Table 6-8

First Part Done IDB Format

Except ion and
Subtype

T-Bit
Count

State
Bits

PSL of exception
PC of exception
PSL of latest T-bit trap
PC of latest T-bit trap
User service routine address
Number of arguments (zero)
The service routine address points to the code that implements the
faulting algorithm. The exception type and subtype are loaded with
the values for translation-not-valid faults.
This test also interfaces with the CITS routine through a
Control Block (TCB). The TCB format is shown in Table 6-9.
Table 6-9

First Part Done TCB General Format

Current Test Table Address
Unused

Exception

Subtype

Operand 1 address, or

"
"
Operand 3 address, or
"
Operand 4 address, or
"
Operand 5 address, or
"
Operand
Operand 2 address, or

6 address, or

6-27

T-bit trap

Test

The current test
instructions.
The TCB passed
Table 6-10.

table

address

points

to CITS DECODE and

Table 6-10

into

the

table

to CITS REDECODE

test

is shown

First Part Done TCB Passed to CITS DECODE

TCB:
TCB INST ADDR:
TCB T BIT:
TCB-SUBTYPE:
TCB-EXCEPTION:

• LONG
.BYTE
.BYTE
.BYTE
.BYTE
.BLKL

TCB OPERANDS:

;current test table address
;trace trap expected flag
;exception subtype
;expected exception vector
;unused
;optional operand addresses

0
0
0
0

0
6

Typical Error Message

********
PASS 1

********

CPU CLUSTER EXERCISER -- 9.0
TEST 2

HARD ERROR
occurred.

SUBTEST 0

WHILE

TESTING

ERROR 212
CPU:

19-JUN-1977

unexpected

21:41:22.03
type

Fault code

Referenced address

PSL

00000000

0001F7F8

00003DD0

000000EB

Table number

Test case

TCB's address

Test table address

Current entry address

00008F9C

00000A7C

Example 6-25

fault

ESKAX Test 2, Subtest 0, Error 212

Interpretation of Example 6-25
The printout is representative of the first part done test, which
interfaces to the CITS portion of the program for its data pool as
follows.
1.

This test interfaces with CITS
format is shown in Table 6-10.

through

the

TCB

whose

In this example, the first address of the TCB is 8F9C.
The current test table address (which
longword of the TCB) is given as A7C.
2.

The starting
A7C.

address

of the
6-28

the

first

test table within CITS

CITS contains a number of tables; each table contains a
number of cases (or distinct pieces of data) where:
Table 1
Table 2
Table 3
Table 4

represents
represents
represents
represents

BASE FP instructions
DECIMAL instructions
EDIT PC instructions
FPA instructions

A summary of the information
First Part Done Test follows.

presented

far

We are using Table 1 from CITS for our data.

The starting address of this table is A7C.

We are using DATA CASE 1.

The address for DATA CASE 1 is A7C.

The address of the CONTROL BLOCK guiding this test
execution is 8F9C (whose format is shown above in
Table 6-10).

Examination of the next n locations starting with the
CURRENT ENTRY ADDRESS (in this case A7C) will give
information concerning the instruction under test as
follows:
1st byte
2nd byte
3rd byte
4th byte

is
is
is
is

the
the
the
the

op code of the test instruction.
op code's complement.
INITIAL condition code (N,Z,V,C).
RESULTANT condition code (N,Z,V,C).

The next n bytes represent operand specifiers.
The number of operand specifiers depends on
instruction under test.
4.

the

The starting address of the area where the test
instruction is placed {residing) while undergoing test is
the PC of 3DD0.

6-29

A Second Error Message

********
PASS 1

CPU CLUSTER EXERCISER -- 9.0
TEST 2

SUBTEST 0

ERROR 213

HARD ERROR WHILE TESTING CPU:

********

19-JUN-1977

21:41:22.03

Page fault on non-test instruction.

Fault Code

Reference address

PSL

00000000

0001FFF8

00003000

000000EB

Table number

Test case

TCB's address

Test table address

Current entry address

00008F9C

00000A7C

Example 6-26

ESKAX Test 2, Subtest 0, Error 213

Interpretation of Example 6-26
The REFERENCE ADDRESS of 1FFF8 represents the address which caused
the FAULT CODE of 0.
The breakdown of the FAULT CODE is as follows:
Bit Position

Meaning
0 =
1 =

translation not valid
access control violation

1 =

fault occurred during virtual reference to the
PTE of the stored process virtual address

0 =
1 =

read access
write or modify access

The interrupts portion of the test begins by setting up the test
instruction and data, using the CITS routines named CITS DECODE
and CITS SETUP.
CITS SETUP returns with the PC and initial PSL of the test
instruction on the stack. The test saves a copy of the test
instruction's PC and general registers, so that its progress may
be observed. Then the test initializes the interval timer service
routine.

6-30

It then sets up a timer interrupt and executes an REI to the test
instruction, which is interrupted immediately.
Since the state of the instruction is contained in the registers,
if they are unchanged since the previous interrupt, the
instruction has not progressed. This condition results from
interrupting too soon. In this case, the interval timer is
increased, and the test instruction is resumed.
In the other case, when the general registers have changed,
instruction has progressed.

the

Next, a divide-packed instruction is executed in an attempt to
modify the state of any internal registers that might be used by
the instruction under test. The timer is then set up for the new
wait time, started, and the test instruction is resumed.
When the test instruction has been
checked and any errors are reported.

completed,

the

results

are

Once interrupts and faults have been tried, the next entry in the
test instruction table is selected, and the testing of that
instruction begins.
There are four classes of errors that may occur.
Class 1

Unexpected exceptions or interrupts.

Class 2
state

Exception or interrupt identifier reports, which simply

ERROR IN TEST CASE NN.
These occur when an exception or interrupt occurs during the
testing of an instruction, and they are immediately followed by
the exception report. They exist solely to inform the operator of
the test case in which the exception occurred.
Class 3 -- Instruction test errors describe incorrect results from
instruction testing. The instructions tested are a subset of those
tested in ESRAY05 TEST04 and ESKAY06 TEST05, so that the
instruction test errors are identical between those tests and this
test, ESKAX04 TEST02. This data is in module ESKAX03 FPO DATA.

6-31

Class 4 -6-27) •

These

errors

are

first

part done

specific

(Example

They have error numbers 200 through 209. Each reports error
specific information, the table number, and the test case number.
The interpretation of table numbers is as follows:
Table Number

Meaning

Floating-point test taQle
Decimal string test table
EDITPC test table
Floating-point test table
(Executed with FPA enabled
exists)

3
4

The test case number
indicate a single test.

*********
PASS 1

indexes

into

the

CPU CLUSTER EXERCISER -- 9.0

TEST 2

SUBTEST 0

appropriate

FPA

table

********

ERROR 207

HARD ERROR WHILE TESTING CPU:

EXPECTED
OCCUR.

TIMER

INTERRUPTS

DIDN'T

VALUE PASSES
-30
TABLE NUMBER

TEST CASE

115

TCB'S ADDRESS

TEST TABLE ADDRESS

CURRENT ENTRY ADDRESS

18E0

9F6

Example 6-27

ESKAX Test 2, Subtest 0, Error 207

6.3.3
SBI Verification Module (ESKAXSS, Test 3)
The SB! verification test is designed to exercise and partially
diagnose faults on the SB I nexus connected to it. Error reports
will differentiate between faults on the SB! proper and faults
caused by a nexus. The error printouts will serve as guides to
selection of the appropriate repair level diagnostic to further
isolate the problem.

6-32

With the exception of the interactive mode setup subtest, errors
will be reproducible via looping. For interactive mode, due to the
asynchronous operation of the exerciser, only errors introduced by
interrupts from the interval timer. are guaranteed to be
rep rod uc i ble.
Note that failing devices are deselected from further testing at
the point of failure. This means that if an MBA or UBA fails in a
test before MBE or UBE checkout, the MBEs or UBEs attached are not
checked for the failing MBA or UBA.
The SBI verification test is composed of the following parts.
SBI checkout -- Verifies configuration register of each
nexus that can be accessed.
UBA checkout -- Verifies that each selected UBA on the
SBI can sustain data transfers without incurring errors
and that interrupts occur at the proper BR level.
MBA checkout -- Verifies that each selected MBA on the
SBI can sustain data transfers without incurring errors
and that interrupts occur at the proper BR level.
SBI interaction -- Verifies that all UBAs are capable of
block data transfers in a controlled sequential mode of
operation.
UBE checkout - - Ve r i f i es th a t a 11 ex i st in g UBE s -a re
capable of sustaining data transfers and interrupting on
completion without errors.
MBE checkout -- Verifies that all existing MBEs for
selected MBAs are capable of sustaining data transfers
and interrupting on completion without errors.
6.3.3.1 SBI Checkout Subtest -- The SBI checkout subtest will
perform reads and writes to the configuration register of each
nexus on the SBI as defined by the hardware P-Table. This subtest
will set up the Hardware Interrupt Request Table (HIRT), which
will contain an entry for each UBA and/or MBA responding to a read
of its configuration/status register. This table will be used by
all subtests within the SBI verification test. A nexus that does
not respond will not be entered into the HIRT and, therefore, will
not be used in the following subtests. No response from a ~exus is
treated as an error.

6-33

The SB! checkout subtest uses the CPU silo comparator register to
check the validity of the commands and responses from the
receiving nexus on the SBI.
The primary purpose of this subtest is to provide the field user
with a detailed check of the SBI. It will isolate faults in such a
manner that the error information printed will aid the user in the
selection of the proper diagnostic, which may then be run to
further isolate the fault.
Si lo Com pa re Servicing
The silo com pa re service
routine will read back the SBI silo and compare the
contents with the arguments supplied
in the IDB
(interface data block) • Nul 1 eye les between command
issue and read reply are checked for continuity of
function, i.e., TR lines not continually asserted. No
checking will be made for the number of null cycles.
On completion of the silo read back, the fault bit in the CPU SBI
status register will be checked for clear. The error flag will be
set and the appropriate information will be placed on the error
stack if it is set. The fault bit will be reset if set. The
interrupt on silo compare bit will be cleared and the SBI silo
compare register will be cleared.
A return is then made to the point of invocation of the interrupt
causing this routine to be executed.

6-34

6.3.3.2 UBA Checkout Subtest -- This subtest will only be run for
UBAs that exist in the HIRT and have been qualified by the SB!
checkout subtest.
Each UBA will be set up to operate in a wraparound mode so that
access from the SB! to Unibus memory space will be mapped into SB!
memory space.
This subtest will check the following UBA capabilities.
1.

DDP and BDPl data paths are operational.

Interrupts can be initiated by the adapter and result in
the correct vector being accessed.

The map registers can be accessed and used correctly.

Purging operates correctly.

A read to nonexistent Unibus memory
correct error sequence and interrupt.

space

causes

the

The subtest will autosi ze the Unibus memory and set the map
register disable portion of the Unibus Adapter Control Register
(UACR) for use by other subtests within the SB! verification t~st.
Faults detected within this subtest will cause the UBA under test
to be disqualified from further use by any other subtest within
the SBI verification test.
UBA Interrupt Servicing -- Interrupts
Adapter are serviced by this routine.

generated

the

Unibus

The routine will compare the configuration register and the Unibus
Adapter Status Register (UASR) with arguments supplied in the
Service Data Block (SDB). If there are any differences, they will
be pushed on the error stack and the error flag will be set. For
an invalid map register type interrupt, the failed mapped entry
register will be compared with the SDB entry. Also, for a Unibus
SSYN timeout, the failed Unibus address register will be compared
with the SDB entry.
The AEIL (Additional Exception or Interrupt Longword) is used as
the transfer vehicle to indicate to the interrupted program the
IPL level at which the interrupt occurred.
6.3.3.3 MBA Checkout Subtest - This subtest is run only on MBAs
that exist in the HIRT and have been qualified by the SBI checkout
subtest.
Each MBA is set up to operate in maintenance mode.

6-35

This subtest checks the following MBA capabilities.
1.

Initialization
interrupts.

clears

registers

and

does

not

cause

DT BUSY can be set and causes no interrupts.

PGE can be set and causes an interrupt.

Read and write transfers operate correctly; on completion
of read data transfer, DONE is set and causes an
interrupt.

Faults detected within this subtest cause the MBA under test to be
disqualified from further use by any other subtest within the SBI
verification test.
MBA Interrupt Servicing
Interrupts
adapter are serviced by this routine.
Th i s rout i n e com pa res
supplied in the SOB.

the

status

generated

reg i st e r

by the

w i th

Massbus
a r g um en t

If there are any differences, the SOB + 2 will be set to indicate
error and the error information will be put into the appropriate
slots in the Master Control Space (MCS).
6.3.3.4 SBI Interaction Subtest -- After the UBAs are set up for
wraparound operation, the following data transfer types are
initiated.
1.
2.
3.
4.
5.

read word
write byte
write word
modify byte
modify word

6.3.3.5 UBE Checkout Subtest
This subtest determines the
number and location of Unibus exercisers for each Unibus adapter
and checks each as it is found. If no faults are detected, the UBE
is entered in the HIRT and the qualify bit will be set.
Only qualified UBAs are used during this subtest. If none exists,
the subtest will be skipped.
UBAs are set up with two map registers pointing to SBI memory
space. One map uses the Direct Data Path (DP0) and the other uses
buffered Data Path One (DPl). All interrupts are enabled.
Autosizing
exerciser.

used

determine

6-36

the

location

Unibus

Each exerciser is checked for the following two capabilities:
1.

ability to execute DATO, DATI functions,

ability to interrupt at BR levels 4 through 7 following a
function.

If any of the above conditions is not met, the UBE is not entered
in the HIRT.
UBE Interrupt Servicing -- The contents of the BRRVR and UBA base
address are passed into the test from the master except ion and
interrupt handler. In addition, the routine performs the following
four functions.
1.

If bit 31 is set in the BRRVR value read, then call the
UBA service routine.

Derive the UBE address from the vector
low word of the BRRVR value.

Examine bit 15 (error bit) of CRl. If the bit is set,
push the error type information and contents of the
control registers, CRl and CR2, on the error stack and
set the error flag. Clear the error bit.

Return.

supplied

in the

6.3.3.6 MBE Checkout Subtest -- This subtest determines if an MBE
is present for each MBA that has been previously qualified.
Each exerciser will be checked for the following:
1.
2.

read transfers
write transfers.

Additionally, the MBA is checked for whether
1.
2.

Attention can be set which causes an interrupt.
Massbus exception can be set which causes an interrupt.

If any of the above conditions is not met, the MBE is not entered
in the HIRT.

6-37

Typical Error Messages for the SBI Verification Module:

********
PASS 1

CPU CLUSTER EXERCISER
TEST 3

SUBTEST 2

9.0

ERROR 10

********

19-JUN-1977

21:53:25.06

HARD ERROR WHILE TESTING UBA: INVALIDATED MAP REGISTER ACCESS
ERROR: DESTINATION OVERWRITTEN
ADD ACCESS

NEXUS ADD

MR ADD

FUNC

EXP DATA

ACT DATA

201009F8

60006000

60006810

WRITE

25255252

24255252

Example 6-28

********
PASS 1

ESKAX Test 3, Subtest 2, Error 10
9.0

CPU CLUSTER EXERCISER
TEST 3

SUBTEST 3

ERROR 4

HARD ERROR WHILE TESTING MBA0:

********

19-JUN-1977

21:57:03.12

MBA WRITE

ERROR: RESULT
ADD ACCESS

NEXUS ADD

EXP DATA

ACT DATA

6001040

60010000

00002000

00002400

Example 6-29

********
PASS 1

ESKAX Test 3, Subtest 3, Error 4
9.0

CPU CLUSTER EXERCISER
TEST 3

SUBTEST 3

ERROR 4

********

19-JUN-1977

21:57:13.07

HARD ERROR WHILE TESTING MBAl: MBA WRITE
ERROR: RESULT
ADD ACCESS

NEXUS ADD

EXP DATA

ACT DATA

60012400

60012000

00002000

00003000

Example 6-30

ESKAX Test 3, Subtest ·3, Error 4

6-38

Interpretation of Example 6-28
These printouts are typical of ESKAX Test 2, where:
1.

The nexus address is 6"00600 0. A nexus is defined as a
physical connection to the SBI. In this case the nexus is
the UBA.

Since the SBI deals in 30-bi t addresses, 18-bi t Unibus
addresses must be translated to 30-bi t SBI addresses.
This function is performed by the Unibus adapter through
one of the 496 UBA memory map registers, as shown in
Table 6-11.
Table 6-11

Unibus Adapter Map Register Address Offsets

Unibus Memory Page

Off set from the
UBA Base Address
800
80 4
808
80C
810

0
1
2
3

495

FBC
FC0
Reserved
FFC

In the example given, the MR ADDRESS is 60006810. The underlined
portion of the address (using Table 6-11) tells us that we are
working with the map register for Unibus memory, page 4.
One Unibus memory page equals 512 bytes.
3.

The function performed was a write.

Each UBA has an associated Unibus address space with a
physical starting address as follows:

UBA Number

Physical Starting Address

20100000
20140000
20180000
201C0000

1
2
3

From Example 6-28 the ADDRESS ACCESSED is 201009F8, indicating
UBA 0 under test.
5.
6.3.3.7

EXPECTED and ACTUAL DATA are self-explanatory.
Memory Verify (ESKAX96_TEST94) -- Not yet implemented.
6-39

6.4

ESKAY

6.4.1
Interval Timer and Day Clock Verification Module
(ESKAY02 TEST01)
This module tests the interval timer and the day clock. The
inte·rval timer is used extensively throughout the cluster
exerciser package during interactive operation.
6.4.1.1

Interval Timer Functions

Subtest 1
The interrupt enable
register can be set and cleared.

bit

the

control

status

Typical Error Message
....:...

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

HARD ERROR
CLEARED

SUBTEST 1

WHILE

TESTING

Example 6-31

9.0

ERROR 2
CPU:

********

18-JUN-1977
INTERRUPT

06:38:05.10

ENABLE

BIT

CAN'T

ESKAY Test 1, Subtest 1, Error 2

Subtest 2 -- This subtest checks that the transfer bit (bit 04) in
the control status register can be set, thus activiating a
transfer of the contents of the next interval register to the
current interval register.
A check that the transfer bit is read as 0 is also performed.
Typical Error Messages

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 2

ERROR 1

9.0

********

18-JUN-1977

6:39:58.61

HARD ERROR WHILE TESTING CPU: XFER BIT STUCK AT 1
Example 6-32

********
PASS 1

ESKAY Test 1, Subtest 2, Error 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 2

ERROR 2

9.0

********

18-JUN-1977

06:39:58.61

HARD ERROR WHILE TESTING CPU: XFER FROM NEXT INTERVAL TO INTERVAL
COUNT INCORRECT
Example 6-33

ESKAY Test 1, Subtest 2, Error 2

6-40

Subtest 3 -- The single clock bit {bit 5) in the control status
register can be set, thus causing the current interval register to
advance by one.
The test also checks that the single clock bit is read as zero.

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 3

HARD ERROR WHILE
PROPERLY

ERROR 2

TESTING CPU:

Example 6-34

9.0

********

18-JUN-1977

06:43:14.82

SINGLE CLOCK BIT NOT FUNCTIONING

ESKAY Test 1, Subtest 3, Error 2

Subtest 4 -- This test floats a one through a field of zeros in
the current interval register. The medium of transfer is the
read/write unit comprised of the current interval register and the
next interval register, respectively. Since the next interval
register is write-only, only the current interval register is
checked at the end of the transfer. If a failure is detected in
the current interval register, it is possible that the failure
originated in the next interval register.
Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 4

ERROR 1

9.0

********

18-JUN-1977

06:44:31.89

HARD ERROR WHILE TESTING CPU: ADJACENT PIN STICKING IN INTERVAL
COUNT REGISTER
EXPECTED RESULT

RECEIVED RESULT

ENTRY VALUE

00000004

00000006

00000004

Example 6-35

ESKAY Test 1, Subtest 4, Error 1

Interpretation
1.

The ENTRY VALUE of 00000004 represents the value loaded
into the next interval register {hex 19).

The EXPECTED RESULT of 00000004 represents what the
content of the current interval register {hex lA) should
be after the transfer is complete.

The RECEIVED RESULT is self-explanatory.
6-41

Subtest 5 -- This subtest checks the carry bi ts of the current
interval register. This is accomplished by preloading the next
interval register with the value to force the carry, transferring
this to the next interval register, and then single-clocking to
force the carry expected.
Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 5

ERROR 1

HARD ERROR WHILE TESTING
PROCEEDING PROPERLY

CPU:

9.0

********

18-JUN-1977
INTERVAL

TIMER

EXPECTED RESULT

RECEIVED RESULT

ENTRY VALUE

00000002

00000001

Example 6-36

********
PASS 1

SUBTEST 5

ERROR 1

HARD ERROR WHILE TESTING
PROCEEDING PROPERLY

CPU:

9.0

NOT

********

18-JUN-1977
INTERVAL

06:45:50.65

TIMER

EXPECTED RESULT

RECEIVED RESULT

ENTRY VALUE

00000004

00000003

Example 6-37

COUNTING

ESKAY Test 1, Subtest 5, Error 1

CPU CLUSTER EXERCISER
TEST 1

06:45:50.65

COUNTING

NOT

ESKAY Test 1, Subtest 5, Error 1

Interpretation of Example 6-36
1.

The ENTRY VALUE of 00000001 represents the value loaded
into the next interval register (hex 19).

The EXPECTED RESULT of 00000002 represents what the
content of the current interval register (hex lA) should
be after the transfer is complete and the single clock
bit has been ticked once.

The RECEIVED RESULT is self-explanatory.

6-42

Subtest 6 -- This subtest checks that the error bit in the control
status register will set in the case of a current interval
register overflow occurrence before a previous interrupt has been
serviced.
The error messages are self-explanatory.

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

HARD ERROR
OVERFLOW

SUBTEST 6

WHILE

TESTING

Example 6-38

********
PASS 1

ERROR 1
CPU:

********

18-JUN-1977
INTERRUPT

06:53:13.11

REQUEST

NOT

SET

ESKAY Test 1, Subtest 6, Error 1

CPU CLUSTER EXERCISER
TEST 1

9.0

SUBTEST 6

ERROR 2

9.0

********

18-JUN-1977

06:53:13.11

HARD ERROR WHILE TESTING CPU: ERR NOT SET FROM UNSERVICED OVERFLOW
Example 6-39

ESKAY Test 1, Subtest 6, Error 2

Subtest 7 -- This subtest checks the run bit of the control status
register with the interrupt enable bit not set (i.e., a check of
no interrupt capability).
Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 7

ERROR 3

9.0

********

18-JUN-1977

06:53:13.11

HARD ERROR WHILE TESTING CPU: ERR BIT SET -- SHOULD NOT BE
Example 6-40

ESKAY Test 1, Subtest 7, Error 3

Subtest 8 -- This subtest checks the run bit of the control status
register with the interrupt enable bit set, a check of interrupt
capability. A check is also made to verify that the interrupt is
enabled at IPL 24 (hex 18).

~43

Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 8

ERROR 2

9.0

********

18-JUN-1977

06:55:56.48

HARD ERROR WHILE TESTING CPU: INTERRUPT OCCURRED AT OTHER THAN IPL
24
IPL WAS 18
Example 6-41

ESKAY Test 1, Subtest 8, Error 2

Interpretation of Example 6-41
1.

The IPL WAS would indicate at what IPL
interrupt did occur (if other than IPL 24).

level

the

6.4.1.2 Day Clock Function
Subtest 9 -- This subtest checks the ability of the time of day
register to advance from a known state, given 20 ms to do so.
Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER
TEST 1

SUBTEST 9

ERROR 1

9.0

********

18-JUN-1977

06:58:26.79

HARD ERROR WHILE TESTING CPU: TIME OF DAY CLOCK NOT INCREMENTING
Example 6-42

ESKAY Test 1, Subtest 9, Error 1

Subtest 10 -- This subtest checks the ability of the time of day
register to accept a back-to-back loading of two different and
unique values.
Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER -- 9.0
TEST 1

SUBTEST 10

ERROR 2

********

18-JUN-1977

06:59:43.78

HARD ERROR WHILE TESTING CPU: DOUBLE LOADING OF TIME OF DAY NOT
CORRECT
EXPECTED RESULT

RECEIVED RESULT

!ST LOAD

2ND LOAD

AAAAAAAC

AAAAAAAA

55555555

AAAAAAAA

Example 6-43

ESKAY Test 1, Subtest 10, Error 2
6-44

Subtest 11 -- This subtest checks for any stuck-at-zero bits in
the time of day register.
Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER -- 9.0
TEST 1

SUBTEST 11

ERROR 1

********

18-JUN-1977

07:00:30.34

HARD ERROR WHILE TESTING CPU: ADJACENT PIN STICKING IN TIME OF DAY
REGISTER
EXPECTED RESULT

RECEIVED RESULT

ENTRY VALUE

FFFFFFFE

FFFFFFFF

FFFFFFFD

Example 6-44

ESKAY Test 1, Subtest 11, Error 1

Subtest 12 -- This subtest checks the Carry bits of the time of
day register. This is accomplished by preloading the time of day
register with the value to force the Carry, and then expecting a
Carry bit in approximately 14--15 ms.

********
PASS 1

CPU CLUSTER EXERCISER -- 9.0
TEST 1

SUBTEST 12

ERROR 2

HARD ERROR WHILE TESTING CPU:

********

18-JUN-1977

TIME OF DAY COUNTING NOT PROCEEDING
PROPERLY

EXPECTED RESULT

RECEIVED RESULT

ENTRY VALUE

00000002

00000001

Example 6-45

07:05:02.22

ESKAY Test 1, Subtest 12, Error 2

Interpretation of Example 6-45
1.

The ENTRY VALUE of 00000001 is what is initially loaded
into the time of day register.

The EXPECTED RESULT of 00000002 is the final value
expected to be in the time of day register approximately
14 ms after the initial load.

The RECEIVED RESULT is self-explanatory.

In addition, the test checks for stuck-at-zero bits in the time of
day register.

6-45

6.4.2
Arithmetic, Logic, and Field Instruction Test Module
(ESKAY03, Test 02)
This module tests the integer arithmetic, logical, and field
instruction microcode and associated hardware. CITS performs all
of the functional control, building expected data patterns,
executing the instructions to be tested, and checking the results.
The following two printouts are typical of error
from this test.
a.
b.

One shows a result PSL error.
The second shows incorrect operand result contents.

********
PASS 1

reports coming

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 1

9.0

ERROR 1

********

6-AUG-1978

11:34:41.92

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 1
? RESULT PSL ERROR
EXPECTED

ACTUAL

000000E5

000000El

INITIAL CONDITIONS:
PC 00004958 PSL 000000EF
OP CODE -- 90 WITH REGISTER INDIRECT OPERANDS
INITIAL REGISTERS R0--R6:
R0

0000AE04

00000000

0000AE0D

R2
RS

SOURCE OPERAND DATA:
OPERAND 1
05
Example 6-46

ESKAY Test 2, Subtest 2, Error 1

6-46

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 1

9.0

ERROR 31

********

6-AUG-1978

11:35:27.25

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 31
? INCORRECT RESULT, OPERAND 2
EXPECTED

ACTUAL

00004300

00004304

INITIAL CONDITIONS:
PC 000046FA PSL 000000EF
OP CODE -- 6C WITH REGISTER INDIRECT OPERANDS
INITIAL CONDITIONS:
R0

0000AE04

0000AE0D

00000000

SOURCE OPERAND DATA:
OPERAND 1
21
Example 6-47

ESKAY Test 2, Subtest 1, Error 31

6-47

Interpretation of Example 6-47
1.

The op code 6C defines the instruction under test as
CVTBD (you can know this by simply looking up the given
op code on a coding card).

The general format of this instruction
looking at the code card) is as follows:

(again

from

op code scr.rx, dst.wy
The statement WITH REGISTER INDIRECT OPERANDS indicates
that the form of the instruction being tested is CVTBD
(R0), (Rl).
NOTE
All instruction testing is set up so
that the first operand always uses RI,
second operand always uses Rl, third
operand always uses R2, etc.
PC

and

PSL

should

Th e
init ia1
con d i t i on s
self-explanatory.

The TEST CASE NUMBER of 31 shows nothing more than how
far into the current test table we are, i.e., 30
instruction types were tested up to this point with no
errors.
For all intents and purposes, you can ignore this number.

The error indication of INCORRECT RESULT, OPERAND 2
states that the final contents of the destination operand
were wrong. OPERAND 2 is shown above as (Rl).

The SOURCE OPERAND DATA of 21 is self-explanatory.

The INITIAL REGISTERS R0--R6 specify the addresses in
memory in use for the instruction. In this case, CVTBC
(AE04) , (AE0D).
NOTE
R2 through R6 contain es since the CVTBD
instruction uses only two operands.

Finally, the EXPECTED value of 4300 and the ACTUAL value
of 4304.
If you examine the content of AE0D (/W)
4304.

it should contain

Example 6-48 is another form of printout similar to the preceding
two examples with a twist. An unexpected exception occurred during
the testing of an instruction.
6-48

********
PASS 1

CPU CLUSTER EXERCISER
TEST 2

SUBTEST 3

9.0

ERROR 1

********

6-AUG-1978

11:34:42.57

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR
? ERROR IN TEST CASE NUMBER: 1

UNEXPECTED EXCEPTION
ERROR# 00000001
VECTOR# 00000034
SUBTYPE# 00000001
PSL 000000EB
PC 00004933
INITIAL CONDITIONS:
PC 00004930 PSL 000000E0
OP CODE -- SE WITH REGISTER INDIRECT OPERANDS
INITIAL REGISTERS R0--R6:
R0

0000AE04

0000AE0D

00000000

SOURCE OPERAND DATA:
OPERAND 1
80
Example 6-48

ESKAY Test 2, Subtest 3, Error 1

6-49

Interpretation of Example 6-48
1.

The unexpected exception occurred through VECTOR 34
(Paragraph 2. 7 of the KA780 Central Processor Technical
Description 1 is ts VECTOR 34 as the ARITHMETIC TRAP
vector) •

The SUBTYPE of 1 informs you that the condition was
INTEGER OVERFLOW (Paragraph 2.7 of the KA780 Central
Processor Technical Description) •

The PC of 4933 and PSL of EB are those existing at the
time of the exception occurrence.

The ERROR 1 is nothing more than a repetition of
ERROR 1 printout of the header report.

The rest of the printout is as outlined for the two
printouts preceding (i.e., the same breakdown applies).

the

6.4.3
Branch, CRC, and Queue Test Module (ESKAY04, Test 13)
Not yet implemented.
6.4.4
Floating-Point Instructions Test Module (ESKAYIS, Test 4;
ESKAY06, Test 5)
Tests 4 and 5 check both the basic floating-point instructions and
the accelerated floating-point instructions. Arithmetic and
reserved
operand exceptions
pertaining
to
floating-point
instructions are also tested. Since the FPA takes part in the
execution of MULL2 and MULL3, the tests also check. these
instructions. The floating-point accelerator is turned off for
test 4 and on for test 5.

6-50

Typical Error Messages for Test 4

********
PASS 1

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 4

SUBTEST 1

ERROR 2

20-FEB-1978

********

11:26:00.00

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR
? ERROR IN TEST CASE NUMBER:

? RESULT PSL ERROR
EXPECTED

ACTUAL

001F00E3

001F00El

INITIAL CONDITIONS:
PC 00004420 PSL 001F00EF
OP CODE -- 4F WITH REGISTER INDIRECT OPERANDS
INITIAL REGISTERS R0--R6:
R0

0000AC04

0000AC10

00ctrnAClC

00000000

SOURCE OPERAND DATA:
OPERAND 1
00004080
OPERAND 2
00004080
OPERAND 3
00000000
Example 6-49

ESKAY Test 4, Subtest 1, Error 2

6-51

********
PASS 1

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 4

SUBTEST 1

ERROR 7

HARD ERROR WHILE TESTING CPU:
? ERROR IN TEST CASE NUMBER:

20-FEB-1978

********

11:26:00.00

INSTRUCTION TEST ERROR
7

? RESULT PSL ERROR

EXPECTED

ACTUAL

001F00E5

001F00E4

INITIAL CONDITIONS:
PC 00004695 PSL 001F00EB
OP CODE -- 71 WITH REGISTER INDIRECT OPERANDS
INITIAL REGISTERS R0--R6:
R0

0000AC04

0000AC14

00000000

SOURCE OPERAND DATA:
OPERAND 1
00004080
00000000
OPERAND 2
00004080
00000000
Example 6-50

ESKAY Test 4, Subtest 1, Error 7

6-52

********
PASS 1

********

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 4

SUBTEST 1

ERROR 24

20-FEB-1978

11:26:00.00

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 24
? RESULT PSL ERROR
EXPECTED

ACTUAL

001F00E8

001F00E0

INITIAL CONDITIONS:
PC 00004873 PSL 001F00EF
OP CODE -- WITH REGISTER INDIRECT OPERANDS
INITIAL REGISTERS R0--R6
R0

0000AC04

0000AC14

0000AC1D

0000AC2D

0000AC39

00000000

SOURCE OPERAND DATA:
OPERAND 1
FFFE4FFF
FFFFFFFF
OPERAND 2
FF
OPERAND 3
00004080
00000000
Ex.ample 6-51

ESKAY Test 4, Subtest 1, Error 24

6-53

A lengthy detailed description of this type of error report has
been supplied in Paragraph 6.4.2. Using that description as a
reference, interpretations of the preceding three error reports
follow.
Interpretation of Example 6-49
The instruction being tested is
ACBF (R0), (Rl), (R2), displacement
BREAKING DOWN FURTHER-ACBF (AC04), (AC10), (AClC), displacement
BREAKING DCMN FURTHER-ACBF 4f80, 4i80, 0, displacement
limit

addend

index

Interpretation of Example 6-50
The instruction being tested is
CMPD (R0) , (Rl)
BREAKING DOWN FURTHER-CMPD (AC04, (AC14)

BREAKING DOWN FURTHER-CMPD 4080, 4080
source

. .
dest1nat1on

Interpretation of Example 6-51
Going through a similar analysis
EMODD (R0), (Rl), (R2), integer, fraction
EMO DD

FFFE4FFF
FFFFFFFF

fltating~

00000000, integer, fraction

~l multtplicand

point multiplier

floating-point
multiplier extension

6-54

Typical Error Messages for Test 5

********
PASS 1

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 5

SUBTEST 2

ERROR 7

20-FEB-1978

********

11:26:00.00

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 7
? INCORRECT TRACE TRAP PSL
EXPECTED

ACTUAL

001F00F5

001F00F4

INITIAL CONDITIONS:
PC 00004695 PSL 001F00FB
OP CODE -- 71 WITH REGISTER INDIRECT OPERANDS
INI~IAL

REGISTERS R0--R6:

0000AC04

00000000

0000AC14

00000000

SOURCE OPERAND DATA:
OPERAND 1
00004080
00000000
OPERAND 2
00004080
00000000
Example 4-52

ESKAY Test S, Subtest 2, Error 7

6-55

********
PASS 1

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 5

SUBTEST 8

ERROR 100

20-FEB-1978

********
11:26:00.00

HARD ERROR WHILE TESTING CPU: FLOATING NORMALIZE SUBTEST
? ERROR IN TEST CASE NUMBER: 113

EXPECTED

ACTUAL

FFF849FF

00003F80

TEST AT PC: 00009A87
R0

00004080

0000C040
Example 6-53

********
PASS 1

ADDF3 R0, R2, R4

ESKAY Test 5, Subtest 8, Error 100

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 5

SUBTEST 8

ERROR 101

20-FEB-1978

********
11:26:00.00

HARD ERROR WHILE TESTING CPU: FLOATING NORMALIZE SUBTEST
? ERROR IN TEST CASE NUMBER: 161
EXPECTED

ACTUAL

00004040

00004000

00000000

TEST AT PC: 00009Bll
Rl

0000C000

FFFF4D7F

0000E000
Example 6-54

ADD3 R0, R2, R4

ESKAY Test 5, Subtest ·8, Error 101

6-56

The interpretation of Example
given for Example 6-47.

6-52

similar

that

already

Examples 6-53 and 6-54 are for the FLOATING NORMALIZE SUBTEST and
differ from the standard CITS printouts as follows:
1.

Both printouts give the instructions under test and their
operands, i.e.,
ADDF3 R0, R2, R4
ADD3 R0, R2, R4

The operand data is listed directly under the TEST AT PC
statements.

The EXPECTED and ACTUAL data in both cases reference the
contents of R4
(R4, by definition, specifies the
destination operand) •

6.4.5
Operand Specifier Dependent Floating-Point Test (ESKAYl7,
Test 6)
Not yet implemented.
6.4.6
Decimal Strings Module (ESKAX08, Test 7)
This module tests the microcode and hardware used
string execution.

for

decimal

Interpretation of Example 6-55
The error printouts coming from this test are designed like those
of test 5. An overall interpretation has already been described in
the test 2 writeup.
Analysis should show the instruction under test to be
ADDP6

(R0) ,

addllen

(Rl) ,

addladdr

(R2) ,

add2len

(R3) ,

(R4) ,

add2addr

(RS)

sumaddr

sumlen

with ADDRESSES REFERENCED shown under INITIAL REGISTERS R0--R6 and
OPERAND DATA as indicated.
6.4.7
EDITPC Operators Module (ESKAYl9, Test 8)
This module tests the EDITPC microcode and associated hardware.

6-57

Typical Error Message

********
PASS 1

********

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 7

SUBTEST 2

ERROR 26

20-FEB-1978

11:26:00.00

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR
? ERROR IN TEST CASE NUMBER: 26

? INCORRECT TRACE TRAP PSL
EXPECTED

ACTUAL

001F00F8

001F00F0

INITIAL CONDITIONS:
PC 00004585 PSL 001F00FF
OP CODE -- 21 WITH REGISTER INDIRECT OPERANDS
INITIAL REGISTERS R0--R6
R0

0000AC04

0000AC0E

0000AC1B

0000AC25

0000AC35

0000AC3F

00000000

SOURCE OPERAND DATA:
OPERAND 1
0009
OPERAND 2
12, 34, 56, 78, 9C
OPERAND 3
000E
OPERAND 4
00' 00' 00, 77, 77, 77, 77, 7E
OPERAND 5
001F
Example 6-55

ESKAY Test 7, Subtest 2, Error 26
6-58

Typical Error Message

********
PASS 1

CPU CLUSTER EXERCISER (ZZ-ESKAY) -- 9.0
TEST 8

SUBTEST 1

ERROR 48

20-FEB-1978

********
11:26:00.00

HARD ERROR WHILE TESTING CPU: INSTRUCTION TEST ERROR

? ERROR IN TEST CASE NUMBER: 48
? RESULT PSL ERROR
EXPECTED

ACTUAL

001F00E5

001F00E4

INITIAL CONDITIONS:
PC 0000485A PSL 001F00EB
OP CODE -- 38 WITH REGISTER INDIRECT OPERANDS
INITIAL REGISTERS R0--R6:
R0

0000AC04

0000AC0E

0000AC1E

0000AC2F

00000000

SOURCE OPERAND DATA:
OPERAND 1
0000F
OPERAND 2
00, 00, 00, 00, 00, 00, 00, 00
OPERAND 3
40, 40, 43, 25, 04, 9F, 46, 10, 00
Example 6-56

ESKAY Test 8, Subtest 1, Error 48

6-59

Interpretation of Example 6-56
The error printouts coming from this test are designed like those
described in Paragraph 6.4.2.
Therefore, analysis should show the instruction under test to be
EDITPC·

(R0) ,

srclen

(Rl) ,

(R2) ,

i
pattern

srcaddr

(Rr
dstaddr

with ADDRESSES REFERENCED shown under INITIAL REGISTERS R0--R6 and
OPERAND· DATA as indicated.

6.4.8
9)

Character String Instructions Test Module

(ESKAYle, Test

Not yet implemented.

6.4.9
Privileged Instruction Exception Test (ESKAYll, Test 10)
Not yet implemented.
6.5

ESKAZ DESCRIPTION

6.5.1
Memory Management Test Module (ESKAZ03, Test 1)
The object of this test is to test memory management on a
VAX-11/780 CPU. Memory management is that part of the CPU which
checks protection on memory references, performs virtual to
physical address translation, monitors updates to pages of memory
(with the modify bit of the page table entry), and resolves
unaligned data references. These functions are tested by making
many different kinds of references to see that they work. Working
is defined as: reading or writing the correct data, leaving the
contents of adjacent addresses unaffected, setting the M bit on
the first write to a page, and faulting if required. Upon
detecting a failure, the test issues an error report containing
the failure symptom (e.g., unexpected fault, wrong condition
codes) and the circumstances surrounding the failure (instru_ction
and address under test, expected and received data, etc.).
The test is organized in six subsections, each testing some area
of memory management functionality.
1.

Valid read and write -- The intent is to quickly verify
that the basic functions work. Longword aligned reads and
writes are performed to each address space (P0, Pl, and
System). This process performs initial checks of reading
and writing, physical address translation in each address
space, translation buffer loading, and setting of the
modify bit.

6-60

Length register boundary checks - References are made
just before and just beyond each of the length boundaries
to verify the length boundary checks.

Page Table Entry {PTE) combinations -- This subsection
changes privilege modes to kernel, exec, super, and user.
It makes references to pages mapped with each access
code, and with the PTEs both valid and invalid, to verify
the access privilege checks.

Size with PTE combinations -- The size of the access is
varied from byte to quadword and tried with PTE
combinations.

Page boundary checks -- The size of the access and the
position of the access with respect to a page boundary
are varied.

IB references with PTE combinations -- This subsection
attempts to make instruction buffer references while
varying the protection of the referenced page.

6-61

6.5.1.1 Memory Management Test General Flow
Initialization -- Three buffer a re as are requested from the
supervisor, one each from P0, Pl, and system spaces. A control
block (BVAS) is loaded with their addresses, and with the
addresses of three other buffer areas, which are on the last page
in each space.
Execution of Subsections
the subsections, as follows.

A loop selects and

executes each

Select an sec -- The entry in the subsection description
table associated with the current subsection is selected.
It includes a pointer to a Setup Command Chain (SCC).
There is an sec for each subsection. The execution
section includes six nested loops, varying access size,
address space, and operand alignment. The sec contains
start and end limits for these loops. For instance, the
sec for the fourth loop, page boundary checks, specifies
varying access size from byte to quadword, varying the
off set from a page boundary from 8 bytes before through 1
byte after the page boundary, and varying address space
from P0 to system.

Create defaults
Defaults are
variables not specified in the sec.

Execute subsection -- A procedure is called that will
make test references, varying each reference variable
specified in the sec across the range.

provided

for

any

Clean up -- At the end of the test, all buffers are returned and
control returns to the dispatch routine in the supervisor.

6.5.1.2 Memory Management Test, Subsection Flow
Loop start -- All reference parameters that will vary are loaded
with initial values specified in the sec.
Execute -- The test reference described by the current state of
all the reference variables is made.
Increment -- The next value of the most rapidly varying parameter
is loaded. If its range has been covered, it is set to its initial
value -and the next variable is changed.
Loop -- If the slowest varying reference parameter has completed
its range, the subsection is complete. Otherwise, the next
reference is made.

6.5.1.3 Test Reference Execution
Initialize -- The control blocks for this section
are set up.
Decode
A CITS
instruction.

(CITS_DECODE)

6-62

called

(MRDB and TCB)

decode

the

test

Simulate -- The test reference is
results are loaded into the MRDB.

simulated,

and

the

expected

Setup -- Another CITS routine (CITS SETUP) is called to initialize
the data areas, general register, and stack for the test
instruction.
Map -- The address of the test reference is mapped according
the variables controlling page validity and accessibility.

Probe -- A probe is made to the test address in order to verify
the mapping, and the results are compared with the simulated
results.
Execute -- The test reference is made.
Remap -- The test address mapping is reset to allow all access,
and the result maps are copied and checked.
Data Check -- CITS CHECK
test instruction.
Loop -- The flow from
buffer states.

is called to check the

setup is repeated

Return.

6-63

results of the

for various translation

Typical Error Messages

********
PASS 1

********

CPU CLUSTER EXERCISER -- 9.0
TEST 1

SUBTEST 1

ERROR 20212

28-MAY-1978

08:31:01.89

HARD ERROR WHILE TESTING CPU: LENGTH REGISTER BOUNDARY
ERROR OCCURRED DURING: ACCESS OR ACCESS CHECK
ERROR: PAGE TABLE ENTRY WAS MODIFIED
TESTED

PSL

MODE

ACCESS

ADDRESS

PRV

CUR

TYPE

SIZE

80001FF8

SPTEl:
SYS BASE
REG

PTE

PROTECTION

V-BIT

M-BIT

ACCESS

ALLOWED

ADDRESS

VALUE

CODE

STATE

0001F43C

00000098

0003

VAL

CLR

NO NO

SYS LENGTH

REG

0001F400

00000022

EXP DATA

ACT DATA

PTE MODIFIED

00000098

SPTEl:

Example 6-57

ESKAZ Test 1, Subtest 1, Error 20212

6-64

********
PASS 1

CPU CLUSTER EXERCISER -- 9.0
TEST 1

SUBTEST 1

********

ERROR 20213. 28-MAY-1978

08:50:58.91

HARD ERROR WHILE TESTING CPU: LENGTH REGISTER BOUNDARY
ERROR OCCURRED DURING: ACCESS OR ACCESS CHECK
ERROR: MODIFY BIT ERROR
TESTED

PSL

MODE

ACCESS

TESTED

OPERAND

ADDRESS

PRV

CUR

TYPE

SIZE

INSTR

NO.

6013001F8

MOV

PTE

PROTECTION

V-BIT

M-BIT

ACCESS

ALLOWED

ADDRESS

VALUE

CODE

STATE

0001F480

000000g4

0002

VAL

SET

RW NO

NO NO

PPTEl: 0001F200

00000094

0002

VAL

SET

RW NO

NO NO

SPTEl:

T-BUFF
STATE
MISS

HIT
SYS BASE

SYS LENGTH

REG

0001F400

00000022

Pl BASE

Pl LENGTH

REG

7FC01A00

0010000F

EXPECTED

PTE

STATE
SET

SPTEl:
Example 6-58

ESKAZ Test 1, Subtest 1, Error 20213
6-65

Interpretation of Example 6-57
1.

First, a discussion of ERROR 20212
All error numbers consist of 3 bytes with a breakdown as
follows:
a.

The left byte ( 2) defines the location
test where the error was encountered

within

the

where,
0

= Subtest

1--6
b.

Subsection defined prior to
examples (Paragraph 6.5.1).

the

preceding

The middle byte (02) indicates the action being taken
by the test at the time of error
where,
0 = SETUP
1 = PROBE/PROBE CHECK
2 = ACCESS/ACCESS CHECK
3 = ACCESS DATA CHECK
4 = FINAI:. SETUP

The right byte (12) is indicative of the error itself
(it is used by the test software to determine what
gets printed at error report time).

So, the ERROR number tells us that we were in the LENGTH
REGISTER BOUNDARY subsection (2) performing an ACCESS/ACCESS
CHECK (02), when we got a message saying PAGE TABLE ENTRY WAS
MODIFIED (12).
2.

The ADDRESS UNDER TEST was 80001FF8.

The PREVIOUS and CURRENT MODES
time are shown as K K
where,
K = Kernel
E = Executive
S = Supervisor
U = User

6-66

in the

PSL at the test

The ACCESS occurring at the time of the error is shown as
R

where,
R = Read
W =Write
M = Modify

The SIZE of the access is shown as L
where,
L

= Longword

B = Byte

w = Word
Q

= Quadword

A discussion of the line labeled SPTEl follows.
In the given example we have only one line of
information, but depending on the set of circumstances
there can be more than one line (as shown in Example
6-58) •

The lines
follows:

and

SPTEl:
SPTE2:
PPTEl:
PPTE2:

1 system page table

Page
Page
Page
Page

combinations

that

can

appear

are

2 system page table
1 processor page table

2 processor page table

where,
Page 1 = page number of the address of the lowest byte of
the reference address as determined by either the Base
Virtual Address (BVA) or, if the position is negative, by
the BVA + position.
Page 2 = the next page.
NOTE
A reference may be either entirely
within PAGE 1 or PAGE 2, or it may cross
over.
In our example,
ACCESSED.

the

PAGE

6-67

1 system page

table

is being

The PHYSICAL ADDRESS of the PTE is 1F43C.
NOTE
The PTE is the medium of translation of
all virtual
addresses
to physical
addresses.

The PTE VALUE represents the contents of the PTE or 98.
The PTE content comprises 4 fields.
a.

Page Frame Number (PFN) -- Bits <20:00>
This is the upper 21 bits of the physical address of
the base of the page.

Modify bit

Bit <26>

Protection

Bits <30:27>

valid -- Bit <31>

The PROTECTION CODE for the page accessed was 3.

10.

Chapter 5 of the VAX-11 System Reference Manual gives an
analysis of a protection code meaning.
To ease the strain of searching through the VAX-11 System
Reference Manual, the protection code breakdown is shown
under ACCESS ALLOWED as R, NO, NO, NO.
This states that the page being accessed can be READ in
kernel mode, and cannot be accessed in any other mode.
NOTE
A W under this column would indicate
that the page can be written in a given
mode.

11.

The state of the valid bit (V-BIT)

is VAL

where,
VAX = 1 (valid)
INV = 0 (invalid)
12.

The state of the modify bit (M-BIT)
where,
CLR = 0 (no modify)
SET = 1 (modify)

6~68

is CLR

13.

The content of the SYSTEM BASE REGISTER was 1F400 and the
content of the SYSTEM LENGTH REGISTER was 22.
These 13 items represent the SETUP portion of the error
report (i.e., what were all the initial conditions, or
states, at the time of the error).
The SYS BASE REG and SYS LGTH REG printouts always occur
as parts of the SETUP. As a function of the TESTED
ADDRESS value, one or two other printouts will occur
additionally as follows:
a.

14.

If bit 31
includes

is clear and bit 30

Pl BASE

Pl LENGTH

REG

set,

the message

If bit 31 is clear and bit 30 is clear, the message
includes
P0 BASE

P0 LENGTH

REG

The ERROR portion of the printout shows further proof of
the ERROR: PAGE TABLE ENTRY WAS MODIFIED statement by
showing the EXPECTED and ACTUAL DATA and the PTE
MODIFIED.

Example 6-58 is similar to Example 6-57 except that it shows
additional information which reflects circumstances at the time of
the error.
The new items in Example 6-58 are:
a.
b.
c.

TESTED INSTR is a MOV
The OPERAND NO. in question is 02 (i.e., the DST).
The translation buffer state (TB-STATE) is listed
where,
HIT = 1
MISS = 0.

6-69

6.6

COMPATIBILITY MODE INSTRUCTION TEST (ESKAZ93, TEST 2)

6.6.1
Instructions Tested
Most of the instructions provided by the compatibility mode
hardware are exercised using various data patterns and address
modes (Figure 6-3). These instructions are listed in Table 6-12.

START

SUBTEST
SETUP

SUBTEST
INSTRUCTION __.
IN:._____________

VERIFY

LOOP

GOTO
NEXT
SUBTEST
TK-1200

Figure

6-3

Compatibility

Mode Instruction
Structure

6-70

Module

Subtest

Table 6-12
Compatibility Mode Instructions Provided
Compatibility Mode Hardware and Exercised by ESKAZ Test 2
Op Code (8)

Mnemomic

Op Code (8)

Mnemonic

.055DD
.06SSDD
.063DD
.062DD
.4SSDD
.5SSDD
.3SSDD
400-377 7
100000-3777
.050DD
.2SSDD
.051DD
240-277
• 0 53DD
.052DD

ADC ( B)
ADD
ASL (B)
ASR ( B)
BIC (B)
BIS(B)
BIT (B)
BRANCHES(*)
BRANCHES(**)
CLR (B)
CMP (B)
COM(B)
CND CODES(***)
DEC ( B)
INC ( B)

0001DD
004RDD
.lSSDD
.054DD
.061DD
.060DD
.0020R
000006
.056DD
077RNN
16SSDD
0003DD
0067DD
.057DD
074RSS

JMP
JSR
MOV (B)
NEG ( B)
ROL {B)
ROR ( B)
RTS
RTT
SBC ( B)
SOB
SUB
SWAB
SXT
TST ( B)
XOR

where,
(*)=BR, BNE, BEQ, BGE, BLT, BGT, BLE
(**)=BPL, BMI, BVC, BCC, BCS, BHI, BLOS, BHIS, BLO
(***)=CLC, CLV, CLZ, CLN, CCC, SEC, SEV, SEZ, SEN, sec
The instructions provided by the compatibility mode hardware that
have not yet been included in this test are listed in Table 6-13.
Table 6-13

Compatibility Mode Instructions Not Yet Tested
Op Code(8)

Mnemonic

072RSS
073RS8
071RS8
1065S8
0065S8
1066DD
0066DD
070RS8

ASH
ASHC
DIV
MFPD
MFPI
MTPD
MTPI
MUL

6-71

NOTES
instruction

The test
tagged IN.

The error is always tagged EN.

The return point
always tagged RN.

If more than one verification is
made in a single subtest, the
entries to subsequent checks are
tagged AN, BN, etc.

If more than one error is included,
subsequent errors are tagged ElN,
E2N, E3N, etc.

for

always

looping

The RTI instruction provided by compatibility mode hardware is not
tested in this module. The compatibility mode entry/exit module
(ESKAX02, Test 01) tests this instruction thoroughly.
6.6.2
Compatibility Mode Test Error Message Format
The following header is printed when an error is detected.
(PC)

(PSW)

(SP)

(Rl)

(R2)

(R3)

(R4)

Interpretation of Compatibility Mode Test Error Message Format
(PC)

Indicates the content of the program counter at the time
of the error call. This is normally an address that is
used to locate the error cal 1 statement in the failing
subtest.

(PSW)

Indicates the content of the processor status word at the
time of the error call.

(SP)

Indicates the content of the
time of the error.
The error
twice.

call

NOTE
wi 11

6-72

stack pointer

push

the

stack

(R6)

at the

(Rl)

Indicates a mnemonic of the instruction under test
e.g., MOVB, ASL • • • et al.

(R2)

For single- and double-operand instructions, R2 normally
contains the destination address.

(R3)

For single- and double-operand instructions, R3 contains
what the result (destination operand) actually was after
the test instruction was executed.

(R4)

For single- and double-operand instructions, R4 contains
what the result (destination operand) should have been
(S/B).

In some cases, the error information may deviate from that
previously described but the program annotation for those subtests
will describe the meaning of those entries that have been
redefined.
The error call statement is encoded to print only the information
relative to the particular function being tested. Interpretation
of the error calls is shown below.
Print
Print
Print
Print
Print
Print
Print

ERROR
ERRORl
ERROR2
ERROR3
ERROR4
ERRORS
ERROR6
6.6.3

********
PASS 1

all 7 col urnns
only column 1
columns 1, 2
columns 1, 2,
col urnns 1, 2,
columns 1, 2,
col urnns 1, 2,

3
3, 4
3, 4, 5
3, 4, 5, 6

Sample Error Message Explanation

********

CPU CLUSTER •
TEST XX

SUBTEST 208 •

HARD ERROR WHILE TESTING CPU: COMPATIBILITY MODE
(PC)

(PSW)

(SP)

(Rl)

(R2)

00008DD0

00000004

0000ASAA

MOV

00000400

Example 6-59

(R3)

ESKAZ Compatibility Mode Test Error

6-73

(R4)
0000FFFF

Interpretation of Example 6-59
8DD0

Represents the PC of the error call in the listing.

Represents
call.

ASAA

Represents the
pointer (R6).

MOV

Is a clue that the MOV instruction failed under test.

400

Represents the address used by
portion of the MOV instruction.

destination

mode

0000

Represents the actual content of the destination
instruction execution.

after

FFFF

Represents what the content of the destination
have been after the MOV instruction was executed.

should

the

content
last

the

PSW prior

position of

the

error

PDP-11

mode

stack

the

The listing is laid out with a subtitle printed at the top of each
page. The operator can look through the program listing for
·subtest 208. The subtest description of 208 shows that a MOV
instruction is tested with source mode 2 and destination mode 3.
6.6.4
Compatibility Mode Instruction Module Assumptions
Four compatibility mode trap instructions are used to control the
execution of this test, as follows.
1.
2.

SUBTYPE 0 (SPL) Used as program end indicator.
SUBTYPE 2 (IOT) Used as next subtest indicator.
NOTE
Appears as SCOPE statement in listing.

SUBTYPE 3 (EMT) Used as error report indicator.
Appears as
listing.

NOTE
ERROR + XX

statement

SUBTYPE 4 (TRAP) Used as PSW reference indicator.
NOTE
Appears as
listing.

TRAP

statement

It is assumed that the test performing the exercising of
compatibility mode entry/exit conditions has been executed prior
to this test, in which event, the com pat i bi 1 i ty mode trap
instructions have been checked -out.

6-74

APPENDIX A
GLOSSARY OF DIAGNOSTICS SOFTWARE TERMS
absolute (ABS) -- A program section (psect} attribute. An absolute
psect contains only symbol definitions. It does not contribute
binary code to the image. Therefore, it must have a zero-length
memory allocation. The converse is relocatable (REL}.
access mode -- Any of the four processor access modes in which
software executes. Processor access modes are, in order, from most
to least privileged and protected: kernel (mode 0), executive
(mode 1) , supervisor (mode 2) , and user (mode 3) •
When the processor is in kernel mode, the executing software has
complete control of, and responsibility for, the system. When the
processor is in any other mode, the processor is inhibited from
executing privileged instructions. The processor status longword
contains the current access mode field. The operating system uses
access modes to define protection levels for software executing in
the context of a process. For example, the executive runs in
kernel and executive modes and is most protected. The command
interpreter is less protected and runs in supervisor mode. The
debugger runs in user mode and is no more protected than normal
user programs.
access type -- The way in which the processor accesses instruction.
operands. Access types are: read, write, modify, address, and
branch.
alignment -- The address boundary at which a
based.

program section is

allocate a device -- To reserve a particular device unit for
exclusive use. A user process can allocate a device only when that
device is not allocated by any other process.
allocation -- The number of bytes of memory
program section to a particular module.

contributed

alphanumeric character -- An upper or lower case letter (A--Z,
a--z}, a dollar sign ($}, an underscore ( } , or a decimal digit
(0--9} •

ancillary control process (ACP}
A process that acts as an
interface between user software and an I/O driver. An ACP provides
functions supplemental to those performed in the driver, such as
file and directory management.
argument -- An independent value within a command statement that
specifies where, or on what, the command will operate (e.g.,
address, data}.

A-1

argument pointer -- General register 12 (Rl2). By convention, AP
cont a i n s the add r e s s o f th e b a s e o f th e a r g um en t 1 i s t f o r
procedures initiated using the CALL instructions.
assign a channel -- To establish the necessary software linkage
between a user process and a device unit before a user process can
transfer any data to or from that device. A user process requests
the system to assign a channel and the system returns a channel
number.
assembler -- A program that translates source language code, whose
operations correspond directly to machine op codes, into object
language code.
asynchronous system trap (AST) -- A software-simulated interrupt
to a user-defined service routine. AS Ts enable a user process to
be notified asynchronously, with respect to its execution, of the
occurrence of a specific event. If a user process has defined an
AST routine for an event, the system interrupts the process and
executes the AST routine when that event occurs. When the AST
routine exits, the system resumes the process at the po int where
it was interrupted.
attributes
Various characteristics that can be assigned by the
programmer to each psect in a module (e.g., ABS).
base register --- A general register used to contain the address of
the entry in a list, table, array, or other data structure.
block
1. The smallest addressable unit of data that the
specified device can transfer in an I/O operation (512 contiguous
bytes for most disk devices). 2. An arbitrary number of contiguous
bytes used to store logically related status, control, or other
processing information (i.e., process control block).
breakpoint
In diagnostics, an address assigned through
diagnostic supervisor. When the PC equals the value of
breakpoint, control returns to the diagnostic supervisor.
boot (bootstrap) - - A program that 1 o ads another
program into memory from a peripheral device.

the
the

( usu a 11 y 1 a r g e r)

buffer -- A temporary data storage area.
call frame -- A standard data structure built on the stack during
a procedure call, starting from the location addressed by the FP
to lower addresses, and popped off during a return from procedure
(also called stack frame) •
channel -- A logical path connecting a user process to a physical
device unit. A user process requests the operating system to
assign a channel to a device so that the process can transfer data
to or from that device.

A-2

command file -- A file containing command strings.
command interpreter
Procedure-based code to receive, syntax
check, and parse commands typed by the user at a terminal or
submitted in a command file.
command parameter -- The positional operand of a command delimited
by spaces, such as a file specification, option, or constant.
command string
A line, or a set of continued lines, normally
terminated by typing the carriage return key containing a command,
and optionally, information modifying the command. A complete
command string consists of a command; its qua 1 if ie rs, if any; its
parameter (file specifications, for example), if any; and their
qualifiers, if any.
concatenate (CON)
A program section attribute. If a psect is
concatenated, all psects of the same name yet from different
modules are to be assigned contiguous addresses in the virtual
address space. Each module can specify an independent alignment.
The linker performs the necessary padding of zero bytes between
con tr ibut ions. The base alignment of the resulting concatenated
psects is according to the greatest alignment granularity of all
the contributions to the psect. For example, if the greatest
alignment granularity of all contributors is a page, the psect is
page-aligned; although, some contributors may be byte-aligned,
others word-aligned, etc.
condition
software·.

exception

condition

detected

and

declared

condition codes -- Four bi ts in the processor status word
indicate the results of the previously executed instruction.

by
that

condition handler -- A procedure that a process wants the system
to execute when an exception condition occurs. When an exception
condition does occur, the operating system searches for a
condition handler. When it finds the condition handler, the
operating system initiates the handler immediately. The condition
handler may perform some act to change the situation that caused
the exception condition and then continue execution of the process
that incurred the exception condition. Condition handlers execute
in the context of the process at the access mode of the code that
incurred the exception condition.
context switching
Interrupting the activity in progress and
switching to another activity. Context switching occurs as one
process after another is scheduled for execution. The operating
system saves the interrupted process's hardware context in its
hardware PCB using the save process context instruction, loads
another process's hardware PCB into the hardware context using the
load process context instruction, and schedules that process for
execution.

A-3

cylinder
The tracks
surfaces of a disk pack.

the

same

radius

all

recording

default -- Assumed value supplied when a command qualifier does
not specifically override the normal command function; also,
fields in a file specification that the system fills in when the
specification is not complete.
default disk -- The system disk to which the system writes all
f i 1 es that the opera to r c re ates , by def au 1 t • The def au 1 t i s used
whenever a file specification in a command does not explicitly
name a device.
delimiter -- A character or symbol used to separate or limit items
within a command or data string. However, the delimiter is not a
member of the string.
device
The general name for any physical terminus or link
connected to the processor that is capable of receiving, storing,
or transmitting data. Card readers, line printers, and terminals
are examples of record-oriented devices. Magnetic tape devices and
disk devices are examples of mass storage devices. Terminal line
interfaces and interprocessor links are examples of communications
devices •.
device interrupt -- An interrupt received on interrupt priority
levels 16 through 23. Device interrupts can be requested only by
devices, controllers~ and memories.
d ev ice name - - The f i e 1 d i n a f i 1 e spec i f i cat ion that id en t i f i es
the device unit on which a file is stored. Device names also
include the mnemonics that identify an I/0 peripheral device in a
data transfer request. A device name consists of a mnemonic
f o 11 owed by a cont r o 11 er i dent i f i cat ion 1 et t e r ( i f a pp 1 i cab 1 e) ,
followed by a unit number (if applicable). A colon (:) separates
it from following fields.
direct I/O -- A mode of access to peripheral devices in which the
program addresses the device registers directly, without relying
on support from the operating system drivers.
drive
The electro-mechanical unit of a mass storage device
system on which a recording medium (disk cartridge, disk pack, or
magnetic tape reel) is mounted.
driver -- The set of system code that handles physical I/O to a
device.
entry mask -- A word (1) whose bits represent the registers to be
saved or restored on a subroutine or procedure call using the call
and return instructions, and (2) which includes trap enable bits.
entry point -- A location that can be specified as the object of a
call. It contains an entry mask and exception enables known as the
entry point mask.
A-4

event -- A change in process status or an indication of the
occurrence of some activity that concerns an individual process or
cooperating processes. An incident reported to the scheduler that
affects a process's ability to execute. Events can be synchronous
with the process's execution (a wait request, or they can be
asynchronous (I/O completion). Some examples of events: swapping,
wake request, page fault.
event flag -- A bit in an event flag cluster that can be set or
cleared to indicate the occurrence of the event associated with
that flag. Event flags are used to synchronize activities in a
process or among many processes.
exception -- An event detected by the hardware (other than an
interrupt or jump, branch, case, or call instruction) that changes
the normal flow of instruction execution. An exception is always
caused by the execution of an instruction or set of instructions,
while an interrupt is caused by an activity in the system
independent of the current instruction. There are three types of
hardware exceptions: traps, faults, and aborts. Examples are:
attempts to execute a privileged or reserved instruction; trace
traps;
compatibility mode
faults;
breakpoint
instruction
execution; and arithmetic traps such as overflow, underflow, and
divide-by-zero.
exception condition -- A hardware- or software-detected event
( o the r than an int e r r up t o r j ump , branch , case , o r ca 11
instruction)
that changes the normal flow of instruction
execution.
·except ion d i spat ch er - - An ope rat i n g sys t: em pro c e d u re that
searches for a condition handler when an exception condition
occurs. If no exception handler is found for an exception or
condition, the image that incurred the exception is terminated.
executable (EXE) -- A program section attribute. The psect
contains only instructions. This attribute provides the capability
to separate instructions from read-only and read/write data. The
linker uses this attribute in gathering psects and in the
verification of the transfer address that must be present in an
executable psect.
executable image -- An image that is capable of being run in a
process. When run, an executable image is read from a file for
execution in a process.
executive -- The generic name for the collection of procedures
included in the operating system software that provides the basic
control and monitor functions of the operating system.
file
A logically related collection of data treated as a
physical entity that occupies one or more blocks on a volume such
as disk or magnetic tape. A file can be referenced by a name
assigned by the user. A file normally consists of one or more
logical records.
A-5

file specification -- A unique name for a file on a mass storage
medium.
frame pointer -- General register 13 {Rl3). By convention, FP
contains the base address of the most recent call frame on the
stack.
global symbol -- A symbol defined in a module that is potentially
available for reference by another module. The 1 inker resolves
(matches references with definitions) global symbols. Contrast
with local symbol.
granularity -- The alignment of a contribution to a psect on a
boundary. The alignment granularity may be byte, word, quadword,
or page.
home block -- A block in the index file that contains the volume
identification, such as volume label and protection.
image -- An image consists of procedures and data that have been
bound together by the 1 inker. There are three types of images:
executable, sharable, and system.
index file -- The file on a FILES-11 volume that contains the
access information for all files on the volume and enables the
operating system to identify and access the volume.
interrupt -- An event (other than an exception or branch, jump,
case, or call instruction)
that changes the normal flow of
instruction execution. Interrupts are generally external to the
process executing when the interrupt occurs.
interrupt stack -- The system-wide stack used when executing in an
interrupt service context. At any time, the processor is either in
a process context executing in user, supervisor, executive, or
kernel mode; or in system-wide interrupt service context operating
with kernel privileges, as indicated by the interrupt stack and
current mode bits in the PSL. The interrupt stack is not
context-switched.
I/O function code
A 6-bit value specified in a queue I/O
request system service that describes the particular I/O operation
to be performed (e.g., read, write, rewind).
library file
A direct access
modules of the same module type.

file

containing

one

linked commands
A group of independent commands connected
together (linked) so as to form a single executable list of
commands. Once initiated, the entire linked command list may be·
executed without further operator intervention.

A-6

linker -- A program that reads one or more object modules created
'by language processors and produces an executable image file, a
sharable image file, or a system image file.
linking -- The resolution of external references between object
modules used to create an image; the acquisition of referenced
library routines, service entry points, and data for the image;
and the assignment of virtual addresses to components of an image.
link map -- A link map shows the virtual memory allocation of the
total program image. The link map is found in a program listing in
the program section allocation synopsis.
literal -- An operand which is used immediately, without being
translated to some other value. An operand which specifies itself.
1 i t er a 1 a r g urn en t - - An i n depend en t
statement that specifies itself.

v a 1 ue

w i th i n

co mm and

local symbol -- A symbol that is meaningful only to the module
that defines it. Symbols not identified to a language processor as
global symbols are considered to be local symbols. A language
processor resolves (matches references with definitions) local
symbols. They are known to the linker and cannot be made available
to another object module. They can, however, be passed through the
linker to the symbolic debugger. Contrast with global symbol.
logical block -- A block on a mass storage device identified by
us i n g the v o 1 um e - re 1 at iv e add res s rat he r than the phys i ca 1
(device-oriented) address or the virtual (file-relative) address.
The blocks that comprise the volume are labeled sequentially
starting with logical block 0.
macro
A statement that requests a language
generate a predefined set of instructions.

processor

memory management -- The system functions that include the
hardware's page mapping and protection and the operating system's
image activator and pager.
module -- A part of a program assembled as a unit. Modular
programming allows the development of large programs in which
separate parts share data and routines.
mount a volume
To logically associate a volume with the
physical unit on which it is loaded (an activity accomplished by
system software at the request of an operator). Or, to load or
place a magnetic tape or disk pack on a drive and place the drive
on-line (an activity accomplished by a system operator).
object module -- The binary output of a language processor such as
the assembler or a compiler, which is used as input to the linker.
operand -- a value (address or data)
by an instruction.
A-7

that is operated on, or with,

overlay (OVR) -- A program section attribute. If a psect is
over layed, al 1 con tr ibut ions to the psect have the same base
address. The length of the psect is the size of the largest
con tr ibut ion. All con tr ibut ions to an overlayed psect must have
the same alignment.
page -- A set of 512 contiguous byte locations used as the unit of
memory mapping and protection. Also, the data between the
beg inning of a file and a page marker, between two markers, or
between a marker and the end of a file.
page frame number (PFN) -- The address of the first byte of a page
in physical memory. The high-order 21 bits of the physical address
of the base of a page make up the PFN.
page table entry (PTE) -- The data structure that identifies the
location and status of a page of virtual address space. When a
virtual page is in memory, the PTE contains the page frame number
needed to map the virtual page to a physical page. When it is not
in memory, the PTE contains the information needed to locate the
page on secondary storage (disk).
parameter -- A parameter is the object of a command. It can be a
file specification, a keyword option, or a symbol value passed to
a command· procedure. In diagnostics, parameters are usually
operator-supplied answers to questions asked by a program
concerning devices to be tested.
parameter switch -- A command
preceded by a slash (/).

qualifier.

diagnostics,

parser -- A procedure that breaks down the components of a command
into structural forms.
physical address -- The address used by hardware to identify a
location in physical memory or on directly addressable secondary
storage devices such as disks. A physical memory address consists
of a page frame number and the number of a byte within the page. A
physical disk block address consists of a cylinder or track and
sector number.
physical block -- A block on a mass storage device referred to by
its physical
(device-oriented) address rather than a logical
(volume-relative) or virtual (file-relative) address.
position independent code (PIC) -- A program section attribute.
The contents of the psect do not depend on a specific location in
virtual memory. The converse is nonposition independent code
(NOPIC}.

A-8

priority -- The rank assigned to an activity that determines its
level of service. For example, when several jobs contend for
system resources, the job with the highest priority receives
service first.
program section -- A portion of a module. The assembler creates a
number of program sections (psect) within a module, according to
directives by the program developer. In addition, any code that
precedes the first defined program section is placed in the BLANK
program section by the assembler.
Through program sectioning the program developer controls the
virtual memory allocation of a program. Any program attributes
established by the program section directive are passed on to the
linker. Thus, program sections can be declared as read only,
nonexecutable, etc. See the VAX-11 MACRO Language Reference Manual
for an explanation of the various program section attribute
functions.
In the diagnostic programs, each test is given a separate program
section.
prompt -- A program's
operator action.

typed

out

response

and/or

request

for

qualifier -- A portion of a command string that modifies a command
verb or command parameter by selecting one of several options. A
qualifier, if present, follows the command verb or parameter to
which it applies and is in the format: /qualifier:option. For
example, in the command string "PRINT <filenam·e> /COPIES: 3", the
COPIES qualifier indicates that the user wants three copies of a
given file printed.
queue -- A list of commands or jobs waiting to be processed.
queue I/O -- A mode of access to peripheral devices in which a
program calls on driver routines provided by the VMS operating
system or the diagnostic supervisor to transfer data.
radix -- The base of the number system currently in use.
readable (RD) -- A program section attribute. The contents of the
psect can be read at the execute time. The converse is nonreadable
(NORD) •
record -- A collection of adjacent i terns of data treated as a
unit. A logical record can be of any length whose significance is
determined
by
the
programmer.
A physical
record
is
a
device-dependent collection of contiguous bytes such as a block on
a di s k , o r a co 11 e ct ion of bytes sent to o r received from a
record-oriented device.
relocatable (REL) -- A program section attribute. The psect must
be assigned a base address by the linker. This psect can contain
code and/or data.
A-9

script file -- A line-oriented ASCII file that contains a list of
commands.
section -- A group of tests in a diagnostic program that may be
selected by the operator.
sector -- A portion of a track on the surface of a disk. On a
VAX-11 system, each track on a disk is normally divided into 22
sectors.
semantics -- The interpretation of and relation between commands
or command symbols.
sharable image -- An image that has all of its internal references
resolved, but which must be linked with an object module(s) to
produce an executable image. A sharable image cannot be executed.
A sharable image file can be used to contain a library of
routines. A sharable image can be installed as a global section by
the system manager.
stack -- An area of memory set aside for temporary storage, or for
procedure and interrupt service linkages. A stack uses the
last-in, first-out concept. As items are added to (pushed on) the
stack, the stack pointer decrements. As items are retrieved from
(popped off) the stack, the stack pointer increments.
stack frame -- A standard data structure built on the stack during
a procedure call, starting from the location ~ddressed by the FP
to lower addresses, and popped off during a return from procedure.
Also called call frame.
stack pointer
General register 14 (Rl4). SP contains the
address of the top (lowest address) of the processor-defined
stack. Reference to SP will access one of the five possible stack
pointers: kernel, executive, supervisor, user, or interrupt,
depending on the value in the current mode and interrupt stack
bits in the Processor Status Longword (PSL).
standalone mode -- A diagnostic program environment in which the
pro g ram and the d i a g nos t i c super v i so r run w i thou t the VMS
operating system. The operator must use the console terminal when
running di'agnostics in the standalone mode, and no other users
have access to the system.
symbolic argument -- An argument within a command that refers to
another value.
syntax -- The
way in which
statements.

rules governing a command language structure. The
command symbols are ordered to form meaningful

syntactic unit -- An i tern contained within
(e.g., an argument, a qualifier).

A-10

command

statement

system image -- The image that is read into memory from secondary
storage when the system is started up.
test -- A unit of a diagnostic program
function or portion of the hardware.

that

checks

specific

time stamp -- A statement of the time of day at which a specific
event occurred.
track
A collection of blocks
recording surface of a disk.

single

radius

one

trap -- An exception condition that occurs at the end of the
instruction that caused the exception. The PC saved on the stack
is the address of the next instruction that would normally have
been executed. All software can enable and disable some of the
trap conditions with a single instruction.
unit record
printer.

device -- A device

such as

card

reader

line

unwind the call stack -- To remove call frames from the stack by
tracing back through nested procedure calls using the current
content of the FP register and FP register content stored on the
stack for each call frame.
UUT (unit under test)
The device or portion of the computer
hardware being tested by a diagnostic program.
virtual block number
A number used to identify a block on a
mass storage device. The number is a file-relative address rather
than a logical (volume-oriented) or physical (device-oriented)
address. The first block in a file is always virtual block number
one.
writable (WRT) -- A program section attribute. The content of the
psect can be modified at execute- time. The converse is nonwritable
(NOWRT) •

A-11

VAX-11/780 DIAGNOSTIC SYSTEM
TECHNICAL DESCRIPTION
EK-DS780-TD-001

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