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MISC-6840B6E7

1980

529 pages

Original

13MB

Document:	VAX 11/750 Level II Student Workbook
Order Number:	MISC-6840B6E7
Revision:
Pages:	529
Original Filename:

OCR Text

VAX-11/750 LEVEL II

Student Workbook

For Internal Use Only

Copyright© 1980, Digital Equipment Corporation.
All Rights Reserved.
The reproduction of this material, in part or whole, is
strictly prohibited. For copy information, contact the
Educational Services Department, Digital Equipment
Corporation, Bedford, Massachusetts 01730.

Printed in U.S.A.

The information in this document is subject to change
without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital
Equipment Corporation assumes no responsibility for
any wrors that may appear in this document.

The software described in this document is furnished
under a license and may not be used or copied e,.;cept
in accordance with the terms of such license.
Digital Equipment Corporation assumes no responsibili~f

for the use or reliabHity of its software on equipment
that is not supplied by Digital.

The following are trademarks of Digital Ecwipment Corporation,

Maynard, Massachusetts:
DIGITAL
DEC

MASS BUS

POP

DECsystem-10
DECSYSTEM·20
DIBOL

OECUS

EDUSYS"rEM

RSTS

JN I BUS

VAX

ASX
f AS

VMS

OMNIBUS

05/8

System Introduction

SYSTEM INTRODUCTION
INTRODUCTION
The 11/750 system is an extension of the VAX Family System
with many of the same characteristics of the VAX 11/780.
The 11/750 system allows users up to 4. 3 bill ion virtual
address while only using 2 MEG of physical memory.
To do
this the 11/750 has mass storage devices on a Mass bus or
Unibus for quick and easy access by the CPU.
The 11/750 may run in two modes of operation:
1.

NATIVE (VAX VMS)

COMPATABILITY (PDP-11)

There is also the capability of Remote diagnostics to help
both the user and the field service technician.
With this
Introduction Module we will attempt to give you the basic
facts and concepts of the 11/750 System including:
1.

Basic Architecture

Analysis of Block Diagram

Physical Characteristics

Diagnostic Overview

1-1

System Introduction

11/750 SUPPORT COURSE
MODULE I:

SYSTEM INTRODUCTION
SYNOPSIS

The system introduction module consists of 11/750
system characteristics and block diagram analysis.
OBJECTIVES
Provided with a blank 11/750 system block diagram
and a list of 11/750 component names, correctly
label the 11/750 system block diagram.
Given a list of 11/750 characteristics, correctly
indicate as True/False the characteristics that make
11/750 a unique system.
SAMPLE TEST ITEM
Identify the following 11/750 unique characteristics
as True or False.
1.

The 11/750 Processor Microword is 99 bits.

The 11/750 has a Virtual Memory System.

The 11/750 data path is 16 bits.

There is no Remote Diagnosis capability
with the 11/750 system.
RESOURCES

11/750 Specification
New Product Data Sheet
11/750 Block Diagram
11/750
11/750 Pocket Reference Guide

1-2

System Introduction

MODULE OUTLINE
I.

SYSTEM INTRODUCTION
A.

Course Overview

Basic Architecture

11/750 Specifications

11/750 Physical Characteristics

Block Diagram Analysis
1.

CPU
a.

Data Path Module

Memory Interconnect Module

11/750 Control Store

Unibus Interface

Major Buses

Memory
a.

Controller (1)

Array Boards (up to 8)

Options
a.

CPU Options
1.

Writable Control Store

Floating-Point Accelerator

Mass Bus Options

Unibus Options

Remote Diagnostic Module

1-3

System Introduction

11/750 Physical Inspection

Front Panel

Card Locations

Backplanes

Power

Diagnostic Overview

1-4

System Introduction

---.. ...__._ .... -

Figure 1-1 Course Map

1-5

System Introduction

Basic Architecture
1.

Comet Specifications
a.

Micro-controlled machine

Similar 32-bit architecture except:
(1) Use of LSI curcuits (gate arrays)
(2) Increases reliability
(3) Decreases size

Virtual 32-bit addressing (hexidecimal)
(1) 4.3 billion virtual processes
(2) 2 meg max physical (moss - batt.
min.)

backup 10

Two modes of operatiton
(1) Native (VAX VMS)
(2) Compatibility (PDP-11)

Remote Diagnostic Capability
(1) Company owner module
(a) Increase level of service
(b) Improves field service efficiency

Power
(1) 115 or 230 volts

Physical Characteristics
a.

40 inches high, 30 inches deep, 29 inches wide

Five basic sections
(1)
(2)
(3)
(4)
(5)

CPU - 4 boards - 3 major buses
Options - CPU and I/O
Front Panel
Backplanes - Comet and Unibus
Power

1-6

System Introduction

What Is an 11/750 Gate Array?
400 identical two transistor cells which can:
1.

Be connected to form 4 input NAND

Together with a neighboring
form 4 input NAND or AND.

cell

connected

44 identical transceiver cells which can:
1.

By disconnecting the receiver, be a TTL, Tri-state
or open collector drives (Internal array to outside
world)

By disconnecting the driver, be a TTL receiver (high
impedance)

Both

Implementation Technique - Gate Arrays
Circuit Technology - Low Power Dipolar Schottky
Circuit Density - Large Scale Integration (LSI)
Die Size - .215 inches X .244 inches
Power Utilized per Die - 2 watts max
Package Size - 1.44 sq. in. (2.4 inches X 0.6 inches)
Number of Pins/Package - 48
I/O Circuits/die - 44 I/O transceiver gates
Logic Gates - 400 identical 4 input NAND gates
Voltage Used - +2.5 volts, +5 volts
Speed per Gate - 5-10 nanoseconds
Unique Gate Array Types
CPU and Memory Controller - 27
Floating-Point Accelerator - 7
Mass Bus Adaptor - 5
Total Number of Gate Arrays Used:
CPU and Memory Controller - 55
Floating-Point Accelerator - 28
Mass Bus Adaptor - 12

1-7

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......
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CD
I-'

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N

0
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00

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IS EQUIVALENT TO

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c:
......
rt
Ul

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0

.......
0

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LOGIC CIRCUIT EQUIVALENCES
TK·2098

W-BUS

UBI

8
TU58
INTERFACE

DATA
ROUTING
ANO
ALIGNMENT'

CONSOLE
INTERFACE

5
MEMORY
CONTROL

TRANSL
BUFFER

ARRAY

WCSPRES

MICROSEOUENCER
& TRAPS·

INTERRUPTS

ADDRESS
LOGIC

DATA
PATH

CACHE

INTERNAL MEM BUS

MBUS
UNIBUS
INTERFACE

CMI

FLOATING
POINT
ACCEL

CPU
CONTROL
STORE

.......
I
\0

WRITABLE
CONTROL
STORE
MASSBUS
ADAPT.

sous
2 T.

UNIBUS

(/)

-r:- .

DZ-11

RL02
CONTROLLER

LP 11
CONTROLLER

...

- -

"'<:

!3
H

RM03

::s

RM03

_. _ _J

l"1

c:
VT 100

DRIVE 0

DRIVE 1

LP04

......
0
::s

COMET SIMPLIFIED SYSTEM BLOCK DIAGRAM
TK 2079

Figure 1-3

11/750 Simplified Block

System Introduction

Block Diagram Analysis
1.

CPU - Four Boards
a.

Data path module (slot 2) bPIY"a

(1) Functions
(a) Control Microsequencing
(b) Arithmetic actions
{c) Generate basic CLK from OSC on CCS

(2) Contents
(~)

(b)
{c)
(d)
(e)
b.

Super Rotator
ALU
64 GPRs
Interval timer and basic CLK
Microsequencer

Memory Interconnect Module (Slot 3) /tlLC

(1) Functions
(a) Acts as memory management by making
physical address from virtual address
(b) Checks for that physical address to find
if it is located in memory
(c) Stores data in a lK cache for quick use
by the CPU
(d) Holds "PC" (program counter) to allow
CPU greater efficiency.
(Updates the PC
without CPU microintervention.)
(e) Due to VAX data and instruction storage
it aligns data or
instructions to
useable positions for DPM.
(f) Generates
microtraps
interrupts and exceptions

for

needed

(2) Contents
(a) Address Logic
(b) Translation
Buffer
associative cache
1-10

2-way

set

System Introduction

CPU Control Store (Slot 5) C5S
(1) Functions
(a) Hold proms (microprogram)
(b) Mother board for WCS option
(c) Works in conjunction with microsequencer
(2) Contents
(a) Proms for ,80 bit, microword (lK)
(b) Snap on for WCS

CPU Unibus Interface Module (Slot 4) UC,'I
(1) Functions
(a) Interface the TU58 cartridge tape to
operating system. TU58 used possibly for
booting
the
system or
loading
of
diagnostics.
One chip, serial data
between TU58 and interface.
Parallel
between interface and CPU.
(b) Interface
the
console
terminal
so
operator may talk to system.
May be
used as user input.
Once chip serial
data between console and interface.
Parallel between interface and CPU.
(c) Interface for all data
between CPU and unibus.
(d)

Generates all interrupts
massbus
devices,
TU58
terminal.

passed

from unibus,
console
and

(e) Acts as generator for time of year (TOY)
clock.
To keep system informed as to
correct time.
Battery run.
(Batteries
included)

1-11

System Introduction

Buses: M, W, CMI
(1) Functions - to interconnect via etching on
backplane all sections of CPU to allow them
to communicate•'
(a) M Bus - used to transmit data to and
from scratch pad registers, memory data
registers,
PC,
virtual
address
registers, PC, virtual address registers
and data path module.
Also included is
data to and from FPA.
(b) W Bus - originates at ALU in DPM and
xmits
data
to
data
routing
and
alignment,
address
logic,
uni bus
interface and FPA.
(c) CMI Bus - (CPU Memory Interconnect) etch
on backplane that connects CPU to all
I/O buses and memory for data exchange.
Synchronous interlocked 160 nanosec
cycle.
(2) Contents
(a) M Bus - data lines <31:0>
(b) W Bus -.data lines <31:0>
(c) CM! Bus - 45 lines
32 data/address
1 wait
iii. 1 hold
iv. 1 busy
v.
7 arbitration lines
vi. 2 status
vii. 1 8MHZ clock
i.
ii.

1-12

System Introduction

32 DATA/ADDA.

1 WAIT

DATA/ADDRESS (35)

ARBITRATION (7)

1 HOLD
1 BUSY

3MBA
1 UBI

1 ROM
2 RESERVED
NEXUS

NEXUS

STATUS (2)

6.25 MHZ B CLOCK (1)

THE CMI STRUCTURE
TK-2064

Figure 1-4

CMI Structure

1-13

System Introduction

Memory - two to nine modules
a.

Controller module (Slot 10)
(1) Functions
(a) Controls data moving to-and from CMI and
memory
(b) Controls
memory

refresh

circuitry

for

moss

fast
used
controller

between

CMI

and

ii.

slow - used between controller and
memory

(b) Error correcting circuitry
(c) Up to 4 boot ROMS
(d)
b.

refresh circuitry

Array Boards - up to 8 (slots 1 -> 8 in hex)
(1) Function meg

hold data

for

storage -

up to 2

(2) Content
{a) 256K of mos¥ each board
(b) max 8 boards
c.

Memory Internal Bus
(1) Function - carry data addresses and control
signals between controller and memory
(2) Contents
(a) 39 data lines

1-14

Systen Introduction

(b) 7 multiplexed chip address lines
(c) Two address lines for 16K 39 grp select
(d) One ROM address strobe or column address
strobe
(e) One read/write control
3.

Options
a.

CPU options - 2 boards
(1) Writeable control store (slot 5 in ex-hex)

(a) Function - allow programmer to write his
own microcode. Ex: subroutine
(b) Contents-RAMs, board is plugged to CCS
(2)

Floating-point
ex-hex)

accelerator

(slot

(a) Function - used for working arithmetic
functions which have large numbers o-f
many decimal places
b.

Massbus Options - maximum of 3 adaptors (slots 7
-> 9 in ex-hex)
(1) Function - to interface data between one of
8 devices possible on each adaptor to the
CMI bus. Devices could be used for storage
of operating system, space for user programs
or overall virtual memory space.
(2) Contents
made
standard logic

LSI

arrays

Note
Interrupts from massbus devices are given
a BR4 level and passed to CPU via unibus
interface board.
To receive BG back it
must have the BG jumper removed if
adaptor is present in a slot.

1-15

and

System Introduction

Unibus Options (slots 1 -> 9 unibus backplane)
(1) Function - many and varied according to what
devices are purchased.
DZll is normally
bought to interface up to 8 user terminals.
(2) Contents - relative to what is purchased,
but will always have M9313 for end of the
bus termination and diagnostics.

Remote Diagnostic Module (slot 6 ex~hex) Rb/Vl
(1) Functions
(a) Needed to run microdiagnostics
(b) Run macrodiagnostics from remote site
(c) If macros won't run,
between CPU and memory

differentiate

(d) Utilize TU58 as backup source for
hardcore, cache/TB diagnostic supervisor
in case mass medium is down
(e) Down line load of micros is not a goal
(2) Contents
(a) RAMs - to hold microdiagnostic monitor
(b) DCS
(Data
Control
Store)
to
microsequencers loaded by monitor

1-16

hold

t'J:j
.....

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t"1

.......
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CABLE
TO
SEPARATE
BOX

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UNIBUS

HEX

.....

EXTENDED HEX

::s

BACKPLANE CARD LOCATION
FRONT VIEW

ITK-3210

System Introduction

__., -

HEX

EXTENDED HEX

- ·- -·
,, 2 3 4 ··-5. 8 7 8 9 10 1 2 3 4 5 8 7 8 9
-·-

UNIBUS

11.-i

1 2 3 4 5 8 7 8 9
l

c
F

1•
•94 PINS TWO STRAIGHT ACROSS

3•

5•
--

•2

.. _.~

•4

•8

=36 PINS lWO STRAIGHT ACROSS, DEC ALPHABET

•36 PINS TWO OFFSET ACROSS, DEC ALPHABET

A1•

•A2

81 •

• B2

•C2

A1•
81•

•A2
• 82

Ct•

•C2

BACKPLANE
REAR VIEW

Figure 1-6

Backplane Rear V~ew

1-18

--'

-_.-

SEPARATE DD-11DK
BACKPLANE

TK-3211

System Introduction

1· •

3.
5 •

2
1
e A•
• B

• 2
• 4

7 •

• 6
• 8

• c ••

• 10

• D •

•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
• •
• •
• ••
•
• •
• ••
•• •
• •
• •
• •
• •
• •
• •
•• •
•
• •
• •
•
•• 90
89.
91.
93.

• E •

• F •
•.H •

• J •
• K •

• Le
• M•
• N•

• p •

• sR •
•• T •
u •
•• v.

HEX PIN BREAKOUT

!2
Ae

•• B

•
•• D
•
• • EF •
•
• • JHe
•
• K•
• L •
• M•
• N
•
• p•
• R
•
• •Ts •
•
• •Vu •
·•
c •

UNIBUS PIN BREAKOUT

• 92
• 94

- --·

EXTENDED HEX
PIN BREAKOUT

COMET BACKPLANE PIN BREAKOUTS
TK-3213

Figure 1-7

11/750 Backplane Pin Breakouts

1-19

System Introduction

llOWIR RIEF
-J1 J2 J3-

J1-

+11 -lli +58

J2-

1 4 7

141

211
319

2 5.
3 I I

GNO GND +58
+12 GND-58
Ol'TIDN SLOT BUS GRANTS
REMOVE JUMPER

TOS!:l.ECT
8G<t
BGS
BGI
BG 7
X-SLOT7.8.8

AOOX 17

AOOX 61
"'30X 73
AllOX

:Bl

~~":'! ~ ~ ~

Ci
Q

:El

1:1

1:
2

TUTl'OINTS
RDM 19

ROM 23
ROii

Dl'M 17
Dl'M 17
Dl'M 17
MIC

°"

Dl'll 17

=~
RDMA8SENT

llDMPflESENT

z
1:1
~

5
B
50

MATCH PULSE
SA CLOCK
SAST/SP
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CDOUI
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IASECLOCIC
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800209

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1
2
3

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illll4l3
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800449

4
5

I
7

l!IOl)WI

llOOM8

CONSOLE BAUD RA TE

COHBR
RA.TE

300

o·.

600

1200
2400
3600

I
1
1

0
0
0

I
I

1
1
I

1
I

....,
9600
l9:IOD
33400

I
1

1
1
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0
0
1
0

. i

!'IN#

COOIMS

COOMI CllO&W

COllli50

JUMPER

COOIM3

COOIW4

COO&!il

C00652

T'OGNO

1 4 1

251
311
J3-

Figure 1-8

ACL mtl.ocL r'l'lrov

'L.!.!.!1

J4-

JS-

Jumper and Cable Connections

1-20

System Introduction

MICRO
VERIFY

ROM

CONSOLE FUNCTIONS
(ROM FIRMWARE)

MICRO
DIAGNOSTICS

CPU 'KERNEL
HARDCORE'
INSTRUCTION TEST

...

CPU
CLUSTER

110

DIAGNOSTIC
SUPERVISOR

1/0 INTERCONN.
(DR&MAI

MEMORY
DIAGNOSTIC

MA.~ STORAGE

DRIVE, DEVICE, PER·
FORMANCE ANALY./
FUNCT. TIMERS

SU.:r::MS---~-~-~v_l=-~-BAS_STS_•c____

l/OCHANNEL
(MBA&UBAI
DIAGNOSTICS

COMM ADAPTER
INTERFACE
DIAGNOSTICS

VMS

DIAGNOSTIC
SUPERVISOR

CPU CLUSTER
EXERCISER

MASS STORAGE SUB
SYSTEM FUNCTION &
RELIA/ACCPT. TST

UNIT RECORD/COM
ADAPTER FUNCT.
DIAGNOSTICS

SYSTEM EXERCISER
&

BUS INTERACTION

VAX/COMET DIAGNOSTIC
SYSTEM OVERVIEW
TK-3209

Figure 1-9

VAX Diagnostic Overview

1-21

System Introduction

The next section describes the diagnostics available on the
11/750 their different levels of usage. The names and
locations of all diagnostics be found on micro fiche under
ZZ-EVNDX. There is an other tape [TU58] lable to the field
· that is n6t concerned with diagnostics; that being CONSOLE
tape which has the BOOT 58 program and BOOT command files
locates it. That tape is not listed here and will be
discussed later.
This is the beginning of diagnostic overview.
Diagnostics are broken down into five levels, four of which
are numbered 1-4; The remaining level is microdiagnostics.
LEVEL 1. These are diagnostics that run under the VMS
operating system and not using the diagnostic
supervisor. EX. UETP (not a diagnostic, an
excersiser) •
LEVEL 2. These are diagnostics that run under the diagnostic
supervisor while the VMS system is still operating.
EX. Reliability and acceptance tests, line printer.
LEVEL 3. These are diagnostics that run under the diagnostic
supervisor while the VMS system is not running. The
diagnostic supervisor must be running stand alone.
EX. UBI DIAGNOSTIC.
LEVEL 4. These are diagnostics that are run stand alone
without the diagnostic supervisor or VMS operating.
EX. Hardcore instruction.
MI CR Os

These are diagnostics that are loaded from the TU58
and run from the RDM RAM memory. There will be a
total of four;
1. DPM micro [data path]
2. MIC micro [memory interconnect]
3. CMC micro [memory controller]
4. FPA micro [floating point]
Of these four only the first two are available as
of August 1, 1980.
There is another diagnostic that is run every time
the machine is powered up or the Initialize button
is pushed. This is called micro verify. This is
resident in the machine inside the microcoded CSC

1-22

System Introduction

module and checks the basic sanity of the data path
and mic module before any other operations are
performed. This is discussed in its entirety in a
later section.
There are some diagnostics that may be run under
level 2 or 3 and should not be thought of as just
level 2 or 3. These will be discussed as we reach
them.
The following is a list of the diagnostics
that are available and which TU58 tape they
are distributed on.
The following four tapes are run at the micro level to check
the CPU. They are not to be run in their numerical order for
troubleshooting purposes. Order for troubleshooting will be
discussed later.
TU58 TAPE il: VAX 11/750 MICRO DATA PATH [DPM]
ECKAA~EXE
MICRODIAGNOSTIC MONITOR [MM FROM NOW ON]
ECKAB.EXE MICRODIAGNOSTIC DPM
TU58 TAPE #2: VAX 11/750 MICRO MEMORY INTERCONNECT [MIC-]
ECKAA.EXE MM
ECKAC.EXE MICRODIAGNOSTIC MIC
TU58 TAPE i3: VAX 11/750 MICRO COMET MEMORY CONTROLLER [CMC]
ECKAA.EXE MM
ECKAD.EXE MICRODIAGNOSTIC CMC
TU58 TAPE #4: VAX 11/750 MICRO FLOATING POINT [FPA]
ECKAA.EXE MM
ECKAE.EXE MICRODIAGNOSTIC FPA
[TAPE 3 AND 4 NOT RELEASED AS OF AUG. lST 1980]
The following
than MICRO.

four

tapes are used to test the

CPU levels other

TU58 TAPE #5: VAX 11/750 CACHE/TB;MEMORY;CLUSTER EXCERSISOR
ECKAL.EXE CACHE/TB [BOOTABLE;LEVEL 4]
ECKAM.EXE MEMORY DIAGNOSTIC [LEVEL 3]
ECKAX.EXE CLUSTER EXCERSISOR [LEVEL 3]
TU58 TAPE i6: VAX 11/750 DW 750 [UBI];DIAGNOSTIC SUPERVISOR
ESSAA.EXE DIAGNOSTIC SUPERVISOR [ONLY TAPE TO CONTAIN
THIS BOOTABLE]
ECCBA.EXE UBI DIAGNOSTIC [LEVEL 3]

1-23

System Introduction

TU58 TAPE #7: VAX 11/750 HARDCORE INSTRUCTION
EVKAA.EXE HARDCORE INSTRUCTION [BOOTABLE;LEVEL 4]
TU58 TAPE i8: VAX 11 INSTRUCTION TESTS
EVKAB.EXE VAX ARCHITECTURAL INST. [LEVEL 2 AND 3]
EVKAC.EXE VAX FLOATING POINT INST. [LEVEL 3]
EVKAD.EXE VAX COMPATIBILITY MODE INST. [LEVEL 3]
EVKAE.EXE VAX PRIVILEGED ARCHITECTURAL INST. [LEVEL 3]
Remaining tapes that follow are to be used to test options
available on the 11/750. These will be [as the previous
tapes #7 and 8] the same diagnostics that are run on the
11/780. To determine which level the diagnostics will be run
at you will need to read the associated manual.
TU58 TAPE 19:
EVQDR
EVQDM
EVQDL
EVABA
EVRAA

EVRACX

VAX CR/DISK USER MODE
VAX LOADABLE DRIVER FOR RMOX/RM 80
VAX LOADABLE DRIVER FOR RK611-RK06/07
VAX LOADABLE DRIVER FOR RL11-RL01/02
VAX CRll CR DIAGNOSTIC
VAX RP/RK/RM/RX/TU58 RELIABILITY
VAX DISK FORMATTER

TU58 TAPE #10: KMCll/DMCll/DZll
EVDMA
VAX M8203 REPAIR LEVEL
EVDXA
VAX COMM IOP REPAIR LEVEL
EVDAA
VAX DZll 8 LINE ASYNC MUX
TU58 TAPE ill: RK6ll DIAGNOSTICS #1
EVREA
VAX RK611 DIAGNOSTIC PART A
EVREB
VAX RK611 DIAGNOSTIC PART B
TU58 TAPE #12: RK611 DIAGNOSTICS #2
EVREC
VAX RK611 DIAGNOSTIC PART C
EVRED
VAX RK611 DIAGNOSTIC PART D
EVREE
VAX RK611 DIAGNOSTIC PART E
TU58 TAPE #13: RK611 DIAGNOSTICS i3
EVREF
VAX RK06/07 DRIVE FUNCTION TEST PART 1
EVREG
VAX RK06/QJ7 DRIVE FUNCTION TEST PART 2
TU58 TAPE #14: RM03/RM05
EVRDA
VAX RM03/RM05/RM80 DISKLESS
EVRDB
VAX RM03/RM05 FUNCTIONAL TEST
TU58 TAPE #15: TSll DIAGNOSTICS
EVQTS
VAX LOADABLE DRIVER FOR TS11/TS04
EVMAA
VAX TM03/TE16/TU45
EVMAD
VAX TSll SUBSYSTEM REPAIR

1-24

System Introduction

TU58 TAPE #16: RL02 SUBSYSTEM FUNCTIONAL DIAGNOSTICS
EVRFA
VAX RL02 SUBSYSTEM FUNCTIONAL DIAGNOSTICS
EVRGA
VAX RM80 FORMATTER
EVRGB
VAX RM80 FUNCTIONAL DIAGNOSTICS
As of August 1, 1980 the above were the only diagnostics
proven compatible with both the 11/780 and 11/750. The
following are the remaining diagnostics that are planned.
POSSIBLE ONE TAPE:
ESDRB
VAX DRllW DIAGNOSTIC
VAX DRllW REPAIR LEVEL
ES DRE
POSSIBLE 2ND TAPE:
ESDBA
VAX M8201/2 REPAIR LEVEL DIAGNOSTIC
VAX DMCll EXCERSISOR PROGRAM
ESDBB
POSSIBLE 3RD TAPE:
VAX DUPll REPAIR LEVEL PART 1
ESDUP
VAX DUPll REPAIR LEVEL PART 2
ESDUQ
Please note that all diagnostic (not including the micro
diag. or EVKAA and ECKAL) that relate to your system will be
sent with the system pack as part of the system on whatever
medium your VMS is incorporated in.

1-25

VAX 11-/750 LEVEL II

Console Command Language
and Bootstrap Process

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Console Command Language and Bootstrap Process

OUTLINE
II. A.

Console Command Language
1.
2.
3.
4.

Control Characters
Console Command Symbols
Console Commands
Errors and Illegal Characters

Bootstrap Process
1. Definition
2. Different Boot Methods
3. How Boot is Accomplished
4. Boot 58
S. Automatic Boot
6. System Shutdown
7. Copy Console Device Files

2-1

Console Command Language and Bootstrap Process

INTRODUCTION
This lesson introduces the student to the VAX console
commands needed to communicate with the VAX-11/750. After
becoming familiar with the commands and their functions in
the classroom, a lab session will be provided to utilize
each command. The lab session will allow the student to
initialize the system and perform deposits and examinations
to various registers and memory locations.
This lesson also covers the VAX-11/750 bootstrap process. By
using flowcharts, the process will be covered from device
selection to error indications. Once the process has been
covered by lecture, a lab session will be utilized to
reinforce the concepts and to demonstrate error conditions.

2-2

Console Command Language and Bootstrap Process

OBJECTIVES
1. Using console commands, initialize the system.
2. Using console commands, deposit data to a register.
3. Using console commands, examine data in a register.
4. Boot the system.
5. Given the console printout indicating a
clear the fault by locating the problem.

boot

failure,

SAMPLE TEST ITEM
This console printout occurred while booting the system with
FPSl set to boot.
% %

xxxxxxxx

>>>

What is indicated to the operator?
a.
b.
c.
d.

A 64K bytes of good memory not found
A nonexistent boot ROM
A HALT was executed
Wrong Rev. level
RESOURCES

1. VAX 11/750 RDM Maintenance Card
2. VAX 11/750 Diagnostic System Overview Manual

2-3

THE BOOT COMMAND

>>>B(/X][/<n>] (<SPACE><ddcu>]<CR>

THE CONSOLE

__
tl'

PROMPT~~~~~~~~---

THE BOOT COMMAND

INHIBIT MICRO VERIFY
(DEFAULT IS, PERFORM MICRO VERIFY)--------SELECT A BOOT CONTROL
FLAG (DEFAULT IS, FLAGO; (CONVENTIONAL BOOT))
N

MNEMONIC

DL
OM
DB

INSERT A SPACE HERE
IF MANUAL BOOT SELECT IS TO BE

DD
USED~~~~~~~~-

REPRESENTS THE BOOT
DEVICE.
IF NOT USED, DEFAULT TO THE BOOT DEVICE
SWITCH ON THE FRONT PANEL. THIS MUST BE
USED WHEN SELECTING A BOOT CONTROL FLAG OTHERWISE THE FLAG IS IGNORED.~~~~~~~~~~~~~~~~~dd IS A TWO LETTER DEVICE MNEMONIC (SEE CHART)
IS A I/G CHANNEL ADAPTOR. A,B,C, OR D.
u
IS THE DEVICE (dd) DRIVE NUMBER.

ENTRY COMPLETED BY
CARRIAGE RETURN~~~~~~~~~~~~~~~~~~~~~~~~~--

DEVICE

RL"2
RK0'i/7
RP04/5/f;
RMA3
TU58

Console Command Language and Bootstrap Process

BOOT CONTROL
FLAG

FUNCTION

/<N>

CONVERSATIONAL BOOT.

DEBUG

INITIAL BREAKPOINT

NOT USED WITH VAX 11/750

DIAGNOSTIC BOOT

BOOTSTRAP BREAKPOINT

IMAGE HEADER

MEMORY TEST INHIBIT

FILE NAME

100

HALT BEFORE TRANSFER

200

BOOT CONTROL FLAG FUNCTIONS

2-5

THE DEPOSIT COMMAND

>>>D[<qualifier-list>] [<space><address>]<space><data><cr>
CONSOLE PROMPT
DEPOSIT COMMAND
SIZE & SPACE
/B
/V
/W
/P
/L
/I
/G
TO SELECT A
DEPOSIT ADDRESS
OTHER THAN 0
<nnnnnnnn> -- HEX ADDRESS
<*>
LAST LOCATION
<P> -- PSL
<+> -- NEXT LOCATION
YOU MUST SELECT A
HEX VALUE (1-8 DIGITS)
OPERATION COMPLETED

THE BOOT/BOOTSTRAP AS DEFINED BY THE
DEC DICTIONARY - PG 28

boot (boots, booting, booted)* v. (See also bootstrap.)
To bring a device
or system to a defined state where it can operate on its own.
EXAMPLE(S):
The operator boots the system before starting operation.

I
.....,

boot (boots)* n.
A protective housing, usually made from a ~esilient
material, used to protect connectors or other terminals from moisture.
EXAMPLE (S)
Pull the boot up over the plug to make the connection
waterproof •
bootstrap (bootstraps, bootstrapping, bootstrapped)* v.
(See also
boot.)
To bring a device or system to a defined state where it can operate on
its own.
EXAMPLE(S):
You must bootstrap the system before logging on.
bootstra~

(bootstraps)* n.
A technique or device designed to bring a system
or
ev ice into a desired state by means of its own action, e.g., a
machine routine whose first few instructions are sufficient to bring
the rest of itself into the computer from an input device.
EXAMPLE(S):
Using the bootstrap saves time.

CONSOLE MICROCODE EXAMINES THE BOOT DEVICE
AND POWER ON ACTION SWITCHES ON THE
FRONT PANEL;
o

When you initially apply power by turning the front panel keyswitch

When recovering from a power failure

When the operator pushes the front panel initialize switch.

After a software "CRASH"

2-8

Console Command Language and Bootstrap Process

BOOTING WITH FRONT PANEL SWITCHES
FRONT PANEL
KEYSWITCU
POWER ON

POWER

FAILURE
RECOVERY

INITIALIZE
PUSH BUTTON

COME UP

UAL TEO

BOOT SYSTEM

VIA DEVICE A

8001 SYSTEM

VIA DEVICE B

BOOT SYSTEM

VIA DEVtCE C

CONTll'1lJE

EXECUTION
BOOT SYSTEM

VIA DEVICE D

Figure 2-1

2-9

SOFTWARE
CRASU

Console Command Language and Bootstrap Process

SOFTWARE BOOT CONTROL FLAGS
( 1 of 2)
Flag

Hex
Value

Function

Conversational boot.
At various points
in the system boot procedure, parameters
and other inputs will be solicited from
the console.

Debug.
This flag is passed through to
VMS and causes the code for the executive
debugger to be included in the running
system.

Initial breakpoint. If this flag is set,
and the executive debugger code is
included (flag bit 1), then a breakpoint
will occur immediately after the exec
enables mapping.

Not used on the VAX-11/750.

Diagnostic boot.
by
file
name
supervisor.

2-10

This flag causes a boot
for
the
diagnostic

Console Command Language and Bootstrap Process

SOFTWARE BOOT CONTROL FLAGS
(2 of 2)
Flag

Hex
Value

Function

Bootstrap break po int.
This flag causes
the bootstrap to stop at a breakpoint
after
performing
necessary
initialization.

Image Header.
If this flag is set, the
transfer address from the image header of
the boot file will be used.
Otherwise
control will transfer to the first byte
of the boot file.

Memory test inhibit.
the
testing
of
bootstrapping.

100

File name.
Causes the bootstrap
solicit the name of the boot file.

200

Halt before transfer.
Causes a HALT
instruction to be executed prior to the
transfer to the secondary boot file.
This option is useful for debugging
purposes.

2-11

This flag inhibits
memory
during
tp

Console Command Language and Bootstrap Process

BOOT DEVICE CODES (ddcu)
DEVICE CODE (dd) *

DEVICE TYPE
RL02
RK06/07
RP04/05/06
RM03/RP07
TU58

DL
DM
DB
DR
DD

Identifies
block.

the

device

that

storing

the

boot

CHANNELS ADAPTER (C)

To which port is the Device (dd) channeled to.

DRIVE NUMBER (u)
0} on which drive of our device (dd)
1 our boot block located.

2-12

CONSOLE COMMAND ERROR CODES

If an illegal console command is attempted or command is aborted because of
a microtrap or some other condition a two digit error code is typed out and
the console waits for new input.
For example •••
>>>E P<CR>
>>>E<CR>
?11
>>>

!Examine PSL
!Implies Examine Next Location, this is illegal.
!Question Mark and error code is typed by console
!At this point ready for new command

Error Codes

20=

Deposit or Examine of Memory Failed (Access Violation,
Translation not valid, Bus Error, TB Parity Error, or Control
Store Parity E
11= Illegal access of an ipr
30= Apt Loading Checksum error
33= Attempt to Boot from unknown Device type (DM,DL,DO)
34= Boot Device Controller not "A","B","C", OR "D"

Console Command Language and Bootstrap Process

ROM STARTING ADDRESSES

DEVICE ROM

STARTING ADDRESS

FA02

FB02

FC02

FD02

2-14

CONSot E SUBSYSTEM ACTION ON bOOT

I
FINO GOOO
ti4K Of
MC:MOHY

Cll:Alt llNlll
COLO~lAHf HAG

CttECK FOR
NONEXISlAN1
ROM

CHECK COlO
START HAG

()

TYPE CONSOLE
HALT ERROR
COOE,.. 14. PC
ANO PROMPT

TYPE CONSOll.
HAU ERROR
COOE"' 16. PC

. -SHW

......
Cl)

()

-STOP-

l Yi't.
MICRO VERIFY
ERROft CODE;ff
PC & PROMPT.
-SJOf'

WHITE
UBI
MAP

FLAG

COlOSTART

IROI Of
ROM HOUllNE
LOAO 8001
Bl.OCK
-

Ul.il

SET COISABlE)

1Ntl1All2E

TYPl ~ ..
AT CONWl[

TYPE CONSOLE
UAL T EHROH
coot= tJ. PC
ANO PHOMPT
STOP

PC tuUflM
MICHO v'EHlf Y

!:l

.,,........

!3
!3
Q.I

!:l

0..

t""'
Q.I

!:l

"°c
"°

LOAOINPUT
ARGUMENTS
FOR ROM COOE
ANOVMB

Q.I

Cl)

Q.I

!:l

0..

TYPl: ~[CONll
%
AT CONSOt £

lOAO ALL
OOOT ROMS
INTOMEMOHY

SHECT ROM
COOE POINTED
10 BV BOOT
.DEVICE SWITCtt

0
0
rt

""'Q.I

t-0

lOAU P~L

"t1
l"1

0
0
Cl)

en
en

..... ,,,

Console Command Language and Bootstrap Process

INPUT ARGUMENTS
The general registers
console subsystem.

receive the

input arguments from

the

Rl -

system bus address of a Massbus adapter (MBA0 unless
otherwise specified in the Boot command).

R2 -

physical address of the Unibus I/O page
with a Unibus adapter
(UBI0 unless
specified in the Boot command).

R3 -

device unit number
the Boot command).

RS -

software boot control flags
(0
specified in the Boot command).

SP -

<base address
memory.

associated
otherwise

(0 unless otherwise specified in

+ "X200> of the

unless
64K

bytes

C(SP)- transfer address of the boot block code.

2-16

otherwise
of

good

FUNCTIONS AVAILABLE UNDER BOOT 58
o

Load and start level 4 diagnostic programs.

Bootstrap from the Massbus adapter

Bootstrap from a disk whose boot block is bad.

Bootstrap from a disk whose error rate prohibits ROM
and boot block loading of a primary bootstrap.

Boot the diagnostic supervisor instead of VMS.

Deposit and examine data in physical memory, general
registers, and internal processor registers.

Load and start a program from a magtape drive on a
Massbus.

Store and invoke indirect command files on the TU58
cartridge to per~orm any of the above functions
automatically as well as interactively.

2-17

Console Command Language and Bootstrap Process

POWER UP AND BOOT ERROR REPORTS
xxxxxxxx 13

>>>
xxxxxxxx 14

>>>
xxxxxxxx 06

This indicates that a good 64KB section of
memory was not found and return to console
mode
This indicates a failure or nonexistance of
the boot ROM
If a halt instruction is executed after
typing
a
console boot command,
this
indicates a failure of the read of logical
block 0 from the selected boot device, the
PC should be equal to the base address of
the first good 64KB of memory plus FX16 for
TU58 or FX20 for RK06.
This failure occurs
in the Boot ROM routine.

2-18

Console Command Language and Bootstrap Process

VMB PRIMARY BOOT FAILURES
BOOT is the program name for VMS.EXE
The "F" indicates a fatal error and
reported.

the

type

error

%BOOT-F-Unknown processor

This indicates that CPU is
not a Comet or 11/780,
check SID register for
proper jumpering in the
CPU type field on the
Backplane.

%BOOT~F-Unexpected Exception

This indicates that one of
the following exceptions
occurred.
1. Access Violation
2. Breakpoint Opcode
3. Reserved Operand
4. TBit Trap
5. Page Fault (TNV)

%BOOT-F-Unexpected Machine Check

This indicates some sort
of machine Check occurred.
Check all adaptors using
console
examine
and
deposit
commands.
Probably a timeout.

%BOOT-F-Nonexistant Drive

Self explanatory, Check
DEFBOO.CMD on 11/780 and
insure
system disk
is
drive being booted.

%BOOT-F-Unable to locate BOOT
file

VMS
can't
find
[SYSEXE]SYSBOOT.EXE or if
bit 4 in RS is set, VMS
can't
find
[SYSMAINT]DIAGBOOT.EXE

%BOOT-F-Bootfile not contiguous

Indicates
that
[SYSEXE]SYSBOOT.EXE
or
[SYSMAINT]DIAGBOOT.EXE is
not contiguous on system
disk.
Recopy or rebuild

%BOOT-F-I/O error reading boot
file

Indicates problem reading
boot file from disk by
$QIO service (VMS System
Service) •

2-19

VAX-11/750 LEVEL II

System Overview

Student Guide

Course produced by Educational Services Department
of

Digital Equipment Corporation

SYSTEM OVERVIEW

INTRODUCTION
This lesson is developed to give you a basic understanding
of location of Gate Arrays in 11/750 prints and overall
understanding of how each board (DPM, MIC, UBI, and CCS) is
laid out. All of the data given out in this section will be
reiterated when each board is gone over in detail. You
should start to form concepts of how the machine works
functionally and how the prints are set up. There will be
very little in the Student Guide so listen, take notes in
your prints or Functional Block.

4-3

SYSTEM OVERVIEW

OBJECTIVES
The student will be able to locate all gate arrays in the
prints relating to the four basic LPU boards, DFM, MIC, UBI
and CCS.
The student will be able to take a MOVL LONG instruction and
follow the path of the data from beginning to end.

SAMPLE TEST ITEM
The access control violation chip is located on which board?
1. DPM
2. MIC
3. UBI
4. ccs

RESOURCES
11/750 Print Set
11/750 Functional Block

4-4

SYSTEM OVERVIEW

The CPU Overview
1. Board common to all CPUs four (4) each
a. Unibus Interface
hex section)
1)
2)
3)
4)

TU58 Data in and out
Console Data in and out
Handles interrupts
Interfaces Unibus data and CPU data with each
other

b. Data Path Module
section)
1)
2)
3)
4)

(UBI Module - Slot 4 of extended

(DPM -

Slot

extended

hex

Contains the arithmetic logic
Contains the rotator logic
Houses the Scratch Pad logic (Registers)
Also houses the Microsequencer logic

c. Memory Interconnect (MIC Module extended hex section)

Slot

3 of

the

1) Contains the address logic (PC)
2) Houses the Translation Buffer which translates
virtual addresses to physical addresses
3) Cache
4) Contains the Data Routing and alignment which
handles the routing of data in and out of or to
and from memory and the data path.
d. CPU Control Store (CCS Module - Slot 5 of extended
hex section)
1) Contains
Microcode

the

Control . Store

ROMs

2) Houses the optional snap on WCS Module
B.

Component Analysis
1. CPU Control Store (CCS)
a. 6K x 80 Bits, no gate arrays
2. Data Path (DDPM) - 22 gate arrays
a. Gate Array Chips

4-5

for

the

SYSTEM OVERVIEW

1) The microsequencer (MSQ) - Sequences the CPU
microcode that controls most operations (NOT
SHOWN AS ONE CHIP ON BLOCK SHOW IN PRINTS)
2) Practically Half the Buts (PHB) - Contains some
of the bits of the PSL, the status flags and
the step counter. It also contains the logic to
generate half of the but micro orders.
3) Service Arbitration and Clock (SAC)
Deals
with the IRD counter, service arbitration, and
the system clock.
4) Condition Code Chip
(CCC)
Deals with
condition codes. It determines the condition
codes for both VAX and compatability mode
instructions,
stores
the
PSL
bi ts
<FU,IV,DV,N,Z,V,C>, reads the bits out at Ucode
request.
5) Instruction Register Decode (IRD) - Handles the
IR Decode. It receives an opcode and operand
specifier from the execution buffer (XB),
decodes it and creates the signals needed by
the microsequencer to process the appropriate
routine.
6) Super Rotator Control (SRK) - It controls the
functions of the Super Rotator (SR). The info
it needs to control the SR comes from the 6 bit
ROT field of the microcode. (NOT ON BLOCK IN
TOTAL, PRINTS.)
a. SPK chip contains the S and P latches and
their associated mux in and out. Controls
the super rotator via the ROT field of the
microword and certain Wbus inputs.
7)

Super Rotator Multiplex (SRM) - 4 ea - Perform
64 different operations via control of the SRK
chip.

Scratch Pad Addressing (SPA) - Controls the
operating of the 64 scratch pad registers, and
it provides a mechanism to undo the auto
decrementing and auto incrementing of the
general purpose registers.

4-6

SYSTEM OVERVIEW

Timed Operation Control (TOK) - Implements the
architecturally defined programmable interval
time clock.

10) Carry Look Ahead
(CLA)
An array of
combinational logic used to propagate and
generate carries for up to 8 ALU slices. (NOT
ON BLOCK, SHOW IN PRINTS.)
11) Arithmetic and Logic Control
BLOCK, SHOW IN PRINTS.)

(ALK)

-. (NOT ON

a) Reencodes the ALP control field
microword for special functions.

b) Controls the carry input and
for the ALP chips.

inputs

shift

the

c) Decodes the scratch pad write enable.
d) Decodes miscellaneous signals.
12) Arithmetic Logic Processors (ALP) - 8 ea Each chip is 4 bits wide. They form the
circuit that performs the majority of the data
manipulating
when
executing
macro
instructions.
3. Memory Interconnect Module (MIC) 18 Gate Arrays

Memory Data Registers (MDRs) - 8 ea - Major
portion of the data routing and alignment
circuit. They receive and hold data in/out
to/from the Mbus.

Prefetch Control (PRK) chip - Prefetch 8 bytes
of instruction data starting with the PC
address and replace used bytes as execution
progresses.

Address (ADD) chips - Contain the VA,
backup and VA save circuits.

Address Control (ADK) chip - Is the control
for the address logic and also works in
conj unction with the pre fetch control and
memory data regs.

4-7

PC,

SYSTEM OVERVIEW

Access
Violation
(ACV)
chip
Besides
detecting access violations it monitors and
detects.
a.
b.
c.
d.

Control store parity errors
FPA reserved operands
Unaligned data, including unibus data.
Crossing of page boundaries.

It then generates the. appropriate
signals to the Microtrap chip (UTR) •

Utrap

Microtrap (UTR)
chip
Monit0rs machine
conditions that can cause a microtrap.

The Cache control (CAK) chip - Controls the
enabling and disabling of cache, controls the
transfer of data to/from the MOR chips. Works
in conjunction with the CMK chip to invalidate
cache on CMI writes.

CPU Memory Interconnect Control
(CMK)
Monitors and transmits control signals to/from
the CMI bus.
(Busy and HOLD.) Stalls the
microcode for certain conditions.

4. Unibus Interface Module (UBI) 8 Gate Arrays
a. 1.

The TU58 Interface consists of a Gate Array
Chip (CON) and some associated logic that
allows communication between the CPU.

The console Interface consists of a Gate Array
chip (CON) and some associated logic that
enables communication between the CPU and its
console.

The interrupts circuit consists of a Gate
Array chip (INT) and some associated logic
that enable the handling of interrupts.

The Unibus interface consists of five (5) Gate
Array chips, a ROM and Unibus Map.
a. The Unibus Data Path (UDP) chips make up
the data path for the unibus interface,
four (4) ea.
1) Areas that represent UDP Chips.

4-8

SYSTEM OVERVIEW

a. 3 buffered data paths for data and
addresses
b. 1 direct data path for data and
addresses
c. Byte swapping and rotating circuits
to align data
b. The Unibus Data Path Control - Controls UDC
chips and Microcode (UCN) chip.
c. Unibus map for translating Unibus addresses
to CMI addresses.
d. ROM
for
controlling
UBI
functions
independent
of
CPU.
(Note
circles
controlling UDP Chips are fields from ROM.)

4-9

SYSTEM OVERVIEW

SAM

ALP

~~~

ALP

~
~

I
~

>OK:

CCC

PHB

THE DATA PATH
MODULE (DPM,
GATE ARRAY CHIP
LOCATIONS

TK~'11

Figure 4-1

DPM Gate Array Locations

4-10

SYSTEM OVERVIEW

MOR

PRK

THE MEMORY
INTERCONNECT
(MIC) MODULE
GATE ARRAY CHIP
LOCATIONS
CAK

TK-4112

Figure 4-2

MIC Gate Array Locations

4-11

SYSTEM OVERVIEW

.......... +...............

CO_~SO~~

CON

THE UBI MODULE ;
GATE ARRAY CHIP.
LOCATIONS
.

__ ___
...... 1: ................. .

. . ,,
. . ...............
..
~

CON

.. .

TU58

.........................
....
..........................
INT

.
.
.
·----------.........:.......:.......
. ..
.........................

...,...,
•
....................

UDP

UDP,
't

UDP

.............................

_
.

•
....................
.
UDP

...

t ••

•

...

t .......................

UCN

--1-'-·~·\..+··

·. •

.1 '
TIC-'718

Figure 4-3

UBI Gate Array Locations

4-12

SYSTEM OVERVIEW

I
I
I
I
I
I
I
I

CCS/WCS .

~I
m
~I
m

m
ij1

·I

~
m
OI

IOI
101

l~I

1ij1

1rn

I
I
I

101

1011

I
I

IOI

WI
WI

I
I
I

m1
m1

I
I

IOI

I
I
I
I
I

I
I

l~I

I
I
I
I
I
I
I
l

IOI

I
I

I
I
I
I
I
I
I
I

I
I

.1ij1

I
I

I
I
I
I

0C30C3 C3 C30c:::3

c::JO c:3 c:::3

c::3 0CJ c::::3

C3~c::::3 c::s c::::3

c::::3

c::::3~

cr:=3

c::::3

0c::::30c::::3 c:::::3 o=J3

[l:=3

c::::3
§

c:::>

TK~710

Figure 4-4

CCS Module

4-13

SYSTEM OVERVIEW

THE CPU MEMORY
CONTROLLER (CMC)
GATE ARRAY CHIP
LOCATIONS.

B8 8 B
RED
LED

arl
~

GREEN
LED

_I
MDL

·1 _I

___

MDL

I_
MEC_____.·1 I MDL

MEC

·1

• 11 MDL

·1

TIC-4717

Figure 4-5

Memory Controller

4-14

VAX-11/750 LEVEL II

Programming

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Programming

OUTLINE
V.

PROGRAMMING
A.

VAX Instruction Set
1. Operand and Instruction Formats
2. VAX Addressing Modes
3. VAX Integer and Logical Instructions
4. VAX Branching Instructions

Laboratory Exercise 3
Write a routine to convert packed hex data to
.an ASCII string utilizing VAX 11 Programming
Tools

VAX Instruction Set
1. VAX Floating-Point Instructions
2. VAX
Subroutine
and
Procedure
Instructions

Calling

Laboratori Exercise 4
Modify routine written in previous lab to
called as a procedure utilizing a CALLS
CALLG instruction

be
or

VAX Instruction Set
1.
VAX Character String, Packed Decimal and Field
Instructions
2. VAX Privileged Instructions
3. Programming Examples

Laboratory Exercise 5
Write a standalone program for the Comet CPU to
communicate between the local console and a
terminal on the Unibus

Summary

5-1

Programming

OBJECTIVES
Utilizing the VAX-11/780 Programming card, Architecture
handbook and any class notes, write two (2) programs that
perform the following:
a}
b)

Packed hex to ASCII conversion
2 way· communication between
terminal on the Unibus.

CPU

Console

and

Load and execute the previously writ ten programs and
instructor will verify operation.

a
the

SAMPLE TEST ITEM
Using the Cornet system, load and execute the two (2)
programs previously written in class.
The instructor will
verify proper operation by witnessing program execution.

LAB EXERCISE
a)

Utilizing the VAX program development tools, write a
packed hex to ASCII conversion routine in VAX-11
Macrocode.

Again, utilizing the same VAX programming tools,
write a standalone program to communicate between
the console terminal and a Unibus terminal and copy
it on to a TU58 tape cartridge for console loading.

RESOURCES
VAX-11/780 Architecture Handbook
VAX-11/780 Software Handbook
Terminals and Communications Handbook
Program Development L1st1ng

5-2

Programming

DATA TYPES
•

BYTE

•WORD
• LONGWORD
• QUADWORD
4

7654 3210

I: 11 I 11111

BYTE

!WORD

8 7

1:1

LONG
WORD

I
0

1:1

I::1

OOAD
WORD

SB EQUALS SIGN BIT
TK-3240

Figure 5-1

5-3

Programming

DATA TYPES
e FLOATING

• DOUBLE FLOATING
FLOATING

16 15 14

FRACTION.

I:I

7 6

EXPONENT I

FRACTION

DOUBLE FLOATING

7 6

16 15 14·

FRACTION

EXPONENT

FRACTION

FRACTION
48 47

TIC-32'1

Figure 5-2

5-4

Programming

ARRAY::

127

AFTER EXECUTION

EXTZV#48,#8, ARRAY, RO

EXTV#64,#8, ARRAY, R1

I I I I I I I I I
I I I I I I I I I
0

CMPV#48,#, ARRAY, RO
BEOL1$

FFC, #0, #8, ARRAY, R2

PSW

I I I I I I I I
I I I o I o o Io I
0

FIELD INSTRUCTION EXECUTION EXAMPLES
TK-3238

Figure 5-3

5-5

Programming

REPRESENTATIONS OF+ AND -123 CHARACTER STRINGS
TRAILING NUMERIC

.ASCll/123/ZONED FORMAT

33
+2

.ASClll12;YZONED FORMAT

ADDRESS

BINARY REPRESENTATION

SIGN BIT
.ASCll/12C/OVERPUNCH FORMAT

.ASCll/12L/OVERPUNCH FORMAT

I
I

LEADING SEPARATE NUMERIC STRING
FORMATS
.ASCll/+123/

.ASCll/-123/

2D
TK-3237

Figure 5-4

5-6

Programming

3210
.PACKED - 12345
ADDRESS

.PACKED 12345
SIGN

.PACKED 01234567891

I*I I I I I I I I I I I
c

PACKED DECIMAL STRING FORMATS
TK-3239

Figure 5-5

5-7

SINGLE OPERAND
ASSEMBLER

OPERAND SPECIFIER

CLRL RO

OP CODE

lo11lol1lolololol1l1lol1lol1lolol
\

.....

MODE 1

zws

REG,
+1

ADDRESS

TWO OPERAND
SPECIFIER 2;

SPECIFIER 1 ·

OP CODE

MOVL RO, R1
MOOE.

REG

MODE

REG

+2
U1

THREE OPERAND

ADDL3 #1, RO, R1

ADDRESS

SPECIFIER 2

SPECIFIER 3

MODE

REG

MODE

SPECIFIER 1

REG

OP CODEi

SHORT LITERAL
ADDRESS

TWO OPERAND WITH IMMEDIATE MODE

MOVB# X80,(R2)
SPECIFIER 2

MODE

IMMEDIATE DATA

REG
+3

SPECIFIER 1

MODE

OP CODE

REG
+1

ADDRESS

INSTRUCTION FORMATS
TK-3243

ADDL2 RO. R 1

BEFORE

•

AFTER

I I I I I I I I I> 13 I I I I I
I II I I I I I
I I I II I II I
(

8 )

4 ) s

ADDL3 RO, R1. R2

I
\.0

I I I 31 4 I I j I I I I 2l 3 14 j I I I I
1

I o I o I o I o I I j I a I fo I o I o I o ( I I I a I
I I I I I I I I I
I I I I II I I
0

TWO AND THREE OPERAND INSTRUCTION
EXECUTION IN REGISTER MODE
TK-3242

ASSEMBLER SYNTAX
.= /\ XlOO
SELF: BAB SELF

NEXT INSTRUCTION

DISPLACEMENT

0 0 0 0 0 0 0 0

1 1 1 1 1 1 0

102

101

OP CODE

0 0 0 1 0 0 0
100

PROGRAM COUNTER POINTING
MERE WHEN DISPLACEMENT IS EVALUATED

I"!]

I
I-'

......
Ul
c::
l""C

SIGN EXTENDED
DISPLACEMENT
(-2)

1 1

1 I 1 1 1 1 11 1 1 1I 1 1 1 1 I 1 1 1 1 11 1 1 1 I 1 1 1 1 I 1 1 1 0

PLUS

CX>

PROGRAM COUNTER
(102)

++ +++ I +
I + + + + +
+ I
0 0 0

0 0

0 0 1

0 0 0

0 1

0 0

0 0 1

Io 0 0

0 0 0

EQUALS
NEW PROGRAM
COUNTER
(100)

BRANCH OFFSET CALCULATION

TK-3225

.,,
""'0
Ul
11-1
DJ

3
3

......

;:J

Programming

A+3 A+2 A+ 1

INPUT 1 2

OUTPUT

4 A

32
42

31
41

A
A+4
TK-4•58

Figure 5-9

5-11

Programming
START
ROUTINE

GET NIBBLE

NO~ NIBBLE • 0 - 9

YES, NIBBLE•A·f

ADD37

Aoo·30--HEX

HEX

TO NIBBLE

NIBBLE

STORE ASCII

BYTE IN

CHARACTER
BUFFER

EXIT FROM
ROUTINE

FLOil DIAGRAM FOR PACKED HEX
TO ASCII CHARACTER CONVERSION
ROUTINE
TK-3231

Figure 5-10

5-12

l'1:J
......
U1

.......

c T

l"1

F
p
D

CUR

MOD

IPL

v u v

z v c

CD
U1

.......
.......

VAX FAMILY PSL
TK-3224

BRANCH ON
MICROTEST
IRD+ONE

0038
SOFTWARE
INTERRUPT
REQUEST

IE.CONSOLE.INT

IE.UNIBUS.INT

0039
TEMPB+-14
CONSOLEINTR

003A
TEMP 8+- 1PL
REIGRA
UNIBUSINTR

IE.CONSOLE.INT2

t%j
.....

CD
U1

I
~

003D
CACHE
PARITY
ERROR ·

003E
WRITE aus
ERROR
INTERRUPT

l
003F
POWEn FAIL
INTR

NUMBERS IN BOXES ARE HEX MICRO ADDRESSES
FORCED BY THE HARDWARE AND ARE CONSTANT

c
""(

1
003C
CRD
INTERRUPT
REQUEST

IE.UNIBUS.INT2

l.Q
U1

I
0038
INTERVAL
TIMER
INTERRUPT

HARDWARE FLAGS UTILIZED IN
MICRO ROUTINES
FlAGO •O
•1

INDICATES INTEllRUPT BEING SERVICED
INDICATES EXCEPTION BEING SERVICED

FLAG1 •O
•1

HANDLE ON INTERRUPT STACK
HANDLE ON KERNEL STACK

· FLAG2 •0
•1

MORE PARAMETERS TO PUSH ON STACK
NO ADDITIONAL PARAMETERS

FLAG3 •O
•1
STACK
FLAG
•1

PC - 2 ON STACK, FLAG3 • 0 ON INTERRUPTS
PC
ON STACK, FLAG3 • t DURING MICRO DETECTED TRAPS

-o

INDICATES ADDRESS TRANSLATION ON KERNEL STACK VALID
KERNEL STACK NOT VALID

BRANCH ON MICROTEST
TARGETS
TK-3234

Programming

TU58 OR PASSIVE RELEASE FLOW
IE. TU58

IE.UNIBUS.INT2
ISSUE
BUS GRANT
ANO
SAVE IPL

LOAD TRAR
WITH RXCS
ADDRESS

READ VECTOR
WRITTEN
REGISTER

READ
TU58 RXCS

•...
NO

LOAD
ERRCOD

CLEAR
VECTOR
WRITTEN
REGISTER

YES

LOAD TRAR
WITH CCSR
ADDRESS

LOAD VA
w1TH seas
+FO
TU58 INTERRUPT 8R7

READ
CCSR
CLEAR
TXINTR

NO ADDITIONAL
PARAMETERS
GET seas

VA GETS

seas+ F4
ADD SCBB
TO VECTOR
IN MOR PLUS
200 HEX

IE. NO. UNIBUS
BACKUP

BR GONE
PASSIVE
RELEASE

=O
IE.UNIBUS.INTS
JOIN

GL.NOP.I RD1

INTER~UP!_

FLOW NEXT/IE.
INTERRUPT

IRD1

T K-4455

Figure 5-13

5-15

Programming

....-------------.....

IE.CONSOL.INT2

LOADCRAR
WITH RXCS

READ RXCS

YES

VA GETS

. SCBB +FB

LOADCRAR
WITH CCSR
ADDRESS

CLEAR
XMIT
INTR

VA GETS

SCBB +FC
,:;,

______........._____....,.

IE.INTERRUPT

TK-4456

Figure 5-14

5-16

IE.INTERRUPT
READ
MACAO
VECTOR

GO TO KER
STACK NOT VALID

t'ij

......

SAVE CONTENT
OF MACRO
VECTOR IN TEMP 5

lQ
U1

I
~

l'"1

Cl>

-....]

=00 USE KERNEL STACK UNLESS IS= L

= 10 TRAP TO WCS

=11 HALT SYSTEM

•

=01 USE
INTE,RRUPT STACK

--~~~~~~~~-.-~~~~~~~~--~~~~~~~~~~~~~~~~~~-

1E.25
ENTER
CONSOLE
MODE

ENTER

SAVE SP

wcs

AT 2001

TEMP9

SAVE SP
IN
TEMP9

tO
l'"1

lQ
TK-4459

l'"1

!3
!3

......

::s

PSL IS= 0

PSL IS= 1

SETIS
BIT
IN TEMPS

SETIS
BIT IN'
TEMPS
IE.KSTACK

SETIS
IN
TEMPB

IE, ISTACK

SET PREV

SAVE KSP
IN
TEMP10

SET PREV
MODE TO
. KERNEL

TEMP10
GETS
SP

MODE
TO KERNEL

I
.......
.....J

:ti'

=10

=00

=11

IE.SAVE.SP
ESP GETS.
SP
(TEMP9)

SSP GETS
SP
(TEMP9)

IE.75

IE.70
SET PREV
MODE TO
EXEC

KSP GETS
SP
(TEMP9)

USP GETS
SP
(TEMP9)

IE.80
SET PREV
MODE TO
SUPV

SET PREV
MODE TO
KERNEL

'"Cl
l"1

\Q
l"1

6
6
.......

SP GETS
KSP

::s

TK-4460

Programming

VA+-(SP-4)
SET STACK FLAG
PSL .... TMP 8

<15:0>

LOAD STEPR
COUNTER

a
EMP 4+-PSL
INTERRUPTS OFF

WRITETMP4
SIZE LONG
CLEAR STACK
FLAG.

LOADS
LATCH= 16
RTEMP +- ANUM

CLA Rn
BITS <31 : 16>
IN GPR'S

NO
V..~ .... (SP-4)
·seTSTACK
FLAG

VA .... (SP-41
SET STACK
FLAG
IE.PUSH.PC

CLRPC

<31:16>

NO
WRITEM
PC, LONG

WRITE M
PC-2, LONG

CLEAR STACK

Cl.EAR STACK

FLAG

PAGE 2 INTERRUPT/
E~t;::~PTION FLOWS
iK-323!5

Figure 5-16

5-18

Programming

NO 0
----

WRITE M
PC-2 LONG
CLEAR STACK
FLAG

WRITE M
PC LONG
CLEAR STACK
FLAG

RETURN+1
¥

RETURN+ 1 I

EXCEPTIONS WITH EXTRA
PARAMETERS

IE.LOAD.PC
PC+-TEMP5

ANO BITS
<1:a>

PC+-TEMP5
ANO BITS <1 :O>

PC+-TEMP5
AND BITS<1:0>

GETO

TEMP8+-1PL

•IF

IE.BEGIN.MACRO

IR01

PAGE 3 GENERALIZED INTERRUPT/EXCEPTION FLOWS
TK-3230

Figure 5-1 7

5-19

IRD1

IE.REI

WBUS+-MOR

READ VIRTUAL

YES

ADD (SP+41

IE.RE.20

READ VIRTUAL
TEMP+-MDR

WBUS+-MDR

CHECK MORE

DO REI CHECK

MBZBITS

ADD(SP+41

GENERATE
LONG LITERAL
3020FFOO

.LONG LIT

WBUS ... MOR

M(SISR) +MBUS+ZLIT4
AST PEND.
SOFTINTR

TEMP9+-SP
BRANCH PSL
<IS.CUR>

IE.SOFT.IPL

REI CHECK
FAILED

PC-2
CLR FLAG3

RESERVED
OPERAND

FAULT _

RESERVED
OPERAND
FAULT

REI INSTRUCTION GENERALIZED
MICRO FLOWS

Figure 5-18

5-20

Programming

IE.REl.60

000

KSP+-TEMP9

011

001

SSP+-TEMP9

ES? +-TEMP9

USP+-TEMP9

100
ISP+-TEMP9

YES

IE.REl.70
SET TRACE
PENDING
PSL +-MOR

PSL +-MOR

PC +-TEMPS

IE.REl.80[+1] 000

001

TEMPS+- KSP

TEMPS+- ESP

011

TEMP9+-SSP

100
!RD
INTERRUPTED
ROUTINE

SP +:.TEMPS
IR01

'
Figure 5-19

5-21

1'1<-.3232

Programming

SET POSITION
POINTER
SET OUTPUT

START

r-------PASS ADDRESS
OF NIBBLE
STRING
TO PROCEDURE

'
I

GET NIBBLE
FROM LOCAT·
IONTOCONV·
ERT

YES A·F

0-9 NO

--,I

ADD37HEX
TO NIBBLE

AD030HEX
TO NIBBLE

I
PASSNUM·
BER OF LONG·
WORDS TO
CONVERT

'
-,
I

I
I

L-- ... --~--

STORE ASCII
CHARACTER
IN LOCATION
·SPECIFIED

I
I

I
RETURN HERE
FROM PROC·

L-----.-,-~

EDU RE

ADD4
TO

12 (AP)

FLOW DIAGRAM FOR PACKED HEX TO ASCII
CHARACTER CONVERSION PROCEDURE

Figure 5-20

5-22

TK-3229

Programming

SET-UP
STATE DEFINITIONS
ALLOCATE MEMORY

SETUP
A STACK
. JUMP TO BUILD see

BUI LO see AND
TRCS SUBROUTINE.

LOAD DZ LINE
PARAMETER REG
WITH DESIRED
BAUD RATE, FOR
DESIRED LINE.
TURN RXON

TURN RECEIVE
INTERRUPT ENABLE
ANO MASTER SCAN

ON
LOAD CONSOLE
RX VECTOR WITH

LOWER CPU IPL
TO TAKE
INTERRUPTS

ADDRESS OF
SERVICE ROU·
TINE
TURN ON CONSOLE
RX 1E

LOAD UNIBUS .
VECTOR 2xx
WITH ADDRESS
OF SERVICE
ROUTINE
NO, UNIBUS BR
DZ·11 SET-UP

LABORATORY EXERCISE 5

PROGRAM FLOW DIAGRAM
TK-3227

Figure 5-21

5-23

Programming

CONSOLE SERVICE

UNIBUS SERVICE

LINE

READ DZ
RECEIVE

IN DZTCR

BUFFER

TURN ON

REI

GET CHAR

GET
CHAR FROM

FROM
DZBUF

CONSOLE
------.

ECHO
CHAR BACK

ZERO EXTEND <31 :S>
AND SEND CHARACTER
TO CONSOLE

TO
CONSOLE
RESELECT
DZ LINE

SEND .
CHAR TO

SEND
CHARACTER BACK
TO

TERMINAL
REI

REI
TK-3228

Figure 5-22

5-24

Programming

OOOQOQ

:S&KB

03FFFF

1 ARRAY 30ARO

040000
5t2KB

07FFFF

080COO

768KB

CSF=FF

occooo

1024K8

FFFFF

100000
128CIKB

T3FFFF
140000

1$3SK8

17FFFF

180000

18921(8

19FFFF

ICCOOO

21W81(8
MAXIMUM FULLY ?OPULATCO ARRAYS

1FFFFF

FOOOOO
F!OCOQ

F20000

F3l004

!JIEMOAY CONFIGURATION REG.

F:CCOS

MEMORY CCNFIGUAAT!ON R5G. C

F20400

cOOTSi'RAP ROM ?ROGRAM

F2SQCO

!AASSBUS .ACA?TOA 0 INT. REGISTE?.S

F78400

MASSaUS AOAPTOA 0 EXT. ?EGls:'ERS

F2S800

MASSSUS AOAPTOA 0 MAP REGISTERS

F2AOQO

MASSIUS AOAPTOl'I 1 INT. i'!EGISTERS

F2A400

'otASSBUS .A CAPTOR 1 =xT. REGISTERS

F2A800

MASSBUS ADAPTOR 1 MAP REGISTERS

F2CQOO

\IASSSUS ADAPTOR 2 INT. REGISTERS

MASS8US ADAPTOR 2 EXT. REGISTERS

;::zcaoo
F30000

~.4ASSaUSACAPTOR 2 MAP REGIS'l'aRS

,,.

F30C!Q4.C

UNIBUS OATA ?ATH CONTROL Si STATUS

F300t4-IC

'..iNIBUS DIAGNOSTIC REGISTERS

F30800

UNIBUS MAP REGISTERS

;::32000
F32014
Cl28QO

FSOOOO

2NO UNIBUS MEMORY SPACE
128KW

UNIBUS MEMORY
SPACE 12SKW

COMET PHYSICAL MEMORY ORGANIZATION

Figure 5-23

5-25

ENO OF EXISTENT MEMORY

ORO{

MSB
15

CONTROL

t-R~_t-R_Q

& STATUS

TROY

TIE

-~-- ~"°<S~

~ $
.,Y

SAE

(CSRI

BYTES
HIGH LOW
08
07

JlQ_rR_Q ___

-[%'.

LSB
00

~-- '!Q_ -!!_w__._~W--~s--~6'r-ffj;f-~"'-!

TLINE TUNE TUNE RDONE
C

;-..,.,

MAINT

CLR

~ 4J ~ ~

.;:,

~
.;:,

.;:,Cj

'-~~~~-1-~~..i-----1-~~--1-------1'-~--+-~.......~~-+-~--1---~~~~

,_ i:o__ ,_n~ _

llECEIVER
BUFFER
IRBUFI

DATA
VALID OVRN

lJ1

c::

t-1

°'

lJ1

LINE
PARAMETER
ILPRI

"11
.......

'!_~ _
PAR
ERR

S' O

~ ~
..;:,

DR2

'!_0_ _
FRAM
ERR

P.i

_!'~ _ _!'~ _' '!!'_ _ '!_0_ ~ _!!.'!__ _!!'!_ _ _!!'!_ ___ '!_0_ _

RX
LINE
C

RO
I-----

RBUF
02

RBUF
01

RBUF
DO

RX
LINE
B

~'··11~.~ » "'

~ ~\~
'

RBUF
07

RBUF
D6

TRANSMIT•
CONTROL
(TCR)

.t:=.

MODEM"
STATUS
(MSR)

DTR
7

DTR
6

DTR
5

DTH
4

-~ ~

OTA
3

I~~

DTR
1

OTA
0

TRANSMIT
DATA
(TDRI

DTR
2

RO
RO
RO
RO
RO
RO
RO
no
r- - - - - - + - - - -r- - - - -r- - - - - - + - - + - -

DR6
I- -

WO
-t- -

WO
-

I- -

WO
-

t- -

WO
-

BAK

ORK

BflK

BAK

I- -

BAK
3

RBUF
D4

RBUF
DJ

~~- ~~- ~O :-.~@ 1-~-+!!~- !~-

_R_!'_+"!'!-+f'!!V __ t-~w_--t-~w--..,~-+'ll'Y-- R\!.._ J1vt..-..'llL
OR4

RBUF
D5

~ ~ ~R~~ ~:: :~:8 ~~: ~ ~ -~~

~ ~

RX
LINE
A

WO
I- -

WO
-

ORK
2

I- -

LINE
ENAB
7

BAK
1

I- -

RO
-i

WO
- -

ORK
0

LINE

R.Y-+'LW_ _ 1-'3Y'---~-1-nw
LINE
ENAB
6

LINE
ENAB
4

·t- - -

'"" - - -

RI&

Rl5

Rl4

t- -

Rl7

WO
-

LINE
ENAB
6

~~ ~~

LINE
ENAB
3

LINE
ENAB
2

RO
I- -

RO
-

.,. -

Rl3

Rl2

+ - - - - - ., - - - ..... - - - -1- - -

TBlJF
7

TBUF
6

TBUF
5

TBUF
4

TBUF
3

LINE
ENAB ~~~~~~~

1~·

RO
-

.... -

RI 1

WO
-

TBUF
2

TBUF
1

t- -

RI 0

WO
t- -

TBUF
0

*The hiyh byte of the TCR (Data Terminal Ready) and the MSR are not used with the 20 mA options.
TK-446A

Programming

Figure 5-25

5-27

Programming

CPU AND MASSBUS
VECTOR PAGE

SRBB+200i--~~~~~~~~~~~~~~~~~~~~~~~~~~~~--t?AGE2

INTEGRAL UNIBUS VECTOR
PAGE

2ND UNIBUS VECTOR
PAGE

COMET SYSTEM CONTROL BLOCK
"':"K-1740

Figure 5-26

5-28

Programming

RELATIVE
ADDRESS TRCB:: .BLKL 256

SCB:: .BLKL 256
00000400.

400

00000000

00000404

404

00000000

00000408

408

00000000

0000040C1

40C

00000000

000007f 8

3f8

7F8

00000000

000007FC

3FC

7FC

00000000

•t

•
I

TK~457

Figure 5-27

5-29

Programming

HEX NAME

00
01

KSP

02
03

SSP
USP
. ISP

ESP

KERNEL STACK POINTER
EXECUTIVE STACK POINTER
SUPERVISOR STACK POINTER
USER STACK POINTER
INTERRUPT STACK POINTER
31

00
VIRTUAL ADDRESS OF TOP OF STACK

POBR

PO BASE REGISTER .
RESERVED OPERAND FAULT IF VLA < 2**31

P1BR

Pl BASE REGISTER
RESERVED OPERAND FAULT IF VLA < 2**31 - 2**21
31

02 01 00
VIRTUAL LONGWORD ADDRESS

POLR

PO LENGTH REGISTER
LENGTH OF POPT IN LONGWORDS

P1LR

Pf LENGTH REGISTER
2**21 - LENGTH OF P1PT IN LONGWORDS

SLP

SYSTEM LENGTH REGISTER
LENGTH OF SPT IN LONGWORDS
RESERVED OPERAND FAULT IF MBZ =?O
31

22 21

MBZ

LENGTH IN LONGWORDS
TK-1750

Figure 5-28

5-30

Programming

HEX NAME
10

PCBB

PROCESS CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ :¢: 0.
3130 29
MBZ

SCBB

02 01 ()()

PHYSICAL LONGWORD ADDRESS OF PCB

MBZ

SYSTEM CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ :¢: 0.
313029

IMszl

IPLR

PHYSICAL PAGE ADDRESS OF

020100

scs

INTE.RRUPT PRIORITY LEVEL REGISTER
31

05 04

MBZ

ASTR

AST LEVEL REGISTER
RESERVED OPERAND FAULT IF NOT VALID I.E., MBZ ¢0.
31

I
OC

SBA

03 02

MBZ

SYSTEM SASE REGISTER
RESERVED OPERAND FAULT IF MBZ:;:: 0.
31 30 29

f Mszj

02 01 00

PHYSICAL LONGWORD ADDRESS

TK-1753

Figure 5-29

5-31

Programming

NEXT INTERVAL COUNT REGISTER (WRITE ONLY)
31

PR#

NAME

NICR

ICR

ICCS

0
2'S COMPLEMENT OF INTERVAL DESIRED X 1 µSEC

INTERVAL COUNT REGISTER (READ ONLY)
31

0
ACTUAL INTERVAL COUNT PERIOD

INTERVAL CLOCK CONTROL AND STATUS (COMET HARDWARE)
0
0

ERROR
TRANSFER OVER FLO PENDING
INT REQUEST
INT E N A B L E - - - - - - - - SINGLE C L O C K - - - - - - - -

•

TRANSFER - - - - - - - - - - - - - •
SERVICE R E Q U E S T - - - - - - - - TRANSFER REQUEST - - - - - - - - - OVERFLOW P E N D I N G - - - - - - - - - - - - '
RUN--------------------'

INTERVAL CLOCK CONTROL STATUS (VAX SOFTWARE)
16 15 14
31
E

76543210
0

ICCS

INTEN
SINGLE CLOCK
TRANSFER---'
RUN------------

INTERVAL TIMER PROCESSOR REGISTERS
TK-1724

Figure 5-30

5-32

Programming

TOOR

TIME OF DAY REGISTER
31

00
TIME OF DAY (10 MILLISECOND INCREMENTS)

SIAR

SOFTWARE INTERRUPT REQUEST REGISTER
RESERVED OPERAND FAULT IF READ
31

MBZ

0403

SIRL

WRITE ONLY

SISR

SOFTWARE INTERRUPT SUMMARY REGISTER
31
MBZ

1615
0100
SOFTWARE INTERRUPT REQUEST
F EDCBA98765 4321
MBZ
TK-1752-

Figure 5-31

5-33

CONSOLE STORAGE RECEIVER STATUS
31

7 6

1:#

1°_l•e~l______

0 ___________
l________,____

NAME
CSRS

CONSOLE STORAGE RECEIVER DATA

4 3

RECEIVE
·DATA

CSRD

'°

RECEIVE FROM TU-58
tx]

.......
lO
U1

w
~

CD
"""'
U1

w
N

CONSOLE STORAGE TRANSMIT STATUS

7 6

1+1

llE

CSTS

CONSOLE STORAGE TRANSMIT DATA
31

7 6

5 4

o__________________......l.______~-~-~-~-SM_l_T_____
.llF

_l_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

CSTD

TRANSMIT TO TU-58
·1 K·173:1

Programming
MACHINE CHECK ERROR SUMMARY REGISTER (REPORTS TYPE OF MACHINE CHECK)
31

[

2 1 0

11TI1

1. WRITING A "ONE" TO BIT 3, CLEARS BUS ERROR REGISTER
2. WRITING A "ONE" TO BIT 2, CLEARS TB GROUP PARITY REGISTER

MCESR

1=TB PARITY ERROR

1 = uNALIGNED UNIBUS REF.
1=XB REF.
O=OPERAND REF.

BUS ERROR AND MACHINE CHECK ERROR AND SAVED MODE REGISTER
TK-1742

TRANSLATION BUFFER GROUP DISABLE REGISTER
(CONTROLES 2 WAY ASSOCIATIVE MEMORY OPERATION,
NORMAL LOADING IS RANDOM PLACEMENT OF DATA
IN PTE CACHE)
MEMSCHAR#

~31:.....----------------------------------------------..............-..,......_.PR#

NAME
TBGDR

O=RANDOM
1 =FORCE

0 = REPLACE GO
1 = REPLACE Gl

O=NORMAL---1 = FORCE MISS G1
O=NORMAL~------'

1 = FORCE MISS GO

TRANSLATION BUFFER CONTROL ANO STATUS REGISTERS
TK-1732

CACHE GROUP DISABLE REGISTER (CONTROLS REPLACEMENT OF DATA
INTO CACHE) 1 X 1K LONGWORD
MEMSCAR #
31
3 2 1 o.
5

1° I I I I

0 0

O= NORMAL
1 = FORCE MISS

PR#

NAME

CGDR

CAER

CACHE ERROR REGISTER
31

3 2 1

lll l J

TAG PARITY ERROR
DATA PARITY ERROR

2ND ERROR
CACHE HIT

UNIBUS. CACHE CONTROL AND STATUS REGISTERS
TK-1734

Figure 5-33

5-35

Programming

HEX NAME
20

RXCS

CONSOLE RECEIVE CONTROL/STATUS
08070605

MBZ

DONE

RXDB

CONSOLE RECEIVE DATA BUFFER
Jl

0807

00
BYTE 0

READ ONLY
22

TXCS

CONSOLE TRANSMIT CONTROL/STATUS
00

08 070605

IIlie!

MBZ

READY
23

TXDB

CONSOLE TRANSMIT DATA BUFFER
31

08 07

00
BYTE 0

WRITE ONLY
TK-1749

Figure 5-34

5-36

Programming
HEX NAME ID:;:
38

MME

MEMORY MANAGEMENT ENABLE
WRITE 1 ALSO CAUSES MICROCODE TO INVALIDATE TB.

01 00

MME

TBIA

TRANSLATION BUFFER INVALIDATE ALL
RESERVED OPERAND FAULT IF READ
31

I
3A

TBIS

MBZ
WRITE ONLY

TRANSLATION BUFFER INVALIDATE SINGLE
RESERVED OPERAND FAULT IF READ
31

VIRTUAL ADDRESS
WRITE ONLY

PMR

PERFORMANCE MONITOR REGISTER
RESERVED OPERAND FAULT IF >1
31

01 00
MBZ

PME

SID

SYSTEM IDENTIFICATJON

(READ ONLY)

RESERVED OPERAND FAULT IF WRITE

24 23
SYSTEM TYPE

8 7

16 15

MICROCODE
REVISION
LEVEL

HARDWARE
REVISION
LEVEL

FROM MICRO
WORD LITERAL
FIELD

FROM SWITCHES
LOCATED ON UBI
MODULE

TK-2099

Figure 5-35

5-37

MEMORY CONTROL &
STATUS REGISTER

31 30 29

PAG~ ADDRESS OF ERROR

0 f 20000

9 8 7

24 23

0 0 ERRORSYNDROME

CORRECTABLE ERROR FLAG (1 BIT ERROR)
2ND UNCORRECTABLE ERROR
---UNCORRECTABLE ERROR FLAG (MORE THAT 1 BIT ERROR)

31
1 f 20004

0 0 0

0 0 CHECK SYNDROME

PAGE MODE ADDRESS

'---DIAGNOSTIC CHECK MODE (FOR VERIFY SYNDROME BITS FUNCTION)

l o[

9 8

DISABLE ERROR CORRECTION

t'1:J
......
lJ1

29 28 27 26 25 24 23

PAGE MODE
INHIBIT REPORTING CORRECTED ERRORS INHIBITS CAD INTERRUPT

l"1

lJ1

°'
2 F20008

24 23

17 16 15
STARTING
ADDRESS

00000000
\_

0
MEMORY PRESENT

......_.......

BACKPLANE JUMPER
SELECTABLE

BITS <15:0> INDICATE MEMORY PRESENT
IN 128KB INCREMENTS (2 BITS PER
MODULE)

INIT
--~~~~---~--~~~~--,
r
COLO/WARM RESTART FLAG
= 1 ON POWER UP OR BATTERY DEAD
= 0 AFTER FIRST 4 BYTE WRITE
·rK-1725

1 0

31 30 29 28
BOP #1 F30004
#2 F30008
#3 F3000C

BIT <o> PURGE. nus BIT ALWAYS READS A ZERO. WRITING A ZERO TO IT
HAS NO AFFECT. WRITING A ONE TO IT PRODUCES A RESULT BASED ON THE
CONTENTS OF THE BUFFER:
UNIBUS DATA:
CMI DATA:
EMPTY:

THE DATA IS WRITTEN TO THE CMI AND THE FLAGS
ARE SET TO MARK THE BUFFER EMPTY.
THE FLAGS ARE SET TO MARK THE BUFFER EMPTY. ·
NO ACTION OCCURS.

--~~~~~~--~~~~-----UCE

'"z:J
.....
U1

w
l.O

'°c

'CD""

--~~--~~~~~~~~--_........__---~--~--~--~~----~--~(BIT <29> UNCORRECTABLE ERROR (UCE). THIS BIT IS SET WHEN
')
UNCORRECTABLE ERROR STATUS IS RECEIVED FROM CMI MEMORY. PB IS
ASSERTED WITH THE DATA THAT IS PASSED BACK TO THE UNIBUS DEVICE ON lHE
FIRST READ FROM THAT LOCATION. IT IS NOT ASSERTED ON SUBSEQUENT READS
FROM nus BOP. Tl-IE BIT IS WRITE ONE TO CLEAR.

w
.....J

BIT <JO> NON EXISTENT MEMORY (NXM). THIS BIT IS SET WHEN NXM,STATUS
IS RECEIVED FROM THE CMI MEMORY. SSYN IS WITHHELD FROM THE UNIBUS
DEVICE. ALL FUTURE UNIBUS TRANSACTIONS THROUGH THIS BOP ARE IGNORED
(NO SSYN ISSUED) UNTIL THIS BIT IS CLEARED. THE BIT IS WRITE ONE TO
CLEAR.

"'t1

BIT <31> ERROR. THIS BIT ON READ IS THE "OR" OF BITS 30 AND 29.
WAITING TO THIS BIT HAS NO EFFECT.

'0""

'°'""

a
a
.....

BOP CONTROL AND STATUS REG.
TK-1721

::J

'°

Programming

F30800TO {
F30FFC

- PAGE FRAME NUMBER CONCATENATED WITH BITS <8:2>
OF THE UNIBUS ADDRESS TO FORM
THE 22 BIT CMI LONGWORD ADDRESS.
--------------DATAPATHNUMBERUSED TO SELECT 1OF4 DATA PATHS.
0 0 DIRECT DATA PATH
0 1 BUFFERED DATA PATH 1
1 0 BUFFERED DATA PATH 2
1 1 BUFFERED DATA PATH 3
- BYTE OFFSET - - - - - - - - - - - - - - - - - U S E D WHEN ADDRESSING ODO BYTE
BOUNDARIES.
- - - - - - - - - - - - - - - - - - - - - - - - - - V A L I D BITIF NOT SET, TREAT CYCLE AS A NOP.

UNIBUS TO CMI MAP DATA FIELDS ADDRESS
TK-1739

5-40

00
DSR #1 f 30014
OSR #2 F30018
DSR#3F3001C ...,..........,......,..~-------------------------------------------------------BYTE 0 VALID }
BYTE 1 VALID . READ ONLY DATA PATH STATUS
----BYTE 2 VALID
- - - - - B Y T E 3 VALID
NOTE 1:

THERE ARE FIVE FLAGS THAT KEEP TRACK OF THE DATA IN THE DATA
BUFFER, NAMED CD AND BF3 THROUGH BFO. IF CD= 1, THEN THE BUFFER
HAS FOUR BYTES OF DATA FROM THE CMI AND BF3 THROUGH BFO ARE
ALWAYS 0. IF CD= 0, THEN BF3 THROUGH BFO INDICATE WHICH BYTES
IN THE DATA BUFFER HAVE VALID UNIBUS DATA. IF THEY ARE ALL 0,
THEN THE BUFFER IS CONSIDERED EMPTY.

NOTE 2:

THIS IS A READ ONLY REGISTER THAT ALLOWS ONE TO CHECK THE FLAG
BITS ASSOCIATED WITH EACH BOP. IT IS INTENDED ONLY FOR POSSIBLE
DIAGNOSTIC USE AND NO REFERENCE TO IT IS REQUIRED FOR NORMAL.
USE OF THE BOP'S.

CUI DIAGNOSTIC STATUS REGISTER
TK-1726

Programming

20 19 18 17 16

O= CMI ENABLED

l
l
I
l
1
l
J

1PR#17

11 10 09 08

04 0302 01 00

1= CMI DISABLED
READ=l, MODIFY=O
VIRTUAL=O, PHYSICAL=-1
CPU MODE,
K,E,S,U

{

READ LOCK TIMEOUT
TB G1 TAG ERROR
/

TB GO TAG ERROR
TB G1 DATA ERROR
TBGO DATA ERROR

TBHIT
MEMORY ERROR
READ DATA SUBSTITUTE
LOST ERROR
CORA ECT ED REA D DATA

CMI ERROR PROCESSOR REGISTER
TK-326~

11PR#37

----------------------~,
ISSUE UNIBUS I N I T - - - - ·

10 RESET PROCESSOR REGISTER
TK-3267

5-42

Programming

HEX NAME

MME

ID~

MEMORY MANAGEMENT ENABLE
WRITE 1 ALSO CAUSES MICROCODE TO INVALIDATE TB.

01 00

MME

TSIA

TRANSLATION BUFFER INVALlOATE ALL
RESERVED OPERAND F.~ULT IF READ
Q()

I
3A

TBIS

MBZ
WRITE ONLY

TRANSLATION BUFFER INVALIDATE SINGLE
RESERVED OPERAND FAULT IF READ

VIRTUAL ADDRESS
WRITE ONLY

?MR

PERFORMANCE MONITOR REGISTER
RESERVED OPERAND FAULT :F >1

01 00

MBZ

'
?ME
3E

SIO

SYSTE!!l_!DENTIFl_<;ATION

(_READ ONLY)

RESERVED OPERAND FAULT :F WRITE

1615

24 23
SYSTEM TYPE

00
01
10

UNDEFINED

NEBULA

11/780
11/750

0
MICROCODE
REVIS:ON
LEVEL

HA.RDWARE

FROM MICRO
WORD LITERAL
FIELD

FROM SWITCHES
LOCATED ON UBI
MODULE

FROM MICRO
WORD LITERAL
FIELD

REVISIO~

LEVEL

BACKPLANE JUMPERS

71<-2099

Figure 5-41

5-43

VAX-11/750 LEVEL II

Microcode

Student Guide

Course produced by Educational Services Department
of

Digital Equipment Corporation

Microcode

OBJECTIVES
Utilizing the Comet microcode listing, correctly trace a
microroutine for a specific machine function, listing only
the microaddresses.
Provided with a Comet microcode macro expansion and a Comet
microcode listing, write each of the field values for that
microinstruction.
Provided with a schematic diagram, trace the origin and
destination of a specific signal within the microsequencer
logic.
Given a series of true/false questions, correctly indicate
as
true or
false
statements
regarding
the comet
microsequencer operation.
Provided with a laboratory exercise procedure, the student
will
a)
b)
c)
d)

load Microdiagnostics
operate the remote diagnosis module
trace microroutines
set up and trace selected signals

SAMPLE TEST ITEM
Referring to the CUI module schematic, drawing number 1 of
14, locate the signal called "RCS 01 CS AD 13 L". Trace the
origin of this signal and all of the destinations in the
space below.

LAB EXERCISE
a)
b)
c)
d)

load microdiagnostics
operate the RDM Module
trace microroutines
set up and trace selected signals

6-1

Microcode

RESOURCES
1.

COMET CPU Microcode listing

DPM module schematic

LSI Chip Schematic
SAC
MSQ
PHB

!RB
4.

Wall charts

COMDEC, Microword decoding program

6-2

Microcode

OUTLINE
I.·

II.

INTRODUCTION TO MICROCODE
A.

Why Microcode?
1. Concepts
2. Advantages

Comet CPU Microinstruction
1. 80 bits
2. Vertical functionality
3. Microcode/hardware relationship
4. Fields and functionality
5. How is microcode created?

Summary

MICROCODE LISTINGS
A.
B.

Microprogrammers Code
Microcode Listing/Macrocode Listing Similarities
File Structure
Reading the Listing
1. Assembler directives
2. Addressing constraints
3. Machine definitions
4. Macro expansions
5. Next address field
6. CREF
Summary

III. MICROSEQUENCER AND CONTROL STORE SUBSYSTEM
A.
B.
C.

Purpose
Cycle Time
LSI Chips
1. SAC
2. MSQ
3. PHB
4.
IRD

E.
F.
G.
H.

CCS Interface
Block Diagram Analysis
CCS Module Block Diagram Analysis
Schematic Analysis
1. Major addressing modes
2.
LSI chip functionality
3.
Timing

6-3

Microcode

IV.

CLASSROOM EXERCISE
LOCATE AND TRACE !NIT MICROROUTINE

CPU CONSOLE MICROCODE
A.
B.

D.
E.
VI.

Console Emulator
Console Interface
Microroutines - Character by Character Parse
Console Functions
Console Functions Flow Diagram Analysis

LABORATORY EXERCISE 6 - TBS

VII. LESSON SUMMARY

6-4

Microcode

INTRODUCTION TO MICROCODE
A.

Why Microcode?
1.

Basic computer designs
a.

direct hardware decode of macro instruction
requires elaborate timing and hardware
design

microprogrammed machine architecture allows
general purpose design to be customized
with ROM microcode.

Microcoding has created a demand for an
individual that understands hardware and
software to write microroutines

Microcode can repair
changing hardware.

Microcode updates require changing only control
store ROMS.

design

problems

without

The advantages or microprogramming are clearly
apparent to other hardware designs

COMET CPU Microinstruction
1.
2.
3.

80 bi ts wide
Vertical functionality
Microcode/hardware relationship
a.
b.
c.
d.

DPM module UBI module MIC module WCS module -

green
blue
yellow
red

6-5

W-BUS

UBI
TU58
INTERFACE

OPM
ADDRESS
l.OGIC

DATA
PATH

DATA
ROUTING
AND
ALIGNMENT

CONSOLE
IN"fERFACE

TRANSL
BUFFER

TRAPS

MEMORY
CONTROL

ARRAY

CACHE

&
INTERRUPTS
M-BUS

UNIOUS
INTERFACE

CMI

0\
ADDRESS

......

FLOATING
POINT
ACCEL

REMOTE
DIAGNOSTIC
MODULE

WRITABLE
CONTROL
STORE

saus
2 T.
3

r:----.
I

RMOJ

_..J
3:

.....

0
COMET SIMPLIFIED SYSTEM BLOCK DIA~RAM

I"'(

0
0
0.
C1)

Microcode

Figure 6-2

6-7

Microcode

Pay<? 30

IN
~~.NOB
.RTOL
;975
;976
;977
;978

;9i9

:969
;970
;971
•972

LINE NUMBER

.TOC
.roe

"DEFIN.r:.rc·
"REVISION 53.3"
P. !L GUI L6AUL T

I.._

DO NOT UST BINARY OUTPUT
NUMBERS ARE FROM RIGHT TO LEFT FOR BINARY
RADIX ISHEX

i..._

.HEXAOECI!.fAL
.SOURCE/33
.SET/NATIVE=!
.NOCREF
i--,
i..._

....

;SET UP FOR CREF ONLY WHEN FULL ASSEMBLY

VAX NATIVE INSTRUCTION MICROCODE
00 NOT CROSS REFERENCE FOLLOWING CODE

;960
;9d1
:982
;983
;984
;985
;986
;987

INSERT TEXT IN TABLE OF CONTENTS

53
52

;~69

;989
;990
;991

;992

51
50
49

;993

;9!:14
;995
;996
;997
;998

:999
: 1000

; 1001
: 1002

: 1003
; 1004

; !COS
; 1006
; 1007

: 1008
; 1009
:1010
: 1011
:1012

;1013
;1014
;1015
;1016
;1017
; 1018

;1019
; 1020
:1021
: 1022
; 1023

CORRECT 't.l!DTH OF CCODEf.Co:npatibilityl ROM
ADD NE\'f ~-:OR_O COtlFLlCT WITH MSi7C PER EIHIOER OS-MAR-79
ADD NEW ~SRC;vA CONFLICT WITH BUS PE~ BINOE~ 15-FE0•79
CHANGE 11i01 R::M OEF'INIT IOU PER SMITH O::?-FE9•79
ADD MlCRO ORDERS FOR OPSPEC FIELDS IN IRO ROMS
CHA~GE t~OX P.Oi.t DEFINITION PER SMI iH 02-FE6-79
DELETE '6UT/M6US19T018' ?ER LI e-FEB-79
C~ANGE CUQDE ROM PER SMITH 02-FEB-79
UPO~TE VD23 & V02S .1NO DISABLE MSRC/TB PER BINDER ~5-JAN-79
ADO VALIDITY CHECKS FOR IRD RO~'S
CHANGE 'USRC/~TE~Ptl' TO 'MSRC/ERRCOD' TO REFLECT ITS PROPER USE
CHANGE VALIDITY CHECKS TO ALLOW 'CLRTB.VA_WB' WITH 'PRB.RO.PTE' WHEN NOT 'BUT/UVCTR'
CHANGE NOTATION FOR MULTIPLE VALIDlTY CHECKS
DELETE 'WCTl~L/VA VAS·;~B' PER BINDER 15-l!OV-78
DELETE ·~xTRL;Roi· & ·~cTRL/ROM WB' PER KRAUS 16-NOV-78
ADO '~CTRL1FPA.ENA8LE ~BS' PER ~PAUS 12-CCT-78
CORRECT DESCRIPTION OF BRATST IN CC TABLE
ADO INFORfAATION AEOUT cceci. SRKSTA. AND SPASTA BUTS
AOO VALIDITY CHEC~S TO CEFIN ANO DELETE VALID.MIC
REVISION H[STOR'f FROM VAL!O :
01
GET RID OF OU'll!'.W CHECV.S AUD RE~:avE COMENT STATUS OF CASE CHECKS
GET RIO OF V003 BECAUSE IT IS IDENTICAL TO V001
00
INITIAL C!ELEASE
ADD 'WCT::<L,flDA_O' AS CJNFLICT lllITH •11.;sRC,"WDR' PER 5!NDER 21-oec-;s
.l.00 NEW CONFLICT FOR SOUR::E PC OR PCB.!.CK ANO RE:.:> OR WRITE
.1DD NOfE TO BUT'S ON IR THl'.T ARE DtFFEt;E:'IT rn cor,,?ATIBILITV MODE
CHAf.fGE 'BUS vs r.ISRC' VALID I TV PER BINOSR 29-DEC-78
CORRECT C')f.lrAENTS FOR 'POr,·1n.RM.P'. 'RGT,'RL.RM.PS'. 'ROT/ASL.R.P'. !t 'ROT/ASL.M.P'
CQR;ECT 'CCPSL;MDR_DSR.CCBR_BRATST' & '~CTRLi~DR_l~' MIC~O ORDER ASSIGNMENTS PER SMITH 12-JAN-79
AOO VAL IOI i'f CHECKS FOR MUL TLPL'f ~ND DIVIDE SPECIAL FUNCTIONS
CHANGE ·~cTRL/STEPC' TO ·~cTRL/CM.TP.FPD.FS.STEPC'
CHANGE '~CTRL/FLAGS' TO 'WCTRL/CM.TP.FPD.FLAGS'
RENAME IRD RO~" FIE LOS TO BE rt.ORE CONSISTANT Ill TH IRD ROM MACROS
INCOPORATE CHANGES PER LI 14-DEC-78
, .)
CHANGE ·wx_s.Q_D' TO ·wx_s.Q_O'
2.1
CHANGE •wx_o_s.o_o· ro •wa_o_s.o_o•
3.)
DELETE 'MUXDZ' FIELO
4.)
DELETE '004' f'i.HD
S.l
ADD NEW SPECIAL FUNCTIONS
CHA~GE ALL V003 TO V001
CORRECT VALIDITY CHECK ON 'CCPSL/MDR_OSR.CCSR_BRATST"
CORqECT CO~PATA9ILIT'f MOOE IRO RO~ OEFINITlON

MICR02 ASSEMBLER DIRECTIVES 1

Figure 6-3

6-8

Microcode

: CMT018.MCR (130,2112] Micro-2.1 1A(3J)
14:40:3 9-Mar-1979
: OEFIN .MIC [130,2112]
Machine Definition
: IR01 ROM
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
19&1
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997

.roe• Machine Definition
: IRD1 ROM"
SWITCH FROM OEFAULT ROM (UI ANO DEFINE IRO ROM AS 32 BITS WIDE.
1: !ig~~/32

+-+-+-+-------------+-+-------------+-+-------------+-+-------------+
:v:v:1:
:1:
:F;
:r:
:1:FIF:
:o:o:P:
:1: : :

IR01.FPA

:R:P:o:

:o:
;P:
: :
; :

iRD1

:Fl

:o:
~P:

: :

FPO.FPA

IOl
IP:

: :
: :

FPO

+-+-+-+-------------+-+-------------+-+-------------+-+-------------+
:J:3l3!3 2 2 2 2 2 2:2:2 2 2 1 1 1 1:1:1 1 1 1 1 0 o:o:o 0 0 0 0 0 o:
:a:2:1:0 9

a 1 6 s 4lll2 1 o 9 a 1 6l5l4 3 2 1 o 9 a:1:s 5 4 3 2 1 o:

+-+-+-+-------------+-+-------------+-+-------------+-+-------------+
FPO
/:<6:0>
FPD.FPA /=<14:8>
IRD1
/=<22:16>
IRDt.FPA/=<30:24>

FOP /•<07:07>
NQP:O

L00=1
FFOP/s<15:15>
NQP:O
LOD=1
IOP /•<23:23>
NQPsO
LQ0s1
IFOP/,.<31:31>
NOPsO
L00:1
VFPO /s<J2:32>,
V1R01/=<JJ:33>,

• VALIDITY=<V060>
• VALIOITY•<V061>

MICR02 ASSEMBLER DIRECTIVES 2

Figure 6-4

6-9

Microcode

Page 54

; CMT018.MCR [130,2112] Micro-2.1 1A(33)
14:40:3 9-Mar-1979
: OEFIN .MIC [130,2112]
Machine Definition
: IROX ROM
1998
1999
2000
2001
2002
2003
2004
2005
2005
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031

2032

::<'.033
2034
2035

2036

.roe •

Machine Definition

+---+--------------~----+---------------------+---+---------------------+---------------------+
: 0
: 0

:
:

l P :

: 0 :
: F !

:
:

CNTO.REG

l 0 :

CNTO.MEM

CNTO.FPA.REG

: p :

CNTO.FPA.MEM
'

+---+---------------------+---------------------+---+---------------------+---------------------+
:4 4l4 4 4 4 4 4 3 3 3 3 313 3 3 3 3 2 2 2 2 2 2:2 2:2 2 1 1 1 1 1 1 , 1 1:1 0 0 0 0 0 0 0 0 0 o:
:1 s:s 4 3

2 1 o gs 1 6 s:4 J 2 1 o 9 a 1 s s 4;3 2:1 o 9 a 1 & s 4 3 2 1:o 9 a 1 s 5 4 J 2 1 o:

+---+---------------------+---------------------+---+---------------------+---------------------+
+-+-+---+---------------------.---------------------+---+---------------------+---------------------+
:v:v: 1
1 :
:c:c: 0 ,

:N:N: P :

lT: T:
;1

:o:

F :

CNTt.REG

CNT1.MEM

0 :

CNT1.FPA.REG

CNT1 .FPA.MEM

P l
: e

+-+-+---+---------------------+-----------------~-+---+---------------------+---------------------+
:9l9l9 919 g g 9 e a 0 e a s e:e a a 1 1 1 1 1 1 1 1:1 1:s & & & s s s 6 & 6 s:s s s s s s s s s 4 41
:1:s:s 413 2 1 o 9 8 1 s s 4 312 1 o 9 a 7 6 s 4 3 2:1 o:g s 7 s s 4 3 2 1 o 9:a 1 6 s 4 3 2 1 o 9 a:

+-+-+-~-+---------------------+---------------------+---+-----------~-------+---------------------+
CNTO.FPA.MEM/•<10:0>
CNTO.FPA.REG/=<21:11>,
OFOP/s<23:22>
NOPzO
LQ0:3
CNTO.MEM/=<34:24>
CNTO.AEG/2<45:35>,
OOP /:<47:46>
NOP•O
L00•3

2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
20'17

CNTt.FPA.MEM/•<58:48>
CNT1.FPA.REG/•<69:59>,
1FOP/•<71:70>
NQP•O
L00=3

2049
2050

VCNT0/=<96:96>,
VCNT1/•<97:97>,

2048

: IRDX ROM"

~r:cCoQEl£10~CgOJ;!D;_E~,.~;--------------------· SWITCH FROM DEFAULT ROM IUI TO OSR ROM AND DEFINE BITS AS 96 BIT WORD.

lffiTH/961

CNTt.MEM/:<82:72>
CNTt.REG/:<93:83>,
10P /•<95:94>
NOP=O
LQ0s3

.VALIDITYa<V062>

.VALIDITYa<V063>

.VALIDITY•<V064>

.VALIDITYs<V065>

.VALICITY:<V066>
.VAL1DITY•<V067>

MICR02 ASSEMBLER DIRECTIVES 3

Figure 6-5

6-10

CMT01B.MCR {130,2112) Mlcro-2.1 1A(33)
14:40:3 9-M~r-1979
lNIT
.MIC [130,2112)
Initialize Mlcroc."lde for the Con$ole and Power up

U 0000, 7100,70F0,7Fff,0450,0B3E

U 0010, OOB0,56E4,0B08,4850,000t
l'1:j
I-'•

\.Q

°'I

......
......

c
...,

U 0825, 4800,5BE4,0B00,4A50,0001

°'I
°'

U 0839, 3500,70F0,7FFF,B450,083E

U OB3E, 0000,5BF4,0304,0050,0B20

3595
3596
3597
3599
3599
3600
3601
3€02
3603
3604
3605
3606
3607
3600
3609
3610
3611
3612
3613
3614
3615
3616
3517
3618
3619
3620
3521
3622
3623
3624
3625
3626
3527
3629
3629

U 0020, 5AOO,CJ'l0,0340,2450,4BtB

3630

.roe •
o:

Initial iza MicrocodQ for the Console and Power uµ"

IN .. INIT:

~~~~;;:i;~;;~~~~:---------------:LONLIT GETS 41FOOOO
CLEAR FLAG2,
NEXT/IN.PSL.LONLIT

1. REGION/< IN IT, RI L>, <IN IT. R1H>/< INIT. R2L>, <lNl 1. R211> /<INJ T. RJL>, <IN IT. R3~1> l--------0 LOCATE IN

MACRO FILE

IN.PC_O:

·-------------------------------·;PC GETS 0

PC_R(ZERO),
FLAGI,
RETURN [1J

CLEA~

IN.VA_O:

:FOR CHARLIE'S CLEAR TB SUBR
;RETURN+1

·-------------------------------·;VA GETS 0

VA_R[ZERO).
RETUnN (1)

;RETURN+1

IN.CN. JNtT:

.
.
·-------------------------------·

LONLIT_(41FOOOO),
SET FLAG2

IN. PSL. LONLI T:

;LO~LIT GETS 41FOOOO
;?~OCESS JNIT CLEAR FLAG2

.;PSL GETS LONLIT CLEAR FLAGO

·-------~-----------------------·

PSL_R[LONLIT),CLEAR FLAGO

;0------------------------------;;JSR

PUSH,

5TEPC 2.
CRAR_Zt.JTO[OOJ.
NEXT /Ttl\. po_o

3631

U 0021, B9EF,5BE6,0308,2C50,0BAO

:PROCESS (NIT CLEAR FLAG2
;GOTO REG FLOW

3632
3633
3634

CO~REGS_D_M(Sl5R)_R[ZEROJ,

3635

DEC SJEPC

;CRAR GETS 2
;NJW IF ~E CONWRITE
;WE Will WRITE TO RXCS

:•------------------------------;;RXCS GETS 0
:SISR GETS 0

3636
3637

3:
REGION DIRECTIVE

I-'•

...,
0
0
0

0.,

Microcode

; CMT018.MCR (130,2112] Micro-2.1 1A(33)
14:40:3 9-Mar-1979
: MACRO .MIC [130,2112]
Control Store Region Expressions
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341

2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
235!
2356
2357
2358
2359

.roe

Control Store Region Expressions•

;Inltial~i=z=e__,..,..___,..~~~-~

.SET/INIT.R1L=0800
.SET/INIT.R1H=OFCF
.SET/INIT.R2L=0400
.SET/INIT.R2H=07FF
.SET/INIT.R3L=OOOO
.SET/INIT.RJH=OJFF

:Console
.SET/CONSOL.RllsOSOO
.SET/CONSOL.R1H=OFCF
.SET/CONSOL.R2L=0400
.SET/CONSOL.R2H=07FF
.SET/CDNSOL.R3Ls0000
.SET/CONSOL.R3H=03FF

•

;Integer, Loqicai, and Address
.5Ei/I~TLQG.R~L=0800

.SET/INTLOG.R1H=OFCF
.SET/INTLOG.R2L=0400
.SET/INTLOG.R2H=07FF
.SET/INTLOG.R3L=OOOO
.SET/INTLOG.R3H=03FF
;Floating Point and CRC
.SET/FLOAT.R1L=0800
.SET/FLCAT.RIH:OFCF
.SET/FLOAT.R2L=0400
.SET/FLOAT.R2H=07FF
.SET/FLOAT.R3L=OOOO
.SET/FLOAT.R3H=03FF
:Variaole Length Bit Field
.SET/VlELO.R1L=0800
.SET/VIELD.R1HsOFCF
.SET/VIELO.R2L=0400
.SET/VIELO.R2H=07FF
.SET/VIELO.R3Ls0000
.SET/VIELO.RJH•OJFF
:Control Instructions
.SET /CONT~L. R1 L•OBOO
.SET/CONTRL.R1Hs0FCF
.SET/CONTRL.R2L•0400
.SETiCONTRL.R2Hz07FF
.SET/CONTRL.RJL•OOOO
.SET/CONTRL.R3H•03FF

REGION DIRECTIVE MACROS

Figure 6-7

6-12

Microcode

CMT01B.MCR {130,2112] Micro-2.t tA(33)
14:40:3 9-Mar-1979
INIT
.MIC (130,21t2)
Initialize Microcode for the Console and Power up
3595 .TOC •
Initialize r.Hcrocode for the Console and Power up•
3596---W:"l
3597 jIN<i. . N,. ,._,l...,.N"'
. I._.f....,:j-.
SYMBOLIC ADDRESS
NEXT
:---------------------------~--:
ADDRESS 3599
3599
~
:LONLIT GETS 41FOOOO

7100,7DF0,7FFF,B4~0,@8\Ef 3601
3602

CLEAR ~lAG2.

3600

000,

NEXT/IN.PSL.LONlIT

3603
3604

.REGlON/<INlT.R1L>,<INIT.A1H>/<lNIT.R2L>,<INlT.R2H>/<INIT.R3l>,<1NlT.R3H>

3605

IN. PC_O:

~=g~

u 0818, ooeo.SBE4,0BOB,4850,0001

:PROCESS INtT CLEAR FLAG2
REG FLOW

LOCATE IN ;GOTO
MACRO FILE

~~=;(;;;~j:---------------------;PC GETS 0
FLAG1,
:FOR CHARLIE'S CLEAR ts SUBR
RETURN (1)
;RETURN•I

CLEA~

3608
3609

3610
36f 1

IN. VA_O:

:-------------------------------::VA GETS 0

3612

VA_R{ZERO).
RETUqN (1)

3613

U 0825, 4900,5BE4,0809,4A50,0001

3614
3615
3616
36f 7
3618

U 0839, 3S00,7DF0,7FFF,8450,083E

;RETURN•t

IN.CN.INIT:

:-------------------------------:: L01' LIT GtT S 41F0000

LONLIT_(41FOOCO),

3619

;~ROCESS

SET FLAG2

tNIT CLEAR FLAG2

3620
3621

U 083E, 0000,59F4,0304,0050,0820

3626
3627
3628
3629
3630
3631

3632
3633
U 0921, 99EF,58E6,0308,2C50,09AO

:-------------------------------:
FlAGO
;PSL

3622
36:!3
3624
3625

U 0920, 5AOO, C370, 0340 ,'2450, 481 S

IN.PSl.LONUT:

3634
3635
3636
3637

PSL_R(LO~llT),CtEAR

•O

GET~

LONllT CLEAR FLAGO

;o------ ··-- --- --·•------,----------:
PUSH,

STEPt: 2.

_z·_

:JSR

r:." i.

c?..i:;:
17c
NEXT. i'··; C_'J

;CRU GETS 2
:Ncr~ IF WE CONWRITE
:WE WILL WRITE TO R~CS

:t------------------------------:;RXCS GETS 0

co~~EGS_O_M(SIS~J_R(ZEROJ.

DEC STEPC

;SISR GETS 0

LABELS AND MACRO EXPANSIONS

Figure 6-8

6-13

Microcode

CMTOtB.MCR (130.2112} Micro-2.1 1A(33)
CONSOL.MIC [130,2112]
Ccnsole

14:40:3 9-Mar-1979
: CONSOLE EXAMINE ANO DEPOSIT

-------------:
1

Page 105

;4192
;4193
FINISHING OFF E OR D
;4194
·······················································-~···········••••••+*•
;4195
41 96~ CONSTRAINT BLOCK= 4 WORDS
;4197 CN.E.FLAGO:
;4198
:00-----------------------------;
;4199
FLAGO?,
;EXAMINE????
;4200
R[TEMP12)_RNUM,
;FOR POSSIBLE BUMPING RNUM LATER
U 093
08S6,0364,4330,0450,08C4 ;4201
NEXf/CN.E.FLAGO.CLR
;4202
;4203 CN.E.15.JT.A.SP:
;4204
;01-----------------------------;
PUSH,
;GET ~EXT CHARACTER
;4205
;4206
M[TEMP2J_ZLITO[O],
;TEMC2 GETS 0
NEXT/CN.GET.NEXT.CHAR
;RET+I
U 0931, 1862,C370,0300,0450,4A9C ;4207
;4208
;4209
;10-----------------------------:
FLAGO?
;EXAMINE????
U 0932, 4800,0364,4300,0450,08A4 ;4210
;4211
U0933 NOT USED
•4212
: 421 3 = END PREVIOUS BLOCK
- - - - - - - - - - - - - - : 4214 sO ....---------CONSTRAINT BLOCK= 2 WORDS
;4215
;0------------------------------:
;4216
we_~[TEMP6)-ZLIT0(2A},
:IS IT AN •
;4217
WX.EQ.0?,
;NO --•••*****•*•••••••DEPOSIT••••••••
NEXT;CN.NOT.ASTERICK
U 08
5806,C100,A315,0450,0860 ;4218
;4219
;4220
;..::!:1
~S-~[TE~P6]-ZLIT0[2A),
;IS IT AN•
WX.EQ.O?,
;NO --••·••••••••••••••EXA~INE•••·••••
:4222
NEXT/CN.E.NQT.ASTERICK
U 08A5, 5B06,C100,A315,0450,09AB ;4223
;4224
;4225 ~14•--------CONSTI'IAINT BLOCK., 8 WORDS
:4226 CN.NOT.ASTERicK:
;4227
:000----------------------------:
~8_M[TEMP6)-ZLITO[SO),
;NOT •-IS IT A P????
;4228
;4229
WX.NE.O?.
NEXT/CN.O.SL.P
U 0860, 1806,C100,A728,0450,0800 ;4230
;4231
;4232
:001----------------------------;
;4233
PUSH,
:PROCESS NUMBERISI
;4234
M(TEMPB]_ZLITO[OD],
;1 NUMBER TO PROtESS
;4235
SET FLAG!,
;FOR PROCNO
NEXT/CN.PROCNO
;RET+4 SO RETURN TO 101 :cN.D.ASTERICX)
U 0861, 14ES.C370,0306,8450,4BOO ;4236
;4:!37
. . - - - - - - - - - - - - - - ; 4238--E:l[!},.•--------LQCATION 5 OF 8 WORD BLOCK
;4239
;101----------------------------:
;4240
R(TEMP1)_M(VAJ,
;RESTORE TEMP1
;4241
NEXT/CN.O.ASTERICK

;1------------------------------;

ADDRESSING CONSTRAINTS

Figure 6-9

6-14

Pa\Je 34

; CMTOIB.MCR [130,2112} Micro-2.1 1A(J3)
14:40:3 9-Mar-1979
; DEFIN .MIC (130,2112)
Machine Definition
: ALPCTL
; 1166
; I IG7
; I 168
;1169
; I 170
; I 171
; I I 72
; 1173
; 1174
; 1175
: 1176
• 1I77
1170

1179
1100
110 I
1182

1183
I 104
1185

1166
1107
O'\

I
I-'
U1

1108
1189
1190

I 191
• I 192

1193

1194
1195
1196
1197
1198

1199

.TOC •

Machin~

Oef inltion

ALPCTL/=<57:40>,.0EfAULT•364
Nor=J6·1
wx_o_Q .o __ D=2D7
wx_D_Q.Q_M=OD7
WX D R .Q C<257
WX=D=R. o=r.1=057
wx_D_R.O_XM=157
wx_o_s .0 .. 0=357
wx_o_s.Q_r<=3D7
l~X D 5.Q Kl.1=107
l~X-Q~Q D~2C7

wx-o.o-r.hoc1
wx:R.Q=Q,.247
WX R.Q ~~=047

wx:R.Q=X~h147

wx_s.0_0=347
wx_s.Q_R=JC7
wx_s. o_xr.•= 1c7

: ALPCTL"

;ALU OPf RA l ION FOR
;SETTING OF ALU FLAGS
OtQ-1Cl.BCO
M-1QH: I. BCD
O+iHC I. OCO
M1·R-1Cl .UCO
XMHHCI .eco
0-151 O.BCD
R 1-S-1 O.BCD
XM+St o.aco
O-Q-Cl.BCO
M-Q-Cl.BCD
0-R-Cl.BCD
M-R-CI. BCD
XM-R-C I. UCO
o-s- 0. BCD
R-S- O.BCO
XM-S- O.BCD

;ALP SPECIAL FUNCTIONS
;ALUOO/OR,MUX/Z.S,001/NOP
;A'MUX & D <- Q OLD
Q <- 0 Ol.D
;w.1ux & D <- Q OLD
0 <- MBU5
;wr.1ux & 0 <- RBUS
Q <- D OLD
;Wr.HJX & 0 <- RBUS
Q <- MBUS
Q <- S/Z MBUS
;Wl11UX & D <- RBUS
;Wl11UX & 0 <- SUP ROT
Q <- 0
:wt.IUX & D <- SUP ROT
Q <- RBUS
;WMUX & D <- SUP ROT
Q <- S/Z MBUS
<- Q OLD
;wr.1ux
0 <- D
;~Jl,1UX
<- Q OLD
Q <- MBUS
Q <- 0
<- RBUS
:wr.1ux
<- RSUS
; l.\~.1\JX
Q <- MBUS
Q <- S/Z MBUS
;wr.1ux
<- RBUS
Q <- 0
;wr.1ux
<- SUP ROT
<- SUP ROT
;WMUX
0 <- RBUS
<- SUP ROT
Q <- S/Z MBUS
;l~MUX

l~X_.NOT.5=360

;w:.1ux & 0 & Q <- SUP ROT
; :·Jl,1lJX & D
<- SUP =<OT
<- St.JP nor
<- SUP ROT
:~r.1ux
:wr.1ux & D & Q <- • NOT. (SUP ROT)
;WMUX & 0
<- .NOT.(SlJP ROT)
;Wl\1UX & Q
<- • NOT. (SUP ROT)
;~Jf.llUX
<- .NOT.(SUP ROT)

wx_o_DSL.SQL=24E
wx_o_DSL.SQR=24F
wx_o_DSR.SQL=24A
wx_O_DSR.SQR=24B

;Wi.lXU & D <- 0 SHF LEFT
:wraxu e 0 <- 0 SHF LEFT
:~mxu & 0 <- 0 SHF RIGIH
:wro.u .'1 D <- D SHF RIGHT

W!J LOOPF=370
WB-LOOPF.Q 0=379
WB-LGOPF.0-0•37A
we-LOOPF.Q-0 0=378
WB-ALUF=37C WB=ALUF .Q_S=37D
l~B AlllF.O S=37E
we:ALUF.Q=O_S=37F

;WB<Jt:30> <- O' LOOP Fl.AG
:~:e<Jt :JO> <- O'LIJOP fLAG
;wB<Jt :30> <- O'LOIJP FLAG
:wB<31:3C> <- O'LOOP FL.\G
;WB<J1:30> <- ALUSO'ALKC
;wfl<Jt :30> <- ALUSO'ALKC
;WB<Jt::>O> <- ALUSO'ALKC
;WB<31 :JO> <- ALUSO' AU<C

vlX_D_O_S=373
wx_o_S=J·n
wx_0_5=3'lt
wx 5=370
wx:D_O_.NOT.5=363
wx_o_.NOT.5=362
wx_o_.NOT.5=361

:wr.:ux & Q

0 <Q <Q <Q <-

SHF LEFT
SHF RIGHT
SllF LEFT
SHF RIGHT

(D-R-Cl).SL
(O-R-Cl).Sl
(O-R-CIJ.SR
(O-R-C1J.SR

1200

1201
1202
1203
1204

1205
1206
1207

noa

1209
1210

MtJLFAST ~, :279,

.VALIDITY:<VS0-54.21>

I 211

MULSL0\~+=278,

.VALIDITY=<0~0.051>

1212
1213
1214
1215
1216

MULFAST-=2C9,
MU LSLO/J- = 215B,
DIVFAST+=26C,
OIVSLOW+=25E,
DIVFAST-=27C,
DIV5LOW-=27E,
REM=26A,
DI VOA=27F,
OIV05=26F,

.VALIOITY•<VS0-54.21>
.VALIDITY=<050.051>
.VALI01TY•<V50-54.21>
.VALIDITY=<OS0.051>
.VALIDITY=<V50-54.2t>
.VALIDITY•<050.051>
.VALIDITY•<V050>
.VALIDITY=<VOSO>
.VALIOITY=<VOSO>

1217
1210

, 1219
; 1220

<- 0
<- 0
D
0 & D <- 0

D
Q &

<- 5
<- s

D <-

;MULTIPLY +RBUS BY Q (2 ITERATIONS PER CYCLE)
;MULTIPLY +RSUS BY Q t 1 ITERATION PER OCLE)
;MULTIPLY -R9US OY Q (2 ITERATIONS PER CYCLE)
:~ULTIPLY -RBU5 BY Q (1
ITERATION ~ER C)CLE)
;DIVIDE 0 BY +RBUS (2 ITERATIONS PER CYCLE)
;DIVIDE 0 BY +R6liS (1 lTERATICN PER CYCLEI
;DIVIDE Q BY -RBUS 12 ITERATIONS PER CtCLE}
;DIVIDE Q BY -RSUS (1 ITERATION PER CYCLE)
;Ut{51H FT REMAlt{OER (RBUS MUST BE 0)
;DIVIDE DOUBLE ADD
;DIVIDE DOUBLE SUB

MACHINE FIELD DEFINITION

3
......
0
l'1

0
0
0
0..
CD

Microcode

; CMT018.MCR (lJ0,2112) Micro-2.1 1A(33)
; MACRO .MIC (130,2112)
Basic Macros
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467

2468
2469
2470
2471

2472
2473
2474
2475
2476
2477

2478
2479
2480

24Bt

.roe •

14:40:3 9-Mar-1979

Basic Macros"

CCOP1
CCOP2
CLEAR A001(FLAGO)
CLEAR A002(FLAG1)
CLEAR BOOT( FLAG MMNOINT)
CLEAR fl.II.GO
CLEAR FLAG1
CLEAR FLAG2
CLEAR FLAG3
CLEAR FPO
CLEAR MOPZERO(FLAG1)
CLEAR MUL1{FLAG2)
CLEAR MUL2(FlAG31
CLEAR OPZERCtFLAGJ)
CLEAR oveq(FLAG2)
CLEAR REAQ(FLAG1)
CLEAR REGINT(FLAG1)
CLEAR SAMESIGN(FLAG4)
CLEAR STACK FLAG
CLEAR SUBIFLAG1)
CLEAR TP
CLHR UNOER(FLAG3)
CLEAR WR(TEtFLAG1 I
CLOBBER MTEMPO
CLOBBER MTEMPO DEF

•cc;ccoP1.cceR SIGND"
"CC/CCOP2.CC9R:SIGN0"
"MISC/CLR.FLAGO"
"r.':I SC/CLR. FLAG1"
"MISC/CLR.MMNCINT"
"MISC/CLR.FLAGO"
"MISC/CLR.FLAG1"
"!1'1 SC/CLR. FLAG2"
"MISC/CLR.FLAGJ"
"MISC/CLR.FPO"
"MISC/CLR.FLAG1"
"Ml SC/CLR. FLAG2"
"llllSC/CLR.:=LAG3"
"MISC/CLR.F-.AG3"
"MISC/CLR.FLAG2"
"MISC/CLR. FLAG1"
"MlSC/CLR.FLAGf"
"MISC/CLR.Ml'.INOINT"MISC/CLR. STACKFLG"
"MISCiCLR.FLAG1"
"MISC/CLR.TP"
"MISC/CLR.FLAG3"
"Ml SC/CLR. FLAGt"
"MSRC/TEMPO,SPW/MLONG"
"SPW/MLONG"

DEC STEPC
DISABLE INT
DIVOA so~ IN R[]
OIVOS SOR IN R[]
DJVFAST+ SOR IN R(]
OIVFAST- SOR IN R[J

"MISC/DEC.SC"
"MISC/SET.M~NOINT"
"ALPCTL/OIVOA,RSRC/~1.ROT/0"
"ALPCTL/OIVOS,RSRC/~1.ROT/0"
"ALPCTL/OtVFAST+,RSRC/~1.ROT/O"
"ALPCTL/OIVFAST-,RSRC/~1,ROT/0"

FLUSH XB

•wcTRL/PC_wa,wB_M[PC)"

IO RESET
IR01
IROX [)
ISIZE[)

"BUS/I 01111 l r"8UT/ IR0f"

MULFAST+ CANO IN R(]
MULFAST- CANO IN R[]

"ALPCTL/MULFAST+,RSRC/@1,ROT/0"

NOP

"ALPCTL/NOP"

PUSH
PUSH RBS+
PUSH RBS-

"JSR/PUSH"
"MSRC/PSHD.00"
"MSRC/PSHSUB"

2496
2497
2498

PROCESS IN IT

•BUS/PR IN IT•

2499
2500

RETURN (J
"SUT/RETU~N,NEXT/~1·
RETURN AND INHIBIT DESTINATIONS "SUT/RET.OINH"

2492

2483
:Z4S4
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494

2495

"BUT/IRDX.NEXT/~1"
"ISTRMiISIZE_OSIZE,DTYPE/~1·

"ALPCTL/MULFAST-,RSRC/~1.ROT/0"

BASIC MACROS

Figure 6-11

6-16

Page 65

Microcode

: CMT018.MCR [130,2112]
; MACRO .MIC [130,2112)
;2527
;2528
;2529
;2S30
;2531
;2532
;2533
;2534
;2535
;2536
;2537
;2538
:2539
;2540
;2541
;2542
;2543
;2544
;2545
;2546
;2547
;2548
;2549
;2550
;2551
;2552
;2553

;2554
;2555
;2556
;2557
;2550
:2559
:2560
;2561
;2562
;2563
;2564
;2565

.roe •

~icro-2.t

Page 67

Bus Function Macros"

READ
READ.LONG
READ. LO.NG. MCD
READ.MOO
READ.MOD.LOCK
READ.NOTRAP
READ.PHY
READ.SECOND
'KRITE
WRITE -M[)
WRITE -O
WRITE D+R( ]+AlKC
WRITE M[ I
WRITE M( ]+PSLC
WRITE M[ }+Q .
WRITE M(j+O+PSLC
WRITE M[ J-PSLC
WRITE M[ J-0
WRITE M[ J-0-PSLC
WRITE M().ANO.ZLITO(]
WRITE M[).ANDNOT.Q
WRITE M{].ANDNOT.R{]
WRITE M[).ANONOT.ZLITB(}
WRITE M{ J.OR.Q
WRITE M[).OR.R[]
WRITE M[ J.XCR.Q
WRITE M[]. XZ
WRITE NOTREG
WRITE 0
WRITE Q.NOT
WRITE R[ J
WRITE R[J+CONX(4)
WRITE R[)-D-ALKC
WRITE R[ J-M[ J
WRITE R[ )-M( }-1
WRITE XB PC_PC+t

;~556

;2567
;2568
:2569
:2570
;2571
;2572
;2573
;2574
;2575
;2576
;2577
;2578
;2579
;2580
;2581

1A{33)
14:40:3 9-Mar-1979
Bus Function Macros

WRITE XB PC_PC+4
WRITE ZU TO[]
WRITE. LONG
WRITE. LONC C
WRITE.LONG M(].ANONOT.Q
WRITE.LONG M[].OR.Q
WRITE.LONG.NOTRAP
WRITE. NOTRAP
WRITE.PHY
WRITE.PHY M[]
WR I TE • PHY R{ ]
WRITE. SECOND
WRITE. SECOND. UL
WRITE.UL M{]

"SUS/REA!::>"
"SUS/READ.LNG"
"SUS/REAO.LNG.~00"

"SUS/REAQ.r,•oo·
"BUS/REAO.UOD.LCK"
"BUS/RE~O.NT"

"SUS/READ.PHY"
"SUS/READ.SEC"
•eus1wRITE,WCTRL/WOR we·

"SUS/WRITE.WCTRL;WDR:~B.MSRC/P1,RSRC/ZERO.ALU/B-A-CI,ALUCl/ZERO.MUX/M.R1"
"SUS/~RITE,WCTRL/WDR_WB,MUX;R.Q.RSRC/ZERO,ALU/A-B-CI,ALUCI/ZERO"
"BUS/WRITE,WCTRL/WDR_W9,RSRC/~t.MUX/0.R1,ALU/A+B+CI,ALUCI/ALKC"
"BUS/WRITE,WCTRL;WDR_WB,MSRC/~1,ALU/OR,MUX/M.S,ROT/ZERO"

"BUS/WRITE,WCTRL/WDR_we.MSRC/~l.RSRC/ZERO,MUX;M.Rl,ALU/A+B+CI.ALUCl/PSLC"
"BUS/WRITE,WCTRL;WDR_WB,MSRC/~1,MUX/M.Q1.ALU/A+B+Cl"

"SUS/WRITE,WCTRL;W~R_WB.MSRC/~1.MUX/M.01,ALU/A+B+CI,ALUCI/PSLC"

• aus !WRITE, \liCTR l/ i•DR_\•IB, rt.St;C/1?1 • RSRC/ZERO. ~.'Qlx: ~,1. R1 • ALU/ A-B-C I. ALUC I /PSLC.
·sus/~AITE,WCTRL/WOR_~B.MSRC/•1.MUX/M.Qt,ALU/A-8-CI"
·eus;wRITE.WCTRL/WDR_WB.MSRC/~1.~UX/M.01,ALU/A-B-CI.ALUCI/PSLC"
"SUS/WRITE,WCTRL/WDR_WB,MSRC/~1.LIT!LITRL.LITRL/~2.ROT/ZLITO,MUX/M.S,ALU/ANO"
"SUS/WRlTE,WCTRL;WDR_~B.MSRC/•1.MUX/M.01,ALU/ANONOT"
"BUS/WRITE,WCTRL/WOR_WB.~SRC/~1.RSRC102,ALU/A~D~OT,MUX/M.R1"

"8US/WRITE,WCTRL/WDR_ws,MSRC;~1.LIT/LITRL,LITRL/~2.ROT/ZLIT8,MUX/M.S,ALU/ANDNOT"

"9US/WRITE.WCTRL/WDR_W8,MSRC1•1,MUX:M.Q1 ,ILU:CR"
"BUS/WRITE,WCTRL/~DR_WB.MSRC/@l,RSRC/P2,ALU/CR,MUX/M.R1"

"SUS/WRITE,WCTRL,WDR_WB.MSRC/Pt.MUX/M.01,ALU/XOR"
"SUS/WRITE,WCTRL;WOR WB,MSRC/~1.A(PCTL/WX S,ROT/XZ.MM"
"BUS/WRITE.NOREG.WCTiL/WDR_wa•
"BUS/WRITE. WCTRL/\•DR_wa. RSRC/ ZERO. MUX/R. o. ALU, OP."
"SUS/WRITE,WCTRL;WOR_WB,RSRC/ZERO,MUX/R.O,ALU;A-B-Cl,ALUCI/ONE"
·euS/WRITE,WCTRL/WDR WB.RSRC/~1.ALU/OR,MUX/R.S.ROT/ZERO"
"BUS/WRITE,WCTRL/WCR:wB,RSP.C/•1.ALU/A+B+Cl,MUX/R.S.ROT/CONX.SIZ,OTYPE/LONG"
"BUS/WRITE,WCTRL/W:R_WB.RSRC/Pl,MUX/D.Rt.ALU18-A-CI,ALUCI/ALKC"
"BUS/WRITE,WCTRL/WCR_W6.~SRCl•2.RSRC;@l,ALU/B-A-CI.~UX/M.Rt"

"SUS/WRITE,WCTRL/WDR_W6,~SRC~~2,RSRCl•1,ALU/B-A-CI.MUX/M.Rt,ALUCI/0NE"

"BUS/WRlTE,WCrRL/WDR_ws,MSRC/XB.PC_?C+I,ROT/ZERO,ALU/OR,MUX/M.S,
ISTRM/lSIZE_DSIZE,OTYPE/BYTE"
"BUS/WRITE. WCfl~L/'«OR_wa. MSRC/ xe. PC_?C+I. ROT /ZERO ,.l.LU/OR ,rl.UX/M. s.
ISTRM/ISIZE_DSIZE.OTYPE/LONG"
"BUS/WRITE. '.VCTRL/W:JR_'llB, AL PCT L/wx_s. ROT /ZLITO. LIT; LI TRL. LI TRL/l'1"
·eus;wRITE.LNG.lltCTRL/vlDR wS.lJR"
"SUS/WRITE.LNG,WCTRL/WOR:wa.UR,RSRC/ZERQ,MUX/O.R1,ALU/0R"
"SUS/WRITE.LNG.'llCTRL/WOR_WB.UR,MSRC/i?1,MUX/M.Q1,ALU/ANONOT"
"BUS/WRITE.LMG,WCTRL/WCR_WB.UR,MSRC/@t,MUX/r.1.01,ALU/OR"
·euS/WRlTE.NT.LNG"
"SUS/WRITE.NT"
"BUS/WRITE. PHY"
"BUS/WRITE.PHY,WCTRL/WDR_WB,MSRC/@1,ALU/OR,MUX/M.S.ROT/ZERO•
•suS/WRITE.PHY,~CTRL/WOR_wB.~SRC/~t.ALU/CR,MUX/R.S,ROT/ZERO"

"BUS/'NRITE.SEC"
"BUS/WRITE.UL.SEC"
"BUS/WRITE.UL,lllCTRL/lllOR_WB.MSRC/@11,ALU/OR,MUX/M.S,ROT/ZERO•

BUS FUNCTION MACROS

Figure 6-12

6-17

Microcode

: CMT018.MCR (130,2112} Micro-2.1 1A(33)
14:40:3 9-Mar-1979
; MACRO .MIC [130,2112]
Register Transf@r Macros
2586

.TDC •

Page 69

2587
2588
2589
2590
2591

2592
2593
2594

2595
2596
2597

2598
2599
2600

2601
2602

2603
2604

ALUS_BCO SIGN.ZERO(M[))
ALUS_SIGNO
AlUS U!llSGN
ASTLVL_M[].RL.24
ASTLVL_R[ ]_M[)
ASTLVL_[ J

"CCMISC/ALUS_osoz.ccsR_ALUS,MSRC/@1,RSRC;ZERO.ALU/OR,MUX/M.Rl"
•ctMISC/ALUS_SIGNO.CCBR_ALUS"
"CCMISC/ALUS UNSGN.CCBR ALUS"
•wcTRL/ASTLVL_;..;a,ALPCTL/wx_S,MSRC/tiill.ROT/P.R.MM.SIZ,OHPE/BYTE"

BUS GRANT M(J_IPL

"BUS/GP.ANT,WCTRL/GRANT,S~~/MLONG,MSRC/91"

CC_M[]
CC_M().NOTANO.R(]
CC_M[).OR.R[J
CC_M()_MS.ANDNOT.CONX(1)
CC_M[ )_MB. ANONOT. CONX( 4)
CC_M[)_MB.OR.CONX(1)
cc_M( LZLI TO( 1
CC_ZLITO( I

·cCPSL/CC_we.cceR_ALUS,ALU/OR.~UX/M.S,~SRC/@11,ROT/ZERO"

"WCTRL/ASTLVL_WB,SPW,RLCNG,RSRC/~1 ,ALU/OR.~UX/M.S,ROT/ZERO,MSRC/~2"

·wcTRL/ASTLVL_WB,LITRL/~1.LIT/L[TRL,ROT/ZLIT24,ALPCTL/WX_s·

·ccPSL/CC_111e.ccpR_ALUS,MSRC/~1.~SRC/•2.~UX/M.R1,ALU,NOTAND"
"CCPSL/CC_l•B.CCSR_ALUS ,MSRC/~1 ,RSRC/@2, MUX/M. Rt, ALU/OR"
"CCPSL.'CC_lllB.CCBR_ALUS. ALU/ ANONOT ,MUX/~.'I. S, SPW1MLCNG.MSRC/~1, ROT /CONX. SI Z, OT YPE/SYTE •
·ccPSL/CC_~e.cceR_ALUS,ALU/ANONOT,MUX/U.S,SPW.MLO~G.MSRC/•1 ,ROT/CO~X.SIZ.OTYPE/LONG"

. ·ccPSL/CC_1;B.CCSR_ALUS. ALU10R ,f,'.UXjrA. s. SPl//MLONG.MSRC/@!. ROT /CONX. SIZ. OTYPE; BYTE"

•ccPSL/CC_wa.ccsR_lLUS,SPW/MLONG,~SRC/•1.~LPCTL/WX_S,ROT/ZL!TO,LIT/LITRL.LlTRL/P2"
•ccPSL/CC_lllB.CCBQ_ALUS,ALPCTL/WX_S,ROT/ZLITO.LIT/LITRL,LlTRL/~t·

2E05
2606

cc_[!

"CCPSL/CC_wB.CCBR_ALUS,ALPCTL/wr_S,ROT/ZLlTO,LIT/LITRL,LITRL/~1·

2607

2609
2609

CONREGS_O_M[]_R[)
CONREGS_M[]
CONREGS_M( ].OR.ZLIT16[]

"WCTRL/CONWR I TE ,MSRC/~1. SPW/r.'ILONG, ALU/OR ,MUX/R. s. ROT /ZERO. RSRC/·~2. 001 ;o_wx"
"WCTRL/CONWRITE.we_r..i('?-1 J•

2610
2611
2612

CONQEGS_~[].RR.16

"lllCTRL/CO~JWRITE,ALU/OR,l!UX/M.S,MSRC/~1 .ROT/Z~IT16,LIT/LITRL,LlTRL/~2·
"WCTRL/CONlllR IiE. ROT /RR .MM.
CTYPE/WOl?D. P.~SRC/~1. ALPCTL/lllx_s·

CONREGS_R( )
CONREGS_ZL1T16[]

"WCTRL/CONWRCTE,ALPCTL;WX_S,ROT/ZLIT16,LIT/LITRL,LITRL/•t•

2613
2614
2615

CRAR_ZLITO[ J
CRAR_ZLIT 16[ 1

"WCTRL/LOADCRAR.ALPCTL/WX_S,ROT/ZLITO,LIT/LITRL,LITRL/~1"
•wcTRL/LOAOCRAR.LlTRL/'1'111,LlT/~ITRL,ROT/ZLIT16.ALPCTL/WX_S"

OIOD)_ZLITO[}
D_(P.t{ J. R!1. PI .ANO. R()
O_(R[] ~[j).RL.P
o_o+R[J
o_o+ZUTO[]
o_o-R[ J
o_o-zu roe l
0 O.ANO.ZLITO[]

•001 ;o_wx .ROT /ZL ITO. LIT /LI TRL, LI TRL/-?11. ALUOD/OR. co. MUX/Z. s·
·001 ;o_wx ,l'l.Sl<C/~1 ,·RSRC/f:o2. l<OT /RR .M~.!. p. ALU/ llND. Mi.JX/R. s·

2616
2617
2616
2619

2620
2621
2622
2623

2624
2625
2626

2627
2€28
2629
2630
2631

2632
2633
2634

2635
2636
2637
2638
2539

2640

o:o.AN~.ZLIT28[)

O D.XOR.ZLlT12()
o:M[}
O_PJ( J+R[]
D_M( J+ZLITO[]
D_M{]-R[ I
D_M( ) . A!>.iil. R{ J
O_M{ ] . RR. 1 6
O_M[].RR.16 Q_R[]

o_o o_o

s r z.

"WCTRL/CO~WRITE,ALU/CR,MUX/R.S,ROT/ZERO.RSRC:~I"

"ALPCTL/W~_o_s.~SRC/Q2.?SRC/~1.RCT;RL.R~.?·

•0Qt/O_WX,RSRC/•?1,MUX/D.R1 ,ALU/.l.+B+Cl"
"001 /D_WX .MUX/0 .S, ALU; A+B+Cl, F.OT /ZLI TO, LIT/LI TRL, LITRL/&91 •
"001/0_wx,RSRC/~1 .MUJl:/O.R1,AlU/A-6-CI"
·001 /D_wx. LIT/LI TRL. LI TRL/"'' • oar/ zu TO .MUX/0. s. ALU/ A-8-CI.
"001 /O_lrU, ALU/ ANO, MUX/0. S. ROT/ ZLI TO, LIT /LI TRL, LI TRL/@1 •
·001 ;o_wx. ALU/ '4111!),MIJX/O. s. ROT/ ZL IT28. LIT: !.I TP.L, l I TRL/•t.
"001/0_~X.MUX/0.S,ALU, XOR,P.0T/ZLIT12.LIT/LITRL,LITRL/~t·
·0011o_wx,MS~C/•1.RSRC/ZE~C.ALU/OR.MUX;~.R1"

"COl/D_~X.MSRC/~1,RSRC/~~.ALU/A•9+CI.MUX,'M.R1"

"001 ,'D_lllX. ALU/ A+B+CI, M:.J)( ,..M. S ,MSi!C/'!!11. ROT /ZLITO, LIT/ LITRL, LITRL/{12"
·001 /O_wx. MSRC/€01. RSR:,:e2 ,l.tUX/M. R1. ALU/ A-B-C I.
•001 /O_wx. ALU/ ANO ,Mt.:X, M. RI ,loilSRC/'1'111 'RSRC/.@12"
"ALPCTL/WX_O_S.MSRC/~t.ROT/RR.Ml.1.SIZ,OTYPE/WORO"
"ALPCTL/~x_o_s.a_R.MSRC/~t.ROT/RR.M~.SIZ.OTYPE/WORO,RSRC/,2"

"ALPCTL/wx_o_a.o_o·

D_Q_M(]

·0011a_o_~x.MSRC,,1,ROT/ZERO,MUX/M.S.ALU/0R"

O_R[]

"001/0_WX,ALU/OR.MUX/R.S.RSRC/@I,ROT/ZEP.il"

D_R{]-0-ALKC
D_R[]-M()
O_SEXT(M(])
O_SEXT(M[]) PL<4-0>_31 PL<S>_t

•001;o_wx,MSRC/~1.RSRC/ZE~O.MUX/XM.R,ALUXM/SIGN,•LU/OR"
"0Q1/D_wx,MSRC/@1,ROT/0LITO.PL_LIT,LIT/LIT~L.Llf~l/1FF,MUX/XM.S,ILU/ANO"

"OQ1/0_~X,RSRC/f1.MUX,O.R1.AlU/B-A-Cl,ALUCI/ALKC"
"001/D_wx,RSRC/~1.MSRC/~2.MUK;M.R1,ALU/B-A-CI"

Figure 6-13

6-18

Microcode

; CMT018.MCR [130,2112) Micro-2.1 1A(33)
14:40:3 9-Mar-1979
: MACRO .MIC [130,2112]
BranchinQ Macros
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
33g7
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417

.roe "

Branching Macros•

(M[TEMP3]-SL)SYTE RANGE CHECK?
(PL+SLJ.GT.327

"BUT/SRKSTA,MSRC/@1.MUX/M.S,ALU/A-B-CI,ROT/SL"
"BUT/SRKSTA,ROTSRK/VIEL0.000"

ABSVAL M[]<7-0>?
ADD1(FlAGO)?
AD02{FLAG1) AOD1(FLAGO)?
ALLOi'I INT?
ALUS?
APT LOAD?

"SUT/FLAGO"
"BUT /FLAG! TOO"
"BUT/CC8R1.INT-TS"
"SUT/CCSR,CC/NOP.CCBR ALUS"
"CC/NOP.CCBR_ALUS,Bur7ccBR"

"BUT/SPKSTA,ROT/MINUS1,MSqC/~1,MUX/M.S,ALU/ANO"

·suT/SRKSTA,ROT/BCOSWP,MSRC/~1·

BCD SIGN r.1[]?
BCD SIGi'LZERO'?
BOOT(FLAG MMNOINT)'?
BRA ON ADO?

"BUT/CCBR,CC/NOP.CCBR_ALl.iS"
"9UT/MM.NOINT"
"BUT/BRA.ON.ADO"

CCOPI SIGNO?
CCOP2 SIGNO CMP .NOT.IRO'?
CHECK INTERRUPTS?
CMP SIGNS?
COUNT OR INT TIMER'?

•suT/CCSR,CC/CCOP1 .CCBR_SIGNO"
"SUT/CCBR1.CCBRO.IRO,CC/CCDP2.CCSR_SIGNO"
"BUT/CCBR1.INT-TS,OTYPE/LONG"
"BUT/CCSR,CCMISC/NOP.CCSR CSIGNS"
·euT/CCBR1.INT-TS"
-

OBZ STEPC?
DSIZE?

"SUT/DBZ.sc·
·euT/DSIZE"

EXPONENT RANGE?

"BUT/SRKSTA"

FLAGO?
FlAG1 FLAG2.XOR.FLAG3?
FLAG!?
FLAG2'?
FLAG3?
FLAG<1-0>'?
FPO'?
FPS3?
FRO. FLTZ?

"BUT/FLAGO•
"BUT/F1.XOR23"
•sur /FLAGI.
"SUT/FLAG2"
"BUT/FLAGJ"
"BUT /FLAG HOO•
"BUT/FPO"
·suT/FPSJ"
"BUT/FRO.FLTZ"

HALT?

"BUT/FPS1"

INTPENO OR TIMER?
IP.TS'?
IR<2>?
IR<S>?
IA<2-0.>'?

"SUT/CCSRt.INT-TS,CCMISC/NOP.CCBR_BRATST"
·sur /IR2"
"BUT /IRS"
"BUT/IR.2TOO"

LOO INC SRA'?

"BUT/LOO.INC.BRA"

MOR GPA.A RNUM.E0.7'?
MOR=ZEXT(OSR) BRATST?

"SUT/SPASTA,WCTRL/MCP._wB,RSRC/GPR.R,ROT/ZERO,MUX/R.S,ALU/OR"
"BUT/CCBR,CCPSL/MOR_OSR.CCBR_BAATST"

VECTOR?

341~

~HCRO

3419
3420
3421

MM IPENO OR TIMER?
MM.ALLOw. !NT'?

"BUT/INT-TI~SERV"

"SUT/UVCTR,CLKX/XTND"
"BUT/MM.ALLOW.INT"
"9UT/MM.ALL0~.1NT"

BRANCH IN G MACROS.

Figure 6-14

6-19

Page 84

Microcode

CMf018.MCR ( 130, 2112) r.ncro-2.1 Ill J3t
14:40: J 9-Mar-1979
INIT
.MIC [IJ0,2112)
Initialize Mlcroc~de for th• Console and Po.er up
ABSOLUTE ADDRESS

NEXT
AOORESS

7100.70FO,

7FFF,8450,~e\Et

U 0918, OOB0.5EEd,OB09,4g50,0001

U 0~25,

U 0939,

4900,5~E4,0BD8.4AS0.0001

JS00,70~0.7FFF,8~50,0BJE

U OBJE, 0000.59F4,0J04,0050,0920

3595 .TOC •
lnitialtz~ Uicrocode for the Console and
3596-W:l
3597 ITIT."""'.....
N ,.l'""N...
I ...
f.,...!Ja
SYMBOLIC ADDRESS

3599
3599
3600
3601
3602
3603
3604
36GS
3606
3607
3609
3609
3610
361'
3612
3613
:?614
3615
3516
3Sl7

3625

U 0920, SAOO.C370,0J40,2450,4918

U 0821, 89EF,58E6,0308,2CS0,08AO

3626
3627
3626
362'?
3630
3631
3632
3633
3634
3635
3636
3637

Powe~

:-------------------------------:

~
~v..i
~EX.T/IN.PSl.LONLIT

:LONLIT GETS

up•

41FOOOO

:PROCESS Hiil CLEAR FlAG2
LOCATEIN :GOTO REG FLOW
MACRO FILE
.REGIONi < INIT. RI L>, <lNIT. AtH> /<INIT. R2L>, < INI T. A2H>/<INI r. RJL>, < lNIT. R3~1>
-'-..:../

lN.PC_O:

:-------------------------------::PC GET5 0

PC_R(ZERO),
ClEA~

:FOR CHARLIE'S OLE•R Tl SU8R
;RETURN+t

FLAGt.

RETU"" {'}
IN.VA_O:

.·-------------------------------·:VA
.
GETS 0

V~_P(ZEAOJ,

RETUON lll

;PETUP~•1

lN.CN.Hlff:

.·-------------------------------·.

::s•e
3519
:?620
3521
J622
36:73
:!624

Pape 90

LO~LIT_(41FOOtOJ,

SE'i Fl-'Q2

:LOHLIT GETS 41FOOOO
INIT CLEAR FLAG2

:~~CCESS

lN.PSL.LO~LIT:

.
.
·-------------------------------·
:PSl GETS lONllT CLEAR FlAGO

PSL_R{LONllf),CLEAR FLAGO
•O

:o------ -- -- --------~---------:

:JSR

PUSH,

STEC::t. 2.

C? ~ ~

z· I~·~~ -

NEA;

I'··

·;_-;

:cqaq GETS 2

;NJW IF WE CONWRITE
:WE Will WRITE 70 RXCS

:'------------------------------:;RXCS GETS 0

co~~EGS_O_M(Sli~J_R[ZEAO),

DEC STEPC

:SlSq GETS 0

LABELS ANO MACRO EXPANSIONS

Figure 6-15

6-20

; CMT010.MCR (130,2112) Micro-2.1 1A(33)
14:40:3 9-Mar-1973
: MACRO .MIC [130,2112)
Register Transfer Macros

1-.i.j

~·
l.Q

"'I
._.
N

"'._.I

2641
2642
2643
2li4·1
26·15
2646
2647
2640
2fi4'J
2G50
2651
2652
2653
2654
2655

O_SEXT(:<B) PC_PC-t 1
D_SEXT(XBI PC_PC+2
O_ZEXT(M[J)
O_ZL I TO( I
O_ZLI JO( J-0
O_ZLIT12(]
O_ZLIT24( I

2656

ILONLIT_[

2657
2658
2659
2660
2661
21o62
2663
2664
2665
2666
2E67
2660
2669
2670
2671
2672
2673
2674
2675
2676
2677
2670
2679
2680
2681
2682
2683
2684
2605
2686
2607
2680
268'9
2690
2691
2692
2693
2694
2695

"DQ1/0_WX,MSRC/X8.PC_PC+f,RSRC/ZE~O,MUX/XM.R,4LUXM/SIGN,ALU/OR,OTYPE/BYTE,ISTRM/ISIZE_OSIZE"
"OQl/O_WX,MSRC/XB.PC_PC+l,RSRC;ZERO,MUX/XM.R,ALUX~/SIGN,ALU/OR,OTYPE/WORD, ISTRM/ISIZE_OSIZE"
"001/D_WX,MSRC/~l,RSRC/ZERO,MUA/XM.R,ALUKM/ZERO,ALU/OR•

"ALPCTL/WX_O_S.ROf/ZlllO,LIT/LITRL,LITRL/~1"

•oo I ;o_wx ,MU.</D. s. ALU/B-A-C I. RO r I Zl. I TO, LIT /Ll TRL. Ll TRL/<ll1.
"ALPCTL/WX_O_S,R0l/ZLIT12,LIT/LITRL,LllRL/~1"
"ALPCTL/WX_O_S,ROT/ZL1124,LlT/LITRL,LlfRL/~1"

FLAGS_D_R[ )
FLAGS_M[ J. ANO. ZLI JO()
FLAGS_R( J

"WCTRL/FLAGS_WB,RSRC/@1,ROT/ZERO,ALU/OR,MUX/R.S.001/D_WX"

INIR_M[ LO
IPL_M[) .RL .16

"WCTRL/INIR_wa.MSRC/Pl,SPW/MLONG,ALU/OR,MUX/R.Q,RSRC/ZERO"
"WCTRL/IPL_WB,ALPCTL/WX_S,MSRC/@1,ROT/RR.MM.SIZ,OTYPE/WORD"

il-0

MDR_(M[) R[]) .RR.P
MOR -I
MOR=-M[)
MOR 0
Mor(M[}
MOR_M[)+ALKC
MOR_M( )+R( l+ALKC
MOR_M[ I ~Zl. lT24[)
MDR _M( I. AtlD. OL ITB(]
MDR_M( ).ANO.ZLITO()
MDR_M( ).ASR.P
MOR_M( I. FPLI T
MOR_r.1() .OR. (R() .RR.24)
MDfl_Ml I .OR. ZLI T24()
r.~oR_M[ J. RL. 24
MOR_M(J.RL.8
MOR_M[ ).RL.9
MOR_M( }.RR.16
MDR_M( ).XOR.R()
MOR M[l.XOR.ZLIT12(}
MDR=M(}_R[}.RP..16
MDR_M( }_ZLI TO[}
MOR_Q
MOR_Q_M[ I
MDR_R( I
MDR_R[ )-M( )-ALKC
MORR( J.RR.24
MOR=R( )_M(}
MOR_R[ )_ RB-CONX.SIZ
MOR SEX f(M() I
MOR=SEXTtXCl+R[) PC_PC+l
MOR_XB PC_PC+2
MOR_XB PC_PC+4
MOR xe PC PC+I
MDR=ZEXT(M( J)
MOR ZEXT(OSR)
MOR=ZLlTO()
MOR_ZLIT16()

Paqe 70

"WCTRL/FLAGS_WB,MSRC/~l,ALU/AND,MUX/M,S,ROT/ZllTO,LIT/LITRL,llTRL/~2"
"WCJRL/fL4GS_W0,RSRC/~l,ROT/ZERO,ALU/OR.MUX/R.S"

tfi..:!!LONL~T ,LONLIT/<.NO_Tl<LONLIT /~1~~ LOCATE IN DEFINE FILE
•wcrRL/MOR_WB,MSRC/9t,RSRC/02,ROT/RR.MR.P,ALPCTL/WX_S"
"WCTRL/MOR_~a.ROT/Ml~USl.ALPCJL!WX_S•

•we TRL./MOR_Wll, MSRC/©l1. ALU/B-A-C I. ALUC I/ ZERO, RSRC/Z£RO ,MUX/M. RI.
"WClRL/r.•oR_O"
"WCTRL/MOR_W9,MSRC/~l,RSRC/ZERO,MUX/M.R1,ALU/OR"
"WClRL/MDR_W~.MSRC/~1,ALU/A+OtCJ,ALUCl/ALKC,RSRC/ZERO,MUX/M.RI"

"WC1Rl/MOR_Wll,MSRC/?1,RSRC/•2,MUX/M.Rl,ALU/At84Cl,ALUCl/ALKC"
"WCTRL/MOR_WB,MSRC;•1,ALU/AtB+Cl,MUX/~.S.ROT;ZLIT24,LIT/LITRL,LITRL/P2"
"WCTRL/MOR_WB,MSRC/@1,LIT/llTRL,LITRL/~2,ROT/OllT8,MUX/M.S,ALU/AND"

"WCTRL/MOR_WO,MSRC/•t,LIT/LITRL.LITRL/92,ROT/ZLITO,MUX/M.S,ALU/ANO"
"WCTRL/MDR_WO,MSRC/•t ,ROT/4SR.M.P.ALPCTL/~x_s·
"WCTRL/MOR_WB,MSRC/~1 ,ROT/FPLIT,ALPCTL/WX_S•
•wcrRL/MDR_WO,MSRC/@1 ,RSRC/@2,ROT/RR.RR.SIZ,OTYPE1LONG,MUX/M.S,ALU/OR"
"WCTRL/MD~_WB,ALU/OR,MUX/M.S.MSRC/~l,ROT/ZLIT24,LIT/LITRL,LITRL/@2"
"WCTRL/MOR_WB,MSRC/@1,ROT/RR.M~.SIZ,DTYPE/BtTE,ALPCTL/WX_S"
"WCTRL/MOR_W8,MSRC/~1 ,OlYPE/LONG,ROT/RR.M~.SIZ,ALPCTL/WX_S•
•wCTRL/MOR_WB,ALPCTL/~X_S,ROT/RL.MM.PTE,MSRC1~1·
•wcTRL/MOR_WB.MSRC/~l.ROT/RR.MM.SIZ.DTYPE,~OR~.ALPCTL/WX_S"
"WC1Rl/MDR_WB,MSRC/@1.RSRC/P2,ALU/XOR,~ux;M.RI"
MWCTRL/MOR_WB.WSRC/@1 ,ROT/ZLIT12,LIT/LITRL,LITRL/~2.MUX/M.S,ALU/XOR"
"WCTRL/M~R_WB,MSRC/~I ,SPW/Ml.OHG,RSRC/@2,ROT/RR.RR.SIZ,OTYPE/WORD,ALPCTL/WX_S"

"WCTRL/UOR_WB,MSRC/•I ,SPW!MLONG,LIT/LITRL,LITRL/P2,ROT/ZLIT0,ALPCTL/WX_S"
"WCTRL/MDR_WB,RSRC/ZERO,U~K/R.Q,ALU/OR"
"WCTRL/MDR_W0,001/Q_WX,MSRC/@1,ROT/ZERO.~UX/M.S.ALU/OR"

"WCTRL/MDR_WS,RSRC/01,ROT/ZERO.MUX/R.S,ALU/OR"
"WCTRL/MDR_WB,MSRC/92,RSRC;01,ALU/B-A-Cl,ALUCl:ALKC,MUX/M.R1"
•we fRL/MOR _WA. RSRC;flil1. ROT /RR. RR. s IZ. DTY PE/LOllG. AI. PCTL/WX_S"
"WCTRL/MOR_WB,RSRC/01,SPW/RLONG.MSRC/~2,ALU/GR,~UX/M.S,ROT/ZERO"
"WCTRL/MOR_W9,RSRC/@1 ,ROT!Ci~x.SIZ.MUX;R.S,ALU/A-B-Cl,SPW/RLOHG.DTYPE/IOEP"
"WCTRL1MDR_WB,MSRC/~1,RSRC/ZERO.~UX/XM.R,ALUXM/SIGN,ALU/OR"
•wcrRL!MDR_WB,RSRC/~1.MSRC/XO.PC_PC+l,r.IUX/XM.R,ALUXM/SlGN.ALU/A+B+CI"
"WCTRL/MDR_WB,MSRC/XO.PC_PC+I,RSRC/ZERO.~UX/M.R1 ,ALU/OR,ISTRM/JSIZE_OSIZE,DTYPE/WORD"

"WCTRL/MDR_WB.MSRC/XB.PC_PC+l,RSRC/ZERO,MUX/M.RI ,ALU/OR,ISTRM/ISlZE_OSIZE,OTYPE/LONG"
"WCTRL/MDR_WB,MSRC;XB.PC_PC+l,RSRC/ZERO.MUX/M.Rt ,ALU/OR,ISTRM/ISIZE_OSIZE,DTYPE/IOEP"
"WClRL/MOR_WB,MSRC/~1.RSRC/ZERO,MUX/XM.R,ALUXM/ZEAO,ALU/OR"

"CCPSL/MDR_OSR.CCBR_BRATST"
~wCTRL/MOR_WB,LJT/LITRL,LITRL/~1 ,ROT/ZLITO,ALPCTL/WX_s•

·wCTRL/MDR_WB,llT/LITRL,LJTRL/~1 ,ROT/ZLIT16,ALPCTL/WX_s•

MACRO EXPANSIONS 2

~·

0
0
0

a.
CD

Microcode

; CMT010.MCR [130,2112) r.licro-2.1 1A(33)
14:40:3 9-Mar-1979
; DEFIN .MIC [130,2112]
Machine Definition
: ISTRM, JSR, LIT, LITRL, LONLIT, MISC
: 1504
: 1505
; 1506
: 1507

:.1so0
,ltfS09
~1.11:s1

11s11
: 1512

: 1513
; 1514
;1515
:t516
;1517

;1518
;t519
: 1520

;1521
; 1522
;15::'3
: 1524
: 1525

.TOC •

: ISTRFA, JSR, LIT, LITRL, LONLIT, MISC"

Machine Definition

lSTRM/:<33:33>,.0EFAULT=O
NQP=O
; ISIZE IS DETERMINED e·f HARO\~ARE
ISIZE_DSIZE=1
;!SIZE IS DETERMINED av DSIZE

r.··

J9Rj=<14:14~;.0EFAULT:O ;SUBROUTINE CONTROL
NOP=Q
;NO OPERATION
PUSH"1
;PUSH CURP.ENT ADDRESS ON MICRO STACK

:<77:76>,.0EFAULTzO ;DEFINE UWORD FIELD INTERPRETATIONS
NORMAL:O
;FIELCS ARE NORMAL
LITRL:1
;SHORT LITERAL FIELD ENABLED
FPA~AIT=2
;WAIT FOR FDA TO COMDLETE PROCESSI~G
LONLIT=3
;LONG LITERAL FIELD ENABLED
LITRL/s<J9:31>

;SHORT LITERAL

ONLIT/=<62:31>

:LONG LITERAL

MISC/•<75:i1>,.CEFAULTs10
~lQP= 10

:DEFINE MISC FUNCTIONS

: 1526
: 1527

; 1520
: 1529

; 1530
: 1531
: 1532
: 1533

: 1534
: 1535
: 1536
: 1537

: 1530
; 1539
; 1540

;1541
: 1542
: 1:1:~
; 1544

: 1545
: 1546

: 1547
: 1548
: 1549
; 1550

;1551
; 1552
; 1553

CLR.FLAGO=O
CLR.FLAGl=1
CLR.FLAG2=2
CLR.FLAG3=3
CLR .Ml'ANOINT=4
CLR. SUCi<FLG•5

CLEAR FLAG 0
CLEAR FLAG 1
CLEAR H.:.G 2
CLEAR FLAG 3
CLEl.R FLAG 4
CLEf.R FLAG 5

SET. !"lAG0:8
SET.FLAG1=9
SET. FLAG::.'=OA
SET .FLAG3=08
SET .MMNOJIH=OC
SET.STACKFLGzOO

SET FL.lG 0
SET FLAQ 1
SET FL.AQ 2
SET FLAG 3
SET FLAG 4
SET FLAG 5

RSSC:IB
R:-.!UM_2REG=11
CLR.TPz12
CLR.FPOztC
SET.FPOs10
FORCE.TB= IE
FORCE.CACHE,,1F

R5TUP~ ANO SUPPRESS
CYCLE
R:~urn <- COMP MOOE SECOND REG

PSL<TP> <- 0
PSL<F?O> <- 0
PSL<FPO> <- 1
Foqce TB PARITY ERROR
FORCE CACHE PARITY ERROR

DEC.SC213
SC_2zt4
sc_s•1S
SC 14z16
sc:3ost7

STEP CNT <- STEP CNT - 1
STEP CNT <- 2
STEP CNT <- 6
STEP CNT <- 14
STEP CNT <- 30

aus

MACRO EXPANSIONS 3

Figure 6-17

6-22

Page 42

Microcode

CMT019.MCR (1J0,2tt2) t.Hcro-2.t 1A(33)
14:40:3 9-Mar-1979
lNIT .MIC (130,2112}
Inltfallze Microcode for the Con~ole and Power

'
U 0000, 7100,7DF0,7FFF,8450,083E

U 0816, 0090,SBE4,0B08,4850,000t

U 0825, 4800,SBE4,0808,4AS0,0001

U 0939, 3S00,70F0,7FFF,84S0,093E

U 093E, 0000,59F4,0304.00S0,0920

U 0920, 5AOO,C370,0340,'24S0,4818

U 0821, 99EF,5BE6,0308,2CS0,09AO

3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
361 t
3612
3613
3614
3615
3616
3617
3619
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637

.TOC •

IN. INIT:

lnitlallz~

Pape 90
UP

r.licrocode for the Console and Power up•

:-------------------------------:
LOCATEIN :LONLIT GETS 41FOOOO
3 MACRO
FILE

:PROCESS INIT CLEAR rLAG2
;GOTO REG FlOlil

.REGIONi<lNlT.R1L>,<lNJT.R1H>/<lNlT.R2L>,<INIT.R2H>/<lNIT.R3L>,<INIT.R3H>
IN.PC_O:

~~=;1;;;~j:--------------~----;PC GETS 0
CLEA~ FLAG1,
RETURN [1)

:FOR CHARLIE'S.QLEAR fa SUBR
:RETURN+1

JN.VA_O:

:-------------------------------:;VA GETS 0

VA_R(ZERO},
RETURN {1 I

:RETURN+1

IN.CN. !NIT:

:-------------------------------::LONLIT GETS 41FOOOO

LONLIT_[41FOOOO),
SET FlAG2

;PROCESS INIT CLEAR FLAG2

lN. PSL. LONLt T:
:-------------~-~~--------------:

PSl_R{LONllT),ClEAR FlAGO

:PSl GETS LONLIT CLEAR FlAGO

•O

:o------ -----------------------

PUSH.
STEPC 2.

JSR

CRAR_ZL 170(.0QJ.
NEXT IN •. PC_')

CRAR

GETS 2
NOW IF WE CON~RITE
WE WILL WRITE iO RXCS

;1------------------------------ RXCS GETS 0

CONREGS_O_M[SISRJ_R[ZEROJ.
DEC STEPC
'

MACRO EXPANSIONS 4

Figure 6-18

6-23

SISR GETS 0

Microcode

; CMf0f8.MCR (t30,2tt2) Mlcro-2.1 1A(33)
; MACRO .~IC {tJQ,2112)
Basic Macros
;2446
;24-17
;2449
;2449
;2450

;2<15f
;2452
:2453
;2454
;2455
:2t156
;2457
;2459
;2459
;2460

;2461
:2462
:2463
:2464

;24f;5
;2466
:2467
;2<168
;2469
:2470
;2471
;2472
;2473
;2474
;2475
;21176
;2477
;2478
;2479
;21100
;2401
;21182
;2483
;24e4
;2485
;2406
;2487
;2481)
;2'189
;2490
;2491
;2492
;2493
;2494
;2495
;2496
;2497
;2498
;2499
;2500

.roe •

t4:40:J 9-Mar-1979

Basic Macros•

CCOPI
CCOP2
CLEAR ADDt(FLAGO)
CLEAR ADD2(FLAGf)
CLEAR BOOf(FLAG MMNOINT)
CLEAR FL.AGO

~
CLEAR FlAG3
CLEAR FPO
CLEAR MOPZERO(FLAG1)
CLEAR MIJLl(fLAG2)
CLEAR MUL21FLAG3)
CLEAR OPZEAOIFLAGJ)
CLEAR 0Vf.q(FLAG2)
CLEAR REAO!FLAGfl
CLEAR REGINT(FLAGt)
CLEAR SAMESIGN(FLAG4)
CLEAR STACK FLAG
CLEAR SUBI FLAGf)
CLEAR TP
CLEAR UNOER(FLAGJ)
CLEAR ~RITE(FLAGf)
CLOBBER MTEMPO
CLOBBE~ MTEMPO DEF

"CC/CCOP1 .CCBR SIGND"
•cc;ccoP2.ccBR-SIGND"
"Ml SC/CU?. FLAGO"
"MISC/CLR.FLAG1"
·r.u SC /CL R. M~mo I NP
"MISC/CLR.FLAGO"
"Ml SC/ClR. FLAG!•

~LOCATE IN DEFINE FILE
"MISC/CLR.FLAG3"
•MISC/ClR.FPD"
"Ml SC/CLR. FLAG!•
"MlSC/ClR.Fl~G2"

"MISC/CLR.rLAGJ"
•Ml SC/ClR. FLAGJ"
"MISC/CLR.FLAG2•
•u1sc/tLR.FLAGI"
•uJSC/CLR.FLAG1"
"MISC/CLR .MMNOINT"
"MISC/CLR.STACKFLG"
•uISC/CLA.FlAG1"
"MISC/CLR.TP"
"MISC/CLR.FLAG3"
"MISC/ClR.FLAGI"
"MSRC/TEIAPO, SPlll/MlONG"
•srw/MLOHG"
"MISC/DEC.Sc·
•1,u SC/SET. MrAtlQ INT"

DEC STEPC
DISABLE INT
OlVOA SOil lN R()
OIVOS SOR IN R()
OIVFAST+ SOR IN R()
DIVFAST- SOR IN A()

"AlPCTl/DIVFAST+.RSRC/@1.AOT/0"
•AtPCTl/OIVFAST-,RSRC/9t,ROT/0"

FLUSH xe

"WCTRl/PC_we.we_M(PC)"

10 RESET

"ALPCTL/OIVOA,RSRC/~1,ROT/0"
•ALPCTL/OIVDS,RS"C/~l,AOT/O"

"BUS/tofNIT"
"9UT/1Rf'I•

IRD1
IRDX [)
ISIZE( I

"ISTRM/ISJZE_OSllE,OTVPE/CD1"

MULFAST+ CANO IN R()
MUlFAST- CANO IN A(]

•ALPCTl/MUlFAST-,RSRC/~1,ROT/0"

NOP

•.UPC Tl/NOP"

PUSH
PUSH RBS+
PUSH RBS-

"JSR/PUSH"

PROCESS IN IT

"BUS/PAIN IT"

"BUT/IRDX,NEXT/~1·

"ALPCTl/MUlFAST+, RSRC/«91 ,ROT /0"

"MSRC/PSHADD"

"MSRC/PSHSUB"

RETURN ()
"BUT/RETU~tt.NEXT/~t·
RETURN ANO INHIBIT OESTINATIO,,S •sur /RET .DINH"

MACAO EXPANSIONS 5

Figure 6-19

6-24

Page 65

Microcode

; CMT01B.MCR (IJ0,2112) Micro-2.1

: OEFIN .MIC [130,2112}

1A(33l

14:40:3 9-Mar-1979

Machine Definition

: ISTRM, JSR, LIT, LITRL, LONLIT, MISC

: 1504
: 1505

.roe "

: 1506

ISTRM/:<J3:3J>,.OEFAULT:O
NOPo:O
:ISIZE IS DETERMINED BY.HARDWARE
rslZE_OSIZE:t
:ISIZE IS DETEl<MlNED BY OStZE

;1507

ttsoe

..•t1!i09
';~.510

J1Stl
:1512
: 1513
;1514
;1515

: ISTRrA, JSR, LIT, LlTP.l, LONLIT, MISC"

Macnine Definition

J~R/,.<14:14>~.hEFAULT:O ;SUBROUTINE CONTROL
NOP~Q
;NO OPERATION
PUSH~
;PUSH CURRENT ADDRESS Otl MICRO STACI<

;1518

llT/=<77:76>,.DEFAULTeO :DEFINE UWORD FIELD INTERPRETATIONS
NORMAL20
;FIELDS ARE NORMAL
LITRL:1
;SHORT LITERAL FIELD ENABLED
FPAWAIT=2
;WAIT FOR FPA TO COMDLETE P~OCESSiNG
LONllTs3
;LONG LITERAL FIELD ENABLED

;t519
: 1520

: 1516
;1517

LITRl./s<J9:3t>

;SHORT lITERAl.

;1521
: 1522
: 15'3

LONLIT/:<62:31>

: LONG Lt TERAL

: 1524
: 1525

MlSC/•<7S:71>,.CEFAULTs10
HQP:10

:t526
; 1527
: 1529
: 1529

; 1530
;1531
: 1532

: 1533

CLR.FLAGO=O
CLR. FLAGbt

~
CLR.FlAG3:3
CLR .MfANOINT:<I
CLR. STACKFLG:S
SET. FLAGO=B
5ET. FLAG1:9

;DEFINE MISC FUNCTIONS
CLEAR FLAG 0
CLEAR FLAG 1
CLEAR !='1.,AG 2
CLEAR FLAG J
CLEAR FLAG 4
CLEAR FLAG 5

SET .MPANOINhOC
SET .SJACKFLG20D

SET
SET
SET
SET
SET
SET

;1541
: 1542

RSBC" 18
RNUM 2REG2 11

RETURN ANO SUPPRESS BUS CYCLE
Rr.itJM <- COMP MOOE SECOND REG

;1543

CtR.TP=t2

: 1544

CLR.FPD.,1C
SET. FP0:10
FORCE.TB=tE
FORCE.CACHE=1F

PSl.<TP> <- 0
PSL<Fl'D> <- 0
PSL<FPO> <- 1
fQqce re PARJTV ERROR
FORCE CACttE PARlTY ERROR

: 1534

: 1535

; 1536
: 1537

: 1538

: 1539

SET. FLAG:;>::OA
SE l. FLAGJ=OB

: 1540

: 1545
: 1sa6

: 1547

: 1548
: 1549
: 15~0
;1551
;1552
: 1553

DEC.SCstJ
SC_2:t4
SC_6=15

SC_14s16
sc_Jo=t7

HAG 0

FLAG 1
FLAG 2
FLAG 3
FLAG 4

FLAG 5

STEP CUT <- STEP CNT STEP CNT <~ 2
STEP CNT <- 6
STEP CNT <- 14
STEP CNT <- 30

MACRO EXPANSIONS 6

Figure 6-20

6-25

Page 42

CMIOte.MCR (IJ0,21121 Micro-2.1

INIT

U(J3f
14:40:3 q-M;ll'-Hl79
lnlt lal h:e MlcroC•">de for th~ ('>ll">Ole and Power up

.MIC [ IJ0,2112)

;3595
;3596

;3597
I

.TOC •

IN. INI 1:

;3599
;3599
;3600

NEXT l!iE PSL. IOiiiTfL

°'I
°'
N

'°c=

l"1

°'NI
I-'

INIT CLEAR FLAG2
;GOTO REG FLOW
LOCATE IN FIELDNAME & DEFINE VALUES cnEF

.REGION/< INIT. RI l> I< 11~1'. RtH>/<INIT. R2l>. <INIT. R21f> /< INI'. RJL> ,< INIT. AJU>

:3605

IN.PC_O:

; :t604

~~~;1~~;~1:---------------------;PC GETS 0
CLEA~

;3608
tZj

;PROCESS

;3603

;3607

......

:-------------------------------::LONLIT GETS 41FOOOO

LONllf_(41fOOOOI,

;3606
U 0818, 0000,5BE4,00D0,4050,000t

the Console and Power up~

CLEAR FLAG~

U 0000, 7100,7DF0.7FFF,0450,f0j3El ;3601
:3602
LOCATE IN UPC CREF-

lnlllallzei.li;;1·11<:01je for

Pape 90

FLAGI.
REIURN (I)

;3609

;FOR CHARLIE'S CLEAR TB SUBh
;RETURNtl

:3610
;3611

;3612
;3613
U 0025. 4800,50E4.000B,4A50,0001 ;3614
;3615
;36t6
;36t 7
;3618
U 0839, 3500,7DF0,7FFF,8450,00JE ;3619
;3620
;3621
;3622
U 083E, 0000,58F4,0304,0050,0020 ;36~3
;3624
;3625
;3626
;3627
;3628
;362!c'

U 0820, 5AOO,C370,0340,~450,4Dt8 ;3630
13631
;3632

;3633

;3634
U 0821, 89Ef,5BE6,0308,2C50,08AO ;3635

)N.VA_O:

~;=;·~~;~1~---------------------;VA GETS 0
REJURN f 11
;RETUAN+I

.·-------------------------------·.;LONLIT GETS 4tFOOOO

IN.CN. INI J:

LONlll_(41FOOOO),

SE r fLAG2

;PROCESS INIT CLEAR fLAG2

IN.PSL.lONllTI

~;~=;·~~~~~;J~~;;~;-;;;~~-------~PSL GETS LONLIT CLEAR FLAGO
;0------ -------------~---------

PUSH,

JSR

SIEPt;_~.

Cft.\ILZL 110(00).
NEXT /f'f9. Pr;_O

CRAR GElS 2
NOW IF WE CONWRITE
WE Will WRITE TO RXCS

;1------------------------------ RXCS GETS 0

COJ>REGS_D_M( s I SR LR I ZERO J.
DEC STEPC

13636
:.3637

SISR GETS 0

3:
......

NEXT ADDRESS FIELD

0
l"1

0
0
0

0.
CD

14:40:3 9-Mar-1979
CMT018.MCR ( '30, 2112) Micro-2.1 1A(33l
Cross Reference Listing field Names and Defined Values
I L.ROTLMEM
IL.ROTLREG
IL. SB•~CMEM
IL. SBWCREG
IL.SOR+.ENDt
IL.SOR+.ENDIL. SOR-. Er~Dt
JL.SOR-.ENDJL.SU02.0.W.L.MEM
JL.SUB2.B.W.L.REG
IL.SUB3.B.W.L.MEM
IL.SUB3.B.W.l.REG
ll.TST.0.W.L
JL.XOR2.B.W.l.MEM

°'I

.......)

~
I-'•

JL.XOR2.0.W.L.REG

l.O

IL.XORJ.B.W.L.MEM
IL.XOR3.B.W.L.REG

l"1

°'I
N
N

IN.CLR.CACllE
IN.CN. INIT
IN.DEC.D
IN. INIT
JN.PC_O
IN.PSL.LONllf
IN.VA_O
LS. LDPCTll.
·LS.LOPCTX.GPRS.0
LS.LDPCTX.GPRS.1
LS.LDPCTX.f'OBR
LS.lDPCTl\.PSL
LS.LOPCTX.PUSH
LS.LOPCTX.SUB1
LS .MODE. CHECI<
LS.SVPCTX
LS.SVPCTX.GPRS.2
LS.SVPCTX.GPRS.4
LS.SVPCTX. IPL
LS.SVPCTX.PC
LS.SVPCTX.SPS
MM.BUT.XB.TBMISS
MM.DEC.VA
MM. FLUSH. XO
MM.GET.ACY
MM.GET.BUT.FLUSH
MM.GET. BUT. PTE
MM.GET.BUT.PTE05
MM.GET.BUT.PTE10
MM.GET.BUT.PTE20

7818
6091
7818
6104
7918
7818
7825
7025
6320
6315 /I 7824
7824
#
6903
6974
6990
6900 #
6905 #
6991 II
6273 # 7032
7032
7860
7860
7846
6268 # 7031
7831
7859
#
7939
7839
6280
6274 II 7839
7839
7866
5877 # 7872
7872
7879
7886
7686
6354 # 7894
7894
79)8
7921
7921
6349 #
7893
7893
7920
6361 # 7901
7901
6355 # 7901
7901
7928
3664 II 3698
3616 ,, 4834
4892
3695 II
3667
3597
3605 /I 3630
3672
3601
lfilI.1}t-3611 II 3661
25797 # 26103
26103
25821 # 25033
25829 ,,
25016
25824
25835 II
25828
2sqo4 II 25928
25897
25931 #
25901
25934
25907
25940 II
25<)68
25801
26092 "
25964 /I 26133
26133
25976 • 25998
25984 II
25979
26025 II
26019
25982
25989
26044
26023
28659 #
28373
28380 " 28401
28G·l2
28649 #
20611
28725 II 20740
20807
29006 # 2<:!063
28662
28902 "
28\)89 II 29028
29004
23993
29C14 "
29044
29039
29046 "

7919
7025
7624

7818
7825
7824

7825

7832
7060
7031

7632
7060
7831

7032
7860
7845

7832
7860
7045

7853
7839

7853
7639

7866
7053

7066
7853

7872
7686
7894
7921
7093

7072
7086
7894
7921
7893

7872
7886
7894
7921
7907

7915
7901

7920
79t5

7928
7915

Page 075

7846

70•16

7046

7045

7845

7659

7059

7ll59

7853

7866

7056

7879

7908

7907

7920

7915

7928

7920

7928

5035

INDICATES LOCATION OF LABEL

26103

26133

20411
28825

28846

3:
......
0
l"1

29021

MICROINSTRUCTION CROSS REFERENCE

0
0
0

a.
CD

Microcode

CMT018.MCR [ 130,2112) Micro-2. 1 1A(33)
Location I

u 0708
u 0710
u 0718
u 0720

u 0728

u 0730

u 0738
u 0740

u 0748

u 0750

u 0758
u 0760

u 0768
u 0170

u 0778

u 0780
u 0788

u 0790
u 0798
u 07AO

u 07A8
u 0760
u 0786
u 07CO
u 07C8
u 0700
u 0708
u 07EO
u 07E9
u 07FO
u 07F8

u 0800
u 0810
u 0618
u 0820
u 0829
u 0830
u 0809

u 0830
u 0840

u 0848
u 0850
u 0858
u 0860
u 0868
u 0870
u 0878
u 0980
u 0880
u 0890

u 0898
u 08AO

u 08A8

u 0880

20852=
21156=
21347=
215702
21797•
22262=
22337:11
22390:s
22548:1
22915=
23298=
236J0s
24312:11
24630:1
24700:11
25237•
25645=
25624=
25934=
26362=
26i04z
~70C8:z

27180=
27717=
26157•
29248=
29920=
30264•
30892:a
31216•
31360=
16967•
1i003•
'7038•
17073•
3630=
17102•
17121=•
17141•
3683
29111•
4161 ..
3981
4230•
~6459•

3994
23222•
5537•
5119s
5663•
5700 ..
364Ja
9373s:
7014•

20858=
21161=
21350:
21574=
21800=
22265=
22340=
22394=
22552=
22919=
23302=
23635=
24315=
24633=
24704:
25243z
25649=
25828=
25938=
26366:
26708=
270110:
27183=
27722=
28160:
29252=
29923:11
30268s
30895.:
31219:s
31363•
16972•
11001 ..
17042•
17077s
3o3Sz
3687=
6526=
3619
3661=
28115s
4166•
28127=
4236s
26463:1
4267•
23227=
5096=
6568=
5668s:
6894=
3550:
9381s
7018s

20952:
21167:
21411=
21616=
21888=
22269=
22344=
22422=
22559=
23178=
23566=
23674=
24320=
24662"
24781:
25462=
25692"
2SS52s:
25979=
26390=
26757=
27034=
27436"
27833=
28193:
29:112=
JOOCSs

30274z
30961=
31225s
31371=
16977:
17012s
17047"'
t7082:z
17087=
171C7=
17126=
17146::
3667=
28119s
41i1•
5317:=
9439=
26467s
t0045s
23232=
5542=
4191
5673•
4321
3653=
12313:&
5334=

14:40:3 9-Mar-1979
Line Number Index

20958=
21171=
21416:s
21620=
21692=
22272=
22348=
22427=
22563=
23181.:
23570=
23678=
24323=
2.1666=
247870:
25.:165=
25666=
2:855=
25962z
26394=
26761=
27038=
27440=
27836=
261'?7=
2931Gs
3C009s
30277=
30964z
31229=
31374.a
1698h
17016=
17051=
3609
12632:0
2.1343=
6532=
23056a
3572=
29123=
28212•
5322=
9444=
2647h:
10C51z
23238•
5102=
6571=
Sc77s
6898s
4341
12317•
233ata

21079:
21290=
21447:
21684=
22221=
22281=
22352=
22433=
22G07=
23259=
23605=
23746=
24352=
24675=
24883=
25482=
25759=
25878"
26031=
26543z
26915"
27105:
27515=
27842=
2e-=49=
2"J368=
30203s
3oi;23 ..
30990a
31237"
3148Js
16986s
17021=
17056:
17868=
17092=
17112"
17131=
4016"
3677:
4070=
4177:1
4141=
3385
4152=
4275:
23241:=
51082
17974:11
5681=
17992•
4218:0
24294=
7022s

Page 951

21084::
21095= 21099=
21294=
21313= 21316=
2 I 461=
21450=
21456=
21588= .. 21730= 21733=
22247=
22225= 222·M=
22286= 22296= 22299=
22355=
22382=
22385=
22437=
22530= 22533=
22613= 22520= 22624:
23262= 23267: 23270=
23609= :03615= 23618=
23750=. 23968= 23971=
24618 ..
24614=
24356=
24679= 2.1687:1 24691=
24887= 24892= 24896=
25.!85= 25602-=
25E.06=
25816= 25819=
25763=
2se03=
25897= 25901=
26034= 26349a 26355=
26547= 26552= 26556=
26919= 26986=
26990=
27109= 27167= 27170=
27518= 27603= 27607=
273·15= 2SC80=
28084"
280::54= 23462=
26466=
29916=
29372= 29912=
30206=
3'225= 30229=
30849=
30'527= 308~4z
30994= 31104= 31108=
31240s 31350s 31353=
31486= 31493= Jl496:s
16995=
16999=
16990=
11025 .. 17030= 17034=
17069=
17060= 17065=
17877:
17881=
17972=
3614
17097=
12636=
17116= 24347=
3632=
15109:
15106:
17136=
4019:
~23060=---INDICATES LOCATION OF MICROINSTRUCTION
3699
3
7098=
AND THAT THE LOCATION IS NOT CONSTRAINED
4075:
26605= 23108=
4131=
4185=
26216=
4145:
26609= 23112:
15814= 15818:
42.ll"
4156=
J;sa
23116=
42792
15905• 15909:0
23253:
23245= 23249s
1se57,.
5113=
15863=
17977=
17981=
1i986=
5685::
5691=
5696=
17997: 18CO:.:?s
18007:
4223•
9361=
9365=
242980:
24302• 24306=
4377
::?3384=
5339=

MICROINSTRUCTION CROSS REFERENCE 2

Figure 6-23

6-28

Microcode

CMT018.MCR ['J0,2112} Mlcro-2.1 1A(33)
14:40:3 9-M.1r-1979
INIT
.MIC (130.2112)
InltlaHze Microcode for thP C·.,r;·.ole and Po•er UP

U 0000, 7100,7DF0,7FFF,8450,083E

U 0818, OOBO,SBE4,0B09,48SO,OOOt

U 0825, 4BOO,SBE4,0809,4AS0,0001

U 0839, 3S00,70F0,7FFF,84S0,083E

:3595
;3596
;3597
:3598
:JS99
;3600
;3601
;3602
:3603
:3604
;3605
:3606
:3607
;3609
;3609
;3610
;3611
:3612
;3613
;3614
;3615
:3616
:3517
;3618
;3619
:3620

FROM FIELD NAME CREF ~

:3622
U OBJE, 0000,5BF4,0304.00S0.0820J:;s;~t
FROMUPCCREF__/

:3~25

:3626
;3627
;3628
:3629
U 0820, 5AOO,CJ70,0340;~4S0,4818 ;3630
;3631
;3632
;3633
;3634
U 0821, 89EF,5BE6,0308,2CS0,08AO ;3635
;3636
:3637

Page 90

.TOC •
lnltializ~ ~icrPcode for the Console and Power up•
0:
IN.JNIT:

;-------------------------------::lONlIT GETS 41FOOOO.

LONlIT_(4t,OOOOJ.
CLEAR FLAG2,
NEXJ/JN.PSL.LONLIT

:PROCESS INJT CLEAR FLAG2
;GOTO REG FLOW

,.REGION/<tNIT.R1L>,<INIT.RIH>/<lNIT.A2L>,<JNIT.R2H>/<INIT.R3L>,<INIT.RJH>
IN.PC_O:

:------------------,------------;
.
:PC GETS 0

PC_R[ZERO),

CLEA~ FLAG1,
R~fURN [IJ

:FOR CHARLIE'S CLEAR tB SUBR
;RETURN+1

IN.VA_O:

:-------------------------------:;VA GETS 0

VA_R[ZEROJ,
RETURN (1 I

;RETURN+I

lN.CN.JHIT:

:-------------------------------:;LONLIT GETS 41FOOOO

LONLIT_[41FOOOOJ,
SET fl.\G2

;~ROCESS

INIT CLEAR FLAG2

IN. PSL. LONUT:

-------··----------------------:

PSL_R(LO~L£T).CIEAR

FLAGO

:PSL GETS LONLIT CLEAR FLAGO

;o------ ---- ---------------------:

PUSH,
STEPC_2.

;JSR

CRAR_z·.1 ~NOOJ.

;CRAA GETS 2
:NOW IF WE CONWRITt
:WE WILL WRITE ro AXCS

k!XT/N •• f't_O

:•--------~--------------------:

CON~;as_o_M[SI5RJ_R(ZERO).

DEC STEPC

;RXCS GETS 0
:SISR GETS 0

MICROINSTRUCTION CROSS REFERENCE 3

Figure 6-24

6-29

Microcode

CMT0t9.MCR (tJ0,2112) Mlcro-2.1 1AC33)
14:40:3 9-M~r-1979
INIT .MIC (130,2112}
Initialize Microcode for the Console and Power up

' 083E
U 0000, 7t00,7DF0,7FFF,9450

3595
3596
3597
3599
3599
3600

U 0825, 4900,5BE4,08D9,4AS0,000t

U 0939, 3500,70F0,7FFF,8450,083E

3604
3605
3606
3607
3609
3609
36t0
3611
3612
3613
3614
3615
3616
3517
3618
3619
3620
3621
3622

0000,58F4,0304.0050,0920

JN. INIT:

36'3

lnitializP- Microcode for the Console and Power up•

;-------------------------------::lONLlT GETS 41FOOOO

LONLJT_[41FOOOO),

3601
3602
3603

U 0918, 0090.55E4,0BD8,48SO,OOOt

.TOC •

Pape 90

CLEAR FLAG2.

:P~CESS

NEX1 IN.PSL.LorRlt

:GOTO REG now

WIT CLEAR FLAG2

.REG10N/<INIT.R1L>,<lNIT.R1H>/<INtT.R2L>,<INIT.R2H>/<lNIT.RJL>,<lNIT.R3H>
lN.PC_O:

:-------------------------------::PC

PC_A(ZE!fO),
FlAG1,
RETURN [ti
CLEA~

GET~ 0
;FOR CHARLIE'S OLEAR TB SUBA

;RETURN+1

lN.VA_O:

:-------------------------------::VA GETS 0

VA_R(ZERO).
RETURN (If

;RETURN+t

IN.CN.JNIT:

:-------------------------------:;LO"llT GETS 41FOOOO

LONLIT_(41FOOOOJ.
SET FUlG2

: ?ROCESS IH lT CLEAR FLAG2

._______ _____ ------------------.
:PSL GETS LONLIT CLEAR FlAGO

IN. PSl. LONlf T:

.....

PSl_R(LOHllT).ClEAR Fl.AGO

3624

U 0920, SAOO,CJ70,0340,2450,481B

U 0821, 89EF,5BE6,0308,2C50,09AO

3E25
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637

:o----- - . -- -----------.----------:

PUSH,
STE PC 2.
CRAR_z:. r- .:'~OOJ.
NUT/N... pc_o

:JSR
;CRAR GETS 2
;NOW IF WE CONWRITE
:WE Will WRITE ~O RXCS

:•------------------------------:;RKCS GETS 0

CO~REGS_D_M{Sl5wl_R(ZERO),

DEC STEPC

:SISR GETS 0

MICROINSTRUCTION CROSS REFERENCE 4

Figure 6-25

6-30

JBO.POWER.UP:
f

Microcode

0:
10 RESET

SETUP
250 MSEC
WAIT LOOP

CLEAlf
COLD
·START
·FLAG

-----~-~-------·------

DO MICRO
VERIFY
SEQUENCE

"%%"PRINTED AT CONSOLE

DO INIT
SEQUENCE

TK-4524

Figure 6-26

6-31

4 WAY BRANCH ON POWER ON ACTION SWITCU

BOOT
DO MICRO
VERIFY
AND INIT

RESTART/BOOT
BEGIN SEARCH
FOR APB

HALT

!START/HALT
ENTEH
CONSOLE
MODE

BEGIN SEARCH
FOR RPB

tzJ

.......

°'
I
w

'°c:...,
CD

l\J

°'I
l\J
....J

GO TO FIND RPB
ROUTINE

Rl GET
F28000
(MBAI

GOTO FIND
RPB ROUTINE

CONSOLE
PRINTOUT

%%
00000000016
GOTO
BOOT SUB

>>>
RETURN FROM· RPB ROUTINE

RETURN
FROM
BOOTSUB
CONSOLE PRINT OUT

PASS
DEFAULT
BOOT
ARGUMENTS

0000000011

>>>
IRD1
OF RESTART
ROUTINE

3
.....
1

...,

CONSOLE PRINT OUT

%%
00000000012

>>>
TK·4529

0
0
0
0.
CD

Microcode

IN.INIT:

LONLIT[41FOOOO]

IN.PSL.LONLIT

PUSH
D-ZLIT24[80]
.~_L§A R _E L~_G_1_

SOFTIPR-0

MP.MTPR

.T81A20

CLEAR SYS
128 ENTRIES
IN TBUFF

PSLA[ LON LIT]

TCSR-0

R~1:_URN (1_] --

PUSH,
STEPC·Z
CRAR-ZL!T16

PUSH,
ASTLVL-4
NEXT/IN.PC-0

PUSH
CONREGS-R
[ZE~_QL_

[80]

IN.PC.a
PC-R(ZEAOJ
CLEAR FLAG1
RE"'l'URN [1]

+1
PME-0
FPDO F FSET-3

PUSH
O.ZL1T8[4]

PROCESS
ANO 10 INIT
--

+1
CONREGS-0
-M[SlSR]R[ZERO]
DEC STEPC

J
-

VA.R[ZERO]
AETURN(11

CRAR
ZLIT16(CO]

PUSH
DEC STERC
CRAR-ZLIT16

vA...:.vA+4
CLEAR CACHE

[40]
MP.MTPR.

j_ T81A20
--- -·

CLEAR PX
128 ENTRIES
IN TBUFF

M[SCBB]-1
RETURN[1]

M[TElVIP6J
ZLITO(O]
RETURN(1]

RETURN [1]

-;"l(-4525

Figure 6-28

6-33

DEVICE C.

DEVICE A (SYSTEM DISK)

PC GETS ADDRESS
; OF DEVICE B CODE
READ

t'Zj

O'\

......
c::

"°

--·- ·-·- ·---

__.._...

_.PC GETS ADDRESS ~
OF DEVICE C CODE.
READ

·DEVICE D (TU-58)

PC GETS ADDRESS- ;.OF DEVICE D CODE
READ

l"1

°'I
N
\.0

,,_.,_

IRD1
OF BOOT ROM
MACRO
CODE

ENTER
CONSOLE
MODE

CONSOLE PRINTOUT

""
>>>

OOOFXXX 14

3
......
0
t"1

0
0
0
0.

, TK-4527

Microcode

BO.BOOT-SUB:
SET UP

LOOP TO
$GAN M_ErytQR_y
TURN CACHE

Qff___ --

TEST LAST
LOCATION

OF__64 KB

ENTER
CONSOLE
MODE_

CONSOLE

INVALIDATE
UBIO MAP

PRINTOUT

% ~7aw·~~~--

_REGISTERS

----,----.J >>>
0000000013

TRANSFER
BOOT ROM
CODE TO
MEMORY

INVA[JDATE
UBl1 MAP

REGISTERS

ENTER
CONSOLE

MODE

CONSOLE-PRINTOUT

%%
0000000015

>>>

TK-4523

Figure 6-30

6-35

Microcode

_P_AG~~Q_Q_~~S~

BO.FIND.APB.SUB

APB PHYSICAL ADDRESS

PHYSICAL ADDRESS OF RESTART

CHECKSUM

WARM START FLAG

SET UP

SCAN LOOP
VALID RPB HEADER

COMPUTE
CHECKSUM
ON FIRST

READ

PHYSICAL
PAGE

128 BYTES
YES

INCREMENT
PAGE
ADDRESS

READ
MEMORY
F_LAG

YES
RETURN

. TK-4526

Figure 6-31

6-36

Microcode

u 0016
C01'4TROL

TYPE2
SPACES

ENTRY POINT

CONSOLE
FLOW
ENTRY

CLEAR
COLD
START

TYPE
CONSOLE

PROMPT

TYPE 2
DIGIT HALT
CODE-

TYPE

<LF><CR>
THIS FLOW IS USED T-0 TYPE
THE PC, HALT CODE AND
PROMPT.

FLAG

· <LF><CR>
XXXXXXXX YY<LF><CR>
>>>

TYPE

<LF><CR>
AT CONSOLE
TERMINAL

TYPE_8 ______
DIGIT PC
SAVE MME

TK-41519

Figure 6-32

6-37

Microcode

PASS
SYNTAX

Af!.GQl\!IJ;J~!L

AB__G.Q~

PASS
SYNTAX
ARGUMENT

PASS
SYNTAX
.ARGUMENT

PASS
SYNTAX
A_RGUMENT

PASS
SYNTAX
ARGUMENT

PASS
SYNTAX
ARGUMENT
·-··
- --·-

PASS___ ----- .
SYNTAX
ARGUMENT

PASS
SYNTAX
ARGUMENT

sNT

·-·

T'<:-4'328

Figure 6-33

6-38

!NO

;WAIT FOR .
OPERATOR TO
ITYPE 2ND CHARACTER
I OF COMMAND STRING_

•
O'\

w
\0

I ANY CHARACTER OTHER THAN
i <SP>,<CR>,"/"
I >>>~<CR>
,...______.._
______
<CR>
~

'RING
BELL
AT CONSOLE

DISPATCH
COMMAND

j GET ADDRESS
,QR
I DATA STRING

IPROCESS
lcoMMAND
!SWITCH

3:
......

THESE COMMANDS
ARE NOT DISCUSSED
IN THIS SECTION.

0
t;

0
0
Q,
1

TK-462°2

t"lj

.......

Ul
CJ'\

I
.i:::.
~

'""
CD

CJ'\

>>>N<CR>·
SET UP
SINGLE
STEP MODE

>>>C<Cn>
SETUP
START WITH'.
OUT INIT

>>>l<CR>
SET UP ·
START

>>>T<CR>

: DO NOT
; CLEAR
SCBB

SETUP
'FOR
·MICRO VERIFY

DO INIT
SEQUENCE

:DO MICRO
. VERIFY
TEST

>>>H
HALT
NOP

TK-1520

3:
I-'•
0

'0""

0
0
0..
CD

Microcode

SAVE
PC

DO INIT

SEQUENCE

CLEAR
HALT
FLAG

RESTORE
PC
AND BEGIN

PRE FETCH

RESTORE
MME

BIT

•
IRD1

YES

OF MACRO

PROGRAM
-

TK-4521

Figure 6-36

6-41

Microcode

Figure 6-37

6-42

Microcode

llOMNEXT FIELD

xa<i:0>

---- -,

XB<lS:O>

I
I
__ ,_ _ .JI

r;:;;e1~
lllllUS

I
I

CSAOD<ll:O>L

STEP
COUNTEll

STATUS
FLAGS

<s:o>

I
I
I
I

PSI.
Tl'.FPO.Cll

CS ADO
<S:O>L
CSAOD

WW!
INTERFACE

BUT
FIELD

L-~

_.J

1.ATCHED NEXT flEL0<1:t:1>:

,.,.._,

Figure 6-38

6-43

Microcode

s ,......,.__
OR

IS EQUIVALENT TO

LOGIC Cl RCUIT EQUIVALENCES
TK-2097

Figure 6-39

6-44

:.--....&.---o

°'I

ii::=.
U1

IS EQUIVALENT TO

__r

3:
.....
0
l""'I

0
0
0

..._.....____ o

LOGIC Cl RCUIT EQUIVALENCES
TK-2098

Microcode

NEXT FIELD

<13:0>
13

CHIP ADDRESS, LOCATION WITHIN CHIP
- - - - - - - - - - - - - C H I P ARRAY SELECT, 1K BANK OF CHIPS

CONTROL STORE SELECT
O=CCS
1 = WCS,DCS

WCS,DCS
13 12 11 10
0 0 0-1ST K WCS

0 0
1 0 1 0
0 1

0
1 1 0
1 1
1 1

NOT USED

~-64WORDDCS

NOT USED

ccs
13 12 11 10
0 0 0 0
0 0 0 1
0 0 1 a
0 a 1 1
0 1 0 0
0 1 a 1
0 1 1
0 1 1

1ST K
2ND K
3RD K
4TH K
STH K
6TH K

~} NOTUSED

COMET CONTROL STORE ADDRESSING
TK-1985

Figure 6-41

6-46

Microcode
MICROWORD.

80 BITS
________________
,A______________-...

AMOUNT

ADDRESS

18K

3FFF

12K

23FF

2000

6-47

SELO H
SELO H
SEL 1 H

OCTAL

CS ADO 12 H
CS ADD 11 H
CSADDlOH

TO
UNITARY
DECODE

151

SEL 2 H
SEL JH
SEL 4 H
SEL 5 H

SEL 1 H
CS ADD 13 H
2ND
K

PAR
CHECK
SEL 2 H
CS PARITY·
ERROR

3RD
K
CS NEXT PARITY L

tTj

O'\

I
~

......
'°c::

CS NEXT
<13:6 >L

CD
O'\

CS ADO
<13:6>H

NEXT
FIELD
LATCH

t"1

MCLK L

SEL 3 H

4TH
K

5TH
K

DPM
CONTROL
STORE
LATCHES

DPM
.PARITY
CHECK

I
~

SEL4H

CSADD12H
CS ADO 11 H

0
DISABLE

ADDRESS
10

c
CS ADDRESS
BUFFERS
DISABLE HI NEXT H

6TH
K

3
.....

CS ADO < 5:0> H

...,
0
0
0
0..

SEL5H

ROM
BANKS

COMET CONTROL STORE SIMPLIFIED DIAGRAM
TK·199!S

Microcode

SAC
E68
SERVICE AND ARBITRATION CONTROL
MAIN TIMING CIRCUIT

-----~NBSCK

osc 1N H------..osc

MAIN TIMING MODE CONTROL
CIRCUIT ALLOWS SINGLE TICK, SINGLE
MICROINSTRUCTION, OR NORMAL
CLOCK CONTROL MULTIPLE CS
PARITY ERRORS STOP B CLK

CLK CTL 0 H ----~... CTLO

9 CSPE
CS PAR ERA H _ _ __..,.

CLKX H------~... CLKX
44
FPA WAIT L
FWA7
FPA STALL L
.:. FSTL
29
GEN OEST INH L ----t1i.tDINH.
32
DOUBLE ENABLE--....,.OBLE
10
PSL C MOOE H
~ PSCM
23
MSEQ INIT L
MINI

ENODt-- ---1--•

1-19
BUT CONTROL CODE H - - sec
17

---

BUT FIELD DECODING LOGIC

BUT2H-----~BUT2

BUT 1 H------1-~ BUT1

4 _ __.,INSTR FETCH H
IFET ...2...

THIS LOGIC IS USED TO DECODE
BUT FIELD AND GENERATE
VARIOUS INTERNAL CONTROL
SIGNALS

BUTQ H-----....,.BUTO

---- -- -- ---

1-- -

ARITH TRAP L - - -....
~... ATRP
47
FP TRAP L - - - - - - 1 . , . FPTP

SRVC,_3_4--•00 SRVC L
4
AOC2 0
~ CS ADO 2 L
ADC1 42
CS ADO 1 L

BUT SERVICE ARBITRATION LOGIC

_l CHLT

28
MKENt-- - - - M CLK ENABLE H
27
OKEN
D CLK ENABLE H

THIS CIRCUIT IS USED TO STALL
M CLOCK DURING MEMORY STALLS,
FPA STALLS, ETC. IT ALSO INHIBITS
THE D CLOCK WHEN NECESSARY
M CLK ENABLE ANO D CLK ENABLE
ARE GATED EXTERNALLY WITH B
CLK TO GENERATE MAIN SYSTEM
TIMING.

H---..,._..i TSER

1
HALT r--1---1--"i.HALT L

M CLOCK STALL AND D CLOCK
INHIBIT CONTROL

MEM STALL H ----..MBTL

CON HALT L

----11•

THE OSCILLATOR INPUT IS -:-3y 3
TO PRODUCE SET C, SET C BECOMES
BSCK EXTERNALLY, ANO IS USED TO
GENERATE PHASE. PHASE IS OSC. -:-5

CU< CTL 1 A -----1~ CTL 1
26

TIMER SERV

6
SET Cr-- - - - '
4
PHAS 1-

THIS LOGIC SELECTS HIGHEST
PRIORITY SERVICE REQUEST

ANO ASSERTS IT'S MICRO

INT PENDL----__. IPNO
37
PSL TP L ------1~~ PSTP

ADDRESS ON ADDRESS LINES

r---

ADCO

---

-- CS ADO 0 L

_,
ICT2i-2-2 ----1•1RD CTR 2 H

IRO COUNTER

THIS A3 STAGE COUNTER USED TO E~TER
ICT 1 15
OPERAND SPECIFIER AND EXECUTION FLOWS
21

-- IRD CTR 1 H

ICTO~--~ !RD CTR 0 H

351--

LD OSR L-------tMLDOSR
14
UTRAP L ------tMMTRP

LO OSR LATCH, MICRO TRAP LATCH

--1

LUTP ...__ __,.LATCH UTRAP L

MCLKL~-----------------20_.J
TK·1989

Figure 6-44

6-49

Microcode
B ClK L

MSQ
E58_
MICROSEQUENCER
33
NEXT05 H

NXTS

NEXT04 H

NXT4

NEXT/MICROSTACK
ADDER

NEXT03 H
NEXT02 H

NXT2

NEXT01 H

NXT1

NEXTOO H

NXTO

NSTACK 05 H
NSTACK 04 H
NSTACK03 H
NSTACK02 H

STK2

NSTACK01 H

STK1

THE MICROSTACK ADDER
IS PRIMARILY USED TO
ADO ON RETURNS FROM
MICRO SUBROUTINES BY
ADDING THE NEXT FIELD
TO THE ADDRESS AT THE
TOP OF THE MICROSTACK
OTHERWISE THE NEXT FIELD
IS USED DIRECTLY.

ADC5

CS ADD 05 L

ADC4

CS ADD 04 L

ADC3
ADC2
ADC1

CS ADO 03 L

25
21

ADCO

CS ADD 02 L
CS ADO 01 L
CS ADOOO L

NSTACKOO H

LIT 1 H

LIT1

LITOH

UTO

BUT CONTROL
COOEH

ace

BUT2H

BUT2

BUT1 H

BUT1

BUT OH
JSR H

FPA WAIT
WAIT

FPA WAIT L

IF LIT .. 2, THE FPA WAIT• L

BUT FIELD DECODE
LOGIC AND MICROSTACK POINTER
CONTROL
THIS LOGIC MOVES THE MICRO
STACK POINTER FOR PUSHES
ANO POPS OF THE MICRO
STACK. THIS AL.SO CONTROLS
CS ADDRESS BITS DURING
PUSHES ANO POPS.

ENZH
AOS3

4
9

ZERO HI NEXT
USTACK ADO 3H

ADS2

USTACK ADD

ADS1

UST.A.CK ADD 1H

AOSO

USTACK ADO OH
NSTACK OUT EN L

ENST
DSHN

DISABLE HI NEXT H

!RO ROM CONTROL
THIS t..OGIC EVALUATES IRD
COUNTER & BUT FIELD AND
ENABLES IRO ROMS, AND
LOADING OF CSR

ENABLE IRO ROM
LOAD OSR

INIT

MSEQ INIT L
MICRO ADD
INH L
ENABLE
UVECT H

MAI

DO SRVC L

SRVC

UVCT

42
ROMOS
OSGN
!NH.PHASE L H

MCLK L

ENIR
LO OSR

MISCELLANEOUS CONTROL
THIS IS GENERAL LOGIC THAT
AFFECTS THE OPERATION OF
MOST OF THE CHIP CIRCUITRY.

44
TK·1988

Figure 6-45

6-50

Microcode

DCLK ENABLE H

,J_
PHB E59
"PRACTICALLY-HALF THE BUTS"

WB 31 H

39
~

W830H
WB27 H

WBOSH
WB04H
WB03 H

WB31
WBUS

INTERFACE
WB30

W830
WB27

WBOS

WBUSOUT

WBUS IN
WB31

WB04

....6 INB03
~

THIS LOGIC CONNECTS WBUS
INPUT TO PSL BITS, STEPC,
AND CONTROL LOGIC, WBUS
OUTPUT IS MULTIPLEXED BET
WEEN THE STEPC, STATUS
FLAGS, AND PSL BITS

WB27
WBOS
WB04
WB03

W801 H

- WB02
.....
W801

W801

WBOO H

waoo

WBOO

WB02H

WB02

MISC CT L4 H
MISC CT L3H
MISC CT L2H
MISC CT L 1 H

MISC4

MISC 1

45
MISC CT LOH

MISCO

GO SAM 2H

GSM2
44

GO SAM 1 H
GO SAM OH

.....

GSM i

..... GSMO

...

PSCM
PSFP

?STP

IBUT

CTL 1

..... LDIR

CTL 0

46
10

OOSRVCL

SRVC
30

LDOSR L

LDOSR
7

DCSA
8UT 5

19
BUT4

8UT3

21
BUT02 H

..... BUT2

17
BUT01 H
SUTOO H

MCLK L

IRD CHIP CONTROL, RNUM
LOAD CONTROL, AND
MISCELLANEOUS
CONTROL

15
20

BUT04 H
8UT03 H

6
14
11

WBOSH
~

WB04H

--""

WB03H

--.....

WB02H

WB 01 H
WBOOH

ILRN

34
37

....
-- PSL CM H
.... PSL FPO H

31
29
32

PSL TRACE

~I RO ADD CTL t H

-- I RD ADO CTLO H

!RD LDRNUM H

INTR

INTERR UPTH

BUT OS H

DIS.CSA DORESS H

WB 27 H

THE MISCELLANEOUS CONTROL
FIELD OF THE MICRO INSTRUCTION SETS ANO CLEARS
STATUS FLAGS ANO LOADS
THE STEP COUNTER WITH
SEVERAL VARIABLES. THE
GOOO SAMARITAN ROM PROGRAMS PART OF THIS LOGIC

PSL BIT LATCHES

LO IR L

WB30H

FLAGS<S:O>

COMPATASILITY MODE LA.TCH. FPO
LATCH, T BIT LATCH, TRACE PEND·
ING LATCH ARE CONTAINED HERE.
FOR MICROBRANCH CONDITIONS
LONG L IT L

wa 31 H

STEP COUNTER <4:0> & STATUS

..... MISC3
~ MISC2

BUT 1

MICROBRANCH MUX
CONTROL
THE PHB CHIP CONTROLS A
MAJOR PORTION OF THE ~.11cRO BRANCHING lr..OGIC, THE
Fl.ELD
oecoDED AND
ENABLES A SPECIFIED BRANCH
CONDITION ON PSL BITS, STATUS
FLAGS, OR THE STEP COUNTER

su=r

SUTO

ace 4
ADC5
ADC4
ADC3
ADC2
ADC1
ADCO

..... BUT CONTROL CODE

CS ADD 05 L

CS ADD 04 L

.... CS ADD 03 L

9
~

--""
~

CS ADD 02 L
CS ADD 01 L
CS ADO 00 L

47J
Tl<-1991

Figure 6-46

6-51

Microcode

IRD E82
INSTRUCTION REGISTER, OP. SPE~. REG.

XBUF 14H
XBUF 1 3H
XBUF 12H
XBUF 11 H
XBUF 1OH

X815

22
20
47

XS14

XB14

X813

XB13

X812
XS11

....4 X810
~

X809

XBUF 9 H
XBUF 8 H

-- xsoi
.... XB07

24
XBUFS H

42
XB06

XBUF 5 H

....17 XS05

XSUF4 H

X804

XBUF 3 H

43
.....

X803

XBUF 1 H

1 XB02
1 XS01

XBUFO H

....1 XBOO

XBUF 2 H

XB15

XSUF 7 H

XS OUT

XSIN

19
XBUF 1SH

XBINTERFACE
THE OUTPUT OF THE XB
ROTATOR, BITS <15:0>
INTERFACE TO THIS CHIP.
THE IA IS LOADED FROM
XB<7:0>, THEOSR IS
LOADED FROM
15:8>
AT IRDX, THE WCTRL
MICRO ORDER 28 ALLOWS
THI; XS BUS TO SOURCE
THE IR ANO OSA, COM·
PATASILITY MOOE IS SLIGHTLY DIFFERENT.

xs<

XS12
XB11
XB10
X809
X808
X807
XS06
XB05
X804
XS03
X802
XS01

!ROAD OCTLO

LO IR L
IRD CON TROLL

?2
-- CTL1

23
30
~

CTLO
LOIR
SEL1

45
WCTRL 2L
PSLCM H

SELO
16

INSTRUCTION REGISTER<7:0>
LOADED FROM XS <7 :0 >
NATIVE MOOE OR <t 5:B>
COMPATABILITY MOOE.
OP CODE REMAINS HERE
THROUGHOUT MACRO
INSTRUCTION EXECUTION

LDOSR

IRD2
IRDt
IROO

OPERAND SPECIFIER REGISTER
<7:0>
THE OPERAND SPECIFIER REGISTER
IS USED TO ENTER OPERAND
SPECIFIER ROUTINE!fAT ---

LDOSR L

IR03

IRDX. THE ADC LINES ARE
ASSERTED AS A FUNCTION
THE ADDRESS MODE, RNUM
IS LOADED WITH <J :0 >
OF THE OSR, iSIZE IS A
FUNCTION OF DISPLACEMENT
SIZE WHICH OBTAINED FROM
ADDRESS MOOE.

XBUF 15 H
XBUF 14 H
XSUF 13 H
XSUF 12 H
XBUF11H

.... XBUF 10 H

..... XSUF 8 H

XSUF 9 H

24
42
17

XBUF 7 H

XBUF 6 H

XSUF 5 H

2
43

8
3

XBUF 4 H

XBUF 3 H

--....

XBUF 2 H
XBUF 1 H
XBUF 0 H
IR 7 H

.... IR 6 H
~

--....

IA 5 H
IA 4H
IA 3 H
IR 2 H

IA 1 H

IA 0 H

AOC3 29

CS ADD 03 L

..... CSAOO 02 L

ADC2
ADC1
ACCO
RNM3
RNM2
RNM1
RNMO

151
152
ORM
RGMD

MCLK L

IRD5 g
IRD4

!R06 6

PSLM

xeoo t
I RD7

\ROAOO CTL t

19
33

CS ADD 01 L

CS ADO 00 L

IRD RNUM 3 H

__..

..... IRO ANUM 1 H

I RD RNUM 0 H

44
21

IRD RNUM 2 H

DIS? ISIZE 1 H

.... DISP ISIZE 0 H
~

DST R :'.10DE H

..... REG MOOE H
~

Jij
TK-1990

Figure 6-47

6-52

ONE MICROINSTRUCTION
i.....~~~~~J20NS~~~~~.......,,._~

DPM17
BASE CLK L
DPM17
M CLK ENABLE H
l"1j
.....

Ul
O'\

I
U1

DPM17
OP CLK EN H

ct>
O'\

I
~
())

DPM17
BCLK L
DPM17
MCLK L
DPM17
0,D CLK L
DPM17
PHASE 1 H

TK-4313

3:
.......
0

0
0
0..

MICROINSTRUCTION WITH CLKX SET
480NS~~~~~~~~~~

DPM17
BASE CLK L
DPM17
M CLK ENABLE H

t'%J
.....
lQ

"'I

U1
.p..

c
...,

DPM17
Q,D CLK EN H

DPM17
BCLKL

°'
I
.p..

DPM17
MCLK L

LOAD NEW MICROINSTRUCTION

DPM17
D CLK L

DPM17
PHASE 1 H
TK-4314

3:
.....

...,0
0

0
0

°'CD

BCLK-L
;lJ

!MCLK-L
BUS ACLO L

l"Jj

°'I

U1
U1

IUBI 14 RCVD

.....

ACLOH

'°s::

IUBI 14 SYNCH A

l"1

'1>

°'I
U1

tSI

ACLOH

IUBI 13 E131-14
IUBI 13 ES48
SPFIL

IUBI 14 UBUS
DCLO

2-3 MSEC
TK-4316

::s:
.....
0
l"1

0
0
0
0..
'1>

PB INIT L

INIT BUTTON RELEASED

6.6 MSEC

UBI 14 PB INIT H
UBl13 E133-12

UBl14 UBUS
BBSY L
UBl13 E133-4

t'Jj

.....
O'\

I
U1
O'\

"°c

l"1
(\)

6.4 NSEC

UBl13 ASSERT
DCLOH
~

BUl14 UBUS
DCLO L

O'\

I
U1
~

UBl14 RCVD
DCLOH
UBl14 MSEO
INITL

1.9 NS

UBl14 UB INIT H

'UBl14 INIT UB
REOH
UBI 14 E133-12

.,J 70 MSEC

3
.....
0

.139 MSEC

l"1

0
0

TK~15

a.
(\)

Microcode
320NS
DPMl7 _____ -BASE CLK L
DPM17
CLK ENABLE H
DPM17
PCLK EN H
DPM17 CLK L
DPM17 CLK L
DPM17 D CLK L
DPM17
PHASE 1 H

f
DPM17 E25
CCS01 E6
DPM17 E58

LOAD NEW
MICROINSTRUCTION

------~' NExr <5:0> LATCH

I
l

NEXT <13:6> LATCH
- - - - - - - - - , C S ADD <5:0> L

CCS01 E7

------~'CS ADD <13:6> H

DPM17 E39

__________.lcs ADD <13:6> H

I
I

IADDRESS CONTROL ROM I

>e:_

_________________,X...__R_o_M_D_A_T_A_o_u_r_Pu_T_.......
;

-LOAO NEW
f
- - - - - - - - - - - - - - - - - ' MICROINSTRUCTION
TK~1

Figure 6-52

6-57

, CONTROL PARITY THIS
MICROINSTRUCTION

GENERATE CONTROL
STORE
ADDRESS 0020

DPM17 BCLK L

DPM17 MCLK L

DPM17 PHASE 1 H

'°~.
l'%j

°'I

DPM20
PARITYCS
ERROR H _ _ __..._ _

_,r....--......--. . .-.-t----......------L-

m
~

MIC UTRAP L

MIC GEN DEST
INH L
DPM17

ENABLE/UVECTH~~~~~~~~~~~~~~~~~~

_____.f LOAD 0020
INTO LATCHES
TK ....322

._..

0
i"1

0
0
0

a.
(I)

VAX-11/750 Level II

Data Path

Student Guide

Course produced by Educational Services Department
of

Digital Equipment Corporation

Data Path

INTRODUCTION
The COMET data path is 32 bits wide.
The main
components are five different types of LSI gate array
chips and two arrays of scratch pad registers.
Some
special features include a rotator capable of multiple
bit shifting and variable length bit field extraction;
an arithmetic and logic processor (ALP) capable of BCD
calculation and hardware controlled multiply and divide;
and two sets of scratch pad registers for microcode
temporaries.
Figure 2 depicts the block diagram of the data
Two tri-state buses
non-data path logic.
WBUS.

path~

are used to interface with other
The two buses are the MBUS and the

The MBUS is used to receive data from the scratch pad
and the memory interface logic.
Data coming from these
sources are latched during the first half of the cycle
and must be turned off during the last half of the
cycle.
The WBUS is used mainly to send the data path results tothe various destinations of the CPU.
Examples of these
destinations are the WDR (Write Data Register), PC, VA,
and the scratch pads, etc.
In addition, two other internal data buses are present.
These are the RBUS and the SBUS.
The RBUS interfaces
the ALP with the scratch pad array containing most of
the VAX architectural registers.
The SBUS sends the
rotator output to the ALP.
In general, data from the two arrays of scratch pad can
be operated on directly by the rotator and the ALU, with
the results written back to the same location in the
same cycle.

7-1

Data Path

OBJECTIVES
Identify the various data path entities by answering
multiple choice questions.
The entities will
include:
a)
b)
c)
d)
e)
f)

system clock and timing
control store
register
buses
super rotator
arithmetic and logical section

Utilizing the DPM pr int set, trace the signal path
for a preselected signal in the Comet data path.
Given a faulty processor, isolate the defective data
path gate arrays by running the
applicable
diagnostics.

SAMPLE TEST ITEM
The process of extracting and
operand is the function of the
a)
b)
c)
d)

zero

arithmetic and logical section
super rotator
control store
general registers

RESOURCES
Data Path Specifications
Microcode Listing

7-2

extending

Data Path

OUTLINE
VII.

3 Sections of Data Path
1.
2.
3.

Scratch pad
Rotator
Arithmetic & logical

Data Path Registers

Data Path Buses

Scratch Pad Logic
1.
2.

RAM R.
RAM M.

3.
4.
5.
6.
7.
8.

RSRC
MSRC
RNUM
RBS
SPA Status
Scratch Pad Address Control

Long Literal Register

Super Rotator Logic
1.
2.
3.
4.
S.

The
The
The
The
The

inputs
outputs
SRM chips
SRK chip
ALP chips

Multiple Bit Shifting

Variable Bit Field Extraction

Generate Constants

various Bit Shuffling

Rotation of Data

ALP Logic Section
1.
2.

Inputs & outputs
Misc signals & associated circuits

7-3

Data Path

OUTLINE (Continued)
M.

ALP Function
l.

2.
N.

o.
P.
Q.

Arithmetic
Others

ALP Control Function Chart
Microcode Example
Print Familiarization
Summary

7-4

Data Path

•INS

SIUS

WINS

DATA PATH 81.0CJC DIAGRAll

Figure 7-1

7-5

Data Path

WIDTH

CLOCK

SCRATCH PAD*
Q REGISTER
D REGISTER
LONLIT
RNUM
Resp••

32 BITS
32 BITS
32 BITS
32 BITS
4BITS
3BITS
6BITS
SBITS

D
aD
OD
D
D/M
M
D
D

PLATCH
SLATCH

.
\

*SCRATCH PAD REGS. ARE DIVIDED INTO lWO SECTIONS. 16M & 48R.

** RBSP POINTS TO A 6 WORD BY 7 BIT STACK CALLED RBS

DATA PATH REGISTERS
TK-3054

Figure 7-2

7-6

Data Path

Scratch Pad Section
The scratch pad section of the data path consists of the
Scratch pad register and the scratch pad address logic (SPA
chip). Figure 3 illustrates the associated logic.

7-7

WBUS
REG.NO.

I
I

t'!j

.....

-.]

I
00

"°....c::

-.]

LONLIT

32
LONG
LITERAL

1
~AM
~----

I
I

32
R
TEMPS

--- ---1I
32

GPR'S

RSPA

IPR'S

L---------

SPA

CHIP

~·
SCRATCH
PAO
ADDRESS
CONTROL

J__

BUT LOGIC
MSPA

r;-'- - AM

TEMPS

---- -_J_

,
I

I
_...J

RBS

32
MOUS

SCRATCH PAD LOGIC
rK 307:1

Data Path

RSRC

.ASSIGNMENT/PURPOSE

DUAL PORT TEMP 0

2
3

02
03
04

DUAL PORT TEMP 1
DUAL ?ORT TEMP 2

REG NO

DUAL PORT TEMP 3

DUAL PORT TEMP 4

DUAL PORT TEMP 5

5
6

DUAL PORT TEMP 6

DUAL PORT TEMP 7

8
9

R S-PAO TEMP 8
R 5-PAD TEMP 9
R 5-PAO TEMP 10
R S-PAO TEMP 11
R 5-PAO TEMP 12·
R 5-PAO TEMP 13
MEMORY MANAGEMENT TEMP 5
MEMORY MANAGEMENT TEMP 1

11
12

09
OA
. OB

13
14

RTEMP

Figure 7-4

~EGNO

RSRC

ASSIGNMENT/PURPOSE

GPRO

GPA 1

2
3

GPR2

GPR3
GPR4

GPRS

6
7

16
17

GPR 6
GPR 7

GPRS

9
10

GPR9
GPR 10

11
12
13

1C
10
lE

GPR 11
GPR 12
GPR 13
STACK POINTER
MICRO CODE TEMPORARY

GPR

Figure 7-5

7-9

Data Path

RSRC

ASSIGNMENT/PURPOSE

20
21

KERNEL STACK POINTER
EXECUTIVE STACK POINTER

22
23

SUPERVISOR STACK POINTER

INTERRUPT STACK POINTER

6
7

26
27

PROCESS CONTROL BLOCK BASE
MEMORY MANAGEMENT TEMP 2

2A
28

REG NO

0
1

11
12

14
15

USER STACK POINTER

MEMORY MANAGEMENT TEMP 3

PO BASE REGISTER
PO LENGTH REGISTER
P1 BASE REGISTER
P1 LENGTH REGISTER
SYSTEM BASE REGISTER
SYSTEM LENGTH REGISTER
NEXT INTERVAL REGISTER
MEMORY MANAGEMENT TEMP 4

IPR

Figure 7-6

REG NO

MSRC

ASSIGNMENT/PURPOSE

0
1

2
3

02
03

DUAL PORT TEMP 0
DUAL PORT TEMP 1
DUAL PORT TEMP 2
DUAL PORT TEMP 3

04
05
06
07
08

DUAL PORT TEMP 4

M S.PAO TEMP 9

5
6

1
8
9

DUAL PORT TEMP 5
DUAL PORT TEMPS
DUAL PORT TEMP 7
MS-PAD TEMP 8

13
14

MEMORY MANAGEMENT TEMP 0

OE
OF

SYSTEM CONTROL BLOCK BASE
SOFTWARE INT SUMMARY REGISTER

M S-PAO TEMP 10
ERROR CODE, MEM FAULTS & ARITH TRAP
FPO PACK ROUTINE OFFSET

--- .

MTEMP
TK-3069

Figure 7-7

7-10

Data Path
RSRC ASSIGNMENTS

OPERATION

HEX

RAM·R
REGISTER

00-00

TEMPO-TEMP13

MM.TEMPS

MM.TEMP1

10-10

RQ..R13

RTMPGPR

l<SP

ESP

SSP

USP

ISP

PCSB_

MM.TMP2

MM.TEMP3

POBR

POLR

P1BR

P1LR

SBR

SLR

SPNICR.SPtCR

MM.TEMP4

RSRC<S:O

Figure 7-8

7-11

TK-3060

Data Path

RSRC ASSIGNMENTS (CONT)

RSRC

<s:o>

RAM-R
REGISTER

OPERATION

HEX
30

TEMP.A

OST.R

IPR.A

CRP.R

(TEMPO)

(TEMP7)

LON LIT

(TEMPOt

ZERO

(TEMPO)

ZERO.CLRRBSP

TEMP.ROR1

OST.POR1

IPR.RORl

GPR.ROR1

TEMP.R+l

DST.R+l

IPR.R+1

GPR.R+1

TK-3061

Figure 7-8 (Continued)

7-12

Data Path

MSRC ASSIGNMENTS
MSRC<4:0>

HEX

RAM-M

OPERATION

DESCRIPTION

OO-OA

TEM PO-TEMP10

MICROCODE TEMPORARIES

ERRCOO

ERROR CODE

F PDOFFSET

FPO PACK ROUTINE OFFSET

MM.TEMPO

MEMORY MANAGEMENT TEMP

SC88

SYSTEM CONTROL BLOCK

BASE
OF

SISR

SOFTWARE INT SUMMARY

TEMP.A

MTEMP INDEXED BY RNUM

TeMP.R+t

MTEMP INDEXED BY RNUM+1

(TEMPOJ•

MOR

MBUS<··MDR

(TEMPO)•

WOR

MBUS<··WOR

(TCMPO)

PSHSUB

WRITE ··TO RBS

(TEMPO)

PSHAOO

WRITE +TO RBS

(TEMPOl

WBUS RNUM

WBUS<··PNUM

(TEMPO)•

XS.PC PC+1

M8US < • • XS, PC<·· PC+I

(TEMPO)•

MBUS<··MA

(TEMPOl.

PC BACK

MBUS < • • PC BACK

CTEMPC»•

MBUS<·· PC

(TEMPOt•

MBUS<··VA

(TEMPO)

READ RBS

(TEMPOa

RHUM WBUS

RNUM<··WBUS

(TEMPO)

WB RBSP

WBUS<·· RBSP

(TEMPO)•

MBUS <··TB DATA
TK-3079

Figure 7-9

7-13

Data Path

LOAD SIGNAL
ASSERTED

MSRC

YES

xxxxx

MICROSEQUENCER

11101

RNUM ._WBUS

11100

POP RBS

OPERATION
SPECIFIED

RNUM
CONTENTS
REG. FIELD SPECIFIED
BY ~ICROCODE
WBUS<3:0>
REG FIELD OF RBS

RNUM LOADING CHART
Tl<-3050

Figure 7-HJ

7-14

Data Path

I
RBS

, 10!110111110
I

t
6

I~~~OR

o s;ze

fEG1STER'.NuMBER:

RBS ENTRY

•AUTO-INCREMENT, WORD, REGISTER 6

RBS ENTRY FORMAT
TK-3062

Figure 7-11

7-15

Data Path

DATA TYPE

ENCODED
VALUE
ON SBUS

BYTE

0001

WORD

0010

LONG

0100

QUAD

1000

D
SIZE

. .... .,

ADO OR SUB

OPERATION

SUBTRACT (DEC)

ADD (INC)

OTHRU F

RBS ENTRY Fl ELDS
TK-3063

Figure 7-12

7-16

Data Path

IF RSRC OR RNUM SPECIFIES GPR
SPASTA
1:0

RNUM REG
CONTENT

GPA USE

1 110

VAX MODE SP

0111

COMP. MODE PC

0 1 10

COMP. MODE SP

ALL OTHER VAL.

IF MSRC SPECIFIES RNUM +- WBUS & RSRC IS NOT GPR
SPASTA

WBUS

1:0

3:0

IPR USE

0-4

PROCESSOR
CONTROL SP#S

5-7, E, F

RESERVED

8-D

ALL OTHERS

•

IF MSRC SPECIFIES A POP RBS & RSRC IS NOT GPR
SPASTA
. 1:0

RBS BIT6

INDICATED MODE

AUTO-INC

AUTO-DEC

-v

SPA STATUS
TK-3051

Figure 7-13

7-17

Data Path

IF MSRC SPECI Fl ES WBUS +- RBSP & RSRC IS NOT GPR

SPASTA

1:0

RBSP

RBS CONDITION

EMPTY

ALL OTHER VAL.

NOT EMPTY

IF RSRC OR RNUM IS NOT GPR, STATUS IS DEFINED
FOR THE FOLLOWING ONLY.

MSRC

OPERATION

68:64

SPECIFIED

..
111 00

POP RBS

1110 1

RNUM +-WBUS

11110

WBUS+-RBSP

SPA STATUS
TK-3064

Figure 7-14

7-18

ROUS

MBUS
<39:31>

LITRL

<63:56>

ROT

BMUX

.....
lO

I
~

p-~~,
ca1 SECOND
I

t'Zj

-...J

'CD""

WBUS

FIRST LEVEL SHIFT

LEVEL

--.L
36

MUX&MASK

- - - - - !.5..L
36

Pu£

....,J

SHF

I
~

_ _o_s_1z_E_____....

-----f;

PRI

0 CLK
-----~--~~

SEC

SAK

6
MUX

FIND FIRST

WMUXZ

SRK

STATUS

BUT LOGIC..,_

sous
ROTATOR LOGIC

Data Path

ROTATOR LOGIC
The rotator is conceptually a 64-bit in, 32-bit out barrel
shifter combined with a data shuffling multiplexer.
There are three sources of data into the rotator.
(1) MBUS, denoted by M, is normally used as the input
data <63:32> to the rotator.
(2) RBUS, denoted by R, is normally used as the input
data <31:00> to the rotator.
(3) LITRL, these are 9-bit input data directly from the
following micro-fields: RSRC, ISTRM and CC.
The 9
bit LITRL can be zero or one extended to 32 bit and
rotated by 0, 1, 2 • • • , 7 nibbles.
The barrel shifting operation is implemented in two levels.
The first level shifts the 64-bi t inputs right by 0, 4, 8
• • • • • 28 bf ts and outputs a 35-bi t intermediate result.
This level shifts the SBUS data right by 0, 1, 2, or 3 bits.
Outputs from the second level shifter will be denoted by
S<31:00>. By a proper combination of the two level shifts,
the 64-bit input data can be shifted right 0 through 31 bits
and left 1 through 31 bits.
The SBUS data can also be masked off starting from an
arbitrary bit position.
This, combined with the barrel
shifting operation, effectively executes a variable length
bit field extract, and zero extended operation.
The data shuffling multiplexer implements some VAX peculiar
functionality such as BCD swapping, convert from BCD format
to ASC I I , etc •

7-20

MBUS

R BUS

-------~---------------·--------~3
Y
o'

THE 32 BITS OF NEEDED DATA
<44:13>
RESIDE IN NIBBLES <11 :3>

SHIFT IN BITS TO

3231

: I ;+: I : f : I : ~ : I : i : I : ~ : I : ~ : I : ~ :·I : I
3
;

...J

I
N
I-'

- FIRST OPERATION -

;

... •

SHI FT RT 3 NIBBLES
- SECOND OPERATION SHIFT RT 1 BIT
SECOND
LEVEL
OUTPUT

I I

I I I

I I

I I I

I I h3
0

- - - - - 1 S T SHIFT, HOW MANY NIBBLES.
2ND SHIFT, HOW MANY BITS.

SHF

ROTATE RIGHT OPERATION
RR.MR.P
TK-3065

EXTRACT DATA STARTING
WITH BIT 20 AND ENDING WITH
... BIT 27. PUT DATA IN LOW ORDER

POS OF SBUS & ZERO EXT.
34
.....J

FIRST

N
N

LEVEL

s BUS

..-.r--9----.....---·----------.._..-.---...-------------------------..-......
~---.
0 I 0 I 0 0 I0 I 0 I 0
STEP2.
PASS FIRST 32 DATA BITS WITH NO SHIFT.

0
LEVEL

o~~~~~~~~~~~~~~~~~~-o

xlxlx(x xfxlxlx

OUTPUT

SEC

l+H +H=27

1 0

PAI

EE1 -·

SHF

I+ i+ !

ij=20

Posfil]=5

ROTATOR EXTRACT AND ZERO OPERATION
XZ.MR

TK-3066

16 NIBBLES/64 BITS

SRMDATA

f++++++ ls I+l+l+l H
1

STEP 1

SBUS BITS

<2:o>+-O

<3> +-1
<34:4>+-0
FIRST

LEVE+

SBU~

E!I ! ! ! I ! ! ! I i ! ! I ! ! ! I i ! !1!! ! I ! i3+H+I
O

.hEP2

SHIFTCONSTANTRT

0=8

""14

•

3=1

I+ ! I i i ! I ! i i I ! ! i I !! !I ! ! ! I ! ! ! I ! i3+H+I

SECOND 31.

LEVEL

OUTPUT

CONX.SIZ

SHF.V!M+I
TK-3071

THIS FUNCTION IS USED TO CONVERT A 4 DIGIT BCD STRING ON THE MBUS TO A

4 DIGIT NUMERIC (ASCII) STRING. TO USE THIS FUNCTION PROPERLY, A
CONSTANT XXX3 XX33 (HEX) MUST BE SET UP ON THE ROUS.

ALTERNATE 4 BIT CHUNKS FROM THE MBUS AND THE RBUS ARE SHUFFLED ONTO
THE SBUS AS FOLLOWS:
SBUS<03:00> < - MBUS<07:04>
SBUS<07:04> <-- RBUS<03:00>
SBUS<11 :08> < - MBUS<03:00>
SBUS<15:12> <-- RBUS<07:04>
SBUS<19:16>

<-- MBUS<15:12>

SBUS<23:20> <-- RBUS<03:00>
SBUS<27:24>

SBUS<31 :28:> < - RBUS<19:
16>
....

l'"Zj

-.J

I
N
.s::i.

......
l.Q
,.,c

RBUS

-.J

......

<- MBUS<11:08>

SBUS<34 :32> <-- 0

MBUS
24

20'

\.0

SBUS

CVTPN CONVERSION OF BCD TO ASCII (SHUFFLE)
BCD.SWP

TK-3063

16 NIBBLES / 64 BITS

l'Xj

......)

I
N
lJ1

......
~
..,c::
CD

FIRST

•

:LEVEL

o:o:o

.SBUS

......)

I
N
~

. SECOND
I

LEVEL

2
I

OUTPUT

.•

I
8

D SIZE<l:O>

3• I•

•

3•
I

BYTES
ROTATED

00
01

w
w

C1"

RR.MM SIZ ROTATE RT M BUS & M BUS

'"tJ
DJ
C1"

BY 2 BYTES· FOLLOWED BY CVTPN
TK-3057

!:3'"

SIGN/ZERO

SECOND u:vEi..

EXTEND
RBUS

OREG.

MBUS

CLA

- - . . Cl t

ALP(8t

C<7:0>

- - + BCDL

ALK

--+SB

Ff'S
ALKC

G<7:0>A&B

Al USO
TOG

LOOP
~

--+ LLIT L

l.Q

._..,. ASl031 l

.....

....J

I
N
O'\

++ AS1000l

........... 051031

l"1

....J

._.... OSIO 16

I
N
........

P<7:0>

,.__... BINC8 L
.,.___ 8COC8 l

+--- c
,..____ FS
.,.___ FOV

---+ MUXSEL

- - + MUXIUA

---+ MUXIUB

ALU

..,..__ MUXOUT

........ 05107
......, OSIOO

WMUX

OREG .

0 REG.

--+ PSL C
--+ ALUCJ1 L
4 - - SPWBENL

+ - SPWWENL
..._ SPWLEN l

~BMUX

~~o--

--+ ODCLKL

we us

+--DBL EN
. _ BCDL

t:J

,..__ CAR OUT l
+-BYTE l
-----10- - 1 1 ALPCTL <57:48

ALP LOGIC
TK 10111

Data Path

ALP LOGIC
The ALP is made up of eight identical slices of gate array
chips connected to perform 32-bi t binary and 8 digit BCD
arithmetic with carry look ahead logic.
Two internal
registers are provided for intermediate storages.
There are
logic:
l.
2.
3.
4.
5.
6.
7.

seven

major

sections

associated

ALU input mux, AMUX and BMUX
ALU
Output mux, WMUX
Q Register
D Register
WBUS control
Status logic

7-27

with

the

ALP

Data Path

A BCD STRING 1 2, 3 4 5, 6 7 8

lwouLo BE STOR:o IN MEMORY AS FOLLOWS:

12-ADDAESS

34-ADOAESS

X+ 1

56-AOORESS

X+2

78-ADDRESS

X+3

WHEN READ OUT AS A LONGWORD

11 8 5 6 3 4 1 21
APPEARS AT THE DATA PATH

NIBBLE

7 6 5 4 3 2 1 0

DATA

IN ORDER TO PERFORM AN ARITHMETIC FUNCTION ON TWO
SUCH STRINGS (ADO), THE CARRY FROM NIBBLE 6 WOULD
HAVE TO BE PROPAGATED TO NIBBLE 7, ANO NIBBLE 7
PROPAGATED TO NIBBLE 4, ANO SO ON .•..•
-

START

STOP

CLA
TIC-3052

Figure 7-22

7-28

Data Path

SIGN;ZERO
EXTEND

SECOND LEVEL

MBUS

RBUS

OREG.---.•- 32
32

DREG.

WMUX

32
32

BMUX

WBUS

ALP LOGIC
TK-3074

Figure 7-23

7-29

Data Path

ALU
--

Q REGISTER

ALUSHF • 011

ALUSHF •010

SHIFT

(ROTATE)

(SHIFT)

LEFT

SHIFT

d H b
a

ALU

0
ALU

ALU
LEFT

ALU

RIGHT
0

RIGHT

LEFT

RIGHT

NONE

LEFT

NONE

RIGHT

LEFT

RIGHT

NONE

®
r H

h
~ d h
ALU

cffi:

ALU

I .., ALU

G!] 4

!;,3,r I

~ CT]

13~
~CD

b CT]

@-CTI

d h
0

WBUS(31)

0(31)

*0(31) IS UNDEFINED FOR ANY LOAD 0 FUNCTION.

ALU/Q SHI FT & ROTATE
TK-3059

Figure 7-24

7-30

Data Path

THE ALU PERFORMS THREE BINARY ARITHMETIC OPERATIONS, iWO QUASI-BCD
ARITHMETIC OPERATIONS, AND FIVE LOGICAL OPERATIONS.

THE THREE BINARY ARITHMETIC OPERATIONS ARE:
A PLUS B PLUS CIN (A + B + CIN)
A PLUS .NOT.B PLUS CIN (A - B - CIN)
B PLUS .NOT.A PLUS CIN (B - A - CIN)

IN THlS MOOE, TWO CAR RY LOOK AHEAD SIGNALS (PANO G) ARE
CALCULATED BASED ON 16.

THE TWO QUASI-BCD ARITHMETIC OPERATIONS ARE:
A PLUS B PLUS CIN (A + B + CIN, BCD)
A PLUS .NOT.B PLUS CIN (A ~ B - CIN, BCD)

IN THIS MODE, THE OUTPUT OF THE ALU IS THE SAME AS
WERE DOING BINARY ARITHMETIC, BUT THE P AND G 51GNALS ARE
CALCULATED BASED ON 10. EXTRA LOGIC ARE USED TO ADJUST THE

4 BIT ALU OUTPUT TO A TRUE BCD RESULT.

THE-FIVE LOGICAL OPERATIONS ARE:
A.ANO.B
A.OR.a
A.ANONOT.S
B.ANDNOT.A

A.XOR.B

ALU ARITHMETIC FUNCTIONS
TK-3055

Figure 7-25

7-31

Data Path

ALU FUNCTIONS
THE ALU CAN PERFORM 16 LOGICAL ANO ARITHMETIC OPERATIONS
WHICH IS SPECIFIED BY ALPCTL <S:X>.
IN GENERAL, THE 16 ALU OPERATIONS ARE CLASSIFIED INTO THREE
GROUPS: BINARY ARITHMETI~. BCD ARITHMETIC AND LOGICAL.

ALPCTL <5:2>

ALU OPERATION

GROUP

0000

A-8-CI

BINARY ARITH

0001

A-B-CI, BCD

BCD ARITH

0010

(A-8-CI ).SR

BINARY ARITH

0011

(A-B-Cl).SL

BINARY ARITH

0100

A+B+cl

BINARY ARITH

0101

A+B+CI, BCD

BCD ARITH

0110

(A+B+cl) .SR

BINARY ARITH

0111

(A+B+CJ).Sl

BINARY ARITH

1000

A.ANO.a

LOGICAL

1001

A.OR.8

LOGICAL

1010

(A.ANO.B).SR

LOGICAL

1011

(A.AN0.8).SL

LOGICAL

1100

B-A-CI

BINARY ARITH

1101

A.XOR.8

LOGICAL

1110

A.ANO.(.NOT.8)

LOGICAL

1111

(.NOT.A) .ANO B

LOGICAL

NOTATIONS
A•AMUX
B= B MUX
Cl =CARRY INPUT
SR :i: SHIFT RIGHT
SL= SHIFT LEFT
TK-30!58

Figure 7-26

7-32

Data Path

MICROWORD

ALPCTL=<57:48>

I
I

I·

WHICH COLUMN

WHlCH ROW

WHICH O&D OPERATION

ALPCTL= 373

CHART FUNCTION

111

I
I
I

I
0

0I 1
I
I
I

; } EXAMPLE•
3

COLUMN "o" - AMUX GETS ZERO
BMUX GETS SUPER ROTATOR

- ROW"C"

BMUX MINUS AMUX MINUS CARRY IN

(SR-0-0)

OPERATION 3"

WMUX GETS SUPER ROTATOR

OREG & OREG GETS WMUX
•PASS THE SBUS THROUGH THE ALU

READING THE ALPCTl FUNCTION CHART
. TK-3056

Figure 7-27

7-33

Data Path

__[[;MICRO ORDER____.,
LU

AMUX,BMUX

A-8-CI

A-8-Cl,BCO

(A-8-Cll.SR

(A-B-Cll.SL

A+B+CI

A+B+Cl,BCO

(A+B+Cl).SR

(A+B+Cl).SL

0,01

0,02

o.s

A,Q

R,S

..
s·

A.ANO.B

A.OR.B

(A.AND.Bl.SR

(A.ANO.Bl.SL

8-A-CI

A.XOR.a

A.ANO.(.NOT.B)

{.NOT.A).AND.B

I
i-_::._T'.

..
;

wx~

Qt-Oo-WX

ALPCTL FUNCTION CHART COLUMNS A·F
TK-3087

Figure 7-28

7-34

Data Path

AL PC TL
This is a 10-bit field used by the data path to control the
ALP logic. The 10-bit field specifies 1024 functions. Most
of them can be grouped together based on (1) the ALU
operation, (2) the inputs to the ALU, and (3) the Q and D
registers control.
Such grouping of the ALP functions is
depicted in Figure 28, the ALPCTL FUNCTION CHART.
In the ALP FUNCTION CHART, there are 16 major columns. Each
column is identified by ALPCTL<9:6>, which in general
specified the inputs to the ALU.
There are also 16 major
rows.
Each row is identified by ALPCTL<S:2>, which in
- general specifies the ALU operation. At the intersection of
a major column and a major row, there are four blocks which
are further identified by ALPCTL<l:0>. Each block specifies
an operation on the Q and D registers with the given ALU
operation and the ALU inputs.
Functions that cannot be readily specified by the above
scheme are called ALP special functions.
All these
functions are marked off with a shaded corner in the ALPCTL
FUNCTION CHART.

7-35

Data Path

°tOllOITIONS

-·
llTrt

DUlllllG

'"°'

SIU$

~
IUTLOOIC

.. aus

QMG.

0
_.,....:..:.i)ltm
F•~iiJIMGPllt

Tr1 .- WA.

DREG.

MICRO ADDRESS IOS.RED+11
DATA '"TH ILCICIC DIAGRAM

llOVL IRDI+. R1

Figure 7-29

7-36

Data Path

WBUS

RSl'A
OSIZE

SAVE
AOOlliSS.DSIZ

••-Of' INCD
Gl'll.

@
ESl'AIUSH
a:JNSTANT•

WIUS

0
IUSIR&AO
LOAOlllOll
WITMGATA

f-111111
l.Ol:ATIOH

SPECIFIED
IYVA.

SIUS

lllUS

Qlllll.

DllEG

WIUS

MICRO ADDRESS 105..RED-AUTO.INCI
DATA PATH BL.CCX OIAGRAM

MOVL (ROI+, R1

Figure 7-30

7-37

Data Path

-· 0 ,

w•us

WlllTI DATA

lllTOGPll2

Wllllli

CONlllTIOlll

SETIY
HA-"I
OUlllNG
lllDX

~
~
1111'1.0GIC

....

,...,..

PUT-

llCUTIDATA

OATAOll

10-.

OllliG.

llllCllO ADDRESS llUIOV.8.W.L.REGI
DATA MTH ILOCX DIAGRAM

. llllOY\.111111+,lll

Figure 7-31

7-38

Data Path

CHAPTER 7

INTERVAL TIMER AND TIME OF YEAR CLOCK

7.1 INTRODUCTION TO INTERVAL TIMER
The Interval Timer is an integral part of the Comet CPU
hardware and it is used primarily to schedule events and
control the· amount of time a particular task can operate.
The operation of the Comet Interval Timer. from the software
level is consistent with other VAX family processors. Most
of the Timer is implemented within a gate array called TOK.
The Timer is implemented using a 10 MHz TTL oscillator, a
divide by HJ, and the TOK gate array. The Timer is
incremented at 1 microsecond intervals which makes the
operation consistent with other VAX family Timers. The
maximum
interval
then
could
be
expressed
as
(((2**32)-l)*.000001)/60 which works out to be around 71
hours or approximately 3 days. It does require external
dedicated scratchpads to maintain the interval count, so the
TOK gate array was placed on the OPM module. The Interval
Timer is accessible to the VAX-11 macro code through
Internal Processor Registers (IPRs) • These IPRs can be
accessed with MTPR and MFPR macro instructions, and also
from the console terminal. An explantion of the Internal
Processor Registers will follow in subsequent ·paragraphs.•
The Interval Timer operation is basically straightforward.
The operating system loads the Timer with 2's complement of
the desired interval a particular task must run. The Timer
is started with an MTPR instruction and when the Timer
overflows at the end of the desired interval, a macro level
interrupt request is booked with the CPU. If the IPL level
of the Timer Interrupt Request (IPL 18) is greater than the
current PSL IPL, the timer service macro routine is entered
via SCBB+C0. This would terminate the current task, if
something else of higher priority had not done so.
7.2 DETAILED DESCRIPTION OF THE TIMER CIRCUITRY
For the following discussion you will need the module
schematic diagram of the DPM and CCS ~odule. Refer to the
CCS module schematic page CCS14 and locate ES. ES is the 10
MHz TTL oscillator that provides the time base for the
interval timer gate array (TOK) on the DPM -module. The
output from ES goes to the 7490 IC which is a decade
divider. The output of E4 is a symmetrical 1 MHz signal that
provides the increment interval of 1 microsecond. The signal
TOK OSC OUT H is wired from slot S (CCS module) to slot 2
(DPM module). Refer to the DPM module schematic page DPM13.
The TOK gate array is shown in the lower left corner. The
signal TOK OSC OUT H enters the DPM module and goes to pin
4S of the TOK gate array. The other inputs to the TOK gate
7-39

Data Path

array are PROC !NIT L which will clear any interrupt
requests left in the gate array and set the logic to a known
state. BCLK L and D CLK ENABLE H are used internally to form
a D CLK to load the Timer control and data registers. Access
to the gate array is entirely controlled by the WCTRL field
of the microword which is used in the MTPR and MFPR macro
instructions and the interval timer service microroutines.
There is a full 32 bit bi-directional interface to the CPU
WBUS for reading and writing the timer control and data
registers. The signal TIMER SERVICE H that exits the TOK
gate array is used to signal the microcode that a
micro-routine to update the high half of the interval count
or a transfer of data to the IC.R register from the NICR
register is necessary. The signal TIMER INT L is the timer
interrupt request that is generated when the interval timer
overflows. This goes to the INT gate array on UBI so that
the interrupt request can be arbitrated among the other
requests. This concludes the detailed circuit description of
the Timer circuitry. Timer functionality is verified with
the Hardcore instruction test EVKAA. a failure of the timer
can be isolated to one of three components, the oscillator,
the decade divider, or the TOK gate array.
7.3 INTERVAL TIMER FIRMWARE REQUIREMENTS
The implementati'on of the Interval Timer in the Comet
CPU is not at first obvious. Figure 7-32 shows the VAX 11
Interval Timer IPRs as they appear to the software. There
are 3 registers associated with the Interval Timer. IPR 19
is the Next Interval Count Register (NICR) and this register
is loaded with the 2's complement of the desired interval.
The number loaded into this register is the two's complement
of the desired interval in seconds divided by 1 microsecond.
The IPR lA is the Interval Count Register (ICR) and it
contains the current count of the timer at all times. The
ICR is loaded from the NICR and the value in the NICR does
not change unless an MTPR instruction writes new data into
it. IPR 18 is the Interval Counter Control and Status
Register. This register controls the operation of the
Interval Timer. The function of the bi ts in the ICCS is
explained below.

7-40

Data Path

MAIN PARTITION IS BUSY
LOCATE FIRST SUBPARTITION

50$:

,, -IS THIS SUBPARTITION BUSY?

60$:

DETERMINE IF TASK WHICH OWNS
BUSY SUBPARTITION CAN BE
CHECKPOINTED ($TSTCP)

CAN OWNER TASK BE CHECKPOINTED

} NO-. 100$

,,-70$:

80$:

DOES THE NEXT SUBPARTITION EXIST

IS THIS SUBPARTITION BUSY?

YES

,.--l

INITIATE CHECKPOINT OF TASK
WHICH OWNS SUE:PARTITION ($1CHKP)

,,-90$:

ANY MORE SIJBPARTITIONS?

100$:

DONE, RETURN TO CALLER

YES

TK-1724

7-41

Data Path

ICCS BIT

FUNCTION

<15>

ERROR

This bit is set if an improper
operation is attempted, for
example
start
the
timer
without clearing the Interrupt
Request (IR) from the previous
Timer overflow.

<7>

Interrupt Request is set when
the Timer overflows.

<6>

Interrupt Enable, This bit
must be set by the VAX 11
macro code to enable Timer
interrupt requests at IPL 18.

<5>

This is a write only bit that
the macro programmer can use
to step the interval clock 1
count at a time. Each write to
the ICCS with bit <5>=1 wi 11
step the interval timer 1
count.

<4>

Transfer
moves
the
contents to the ICR.

<0>

RUN

This bit starts the interval
counter incrementing until it
overflows. This bit would be
set after the transferring the
NICR to the ICR.

NICR

Figure 7-33 shows how the hardware is implemented. The TOK
gate array does not contain all the circuitry, as stated
earlier, to make the timer function. The first register in
Figure 7-33 shows the TOK control bi ts in the high half of
the WBUS bits. The lower 15 bits of the TOK gate array can
be read as either bits <15:0> of the NICR or as <15:0> of
the ICR depending on which is desired. The high half of both
the NICR and ICR are maintained in an RTEMP scratchpad that
is dedicated to the timer. This means that when the lower 16
bits of the !CR are going to overflow, a carry from bit 15
must be added to the contents of the scratchpad that
contains the high half of the ICR. This is accomplished by
forcing a timer service trap at BUT SERVICE to micro-vector
to control store address 0014. At location 0014 is the
micro-service routine that will update the scratchpad
portion of the !CR. The RTEMP scratchpad that contains the
7-42

Data Path

high half of the reR is a single 32 bit location that is
called R[SPNieR.SPieR]. The scratch pad location contains
the high 16 bits of the NieR in bit positions <31:16> and
the high half of the ICR is stored in bits <15:0> of
R[SPNieR.SPICR]. Figure 7-33 shows how this is laid out. The
timer service microcode has to access the scratchpad by·
rotating the contents properly. As you can see the NICR IPR
is scratchpad memory in bi ts <31: 16> and <15: 0> actually
live in the TOK gate array. The same is true about the ICR.
The ICCS shown in the bottom register interfaces to the TOK
gate array bits <31:16>. The MTPR and MFPR instructions have
to rotate the write and read data to the recs 16 bits to the
left. The bits described previously in the recs register are
visible to the WBUS rotated left 16 bit positions. The
following TOK control bits are explained below.
TOK BIT

FUNCTION

VP (WBUS <17>)

This
bit
is
set
by
the
microcode in the interval timer
service
microroutine
to
indicate that the contents of
the SPICR is all ones. This
informs the TOK gate array that
the next reR overflow should
set TIMER INT L.

TR (WBUS <18>)

TR is set in the TOK gate array
after an MTPR initiates a
transfer to the NICR. TR is not
the same as TRANSFER (WBUS
<20>) which is set by the macro
program
to
initiate
the
transfer of the NICR data to
the ICR.

7-43

Data Path

7.4

ICCS BIT

FUNCTION

SR (WBUS <19>)

SR means service request, SR is
set by the TOK gate array to
request service from the timer
service micro routine to update
the
SPi:CR
after
the
ICR
overflows.

TVP (WBUS <24>)

This
bit
is
set
by
the
microcode to tell the TOK gate
array that the SPNICR is equal
to -1. This enables the VP to.
set when a transfer to the ICR
is done and it prevents the ICR
from being auto loaded after
interrupt.

TIMER SERVICE AND INTERRUPTS
The signal TIMER SERVICE H from the TOK gate array is
asserted for two conditions. The first is if SR is set
indicating an overflow from ICR <15:0> and the second
is if TR is set indicating that the previous macro
instruction was an MTPR that set the TRANSFER bit
(WBUS <20>). At the next BUT SERVICE the TIMER SERVICE
request, if honored, will invoke the TIMER SERVICE
microroutine that begins at control store address
0014. This routine has to determine if there is a
SERVICE REQUEST (SR) or TRANSFER REQUEST (TR) and do
the appropriate service. A SERVICE REQUEST (SR) means
the microcode has to increment the SPICR. A TRANSFER
REQUEST (TR) causes the SPNICR to be moved to SPICR.
Once the service request is completed the microroutine
backs up the PC and does IRDl on the VAX-11 macro
instruction preempted by the TIMER SERVICE request.
Timer Inte~rupt requests operate in a similiar
fashion, at BUT SERVICE if any interrupts are pending,
the INT gate array has already completed arbitration
and it will drive the MICRO VECTOR address lines <2:0>
with the highest priority request encoded into a micro
address. The complete microaddress of the Timer
Interrupt service routine is formulated by the SAC,
MSQ, and INT gate arrays. The control store address of

7-44

Data Path

the first microinstruction of the Timer interrupt
service routine is 0038. The microcode would transfer
control of the macro program to the Timer Service
Routine that is pointed to by contents of SCBB+C0.
This routine must clear the IR bit of the ICCS before
using the timer again or an Interval Timer ERROR will
occur.
7.5

TIMER MACRO CODING EXAMPLE
Figure 7-34 is an example macro program that activates
the interval timer. This is a stand alone program and
could not operate under VMS as is. All this routine
does is set up the interval timer with a 10 second
interval. The timer is started and the CPU just waits
for the interrupt that occurs 10 seconds later when
the counter overflows. When the counter overflows, the
interrupt service routine is entered via SCB+C0 where
it just halts the CPU. If C is typed at the console
the program will reload the timer and wait for another
10 seconds until the counter overflows. That all this
program is capable of, but it does show how to load
the timer, start it, and handle the interrupt at
Vector SCBB+C0. Let's analyze it.
Lines 4,5, and 6 are assembler directives that build
the SCB in the low two pages of memory (0 to 3FC). The
value associated with label INTERVAL is the test
interval in microseconds. 10000000 microseconds is the
same as ten seconds. The label ST TIM has the value 51
hex associated with it and this-will be used to set
bit <6> Interrupt Enable, bit <4> Transfer NICR to
ICR, and bit <0> the GO bit that starts the timer
running. Lines 13 to 16 are local symbol definitions
for internal processor registers. At 1 ine 19 is a
directive to allocate 20 longwords\for the stack
space. Line 23 is the beginning of the main program to
get things going. The first instruction sets up the
stack pointer. The next instruction points the SCBB to
address 0 in memory. At line 25 the interval value
defined at line 8 is negated (2's complement) and put
in R0. The address of the service routine (TIM SERV)
is moved into the SCB so that timer interrupt will
vector to relative address 478. At line 27, the NICR

7-45

Data Path

is loaded with the 2's complement of the interval (10
seconds). The instruction at line 28 transfers the
data pattern defined in line 9 to set IE, transfer the
NICR to the !CR, and start the timer. The IPL of the
machine is lowered to 17 to take the timer interrupt
when the timer overflows. The next instruction just
waits for the interrupt.
When the interval timer overflows, the interrupt
request at IPL 18 is generated and if honored, the
macro code resumes at the label called TIM SERV. The
interrupt service routine must clear bit <7> in the
ICCS or when the REI is executed, the IPL 18 interrupt
request is immediately generated again. The HALT
instruction is there to print out the PC at the end of
10 seconds. If the program is continued by typing C at
the console, the timer is restarted with the same
interval. This means that the timer can be reloaded
from the NICR continuously. The primary intent of the
program is to show ~he mechanism by which the timer
establishes intervals of execution time for programs
in a time shared environment. This concludes the
discussion of the interval timer operation.

7-46

Data Path

WBUS
00

24 23 22 21 20 19 18 17 16 15

NICR <15:0>
ICR <15:0>
ERROR
TOK GATE ARRAY
INTERFACE
.
TO CPU WBUS __ '

INTEN
SINGLE CLOCK
TRANSFER
SERVICE REQ
TRANSFER REQ
OVERFLOW PENDING
RUN

ICR
31

1615
SCRATCHPAO ICR R [SPNICR.~ICR] <15:0>

IPR 1A

00
TOK GATE ARRAY ICR <15:0>

NICR
31

ocr

1615
SCRATCHP~O NICR R [SPNICR,SPICR] <31:16>

IPR 19

TOK GATE ARRAY NICR <15:0>

ICCS
15

31
IPR18

07 06 05 04

0
TOK GATE ARRAY <31>

TOK<21>
TOK<20>
TIC-'311

7-47

Data Path

TEST

Pase
27-AUG-tsso 1s:39:20 VAX-11 "aero V02.4S
19-AUG-1980 12:44:02 _DLAO: CPEACOCK lTIPIER .MR; 1

TIPIER
0000
00000000
0000

0000
0000
00000003 0000
0400
00989680 0400
00000051 0404
0408
0408

0408
00000011 0408

00000012 0408
00000018 0408

00000019 0408
0408
0408
00000458 0408

0458
0458
5E

so
FC54 CF

FD AF
11

00
9E AF

00000478 'EF

19
18

92 AF
12 17
FE

00000080 BF
18

81 AF

0458
DE 0458

.TITLE TEST TiftER
.PSECT ALIGN LONG

1
2
3

; Build the SCB

4 scs:
5

.REPT 256
.LOIG 3

6
7

.ENDR

8 INTERVAL:

.LONG 10000000 : 10000000 •icrasecands is 10
; Data to set IE, TRr and GD in ICCS
.LONG 4 XS1

s sr_n":

10
11 ; Local delintions Fer Prosraa.
12
13
SCBB= 4 X11
14
IPl..= 4 X12
15
ICCS= 4 X18
IICR=AX19
16
17
18 ; Stack sPace

.BLKL 20

21 ; Plain Routine
22

CE 045F
DE 0463
DA 046C
DA 046F
DA 0473
11 0476

25
26
27
ZS
29

: Initialize a Stack Pointer
flDVAL START, SP
: Point SC8B ta address 0
tlTPR 10, ISCBB
lfE6I.. INTERVAL, RO
: Nesate the interval ti1e
tlJIJAl. TI"-SERU, SC8+ 4 XCO: Put address aF service in CO
; Load cauat into NICR
flTPR RO, INICR
; Stt IE, TR, and start ti1er
flTPR ST_TI"' IICCS
; Lawer IPL ta take interruPt
"TPR fAX17r #IPL

30 HERE:

BR8 HERE

0478

0478
0478

32 ; Ti1er Service Routine

0478

34
35 Till.SERV:

.ALIGN LONG
"TPR 1•xao, IICCS

36
37
38
39

HALT

DA 045C

DA 0478
00 047F
DA 0480

02 0484
0485

23 START:
24

"TPR ST_Tift, fICCS

; Clear Ti1er IR •eFore REI
; TYPe •c• at console to go
; Restart ti1er with sa1e count

REI

; REI back to BRB HERE

.END START

7-48

1
(1)

VAX-11/750 LEVEL II

Remote Diagnostics

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Remote Diagnostics

INTRODUCTION
The RDM was placed at this section of the course to allow
the student to understand its use in the overall system.
That use is: the RDM is a TOOL to be used by the technician
to maintain the equipment. The ROM is NOT needed by the
customer to operate the system. Due to this fact the
maintenance philosophy is: THE ROM IS A FIELD REPLACABLE
UNIT AND WILL NOT BE REPAIRED. This makes sense if you say
to yourself; "Self I can't take up the customer's system
time fixing my repair equipment."
What you should obtain, from this lesson and following
lessons, is the confidence in the use of the ROM and the
many functions available to you when using the RDM. These
functions will be mentioned in this lesson but not all will
be reinforced with labs directly after the lesson. The
different uses will be spread out to allow you the chance to
apply these uses in actual troubleshooting situations as
they arise in the course.
There are two levels of maintenance involved with the use of
the RDM.
1.

By the branch or support person on site to fix -a
problem by running Micro Diagnostics (TO RUN MICROS
YOU HAVE TO HAVE AN ROM) or by taking an instruction
through a complete cycle one micro instruction at a
time. (AGAIN YOU NEED THE RDM TO SINGLE STEP
MICROINSTRUCTIONS.)

The same functions may be used remotely by the DOC
in Colorado to help the branch or support person
perform fault isolation or preventive maintenance.

THESE ARE NOT ALL THE FUNCTIONS OF THE ROM. They do show
that it is needed to perform onsite maintenance as well as
remote diagnosis.

6-3

Remote Diagnostics

OBJECTIVES
At the completion of this lesson the student will be able to
distinguish between the two basic modes of operation
available using the RDM.
The student will be able to match the blocks in a
block diagrams to its function.

bl~nk

RDM

The student will be able to match the RDM commands to their
related function in running micro-diagnostics while
troubleshooting the machine.

SAMPLE TEST ITEM
Match the function in the right column to the command in the
left column by placing the proper letters in the space
beside the command.
EXAMINE
DEPOSIT
RET
"p

A. Enter RDM mode
B. Place data into a location
C. Read data from a location
D. Return to previous mode

RESOURCES
11/750 RDM Maintenance Card
11/750 Option Technical Manual

Guide

6-4

and

Mic rod iagnostic User's

Remote Diagnostics

OUTLINE
VI.

Remote Diagnostic Module
A. Reasons for RDM
B. Physical Characteristics
1.
2.
3.

Location
Power
Front Panel Indicators

C. Operational Overview
D. Block Diagram
E. Addressing
F. Pseudo Instructions

6-5

KA760 ,_
UNDER
TEST
CON

t'J,J

......

'°c

DOC
ENGINEER.
TERMINAL

•

""'CD

I
°'
.......

:x:t

:3:

°'I
°'

t'J,J

::s
0

rt
......
0

:TU-58
\TAPE
!DRIVE

!HOST
1
SYSTEM

KC750
SUBSYSTEM
'C N
MOD

::s
OJ

.......

0
0

......
0

::s

CONSOLE
TERMINAL
'LAXX
VTXX

-vA:l5ic
OR
1GTE
'.MODEM

CUSTOMER SITE

PHONE LINE

ERIAL
LINE
INTERFACE

·MODEM

:x:t
CD

'DOC

t1
......
OJ
TK ... 662

'°::s
0

en
rt
......
0

Remote Diagnostics

Physical Characteristics
l.

Located in slot 6 of extended hex backplane as noted in
introduction.

Power

a. MAX
TYP
3.

+5V @ 12.0A
+SV @ 9.3A

+12V @ 120MA
+12V @ 60MA

-lSV @ 85MA
-15V @ 30MA

Control Panel Interconnections
.Connections to the control panel will be incorporated in
the basic cabinet and its wire harness. The processor
will have full use of all processor specific controls
and indicators whether the RDM is installed or not. When
the RDM is installed in its slot the RD specific
functions will also be operational. The RD functions
implemented on the control panel are as follows:
a. INDICATORS
1. REMOTE
This green light is lit by the RDM
software whenever it detects that the ~ontrol
panel key switch is in one of the two remote
positions.
2. CARRIER
This amber light is lit by the RD
software whenever it detects that the remote port
carrier is present. It is an indicator to the
customer that the DDC has established connection.
3. TEST - This green light is lit by the DDC software
to indicate that tests are in progress.
4. FAULT - This red light is lit by the RDM software
if it detects a fault in its own logic. No tests
should be attempted when the fault indicator is
lit.
b. SWITCH SETTINGS
The processer' s keyswi tch has 5 positions, two of
which allow remote connection. The REMOTE and REMOTE
SECURE positions allow the DDC to connect to the
processor. The REMOTE position allows the control
console to enter console mode at any time while the
REMOTE SECURE prevents the console from being used in
other than program mode.

6-7

Remote Diagnostics

1. There are also switch settings that relate to the
remote BAUD rate but those will be covered in the
installation section in the final week.

6-8

Remote Diagnostics

"""

CMI

COMET CPU WBUS

SWMET r -

CPU
CONCHIPi.--

TU58
TAPE
DRIVE

I----.
~

1
t-UART

UART

......

A
REG

H
REG

32BIT

14--

D
REG
3281T

...__

1--

8085 INTERNAL BUS

......

SIMPLIFIED RD BLOCK DIAGRAM

1---'
LOCAL
!TERMINAL I---

I-'
UART

r--

,.....

4K
RAM

.,___...
lo---

8085
NCPU

f..,--.
PHONE

i.--

MODEM

~ REMOTE i---.
i.--!--- LINE

UART

I-'

i.-

...._ ,.....

6K
PROM

1---

SERIAL INTERFACES

I
CONTROL
~ REGS

TRACE
<SADD
MATCH

64 X 80 BIT
DCS RAM

i.L.--.

ADDA
DECODE
LOGIC

ENABLES

i-.

MMATCH

A
CONTROL STORE DATA

..._.

CON STORE ADDRESS

....
TK-4561

Figure 6-2

Simplified ROM Block Diagram

6-9

Remote Diagnostics

0000

6KB
ERASABLE
PROM
MACROCODE;
~QftAG_E__J

17FE/

UNUSED

8000
13KB
MICRODIAGNOSTIC
MONITOR
STORAGE
f 800
f 830

UNUS_ED
INTERFACE
REGISTERS

FFFF
UNUSED

Figure 6-3

8085 I/O Addressing

6-10

Remote Diagnostics

\. -

"-._-~---'
'"~-~-_,J
'Y
T'

~-Ncoo·eo· KEv--

iENCOlDPOWER LjENci:>l>EOOEViCE

sw1TcH POSITION

(ON ACTION
:SWITCH POSITION

- -- =--------

OFF
·----_SECURE
;;T1
LOCAL
=10REMOTE/SECURE;= Qt
REMOTE
!=00

/oo = RES/8-b6T
01 = RES/HALT
,10= BOOT
11 =HALT

:SWITCH POSITION

:A=1f
B= 10
C=01
0=00
i TK-'558

Figure 6-4

Front Panel Status Register F820

6-11

Remote Diagnostics

Remote D

Red

This
indicates
that
the
keyswi tch is in either of the
remote positions.

RD Test

Green

This indicator is illuminated
if a remote diagnostic session
in protocol mode is in progress.
The transparent mode
turns the lamp off.

Carrier

Amber

Carrier indicator is on if the
modem is receiving the carrier
from the telephone line.

RD Fault

Red

Indicates a hardware fault on
RDM module if constantly on.
Normal sequence is to illuminate for 10 seconds at power
up and then go out. If lamp is
always one, replace RDM.

Figure 6-5

RDM Operator Control Panel Indicators

6-12

VAX-11/750 LEVEL II

CMI

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

CM!

INTRODUCTION
The CMI is a tristate synchronized inforamtion path for
data exchanges between the central processing cluster
(CP Cluster), memory, and adapters of the Comet system.

8-1

CMI

SYNOPSIS
The CPU Memory Interconnect module includes lecture
on the architecture and types of data transfers
used.

OBJECTIVES
Provided with a multiple choice test, correctly
answer questions regarding CMI architecture and
types of transfers.

SAMPLE TEST ITEM
Which of the following best describe the CMI?
a)
b)
c)
d)

55 lines of equal length forming a 2 layer
belt
80 lines of various lengths formed by etch
55 lines etched into the backplane, all
equal length
45 etched lines of various length

RESOURCES
Comet Specification

8-2

CMI

MODULE OUTLINE
VIII.

CPU MEMORY INTERCONNECT (CMI)
A.

CMI Structure
1.
2.
3.

CMI protocol
CMI status bits
CMI control signals
Data/Address
Clock

Address/Data Transfers
1.

Address format
ae

function code
mask field

Summary

8-3

CMI

32 DATA/ADDR.

1 WAIT
DATA/kooRESS (35)

1 HOLD
1 BUSY

3MBA
1 UBI

ARBITRATION (7)

1 ROM

2 RESERVED

NEXUS

STATUS (2)

6.25 MHZ B CLOCK ( 1)

THE CMI STRUCTURE
TK-2064

Figure 8-1

CM! Structure

8-4

CMI

---·-·--··-

ITEM

PRIORITY

.ROM ----·---

7
6
5
4

RESERVED
RESERVED
CUI
OPTION

;

OPTION~

_OPTION L._,

·---~NONE

CPU

CMI PROTOCOL

Figure 8-2

ST1 STO

CMI Protocol

.INTERPRETATION
NON EXISTENT MEMORY
-----------~---

NON CORRECTABLE ERROR

--------------~

- - CORRECTED
-NO-ERRORS
- - DATA
-- -- ._

--~

THE CMI STATUS BITS
TK-2062

Figure 8-3

CMI Status Bits

8-5

CM!

DATA/ADDRESS BUS BUSY
THE DATA/ADDRESS BUS BUSY (DBBZ) SIGNAL INDICATES THE
AVAILABILITY OF THE DATA/ADDRESS BUS.
THE ABSENCE OF DBBZ
INDICATES TO ALL NEXUS THAT THE DATA/ADDRESS BUS WILL BE
FREE AT THE BEGINNING OF THE NEXT CMI CYCLE.
DBBZ
DBBZ IS ASSERTED BY THE BUS MASTER FOR ONE CMI CYCLE WHEN AN
ADDRESS FORMAT IS PLAC&D ON THE DATA/ADDRESS BUS. DURING A
READ, THE SLAVE ALSO ASSERTS DBBZ IN THE FOLLOWING CYCLE AND
CONTINUES TO ASSERT IT UNTIL THE READ DATA IS READY FOR
TRANSMISSION. DURING A WRITE, DBBZ IS ASSERTED BY THE SLAVE
WHILE IT PREPARES TO ACCEPT THE WRITE DATA.
FOR THIS CASE,
DBBZ IS NOT ASSERTED IF THE NEXUS IS IMMEDIATELY READY.
BOLD
THE HOLD SIGNAL ·CAN BE ASSERTED BY ANY NEXUS TO PREVENT
OTHER NEXUS FROM GAINING CONTROL OF THE DATA/ADDRESS BUS.
THE HOLD SIGNAL IS PRIMARILY PROVIDED TO ALLOW BUS WATCHING
CACHES TO CONTROL THE RATE AT WHICH WRITE TRANSACTIONS OCCUR
ON THE CMI.
WHILE HOLD IS ASSERTED, ALL BUS REQUESTS ARE
IGNORED.
WAIT
THE WAIT SIGNAL IS ASSERTED BY A NEXUS WHEN IT INITIATES AN
INTERRUPT TRANSACTION.
THE ASSERTION OF WAIT IS AN
INDICATION TO THE CPU THAT AN INTERRUPT TRANSACTION IS IN
PROGRESS ON THE UNIBUS AND THAT A WRITE VECTOR OPERATION MAY
BE PENDING.
WAIT IS REMOVED AT THE BEGINNING OF THE CM!
CYCLE FOLLOWING THE COMPLETION OF THE INTERRUPT TRANSACTION.
THE REMOVAL OF WAIT ALLOWS THE CPU TO CONTINUE NORMAL
OPERATION.

8-6

CM!

31
MASK

PHYSICAL LONG WORD ADDRESS

FUNC.

31
DATA

THE ADDRESS TRANSFER FORMAT IS USED TO TRANSFER ADDRESS AND
CONTROL INFORMATION DURING THE BUS CYCLE IMMEDIATELY FOLLOWING
A successFUL ARBITRATION CYCLE.
THE DATA TRANSFER FORMAT IS USED TO TRANSFER 32-BITS OF DATA (1
LONGWORD). IF THE TRANSACTION IS A WRITE, THE BUS MASTER USES THIS
FORMAT TO TRANSMIT WAITE DATA IN THE BUS CYCLE IMMEDIATELY
FOLLOWING THE TRANSMISSION OF THE ADDRESS FORMAT. IF THE
TRANSACTION IS A READ, THE SLAVE USES THIS FORMAT TO RETURN READ
DATA TO THE BUS MASTER.
CMI DATA/ADDRESS FORMATS
TK-2069

Figure 8-4

CMI Data/Address Formats

8-7

CMI

2827

2 1 0

252423

MASK

PHYSICAL LONG WORD ADDRESS

FUNCTION CODES
DATA/ADDRESS BIT

CMI

OPERATION

READ

READ LOCK

READ WITH MODIFY INTENT

(UNDEFINED)

WRITE

WRITE UNLOCK

..I

WRITE VECTOR

(UNDEFINED)
CMI FUNCTION CODES
TK-2073

Figure 8-5

CMI Function Codes

8-8

CMI

MASK FIEJ..D

31·

2827

MASK.

252423

FUNC

D<l

2 1 0
PHYSICAL LONG WORD ADDRESS

3 2 1 0

2423

8 7

1615
1

EACH BIT IN THE MASK FIELD CORRESPONDS TO A "PARTICULAR BYTE IN
SUBSEQUENTLY TRANSFERRED DATA FORMAT. THESE BITS SPECIFY
WHfCH OF THE CORRESPONDING DATA BYTES ARE TO BE READ OR
_ WRITTEN. THE BYTE IS SELECTED WHEN THE MASK BIT IS SET.
NEXUS WHICH ARE CAPABLE OF TRANSFERRING LONGWORDS IGNORE THE MASK
ON READS ANO ALWAYS RETURN ALL FOUR BYTES (E.G., MEMORY).
TIC.·20.1

Figure 8-6

8-9

Mask Field

CMIWRITE

CMIREAD
160nSEC

r-"'-l
t'1j

......
'°c::
<D
"""

(X)

PRIORITY
(ARBNI

DBDZ
(ASSERTED LO)

I
~

::0

<D
DJ

a,
........
~

......
"""

STATUS
(ASSERTED BY
SLAVE AT END
OF TRANSA TION)
.~DD RESS

(ASSERTED FOR
1 CYCLE)

t-3
.....
3

DATA
(ASSERTED FOR
1 CYCLE)

.....

~
I
I
I
I

I
I
I

I
I

'°

I
.....i

1-J

CMICLK
(BCLK L)

(X)

CMICYCLE

BOOnSEC

()

3
H

VAX-11/750 LEVEL II

Address Translation

Student Guide

Course Produced by Educational Services Department
of
Digital Equipment Corporation

Address Translation

OBJECTIVES
1.

To u t i 1 i z e prov id e d wo r ks he e ts i n o rd e r to
perform address translations from a system
virtual address to a physical address and from a
processor virtual address to a physical address.

To utilize the console terminal and be able to
determine what type of error occurred during an
address translation by using the stack.

To correctly indicate on a series of true/false
questions, statements regarding the 11/750
address translation procedures.

To run and interpret MIC Module Microdiagnostics
that relate to address translation.

SAMPLE TEST ITEM
True or False
l.

Bit 31 in the system virtual address denotes which page table is accessed.

LAB EXERCISE
a.

Load and run microdiagnostics

Run RDM to step through Translation Buffer
Double T.B. miss.

RESOURCES
1.

11/750 Micro Listings

11/750 Microdiagnostics and
Module

MIC Module Schematics

Student Guide

9-1

Listin~~_!£~~~C

Address Translation

INTRODUCTION
When we talk about address translation we actually mean to
take a virtual address (system or processor) and translate
it to a physical address.
To understand the concept you will have to understand
virtual address space in relation to physical address space
and how the system uses the translation to control access to
certain areas in the machine.
You will learn the actual machine translation from a virtual
address to a physical address and the controlling factors in
performing this translation.

9-2

Address Translation

VIRTUAL MEMO AV

VIRTUAL ADDRESS

ALLOcATION
00.000.000
PROGRAM REGION
{POI
3FFFFFFF

40.000.000

CONTROL REGION

III

?!-lOCESS

SPACE

··~

1?1)
7F,FFF,FF!=

so.coo.coo
SYSTEM REGION
(SQ}·

BF,FFF,FFF
60.000.000

30 29

9 8
VIRTUAL PAGE NUMBER

lsYTE OFFSET

When bit 31 is clear. the virtuai address is a pr~
virtua "ddress .found in process soace or "per-process"
space. Each process has its own process space and it is
practically impossible fot one process to ref!r to a process
virtual address of anorher process.
Both process space and system space are further divided
into two pjeces determined by the setting of bit 30 in the
virtual address.

I
I
?
I

1. VA<:31:JO>:r 0 Program Region

SYSTEM

SPACE

This portion of virtuai address space is cailed PO space
or the program region. PO space typically contains the
cede and data of an image being executed by the process.

2. VA<:l 1:30>,. 1 Controt Region.

·RESERVED REGION
(Sl)

FF,FFF,FFF

This portion of virtual address ~pace is called P1 space
or the central region. It contains sucn information as
the four per-process stacks, a Command Language
lnterpP-ter, DEBUG symboi table, process 1/0 data and so
on.

3. VA<3t:30> • 2 System Region

This portion of virtual address space is called me
system 1"e1;ion. It contains the executive, device
drivers anci th9ir auociateci data structUres, RMS code
and Pore data, both the system and process page tables
and o~er code and dau that does not belong to any Ont'!
process in the system.

4. VA<31:30>• 3 Reserved
This portion of virtual address space is currently
reserved • ..A-rfierence to a virtual address inthis

~ will c:aUse a length violation.
TK-3413

Figure 9-1

Virtual Memory

9-3

PHYSICAL MEMORY

23 22 2] 20 19 18 17 16 16 14 13 12 11 19

PHYSICAL ADDRESS

.......
'""I

040000

"°I
..i:::..

"°r-..>I

07FFF Fi

'"O

OBFFF F

::r
'<
Ul

OJ
I-'

140000

'""I

17FFF F

258K

180000

1BFFF F

266K

1COOOO

1FFFF F

~
\
\ ..
\
\

>t: :.

1FC

\
\
\

1FD

\
\

1FE

\
\
\
\

\
256K

\
\
268K

002

100000

003

256K

13FFF F

256K

OFF FF F

001

BYTE
•ADD
0

ocoooo

()(X);

256K

080000

.......
()

I
......

-I

PAGE

256K

03FFF F

l)<r><l

BYfE

MAXIMUM PHYSICAL MEMORY
000000

l.Q

PFN

l'%j

II IIIIIIIII IIIIIII)I II~

1FF

.... '¢ ..

1FO

0..
0..
'""I

1F4

\
\
\
\

1FB

Ul
Ul
~

'""I

:::l

·1FC

Ul
I-'

•NOTE FOR ADDRESS BYTE BITS 0 + 1 NOT USED.
TK-3411

rt
.......
0
:::l

Address Translation

PAGE CONCEPT

-------···------WHICH ROOM DO I GO TO TO RECEIVE TRAINING?
----·
.

YOU NEED DIRECTIONS
-GO TO SCHOOL #3,

ROOM 5.

iffi

6 :~

•••

PAGE 1

PAGE

T.1

I
I

BYTE OFFSET #:. 1

BYTE OFFSET

MEMORY

H
0

•··--·M·--- -•

PAGE NUMBER

if1-SCH00L

#11{) : {)#i
#;o~

---

WHERE DO I GO TO GET MY DATA?
YOU NEED AN ADDRESS.
ADDRESS

#96 {)#4
#S(J ~trs
I
#7() ~#6

---•·

· - · - - - --·•w-••·•·---

SCHOOL ROOM
BREAKDOWN

WHICH SCHOOL •WHICH PAGE
WHICH ROOM IN THAT SCHOOL• WHICH BYTE IN THAT PAGE
TK-3412

Figure 9-3· Page Concept

9-5

Address Translation

PAGE BREAKDOWN
BYTE

1 2 T1 T 0
BYTE

BYTE

LONGWORDO
LONGWORD4

c
13

I I ,, I

PAGE#

18
1C

l T l
22

EACH PAGE OF MEMORY CONSISTS OF 1FF (HEX) BYTES.
IN ntE t
MEMORY is LONGWORD ALIGNEO, MEANING
YOU READ FROM MEMORY ONE LONGWORD AT A TIME.

tnso

EACH LONGWORD CONTAINS 4 BYTES.

1cF

1ce }

1co

IF WE START AT ADDRESS 000000 ANO
INCREMENT UPWARDS AT LONGWORD BOUNDARIES
we COULD ACCESS 1FF BYTES WITHIN PAGE 0
OF THE ADDRESS BEFORE CH.A.NGING TO PAG; 1 BYTE 0.
IN THE NEXT INCREMENTED STEP.
1cc

TCC
100

104

108
tOF

I T l
JOE

100

iOC

iFO
~F4

1F8
1FF

1FE

T T
1FO

1FC

1FC
il(-3410

Figure 9-4

Page Breakdown

9-6

Address Translation

PTE FORMAT

3130

H IM'
PROT

1514

27 26 25

PROTECTION
CODE

0
PFN

MBZ
~

MUST BE ZERO'S

PAGE FRAME NUMBER

PAGE MODIFIED
PAGE VALID
TK-1880

Page Tables and Mapping Registers
Figure 9-5

Page Table Entries

The system page table is built at initialization time and is
located in contiguous pages of physical memory • . Process
page tables are set up at process creation and altered at
image activation, image exit and in response to various
system services.
Process page tables are located in
virtually contiguous pages of system space.
That is,
process page tables need not be physically contiguous. This
design feature prevents a potentially serious fragmentation
problem in physical memory.

9-7

Address Translation

System Page Table
(SPT)

Describes the physical
location and status of
all pages in the system
region of virtual
address space.

System Base
Register (SBR)

Points to the starting
physical location of the
System Page Table.

IPR # 0C

System Length
Reg is t er ( S LR )

Specifies the number of
entries in the System Page
Table

IPR # 0D

0 Page Table
(P0PT)

Describes the physical
location and status of all
pages in the program region
of virtual address space.

P0 Base Register
(P 0BR)

Contains the system
virtual address of the
P0 page table.

IPR # 08

P0 Length Register
(P0LR)

Specifies the number of
entries in the P0 page
table.

IPR # 09

1 Page Table

Describes the physical
location and status of
all pages in the control
region of virtual address
space.

(P lPT)

Pl Base Register
(P lBR)

Contains the system
virtual address of the
Pl page table.

IPR # 0A

Pl Length Register
(P lLR)

Specifies the number of
entries in the nonexistent portion of the
Pl page table.

IPR # 0B

9-8

Address Translation
PHYSICAL MEMORY

P1PTE'S,
PO OPERANDS

---

POPTE'S

P1 OPERANDS

SYSTEM-OPERANos

....

HtT

MISS

sYSTEM -PTE'S

. - PA

.,.-----SBR + sVA ..__

SBR+SVA
--------

CPOSR+PVA~
(SVA)
..

POPTE

!-i-SVA

~ PVA

.. PA

P1PTE

SBR+SVA

P18R+PVA .,_..,
(SVA)

~ PVA

T K-328!5

Figure 9-6

Address Translation Block Concept

9-9

Address Translation

ADDRESS TRANSLATION
EXAMINE VIRTUAL
ADDRESS

FORM SYSTEM
VIRTUAL ADDRESS
OF PxPTE
YES

YES ("HIT")

FORM PA OF SPTE

FETCH SPTE

FORM PA OF PxPTE

FETCH PxPTE

FORM PA OF
OPERAND

TK-3426

Figure 9-7

Address Translation

9-10

Address Translation

PTE FORMAT

3130

1514

27 26 25

PFN

MBZ

...

PROTECTION
CODE
.

.....

,...
'
PAGE FRAME NUMBER

MUST BE ZERO'S

- - - - P A G E MODIFIED

- - - - - - - - - P A G E VALID
TK-1880

Page Tables and Mapp{ng Registers
Figure 9-8

Page Table Entries

The system page table is built at initialization time and is
located in contiguous pages of physical memory.
Process
page tables are set up at process creation and altered at
image activation, image exit and in response to various
system services.
Process page tables are lcoated in
virtually contiguous pages of system space.
That is,
process page tables need not be physically contiguous. This
design feature prevents a potentially serious fragmentation
problem in physical memory.

9-11

Address Translation

SYSTEM CONTROL BLOCK
SCBB
(PHYSICAL)

EXESACVIOLAT

OFFSET2018

(ACCESS VIOLATION- FAULT)
-··- -··---·--- - MMGSPAGEFAULT

OFFSET24 18

(TRANSLATION NOT VALID FAULT)

TK-4M&O

Memory Management Exceptions
Figure 9-9
During address translation,
exception
can
occur:
translation-not-valid

exception.

two di fferrent kinds of
access
violation
and
Both

forms

exception

are faults.
That is, the processor backs up the faulting
instruction so that it can be restarted when {or if) the
exception is resolved. Two adjacent longwords in the system
control block are set up at initialization time to point to
the routines which will service these exceptions.
Both
exceptions are handled on the Kernel stack.

9-12

Address Translation

Management Management Exceptions
Access Violation
An access violation can occur in two different forms.
A
protection code violation occurs when the intended access
request (read, modify, write) is not allowed for the current
access mode.
Recall that the protection code is found in
bits <30:27> of the appropriate page table entry.
A length violation. occurs when the virtual page number of
the address to be translated is greater than or equal to the
contents of the appropriate length register.
(Because Pl
space grows toward smaller addresses, th length violation
fault occurs when VA<29:9> is strictly less than the
contents of PlLR.
When an access violation occurs, the faulting PSL and PC are
pushed onto the kernel stack, followed by the virtual
address which caused the access violation.
Finally, a
longword fully describing the access violation is pushed
onto the stack.
Note that bit <0> of the reason mask
distinguishes length violations from protection code
violations.

9-13

Address Translation

PROTECTION
CODE IN
PTE

CURRENT ACCESS MODE
KERNEL

EXECUTIVE

SUPERVISOR

USER

0000
0001
0010
0011

RW
R

---

0100
0101
0110
0111

RW
RW
RW
R

RW
RW
R
R

1000
1001
1010
1011
1100
1101
1110
1111

RW
RW
RW
R

RW
RW
R
R

RW
R
R
R

RW
RW
RW.

RW
AW
R
R

RW
R
R
R

R
RW

UNPREDICTABLE

---

-------

R
R
R
R

. (NO ACCESS)
(READ-ONLY ACCESS)
(READ AND WRITE ACCESS)
TK-3567

Figure 9-10

Use of Protection Codes for Access Control

9-14

Address Translation

Memory Management Exceptions
Access Violations

1i'

REASON MASK

f',

INVALID VIRTUAL ADDRESS
PC OF FAULTING INSTRUCTION

REASON rMSK FOR TRANSLATION

PSL AT TIME OF FAULT

,..

-NOT-VALID FAULT

THIS BIT tS ALWAVS 0 FOR TRANSLATION

- NOT - VALID FAULTS

STATE OF THE KERNEL STACK FOLLOWING
...
A TRANSLATION -NOT - VALID FAULT

..__...~PTE

REFERENCE
0 -..y1RTUAL ADDRESS NOT VALID .
-·
t-.ASSOCIATED PTE NOT VALID

-----INTENDED ACCESS TYPE
0 -+READ ACCESS
1 -+MODIFY OR WRITE ACCESS
TK~8

Figure 9-11

State of Kernel Stack Following Access
Violation Fault

9-15

Address Translation

Memory Management Exception
Translation-Not-Valid Fault
A Translation-Not-Valid fault occurs when the Valid Bit
(VA<31>) is clear. The faulting PSL and PC, followed by the
invalid virtual address and reason mask, are pushed onto the
kernel stack.
Control is passed to an executive routine
called the pager, which will use the information in the
invalid PTE to locate the page and add it to the working set
of the requesting process.
(The information contained in an
invalid PTE and the actions taken by the pager will be
discussed in the next module.)
Since process page tables are mapped (by SPT entries),
address translation for process virtual addresses can incur
page faults both in translating the system virtual address
of the process page table entry and in translating the
process virtual address itself.
These two different cases
are distinguished by bit <l> of the reason mask.

9-16

Address Translation

Memory Management Exceptions
Translation Not Valid Fault

PC OF FAULTING INSTRUCTION,
PSL AT TIME OF ~ULT
TYPE__OF ACCESS VIOLATION·
.
0 ~ PTE PROTECTION CODE VIOLATIO~_l

.....

STATE OF THE KERNEL STACK FOLLOWING AN ACCESS VIOLATION FAULT
..__~

PTE REFERENCE

o.... VIRTUAL ADDRESS NOT ACCESSIB~E I
1-.~ATED PTE NOT ACCESSJBLE-!

INTENDED ACCESS TYPE,
o-. READ ACCESS
1 _. MODIFY OR WRITE ACCESS

Figure 9-12 State of Kernel Stack Following
a Translation Not Valid Fault

9-17

Address Translation

NOTE

The address translation mechanism checks
the protection code before it checks the
valid bit.
Thus, if a given address
translation could cause both an access
violation and a page fault, the access
violation will be taken.
This design
avoids the· overhead of faulting into a
process working set a page which it is
not allowed to access.
A further
discussion is found on page HJ8 of the
VAX-11/780 Hardware Handbook.

9-18

Address Translation
EXAMINE VIRT~Ai...
AD~RESS IVAl

FORMSYSTfM
VIRTUAL ADDRESS

OF FxPTE

LENGTH
VIOLATION

FETCHSPTE
FROM MEMORY

ACCESS
VIOLATION

YES

I
I
ACCESS

VIOLATION

TRANSLATION
NOTVAL:D
ACCESS
VIOLATION
FORM PHl'SICAi.
ADDRESS OF
OPERAND

.
I

(!RANSLATION' \
'DONE

)
Tl(-3425

Figure 9-13

Address Translation Faults

9-19

Address Translation

MEMORY MANAGEMENT WORKSHEET FOR SO

3130 29 28 2726 25 24 23 22 212019 18 171615 14 13 12 It 10 0908 07'06 05 0403 02 01 00
SYSTEM VA (SVA)

I I I I I -, I I I 1 I I I I I I I I I I I I I I I I I I I I I I I
~

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
4 x

SVP~ I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I0 I0 I
31 30 29 28 27 2G 2524 23 22 21 20 19 18 17 16 15 14 1312 1110 09 08 07 06 0504 03 020100
SBA

·I I I I I I I I I I I I I I I I I I I I I ' I I I I I I I I I I I
23 22 21 20 19 18 17 1615,14 13 12 11 10 0908 07 06 05 04 03 02 01 00

PHYSICAL ADDRESS OF SPTE

I I I I I I I l (I I I I I I I ' I I I I I III

SBR + 4 (SVPNI

31 30 29 28 27 2G 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 OG 05 04 ·03 02 01 00

I I I I I I I I I I I I I I I I I I I I I I I I t I I I I I 1°1°1 *
31 30 29 28 27 2G 25 24 23 22 21 20 19 18 17 lG 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

I I I I I I I I I I I I I I I i I I I I I I I I I I I I I I I 11 *
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

11 I I I I 111 I I I I I I I I I I I I I 11 I· I I I I I 111*
31 30 29 28 'l.7 2G 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 '03 02 0100

SYSTEM PTE

I I I I I I I I I I I I I I I I I I I I I l I I I I I I I I I II
~

CONTENTS OF PA FOR SPTE

23 22 2120 1918 17 16 1~ 14 13 12 1110 09 OS 07 06 05 04 03 0201 00
PA OF SPTE OPERAND

1 1 1 1 1 1 1 1 1· 1

rT r 1 1 1 1 1 1 1 1 1 1 1 1
L

CONCATENATED ___)
......,

rr- FROM SVA

31 30 29 28 27 26 2524 23 22 21 20 19 18 17 1615 14 13 12 11 10 0908 07 06 05 04 03 02 01 00

I I I I I I 11 I I I I I I I I I I I I I 11 I I I I I I 111~

*NOT REQUIRED IN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 OS 07 06 05 04 03 02 01 00

SO CALCULATION

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I*
TK·4G13

Figure 9-14

Memory Management Worksheet for 80

9-20

Address Translation

MEMORY MANAGEMENT WORKSHEET FOR SO

3130 29 28 2726 25 24 23 22 212019 18 171615 14 13 12 11 10 0908 07'06 05 04 03 02 01 00

SYSTEM VA (SVA)

I I I I I I I ! I I I I I I I I I I I I I I f I I I I I I I I II

1·

·I

SVPN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

4 x SVPN

I IIIIIII l IIIIIIII I I II I I' I ' II IIIlI
0 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 OS 07 06 05 04 03 02 Ot 00

SBR·I

I I I I I III I I I I I I I I I I I I I I I I I I I I I III
.. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

I I I I l I I I I I I I I I I l I I I I I I I I ssR + 4 1svPNI

PHYSICAL ADDRESS OF sPTel

31 30 29 28 27 2G 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 OG 05 04 ·03 02 01 00

I I I I I I I I I I I I I l I I I I I I I I I I I I I I I I 1°1°1 *
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 lG 15 14 13 12 11 10 09 08 07 OG 05 04 03 02 01 00

I I I I I I I I I I I I I I I I I I I I I \ I I I I I I I I I 11*
31 30 29 28 27 26 2524 23 22 21 20 19 18 17 1615 14 13 12 11 10 0908 07 06 05 04 03 02 01 00

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 11 *
31 30 29 28 27 2G 2524 23 22 21 2019 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04°03 02 0100

SYSTEM PTE

I I t I I I I I I I I I I I I ) I I I I I I I I I I I I I ' )II

CONTENTS OF PA FOR SPTE

PFN

23 22 21 20 19 18 17 16 tS 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

PA OF SPTE OPERAND f

III IIIII I IIII III III IIIII
L

CONCATENATED__)
r-FROMSVA
I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

I I I I I I i 11 I I I I I I I I I I I I I I I \ I I I I I 111$
* NOT REQUIRED IN
SO CALCULATION

3130292827262524232221201918171615 14 1312 1110 09080706050403020100

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I~TK-4513

Figure 9-15

Memory Management Worksheet for 80

9-21

Address Translation

MEMORY MANAGEMENT WORKSHEET FOR SO

3130 29 28 2726 2524 23 22212019 18 171615 14 13 12 1110 0908 07 06 05 0403 02 01 00
SYSTEM vA

csvAd I I I I I I ! l I I I I I I l I I I I I I I I I I I I I I I I I

SVPN

•

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
4 x SVPN

I IIII II II III IIIII I I II I III III IIIII
0 0

31 30 29 28 27 26 2524 23 22 21 20 19 18 17 16 1514 13 12 11 10 09 OS 07 06 0504 03 020100

SBR'.I

I I I I I I I .1 I I I I I I I I I I I I I I I I I I I I I I I I
. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

PHYSICAL ADDRESS OF SPTE

I I I I I I I I I I I I I I I I I I I I I I III

SBA + 4 (SVPN)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 M 13 12 11 10 09 08 07 06 05 04 ·03 02 0100

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I0 1°1 *
31 30 29 28 27 26 2524 23 22 21 20 19 18 17 1G 1514 13 12 11100908 07 06 0~04 03 020100

I I I I I I I I I I I I I I I I I I I I I \ I I I I I I I I I 11 *
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I*
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 '03 02 01 00

SYSTEM PTE

I I I I I I I I I I I I I I I I I I I I I l I I I I I I I I I II

CONTENTS OF PA FOR SPTE

23 22 2120 1918 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 0201 00

PA OF SPTE OPERAND

I III I I I' I I I II I II I II I IIIII
L

CONCATENATED__)

~FROMSVA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0908 07 06 05 04 03 02 01 00

I I I I I I I 11 I I I I I I I I I I I I I I I I I I I I I 111*
* NOT REQUIRED IN

313029 28 27 26 25 24 23 22 212019 18 17 16 15 14 13 12 11 10 09 08 07 00 05 04 03 02 01 00

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I*

SO CALCULATION

TK-4513

Figure 9-16

Memory Management Worksheet for 80

9-22

Address Translation

MEMORY MANAGEMENT WORKSHEET FOR PO, P1

3130 29 28 2726 25 24 23 22 212019 18 1716h5 14 13 12 11 10 0908 07!06 05 04 03 02 01 00

PO, P1 VIRTUAL ADDRESS

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II
,.

•I

SVPN

31302Q2s 2126 2s 24 23 22 2120 191s 111s ts 14 13 12 11 10 09 os 0106 os 04 oJ 0201 oo

4 x svPN

l IIl IIIIIIf IIIIII IIII IIIIIIIl H

POBR OR Pl BR

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II

31 30 29 28 27 26 252423 22 21 201913 17 161514 1312 1110 09 0807 06 0504 03 020100

31302928 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

POBR OR Pl BR+ <4 x VPNI

I I I I I l I I I f l l I I l I I I I I I J I l I I I I I I I I JsvA

I·

·I

SVPN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 00 05 04 ·03 02 01 00
4

xsvPN I I I I I l I I I I I I I I I I f I I I I I I I I I I I I I Io !of
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

SBR

I I I I I I I II I I I I I I I I I I I I l I I I I I I I I II(
23 22 21 2() 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

SBR + (4 x SVPN)

I I I I I I I I I I I I I I II I I I I I I l II

PA OF SPTE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 '03 02 01 00

SYSTEM PTE

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I ICONTENTS OF

I· .

·I

PFN

PA FOR SPTE

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PHYSICAL ADDA. OF !POPTE OR P1 PTE>f

l Ij IIIII I III I IIIl II l IIII
L CONCATENATED~
i-- FROM SVA
I

31 30 29 28 27 26 2524 23 22 21 20 19 18 17 1615 14 13 12 11 10 0908 07 06 0504 0302 01 00

~p~~E~~~~:T~A FOR I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
23 22 212019 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

PA OF OPERAND FOR PO OR Pl

I IIIIIIII I IIIIIIIIIIIIIII
L_ CONCATENATED __J
FROM PO, Pl VA I

TK 4514

Figure 9-17

Memory Management Worksheet for P0, Pl

9-23

Address Translation

MEMORY MANAGEMENT WORKSHEET FOR PO, P1

3130 29 28 27 26 25 24 23 22 21 20 19 18 1716'15 14 13 12 11 10 0908 01100 05 04.03 02 01 00

PO, P1 VIRTUAL ADDRESS

I I I I I ·1 I ! I I I I I I I I I I I I I I I I I I I I I I I I I

·I

SVPN

31302928 27 26 25 24 23 22 212019 18 171615 14 13 12 11 10 09 08 07 06 05 04 03 0201 00

svPN

I I I I I I I I I I I I I I I I I I I I I l l I I l I I I I lo l:ol
31 30 29 28 27 26 2524 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 OS 07 06 05 04 03 02 01 00

POBR OR P1 BR

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II

POBR OR P1BR + 14 x VPN)

I IIII II I I I I I II I III I II IIII III I I IIf

31302928 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0908 07 06 05 04 03 02 01 00

SVA

I·

·I

SVPN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 0100

4 x svPN

I I l I I I I I I I I l I I I I I I I I I I I I I I I l I I Io lof

SBA

I I I I I I I I I I I I I I I i I I I I I ' I I I I I I I I I II

31 30 29 28 27 2G 25 24 23 22 21 20 19 18 17 10 15 14 13 12 1 t 10 09 08 07 06 05 04 03 02 01 00

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

I I I I I I I I I I I I I I I I I I I I I I III

SBR + (4 x SVPN)

PA OF SPTE

31 30 29 28 27 2G 2524 23 22 21 201918 17 16 15 14 13 12 1110 090807 06 05 04'03 020100

SYSTEM PTE

I I I I I I I I I I I I I I I I I I I I I l I I I I I I I I I II
,..

·I

PFN

CONTENTS OF PA FOR SPTE

23 22 2120 1918 17 16 15 14 13 12 1110 Q9 08 07 06 05 04 03 0201 00

PHYSICAL AooR:oF IPOPTE OR PtPTEI

I Il I IIIl I I III IIII III IIIIl

CONCATENATED _.j

r--FROMSVA
31 30 29 28 27 26 2524 23 22 21 20 19 18 111615 14 13 12 11 10 0908 07 06 0504 03 02 01 00

~P~~e~;;~:T~A FOR I I l I I I I l I I I I I I I I I I I l I I I I I I I I I I l I I
23

PA OF OPERAND FOR PO OR P1

n 21 20 19 rn 11 1s 15 14 13 12 1t 10 09 00 01 06 os 04 03 02 01 oo

I IIIIIIII I III IIIIIII IIIII
L_ CONCATENATED~

FROM PO, Pl VA

T K -4514

Figure 9-18

Memory Management Worksheet for P0, Pl

9-24

Address Translation

MEMORY MANAGEMENT WORKSHEET FOR PO, P1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 1716'15 14 13 12 11 10 0908 07106 05 04 03 02 01 00
PO, Pl VIRTUAL ADDRESS

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II

I·

4 x SVPN

·I
I IIIIIIII IIIIIIIII IIIIIIIIIIIIlH

POBA OR Pt BA

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II

SVPN

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0

31 30 29 28 27 26 2524 23 22 21 20 19 18 17 1615 14 1312 1110 09 OS 07 06 0504 03 020100

3130 2928 2726 25 24 23 22 21 20 1918 17 1615 1413 12 11 10 0908 07 06 0504 0302 01 00
POBA OR Pt BR+ <4 x VPNJ

I I I I I I l I l l I I I l I I I I I I I I I I I I I I I I I I lsvA

I·

·I

SVPN

31 30 29 28 27 2G 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 00 OS 07 05 05 04 03 02 01 00
4 x svPN

I I I l I l l I I I j I I l I l l l l l I l I 1-1 I l I I I Iolol
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 tG 15 14 13 12 11 tO 09 08 07 06 05 04 03 02 Ot 00

SBA

I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

SBR + 14 x SVPN)

I I I I ( i I I I I I I I I I I I I I I I I I t I PA OF SPTE
I

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 '03 02 0100
SYSTEM PTE

I I I I I I I I l I I I I I I I I I I I I I I I I I l ' I \ I II
J..
PFN
•I

CONTENTS OF PA FOR SPTE

23 22 212019 18 17 16 15 14 13 12 1110 09 08 07 06 05 04 03 0201 00

PHYSICAL ADDA.OF IPOPTE OR PlPTE)

I I I I I I I: I I I I I I I I I I I I I I I I I I
.

CONCA TENATED__)
r-FROMSVA
I

31 30 29 28 27 26 252·t 23 22 21 20 19 18 17 1615 14 13 12 11 10 0908 07 06 0504 0302 01 00

~p~~E~;~~:T:A FOR I I I I I I I I I I I I I I I I I I I I I I I I I I I l I I I I I
23 '22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

PA OF OPERAND FOR PO OR Pl

I I I I I -1 I I I I I I I I I I I I I I I I I I I
L_ CONCATENATED __J
tFROMPO.Pl VA I
TK-4514

Figure 9-19

Memory Management Worksheet for P0, Pl

9-25

Address Translation

ADDRESS TRANSLATION PROGRAM
0
SCBB
200

TEST PROGRAM

SCBB

TEST OPERAND

SCBB

400

TRCS
TRCB

1200
PROCESSOR SETUP

TRCB
TEST OPERAND

TEST PROGRAM
PROCESSOR SET UP

80,000,000

SYSTEM PAGE TABLES
SVA OF POPTE

80,000,400
80,000,600

SBR

I SLR

400
600

800
AOO

coo
EOO

INTERRUPT STACK

1400

200

80,000,000

POBR

Pl LR

1000
1200
1400
1600

PO PAGE TABLES

VA 200 = PA 1000
VA 400 =PA COO
VA 1200 =PA 1200
VA 80,000,000 =PA 1600
VA 80,000,400 =PA EOO

INTERRUPT STACK

TK-4451

Figure 9-20

Address Translation Program

9-26

VAX-11/750 LEVEL II

System Introduction

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

VAX 11/750 LEVEL II

Memory Address Logic

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Memory Address Logic

Memory Address Logic
INTRODUCTION
The memory address logic is located on the MIC module
and consists of four individual address chips that are
identical.
The purpose of this logic is to provide virtual address
information to the translating buffer and physical
address information to the data routing and alignment
section.
The function
address for:
a.
b.
c.
d.
e.

the

logic

Normal PC
Branch offsets
Pre fetching
Microcoded memory references
Snapshooting the CMI

10-1

manipulate

memory

Memory Address Logic

MODULE X:

MEMORY ADDRESS LOGIC
SYNOPSIS

This module presents technical information concerning
the memory address logic of the 11/750 CPU at both
the block diagram and chip level to include the
following:
a.
b.
c.
- d.

virtual add r,ess registers
program counter
program counter backup
program counter increment

and a fault isolation laboratory exercise.
OBJECTIVES
Identify the major memory address logic components by
correctly labeling them on a blank block diagram.
Utilizing the MIC module schematics, trace the signal
path for a preselected signal in the memory address
logic.
Given a diagnostic printout of a failing 11/750 CPU,
isolate the defective memory address logic gate
array.
SAMPLE TEST ITEM
In the memory address logic, the signal LATCH MAL is
used to:
a.
b.
c.
d.

load PC
load MA
select W Bus as input to address logic
none of the above

10-2

Memory Address Logic

LAB EXERCISE
a.
b.
c.
d.
e.
f.

load microdiagnostics
run microdiagnostics
interpret error printout
isolate malfunction to module
isolate malfunction to chip
perform appropriate repairs
RESOURCES

11/750 Specifications
11/750 Microcode Listing
11/750 Schematic Drawings

10-3

Memory Address Logic

OUTLINE
A.

Characteristics
1.
2.

Location
Implementation

Purpose

Functions
1.
2.
3.
4.
5.

Prefetching
Normal PC
Branch offsets
Snapshooting CML
Microcoded memory references

Detailed Description
1.
2.

Eight bit slice
Major sections

Add Chip Inputs/Outputs

Signal Flow

10-4

Memory Address Logic

Address Logic Purpose/Functions
Purpose: provide address information to:
A.
B.

Translation Buffer
Memory Data Register

Function: manipulate memory address for:
A.
B.
C.
D.
E.

Normal PC
Branch Offset
Prefetching
Microcoded Memory References
Snapshooting CMI

r~ss-----

-- ---- --

Ct!W

I
I
I

I
I

I
I
I
I

L __ _
OAT.I\ ROUTING
ANO ALIGNMENT

TOX9
D£COOE

ADDRESS CHIP BLOCK DIAGftAM

Figure 10-1

Simplified Chip Block Diagram

10-5

Memory Address Logic

ADDRESS CHIP (ADD)

4 X 8 BIT SLICE
PC+SIZE

LATCH

(AOK) MIC08 E-VA VAL

(PRK) MIC 08 ENA PC L _ _.._..__ ___.w
MIC04 ENA PC BACKUP L

--+-+-------to---....

PC BACKUP

+4
INCREMENT

weus ·

0 +1 +2 +4

1XX 0

2 3

MUX

LATCH

MIC04 ASRC SEL SxH
\ADK) MIC08 BSRC SEL SxH

MtCOll LATCH MA L
(PR Kl

ADDER
(PRK) MIC06 MA SELECT SxH ------<~------

TK·3350

Figure 10-2

Address Chip 4 X 8 Size and Signals

10-6

Memory Address Logic

ASRC, B SRL and MA Select Lines

Table 13-1

ASRC <S 2: S0> H TRUE
Controls A MUX Input to ADDER, From MIC 4
S2

A Input

WBUS

B SRC <Sl:S0> H TRUE
Control B MUX Input, From ADK Chip
Sl

B Input

VA SAVE (PC+SIZE)

MA SELECT <Sl:S0> H TRUE
Controls MUX Input to MA LATCH, From PRK Chip
Sl

MA Input

INC REMENTER

PC BACKUP

10-7

Memory Address Logic

LATCH MA
COMP ~.!ODE

EN PC SAC:< UP
ENPC

MSEO VA 00

CLK
CONT~CL

ENVA
EN VA SAVE
8 CL:<--t---'

MAOOO

INC. CARRY I N - - + - - - - - - - . - . . P . - - . ; . . - - - - - - -

MAOOl

ASRCSEL S2

ASRCSELSl

MA002

ASRCSELSO
BSRCSELSl
BSRCSEL SO

MUX
CONTROL

BACKUP

PG SNORY

MAMUX

MA0-03
MA004

PCINC.

CHIPIO

MAO OS

MA SELECT SI
MA SELECT SO

MA006

MAO OT

CARRY IN

XBPCOO

weoo
PC

WBOl
WB02

AMUX/

WBOJ

ADDER

XBPCOl
XS PC02

'NB 04

wees

CARRY

WSC6

LOOK

WB07

AHEAD

CARRY GEN 1'
CARRY GEN 2·
CARRY PROP
INC. CARRY OUT

ADO CHIP SIGNALS (1 OF 4)
TK~D71!

Figure 10-3

Address Chip Signals In/Out

10-8

l':rj

......
Ul
c

INC
XO PC <02:00> CARRY
IN

l"1

Cl>

.....
I

ENPC

VA SAVE

a..

B MUX

LATCli

.....
&

"°

SAVE

BSRC SEL 51

BSAC SEL SO

EN PC

BACKUP

()

PAGE BNOAV

A CARRY IN - -

.....

0
......
OJ
Ul
l"1

EN VA

ASRC SEI. Sl
ASRC SEL SO

LATCli MA

l"1

0
0

W BUS<7:0>

0
:J

MAD<7:0>

LATCll

UP
ADDER 1 - - - - - - 1

ll1
.....

BACK

()

::r
......

_..,.INC CARRY OUT

l"1

en
en

INC

CARRY
CARRY

MA SEL Si
MA SEL SO

COMP MODE

----'

~AOP

GEN

- .. "'

I LOOK 1
AHEAD

r-~

I CAfiRV I

l'1

~----J
745182

CONTROL BLOCK DIAGRAM
'ADD CHIP'
<10F4>

a..
TK·ll3B

'CD
"""

en
en

......
0

Memory Address Logic

As you look at the Memory Interconnect Module [MIC] you
must first look at all of its basic funtions as written in
2.6 of the manual and attempt to put them in perspective. To
do this one of the ideas you must maintain is that the MIC
module only functions in two basic fashions.
I.
2.

performs micro coded orders
monitors non micro coded functions
a. prefetch needed I-STREAM data
b. monitor micro trap conditions

Let's look at these two functions in an overview separately.
1.

Performs Micro Coded Functions

Micro coded functions are functions that the MIC
performs under direct control of the different micro fields
W control, bus function and M source that are sourced from
the control store module for a specific micro address. Some
examples of these are:
a.
b.
c.
d.

read or write to memory [or an I/O device]
source data from the MDR to the M bus
probe translation buffer for access violations
write to status and control registers on MIC

Since these functions are coming from the micro word and use
some of the same circuitry you must realize that not all
functions can be performed at once.
The MIC decodes one
micro instruction at a time for its needed fields. [W
control, M source, and bus function].
You cannot tell the
MIC to read from memory in the same micro instruction that
tells it to load the virtual address with data from the
WBUS. For example: it takes at least four micro words to
perform the following macro instruction. MOVL (Rl) ,(R2).
2. Non Micro Coded Functions.
Some of the non micro coded functions relate directly to
the micro coded functions, such as; while the MIC is reading
from memory data in address 1000 it is possible that memory
management is enabled. This would have been enabled by
writing to the MME status and control register (a micro
coded function).
Once it is enabled the MIC will monitor
for translation buffer hi ts, misses and access violations.
This will be performed independently of the microed function
of read. This monitoring function is due to the access
control violation chip [ACV] and the micro trap chip [UTR].
These chips are constantly monitoring for hits, misses and

10-10

Memory Address Logic

access violations when MM is enabled. If any improper
conditions are found during a micro coded function a micro
trap is performed to place the proper micro address on the
micro address lines that places the machine in the proper
routine to handle the improper condition.
That is only one example of monitoring error conditions.
The ACV chip is also constantly monitoring the control store
parity condition in the machine for parity errors.
Another non micro coded function is to fetch I-STREAM
data for use by the processor independent of the micro code.
To do this the MIC must first load the execution buffers
with. the needed data to start with. This is done by loading
the 0 PC 0 with an address thus causing the condition of
0
flushing the execution buffer 0 • Flushing causes the MIC to
take the address in the 0 PC" and reading from memory two
longwords and storing them into the execution buffers
[XB0,XB1]. The I-STREAM data is then constantly monitored by
the pre fetch control chip [PRK], UTR using the updated "PC"
to see if one of the XBs are· empty and need to be refilled
with another instruction from memory.
If this occurs the
MIC will perform a non micro coded function called prefetch.
This causes the MIC to generate a non micro coded read to
memory (or cache) to keep the XBs full for use by the
processor. This prefetch·function cannot be performed at the
same time as a microcoded read as they use the same data
pa th on the MIC.
This brings up another non micro coded function of the
MIC. That being, what happens if the instruction being
executed asks for data from memory (via the virtual address
register VA)?
This data is not I-STREAM data but data
needed by the operand to complete the instruction. This data
is not stored in the XBs and may not be cached so it might
have to be fetched from memory. Now this takes more time
than the micro word takes to execute, so it is possible that
the next micro word from the control store says get the data
I just asked for and it may not be available yet. If this
happens at this time the MIC would generate a stall
condition to the DPM module stopping the micro word from
performing the function until the data that was asked for
was fetched and stored for its use.
NOTE: The MIC didn't automatically
generate the stall condition when it
went to memory to fetch the needed data.
Only when the micro word needed the data and it wasn't
available did the MIC generate the stall condition.
This
10-11

Memory Address Logic

stall condition, access violation checks,~ cache and
translation buffer hi ts and misses are monitored for both
prefetches and micro coded memory reference~.

10-12

VAX-11/750 LEVEL II

Translation Buffer

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Translation Buffer

INTRODUCTION
The location of the translation buffer is on the MIC
module.
The purpose of the translation buffer is to
store PTEs for address translation and access rights.
Its function is to provide the 15 most significant
address bits which correspond to the 23 most significant
virtual address bits.

11-1

Translation Buffer

MODULE XI:

TRANSLATION BUFFER
SYNOPSIS

This module is designed as a block diagram
schemetic level analysis of the following:
a.
b.
c.
d •·
e.
f.

and

characteristics
inputs/outputs
microroutines
PTE formats
tag and index formats
parity checking

Also included
exercise.

fault

isolation

laboratory

OBJECTIVES
Identify
the
major
translation buffer logic
components by correctly labeling each on a blank
b 1 oc k d i ag ram •
With a malfunction inserted on the MIC module of the
Comet CPU, utilize all available documentation,
diagnostics and test equipment to isolate the
malfunction to the chip level.
Given statements concerning the translation buffer,
correctly select the major components described from
a list of components, writing the answer in the space
provided.

SAMPLE TEST ITEM
The translation buffer is a/an
a.
b.
c.
d.

instruction decoder
two way set associative memory
physical address generator
none of the above

11-2

Translation Buffer

LAB EXERCISE
a.
b.
c.
· d.
e.
f.

load microdiagnostics
run microdiagnostics
interpret error printout
isolate malfunction to module
isolate malfunction to chip
perform appropriate repairs

RESOURCES
Comet Specifications
Comet Print Set
Comet Microcode Listing

11-3

Translation Buffer

OUTLINE
A.

Purpose

Characteristics
1.
2.
3.

Type
Location
Interfaces with

Function
1.
2.

Translation Buffer Organization
1.

2.
3.
E.

Tag
Data Stores
Physical Dimensions

Simplified Block Diagram
1.
2.
3.
4.
5.

2-way set associative cache
VA bit grouping
Operation
Parity
Control

11-4

Translation Buffer

OUTLINE (continued)
F.

Address Translation

Detailed Block Diagram Description
1.

2.
H.

Microroutines
1.

2.
I.

Read cycle
Write cycle

Invalidate
TB Miss (Read Cycle)

Registers

11-5

Translation Buffer

Translation Buffer
Purpose:

To store Page Table Entries
translation and access rights.

(PTEs)

for

address

Function: 1.

Provide 15 most significant physical address
bits corresponding to the 23 most significant
address bits of a virtual address to the
Physical Address Bus (PA) •

Provide 4 access conrol bits and modify bit to
Access Control Violation (ACV) chip and utrap
(UTR) chip for control functions.

Characteristics: 2-way set associative cache mode up 2K
discrete RAMs on Mic module.
Cache
similar to 11/70 in that divided into
Tag and Data store with each containing
518 locations.
The translation buffer (TB) is transparent to the microcode.
That is, when a regular read or write function is being
performed the microcode does not determine whether TB is
enabled or disabled.
This is done by the Memory Management
Enable bit.
Bit 0 in S/C Register i 0 in ADK chip {IPR
Register i 38 bit 0) by enabling this bit you do two things:
1.

Change output of AMUX select from ADK chip to say Sl
Low/S0 Low instead of Sl High/S0 Low.
This allows
only lower byte of MAD 1 ines to Physical Address
Lines (PAD) to be concatenated with output of TB
data store for 24-bit physical address when DBUS
select is cache to DBUS.

Al lows outputs from ADK for enabling errors to be
checked from TB and allows passing of data from TB
data to PAD.

11-6

Translation- Buffer

To look at the TB and see how it works, we must realize some
basic facts.
1.

There will always be an address inputted to the TAG
store with or without MME.
Whatever is input will
cause an output that will be checked for bits and
Parity without enabled control signals.
Whatever
signal (hit or error) will not be used unless MME is
set and TB Parity Enable generated from ADK chip.

The TB data store is always receiving the MAD lines
also and will always output whatever it has that
rel ates to the address bit not allowed out to the
PAD unless "TB output En" generated by ADK chip
when MME.
Data Parity is detected but not used by
utrap chip unless "TB Parity Enable" generated by
ADK.

11-7

Translation Buffer
TRANSLATION BUFFER ORGANIZATION

t==

GROUPO

@=ADDRESS TAG FIE LO

17 BITS

··

FIELD

ADDRESS
BITS
<31;15:9>

PARITY-rr
ADDRESS FiELD

_r.:"\

I
I

;I]

..!

'
Li

ADDRESS
BIT

A = B
COMPARATOR
Az B

J i~
~.q

PARITY
CHECK

I COMPARATOR

•

HIT l

PARITY
CHECK

A=B

TB TAG 0
PERR

ACV

FIELD

l p vi

PFN

HITO

TB TAGS

I
I
I

I
I

ADDRESS BITS
ADDRESS FIEL D

I
I
I

rr--•ARITY

-I

<30:16>

VALID BIT
!. ADDRESS FIELD

256
!NO EX
POS ITIONS

I
INDEX

17 BITS~

BIT~ !--15 BITS- ~1 BIT

VAL 10 BIT

INDEX

GROUP1

34 BITS

TB TAG 1 PE RR

--lo-

lMUX

l
PFN

PAO OUT

l I-p

jACV M

I I

256
IND EX
ITIONS

TB
DATA
STORES

CI9> PO]

F .

J::Lj

ACU BITS

15
BITS
PFN

1:1TS~1
ACY
!

3
SITS
PARITY

MSIT

IPARITY 23 BITS--1-,- - - - - 23 BITS
~GROUPO

GROUP1
TIC-1171

Figure 11-1

Translation Buffer Organization

11-8

Translation Buffer

MAD<31:9>
<30:16>

<31,15:9>

<31,15:9> <30:16>

<31,15:9>

<30:16>

TAG 1

TAGO

A=B

HITO

<S>
PAD[23:3]

<23:9;7:3>

PTE

PTE
GROUP1

GROUPO

...
MUX

PAD<23:3>
'SIMPLIFIED BLOCK'

TRANSLATION BUFFER
TK-1112

Figure 11-2

Translation Buffer Simplified Block

11-9

MA0<31:9>
1"%.]

<30:16>

<31,16:0>

1-J•

PAR.
GEN.

""'Cl>

<31,15:9> <30:16>

I-'
I-'

T1 WRITE ENAL

TB TAG 1 PERR

t-3

""'
QJ

::J

HITl

Ul
I-'
QJ

rt
1-J•

I-'

.......

0
::J

I
I-'
tSl

°'c

<B>
PAD(23:3)

<23:9;7:3>

Ml
Ml
Cl>

PTE
GROUPO

PTE
TO WRITE
ENAL

GROUP1
T1 WRITE ENA L

""'
1"%.]

c
::J
n

t-3

rt
1-J•

0
::J

QJ
I-'

°'

.......
0

7'"

""'

PTE CHECK

::J

.......

PA0<.'.23:3>

rt
1-J•

TB DATA PERA
"fµNt;TIONAL BLOCK"".
TRANSLATION BUFFER

TK:,•1•-1

::J

°'

Ml
Hl
Cl>

..,

PTE liORMAT
h:.J
......
31 30
c:
t"'(

l.Q
CD

........

27 26 25
M

PROT

15 14

0
PFN

MBZ

........

........
........

1..

........
........

•ti

) f,. \

PROTECTl ON

--------~--~~~----------------------------------.~.,---~~----~~----

MUST BE ZERO'S

'PAGE FRAME NUMBER

CODE_·........
h:.J

"'"-----PAGE MODIFIED

t"'(

- - - - - - - - - - - - P A G E VALi D
. TK-1880

t-3
t"'(

::s

1--'

I-'•

::s
0::1

Hl
Hl
CD
t"'(

t'%j

......
lQ
c
rt
CD

I-'
I-'

PTE ROTATION FOR TRANSLATION BUFFER STORAGE

I
U1

31 30
'"O

::t1

tXJ

PROT

15 14

27 26 25

lMI

MBZ

PFN

I··

0
rt
DJ
rt

......

::J
I-'
I-'

·\.

ROT FIELD= 11"" RL.MM.PTE; ROT LEFT MlM. NO. BITS• 9

0
rt

I-'

rt
DJ
::J
(fJ

........
DJ
rt

......

24 23

MBZ

9 8 1

PFN

4 3 2

lvE~G1
~

::J

o:J

H\
H\

CD
rt
(J)

rt
0
rt
DJ
lQ

TK·1877

t%j
~·

"°c

I""(

PTE AFTER ROTATION

~
~

°'
~
~

'"O

ti:J

i-3

:J:il

Hl
rt

MBZ
I

J
.A

MVSJB{ZERO'S

PFN
_J
~

PAGE FRAME NUMBER

4 3 2

9 8 7

24 23

PROT

MBZ

~RorE'cr10~ tPAGE
CODE

MODIFIED

I""(

:;o

PAGE

VALID

OJ
rt

Tt<.·1876

i-3

~·

I""(

::J

::J
Ul
~

OJ
rt
~·

::J
tI1

Hl
Hl

ADDRESS TRANSLATION
31 30

g 8

16 15

BYT1=

VIRTUAL PAGE NUMBER

TRANSLATION BUFFER

,....
""

6:0..
I"'(

Ul
Ul

PFN

i-3
OJ

::s

°'rt......
0

::s

FFL
1

, ..

·j

__J

_JJ

I"'(

........

)

r
PROT.

2 1

PFN

=J-lI-.
td I
PROT

g 8

2·

~--------------P-FN_______________...._______s_v_T_E______~IPA
TK-1881

MIC MODULE
l'1:j

.....

..a
c::
CD
"""'

l
l
I
I
I
I

I-'
I-'

I
00

t-3

::J

I-'

rt
.....
::J
I-'
I-'

I
I-'
U1

r;D;;ll;s- - -

c::

HI
HI

1
I
I
I

Im .J

HITO& 1

--...,

BUS 3:0

I AOK CHIP I

t--.----IWCTRL 5:~1

GAP
0& 1
WA

i
I

IMAD

<31:0>

CONS.

--•f-:--1
LJ-+

L.. TB OUTPUT ENA ITO MUX)
t-..ra GAPO & 1 WR no TAG/DATA sroREI

L---

r---1
'UTR CHIP

I
DATA rrnn I
TAG PEAR ,.J
HIT

ADD

I _______ J

"""'
()

l u VECTOR 3:0 TOMSQ

I
l

UTAAP

WBUS

::J
rt
t;

0
I-'

PAO
<23:3>

l'1:j

r----,

c::

::J
()

t-3

AC 3:0--...1 ACV CHIP I ACV

TB VALID~

l:NC U TRAP

PG BNDRY-l

I PTE CHECK/PAO

.....

::J

u TRAP

I-'

DSIZE 1:0-l

BUS 3:0-+-l

I-'

0
()
~

::J

I-'

rt
.....

I
I

::J

'----'

c::

HI
HI

TB CONTROL

FUNCTIONAL BLOCK
TK·I~

Cl)
t;

Translation Buffer

CLOCK

MICA OT RAP
DECODES

ENABLES

S:.:FFER

4
~

15
MtCflO'{ECTOR

CHECKS
RECEIVERS
PREFEiCH

MICROVEC10R

16/17

STATUS
REGISTERS

xa SELEC"i

XB1
STATUS
REGTSTER
6

ADO REG ENA
STATUS VALID
DOSRVC
MBIT

SC
REGISTER
EN.:..SLES

SC
REGISTERS

INHlSITCMI

ERROR
SUMMARY
REGISTER

".":CTRL HHLXXXLATCHED WCTRt. 2:0
ENC UTRAP 2:0
RTUTOINH
TB P.:.RITY ENA
iB TAG l:OPEAR
TB CATA PERR
TB HIT 1:0

BUS
ERRORS

WRITE aus
Ei<RORINT

BUS ERROR
REGISTER

ACV
213

PARITY
ERROR
REGISTER

wsus

wsus 27:24

XCVRS

VTR CHIP ll".PUTS..'OUiPUTS

*Note:

UT RAP

3:0

xso

P":"~ CH~CK On ?ROSE

GEN DEST INH

7
TK.::1021

Some signals are sent to UTR chip even if memory
management is not enabled, but are not checked unless
•Ts Parity Enable e• is sent from ADK.

Figure 11-9

UTR Chip Inputs/Outputs

11-16

Translation Buffer

ADK CHIP SIGNALS
BCLK
PHASE 1
MCLK EJA
DCLK ENA
DST RMODE
WRITE VECTOR OCC
ATUT DINH
SNAPSHOT CMl
LATCHED WCTRL 5
LATCHED WCTRL 4
LATCHED WTCRL 3
LATCHED WCTRL 2
LATCHED WCTRL 1
LATCHED WCTRL 0
CS BUS 4
LATCHED BUS 3
LATCHED BUS 2
LATCHED BUS 1
LATCHED BUS 0
STATUS VALID
PSL CM.
TB HIT1
TS HITO
PRE FETCH·

BUFFERED
CLOCKS

TB
CONTROL
REGISTER

AMUX
STEERING

RECEIVERS
SAVED MODE
REGISTERS

0 BUS
CONTROL

AMUX SEL Sl
PTE CHECK
AMUX SEL SO
TB OUTPUT ENABLE

0 BUS SEL Sl
D BUSSEL SO
CLK SEL S1
CLK SEL SO

SC
REGISTERS
TB
CONTROL

TB GRP 1 WR
TS GRPOWR

SC REG.
ENABLES

TB PARITY ENA
WBUS
XCVRS/CONT.

BUS
DECODERS
BUS
CYCLE
STATUS

MMUX SELS1

ADDRESS
REG.
ENABLES

WBUS 27

wsus 26
'NBUS 25
WBUS 24

ADO
CHIP
CONTROL

COMP.MODE
BSRC SEL Sl
SSAC SEL SO
ENA VAL
TIC-1873

Figure 11-10

ADK Chip Signals Input/Output

11-17

Translation Buffer

'ACV CHIP SIGNALS•
(•

BCLK
PHASE 1
MCLK ENA
D CLK ENA

CLK

DECODES

BUFFER

FORCE MA 09

PROC INIT

PREF ETCH
RECEIVERS
wsus 27
WBUS26 ·:.eus 25 ---.
'.•/BUS 24
DSIZE 1
D SIZED

MME
REGISTER

ACCESS
CHECK

ACV

MAOO

MICROVECTOR 1

MA01
MA02

MICROVECTOR 0

PG SNORY
BUS4

UTRAP
FP RES OP
CS PARITY ERA
LATCHED BUS 3
LATCHED BUS 2
LATCHED BUS 1
LA TCHE:D BUS 0
TB VALID

CURRENT
MOOE
REG

PTE CHECK/PROBE

!
MICRO
TRAPS

ENC UTRAP2

AC3--+

ENC UTRAP 1

AC2
AC 1
ACO

ENC UTRAPO

TK-1889

Figure 11-11

ACV Chip Signals Input/Output

11-18

LONLIT 41FOOOO'

LONG LITERAL• 41FOOOO

.__c_L_E_A_R...F_LA_G_2_1_ _

•

MP. MTPR. TBIA20

~~oc~ss ·-~·T ~LE~R~ ~~-~ 21

PSL R(LONLIT]
CLEAR FLAGO

TB D+ZLIT8(4]j

TB GET 400 (BIT 10 SET]
VA UNKNOWN

PUSH
JSR
STEPC 2
STEP COUNTER GETS 2,r .
~/
CRAR
ZLIT16[80]
I
.__..._
__
_ _ _ __ . CRAR. GETSWBUS23
.

INCREMENT VA IN BIT 10

SUB. 1 AND BR. IF • 0
LOOP 32 TIMES UNTIL SC • 0

........

INVALIDATE PROCESS SPACE

I\.)

:J
t'(J

........
........

PCR[ZERO]
I
PC·O
CLEAR FLAG 1 .
CLEAR FLAG 1
i
________
....______
RETURN
(1]
1 .... RETURN +1 TO AD0l PUSH i
1

•

I
........

6'c

.......

:J
ct>

CONREGS 0 M[SISEl
R [ZERO]
DECSTEPC

PUSH
DECSTEPC
CRAR ZUT16 [ 40)'.

2ND LOOP
TB GETS 400 (BIT 10 SET)
LOOP TILL FLAG 1 SET

RXCS•O
SISR • 0
STEP COUNTER • 1

JSR

STEP COUNTER • 0 I
CRAR GET WBUS ZZ\

RETURN TO INIT AT
PUSH+1

RETURN+1.

~
"'1
QJ

'PUSH
'
0 ZLIT (80)

MP MTPR. TBIA20·

JSR
SET BIT 31
START CLEAR SYS SPACE

(/)

.....
QJ

.......

::J
ttl

MP. MTPR. TBIA20

Hl
Hl

ct>

INIT ROUTINE <CLEAR Tit>\

"'1

TK-3021\

Rll\O

GET flRE

rn MISS

IMM.OET.PTEI

OET flAOCE5S
flTE

IMM. Ot:T. 'TE. PXI
SYSTEM

flROCESS
SPACE

SflACE

......

SET ERROR
CODE

"°c

RETURN

'7:J

Cl)

1--'
1--'

SET ERROR
CODE

1--'

w
1--'
1--'

I
N
~

OFT flROCE$S
rTE

::0

RETURN

IMM. Gt:T PTE. r>O

Cl)

SET ERROR
CODE

nrrunN

t-3

tII
RETURN

3:
......

• lo

Ul
Ul

t-3

'7:J

FETCl4 PROCESS PTE
!VIRTUAL REAOI

1--'

fMM. GET. l'fE. P>C!IOI

Ul
1--'

OJ
rt

RETURN
RETURN •O

READ TB MISS FLOW

, ,.,.,

......

0
:J
tII

Hl
Hl

Translation Buffer
TRAl'JSLATION BUFFER REGISTERS ·

PROCESSOR REGISTER <3:0>

NAME

PR#

TBGPR

ii:-

MEMSCAR#
D

'UTR CHIP'

l'A ll T- 17

0 =NORMAL
1 =GO DATA ERROR
0 =NORMAL
1=G1 DATA ERROR

O= NORMAL
1 =GO TAG ERROR
0 =NORMAL
1 = G1 TAG ERROR
PROCESSOR REGISTER <3:0>

NAME
MCESR

PR#

~·

MEMSCAR#

8 .
'UTR CHIP'

O=OPERAND
1 = XB
O= NORMAL
1 =UNIBUS UNALIGNED REFERENCE
O= NORMAL
1 =TB ERROR (WRITING A ONE CLEARS TBGPR)
O= NORMAL
1 =BUS ERROR (WRITING A ONE CLEARS BER)
PROCESSOR REGISTER <3:0>·

[ -~=121

NAME
TBHR;

PR#

MEMSCAR#

0
'UTR CHIP'

Lo=Mtss
1 =HIT ;

........... __

'--=0

'""--=0
~=O
TK-1878

Translation Buffer S/C Registers

11-21

Translation Buffer

TRANSLATION BUFFER REGISTERS CON'T

PROCESSOR REGISTER <3:0>

NAME

8=~I~~~~~cJ

TBGDA

~: ~g~~:~ISS

PR#
24

MEMSCAR#
3
'ADK CHIP'

IN GO

0 =NORMAL

1 =FORCE A MISS IN G1

0 =FORCE REPLACE GO
1 =FORCE REPLACE G1
0 = Rfo.NDOM REPLACEMENT
;
1 =FORCE REPLACE (USED WITH BIT 2) ·
PROCESSOR R~GiSTER <3:0>

r--·2T"
L,_______ --

~-:-i
---~L=J

· L
1

NAME

MME

PR#

MEMSCAR#

0
'ADI< CHIP'

a= MEMORY MANAGEMENT OFF
1 =MEMORY MANAGEMENT ON .

TK-1879

Note: S/C Registers are loaded by microcode when a Processor
Register is loaded.
Translation S/C Registers

11-22

VAX 11/750 LEVEL II

Cache

Student Guide

Course produced by Educational Services Department
of

Digital Equipment Corporation

Cache

INTRODUCTION
The cache is located on the MIC module.
Its purpose is
to increase system operation speed by decreasing memory
cycle time.
The function used is storing data in a lK
direct mapped data cache with lK X 14 TAG store and lK X
36 data store.

12-1

Cache

MODULE XII:

CACHE
SYNOPSIS

The cache module is designed as a block diagram and
schematic level analysis of the following:
a.
b.
c.
d.
e.

characteristics
inputs/outputs
tag/index formats
control registers
parity checking

Also included
exercise.

fault

isolation

laboratory

OBJECTIVES
Given a faulty Cornet CPU, isolate the defective cache
chip,
utilizing
all
available
documentation,
diagnostics and test equipment.
Given statements concerning cache and several
possible definitions for each, select the one correct
definition.
Given a blank block diagram of cache,
identify each block by labeling it.

correctly

Utilizing the MIC print set, trace the signal path
for a preseiected signal from origin to destination.

SAMPLE TEST ITEM
The signal EN CACHE L on page 11 of 17 in the MIC
print set, is utilized to:
a.
b.
c.
d.

control output data
control input data
turn cache on
enable parity checker

12-2

Cache

LAB EXERCISE
a.
b.
c.
d.
e.
f.

load rnicrodiagnostics
run rnicrodiagnostics
interpret error printout
isolate malfunction to module
isolate malfunction to chip
perform appropriate repairs

RESOURCES
Cornet Specifications
Cornet Print Set
Cornet Microcode Listing

12-3

Cache

OUTLINE
A.

Function

Purpose

Characteristics

Simplified Block Diagram Physical Description
1.

2.
3.

4.
5.
6.

Tag Store
Data Store
Pad <23: 02>
Parity Generators
Parity Checkers
Comparator

Cache Organization
1.

2.
3.
4.
5.
6.

Tag
Comparator
Tag Parity Checker
Data Store
Data Parity Checker
Pad

12-4

Cache

OUTLINE (continued)
F.

Simplified Block Diagram (Cycle Description)
1.
2.
3.
4.
5.

Read Hit
Read Miss
Write (Four Byte)
Write Hit (1-2 Bytes)
Write Miss

Detailed Block Diagram
1.
2.
3.
4.

Chip Overv~ew
CAK Chip
CMK Chip
UTR Chip

Clear Cache !nit Routine

Registers

12-5

Cache

12
12
PAD < 23:2> - - - , . - - -+--<_i_J"T:- - = > - - - - - - - - . . .

TAG
lKX 14

OUT

<t1:2>

A
DATA
IN

STORE
11(

x 3S

OUT

D BUS DATA
CACHE <31:0>

BYTE< 3:0>
CACHE SIMPLIFIED BLOCK DIAGRAM
TK-3041,

Figure 12-1

12-6

Cache

14BITS~

0
ft6

BITS~-4-~~IT

ADDRESS FIELD BITS

A
L

ADDRESS

BITS

INDEX

CACHE
TAG
STORE

<tt:02>
PAO <t 1:02>

ADDRESS BITS
<23:12

ADDRESS FIELD - - - - - - - . ,_..-"'_._,

osus
CA TAG PAR ERR

CAHIT

ENCACHE

CACHE
DATA
<Jt:O>
CA DATA
PAR ERR

i - - - - 0- - + - - - - 1

ADDRESS

BITS
<11:02>

INDEX

CACHE
DATA
STORE

DATA

PARITY

CACHE ORGANIZATION
TK-3037

Figure 12-2

12-7

Cache

MICROVECTOR 3:0

STATUS 1
PAD 11:02
CACHE TAG
STORE

CAHIT

11< X 14 BITS·

CACHE INT

CACHE VALID

CACHE WR ENA

(TOMSOl
CMK
CHIP

UTA
CHIP

STATUS 0

U TRAP (TO ACV)

STATUS VALID
ENA CMI

(TO MOR)

PAD 23:12

CATAG PAR ERR

CAHIT
CA TAG PAR ERR

PAD 11:02
ENA BYTE 3:0

CACHE WR ENA

CACHE DATA
STORE

BUS4:0
MA 1:0

lK X 36 BITS

CACHE INT

WCTRL 5:0
CAK
CHIP

D SIZE 1:0

ENA BYTE 3:0 (TO OATAI
CACHE VALID (TO TAG)

B CLK H
CACHE WC ENA

CA DATA ?AR ERR
CACHE GRP 0 WR H

STATUS VALID

(TO TAG STORE•

EN CACHE

0 BUS DATA

CACHE DETAI LEO BLOCK DIAGRAM

Figure 12-3

12-8

TK-30::9

Cache

CLOCK
BUFFER
PHASE 1

PRE FETCH
DST RMODE
D SIZE <o 1:OO>
CA TAG PAR ERR
CA DATA PAR ERR
MAD <01:oo>
LATCHED WCTRL <s:o>
STATUS VALID

ROTATOR
CONTROL

D BUS ROT <s1:so>

SUS
DECODES

BYTE
MASK

ENA BYTE <J :O>

9
RECEIVERS

BUS
CYCLE
STATUS

LATCHED BUS <4:0>
SNAPSHOTCMI
1/0 ADDRESS
CAHIT

M MIJ~SELSl

·o·sus

ADDRESS
REGISTER
ENABLE

CACHE
CONTROL
REGISTER

213

INVALIDATE
CONTROL

PARITY
ERROR
REGISTER
16

CACHE
WRITE
CONTROL
10

CACHE
VALID

CACHEGRPOWR

CACHE VALID 0

BIT
11

WBUS.
XCVRS

ERROR
REGISTER

wsus<2 7:24 >
12

14/15
SC
REGISTER
ENABLE
13

SC
REGISTER

CACHE INT.

CAK CHIP INPUTS/OUTPUTS
r

Figure 12-4

12-9

TK-3040

Cache

BCLK
PHASE 1

CLOCK
BUFFER

D SIZE 1:0
MAl:O
OST RMOOE
PREFETCH
MSEQINIT

M CLK ENABLE
CMI CPU PRIORITY

CMI 31:28

BYTE MASK
10/11

BUS
CYCLE
DECODE

CMI
BUS
FUNCTION

ADDRESS REGISTER ENABLE

CMI 27:25
9

CMI DRIVER ENABLE

ADD REG ENA
ENACMI

DCLK ENABLE
HIT

CYCLE
CONTROL

INHIBITCMI

HOLD

INVALIDATE
CONTROL 7

OBBZ

INnCK
TIMEOUT
13

MISCELLANEOUS

ST 1:0

WRITE VECT. ace

CORR. DATA INT.

,,.
M MUXSELSl

STATUS 1:0:

STATUS
CACHE INT
BUS4
LATCHED BUS 3:0
WAIT

STALL
LOGIC

GRANT STALL

INT GRANT

CMK CHIP INPUTS/OUTPUTS .
TIC-3079'

Figure 12-5

12-10

Cache

BClK
0 CLK ENABLE
PHASE 1

CLOCK
SUFFER

MICROTRAP
DECODES

ENABLES
4

MACHINE
CHECKS
RECEIVERS

MICRO'{ ECTOR

UT RAP

MICROVECTOR
3:0

16/17

xao

PTE CHECK OR PROBE
PREF ETCH
XS SELECT
.XB 1:O IN USE
STATUS 1:0
PROC. INIT.
ADD REGENA
STATUS VALID
OOSRVC
MBIT
MSRCXB
LATCHED BUS3
WCTRL HHLXXX
LATCHED WCTRL 2:0
ENC UTRAP 2:0
RTUTO!NH
TB PARITY ENA_
TB TAG l:OPERR
TB DATA PERR
TBHIT 1:0
ACV

GEN DESTINH

STATUS
REGISTERS
XBl
STATUS
REGISTER

SC
INHIBITCMI

REGISTERS
6

SC
REGISTER
ENABLES

ERROR
SUMMARY
REGISTER~

BUS
ERRORS

WRITE BUS
ERROR INT
14

BUS ERROR
REGISTER
10

2/3

PARITY
ERROR
REGISTER

WBUS
XCVRS
11

WBUS27:24

UTR CHIP 11\PVTS/OUTPUTS
TK~027,

Figure 12-6

12-11

------------ I ,!:'.~,:::'°"'"'
...
.. _..,,1oe1u1•1

aDCMl.f,MUW&AltDt

••lt11Utel

.. -...

I:~::

...

1•1t1Ct ......e

I
I

:
t'%j
I-'•

........
N
I
........
N

L---1----.--'

l.Q

L....:.------~-

l"1

1 :.:.".:~:.

VAL•

I~~~

l-@I

i-----··.........

rAO <H.11>

PAl<tUI>

lf'AD<nM>

I
I
~'\.,:.=;:....:..;:,.:;,;_,.
----L----------v------~--------- ------rI

_ _ ___,

••D CUii>

I ::':~lh.CI

........
N
I

I
I
I
I

-....]

I
I
I

tlQIAMUJ.llLlatl

IANI

I
I

1----(V>P-~~~-1-~~~--~~~~~~~

"~----a

:::J

.. 1oa.

I
I
I

&AHi

. . . . . . . !(.DI . . . . . . . , . .

•

. ....

.. .c.IOllAIU.ta'\.

~lAf"'IOWIM.I ..

..!11.'!!\n~':'!•
•
lAUtC

1UH

I
I

•Ila
Ol'I

"""'

li'l"'CU.Nlla ..

!.!.\'
!!\!'!!?".!.
t
I

... 1141

.., •

.oa

IH(&lf\4-,

L----------------·--------------- ------------------~
acao.aovaw.

()

OJ
0

::r
CD

Cache

IN. INIT:
PUSH,
D 2 LIT 0 [400],
NEXT/IN. VA 0

LON LITE 41 FOOOO,
NEXT/IN. PSL. LONLIT

000
IN. PSL. LONLIT:
PSL+-LONLIT

TB ATTEND
CLEAR CACHE
D +-1024

841
IN. VA-0:
VAR [ZERO],
RETURN {1]

________________.

PSL R [LON LIT].

._
83E

VA-O
RETURN +1

825
IN. CLR CACHE:

JSR
CRAR +-2

PUSH,
STEPC2.
CRAR ZLITO [80]
NEXT/IN. PC 0

VAVA+4
CLEAR CACHE,
NEXT/IN. DEC. 0

CLEAR CACHE
VA+- VA+4

820
IN. PC-0:

PC..-o
RETURN+1

PC R [ZERO].
CLEAR FLAG 1,
RETURN [1]

0-0-1
CLEAR CACHE LOOP

818

RXCS+-0
SISR+-0

ASTLVL [4]
NEXT/IN. PCO

843

821

JSR
CRAR+-1
TB
INVALIDATE
ROUTINE

JSR

PUSH,
DECSTEPC
CRAR ZLITO [40],
NEXT/MP. MTAR. TBIA 20
PME-0
FLAG 2 SAY RET OR IRD·1

SAO
PUSH,
D ZLIT 24 [80],
CLEAR FLAG 1
NEXT/MP. MPTR. TBIA 20

8A1
TXCS+-0

DONE WITH CACHE
ASTLVL+-4
FLUSH XS

PUSH,

CONREGS D M(SISR]
R [ZERO].
DEC STEP C

M [SCBB} -i,
NEXT/CN.CPRS. OR. 8,
OR.I

820

CONREGS M [FPDOFFSET]
R [ZERO],

8A2

SCBB+--1
CALLED FROM CONSOLE
END OF INIT

SCBB _ -1

M [SCBB] -1,
IRD1

END INIT
POWER UP

829

CLEAR CACHE INIT ROUTINE
TK-3038

Figure 12-8

12-13

Cache
NAME
3

PR #

MEMSCAR #

CACHE ERROR
REGISTER

UTR Chip

0 = MISS
- - 1 =HIT

0 = NORMAL
= DATA ERROR

'------~l

0 = NORMAL

----------1 = .TAG ERROR
NAME
3

PR i
25

CACHE GROUP
DISABLE REGISTER

MEMSCAR #
6

UTR Chip

___ 0 = CACHE ON
1 = CACHE OFF

-------UNDEFINED
----------UNDEFINED
---------UNDEFINED
NAME

PR i
PART OF
17

CACHE WRITE
ONLY REGISTER
- - 0 =CM! ON

1 = CMI OFF

----= 0
------= 0

----------= 0
CACHE REGISTERS
Cache S/C Registers
12-14

MEMSCAR #
E

UTR Chip

VAX-11/750 LEVEL II

Data Routing and Alignment

Student Guide

Course produced by Educational Services Department
of

Digital Equipment Corporation

Data Routing and Alignment

INTRODUCTION
The data routing and alignment (DR+A) is located on the
MIC module and made up primarily of MDR chips.
Its purpose is to take or give data to/from the data path
portion of the CPU.
The function
following:
I.

the

DR+A

Input buses
1. W bus
2. MA bus

Output

Bidirectional buses
1.
PA bus
2.
Cache bus
3. CMI bus
4.
XB decode bus

Internal buses
1.
C bus
2.
D bus

interface

with

the

bus - M bus

II.

Perform data transfers on read and write cycles.

III.

Data alignment for use by the data path module.

13-1

Data Routing and Alignment

MODULE XIII:

DATA ROUTING AND ALIGNMENT
SYNOPSIS

The data routing and alignment module is designed as
a block and schematic diagram analysis of the
following:
a.
b.
c.
d.
e.
f.
g.
h.
i.

data routing
cache/CM! interface
WDR
MOR
W bus interface
XB interface
CMI address register
I/O address latch
microroutines

OBJECTIVES
Identify the data routing and alignment elements by
answering multiple choice questions.
The elements
include:
a.
b.
c.

data routing
cache/CM! interface
CPU bus interfaces

Utilizing the MIC module schematic diagram, trace the
origin and destination of a specified signal.
With a malfunction inserted in the 11/750 CPU on the
MIC module, utilize all avail'able documentation and
test equipment to isolate malfunction to chip level.

SAMPLE TEST ITEM
Select the statement that is NOT true about the data
routing and alignment logic.
a.
b.
c.
d.

Memory data received from the CM! is stored in
the MOR.
The CMI address latch holds the virtual address
of the operand or instruction referenced.
The XB is an 8 byte instruction cache.
Immediate operands go to the data paths via the M
bus.
13-2

Data Routing and Alignment

LAB EXERCISE
a.
b.
c.
d.
e.
f.

load 11/750 microdiagnostics
run microdiagnostics
interpret error print out
isolate malfunction to a module
isolate malfunction to a chip
perform appropriate repairs

RESOURCES
Comet Specification
Comet Pr int Set
Comet Microcode Listing

13-3

Data Routing and Alignment

OUTLINE
XIII.

Data Routing and Alignment
A.

General Characteristics

Purpose

Functions

Simplified Block Diagram

Memory Cycles
1.

Basic

With Cache

Virtual Memory Addressing

Control Block Diagram Signals

Data Rotation

Chip Descriptions
1.

MDR

PRK

13-4

...

AO(ltili!HCl•IAelll

, ''""'

I-'

w
I

L_:.. ___ _

I-'

w
I

I :~·.:::.

I ~::~IUICI
I
I
I
I

H
()

tp
1--1

--0

w
rt

::0

"'.!!'

•IOCMI

I
I
I
I
I

I
I

·~·· JI

p1U"'41

L____ _

......

I
I
•

::J

l.Q

I
I

::J
0..

)>I
I-'

l.Q

..J

......

,,_ !3::J
CD

::J
rt

waus---.----1 ADDRESS
l"%j

.......

\.Q

CACHE

c..,
Cl)

......
w
I
N

......
w
I
O"I

.......

"'d

......
.......

c
BUS

.......

Cl)

0...

CMI

0
:;o
XBO

01
t-t

DATA ROUTING
AND ALIGNMENT
(MORI
8 X 4 Bl'f SLICE

XB1

TO XB

DECODE

'----

I
I
I

0
7"'

!lJ

rt
DJ

MBUS-.-.----<

SIMPLIFIED BLOCK DIAG

TK-3030

:;o
0

c
rt
......
:;::J

\.Q
!lJ
:;::J

0...
~
......
......

\.Q

:;::J

a
CD

:;::J

Data Routing and Alignment

WBUS

FROM

ADD REGENA

TOTS

TO CACHE

ADDRESS

AMUX SELX

DBUS ROTSX
CBUS

CLKSELSX

t/0
DBUS

~""'---~~~~~~~~~...._~

WRITE
ADD
i--..._~~

CMI

REG

MBUS

SNAPSHOT
CMI

XBPCXX
MMUX
SELX2
(AOK)
0 BUSSELSK

S1
0
0

B
DECODE

so I DBUS

S1 sol CLOCK

0
1
0
1

0
0
1

CACHE
CMI
WBUS
OSR

MOR CONTROL

Figure 13-3

DR + A Control Block

13-7

ADK
CLKSEL SX

0 ' NONE
1
0

MOR
XB

WOR
TIC-3031

Data Routing and Alignment

A MUX SEL <Sl:S0> H TRUE
Controls MOX Input to A MOX, From ADK Chip, To PA BUS
Sl

Input to PA BUS

CMI ADD REG

CMI DATA

MA BUS

D BUS

* Note:

During VA transfer with MME, A MOX SEL = CMI
address and D BUS SEL = Cache only lower byte of
address allowed to pass through AMUX.
M MOX SEL <Sl:S0> H TRUE

M MOX SEL control what inputs are selected to the M
BUS.
Sl is actually named M MUX SEL 1 from PRK.
50 is actually latched MSRC 2 from MIC 5.

Data to M BUS

MDR

XB DATA

MA BUS

PA BUS

13-8

Data Routing and Alignment

DBUS ROT S<l:0> H
DBUS ROT S<l:0> H cause data from the DBUS to appear on the
inputs to the MDR and WDR byte rotator as shown in the
following chart:
DBUS ROT Sl H

DBUS ROT S0 H

LOW

HIGH

LOW

HIGH

ROT OUT (BYTES)

CLK SEL S<l :0 > H
CLK SEL S<l:0> H determine which DBUS destinations will be
clocked on the low to high transition of B CLK L according
to the following chart:
CLK SEL Sl H

CL.K SEL S0 H

ENABLE

LOW

NOTHING

LOW

HIGH

MDR

HIGH

LOW

HIGH

WDR

13-9

Data Routing and Alignment

In addition to the conditions listed in the chart, portions
of the MOR must be enabled for data returning from a READ,
SECOND REFERENCE.
A READ< SECOND REFERENCE is decoded in
the MOR chip when:
DBUS ROT S<l:0> Hnot equal to zero and
CLK SEL S<l:0> H equal zero and
WDR not being sourced onto the MBUS
Then, clocks are enabled for bytes of the MOR as shown in
the following chart:
DBUS ROT Sl H

DBUS ROT S0 H

LOW

HIGH

LOW

HIGH

BYTES ENABLED

Any time the MDR or any portion of the MOR is enabled or XB
is enabled, and CM! DATA is selected on the DBUS, the WDR is
also enabled.
In this case, the WDR MUX is steered to DBUS
data enabled.
In this case, the WDR MU X is steered to DBUS
data instead of the DBUS ROTATOR output.

13-10

Data Routing and Alignment

Execution Buffer
XB DATA SELECTION
PC <01: 00 > H
PC <01:00> H and XB SELECT H determine which bytes of each
XB will appear on the XB DECODE BUS, and on the MBUS i f the
MBUS MULTIPLEXER is steered to XB DATA, according to the
following chart:
XB DEC
BYTE 1

XB DEC
BYTE 0

PC 00 H

MBUS
BYTE 3

MBUS
BYTE 2

MBUS
BYTE 1

MBUS
BYTE 0

LOW

XBl
BYTE 3

XBl

LOW

BYTE 2

XBl
BYTE 1

XBl
BYTE 0

LOW

HIGH

XB0
BYTE 0

XBl
BYTE 3

XBl
BYTE 2

XBl
BYTE 1

LOW

HIGH

LOW

XB0
BYTE 1

XB0
BYTE 0

XBl
BYTE 3

XBl
BYTE 2

LOW

HIGH

XB0
BYTE 2

XB0
BYTE 1

XB0
BYTE 0

XBl
BYTE 3

HIGH

LOW

XB0
BYTE 3

XB0
BYTE 2

XB0
BYTE 1

XB0
BYTE 0

HIGH

LOW

HIGH

XBl·
BYTE 0

XB0
BYTE 3

XB0
BYTE 2

XB0
BYTE 1

HIGH

LOW

XBl
BYTE 1

XBl
BYTE 0

XB0
BYTE 3

XB0
BYTE 2

HIGH

XBl
BYTE 2

XBl
BYTE 1

XBl
BYTE 0

XB0
BYTE 3

XB
SEL H

PC 01 H

LOW

HIGH

13-11

Data Routing and Alignment
ADD REG. ENA
SNAPSHOT CMI

MGM·
DATA:
REG

CLK
CONTROL I

CLK SEL S1 :SO

D BUS SEL S1 :SO

·--r.> PAOOO
AMUX SEL Sl :SO

A BUS MUX

PAOOS

> PA016
MISC.
CONTROL;

ENABLE CMI

EXECUTION
BUFFER
D BUS ROT S1 :SO

D BUS ROTATOR

WRITE
DATA
REGISTER

CACHE 00·

CACHE OS

, - - CACHE 16
' - - CACHE24

, - ; . XBUF 00

XB SELECT

XB ROT 83:80

CMI
ADDRESS
REGISTER

MMUX SEL S1 :SO

MADOO
MAD08

I-> M~OO
!-> r1:rn oa

MAD16

kMB16

MAD 24

MBUS ENA

l-:> XBUF 08

MBUS
MUX

!-~~ MB24

i
t - - - - - - - - - - - - - - - - -''i

WB 00

WB 08

CMI

TRANSCEIVERS

WB16
WB 24

;~-~--·CM 00
I
!.-:-....CMOS

L:!'>

CM 16

'-->CM 24
MOR CHIP INPUTS/OUTPUTS (10F8)
TK-3028

Figure 13-4

MDR Chip Signals Input/Output

13-12

l"%j
.....

ill

(7oo~ssToG~

I-'

w
I

WBUS

I
I

~---~~-

H
()

3
I-'

w
I

I-'

0
OJ

ADD

CHIP

=II

M--~---.

r -.~R:SL~;B;E;-.-, r - -CA~EI
I I
....

....

ADK

~ACV

CHIP

~---J

I I
I I
- - - ...I L
UTR

CAK

CHIP

I-'

()

'"d

:u
<D
I-'

.....

CMK

CHIP

..,
~TOMORIPRK
I

·-·-1- - -- _J
TOMDR

::r
.....

MAD

r-1-.- l .... - -- --.---,·
~

• I 1

MBUS 4 4 - - -

MDR

CHIP

PRK
CHIP

__________
~

'---,••CMI

_..,,I

DAT A ROUTING
ANO ALIGNMENT I

rt
.....

::s

::s
fJl

::r
.....
'"d
fJl

ill

MIC MODULE CHIP RELATIONSHIPS
TK·30:14

::s

OJ
~
I-'

.....

ill

::s

a
<D

::s

Data Routing and Alignment

BCLK
PHASE 1
MCLK ENABLE

CLOCK.
BUFFER

REG LOADED
FLOPS

-> XB SELECT

XB USAGE

XB01 :00
IN USE

DECODES

D CLK ENABLE

ADD
REG
ENABLE

XB PC 01:00

MAMUX
STEERING

::>-MA SELECT

LATCH MA

ISIZE 01:00

Sl:SO

IRD1

DST RMODE
LO OSR.
LATCHED MSRC 04:00

RECEIVERS

BUS
CYCLE
STATUS
ADDRESS
ENABLES

~ENA PC

>ENA VA SAVE

STATUS VALID

LATCHED BUS 03:00
INVALIDATE
CONTROL

MSEQ INIT

MMUX SELECT

> MMUX SEL S1

. SNAPSHOT CMI

LATCHED WCTRL 05:00

- ENA ACV STALL
STALL
~STALL

MISC
PRE FETCH
PRE FETCH

~>PREFETCH

PRI< CHIP INPUTS/OUTPUTS
TK-3023 i

Figure 13-6

PRK Chip Signals Input/Output

13-14

VAX 11/750 LEVEL II

Execution Buffer

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Execution Buffer

INTRODUCTION
The Execution Buffer is located on the MIC module just as
the DR+A is located in the MDR chips.
Its purpose is to
effectively eliminate the time spent by the CPU waiting
for the next instruction or waiting for two memory cycles
when bytes that are needed cross longword boundaries.
Its function is to act as a two longword FIFO buffer that
provides two bytes addressed by. PC and PC+l to the XB
decode bus.

14-1

Execution Buffer

MODULE 14:

EXECUTION BUFFER
SYNOPSIS

The execution buffer module is designed as a block
diagram and schematic level analysis of the
following:
a.
b.
c.

instruction register
operand specifier register
instruction decoder

Execution flows and operand specifier routines will
also be· covered in detail.
A fault isolation
laboratory exercise will be utilized to check student
comprehension.

OBJECTIVES
Given a list of register bits and a list of
functions, correctly match the register bits to its
function.
Identify the major execution buffer logic components
by correctly labeling each on a blank block diagram.
With a malfunction inserted on the MIC module of the
Comet CPU, utilize all available documentation,
diagnostics and test equipment, to isolate the
malfunction to the chip level.
Identify as true or false statements regarding the
execution buffer segment of the 11/750 CPU, writing
the correct answer in the space provided.

SAMPLE TEST ITEM
Indicate in the space provided whether the statement
is true or false.
a.
b.

the instruction register is 32 bits.
the instruction decode is performed by roms.

the

operand

specifier

( 0) •

14-2

is always

byte

zero

Execution Buffer

LAB EXERCISE
a.
b.
c.
d.
e.
f.

load 11/750 microdiagnostics
run microdiagnostics
interpret error printout
isolate malfunction to a module
further isolate malfunction to chip
perform appropriate repairs.

RESOURCES
11/750 Specification
11/750 Print Set
11/750 Microcode Listing

14-3

Execution Buffer

OUTLINE
XIV.

Execution Buffer
A.
B.

D.
E.
F.
G.

Purpose
Function
General Description
Simplified Block Diagram
Prefetch Cycle General Description
Prefetch Detailed Description
XB Selection And Control

14-4

.--------------..1 ::.A:1~..:IO.. IUlll~

AbCllHMCIHl'IAQW

411111U.tCI

1I ~:~2::

l'llllAVAHO<il"tl'il

OtMICIMA,.IQ

111111

+.-

f,t.0 <UU">

__r;;;-i_
~

I-'

.a:::.
I
I-'

I-'

.a:::.
I
U1

H
()

I-'

0
()

;i'\"

t:1
I-'•

l.Q
~

9
(AOl(I

lfRllUM!Clll ..... UllMll'H
MtQoil.AICttlDlitlt.M.JM

.. ICWPllUillLIKH

l"Lllf

.!.!_\'~'
~H>.~
8
8 ,. U1•11dl

t
I

f.MI

t.tllO

"'el.IS

()$ft

WUR

..!.!..1·-~'c\""~••

'""'
DIU.t\t-,---

EP-

l ___ __: ______________________ ~---•111: ULQ.~ Dollt•Wl

t.lOIU
MICOIUM.lhlJIU

I tlJ
I xCD

()

c
I rt

I-'•

I ::J
------------------~ ,,_,to
c

t-ti
t-ti

CD
~

Execution Buffer

MSRC XB
XB SELECT

INHIBIT CMI (TO CMA)

XB1:0 IN USE

UTR CHIP

UT RAP

XB PC 1:0
STALL
.,.._E_N_A_PC
_ ___,. .

WBUS

CLOCKS

SAL
CHIP

PAK CHIP

IR01

PRE FETCH

LDOSR

CMK CHIP

ENACMI

GRANT STALL

MOR
CHIP

-------------~xe SELEC.T

I
I

PC01:00

1/0

xeo

MBUSMUX

0 BUS

WAT.

ADO

t--...._-+-..,.CMI

LATCH

MBUS

TO
IRO

ROMS

OSA

____ _

XB1

DECODE
BUS

..._,

EXECUTION BUFFER BLOCK DIAGRAM
'SIMPLIFIED'

Figure 14-2

Execution Buffer Simplified Block

14-6

_J
Tl( 3032

Execution Buffer

LATCH MA
COMP MODE
EN PC BACK UP
ENPC
ENVA

EN VA SAVE

--...
-- CLK
- CONTROL
-..-------

ASRCSELS2
ASRCSELS1
ASRCSELSO
BSRCSELS1
BSRCSELSO

CHIP tD
MASELECTS1
MA SELECT SO

BCLK
INC. CAR RY IN

--..-

-·--

BACKUP

- CONTROL PGBNORY
MUX ---·

---

---.._.

----

WB02
W803

WB04
WB05
WB06
WB07

----

MSEQVAOO

-- MAli-00
-- MAD01

---

MAD02
MAD03
MAD04
MAD05

--- MAffo7
MAD06

INPUT

SAVE

MUX·

MAMUX

MA
PC INC•.

-I

.. .' ~·

i--- ·-

WBOO
WB01

CARRY IN

...-

---.. ADDER
---

-- CARRY'

..-

AMUX/

---

LOOK
AHEAD

----

XBPCOO
XB PC01
-

XBPC02

-- CARRY GEN 1
GEN 2
------ CARRY
CARRY PROP
-- INC. CARRY OUT

ADD CHIP SIGNALS (1 OF 4)
TIC-3028

Figure 14-3

Add Chip Signals Input/Output

14-7

Execution Buffer

REG LOAD~Q
_fl~

BCLK

PHASE 1
MCLK ENABLE

CLOCI(_
BUFFER

XBSELECT

DECODES

DCLK ~NABLE
XBUSAGE

XB01:00

INUSE
ADD
REG

• ENABLE

XB PC01:00

MAMUX

STEERING

ISIZE 01:00

MA~~LECT

S1:SO

LATCH
MA
--.. · · - -

LATCH MA

ADDRESS
ENABLES

ENA PC
ENA VA SAVE

MMUX SE!-~_ci:

MMUX SELS1

BUS
CYCLE
RECEIVERS
.

$.TA1'US

INVALIDATE
CONTROL

ENA ACV STALL
STALL
STALL
MISC
PRE FETCH
PREFETCf:i

PRE FETCH

PRK CHIP INPUTS/OUTPUTS
TK-3023

Figure 14-4

PRK Chip Signals Inputs/Outputs

14 8

Execution Buffer

BCLK
DCLK ENABLE
PHASE 1

-·-- ··-· --··· -

ENABLES

CLOCK
BUFFER

MICROTRAP
DECODES

1
MACHINE
CHECKS
RECEIVERS

PTE CHECK- OR PROBE
PRE FETCH
XBSELECT
.xe 1:0 IN USE
STATUS 1:0
PROC. INIT.
ADO REG ENA
STATUS VALID
OOSRVC
MBIT
MSRCXB
LATCHED BUS 3
WCTRL HHLXXX
LATCHED WCTRL 2:0
ENC UTRAP 2:0
RTUTOINH
TB PARITY ENA

15
MICROVECTOR

13
XBO
STATUS
REGISTER

GEN OEST INH
UTRAP
MICROVECTOR
3:0

18/17

XB1
STATUS
REGISTERS

SC
REGISTERS

INHIBITCMI
12

SC
REGISTER
ENABLES B
ERROR
SUMMARY
REGISTER

BUS
ERRORS
9

WRITE BUS
ERROR INT
14

BUS ERROR

Tl TAG f :0 PERR

TB DATA PERR
TB HIT 1:0
ACV

2/3

PARITY
ERROR
REGISTER11

WBUS
XCVRS

WBUS27:24
7

tJT'RCHIPI~
TK-3027

Figure 14-5

UTR Chip Inputs/Outputs

14--9

Execution Buffer

··--

BCLK

CLOCK
BUFFER

PHASE 1

D SIZE 1:0

MA1:0-__.

DST RMODE
PRE FETCH
. .. ....

-----

MSEQ INIT

CMI CPU PRIORITY'

BYTE MASK

CMI 31:28

10/11

-----------....----------------------....
BUS
CMI

CYCLE

BUS

DECODE2
-

MCLK ENABLE

---···-·· ......

FUNCTION

CMI 27:25

...

ADDRESS REGISTER ENABLE

ADD REG ENA

CMI DRfVER ENABLE

ENACMI

DCLK ENABLE

HIT

CYCLE
CONTROL

INHIBIT CMI

DBBZ
INTLCK

TIMEOUT

HOLD

M MUXSEL S1

CACHE INT

INVALIDATE

CONTROL

WAIT

ST 1:0

.._________1_2.......___.~ WRITE VECT. ace

...

..__..STATUS 1:0

STATUS
.._________________________________
...._...,STATUS VALID
8

BUS4

LATCHED BUS 3:0

MISCELLANEOUS

CORR. DATA INT.

•
STALL
LOGIC

GRANT STALL

INT GRANT

CMK CHIP INPUTS/OUTPUTS

•
TK-3029

Figure 14-6

CMK Chip Inputs/Outputs

14-10

Execution Buffer

ADD REG. ENA_
CLK SEL S1 :SO

MGM

CLK
CONTROL

OAT~

REQ

D_ BUS SEL S1 :sg

....,__,. PAOOO

...__. PAOOS
......,_. ~A016

MISC.

CONTROL
....._

0 BUS ROTATOR

EXECUTION.
BUFFER

WRITE

'DATA
REGISTER

CACHEOQt

----CACHE OS
.._-CACHE16
CACHE 24

XBUF 00
XB ROTB3:BO
XBUF 08

CMI
ADDRESS

MMUX SEL S1 :SO

MBOO
·MB08
MB16

MBUS
MUX

~82~

.,__.,. CMOO
CMI
TRANSCEIVERS

........ CMOS
CM 16
---~CM24.

MDR CHIP
. INPUTS/OUTPUTS C10F8)
TK-3028

Figure 14-7

MDR Chip Signals Input/Output

14-11

Execution Buffer

XBO

M BUS

---

MBUS
MUX

BYTE 0

t--

14 13 12 11 10

BYTE 1

22 21 20 19 18 17

BYTE.2

31 30 29 28 27 26 25 24

BYTE 3

,__

t---; 23
t--

- XB DECODE
XBUF BITS

XB
ROT

)XBSELE

BYTE 0

1-- 15

14 13 12 11 10

BYTE 1

t-- 23

22 21 10 19 18 17 16

BYTE 2

29 28 27 26 25 24

BYTE 3

..___
4~

D BUS

XB1j

,..._ 7 6

XB SELECT

14--

BUS

r--

31 30

PC 01 ! 00
XB SELECTION
Tl<.·3034

Figure 14-8

XB Selection

14-12

Execution Buffer

XB DATA SELECTION
PC <CH: 00 > H
PC <01: 00> H and XB SELECT H determine which bytes of each
XB will appear on the XB DECODE BUS, and on the MBUS if the
MBUS multiplexer is steered to XB DATA, according to the
following chart:
XB DEC
BYTE 1

XB DEC
BYTE 0

XB
SEL H

PC 01 H

PC 00 H

MBUS
BYTE 3

MBUS
BYTE 2

MBUS
BYTE 1

MBUS
BYTE 0

LOW

XBl
BYTE 3

XBl
BYTE 2

XBl
BYTE 1

XBl
BYTE 0

LOW

HIGH

XB0
BYTE

XBl
BYTE 3

XBl
BYTE 2

XBl
BYTE 1

LOW

HIGH

LOW

XB0
BYTE 1

XB0
BYTE 0

XBl
BYTE 3

XBl
BYTE 2

LOW

HIGH

XB0
BYTE 2

XB0
BYTE 1

XB0
BYTE 0

XBl
BYTE 3

HIGH

LOW

XB0
BYTE 3

XB0
BYTE 2

XB0
BYTE 1

XB0
BYTE 0

HIGH

LOW

HIGH

XBl
BYTE 0

XB0
BYTE 3

XB0
BYTE 2

XB0·
BYTE 1

HIGH

LOW

XBl
BYTE 1

XBl
BYTE 0

XB0
BYTE 3

XB0
BYTE 2

HIGH

XBl
BYTE 2

XBl
BYTE 1

XBl
BYTE

XB0
BYTE 3

14-13

Execution Buffer

IR01

LDOSR

#BYTES

FALSE

TRUE

FLASE

TRUE

NUMBER OF BYTES OF I STREAM
MSRC#XB
TK·3033

Figure 14-9

Number of Bytes of I-Stream MSRC # XB

14-14

Execution Buffer

'IWO LONGWORD BUFFERS IN MDR CHIPS

PC JUST LOADED WITH 1.
BOTH
BUFFERS EMPTY.
'IWO BYTES OF
I-STREAM REQUIRED.

PC=l
LONGWORD ADD=0

LONGWORD AT ADDRESS 0 FETCHED.
TWO BYTES OF I-STREAM USED.
PC
INCREMENTS TO 3.
IJWO BYTES OF
I-STREAM REQUIRED.

PC-=3
LONGWORD ADD=4
7

LONGWORD ADD=0
3

LONGWORD AT ADDRESS 4 FETCHED.
TWO BYTES OF I-STREAM USED.
PC
INCREMENTS TO 5. FOUR BYTES OF
I-STREAM REQUIRED.

PC=S
LONGWORD ADD=4

FIRST
BUFFER
NOW
EMPTY.
LONGWORD AT ADDRESS 8 MUST BE
FETCHED TO SATISFY REQUIREMENT.

PC=S
LONGWORD ADD=8
8

LONGWORD ADD=4
7

LONGWORD AT ADDRESS 8 FETCHED.
FOUR BYTES OF I-STREAM USED.
PC INCREMENTS TO 9.

PC=9
LONGWORD ADD=8

PC=9

14-15

ONE
BUFFER
BECOMES
EMPTY.
THREE BYTES REMAIN IN OTHER
BUFFER.
PREFETCHER WILL FILL
EMPTY BUFFER FROM ADDRESS C
(HEX) .

Execution Buffer

NAME
3

PR #

MEMSCAR i

PR #

MEMSCAR i

Part of

ADK Chip

PR #

MEMS CAR i

Part of

BUS ERROR MEMSCAR i
Summary Register 9

_ _ 0 = Normal
1 = Corrected Data
_ _ 0 = Normal
1 = Lost Error

-- =

0 = Normal
1
Uncorrectable Data Error

0 = Normal
1 = Non-Existant Memory

NAME

L3 I 2 I

I 0 ]

Saved Mode
Register

MODE 00 = Kernel
01 = Executive
10 = Supervisor
11 = User
·
0
1
0
l

= Virtual
= Physical

= Read
- = = Modify

NAME
3

Write Vector
Occurred Register

1 = Vector in MOR

Bit <0> is READ/WRITE and is initially 0.
In addition, it
is cleared by an INTERRUPT GRANT bus function and set by a
WRITE VECTOR transaction on the CM! or by a READ LOCK
TIMEOUT.
Miscellaneous Registers

14-16

Execution Buffer

Memory Interface Connect Control Logic General Description
Six 48 pin gate array chips and associated logic chips
working in conjunction with each other monitor WCNTRL, bus
function and MSRC fields from the microword to control
address and data gating, aligning and mutliplexing to and
from the data path module and CMI bus. During this gating,
aligning and multiplexing, the chips will also monitor the
condition of the operation being performed during the
execution of this microinstruction that may cause a
microtrap condition to occur.
If this happens the control
logic will generate the proper microaddress to respond to
the microtrap condition generated.
The basic functions the control logic must perform are
related to the six control chips that are located - on this
module. They are:
1.

Address control chip {ADK) - Drives multiplexing and
gating of address from ADD chip and helps control
transfer through MDR chip.
Also used
for
controlling translation buffer group disables or
group displacement.

Pref etch control chip {PRK) - Controls pref etching
of I-Stream data from memory to be brought to
execution buffers XB0 or XBl independently of
microcode~
PRK also used in conjunction with ADK to
generate or load proper address from/to ADD chips.

Cache control chip (CAK) - In conjunction with ADK
chip controls disabling and enabling of cache.
Controls driving and receiving of data to and from
MOR and cache.
Monitors CMK chips snapshot CMI
output for invalidation of cache on CMI writes.

Access control violation {ACV)
Monitors and
generates ACV signal for access violations and
translation not valid during TB usage or PTE checks
and probes on WBUS. Monitors and generates codes to
microtrap chip in privileged sequence for the
following microtrap conditions.
1.
2.
3.
4.
5.
6.
7.

Control store parity error
FPA received operand
Unaligned unibus data
Write crossing page boundary
Write unlock crossing page boundary
Unaligned data, write unlock
Unaligned data
14-17

Execution Buffer

Microtrap chip (UTR) - Monitors microtrap conditions
during microinstruction and generates encoded
microvector bits <3:0>.
These bits are used in
conjunction with bits <5:4> from microsequencer chip
on DPM to generate 6-bit microaddress. This address
points to the proper microroutine to handle the
microtrap condition decoded by microtrap chip. Also
monitors status from CMK chip to generate write bus
error interrupt to interrupt chip on UBJ module.

CPU memory interconnect control chip (CMK)
Monitors and transmits control signals to and from
CM! bus.
These signals are DBBZ and Hold.
Transmits and monitors byte mask and function bits
<31:25> onto/from CM! bus. Monitors status lines of
CM!.
Generates corrected data interrupt to UBI
module.
Generates grant stall in response to INT
Grant from UBI module to stall microcode during an
interrupt from UBI module.

As we continue on to the discussion of the MIC you must bear
in mind that it monitors actions being performed by the same
microword.
That is, it will be monitoring the same WCNTL
lines, bus function lines and MSRL lines so they may work
together to perform the function specified by the microword.
All WCNTL lines and bus function lines from CSS module are
latched on low to high transition of M CLK and feed to
needed locations on MIC module. M CLK Enable H, B CLK L, D
CLK Enable H and Phase l H will also be used internal to all
control chips for transmitting and receiving purposes along
with loading or reading internal registers (Ex: MEMSCAR).
Following are
definitions:

the

selected

bus

functions

and

their

BUS FUNCTIONS
A 5-bit microfield is required to specify which of the
following bus functions is to. be performed during each
microstep: (BUS CONTROL CODES IN PARENTHESES ARE IN HEX)
(07) NO FUNCTION
(10)

READ

Replace the contents of the MOR with the contents of the
memory location specified by the virtual address presently
in the VA and DSIZE.
(14) READ WITH MODIFY INTENT

14-18

Execution Buffer

Checked for WRITE access.
Otherwise, same as READ unless
the resulting physical address is in UNIBUS space, in which
case the UNIBUS must perform an interlocked operation
(DAT IP).
(11) READ LONGWORD
Same as READ, except the two least significant bits of the
address are ignored.
(For FIELD instructions.)
(15) READ LONGWORD WITH MODIFY INTENT
See READ LONGWORD and READ WITH MODIFY INTENT.
(02) READ, NO MICROTRAP
Same as READ,
microtraps.

but

suppress

ACV

and

unaligned

data

(13) READ LOCK
Same as READ; Checked for WRITE access.
In addition,
signifies to other masters on the CM! that they must not
perform READ LOCK operations until a WRITE UNLOCK operation
has taken place.
If the CPU is unable to perform a READ
LOCK within approximately 64 microseconds of the time it was
initiated, a READ LOCK TIMEOUT will occur.
The READ LOCK
operation will be aborted, a NONEXISTENT MEMORY machine
check will occur, and the WRITE VECTOR OCCURRED bit will be
set in the appropriate status/control register.
(00) READ PHYSICAL ADDRESS
Sarne as READ except that the address in the VA is to be used
as a physical address instead of a virtual address and the
two least significant bits are ignored.
(06) READ, SECOND REFERENCE
Indicates to the memory interface control logic that a
previous READ crossed a longword boundary.
Therefore, only
the portion of data fetched from memory which was not
previously fetched should be clocked into the MDR.
(0B) WRITE UNLOCK, SECOND REFERENCE
See WRITE UNLOCK and WRITE, SECOND REFERENCE

14-19

Execution Buffer

Note
There exists in the memory interface
control logic a "CM! Write Size Latch"
which is used in performing certain write
bus functions.
There are actually three categories of write bus functions:

1.
2.
3.

Those which load the "Write Size Latch"
Those which use the latched size
Those which always write all four bytes regardless
of DSIZE

Category 1 includes:
WRITE
WRITE IF NOT RMODE
WRITE UNLOCK
(WRITE LONGWORD)
Note
WRITE LONGWORD causes the •write Size
Latch" to be loaded with DSIZE, but
always writes all four bytes.
Category 2 includes:
WRITE, SECOND REFERENCE
WRITE UNLOCK, SECOND REFERENCE
WRITE, NO MICROTRAP
Category 3 includes:
WRITE PHYSICAL ADDRESS
WRITE LONGWORD, NO MICROTRAP
WRITE LONGWORD
The "Write Size Latch" is loaded with DSIZE during any
microstep which specifies a Category 1 write bus function,
regardless of any destination inhibits or microtraps which
might occur during that microstep.

(04) READ LOCK TIMEOUT TEST
(Special function for testing timeout counter in MOR chips.)
(18)

WRITE

14-20

Execution Buffer

Replace the contents of the memory location specified by the
virtual address presently in the VA and DSIZE with the
contents of the WDR.
(lA) WRITE IF NOT REGISTER MODE
Sarne as WRITE unless RMODE (REGISTER MODE) from
rnicrosequencer is asserted, in which case do nothing.

the

(19) WRITE LONGWORD
Sarne as WRITE, except the two least significant bits of the
address are ignored.
(For FIELD instructions.)
(0C) WRITE, NO MICROTRAP
Same as WRITE, but suppress ACV,
boundary crossing rnicrotraps.

unaligned data,

and page

(0E) WRITE, NO MICROTRAP, LONG
Sarne as WRITE, NO MICROTRAP, except that a longword is
written ignoring the latched write size. Used for wr i t.ing
the Mbit during mapping subroutines.
(lB) WRITE UNLOCK
Sarne as WRITE. In addition, releases the interlock set by a
READ LOCK operation.
(08) WRITE PHYSICAL ADDRESS
Sarne as WRITE except that the address in the VA is to be
used as a physical address instead of a virtual address and
the two least significant address bits are ignored.
(0A) WRITE, SECOND REFERENCE
Indicates to the memory interface control logic that a
previous WRITE crossed a longword boundary.
Therefore only
the portion of the data in the WDR which was not previously
stored should be written into the specified memory location.
(lD) PROBE ACCESS, WRITE
Check the translation buffer entry corresponding to the
address presently in the VA against the current mode for
validity and write access.
Indicate the results of the
check on the microvector lines.
14-21

Execution Buffer

(lC) PROBE ACCESS, WRITE, MODE SPECIFIED
Same as PROBE ACCESS, WRITE except that access ·is checked
against WBUS <25:24> instead of the current mode.
(12) PTE ACCESS CHECK, WRITE
Same as PROBE ACCESS, WRITE except that a PTE image on ~he
WBUS is checked instead of a translation buffer entry. Note
that the valid bit and the protection code bits must occupy
the same positions on the WBUS as they would if the PTE were
to be loaded into the translation buffer.
( 09) REI CHECK
Check for:
Saved PSL <current mode> GEQU ASTLVL and Saved PSL <IS>

and check the saved PSL (on the WBUS) against the PSL for
any of the following conditions.
Indicate the results of
the checks on the microvector lines:
l.
2.

4.
5.
6.

Saved PSL <current mode> LSSU PSL <current mode>
Saved PSL <IS> EQLU 1 and PSL <IS> EQLU 0
Saved PSL <IS> EQLU l and saved PSL <current mode>
NEQU 0
Saved PSL <IS> EQLU l and saved PSL <IPL> EQLU 0
Saved PSL <IPL> GRTU 0 and saved PSL <current mode>
NEQU 0
Saved PSL <previous mode> LSSU saved PSL <current
mode>
Saved PSL <IPL> GTRU PSL <IPL>

(03) I/O INITIALIZE

Generate UNIBUS !NIT.

(01) PROCESSOR INITIALIZE
Generate a
registers.

reset

signal

which

initializes

status/control

(0F) INTERRUPT GRANT
Causes a BUS GRANT to be issued on the UNIBUS in response to
the highest level BUS REQUEST.
After the grant is issued,
memory interface logic will stall the processor clock until
the grantee releases the UNIBUS.
During the time the

14-22

Execution Buffer

processor is stalled, a WRITE VECTOR transaction may take
place on the CMI which will cause an interrupt vector to be
written into the MOR.
If so, a status register bit will be
set.
(lF) PROBE ACCESS, READ
Check the translation buffer entry corresponding to the
address presently in the VA against the current mode for
validity and read access.
Indicate the results of the check
on the microvector lines as follows:
Note
The following signal name abbreviations
are used to define the state of the
microvector lines during PROBE and
PTE-CHECK microorders:

= PTE MODIFY BIT
= 1 IF VALID PTE
AC
= 1 IF ACCESS ALLOWED
PBOK = l IF NOT CROSSING A PAGE BOUNDARY
PA
= 1 IF MEMORY MAPPING IS NOT ENABLED (PHYS. ADD_.)
M

On PROBE the microvector lines are:
MICROVECTOR <3> = (PBOK .AND. V .AND. AC) .OR. PA
MICROVECTOR <2> = M .AND. ((V .AND. AC) .OR. PA)
MICROVECTOR <l> = V .OR. PA
MICROVECTOR <0> = (AC .AND. V) .OR. PA
On PTE CHECK the microvector lines are:
MICROVECTOR <3> = 0
MICROVECTOR <2> = M .AND. V .AND. AC
MICROVECTOR <l> = V .AND. AC
MICROVECTOR <0> = AC
-~

(lE) PROBE ACCESS, READ, MODE SPECIFIED
Same as PROBE ACCESS, READ except that access is checked
against WBUS <25:24> instead of the current mode.

(16) PTE ACCESS CHECK, READ

14-23

Execution Buffer

Same as PROBE ACCESS, READ except that a PTE image on the
WBUS is checked instead of a translation buffer entry. Note
that the valid bit and the protection code bits must occupy
the same positions on the WBUS as they would if the PTE were
to be loaded into the translation buffer.
(17) PTE ACCESS CHECK, READ, KERNEL MODE
Same as PTE ACCESS CHECK, READ except that access is checked
against kernel mode instead of current mode.
The last group of microorders from the microcode that the
MIC m9d ule needs for performing its functions are the MSRC
group bits <68:64> from the microcode.
The following are
the MSRC codes required for the MIC module.
The MSRC
assignments in parenthesis are in Hex.
(12) MBUS <- MDR
MBUS <- WDR
(17) MBUS <- XB
(18) MBUS <- MA
(19) MBUS <- PC SAVE
(lA) MBUS <- PC
(18) MBUS <- VA
(lF) MBUS <- TB Data (Address in VA)
(13)

Mote
Bits <31:24> will always read as ones.
There are 10 registers internal to 3 control chips that are
designated as status and control registers (S/C) •
The
microcode reads from and write to these registers by loading
a 4-bi t S/C register (not included in the 10 S/Cs) called
S/C address register using WCNTL lines and WBUS.
These
registers will be referred to in the microcode as MEM S/C
REG numbers, yet may be included in a different numbered
Internal processor register (IPR) discussed previously. The
following registers, location, S/C register numbers and IPR6
numbers were discussed previously.
Another important group of controls to be used by the MIC
module are the WCNTRL lines from your microword
(bits
<30:25>).
these lines control the source and destination of
data and address.

14-24

Execution Buffer

the following wbus control codes are required for the memory
interface: (wctrl assignments in parentheses are hex)
(20) VA <- PC + ISIZE + (WBUS)
PC <- PC + ISIZE
(21) RESERVED
(22) VA <- VA + 4
(23) MDR <- (WBUS)
(24) PC <- (WBUS)
(25) VA <- (WBUS)
(26) MBUS <- WDR
(27) MDR <- 0
(28) TB DATA <- (WBUS)
(29) TB VALID BIT <- 0
VA <- (WBUS)
(Invalidate both groups at the index position
addressed by VA) •
(2A) WDR <- (WBUS) UNROTATED (2B) MDR <- OSR, ZERO
EXTENDED
(2C) PC <- PC + (WBUS)
(2D) CACHE VALID BIT <- 0
VA <- (WBUS)
(Invalidate both groups at the index position
addressed by VA.
The address in the VA regis_ter
will be interpreted as a physical address.)
(2E) WDR <- (WBUS)
(2F) MDR <- IR, ZERO EXTENDED
(30) STATUS/CONTROL REGISTER <- WBUS<27:24>
(31) PREVIOUS MODE REGISTER <- WBUS<23:22>
(32) w~US<27:24> <- STATUS/CONTROL REGISTER
(33) BUS GRANT
WBUS<20:16> <- IPL OF CURRENT UNIBUS GRANTEE
(34) STATUS/CONTROL ADDRESS REGISTER <- WBUS<27:24>
(35) PREVIOUS MODE REGISTER <- CURRENT MODE REGISTER,
THEN IS/CURRENT MODE REGISTER <- WBUS<26:24>
(37) REI CHECK (38) ASTLVL REGISTER <- WBUS<26:24>
{39) {RESERVED)
(3A) WBUS<26:24> <- ASTLVL REGISTER
( 3B) (RESERVED)
{3C) HIGHEST SOFTWARE IPR REGISTER<- WBUS<20:16>
(3D) IPL REGISTER <- WBUS<20:16>
(3E) RESERVED
{3F) WBUS<20:16> <- IPL OF LAST UNIBUS GRANTEE

14-25

Execution Buffer

There are two ways to read from memory
l.
2.

Read bus function (microword dependent)
Prefetch (microcode independent)

You may write to memory only under
(microdependent).

a write bus

function

The following functions read, write may create what is
called a "bus cycle" decode from the microword.
A
definition for "bus cycle" would be the starting of and
ending of retrieving data from a location or depositing data
to a location. On a read from memory at address 1000 a bus
cycle may include going out on the CM! to memory or
retrieving the data needed from cache which would not need a
CM! function to memory.
This fact in itself shows that a
definite period of time cannot be assigned to the term "bus
cycle"·. You can, by use of signal names, give the term "bus
cycle" a relative time period.
A bus cycle starts at "Address Register Enable" and ends
with "Status Valid". This means a bus cycle starts when the
address needed for read or write is enabled into CM! ADDRESS
REG on MOR. It ends upon the CMK chip receiving status from
CM! or data from CA received with no errors.
The term "bus cycle" will be used only when referring to
microdependent bus functions that are decoded to need a
"bus cycle".
The same function of reading from memory of
cache may be accomplished by prefetch. That is, Add REG ENA
and status valid signals are used to perform the read start
and end bracketing. Since prefetch is microcode independent
and it uses the same path as a bus function read or write,
they cannot be done at the same time.
Therefore, "bus
cycle" and prefetch use the same basic path for address and
data, but at different times.
Using the instruction MOVL (Rl) (R2) as an example for
control logic in the MIC module includes a lot of
functionality for the module.
1.

You must read f rorn memory at address in GPR#l and
store it.

You must take the data you
address stored in GPR#2.

read and write

it to

Independent of this instruction are the functions of cache
enabled or disabled translation buffer enabled or disabled
and the fact that you might prefetch I-Stream data from
memory to the execution buffer.
14-26

Execution Buffer

Along with these actions, a write to memory may occur on the
CM! causing the MIC module to snapshot the CM!. This being,
taking address that was written on CM! by someone other than
CPU and checking data cache for a hit and invalidating if a
hit.
You may also generate a microtrap condition during the
reading or writing to memory that may cause you to leave the
microsubroutine that handles the MOVL (Rl) (R2) instruction,
to make sure the instruction is completed properly (Ex: TB)
miss may perform address translation and return to finish
instruction. It is also possible the instruction may not be
able to be completed even with microtrap intervention and
you would have to notify the operating program.
Ex: Access
control violation needs macrointervention.
These are the functions and different conditions we wi 11
cover here.
To
perform
this we
will
take
the
microinstruction through each microword needed to perform
the macro MOVL (Rl) (R2) using the needed fields in the MIC
module.
Bus function
WCNTL
MSRC
Following the four microwords needed to perform the MOVL
instruction we'll take it through all four and explain what
needs to be done in the MIC module for each one.
MOVL (Rl)

(R2)

Take data longword from address in Rl and
move it to address in R2.

First Microword
OS.RED 108 address
FPA_Q_M[MDR] VA_R[GPR.R]
CLOBBER MTEMP0 REF
NEXT/OS.READ.EXIT

(RN) register deferred mode
operand address is GPR
(RNUM) put garbage in
MTEMP0.

What the MIC module must do in the first microinstruction
during the first half or phase 1 H is
l.

Source the contents of MDR to the MBUS to be stored
in Q register.
The contents of MDR for this
particular instruction are meaningless but the
microinstruction is used by more macroinstructions
than MOVL long and considerations must be taken.

14-27

Execution Buffer

2.·

During last half or phase 2 it loads the address
from GPR#l via the WBUS to the VA Register in ADD
chip.

Second Microword
OS.READ.EXIT 10E
READ.SIZE [IDEP]
IRDx[l]

Read memory at VA size

During this micro the MIC module must
1.

Take address from VA r~gister and retrieve the data
from either main memory or cache and store into the
MOR (Reg).
(We now have data from address Rl.)

Make available next byte from execution buffer being
used to DPM to decode operand specifier (R2) and DPM
generates next microaddress to go to and update PC.

Third Microword
OS.WRT2 158
Q_M[MDR] VA_R[GPR.R],
CLOBBER MTEMP0 DEF.
IRDx[l]

(RN) Register deferred mode
GPR (RNUM) is operand
address.
Put garbage in
MTEMP0.

MIC Function

Source MOR to MBUS to be stored in Q by DPM.

Load address from GPR#2 via WBUS to VA Reg.
chip.

in ADD

Fourth Microword
IL.MOV.B.W.L.MEM (OR MOVA)
R[DST.R] .SIZ - Q Q - D, WRITE NOT REG
SIZE[IDEP], CCOP2, IRDl
MIC Module

Takes address from VA register and data from WBUS
and writes to memory (and cache if a hit) depending
upon instruction size using write not Reg.

Make available next two bytes from execution buffer
for decoding of next instruction and update PC.

14-28

Execution Buffer

Now that we have the overall picture of all four microwords
let us take a look at each one and see how the MIC module
performs them.
First Microword - OS.RED
FPA Q M[MDR] VA R[GPR.R]
CLOBBER M TEMP 0 DEF.
NEXT/OS.READ.EXIT
Decoded MSRC Field = 12 or MBUS <- MDR
Decoded WCNTL = 25 or VA <- WBUS
Decoded Bus Function = 7 or No Op.
As we said previously, the two functions performed by the
MIC module for this microword are:
1.
2.

Source contents of MDR to QMBUS
Load address from GPR#l to VA Register in ADD chip

These are done at different halves of the microword, since
it is possible to take data fromMDR and have DPM work on it
and send it back to MIC.
This does not happen in t_his
instance but it is possible.
Phase 1
1.

MDR (Reg) sourced to MBUS on Phase 1 H due to MUX
Sel 1 H being L (L=0) and MSRC 2 from CSS being L
(L=0). n MUX Sel 1 H" = 1 comes from PRK chip due to
the fact that no other function needing the MBUS MUX
was decoded and MSRC line 2 was latch as Low
(false).

VA Reg is loaded on Phase 1 L from WBUS in ADD chip
due to:
A.

ASRC Sel line 2 is H coming from miscellaneous
control saying WCNTL 1 ine 1 latched to 0 (Low)
and Phase 1 L causing WBUS through AMUX input to
adder (ASRC lines 0,1 can be anything).

14-29

Execution Buffer

ADK chip decoded WCNTL as WBUS -> VA and
selecting B SRC Sel lines S0, Sl to Sl/0 S0/0 (0
= Low) selecting 0 input to BMUX of adder. WBUS
+ 0 = WBUS.

ADK also sending "ENA VA L" to latch output of
adder to VA because of decoded WCNTL.

Second Microword
As we see, the second microword must read from the address
specified in VA.
The read may be >performed from cache (if
enabled and data is available) or from main memory. To show
this we have what happens during a cache hit and a- cache
miss (both with TB off).
The second function of updating the PC due to DPM taking
next operand specifier will be covered under the prefetch
area.
Basic Read Cache Hit, TB Off
Microword at address 10E:
OS.RED - READ EXIT:
READ SIZE [IDEP]
IRDx[l]
Bus Fune

Read memory from address
in VA • SIZE = DS I ZE
Ex: VA =
100 0
Size
=
Longword

= Read, Meaning - Memory read from VA and DSIZE
from define file and placed into MDR

WCNTL

= From Define File - No Op

MSRC

= From Define File - Default M Temp

As you can see there is no mention of cache or translation
buffer within the microword. You will not see any with the
exceptions of invalidating TB or cache, making checks of TB
for access or validity but never in conjunction with normal
operations on a read or write.
Following this microword through the MIC block diagram we
will find how the address is sent and data is received.
Five of the six control chips (not microtrap chips) monitor
the bus function and checked to see if any other functions
that may be using the needed paths are being done i.e.,
prefetch, snapshot CMI for invalidating cache, for example.
If the paths that are needed are free a Bus Cycle is started
within the MIC module.
14-30

Execution Buffer

We must take the address from the VA register (1000) through
the memory address latch on the ADD chip to the memory
address lines.
(PRK chip decodes read using address in VA)
PRK sets MA 5el lines to 51/l 50/1 with a l = a high true
allowing VA through MA latch.
The addres~ is now on the memory address lines and must get
onto the physical address bus to be sent to cache.
The ADK
chip also decoded read and ORed the fact that memory
management had been disabled to get the AMUX 5el line 50, 51
to 51/l 50/0 (1 H line).
This allowed bits <02:23> of the
VA to be fed onto the physical address lines (PADs).
Note
Bi ts <91: ee> not used as we read only
longwords.
The address (bi ts <02: 23>) are now sent to cache and are
checked for a hit, validity and errors.
At the same time
this is being done the same address from PAD is being
latched into the CM! address register when "ADD REG ENA L"
comes from CMK chip.
(This says start bus cycle.)
The
latching into the CM! address register is done in case of a
cache miss and we need to go to main memory.
In this case
it will not be used.
If the cache has a hit the signal cache hit is sent to the
CAK chip and the CMK chip.
When sent to CAK it is ORed with the fact there are no
errors (the signals Tag or Data Parity errors are false) and
the fact that cache is enabled (from 5/0 Reg #6). This will
Hit
No Errors
Cache Enable

Enable needed byte outputs

allow the CAK chip to use the monitored D5IZE and VA lines
to generate the proper byte enables.
These byte enables go
to the cache data store and allow the data selected by PAD
to be outputted from the RAMs.
In case of longword at 1000
Enable byte 0 and 1, 2, and 3 would be used.
The cache hit signal also goes to CMK chip along with cache
INT from CAK.
(Cache INT meaning Tag or Data Parity errors
are not valid if not a hit).
These signals will be used to
stop a CMI cycle to memory by the CMK chip not sending ENA
CM! to MDR chip and generate status valid for stopping bus
cycle in MIC.
14-31

Execution Buff er

The data outputted from the cache must be sourced onto the D
Bus in the MOR chip and stored into the Memory Data Register
(MOR Reg) •
To do this the ADK chip, when it decodes read
function and no forced CM!, will steer the cache data to the
DBUS by using DBUS S0, SI (SI ANDed with fact no write
vector occurred) to give us Sl/0 S0/l (1 = High) selecting
the MOR (Reg) to CLK in data from DBUS output of rotator.
The D Bus rotator used inputs from CAK chip which said no
rotation or DBUS Sel S0, SI = Sl/0 S0/0 (1 = High).
The microword has now performed the function of read memory
at address 1000 and stores data in MOR. What you just read
was the functionality and signals needed to accomplish this
bus cycle. The timing is shown on attached sheet.
Basic Read Cache Miss, TB Off
Microword at Address 10E:
OS.READ - READ EXIT:
READ SIZE [IDEP]
IRDx[l]
Bus Fune =

Read Memory from Address
In VA. SIZE = DSIZE
EX:VA = 1000 Size=Longword

Read, Meaning
Memory read from VA and
DSIZE from define file and placed into MOR.

WCNTL

From define file - No Op

MSRC

From define file - Default microtrap

What must be done in this example is to read data from
address in VA and store it in MOR.
This is the same as a
cache hit in overall functionality but the data comes from
main memory and not cache.
Also, we must write data from
1000 back to cache when received from memory.
Following the microword through the MIC block diagram, we
will find how the address is sent to main memory and data
received and stored into MOR and cache.
Five of the control chips (not microtrap) monitored the bus
function and checked to see if any other functions, that may
be using the needed paths are being performed, that is,
pre fetch, cache invalidate due to snapshot.
If all paths
that are needed are available we will continue and start a
bus cycle within the MIC module.

14-32

Execution Buffer

We must take the address from the VA Register (1000) through
the memory address latch on the ADD chip to the memory
address lines (MAD).
To do this the PRK chip has decoded
the read function using VA and sets MA SEL 50, Sl to Sl/l
50/l (1 = High) allowing VA through MA Latch to MAD.
With the address now on MAD we must get the address to the
PAD via the PA MUX.
The ADK chip also decoded the read
function and memory management disabled to set the AMUX SEL
lines 50, Sl to Sl/l 50/0 (1 = High).
This allows bits
<2·3: 02> to pass to the PRO 1 ines.
Bote
Bi ts <01: 00>
longwords.

not

used

only

Address bits <23:02> are being fed to cache and written to
the CMI address register.
The cache is checked and no hit
is recorded.
The address is also being latched into CMI
address register when "Add Reg Ena. L" comes from CMK chip.
This says start MIC module bus cycle.
THe fact that no hit signal was received from cache causes
the CAK chip to not send ENA bytes to cache which would
enable cache to output data.
The fact that no hit signal goes to the CMK chip allows the
CMK to arbitrate for CMI bus and send "ENA CMI L" to the MOR
chip when bus won.
This signal will be used to pass the
address in CMI Address Reg (1000) to be sent onto the CMI
bus <23:02>. At the same time the CMK chip is going to send
out the remaining functions needed to read from the address
(1000) in main memory, i.e., function of read on lines
<27:25> 000 and byte mask on lines <31:28> 1111. Also sets
DBBZ on CMI.
The CMK diagnostic DBBZ and memory asserts
DBBZ and sends needed data from 1000. When memory has data
and status on lines (CMI lines) the memory diagnostics DBBZ.
This tells CMK chip to monitor "status line <01:00>" for
possible error. Assume no error. The data on the CMI lines
are received by MOR chip.
At this point the ADK chip has passed the time to where
cache -> DBUS was needed and asserts the DBUS Sel lines 50,
Sl to Sl/0 50/l (1 = High) which selects data from CMI onto
the DBUS.
The ADK also knows that the data that is on the
DBUS must be latched into MDR (Reg). So it

14-33

Execution Buffer

generates CLK Sel S0, Sl to Sl/l S0/l (l = High) to perform
this.
Also -because the MDR was selected and CMI data was
selected to the DBUS the WMUX steers the data from the DBUS
into the WDR {used to store data to be written to cache).
The basic function of retrieving data from 1000 is complete,
but we must store that data into cache.
We still have the
address in· the CM! register and the data is in the WDR.
Let's do it!
The CMK chip monitored the status lines <l: 0> and found
status valid and outputs that signal to the control chips.
When the CAK chip sees the data is correct by receiving
status valid, it says cache GR 0 WR EN to allow cache to be
written.
To have the cache written to we need to get the
address through the PA MUX and data from WNR.
Data is easy
because as long as D Bus Sel does not have cache selected to
D Bus the drivers are driving the data from WDR to cache.
Because "Add Reg L" is now High from CMK and no other
function is needed in the ADK chip, the ADK outputs AMUX Sel
to select CM! address register and the drivers pass the CM!
address (1000) to cache to be used with cache GR0 and data
to write into cache the data retrieved from memory. Now all
the functions of a read with cache miss are complete and
another microword may be worked on.
The basic timing is on
attached sheet.
Thi rd Microword
One way or the other we now have the data, from the address
that was stored in Rl, latched into the MDR (Reg).
The
third microword now must do two things:

Store data that is to be written into a Q Reg.

Load address from GPRt2 to VA Reg. in ADD chip.

OS.WRT2 158
(RN )
Reg i s t e r
mode
differed. GPR (RNUM) is
operand
address.
Put
garbage in M Temp 0.

Q_M[MDR] VA_R[CDR.R]
CLOBBER MTEMP0 DEF
IRDX [ 1]
Decoded MSRC Field

= 12 or MBUS <- MDR

= 25 or VA <- WBUS
Decoded Bus Function = 7 or No Op

Decoded WCNTL

14-34

Execution Buffer

As you can see, this function is very similar to the first
microword.
It uses the same signals and paths to perform
the function.
All we are doing is setting up to perform a
write from address in VA instead of a read.
With Microword OEE
IL.MOV.B.W.L.MEM (also used
for MOVA)
R[DST.R].Size Q Q D, Write not
Reg, Size [IDep] ,~COOP2, IRDl

Write data stored in
Q to address in VA.
(Ex: VA = 2000)

to
memory
(and
Bus function decode = lA or - Write
cache) if register mode
not decoded.
If register
mode is decoded MIC will
not do anything, the DPM
mode takes data from Q
register to R2.
In case
Reg mode not decoded start
"bus cycle"
for write
using
address
in
VA
register.
WCNTL = 2E or

Data from WBUS -> WDR
rotated
for
longword
alignment.

MSRC = 0 or

M Temp 0 -> MBUS (no
function for this macro) •

We will say code is enabled and a hit is recorded.
That
means the data to be written will be written to cache and
main memory.
Following the microword through the MIC block diagram we
find we have to worry about transferring data and an address
at the same time.
Five of the six control chips (not microtrap) monitor the
bus function which will be used to open paths for the
address and help start the CM! write function.
All chips
monitor the WCNTL lines and then in effect will open paths
for the data to be transferred.
For ease of understanding we will take the address from VA
to CM! address latch and then bring the data from WBUS to
WDR even though it is happening at the same time.

14-35

Execution Buffer

We take the address from VA (address originally in R2)
through MA MUX of ADD chip by PRK chip decoding a write and
setting the MA Sel lines Sl, S0 to Sl/l S0/l (1 = High)
allowing the contents of VA to pass through to MAD bits.
We must now get address from MAD to the physical address
(PAD) lines to be sent to cache and CMI address register.,
Only bits <23:02> go to the PAD.
To do this the ADK chip
also decoded the write and ORed the fact memory management
was disabled to set the AMUX Sel lines Sl, S0 to Sl/l 50/0
(1 = High).
This allows bits <23:02> to be passed to the
PAD to be sent to cache and check for hit and be received at
the CMI address register.
When the CMK chip decoded bus
function and determined that no other function was needed,
the same path bit (CMK) asserted "ADD REG ENA L" to start
"bus cycle" and latch address into the CMI address register.
To get the data to the WDR register we must take it from
WBU5 through the DBU5 rotator through WDR MUX.
The ADK chip which selected MAD -> PAD also selected the
WBUS to DBU5 by outputting DBUS Sel 51, 50 to 51/l 50/0 (1 =
High).
While this is being performed the CAK chip selected
the DBUS rotator to pass the bytes through as they were 3,
2, 1, 0 by writing DBUS ROT 51, 50 to Sl/0 80/0 (1 = High).
Internally to the MOR chip because CMI data to DBU5 was not
selected, DBUS ROT was steered through the WDR MUX.
When
the ADK selected MAD -> PAD and WBUS -> DBUS it also was
setting CLK Sel Line Sl, S0 to Sl/l 50/1 (1 = High) to latch
data from WDR MUX into WDR on first L -> H transition of B
CLK.
The point at which we are now, data in WDR and address in
CM! takes one microcycle (two B CLKs). We must now write to
memory and to cache.
What would happen when the next
microword wanted to use some portion of the MIC that we
still must use? Well, since we set "Add Reg Ena L" and have
not received "status valid" we are still in a MIC module
"bus cycle" and if the control chips noted the next
microword wanted the paths needed it would stall the
processor.
Stalling the microcode will be covered later.
We will assume the MIC is not needed so a stall will not
occur.
With data and address where we want it we will send the
address and function/byte mask onto the CM! at the same time
we write data to cache because of the bit we received.

14-36

Execution Buffer

We will discuss the CM! function first.
When the CMK chip
first decoded a write to memory it knew it would have to
generate a "CM! Bus Cycle" (the CM! bus cycle may be a part
of MIC module bus cycle) so it would monitor the signal
input "CM! CPU PR! L". When this occurs and data address is
set the CMI would assert DBBZ to the CM! along with write
function bits <27:25> and byte mask bits <31:28> to the
proper values at the L -> H transition of B CLK.
At the
same L -> H transition of B CLK and ENI CM! from CMK the MDR
drives the output of CMI address register to CMI. All those
signals stay asserted until the next L -> H transition of B
CLK.
At this time CMK deasserts DBBZ and the WDR (data to
be written) is asserted on CM!.
The memory controller will
assert DBBZ if not able to write at this time and deassert
DBBZ and send status when it is able.
It is also possible
that the controller was able to write the data immediately
upon receiving it and not assert DBBZ but assert status.
Whichever happens the chopping of DBBZ causes the CMK chip
to stop sending "ENA CM! L" to MDR chips and monitor the
status line on CM!.
With status valid received we end the
MIC module "bus cycle" and allow the microcode to continue
if it was stalled.
While the above was happening we were also writing the data
to cache at the address specified from CM! address register.
We did this by using the same signals that we need on a
cache read miss, but they were generated by the decode of a
write bus function and a cache bit.
We have read about reads and writes with cache off and on,
yet we have not mentioned the translation buffer (TB) • What
is it and what does it do?
It is used to store translated
addresses for the use of the system.
Page frame numbers of
virtual addresses are used to search for page table entries
stored in TB tag on 1.
These PTEs if found may use the
virtual address to source a physical address onto the
physical address (PAD) lines to be used in the same way a
physical address was used to reads or writes previously
mentioned.
The main difference between virtual address and the use of
microcoded read physical, write physical or using VA and PC
with memory management off is where the address goes when
leaving the MA Latch.
The major difference comes from the ADK chip and MDR chip.
Normally with memory management off the address flows (bits
<31: 00>) through the MA Latch and all bi ts except <01: 00>
are passed through the AMUX on MDR to physical address MUX.

14-37

Execution Buffer

READ or WRITE with Memory Management Enabled
Translation buffer (TB) is enabled when memory management
bit set in physical/virtual address register = S/C Reg 0 in
ADK chip.
Microcode sets bit in S/C Reg 0 due to VAX
instruction MTPR #38 the tl.
With this bit set and bus function
physical the TB is enabled to output:
1.

Address onto PAD bits <23:09>

Da t a and tag
violations

Hit or miss

po i n ts

e r r or s

not

read

a nd

access

write

cont r o 1

If mm was not enabled or read or write physical was decoded
and mm was enabled you would still address the TB and check
for hit or miss but:
1.

Address would not be allowed to be outputted to PAD

Tag Parity errors and access violations would be
sent to ACV or microtrap chip but not used.
Data
parity not sent

Hit or miss would still be sent to microtrap chip
but not used because TB parity error not available.
(TB Parity ENA generated by mm enabled and no read
or write physical from ADK)

By looking at Figure ? let us take an example of one of the
microwords we have used previously.
Read with cache hit,
this time TB enabled
OS .RED .EXIT 10E
Read.Size [IDEP]
IRDx[l]

= Read

Read memory at VA size IOep

Memory read from VA and
and placed into MOR

OSIZE

What must be done is to take address from VA register.
this address to retrieve data and place data in MOR.

Use

Bus Function
WCNTL = No Op
MSRC

= Default M Temp 0

14-38

Execution Buffer

Five of the six control chips (not microtrap) monitor the
bus function and check to see if any other functions that
may be using the needed paths are being performed, i.e.,
pre fetch, snapshot CM!.
If no other functions are being
performed the control chips are free to start a MIC "bus
cycle".
·
We must first take the address from VA register in ADD chip
through MA MUX to MAD.
This is done by PRK having decoded
read bus function and setting MA Sel lines Sl, S0 Sl/l 50/l
(1 = High) allowing VA through MA Latch to MAD lines.
Now we have to go into parallel actions.
1.

Pass only bits <08:02> through AMux to PAD and

Check for TB to perform its function and put bi ts
<23:09> to PAD.

We will take the AMUX function first.
With ADK chip
decoding a Read function MM enabled the selection of AMUX
Sel Sl and S0 = Sl/0 S0/0 (0 = Low). This would normally be
seen as selecting the CMII address register to PAD bus.
But when used in conjunction with DBUS Sel lines only the MA
lines <8:00> are enabled and driven to PAD.
To do this the ADK chip has also selected DBUS Sel S0 Sl to
Sl/0 S0/0 say cache to DBUS.
When this happens along with
AMUX Sel Sl, S0 being Sl/0 S0/0, the AMUX passes whatever is
on MAD lines <08:02> to PAD.

14-39

Execution Buffer

This is a special function used in MDR for this case. At this
time of the microword DBUS Sel would be selecting cache to
DBUS normally. CMI ADD Reg would only be used through the AMUX
on a cache replacement if a miss or write to TB, which would
both involve no cache -> DBUS selection.
Now for the TB function that was happening at the same time.
As stated previously the address lines <31 and 15:09> always
feed the TB and generate a hit or no hit signal. When MM is
enabled (S/C Reg i0 in ADK) and a hit is recorded in the TB
tag store the signals TB "OUTPUT ENA L" and "TB PARITY ENA H"
are generated.
1.

"TB OUTPUT ENA L" is used to send to TB data store to
output the physical PFN onto the PAD lines. Also used
in TB on (MIC 16) to enable TB parity out.

TB parity enable is sent to microtrap chip to be ANDed
with hit (or lack of) so the microtrap chip will at
this time monitor to TB miss, data and tag, M bit,
parity errors and ACV from ACV chip.

If any of these conditions exist we leave the microinstruction
via a microtrap and proceed to the proper routine specified by
microvector lines <5:0>.
Lines <3:0> coming from microtrap
from microtrap chip and lines <5:4> from microsequencer chip.
If none of these conditions exist you continue the instruction
the exact same way as the read, cache hit TB off was
discussed.

14-40

VAX-11/750 LEVEL II

Unibus/Unibus Interface

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Unibus/Unibus Interface

Unibus/Unibus Interface
INTRODUCTION
The COMET Unibus Interface (CUI) serves three purposes.
It allows the processor to access registers on the Unibus,
it allows devices on the Unibus to perform DMA transfers
to COMET memory, and it allows Unibus devices to interrupt
the processor.
There are several characteristics of the VAX architecture
and the COMET memory system that require more than a
"straight-through" connection from the Unibus to the CMI.
Addresses that are contiguous in the virtual address space
may be discontiguous in the physical address space on 512
byte boundaries.
Since all Unibus NPR devices broadcast
sequential addresses, a means must be provided to break
these up into disjoint 512 byte blocks.
The VAX a r ch i t e c tu re i mpo s e s no res tr i c t i on s o n the
alignment of data in memory.
Unibus word transfer NPR
devices, however, only transfer word date on even
addresses.
The CUI provides a mechanism that allows the
t ran f s e r to be e ff e c t iv e 1 y s h i ft e d by one byte - to
accommodate requests for I/O buffers on odd byte
addresses.
·
The CMI has 24 address bits, the Unibus has 18. A method
is provided that allows a Unibus device access to all of
the CMI address space.
Finally, the CMI is four bytes wide, the Unibus is two
bytes wide.
Utilization of both CMI and Unibus can be
improved if each two sequential Unibus transfers are
compressed into a single CMI transfer.

15-1

Unibus/Unibus Interface

SYNOPSIS
This
module
contains
technical
information
concerning the characteristics and functions of the
Unbius and the Unibus interface.

OBJECTIVES
Given a True/False test, correctly determine if the
Unibus/UBI characteristics listed are true or false.
Given statements concerning the Unbius and Unibus
interface
functions,
and
several
possible
definitions for each, select the one correct
definition.

SAMPLE TEST ITEM
Identify the following statements as true or false.
a)
b)
c)
d)

The Unibus contains 56 lines.
The Unibus interfaces to the W Bus.
The Unibus buffered data paths hold 8 bytes.
The Unibus interface performs Unibus to CM!
address mapping.

RESOURCES
Comet Specification
Peripherals Handbook

15-2

Unibus/Unibus Interface

MODULE OUTLINE
XV.

Unibus/Unibus Interface
A.

Unibus structure
1.
2.
3.

41 data transfer lines
12 priority arbitration lines
Initialization lines

Unibus interface characteristics

Unibus memory & I/O space allocation
1.
2.
3.

Unibus to CMI address registers
1.
2.
3.

Minimum & Maximum addresses
Mapping example, unibus to CMI conversion
CMI address transfer

Unibus interface data paths
1.

2.
3.

6.
7.
8.
9.

CMI address space assigned to the UBI
Control and status registers
Diagnostic status registers

CPU write
CPU read
NPR DATI, DDP
NPR DATO, BDP to buffer
NPR DATO, DDP
NPR DATO, BDP write from buffer
Purge
Read the map
Write the map

Data posit ion ing
1.

2.
3.

Reads from memory, data buffering
Writes to memory, data buffering
Write to memory, byte offset

15-3

Unibus/Unibus Interface

Unibus microcode
1.
2.
3.
4.
5.
6.

Micro code flow charts
l.
2.
3.

First fork
DDP DATI
BDP DATO

Print familiarization
1.
2.
3.
4.
5.
6.
7.

28 bit word format
Field definitions
Micro code breakdown
Read code at address OFF
Read code at address OOF
Read code at address 000

Increment logic
Unibus address mux
Unibus data path chips
CUI map
UCN Chip
CUI control ROMS
CUI map decode

Summary

15-4

Unibus/Unibus Interface

UNIBUS SUMMARY
In the Comet system, the Unibus connects PDP-11 devices to
the Comet Unibus Interface (CUI) of the CP Cluster.
The 56
1 ines of the asynchronous Unibus can be divided into three
functional groups: priority arbitration, data transfer, and
initialization signals.
The 12 lines of the priority
arbitration group comprise those signals required for
selection of the next bus master while the current bus
master is still in control of the bus.
The 41 bidirectional 1 ines of the data transfer group are
used during data transfers to or from a slave device.
The
initialization group consists of the initialization and
power fail signals.
table 10-1 describes the bus signals
within each group.

15-5

Unibus/Unibus Interface

MHIOllY

AllllAY

CONTllOt.

r::___

__ ...

~--~~

l:.=J ~

Figure 15- J..
15-6

-----

5
6:
L
I
N
E

t:lj

~·!

......

t"'I

UNIBUS

INTERFACE

I
~

3
G
R

......

.
I

. I\.)

(1) INTR
(1) MSYN
(1) SSYN
. (2) PARITY *PA,PB
· (2) CONTROL CO,C1
(16) DATA
(18) ADDRESS

(1) BBSY
(1) SACK
(2) NON PROCESSOR (NPR~G)
(4) BUS-REO.(BR7-BR4)
(4) BUS GRANT (BG7-BG4)

41 DATA TRANSFER

12 PRIORITY ARBITRATION

u
s

c::

::s

.......

(1) INITIALIZE
(1) ACLO
(1) DCLO

en
c::

.........

3 INITIALIZATION

::s

.......
O"

::s
rt
CD
t"'I

*PA IS NOT USED

t-h

UNIBUS STRUCTURE

()

CD
TK-2066

DATA FLOW CONTROL SIGNALS
tTj
.....

Cl 8c CO

DATA IN (DATO: A DATA WORD OR BYTE TRANSFER INTO THE MASTER FROM THE SLAVE.

DATA IN PAUSE: (DATIP): SIMILAR TO DATI EXCEPT IT IS ALWAYS FOLLOWED BY A DATOB.

DATA OUT (DATO): A DATA WORD IS TRANFERRED FROM MASTER TO SLAVE.

DATA OUT BYTE (DATOB): SAME AS DATO EXCEPT A BYTE IS TRAN FEARED.

TRANSFER OPERATION

l.Q

.......
Ul

I
CX>

'CD""
........
Ul

c:::

::J

TK-2047

.....
O"

c(/)

'::Jc:::

.....

c(/)

Unibus/Unibus Interface

TRANSFER REQUESTS
There are two types of requests for control of the Unibus:
Non-Processor Request (NPR) and Bus Requests (BR).
The NPR
is used when a device requests a direct memory or device
access transfer (i.e., a transfer not requiring processor
intervention).
Normally, NPR transfers are used between a
mass storage device (e.g., disk) and memory.
A device
issues an NPR by asserting the NPR line; the processor (CUI
in the comet system) honors the request by asserting the
Non-Processor Grant (NPG) line.
The BR is used when a device interrupts the processor to
request service. This type of request is used to notify the
processor of an error condition or required transfer.
A
device issues a BR by asserting its assigned Br line
(BR7-BR4); the processor (CUI in Comet) honors the request
be asserting the corresponding Bus Grant (BG)
line
(BG7-BG4).
Request Priority
The device
follows:

structure

priority

structure

TYPE REQUEST

PRIORITY

NPR

HIGHEST

_A~

BR7
BR6
BRS

BR4

LOWEST

* IF TWO DEVICES ISSUE SIMULTANE0US
REQUESTS, BUS GRANT WILL GO TO THE
HIGHEST PRIORITY REQUEST.
BUS REQUEST PRIORITY

Figure 15-4

15-9

TK-2058

organized_ as

Unibus/Unibus Interface

The priority arbitration logic is structured such that if
two devices on different BR levels issue simultaneous
requests, the bus is granted to the device with the highest
priority.
The lowest priority device must keep its
requested asserted in order to gain control of the bus when
the highest priority device is finished (providing no other
higher priority device issues a BR).
Since there are only five priority levels, more than one
device may be assigned to a specific request level. If more
than one device makes a request at the same · level, the
device closest (electrically) to the processor has the
highest priority.
Priority Arbitration Sequence
Priority arbitration involves the signal sequence which
selects the next bus master.
The operation does not
actually transfer bus control but only selects the next bus
master.
The device requ1r1ng service asserts its BR (or NPR) line.
In practice, the Comet Unibus Interface May be receiving
several simultaneous BR signals..
These signals enter the
Unibus arbitration logic of the CUI.
If enabled by
software, the CUI then conducts a dialogue with the CPU and
asserts the corresponding BG (or NPR) line.
The grant is
propagated through each device on the asserted BG line. The
first device on the line having BR asserted acknowledges the
grant by asserting SACK, blocks the grant from following
devices, and clears its BR. The Unibus Adaptor responds to
SACK by clearing BG.
If SACK is not asserted by the
requesting device, BG is Ored with the other grant lines and
returned as a SACK signal to clear BG.
The device will keep SACK asserted until the current bus
master relinquishes the bus control by clearing its BBSY.
SACK asserted prevents other devices from gaining bus
control.
Once the current bus master has relinquished the
bus and negated BBSY, the requesting device asserts BBSY and
negates SACK, becoming the new bus master.
Priority
arbitration can be performed at the same time as the data
transaction of the servicing of an interrupt.
While one
device is using the bus, the arbitration logic is free to
monitor other requests and issue an appropriate grant.

15-10

Unibus/Unibus Interface

THE UNIBUS INTERFACE
•

~LLOWS THE PROCESSOR TO ACCESS REGISTERS ON THE UNIBUS

THE CMI HAS 24 ADDRESS BITS WHILE THE UNIBUS ONLY HAS 18. A METHOD IS USED THAT ALLOWS ANY
UNIBUS DEVICE ACCESS TO All OF THE CMI ADDRESS SPACE.

ALLOWS DEVICES ON THE UNIBUS TO PERFORM OMA TRJ'.:.;SFERS TO MAIN MEMORY.
THE CMI IS 4 BYTES WIDE WHflE THE UNIBUS IS ONLY 2 BYTES. TO MORE EFFICIENTlY UTILIZE THE CMI,
THE DATA IS MOVED ONTO THE CMI AFTER EACH PAIR OF UNIBUS TRANFERS.
THE UNIBUS MOVES DATA ON EVEN ADDRESS BOUNDRfES. TO BE ABLE TO ACCESSl/OBUFFERS ON ODD BYTE
ADDRESSES, A MECHANISM IS IN use THAT SHIFTS THE ADDRESS BY ONE BYTE.

•

ALLOWS UNIBUS DEVfCES TO INTERRUPT THE PROCESSOR.
TK-21Jso

Figure 15-5

15-11

Unibus/Unibus Interface

Table 15-1.

Unibus Signal Description

Signal

Description

Data Transfer Group
Address Lines
(A <17:00>)

These lines are used by
the
master
device
to
select the slave (actually
a unique memory or device
register address).
A<l7:01>
specifies
a
unique 16-bit word; A00
specifies a byte within
the word.

Data Lines (D<l5:00>)

-1 ine s
These
transfer
information between master
and slave.

Control (Cl, C0)

These siganls are coded by
the
master
device
to
control the slave in ·one
of the four possble data
transfer
operations
specified below.
Note
that
the
transfer
direction
is
always
designated with respect to
the master device.

*"""''-'- •14'.;... ,..'=' .... .._""'
C:::o o

is-12

11 ~ o

1 OI - "l

..i.u

Unibus/Unibus Interface

Table 15-1.

Unibus Signal De.script ion (Cont.)

Signal

Description

Control (Cl, C0)

TRANSER OPERATION
Data In (DAT!): a
data word or byte
transferred into
the master from
the slave.

Data Out (DATO):
a data word is
transferred out of
the master to -the
slave.

15-13

Data
In
Pause
(DATIP):
similar
to
DAT I
except
that it is always
followed
by
a
DATO/B to the same
location.

Data
Out
Byte
(DATOB)
identical to DATO
except a byte is
t r a n s f e r r e d
instead of a full
word.

Unibus/Unibus Interface

Table 15-1

Unibus Signal Description (cont.)

Signal

Description

Parity A-B (PA, PB)

These signals transfer
Unibus parity information.
PA is currently unused and
high.
PB, when true,
ind i ca te s a d ev ice parity
error.

Master Synchronization

MSYN is asserted by the
master to indicate to the
slave that val id address
and control information
(and data on a DATOB) is
present on the bus.

(MSYN)

Slave Synchronization

SSYN is asserted by the
slave. On a DATO it indicates that the slave has
1 atched the write data.
On a DATI /P it indicates
that
the
slave
has
asserted read data on the
Unibus.

(SSYN)

Interrupt (INTR)

This signal is asserted by
an interrupting device,
after
it
becomes
bus
master, ...... ,....v
inform
processor
that
an
interrupt
is
to
be
performed, and that the
interrupt
vector
is
present on the D 1 ines.
INT R i s
negated
u po n
receipt of the assertion
of SSYN by the processor
at
the
end
of
the
transaction.
INTR may be
asserted only by a device
which became MASTER by
receiving a BG signal.

15-14

Unibus/Unibus Interface

Table 15-1

Unibus Signal Description (cont.)

Signal

Description

Priority Arbitration Group
Bus Request (BR7-BR4)

These signals are used by
peripheral devices on the
Unibus and nexus on the
CMI to request control of
the bus for an interrupt
operation.

Bus Grant (BG7-BG4)

These
signals
form
processor's response to a
bus request.
Only one of
the four will be asserted
at any t ime •

Nonprocessor Request

This is a bus request from
a device for a transfer
not
requiring
CPU
intervention (i.e., direct
memory access).

(NPR)

This is the bus grant
response to an NPR.

Nonprocessor Grant

(NPG)
Select Acknowledge

SACK is asserted by a busrequesting device after
having received a grant.
Bus control passes to this
device when the current
bus master completes its
operation.

(SACK)

Bus Busy (BBSY)

BBSY indicates that the
data lines of the bus are
in use.

15-15

Unibus/Unibus Interface

Table 15-1

Unibus Signal Description (cont.)

Initialization Group
Initialize (!NIT)

This signal is asserted by
the terminator board (UET)
when DC LO is asserted on
the Unibus.
!NIT stays
asserted
for
10
ms
following the negation qf
DC LO.

AC Line Low (AC LO)

This signal initiates the
power fai 1 trap sequence,
and may also be issued in
peripheral
devices
to
terminate operations in
preparation
for
power
loss.

DC Line Low (DC LO)

This signal is available
from each system power
supply and remains clear
as long as all de voltages
are within the specified
limits.
If an out-ofvoltage condition occurs,
DC LO is asserted.

15-16

Unibus/Unibus Interface

ADDRESS SPACE
Any processor access with a physical address in the range of
FC0000 through FFFFFF will map directly on to the Unibus in
the range 0 through 777777 (octal).
Any device on the CMI
other than the processor that does a CM! transaction in that
address range will be ignored by the CUI. See Figure 10-7.
CUI ADDRESSES
The CUI is assigned a block of 8KB of CM! address space for
the map, CSR's and DSR's. See Figure 10-8.
CONTROL AND STATUS REGISTERS
Proper operation of transfers through the BDP' s requires
some intervention on the part of system software.
The use
of BDP's is not totally transparent.
When a device has
finished a series of transfers to CM! memory (DATO(B) 's), it
is possible that some data will remain in the buffer if the
transfer did not end on an even longword boundary.
It is
necessary for the software to initiate action that causes
this data to be written to memory.
When a device has
finished a transaction ·that involves DATl(P) 's, data is left
in the buffer with a corresponding Unibus address in the
address register. Should the cont~nts of the map be changed
at the location corresponding to the address in the address
register, there will no longer be the correct association
between address and data in the buffer.
It is therefore
necessary to clear the buffer following this class of
transactions. See Figure 10-9.
BDP SDR (Diagnostic Status Register)
This is a read only register that allows one to check the
flag bits associated with each BDP.
It is intended only for
possible diagnostic use and no reference to it is required
for normal use of the BDP's.
BITS <31:28>

BF3:BF0

BIT <27>

See Figure 15-1 0 •

15-18

Unibus/Unibus Interface

000000

MAIN
MEMORY
15360K

NONE-UN I BUS

EFFFFF
FOOOOO

ADDRESS SPACE
728K

UNIBUS 1/0 ADDRESSES
256K

FBFFFF
FCOOOO
FFFFFF

16384K

ADDRESS SPACE ALLOCATION
TK-2071

Figure 15-7

15-19

Unibus/Unibus Interface

F30000

CSR 1

BOP 1

CSR 2

BDP2

CSR 3

BDP3

MAP

.F31FFC
SK BYTE OF CMI ADDRESS SPACE
ASSIGNED TO THE UNIBUS INTERFACE
. TK-2068

Figure 15-8

15-20

BOP #1 F30004
#'2 F30008
#3 F3000C

BIT <O> PURGE. THIS BIT ALWAYS READS A ZERO. WRITING A ZERO TO IT
HAS NO AFFECT. WRITING A ONE TO IT PRODUCES A RESULT BASED ON THE
·coNTENTS OF THE BUFFER:
UNIBUS DATA:
CMI DATA:
EMPTY:
t':lj

......
lQ

.......
U1

c::
....,

.......

THE DATA IS WRITTEN TO THE CMI AND THE FLAGS
ARE SET TO MARK THE BUFFER EMPTY.
THE FLAGS ARE SET TO MARK THE BUFFER EMPTY.
NO ACTION OCCURS.

.._----·------------------------ucE
r-_,. . . . .__

BIT <29> UNCORRECTABLE ERROR (UCE). THIS BIT IS SET WHEN
UNCORRECTABLE &RROR STATUS IS RECEIVED FROM CMI MEMORY. PB IS
ASSERTED WITH THE DATA THAT IS PASSED BACK TO THE UNIBUS DEVICE ON THE
FIRST READ FROM THAT LOCATION. IT IS NOT ASSERTED ON SUBSEQUENT READS
FROM THIS BOP. THE BIT IS WRITE ONE TO CLEAR.

c
::J
......

'"-----------------------------NXM

r--------------------------,,,,,,,,,,,....------------------------------BIT <30> NON EXISTENT MEMORY (NXM). THIS BIT IS SET WHEN NXM STATUS
IS RECEIVED FROM THE CMI MEMORY. SSYN IS WITHHELD FROM THE UNIBUS
DEVICE. ALL FUTURE UNIBUS TRANSACTIONS THROUGH THIS BOP ARE IGNORED
(NO SSYN ISSUED) UNTILTHIS BIT IS CLEARED. THE BIT IS WRITE ONE TO
CLEAR.

c::

en
c
::J
......

.........

c::

en
H

""---------·----------------------ERR

::J
rt

CD
....,

BIT <31> ERROR. THIS BIT ON READ IS THE "ORu OF BITS 30 AND 29.
WRITING TO THIS BIT HAS NO EFFECT.

DI
0
CD

BOP CONTROL AND STATUS REG.
TK-1727

00
DSR #1 F30014
DSR #2 f 30018
DSR#3F3001C ....................._~------------------------------------------------------BYTE 0 VALID }
----BYTE 1 VALID
----BYTE2VALID
- - - - - B Y T E 3 VALID
NOTE 1:
tXj
.....

......
U1

I
N
N

THERE ARE FIVE FLAGS THAT KEEP TRACK OF THE DATA IN THE DATA
BUFFER, NAMED CD AND BF3 THROUGH BFO. IF CD= 1, THEN THE BUFFER

l.Q

c=
t"'(

READ ONLY DATA PATH STATUS

HAS FOUR BYTES OF DATA FROM THE CMI AND BF3 THROUGH BFO ARE
ALWAYS 0. IF CD= 0, THEN BF3 THROUGH BFO INDICATE WHICH BYTES

......
U1

IN THE DATA BUFFER HAVE VALID UNIBUS DATA. IF THEY ARE ALL o.

THEN THE BUFFER IS CONSIDERED EMPTY.

......

NOTE 2:

CUI DIAGNOSTIC STATUS REGISTER
TK-1726

Uni~us/Unibus

Interface

UNIBUS MAP
Unibus address bits <17: 9> are used to enter into a 512
location by 19 bit wide memory. The data coming out of that
memory is used to determine the details of how the
transaction is to be handled. The map data field is divided
into four sections. See Figure 10-llG
MAP SECTIONS
PFN
The PFN is a 15 bit field. On· Unibus initiated transactions
that cause a CMI read or write cycle to occur, the map PFN
is concatenated with Unibus address <8: 2> to form a 22 bit
longword address on the CMI.
DATA P~TH NUMBER
This two bit field is used to select one of the four data
paths.
Data paths 1, 2, 3 are called buffered data paths.
Data path 0 is called the direct data path.
OFFSET
When the offset bit is a 1, it causes the transaction to
behave as if the Unibus address supplied by the DMA device
was incremented by 1. This allows devices that only produce
even

byte

addresses

access

buffers

odd

byte

boundaries. A transaction that causes a word to cross page
boundaries because the offset bit is set must have data path
number, offset, and val id identical in both map entries.
Any differences will yield unpredictable results.
VALID BIT
When the valid bit is a 1, the CUI processes the
transaction.· When it is 0, the CUI ignores the receipt of
MSYN. The valid bit must be set to 0 for map entries that
correspond to sections of Unibus address space in which
there are slaves that are expected to respond to
transactions that originate on the Unibus.
Transactions
that start on the CMI and cause a Unibus transaction to
occur are always ignored by the CUI and can never wrap back
through the CUI onto the CMI.
15-23

Unibus/Unibus Interface

MAP ACCESS FROM THE CMI
The map is accessible for both reading and writing from the
CMI.
Each entry uses up a longword address or the CMI.
The
format of the map data fields as they appear on the CMI is
shown on Figure 10-11.
The logic that causes the map to be written ignores the byte
mask bits on the CMI.
It assumes that any write to the map
addresses is a longword write.
Any write other than a
longword will cause the contents of the map at the written
location to become unpredictable.
A Unibus initiated transaction that causes a CMI transaction
in the map address space on the CMI will properly address
the map and cause appropriate action.
Note, however, that
writing the map requires a longword write and the only way
that a Unibus device can cause a longword write is to do two
sequential transfers within a longword to a buffered data
path.
It is also a requirement that the buffered data path
not receive any other transfer in between the two that made
up the longword.
The CMI byte mask controls the setting of the Al, A0, ·and
{for writes) the C0 lines of the Unibus.
For reads the
setting is: See Figure 10-18.
Byte Mask

1111
1110
1100
1000

0
0
1
1

0
0
0
0

The processor will never produce any other values with reads
to the Unibus.
For writes:
Byte Mask

0001
0010
0100
1000
0011
1100

0
1

1
1
1
1

0
1
1
0
1
15-24

1
0
0

Unibus/Unibus Interface

The different types of CMI operations are mapped into Unibus
operations as follows:
CMI

UNIBUS

Read
Read with modify intent
Read lock
Write
Write unlock
Write vector

DATI
DAT IP
DATIP
DATO (B)
DATO ( B)
No Response

NOTE
( 1)
( 1)

( 2)
(2)
( 3)

When a CMI operation that causes a DATIP occurs, BBSY is
asserted and held until the end of the next operation
that does not cause a DATIP to occur.

The choice of DATO or DATOB is made based on the byte
mask.

The processor will never actually issue a write vector.

15-25

0
F30800TO {
F30FFC

·P

- PAGE FRAME NUMBER . CONCATENATED WITH BITS <8:2>
·OF THE UNIBUS ADDRESS TO FORM
THE 22 BIT CMI LONGWORD ADDRESS.

i~
lQ

........

....,

I .

.......,

U1
I

- DATA PATH NUMBER ------------------~---- USED TO SELECT 1OF4 DATA PATHS.

0 0 DIRECT DATA PATH
0 1 BUFFERED DATA PATH 1
1 0 BUFFERED DATA PATH 2
1 1 BUFFERED DATA PATH 3

.......
.......

c
......
O'
c:
CJ)

::1

. -BYTE OFFSET- - - - - - - - - - - - - - - - - - USED WHEN ADDRESSING ODD BYTE
BOUNDARIES.

'::1c

......
c:
CJ)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - V A L I D BIT IF NOT SET, TREAT CYCLE AS A NOP.

CMI MAP DATA FIELDS
TK-1739

Unibus/Unibus Interface

9 8

2 1 0

UNIB~S ADDRESS!...---(9_)_ _ _...l ___(7_)_ _...1_(2_)...1
BYTE
NUMBER

MAP INDEX

BYTE MASK BITS

PFN
ADDRESS MAP
RAM;512 X 1-9

2 1

cM1AooReSSl...______(1_s_)__________l _____(1_)____~l-(_2,~I
UNIBUS TO CMI ADDRESS TRANSLATION
TK-2068

Figure 15-12

15-27

2 1 0

loo olo oojo 1olo o1lo o1l1l1 ol
MAP (BOO·f FC)

0 0 0 0:1 1 1:0 0 111 1 0 1 0 0
I

1 o o 1:1 o op o 0:1 1 o o o 1
I

2 0 1 o:o 0 1:0 0 0~1 1 0 1 1 0
3 1 0 1:1 0 0:1 1 o:o 0 1 1 1 1

.......
lT1

N
00

(21066)

.......

4 1 0 011 0 110 1

lT1

.......

5 1
c::

::J

.....
O"

c:
Ul

CMI ADDRESS 0 1 0 0 t 0 1 0 0 I 0 1 1 0 : 1 1

(446C4C)

9 8

.........

c::

::l

.....

o oI 1 1

c:
Ul
H

:::J·

rt'

ro
'""'

UNIBUS ADDRESS (002116)

ti\

TK-20G2

Ill

Unibus/Unibus Interface

THE UNIBUS ADDRESS EQUALS <17:0> OF THE CMI ADDRESS
23

1817

ALWAYS All ONES 5
(UNIBUS SPACE)

HEX CMI ADDRESS

OCTAL UNIBUS
ADDRESS
TK-2048

Figure 15-14

15-29

Unibus/Unibus Interface

MINIMUM ADDRESS REQUIREMENTS FOR DIRECT TRANSLATION FROM
CMI ADDRESSES
TO
UNIBUS
ADDRESSES.
--· - ·-··.
-------·--··· ··-

+I H I I

1a111

1 1 1

1I11Io oI

HEX---F

OCTAL

oQ ooo

I 0

O I ·

o o!a o o! o o o
0

I 0

MAXIMUM UNIBUS ADDRESS AT UBI

++I+ I
.1al11.

Ix xx
HEX

I F

7 I

F I
7 I

I F ;
I 1 I

FI
7 I

OCTAL

1 ,

I F

MAXIMUM UNIBUS ADDRESS ON CMI
-~ 23

1al17

711 1 1 1I1 1I1! 111 11 +11+11+ 1 1I

HEX

OCTAL

F
1.

i 1·

I F
7

7
T~·2090

Figure 15-15

15-30

Unibus/Unibus Interface

HARDWARE COMPONENTS
DATA BUFFERS
Each BDP consists of a data storage buffer of 4 bytes. This
storage buffer can be loaded from the Unibus or the CMI, and
its contents can be output to either the Unibus or the CMI.
Data can be loaded into the buffer one or two bytes at a
time from the Unibus, but is always loaded 4 bytes at a time
from the CMI.
ADDRESS REGISTER
Each BDP has a sixteen bit address register that can be
loaded from either Unibus addresses <17:2> or <17:2> + 1 (if
offset is on). There is circuitry that compares the stored
address with the address on the Unibus to see if there is a
match.
The address held in the register is the Unibus
longword (Unibus Al 7:A2) corresponding to the data in the
data buffer.
FLAGS
There are five flags that keep track of the data in the data
buffer, named CD and BF3 through BF0.
If CD=l, then the
buffer has four bytes of data from the CMI and BF3 though
BF0 are always 0.
If DC=0, then, then BF3 through BF0
indicate which bytes in the data buffer have val id Unibus
data.
If they are all 0, then the buffer is considered
empty.

15-31

Unibus/Unibus Interface

XCVR

----- -,
UNBUF

BYTE SNAP

DATA LATCH

I
I
L---

A1.AO

----- -,
<A17:A2>

BYTE ROT.

AOORESS

ALIGN

BUFFER

3
BD,MUX

SACE.SI~

MUX

:2 i1

:0 T

BOPBUFS

AOORESS
COMPARE

: 3

CMIMUX

ACAR

BUF

CMI

c1.co

MUX

I
I
I
I
I
I
I
I
I
I

XCVR

UCN
FLAGSICMI
CUN/MASK

AOOAESS
MAP

512 x 19.

I
_
_.
-- ------

.•

UNIBUS INTERFACE BLK DIAGRAM

T1'·20H

Figure 15-16

15-32

Unibus/Unibus Interface

UCN SIGNALS
BUTO
BUT 1
BUT2
TIMEOUT
MSYN
SSYN
INT

- BUT LOGIC

UCR AO

---

UCR A2

CMI BYI_E
MASK

--...

INIT

...-

]UF CMI 28

-]UF CMI 29
...-

j3UF CMI 30

--...

--..
-

UCR A3

----

BCLK

UCR A1

---jlUF CMI 25

· jiUF CMI 31

CLOCKS
CMI
FUNCTION

__..

------

------..
--

--BUF CMI 26 -..
-

j3UF CMI 27

~UF CMI 0

--_co

ADDU

--- UNIBUS CONTROL

ADDC

..- CONTROL

__AO

----

f4.1

CSRA2
CSRA3
CSRA4
CSRA 11

HIGH

SLAVE

!=1

---...
--

--PB
-.OFFSET
--

---

sea

...

---------

SC 1

- CMICONTROL

_§TATUS 0
_sTATUS 1

-DBBZ

BYTE FLAG

-BLK ARB

---

--DP SELECT 1
DPSELECTO

ERR0_8___
BITS

PURGE

MAP CNTR EN

----

TK-2039

Figure 15-17

15-33

PYTE
MASK
l

PHYSICAL LONGWORD ADDRESS

.....

2t--~------T-rt:-1 1 1 1 -0 0

o o o 1 - o !o :,-

1 1 1 O;- 0 0 '.

0o1

1 1 0 0 - 1 O·

0100-101

0 1 0 -

1 0 0 0 - 1 0

1 0 0 0 - 1 1 ,,.

0 1 1 - NU

0011-000

1 0 0 - WRITE

1100-100

1 0 1 - WAITE UNLOCK

l"!j

l.Q

......

A1 AO

2 1

28 27
26 24 23
·FUNCTION
CODE

l"1

A1AOCO

o - o 11

(

0 0 0 -

READ

0 0 1 - READ ~OCK

Cl>

......

......
00

..,,
READ

READ W/MOD,FY INT

c::

::s.....
O'

WAITE

1 1 0 - WAITE VECTOR

.........

1 1 1 - NU

.....

c:::
::s

c
en

CMIADDRESSTRANSFER
TK-2067

Unibus/Unibus Interface

().

6 1UI

J lua DATA

XCVR

XCVA

•roo,-,., ...

I
I
I
I

- - - - ·-

r-- 1

INC
I [ ADDER

- - -

A1,AO

C1.CO
~

-- - - - -

L~MUX

ADO. "\.
_\.

<A17:A2>I
ADDRESS
BUFFER
1981TS

SRCE.SE~

COMPARE

3
~

] ~1

XCVR

I.
I

1
UCN

I <1;:9>1 j_,____
t
I
ADO RESS
MAP
.
I
s12 x 19

ADDRESS

3 :2 :, :0 1
80P8UFS : 2

Fl..AGS/CMI
CUN/MASK

MUX

...,__,...)

•

---------.

I ~ MUX I
L \.

BYTE ROT.
ALIGN

BDPMUX

DATA LATCH

UNIUF

IYTE MAP

I
I
I
I

I~
I
I

ADDRESS
<17:2>

I~
I

<8:2> f<:23:9~ <14:0> <31 :25>

CMIMUX

~, -.zt_,

RCAA

l
iiUF
CMI

~ MUX
---.~~----------------v·~

''
---- '--- -------- CMt

I
I
_

UNIBUS INTERFACE ILK DIAGRAM

TS.·2011

Figure 15-19

15-35

Unibus/Unibus Interface

TYPES OF TRANSACTIONS
The table below indicates what type of
initiated as a result of a Unibus cycle.

CMI

function

UN I BUS C1, C0

CM! FUNCTION

DAT!
DATIP
DATO ( B)

Read
Read Lock
Write or write unlock

If a DATO(B) follows a DATIP, then a write lock will go out
on the CM!, otherwise an ordinary write will occur.
STATUS
CM! STATUS

CUI RESPONSE TO UNIBUS

No error, or corrected data

SSYN issued

NXM

SSYN withheld

Uncorrectable Error

PB asserted with SSYN

OFFSET
If the offset bit in the map is set, then the transaction
will be treated as if the Unibus address were incremented by
1.
Note that if this is a DATI (P) or a DATO and if Al=l,
two CMI cycles will occur since the two bytes of Unibs data
fall across a longword boundary.
BUFFERED DATA PATHS
When the data path section of the map has a value of 1, 2,
or 3, then a buffered data path has been selected.
Each of
the three BDPs consists of four bytes of data storage, 16
bits of address storage, five flag bits, and logic to make
the BOP operate. The general intent of the BOP is that when
the Unibus transactions are occurring with sequential
addresses (either ascending or descending), only one CMI
transfer is needed for every two Unibus transfers.

15-36

Unibus/Unibus Interface

DIRECT DATA PATH
When the data path bits in the map specify 0, the
transaction is said to use the direct data path (DDP). This
means that SSYN is not issued by the CUI until the CMI
transaction corresponding to the UNIBUS has been completed.
DATI(P) WITH BYTE OFFSET
When byte offset is asserted out of the map, the behavior
depends on whether or not it causes this transaction to wrap
around across a longword boundary.
If it doesn't (Unibus
Al=0) then the data is shifted one byte to the left.
If it
wraps (Al=l) the CUI effectively acts as if two sequential
transfers occur, the first at the given Unibus address, the
second at the address incremented.
The two CM! reads are
pieced together to form the Unibus data word and SSYN is
issued.
The data buffer and address register hold the
information from the second read at the end of the
transaction.
DATO(B) BEHAVIOR
The CUI behavior on Unibus DATO(B) 's is primarily dependent
on the contents of the buffer.
Buffer has Unibus data, no address match.
The data in the buffer is written out on the CMI, and the
flags are set to mark the buffer empty.
Buffer is empty or has CMI data.
The Unibus data is put in the data buffer, the Unibus
address is put in the address register, the flags are set to
indicate the appropriate Unibus data and SSYN is issued.
Buffer has Unibus data, address match.
If the data on the Unibus combined with the data in the
buffer forms a full four byte longword, then a CM! write is
performed, the buffer is marked as empty, and SSYN is
issued.
If a ful 1 longword is not formed, then the Unibus
data is put in the buffer and the flags are set.
SSYN is
asserted.

15-37

Unibus/Unibus Interface

DATO WITH BYTE OFFSET
If this wraps across a longword boundary, it is treated as
two one byte writes.
If it does not cross a boundary, it is
handled the same as DATO.
DATOB WITH BYTE OFFSET
If Al A0=11, this is handled the same as with the address
effectively incremented by 1.
If Al A0 = 11, then it is
treated as if it were a DATOB in the ne·xt longword with Al
A0 = 00, except that address match is forced to no match.

15-38

Unibus/Unibus Interface

WRITE;
A B C D TO ADDRESS FCOOOO
AND
1 2 3 4 TO ADDRESS FC0002

I l

1
4

Ur.l_l_EtVS

1
A1 B

CMI

! B Ic ! D

C I D
j

ADDRESS

_J_

I
I

_J_

READ;
ADDRESS FCOOOO

UN.IBUS

Al B

ADDRESS
2

CMI

I!
A

C I D

I
I

__[_

__l

i I
D

4
0

Ic !

D
I

LcPu uses THIS WORD
ADDRESS FC0002

CM1l__1_.__2_l.__3_..!_4__.l__1_._j_2--'"l__3_,__4_.
\

LcPu uses THIS WORD
DATA POSITIONING
TK-2053

Figure 15-20

15-39

Unibus/Unibus Interface

BUFFER 1ST DATO
B

BUFFER 2ND DATO

I lc I

B 1 A

BUFFER FULL
DO A CMI WRITE

D • c

BUFFER 3 RD DATO

I !. I

'"7
"7
.•

-.I

F' : E

- I•
I

1I
I

•

I
I

THATS ALL FOLKS,
PURGE
DO A CMI WRITE

•I

•

.•

UNIBUS
DATA

CMI
ADDRESS

0
2

A
-

-1.

-WRITE TO MEMORY
WITH DATA BUFFERINGTK-2056

Figure 15-21

15-40

Unibus/Unibus Interface
-DO A CMI READBUFFER 1ST DATI

I
I

-;N

IJ! 1 IH!GI

I
I

·x

I
I

I
_l_

UNIBUS DATA HG

-DO A CMI READBUFFER 3RD DATI

IN!MI

L! Kl

BUFFER 2ND DATI

IJlllH>I

••
•

UNIBUS DATA L K

BUFFERf4TH DATI

IN!MI L

UNIBUS DATA

·-

----

----- .

DEVICE REQUESTS 4 WORDS FROM CMI MEM LOCATIONS 0,2,4,6.
·-

-READS FROM MEMORY
WITH DATA BUFFERINGTK-2054

Figure 15-22

15-41

Unibus/Unibus Interface

UNIBUS ADDRESS

UNIBUS DATA
BA
DC
FE

0
2

+
+

OFFSET ON

CMIMEMORY
t

c r B

'.Q

8
-BYTE OFFSETTK-2055

Figure 15-23

15-42

CUI MICROWORD
23 22

(BUF CMI)

BUFFERED CMJ

~·

(NEXT)

NE)~T ADDRESS

...,c

(BDPC)

BUFFERED DATA PATH CONTROL

(PRTC)

PORT CONTROL

l'1j

.._....

'°

(1)

I
.i:::i.

.._....
U1

(VA.CTRL)

16 15

13 12

10 9

...l.

8 7 6 5 4 3 2

~..J

UNIBUS ADDRESS CONTROL

l\.)

.i:::i.

(MSYN)

MJ\STER SYNC

(SSYN)

SLAVE SYNC

c
::s

(UiJDATA)

UNIBUS DAiA CONTROL

(CMl..A.RB)

CMI AAIBITRATION

'::sc::

(BUTj

~·

c{/)

BRANCH UNDER TEST

~·

TK-3417

Ul
H

::s

(1)

l"'1

OJ
0
(1)

MICROCODE BREAKDOWN
----~~~~~-----ROM

- - - - - - - - W O R D RESIDENT ADDRESS
- - - - - H E X CODED MICROWORD
--CODE LINE NUMBER
CONDITIONS

l'Jj

......
c

.......

1-1

I
.i::..
.i::..

.......
U1

I
N
U1

~131

;132
;133
;134
;135
;136
;137.

=000
MAIN

;THIS IS THE TOP OF FIRST FORK

;0000---------;
BUT/CLK. FLAGS,
BDPC/DATOB,

~EXT/BDP.DATq

. . .....

1------'

\;BOP DATOB; CMI WRITE

LINE COMMENTS

-------------FUNCTION
- - - - - - - - - - - - - - - - - - R O U T I N E NAME
------------------------------------------CONSTRAINT
TK-2084

c::

::l

......
c
O"

'c::
::l

......
c
O"

CUI MICROWORD
23 22

16 15

13 12

10 9 8 7 6 5 4 3 2

"POWER UP" CODE OF02,20
(BUF CMI)

BUFFERED CMJ

(NEXT)

NEXT ADDRESS

t'%j

(BDPC)

BUFFERED DATA PATI~ CONTROL

l.Q

(PRTC)

PORl" CONTROL

.....

c.::

......

l"1

l11

Ci>

......

l11

I
r-,.)

°'

(VA.CTRL)

UNIBUS ADDRESS CONTROL

(MSYN)

MASTER SYNC

(SSYN)

SLAVE SYNC

(UBDATA)

UNIBUS DATA CONTROL

(CMl.ARB)

CMI ARBITRATION

(BUT)

c:::

::s
.....
O"

BRANCH UNDER TEST

c.::
en

'c:::::s

UNIBUS DATA X:CVRS = RCV
UNIBUS ADDRESS XCVRS = RCV
NEXT=OOF

.....

c.::
en

TK-2082
H

::J
rt
Ci>
l"'1

HI
llJ

0
C1)

CUI MICROWORD
16 16

00000000

ADDRESS OF , IDLE 0002,27

tr.I

......

\.Q

t'1

(BUF CMI)

BUFFERED CMJ

(NEXT)

NEXT ADDRESS

(BDPC)

BUFFERED DATA PATH CONTROL

(PRTC)

PORT CONTROL

(VA.CTRL)

13 12

8765

432

UNIBUS ADDRESS CONTROL

(MSYN)

MASTER SYNC

(SSYN)

SLAVE SYNC

.........

I
N
....J

(UBDATA)
(CM I.ARB)
(BUT)

UNIBUSDATACONTROL--~~--~----~~----~------------------

CMl ARBITRATION------------------~~------~------~-----
BRANCH UNDER TEST--------------------~~~~--------------------

c::
::s......
O"

Ul
..........

UNIBUS DATA XCVRS= RCV
UNIBUS ADDRESS XCVRS = RCV
NEXT=OOO
BUT= FIRST FORK

c::
......

::s

Tl<-2085

Unibus/Unibus Interface

OFF

OOF
PWR UP

IDLE

ooo+

OOF

OOE

•

000

DDP DATOB
OFFSET

I
PURGE

OOA

ooc

OOB

DDP
DATl(P)

PURGE

]_
008

009

DDP
DATO(B)

006
BOP DATOB
OFFSET

005

CPU READ

007
BOP DATI
NO DATA
AVAIL

CPU WRITE

004

003
BOP DATI
WRAP

BOP DATI
0-AVAIL

BOP DATO
NO WRITE

1ST

002

001
BOP DATO
CMI WRITE
NEED

BOP DATOB
NO WRITE

FIRST FORK

000
BOP DATOB
CMI WRITE
NEED

FLOW,
Tl<-2076

Figure 15-28

15-47

Unibus/Unibus Interface
CPU READ

POWER UP

IDLE:

- - -

FIRST FORK
(CPU READ)

-ENABLE XCVRS TO RECEIVE &·Go TO IDLE.

-WAIT HERE FOR SOMETHING TO HAPPEN

- - - - -we HAVE IDENTIFIED A CPU READ OPERATION

-----,
I

IF SSYN IS GONE FROM LAST TRANSACTION,

START DESKEW. OTHERWISE WAIT.
UNIBUS DATA CONT IS SET TO RECEIVE.

'1-- ASSERT THE ADDRESS ONTO THE UNIBUS ANO

_ _ _ _ _ _J

CPU.RO

CPtJ.R0.10

--WASTE TIME FOR DESKEW (125n SEC)

-- --,
l

~-KEEP ADDRESS ON UNIBUS & DROP MSYN

CPU.RD.20

-- -

CPU.WRT.25

- -

ASSERT MSYN, {DATA ASSERTED) & WAIT
FOR SSYN. ONCE SSYN IS PRESENT
KEEP MSYN ASSERTED TO HOLD DATA ON
BUS.

ASSERT HI Z ON ADDRESS LINES TO
-PRESENT TRISTATE OVERLAP & GO BACK
TO IDLE & WAIT FOR NEXT TRANSACTION.

TK-2060

Figure 15-29
15-48

Unibus/Unibus Interface
BOP DATO SECOND PASS

POWER UP

IDLE

- -

- - - - - --ENABLE XCVRS TO RECEIVE & GO TO IDLE

- - - - - - - -WAIT HERE FOR SOMETHING TO HAPPEN

FIRST FORK
BDPDATO

- - - - -we HAVE IDENTIFIED A DATO USING THE
BUFFERED DATA PATH. PUT THE UNIBUS
DATA INTO THE BUFFER & CLOCK THE BYTE FLAGS.

BOP.DATO

- -

- - - - --ARBITRATE FOR THE CMI, PUT THE MAP PFN
& THE LOW ORDER ADDRESS BITS ON THE BUFFERED
CMI PATH. ENABLE ADDRESS TO CMI.

BOP.DATO.OS

BOP.OAT0.10

- -

BOP.OAT0.20

OOP.45

OOP.40

- - - -WON THE BUS, ASSERT DATA & CHECK
CMISTATUS

- -

- - -

WE HAVE NO WRAP, BUSY IS UP, GOOD ADDRESS.
KEEP THE DATA ON THE BUS UNTIL OBBZ
GOES AWAY,

- -

- - - WAITING FOR MSYN OR INTERRUPT TO GO
·AWAY BY CHECKING FOR SSYN. SSYN = 1

- - -SSYN • 0, ALL DONE. GO BACK TO
IOLE&WAIT.

- - DBBZ IS GONE' SO ASSERT SSYN

'T"l(-2061

Figure 15-30
15-49

. CPU WRITE TO UNIBUS

UBI

.UNIBUS DEVICE

rI -- ... ------,I

UNIBUS

I
tZj

......
c

l.Q

! ASSERTT UBSY@ (i)

1
I

INT

.....

I-'

w
I-'

I-'

()

I
U1

......

c::

...,~

......

rt
(1)

rt
0

c::
:J
......
O"
c

!
i

-- STATUS VALID
UNREQ

• &.

(1)

BACKPLANE

_.. i

·© '
.(i)

CMI

_ •i>BBZ _ ;Ci) ©
LINES <S> _@ ·FUNCTION
-- CONTROL.
ADDRESS LINES <B> -_@ADDRESS
=ADDRESS -(3) DATA ®
-- DATA
-<D> _@DATA
--- MSYN
/HOLD :<i) (j)
@ -..
- SLAVE SYNC
STATUS ;(I)
svr~c

c::
::s
......

,Ci) -

'c::s

......
c

TK-3889

Unibus/Unibus Interface

_Signal Explanation for CPU Write to UNIBUS
1.

The MIC Module decodes the address to be sent to
CMI.
If address is a Unibus address, the MIC sends
"un REQ" via the backplane to the UBI module.
(This
says arbitrate for the Unibus you have an address on
theh way) •

At this point, I'm saying the UBI arbitrated for the
bus and won, and is asserting bus busy.

The CPU via the MIC module asserts DBBZ on the CMI
along with the address and bus function of WRITE.
When UBI receives it, enables go out to drivers to
place address on Unibus.
C0 and Cl generated from
Function. NOT USED UNTIL SYNC IS SENT.

CPU drops DBBZ and UBI puts DBBZ on the 1 ine.
CPU
also sends data to be written on CMI.
DATA is
passed to Unibuss drivers that are enabled.
NOT
USED UNTIL MASTER SYNC SENT.

UBI sends Master SYNC and device should receive
Address, data and control signals. UBI sets hold on
CMI.

When slave sync is returned from the device, the UBI
drops Hold and returns status to CPU via CMI.

UBI drops BBSY on Unibus when
Valid" from MIC module.

15-52

receives

"Status

Unibus/Unibus Interface

DISK NPR XFER TO MEMORY, BOP EMPTY.

UNIBUS DEVICE

'MEMORY

UBI
BACKPLANE

UNIBUS
NPR

<D ®-

INT

__ NPG

.... --

··--

SACK'
-.

(3) @ -

BBSY
CO,CI

1e 8-ii-S-oATA @ @ :
··-ADDRESS
@) @ _
MASTER s'f'NC @ @ ~

....I @ @ WAIT ~ CMI (I}
l n-11- DBBZ @ @ ~
- I[ I I L ADDRESS @
-:
II (w8lfb
-~ ... ~ l
DATA (32 BITS) (j) -·
•st~ I
- SLAVE SYNC @ @I IDWOAD+ STATUS @
-

~---

a..+

A
p

-.Jr-

TK-3870

Figure 15-32

Disk NPR XFER to Memory BDP Empty

15-53

Unibus/Unibus Interface

Signal Explanation for Normal NPR Disk Transfer to Memory
Ground rules for this explanation.
A.
B.
C.

16 Data lines on Unibus, 32 on CMI
BUffer in CMI is empty
Starting at even address
1.

Disk sends NPR on Unibus.

UBI arbitrates and sends back NPG.

Disk receives NPG and sends SACK.
UBI asserts wait
when SACK received (not used here).

4•

When bus av a i 1 ab 1 e d is k a s s e r ts BBS Y, C 0 , C 1 ,
ADDRESS, data and master sync.
When UBI receives
this it stores the 16 bits of data in a buffered
data path because it is empty.
(It holds 32 bits or
4 bytes).
SACK is dropped to UBI so wait is dropped
on CM!.

Slave sync is sent to device from UBI.

Since Unibus cycle complete another NPR is sent.

NPG again sent in response by UBI.

SACK sent from disk and UBI again asserts wait.

When Unibus available disk again asserts BBSY, C0,
Cl, ADDRESS, Data and Master Sync. 16 bits of data
now stored in remaining section of buffer, and
address sent to map to get proper location in memory
to send data to.

10. UBI (when finished arbitrating for CMI) asserts DBBZ
and Address on CMI.
11. UBI drops DBBZ and Memory Controller puts it on CMI.
UBI asserts data (32 bits from BDP).
12. Status sent by controller to UBI, UBI clocks status
when DBBZ deasserted.
13. SLAVE SYNC sent to Device.

15-54

UNIBUS INTERRUPT TO CPU
UNIBUS DEVICE

tz:i
......
"°c

UNIBUS
BUS REQUEST

'"1

.......

BUS GRANT

i!2 -- -~
_ill_
@

SACK

lTI

ASSERT BUS BUSY

.......
I
lTI
lTI

c::
::s......
O"
c
{/)
H

::s

INTR

_..

f4--

-- 1
I

BACKPLANE

.-.;rr.-

l;e--...,
I

w
w

lTI

CPU

UBI

l VECTOR ADDRESS : -----'
VECTOR

SLAVE SYNC

+200

®_.

-.ENABLE BUS GRANT

-... @ INTGRANT

....____

. L--1SJ)_ ®

INTERRUPT PENDING

- .,~:[)Al~

CMI

_. . @} WAIT •@_ SJ2

..- I

UNIBUS DEVICE VECTOR+ 200i@ _..
WITH WRITE VECTOR FUNCTION

...

VECTOR +200
+SCBB

OUT TO MEMORY_..
VIACMI

VECTOR ADD OF
SUBROUTINE

c
......

l"1
l"1

::J

l'tj

{/)

rt
0

.........

c::
::s......

0
"O

c::

c{/)

Tt<-3428

Unibus/Unibus Interface

Signal Explanation for Unibus Interrupt to CPU
1.

BR generated by unibus device.
UBI Synchronizes BR
to M elk to get SBR signal.
SBR sent to Interrupt
chip.
The Interrupt chip checks SBR level (4, 5, 6, or 7)
which will give you the corresponding IPL level of
IPL 14, 15, 16, or 17.
This level is compared to
present IPL level and if SBR has a higher IPL then
two things take place.
A.

INT pending signal sent to
module

DPM module and

MIC

The Interrupt chip on UBI also generates u
vector lines 0, 1 and 2 to the state needed to
identify the type of interrupt pending.

Interrupt Pending sent by UBI to CPU modules DPM and
MIC is used to generate remaining vector lines 3, 4,
5 to give you the proper micro vector address that
starts the microroutine to handle the incoming
interrupt. Caution; INT pending is sent to SAC chip
on DPM while macro code i s running but wi l 1 not be
interpreted until IRDI of next instruction (macro).
when this time arrives THE SAC chip generates DO
service signal and Enable u vector to go to the MSQ
chip and generate bits 3, 4, and 5 to pull down the
porper bits for the address of the microvector.
When these signals are ored with bits 0, 1, 2 from
UBI module you have microaddress of the routine to
handle the interrupt that is pending from Unibus.

The microroutine starts at microaddress and the
first function is to send, via the WCNTL F.LA, A
"33" which says Enable sending Bus Grant to the Int.
chip on UBI.

The Int. chip (and associated logic) then sends the
appropriate bus grant on the Unibus AND also hands
INT grant back to the MIC module at the CMK chip.
The CMK gene rates "GRANT STALL" to st al 1 the
microcode before the next microaddress.
The CPU
MICROCODE REMAINS STALLED UNTIL THE VECTOR HAS BEEN
WRITTEN TO THE MIC Module.

15-56

Unibus/Unibus Interface

SACK is returned by the unibus device who issued the
BR in response to the BG. SACK will at this time in
the UBI module assert the "WAIT" line on the CMI.
This will go to the MIC Module and replace int grant
to hold the CPU stalled.
It will also drop BG in
the UBI.

6,7 When Unibus device that sent BR SEES Bus Busy on the
Unibus dropped by previous device, he will assert
bus busy, INTR and vector address {on DATA lines)
all to be sent to the UBI module.
At this time,
INTR will replace SACK to keep the wait line pulled.
8.

The UBI module sends Unibus Device Vector plus 200
{by pulling address 1 ine 9 low) on the CMI with a
write vector function. This causes #9.

Slave sync is asserted on unibus because INTR and
write vector sent. When device receives Slave Sync,
INTR is dropped to UBI.

10. UBI no longer has INTR so the wait line is dropped
causing stall to be dropped and the microcode goes
to previously defined microaddress to handle
interrupt. The loss of wait line to CMK chip on Mic
is not the only way to install the machine. If the
CMK monitors a write vector function on the CMI and
sets the bit in write vector written register that
will also install machine by dropping Grant Stall.

15-57

FFF4601

IIII IIIII

I I I I I I

UNIBUS ADDRESS REG!STER

FFF4621~__..___.___.___..___l...._--.___.___.__.__. . .___..__.___..__.._--.j...__.
UNIBUS DATA REGISTER

•
UET CONTROL STATUS REGISTER

FFF464 INIT

BR7 BR6 BAS BR4

A17 A16

co NPR

BUS REQUEST
LEVEL SELECT -

UET
SSYN
TIME
OUT

ADDRESS
EXTENSION

GO
ISSUE
NPR

FORCE

ISSUE
UNIBUS
INIT

UNIBUS
PARITY
ERROR

UNIBUS
TRANSFER
SELECT

FFF4661____________z_E_R_o_______________________R_o_M_o_A_T_A__________,
TK~609

15-58

VAX 11/750 LEVEL II

Interrupts and Exceptions

Student Workbook

Course produced by Educational Services Department
of
Digital Equipment Corporation

Interrupts and Exceptions

INTRODUCTION
The interrupt circuit is a composite of both TTL and gate
array logic, with the center of attention focused on the INT
chip housed on the UBI module.
The INT chip uses signals from other chips on the UBI board
and signals originating on both the MIC module and the DPM
module with control coming from the control store module via
WCTRL.
The various signals are used to produce UNIBUS grants, U
Vectors to the control store, and by way of the W Bus, route
IPL data to and from the INT circuits.

16-1

Interrupts and Exceptions

INTERRUPTS AND EXCEPTIONS

MODULE XVI:
SYNOPSIS

This module consists of theory on interrupts and exception
handling utilizing block diagrams and microroutines.
OBJECTIVES
Utilizing the block diagram and the micro listing, trace the
operation of the stack and associated circuitry while
servicing each of the following:
a. traps
b. interrupts
c. exceptions
SAMPLE TEST ITEM
Which of the following is a typical example of an Exception?
a.
b.
c.
d.

A power failure.
The attempt to execute a privileged instruction.
A parity error.
An error detected on the Unibus.
RESOURCES

Processor Specifications

16-2

Interrupts and Exceptions

OUTLINE
XVI.

Interrupts and Exceptions
A.

Interrupt

Exception

Execution
of
Instructions

Privilged

Trace Traps

Compatability Mode Faults

Breakpoint Instruction Execution

Arithmetic Traps

3 Types of Exceptions
l.

Traps

Fault

Abort

Interrupt Priority Level

Vector

System Control Block Base Register

Interrupt Block Diagram

INT Chip

INT Chip Inputs

INT Chip Outputs

Interrupt Registers
1.

SPFIR

WEIR

16-3

Reserved

Interrupts and Exceptions

CPIR

CDIR

HSI PR

IPL

CURMODE

ASTLVL

Operations Performed
1.

Save and return values of parts of the PSL
and AST level via the W Bus.

Receiving and storing the value of the HSIPR
which is used in interrupt arbitration.

Placing various data onto the Micro Vector
lines.

Perform REI check calculations.

Arbitration of all interrupt requests,
encoding the highest priority pending
interrupt and generation of the interrupt
pending signal=

Unibus arbitration within the group of
devices and issuing of BGs.

Unibus ACLO/DCLO, initiate functions are
handed by the INT Chips associated TTL
circuits.

The generation of Micro sequencer INIT is
also
handled
by
the
associated
TTL
circuitry.

Unibus arbitration among
devices and the BR devices.

16-4

the

CMI,

NPR

Interrupts and Exceptions

HJ. Informing

the CMI

that it may talk to the

Unibus •.

11. Request Unibus number 2 via NPR.

Interrupt and Exception Microcode for a Unibus
INT
1.

I and E Mic, IE.UNIBUS.INT:

Address OFlA

Address OFlB

Address OFlC

Address OFlD

Address OFlE

Address OFlF

Address OF00

Summary

16-5

Interrupts and Exceptions

INTERRUPT AND EXCEPTIONS
•

INTERRUPT

An event other than an exception, branch,
j ump , ca s e , o r ca 11 i n s tr u c t ion th a t
changes the normal flow of instruction
execution.
Interrupts are generally
external to the process executing when
the interrupt occurs.

•

EXCEPTION

An even-t detected by hardware other than
an interrupt, jump, branch, case or cal 1
instruction that changes the normal flow
of instruction execution.
An exception
is always caused by the execution of an
instruction or set of instructions.
There are 3 types of exceptions.

TRAP

An exception conditions that occurs at
the end of the instruction that caused
the exception. The PC saved on the stack
is the address of the next instruction
that would normally have been executed.

•

FAULT

A condition that occurs in the middle of
an instruction that leaves the registers
and memory in a consistant state which
allows the instruction to restart and for
correct results once the fault has been
cleared or eliminated.

•

ABORT

An exception that occurs in the middle of
an instruction and leaves the registers
and memory in an indeterminate state
which
may
prohibit
an
instruction
restart.

Figure 16-1

16-6

Interrupts and Exceptions
- - ·-

----- ----

·-~-~-.

··- ----- -- - .. ·-- - -_.

VECTORS AND SYSTEM CONTROL BLOCK FORMAT·
VECTOR

DESCRlPTION

SCBB+O
SC88+4

NOT USED
MACHINE CHECK
CS PARITY
BAD IRD
MEMORY ERROR
CACHE PARITY
KERNEL STACK INVALID
POWER FAIL
RESERVED OPCODE
CUSTOMER OPCODE XFC
RESEVED OPERAND
RESERVED ADDRESS MODE
ACCESS VIOLATION
TRANSLATION INVALID
TRACE TRAP
BREAKPOINT OPCODE
COMPATABILITY MODE
ARITHMETIC TRAP

SCBB+8
SCBB+C
SCBB+10
SCBB+14
SCBB+18
SCBB+1C
SCBB+20
SCS8+24
SCBB+28
SCBB+2C
SCBB+lO
SCBB+34
SCBB+40
SCBB+44
SCBB+48
SCBB+4C
SCSB+54
SCBB+oo
SCBB+84
SCBB+88
SC88+8C
SCBB+90
SCBB+94
SCBB+98
SCB8+9C
SCBB+AO
SCBB+A4
SCBB+A8
SC BB+ AC
SCBB+BO
SCBB+B4
SCB8+88
SCBB+BC
SCBB+CO
SCBB+FO
SCBB+F4
SCBB+F8
SCBB+FC
SCBB+160
SCBB+164
SCBB+lb8
SCBB+200

IPL

IIE

lF
1E
1F
lF
1F
1F
1F
1 f'
lF
lF
1F

E
E

CH'4K

E
E

CHMU

1F
1A

CHME
CHMS

1F
1F' ~

CORRECTED READ DATA
WRITE BUS ERROR
10
SOFT INTERRUPT
1
SOFT INTERRUPT
2
SOFT INTERRUPT
3
SOFT INTERRUPT
4
5
SOFT INTERRUPT
6
SOFT INTERRUPT
SOFT INTERRUPT
7
SOFT INTERRUPT
8
SOFT INTERRUPT
9
A
SOFT INTERRUPT
B
SOFT INTERRUPT
c
SOFT INTERRUPT
D
SOFT INTERRUPT
SOFT INTERRUPT
E
SOFT INTERRUPT
F
INTERVAL TIMER
18
TU•58 RECEIVE
17
TU•58 TRANSMIT
17
CONSOLE RECEIVE
14
CONSOLE TRANSMIT
14
MASSBUS ADAPTOR 0
15
MASSBUS ADAPTOR 1
15
MASSBUS ADAPTOR 2
15
UNIBUS
14•17
CSCBB+200+UNIBUS VECTOR)

l
I
I
l
I
I
1
I

I
I
I

I
I
1·
I
I
I
I
I
I
I

I
I
I
I
TK-3273

Figure 16-2 Vector and System Control Block Format

16-7

Interrupts and Exceptions

INTERRUPT BLOCK DIAGRAM

r----T---I

CONTROL STORE

I- -

-- •
MIC

I
L

UTR

SBR5

WCTRL<5:0>

SBR6
SBR7
~

I
I CORR DATA INT
~M

IM CLK EN

SAC

D CLK EN
PHASE 1

....----

B CLK
TIM

TIMER INT

I PROC INIT
I SPFI

UB INT GRANT

MICRO VECTOR 1
MICRO VECTOR 0

MICRO VECTOR 2

__..

; ---

INT PEND

_..

HPBG4

-....
--

SYNCHR RESET BG

----

Interrupt Block Diagram

16-8

--..

HPBG 5

__..

L---

Figure 16-3

I ....

HPBG 6

L - - - - 1. SERIAL LINE INT
I

I
I

WBUS<26:22 & 20:16>

INT

DO SERVICE

I
I

I UVCTR BRAN ~

--(

J----i

,,-

--=>--

PTE CHK OR PROBE
WR BUS ERR INT
UT RAP

CMK

UB1------~;1

I
I

ACV

I
I
I

-•

__..

_..

I
I
I
I

_J
TIC:-3270

Interrupts and Exceptions
MICRO VECTOR VALUE CHART
IPL

NAME

U VECTOR

NO INTERRUPT REQUEST PRESENT

000

01-0F

(HSIPR) HIGHEST SOFTWARE
INTERRUPT PENDING
REQ.
- .

000

(SLINE INT) SERIAL
LINE INTERRUPT

. 001

14-17

(SB Rn) SYNCHRONOUS
BUS REQUEST (~7)

010

(TIMER INT) INTERVAL
TIMER INTERRUPT

011

(COIA) CORRECTED DATA
INTERRU?i: REQUEST

100

(CPIR) CACHE PARITY
ERROR INTERRUPT REQ.

101

(WEIR) WRITE BUS ERROR
INTERRUPT REQUEST

110

(SPFI R) SYNCHRONOUS
POWER FAIL INTERRUPT REQUEST

111

BRANCH ON MICROTEST MICRO TARGETS
38=SOFT INTERRUPT REQUEST
39=CONSOLE INTERRUPT REQUEST ·
3A=UNIBUS INTERRUPT REQUEST
3B=INTERVAL TIMER INTERRUPT
3C=CORR~CTED MEMORY DATA
3D=CACHE PARITY ERROR
3E=WRITE BUS ERROR
3F=POWER FAIL INTERRUPT
TK-3272

Figure 16-4

Microvector Value Chart

16-9

Interrupts and Exceptions

INT REGISTERS
NUMBER
OF BITS

NAME

IPL

COMMENTS

SPFIR

LATCH FOR SPFI

WEIR

LATCH FOR WEI

CPIR

LATCH FOR CPI

CDIR

LATCH FOR COi

HSIPR

01-0F

SOFTWARE INTERRUPTS

IPL

00-1 F

INTERRUPT PRIORITY
LEVEL

INTERRUPT STACK
FLAG

CURMODE

CURRENT MODE

ASTLVL

SOFT

ASYNCHRONOUS
SYSTEM TRAP
LEVEL

LUBIPR

14-17

LAST GRANTED UNIBUS IPR

PRVMODE

PREVIOUS MODE

1
TK-3271

Figure 16-5

Interrupt Registers

16-10

Interrupts and Exceptions

Interrupts and exceptions in some ways are alike in what
they accomplish within the machine. They also have their
differences. To understand the differences and how they both
function you must be able to answer two questions.
1. Why do interrupts and exceptions occur?
2. How does the machine get to the proper MICRO address
to handle interrupts and exceptions when they occur?
We' 11 attempt to answer these questions one at a time to
give you an idea how the machine handles interrupts and
exceptions.
1. Why do interrupts and exceptions occur?
When the machine is running normally it is executing one
MACRO instruction at a time. After completion of the MACRO
the machine goes to the execution buffer on the MIC to fetch
and execute another MACRO instruction. This is the normal
flow of operation. There are some MACRO instructions that
during their execution go to different areas of the program
and not the next MACRO instruction in the execution buffer;
such as jump, branch etc. These examples are still a normal
type flow to the machine. When a normal flow needs to be
changed either an interrupt of an exception occurs. IN ALL
CASES A MICRO ADDRESS IS GENERATED THAT POINTS TO A ROUTINE
TO HANDLE THE INTERRUPT OR EXCEPTION.
INTERRUPT - An event other than an exception, branch, jump,
case or call instruction that changes the normal flow of
instruction execution. Interrupts are generally external to
the process executing when the interrupt occurs.
EXAMPLE:
Interrupt from the console terminal.
EXCEPTION - An event detected by hardware other than an
interrupt, jump, branch, case or call instruction that
changes the normal flow of instruction execution. An
exception is ALWAYS caused by the execution of an
instruction or set of instructions. There are three types of
exceptions.
A. An exception condition that occurs at the end of the
instruction that caused the exception. The PC saved on the
stack is the address of the next instruction that would
normally be executed. EXAMPLE: Arithmetic Trap
B. Fault - A condition that occurs in
instruction that leaves the registers

16-11

the middle of an
and memory in a

Interrupts and Exceptions

constant state which allows the instruction to restart and
for correct results once the fault has been cleared or
eliminated. EXAMPLE: Translation Buffer Miss
C. Abort - An exception that occurs in the middle of an
instruction and leaves the registers and memory in an
indeterminate state which may prohibit an- instruction
restart. EXAMPLE: Kernel stack invalid.
These are the reasons that interrupts and exceptions occur.
The second and maybe the most important question is:
2.

How does the machine get to the proper MICRO address to
handle the interrupts and exceptions when they occur?

To figure this out let us redefine some terms previously
explained. Look in the micro-code listings in the chart file
for the FIXED CONTROL STORE ADDRESS CHART. You should note
that these addresses are broken down into three sections;
lX, 2X and 3X. These sections relate to the MICRO addresses
that all interrupts and exceptions go to when handling the
events other than the normal flows within the machine. If
there are three types of exceptions along with interrupts
why aren't there four sections? The answer lies in
terminology.
An interrupt is an interrupt and all of them start at MICRO
addresses beginning with 3(X).
Exceptions are where the ambiguous statements begin.
TRAP is an exception,
generated will always go

explained previously, that when
to MICRO addresses beg inning at

1 (X) •

This leaves two types of exceptions that relate to one group
FIXED CONTROL STORE ADDRESSES. The exceptions fault and
abort, explained previously, are both classified as MICRO
TRAPS in the FIXED CONTROL STORE ADDRESS CHART. Using these
redefined terms for faults and aborts they will now both be
discussed as MICRO TRAPS from now on.
Looking at the redefined terms what follows is a brief
overview of what happens at the time an interrupt, trap or
micro trap occurs. Knowledge of the Micro Sequencer Chip
(MSQ) from the manual or class is assumed.

16-12

Interrupts and Exceptions

After the execution of each macro-instruction, a test must
be made to see if there are any traps or pending interrupts
to be serviced. This test is called BUT SERVICE. It is done
by the hardware one cycle after the completion of the
macro-instruction to allow the Condition Codes to become
stable for checking overflow. This is one cycle after the
first IR Decode branch of the next micro-instruction. There
is no micro-order which invokes this test.
If a trap condition or interrupt is pending, then the
micro-vector associated with the highest priority event is
asserted on the Control Store address lines overriding the
address mode specified by the current micro-instruction. The
address of the instruction during which the test was made is
pushed on the micro-stack. When the BUT SERVICE test is
true, all action in the micro-cycle is inhibited by the
hardware. This includes starting bus cycles, updating the
PC, IR, or OSR and writing destinations.
If there is a micro-trap condition in the same micro-cycle
in which the BUT SERVICE test is true, then BUT SERVICE has
higher priority than the micro-trap condition. The reason
for this is that the micro-trap was caused while attempting
to execute the next macro-instruct. The exception to that is
a Control Store Parity Error which overrides the BUT SERVICE
test.
During the execution of long macro-instructions interrupts
can be detected by micro-orders in the BUT field. If an
interrupt has occurred then a micro-branch to the
appropriate service routine is specified.
A micro-trap is a mechanism for handling conditions which
prevent a micro-instruction from completions successfully.
The micro-sequencer does a utrap operation at the end of the
micro-cycle by forcing a JSR to a routine which corrects the
problem. After the condition has been corrected, the routine
returns to the micro-instruction and re-executes it. This
transaction is transparent to the micro-programmer.
With this in mind let us find out how the machine actually
gets to the physical MICRO-ADDRESS to handle the proper
Interrupt, Trap or Micro-Trap.
All Interrupts are generated from the Interrupt chip located
on the UBI module and, depending on which Interrupt is
generated goes to MICRO-ADDRESS locations 38 through 3F. How
are these addresses generated? The address comes from three
location in the CPU, broken down by bits 5-0.

16-13

Interrupts and Exceptions

Bi ts 0,
Module.

1 and

2 come

from

the

INTERRUPT CHIP on

the

UBI

Bit 3 comes from the UTRAP CHIP on the M/C Module.
Bi ts 4 and 5 are gener.ated from
PATH Module.

the MSQ CHIP on the DATA

As the machine is running macro code a request for an
interrupt is sent to the INTERRUPT CHIP. As an example we
will use a Console Interrupt, al though ALL interrupts are
handled the same way. The Interrupt Chips will check the IPL
of the request to the IPL now in its IPL Register. (In the
Int. Chip.) If the requested IPL is higher then the signal
INT PENDING is sent to the SAC CHIP on the Data Path Module.
Nothing will happen until IRDl of the MACRO Instruction that
is now running in the machine. What happens when IRDl is
decoded by the SAC from the BUT FIELD is going to cause
·action by the INT. Chip, MSQ Chip, and U Trap Chip
simultaneously, but on paper can only be explained one chip
at a time.
When IRDl is decoded and INT Pending is asserted the SAC
chip generates DO Service L and ENABLE UVECTOR H. These
signals will cause the three previously mentioned chips to
output the needed MICRO ADDRESS 39 for CONSOLE INTERRUPT.
INT. CHIP - When request for console interrupt n DO service
L was generated by SAC the Interrupt Chip, on the trailing
edge of MCLK, allow the bits to be driven onto the uvector
lines. These bits would equal 001 for Console Interrupt.
MSQ CHIP
When DO Service L and ENABLE UVECT H are
generated, along with the fact MICRO ADDS INH L is H, and
MSEQ INIT L
is H, the MSQ chip outputs a 30 onto uvector
lines. This always occurs on Interrupt. (See Chart.) Use for
Traps and micro traps also.
.Micro
ADDR
Inhibl

Enable
uvector
H

Do Serv
L

Internal
MSQ
Initial

cs Lines

H
H
H

H
L
H

H
L
L

H
H
H

20 HEX
10 HEX
30 HEX

5-0

UT RAP CHIP - The signal DO Service L also goes to the
TRI-STATE driver to uvector Line 3 to be shut off and float

16-14

Interrupts and Exceptions

to a High which is a 1. This line is sent to the DPM (just
below the MSQ chip in prints) and is allowed to be ored with
the 30 from MSQ chip due to the fact uvector is enabled.
What we end up with is the Micro address 39 to be sent to
the control store module. That answers the question of how
the micro-address was generated for an Interrup~.
How is the Micro address generated for a Trap Condition?
TRAP - As you can see by the "FIXED CONTROL ADDRESS" chart
all traps are lX. This will be a simpler action because
there are only Two Chips involved. SAC for bits 0, 1 and 2.
MSQ for bits 3, 4, and 5.
If you look at the 5 possible traps and look at the SAC chip
you will see that all 5 traps feed directly to the CHIP.
11
12
14
15
16

= Arith Trap
= FPA Trap
= Timer Services
= T-Bit Trap (PSL TB)
= Console "'p Trap (Console Halt)

SAC
During IRDl But Service is performed and a Trap
Condition exists for an Example we will use ARIH Trap L. The
SAC chip at this time only outputs DO Service L. NOT ENABLE
uvector. The SAC chip also outputs to the uvector lines 001
for bits 2, 1, 0. These lines will determine which type of
Trap exists.
MSQ - Do Serv L is received from SAC and· referring to
previous chart you find the 110 being outputted to uvector
lines. il0 or with 1 gives you the ill to the control store
for the proper address to handle th~ Arith Trap.
That should answer how the proper Trap address gets to
Control Store.

the

How does a Micro-Trap address get sent to the Control Store?
We know that a micro trap is a mechanism for handling
conditions
which
prevent
a
micro-instruction
from
completions successfully. To do this the proper address
needs to be sent to the control to the routine to handle the
condition.
MICRO-TRAP - To find how the address is generated you must
go to the UTrap Chip on the MIC mode and the list of Micro
Traps in the "Fixed Control Address" Chart. We will not be
concerned at this point which micro-trap has priority over

16-15

Interrupts and Exceptions

the others as that is covered in the MIC section. We are
concerned with how the address is generated. For an Example
we will take a TB miss UTrap~ 2A. You notice all micro-Traps
are 2X. These chips are involved Utrap chip, SAL and MSQ.
UTRAP CHIP - The utrap chip is constantly monitoring the
events during each micro instruction and if a Translation
Buffer Miss occurs during read MICRO-instruction it cannot
be completed. You trap chip see the TB Parity Era H signal
and NO TB Hit from 0 or 1 the signal Utrap is generated and
the uvector lines 3-0 are set to 1010 {but not driven until
trailing edge of MCLK) •
SAC - The Sac chip receives Utrap L signal
ENABLE UVECTOR H, but NOT do service.

and generates

MSQ - The MSQ receives the Enable uvector H signal and
referring to previous chart you find the MSQ chip outputs 20
to be ored with the uvector lines that are just below the
MSQ in prints that come from the UTrap Chip which are
allowed to pass with the Enable uvector H signal from SAC
chip. The address 2A is sent to the control store for the
routine to handle a TB miss.
This should explain how the address of a micro-trap is sent
to the control store module.

16-16

VAX-11/750 LEVEL II

Console Interface

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

Console Interface

INTRODUCTION
The console interface chip is an asynchronous serial
1 ine interface between the COMET console terminal and
the CPU.
It contains logic to do limited character
recognition of the received characters for entering in
Console Mode.
It asserts signals to request both micro
and macro level. interrupts.
Addressing of internal
registers is indirect through Console Register Address
Register ( CRAR) •

17-1

Console Interface

SYN POSIS
This module is designed to be a block diagram and
chip level presentation on the following:
a)
b)
c)

Transmit parallel to serial converter
Receive serial to parallel converter
Microroutine

OBJECTIVES
Given a block diagram of the Console Interface,
correctly identify each block by labeling it.
Provided with a list of Console Interface functions
and signals, correctly match the signal to its
function.

SAMPLE TEST ITEM
Utilizing the CUI Print Set, match the below listed
Console Interface signals to their functions:
a)
b)
c)
d)

Disables console interface
INSTR FETCH H
SERIAL LINE INT. Asserted
is
when
data
available for output
CON SO
When asserted, equals data
out
Latch data in
M CLK L

RESOURCES
Comet Specifications
Comet Print Set

17-2

Console Interface

MODULE OUTLINE
XVII.

CONSOLE INTERFACE
A.

CON Chip
1.

WCTRL
W-BUS
SERIAL IN/OUT

Transmitter Half of CON Chip

Receiver Half of CON Chip

Print Famliarization

Summary

17-3

Console Interface

'~·

WBUS

rV
-

~
WCTRL

<30:25>

vi-

OCLK

SERIAL IN

CONSOLE XMIT
CONTROL&
STATUS REG ..
(CTCSR)

CONSOLE XCV
DATA BUFFERREG. (CROB)

CONSOLE
STATUS REG.

CONSOLE REG.
ADDRESS REG.
(CRAR).

(CSR)

CONSOLE XMIT
BUFFER REG.
(CTBR)

CONSOLE XCV
CONTROL&
STATUS REG.
(CRCSR)

XCV REG.
(RR)

XMIT REG.
(TR)

XCV TIMING
COUNTER
(RTCTR)

XCV CONTROL
COUNTER
(RCCTR)

BAUD CLI<

READY

HALT
HALT PEND.

---

DONE

SERIAL OUT

'---INIT

XMITTIMING
COUNTER

.. .. ,,

ITTl"TD\
.__

XMIT CONTROL
COUNTER

I .. -C ....

ITr _TR\

CON CHIP
Tl(-2077

Figure 17-1

CON Chip Input/Output Signals

17-4

D CLK
WCTRL <30:25>

LO CLK
l'1.]
.....

WBUS

'°c:re

1
-

CTBR

CONSOLE XMIT
BUFFER REG.
l------------..-------------1

......
.....J

I
"'->

.....J

CTCSR

CONSOLE
XMIT
CONTROL&

REG.
ADDRESS
REG.

()

......

CRAR

CONSOLE

~=------------------------4~
a-=..:.RE~A~D~Y..;_

____________________
__

STATUS REG.

::J

......

XMIT REG.

SERIAL OUT

.-3

1
0
TCCTR
XMIT CONTROL COUNTER

::J

......
rt
rt

'
(")

INIT
BAUD CLK

TT CTR

XMIT TIMING COUNTER

=16

::s

]

......
<D

CONSOLE TRANSMITTER
TK-2070

TRANSMITTER TIMING
I

BR CLK

JUUUUUU
I

t'Jj

LDCLK

'°c:

TCLK

.....
l"1

~----r

........

......
I
w
........

......
I

°'

TCLK

::J

{/)

.....

rt
rt

I
I

tL-h__
I

__n__rui_

I 1111111111
t

___

--,

::J

'°

I
I

TCC

.....
8
.....

1111111111111111111111

l"1

--------r------,-------,-------~-1
I
I
I
I
I

l"1

I
60

_ _ _,_J

I
I

::J
{/)

:
lsr[S\J\f!J\l\:C'8J\l\I sP
---------------,----~-----I

()

0
0
........

I
t

H
TK-3418

::J
rt

l"1

1-tl

Console Interface

CRAR
CONSOLE REG .. ADDRESS REGe
ADDRESS FORMAT
REGISTER

ADDRESS

CTDB

CRDB

00
01

CT CSR

CR CSR
CSR

11
TK·2CM2

Figure 17-4

Console Register Address Format

17-7

Console Interface

0 CLK
WCTRL<"30:25>

CROB

weus

CONSOLE XCV DATA
BUFFER REG.
CONSOLE STATUS

CRCSR
CONSOLE
XCV

RR
SERIAL IN

XCV REG.

HALT
HALT PENO.

CONTROL&

DONE

STATUS REG

RCTCR
XCV CONTROL COUNTER

RTCTR
BAUD CLK

XCVTIMING
COUNTER

CONSOLE RECEIVER
TIC·20'14

Figure 17-5

Console Receiver

17-8

RECEIVER TIMING
BRCLK

tTJ
......

1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

cI""(
CD

2
RT

I-'
.....]

I
0\

I-'
.....]

::0

()

......
<
CD
I""(

t-3
......
a
I-'•
::s

2---3-------

4~------------~----------

(')

::s

(J)

0
TK-3416

I-'

CD
H

::s
rt
CD
I""(

()

Console Interface

THE CONSOLE INTERFACE CHIP
CON
117
WCT5
WCT4
WCT3
WCT2
WCT1
WCTO
CHSL
MCLK

W807

WBUS25H
WBUS24 H
W8US2JH

W806
W805

WBUS21 H

W809
W808

W8US22 H

W804
W803
W802
W801
W800

MCl.K
CNIT

WBUS20H
WBUS 19H
WBUS 18H
WBUS 17 H
WBUS16H

UBl11 SERIAL LINE INTL

DCKE
CMCR
BRCK

HTLT

MOIT
9

UBl11 CON HALT l

SLDT

FTPL

2 C4
GND

GND_J:
OPM17 INSTR FETCH,H
UBl1°1 HALT DET SYNC H

•·

UBl11 CON DONE SYNC H
UBl11 CON T READY SYNC H
RDINTINH H

CNHT
SELi

A35
R10I
3K

HDBR
ITCR
IRFH

33
48

DEBR
TR8R

C3
330PF
100V

HOSY
DESY

LCLK
DCLK
CKDD

TRSY
ADIH
CLDI

CLCO

CLCI

GHD

TK20M

Figure 17-7

Console Interface Chip

17-10

VAX-11/750 LEVEL II

TU58

Interface

Student Guide

Course produced by Educational Services Department
of
Digital Equipment Corporation

TU58 Interface

INTRODUCTION
The TU58 interface chip is an asynchronous serial line
interface between the TU58 tape unit and the CPU. With
very few exceptions, it is identical to the Console
Interface.
The TU58 mag tape unit is a low cost mass memory device
with random access, block formatted, pocket size
cartridge media.

18-1

TU58 Interface

SYNPOSIS
This module is designed to be a block diagram and
chip level presentation on the following:
a)
b)
c)

Transmit parallel to serial converter
Receive serial to parallel converter
Microroutines

OBJECTIVES
Given a block diagram of the TU58 Interface,
correctly identify each block by labeling it.
Provided with a list of TU58 Interface functions and
signals, correctly match the signal to its function.

SAMPLE TEST ITEM
Utilizing the UBI print set, match the TU58
Interface signals listed below to their function.
a) •
b) •
c) •
d) •

TU SO L
M CLK L
TU SI L
MSEQ !NIT L

Data out
Latch data in
Data in
Initialize
chip
registers

RESOURCES
Comet Specifications
Comet Print Set

18-2

and

clear

TU58 Interface

MODULE OUTLINE
XVIII. TU58/INTERFACE
A.

CON Chip

TU58

Specifications

Component Identification, Mechanical

Component Identification, Electrical

Block Diagram

Registers

Data Format

Summary

18-3

TU58 Interface

SELECTED TU58 SPECIFICATIONS
CARTRIDGE CAPACITY

262.144 BYTES
512 BLOCKS OF 512 BYTES EA.

TRACK FORMAT

140.FEET PER CART .
. 150 IN WIDE
2 TRACKS, EACH CONTAINING
- 1024 NUMBERED RECORDS

4 RECORDS=1·512 BYTE BLOCK
BIT DENSITY

800 BPI

READ/WRITE TAPE SPEED

30 IPS

SEARCH TAPE SPEED

60 fPS

AVE RAGE ACCESS TIME

9.3 SEC.

MAXIMUM ACCESS TIME

28 SEC.

DATA TRANSFER RATE

· 41.7 US/DATA BIT
24KBPS

INTERFACE BUFFERING

150 TO 38.4K BAUD.
JUMPER SELECTED

DRIVES PER CONTROLLER

1 OR 2
ONLY ONE CAN OPERATE
AT ATIME.
TK-2049

Figure 18-1

Selected TU58 Specifications

18-5

TU58 Interface
TU58 DRIVE UNIT

DRIVE PUCK

....,_ _ SWING-OUT
,·

~,.

HEAD GATE

WRITE
PROTECT
TAB

MAG.

TAPE

TAPE CARTRIDGE
ELASTOMER

BELT
Figure 18-2

Tape Cartridge and Drive Unit

18-6

TK-2040

DIAGNOSTIC
LED

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300+2
600+3
1200 + 4
2400 + 6
4800 + 6
9600 + 7
19.2K + 8
38.4K +9
RCV + 10
XMIT + 11
AUX A+ 12
AUX B+ 13

WW9
WW10
WW11
WW12
WW13
WW14
WW15
WW16

150
BAUD
300
BAUD
600
BAUD
1200
BAUD
2400
BAUD
4800
BAUD
9600
BAUD
19200
BAUD
38400
BAUD
UART RECEIVE CLOCK
UART TRANSMIT CLOCK
AUXILIARY A
AUXILIARY B
FACTORY TEST POINT
GROUND
BOOT

WW17
WW18
WW19
WW20
WW21
WW22
WW23
WW24

RS-423 DRIVER
RS-423 COMMON (GROUND)
TRANSMIT LINE +
TRANSMIT LINE RS-422 DRIVER+
RS-422 DRIVER RECEIVER SERIES RESISTOR
(JUMP FOR RS-422)

wwe

WW
25 23 21 19
++ ++++++++
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WW4
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Figure 18-3

Interface· Selection Jumper i Locations

TU58 Interface

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HEAD
SELECT

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READ
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PROCESSOR

8085
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DRIVER
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256
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ROM
2K
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UART

DRIVERS

RECEIVERS

TO HOST

TU58 BLOCK DIAGRAM
Tllt·201!5

Figure 18-4

TU58 Block Diagram

18-8

TU58 Interface

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BOT

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#129

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BLOCK LOCATIONS ON TAPE.
TK-2080

Figure 18-5

Block Locations on Tape

18-9

VAX-11/750 LEVEL II

Condition Codes

Student Guide

Course produced by Educational Services Department
of

Digital Equipment Corporation

Condition Codes

CONDITION CODE LOGIC DESCRIPTION
The Condition Code logic in the Cornet CPU is designed to set
or clear the PSL N, z, V, and C bi ts according to the
architectural def ini ti on of each VAX 11 macro instruction
and the result of the data path operation. The condition
code logic also determines whether or not conditional VAX 11
branch instructions are satisfied so that the microcode can
rnicrobranch properly. A third function of CCC is to initiate
all arithmetic traps. Most of the logic circuitry to perform
these three functions is implemented within a gate array
called CCC. CCC is located on the DPM module in slot 2. This
gate array is controlled by a secondary encoding of the CC
·field and the WCTRL field of the microword called CC CTRL
<3:0>. The PSW lives in the CCC gate array, while the copies
of the CM bit <31> exist in PHB and CCC. PSL FPO bit <27> is
contained in the PHB gate _array which is part of the
microsequencer logic. The PSL IS bit <26>, CUR MOD <25:24>,
PREV MOD <23: 22>, and the IPL <20: 16> all are part of the
INT gate array located on UBI. When a CCPSL WB PSL
micro-order is issued, the entire PSL is sourced to the WBUS
on a read from all three gate arrays. Writing the PSL is
also accomplished from the WBUS so all three gate arrays are
enabled when the CCPSL function is PSL WB. We will limit
this discussion to the PSW which is in the CCC gate arra·y.
The CCC gate array is controlled by the CC and WCTRL fields
of the microword, after they are reencoded by what is called
the CC CONTROL (El4) ROM on the DPM module. This rorn is not
defined in the microcode listing so figure 18-1 is included
in this discussion of what the rom content is for the
various CC and WCTRL field functions. We should look at the
CC and WCTRL fields and understand what fields are relevant
to the CCC gate array. The vertical functionality of the
microword is explained in a previous lesson. The CCMISC
field of the microword is true if any of the following
combinations of the CC and WCTRL fields is desired by the
rnicroprogrammer.
CCMISC

CC BINARY

WCTRL BINARY

NOP.CCBR BRATST
NOP.CCBR-CSIGN
WB ATCR.CCBR SIGND
ALUS DSDC.CCBR ALUS
ALUS-SIGND.CCBR ALUS
ALUS-UNSGN.CCBR-ALUS
SETv:ccBR SIGND-

000111
000110
000111
000110
000110
000110
000111

Notice

that

the WCTRL

01
00
00

11
10
01

field

19-1

the

microword

during

the

Condition Codes
CCMISC is either 6 or 7. There is no WCTRL field definition
for 6 or 7, which means that CCMISC micro-orders are unique
operations. The CCPSL field of the microword is true if the
microprogrammer specifies one of the below operations in the
microinstruction.
CCPSL

WCTRL BINARY

WB PSL.CCBR SIGND
cc-WB.CCBR ALUS
PSL WB.CCBR ALUS=0
PSL-WB.CCBR-ALUS=l
MDR-OSR.CCBR BRATST

000100
000101
000000
000001
101111

The above field definitions are really variations on the
WCTRL microorders that are not defined as WCTRL functions.
You' 11 notice that in both the CCMISC and CCPSL functions,
the name of the def ini ti on has the CCBR microbranch bi ts
defined also. The CCBR bits are two microbranch status bits
that are defined in the microinstruction that specifies a
BUT
micro-order
BUT/CCBR,
BUT/CCBR.CCBR0.IR0,
or
BUT/CCBR0.SRKSTA0. The definition of CCBR <1:0> is defined
in the CCPSL or CCMISC micro-order of the microword. For
example, the CCPSL micro-order WB PSL.CCBR SIGND indicates
that the WBUS gets the PSL from the INT, PHB, and CCC gate
arrays. Additionally, the CCBR bits <1:0> assume the~r
default values, which are •••
CCBR

<l>

<0>

0= WBUS greater than
or equal to 0

0= WBUS not equal to 0

l= WBUS less than 0

l= WBUS equal to 0

These bits are particulary useful for microbranching on the
result of
ALU operations or WBUS data. The CCBR bits can
assume different functions depending on the CCMISC, CCPSL,
or CC micro-order. An example of this is the CCMISC
micro-order NOP.CCBR BRATST. The CCBR bits take on a new
function.
CCBR

<l>

<0>
0= Conditional branch not satisfied.
l= Conditional branch condition is
true.

This micro-order is specified in the microcode that executes
the VAXll macro conditional branch instructions. Basically
it decodes the opcode of the branch instruction and compares
the PSL N,Z,V, and C bits to the branch condition. For
example, a BNEQ macro instruction would assert CCBR <0> if
the PSL Z bit was clear during the execution. There is a
19-2

Condition Codes
most useful chart in the microcode listing called BUT/CCBR.
Locate this chart in the CHARTS .MIC file of the microcode
listing. This chart defines the CCBR bits <1:0> for each of
the CCMISC, CCPSL and CC micro-orders. The CCBR bi ts <l: 0>
are generated in the CCC gate array under control the
redefined CC and WCTRL fields.
The CC field of the microword also can effect the CCBR bits
<1:0> as shown· in the chart. The CC field also has the 2
fields that set the PSL condition codes according to the
architectural requirements and data path operation results.
The CC field is defined as follows •••
CC/=<32:31>,.DEFAULT=0
·NOP.CCBR SIGND=0,
NOP.CCBR-ALUS=3
CCOPl.CCBR_SIGND=l,
CCOP2.CCBR SIGND=2,
The first two micro-orders are NOPs as far as the PSL
condition codes are concerned, but they do effect the CCBR
bits. Th~ microprogrammer can use either of the NOP
micro-orders with a BUT/CCBR micro-order to microbranch on
the default signs explained above or the ALU STATE bi ts
<1:0> that are part of the ALU. The CCOPl and CCOP2
micro-orders are used to set the PSL condition codes. The
CCOPl micro-order is used for about half of the macro
instruction set to set the condition codes. The CCOP2
micro-order is used to set the condition codes for the
remainder of the macro instruction set. Locate the VAX
NATIVE MODE CONDITION CODE CHART in . the charts microcode
file CHARTS .MIC. This chart indicates which CC micro-order
must be specified for a particular macro instruction in the
far right column. The 4 columns across the page describe how
each PSL condition code bit is affected when the CCOPl or
the CCOP2 micro-order is specified.
To understand how this works we will trace the microcode
executed for a VAX 11 macro instruction and see how the
condition codes are set. Before we can do this we should
review the operation of the D Size ROM and how to read the
microcode macro expansion. The D Size rom is blasted by the
microprogrammer that wrote the microcode for the VAX 11
macroinstruction being
executed.
The
VAX
11 macro
instruction that we will trace is.
ADDL2

R0, Rl

; Where R0 is 7FFFFFFF and Rl
; is equal to 00000001

Remember how to read the IRD ROMS?
We will get to that
momentarily. First of all, what type of instruction is this?
Well this happens to be an INTEGER add so we should find the
microcode for this VAX 11 macro instruction in the
INTLOG.MIC file of the microcode listing. What we are
19-3

Condition Codes
looking for is the D Size rom macros which are typically the
last section of one of these files. Locate the D Size rom
macro for the ADDL2 instruction. The hex opcode for an ADDL2
is C0. The D Size ROM macro should appear as below •••

000:

SIZE [LONG]

[LONG]

[ 0]

;ADDL2

The way one reads this macro is starting from the left
column, the number 0D0 is address input to the D Size Rom.
The !RD counter output also addresses the D size rom, so
that for one opcode, there are six locations in the rom. The
reason there is six locations is because the VAX 11 macro
instructions can have up to six operand specifiers that must
program the size of the data path during each execution
phase.. In the ADDL2 macro instruction, there are only 2
operands, so the D size ROM must be blasted with data size
for 1st and 2nd operand specifier evaluations. The SIZE of
the data path for each operand specifier evalution is
contained within the []. As you can see the first operand
specifier evaluation is in the next column. The data size
for each of the six operand specifier evaluations from 1 to
6 is read from left to right. Instructions that have less
than 6 operands, contain 0 in unused locations. The ADDL2
instruction contains the size [LONG] in the first and second
operand specifier evaluations. Refer to the DEFIN.MIC file
for the D size rom definition and you'll find that the data
size definitions are as follows...
·
IF DSIZE = [BYTE]
IF DSIZE = [WORD]
IF DSIZE = [LONG]
IF DSIZE = [QUAD]

THEN DSIZE
THEN DSIZE
THEN DSIZE
THEN DSIZE

<1:0> = 0
<1:0> = 1
<1:0> = 2
<1:0> = 3

So the D Size rom would be blasted with a 2 bit binary size
code for every execution phase of the macro instruction. It
is important to remember that the D Size rom output is used
only if the DTYPE field of the microword specifies IDEP
{data size is instruction dependent). The D Size bits <1:0>
go to the CCC gate array so that the PSL condition codes are
properly set according to the data size of the VAX 11
macroinstruction. Now that we know how to read the O. size
ROM, let's trace the ADDL2 macro instruction through the
microcode. We have to refer to the IRDl and IRDx rom macros
located at the end of the INTLOG.MIC file. The IRDl and IRDx
rom macros appear as below •••
• !CODE
0C0: FPD
IRDl

OPS
[NOP] [IE. OPCOD. DEC]
[LOD] [OS. RED]

OPS
[NOP] [IE.OPCOD.DEC]
[LOD] [OS.RED]

This is the IRDl rom macro definition for ADDL2. The IRDl
ROM is addressed by the opcode of the instruction to be
executed and the FPD and the signal FPA PRESENT.This means
the macro instruction opcode provides the base target
19-4

Condition Codes
address in the rem of which there are 4 locations. That is
what this macro is used for. It allows the microprogrammer
to blast all four locations with the address in control
store of the microroutine to evaluate the first operand
specifier. The FPD bit should not be set at IRDl of an ADDL2
instruction because it is not interruptable. If it is set,
then the machine will vector to location SCBB+l0 and execute
the RESERVED to DEC opcode_ instruction fault service
routine. FPA PRESENT is a signal that is used to change the
flow if an FPA is present or not. You'll note the IRDl rem
macro has 2 targets across the page. 1 with FPA and 1
without FPA. The OPS bit is used to load the OSR at IRDl and
IRDx. The IRDl rem macro could be changed to show how the
rom is addressed as follows.
000:

FPD
NOT FPD

NOT FPA
NOT FPA

FPA
FPA

What this shows us is at base IRDl rem address 0D0, the 4
locations that are blasted are all the possible combinations
of FPO and FPA PRESENT. The contents of the [] is the label
of a microroutine that is entered for each of the 4 possible
combinations. In the case that we are using, an ADDL2 does
not use the FPA, FPD should be clear, and both the source
and destination operands are in registers. For this
discussion we will assume that the FPA is not present, even
if the FPA was installed in the CPU, the operand specifier
routine address is the same, [OS.RED]. PSL FPD is false and
REG MODE is true for both the source and destination
operands. This means the microcode will microbranch on the
addressing mode and enter the OS.RED flows at the
microinstruction that fetches the source operand from a
register. We will see this in a little bit. Lets look at the
IRDx rem macro, This is similiar to the IRDl macro except
that the IRD COUNTER output addresses these ROMS •
• OCODE
OPS
REG
MEM
0C0: CNT0 [LOD] [IL.ADD2.B.W.L.REG ] [OS.MOD]
CNT 1 [ N0 P] [ IL • ADD 2 • B • W. L. MEM ] [ IL • ADD 2 • B • W. L. MEM
The combinations of REG MODE and FPA PRESENT are used as
address input to the IRDx rem along with the IRD counter
output. This means there are eight possible targets at IRDx
(CNT0 has 4 combinations and so does CNT 1). CNT0 address is
used at the first IRDx and the CNTl address is used at the
second IRDx. Since this is register mode for both the source
and destination, the control store address at CNT0 is
[IL.ADD2.B.W. L.REG] and the CNTl control store address is
[IL.ADD2.B.W. L.MEM]. In register mode the CNTl address is
really meaningless. If the destination was not a register,
the MEM flows would have been followed. and the microcode
would have gone to the following control store addresses.
VA GPR

[OS.MOD]
19-5

Condition Codes
WRITE MEMORY AT VA

[IL.ADD2.B.W.L.MEM]

To summarize the flow of the ADDL2 R0,
goes to the following two rom addresses.

Rl,

the microcode

[OS.RED]
[IL.ADD2.B.W.L.REG]

IRDl
IRDX

With this knowledge we can trace the microinstructions. They
are reproduced below from the OSR.MIC and INTLOG.MIC files
respectively •••
100:
OS.RED:
;0000------------------FPA_Q_M[MDR] MDR_R[GPR.R] I
CLOBBER MTEMP0 DEF, IRDX [l]

;Rn
REGISTER MODE
; PLACE OP (GPR (RNUM))
IN MOR
; SAVE MOR IN Q

This moves the source operand from R0 into the MOR and Q
The
IRDX
address
is
gets
the
old
MOR
data.
[IL.ADD2.B.W.L.REG] and at this IRDx, the next control store
address is [IL.ADD2.B.W.L.REG]. This is the microinstruction
stored at IL.ADD2.B.W.L.REG •••
; 80 A0 C0

IL.ADD2.B.W.L.REG:

;-----------------------------------;;

R[GPR.R].SIZ M[MDR]+RB,CCOPl,
SIZE [IDEP],-IRDl

;

This microinstruction specifies that the GPR pointed to by
the RNUM latch <Rl> is the destination. The MOR <R0> is
added to the destination GPR <Rl>, which is selected by
RNUM, and that GPR <Rl> is modified. The PSL condition codes
are set with the CCOPl micro-order. The condition codes are
set according to the D Size which is specified with the SIZE
[j macro. The SIZE being equai to IDEP means the D Size ROM
specifies the data size and the D Size Rom macro explained
above indicates the data size of the source operand is
[LONG] and the data size of the destination is also [LONG].
The result of adding 7FFFFFFF and 00000001 is 80000000. This
is an integer overflow and as a result the PSL N, Z, v, and
C bits should be set as follows for an ADDL2.
PSL N
ALU<31>

WX<31:0>=0

ALU<3l>V

ALU<3l>CO

1
2.9.2

VAX 11 BRANCH INSTRUCTION IMPLEMENTATION

The CCC gate array also is used to decide if a VAX 11 macro
19-6

Condition Codes
branch instruction is satisfied, so that one of two things
can happen. If the branch condition is NOT satisfied, the
hardware must bump the PC to the next sequential instruction
and do the IRDl. If the branch condition IS satisfied, the
sign extended displacement is added to the PC. Writing the
PC flushes the XB and initiates prefetch for the new
Instruction Stream Data. We are going to trace a VAX 11
macro branch instruction called BNEQ. This macro instruction
branches if the PSLZ bit is clear. We will show both paths
that are followed. The BNEQ instruction is located in the
CONTRL.MIC file. First lets look at the IRDl rom macro for a
BNEQ in the back of the CONTRL .MIC file. The Macro appears
below •
• !CODE

OPS

REG

012: FPD [NOP] [IE.OPCOD.DEC]
IRDl[LOD] [CO.BRCND]
.OCODE
012: CNT0[NOP] [IE.BAD.IRD]
CNTl[NOP] [IE.BAD.IRD]

OPS

FPA REG

[NOP] [IE. OPCOD. DEC]
[LOO] [CO.BRCND]
(NOP] [IE.BAD.IRD]
[NOP] [IE.BAD. !RD]

The IRDl macro specifies that the address of the BNEQ
microcode is CO.BRCND which is the target address for all
the conditional branch instructions. Notice that this
instruction will NOT do an IRDx and that the address for a
fault is [IE.BAD.IRD] which initiates a Machine Check
Exception. The microcode sequence for the BNEQ is shown
below.
=1000
CO.BRCND:
;1111--------------------;
MDR_ZEXT(OSR) BRATST?,
; GET DISPLACEMENT FROM OSR
; TEST FOR BRANCH
NEXT/CO.BRCND-DECIDE
; GO TO DECISION BLOCK
This microinstruction moves the branch displacement from the
OSR to the MDR zero extending from bit <8> to bit <31> in
the MDR. In the same macro,the BRATST? implies that the BUT
micro-order is BUT/CCBR and the CCPSL micro-order is
CCPSL/MDR OSR.CCBR BRATST. Locate the this macro in the
MACRO.MIC- file and verify that this is true. This micro
instruction has two possible destinations. If the PSL Z bit
is set, the microcode will read the microinstruction at
CO.BRCND-DECIDE. If the PSL Z bit is clear, the microcode
will execute the microinstruction at CO.BRCND-DECIDE+l.
If the PSL Z bit is set, the branch condition
satisfied and the next microinstruction is
=0
CO.NOP:
19-7

not

Condition Codes
CO.BRCND-DECIDE:
;-----------------------------; NO BRANCH IF CONTROL COMES
IRDl
; HERE,GO DO NEXT INSTRUCTION
Simply do IRDl and execute the next sequential instruction.
If the PSL z bit is clear, the CCBR bits <1:0> are equal 01,
according to the to the CCPSL micro-order at location
CO.BRCNDc The following microinstructions are executed
CO.BRCND-BRANCH:

IF CONTROL COMES
;1---------------------------;; BRANCH
HERE, CALCULATE NEW PC

PC PC+SEXT(M[MDR]},
SIZE [IDEP], NEXT/CO.NOP

WASTE CYCLE TO LET PC CATCH
UP

The PC gets the sign extended MOR if the branch condition is
s~tisfied and the data size of the value written into the PC
is determined by the D Size ROM. Writing a new value in the
PC causes the XB to be invalidated and prefetch for the new
I Stream begins, If the XB is not full at IRDl, the
micromachine is stalled until the XB is filled. The next
microinstruction is at CO.NOP which IRDl and it is shown
above.
We have seen two of the major functions of the CCC gate
array and how the microcode implements setting the condition
codes and branching macro instructions. The CCC gate array
also generates the signals that cause an arithmetic trap at
the BUT SERVICE following an arithmetic operation, The PSW
bits <7:5> are the TRAP enable bits that must be set up by a
VAX
macro routine. The functions of these bits briefly is
described below.

PSW <7>
PSW <6>
PSW <S>

Decimal Overflow TRAP enable.
Floating Underflow TRAP enable.
Integer Overflow TRAP enable.

If an arithmetic operation is performed that causes one of
the TRAP conditions, the CCC gate array will assert the
signal ARITH TRAP L. At the next BUT SERVICE, the Arithmetic
Trap is arbitrated with console halt, Interrupt Pending,
etc. and the trap flows should be entered. The type of
arithmetic trap is logged the Arithmetic Trap Code Register
(ATCR} which is also contained in the CCC gate array. The
Arithmetic trap results in aborting the next macro
instruction and performing the trap service from SCBB+30.
The trap microcode pushes the PSL,
PC of the NEXT
instruction, and the ATCR on the stack.
This
completes
implementation.
2.9.3

the

discussion

the

microcode

HARDWARE IMPLEMENTATION OF CONDITION CODE LOGIC

19-8

Condition Codes
The actual hardware that implements the condition code logic
is a small percentage of the total. The condition code logic
is on the DPM module and we'll refer to the print set. Refer
to DPM20. At the beginning of this discussion we stated that
the CCC gate array is controlled by 4 bit field called CC
CTRL <3:0>. This field comes from the output of the rom El4
on DPM20. The address input to this ROM is the CC and WCTRL
fields of the microword that is latched on DPM20 and DPM12.
The output is called CC CTRL <3:0> H and these 4 signals go
to the CCC gate array shown on DPM10. Figure 18-1 shows how
the CC CTRL lines and the GOOD SAMARITAN ROM are programmed
for various combinations of the WCTRL and CC fields. The
reason the signal LIT 0 H is present is because if the LIT
field is 1 or 3, the CC field is not interpreted and becomes
part of the short or long literal. On DPM10 again let's look
at the CCC gate array inputs. The 1 ines CC CTRL <3: 0> are
the control input to the gate array. The VAX 11 or
compatibilty macro instruction opcode is latched in El2 and
is the input to combinational logic that sets the PSL
condition codes according to the architectural defintions
and data path results. The D Size bits <1:0> enter the CCC
gate array and are used to select the correct data path
sign, C bit, and V bit. The sign can be either WBUS<31>,
WBUS<lS>, or WBUS<7> depending on the D-size bits <1:0>, the
same is true about the source of the C bit and V bit. The C
and V bits would be selected as a function of data size
also. FPA z a-nd V are interfaced to CCC so that FPA divide
by zeros and overflow can force the appropriate ari thm_etic
trap condition. CCC generates the TRAP for FPA instruction
traps also. The interface to the WBUS is a bi-directional
interface that essentially connects the PSW (-TP) to the
rest of PSL when the CCPSL micro-order specifies WB PSL.
Writing the PSW from the WBUS is accomplished with- the
PSL WB micro-order. The PSL C bit goes to the BUT mux on
DPMl6 for microbranching on the state of the C bit. ARITH
TRAP L goes to the SAC gate array on DPM 17 for initiating
the arithmetic trap at BUT SERVICE. The CCBR bits <1:0> go
to the BUT mux on DPMlS and 16 for microbranching on their
state.
The functionality of the CCC gate array is tested with the
microdiagnostics and indirectly with the macro diagnostics.
Figure 18-1 is included here to show the programming of the
CC CTRL rom and the GOOD SAMARITAN rom which are not blasted
by the microprogrammers.
This concludes the discussion of the Condition Code Logic.

19-9

Condition Codes

GOOD SAMARITAN ENCODING
GOOD SAMARITAN INPUTS

GOOD SAMARITAN OUTPUTS

WCTRL
Function

WCTRL

LIT e H

CC CTRL <3:8>
G.S .. <7:4>

WRITE PSL
WRITE PSW
READ PSL
WRITE CC
CC MISC 1
CC MISC 1
CC MISC 1
CC MISC 1
cc MISC 2
cc MISC 2
cc MISC 2
cc MISC 2
cc MISC 2

00
01
04
05
06
06
06
06
07
07
07
07
07

x
x
x
x

B
3

0
1
2

0
0
0
0
0
0
0

0
1
2

A
5
8

7
6
2
F
0

Any other
WCRTL Function

Any other
WCTRL Function

Figure 18-1
This concludes the discussion of the Condition Code logic.

19-10

VAX-11/750 LEVEL II

Memory Subsystem

Student Workbook

Course produced by Educational Services Department
of

Digital Equipment Corporation

·+6V

-f

BATTERY
INTERNAL DATA BUS 39 BITS
'INT DB <31 :O>
TIMING &
CONTROL

TOTI

----

REFRESM, !NIT/_..................,....
ROW, COLUMN MUX

CONTROLLER
MIC ROSE QUENCER
ROM

REF.

ROW
ADD&
INIT

UWORD

11-+--.INT BUS ADD

ADD
LATCH

;<6:0>&
'INT BUS CS TIM
INT BUS
ADD
MEM SEL
........-.--- FNGPJ

'A <23:17>

1>..._,_- MEM PRES

ROM
DATA

256 x 4

ROMO

ROM 1

256 4
ROM2

256 x 4
ROM3

:CONFIGURATION
ERROR

,_
,_
START ADDRESS
JUMPERS

ARRAYS--....
T K ·4667

Memory Subsystem

BANK3
16K X 32

1
.-.111!!!----1111A

BANK2
16K X 32

1
7

eAr;HC3
16K X 7
CHECK
BITS

BANK2.
16K X 7
CHECK
BITS

BANK
SELECT,
DECODE)
LOGIC
I

MA<15:145

BANK 1
16K X 32

1N"rB·us·A"ob1 M.EMSEL.

BANK 1
16K X 7
CHECK
BITS

BATTERY

1 ··-...

+~
INT.BUSA[fb-.
<6:0>&
INT BUS CS TIM

BANKO
16K X 32

7·

BANKO
16K X 7
CHECK
BITS

TK-45158

20-2

Memory Subsystem

p_HVSICAL r,1EM_Q~Y MAI'.'

Z56KB
256_K_8·
~~-~~

~~-~'
~K~
~_KB:
~1(8,

JfFFFft

251.KI·

•

F21>Q90!

CSRQ:

E~QQQ4l

CSRl

F20008!
-·---

CSR2

~~i

DE\(ICE"A" aOQT ROM

F20500i

o_t;y1ce ."8~.'- BOOT ROM

f.20600!

DEVICE "C" BOOT ROM

F~~~OO;

QEVICE '~P"_J~OQT ROIVJ
• . •I-

TK~560

20-3

Memory Subsystem

Vee

16
14

2
DIN

OUT D

•

AO
A1
A2
12

10
·13

A3
A4
A5
A6

(4116/64
·.16K x 1

MOS
RAM

A7
RAS

CAS

TK..t559

20-4

Memory Subsystem

Comet Memory Microprogram Functionality
Function

Purpose

IDLE

NOP

0000

CSR 1 WR

WRITE TO CSR 1 (F20004)

0001

CSR 0 WR

WRITE TO CSR 0 (F20000)

0010

CSR RD

READ CSR 0, 1, 2

0011

ROM RD

ASSEMBLE BOOT ROM LONGWORD

0100

UNUSED

!NIT

UNUSED

MEM 4 BYTE WR

LONGWORD WRITE, MASK=llll
(ECC)

1000

10. MEM 4 BYTE WR

LONGWORD WRITE, MASK=llll
{ECC OFF)

1001

11. REFRESH

REFRESH DYNAMIC RAMS

1010

12. BYTE WRITE

ANY WRITE OTHER THAN LONG

1011

13. MEM READ DIAG PG

DIAGNOSTIC PAGE MODE

1100

14. MEM READ DIAG PG

DIAGNOSTIC PAGE MODE

1101

15. MEMORY READ

READS A LOCATION

1110

16. MEMORY READ (ECC)

READS A LOCATION (ECC OFF)

1111

Entry Address

0101
WRITE ALL ZEROS

0110
0111

Figure 20-6

20 6

01 00

_____...____...______.._____._____...__...1_1......,·1 PHYSICAL ADDRESS
23

..l------------------------.....111
15 14

09 08 07

COLUMN ADDRESS

PHYSICAL ADDRESS <1 :O>

1E;>K RAM CHIP ADDRESS

ROW ADDRESS

16 K CHIP SELECT (0-3)
INT BUS CS TIM

•

17 16

ARRAY BOARD SELECT & FINGER
PRINT LOGIC SELECT ARRAY
BOARD

20 19 18 17

II I I I
3

ROW ADDRESS

COMPLETE ADDRESS

Cl>

a
0
...,
'<

INT BUS CS TIM
ARRAY
SELECT

(/)
~

O-

en
'<
[/)

rt
Cl>

16K CHIP
SELECT

TK-~555

Memory Subsystem

Check Bit Code Generation Algorithm
(Refer to Check Bit Generation Chart)
Desired Parity
EVEN
EVEN
ODD
ODD
ODD
ODD
EVEN

Cl = 1,
C2 = 1,
C4 = 1,
ca = 1,
Cl6 = 1,
C32 = 1,
CT = 1,

IF THERE IS AN ODD NUMBER OF ONES IN ROW 1
IF THERE IS AN ODD NUMBER OF ONES IN ROW 2
IF THERE IS AN EVEN NUMBER OF ONES IN ROW 3
IF THERE IS AN EVEN NUMBER OF ONES IN ROW 4
IF THERE IS AN EVEN NUMBER OF ONES IN ROW 5
IF THERE IS AN EVEN NUMBER OF ONES IN ROW 6
IF THERE IS AN ODD NUMBER OF ONES IN ROW 7
Figure 20-8

20-8

Byte 3

Byte 2

Byte 1

Byte 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 18 9 8
Row

Row 2

Row 3

x x x x
x x x x
x x x x x x x x

Row 4
Row 5
Row 6
Row 7

N
tSl

x x

x x
x

" CT C32 Cl6 ce C4 C2 Cl

7 6 5 4 3 2

x x
xx

Check Bits

xxxx

x x x x x x xx xxxxxxxx
x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x xx
x
x
x x
x x
x
x
x x
x
x x
x
xx
x

e e

e o e

e e

0 0

0 0 0

e e 1 e i

e e e

e e e e e e e

SYNDROME

NORMAL READ EXAMPLE
0

CHECK CODE

WRITE DATA EXAMPLE

\.0

e e e o e e

e e 0 0 0 0 1 0 I e e

DROP BIT <0>
0

(1)

:::J
(1)

'OJ
"""

()

::r
OJ

'rt
"""

" ""
0

PICK BIT <16>
0

0
0

PICK BIT <I>
0

......

:::J

" DROP CB <2>

0
"

" " ""
0

" 0

" " 0 0 " l " " 1

fi)

3
" 0 " " " 1 1 l 0

" " " 0 " l

D-1
~

0 1 1

{/)

o" " " 0 " 1 " 1 0

rt
CD

Memory Subsystem

Memory System Single Bit Error Syndrome Chart
Bit Position
In Error

CSR 0 <6:0>
Syndrome

Hex
Syndrome

0
1
2
3
4
5
6
7

1011000
0011001
0011010
1011011
0011100
1011101
1011110
0011111

58
19
lA

8
9
10
11
12
13
14
15

ll0HH'.J0
0101001
0101010
1101011
0101100
1101101
11011HJ
0101111

68
29
2A
68
2C
6D
6E
2F

16
17
18
19
20
21
22
23

1110000
01100fH
0110010
1110011
01HH00
1110101
1110110
0110111

70
31
32
73
34
75
. 76
77

24
25
26
27
28
29
30
31

0111000
1111001
1111010
0111011
1111100
0111101
0111110
1111111

38
79
7A
38
7C
3D
3E
7F

Figure 20-10

20 10

SB
lC
SD
SE

Memory Subsystem

MEMORY SYSTEM SINGLE BIT ERROR SYNDROME CHART
24
25
26
27

28
29
30
31

0111000
1111001
1111010
0111011
1111100
0111101
0111110
1111111
Figure 20-11

20--11

38
79

7A
38
7C
3D
3E
7F

VAX-11/750 LEVEL II

Writable Control Store

Student Workbook

Course produced by Educational Services Department
of

Digital Equipment Corporation

Writable Control Store

INTRODUCTION
The Writable Control Store (WCS)
is an optional
extension of the control store that permits the customer
to design his own microroutines or macro instructions
that use WCS microcode.
The WCS interfaces to the CMI
for data input and output •.
The WCS RAM data is connected to the control store bus
lines and is enabled when control store address bit 13
is asserted.
The WCS module is a daughter board
connected to the motherboard module via 4 signal
connectors, the mother board is the 6K x80 main control
store module located within the CPU.

21-1

Writable Control Store

OBJECTIVES
From a list of statements concerning
identify each statement as true or false.

the

WCS,

Provided with the laboratory procedure, write a
program to transfer 10 Comet CPU microinstructions
from main memory to wcs.

SAMPLE TEST ITEM
Identify the following statements as true or false.
a)

In order to store one microinstruction
WCS, 8 CM! bus cycles are required.

The WCS address register has
register address of 2C hex.

Microinstruction execution speed is slower
when
executed
from
WCS
because
of
interfacing with CM!.

The base address of the WCS module in the
CMI memory space is FE0000.

RESOURCES
WRITEABLE CONTROL STORE
SCHEMATIC DIAGRAM

21-2

the processor

Writable Control Store

OUTLINE
XXI.

WRITEABLE CONTROL STORE (WCS)
A.
B.

D.
E.
F.

WCS Specifications and Characteristics
CMI Interface
Memory Address Allocation
Control Store Interface
Programming Examples
Laboratory Exercise 16
1. Write a routine to transfer 10 Comet
microinstructions from memory to WCS
2. WCS Fault Isolation
Summary

21-3

CPU

Writable Control Store

WCS Module Functionality
The WCS module is a daughter board that attaches to the main
control store module in the CPU.
Loading the WCS is
accomplished by writing the desired WCS data on the CMI with
the destination of the wcs.
Data contained within the WCS
may be read onto the CMI and transferred to memory for
comparison with input data if so desired.
Loading one 80 bit microinstruction into WCS requires 4 CMI
write cycles because the WCS rams are loaded sequentially 20
bits at a time.
This means that bits 21 to 31 of the data
are ignored.
Bit 20 has a special function that will be
discussed later.
Refer to Figure 22-1, the WCS block diagram. At the left of
the drawing are CMI interface drivers to receive and
transmit to and from the CMI. The received address and DBBZ
are used to activate the WCS Control logic when a transfer
of data to or from the WCS occurs.
Basically the chip
enables and write enables are generated on CMI writes to WCS
so that CMI data is sequentially loaded into the rams from
left to right.
The WCS rams can be addressed from two sources; either from
the microsequencer (CSA<9:0>) or the CMI address latch.
Naturally when loading or reading WCS, the address latch is
gated through the two to one mux and becomes the ram
address.
The WCS ram data output has two destinations, the
DPM module control store latches and an interface to the
transmit side of the CMI.
Some of the technical spec if ications that one should be familiar with are:
1.

WCS ram read access time is to 70 - 90ns.

Module timing is derived from CPU B clock.

No parity bit generation or checking

To understand the functionality of the WCS CMI interface
let's design an example program to load one 80 bit microinstruction into WCS address 2000, refer to figure 22-2
which is the comet physical memory organization and locate
hex address F00000 on the left of the drawing, this is the
I/O address for WCS.
It extends from F00000 to F03FFC
because 4 longwords are required to load one WCS location.
Our example program will require 4 longwords of data to

21-4

Writable Control Store

build one microinstruction.
The next question is, where is
WCS address 2000 and how do we load WCS address 2000 from
the CM!?
Simple, refer to Figure 22-3, the control store
memory allocation.
Note that WCS address 2000 is the first
location of WCS from the control store side.
From the CM!
side,
locations
F00000,
F00004,
F00008,
and
F0000C
correspond to WCS address 2000.
Remember 4 longword writes
are required to load one WCS location.
Examine the
following macro code l ist1ng, Figure 22-3.
Note that the
microinstruction itself is irrelevant, but the code that
loads it is what we want to study.
This subroutine is
rather useless but could be doctored up so that parameters
can be passed to it. Each time the instruction on line 1700
is executed, a CMI write to WCS occurs.
The address bi ts
<l :0> are irrelevant on the CMI because of longword
alignment.
Bits <3:2> of the CMI address lines are used to
sequentially load the WCS rams.
Refer to the following
table.
LOAD WCS RAM

CMI ADDRESS BITS

BITS

<19:0>

=
=
=
=

<39:20>
<58:40>
<79:60>

Since the program is using autoincrement addressing mode
this will automatically sequence through and load 20 bits at
a time into the WCS Rams, it is important to insure that the
macro program set the pointer to WCS to double quad word
boundaries, that is, initially the pointer must be as
follows •••
CMI ADDRESS
BITS
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
1 1 1 1 0 0 0 0 0 0 x x x x x x x x x x 0 0
This insures that the correct longword is loaded into the
proper location in WCS.
The 2nd part of the program reads
the data written into WCS and compares it with the data in
the table to verify that the WCS was properly loaded.

21-5

Writable Control Store

Reading and writing WCS both drive the chip enable decoder
shown in the block diagram Fig. 22-1.
Writes to the WCS
enable the upper WCS data drivers, while reads enable the
lower data drivers RAMS to the CMI.
Reading the RAMS is
possible provided the CPU microcode is not running out of
wcs. This will be the rule rather than the exception. The
microwor~ parity bits <79:78> must be contained in the data
transferred to WCS because there is no parity generator
within the WCS module.
Execution of the microinstructions from WCS is similar to
that of any microinstruction in the main control store. The
WCS is enabled any time the next address is 2000 to 23FF
Hex, refer to Fig. 22-5, Comet Control Store addressing.
Bit 13, if set, indicates a WCS address.
Since the WCS is
only lK, bits <12:10> are irrelevant.
Bits <9:0> directly
address the RAMS.
the beg inning of the discussion we mentioned bit 20 of
the WCS data transmitted to WCS had special meaning.
This
bit sets a flip-flop called WCS PRESENT whose output goes to
the microsequencer.
The flop is used for a microbranch
condition called WCS PRESENT.
It will be used in the
situation where if the macro vector bits <1:0> = 2 and there
is no WCS present a ·console halt occurs.

To summarize, the basic function of the WCS is to provide
the customer with capability of creating his own micorcode
programs to enhance performance.

21-6

Writable Control Store

TOBYTLOGIC
CMI

CHIP
.
ENABLE.::
DECOD_ER

<3:2>

wcs
PRES

wcs

DATA
DRl'{ERS

WRITE
ENABLE
DECODER

CSA<9:0>

1K
X·
20

:X
20

OOUT

DOUT

OOUT

TIMING

CONTROL!

wcs
DATA
STATUS
<1:0>

DRIVERS

CS<t3>
H

- ·- ··-

CONTROL STORE OUTPUT TO DPM

1K X 80
WRITEABLE CONTROL STORE BLOCK DIAGRAM

Figure 21-1.

lK X 80 Writable Control Store Block Diagram

21-7

TK-2096

Writable Control Store

toJIJDO
2511<8

Q:JF!IFfl
oaoDDO
07flflflF
OlllOOO

1 ..i.RRAY :!OARO

5121(11
7881(8

QlllllllFF

ocoooo

102•KB

FFllflfl
IOOGOO
13'11P:F
14IOCCIO
17flFFir
tlOOOO

12801<8
15311<1

,,,,,,

1m1C1

ICOOllO
1f1Firfll'

21>'!11<1
MAXIMUM flUL.L. Y POPUl.A TED ARRAYS

irooaao

IC Kl WfllTUIU CONTROL. STORE

FIOODO

'4EUOflY CONFIGURATIO~ REG. A

F2QOQO
FDlQ4

MIMOflY CONFIGURATION 'iEG. 3

F20DDI

MIMO"V CONFIGURATION REG. C

F2DIGO

800TST"Att ROM PROGRAM

P:DllllO

MASS1US .l.DAPTOR C INT. REGISTERS

fllta

MASS1US ADAl'T'Ofl 0 EJCT. Fl!GlSTeRS

1112811111

MASSllUS .ADAPTOR 0 MAP REGISTERS

lllAOOO
MASSIUSAOA"1"0FI 1 EJCT. REGISTEFl!i

F'2MOD
~

F2CDDD

MASSIUSAOAl'TOI' 2 INT. i'IEGISTERS

F2CQi

""'558USADAl'1'0fl 2 EXT. "IEGISTERS

lllaOO

MASSIUS ADAPTOR 2 MAP REGISTERS

F3QODO

F3DQGl.C

UNIBUS DATA l'ATM CONTROL 9i ST.iTt:S

11300t'"IC

UNllUS DIAGNOSTIC REGISTERS
UNllUS MM" REGISTERS

F30lllll

~~r

iit;~l~~,,~W:!~·'

F3ZOQO

:;?NO UNllW OATJ. PATH CONT. ST.lo

F3201•

2ND UNllUS DIAGNOSTIC REGISTERS

F32D

F80000

2NO UNtlUS MEMORY SPAC~

1211<W

UNllUS MEMORY
SPACE 1281CW

COMET PHYSICAL MEMORY ORGANIZA ~!ON

Figure 21-2.

Comet Physical Memory Organization

21-8

Lll/l l>

ANO VER I f"t

\ffS

!OO

.......

\.0

"i::I
......
lQ
c

'""
CD

.......
I

H
81

Hrl

82
01

HF5
50

0000
00000000
00
000'8
JOO
Ol)Ot 2l45 000 ' ' 400 TABLE Ii
0002 3456 0004 '--600
oo·oe 608
OOOJ4:i~7
000456 9 oooc
10
0010
800
OOJO
900
0010
04 0010
too INlTt
oorooooo ~o
uo 0012 ~00
Of
E4 Af
DE
0019
00
05 goto
500
OU
EF' Af
16 oou:
600 STAR'U I
82
DO
ts II

roo

0.1
50

f'l

88H
0021

f.l At'
81

oop
00 0

DO
05
04
05

002

!'188°°

OOl

381~
OOH'

DMA0t(8[NJCOMWCS.MARJil

.TITLE LOAD AND V!Rtrr
.PSECT ALIGN LOHQ

wcs

.t.ONG "'XOOOUl4!S

~80t. 1 ~nu, CfU )+
ACBL

(1)

ITHIS TABLE REPRESENTS 1 80 8JT

CLRk
RO
HOV l"XF000001 Rt
HOV L TABLE, R2

PAGE

I MICROINSTRUCTION

• LONO "'XOOOl l45?
,LONG "XOOOl456
tLONO "X0004567

RSB

VAX•ll MACRO vo2.10

h, I • RO, U:

ITHIS LONGWORD MUST INCLUDE THE
tPROPER PARITY IN BITS <l9tl8>
IACCORUING TO MICROCODE RP~C
THIS SETS UP LOOP COUNT ETC.
rooooo ls 1u1 PASE CMI ADDREss

1ur NCS

oc TION o.

'
IWRITE DAJA FROM TABLE
)LOOP i T M!S TO WRITE

lo LONGWORDS
WCS

1900

l?g8 2UI
0010 h 8
230
OOl~

0018
0036

~g:~u~=til~ 8ltll111

USS Un

IREAD we& AN COMPARE TO TABLE DATA
llF tRROR, CLf.AR RO AND RETURN

#NO ERROR, DO A NORMAL RETURN

(J)

rt
0

'CD""

Writable Control Store
MICROWORD

80 B1TS
, ____________
_A_____________
AMOUNT
16K

ADDRESS

3FFF

~~~~~~~~~~~~~~

12K

23FF

2000

21-10

Writable Control Store

NEXT FIELD

~1-~:q>

- -- ---

- -- --- -·-·-

9~_,_~ ADOR_~ss. l,.09ATION WffHIN CHI~
·---

------------CtflP_ARRAY_SELECT,_ 1!( BANK OF CHIPS

-ccs-

CONTROL STORE SELECT

_ _o,___==- ~cs____________________ _

1312·1110.

-1_~-~~~qcs,

oa o a

1ST K

0 0 0 1
0 0 1 0

2NO K
3RD K

-0 • 0 1 1_

4TH K

Q; 1 0

6TH K

a i er o
1

0 1d}
f

0 ,. 1 1

COMET CONTROL STORE ADDRESSING

Figure 21-5.

Comet Control Store Addressing

21-11

Siif-i<
-NOT-USED

DATA

ADDRESS

--.

DATA

STATUS VALID

FUNCTION

DBBZ·L

BCLKL

J
;-"

ADDRESS

SELECT
WCSL
LOAD ADDRESS
LATCH(BCLKN )

.....
I

.....

TIME 1L

TIME 12H

"ll

l
~

TIME 2H

.....
"""

er
.....

\
WRITEH

n
0

WRTCLK L

CHIP ENxL

WRT ENxl

~LOAD RAMS

l ENABLE CHIP IN J
ll

ENABLE WRITE

::s

0
"""
I-'
Cll

CD
"""

STATUS

ADDRESS
&
FUNCTION

•

RETURN READ
DATA

READ DATA

BCLK L

DBBZ-L

ADDRESS

i SELECT WCS L

N
I-'

LOAD ADDRESS
LATCH H

I
I

I
,_

~,....,.

I-'

TIME 1L

TIME 12H

I
1.

TIME 2H

'ac

'......
""'

rt
DJ

O"
I-'

CD
(')

WRITE H

::s

DRIVE CMi L

CHIP ENxl

I
I

READ RAM

I
I

'""'
......
0

C/l

rt
0

'CD""'

VAX-11/750 Level II

Power Systems

Student Guide

Course Produced By Educational Services Department
of

Digital Equipment Corporation

Power Systems

Power System

INTRODUCTION
The VAX-11/750 power sys.tern lesson consists of a block
diagram of power distribution including memory battery
backup and the power cells for the time of year clock.
After a classroom lecture, a lab will be utilized to
troubleshoot power system failures.

OBJECTIVES
Given a system that won't power up, isolate the malfunction
and replace the faulty field replaceable unit.

SAMPLE TEST ITEM
The time of year receives its power from
a.
b.
c.
d.

+5 V supply
+12 V supply
1.5 V dry cells
Battery backup

RESOURCES
1.

VAX-11/750 System Maintenance Guide

VAX-11/750 Power System Technical Description

24-1

VAX 11/750 POWER SYSTEM
-COMPONENTS-

A.C. POWER
CONTROLLER

+2.5V POWER SUPPLY
ASSEMBLY

+5V POWER SUPPLY
ASSEMBLY

.i::.
I
N

BLOWER
·MOTOR
!AIR FLOW
'SENSOR

TOY
'CLOCK

BATTERY
BACKUP
UNIT

;BATTERY
!CHARGER

(OPTIONAL)

TOY
BATTS'

TK-4723

"'O
0

~
(I)

t'1

Figure 24-1

Power Components

rt
<D

VAX 11/750 POWER SYSTEM·

Ac;_ powr;~ P~~Iftl~UTIQ~L/
115VAC/23.0VAC IN

OPTIONAL/
REMOTE

A.C. POWER
CONTROLLER

ASSEMBLY

+5V POWER SUPPLY/
ASSEMBLY
_
t

AC
_

SW
AC

+2.5V POWER SUPPL

SWITCH i
1
CONTROL

________________________---'

BLOWER
MOTOR
AIR FLOW
SENSOR

BATTERY
BACKUP
UNIT

TOY

(OPTIONAL)

CHARGER

CLOCK

TOY

BATTERY

BATTS':
6V
"O

TK-4724

Cl>
!""(

Figure 24-2

AC Distribution

(/)

rt
Cl>

VAX 111750 POWER SYSTEM
DC POW~~ plSTRIBUTION

r::::\

BIASI
. . . - - - - - - VOLTAGES!
+2.5V POWER\ +12VA, +5VA\

A.C. POWER'
CONTROLLER

BLOWER
MOTOR !
AIR FLOW'
SENSOR

SUPPLYr·· ..

~·

BACKUP

+5V POWER I

SUPPLY[""

A~SEr~13~ YI

BATTERY ;

+5V, 135Ai _

AS~EM_(3_~ YI

TOY

-....

+15V, 2A! __

-15V, 3.5A\ __

TOY

~ CLOCK . - - BATTS'
BATTERY'~
5
CHARGER
V
.__

·~

UNIT
. 30V
(OPTIONAL)

.....

.li

+2.5V +5V~
85A
10A
,~

-5VB +12VB TO
1.2A 10A
TOY
CLOCK

TK""4714
(/)

Figure 24-3

DC Distribution

'<
C/l

rt
CD

C/l

Power Systems

CONTROLLER INDICATORS
Overvoltage (red)

Indicates that there is an
overvoltage condition in either
th~ +2.5V or +5V power supply.
The correct voltage of the
failing box will not be present.
Also,
the
appropriate
fail
indicator will be. on.

Overcurrent (red)

Indicates that there is an
overcurrent condition in. either
the +2.SV or +5V power supply.
The failing box will nott have
an
output.
Also,
the
appropriate indicator will be
on.

DC OK (green)

- Indicates the power system is
in correct functioning order.
If any other status indicator is
on, this indicator is off.

+5 Fail (red)

- Indicates the +SV power supply
is malfunctioning.
The SV box
will not have a correct output.

+2.5 Fail (red)

Indicates the +2.5V ppower
supply is malfunctioning.
The
2.5V box will not have a corret
output.

Plug in reg fail (red)

- Indicates that either the .±.5
volt, +12 volt, or +14 volt
regulator is malfunctioning.

Overtemp indicator (clear)

Indicates an overtemperature
condition in either the +2.5
volt or +5 volt power supply.

AC Power Indicator (amber)

- Indicates that AC is applied
to the controller. It is on and
remains on as long as the AC
power ~ord is plugged in and AC
is present.

24-5

Power Systems

VAX 11/750 POWER SYSTEM
SENSING
AC LOW
OPTIONAL
---..,, REMOTE

DC LOW

SENSE

OVER TEMPERATURE SENSE

STATUS
CONTROL +2.SV POWER
A.C. POWER ...__ _ _-t SUPPLY"
,__...... CONTROLLER
ASSEMBLY

STATUS
SENSE

+5V POWER
SUPPLY
ASSEMBLY

BATTERY
.BACKUP ENABLE

BLOWER
MOTOR
AIR FLOW

·SENSOR
AIR
·FLOW
SENSE

BATTERY
BACKUP
UNIT
(OPTIONAL)

TOY
CLOCK
BATTERY
CHARGER

TOY
BATTS'
6V

TK-4713

Figure 24-4

Power Sensing

24-6

Power Systems

+2.5 VOLT POWER SUPPLY .
.. ...., ____

----.----- ····-··-----·--·--------·-.,-,·

DC LOW

AC LOW

~OVERT~MPERATURESENSE

VOLT AGE/CURR ENT STATUS
.-.
..
.
REGULATOR STATUS

_ +12VA BIAS VOLTAGE

2.5 V CONTROL
BOARD

__ -12VA BIAS VOLTAGE

. -

__ +SVA BIAS VOLTAGE

2.SV MOTHER
BOARD

AC IN FROM CONTROLLER

6PfiONS

.+12 v
,...;3_0_V_F_R_O_M_____. - - -...llllll. REGULATOR

+5 VOLT
REGULATOR

.'BATTERY BACKUP
'BOX

BOARD

:aoARD

L
I

STATUS SENSE
FROM +5V SUPPLY

"'---r---.A...__,.1-~-..L-~-....J

__Jt____
+12VB
10A

l _.

+5VB ;-5VB
·1.2A l 10A

+2.5V
85A
. -·-

TK-4716

Figure 24-5

+2.5 Volt Supply

24-7

Power Systems

;+5 VOLT POWER SUPPLY

+5VA BIAS VOLTAGE
-12VA BIAS VOLTAGE
+12VA BIAS VOLTAGE

VOLTAGE/CURRENT STATUS

...

_REGULATOR STA_TUS

+SV CONTROL BOARD

+SV MOTHE.R BOARD

OVERTEMPERATlTFfE SENSE

OPTION
AC IN FROM CONTROLLER __

±15 VOLT
REGULATOR
BOARD

l
.J.

+15V
2A

I
..t +

-15V
3.5V

+5V
135A

TK-4715

Figure 24-6

+5 Volt Supply

24-8

VAX 11/?~~ P9WER SYSTEM
'OPTIONAL
------u-iREMOTE.SENSE

- - - - - : : • AC LOW
_ _ _.......
..,DC LOW
OVERTEMPERATURESENSE

115VAC/230V A.G

g_.
o---

~!~.'-N___..~__.~

BIAS

.....

OPTIONAL
REMOTE
r-+ SWITCH
A.C. POWER
CONTROL
CONTROLLER
__ STATUS

+2.5V POWER
SUPPLY
ASSEMBLY

·~"---..--...--~-CONTROL

SW SW AC

VOLTAGES
,±.12VA,
+5VA --~----1 +5V, 135A..,
""'
+5V POWER

_.,Ji..-_ _...._......

STATUS
SENSE

SUPPLY
ASSEMBLY

----t J

4•'··-

+15V,2A

-15V, 3.5A
.....

ACL-------------tf--L-t-t-;-;-----------BATTERY BACKUP
ENABLE

BLOWER

MOTOR

AIR

AIR FLOW
SENSOR

BATTERY
BACKUP
UNIT
(OPTIONAL)

TOY
CLOCK
BATTERY

30V

CHARGER

:::·

~·

.TOY
BATTS'
6V

FLOW
'SENSE

,r
+2.5V
85A

-=5vs :+5VB +12VB TO
1.2A

hoA

:10A

to<:

TOY
CLOCK

rt
CD

TK-4721

Figure 24-7

Total System

VAX-11/750 LEVEL II

Appendices

Course produced by Educational Services Department
of

Digital Equipment Corporation

Appendix A
Vectors and System Control Block
System Control Block Format
Vector

Description

SCBB+0
SCBB+4

SCBB+8
SCBB+c
SCBB+l0
SCBB+l4
SCBB+l 8
SCBB+lC
SCBB+20
SCBB+24
SCBB+28
SCBB+2C
SCBB+30
SCBB+34

Not used
Machine Check
CS Parity
Bad Ird
Memory Error
Cache Parity
Kernel Stack Invalid
Power Fail
Reserved Opcode
Customer Opcode XFC
Reserved Operand
Reserved Address Mode
Access Violation
Translation Invalid
Trace Trap
Breakpoint Opcode
Compatability Mode
Arithmetic Trap

SCBB+40
SCBB+44
SCBB+4 8
SCBB+4C

CHMK
CHME
CHMS
CHMU

lF
lF
lF
lF

E
E

SCBB+54
SCBB+60

Corrected Read Data
Write Bus Error

lA
lD

I
I

SCBB+84
SCBB+88
SCBB+8C
SCBB+90
SCBB+94
SCBB+98
SCBB+9C
SCBB+A0
SCBB+A4
SCBB+A8
SCBB+AC
SCBB+B0
SCBB+B4
SCBB+B8
SCBB+BC

Soft
Soft
Soft
Soft
Soft
Soft
Soft
Soft
Soft
Soft
Soft
Soft
Soft
So ft
Soft

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt

IPL

I/E

lF
lE
lF
lF
lF
lF
lF
lF
lF
lF
lF
lF

3
4
5

6
7

8
9
A
B

c
D
E

I
E
E

E
E
E

E
E

SCBB+C0

Interval Timer

SCBB+F0
SCBB+F4
SCBB+F8
SCBB+FC

TU-58 Receive
TU-58 Transmit
Console Receive
Console Transmit

17
17
14
14

I
I
I
I

SCBB+l60
SCBB+l64
SCBB+l68

Massbus Adaptor 0
Massbus Adaptor 1
Massbus Adaptor 2

15
15
15

I
I

SCBB+200

14-1 7
Unibus
(SCBB+200+Unibus Vector)

I
I

Appendix 8
Vector Operation
If Vector bits <1:0> are as follows •••
Vector bits <1:0>=0
Vector bits <1:0>=1
Vector bits <1:0>=2

Vector bits <1:0>=3

Use Kernel Stack unless IS bit = 1
Use Interrupt Stack
Trap to WCS location 2001, if WCS is
not present or disabled, trap to
Remove
location 0001
in CS.
backplane jumper from slot 5 844 to
848 if WCS is installed.
Halt at Vector
(PC po in ts to
interrupted instructio~ or faulted
instruction

Appendix C
Machine Check and Write Bus Error
Logout Area and Error Codes.G.
Machine Check Exception Stack Logout Table
(SP)
(SP)+4
(SP) +8
(SP) +C
(SP)+l0
(SP)+l4
(SP)+l8
(SP) +lC
(SP)+20
(SP)+24
(SP) +28
(SP) +2C
(SP) +30

LENGTH PARAMETER
SUMMARY PARAMETER
VA
PC
MOR
SAVED MODE REG
RLTO
TBGPR
CAER
BER
MCESR
PC
PSL

00000028
0000000X

xxxxxxxx
xxxxxxxx
xxxxxxxx

0000000X
0000000X
0000000X
0000000X
0000000X
0000000X

SUMMARY PARAMETER
1 = cs Parity Error
2 = Memory Error
3 = Cache Parity
4 =Write Bus Error
5 = Corrected Data
7 = Bad IRD

xxxxxxxx
xxxxxxxx

ACV OR TNV
Translation Not Valid or Access Violation exception stack
logout
(Exception Service from Vectors t4 and 20
Respectively)
(SP)
(SP) +4
(SP)+8
(SP)+l2

Error Code (See Below)
Virtual Address Referenced
Program Counter
Processor Status Longword

Error Codes:

Read Access Violation or XB Access
Vioiation or PTE Fetched not valid for read
l= Accessing System 1 Space (Sl) or length
Violation
2= No Access to Process Page Table (from SPTE)
3= Process PTE VA not in System Virtual Space
4-7= Same as 0 to 3 but for write access rather
than read access
0=

COMPATABILTY MODE TRAP
Compatabilty Mode Stack Logout
Vector 30)
(SP)
(SP) +4
{SP) +8

(Exception Service from

Error Codes (See Table Below)
Program Counter
Processor Status Longword

Error Codes:

0= PDP 11 Reserved Operand
l= Breakpoint Opcode Executed
2= I/0 Trap
3= Emulator Trap
4= Trap
5= Reserved Instruction (HALT)
6= Odd Address Referenced

ARITHMETIC TRAP
Arithmetic Trap Stack Logout (Exception Service from Vector
34)
(SP)
(SP) +4
(SP) +8

Error Code
Program Counter
Processor Status Longword

Error Codes:

0= Undefined
l= Integer Overflow
2= Integer divide by zero
1= Floating Overflow
4= Floating/Decimal divide by zero
5= Floating Underflow
6= Decimal Overflow
7= Subscript Out of Range

Appendix D
Console Commands
The Comet system has console functionality simil iar to the
VAX 11/780. These commands are illustrated below with
examples.
Commands
The console prompt is the same as the VAX 11/780
">>>" and appears at the beginning of every line.
"AP"

Enter Comet Console mode

"AD"
ROM>

Enter RDM console mode

>>>E

Examine Command

>>>D

Deposit Command

>>>I<CR>

!nit Command, Invalidates TB, Cache,
and does Processor Ini t and Unibus
!nit

>>>T<CR>

Te st Command, Runs Micro Verify
Microroutine explained below

> >>S 1000 <CR>
>>>S<CR>

Start command, The command may have
a n add res s a r g um en t f o 11 ow i n g o r
carriage return. If a carriage
return is typed, the address in the
PC

used.

The

start command

does

an init sequence before going to
IRDl of the macroinstruction pointed
to by the PC.
> >>C <CR>

The Continue command is the same as
starts
the
start
command
and
macrocode execution at the address
in the PC.

> >>N <CR>

This command is used to single step
the macroinstructions after the PC
is loaded.

>>>B<CR>

The Boot command in this example
will boot the device selected by the
front panel DEVICE switch

>>>X

Apt Load and Dump Command

Command Switches for Examine and Deposit Console Commands
Size switches

/B
/W
/L

sets the data size to byte
word
long

Function

/G
/I
/P
/V
<SP>P

GPR
IPR
Physical Memory
Virtual Memory
PSL

Command Switches for Boot Console Command
>>>B/X DDCU<CR> Boot Device selected by DDCU typed
at console and inhibit Micro Verify
Test.
>>>B/n DDCU<CR> Boot Device selected by DDCU typed
at console and pass a four digit
number as software control flags to
VMB.EXE in RS
> >>B DDCU<CR>

Boot device specified by operator

Examples
>>>D/G/L F 1000<CR>
>>>D/P 1000 005251D0<CR>
> >>E/I 25<CR>
>>>I<CR>
>>>B/10/X DMA0<CR>

;Put 1000H in PC
;Put code in address 1000H
;Examine cache disable Reg
;Do !nit sequence
;Boot Diagnostic Supervisor
;without Micro Verify from
;DMA0

CONSOLE COMMAND ERROR CODES
If an illegal console command is attempted or command is
aborted because of a microtrap or some other condition a
two digit error code is typed out and the console waits
for new input. For example •••
>>>E P<CR>
>>>E<CR>
?11
>>>

!Examine PSL
!Implies Examine Next Location, this is illegal.
!Question Mark and error code is typed by console
!At this point ready for new command
7

Error Codes

20=

Deposit or Examine of Memory Failed
( Access Vi o 1 at ion , Trans 1 at ion no t v a 1 id ,
Bus Error, TB Parity Error, or Control
Store Parity Error)
11= Illegal ?CCess of an IPR
30= Apt Loading Checksum error
33= Attempt to Boot from unknown Device type
(DM,DL,DT,DR)
3 4 = B0 0 t Dev ice Cont r 011 er n 0 t " AII , " Bn , " c" , 0 r
"D"

MICRO VERIFY

The following table indicates the microtest
sequence during micro verify. If a test
failure occurs, the PC is replaced with an
error code and the failure letter is typed.
Micro Verify then merges to console front end
flows.

Normal Test sequence as appears at console after power up
with FPSl set to HALT
%%

00000000 16

>>>
Test
in Progress
1.

2.
3.
4.
5.
6.
7.
8.
9.
HJ.

11.
12.
13.

14.
15.
16.

Test Name

Fail Character

R-Bus, W-Bus, D Reg Tests
@
M-Bus, Q-Reg Test
c
Scratchpad Test
E
Scratchpad Explicit Address Test Mtemps F
Scratchpad Explicit Address Test Rtemps I
Scratchpad Explicit Address test IPRs
J
Scratchpad Explicit Address test GPRs
L
Dual Port Address Test
L
XB,IR, and OSR tests
0
XB,PC, and PC+Isize test
Q
D-Size Tests
R
D-S i ze Te st s
T
Cache Parity Checker Test
X
TB Parity Checker Test
[
Control Store Parity Checker Test
]
Cache Test

Test Failure sequence would appear at console as follows

This indicates a failure of the Mtemp Scratchpad
address test.
00000XXX FF
PC contains loop count or point at which test
>>>
failed and "FF"
indicates micro verify
failure.
CONSOLE HALT Error Codes that are typed upon execution of
the following conditions:
Code=00
Control P while in console mode
Code=01
Execute TEST console command
Control P Halt or single macroinstruction mode>>>N<CR> Code=02
Code=04
Interrupt Stack Not Valid
Halt Instruction Executed
Code=06
Code=07
Vector Bits <1:0>=3, Halt at Vector
Code=08
Vector Bits <1:0>=2, WCS disabled or not present
Code=0A
Change Mode Instruction executed on Interrupt Stack
Change mode instruction executed and vector <1:0>not=0 Code=0B
Code=QJF
Double Bus Write error halt
Code=ll
Power up and can't find RPS, FPSl at RESTART/HALT
Power up and warm start flag false FPSl at RESTART/HALT Code=l2
Code=l3
Power up and can't find good 64K of memory
Code=l4
Power up and booting, but bad or no Boot ROM
Power up and cold start flag· set during boot subroutine Code=lS
Code=l6
Power up halt FPSl at HALT position
Code=FF
Micro verify test failure
The format for entering console mode is that the PC is typed
and a two digit error code is immediately following. For
Example •••
00010004
>>>

The preceding example indicates that a halt instruction was
executed at location 10003.

Appendix E
ROM Console Command Summary
Control Key Functions
Control
Control
Control
Control
Control
Control

D
P
U
0
R
C

Control S
Control Q

Enter ROM console mode.
Enter Comet Console Mode
Abort current Command Line
Inhibit Printing of text
Retype current command line
Cancel current function (Repeat console
command)
Disable CPU output to active T~rminal
Continue Output to Terminal after Control

ROM Console Commands
RDM>TE
RDM>TE/C

Load and Run Microdiagnostics
Load Micromoni tor and go to Micromoni tor
parser

MIC>
RDM>TE FILENAME.EXT
Load different monitor program and
transfer control to it. {WCS Debugger
etc.)
RDM>LOA FILENAME.EXT <PHYS ADDRESS>
Load RTll file from TU-58 into CM! memory
at <PHYS ADDRESS>. If no address is
specified, default is 0
RDM>TA

Enable Talk mode between local and Remote
Terminal (Used during RD session)

RDM>E

Examine Command, the following are valid
Examine command switches
E/B <ADDRESS>
E/W <ADDRESS>
E/L <ADDRESS>

RDM>D

Data size is byte
Data size is word
Data size is long

Deposit Command, the following are valid
Deposit command switches
D/B <ADDRESS> <DATA>
D/W <ADDRESS> <DATA>
D/L <ADDRESS> <DATA>

Data size is byte
Data size is word
Data size is long

RDM>SE 2001

Set micromatch address
generate scope sync

RDM>TR

Trace until micromatch, dumps DCS RAM for
64 Rom States prior to micromatch, most
recent microaddress is printed first.

RDM>CL

Clear stop on Micromatch

RDM>STE

Single Microinstruction cycle

RDM>STE/T

Single Tick Clock

RDM>STO

Stop CPU Clock

RDM>CON

Restart the CPU clock

2001

and

RDM>PAR <CS ADDRESS>
Perform a Parity Scan of the control
store
beginning
at
the
location
specified. There is bad parity written
into location 1 ?FD so that is where the
parity scan stop.
RDM>UA <CS ADDRESS>
Reads the control store microinstruction
at the <CS ADDRESS and latches the
microinstruction. Clock is stopped.
RDM>UA/C <CS ADDRESS>
Similiar to above except microinstruction
is not latched.
RDM>INI

Do a processor !nit
Ini t)

RDM>SH

Displays CPU control store address of
current microinstruction, and next field
of the next microinstruction. (Clock must
be stopped.)

RDM>SH/V

Displays the version and date of the RDM
8085 rom macrocode.

RDM>REP

Repeat
the
continuously

last

console

command

RDM>R E/B 0

Repeat the
continuosly

current

console

command

(same as Front Panel

RDM>RET

Return to program I/O mode

RDM>RET/D

Return to program
microbreak set.

I/O

mode

but

leave

RDM CONSOLE ERROR CODES
Tape function errors
TAP: 01
TAP:02
TAP: 03
TAP:04
TAP: 0 5
TAP:06
TAP:07
TAP:08
TAP:09
TAP: 12
TAP:l3
TAP:l4
TAP:C9
TAP:D0
TAP: DF
TAP:E0
TAP: EF
TAP:FS
TAP:F7
TAP:F8
TAP: EE
TAP:FF

UART - Device timeout
UART - Error from UART
UART - Data Set Ready dropped
UART - Receive Overflow
Tape checksum error received
Tape count byte exceeded maximum
Tape no end packet, invalid operation
Tape invalid packet received
Tape file not found
Tape Directory Error
Tape flag received, not command or data
Tape Read Length Error, not all records
fit
Tape Bad Record number
T~pe Bad Operation Code
Tape Motor stopped
Tape Block not found
Tape Data check error
Tape write protocol error
Tape cartridge not present
Tape Bad Unit number
Tape End of medium
Tape diagnostic failure

Terminal Error Codes
TRM: 0A
TRM: 08
TRM: 0C
TRM: 0D
TRM: 0E

Terminal
Terminal
Terminal
Terminal
Terminal

Control C received
Command input buffer overloaded
Control D received
Command Input larger than buffer
Remote Line CRC error occured

CM! Error Codes
CMI:00
CM!: 01
CMI:02

Nonexistent memory
Corrected Read Data
Read Data Substitute

General Errors
SYNTAX ERROR
INVALID
COMMAND RDM
RDM: HJ
RDM: 11

Error in entering console commands
does not know the command just entered
Operation already in progress
Invalid operation code contained in Macro

Appendix F
Power Up and Boot Error Reports
FPS! set to either RESTART/BOOT or BOOT
%%%%

xxxxxxxx 13

This indicates that a good 64KB section
of memory was not found and return to
console mode

>>>
%%%%

xxxxxxxx 14

This indicates a failure or nonexistence
of the boot ROM

>>>
xxxxxxxx 06

If a halt instruction is executed after
typing a console

>>>

Boot command, this indicates a failure of
the read of logical block 0 from the
selected boot device. The PC should be
equal to the base address of the first
good 64KB of memory plus FX16 for TU58 or
FX20 for RK06. This failure occurs in the
Boot ROM routine.

VMS PRIMARY BOOT FAILURES
BOOT is the program name for VMS.EXE
The "F" indicates a fatal error and the type of error is
reported.
%BOOT-F-Unknown processor

Th is indicates that CPU
is
not
a
Comet
or
11/780,
check
SID
register
for
proper
jumpering in the CPU
type
field
on
the
Backplane.

%BOOT-F-Unexpected Exception

This indicates that one
of
the
following
exceptions occurred.
1.
2.

3.
4.
5.

Access Violation
Breakpoint Opcode
Reserved Operand
TBit Trap
Page Fault (TNV)

%BOOT-F-Unexpected Machine Check

This indicates some sort
of
machine
Check
occurred.
Check
all
adaptors using console
examine
and
deposit
commands. Probababl y a
timeout.

%BOOT-F-Nonexistent Drive

Self explanatory, Check
DEFBOO.CMD on 11/780 and
insure system disk is
drive being booted.

%BOOT-F-Unable to locate BOOT file

VMB
can't
find
[SYSEXE]SYSBOOT.EXE or
if bit 4 in RS is set,
VMB
can't
find
[SYSMAINT]DIAGBOOT.EXE

%BOOT-F-Bootfile not contiguous

Indicates
that
[SYSEXE]SYSBOOT.EXE or
[SYSMAINT]DIAGBOOT.EXE
is not contiguous on
system disk. Recopy . or
rebuild

%BOOT-F-I/O error reading boot file Indicates
problem
reading boot file from
disk by $QIO service.