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Document:	KA655 CPU System Maintenance
Order Number:	EK-306AA-MG
Revision:	001
Pages:	181
Original Filename:

OCR Text

KA655 CPU System Maintenance
Order Number EK-306AA-MG-001

digital equipment corporation
maynard, massachusetts

March 1989

The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation.

Digital Equipment Corporation assumes no responsibility for any errors that may appear in
this document.
The software, if any, described in this document is furnished under a license and may be used
or copied only in accordance with the terms of such license. No responsibility is assumed
for the use or reliability of software or equipment that is not supplied by Digital Equipment
Corporation or its affiliated companies.
© Digital Equipment Corporation 1989. All rights reserved.
Printed in U.S.A.
The READER’S COMMENTS form on the last page of this document requests the user’s
critical evaluation to assist in preparing future documentation.
The following are trademarks of Digital Equipment Corporation:

DEC
DECmate

MicroVAX
MicroVMS

UNIBUS
VAX

DECnet

PDP

VAXBI

DECUS

P/OS

VAXELN

DECwriter
DELNI
DEQNA

Professional
Q-bus
Rainbow

VAXcluster
VAXstation
VMS

DESTA

RSTS

DIBOL

RSX

Work Processor

DSSI

MASSBUS

MicroPDP-11

ThinWire
ULTRIX

Eflfiflan

ML-S1123

FCC NOTICE: The equipment described in this manual generates, uses, and may emit
radic frequency energy. The equipment has been type tested and found to comply with the
limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which
are designed to provide reasonable protection against such radio frequency interference when
operated in a commercial environment. Operation of this equipment in a residential area
may cause interference, in which case the user at his own expense may be required to take
measures to correct the interference.

This document was prepared using VAX DOCUMENT, Version 1.1.

Contents
Preface

Chapter '1 KA655 CPU and Memory Subsystem
1.1

Introduction ..........c.oiiiiiiiiiiniiieneeenenn.

1.2

KAGB55CPUFeatures.........cciiiiiiienrnneenenn.

1-7

Central Processing Unit (CPU) .....................

1-8

1.2.2

Clock Functions . .........iiiiiiieeeneeaennennnn

1-9

1.2.3

Floating Point Accelerator .............
... ... .....

1-9

121

- 1-1

1.2.4

Cache Memory .....c ittt ittt et et e e ieeeaens

1-9

1.2.5

Memory Controller. .. ...... ...

1-10

1.2.6

MicroVAX System Support Functions ................

1-10

1.2.7

Resident Firmware ................... [

1-11

1.2.8

Q22-Bus Interface ................. e e

1-11

1.3

KAB55Conmectors .........covivinrnietneaenennn

1-12

1.4

H3600-SACPUITOPanel .........ccovvivieerenennnn.

1-12

1.5

MS650-BA Memory ......c.ciii ittt

1-16

2.1

Introduction............ .0t

2-1

GeneralModuleOrder ............ ...

2-1

2.2.1

Module Order Rules for KA655 Systems ..............

2-2

2.2.2

Recommended Module Order for KA655 Systems .......

2-2

2.3

Module Configuration............
... ...
..

2-3

Chapter 2

Configuration

DSSIConfiguration ...........viiumerennmnnnneennns

2.4.1

Changing RF-Series ISE Parameters.................

2—6

2.4.2

Changing the Unit Number . ............ ...

... .....

2-7

243

Changing the Allocation Class . .....................

2-9

244

DSSICabling ..........ciiiiiiiiiiiiiiiiiiinn

2-10

2441
245

2.46
2.5

DSSI Bus Termination and Length ................

2-12

Dual-HostCapability ................ ...,

2-13

Limitations to Dual-Host Configurations ..............

2-14

Configuration Worksheet ................
... ... .. ....

2-14

Chapter 3

KA655 Firmware

Imtroduction..............c0iiiiiiinriirinnnecnnns

3-1

3.2

KA655 Firmware Features...... i

tas et

3-1

3.3

Halt Entry, Exit, and DispatchCode ...................

h et

3-2

ExtermalHalts ............. .. .00

iiieennnn.

3-3

Power-UpSequence ...........coiiiiiiininnnnnneannn

3—4

35,1

Mode SwitchSettoTest................... e

3.52

Mode Switch Set to Language Inquiry ................

3-5

Mode Switch SettoNormal . ................ e

3-6

- 8.53
36

te ettt

3-6

3.6.1

Bootstrap Initialization Sequence ...................

3-7

362

VMBBootFlags...........iiiiiiiiiiinininnnnn

3-8

3.6.3

Supported Boot Devices . ...........ciiiiiiin..

3-8

364

Autoboot.............
.. ..
i i i

3-9

3.7
371

3.72

Bootstrap.................... @

OperatingSystem Restart ...........................

3-11

RestartSequence .............c.iiiiiiiiiiiinann.

3-11

Locatingthe RPB.......... e ettt
e,

3-12

Consolel/OMode............... ettt e

3-13

881

Command Syntax.........o.oveiinunerennnneeenenns

3-13

382

AddressSpecifiers ...........cc0

3-14

3.8.3

Symbolic Addresses ..........cciiiiiiiiiininann

3-14

3.84

Console Command Qualifiers ............ et

3-17

3.85

ittt

Console Command Keywords .......................

3-19

ConsoleCommands ............c.0iiiiiinrnennnnnnn

3-21

391

BOOT........ii
it
ittt tneannaaaannas

3-21

392

CONFIGURE........ciiiiiiiiiiiiiiinenanenn

3-23

393

CONTINUE .......ci ittt titititieeanaannnn

3-25

394

DEPOSIT........cciiiiiii
it iiieieenaanannnn

3-26

395

EXAMINE ..........0ciiiiiiiinennnnn e

3-27

396

3.9.7

FIND ... ...
e i e e

3-29

HALT ...

3-30

e i eee e

3-33

3.9.8

= 1 7

3.9.9

INITIALIZE . . ...

3-31
...

3.9.10

MOVE ...

3.9.11

NEXT . .....ciiii

3-34

ittt ettt

3-36

3.9.12

REPEAT . .. ... it
it i,

3-38

3913

SEARCH ................. et ettt
e

3-39

3.9.14

SET ...
e e
e e e e

341

3.9.15

SHOW ...

3-44

3-47

3-48

3.9.18

UNJAM ... ...t
ittt et e e e

3—49

3.9.19

X—BinaryloadandUnload .......................

3-50

3920

!(Comment)........oiiiiiiiiiiin
it itinennn

3-52

3.9.16

START ... ..

3.9.17

TEST . ...

Chapter 4

Troubleshooting and Diagnostics

Introduction...............c.0
ittt iiiinnnnnnnn

4-1

General Procedures ..............
..
..

4-1

4.3

KA655 ROM-Based Diagnostics . ......................

4-2

43.1

DiagnosticTests . ..........
...
..

4-3

4.3.2

S o|¢

7S e,

4.3.3

Script CallingSequence . .................iiivan..

4-8

434

Creating Scripts.........coi ittt

4-10

4.3.5

Console Displays ..............

4-14

436

SystemHaltMessages ..............cciiiirno...

4-24

437

ConsoleErrorMessages..........ccovieneennnnn.

4-25

438

VMBErrorMessages.........uuuiiieiunenennnnnn.

4-26

AcceptanceTesting...........
...
.

4-26

Troubleshooting .............
.. ...

451

4-31

... i,

4-31

4.5.2

Isolating Memory Failures . .. ................c.....

4-34

4.5.3

Additional Troubleshooting Suggestions...............

4-37

4.6.1

FEUtility.......

Loopback Tests............ ..t

TestingtheConsolePort ................

oo,-

4-38

4.7

Module Self-Tests . ... .o v it ittt et et ettt e

4.8

RF-Series ISE Troubleshooting and Diagnostics ..........

440

4.8.1

DRVIST.........ciiiiiiii... @t

4-42

4.8.2

DRVE
X R ..ottt ittt

443

4.8.3

HISTRY .. oottt

teaaaas

4-44

4.8.4

ERASE . ...

445

4.8.5

PARAMS ..t
e e ettt e
e

4-46

it et it

et ittt e

e e

4.8.5.1

EXIT .......... e

447

HELP . ...ttt
ittt eetetnaaanns

4-47

SHOW ..t

4-48

4.8.5.5

ST AT US . .ottt
et it e e
e ee

448

4.8.5.6

WRITE . ... e
e

448

DiagnosticErrorCodes ............
... .. .
L..

449

4.9

Appendix A
Al
A.1.1

e e

4-38

4.8.5.2

4854

e e e

iee e

Configuring the KFQSA

KFQSA OVervieW . ... ...ttt iitnnteneeeeeasenenans
Dual-Host Configuration ................ e

A-1

e e

A-2

A.2

Configuring the KFQSA at Installation .................

A-2

A21

EnteringConsole/OMode ...............
... .. ...

A-4

A.2.2

Displaying Current Addresses ......................

A-5

A.2.3

Running the Configure Utility ......................

A-6

A.3

Programmingthe KFQSA .........
... ... .. . . ...

A-8

Reprogrammingthe KFQSA ............
... .. .. ... .. A-15

A.5

Changing the ISE Allocation Class and Unit Number . .. ... A-17

Appendix B

KA655 CPU Address Assignments

B.1

General Local AddressSpaceMap .....................

B-1

B.2

Detailed Local Address SpaceMap ....................

B-2

B.3

Internal Processor Registers ..............
... .. .. ...

B-6

B3.1

KA655VAX StandardIPRs ...............
... ......

B-9

B32
B.4

EKA655UniquelIPRs........

... . . ... B-10

Global Q22-Bus Address SpaceMap ................... B-11

Appendix C

Related Documentation

Index

Examples
2-1

Changinga DSSINodeName ........................

2-2

Changinga DSSI Unit Number .. ..........coovvnn....

2-3

Changing a DSSI AllocationClass . ....................

3-1

Language SelectionMenu .............
... iiio....

3-2

SelectingaBootDevice ...........
... ... ...
..

4-1

Creatinga Script with Utility OF . . ................ e

4-2

Listing and Repeating Tests with Utility OF .............

4-3

Console Display NoErrors).............ccoiiiiion.
..

Sample Outputwith Errors ..........................

4-5

FEUtilityExample .........
... 0.,

4-6

Isolating Bad Memory UsingT9C.....................

4-7

9C—Conditions for Determining a Memory FRU .. ... ... ..

A-1

KFQSA (M7769) Service Mode Switch Settings ...........

A—2

Entering Console Mode Display ................ e

A-3

SHOWQBUSDisplay ..........cciiiiiiiinnn..

A—4

ConfigureDisplay

A-5

Display for Programming the First KFQSA ..............

A—6

Display for Programming the KFQSA in a Dual-Host
Configuration
(Second System) .......................

A-7T

SHOWQBUSDisplay .......ciiiiiiiiiiin
e

A-8

SHOWDEVICEDisplay .........c.oiiiiiiiinnn..

A-9

Reprogramming the KFQSA Display ...................

............ .0t

-A-10 Display for Changing Allocation Class and Unit Number .

vii

_Ei_gy res

1-1

KA655 CPU Module (M7625-AA) . .. ..oovveeeennnnnn..

1-2

KA655 CPU Functional Block Diagram .................

1-3

KA655 System-Level Block Diagram, PartI .............

1-5

1-4

KA655 System-Level Block Diagram, PartIT.............

1-6

1-5

KA655PinOrientation .............................

1-12

1-6

H3600-SACPUI/OPanel ..............
.. ...,

1-13

1-7

MS650-BA Memory Module (M7622-A)

1-17

2-1

DSSI Cabling, BA213 Enclosure ......................

2-11

2-2

RF-Series ISE Operator Control Panel (OCP) ............

2-12

2-3

BA213 Configuration Worksheet ......................

2-16

4-1

EKA655CPUModule LEDs................. e
ee e

4-18

A-1

KFQSA Module Layout M7769) ............covvvu....

A-3

A-2

Dual-Host Configuration Nodes and Addresses (Example)...

A-9

................

Tables
1-1

H3600-SA Controls and Connectors ...................

1-14

1-2

H3600-SA CPU I/O Panel Switches. . ..................

1-15

2-1

DSSIDeviceOrder..............
i
iinnnnn.

2-5

2-2

RF-Series ISE Switch Settings........................

2-5

2-3

Power and Bus Loads for KA655Options ...............

2-15

8-1

ActionsTakenonaHalt ...............cviiunnnn... -

3-2

Language Inquiry on Power-UporReset ................

3-5

3-3

Virtual Memory Bootstrap (VMB) Boot Flags ............

3-8

3—4

Boot Devices Supported by the KA655-AA ..............

3-9

3-5

Console Symbolic Addresses. . ...........cciiviiien..

3-15

3-6

Symbolic Addresses Used in Any Address Space ..........

3-17

3-7

Console Command Qualifiers . ..............cc.....

3-18

3-8

Command Keywordsby Type............
...
...,

3-19

3-9

Console Command Summary ...............c.ccvuu....

3-19

4-1

Testand Utility

Numbers ................
... ...,

4-4

4-2

Scripts Available to Field Service......................

4-7

4-3

Commonly Used Field Service Seripts . .................

4-8

Values Saved, Machine Check Exception During Executive . . 4-17

4-5

Values Saved, Exception During Executive ..............

viii

4-17

KA655 Console Displaysand FRUs . ...................

4-19

4-7

System Halt Messages . . ... .....cciiiiiiiiinnnenn.

4-24

Console Error Messages . . .. ....ciiiiiiiininnennnnnn

4-25

4-9

VMBError Messages . ... ..o iiiiitneeeeenenenenns

4-26

4-10

Hardware Error Summary Register.

. .. ................

4-33

4-11

Loopback Connectors for Q22-Bus Devices. ..............

4-39

412 DRVTST Messages . . .. ..coitiiiiiiinineneneennennnns

4-42

DRVEXR MesSsages ........uiiitmtntmenenennennnnns

4-43
444

4-13
4-14

HISTRY Messages . ..o vvviiiiiiiitinenenanennennns

4-15

ERASE Messages . . ..o vviiin it eiieeteineneneneenns

4-46

4-16

RF-Series ISE Diagnostic ErrorCodes . . . ...............

4—49

VAX Memory SpPace ... .ovviiitinentneeneennnenenn.

B-1

VAX Input/Output Space ...........cc

...

B-2

Detailed VAX Memory Space .. ....ouvveeeenennnennn..

B-2

Detailed VAX Input/Qutput Space . ....................

B-3

KA655 Internal Processor Registers. . ..................

B-7

IPRs Implemented According to Standard VAX Architecture.

B-9

KA655 Unique IPRS . .. ....... .ttt
iiien.

B-10

Q22-Bus Memory Space . . ........
it i

B-11

Q22-Bus I/O Space with BBS7 Asserted ............. ...

B-11

Preface
This guide describes the base system, configuration guidelines, ROM-based
diagnostics, and troubleshooting procedures for systems containing the
KA655 central processing unit (CPU).

Intended Audience
This document is intended only for Digital Field Service personnel and
qualified self-maintenance customers.

Organization
This guide has four chapters and three appendixes.
Chapter 1 describes the KA655 CPU and the MS650-BA memory.

Chapter 2 contains system configuration guidelines and provides a table

listing current, power, and bus loads for supported options.
Chapter 3 describes KA655 diagnostic firmware.

Chapter 4 describes the KA655 diagnostics, including an error message
and FRU cross-reference table. It also describes diagnostics that reside on

RF-series integrated storage elements (ISEs).

Appendix A explains how to configure the KFQSA storage adapter.
Appendix B contains a list of KA655 CPU address assignments.
Appendix C contains a list of related documentation.

Warnings, Cautions, and Notes
Warnings, cautions, and notes appear throughout this guide. They have
the following meanings:

WARNING

Provides information to prevent personal injury.

CAUTION

Provides information to prevent damage to equipment or software.

NOTE

Provides general information about the current topic.

Chapter 1

- KAG655 CPU and Memory Subsystem

| 1.1 Introduction
This chapter describes the KA655 central processmg umt (CPU) and the
MS650-BA memory.
The KA655 CPU module (M7625-AA), shown in Figure 1-1, is a quadheight VAX processor for the Q22-bus (extended LSI-11 bus)
It is
designed for use in high-speed, real-time applications and for multiuser,
multitasking environments.
The KA655 employs a cache memory to
maximize performance.

KA655 CPU and Memory Subsystem

1-1

Figure 1-1:

KA655 CPU Module (M7625-AA)

'MEMORY CONNNECTION

CONSOLE CONNECTION

CONSOLE SERIAL
LINE CONNECTION

é:;'/"‘“

LEDs

EPROM

Ly] 2]

‘J_;lCOND
CACHE
LEVEL

Of:

SSC

CCLK

CVAX

CFPA

CQaBIC

CMCTL

MLO-002367

1-2

KA655 CPU System Maintenance

Figure 1-2 shows a functional block diagram of the KA655 CPU.

Figure 1-2:

KA655 CPU Functional Block Diagram
A<16:2>

+ E—=I\J
A<31:25

—l/

SECOND
LEVEL

SYSTEM

CACHE

SSCDAL<31:0> J SUPPORT

|/1

CONSOLE PANEL

\—\z;“/ SUBSYSTEM \,

|sscoaLxcvrs

@L__

CPUEFPA N/

CLOCK

CDAL<31:0>

[ conTROL BUS

l"—‘/ INTERFACE

MAIN MEMORY

CONTROLLER

MAIN MEMORY

INTERCONNECT

MLO-002368

KA655 CPU and Memory Subsystem

1-3

The KA655 has two variants:
e

KA655-AA. Runs multiuser software.

KA655-BA. Runs single-user software.

The KA655 is used in two systems:
e

MicroVAX 3800 (BA213 enclosure)

MicroVAX 3900 (H9644 cabinet)

Refer to BA213 Enclosure Maintenance and H9644 Cabinet Maintenance
for a detailed description of the enclosure and the cabinet.

CAUTION: Static electricity can damage integrated circuits. Always use a
grounded wrist strap (part no. 29-11762) and grounded work surface when
you work with the internal parts of a computer system.

The KA655 CPU module and MS650-BA memory modules combine to form
a VAX CPU and memory subsystem that uses the Q22-bus to communicate
with I/O devices. The KA655 and MS650-BA modules mount in standard
Q22-bus backplane slots that implement the Q22-bus in the AB rows and
the CD interconnect in the CD rows. The KA655 can support up to four
MS650-BA modules, if enough Q22-bus CD slots are available. Figures 1-3
and 14 show the KA655 system-level block diagram.

'NOTE: The KA655 CPU supports only the MS650-BA (16 Mbyte) memory

module. The MS650-AA (8 Mbyte) is not supported because of its slower
access speed.

The KA655 CPU communicates with the console device through the H3600SA CPU 1/O panel, which contains configuration switches and an LED
display. The H3600—SA is described in Section 1.4.

KA655 CPU System Maintenance

Figure 1-3:

KAG655 System-Level Block Diagram, Part |
H3600-SA

COVER

CONSOLE

50-PIN CABLE

Micro VAX LOCAL MEMORY INTERCONNECT (32-bit data + 7-bit ECC)

MS650-8A

MSE50-BA

MS650-BA

MODULE

CPU/FPU
FIRST-LEVEL

SECOND-LEVEL

CACHE

F==—==

MS650-8A

MEMORY

53 )

MODULE

: Q22-bus
f

MAP

]
|

Q22-bus

INTERFA

|
_____

_ oz

o o

wls_

MicroVAX LOCAL MEMORY INTERCONNECT { ADDRESS )

Y Q22-bus / €D
¥ ALL BACKPLANE SLOTS

wlsS

A
[

w8
_

]

Q22-bus | 16-B1T DATA , 22 ADDRESS LINES , CONTROL , POWER )

(BACKPLANE

SERIAL
LINE

CONTROLLER

i
TM

3
4}

’

H3104
CABLE
CONCENTRATOR

\/
REMOTE TERMINAL

LOCAL TERMINALS

PRINTER

MLO-002369

KA655 CPU and Memory Subsystem

1-5

Figure 1-4:

KAG655 System-Level Block Diagram, Part li

OTHER
SYSTEMS

NETWORK
INTERFACE

Q22-bus

OPTIONS

CONTROLLER

N
B80COK

B8POK

BEVENT |

]

)

]

}

C—

{

]

L L25

}

B8A200-SERIES
ENCLOSURE

——

=l
s S @

KFQSA

= : =

STORAGE

TAPE

CONTROLLER

POWER
W

SUPPLY

_ -} - =

'd'
%
DCOK
RESET SWITCH

OPERATOR '\\
CONTROL
PANEL

Wi
\

N
TERMINATOR

MLO-002370

1-6

KA655 CPU System Maintenance

1.2 KA655 CPU Features

The KA655 CPU provides the functionality of the KA650 CPU, but
reduces the cycle time from 90 to 60 nanoseconds (ns), placing the KA655
performance at about 3.8 VAX Units of Performance (VUPs).
The major features of the KA655 CPU are as follows:
A VAX central processor with a 33-MHz clock rate that supports the
MicroVAX chip subset of the VAX instruction set and data types, plus
the following string instructions: CMPC3, CMPC5, LOCC, SCANC,
SKPC, and SPANC. The processor also supports full VAX memory
management with demand paging and a 4-Gbyte virtual address space.
A floating point accelerator with the MicroVAX chip subset of the VAX
floating point instruction set and data types.
A two-level cache consisting of a 1-Kbyte, 60-ns, first-level cache and
a 64-Kbyte, 120-ns, second-level cache. Both caches provide parity
protection on the tag and data stores.
A main memory controller that supports up to 64 Mbytes of 450-ns
ECC memory. The controller resides on the CPU module and supports
up to four MS650-BA memory modules, dependmg on the system
configuration.

A console port compatible with VAX processors. The console port has an
external baud-rate switch located on the CPU I/O panel (H3600-SA).
A set of processor clock registers that support:

— A VAX standard time-of-year (TOY) clock with support for battery
backup. (The batteries are located on the inside of the H3600-SA.)

—

An interval timer with 10-millisecond (ms) interrupts.

—

Two programmable timers, similar in function to the VAX standard
interval timer.

A boot and diagnostic facility with four on-board LEDs. This facility
supports an external 4-bit display and configuration switches located
on the H3600-SA. It also supports 128 Kbytes of 16 bit-wide ROM
containing programs for:
—

Board initialization

—

Emulation of a subset of the VAX standard console

—

Power-up self-testing of the KA655 and MS650-BA modules

—

Booting from supported Q22-bus devices

KA655 CPU and Memory Subsystem' 1-7

—

Help utility

—

KFQSA programming utility

A Q22-bus interface that supports up to 16-word block mode transfers
between a Q22-bus DMA device and main memory, and up to 2-word
block mode transfers between the CPU and Q22-bus devices. This
interface contains:
—

A 16-entry map cache for the scatter-gather map, which resides in
main memory. This 8192-entry map is used for translating 22-bit,
Q22-bus addresses into 26-bit, main memory addresses.

—

Interrupt arbitration logic that recognizes
requests BR7 through BR4.

—

An interprocessor communications facility that supports communication between the Q22-bus arbiter and up to three auxiliary processors by means of doorbell interrupts.

Q22-bus interrupt

1.2.1 Central Processing Unit (CPU)
The central processing unit (CPU) is implemented by the CVAX chip.
The CVAX chip contains approximately 180,000 transistors in an 84-pin
CERQUAD surface mount package. The chip achieves a 60-ns microcycle
and a 120-ns bus cycle at an operating frequency of 33 MHz. The chip
also supports full VAX memory management and a 4-Gbyte virtual address
space.

The CVAX chip contains all general purpose registers (GPRs) visible to the
VAX processor; the MSER, CADR, and SCBB system registers; the 1-Kbyte
first-level cache; and all memory management hardware, including a 28entry translation buffer.
|
The CVAX chip performs the following functions:

Fetches all VAX instructions

Executes 181 VAX instructions

Assists in the execution of 21 additional instructions

Passes 70 floating-point instructions to the CFPA60 chip

The remaining 32 VAX instructions (including h_floating and octaword) are
emulated in macrocode.

1-8

KA655 CPU System Maintenance

In addition, the CVAX chip provides the following subset of the VAX data
types:

Byte

Word
Longword
Quadword
Character string
Variable-length bit field

Support for the remaining VAX data types can be provided through
macrocode emulation.

1.2.2 Clock Functions
Clock functions are implemented by the CVAX clock chip (CCLK). The
CVAX clock chip is a 44-pin CERQUAD surface mount chip that contains
approximately 350 transistors. It provides the following functions:
¢

Generates two MOS clocks for the CPU, the floating point accelerator,
and the main memory controller

Generates three auxiliary clocks for other TTL logic

Synchronizes the reset signal for the CPU, the floating point accelerator,
and the main memory controller

Synchronizes data ready and data error signals for the CPU, floating
point accelerator, and the main memory controller

1.2.3 Floating Point Accelerator
The floating point accelerator is implemented by the CFPA60 chip.
The CFPA60 chip contains approximately 60,000 transistors in a 68-pin
CERQUAD surface mount package. It processes f, d_, and g_floating
format instructions and accelerates the execution of MULL, DIVL, and
EMUL integer instructions. The CFPA60 chip receives opcode information
from the CVAX chip and receives operands directly from memory or from
the CVAX chip. The floating point result is always returned to the CVAXchip.

1.2.4 Cache Memory
The KA655 CPU module contains a two-level cache memory to maximize
CPU performance.

The first-level cache is implemented within the CVAX chip. This cache is a |
1-Kbyte, two-way associative, write-through cache memory. It has a 60-ns
cycle time.

KA655 CPU and Memory Subsystem

1-9

The second-level cache is implemented using 16K x 4-bit static RAMs. This
cache is a 64-Kbyte, direct-mapped, write-through cache memory. It has
a 120-ns cycle time for longword transfers and a 180-ns cycle time for
quadword transfers.

1.2.5 Memory Controller
The main memory controller is implemented by a VLSI chip called the
CMCTL. The CMCTL contains approximately 25,000 transistors in a 132pin CERQUAD surface mount package. It supports up to 64 Mbytes of
450-ns ECC memory.

The ECC memory resides on from one to four 16-Mbyte memory modules
(MS650-BA), depending on the system configuration.
The MS650BA modules communicate with the KA655 through the MS650 memory
interconnect, which utilizes the CD interconnect by means of a 50-pin
ribbon cable.

1.2.6 MicroVAX System Support Functions
System support functions are implemented by the system support chip
(SSC). The SSC contains approximately 83,000 transistors in an 84-pin
CERQUAD surface mount package. The SSC provides console and boot
code support functions; operating system support functions; timers; and
many extra features, including the following:

Word-wide ROM unpacking

1-Kbyte battery backed-up RAM

Halt arbitration logic

A console serial line

An interval timer with 10-ms interrupts

A VAX standard time-of-year (TOY) clock with support for battery
backup

An IORESET register

Programmable CDAL bus timeout

Two programmable timers

A register for controlling the diagnostic LEDs

1-10

KA655 CPU System Maintenance

1.2.7 Resident FirmWare
The resident firmware consists of 128 Kbytes of 16 bit-wide ROM, located on
one 27510 EPROM. The firmware gains control when the processor halts.
It contains programs that provide the following services:

Board initialization

Power-up self-testing of the KA655 and MS650-BA modules

Emulation of a subset of the VAX standard console (automatic or
manual bootstrap, automatic or manual restart, and a simple command
language for examining or altering the state of the processor)

Booting from supported Q22-bus devices

Multilingual capability

The KA655 firmware is described in detail in Chaptér 3.
1.2.8 Q22-Bus Interface
The Q22-bus interface is implemented by the CQBIC chip. The CQBIC chip
contains approximately 40,870 transistors in a 132-pin CERQUAD surface
mount package. The CQBIC chip supports block mode transfers as follows:
¢

Sixteen words on memory write

Four words on memory read

Longword transfers between CPU and Q22-bus

The Q22-bus interface contains the following:

A 16-entry map cache for the 8192-entry scatter-gather map that
resides in main memory. The map is used for translating 22-bit, Q22bus addresses into 26-bit, main memory addresses.

Interrupt arbitration logic that recognizes Q22-bus interrupt requests
BR7 through BR4.

The Q22-bus interface handles programmed and power-up resets, and CPU
halts (deassertion of DCOK).

The KA655—-AA module contains 240-ohm termination for the Q22-bus.

KA655 CPU and Memory Subsystem

1-11

1.3 KA655 Connectors
The KA655 CPU module has three connectors:
e

J1. For the cable from the internal console SLU connector on the
H3600-SA CPU /O panel.

J2. For the cable from the configuration and display connector on the
H3600-SA. (Connects the CPU to the three switches and LED display
on the I/O panel.)
|

J3. For a cable from the first MS650-BA memory module.

The orientation of connectors J1, J2, and J3 is shown in Figure 1-5.
- Figure 1-5:

KA655 Pin Orientation

9
L L B

1
N

000506000

\ 2

..‘.O

..... ‘.0000

O 0000

OO OGO OSSOSO OOOE SOSGOSESOSIOSNOGIGS

| ,ic00000000000j®

8421
,

¢ ¢ 0 00 [ BN 2 N A J

2
J3

MLO-002371

1.4 H3600-SA CPU /O Panel
The H3600-SA CPU I/O panel, shown in Figure 1-6, has a ribbon cable
with two connectors that plug into the KA655 module console SLU and
console control connectors. The H3600-SA fits over backplane slots 1 and
2, covering both the KA655 module and the first of up to four possible
MS650-BA memory modules.
The controls and connectors on the H3600—SA are shown in Figure 1-6 and
listed in Table 1-1.

1-12

KA655 CPU System Maintenance

Figure 1-6:

H3600-SA CPU I/O Panel
POWER UP MODE SWITCH

LANGUAGE INQUIRY
NORMAL OPERATION

(FACTORY SETTING)

)

(T) LOOPBACK TEST

BREAK ENABLE SWITCH /'go

(DOWN=DISABLED)

LED DISPLAY |

SLU CONNECTOR\

CABLE TO

CPU

’
BAUD RATE
SELECT SWITCH

(9600 IS FACTORY

SETTING)

BATTERY BACKUP
UNIT (BBU)

LIST OF SWITCH SETTINGS
|
FOR BAUD RATES
0=300
1=600
2=1200
3=2400
4=4800

5=9600
6=19200
7=38400
MLO-002372

KA655 CPU and Memory Subsystem 1-13 |

Table 1-1:

H3600-SA Controls and Connectors

Outside

Inside

Modified modular jack (MMJ)
SLU connector

Cable to SLU connector on KA655

Power-up mode switch

Battery backup unit (BBU)

Hex LED display

Cable to console control connector on KA655

Enable/disable switch

Baud rate select switch

Enable/Disable Switch

Although the KA630, KA650, and KA655 CPU modules all use the H3600SA, the function of the enable/disable switch is slightly different in each
case:

When the H3600-SA is connected to a KA630 CPU, the switch enables
and disables halts from the
key on the console keyboard and from
the halt button on the system front panel. In MicroVAX II systems, the
switch is referred to as the halt enable switch.

When the H3600-SA is connected to a KA650 or KA655 CPU, the switch
enables and disables halts from the
key on the console keyboard
only. You cannot disable halts initiated from the halt button on the
system front panel. In MicroVAX 3500, 3600, 3800, and 3900 systems,
the switch is referred to as the break enable switch.

You also select the power-up mode and console terminal baud rate using
switches on the H3600-SA. Release the H3600—SA quarter-turn fasteners
and turn the H3600-SA around (do not disconnect the ribbon cable) to
change the baud rate of the console serial line, or to change the batteries for
the backup unit. The factory setting for the baud rate is 9600. Figure 1-6
shows the possible baud rate settings.
Hexadecimal LED Display

The LEDs display a hexadecimal number for each power-up test and stage
of the bootstrap process. Chapter 4 lists the meanings of these numbers.
Modified Modular Jack SLU Connector (Outside)

The modified modular jack (MMJ) is a six-pin connector for a cable that
connects to the console terminal.

1-14

KA655 CPU System Maintenance

Battery Backup Unit (Inside)

When the system is turned off, the battery backup unit (BBU) provides
power to the KA655 time-of-year logic (25.6-kHz oscillator, TODR register,
and 1 Kbyte of RAM in the SSC). The 1 Kbyte of RAM stores the code for
the language that is displayed in the console messages. If the BBU fails,
the code is lost.

Cable

The cable contains two connectors that plug into the console SLU and
console control connectors on the KA655 module. The 20-conductor end
connects the baud rate select switch, the power-up mode switch, and the
hexadecimal LED display to the console control connector (J2) of the KA655.
The 10-conductor end connects the console serial line to connector J1 on the
KA655.

Table 1-2 lists the H3600-SA switch functions.

Table 1-2:

H3600-SA CPU I/O Panel Switches

Switch

Position

Enable/disable

Dot outside

(two-position toggle)

Function

circle

Dot inside

(three-position
rotary)
|

Arrow

power-up or restart,

the system tries to

load software from one of the devices after
completing the power-up diagnostics.
Breaks are enabled. On power-up or restart,

circle

Power-up mode

Breaks are disabled (factory setting). On

the system enters console I/O mode after
completing the power-up diagnostics.

Run (factory setting). If the console terminal

supports the DEC multinational character set
(MCS), the system prompts the user for the
console language if the battery backup has

failed and upon initial power-up of a system
containing a new CPU. All start-up diagnostics
run.

Baud rate select

Face

Language inquiry. If the console terminal
supports the DEC MCS, the user is prompted
for the console language on every power-up and
restart. All power-up diagnostics run.

T inside
circle

Test. ROM programs run the wraparound
console serial line unit (SLU) tests.

300 to
38,400

Sets the baud rate of the console terminal serial
line. The factory setting is 9600 baud. The
baud rate of this switch must match the rate
of the console terminal.

KA655 CPU and Memory Subsystem

1-15

1.5 MS650-BA Memory
The MS650-BA (M7622-A) is a 16-Mbyte memory module that provides
memory for the KA655 CPU module. The MS650-BA is a nonintelligent
memory array module controlled by a custom memory controller chip
(CMCTL) on the KA655 CPU module.
The quad-height MS650-BA, shown in Figure 1-7, has a 450 ns, 39 bitwide array (32-bit data and 7-bit ECC), implemented with 1 Mbit dynamic
RAMs in surface mounted SOdJs.

Ordering Information
MS650-BA

16-Mbyte module only (M7622-A).

MS650-BF

Option installation kit for BA200-series enclosures. Includes MS650-BA, filler
panel assemblies, blank cover, CPU cable, labels, and installation guide.

Diagnostic Support
MicroVAX Diagnostic Monitor

Release 126 (version 3.01)

Self-test

'KA655 self-test

1-16

KA655 CPU System Maintenance

Figure 1-7:

MS650-BA Memory Module (M7622-A)

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MLO-002373

- KA655 CPU and Memory Subsystem

1-17

Chapter 2

Configuration
2.1 Introduction
This chapter describes the guidelines for changing the configuration of a
KAG655 system, and for configuring a dual-host system.

Before you change the system configuration,
following factors:

you must consider the

Module order in the backplane
Module configuration
Mass storage device configuration
If you are adding a device to a system, you must know the capacity of the
system enclosure in the following areas:
Backplane
I/O panel
Power supply
Mass storage devices

2.2 General Module Order
The order of modules in the backplane depends on four factors:
*

Relative use of devices in the system

Expected performance of each device relative to other devices

The ability of a device to tolerate delays between bus requests and bus
grants (called delay tolerance or interrupt latency)

®*

The tendency of a device to prevent other devices farther from the CPU
from gaining access to the bus

Configuration

2-1

2.2.1 Module Order Rules for KA655 Systems
Observe the following rules about module order:
e

Install the KA655 CPU in slot 1.

Install a MS650-BA memory module in slot 2. Install any additional
MS650-BA memory modules in slots 3 through 5.

Do not install dual-height modules in the CD rows.

The Q22-bus does not pass through the CD rows of the backplane in a
BA200-series enclosure. Install all Q22-bus modules in the AB rows. Install
dual-height grant cards in the AB rows only, or single-height grant cards
in the A row only.

2.2.2 Recommended Module Order for KA655 Systems
Here is the recommended module order for a KA655 system:

KA655
MS650-BA
AAV11-SA
ADV11-SA
AXV11-SA
KWV11-SA
DRV1J-SA
TSV05-SA
DMV11
LNV21
DEQNA/DELQA/DESQA-SA
DPV11-SA
KMV1A-SA, -SB, -SC
DZQ11-SA
DFAO1-AB
CXY08-AA
CXB16-M/CXA16-M
CSF32-M
LPV11-SA
DRV1W-SA
IEQ11-SA
ADQ32-M
DRQ3B-SA
IBQO1-SA

2-2

KA655 CPU System Maintenance

KLESI-SA
TQK50-SA/TQK70-SA
RQDX3-SA
|
KDA50-SA
KFQSA-SA
M9060-YA

2.3 Module Configuration
Each module in a system must use a unique device address and interrupt
vector. The device address is also known as the control and status register
(CSR) address. Most modules have switches or jumpers for setting the
CSR address and interrupt vector values. The value of a floating address
depends on what other modules are housed in the system.

Set CSR addresses and interrupt vectors for a module as follows:
1.

Determine the correct values for the module with the CONFIGURE
command at the console I/O prompt (>>>).
The CONFIG utility
eliminates the need to boot the VMS operating system to determine
CSRs and interrupt vectors. Enter the CONFIGURE command, then
HELP for the list of supported devices:
>>>

configure

Enter device

configuration,

Device,Number?

HELP,

or EXIT

help

Devices:

LPV11l

KXJ11

DLV11J

DZQ1l1

DZV11l

RLV12

TSVO05

RXV21

DRV11W

DRV11B

DFAQO1
DPV1l

DMV1l
RRD50

DELQA
RQC25

DEQNA
KFQSA-DISK

DESQA
TQK50

RQODX3
TQK70

KDAS0
TUS1E
DHV11

RV20

KFQSA-TAPE

KMV1l

IEQ11

DHQ11

CXAl6

CXB16

CXY08

VCBO1

QVSS

LNV11

LNV21

QPSS

DSV11l

ADV11C

AAV11C

AXV1lC
DRV11J

KWV11lC

ADV11D

AAV11D

VCBO02

QDSS

DRQO3B

VsvV21

IBQO1

IDV11A

IDV11B

IDV1iC

IDV11D

IAV11A

IAV11B

MIRA

ADQ32

DTCO04

DESNA

IGQ11

Numbers:

255,

default

Device, Number?

exit

See the CONFIGURE command in Chapter 3 (Section 3.9.2) for an
example 'of how to set the correct CSR addresses and interrupt vectors.

Configuration

2-3

The LPV11-SA, which is the LPV11 version compatible with the BA200series enclosures, has two sets of CSR address and interrupt vectors.
To determine the correct values for an LPV11-SA, enter LPV11,2 at the
DEVICE prompt for one LPV11-SA, or enter LPV11,4 for two LPV11SA modules.

See Appendix A for instructions on how to configure the KFQSA storage
adapter. Appendix A explains how to do the following:

Seta four-position switchpack on the KFQSA before you install it

Program the CSR addresses for all the system’s DSSI devices into
the EEROM on the KFQSA

Reprogram the EEROM when you add additional DSSI devices

See Microsystems Options for CSR and interrupt vector jumper or
switchpack settings for supported options.

2.4 DSSI Configuration
The KA655 CPU and memory subsystem support RF-series integrated
storage elements (ISEs) and the KFQSA storage adapter.
The RF-series ISEs are part of a series of mass storage devices based
on the Digital Storage Architecture (DSA). These devices use the Digital
Storage System Interconnect (DSSI) bus and interface. The term integrated
storage element is used because each DSSI ISE has an on-board intelligent
controller and mass storage control protocol (MSCP) server in addition to
the drive and the control electronics.

DSSI supports up to seven ISEs daisy-chained through a single cable to the
KFQSA storage adapter. The KFQSA is a protocol converter that supports
Q-bus protocols to and from the KA655 CPU and DSSI bus protocols to and
from the ISEs. The KFQSA contains the addressing logic required to make
a connection between the host and a requested ISE on the DSSI bus. DSSI
adapters can also be embedded on a CPU module, such as on the KA640.
Each ISE must have a unique node ID. The ISE receives its node ID from a
plug on the operator control panel (OCP) on the front panel of the BA200series enclosure. By convention, DSSI devices are mounted in the BA200series enclosures from right to left, as listed in Table 2-1.

2-4

KA655 CPU System Maintenance

Table 2-1:

DSSI Device Order

Device

Position

Node ID!

First

Right side

Second

Center

Third

Left side

1KA655 node ID = 7

If the cable between the ISE and the OCP is disconnected, the ISE reads the
node ID from three DIP switches on its electronics control module (ECM).
The node ID switches are located behind the 50-pin connector on the ECM.
Switch 1 (the MSB) is nearest to the connector. Refer to the RF30 or RF71
section in Microsystems Options for more information. Table 2-2 lists the
switch settings for the eight possible node addresses.

Table 2-2:

RF-Series ISE Switch Settings
Switch!

DSSI
Node ID

1(MSB)

3 (LSB)

-0

Down

- Up

1Up = toward the head disk assembly (HDA); Down = toward the drive module
2Normally reserved for the host adapter

NOTE: Pressing the system reset button on the front of a BA200-series
enclosure has no effect on ISEs. If you change a node ID, you must perform
- _a power cycle to enable the new node ID to.take effect.

The VMS operating system creates DSSI device names according to Dlan,
where a is the controller letter (A, B, C, and so on) and n is the unit number.

Configuration

2-5

You can gain access to local programs in the ISE through the MicroVAX
Diagnostic Monitor (MDM) or through the console I/O mode SET
HOST/DUP command. This command creates a virtual terminal connection
to the storage device and the designated local program using the Diagnostic
and Utilities Protocol (DUP) standard dialogue. Section 3.9.15 describes the
console I/O mode SET/HOST/DUP/UQSSP command and shows an example
of how to set host to the RF71 ISE through the KFQSA storage adapter.

2.4.1 Changing RF-Series ISE Parameters
Each ISE has a node name that is maintained in EEPROM on board the
controller module. This node name is determined in manufacturing from
an algorithm based on the device serial number. You can change the node
name of the DSSI device to something more meaningful by following the
procedure in Example 2-1. In the example, the node name for the RF71
ISE at DSSI node address 1 is changed from R3YBNE to DATADISK.
See Section 4.8.5 for more information about the PARAMS local program.
Example 2-1:
>>>

sho

Changing a DSSI Node Name

ugssp

UQSSP Disk Controller 0
-DUAQO

(772150)

(RF71)

UQSSP Disk Controller 1
-DUB1 (RF71)
|

(760334)

!The node name for this drive
lwill be changed from R3YBNE
'to DATADISK.

>>> set host/dup/ugssp/disk

Starting DUP

server...

1988

Digital Equipment Corporation

DRVEXR V1.1

6-MAR-1989