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EK-V5200-TM-PRE

November 1984

193 pages

Original

5.1MB

Document:	VAXstation I Technical Reference Manual
Order Number:	EK-V5200-TM
Revision:	PRE
Pages:	193
Original Filename:

OCR Text

..
EK-VS200-TM-PRE

-- -

VAXstation I
Technical
Reference Manual
PRELIMINARY

PLEASE RETURN TO

LIBRARY
CRG J TELESUPPORT
_ _ _V_NO--·~T~J

Prepared by Educational Services
of
DigittJI Equipment Corporation

Preliminary, November 1984

Copyright Digital Equipment Corporation 1984
All Rights Reserved
Printed in U.S.A.
The material in this document is for informational purposes and
is subject to change without notice; it should not be construed
as a commitment by Digitial Equipment Corporation.
Digital
Equipment Corporation assumes no responsibility for any errors
that may appear in this document.
NOTICE: The VAXstation I generates, uses, and may emit radio
frequency energy.
The equipment has been type tested and found
to comply with the limits for a Class A computing device pursuant
to Subpart J of Part 15 of FCC Rules, which are designed to
provide reasonable p(otection again5t such radio
frequency
interference
when
operated
in
a commercial environment.
Operation of this equipment in a residential area may cause
interference in which case the user at his own expense may be
required to tak.e measures to correct the interference.
Book production was done by Educational Services Development
Publishing in Marlboro, MA.
Th~

"-'

and

following are trademarks of Digital Equipment Corporation:

mamaama·¥
DEC
DECmate
DEC sys tern -1_0
DECSYSTEM-20
DECUS
DECwriter ..
DIBOL

MASS BUS
... PDP
P/OS
Professional
Rainbow
ReGIS
RSTS
RSX
TOPS-10

TOPS-20
UNIBUS
VAX
VAXstation
VMS
VT

Work Processor

-----("'

VAXstation I TECHNICAL .MANUAL
CONTENTS

PREFACE
CHAPTER l
l. l
l .··l .. l

l.2

CHAPTER 2

GENERAL INFORMATION
SY'STEM OVERVIEW • • • •
• Phys~cal D~scription .
. SPEC I FI CATIONS . . . . .

l-1
l. 3
l. 4

SYSTEM CONFIGURATION

2.1
INTRODUCTION . . . • • • . • • • • • • •
2·1
2.2
H9278·A BACKPLANE . . . . . . • • •
2-5
2. 3
KD32·AB CPU
. . • • . • • .
2-5
2.3.l
M7135·YA OAP . • . . . • .
2-6
2.3.l.l
Switches . . . . .
. • .
. • •
2·6
2.3.l.2
Microverify Jumper . . . . .
2-6
2.3.2
M7136 MCT Module • • • .
. . .
. . 2-9
2.4
MSVll·QA MEMORY
. • . . . •
2-9
2. 4. 1
Switches . . • • . . . . . . . • ·· .
2-9
2. 4. 2
Jumpers . . .
. . • . . . . 2-13
MASS STORAGE • . .
. • • . . . • • . . . 2-16
2.5
RQDXl Controller . . . . • . . . . • . . . 2-16
2. 5. l
2.5.1.1
Jumpers . . .
. . . . .
. . . 2-16
RX50 Diskette Drive . . . . . . . . .
2-16
2.5.2
2. 5. 3
RD52 Fixed·disk Drive
. . . . . . . . 2-17
VCBOl VIDEO CONTROLLER .
. . . .
. 2·17
2.6
2. 6. l
Switches . . . . . . .
. . . .
. 2-17
Memory Starting Address (MSA) . . . . ~ 2-19
2.6.l.l
2.6.1.2
CSR Base Address .
• • . •
. ~ . . 2-19
Display Density . . . . . . . .
·•
2"·20
2.6.1.3
OPERATOR I/0 DEVICES
. . . . .
2-21
2.i
VRlOO Video Monitor
. . .
. . 2-21
2. 7. 1
LK201 Keyboard
. . . .
. • .
2·22
2. 7. 2
VSlOX Mouse
. . .
i-22
2.7.3
LASO And LA100 Printers . . . . . .
2·22
2.7.4
OPTION MODULES . . . . . .
2-22
2.8
DEQNA Ethernet Controller . . . .
. . 2 · 22
2. 8. 1
Jumpers
...... .
• 2-23
2.8.l.l
DZVll Asynchronous Line Multiplexer . . . 2 - 2 5
2.8.2
Switches And Jumpers . . . . . . .
• 2 - 25
2.8.2.1
CHAPTER 3
3. 1

VCBOl FUNCTIONAL DESCRIPTION
OVERVIEW . . . .
i i i

. . . . . . . . . . . .

3. 1

VAXstation I TECHNICAL MANUAL
TIMING . . . . . . . •
. • . . . . .
3.2
Q22
·BUS/CPU
INTERFACE
.
.
•
.
. • .
3.3
Interrupt Controller . • . • . • .
3.3.l
Registers . • . . • .
. . . •
3.3.2
CSR
. . . .
. . .
. . . .
.
3.3.2.l
CRTC......
. . . . . . . . .
.
3.4
CRTC Timing . . . . ' .
3. 4 .1
VIDEO MEMORY . .
. . • • .
.
3.5
Scan Line M·a·p . . .
. . • •
.
3.5.l
Video Memory - Update Memory .
. ...
3.5.2
Video Memory - Video Refresh • . • .
.
3. 5. 3
Video
Memory
RAM
Refresh
.
.
.
•
.
.
3.5.4
Scan Line Map - Update .
. . .
. •
3.5.5
Cursor . . . . . . .
. • •
3. 5. 6
Cu r so r RAM · Wr i t e . .
.
3.5.7
Cursor RAM - Read
. . .
3. 5. 8
MOUSE . . .
. . . . . .
. . .
3.6
KEYBOARD
.
.
.
.
.
3.7
MONITOR . . .
. ......
3.8
Monitor Power Supply
. . .
.
3. 8 .1
Video Module Description . . • .
. .
3. 8. 2
Deflection Module . . . . . . . .
. .
3. 8. 3
Vertical
Deflection
.
.
.
.
.
3.8.3.1
Horizontal Deflection
. • .
.
3.8.3.2
Focus And Linearity Control
.
3.8.3.3
Blanking Control . . . . . . . . • . . .
3.8.3.4
Field Replaceable Units . . .
3. 8. 4
POWER
SUPPLY
. . . . . .
. . .
.
3.9
CHAPTER 4
4.1
4.2
4. 2. 1
4. 2. 2
4. 2. 3

4.2.4
4.2.4.l
4.2.4.2
4.2.5
4.2.5.l
4.2.5.2
4.2.5.3
4.2.5.4
4.2.5.5
4.2.5.6
4.2.5.7
4. 2. 6

3·4
3-5
3-8
3-9

3 .. l 0
3-12

3-12
3 -1.5
3-1·6
3-17
3·17
3·20
3 · 20
3- 24
3 • 24

3·24
3-26
3·27
3·30
3-30
3·31
3-33
3-33
3·34
3·36
3-36
3-36
3·37

PROGRAMMING INFORMATION
4-1
ADDRESS SPACE
4. 3
VCBOl REGISTERS
4.
4
Control And Status Register
. . . .
4-5
Cursor X Position . . .
• • • •
4•6
Mouse Position Register . . .
CRTC Registers . . . . .
. .. • • • • 4• 6
4·6
CRTC Address Register Pointer
4-8
CRTC Data Register . . . . .
4. 9
Interrupt Controller Registers .
4-9
I CDR .
. . .
. 4 - 10
I CSR . . • .
. • . .
. 4. 12
IRR
.
. 4. 12
IMR
4 · 13
I SR
. . .
• • 4 • 13
ACR . . . . . . .
4 . 13
Mode
4. 14
UART Registers .

.........

VAXstation I TECHNICAL MANUAL
Mode Registers lA And 2A • • •
Mode Registers lB And 2B • . . . . . .
Status/Clock Select Register A . • • •
Status/Clock Select Register B . . • .
Co~mand Register A . . • . • . . • . .
Command Register B . . . • • • . • • .
4.2.6.7
Transmit/Receive Buffer A • . • • • .
4.2.6.8
Transmit/Receive Buffer B
..•.
4.2.6.9
Interrupt Status/Mask Reg.ister . • • .
PROGRAMMING
. . . . . . . .
4•3
Cursor . . . . . . . . . . . . . 4. 3 .1
• •

4.2.6.1
4.2.6.2
4.2.6.3
4.2.6.4
4.2.6.5
4.2.6.6

CHAPTER 5

• 4-17

. 4-17
•
•
.
.

4-18
4-18
4-19
4 -19

4-20
• 4 - 20

MAINTENANCE

MAINTENANCE STRATEGY .
Service Features . .
. ....•. •
Diagnostic Structure • . . . . . .
5.2
MICROVERIFY . . . . .
. ...
5.2.1
Microverify Error Reporting
5. 2 •2
Monitor Display Errors .
5. 3
STANDALONE DIAGNOSTICS . .
5. 3. 1
Macroverify . . . . .
•
5.3.1.1
Running Macroverify
5.3.l.2
Macroverify Error Messages .
5. 3. 2
CPU Diagnostic . . . . . . .
5.3.2.1
Running The CPU Diagnostic
5.3.2.2
CPU Diagnostic Error Reporting
..
5. 3. 3
Memory Diagnostic . . . . . . . . . .
5 . 3. 3. 1
Ru ning The Memory Diagnostic . . .
5.3.3.2
Memory Diagnostic Error Reporting
5.4
VOS DIAGNOSTICS . . . . . . . .
5. 4 . 1
VCBOl Diagnostic (EHXVS) . . . . . .
5.4.1.l
Running The VCBOl Diagnostic . .
5.~.1.2
VCBOl Diagnostic Error Messages
s. s
MONITOR LED INDICATORS . . . . .
MONITOR ADJUSTMENT PROCEDURES
5.6
Power Supply . . . . . . . . .
s.6 . 1
5.6.2
Video Module . . . . . . . .
5.6. 3
Deflection Module . . . . .
Cutoff Preset (G2 Voltage) .
s.6. 3. l
Horizontal Frequency .
5.6.3.2
Contrast . . . . . .
5.6.3.3
5. 6. 3. 4
Horizontal Size
Horizontal Centering . . . . .
S.6.3.S
Vertical Height
5.6.3.6
Vertical Centering .
Horizontal And Vertical Linearity
S.6.3.8
Static And Dynamic Focus . . . . .
5.6.3.9
5.1
5 .1.1
5. l. 2

. 4. 14

. 4·16
. 4-16

5-1

. .

• •

. .
.
.
.

5- l
5-2
5. 3
5-4
5-6
5-6
5•7
5.7
5.9
5-9
5-10
5 -10
5-11
5 · 13
5. 16

5-16
• 5 . 18
5-22
. s.23

5-24
• 5 . 25
5-26

. 5-26
5-26
5-26

5-26
5-27
5-27
• S-28
5 - 28
5-28
'3. 2 8
. s -29

VAXstation I TECHNICAL MANUAL
5.7

TROUBLESHOOTING FLOW

. . . . . . . . . . . . 5-30
,

CHAPTER 6
6.1
6. l. l
6 .1. 2
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
6 . 3. 1
6.3.2
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6. 5. 3
6.5.4
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6. 8. 2
6.8.3
6.8.4
6. 8. 5
6.8.6
6.8.7
APPENDIX A

______,

REPLACEMENT

.............
.
...
..
. . . . . . .. . .. .
. ...
...
... ..........
...
. .. ...
.........
. ....
. . . .
. .
.
. .... . ..
...
. . . .. .. . .
. .
.
.
. .
........
. . . . .
.
. .. . ...
.
. .
.
.. ...
. .. .
. . .
...
. . .
. .. . . .
. . .
. . ... ..
.
. ...
. . . .
. . .
...
. . . .
. . .
. . . . . ....
.
.....

BACKPLANE MODULES
6-1
Module Removal .
6-1
Module Replacement
6-4
STORAGE SUBSYSTEM
6-6
Access
.
6-6
RD52 Removal
.
.
6-8
RD52 Replacement
6·12
RX50 Removal
6-17
RX50 Replacement
6-18
POWER SUPPLY
6-19
Power Supply Removal
6-19
Power Supply Replacement
. 6-20
BACKPLANE ANO SIGNAL DISTRIBUTION PANEL
6-22
Backplane Removal
.
. 6-22
Backplane Replacement
. . 6-25
COOLING FANS . .
.
. 6-27
Rear Fan Removal
. 6-27
Rear Fan Replacement
.
6-27
Front Fan Removal
6-29
Front Fan Replacement
6-31
PATCH ANO FILTER PANEL
. 6-32
Insert Removal . . .
6-32
.
Insert Installation
6-33
FRONT CONTROL PANEL
6-33
Control Panel Removal
6-33
. . 6-35
Control Panel Replacement
6. 36
. .
MONITOR .
.
Monitor Cover Removal .
6-36
6-36
EMI Screen
. .
6-37
Monitor Power Supply
6-37
Oef lection Module
. . 6-37
.
.
Video Module
.
6-38
CRT Cable
.
.
Replacement
.
6-38
Monitor Cover
0,

. . . .

....

GLOSSARY

INDEX

... .
. . . . .
. . .
. .
. . . .

''---

VAXstation I TECHNICAL MANUAL
EXAMPLES
2-1
2-2

One MSVll·QA Starting Address Selection
Two MSVll·QA Starting Address Selection

1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3. 5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3 - 16

vAX s t a t i 0 n I

. . 2 -10
•• 2-10

FIGURES

3-17

3-18
3 - 19

3-20
3-21
4 -1

4-2
4-3
4-4

4-5
4-6
4 - "7
4-8

• • • • • • • • • • • • • • • •

1.2

VAXstation I Block Diagram • • .
Backplane Configuration Example • • • •
H9278-A Backplane . . . • • • •
M7135-YA DAP Switches and Jumper . • • •
MSVll-QA Jumpers and Switches . • . • • . .
RQDXl Jumpers
. . .
. •.•••.•
VCBOl Switches . . . . .
. . .
.
VRlOO Monitor Rear Panel . . . . • . • • . .
DEQNA Jumpers
. . .
. • • .
DZVll Switches and Jumpers . . . . . • . . .
VCBOl Simplified Block Diagram . . . . . .
VCBOl Functional Block Diagram . . . • .
Simplified Timing Generator
. . • • . .
Q22-Bus Interface . . • . • .
CSR Read/Write . . . . . . .
. . . .
.
Video Memory Access Cycle
..
CRTC Horizontal Timing . . . . . . • .
.
CRTC Vertical Timing . . . . . . .
.
Display Mapping . . . . . .
.
Video Memory Write (Update)
. . .
.
Video Memory Read (Video Refresh)
. . . .
Video Memory Read (RAM Refresh)
..
Scan Line Map Write (Update) .
.
Cursor RAM Read/Write
. . . .
Mouse Construction .
Mouse Interface . . .
~ . . .
Keyboard Interface
. . .
Monitor Functional Block Diagram .
Video Module Block Diagram . . .
Vertical Deflection Block Diagram
Horizontal Deflection Block Diagram
MicroVAX Physical Address Space
VAXstation I Physical A,ddress Space
VCBOl 256 kB Address Space .
. . .
CSR Format . . . . . . . . . .
Cursor X Position Format . . . .
Mouse Position Register Format
CRTC Address Register Pointer Format
CRTC Data Register Format
IC::::>R Format

1-3
2-3
2-4
2-7
2-11
2-15
2-18
2-21
2-24
2-26
3-2
3- 3
3-4
3-6
3-11
3-12
3-13
3-14
3-16
3-18
3-21
3-22
3-23
3-25
3-26
3-28

.rii

3-29

3-31
3-32
3-34
3-35
4-1
4-2

4-3
4-~

4-s
4. 6

.. . -/

'~ - 9

VAXstation I TECHNICAL MANUAL
4-10
4-11
4-12
4-13
4-14
4-15
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31

...
. ..
. . . . . .

. . . .

!CSR Format .
.
. . .
. 4-10
Mode Registers lA and 2A Format
. 4-15
Status/Clock Select Register A Format
4-16
Command Register A Format
4-17
Transmit/Receive Buffer A Format . .
4-18
Interrupt Status/Mask Register Format
. 4-19
Diagnostic Structure
. .
5-3
Macroverify Run Report
.
5-8
CPU Diagnostic Run Report
5-10
CPU Diagnostic Error Message Format
5-11
Memory Diagnostic EHXMS View Command
. 5-15
Memory Diagnostic Operator Error Format
5-16
Memory Diagnostic Memory Error Format
5-16
Monitor Internal Controls
5-25
Rear Cover Removal
.
.
.
6-2
Rear Cable Removal . . . . . . .
. .
6-2
Patch and Filter Panel Assembly Access
. 6-3
Module Cable Removal . .
.
6-3
Module Removal . . . .
. .
.
6-4
Module Cable Replacement
. .
6-5
Module Replacement .
.
. .
6-5
Front Cover Removal
.
6-6
Front Bracket Removal
6-7
Storage Subsystem Cover Removal
.
6-7
RD52 Cable Access
. . .
.
6-9
RD52 Cable Removal
. .
6-10
RD52 Head Positioning Arm Cover Replacement 6-11
RD52 Shipping Container . . . .
. .
6-12
RD52 DIP Switches .
.
.
. 6-13
RD52 Head Positioning Arm Cover Removal
6-14
RD52 Insertion
. . .
. . 6-15
RD52 Cable Connection
6-16
RX50 Cable Access . . .
. 6-17
RX50 Removal . . . . .
6-17
RX50 Cable Connection
6-18
Power Supply cable Removal
6-20
Fan Power Connector
6-21
Drive Cable Backplane Conn~ctors
. . 6-23
Other Backplane Cable Connectors
.
6-24
Q22-bus Cable Backplane Connector
6-25
. .
Rear Fan Installation
6-28
Front Fan Removal .
. . .
6-30
Front Fan Installation . . .
6-31
6. 3 4
Front Control Panel Removal
Front Control Panel Disassembly
6-35

.
.
.

.
. . .
.
. . . . . .
. . . . . . .
.
.
. . . .
. . .. . . . . . .
.
.
. .
. .
. .
. . . .
.
.
. .
.
. . . .
. .
... ... ...
. .
.
. . .
. .
. . . .
.
.
. . .
.. .. ....
.
.

. . .

viii

VAXstation I TECHNICAL

~ANUAL

TABLES
1-1
1-2
1- 3
1-4
1. 5
1-6
1-7
2-1
2-2
2·3
2-4
2-5
2-6
2-7
2-8

2-9
2-10
2-11
2 - 12
3-1
3-2
3- 3
3. 4

3. 5
3-6
4. l
4. 2
4. 3
4. 4

4-5
~ -6

lj •

-i

4. 8
4-9
4 . 10

4. 11

4·12
'1 . l 3
~. 14
4-15
4~ l 6

.:J .. l'

.'J • L....,

5. 3
r

)

s. )
:, . 6

VCBOl Module Specifications
• • • • • .
BA23-A System Box Specifications • • • .
VRlOO Monitor Specifications . • •
• . •
VSlOX Mouse Specifications • • • • • . • • •
LK20l·CA Keyboard Specifications •
• • .
Mass Storage Capacity • • • • . . • • • . .
DC Power and Bus Loads • • • • . .
System Components and Options • • . • • . .
DAP Option Switches . . . .
• • • •
MSVll·QA Switches • . . . • • . . • •
•
MSVll·QA CSR Address Jumpers • • • . • • .
MSVll·QA Jumper Pairs
.•.•
RQDXl Device Address Select . . . .
VCBOl MSA Selection . • • • • . . . .
.
CSR Base Address Select
• . .
.
Display Density Selection
•
DZVll Address Switches .
. . . • .
.
DZVll Vector Switches . . • . . • . .
.
DZVll Jumpers
. • • . .
.
VCBOl Clocks. . . . . . .
• ••.
Q22-bus Signals
• • • . . . . . • . .
VCBOl I/0 Registers . . • •
• • .
.
Video Referesh Address Derivation
.
Failure Thresholds . . . . . • . . .
.
Voltage and Current Protection Thresholds
VCBOl Registers . . . .
• . • .
CSR Bits . . . . . . . . . •
Cursor X Position Bits . . . .
Mouse Position Register Bits . .
CRTC Address Register Pointer Bits
CRTC Internal Registers
CRTC )ata Register Bits
ICDR Bits
ICSR Bits
. . . . .
.
ICSR Commands
Interrupt Controller Mode Register Bits
Mode Registers lA and 2A Bits
Status/Clock Select Register A Bits . . . .
Command Register A Bits
Transm1t;Receive Buffer A Bits
.
Interrupt Status/Mask Register Bits
.
Microverify Error Codes
Monitor Display Errors • . . .
Memory Diagnostic Tests
. . . .
Memory Diagnostic Control Keys
Memory Diagnostic Commands. .
Memory Diagnostic Command Options
ix

1·4
1·5
1-6
1-7
1-7
1·7
1 -8
2-2
2-8
2-12
2-13
2-14
2-16
2-19
2-20
2-20
2-25
2-27
2-27
3.5·
3-7
3-10
3-19
3·33
3-37
4-4
4-5
4-6
4·6

4-7
4-1
4·8
4-9
4·10

4·11
4-13

4-13
4-17
4-18
4-19

4-20
S-4

5-6
S-11
S-13

3-13

5-14

VAXstation I TECHNICAL MANUAL
5.7
5-8
5-9
5-10
5-11
6-1

VOS Command Summary . . . . . . . . • . . .
VCBOl Diagnostic Tests . . .
. . . .
VCBOl Diagnostic sections . . • . • • . . .
Monitor LED Description . • . . . • .
.
Troubleshooting Flow .
• •...•.
Part Numbers . . . • • •
. • • •

5-17
5-18
5-21
5-24
5·31
6-39

PREFACE

INTRODUCTION TO THE MANUAL
This manual contains a general description of the VAXstation I; a
functional description of and programming information for the
VCBOl video controller board; and system maintenance procedures.
This manual does not describe VAXstation 1 installation or normal
operation (see the VAXstation I Owner's Manual, EK-VS200-0M); nor
does this manual provide detailed technical information on system
components other than the VCBOl. For such information on other
system components refer to the appropriate documentation, listed
at the end of this preface.
CHAPTER:
1

GENERAL
INFORMATION .. Introduces
and
overviews
thE
VAXstattion I.
System specification tables are included at
the end of this chapter.

describes
the
major
SYSTEM
CONFIGURATION .. Brifely
Controls,
components
and options of the VAXstation I.
switches,
jumpers, and backplane configuration are als2
included in this chapter.

is
a
technical
FUNCTIONAL DESCRIPTION -- This chapter
description of the VCBOl Video Controller and the graphics
I/0 devices.

PROGRAMMING INFORMATION ·· This information describes
VCBOl address space and programmable functions.

the

PREFACE
Describes diagnostic programs and procedures.

MAINTENANCE

REPLACEMENT
Gives step-by-step procedures for removing and
replacing system components.

APPENDIX:
A

GLOSSARY -- defines terms associated with the VAXstation I.
Reference to the Glossary is indicated when a term in the
main part of the document is set in italics.

INDEX ·· provides a reference to key words,
mnemonics,
acronyms, and certain part numbers; and also defines most
mnemonics and acronyms.

RELATED DOCUMENTS
VAXstation I Owner's Manual
EK·VS200·0M
VAXstation I Pocket Service Guide
EK·VS200-PS
MicroVAX I CPU Technical Description
EK·KD32A·TD
MicroVAX I Owner's Manual
EK·KD32A·OM
MicroVAX Handbook
EB-25156-47
RQDXl Controller User's Guide
EK·RQDXl·UG
RX50-D-4 Dual Flexible Disk Drive Manual
EK·LEPOl·OM
RD52 Fixed Disk Drive
[TBSJ
DEQNA User's Guide
EK·DEQNA·UG
DZVll Asynchronous Multiplexer Technical Manual EK·DZVll·TM
MSVll·QA Memory [TBSJ
[TBSJ
Microcomputer Interfaces Handbook
EB-20175·20
Print Set
MP-02005-01
You can order these documents from:
Digital Equipment Corporation
Accessories and Supplies Group
P. 0. Box CS2008
Nashua, NH 03061
Attention: Documentation Products

xii

PREFACE
CONVENTIONS

The following table defines the conventions used throughout
manual.

this

- - - - - - - - - - - - - - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CONVENTION
I MEANING
- - - - - - - - - - - - - - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

<mm:nn>

Read as "mm through nn"; indicates a bit
field or a set of lines or signals. For
example, A<l7:00> is the mnemonic for
Unibus Address Lines Al7 through AOO.

DS> RUN EHXVS<RETURN>

Terminal dialogue.
Prompts and system
typeouts are shown in normal type. User
responses are shown in boldface type.
<RETURN> is described below.

The boldface symbol of a label enclosed
by
angle
brackets represents a key
(usually a control or special character
key) on the keyboard (in this case, the
RETURN key). (Draft document only.
The
convention
is
different
for
final
documentation -- see DEC STD 165.)

abbreviations

Abbreviations used in this manual are in
accordance with DEC STD 015, 3 February
19 8 J .

italics

Terms are set in italics to indicate that
more information can be found in the
Glossary (Appendix A).

- - - - - - - - - - - - - - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

NOTE
CAUTION
WARNING

contains general information.
contains information to prevent damage to equipment.
contaiP.s information to prevent personal injury.

xiii

CHAPTER l
GENERAL INFORMATION

This
chapter
gives
an
overview
of
the
VAXstation I.
Specifications are listed at the end of the chapter.
1.1

SYSTEM OVERVIEW

The VAXstation I is a video graphics workstation operating in a
single-user environment. It is a self-contained system, and uses
the MicroVAX I as its CPU (central processing unit), interfaced
to a special·purpose video graphics module, the VCBOl.
As Figure l·l shows, the
units:
1.
2.
3.
4.

VAXstation I

comprises

four

physical

System Box
Display Monitor
Keyboard
Mouse

The system provides a 256 kB (kilobyte) bit-mapped, single-plane,
video memory.
The video memory is contained in the VCBOl. In
addition, the VCBOl provides cursor control, monitor video and
sync
signals, keyboard and mouse interfaces, and supports
VTlOO-style split-screen scrolling.

1 -1

GENERAL INFORMATION

.... 1)•,..4

Figure l·l:

VAXstat ion I

To the programmer, video memory is a block of standard MOS RAM
(metal-oxide silicon random-access memory) in the Q22-bus address
space. Data in this memory is accessible to the CPU's data
manipulation primitives.
Figure 1-2 is a block diagram of the VAXstation I and its
options. There are two major functional parts to the system:
o

The MicroVAX I -- The CPU and Q22-bus peripherals other
than the VCBOl. These provide all system computational
and integral mass storage functions.

The Graphics Subsystem ·· The VCBOl and its I/O devices.
These provide the user interface. The video monitor
displays high-resolution alphanumerics and graphics on a
48 cm {19 in, diagnol), monochrome (black and white),
CRT (cathode-ray tube1. The display is in landscape
format.
The monitor and keyboard also serve as the
system console. Operator control and data input is
through the keyboard and mouse.
1-2

GENERAL INFORMATION

+-·-·····--+
+·--···-··-+
'LA50/LA100i<--····>iMicroVAX II
.PRINTER* I
CPU
I
+-········-+
+··-··--···+
I\
I \
+- - - - - - - • - - - - . - - - - -+
l
+········+
MSVll-QA
/···\ l
+···>!LK201
.SYSTEM MEMORY
· \ · · ·I I
I KEYBOARD:
+--------------···-+
I
+······-···+
+···-·-··+
+- - - . - - . . - - . - - - - . - . +
/-··\fVCBOl
1<··+
+···--·-·+
i MASS STORAGE
\---/iVIDEO
I ·······)lVRlOO
+- - - - - - -. -• -. . . . .+
!CONTROLLER:<··+
!MONITOR
,RQDXl CONTROLLER :/··-\
+······· ·+
+ - ••••••• +
'+-. - - . - -+- .. - - - - ·+ '\·. ·/
. RD52
RX50
+· · ·> VSlOX
'DISK
DISKETTE
MOUSE
+ .•••. - •. +
+-------+-----·-·+
+·······-··········+
Q22
+··--··············+
MSVll-QA
* I ... \
BUS
ADDITIONAL MEMORY \ - .. I
+-···--········---·+
+- .. - .. - . - . - - - . - - - -+

DEQNA
* /---\
ETHERNET CONTROLER \···/
+······---·········+
+·················-+
DZVl l
* /-

-. \

\ - . -I

MULT:'.:PLEXER
+----------········+

\
* ·· OPTIONAL
Figure 1·2:
1.1.1

I
\I

VAXstation I Block Diagram

Physical Description

All the components shown in Figure 1-2, except the monitor,
keyboard,
and mouse, are mounted in the system box. The system
box is a BA23·A mounting box, which includes:
H7864 Power Supply
H9278-A 8-slot Backplane
Rear Patch and Filter Panel Assembly
Front Control Panel Assembly

o
o

o
a
rn~

~~Jse

it.s

:;·"·n

connects to the Patch and Filter panel Assembly througn

~able.

1-3

GENERAL INFORMATION

Monitor sync and video, and the keyboard signals are all carried
by the BC18T-10 video cable, between the Patch and Filter Panel
Assembly and the monitor. The keyboard lead plugs into this
cable at the monitor end.
The system box connects to the ac power line; however, ac power
is· provided to the monitor through its own ac power cord. (For
complete information on cable installation, see Chapter 2 in the
VAXstation I Owner's Manual, EK-VS200-0M).
Switch, jumper, and control settings
components are described in Chapter 2.
1.2

for

the

various

system

SPECIFICATIONS

Table l·l:

VCBOl Module Specifications

+ • - - - • • - - • • - . - - . - . - . - . - . - . - - • • - - • - - - • - - • - - • • • • - • - • • • - - - - - • - • - -+

i Physical
+- - - - - - - •.. - . ·+·. - .. - - - - - . - .... - .. - ... - . - .. - - . - .... - . - - .• - ... -+

! Length
! Width

26.50 cm (10.4 in)
21.26 cm (8.4 in)

+- •• - - - . - - - - - ·+- - - - - ... - - .. - .. - . - - .. - - - . - - - ... - . - •. - - - • - •... - ·+

; Power Requirements
+ - - - - - . - . - - . - •+. . . - . . - - . - - . . - - . - . . . - - - - - - - - - - - • . . • - - • - . - - - - - - -+

Voltage
: Current

. 5.0 Vdc +/· 0.5%
! 5.0 A (typical, operating)
4.4 A (typical, standby)

+. • - • • - - . - . . . -+. - . • - - • - - - - . - . . - - - - - - . - - - - . - . . • . - • - . . . . . - - - . - . . +

Access and Cycle Time (nanoseconds)
+- - - . . . - . . . - . . +. . . . - - - - . - - - . - - - - - - - - - - - - . - - - - - - - . . - - . . - . - - - . - -+

DAT!
DATO (BJ
DATIO (BJ

Ta cc
Typical Maximum
950
1380
950
1380
2010
2440

Tcyc
Typical Maximum
1490
1920
1490
1920
2550
2980

+- - - - - . . . - . - . •+ . . • - - . - - . - - • • • - - • • • • - • • • - - • - • - - - • - • - - - • - • - • - - . -+

1-4

GENERAL INFORMATION

Table 1·2:

BA23~

System Box Specifications

+· .......•... - - .. - . - - ................. - ...• - . - •. - ...... - ..... ·+

i Physical

+· ........... ·+· .... - ... - ... - .... - ..• - . - . - - . - .. - ....•........ ·+
Height
64.25 cm (24.5 in)
i
Width
Depth
Weight

25.40 cm (10.0 in)
72.64 cm (28.6 in)
! 31.75 kg (70 lb)

+-············+···············-························-··-···+
i Operating Range

+ .... - - - - - - - .. + ... - - . - - - - - - .. - - - . - . - ......... - ...... - - - . - .... ·+
Temperature
: Relative
I Humidity

15 C to 32 C (59 F to 90 F)
20% to 80% with maximum wet bulb 25 C (77 F) i
and minimum dew point 2 C (36 F) !

+ .••• - - • - - - - . -+ - - •.. - - - - ••••• - - •.• - - ••• - •••••.••••.••••. - • - •• -+
I Recommended Operating Range
+ ••••••• - •••• ·+- .. - .. - ..............•... - .•....•. - - . - •..•..... +

Temperature
Relative
Humidity
; Altitude

18 C to 24 C (65 F to 75 Fl
60% to 60%

0 to 3048 m (0 to 10000 ft)

+ ..... - .... - - ·+-. - - . - ... - ... - - - ............................. - ·+
! AC Power Requirements
+• • • • • • • - . • - • . - - - - - • • - - . • • . . - • • • • • - • • • • - . - - - • • - . • - - • - • • . • • . • • .+

"'---

: 120 Vac Input

+. . • • - . • - • - - . .+. . • . - • • • - • • . . . . • . - • • • . • . • • • • - • - - • • • • . • • • • • • . • . .+

' Voltage
' Frequency
' Current

88
128 v RMS (nominal 120 V)
47 · 63 Hz
(nominal 60 Hz)
4.4 A RMS nominal

+·············+·····-········-····························-··-+
240 Vac Input
+ - .•• - . - - - - • - ·+. - - . - - . - - .•. - .. - ............... - - . - . - - . - ...... -+

Voltage
Frequency
Current

176
256 V RMS (nominal 240 V)
47 · 63 Hz
(nominal 50 Hz)
2.2 A RMS nominal

+ .• - • - .••..•. ·+ - .. - - - - . - . - - - - . - - - - . - - .. - . - •.• - - .... - - .. - . - . - - ·+

l -5

GENERAL INFORMATION

Table 1·3:

VRlOO Monitor Specifications

+. - - ......... - - - ... - .. - . - - - - .. - - - . - - - - - . - - .• - .. - - . - - - - - - - - - - - ·+
I Physical
I
+. - - ........ - . +. - - . - ..... - .... - - . - . - . - . - - - - - - - - - .. - - - - . - - - . - . ·+

' Height
Width
Depth
weight

37.50
45.70
40.60
20.50

cm
cm
cm
kg

(14.75
(18.00
(16.00
(45.00

in) (less base)
in)
in)
lb) (less base)

+· - - ......... ·+· .......... - . - ..... - . - ......... - - ... - ......... ·+

: Screen

+· ........... ·+· ............................ - - ..... - - ........ ·+

Horizontal
Vertical
Viewable
Area

354.3 mm (13.95 in)
281.4 mm (11.08 in}
960 X 864 pixels

+. • • • • • • • • • . • -+ - - - . - - - - . - • . • • • • - • • • • . • • • • • • • • • • - • - • • . • • • • • - • • •+

! Pixel
+ . . . . . . . • • . . . -+ - - . - - - . . • • • . • . . . - . . • - - . • • . • • • • • • . . • • - • • • • • • • • - •+

! Horizontal
l Vertical

; 0.325 mm (0.0128 in)
!
0.325 mm (0.0128 in)

+· .......... - ·+· ..... - . - - - ... - . - ......... - ........ - .... - . - - .. ·+

! AC Power
; 120 vac at 1.0 A
I Requirement · 240 Vac at 0.5 A
+- - .. - - - - - - - - -+· ..•. - ..........•• - .. - .•••.••.••.•..• - .••..• - . ·+
I

Inputs

+- . . • • • • • . - . --+. . . - - . . - - . - • . • . • - . • . • - - • • • • • - • . • - - - . • • . • • • . • • • •+

Video

Horizontal

Vertical

Voh: (white level)
Vol: (black level)
Tr: <3 ns
Tf:
<3 ns
Sync Width:
Sync Period:
Sync Tr:
Sync Tf:
Blanking Interval:
Unblanking Interval:
frequency:
Sync Width:
Sync Period:
Sync Tr:
Sync Tf:
Blanking Interval:
Unblanking Interval:
frequency:

2.0 to 8.0 us
18.416 us
<3 ns
<3 ns
4.804 us
13.612 us
54.3 kHz
0.1 to 0.5 ms
16.667 ms
<3 ns
<3 ns
0.775 ms
15.912 ms
60 Hz

+. . • . . • • • . • • • •+- . - - . . . - . . . . - . -. - . . - - • • • - . • • . • . • • • • • . . . • • • - - • - . +

1-6

GENERAL INFORMATION
Table 1·4:

VSlOX Mouse Specifications

+- - • - • - •••• - - - .•••••••.•••••••• - - •••••• - • - ••••• - •• - •• - ••• - ••• ·+

Physical

+· ... - . - . - . - . -+. - .. - . - - - .. - .................. - . - ... - .... - - ... ·+

3.30 cm (1.30 in)
Height
7.00 cm (2.75 in)
Width
Length
9.50 cm (3.75 in)
Weight
0.50 kg (1.10 lb)
+·-·-·····--··+···············································+
DC Power
: +5.0 Vdc +/- 10% at <150 mA
i Requirement ;
1

+ ..•.• - - •••... +. - .. - ......... - ....... - .... - .. - .. - ... - ... - ... - ·+

: Accuracy

7.87 pulses/mm (200 pulses/in)

+ •.•.• - .•.•.. - + ••. - ••• - • - • - • - •• - - • - ••• - ••• - ••••••••••• - - •••• - ·+

Rate of
: Movement

25.4 cm/s (10 in/s) or less

+ .• - •.• - •••..• + .... - ..•. - • - • - • - - - - ••••• - - - - •• - •• - • - • - •••••••• ·+

Table 1·5:
+• . • - • •• . • . - - .

LIC20l·CA Keyboard Specifications

. . . - . . . - . . - • - • • • • • • • • - • • • - • • - • - • • - • • • • • • • • • • - • •+

Physical
+. . . . . - . . . . . -.+- . • - . • . • • • • •• • • - - - - •- • - - • • • • • • • • - - • - • • • • • • - • • • •+

Height
Width
Depth
Weight

5.10
53.30
17.20
2.30

cm (2.00 in)
cm (21.00 in)
cm (6.75 in)
kg
(5.00 lb)

+. . . • • • . - . • - • . + - . . . • . . • • • . • . . • • - . • • - - - . . - • • - - - • • • • • • • • • • • • • • • •+

DC Power
Requirement

+12.0 Vdc at 350 mA

+··········-··+-··············································+
Table 1·6:

Mass Storage Capacity

+····-··-········+············································+

Drive
Byces/sector
Sectors/track
Tracks/surface
Surfaces
Capacity/drive

RX50
512
10
80
2
816 kB

RD52
512
18
375
8
28 MB

+ . • • • • • • • • • • • • . • ·+ .... - ... - . - . . . . . . . . . . - •...•..• - • - •.... - •. - . ·+

1·7

GENERAL INFORMATION

Table 1·7:

DC Power and Bus Loads

+- . . - . . • • • - - • - . - • . . . • • . . - - - • . . - . - • - • - • . . - - • • • • • • • • • • - - • • - - . . . . . -+

: H9278 Backplane (handling capacity)

+ •••••• ·+ •.. - - - .. - ...•. - - •• - - •. - . - • - . - • - - - - - •• - - - - • - - - - •. - - .• - • -+

Bus
I 30 AC Loads
Loads I 20 DC Loads

BA23-A Single Box System

I
I 15 AC Loads (per box) BA23·A

Multi-Box System

I 20 DC Loads {total)
+- •• - •• ·+ .. - - . - - - .. - .. - - - - - - - - - - - .. - . - . - . - .. - ...... - - ... - - - . - .. ·+

i KD32-AB CPU (Both Modules)
+· ..... ·+- ....... - . - - - - .... - ...... - - .... - . - • - .. - ... - - - - . - .. - - . - -+

I 2 AC Loads
i Loads \ l DC Load

I Bus

+. . - . . . . +- - . . - - - -. . . . - - - - - - - -- • . •- - - . • - - - . . - • . • - . . . . - . - . . . . - . - - . +

! M7135 Data Path Module
+. - - • • • •+ . • . . - - - . . . - • - . • • - - - . • - • • - • . - . • - . . . . - - . - • • • . . . • • • - . - . . - - +
I Power I +5 Vdc +/- 5% at 7.0 A maximum
I
I +12 Vdc +/· 5% at 0.5 A maximum
+ - - - - - - -+ - . . • . . • - - • . - - - - • - - - - - - • • . - • . . . • • • - • . . . . - • . . . . . - • • - . . - . -+

I M7136 Memory Controller Module
+. • - • - . -+- . . . . . - . - - . - - - - . . • • . • . • • • • . • • • • . - • • • - - . • . - - . - • . . - - - - - • . +

I Power I

+5 Vdc +/· 5% at 7.0 A maximum

+- ..••. ·+· - ... - . - . - - . - ... - . - ... - . - ... - . - ... - .... - - . - - - - . - - . - - . - -+

I MSVll·QA Memory

+·. - . - . ·+· - .... - - - .............. - ....... - - ....... - ... - - . - - . - - .. ·+

Power

+5 Vdc +/· 5% at 1.0 A typical

Bus
Loads

l Unit Q-bus Load

+ . . . - • - . +. • - - - - - - - . . . - - . . . . . . - - - . . - . . . • • . . . . - - - . . • . - - . . . - . - . . . . -+

' RQDXl controller
+. - - - - - -+. . . - - - - - . . . . . . . . . - . . . . . . . . . . . . . . . . - - - - - - - - - . - - - - - - - . . - -+
Power
+5 Vdc +/- 5% at 6.4 A
+12 Vdc +/· 5% at 0.1 A
Bus
Loads

2.5 AC Loads
[TBS] DC Loads

+• • • - • - -+- - - . - - - -- - - - • - . - - - • - - - • - - - - • • • - - • - • - • • . . - • • - • • . . • . . • - . .+

RD52 Fixed-Disk Drive
+ • . • • • • -+- - . . . . . . . - . . . - . - . - - . . - - . - . - - - - - - . - . • . . . . . - - . - . . - . . . . - . .+

Power

+5 Vdc +/- 5% at 1.4 A maximum
+12 Vdc +/· 5% at [TBS] A maximum

+ • - • • • • •+ - . • - . - • . • • • • • - - - - - • • • - - • - • • - • • - • - - • - - • • • • • • - - • • • - • - • • • •+

RX50 Diskette Drive
+ ••• - • - ·+ .... - .. - ...... - - - . - . - ..... - . - •..... - - . - - - - . - .. - - .. - - . - ·+

Power

+5 Vdc +/· 5% at 0.85

A typical

+. . - • - . -+ • - . - . - - . - . - . . . . . - . - . • • • - - . . • • • - . . . • • . . - . . - - . • - . . . . . . . . .+

1-8

GENERAL INFORMATION

Table 1·7:

DC Power and Bus Loads (continued)

+· - - . - . ·+- - • - • - - •••• - - - - •••••.. - - - - - • - • - - - • - - - - - - - - - - • - - - - - - - . - -+

I VCBOl Video Controller
+· - - - - • -+-. - - - - - . - - - •• - - • - • - - - - - - - - - - - - . - • - • - - - - - - - .. - - - - . - .. - - ·+
Power
+5 Vdc +/· 5% at 5.0 A typical

Bus
Loads

[TBS] AC Loads
[TBS} DC Loads

+· - - . - . ·+ ... - - .• - - - - - - - - - - - - - - - - - - - - - - - - - - - . - . - . - - - - . - - . - . - .. - . ·+

1-9

CHAPTER 2
SYSTEM CONFIGURATION

This chapter gives a brief overview of the system components
configuration, including controls, indicators, switches,
jumpers.
2.1

and
and

INTRODUCTION

In many respects the VAXstation I resembles any other MicroVAX I.
However, unlike a typical MicroVAX I, the VAXstation I is a
special-purpose system, designed to function as a single-user
workstation.
Therefore, the expansion capabilities of the
VAXstation I are also designed to support and limited
to
workstation
applications.
Specifically,
the
VAXstation l
includes the components listed in Table 2-1.
figure 2-1 shows an example backplane installation for a system
configured with all the option modules listed in Table 2-1. With
regard to the backplane, the following should be observed:
o

The M7136 MCT (memory controller} module is installed in
slot 1.

The M7135-YA OAP (data path) module is installed in slot
2.

Memory modules are installed adjacent to
that is, starting with slot 3.

It is recommended that the DEQNA be installed ahead
(that is, in the lower-numbered slot) the VCBOl.

The DEQNA ~s a dual-height module and requires a G 7 ?~;
Grant Continuity card in the A or C position of the same
2.1

the

M7135-YA;

SYSTEM CONFIGURATION
slot. As Figure 2·1 shows, the DEQNA occupies the A/B
position and the G7272 occupies the C position. (Figure
2-2, below, shows the Grant path).
0

The RQDXl Disk Controller is installed in the last
active slot in the backplane. For example, in a base
system with no options, the VCBOl would occupy slot 4
and the RQDXl would occupy slot 5.
Table 2·1:

System Components and Options

+• • • • • • • • • • - • . • • - • . - • . • • • • - • - - - • • - - • • • - - - - - - - • • - - - - - - • -+
I BASE SYSTEM
I
+- - •••••.. -+- ••• - ....• - • - - - - - - - • - •••. - . - • - - - • - - - ••• - • - -+

KD32-AB
MSVll·QA
RQDXl
RD52
RX50
VCBOl
VRlOO
LK201-CA
VSlOX

MicroVAX I CPU (includes):
M7135-YA OAP (Data Path) Module
M7136
MCT (Memory Controller) Module
1 MB Memory Module
Disk Controller
28 MB Fixed-disk Drive
400 kB Diskette Drive
Video Graphics Controller Module
48 cm (19 in) Video Monitor
Keyboard
Mouse

+• • • • - • • • • . + . - . . . . . - . . - . . . . - . - - . • . . . . . • - • • • • - • - - - . - . • • - +
! OPTIONS
+- • • . • . -- . -+• - - . - . . . . . - - - - - . - . - - - . - . - - - - - - - • • - - • • . • . - . •+

MSVll-QA
DEQNA
DZVll
LASO or
LAlOO
[TBD]
[TBS]

1 MB Memory Module
Ethernet Controller
4-line Asynchronous Multiplexer
Printer
Printer
Graphics Tablet
Tilt/swivel Base for Monitor

+- . - - . . . . . . + - - - - - - . - • . • ~ - - - - • . . - . . • • • • . . . . . • • • • • - • • • . - . +

2-2

(

--------

.-1

M7 1.l',·· iA

MCT

MEM\JRY CONTROLLER (K032-AB CPU)

OAP -

DATA PATH

MSV I I -(JA MEMORY

M7551
M7551

M$Vll ()A MEMORY

M75fJ4

OEQNA ETHERNET CONTROLLER

M760:.!

VC601 VIDEO CONTROLLER

M86.B

+-------------------

---------------------+I
----------------------+I
--------------------------------------+
-----------------------------------+

RQOXl DfSK CONTROLLER

---------"'"

__ _

-------------+

--------------+------------------~-------+--------------------------+
I G7272
GRANT CONTINUITY I

DZVll ASYNCHRONOUS LINE MULTIPLEXER

.,...

--~------------------------+

+-----7 I M7957
+-- ____ ,.. __

------- ---------+
-------------------------------------+I

(KD32-AB CPU)

+--------

------~-------------+

-------------~---------+

--+

I
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I

I
II

I
I

II
I
I
I

+------------------------------------------------------------+ fltt'4

...
flt

Figure 2-1:

Backplane Configuration Example

I.Ill

•n

..
0

a
c

...
=
H

)

+-----------------------------------------------------------

GRANT

+---------------------1----+--------------------------+---------11 Q22
PRIORITY l
V
I
+---------------------t----+--------------~-----------~------

21 Q22

PRIORITY

-~-

- ------+

------ -------

CID

--+--C/D

------------- _.,.
+---------------------!----+--------------------------+-----------------------+ -------31 Q22
PRIORITY 3
V
I
CID
-- ...
+------- PRIORITY
-------------1----+--------------------- --+----------- ------- ------+
PRIORITY 5
022 I
41 Q22
4
+------------------->-------------+--------------------------+-----------------------+ - 1---- ----------------+---PRIORI TY 6
Ci22 I
51 022
PRIORITY 7
+------------ ------<------ --- - -+
----·-+
+---------------------]- +---- --------------+- ------ ------- --PRIORITY lit
Q22
61 022
PRIORITY 8
+------------------->----------------+
-----+--------------------------+------------------ -------+ ---)---~-fJRIOR!TY
022 I
71 Q22
PRIORITY 11
+-------- ----- -<--- ------------+
+---------------------1----+--Bl Q22
PRIORITY 12
+------PRIORITY
Q22
______ .,.
- -- - - - --·----+-----------+---- - -------------------+
-+

~-------------------+

-+--

-----

-------

-----

;-----------a

.
~
.
.
0

CJ
H

a
0
u

x"1

:ii..

1-----------

SIDE

________ . .,. ___

--+

I
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I

I .
IN
I
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I
l

Figure 2-2:

+--- ------ ---- - ---- -------H9278-A Backplane

I
--+

SYSTEM CONFIGURATION
2.2

H9278~

BACKPLANE

The H9278-A is an 8-slot backplane for quad· and dual-height
Q22·bus modules (see Figure 2·2). The A and 8 connectors in all
the slots supply Q22·bus signals to the modules (see Table 3·2).
Tne c and o connectors in slots 4 through 8 also supply Q22-bus
signals to the mcdules. However, the C and O connectors in slots
l
through 3 interconnect the three slots; that is, selected
side·2 pins of a given slot are connected to selected side·l pins
of
the
slot
immediately following.
This so-called "C/D
interconnect" provides 32 C/D connections per slot.
The figure also shows the the interrupt acknowledge priority,
PRIORITY 1 through PRIORITY 13, and grant continuity chaining.
If a dual-height module is mounted in slots 1, 2, or 3, it must
be mated to the A/B conn~ctors.
If a dual-height module is
installed in slots 4 through 8, the configuration may require a
G7272 Grant Continuity card in the A or C connector position of
the same slot, to maintain grant chaining.
The backplane also has connectors for the Power Supply backplane
power cable and the Front Control Panel assembly cable.
2. 3

KD32·AB CPU

The KD32·AB CPU comprises two quad-height modules: the M7135·YA
OAP (data path) module, and the M7136 MCT (memory controller)
module. The KD32-AB supports the following:
o
o

MicroVAX I CPU functions
Q22-bus interface
Block mode transfers
Up to 4 MB {megabytes) of physical memory

o
o
o
o
o

8 kB

direct-mapped cache

512 longword-entry tanslation buffer

10 ms interval timer
SLU (serial line unit)
16 kB bootstrap PROM (programmable read-only memory)

Ter~inal

For more information on the KD32-AB (in addition to the following
subsections), see the MicroVAX I CPU Technical Description,
EK KD32A·TD.

2-5

SYSTEM CONFIGURATION
2.3.l

M7135·YA OAP

The OAP (data path) module (Part Number M7135·YA) contains the
data path and the instruction decode and microsequencer logic.
It decodes macroinstructions, controls microinstruction flow, and
processes program interrupts.
The OAP is connected to the MCT
with a ribbon cable (see Figure 2-3).
2.3.1.1 Switches - As the figure shows, the OAP contains two
sets of eight DIP (dual in-line package) switches and a single
jumper. The SID (system identification) register switches are
used by manufacturing and should not be changed. Table 2·2 lists
the Option switch functions and :he normal setting for the
VAXstation 1.
The three LEDs display a binary error code that matches the error
code displayed in the segmented-LED display on the CPU insert
mounted in the Patch and Filter Panel assembly.
2.3.1.2 Microverify Jumper - This jumper determines the test
mode for Microverify (automatic power-up self-tests). The jumper
is factory-set to single-pass mode (as shown in Figure 2·3).
In
this mode, Microverify runs one pass each time it is called; and
reports either a pass, or a fail, if any part of the tests fail.
In the alternate jumper positon, multiple-loop mode, Microverify
repeats all tests until halted, if no errors are detected.
In
order for multiple-loop mode to execute correctly, OAP Option
Switch 2 (Table 2-2) must be in the OFF (VTlOO compatible)
position (also see the NOTE ·· VTlOO Mode, below). If any test
fails, Microverify continues to loop on the· failing test.
Subsequent successful passes of the failing test will not stop
Microverify from looping on the error; it must be halted by
operator intervention.
NOTE - VT100 Mode
If OAP Option switch 2 is set to the OFF
position,
a VTlOO can be connected to the
terminal SLU and used as the console terminal.

2-6

(

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I '
I
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I
I

1+-+-+I
+I
• - • +I
+ +-+I
• .. ··+I
•-•-+I
• •-+I

i+-+-+I
+-+I
+·•·+I
•-•-+I
• •-+I
+-+ +I
+ •-+I
B•-+-•I

--+

•

LEDs.

--------------- --------- ------- --------------------+I

+----+

I I I I I I

I
I

J 1

------

----------

---------+

I J3 I
I
I

+------------------------------+
DAP TO MCT CABLE CONNECTOR

+----+

TERMINAL

I
I

+"""'---+

+----+

PATCH AND
FILTER PANEL
ASSEMBLY
CABLE
CONNECTOR

e+ • •I

I
I
I

.. - - - -+
OPTION
SWITCHES

+ --

SID

I
I

I
I
I

I
N

MULTIPLE

SINGLE

LOOP

...... I
I

PAS'.:i
...

- +

MlCROVERIFV
JUMPER

I
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I
I

I
I
I
I
I
I
I

+-+

+ -- •

+---·
t

---

~--

+-+
+-+

+ - ._

Figure 2·3:

--+

+-+

+---+

+------------------------+

M7135·YA DAP Switches and Jumper

+-+

II
I
+------------------------+

;

SYSTEM CONFIGURATION

Table 2·2:

OAP Option Switches

+- - - - - ·+· - - - . - -+· - - - - - - - - - - - •• - •• - • - ••. - • - - - - • - - - - • - - - •• - •• - - • - -+

jSWITCHINORMAL !FUNCTION
\SETTING!

+- - - - - -+- - - - - . -+- - - - - - - - - - - - - • - - - • - - - - - - - •••• - - •••• - - •••••• - - • - -+

8
7

OFF
OFF

BAUD RATE SELECT -- specify the data transfer
baud rate between the CPU and console terminal.
8

OFF
OFF
ON
ON

OFF
ON
OFF
ON

9600
19200
300
1200

OFF

(reserved)

OFF

BREAK DETECT ENABLE -- determines whether a break
condition on the SLU causes a halt:
OFF = <BREAK> key disabled
ON = <BREAK> key enabled

4
3

OFF
OFF

RECOVERY ACTION ·· determine attempted CPU
functions during Power-on:
4

OFF
OFF
ON
ON

OFF
ON
OFF
ON

warm start or boot or halt
boot or halt
warm start or halt
halt

CONSOLE TERMINAL TYPE ·- identifies the type
console terminal connected to the system:
OFF= VTlOO compatible (see NOTE ·above)
ON = Graphics terminal

OFF

VTlOO

Mode,

BOOTSTRAP
SEARCH
ORDER -·determines
which
devices
are
searched
when
the system is
bootstrapped:
OFF = All devices searched
ON · = Disk/diskette drives not searched

+· . . . . ·+· .. - .. ·+· - - - - . - - - ...... - .... - - - - - .. - ... - . - .... - - ... - . - . ·+

2-8

SYSTEM CONFIGURATION
2.3.2

M7136 MCT Module

The MCT (memory controller) module (Part Number M7136) accepts
memory reference commands from the DAP module, and sequences the
controller logic to perform the commands. The MCT contains no
user-configurable components, and is connected to the DAP with a
ribbon cable. The module:
o
o
o
o
o

2. 4

rlenerates clocks
Controls MCT microinstruction flow
Translates virtual addresses to physical addresses
Accesses the data cache
Is interfaced to the 022-bus

MSVll·OA MEMORY

The MSVll·QA Memory (Figure 2·4 and Tables 2·3, 2·4 and 2·5) is a
1 MB, dynamic RAM, quad· height modul,e (Part Number M75Sl·AA).
The memory supports block mode OMA transfers using 22-bit
addressing.
It is addressable as a contiguous block in 128 kB
increments, between 0 and 4 MB.
An on-board
CSR
parity
controller provides parity generation, checking, and reporting.
The CSR stores the error flag and bad-block address, and an
on-board LED indicates the parity error. The CSR address is
selectable.
2.4.1

Switches

As figure 2-4 shows, the MSVll has two sets of six DIP switches.
These are the memory's starting and ending address switches, and
select the address on 128 kB boundaries (Table 2-3)
VAXstation I configuration guidelines are:
l

= OFF and 0 =ON.

For all switches:

SWl positon 6 is not used.

If the MSVll·QA is the only memory or the first memory
installed (in other words, the memory installed in
backplane slot 3):
the STARTING ADDRESS must be 00000.
the ENDING ADDRESS must be 1024 kB.

\"-----'

2·9

SYSTEM CONFIGURATION

If the MSVll-QA is the second memory:
the STARTING ADDRESS must be 1024 kB
the first memory's ending address).

(the

same

the ENDING ADDRESS must be 2048 kB.
The VAXstation I supports only one or two MSVll-QA
memories, and they must be configured as stated above.
Any other configuration is invalid and not supported.
For example, to configure one MSVll-QA, the address switches must
be set to:
+- - . . . . . - . . . . . - - . . . . . . . . . . - . . -+. - - - - - . - . . . - - - - . - - . - . . - .+

STARTING ADDRESS

ENDING ADDRESS

+- . . . - . . . . . . - . . . . . - . . - - - -+ - - - -+- - . - . - . - . . - . - - . . - - . - . . . -+

SWl

SW2

+· - - -+-. - ·+· .. -+· - - ·+- - . ·+-. - -+- .. -+- - - ·+· - - -+- - . ·+· - . ·+

ONE
I 5
MSVll-QA I ON
I

4
ON

3
ON

2
ON

1
ON

6 ! 5
ON I OFF
!

4
OFF

3
ON

2
ON

1
ON

00000
1024 kB
+· .. -+- .. -+- - - -+- - - -+- - - ·+·. - -+-. - ·+- - - ·+- - - ·+· - - ·+·. - ·+

Example 2·1:

One MSVll~A Starting Address Selection

When two MSVll·QAs are installed, the address
set to:

switches

nust

+. . . . . . - . - - . . . . - - - . . - - - - - - - - - -+ - - - - - - . - - - - - - - - - . - - . . - - -+

STARTING ADDRESS

ENDING ADDRESS

+- . - - - - - - . . - - . - - - - - . - - . - -+- . . -+. . . - . . . . . . . . - . . - - . . . . - - -+
sµl
I
SW2
+· .. ·+·. - ·+· - - ·+- - . ·+- - - -+- - - ·+- - . ·+·. - -+· - - -+- - . ·+- - . -+

FIRST
MSVll-QA

5
ON

4
ON

3
ON

2
ON

1
ON

6
ON

5
OFF

4
OFF

3
ON

2
ON

1
ON :

1024 kB
00000
+·. - ·+· - - ·+· - . ·+·. - -+- - . -+-. - -+- - . -+-. - ·+· - - ·+· - . ·+-. - -+

SECOND
MSVll-QA

5
OFF

4
OFF

3
ON

2
ON

1
ON

6
OFF

5
OFF

4
ON

3
ON

2
ON

l
ON

2048 kB
1024 kB
+· .. -+- - - ·+· - - -+-. - ·+-. - -+·. - ·+· - . ·+·. - -+- - - ·+· - - -+· .. ·+

Example 2·2:

Two MSVll·QA Starting Address Selection

2-10

(

. ---------------------+
+
I

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R +
p

+--+

N +--+
M +--+

I
I
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+
A

I
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I
I

SW1
1+-+-+
+-+-+
+-+-+
+-+-+
+-+-+

6+-+-+
OFF
ON

I
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t
I

+
+

I
tvl

I
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• I
..._. I
..._. I

l
I
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I
I

SW2
1•--+--+
+--+--+
... --+--+

+--+--+
6+--+--+
OFF
ON

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II st=

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•

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+
+

.. - +

•

+-+

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+-+

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------·------+

Figure 2·4:

+-+

+---·

-------------+

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+-+

+------------------------+

.
0

c:
~
tot
H

MSVll-OA Jumpers and Switches

SYSTEM CONFIGURATION

Table 2-3:

MSVll·QA Switches

+----+----+----+----+----+
19
18
20
18
21
20
19
17 I
17 I
BOAL: I
I 21
+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+
STARTING ADDRESS
ENDING ADDRESS
!
+- - - - - - - - - - - - - - - - - - - - - - - -+- - - -+- - - - - - - - - - - - - - - - - - - - - - - -+
I
SWl POSITION
SW2 POSITION
+ - - - - - - + - - - - + - - - - + - - - - + - - - - +. - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - +
4
3
2
4
2
1 !I
3
1 I 6 I 5
I (kB) I 5
+- - - - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+
0
0
4096
0
0
0
0
0
0
1
0
0
3968
1
0
0
1
0
0
0
1
1
0
0
3840
0
1
0
0
0
0
0
1
1
0
3712
0
1
0
0
1
1
0
1
0
3584
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
3456
1
0
0
1
1
1
3328
0
1
1
0
0
1
1
0
0
1
3200
0
1
1
0
0
l
1
0
1
1
3072
0
1
0
0
1
0
1
0
0
0
0
2944
1
0
0
0
1
0
1
0
0
1
1
1
0
1
0
1
2816
0
1
1
0
0
0
1
0
1
1
2688
0
1
0
1
0
1
1
1
1
2560
0
0
1
0
1
1
0
0
0
1
1
2432
0
0
1
0
1
1
0
1
1
I
1
1
0
1
1
0
1
1
1
0
0
I 2304
1
1
1
1
1
1
0
1
1
1
1
I 2176
1
0
0
0
1
1
0
0
0
0
0
* ! 2048
1
0
0
1
1
0
1920
0
1
0
0
1
1792
1
0
0
1
0
1
1
0
0
1
0
1
1
1
1
0
0
1
1
1664
0
0
1
1
1
1
1
1
0
1536
0
0
0
0
0
1
1
1
1
1
0
1
1308
0
0
1
0
1
1
0
1
1
1280
1
0
1
1
0
0
1
1
0
1
1
1152
1
0
1
1
1
1
1
1
0
l
1
0
0
1024
1
0
0
0
*
0
1
1
1
1
1
0
896
1
1
0
0
1
1
1
1
0
0
1
1
1
0
768
0
1
1
1
1
1
0
0
1
1
640
1
1
1
l
1
1
0
0
1
1
0
0
512
1
1
1
1
1
1
0
1
1
0
1
384
1
1
1
1
0
1
0
1
1
1
1
1
256
1
1
1
1
1
1
1
1
1
1
128
1
0
0
0
0
0
0
0
* I
+- - - - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+- - - -+
1 = OFF
0 = ON
* VAXstation I addresses
+----+----+----+-~--+----+

2-12

SYSTEM CONFIGURATION

2.4.2

Jumpers

As Figure 2-4 shows, the MSVll·QA has 6 sets of jumpers. The CSR
Address jumpers (Table 2·4) are a set of 4 jumpers. In the
VAXstation I, the first (or only) MSVll·QA CSR address is set to
17772100, and the second MSVll·QA CSR address is set to 17772102.
Because the VAXstation I supports only one or two MSVll·QAs, the
j~mpers should not be set to any other positions.
Table 2·4:

MSVll·OA CSR Address Jumpers

+ ............... ·+ ... ·+· ................ - ·+· ·+
BOAL: 121
I 05 ~ 04
03
02
01 jOOj
+············ ····+····+···················+··+
!11111111110100011 0 I x
x
x
x I 01
+· .............. ·+· .. ·+· ....... ·+· ....... ·+· ·+
OC'i'AL: ' 1 7 7 7 2 1 !
X
X
+· .............. ·+· .. ·+· .. ·+· .. ·+· .. ·+· .. ·+· ·+
I
JUMPER
+· .. ·+· .. ·+· .. ·+· .. ·+
ADDRESS
p
R I
N
! M
+· ...............•.•. ·+· .. ·+· .. ·+· .. ·+· .. ·+
17772100
IN
IN
IN
IN '
* FIRST
SECOND
17772102
IN
IN
IN
OUT'
*
17772104
IN
IN
OUT IN
17772106
IN
IN
OUT OUT1
17772110
IN
OUT IN
IN
17772112
IN
OUT IN
OUT
17772114
IN
OUT OUT IN
17772116
IN
OUT OUT OUT
17772120
IN
OUT IN
IN
17772122
OUT IN
IN
OUT:
17772124
OUT IN
OUT IN I
17772126
OUT IN
OUT OUT,
17772130
OUT OUT IN
IN
17772132
OUT OUT IN
OUT
17772134
OUT OUT IN
i OUT
17772136
OUT OUT OUT OUT:
+ ..•••..•.••••••••••• ·+· .. ·+· - . ·+·. - ·+·. - ·+· ·+
* VAXstation I MSVll·QA CSR addresses
I

\.,.____.

The remainir3 sets ( ~ble 2-5) consist of S pairs of jumpers,
each pair having a common pin. The VAXstation 1 settings are
indicated with an asterisk (*).

2-13

SYSTEM CONFIGURATION
Table 2·5:

MSVll·OA Jumper Pairs

+· ...... - ............ -+- .............. ·+-. - .... ·+· ...... ·+
I FUNCTION
l SELECTION
! JUMPER ! STATUS I
+- ... - .. - ........ - - - . ·+· .. - - . - .. - - - . - . ·+·. - .... -+- - .. - - . ·+
MEMORY TYPE

i CSR PARITY

A
8

OUT
IN

I
I
I
+············-···+········+········+
i

NON-PARITY

A
B

IN
OUT

OUT

+ ... - .......... - - .... ·+·. - - ... - - .... - . ·+· - ..... ·+· .. - . - . ·+
PARITY ERROR ENABLE i ENABLE
I
H
IN
!*
i

+················+········+········+
I DISABLE
H
OUT
J
IN
+· ... - - . - - .. - - . - . - - - - -+· .. - - - - - - . - - - .. ·+· ... - .. ·+· - ..... ·+

CSR MEMORY TYPE

22 bit CSR

OUT

·*

I
L
IN
+················+········+·······-+
I 18 bit CSR
K
IN

I
L
OUT
+- - .......... - ....... ·+· ...... - - - .. - - . ·+·. - - - .. ·+-. - .. - . ·+
I/0 PAGE SIZE
I 4 k WORD
C
I
IN
I*
D
I
OUT I
+· ... - - . - - - .... - -+- - - - - - - ·+· ... - .. ·+
: 2 k WORD
C
OUT I
D
IN

+··············-----··+-·········--····+····-···+········+
BLOCK MODE

; ENABLE

IN
OUT

+················+········+········+
1

DISABLE

OUT
IN

+ - - . - . . . . . . . . . . - . . . - . -+- - - - - - - - . - - . . - - . + . . . . . . . . + . . - . . . . . +
ws
WRITE WRONG PARITY
FROM CSR
OUT
·*
+·. - ... - . - .... - . -+- - . - - - - ·+· ... - .. ·+

: FROM BDAL<l6>

WS
W6

IN
OUT

+·. - - ... - - ...... - . - - - ·+· ........ - ... - . ·+· ...... ·+· - .... - -+

* VAXstation I position
For more information on the MSVll-QA
[TBS] , (TBS] .

2-14

memory,

see

the

MSVll-QA

(
I,

(

·------ ----- -------------------- -------------------------------------------------+I
I I 11 I I · CJ
+------------------------------+
LEDs
II
+------------------------------+
RQDX1 TO SlGHAL DISTRIBUTION

I
I
I

...

(

t-++++

lUN

PAHEL CABL& CONNECTOR

I
I
I
I
I

I
I

I
I
I

I
I
I
rvl
I
....... I
U1 I
I
I
I
I
I
I
I

I
I

fw3
V-14 I

I
I
I
I

I
I
I
I
I
I
I

ADDRESS JUMPERS
(12150 OCTAL)

A12
... --+

W:l

+ +

+ + +

+ +

+ + +

+
+

1,1

+-+

+-+
----+

Fiqure 2·5:

+---+

+------------------------+
RODXl Jumpers

+-+

~=
n

I •.
0

+-------~----------------+

e
H

I!:

SYSTEM CONFIGURATION
2.5

MASS STORAGE

The VAXstation I Mass Storage subsystem includes the RQDXl
controller, RXSO Diskette Drive, and RD52 Fixed-disk Drive.
2.5.1

RQDXl Controller

The RQDXl (Part Number M8639) provides the interface between the
Q22-bus and the disk and diskette drives (Figure 2-5). It
communicates with the drives using MSCP (mass storage control
protocol).
The RQDXl is a block-mode OMA (direct memory access)
device.
A single cable (Part Number BC06L-1C) connects the RQDXl to the
Mass Storage Cable Distribution Panel. This panel (also called
the signal distribution board) is attached to the pin side (side
2) of the backplane.
2.5.1.1 Jumpers - As Figure 2-5 shows, the RQDXl contains three
sets of jumpers.
The jumpers are shown in their factory-set
configuration. Wl through W4 are for manufacturing use only.
The LUN (logical unit number) is set to LUN O; that is jumpers
LUN7 through LUNO are all out. The device address is set to
772150 (octal); that is jumpers Al2, AlO, A6, AS, and A3 are in
(see Table 2-6).
Table 2-6:

RQDXl Device Address Select

+- - - - - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+- - . - -+

BOAL:

!17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02:01 00i
+- - - - - - - . - . - . - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+- - - - -+

DEVICE ADDRESS SELECT
JUMPER

+- - - - - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+- - - - -+
A:
12 11 10 9 8 7 6 5 4 3 2:
1 1 1 l
1 l 0 l 0 0 0 l l 0 l 0 ) 0
+ - - - - - - - -+ - . - - -+ - -+- - - - - - - . +- - - - - - - -+ - - - - - - - -+ - -+ - - - - -+
OCTAL:
7
7
2
l
5
0
+ - - - - - - - -+ - - - - - - - -+ - - - - - - - -+- - - - . - - -+ - - - - - - - -+ - - - . - - - -+

For more information on the RQDXl, see the
EK-RQDXl-UG.
2.5.2

RQDXl

User's

Guide,

RXSO Diskette Drive

The RX50 is an 133 mm (5.25 in) dual random access, moving-head
drive.
It stores up to 800 kB (400 kB per diskettel
in
fixed-length
blocks
on
two,
pre-formatted,
removable,
single-sided diskettes.
The RX50 is connected to the Mass
2-16

SYSTBH CONFIGURATION

storage Cable Distribution Panel with one cable (Part Number
17-00285-02), and to the power supply with another cable (Part
Number 70-20435-lK). This second cable also connects the RD52 to
the power supply.
2.5.3

RD52 Fixed·disk Drive

The RD52 is an 133 mm (5.25 in) random access, moving head,
non-corltact drive, which s~ores formatted data in fixed-length
blccks on four non-removable disks. Total storage capacity of
the eight surfaces is 28 MB. The R052 is connected to the Mass
Storage Cable Distribution Panel with two cables (Part Numbers
17·00282 and 17·00286), and to the power supply with another
cable (Part Number 70-20435-lK). This third cable also connects
the RX50 to the power supply.
2.6

VCBOl VIDEO CONTROLLER

The VCBOl (Figure 2-6) is a quad-height, Q22·bus bit-mapped video
option
module
(Part
Number M7602), providing workstation
capability for 022-bus systems.
The bitmap memory (also called video memory),
is
256 kB
{kilobytes) of MOS RAM, residing in the Q22-bus address space.
In the VAXstation 1, a subset (sometimes called the screen
memory) of the bit-mapped video memory is displayed on a 48 cm
(19 in) monochrome monitor (the VR100). The VCBOl relies on the
CPU to generate all images stored in video memory.
The VCBOl also provides several basic I/0 functions, including:
o
o
o
o
2.6.l

cursor controls
mouse interface
keyboard interface
primitives for VTlOO-style split-screen scrolling
Switches

The VCBOl contains switches to select:
o
o
J

The MSA (Memory Starting Address)
The CSR (Control and Status Register) base address
Display density

2-17

SYSTEM CONFIGURATION

+-----·:---------------------------------------·
I
I
I
I
I
I
I
I
I

I
I

I
I
I

I
I

'I
I

I
I

+---+
+ - ..
I

-----+

+--·
I
I
I

I
I
I

I
I

n
m

....
C)

en
....c

+---+

+-----·
I

I
I
I
I

I
I

I
I
I
I
I
I
I

+
11"11
+ Cl>

l"'t

::r

(I)

tll

+ + + + + + ..

... + + + + +

Im
+ ~

I
f

.. !"11

1
I
t
I
......................
l

.. ..
I

+ +

.......... ,t.
I

2-18

I
I

.+--i

I
I
I
I

SYSTEM COHFIGURATIOH

'--~

2.6.l.l Memory Starting Address (MSA) ~ Switches 1 through 4 of
switch-pack El4 select the starting address for the 256 kB block
of MicroVAX physical memory where the VCBOl resides.
Table 2-7
shows the switch settings (0 •OH and l •OFF).
Table 2·7:
BOAL:

El4:

VCBOl MSA Selection

+-···+----+·--·+·-·-+
20
19
18 II
I 21
+- .. ·+- .. -+· - . ·+- .• ·+
I

I
I

+· .... -+· - . -+· - . ·+· - - -+- - - -+

I (kB)

+· - - - - ·+- - - ·+· - . ·+·. - ·+- - . ·+
l
1
l ~
1
*! 3840

I 3584
3328
3072
2816
2560
2304
2048
1792
1536
! 1280
1024
768
512
256
I

1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
0
0
1
1
0
0

1
1
0
0
1
1
0
0

0
1

1
0
1
0
1
0
1
0
1
0
1

1 = OFF
0 = ON
0
+· - ... ·+· .. ·+·. - ·+· - . -+- - - ·+
0

* VAXstation I setting
To take advangtage of certain MicroVAX architecture features when
programming bit-map operaticns, the video memory always resides
in the topmost 256 kB of the 4 MB MicroVAX physical address space
(see Figure 4-2).
Therefore, all the MSA switches are set to
OFF; that is, BDAL<21:18> select the 256 kB block
starting at
3840 k.
2.6.l.2 CSR Base Address - In the system I/O Page, 32 locations
are allocated to the VCBOl. These locations allow the CPU and
VCBOl to exchange control and status information,
through
hardware registers on the VCBOl. As a group, these registers are
~ometimes called CSRs (control and
status regist~rs); however,
only the first register is specifically named the CSR (see Table
3-21. Switches 1 through 7 of switch-pack E48 correspond tc
BDAL<l2:06>, and select the base address for these registers
(Table 2-8).

2·19

SYSTEM CONFIGURATION
Note that BDAL<l7:13> are all ls (ones), allowing the address to
be set in the range of 7600xx through 7777xx (octal); BOAL
<05:01> select one of the 32 registers; and BDAL<OO> is byte
select and MBZ (must be zero). Currently, in the VAXstation I,
E48 switches S7:Sl are set to 172 (octal).
This
makes
BDAL<l7:00> = 7772xx (octal; 3FExx, hex).
Table 2·8:

CSR Base Address Select

+ .... - . - . - . - . - -+- - ... - - - • - • - - ....•. ·+· ... - - •. - ...• ·+· ·+

BOAL: 117 16 15 14 13!12 11 10 09 08 07 06j05 04 03 02 OljOO:
+·. - .. - - - - - - - - -+- - .. - - - - .... - - .... - ·+· ..... - - - .. - - ·+- ·+
! (HARD WIRED) i CSR BASE ADDRESS
! CSR SELECT
+ - - - - - - . - - . - - . ·+. - - - - - .•. - - •. - . - - - - - + - - .. - .. - . - • - - ·+ .. +

E48: I
I 1

I S7 S6 SS S4 SJ S2 Sl I
I
1 1 1 11 1 1 l
l
o l 01 x x x x xi o;
+- ... - - . ·+· .. - ·+· -+- - - - - - . ·+· - - - •. - ·+· - - . - - - ·+·. - . -+- -+

OCTAL:

+· - . - - .. ·+· - - - - - . -+- - - - . - - ·+- - - - - - - -+- - • - - - - -+- - - - - - . ·+

2.6.1.3 Display Density · The VCBOl can support either full-page
or half ·page monitors, selected by switch E68 and switch 58 of
switch-pack E48 (Table 2·9). The VAXstation I uses a full-page
monitor (the VR100) and E68 is ON (position C2); £48 SS is OFF.
Table

2~:

Display Density Selection

+ .. - - . - .. - - . - - . ·+. - . - - . - - .. - .. - - +

! FULL·PAGE
i MONITOR

I HALF-PAGE
I

MONITOR

+ - . - • • • - - - +- - • • - • - - • - • • - - -+- - . - . - - - - - - - • - . +

E68

ON (C2)

OFF (Cl)

E48 S8

OFF

+ . . - - . - . . ·+. - . . . . - •. - • - . - . + •...•.• - • - - - •.. +

DIAGNOL

48 cm (19 in)

PIXELS

829 k

38 cm (15 in)
I

384 k

+·········+···············+····-··-·······+

2-20

SYSTEM CONFIGURATION

2.7
2.7.l

OPERATOR I/0 DEVICES
VRlOO Video Monitor

The VRlOO monitor (Part Number VRlOO·AA) has only two external
controls,
contrast and brightness (Figure 2-7).
Alignment
controls and adjustments are contained within the enclosure, and
described in Chapter 5. The functions of the four LEDs are also
described in Chapter 5.

POWER

VIDEO

HSY NC

VSYNC

0
VIDEO BNC
CONTRAST
HSYNC BNC

VSYNC BlllC
BRIGHTNESS

Figure 2·7:

VRlOO Monitor Rear Panel

The monitor is connected to the Patch and Filter Panel Assembly
with the video cable {Part Number BC18T-10). At the VRlOO end of
this cable, the VIDEO, HSYNC, and VSYNC coaxial leads are
connected to match the icons molded in the cable and the VRlOO
enclosure.
Note that the lead from the keyboard also plugs
~nd of this cable.

into

The monitor has a self-contained power
pow:r cord.

and

2-21

supply

the
its

VRlOO
own

SYSTEM CONFIGURATION

2.7.2

LK201 Keyboard

The keyboard Part Number is LK20l·CA.
"C" indicates that the
configurable keys on a standard LK201 are configured for a
VAXstation application. "A" means that the keyboard supports
USA/Canada English language conventions (the VAXstation I does
not currently support any other language options). The keyboard
is
driven
by
a
microprocessor, and contains a set of
microdiagnostics.
Communication between the keyboard and the VCBOl is full duplex,
serial asynchronous at 4800 baud, and conforms to EIA standard
RS423. The keyboard lead is terminated in a 4-pin modular
connector that plugs into the monitor end of the video cable
(Part Number BC18T·l0).
2.7.3

VSlOX Mouse

The hand-held mouse (Part Number 30-20038-01) controls the
pointer image (called an icon) on the monitor screen. It
provides relative pointer position to the VCBOl, in the form of
x-coordinate and Y·cJordinate pulse outputs. Three pushbuttons
on the mouse perform software-defined functions.
The Mouse is
connected to the Patch and Filter Panel Assembly with a 3.7 m
(12 ft) 10-conductor cable.
2.7.4

LASO And LAlOO Printers

Either an LASO or an LAlOO can be installed as an optional
hard-copy output device. Both are dot-matrix printers, and print
either bit-mapped or character cell graphics.
Either printer
communicates with with the CPU through the SLU (serial line
unit), and is connected to the CPU insert in the Patch and Filter
Panel Assembly with a single cable (Part Number BC22D·l0).
2.8
2.8.l

OPTION MODULES
DEQNA Ethernet Controller

The DEQNA (Figure 2-8) is a double-height Q22-bus module (Part
Number M7504) that provides an interface between the Ethernet LAN
(local area network)
and
the
VAXstation 1.
The
DEQNA
encodes/decodes
data
transferred between the CPU and the
Ethernet, in accordance with the Ethernet protocol.
With a DEQNA, the VAXstation I becomes a node on the LAN, and can
communicate with other LAN nodes.
In addition, the DEQNA
2-22

SYSTEM CONFIGURATION

provides the capability to down-line load the
the LAN.

VAXstation 1

over

NOTB - G7272 Required

In the VAXstation 1, it is recommended that the
dual-height OEQNA be installed between the last
quad-height MSVll·QA and the quad-height VCBOl
(see section 2.1).
Therefore, a G7272 Grant
Continuity card must be installed in the A or C
connector position of the same slot as the OEQNA.
The OEQNA communicates with the .Ethernet through an H4000
Ethernet Transceiver and Cable Tap. A Transceiver Cable connects
the H4000 to the DEQNA insert in the Patch and Filter Panel
Assembly.
2.8.1.1

Jumpers · Figure 2-8 shows the three OEQNA jumpers:

This jumper identifies the first or second OEQNA in the
system.
Factory connected to pin 1 as shown, it identifies
the first (and only, in the VAXstation 1) DEQNA.
It is
normally installed.

This jumper controls the Hold-off
removed.

Timer.

normally

This jumper controls
installed.

Timer.

normally

the

Sanity

correct
for
most
Factory set as shown, W2 and W3 are
For more information see the DEQNA User's Guide
applications.
EK·DEQNA·UG.

2·23

SYSTEM CONFIGURATION

+- - - - - . - ............... - - - ... - .. - . - ........ - . - .... - - .. - . - ..... - ·+
+ - ••••• - ••• - • - •••••• ·+
Jl
I
LEDs
i

I l l ll ll

+····················+

+··+
Wl

+····················+
I EXTENDED BOOT ROM
I
+····················+
+ •. +

;

+ ••.••.• - •••••••• +

DMARC
GATE ARRAY
+

+•· · • • • · • • · • • • · • ·+

(OUT)

+-+

+·+

+- .+

+·. - . - - - - - - . - - - .... - ...... -+

+· - . - - .. - .. - - ... - .. - - - - . - - - ·+

[MicroVAX I OM Figure 22-1]
Figure 2·8:

DEQNA Jumpers

2-24

SYSTEM CONFIGURATION

DZVll Asynchronous Line Multiplexer

2.s.2

The ozvll (Part Number M7957) interfaces up to four asynchronous,
serial, data communications channels to the Q22-bus. In the
VAXstation 1 it is intended to be used to interface a plotter to
the system.
It might also be used as a 9600 baud asynchronous
DECnet link to another VAXll, if a DEQNA is not installed.
In
the VAXstation I, it will not work as a terminal interface. The
ozvll includes the module, an insert for the Patch and Filter
Panel Assembly, and a cable between the two.
2.8.2.l Switches And Jumpers · As shown in Figure 2-9, the DZVll
contains a set of 10 and a set of 8 DIP switches, and 16 jumpers.
The switches select the device starting address (Table 2-10) and
floating vector (Table 2-11). The jumpers (Table 2·12) configure
the module for various applications; factory set as shown, they
are correct for most applications.
·
The address switches are factory set to
except 57):
Table 2·10:

address

760100 (all OFF

DZVll Address Switches

+-. - - .. - ... - - - ·+· - .. - - - . - - . - - - - ...... - ....•. -+· •• - - •. -+

BOAL: .17 16 15 14 13!12 11 10 09 08 07 06 05 04 03!02 01 OOi
SWITCH

+. - - . - - - - . . - . - -+. - - - - . . - . . . - . . . . . . - . - - . - - - - . -+. . - . - - - -+
DEVICE ADDRESS SELECT
+ . . . . . . . - - - - - - -+ . - . . . . - - . . . . . . . . . . - . . . . . . - . . . + - - . - . . - . +

: 1

9 lOi

:12 11 10

0i 0

1. 0

2
0

+·--·····+·····+··+-··-----+-····-··+······-·+········+
7
6
0
1
0
i
0
OCTAL:
+- - ..... ·+· - - . - . - ·+· - - ... - ·+· - . - .. - ·+·. - .. - . ·+· .. - ... ·+

2-25

)

·------------------------------------- ----------- ---------+-----------------------------·
+-----------------------------·
WS+
we+

+Wti

•

•w7

----- ~-

I
I
I
I

I
I

·-----

-------+

+--------------------- +
+------------------- +
+-------

·--·

WI+
W4+
+
+

+ +

+W2
+W3

... ..

+--+

.. --+

Wl4

WIS

WI&

i
..•
>t

Ill

-----------

-----+

----~----

"°

A
J

........

+++++++-.++

++++++

ONI 111111111

Ortl 11111

++++•+++++

++++++

AOORE~S

+-+

+--+

WIO

WI I

·-·

VECTOR
SWITCHES

SWITCHES
+-+

·------ ---------- ----+

+ -

+--

-------

-------·

DZVll Switches and Jumpers

+----

II
I
I

I
I
I

+-+

·------------------------+

OFF 111111

++++++++++

+--+

I
I
I
I
IIN
I '
IN

OFF 1111111111

I
I

A
I2

Ill

--+

+--·

8
I...

--------

Wl2

• II
....

+--------- ---------·------

---+

WIJ

-----

• •--•w9

I
I
I
I
I

I
I
I
I
I
I
I

- - .... - -- - - ... +

SYSTEM CONFIGURATION

The vector switches are factory set to vector 310: Sl, 54, and
Switches S7 and S8 are not used:

ss OFF: S2, S3, and S6 ON.
Table 2·11:

DZVll Vector Switches

+- - - - - - - • - - - • - - • - - •••• - - - - -+- - - - - - - - • - • - •••• ·+· - - - - - - ·+
BOAL: 117 16 15 14 13 12 11 10 09!08 07 06 05 04 03102 01 00!

SWITCH
S:

+ - • - • - • - ••. - - •• - - ••• - •••.• ·+ •• - .••• - - •••••... +- - - - .. - -+
VBCTOR SELECT
!
+· .• - - .. - •. - .. - . - -+- - - - ••• -+

l
' 8

l 0

2
1

3
6
1

s
0

5
4
0

6! 7
31
11 0

+···-····+········+-·······+

OCTAL:

3
1
0
+········+····--··+·--·----+
Table 2·12:

DZVll Jumpers

+· .. - . ·+· - .. - . - . ·+- - . ·+· - .. - ... - ..................... - ...... - .. ·+
:JUMPER; STATUS
NOTE! FUNCTION
+· .... ·+ .... - ... ·+- - - -+- - •• - ..•• - •..• - . - - •• - - .. - - - .. - - - - - - - - - - - -+
1

Wl
W2
W3
W4

•REMOVED
!REMOVED
iREMOVED
!REMOVED

Wl:W4 connect DTR (data terminal ready
to RTS (request to send)

+- - • - - -+- - - - • - - - -+-. - -+-. - - ...... - - - - . - ... - . - - . - . - - ... - - . - - - - - - ·+

W5
W6
W7

,REMOVED
]REMOVED
!REMOVED
!REMOVED

W5:W8 connect FB (forced busy) to RTS

+- - - - • ·+ .. - .. - ... +- - - ·+·. - . - ..... - . - - .. - ....... - - . - - - - - - - - - - - - ....

W9
,INSTALLED·
WlO INSTALLED'
Wll INSTALLED
Wl 2 INSTALLED'
Wl3 . INSTALLED
Wl4 INSTALLED
Wl5 INSTALLED•
~16
INSTALLED

1
W9:Wl6 connect bus signals
2
2
1 '
1
1
1
1

t- - • - - •• + .••. - . . . - + - . . • + •• - . . . . . . . • • - • - . . ••• - . . . • - . - . - - - - . - • . - . • . +

NOTES: 1. Removed only for manufacturing tests. Should not be
removed in the field.
2. Remcved if the module is installed in C/D interconnect
slot.
For more information, see the
Technical Manual, EK·DZVll·TM.

DZVll

2-27

Asynchronous

Multiplexer

CHAPTER 3
VCBOl FUNCTIONAL DESCRIPTION

This chapter is a functional description of the VCBOl Video
Controller and its associated graphics I/O devices. Functional
descriptions of other VAXstation I system components and options
are contained in the documents listed in the Preface.
Unless otherwise noted, all descriptions refer
full-page operations with the VRlOO monitor.
3.1

VAXstation I

OVERVIEW

Figure 3-1 is a simplified block diagram of the VCBOl, showing
the major functional areas, with the exception of the power
supply and timing generator. Figure 3-2 is a functional block
diagram of the VCBOl, showing the major address and data paths.
The following sections describe the functional operation of each
major area.

3-1

VCB01 FUNCTIONAL DESCRIPTION

Q22 +·····+
INPUT/OUTPUT
BUS I
I
+······-···-·····-·+
/-··\jXCVRS!<··+··>ICONTROL AND STATUS!
\···/I
I
I
I REGISTER (CSR) I
+···-·+
I
+--··········-·-···+
I
I
INTERRUPT
I
I
CONTROLLER
I
+··················+
.1
I
CRT CONTROLLER I···+
I
(CRTC)
!
i
!
+··················+
I
!
MOUSE LOGIC
1<··1····-·····-···MOUSE
+--················+
I
UART
I < · • I • • • • • • • • • • • • • ·KEYBOARD
+ ••••••••••••• - •••• +

I
I
I
I

MEMORY
+··················+
I< .. +

I
I
I
I .•• +
+· ..... ············+
I

+··>!

VIDEO MEMORY

+·······+
VIDEO
+·->I
SCAN LINE RAM
+··>!SHIFTER! -·>TO
I
+····-·············+
I
+·····--+
MONITOR
+··>i
CURSOR RAM
I·--+

+·-···-·--····-----+
Figure 3·1:

VCBOl Simplified Block Diaqram

3-2

(

----

iJ~Z

BUS

---/\----

(

II
.. - \ / - - +

··------------- ~1xcvRSfRCV/ 1--- ----->CTRL
I
•-----·
I
IDRivRI
··--->I CSR I
I
•-----•
+-----+
•-------•
••----------------IMOUSEl<--IMOuSE f<---MOUSE
I
I REG I
I COUNTER I
I
+-----+
+-- ----•
I
•-----+
I
+---->IDUARTI<----- ---------KEVBOARO
I
I +-->I
1~---------------TABLET
I
I I
•-----•
I
I I
•---------•
I
+-1-->IINTERRUPTl<-----------INTERRUPTS (7)
I
I +-->ICONTROLLRI
I
I I
+---------+
•-----+
I
·----+ I I
·----+ +-------------- 4 -------->ILATCHI
+-->IXCVRl--+-1-->ICRTCI I
+----+
+----+
I
I
+----+
..., I
+----..
+-->I
1--+-->IMAP I
ISCANI
I
1-->IMEM I
256 kB
I
+-----+
I
+----+
IAODRl-->ILINEf--+-->I
I
IAOORI
RAM
w
+ -•IADOR 1---+-------------->IMux I
IMAP I I
+-----+
IMUX I
+-----+
I
ILATCHI
I
·----+
+----· I
I
1-->fADDR
I
•-----•
•--------------------------------1------------>I
I
I
I
+----+
I
v
+----+
I
I
I
·-->IBUFFI - 1-------------~------------------+-->fRFSHl--->I
I
I
I
·----·
I
MEMORY REFRESH--->IMUX I
·----·
I
I
I
•----+
I
·--- - -------1------------------------------------------------------>IDIN I
+-----+
I
I
+----+
+-----I DOUTf-->fDATA
I
+-->IPROMl~->1/0 DEVICE SELECT
+-->IWRITEl----------->IWE
I
!LATCH
I\ DATA
I
+----+
I
ILOGICI
I
I
I
I
·-------·
I
I
·------+
I
+-----+
IRAS/ I
I
1-->IVIOEO I
I
ADDRESS ,,
CLO~KS·---ITIMINGl---+--------------------->ICAS
I
+-----+
ISHIFTERI

·-----·-----+

<
n
DJ

.
0

....

I
I

•-------+
•-----+
I
+-->!VIDEO&!----------------------------->!

I
I

•~-----+

+-->1CUR~ORI---------

----------------------------------------------------->!·-------+I

•---+

+------+
1-->IDIAl-->VIDEO OUT
. ----------- I ->fCURSORl------------------------>ICURSOR I
+-------+
I
I
I
I REG
I
I TIMING I
+-------+
I
I
I
•------+
I
1----------------------------->ICuRSO~ 1-->I
I
I
+ -----+
·-------+
ISHIFTERf
+---+

·-------..I

• --------- - --->IRAM

Fiqure 3·2:

VCBOl Functional Block Diaqram

•n
toi
....

Iii

•.....,n
toi
....
0
2S

VCB01 FUNCTIONAL DESCRIPTION
3.2

TIMING

Refer to Figure 3-3. Basic timing for the VCBOl is provided by
an on-board 69.1968 MHz oscillator, providing a 14.45 ns clock.
(An alternate on-board 32 MHz oscillator is not used with the
VR100 monitor.) This frequency is divided through a pair of
flip-flops and a counter to generate the clocks listed in Table
3-1.
A timing PAL (programmable logic array) uses these clocks
to generate the CRTC (CRT Controller) clock input as well as
timing for other functions (for more on CRTC timing, see
subsection 3.4.1).
+ .....• +

+·-----·-+
I
+----·+
+----·+
1 69 MHz ! ·····>+
I osc
i
\
i
+- · - · - - - · +
I
+ · · Dl 2DOTCLK · · > ! F /F I · - + · · > I F /F : • - +
+. - .. - •• - +
I
+-----+
+----·+ i
i 32 MHz I·····>+
: osc
I
I
I
+·------·+
l
I
I
+----··-·····I E68 I ··DlODOTCLK/2--------+
I ··Dl2DOTCLK/4-------············--+
+- -. . --- -- - !
: ;
I
+----·--·---->+
+·----··+
+··---+
\
I
! ··Dlll20NS··>l
I
+ - · · · 012 6 ONS · · + · · > I COUNTER I • • Dl 12 4 ONS · - > i PAL
I
I
l··Dll480NS-->!
+-------------->+
!
I --Dll960NS-->I
i
+---····+
I
+ - - - - - -+
+ - - - - - - - - - . - - - . - - - - . - - - - - >!
+--···+

Figure 3-3:

Simplified Timing Generator

3-4

VCBOl FORCTIORAL DBSCRIPTIOR
Table

3~:

VCBOl Clocks

+ •• - ••. - • - - - - -+- - • - - - - - - - • - - - • - - -+

I
I NAME
I

I PERIOD (ns)

+------·-+--------·+
I ACTUAL I ROMIRAL I

+- - - ..... - •• - •• ·+· ..... - ... -+·. - ... - . ·+

Dl2DOTCLK
DlODOTCLK/2
Dl2DOTCLK/4
Dl260NS
Dlll20NS
Dll240NS
Dll480NS
Oll960NS

14.45
28.90
57.80
57.80
115.60

15
30

60
115.5

231.20

231. 0

462.40
924.80

925.0

462.5

+· ..... ·······+--······+·········+
Another on-board oscillator provides a 3.7 Mhz clock to the
keyboard/auxiliary DUART (Dual Universal Asynchronous Receiver
Transmitter) .
NOTE -

Nominal Values

In most cases, the following descriptions and
explanations rely on the nominal values listed in
the preceding table.

3. 3

'------

022·80S/CPU INTERFACE

The VCBOl interface to the 022-bus
us~s
standard
DCOOS
transceivers and a DC004 protocol chip, and a 9519A Interrupt
Controller (Figure 3-4). The interface supports the following:
0
0
0

0
0
0
0

DATO
DATI
DAT IO
DATOB
DAT BO
DAT BI

Write word
Read word
Read/modify/write word
Write byte
Write block
Read block
Read interrupt vector

The VCBOl can perform a block data transfer of up to two words.
The block must be longword aligned (BDAL<Ol:OO> • 0).
The Q22-bus signals are described in Table 3-2.

3-5

)

Y5l9A
!NTERRUl-'T
C.ONTROLLt.R

+------ . .

I
RlPI
IKEYBOARD}--COMINT----- IIRQO
I
(CRTCJ------VSYNC------ llRQl
I
{CRTCJ------STARTX----- IIRQ3
I
(MOUSEJ-----MOUSECTINT--IIRQ2
I
[MOUSE)-----MSWA:C------IIRQ4:6l
lNTEN-------lENI
I
·----IACKI------------------------------------------------ ------- ---------------llACK
I
I
+---+
I
<>!--+
I +--DAL15:01--ILATI----------------------+------------------- ----- --LAOR15:01--IC/-D
I I
I I
+---+
I
•-------------------------------------IRD
I I

•-----+
+--1 CSR
I I SW

I
I

•-----+

XCVRS

Ii----------

I I

+---•

l I

ll
I

+--OAL07:00--IB Al---------- -----~-----1-- --1-1
I
BUFEN--IEN I
•-------------1-- --1-1I
·---·
I
DC004
I
I I
I
I
REG SEL
I
I I

I
I I
I I

•-------•

I
I
I
I
+----

I
I
I
I

------------:==!~~
I

6007:00------------vEC---

I
I

_.
0

'>°

Figure 3·4:

Q22~us

Interface

-------!------------+

--1----I

I
I

+-----+
·--101
Rt:: 1.:; SEL
I
IDC003f--l-+--DAL00---------------------100
I
PROM
I
+--lxcvRSl--l----MATCH---------------------102
I
•----•
I
+-----+
I
I
I
l-l--LADR05:01 -IADR I
I
1 - - \ loRvRSI--•
I
INllllDl--INwD--• I
I
1--CSRSEL
I
I Q22 \I
1-------RINIT
I OUTLBl--OUTLB---+
I
1--CURREGSEL
I
' BUS , ,
I -------RBS7
I OUTHB I --OUTHB
I
I - -MOUSE SEL
I
\---/ I
1-------RllllTBT----------- ---------IWTBT
I
I
1--CRTCSEL
I
I
I
1-------ROIH----------------------IDATAIN I
I
1--INTSEL----- ..
I
I
l-------OAL21:16--+
I
SEL21--IOSEL--+
I
1--UARTSEL
I
+-----·
I
I
SEL4 f --BMSEL
I
I
I - -MO$
+-----------------eoour-----1
- ----------IDATAOUTI
.. ----IEN
I
·-------- --------esv~c-----1---------------ISVNC
I
•--- •
·-----+
.. -..
I BRDLV 1--RPLY
I MSA t----------------1=1--HIMeMMATCH--IEN
I
I SW I
·-·
.. -------+
+-----+

l I

.. ------+

-•

VC801 FUNCTIONAL DESCRIPTION
Table 3·2 z

Q22·bus Signals

+· - .. - . - ·+· - .... - - ... - . - . - - - - - - . - - - • - .• - • - - - - - - - - - - - - .... - ....• ·+

IMNEMONICI DESCRIPTION

+- - • - - - . -+- - - - - •. - - - .. - - .• - - - - - - - - - - - - - . - - - • - • - - - • - •• - - . - - . - . - - -+

BIRQ7
BIRQ6
BIROS
BIRQ4

Interrupt ReQuest

BI AKO/I

Interrupt AcKnowledge Out (BIAKO)
and
Interrupt
AcKnowledge
In
(BIAKI) -- Asserted by processor.
Passed through the devices to the device with both
interrupt request asserted and the highest priority
level.

BDMR

DMA Request -- Asserted
mastership.

BDMGO/I

DMA
Grant
Out
(BDMGO)
and
DMA
Grant
In
by
arbitrator
to grant bus
(BDMGI) -- Asserted
mastership. Passed through devices to device that
asserted BDMR.

BSACK

BDMGO ACKnowledge -- Asserted by device in response to
BDMGO, indicating device is now bus master.

&DAL

Data/Address Lines:
<21:18> -- Data/extended address.
<17:16> -- Parity control/extended address.
<15:00>-- Data/address.

BSYNC

SYNChronize -- Asserted by master to indicate
placed an address on the bus.

BOIN

Data IN -1.

2•

BDOUT

Priority level
Priority level
Priority level
Priority level

device

7.
6.
5.
4.

request

bus

has

Asserted with BSYNC - master ready for
input.
an
interrupt
without
BSYNC
Asserted
occuring.

d.: ta

Data OUTput - . Master has placed valid data on bus.

3-7

VCBOl FUNCTIONAL DESCRIPTION
Table 3·2:

022·bus Signals (continued)

+- - .. - - - ·+·. - - - . - . - . - - - - . - . - .. - . - •. - - .. - . - - .. - - - ...•.• - .. - - - ... -+
;MNEMONIC! DESCRIPTION
+- - • - - . - ·+ .•. - - - - - . - - ... - - - . - - . - .. - - - - . - - - • - ••.. - - .. - ... - - - .... ·+
BRPLY
RePLY -·

BWTBT

Slave has read data from
master's BDOUT; or
Slave has placed data on
master's BDIN.

bus

response

bus

response

WriTe/ByTe -·
1.

Asserted with BSYNC ·· output sequence (DATO or
DATOB} is to follow.
Asserted with BDOUT during DATOB ·· indicates byte
addressing.

BBS7

Bank 7 Select
Asserted by master to
Page (address in BOAL <12:00>).

BHALT

HALT processor ·· Processor services halt interrupt,
stops normal program execution, and enters console
mode.

BREF

memory REFresh ·· Forces
devices.

dynamic

memory

BEV NT

external EVeNT -- External event interrupt
(for example, line time clock interrupt}.

request

BI NIT

INITialize
Resets system, placing
the bus in a known state.

all

BDCOK

DC power OK -- Asserted by the power
power is within tolerance.

supply

BPOK

Power OK - - Asserted by the power supply when ac power
is normal. When negated, initiates a power-fail trap.

refresh

reference

devices
when

I/O

on
de

+- - - • • - • •+- - - . • - • • • • - • . • • . - • • • - - • • . • • - • • • • • • • • • . • - . • • - • - - • - - . . . -+

3.3.l

Interrupt Controller

The 9519A Interrupt Controller handles eight interrupt
on priority levels 0 (highest) to 7 (lowest):

3-8

requests

VCBOl FUNCTIONAL DESCRIPTION

0
1
2

3
4
5

6
7

DUART
Vertical Sync
Mouse
Cursor Start
Mouse Button A
Mouse Button B
Mouse Button c
(spare)

set of internal registers control specific features
of
Interrupt Controller operation. The registers are described in
Chapter 4.

Figure 3·4 shows the control and data paths for the Interrupt
Controlller.
Each interrupt level has its own vector, stored in
the controller's internal 8 X 32 Response Memory.
When an
interrupt is requested on any level, the group interrupt (GINT)
signal asserts BIRQ4. When the CPU acknowledges the request, the
controller selects the highest priority request, asserts RIP
(response in process), and outputs the vector on BDAL<07:00>.
3.3.2

Registers

Control and Status information is exchanged between the VCBOl and
the CPU through hardware registers and 32 16·bit locations in the
I/0 Page. These 32 locations are listed in Table 3-3, and
described in Chapter 4.

3-9

VCBOl FUNCTIONAL DESCRIPTION
Table 3·3:

VCBOl I/O Registers

+ - - - - - - . - . +- - - - - - . - - - - - . - - - . . - - - . - - - . . . - . - . - . - - - • - - - . - - . - - . . - - - - +
i ADORESS*I NAME
I
+. . - . . . . - - + - - - - . - . . . - - . . . . - - - - . . - . - . . - - . - - . • . . - . • - . . • - - . . . . - . . . . +
CSR·· Control and Status Re9ister
BASE
cursor X Position
BASE+2
BASE+4
Mouse Position Register
BASE+6
(spare)
BASE+8
CRTC Address Pointer Register
BASE+lO
CRTC Data Register
BASE+l2
ICDR
Interrupt Controller Data Register
BASE+l4
ICSR
Interrupt Controller Command/Status Register
BASE+l6
(spare)
through
BASE+31
(spare)
BASE+32
UART Mode Registers lA and 2A
BASE+34
UART Status/Clock Select Register A
BASE+36
UART Command Register A
BASE+38
UART Transmit/Receive Buffer A
BASE+40
(spare)
BASE+42
UART Interrupt Status/Mask Register
BASE+44
(spare)
(spare)
BASE+46
BASE+48
UART Mode Registers lB and 2B
BASE+ SO
UART Status/Clock Select Register B
BASE+52
UART Command Register B
BASE+54
UART Transmit/Receive Buffer B
BASE+56
{spare)
through
(spare)
BASE+62
+- - - . - - - - -+- - - - - - - - - - - - - - - - - - - . . . - - - . - . - - - - - . - - - . - - - - . - - - - . - - - -+
• BASE= The CSR Base Address (Chapter 2, subsection 2.6.1.2).
CSR · Figure 3-5 shows the read and write paths for the
CSR.
Note that the CSR comprises separate input and output
registers (see Table 4-2 for bit descriptions).
The input
register dala comes from BDAL<06:02>. The CSR output register
returns CSR bit status on BDAL<l0:06,04:02>.
3.3.2.l

3-10

(

+----------------------------------------------------------------------·
I
CSR
CSR
I

I
(IN)
(OUT)
I
I
•----+
+----+
I
+--OAL05-- I
1--TESTBIT
I
I
I
+--OALOZ--1
l--VIDBLANK---------------------------1
l--DAL02-----+
+--DAL03--I
l--NORM-------------------------------1
l--DAL03-----+
+----- •
+--DAL04-- I
I --VIDEN------------------------------1
l--DAL04-----+
1---\ 1ocoo~1---------------------+--DAL06--I
l--INTEN------------------------------1
l--DAL06-----+
1 on \lxcvRsl
I
I
STARTx--1
l--DAL07-----+
\ BUS /+-----+
I
I
MSWA:C--1
l--DAL08: 10--+
\---/ IDRVRSl---------------------RINIT-----ICLR I +----------------------------------ICLK I
+-----+ REG SEL
+--1 CLK I I
+--1 EN I
PROM
I +----+ I
I +----+
+----+
I
I
+---• I
DC004
OMl--CSR SEL--+---------1----------1------------------------IANDI--+
REG SEL +----+
I +---+ I
I
+----RECDIS--1
I
+-----+
+--IANOI--+
I
I
+---+
l--OUTLB---------------1
I
I
I

•-----+

1--+
I
+------------------ILOGICI
1--IOSEL--IANDI
I +----------------1
I
I --BM~.EL--1
1--MODSEL--+ I
+-----+
•-----+
+---+
I
9519A
I
INT CONT
I
1--JNW~----------------------------------+--ICOMB

+----•
I

<
n
bt

0
.....

RIPl--VE~----------------------+

.......
0

Fiqure 3·5:

CSR Read/Write

~
0

lll

...
:0

"O
.......

:z:

VCBOl FUNCTIONAL DESCRIPTION
3.4

CRTC

The CRT Controller generates CRT (cathode-ray tube) timing, video
refresh addresses, and controls cursor position. The CRTC is
programmable, and accessed through the CRTC Address Pointer and
the CRTC Data Register (see Chapter 4, subsection 4.2.4).
3.4.l

CRTC Timing

The horizontal frequency (approximately 54 kHz) and vertical
frequency (60 Hz) of the VRlOO monitor, along with the 925 ns
clock (nominal ·· see Table 3·1, above), determine the timing
sequence for transferring an image from Video Memory to the CRT
screen.
The dual-ported Video Memory is accessed in both halves of a
925 ns access cycle, as shown in Figure 3-6. During the first
half-cycle, the memory is addressed and updated from the Q22-bus.
During the second half ·cycle, the memory is addressed by the
video refresh address from the CRTC, and read to refresh the CRT
screen.
(The update and refresh cycles are described in more
detail in section 3.5.)
. -+· ..• - ... -+· ...... - -+- - - - - .. - ·+· - - - - - .. ·+· - - . - - - - ·+· .. - - .. - -+-.

VIDEO
RE FRESE

Q22-BUS
UPDATE

VIDEO ' Q22-BUS i VIDEO
Q22-BUS
REFRESH
UPDATE 1 REFRESH ' UPDATE

. ·+·. - - - ... ·+·. - .... - ·+· ....... ·+· ..... - . -+- ... - - . - -+·. - .. - - . ·+·.

<-··· 925 ns ·····»
Figure 3·6:

Video Memory Access Cycle

In CRTC terminology, the 462.5 ns video refresh half-cycle is
equivalent to a character time. The number and duration of the
character times determine tle period of Hsync (horizontal sync1;
that is,
the time for each horizontal scan line (Figure 3-nJ.
Using the VRlOO monitor with a horizontal frequency of 54 kHz,
the Hsync period is 18.5 us, or 40 character times (note that
time and frequency values are nominal). The horizontal retrace
period (horizontal blanking) is the difference between the total
time for one horizontal scan line and the displayed (unblanked\
part of the scan line.
For the VRlOO, this is 40 · 30 = lC
character times; er, 4.625 us horizontal blanking.

3-12

VCBOl FONCTIORAL DESCRIPTION

+---·- l CBARACTER TIME
I
v

(462.S ns)

! <••• >I
·····+···--+·····+···--+-//·+-----+---··+--···+·//-+·····+-····
Q22 IVIOEOI 022 IVIOEOI
!VIDEO! Q22 IVIOEOI
!VIDEO! 022

UPOATIRFRSH!UPDATIRFRSHI

!RFRSHJUPOATIRFRSHI

!RFRSH!UPDAT

... - ·+· - - - ·+- - - - -+· - .. ·+·//·+· - - - ·+· - - • -+- - - . ·+·//·+·. - • -+· - - - -

\ ___ /

__ /

\ .. I

\ __ /
I

+ ..• - • +

+····-·········+
l

+·····+
+··············+

+··-·····+

30 31

<• • · • • • - • • • • • • • • • • UNBLANK • • • • • • • • • • • • • • • • • • > ! <• • • BLANK

• • • - >,
(4.625 US)
t<···················· 40 CHARACTER TIMES·····················>·
(18.5 US)

Figure 3·7:

CRTC Horizontal Timing

In a similar way, the CRTC controls vertical timing (Figure 3·8).
In a 60 Hz VRlOO monitor, the Vsync period is 16.667 ms; of this,
approximately 0.7 ms is vertical retrace (vertical blanking) time
and the screen is unblanked for 15.9 ms. With a horizontal scan
line time (Hsync period) of 18.5 us, a total of 901 horizontal
scan lines can be generated during the Vsync period {16.6 ms),
with 864 scan lines displayed during the 15.9 ms verti:al
unblanking time.

In CRTC terminology, vertical timing is programmed in terms of
character row (or character· line) times.
A character row
comprises 16 horizontal scan lines. For the displayed portion of
the vertical scan, the CRTC is programmed for 54 character rows
(864 scan lines). For the total vertical scan, the integer value
of character rows programmed into the CRTC for the VRlOO is 56.
This equates to 896 horizontal scan lines, where 901 need to be
generated.
Therefore, the CRTC is programmed with a vertical
adjust value. This value (less than 16) provides the required
number of scan line times (5 for the VR100) to complete the
16.6 ms vertical scan.

3 - 13

VCBOl FCNCTIONAL DESCRIPTION

+. - >

CHAR
ROWS
1 + •. >

s l
p

I
L I
A
y

TIME

1 - - - - - - - - . - - - - - - - - - - • - - - . - .. - - - - - - - - - ( 18. 5 us)

I
D
I

SCAN
LINES

I
I
I

+·->

16 -----------------····---------------

54 +·-> 849

I
I
I
+ . - > 864 · · · · - · · · · · · · - · - · · · · · - · · - · · - · - - - - · - · ·
+.· . >
+ - - > 55 +. - > 865

( 15. 9 ms \

I
I
I
R

+ •. > 880
56 + • - > 881

T
R
A

I
/

+ .. > 896

+ .• >

897
898
909
900
901 ····················---------------- (16.6 ms)
Figure 3·8:

CRTC Vertical Timing

During the time that the display is blanked, the 462.5 ns video
refresh cycles are used to refresh the video memory RAMs. The
dynamic RAM refresh address is generated by a 4-bit refresh
counter.
Qther timing values programmed in the CRTC include
width, start of sync, and start of display enable.

sync

pulse

The CRTC also contains a video refresh register and cursor start
The refresh register contains the
and end address registers.
address of the the first video memory address to be read at ~hs
The cursor start address register
~nd
~f
vertical blanking.
contains the scan line where the cursor starts; and control bits
3-14

VCBOl FUNCTIONAL DESCRIPTION

to enable the cursor,
which it blinks.
3.5

cause

it to blink, and set the rate at

VIDEO MEMORY

The Video Memory is a 256 kB dual-ported MOS RAM array. It is a
single-plane (or l·plane) bit-mapped memory: that is, the value
(on or off) of each pixel on the screen corresponds to the value
(1 or 0) of only one bit in memory. Each pixel is defined by its
X,Y position in the memory, where Y represents a scan line 1
pixel (bit) high and 1024 pixels (bits) long (X). There are 2048
scan lines in Video Memory (Figure 3-9).
NOTE - Coordinate System
The top, left corner of the screen is X,Y
coordinate 0,0. The bottom, right corner of the
screen is X,Y coordinate 959,863.
Video Memory is dual-ported, giving access to the Q22·bus to
update Video Memory, and to the Scan Line Map to refresh the
monitor screen (video refresh).
The 32 64k x 1 dynamic RAMs (refresh is required) that make-up
the array are arranged in 32-bit words. The byte, word, or
longword
operand
is
specified
by
Q22-bus
BDAL<l7:00>.
BDAL<l7:07> specify one of the 2048 scan lines, and BDAL<06:00>
specify one of the 128 bytes within the scan line.
Individual
bits are controlled by CPU bit operations.
For video refresh, Video Memory is addressed through the Scan
Line Map as an X·Y address space. The Scan Line Map selects any
864 scan line segment of Video Memory, each line having 960
pixels.

VCBOl FUNCTIONAL DESCRIPTION
+ ...... +
; SCAN I
i LINE I
I MAP
I
+-·····+

+----····+
I CURSOR I
RAM
I
+······--+
1024
o
II
2048+ - - - · - · - · - · · · - · - · +
II

I
I

VIDEO MEMORY
+. . . . . . . >

0
960
II
i·····\/·····\ O+---··········+
I
\
VRlOO
I
\
FULL PAGE
I
\
DISPLAY
I
I
I
i - - ... - . - ••.. /8 6 4 + ..•. - - ... ·.... +

0+················+
Figure 3·9:
3.5.1

Display Mapping

Scan Line Map

The Scan Line Map comprises two 2 k x 8 static RAMs (refresh is
not required).
It is configured as a l k X 11 RAM; that is the
MSB (most significant bit) of the address is disabled, and the
five MSBs of the output are not used. It translates the 10 MSBs
of the CRTC Start Address Output (video refresh address) into an
11-bit Video Memory physical address; mapping any 864 of the 2048
Video Memory scan lines to the VRlOO monitor (Figure 3-9, above).
Only the the lower 960 pixels (bits) of the lines are displayed.
If the VCBOl is used in half ·page mode, the Scan Line Map maps
only the lowest 800 pixels of any 480 scan lines to the half-page
monitor (see Table 2-9).
The Scan Line Map is addressed as the upper 2 kB of VCBOl address
space (see Figure 4-3), making these Video Memory addresses
unavailable for storing and refreshing video images.
(Note that
read and write operations to these addresses access both the Scan
Line Map and Video Memory.) Therefore, the 11 LSBs (least
significant bits) of location MSA + 254 k (MSA+260096) are the 11
bits output from the Scan Line Map.
They point to the Video
~emory
address of the first video scan line; MSA + 254 K + 2
001nts to the next scan line, and so on.
3-16

.VCBOl FUNCTIONAL DESCRIPTION

3.5.2
~.

Video Memory · Update Me•ory

As Figure 3-10 shows, Video Me111ory is addressed by eight lines
from the Memory Address Mu~ (multiplexer).
These lines are
multiplexed, 8-bit, row and column addresses. The row and column
addresses are latched in memory at the appropriate time by RAS
and CAS (row address strobe and column address strobe) inputs,
providing a 16-bit memory address.
The Memory
following:

Address

Mux

output,

D4MA07:00,

one

the

(read

0 . video ref re sh column address
1 - video ref re sh row address
2 . update memory column address
3 . update memory row address
selected by the combinations of DllUPDATE and
"not DllCOL").

·DllCOL

Video Memory is updated from the Q22-bus every 925 nsec.
To
update the image in Video Memory, the row address on BDAL<l4:07>
is selected by:
OllUPDATE = HIGH
·DllCOL
= HIGH
and the column address on BDAL<l7:15,06:02>, is selected by:
DllUPDATE = HIGH
·DllCOL
= LOW
The addresses are latched by DllRASO and DllCASO from the
PAL.

timing

The input data (two 16-bit words) on BDAL<lS:OO> is written into
each of the four bytes of the 32-bit memory by four write-enable
signals, Dl2WE03:00, from a 32 X 8 write PROM.
3.5.3

Video Memory ·Video Refresh

Figure 3-11 shows the read-access paths to Video Memory.
To
refresh the monitor screen, the row address on D5CR07:~0 is
selected through Memory Address Mux input 1-DA by:
DllUPDATE == LOW
= HIGH
-DllCOL

3 17

+----+

+---+

i~--::j

I LAT I
I
I

RE;;~~~ MUX

MEMORY
AOR MUX
+----+
I ODA

+-----+
+---+
I REF I
I CTR I
+---+

+----+
I ODA I
I I OA I
I
I
I
I
I lSELI
+----+

I
I JOA
I
I
I
I
I

I
I
I
I CRTC I

I I
I
I
I
I
I
I
I
I
I
I
I
I
+----+

I
MAP
ADDR MUX

i~---+
I

SCAN LINE
MAP RAM

VIUEO
MEMORY
... - - - - +
I OUT 1--0031: 00
--MA07, oo--1 ADR I
I
I
co
I
I
.......

+---+
I
I
I
Q22 \IOC0031--0AL15:00------------------------------------+--ILATl--+--LADR17: 15,06:02--l2DA
I
I
\ BUS /IXCVRSI
I
+---+
I
I
I
I
\---/ +-----+
I
+--LADR14:07--------l3DA
I
I
I
UPDATE---- I 2SEL
I
I
I
COL--1-llSEL
I
I
I
+----...
I
I
+----------------------· -----------------------IDATAI
RASO--IRAS I
CASO--ICAS I
WEOJ:OO--IWR
I
1---\ • - - - - - •

+-- --+

Figure 3-10:

=
0

1-4

u
z
:>

r-t

0
CQ

Video Memory Write (Update)

VCBOl FUNCTIONAL DESCRIPTION

and the column address on D5LMAP10:08
selected through input 0-DA by:

and

05LCADR04:00

DllUPDATE = LOW
-DllCOL
• LOW
The row address is selected through Refresh Mux input 0-DA (this
mux is described in more detail below), and is supplied by the
scan Line Map, on D5MAPDAT07:00. The Scan Line Map also supplies
the three MSBs of the column address, on D5LMAP10:08. The five
LSBs of the column address, D5LCADR04:00, are supplied by the
CRTC. This 16-bit (8 row, 8 column) Video Memory read address is
interpreted as shown in Table 3·4, and described below .

Table 3-4:

Video Referesh Address Derivation

+· ... - - ... - ............ ·+·. - .. - .... - .... - .. - .. - ·+

ROW

COLUMN

+. - . - ... - - . - - - - . - - - - - .. ·+ .. - ...• - - •• - • - - - . - . - - . -+
Memory Address MA_
Memory Address MA_

ADDRESS

+- -+- -+- ·+· ·+· -+- ·+· ·+· -+- -+- -+- -+· ·+· ·+- -+- ·+- -+
\

101 06:os104:031021011001011061os104103102101;00:

+- -+- ·+· ·+· -+· -+- -+· ·+- ·+· ·+- ·+· ·+- -+· ·+· -+- ·+· ·+

Scan Line Map

CRTC

+· - - - - - - - - - - - - - - •.... - - ·+· - - - - .. -+· - - . - ... - - ... ·+
MAPDAT
LMAP_ I
LCADR
I
+-·+--+·-+··+··+·-+--+--+--+--•··+··+··+·-+--+-·+

SOURCE
\

'07 06 05;04 1 03i0210lj00!10!09i08!04J03102!0li00,
+- -+· ·+· ·+· -+- -+- -+- ·+· -+- -+· ·+· -+· ·+· ·+· ·+- -+- ·+

11 bits address 2048 lines
(32 words per line)

!5 bits address:
32 words

+- - - - . - - . - - . - •. - ••••• - - • - • - - - - - - ·+. - ... - - . - - - . - -+

For video refresh, Video Memory represents 2048 scan lines with
1024 pixels per line. Therefore, each line of the video image
requires 32 32-bit words. Because each ~ernory address reads one
32-bit word, 32 addresses are required to read one scan line. To
read a specific line for display, the 11-bit Scan Line Map
output, D5MAPDAT07:00 and D5LMAP10:08, provide the 11 MSBs of the
memory address. Each of the 32 32-bit words in that line are
read by incrementing the 5 LSBs of the memory address, supplied
by the CRTC as D5LCADR04:00.
In the VAXstation I, using che
VRlOO monitor, only 864 of the 2048 lines are displayed, and only
the 960 low-order bits (30 32-bit words) of any scan line are
displayed.
The 30 words correspond to the 30 character times
that the screen is unblanked (Figure 3-7, above).
The Scan Line Map is addressed by the 10 MSBs of the CRTC address
outFut, D5RA03:00 and D5CADR13:08, through Map Address Mux inpuc

3-19

VCB01 FUNCTIONAL DESCRIPTION

o tthis mux is described in more detail below). The CRTC Start
Adjress Register contains the the value of the first address
output by the CRTC; the address is then updated at the CRTC clock
rate (determined by the timing PAL). Timing is such that 864
scan Line Map locations will be addressed during vertical display
time, and 37 addressed during vertical retrace time {see Figure
3-8). The CRTC output address will then be reset to the value of
the Start Address Register, and the process repeated. Continuing
the address update during vertical retrace provides the addresses
needed for dyanmic RAM refresh (described below).
The contents of each Scan Line Map location is the 11 MSBs
Video Memory address.

3.5.4

Video Memocy · RAM Refresh

As figure 3-12 shows, the only difference between the Video
Memory read path (Figure 3-11) and the dynamic RAM refresh path,
is that the row address, D5CR07:00, is supplied by the Refresh
Counter through input 1-DA of the Refresh Mux.
The RAM refresh row address, D4REF07:00, is selected through the
Refresh Mux when DSDE {display enable) from the CRTC is not
asserted. DSDE is de-asserted during horizontal retrace time and
vertical retrace time.
The Refresh Counter is updated during every Video Memory update
cycle {every 925 ns
Figure 3-6, above) when D5DE is not
asserted. Therefore, every video refresh cycle during horizontal
and vertical retrace times is a RAM refresh cycle, and updated
row and column addresses are generated each cycle.
3.5.5

Scan Line Map ·Update

The 864 Video Memory addresses to be read for video
stored in the Scan Line Map (Figure 3-13).

refresh

are

When DllUPDATE is asserted, the Scan Line Map is addressed frcm
the Q22-bus through input 1 of the Map Address Mux. If the the
bit-map memory (Video Memory) is being a~dressed
(D3BMSEL
asserted) and the upper 2 kB is being addressed (BDAL<l7:ll>
asserted), then the buffer is enabled, and write data is gated
through to the Scan Line ;!ap RAM I/0 pins. The write is enabled
to each of the RAMs by Dl2WRSCANHB:LB from the 32 x 8 write PROM.

3-20

(

•

MEMORY

-I
l--LCAOR04:00--+
ADR MU><.
I CAORO<l:til.J----·---- --- ---- - - - - -- - - - - - - - - - --- --MAI'
!>CAM LINE
ILATI
I .. ----+
I
I
MAP RAM
+--MAPOAT10:08--I
I -LMAP10:08---+--IODA I
I•" IL I - -(.A[Jf.; l .~: _.,, . . . AOUI'< Ml))<
+-----+
I
+---•
I
.I
I
I
I +----+
l--MAPADR09:00--IA
<>I--·
REFRESH MUX
I
I
I
t--RAIJJ:i11..- --+ -10

I
I

/---\

+---

+---+
I HEF I

I
+----+
I
+--MAPOAT07:00--IODA l--CR07:00-------I 10A
I JOA I
I

I
I
I
I
I 1 SEL I

ICTRI

+---·

I
I
w ..I _.,.,,._ I
rv

•---+

•-----+

I-' I

Q22 \IDCOOJI

ILATI

BUS /IXCVRSI

+---+

\---/ +-----·

+----•

I
I
I
I_.

VIDEO
MEMORV
+----+
I OUT,--0031:00
l--MA07:00--IADR
I
I
I

I
I
I
I
I
I
I
I 2DA I
I
I
l3DA I
I 2SEL
11 SEL
.. ----•

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
f OATAI
IRAS I
ICAS I
lwR I

+----+

Figure 3-11:

Video Memory Read (Video Refresh)

<
n
ID

....
c:

~
M
0

+----+

+---+

MEMO~Y

l--CAOR04:00---------------------------------------------------I
l--LCAOR04:00--+ AOR MUK
I
I
MAP
SCAN LINE
I LAT I
I +----+
l~RTCl--CAORl3:08--+ AODR MUX
MAP RAM +--MAPOATIO:OS--1
l--LMAP10:08---+--IODA I
I
I
I •----•
+-----+
I
•---+
I
I
I
1--RA03:00----·--IO
l--MAPAOR09:00--IA <>I--·
REFRESH MUX
I
I
I
I
I
I
+-----+
I
+----+
I
I
VIDEO
I
I
+---+
·--MAPDAT07:00--IODA l--CR07:00----I ILJA I
MEMORY
I
I
IREl'l----------REF07:00--l 10A I
I
I
·----+
I
I
ICTRI
I
I
I
I
I ourl--0031 :OO ~
I
I
+---+
I
I
I
l--MA07:00--IAOR
i
1--0E--------------------------------------------------------1-11 SELi
I
I
I
M

•----+

1---\ +-----•
Z1 Q22 \IOC0031

+---+
ILATI

o, BUS /IXCVRSI

•----+

+---+

;: \---/ +-----+

I
I

I
I
l2DA I
I
I
I :3DA I
l2SELI

I !SHI

1-4

•----+

lllll:

I
I

I
I
I
I

I
I
I DATA I
I

IRAS

ICAS I

!WR

... ----+

Figure 3·12:

.....

0
IQ

u
>

Video Memory Read (RAM Refresh)

VCBOl FUNCTIONAL DESCRIPTION

+----+
!CRTCl--CADR13:0a--+

I
I

MAP
ADDR MUX

+----•

1--RA0~:00----+---------------------------------10

·----+
+---+
+------------DALl7:16-----ILATI
I
I
I
I

--\

+-----..

022 \IDC003J--DALl5:00--+--I

,·eus 11xcvRSI
\---1

+-----+

I
I

I
I
I

I
I

SCAN LINE
MAP RAM
+-----+
l--MAPADR09:00--IA <>I--+

l--+--LADRI0:02--•--l1

•---•

INCLADR01--+

I
I

UPDATE--+--llSELI
I +----+

WRSCANHB:LB--IWE

•-----•

BUFFER

•---+

•----•

•---•

+--IANDl---IEN
+--LADR17: 11-----1
I
I
BMSEL-----1
I
I

+-------------DALll:00-----~-------1

Scan Line Map Write (Update)

3·23

I
I
I
I
I

I
I
I
I

I
!----------------•

+----+

Figure 3·13:

I
I

VCBOl FUNCTIONAL DESCRIPTION
3.5.6

Cursor

The cursor is a 16 X 16 pixel image stored in the Cursor RAM
(static RAM). The output of the Cursor RAM is logically combined
with the output of Video Memory, by either ANDing or ORing the
two outputs.
The cursor image is stored by writing to the upper
of the VCBOl address space (MSA + 256 k - 16).

locations

The cursor can be positioned at any point on the screen, within
the limits of the coordinate system. The cursor origin is its
top, left corner; its minimum X,Y position is 0,0 and its maximum
X,Y position is 943,847. The cursor Y position is determined by
the contents of the CRTC Cursor Start, End, and
Address
Registers; its X position is stored in the Cursor x Position
register.
3.5.7

Cursor RAM· Write

Refer to Figure 3-14. When the top 16 locations (BDAL<l7:05>
asserted) of bit-map memory are addressed (D3BMSEL asserted)
during an update cycle (DllUPDATE asserted), the 16 Cursor RAM
locations are addressed by BDAL<04:01> through input 0 of the
Cursor Address Mux.
The data (cursor image) on BDAL<l5:00> is written into the
when Dl2WRCURSHB:LB are asserted by the 32 X 8 write PROM.
3.5.8

RAM

Cursor RAM ·Read

To read the Cursor RAM and display the cursor image, the RAM is
addressed by a 4·bit address counter through input 1 of the
Cursor Address
Mux.
The
counter
is
enabled
{through
combinational logic) by the CURS and HSYNC outputs of the CRTC.

3·24

:VCBOl FUNCTIONAL DESCRIPTION

' '--

CURSOR
ADR CTR
CURSOR
+---+
CURSOR
RAM
·-----· I
!-----------------------------+ ADR MUX
+----+
I LF<TC I - -H~'tNC-- I CUMB 1--1 EN I
+--------------------------1-------------1 D
I
I
1--CURS---ILOGICI +---+ I
I +----+
I
l--CURS15:00
·----+
+-----+
I
•--11
I
I
I
I +---+
I
1-----IA
I
·------------DAL17:16-------l--ILATl--LADR04:01-----------IO
I
I
I
I
I I
I
+---•
I
I
I
I
1 ---\
+-----·
I I
l--LADR17:05--IANDl--l-l1SELI
I
I
I
Q~2 \IDC0031--DAL15:00-------+--I
I BMSEL------1
I
+----+
I
I
' ~us 11xcvRsl
+---+ UPDATE-----1
I WRCURSHB:LB--lwR I
\---/ +-----+
+----·

·---+

Figure 3·14z

Cursor RAM Read/Write

3-25

VCB01 FUNCTIONAL DESCRIPTION

3.6

MOUSE

The mouse position logic comprises
flip-flops
driven
by
commutator
brushes
(Figure
3-15)
and push-but~ons.
The
flip-flops provide signal-settling (de-bouncing)
and
pulse
shaping, and generate square-wave outputs.
The square-wave
leading edges are counted, giving an effective resolution of 100
counts per 2.54cm (1 in).
COMMUTATOR

f
BRUSHES - - -

Figure 3·15:

Mouse Construction

The X and Y commutators each provide a distance signal (DlSCLKlB
and DlSCLKlA) and a direction signal (Dl5CLK2B and Dl5CLK2A),
which control the clock and count direction of X and Y counters
(Figure 3-16). The mouse push-buttons are input to the Interrupt
Controller and CSR.
Mouse direction is determined by the direction of the count; that
is, up or down.
The direction of count is determined by the
phase relationship between the distance and direction outputs.
When the Mouse is moved in one direction, the distance output
leads the direction output; Mouse travel in the
opposite
direction
reverses
the
phase
relationship.
This phase
relationship is a result of commutator construction.
Another characteristic of mouse constructicn is that the period,
and therefore, the number of square-wave edges-per-inch, varies
with direction of travel. For example, if the Mouse is moved in
an exact vertical ~irection, the Y-axis would output the maximum
number of edges-per-inch, indicating the maximum rate-of-change;
the x-axis output would be flat, indicating no rate-of-change.
3-26

VCBOl FURCTIORAL DBSCltIPTION
If the Mouse is moved in a direction that is halfway between
vertical and horizontal, both the X·axis and Y·axis will output
the same number of edges·per·inch.
Each time the Mouse is moved, an interrupt request is generated
(OlSMOUSECTINT). The accumulated X and Y count is transferred to
BOAL<l5:00> through the X and Y registers as a result of a bus
OATI function (03INWD).
Normally, this occurs during vertical
sync time; 'that. is, every 16.6 ms.
The distance the Mouse
traveled in that time is proportional to the change in the
accumulated count.
3.7

KEYBOARD

The Keyboard is driven by an 8051 microprocessor, and contains a
set of microdiagnostics. The keyboard logic detects and encodes
keystrokes, and transmits the ·nformation to the OUART (Figure
3-17).
The programmable DUART serializes/deserializes parallel
bus data (BDAL<07:00>), implements the EIA RS423 interface, and
generates an interrupt request (Ol4COMINT) to the Interrupt
Controller.
The internal OUART registers are described in
Chapter 4.
An on-board 3.6864 MHz oscillator supplies the
baud-.rate clock input to the DUART.

3·27

)

+-----+

...
H

Ile

pi:

u
Q

X CTR

X REG

+----+

T----+

MOuSEl--CLKlB--IF!Fl--+----ICLK 1----------------------------------------------1
l--OALU7:00---+
I
+---+ I
I
I
+--------------------ICLK I
I
l--CLK2B---------l----loowNI
I
+--IEN I
I
I
I
+----+
I
I +----+
I
I
I
v CTR
I
I v REG
I
I
+---+ I
+----+
I
I +----+
I
l--CLKlA--IF/Fl--1-+--ICLK 1-------------------------1-----------------1--1
l--uAL15:08---+
I
+---+ I I I
I
+-----------------1--1 CLK I
I
l--CLK2A---------l-1--IDOWNI
I
+--IEN I
I
I
I I +----+
I
I +----..I
I
I I +-----+
+------+ I
I
I
I
I +--ICOMB l--MOUSECTINT--l!RQ2 I I
+-----+ I
I
I
+----ILOGICI
I
R!Pl--1---vEC--ICOMH 1--+
I
I
+-----+
I
I +---------ILOGICI
I
l--MSWA:C--+-------------------------------l!RQ4:6I I +------1
I
I
-----+
I
+-------+
-.-------... I I +----1
I
I
I
I DC004 1-------------!NWO--+ I I +--1
1--+
I
I
IREG SELl------------MODSEL--+ I I .------+ I
I
I
+-------+ +-------+
I I
I
CSR
I
I
IREG SELl--MOUSESEL--+ I
I
(OUT)
I
I
I PROM 1--CSRSEL------+
I +-----+
I
I
+-------+
+--IEN
I
I
+----------------------------------------------------·---------ID
Rl--DAL08: 1U--+

Ul
l'l:i

+---+

/---\ +----- ...

022 \l~C0031--DAL15:00--------------------------------------------------\BUS 11xcvRSI
\---/ +-----+

II(

...u

z
0

(I.,

)

Figure 3-16:

Mouse Interface

+-----...

----------------------.-

co
N

VCBOl FUNCTIONAL DISCRIPTION

+----------------------------------------------------------+
DUART
I
I •--------•
•------• I
··-IKEveoARDl------------------------------------,Rx Txl--•

•--------•

I
1--------------INWO------RD
I
IREG SELl--------------OUTLB------fWR
I
•--------•
•-------+
I
I
13.6& M~zl------------------------------------1•RCLK I

I osc
I
+--------+

1---\ •-----•

•-------•
1 DCD04

9519A
INT CONT
•-----•
<>1·-+
·-------•
INTRN --coMINT-- rRoo
I
!REG SELl--------------UARTSEL----l!N
I
I
I PROM I
+---+
I
<> 1--+
I
+-------+ +--ILATl----LADR04:01--IADR
I I
I
I +---•
+------+
I
I
I
XCVRS
I
I

•-----•

, U22 \IDCOC3i··DAL15:00--+--IB

' eus 11xcvRSI

\---/ +-----+

euFEN--------IEN

+-----+

Al--8007:00--------------+----------------+

...... ----+

Figure 3·17:

Keyboard Interface

3·29

VCB01 FUNCTIONAL DESCRIPTION
3.8

MONITOR

The VRlOO Monitor uses a 48.3 cm (19 in, diagonal) monochrome
CRT.
The screen display dimensions are 354.3 mm (13.95 in)
horizontal and 281.4 mm (11.08 in) vertical, with an aspect ratio
of 1.26:1.
The Monitor has a self contained power supply, and
requires a line input of 120/240 Vac 50/60 Hz at 100 w.
The Monitor has two external controls: contrast and brightness.
Other controls and adjustments, located within the monitor
enclosure, are:
0
0
0
0
0
0

Horizontal centering and vertical centering
Horizontal linearity and vertical linearity
Horizontal width and vertical height
Horizontal frequency and vertical hold
Hori"zontal dynamic focus and vertical dynamic focus
Static focus
NOTE - Monitor Alignment
Normally the Monitor does not have to be aligned;
however, alignment may be required as a result of
FRU replacement. The adjustments are described
in Chapter 5, and in the Pocket Service Guide.

The Monitor has five major subassemblies (Figure 3-18):
1.
2.
3.
4.
5.
3.8.1

Power supply
Deflection module
Video module
Flyback assembly
CRT/Yoke/Bezel assembly
Monitor Power Supply

Ac power is input to the Power Supply through an input line
filter.
The Power Supply outputs regulated 52 Vdc (B+ voltage),
distributed throughout the Monitor. The Power Supply can operate
from either 120 vac or 240 ~ac line input. The input rectifier
operates as a full-wave doubler when 120 vac is input, and as a
full-wave rectifier when 240 Vac is input; providing the same
rectified voltage to the regulation and protection circuits for
either ac input.

3-30

VCBOl FUNCTIONAL DESCRIPTION

OEFLEC ION BOARD

r------------,
I

VIDEO BOARD

BRIGHTNESS - - CONTROL

r - - - - - ----,
I
I I
I VIDEO
I II
INPUT
VIDEO
TO CRT
AMP
I SYNC
VERT
I I
VERT SYNC
LED
1--1111 DRIVERS 1 1 - - - - - 1 -........
HORIZ
HORIZ SYNC
SYNC
I

POWER
I
VIDEO
I
VERT SYNC
L __

STATIC AND
DYNAMIC
FOCUS

CRT

FROM
VIDEO
AMP

1 I

I I
I I

H~~~--~L

HORIZONTAL
TIMING

HORIZONTAL
OUTPUT

______ _

r----1
120/240 v AC
INPUT

DEFLECTION
COIL

LEDS

VERTICAL
OUTPUT

VERTICAL
PROCESSING

r--

I POWER I
I SUPPL y i--l-+-S2_V_D.C
L - - _ __J REGULATED

---,

ANODE
VOLTAGE

Aux. LOW
VOLTAGE PWR

FLVBACI<

18 KV

IL ____ _JI
FLYBACK ASSEMBLY

Figure 3·18:

Monitor Functional Block Diagram

The B+ voltage is monitored by an over-voltage circuit that
reduces the power supply output if B+ exceeds +SS Vdc. An
overcurrent circuit protects the Monitor by reducing B+ if
current exceeds 1.2 A.

3.8.2

Video Module Description

The Video Module contains the main video amplifier and circuits
that drive four monitoring LEDs. The video input signal from the
DPM is supplied through a BNC connector on the Monitor's rear
panel.
The positive TTL video input has an amplitude of 400 mv
to 800 mv.
The main components of the module are a
3 - 31

prea~plifier,

optical

VCBOl FUNCTIONAL DESCRIPTION

coupler,

and

several

stages of video amplification (see Figure

3-19).
CONTRAST CONTROL • RIS38

+voe
BIAS
r---9<: ADJUSTMENT

OPTOCOUPLER

R609
CATHODE
VIDEO
INPUT_....,.

VIDEO
AMPLIFIER
STAGES

PRE·
AMPLIFIER

CRT
VIDEO
HORIZONTAL SYNC
VERTICAL SYNC

LED DRIVERS
ANO
INDICATORS

POWER SUPPLY
... llltK!

Figure 3·19:

Video Module Block Diagram

Video input is applied to the preamplifier. Preamplifier gain is
controlled by the light-variable resistance of the optical
coupler. The contrast control, R636, controls the emitted light
level of the optical coupler's LED. The optical coupler's output
resistance varies with the LED's emitted light level.
The
preamplifier's gain varies with the output resistance of the
optical coupler. Because of the optical coupler, the contrast
sontrol is mounted on the Monitor's rear panel rather than on the
Video Module.
Preamplifier output is coupled through several stages of video
amplification to the CRT cathode, and controls beam current. The
bias adjustment, R609, controls the quiescent level of the video
amplifiers which supply the drive voltage for the CRT cathode.
It is set to a level that corresponds to the CRT screen blac:
level.
The monitoring LEDs are mounted on the Video Module and
through the Monitor's rear panel.

protrude

Eacn monitor input signal and power supply output IB+J is sampled
3P.d input to a set of LED drivers.
The LEDs are normally
lighted, indicating a no-fault condition (see Table 5-10).
If

VCBOl FUNCTIONAL DESCRIPTION

any
sampled input is less than a
corresponding LED is turned-off. Table
thresholds.

Table 3·5:

failure threshold, the
3-5 lists the failure

Failure Thresholds

····-····-·-···-+--·-····-·

INPUT
.SIGNAL

I FAILURE

Video

>300

Horizontal Sync

>2.2 v

Vertical Sync

>2.2 v

B+

>48 Vdc

I THRESHOLD
• • - - • • • • • • • - • • • •+• - - - • • • • • -

3.8.3

Deflection Module

The Deflection Module contains the following major CRT circuits:
o
o
o
o

Horizontal deflection
Vertical deflection
Static and dynamic focus
Vertical blanking control

3.8.3.l Vertical Deflection · The Vertical Deflection circuit
comprises
a
pulse
generator, ramp generator, and output
deflection amplifier (Figure 3·20).
The Vertical Sync signal
from the DPM is input to the pulse generator through a BNC
connector on the Monitor's rear panel.
The ramp generator charges its output capacitor, producing a
voltage that increases at a linear rate. The positive pulse
output of the pulse generator causes the ramp generator to
rapidly discharge the output capacitor; producing a sawtooth
waveform. The Vertical Sync input drives, or synchronizes, the
pulse generator.
Note that the linear portion of the sawtooth
(capacitor charge) corresponds to the 60 Hz ~ertical sweep
frequency.
The
waveform
fall time (capacitor discharge)
corresponds to vertical blanking and retrace time.

3. 3 3

VCBOl FUNCTIONAL DESCRIPTION

VERTICAL
SYNC
INPUT

PULSE
GENERATOR

RAMP
GENERATOR

OUTPUT
AMPLIFIER

LINEARITY
ANO SIZE
CONTROLS

CAPACITOR CHARGE
CORRESPONDS TO
VERTICAL SWEEP
FREQUENCY
111a.tttU

Figure 3·20:

Vertical Deflection Block Diagram

The sawtooth is input to the output amplifier.
The amplifier
comprises a drive stage and a complementary output stage. The
output stage provides positive and negative current to the
vertical deflection coils.

3.8.3.2 Horizontal
Deflection - The
horizontal
Deflection
circuit
consists of a monostable oscillator, free running
oscillator, output amplifier, flyback transformer, and deflection
coils {Figure 3-21).

3. 34

VCBOl FUNCTIONAL DESCRIPTION

HORIZONTAL
SYNC
INPUT

MONOSTABLE
OSCILLATOR

FREE RUNNING
OSCILLATOR

FOCUS AND
LINEARITY
CONTROLS

OUTPUT
AMPLIFIER

17.5 KV

..,__..., [

TO CRT
ANODE

L--""'.......,"'- HORIZONTAL
DEFLECTION
""--~.J...JUT COILS

Ml·llMt

Fiqure 3·21:

Horizontal Deflection Block Diaqram

The Horizontal Sync signal from the VCBOl is input to the
monostable oscillator through a BNC connector on the Monitor's
rear panel. The sync signal causes a positive pulse output from
the monostable oscillator.
This pulse synchronizes the free
running oscillator. The free running oscillator output is fed
through an amplifier and shaping circuit, producing a rectangular
waveform that drives the output amplifier. The output amplifier
supplies the horizontal deflection coil current.
When the
amplifier is switched on, a linear increase (sawtooth) in current
through the deflection coils drives the beam across the CRT
screen.
When the amplifier is switched off, the
current
reverses, and the beam is returned and blanked.
when the amplifier is switched off, the resulting voltage pulse
is applied to the primary of the flyback transformer. In the
transformer's secondary the pulse is stepped-up to 17.S kV,
(ectified, and applied to the CRT anode.
3.35

VCBOl FUNCTIONAL DESCRIPTION

3.8.3.3 Focus And Linearity control · CRT image
focus
is
controlled by a bias voltage applied to the CRT focus grid. The
static focus control, R431, controls beam focus at the center of
the CRT screen. However, as the beam is deflected away from the
CRT's center (both horizontally and vertically), greater focusing
bias voltage is required. The dynamic focus circuit supplies the
needed additional bias voltage.
This circuit samples
the
horizontal and vertical deflection voltages, and increases focus
grid bias by a proportional amount. The horizontal component is
controlled by the horizontal dynamic focus control, R418, and the
vertical component is controlled by the vertical dynamic focus
control, R416.
Because of deflection coils losses, the current waveform is
distorted {that is, non-linear), resulting in a stretched image
on the left side of the CRT. The variable linearity coil, L232,
is adjusted to compensate for this distortion. In addition, the
width coil, L23i, controls the raster width.
3.8.3.4 Blanking Control · The Vertical Blanking and Spot-killer
circuit provides blanking during vertical retrace time, and
protects the CRT's phosphor coating.
Display image brightness is controlled by a bias voltage applied
to the CRT's control grid. This bias voltage controls the beam
current and is developed through the brightness control, R636,
and its associated voltage divider network. The bias voltage is
set·up to allow the CRT to conduct during horizontal scan.
During vertical retrace time, the vertical amplifier generates a
large negative output that input to the control grid bias
network.
This negative voltage drives the CRT into cutoff,
reducing beam current to zero. The grid bias network also senses
any loss of horizontal deflection output, driving the CRT into
cutoff to protect the phosphor.
3.8.4

Field Replaceable Units

The Video Module, Deflection Module, and Power Supply are FRUs.
(The CRT/yoke/bezel and the flyback assemblies are not FRUs, and
are considered to be too dangerous to replace on site. They are
returned in the Monitor enclosure when replacement is required.)
The cable connecting the CRT to the Video and Deflection Modules
contains components, such as resistors and capacitors, which car
fail; therefore, the cable assembly is also an FRU.
Replacement of some FRUs can result in a need for Monitor
alignment.
The adjustments are described in Chapter S, and in
the Pocket Service Guide.
3-36

VCBOl FUNCTIONAL DESCRIPTION

3.9

POWER SUPPLY

The VAXstation I uses a standard H7865 power supply to convert
the ac line voltage to de. The Power Supply provides +S.O Vdc,
+12.0 Vdc, and ·12.0 Vdc outputs; and status signals which
indicate that the de outputs have reached their operating levels.
The Power Supply includes logic to monitor voltage input and
output, and protect the system from incorrect levels. Table 3-6
lists the thresholds.
Table 3·6:

Voltage and Current Protection Thresholds

•••• - . - •.. + .•••••. - - . •, .• - + - • - • - - • - - ••••

OUTPUT

' OVER VOLTAGE I OVER CURRENT
; THRESHOLD
! THRESHOLD

- . . . . . . . • . +. . • . • . . . • . . . . •+. . • . . . • . - - . . •

+5.6 Vdc

+7.0 Vdc

21 to 29 A

+12.0 Vdc

+14.5 Vdc

11 to 15 A

·12.0 Vdc

·14.0 Vdc

l. 5 to 2. 5 A

WARNING - Input Power
The power supply has a 120/240 Vac select switch
that must be set to match the ac line input.
WARNING - Power Supply Capacitors
The input capacitors retain their charge for S
minutes after system power is removed. Before
removing the power supply cover, turn-off the
power and wait 5 minutes.

3. 3 7

CHAPTER 4
PROGRAMMING INFORMATION

This chapter describes the programmable functions of the VCBOl;
that is, the func:ions that can be specified and/or examined by
software.
4.1

ADDRESS SPACE

The MicroVAX architecture specifies a l GB (gigabyte) physical
address space, divided into a Memory Space and I/0 Space (Figure
4. l ) •
+. • • • • • . • . • . • . • • • • • . • • • . . • • - • - • • • • • - • • • • • • - . . . . . • • . • • . . +

3FFFFFFF

I/0 SPACE

20000000
+-. . . . • . - . . . . . . . . •. . . . • . . . . . . . . . . • • . . • • • . - - - . . . . . . . . . . .+

MEMORY SPACE

lFFFFFFF

00000000
+•• • • - . • • • . . • • . • • - • •- • • ••- • • • - - • • - •• • • • • • • • • • . . • • . • • . . .+

Figure 4·1:

MicroVAX Physical Address Space

in the MicroVAX, address bit <29> selects either the Memory Space
or I/O space; bit <28> is a no-cache indicator; bits <27:22> are
ignored; and bits <21:00> select a location within Memory Space
·n I/0 Space.

In :he VAXstation I,

the VCBOl resides
4. 1

the

Q22-bus

address

PROGRAMMING INFORMATION

space; in the highest 256 kB of Memory Space that is addressable
by BDAL<21:00>. Figure 4·2 shows the location on the VCBOl Video
Memory in the VAXstation I physical address space. The MSA
(Memory Starting Address) of the 256 kB VCBOl block is switch
selectable (see Chapter 2, subsection 2.6.1.1).
+- ••• - •. - - - .••. - - •• - . - .. - - - •.. - • - . - •.•• - ..... - •• - - - - •. ·+

3FFFFFFF
(unused)
20002000

+········-···-·········································+

20001FFF !

Q22·BUS I/0 SPACE
20000000

+. -...... - - - .. -.. -......... -...... - ...... - ... - .... - - - - -+

lFFFFFFF
(unused)
00400000
+· - . - - . - - - - - - - . - - - .............. - . - ... - . - - - .. - - . - . - .. - ·+

003FFFFF
VCBOl VIDEO MEMORY
003COOOO
+- - - - - - • • . • . - • • • • • • • • • • • • • - • • - • - • • • • - - - - • - • • - • - - • - • - • - •+

MEMORY SPACE BEYOND INSTALLED MEMORY
+· ......... - .... - - - . - - - - - .. - - .. - ... - .•.•.... - ..... - .. - ·+

INSTALLED MEMORY
00000000
+- - • - . - - - - . - - . . . - - - • • - - - - - - - - - • • • • - • • • • • • - - • - - - • - . • - - - -+

Figure 4·2:

VAXstation I Physical Address Space

The 256 kB VCBOl address space comprises the three segments shown
in Figure 4-3. The Scan Line Map RAM overlays the upper 2 kB of
the 256 kB bit-mapped RAM; and the Cursor RAM overlays the upper
32 bytes of the Scan Line Map RAM. As described in chapter 3,
these are all separate RAMs, not part of the same RAM.

4-2

PROGJUUCMIRG IRFORMATIOH
+ • • • • • • - - • • • • • • • - • • • • • • • .. • • • - • • • • • - • - - • • • • - • • • - .. - • - • +

MSA+262143
MSA+262112

CURSOR RAM
(32 BYTES}

+·······-·-········· . - - ... - .......... - ...•. - •.•. - .. - • ·+

MSA+262111 I
I
I
MSA+260096 I

SCAN LINE MAP RAM
(2 kB less 32 BYTES)

I
I

........................................................... +

MSA+260095
i

I
l

BIT·MAPPEO RAM
(256 kB less 2 kB)

I
I

MSA+OOOOOO

+- - . - . - • • - • • . • • . • • • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • - . • . +

Figure 4·3:
4.2

I
I

VCBOl 256 kB Address Space

VCBOl REGISTERS

Control and Status information is exchanged between the VCBOl and
the CPU through 32 16·bit locations in the I/0 Page. These
locations are listed in Table 4·1 and described below.
NOTE - Bit Descriptions

Many of the bit descriptions in the following
tables
include a value in parenthesis; for
example:
(1 =chip
armed).
This
usually
indicates the initialized value of the bit.

4. 3

PROGRAMMING INFORMATION
Table 4·1:

VCBOl Reqisters

+- - - - . - - - -+- - - .. - .... - - . - - - - . - - - - ...... - . - ..•.. - . - - - - - - - • - . - - - - ·+
i ADDRBSS*I NAME
I
+-. - . - - - . -+- - - - - . - - - - • - - • - - .•. - - •. - - - • - - - - • - - - . - - . - .. - • - - - ..• - - ·+
BASE
CSR ·- Control and Status Register
BASE+2
Cursor X Position
BASE+4
Mouse Position Register
BASE+6
(spare)
BASE+8
CRTC Address Pointer Register
BASE+lO
CRTC Data Register
BASE+l2
ICDR
Interrupt Controller Data Register
BASE+l4
ICSR
Interrupt Controller Command/Status Register
BASE+l6
(spare)
through
BASE+3l
(spare)
BASE+32
UART Mode Registers lA and 2A
BASE+34
UART s·tatus/Clock Select Register A
8ASE+36
UART Command Register A
BASE+38
UART Transmit/Receive Buffer A
BASE+40
(spare)
BASE+42
UART Interrupt Status/Mask Register
BASE+44
(spare)
BASE+46
(spare)
BASE+48
UART Mode Registers lB and 2B
BASE+ SO
UART Status/Clock Select Register B
BASE+52
UART Command Register B
BASE+54
UART Transmit/Receive Buffer B
BASE+S6
(spare)
through
BASE+62
(spare)
+ . . . . . - - . - +- - . - - . - . - . . . . . . - . . . . - . - . - - - - - - . . - . - - . . - - - - - . . . . - - - - - . +
* BASE= The CSR Base Address (Chapter 2, subsection 2.6.1.2).
4.2.l

Control And status Register

The CSR bits are described in Figure 4-4 and Table 4-2.
Note
that following a Q22·bus BINIT, bits <06:02> are cleared (= 0}.
15 14 13 12 11 10 09 08 07 06 OS 04 03 02 01 00
+·. ·+·. ·+·. ·+-. ·+·. ·+· - -+-. -+·. -+- - -+-. ·+· - ·+· - -+·. -+-. -+- - -+· - ·+
nu BK3 BK2 BKl,BK01MSCiMSBIMSA!CUR!IEN;TST:VRB·FNC VID nu MOD
+· - -+- - -+· - ·+·. ·+-. ·+· - -+· - -+-. -+- - ·+·. -+· - ·+· - ·+·. -+- - ·+- - ·+·. ·+
~DDRESS = CSR BASE
Figure 4·4:

CSR Format

4. 4

PROGRAMMING INFORMATION

Table

4-~z

CSR Bits

+·-·-····+········+··········· ··································+
I BITS

I ACCESS I DESCRIPTiuN

+········+········+·············································+
<15>

(spare • not used)

<14:11>

READ

Memory bank switch 0:3 (MSA switch El4 51:54)

<10:09>

READ

Mouse switch C:A (0 • closed)

<07>

READ

Cursor active (1 • cursor on)

<06>

RD/WR

Interrupt Enable (1 • enabled)

<05>

RO/WR

Test Bit (used with loop-back connector)

<04>

RO/WR

Enable video read-back (1 • enabled)

<03>

RD/WR

Cursor function (1 • OR, 0 • AND)

<02>

RD/WR

Enable video output (1 • enabled)
(spare · not used)

<01>
<00>

READ

19 in / 15 in mode (1 • 19 in)

+········+········+·-·-·········································+
4.2.2 Cursor x Position
This location contains the horizontal position of the top left
corner of the 16 x 16 (pixel) cursor image. The value is in
pixels and must not allow the cursor to be positioned beyond the
maximum X pixel.
That is, the maximum value is 943 (959 · 16)
for a VRlOO monitor, and 783 (799 · 16) for a 38 cm (15 in)
monitor.
10

+ • - - • • . • • • • • • - - • - - - . - • • •+ . . . . . . . . - . - . . . . . . . . . - . . . • - . . . . . - - - . . - . . +

CURSOR x POSITION

not used

+• . . • • . . . • . • • . . • • . - . - . . . +. - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . - - . -+

ADDRESS

= CSR BASE + 2
Figure 4·5:

Cursor X Position Format

4-5

PROGRAMMING INFORMATION
Table 4·3:

Curso' X Position Bits

+- ••.•.• ·+· •. - - - - ·+- .. - - ..... - ... - - . - - . - - - - - - . - - .. - .• - - - - - - . - - - ·+
BITS
i ACCESS i DESCRIPTION

+· ...... ·+· - ..•.• ·+· ..• - ..•..• - . - • - . - - - - - - - - - .•• - - ......... - - - - ·+

<15:10>
<09:00>

(not used)
WRITE

Cursor X position in pixels.

+ • • • • • • - - +. . - . . • . . +- - - . - - . • . - . . . . • . • - - - - . - - • • . . • - - . . . . • . . - - - - - - . +

4.2.3

Mouse Position Register

This register contains mouse X and Y position values. The values
are counted up or down, in proportion to the direction and amount
of mouse movement.

+. . - - . . . - - . . - . . . - . . . - - - . . . - - - . . .+. - - - . -• • - - • - - - - - •- • - - - • •. . . . . . .+

Y COUNT

X COUNT

+····-----···········-··········+·-················-············+

ADDRESS = CSR BASE + 4
Figure 4-6:

Mouse Position Register Format

Table 4·4:

Mouse Position Register Bits

+ • • • • • • • •+ • . • • • • • •+. - - - . - - - . . . . . . . . . . . . . . • • • . . - . . . • . . . . . . - . . . . . . +

BITS

ACCESS

DESCRIPTION

+. . - - - . - -+ . . . . . . - -+ . . . - • . - . . - - . • . - . . . . - • • - . . - - - . • • • . - . . . . • . . . . . -+

<15:03>

READ

Mouse Y position count.

<07:00>

READ

Mouse X position count.

+. . . . . - . . + . . • . • . . •+. . . . . . • • • . • . - . . - • • . • . - . • • • • • . • . - • • • • • . • . • • . • • +

4.2.4

CRTC Registers

4.2.4.l CRTC Address Register Pointer · This register points to
the one of 17 internal CRTC registers (Table 4-6), that is to
receive the data contained in the CRTC Data Register (described
below). It also contains three status bits (Figure 4-7 and Table
1. s i .

4-6

PROGRAMMING INFORMATION
03

+·······························+···+···+···+····--·--··········+
!

not used

(USTILPFIVBLI REGISTER ADDRESS
·+·. ·+-. ·+·. -. --............. ·+

+· "" ...• - .......................... ·+·.
ADDRESS • CSR BASE + 8

Fiqure 4·7:

CRTC Address Register Pointer Format

Table 4·5:

CRTC Address Register Pointer Bits

+· ...... ·+· ...... ·+· .......... - ....... - - -.. -.. --. -... -.... -....' ·+
I BITS

I ACCESS

DESCRIPTION

+········+·· . ·····+···-··········-······························+
(not used)

<15:08>

<07>

READ

Update strobe (not used)

<06>

READ

Light pen register full (1 • full)

<05>

READ

Vertical blank (1 • Vblank time)

<04:00>

WRITE

CRTC internal register address (Table 4·6)

+• - . . • . - -+ - - . . . • . •+ • • - - - - . • - • • • • • . • • • • - - - • • • • • • • • • • • • • • • • • • • • • • •+
·."----

Table 4·6:

CRTC Internal Registers

+. • . + . . • . . • . . . . . . . . - . • • - - • . • •+ • • • • • • • • • • • • • • • • • • • • • • - • • • • • • • • • • •+

REG, NAME

i DESCRIPTION

+-··+·······-················+·······························-·-+
00

Horizontal Total

Horizontal Displayed

Hsync Positon

Hsync/Vsync Widths

Vertical Total

Vertical Total Adjust

Vertical Displayed

I/sync Position

The total number of
character
times in a line, minus 1.
The total number of
displayed
characters in a line.
Defines the number of character
times
until
Hsync (horizontal
sync) .
Four bits each are used to define
the Hsync pulse width and the
Vsync (vertical sync). pulse width.
Total number of character rows on
the screen, minus 1.
The number of scan
lines
to
complete the screen.
The number of
character
rows
displayed.
Number of character rows until
Vsync.
4.7

PROGRAMMING INFORMATION

Table 4·5:

CRTC Internal Registers (continued)

+·. ·+· ..... - - - - .. - .•. - - - - - . - -+- - • - - - - - - - • - - - - - - • - - • - •••••••• - • - ·+

I DESCRIPTION

iREGI NAME

+·. ·+· - .. - .......... - . - .• - - . -+· ...• - - ... - ••• - •• - •••••.••.•• - •.. ·+

Mode

Maximum Scan Line

Cursor Scan Start

Cursor Scan End

Controls addressing,
interlace,
and cursor.
The number of scan lines in a
character row, minus 1.
Defines the scan line at which the
cursor starts.
Defines where the cursor ends.

Start Address High
Start Address ·Low

Defines the RAM location where
video refresh begins.

Cursor Address High
Cursor Address Low

Defines the cursor position in
RAM.

Light Pen Position High

Contains the position of the

13
14

17 Light Pen Position Low
light pen.
+·. ·+· " ... " ... - .... - - ....... ·+- ... - . - - - - .... - .. - .... - - - - - ...... -+

4.2.4.2 CRTC Data Register - This register contains the eight
bits of data to be loaded into the internal CRTC register
addressed by bits <04:00> of the CRTC Address Pointer Register
(above).
08

+· .. - - - . - ...................... ·+· .. - - - - ... - ..... - ............. ·+
not used

DATA

+. . . • • • . . • • " . . - - • . - - . • . . • . . . - • - •+. - • . . . - . . . . • . . . - . . . . . - - . . . - . . . . +
ADDRESS : CSR BASE + 10

Figure 4·8:

CRTC Data Register Format

Table 4·7:

CRTC Data Register Bits

+·····-··+········+·············································+
BITS

, ACCESS

DESCRIPTION

+ . . - . . . . -+ - - . . . - . . + • . . . . . . • . . • • . . . . • . . . . . • . • . - . • . . • . . . . . . . . . . . . . +

<15:08>
<07:08>

(not used)
RD/WR
/

CRTC internal register data

+········+········+····················-························+

4• 8

PROGRAMMING INFORMATION

4. 2. S

Interrupt Controller Re<;isters

using a set of internal reg:sters, the Interrupt Controller
handles eight interrupt requ1sts on priority levels 0 (highest)
to 7 (lowest):
0
1
2
3
4
5
6
7

DUART
Vertical Sync
Mouse
Cursor Start
Mouse Button A
Mouse Button B
Mouse Button c
(spare)

A vector for each request level is stored in an internal 8 x 32
response memory.
The Response Memory cannot be read and is
unaffected by a RESET command.
The internal registers are accessed through the ICSR (Interrupt
ICDR
(Interrupt
Controller
Command/Status
Register)
and
Controller Data Register). The registers are described in the
following subsections.
4.2.5.1 ICDR · The Interrupt Controller Data Register contains
the data for/from the internal Interrupt Controller register
addressed by the last Preselect command (see ICSR, below).
08

+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -+. . . . . . . . . . - . . . . . . . . . . . . . . . . . . . . +

not used

DATA

+ .. - . - - . - ...... - ............... ·+· - ........ " ........ - . - ........ ·+
ADDRESS = CSR BASE + 12

Figure 4·9:

ICDR Format

Table 4·8:

ICDR Bi ts

+- . . . . . . •+ . . • . • • . •+. . . . . . • . . . • . . • . . . • . • • . • • • . • . . . . • - - • • . • . . . . . . •+

BITS

ACCESS : DESCRIPTION

+- - - - - - - -+·. - - - - . ·+- - . - - - - . - ... - . - .. - ...... - ..... - - .. - .. - - . - - . - -+

<15:08>
<07:08>

(not used)
RD/WR

Interrupt Controller internal register data

+ - . - • - - - -+ - . - . - - . -+ - - - - . - - . • • • - . • . - • • . . . . • - . - . • . - . - - - . - - . . - - - - . -+

4-9

PROGRAMMING INFORMATION

4.2.5.2 ICSR - The internal· Interrupt Controller registers are
accessed through the ICDR (above) and the ICSR (Interrupt
controller Command/Status Register).
The ICSR is a command
register on write operations and a status register on read
operations.

+- - - - - - - - - - - - - - -- .. - . - - - . -.. - - - -+- - ·+·. ·+·. ·+·. ·+·. ·+· ...... - .. ·+
!

not used

jGRijENA!PRMIINMIMMSIIRR VECTOR '.

+· - . - - .... - . - ... - ... - ...... - .. - ·+· - -+·. ·+· - ·+·. ·+·. ·+· ... - ..... ·+

WRITE:
15

+• • • • • • • • • • • - • • • • • • • • • • • • • • • • - • •+- - - - - • - - - • - - • • - - - • • • • • - - - - - - - • •+

not used

COMMAND

+···-··-··~··-···········-······+·------···········---·---------+

ADDRESS = CSR BASE + 14
Figure 4·10:

ICSR Format

Table 4·9:

ICSR Bi ts

+- •. - - - . -+- - - - . - - -+- - - - - - - - - - - . - - ••• - - •••• - • - • - •• - - • - - ••••• - • - • ·+

I BITS

ACCESS I DESCRIPTION

+- .• - - • - -+- - - - - - - -+- - - - - - • - - - - - - - - •• - - - - - - •••.• - •• - • - • - - ••••• - • ·+

<15:08>

(not used)

<07>

READ

Group interrupt
(1 • interrupt
Vector is in bits <02:00>.

<06>

READ

Enable (l = chip enabled).

<05>

READ

Priority mode (1 =rotating, 0 =fixed).

<04>

READ

Interrupt mode (1 =polled, 0 =interrupt).

<03>

READ

Master mask (1 •chip armed).

<02:00>

READ

Binary vector of the highest unmasked bit in
the
IRR
(Interrupt Controller Interrupt
Response Register). Valid only when bit <07>
is set.

<07:00>

WRITE

Command (see Table 4-10).

pending) .

+ - - - • . . • •+. - - . - - - . +- - - - - - . . . - . - - • • - - . • - - • - • - - - - - . - • - . • • . - - - - . - - •+

4-10

PROGRAMMING INFORMATION
Table 4·10:

~CSR Commands

+- - - - • - - - ·+- - . - ... - .... - ..... ·+ ........... - - - .. - - - .•.••.. - . - . - . ·+

ICSR*
I COMMAND
<07:00> I

DESCRIPTION

+· ... - •.• ·+· - - - ... - .. - - .... - . ·+· ... - - . - . - - .... - - - ... - .... - ..... ·+

00000000

RESET

Sets the IMR (Interrupt
Mask
Register) to all ones. Clears to
zeros,
the
IRR
(Interrupt
Response
Register),
ISR
(Interrupt Service Register), ACR
{Auto Clear Register), and Mode
Register.
Response Memory and
byte
count registers are not
affected.

OOOlOxxx

CLEAR IRR AND IMR

Clears all bits in
IMR.

00010888

CLEAR ONE IRR AND
IMR BIT

Clears both the IRR bit and the
IMR bit specified in <02:00>.

OOllOxxx

SET IMR

Sets all IMR bits to ones.

00111888

SET ONE IMR BIT

Sets the
<02:00>.

OlOOOxxx

CLEAR IRR

Clears all IRR bits to zeros.

01001888

CLEAR ONE IRR BIT

Clears the IRR bit
<02:00>.

OllOxxxx

CLEAR HIGHEST
PRIORITY !SR BIT

Clears the highest priority bit
set in the ISR.

OlllOxxx

CLEAR ISR

Clears all ISR bits to zeros.

01111888

CLEAR ONE ISR BIT

Clears the ISR bit
<02:00>.

100MMMMM

LOAD MODE BITS
M4:MO

Sets the five low-order bits of
the Mode Register to the value in
<04:00>.

4-11

IMR

bit

the

IRR

and

specified

PROGRAMMING INFORMATION

Table 4·10:

ICSR Comm.ands (continued)

+· ...... - -+· - .. - ... - •........ ·+·. - ..... - - - .. - . - - . - . - - . - - - - - - . - - ·+
i ICSR*
I COMMAND
I DESCRIPTION

I <07:00> I
+· - - ... - - -+· .. - ... - - . - .....•• ·+·. - - . - - ... - - .. - .. - - . - - . - ........ -+
lOlOMMNN
CONTROL MODE BITS
Sets Mode Register bits 6 and 5

M7:M5

to the value in <06:05>.
Mode
Register bit 7 is set according
to <01:00>, as follows:
01 00

Bit 7

Unchanged
Set
Cleared
(illegal)

l
0

0
l
0
0

------···

lOllxxxx

PRESELECT IMR FOR
WRITING

All future write operations to
the ICDR load the data into the
!MR.

llOOxxxx

PRESELECT ACR FOR
WRITING

All future write operations to
the ICDR load the data into the
ACR.

lllOOLLL

PRESELECT RESPONSE
MEMORY FOR WRITING

All future write operations to
the ICDR load .he data into the
Response Memory at the interrupt
request level location specified
in <02:00>.

+. . . . . . - . -+- - - - - . - - - - - - - - - - - . -+ - - • • • - • • • - • • • - - • - • - - - - - • - - - - - - - - - +

x = l or 0 (doesn't matter)

4.2.5.3 IRR - The 8-bit Interrupt Request
Register
stores
pending
interrupt requests.
An IRR bit is set when the
corresponding interrrupt
request
line
is
asserted;
and
automatically cleared when the request is acknowledged. The IRR
bits can be read, set, and cleared through the ICSR and ICDR.
RESET clears the IRR.
4.2.5.4 IMR - The 8-bit Interrupt Mask Register is used to
enable (bit cleared) or disable (bit set) the corresponding
interrupt request lines. A set IMR bit does not disable the IRR
bit, and the request will remain pending until the IMR bit is
cleared. Only unmasked interrupts generate the Group Interrupt
output. All IMR bits are set by RESET.
4-12

PROGRAMMING INFORMATION

4.2.5.S ISR · The 8-bit Inter1upt Service Register stores the
acknowledge status of interr1pt requests. When an interrupt is
acknowledged, the controller stlects the highest priority pending
request, clears its IRR bit, end sets its ISR bit. ISR bits can
be automatically cleared at the end of the acknowledge cycle or
on specific command. The ISR can be read throu9ht the ICSR and
ICDR. RESET clears the IRR.
=

4.2.S.6 ACR · The 8-bit Auto Clear Register specifies
the
clearing mode for the ISR.
A set ACR bit specifies the
corresponding ISR bit will be automatically cleared at the end of
the acknowledge cycle; and a cleared ACR bit means that the
corresponding ISR bit must be cleared by the CPU through the ICSR
and ICOR. The ACR can be read through the ICSR and ICDR. RESET
clears the ACR.
4.2.5.7 Mode · The 8-bit Interrupt Controller Mode Register
controls many contrciller option~. T~e Mode register is loaded
through the ICSR and ICDR. It cannot be read. Bits 00, 02, and
07 are available to the ICSR on read operations. RESET clears
the Mode register. The bits are described in Table 4-11.
Table 4·11:

Interrupt Controller Mode Register Bits

+· ..... ·+· ....... - ...................•...•..................... ·+
i BITS
I DESCRIPTION
I
+ ••••••• + ••••••••••.•••••••••••••••••••••••••••••••••••••••••••• +

07
06:05

MM ·· Master Mask.
Enables
(set)
(cleared) group interrupts to the CPU.

and

disables

RPl:RPO ·· Repister Preselect.
Select the internal
register to be read when the CPU reads the ICDR:
RPl RPO Register
0
0 ISR
0
l IMR
1
0 IRR
l
l
ACR

REQP
Interrupt
Request
Polarity.
Determines
interrupt request transition direction for setting IRR
bits. Set = LOW to HIGH, cleared = HIGH to LOW.
{Should always be cleared.)

GIP .. Group Interrupt {GINT) Polarity. When set, GINT
is asserted HIGH; when cleared, GINT is asserted LOW.
(Should always be cleared.)

4-13

PROGRAMMING INFORMATION

Table 4·11:

IMR Bi ts (continued)

+· - .... ·+· .. - ..... - - - - - . - . - - . - . - ... - . - - . - . - . - - - . - - - - - ... - . - .... ·+

I BITS I DESCRIPTION
+· ..... ·+· ...... - - .... - - . - . - . - - - - - . - . - - ........•...... - ........ ·+
02
IM -- Interrupt Mode.
When set, polled
mode
is
selected, and group interrupt disabled. The controller
will not interrupt the CPU. To respond determine if
there are any pending interrupts, the CPU must read the
!CSR. When cleared, interrupt mode is selected, and
group interrupt functions normally.
01

vs -- vector Selection. When cleared, each interrupt
will generate its own vector (contained in Response
Memory). When set, all interrupts generate the same
vector (request level 0 vector).

PM -- Priori~y Mode. When cleared (fixed priority),
level 0 interrupt requests are the highest priority,
level 7 the lowest. When set (rotating priority), the
last
interrupt level serviced becomes the lowest
priority level.

+-. - . - . -+-. - - - - . - - - - - . - . - - - - - . - . - - .. - ..• - - - - - - •• - - - - - • - ....•••. ·+

4.2.6

UART Registers

The registers described in the following figures (4-11 through
4-15) and tables (4-11 through 4-15) are all used to communicate
with and control the keyboard/auxiliary DUART.
Note that Mode Registers lA and 2A are accessed by two succesive
references to the same I/O address. The same is true for the
channel B mode registers. Also note that the following registers
serve different funct~ons on reads and writes:
REGISTER (A and B)

READ

WRITE

Status/Clock Select
Transmit/Rece1ve Buffer
Interrupt Status/Mask

UART Status
Receive Data
Interrupt Status

Tx/Rx Clock Select
Transmit Data
Interrupt Mask

4.2.6.l Mode Registers lA And 2A - These UART registers are
accessed by two successive references to the same I/0 address.

4-14

PROGRAllMIRG IRFORMATlON
lA:
03 07 06 05 04 03 02 01 00
15
+· ..... - ...... - ................ -+·. ·+·. ·+·. ·+· ..... -+- - ·+· ..... ·+
not used
!RRCIRISIERMIPAR MODjPATIB/CHAR
+·. - ..... - ......... - .......... - ·+· - ·+·. ·+·. ·+· ..... -+-. ·+· ..... ·+
2A:
15
08 07 06 05 04 03
00
+· .......•.• - . - .. - .•........... ·+· ... - . ·+· - ·+· - ·+· .... - ... - .. - . -+
!
not used
!CH MODEITRC!CETISTOP BIT LENGTH•
+·. - ...... - ................ - - - - ·+· ..... ·+·. ·+·. ·+· .. - .......... ·+
ADDRESS • CSR BASE + 32
Figure 4·11:

Mode Registers lA and 2A Format

Table 4·12:

Mode Registers lA and 2A Bits

+········+········+·············································+
: BITS
l ACCESS : DESCRIPTION
+· ...... ·+·. - .... ·+· . . . . . . . . . - . . . . . . . . . • . . . . . . . . . . . . . • . . . . . . . . . ·+

(not used)

<15:08>

lA:
<07>

RD/WR

Rx (receive) RTS (request
( l .. no) .

<06>

RD/WR

Rx interrupt select (1 •FIFO full).

<05>

RD/WR

Error mode (1 •block).

<04:03>

RD/WR

Parity mode (10 •no parity).

<02>

RD/WR

Parity type (1 =odd).

<01:00>

RD/WR

Bits per character (11

<07:06>

RD/WR

Channel mode (00 =normal).

<05>

RD/WR

Tx (transmit) RTS control (1 =no).

<04>

RD/WR

CTS (clear-to-send) enable Tx (1 =no).

<03:00>

RD/WR

Stop bit length (0111

send)

control

= 8).

2A:

= 1 bit).

.... ······+·······-+·-···········································-T-

4-15

PROGRAMMING INFORMATION

4.2.6.2 Mode Registers lB And 2B - (ADDRESS
Mode Registers lA and 2A

= CSR BASE + 48) See

4.2.6.3 Status/Clock Select Register A - This register returns
UART status information on a read, and selects the Transmit and
Receive baud rates on a write.
READ:
15

+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+- - -+- - -+-. ·+-. ·+-. ·+·. ·+·. ·+· - -+

not used

RXBIFER!PERIOERITXE!TXRIFFL;RXR

+· - . - - - .. - - - . - - - - -- - - - - - - - - - - - - -+· - -+·. ·+- - ·+- - -+-. -+- - -+· - ·+- - -+

WRITE:
15

+- - - . - - . - - . - - - . - •.. - - . - - - - ... - - -+·. - - - - - . - - . - . - ·+- - - - . - - - - . - - - . -+

not used

IRX CLOCK SELECTITX CLOCK SELECT

+- - - - - - - - - - - - - • - - - - - - - - - - - - - - - - -+- - - - - - . . - - . . . . . + - - - - - - - - - . . - - . . +
ADDRESS = CSR BASE + 34.

Figure 4·12:

Status/Clock Select Register A Format

4-16

PROGRAMMING INFORMATION

Table 4·13:

Status/Clo:k select Register A Bits

+- - •.• - - -+- - • - - - - -+· - .•• - - - - - . - • - - - - - - - • - ••.• - - - - - - - - •. - - - - - - - -+
! BITS
I ACCESS I DBSCRIPTIOU
j
+- - - - - - - -+- - - - - - - -+- - - - - - - • - - - - • - - - - - •• - - - •• - • - •• - - - - ••• - - - - - .• ·+
<15:08>
(not used)

<07>

READ

Received break (1 •yes).

<06>

READ

Framing error (1 •yes).

<05>

READ

Parity error (1 •yes).

<04>

READ

Overrun error (1 •yes).

<03>

READ

Transmitter empty (1 •yes).

<02>

READ

Transmitter ready (1 •yes).

<01>

READ

FIFO full (1 - yes).

<00>

READ

Receiver ready (1 •yes).

<07:04>

WRITE

Receiver clock select (1001 • 4800 baud).

<03:00>

WRITE

~ransmitter

'"--.._.

clock select (1001 • 4800 baud).

+- •• - • - • -+·. - - - - • ·+· - - ...... - .. - .. - - . - . - .. - .. - . - - - - - . - - . - .. - .. - -+

4.2.6.4 Status/Clock Select Register B - (ADDRESS = CSR
50) See Status/Clock Select Register A

BASE

4.2.6.5 Command Register A · All the bits in this UART
are write access only.

+• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •+• • •+• • • • • • • • • • •+• • • T • • • +• • •+• • •+

not used

, 0 'MIS COMMAND DTX ETX DRX ERX
1

+· .. - ...... - .. - - - - - . - . - ........ ·+· - ·+· - - . - •... - ·+-. ·+· - ·+·. ·+·. ·+

ADDRESS

= CSR BASE + 36
Figure 4·13:

Command Register A Format

4-17

PROGRAMMING INFORMATION

Table 4·14:

Command Register A Bits

+- - - ••. - ·+- - . - - - - ·+· - - - • - - - - .• - - - - - - - - - - - - - - - - - - - • - - - - - - . - - - - - - -+
i BITS
ACCESS
DESCRIPTION
i
+- - - - - - - -+- - - • - - - ·+· - - - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .. - . - - - ·+
J

<15:08>

(not used)

<07>

WRITE

(spare - must be zero).

<06:04>

WRITE

Miscellaneous commands:
000 NOP (no operation)
001 Reset mode register pointer. Causes the
Mode
Register
pointer
to ~oint to
register l.
010 Reset receiver
011 Reset transmitter
100 Reset error status. Clears error status
bits
<07:04>
in Status/Clock Select
Register.
101 Reset channel A break-change interrupt.
Clears Interrupt Status/Mask Register bit
<02>.
110 Start break
111 Stop break

<03>

WRITE

Disable Transmitter (1 =yes).

<02>

WRITE

Enable Transmitter (1 =yes).

<02>

WRITE

Disable Receiver (1

<00>

WRITE

Enable Receiver (1 =yes).

yes).

+- - • - - - • ·+-. - - ... ·+· - - - ... - - - - . - - . - ... - - - .. - .. - .. - - - - . - . - .. - - .. ·+

4.2.6.6 Command Register B · (ADDRESS
Command Register A
4.2.6.7

= CSR

BASE

52)

See

Transmit/Receive Buffer A 08

+· ..... - ..• - .. - - - ... - ... - - - . - . - - ·+· ... - . - .... - . - . - - - - . - ..... - ... ·+

not used

DATA

+·. - - . - - - - - - - - - - .. - . - - . - - - - ... - ·+- - - .. - - ... - - - - - - - . - - . - - - - . - ... -+
ADDRESS = CSR BASE + 38

Figure 4-14:

Transmit/Receive Buffer A Format

4 · 18

PROGRAMKING INFORMATION

Table 4·15:

Transmit/teceive Buffer A Bits

+· ...... ·+· - ... - . ·+·. - .......................... - - .. - - .. - . - .... ·+
i BITS

I ACCESS I DESCRIPTION

+· ...... ·+· ... - - - ·+·. - .... - ........... - ............ - .. - - .. - . - - . ·+
<15:08>
:

(not used)

<07:00>

READ

Receive data.

<07:00>

WRITE

Transmit data.

+· ..... - ·+· ...... ·+- .. - . - ....... - . - ...... - ................ - .. - . ·+
4.2.6.8 Transmit/Receive Buffer 8 . (ADDRESS - CSR
See Transmit/Receive Buffer A

BASE

54)

4.2.6.9 Interrupt StatusjMask Register · This register transfers
interrupt status on a read. On a write, set bits enable the UART
interrupt request associated with the corresponding status bit.

+· ....................... - ..... ·+·· ·+·. ·+·. ·+·. ·+·. ·+·. ·+·. ·+·. ·+

not used

IIPC!CBBIRBI!TBiiCRIICBAiRAI TAI,

+· ............. - ............... ·+·· ·+·. ·+·. ·+·. ·+·. ·+·. ·+·. ·+·. ·+

."-

WRITE:
15

+·········-·····················+·······························+
not used

MASK

+·······························+·················--············+
= CSR BASE + 42

ADDRESS

Figure 4·15:

Interrupt Status/Mask Register Format

4-19

PROGRAMMING INFORMATION

Table 4·16:

Interrupt Status/Mask Register Bits

+- - - - - • - -+. - - - . - - -+. - . - ... - . - - - - - - - - - •.......••••. - - . - - - .. - - - - - - +

I ACCESS I DESCRIPTION

' BITS
'

1
'

+- - - • - • - -+-. - - - - - -+- - - - - - - - .• - - - - - - - .. - •• - - •• - .. - •. - ~ .• - - - . - .•. ·+

<15:08>

(not used}

<07>

READ

Input port change (1 •yes).

<06>

READ

Change in break B (1 •yes).

<05>

READ

Receiver ready/FIFO full B (1 =yes).

<04>

READ

Transmitter ready B (1 •yes).

<03>

READ

Counter ready (1 =yes).

<02>

READ

Change in break A (1 =yes).

<01>

READ

Receiver ready/FIFO full A (1 =yes).

<00>

READ

Transmitter ready A (1 =yes).

<07:00>

WRITE

Bit-for-bit mask to enable interrupt request
asscociated
with
the above status bits
(00000010 = enable Receiver Ready interrupt
on channel A).

+· ..•••• ·+ ... - . - - -+- - - - .... - .... - .. - .•.•• - ••••• - • - - - ••.•.•.••. - ·+

4.3

PROGRAMMING

4.3.l

Cursor

The cursor image is stored in the Cursor RAM and occupies the
upper 16 locations (32 bytes) of the VCBOl address space (Figure
4•3) •

The cursor position is determined by the Cursor x Position
Register (subsection 4.2.2) and the CRTC internal registers:
Cursor Scan Start, Cursor Scan End, and Cursor Address High
(Table 4-6). These registers are loaded as follows.
1.

The four Y-positon LSBs determine where the cursor
starts within a character row, and are loaded into the
CRTC Cursor Start Register and Cursor End Register.
Note that the Cursor Start Register includes the cursor
enable bit and the cursor blink rate bit.
4-20

PROGRAMMING INFORMATION

The next six Y-positon bits determine in which character
row the cursor starts. These bits are loaded into the
CRTC Cursor Address High Register.
After these registers have been loaded, the
CRTC
generates a cursor signal which starts a 16·scan line
counter. This counter addresses the Cursor RAM.

Cursor X-position is loaded into the Cursor
Register.

x Position

The minimum X and Y positons are zero. The maximum X positon is
last pixel minus 16. The maximum Y position is last scan minus
16. For best display presentation, all cursor operations, such
as loading position or changing the image, should be performed
when the cursor is off or during vertical retrace time.'

4-21

CHAPTER 5
MAINTENANCE

This chapter describes the VAXstation I system
maintenance
strategy,
maintenance
features, the diagnostic system and
procedures, and monitor aiignment. A troubleshooting flow (Table
5·11) is included at the end of the chapter.
5.1

MAINTENANCE STRATEGY

The maintenance strategy for the VAXstation I is FRU (field
replaceable unit) replacement.
Fault isolation is provided
through
rnicrodiagnostics
(resident)
and
macrodiagnostics
{non-resident).
5.1.1

Service Features

Features which support the maintenance strategy include:
SYSTEM
o

o
o
o

Resident power-up self test
FRU callout and isolation
On·board and remote LED displays
Hardware diagnostics:
Microverify
Macroverify
Device liagnostics
Standalone, VOS (VAX Diagnostic
compatible rnacrodiagnostic

No PM (preventive maintenance)

s. 1

Supervisor)

MAINTENANCE

MONITOR
o
o

Four fault·indicating LEDs
Alignment pattern diagnostic

KEYBOARD
o
o

Power-up self ·test
Key test diagnostic

MOUSE
o

5.1.2

Button test diagnostic

Diagnostic Structure

The VAXstation I diagnostic system (Order Number ZN055-C3),
structure, has three levels, as shown in Figure 5-1.

5-2

MAINTENANCE

+. . . . . . . . . . . . . +
I MICROVERIFY I

AUTOMATIC
EXECUTION

I
+. . . . . . . . . . . . . +
(EHKMC)

.••.•.• I ......................................................... .

+-····························----··+
I
+······-················+
+- - • - - . . • . +

!
I
I
I
I

+········ ·····+ +· ········+ +·········+
I MACROVERI FY I I
CPU
I I MEMORY I
I
( EHKMV)
I i ( EHKAA) I I ( EHXMS) I
+· ........... ·+ +· ....... ·+ +· ....... ·+

STANDALONE
EXECUTION

I
••••••• I •••••••••••.••••.••••••••••••••••••••••••••••••••••••••

•

+ ••••••••••••• +

VDS
(EHSAA)

+ • • • • • • • • • • . . •+

! I i
I I +······························+

''-----

I +···················-+

+ •••••••••• +

I
+···········+ +·········+ +·········+ +······--·+
i

STORAGE I
VCBO 1 i i DZVl 1 i I DEQNA I
SUBSYSTEM I : ( EHXVS) I I ( EHXDZ) I I ( EHXQN) I
(EHXRQ)
+·········+ +·········+ +·········+

EXECUTION
UNDER VOS

+ ••.••••••.. +

Figure 5·1:

Diagnostic St rue tu re

The diagnostics are described in the following sections.
5.2

MICROVERIFY

Microverify (including the power-up self-test for the VCB01) is a
microcoded diagnostic, resident in the 16 k Boot ROM on the
M7135·YA OAP module. It is automatically executed at power-up,
and in response to the console-mode TEST command.

5-3

MAINTENANCE
CAUTION - Console Mode
Before entering console mode, all open files
should
be
closed,
and
all open accounts
logged-off the system. The console interface is
described in Appendix A of the VAXstation I
Owner's Manual, EK-VS200-0M.
Microverify normally
configured
to
run
subsection 2.3.1.2)

runs in single-pass mode, but can
in multiple-loop mode (see Chapter

In single-pass mode, the result of Microverify
reported on the monitor screen as follows:

execution

be
2,

MICROVERIFY STARTED
(approximately five seconds later:)
MICROVERIFY PASSED
(or)
MICROVERIFY FAILED
When Microverify, including the VCBOl self-tests, is successfully
completed and bootstrap is initiated, the keyboard bell sounds.
5.2.l

Microverify Error Reporting

If the MICROVERIFY FAILED response is displayed, the system
returns to console mode, and the >>> console prompt is displayed
on the screen. Failures are reported in the seven-segment LED
located on the CPU insert in the Patch and Filter Panel assembly
{and in the LEDs on the M7135-YA DAP module).
A blinking code
indicates a VCBOl self-test failure.
The failure codes are
listed in Table 5-1.
Table 5-1:

Microverify Error Codes

+-. - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • - - - - - - - - - - - - -+

DESCRIPTION/ACTION

CODE

+ - - - - - - - - - - - -+- - -- -- -- - - --- - -- - - -- - - -- -- -- -- -- - - -- - . - -- -- . - . - -- .+

Microverify failed before completing the
microsequencer test. Error on DAP module.

M7135-YA OAP error.

M7136 MCT error.
5-4

OAP

MAINTENANCE

Table 5·1:

Microverify Error Codes (continued)

+- .. - -. - -... -+- •. - • - - - ••••• - • - . - ••••••• - •• - ••••••• - •••• - ••••••• ·+
I DESCRIPTION/ACTION

CODE

+············+·····················--···························+
4

Undertermined error in DAP/MCT interface.
be DAP, MCT, or interconnect cable.

Memory error.
diagnostics.

Run CPU (EHKAA) and memory

Boot device
controller.

was

Unable to boot from selected
fault).

not

found.

Could

(EHXMS)

Check

device

RQDXl

(media/drive

(period) Primary bootstrap successful.
passed to secondary bootstrap.

Control

BLINKING 7
BLINKING 6

Scan line map test failed if either blinking 7 or
blinking 6 is displayed. Replace the VCBOl.

BLINKING 5

Keyboard
power-up
self-test
failed.
Check
keyboard
cable
and
BCIBT-10
video
cable
connections, or replace the keyboard, or replace
the VCBOl.

BLINKING 4

DUART polled loop-back test failed.

Replace

the

VCBOl.
BLINKING 3

Bitmap memory test failed.

BLINKING 2

Make sure the
backplane slot

Replace the VCBOl.

VCBOl is in
(see Chapter

the
2,

correct
subsection

2 .1).

Make sure the MSA is set to 3840 k.
switch pack El4, Sl:S4 all OFF.
Replace VCBOl.

5-5

VCBOl

MAINTENANCE
Table 5·1:

Microverify Error Codes (continued)

+- - - - - - .•• - - ·+- .. - - •• - ••• - •. - - .. - - ..•. - - - - - - • - - - - •• - - - - - - • - - - - - -+

I DESCRIPTION/ACTION

CODE

+- - - - - - - - • - - -+-. - - - - - - - - - - - - - - - • - - - - • - - - . - - - - - - - - .••• - - - - - - - - - - -+
BLINKING 1
Failed CSR test:

Make sure that the CSR base address is 177200.
VCBOl switch pack E48:
Sl
ON

OFF ON

OFF

Replace VCBOl.

+- - - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+

5.2.2

Monitor Display Errors

In addition to displaying diagnostic failure reports, the monitor
display itself may indicate errors, as described in Table 5-2.
Table 5·2:

Monitor Display Errors

+- - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - • - - - - - - - - • - - - - - - - - - - - - - - - - - - -+

DISPLAY

: DESCRIPTION/ACTION

+ - - - - - - - - - - -+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+

HALF-PAGE

Check VCBOl switches E68 and E48 58.

IMPROPER
SYNC

Check VCBOl switches E68 and E48 58.
E68
= OFF
E48 SS = ON

+- - - - - - - - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+

5.3

STANDALONE DIAGNOSTICS

The standalone diagnostic comprise:
o
0

Macroverify (EHKMV)
CPU )iagnostic (EHKAA)
Memory Diagnostic (EHXMS)

5-6

MAINTENANCE

The three diagnostics are
"MICROVAX DIAGNOSTICS l
console mode.

contained on one diskette, labeled
of 3," and are run with the system in

Macroverify

5.3.1

Macroverify (EHKMV)
is
normally
run
to
verify
system
installation, and run before any other diaqnostics to isolate
faults. Running Macroverify does not destroy disk data.
5.3.1.1 Running Macroverify - Figure 5·2 is
Macroverify run report. To run Macroverify:

example

Close any open files and log-out any open accounts.

Turn system power OFF.

Disconnect external· cables from the
(if any) .

Turn monitor power ON.

Turn system power ON.

Enter console mode (press the HALT button twice).

Insert a blank diskette in drive 2.

Insert the MICROVAX DIAGNOSTICS l of 3 diskette in drive

DZVll

In response to the >>> console prompt type:
>>> B OUAl<RETURN>

5-7

patch

panel

MAINTENANCE

- -. - . - ----. - ----- - . - -- . --. -- . -. -- ----. - ---. . - - - . - -

- - . - . - - - - . - - - - -- - - .

>>> B DUA!
ATTEMPTING BOOTSTRAP
Macroverify Vl.7
This MicroVAX is at microcode revision level 5, hardware revision
level 1, and includes support for F FLOAT and D.FLOAT data types.

Testing

Time to
Test (Mins.}

Memory
0:50
Disk unit DUAO 0:20
Disk unit DUA! 0:20
Disk unit DUA2 0:20
DLVJl
0:40
DZVll
DEQNA
VCBOl

0: 40
0:10
0:10

Comments
TEST SUCCEEDED (1.0 MB)
TEST SUCCEEDED (RD52)
TEST SUCCEEDED (RX50)
TEST SUCCEEDED (RX50)
DEVICE DLVJl WITH CSR 776500 NOT FOUND.
NO TESTING PERFORMED.
TEST SUCCEEDED
TEST SUCCEEDED (Address=AA-00-03-01-10)
TEST SUCCEEDED

Macroverify test completed.
Press RETURN key to enter console command mode.

Figure 5-2:

Macroverify Run Report

Verify that the reported memory size (1 MB in Figure 5-2) is the
size of memory installed in the system. If not, run the Memory
Diagnostic (EHXMS, described below).
Macroverify tests each device to see if it responds to its
assigned Q2-bus address.
If the device does not respond, no
testing is done and Macroverify outputs the device name, CSR
address, and vector address (see DLVJl in Figure 5-2). The
vector address is not output for devices with floating vectors
(such as the DLVJl and DEQNA). Verify that devices not found are
not installed.
For devices that do respond,
the test result is reported as
either TEST SUCCEEDED or TEST FAILED.
If a given tes~ time
~xceeds the minutes indicated in Time to Test (Mins.)
(that is,
SUCCEEDED or FAILED Ltatus is not reported), assume the device
5-8

MAINTENANCE

failed. A complete Macroverify run takes approximately four
minutes. If a device fails Macroverify testing, run the specific
device diagnostic.
5.3.l.2 Macroverify Error Messages - The diagnostic
reports
operator and hardware errors in the Comments column (Figure 5-2).
The following list gives some examples and corrective action.
MESSAGE: Please verify that the cable from the DEQNA module to
the DEQNA patch panel assembly is correctly connected.
Please verify that the fuse at the OEQNA patch panel
assembly has not blown.
ACTION: Check cable connection and fuse.
MESSAGE: This unit either has no media or has been disabled.
Please correct and rerun this diagnostic.
ACTION: Make sure the Fixed Disk Ready pushbutton (on the system
control panel) is.· in the out position (glowing green)
and that the diskettes are correctly inserted.
Re-run
Macroverify.
MESSAGE: This disk is not hardware formatted. Please format the
disk, or,
if this is a diskette, please use another
diskette with correct hardware format and rerun this
diagnostic.
ACTION: Fixed-disk -- run the disk subsystem diagnostic.
Diskette ·· Insert the correct diskette and
re-run
Macroverify.
MESSAGE: This disk is write protected. Please enable writing on
the disk and rerun this diagnostic. NOTE: Testing will
not destroy disk data.
ACTION: Fixed-disk ··put the Fixed Disk Write Protect and Ready
push buttons (on the system control panel) in the out
position (Write Protect does not glow, Ready glows
green).
Diskette -· Remove the write protect tab from
the
diskette or replace the diskette with one that has the
write protect tab removed.
Insert the diskette (the
Removable Disk Write Protect indicator{s) should be
cff). Re-run Macroverify.
5.3.2

CPU Diagnostic

This diagnostic (EHKAA) is run when a CPU fault is indicated by
~icroverify or Macroverify failing, intermittent system problems,
0r failure to bootstrap correctly.

5-9

MAINTENANCE
5.3.2.1 Running The CPU Diaqnostic · Figure 5-3 is an example of
a CPU diagnostic run report. To run the diagnostic:
1.

Insert the MICROVAX DIAGNOSTICS

of 3 diskette in drive

In response to the >>> console prompt enter:
>>> B/100 DUAl<RETURN>

Enter the CPU diagnostic file name
prompt appears:

when

the

Bootfile:

Bootfile: (SYSO.SYSMAINT]EHKAA.EXE<RETURN>
The test will start running, and report every 10
passes
(approximately 20 seconds) as shown in Figure 5-3. It will
continue to run until an error is detected, or until it is
stopped {press HALT pushbutton twice).

EHKAA Vl.13 CPU Test
EHKAA Vl.13
EHKAA Vl.13
EHKAA Vl.13
EHKAA Vl.13
EHKAA Vl.13
EHKAA Vl.13

pass number
pass number
pass number
pass number
pass number
pass number

Figure 5-3:

10 done!
20 done!
30 done!
40 done!
50 done!
60 done!

CPU Diagnostic Run Report

5.3.2.2 CPU Diagnostic Error Reporting - If the
diagnostic
detects an error, it executes a HALT instruction, and outputs an
error message in the format:

5-10

MAINTENANCE

. . . - - - . . - - - . - - . . - - - - - - . -. . . . . --. - . - . -- - --- --- . --. -- ---- -- . -- . - - . .
???Error Test n subtest n problem
problem description
No expected/received data
(or}
Expected - nnnnnnnn
Received - nnnnnrinn

Figure 5-4:

CPU Diagnostic Error Message Format

If the CPU fail3,
replace the DAP module and re-run the
diagnostic.
If the CPU fiils again, replace the MCT module.
(Also see the Troubleshooting Flow, Table 5-11.)
5.3.3

Memory Diagnostic

The Memory diagnostic (EHXMS} is run to isolate a failing memory
module when the operating system detects memory errors or when
intermittent program failures indicate possible memory problems.
The tests are described in Table 5-3.
Before running the Memory diagnostic, the CPU
be run to verify CPU operation.
Table 5·3:
+- - - ·+· - . - - .

diagnostic

should

Memory Diagnostic Tests

- - - - . - .. - . - - - - - ... - - - - - . - .. - - - - - - - •.. - . - - - - - - - - . - - ·+

TEST. DESCRIPTION
+·. - ·+- - ... - . - ... - - . - - - ..

·~.

- .. - .. - ... - .. - . - - - . - . - .. - .••... - - - - . - ·+

CSR FUNCTION TEST ·· Determines the number of CSRs present
and that they set and clear correctly when the Q22-bus is
initilaized.

MEMORY CONFIGURATION TEST ·· Verifies the size of memory,
memory contiguity, and the CSR/memory correlation.

MEMORY ADDRESS TEST PART 1
Memory addresses are written
and verified, one longword at a time.

MEMORY ADDRESS TEST PART 2 ·· Two's complement memory
addresses are written and verified, one word at a time.

5 -11

MAINTENANCE

Table 5·3:

Memory Diaqnostic Tests (continued)

+- - - -+- - - - - - - - - - - - - - - - • . • • - • • - - - • - - - - . - - - • - - • - • - . - - - - - - - - - - - . . - . +

/TEST) DESCRIPTION
+- . - -+- - - - - - - - . - - - - - - • - - • - - - - - - - • • - - - - - - - - - - • • - - • - - • - - - - - - • - • - . -+

MEMORY ADDRESS TEST PART 3 -- The 16 kB bank
written and verified, one byte at a time.

number

MEMORY ADDRESS TEST PART 4 -- The two's complement 16 kB
bank number is written and verified, one byte at a time.

WORST CASE NOISE
TEST ·· A
series
of
stuck-at-0,
stuck-at-1,
and worst-case word parity patterns are
written and verified, one word at a time.

MEMORY PARITY TEST -- Forced bad parity, together with a
set of worst-case patterns, is written into each byte in
memory. This test is executed only if the parity option
is enabled, by entering an ENABLE PARITY command.

DATIO TEST -- Uses the Q22-bus DATIO
memory data, one word at a time.

function

write

DATIOB TEST -- Uses the Q22-bus DATIOB function
memory data, one byte at a time.

write

INSTRUCTION EXECUTION TEST -- Executes a series of simple
instruction sequences, from locations throughout memory.

MARCHING ONES AND ZEROS TEST -- Exercises each 16 kB
memory bank by writing and reading several passes of
alternating bytes of ones and zeros. Memory refresh and
quadword memo:y references are also checked.

+ - - - -+ - - - - - - - - - • - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • • - - - • - - - - - - - - - - - - -+

5-12

MAINTENANCE
5.3.3.l Running The Memory Diaqnostic - The diagnostic control
keys, commands, and options are described in Tables 5-4, S·S, ~nd
5-6.

Table 5·4:

Memory Diagnostic Control Keys

+- - - - - • - - -+-. - . - - - - - •••.. - - - - • - . - • - - - . - - - . - • - - ...... - - . - - - - - - - - ·+
; KEY
I DESCRIPTION
I

+ - - - - - - - - - + - • - - •... -.- .•• - •••• - - ••• - - - • - ••••••••.••••• - - - • - - - - • - • +

Backspaces one character and deletes it. The deleted
character is displayed, preceded and followed by a
backslash ( \) .

<CTRL>U

Deletes and ignores the current line of text.

<CTRL>R

Reprints the current line of text
characters and backslashes omitted.

with

deleted

+- - . • - - - - -+- - - - - - . - . - - . - • - - - - - • - - - - - - - - - - - - - • - - - - • - - - - • • - • - • - - - -+

Table 5-5:

Memory Diagnostic Commands

+- .....•.••... -+- •. - •• - - - •• - - - • - - •• - •• - ••• - •••••• - • - - - - - - • - ••• - ·+
COMMAND
' DESCRITPION
+- - - - - - • - - - .•. -+- .. - •• - •••. - - - - • - - - - - - •••••••• - - - - - - • - - - - - ••• - - -+

HELP

Provides information about the commands.

ENABLE

Selects a command option.

DISABLE

Disables a command option.

MEMORY SIZE n

Specifies the amount of installed memory.

START n

Starts the test(s).

VI E'iJ

Shows the status of command options.

+ . - - - . - . . - - - - - - +- - - - - . - - - - - - - - - - - - - - - . . - • - - - - . - . - - - - • - - - - - - - - . . -+

5-13

MAINTENANCE

Table 5·6:

Memory Diagnostic COll\Jlland Options

+ .. - - - - - - - - • + - . - - - - - - - - - . - - - - - - - • - - - - - - - - - - - - - .. - - - - - - - - .. - - - - - -+

I OPTION
\ DESCRIPTION
+- - • - ••• - - - ·+· - - . - ... - - - - - - - - - - . - - - . - . - .. - - .. - - . - - - - - .. - . - - ... - -+

BELL

Sounds keyboard bell upon error detection.

ERRORS

Prints error messages upon error detection.

HALT

Halts the test upon error detection.

LOOP

Loops on test upon error detection.

MAP

Outputs a memory map.

PARITY

Enables Test 11 execution.

RELOCATION

Causes the diagnostic to relocate itself in
during testing. E*

TRACE

Prints status after each test.

E*
E*
memory

+ . . - . - - . • . . . +• . - - • - . - • - • • • • • • - - - • - . • • • - - - • - • . • • • . • • - - - • • • • • - - • - -+

E*
D*

Default enabled.
Default disabled.

To run the diagnostic:
1.

Insert the MICROVAX DIAGNOSTICS 1 of 3 diskette in drive
1.

In response to the >>> console prompt enter:
>>> B/100 DUAl<RETURN>

Enter the CPU diagnostic file name
p::-ompt appears:

when

the

Bootfile:

Bootfile: [SYSO.SYSMAINT]EHXMS.EXE<RETURN>
A header message with the diagnostic version number, and
the EHXMS> prompt, will appear on the screen. Testing
is continued by typing commands in response to the
prompt.
4.

To display status after each test, enter:
EHXMS> ENABLE TRACE<RETURN>

5-14

MAINTENANCE

Enter the memory size (in kilobytes), for example:
EHXMS> MEMORY SIZE 1024<RBTURN>

To run all the memory tests, enter:
EHXMS> START<RETURN>
There are 12 memory tests
particular test, enter:

;

(Table

5-3).

run

EHXMS> START n<RETURN>
where n is the number of the test.
7.

To get descriptions of the diagnostic commands, options,
and syntax, use the HELP command:
EHXMS> HELP<RETURN>
The command options are enabled and diabled
ENABLE and DISABLE commands. For example:

with

the

enables (and is required} to run the Memory Parity
(Test 8) .

Test

EHXMS> ENABLE PARITY<RETURN>

The status of the options, and the specified memory size
can be displayed with the VIEW command:

EHXMS> VIEW<RETURN>
Options status: BELL = ENABLED, ERRORS = ENABLED,
HALT = ENABLED, LOOP = DISABLED,
MAP = ENABLED, PARITY = ENABLED,
RELOCATION = ENABLED, TRACE = DISABLED
Memory size

= 1024 kB

Figure 5·5:
8•

Memory Diagnostic EHXMS View Command

The diagnostic will loop through the specified test(si
until stopped.
To stop testing and return to the
5·15

MAINTENANCE
prompt, enter <CTRL>C. To exit the diagnostic press the
HALT pushbutton (on the system control panel).
5.3.3.2 Memory Diagnostic Error Reporting · The diagnostic will
print error messages in two formats, one for operator error
(Figure 5-6) and the other for memory errors detected by tests
(Figure 5-7).

- - - - - - - - - - - - - - - - - - - - - - - - - ... - - . - - - ... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - EHXMS - message text

- - - - - - - - - - - ... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .. - Figure 5·6:

Memory Diagnostic Operator Error Format

........................................................................................................................ -- ... ------

EHXMS · Error durnig test n, subtest n
testnarne, subtestnarne
message text
. -- ............ -- ...... -- - - - - - ....... -- - - --- --- ......... - ... ·-- ..................... -- ..... ---- ·- - -- ... - -

Figure 5·7:
5.4

Memory Diagnostic Memory Error Format

VDS DIAGNOSTICS

This section describes the VCBOl diagnostic and the VOS \VAX
D1agnostic Supervisor) procedures needed to run it. Procedures
for
running other VAXstation 1 diagnostics under
VDS
are
described in the VAXstation I Owner's Manual, EK·VS200-0M.
For
more information on these other diagnostics refer to
the
appropriate device documentation, listed in the Preface.
The VDS diagnostics are contained on two diskettes, as follows:
Diskette:

MICROVAX DIAGNOSTICS
2 of 3

MICROVAX DIAGNOSTICS
3 of 3

(EHXRQ) Storage Subsystem
(EHXDZ) DZVll
(EHXQN) DEQNA

(EHXVS) VCBOl

5-16

MAINTENAN.CE

Table 5-7 is a summary of the VOS commands needed to run
diagnostics. The diagnostics are booted from console mode.

the

CAUTION - Console Mode

Before entering console mode, all open files
should
be
closed,
and
all open accounts
logged-off the system. The console interface is
described in Appendix A of the VAXstation I
Owner's Manual, EK·VS200-0M.
Table 5·7:

VDS Command Summary

+· .....• - . - . - ..• - -+-. - . - . - - - .. - - - - . - - - . - .. - - - - - . - . - .. - - . - - - - - - - -+

I COMMAND/
! QUALIFIER

I DESCRIPTION
I

+- - - - - . . • • . . . - . . . .+- . . . - . . . - . . . . . . - - - . . . - - - - • - - • . . . - - . . . . . . . • . . .+

ATTACH

Defines the device to be tested, and path
the device, in the following order:
1.
2.
3.
4.
5.

device type
link type
device name
CSR base address {octal)
vector address (octal)

Note that every item in the
apply to a particular device.

list

may

not

DEATTACH

Used to correct ATTACH command mistakes.

HELP EHXnn

Displays information about the diagnostic,
where nn identifies the specific diagnostic
mnemoric.

RUN EHXnn

Loads and starts the diagnostic.
used
in
place
of the LOAD
commands. )

LOAD EHXnn

Copies the diagnostic into system memory
execution.

ST.~RT

EHXnn

Executes the diagnostic.

5 - 17

(Some ti mes
and START
for

MAINTENANCE

Table 5·7:

VOS Command summary (continued)

+· ...... - ..• - •. - . ·+·. - - . - - .... - ... - . - . - - .. - ..... - - .. - - - - - - .... - ·+

I DESCRIPTION
I

COMMAND/
! QUALIFIER

+. - . - - . - - • - - . - - - - -+. - - •. - - . - .•. - .• - - - . - ... - - - - - - - - - - ... - - - . - - - - . +

/PASSES=n

Where n is the number of times the diagnostic
will be run.

/SECTION=name

Where name is the specific test or section of
the diagnostic selected for execution.

SET EVENT FLAG n

Where n specifies a specific test condition.

SELECT

Identifies the UUT (unit under test).

+- .••. - •••••.. - - - -+- .. - • - .• - - ... - - - - - .•• - •• - •••.. - ...... - . - - - ... +

5.4.l

VCBOl Diagnostic (EHXVS)

The diagnostic comprises 14 tests/routines (described in Table
5-8).
The tests are structured in nine sections; four of which
are selectable (Table 5-9).
The monitor screen should be observed while the tests are
running, to verify correct operation. More specifically, Tests
12, 13, and 14 require visual verification.
Error messag~s are displayed in standard VDS format. Khen there
is no apparent output or activity for certain tests, the keyboard
WAIT LED is turned-on, to indicate that the software is running.
Table 5·8:

VCBOl Diagnostic Tests

+- . - -+ - • - . . • - - - - - - - • - - - - • - • . • • - • • • • • • . • • - • • . . - - - . . - - . . . . . • .

. . .

TEST DESCRIPTION
+··-·+···········-·----·········-···-·····-···-················ +

REGISTER PROBE TEST ·· Performs an access test on ~he
VCBOl I/O registers residing on the Q22-bus. The test is
checking for bus time-outs resulting from the register
probe.

BITMAP MEMORY TEST ·· Performs byte, word, and longword
read/write operations on the 512 kB on-board memory.
Memory addressing, time-outs, and i~valid memory responses
are
checked.
using alternating ones-and-zeros data
patterns.

5-18

MAINTENANCE
Table 5-8:

VCBOl Diaqnostic Tests (continued)

+• • - - +- - - - - - - - - - - - • - - - • - - - - - - • - - - - - - - - - - • - - - - - • - • - • - • - - - - - - - - • - •+
,TEST! DESCRIPTION
I
+ · - • ·+- - - - - - - - - . - - . - - - - - - - - - - - - - - - - - . - - - - - - - .. - .. - - - - - • - - - - . - - - ·+
3

INTERRUPT CONTROLLER R/W -- Tests the internal functions
of
the
Interrupt
Controller chip, with interrupts
turned-off at the CSR and the Interrupt Controller.
(Because
interrupts
are
turned-off,
the Interrupt
Controller response memory is not tested.)

INTERRUPT CONTROLLER
INTERRUPT
TEST ·· An
Interrupt
Controller internal test, including response memory, with
interrupts enabled, using fixed and rotating interrupts.

DUART REGISTER R/W TEST -- Tests
all
the
internal
read/write registers in UARTs A and B, using all-ones,
all-zeros, and alternating· ones-and-zeros data patterns.

DUART LOOPBACK TEST ·- Using the chip's internal loopback
facilities, verifies that both UARTs can transmit data at
all baud rates. The patch panel and cables can be tested
if
an external loopback connector is used and the
appropriate event flag is set.

DUART INTERRUPT
DRIVEN
LOOPBACK
TEST ·· Using
the
Interrupt Controller to drive the software, this test
verifies that data can be transmitted through the DUART.
The patch panel and cables will be tested if an external
loopback connector is used; otherwise, only the internal
loopback path will be tested.

Using
CURSOR TEST·· Tests the CRTC and the Cursor RAM.
the video readback path, the following functions are
checked for valid responses:
o
o
o
o

cursor positioning
cursor RAM
cursor-generated interrupts
cursor enable/disable

SCAN LINE MAP TEST ·- Tests each word in the Scan Line Map
RAM.
Data patterns are written into the RAM and verified
using the video readback path.

5-19

MAINTENANCE

Table 5·8:

VCBOl Diagnostic Tests (continued)

+. - - -+ - - - - - - . - - - - - - • - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+
:TEST! DESCRIPTION
!
+- - - -+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+

MOUSE COUNTER TEST -- Using exetrnal loopback connectors,
the CSR, and UART B, this test forces the mouse X/Y
counters to count up and down.

MEMORY REFRESH TEST -- Verifies
VCBOl's memory refresh circuitry.

ODD/EVEN PIXEL GENERATOR -- Verifies the video
shift
registers (requires visual verification).
Odd pixels
should be displayed on the ·top-half of the screen and even
pixels on the bottom-half. If half or all of the screen
is blank, then a problem exists in either or both shift
registers.

MOUSE AND KEYBOARD INTERACTIVE
TEST -- Displays
the
pointer icon, and a test pattern comprising a square in
each corner of the screen. The test also initializes the
keyboard.
The icon should reflect mouse movement, and a
check is made to see if the returned mouse coordinates
compare to the coordinates of the squares displayed on the
screen. Any combination of depressed mouse buttons should
display the equivalent octal code, and the code for any
depressed keyboard key should be displayed.

ALIGNMENT PATTERN
alignment pattern.

the

operation

GENERATOR -- Displays

the

monitor

+- - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+

5-20

MAIR"l"BllAHCE
Table 5·9:
""---'~

VCBOl Diagnostic Sections

- - - - ........ - • ·+- - - - - - - - - - - - - - - - .. - - - - - - - ... - - ..... - .• - - - - . - -+- - - - .. - .. - •••
I
TESTS
l
SECTIONS +··+··+-·+··+··+··+··+··+··+··+··+·-+··+··+ SBLECTABLE

I 11 21 31 41 51 61 71 81 9110111112!l3ll4l
-------···+·-+··+··+··+··+··+··+·-+··+·-+··+··+--+--+----------MEMORY
I XI XI
I I I I
I XI
I XI X!
I
---------·+·-+··+·-+·-+··+··+--+--+-·+--+··+··+··+··+·-·········

INTERRUPT I

Xi XI

I XI

---·······+··+··+--+··+-·+··+··+-·+··+··+--+-·+··+··+--·········

: xI xI xI

DUART

··········+··+··+--+--+--+--+--+--+··+··+··+··+··+··+···········

CURSOR

··········+··+··+--+··+··+··+·-+··+-·+--+--+-·+··+-·+···········

MOUSE

! XI

... - . - ... ·+- ·+· ·+· ·+· ·+· ·+· ·+· ·+· ·+· ·+· -+· ·+· -+· -+· ·+· - . - . . . . . . .
REFRESH
I
I
I
.1
i XI
X
. . . . . . . - . ~+- ·+· ·+· ·+· ·+· ·+· ·+· ·+· -+- ·+- -+· -+- -+- ·+- ·+·. - •.... - ..

DEFAULT

: X1 X' X: XI X! Xi Xi X Xi XI XI Xi

··········+· ·4··+··+··+-·+··+··+··+··+·-+··+··+··+··+···········
I
I
I XI
X
··········+··+··+··+··+··+··+··+-·+··+··+··+··+··+··+········--ALIGN
I
I XI
x
··········+··+··+··+·-+··+··+··+··+··+··+··+·-+··+··+···········

OPERATOR

The selectable sections (Table 5-9) are:
o

DEFAULT ·· This section, comprising tests l through 12,
is run when no other section is selected. One pass
takes approximately two minutes.

REFRESH -- This section runs Test 11. If event flag 2
is set, a prompt asks for the number of seconds the test
is to run, otherwise, the test runs for 20 seconds.

OPERATOR ·· This section runs Test 13.
To exit the
test, press either the leftmost mouse button or the
keyboard <CTRL> key three consecutive times.

ALIGN -- This section runs
the
alignment
pattern
generatot (Test 14). Pressing <CTRL>C exits the pattern
and returns to the DS> prompt.

5-21

MAINTENANCE
5.4.1.l
1.

Running The VCBOl Diagnostic · To run the diagnostic:
Press the HALT pushbutton twice, to enter console mode.
CAUTION - console Mode
Before entering console mode, all open files
should
be
closed,
and all open accounts
logged-off the system. The console interface is
described in Appendix A of the VAXstation I
Owner's Manual, EK·VS200·0M.

'
2.

Load the MICROVAX DIAGNOSTICS 2 of 3 diskette

drive

Enter:
>>> B/10 DUAl<RETURN>
The VDS header should be displayed, with the DS> prompt.

Load the MICROVAX DIAGNOSTICS 3 of 3 diskette
2.

Enter:

drive

DS> ATTACH RXSO DUA DUA2<RETURN>
DS> SET LOAD DUA2:[SYS0.SYSMAINT]<RETURN>
DS> LOAD EHXVS<RETURN>
OS> ATTACH VCBOl HUB VCBO 777200 lOO<RETURN>
DS> SELECT VCBO<RETURN>
6.

If the screen display appears to be missing pixels, the
run time for the Refresh Test (Test 11) can be increased
by setting event flag 2:
OS> SET EV 2<RETURN>
and responding to the number of seconds prompt with a
value between 0 and 327679. Running the test for a few
minutes (that is, between 150 and 300 seconds) is
usually enough.
If the screen display appears to be
step.

:; - 2 2

normal,

omit

this

llAIRTBRAHCE
7.

If the VCBOl is not the console
must be set:

device,

event

flag

OS> SBT IV S<RBTURR>
8.

Run the diagnostic, by entering:
OS> START<RBTURR>
The diagnostic will execute the DEFAULT section.
To run a different section, use the /SECTION
for example:

qualifier,

OS> START/SBCTION•ALIGN<RITURN>
will run the alignment pa~tern generator (Test 14).
9.

To abort testing and return to the DS> prompt, type
<CTRL>C.
To exit the test normally after completion,
enter:
DS> EXIT<RETURN>

5.4.1.2

VCBOl Diagnostic Error Messages [ TBC ••• )

5-23

MJ,INTENANCE
S.5

MONITOR LED INDICATORS

The monitor is equipped with four LEDs, located and labeled as
shown in Figure 2-7.
All the LEDs normally glow. With the
exception of the POWER LED, a turned-off LED means that the
associated signal is not present. Table 5-10 specifies the LEDs,
their operation, and associated FRU.
Table 5·10:

Monitor LED Description

.... ·+·. ·+· ..................................................... .
LABELIFRUjOPERATION

·····+···+·······················································

POWER [a] The LED is switched OFF when the Power Supply
voltage drops below its failure threshold.

output

VIDEO [b] The LED is switched OFF when
below its failure threshold.

drops

the
•

Video

signal

HSYNC [b] The LED is switched OFF when the Horizontal Sync signal
drops below its failure threshold.
VSYNC [b] The LED is switched OFF when the Vertical
drops below its failure threshold.
(a]

Power Supply

[b]

Most probable failed·FRU first:

Sync

signal

1 VCBOl Module
2 Monitor Video Module
3 Video Cable BC18T-10
When most of the screen is black (that is, only one or two
lines of text are displayed) the VIDEO LED may appear to be
OFF (due to low average-video-pulse input). To verify,
run
the VCBOl diagnostic ALIGN section (subsection S.4.1.1). If
the LED remains OFF, replace the Video module. If the LED
turns ON, there is no failure.

5-24

llAIRTBIJARCB
5.6

MONITOR ADJOSTMBHT PROCBDORBS

Replacing an FRU in the monitor may require that one of the
following
adjustment
procedures be performed.
Figure 5-8
identifies the adjustment controls. The controls are also shown
on a sticker located on the CRT, and identified by a label above
each control.

DYNAMIC

YINTICAL
LINIAIUTY

fOCUI

HOlllZOHTAL

STATIC

J:.=l--------l---------------11r-FOCUS
l'OWEfl SUPPLY_..,......_ _ __
MOOUlE

OUTPUT
VOLTAGE
ADJUST
!COMPONENT
SIOE OF 80AA0l

OVER
VOLTAGE

!COMPONENT
StOE OF 80AROI

Figure 5·8:

Monitor Internal Controls

S-25

MAINTENANCE
5.6.l

Power Supply
1.
2.

Connect a digital voltmeter across the Power Supply
output:
positive test lead to the red output lead;
negative test lead to ground.
Adjust the OUTPUT VOLTAGE control (Rl4) for an output of
+52 Vdc +/- 0.1 Vdc.
CAUTION - Overvoltage Adjustment
DO NOT adjust the OVERVOLTAGE ADJUSTMENT
(R21). It is preset at the factory.

5.6.2

control

Video Module
1.
2.
3.
4.
5.

5.6.3

Remove the video inpu~ cable from the rear panel BNC
connector.
Set the BIAS control (R609) fully clockwise.
Turn up the BRIGHTNESS control (rear panel) until the
raster is visible on the screen.
Turn BIAS control counter-clockwise until the raster
brightness starts to increase. Leave at this setting.
Reconnect the video input cable.
Deflection Module

5.6.3.1
1.
2.

5.6.3.2
1.

Cutoff Preset (G2 Voltage) ·
Remove the video input cable from the rear panel BNC
connector.
Set the BRIGHTNESS control (rear panel) to its midrange,
or to the point where the raster becomes visible.
Adjust the CUTOFF PRESET control (R434) to the point
where the raster disappears.
Reconnect the video input cable.
Horizontal Frequency Run the VCBOl diagnostic and select
(subsection 5.4.1.1):
a.
b.

Enter console mode.
Load the MICROVAX DIAGNOSTICS 2
drive 1.
5-26

the

ALIGN

sectior:

diskette

MAilrl'BNAHCE

c.
"---

Enter:
>>> 8/10 DUAl<RETURN>

d.
e.

Load the MICROVAX DIAGNOSTICS 3
drive 2.
Enter:

diskette

DS> ATTACH RXSO DUA DUA2<RBTURN>
DS> SET LOAD DUA2:(SYSO.SYSMAilrl')<RBTURN>
DS> LOAD EHXVS<RBTURN>
OS> ATTACH VCBOl HUB VCBO 777200 100<RBTURN>
OS> SELECT VCBO<RBTURN>
DS> START/SECTION•ALIGN<R!TURN>
2.

Turn the HORIZONTAL FREQUENCY control (R211) clockwise
and counter-clockwise, noting the points where the image
loses synchronization. There can be none, one, or two
points of sync loss:
a.
b.
c.

5.6.3.3
1.

"---

2.
3.

5.6.3.4
1.

If there is no loss of synchronization, set the
HORIZONTAL FREOUENCY control to its midrange.
If there is one point, set the HORIZONTAL FREQUENCY
control midway between the sync loss point and the
end of its range.
If there are two points, set
the
HORIZONTAL
FREQUENCY control midway between the two points.

Contrast Run the VCBOl diagnostic and select the ALIGN section
(see
subsection
5.4.1.l
or
Horizontal Frequency
adjustment, above).
Using the re-ar panel CONTRAST control, increase contrast
until the horizontal crosshatch lines at the right start
to distort.
Decrease contrast to the point where the crosshatch is
not distorted and there has been a noticeable decrease
in intensity.
Horizontal Size Run the VCBOl diagnostic and select the ALIGN section
{see
subsection
5.4.1.1
or
Horizontal Frequ~ncy
adjustment, above).
5-27

MAINTENANCE

5.6.3.5
1.
2.
3.
4.

5.6.3.6
1.
2.

5.6.3.7
1.
2.
3.
4.

5.6.3.8
l.

Using an alignment tool adjust the HORIZONTAL SIZE
control
until
the image is set to a width of:
368.3 +/· 3 mm (14.5 in).
Horizontal Centering Run the VCBOl diagnostic and select the ALIGN section
(see
subsection
5.4.1.l
or
Horizontal Frequency
adjustment, above).
Measure and record the distance between the center left
edge of the test pattern and the monitor bezel.
Measure and record the distance between the center right
edge of the test pattern and the monitor bezel.
Compare the measurements of steps 2 and 3.
If the
difference between the two measurements is greater than
5 mm, adjust the HORIZONTAL CENTERING control until the
difference is less than 5 mm.
Vertical Height ·
Run the VCBOl diagnostic and select the ALIGN section
(see
subsection
5.4.l.l
or
Horizontal Frequency
adjustment, above).
Adjust the VERTICAL SIZE control until the image is set
to a height of: 283.5 +/· 3 mm (11.16 in).
Vertical Centering ·
Run the VCBOl diagnostic and select the ALIGN section
(see
subsection
5.4.1.1
or
Horizontal Frequency
adjustment, above).
Measure and record the distance between the center top
edge of the test pattern and the monitor bezel.
Measure and record the distance between the center
bottom edge of the test pattern and the monitor bezel.
Compare the two measurements of steps 2 and 3.
If the
difference between the two measurements is greater than
5 mm, adjust the VERTICAL CENTERING control until the
difference is less than 5 mm.
Horizontal And Vertical Linearity ·
Run the VCBOl diagnostic and select the ALIGN section
(see
subsection
5.4.l.l
or
Horizontal frequency
adjustment, above).
5-28

llAIRTBHAHCB

2.
3.

Check that all vertical lines in the test pattern are
equidistant across the screen.
If not, adjust the VERTICAL LINEARITY control (R318)
until the vertical lines are equidistant.
NOTE

Exact equidistance may not be possible. In that
case, adjust for the best possible pattern.

4•

6.
'"-----

5.6.3.9
1.
2.
3.

Check that all horizontal lines of the test pattern are
equidistant across the screen.
If not, adjust the HORIZONTAL LINEARITY control (L232)
until all horizontal lines are equidistant (see the note
above).
Recheck the horizontal and vertical size, and horizontal
and vertical centering. There will be some interaction
between these adjustments ·-:readjust if necessary.
Static And Dynamic Focus Run the VCBOl diagnostic and select the ALIGN section
(see
subsection
5.4.1.1
or
Horizontal Frequency
adjustment, above).
Adjust the STATIC FOCUS control (R431) for a sharp image
at the screen center.
Individual pixels should be
distinguishable.
Adjust the HORIZONTAL DYNAMIC FOCUS control (R418) for a
sharp image at the right and left edges of the screen.
Adjust the VERTICAL DYNAMIC FOCUS control (R416) for a
sharp image at the top and bottom of the screen edges.
Visually check the entire image for center, horizontal,
and vertical focus quality. If necessary, repeat steps
2, 3, and 4.

5-29

MAINTENANCE
5.7

TROUBLESHOOTING FLOW

The following notes apply
5-11):

the

Troubleshooting

Flow

(Table

The answer to any procedure decision is either the
line, or a branch to another step

The=> {"arrow") is read as:

"90 to step."

For example:
- - - - -+- - • - • - - •. - •• - - ..••• - - •••• - ••••.•••• - - - - - • -+- - ••• - .
STEP jPROCEDURE/DECISION
iBRANCH
- . - - ·+· - - . - - ..... - .... - .. - .. - ....... - .... - - - • - . ·+· ... - ..
START Turn system power ON.

Does the system bootstrap?
Is the system operating reliably?
DONE

N •> 1
N •> 20

If the answer to: "Does the system bootstrap?" is no
(N), branch to step 1 (N •> l); if yes (Y), take the.
next line: "Is the system operating reliably?" If that
answer is no, branch to step 20 {N •> 20); if yes, you
are done.
o

Microverify error numbers displayed in the CPU patch
panel segmented-LED display, are valid only when the CPU
is in console Halt mode {the >>> console prompt is
displayed on the monitor screen).

5-30

MAINTENANCE

Table 5·11:

Troubleshooting Flow

.. - - -+· ... - ... - ... - - . - - - - - - - . - - - - - - - - .. - - •. - - •..... - - - . - ·+· .... - .
STEP IPROCEOURE/DECISION
JBRANCH
...... ·+- .. - . - .. - ...... - - - - ... - - - - ........ - •. - - - .. - .. - - ........... - ... - ......... ·+- .... - ..... . .

START Turn system power ON.
Does system bootstrap?
Is the system operating reliably?
DONE
l

N •> l
•> 20

Is DC OK LED ON?
"MICROVERIFY STARTED" displayed on monitor?
Garbled or no monitor display?
Error number in Microverify LED display?
Error message dispalyed on monitor?

N
N
y
y
y

•>
•>
=>
=>
=>
N =>

10
14
19
20

Is AC power switch lighted?
Both fans turning?
Turn power OFF.
Remove all modules except CPU.
Turn power ON.
Is DC OK LED ON?

N ., >
N •>

3
4

N =>

a)
b)
C)

Turn power OFF.
Re-install one module in backplane.
Turn power ON.
Is DC OK LED ON?

Repeat a )

2
8

c ) until d) = NO

Check: AC wall receptacle
AC power cord
AC circuit breaker
Power-on switch
AC power switch

Possibly power supply and/or fan.
Replace fan; or
Replace H7864 power supply.
Return to START

Replace H7864 power supply.
Return to START

Replace failed module.
Is DC OK LED ON'?
Return to START
5-31

MAINTENANCE
Table 5·11:

Troubleshooting Flow (continued)

- - - - -+-. - . - - - - .. - - ..... - .....•... - - ..... - .......•.....•. -+·. - . - - .
STEP !PROCEDURE/DECISION
!BRANCH
.. - . ·+· - - - - .. - ....... - .... - ........ - ........•.. - ... - - ... ·+-. - .. - .
7

Power supply +5 Vdc and +12 Vdc outputs OK?
Possibly faulty LED or cable.
Replace DC OK LED; or
Replace Front Control Panel cable.
Return to START

Microverify LED display ~ 6 or 7?
HALT light ON?
Press HALT button (to release it).
Return to START

Replace DAP.
If error still present, replace MCT.
Return to START

VCBOl Display Density switches set OK?
Set: E68
E48 SB

7
N

or 10
=> 9

=> 11

= ON
=

OFF

Return to START
11

Run VCBOl diagnostic.
VCBOl passes diagnostic.
Replace VCBOl
Return to START

y ::) 12

Possibly faulty cable.
Replace BC18T-10 video cable.
Problem resolved?
Return to START

Possibly monitor problem.
Repair/replace monitor.
Return to START

LED =
LED =
LED ==
LED =

N => 13

6 or 7?
C::.?
.,, .

y :)
y =>
y =>

15
16
17
N => 19

4?
3?

5-32

ICAIRTBRAHCB

Table 5·11:

Troubleshooting Flow (continued)

. - - - ·+- - - - - .. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+- - - • - - STEP !PROCEDURE/DECISION
!BRANCH
- - - - -+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+- - - - - - -

Replace MCT
Return to START

Check OAP to MCT interconnect cable seating.
If seated OK: replace OAP; then MCT; then cable.
Return to START

Can deposit/examine any memory location?
Error message on monitor?

N •> 18
y •> 19

N •> 20
18

Possibly MCT or memory.
Replace MCT; then first MSVll·QA.
Return to START

LED = 2 or l?
Is one of following error messages true?

N •> 20

N •> 24

DEVICE IS NOT PRESENT
DEVICE IS OFFLINE
NO VALID ROM IMAGE FOUND
BOOT DEVICE I/0 ERROR
FAILED TO INITIALIZE BOOT DEVICE
NO RESPONSE FROM LOAD SERVER
MEMORY INITIALIZATION ERROR
Do all the following check OK?
Named valid boot device?
Bootable media is in boot device?
Fixed-disk is ready?
Boot device installation is OK?
System configuration is correct?
Grant continuity is OK?
Switch and jumper settings are correct?
Cable connections are OK?
Correct configuration and re-boot.
Return to START

5-33

y •> 22

MAINTENANCE

Table 5·11:

Troubleshooting Flow

(~ontinued)

- - - - -+- • . - • . • - . • . - • - - - • • • • • - • - - • • - - - - - - - - - - • • - • - • - - - - - - - -+- - • - . . STEP jPROCEDURE/DECISION
!BRANCH
- - - - -+- - - • - - . - •• - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . - - - . - - -+-. - - - - -

Boot diagnostic diskette.
Will Macroverify or other diagnostics load?
Load and Run Macroverify.
Did Macroverify find failed FRU?
Replace FRU.
Return to START

Run applicable device diagnostic.
Replace FRU.
Return to START

Will any (other) device boot?
Replace boot unit, then RQDXl.
Return to START

Possible interrupt or Q22-bus fault.
Replace OAP for interrupt fault.
Replace MCT or backplane for Q22-bus fault.
Return to START

Is following error message true?

N => 27
N => 21

N => 23

=> 27

UNEXPECTED SCB EXCEPTION OR MACHINE CHECK
Is one of following error messages true?
NO VALID BOOT DEVICE IS PRESENT IN THE CONFIGURATION
NONE OF THE BOOTABLE DEVICES CONTAIN A PROGRAM IMAGE
PROGRAM IMAGE NOT FOUND
INVALID BOOT DEVICE FILE STRUCTURE
PROGRAM IMAGE FILE NOT CONTIGUOUS
FILE CHECKSUM ERROR
BAD FILE STRUCTURE HEADER
BAD VOLUME DIRECTORY
INVALID PROGRAM IMAGE FORMAT
PREMATURE END OF FILE
UNEXPECTED EXCEPTION AFTER STARTING PROGRAM IMAGE
Suspect media.
Try to boot from another media.
Return to START

5-34

N => 25

MAINTENANCE

Table 5·11:

Troubleshooting Flow (continued)

... - ·+· ........... - - ... - - - .. - ....... - - - - . - - - - - - - - .. - - . - . ·+- .... - .
STEP !PROCEDURE/DECISION
!BRANCH
. - - . -+· ... - - - ...... - ....... - ... - . - .. - . - .... - .. - - .... - . - - ·+· .. - - ..

Is following error message true?

•> 26

INVALID FILENAME
Re-enter correct filename.
Return to START
26

Is following error message true?

N => 27

PROGRAM IMAGE DOES NOT FIT IN AVAILABLE MEMORY
More physical memory is required for this boot.
Return to START
27

FATAL SYSTEM ERROR.
Possible multiple failures. The following sequence is
recommended:
a)

Reduce system to minimum configuration:
0
0
0
0
0

b)
c)
d)

CPU
MSVll·QA ( 1 )
RQDXl
RX50
VCBOl

Follow troubleshooting flow from START.
Replace failed unit.
Re-install other FRUs, one-at-a·time.
Verify each re-installed unit, by repeating
through d).

steps

- ..••• +- ........•..••• - - .••••••••• - - - •••••• - • - - •• - - - - ·+ .. - - - .....

5-35

CHAPTBR. 6
R.EPLACBKBNT
::

This chapter lists the procedures for removing and replacing
failed FRUs in a desk-top system. With the exception of cover
removal, the same
procedures
apply- to
floor-stand
and
rack-mounted systems. Table 6·1, at the end of this chapter, is
a list of replacement part numbers.
6.1

BACKPLANE MODULES

The general procedure for removing/replacing modules plugged into
the backplane is the same for all modules.
Module Removal

6.1.1
1.

Turn-off system and monitor power.

Remove the
receptacle.

system

6·1

power

cord

from

the

wall

REPLACEMENT
3.

Remove the system unit rear cover, by grasping each
and pulling the cover toward you (Figure 6-1).

Figure 6·1:
4.

end

Rear Cover Removal

Note the position of any external cables connected to
the Patch and Filter Panel assembly. Remove the cables
(Figure 6-2).

Figure 6·2:

Rear Cable Removal

6-2

RBPLACBMBNT

Loosen the two captive screws on the
Patch and Filter Panel assembly,
(Figure 6-3).

left end of the
and swing it open

Captive Screws

Figure 6·3:

Patch and Filter Panel Assembly Access

Note the location of the module to be replaced, and
position of any cables connected to the module.

Disconnect any cables connected to the module (Figure
6·4).
Note: the module may first have to be partially
withdrawn, before the cable(s) can be removed.

Figure 6·4:

Module Cable Removal

6·3

the

REPLACEMENT

Pull the levers at each end of the module to release it,
and carefully pull the module toward you (Figure 6-5).

Figure 6·5:
9.

Module Removal

Note the settings of any switches
removed module.

and

jumpers

the

Module Replacement

6.1.2

Normally, switches and jumpers on the replacement module
should be set to the same position as those on the
removed module. (Also see Chapter 2.)

Make sure the locking levers at each end of
are in the released position.

6-4

the

module

RIPLACIHBNT

Slide the module partially into the slot, and reconnect
any cables removed from the old module (Figure 6-6).

Figure 6·6:
4.

Module Cable Replacement

Slide the module into the slot until firmly seated,
close the locking levers (Figure 6-7).

Figure 6·7:

and

Module Replacement

Close the Patch and Filter Panel assembly, and
the two captive screws.

Reconnect any removed cables to
Panel assembly.
6-5

the

?atch

and

refasten
Filter

REPLACEMENT

6.2

Replace the rear cover.

Turn-on system and monitor
run.

Run Macroverify.

power.

Microverify

should

STORAGE SUBSYSTEM

This procedure describes removal/replacement of the RD52 and RXSO
drives.
Access

6.2.1
1.

Turn-off system and monitor power.

Remove the
receptacle.

Remove the system unit rear cover, by grasping each
and pulling the cover toward you (Figure 6-1).

Remove the system unit front cover, by grasping each end
and pulling the cover toward you (Figure 6-8).

system

Figure 6-8:

power

cord

Front Cover Removal

6-6

from

the

wall
end

RBPLAeBMBRT

Remove the front chassis retaining bracket by removing
the screws that secure it to the enclosure (Figure 6-9).

Figure 6·9:

Front Bracket Removal

Make sure there is enough slack in the cables connected
to the back of the system unit, and slide the system
unit out of the enclosure until restrained by the
stopper on the chassis.

Remove the storage subsystem cover (Figure 6·10).

Figure 6·10:

Storage Subsystem Cover Removal

6-7

REPLACEMENT
6.2.2

RD52 Removal
CAUTION .. R052
Use extreme care when handling the RD52 drive.
It will be damaged by sudden physical shocks
(such as dropping it on a hard surface).
A
shipping case is required to protect the drive in
transit.
CAUTION - Head Positoner Flag
When handling the drive, do not hold the front,
right-hand side of the drive; doing so will cause
the head positioner flag to rotate (Figure 6-11).

6-8

RBPLACBMBNT

Push down the release tab, and slide the drive forward
to access the cables at the rear of the drive (Figure
6-11).

Head flag positioner

donottouch!~~;;:..,,,_,,,,,,,,,,.o:::::::::::::::::::::::::::::::::::::::::~'.'.::::iiii

Figure 6·11:

RD52 Cable Access

f-9

REPLACEMENT

Disconnect the de power and two signal cables
drive (Figure 6-12).

from

the

Rear

Figure 6·12:

RD52 Cable Removal

Remove the drive from the chassis by sliding it forward.
Observe
the previous head positioner flag caution
(Figure 6·11).

6-10

RB PLACEMENT

Replace the red plastic cover on the head positioning
arm (Figure 6·13). (This cover should have reen removed
and taped to the top of the drive during installation.)

Figure 6·13:

RD52 Head Positioning Arm Cover Replacement

6-11

REPLACEMENT

Pack the removed drive
(Figure 6-14).

Figure 6·14:
6.2.3

its

RD52 Shipping Container

RD52 Replacement
1.

special

Unpack the replacement drive.

6-12

shipping

case

RBPLACBMBNT

Set the DIP switches as shown in riqure 6-15 •

·Rear of drive

Z I

t>- ~

BSg~
Front of drive

•

Figure 6·15:

RD52 DIP Switches

6·13

REPLACBMBNT

Remove the red plastic cover on the head positioninq arm
and tape it to the top of the drive (Figure 6·16).

Figure 6·16:

RD52 Head Positioning Arm Cover Removal

6-14

REPLACEMENT

Slide the drive most of the way into the chassis,
leaving, enough room to reconnect the cables (Figure
6-17). Push on the front corners of the drive. Observe
the head positioner flag caution.

;

Head flag positioner
do not touch!

~----~~~

Figure 6·17:

RD52 Insertion

6-15

REPLACEMENT

Connect the de power and two
6 -18) .
Push the drive into
latches.

Figure 6·18:

signal cables (Figure
the chassis until it

RD52 Cable Connection

Replace the storage subsystem cover.

Push the system unit all the way into the enclosure.

Replace the front chassis retaining bracket.

Replace the front cover.

10.

Reformat the disk (see Chapter
Owner's Manual, EK-VS200~0M).

11.

Turn-on system and monitor
run.

12.

Run Macroverify.

6-16

power.

the

VAXstation

Microverify

should

REPLACEMENT

6.2.4

RX50 Removal
l.

Slide the drive forward to access the cables at the rear
of the drive, and disconnect the de power cable and
signal cable (Figure 6-19).

Figure 6·19:
2.

RX50 Cable Access

Push down the release tab, and slide the
and out (Figure 6-20).

Figure 6·20:

RXSO Removal

6-17

drive

forward

REPLACEMENT
6.2.S

RXSO Replacement
1.

Slide the drive into the chassis to reconnect
power and signal cables (Figure 6-21).

Figure 6·21:

the

RXSO Cable Connection

Push the drive all the way into the chassis.

Replace the storage subsystem cover.

Push the system unit all the way into the enclosure.

Replace the front chassis retaining bracket.

Replace the front cover.

Turn-on system and monitor
run.

Run Macrcverify.

6-18

power.

Microverify

should

RBPLACBMBHT

6.3

POWER SUPPLY

The power supply is not adjustable and does not contain any FRUs;
it is an FRU.
6.3.1

Power Supply Removal
1.

Turn-off system and monitor power.

Remove the
receptacle.

Remove the system unit front cover and rear cover.
Grasp each end of the cover and pull the cover toward
you (Figures 6-1 and 6-8).

Note the position of any external cables connected to
the Patch and Filter Panel assembly. Remove the cables
(Figure 6-2).

Remove the rear chassis retaining bracket on
left side of the system unit.

Slide the system unit out of the enclosure.

Remove the storage subsystem cover (Figure 6-10).

Loosen the two captive screws on the
Panel assembly (Figure 6-3).

system

6-19

power

cord

from

Patch

the

and

wall

rear,

Filter

REPLACEMENT

From the front of the power supply,
6-22):
a.
b.
c.
d.

disconnect

(Figure

J7
6-pin, keye<l, locking ac power connector.
JS
9·pin. mass storage power connector.
J9
18-pin backplane power connector.
JlO
4-pin, in-line, keyed, locking fan power
connector.

Figure 6-22:

Power Supply Cable Removal

10.

Remove the five screws that hold the power supply to the
chassis.

11.

Carefully lift the power supply and rest it on the cover
of the backplane modules.

12.

Disconnect the rear cooling fan power connector.

Power Supply Replacement

6.3.2
l .

Rest the power supply on
modules, and reconnect
connector.

6-20

the
the

cover
rear

the

~ooling

backolan_
fan powe~

RBPLACBMENT
CAUTION - Fan Power

The polarized, de oower connector to the cooling
fan must be installed with the curve of the
connector matching the curve of the fan housing,
for correct fan rotation (Figure 6·23).

Figure 6·23:

Fan Power Connector

Place the power supply in positon, making sure that the
rear fan power cable is routed over the top of the fan.

Insert the five power supply hold-down screws.

On the front of

the

power

supply,

reconnect

(Figure

assembly

captive

6-22):

a.
b.

J7
JS

c.
d.

J9
JlO

6-pin, keyed connector.
9-pin connector.
18-pin connector.
4-pin, keyed connector.

Refasten the Patch and
screws.

Filter

Replace the storage subsystem cover.

Make sure that the voltage selector switch
local requirements.

6-21

Panel

set

for

REPLACEMENT

Slide the system unit into the enclosure.

Install the rear

10.

Reconnect any removed cables to
Panel assembly.

11.

Replace the front and rear covers.

12.

Turn-on system and monitor
run.

13.

Run Macroverify.

6.4

chas~is

retaining bracket.
the

power.

Patch

and

Filter

Microverify

should

BACKPLANE AND SIGNAL DISTRIBUTION PANEL

Backplane Removal

6.4.l

Turn-off system and monitor power.

Remove the
receptacle.

Remove the system unit front cover and rear cover.
Grasp each end of the cover and pull the cover toward
you (Figures 6-1 and 6-8).

Note the position of any external cables connected to
the Patch and Filter Panel assembly. Remove the cables.

Remove the rear chassis retaining bracket on
left side of the system unit.

Slide the system unit out of the enclosure.

Remove the storage subsystem cover (Figure 6-10).

Remove the backplane modules cover.

Loosen the two captive screws on the Patch and
Panel assembly and swing it open (Figure 6-3)·.

10.

qemove the backplane modules as described in
6.1.1, steps 6, 7, and 8.

system

6 22

power

cord

from

the

wall

rear,

Filter

subse~ticn

RBPLACBMBNT

11.

Without disconnecting the cables from the drives, remove
the disk drives, following the procedures described in
subsection 6.2.2, steps 1 and 3, and subsection 6.2.4,
steps 1 and 2. The drive cables are disconnected from
the backplane (F~gure 6-24):

a.
b.

J6
J2

RXSO signal cable
RD52 signal cable
RD52 signal cable

Figure 6·24:

Drive Cable Backplane Connectors

6-23

REPLACEMENT
12.

Remove the following cables (Figure 6-25):
a.

J2
J4

Power supply cable
10-pin connector
10-pin connector

Figure 6·25:

Other Backplane Cable Connectors

6 - 24

RB PLACEMENT
13.

To remove the 022-bus cable connected to the signal
distribution panel, loosen the two screws holding the
cover and lide the co\er off. Remove the cable (Figure
6-26).

Fiqure 6·26:

Q22·bus Cable Backplane Connector

14.

Remove the four screws holding the backplane assembly to
the chassis.

15.

Pivot the C/D interconnect side of the backplane 45
degrees (toward the Patch and Filter Panel assembly).
Remove the backplane assembly from the chassis by
lifting it straight up.

16.

Remove the signal distribution panel from the
by removing four screws.

6.4.2

backplane

Backplane Replacement
1.

Install :he signal distribution panel on
with four screws.

Install the backplane assembly with four screws.

Reconnect the Q22·bus cable (Figure
the cover.
6-25

6-26)

the

and

backplane

install

RS PLACEMENT

Reconnect (Figure 6·25):

a.
b.

Jl
J2
J4

Power supply cable
10-pin connector
10-pin connector

Replace the disk drives as described in subsection
6.2.3, steps 3 and 5, and subsection 6.2.5, steps 1 and
2.

Making sure that the connectors
properly aligned, reconnect:

a.
b.

J6
J2
J7

(Figure

6-24)

are

described

RX50 signal cable
RD52 signal cable
RD52 signal cable

Re-install the backplane modules as
subsection 6.1.2, steps 2, 3, and 4.

Refasten the Patch and
screws.

Replace the backplane modules cover.

10.

Replace the storage subsystem cover.

11.

Slide the system unit into the enclosure.

12.

Install the rear chassis retaining bracket.

13.

Reconnect any removed cables to
Panel assembly.

14.

Replace the front and rear covers.

15.

Turn-on system and monitor
run.

16.

Run Macroverify.

Filter

6·26

Panel

the

power.

assembly

Patch

captive

and

Filter

Microverify

should

RB PLACEMENT
6.5

COOLING FANS

6.5.l

Rear Fan Removal
l.

Turn-off system and monitor power.

Remove the
receptacle.

Remove the system unit front cover and rear cover.
Grasp each end of the cover and pull the cover toward
you (Fiqures 6·1 and 6·8).

Note the position of any external cables connected to
the Patch and Filter Panel assembly. Remove the cables
( Fi gu re 6 • 2 ) •

Remove the rear chassis retaining bracket on
left side of the system unit.

Slide the system unit out of the enclosure.

Remove the power supply as
6.3.1, steps 7 throuqh 12.

Remove the four screws and spacers holdinq the fan to
the chassis; lift the fan and guard from the chassis.

6.5.2

system

power

cord

from

described

the

wall

rear,

subsection

Rear Fan Replacement
1.

Place the four fan mounting screws in the chassis holes.

E-27

REPLACEMENT
2.

Place the guard over the screws, with the circular wires
of the guard against the chassis (Figure 6-27).

Place the four spacers over the screws.

-Rear
Front . .

Figure 6·27:

Rear Fan Installation

Fasten the screws to the fan. The fan must be
such that airflow is away from the power supply.

Reconnect the rear cooling fan power connector.

placed

CAUTION - Fan Power
The polarized, de power connector to the cooling
fan must be installed with the curve of the
connector matching the curve of the fan housing,
for correct fan rotation (Figure 6-23).

6-28

RBPLACBMBNT

Replace the power sup~ly
6.3.2, steps 2 through 7.

Slide the system unit into the enclosure.

Install the rear chassis retaining bracket.

Reconnect any removed cables to
Panel assembly.

10.

Replace the front and rear covers.

11.

Turn-on system and monitor
run.

12.

Run Macroverify.

described

the

power.

Patch

subsection

and

Filter

Microverify

should

Front Fan Removal

6.5.3

Turn-off system and monitor power.

Remove the
receptacle.

Remove the system unit front cover, by grasping each end
and pulling the cover toward you (Figure 6-8).

Remove the front chassis retaining bracket by
the screws that secure it to the enclosure.

Make sure there is enough slack in the cables connected
to the back of the system unit, and slide the system
unit out of the enclosure until restrained by the
stopper on the chassis.

Remove the storage subsystem cover (Figure 6-10).

Remove the RX50 as described in subsection 6.2.4,
1 and 2.

system

6-29

power

cord

from

the

wall

removing

steps

REPLACBMBNT

Disconnect the power cord from JlO (Figure 6-28).

Remove the four screws and spacers holding the fan to
the chassis; lift the fan and guards from the chassis.

Figure 6·28:

Front Fan Removal

6-30

RBPLACBHBHT
6.5.4

Front Fan Replacement
l.

Remove the power cable and fan guard from the intake
side of the removed fan and fit them to the replacement
fan.
CAUTION - Fan Power
The polarized, de power connector to the cooling
fan must be installed with the curve of the
connector matching the curve of the fan housing,
for correct fan rotation (Figure 6·23).

Place the four fan mounting screws in the chassis holes.

Place the guard over the screws, with the ci~cular wires
of the guard against the chassis (Figure 6-29).

Place the four spacers over the screws.

Figure 6·29:

Front Fan Installation

rasten the screws to the fan. The fan must be
such that airflow is away from the power supply.

Reconnect the fan power cable to JlO.

6-31

placed

REPLACEMENT

Install the RX50 drive as described in subsection 6.2.5,
steps 1 and 2.

Replace the storage subsystem cover.

Slide the system unit into the enclosure.

10.

Install the front chassis retaining bracket.

11.

Replace the front cover.

12.

Turn-on system and monitor
run.

13.

Run Macroverify.

6.6

power.

Microverify

should

PATCH AND FILTER PANEL

Insert Removal

6.6.l

Turn-off system and monitor power.

Remove t~e
receptacle.

Remove the system unit rear cover, by grasping each
and pulling the cover toward you (Figure 6-1).

Note the position of any external cables connected to
the Patch and Filter Panel assembly. Remove the cables.

Loosen the two captive screws on the
Patch and Filter Panel assembly,
(Figure 6-3).

Note the position of any internal cables connected to
the Patch and Filter Panel assembly insert. Remove the
cables.

'·

Remove the four screws holding the insert to the
and Filter Panel assembly. R~move the insert.

system

6 - 32

power

cord

from

the

wall
end

left end of the
and swing it open

Patch

RBPLACBMBNT

6.6.2

6.7

Insert Installation
1.

Using four screws, fasten the insert to
Filter Panel assembly.

Connect the internal cables to the insert.

Refasten the Patch and
screws.

Filter

Panel

assembly

captive

Reconnect any removed cables to
Panel assembly.

the

Patch

and

Filter

Replace the rear cover.

Turn-on system and monitor
run.

Microve~ify

should

Run Macroverify.

power.

the

Patch

and

FRONT CONTROL PANEL

Control Panel Removal

6.7.l

Turn-off system and monitor power.

Remove the
receptacle.

Remove the system unit front cover. Grasp each end of
the cover and pull the cover toward you (Figure 6-8).

Remove the four screws from the
panel assembly.

system

6-33

power

cord

front

from

the

wall

control

REPLACEMENT

Remove the connector from the
circuit board (Figure 6·30).

control

0
00 00
0()00 °00

Figure 6·30:

Front Control Panel Removal

6-34

panel

printed

R.BPLACBMBN'l'

Remove the four screws that hold
assembly together (Figure 6·31).

the

control

panel

r'I
I

Figure 6·31:
6.7.2

Front Control Panel Disassembly

Control Panel Replacement
LEDs
the

to correctly position the assembly,
four screws that hold the assembly

Using the
refasten
together.

Reconnect the control panel cable.

Remount the panel with four screws.

4•

Replace the front cover.

6-35

REPLACEMENT

6.8

Turn-on system and monitor
run.

Run Macroverify.

power.

Microverify

CRT

should

MONITOR

Monitor Cover Removal

6.8.1
1.

Place the monitor on
surface.

its

face

level

work

WARNING - CRT Face

The integral CRT bezel is designed to keep the
CRT face above the work surface; however, the
work surf ace under the CRT face should be clear
of any debris. In addition, it is recommended
that rough work surfaces be covered to prevent
any unnecessary scratches on the bezel.
2.
3.
4.

To remove the tilt-swivel base from the monitor cover,
remove the four mounting feet from the monitor. The
mounting feet are finger tight.
Remove the four philips-head screws from the rear of the
cover.
_
Lift the cover off the monitor compartment.
EMI Screen

6.8.2

WARNING - CRT Neck

With the EMI screen removed, the neck of the CRT
is exposed and can be broken. Be very careful
when removing modules or passing tools over the
monitor compartment.
1.
2.
3.

With the cover removed, place the monitor in its
viewing position.
Loosen the six screen hold-down screws.
Remove the EMI screen.
6-36

normal

REPLACEMENT

4.
5.
6.8.3

When installing the screen, be sure that each slot of
the screen flange is under its a~sociated hold-down
screw.
Tighten the hold-down screws.
Monitor Power Supply

1.
2.
3.
4.
6.8.4

Remove the two connectors on the Power Supply assembly.
Loosen the four philips-head mounting screws (right side
panel, viewed from rear).
Remove the assembly by working the mounting screws
through the elongated mounting holes.
To install the assembly, reverse the previous steps.
Deflection Module

1.
2.
3.
4.
6.8.5

Remove the four module connectors.
Loosen the four philips-head module mounting screws
(left side panel, vie¥ed from rear).
Remove the module by working the mounting screws through
their elongated mounting holes.
To install the module, reverse the previous steps.
Video Module

1.
2.
3.

Remove the four module connectors.
Loosen the four philips·head mounting screws on the rear
panel.
Remove the module by working the mounting screws through
their elongated mounting holes.
CAUTION

Be careful not to entangle any module component
on the CRT cable, or bend/break the LEDs of the
module assembly.
4.

To install the module, reverse
observing the previous caution.

6-37

the

steps,

REPLACEMENT
CRT Cable

6.8.6

1.
2.
3.
4.

S.
6.8.7

Remove the CRT cable connector from the Video Module.
Slide the quick~disconnect spade and pin of the cable
from the Video Module.
Slide the quick-disconnect spade from the grounding lug.
Disconnect the CRT socket and remove the cable from the
compartment.
To install the cable, reverse the previous steps.
Monitor Cover Replacement

Place the monitor on its CRT face.
WARNING - CRT Face

The integral CRT bezel is designed to keep the
CRT face above the work surface; however, the
work surface under the CRT face should be clear
of any debris. In addition, it is recommended
that rough work surfaces be covered to prevent
any unnecessary scratches on the bezel.
2.
3.
4.
5.
6.

Place the cover over the compartment; be sure that the
cover edge fits into the CRT bezel assembly.
Insert and tighten the four philips-head mounting screws
on the rear of the cover.
Hold the tilt-swivel base, with the lever pointed down,
against the monitor bottom.
Align the base and monitor mounting holes, and replace
and tighten the monitor feet.
Place the monitor in its normal viewing position.

6-38

REPLACEMENT

Table 6·1:

Part Numbers

+- - . - .... - .. - - - - ... - .. - - - . - - - . - - - . - .. - . - - .... ·+· .. - - . - . - . - . ·+
I DESCRIPTION

PART NUMBER I

+ .. - . - . - . - - - .... - - ...... ·.... - ................. + .. - .......... +
KD32-AB

Module, Data Path
Module, Memory Co~troller
Fll MMU
Cable, LED and Baud Rate
Cable, OAP - MCT
Cable, Patch Panel
Insert, Patch Panel

M7135-YA
M7136
21-15542-01
BC22K-1C
70-18448-00
70-11411-lC
70-21150-01

+·················------·-·-··················+····--·······+

l MSVll·QA
Module, l MB Memory
.M755l·AA I
+· ....... - . - - - . - .. - - - - - . - . - - . - - - - - - .. - . - - ... - ·+· ........... ·+

RQDXl

Module, Disk Controller
Cable, RD/RX Data

M8639
BC06L-1C

+· - - - - ... - ... - - - - - .... - - ... - .. - . - ........ - . - . ·+· - . - - . - . - . - . ·+

RD52

Drive, 30 MB Winchester
Cable, Data · 20 Conductor
Cable, Data · 34 Conductor

RD52
I 17-00282
I 17-00286

+ - - - - - - - - • - - - - • - . • - • - - - • • • - • - • • • - • - - - - - • - • • • • •+- • • • . • . - . . . - -+
I RX50
Drive, Diskette
I
RX50 -AA i

I 17-00285-02

Cable, Data

+ - - • - • - - - ••••.•• - - •• - - • - • -·- - • - - - •• - • - ••• - ••••• + .• - - ••.• - - •.. +

: RD/RX

I 70-20435-lK

Cable, Power

+· - - - . - - - - - - .. - . - - ... - .... ··- - - - - ... ~ - ........ ·+· ...... - .... -+

VCBOl

Module, Video Controller
!
M7602
Cable, Monitor/Keyboard (Video) i
BC18T-10 '
Insert, Patch Panel
! 70-21495·01 '

+· ... - .... - . - . - . - - - . - .. - - .. - - - - - - - - - - - . - . - . - - -+- .• - - - - - - - - - -+

VRlOO

Monitor
Power Supply
Board, Video
Board, Deflection
Assembly, CRT Socket
Assembly, Control Bracket
Cable, Video - Deflection
Cable, Power Supply
Video
Cable, Power Supply · Deflection
Alignment Wrench
Alignment Ruler

VR100-AA
29-24782
29-24783
29-24784
29-24785
29-24789
29-24786
29-24787
29-24788
29-23190
29-24868

+ ... - - ..• - - - - . - - - • - - - - . - . - . - - - - - - - •.•• - •. - •.. ·+·. - ... - .. - .. ·+

6-39

REPLACEMENT

Table 6·1:

Part Numbers (continued)

+- - - - - - . - . - . - . - - - - . - - - - - - - . - - - - - - . - - - - - - • - - - . -+- - - . . - . - - - . - -+
DESCRIPTION
I PART NUMBER I
+-. - .. - - - . - .. - . - - - - - - - . - ·.· - - . - - - .. - - - - - - • - - - • ·+·. - - - - . - - - - - -+
, H7864
Power Supply
I 30-21794-01
Fan, 12 Vdc
I 12-17556-01 ,
+- - - - - • - - - - - - • - - - .• - - . - . - - ... - - - - - - - - - - - - - - - - -+- - - - - - - - - - - - -+

H9278-A

Backplane Assembly

I 70-19986

+- - - - . - •. - - - - • - . - . - . - •. - . - .• - • - •. - - - - . - - - • - - • -+· - - - - - - - - . - - -+

Keyboard

LK20l·CA

+· - - - . - - - . - - - - - - - - - - - . - - - .. - - - . - .... - - - . - - - - - -+-. - .... - . - - . ·+

Mouse

30-20038-01

+- - - . . . . . . . • . - - - . - . - - - . - - - - . - - - . - - . - - - - - - . - - . . +- - - - - . - - - - - - -+

· Jumper

Two-position

12-18783

+. • - - - - - - - - - - - - - - - . - . - - - - - - - - - • - • - - - - - - - - . - - . -+ - - - - - - - - - - - - -+

DEQNA

Module, Ethernet Controller
M7504
Cable, Patch Panel
[TBS]
Insert, Patch Panel
[TBS]
H4000
Transceiver
[TBS]
Cable, Transceiver
[TBS]
+-------------- ····-···-· ---·-----------····+·-···········+
DZVll
Module, Async. Line Multiplexer
M7957
Cable, Patch Panel
[TBS]
Insert, Patch Panel
[TBS]
+· - . - - . . . . - . . . . . . . . . - .. - . . . . . . . . . - . . . . . . . - . - . ·+- ...... - . - . - ·+

LASO
LA100
+

Printer
Printer
Cable, Printer - SLU

[TBS]
[TBS]
BC22D-10

... - .. - - - - - .. - • - . - - • - - - - . - - - - • - - •• - . - ••• - - . ·+·. - .... - - . - - -+

6-40

APPENDIX A
GLOSSARY

l·plane ·- Sarne as single-plane.

See Video memory.

Bitmap memory -- See Video memory.

Cursor ·- The small
image, that shows

blinking
position

rectangle, underscore, or other
in a display.
(Not the same as

Pointer.)

Full-page monitor -· The VAXstation I uses a full-page monitor;
that is, a 48 cm (19 in, ~iagnol) CRT with a display density of
885 k pixels (1024 h X 864 v). {Also see Half-page monitor.)
Half-page monitor ·-A 38 cm (15 in, diagnol) CRT with a display
density of 384 k pixels (800 h X 480 v). The VCBOl can drive
either
full-page
or
half-page
monitors
{hardware-switch
selectable). (Also see Full-page monitor.)

Landscape -- A video display format in which the screen is
than it is high. (Also see Portrait.)

wider

Mouse -- The small box-like device connected to the VAXstation
for
moving the pointer. The mouse has three control buttons, a
mcvernent·transmitting ball underneath, and a cable.
No·cache indicator ·· Bit <28> of the 30-bit MicroVAX physical
Jddress.
Addresses with bit <28> set are treated the same as
addrresses with bit <29> set, with the following constraints:

o
o
o

Data at the specified address is not cached.
The reference must be byte· or word-aligned.
String, quad, octa, floating, and field references
not allowed.

Pointer .. The locating up-arrow

A-1

displayed

the

are

VAXstation.

GLOSSARY

The pointer is moved to a location on the monitor screen by
moving the mouse. (Not the same as Cursor.)
Portrait -- A video display format in which the screen is
than it is wide. (Also see Landscape.)

higher

Screen memory -- This term is sometimes used to describe the
portion of video memory that is selected for display on the
screen. The number of bits in screen memory is the same as the
number of pixels on the screen. (Also see Video memory.)

Sinqle·plane ·· See video memory.
Split·screen scrolling ·· The VTlOO terminal allows a scrolling
region to be defined. The scrolling region comprises any number
of lines; from a minimum of two to the full screen.
Therfore,
information
displayed in the scrolled-region lines can be
replaced by ~ntering key strokes (as when reviewing entries in
the columns of some table); while information displayed in the
lines of the non-scrolled region is constant (as in table column
headings).

System console ·· A terminal connected to the CPU through a
special purpose interface (unlike the serial interface for normal
user terminals). This interface allows the terminal to function
as a user terminal or as the operators control terminal. In the
VAXstation I, the VRlOO and keyboard function as the system
console, and the VCBOl provides the special purpose interface.
Video memory ·· The VCBOl contains a single-plane bit-mapped
video memory.
Single-plane means that there is a one-to-one
correspondence between pixels on the monitor screen and bits in
the memory; in other words, the value (on or off) of each pixel
on the screen corresponds to the value (1 or 0) of only one bit
in memory. In multi-plane systems, each pixel may be defined by
a number of bits, representing several intensity levels (shades
of gray), or colors, or both. In a single-plane system, gray
shading is contollled by the pattern of on and off pixels (1 and
0 memory bit values). Bit-mapped means that the image displayed
in pixels on the screen has a one-for-one correspondence to a bit
pattern mapped in memory. {Also see Screen memory.)

A·2

~·

I:.~OEX

ACR (Interrupt Controller Auto
Clear Register), 4·11
asynchronous multiplexer part
number, 2·25
baud rate, 4-16
8857, 3-8
BDAL<21:00>, 3·7
BDCOK, 3·d
BOIN, 3·7
BDMGI, 3-7
BDMGO, 3-7
BDMR, 3·7
BDOUT, 3-7
BEVNT, 3·8
BHALT, 3-8
BIAKI, 3-7
BIAKO, 3·7
BINIT, 3-8
BIRQ7,6,5,4, 3-7
blink rate, 4-20
BPOK 3. 8
BREF, 3-8
BRPLY, 3-8
BSACK, 3-7
BSYNC, 3-7
BWTBT, 3·8

CPU (central processing unit),
1-1
CRT (cathode-ray tube), 1-2,
3-12
CRTC, 3·12
character
line, 3-13
row, 3·13
time, 3·12
(CRT controller), 3-4
horizontal
blanking, 3-12
character time, 3-12
retrace, 3-12
sync, 3-12
Hsync, 3-12
vertical
blanking, 3-13
retrace, 3-13
sync, 3-13
Vsync, 3-13
CSR (control and status
register), 2-17, 2-19
CTS (clear-to-send}, 4-15
cursor
blink rate, 4-20
enable, 4 - 20

CID interconnect, 2-5
CAS (column address strobe),
3-17
CAUTION
Console Mode, 5-4, 5-17,
5-22
Fan Power, 6-21, 6-28, 6-31
Head Positoner Flag, 6-8
Overvoltage Adjustment, 5-26
RD52, 6-8
character
line, 3-13
row, 3-13
ti me, 3 -12
console mode, 5-3, 5-4, 5-7

OAP
(data path), 2-1
module part number, 2-6
data path module part number,
2-6
DEQNA part number, 2-22
diagnostic system order number,
5-2
DIP (dual in-line package),
2-6
disk controller
cable part number, 2-16
part number, 2-16
diskette drive cable part
numbers, 2-17

Index-1

OMA (direct memory access),
2-16
documents
order numbers, x11
related documents list, x11
DTR (data terminal ready),
2-27
DUART (Dual Universal
Asynchronous Receiver
Transmitter), 3-5
dynamic RAM, 3-15
DZVll part number, 2-25

IMR (Intctrupt controller
Intcrtupt Mask Register),
., - l 1
initi~li~ed bit values, 4·3
interrupt
controller
registers
ACRI 4 -11
ICDR, 3-10, 4-9
!CSR, 3-10, 4-10
IMR, 4 · 11
I RR I 4 - 10 I 4 - 11
ISR, 4-11
Response Memory, 4-J
mode
interrupt, 4·14
polled, 4·14
priority mode
fixed, 4·14
rotating, 4-14
IRR (Interrupt Controller
Interrupt Response
Register) , 4 -10, 4 - 11
ISR (Interrupt Controller
Interrupt Service
Register ) , 4 - 11

Ethernet controller part
number, 2·22
FB (forced busyl, 2-27
FIFO (first·in·first·out
stack, silo), 4-15
f ixed·disk drive cable part
numbers, 2-17
FRU (field replaceable unit),
5·1
full-page monitor, 2·20
G7272 Grant Continuity card,
2·23
GB (gigabyte), 4-1
GINT (Group Interrupt), 4-13
Grant Continuity card G7272,
2-23

kB (kilobyte), 2-17
keyboard
part number, 2-22
(video) cable part number,
2-22

half ·page monitor, 2-20
horizontal
blanking, 3-12
character time, 3·12
retrace, 3-12
scan line, 3·12
sync, 3-12
Hsync (horizontal sync), 3-12,
4. 7

LAlOO cable part number, 2·22
LASO cable part number, 2-22
LAN (local area network), 2·22
LSB (least significant bit),
3-16
LUN (logical unit number),
2-16

ICDR (Interrupt Controller
Data Register), 3-10, 4-9
icon, 2-22
ICSR (Interrupt Controller
Command/Status Register),
3-10, 4-9

MB (megabyte), 2·5
MBZ (must be zero), 2·20
MCT
(memory controller), 2-1
module part number, 2-9
memory

Index-2

controller module (MCT) part
number, 2-9
module (MSVll-QA) part
number, 2-9
MOS (metal-oxide silicon),
1-2
MSA (memory starting
address), 2-17, 4-2
PROM (programmable read-only
memory) , 2 - 5
RAM (random-access memory),
1-2
Response Memory, 4-9
screen memory, 2-17
also see Appendix A
starting address (MSA), 2-17,
4-2
video memory, 2·17
also see Appendix A
Microverify
~ultiple-loop mode, 2·6, 5·4
single-pass mode, 2-6, 5·4
mode
interrupt
fixed priority, 4-14
interrupt, 4·14
polled, 4-14
rotating priority, 4-14
Microverify
multiple-loop, 5-4
single-pass, 5-4
VTl 0 0 2 - 6
monitor part number, 2-21
MOS (metal-oxide silicon), 1-2
mouse part number, 2-22
M3A (memory starting address),
2·17, 4·2
MSB (most significant bit),
I

3-16

...

MSCP (mass st~rage control
protocol), 2·16
MSVll·QA part number, 2-9
multiple-loop mode, 2-6, 5-4
mux (multiplexer), 3-17
~OP (no operation), 4-18
NOTE
Bit Descriptions, 4·3

Coordinate System, 3-15
G7272 Required, 2-23
Monitor Alignment, 3-30
Nominal Values, 3-5
VTlOO Mode, 2-6
Order Number
listed under Part Number
PAL (programmable logic array),
3-4
Part Number
asynchronous multiplexer,
2-25
CPU
data path module, 2-6
memory controller module,
2-9
DEQNA, 2-22
diagnostic system, 5-2
disk controller, 2-16
disk controller cable, 2-16
diskette drive cables, 2-17
documents, xii
DZVll, 2-25
Ethernet controller, 2-22
fixed-disk drive cables,
2-17
keyboard, 2-22
keyboard (video) cable, 2-22
LAlOO cable, 2-22
LASO cable, 2-22
memory module, 2-9
monitor, 2-21
mouse, 2-22
MSVll-QA, 2-9
printer cable, 2·22
RD52 cables, 2-17
RQDXl, 2-16
RQDXl cable, 2-16
RXSO cables, 2-17
Table of, 6-40
VCBOl, 2 -17
VCBOl cable, 2-21
video cable, 2-21
video controller, 2-17
PM (preventive maintenance),
5-1

lndex-3

Printer cable part number,
2-22
priority mode
fixed, 4-14
rotating, 4-14
PROM (programmable read-only
memory), 2-5

RTS (request to send), 2-27,
4-15
Rx (receive, receiver), 4-15
RX50 cable part numbers, 2-17
screen memory, 2-17
also see Appendix A
SID {system identification),
2-6
single-pass mode, 2-6, 5-4
SLU (serial line unit), 2-5
split-screen scrolling - see
Appendix A
static RAM, 3-16, 3-24

Q22-bus signals
BBS7, 3-8
BDAL<21:00>, 3-7
BDCOK, 3-8
BOIN, 3-7
BDMGI, 3-7
BDMGO, 3-7
BDMR, 3-7
BDOUT, 3 · 7
BEVNT, 3-8
BHALT, 3-8
BIAKI, 3 • 7
BIAKO, 3- 7
BINIT, 3-8
BIRQ7,6.,5,4, 3-7

Tx (transmit, transmitter),
4-15
UART (Universal Asynchronous
Receiver Transmitter), 3-5
UUT (unit under test), 5-18

B POK I • ·3 - 8
EREF, 3-8
BRPLY, 3-8
BSA CK I 3 - 7

BSYNC, 3-7
BWTBT, 3-8
RA!1

dynamic,

3-15

'. candom-access memory), 1-2
static, 3-16, 3-24
RAS (row address strobe), 3-17
sa~2 cable part numbers, 2-17
re.:l:sters
:SR, 2-17,

2-19

1nterrupt controller
.;CR, -l-ll
ICDR, 3-10, 4-9
ICSR, 3·10, 4-10
I MR, ~ - 11

IRR, ~-10, -l-11
ISR, -i·ll

cable part number, 2-16
oart number, 2-16

VCBOl
cable part number, 2-21
part number, 2-17
VOS (VAX Diagnostic
Supervisor), 5-1, 5-16
vertical
blanking, 3-13
retrace, 3-13
sync, 3-13
video
cable part number, 2-21
controller part number, 2-17
memory, 2-17
also see Appendix A
refresh, 3-15
Vsync (vertical sync), 3-13,
4-7
VTlOO mode, 2-6
WARNING
CRT face, 6-36, 6-38
CRT Neck, 6-36
Input Power, 3-37
Power Supply Capacitors,
3-37

Index-4