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EK-VT100-TM-002

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Document:	VT100 Series Technical Manual
Order Number:	EK-VT100-TM
Revision:	002
Pages:	348
Original Filename:

OCR Text

\"AL°,°,

SERIES

TECHNICAL MANUAL

EK-VT100-TM-002

vTiIOO

SERIES

TECHNICAL MANUAL

digital equipment corporation - maynard, massachusetts

Ist Edition, August 1979
2nd Edition, September 1980

The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS
UNIBUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
IAS

CONTENTS

CHAPTER 1

INTRODUCTION AND SPECIFICATIONS

VT 100 SPECI ICALIONS .. uuvuiiiiiiiiiiiiiiiiieeieeeeeeeeeeeee
et e eeeeeeeeeeeeeeeeeereeeeteeeereeertererasstarsstaraerassssssrarasrrersssssssrens
Ordering Hardware DOCUMENtAtION ...........cooiiiiiiiiiiiiiiiiiiiiiiiiii
s snnns
Related Documentation ...........oooiiiiiiiiiiiiiiiiceeeeee
e
CHAPTER 2

1-2
1-4
1-4

OPERATOR INFORMATION

Part 1 — Keyboard Controls and INdicators ..o
e e ee e
NUMETIC KEYPaAd....cooiiiiiiiiiieeee
e e
e e e e e e e e eeeeens

1% (0] 1 1170)g @)
114 () SRR
U PRSP RRPUURRRPURPRRRRRIN
Audible Indicators (TONES) .......ouuuiiiiiiiiiiieeee
ettt
e e e e teraeeeeeeeesenaanes
Part 2 — SET-UP Mode ...
nsssnsssnnes

2-1
2-3
2-5
2-5
2-6

SET-UP FEatUres.....cccccoiiiiiiiiieeteeeeeeeeeee
e ee e e e e e eeeee e e ananens
2-7
SET-UP A
et
e e e e e e e e e e e e e e e e e e e s e e e e e e e e e eeeeeeeeeeeeeeaeeeeeeeeeeeens
2-7
SET-UP B ...t
reee e e e e et e e e e e e e e
asarsane e
2-8
Determining What a SET-UP Feature Does .........ccccccceiviiiiiiiiiiiiiiiiiiiiiiiieieeeeeee, 2-8
How to Change a SET-UP Feature.......cccooovviiiiiiiiiiiiiiciiicieeeeeeeee
e 2-10
Setting the Answerback MesSage .........coovvviiieiiiiiiiiiei

e,
Saving SET-UP Features.......cooovvmiiiiiiiiiiiiieeeeeeceeee
e
Recalling SET-UP Features.........ccccoooiiiiiiiieiiecceieeceecceeeeeeeeereeceeeeeeeeeeeeeeeeeeeeeeeee
Resetting the Terminal ...
Part 3 — Definitions of SET-UP Features ................oovrmiiiiiceceeeeceeeeee
e
e e ee e e
ANSI/VTS2 MOAE .....ooiiiiiiiiiteeeteete
ettt ettt et e s aa e s e e s aae e sste e s saeenns
ANSWETDACK MESSAZE ....uuuiiieiiiiiiiieeeiiee
e e e e e e e e e eeeesereaseraaaaaes
AULO REPCAL ...t
AUt XON /XOFF ...ttt
e se e e e s b e e e srte e e s e aree e e ennnees
Bits Per CharaCter....ccc.uuuiiiiiiiiiiiieceeee
et
e e arar e e e e anees
Characters Per LINE ......ccoovieeeee
e eeeeeceecnerrereeree e e e e e e e e e e e e e e e sannes
CUTSOT ... ittt
eeeeeee e e e e e et eeeeeeeeesessssssssraerereeeeeeeseeeessssssssssssssssrerreessseeseesessnnns
INEETIACE ...t
e e e e e e e e e s e s enans
KEYCHCK TONE ...t
cee et e e e e aare e e e e s ens
LINE/LOGCAL ... ettt
e e e eearae e e e saae e s ssaaaeesessaneeeas
Margin Bell ..........cccovveeeeiinnnnnnnnn. e eeeetettetetettettttttt———————t————————at————aa————tta———————a——a————.s
LA
3 5 oUU

2-11

PaATIEY i
e e s s e s bbb aar e e e e s s e anbraaaeeeeenan
PATILY SENSE ..ottt
e e e e ee e sbaeeseeeese s ssssaasaeeeesesnnsssaneens
POWET ...t
s e s es
e e ee
renesennnnnnnnnnnn
RECEIVE SPEEA.......oeiiiiiiiiiee
et
e e e e ba e e s e rea e e s aenes
Screen BaCkGround ...........eeeiiiiiiiiiccceeee
e e ee ee

2-15
2-15
2-16
2-16
2-16

111

2-12
2-12
2-13
2-13
2-13
2-13
2-13
2-14
2-14
2-14
2-14
2-14
2-15
2-15
2-15
2-15

Screen Brightness........ccooooiiiiiiii
e, 2-16
SCTONL....eceiiiie ettt
e e e e s ab e e e s s s et e e e s se bt e e e e e e naaraaaeas 2-16
DS ittt
ettt ee et ee ettt et e ettt aan e aanaaanareanastnnrannaaannaanan 2-16
Transmit SPEEd ........ccoiiiiiiiiree
e
rrrreeeee e st e e s e s e e e e s naanes 2-16
WIAPATOUNA .....ooiiiiiiiiiiiieee et
e e re e e e eeecrae e e e e e nbaeeeeseeasbaeeeeesssnsaseeesan 2-17
Part 4 — Self-Testing the VT 100 ... et 2-17
SElf-TESt EXTOT COAES ..oenniiienniieiiee ittt eeteee e e eeee e e eteeseeeeaessesasesessnssssssnaesssannsesssnns 2-17
Part 5 -What ToDointhe Event of @ Problem......... ..ot
e eeee s eeeeeeareeeereessnnns 2-19
CHAPTER 3

INSTALLATION AND INTERFACE INFORMATION

SILE CONSIACTALIONS ...eeveeeieneeiiee et et et e et et eteeeeaneseanseeetnesennssssnssessseessnsnsstnnessesneseennsessnnssesnnesssnnnes
Unpacking and Installation............cccooiiiiiiiiiiiiiiii
et
ee e e e e e e e e e e e s
USET M aAINEEIANCE .. cenienieniiie ettt ettt et et et etae st st e taeseenseaseansenestnestnsssnnssnnsesnsmnnsensssnnssnssensssenssen
| X7 9 Lo Bed {0) w4 0 T:1 5 (o) « KOO
RPRR PR
BIA INEEITACE ..o ettt
et e e s e e e e e s e esanesenesenaanns
EleCtriCal CRATaCEIISTICS ouuuiinniiiniieieeeie
et ettt e teeeeiteeeeneetasesnesernessanesesnesennssens
VTI100 Output VOILAges........cuuvviiiiiiiiiiiiieiiiiniieiceieiiiirrerteeeeeeeeeeeesesssssnsasssnnnns
VTI100 Input VOItages ........ccooeiiiieiiiiiiiiiiircreceerereeeeeeeee
e
Optional 20 mA Current Loop Interface........c.cccceveieviviincciencciiicieeceeeee,
ExXternal VIideo CONMECLONS . .....c.iiuuiiiiiieeiee
ettt ettt et et s eeaseenestaseennnes
Composite Video Qutput (J9) ..ot
ee s e
Video INPUL (J8) .eeeiiiiiie
ettt ee s e seree e e e e e s s arenaeaee e s eseas

CHAPTER 4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.5.1
4.1.5.2
4.1.5.3
4.1.5.4
4.1.5.5
4.1.5.6
4.1.5.7
4.1.5.8
4.1.5.9

4.1.5.10
4.1.5.11
4.1.5.12
4.1.5.13
4.1.5.14
4.1.5.15
4.1.5.16
4.1.5.17
4.1.5.18
4.1.5.19

4.1.5.20
4.1.6

3-1
3-1
3-3
3-4
3-4
3-5
3-5
3-5
3-5
3-6
3-6
3-8

TECHNICAL DESCRIPTION
Introduction to VT100 Technical Description..........ccccceveieeeeeeiiiiniiiiiiiiiiiineeneenn.
SCOPE Of ChaPLEr ...coiiiiiiiiiiie e
ee e e e e e e s e e s eneeas
Order Of PresentatiOn.........cooeuiieeeiieeiieeeiee
ettt eeieeesnesereseaesenesennseennnes
Definition of Terms and ADDreviations .........coevvuevevuriieiiiinieiieeeieeiiereieerenns.
Hardware INtrOQUCTION .. ...eeeie ettt
ettt et st eean e enesenaeesaness
Block Diagram DesCrIPtion ...........uueviieiiiiiiiiiiiiiiiiiiieiceeeeeeeeeeeeeeeeeterreereenees
M I T OPTOCESSOT ...
iiiiiiirerretrr e eeee e e e e e e e e eer s rrebeeeeeeeeeeeesesessennses
Program ROM ...
eee e e e e e e e e ee e
Y&
2 100 11 SN\ OO
INONVOLALIIE RAM ...ttt
et s it e e
Advanced Video Option ........cccccuviiiiiiiiieeiiiiiiiieeeecieiererereeeeeeeeeeeeeneens
KeYDOArd .......oviiiiiiee
e
L DS et
e e st e st s e et e ea e e e rran s
Keyboard Translator ...........ooeivveiiieiiieeieereeteeeetcee
e,
TraNSIIL BUI
T . oottt
et e e e e b e s s eesan s

4-1
4-1
4-1
4-1
4-1
4-3
4-3
4-3
4-3
4-3
4-3
4-5
4-5
4-5
4-5

Current Loop Interface Adapter........ocoovviiiiiciiiiiiiiiiieicinniniiincennnne,
FIrmware INtrOQUCHION. .. ... veueieeiieieiieeeetee
et et erteerieernneersnerraneraneersnessnnnns

4-7
4-7

CommuniCation TTaNSIMUILLET .....oevnnieeniieeeeeineeteeeeeerieereerieerreeraeseaeen,
CommuUNICAtION RECEIVET .....eeeeeeeeeeeeeeeeeeee
ettt eereeserieeeraaeenes
N § 5O JS
O OO USROS RPN
CoNtrol FUNCLION PATSET ...oneeeeeieeieeeeee ettt e e e eeaeeraeennes
SCIEEN RAM ..ottt
et et eeaesesessanesrsesrnessaserasrresssnsesnessnns
VAACO PrOCESSOT .. eeeeeeeeeeeeeeeeeeeeaereterenestueetseeesnesssersansrnsesssersnerseesanersnnns
(@ 24 ALY [0 111 0o A UUTOOT OO
TR
POWET SUPPIY ..ottt
Standard Terminal POrt........coouuiiveiiiiiiieeeieiieeeeeeeireereeeeraeeeraeeenaans
| DA 2N 011050
o £ 1o PR

4-5
4-5
4-5
4-5
4-6
4-6
4-6
4-7
4-7
4-7

4.2
4.2.1
4.2.2
4.2.3

4.2.4
4.2.5

4.2.5.1
4.2.5.2
4.2.5.3
4.2.5.4

4.2.5.5

4.2.6
4.2.6.1
4.2.6.2
4.2.7

4.2.8
4.3

4.3.1
4.3.2

4.3.3

4.3.4
4.3.5
4.3.6

4.3.7
4.3.8

4.3.9
4.3.10
4.3.11

4.3.12
4.3.13

4.3.14
4.3.15

4.3.16
4.4

4.4.1

4.4.2
4.4.3

4.4.4
4.4.5
4.4.6

4.4.6.1
4.4.6.2
4.4.6.3

4.4.6.4
4.4.6.5
4.4.6.6
4.4.7

4.4.8
4.4.9

4.4.9.1

4.49.2
4.4.9.3
4.4.9.4

LY B8 0] 8] (0T R o) OO
OO
OO
BOB0 MICTOPIOCESSOT... .ceeeuvrreeeerreeenireeeseseeeresnseeseseessensesesesseeesssseesssssnessensees

4-9
4-9

Data Bus and System Controller ............ccooviiiiiiiirnneeirnnerrieeeenneieeee
e 4-11
ClOCK GENETALOT .....cceeeeeeeeeieiiiiii
s es s s sssessassssssssssassssssnasassasasasasens 4-13
BUS TIIMINE . .civiiiiieiieeeieeeeeeicceeeeceeeceereeerevaeeseeeeeeeeeeseeasennsssssssssssssssseeassasennsans 4-13
MiCroproCesSOr MEMOTY.....ccvvuuiueiiiireireiiiiiiretienirneeeeeeeeeeennnnnnaeeeseaseeaens 4-13
1\Y% (31410)
0281 - o JU O 4-16
MemOTY DEVICES......ccooiiiiiiiiiiieccrrerereeteeeeeeee e 4-16
ROM DeCOAING ...coeeiieiiiiiicccccerrscsress
e s sesessseess e e s e e s e s e s e e s eeaeneeenas 4-16
RAM DeECOAING ...cooveeereiiiiicceree
s eesseeseersee e s e e s s e e e e e e e e e e e e
4-16
Memory Disable ... 4-16
I/O DECOAING ....eeeeiiiieiiiiieeeeteeeete
et eeetee e eree e s eeesseneteseesrteesenaneesssnneens 4-17
PUSART Read and WTite ... 4-17
I/O Read and WIite........ccoooiiiiiiiiiiiiiiiiiinecinetccete
e 4-17
INEEITUPE VECIOT ...ttt
rse e e s s e e e e eeesaenananaasssannns 4-18
Power-Up and Self-Test ..ottt
e e eneeaeees 4-19
CommuniCation TTaANSCEIVET .........cccvviiiiiiiiiiiiiiiieeirieeiir
e sssessnsnns 4-20
PUSART PrinCIPIES ....cooiiiiiiiiiiiiiiiiiiiiccccciiinrreeteeeeeeeeeeesessseassesennssnsnnnsnns 4-20
PUSART OPEration ........ccceiiiiiiiiiieiiiiiiiiiieieseeeeeeeereinnnsesseeeeesssesesessesssssesssssnns 4-23
PUSART Addressing .........oovviiiiiiiiiiiiiiiiiiiiecccccccccccnrrevseeeesenseeeseeseeesseesssesns 4-23
PUSART Programming ............ceeieieireeeiiiiiiiiieieeeeeirieieeiieeeneereeseeessesessssessennns 4-23
Data TranSmiSSION ......cuuuuueeeiiiieiiiiiiiiiiiieeee
et eeeeeeeererrrereeeeeeseeeeasesssssnnnnnnnnnnnns 4-23
Data Reception................ eeetrerereteetteat..—reatieaeeeseesssesssaeesaeeseeeeeeteeeeeeeeeararaeens 4-27
Baud Rate Generator..........cccoooiiiiiiiiiiiiiiiiccccceeccccerecceeeeceeeeeeeeeeree
ee e 4-27
Serial INtErface..........cooiiiiiiii
e e 4-28
Modem Control.........cooiiiiiii
e srsese s e e e e e e e e e e e e e e e e e e e e e 4-28
1D 21 F T

Y o T OO
PO
PPPPRR 4-28
3 § 5O USSR 4-28
XON/XOFF ...ttt
sttt e s s sree s s sssaaeeesssneessssnsaaessnans 4-29
Control FUnCtion Parser...........cooiiiiiiiiiiiiiiiiieeeeeeeeveerereeeeeseeesesennnennananennnns 4-29
0Tz) R
PRRPRRR 4-29
Standard Terminal Port..............ooeevmmiiiiiiiiiccrrceeee
e eee e e e e e e e e e 4-29
Communication Self-Test ..........cooiiiiiiiiiiiiiii
e 4-30
KeYDOATA..... .o
ere e e e e e e e e e e e s e e e e e 4-30
Keyboard Block Diagram ............cooiiiiiiiiiiiiiiiiiccccccrrrrreereeeeeeeee
e s e eee
4-30
Keyboard UARTS......ccoottrttrtererteee
et ceeeese e
narae e aeeeee s 4-31
Keyboard Status Byte.......cccoovviiiiiiiiiiiiieeeeeeeeeeeevteeetreveevieeenreaesee
e
naaee 4-31
Key AdAress CoUNter........ccooviiiiiiiiiieeiicccccciireeeeeeceeenrrreee
e e ee
ssrreseeeesennns 4-32
Key Scanning and Address FOrmation .............ccccvveeeeeeeeiinnveeeeeeeeeeineinnneennee 4-34
Bidirectional Interface Operation.............ccccceeeeeeeiiiriieieeieeiiiieeeeeecec
e, 4-34
INterface LINE.........oviiiterereetereeeeeee e 4-34
ReCeIVING S1de......ccoiiiirrerree
e 4-34
Terminal Data Encoding ...........cccuumnnnmmiieviiiiiiieeeeeeecceeeeeeeeecaae, 4-37
Combined Interface Signal ............cooeeeevvivviviriieiiieiiiiiiieiieeeeenaae, 4-38
Decoding of Data from Terminal .............cccccvvveeiiiiiiniiiieieeeciieneeeeee, 4-38
Keyboard OUtput.........cooiiiiiiiiccreeecereee
e 4-38
Bell.. e
ee e
e e se s aab e e e e e e s enan 4-38
Keyboard Interrupt ROULINE........ccoceveniiiiiiiiiiiiiiiieeeeeeeeeeeeeeeeeeeee
e 4-41]
Logical Keyboard ProCessor...........ccccevveiieiiiiniriiiiiinirecnerecenreeeeeeeesseesennes 4-4]
Key RECOGNILION ...coeeiiiiiiiiieiceccccccctnrreeee
e ce s sareree e 4-42
KEY ROIOVET.....cciiiiiiiiiteieeceee ettt s s aare e e es s 4-42

Generation of Codes.......cccevvviiiiiiiiieiccireeceeccee
e 4-43
Keyboard Transmit Buffer.............ccoovvvveeeiiiiiiiieeccceccreereeeeeeeeas 4-44

4.49.5
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.6
4.6.1
46.1.1
4.6.1.2
4.6.1.3
46.1.4
4.6.1.5
4.6.1.6
4.6.2
4.6.2.1
4.6.2.2

46.2.3
4.6.2.4
4.6.2.5
4.6.2.6
4.6.2.7
4.6.2.8
4.6.2.9
4.6.2.10
4.6.2.11
4.6.2.12

4.6.3
4.6.3.1
4.6.3.2
4.6.3.3
4.6.3.4
4.6.3.5
4.6.3.6
4.6.3.7

4.6.3.8
4.6.3.9
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9
4.6.10
46.11
4.6.12
4.6.12.1

4.6.12.2
4.6.12.3
4.6.13
4.7

AUtO REPEaL ... 4-44
INONVOIALIIE RAM ..ot
e e e et e e e st e e eeaaaeseann 4-44
PIINCIPIES ..o 4-44
INVR DEVICE ..ottt
e e ee
s e s ee ee
s 4-45
YA
S O]
115 (o) SRR 4-45
N
28] 150)
070 o A G5 0 (1 1 3 £ S 4-46
Microprocessor Management .........ccouuuueiiiiiiiiiiiiinen
e
eee e 4-47
INVR TIMINE .coieiiiiiiiiieeiiceeceeeeeeee
e eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeereereeeeeaeereeeeeasaraaa, 4-47
AY4T0 (1030 & (0 16T o) RO 4-48
| 5018 070 11 1o 5 (o)« REUUR TSR
TRRPRRR 4-48
The RaASEET ..cvveeeiiieeeeeeee
e
e e e e e e e 4-51
Character FOrmation ........cooovviieeeiiiiiiiicieeeeeeeecceeceeeeeree
e 4-51
Vi1deo Processor Data .......cooouvviiiiiiiiiiiiiieiie
et eee e 4-52
Video Processor Character Generation...........cooovvvveeeiviiiiieeeevinneeneennnnnns 4-52
ABETIDULES oeeniiiiiiiieeeeiee
e e et et ee st e rabeeraaessaanesannes 4-52
Advanced Video Option (AVO) ... 4-54
Timing Chip DeSCIIPION c....eeuuueiiiiiiiieeieiiiiieeeenereeeeeeer
e eeeeeeee e eeeee 4-55
INPUt DECOAET......ooiiiiiiiiieiee
ee
e e 4-55
80/132 Column Selection.........c.ccovuevvviiiiiiiniiiiiiiiiiiiic
e, 4-57

| 2o A O0]
11 4 113 SHU 4-57
Double-Width MultipleXer.........cooooreee e, 4-58
HOTZONtAl COUNLET.....ccoviiiiiiiiicieeeeiieeeeeeeeeeeee
e
e e e 4-60
Horizontal Drive and Horizontal Blank ...........ccoeeeeiiiiiiiiiiiiin. 4-60
Line Buffer Addressing ..........ccoooviiiiiiiiiiiiiiiiiiiieiiieerrcreeecereeceeeereeeee 4-60
Vertical OPeration.......c.cccccuiiieerieeiiiieeee
et e
e eerreeee s eernrteee
4-64
VeErtiCal COUNLET ......iiieieiiiiiieeeeeeiiee
et eeereeeeeerrt e e eeraraeeeesaaaaeneaens 4-64
VertiCal OQULPULS ... .oueiieeiiiiiteeee ettt
ee e eenrree e s einneeee s 4-64
COMPOSILE SYIIC ....uvviiiiiiiiiieeeeeteee
ettt ereee e eenr e e s sasae s ssnas e e 4-67
Hold Request, Address Load, and
DOoUDBIE-WIAth ....ccovviiieeiiiiiiiicccceec
et
eree e e e e e e e e e e e e aeeeaeeaeaaaas 4-67

Control Chip DesCriPtion..........ceeeeeeiieiiieeereriiiirteiriee
e 4-67
Input Decoder FUNCLIONS..........coooceeviiiiniiiniiiiiiiiieciece
e, 4-70
AIIDULE LAtCRES c.uvieieeeieiieee et
e eer e e 4-71
SCIOIl COUNLET ....covvvniiiiiiiiiiieeeeeeetiiereeeeeeeeteieeeeeeereesassaeessessesssssnssasees 4-71
Scan Count Math .....coueeeiieiiiiiiiiiiieieee
e eeeraa e e eeea e 4-72
Generation of HOLD REQUEST ..., 4-72
Horizontal Blank and Terminate.........ccoovvevuneiieiiiiiieiieeeeeeeeceveeneeeeeeen 4-73
Double Width and Hold Request ...........ccooiriiiiiiiiiiiiieiieeeeeen 4-74

ATETIDULES ceeveeeeiiiiiiiicieeeeriiiiieeeeererrtsnereeeeetenareansssseseersssnnsessesserssssmsnness 4-74
D L0 1A 1 0 (=111
(= U
PR UPPPPPRPPPPPPPPN 4-74
Address Counter and Data Structure in RAM ..., 4-74
Address LatCh Buffer ......cooueviiiiiiiiiiiiiieeeeeeceeeeetrce
et serrrae s s ee e 4-77
B0 2 100 3 (= PO
U
PPPUOPPRRR PP 4-77
Character GENETALOT . .....cceuuuieiieeereiieieeeerrrerrneereeeernrrreneeseeeeeeremnsssesseesesssnnnnnnss 4-77
Video Shift REZISIET ...cooeeeireeiecireee et 4-80
O TIMIMALOT .ceeeeeeeeeeeeeniieeeeereraeeeeerrrannneaeeeeeersssssnssaseeeerassssssnsssesnesesnnsenssssessnnnns 4-80
e 4-80
DMA Cycle Timing Diagram.........cccccovuiiiniiinniiiniiiiiiiiiii
e 4-82
Video Blanking ......oooeeeiiiiiiiiiiiiiieeeeeccctttrrrne
e, 4-83
Video Input and Qutput........ccccceveiiiiiiiiiiiiniiiic
eenee 4-83
s eeeeeneseseeeenneesesennneess
DIreCt DIIVE VIO ...ceveeeiiiiiiiieetiieeeeeretceeeee

e 4-84
Composite Video Out ..........ccoviiniiiiiniiniiiniiiicie
et eeetereteeeee e eeeeeeeereraessannn i eseseesaeaeeessaesesnnnnssssssssssnsass 4-84
VAACO LM
et 4-84
ereeeiiiiiiii
Intensity CONLIOL.......ccceereeie
Microprocessor — Video Processor Interface ..o 4-85
vi

Screen Memory Organization...........ccceevveeerveeenenieinniiiennneenniicenecceaee
e, 4-86

iieeiiie 4-87
ettt cenreeeeresesasessaeeees
Fill Line OPeration ........coeeeueeeereiieeniiiieiiiiiiii
s 4-88
e s e siaaeaen
e
enrra
e
ceiiree
iiiiiieeniiiiiiii
it
Line Organization.......cccceeeieeeeian
Physical SCreen ........ooociiiiiiiiiiiiiiiiiiiinr
e 4-92
LOZICal SCIEen....cciieeiiiiiieiiiiiieeetee et 4-92
Address ShUffling ........oovveiiiiiiiiiiiiiie e 4-92

Shuffle TIMING......cooiiiiiiiieee ettt 4-94
Scrolling ReGION ......ooooiiiiiiiiiii
e 4-95
Split Screen Jump SCrolling .........ccoovvvviiieiiiiiiiiiiiiiii
e 4-95
SMOOLH SCIOI] ...eeeieieeeeeee
et
e e e e e e e eeereneans 4-95
Split Screen Smooth Scrolling.........ccccveiiiiiiiiiiiiii, 4-97
CUTSOT «aiiiiieiieeeeeeeeeeeeeeee
e ettt eeeeeeeeeeeeeseeseesaasaaaaassssssssasseeeeseneeessnnnnnnnnnenssssees 4-98
SET-UDP ..ottt
e et ra ettt b s be e b e e sesssesesessenensnnns 4-99
1LY (o) ¢ V1 1) (PP
PP PSR O R PP P PR OO RPP 4-99

> ARABEDAD
oo 90 90 00 90 00 90 00 90

4.8.

4.8.2.1
4.8.2.2
4.8.2.3

4.9

4.9.1
4.9.2

4.9.3
4.9.4
4.9.5
4.9.5.1

4.9.5.2
4.9.5.3

DY =

L
R
b —

CHAPTER 5§

5.2.4

5.2.5
5.2.6
5.2.6.1
5.2.6.2
5.2.6.3
5.2.6.4

Monitor Description: 30-16080 (EISton).........cccceiiiriiieiiieiiiiiiiiininiiinnana -100
VIAEO DITIVET ...ttt
ere e e e e e eerea e as e e esaaeseesaseees 4-100
133 §1ed 118 4 (11 SO
PP PP PPUOPPRRPRPPPRRPRPRRR 4-100
Vertical OSCIlator ... ...oovvviiieiii
e
e4-100
Self-OsCIIAtION ......cccoiiiiiiee
e eeeeaees 4-100
Vertical QULPUL .oooveeee s
e e e e e e e e e e eeeees 4-100
LINCATIZAION ouuiueiieiiiiiie et
eeeticee e e e eeeeeraaae s e e e eeeaaaaeesesseeennennnns 4-101
HOrIZONtal DIIVET ..o
e e e e e e eaaaaes 4-101
Horizontal Deflection Operation.............uueeieeiiiiiiiiiiiiiiiiniiicreeeeeeeenad -101
Horizontal Qutput CirCult..........covvveiiiiiiiiiireiieiierieeeeeeeeeereeerreeereeeee.—.— -103
High Voltage and FOCUS ...........cooiiiiiiiiiiiiiiiiiiiceceeerreeeerevveeeeeeeveeeee
e -104
Monitor Description: 30-14590 (Ball)........uiccecced -104
Video AMPITICT....cciiiiiiiiiiiiiiiiiirrrrerereereeerer
e saeaees 4-104
Vertical DefleCtion ..........coiiiiiiiiiiiccrrrrre
e 4-104
Horizontal Deflection..........ccoooiiiiiiiiiiiiieii
e 4-105
| VL S BN 110 0) o] | A
RRRRRPPPPPRRR 4-107
POWET INPUL .
eee et
e s s e s e s e e e e eeaans 4-107
SATt-UP CITCUIL...ciiiiiiiii
e
eereee e e rreeee s e e aaae e e s eeanneseaannns 4-107
(000115
o) G5
§ 11 5 | S U
RPTPURR 4-108
OULPULS et
ree s e e e e e e eeeeeeeeesanssnnnannnneaeaseaeaeaeeeens 4-110
Power Supply SpecifiCations ............coouviiiiieiiiiiiiiiiieeeeeeeeeeeee
e 4-112
Input SPeCifiCatiONS.......uuuuvuiiiiiiiiiiiiiccc
e 4-112
COOLINE. ..ot
eeeeeeeeeeeeeeseeeensssnaaanans 4-115
Base Product Power ReqQUIrements .........ccccceeeeeiiiiieeiiiieeieiecceeannn -115
VT100 SERIES SERVICE

INEEOAUCIION ..eeiiiiiiiicceeeee et eeeeeeeee e eerbaare e e aasaaarassaasssassseesssareees
TroubleShOOtING .....cooeiiiiiiieeeeeeeeeeee
ee e e e e e e
Troubleshooting the VT100 with Self Test......... teerereeeeereeeeeeeeeeeerererrtrrrarna————_,
Troubleshooting Basic VT100 Variations
Without Self Test......uuieiiiiiiieeeeeeeeeeeeee
Troubleshooting the VT10S5 ...
Troubleshooting the VT 132 ..ot

5-1
5-1
5-1
5-3
5-3
5-3

Troubleshooting OPLIONS.........ccevviiiieeiiiiiiiiieececreee
e 5-3
VTI100 Internal Self Tests .......cccoimrriiiiieeiiiiiiiiieeeecee e,
5-8
POWET-UD TSt ...ttt
errrerreeeereere e areaaraasaasaees
5-8
Data Loopback Test ........coeeiiiiimiiiiiiiiieiiiericiieeeeee
s reeccrrtree e e
eveneees 5-10
| O 7 N =) AU 5-11
Video AdJust Test.......cooiiiiiiiiiiecccceeee
e e e e e e e e e e eeeeas 5-11
Vil

(W,|

RPN
N

GO ULWBAWN—=

VIRV
A WN—

WWLLWLWWLWWWNNNNNNDNDNDD
=

L
nanlines PLLLLVWLLVLLLLLLLWLWWLWWWWWNN

5.4.3

5.4.4
5.4.5

5.4.6
5.4.7

5.4.8
5.4.9
5.4.10
5.4.11
5.4.12
5.4.13
5.4.14

5.4.15
5.4.16
5.4.17

5.4.18

5.4.19
5.4.20
5.4.21

5.4.22

W N

LA
L L
NN

5.5

SET-UP SCreen TesSt .....ccceeiiiiiiiiiieiiiieiieeieeeeeeeeee
e, 5-12
EITOr COAeS. ..ottt
e e ee e e e e ee et ra e e e aeee s 5-12
Video ALIGNMENt ...oooiiiiiiiiee ettt e e et e e e e s e e e 5-12
GENETAL ...
e 5-12
Monitor Adjustments (Ball Brothers).........ccoocooimiiii, 5-15
Brightness ....cooooiiiiiiiiiiiiiiiieeere
e 5-15
FOCUS. ..
e e 5-16
YOKE ROtAtION.......couiiiiiiiiiiiee
e
e, 5-16
Vertical Height........o.oiiiii

e, 5-17

Horizontal Width..........ccooiiiiiiiiiii
e, 5-18
(@13
1175 ¢ | 11 OO 5-19
Vertical Lin@arity ......ccoeeiiiiiiiiiiiiiiciiee
e
e e e eeeer
s 5-19

Horizontal LiNearity.........coeeeiiiiiiiiiiiieieeecceee
e 5-20
VertiCal HOI ... 5-20

Monitor Adjustments (EIStOn) ..........cccooeeiiiiiiiiiiicce e,
BIightness ...
FOCUS. ..ottt
e e et s e e e e e e aa e e e e e e e eaaaaas
YOKe ROLAtION.......coviiiiiiiiiiiieieeeeceeee
e
e e

5-21
5-21
5-22
5-23

Vertical Height......ooooeeiii e 5-23

Horizontal Width. ..., 5-24
Centering.......cccceeeeeeeee.e. eteeeeeeeeteetertettt—————————aaeetetererrrrrarrrr———————aas 5-24
Vertical LINCATItY .....ouvvuuiiiiiiiiiiieeeieeeeeeeeeeeeeee
e eeee e e eeae e 5-25
Module Removal and Replacement...............cooooiiiiiiiiiiiiiiiiirerrecerreerevee, 5-26
GENETAL ...t
e e s e e e e e s ee e r
e e e e e aeeeeeaeees 5-26
ALCCESS CCOVET ..iiiiiieiiiitiieeeeeeeee
ettt tteeae e e e e e e e e reeatssaaaaaaaeeseaaeasersesesssnnnnnnnassas 5-26
Terminal Controller Board ............oovuiiiiiiiie
e 5-26
Advanced Video Board...........cccooomiiiiiimiiiiiiiieiieeeeeeee e 5-26
VT105 Waveform Generator Board .............oiiiiiiiiiiiiicieee
e, 5-28
20 mA Current Loop Board..........cooooiiieeee 5-30
Keyboard Top CoOVer......coo
ittt ettt ee e
e e e e e s eiiiereneeeee e s 5-31

KEYDOATA ...t 5-31
Keyboard Cable..................... ett
e eeeeeeeeeeeeeeeer——————————aaeeeeeeertrtrartranaaaaeaaes 5-31
Keyboard Speaker ................. eeeeeereeeeeeeeeeeieseeseseeeesessseseessstetttrttetteteeeeaeeeeeeaaans 5-33
Terminal TOP COVET......uueriiiiiiiiieirieeeeeeeee
ee e
5-33
Video Monitor Board (Ball Monitor)..........cceeeeieiiriiiieeeicee
e 5-34
Flyback Transformer (Ball Monitor)..........ccccoviiiiiiiiiiiiniiiiiiinene, 5-36
Video Monitor Board (EIStOn) ..........ucoeiiiiiiiiiiicieeree
e 5-36
Flyback Transformer (EISton) ...........cccooociiiiiiiiiiiiiiii
e, 5-38
Terminal BottOm COVET .......ouvviieeiiiiiiiieee
e
e eeeetbe e e e e eereennaes 5-39
POWET SUPPIY ..ttt 5-39
VT100 DC PoWer HarnESs....coovvueiieiiiieeeeeiieeeeeetieee
e eeeeiiee s e ereeiee s eeeeaneeeeeeennes 5-41
VT105 DC POWET HAINESS....u.ciiiiiiiieeiiiiiieieeeeeeeeeeeeeeeereeeese
e e eeeeenaneeennannees 5-42
VT105 Expansion Backplane Removal and
INSTALIALION coeeviiiii it
e ettt e e e s e e ereea e e e e e e eebb e e s e eaaaaaas 5-44
Field Service CRT Monitor Assembly ..........ouiiiiiiiiiiiiiiiieeee, 5-44

CRT Storage and Disposal ..........ccccooeriiieiiiiiniiiiiiiiiiii
e, 5-45
Board ConfigUurations ...........ccccuiveeereieeeeerneiieeeeninteseiieee
et ce esnae e erree s eraaee s 5-45
Terminal Controller Board ...........oovvuiiiiiiiir
et 5-45
Advanced Video Board ...........ooeeiiiiiiiiiiii
e 5-46
VT105 Waveform Generator Board .............ooviiiieeiiiiiiiiiiiiiicieee, 5-46

Component Level Troubleshooting ..........cccccooviiiviiiiiiiie 5-46
. 5-46
Troubleshooting the Terminal Controller.............cccoovvniii
MICTOPTOCESSOT ...eeeeeiniiiirieeeeeeeiiiteeeeerirtteeeesirrar
saabe e e e e abare e e e enaes

viil

5-50

VA0 PrOCESSOT . .ccvviiiiieiieieeeeteerccee
e eeeeerere s ss e e s e e e e e e e e aaass e s 5-52

COMMUNICALIONS .. .uuuuvririrrrreeeereiereeeiinrrrereeeesesresssssrrsereesssssesssssssssseeseees 5-33
Nonvolatile RAM ... 5-54
Troubleshooting the Keyboard .............cooiiiiiiiiiiiiirrereere
e 5-54
Troubleshooting the POWer SUpply .......ccceeeiiiiiiiiiiiiiiieieeeicceereeee
e, 5-54
Troubleshooting the CRT MoONItor.........ccoooviiiiiiiiiiiiiiiieccccceerreee
e, 5-55
Troubleshooting the Options..........erreeeeree———etereraereeetetatatteeereeasesanananrrrnrnrnnes 5-56

WWWWWWwwWwwwwwww
—

=
NN BN
I
O 00
—— =
N — O

N
W

=AN=ANE) N

Np—-fi.._np—tp——a.—ap—tp—a.—a;—a.—ip—u;—-fl.—ay—ay—ap—a

CHAPTER 6

6.2.4
6.2.4.1

6.2.4.2

6.2.5
6.2.5.1
6.2.5.2

6.2.5.3

6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.4.1
6.3.5
6.3.6

6.3.7

6.4

6.4.1
6.4.1.1

OPTIONS
SET-UP Procedures for VT100 Series Options...........ceeeeeiiiieieeiiiirinenienniinieeciennnes
VT100-WA and VT100-WB SET-UP ..o,

6-1
6-1

VTIO0S SET-UP .ttt
e seeee e e e e e s e e ee e ee

6-2

VTI32SET-UP ...ttt
e ee e e e e e s e e e e e e

6-2

VTI32SET-UP A ...ttt
ettt e e e s e e e aavreaa e e e e e aens
VTI32SET-UP B.....oettrttrreeeteeeeee
et e e s e e e e e

6-2
6-2

VTI32SET-UP C ...ttt
eerrrtte e e e e s e enaaaeee e e e e e

6-2

Changing a VT132 SET-UP Feature ...........cooooiiriiiieiiineiieeeeeeeeees
Setting the VT132 Answerback Message.............oceeeveeiiiiiiiiiiiiniiinnennnee.
Setting the VT132 Transmit Parity......ccccoooivviiiiiiiiiiiiiiiiiiiiierneeeennee,
Saving VT132 SET-UP Features .........cccooviiiiiiiiiiiiiiienccceens
Recalling VT132 SET-UP Features..........ceeeeeeeeeiiireeeeiiiceeeeeeeeeeeeeee,
VT132 Default Feature Settings ..........coovvvuieeiieriiiiiiiiiicciccceeeeeeeeeeeee,
VT132 Tab Default ...t
VT132 General Default.............oooovvimiiiiicceeeeeeeeeeeeeeeeeeee
e,

6-2
6-2
6-6
6-6
6-6
6-6
6-6
6-6

Resetting the VT 132,
e e 6-6
Advanced Video OPtion........c.cccccuiiiiiiiiiiiiiiiiieeeeiereeeeeeeeeeseeseseeeesssnneersrereseeeeesseees
6-6
Advanced Video Option Installation ............ccccceveeeeeiiiiiiiniiiiie, 6-8
Advanced Video Option Checkout ..........ccccoovviriiiiiiiiiiiiiiiiniireeece
e 6-8
Program Memory EXpansion..........ccoooiiiiiiiiiiiiiieeirieee
et eeeevvee e 6-10
Alternate Character Set ..o 6-11
Alternate ROM DesCIription.........ccouuiiiiiiiiiiiiiiiiiec
et
eeeeeanee
6-11
Character ROM Programming
INSEIUCHIONS ...cceeiiiieieiceeeeceeec
e e e e e e e e e e e e e e 6-12
AVO Technical DesCrIPtion ............cooceiiiiiiiiiiieeeecccccereee
e ceerrreee e 6-12
Extended Character and Attribute
1\ (310
16) o AU
U SRR
PRP 6-12
Character Attribute Latches............cccooiiiiiiiiiiriiiees 6-13
Program ROM Decoding .........ccoooniiiireeerreeeeee e 6-13
Troubleshooting the AVO ..., 6-13
20 mA Current Loop AdapPter......cccoiieiiiiiiiiiiieececeeeeeeceeeeeeeeeeeeeeeeeeeeeree
e 6-13
20 mA Current Loop Option Installation ............cccccovvvvvrriiiriieieiiieniiieieeennnnn. 6-13
CONFIGUIALIONS ...oeviviiiiiiiiieiieeeeeieeeeeeeeeeeeeeeeeeeeeeeeeeere
e e e reeaereeaaa b e aaaaanaaaan 6-14
20 mA Current Loop Option Checkout .........cooeceiiiiiiiiiiiiiieieeeecciieee
e, 6-15
Current Loop PrinCiples ........ccvvviiiiiiiiiiiieeeeees ettt 6-15
Current Loop Adapter DesCription .............eeeeeeeeeveeiineeeeieeeeeeiieinenneneee. 6-15
Interface SigNals......ccccovviiiiiiiiiiieee
e 6-17
Interface SPeCifiCatiOns..........cccviiiiieiiiiiiieccreee
e
e e e 6-17
Troubleshooting the Current Loop Adapter.........cccceeeeevvvereiiiicciieieeeeeeennne, 6-18
VTI10S GraphiCs ProCeSSOr......ccciiiiiiiiriiiireiieeee et
e e e 6-18

Enabling Graphic Information ............ccceieiiiiiiiic
Writing Data to the Waveform

e 6-18

(€121
153 ¢ 1 ¢) SUU SO
UUUOPUPPRPR

6-19

6.4.1.2

6.4.1.3
6.4.1.4
6.4.1.5
6.4.1.6
6.4.1.7
6.4.1.8
6.4.1.9
6.4.1.1
6.4.1.1
6.4.1.12
6.4.1.13
6.4.1.14
6.4.1.15
6.4.1.16
6.4.2
6.4.2.1
6.4.2.2

6.4.2.3
6.4.2.4
6.4.2.5
6.4.2.6
6.4.2.7
6.4.2.8
6.4.2.9
6.4.2.10

CHAPTER 7

Reading Data from the Waveform
L€ 153115
21 10 U 6-21
Decoding the Input........cooooiiiiiiiiiiiiiee
e, 6-21
Selecting Mode of Operation ............ccceeeiieiiiiiiiiiiiiee, 6-24
Decoding Field Selection.............ccooovvviiiiiiiiiiiiieeeeee
e, 6-25
Phase Lock Loop Timing.........ccoooveveiiiioiiiiiiiiieieeeeeeeeeeeeeeeeeeeeeee, 6-26
Establishing Desired Display.......cccooeeeeeeeeiiin 6-26
Loading X-Address Information ............................coc 6-30
Loading Graph MEemOTIES .........ccccvvmiiiiiiiiiiiiieieeeeeeeeeeeeeeeeeeeeee 6-30
Generating Baselines (Shade Lines)...........ccooovveeeeeiiiiiiiiiiiiiiiieeeeee, 6-32
Enabling a Histogram (Shading a
GTaAPR) oo, 6-32
Loading Vertical Lines.............ccccoiiiiiiiiiie
e, 6-32
Adding Graph Marker...........iiiiiiiiieeeieeeeee 6-36
Generating Horizontal Lines.........ccccoooeiiiiiiiiiiiiiiiee
e, 6-36
Generating Strip Charts .........oooooiviiiiiiiii
e, 6-36
Combining Video Out and Timing ............c.ccccooe 6-41
VT105 Graphic Test Procedure.............ooooivviiiiiiiiiiee
e 6-43
B S AT L U o T
SO
U PP PP PP URPPPUUUUURRR 6-43
Test Graph 0, Histogram 0, and Graph 0
MATKETS oo
e et e e e e e e 6-44
Test Graph 1, Histogram 1, and Graph 1
MaATKETS e
et e e 6-46
Test the Horizontal Lines.............coieeieiiiiiiiiiicieee e 6-46
Test the Vertical Lines ...........ooeviiiviiiiiiiiiii
e, 6-46
Test Shade Line O (Baselineg 0).......c.ooovvuvueeeiiiiiiiiiieee
e 6-48
Test Shade Line 1 (Baseline 1)......cccoovvvviiiiiiiiiieiiiiiieeiie
e, 6-49
Test Strip Chart O. . co v ei e ie e 6-50
Test Strip Chart 1. e, 6-51
Exit the Graphic Test Mode.......ccooeeeiimieeiiiii, 6-51

STANDARD TERMINAL PORT

7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.2.1

| 118 (076 L) (o5 10 ) o KOS
TPPPPP
Definitions........cccccoeeerreviiiiiiinnennens eteeeeeeeestesseaeeeeetteesnaaaeeetertrraiaeaattterranaaaeraeeees
OVEIVIEW ..o, eeeeeetertteteeeeeeeretran—aeeeeererttt—aaaeeearrtraaeaeeearrnnans
Functional SpeCifiCations..........ccooiiiiiiiiiiiiiiiiiiiii
e e
Interface Signal Lines.........oouvieiiiiiiiiiiiiiiiiiii
e
Protocol SpecCifiCations ........ccccuueiiiiiiiiiiiiinee
e
Terminal Operation With No Option
Present............ ett teeeaeertaeeteertetateetaeeteaareetteetaeataettaatteeraaareannns

7-1
7-1
7-2
7-3
7-3
7-6

7.4.2.2
7.4.2.3

Standard Set-Up For Local LinK.........ccccooiiiiiii,
Control Sequences For Terminal
| 20 00 111 1<) o TR PSSP
P PP PR

7-6

7-9

7.4.2.4
7.4.2.5
1.5
7.5.1
7.5.1.1

7.5.1.2

7.5.2

7.5.3
7.6

INItIAlIZATION cevvveeiiiieiie et
e e et e
BREAK... ettt
s
Electrical SPecifiCations ...........coouevuiiiimiiiiieiiiiiiiiii
e,
SIZNAL LINES ..ovviiiiiiiiiiiiieiee ettt
Signal Levels ......ooiiiiiiiiiieeiiiiieei

SigNnal TIMING ...ooeiiiiiiiiiiiiciiiii

7-6

7-7

7-9
7-9
7-9
7-9
7-9

iicccecc 7-10
Power SUPPLY LINeS ..cc.uvveeeiiieeiiiiiiiiiiciiicie

ConneCtor PINOUL .......ovvviiiiiiiiieeeeeee
e 7-10
Mechanical SPecifiCations ...........ccceeiiiiiiiiiiiiiiecieeeeceeeeeeeeee
e 7-10

7.6.1

7.6.2
7.7
7.7.1
7.7.1.1
7.7.1.2
7.7.2

Shorting ConneECtOr......ccouuieeiiiiiiiiie

STP Connector Card .......cooveeiviieiiiiiiiieee
e
Guidelines for the Designer .........ccooooeiiiiiiiiiii
e,
Use with Receive Only Device ..........cceeeeeeeiiiiiiiiiiiceeeee,
Single UART Method ...,
Two UART Method ..o,
Use With Passive DeviCe ......ccoovviiiiiiiiiiiiiiiiiiiiee
e,

7.7.3

Use With ACtive DevICE ....c.uuiiiiiiiiiiiiiiieeee

7.7.3.1
7.7.3.2

7-11

R A&

7-13

Terminal Processor as Standalone CPU..........................
Terminal Processor Augmenting Basic

oooooooooooooooooooooo

Terminal Operation.......ccccceeeeeeiiiiiiiiiiiiiccciceee
e,
7.7.4

Use With Communications Option..........cccceeeeeeiiieieereeeieeeeennnnn.

7.7.5

Use With An External Processor.........ccoocoeeevviiieiiiievieeeenennnnnn.

7.7.6

Use With More Than One Option ...........cccoceeeeeeieeeiiiiieereeennnnnnn.

8. 1
8. 2

Hardcopy Enable ...

APPENDIX A

PROGRAMMING INFORMATION

APPENDIX B

RECOMMENDED SPARES LIST (RSL)

APPENDIX C

GLOSSARY OF TERMS AND ABBREVIATIONS

oooooooooooooooooooooo

FIGURES
2-1

VTI100 Keyboard.........ooovviiiiiicceieeeeeeee,

2-2

VTI100 Terminal (Rear VIEW) ....cccovvviiiiiiiiiiiiieeeiceeeeeeeeeeeeee

2-3

SET-UP A Mode Presentation............ccoueeviiiiiieiiiiiieiiiiececeeeeeeennee,

2-4

SET-UP B Mode Presentation........cccooeeeeeeeeeeeiiiiinii.

2-5

SET-UP B Mode SUMMATY .....ccoooieeiiiiiiiieieeeeeteeeeeeeeeeeeeeeeeeeees

3-1

VT100 Terminal DImensions .........uueceeiiiieeiieiiiieeeeeeeeeeeeeeeeeeeeeeeeeeee,

3-2

VT100 Rear VIEW coovviiiiiiieieeeeeeceee

oooooooooooooooooooooo

3-3

20 mA Current Loop Interface.............ccccociiiiiiiiiiiiiiiiiieeeee,

3-4

Composite Video Output........cccooeeiieiiiiiiiicccereeeeeeeee
e

4-1-1

VT100 COMPONENLS .....uuvviiriiiririiiiiiiiiiiiiiiiriererereeeeeeeeeeeeeeeesesesenennnenns

4-1-2

Functional Block Diagram .........ccccooovvvviiiiiiiiiiiiniiiiiiiiieeeeeeee

4-1-3

VT100 Firmware Block Diagram.............cocoovviriiviiieeeieiiiiiieeeeeeen,

4-2-1

8080 Block DIagram ........covvvveeveiiiiiieieieeieiiiiiiee

4-2-2

Microprocessor Block Diagram ............cccovvvvvevieeeiiiiiiiiiiiiiiiiinnneee,

4-2-3

Microprocessor Bus Timing ..............evvvvviiveeeiiieieieiiiiiiiiiiiiiieennnee,

4-2-4

MEMOTY MAP i

4-3-1

8251

4-3-2

Asynchronous Data Format ..............ccccccvviiiiiiiiiiiiiiiiiieeeeeee,

4-3-3

Mode INStIUCHION.....ccciiiiiiiirireeeeeeee

4-3-4

Command INStrUCtION ........cooiieieiieeec

4-3-5
4-4-1

Status Byte Format ..........cooovviiiiieii
e
Keyboard Block Diagram ............ccccoovvviviiieiiiiiiiiieeeeee e

4-4-2

Keyboard Status Byte ........ooooveeeeiieeeeeeeeeeeeee
e

4-4-3

Key Address Transmission Delays............ccccccooveeiiiniiiiieieiiiiinnnnnneee.

A PUSART Block Diagram............ccceevvvvvveimmeeieenannns

oooooooooooooooooooooo

ooooooooooooooooooooo

oooooooooooooooooooooo

ooooooooooooooooooooo

oooooooooooooooooooooo

.....................

......................

oooooooooooooooooooooo

4-4-4

4-4-5A
4-4-5B
4-4-5C
4-4-6
4-4-7
4-4-8
4-4-9

4-4-10
4-4-11
4-5-1
4-5-2
4-5-3
4-6-1
4-6-2
4-6-3
4-6-4
4-6-5
4-6-6
4-6-7
4-6-8
4-6-9
4-6-10
4-6-11
4-6-12
4-6-13
4-6-14
4-6-15
4-6-16
4-6-17
4-6-18
4-6-19
4-6-20
4-6-21
4-7-1
4-7-2
4-7-3
4-7-4
4-7-5
4-7-6
4-7-7
4-7-8
4-7-9
4-7-10
4-7-11
4-8-1
4-8-2
4-8-3
4-8-4
4-8-5
4-9-1
4-9-2
4-9-3

Keyboard SWItCh ATTay ......ccoooviiiiiiiiiieiie
e 4-35
Keyboard Interface CirCuit..........ccooeeiivuiiiniiirieiiececee
e 4-36
Bias Network — E8 High ......coooiiiiii
ettt e e 4-36
Bias Network — E8 LOoW ..cciviiiie
e 4-36
Encoding of Terminal Data and Clock ...........cccovviiieeviieiiiiiiiieeeeee, 4-39
Four Keyboard Interface States .........ccoovueiiiiiiiiiiieiiieee
e, 4-40
Keyboard Interface Signal.........c.coccooviiiiiniiiiie 4-40
BEll CATCUIL.....cciiiieiiiiieeecccee
e
ettt e sssatb e e e e s e e seneeeeeaean. 4-41
KeyS FIag Byte....coonnnniiiiiiiieeeeee
et
eenaee s 4-41
SNEAK Path ...ttt
e e e 4-43
ER1400 NVR Block Diagram ........ccccueieieiiiiiiriiiiireee
e
ceeeeveeee e e, 4-46
INVR SIZNALS ...ttt
et e s esbe e e s sanra e e e 4-48
NVR Timing Diagrams.................. eeeeteeseseeeteeeerereetterttann—————eeeeeerrrrrarrtrtann——————oos 4-49

Video Processor Block Diagram.......... e eertreeeeeeeeeeeeeetrrarrtra—————————————aeettertrerarrannnana, 4-50
Dots, Scans, ANA CRATACLETS ..........iiiiiiiieieiieeeeeeee
ettt eeeeteeeeeeerteeeeesesnnaaesens 4-51
Video Processor Functional Diagram..............cccccovviiieeieeeiiiiiiiiiiiiicereeeeeeeeeeen 4-53
Character Generator EXample...........uuueiiiiiiiieieiiieeiieeeeeeeeeeeeeeeeeee
e 4-54
DCO011 Block Diagram..........ccccc...........ett tterer——————aeeeeeeteereeerrrrarta———eeeaeeerrrrrarns 4-56
Video Latch Timing — 80 Column..........c.coooiiiiiiiiiiieeeeee
e, 4-57
Video Latch Timing — 132 Column.......ccoooviriiiiiiiieeeeeeeeeeeeeeeeee
e, 4-58
Address Count TimINEG ........c..uvrvieiiieeiiiiieeeeeecceeee
e
rrrre e earaeee e
4-59
Horizontal Timing.........coooiiiee
e et
ee e e e e e
eans 4-61
Line Buffer Address Outputs — 80 Column .............ccceveeeiiieiiiiiriiieeceeceeeeeee 4-62
Line Buffer Address Outputs — 132 Column ...........ccccocveeeeiiiiiiiiineeeeee e, 4-63
Vertical Signals — 60 Hz .............euneiiiiiiiiiiiiiiiieeee
e e e e e e eeee e 4-65
Vertical Signals — SO HZ ... 4-66
Composite SYNC QULPUL ......ccoeiiiiiiiiiceee
et eeeecrrre e e e e e s e nraaereeeeaens 4-68
DCO012 BloCK DIaBram........ccevveiiiiiiirieiieieieeeiieieeeeceeeecirnrrreeereeeeeeeeeeeeeeeeeeesnnsnnns 4-69
| D J0 AN 8 {173
111 11 - 2SSO
SRRRRRR 4-76
Dot Stretcher EXample .....ccoooonnnnniiiiiiieeeiieieccrreeee
ettt s e
ee e e e 4-76
Character Generator ROM Patterns ...........coooeeiiiiiiiiiieiieeeeeeeee e 4-78
DMA Cycle Timing Diagram...........cceeeiiiiiiiiiiiiiiiieiriiirriinrnnenieereeceseeeeeeseeeseesennnens 4-81
Character LatCh Timing .......ueeieeiiiiiiieiiiiiiiiceceeeeceeeeeeeeeeetreeeee
e e e eeeseeeereeeeeasanannas 4-83
Video BIANKING.......ccooiiiiiiertrrr
et
s
eaneer st raeee e e e e e e e anenan 4-84
Line OrgamiZation ............ccveiiiiiiiiiiiiiiiiieeeeeeeeeeeeseseiretereeeeseesesnssseseeesesssnsnssneaaeesasans 4-86
Terminator and Address Bytes.........cccooeeeeieeiiiiiieiiiereeeeee
e
erreeeeee e 4-86
Screen RAM Organization — 80 Column, 60 Hz...........cccoooiiiiiiiiiiiiiiiieeeeeeenn, 4-88
INeed for Fill LINes........coccoiiiiiiiiiieeeeeeccccceteeee
e ceeccentee e ee e e cnrreae e e e e e avneaeens 4-90
Fill Line Operation — 60 Hz...............uniiiiiiiiiiiiieeecneccirreeee
e eveeee e e e ees 4-90
Fill Line Operation — SO HzZ..........coooiiiiiiiiireeceereecesrrre
e seeree e s s eaeneee s 4-91
End Of Screen Fill Line Operation...........cccccvveiiriieiiiiiiiioniiccccciiniirneerreseeeeseeesssns 4-91
Line Address Offset Table..........ccooveeiieeieiieecieeteeee
e e 4-93
Full Screen Address Shuffling...........coooevvviiiiieiiiiiiiiiiiiiiiieeiieererertvreveerereeeeeaeeeaee 4-94
Split Screen Address Shuffle........cooo oot 4-96
Split Screen Smooth Scroll at Midpoint ............ccceoiiiiiiiiiniiiiiieeeneeee 4-97
Horizontal Deflection Current — TO.........cccoooiiiiiiiiiieiieeeee
e eee e -102
Horizontal Deflection Current — Tl.........miriiiiiiiiiieeeeeccerrtee
e e eneneee e -102
Horizontal Deflection Current — T2..........oviiiiiiiiiiiiiiiieieeccerere
e e e e s eanneees -102
Horizontal Deflection Current — T3.........enee
e ccrrecererreereeeee e -103
Horizontal Deflection Waveforms.........cccvvvvvviiiiiiiiiiiiiiiiiccccccirreeeeteeeeeeeeeeeeennes 4-103

VT100 Power Supply Block Diagram .........cccccoeeviieeiinieiniiinncieencieniee
e -107
3524 Regulator Block Diagram ..........cccccevncmmiiiciiniinincenicnnnenee. erereeeereerrenaaeeeneans4-108
Power Supply Timing Diagram........cccccocceiiiiriniieiiiiiiniiiiniiiiniieecceennnnieeeee
s4-109

X1i

WLM b W

A
O
s
UlUIL.IlUlUl'

O OO0

WNE WN

=
o

prd pmed pmd ek ek ek pmed et sk ek O OO

&.II

NN
DD

5-23
5-24
6-1
6-2
6-3
6-4
6-6

6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21

6-22
6-23
6-24
6-25

Video Alignment Templates .........ccouiiiiiiiiiiiiieiiiriiiiriireeeeeeee
e e e s seesecsseaeeeeeeeeeens 5-13
Ball Video Monitor Board Adjustments..........cccooeeeeeeeeiiieiiieiiiecrereeeeeeeceeeeeeeeeeeeeeeenes 5-15
Ball Monitor CRT AdJUStmEnts...........ccovvvviviiiriiiiiiiieiieeieereeeeeeeeeeeeeeeeeeesseereseeesseee.. 5-17
Elston Video Monitor Board Adjustments..............ccccveeveeeiiiiiiiiiiiniiiceeereeeeeeenen 5-21
Elston Monitor CRT AdJustments.............cuuvveeriiiirieiiieriieiiieeeieierieeeeeeeeeeeeeseseeeseee. 5-22
Removal Procedures Flowchart ..............cccoooiii
e, 5-27
VTI100 Terminal (REAr VIEW) ....ccoovuuiiiiiiieiiccei ettt eeeeeeeraenare e e e eeees 5-28
VT105 INterCONNECLIONS.........coviieiiiiiiieieeeeeiiiiiieeeeeeeeretieeeeeeeeerearaneeeesessssssnsneeeesenns 5-29
Terminal Controller with AV
O ... 5-30
Keyboard Disassembly..........ccooiiiiiiiiiiiiiiiiecc
e 5-32
Top Cover Removal (Front VIEW)..........coceiiiiiiiiiiiiiiieei et
e e 5-33
Top Cover Removal (Rear VIEW).......ccooviiiiiiiiiiiiiiiiiiiieiieierereeeevveeeeeeeeeseeseseeesessreseaes 5-34
Ball Video Monitor Board Removal............cooooiiiiiiiiiiiiiireeeeeeeee e, 5-35
CRT Anode DiSCharging...........ooouvuiiiiiiiiiiieieieiiiricccrereeeeeeeeeeeeeseeeeeessnaneeeeeeeens 5-37
Elston Video Monitor Board Removal.............coooviiiiiiiiiiiiiiiriereeeeeeeeeee 5-38
Power Supply Removal ..........euuieiiiiiiiiccccrcccre
e 5-40
Power Supply Capacitor DiSCharging.........cccccoeeeeeiiiiiiiiiiiiiieecccccccccecececeeee
e 5-41
VT100 DC Power Harness Removal...............oovvviviiiiiiiiiiiiiiiieeiirereveeevereeeeeeeeeseeene 5-42
VT105 Expansion Backplane Removal...........cccccccceiiiiiiinnininiiiineeceeeeeeeeeee, 5-43
Terminal Controller Board, VT100
L000) 11 31241021810« F TSP 5-45
Terminal Controller Board, VT132
L000) 13 312408 214 0] « PP 5-46
Advanced Video Board, VT100 Configuration.............ccccevvveevevevevreveveereveeeeeeeeeeenn, 5-47
Advanced Video Board, VT100-WA /WB
CONFIGUIALION .. .cceiieeieei it
ee e eeeeeeeseasssassasarsessasesrsasrssssaens 5-48
Advanced Video Board, VT 132 Configuration...........ccccceeveeeeevieeeeeirieeeceeececnnnns 5-49
VT105 Waveform Generator Board Configuration .............cceevvvvevvvveeveveeeeeeeeeeeeenne 5-50
VT100-WA SET-UP SUMMATY .....coovviiiiiiiiiiiiiieecccccccierrcvineeeeeeeeseeeeeeeeeennnnnnnas 6-1
VTI100-WB SET-UP SUMMATY.......couviiiiiiiiiiiieciiireeeeececcciireeee
e eeeenneeeeeeeeeennnns 6-2
VT132 SET-UP B Presentation ..............cocvvvvvevvviiieieieiereeieeeeeeeeeeeeeesieeesseee.reeeeeeeeens 6-3
VTI132 SET-UP B SUMMATY ....ouuiiiiiiiieeerceeeer
s eeeeeereeeeeeese e s e es e e e ee e
6-3
VT132 SET-UP C Presentation............c.covvvvviiviieiiiiiiiieieeeiieeeeeeeeeeeeeeeeeeseessessssssssee. 6-4
VT132 SET-UP C SUMMATY .....oovviiiiiiiieeieieeeeceeeecceccnrnneereeere
e e e e e e eeseeeee
6-4
VT132 SET-UP B Default Summary .......ccoooeeiiiiiiiiiiiiiiieeeeeeeeeee, 6-7
VT132 SET-UP C Default SUmMmary ........cccoocvvviiieiiiiiiiiicccccecccineeiereeeeeeeeeeeeeaes 6-7
Advanced Video Option Installation..............cccceveiieieiiiiiiiiieiiccrieereeeeeee
e 6-9
20 mA Current LOOP OPtion..........uviiiieiiiiiiiiiiiiieeeeeececciiireeeeessessciveeeeesesssssnnnessans 6-14
INEErface StAtes.......uiieeeeeeeeceeee
e 6-16
M7071 Waveform Generator Block Diagram ..........ccccccooevieviiciiiiinnnieiieeeeeeeeeeeeenes 6-20
Decoding the Control Character.............ouvveeiiiiieiiiieiiiiiiiieeieeee
e eeeeee e 6-23
Rectangular Aspect Ratio Graph Drawing Field ............ccoovvvvviiieiiiiiiiiniiinnnneee, 6-24
Square Aspect Ratio Graph Drawing Field............ccccovvvieieiiiiiiiiiiiieiieeeeeeeeeee, 6-24
Selecting Mode of Operation.........ccccceeeeeeninnreeeeennn...etrreeeeteeeeeeeeaeaeaennnnnnnararaaaraaees 6-25
Phase LOoCK LOOP TImMING .......uuiniiiiccccc
s 6-27
Loading the REGISLETS .........uuviiieiiiiiiiiieeeec ettt
eessaarre e e e s esan 6-28
Register O (1st Data Character)..........ccovvvevieviiieiiiiiieiiiiiiieeeieeeeeeeeeeereereereeereeeraeeae—ae. 6-29
Register 0 (2nd Data Character) .........ooveieviiieeeiiieeeeecceecrrereee
e e e csssnaaens 6-29
Register 1 (1st Data Character)...........ooovvviveiiieiiieiiiieiieiiieeereeeeeeieeereeeeeeeeeeeeseseeeeneees 6-29
Register 1 (2nd Data Character) ............cooveeiieeieiiiiiiieeccereeee
e eeeenas 6-30
Loading Address Data ...........coooovveiioiiiiiiiiiireeeeeeececcc
e e e e e s s esseann 6-31
Graph Memory and Y-Address MONItor..............ccooveiieeiiiiiieeieniieneeenreeeeecneeeeennns 6-33
Baseline (Shade Line) Registers and
000711101
& 170 ¢ SOUOU U 6-34

Vertical Line and Graph Marker Memory .......ccccccceiiiiiiiiiiiiirceeeeeee 6-35

Graph Marker Y-Address Comparator...........cccceeeiiiiieeeiiiiiieeeeeceeeeirieee
e e, 6-37
Horizontal Line MEMOTY ....coooiiiiiiiiiiiii et
rese e e e e e e e e e aeeeans 6-38
Generating Strip Charts.................. ettetetteieeeteeeeeeteeeeertrtera—aaaaeaeererertettrtrrn———aaas 6-39
Dual Strip Chart Timing Diagram .........ccccooieiiiiiiiiiiiiiciee
e, 6-41
Combining Video Out ..................... e eeeeeeeeeteeaeaaea e aaaha———ttetatataeaeeaeaeseeanaasaaannrreens 6-42
Graph Test Pattern ..o
e e e e e 6-44
Histogram Test Pattern................... et eetete i eeeeeeeeeeeteteeertrrn—————aaaeteatertertttrrnaaans 6-45
Graph Marker Test Pattern............. eteeeteeteettet——————————————————tthaaanaanaaaaaaaa
e annannn 6-45
Horizontal Lines Test Pattern......... et tteeeeeeeeeetetaaeeteeettten—aeteeraatanaateeeaernnnaaaaeeeeens 6-47
Vertical Lines Test Pattern............. eteetereeeeesteetereeenettter——————aaareeeterretrrttraaes 6-47

Shade Line (Baseline) Test Pattern .......c.oouvvvueeeiiiiiiiiiiieeeiiieetiieeeeeeeeeee
e 6-48
Strip Chart Test Pattern.................. et eeeeeeeteeeae e e a—a—————attateeeaeeeeteaeeeeaaaaaeaaannnnens 6-50
Serial Line Splice Connection......... eeeeeeeeeteesteteeessesesttestet——t—.——————_tttntnrannnannnnnnnnnnnnnnn 7-2
STP With NO Option Present ..........ccoeeiiiiiiiiiiiiiiiciieiee
e e e e e e eeeee, 7-2
STP With Option Present ............... eeeeeeettersrstesstestestttett———.—.————————————_—nnnnnnonnnnnnnnnnnn 7-2
STP SigNal LINES ...cooovieiiiiieiee
ee e ee eeee e ve
eee ee
7-3
| o Yo 1 N @) [0 Y]
U T TSP 7-10
STP CONNECLOT ...cciiiiiiiiiiiiiieeietee
ettt e e
e s s erae e 7-11
STP OPtion Card ......cccooviiiiiiiiiiiieee
ettt e e e s st e e e e e s et eeeeeeaans 7-12
Terminal Data FIOW ......cooooimiiiiie et
e s e e e e e e e va e A-1
VTI100 Keyboard..........ccovriiieiiiiiiiieee
sttt e e s e a e e s s aeaee e e e e snaes A-3

Categories of SET-UP Features..........uuuuuuiiiiiiicrieieecccrerereeeeee 2-9
SET-UP Feature Change Summary ...........cceoeiiiiiiiiiiiiiiieiiiereeeeeeeeeeeeeeeeeeeeeeenee 2-10
Fatal Displayed Error Codes........... eteeeeeeeerreteteeeeeieeeeeieeeereeeeeeeeanararrrataeeeeeennanreres 2-18
Nonfatal Displayed Error Codes..........ccouvviiiiieiiiiiiiiiiiiieeeeee
et e 2-18
Problem CheckliSt.........uuuiiiiiiiiieieieieee
et ee e 2-19
EIA Connector Signals ..........cevviiiiiiiiiiiiiiiiiiiiercrceeereeee e 3-5
ROM Ship Select Addressing......... eeeeeereteerereretesssseesesttttb———————————————————nnonnnnnnanaannnnan 4-17
List of Hex I/O Addresses........ccocovevieeniiiiiieiniiiniiiniiniiiciiccric st 4-17
INtErrupt AdAIESSES .ooeeeeiiiieiieeei et 4-18
Baud Rate Generator Divisors........ eeeeeeeetessseerereesstseetteter————.————————tannaonannnnann
i nnaen 4-27
Loopback Test CONNECLOTS........ccoiiiiiiiieeiiiiiiiieiiiiriie
e 4-30
Keyboard Receiver Signals...........coovoieeieiiiiiiiiiiiiieieiiieeintcciecceece
i 4-37
Video Mode Selection (Write Address = C2H) ......oooiviiiiiiiiiiiiiiiiiiiiceeeeeeeerveeeee, 4-55
Control Chip Commands (Write Address = A2H)......ccccovviiiiiiiiiiiniiiiiinniiinnnnn, 4-70
SCAN COUNt SEQUENCE .....eeviiiiiiiiieiiiieeeeeeeeeteeeeeeeeeeeeaseerererteeeeeeeeeessessesasssssssssssnnns 4-72
Character Attribute Combinations..........c.uuuuueiiiiiierriirieiiiiiieeee
e 4-75
Keyboard LED Error Codes........... eeeeeeeeeeesteteteeeete————.—a———tan—aanhhaanaaaaanaaaaaeaneaees 5-1
VT100 Display Error Codes............ eeeeeeeeeeeeesteeeeeeteessessrereeeeeeeeeeeaaaaretatateeeeeeaaannns 5-2

Basic VT100 Troubleshooting Procedure ...........co.veuvereemmeerieeememmeeeneiiieinnans 5-4
LED EITor COAES ....cccoioiiiiiieieeeeeieeeeeecciiiiritteeeeeeeeeeeeeeesssesssssssnnssseseessaeaeeeeaseas 5-9
Displayed Error Codes........ccoovviiiiniiiriniiiiiieiiicniiiiiiccniiccentceic
e, 5-10
VT132 SET-UP Feature Change Summary .........cccceiiiiviiiiniirieniiicciececieenniiieneennne. 6-5
(0007118
18] O] 1 T2 721
11 ¢ TH00
U O
RO O UP PP PP PP PP PPPPPPPPPI 6-22
SET-UP Features and Machine States..........ccuuuvevreemmeeeemmeiemeeemieinnns A-4
Alphabetic Key Codes (OCtal).......c.cceevueriiiiniiiniiiniiiniiiiiiciecieccneccnee
e, A-5
NonAlphabetic Key Codes (Octal)........cccoooeiiiimiiiiiiiiiiiiiiiiniieiee
e, A-6
Function Key Codes...........uvviiiiiieiiiiiieieneeecenciittceceniintte
s A-7

X1V

A-6

Control Codes Generated............ovvviiiiiiiiiiiiiiiiiiecrrerrreee
e et e e e s s e e s s essnnes
Cursor Control Key Codes ......ccoviviiiiiiiiiiiiiiiieiniiteeeescirreee
s eesireeee e eeereree e

A-7

VT52 Mode Auxiliary Keypad Codes.........cccoooeiiiiiiiiiiiiiiieeeenceeeeeceeeeeeeeeee, A-10

A-8

ANSI Mode Auxiliary Keypad Codes...........cccoooiiiiiiiiiiiieeeeeeceeeee e, A-10
Special Graphics CharacCters ...........oooovviviiiiiiiiiieiiiiei
e e e e e eens A-12
(000)
115 (o) O] 1 F:§ - 101 13 5 T
U O PSP P U PP A-15
VT100 Escape SeqUences SUMMATY ........cccooeeeeeiiiiiniririiiiiereeeseeeeeeeeeseeessesssssnsnnenens A-16

A-5

A-9

A-10
A-11

B-1

Recommended SPares.........couvvviiiiiiiiiiiiiiiiiiicccrcrcereeerereseeeeeeeeeee
e e e e e e e e e e e e e e eeeeeaeeeas

B-2
B-3
B-4

VT100-WA Recommended Spares........cccoeeeeeeiiiiiiiiiiiiiiiiceeeeeeeererereeeeeeeeeeeeeeeeeeeeeee
VT105 Recommended Spares..........ccccccveviiiiiiiiiiiiiieeeeeeeeeeeeeeeceecccvereeeeeeeeeeee
VT132 Recommended SPares...........uuueuuuiiiiiiiiiiiieieieeeireeeeseeeeseeeeeeeseeeeeeeesaaeaesaenens

A-8
A-9

B-2
B-3
B-3
B-4

CHAPTER 1

INTRODUCTION AND SPECIFICATIONS

This is the technical manual for the VT100 series video terminals. It contains information a service technician or engineer needs to operate, test, and repair the VT 100 series to a component level.
Chapter |

Contains VT100 specifications and documentation ordering information.

Chapter 2

Contains basic operator information, including use of the keyboard, use of SETUP modes for setting terminal characteristics, and simple trouble checking.

Chapter 3

Contains installation procedures and interface information.

Chapter 4

Contains a technical description of the basic VT 100 video terminal. This chapter
assumes that the reader has the Field Engineering Print Set, MP00633.

Chapter 5

Contains servicing information for the basic VT100 video terminal.

Chapter 6

Contains SET-UP information for the various VT 100 series options, installation
information, a technical description, and service information for the Advanced
Video option, the Current Loop option, and the VT 105 Graphics Processor.

Chapter 7

Contains a technical description and interfacing information for the standard
terminal port (STP).

Chapter 8

Contains interfacing information for the graphics connector.

Appendix A

Contains programming information for the VT 100 series, including interface
timing considerations and descriptions of control functions the VT 100 responds
to, both in ANSI mode and in DEC VT52-compatible mode.

Appendix B

Contains a Recommended Spares List.

Appendix C

Contains a glossary of terms and abbreviations used in this manual.

1-1

VT100 SPECIFICATIONS

DIMENSIONS
Monitor
Height
Width
Depth

36.83 cm (14.5 inch)
45.72 cm (18 inch)
36.20 cm (14.25 inch)

Keyboard
Height
Width
Depth
Minimum table depth

8.89 cm (3.5 inch)
45.72 cm (18 inch)
20.32 cm (8 inch)
51.4 cm (20.25 inch)

Weight
Monitor
Keyboard
Shipping weight

13.6 kg (30 Ib)
2.0 kg (4.5 Ib)
18.6 kg (41 Ib)

ENVIRONMENTAL
Operating
Temperature
Relative humidity
Maximum wet bulb
Minimum dew point

Altitude

10°t040° C(50° to 104° F)
10% t0 90%
28° C(82°F)
2° C(36°F)
2.4 km (8,000 ft)

Nonoperating
Temperature

Relative humidity
Altitude

—40°t066° C(—40°to151°F)
0to95%
9.1 km (30,000 ft)

Power

Line voltage

90-128 V rms single phase, 2 wire
180-256 V rms single phase, 2 wire (switch-selectable)

Line frequency

47-63 Hz

Current

3.0
Arms maximumat 115 V rms
1.5 A rms maximum at 230 V rms

Input power
Current limiting
Power cord

250 VA apparent 150 W max.
3 A normal blow fuse
Detachable, 3 prong, 1.9 m (6 ft)

1-2

Display

CRT

30 cm (12 inch) diagonal measure, P4 phosphor

Format

24 lines X 80 charactersor 14 lines X 132 characters (selectable)

Character
Charactersize
80 column mode
132 column mode
Active display size
Character set

7 X 9 dot matrix with descenders

Cursor type

Keyboard-selectable, blinking block character or blinking underline

3.35mm X 2.0mm (0.132 inch X 0.078 inch)
3.35mm X 1.3 mm (0.132inch X 0.051 inch)
203 mm X 127 mm (8 inch X Sinch)
96-character displayable ASCII subset (upper- and lowercase, numeric,
and punctuation)

Keyboard

General

83-key detachable unit with 1.9 m (6 ft) coiled cord attached

Key layout

65-key arrangement and sculpturing similar to standard typewriter, with
18-key numeric keypad.

Numeric keypad

18-key with period, comma, minus, enter, and four general purpose
function keys.

Visual indicators

7 LEDs; 3 dedicated to ON LINE, LOCAL, and KBD LOCKED:; 4 are

user-programmable.
Audible signals
Keyclick
Bell

Multiple bell

Sound simulates typewriter.
1) sounds upon receipt of BEL code; 2) sounds 8 characters from right
margin (keyboard-selectable).
Sounds upon detection of error in SET-UP save or recall operation.

Communication
Type

Speeds

EIA
Full duplex: 50, 75, 110 (two stop bits), 134.5, 150, 200, 300, 600, 1200,
1800, 2000, 2400, 3600, 4800, 9600, 19,200

Code
Character format

ASCII
Asynchronous

Charactersize

7 or 8 bits; keyboard-selectable. (Note: if 8-bit character is selected, 8th
bit is always space.)

Parity

Even, odd, or none (keyboard-selectable)

Synchronization

Keyboard-selectable via automatic generation of XON and XOFF control
codes.

1-3

ORDERING HARDWARE DOCUMENTATION
The following VT100 DECscope video terminal hardware manuals can be purchased from DIGITAL’s
Accessories and Supplies Group.

Part No.
EK-VT100-UG
EK-VT100-J1
EK-VT100-IP
EK-VT105-TM
MP 00633
MP 00642
EK-VT105-1P

Title
VT100 User Guide
VT100 Pocket Service Guide
VT100 Illustrated Parts Breakdown (IPB)
VT105 Technical Manual
VT100 Print Set
VTI105 Print Set

VT10S5 Illustrated Parts Breakdown (IPB)

Purchase orders for accessories and supplies should be forwarded to:
Digital Equipment Corporation
Accessories and Supplies Group
Cotton Road
Nashua, N.H. 03060

Contact your local sales office or call DIGITAL Direct Catalog Sales toll-free 800-258-1710 from 8:30
a.m. to 5:00 p.m. eastern standard time (U.S. customers only). New Hampshire customers should dial
(603)-884-6660. Terms and conditions include net 30 days and F.O.B. DIGITAL plant. Freight charges
are prepaid by DIGITAL and added to the invoice. Minimum order is $35.00. Minimum does not apply
when full payment is submitted with an order. Checks and money orders should be made out to Digital
Equipment Corporation.
Related Documentation

Intel 8080 Microcomputer Systems User’s Manual
From:
Intel Corporation
3065 Bowers Avenue
Santa Clara, California 95051
EIA Specifications RS-232-C and RS-170
From:
Electronic Industry Association
EIA Engineering Department
2001 Eye Street, N.W.
Washington, DC 20006

ANSI Standards X3.41-1974, X3.64-1977, 3.4-1977
From:
Sales Department
American National Standards Institute
1430 Broadway
New York, NY 10018

CHAPTER 2

OPERATOR INFORMATION

PART 1

KEYBOARD CONTROLS AND INDICATORS

The VT100 terminal normally performs a two-part function. It is an input device to a computer information entered through the keyboard is sent to the computer. It is simultaneously an output
device for the computer - that is, data coming in from the computer is displayed on the video screen.
The following controls and indicators on the VT 100 keyboard are illustrated in Figure 2-1.

SET-UP

SET-UP Key

Used in conjunction with other keys to perform specific functions such as setting tabs, scrolling, and
altering terminal characteristics.
ON LINE Indicator
|
Lights to show that the VT 100 is on-line and ready to transmit or receive messages.
LOCAL Indicator

Lights to show that the terminal is off-line and cannot communicate with the host device. In local
mode the keyboard remains active and all characters typed are placed on the screen.
KBD LOCKED Indicator

Lights to show the keyboard has been turned off. The VT 100 is still able to receive data from the host.
This condition can be cleared by entering and exiting SET-UP mode.
L1-L4 Indicators

These indicators are turned on and off by the host. Consult your local operating procedures for the
meaning of each indicator. L1-L4 also show self-test errors.

Keys

Each of these keys causes the VT100 to transmit a code that has a special meaning to your system.
Consult your local operating procedures for the meaning of these keys. In SET-UP mode the tand |
keys increase or decrease display brightness. The « and — keys move the cursor left and right.

BACK
SPACE

BACKSPACE Key

Transmits a backspace code.

2-1

20 0 ¢ ‘ /
21ndig -7 0 ILA pi1e0qAaY

| © J#| % v R * +
l4d

¢4d

vid

H3I1IN3

2-2

BREAK

BREAK Key

Transmits a break signal.

PF1

PF2

PF3

PF4

PF1-F4 Keys

Each of these keys causes the VT 100 to transmit a code that has a special meaning to your system.
Consult your local operating procedures for the meanings of these keys.
Numeric Keypad

The numeric keypad enables numbers to be entered in calculator fashion. Each key in the numeric
keypad generates the same character as the corresponding numeric key on the main keyboard. The
ENTER key corresponds to the RETURN key. These keys may also be interpreted by the host computer as special function keys. Consult your local operating procedures for the meanings of these keys.

DELETE

DELETE Key

Causes the VT100 to transmit a delete character code to the host system. The deleted character may or
may not be erased from the screen.

RETURN

RETURN Key
Transmits either a carriage return (CR) code or a carriage return and line feed (LF) code. This is a

SET-UP selectable feature.

LINE
FEED

LINEFEED Key

This key transmits a line feed code.

SHIFT

SHIFT Key

When pressed, this key enables the uppercase function of all keys. If a key does not have an uppercase
function the SHIFT key is disregarded.

)

O | RESET Key
In SET-UP mode this key starts the reset sequence. This has the same result as turning the terminal
power off and then on.

2-3

(

80/132 COLUMNS Key

In SET-UP A mode this key switches the display line size from 80 to 132 characters per line or from

132 to 80 characters per line.

8 | RECEIVE SPEED Key
In SET-UP B mode this key steps the terminal through the receive baud rate settings in ascending
order.

&
7

TRANSMIT SPEED Key

In SET-UP B mode this key steps the terminal through the transmit baud rate settings in ascending
order.

5 | TOGGLE 1/0 Key
In SET-UP B mode this key turns the selected operational feature on or off.

BELL

G | BELLKey
When pressed in combination with the CTRL key this key causes a bell code to be sent to the host.
p 4

S | SET-UP A/B Key
In SET-UP mode this key switches the terminal from SET-UP A to SET-UP B or from SET-UP B to
SET-UP A.

LINE/LOCAL Key

In SET-UP mode this key switches the VT 100 to communicate with your system (ON LINE) or stops
the VT100 from communicating with your system (LOCAL).
#

3 | CLEAR ALL TABS Key

In SET-UP A this key clears all horizontal tabs set in the VT100.

SET/CLEAR TAB Key

In SET-UP A this key sets or clears individual horizontal tabs.

2-4

CAPS

LOCK

CAPS LOCK Key

This key enables the transmission of uppercase alphabetic characters only. All numeric and special
symbol keys remain in lowercase.

SCROLL

NO SCROLL Key

When first pressed, this key stops the transmission of data from the computer to the VT100. When
pressed a second time, transmission resumes from where it was stopped. Check your local operating
procedures to ensure that your system recognizes this key.

CTRL

CTRL Key

When pressed in combination with another key, CTRL causes the VT 100 to transmit a code that has a
special meaning to your system.

TAB

TAB Key

This key transmits a tab code.

ESC

ESC Key

This key transmits a code that normally has a special meaning to your system. In many applications, it
tells your system to treat the next keys pressed as a command.

MONITOR CONTROL

The VT100 monitor contains only one control, the power switch, shown in Figure 2-2.
AUDIBLE INDICATORS (TONES)
There are three audible indicators associated with the VT100: a short tone (click), a long tone (beep)
and a series of long tones.
Short Tone (click)

The short tone sounds whenever a key is pressed, with the following exceptions:
e

SHIFT or CTRL keys do not generate any keyclick because these keys do not transmit any
codes but only modify the codes transmitted by other keys.

When the KBD LOCKED indicator is turned on; in which case, the characters typed are

lost.

The keyclick feature has been turned off in SET-UP mode.

2-5

Long Tone (beep)
The long tone sounds to indicate one of the following conditions:
*

A bell code was received from the computer.

The cursor is eight characters away from the right margin and the margin bell feature is

enabled.

Series of Long Tones
The terminal sounds the long tone several times in rapid succession to indicate that the nonvolatile
memory (NVR) had difficulty reading or writing SET-UP features. (When this occurs, check the SET-

UP features and then perform the recall or save operation again.)

CAPTIVE

ACCESS

SCR/EWS (4)

C?VER

LINE PRINTER

I
OPTION

L/3 CONNECTOR

COMMUNICATIONS

VIDEO
— EXTERNAL
INPUT CONNECTOR
/ EXTERNAL VIDEO

CONNECTOR
|

EIA

‘

PRINTER

INDIC|)|ATOR

——OUTPUT CONNECTOR
MAIN FUSE

POWER SWITCH

MODEL + SERIAL
NUMBER LABEL

KEYBOARD

POWER

POWER CORD

CONNECTOR

SELECTOR

CONNECTOR

OPTIONAL 20mA

SWITCH

COMMUNICATION

MA-1987

CONNECTOR
Figure 2-2 VT100 Terminal (Rear View)

PART 2

SET-UP MODE

Unlike most terminals, the VT 100 does not use switches or jumpers to individually turn the built-in
terminal features on or off. Instead, the VT 100 uses a nonvolatile memory (NVR) that always remembers what features have been selected, as if a switch had been set.

2-6

Selection and storage of built-in terminal features is performed in a special mode of operation called

SET-UP mode. When you enter SET-UP mode, the status of features stored in temporary memory
shows on the screen. You can then change the features and store any new feature selections either
temporarily, by leaving SET-UP mode; or on a fixed basis, by performing a Save operation. In either

case, terminal operation reflects the new feature selection. If a recall operation is performed, or the
terminal is reset, or terminal power is turned off, all temporary feature settings are replaced by features
that have been stored on a fixed basis.
SET-UP Features

SET-UP mode provides two brief summaries of the current feature status. The first presentation SET-UP A - displays the location of tab stops set and a visual ruler that numbers each character
position on the line. The second presentation - SET-UP B - summarizes the status of the other terminal features.
SET-UP A - To enter SET-UP A, press the SET-UP key. The display has a presentation similar to
Figure 2-3. The bottom line of the display consists of a “‘ruler” that numbers each character position
available on a line. Each tab stop is shown by a “T” above the ruler. If the tab stop(s) set are those

desired, you may exit SET-UP mode by pressing the SET-UP key again or you may now change the
tabs to meet your requirements.

SET-UP A

)}

234567990 pREGTRERG1
2 345678 30 PRL LI

23456788

MA-2732

Figure 2-3 SET-UP A Mode Presentation

2-7

SET-UP B - SET-UP B mode may only be entered from SET-UP A mode. To enter SET-UP B from
SET-UP A press the 5 key on the main keyboard. The display looks like Figure 2-4. Figure 2-5
summarizes the SET-UP B presentation. This summary allows you to quickly determine what features
are enabled. For additional information on a feature refer to in Part 3, SET-UP Feature Definitions.
To exit SET-UP B press the SET-UP key.

3
£
I

Figure 2-4 SET-UP B Mode Presentation

Determining What a SET-UP Feature Does

SET-UP features are basically a series of options in the VT 100 that allow the terminal to be tailored to
its operating environment. Table 2-1 lists each feature and shows one of the following general categories.
Installation

Computer compatibility
Operator comfort

The installation category includes the initial installation of the terminal and any special options that
may be attached to the terminal. If any options are added or removed, or the physical location of the
terminal is changed, verify the settings of these SET-UP features.
2-8

SCROLL {? B

(SHIFTED) {? .

—— AUTOREPEAT {? - g;':

—— WRAP AROUND {? _ g;F

SCREEN {o = DARK BACKGROUND

NEW LINE {o = OFF

1 = LIGHT BACKGROUND

1 = ON

‘[cuason {? - g[‘ODCEI?“NE

(OPTIONAL

INTERLACE {? - 8:F

DISPLAY
FOR CUSTOM

FUNCTIONS)

2(1T11]

AlTT1]

vvvvvvvvv -

labdededad

\—POWER {0 = 60 M

AUTO XON XOFF {? _ 8;F

TSPEED[___]

= 50 Hz

— ansivrsz {97V

L BITS PER CHAR. {01 == 78 BITS
BITS

L KEYCLICK {? _ g;F

L PARITY {O1 == OFF
ON

L MARGIN BELL {? _ 8::

R SPEED[___]

PARITY SENSE {01 == 0ODD
EVEN

MA-1988

Figure 2-5 SET-UP B Mode Summary

Table 2-1 Categories of SET-UP Features

Computer
Compatibility

Installation

Ansi/VT52 mode
Answerback message

XX
AK

Auto Repeat
Auto XON/XOFF
Bits per Character
Characters per Line

X AKX

XXX

Cursor
Interlace
Keyclick
Line/Local
Margin Bell
New Line
Parity
Parity Sense
Power
Receive Speed
Screen Background
Screen Brightness
Scroll
Tabs
Transmit Speed
Wraparound

Operator
Comfort

3£ (shifted)

2-9

Feature

Computer compatibility contains the features that must be set correctly so that the VT 100 can communicate with the host computer. An error in these settings may cause incorrect data to be sent to or
received from the computer; or an error may prevent the VT 100 from communicating with the computer. The settings for these features must be obtained from the host computer programmer, operator,

or system manager since there are many combinations of settings designed to work with particular
computers and special software. These feature settings normally change only when you need to communicate with a different computer or a unique software package.
The operator comfort category contains SET-UP features designed exclusively for the operator. These
features allow the operator to tailor the VT 100 to fit individual preference. These features do not affect
any operations that occur between the terminal and the computer.
Part 3, SET-UP Feature Definitions, describes the specific function of each feature.
How to Change a SET-UP Feature
Changing any or all SET-UP features is a simple operation and is generally performed by following the
same basic steps.
1.

Enter SET-UP mode by pressing the SET-UP key.

Select the appropriate SET-UP mode by pressing the § key on the main keyboard each time
you want to switch from SET-UP A to SET-UP B or from SET-UP B to SET-UP A.

Position the cursor above the feature switch or tab stop to be changed. To position the
cursor, the SPACE bar, «, -, TAB, and RETURN keys may be used. Some features do not
use this step since a specific key is dedicated to changing the feature.

Change the feature setting by pressing either the 6 key on the main keyboard or the appropriate dedicated key. Each time the key is pressed the feature changes, generally to the
opposite state.

Table 2-2 briefly summarizes SET-UP features, the SET-UP mode you must be in to change a feature,
and the key used to change the feature setting.

Table 2-2 SET-UP Feature Change Summary

Changed In

Key to
Change

Feature

SET-UP Mode

Feature

Answerback message

ANSI/VTS52 mode
Auto Repeat
Auto XON/XOFF
Bits per Character

B
B
B
B

g
g
g
8

Brightness

* A special sequence is required for this feature. See the detailed features description.
2-10

Table 2-2 SET-UP Feature Change Summary (Cont)

Changed In

Key to
Change

Feature

SET-UP Mode

Feature

Characters per Line

Cursor

Interlace

Keyclick

Line/Local

Margin Bell

New Line

Parity

Parity Sense

Power

Receive Speed

Screen

Scroll

Tabs

(

(@ |

2 | and

Transmit Speed

Wraparound

# £

3 | (shifted)

#€

Setting the Answerback Message
Setting the answerback message differs from setting any other terminal feature. An answerback message can be typed into the VT100, using the following steps.
1.

Place the terminal in SET-UP B mode.

Press the SHIFT and A keys at the same time. The terminal responds by placing A = on the
screen. (The SHIFT key is required. The CAPS LOCK key does not work here.)

2-11

Type the message delimiter character which may be any character not used in the actual
answerback message. The message delimiter character is not part of the answerback message. If a mistake is made when typing the answerback message, type the message delimiter
character again and go back to step 2. This is the only way to correct errors in the answerback message.

Type the answerback message. The message may be up to 20 characters, including space and
control characters. Control characters are displayed as a character to indicate their presence
in the message.

Type the message delimiter character. Once the message delimiter character is typed the
answerback message disappears from the screen.

Once the above steps have been completed the answerback message is temporarily stored in the VT 100
and can be saved with the save operation.
Saving SET-UP Features

SET-UP features may be changed and stored on either a temporary or a fixed basis. To temporarily
store a feature, exit SET-UP mode after changing the feature; the terminal now reacts according to the
new setting. If a recall operation is performed, or the terminal is reset, or terminal power is turned off,
all temporary feature settings are replaced by the features that have been stored on a fixed basis.

To store SET-UP feature settings on a fixed basis, perform a save operation. This is a simple operation
that is accomplished by performing the following steps.
1.

Place the terminal in SET-UP mode.

Press the SHIFT and S keys at the same time. The screen clears and the message “Wait” 1s
displayed in the upper-left corner. After a brief wait, the terminal returns to SET-UP A
mode.
NOTE

The save operation must be performed at the terminal keyboard. The computer cannot perform this operation, although it can temporarily modify the
setting of VT100 features.

Once these steps have been performed, SET-UP features which had been temporarily stored are now
stored on a fixed basis.
Recalling SET-UP Features

Temporarily stored SET-UP feature settings may differ from settings that are stored on a fixed basis.
To return to the fixed settings, perform the recall operation as follows.
1.

Place the terminal in SET-UP mode.

Press the SHIFT and R keys at the same time. The screen clears and the message “Wait”
appears in the upper-left corner. After a brief wait the terminal returns to SET-UP A mode.
NOTE

When a recall operation is performed the contents of
the screen are destroyed.

2-12

Resetting the Terminal

The VT 100 may be reset from the keyboard. When the terminal is reset, the terminal memory is cleared
and the self-test program runs as if the terminal power switch was turned off and then back on. To
reset the terminal:
1.

Place the terminal in SET-UP mode.

Press the O key on the main keyboard. The VT100 is reset, the power on self-test runs, and
the terminal reacts according to the fixed SET-UP features.
NOTE
When a reset operation is performed the contents of
the screen are destroyed.

PART 3

DEFINITIONS SET-UP FEATURE

This section describes each SET-UP feature in detail (in alphabetical order) and states how each
feature affects the terminal.
NOTE
Unless otherwise stated, entering SET-UP mode and
changing features does not result in the loss of data
displayed on the screen.
ANSI/VTS52 Mode

The VTI100 terminal follows two programming standards - American National Standards Institute
(ANSI) and VT52. In ANSI mode, the VT100 generates and responds to coded sequences per ANSI
standards X3.41-1974 and X3.64-1977. In VT 52 mode, the VT 100 terminal is compatible with previous
DIGITAL software using the VT52 video terminal. Both ANSI and VT52 modes are outlined in
Appendix A of this manual.
Answerback Message

Answerback is a question and answer sequence where the host computer asks the terminal to identify
itself. This feature allows the terminal to identify itself by sending a message to the host. The entire
answerback sequence takes place automatically without affecting the screen or requiring operator
action. The answerback message may also be transmitted by pressing the CTRL and BREAK Keys at
the same time.
Auto Repeat

Auto repeat allows a key to be automatically repeated at the rate of about 30 characters per second
when the key is held down for more than one-half second. The auto repeat feature affects all keyboard
keys except the following:
SET-UP
ESC
NO SCROLL
TAB

RETURN

CTRL and any key

2-13

Auto XON/XOFF

The VT100 can automatically generate synchronizing codes XON (DC1) and XOFF (DC3). XOFF

Hwho
—

stops data transmission from the computer to the terminal; XON resumes transmission. With the
feature enabled, the VT 100 generates the XOFF code when one of the following occurs:

the internal buffer is nearly full
the NO SCROLL key is pressed
the terminal is placed in SET-UP mode
CTRL-S is pressed.

When the buffer empties, the NO SCROLL key is pressed again, the terminal is taken out of SET-UP
mode, or CTRL-Q is pressed, the VT100 transmits the XON code to resume transmission from computer to terminal.

If the host computer software does not support the XON/XOFF codes, data sent during buffer full
conditions, or when the terminal is in SET-UP mode, may be lost.

The

VTI100

NOTE
always stops transmission

when an

XOFF (DC3) code is received and resumes transmission when an XON (DC1) code is received regardless

of the Auto XON/XOFF feature setting.
Bits per Character
This feature allows the terminal to transmit and receive either 7- or 8-bit characters. When set for 8-bit
operation, bit 8 is set to a space (or 0) for characters transmitted and is ignored for all characters
received.

Characters per Line
The VT100 can display either 80 or 132 characters per line. In 80 character per line mode, the screen is
80 characters wide by 24 lines high. In 132 character per line mode, the screen is 132 characters wide by
14 lines high (24 lines if the VT 100 1s equipped with the Advanced Video Option). In 132 character per
line mode, the displayed lines are physically the same width as 80 character per line mode but the
characters are more compact.
NOTE
When changing from 80 to 132 character per line

mode or vice versa, the current contents of the screen
are lost.
Cursor
The VT100 has two cursor displays to indicate the ‘“‘active positions’ or where the next character will
be placed on the screen. The cursor may be displayed as either a blinking underline (—) or a blinking
block (m). The cursor selection may perform an additional function; see the SGR escape sequence
definition in Appendix A.
Interlace
This feature is used for high resolution options. The interlace feature should be turned off if such an

option is not installed.

2-14

Keyclick Tone

The keyclick is a tone that sounds every time a key is pressed. The keyclick may be turned on or off to
suit the operator’s needs. However, research and experience has shown that an operator is more accurate when there is audible feedback from the keyboard. Like the bell tone, the keyclick volume is not
adjustable.
LINE/LOCAL

The LINE/LOCAL feature allows the operator to easily place the terminal in either an ON-LINE or a

LOCAL (off-line) condition. When the terminal is on-line (ON-LINE indicator 1is lit) all characters
typed on the kevboard are sent directly to the computer and messages from the computer are displayed

on the screen. In the LOCAL condition (LOCAL indicator is lit), the terminal is electrically disconnected from the computer; messages are not sent to or received from the computer; and characters
typed on the keyboard are echoed on the screen directly.
Margin Beli
The margin bel! feature is much the same as the bell in a typewriter. If the cursor is eight characters

from the end of the current line while typing, the VT100 sounds a tone to alert the operator.
New Line
The new line feature enables the RETURN key on the terminal to function like the return key on an
electric typewriter. When the new line feature is enabled, pressing the RETURN key generates the
carriage return (CR) and line feed (LF) codes. When a line feed code is received, the code is interpreted
as a carriage return and line feed.
When the new line feature is disabled, the RETURN key generates only the CR code; an LF code
causes the terminal to perform a line feed only.
NOTE
If double line feeds occur consistently, turn this feature off since the computer is already performing this
function.

Parity

When enabled, parity checks for correct data transmission. If a transmission error occurs, the VT100
detects it and indicates its presence by placing a checkerboard character ( § ) on the screen in place of
the character with the error. The parity sense feature determines if the parity is even or odd. When
parity is disabled, no parity bit is transmitted or received.
Parity Sense
The parity sense feature defines which of the two methods of parity checking, odd or even, is being
used by the VT100. If the parity feature is on, the terminal’s parity sense must be matched to the parity

the computer is sending. If the parity sense features do not match, most characters sent to the computer are rejected even though the character was received correctly by the VT100. If a parity incompatibility occurs, the checkerboard character appears on the screen in place of the received

character.
NOTE
If the parity feature is turned off, the parity sense

selection is disregarded.

Power

During initial installation, the terminal display must be set to the power line frequency. In the U.S. this
is 60 hertz.

Receive Speed
Receive speed must be set to match computer transmit speed. The VT100 is capable of receiving at any
one of the following preselected speeds: 50, 75, 110, 134.5, 150, 200, 300, 600, 1200, 1800, 2000, 2400,
3600, 4800, 9600, and 19,200 baud.
Receive speed is independent of transmit speed; the terminal may receive data at one speed and transmit data at a different speed.
Screen Background
This feature allows the operator to select the background of the screen display. In the normal screen

mode, the display contains light characters on a dark background; in reverse screen mode, the display
contains dark characters on a light background.
Screen Brightness

Unlike most video terminals, the VT 100 does not ccntain switches or knobs to adjust screen brightness. Instead, the VT100 electronically controls screen brightness. This feature eliminates the high
failure rate of mechanical controls and still allows the operator to select the desired level of brightness

for maximum comfort under varied lighting conditions. This setting may be saved like any other
feature in the terminal.

Scroll

Scrolling is the upward or downward movement of existing lines on the screen to make room for new
lines at the bottom or top of the screen. It can be performed in two ways: jump scroll or smooth scroll.
In jump scroll mode, new lines appear on the screen as fast as the computer sends them to the terminal.
At the higher baud rates, the data is very difficult to read due to the rapid upward movement of the
lines. In smooth scroll mode, a limit is placed on the speed at which new lines of data may be sent to
the terminal. Upward movement of lines occurs at a smooth steady rate allowing data to be read as 1t
appears on the screen.
NOTE

Smooth scroll mode allows a maximum of six lines of
data per second to be added to the screen. The auto
XON/XOFF feature must be enabled and supported
by the host computer to ensure that data is not lost
when smooth scroll mode is enabled.

Tabs

The VT100 can jump or tab to preselected points on a line just like a typewriter. The tab stops may be
individually changed or totally cleared and then reset.
Transmit Speed

Transmit speed must be set to match the computer receive speed. The VT 100 can transmit at any one
of the following preselected transmit speeds: 50, 75, 110, 134.5, 150, 200, 300, 600, 1200, 1800, 2000,
2400, 3600, 4800, 9600, and 19,200 baud.

Transmit speed is independent of receive speed; the terminal may transmit data at one speed and
receive data at a different speed.

Wraparound

When this feature is enabled, the 81st or 133rd character (depending on line size selected) inserted on a
line is automatically placed in the first character position of the next line. If the wraparound feature is
not enabled, the 81Ist or 133rd character and all following characters are overwritten into the last
character position of the current line.

#3£ (shifted)
The VT100 contains character sets for the U.S. and the United Kingdom. The difference between the
two sets is one character, the # or 1 symbol. When the standard U.S. character set is selected, the
uppercase 3 key on the main keyboard displays the # character. The 1 character is displayed when the
U.K. character set is selected.
PART 4

SELF-TESTING THE VT100

A self-test mode in the VT 100 automatically, or on command, tests the condition of the terminal if a
fault is suspected. The self-test program checks the following items.
Internal memory
Advanced video memory (if option is installed)

Nonvolatile memory (NVR)
Keyboard
This test 1s performed automatically whenever the terminal is turned on.
Self-Test Error Codes
There are two broad categories oferrors: fatal and nonfatal. Fatal errors cause the terminal to immediately stop all operations. No intelligible information is displayed on the screen, but the screen most

likely contains a random pattern of characters. The only error indication (in addition to random
characters) is a possible error code displayed on programmable keyboard LEDs L1-L4. However, no

terminal function, including the lighting of LEDs, is guaranteed if a fatal error is found. See Table 2-3.
Nonfatal errors do not halt the terminal processor. Instead, the terminal is forced to LOCAL mode

and an error code character is displayed in the upper-left corner of the screen. There are five types of
nonfatal errors:
Advanced Video Option data RAM (AVO)

Nonvolatile data RAM checksum error (NVR)
Keyboard missing or malfunction (KBD)
Data loopback error (Data)
EIA modem control lines loopback error (EIA).

NOTE
Loopback tests are not performed on power-up; they
must be invoked separately with the proper escape

sequence. See Appendix A for further information on
this test.

Table 2-4 shows the possible nonfatal error characters that may appear on the screen and the failure
represented by each character.

If the terminal passes all these tests, a final check of its operation is possible in SET-UP mode. Examine the display and compare it with the printed examples. Double height, double width, bold, blinking,
reverse, etc., are all represented in SET-UP mode.

2-17

Table 2-3 Fatal Displayed Error Codes
Keyboard LEDs

Error

Replace FRU

OFF
OFF

OFF
ON

ON
OFF

ROM 1
ROM 2

Terminal controller
Terminal controller

OFF
OFF
OFF

OFF
ON
ON

ON
OFF
OFF

ON
OFF
ON

ROM 3
ROM 4
Main Data RAM

Terminal controller
Terminal controller
Terminal controller

Table 2-4 Nonfatal Displayed Error Codes
Faulty Module

Char

AVQO

!
2
3
4

5
6
7
&
9
,
,
<
=
>
?

A
B
C
D
E
F
G
H
I
J
K
L

NVR

KBD

ElIA

X
X

X
X
X

X
X

X
X
X
X

M
N
O

Data

X
X
X
X
X
X
X
X
X

X
X

X
X
X
X

X
X
X

2-18

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

PART 5§

WHAT TO DO IN THE EVENT OF A PROBLEM

If it appears that there is a problem in the terminal, you should initiate the self-test procedure. This test
will help to determine if the problem lies in your terminal or in some other part of the computer
system. If the terminal appears to be faulty, refer to Table 2-5. This table describes the items an
operator can check prior to making a service call.

Table 2-5

Problem Checklist

Symptom

Possible Cause and Corrective Action

VT100 will not turn on
when power switch

AC power cord not plugged into wall
outlet; plug in cord.

is set to ON.

AC power cord not plugged into terminal;
plug in cord.
Power not coming from wall outlet; check
outlet with known working electrical
device (a lamp). If no power, call your
electrician.

AC line fuse blown. Turn terminal OFF and
have the fuse replaced. (See Figure 1-2
for location.)
No keyboard response

Keyboard cable not plugged into monitor;
plug in keyboard cable.
KBD LOCKED indicator on; computer has
turned keyboard off. If condition
persists, check with the host computer
software people for a possible operating
error.

Perform the self-test operation.

Garbled characters

Transmit and/or receive speeds, parity
sense, or parity enable may be wrong;
check settings.
Perform the self-test operation.

2-19

CHAPTER 3

INSTALLATION AND INTERFACE INFORMATION

SITE CONSIDERATIONS

The design of the VT 100 (Figure 3-1) normally poses few constraints on selecting a place in which to
install the terminal. In most cases, any environment suitable to the operator is a satisfactory environment in which to operate the terminal. Extremes of temperature and humidity should be avoided. A
summary of VT100 guaranteed operating conditions may be found in Chapter 1.
UNPACKING AND INSTALLATION
The VTI100 shipping carton contains the following items:
VTI100 monitor

VTI100 detached keyboard
VTI100 power cord
VT100 SET-UP label

VTI100 User Guide.

To install the VT 100 perform the following steps:
l.

Remove the VT100 from the shipping carton and place it in the desired work area.

Place the keyboard in front of the terminal and plug the keyboard coiled cord into the
keyboard receptacle at the rear of the terminal (Figure 3-2).
Verify that the power selector switch shows the correct wall outlet voltage (115 V is standard
in the U.S.) and the power switch is off.
Connect the power cord to the power cord receptacle at the rear of the terminal and plug the
other end of the power cord into a nearby wall outlet.
Connect the communications cable to the appropriate communications receptacle.
Turn the power switch on. The terminal automatically performs the power-up self test and
either the ON LINE or LOCAL indicator on the keyboard will light. After approximately
one minute the cursor will be visible in the upper-left corner of the screen.

Set the desired SET-UP features outlined in the operator section of this manual.

Once the installation procedure is complete, record the SET-UP features selected on the
VT100 SET-UP label and attach the label to the underside of the keyboard.

3-1

36.8 CM
(14 1 /2 IN.)

8.9 CM

(3 1/2 IN.)

4.8 CM

(17/8 Il\l.)

L_ 11.1CM
(4 3/8 IN.)

te——20.32 CM

—

k245 cm (9 5/8 IN)—
30.56 CM (12 IN.)

(8 IN.) —

36.2 CM (14 1/4 IN))
51.4 -CM (20 1/4 IN.")

41.3 CM (16 1/4 IN))
45.7CM (18 IN.)

*MEASUREMENT TAKEN WITH THE KEYBOARD PLACED FLUSH TO FRONT OF TERMINAL UNDER UNDERCUT.
MA-1991

Figure 3-1 VT100 Terminal Dimensions

CAPTIVE

ACCESS
COVER

SCREWS (4)

EIA

COMMUNICATIONS
— CONNECTOR

LINE PRINTER

EXTERNAL VIDEO

CONNECTOR

— INPUT CONNECTOR

PRINTER

OPTION

EXTERNAL VIDEO

INDICATOR
i

—OUTPUT CONNECTOR

T//l MAIN FUSE

POWER SWITCH

MODEL + SERIAL
NUMBER LABEL

O
1

—
KEYBOARD

CONNECTOR

POWER

POWER CORD

SELECTOR

CONNECTOR

SWITCH

OPTIONAL 20mA
COMMUNICATION
CONNECTOR

MA-1987

Figure 3-2 VT100 Rear View

USER MAINTENANCE
The keyboard keys are the only moving parts of the terminal and require no preventive maintenance
by the owner. The VT100 surfaces may be cleaned with soap and water or any mild detergent. Cleaners
with solvents should not be used.
The VT100 packaging is not meant to be weatherproof; there are several openings in the case through
which liquids, coins, paper clips, and other objects can fall. Such objects would disturb the electronic

operation of the terminal if they came into contact with the circuitry. For this reason, avoid putting

drinks and metal objects on the top of the terminal, or using excessive water to clean the terminal.
Rubbing the keys with a dry or barely moist cloth should clean them. Do not remove the keycaps to
clean them more thoroughly; damage may result to the switch contacts if they are replaced incorrectly.

Keep the ventilation slots clear. Blocking these slots by placing objects on top of or under the VT 100
may cause the terminal to overheat.

3-3

INTERFACE INFORMATION
EIA Interface
The basic VT 100 operates on full duplex, asynchronous communication lines. The terminal interfaces
to the line with a 25-pin connector mounted on the back of the terminal which meets the requirements
of EIA specification RS-232-C. Table 3-1 summarizes the EIA connector signals. The following paragraphs explain each signal as used in the basic VT100.
Protective Ground - Pin 1
This conductor is electrically bonded to the VT 100 chassis. Use of this conductor for reference potential purposes is not allowed.

Transmitted Data (from VT100) - Pin 2

The VTI100 transmits serially encoded characters and break signals on this circuit, which is held in the
mark state when neither characters nor break signals are being transmitted.
Received Data (to VT100) - Pin 3

The VTI100 receives serially encoded characters generated by the user’s equipment on this circuit.
Request to Send (from VT100) - Pin 4
Asserted at all times when terminal is powered up.

Carrier Detect (to VT100) - Pin 8
Ignored at all times.

Speed Select (from VT100) - Pins 11, 19, and 23

This signal is alternately called secondary request to send. The basic VT100 maintains this line in the
asserted state at all times.
Speed Indicator (to VT100) - Pin 12

This signal is alternately called secondary carrier detect and is ignored at all times.
Transmission Clock (to VT100) - Pin 15

Ignored at all times.
Clear to Send (to VT100) - Pin §
Ignored at all times.
Data Set Ready (to VT100) - Pin 6
Ignored at all times.

Signal Ground - Pin 7

This conductor establishes the common ground reference potential for all voltages on the interface. It
is permanently connected to the VT 100 chassis.
Receive Clock (to VT100) - Pin 17
Ignored at all times.

Data Terminal Ready (From VT100) - Pin 20
Data terminal ready is asserted at all times.
Ring Indicator (to VT100) - Pin 22
Ignored at all times.

Table 3-1 EIA Connector Signals
Pin

No.

Description

]
2
3
4
5

Protective ground
Transmitted data
Received data
Request to send
Clear to send

6
7
8
9
10

Data set ready
Signal ground (common return)
Carrier detect
(Not used)
(Not used)

Same as pin 19

(Secondary carrier detect) speed indicator

13
14

(Not used)
(Not used)

Transmit clock

16
17
18
19
20

(Not used)
Receive clock
(Not used)
(Secondary request to send) speed select
Data terminal ready

21
22
23
24
25

(Not used)
Ring indicator
Same as pin 19
(Not used)
(Not used)

Electrical Characteristics

VT100 Output Voltages — On all signals designated ““from VT100,” the mark or unasserted state is —6.0
V to -12.0 V; the space or asserted state is +6.0 V to +12.0 V.

VT100 Input Voltages - On signals designated ‘“‘to VT100,” -25.0 V to +0.75 V or an open circuit is
interpreted as a mark or unasserted state, and +25.0 V to +2.25 V is interpreted as a space or asserted
state. Voltages greater in magnitude than 25 V are not allowed. These levels are compatible with EIA
STD RS-232-C and CCITT Recommendation V.28.
Optional 20 mA Current Loop Interface
In most current loop applications, the VT 100 is connected in a passive configuration - that is, current

is supplied to the VT100. In this mode, the transmitter and receiver are both passive, both optically
isolated, and the transmitter goes to the mark state when power is turned off.

Conversion from active to passive (or vice versa) requires moving a slide switch.

3-5

In active mode either the transmitter or the receiver or both may be connected so that the VT100

sources the 20 mA of current. In active mode isolation is not present and the transmitter goes to the
space state when power to the VT100 is turned off.
Figure 3-3 shows the 20 mA current loop interface connector mounted to the access cover and lists the

individual pin assignments.

The electrical characteristics of the 20 mA current loop interface are shown below.
Transmitter

Open circuit voltage
Voltage drop marking
Spacing current
Marking current

Min
50V

Max
50V

20V

20 mA

2.0 mA
50 mA

Receiver

Min

Max

Voltage drop marking

2.5V

Spacing current
Marking current

15 mA

3.0 mA
50 mA

In addition to the above specifications for passive operation, active mode places the transmitter or
receiver in series with a source of 17 V £ 5 percent and 660 ohms.
External Video Connections

In addition to the EIA interface, the VT 100 can easily interface to external video devices. The video
devices may act either as a slave to the VIT100 when connected to the composite video output or
provide synchronized video to the VT 100 video section when connected to the video input. The external video connectors are the two female BNC connectors located on the back of the terminal just
below the EIA connector. The upper connector, J8, is the video input while the lower connector, J9, 1s
the video output.
Composite Video Output (J9)

The composite video output provides RS170 output generated by combining the video signal with a
composite sync signal. The output contains all video data appearing on the VT 100 screen except that
video which comes from J8. The output has the following nominal characteristics (Figure 3-4):
1.

Output impedance = 75 ohms, dc-coupled

Synclevel

=0V

Black level

= approximately 0.3 V when loaded with 75 ohms

White level

= approximately 1.0 V with a 75 ohm load

The composite sync waveform conforms to EIA RS170 standards. The vertical interval is
composed of six equalizing pulses, six vertical sync pulses, and six more equalizing pulses.
The timing is as follows:
Equalizing pulse width
Vertical pulse width
Horizontal pulse width
Horizontal blank width

233 45+ 50 ns

=
=
=

27.28 us + 200 ns
4,71 ys + 50 ns
11.84 us + 50 ns/80 column
mode

12.34 us £ 50ns/132 column

mode

Front porch

1.54 us £ 50 ns.

TERMINAL
ACCESS

T/COVER

PIN ASSIGNMENTS
1

- TEST NEGATIVE

2 - TRANSMIT -

3 - RECEIVE -

5 - TRANSMIT +
7 — RECEIVE +

8 - PROTECTIVE GROUND

20mA CURRENT

__—
123

LOOP CONNECTOR

Figure 3-3 20 mA Current Loop Interface

MA-1992

EVEN FIELD:

60 Hz

VERTICAL BLANKING INTERVAL

NON-INT = 22 SCANS

60 Hz INT

= 22 SCANS

50 Hz

= 75 SCAN
o0 o NON-INT
INT
e 2CAN2

LAST DISPLAYED SCAN OF
PREVIOUS FIELD

FIRST OF 240 DISPLAYED
SCANS IN

60 Hz NON-INT = 2 SCANS

60 Hz INT

= 2 SCANS

50 Hz INT

= 24 SCANS

50 Hz NON-INT = 25 SCANS

1.0V

EVEN FIELD

/\/
T

RN
R

TIME ——»

START OF

ODD FIELD:

H PERIOD = 63.56 us + .01%

EVEN FIELD

50 Hz INT = 75 SCANS
60 Hz INT

SCANS IN ODD FIELD

2.5 SCANS

50 Hz INT = 24.5 SCANS

1.0V

TIME ———»

| START OF

‘.‘

F H PERIOD = 63.56 us + .01%

ODD FIELD
NOTES:

NON-INTERLACED

EVEN

FIELD

UOUSLY,

AND

OPERATION

REPEATED

THE

ODD

THE

CONTIN-

FIELD

NOT

OPERATION

THE

USED.

THE

INTERLACED

EVEN FIELD ALTERNATES WITH THE ODD

H BLANK {1 1.84 us + 50 ns / 80 COLUMN
12.34 us £ 50 ns

FIELD.

/ 132 COLUMN

ALL FIELDS CONTAIN

—s
je—

BRIGHT =

1.00 V—»

NORMAL =
DIM =

79 V—»
.64V —»

BLACK = .29 V —»

swc= 00w

FRONT PORCH = 1.54 us + 50 ns *O’ 4‘
H SYNC = 4.71 us + 50ns

240 DISPLAYED

SCANS.

VRN

EQ = 2.33 us 3: 60ns -’l l‘-

‘0‘

) S

"-V SYNC = 27.28 us

+ 200 ns

—>

r—H PERIOD = 63.56 us £ .01%

MA-1993

Figure 3-4 Composite Video Output

Video Input (J8)
An analog signal applied to the video input is “ORed” with the internal video signal such that the

o
—

beam intensity at any point on the screen corresponds to the intensity of that signal which tends to
make the beam brighter at that point. A video signal on this input affects only the internal screen and
does not appear on the composite video output. This input has the following nominal characteristics:

Input impedance = 75 ohms, dc-coupled
Black level = 0 V
White level = 1.0 V
Maximum continuous input = £2.0 V.,

The external video source must be synchronized to the VT100; it may do this by referencing the
composite sync on the composite video output. This means that the VT 100 video input will not synchronize with any composite video source including the composite video output of another VT100.

3-8

CHAPTER 4
TECHNICAL DESCRIPTION

4.1
INTRODUCTION TO VT100 TECHNICAL DESCRIPTION
This section describes the contents of the technical description chapter and provides a technical overview of the terminal.

4.1.1
Scope of Chapter
This technical description is intended to provide an understanding of the terminal operating principles
for Field Service, depot repair, and engineering personnel. The description considers the terminal to be
several functional or replaceable subunits. Each subunit is described in its own section. Several subunits interact. Those interactions are discussed in the section about the subunit most involved in the
particular process. For example, power-up involves the nonvolatile RAM but is described in the microprocessor section. Scrolling has its own section because it is a complex process that involves the
microprocessor and video processor equally.
4.1.2 Order of Presentation
Each section describes the hardware first and the associated firmware operations second. This section

contains a block diagram level discussion of the terminal hardware and firmware. More detail is
provided in the functional block descriptions in later sections. Refer to the VT 100 series Field Maintenance Print Set, No. MP00633, for circuit details while studying this manual.
4.1.3

Definition of Terms and Abbreviations

Many terms are written out the first time they appear, with an abbreviation or mnemonic in parentheses after it. The abbreviation is generally used after that. There is a glossary of abbreviations and
signal names in the appendices of this manual. Numbers may be given in binary, octal, decimal, or
hexadecimal (hex). The normal form will be decimal for scalar or ordinal values, and hex for data and
addresses. Numbers are subscripted B for binary, Q for octal, H for hex, and no subscript for decimal.
4.1.4

Hardware Introduction
The VTI100 is a complete computer input and output terminal that has a keyboard like a typewriter

and displays its data on a video screen. It fits into two compact packages; the keyboard is flexibly

attached to the main cabinet by a coiled cable. Refer to Figure 4-1-1.
The terminal consists of four basic components (not including enclosures) plus two important options.
The components are the terminal controller, the keyboard, the CRT monitor, and the power supply.
The options are the advanced video option and the current loop adapter option.

CRT

MONITOR

TERMINAL CONTROLLER
e MICROPROCESSOR
e

LED’S

KEYBOARD

VIDEO PROCESSOR

RAM

ROM

NVR

® UART

STP

CONNECTOR
e

EIAI/O

ADVANCED

VIDEO

OPTION

EgggENT

ADAPTOR
SAL

TOHOST

POWER

SUPPLY

MA-4656

Figure 4-1-1 VT100 Components

The terminal controller is a single pc board module that manages all displays and all communication.

Everything else connects to it. The terminal controlller contains these functional components:
A microprocessor to manage terminal operations

A video processor for converting data to recognizable patterns

3072 bytes of random access memory (RAM) for screen data storage and microprocessor
scratch memory

8192 bytes of read only memory (ROM) containing the microprocessor’s programming to
operate the terminal with its particular features

A nonvolatile RAM (NVR) to store the user-settable operating features without requiring
hardware switches

An asynchronous serial receiver-transmitter (UART) for data exchange with the computer

EIA level converters to adapt the on-board input and output (I/0O) signals to the communications interface

A special connector, the standard terminal port (STP) that allows a plugged-in option to
intercept terminal communications inside the terminal enclosure.

The keyboard is the typewriter-style input device for the operator. It has a loudspeaker for user feedback keyclicks and bells, and indicators that show internal states of the terminal.

The CRT monitor is a video screen that displays exchanges between the operator and the computer. It
can display data in two modes: 80 characters by 24 lines, or 132 characters by 14 lines (or, with the
AVO, 132 by 24). With the control circuitry on the terminal controller board, the CRT can perform
many special character display functions.

The power supply converts the ac power line to the four dc voltages required by the terminal. It has a
switching regulator for highest efficiency and coolest operation.

The advanced video option provides greater display capacity, plus it can carry extra firmware for the
expanded functionality of other products in the VT100 series.

The current loop adapter option converts the EIA output of the terminal controller to a more noise
immune standard when longer distances between the terminal and the computer are required.
4.1.5
Block Diagram Description
Figure 4-1-2 shows the VT 100 terminal as a set of functional blocks. The rest of this section describes
these blocks in greater detail.

4.1.5.1
Microprocessor — A microprocessor manages all terminal input and output operations. It also
provides the intelligence that enables the VT100 to respond to and generate a wide range of ANSI
control functions, and to emulate the characteristics of the VT52. Several of the microprocessor’s
program functions are effectively in series with data paths in the terminal. These functions have their
own blocks in the functional block diagram to clarify the processes involved. These blocks are shaded
to indicate that they are program functions or that the microprocessor controls data transfers between
the blocks. The microprocessor is a computer with its instructions in program ROM (read only memory) and working memory in the scratch RAM (random access memory). Terminal parameters for
start-up are stored in the nonvolatile RAM (NVR). The advanced video option (AVO) normally
contains extra RAM as described below but can also contain extra program ROM.
4.1.5.2

Program ROM - The VT100 program ROM is an 8K X 8 memory containing instructions
and data tables for the terminal’s microprocessor. Memory comes in four 2K packages (later VT 100s
may have a single 8K package). Checksum data stored in each ROM allows the terminal to confirm

the condition of its programming at self-test.
4.1.5.3

Scratch RAM - The scratch RAM is the portion of RAM on the terminal controller that is
not used for the screen RAM. That is, the RAM is 3K bytes long, but only about 2.3K bytes are used
for screen display. The rest of the RAM contains the microprocessor stack, SET-UP data, various flag
bytes, the communication SILO, the keyboard buffer, and so on.

4.1.5.4 Nonvolatile RAM - The nonvolatiie RAM (NVR) does not lose its data when its power is off.
It stores all user-settable features and parameters and the answerback message so that they are avail-

able each time the terminal is turned on. Even the screen intensity can be stored. There are no mechanical switches needed for configuration.
4.1.5.5

Advanced Video Option - The advanced video option (AVO) contains the 1K X 8 of extra

screen RAM needed to expand the display from 14 lines of 132 characters to 24 lines, plus a 4K X 4
RAM to store an extended set of attributes for all characters. The AVO also contains an additional

segment of video processor to manage the four extra bits of data. Sockets for ROMs and jumper- or
switch-programmable decoders allow expansion or overlay of program memory.
The AVO is a replaceable subunit of the VT 100.

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4-4

4.1.5.6 Keyboard - The keyboard is the user’s input device to the terminal. The keyboard’s output is a
serial data signal that travels along the same wire as data coming from the terminal. The keyboard
contains a bidirectional interface circuit, a set of keyswitches arranged like a typewriter, circuits to
send the key information to the interface, LED indicators, and a small loudspeaker for keyclicks and
bells. The connection to the terminal is a 3-wire coil cord carrying signals, power, and ground.
The keyboard is a replaceable subunit of the VT 100.

4.1.5.7 LEDs - The terminal can inform the user of some internal conditions such as on-line or local
and keyboard locked through the LEDs on the keyboard. The LEDs also may indicate the location of
a failure during self test and are user programmable during normal operation.

4.1.5.8 Keyboard Translator — The output for each key i1s a number that represents the key’s location
(address) in the keyboard switch matrix. The microprocessor’s keyboard translator translates the address to the industry-standard ASCII code.
4.1.5.9

Transmit Buffer - The ASCII codes wait in a transmit buffer until they can be transmitted.
Some keys (such as the numeric keypad in application mode) produce control functions that are three
bytes long. The transmit buffer is nine bytes long and thus can store at least three keys of any kind.

4.1.5.10

Communication Transmitter - The communication transmitter is one-half of a programmable universal synchronous/asynchronous receiver transmitter (PUSART) and its associated circuitry and firmware routines. The PUSART is programmed to place data in a standard asynchronous
format by adding control and error detection bits to the original byte. The communication transmitter

thus takes the parallel ASCII keycodes out of the keycode buffer, converts them to serial form, and
delivers them to the EIA interface.
4.1.5.11

Communication Receiver — Data that the host sends to the terminal enters the communication receiver which is the other half of the PUSART. The PUSART accepts serial data from the

interface and converts it to parallel form. The PUSART also checks for errors and records them in a
status byte. The microprocessor reads the data and then the status byte to confirm the correctness of
the data. If an error is detected, a checkerboard is displayed instead of a character to symbolize the
error. If the microprocessor is busy managing the display, it devotes only enough time to the communication receiver to get the incoming code and check it for special codes requiring immediate action.
4.1.5.12
SILO - The rest of the incoming codes are stored in a part of RAM memory called a SILO.
This memory maintains the order of the data as it arrives; the first data to arrive leaves first. This
memory gives incoming data a place to wait when the microprocessor cannot transfer data from the
communication receiver to the screen RAM as fast as it arrives. The SILO control routine checks the

filling of the SILO and can issue XON and XOFF commands to the host to try to keep from overfilling. (XON and XOFF are explained in Section 4.3, Communication.)
In local mode, data from the keyboard bypasses the communication receiver and transmitter and the
SILO.
4.1.5.13

Control Function Parser - When the microprocessor has enough time, it takes data from the
SILO and puts it through a control function parser routine in the microprocessor. Each code is tested
to see if it is in the control range (<20H or 7FH). If it is, the microprocessor acts on it immediately.
Line feed, for example, causes a one line scroll. If the code is 1BH (escape), more codes are read from
the SILO until the characters that define a control function are seen. Then the microprocessor executes
the control function immediately or discards it if it is not a valid function. Noncontrol codes are
ignored by the parser and are written into the screen RAM.

4.1.5.14

Screen RAM - The screen RAM is a memory that stores data for display on the screen

(CRT monitor). The memory is organized according to the SET-UP line iength specifications. Basic
terminal memory can hold 24 lines of 80 characters or 14 lines of 132 characters. With the extra
memory provided by the advanced video option, the screen size may increase to 24 lines of 132 characters and four additional bits are appended to each character location to allow expanded character

attributes. (A character attribute modifies the display of that character relative to the preset values for
the entire screen.)

Most of the time, the screen RAM is readable and writable by the microprocessor. For about 10
percent of the time, during the first scan of each 10 scan line of characters, the video processor silences
the microprocessor and takes full control of the screen RAM, providing its own addresses to access the
memory. This complete control of memory (by a device other than the microprocessor, which is normally in control) is called a direct memory access (DMA). The DMA ailows fast access of data in
memory because the microprocessor does not have to perform all the steps of addressing, reading, and
writing to a destination. The video processor needs the fast access because the data rate required to
display a line of characters on the CRT is greater than the microprocessor can handle.
4.1.5.15
Video Processor - The microprocessor puts displayable data in the screen RAM. The video
processor direct memory accesses (DMAs) data a line at a time from the RAM. It converts the ASCII-

encoded data into streams of pulses which, when converted to light on a CRT screen, appear to form
characters on the screen. Custom ICs provide the complex timing and control signals required for this
conversion. The video processor can be programmed by the user to perform the conversion at different
rates (called refresh rates) to minimize flicker at different power line frequencies. A number of other
aspects of video processor operation can be programmed as well.
4.1.5.16
CRT Monitor - The cathode ray tube (CRT) monitor is a simplified monochrome television
set. It converts electrical pulse streams into dots of light by exciting a phosphor on the face of the tube
with a moving electron beam. A video input from the video processor enters a cathode drive circuit
that regulates the strength of the electron beam. The cathode driver is a linear amplifier that allows the
CRT to display different intensities (gray scale). The monitor uses timing pulses from the video processor to drive the horizontal and vertical electron beam deflection circuits. These circuits cause the beam
to travel down the screen slowly while rapidly moving sideways to draw horizontal traces called scans.
This beam movement produces a pattern which is called a raster and the display system is called raster
scanning. Because the beam repeatedly passes by each location on the screen, the video processor, by

synchronizing its output with the motion of the beam, can make rows of dots of light align to form
characters.

The screen does not hold its image after the electron beam has painted dots on it. For the eye to
perceive it as continuously illuminated (i.e., without flickering) the screen must be repainted (refreshed) repeatedly some 30 or more times per second. Also, stray magnetic fields and electrical noise

at the power line frequency can cause distortions in the display. If the refresh frequency is different
from the power line frequency, the distortions appear to move up or down the display. This is very
noticeable. Most distortions disappear by matching the refresh rate to the power line frequency. The
VT100 can refresh at either of the two world power frequencies, 50 or 60 Hz, satisfying both flicker and

distortion requirements. (VT100 refresh is not locked to the power line but is close enough to conceal
most distortions.)

The CRT monitor, the monitor circuit board, and the flyback transformer are replaceable subunits of
the VT100.

4-6

4.1.5.17
Power Supply - The VT100 power supply provides enough power to run the terminal and a
few options. It is a switching supply to allow highest efficiency and to minimize the heat load on the
rest of the terminal. It rectifies line voltage directly (without a transformer), and chops the resulting
high dc voltage with a transistor at about 30 kilohertz. This ultrasonic ac is stepped down in a relatively tiny transformer and then regulated at low voltage to give the various outputs.
The power supply is a replaceable subunit of the VT 100.
4.1.5.18
Standard Terminal Port - The standard terminal port (STP) is a shorting connector in series
with the communication port, the modem control lines, and some power and timing lines. By con-

necting to the terminal through this port, options can exchange signals with the terminal controller or

intercept terminal-host communications from inside the terminal cabinet.
4.1.5.19
EIA Interface - The Electronic Industries Association (EIA) interface used on the VT100 is
the RS-232-C unbalanced bipolar voltage standard. The terminal controller has two types of ICs that
provide conversion between EIA levels and the TTL levels used on the controller board. One IC is a
line driver that outputs EIA levels for TTL inputs, and the other senses the EIA levels on the input line
and converts them to TTL.
4.1.5.20

Current Loop Interface Adapter — The current loop adapter option plugs into the terminal
controller board and mates with the EIA voltage interfaces to convert the terminal to 20 milliampere
current loop interfaces. The current loop interfaces can be individually selected to be active or passive.

The 20 mA adapter is a replaceable subunit of the VT100.

4.1.6 Firmware Introduction
Figure 4-1-3 portrays the VT100 as a system with four levels of operation.
At the deepest level, the background routines continually repeat to manage functions that do not
require precisely timed responses. The keyboard processor commands the keyboard to perform address scans, controls the bell and LEDs, and manages the conversion of key information from hardware-dependent codes to ASCII. The transmitter routine manages the transmission of ASCII data to
the host. The received character processor examines incoming data, manages the SILO, initiates special functions as specified in the data, and writes displayable data into the screen RAM. When the
terminal is in local mode, a logical shortcut bypasses the communication process and allows the keyboard data to enter the received character processor directly.

The background routines work on the internal buffers, registers, and flags which are logical devices
located in hardware and RAM. These are physical locations in hardware that contain information
placed there the hardware and by the firmware. The key buffers store up to three key addresses for the
keyboard processor to pass through the transmit buffer to the transmitter routine for transmission to
the host. The screen Ram, which stores the displayable data, is the largest segment of RAM. The
scrolling flags contain data for the scrolling process in the video processor. The SILO stores data
coming from the host in case the received character processor cannot transfer data to the screen RAM
as fast as it arrives. The Send XOFF flag, set by the SILO manager, signals the transmitter routine to
send the XOFF code to the host to halt transmission and prevent SILO overflow.

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Interrupt routines are segments of the firmware that take precedence over other business in the microprocessor because of the short-lived nature of the data that they handle. The Key Down interrupt
routine is initiated by the appearance of data at the keyboard control circuits. It instructs the microprocessor to get the key address from the keyboard UART and put it in the key buffer. The Vertical
Frequency interrupt routine occurs every 50th or 60th of a second and provides synchronization of
video routines with the actual display timing. The Receiver interrupt routine moves incoming data

from the communication transceiver to the SILO.

At the exterior level of the VT 100 system, the hardware responds to the firmware by exchanging data
between the user and the host computer in forms that are understandable to each.

4.2

MICROPROCESSOR

The VT100 has an 8080 microprocessor at the heart of its intelligence. The 8080 performs all the usual

functions of a stored program computer, fetching instructions and data from ROM and RAM and

responding to service requests from various devices in the system. Because of technical limitations in
the implementation of the microprocessor hardware, some high speed counting and timing circuits and
some power circuits are located in peripheral ICs made with a different semiconductor technology.
These components are bipolar (8224, 8228) while the 8080 is NMOS.
4.2.1

8080 Microprocessor

The 8080 (Figure 4-2-1) contains a set of general and special purpose registers (the register array),

timing and control logic which responds to machine code instructions, and an accumulator and arithmetic logic unit that perform the computations associated with the microprocessor operation.
The stack pointer is an important register that points to the bottom of the stack. The stack is a lastin/first-out area in RAM that stores information about the current process when a subroutine or
interrupt branches away from the current instruction sequence. By storing this information at the

beginning of an interruption and restoring it at the end of the interruption, the 8080 can continue the
main program without any disturbance. This is the meaning of the interrupt process as it applies to the
interrupt-driven routines mentioned in the firmware block diagram in Figure 4-1-3.

Most of the pins on the 8080 are tristate data and address lines. Four pins are power supplies and
ground. The others, briefly, are:
HOLD - an input that lets another device get control of the buses when the 8080 finishes the current
machine cycle. Hold Request from the video processor is the input signal.
HLDA - Hold Acknowledge output indicates that the buses will be given up for the Hold state.
INT - Interrupt Request input accepts INTR H signal that causes read of the interrupt vector address

and branch to it.
READY - input for use with slow memory or 1/O. If low, the 8080 enters the wait state (an indefinite

portion of a machine cycle). It is not used in the VT100.
WAIT - output acknowledging the wait state. Not used by VT100.

INTE - Interrupt Enable output indicates whether interrupts have been enabled or disabled with the
related instructions or by servicing an interrupt request. Not used by VT100.
0/1, 0/2 - Clock phases 1 and 2. Inputs to drive the 8080.

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SYNC - output that indicates the beginning of each machine cycle. Combines with clock in the 8224 to
produce Status Strobe (STSTB).

RESET - clears the program counter so that when it is released, program starts at location zero. Used
to initiate power-up sequence and self-test.
WR - Write output controls memory and 1/O writes by indicating the stable period of the data bus
during a write instructior..
DBIN - Data Bus In output indicates that the data bus can accept data.
For more detail, see Intel’s 8080A manuai.
4.2.2

Data Bus and System Controller

The microprocessor data bus passes directly to the 8228 bus driver and system controller. This device
provides TTL output buffering and level translation for the MOS 8080 bus. Because of the large
number of devices on the data bus, the drive capability of some devices would be exceeded at times 1f
all devices were on the same bus. (The keyboard UART is the weakest low-level current driver.) To
distribute the load. the bus is split into those devices that communicate bidirectionally or are only read
by the microprocessor, and those that are only written into. Read and writable devices are on the
bidirectional data bus (DB). The write-only devices are driven by a one-way bus buffer and are on the
data output (DO) bus. The terminal controller block diagram (Figure 4-2-2) shows which devices are
on each bus.
The ROMs do not have sufficient high-level current capacity to drive all of the other inputs on the bus.
Inactive devices have their outputs tristated but their inputs still draw enough current to accumulate a

significant load over the entire bus. Pull-up resistors are connected to the bus to provide the additional
current required. Their resistance is seiected to supply enough current to meet high level needs on the
bus without exceeding the low level sink capacity of any driving device.
Pull-up resistors are used on the output-only DO bus because the baud rate generator, a MOS device,
has an input threshold higher than TTL driver ES58 is guaranteed to deliver. Pull-up resistors ensure

that the data lines rise enough.
An additional function of the 8228 is a combinational logic decode of the 8080 status byte. This byte,

output by the 8080 at the beginning of each machine cycle, contains flag bits indicating the nature and

function of the cycle. The byte is latched into the 8228 by the Status Strobe (STSTB) signal from the
clock generator. In combination with three control output bits from the 8080, the system controller
produces Interrupt Acknowiedge (INTA) and Memory and Input/Output Read and Write (MEM
WR,RD; I/O WR,RD). These signals reduce the external decoding requirements while saving pins on
the 8080 package.
When the video processor asserts Hold Request during a direct memory access (DMA) of the screen

RAM, the 8228 floats its outputs. Since these include the memory control signals, the video processor
must provide its own memory control. The DMA Enable signal, buffered into the MEM RD line by

gate E28 (pin 13), provides memory read enabling during the DMA. The other control signals are
pulled high by the pull-up resistors.

4-11

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4.2.3

Clock Generator

The 8224 provides the asymmetrical two-phase clock required by the 8080 logic. Its running frequency
is crystal-controlled. An LC circuit on the tank input improves the crystal’s mode stability. The capacitor in series with the crystal compensates for internal phase shifts in the 8224 at the high operating
frequency. The 24.8832 MHz crystal frequency gets divided by 9 to produce a 361.69 ns clock period.
The buffered TTL phase 2 output clocks the PUSART and the baud rate generator. 361.69 ns is the
system clock period for the microprocessor.

The sync signai from the 8080 combines with an internal clock phase to produce the Status Strobe

(STSTB) during the last ninth of the first state of each machine cycle. STSTB latches the status byte
into the 8228 system controller.
The Ready input is not used in the VT100. It is an asynchronous input that gets synchronized to the
machine cycles in the 8224. The synchronized signal can cause the microprocessor to enter a wait state
during a memory access to wait for slow memory to respond. Memory used in the VT100 matches the
processor speed so Ready is not used.
The Reset input i1s a Schmidt trigger. Its input is the +5 volt supply delayed by an RC circuit with a

diode bypass for fast discharge. The Reset input is held low until well after all power supplies have
settled. When the capacitor volitage reaches the Schmidt threshold, reset is released and the microprocessor begins operation at memory iocation O {the start of the firmware ROM). The inverted and
noninverted reset signals clear other portions of the terminai controller.
4.2.4

Bus Timing

The bus timing diagram in Figure 4-2-3 illustrates the basic time relations between the address, data,
and control lines in the microprocessor system. The figure distinguishes between write and read cycles,
with the exception of the three top lines. These show the constants of the system: the two clock phases

irom which all timing is derived, and the address bus, that always provides the current address for

either xind of cvcle earlv in the cycle. Numbers on the diagram
imum/maximum nanoseconds between signals for normal operation.

represent

specified

min-

Starting with the write cycle, note that the status strobe signal (STSTB L) shown in the read section

occurs at the same point in the write cycle. Therefore, the status strobe latches the status byte into the
8228 during the first clock cycle. The 8228 delivers the decoded Memory Write L or 1/O Write L
(MEMW or [OW) signals in the third clock cycle when data to be written is stable. The 8080 Data Bus,
DB Bus, and DO Bus graphs show the propagation delays between the three buses. The 8080 bus is the

output pins on the chip. The DB bus is the output of the buffered 8228 bidirectional bus, and the DO
bus is the unidirectional buffered output-only bus.
In the read cycle, the Memory Read L signal (along with I/O Read L and Interrupt Acknowledge L:
MEMR, IOR, INTA) starts early to enable the chip selects and allow the data buses to stabilize. Data

Bus In (DBIN) goes high before data settles but does not latch data into the 8080 until its falling edge,
when data is settled. The two bus graphs show the assertion of stable data and also show the delay
through the bidirectional bus buffer to the 8080 data bus.

4.2.5 Microprocessor Memory
The basic terminal controller contains 8192 bytes (8K) of program ROM and 3072 bytes (3K) of static
RAM. (One byte = eight bits.) The original board utilizes four 2K X 8 ROM ICs; later versions may

use a single 8K X 8 ROM. The RAM is six 1K X 4 ICs arranged in pairs. The microprocessor can
address up to 64K memory locations. Some of these locations are reserved for future expansion. The
memory map of Figure 4-2-4 shows the portions of addressable space that are reserved and also those
areas that are available for new applications.

4-13

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DESCRIPTION

PHYSICAL

LOCATION

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0000

8K X 8

BASIC ROM

BVB

1 FFF

2000

3K X 8

SCREEN AND

SCRATCH RAM

BVB

1K X 8

AVO SCREEN RAM

AVO

4K X 4

ATTRIBUTE RAM

AVO

16K X 8

UNASSIGNED

2BFF
11

2C00

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12

3000

3FFF
16

4000

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32

8000

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2K X 8

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EXPANSION (USE
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8K X 8

PROGRAM MEMORY
EXPANSION (USE
8K X 8 ROM)

16K X 8

UNASSIGNED

AVO

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CO00

FEEF

MA-4270

Figure 4-2-4 Memory Map

4.2.5.1

Memory Map - The basic terminal controller board contains 8K of program ROM and 3K

of screen and scratch RAM. These account for the locations from 0000H to 2BFFH in memory. The
advanced video option adds another 1 kilobyte of RAM (2CO0H to 2FFFH) to increase the number of
characters that can be displayed. The AVO also contains additional memory for character attributes.

This memory is only 4 bits wide, but to address each location in correspondence with each of the 4K
characters, it uses another 4K of addresses from 3000H to 3FFFH.
The next 16K locations (4000H to 7FFFH) are unassigned. However, 4000H to 4FFFH can be ad-

dressed by the video processor using the DM
A address counters so 4000H to 4FFFH could be used for
additional screen RAM with 5000H to SFFFH as associated attribute storage.
Above 7TFFFH is an 8K area intended for additions or changes to the program ROM in 2K segments

and above that is an area intended for the same purpose but in one 8K segment. The top 16K are
unassigned.
4.2.5.2
Memory Devices - Each ROM has three ANDed chip select inputs that are mask-programmed to be either active-high or active-low, eliminating the need for external inverters. The programming provides 1 of 4 decoding of the two address lines A11 and A12. The third chip select line is
common to all four ROMs. In later VT 100s jumpers W2 and W3 can be used to select either a high or
low assertion for this single chip select to allow for 64K ROMs that do not have a programmable chip
select. Table 4-2-1 shows the addressing of the ROM:s.

4.2.5.3
ROM Decoding - The program ROM is enabled when the top half of memory decoder E31 is
enabled and the correct address space is requested by the microprocessor. MEM RD or MEM WR
from the 8228, in the absence of MEM DISABLE, enables the decoder. The ROM is in addresses OH
to 1FFFH, so A13 (the 8K bit) is not asserted during ROM reads. Bit A12 is low or high for 0-4K or
4-8K sections of ROM. The decoded outputs from both states are ORed to provide one of the select

signals for the ROM. Then bits A11 and A12 at two ofthe chip select lines enable the outputs in one of
the 2K segments. The low 11 bits address one of the 2K bytes in the enabled ROM. If the program is in
one 8K ROM, All and A12 are used as regular address lines; only one chip select line enables its
outputs.

4.2.5.4
RAM Decoding - If A13 is asserted, the memory space between 2000H and 3FFFH is being
addressed. The ROM outputs are disabled and the decoded output from the top half of the decoder
enables the bottom half. Now bits A10 and A11 are decoded to select 1K segments of the screen RAM.
The 1K X 4 RAMs are paralleled in pairs to make each location 8 bits wide. There is 3K on the basic
video board. The fourth 1K is located on the AVO; its addressing is decoded separately.
4.2.5.5
Memory Disable - Memory Disable turns off all memory on the terminal controller board. It
is used by options that plug into the advanced video option connector:
1.

To replace (overlay) existing memory,

To disable the terminal controller memory when using memory above 4000H (since the
terminal controller does not decode A14, Al5J).

The advanced video option can contain overlaying program memory. This is a set of address locations
that the AVO can be jumper-programmed to decode and provide data for. Since the main memory
may also be decoding the same location, the AVO must assert MEM DISABLE to disable the main
memory (ROM and RAM) so that only one data byte is asserted on the bus.

4-16

4.2.6 1/0 Decoding
The I/O address space is divided into two regions: one, containing the 8251 PUSART, has address bit
AO1 always low; the other region contains all other 1/0 devices and has bit AO1 always high. The list of

I/O addresses in Table 4-2-2 illustrates this by the presence of hex 2 in the low half of each nonPUSART address byte.
|
4.2.6.1

PUSART Read and Write - When bit A01 is low, the PUSART is enabled. The I/O RD and

WR signals from the 8228 control the read or write operation. Address bit A0O selects either the
command or data register for the

1/O operation.

4.2.6.2

1/0 Read and Write - When bit AO1 is high, the PUSART is disabled. Bit AO1 high is one of
two signals required to enable the I/O write decoder (E27). /O WR is the other signal. Address bits
A05, A06, and AO7 select one of the seven writable 1/0 devices. These are the baud rate generator, the
brightness control D/A latch, the NVR latch, the keyboard UART transmit buffer, the DCOI1 and
DCO012 video processor chips, and the graphics processor data port.

Table 4-2-1 ROM Chip Select Addressing

Address

Chip

ROM

Line 11

Line 12

Select 2

Select 3

Selected

0
1
0
1

0
0
1
1

Active Low
Active High
Active Low
Active High

Active Low
Active Low
Active High
Active High

Table 4-2-2 List of Hex 1/0 Addresses
READ OR WRITE
OOH
PUSART data bus
OlH
PUSART command port

WRITE ONLY (Decoded with I/O WR L)
02H
Baud rate generator
42H
Brightness D /A latch
62H
NVR latch
82H
Keyboard UART data input
A2H
Video processor DCO012
C2H
Video processor DCO11
E2H
Graphics port

READ ONLY (Decoded with I/O RD L)
22H
Modem buffer
42H
Flags buffer
82H

Keyboard UART data output

4-17

1
2
3
4

Only three I/O devices are readable so their addresses were chosen to allow read decoding directly
from the three address lines. When the 8228 asserts /O RD, 1/O WR deasserts and decoder E27 is

disabled. I/O RD enables the gates in E34 to allow reading of the keyboard UART receive buffer, the
flag buffer, or the modem control signal buffer, depending on which address bit is asserted.
4.2.7

Interrupt Vector
When any of the three interrupting devices (communication receiver, vertical frequency, or keyboard)
sets Interrupt Request (INTR H) through gate E23, the current instruction is completed and then the
microprocessor sets its Interrupt Acknowledge (INTA) status bit and performs an instruction fetch.

The address requested in the fetch is the contents of the program counter. Its value is ignored in the

interrupt process, but it is not incremented, as it would be in a normal fetch cycle. The INTA bit is
decoded from the status word in the 8228 system controller; it enables the tristate interrupt vector
buffer (E41) which then presents a restart (RST) instruction to the data bus. Main memory does not
conflict with the vector buffer because the 8228, in decoding the interrupt status word, does not produce the memory read or write command bits needed for address decoding. (Refer to Table 4-2-3.)

Table 4-2-3

Interrupt Addresses

O0OH
O8H

Power-up (Not hardware driven)
Keyboard

10H
18H
20H
28H
30H
38H

Receiver
Receiver and keyboard
Vertical frequency
Vertical frequency and keyboard
Vertical frequency and receiver
Vertical frequency, receiver and keyboard

The RST instruction disables further interrupts, pushes the current program counter contents (the
location of the next instruction in the interrupted program) onto the stack and decrements the stack
pointer. Then the program counter is loaded with the bits in the address field of the RST instruction.
This field is produced by the interrupt signals of the interrupting devices. The signals are passed onto
the data bus as bits in the address field (bits 3, 4, and 5). The rest of the instruction is hard-wired
through diodes that supply high level to the other data bits during INTA and that are reverse-biased to
isolate these data bus lines when the vector buffer is inactive.
The RST address field, when mapped into the same bit locations in the program counter, defines a set
of eight 8-byte long memory spaces at the beginning of the memory. The first address, O, is the starting
point for the terminal controller program and is not used for interrupts. The program is normally
started by a hardware reset signal that sets the program counter to 0. It can also be started by an escape
sequence that the host can send to force the program to jump to zero, or in SET-UP mode the RESET
key can be pressed. The other seven memory spaces, starting at 8, 16, etc., contain jumps to places in an
interrupt handling routine that can mediate requests for service from any of the seven combinations of
interrupting devices.

At the end of the interrupt service routine, the stack is popped, interrupts are enabled, and the interrupted program continues.

Early VT100s can disable the receiver interrupt by programming D4 in the NVR latch. However, thi.s
is never used by the VT100. Later VT100s instead, have the ability to add a Communications Transmit
Buffer Empty interrupt by adding W6. The 8080 would then have to distinguish transmit and receive

interrupts by testing the transmit flag on the flag buffer. This provision is not used on the VT100.

4-18

4.2.8

Power-Up and Self-Test

When power is first applied to the terminal controller board, the reset circuit in the 8224 holds the
microprocessor in a halt state. Within a second, after the voltages stabilize in the power supply, the RC
network at the reset input allows the input voltage to rise to the switching threshold of a Schmidt
trigger. Then the reset is released with the 8080 program counter set to 0. The low 64 bytes of program
are reserved for the eight interrupt service routines which can be addressed by the restart instruction
(see previous section). The low 8 bytes start the power-up routine by disabling the interrupts, setting up
the stack pointer, and then going immediately into the self-test routines.
Assuming there are no hard logic failures present on the board, the microprocessor attempts to perform a confidence check of the controller. Some failures are considered fatal and will stop the machine;
other failures limit its operation but will not prevent its use. Fatal failures are indicated by the LEDs
on the keyboard, while nonfatal errors are indicated as a single character on the screen.
The microprocessor first sends the number of the first ROM to the LEDs on the keyboard. Then it
calculates a checksum of the contents of the first 2K of program. (Since firmware is treated as four 2K
blocks of code, later VT 100s with one 8K X 8 ROM chip operate the same way but any block failure
requires replacement of the one chip.) At the time of ROM preparation, a special byte was included
within each block to make the checksum equal zero if there are no errors. If there is an error, the

microprocessor halts and the LEDs indicate the current ROM at the time of failure. Otherwise, the
LEDs are incremented to show the next ROM number and the process continues.
The next part of the test is writing and reading the RAM. Every bit in the RAM is written with a 0 and
a 1 and read each time. If the advanced video option is present (as indicated by the Option Present
flag), its RAM is tested immediately after the main RAM. In the main RAM a failure halts the
machine. Failure of a bit in the advanced video option RAM is indicated on the screen and the process
continues. In another terminal, like the VT52, one bad bit in the screen RAM means there is one
location that may not contain the right character. This can be annoying to the user but does not affect
the rest of the screen. If one bit is bad in a VT 100 line address, the entire screen below the affected line
can become garbled and unusable. A bad bit in the scratch area could disable communication with the
host. So this confidence check ensures that any RAM failure is detected immediately.
The next test checks the nonvolatile RAM by reading it. A checksum is calculated and compared with

the value stored the last time the NVR was written during a save. A bad NVR does not stop the VT 100
because the SET-UP values can always be reestablished from the keyboard at power-up. The NVR test
is also the normal time when the terminal gets its auto SET-UP readings from the NVR. Time is saved
because reading the NVR is the most time-consuming part of both the self-test and the auto SET-UP.
If the NVR fails, the bell sounds several times to inform the operator, and then default settings stored
in the ROM allow the terminal to work. The operator must then manually reset any parameters that
differ from the default values.
To test the keyboard, the microprocessor commands the keyboard to scan once, lights all the LEDs,

for about a half second, and sounds the bell. It waits for the scan to finish and then looks for the last
key address 7FH at the keyboard UART. If the test fails, the terminal remains on-line, making it a
receive-only (RO) terminal.
This is the end of testing.
Once the NVR data is in the scratch area in RAM, the microprocessor uses that data to program the
hardware. All operating parameters that were last saved (see NVR) are recalled and the terminal is set
to match them. Finally the cursor appears at column 1, line 1, and the microprocessor enters its

background routine, ready for operation.

4-19

Refer to the Communication chapter for a discussion of Data and EIA tests, and to the Service chapter
for a listing of the Self-Test Results tables.

4.3 COMMUNICATION TRANSCEIVER
The VTI100 interfaces to its host system through a serial data port. An 8251 programmable universal
synchronous or asynchronous receiver-transmitter (PUSART), illustrated in Figure 4-3-1, drives the
port. This device translates between parallel and serial formats, adding or removing start and stop bits
as required. The data exchanged are ASCII characters; parity may be enabled or disabled; the selectably odd or even parity bit will take the most significant bit position.
4.3.1

PUSART Principles

Most data in computer systems is exchanged as groups of bits. The bit is the smallest unit of information, but to be useful, most information must be encoded into groups of bits in standardized patterns.
The VT100 operates with the standard patterns described by the American Standard Code for Information Interchange (ASCII). ASCII defines the use of 7 bits, specifying 128 different patterns that
correspond to almost all of the letters, numerals, and punctuation marks used in English and several
other languages. An eighth bit is reserved for an expanded standard.

The eight ASCII bits can be exchanged most rapidly over eight separate wires (in parallel), but this 1s
very expensive to do anywhere outside the computer cabinet. Instead, the bits are rearranged to pass

over a single wire one after the other. This is called serial transmission. The circuitry for converting
parallel to serial and back again is complex but suited to large scale integration (LSI). The savings
allowed by the use of serial lines has encouraged the development of very sophisticated but inexpensive
conversion devices in LSI. At the same time, a variety of data exchange protocols has been developed.
The result is an LSI device that can operate with virtually any protocol depending on the programming
that it receives from its local processor. This is the PUSART. The VT 100 uses one such device (Intel’s
8251A) only in asynchronous mode, plus two simpler, wire-programmed asynchronous-only UARTS
for the keyboard interface.

Synchronous and asynchronous describe the manner in which separate groups of bits (called bytes) are
exchanged. In order for a receiver to know which bit is arriving at any given time, it must know the
format of the byte and which bit of the byte is the first one. In synchronous mode, one or more special
bytes are transmitted which the interface recognizes as synchronizing characters. Then all data bytes
are transmitted together in rapid and precisely timed succession. Both the transmitter and receiver
must have the same externally-supplied clock.

The VT100 only communicates asynchronously. Asynchronous transmission uses bits added to each
data byte to provide synchronization between the transmitter and receiver. Because any two data

exchanges can originate at random times with clock frequencies as much as 1 percent different, the
protocol assumes random arrival of any byte of data, and relies on the synchronization information in
the byte. This synchronization consists of extra bits appended to the beginning and end of the byte.
One bit at each end (one start bit and one stop bit) is the most common configuration. The start bit and
stop bit are defined to have specific states, and in particular, the start bit has a different state from the
idling condition on the line. The interface looks for the transition from the idling state (called mark) to
the start bit state (called space) and then clocks in the byte. The stop bit is the mark state, as is the
idling line, so an immediately following byte has the correct mark to space transition to provide
synchronization. The data bits, which occur between a start and a stop bit, are represented by a mark
for a one and a space for a zero. Figure 4-3-2 shows the asynchronous data format.

4-20

DATA

_.f\

BUS

D; Dy

TRANSMIT
BUFFER

PARALLEL [> DD

BUFFER

SERIAL

RESET ——»

CLK — peAD/WRITE <::>

— > TxRDY

C/D —»{

CONTROL

RD —»Of LOGIC

& TXxEMPTY

O=-TxC

WR —»QO

—

RECEIVE

DSR —*d
CcTS —=O|

BUFFER

CONTROL

SERIALTO

PARALLEL

RTS «+O

—+#

||
A

INTERNAL /

RECEIVE

CONTROL

RxRDY

—

O<— RxC

e—» SYNDET/

BRKDET

DATA BUS

PIN NAME | PIN FUNCTION
D, D,

DATA BUS (8 BITS)

c/D

CONTROL OR DATA IS TO BE WRITTEN OR READ

WRITE DATA OR CONTROL COMMAND

CHIP SELECT

CLK

CLOCK PULSE (TTL)

READ DATA COMMANCD

RESET

TxC

TRANSMITTER CLOCK

TxD

TRANSMITTER DATA

RxC

RECEIVER CLOCK

RxD

RECEIVER DATA

RxRDY

RECEIVER READY (HAS CHARACTER FOR CPU)

TxRDY

TRANSMITTER READY (READY FOR CHAR. FROM CPU)

DSR

DATA SET READY

DTR

DATA TERMINAL READY

SYNDET,
BRKDET

RTS

| SYNC DETECT/
BREAK DETECT

REQUEST TO SEND DATA

CTS

CLEAR TO SEND DATA

TxEMPTY

| TRANSMITTER EMPTY
MA-4302

Figure 4-3-1 8251A PUSART Block Diagram

4-21

GENERATED
TRANSMITTER OUTPUT

D, D,

BY 8251A

l
TxD

MARKING | START

DATA BITS

BIT

))

((C

PARITY |

STOP

BIT

BITS

u
DOES NOT APPEAR

RECEIVER INPUT

Do Dy ---=-- Dx

I START

ON THE DATA BUS

DATA BITS

PARITY lTOP

(

BIT

-—

BITS

PROGRAMMED

CHARACTER
LENGTH
TRANSMISSION FORMAT

CPU BYTE (7-8 BITS CHAR)

DATA CHARACTER
_())

ASSEMBLED SERIAL DATA OUTPUT (TxD)
))
¢

PARITY | STOP
l START
BIT
DATA CH)A;RACTER 81T
BITS
—(

{

RECEIVE FORMAT
SERIAL DATA INPUT (RxD)
A

()(L

START
BIT

()

DATA CHARACTER
Yy

PARITY

STOP

BIT

BI}TS

CPU BYTE (7-8 BITS CHAR)*

DATA CHARACTER

_e
*NOTE: IF CHARACTER LENGTH IS DEFINED AS 7
BITS THE UNUSED BITS ARE SET TO “ZERO”
MA-4284

Figure 4-3-2 Asynchronous Data Format

4-22

4.3.2

PUSART Operation

The complete functional definition of the PUSART is programmed by the system’s software. A set of
control words must be sent out by the microprocessor to initialize the PUSART to support the desired
communications format. Once programmed, the PUSART is ready to perform its communication
functions. The Transmitter Ready (TxRDY) output is raised high to signal the microprocessor that the
PUSART is ready to receive a data character from the microprocessor. TXRDY is reset automatically
when the microprocessor writes a character into the PUSART.

Upon receiving an entire character from the serial input, the Receiver Ready (RxRDY) output is
raised high to signal the microprocessor that the PUSART has a complete character ready to be read.
RxRDY is reset automatically when the data is read. The PUSART cannot begin transmission until
the Transmitter Enable (Tx Enable) bit is set in the command instruction and it has received a Clear To
Send (CTS) input. The Transmit Data (TxD) output will be held in the marking state when the line is
idle.

For a more detailed description of the PUSART’s operation, refer to Intel’s 8251
A specification.
4.3.3

PUSART Addressing

I/0 read, write and enable addressing and commands are discussed in the microprocessor I/O decoding section.
4.3.4

PUSART Programming

The microprocessor can program the PUSART to opeate with several standards and parameters.
Many of these parameters are predetermined by the VT 100 specifications. Character length, number of
stop bits, parity enabling and format, baud rate multiplication factor, and asynchronous operation are
all programmed in at power-up through the mode instruction (Figure 4-3-3) from the stored SET-UP
information. Address bit A0O selects either the command register in the PUSART for writing the byte
containing this information, or the transmit buffer for normal operation. A different programmable
device, discussed later, provides the selected baud rate from SET-UP data.
After the PUSART mode of operation is selected by writing a mode instruction, PUSART operation is
controlled by writing a command instruction (Figure 4-3-4). Once the mode instruction has been
written into the PUSART, all further “control writes” (C/D=1) load a command instruction. A reset

operation (internal or external) returns the

PUSART to the mode instruction format.

The status of the PUSART can be read by the microprocessor by performing a read with C/D=1.

Some of the bits in the status word (Figure 4-3-5) have the same meaning as output pins on the
PUSART chip. The status word may be a maximum of 28 clock periods behind the event causing the
update. This clock, from the microprocessor’s phase 2 TTL signal, is the clock for the internal operation of the PUSART, which is a dynamic device requiring internal refresh at regular intervals.
4.3.5

Data Transmission
When the microprocessor wants to send a character out, it checks the XMIT flag at the flag buffer. If

this flag is high the transmit buffer is empty and can accept data. If the flag is low, the microprocessor
continues through its background program and returns to check again later.
When the flag is high, the microprocessor loads a data byte into the transmit buffer. The PUSART is

double-buffered; this means that there is a second data buffer inside that is automatically loaded from
the first buffer. The second buffer’s contents get start and stop bits and parity (if enabled) appended
and are shifted out by the continuously running clock. Immediately after the second buffer is loaded,
the transmit flag goes high and the first (transmit) buffer can be loaded again.

4-23

s
BAUD RATE FACTOR
0

SYNC

MODE|

(1X)

| (16X) | (64X)

CHARACTER LENGTH

BITS | BITS

| BITS | BITS

_ PARITY ENABLE

"1 =ENABLE

O =DISABLE

EVEN PARITY GENERATION/CHECK

"1 =EVEN

0= 0DD

NUMBER OF STOP BITS

m\IVALID BIT

BITS

(ONLY EFFECTS Tx;Rx NEVER
REQUIRES MORE THAN ONE

STOP BIT)
MA-4283

Figure 4-3-3 Mode Instruction

4-24

RTS

SBRK

RxE

DTR

TxEN

TRANSMIT ENABLE
1 = ENABLE

O = DISABLE

DATA TERMINAL READY

“HIGH" WILL FORCE DTR
OUTPUT TO ZERO.

RECEIVE ENABLE

0 = DISABLE

1 = ENABLE

SEND BREAK
»|

CHARACTER

1 = FORCES TxD "LOW"

O = NORMAL OPERATION

J ERROR RESET

1 = RESET ERROR FLAGS

|__PE, OE, FE

REQUEST TO SEND

“HIGH” WILL FORCE RTS
OUTPUT TO ZERO

r__J

JNTERNAL RESET : “HIGH"

#IRETURNS 8251A
TO MODE

INSTRUCTION FORMAT

ENTER HUNT MODE*
»1

1 = ENABLE SEARCH FOR

SYNC CHARACTERS

* (HAS NO EFFECT
IN ASYNC MODE)
NOTE: ERROR RESET MUST BE PERFORMED WHENEVER RxENABLE AND
ENTER HUNT ARE PROGRAMMED.

COMMAND INSTRUCTION FORMAT
MA-4276

Figure 4-3-4 Command Instruction

4-25

SYNDET

TxEMPTY

DSR

TxRDY

RxRDY

|
—

NOTE1
j-

SAME DEFINITIONS AS 1I/O PINS

PARITY ERROR
THE PE FLAG IS SET WHEN A PARITY

ERROR IS DETECTED. IT IS RESET BY
THE ER BIT OF THE COMMAND

INSTRUCTION. PE DOES NOT INHIBIT
OPERATION OF THE 8251A.

OVERRUN ERROR
THE OE FLAG IS SET WHEN THE CPU

DOES NOT READ A CHARACTER BEFORE
THE NEXT ONE BECOMES AVAILABLE
.

IT IS RESET BY THE ER BIT OF THE

COMMAND INSTRUCTION. OE DOES
NOT INHIBIT OPERATION OF THE 8251A;
HOWEVER THE PREVIOUSLY OVERRUN

CHARACTER IS LOST

FRAMING ERROR (ASYNC ONLY)

THE FE FLAG IS SET WHEN A VALID
STOP BIT IS NOT DETECTED AT THE

END OF EVERY CHARACTER. IT IS RESET
BY THE ER BIT OF THE COMMAND
INSTRUCTION. FE DOES NOT INHIBIT
THE OPERATION OF THE 8251A.

DATA SET READY INDICATES
THAT THE DSR IS AT A ZERO LEVEL.

STATUS BYTE FORMAT
NOTE 1:

TxRDY STATUS BIT HAS DIFFERENT MEANINGS FROM THE
TxRDY OUTPUT PIN. THE FORMER IS NOT CONDITIONED

BY CTS AND TxEN: THE LATTER IS CONDITIONED BY BOTH
CTS AND TxEN.
i.e. TxRDY STATUS BIT = DB BUFFER EMPTY

TxRDY PIN OUT = DB BUFFER EMPTY @ (CTS-O) ® (TxEN-1)
MA-4275

Figure 4-3-5 Status Byte Format

4-26

4.3.6

Data Reception

Any data that appears on the receive data line is shifted into the internal receive shifting buffer. When
a full character of bits has arrived, the start, stop, and parity bits are stripped. Parity is checked, and if
bad, the parity error flag in the status word is set. Data is transferred to the receive data buffer, and the
receive flag is set. This flag requests an interrupt from the microprocesor. The microprocessor then has
the amount of time it takes the next character to shift in to read the first character. After reading the
character, the microprocessor reads the status byte to check the integrity of the data. If the microprocessor does not read the receive data buffer in time, the second character writes over the first one

which is lost. Then, an overrun error is reported in the status word. The checkerboard character

appears for all errors.
4.3.7

Baud Rate Generator

PUSART clocks are derived from the microprocessor clock. The microprocessor clock crystal was
selected to provide a frequency within the limits of the 8080 which could be readily divided to provide
standard baud rates. The division occurs in programmable baud rate generator E60. This device con-

tains two independent counters to allow different receive and transmit (split) baud rates. Each counter
has 4 input lines to select 1 of 16 rates. Thus, a 1-byte load into the device can set up both send and
receive rates. The baud rate generator’s input register is written into as a device in the 1/O address
space.

E60 1s factory mask-programmed with the division ratios required to get standard baud rates from the
crystal frequency. The 4-bit input is an address for a ROM location containing the SET-UP information for each rate. Table 4-3-1 lists the baud rate generator divisors.
E60 was originally designed to operate with a crystal as a self-contained crystal controlled oscillator
and divider. The oscillator is located elsewhere, so the oscillator inputs EXT1 and EXT2 receive the

microprocessor clock driven out of phase by two inverters in E38.

Table 4-3-1 Baud Rate Generator Divisors
(Input frequency = 2.76480 MHz)

Freq
(Hz)

X16

Baud Rate

Divisor

Output

Error

50
75
110

3456
2304
1571

800
1200
1760 *

-0.006%

134.5
150

1285
1152

2152°
2400

200
300

864
576

3200
4000

600

288

9600

1200
1800
2000

144
96
86

19200
28800
32000 *

2400

38400

3600

57600

4800
9600
19200

36
18
9

76800
153600
307200

-0.019%

+0.465%

*Output frequency shown is nominal value. Include percentage error to get actual frequency.
4-27

4.3.8 Serial Interface
The serial transmit and receive interfaces are ICs that convert between TTL signals and EIA RS-232-C
unbalanced bipolar signals. The electrical specifications and connector pinouts are described in Chapter 3, Installation.
4.3.9

Modem Control

Certain pins on the PUSART are labeled with standard modem control designations. These pins are
readable [Data Set Ready (DSR)] or writable [Data Terminal Ready (DTR)] and [Request to Send
(RTS)] as buffered bits in the PUSART’s status and control bytes. Other signals from the modem pass

through EIA level translators with Schmidt trigger inputs to a tristate buffer which, when enabled by
the MODEM RD command, presents them to the data bus. Another signal [Speed Select (SPDS)] is
written from the data bus into the NVR latch which is a convenient extra latch position. None of these
signals are used to support modem control in the basic VT100. They are always programmed at powerup to allow normal full duplex operation with some modems when a standard EIA cable is installed
between the modem and the VT100. See Chapter 3 for more interface information.
4.3.10 Data Types
Three kinds of data can be exchanged between the VT100 and the host: control characters, control
functions, and displayable characters.

Control characters are any ASCII characters in the range 0 — 1FH. They include carriage return and
line feed.

Control functions start with a control character (escape) and contain additional characters which
extend the range of special actions that the terminal can perform. Cursor home is such an action. Some
control functions can contain numeric parameters to modify the special actions. Direct cursor addressing 1s a typical example. Appendix A of this manual describes the programming and use of the control
characters and functions in detail.
Displayable characters are those ASCII codes that are stored in the screen RAM, causing a character
to be displayed on the screen.
4.3.11

SILO
The microprocessor checks each character as it comes in from the PUSART. Only four characters

cause any special action at this time. Control codes XON and XOFF (see below) are immediately
processed while NULL and DELETE are discarded. Everything else gets put in a 64 character (128
characters in later model terminals) first-in/first-out space in the scratch area of RAM called the
SILO. The SILO processor routine maintains this area by updating two locations called SILIN and

SILOUT. These point to the current entry and exit points in a loop of memory locations. The farther
apart they are, the more characters are in the SILO. The addresses of the two points are subtracted
from each other to determine the filling of the SILO. The subtraction is performed in modulo 64 (or
128) arithmetic to accommodate the rotation of the locations.
The SILO is necessary because when the microprocessor reads a character, it acts on that character

completely before taking another one. For example, a line feed character causes the processing needed
to accomplish a scroll. The processing time often exceeds the time between characters at the port. To
save the characters that might arrive and get lost during a special action, the microprocessor responds
to the received data interrupt by quickly moving the data to the SILO. Only the examination described
above gets performed. After the current action is finished, the microprocessor gets the longest waiting
character out of the SILO and range checks it. If it is less than 20H, it is a control character and the
microprocessor processes it. If it is 20H or above, the microprocessor puts it in the next character
position in the screen RAM.

4-28

4.3.12

XON/XOFF

XON and XOFF are two control codes that the terminal and host may send to each other to control
the pace of data transmission. The host usually has a buffer space similar in function to the VT100’s
SILO. If either device has a large processing load at the same time that a lot of data is being received,
the buffer or SILO can fill up. The receiving device monitors its buffer and sends Transmit Off
(XOFF) when the buffer contains a predetermined number of characters. On the VT 100 this value is 32
characters. (A second XOFF i1s sent at 112 characters in late model VT100s.) The sending device
should stop transmitting until it receives Transmit On (XON). When the receiving device empties its
buffer to another predetermined number of characters (16 characters on the VT100), it sends XON.
The No Scroll key on the keyboard enables and disables SILO fetching. If data continues to arrive, the

SILO management routine sends XOFF or XON as required. The microprocessor keeps track of the
current state and sends the opposite command the next time the key is pressed. Control S and Control

Q send XOFF and XON directly. Coordination of various causes of XON and XOFF is discussed in
Appendix A.

Because of the serial interface, several character times may elapse before the transmitter acts on XOFF
and its last character passes through the receiver. This partly determines how full the buffer can be
before XOFF must be sent. The other determinant is the worst case condition in split speed operation.
[f the terminal transmits at a low speed and receives at a high speed, the interface delay can allow
several characters to arrive before XOFF stops their transmission. A detailed discussion of this problem is in Appendix A.
4.3.13
Control Function Parser
A parser is a routine that examines a sequence of characters. It then starts processes and extracts

parameters based on the contents of the sequence. The term comes from the grammarian’s practice of
parsing (separating) a sentence into its component parts: subject, verb, object. The meanings of many
sequences are being standardized throughout the data processing industry through American Standards Institute (ANSI) and International Organization of Standardization (ISO) committees. The
VTI100 employs a subset of several of these standards, plus it has several private sequences to allow it

to perform certain DEC-specific functions like behaving as a VT52.
A character in the range below 20H is always the starting flag for the parsing process. Some functions
have only the first character for their sequence; line feed (OAH) is an example. After the function is

performed, the next character is taken from the SILO. If it is not in the control range, it is put on the
screen. Escape (1BH) is the flag for a longer sequence. After escape, characters are taken from the
SILO and range-checked as intermediate (20H to 2FH) or final (30H to 7EH) until a final character
appears. The sequence is interpreted and the appropriate function performed. Then the next character
is taken from the SILO and displayed if not in the control range. If a sequence is not supported by the
VTI100, it 1s parsed and then ignored.

Detailed descriptions of the functions are in the V'T100 User Guide and in Appendix A of this manual.
4.3.14 Local
In local mode, keyboard output bypasses the communication transmitter and receiver and SILO and is

acted on directly. The Data Terminal Ready signal (DTR) at the EIA interface is unasserted in local.
4.3.15

Standard Terminal Port

The standard terminal port (STP) is a printed circuit board edge connector on the basic video board
that contains twenty pairs of contacts. When no board is plugged into the connector, the pairs of
contacts meet. All EIA data and modem control signals plus the two baud clocks pass through this
connector. Future options may utilize the signals present at this connector. For a complete discussion

of the details of the STP, see the

STP Option Interface Guide, Chapter 8.

4-29

4.3.16 Communication Self-Test
The VT100 can test its communication circuits, but because the operator must temporarily plug in a

specially wired loopback connector, the test is not performed automatically. Refer to the Service
chapter for instructions. There are two tests. One is a data test for either 20 mA current loop or EIA
interfaces. This test transmits a pattern of data out the transmit line and examines the data as it returns
through the receive line. Each bit of the data bus is tested with the eight test characters: O1H, 02H,
04H, O8H, 10H, 20H, 40H, 80H. This group of eight passes through the circuit repeatedly while the
microprocessor changes the baud rate after each pass.
The second test, for EIA only, tests the modem control lines to ensure that they can be controlled.
Some terminal controller modules have an etch revision at E39 that does not permit EIA testing. These
modules can be recognized by the presence of extra wires attached at E39.
Table 4-3-2 lists the test connector wiring.

Table 4-3-2 Loopback Test Connectors

4.4

From

EIA:

Pin 2
Pin 4
Pin 20
Pin 19

Pins 3 and 15
Pins Sand 8§
Pins 6 and 22
Pins 12 and 17

20 mA:

Pin 1
Pin 2
Pin 5

Pin 3
Pin 7
Pin &

KEYBOARD

The VT100 keyboard is a typewriter-like array of momentary, normally-open switches. The array 1s
mounted in a small case with a speaker for audio feedback and electronics for interfacing the array to
the terminal. The VT100 keyboard connects to the terminal controller board through a three conductor cable that plugs into the back of the terminal cabinet. The cable carries power, ground, and a
complex bidirectional data and clock signal. The terminal sends the clock signal and a status word that
controls the LED indictors, the bell, and the keyboard scan process. The keyboard sends the row and
column address of each key that is pressed. The terminal’s microprocessor then translates that address
into an ASCII character and transmits it serially to the host through a UART or performs internal
actions such as SET-UP and no-scroll. Refer to Section 4.3 for a discussion of UART principles.

This section describes the operation of the keyboard and its interface hardware and software in the
terminal.

4.4.1

Keyboard Block Diagram (Figure 4-4-1)

The bidirectional interface separates incoming from outgoing data on the single signal line. Incoming
data from the terminal contains a clock that passes directly to the UART and the address counter
circuit. Then the data and clock are integrated. The duty cycle encoded data becomes serial data. The
UART deserializes the terminal data and produces an 8-bit parallel output. These bits control the bell
and LEDs, and start address scanning, depending on which bits were set by the terminal in the keyboard status byte.

4-30

-» CLOCK

SERIAL

LINE
TO

TERMINAL

BIDIRECTIONAL
-

INTERFACE

INTEGRATOR

BELL

)

CLOCK

sRen

SERIAL
DATA IN

| |

UART

BELL

TERMINAL DATA

LEDS
START

SCAN
r—CLOCK

SERIAL
e

ADDRESS

COUNTERS

J L

DATA

KEYBOARD DATA

STROBE

KEYBOARD
ITCH

iV;RXY

KEYDOWN
MA-4661

Figure 4-4-1 Keyboard Block Diagram

The address counters start on command and send row and column addresses to the keyboard switch
array. When an address matches a key that is down, the Key Down signal strobes that address into the
UART. The UART serializes the address and the bidirectional interface sends it to the terminal.
4.4.2

Keyboard UARTSs

Information is exchanged between the terminal and the keyboard in serial form. One start bit, eight
data bits, and one stop bit are transmitted using a clock derived from the horizontal timing circuits in
the terminal. Besides timing the serialization of data in the terminal, the clock is also transmitted to the
keyboard to time its circuits. The terminal data is a status byte that controls the keyboard by commanding key scans and other functions.
The keyboard transmits its data in the same format and with the same clock. Its data are the addresses
of whatever keys are down during a scan. The last key address sent has the highest address possible and
is always sent to indicate to the microprocessor that the scan is complete.
4.4.3

Keyboard Status Byte
The terminal controls the keyboard through a status byte that it sends through the interface along with

the keyboard clock. The first six bits of the 8-bit byte (Figure 4-4-2) control the On-Line/Local,
Keyboard Locked, and four user programmable LEDs on the keyboard. Every time the status byte is
-sent, it refreshes the LEDs even if no new action is being taken. The seventh bit is sent only once in a

vertical interval and initiates the scanning process in the keyboard. The eighth bit, if sent only once,
causes the keyboard speaker to click. (Keyclick is defeatable at SET-UP.) If the bit is sent approximately two hundred times in a row, for about a quarter second, it sounds a bell.

4-31

L D7

SPKR.

ON LINE/

LED

CLICK

LOCAL

START

KEYBD.

LED

SCAN

LOCKED

4
MA-4293

Figure 4-4-2 Keyboard Status Byte

The operating clock for the keyboard interface comes from an address line in the video processor
(LBA4). This signal has an average period of 7.945 microseconds. Each data byte is transmitted with
one start bit and one stop bit, and each bit lasts 16 clock periods. The total time for each data byte is
160 times 7.945 or 1.27 milliseconds. Each time the Transmit Buffer Empty flag on the terminal’s
UART gets set (when the current byte is being transmitted), the microprocessor loads another byte
into the transmit buffer. In this way, the stream of status bytes to the keyboard is continuous.
4.4.4

Key Address Counter

Keyboard addresses are outputs from a counter that correspond to locations in a keyswitch matrix.
The counter can address all locations in the matrix. If a keyswitch is closed, the counter output addressing that location is transmitted. The address counter is a pair of 4-bit binary counters arranged so
that only the top seven bits go to the switch matrix. These outputs also connect directly to the UART
transmit data inputs. The output of the first bit in the counter is a squarewave with a period equal to
the amount of time that each key is sampled during a scan. Key Down L appears at the input to flipflop E6 when the counter reaches the address of a key that is pressed. Half a sample period later, the
first counter bit clocks the Key Down signal through flip-flop E6. The half period delay allows any
glitches in the address counter to settle before Key Down asserts Data Strobe. Data Strobe loads the
UART transmit buffer with the address count present at the data input at that moment. That address
count represents the key that was down when Key Down was asserted.

The UART, which is double-buffered, deasserts Transmit Buffer Empty while the transmit (outer)
buffer is full. This stops the counter by blocking the clock at gate E4. As soon as the data moves into
the inner shifting register, the transmit buffer empties, TBMT is asserted, and the count continues. In
this way, any number of key addresses can be sent to the terminal. The time the scan takes to finish
varies with the number of keys down. On the first address load, when transfer from the transmit buffer
into the shifting register is immediate, the UART reasserts TBMT almost immediately. For loads later

in the scan, the UART deasserts TBMT for a longer period because an address that loads into the
transmit buffer must wait with the counter stopped until the previous transmission is done. Because
the transmission time is 160 counts and the complete address scan takes only 128 counts, there is a
minimum wait of 32 counts or about 20 percent of a character transmission time between the scan of
address 7FH and the transmission of address 7FH if the first key in the scan was down. (Refer to
Figure 4-4-3.)

Because it is hard-wired, the highest address (7FH) always asserts Key Down and gets transmitted,
indicating end of scan to the terminal. The highest bit also clocks flip-flop E3 which clears the counters
and stops the count. This is the only way that the scan is terminated. The scan begins again when the
terminal sends the Start Scan bit in the status byte to the keyboard. When the data arrives, the UART
asserts its Data Available flag. On the next clock transition, flip-flop E6 passes a short, clock-synchro-

4-32

nized Data Available pulse to gate ES, resetting the flag in the process. E5S combines the Data Available pulse with the Start Scan bit if present to clear E3, allowing the count to begin.
After the terminal starts the scan, it waits for the 7FH address and then for a vertical interrupt (a
synchronizing signal explained in VIDEO) before it will start the scan again. If there are a lot of keys
down, the scan may take more than one vertical interval to finish. The keyboard ignores further
requests to scan until the current scan is complete.

BEST CASE

SCAN:

ADDR 1.......... 127 COUNTS ........ADDR 7FH

TRANS: ADDR 1oevvvoee v, 160 COUNTS oo ADDR 7FH

DELAY BETWEEN SCAN & TRANS
OF ADDR 7FH

WORST CASE

SCAN:

ADDR

1. ADDR 2...NO COUNTS.....START COUNTS.....126 COUNTS.....ADDR 7FH

TRANS:

ADDR

1...............160 COUNTS.........ADDR 2. oo, 160 COUNTS............. ADDR 7FH

|‘_’i

DELAY BETWEEN SCAN &
TRANS OF ADDR 2

DELAY 1 COUNT MORE
THAN BEST CASE
MA-4278

Figure 4-4-3 Key Address Transmission Delays

Here is a formula that estimates the delay between the time that the terminal asserts the start scan bit at
its UART and the time that the terminal UART asserts data available upon receiving the final address
TFH. The clock driving the address counter and UART has a period of 7.945 microseconds, there is
the number of addresses to the first closed key to be counted, and the serial transmission of an address
takes 160 clock periods (16 clocks per bit, 8 data bits, 1 start and 1 stop bit).
160

start scan command word to keyboard

counts to first key

+nX

160

fornkeysdown

160

transmission of 7FH

Total X 7.945 = microseconds
For example, suppose that one key, #24, is down.

160

start scan command word to keyboard

counts

160

transmission of key #24 address

160

transmission of 7TFH

504 X 7.945 = 4004 microseconds (4.0 us)

4-33

4.4.5

Key Scanning and Address Formation
The keyboard is an array of contact pairs arranged in 16 rows and 8 columns (Figure 4-4-4). One side

of each pair is connected to all the others in its column and each column connects to +5 volts through
a resistor. Each of the eight columns also connects to an input on the eight-to-one multiplexer E14.
The other side of each contact pair connects to all the others in its row and to an output on one of the
one-to-eight demultiplexers E11 and E13. The seven outputs of the keyboard scan counter control the
multiplexer and demultiplexers. The rows are selected by the lower four bits and the columns by the
upper three.
A low input to the selected column line on the multiplexer causes a Key Down L signal. If a key is
pressed when the row and column address is not on its position, the unselected demultiplexer line is
high and there is no change in level across the contacts. If the demultiplexer line is selected, it is low,
and the closed contact pulls the column low through the resistor. Each column is scanned top to
bottom as the low four address lines count; then the next column is selected and scanned. The complete
keyboard scan takes about 1 millisecond when no keys are down.

The last row and column position (address 7FH) is wired to always indicate key down. This value
indicates to the terminal that the scan is ended.

4.4.6

Bidirectional Interface Operation

The terminal sends data and clock to the keyboard; the keyboard sends data only. Transmission is
asynchronous, full duplex, serial, 8-bit data with one start bit and one stop bit over a single signal line.
Four states can exist on the line, representing the two signal states from each end of the line.

Both signals may coexist on the same wire, originate at opposite ends, and simultaneously communicate provided that sensing resistors are put at each end. The interface works by observing the voltage
variations on its input (across the sensing resistor) while biasing the input in an opposite direction with
its own output signals so that only input variations can cause enough change to exceed the threshold of
detection.

4.4.6.1 Interface Line — Refer to the keyboard interface schematic, Figure 4-4-5a. If one side of the
line is at +12 volts and the other is at ground, then by Ohm’s Law, the center of the two equal resistors
will be at V/2 = 6 volts. If both sides are at 0 or 12, the center will be identically at 0 or 12. Thus the
signal line can either have no current flow but with the junction of the two resistors at either 0 or 12
volts, or the junction can be at 6 volts with current flow to the left or to the right, thereby representing
the four required states.

4.4.6.2 Receiving Side - The receiving side of the keyboard interface separates the incoming signal
from its own output by delivering a sample of its output to the inverting input of a comparator. Refer
back to Figure 4-4-5. This provides an additional input for the comparator which compensates for the
variation that occurs on the noninverting input at the same time that the output changes. R12 and R13
(both approximately 20K) and R11 (10K) are a divider providing bias to the comparator. If E8 (an
open collector driver) is off (high), then the end of R11 connected to ES8 is essentially at +12 volts
through R15 (470). The R11, R12, R13 divider outputs 9 volts as shown in Figure 4-4-5b. If E8 is on
(low), the end of R11 is at ground, and the divider outputs 3 volts (Figure 4-4-5c).

Meanwhile, the signal from the other end of the signal line is admitted to the noninverting input of the
comparator through a resistor (R7) whose value is small compared to the comparator’s high input
impedance. The positive feedback resistor R8 provides a small amount of hysteresis to improve the
circuit’s noise immunity.

4-34

COLUMNS

MSD

LSD

1000 ONER=:
3 <::£::><:::::><:::::>F 0 > 2:5;5 BREAK

ROWS

?
/

>
:

SPACE

SACE

}

LINE

)

—

{

—

[

RETURN

DELETE

FEED

—

RETURN

é)

#39

ggROLL

TAB

ESC

seTup

cTRL

SHIFT

(

]

CAPS

Lock

ALWAYS

FlcLosep

MA-4361

Figure 4-4-4 Keyboard Switch Array

4-35

AAA
\ A

TE2

COMPARATOR

OUTPUT
12

lf' N
YR12 |
|

20K

T
C7

le——SIGNAL LINE—
SENDER

BIAS

NETWORK|

;]; e
I $10K

R13

20K

: RECEIVER

JUNCTION
|

e
A A

A\ A

7
H

v o

CABLE

CAPACITANCE
MA-4659

Figure 4-4-5A Keyboard Interface Circuit

;

—

10K

— g VOLTS

;

20K

Figure 4-4-5B Bias Network - E8 High

iZOK 10K

—= 3 VOLTS

M A-4660

Figure 4-4-5C Bias Network - E8 Low

4-36

For the case where the junction is at 12 volts, there is no ambiguity about what signal the sender is
sending. The comparator must produce a high output because the sender is outputting a high level.
(The receiver is also sending a high level but no distinction between the two needs to be made.) The
bias network presents a 9 volt signal to the inverting input, so the comparator sees a +3 volt difference
and goes high.

For the case where the junction between the sender and the receiver is at O volts, there is again no
ambiguity. The comparator must produce a low output because both sender and receiver are outputting low levels. The bias network presents a 3 volt signal to the inverting input, so the comparator
sees a -3 volt difference and goes low.
For the case where the junction is at 6 volts, either end could be the high or low sender. The decision is
made at each end by each circuit examining its own output to decide whether it or the other end is
sending a particular level. If the sending end is at 0, the noninverting input sees 6 volts. The receiving
end is outputting 12 volts, and the network outputs 9 volts to the inverting input. The comparator sees
a difference of -3 volts and outputs low in recognition of the low level at the sending end. If the sending
end is at +12, the noninverting input sees 6 volts. The receiving end is outputting 0 volts, and the
network outputs 3 volts to the inverting input. The comparator sees a difference of +3 volts and
outputs high in recognition of the high level at the sending end.
Table 4-4-1 summarizes the effects of the various signals.

Table 4-4-1 Keyboard Receiver Signals
Non-

Invert.

Send.
End

Rec.
End

Input
(Junction)

Invert.
Input

0
0
12
12

0
12
0
12

0
6
6
12

3
9
3
9

Difference
-3
-3
+3
+3

Output
0
0
5
5

4.4.6.2.1

Keyboard Cable Compensation - C7 compensates the circuit for the capacitance of the cable.
If C7 were not present, the output of the comparator would glitch when the output driver on the same
end of the line changed state. This would be caused by the output signal propagating immediately to
the inverting input of the comparator but being delayed (by the RC time constant of the line) to the
noninverting input. C7 is chosen so that the time constant of the line is the same at both inputs.

Because the resistance seen at the middle of the line is approximately 1000 ohms (two 2K resistors in
parallel) and the resistance seen at the inverting input is approximately 5000 ohms (one 10K and two
20K resistors in parallel), C7 is about one-fifth of the cable capacitance. The value is not critical

because the ratio of the two time constants can be as large as two and still provide acceptable noise
immunity.
4.4.6.3 Terminal Data Encoding - The keyboard requires a clock for its operation and is provided
with one by the terminal controller side of the interface. To transmit a clock independently of data on
the same wire, the terminal side of the interface generates a clock signal within which data is encoded
as a pulse width modulation. The terminal circuit produces a 75 percent high pulse width output for
the mark state. Data transmission causes the clock output to switch between 75 and 25 percent pulse
width (duty cycle).

4-37

Figure 4-4-6 is a timing diagram that illustrates the formation of the pulse width modulation. Three

nand gates, I, II, and III, combine three signals, Data, LBA 3, and inverted (not) LBA 4. The three
gate outputs are wire-ANDed so that all three must have high outputs to produce a high to the out
inverter, which drives the terminal’s end of the bidirectional interface. The timing is not precisely

correct in this drawing because the LBA signals, addresses to the line buffer in the video processor, are
not pure squarewaves and have variations in their periods (see the DCO11 section). These variations
give the keyboard signal the appearance of clustering in groups of four, but they do not affect the
operation of the circuit.
The negative transition of each output pulse occurs at the clock interval regardless of the presence of
data. This transition is therefore the reference point for the keyboard clock at the receiving end.
4.4.6.4
Combined Interface Signal - Figure 4-4-7 illustrates the four possible conditions on the interface line when the effect of the clock is included. Figure 4-4-8 shows all four states and the transitions
between each of them. Two series sensing resistors in the interface circuit divide the signal in half at the
wire. Therefore, although the drivers swing 12 volts at each end, the figures show only 6 volt variations.

4.4.6.5
Decoding of Data from Terminal - The keyboard recovers the modulated clock signal sent by
the terminal but must also separate the data from the clock. The signal is sent directly to the UART
and address counter circuits as a clock. The negative edge of the clock occurs at a fixed interval while
the positive edge varies according to the duty cycle modulation. The keyboard circuits use the negative
edge and ignore the variable pulse width.

Data is extracted from the combined clock-data by a simple resistor-capacitor filter on one input to a
comparator. The other comparator input is referred to one-half the power supply. Because the duty
cycle of incoming data is either 1/4 or 3/4, the capacitor charges to that proportion of the supply
voltage over the 16 clock periods of each bit. The comparator switches when the capacitor voltage rises
or falls past the reference value. The short duty cycle of zeros averages to a low voltage that holds the
comparator output low. The long duty cycle of ones averages to a high voltage and switches the
comparator to a high state. The comparator output goes to the serial data input of the UART where it
is deserialized. When all ten bits of a transmitted character are loaded into the UART, it asserts Data
Available. This signal enables the bell and scan start if the appropriate bits were set in the byte. The
LED bits remain latched at the parallel output of the UART until the next command byte arrives.

4.4.6.6
Keyboard Output - The keyboard UART serial output goes directly to an open collector
driver that swings its end of the bidirectional signal line between 0 and +12 volts. This is shown as E8
and R15 in Figure 4-4-5a. The circuit is identical at both ends of the interface.
4.4.7

Bell

The keyclick /bell circuit provides audio feedback and attention signals for the user. A bit in the
keyboard status word controls the bell. Refer to Figure 4-4-9 for the circuit. Capacitor C8 charges to
+5 volts through resistor R16. The speaker connects between the capacitor and the collectors of the
transistors in E1. When a single status word contains the bell bit, flip-flop E3 toggles and turns on EI.

C8 discharges through the speaker and El, generating a click. When the voltage on C8 falls low
enough, it clears E3. El turns off and C8 charges up for the next click. The value of C8 is selected to
determine the volume of the click. D8 protects the transistors from inductive spikes from the speaker.
If the bell bit is set for many words in succession, the UART latch holds the data output constant. A

one clock period pulse from the Data Available flip-flop E6 gates the bell bit through ES to form a
clock to E3. As C8 discharges through the speaker and El, E3 clears itself, turning El off. Then C8
charges up again until the next Data Available pulse clocks E3 on again to repeat the discharge cycle.

C8 discharges fast enough so each Data Available pulse (which arrives every 1.28 ms) triggers a cycle,

4-38

[ o IR i S I T

O D (S ) S B S

- _

4-39

allowing the circuit to produce an 800 hertz tone. Bell is generated by setting the bell bit for 0.25
seconds (about 200 status words). Each cycle of the tone is at a reduced amplitude compared with the
single keyclick because R16 is selected to limit C8’s charging rate. The overall effect of the tone burst
on the ear is that of a beep.

INTERFACE

KEYBOARD | TERMINAL

STATE
__________

LT,
e

T .

TERM XMITS 1

[

ANNANRNACOArr-

[

]

]
]

c------d
W GEE G GEn GNP SNp ;P SER —-fl

[

ol
TERM XMITS O

KEYBOARD XMITS O

TERM XMITS 1

KEYBOARD XMITS 1
MA-4666

Figure 4-4-8 Keyboard Interface Signal

4-40

R16
+5 —-AM—

C8 A<

£
BELL

‘1;

| FLIP

SPEAKER

FLOP

BIT

E3
O.—J

—

CLEAR]

MA-4658

Figure 4-4-9 Bell Circuit

4.4.8 Keyboard Interrupt Routine
When the microprocessor responds to an interrupt from the keyboard UART and reads a key address
from the UART data output, it immediately range tests the address. The function key addresses are all
above the regular key addresses, with SET-UP the lowest at 7BH and the always down Last Key at
T7FH. An incoming function key address causes a bit to be set in a flag byte called Keys (Figure 4-4-10).
When a key address below the function range arrives, the microprocessor checks the low three bits in
Keys for the key count. If the count is less than three, the key address is stored in a three place New
Key Address Buffer and the counter is incremented. If the count is already three, the counter is incremented but the key address is discarded.

[
|

KEY COUNTER ]
|

CAPS

CONTROL

LOCK

LAST

KEY

OVER
FLOW

SHIFT

SETUP

BIT
MA-4291

Figure 4-4-10 Keys Flag Byte

4.4.9

Logical Keyboard Processor

The logical keyboard processor is that portion of the operating firmware that manages the interpretation and transmission of keyboard data. It consists of several processes.

4-41

4.4.9.1

Key Recognition — For a key to be recognized as a new key, it must not have been down in the
scan before entry is accepted. The microprocessor checks each key’s history at each scan. If a key was
down during the last scan, it is old and is not entered. Only new keys, those not previously seen, are

entered. This system allows a key to be held down without being continuously entered at each scan.
(This process and auto repeat are discussed later.)

If a key is detected as down for the first time in a while, the microprocessor assumes that it has been
pressed. During the scan when the key is first down, the contacts may bounce for several milliseconds.
The time window when the contact is scanned is very short. If the contact happens to be bouncing open
during that interval, it is not detected in that scan but the time between scans is long so it is finished
bouncing by the next scan and is detected normally. If the contact happens to be closed for the first
scan while still bouncing, it is detected. It is also detected on the next scan after it has stopping

bouncing but now it is an old key and is not reentered.
When the microprocessor is free to perform its background routines, it processes the results of the last

keyboard scan. First it checks the high bit of the Key’s byte to see if the scan is finished. If it is not, the
microprocessor continues with other work (exits). If it is , the microprocessor checks the key counter

overflow bit representing four or more keys sent in the scan. If the bit is set, the microprocessor clears
the New Key Address Buffer and exits.
If the overflow bit is not set, the first key is taken from the new key address buffer and tested. If it is

either the SET-UP or NO SCROLL key, the microprocessor acts on it immediately and branches to
the appropriate routine. It then returns to the keyboard process. (Refer to the microprocessor section
for a discussion of SET-UP and to the Communication section for no scroll.)
Another three place buffer contains the keys from the last scan. The microprocessor compares the
three new keys with those in the old key buffer. If an old key is not in the new key address buffer, that
key is cleared from the old key buffer. New keys then go into the old key buffer. Each key address is
only seven bits long, so the high bit in each key entry is used to indicate how long that entry has been in
the buffer. If a key 1s new, the bit is set to 0. This means that the microprocessor has only seen the key
once. If the key appears in the new key address buffer on the next scan, the microprocessor sets the
high bit to 1, converts the key address to an ASCII code, and sends it to the keycode buffer. Only one
key is converted and sent in each cycle of the logical keyboard processor routine. Since the set bit
indicates that the key has been sent, in the next cycle that key will be ignored and the next key will be
processed.
4.4.9.2

Key Rollover - Key rollover means that more than one key can be down at the same time and
be accepted. Normally the VT100 accepts 3-key rollover. If the keys were pressed during different
keyboard scans, they will be accepted in the order in which they were pressed. If they were all pressed
during the same keyboard scan, they will be accepted in the order of their addresses.

Certain conditions will limit the rollover to only two keys. The 2.5 key rollover specification reflects
the presence of these conditions. Because there are no isolating diodes in the switch matrix, certain
patterns of contact closure can produce false key down indications. Specifically, three switches closed
in three corners of a rectangular pattern, as in Figure 4-4-11, will cause a fourth apparent key address
to be sent to the terminal. (Refer back to Figure 4-4-3 to see how the pattern fits into the row-column
configuration.) For this reason, although any number of key addresses may be sent by the keyboard
during a scan, no more than three may be sent if any are to be accepted. If four or more appear, the
terminal ignores all of them and waits for a scan with only three. The special function keys (SHIFT,

CAPS LOCK, CONTROL, SET-UP) are in a part of the matrix where there is no pattern sensitivity
and no ambiguity. They all are accepted in the same scan with the regular keys and are not counted in
the 3-key maximum.

4-42

K
—-———————-/

RS
A

SCANNING ORDER

OUTPUT

COLUMN 5.ROW 7

C5-R8

C4-R7 (C4 SEES C5—R7

K (FALSE 4TH KEY)

THROUGH G, H)

Ca-R8
M A-4668

Figure 4-4-11 Sneak Path

The sneak path problem is also the reason that the keyboard processor looks for the appearance of a
key in two successive scans. In Figure 4-4-11, the keys are scanned in the order J, H, K, G. Normally,
the keyboard processor counts the number of keys in a scan and ignores all of them if the count is over

three, as it is in this case. But it is possible for a user to briefly press keys J, H, and G and then release
G before the scan is completed. Then the keyboard processor might see J, H, the false key K, and,
because G was lifted just before it was scanned, register only three keys. One key would be false, but
with a count of only three, all would be accepted. To prevent this, the keyboard processor looks for the
same keys two scans in a row. Because the G key is released, the K key does not appear in the second
scan, and only J and H appear and are accepted by the keyboard processor.
4.4.9.3

Generation of Codes - Because the keys are essentially randomly ordered with respect to the
ASCII standard, the program ROM includes several look-up tables that assist in the generation of
ASCII codes. Most keys convert directly from an address to an ASCII code. The codes for alphabetic
keys with SHIFT or CAPS LOCK down are formed from the tables with bit 5 forced to 0 to produce
uppercase alphabetic codes. Holding down the CONTROL key when another key is pressed causes
another table look-up. If the key is in the table of valid control codes, that keycode is changed by
forcing bits 5 and 6 to 0. For example, the ASCII code for the letter ““g” is 67H. Holding down the

CONTROL key and typing G transmits the ASCII code 07H.

Normal code
Control code
Shift code

B7
X

B6
1

BS
1

B4
0

B3
0

B2
1

Bl
1

B0
1

X
X

0
1

0
0

1
1

4-43

Nonalphabetic keys have a second look-up table that provides the shifted code given the unshifted

code. CAPS LOCK performs the shift function only on alphabetic codes, leaving the nonalphabetics

to be performed with an extra shifting action. If a key that does not make a standard control code is
pressed with CONTROL, it is not sent.
4.4.9.4

Keyboard Transmit Buffer - Some keys generate three byte ASCII codes. The auxiliary keypad, for example, when in alternate mode, transmits escape sequences that a system can be programmed to interpret in a special way. Cursor control keys also send escape sequences which the operator

can use to control the cursor position. To store the codes that might be generated by three simulta-

neous keys, a 9-byte buffer is provided for the communication port. If the buffer fills up, the keyboard
1s locked and the appropriate LED lights. When a key is about to be converted to ASCII and stored in

the buffer, the microprocessor checks the buffer to see if there is room. Since any key might produce
three bytes of code, the microprocessor must be sure that there are at least three places available in the
buffer. If six 1-byte keys have been sent, the next 1-byte key leaves only two places. Therefore, the
keyboard locks with only seven places filled in the buffer.
4.4.9.5

Auto Repeat - If only one key is in the old key buffer (in the logical processor), and if it

appears continuously, it may be a candidate for auto-repeating. A key with control cannot repeat, and
a nonrepeat table contains a few keys that do not repeat. These are SET-UP, NO SCROLL, ESCAPE,

RETURN, BREAK, and ENTER.
A count-down timer gets loaded with a value each time the buffer changes. When there is no change
for a while, the timer decrements to zero. This takes about one-half a second. Then the key is sent to
the keyboard buffer a second time and the timer is loaded with a smaller value. This time the count
lasts about one thirtieth of a second. The key is sent and the timer reset the same way until the key is
lifted or another key is pressed while the first is still down. If the second key is lifted, the count

continues at the fast rate. The timer is decremented every time a status byte is sent to the keyboard
(every 1.27 ms).
4.5 NONVOLATILE RAM
The nonvolatile RAM (NVR) used in the VT100 can retain its data for about 10 years and 1 billion
reads. This type of device is also called electrically alterable read-only memory (EAROM). It contains
the programmable configuration information that would otherwise have to be reentered every time power was turned on or else stored in mechanical switches.

While the microprocessor sets up initial conditions using the specifications in the NVR, a user can
change those settings at any time from the keyboard. However, the new settings are only stored in the
scratchpad memory until a special Save sequence is initiated from the keyboard to store the settings in
the NVR.
This section contains an overview of NVR principles, the circuitry used with this particular device, and
the microprocessor’s procedure for using the NVR. Information about the SET-UP data contents may
be found in Section 4.7.11.
4.5.1

Principles

An NVR memory cell consists of an MNOS (metal nitride oxide semiconductor) field effect transistor
whose gate is insulated with a material (silicon nitride) that can accept charge movement through itself
and yet hold a charge as a superior insulator. Under high voltage conditions, electrons can migrate between the insulating layer and the substrate, leaving a net charge buried in the insulator. This is the
process of erasing and writing.
An FET transistor normally has a physically determined voltage required between its gate and channel
for it to conduct. A charge in the insulator between the gate and channel adds algebraically with the
voltage on the gate and shifts the value of threshold voltage accordingly.

4-44

A reference voltage is applied to the gate of a memory transistor in the read process. If the threshold is
below the reference, the transistor will conduct. If the threshold is above the reference, there 1s no
conduction. Decay of the stored charge causes the difference between high and low thresholds to
become smaller. At normal operating temperatures this decay takes 10 years to affect recovery of data.
Erasure consists of writing all the memory cells in a word to the same low threshold. Writing pushes
the selected cells to a high threshold. The time required to write or erase is determined by the thickness
of the gate insulation, the voltage used, and the temperature of the device. The thickness of insulation
is a trade-off between writing time and data longevity.

The writing process damages the insulating properties of the nitride layer. With the ER1400’s layer
characteristics, its data retention time is at least 10 years provided that it is written less than 1000 times.
The data retention time is at least 1 year if it is written between 1000 and 10,000 times.
4.5.2

NVR Device

The ER1400 (E24) is a 1400-bit memory arranged as 100 14-bit words. Data and addresses enter or
leave the device in serial form through a single bidirectional line. Information is shifted with an external clock; identification of the meaning of the bit stream is made by setting three control lines that
specify the operation in progress (Figure 4-5-1).

DATA REGISTER

14 BITS

DATA

| BUFFER

1/0

[

MEMORY

10BITS |ApDRESS
|-+

ARRAY

TENS

100 X 14

<EAD

MODE

_WRITE

< ASE

ADDRESS

DECODE

LOGIC

c,
|e—

|le—,

Y
DECODE

CLOCK |g—

GEN

UNITS ADDRESS

CLOCK

10 BITS
MA-4308

Figure 4-5-1 ER1400 NVR Block Diagram

4-45

4.5.3

NVR Control
Seven states of the three control lines give commands to the NVR device:

Data Bus

State

Standby. The device output floats.

Accept Address. Two 1 of 10 addresses are shifted in at the clock rate.
The first group is the 10’s decade and the second is the 1°s decade of the

1 of 100 word address.
2

Erase. The word stored at the addressed location is erased to all zeros.

Accept Data. The data register accepts serial data shifted from the I/O
pin. The address register remains unchanged.

Write. The word contained in the data register is written into the
location designated by the address register.

Read. The addressed word is read from memory into the data register.
Shift Data Out. The output driver is enabled and the contents of the data
register are shifted out.

4.5.4

Not Used.

NVR Support Circuits

Several factors in the ER1400’s design require special treatment by its support circuitry. It requires 35
volts for the write and erase processes. Its signal levels are specified to be Vss (the positive power
supply) for the high level and 12 volts lower than that for low. The logic of these signals is negative: 1 is
asserted as a low level, and 0 is asserted high. When driving data, the NVR’s output actually switches
between +12 and -23 volts with a high impedance in series with the negative source. This requires that
an external clamping diode (D4) be present to pull the low level up to ground through the high
impedance. 12 volts and ground are thus the I1/O logic levels. The terminal controller is made with
TTL, so open collector buffers with pull-up resistors to +12 volts are the interface.

The Standby command of the ER1400 is not used in the VT100. Instead, Accept Data serves as the
command to the NVR during idle periods. The code for Accept Data is all inputs low. This arrangement protects the contents of the NVR from spontaneous writes that might occur due to the powerdown behavior of E29, the 7417 open-collector buffers. E29, in powering down, tends to drop its
outputs from the high to the low state in an unpredictable order. This could present a write command
to the NVR before the power supply voltages drop low enough, if the NVR had been maintained in the

Standby mode by keeping its inputs high. By keeping all outputs low with the Accept Data command,
no new command can occur accidently during power-down.

4-46

The pull-up resistor used to drive the data input is too low an impedance for the ER1400 output to
drive. Line C2 is high during state 5 when the output driver is enabled, and low when data is being
input to the NVR, so transistor QI’s base is connected there. When the line goes high, QI turns off,
raising the impedance at that point to the leakage values of Q1 and E29, and the input impedance of
comparator E48. D4 clamps the output to -0.6 volts to protect the comparator input from leakage to
-23 volts in the ER 1400.
Later VT100s may have power down circuitry in series with the Vgg pin on the ER1400 to ensure that

the -23 volt supply is cut off when the +5 volt supply is low. This would prevent writing during powerdown.
The comparator is a high impedance load for the ER 1400 output driver and is biased to switch at +8
volts. This threshold ensures that a wide range of output levels will still pull the low state down enough

to switch the comparator. The comparator output, pulled to +5 volts by a resistor, provides the NVR
DATA bit to the flag buffer. The microprocessor reads the flag buffer after it sees the NVR clock flag
change, and samples the NVR DATA bit to get the serial data.
The NVR clock is the lowest frequency line buffer address signal and occurs at the horizontal line rate,

15734 kHz. This is the bit shifting rate during address and data transfers. A read operation requires
only a single clock cycle to transfer data into the data register but an erase or write of a word each
takes 20 milliseconds.

4.5.5

Microprocessor Management

During an NVR operation, the microprocessor uses 21 bytes of scratchpad memory to set up a group of
NVR address or data bits. Each group consists of 20 bits of address or 8 bits of data with another 6 bits
of fill for the 14 bit NVR word. These groups must enter the NVR serially with precise timing. The
microprocessor cannot calculate the groups fast enough to keep up with the shifting process while also
managing the shifting process, so it saves time by precalculating and storing each group of bits. Then it
reads the stored groups, and delivers them to the NVR at the NVR clock rate through the NVR latch.
The microprocessor serializes its data by rotation in a register. It combines the data with command bits
to control the NVR device. Output from the microprocessor reaches the NVR through the NVR latch.
The latch 1s updated at each clock during an NVR operation. One unrelated signal from the communication port is routed through an extra bit in the NVR latch device.

The microprocessor reads the NVR during the power-up process. The bits are deserialized by rotation
as they are read in. Although 14 bits from each NVR word are written or read, only 8 bits are used by
the microprocessor. The data goes into location in the scratch portion of RAM for use during a later
portion of the power-up.
4.5.6

NVR Timing
Use of the ER1400 in the VT 100 takes place during normal operation of the video circuits. The 8080
must be free to operate on every scan line in order to load data and address and shift data out (the
ER 1400 1s clocked at the horizontal rate and this signal is provided as a clock to the flag word for the
8080). Because of the above two conditions, it is necessary to ensure that all DMAs performed by the
video processor are short.

The processor works fast enough to permit the display of the short message “WAIT” at the left edge of

the screen. This causes the DMA to be longer but informs the operator during long save and recall
sequences. The timing for all of these conditions is shown in Figure 4-5-2.

4-47

CLOCK SIGNAL ON
5 OF NVR
PIN

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—

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«—TTL L (0)

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—

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HOLD REQUEST

132 COLUMN MODE 1
-]

HOLD REQUEST

80 COLUMN MODE

[

- 12
Vss

[*— 10 us + 623 ns FOR EACH CHARACTER DISPLAYED

le—11.3 us + 373 ns FOR EACH CHARACTER DISPLAYED
MA-4299

Figure 4-5-2 NVR Signals

All data and command changes to the ER1400 occur immediately following the falling edge of the
clock flag (the rising edge of the signal on pin 5 of the ER1400); the data is strobed into the NVR on
the opposite edge. The two one-of-ten codes for address have a single zero and nine ones (at DO of the
8080 bus).

When the “shift data out”” mode is entered as per the timing diagrams in Figure 4-5-3, the first data bit
may appear when the mode is entered but will become stable 25 us later; subsequent data bits will be
shifted out on the falling edge of the clock flag (rising edge of the signal on pin 5 of the chip) and will
become valid 25 us later. This means that, following a change to ‘“‘shift data out” mode or a falling

edge of clock flag during this mode, a delay of 25 us must occur before reading of the NVR data flag is
attempted. The first bit shifted in when writing is the first bit shifted out when reading.
When using the ER1400, it is necessary to operate with interrupts off.
4.6

VIDEO PROCESSOR

The video processor is the heart of the VT 100 display. It is composed of the devices shown on the right
side of the terminal controller block diagram (Figure 4-6-1). This section discusses the general mechanism that converts data into a visible display, followed by a discussion of the two central devices (the
timing and control chips) followed by a general discussion of all the other blocks on the video processor side of the block diagram. The interactions between the data paths on the left of the diagram and
the processor on the right are covered in Section 4.7, Microprocessor - Video Processor Interface.
4.6.1

Introduction

The video processor converts data into an electrical signal that a CRT monitor can turn into visible
letters, numbers, and symbols. The video processor works with the characteristics of the CRT monitor
to do this. A brief description of these characteristics precedes an introduction to the video processor’s
operation.

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4.6.1.1
The Raster - The raster is that area on the CRT screen that is scanned (passed over) by an
electron beam moving in a regular pattern. Deflection coils cause the beam to quickly scan a series of
horizontal lines while moving relatively slowly down the screen. This scanning repeats quickly and
constantly, and persistence of vision makes the entire screen look continuously scanned. The beam
may be on or off, lighting the fluorescent phosphor on the face of the CRT or leaving it dark, but the
beam’s continuous motion traces and defines the raster.

4.6.1.2
Character Formation - As the beam moves in its horizontal scans, it can be turned on and off
very fast. This means that a spot of light (called a dot) can be produced anywhere along each horizontal scan line. Each scan contains the same number of potential dots. If only one dot is lit in a scan but
dots in the same position on several successive scans are also lit, the screen appears to have a vertical
line on it. This ability to line up dots on different scans is the key operating feature of the video
processor.

Limiting our discussion to 80 column lines for this description, each character that can be displayed on
the VT 100 is made up of a matrix of dots, ten wide and ten high (Figure 4-6-2). There are 800 dots in a
scan and the raster is made of 240 scans. So there are 80 groups of ten dots in each scan horizontally,
and 24 groups of 10 scans vertically. Each 10 dot X 10 scan group is a character cell, where a character
can be displayed, and there are 80 X 24 character cells on the screen. As the electron beam scans the
raster, the video processor turns the beam on and off, assembling the characters scan by scan.

INTERCHARACTER
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MA-4655

Figure 4-6-2 Dots, Scans, and Characters

4-51

4.6.1.3
Video Processor Data - When we say the characters are assembled scan by scan, we mean
that only one scan of information about a character is displayed and then the same scan for the next
character is displayed. This continues to the end of a line of characters. Then the next scan of the first
character is displayed, followed by the same scan of the next character, and so on. Therefore, each

character must enter the video processor ten times, once for each scan, and remain only until the next
character in the line is displayed.
Each character in a line is stored in one of a group of adjoining locations in the screen RAM. (See
Figure 4-6-3 for the video processor functional diagram.) The process of moving a line of character

data from the screen RAM to the video processor takes the same amount of time as a scan. During
data movement, the microprocessor cannot use the RAM. So, to give the microprocessor as much
working time with the RAM as possible, the video processor accepts the line of character data for
display during the first scan and stores it in its line buffer at the same time for use during the other nine
scans. Movement of data from the screen RAM to the line buffer by the video processor is called direct
memory access (DMA). During the DMA, the video processor provides addresses to the screen RAM
with the address counters. The data is stored in the line buffer which gets its addresses from the line
buffer address (LBA) outputs from the DCO11 timing chip. Both kinds of addresses change values
when they receive a clock (called character clock) that occurs after each 10 dots. This clock makes the

character data in the video processor change at the right times to provide proper alignment of the
display.
The character latches hold the data coming from the screen RAM or line buffer and ensure that the
data remains stable for long enough periods to be written into the line buffer or the video shift register.
The buffer between the latches is tristatable and, during non-DMA time, prevents the normal data
flow on the microprocessor data bus from interfering with the video processor’s reading of data from
the line buffer.

4.6.1.4
Video Processor Character Generation — Data, coming either from the screen RAM for scan |
or the line buffer for scans 2 through 10, becomes part of an address to a character generator ROM.
(See Figure 4-6-4, Character Generator Example.) The rest of the address comes from a scan counter
in the DCO12 control chip. The scan counter addresses the ROM according to which ofthe ten scans is
to be displayed. The 4-bit scan counter skips over the other 6 possible addresses to the ROM, so the
ROM contains data in only 10 out of 16 locations. The output of the ROM is eight bits that represent

the pattern of sequential dots to be displayed for that character on that scan. The eight bits enter the

video shift register, a serializer that converts the eight parallel bits into a one-bit-wide stream. An extra
flip-flop stores the last bit so it can be output to the stream two or three extra times (depending on line

length) to fill the intercharacter space. The stream enters the DCO12 control chip, where the final
adjustments for video display are made, and then the video signal goes to the CRT monitor.

4.6.1.5
Attributes — Three attributes apply to the VT 100 display: character, line, and screen. Character attributes provide a special appearance to characters as they appear on the CRT screen. In the basic
VT100 (without an advanced video option) only one bit of memory (called the base-attribute bit) 1s
available to each character on the screen. The original character data from the screen RAM is eight
bits wide but only seven bits define the character itself. The eighth bit defines the base attribute. The
attribute bit bypasses the character generator ROM and video shift register and enters the DCO12.
There it controls the presence or absence of the attribute as that character is displayed. The base

attribute is displayed as either reverse video or underline, depending on the selection of the cursor at
SET-UP, and is invoked by the base attribute bit. Reverse video appears as all 10 scans of a character
cell reversed (black changes to white and vice versa). Thus, if two vertically adjacent characters are in
reverse video, no black space appears between them. Underline forces the ninth scan on (off with
reverse video screen attribute.) Once a character attribute or combination of attributes is set, all displayable characters sent to the terminal have that attribute regardless of where they are placed on the
screen. This continues until the attribute selection is changed.

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Figure 4-6-4 Character Generator Example

Line attributes are double height, double width, and scroll. The VT 100 displays single-width, doublewidth or double-height, double-width characters on a line by line basis. All characters on one line

appear in the same mode. Double-width lines are generated by displaying each dot of a character twice
in the horizontal direction. Double-height, double-width lines are generated by displaying each dot of
a character four times (twice horizontally and twice vertically). The top and bottom halves of a doubleheight, double-width line must be entered as two separate lines of characters. The scroll attribute
indicates that a line is part of the scrolling region.
Screen attributes affect the entire screen’s characteristics at once. They include the base attribute
selection (reverse or underline as mentioned under character attributes), reverse video over the entire
screen, 80 or 132 character line length, 50 or 60 Hz refresh rate (chosen according to the local power
supply), interlaced or noninterlaced operation, and jump or smooth scrolling of data over the screen.

4.6.1.6
Advanced Video Option (AVO) - The AVO extends the length of the screen RAM so more
characters can be displayed in 132 column mode. In addition, it allows each character to have four
more attributes, for a total of five. Three of the AVO attribute bits enter the DCO012 to control displayable features of each character. The fourth AVO attribute bit controls the selection of an extra
character set by switching in an optional alternate character generator ROM that can provide nonASCII characters or other special displays.

To provide the extra attribute bits, the AVO widens the entire screen RAM by 4 bits to make each
character location 12 bits wide. It also contains a 4-bit wide extension of the character latches and a 4bit wide attribute line buffer, addressed by the same LBA signals as the regular line buffer. This
extension treats the attribute data with the same timing as the character part of the circuit, and
matches each character with its attributes.

With the AVO present, reverse video, underline, bold, and blinking are all available singly or in
combination. Reverse and underline appear as described above with the addition that if both reverse
and underline are asserted, the underscore is forced dark instead of light. Bold increases the intensity
of the display. The blink rate is about half that of the cursor or about 0.5 Hz. Cursor selection is
independent of character attributes when the AVO is installed.
4.6.2

Timing Chip Description

The DCOI11 is a custom designed bipolar integrated circuit that provides most of the timing signals
required by the video processor. Internal counters divide the output of a 24.0734 MHz oscillator
(located elsewhere on the terminal controller module) into the lower frequencies that define dot, character, scan, and frame timing. The counters are programmable through various input pins to control
the number of characters per line, the frequency at which the screen is refreshed, and whether the
display 1s interlaced or noninterlaced. These parameters can be controlled through SET-UP mode or
by the host. In the following discussion, refer to the block diagram in Figure 4-6-5.

4.6.2.1
Input Decoder - The input decoder responds to commands on the DO H and D1 H pins
(connected to D5 and D6 of the 8080 bus respectively) whenever the VIDEO WR 1 L pin is low. The
outputs of the decoder select 80/132 column, 60/50 hertz refresh, and interlaced /noninterlaced modes
of operation. Table 4-6-1 shows that when D1 H is low the number of columns is programmed according to the state of DO H, and when D1 H is high the refresh rate is programmed. Interlaced mode is
always selected when the column mode is set, and noninterlaced mode is selected when the refresh rate
is set. The interlace mode that is in use depends on whether ““number of columns” or “‘refresh rate”
was selected last.

Table 4-6-1 Video Mode Selection
(Write Address = C2H)
Inputs

DS
Pin 21

D4
Pin 20

80 column mode

]

132 column mode

0
1

60 hertz mode
50 hertz mode

Configuration

Sets interlaced mode

Sets noninterlaced mode

In addition to strobing data into the input decoder, VID WR | L also acts as a reset signal for the
DCO11. Whenever VID WR 1 L is low, the counters in the DCO11 are held in a cleared state. Resetting
the counters serves no purpose in the VT100 because the remainder of the VT 100 synchronizes itself to

the DCO11, but a reset is useful for testing both individual chips and complete modules. Because
writing into the DCO11 would cause the counters to reset and disturb the display, this is never done

unless the mode is being changed.

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4.6.2.2
80/132 Column Selection - The column mode is changed by modifying the divisors of three of
the counters in the DCOI11. The first of these counters divides the input clock (MASTER CLK) by 1.5
to produce the dot rate clock for 80 column mode. The DOT CLK output provides the signal that
controls the shifting of dots out from the video shift register. A multiplexer determines what rate DOT
CLK will have for the entire screen by selecting either the output of the divide-by-1.5 in 80 column
mode, or by selecting the 24 MHz MASTER CLK directly in 132 column mode. The other two
counters affected by 80/132 selection are the dot counter and the horizontal counter.
4.6.2.3

Dot Counter - The dot counter uses four flip-flops to divide the DOT CLK that was selected

by the multiplexer by 10, in 80 column mode, or by 9, in 132 column mode. The output of the dot

counter 1S the character rate clock, which is used to move character codes in the latches that are outside
the DCOI11. Character clock is further divided by the horizontal counter. The timing of CHAR CLK is
shown in Figures 4-6-6 and 4-6-7 for each of the two column modes. CHAR CLK is unaffected by
double-width mode. The output of the next-to-last flip-flop is used for the write enable signal for the
line buffer RAMs (WRITE LB L). WRITE LB L is also shown in Figures 4-6-6 and 4-6-7. This signal

allows the data and address changes, caused by the rising edge of CHAR CLK, to become stable
before writing is enabled and then disables writing before CHAR CLK rises again. WRITE LB L is
gated directly with HOLD REQ H so that it is active only during DMAs. Intermediate signals from
the four flip-flops are used by various other functions in the DCO11 such as the double-width multiplexer and the composite sync generator.

80 COL — SINGLE WIDTH

—

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[
1

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|
MA-4297

Figure 4-6-6 Video Latch Timing - 80 Column

4-57

132 COL — SINGLE WIDTH

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Figure 4-6-7 Video Latch Timing - 132 Column

4.6.2.4
Double-Width Multiplexer - The double-width multiplexer (MUX) produces the three signals
whose timing must be changed when a line of characters is switched between single- and double-width
modes. The frequency of DOT CLK must be divided in half on a double-width line so that the video
shift register will shift half as often, making each dot (and therefore each character) twice as wide as it
would be in single-width mode. In order for the video shift register to work properly with the half-rate
DOT CLK in double-width mode, the load signal for the shift register (VSR LD H) must still come
every 10 dots (80 column mode) or 9 dots (132 column mode). Therefore loads must occur at every
other CHAR CLK. Similarly, incrementing the DMA address counters occurs on every other CHAR

CLK to ensure that characters that are stored sequentially in the screen RAM are presented to the shift
register at the correct time for each VSR LD H pulse. The different modes of DOT CLK and VSR LD
H are shown in Figures 4-6-6 and 4-6-7.

In single-width mode, the double-width MUX directs the output of the 80/132 MUX to the DOT
CLK pin, providing either a 16 MHz or 24 MHz output. To get the half-rate DOT CLK for 80 column
mode, the double-width MUX selects the output of the first flip-flop in the dot counter, that acts as a
divide-by-2 because the dot counter is dividing by 10 (10 is an even number). In 132 column mode the
same selection cannot be made because the dot counter is dividing by 9. But the divide-by-1.5 is not

needed in 132 column mode, so this divider is converted to a divide-by-2 and the double-width MUX
selects its output when a double-width line is displayed in 132 column mode.

4-58

The load input of the video shift register used in the VT 100 is a synchronous input. This means that
when the load input is high, the rising edge of DOT CLK causes a parallel load to be performed
instead of a shift. To get one load and many shifts for each character, VSR LD H can only last for that
one cycle of DOT CLK that is adjacent to CHAR CLK. Furthermore, transitions of VSR LD H must
satisfy SET-UP and hold times with respect to the rising edge of DOT CLK. In single-width modes,
VSR LD H is one dot time wide, generated from the outputs of the dot counter, and its SET-UP and
hold times are guaranteed by internal propagation delays. This relationship is shown in Figures 4-6-6
and 4-6-7 by a slight shift in the transitions of VSR LD H with respect to DOT CLK. In double-width
mode, VSR LD H is created by selecting every other CHAR CLK (Figure 4-6-8 shows a flip-flop that
divides CHAR CLK by two for this purpose) and then delaying this signal by one single-width dot
time.
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Figure 4-6-8 Address Count Timing

4-59

The signal that increments the DMA address counter (ADDR CNT) is shown in Figure 4-6-8. ADDR

CNT has the same timing as CHAR CLK; the difference is that it does not run continuously. Figure 46-8 shows that ADDR CNT can only be generated if HOLD REQUEST H is high and that it is further

controlled by a signal from the horizontal timing section (ADDR CNT ON H) that allows ADDR
CNT to provide exactly three pulses (in single-width mode) before HORIZ BLANK H goes low. The

three pulse delay primes the external character latches so that the dots for the first character on a line
are being loaded into the video shift register at the same moment that HORIZ BLANK H enables the
video at the beginning of a scan. The only change made to ADDR CNT for double-width operation is

that every other pulse is deleted, beginning with the first pulse (Figure 4-6-8).
4.6.2.5

Horizontal Counter - The block diagram in Figure 4-6-5 shows the horizontal divider broken
into three stages. The first divider is programmable according to the number of columns selected and is
driven by CHAR CLK from the dot counter. For 80 column mode the divisor is three: for 132 column
mode the divisor is five. The total division from MASTER CLK to the output of this first divider is 45,
independent of mode (for 80 columns: 1.5 X 10 X 3 = 45, for 132 columns: | X 9 X 5 = 45). Therefore,
the operation of all of the remaining dividers in the DCO11, which are driven from the first horizontal

counter, are also independent of the column mode. The second stage of the horizontal divider has a
divisor of 17, which is chosen to give the required number of displayable columns plus about 28
percent more to allow time for the monitor to execute a horizontal retrace. The last stage is a simple
divide-by-2 that provides the horizontal frequency. Designing the last stage to be a divide-by-2 guarantees that the signal at its input will have a frequency twice that of the horizontal frequency as required
by the vertical dividers to create interlaced operation. The total division from CHAR CLK provided
by the horizontal divider is 102 in 80 column mode and 170 in 132 column mode. In either mode the
frequency at the output of the horizontal counter is 15.734 kHz.
4.6.2.6

Horizontal Drive and Horizontal Blank - Two timing signals are generated from the horizontal counter to control those system functions occurring at the scan rate. These signals begin at the end
of a scan and last until the horizontal counter is incremented past a specific state that is decoded to
turn the signals off. The monitor requires a pulse at the end of every scan to tell it when to initiate a
retrace and begin the next scan; the duration of this pulse must be between approximately one-quarter

and one-half of one scan. Figure 4-6-9 shows HORIZ DRIVE L as produced by the DCOI11; the slight
difference in timing between 80 and 132 column modes is the result of design convenience and is not
significant to the operation of the VT100. HORIZ BLANK H is designed to allow 83 characters
during the forward scan in 80 column mode and 137 characters in 132 column mode. The extra characters are included for possible future use such as a field of indicators along the right margin of the screen
or as extra symbols inserted to mark text. The rising edge of HORIZ BLANK H is resynchronized to
CHAR CLK to eliminate the accumulated delay of the horizontal counter. The falling edge of HORIZ
BLANK H occurs between two CHAR CLKs (Figure 4-6-8) to meet some requirements of the DCO012,
but inside the DC012 HORIZ BLANK is delayed to the following edge of CHAR CLK so that the
beginning of each displayed scan will coincide with a character boundary.

4.6.2.7
Line Buffer Addressing - The line buffer memory stores one line of characters during a scan
on which a DMA occurs and then recalls these characters on each successive scan until the next DMA.
Because the line buffer is a random access memory, it has address inputs that must be provided with a
sequence of addresses that change at each CHAR CLK such that each character is stored in a unique
location. The horizontal counter can provide such addresses because it is incremented through a series
of unique states that repeat in the same sequence on every scan. Because of the three stages that
comprise the horizontal counter, there are nine flip-flops whose outputs must be converted into the
eight line buffer address (LBAs) outputs. The conversion is possible because the 9 flip-flops represent a

maximum of 170 states in 132 column mode (8 bits can represent 256 states). The DCOIl1 contains
gates that combine the output of the ninth flip-flop in the horizontal counter with the outputs of the

4-60

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other eight to generate some addresses that are not otherwise represented by the eight. The resulting
LBAs do not follow a normal binary counting sequence but the sequence of unique addresses repeats

exactly on each scan. Figures 4-6-10 and 4-6-11 show the LBA sequence for one-half of a scan; the
other half is identical except that LBA 7 is low.

Several of the LBAs are used as general purpose clocks in the VT100. LBA 3 and LBA 4 are used to
generate timing for the keyboard. These signals satisfy the keyboard’s requirement of two squarewaves, one twice the frequency of the other, even though every 16th transition is delayed (the second

stage of the horizontal counter divides by 17, not 16). LBA 7 is used by the nonvolatile RAM. The
31.468 kHz signal on LBA 6 could be used for power supply synchronization, although this is not done

in the VT100.

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4.6.2.8
Vertical Operation - To paint a complete picture on the screen, the monitor moves the
electron beam slowly from the top of the screen to the bottom, while it is also moving the beam quickly
from left to right to paint each scan. The vertical sweeps of the beam must be repeated continuously so
that the picture is refreshed often enough to prevent the appearance of flicker. In television terminology, a single pass of the beam from the top ofthe screen to the bottom (and the data displayed during
that time) are referred to as one field. A complete picture, which may contain one or more fields
depending on the type of interlacing in use, is called one frame. When the VT 100 is used in noninterlaced mode, each successive field is identical and therefore only one field is contained in each frame.
During interlaced operation in the VT100, there are two types of fields that alternate with each other
so that each frame consists of two fields. Even fields start at the top of the screen and display 240 scan
lines before reaching the bottom. Odd fields place their first scan line between the first and second
scans of the preceding even field and then place each additional scan between succeeding scans of the
even field. Interlacing the even and odd fields gives a whole frame of 480 scans, instead of 240 scans, to
provide increased vertical resolution. In noninterlaced operation, commands to the monitor to begin a
new field are always coincident with commands to begin a new scan. This causes the beam to always be
in the same vertical position when the first displayed scan is begun. But, in interlaced mode, odd fields
begin with a command for a new frame that occurs halfway through a scan line. This causes the beam
to have moved down the screen from where it would have been during an even field (by the distance
that it moves in one-half of a scan) when the first displayed scan is begun. Even and odd fields are
made to alternate by including an odd number of half-scans in every field. This is in contrast to
noninterlaced operation, where each field contains only complete scans. The VT 100 always displays
the same video information on both even and odd fields. Interlaced mode is provided for future use by
options that desire increased vertical resolution.

4.6.2.9
Vertical Counter - The 10-bit vertical counter, shown in Figure 4-6-5, determines the frequency at which the screen is refreshed by counting the number of horizontal scans to be included in
each field. The vertical counter uses the 31.468 kHz output of the horizontal counter so that it can
count the half-scans required for interlaced operation. Figure 4-6-5 lists the four available divisors that
select the interlace mode and keep the refresh frequency as close to the local power line frequency as
possible (to minimize interference with the screen from nearby equipment). The vertical frequencies
produced by these divisors are approximately 1/20 Hz above or below the nominal power line frequency.

4.6.2.10 Vertical Outputs - Three outputs are derived from the flip-flops in the vertical counter to
control the vertical refresh operations in the VT 100. These signals are shown in Figures 4-6-12 and 4-613 for all four modes. VERT DRIVE H is issued at the bottom of the screen to initiate a vertical
retrace followed by a new vertical scan. This operation is analogous to the effect of HORIZ DRIVE L
on horizontal scans. The time between any two VERT DRIVE Hs is a constant, equal to an even
number of half-scans in noninterlaced mode and equal to an odd number of half-scans in interlaced
mode. VERT BLANK L always enables exactly 240 scans during any field and blanks any remaining
scans. Furthermore, VERT BLANK L is always turned off exactly 20 scans after VERT RESET H in
60 Hz mode and 50 scans after VERT RESET H in 50 Hz mode. VERT BLANK L is always adjusted
to display complete scans even during odd fields in interlaced mode. VERT RESET H initiates the
DMA process at the start of every field. When VERT RESET H goes high, the DMA address counters

are reset to point to address 2000H in the screen RAM, all line attributes are cleared, and the scroll
counter in the DCOI12 is preset to the value stored in the scroll latch. (See the DCO12 description for
more explanation.) During noninterlaced operation and on even fields, VERT RESET H occurs at the
same time as VERT DRIVE H; but, on odd fields VERT RESET H is delayed one-half of a scan to
match the start of a horizontal scan. The relationship of VERT RESET H and transitions of VERT
BLANK L to HORIZ BLANK H and HORIZ DRIVE L is depicted in Figure 4-6-9. Notice that
VERT BLANK L always turns on or off when the video is already blanked by HORIZ BLANK H.

4-64

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4.6.2.11 Composite Sync - The COMP SYNC L signal supplied by the DCO11 is combined with
video information by the terminal controller board to produce the composite video signal that appears
on J9 at the back of the VT 100. An external monitor can use the composite video signal to reproduce
the image displayed on the VT100 screen. This is accomplished by using the video information to
control beam intensity and the composite sync waveform to synchronize the raster to the video information. The composite sync generator in the DCOI11 uses outputs from the dot, horizontal, and vertical counters to generate the complex timing of COMP SYNC L. COMP SYNC L consists of one of the
vertical intervals depicted in Figure 4-6-14 followed by 240 horizontal sync pulses, another vertical
interval, etc. The vertical synchronizing interval consists of a transition from horizontal sync pulses to
six equalizing pulses, six vertical sync pulses, six more equalizing pulses, and then a return to horizontal sync pulses. Two vertical intervals are shown in Figure 4-6-14. The vertical interval that begins an
odd field is similar to that which begins an even field except that the equalization and vertical sync
pulses are shifted by one-half scan with respect to the horizontal sync pulses. In noninterlaced mode all
fields are even fields; but, in interlaced mode every other field is an odd field. Figure 4-6-14 also shows
the relationship of COMP SYNC L to both HORIZ BLANK H and VERT BLANK L. COMP
SYNC L meets the requirements of EIA RS-170 and the NTSC standards for sync pulse generators.
4.6.2.12 Hold Request, Address Load, and Double-Width - The logic associated with HOLD REQ H,
ADDR LDL, and DW H is shown in Figure 4-6-5. The falling edge of HOLD REQ H sets ADDR LD
L to the low state; ADDR LD L is subsequently cleared by the falling edge of CHAR CLK, thus

creating a short low pulse on ADDR LD L at the end of each DMA. ADDR LD L stores, in their
respective registers, all line attributes and the memory address of the next line to be accessed by a
DMA. The rising edge of HOLD REQ H causes the value of DW H that was stored in the holding flipflop by the previous ADDR LD L to be transferred to a second flip-flop whose output controls the
double-width MUX. This means that the value of DW H stored at the end of one DMA by ADDR LD
L does not actually become effective until the beginning of the next DMA. The holding flip-flop for
DW H is cleared by VERT RESET H at the start of every field. HOLD REQ H is also used to enable
ADDR CNT and WRITE LB L only during DMAs. Interactions of HOLD REQ H with other signals

during a DMA are further defined in Figure 4-6-19.
4.6.3
Control Chip Description
The control chip (DCO012), like the timing chip, is a custom bipolar device. It accepts attribute specifi-

cations and timing signals and delivers addresses for the character generator ROM and attributes for
the video output to the monitor. It also generates the HOLD REQUEST signal that halts the microprocessor and initiates DMASs to get lines of characters. Refer to the block diagram, Figure 4-6-15.

The DCO12 performs three main functions:
1.

Scan count generation. This involves two counters, a multiplexer to switch between the
counters, double-height logic, scroll and line attribute latches, and various logic controlling
switching between the two counters. This is the biggest part of the chip. It includes all
scrolling, double-height logic, and feeds into the underline and hold request circuits.

Generation of HOLD REQUEST. This uses information from the scan counters and the

scrolling logic to decide when to generate HOLD REQUEST.
3.

Video modifications: dot stretching, blanking, addition of attributes to video outputs, and
multiple intensity levels.

4-67

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4.6.3.1
Input Decoder Functions - The input decoder accepts a 4-bit command from the microprocessor when VID WR 2 L is asserted. Table 4-6-2 lists the commands.

The low eight values are used to load the scroll latch with the offset for smooth scroll. The scroll latch
is loaded in two passes, first writing the two least, and then the two most significant bits. Because the
offset is a decimal value controlling 10 display scans, the combination setting the most significant bits

to 11B is not used in the VT100 (11B covers the range 12-16).
The input decoder also toggles the blink flip-flop by complementing the state of the flip-flop whenever

1000B is written. The blink flip-flop invokes blink only where the blink attribute is set.
To save external hardware the vertical frequency interrupt flip-flop is located in the DC012 because a
spare pin was available. It is set by the falling edge of Vertical Reset. It is cleared by writing 1001B

into the input decoder.
Set and clear of reverse field are not toggled because the absolute state is important and there is no
feedback for the system to detect the current state. Therefore, the two states are explicitly set to their
desired values.
1100B means set base attribute to underline and 1101B means set base attribute to reverse video.
1110B and 1111B are for future specification.

Any time the input decoder is loaded with 11XXB, the blink flip-flop gets cleared. This is the only way
to initialize blink in the chip testing process. The firmware does not currently use the ability to clear the
blink flip-flop but if hardcopy output was being implemented, it could be used to set the blink to a
known state during a freeze.
Table 4-6-2 Control Chip Commands

(Write Address = A2H)
D3 D2

Function

O
O
O
O

0
0
0
0

0
0
1
1

O
1
O
1

Load low order scroll latch = 00
Load low order scroll latch = 01
Load low order scroll latch = 10
Load low order scroll latch = 11

O
O
O
O

1
1
1
1

0
0
1
1

O
1
0
1

Load high order scroll latch = 00
Load high order scroll latch = 01
Load high order scroll latch = 10
Load high order scroll latch = 11 (not used)

1
1

0
0

0
O

Toggle blink flip-flop
Clear vertical frequency interrupt

1
1

0
0

1
1

O
1

Set reverse field on
Set reverse field off

Set basic attribute to underline*

1
1
1

0
1
1

1
O
1

Set basic attribute to reverse video*
Reserved for future specification *
Reserved for future specification*

*These functions also clear blink flip-flop.

4-70

4.6.3.2
Attribute Latches - The line attributes are managed by two latches that store the scrolling,
double height (DH), and double width (DW) bits. The first latch stores the incoming data when
Address Load (ADDR LD) goes low at the end of a DMA. Scrolling means that the next line will be
part of the scrolling region, DH means the next line will be double height, and DW specifies top or
bottom half for double-height lines. There is no double height, single width combination, so in double
height, double width is assumed. The DW pin also tells the DCO12 to extend HOLD REQUEST
during double width. The second set of latches for double width and double height are clocked by the
rising edge of HOLD REQUEST (similar to the second latch for double width in the DCO11) to invoke
the attributes at the beginning of the new line. The first latch stores those attributes from the end of
one DMA to the beginning of the next. It is the outputs of the second latch that invoke attributes in the
chip. The scroll bit is invoked by a different signal that will be discussed later. The pin defining
scrolling is the same pin as reverse video; it means scrolling when loaded in by ADDR LD L and it
means reverse video at all other times. The reverse video signal passes from the input pin around the
first latch directly to the attribute logic.
4.6.3.3
Scroll Counter - The scroll counter consists of two 4-bit, divide-by-10 counters called the
Scan counter and the Offset counter. Both are clocked at the horizontal rate to count scans. The Scan
counter is cleared by VERTICAL RESET so that it starts at 0 and counts by 10s down to the end of
the screen.
The Offset counter is loaded with the contents of the scroll latch by VERTICAL RESET. The Scroll
latch 1s loaded by the microprocessor and defines the offset between the Scan and Offset counters for
an entire frame because the Offset counter is only loaded at vertical reset time. The microprocessor will
load the latch with the offset for the next frame during the current frame.
At the beginning of a frame, the two counters divide by 10 but start at different numbers. If not
currently scrolling, the offset is 0 and there is no functional difference between the counters. If in the
middle of a smooth scroll, the offset will be some other value from 1 to 9. The scan address outputs
from the chip to the character generator ROM are either the output of the Offset counter or of the
Scan counter, depending on whether the current line is in or out of the scrolling region, respectively.
One of the two counters is selected by a 4-bit wide multiplexer (MUX) whose output is the Counter In
Use. The MUX is controlled by the scroll flip-flop which is the second latch for the scroll attribute bit.
Most line attributes (double height, double width) take effect when HOLD REQUEST goes high for
the line in which they are effective. They always take effect with the actual data being displayed.
However, the scroll flip-flop can only change state when crossing one of the fixed 10 scan boundaries
that are defined by the Scan counter reaching 0.
Each scan when the Scan counter reaches 0 is a scan on the screen where a change can occur from a
nonscrolling to a scrolling region, or from a scrolling to a nonscrolling region since this is normally
where one line of data changes to the next if the line were not scrolling. This is the only place changes
can occur because the bottom of a nonscrolling line of characters is the place for moving into a
scrolling region and the top of a nonscrolling line is the place for getting out of a scrolling region. To
get into or out of a scrolling region the Scan counter must be at zero. A 4-bit Boundary Detect decoder
gate is connected to the outputs of the Scan counter and clocks the scroll flip-flop when all its inputs
are zero. If the input to the scroll flip-flop (from the scrolling attribute latch) has been low and goes
high at the end of the previous line’s DMA, then on 0 (boundary detect), the output of the scroll flipflop, which is the control line of the MUX, causes the MUX to switch from the Scan to the Offset
counter. At the bottom of the scrolling region, the last DMA in the region gets a line from the screen
RAM with its scroll attribute not set so when the next 0 boundary is reached, as defined by the Scan
counter, the scroll zone is exited. This is because the scroll flip-flop will get a zero input again which
will switch the MUX back to the Scan counter right in the middle of the line that was partway through
scrolling.

4-71

4.6.3.4
Scan Count Math - The scan count output of the scroll MUX goes through combinatorial
logic that looks at the double height bit and the top and bottom half bit and decides whether those scan
counts need to be modified for double height before going out of the chip. If double height is not
asserted, the top and bottom half bit is ignored and the scan is passed through with 1 subtracted in

modulo 16 arithmetic. (Thus, 0 becomes 15, 3 becomes 2, 9 becomes 8.) If double height is asserted and
top half is asserted, then the operation is to divide the scan count by 2, and continue to subtract 1 after
dividing by 2 so the first scan = 15, second scan = 15, third scan = 0. If bottom half is asserted, the
operation Is to divide by 2 and add 4. This particular arithmetic arrangement was designed for an
external component that is no longer needed. Otherwise, dividing by 2 (and adding 5 for bottom half)
would be sufficient. Table 4-6-3 shows the scan count sequences for the various modes. The scan count
changes on the rising edge of HORIZ BLANK H.

Table 4-6-3 Scan Count Sequence
Normal and Double Width

SC3

SC2

SC1

Double Height Top

Double Height Bottom

SCO

SC3

SC2

SC1

SCo

SC3

SC2

SC1

SCO

]

NOTE: Top line of table is first scan of character line (where HOLD REQ H occurs).

4.6.3.5 Generation of HOLD REQUEST - HOLD REQUEST is the signal to the microprocessor
that makes it give up control of the data bus. Then the video processor can DMA a line of data out of
the screen RAM and place the data in the line buffer. Two principle conditions can generate HOLD
REQUEST. The most common is when the output of the Counter in Use = 0, meaning on the first
scan of a new line of characters. (The Counter in Use, which is the output of the scroll MUX, is either
the output of the offset or scan counter, depending on whether the current line is in or out of a scrolling
region.) Whenever a new line of characters starts, a HOLD REQUEST is needed to get the line’s data.
Therefore, a detector at the output of the scroll MUX detects scan 0 of the Counter in Use.

The other condition for generating HOLD REQUEST is at the top of a new scrolling region. This is
necessary because as the CRT beam moves from a nonscrolling region into a scrolling region, it

switches from the last scan of a normally registered line to the first displayed scan of a line that is
scrolling. Assuming the scrolling region is in midscroll, the first scan is not the Oth scan ofthe scrolling
line, so the Counter in Use is not 0. The new scroll zone flip-Top (whose clock input comes from the
scroll flip-flop that controls the scroll MUX) is triggered by entrance into a scrolling region. When the
new scroll zone flip-flop is set, it forcesa HOLD REQUEST ¢'en if the Counter in Use is not also 0. If
the Counter in Use is O (implying an offset of 0 between scroiling and nonscrolling lines) there are two
simultaneous causes for HOLD REQUEST.

4-72

The new scroll zone flip-flop is cleared by ADDR LD that occurs at the end of the Hold Request
generated by the new scroll zone flip-flop. That is, the new scroll zone flip-flop generates HOLD
REQUEST. HOLD REQUEST is cleared either by Terminate or Horizontal Blank, whichever comes
first (the way the VTI100 is programmed, Terminate is always first) and termination of that HOLD
REQUEST feeds back through ADDR LD and clears the new scroll zone flip-flop. More about
HOLD REQUEST follows a discussion of Horizontal Blank and Terminate.

4.6.3.6 Horizontal Blank and Terminate - Horizontal Blank, in addition to blanking the video output,
clears the terminate flip-flop and also generates an internal timing signal (horizontal time reference)
for clocking counters.

A short signal, that occurs on every horizontal scan and lasts only a few character times, is needed in
the chip to clock flip-flops and to disable the decoder gates that detect boundaries and generate HOLD
REQUESTS while the counters settle. Horizontal Blank cannot be used for this purpose because
HOLD REQUEST and Boundary Detect (and other signals) need to be settled well before Horizontal
Blank ends. The required short signal comes from a small counter triggered by Horizontal Blank and
further clocked by character clock. The counter has two outputs: a two-character clock wide signal
that enables and disables the boundary detect flip-flop (that drives the scroll flip-flop) and a threecharacter clock wide signal (H CLK) that enables the Hold Request gate. Boundary detect is enabled
earlier than the HOLD REQUEST gate so that the existence of scrolling can set up the new scroll zone
flip-flop before HOLD REQUEST is enabled. A gate combines the output of the new scroll zone flipflop and the output of the boundary detector (Counter in Use = 0). The output of that gate is combined with H CLK (three character clocks long following Horizontal Blank) to generate the rising edge
of HOLD REQUEST three character times after the rising edge of Horizontal Blank, and is also
combined with the signal from the terminate flip-flop to end HOLD REQUEST when a terminator is
detected.
‘
If Terminate did not cut off HOLD REQUEST, then HOLD REQUEST would be disabled by the
next falling edge of the H CLK signal, but the VT 100 is programmed to always end HOLD REQUEST
with Terminate. If the VT 100 was not working right, HOLD REQUEST might be ended by Horizon-

tal Blank.
Terminate causes a number of functions inside the DCO012. The Terminate input is not direct; it is

sampled on each rising edge of character clock and latched into a flip-flop. When detected, it ends any
HOLD REQUEST in progress. In normal screen mode, it blanks the video output, but in reverse
screen mode it forces the video output to the dim intensity level. The terminate flip-flop output feeds
back to its own input, so that as soon as the flip-flop is clocked with Terminate asserted, the flip-flop
latches itself up.
Once the terminate flip-flop is latched up by feedback from its output, there is only one way to clear it:

through the asynchronous clear input. The flip-flop must not be cleared until Horizontal Blank has
taken over blanking the video output; therefore the clear is delayed slightly (by one character time after

the onset of Horizontal Blank). The clear is maintained until just before the character clock which
corresponds to the first character on the screen because data on the video data bus may be undefined
and might contain extraneous Terminates. These must not be detected during the horizontal blanking
interval because they would latch up the terminate flip-flop for an entire scan. However, the internal
signal that blanks the video outputs of the DCO012 during the horizontal blanking interval cannot be
used to clear the flip-flop directly because it must release the video output at the exact beginning of the
first character on the screen, and the terminate flip-flop must be capable of detecting the terminator in
the first character position. If the internal blanking signal was used to clear the terminate flip-flop, the
release time of the flip-flop would not be satisfied, and it might miss a terminate in the first character
position (as would be found in SET-UP and the top and bottom fill lines). Therefore the Horizontal
Blank output of the DCO11 is made to end approximately one-half character time before video unblanking to release the clear on the terminate flip-flop. Inside the DCO012, the falling edge of Horizontal Blank H is delayed to the following character clock to provide the correct video blanking.

4-73

4.6.3.7

Double Width and Hold Request - The first occurrence of Terminate or Horizontal Blank at

the end of a DMA normally gates Hold Request off. But in double-width mode, Hold Request is
extended by two character times. This is required because each character appears twice in the external
character latch pipeline. To get the first and second byte of the address ofthe next line correctly placed

with respect to Address Load, the end of Hold Request must be delayed by two character times after
Terminate or Horizontal Blank. This delay occurs either when double width is asserted alone or any

time double height is asserted (because double height implies double width) by combining Hold
Request with a two character time delayed version of Hold Request to give a Hold Request that starts

at the normal time but ends two character times later.
4.6.3.8

Attributes — The attribute section of the DCO012 basically implements Truth Table 4-6-4 which

decides how to interpret various combinations of attribute inputs. A number of different inputs determine attributes applied to each character. There are the four attribute pins: Reverse Video H, Underline L, Bold L, Blink L. But there are internal signals (mostly from the input decoding section) that
affect attributes also: the blink flip-flop (toggled by the input decoder to provide blink timing), the
reverse/normal field flip-flop (set by input decoder), the base attribute flip-flop (set by the input
decoder to select whether the reverse video pin is interpreted as reverse or underline) and the scan
counts (from the output of the double height section, that enable the underline on the correct scan).
These inputs are applied to a combination of gates that feed into a 4-bit latch before controlling the
video outputs. This latch i1s clocked by character clock to change the attributes during the inter-

character space.
Table 4-6-4 defines the following appearance for characters with attributes.
Normal characters appear uninverted at normal intensity by asserting VID OUT 2 whenever VID IN
H is asserted. Bold characters are the same as normal characters except that VID OUT 1 and 2 are

enabled. Reverse characters (exclusive-OR of reverse video and reverse screen) normally have dim
backgrounds with black characters so that the large white spaces have the same impact on the viewer’s
eye as the smaller brighter white areas of normal characters. Bold and reverse asserted together give a
background of normal intensity. Blink applied to nonreverse characters causes them to alternate between their usual intensity and the next lower intensity. (Normal characters vary between normal and
dim intensity. Bold characters vary between bright and normal intensity.) Blink applied to a reverse
character causes that character to alternate between normal and reverse video representations of that
character. Underline causes the ninth scan of a character to be forced to white of the same intensity as
the character for nonreversed characters, and to black for reverse characters.
4.6.3.9 Dot Stretcher — The dot stretcher reduces the video bandwidth required in the monitor (especially in 132 mode) by making the minimum dot width 80 nanoseconds. Wider dots give the CRT time
to reach full intensity before turning off again. This makes vertical lines appear to have the same
intensity as horizontal lines, rather than looking dimmer because of the brightness loss as illustrated in
Figure 4-6-16. The dot stretcher works by delaying the VIDEO IN H signal by one dot time (using a
flip-flop clocked by Dot Clock) and then ORing the undelayed and delayed signals. Figure 4-6-17
shows an example of the dot stretcher’s operation.
4.6.4 Address Counter and Data Structure in RAM
Refer to the print set and to Figure 4-6-20. The address counter (E21, E22, E25, E30) is three pre-

settable 4-bit binary counters cascaded to form 12 bits with an additional flip-flop that provides a 13th
bit of address to the screen RAM. Vertical reset clears the counter to an initial hardwired value of
2000H so that the video processor always begins to process from that location after a vertical reset.
The counter is loaded with a new address at the end of each DMA when the address load signal
appears. The counter counts forward from this address at the character clock rate, using the address
count (ADDR CNT H) signal. ADDR CNT H only occurs during Hold Request; thus, the counter
only counts during the DMA portion of each line. The address is loaded at the end of the DMA scan

4-74

and held until the next DMA begins. The 13th bit is programmed by D4 in the high byte of a DMA
address. The VT 100 firmware programs this bit high to access address 2000H plus the contents of the
12-bit counter. But if D4 were programmed low DMAs would access address 4000H plus the contents

of the 12-bit counter.

Table 4-6-4 Character Attribute Combinations
Attributes

Effect*
Background

Character

Under-

Bold

Blink

Video (VID

Underline

L
L
L

H
H
H

H
H
L

H
L
H

O
O
O

N
N/D
B

X
X
X

B/N

L
L

H
L

L
H

0)
0]

N/D
B

B/N

H
H

H
L

L
H

D/O
N

O/N
O

X
X

N/O

O/B

H
H
H
H

L
L
L
L

H
H
L
L

H
L
H
L

D
D/O
N
N/O

O
O/N
O
O/B

Reverse T

line L

Rev Field H

Rev Vid H

Reverse

L
L
H
H

L
H
L
H

L
H
H
L

INH = 0)

Code in

Beam

Table

Intensity

VID2H

VID1H

Off

Dim

N
B
X

Normal
Bright
Not Applicable

H
H

L
H

INH=1)

Video

* For blinking, outputs are shown as OFF/ON where OFF and ON are the blink flip-flop states.

t Reverse = (reverse field H) XOR (reverse video H)

I Intensity of beam on underline scan

4-75

440 ns—»

BRIGHTNESS LOSS

INPUT

MONITOR

PULSE

RESPONSE

THE MONITOR RISETIME IS TOO SLOW TO REACH MAXIMUM
BRIGHTNESS BEFORE THE SHORT PULSE FALLS

j¢—80 ns————»

BY STRETCHING ALL PULSES TO A MINIMUM

OF TWO DOT TIMES, FULLBRIGHTNESS IS ATTAINED

SIMPLE LOGIC ADDS ONE PULSE TO THE
TRAILING EDGE OF ANY INCOMING PULSE

OUTPUT

onp eun o

e of

INPUT

J
MA-4665

Figure 4-6-16 Dot Stretching

ACTUAL CHARACTER DISPLAYED

CHARACTER AS STORED IN

SCAN

WO NOOP»,WN—

NUMBER

AFTER DOT STRETCHING

CHARACTER GENERATOR ROM

c..o

....

. ..............

. ®-:--- -

00 - .

-0

- .

.............

-.
-0000000.- 00---00

- -0-0000 - - —

........'...........

00
00
- - 000 ‘000000

- 0000000 - - -00-: - -0
.

....................

...........‘...-....

-‘....-...... .......

..... .- -

-0-0000 .

........ @ -

e e

o e

o Q@ ¢

....o-.o.....

........ .o....-..

20 DOTS FOR 2 CHARACTERS
IN 80 COLUMN MODE

MA-4663

Figure 4-6-17 Dot Stretcher Example

4-76

In double-width mode, the address count pulses occur half as often as in normal width. The line buffer
receives the normal number of WRITE LB pulses, however, so each character gets copied into two
adjacent locations in the line buffer.
4.6.5

Address Latch Buffer

Tristatable latches (E26, E33) store the address counter outputs for a character period to increase the
speed of RAM accesses that would otherwise be slowed by the long propagation delay of the counters.
They provide sufficient output power to drive the address bus of the basic terminal controller board
and the AVO if present. The outputs are disabled during the non-DMA period to prevent conflict with
the microprocessor address bus.
4.6.6

Line Buffer
Data arrives at the screen RAM latch (E20) during a DMA cycle and is latched in by the character
clock. During the DMA the tristate buffer (E15) is enabled. Data passes through it to the line buffer
(E11, E17) for storage and to the character generator latch input (E16). The line buffer is a 256 X 8
RAM that can hold one full line of data including the three end bytes. The line buffer is written when
WRITE LB L is asserted in the middle of each character clock period. Its outputs are disabled during
the DMA by the Hold Request signal. During non-DMA operation, the screen RAM latch samples
the 8080 data bus at the character rate but the tristate buffer is off so the 8080 data has no effect.
However, the outputs of the line buffer are enabled and the same data is presented to the character
generator latch as was presented during the previous DMA scan. The address signals for the line buffer
are described in Section 4.6.2.7.
4.6.7

Character Generator
The character generator is a ROM that is addressed by the coded representations of the desired characters stored in the screen RAM. Each code is used as the high 7 bits of the address to a 2K X 8 ROM
(that provides enough storage for 128 characters). (The eighth character bit is the base attribute input
to the DCO12.) The low four address bits are provided by the scan counter in the DCO12. The seven
character bits combine with the 4-bit scan count from the DCO012 to give an 11-bit address to the
ROM. The data stored at each (scan + character) address are 8 bits representing the presence or
absence of dots of light at sequential horizontal positions within that scan. Figure 4-6-18 shows the
patterns supplied in the standard VT100 character generator ROM.

If the alternate character generator ROM and the advanced video option are present, the AVO may
assert ALT CHAR SET L to disable ROM E4 and enable ROM E9 when the alternate character set

attribute is set.

If the AVO is installed without the alternate character ROM, any character cell in which the alternate
set is selected will appear white (black if reverse video). See Appendix A (SCS) for selection of alternate
characters.
If it is necessary to use a different main character set than the one provided in the VT100, but an
alternate character set is not required, the following arrangement may be used.
1.

Cut jumper W1 to disable the main ROM.

Plug a new main ROM into the alternate character ROM socket.

_The new main ROM must be programmed exactly as the alternate ROM described in Sec-

tion 6.5.1 except that the chip select on pin 18 must be programmed for high assertion.
To use a UV erasable PROM in the socket for E9 (which must have Intel 2716 pinouts), cut jumper W4
and insert jumper WS to put +5 volts on pin 21. Only later VT100s have these jumpers. The access
time of the ROM must be less than 300 ns to guarantee operation in 132 column mode.

4-77

ot! %»

!
i

i
!

!
_

I| Ol!

I
i

!
!

{
i

!
!

* |
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S

!
1

%
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i
i

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i

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i

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1

1
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1 2

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Figure 4-6-18 Character Generator ROM Patterns (Sheet 1 of 2)

- —
e + o e + e ———— + -+ ——————
——— e + —_————————— + m—————————— + —————————— + ——————
2
2%

!
'
!

4-78

3
2

*
*

——————— — —+ ———————e+ —_— — — — —+ e— — — — —+ — — — — — -+ — — — — — + ,———————-+ r— — — — —
e* =

llllllllll+ o ——————— - —————————— —————————— t—m————————— +————————— e — m—————————— ——————————
»

—

dmwmmmm

MA-4927

80
=

—Sav.wSom—ne

* 2 »*

126

127
pommmmeot

> 3% Ev3

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— — — ———— — T T— 6 E

—wm—
—

%s3

c—A——— S g— — e—

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a——T———o————— —.————

—

MA-4928

Figure 4-6-18 Character Generator ROM Patterns (Sheet 2 of 2)

4-79

4.6.8 Video Shift Register
When VSR LD H is asserted, seven of the eight output bits from the character generator ROM are

latched into the shift register and one is latched into a flip-flop (Figure 4-6-4). At the same time, the
last bit shifted out by the video shift register (VSR) during the previous character time is latched into

the first bit position in the VSR. The VSR is continuously clocked by the dot clock. The first bit shifted
out in the new character time is the same value as the last bit of the previous character, providing
horizontal continuity of characters from one character cell to the next. The seven new bits are then

shifted out.
Meanwhile, the flip-flop that stored the eighth bit has delivered that bit to the serial input of the shift
register. This bit was shifted into each successive register position as the first eight bits were shifted out.
Now the shifting continues, for one more bit in 132 mode, and for two more bits in 80 mode, causing
the last bits shifted out to be the value that was stored in the flip-flop.
VSR LD H then latches the next character into the VSR and flip-flop, with that last, multiply-shifted

bit in the first position. In this way, one bit from the character ROM defines the two or three dots
between characters, while seven bits define the character itself.
At the end of the scan, horizontal blanking forces the flip-flop output low. Since blanking lasts more
than one character time, the low level will be shifted to the first position before the start of the next
line. This ensures that the first dot on the next scan will be at the screen background level.
4.6.9

Terminator
The 7 bits of each character address in a line go to an 8-input terminator detector gate as they are

passed to the character generator ROM. Only seven bits are examined because the eighth bit is an
attribute and does not contribute to the uniqueness of a character. The last bytes in each line are a

terminator character and two address bytes. Only the terminator character activates the gate. During
the character time when the terminator reaches the detector gate, the first address byte is at the input to
the character generator latch and the second address byte is at the input to the screen RAM latch. On

the next character clock, the terminator causes the DCO012 to blank the display and end the Hold
Request. The latch outputs now contain the two address bytes. The low order byte is at the inputs to
counters E30 and E25, while the low four bits of the high byte are at E21. The fifth bit is at the input to
flip-flop E22. This bit is normally high; it allows future development of screen RAM size. The high
three bits go to the line attribute inputs to the DCO012.

The address load (ADDR LD L) pulse, timed to arrive before the next character clock after the
terminator, loads the address counters, flip-flop, and DCO12 inputs with the two final bytes. The
counters and flip-flop designate the address of the first character of the next line to be displayed.
4.6.10

DMA Cycle Timing Diagram

Figure 4-6-19 shows the complex timing in the video processor during the first scan of each new line of
characters. The entire scan is shown, with the repeating portion compressed into the area represented
by dashed lines. The diagram is for 80 columns, single width display as the VT100 is currently programmed. Diagrams in the DCO11 timing chip description (Section 4.6.2) show the differences in
signals in other modes.

The first line shows the Character Clock. This continuous signal is the time reference for all DMA
events.

The terminator occurs at the end of the previous scan. TERM L goes low for one character clock and

then goes to an unspecified state which depends on the random characters that appear at the terminator detector gate. Character Clock continues to shift data through the character latches but invalid
data are present in the character latches and stored in the line buffer until just after DMA ENA is

4-80

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4-81

asserted. The terminator forces the video output to black or white (depending on normal or reverse
screen) effectively blanking the end of the line (Section 4.6.11). It also ends any DMA process in
progress. The terminator’s blanking effect is taken over by Horizontal Blank, and the terminate flipflop in the DCO12 is held cleared until just before the first character in the next scan. This prevents

undefined data from triggering the flip-flop and blanking the whole scan.
Horizontal Blank occurs 3 characters after Terminate in 80 column mode and 5 characters after in 132
column mode. It forces all video to black (regardless of normal or reverse screen) for the horizontal
retrace interval. The Horizontal Blank signal, as an output from the DCOI11, ends one-half character
before the video actually needs to unblank. This early transition releases the clear for the terminate
flip-flop in the DCO12. The blank signal is resynchronized to Character Clock in the DCO012.
Hold Request silences the microprocessor so that the video processor can DMA data out of the screen
RAM. It is initiated when the scan counter in use is equal to 0, or at the setting of the new scroll zone
flip-flop. The terminate flip-flop must be cleared for Hold Request to occur. The start of Hold Request
is delayed by three character times from Horizontal Blank to allow the counter in use to settle before
the 0-boundary is detected. Hold Request is ended by the detection of terminate at the end of a DMA
scan.

DMA Enable is generated from Hold Request and the microprocessor’s hold acknowledge (HLDA)
by discrete logic on the board (E22). It is enabled by the first rising edge of LBA4 if HLDA from the
8080 is available. This ensures that the 8080 has given up the bus before DMA ENA H enables the
DMA address counters onto the bus and drives MEM R low. DMA ENA H is cleared by the end of
HOLD REQUEST H. While the use of LBA4 ensures that enough time has elapsed from the start of
HOLD REQUEST H to guarantee that the 8080 is in its hold state, the use of HLDA H on the D input
of the DMA Enable flip-flop is required to prevent HOLD REQ from preventing a power-up cycle in
the 8080.

The character latch data bus is shown to be tristated from the start of Hold Request until the start of
DMA Enable. Then it starts moving data through the video circuits.
Address Count begins three character times before the end of Horizontal Blank (Section 4.6.2.4).
Address Load is triggered by the falling edge of HOLD REQUEST H. It stores the line attributes for
the next line and loads the address counters with the pointer address bytes at the end of the DMA line
of characters. This address is the location of the first character of the next line to be DMA’d.
Write Line Buffer L is described in Section 4.6.2.3.

Figure 4-6-20 is an expansion of the DMA timing showing the contents of the various storage devices
at different times at the beginning of the active display of a scan.
4.6.11

Video Blanking

The display is blanked by Horizontal Blank during the horizontal retrace interval, and by Vertical
Blank during the vertical retrace interval. These hardware signals ensure that the CRT beam is turned
off while it moves backward through the active screen area. Horizontal Blank controls the video signal
inside the DCO012. Vertical Blank controls the video signal at the video output circuit. Figure 4-6-21

shows a frame of video divided into segments of one horizontal and vertical movement of the electron
beam over the CRT face with respect to time. Figure 4-6-21 plots the screen and its invisible regions by
relating the screen area to the state of blanking at any given time. The top-left corner represents the
first visible dot position. The terminator position is the place where no data is displayed but Horizontal Blank has not yet taken effect. Horizontal Blank then takes effect all through the horizontal retrace
period and unblanks just in time for the first dot of the next scan. After 240 scans, Vertical Blank turns
off the beam while the beam returns to the top of the screen.
4-82

enaracten ceook [

LU
LT U

TERMINATE L

:HORIZONTALBL;NK L—I—
|

‘__3CHARS—j’SYNCHED TO

HORIZONTAL BLANK H

V¥

|
|

| END OF CHARACTER IN DCO12 |
-

]

HOLD REQUEST H
DMA ENABLE H

1
|

|
I

Yy
|

ADDRESS LOAD L

AT E15 OUTPUT

)

VALID DATA AVAILABLE

ADDRESS COUNT

' l'
-

ar
Uy

L
---U
UWUL—LP—U-—LFH:J

WRITE LINE BUFFER—U—L’—LI'_L,_

DATA AT E16 OUT

DATA LOADED INTO VSR

*=UNDEFINED

CHAR1|CHAR1CHARI1|ICHAR2|CHAR3|CHARA4

CHAR1CHAR1CHAR1ICHAR2|CHAR3

HORIZONTAL BLANK BLANK|BLANK|BLANK|BLANK|BLANK

DISPLAYED DATA

‘

CHAR1CHAR2|CHAR3
MA-4669

Figure 4-6-20 Character Latch Timing

The horizontal blanking signal is timed to provide 83 columns of unblanking in 80 column mode, and
137 columns of unblanking in 132 column mode. The VT 100 is currently programmed so that the three

or five extra columns are blanked by Terminate. In normal screen mode, this termination forces the
beam to black, but in reverse screen, termination forces the beam to the screen background intensity.
This means that in reverse screen mode, the last character that can fit on the screen is three or five
characters in from the right edge of the illuminated screen. Because hardware blanking allows 83 or
137 columns on the screen, future program developments may allow the microprocessor to format the
screen RAM for this ability. The main adjustment is to the position of the terminator and address
bytes relative to the starting location of the line. Terminate, as the first character in the line, creates
short lines during the vertical blanking interval to conserve memory while maintaining synchronization of the line address system.
4.6.12 Video Input and Output
Refer to the print set for the circuits discussed in the next three sections.

4.6.12.1 Direct Drive Video - The two video outputs from the DC012, Video Out 1 and Video Out 2,
are combined with Vertical Blank in two open collector nand gates (E7). The outputs of the open
collector gates are wire-ANDed with Graphic 1 and 2 IN (E29) from any option board that may be
present. The combined outputs of E7 and E29 pass through and either float the base of Q4 to +12 V
through R38, R39, and R36 or R37, or pull Q4’s base down to some value determined by one, the
other, or both resistors R36 and R37 in parallel. These four conditions represent the four levels of
intensity visible on the screen: black, dim, normal, and bright.

4-83

3 CHAR TIMES (80 COL)

5 CHAR TIMES (132 COL)
TERMINATOR
——— HORIZONTAL

—»

HORIZONTAL

TIME

RETRACE

TIME

VERTICAL
TIME

DISPLAY TIME

%/ERTK:/{{/%/

BLANKED BY

VERTICAL

éRETRACE
TIME

BLANK

700000
SHADED AREA: BLANKING BY

e BLANKED

TERMINATOR

BY
HORIZONTAL

BLANK
MA-4285

Figure 4-6-21 Video Blanking

4.6.12.2 Composite Video Out - The combined outputs of E7 and E29 control the voltage at Q2’s base
through R31, R32, and R33 in the same manner as described above. At the same time, composite sync
controls Q2’s base through R33 and R30. The result is a 75 ohm output from the terminal controller

consisting of four intensity levels (including black) and composite sync. This signal can directly drive a
standard video monitor or sync can be extracted to synchronize an external device for input to the
terminal. The output is dc coupled. Although the use of dc coupling is not in strict agreement with EIA
specification RS-170, this presents no problem with most monitors because they are usually ac
coupled. See Figure 3-4 for an illustration of the composite video output.
4.6.12.3 Video In - The video input stage terminates a standard video signal in 75 ohms. R43 and D7
bias QS5 into linear operation, while C16 passes video around the bias network. R44 suppresses oscillation in the stage and D6 protects the transistor from a reversed polarity input. D5 biases the base

of Q3 and R41 is the load resistor for the amplifier. R42 stabilizes the amplifier by emitter feedback.
The video input affects only the picture on the internal monitor as described below; it does not appear
at the Composite Video output.
4.6.13

Intensity Control

The video input and output circuits can produce a range of voltages (as compared with circuits that
can produce only two values, white or black levels for example). To do this they are biased into linear

4-84

operating conditions. High current biasing provides the necessary high speed operation. Because of the
high power dissipation that results, the video circuits use discrete transistors.

Direct Drive Video is the output from the terminal controller to the video monitor’s cathode driver
transistor. It is a combination of Video Out 1 and 2 signals from the video processor, and by means of
a parallel transistor Q3, the signal from the video input (labelled Graphics Video In on schematic sheet
BV4). The monitor already receives horizontal and vertical deflection signals directly from the terminal controller, so the terminal’s video input only requires picture information. If the blanking level on
the video input is greater than zero volts, the screen background intensity cannot be black. Note that
composite sync on the input is also ignored by the terminal controller, because the terminal’s timing is
produced entirely by a crystal and cannot be synchronized to external signals. As explained in Chapter
3, external sources may be synchronized with the composite sync signal that appears at the output jack.
Q3 and Q4, in parallel, are one amplifier with common emitter and collector resistors. The emitter
feedback resistor is R40, connected to +12 volts. The collector load is the input impedance of the
monitor to ground in parallel with R54 and any one of 32 parallel combinations of R49, 50, 51, 52, and
53. This arrangement allows either transistor to set the minimum current through the collector and
emitter resistors with the voltage that appears on its base. The other transistor then cannot reduce the
current by being turned off. It can increase the current, however, if it receives a larger base voltage.
Thus the output is always proportional to the greater of the two inputs. Two identical input signals do
not add up because of the common emitter resistor. If the voltage on Q3’s base is more positive than
the voltage on Q4’s base, a voltage at the base of Q4 causes a 0.6 volt different voltage at R40 (both
emitters), and current to maintain that value will flow through Q4 and R40 (as well as the collector
load). If the same voltage as at Q4’s base is applied to Q3’s base, the voltage at the emitters will not
change due to the identical voltage drops across the two base-emitter junctions. There i1s no current
change and so the output remains constant. D8 and R48 provide an extra 0.6 volts of bias for the
cathode drive transistor in the monitor. C17 bypasses the diode for video signals.
The 32 combinations of resistors in the collector load of the output stage are produced by connecting
any of the selected resistors to ground through an open-collector buffer. The buffer inputs come from
the D/A (digital to analog) latch. This latch is written into as an 1/O device by the microprocessor. In
SET-UP mode, the microprocessor uses the up and down cursor keys as inputs to a 5-bit software updown counter. At each vertical reset, the microprocessor writes the current contents of the counter into
the latch. Thus there are 32 possible intensity levels available, controlled from the keyboard, and
frequently updated to minimize the effects of soft errors. Note that the variable intensity only applies
to the internal monitor.

4.7 MICROPROCESSOR - VIDEO PROCESSOR INTERFACE
The microprocessor communicates with the video processor in the following ways.

During setup, the microprocessor reads the setup specifications and writes them into the

The contents of the screen RAM directly control the display of the lines and characters. This
region of memory contains the displayable characters, their attributes, the line attributes,
and the addresses that link one line to the next. The microprocessor modifies and updates
this information in the intervals between DMAs. During each DMA, the video processor
copies one line of characters from the screen RAM for display on the screen.

During smooth scrolling, the microprocessor updates the scroll latch in the DCO012.

DCO011 and DCO012 to establish screen attributes.

This section describes the processes of control through the screen RAM and scrolling. The meaning
and mechanism of the line and character attribute bits and the DMA process are discussed in the video
processor section. The setup process is discussed in the 8080 section.

4-85

4.7.1 Screen Memory Organization
Three bytes of control data are located at the end of each line of characters (Figures 4-7-1 and 4-7-2).
The first byte, called the terminator, is 7FH and is a unique character that the video processor recognizes as the end of the line. (The high bit is not tested by the terminator gate but is set to zero to avoid

complications in the attribute circuits.) Five bits of the next byte and all of the last byte are an address
83
p———

DATA

{T]AlA]

80 CHARACTER SINGLE WIDTH

STARTING LOCATION
-—

135

. DATA

(TlalA]

132 CHARACTER SINGLE WIDTH

DATA

[T{ala]

sBLank

[T][A[A]

40 CHARACTER

DOUBLE WIDTH

DATA

COPIED FROM END OF LINE

| T]A]A]

BLANK

135

[T{A]A]

66 CHARACTER DOUBLE WIDTH

Figure 4-7-1 Line Organization

—ermiNaTOR | HIGH ADDRESS
BYTE

D7D6D5 A A A A Al[A A A AAA A A
)
Li

(7FH, 177Q)

I REGION
SCROLLING

PART OF SCROLLING REGION
NOT PART OF REGION

D6 Db
NORMAL LINE 80/132
1
1
1
O
0O

0
1

BYTE

=
1
O

——

LOW ADDR sl

1=200H+

0=4000H +

DOUBLE HEIGHT
DOUBLE WIDTH

ADDRESS (INPUT TO ADDRESS

COUNTER AT END OF DMA)

THREE HARDWIRED BITS ARE ADDED TO THE THIRTEEN
VARIABLE BITS. WHEN THE ADDRESS COUNTER CLEARS
AT VERTICAL RESET, IT POINTS TO THE START OF RAM.

ALL LINE ATTRIBUTES APPLY TO THE LINE
STARTING AT THE GIVEN ADDRESS.

DOUBLE WIDTH 40/66
TOPHALF,DOUBLE HEIGHT
BOTTOM HALF, DOUBLE HEIGHT

MA-4664

Figure 4-7-2 Terminator and Address Bytes

4-86

pointing to the first character of the next line to be displayed. The three remaining bits in the first byte
define the line attributes of the line pointed to by the address. The high bits of the address are hardwired at the address latch so that when vertical reset clears the address counter, it will point to the
ROM-RAM boundary at 2000H.

During power-up or reset the microprocessor writes terminators and addresses into the screen RAM
according to the specified line length and refresh rate. The 50/60 Hz refresh choice causes the microprocessor to arrange fill lines to place the beginning of the display in the right time slot relative to the
vertical reset and vertical blanking signals. The line length determines the locations of the control

bytes. For 80 column lines, the memory space is arranged in 83 byte intervals; for 132 columns, the
interval 1s 135.
The memory organization for 80 column, 60 Hz mode is shown in Figure 4-7-3. Location 2000H is the

start of the RAM space. When Vertical Reset resets the DMA address counter in the video processor
to zero, the counter latch points to this location. The first 18 bytes are fill lines. Byte 2 is the only one
written differently when 50 Hz refresh is selected. The change causes a longer fill time during the longer
vertical blanking interval.

About 700 bytes of RAM are reserved for the microprocessor stack, scratchpad, and setup areas. The
rest of the 3K RAM is devoted to screen information. At program start, the microprocessor reads the
contents of the NVR into the setup area (Section 4.7.11). Then the microprocessor reads the setup
parameters, erases the screen area and writes in terminator and address/attribute bytes at the selected
line length intervals. The address at the end of each line points to the first location of the next line. At
start-up, this is the next physical location. The end of the last line points to a fill line which points to
itself. The fill line repeats until vertical reset.
4.7.2

Fill Line Operation
The video processor clock is constant so it always takes the same amount of time to refresh the screen.
At any refresh rate there are some fill lines needed at the beginning of the frame so the data can be
displayed starting a few lines down from the top edge of the picture tube. At the slower refresh rate, the
video processor must idle for awhile between frames. Figure 4-7-4 illustrates the vertical position of the
electron beam in the CRT as a function of time for the two refresh rates. The beam sweeps down the
display area at the same rate for both refresh rates but because 50 Hz has a longer interval between
sweeps, the beam travels farther off the ends of the display. While the beam is off screen, fill lines
maintain synchronization in the video processor address system. More fill lines are needed at the top
and bottom of a 50 Hz screen than a 60 Hz screen. Figures 4-7-5 and 4-7-6 show the top-of-screen fill
line operation for both refresh rates. Starting at location 2000H, the terminator-address triplets point
successively to one another and then to the first displayable line of data in the screen RAM. The
change of one byte in the group changes the fill line delay from two lines for the 60 Hz refresh rate to
five lines for the 50 Hz refresh rate. Figure 4-7-7 shows how the single bottom fill line repeats itself as
many times as needed until vertical reset stops it and clears the address counter to 2000H.

4-87

0123456789 ABCDEF
300
01

4-K X4

2D
2E

ATTRIBUTE
RAM

30
31

BF
(010)

FF
MA-4268

Figure 4-7-3 Screen RAM Organization - 80 Column, 60 Hz
(Sheet 1 of 2)

4.7.3 Line Organization
In 132 column mode 25 lines are set up in the RAM for a 24 line screen, and 15 lines are set up for a 14
line screen. With the advanced video option, 25 lines are set up for either 80 or 132 column lines.
Except during a smooth scroll, only 24 lines are seen. But the microprocessor keeps the 25th line erased
in reserve, and when a scroll takes place, the 25th line becomes visible as the new top or bottom line
(depending on scroll direction). All new characters after the command that caused the scroll go into
this line. In preparation for a full screen scroll up, the microprocessor writes the address of the repeating fill line into the 25th line pointer as well as the 24th line pointer. This saves processing time during
the address rearranging which is a part of each scroll.

The line organization changes when the first scroll occurs. Pointer addresses are revised any time a line
is added to or removed from the screen. The extra line is used whenever the screen needs to be scrolled

up or down. Then the extra line is displayed and the old top or bottom line is scrolled off screen,

erased, and made available as the new 25th line.

To understand the pattern of address changes, consider the display to consist of two parallel entities: a
physical screen and a logical screen.

4-88

09 for
50 Hz

O1\23456789ABCDEF
200 7F| 70 [03) 7¢|F2|D0]7F |70 06| 7F| 70| 06 |7F |70 |OF | 7F

01 70[03

3K
X 8

;

STACK

SCRATCH

SETUP AREA

TiA

I[N

FlolR

PAD

Fli1|R]s|T

L
NOTE: ADDRESSES ARE

TYPICAL BUT MAY VARY

30
31

7F|F3|23|D Al T |A
N|D

Flo|R

s|lelclo

[NI|E

SCREEN
RAM

EIN]D
BF

O|F

LiAals|T

N | E|7F| 70|06

ADVANCED VIDEO

1K X 8

SCREEN RAM

FF
MA-4273

Figure 4-7-3 Screen RAM Organization - 80 Column, 60 Hz

(Sheet 2 of 2)

4-89

—— — — —TOP

POSITION

ON SCREEN

20 SCANS

e
—
—BOTTOM

e— (2 LINES) FILL

VERT _&

—{

le———

ACTIVE SCREEN TIME———

[&—
2 SCANS

FilL

RESET

VERT
RESET

60 HERTZ FRAME TIME

<— —-TOP

BEAM
POSITION

ON SCREEN

L1 s scANS BOTTOM

?50 EICNAE'\S Feel

ACTIVE SCREEN TIME ————

25
SCANS
(2.5LINES) FILL

50 HERTZ FRAME TIME

VERT

RESET

MA-4281

Figure 4-7-4 Need for Fill Lines

STARTING
ADDRESS AFTER
VERT RESET
ADDRESS POINTS

HARD-

HERE

WIRED
0

7 IF TOP LINE NOT IN SCROLLING REGION

~°‘-

< T

oR7FY 70 | 03 R7FJ®2 [ po R7F
Y 70 | 06 R7FY 70[ oc R7FY 70 [ oF N7F:
1]

0
o

A 1

2ol

[ 03

]

)
.

TWO FILL LINES
AT TOP OF SCREEN

CROSSHATCHED
BYTE = TERMINATOR

60 HERTZ FILL LINE OPERATION

Figure 4-7-5 Fill Line Operation - 60 Hz

4-90

MA-4360

STARTING
ADDRESS AFTER
VERT RESET

CHANGE FROM 3TO 9
FOR 50 HERTZ

HARD-

WIRED

00 N7FY 70
0

s 4a

7 IF TOP LINE NOT IN SCROLLING REGION

o@Ez‘gfi@z[ DO Eifi\\j 70 ] 06 &‘fi\fi 70 [oc E{F\fi 70 I OF E{F\fl
N~—

|
[
[
[

FIVE FILL LINES AT TOP OF SCREEN

b AT
Al

CROSSHATCHED BYTE = TERMINATOR
MA-4357

Figure 4-7-6 Fill Line Operation - 50 Hz

STARTING ADDRESS
AFTER VERT RESET
HARD-

WIRED

0 o N7FY 70
1L70

[ NG

03 N7y F2 [ oo R7F 70 | 06 N7FY

{

70 | oc N7Fy 70 | oF R7F

‘

FILL LINE REPEATS UNTIL VERTICAL RESET

|
1
D

EREN
-

END OF SCREEN
CROSSHATCHED

)

| 7¢ | 70 | o6 |

BYTE = TERMINATOR
MA-4358

Figure 4-7-7 End Of Screen Fill Line Operation

491

4.7.3.1

Physical Screen - The physical screen is the memory organization already described. The key

feature of the physical screen is the pointer address, contained in each line, that causes the hardware to
chain the lines into a sequence for display. After a series of split screen scrolls, the physical screen will
contain some arbitrary sequence of line addresses.
For example, if the original order of lines was 1,2,3,...23,24, the new order might be 16,13,24,...1,8.

With only this organization,

a command to insert a line at the fifth position on the screen would

require the microprocessor to follow the various pointers around the RAM until it reached the fourth

such pointer in order to learn where the physical address of the current fifth line was in the RAM.
Instead, a list of locations is maintained in the logical screen.
4.7.3.2

Logical Screen — The logical screen is a 25-entry table that points the microprocessor to the
proper locations for shuffling (rearranging) line addresses and placing the cursor in the screen RAM.
The table is set up in a contiguous area of memory starting at the location named LATOFS (Line
Address Offset Table). Figure 4-7-8 shows LATOFS after at least one split screen scroll and in the
process of another split screen scroll. Each entry in LATOFS is the number of a line in the physical

screen. The position of an entry in LATOFS refers to the position of a line on the screen. The micro-

processor updates LATOFS just before each scroll so that the microprocessor can rewrite line addresses during the vertical interval. The microprocessor reads the table to learn which line in RAM is
available for writing as the new 25th line or which line is being used at a given position on the screen.
For example, to insert a character in the fifth line, if the fifth entry in LATOFS is “20,” the microprocessor calculates the starting address of the 20th physical line in RAM. The character address can
be calculated from that starting address and the cursor position within the line.
4.7.4

Address Shuffling
Consider the case of a full screen upward jump scroll. The line in LATOFS #25 is the extra line, not
seen except during smooth scrolls. When a line is jump-scrolled off the screen, it becomes the extra
line, and the RAM area that was line 25 becomes the new last line. The scrolled-off line is erased and
its first location 1s noted as the starting point for new data entry into the RAM. The physical screen
addresses that chain in which the displayed lines must be revised. And since the last fill line must point
to the new first line, which formerly was the second line, the revisions must be done before that last fill
line is DMA’d into the video processor.
When a line feed is received, four numbers are stored in memory. These are Shuffle Address I and 2
(SHUFAD) and Shuffle Data 1 and 2 (SHUFDT). SHUFAD contains the location of the address that
must be changed, and SHUFDT contains the new address that will be inserted there. The two sets are
for the pointer above the line that will be scrolled off, and for the pointer on the end ofthe line that will

be the new next-to-last line (Figure 4-7-9).

The process of changing the addresses is called shuffling because most of the computation is done in
advance. The change is made quickly in a simple point-swap-point-swap sequence. One other item
prepared in advance is the pointer on the 25th (to become the new last) line. The pointer on the present
last line is copied onto the new line. The shuffling process takes less than 550 microseconds (the time
between DM As). The screen’s apparent jump up or down is entirely the result of the revision of pointer
addresses. If, for example, the shuffle occurs during the 15th line, no effect will be visible until the end
of the frame, when the extra line is pointed to but is outside the viewable area. After vertical reset,
however, the shuffled address at the top of the screen will point to the old second line. The first line is
gone, and now there is room on the screen for the extra line and it appears.

4-92

LAT OFS

SCROLLING

REGION

23 25 @«

l
|

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

(EXTRA) #25

25
20

¢
MA-4305

Figure 4-7-8 Line Address Offset Table

4-93

SHUFAD 1

B |—]
{

| FiLL2 PNTR]

’

FLL2 | 1]

SHUFDT 1

[une2
o

EFORE
|

|snurrLe

NTR = LOCATION
OF POINTER ADDRESS

{

AFTER
SHUFFLE

[ LINE 1

L2 l——l

SHUFAD 2

N
|

| LINE 24 PNTR]

SHUFDT 2

LINE 24

FN
[——

| extra

AFTER SHUFFLE

BEFORE

SHUFFLE

| ExTRA LINE

]

[

" Fen | N

FN |
T WRITTEN BEFORE SHUFFLE
MA-4294

Figure 4-7-9 Full Screen Address Shuffling

4.7.5

Shuffle Timing

The shuffles for smooth and split screen scrolls must be synchronous with vertical reset to avoid
disrupting the appearance of the display. Therefore, only one line feed can be executed during a frame.
However, in the case of full screen jump-scrolling, the address shuffle may occur at any time. This
increases the rate at which line feeds can be executed and improves the terminal’s throughput.
While full screen jump scrolling may occur at any time relative to vertical reset, the two other kinds of
scroll are sensitive to the time when shuffling occurs. If a split screen scroll region (say 10 lines in the
middle of the screen) is revised while the display is scanning that region, only the change at the bottom
of the region would take effect during that frame. The extra line would appear at the bottom of the
region and the following lines on the screen would be pushed down one line from their locations in the
previous and succeeding frames. The appearance would be that of a flash of mixed-up data below the
scrolling region. Therefore, all changes are made during the vertical interval, ensuring that the proper
number of lines is consistently displayed because the video procesor cannot ever attempt to execute
only part of a shuffle sequence.

Logically the screen still flashes in full screen scrolling, but because the extra last line is displayed
beyond the end of the screen, Vertical Blank blanks the display. The shuffle is a two part process, with
the two address bytes transferred in separate operations. If the shuffle is not complete before the DMA
that accesses the shuffled address starts, the address that gets read may not be valid, and garbage may
be displayed thereafter. The random start of the shuffle process relative to the video processor’s DMA
timing causes this error.

4-94

4.7.6

Scrolling Region
A scrolling region may be established on the screen, on a horizontal line basis, within which data may
be inserted or lines scrolled without affecting the positions of data outside the region. Only one region
may be defined at a time, but it may be repeatedly redefined. Full screen scrolling is a special case in
which the region margins and the screen margins are the same. A control sequence defines the region

by specifying the line numbers of the top and bottom of the region. When the control sequence arrives,
the microprocessor stops taking characters from the silo and waits for the current scroll to end. It then
checks the parameters for legality (top less than bottom, bottom less than 14 or 24). If they are bad, the
sequence 1s ignored and the next character is taken from the silo. If they are good, they are stored in
locations labelled Top and Bottom. Then starting at the pointer address on the last fill line, the microprocessor sets the fill line’s scroll attribute bit to scroll or noscroll (depending on the specification for
top margin) and jumps to the end of the addressed line, setting its scroll attribute bit. The microprocessor continues down through the screen RAM until it reaches the point to line #Top, the line that
will be at the top of the scrolling region. It sets the attribute bit there to scroll. Jumping down through

the region, the microprocessor continues setting line attributes to scroll until it reaches line #Bottom,
the bottom line in the scrolling region. From there to the end of the screen it sets the bit to noscroll.
4.7.7 Split Screen Jump Scrolling
When a line feed is received, during the remainder of the current frame the microprocessor rotates
LATOEFS and prepares for the shuffle. The line number at LATOFS #25 (25 in Figure 4-7-10) moves
up to the bottom position in the scrolling region (LATOEFS #8). The line at LATOFS #5 (20) moves to
LATOFS #25, and all the other lines in the scrolling region of LATOFS are moved up one position.
The shuffle buffers are set up. (See Figure 4-7-10.) SHUFAD 1 contains the location of the pointer
address at the end of the last line before the scrolling region and SHUFDT 1 contains the pointer
address for the new first scrolling region line. SHUFAD 2 contains the location of the pointer address
at the end of the new last scrolling region line and SHUFDT 2 contains the pointer address for the first
line after the scrolling region.

While the LATOFS and shuffle preparations are underway, data may be coming into the terminal.
Data received after the line feed stay in the silo until the LATOFS rotation is completed. Just before
rotation, LATOFS 25 points to the number of the next RAM line that data should go to. The microprocessor records that location and then performs the rotation and shuffle preparation. Then it resumes writing the data into the line previously noted. When vertical interrupt occurs, the shuffle is
performed and the new line is displayed. If no new line feed is received, data will continue to be written
into the same line.
4.7.8 Smooth Scroll
Become familiar with the operation of the scan counter as described in the video processor section
(4.6.3.3) before studying this description.

In smooth scroll operation, the VT100 changes the positions of the lines on the screen slowly, so the
eye can follow and read the data as it goes by. Instead of moving one character height or 10 scan lines
in a single frame, the data moves up or down one scan line in each frame. The smooth scroll rate is thus
6 lines per second at 60 Hz frame rate. Operation is the same for full or split screen smooth scroll. For
any given line feed, the effect on the screen is delayed by two frames. Line feeds may queue up so that
scrolling is continuous.

Smooth scroll is enabled by a bit in the setup memory that causes the microprocessor to perform all
scrolls as smooth scrolls. Whenever a line’s scroll attribute bit is set, it receives its scan count from the
offset counter. At vertical reset, the scan counter, used for nonscrolling lines, always resets to zero, but
the offset counter is loaded with the contents of the scroll latch. The microprocessor loads the scroll
latch with an offset value. If a jump scroll is involved, the offset is always zero. If a smooth scroll is
involved, the microprocessor loads an offset value according to the number of frames that have passed
since the line began moving.

4-95

LINE 4

SHUFAD 1

\
BEFORE

LINE 5

SHUFFLE

INE6

OF POINTER ADDRESS

[UNEG

L7
-

SHUFFLE

LINE 8

]
2
SHUFAD

B “~

BEFORE

y
LINE 9

L10

EXTRA LINE

SHUFFLE

LINE 8 PNTR

sHyUFDT2
EXTRA

$WRITTEN BEFORE

AFTER

SHUFFLE

SHUFDT1

PNTR = LOCATION

AFTER

LINE 4PNTR]

LE
SHUFF

SCROLLING REGION IS LINES 9-15. AT SHUFFLE, LINE 9
DISAPPEARS, REGION MOVES UP, EXTRA LINE APPEARS
TO FILL SPACE BETWEEN LINES 15 AND 16.

MA-4662

Figure 4-7-10 Split Screen Address Shuffle

When a line feed is received the microprocessor waits for the current scroll to end. It sets an internal
scroll-pending flag. Then, at the next vertical interrupt, during the frame before scrolling begins, the
shuffling process makes its preparations but only to add the 25th line to the display. During smooth

scrolling, all the lines will be visible together. The microprocessor, which keeps count of the number of
frames in the scroll, loads the scroll latch in the DCO12 with an offset value of one. Then, when the
second vertical interrupt occurs, the microprocessor performs the address shuffle, the offset counter
receives the 1 from the scroll latch, and the microprocessor loads the scroll latch with 2. As the frame
begins, the character generator ROM, driven by the offset counter, displays its second scan row on the
top line of the scrolling region. The rest of the scrolling region is moved up by the same amount, so the
last scan in the scrolling region is the top scan of the 25th line.

Succeeding frames contain the data moved up scan by scan as the microprocessor loads the scroll latch
with larger offset values each time. During the ninth such frame, only one scan from the top line and
nine scans of the bottom line are visible. The microprocessor loads 0 into the scroll latch. If the

4-96

microprocessor made no other change, then on the next frame, the data which had been moving slowly
up would jump back down to its original position. Therefore, another address shuffle is performed at
vertical reset. The top line of the scroll region is discarded and the 0 offset applies to the former second
line. The old top line is erased and becomes the new 25th line that will appear in the next scroll.
4.7.9 Split Screen Smooth Scrolling
In a split screen smooth scroll, the scan count to the character generator ROM must switch between

the normal scan counter and the offset counter. (Please remember that full screen scroll is a special case
scrolling region, and that jump scrolling is a special case offset count of 0.) The scrolling attribute bits,
which were set when the control sequence that defined the region arrived, operate the counter multiplexer (MUX).
Refer to Figure 4-7-11 and suppose that the smooth scrolling region extends from line 5 to line 8. The
scroll is shown at its midpoint. The scrolling attribute bits at the ends of lines “Fill” through three
define lines one through four to be outside the scrolling region. Each line’s DMA has occurred when
the scan counter, which always starts together with the top scan on the screen, is equal to zero. A
DMA always occurs:
1.
2.

when the counter in use (MUX output) is zero, or
when the MUX first selects the offset counter.

The offset counter is loaded with its offset at vertical reset. The switch between scan counter and offset
counter may only occur when the scan counter (NOT the MUX output) is zero.

SCAN

OFFSET

COUNTER

IN USE

O —m 5§

0 ——— 5

0 —— 5

SEAD AT END OF DMA

UNE1

UNE2

LNE3 —]

IVI

LINE 4
LINES

LINE 6

LINE 7

O —— 5

V W X

LINES

LINE25

0
0

0 ——— 5

(FILL)

SCROLLING ATTRIBUTE

Neg
|

—

Jlfl

AT NEXT SCAN COUNTER

O BOUNDARY, WILL SWITCH

11 r-— TO OFFSET COUNTER

T Je— COUNTER STARTS AT 5.

+—
1

(1]

SWITCH TO OFFSET

COUNTER CAUSES DMA.

NEXT DMA AT O.

{1
.
0 le— SWITCH OUT OF OFFSET
|~

COUNTER AT NEXT

[5]

O BOUNDARY. COUNTER

{—

DMA.

NE 10 ]

SCAN COUNTER

INUSE=0, THEREFORE

MA-4282

Figure 4-7-11 Split Screen Smooth Scroll at Midpoint

4-97

The scrolling attribute bit on line 4 enters the DC012 during the DMA. However, it does not cause the
MUX to switch until scan O of the next line. Because of the switch to the offset counter, line 5 begins
with a DMA but it starts displaying with scan 5 because of the offset counter. Its attribute bit enters

the DCO12 at the end of the DMA. Five scans later the counter in use is 0, so another DMA occurs.
Because the scan counter did not reach 0 before the DMA, the scrolling attribute bit from line 5 is
ignored. Line 6 DMASs and its attribute bit enters the DCO12. Line 6 is present for all 10 scans and so

as the scan counter passes through zero, the DC012 accepts control from the line 6 attribute bit.
This special case (pointer to the second line in the scrolling region while the smooth scroll is in progress) is the only occasion when an attribute bit is ignored. The double height and width bits in the same
byte are accepted at the moment the DMA for the corresponding line begins.

As line 5 begins to roll off the screen, the extra line in memory, line 25, becomes visible. It becomes the
new line 8 when line 5 is gone. Line 25 carries a non-scroll attribute bit because the next line (which the
address on line 25 points to) is not in the scrolling region. Line 25 was DMA’d in when the counter in
use was 0 so it starts with its top scan. But the attribute bit is accepted when the scan counter reaches 0
five scans later. Now the counter in use is 0 again because of the shift back to the scan counter so
another DMA occurs, bringing in line 9, which also carries a non-scroll attribute bit. The rest of the
screen thus appears in non-scroll fashion.
4.7.10 Cursor
The microprocessor keeps a running account of the cursor position. It starts at the reset position, line 1

— column 1 (top left corner) and responds to any change in position that might result from receiving a
new character, a cursor position command, a line feed, etc. The microprocessor calculates the appropriate screen RAM address from the combination of previous line and column plus change in position,
or from the specified line and column in a direct cursor address (DCA) control sequence. The microprocessor then records the current setting of the base attribute bit of the character at that address and
then periodically inverts the attribute bit, showing the operator that the cursor is located at the spot on
the screen where the attribute appears and disappears.
When a line scrolls on the screen, its location in RAM remains the same. To keep the cursor at the

same screen location as before, representing the cursor moving down through the lines, the microprocessor calculates a new address for the cursor at the same column number but in the RAM location
corresponding to the next line. Then, after resetting the attribute at the old location to its original
value, it records and then toggles the attribute bit at the new location.
The attribute bit that the microprocessor toggles and the appearance on the screen depend on the setup
selection of the cursor attribute and on the absence or presence of the AVO. If the AVO is not installed, the microprocessor toggles the eighth bit in each character word. A setup selection of reverse
video causes the microprocessor to set the DCO012 to interpret its base attribute input (REV VID H) as
reverse video. If setup specifies that underline is to be used for the cursor, the DCO12 is set to interpret
the base attribute as underline instead of reverse. Notice that without the AVO the cursor selection

determines the appearance for all characters on the screen that have the attribute asserted. Furthermore, the microprocessor will accept the commands for either reverse or underline to assert the attribute.

With the AVO present, the microprocessor tells the DC012 to interpret the base attribute as reverse
video. The cursor selection in setup determines whether the microprocessor toggles the base attribute

bit (eighth character bit) to get reverse video or one of the bits in the AVO RAM to get underline. With
the AVO present, cursor selection is independent of attributes and all attributes are available at the
same time,

4-98

4.7.11

SET-UP

The SET-UP area is a portion of the scratch RAM. It contains 8-bit bytes that are passed between the
RAM and the NVR. Here is a list of the SET-UP area contents. This list is subject to change.
22 bytes
17 bytes
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte

1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte

Answerback message (20 characters and 2 delimiters)
Tabs encoded in bits
80/132 column mode
Intensity
Mode byte for PUSART
On-Line/Local
Switchpack 1 (scroll, autorepeat, screen, cursor)
Switchpack 2 (bell, keyclick, ANSI/VTS52, XON/XOFF)
Switchpack 3 (US/UK #, wrap, new line, interlace)
Switchpack 4 (parity sense, parity, bits/char, power)
Switchpack 5 (STP - visible only when option installed)
Transmit baud rate
Receive baud rate
Parity
Checksum for NVR

When the SET-UP key is pressed, the SILO locks and any scroll in progress is allowed to finish. Now
the 25th line (Extra) is available for one of the lines at the bottom of the screen. Another 135 bytes are
available as line Extra2 for use as the other of the two bottom lines, or for the NVR buffer area and the
“Wait” message displayed during NVR operations. Another 125 bytes are the SET-UP screen RAM.
They store the words “SET-UP A twice (for double height) and the words “To exit press SET-UP”
with the three lines’ terminator and address bytes, plus 19 more terminators and addresses for the 19
blank lines in the middle of the SET-UP screen.
For SET-UP A, the microprocessor performs a routine to fill the line at the bottom of the screen with a
ruler. The other free line displays the cursor and letters ““T” to indicate tab positions. Then the microprocessor counts from the beginning of the tab bytes in the SET-UP area to find the bit corresponding
to the column number where the cursor is. If the bit is set, the microprocessor writes the letter “T” in
the current cursor position. Keys (Set/Clear Tab, Clear All Tabs) on the keyboard can toggle the
setting of the bit in the SET-UP area, and the microprocessor writes or erases the *“T” to agree.
For SET-UP B, the microprocessor displays the data contained in the switchpack and baud rate area
by writing corresponding information into the bottom line. Switchpack 5 is only displayed if the
Option Present flag is asserted at the STP. The other free line is not written into but is used to display
the cursor position and to display the answerback message when the message is being entered. The
switchpack data is changed by a key on the keyboard (Toggle 1/0).
The non-switchpack data is changed by separate keys. These include parameters that display themselves - line/local (displayed in the LEDs) and 80/132 column, seen on the screen. Transmit and
receive are displayed numerically as is parity in later models. Switching between SET-UP fields and

starting Reset can also be done with separate keys on the keyboard.
4.8

MONITOR
Two monitors have been used in VT 100 prodection. Early VT100s used DEC part number 30-14590.
Later terminals used DEC part number 30-16080. Most of the circuitry in these monitors is standard
television technique, and this description simply highlights the signal path. An overview of the general
principles of the horizontal section is included because this circuit is not intuitively understandable
from an examination of the schematic. It is also the likely candidate for failure because of high stresses
in the components.

4-99

4.8.1

Monitor Description: 30-16080 (Elston)

4.8.1.1

Video Driver - The cathode driver stage gets its operating supply of 38 volts from a winding of

the flyback transformer. R108 is the collector load resistor.
C101 bypasses the emitter resistor to
improve high frequency response. The stage is intended to be biased by the driving circuit (direct video
out in the terminal controller). R1035 couples the video signal to the cathode limiting current flow if the
CRT arcs.
4.8.1.2

Brightness — The brightness control circuit gets its ~150 volt operating supply from the horizontal output circuit. A charge pump (C104, C105, CR103, CR104) produces a large negative voltage
by inverting the large positive swings in the stage. The brightness voltage returns to the +38 volt video

output power supply, rather than ground, to allow the brightness control output to vary from -42 to
+17 volts. The brightness control potentiometer R109 varies the bias on the first grid of the CRT.
C107 bypasses currents resulting from internal CRT arcs from the high voltage anode and also by-

passes video signals from the grid to ground.
4.8.1.3

Vertical Oscillator - The vertical oscillator receives its synchronizing drive through inverter-

buffer Q298. R331 and C314 are a low pass filter on the input for noise immunity. The input is accoupled so that if the drive stops in either a high or low state, the circuit can self-oscillate to keep the
beam moving on the CRT.
Basically, the oscillator is an RC timer with R333 and R334 through CR304 charging a capacitor made
of C318 and C319 in series. As the voltage across the capacitor rises, emitter follower Q309 drives the
output amplifier Q310 so that its collector current rises at the same rate. CR304 is two diode drops to
compensate for the drops in Darlington Q309 so the voltage at the base of Q310 is the same as the
voltage at the top of C318. When Q308 receives a vertical drive pulse, it discharges the capacitor.
R341 and R342 are positive feedback to the junction of C318 and C319. As Q310’s emitter voltage rises
with increasing current, the two resistors couple that voltage back to the timing capacitor. This makes

the voltage across the capacitor rise faster than it would with only the charging current from R333 and
R334. But because the rise in capacitor voltage causes Q310 to turn on more, the feedback voltage
increases as well. The exponential rise in Q310’s output current that results closely matches the variations in L301’s current. This is explained more under Linearization (Paragraph 4.8.1.6).

4.8.1.4 Self-Oscillation - If the vertical circuit does not receive a drive signal, it oscillates by itself to
keep the electron beam moving to prevent a phosphor burn. The self-oscillation period is longer than
the period between vertical drive pulses so the drive pulses, when present, always control the vertical
scanning rate.
Without a drive signal, Q308 is off. The regular RC circuit produces a rising voltage at the base of
Q310. While Q310’s output moves the electron beam, its base voltage is coupled to Q308 through R335
and CR302. When the voltage rises above the diode drops of CR302 and Q308 base-emitter junction,
Q308 turns on, discharging the timer and cutting off Q310. The retrace voltage that forms at L301 is
coupled by R344, C316, and R339 back to Q308 to keep it on long enough to complete a retrace even
though the voltage from Q310’s base (that started the cycle) has started to decrease. After the voltage

at L301 falls (due to current flow to the yoke), the drive to Q308 is gone, Q308 turns off, and the selfoscillation cycle begins again.

4.8.1.5

Vertical Output - Consider L301, which is a large inductor, to be a constant current source.

Assume that the yoke starts with a current that deflects the beam to the top of the screen, and Q310 is
off. The current flows out of L301 through C321 and into the yoke. Q310 now turns on with a gradually rising voltage on its base. Q310 thus draws an increasing amount of current from the junction of
L.301 and the yoke. Because L301’s current is relatively constant, this means that less current is avail-

4-100

able for the yoke, so as Q310’s current increases, the yoke’s current decreases. Eventually Q310 passes

all of L301’s current and the yoke current is O with the beam in the center of the screen. As the current
in the collector of Q310 increases further, the current in the yoke reverses and adds to the current
coming from L301. This opposite current deflects the beam toward the bottom of the screen. Now the
vertical drive pulse turns Q310 off, and L301 produces a large positive voltage to try to maintain its
constant current. This voltage rapidly reverses the current in the yoke and makes the beam return to
the top of the screen very fast. Q310 turns back on and the cycle repeats.

C320, R338, and R340 limit the voltage across L301 during vertical retrace.
4.8.1.6

Linearization - Because L301 is not an infinitely large inductor, it is not a perfect current

source. Current through it decreases gradually until the beam reaches the center of the screen and then
increases again toward the end of the cycle. This non-ramp component of the current would cause
character height to vary from top to bottom if allowed to pass to the yoke. The exponential drive to
Q310 as a result of feedback causes Q310 to accept the varying current from L301 at the same time that
a ramp current through the yoke is maintained.
4.8.1.7

Horizontal Driver — The horizontal driver receives a TTL level drive pulse from the terminal

controller. R468 limits the base current to Q413. C435 provides noise immunity for the drive input.
When the input is high, Q413 is on. With pin 6 of transformer T403 pulled low by Q413, and with

about half the supply voltage at pin 4, there is approximately 6 volts across the primary winding 4-6.
The secondary winding 3-2 sees one quarter of this voltage across itself due to the 4:1 turns ratio, but
no current flows because Q414’s base-emitter junction is reverse biased. Meanwhile, current increases

through winding 4-6 while Q413 is on, storing energy in T403’s core. When the drive signal falls,
turning Q413 off, winding 3-2 reverses polarity. Current now flows from T403 winding 3-2 through
Q414’s base-emitter junction, Q414 saturates, and the horizontal output functions as discussed below.
When the drive signal goes high again at the beginning of horizontal retrace, Q414 needs to turn off
very quickly to minimize dissipation. The purpose of opposite polarities in T403 is to force Q414 off by
turning Q413 on. When Q413 turns on, winding 3-2 reverses polarity again and this voltage forces
Q414’s base-emitter junction into a reverse biased state, rapidly discharging Q414’s stored base charge

and cutting off Q414’s collector current.
R470 limits the peak current through Q413. R470, and R471 (if present), limit the on time of Q414.
C443 (if present) speeds up the turn-off of Q414. C436 limits the peak voltage that develops across
Q413 caused by leakage inductance in the primary of T403 that prevents complete coupling of the
primary energy into the secondary. C437 filters Q413’s power supply.

4.8.1.8 Horizontal Deflection Operation — The horizontal output circuit consists basically of Q414,
CR406, C438, C441, and the horizontal deflection yoke. Assume that the beam is at the center of the
screen during a scan. Refer to the waveform diagram (Figure 4-8-5) for reference points TO through T4.

4-101

Figure 4-8-1 Horizontal Deflection Current - TO

'/-\

VOKE

Q414

+15

TC441
TO
MA-4670

TO:

Right Half of Scan (Figure 4-8-1)

Initial Condition:

Current through the yoke is zero. C441 is charged to + 15 volts. Q414 is on.

Action:

Current now flows out of the yoke through Q414, pushed by the voltage across
C441. The voltage across C441 is nearly constant so the current through the
yoke’s inductance increases linearly. As the current increases, the beam moves
to the right of the screen. The magnetic field building in the yoke stores energy.

Figure 4-8-2 Horizontal Deflection Current - T1

l '/-\
/[ C438

YOKE

T1
MA-4671

T1:

Start of Retrace (Figure 4-8-2)

Initial Condition:

Current out of the yoke is maximum. Q414 is switched off. C438, which had

Action:

Current continues to flow out of the yoke by inductive inertia as the stored mag-

been grounded by Q414, has 0 volts across it.

netic field collapses. C438, which is a small valued capacitor, quickly charges
to a high voltage. This voltage opposes current flow and causes a rapid reduction in current. The beam quickly returns to the center of the screen.

Figure 4-8-3 Horizontal Deflection Current - T2

q YOKE
+1757= C438
12

MA-4672

T2:

Middle of Retract (Figure 4-8-3)

Initial Condition:

Current through yoke is zero. C438 is charged to + 175 volts.

Action:

The high voltage across C438 causes a rapid rise in current into the yoke. The
beam moves to the left of the screen.

4-102

Figure 4-8-4 Horizontal Deflection Current — T3

/’“\\

YOKE
+15

]\ Ca41

CR406

T3
MA-4292

T3:

Start of Scan (Left Half) (Figure 4-8-4)

Initial Condition:

Current into the yoke is maximum. C438 is discharged.

Action:

Inductive inertia makes the top of the yoke slightly negative, forward biasing
CR406 to provide a return path for current out of the bottom of C441. The yoke

current gradually decreases as the magnetic field collapses and discharges into
C441 against the voltage across C441. The beam moves to the center of the
screen.

T4:

Return to TO

4.8.1.9 Horizontal Output Circuit — (Refer to Figure 4-8-5.) L403 adds a variable inductive reactance
that controls current in the circuit to vary the scan width. L402 is a magnetically biased inductor whose
reactance varies nonlinearly with changes in yoke current. This, with R481 and C442, provides correction for nonlinearity caused by the decaying exponential rate of current increase in the yoke caused by
the yoke’s resistance. It does this by allowing more voltage across the yoke at the end of the scan. This
is needed because as current increases, the voltage drop increases across the resistance of the yoke,
tending to reduce the rate of current increase.

CURRENT
«—— THROUGH

YOKE

<+—
(0 AMPS

—7

«——0VOLTS

VOLTAGE

ACROSS

—

YOKE

T3
T2

T1{

T2
MA-4930

Figure 4-8-5 Horizontal Deflection Waveforms

4-103

Power enters the circuit through the primary of the flyback transformer. CR408 and C439 work with
an autotransformer winding on the primary to boost the stage’s operating voltage to + 15 volts. The

output circuit shuttles yokvbe current back and forth between C438 and C441, losing only a small
amount of power in resistive losses. Therefore, the average current through the flyback primary is small
(approximately 800 mA). C438 is relatively small so that the voltage drop across its reactance can provide “S” correction for the horizontal scan. This compensates for the difference between the arc of the
tube face and the arc of the beam’s deflection. Each time Q414 turns off, a 175 volt pulse, lasting the
interval of horizontal retrace, appears at the dotted end of the flyback primary. This pulse passes into
the flyback secondary to provide high voltages for the CRT.

4.8.1.10 High Voltage and Focus — When the 175 volt pulse appears on the flyback primary at retrace,
the flyback secondary produces 12 kV which is rectified by CR407 and filtered by the capacitor made
by the aquadag (graphite) coatings on the inside and outside of the CRT’s glass envelope. Screen and
focus grid voltages of about 370 volts come from a lower voltage winding on the flyback and are rectified by CR409. For the cathode driver, 38 volts comes from another winding and is rectified by CR102.

4.8.2

Monitor Description: 30-14590 (Ball)

4.8.2.1
Video Amplifier - The video amplifier consists of Q101 and its associated circuitry. The incoming video signal is applied to the monitor through J101-8 and R101 to the base of Q101.
Transistor Q101 has a nominal gain of 15, and operates as a class B amplifier. Q101 remains cut off
until a dc-coupled, positive-going signal arrives at its base and turns it on. R103 provides series feedback that makes the terminal to terminal voltage gain relatively independent of transistor parameters
and temperature variations. R102 and C101 provide emitter peaking to extend the bandwidth to 12
MHz.
The negative-going signal at the collector of Q101 is direct coupled to the CRT cathode. The class B

biasing of Q101 allows a large video output signal to modulate the CRT’s cathode and results in a
maximum available contrast ratio.
Overall brightness of the CRT screen is also determined by the negative potential at its grid which is
varied by the brightness control.
4.8.2.2 Vertical Deflection - Q102 is a thyristor used as a programmable unijunction transistor and
with its external circuitry forms a relaxation oscillator operating at a vertical rate. The sawtooth
forming network consists of A101, C103, and C104. These capacitors charge exponentially until the
voltage at the anode of Q102 exceeds its gate voltage at which time Q102 becomes essentially a closed
switch, allowing a rapid discharge through L101. The rate of charge or frequency is adjustable by
A101. The oscillator is synchronized by a negative pulse coupled to its gate from the vertical drive
pulse applied externally at J101-9.

A divider network internal to A101 sets the free running frequency by establishing a reference voltage
at the gate. This programs the firing of Q102 and amounts to resistive selection of the intrinsic standoff
ratio. Frequency is controlled by passive components only. CR101 provides temperature com-

pensation for Q102 while controlling the gate impedance to allow easy turn on and off of Q102. L101
forms a tuned circuit with C103 and C104 during conduction of Q102 which provides a stable control
on the dropout time of Q102 to assist in maintaining interlace. Q103 collector to base forward diode
clamping action prevents the voltage from swinging too far negative during this flywheel action.

4-104

The sawtooth at the anode of Q102 is direct coupled to the base of Q103. This stage functions as a
Darlington pair emitter follower driver for the output stage Q104. It presents an extremely high impedance in shunt with A101 and prevents the Beta dependent input impedance of Q104 from affecting the
frequency of the sawtooth forming network.
Linearity control of the sawtooth is accomplished by coupling the output at Q103 emitter resistively
back into the junction of C103 and C104. This provides integration of the sawtooth and inserts a
parabolic component. The slope change of the sawtooth at Q103 output is controlled by the setting of
A102. The output at Q103 is coupled into a resistive divider.
Height control R110 varies the amplitude of the sawtooth voltage applied to the base of Q104 and
controls the vertical raster size on the CRT. C105 limits the amplitude of the flyback pulse at Q104
collector.

The vertical output stage Q104 uses an NPN power transistor operating as a class AB amplifier. The
output is capacitively coupled to the yoke. L1 provides a dc connection to B+ for Q104. It has a high
impedance compared to the yoke inductance that causes most of the sawtooth current of Q104 to
appear in the yoke. R114 prevents oscillations by providing damping across the vertical yoke coils.

4.8.2.3

Horizontal Deflection

4.8.2.3.1

Low Level Stages - The purpose of Q105 and Q106 is basically to process the incoming
horizontal drive signal into a form suitable to drive the output stage Q108. The duty cycle of Q108
becomes essentially independent of the amplitude and pulse width of the drive pulse. This is a necessary condition to assure stability and reliability in the output stage. In addition, these stages provide a
horizontal video centering adjustment by delaying retrace with respect to the horizontal drive pulse.

The drive pulse is presented to Q105 via J101-6. The base circuit of Q105 includes a clamp and a
differentiator that makes Q105 output insensitive to drive pulse amplitude and width changes. The
only requirement is that pulse amplitude be of 2.5 volts minimum and pulse width should be 10 to 40
microseconds. Q105 with Q106 functions as a monostable multivibrator with Q107 being a slave that

provides a positive feedback. Specifically, when Q105 is turned on by the drive pulse, it discharges

C112 at a rate determined by the setting of A103. When C112 is discharged to 1.75 volts, Q106 turns
off. This change of state turns Q107 on and the base drive to Q106 from R128 is shunted through
Q107. Q106/Q107 remains in this state for nominally 25 microseconds until C112 recharges through
A103 to 8.25 volts. At this time, Q106 is biased on again by the current through A103. The multivibrator is now in a state in which Q106 is on and Q105/Q107 is off. It remains in this state until the
next drive pulse occurs or power is turned off. C112 is the only timing capacitor in the circuit and has
two time constants associated with it. Primarily, the charge path between pin 1 and pin 3 of A103

determines the on time of Q107. The discharge path through the video centering control and Q105
determines the delay between application of the drive pulse and the start of retrace (turn on of Q107).
4.8.2.3.2

High Level Stages — These stages consist of Q107 driving the output stage, Q108, and its

associated circuitry through T101. Q107 is an inverting slave of Q106 and is driven alternately into
saturation and cutoff as are all stages in the horizontal circuit. Q107 output is transformer coupled to

the output stage with phasing of T101 chosen such that Q108 turns off when Q107 turns on. This
allows Q108 to turn off quickly, thus minimizing dissipation. A careful review shows that Q108 turns
off at a variable delay time after receipt of the drive pulse. This action causes retrace to begin.

4-105

During conduction of the driver transistor, energy is stored in the coupling transformer. The polarity

at the secondary is then phased to keep Q108 cut off. As soon as the primary current of T101 is
interrupted due to the base signal driving Q107 into cutoff, the secondary voltage changes polarity.
Q108 now saturates due to the forward base current flow. This gradually decreases at a rate determined by the transformer inductance and circuit resistance. However, the base current is sufficient to
keep Q108 in saturation until the next polarity change of T101.
The horizontal output stage has two main functions:

to supply the deflection coil with the correct horizontal scanning currents and

to develop high voltage for the CRT anode and dc voltage for the CRT bias, focus, and

accelerating grids, as well as the dc voltage for the video output stage.

Q108 acts as a switch that is turned on or off by the rectangular waveform on the base. When it is
turned on, the supply voltage plus the charge on C123 causes deflection current to increase in a linear
manner and moves the beam from near the center of the screen to the right side. At this time, the
transistor is turned off by a polarity change of T101 that causes the output circuit to oscillate. A high
reactive voltage in the form of a half cycle negative voltage pulse is developed by the deflection coil
inductance and the primary of T2. The peak magnetic energy that was stored in the deflection coil
during scan time is now transferred to C122 and the deflection coil distributed capacity. During this
cycle, the beam is returned to the center of the screen.

The charged capacitances now discharge into the deflection coil and induce a current in a direction
opposite to the current of the previous part of the cycle. The magnetic field thus created around the
coil moves the scanning beam to the left of the screen.
After slightly less than half a cycle, the decreasing voltage across C122 biases the damper diode CR111
into conduction and prevents the flyback pulse from further oscillation. Magnetic energy that was
stored in the deflection coil from the discharge of the distributed capacity is now released to provide
sweep for the left half of scan and to charge C123 through the rectifying action of the damper diode.
The beam is now at the center of the screen. The cycle repeats as soon as the base of Q108 becomes
positive with respect to its emitter.

C123 serves to block dc current from the deflection coil and to provide S’ shaping of the current
waveform. ‘S’ shaping compensates for stretching at the left and right sides of the picture tube because the curvature of the CRT face and the deflected beam do not follow the same arc.

L 103 is an adjustable width control placed in series with the horizontal deflection coils. The variable
inductance allows a greater or lesser amount of deflection current to flow through the horizontal yoke
and varies the width of the horizontal scan.

Linearity control is provided by modifying the deflection coil voltage. During retrace, an auxiliary
winding on the flyback transformer supplies a pulse that charges C119 through rectifier diode CR112
and L102. This voltage is then applied in series with the deflection coil when the damper diode turns on
at the start of trace. The voltage is sawtooth shaped and has the effect of decreasing the deflection coil
current as a function of the sawtooth shape. This compensates for the stretch normally found on the
left side of the screen due to the deflection coil and system RL time constant. Linearity is optimized by
adjustment of L102 that acts as an impedance to the pulse from T2.

The negative flyback pulse developed during horizontal retrace time is rectified by CR110 and filtered
by C117. This produces approximately —130 Vdc which is coupled through the brightness control R117
to G1 of the CRT.

4-106

This same pulse is transformer-coupled to the secondary of T2 where it is rectified by CR2, CR113,

and CR 114 to produce rectified voltages of approximately 12 kV, 400 V, and 32 V respectively. 12 kV
is the anode voltage for the CRT, 32 V is used for the video output stage, and the 400 V source is used
for G2 and G4 voltages for the CRT.
4.9

POWER SUPPLY

The VT100 series power supply is a switching supply that has 95 watts capacity with four separate
voltage outputs. Figure 4-9-1 is a block diagram of the power supply.
4.9.1

Power Input

The input to the supply consists of an electromagnetic interference (EMI) filter, an on/off switch, a
fuse, and a 120/230 volt select switch. Either on 120 Vac or 230 Vac input, thermistors R1 and R50
reduce the start-up inrush currents to safe levels. For 120 Vac operation a voltage doubler rectifier is
used; for 230 Vac operation a full wave bridge rectifier is used. The storage voltage across both C9 and
C14 varies with the input line voltage from 200 to 360 Vdc. R19 and R20 are bleeder resistors.
4.9.2

Start-Up Circuit

Transformer T2 is a start-up transformer that supplies the power to start the control circuit. The ac
voltage on the primary of T2 is stepped down, rectified, and filtered by C33. The dc voltage is applied
to the input of +12 volt regulator Z2. The output passes through two diodes D24 and D25 to the
control circuitry. When the unit is turned on, the only voltage supplying power to the control circuit is
from the regulator Z2. After the outputs come up, the +12 output is fed back through diode D34 to the
control circuitry. This voltage, being higher than that delivered by the start-up circuit, will back bias
D24 and D25, isolating the Z2 regulator. This scheme of returning the output through D34 enables the
power supply to also meet its ride-through specification (ability to supply power during brief outages).

INPUT

RECL;'IFIER
A

SWITCHING

—

TR27NSISTOR

23 VOLT

RECTIFIER-FILTER

400 VOLT

MULTI.

;\-'Lé \é(ég RECTIFIER

AP
AC

ULATOR

30 KHZ

Igfik‘ASER

5 VOLT RECTIFIER-FILTER
AND CURRENT LIMIT SENSE AMP

START-UP

12 VOLT RECTIFIER-SWITCHING-REGULATOR- ]

SUPPLY

FILTER & CURRENT LIMIT SENSE AMP

12 VOLT

SLOW

TURN-ON

CIRCUIT

PULSE
W'DTHl SYNCHRONlZATIONJ
PULSE WIDTH
MODULATOR
1 MODULATOR
E4

E2 & E3

MA-4295

Figure 4-9-1 VT100 Power Supply Block Diagram

4-107

4.9.3

Control Circuit
The control circuit in the VT100 power supply is designed around the 3524 pulse width modulator
(PWM) IC. It houses a voltage reference, error amplifier, oscillator, pulse width modulator, pulse

steering flip-flop, dual alternating output switcher, current limit circuit, and a shutdown circuit. Refer

to the regulator IC block diagram in Figure 4-9-2 and the power supply timing diagram in Figure 4-93.

VREF

REFERENCE
REGULATOR

+5V TO ALL
INTERNAL CIRCUITRY

OSCILLATOR

+5V

RT(6

()

(RAMP)

+5V

OUTPUT

ELIP
L1

‘

NOR

FLOP

OSCILLATOR

-l-

@ Ca

—

/ML

+5V

COMPARATOR \I\

+5V

INV. INPUT @————\

ERROR

CURRENT LIMIT

AMP

N.I. INPUT@

)+ SENSE

@-SE NSE

GROUND

(SUBSTRATE)

@
AN
SHUT DOWN

@ COMPENSATION

$
;I1OK

L
MA-5265

Figure 4-9-2 3524 Regulator Block Diagram

4-108

OSC. OUTPUT
FLIP FLOP OUT

—l

TO NOR 13,14

[

DC LEVEL/‘ L

—1

l--flLjr-A

RAMP —

OUTPUT OF

COMPARATOR
OUTPUT OF

IERS—

NORGATE 13,14

Q13,14 COLL

Q2 BASE

Q2 COLL

FLIP FLOP OQUT

—]

TO NOR 11,12
PIN 2

555
PIN5

5.1V

—

PIN 6,7

PIN3 555 _A—L
coLL Q1

Q7 COLL

CURRENT ]

Q8 Vg _J

MA-4873

Figure 4-9-3 Power Supply Timing Diagram

The oscillator frequency is determined by resistor R18 and C7. The ramp generated by C7 is used as a
reference for the comparator. The discharge time of C7 determines the pulse width of the oscillator
output pulse. This pulse is used as a blanking pulse to ensure that the outputs of the 3524 cannot turn
on simultaneously. Capacitor C5 ensures that the blanking pulse is wide enough.
The error amplifier in the 3524 is a transconductance amplifier with an output (pin 9) impedance of

approximately 5 megohms. Pin 9 is a convenient point to place the compensation network, R30, C17
and R13. It is also an ideal point at which to turn off the switching regulator and also to put the slowturn-on circuit. The slow-turn-on circuit consists of D39, R51, D40, and C34. When the power supply
is initially turned on, pin 9 is pulled to ground by C34 through D39. As C34 charges slowly and
exponentially, pin 9 follows, turning the power supply on slowly and exponentially. The current that
charges C34 comes from pin 9 and the +12 volt start-up. Pin 9 operates at a dc level that is determined
by the input error voltage into the amplifier. C34 eventually charges to +12 volts, thus back biasing
D39. When the supply is turned off, C34 discharges through D40, allowing the supply to be ready for
another soft start.

The inverting side (pin 1) of the input to the error amplifier is tied to the +35 volt output through a
dividing network, R32 and R48. The noninverting side (pin 2) is referenced to a 5.1 volt zener, D38,

through a divider network, R41 and R49. An error appearing at the input causes pin 9 (output of the
error amplifier) to shift. This dc level shift is tied into an input of a comparator. As mentioned earlier,
the ramp generated by C7 is tied into the other input of the comparator. This is the means by which the
regulator is pulse width modulated. The actual frequency of the oscillator is 60 kHz. The switching
frequency of the power supply is one-half that of the oscillator, 30 kHz, because only one of the singleended outputs is used. This output, pin 13, a pulse width modulated wave, turns transistor Q4 on and
off. When Q4 is off, Q3 supplies base current to Q2, turning it on. D7 and D8 are antisaturating

diodes. R14 limits the base drive, and R15 and C4 are a speed-up circuit to turn Q2 on and off fast.

When Q2 is on, Q7 (high voltage switch) is off. Current flows from +12 through R11, D6, and winding
5,6 of pulse transformer T3 through transistor Q2 to ground. The circuit remains in this state until the
base drive to Q2 is removed by the control circuit. When Q2 turns off, the voltage across T3 winding

5,6 reverses, causing all the dotted ends of windings in T3 to become negative. Current starts to flow
into the base of Q7. This causes collector current to flow. This current flows through winding 1,2 of
T1, through the transistor and winding 2,1 of T3. The current in winding 2,1 of T3 produces current
flow in windings 3,4 and 7,8 of T3. The action that takes place is regenerative and causes Q7 to snap
on. When Q7 conducts, energy is transferred from the primary of T1 to the secondary. The positive
voltage at terminal 5 of T1 charges capacitor C6 through D14 and R21. The voltage at terminal 5
depends on the conduction time of the switch. When the control circuit switches Q2 on, C6 discharges
through D9, winding 5,6 of T3 and transistor Q2. The current through winding 5,6 of T3 makes all
dotted ends positive on T3. The negative polarity on the base of Q7 turns it off. D11 is across T3 and
Q2 for noise immunity. Diodes D41, D12, and D3 are antisaturation diodes. C19, R27, and D27 form
the snubbing network.

Winding 1,3 of T1 is a reset winding. On turn-off, this winding clamps the collector of Q7 to two times
the storage voltage. It is also used for resetting the high frequency transformer core.
4.9.4

Outputs

There are four secondary outputs. The -23 volt output is rectified by D28, filtered by C18, and passed
on through a 300 ohm resistor. The output goes to two zeners mounted on the video board. The 300
ohm resistor limits power dissipation in the zeners and also dissipates all power under short circuit
conditions.

4110

The -12 volt output consists of a rectifier diode (D29), filter capacitor (C20), and a regulator Z1.

The voltage at winding 9,10 of T1 is rectified by D36 and goes into an averaging network L2 and C31.
The catch diode, part of D36, completes the conduction path when Q7 is off. When Q7 is on, there is a
voltage on the secondary with pin 9 being positive. D36 is forward biased and current flows through
L2. This causes the inductor current to increase at this time. With the switch open, stored energy in the
inductor forces the current to continue to flow to the load and return through the catch diode (D39).
The voltage across L2 is now reversed and is approximately equal to the output voltage. During this
time the current in L2 decreases. The average current through L2 equals the load current. Since C31
keeps the output voltage constant, the load current will also be constant.
The +12 volt output circuitry works the same way as above except the voltage at winding 4,5 1s turned

on by Q8 and turned off by the voltage at terminal 5 going negative.
The current limit circuits for the +5 and + 12 outputs have identical configurations; only some resis-

tance values differ. The voltage at pin 5 of the comparator referenced to the junction of R16 and R37 is
compared to the voltage drop across R37. When the voltage across R37 increases to a point where pin
6 is more positive than pin 5, E1 switches and pin 7 goes low, pulling pin 9 of E4 to ground and thus
turning off the switching regulator.
The +12 volt control circuitry is synchronized to the 3524 pulse width modulator at a 30 kHz rate.
When pin 12 of E4 is high, capacitor C15 charges up from the +12 start-up through R29, R26, and
D13. The polarity on the capacitor is such that when pin 12 of E4 goes low, the emitter of Q6 is pulled
negative with respect to the base which is at ground. Q6 saturates, pulling pin 2 of E3 down, thereby
allowing the ramp generated at pins 6 and 7 by C13 to ramp up. Pin 6 is the threshold pin. The input to
this pin 1s compared to the voltage at pin 5. When the voltage at pin 6 is equal to that of pin 5, pin 7
discharges capacitor C13 and pin 3 of E3 goes low. Whenever the voltage at pins 6 and 7 is ramping up,
the output of E3, pin 3, is high.
C13 is the timing capacitor for the +12 volt pulse width modulator. C13 is charged from a voltagecontrolled current source. The voltage at pin 5 of E3 is connected to the 5 volt reference. Thus, when
the voltage across C13 reaches 5 volts (pin 6 of E3), the output of E3 pin 3 drops low, turning Q1 off
and thereby turning Q8 on. Q7 and Q8 are turned off simultaneously when Q2 is turned on. The pulse
width that determines the length of time Q8 is on is determined by the rate of voltage rise on capacitor

C13. The faster C13 charges, the longer Q8 conducts. The error voltage that determines the rate of rise
on C13 is generated by error amplifier E2. The noninverting input of the error amplifier is referenced
to D38, a 5.1 volt zener. The inverting input is divided up by R2 and R3 and senses the +12 volt
output. Any difference creates an error signal on pin 6 of E2. This increase or decrease in voltage at pin
6 divided by R33 generates a proportional change in current through Q5, thereby changing the rate of
voltage charge on capacitor C13. As described above, the change in rate of charge affects the pulse
width.
R4, Cl, and R5 are the compensating components of error amplifier E2. D1 and D2 are antisaturating

diodes. R6 limits the base drive and R7 and C3 are a speed-up circuit to turn Q1 on and off.

4-111

4.9.5

Power Supply Specifications

4.9.5.1

Input Specifications

Voltage
Single phase, 2 wire

90-128 V rms (switch-selected)
180-256 V rms

Frequency

47-63 Hz

Current

22Armsmax.@ 115V rms; 1.1 A rms

max. @ 230 V rms.
Input power

250 VA apparent 150 W max.

Power factor

Ratio of input power to apparent power is
greater than 0.6 at full load and minimum
input voltage. The VT100 appears
capacitive to the line.

Leakage current

When installed in VT100 terminal, current
to ground is 0.5 mA max. Each line to
ground at 250 V rms sine, 50 Hz.

Current limiting

When installed in video terminal, 3.0 A
normal blow fuse.

Electrical Magnetic Interference Susceptibility
Single voltage transient without causing
Conducted transients
system degradation: 600 V @ 2.5 W /sec
max.

Single voltage
transient, survival

1000 V@ 2.5 W/sec max.

Average transient power,
survival

0.5 W max.

Conducted cw noise

Unit operates without error at conducted
noise levels up to 10 kHz — 30 MHz: 3 V
rms.

RF Field Susceptibility: 10 kHz — 30 MHz:
2 V/M; 30 MHz — 1 GHz: 5 V/M with power
supply installed in video terminal.
Power line disturbance

4-112

Ride through capability

The VT100 power supply provides a minimum
of 20 ms ride through during a power
outage condition. Ride through capability
is at low line and full load. During this
time, all power supply outputs must be
within their specified limits.

Overvoltages

The VT100 power supply withstands for one
second, an overvoltage of 110% of the
maximum input voltage(s) specified in
Section 4.9.5.1.1 without causing system
degradation or damage.

Undervoltages,
disturbances, and

The VT 100 power supply is capable of
withstanding undervoltage disturbance and
power interruptions without physical
damage.

outages

Hi-Pot

Input to frame for 1 min. — 2.15 kV dc;
input to output for 1 min. — 2.5 kV rms

Output Specifications
General

DC outputs are provided by the dc output
distribution.
DC output specifications are defined at
the dc distribution buses.
Distribution systems must be designed per
this document since no output voltage
adjustments are provided.

Output power

+5V@ 1.5 A minto11.0
A max.
+12V@ 1.0 A min to 2.75 A max.

—12V@ 0.0 A min to 0.5 A max.
—23 V@ 10 mA

+ 5 V Specifications
Total regulation
Static line regulation

Static load regulation
Long term stability
Thermal drift
Ripple
Dynamic load regulation
Noise

+ 5%
+0.75%
+2.0%
0.1% — 1000 hrs
+0.025% - deg C
150 mV p-p for f < 66 kHz
+ 2.2% (see notes)
1% peak at f greater than or equal to 100
kHz (noise is superimposed on ripple)

4-113

+ 12 V Specifications
Total regulation
Static line regulation

Static load regulation
Long term stability
Thermal drift

Ripple
Dynamic load regulation
Noise

+5%
+0.5%
+1.0%
0.1% — 1000 hrs
+0.025% — deg C
240 mV p-p for f < 66 kHz
+ 1.1% (see notes)
1% peak @ f greater than or equal to 100
kHz (noise is superimposed on ripple)

— 12 V Specifications
Total regulation

Static line regulation
Static load regulation
Long term stability
Thermal drift
Ripple
Dynamic load regulation
Noise

+ 5%
+0.5%
+1.0%
0.1% — 1000 hrs
+0.025% — deg C
240 mV p-p for f < 66 kHz
+ 1.1% (see notes)
1% peak @ f greater than or equal to 100
kHz (noise is superimposed on ripple)

— 23 V Specifications
Total regulation

Static line regulation
Ripple

+10%
+ 2%
500 mV p-p

NOTES
1.
For all outputs, the long term stability and thermal drift specifications apply after a 5 minute
minimum warmup, measured at the dc distribution buses with an averaging meter.
2.

Dynamic load regulation is measured in + 25% load steps from a starting point of 75% of full load.
Measurements are made at the power supply terminals.

Zener diodes for —23 V supply are located at the load and not on the power supply.

Regulation limits

Regulation limits are measured at the dc
distribution buses. The root sum squared
of errors due to the following
conditions:

1.
2.
3
4.

5.
6.

Initial tolerance
Static and dynamic input voltage
Gradual load changes over the load
range minimum to full load
Operation over the temperature
environment specified for the VT100
Long term stability per 1000 hours
Ripple and noise must remain within
the total regulation limits stated
above.

4-114

Ripple and noise

Ripple and noise must be measured with a
wide band oscilloscope in the
differential mode between ground and the
output under test. The oscilloscope must
be grounded so as to minimize spurious
responses. The specification applies only
to repetitive voltage variations that
occur while operating with a constant
input voltage and fixed load.

Overload protection

+ 35 V output

Current limit with foldback. Limit point
is 18 A max; foldback is 6.0 A max.

+ 12 V output

Current limit with foldback. Limit point
is 6 A max; foldback is 3 A max.

—12V

Internal current limit of the 3-terminal
regulator is per DEC specifications
PS-19-12048-02.

—23V

Current limited to less than 150 mA.

Voltage adjustments

None. 1.68 kg (3.7 Ibs) max.

4.9.5.2

Cooling - Cooling is by natural convection. Adequate space must be provided around the sup-

ply to allow a free flow of air. The power supply was designed with capability greater than the basic
VTI100 requirements so that options could be casily added in the future. Since the form factor and

power dissipation of these options is not known, additional air flow and thermal profile testing should be
conducted as part of the option design to determine if convection cooling is sufficient.
4.9.5.3 Base Product Power Requirements — The basic VT100 terminal controller, monitor, and keyboard have the following combined maximum power requirements:

+5V
+12V

—12V
—23V

25A
A
1.8
0.03
A
12 mA (no other device should use this voltage).

The advanced video option uses +5 V, 1.1 A maximum power.

4-115

CHAPTER 5

VT100 SERIES SERVICE

S.1

INTRODUCTION

This chapter contains troubleshooting and repair information for VT 100 series terminals. All terminals in the series are based on the VT100. As a result the VT100 can always be isolated as a separate
unit. This allows you to determine if the trouble lies within the VT 100 hardware or the hardware added

to the terminal to make it one of the variations.
5.2
5.2.1

TROUBLESHOOTING
Troubleshooting the VT100 with Self Test

The VT100 contains a series of internal self tests designed to isolate a failure to a field replaceable unit

(FRU). Tables 5-1 and 5-2 show the error codes, the detected failure, and the FRU that should be

replaced.

Table 5-1 Keyboard LED Error Codes
Keyboard LEDs

Error

Replace

FRU

OFF OFF

OFF

ROM 1

Terminal controller

OFF OFF

OFF

ROM 2

Terminal controller

OFF OFF

ROM 3

Terminal controller

OFF ON

OFF

ROM 4

Terminal controller

OFF ON

OFF

Main Data RAM

Terminal controller

Table 5-2 VT100 Display Error Codes

Error Detected
Data

Char.

AVO

w N -

Error

KBD

Loopback

EIA

X
X

®s!

> X

e e

< X

XXk

(O T -8

NVR

> X

5-2

Replace
Advanced video
Terminal controller
Advanced video and
terminal controller
Keyboard
Advanced video and
keyboard
Terminal controller
and keyboard
Advanced video,
terminal and keyboard
Terminal controller
Advanced video and
terminal controller
Terminal controller
Terminal controller
and advanced video
Keyboard and terminal
controller
Advanced video,
keyboard and terminal
controller
Terminal controller
and keyboard
Advanced video,
keyboard and
terminal controller
Terminal controller
Advanced video and
terminal controller
Terminal controller
Advanced video and
terminal controller

Keyboard and terminal
controller
Advanced video,
keyboard and terminal
controller
Keyboard and terminal
controller

Advanced video,

keyboard and terminal
controller
Terminal controller
Advanced video and
terminal controller

Table 5-2 VT100 Display Error Codes (Cont)
Error Detected

KBD

X
X

Replace
Terminal controller
Advanced video and
terminal controller
Keyboard and terminal
controller
Advanced video,
keyboard and terminal

X
X

EIA

oKX

Loopback

NVR

AVO

Char.

Data

Error

controller
Keyboard and terminal
controller
Advanced video,
keyboard and terminal
Controller

5.2.2 Troubleshooting Basic VT100 Variations Without Self Test
Table 5-3 lists the most common VT100 failures and the associated symptoms. To use this table simply
select the symptom that matches the terminal failure.
5.2.3

Troubleshooting the VT105

The troubleshooting procedure for the VT105 consists of two steps: 1) isolate to the base VT100
configuration and troubleshoot the terminal; and 2) perform the internal tests described for the VT 105
in Chapter 6.

To isolate to the base VT 100 disconnect the graphics interface cable from J2 on the VT100 controller

board. Now perform the troubleshooting procedures outlined for the basic VT 100 variations.
To troubleshoot the VT105 graphics module reconnect the graphics interface cable to J2 on the VT100
controller board. Perform the testing procedure outlined in Chapter 6. When performing the test
sequence remember to type the sequence exactly as written. If an error appears retype the sequence to
verify that there is an error and then replace the VT 105 graphics board.
5.2.4

Troubleshooting the VT132

The troubleshooting procedure for the VT132 is the same as the basic VT100. The only difference
between the two machines is the advanced video option (AVO) board. On the VT 132 the AVO board is
standard and contains two (2) ROMs. In addition the ROMs on the video controller board are different. If a spare VT132 video controller board is not available remove the ROMs from the VT100
controller board and substitute the VT132 ROMs. The same is true for the advanced video board. If a
VT132 advanced video board is not available configure the AVO board jumpers or switches and plug
in the VT132 ROMs. Information on board configuration is contained in Paragraph 5.4.

5.2.5 Troubleshooting Options
Troubleshooting terminal options should be performed after the basic terminal is checked and found
to be good. Once this is done, perform the option checkout procedure for the suspected faulty option
as outlined in Chapter 6. If the option does not check out correctly, replace the option module.

5-3

Table 5-3 Basic VT100 Troubleshooting Procedure
General Notes on Using the Procedure

This procedure assumes that only one field replaceable unit (FRU) has failed. Symptoms displayed may be representative of a multiple failure; as a result, symptoms may change as FRUs
are replaced. Always troubleshoot to the current symptoms.

Spare parts do fail. The possibility of a failure should not be discounted
just because the module
has been replaced once.

Power must be turned off before any FRU is disconnected or replaced.

Symptoms

Probable Cause

Corrective Action

No response when
power switch is set

Not plugged in; no
power at wall socket.

wall socket if possible.

to ON. The CRT
filament is not
lit and LEDs are
not lit.

No response when
power switch set
to ON and CRT
filament is lit.

No audible tones
when terminal is
turned on. LEDs
are lit. (Most
usual hard failure
symptoms.)

Plug in VT 100; use different

Main power fuse

Replace fuse (if fuse blows
again there is a possible
shorting problem. Use
appropriate troubleshooting
methods).

Power supply

Replace power supply.

AC line cord

Check for open or short
and replace line cord.

Power distribution
harness

Replace harness.

Power supply

Replace power supply

Terminal controller
board

Replace board

Power distribution

Replace harness

Controller

Replace

Keyboard

Replace

Keyboard cable

Replace

Speaker

Replace

Table 5-3 Basic VT100 Troubleshooting Procedure (Cont)
Symptoms

Probable Cause

Corrective Action

No audible alarms
and indicators
when terminal

Keyboard disconnected

Connect

Keyboard cable

Replace

Keyboard

Replace

Connectors

Check and reconnect

Controller

Replace

Screen brightness
too low

Adjust monitor
brightness

Controller

Replace

Monitor Board

Replace

Flyback transformer

Replace

DC power harness

Replace

F.S. monitor assy

Replace

Monitor fuse open

Replace monitor bd

after the terminal
is powered up.
CRT filament is
lit. Keyboard is
functional.

Monitor Board

Replace

DC power harness

Replace

F.S. monitor assy

Replace

Random characters

Controller

Replace

Monitor connectors

Check and reconnect

Monitor board

Replace

F.S. monitor assy

Replace

turned on and none
of the LEDs are
hit.

Cursor does not
appear on screen

after terminal
powered up.
CRT filament is
lit.

Cursor does not
appear on screen

appear on screen.

Horizontal or

vertical line
appears on
screen.

5-3

Table 5-3 Basic VI100 Troubleshooting Procedure (Cont)

Symptoms

Probable Cause

Corrective Action

Screen display
distorted. Characters

Monitor is
misadjusted

Adjust monitor

Monitor board

Replace

Flyback transformer

Replace

F.S. monitor assy

Replace

Controller

Replace

Ball monitor
misadjusted

Adjust

DC power harness

Check

Controller

Replace

Monitor

Replace

narrow on

left or right side

of screen.

Screen rolling

Display
presentation bows
in or out

Y oke pincushion

Replace F.S. monitor

misadjusted

assy

Display
presentation

Interlace feature

Turn feature off

jumpy

Wrong character
appears on

screen when typed
in LOCAL

Power feature set
incorrectly

Set feature to
correct line
frequency

Controller

Replace

Power supply

Replace

Monitor board

Replace

Flyback transformer

Replace

Graphics or alternate
character set or
alternate keypad
mode or cursor key
mode is selected.

Clear condition with

Keyboard

Replace

Controller

Replace

power up or reset.

5-6

Table 5-3 Basic VT100 Troubleshooting Procedure (Cont)
Symptoms

Probable Cause

Corrective Action

Wrong character

Graphics or alternate
character or alternate
keypad mode or cursor
key mode is selected.

Clear condition with

Transmit and receive
speed not the same.

Change speed setting

Controller

Replace

appear on screen

Receive and/or
transmit speed set

computer.

when typed in

wrong.

appears on

screen when typed
in ON-LINE mode
with loopback
installed.

Terminal functional
in LOCAL mode.

Wrong characters

ON-LINE mode and
connected to
computer. Terminal
is functional with
loopback connector.

Bits per character
feature set

power up or reset.

Set speeds to match

Set feature to match
computer.

incorrectly.
Parity feature set
incorrectly.

Set parity and/or
parity sense feature
to match computer.

Communications line

Check communications
facilities.

Double characters

Local echo set on
full duplex system

Set correct feature

Messages received
are incomplete

XON/XOFF feature set
incorrectly

Set feature

Computer does not
recognize XON /XOFF

See Appendix A

sequence.

Checkerboard
character appears
on screen instead
of character typed
(on-line with
computer).

Controller

Replace

Parity, baud rate,
bits/char set
incorrectly.

computer.

Controller

Replace

Communications
facility problem

Check communications
facility.

Set features to match

Table 5-3 Basic VT100 Troubleshooting Procedume (Cont)

Symptoms

Probable Cause

Corrective Action

All characters
displayed as a

Alternate character
set selected and
not available.

Clear condition with

Only top or bottom

Incorrect use of

See Appendix A.

half of characters
are displayed on
the screen.

double height escape
sequence

SET-UP features
do not work correctly
(multiple alarms
may sound on power
up or recall). Error
“2” displayed on

Save operation not
performed.

Perform Save operation.

Controller

Replace

ANSI/VTS2 feature
set incorrectly.

Set ANSI/VTS2 feature
to correct compatibility.

white area (black

power up or reset.

with reverse
screen).

screen.

Terminal does
not respond to
Escape sequences.

5.2.6 VTI100 Internal Self Tests
The VTI100 contains five self test programs in the basic ROM memory:
Power-up test
Data loopback test
EIA test
Video adjust pattern

SET-UP screen test

Each test is designed to isolate a failure to the faulty module so that the terminal may be repaired in a
minimum amount of time.

5.2.6.1

Power-Up Test — The power-up self test performs the following tests:

Reads the contents of each ROM chip, calculates a checksum, and then compares the checksum to the checksum stored in each ROM chip.

Writes a 1 and a 0 in each bit location of RAM on the basic terminal controller board to
verify that the RAM can store each bit.

Writes a 1 and a 0 in each bit location of RAM on the advanced video option (AVO) board

to verify that the optional RAM can store each bit. If the AVO board is not present this part
of the test is skipped.

5-8

Reads the contents of the Nonvolatile RAM (NVR), calculates a checksum, and then com-

pares the checksum to the checksum stored in the NVR.

Turns the keyboard LEDs on and off, rings the keyboard bell for one-quarter second, and
looks for the end-of-scan character from the keyboard to determine if the keyboard is functioning properly.
The power-up test may be started in any one of the following ways:
l.

Turn the terminal power on.
or

Type the following sequence to perform the test once. The terminal must be in ANSI-compatible mode (in SET-UP B group 2 switch 3 equals a 1).
ESC [2;1y
or

Type the following sequence to perform the test continuously. The terminal must be in
ANSI-compatible mode (in SET-UP B, group 2 switch 3 equals a 1).

ESC [2;9y
or

Reset the terminal.

NOTE
The continuously running test ends only if an error is
found or power is turned off.
Any error found by the power-up self test is displayed on the terminal screen and/or LEDs L1 through
L4 on the keyboard. Tables 5-4 and 5-5 provide the meanings for the error codes.

Table 5-4 LED Error Codes
Error

ROM 1 checksum error
ROM 2 checksum error
ROM 3 checksum error
ROM 4 checksum error
Main data RAM error

off
off
off
off
off

off
off
off
on
on

off
on
on
off
off

on
off
on
off
on

5-9

Table 5-§

Displayed Error Codes

Display | Fault Detected

Char

AVO | NVYR|

]

B
X

6
7

8
9

;

<
=

AVO | NVR | KBD | Data|

4
5

Display | Fault Detected

KBD | Data | EIA | Char

O -

EIA
X

X
X

Note: See Table 1-2 to determine the correct module to replace.

5.2.6.2 Data Loopback Test - In the data loopback test the VT 100 transmit and receive lines VT 100
are connected to each other via a special external connector. A predefined set of characters are then
transmitted. The terminal receives the characters and compares them to the characters transmitted.
The test repeats at all baud rates. If the characters do not match an error is then flagged.

Use the following procedure to perform the data loopback test.
1.

Install the appropriate data loopback connector. Connector part number 12-15336 is for
EIA communications; connector part number 70-15503-00 is for 20 mA current loop communications.

Place the terminal in ANSI-compatible mode (in SET-UP B group 2 switch 3 equals a 1).

Place the terminal in LOCAL mode.

Type the following sequence to perform the test.
ESC [2;2y
or

Type the following sequence to perform the test continuously.
ESC [2;10y

5-10

NOTE

The continuously running test ends only if an error is
found or the power is turned off.

Any error found by the data loopback self test is displayed on the terminal screen. Table 5-5 provides
the meanings of the error codes.

5.2.6.3 EIA Test - The EIA test checks that the following signals can be set to a 1 or a 0: Data
Terminal Ready, Data Set Ready, Request to Send, Clear To Send, Carrier Detect, Ring Indicator,
Speed Select, and Speed Indicator.
Use the following procedure to perform the EIA test.
1.

Install the EIA data loopback connector, part number 12-15336.

Place the terminal in ANSI-compatible mode (in SET-UP B group 2 switch 3 equals a 1).

Place the terminal in ON-LINE mode.

Type the following sequence to perform the test once.
ESC [2;4y
or

type the following sequence to perform the test continuously.
ESC [2;12y
NOTE
The continuously running test ends only if an error is

found or power is turned off.

Any error found by the EIA self test is displayed on the terminal screen. Table 5-5 provides the
meanings of the error codes.
5.2.6.4 Video Adjust Test — The video adjust test provides a screen full of “Es’’ for display height,
width, and linearity adjustments. The test pattern is internal to the terminal and is not sent to the host
computer.

Use the following procedure to display the test pattern.
1.

Place the terminal in ANSI-compatible mode (in SET-UP B group 2 switch 3 equals a 1).

Place the terminal in LOCAL mode.

Type the following sequence.
ESC #8

5-11

5.2.6.5 SET-UP Screen Test - In SET-UP mode the terminal exercises all of its display functions.
The functions available in the base VT 100 include double height, double width characters (SET-UP

A), double width, single height characters (TO EXIT PRESS “SET-UP”), and reverse or underline
base attribute (selected by the cursor setting and displayed by the cursor and the tab ruler).
The other SET-UP features can be checked using the keyboard controls: intensity (cursor up and

down), 80/132 column, tab setting and clearing, transmit and receive speeds, reset, smooth/jump
scroll, auto repeat, reverse screen, margin bell, keyclick, US/UK character set, wraparound, on
line/local control. Check smooth scrolling by filling the screen with Es (Paragraph 5.2.6.4) and pressing the line feed key in LOCAL mode.

With the advanced video option, the terminal displays the top line (SET-UP A) in bold and 'blinking
mode. This means that the line alternates between normal intensity and bright intensity. The next line

is underlined while the tab ruler is reverse video. The cursor setting is independent.

5.2.7

Error Codes
If executing any of the self tests produces an error, the test stops automatically. There are two broad
categories of errors, Fatal, and Nonfatal. Fatal errors cause the terminal to immediately stop all
operation. No intelligible information is displayed on the screen; however, the screen may not be
blank, but may contain a random pattern of characters. The only error indication (except the hung
terminal) is a possible error code displayed on the programmable keyboard LEDs (L1 through L4).
However, no terminal function including lighting the LEDs is guaranteed on a fatal error. The possible
fatal errors and the LED codes are listed in Table 5-4.

Nonfatal errors do not halt the terminal processor. Instead, the terminal is forced to LOCAL mode,
and an error code character is displayed in the upper-left corner of the screen, under the blinking
cursor. Additionally, if one or more nonfatal errors occur while the test is repeating continuously, the
entire screen flashes from white to black to white about once a second as an alarm. This continues until
the terminal is reset. There are five types of nonfatal errors:
|

“Advanced video option” data RAM (AVO)

“Nonvolatile” data RAM checksum error (NVR)

3.
4.

Keyboard missing or malfunction (KBD)
Data loopback error (Data)

EIA modem control lines loopback error (EIA)

Table 5-5 shows the possible nonfatal error characters that may appear on the screen and the failure
each character represents.
5.3
5.3.1

VIDEO ALIGNMENT
General

This section describes the alignment of both the Ball Brothers and Elston video monitors. All of the
individual adjustments do not have to be performed each time the monitor is aligned. However, each
adjustment should always be checked since many of the adjustments are interdependent.

Figure 5-1 shows the alignment templates used in this procedure to adjust both monitors. If the. myl.ar
adjustment templates (DEC part number 940322-3) are not available, reproduce the templates in Fig-

ure 5-1 on a separate piece of paper. Cut out the shaded area on each and use these copies to perform

the adjustments in place of the mylar templates.

5-12

9403246-3A
7179

VT-100

REV. A

CHARACTER-WIDTH
RED

CUT ALONG

SHADED
AREAS

OUTSIDE LINES

CHARACTER-HEIGHT
MIN

MAX

|
N,
ENT

(7179 VI100 940324638 REV.A

RED SHADED AREA

CATE

ALIGNM
84099203
ETI TEM LA

—

MA-5575

Figure 5-1 Video Alignment Templates

5.3.2

Monitor Adjustments (Ball Brothers)

The following paragraphs describe the alignment of the Ball Brothers video monitor. The Ball monitor
is easily identified by the placement of the flyback transformer. In the Ball monitor the transformer is

located on the horizontal brace above the neck of the CRT. In addition a small connector board is
located on the CRT yoke assembly.
All adjust ments must be made under the following conditions:
Lo
-

Normal video mode (white characters on a dark background)
80 characters per line mode
ANSI-compatible mode
LOCAL mode.

5.3.2.1

Brightness - Use the following procedure to adjust the brightness control on the monitor

board.

Allow the terminal to warm up for at least five minutes.

Increase the screen brightness to the maximum level by pressing the “4” key in SET-UP

mode.

Remove the terminal top cover (Paragraph 5.4.11).

Adjust R117 (Figure 5-2) until the display raster is visible. Then back off on the adjustment
until the raster disappears.

J101

BRIGHTNESS

VERT. HOLD

LRz|

A101

FOCUS

R122

—

VERT.

|vipeo

A103 1 CENTERING

LINEARITY

A102

HORZ

LINEARITY

WIDTH

R110

VERT.

HEIGHT

J102

J104

O
MA-2078

Figure 5-2 Ball Video Monitor Board Adjustments

5-15

Replace the terminal top cover.

Restore the screen brightness to normal intensity by pressing the *“} ~ key in SET-UP mode.

5.3.2.2

Focus - Use the following procedure to check and adjust the focus.

Type the following sequence.
ESC #8

Examine the characters at the four corners and in the center of the screen. The individual
dots in the vertical segment of the ‘““E’ should be visible in each character.
|
NOTES
In some cases, the operator may want the focus mis-

adjusted to suit personal preference.
If the focus is adjusted correctly do not perform the
following steps.

Remove the terminal top cover (Paragraph 5.4.11).

Adjust R122 (Figure 5-2) for the best overall character presentation.

Replace the terminal top cover if no further adjustments are required.

5.3.2.3
1.

Yoke Rotation - Use the following procedure to check and adjust the yoke.
Type the following sequence.
ESC #8

With the top cover still on the terminal, place the VT 100 alignment template (part number
940322-3) on the screen. Ensure that the template lies as flat as possible on the screen.

Verify that all four sides of the display presentation are parallel to the red shaded area of the
alignment template.

NOTE

If the yoke is adjusted correctly, do not perform the
following steps.

Remove the alignment template from the screen.

With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around

Remove the terminal top cover (Paragraph 5.4.11).

Tape the VT100 alignment template to the screen. To orient the template use the felt-tip pen

the screen.

marks placed on the screen in step 5.

5-16

8.
9.
10.

Loosen the yoke collar clamp screw (Figure 5-3) and turn the yoke until the four sides of the

display presentation are parallel to the red shaded area of the alignment template.

Ensure that the yoke is pushed all the way forward toward the face of the CRT. While

holding the yoke in place, tighten the yoke collar clamp screen.

Clean the marks off the screen and replace the terminal top cover if no further adjustments
are required.

VERTICAL

i‘

T ——CENTERING

(O)

RINGS

YOKE COLLAR

CLAMP SCREW

Figure 5-3 Ball Monitor CRT Adjustments

5.3.2.4
height.
1.

Vertical Height - Use the following procedure to check and adjust the overall presentation

Type the following sequence.
ESC #8

With the top cover still on the terminal, place the VT 100 alignment template on the screen.
Ensure that the template lies flat as possible on the screen.

5-17

Verify that the top and bottom lines of the presentation are covered by the red shaded area
of the adjustment template.
NOTE
If the vertical height is correct, do not perform the
following steps.

Remove the alignment template from the screen.

With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around
the screen.

Remove the terminal top cover (Paragraph 5.4.11).

Tape the VT 100 alignment template to the screen. To orient the template use the felt-tip pen
marks placed on the screen in step 3.

Adjust the vertical height using R110.
9.

Check and adjust vertical linearity, vertical hold, and centering if needed.

10.

Clean the marks off the screen and replace the terminal top cover if no further adjustments
are required.

5.3.2.5

Horizontal Width - Use the following procedure to check and adjust the overall presentation

width.
1.

Type the following sequence.
ESC #8

With the top cover still on the terminal, place the VT100 alignment template on the screen.
Ensure that the template lies as flat as possible on the screen.
Verify that the first and last columns of the presentation are covered by the red shaded area
of adjustment template.
NOTE

If the horizontal width is correct do not perform the
following steps.

Remove the alignment template from the screen.

With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around
the screen.

Remove the terminal top cover (Paragraph 5.4.11).

Tape the VT100 alignment template to the screen. To orient the template use the felt-tip
marks placed on the screen in step 3.

Adjust the horizontal width coil L103 with a monitor alignment tool (DEC part number 2923190-00 and shaft extender 29-23189-00).

5-18

Check and adjust the horizontal linearity and centering if needed.

10.

Clean the marks off the screen and replace the terminal top cover.

5.3.2.6
1.

Centering - Use the following procedure to check and adjust the presentation centering.
Type the following sequence.
ESC #8

With the top cover still on the terminal, place the VT 100 alignment template on the screen.
Ensure that the template lies as flat as possible on the screen.

Verify that the display presentation falls within the red shaded area on the alignment template. If the presentation is too large or too small perform the appropriate width or height
adjustment.
NOTE

If the centering is correct, do not perform the following steps.

Remove the alignment template from the screen.

With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around
the screen.

Remove the terminal top cover (Paragraph 5.4.11).

Tape the VT 100 alignment template to the screen. To orient the template use the felt-tip pen
marks placed on the screen in step 3.

Set A103 fully counterclockwise.

Center the presentation by rotating the centering tabs on the yoke (Figure 5-3) with respect
to the tube and each other.
NOTE

A103 may be used to move the display presentation a
small distance horizontally. If A103 is misadjusted,
the left side of the screen presentation may be distorted.
10.

Clean the marks off the screen and replace the terminal top cover if no further adjustments
are required.

5.3.2.7

Vertical Linearity - Use the following procedure to check and adjust for uniform character

height.
l.

Type the following sequence.
ESC #8

5-19

Use the VT100 character height template to verify that the height of the characters near the
four corners and center of the presentation falls between the minimum and maximum units
of the template.
NOTE
If the vertical linearity is correct do not perform the
following steps.

Remove the terminal top cover (Paragraph 5.4.11).
Adjust the vertical linearity using A102.

Check and adjust the vertial height, vertical hold, and centering if needed.
Replace the terminal top cover if no further adjustments are required.

P—h

5.3.2.8
width.

Horizontal Linearity - Use the following procedure to check and adjust for uniform character

Type the following sequence.
ESC #8

Use the VT 100 character width template to verify that the width of the characters near the
four corners and center of the presentation falls between the minimum and maximum limits
of the template.
NOTE

If the horizontal linearity is correct do not perform
the following steps.
Remove the terminal top cover (Paragraph 5.4.11).

Adjust the horizontal linearity coil L102 with a monitor alignment tool (DEC part number
29-23190-00 and shaft extender 29-23189-00).

Check and adjust the horizontal width and centering if needed.
Replace the terminal top cover if no further adjustments are required.
Vertical Hold - Use the following procedure to adjust the vertical hold.
Remove the terminal top cover (Paragraph 5.4.11).

Set A101 fully counterclockwise.

Check and adjust the vertical height, vertical linearity, and centering if needed.
Replace the terminal top cover if no further adjustments are required.

5-20

5.3.3

Monitor Adjustments (Elston)

The following paragraphs describe the alignment of the Elston video monitor. The Elston monitor is
easily identified by the placement of the flyback transformer. In the Elston monitor the transformer 1s
located on the monitor sideplate opposite the monitor board. In addition, the connector card is not
present on the Elston CRT yoke assembly.
All adjustments must be made under the following conditions:
1.

Normal video mode (white characters on a dark background)

80 characters per line mode

ANSI compatible mode

LOCAL mode.

5.3.3.1
board.

1.
2.

Brightness — Use the following procedure to adjust the brightness control on the monitor

Allow the terminal to warm up for at least five minutes.
Increase the screen brightness to the maximum level by pressing the

‘4’ key in SET-UP

mode.
3.

Remove the terminal top cover (Paragraph 5.4.11).

Adjust R109 (Figure 5-4) until the display raster is visible. Then back off on the adjustment
until the raster disappears.

R109
BRIGHTNESS
R477

FOCUS

R334
HEIGHT \

R342
VERTICAL=—
LINEARITY

MA-4572

Figure 5-4 Elston Video Monitor Board Adjustments

5-21

Replace the terminal top cover.

Restore the screen brightness to normal intensity by pressing the "t key in SET-UP mode.

5.3.3.2
1.

Focus --Use the following procedure to check and adjust the focus.
Type the following sequence.
ESC #8

Examine the characters at the four corners and center of the screen. The individual dots in

the vertical segment of the ‘““E’’ should be visible in each character.
NOTE
In some cases, the operator may want the focus mis-

adjusted to suit personal preference.

If the focus is adjusted correctly, do not perform the following steps.
3.

Remove the terminal top cover (Paragraph 5.4.11).

Adjust R477 (Figure 5-4) for the best overall character presentation.

Adjust the focus rings furthest from the yoke for the best focus at all four corners (Figure 55). Readjust R477 if needed.

Replace the terminal top cover if no further adjustments are required.

CRT ANODE CAP

FLYBACK

X-FORMER

VIDEO

MONITOR
BOARD

FOCUS YOKE

RINGS

CLQE"VSS CENTERING
SC

RINGS

YOKE

COLLAR

Figure 5-5 Elston Monitor CRT Adjustments

5-22

MA-4573

Pr—

5.3.3.3

Yoke Rotation - Use the following procedure to check and adjust the yoke.
Type the following sequence.
ESC #8

With the top cover still on the terminal, place the VT100 alignment template (part number
940322-3) on the screen. Ensure that the template lies as flat as possible on the screen.
Verify that all four sides of the display presentation are parallel to the red shaded area of the
alignment template.

NOTE
If the yoke is adjusted correctly do not perform the
following steps.

Remove the alignment template from the screen.

With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around
the screen.

Remove the terminal top cover (Paragraph 5.4.11).

Tape the VT 100 alignment template to the screen. To orient the template use the felt-tip pen
marks placed on the screen in step 3.

Loosen the yoke collar clamp screw (Figure 5-5) and turn the yoke until the four sides of the
display presentation are parallel to the red shaded area of the alignment template.
Ensure that the yoke is pushed all the way forward toward the face of the CRT. While
holding the yoke in place, tighten the yoke collar clamp screen.
10.

Clean the marks off the screen and replace the terminal top cover if no further adjustments
are required.

5.3.34

Vertical Height - Use the following procedure to check and adjust the overall presentation

height.
l.

Type the following sequence.
ESC #8

With the top cover still on the terminal, place the VT100 alignment template on the screen.
Ensure that the template lies as flat as possible on the screen.
Verify that the top and bottom lines of the presentation are covered by the red shaded area

of the adjustment template.
NOTE
If the vertical height is correct do not perform the
following steps.
Remove the alignment template from the screen.

5-23

With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around

the screen.
Remove the terminal top cover (Paragraph 5.4.11).
Tape the VT100 alignment template to the screen. To orient the template use the felt-tip pen
marks placed on the screen in step 5.

Adjust the vertical height using R334.
9.

Check and adjust the vertical linearity if needed.

10.

Clean the marks off the screen and replace the terminal top cover if no further adjustments
are required.

5.3.3.5
width.

Horizontal Width - Use the following procedure to check and adjust the overall presentation

Type the following sequence.
ESC #8

With the top cover still on the terminal, place the VT 100 alignment template on the screen.

Ensure that the template lies as flat as possible on the screen.
Verify that the first and last columns of the presentation are covered by the red shaded area

of the adjustment template.
NOTE
If the horizontal width is correct do not perform the
following steps.

Remove the alignment template from the screen.
With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around
the screen.
Remove the terminal top cover (Paragraph 5.4.11).

Tape the VT100 alignment template to the screen. To orient the template use the felt-tip
marks placed on the screen in step 3.

Adjust the horizontal width coil L403 with a monitor alignment tool (DEC part number 2923190-00 and shaft extender 29-23189-00).
9.

5.3.3.6
1.

Clean the marks off the screen and replace the terminal top cover.

Centering — Use the following procedure to check and adjust the presentation centering.
Type the following sequence.
ESC #8

5-24

With the top cover still on the terminal, place the VT 100 alignment template on the screen.
Ensure that the template lies as flat as possible on the screen.
Verify that the display presentation falls within the red shaded area on the alignment template. If the presentation is too large or too small, perform the appropriate width or height
adjustment.
NOTE
If the centering is correct, do not perform the following steps.

Remove the alignment template from the screen.

With a dark blue or black felt-tip pen, mark the four edges of the screen at the bezel around
the screen.
Remove the terminal top cover (Paragraph 5.4.11).
Tape the VT100 alignment template to the screen. To orient the template use the felt-tip pen
marks placed on the screen in step 5.

Center the presentation by rotating the frontmost centering rings the neck of the CRT (Figure 5-5) with respect to the tube and each other.
Clean the marks off the screen and replace the terminal top cover if no further adjustments
are required.

5.3.3.7
height.

Vertical Linearity - Use the following procedure to check and adjust for uniform character

Type the following sequence.
ESC #8

Use the VT 100 character height template to verify that the height of the characters located
near the four corners and the center of the presentation falls between the minimum and
maximum units of the template.
NOTE
If the vertical linearity is correct do not perform the
following steps.

Remove the terminal top cover (Paragraph 5.4.11).
Adjust the vertical linearity using R342.

Check and adjust the vertical height if needed.
Replace the terminal top cover if no further adjustments are required.

5-25

MODULE REMOVAL AND REPLACEMENT

5.4.1
General
This section contains information for removal and replacement of mechanical subassemblies in VT 100

series terminals. Unless otherwise noted each procedure is applicable to all terminals in the series.
Figure 5-6 lists all of the removal procedures in this chapter and the sequence in which they are
performed. As an example, the figure illustrates that to remove the dc power harness, the top cover,
bottom cover, and power supply removal procedures must be performed first.
5.4.2

Access Cover
The following procedure describes the removal and installation of the terminal access cover.
1.

Remove power from the terminal by disconnecting the ac plug.

Unplug the keyboard.
Unplug any connectors from the composite video input/output jacks.
Disconnect the communications cable.

Use a blade type screwdriver to loosen the four captive screws holding the access cover
(Figure 5-7).
If the 20 mA current loop option is installed, gently pull the access cover away from the
terminal about two (2) inches. Then reach in and disconnect J5 from the terminal controller
board.
7.

5.4.3

To install the access cover, perform steps 1-6 in reverse.
Terminal Controller Board

The following procedure describes the removal and installation of the terminal controller board.
l.

Remove the terminal access cover (Paragraph 5.4.2).

Pull the terminal controller board out gently, but firmly. If the terminal 1s a VT105 disconnect the graphic interface cable from J2 of the terminal controller board (Figure 5-8).
Remove the advanced video board (if installed) on the terminal controller board (Paragraph
5.4.4).

To install the terminal controller board, perform steps 1-3 in reverse. Refer to Figure 5-8 for
positioning the VT105 graphic interface cable. This 16-pin connector plugs into the 18-pin
socket with the bottom pair of pins unused.
5.4.4

Advanced Video Board

The following procedure describes the removal and installation of the advanced video (AVO) board.
1.

Remove the terminal access cover (Paragraph 5.4.2).

Remove the terminal controller board (Paragraph 5.4.3).

Place the terminal controller board on a flat surface with the componeht side up (Figure 5-

9).

5-26

ACCESS

KEYBOARD

COVER

Top

(PARA5.4.2)

COVER
(PARA 5.4.7)

KEYBOARD

(PARA 5.4.8)

TERMINAL

OGP
BOARD |
(PARA5.4.6)

VT105

CONTROLLER
BOARD

WAVE
FORM BD
GENERATOR

(PARA 5.4.3)

(PARA 5.4.5)

KEYBOARD
CABLE

(PARA 5.4.9)

SPEAKER

(PARA 5.4.10)

TOP

OPS/E%NCED

COVER

BOARD

(PARA 5.4.11)

VIDEO MONITOR

BOTTOM

%flgfl%416)
'

BOARD

BALL (PARA5.4.12)

ELSTON (PARA 5.4.14)]

(PARA5.4.4)

FLYBACK

TRANSFORMER

BALL (PARA 5.4.13)

| ELSTON(PARA 5.4.15)

POWER
SUPPLY

(PARA5.4.17)

VT 105 DC.
POWER HARNESS|
(PARA5.4.19)

VT105 EXPANSION|
|BACKPLANE
9 (PARA 5.4.20)

| vT100 DC,
PFQWER HARNESS
(PARA 5.4.18)

FIELD SERVICE
2§§E",(‘4%T'YTOR
(PARA B2 21)
MA-4575

Figure 5-6 Removal Procedures Flowchart

5-27

Grasp the advanced video board by its edges near the connector and gently but firmly lift the
board straight up and off the terminal controller board.

To install the advanced video board, perform steps 1-4 in reverse.
NOTE

Check the AVO board to ensure that it contains the
correct ROMs, jumpers, and switch settings (Paragraph 5.6).

)

1004 ’rt4,,

/
/
/
/
l

/
;

COVER

BOTTOM COVER
MA-2074

Figure 5-7 VT100 Terminal, (Rear View)

5.4.5

VTI105 Waveform Generator Board

The following procedure describes the removal and installation of the VT105 waveform generator
board.

Remove the access cover (Paragraph 5.4.2).

Disconnect the graphic interface cable from XE90 on the waveform generator board (Figure
5-9).

Remove the waveform generator board by gently but firmly pulling the board straight out of
J2 on the backplane.

5-28

To install the waveform generator perform steps 1-3 in reverse.

NOTE
If the cable was disconnected at the terminal controller during this procedure, refer to Paragraph
5.4.3 for reconnection information.

USE SCREWDRIVER
TO GENTLY PRY

OF SOCKET

CONNECTOR OUT

\
\<

////;4;;/

XEQ0Q_~
>

47;%;] fi:\\\\T
A

| ACCESS

]

COVER

M7071
WAVEFORM

GENERATOR

RED LINE ON CABLE

xggp

MUST BE IN

POSITION

A
\ \\ \\ \

VT100

J'J
1

TERMINAL

CONTROLLER
J2

PINS9 AND 10

ARE NOT USED
MA-4577

Figure 5-8 VT105 Interconnections

5-29

STANDOFF

COMPONENT SIDE
OF ADVANCED

VIDEO BOARD
f

COMPONENT
SIDE OF

TERMINAL

DETAIL

CONTROLLER
ADVANCED

TERMINAL

VIDEO

CONTROLLER

BOARD

J1 ADVANCE

STANDOFFS (4)

BOARD

VIDEO
CONI}IECTOR

—

7
|—]

GRAPHI

CONNECTOR

J5 20mA
CURRENT LOOP
CONNECTOR

pad

J3 STP

_~~ CONNECTOR

J4 EIA
COMMUNICATIONS

CONNECTOR

J8 VIDEO IN

CONNECTOR
J9 VIDEO OUT
CONNECTOR

J7 KEYBOARD

CONNECTOR
MA-1995

Figure 5-9 Terminal Controller with AVO

5.4.6 20 mA Current Loop Board
The following procedure describes the removal and installation of the 20 mA current loop board.

Remove the access cover (Paragraph 5.4.2).

Use a Phillips screwdriver to remove the two screws holding the Mate-N-Lok connector to
the bottom of the access cover.

5-30

Use a Phillips screwdriver to remove the three screws holding the 20 mA current loop board
to the access cover and remove the board.

To install the 20 mA current loop board, perform steps 1-3 in reverse.

5.4.7

Keyboard Top Cover
The following procedure describes the removal and installation of the keyboard top cover.
1.

Remove power from the terminal by disconnecting the ac plug.

Unplug the keyboard from the monitor.

Turn the keyboard over so that the keycaps are face down and place the keyboard on a flat
surface.
Use a blade-type screwdriver to loosen the captive screws holding the keyboard together
(Figure 5-10).
Grasp the entire keyboard assembly and turn it right side up.
6.

Remove the top cover by lifting it straight up.

To install the keyboard top cover, perform steps 1-6 in reverse.

5.4.8 Keyboard
The following procedure describes the removal and installation of the keyboard.
l.

Remove the keyboard top cover (Paragraph 5.4.7).

Disconnect keyboard cable J2 from the keyboard.

Remove the keyboard.

To install the keyboard perform steps 1-3 in reverse.

5.4.9

Keyboard Cable
The following procedure describes the removal and installation of the keyboard cable.
l.

Remove the keyboard top cover (Paragraph 5.4.7).

Remove the keyboard (Paragraph 5.4.8).
Disconnect the keyboard cable from the speaker.
Remove the keyboard cable.
To install the keyboard cable, perform steps 1-4 in reverse.

AR
YBO

Y
KE

/
K

] ‘]Pt -

B
EY

)
2
(
S
W
E
R
C
S
E
V
'
T
XCAP

Figure 5-10 Keyboard Disassembly

5.4.10

Keyboard Speaker

The following procedure describes the removal and installation of the keyboard speaker.
1.

Remove the keyboard top cover (Paragraph 5.4.7).

Remove the keyboard (Paragraph 5.4.8).

Remove the keyboard cable (Paragraph 5.4.9).

Remove the speaker by sliding it toward the front edge of the keyboard cover.

To install the keyboard speaker, perform steps 1-4 in reverse.

S5.4.11
Terminal Top Cover
The following procedure describes the removal and installation of the terminal top cover.
1.

Remove power from the terminal by disconnecting the ac plug.

Use a small blade-type screwdriver to release the two front pop fasteners located under the
front lip (Figure 5-11a).

~—

’
e

I —

\I\

]

POP FASTENERS (2)

Figure 5-11a Top Cover Removal (Front View)

5-33

MA-2075

Use a small blade-type screwdriver to release the two rear pop fasteners located on the lower
rear edge of the bottom cover (Figure 5-11b).

Remove the top cover by lifting straight up.

To install the top cover, perform steps 1-5 in reverse.

POP FASTENERS (2)

MA-2076

Figure 5-11b Top Cover Removal (Rear View)

5.4.12 Video Monitor Board (Ball Monitor)
The following procedure describes the removal and installation of the video monitor board.
1.

Remove the terminal top cover (Paragraph 5.4.11).

Remove the circular connector from the base of the CRT (Figure 5-12). Bend the wire
harness up and out of the way.

Disconnect the four wires from the yoke connection card:
Tab 1 - yellow
Tab 2 -red
Tab 3 - blue
Tab 4 - brown

5-34

Disconnect 4-wire connector J102 at the bottom of the video monitor board.

Disconnect 7-wire connector J104 at the bottom center of the video board. Move the harness
up and out of the way.

Disconnect the green ground wire.

Disconnect video input cable J101 from the top edge of the video monitor board.

Release the four standoffs and remove the video monitor board.

To install the video monitor board perform steps 1-8 in reverse.

CAUTION
Do not misalign connectors S102 or S103 when reconnecting the cable. The monitor board may be
damaged if the connector is not aligned correctly.

STANDOFFS
(4)
FLYBACK

TRANSFORMER

J101

TAB 4

//////

1102

J104

GROUND

—

CIRCULAR BASE
CONNECTOR

WIRE

MA-2082

Figure 5-12 Ball Video Monitor Board Removal

5-35

5.4.13 Flyback Transformer (Ball Monitor)
The following procedure describes the removal and installation of the flyback transformer.
WARNING
This procedure deals with the CRT anode which may
contain a stored high voltage. See step 3 for the
anode discharge procedure.
1.

Remove the terminal top cover (Paragraph 5.4.11).

Disconnect 7-wire connector J104 at the bottom center of the video monitor board. Move
the harness up and out of the way.

Discharge the high voltage contained at the CRT anode. This is done by gently slipping the
end of an insulated handled screwdriver under the plastic anode cap on the top of the CRT
and shorting the other end of the screwdriver to a nonpainted area of the CRT frame. See
Figure 5-13.
WARNING
All grounds must be intact or the CRT will not discharge.

CAUTION
Do not scratch the glass of the CRT when discharging the CRT anode.

Disconnect the heavy red CRT anode wire from the CRT.

Use a 1/4 inch nutdriver to remove the two (2) nuts mounting the flyback transformer to the
horizontal crossbrace and remove the transformer.
CAUTION
The flyback transformer ferrite material is brittle.
Use care when handling the transformer.

6.
5.4.14

To install the flyback transformer, perform steps 1-5 in reverse.
Video Monitor Board (Elston)

The following procedure describes the removal and installation of the Elston video monitor board.
1.

Remove the terminal top cover (Paragraph 5.4.11).

Remove the circular connector from the base of the CRT (Figure 5-14).

Disconnect the white wire connecting the video monitor board to the yoke ground lug.

Disconnect 8-pin connector S102 from the video monitor board.

5-36

Disconnect 4-pin connector S103 from the video monitor board.
Disconnect video input connector S101 from the top edge of the video monitor board.
Release the four (4) standoffs and remove the video monitor board.
To install the video monitor board perform steps 1-7 in reverse.
CAUTION
Do not misalign connectors S102 or S103 when re-

connecting the cable. The monitor board may be
damaged if the connector is not aligned correctly.

INSULATED HANDLE

SCREWDRIVER
CRT

ANODE

“a

METAL

/FRAME

CRT
MA-2070

Figure 5-13 CRT Anode Discharging

5-37

VERTICAL
CHOKE

GROUND WIRE

CRT ANODE

STANDOFFS

MONITOR
IDE

PCB

CRT BASE \

VOKE COLLAR

FLYBACK

| TRANSFORMER

CLAMP SCREWS
MA-4574

Figure 5-14 Elston Video Monitor Board Removal

5.4.15 Flyback Transformer (Elston)
The following procedure describes the removal and installation of the Elston flyback transformer.
WARNING
This procedure deals with the CRT anode which may

contain a stored high voltage. See step 4 for the
anode discharge procedure.

Remove the terminal top cover (Paragraph 5.4.11).

Remove the terminal controller board (Paragraph 5.4.3). If the terminal is a VT 105 remove
the waveform generator (Paragraph 5.4.6).

Disconnect 8-pin connector S102 from the video monitor board.

WARNING
All grounds must be intact or the CRT will not discharge.

CAUTION
Do not scratch the glass of the CRT when discharging the CRT anode.

5-38

Disconnect the heavy red CRT anode wire from the CRT.

Remove the screw and washer securing the vertical choke to the monitor chassis. Remove
the vertical choke.

Use a 1/4 inch nutdriver to remove the two (2) nuts mounting the flyback transformer to the
monitor chassis.

CAUTION
The flyback transformer ferrite material is brittle.
Use care when handling the transformer.

To install the flyback transformer, perform steps 1-7 in reverse. Be sure to reconnect the arc
ground wire in the cable harness.

CAUTION
Do not misalign connectors S102 or S103 when reconnecting the cable. The monitor board may be
damaged if the connector is not aligned correctly.
5.4.16

Terminal Bottom Cover

The following procedure describes the removal and installation of the terminal bottom cover.
1.

Remove the terminal top cover (Paragraph 5.4.11).
- Disconnect the power cord from the terminal.

Turn the terminal over on its side and remove the four (4) shipping screws (if installed)
securing the bottom cover to the chassis. Discard the screws.

Locate the two (2) front pop fasteners holding the frame to the base. Release the fasteners by
pulling the plunger up.

Locate the two (2) rear pop fasteners holding the frame to the base. Release the fasteners by
pulling the plunger up.
6.

Grasp the metal frame and lift the frame up and out of the terminal bottom cover.

To install the bottom cover, perform steps 1-6 in reverse.

5.4.17

Power Supply

The following procedure describes the removal and installation of the power supply.
l.

Remove the terminal top cover (Paragraph 5.4.11).

Remove the bottom cover (Paragraph 5.4.16).

5-39

Locate the three (3) pop fasteners on the side of the chassis. Release the pop fasteners by
pulling the plungers out (Figure 5-15).
WARNING
Capacitors C9, C14 and the surrounding circuits can

contain a 300 Vdc charge. To discharge the capacitors, leave the power supply plugged into the terminal
for a minimum of four minutes after the power cord
is removed.
To assure complete discharge of the capacitors short

the capacitors with an insulated wire as shown in Figure 5-16.
4.

Grasp the power supply by the housing to the left of the fuse post. Use the pop fastener at
the right side of the end plate to remove the power supply by rocking it out.

To install the power supply perform steps 1-4 in reverse. The projection on the chassis that
enters a slot next to the fuse post provides spring-loaded grounding.

POP
FASTENERS

CHASSIS

‘\
POWER

SUPPLY
MA-2077

Figure 5-15 Power Supply Removal

5-40

CAPACITORS

Jiig

’

\\'

—

j /

—

C9 & C14

\
SHORT THESE 2 POINTS

MA-2072

Figure 5-16 Power Supply Capacitor Discharging

5.4.18

VT100 DC Power Harness
The following procedure describes the removal and installation of the dc power harness.
l.

Remove the terminal top cover (Paragraph 5.4.11).

Remove the bottom cover (Paragraph 5.4.16).
Remove the power supply (Paragraph 5.4.17).

Remove the terminal controller (Paragraph 5.4.3).

Disconnect 10-pin edge connector J101 from the video monitor board.
Remove the card cage by releasing the two (2) pop fasteners holding the top of the card cage
to the chassis. Tilt the card cage out slightly and lift the card cage out of the bottom holding
clips.

Disconnect the ground wire connected to the monitor chassis.

Remove the two (2) fasteners holding the 22-pin edge connector to the card cage. Then
remove the connector (Figure 5-17).

Remove the two (2) fasteners holding the 18-pin edge connector to the chassis and then
remove the connector.

10.

Remove the dc power harness.

11.

To install the dc power harness, perform steps 1-10 in reverse.

POP FASTENERS (2)
CHASSIS

CARD
CAGE

18 PIN

CONNECTOR

22 PIN

CONNECTOR

D.C.POWER
HARNESS
MA-2073A

Figure 5-17 VT100 DC Power Harness Removal

5.4.19

VTI105 DC Power Harness

The following procedure describes the removal and installation of the dc power harness.
1.

Remove the terminal access cover (Paragraph 5.4.2).

Remove the terminal top cover (Paragraph 5.4.11).

Remove the terminal bottom cover (Paragraph 5.4.16).

5-42

Remove the terminal controller board (Paragraph 5.4.3). If the terminal is a
the waveform generator (Paragraph 5.4.6).

VT 105 remove

Remove the power supply (Paragraph 5.4.17).

Release the two (2) pop fasteners holding the top of the card cage to the chassis and tilt the
card cage top out.
Disconnect 10-pin edge connector J101 from the video monitor board.

Disconnect the ground wire connected to the monitor chassis.
Disconnect the 22-pin edge connector on the expansion backplane (Figure 5-18).

WIRE FRAME

11>

EXPANSION BACKPLANE

\SPACER h\ »Ak“’
G

MA-4580

Figure 5-18 VT 105 Expansion Backplane Removal

5-43

Remove the two (2) fasteners holding the 18-pin edge connector to the chassis and then

10.

remove the connector.
11.

Remove the dc power harness.

12.

To install the dc power harness, perform steps 1-11 in reverse.

5.4.20

VT10S5 Expansion Backplane Removal and Installation

Remove the terminal access cover (Paragraph 5.4.2).

Remove the terminal top cover (Paragraph 5.4.11).
Remove the terminal bottom cover (Paragraph 5.4.16).
Remove the terminal controller board (Paragraph 5.4.3). If the terminal is a VT 105, remove
the waveform generator (Paragraph 5.4.6).
Disconnect the 22-pin edge connector from the expansion backplane (Figure 5-18).

Remove the four (4) screws and nuts and two (2) spacers securing the expansion backplane
to the card cage.
To install the expansion backplane, perform steps 1 through 7 in reverse.

5.4.21

Field Service CRT Monitor Assembly

The following procedure describes the removal and installation of the Field Service CRT monitor
assembly.
1.

Remove the terminal top cover (Paragraph 5.4.11).

Remove the bottom cover (Paragraph 5.4.16).
Remove the power supply (Paragraph 5.4.17).
WARNING

High voltage may be present at the CRT anode. See
Paragraph 5.4.13 step 3 for the anode discharge procedure.

Remove the card cage by releasing the two (2) pop fasteners holding the top of the card cage
to the chassis. Tilt the cage top out slightly and then lift the card cage out of the bottom
holding clips.

Remove the two (2) E-clip fasteners holding the 18-pin edge connector to the chassis and
then remove the connector.

Replace the Field Service CRT monitor assembly.

To install the Field Service CRT monitor assembly, perform steps 1-6 in reverse.

5-44

5.4.22 CRT Storage and Disposal
All CRTs should be stored in the closed shipping container.

Place the defective CRT assembly in the replacement part’s shipping container and seal the
container.

2.
5.5

Return the defective CRT assembly to the local service office.

BOARD CONFIGURATIONS

This section contains the information required to configure all boards in the following terminals:
VT100 and all optional configurations
VT105
VT132.

5.5.1

Terminal Controller Board
The following paragraphs show all of the possible configurations of the terminal controller board, part
number 54-13009.
VT100 - Figure 5-19 shows the VT100 configuration of the VT 100 terminal controller board.
VT132 - Figure 5-20 shows the VT 132 configuration of the VT 100 terminal controller board.

2 d

gggg?mz\ \[j
ROM 2
23-033E2

ROM 1— |

2303262

qomo0—"

23-061E2

}

|~
|

23-031E2

GRAPHICD
OPTION

CONN.

ADVANCED:

VIDEO

OPTION
CONN

3
[
:

|
;i

2%#""'?’

0 ON.

CONN.

STP

|[CONNECTOR

EIA

CONN.

EXT. VIDEO IN={ [71J8
CHARACTER
El

EXT. VIDEO OUT
=

GENERATOR

KEYBOARD|

[:3

CONN.

]:]Jg

]

MA-4582

Figure 5-19 Terminal Controller Board VT100 Configuration

5-45

ROM 3

23-095E2 ~
ROM 2

S~—
.

23-096E2

}

//-

ROM O

-140E2

CONN.

}

]

OPTION

ROM 1 _,/_:}

23-139E2

SRAPHIC J2

20Ma

ADVANCED]|:

OPT,ON

(\)/II’["?'IIEC())N

CONN.

[

[STP

CONNECTOR|Y
EIA

;

| )4

CONN.

EXT. VIDEO IN{ [[51J8
6

GENERATOR

KEYBOARD[

CONN.

n
80,

MA-4583

Figure 5-20 Terminal Controller Board, VT 132 Configuration

5.5.2

Advanced Video Board
The following paragraphs show all of the possible configurations of the advanced video board, part
number 54-13097.

VT100 - Figure 5-21 shows the VT100 configuration of the advanced video board.

VT100-WA
/WB - Figure 5-22 shows the VT 100-W
A /WB configuration of the advanced video board.
VT132 - Figure 5-23 shows the VT132 configuration of the advanced video board.
5.5.3

VTI105 Waveform Generator Board
Figure 5-24 shows the configuration of the VT105 waveform generator, part number M7071.

5-46

.
|

NO JUMPERS

INSTALLED

| 1
2

:55553

(15

L__J9
110

ALL

SWITCHES

OPEN

o—s

JUMPER IN

JUMPER OUT

wl,

uZJ

| @

1810
I

[ ]

=1l

o[ 1810

=4 |

NOTE:
DOT ON SWITCH SHOWS
THE SIDE DEPRESSED
MA-4389

Figure 5-21 Advanced Video Board VT100 Configuration

5-47

N
1

AND W7

C_12

INSTALLED

] 2

—

| 8

110

J11

112

IN
B JUMPER

me/

23-069E2

[

JUMPER QUT

‘B |

(o0]

[)

M s

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S1&S7 —

CLOSED TM~__

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N

NOTE:

DOT ON SWITCH SHOWS
THE SIDE DEPRESSED

ROM
23-069E2

MA-4584

Figure 5-22 Advanced Video Board VT100-WA /WB Configuration

5-48

NI
TM

e .

OO0~ SSCTEWN
o

-—

M-—l

—
——

~rW

-—

W6
INSTALLED

B JUMPER
IN
)

ROM

23.099E2

JUMPER OUT

| |
/

S6 CLOSED

12345678

rofl
23-100E2

o e

RON

23-099E2

ROM
23-100E2

BSFO'N SWITCH SHOWS

THE SIDE DEPRESSED

MA-4585

Figure 5-23 Advanced Video Board, VT 132 Configuration

5-49

XEQ0

1781
[

[
dET

W2mm

— W3

[
JE64

[ 9E27
ms W1

[ 9gE20

18
s

JUMPER IN

—

JUMPER QUT
MA-4586

Figure 5-24 VT105 Waveform Generator Board Configuration
5.6

COMPONENT LEVEL TROUBLESHOOTING

5.6.1

Troubleshooting the Terminal Controller
Refer to Paragraph 5.2 to isolate problems to a field replaceable unit (FRU) such as the terminal
controller board. This section explains diagnosis of problems within the board.

Check the power supply for proper voltages and ripple. Make sure the voltage switch is not set to 230
volt on a 115 volt system. Check that all board edge contacts are clean and well seated.
Four possible self-test results are displayable on the screen or keyboard:
No valid LED code
LEDs indicating fatal error
Nonfatal errors with screen display
No indicated error.

This section explains the major areas in the terminal to check for each of the self-test results.
5.6.1.1

Microprocessor

5.6.1.1.1 No Valid LED Code - If the LEDs show some random value not shown in Table 5-1, several
areas must be checked. ROM 1 containing the self test routines may be at fault; the 8080 may be halted
or in an inappropriate routine; there may be a hard failure on the data or address bus. (See Paragraph
5.6.1.2.)

5-50

With ROMs, first try to reseat them in their sockets to ensure good contact. Check the chip select lines
to be sure the ROM is being selected.
Check the clock signals to the 8080 from the 8224 (E32-6, -10, -11). Check that the Ready and Reset
signals are both high (E32-4 and -1). Check for the Sync signal (E32-5) every 3 to 5 clock periods. If
there is no Sync, check Hold Request L (E35-13) which should go high for approximately 60 microseconds every 635 microseconds. Check for the Status Strobe (STSTB L) (E32-7). Hold Acknowledge
(HLDA, E35-21) should toggle in step with Hold Request. If the clocks are present and Sync is
entering E32 but Status Strobe does not appear, E32 is probably bad. If all these signals are okay, the
problem is most likely not in the 8080 circuits.
If Hold Request is always high, the video processor is bad even though it may be able to drive the
monitor. Grounding pin 1 of the Test MUX (E1) disconnects Hold Request, and while the self test
reports keyboard and NVR failures, the microprocessor is able to work. E1 also removes the master
clock from the video processor, so the monitor should be disconnected (to protect it). Connect EI pin 2
to 3, and E1-6 to 5 and 11 to run the microprocessor.

Check the data and address buses for toggling during the power-up test. Virtually every address gets
looked at during the test, and every data bit changes state, so that is the best time to check for stuck
bus lines. Restart the test for each line by shorting C10 momentarily with a clip lead.
Connections made at E1 can serve to force either the microprocessor or the video processor off the
buses. That is, asserting Hold Request L to the 8080 (with a clip lead from ground to pin 11) keeps the
video processor off the buses, and asserting Hold Request H (with a clip lead from E1-16 to E1-6 or
-10) keeps the microprocessor off the buses.
Check that the interrupt input is not stuck high (E35-14) if Interrupt Enable goes high. If the video
processor works there should be a Vertical Frequency interrupt every 16.7 ms. If the processor is stuck
in some kind of loop because some device is always calling it, the possibilities can be narrowed by
looking at each of the devices’ interrupts and flags.
5.6.1.1.2

LEDs Indicating Fatal Error — If the power-up self test never manages to finish, the LEDs

may display a number indicating the area of failure. Table 5-1 relates LED indications to areas of trouble.
LED indications mean the error is a fatal one, which means the terminal cannot function at all. (If the self
test finishes, the LEDs are cleared.) Only the ROMs and the main RAM cause such a failure. The table
shows the ROM to check if a ROM number is displayed. Try reseating the ROMs in their sockets to ensure good contact. Check the chip select lines to be sure the ROM is being selected. There is no simple
way to determine which of the six RAM chips is bad if a RAM failure is indicated. One at a time replacement of all six chips is the only way to find and fix a bad RAM chip. But the memory decoders should be
checked for their ability to address the RAMs before the RAMs themselves are blamed.

5.6.1.1.3 Nonfatal Errors with Screen Display - Nonfatal errors do not disable the terminal completely, although they may limit its usefulness. A keyboard failure, for example, still lets the terminal
operate in receive-only mode. Nonfatal errors have codes assigned to them for display on the screen at
the end of self test (see Table 5-2). The Data Loopback and EIA tests are considered nonfatal because
the microprocessor must work properly before the tests can run at all, but if they fail, the terminal
cannot communicate. To troubleshoot nonfatal problems, see the following paragraphs.
5.6.1.1.4

No Indicated Error - Many video processor and monitor problems (see below) do not affect
the microprocessor, so most self tests cannot detect the problems. But if the screen is filled with
garbage or it is blank after the keyboard beeps with all LEDs on at the same time (indicating completion of self test) the video processor or monitor may be at fault. (If the NVR fails its test, a number

5-51

appears on the screen and the keyboard beeps several times. If garbage or nothing appears when the
beeps occur, the problem is more likely to be in the video processor than in the NVR circuit.) Because

the microprocessor is known good after completion of self test, the screen RAM probably contains
proper control data (terminators and line addresses) so it should be possible to troubleshoot the video

processor (garbage: Paragraph 5.6.1.2) or the monitor (blank: Paragraph 5.6.4) as the first step. Run
the self tests again after fixing the video processor; other nonfatal errors may appear then.
Areas not directly tested by self test (because they have no effect on the microprocessor) are as follows.
NVR Write (tested by Saving)

Graphics port
Video processor (check with SET-UP screen test)
Monitor
Correctness of baud rates (only confirms match between send

and receive)
Keyboard switches
Some video processor functions must work for the self test to pass. For the microprocessor to work,
these video processor signals must be close to frequency:
LBA 3and 4

LBA 7 (NVR clock).
In addition, Hold Request cannot be stuck asserted and the NVR flag buffer must work.
3.6.1.2

Video Processor — There are two classes of video processor failure: 1) those that prevent
proper movement of data from the screen RAM and through the character latches, terminator detec-

tion, line address counters, (DMA problems in general), and 2) all other problems. Those include the
line buffer, character generator ROMs, video shift register, smooth scroll, attribute, and scan count
control in the DCO12, the analog video circuits, and monitor drive signals.
The areas in class 1 are difficult to troubleshoot because failures at any point in the loop from screen
RAM data to screen RAM line addressing can cause the same kind of symptoms. The following
section contains a suggested basic approach to the problem. The areas in class 2 have more straightforward troubleshooting because the character data can be considered valid and failures with a particular symptom are probably caused by a single kind of problem. No further detail is provided here.
In either case, be sure you understand the technical descriptions in Chapter 4 before spending any time
trying to troubleshoot these circuits.

A dual-trace, triggered oscilloscope with delayed sweep is essential for servicing the video processor.
Trigger the scope on Vertical Reset and examine each line for signals according to the DMA timing
diagram (Figure 4-6-19) in Chapter 4. Check the continuous signals from the DCO11. These include
everything except Address Load, Address Count, and Write Line Buffer. All others should be checked
against their timing diagrams for the respective screen modes. Any output affected by double
width/double height may be in either possible state.
Now check signals in this order:
1.

Vertical Reset

Address counter outputs E21, E22, E25, E30 (not the latches). All should be zero except
E22-5 at Vertical Reset.

5-52

Hold Request starting after time specified in Figure 4-6-19.

DMA Enable

Address Count and Write Line Buffer

While triggered on Vertical Reset, delay sweep to the region shown in Figure 4-6-20. Watch
for the data defined by Figure 4-7-5, Fill Line Operation at positions within the character
latches as shown in the chart in Figure 4-6-20.

Check for Terminate L during the time that Horizontal Blank is going low.

On the following character clock, Hold Request should go low causing Address Load to go
low and Address Count to stay high.

Check the address in address counter outputs (E21, E22, E25, E30) according to Figures 4-72 and 4-7-5.

10.

Check for unasserted line attributes at E6-23 and ES5-1, -26, -27.

11.

Adjust sweep delay to observe the second DMA period.

12.

Check the length of Hold Request. If twice as long as normal, this means that double width
mode has been invoked by some incorrect signal at Address Load time. Because the screen
RAM does not contain properly formatted data for double width, the video processor cannot display a normal screen.

Any other failures of address loading cause the second DMA to read from the wrong area of the screen
RAM.

It is possible for later

DM As to fail when early ones are okay if, for example, a high bit on the address

counter is stuck low. Then only higher address lines (lines later in the screen) are affected. This assumes

that no scrolling has been attempted since power-up, because that would eliminate the correspondence
between screen position and address order.
5.6.1.3

Communications - Most aspects of the communications channel operation are under program

control, so the microprocessor must be fully functional (power-up self test passed) for the interface to
work at all. The communications channel is tested with the data loopback connector (either EIA or 20
mA) installed. Self tests can then be started to check the channel operation. If there is a failure, leave
the loopback connector installed. Typing on the keyboard in on-line mode provides data movement to
the transmitter (and receiver if the transmitter works).

Check the STP connector contacts. All interface signals pass through these normally shorted contacts.
Check the baud rate clocks. The baud rate generator (E60) or its two-phase input drivers (E38) may be
bad. Check that the transmit and receive frequencies are as selected (16 times baud rate). It is possible
for E60 to accept changes on one side but not the other. At the PUSART, check the EIA line driver
and receiver chips (E39 and E44) and check for pulses on the address (E43-11, -12) and I/O control
lines (E43-10, -13) and on the interrupt flag lines (E43-14, -15).
Modem control problems are probably either the STP contacts or the EIA driver or receiver chips.

Check the enable line to the modem flag buffer (E-41). (Also check the modem control signal at the
NVR latch E-61.)

5-53

5.6.1.4 Nonvolatile RAM - The NVR is the only device that uses -23 volts (E24-2). The video processor must be providing LBA 7 as a clock with 12 volt swing at E24-6. Q1 must present a very high
impedance when it is off or read data will be lost. Check the NVR latch E-61 and the flag buffer E-42.

5.6.2 Troubleshooting the Keyboard
During the self test, check to see that the LEDs flash and that the bell sounds. Failure of these does not
cause the keyboard to fail but this is the best time to make sure that they work.
If the keyboard fails self test, the terminal automatically becomes a receive-only terminal. The number
4 1s then visible on the screen under the blinking cursor. Keyboard failure means the microprocessor
attempted to start a scan but did not get any results back. (The always-down “‘last key’” should always
be returned.) The problem could be at either end of the keyboard interface but is more likely at the

cable or connectors, or in the keyboard circuitry (because of its greater exposure to the environment).
Either the on-line or local LED should be on if the keyboard has 12 volt power and the 5 volt regulator
works. If power is good, check the interface line for the presence of signals from the terminal. Refer to

Paragraph 4.4 in Chapter 4 for an illustration of normal signal appearance.

On the interface, if the clock from the terminal is on the interface line, it should also be at E9-8. Serial
data input (1 bit for every 16 clocks) should be at the output of the integrator E2-1. Serial data output
should be at E9-12 (TTL level) and E8-8 (12 volt swing).

A clock signal always comes from the terminal, and command bytes come continuously, starting every
1.28 milliseconds. Every 50th or 60th of a second, one command byte includes a bit that triggers the
START SCAN L signal (E5-11) which should start the address counters. KEY DOWN L (E6-12)
should appear once each scan to represent the last address (for simplicity, make sure that no keys,
including CAPS LOCK are down) and should drive the DATA STROBE L input to the UART
(E12-23). TBMT H (Transmit Buffer Empty) (E12-22) should go low when DATA STROBE is asserted. TBMT H goes low for only a few clock periods when only one key address is being sent. More
keys held down causes TBMT H to stay low for more time for each additional key. When TBMT H is
low, the clock cannot pass through E4 to drive the counter clock input (E7-14); it can at all other
times. At the end of a scan, E3-1 goes high and holds the counter CLEAR inputs. The START SCAN
L signal (ES5-11) resets E3 to allow the count to continue.

If no signals are coming from the terminal (and this assumes that the phone jack on the board is good)
check for clock signals LBA3 and LBA4. These come from the video processor so if the display works
they should be present. If they are, check E18-1 and E18-2 (TTL and 12 volt respectively). Also, if the
terminal works otherwise, the microprocessor should be regularly loading the keyboard status byte
into the UART for transmission. Check for Keyboard Write (KBD WR L) at E55-23 approximately
every 1 ms in response to KEYBOARD TBMT (E55-22) which should go high every 1.28 ms. Make
sure that serial data comes out from pin 25.

If data is coming from the keyboard but is not getting read by the microprocessor, check that data
reaches the serial input pin 20, and that each received word sets KEYBOARD DATA AVAILABLE
H. Check that the KEYBOARD DATA AVAILABLE H interrupt signal reaches the Interrupt Vector
Latch E41-2 and the microprocessor through E23-8. Finally, in response to the interrupt, the microprocessor should strobe KBD RD L at ES5-4 and -18. KBD DATA AVAILABLE should go low.
5.6.3

Troubleshooting the Power Supply

The power supply has two basically different sections: one is low power control circuitry and the other
is highly stressed power components. The current limiting circuits are supposed to protect the supply
well enough to prevent fuse blowing in spite of short circuits, so if the fuse blows repeatedly there is
probably a major problem.

5-54

The power switching transistor Q7 and its companion D19 are the usual failure, because they are
subjected to the most stress in the circuit. When they fail, other components may also fail. Check D41,
R22, the input rectifier diodes, and the two thermistors. Heavy currents could cause the thermistors to
crack. Sources of stress include connecting the supply to 230 volts when set to 115 volts, and shorting
of any transformer secondary. If the fuse blows but Q7 is okay, check C9, C14, the input rectifiers (the
two connected to the thermistors are the ones used in 115 volt operation), R19, and R20.

If Q7 repeatedly blows, the control circuit may be driving it incorrectly. Lift one side of R22 to shut off
the power circuit and examine the control circuit. (The absence of voltage at the output causes the
control circuits to produce maximum pulse widths, and the 12 volt startup supply’s regulator Z2 gets
hot from having to provide continuous output. But it is safe.) Look for a strong pulse on Q2’s collector, a ramp on Q5’s collector, a squarewave on Q1’s collector, a negative going pulse on pin 2 of E3
and a 12-13 microseconds squarewave on pin 3. (Refer to Figure 4-9-3, Power Supply Timing Diagram, in Chapter 4.)

The -12 and -23 volt supplies are individually current-limited; the —12 by its three terminal regulator’s
self-protection, and the -23 by a 10 watt resistor in series. The +5 and +12 volt supplies shut down the
entire supply if either supply’s current limiter is triggered. Check for shorts by checking the voltages
across R37, R44, and R45. If there are no shorts and the supply does not turn on, and startup voltage
(10.8 volts at the banded end of D25) is present, lift one side of D10. This diode carries the SHUTDOWN L signal from the current limiters to pin 9 of the 3524 control chip. This isolates the problem
to the comparators (E1). Check the comparators by measuring their inputs: for the +12 circuit, measure the input with respect to the inboard side of series resistor R37; for the +35 circuit, measure with
respect to the inboard side of R44 and R45. Pin 5 should be positive with respect to pin 6, and pin 3
should be positive with respect to pin 2.
The slow turn-on circuit might also keep the supply off. Lift D39 to disconnect it and use an autotransformer to bring the supply up gradually.

If there are oscillations or instability in the +5 volt control loop, check C31 and L2, C17, R31, and
R30. If there are oscillations in the +12 volt control loop, check C26, L1, R4, C1, R5. Excess sensitivity in the current limit circuits can also cause apparent output instability. There is some interaction
in the operation of the supply because the +5 volt supply must deliver at least its minimumm current
for the +12 volt supply to be able to meet its regulation specification. Therefore the supply should not
be operated without some load.
5.6.4

Troubleshooting the CRT Monitor
Most monitor problems are due to blown horizontal output transistors and diodes. These components
are the most stressed in the circuit. Listen to the monitor when checking it: the only normal sound is a
slight 15 kHz whistle.

Other problems include a dark screen (with normal sounds), a horizontal line on the screen, and sync
problems (rolling or tearing horizontally or vertically). If the screen is dark, turn up the brightness
control on the monitor board, press SET-UP, and bring the intensity to maximum with the cursor up
key. If there is a faint display or no display, check the horizontal drive operation, check the CRT
voltages and filament, and check the video output from the terminal controller. The high voltage is
probably okay if the horizontal frequency sound from the flyback is normal. The voltages to check
then are the control, focus, and screen grid biases.
A horizontal line on the screen indicates a failure in the vertical oscillator.

5-55

For rolling or tearing, check the horizontal and vertical drive signals coming from the terminal controller and be sure that these signals reach the monitor board. (On the Ball monitor board the vertical
hold control should be properly adjusted to ensure good lockup to the drive signal.)
5.6.5

Troubleshooting the Options
See Chapter 6.

5-56

CHAPTER 6

OPTIONS

6.1

SET-UP PROCEDURES FOR VT100 SERIES OPTIONS

6.1.1

VT100-WA and VT100-WB SET-UP
|
The VT100-WA and VT100-WB terminals have the same SET-UP features as the VT100. The only

difference between the terminals is the configuration of some of the features. Figures 6-1 and 6-2
summarize the SET-UP B configuration for the VT100-WA and VT100-WB terminals. SET-UP A is
the same as the VT100.

6.1.2

VTI105 SET-UP
The VT105 SET-UP is the same as the VT100 SET-UP. See Chapter 2 for

SET-UP.

a description of the VT 100

6.1.3
VTI132 SET-UP
The VT132 SET-UP is similar to the VT100 SET-UP in many ofthe features

and operations. However,
there are differences between the two terminals. This section will discuss these
differences.

6.1.3.1

VT132 SET-UP A - SET-UP A in the VT132 is the same as SET-UP A
in the VT100. See
Chapter 2 for more information.

JUMP
———SCROLL {10 =e

AUTOREPEA {10 =— OFF
ON
T

——

SCREEN {o = DARK BACKGROUND
1

OFF
{10 =- ON

(O = OFF

! =ON

INTERLA {1 = ON

0 = UNDERLINE

2[ElIem

WRAP AROUN

— NEW LINE

= LIGHT BACKGROUND

URSOR {1 = BLOCK

CUR

(SHIFTED) {10=~ =

[0=OFF

(USE WITH GRAPHICS)
3

I EEHE)

[e)

AUTO XON XOFF {? - SLF

(OPTIONAL

FOR CUSTOM
DISPLAY

FUNCTIONS)

g{IIl.I3

I POWER {? = gg ::

T SPEED[FZec) ' R SPEED[Tes0)

— BITS PER CHAR. {? Zaos

T ANSINVTS2 {? e

| PARITY {(1) - 8:F

L KEYCLICK {? - &ZF

MARGIN BELL {? Con

PARITY SENSE {? o0
MA-4570

Figure 6-1 VT100-WA SET-UP Summary

6-1

——scrou {02 Jowe
1

= SMOOTH

— AUTOREPEAT {10 =_ OFF
on

— CURSOR

1 [I1Ioe

smirreo) {07
——

{1 = BLOCK

0 = UNDERLINE

2[e[

WRAP
AROUND {10 =— OFF
oN
WRAP AROU

INTERLACE

3[1Tello)

(USE WITH GRAPHICS)

l‘ UTO XON X0 {10 =— OFF
oN
AUT

{1 = ON

0 = OFF

4 [o]of1T1

N XOFF

L ANSI/VT52 {10 =— VT52
ANSI

(OPTIONAL
DISPLAY

FOR CUSTOM
FUNCTIONS)
{1173

| POWER {10 =— 6050 HyHz

TSPEED[9222]

R SPEED[%¢22]

L BITS PER CHAR. {10 —= 78 BITS
BITS

l__ PARITY {10 =_ OFF
oN

OFF
L_ EYCLIC {1O =— ON
KEYCLICK

MARGIN BELL {10 =— OFF
oN

PARITY SENSE {10 =— ODD
EVEN
MA-4571

Figure 6-2 VT100-WB SET-UP Summary

6.1.3.2 VTI132 SET-UP B - SET-UP B in the VT 132 is different from SET-UP B in the VT100. In the
VT132 the display has a presentation similar to Figure 6-3. Figure 6-4 summarizes the presentation.
6.1.3.3 VTI132 SET-UP C - The VT132 contains a third SET-UP presentation called SET-UP C. In
SET-UP C the features normally associated with the editing functions are selected. SET-UP C mode
may only be entered from SET-UP B mode. To enter SET-UP C from SET-UP B, press the 5 key on
the main keyboard. The display has a presentation similar to Figure 6-5. Figure 6-6 summarizes the
SET-UP C presentation.

6.1.3.4 Changing a VT132 SET-UP Feature - Table 6-1 summarizes the SET-UP features, indicates
the SET-UP mode required to change the feature, and shows the key used to change the feature.
6.1.3.5

Setting the VT132 Answerback Message — Setting the answerback message in the VT 132 s the

same as in the VT100. See Chapter 2.

6-2

SET-UP
B
-

(rlmmw

MA-3575

Figure 6-3 VT132 SET-UP-B Presentation

SCRO LL {10== JUMP
SMOOTH

[#£]...
| SHIFT

AUTOREPEAT( 0=
OFF
1=ON

WRAP AROUND{ 0= OFF

L3 |7

0=#

ED){1 = £

1=ON

—— SCREEN {1 - LIGHT BACKGROUND
0= DARK BACKGROUND

cu RSOR{?f SNOERHINE
=

NEW LINE {1 - ON

(OPTIONAL

INTERLACE { 2” on

DISPLAY

0= OFF
]

FOR CUSTOM

FUNCTIONS)

(USE WITH GRAPHICS)

R T

AUTO XON XOFF{10=OFF
_on
b

———

|P=|

Ll o 2l d

|T=|

|R=|

= 60 Hz
POWER {10 oot

ANSI/VT52{ '~ (28

0=VT52

——

OFF
KEYCLICK ?ng

LOCAL EC 0{1 Zon
H

0=OFF

L——wps. TERMINAL

MARGIN BELL{ 0= OFF

RECEIVE PARITY { 0= IGNORE

1=0ON

1 = CHECK

MA-3576

Figure 6-4 VT132 SET-UP-B Summary

6-3

SET-UP C

AJEE

COBR

D K

/
MA-3574

Figure 6-5 VT 132 SET-UP-C Presentation

PROTECTED | 1=0ON

EDIT KEY { 1= IMMEDIATE
CHAR'SENT{1 =ALL
J—SP‘ COMPRES { 1=0N

PROTECTED{1 = ON
PROTECTED{1 = ON
PROTECTED{ 1=0ON

_UNDERLINE [ 0=0OFF

0= DEFER

0= UNPRO

_____BLINK

0= OFF

REVERSE

0= OFF

BOLD

EDIT MODE{10=OFF
_ ON

LTRANSN”T O0=DEFER
1 = IMMED.
TRANSMIT

| 0=OFF

[ 0=NONE

TERM.CHAR. | 1=FF

LPRlNT

EXTENT

OiSCROLL REG.

1=FULL SCREEN

0= NONE

TERM.CHAR. | 1=FF

ERASURE [ 0= UNPRO

MODE

TRANSMIT

EXTENT

0 0 PARTIALPAGE
0

PAGE

LINE

NORMAL

1=ALL

{ 0=-OFF

PROTECTED | 1=ON

Figure 6-6 VT132 SET-UP-C Summary

6-4

Table 6-1 VT132 SET-UP Feature Change Summary
Key To

SET-UP Mode

ANSI/VTS52
Answerback message
Auto repeat
Auto XON/XOFF
Blink protected

OWITW

Bold protected
Chars per line
Chars sent

OTOP>O

Change
Feature

Feature

pwEOHO

Changed In

Transmit
Transmit extent

®)

Underline protected
Wraparound

#C
,
3 | (shifted)

Transmit speed
Transmit term char

6
6

S HIFT/P (See 6.1.3.6)
cc NN
Q.

AN
O NSO

6-5

|F'S)

Tabs

Reverse protected
Screen background
Screen brightness
Scroll
Space compression

jas]

Receive parity
Receive speed

6
4

Print extent
Print term char

o We))

Power

o))

Margin bell
New line
Normal protected
Parity

Local echo

wOAOWEI®

Line/local

mxTOOW

Keyclick

ool

Interlace

Y 4

Erasure mode

Edit mode

6
6

OWOO»

Cursor
Edit key mode

SHIFT/A, 20 CHARS

6.1.3.6

Setting the VT 132 Transmit Parity - Set the terminal parity by performing the following steps:

Place the terminal in SET-UP B.

Press the SHIFT and P keys at the same time. The terminal then steps through the preset
bits per character/parity combinations. Each time the key combination is pressed the feature setting changes. The feature settings are as follows.
7M
7S
70
TE
TN

7 bits per character/mark parity
7 bits per character/space parity
7 bits per character/odd parity
7 bits per character/even parity
7 bits per character/no parity

8E
80
8N

8 bits per character/even parity
8 bits per character/odd parity
8 bits per character/no parity

6.1.3.7 Saving VT132 SET-UP Features - Saving the SET-UP features in the VT 132 is the same as in
the VT100. See Chapter 2.

6.1.3.8

Recalling VT132 SET-UP Features — Recalling the SET-UP features in the VT 132 is the same

as in the VT100. See Chapter 2.

6.1.3.9 VTI132 Default Feature Settings - The VT132 contains two default configurations for the
SET-UP features. The first default configuration sets only the tabs. The second default configuration is
a general default and all feature settings including the tabs are reset. The default settings are contained
in the terminal ROM. Figures 6-7 and 6-8 summarize the SET-UP B and SET-UP C default conditions.

6.1.3.10
1.

VT132 Tab Default - Use the following procedure to invoke the tab default.
Place the terminal in SET-UP A.

Press the SHIFT and T keys at the same time. The tab settings clear and new tab settings
appear every eighth character position.

6.1.3.11

VT132 General Default - Use the following procedure to invoke the general default condi-

tion.

Place the terminal in SET-UP mode.

Press the SHIFT and D keys at the same time. The screen clears and after a brief time the
terminal returns to SET-UP A.

6.1.3.12

Resetting the VT132 - Resetting the VT132 is the same as resetting the VT100. See Chapter

6.2

ADVANCED VIDEO OPTION

The advanced video option (AVO) provides the extra memory required for the VT100 to display 24
132-character lines, an extra 4 bits of memory per character for character attributes, plus space for
extra program ROM. Additional hardware in the AVO are the address decoders for memory expansion, and the 4-bit wide set of character-clocked latches for the attribute data. Refer to the video
processor functional diagram (Figure 4-6-3) to see how the AVO functions with the basic video circuitry.

6-6

SCROLL = SMOOTH

[#3*“' I(SH”:TED) -

AUTOREPEAT = ON

WRAP AROUND = OFF

— SCRE EN = DARK BACKGROUND

= OFF
— NEW LINE

(OPTIONAL
DISPLAY

CURSOR = BLOCK

INTERLACE = OFF

FOR CUSTOM

FUNCTIONS)

11011

2101111

3]0{0{0]0

Vo0

41110100

50 010,0101P=7S
T=9600 R =9600
Lol d ol d

AUTO XON XOFF =ON

POWER =60 Hz

——— ANS|/VT52 = ANSI

——— LOCAL ECHO = OFF

KEYCLICK = ON

L—— RESERVED

MARGIN BELL
= OFF

RECEIVE PARITY
= CHECK
MA-3563

Figure 6-7 VT132 SET-UP-B Default Summary

EDIT MODE = OFF

BOLD PROTECTED = OFF

EDIT KEY = IMMEDIATE

——CHAR. SENT =ALL

UNDERLINE PROTECTED =OFF

—— BLINK PROTECTED = OFF

l—- SP. COMPRESS = OFF

Alo[1]1]o0

—

[—REVERSE PROTECTED = OFF

Bloj1]1]1

clojolo}o

plof1]1]1

LTRANSMIT = IMMEDIATE
TRANS TERM CHAR. = FF

}TRANSMIT EXTENT = PAGE

I— PRINT EXTENT=FULL SCREEN
L

PRINT TERM. CHAR.=FF

L—ERASURE MODE=ALL
NORMAL PROTECTED = OFF
MA-3564

Figure 6-8 VT132 SET-UP-C Default Summary

6.2.1

Advanced Video Option Installation

Use the following procedure to install the advanced video option.
1.

Remove the terminal access cover.

Remove the terminal controller board.
Place the terminal controller board on a flat surface with the component side up.

Locate the four mounting holes drilled in the terminal controller board; mount a standoff
in
each. (Figure 6-9).

Grasp the advanced video board by the edges and carefully align the connector pins with the
connector on the terminal controller board. Gently but firmly mount the advanced video
board onto the terminal controller board.
Reinstall the terminal controller board. The terminal controller board must be inserted into
the leftmost slot in the card cage.
7.

Reinstall all cables removed.

Reinstall the access cover.

6.2.2

Advanced Video Option Checkout

Use the following procedure to check out the operation of the advanced video option.
1.

Turn the terminal power on and verify that no error was detected during the power-up self
test.

Press the SET-UP key. The words “SET-UP A’ should blink in boldface, the words “TO
EXIT PRESS SET-UP” should be underlined, and the ruler should contain alternating
normal and reverse video fields.

Place the terminal in 132-column mode and then in LOCAL mode.
Exit SET-UP and type the following sequence.
ESC < ESC #8

The screen should now display 24 lines X 132 columns.

STANDOFF
COMPONENT SIDE

OF ADVANCED

{!\

VIDEO BOARD

COMPONENT
SIDE OF
TERMINAL

CONTROLLER

DETAIL

ADVANCED

TERMINAL

VIDEO

CONTROLLER

BOARD

J1 ADVANCE

STANDOFFS (4)

BOARD

VIDEO
CONNECTOR

]

I"]

i
B

J2 GRAPHICS
CONNECTOR

J5 20mA
CURRENT LOOP
CONNECTOR

—

J3 STP

/CONNECTOR

‘:‘]/J

J4 EIA

COMMUNICATIONS

CONNECTOR

J8 VIDEO IN

CONNECTOR

J9 VIDEO OUT
CONNECTOR

J7 KEYBOARD

—

CONNECTOR
MA-1995

Figure 6-9 Advanced Video Option Installation

6-9

6.2.3
Program Memory Expansion
Basic program memory resides on the basic video board and may be patched in any or all of its 2K seg-

ments, or it may be overlayed by one 8K X 8 ROM on the advanced video board as follows.

Patch

Addr

ROM

Jumpers

PROM

(Hex)

Type

Used

Loc

IC Type*

0000-07FF

ROMA

E19

Intel 2716 or 2316E

0800-OFFF

ROMB

E17

Intel 2716 or 2316E

1000-17FF
1800-1FFFT¥

ROMC
ROMD

W3
W4, W8,

E13
ES8

Intel 2716
or 2316E
Intel 2716 or 2316E

W11,W14

Overlay
Addr
(Hex)
0000-1FFF

ROM

Jumpers

ROM

Type

Used

ROMSA,
B,C.D

W1,W2, W3
W4,
W5 W10,
W12,W13

Loc
E8

IC Type*
Signetics 2664

Program memory can be expanded by up to 14K bytes, using one 8K X 8 ROM and up to three 2K X 8
EPROMs, provided that no 2K X 8 patches were implemented. ROMs may both patch and expand but
each socket may either patch the address range given above or expand in the range given below but not
both.
Expansion
Expansion

Program

Addr
(Hex)
8000-87FF
8800-8FFF
9000-97FF

ROM
Type
2K X 8
2K X 8
2K X 8

Jumpers
Used
—
—
—

Memory
Loc
E19
E17
El13

Intel 2716
or 2316E

98FF-9FFFT
A000-BFFF%

2K X 8
8K X 8

W38,11,14
W6,10,12,13

ES8
E&

Intel 2716 or 2316E
Signetics 2664

IC Type*

Intel 2716 or 2316E
Intel 2716 0or 2316E

Or for addressing convenience use the following range.
Expansion

Expansion
Addr

Program
Memory

ROM
Type

Jumpers

(Hex)

Used

Loc

IC Type*

8000-9FFF%

8K X 8

W7,10,12,13

Signetics 2664

A000-A7FF

2K X 8

—

E19

Intel 2716 or 2316E

A8000-AFFF

2K X 8

—

E17

Intel 2716 or 2316E

B000-B7FF
B800-BFFFt

2K X 8
2K X 8

—
~

El13
E8

Intel 2716 or 2316E
Intel 2716 or 2316E

* May be used only if 8K overlay or 8K expansion has not been implemented.
T These parts must have an access time of 350 ns maximum.

1 If basic ROM has been overlayed by 8K X 8 RAM, program memory cannot be expanded by
another 8K X 8, but by only three of the 2K X 8s as shown above.

6-10

In all configurations, either W5, W6, or W7 must be installed, if none of these jumpers is required by the
above specification. Install one that enables the 8K ROM in an unused address space.
Jumper 15 or 16 can be used in place of jumper 10 or 9 respectively if a high asserted chip select is desired
on an 8K ROM.
6.2.4
Alternate Character Set
If the AVO is present and an alternate character ROM is installed on the terminal controller, an alternate
character set may be selected on a character by character basis. An additional 127 characters may be
provided through the alternate character set. If the AVO is installed without the alternate character
ROM, any character cell in which the alternate set is selected appears white (black if reverse video). See

Appendix A (SCS) for selection of alternate characters.
6.2.4.1

Alternate ROM Description

Size: 2048 words X 8 bits

Speed: 300 ns access time if 132 column operation is desired; 550 ns access time is sufficient
for 80 columns only.

Pin-out (Intel 2316E equivalent)
Pin

No.

Name

Use for Alternate Character ROM

Character address 3

Character address 2

Character address 1

Character address 0

Scan address 3

Scan address 2

7
8

Al
AQ

Scan address 1
Scan address 0

Fill bit

Rightmost character bit/character data 1

Character data 2

12
13

GND
D3

Ground
Character data 3

Character data 4

Characterdata 5

Characterdata 6

Leftmost character bit /character data 7

18
19

CS2
Al0

Chip select — asserted low
Character address 6

CSl1

Chip select — asserted low

CS3

Chipselect — asserted low (Paragraph

22
23

A9
A8

6.2.4.2 below)
Character address 5
Character address 4

Vcce

+ S volts

6-11

6.2.4.2

Character ROM Programming Instructions

Chip selects must always be asserted low.

(To allow use of pin compatible UV erasable PROMs, pin 21 may be tied to +5 V by removing
W4 and inserting WS5. The speed restrictions listed above still apply.)

A high coming from a character data pin produces a dot on the screen. A high from the fill bit
causes the righthand space, between the character in which the bit is asserted and the following character, to be filled on the scan(s) for which the bit is asserted. Horizontal spaces in a
character which are only one dot wide are filled by the dot stretcher.
The following scan and character addresses are in hex.

Scan addresses
Scan
Address
F
0

6.2.5

Character Scan Number
(Figure 4-6-17)
1
Normally blank in VT100 main ROM
2
Top of normal uppercase character

6
7
8
9-E

8
9
10

Bottom of normal uppercase character
Normal descenders (underline scan)
Normal descenders
Not displayed

Character address 7FH is not displayed and should be left blank. Character addresses
20H-7EH are accessed by ASCII codes 20H-7EH respectively when the VT100 character set
is set to “alternate character ROM” (Appendix A, SCS). Character addresses OH-1FH are
accessed by ASCII codes SRH-7EH respectively, and character addresses 20H-5EH respectively, when the VT 100 character set is set to “alternate special graphics” (Appendix A, SCS).
AVO Technical Description

6.2.5.1 Extended Character and Attribute Memory - The complete address and data buses from the
microprocessor enter the: AVO through the circuit board connector. Bits A0O through A09 directly
access 1K of 8-bit RAM (E18 and E20) when A10, A11, and SEL 8-12K enable the RAM chip selects.
The Select Attribute RAM (SEL ATT RAM) signal, decoded on the basic video board, enables the 4K
X 4 memory (E2, E7, E10, E14) for writing and reading attributes. When read by the microprocessor,
these 4K words appear in address space 3000H to 3FFFH and the four bits of each word appear on
DO0-D3. The attribute bits are read and written by the microprocessor through buffer E11 which 1s
configured to drive the four bits in one direction or the other. One half of E9 and a pull-up resistor
form an OR-gate so that data is output from the board when MEM RD and SEL ATT RAM are both
asserted. During a DMA by the video processor, the four attribute bits are read in parallel with the
seven character address bits and one attribute bit from the memory on the terminal controller. This 1s
accomplished by enabling the RAM outputs to the attribute latches whenever an address in the range
of 2000H through 2FFFH is accessed during a DMA.

6-12

6.2.5.2 Character Attribute Latches - The attributes have their own set of character-clocked latches
to provide complete synchronization of attribute and character data in the video processor. At the
assertion of Hold Request and DMA Enable, data pass from the attribute RAM to the input of latch
E5. As with the characters in the character latches the attributes shift through DI1-4 of ES, then
through E9 to the attributes line buffer E4 for storage, and again through D5-8 of ES to the attribute
inputs to the video processor on the basic video board. The attributes line buffer (E4) is addressed by
the same LBA signals as the line buffer on the basic video board.

6.2.5.3 Program ROM Decoding - The AVO has sockets for four 2K or one 8K and three 2K ROMs.
The address blocks that these ROMs can operate in can be selected with wire jumpers (or switches in
later models) on the AVO board. Flexible decoders can address the ROMs as extended program
memory or a ROM can overlay an existing block of program. When existing memory is being overlayed or memory above 4000 H is being addressed, the Memory Disable signal is asserted to turn off
memory on the basic video board.
6.2.6

Troubleshooting the AVO
This is mostly an extension of the character latches in the video processor. Problems in it can be
suspected if character attributes will not work (check with the SET-UP Screen Test). Also, a portion of
the screen RAM resides on the AVO. Problems are evident if the screen is full in 132 column mode.
(Type ESC # 8 in local mode to get the “E” test pattern.) Check the power connections, memory
decoders and the memory disable control line.

Self test tests the AVO RAM, so if errors are suspected in the AVO but it passed self test, the problem
may be on the attribute latch (video processor) side of the AVR RAM control circuits.
6.3

20 mA CURRENT LOOP ADAPTER

The VT100 current loop adapter converts the Electronic Industries Association (EIA) standard serial
voltage input and output from the basic video board to 20 milliamp current signals. Both receiver and

transmitter can be separately switched to operate either passively or actively.
6.3.1
20 mA Current Loop Option Installation
Use the following procedure to install the 20 mA Current Loop Option:
].

Remove the terminal access cover.

On the new terminal access cover containing the 20 mA current loop card set the TRANS

switch to the NORMAL position (Figure 6-10). (If the terminal must provide current on the
receiver line set the switch to the ACT position.)
3.

Set the REC switch to the NORMAL position (Figure 6-10). (If the terminal must provide
current on the receive line set the switch to the ACT position.)

Connect PS5 to J5 on the terminal controller board (Figure 6-9).

Install the terminal access cover containing the 20 mA current loop option in place of the old
access cover.

Connect the communications line to the Mate-N-Lok connector on the bottom of the access
cover.

Perform the 20 mA current loop option checkout.

Q\CAPTIVE

SCREWS (4)

ACCESS

COVER

20mA

CURRENT
____—L0OP

BOARD

TRANSMIT
LINE

TRANS
|

REC

—

\\I

/ SWITCH

___—

RECEIVE

LINE
SWITCH

C\Y//7y/a
0330

20mA

COMMUNICATIONS

)
_——CONNECTOR

MA-1996

'Figure 6-10 20 mA Current Loop Option
6.3.2 Configurations
'
In most current loop applications, the VT 100 is connected in a passive configuration - that is, current

is supplied to the VT100. In this mode, the transmitter and receiver are both passive, both optically
isolated, and the transmitter goes to the mark state when power is turned off.

Conversion from active to passive mode (or vice versa) for either transmit or receive side is switchselectable.
In active mode either the transmitter, or the receiver, or both may be connected so that the VT 100
sources the 20 mA of current. In active mode, isolation is not present, and the transmitter goes to the
space state when power to the VT100 is turned off.

6-14

6.3.3

20 mA Current Loop Option Checkout

The VT100 contains an internal test called the data loopback test. In the data loopback test the VT 100
transmit and receive lines are connected to each other via a special external connector. A predefined set
of characters are then transmitted. The terminal receives the characters and compares them to the
characters transmitted. If the characters do not match an error is then flagged.

Use the following procedure to check out the operation of the 20 mA current loop option.
1.

Disconnect the terminal from the communications line.

Remove the terminal access cover containing the 20 mA current loopback board and place

both switches in the NORMAL position. Reinstall the access cover.

Connect the 20 mA loopback connector (PN 70-15503-00) to the Mate-N-Lok connector
mounted to the bottom of the access cover.

Place the terminal in ANSI-compatible mode (in SET-UP B group 2 switch 3 equals a 1).

Type ESC [2;2y to perform the data loopback test.

When the test is performed the screen clears and the message “WAIT” is displayed in the
upper-left corner of the screen. The entire test takes about six seconds to run.

A loopback error is shown by ‘8" being displayed in the upper-left corner of the screen. If
an error is detected, check the 20 mA board connectors and switch settings and then repeat
step J.

Once the test is complete return the 20 mA current loop board switches to the original
positions, remove the loopback connector, replace the access cover, and reconnect the terminal to the communications line.
NOTE
The terminal is designed to use either 20 mA or EIA
communications. If EIA is used on a terminal con-

taining the 20 mA option, the cable connecting the 20
mA option board to the terminal controller board at
J5 must be disconnected.
6.3.4

Current Loop Principles

The current loop system was developed for teletypewriter communications between remotely located
stations. The 20 mA current was intended to operate the selector electromagnet which decodes data in
teleprinters. All teletypewriters on a circuit were in series so that any station could signal all the other
stations simultaneously by passing and interrupting the current through all stations’ selector magnets.
Today, decoding of the current signal is performed electronically, rather than mechanically, but the
good noise immunity of the system has kept it around as a reliable way to run lengthy in-house
terminal drops at low cost. The states of the interface line are defined in Figure 6-11.
6.3.4.1

Current Loop Adapter Description

6.3.4.1.1 Transmitter Side - An EIA to TTL level converter (E3) inverts the VT 100 output signal, but
a second stage reinverts it. The TTL signal switches a pair of paralleled open-collector drivers that
drive the LED inside an opto-coupler. Resistor R11 limits the LED current. The LED output controls
the conductance of the phototransistor inside the opto-coupler. The transistor’s base is tied to its
emitter by R13 and its base is tied to its collector by D5 to improve its switching speed.

6-15

0-2mA=0FF=SPACE=0

18 - 50 mA = ON MARK =1

18 mAM
\

MARK

50 mA

10 mA

:‘; TR
MA-4277

Figure 6-11 Interface States

When the phototransistor is conducting, the base drive for Q3 is diverted and Q3 and Q4 are cut off to

put the transmitter in the space state. The only current that can flow in the space state passes through

D3, which is a constant current diode rated for | mA. When the phototransistor is cut off, D3 provides
base drive to Q3 and forces the transmitter to the mark state. Use of the constant current diode D3
allows sufficient base drive to Q3 to keep the transmitter in the mark state when the phototransistor is
cut off or when power is removed from the VT100. But D3 still limits the current through the transmitter to less than 2 mA even with 50 volts across the circuit.

In passive mode the transmitter can control the flow of current from an external current source. In
active mode the transmitter is placed in series with current supplied from the +5 volt and -12 volt
power supplies and limited by series resistance.
6.3.4.1.2 Receiver Side - Passive: The optional capacitor on the input gives line transient immunity.
The LED in opto-coupler E1 accepts current from a remote source limited by R2 and Q1. To ensure
proper recognition of the off state, R1 draws 3 mA to bypass low level currents around the LED. If the
line current rises to make the voltage drop across R2 greater than 0.6 volts, transistor QI turns on to
shunt excess current around the LED. Besides protecting the LED, this also improves speed by reducing saturation of the LED and transistor. D1 protects the circuit from reverse connection of the signal
line.

Active: With switch SW2 in the up position, the adapter provides power for the line: +5 volts and -12
volts through similar resistors R8 and R9. The remote device passively switches current to activate the
circuit.

The phototransistor in the opto-coupler controls the base current to Q2. RS speeds up Q2’s turn-off by
pulling the base down faster. C1 speeds Q2 turn-on. R3 prevents the phototransistor from saturating
by allowing the base and emitter voltages to rise until excess base charge can be removed by conduction through R4.
The output is pseudo EIA (RS-232) because it assumes that a particular receiver device is being used
which happens to accept a 0 as a mark. The normal RS-232-C specification calls for +6 = space and -6
= mark. D4 shunts —12 in case someone connects the EIA signal to the exposed connector while the
current loop is installed. It protects E2 pin 3. R7 pulls up to give high drive to the 1489EIA receiver TTL converter on the basic video board.

6-16

6.3.5
Interface Signals
The currrent loop option interfaces to external communication equipment through an 8-pin Mate-N-Lok
connector as described below.

Description

No.

Signal Name

Passive Mode

Negative Test

V-with a series resistance of 480 ohms

Voltage

+ 5%.

Transmit negative

Current flows away
from this terminal.

(T-)

Active Mode

Current flows into
this terminal which

1s connected to Vvia a series

resistance Rs.
3

Receive negative

Current flows away
from this terminal.

Current flows into
this terminal.

Current flows away
from this terminal.
The equivalent
voltage source is
(V4+)—Vdwitha
series resistance
Rs.

Receive positive

Current flows into

Current flows away

(R+)

this terminal.

from this terminal

(R-)
4

(Not used)

Transmit positive

(T+)

6
7

(Not used)

which is connected

to V+ via a series
resistance Rs.
8

Ground

V-

—12Vdc

45Vdc

RS
vd

6.3.6

Interface Specifications

5%
5%

330o0hms + 5%
Vmaximum

2.0

Transmitter

Min

Open circuit voltage
Voltage drop marking
Spacing current
Marking current

0.0
20

6-17

Max

50
2.0
2.0
50

Units
volts
volts
mA
mA

Receiver
Voltage drop marking
Spacing current

Min
—
15

Marking current

Max
2.3
3.0
50

Units
volts
mA
mA

6.3.7 Troubleshooting the Current Loop Adapter
Aside from incorrect setting of the normal (active) and passive selection switches and connector problems, malfunction is probably due to bad semiconductors.
6.4

VTI105 GRAPHICS PROCESSOR

This section describes the VT 105 waveform generator module, M7071. The M7071 complements the
VT100 alphanumeric terminal by adding graph drawing capabilities. Together they comprise the
VTI105 alphanumeric and graphic terminal. This section describes:
the graph module in a block diagram format
decoding the input
establishing mode of operation
phase lock loop timing
rectangular aspect ratio graph drawing field
square aspect ratio graph drawing field
loading the registers
loading graph memories
generating baselines
loading vertical and horizontal lines
generating strip charts
combining video out
6.4.1

Enabling Graphic Information

On initializing
the VT 105, the M7071 forces the GRAPHICS FLAG low so the VT100 terminal controller module recognizes that the graphics option is installed.

To enter the graph drawing mode, an escape sequence ESC 1 is needed. The terminal remains in this
mode until ESC 2 is received. In this mode, graphics data is passed to the M7071 on parallel data lines.
When data is passed, the GRAPHICS FLAG goes high and stays high until the data is stored in the
static random access memories (RAMs). This signal is sensed by the VT 100 terminal controller, and
does not pass another character to the M7071 until this signal goes low.
The M7071 also uses the following signals from the VT100.

DO 00 H - DO 06 H - The parallel 7-bit graphic information in the form of a character to the M7071.
DO 07 H - This signal is used by the VT105 for hard copy.

RESET H - The M7071 uses this signal on power up to initialize its registers. Pressing the RESET key
during SET-UP mode also generates this signal.

HORIZ BLK H - Defines the horizontal blank time of 11.4 us. The horizontal active time is 52.1 us;
the total period is then 63.5 us.

VERT BLK L - Vertical blank time is 1.016 ms. Vertical active time is 15.24 ms for a total period of
16.256 ms.

6-18

WR GRAPHICS L - A pulse passed to the M7071 to strobe the parallel data (DO 00 H — DO 06 H)
into the input latch.
GRAPHICS 1 IN L and GRAPHICS 2 IN L - The video output from the M7071.
The following paragraphs provide a brief discussion of the waveform generator block diagram, Figure
6-12.

6.4.1.1 Writing Data to the Waveform Generator (block diagram discussion) — Data in the form of 7-bit
ASCII characters is received by the data input latch. The first character must be a control character to
give instructions to the waveform generator module as to where to place the next data information. Is
the next data to be loaded into the registers or into the graph memories? Is it horizontal line data or
vertical line data? The control character is loaded into a binary-to-decimal decoder that enables 1 of 10
load modes. (See Paragraph 6.4.1.3 to decode the input character.)

One of these modes is load enable register 0; another is load enable register 1. These two registers store
the information as to the type of graph desired (line graph, shaded graph, or strip chart) and the
desired graph features (horizontal lines, vertical lines, and graph markers). Both registers use either
one or two data characters to enable the desired graph features. The First Data flip-flop keeps track of
these two data characters. Two data characters form a data word.
The second data character following a load enable register | command enables the mode select logic.
Data bit 0 of this character determines the aspect ratio of the graph to be displayed on the video screen.
When this bit is ““1,”’ the square aspect ratio is enabled. This aspect ratio is a new feature of the VT 105
and uses all 240 scan lines on the terminal. When this bit is a *‘0,” the rectangular aspect ratio is
selected. This aspect ratio is compatible with previous DECgraphic video terminals (i.e., VT55) and
uses only 230 scan lines of the terminal for the graph display. This later aspect ratio is also enabled
during the power-up sequence of the terminal (by RESET H).
The outputs of the mode select logic go to a phase-lock-loop to establish the two timing signals necessary to set up the rectangular and square aspect ratios. These are 10.4 MHz and 12.4 MHz, respectively. The phase-lock-loop has a phase detector to monitor the horizontal blank signal from the
VT100 and divides the frequency of this signal by a set number for each aspect ratio.

Another function of the decoder is to select the memory into which the data is to be loaded. This may
be Graph 0 memory, Graph 1 memory, vertical line and graph marker memory, or horizontal line
memory. Data to these memories must always be in the form of two data characters (one data word).
A 5-bit data register holds the first character while waiting for the second. Then they are both parallel
loaded through a 2-line to 1-line multiplexer, becoming RAM DATA to the inputs of each of the
memories. The memory enabled to ““write” at this time is determined by the decoder. The load enable
signal from the decoder is synchronized by the First Data flip-flop and the Load X-Data multivibrator. One of the following signals is enabled to the memories.
WR GRAPHOL

WR GRAPH 1L
WR DATAL
WR HORIZ L

Data is then written into the appropriate memory, as shown in Figure 6-12.
Data for the shade lines (base lines) is loaded into Baseline O register and/or Baseline 1 register.

6-19

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Data for the starting X-address is loaded into the initial X-address counter. The final X-address
counter is loaded to this starting X-address at the end of the current scan (by the 512-bit counter). Data
for successive X-address positions in memory only require one control character. The final X-address
counter increments the position in memory for placing the new data.

When a strip chart is enabled (from register 0), the clear input to the final X-address counter is disabled. This counter does not reset to zero, but rather it follows the initial X-address counter. New data
increments the X-address and is added to the end of the graph. This new data is the last data to be read
from memory. Previous data is read one position earlier causing a shift in the video graph to the left.
6.4.1.2 Reading Data from the Waveform Generator (block diagram discussion) — As long as the terminal is in graph mode, the enabled graph data is read continuously from the waveform generator module. The Y-address down counter is initially preset to one of two values: 240 lines for the square aspect
ratio, or 230 lines for the rectangular aspect ratio. The output of this counter is enabled through the 2to-1 multiplexer, becoming RAM DATA to strobe the row address of the memories. As each scan
proceeds across each row, the X-address counter strobes the column address of the memories.
The output of each memory is strobed into a corresponding D-type data latch. This provides buffering,
as well as an input source for rewriting the data back into memory so it is not lost. The data from each
memory is sent to a respective 8-bit comparator where the data is compared to the Y-address (YO-Y7).
[f both inputs are high at the same time, a high output is sent to the video data latch to intensify that
position on the screen. If a histogram is enabled, all points below the graph position are also intensified. If a cursor (graph marker) is enabled, 16 points are intensified on the screen creating a short
vertical line on the graph at a specific graph point. If a shade line (base line) is enabled at a specific Yaddress: (1) all X-address positions on that line are intensified on the screen; and (2) all positions
between the graph data and the shade line are also intensified. If a vertical line is enabled at a specific
X-address, that X-address is intensified on each scan creating a vertical line on the screen.
All data is presented to the video data latch. At alternate times Histogram 0 and Histogram 1| data are
gated out. This allows two shaded graphs to be displayed on the screen and still be discernible in
overlapping areas. Graph markers, horizontal lines, and vertical lines are clocked to the output every

TIME (1) H pulse. This timing comes from the phase-lock-loop previously mentioned.
The blanking gates keep track of both horizontal and vertical blank times from the VT100 and create
the signal HORIZ + VERT H. This signal is used to clear the X-address counter and a 512-bit counter.
Every COUNT X 00 (1) H from this counter clock the window flip-flop at the proper time to gate the
video to the VT100 terminal controller. These signals are VIDEO H (GRAPHICS 1 IN L in the
VT100) and VIDEO 2 (GRAPHICS 2 IN L).
6.4.1.3
Decoding the Input - When the data received is one of the control characters listed in Table 62, bits 0-3 of the character are used to determine which control signal to enable. Only one set of control
characters is used for one M7071. The extended character set is primarily used for a second M7071
installed in the same terminal to enable up to four graphs or stripcharts. These bits are sent to a binaryto-decimal decoder, Figure 6-13, that enables only one of the outputs at a time.

The extended character set is reserved for future expansion. Current software does not support the
extended character set. Discussion in this chapter is limited to unit O to avoid confusion.
Data bit 4 is used to load X-data and select Graph 1.

Two ASCII characters are necessary to transmit a complete data word. Data bits 5 and 6 monitor these
data bits. The first flip-flop keeps track of the first and second data characters.

6-21

Data bit 7 (DO 07 H) forces the GRAPHICS FLAG high to halt further transmission from the VT 100
terminal controller while the video screen is being copied by a hard copy unit. Signal COPY L is sent to
the hard copy unit on TBI1. The hard copy unit must detect and hold this signal low while it copies the
screen.

Table 6-2 Control Characters

Octal

Unit 0

Unit 1

Ext

Octal

Char

Code

Enable Signal

Char

Code

@
A
B
C
D
H
I
J
K
L

100
101
102
103
104
110
111
112
113
114

Load Baseline
LD ENABLEOL
LD GRAPHOL

P
Q
R

LD CURSOROL
LD HORIZ L

S
T

LDXL

LD ENABLE 1L
LD GRAPHIL
LDCURSORIL
LD VERTL

Y
Z
|
\

120
121
122
123
124
130
131
132
133
134

6-22

GRAPHICS FLAG L

PREWRITE

FROM

VT100

DO 07 H

TB1

—

COPY L

WR GRAPHICS L1|>0

H
DB6

LD CONTROL L
e——

D—O

DB5 H

FIRST

DATA

F/F

LOAD

MODE
MV

)'-(ODAADT

LD MODE H

M-V

50ns

LD X DATA H

Al
»

100

TO LOAD X
ADDRESS

S?
UNIT1H

—O

—

DATA

AND

W3 O

WRITE

>0UNITO H—O0———0—
W2

LOGIC

D— LD VERTL

O— LD HORIZ L

DB4H —

D—

LDCUR1L

BINARY

[O—

LDCUROL

O— LD GRAPH 1L

DECIMALI\~

DECODER

| pGRAPHOL

FROM

DB2H —

INPUT

DB1H

LATCH

DBOH —— FLOPS

O— DXL

DB3H

(O—

DATA

—

D-TYPE

FLIP-

—

OD—

LD ENABLE 1L

D—

LD ENABLEOL

NOPL

REGISTERS

(LD BASELINE)
MA-4735

Figure 6-13 Decoding the Control Character

6-23

6.4.1.4

Selecting Mode of Operation — There are two formats or modes for setting up the display:
rectangular format and square format. The rectangular format uses a 10.4 MHz signal to display
graphic data on the video screen in an area 230 dots high by 512 dots wide, as shown in Figure 6-14.

The square format increases the rate of transmission to 12.4 MHz. The same graphic information is

displayed in a more compact area, as shown in Figure 6-15.

(X0, Y22910)

(X51110. Y22910!

10.9 CM

(43/8 IN)|]

230DOTS

512 DOTS

Y A

(X51110. YO

20.32 CM

[‘

(8 IN)

MA-4732

Figure 6-14 Rectangular Aspect Ratio Graph Drawing Field

(X511, Y239)

(X0, Y239)

]
[

240 DOTS

}

480 DOTS

11.5 CM

(4 5/8 IN)

:
|

le—ole

512 D0TS——M8M8M8M8

EIGHT

(X511, YO0

CHARACTERS-

15.2 CM

(6 IN)

16.5 CM

o0
N

7 CHARACTERS

|
-

(6.5 IN)
MA-4731

Figure 6-15 Square Aspect Ratio Graph Drawing Field

6-24

Rectangular Aspect Ratio — In the rectangular aspect ratio graph drawing field, (Figure 6-14) space is
provided in the left margin for one character. Under the graph field, there is space for one line of
characters. To set up the left margin, a delay is needed before starting the graph. Two signals (1.2 us
and 320 ns) are added together to create a 1.52 us delay after horizontal blank time. This time allows
space for one character in the left margin before starting the first X-address of the graph.
The horizontal line counter is initially loaded to 230 scan lines. Twenty-three lines of characters, each
having a 10 line scan cell, can be printed within the graph drawing field. A 24th character line can be
printed under the graph field.

Square Aspect Ratio — In the square aspect ratio graph drawing field, (Figure 6-15) additional delay
must be achieved before starting the first X-address. A 640 ns pulse is used to clock a counter loaded to
divide by 8. A 5.12 us delay is achieved before starting the graph centering the graph field on the
screen.

The square aspect ratio uses the full vertical screen area of 240 scan lines; 24 lines of alphanumeric data
can be placed on the graph field. Up to eight characters may be placed on the screen to the left of the
graph field; up to seven may be placed to the right of the graph field.

6.4.1.5 Decoding Field Selection — Selecting the field is accomplished by data bit 0 (DB 0) in the second
data character following a Load Enable Register 1 instruction. The first flip-flop, shown in Figure 6-16,
keeps track of the first and second data characters. The second data character enables FIRST (1) L
which clocks DB 0 into the VT 105 mode select flip-flop. If DB 0 is high, the square field is enabled. If DB
0 is low, the rectangular field is selected.

The signal RESET H (INIT L) from the VT100 terminal controller clears the mode select flip-flop and
also enables the rectangular field.

FIRST (1) L

TO PHASE

LOCK LOOP
& Y-ADDR COUNTER

FIRST[@

VT105 (1) H

EG’[’A

»iC

FLOP

O—

(0)

FROM

(SQUARE FORMAT)

VT105

(1)

(RECTANGULAR

CONTROL L

FORMAT)

DECODER | p ENABLE 1 L

RESET H
FROM.

INIT L

VT100
MA-4730

Figure 6-16 Selecting Mode of Operation

6-25

6.4.1.6

Phase Lock Loop Timing — A 10.4 MHzsignal and a 12.4 MHz signal are needed to achieve the

rectangular and square aspect ratio, respectively. A phase lock loop (Figure 6-17) is used to generate and
maintain these frequencies. The HORIZ BLK L signal from the VT 100 terminal controller is used at one
input to a phase detector. The phase detector monitors the output of the voltage controlled oscillator
(VCO) to detect any frequency drift. The output frequency is divided by the number N in a counter to
approximate the HORIZ BLK L input. The value for N is 662 for the rectangular aspect ratio and 800
for the square aspect ratio.

Should the frequency drift, the difference between the leading edge of the inputs to the phase detector is
presented as a voltage change to the VCO and either raises or lowers the output frequency to compensate
for the drift.

6.4.1.7

Establishing Desired Display — Sclecting the desired graph, shading the graph, single or dual

strip chart operation, and adding vertical and horizontal lines is initially stored in registers, shown in Figure 6-18. The signals LD ENABLE 0 L and LD ENABLE 1 L from the decoder enable register O and
register 1, respectively. The first data flip-flop monitors the characters to enable the proper register to

store the type of graph desired.
Loading Register 0 — The letter A, when typed on the keyboard or coded in a program, enables register O.
One or two data characters may follow this letter. The first data character is clocked into a D-type flipflop to determine the graphs or histograms desired (Figure 6-19). DB 0 H must be set to display the
graphic features enabled in register 0 and register 1; if 0, the graphic display is turned off.
A second data character may be used to set up baselines (shade lines) or strip charts (Figure 6-20). The
state of the signal BASELINE CTRL determines whether Baseline O or Baseline 1 is to be loaded. If low,
Baseline 0 may be loaded; if high, Baseline 1 may be loaded. See Paragraph 6.4.1.10 for more details on
baselines.

DB 3 H enables the signal STRIP H to allow Graph 0 or Graph 1 to be a strip chart. DB 4 H enables
STRIP H and DUAL STRIP H. Both signals are required to display both Graph 0 and Graph 1 as strip
charts. Refer to Paragraph 6.4.1.15 for more information on strip charts.

Loading Register 1 — The letter I produces the signal LD ENABLE 1 L to enable register 1. One or two
data characters may follow this letter. The first data character enables horizontal lines, vertical lines, and
graph markers, as shown in Figure 6-21.

A second data character following the letter I enables the desired field and the interactive graphics test
(Figure 6-22). The square field is established when data bit O is a one; the rectangular field is selected
when DB 0=0. The rectangular field is also selected during the initial power-up sequence of the terminal

by the signal RESET H (INIT L) from the VT100 terminal controller.
The interactive test is used to check the M7071 in LOCAL mode of operation. See Paragraph 6.4.2.

6-26

HORIZ

BLK L

—_—

EROM

\
PHASE

INTE:

VOLTAGE

VT105

(HhH

(N=800)
(1L

OSCILLATOR

—» +N

VT105

(N=662)

PHASE
LOOP

—

CLK

OUTPUT

C?R2UIT

LOCK

COUNTER

—*

v_DOTlME (H

TIME (1) L

TIME (1) H
D

COUNT
FROM

TIMEH

_/ TO

BLANKING

GATES

COUNT

ENABLE

CCE)RR'lrzL+

X ADDRESS

COUNTERS

VT105 (1) L
FROM MODE

43y

SELECT F/F

—a| DELAY

COUNTER|

VT105

SQUARE

(M H

+8
LD

1.2

_—j

320 NS
640 NS

RECTANGULAR

CcuP

—_—

VIDEO
DELAY TIME
DEO
HORIZBLK L

RECTANGULAR
MODE

SQUARE MODE

1525
o

fo-

—

e 5.12 u5 »]
MA-4734

Figure 6-17 Phase Lock Loop Timing

6-27

FIRST
(1) H

LD MODE H ey

ETTSX

[-OAD

DBE

CONTROL |LD CONTROL F/F
DB 5 GATES

L& CUR GRAPH 1

FIRST

> VERTICAL LINE

(0) H

Pfi

& HORIZ LINE

(2ND CHAR)

WR GRAPHICS L

LOAD

FROM

MODE
MV

vT100

50ns

- HISTOGRAM 1
gEG'STER >HISTOGRAM 0
>-GRAPH 1
L

»GRAPH 0

e
b8
DB

cLx

FROM

-»=D|SP

NPUT
LATCH

-—O

DB 4

TDB 0

STRIP

AND

DU AL
S TRIP

BASELINE [®STRIP

ENABLE

(3RD CHAR)|

{eBASELINE ENA 01
Ll
»BASELINE ENA 00
L»-BASELINE

CTRL (1) H

-—O

—

—0

CONTROL

HEX

et D-TYPE =i

ENABLE

[—

F/F

DECODER

B DATA

DATA

|\ p ENABLE 1 L

CHARACTER[TM®0-4 (1) H

LD ENABLE O L

BUFFER

TO X-ADDRESS
COUNTER,

—

(1ST CHAR) }—

FIRST (0) H

STATIC

MEMORIES,

)
>

2ND DATA CHARACTER DB0—3 H

AND BASELINE
REGISTERS
MA-4720

Figure 6-18 Loading the Registers

6-28

DB4H

—» REGISTER OFH—*

DB3H

—#

HISTOGRAM 1 (1) H

——»

HISTOGRAMO (1) H

DB2H

—®

—

GRAP
1 (1)
H
H

DB1H

—® CHARACTERF—

GRAPHO (1) H

DBOH

—

DISPLAY (1) H

FIRST

DATA

CLK

FIRST (1) H
LD CONTROL L

LD ENABLEOL

MA-4728

Figure 6-19 Register O (1st Data Character)

—*

DUALSTRIPH

]

DB4H

—| REGISTERO

DB3H

—p

DB2H

—»

DB1 H

___qCHARACTER___’

DBOH

—

STRIP H

SECOND
DATA

—

-—

CLK

BASELINE ENA 01 (1) H

BASELINE ENA 00 (1) H
BASELINE CTRL (1) H

FIRST (1) L
LD CONTROL L

LD ENABLEOL

MA-4722

Figure 6-20 Register 0 (2nd Data Character)

DB 3 H— REGISTER 1 —— CUR GRAPHO (1) H
DB 2 H——

DB1H—

FIRST

DATA

—— CUR GRAPH 1 (1) H

—® VERTICAL LINE (1) H

DBOH — CHARACTER — HORIZ LINE (0) H

CLK
LD CONTROL L{j

LD ENABLE 1 L O
FIRST (1) H

q
MA-4723

Figure 6-21 Register 1 (1st Data Character)

6-29

VT105 (1) H
DBOH—»

—» (SQUARE)

D-TYPE

DB 5 H—O

DB6 L—O

LD MODE —O

FLIP-

FLOP

FIRST (1) L

LD CONTROL
LD ENABLE 1L

TO PHASE LOCK LOOP

o VT105 (1) L

(RECTANGULAR)

CONTROL

INIT L

ENA H

—>

Y
DUAL

— TEST (1) H

STABLE
MULTIVIBRATOR

NOTE:
DB 2 - DB 4 NOT USED
MA-4724

Figure 6-22 Register 1 (2nd Data Character)

6.4.1.8 Loading X-Address Information — In order to load the horizontal address of a dot or line, two
data characters must be transmitted. The first character contains the lower five bits of the binary X-address and is stored in a register while waiting for the second character with the upper bits. When both
characters are received, the signal LD X DATA H loads the initial X-address counter, (Figure 6-23).
When the current scan is complete, this data is loaded into the final synchronous X-address counter and
presented to the random access memories.
During a write data program, the signal LD X DATA L clocks the pre-write flip-flop which triggers the
write monostable multivibrator. The write multivibrator enables one of four write pulses to the RAM
memories, either WR GRAPHO L, WR GRAPH 1L, WR HORIZ H, or WRITE DATA L. This latter
pulse is the write input signal to the vertical line and graph marker static RAMs. If either of the graph
write pulses or WRITE DATA L is present, the initial X-address counter is incremented to be ready for
the next data point.
When the pre-write flip-flop is cleared, GRAPHICS FLLAG L 1s sent to the VT100 terminal controller,
confirming that the data has been stored in the static RAMs, and they are ready to receive a new data
word.

6.4.1.9 Loading Graph Memories — Characters B and J produce signals LD GRAPH 0 L and LD
GRAPH 1 L from the decoder. When enabled by the write multivibrator, these signals become WR
GRAPH 0 L and WR GRAPH 1 L that determine into which memory to write the data.
The second and third characters of a load graph instruction form an 8-bit Y-value. This data passes
through a two-line to-one-line multiplexer becoming RAM DATA 0-7 (1) H, (Figure 6-24). The data is
then written into memory in the address, XADD 0-7, from the X-address counter.

Each RAM memory has 25619 X 4 bits of space available. Four of these are connected together to provide 512 X 8 bits of memory for each graph. The signal X ADDR 8 L enables the upper memory addresses, location 256 to 511.

6-30

DB
3H

2ND DATA

CHARACTER

!
DB O H
!
i
B DATA
4

1ST DATA

CHARACTER

g oatao

INITI

AL
X
ADDR

INCREMENT

FROM

LDCUR

]

LDCURD

" ADD 00
Wal LA PN

X ADD 7

X ADD 0

SYNC
COUNTER | TO
MEMORIES

CLK

COUNT TIME H?

XSTOP
(1) H

COUNT UP

LD X DATA H

I
)

LD GRAPHOH

GRAPH 0]|L >
_ WRITE
DATA TO

ODD EVEN (1) H

X STOP (1) L ]

MEMORIES
RAM

LD X

DATA

[O—

GRAPH 1 |L

LD GRAPH 1 H

LD HORIZ L—d

—O

X
ADDR

)

CUP

DECODER D VERTL

XADDRS8L
|
>

ADD 08

|COUNTER

FINAL

X STOP (1) H

HORIZ H

),
WR

DATA L

12 uS

PREWRITE (1) H
PRE-

WRITE
FLIP-

LD X DATA L

FLOP
|

WRITE DATA L

r\n
|

GRAPHICS

COPY L

DISCLR + INIT L

FLAG

V1100

A
MA-4725

Figure 6-23 Loading Address Data

6-31

The M7071 uses a down-counter for a Y-address monitor. For the rectangular field, the down counter is

initially loaded with address 2301¢ each time the scan reaches the bottom of the screen. The scan then
starts at the top-left corner of the screen. After each row of X-address information is processed, the Yaddress monitor is counted down one increment. (For the square field, the down counter is initially loaded

with address 240;¢.)
In order to read memory, only the X-address must be available. The position of the graph data is compared with the current Y-address of the scan. If they are equal and the graph is enabled, the position on

the screen is intensified.
6.4.1.10
Generating Baselines (Shade Lines) (Figure 6-24) — Data bit 0 in the second data character following a load register O creates a signal called BASELINE CTRL (1) H. If high, this signal loads a base-

line for Graph 1; if low, it loads a baseline for Graph 0. (See Paragraph 6.4.1.7 for loading register 0.)
The position of the baseline is determined by two data characters following the character @ (NOP). As

the scan proceeds from top to bottom, its Y-address is compared with the position of each baseline. When
they are equal, the baseline is intensified on the screen.
6.4.1.11

Enabling a Histogram (Shading a Graph)

Without a Baseline (shade line) Enabled — Enabling a histogram intensifies points below a graph to the

bottom of the graph drawing field. Data bits 3 or 4 in register 0 enable HISTOGRAM 0 (1) H and HISTOGRAM 1 (1) H, respectively. These signals, shown in Figure 6-24, enable all points below the graph
determined by the Y-address comparator.
With a Baseline (shade line) Enabled — When its baseline is enabled, a graph is shaded between the graph

line and its baseline. To do this, two sets of comparators are used. One comparator, shown in Figure 6-24,
monitors the position of the graph with respect to the current scan. The other (Figure 6-25) compares the
position of the baseline with that of the current scan. Together, they determine the points to be intensified. The baseline can be moved up or down, and the intensified area changes accordingly.

Bits 3 and 4 in register 0 enable Histogram 0 and Histogram 1, respectively. These bits should not be enabled if the baseline is enabled for that particular graph. Shading the histogram to line O eliminates the
visual effect of shading only those areas between the graph and the movable baseline.

6.4.1.12 Loading Vertical Lines — Vertical lines are loaded with two data characters following the letter
L. Bit 4 of the second data character [B DATA 9 (1) H] with LD VERT H from the decoder provide the
data input (DI3) to the vertical line and graph marker memory. The other bits of the two data characters
transmit the X-address in memory where the vertical line is to be stored. (See Figure 6-26.) If BDATA 9
(1) H is high, the vertical line is loaded; if low, the line is erased at that address.

Memory is continuously read by the X-address counter. Data in the current address is monitored by a Dtype latch and is enabled only if VERTICAL LINE (1) H is present in register 1. This causes VERT
LINE L to be sent to the output circuit. Every other point at a particular X-address is intensified to create
a vertical line. Up to 512 vertical lines can be enabled on the graph field.

As the vertical line is read from the static RAM, its position is fed back (item C in Figure 6-26) and rewritten into the RAM so as not to lose the data.

When the strip chart feature is enabled, vertical lines follow the graph address in a wraparound fashion;
that is, vertical lines move from right to left with the strip chart graph. When the current address exceeds
address 5111, the vertical line data is taken again from the beginning, address 0, 1,2 . . ., etc.

6-32

1ST

DATA

CHARACTER
B

DATA 0—4

2ND DATA

)

=55 TM

CHARACTER

RAM

GRAPH
O L

DATA 07

0-255

266511

S LINE

GRAPH 0

MEM|ORY

1-LINE
5

‘0 DATA 0—7

MUX

X ADD 8 L
WR GRAPH 1 L
\

0—-255

GRAPH 1

X-ADDR

COUNTER

: 256—511

Y1 DAT

—‘

MEMORY

X ADD 0-7

0-7

X ADD 8 L

L GRAPH 0

A0 < BO._

A0=BO

ADDR

=%1B

COMPAR-

ATOR

A0
> BO
TO OUTPUT
|

CIRCUIT

HISTOGRAMO (1)

AND

BASELINE
-

GRAPH 1

A1<B1_ GENERATOR
>

Y-

Al= B1,

ADDR

INITIAL

INPUT
23010

=18

COMPAR-

ATOR

A1 > B1

ADDR

24010*

MONITOR

DOWN
COUNTER
LD

VERT BLANK H 1

CDN

YO(1)H-Y7 (1) H

—-

HISTOGRAM 1 (1) H

TO BASELINE
COMPARATORS
*SQUARE FORMAT

HORIZ + VERT L
MA-4733

Figure 6-24 Graph Memory and Y-Address Monitor

6-33

HOLYYNVIS<INIT3ISVE INIT3ISVE

4HINI3IIL1LO3OV5VHVHY8VHH1IO410(1)Hfi-YAENLIRERN|—>NOVVIHS<dVA0HN8OIT|IS>VNEVISA

al TVIVaxX

S 3iHa v

“HYdWOD

1V 18>

NVOS >INIT3SVE

g>v

gH<OLVv

dON 7

—[V

isi viva OVvi|vas 3OVHOLS
¥31sio3y|

dON H

INIT3 NOHI

a1Sn1zvv11vv.Qa gOoA9Vv0!(VLl0)ivHaLA<«J4(LO3)1VH5H1O9L3Sy3SVE/(1)HLY<18NHIATV3HSOVE|lI <NVIS'A VN310(1)H SvOdL1Nd1NO

8a ¢

6-34

(FROM WRITE MV)

LD VERT H

WRITE DATA L

B DATA
9 (1) H
VERTDATAH

LD VERT L@ -

o12

X A

FROM

X-ADDR

COUNTER

1 H
LD CUR

W
|.

DIt
CS

X ADD 0-7

VERTICAL

INE

AND

GRAPH MARKER
MEMORY

CUR 1 DATA H

LDCUR 1L

®)
LD CUR
O H

CUR
0 DATA H

LD CURO L

(FROM REGISTER 1)
VERTICAL LINE (1) H
YO 1H

HORIZ LINE L .

HORIZ (11 H 10

FROM HORIZ
LINE STATIC

RAM

L o]
o

QUAD

D-TYPE
LATCH

OUTPUT

L—fi

VERT LINE L

VERT LINE (1) H
| CUr1

OUTPUT

CURO (1) H

CIRCUIT

¢@

\ CURTENAH
CUR GRAPH 1 (1) H

FROM

CUR GRAPHO (1) H

|L/)

TO Y-ADDR
COMPARATOR

CUROENAH _
R

MA-4718

Figure 6-26 Vertical Line and Graph Marker Memory

6-35

6.4.1.13 Adding Graph Marker - The graph marker in the VT 105 is a short vertical line that straddles
the graph. For each graph marker, 16 additional dots on the screen are enhanced above and/or below
the graph point. The number of dots above or below the graph point is hardware-dependent according
to the current graph position. If the graph is at the top of the screen, the 16 dots are all below that of
the graph point; if at the bottom, they are all above the graph point.
Loading a graph marker is accomplished by two data characters following the letters C or K. These
letters are decoded as LD CUR O H and LD CUR 1 H, shown in Figure 6-26. When bit 4 of the second
data character [B DATA 9 (1) H] is a one and WRITE DATA L is present, a graph marker 1s loaded in
the address formed by the two data characters. If bit 4 is a zero, the graph marker is erased.

When the graph marker is enabled and read from memory, an equal condition is forced from the lower
four bits of the Y-address comparator (Figure 6-27). The upper 4-bit comparator holds this equal
condition until one of its bits changes. This does not happen until the Y-address has decremented 16
lines. The graph data point may be on any one of these 16 lines causing the graph marker to vary in
number of dots above and below the graph point.

As the X-address is incremented, the output of the vertical line and graph marker memory is monitored by a D-type latch. As with the vertical line data, the graph marker data is also fed back into
memory (items A and B in Figure 6-26) and wraps around when in strip chart mode.

6.4.1.14 Generating Horizontal Lines - A horizontal line is loaded with the character D. The two data
characters following the D represent an 8-bit Y-position of a horizontal line. Data bit 4 in the second
data character enables the signal DIS CLR + INIT H that allows the A inputs to the two-line to oneline multiplexer (shown in Figure 6-28) to be gated out. The data, or address of the line, is then
presented to the 256 X 1 static RAM memory. Data bit 4 [B DATA 9 (1) H] is also the data to be
written into memory. If it is a one, a horizontal line is stored; if zero, a line is erased at that address.

A down-counter is used for tracking the Y-address when reading data from memory. To read from
memory, only the Y-address is needed. A complement of the data in memory is the output. From
register 1, HORIZ LINE (1) L enables all points at that Y-address creating a horizontal line. The
signal 320 NS allows only every other dot to be displayed to decrease its intensity.

6.4.1.15 Generating Strip Charts — Strip charts are enabled by the second data character following a
load enable register 0 instruction, as shown in Figure 6-29. Data bit 3 (DB 3 H) of this register enables
the single strip chart feature; either Graph 0 or Graph 1 can be incremented from right to left across
the screen.

Data bit 4 (DB 4 H) of this register enables the dual strip chart feature; both Graph 0 and Graph 1 data
can be incremented from right to left across the screen. This must be done in the following sequence.
Data Entry

Character(s) Transmitted

Enable Graph 0
Enter Graph 0 data
Enable Graph 1
Enter Graph 1 data

B
Two data characters
J
Two data characters

6-36

GRAPHO (1) H
CUR 0 ENA H

GRAPH

POSITION

YO DATA
0 > 7H

A0
<

BO
A<BRI22Y
A=B

a=pg|R0=80
Y4-Y7 (1) H »l5

TO OUTPUT
CIRCUIT

|LA0>BO

A <B

—! A
A=B

VERTICAL yo_v3 (1) H

SCAN

=g B

A> B

POSITION

CUR O ENA H
MA-4726

Figure 6-27 Graph Marker Y-Address Comparator

6-37

—_

—

2ND DATA

CHARACTER
1ST DATA

CHARACTER

0—2 H

—

B DATAO0-4(1)H

—

$A2

LINE

1 LINE

—

MUX

LOAD TO 23010
2

(OR 24010%)

YO (1) H-> Y7 (1) H

ADDRESS

—&B

DOWN

ISELECT

|coUNTER

}

LD CDN |

5
f

VERT BLANK
H

DIS CL
+ INT
R
L

HORIZ + VERT L

X STOP

2I0P (1)L

]

X STOP (1) H

DIS CLR + INT H

160NS

WR HORIZ H

HORIZ LINE (1) L

(FROM REGISTER 1)
BDATAQ
() H

RAM DATA

0—7 (1) H

(Y-ADDRESS)

WE
W
256 X 1
STATIC

RAM
HORIZ

HORI1Z

LINE

LINE L

RAM

MEMORY
OUTPUT

| SE—|

0—7 (1) H

GRAPH

320 NS

DATA

INPUTS

* SQUARE FORMAT

**LOW: OUTPUT = A; HIGH: OUTPUT =8
MA-4727

Figure 6-28 Horizontal Line Memory

6-38

DB3H

2ND DATA

FROM

CHARACTER

DATA

1ST DATA

INITIAL

DB OH

X ADD

OVERFLOW (1) H

FINAL
X ADDR

INCREMENT

B DATA‘T‘ (1) H

COUNTER

COUNTER | X ADD

ADDR 00-08 (1) H

CHARACTER BDATA O (1) H

—

TO GRAPH
MEMORIES

LD CUPCDN
u
D X H

CLR CLKLD
(@I
| ?
COUNT TIME H

FROM DECODER
LD X

0—8
H

DATA H

HORIZ +

VERTH

+3VH

WR GRAPH 1 L
WR GRAPHO L

LD GRAPH 1 H

—

ENA
F/F

DUAL STRIP H

STRIP

LD X DATA H

2ND

BIT 3

—

STRIP

?
J

ENA (1) L

\ STRIP H

DATA

_—

CHARACTER

512

—
1 C COUNTER
—|
—

_—

F/F

TIME

(1) H

X STOP (1) H
X STOP

[

DUAL STRIPH =

(1)

START L
109L.{>0—.

—

(]

—oC

CLK

HORIZ + VERT L

COUNT TIME H
MA-4721

Figure 6-29 Generating Strip Charts

6-39

Single Strip Chart Operation - Two X-address counters are used to create the strip chart motion.
Without the strip chart feature enabled, the final X-address counter is cleared to zero at horizontal
blank time (by HORIZ + VERT H). With a strip chart enabled, this clear signal is disabled allowing
the final X-address counter to follow the initial X-address counter counting in a wraparound manner.
Data 1s loaded into the graph as usual for addresses up to 511. At address 512, an overflow occurs in

the initial X-address counter. OVERFLOW (1) H clocks the strip enable flip-flop disabling the clear
signal to the final X-address counter.

A 512-bit counter monitors the horizontal scan position and enables the load signal for the final Xaddress counter only after completing the current line. New data increments the X-address and is
added to the end of the graph. This new data is then the last data to be read from memory. Previous
data is read one position earlier causing a shift in the video graph to the left.
When the strip chart is disabled, the final X-address counter is cleared at horizontal (or vertical) blank

time regardless of its current count. This causes the displayed video graph to reposition itself as the
counter 1s reset to zero.
Dual Strip Chart Operation — For dual strip chart operation, data bit 4 in register 0 must be set,
creating the signal DUAL STRIP H. Data for both Graph 0 and Graph 1 must be placed at the same
X-address and shifted simultaneously. Refer to the timing diagram (Figure 6-30) and the following
sequence of events.

Aninstruction to load Graph 0 is received. WR GRAPH 0 L is placed on the count-up input
to the initial X-address counter. The data is written into Graph 0. After 50 ns, WR GRAPH
0 times out, and the counter increments one address.

When the command to load Graph 1 is received, the Initial X-address counter counts down
one address.

WR GRAPH 1 L is placed on the count-up input to the initial X-address counter. Data is
written into Graph 1. After 50 ns, the initial X-address counter increments one address.

When the initial X-address counter is incremented, this new address is loaded into the final X-address
counter at the end of the current graph line [as X STOP (1) H goes low]. The last data word entered in
each graph is the last X-address read.

Incrementing the initial X-address counter, by adding a new data word to each graph, causes the final
X-address counter to access that data last in both memories. This causes both graphs on the screen to
shift simultaneously one unit to the left for each new set of data words.

The 512-bit counter that monitors the graph drawing field is initially loaded to a ““1”’ in dual strip chart
mode. A count of 512 is reached one count time earlier, eliminating the last bit position on the graph.
This removes the switching motion that would be visible on the screen while alternately plotting data
on Graph 0 and Graph 1.

6-40

DUAL STRIP H _J

[

I L

LD GRAPH 1 H

uouuuU

511
,

u
1

511

210,

U
TM)

ADD 0008

COUNT DOWN*

(]

COUNT uPTM

WR GRAPH 1 L

L =

[ L

-Jn——l

WR GRAPHO L

[ L

J°

worarHon |
|

STRIP ENA (1) L
)

OVERFLOW OF

VIDEO PICTURE

INITIAL X-ADDR

STARTS MOVING

COUNTER

HERE

*INITIAL X-ADDR
COUNTER
MA-4729

Figure 6-30 Dual Strip Chart Timing Diagram

6.4.1.16

Combining Video Out and Timing - All data signals generated within the M7071 are combined to form one video output to the VT100 terminal controller (Figure 6-31).

The timing signals are developed by the phase lock loop using HORIZ BLK L from the VT100 terminal controller. (See Paragraph 6.4.1.6.)
Graph 0 and Graph 1 data, horizontal lines, vertical lines, and Graph 0 and Graph 1 markers are
presented to the video output every TIME (1) H. At COUNT TIME H the 512-bit horizontal counter
clocks the window flip-flop to gate the data out.
Histogram O or Histogram 1 data is alternately enabled to the video output with TIME (0) H and
TIME (1) H. This allows both shaded graphs to be discernible in areas on the screen where they
overlap.

6-41

BASE LINE ONE H
WITH SHADED GRAPH

TIME
(1) H

HISTOGRAM 1

(IF NO BASELINES)

D2
QUAD

BASE LINE ZERO H

WITH SHADED GRAPH

D-TYPE

HISTOGRAM 0

(IF NO BASELINES)
GRAPH O

FLIP-FLOP

OR GRAPH
0 MARKER
HORIZ (1) H

GRAPH 1 OR GRAPH 1 MARKER

DCOLK

TIME (0) H
>

VERT LINE L

TIME (1) H

-A1 VIDEO
H

START L

109

>
—p

J
WINDOW

512

VT100

BIT

HORIZ

F‘d CLK

DOT

COUNTER

DUAL

STRIP H

—

HORIZ + VERT L

FLIP-FLOP

START (1) H

.
VIDEO

COUNT X00 (1) H
COUNT TIME H

FROM
VT100

HORIZ

DELAY

BLK L

COUNTER

fRECTANGULAR
MA-4719

Figure 6-31 Combining Video Out

6-42

6.4.2 VTI10S Graphic Test Prdcedure

The interactive test feature of the VT10S5 is a series of displayable test patterns. These patterns verify
that all waveform generator features are operating correctly. Perform these data tests in the order
indicated.
NOTES
1.

The tests described in this procedure are run

in the rectangular format. The tests may also
be run in the square format, but the test patterns are slightly different.
2.

Do not use the SPACE BAR unless the word
SPACE is spelled out.

Remember to use the SHIFT key for up-

percase symbols; the CAPS LOCK key is
only used for uppercase letters.
4.

If at any time the wrong character is entered,

initialize the registers and memories by typing

the following sequence:
A SPACE SPACE
10

I space “
Then reenter the test data.

6.4.2.1

Test Set-Up

Place the terminal in LOCAL mode

Turn on the auto repeat feature (in SET-UP B group 1, switch 2 equals a 1).

Type the following sequence.
ESC 1
I SPACE SPACE
ISPACE”

6-43

6.4.2.2

Test Graph 0, Histogram 0, and Graph 0 Markers

Type the following sequence.

A#
The graph test pattern in Figure 6-32 is now on the screen.

Type the following sequence.

A)
The histogram test pattern in Figure 6-33 is now on the screen.

Type the following sequence.
I$

The graph marker test pattern in Figure 6-34 is now on the screen.
4.

Type the following sequence.
I SPACE
A SPACE

The graph 0, histogram 0, and graph 0 markers are now disabled.

MA-4741

Figure 6-32 Graph Test Pattern

6-44

2 AR
TR

Figure 6-34 Graph Marker Test Pattern

MA-4743

Figure 6-33 Histogram Test Pattern

6-45

6.4.2.3
1.

Test Graph 1, Histogram 1, and Graph 1 Markers
Type the following sequence.

A%
The graph test pattern in Figure 6-32 is now on the screen.
2.

Type the following sequence.
Al

The histogram test pattern in Figure 6-33 is now on the screen.
3.

Type the following sequence.

I(
The graph marker test pattern in Figure 6-34 is now on the screen.

Type the following sequence.
I SPACE
A SPACE

The graph 1, histogram 1, and graph 1 markers are now disabled.
6.4.2.4

Test the Horizontal Lines

Type the following sequence.
Al
I!

The horizontal line test pattern in Figure 6-35 is now on the screen. Note that the test
pattern appears to be a series of vertical lines. This is the correct test pattern.

Type the following sequence.
I SPACE

The horizontal line test pattern is now disabled.
6.4.2.5
1.

Test the Vertical Lines
Type the following sequence.
Al
I‘C

The vertical line test pattern in Figure 6-36 is now on the screen. Note that the test pattern
appears to be a series of horizontal lines. This is the correct test pattern.

6-46

Type the following sequence.

I SPACE

The vertical line test pattern is now disabled.

MA-4744

Figure 6-35 Horizontal Lines Test Pattern

MA-4745

Figure 6-36 Vertical Lines Test Pattern

6.4.2.6

Test Shade Line 0 (Baseline 0)

Type the following sequence.

A#
The shade line test pattern in Figure 6-37 is now on the screen.
2.

Type the following sequence.
@1l

22
33
44
55
66

SPACE SPACE

The shade line shifts upward with each pair of numbers typed.

Type the following sequence.
A SPACE SPACE

TRITTERTTRT
AT

The shade line 0 test pattern is now disabled.

MA-4746

Figure 6-37 Shade Line (Baseline) Test Pattern

6-48

6.4.2.7

Test Shade Line 1 (Baseline 1)

Type the following sequence.
A %%
The shade line test pattern in Figure 6-37 is now on the screen.

Type the following sequence.
@11

22
33
44
55
66

SPACE SPACE
The shade line shifts upward with each pair of numbers typed.
3.

Type the following sequence.
A SPACE SPACE
The shade line 1 test pattern is now disabled.

6-49

6.4.2.8

Test Strip Chart 0

Type the following sequence.
I SPACE

A+(
The histogram test pattern shown in Figure 6-33 is now on the screen.

Type the following sequence.

- H”
The strip chart test pattern shown in Figure 6-38 is now on the screen.

Type any sequence of two (2) numbers. This causes the graph to move. The SPACE BAR

enters a 0 as in Figure 6-38, 11 enters data at line 49, 22 enters data at line 82, etc. Hold down
the number key if in auto repeat mode.
Type the following sequence.
A SPACE SPACE

AR
ATAT A

The strip chart test pattern is now disabled.

MA-4747

Figure 6-38 Strip Chart Test Pattern

6-50

6.4.2.9

Test Strip Chart 1

Type the following sequence.
[ SPACE
AS(

The histogram test pattern in Figure 6-33 is now on the screen.

Type the following sequence.
H?”?

The strip chart test pattern in Figure 6-38 is will now on the screen.

Type any sequence of two (2) numbers. This causes the graph to move. The SPACE BAR
enters a 0 as in Figure 6-38, 11 enters data at line 49, 22 enters data at line 82, etc. Hold down
the number key if in auto repeat mode.

Type the following sequence.
A SPACE SPACE
The strip chart test pattern is now disabled.

6.4.2.10
1.

Exit the Graphic Test Mode
Type the following sequence.
I10SPACE
A SPACE SPACE

I SPACE SPACE
ESC2
The terminal is now in interactive mode.

6-51

CHAPTER 7
STANDARD TERMINAL PORT

7.1

INTRODUCTION

The standard terminal port (STP) is intended to be a standard interface for terminal options. These options may include communications, graphics, a terminal processor, and mass storage devices.
The STP was originally developed as part of the VT100. Attempts have been made to ensure the generality of the STP, but some compromises toward the VT100 may have been made. Special VT100 considerations are noted in this chapter where applicable.
7.2 DEFINITIONS
The following definitions apply in this discussion:
Active device — A device that either: 1) wishes to take over control of the host communication line; 2) requires all received and transmitted data passed between the host communication line and the terminal
controller to be looped through the device; or 3) needs to communicate with the terminal controller
directly. One example of an active device is a terminal processor doing local editing, standalone computing, etc.

Host — That which connects to the serial line connector on the outside of the terminal. Normally, this is a
computer system (via direct line or otherwise), but might in some cases be another terminal or other deViCe.

Host link — The serial line between the option and the host. The option’s line UART is on one end of this
link, and the host is on the other.

Local link — The serial line between the terminal controller and option when an option is present. The terminal controller’s UART is on one end of this link, and the option’s local UART is on the other.
Passive device — Those devices that do not need the capabilities of an active device. A passive device normally only wants to listen to the data stream from the host and to pass data back to the host, but not to
interfere with normal terminal or communications line operation. Terminal mass storage, such as a tape
cartridge, would fall into this class.
Receive only device — A special case of a passive device that never needs to transmit data to the host, but
only to listen to data from the host. Certain types of graphics options fall in this category.

Terminal controller (TC) — The processor in the basic terminal that controls normal terminal operation.

This term is used to distinguish it from any other processor that might be packaged into a terminal.
Terminal processor (TP) — An additional processor, not necessary for basic terminal operation, but to add
other functions, such as local editing or computing.
SET-UP mode — The terminal mode that allows user to set terminal characteristics.

7-1

7.3

OVERVIEW

The STP provides a means of interfacing terminal options. Logically, this interface is similar to that of a
serial line splice (Figure 7-1) which is accomplished by breaking the serial line from terminal to host and
inserting the option. An internal interface connector is provided for reasons of packaging aesthetics, and
additional signals are present to reduce the interface cost. Part of the terminal controller firmware is also
dedicated to support the STP, since some information needed by the option is passed as data across the
serial line, rather than assigning additional pins on the interface connector. This firmware also allows the
option to use the terminal characteristics specified by the user in SET-UP Mode. The STP provides a reasonably cost-effective interface for a large class of terminal options, and is general enough to allow for
decoupled evolution of terminals and terminal options.

[ TERMINAL

DEVICE

HOST
MA-4288

Figure 7-1a Serial Line Splice Connection

TERMINAL

CONTROLLER|
(TC)

UART
(+EIA)
MA-4289

[TERMINAL
|

CONTROLLER|
(TC)

TC
UART
(+EIA)

EIA

CONDX

LOCAL

LINE

UART

OPTION
MA-4290

Figure 7-1c STP With Option Present

7-2

7.4

FUNCTIONAL SPECIFICATION

7.4.1
Interface Signal Lines
The signal lines that make up the STP are shown in Figure 7-2. The lines are accessed through a standard
20-pair shorting connector, described in Paragraph 7.6. In general, the signals are standard EIA serial
line and modem controls, though some special signals are also present. See Paragraph 7.5 for complete
electrical specifications.

TO TERMINAL

SHORTING

TO EIA LINE

CONTROLLER

PINS

CONNECTOR

TC RXD =

LINE RXD

TC TXD

— LINE TXD

TC TCLK

»t

]

»}

INTERNAL TCLK «a—

TC RCLK
INTERNAL RCLK «-

LOCAL CLK

OPTION PRES =

SIGNAL GROUND

TC INIT

ja-

—»

TC RTS

» LINE RTS

TC DTR

—» LINE DTR

TC SRTS/SPDS

# INE SRTS/SPDS

TC DSR
TC CTS
TC CD

je
le
{e

LINE DSR
LINE CTS
LINE CD

TC RI

LINE RI

TC SCD/SPDI|
=

jo—
jeje-

+5 V
+12 V

—»]
.

—-12V

—»

LINE SCD/SPDI

EXT TCLK
EXT RCLK

MA-4287

Figure 7-2 STP Signal Lines

Each pair of signals is connected together when no option is present. When an option is plugged in, each
connection is broken, though the option may choose to short through any signal it does not wish to control.
Note that some signals are used between the terminal controller and option only or between option and
external connector only, and so are defined on only one side of the connector. The signals and their mean-

ings are as folllows.

7-3

Signal
TCRXD

Type

Meaning

EIA

TC received data. Serial,
asynchronous data is passed from

host or option to the TC on this
line.

LINERXD

EIA

Line received data. Serial data is
passed from host to option or TC
on this line.

TCTXD

EIA

TC transmitted data. Serial data
is passed from TC to host or
option on this line.

LINETXD

EIA

Line transmitted data. Serial data

is passed to host from option or
TC on this line.
TCTCLK

TTL

TC transmitter clock. This signal

from the TC bit rate generator
normally drives the UART that
talks to the host. Its frequency
is 16 times the bit rate.

INTERNAL TCLK

TTL

Internal transmitter clock. This

signal drives the UART associated
with the TC. When no option is
installed this signal is driven by
TC TCLK. With an option installed
this signal would normally be
driven by either TC TCLK or LOCAL
CLK. (Refer to Paragraph 7.4.2.2
for further information.) The baud
rate applied to this line may not
be more than 19,200 fora VT100.
TCRCLK

TC receiver clock. Just like TC
TCLK.

INTERNAL RCLK

Internal receiver clock. Just like
INTERNAL TCLK (19,200 max. for
VT100).

LOCAL CLK

Local bit rate clock. Thisis a
clock signal provided by the TC
whichis 16 X, a “convenient’ data
rate for the local (TC to option)
link. Normally, this bit rate
would be near the highest rate
that the TC can handle
efficiently. It need not be a
standard bit rate, so this clock
can be sourced by some timing

7-4

Signal

OPTION PRESENT

Type

Meaning

TTL

Option present. A low on this line
means that no option is present,
and normal terminal operation is
in order. It must be passively
pulled up on the TC board. A high
on this line indicates the

signal that happens to be
available in the terminal. The
equivalent X 16 baud rate supplied
by the VT100is 15,734 baud
(251.744 kHz).

presence of an option and informs
the TC to make appropriate changes
in its operating modes.
TCINIT

TTL

Initialize. This line notifies the

option that a power-up clear or
terminal reset has occurred. (See
electrical specifications in
Paragraph 7.5.)
TCRTS
TC DTR
TC SRTS/SPDS

EIA

LINERTS
LINEDTR

EIA

Line modem control signals. EIA
modem control signals that go to
the host line may be fed from
option or from the corresponding
“TC” signals. Inthe VT100, LINE
SRTS/SPDS isstrapped topins 11,
19, and 23 on the RS-232-C
connector mounted on the terminal.

EIA

TC modem status signals. These
lines are the standard EIA status
signals: data set ready, clear to
serid, carrier detect, secondary
carrier detect (or speed
indicator), and ring indicator.
The option may source these
signals to the TC, or pass through
the corresponding “LINE” signals.

signals. These signals are the
standard EIA modem control
signals: request tosend, data
terminal ready, and secondary
request to send (or speed select).
The option may ignore them, use
them itself, or pass them through
to the corresponding “LINE”
signals.

LINE SRTS/SPDS

TC DSR
TCCTS
TCCD
TC SCD/SPDI

TCRI

Terminal controller modem control

7-5

Signal

Type

Meaning

LINE DSR
LINE CTS
LINECD
LINE SCD/SPDI
LINE RI

EIA

Line modem status signals. The EIA
modem status signals received from
the host line connector. May be
used by the option, or passed
through to the corresponding “TC”
signals. Inthe VT100, LINE
SCD/SPDI is connected to Pin 12 of
the RS-232-C connector mounted on
the terminal. This pin is used for
different functions by different
modems.

EXTTCLK

EIA

External transmit clock. This
signal i1s provided by a modem or
other external device. This pinis
connected to pin 15 on the
RS-232-C connector mounted on the
terminal. It is intended to be
used by an option that needs this
signal.

EXT RCLK

EIA

External receive clock. This
signal is provided by a modem or
other external device. This pinis
connected to pin 17 on the
terminal’s RS-232-C connector.

+5V,+12V,
—12V

Power

Interface power. (See Paragraph
7.5.2 for further specifications.)

SIGNAL GROUND

Ground

Signal ground.

7.4.2

Protocol Specification

Proper operation with the STP requires some firmware support in the terminal controller. This section
specifies the protocol used to communicate between option and terminal controller.
7.4.2.1 Terminal Operation With No Option Present — In standalone terminal operation, all signals on
the STP are passed through by the shorting connector. The terminal controller senses the absence of an
option and performs its normal function. In SET-UP mode, when the user makes changes to terminal
characteristics, these changes take effect in the normal manner. Any escape sequences from the host destined for a nonexistent device are ignored by the terminal controller.

7.4.2.2 Standard Set-Up For Local Link — When an option is present and breaks the serial line as it
passes through the STP connector, the option and terminal controller must agree on the line characteristics for the local link. To this end, the assertion of OPTION PRESENT causes the following changes:
Bits/Char

Set to 8 bits per character

Stop Bits

Set to 1 stop bit

7-6

Parity

Set to no parity

XOFF

Line synchronization (XON /XOFF) must be supported in both directions on the
local link. Note that the TC must accept XOFF as well as source it.

Normally, it is assumed that the option will use the TC TCLK and TC RCLK signals to drive its line
UART, while using LOCAL CLK to drive INTERNAL TCLK and INTERNAL RCLK. The option
may, however, choose to source another set of clocks to drive the TC UART instead. INTERNAL
CLOCKS should not be driven at a frequency higher than 19,200 baud for the VT100. It is recommended that INTERNAL TCLK and INTERNAL RCLK be set to the same rate to avoid XON/XOFF timing problems.

7.4.2.3 Control Sequences For Terminal Parameters — Only two control sequences are specified for STP
operation. The first of these reports terminal parameters of interest to the option, while the latter is used
to request this information. The formats of these sequences are:
DECREPTPARM - Report Terminal Parameters
ESC [ <sol>;<par>;<nbits>;
<xspeed>; <<rspeed>;<<clkmul>;
<flags> x

DECREQTPARM - Request Terminal Parameters
ESC [ <sol> x

The final character for both strings has been chosen as lowercase x (octal code 98, column/row specifier
7/8). This is a DEC Private sequence.
DECREPTPARM is sent by the terminal controller to notify the option (or host) of the status of selected
terminal parameters. It may be sent when requested by the host or option, or at the terminal’s discretion.
DECREPTPARM will be sent upon receipt of a DECREQTPARM, or voluntarily upon leaving SETUP mode when the terminal sees option present asserted and it has been asked to report unsolicited by a
previous host request.
The option is responsible for sensing a terminal power-up or reset, which it may note by the assertion of
TC INIT by the terminal.

The meanings of the parameters are as follows:
(* indicates the assumed value if the parameter is not specified.)

Parameter
<sol>

Value
0 or none
1

Meaning
This message is a request (DECREQTPARM) and the terminal
will be allowed to send unsolicited reports.
This message is a request, and henceforth, the terminal may only
report in response to a request.
This message is a report (DECREPTPARM) and the terminal
thinks it may report at will, although this particular report may
not be voluntary.
This message is a report, and the terminal is only reporting on
request.

7-7

Parameter

Value

Meaning

<par>

No parity set
Parity is always space (not a VT 100 state)
Parity is always mark (not a VT 100 state)
Parity is set and odd
Parity is set and even

3
4

<nbits>

1*
2

8 bits per character
7 bits per character

Because some terminals have limitations in
handling numeric values, baud rates cannot be
sent as decimal strings (e.g., 2400). This
list of baud rates is basically encoded on
multiples of 8 so further speeds can be
specified later and left in baud rate order.

Bit
Per
Sec
0
8
16
24
32
40
48
56
64
72
80
88
96
104

Rate
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800

112*
120

9600
19200

7200

108

<flags>

1*
2

0-15

(nota VT100 speed)

The bit rate multiplieris 16
The bit rate multiplier is 64

This value communicates 4 bits of user defined information as a
decimally encoded binary number. These bits may be assigned in
an STP device dependent fashion. Bit weightsare 8 4 2 1 from left
to right. The default value for these four bits is 0. In the VT100,
these bits are switch group 5 of SET-UP B.

If any parameter (except for <sol>) is zero or not present, it should be interpreted as the default value
for this parameter. The default for each parameter is marked with an asterisk (*) in the above list. Any
parameter out of its defined range must be treated as an error. Additional parameters (beyond these sev-

en) must be ignored without affecting the interpretation of the other parameters. This last restriction allows for future standardization of the additional parameters.

7-8

7.4.2.4 Initialization - The option must sense the signal TC INIT from the terminal controller and
reset itself to initial state upon reception of this signal. Timing for this signal is specified in Paragraph
7.5.1.2. This signal may be used to reboot a terminal processor if desired. It will be generated at
terminal power-up, and in response to a “reset to initial state’” or confidence test request from the host
or operator.

7.4.2.5 BREAK - The BREAK signal will be transmitted over both the local and host links in the
normal manner. If an option which passes characters from the terminal controller to the host without
modification, the option must detect the break on the local link and generate a corresponding break on
the host link.

If a terminal processor treats the terminal controller as a terminal, BREAK from the terminal controller may be used for a standard purpose such as causing entry into ASCII console microcode. This
may require the option to use a UART with an external “framing error” line, or to design in a
hardware break detector (counter and gate).
7.5
7.5.1

ELECTRICAL SPECIFICATIONS
Signal Lines

Specifications for the signal (nonpower) lines are a follows.

7.5.1.1 Signal Levels - Two classes of signals are present on the STP connector. The first class are
standard EIA levels, and include transmitted and received data, modem control signals, etc. The second class are TTL signals used to control interface operation, and include bit rate clocks, OPTION
PRESENT, etc.
For VT100:

All EIA outputs
Mark State -6.0to-12.0V
Space State +6.0to 12.0V
All EIA inputs
Mark State +0.75 to -25.0 V, -8.3 mA max.
Space State +2.25to +25.0V, +8.3 mA max.
All TTL inputs
VIH = 2.0 V max.
ITH=20uA max.@ VI =2.7V
VIL = 0.8 V max.
IIL=05SmA@VI=04V

All TTL outputs
VOH = 2.7V
@ IOH = 0.1 mA
VOL=05V@IOL =3.2mA

7.5.1.2 Signal Timing - The INIT H signal goes high when the VT 100 starts an initialize sequence and
goes low when the VT100 is ready to operate. The minimum high time is 100 ms.
LOCAL CLK has the following period for the

VT 100 as shown in Figure 7-3.

7-9

’ WHERE T = 1.86928 usec
MA-4298

Figure 7-3 Local Clock

7.5.2

Power Supply Lines

Voltage regulation specifications and base product power requirements for the VT 100 may be found in
Chapter 4. All options drawing power through the STP or 20 mA connectors on the VT100 terminal
controller board may draw no more than 0.5 A from any one voltage. Options drawing power from
any connector in the VT100 must be sure that their requirements, the needs of other options, and the
needs of the base VT100 are consistent with the capability of the VT100 power supply.
7.5.3

Connector Pinout

TCTXD
TCRXD
TCRTS
TCCTS
TC DSR
TCDTR
TCCD
TCRI
TC SPDS
TC SPDI
-12V

2
-4
6
8
-10
12
14
16
18
20
22
24
26

1 LINETXD
JEXTTCLK
5 LINE RXD
7LINE RTS
9 EXT RCLK
11 LINECTS
13 LINE DSR
15 LINE DTR
17 LINECD
19 LINE RI
21 LINE SPDS
23 LINE SPDI
25—

+12V

31 —

LOCAL CLK
TCINIT
+5V

36
38
40

35—
37—
39 —

TCTCLK
TCRCLK
OPTION PRESENT

7.6
7.6.1

28
30

27INTERNAL TCLK
29 INTERNAL RCLK
33 SIGNAL GROUND

MECHANICAL SPECIFICATIONS
Shorting Connector

The STP connector, DEC part number 12-14829 consists of 20 pairs of shorting bifurcated contacts,
spaced on 0.125 inch centers, with 0.4 inch penetration (Figure 7-4).

7.6.2

STP Connector Card

The card that plugs into the STP connector may serve as just a paddle card with connection to a

separate module, or may actually contain circuitry such as a minimum terminal processor. The termi-

nal provides room for a card at least as large as and with finger and connector placement similar to
those in Figure 7-5. STP interfaces to be dedicated to a particular terminal family may depart from this
specification, but at penalty of future generality.

7-10

MA-4286

Figure 7-4 STP Connector

7.7 GUIDELINES FOR THE DESIGNER
This section is not, strictly speaking, part of the STP specification. It is meant to provide some indication of how the STP may be used to implement some different terminal configurations. It is not
intended to be an exhaustive study of all possible options, nor to dictate particular design decisions. It
is hoped, however, that it will be useful to the architect and option designer, and provide some insight
into the choices made in specifying the STP.
7.7.1 Use with Receive Only Device
There are two basic ways to implement a receive only device on the STP. One method requires only
one UART, the other two. The first method is more limited, however, while the second is more
flexible.

7.7.1.1 Single UART Method - In this case, the option shorts through all STP signals and does not
assert OPTION PRESENT. It picks up the receive bit rate clock from the STP signal lines and uses
only the receive side of its UART to tap off the TC RXD/LINE RXD line. It also watches for TC
INIT and may, if desired, monitor the state of the modem control and status lines.
The limitations of this method are:
1.

The option may not send XOFF

to the host to control the received data rate.

The option gets no information or parity status or sense from the terminal controller. It may
try to deduce this information from the data it sees, or specify that it may only be used in
certain modes, however.

7-11

The option gets no information on number of bits/char or bit rate multiplier from the

terminal controller. Similar to parity problem.
The advantage of this method is its low cost for implementing a receive only device.

109.99 mm

851mm

(3.350 in.)

(4.325in.)

—-—

— = &

HOLE LOCATIONS ON

2.03mm

(.800in.)

2.94 mm

(1.156 in.)

'I'

— — —--

TERMINAL CONTROLLER BOARD
105.66 mm

(4.68 in.)

COMPONENT SIDE

L_.l

127 mm

(.05 in.)

3.12 mm

(1.230in.)

693 mm

15 mm R/

(.06in.)
MIN

3.561T mm

(1.380in.)

76 mm

(2.730in.)

nin

]

(.300 in.)

ninin

HHEETHT
T HRTHEE
T

i
_.l

318 mm

(.125in.)

i102g .mr)”

20 mm

KEYSLO

20 PLACES

Cover O

TYP

19 PLACES

(.080 in.) FINGERS
MA-4296

Figure 7-5 STP Option Card

7-12

7.7.1.2 Two UART Method - In this case, the option breaks the serial data and clock lines on the
STP, while passing through the modem control and status signals without change. It asserts OPTION

PRESENT, normally ties LOCAL CLK to INTERNAL TCLK and INTERNAL RCLK as well as to

its own local UART, and uses TC TCLK and TC RCLK to drive its own line UART.

In this mode, the option is responsible for implementing XON /XOFF on the host link, if that feature
is enabled. It may also XOFF the terminal controller if the data is coming too fast, since the data rates
on the local and host links may not be the same. It must, of course, also respond to an XOFF from the
terminal controller.
7.7.2

Use With Passive Device

Unlike the receive only device, the passive device option wishes to transmit data on the host link, and
must therefore break the serial line as it crosses the STP connector.

The passive device connects to the STP in the same way as the two UART receive only device. It
asserts OPTION PRESENT and drives INTERNAL TCLK and INTERNAL RCLK (with either
LOCAL CLK or a clock generated by the option itself).
In this mode of operation, the option must parse all valid ANSI sequences it passes from the terminal
controller to the host. First, it must recognize DECREPTPARM in order to get the current set of
terminal characteristics. Second, it must parse all other ANSI sequences so that it never sends data to
the host in the middle of a sequence generated by the terminal controller. Sequences that must be
handled correctly are specified in ANSI X3.64-1977, and include: escape sequences, control sequences,
control strings, and single shifts.
Since a passive device does not need to talk to the terminal controller, it need not parse ANSI sequences from the host before passing them on to the terminal controller. Note that the terminal
controller must accept an XOFF in the middle of a (escape or control) sequence without error. The
option need only recognize those sequences which belong to it. As long as these are valid ANSI
sequences they will be ignored by the terminal controller.
Because a single terminal may have more than one option, it is required by this specification that any
passive device must replicate the standard STP shorting connector. This shorting connector should
break the host link on the option before that link returns to the STP connector of the terminal controller (or option) that the device plugs into. (For more detail on these requirements, see Paragraph
7.7.6).

7.7.3 Use With Active Device
There are at least two types of active devices: (1) the terminal processor acting as the CPU in a
standalone system packaged in a terminal box, and (2) the terminal processor acting to enhance the
terminal functionality, to provide local editing, format and value checking, etc. In the former case, the
terminal processor (the active device) views the local link and host link sides of the STP as two separate
entities and may, in fact, not even make use of the host link. In the latter case, by contrast, the terminal
processor (again the active device) is seen only as augmenting the basic terminal operation, and (in
some abstract sense) passes through all the data it handles between host and terminal controller.
7.7.3.1 Terminal Processor As Standalone CPU - In this configuration, the terminal processor treats
the local and host links of the STP as two separate devices. It asserts OPTION PRESENT to set the

local link to a standard state. It retains control of the host link, though it may listen to DECREPTPARM sequences sent by the terminal controller
if this is appropriate to the application. It may use

or ignore TC RCLK and TC TCLK as it wishes. If the TP needs “boot” and *“‘console entry” signals,
these needs may be met by INIT and local BREAK, respectively.

7-13

7.7.3.2

Terminal Processor Augmenting Basic Terminal Operation - In this case, the terminal processor 1s used to add functionality to the terminal. Logically, communication is between the host and the

“terminal’” (terminal controller plus terminal processor), rather than between a
CPU and two devices
as in the standalone CPU case. The terminal processor may intercept the normal data stream to and

from the terminal controller, rather than just listening for (and interjecting) special control sequences,
as in the passive device case. One example of such an option is a printer graphics option, which would

receive graphic instructions, convert them into a bit map representation, and transmit that bit map

serially to the printer terminal controller. Another example is that of a multiplexer which might make a
CRT terminal into three logical terminals by maintaining cursors in each of three screen areas, routing
keyboard input to the proper host task, etc.
7.7.4

Use With Communications Option
This case is similar to the active device configurations discussed in Paragraph 7.7.3. In addition, the

option may use the EXT TCLK and EXT RCLK signals. Communication options would not normally
need to replicate the STP connector, since there would be no further options between the terminal and
the communications line.
7.7.5 Use With An External Processor
As long as control sequences used by the terminal controller to pass information to the terminal
processor are present in the terminal controller firmware, there is no reason to prevent an external
processor (host) from using them. This applies when the host CPU wishes to act as an enhancement to
the terminal, (Paragraph 7.7.3.2), but does not fit into the terminal cabinet. Such a capability is also
useful in writing and debugging programs that eventually run in a terminal resident, terminal processor. To allow this operation, a small interface card plugged into the STP does the following:
1.

Asserts OPTION PRESENT.

Provides a standard bit rate (known to the host) to INTERNAL RCLK and INTERNAL
TCLK. TC RCLK and TC TCLK would not be used directly, though DECREPTPARM
would advise the host of this information.

Passes through RXD, TXD, and all modem control signals. If the host needed to sense and
drive all modem signals, a special host interface might be required.

In this way, the host CPU can do a fairly good job of emulating the terminal processor and may
replace it in some applications.
7.7.6 Use With More Than One Option
While it is believed that multiple options can be supported on the STP, no detailed specifications for

such operation are given at this time. All options which plug into the STP must, however, replicate the
STP connector on the ““host” side of their interfaces, to allow for the addition of other options. The
only exceptions to this rule are those devices which must, by their very nature, be the “last’ device in
the terminal. Examples of such devices are a current loop adapter or modem.

7-14

CHAPTER 8
GRAPHICS CONNECTOR

8.1
INTRODUCTION
An 18 pin dual-in-line connector is provided in the VT100 for internal options that generate digital video
signals, and may additionally require 8-bit ASCII data forwarded by the VT100 from the communications line as specified below. An option not requiring all 18 signals may use a shorter connector
plugged into the appropriate set of holes on the graphics connector.
All signals below are identified as “to the VT100” (T) or “from the VT100” (F).

D7(F) 1
D6 (F) 2
DS(F)3
D4 (F)4
D3(F) 5
D2(F)6
D1(F)7
DO (F) 8
Signal Gnd 9

Pin Numbers
18 Signal Ground
17 (T) Graphic Video 1 L
16 (F) Vertical Blank L
15 (F) Graphic Write L
14 (F) Horizontal Blank H
13(F)INITH
12 (T) Graphic Video 2 L
11 (T) Graphic Flag L
10 (F) 24.0734 MHz Clock

Signal

Description

D7-DO0

During the VT100 “Graphic Processor On” mode (see Appendix A for
entry and exit), all characters transmitted to the VT100 on the
communications line are transferred to these data lines with a graphic
write strobe. The only characters not transmitted are the “Graphic
Processor Off”’ escape sequence. (Maximum load = two 74X
X loads
plus 50 pF.)

24.0734 MHz

VT100 Master Video Clock. (Maximum load = one 74SXX load.)

8-1

Signal

Description

Graphic Flag L

On initialization (between the time INIT H goes low and the first
character is transmitted to the graphics connector in “Graphic
Processor On” mode) the GRAPHIC FLAG will be checked. If the

flag is low, the VT 100 assumes the presence of an option on the
graphics connector and enters “Graphic Processor On” mode normally
upon receipt of the appropriate control. If the flag is high, the VT100
assumes that no option is installed and refuses to enter “Graphic
Processor On” mode. Afterinitialization a low on the GRAPHIC
FLAG indicates that the option is prepared to receive characters from
the VT100. A high GRAPHIC FLAG indicates the option is busy, the
VT100 stores incoming characters in its buffer and responds to the
host in its normal fashion if its buffer becomes full (see Appendix A
Communications Protocol). (Input load = one 74L.SXX load plus
4. 7K ohmsto+5V.)
INITH

The VT100 asserts this pin high whenever it begins an initialize
sequence (power-up or on command) and asserts INIT low whenever it
is ready to begin normal operation. The minimum high pulse width is
100 ms. (Maximum load = two 74XX loads plus 50 pF.)

Horizontal Blank H

Asserted high during VT 100 blank time. Used for horizontal sync and
toindicate the start of VT100 display.
Pulse period = 63.556 us
Pulse width = 11.465 us/80 column mode; 12.088 us/132 column
mode
Delay Falling Edge of HORIZONTAL BLANK H to First Dot from
VT100 = 500 ns/80 column mode; 250 ns /132 column mode
(Maximum load = one 74XX load plus 50 pF.)

Vertical Blank L

Asserted high only during displayed scans on the VT100. In all modes
the VT100 displays 240 complete scans/field. The VERTICAL
BLANK signal transitions between 1.2 us and 1.5 us after the rising
edge of HORIZONTAL BLANK H. (Maximum load = one 74XX
load plus 50 pF.)

GraphicVideol Land2 L

A truth table for the intensity of the display for different values of
these inputs is shown below. The table applies only to areas of the
screen that are otherwise black. When graphic data overlaps other
data in the VT100, the display is as bright or brighter than the values in
the table.

GVl
H
L
H
L

GV2
H
H
L
L

Intensity
Black
Dim
Normal
Bright

(Input load = one 74XX load plus 4.7K ohmto +5V.)

Signal

Description

Graphic Write L

This pinis pulsed low by the VT 100 during valid data on D7-D0. Data
(D7-D0) is stable 25 ns before the falling edge of GRAPHIC WRITE
and remains stable for 25 ns after the rising edge of GRAPHIC
WRITE. The pulse width low of GRAPHIC WRITE is 350 ns + 50

ns. (Maximum load = two 74X
X loads plus 50 pF.)
8.2 HARDCOPY ENABLE
Provision has been made in the VT 100 for the future addition of an external hardcopy option to record the
screen. Such a device is assumed to monitor the graphics connector to receive the “copy’” command and

to obtain its picture information from the composite video output. Upon receipt of the escape sequence
DECHCP (see Appendix), the VT100 will stop updating the screen but will not cease blinking operations. Following the freeze, the VT100 will write an 8-bit character of all ones (FFH) to the graphics
port. The GRAPHIC FLAG should go high when this character is transmitted; and the VT100 will maintain the screen frozen until the flag is seen to be low, at which time the VT100 will resume normal operation.

8-3

APPENDIX A

PROGRAMMING INFORMATION

The VTI100 terminal normally performs a two-part function. It is an input device to a computer information entered through the keyboard is sent to the computer. It is simultaneously an output
device for the computer - that is, data coming in from the computer is displayed on the video screen.
Figure A-1 shows the data flow.

This appendix discusses data flow between the VT 100 and the host. Included are the codes generated
by the keyboard; the transmission protocol followed by the terminal; and the actions and reactions of
the terminal to control codes and escape sequences, in both ANSI and VT52 modes of operation.
The VTI100 is an upward and downward software compatible terminal; that is, previous DEC video
terminals have DEC private standards for escape sequences. The American Standards Institute
(ANSI) has since standardized escape sequences in terminals. ANSI standards allow the manufacturer
in implementing each function. This appendix describes how the VT 100 responds to the implemented
ANSI control functions.

VT100

===

l
!

I
|

|
|

RECEIVER

COMPUTER

(HOST)

TRANSMITTER

[

~——

COMMUNICATION
KEYBOARD

LINES

Figure A-1 Terminal Data Flow

MA-1994

The VT100 is compatible with both the previous DEC standard and ANSI standards. Customers may
use existing DEC software designed around the VT52 or new VT100 software. The VT100 has a “VT52

compatible”” mode in which the VT100 responds to escape sequences like a VT52. In this mode, most
of the new VT100 features cannot be used.
Throughout this discussion references are made to “VT52 mode” or “ANSI mode.” These two terms

indicate the VT100’s software compatibility. All new software should be designed around the VT100
““ANSI mode.” Future DIGITAL vidgo terminals will not necessarily be committed to VT52 compatibility,
VT100 KEYBOARD

The VT100 keyboard (Figure A-2) has a key arrangement similar to an ordinary office typewriter. In

addition to the standard typewriter keys the VT 100 has additional keys and indicators that generate
escape and control sequences, cursor control commands, and to show the current terminal status.
The operator uses the keyboard to transmit codes to the host. Some keys transmit one or more codes
to the host immediately when typed. Other keys such as CTRL and SHIFT do not transmit codes
when typed, but modify the codes transmitted by other keys. The code-transmitting keys cause the
terminal to make a clicking sound to verify to the operator that the keystroke has been processed by

the terminal. If two code-transmitting keys are pressed together, two codes will be transmitted according to the order in which the keys were typed. The terminal does not wait for the keys to be lifted, but
transmits both codes as soon as possible after the keys are first typed. If three such keys are pressed
simultaneously, the codes for the first two keys are transmitted immediately; the code for the third is
transmitted when one of the first two keys is lifted.
LED Indicators
The keyboard has seven light emitting diodes (LEDs) of which two are committed to the complementary ON-LINE/LOCAL function. The power on condition is implicitly shown by one of the

two LEDs being on; that is, if the keyboard is connected and power is on, one of these LEDs is on.
A third LED indicates a ‘“keyboard locked” condition. In this condition the keyboard has been
“turned off’” automatically by the terminal due to a full buffer or by the host through the transmission

of an XOFF to the terminal.
The four remaining LEDs are programmable and can be assigned any meaning for specific appli-

cations. The code sequences to turn these LEDs on or off are discussed later.
SET-UP Key
The SET-UP key is at the upper-left corner of the main key array. Operations performed in SET-UP
mode can be stored in nonvolatile memory (NVR) so that turning terminal power off does not, by

itself, alter the terminal configuration.

The procedures to change the SET-UP features are provided in the operator’s information section of
this manual. SET-UP features that may be modified by the host are listed in Table A-1 and described
in detail under the escape sequences.
Alphabetic Keys

The VT100 transmits lowercase code unless either or both SHIFT keys are down, or unless the CAPS
LOCK key is down. Pressing CAPS LOCK locks only the 26 alphabetic keys in the shifted (uppercase)
mode. Table A-2 shows the codes generated by the alphabetic keys.

l4d

¢4d

vdd

}Od|nAH=M3a1v31i30

]

N)\‘é

|
]

Table A-1 SET-UP Features and Machine States

SET-UP Feature

Changeable
from Host

Saved in NVR
and Changeable

or Machine State

Computer*

in SET-UP

Alternate keypad mode
ANSI/VTS52
Auto repeat
AUTO XON XOFF
Bits per character
Characters per line
Cursor
Cursor key mode
Graphics mode
Interlace
New Line

Yes (DECKPAM/DECKPNM)
Yes (DECANM)
Yes (DECARM)
No
No
Yes (DECCOLM)
No
Yes (DECCKM)
Yes (DECGON/DECGOFF)
Yes (DECINLM)
Yes (LNM)

No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes

Keyclick

Yes

Margin bell

Yes

Origin mode
Parity
Parity sense
Power
Receive speed
Screen
Scroll
Tabs
Transmit speed
Wraparound

Yes (DECOM)
No
No
No
No
Yes (DECSCNM)
Yes (DECSCLM)
Yes (HTS/TBC)
No
Yes (DECAWM)

No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes

#39' (shifted)

* The appropriate control or escape sequence mnemonic is indicated in parentheses.

Table A-2 Alphabetic Key Codes (Octal)

Key

Uppercase

Lowercase

A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P

101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120

141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160

121

161

R
S
T
U
\'%
W
X
Y
Z

122
123
124
125
126
127
130
131
132

162
163
164
165
166
167
170
171
172

Nonalphabetic Keys

Each nonalphabetic key can generate two different codes. One code is generated if neither SHIFT key
is pressed. The other code is generated if either or both SHIFT keys are down. Unlike the shift lock key
of a typewriter, the CAPS LOCK key does not affect these keys; it affects only the alphabetic keys.

Table A-3 shows the nonalphabetic keys and the codes they generate.
Function Keys

Several keys on the keyboard transmit control codes. Control codes do not produce displayable characters but are codes for functions. If these codes are received by the terminal, the VT100 performs the
associated function shown in Table A-4.

Table A-3 Nonalphabetic Key Codes (Octal)

Neither SHIFT

Either or Both

Lowercase
Character

Key Down
(octal)

Uppercase
Character

SHIFT Keys Down
(octal)

061

041

062

063

#or L

043

064

044

065

045

066

A (circumflex)

136

067

046

070

052

071

(

050

060

)

051

055

— (underline)

137

075

(plus)

053

. (colon)

073

(colon)

072

(apostrophe)

047

(quote)

042

(comma)

054

074

(period)

056

076

/ (slash)

057

077

\ (backslash)
‘' (accent grave)

134
140

|
~

174
176

135

}

(minus)

}

133

{

100

(tilde)

173

175

A-6

Table A-4 Function Key Codes
Octal Value

of Code Sent

Action Terminal Would

Key

or Received
by VT100

Take if Host Sent That
Code

RETURN#*

015

Carriage return function

LINE FEED

012

Line feed

BACKSPACE

010

Backspace function

TAB

011

Tab function

SPACE BAR

040

Deposit space on screen; erase what

ESC

033

was there before
Initial delimiter of an escape sequence —

interpret following character string from
host as command, rather than display it
DELETE

177

Ignored by VT100

* RETURN key can be redefined so that it issues 015—012 (octal) (carriage return-line feed).
New Line feature in SET-UP mode provides this capability.

NO SCROLL - When NO SCROLL is pressed it generates a single XOFF code and inhibits further
scrolling. When pressed again the same key generates XON. In practice, if the software recognizes
XOFF, the host stops transmitting until NO SCROLL is pressed again to allow scrolling. If the
XOFF/XON feature is disabled (SET-UP function) NO SCROLL causes no action.
BREAK - Pressing BREAK forces the transmission line to its space state for 0.2333 seconds +10

percent. If either SHIFT key is down, the time increases to 3.5 seconds + 10 percent.
SHIFT and BREAK pressed together provide the long-break-disconnect function. Used with properly
configured modems with RS232-C levels, it disconnects both the local and remote data sets. For
modems connected via the 20 mA loop, issuing the long space may disconnect the remote data set only.

CONTROL and BREAK pressed together cause the transmission of the answerback message.
BREAK does not function when the VT100 is in LOCAL mode.

CTRL (Control) - CTRL is used in conjunction with other keys on the keyboard to generate control
codes. If CTRL is held down when any of the keys in Table A-5 are pressed, the code actually transmitted is in the range 000g-0375.
Auto Repeating

All keys auto repeat except: SET-UP, ESC, NO SCROLL, TAB, RETURN, and any key pressed with
CTRL. Auto repeating may be disabled (SET-UP function). Auto repeating works as follows: when a
key is pressed, its code(s) is sent once, immediately. If the key is held down for more than one-half
second, the code(s) is sent repeatedly at a rate of approximately 30 Hz (less if low transmit baud rates
are used) until the key is released.

Table A-5 Control Codes Generated
Key Pressed with
CTRL key down

(shifted or
unshifted)

Octal Code
Transmitted

Function
Mnemonic

Space Bar

000

NUL

A
B

001
002

SOH
STX

C
D
E

003
004
005

ETX
EOT
ENQ

006

ACK

007

BELL

H
I
J
K
L
M
N

010
011
012
013
014
015
016

BS
HT
LF
VT
FF
CR
SO

O
P
Q
R
S
T
U
\%
w
X
Y
Z
[
\
]

017
020
021
022
023
024
025
026
027
030
031
032
033
034
035

SI
DLE
DCI1 or XON
DC2
DC3 or XOFF
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS

~
?

RS
US

036
037

A-8

Cursor Control Keys
The keyboard contains four keys labeled with arrows in each of four directions. These keys transmit
escape sequences. If the host echoes these escape sequences back to the terminal, the cursor moves one
character up, down, right, or left. Table A-6 shows the escape sequences generated by each key.
AUXILIARY KEYPAD

The keys on the auxiliary keypad normally transmit codes for the numerals, decimal point, minus sign,
and comma. ENTER transmits the same code as RETURN. The host cannot tell if these keys were
pressed on the auxiliary keypad or on the main keyboard. Therefore, software that requires considerable numeric data entry need not be rewritten to use the keypad.

However, if software must distinguish between pressing a key on the auxiliary keypad and pressing the
corresponding key on the main keyboard, the host can give the terminal a command to place it in

keypad application mode. In keypad application mode all keys on the auxiliary keypad are defined to
give escape sequences that may be used by the host as user-defined functions.
The codes sent by the auxiliary keypad for the four combinations of the VT52/ANSI mode and

keypad numeric/application mode are shown in Tables A-7 and A-8. None of the keys are affected by
pressing SHIFT, CAPS LOCK, or CONTROL.

NOTE
In ANSI mode, if the codes are echoed back to the
VT100, or if the terminal is in local mode, the last

character of the sequence is displayed on the screen;
e.g., PF1 displays a “P.”

Table A-6 Cursor Control Key Codes

Cursor

VTS2

ANSI Mode and Cursor

Key

Mode

Key Mode Reset

Key Mode Set

Up
Down

ESC A
ESCB

ESC + A
ESC + B

ESCOA
ESCOB

Right

ESC C

ESC £ C

ESCOC

Left

ESCD

ESC+D

ESCOD

Mode

— O

Application

ESC?p

Numeric
Mode

ESC?r

Hh Wi

— O

Table A-7 VTS52 Mode Auxiliary Keypad Codes

ESC ? t

ESC? q
ESC ? s

ESC ? x
ESC?y

ESC? m

00O

ESC? w

39 ONWn

ESC?7v

ESC ? u

ENTER

Same as RETURN

ESC?M

PF1

ESCP

PE?2

ESC Q

PF3

ESCR

PF4

ESC S

ESC ? 1
ESC? n

— O

ESCOp

ESCOr

ESCO'
t

9O\ Wn

ESCOu

Mode

ESC
O x

Application

Mode

ESCOy

Wi
A~

Numeric

ESC
O m

ESC
O q

ESC
O s

ESCOv

ESCO
w

~»

O 00

ONw»n

— O

Table A-8 ANSI Mode Auxiliary Keypad Codes

ENTER

Same as RETURN

ESC
O M

ESCO1
ESCOn

PF1

ESCO
P

ESCOP

PE2

ESCO
Q

ESCOQ

PF3

ESCO
R

ESCOR

PF4

ESCOS

A-10

SPECIAL GRAPHICS CHARACTERS

If the Special Graphics set is selected, the graphics for ASCII codes 137g through 176g will be replaced
according to Table A-9. (See the SCS escape sequence.)
COMMUNICATION PROTOCOLS
Full Duplex

The terminal can operate at transmission speeds up to 19,200 baud. However, the terminal may not be
able to keep up with incoming data. The terminal stores incoming characters in a 64 character buffer
(128 characters in later model terminals) and processes them on a first-in/first-out basis. When the
content of the buffer reaches 48 characters, the terminal transmits 023g (XOFF or DC3). On this signal
the host should suspend its transmission to the terminal. Eventually, if the host stops transmitting, the
terminal depletes the buffer. When 16 characters remain in the buffer the terminal transmits 021g
(XON or DCI) to signal the host that it may resume transmission.
If the host fails to respond to an XOFF from the terminal in a timely manner, the buffer continues to
fill. When the 64-character capacity of the buffer is exceeded, a condition occurs called “‘buffer overflow.” To determine if the buffer will overflow use the following formulas:
No. of chars to overflow =
16 - [3 X (receiver speed/transmit speed)]
Time to respond to XOFF =

No. of chars to overflow X (bits/char + parity bit +

2)/receiver speed
Example
The VT100 is transmitting 8-bit characters with no parity at 1200 baud and receiving at 1200 baud. The

terminal has just sent an XOFF which the host must respond to within 0.1083 second to avoid a buffer
overflow.
No. of chars to overflow =

16- [(3 X 1200/1200)] = 13 chars
Time to respond to XOFF =
13 X (8+0+2)/1200 = 0.1083 sec
Example
The VTI100 is transmitting 7-bit characters with parity at 300 baud and receiving at 1200 baud. The

terminal has just sent an XOFF which the host must respond to within 0.0333 second to avoid a buffer
overflow.

No. of chars to overflow =
16 - [(3 X 1200/300)] = 4 chars
Time to respond to XOFF =
4 X (7+1+2)/1200 = 0.0333 sec

If the buffer overflows, the VT100 begins to discard incoming characters and the error character is
displayed.

A-11

Table A-9 Special Graphics Characters

Octal

US or UK

Code

Set

Special Graphics Set

137

—

140

Diamond

141

Checkerboard (error indicator)

142

HT (horizontal tab)

143
144

C
d

FF (form feed)
CR (carriage return)

145

LF (line feed)

146

Degree symbol

147

Plus/minus

150

NL (new line)

151

Vir

VT (vertical tab)

152

]

Lower-right corner

153

]

Upper-right corner

154

]

[

Upper-left corner

155

Lower-left corner

156

Crossing Lines

157

—

Horizontal line - scan 1

160

—

Horizontal line - scan 3

161

—

Horizontal line - scan 5

162

—

Horizontal line - scan 7

163

—

Horizontal line - scan 9

164

Left “T”

165

Right “T”

166

Bottom “T”’

167

Top “T”

170

Vertical bar

171

Less than or equal to

172

Greater than or equal to

174

Not equal to

176

Centered dot

173

175

}

Blank

Pi (mathematical)

UK pound symbol

NOTES

Codes 1525—1564, 1614, and 1643—1704 are used to draw rectangular grids. Each piece
of this line drawing set is contiguous with others so that the lines formed are unbroken.

Codes 1575 —1635 give better vertical resolution than dashes and underlines when drawing
graphs. Using these segments, 120 X 132 resolution may be obtained in 132 column mode
with the advanced video option installed.

A-12

Software that does not support receipt of XOFF/XON signals from the terminal can still use the
VT 100 provided the software never sends the ESC code to the terminal, the baud rate is limited to 4800
or less, and the software does not use smooth scrolling or split screen features.

Two of the terminal functions, Reset and Self-Test, reinitialize the terminal and erase the buffer. This
means that if characters are received subsequent to the commands to perform these two functions and
the characters are placed in the buffer, the character would be destroyed without being processed.
To compensate for this, the host may act in one of two ways.

Immediately after sending the terminal the commands to perform either the Reset or SelfTest functions, the host may act as if it had received XOFF from the terminal, thus sending
no more characters until it receives XON. The terminal transmits XON only after it completes the specified operation and the XOFF/XON feature is enabled.

When the first method cannot be implemented, a delay of no less than 10 seconds may be
used to allow the terminal time to complete the invoked function. This method, however,
does not guarantee against the loss of data when an invoked function has detected an error.
And while this delay is currently adequate, future options may require a change in the time
delay.

The XOFF/XON synchronization scheme has an advantage over requiring the host to insert delays or
filler characters in its data stream. Requiring a minimum of software support, XON /XOFF ensures
that every character or command sent to the VT 100 is processed in correct order. It frees interface
programs from all timing considerations and results in more reliable operation.
In addition to the buffer-filling condition, there are two other means of transmitting XOFF and XON:
the NO SCROLL key, and Control S/Control Q. If XOFF mode is enabled, the VT 100 coordinates
these three sources of XOFF and XON so that the desired effect occurs. For example, if the bufferfilling condition has caused an XOFF to be sent and then the operator presses NO SCROLL, a second
XOFF is not sent. Instead of sending an XON when the buffer empties, the VT100 waits until the
operator presses NO SCROLL again before sending XON.

Also, entering SET-UP mode causes the VT100 to temporarily stop taking characters from the buffer.
An XOFF is sent if the buffer becomes nearly full.
Control S and Control Q are also synchronized with the NO SCROLL key.

If the XOFF feature is disabled, the buffer-filling condition does not send an XOFF, the NO SCROLL
key is disabled, and Control S and Control Q are transmitted as typed.

The VT100 also recognizes received XOFF and XON. Receipt of XOFF inhibits the VT100 from
transmitting any codes except XOFF and XON. From three to seven keystrokes on the keyboard are
stored in a keyboard buffer (some keys transmit two or three codes, e.g., cursor controls). If the
keyboard buffer overflows, keyclicks stop and the KBD LOCKED LED lights. Transmission resumes
upon receipt of XON.
If the user transmits an XOFF to the host (by Control S or NO SCROLL), the host should not echo

any further type-in until the user types XON. This places the burden of not overloading the host’s
output buffer on the user.
Entering and exiting SET-UP clears the transmit and keyboard locked modes.

A-13

TERMINAL CONTROL COMMANDS

The VT100 has many control commands that cause it to take action other than displaying a character

on the screen. In this way, the host commands the terminal to move the cursor, change modes, ring the
bell, etc. The following paragraphs discuss terminal control commands.
Control Characters

Control characters have values of 000g-037g, and 177g. The control characters recognized by the
VTI100 are shown in Table A-10. All other control codes cause no action to be taken.

Escape Sequences

Table A-11 provides a summary of the VT 100 escape sequences.
ANSI Compatible Mode
Cursor Movement Commands

Cursor up
Cursor down
Cursor forward (right)
Cursor backward (left)
Direct cursor addressing

ESC [ Pn A
ESC [ Pn
ESC | Pn C
ESC [ Pn
ESC | Pl Pc H * or
-ESC [ Pl; Pcf *

Index
Reverse index
Save cursor and attributes
Restore cursor and attributes

ESCD
ESCM
ESC 7
ESC 38

*Pl = line number; Pc = column number.
NOTE
Pn refers to a decimal parameter expressed as a

string of ASCII digits. Multiple parameters are sep-

arated by the semicolon character (073g). If a parameter is omitted or specified to be 0 the default
parameter value is used. For the cursor movement
commands, the default parameter value is 1.
Line Size (Double-height and Double-width) Commands

Change this line to double-height top half
Change this line to double-height bottom half
Change this line to single-width single-height
Change this line to double-width single-height

ESC#3
ESC#4
ESC#5
ESC#6

Character Attributes
ESC [ Ps;Ps;Ps;....;Ps m

Ps refers to a selective parameter. Multiple parameters are separated by the semicolon character (073g).
The parameters are executed in order and have the following meanings.
0 or none
]

All attributes off
Bold on

4
5
7

Underscore on
Blink on
Reverse video on

Any other parameter values are ignored.
A-14

Table A-10 Control Characters
Control

Octal

Character

Code

NUL

000

Action Taken
Ignored on input (not stored in input buffer
see full duplex protocol)

ENQ

005

Transmit answerback message

BEL

007

Sound bell tone from keyboard

010

Move cursor left one character position, unless
it is at left margin, in which case, no action
occurs

011

Move cursor to next tab stop, or to right margin

012

013

Interpreted as LF

if no further tab stops are present on line

Causes line feed or new line operation. (See
new line mode.)

014

Interpreted as LF

015

Move cursor to left margin on current line

016

Select G1 character set, as selected by “ESC)”
sequence

017

Select GO character set, as selected by “ESC (”
sequence

XON

021

Terminal resumes transmission

XOFF

023

Terminal stops transmitting all codes except

XOFF and XON
CAN

030

If sent during escape or control sequence,
sequence is immediately terminated and not
executed. Also causes error character to be

displayed.
SUB

032

Interpreted as CAN

ESC

033

Introduces an escape sequence

DEL

177

Ignored on input (not stored in input buffer)

A-15

Table A-11 VT100 Escape Sequences Summary

Feature

VT52 Compatible Mode

Cursor Up

ESC A

Cursor Down
Cursor Right

ESCB

ESC C
ESCD
ESCF

Cursor Left
Select Special Graphics character set
Select ASC11 character set
Cursor to home
Reverse line feed
Erase to end of screen
Erase to end of line
Direct cursor address
Identify
Enter alternate keypad mode
Exit alternate keypad mode
Graphics processor on
Graphics processor off
Enter ANSI mode

ESCG
ESC H
ESC 1
ESCJ
ESCK
ESC Ylc (see note 1)
ESC Z (see note 2)
ESC =
ESC >
ESC 1 (see note 3)
ESC 2 (see note 3)
ESC <

Note 1

Line and column numbers for direct cursor address are single character codes whose values are the
desired number plus 37g. Line and column numbers start at 1.
Note 2

Response to ESC Z is ESC / Z.
Note 3

Ignored if no graphics processor option is installed in the VT100.

Erasing
From cursor to end of line

From beginning of line to cursor
Entire line containing cursor
From cursor to end of screen
From beginning of screen to cursor
Entire screen

ESC[KorESC[OK
ESC[I1K
ESC[2K
ESC[JorESC[O]J
ESC[11]
ESC[2]

Programmable LEDs
ESC [ Ps; Ps;...Ps g

Ps are selective parameters separated by semicolons (073g) and executed in order, as follows.
0 or none
1
2
3
4

All LEDs off
LED #1 on
LED #2 on
LED #3 on
LED #4 on

Any other parameter values are ignored.

A-16

Character Sets (G0 and G1 Designators)
The GO and G1 character sets are designated as follows:

Character Set
United Kingdom (UK)
United States (USASCII)
Special graphics characters
and line drawing set
Alternate character ROM
Alternate character ROM
special graphics characters

GO
ESC (A
ESC (B
ESC (0

Gl
ESC)A
ESC)B
ESC)O0

ESC (1
ESC (2

ESC) 1
ESC) 2

Scrolling Region
ESC[Pt; Pbr
Pt is the number of the top line of the scrolling region. Pb is the number of the bottom line of the
scrolling region and must be greater than Pc.
Tab Stops

Set tab at current column
Clear tab at current column
Clear all tabs

ESCH
ESC[gor ESC[0g
ESC[3g

Modes

To Set
Mode Name

Mode

Sequence

Line feed/new line
Cursor key mode
ANSI/VTS52
Column mode
Scrolling mode
Screen mode
Origin mode
Wraparound
Auto repeat
Interlace
Graphic proc. opt.
Keypad mode

New line

ESC [20h

Application
ANSI
132 column
Smooth
Reverse
Relative
On
On
On
On
Application

ESC [?1h
N/A
ESC [?3h
ESC [74h
ESC [?5h
ESC [?6h
ESC [?7h
ESC [?8h

ESC [?79h
ESC 1
ESC =

To Reset
Sequence
Line feed
ESC [20]

Mode

Cursor
VT52
80 column
Jump
Normal
Absolute
Off
Off
Off
Off
Numeric

Reports

Cursor Position Report

Invoked by
Response is

ESC[6n
ESC [ PI; Pc R (Pl = line number and

Pc = column number)

Status Report
Invoked by
Response is

ESC[5n
ESC [ 0 n (terminal ok)
ESC [ 3 n (terminal not ok)

A-17

ESC [?11]
ESC [?72]
ESC [?31]
ESC [74]
ESC [?5]
ESC [?6]
ESC [77]
ESC [?8]
ESC [791
ESC2
ESC >

What Are You

Invoked by

ESC [c
or

ESC[Oc
Response is

ESC[?1;Psc

Ps 1s the ““option present’” parameter with the following meaning.
Ps

Meaning

0
1
2

Base VT 100, no options
Processor option (STP)
Advanced video option (AVO)

AVO and STP

Graphics processor option (GO)

5
6
7

GO and STP
GO and AVO
GO, STP,and AVO

Alternately invoked by ESC Z (not recommended). Response is the same.
Reset

Reset causes the power-up reset routine to be excecuted.
ESC ¢

Confidence Tests
Fill screen with “Es”’
Invoke test(s)

ESC #8
ESC[2;Psy

Ps is the parameter indicating the test to be done and is a decimal number computed by taking the
“weight” indicated for each desired test and adding them together.

Test
Power-up self test
(ROM checksum, RAM, NVR, keyboard
and AVO if installed)

Weight
1

Data loopback

2 (Loopback connector
required)

Repeat selected tests(s)
indefinitely (until failure or
power off)

A-18

Valid ANSI Mode Escape Sequences (Detailed)

Definitions - The following listing defines the basic elements of the ANSI mode escape sequences.

Control sequence introducer (CSI) - An escape sequence that provides supplementary controls and is
itself a prefix affecting the interpretation of a limited number of contiguous characters. In the VT100
the CSI 1s ESC [.

Parameter - (1) A string of one or more decimal characters that represent a single value; (2) The value
so represented.

Numeric Parameter — A string of characters that represent a number, designated by Pn. Pn has a range
of 0 (60g) to 9 (71y).

Selective Parameter — A string of characters that selects a subfunction from a specified list of subfunctions, designated by Ps. In general, a control sequence with more than one selective parameter
causes the same effect as several control sequences, each with one selective parameter, e.g., CSI Psa;
Psb; Psc F is identical to CSI Psa F CSI Psb F CSI Psc F.
Ps is a string of zero or more characters with a range of 0 (60g) to 9 (71g) with each selective parameter
separated from the other by; (73g).

Default - A function-dependent value assumed when no explicit value, or a value of 0, is specified.
Final character - A character whose bit combination terminates an escape or control sequence.
Escape sequences - All of the following escape and control sequences are transmitted from the host
computer to the VT100 unless otherwise noted. All of the escape sequences are a subset of those

specified in ANSI X3.64 1977 and ANSI X3.41 1974,

A-19

CPR

Cursor Position Report - VT100 to Host

Format: ESC[ Pn; Pn R

default values: 1

The CPR sequence reports the active position by means of the parameters. This sequence has two
parameter values, the first specifying the line and the second specifying the column. The default condition with no parameters present, or parameters of 0, is equivalent to a cursor at home position.

Numbering of lines depends on the state of the Origin mode (DECOM).
This control sequence is solicited by a device status report (DSR) sent from the host.

CUB

Cursor Backward - Host to VT100 and VT100 to Host

Editor Function; format: ESC[PnD

default value: 1

The CUB sequence moves the active position to the left. The distance moved is determined by the
parameter. If the parameter value is zero or one, the active position moves one position to the left. If
the parameter value is n, the active position moves n positions to the left. If an attempt is made to
move the cursor to the left of the left margin, the cursor stops at the left margin.
CUD

Cursor Down - Host to VT100 and VT100 to Host

Editor Function; format: ESC[ PnB

default value: 1

The CUD sequence moves the active position downward without altering the column position. The
number of lines moved is determined by the parameter. If the parameter value is zero or one, the active
position moves one line downward. If the parameter value is n, the active position moves n lines
downward. If an attempt is made to move the cursor below the bottom margin, the cursor stops at the
bottom margin.

CUF

Cursor Forward - Host to VT100 and VT100 to Host

Editor Function; format: ESC[ Pn C

default value: 1

The CUF sequence moves the active position to the right. The distance moved is determined by the
parameter. A parameter value of zero or one moves the active position one position to the right. A
parameter value of n moves the active position n positions to the right. If an attempt is made to move
the cursor to the right of the right margin, the cursor stops at the right margin.
CUP

Cursor Position

Editor Function; format: ESC [ Pn; Pn H

default value: 1

The CUP sequence moves the active position to the position specified by the parameters. This sequence has two parameter values, the first specifying the line position and the second specifying the
column position. A parameter value of zero or one for the first or second parameter moves the active
position to the first line or column in the display, respectively. The default condition with no parameters present is equivalent to a cursor to home action. In the VT 100, this control behaves identically
with its format effector counterpart, HVP.

The numbering of lines depends on the state of the Origin mode (DECOM).

A-20

CUU

Cursor Up - Host to VT100 and VT100 to Host

Editor Function; format: ESC[ Pn A

default value: 1

This sequence moves the active position upward without altering the column position. The number of
lines moved is determined by the parameter. A parameter value of zero or one moves the active
position one line upward. A parameter value of n moves the active position n lines upward. If an
attempt 1s made to move the cursor above the top margin, the cursor stops at the top margin.
DA

Device Attributes

Format: ESC[Pnc

default value: 0

The hqst requests the VT100 to send a device attributes (DA) control sequence to identify
itself by sending the DA control sequence with either no parameter or a parameter of 0.

Response to the request described above (VT 100 to host) is generated by the VT 100 as a DA
control sequence with the numeric parameters as follows:
Option Present
No options
Processor option (STP)
Advanced video option (AVO)
AVO and STP
Graphics option (GO)
GO and STP
GO and AVO
GO, STP, and AVO

DECALN
Format:

Sequence Sent
ESC [71;0c
ESC [?1;1c
ESC [?1;2c
ESC [?1;3c
ESC [?1;4c¢
ESC [?1;5c¢
ESC [?1;6¢
ESC [?1;7c

Screen Alignment Display (DEC Private)
ESC #8

This command fills the entire screen area with uppercase Es for screen focus and alignment. This
command is used by DEC manufacturing and Field Service personnel.
DECANM

ANSI/VTS52 Mode (DEC Private)

This is a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. The
reset state causes only VT52 compatible escape sequences to be interpreted and executed. The set state
causes only ANSI ‘“‘compatible’ escape and control sequences to be interpreted and executed.
DECARM

Auto Repeat Mode (DEC Private)

This is a private parameter applicable to set mode (SM) and reset mode.(RM) control sequences. The
reset state causes no keyboard keys to autorepeat. The set state causes certain keyboard keys to autorepeat.

DECAWM

Autowrap Mode (DEC Private)

This is a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. The
reset state causes any displayable characters received when the cursor is at the right margin to replace
any previous characters there. The set state causes these characters to advance to the start of the next
line, doing a scroll up if required and permitted.
A-2]

DECCOLM

Column Mode (DEC Private)

This is a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. The
reset state causes a maximum of 80 columns on the screen. The set state causes a maximum of 132

columns on the screen.
DECCKM

Cursor Keys Mode (DEC Private)

This 1s a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. This

mode is only effective when the terminal is in keypad application mode (see DECKPAM) and the
ANSI/VT52 mode (DECANM) is set (see DECANM). Under these conditions, if the cursor key mode
is reset, the four cursor function keys send ANSI cursor control commands. If cursor key mode is set,

the four cursor function keys send application functions.
DECDHL

Format:

Double-Height Line (DEC Private)

Top Half: ESC #3, Bottom Half: ESC #4

These sequences cause the line containing the active position to become the top or bottom half of a

double-height double-width line. The sequences must be used in pairs on adjacent lines and the same
character output must be sent to both lines to form full double-height characters. If the line was singlewidth single-height, all characters to the right of the center of the screen are lost. The cursor remains

over the same character position unless it would be to the right of the right margin, in which case it is
moved to the right margin.
DECDWL

Format:

Double-Width Line (DEC Private)

ESC #6

This sequence causes the line that-contains the active position to become double-width, single-height.
If the line was single-width, single-height, all characters to the right of screen center are lost. The

cursor remains over the same character position unless it would be to the right of the right margin, in
which case, it is moved to the right margin.
DECGOFF
Format:

Graphics Processor OFF (DEC Private)

ESC 2

Turn off the graphics processor.
NOTE
Some DEC hardcopy terminals interpret this private
escape sequence as CLEAR TABS.

DECGON
Format:

Graphics Processor On (DEC Private)
ESC 1

All subsequent characters are interpreted as commands or data to the graphics processor option. The
terminal remains in this mode until the graphics processor off command is received. This command is
ignored if no graphics processor option is installed.

A-22

NOTE

Some DEC hardcopy terminals interpret this private
escape sequence as SET TAB.
DECHCP Hard Copy (DEC Private)
Format:

ESC #7

This sequence causes the screen to cease updating and freeze while the hardcopy output is enabled. The

screen resumes normal operation when the hardcopy has been completed. This command is ignored if
no hardcopy option is installed.
DECID

Identify Terminal (DEC Private)

Format:

ESC Z

This sequence causes the same response as the ANSI device attributes (DA). DECID will not be
supported in future DEC terminals, therefore, DA should be used by any new software.
DECINLM

Interlace Mode (DEC Private)

This is a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. The
reset state (noninterlace) causes the video processor to display 240 scan lines per frame. The set state
(interlace) causes the video processor to display 480 scan lines per frame. There is no increase in
character resolution.
DECKPAM
Format:

Keypad Application Mode (DEC Private)

ESC =

Auxiliary keypad keys and cursor control keys transmit escape sequences.

DECKPNM Keypad Numeric Mode (DEC Private)
Format:

ESC >

Auxiliary keypad keys send ASCII codes corresponding to the characters on the keys. Cursor control
keys send cursor controls.
DECLL

Load LEDs (DEC Private)

Format: ESC [ Ps q

default value: 0

Load the four programmable LEDs on the keyboard according to the parameter(s).
Parameter

Meaning

Clear LEDs 1 through 4

Light LED 1

Light LED 2

3
4

Light LED 3
Light LED 4

LED numbers are indicated on the keyboard.

A-23

DECOM

Origin Mode (DEC Private)

This 1s a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. The
reset state causes the origin to be at the upper-left character position on the screen. Line numbers are

therefore independent of current margin settings. The cursor may be positioned outside the margins
with a cursor position (CUP) or horizontal and vertical position (HVP) control.

The set state causes the origin to be at the upper-left character position within the margins. Line
numbers are therefore relative to the current margin settings. The cursor cannot be positioned outside

the margins.
The cursor moves to the new home position when this mode is set or reset.
Lines and columns are numbered consecutively, with the origin being line 1, column 1.
DECRC

Restore Cursor

Format:

ESC 8

(DEC Private)

This sequence causes the previously saved cursor position, graphic rendition, and character set to be
restored.
DECREPTPARM

Format:

Report Terminal Parameters

ESC [ <sol>; <par>; <nbits>; <xspeed>; <rspeed>; <clkmul>; <flags>x

These sequence parameters are explained below in the DECREQTPARM sequence.
DECREQTPARM

Format:

Request Terminal Parameters

ESC|[ <sol>x

This sequence is sent by the terminal controller to notify the host of the status of selected terminal parameters. The status sequence may be sent when requested by the host or at the terminal’s discretion.
DECREPTPARM is sent upon receipt of a DECREQTPARM.

A-24

The meanings of the sequence parameters are:
Parameter

Value

<sol>

O or none

Meaning
This message is a request ( DECREQTPARM). The terminal is

allowed to send unsolicited reports.
This message is a request. From now on the terminal may only
report in response to a request.
This message is a report (DECREPTPARM).
This message is a report and the terminal is only reporting on

<nbits>

[S—

<par>

request.

8 bits per character
7 bits per character
Bits per second
50
75

110

134.5

150

200

48
56

300
600

64
72

1200
1800

2000

2400

96
112

3600
4800
9600

120

19,200

104

No parity set
Parity is set and odd
Parity is set and even

The bit rate multiplier is 16.
0-15

This value communicates the four switch values in block 5 of SET

UP B, which are only visible to the user when an STP option is
installed. These bits may be assigned for an STP device. The four
bits are a decimal-encoded binary number.

A-25

DECSC

Save Cursor (DEC Private)

Format:

ESC7

This sequence causes the cursor position, graphic rendition, and character set to be saved. (See DECRC.)
DECSCLM

Scrolling Mode (DEC Private)

This is a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. The
reset state causes scrolls to “jump’ instantaneously. The set state causes scrolls to be ‘““smooth” at a maximum rate of six lines per second.

DECSCNM

Screen Mode (DEC Private)

This is a private parameter applicable to set mode (SM) and reset mode (RM) control sequences. The
reset state causes the screen to be black with white characters. The set state causes the screen to be white
with black characters.
DECSTBM

Set Top and Bottom Margins (DEC Private)

Format: ESC[Pn; Pnr

default values: (see below)

This sequence sets the top and bottom margins to define the scrolling region. The first parameter is the
line number of the first line in the scrolling region. The second parameter is the line number of the bottom
line in the scrolling region. Default is the entire screen (no margins). The minimum size of the scrolling
region allowed is two lines, 1.e., the top margin must be less than the bottom margin.
DECSWL
Format:

Single-Width Line (DEC Private)
ESC #5

This causes the line that contains the active position to become single-width, single-height. The cursor
remains on the same character position. This is the default condition for all new lines on the screen.
DECTST
Format:

Invoke Confidence Test
ESC[2;Psy

Ps is the parameter indicating the test to be done. Ps is computed by taking the weight indicated for each
desired test and adding them together. If Ps is 0 no test is performed but the VT100 is reset.
Test
Power up self-test (ROM checksum,
RAM, NVR keyboard and AVO if

Weight
1

installed)

Data Loopback

2 (loopback connector

Repeat selected test(s)

required)

indefinitely (until failure or
power off)

A-26

DSR

Device Status Report

Format: ESC|[Psr

default value: 0

Requests and reports the general status of the VT100 according to the following parameter(s).
Parameter
0

Meaning

Response from VT100 — malfunction —retry

Command from host — please report status (using a DSR control sequence)

Command from host — please report active position (using a CPR control sequence)

Response from VT 100 —ready, no malfunctions detected (default)

DSR with a parameter value of 0 or 3 is always sent as a response to a requesting DSR with a parameter
value of 3.
ED

Erase In Display

Editor Function; format: ESC[Ps J

default value: 0

This sequence erases some or all characters in the display according to the parameter. Any complete line
erased by this sequence returns that line to single-width mode.

Parameter

Meaning
Erase from the active position to the end of the screen, inclusive (default).

Erase from start of the screen to the active position, inclusive.

Erase all of the display — all lines are erased, changed to single-width, and the cursor
does not move.

EraseIn Line

Editor Function; format: ESC| Ps K

default value: 0

Erases some or all characters in the active line according to the parameter.
Parameter
0

Meaning
Erase from the active position to the end of the line, inclusive (default).

Erase from the start of the screen to the active position, inclusive.

Erase all of the line, inclusive.

HTS

Horizontal Tabulation Set

Format Effector; format: ESC H

Set one horizontal stop at the active position.

A-27

HVP

Horizontal and Vertical Position

Format Effector, format: ESC[ Pn; Pnf

default value: 1

Moves the active position to the position specified by the parameters. This sequence has two parameter
values; the first specifies the line position, the second specifies the column. A parameter value of either
zero or one causes the active position to move to the first line or column in the display, respectively. The
default condition with no parameters present moves the active position to the home position. In the
VT100, this control behaves identically with its editor function counterpart, CUP. Numbering lines and

columns depends on the reset or set state of the origin mode (DECOM).
IND

Index

Format Effector; format: ESC D
This sequence causes the active position to move downward one line without changing column position. If

the active position is at the bottom margin, a scroll up is performed.
LNM

Line Feed/New Line Mode

This is a parameter applicable to set mode (SM) and reset mode (RM) control sequences. The reset state
causes the interpretation of the line feed (LF), defined in ANSI Standard X3.4-1977, to imply only vertical movement of the active position and causes the return key (CR) to send the single code CR. The set
state causes the LF to imply movement to the first position of the following line and causes the return key
to send the two codes (CR, LF). This is the new line (NL) option.

This mode does not affect the index (IND), or next line (NEL) format effectors.
NEL

Next Line

Format Effector; format: ESC E

This sequence causes the active position to move to the first position on the next line downward. If the
active position is at the bottom margin, a scroll up is performed.
RI

Reverse Index

Format Effector; format: ESC M

Moves the active position to the same horizontal position on the preceding line. If the active position is at
the top margin, a scroll down is performed.
RIS

Reset to Initial State

Format:

ESC c

Resets the VT 100 to its initial state, i.e., the state it has after it is powered on. This also causes the
execution of the power-up self test and signal INIT H to be asserted briefly.

A-28

Reset Mode

Format: ESC|[ Ps ;Ps ;...; Psl

default value: none

Resets one or more VIT100 modes as specified by each selective parameter in the parameter string.
Each mode to be reset is specified by a separate parameter. (See modes and set mode (SM) following
this section.)
SCS

Select Character Set

The appropriate GO and G1 character sets are selected from the five possible character sets. GO and G1
are selected by codes SI and SO (shift in and shift out) respectively.
GO Sets
Sequence
ESC (A
ESC (B
ESC (0
ESC (1

G1 Sets
Sequence
ESC)A
ESC)B
ESC)O0
ESC) 1

ESC (2

ESC)2

Meaning

United Kingdom set
ASCII set
Special graphics
Alternate character ROM
Standard character set
Alternate character ROM
Special graphics

The United Kingdom and ASCII sets conform to the “ISO international register of character sets to be
used with escape sequences.”’ The other sets are private character sets. Special graphics means that the
graphic characters for the codes 137g to 176g are replaced with other characters. The specified character set will be used until another SCS is received.
SGR

Select Graphic Rendition

Format Effector; format: ESC [ Ps;...; Psm

default value: 0

Invoke the graphic rendition specified by the parameter(s). All following characters transmitted to the
VTI100 are rendered according to the parameter(s) until the next occurrence of SGR.
Parameter

Meaning

0
1
4
5
7

Attributes off
Bold or increased intensity
Underscore
Blink
Negative (reverse) image

All other parameter values are ignored.
Without the advanced video option only one character attribute is possible as determined by the cursor

selection. In that case specifying either the underscore or the reverse attribute activates the currently
selected attribute.

A-29

Set Mode

Format: ESC[ Ps;...; Psh

default value: none

Causes one or more modes to be set within the VT 100 as specified by each selective parameter in the
parameter string. Each mode to be set is specified by a separate parameter. A mode is considered set
until it is reset by a reset mode (RM) control sequence.
TBC

Tabulation Clear

Format Effector; format: ESC[ Ps g

default value: 0

Parameter

Meaning

Clear the horizontal tab stop at the active position (the default case).

Clear all horizontal tab stops.

Any other parameter values are ignored.

MODES

The following VT 100 modes may be changed with set mode (SM) and reset mode (RM)
controls.

ANSI Specified Modes
Mode

Parameter
0
20

Mnemonic

LNM

Function
Error (ignored)
Line feed new line mode

DEC Private Modes

If the first character in the parameter string is ? (77g), the parameters are interpreted as DEC private
parameters according to the following modes:
Mode

Parameter
0
1
2
3
4
5
6
7
8
9

Mnemonic
DECCKM
DECANM
DECCOLM
DECSCLM
DECSCNM
DECOM
DECAWM
DECARM
DECINLM

Function
Error (ignored)
Cursor key
ANSI/VTS2
Column
Scrolling
Screen
Origin
Auto wrap
Auto repeating
Interlace

Any other parameter values are ignored.

A-30

The following modes, specified in ANSI X3.64-1977 standard, may be considered to be permanently
set, permanently reset, or not applicable, as noted. Refer to that standard for further information
concerning these modes.

Mnemonic
CRM
EBM
ERM
FEAM
FETM
GATM
HEM
IRM
KAM
MATM
PUM
SATM
SRTM
TSM
TTM
VEM

Function
Control representation
Editing boundary
Erasure
Format effector action
Format effector transfer
Guarded area transfer
Horizontal editing
Insertion-replacement
Keyboard action
Multiple area transfer
Positioning unit
Selected area transfer
Status reporting transfer
Tabulation stop
Transfer termination
Vertical editing

State
Reset
Reset
Set
Reset
Reset
NA
NA
Reset
Reset
NA
Reset
NA
Reset
Reset
NA
NA

Valid VT52 Mode Escape Sequences (detailed)
Graphics Processor On
Format:

ESC 1

All subsequent characters are interpreted as commands to the graphics option until the graphics processor off command is received. This sequence is ignored if no graphics processor is installed.
Graphics Processor Off
Format:

ESC 2

Turn off the graphics processor.
Cursor Up
Format:

ESC A

Move the active position upward one position without altering the horizontal position. If an attempt is
made to move the cursor above the top margin, the cursor stops at the top margin.
Cursor Down
Format:

ESCB

Move the active position downward one position without altering the horizontal position. If an attempt is made to move the cursor below the bottom margin, the cursor stops at the bottom margin.

A-31

Cursor Right

Format:

ESC C

Move the active position to the right. If an attempt is made to move the cursor to the right of the right
margin, the cursor stops at the right margin.
Cursor Left
Format:

ESCD

Move the active position one position to the left. If an attempt is made to move the cursor to the left of
the left margin, the cursor stops at the left margin.
Enter Graphics Mode

Format:

ESCF

Causes the special graphics character set to be used.
NOTE
The special graphics characters in the VT 100 are dif-

ferent from those in the VTS2.
Exit Graphics Mode
Format:

ESC G

This sequence causes the standard ASCII character set to be used.
Cursor to Home
Format:

ESCH

Move the cursor to the home position.
Reverse Line Feed

Format:

ESCI

Move the active position upward one position without altering the column position. If the active
position is at the top margin, a scroll down is performed.
Erase to End of Screen
Format:

ESCJ

Erase all characters from the active position to the end of the screen. The active position is not
changed.
Erase to End of Line
Format:

ESC K

A-32

Erase all characters from the active position to the end of the current line. The active position is not
changed.
Direct Cursor Address
Format:

ESC Y line column

Move the cursor to the specified line and column. The line and column numbers are sent as ASCII
codes whose values are the number plus 037g. For example, 040g refers to the first line or column, 050g

refers to the eighth line or column, etc.
Identify

Format:

ESC Z

Causes the terminal to send its identifier escape sequence to the host. The sequence is: ESC / Z.
NOTE
Information regarding options must be obtained in
ANSI mode, using the device attributes (DA) control
sequence.

Enter Alternate Keypad Mode

Format:

ESC =

Auxiliary keypad keys send unique identifiable escape sequences for use by applications programs.
Exit Alternate Keypad Mode
Format:

ESC >

Auxiliary keypad keys send ASCII codes for functions or characters on the key.
Enter ANSI Mode

Format:

ESC <

All subsequent escape sequences will be interpreted according to ANSI Standards X3.64-1977 and
X3.41-1974. The VT52 escape sequence in this section will not be recognized.

A-33

APPENDIX B

RECOMMENDED SPARES LIST (RSL)

VT100 RECOMMENDED SPARES LIST (RSL)

Table B-1 lists the recommended spares for the basic VT 100. The list includes spares for the advanced
video option and the 20 mA current loop adapter option.

VT100 WA RECOMMENDED SPARES LIST (RSL)
Table B-2 lists the VT 100 WA recommended spares. This spares kit requires that the VT 100 spares kit

be available.
VT105 RECOMMENDED SPARES LIST (RSL)

Table B-3 lists the VT 105 recommended spares. This spares kit requires that the VT 100 spares kit be
available.
VT132 RECOMMENDED SPARES LIST (RSL)

Table B-4 lists the VT132 recommended spares. This spares kit requires that the VT 100 spares kit be
available.

B-1

Table B-1 Recommended Spares

Qty

Description

Part No.

1
1

Monitor printed circuit board (Ball)
Flyback transformer, Ball monitor

30-14590-02
30-14590-01

Monitor printed circuit board, Elston

30-16080-02

Flyback and choke assy, Elston

30-16080-04

Terminal controller PCB

54-13009

Advanced video PCB

54-13097

20 mA adapter assembly

70-15273

20 mA interface cable (15 ft)

BCOS5SF-15

EIA cable (M-F) (10 ft)

BCO5D-10

EIA cable (null modem)

BCO3M-10

LK keyboard

70-15765

Cable assembly, keyboard

70-14652

Speaker

12-15050

LKO7 keycap set

12-14333-72

LKO8 keycap set

12-14333-91

Keycap removal tool

74-16355

Power supply assembly

70-14979

Power switch

Voltage select switch,

Fuse, 3 A

90-07217

Linecord, 115V

170083-09

Line cord, 230 V

170083-10

DC power distribution cable

70-14978

Card guide

5
5
5

Retainer ring*
Support, chassis*
Cable clamp*

12-12405-00
90-10007
90-09747-01
90-10016-00

Plunger, chassis mounting*

90-09964

Grommet, chassis*

90-09966-01

5
15

Captive screw*
Plunger, base mounting*

12-14811
12-14740-00

15
5
15
5
5

Plunger, base mounting*
Standoff, AVO*
Grommet, base*
Mounting screw*
Feet*

Fuse holder*

90-09965-00
90-09747-03
90-09966-00
12-14817
90-09624-00
12-12893

12-15232

110 V/220V

12-14155-03

* These items are expendable.

B-2

Table B-1 Recommended Spares (Cont)
Qty

Description

Part No.

5
5
1
1
1
1
1
1
1
1

Screw, #6-20 X 1/2, hex head
Screw, #6-32 X 5/16
CRT mask, alignment
CRT mask, character alignment
Shaft extender
Alignment tool, monitor
Kit, carrying case
I.C. container
Loopback connector, RS232C
Loopback connector, 20 mA

90-09680-04
90-09701-00
94-03220-03
94-03270-03
29-23189-00
29-23190-00
29-23187
99-05812
12-15336
70-15503-00

F.S. monitor assy.¥

70-16187

T This assembly consists of the CRT, yoke, vertical coil, flyback transformer, video monitor
board, and sheet metal enclosure.

Table B-2 VT100 WA Recommended Spares

Qty

Description

Part No.

|
1

Word processor keyboard
Word processor AVO firmware ROM

70-15765-03
23-069E2-00

Table B-3 VT10S Recommended Spares

Qty

Description

Part No.

1
1

Waveform generator module
Cable

M7071
70-08612-0F

B-3

Table B-4 VT132 Recommended Spares

Qty

Description

Part No.

VT100 spares Kit

Keycap, Delete

12-14333-U3

Keycap, Insert Line/PF1

12-14333-U4

Keycap, Delete Line/PF2

12-14333-U5S

Keycap, Char Insert/PF3

12-14333-U6

Keycap, Clear/-

12-14333-U7

Keycap, Back Tab/,

12-14333-U8S8

Keycap, Delete Char/.

12-14333-u9

Keycap, Print/Enter

12-14333-WO0

Keycap, (Edit)/PF4

12-14333-W
1

ROM, basic video ROM A

23-095E2

ROM, basic video ROM B

23-096E2

ROM, basic video ROM C

23-097E2

ROM, basic video ROM D

23-098E2

ROM, advanced video ROM E

23-099E2

ROM, advanced video ROM F

23-100E2

Standoff, AVO

90-09747-03

B-4

APPENDIX C

GLOSSARY OF TERMS AND ABBREVIATIONS

20 mA - Value of current used for current loop communications option; also, the name of the option.
75 ohm - Source and terminating impedance for video inputs and outputs.
TFH — Hexadecimal value representing 0111 1111 in binary; the terminator at the end of each line of
characters; also, the last keyboard address, always returned at the end of a scan.
8080 - The microprocessor device.
8224 - The clock generator device.
8228 - The system controller and bus driver device.
8251 - The PUSART.
A0,Al,...,Ax - Address Bus.

Active — For the current loop option, the interface supplies switched current to transmit, and to receive,
detects changes as the remote sender switches the current supplied by the active device. For the STP,
the STP device intercepts the interface signals, acts on them, and then can either withhold them or pass

them on to the terminal controller or the host.
Active Position — The active column and active line position in which the next displayable character will

be placed. The active line is the line in which the cursor is presently located. The active column is the

cursor location on the active line.
ADDR - Address
ADDR CNT - Address Count. Signal that drives the address counters in the video processor.
ADDR CNT ON - Address Count On. Signal inside the DCO11 that controls the output of Address

Count signals.
ADDR LD - Address Load. Signal that loads the address bytes from the end of a line into the pre-

settable address counters; also stores line attributes.
Advanced video option - Optional circuit board that contains extra screen RAM, extra attribute RAM,

and program ROM sockets and decoders.
ALT CHAR SET - Alternate Character Set. If the AVO is present, a ROM with a different character
set can be installed in a socket on the terminal controller, and selected with a control function.

C-1

ANSI - American National Standards Institute
ANSI mode - A mode in which the terminal recognizes and responds only to control functions whose
syntax and meaning follow ANSI specifications.
ASCII - American Standards Committee for Information Interchange

Asynchronous - For serial data transmission; method allows sender and receiver to operate with nonidentical clocks.
Attribute - A display feature such as blinking characters, double width lines, or reverse screen.
AVO - Advanced Video Option

Base attribute — The one attribute that characters on the screen can have when the AVO is not present.
Selectable at SET-UP to be either reverse or underline.
Baud rate - Rate of data exchange on a serial interface.
Bipolar - A kind of transistor construction used in TTL and high speed LSI.
Blink - An attribute that makes a character blink.

Bold - An attribute that makes a character brighter.

Bottom half - In a double height line, this is asserted for the bottom half of the line.
Bus - A group of wires carrying several separate but related signals.
Byte - Eight bits treated as a unit.

C/D - Command/Data. Control line to the PUSART.

Caps lock - A key that forces alphabetics to uppercase without affecting numeric and symbolic keys.
Cathode - The element that is driven to control intensity of the electron beam in the CRT.

CHAR CLK - Character Clock. A clock in the video processor with a period equal to the time between
characters on the display. Varies according to 80 or 132 column mode.

Character - A pattern of dots on the CRT screen representing an ASCII character; a pattern which
represents an element of written language or mathematics; a group of 7 or 8 bits representing a control
or graphic entity. In serial-by-bit transmission, a character is transferred from low-order bit to highorder bit.

Character generator - A ROM that translates character codes into patterns for display.

Character position - That portion of a display that is displaying or is capable of displaying a graphic
symbol.

Checksum - A number created specifically to detect errors in stored or exchanged data.
Column modeé - The number of characters positions provided on a line - 80 or 132.

COMP SYNC - Composite Sync signal

Composite sync - The signal that coordinates the motion of the electron beam in a video monitor that
is external to the VT100.

Control - The term ““control” refers to a “control function.” A control function is implemented
through the use of a control character, escape sequence, control sequence, or control string.
Control (key) - Produces control characters when pressed with other keys.
Control chip - The DCO012
Control character — A single character whose occurrence in a particular context initiates, modifies, or
stops a control function. The value of a control character is in the range 0 through 1FH and 7FH in a
7-bit environment.

Control function - A special action the terminal can perform to affect recording, processing, transmitting, or interpreting data. Also, the sequence of characters that cause the action.
Control Q - An ASCII control character meaning XON.,

Control S - An ASCII control character meaning XOFF.

Control sequence - A sequence of characters used for control purposes to perform a control function.
A control sequence is a string of characters that begins with the control sequence introducer (CSI) and
ends with the first occurrence of a final character (40H-7EH). A control sequence may contain O or
more parameter characters (30H-3FH) and/or intermediate characters (20H-2FH).
Control sequence introducer — A prefix to a control sequence that provides supplementary control
functions. The CSI for the VT 100 series is ESC [ (1BH 5BH).
Control string — A string of characters used to perform a control function and delimited by an opening

and closing delimiter character.
CPU - Central processing unit. Generally means host.

CRT - Cathode ray tube. The display device in a monitor.
CSI - Control sequence introducer
Current loop - The 20 mA interface option.

Cursor - A blinking underline or blinking reverse field indicating the active position.
DO0,D1,...,.Dx - Individual lines on the data bus.

DB Bus - The bidirectionally buffered data bus.

DCO011 - Timing chip for the video processor. Produces timing signals, clocks, and line buffer addressing.

DC012 - Control chip for the video processor. Controls DMAs and generation of character video.

DCA - Direct cursor addressing

DEC - Prefix for DEC private control functions.
Default - Parameters provided when no choice is made by the user.
Demultiplexer - Routes a signal to one of several outputs according to control signals.
DH - Double height

Direct Drive — Controls movement of electron beam in the CRT with separate horizontal and vertical
signals rather than combining the control signals into the single composite video signal.
Direct memory access — An action by which the video processor can read data directly from the microprocessor’s memory.

DMA - Direct memory access

DMA ENABLE - A signal allowing a DMA to occur.
DO Bus - The buffered write-only (output-only) data bus.
Dot - The smallest displayable unit of information on the screen.

DOT CLK - The fastest clock in the video processor; clocks the video shift register. Varies with 80 or
132 column mode.

Dot stretcher — In the DCO012, adds one dot to each row of contiguous dots. Ensures that bandwidth
requirement of CRT is met.

Double height - Makes each line display in 20 scans instead of the regular 10.

Double width - Makes each character display in 20 dots instead of the regular 10.
DSR - Data Set Ready
DTR - Data Terminal Ready

DW - Double Width
E4 - Normal character set ROM

E9 - Alternate character set ROM

E11 - Line buffer D4-D7

E15 - Character latch buffer
E16 - Character generator latch

E17 - Line buffer DO-D3
E20 - Screen RAM character latch

E21 - Address counter A8-All
E25 - Address counter A4-A7
E30 - Address counter AO-A3

E60 - Programmable baud rate generator

EAROM - Electrically alterable read-only memory - the NVR.

EIA - Electronic Industries Association; used to refer to the EIA standard voltage 1/O interface, RS232-C.

ER1400 - Nonvolatile RAM
ESC - Escape character (ASCII 1BH)

Escape character (ESC) - A control character that provides code extension and that is itself a prefix
affecting the interpretation of a limited number of contiguous characters.

Escape sequence - A sequence of characters used for control purposes to perform a control function.
The sequence begins with an (1BH) control character and ends with the first occurrence of a final
character (30H-7EH). An escape sequence may have 0 or more intermediate characters (20H-2FH)
preceding the final character.
Exclusive-OR - A logical function that provides an output only when one or the other input signal is
present but not when both or neither are present.
EXT - External

Field - That part of a video image displayed during one vertical sweep of the CRT beam from the top
of the screen to the bottom.
Fill line - A terminator and a pair of address bytes. Synchronizes the DMA process in the video
processor without requiring a full line of memory.
Firmware - The microprocessor program.
Flag - An internal signal to the microprocessor.
Flyback transformer - Generates high voltages in the CRT monitor.

Frame - A complete video image.
Graphics - A kind of display showing lines and shapes rather than alphanumerics.
Halt - A condition in the microprocessor when no instructions are performed.
Hard copy - Computer output that can be carried away from the output device in human-readable
form.
Hardware - The electrical and mechanical structure of a device.

HOLD REQ - Hold request. A signal asking the microprocessor to give up use of the address, data,
and control buses to the video processor.
HORIZ BLANK - Horizontal blank. Signal that turns the electron beam off during the horizontal

retrace interval.
HORIZ DRIVE - Horizontal drive. Direct drive signal from the video processor that synchronizes
horizontal deflection in the internal monitor.
HORIZONTAL TIME - Gating signal inside the DCO012.
Host - The computer that the VT100 communicates with.

Hysteresis — A characteristic of detection circuits that makes the threshold of detection different for
different directions of change of the input signal.
I/O RD - Input/output read.

A microprocessor control bus signal.

I/O WR - Input/output write. A microprocessor control bus signal.

IC - Integrated circuit.

Idle - On a communication line, a state when no information is being exchanged.

INIT - Initialize. Signal that informs options and internal devices that the VT100 has performed a
reset operation.

INTA - Interrupt acknowledge. Signal the 8080 produces to indicate it is ready for a RST instruction
containing an interrupt vector. The signal enables the outputs on the interrupt vector buffer.

Interlace - A kind of video display where the information from two fields is displayed by offsetting the
vertical position of one field slightly from the other so the scans of one field appear between the scans
of the other.

Interrupt — A signal to the microprocessor to get it to set aside its current work to take care of a high
priority task. Such tasks include getting data from a communication line before it disappears.
ISO - International Standards Organization

Jump - In firmware, a movement to a nonsequential instruction. In a display, a form of scrolling where
lines of characters on the screen move up or down by the height of a character line in one operation
(compare to smooth scrolling).

KEY DOWN - Signal in the keyboard that causes the transmission of a key address to the terminal.

Keypad - Generally refers to the cluster of 18 numeric and special function keys on the right side of the
keyboard.

Latch - A device that can store data.

LATOFS - Line address offset table. Used by the firmware to determine the display order of the lines.

LBA - Line buffer address. Output from the DCO11 to address character location in the video processor’s line memory.
LC - Inductor-capacitor

LED - Light emitting diode. A light source (usually red). There are seven at the top of the keyboard.
Line - A line of either 80 or 132 characters. Characters do not have to be present for the line to exist in
memory.

Line attribute — An attribute that affects the entire line, such as double width.
Line buffer - Memory that stores the current line for display during the nine non-DMA scans.

Local - A condition in which the output from the keyboard goes directly to the screen without going to
the host.
LSI - Large scale integration. Very complex circuitry packed into small packages. The DCOI1,
DCO012, and 8080 are examples.

Mark - One state of a communication line. Generally defined as a low signal level or the presence of
current flow. See also Space.
Mask-programmed - Programmed as part of the manufacturing process and not changeable.
Matrix - An arrangement that allows addressing of many individual points with few address lines.
Used in the keyboard switch array.

MEM DISABLE - Memory disable. Signal used by the AVO to disable main memory outputs when
other memory is being addressed.
MEM RD - Memory read. A microprocessor control bus signal.

MEM WR - Memory write. A microprocessor control bus signal.
Microprocessor — The 8080 and associated devices. Controls VT 100 operation.

MNOS - Metal nitride oxide semiconductor. The semiconductor technology used in the nonvolatile
RAM.
Mode instruction - Command to the PUSART that sets up the basic operating protocol.

Modem - A device that converts the VT 100’s EIA output to audio tones that can pass over telephone
lines.
Modulus - The largest unique value in a counter. If incremented beyond its modulus, a counter returns
to 0 and counts up again.

MOS - Metal oxide semiconductor. A class of devices distinct from bipolar.

ms - Millisecond
Multiplexer — A device that selects from several inputs to give one output.

MUX - Multiplexer
New scroll zone - A signal inside the DCO12 that indicates the beginning of a scroll zone and commands a new DMA.

NMOS - N-channel metal oxide semiconductor. Class of device used in the 8080 and 8251 and 2114
(memory chip).
No Scroll - A key that stops new data from entering the screen.

Nonvolatile RAM - Writable memory that does not lose its data when power is off.
NTSC - National Television Standards Committee
NVR - Nonvolatile RAM

Offset - The number of scans a line is moved from the normal display position in a given frame during
a smooth scroll. Also, the rearrangement of line display order according to LATOFS.
On line - A condition in which all keyboard information passes to the host computer and the screen
receives its data from the host.

Overrun error — Occurs in the PUSART if the microprocessor did not read a character before the next
one arrived on top of it.

Parallel - Data path where all bits travel simultaneously on separate wires.
Parity - An error detection system based on the number of bits set in each data byte.

Parity error - An error condition indicating that at least one of the bits in a byte changed.
Parser - A process that separates a sequence into its component parts.

Passive - For the current loop option, the interface accepts current from outside and passes it or blocks
it to transmit; to receive, it detects changes in the incoming current. For the STP, the option plugged
into the STP examines the data on the interface and can add messages of its own, but cannot change
the data passing between the terminal controller and the host.
Pn - Parameter

Pop - The microprocessor retrieves data from the stack.

Port - A place where data can enter or exit a device.

Pulse width modulation - Encoding of data by varying the duty cycle of a continuous clock.
PUSART - Programmable universal synchronous/asynchronous receiver/transmitter. The commiunication device in the VT100.

Push - The microprocessor puts data in the stack.
PWM - Pulse width modulation

RAM - Random access memory (also known as read/write memory).

Raster - On a CRT screen, the effect of continuous vertical and horizontal deflections of the elgqtron
beam covering the full height and width of the screen. If the beam is turned off, the raster is not visible.
RC - Resistor-capacitor

RCLK - Receive clock

Ready - A control line that forces a wait state in the 8080. Not used in the VT100.
Recall - A routine that sets SET-UP data from the NVR.

Refresh — The process of repeatedly rewriting the screen with data so it appears to to be constantly lit.
Reset — Setting a device to a starting condition, often for clearing errors.
Restart - Instruction the 8080 performs when interrupted.

Retrace - Rapid movement of the turned-off CRT beam from the end of one pass to the beginning of
another.

Reverse video — A character attribute: characters are seen as dark areas in fields of light.
Reverse screen — A screen attribute: the entire screen is normally rendered as black characters on a
white background.

RO - Receive-only

Rollover - Ability to accept more than one key pressed at the same time.
ROM - Read only memory

Routine - Set of instructions to the microprocessor that makes it perform a particular function.
RS-170 - An EIA standard that dictates television signal characteristics.
RS-232-C - An EIA standard that dictates data interface characteristics.
RSL - Recommended spares list
RST - Restart instruction
RTS - Request to send - modem control signal.

RxD - Receive data - PUSART
RxRDY - Receiver ready - PUSART

Save - Process of storing SET-UP data in the NVR.

Scan - One horizontal pass of the CRT beam,; also, the character information displayed in that pass.

Scan count — The video processor keeps count to help decide when to initiate a DMA and to provide
addresses for the character generator ROM.
SCD - Secondary carrier detect.

A modem control signal.

Schmidt trigger — A device that accepts a slowly varying signal to an input with hysteresis in its threshold of detection. It outputs clean transitions when the input passes the threshold of detection in either
direction.
Scratch RAM - That portion of RAM used for microprocessor operations.
Screen - Face of CRT on which data are displayed.

Screen attribute - Applies to the entire display area: reverse screen, smooth scrolling.
Screen RAM - That portion of RAM used for display storage.
Scroll - Upward or downward movement of data on the screen.

SEL 8-12K - Select rhemory in the range 2000H to 2FFFH.
SEL ATT RAM - Select attribute RAM. Signal for reading and writing data in the attribute RAM on
the AVO under microprocessor control.
Serial - Transmission of data bit-by-bit over a single data line.

SET-UP - Special mode of terminal operation for entering operating parameters from the keyboard.

SET-UP specifications - Those terminal operating parameters entered from the keyboard or changeable from the host.

SHUFAD - Shuffle address. The pointer address location that changes during a shuffle.
SHUFDT - Shuffle data. The pointer address stored in SHUFAD during a shuffle.

Shuffle - The process of quickly rearranging pointer addresses when a line scrolls off or on the screen.
SILIN - The address where the next character enters the SILO.

SILO - A Scratch RAM area where data coming from the communication port is buffered on a firstin/first-out basis.

SILOUT - The address where the next character exits the SILO.

Smooth scroll - Scrolling in which the data on the screen moves only one scan per frame.
Soft copy - Computer output that only exists as light on a screen.

Space - One state of a communication line. Generally defined as a high signal level or the absence of
current. (See also Mark.)

SPDI - Speed indicator. A modem control signal.

C-10

SPDS - Speed select.

A modem control signal.

Split screen - Display operation where one part of the screen can scroll while another part remains
stationary.

SR - Shift register. The device that performs parallel to serial conversion of data from the character
generator ROM to the CRT. Also, the parallel-to-serial (or s-to-p converter) in UARTs and PUSARTs.

SRTS - Secondary request to send.

A modem control signal.

Stack - Area of scratch RAM where the microprocessor places its current status while processing an
interrupt or subroutine call.

Start bit — The first bit in a serial, asynchronous byte transmission, always a space.

Status byte - A byte of information about the operation of the 8080 that it outputs during the first
machine cycle of an instruction. The byte is latched and decoded into control signals by the 8228
system controller.

Stop bit — The last bit in a serial, asynchronous byte transmission, always a mark.
STP - Standard terminal port

STSTB - Status strobe. Signal output by the 8080 to latch the status byte into the 8228.

Sync - Any signal that allows one device to operate precisely in step with another. Particularly applies
to synchronization of the electron beam in a monitor to the video data that modulates the beam.
Synchronous - Processes that occur in synchronism.
TBMT - Transmit buffer empty. A signal from the keyboard UART.
TC - Terminal controller. The main VT100 circuit board.
TCLK - Transmit clock

Terminator — A character mixed in with screen data that signals the end of a line and causes the video
processor to advance to the next line.

Threshold of detection - That value of input that causes a detector’s output to change state.
Timing chip - The DCO11

Toggle - To alternate the state of a device between two values.

Top half - In a double height line, this is asserted for the top half of the line.
TP - Terminal processor. A hypothetical nonvideo processor built into the VT100 cabinet.

Tristate — A device output that can sink current, source current, or become high impedance and not
affect the circuits connected to it.

C-11

Tx ENable - Transmitter enable. A bit in the PUSART command instruction.
TxD - Transmitter data. PUSART serial data output.
TxEmpty - Transmitter empty. PUSART control output.

TxRDY - Transmitter ready. PUSART control output.

UART - Universal asynchronous receiver-transmitter. Wire-programmed device used in the keyboard
interface.
Underline - A character attribute that forces scan 9 to show during a character.
us - Microsecond
Vector — The address of the first instruction for an interrupt handling routine.

VERT BLANK - Vertical blank. Signal that turns off the CRT beam during the vertical interval.
VERT DRIVE - Vertical drive. Direct drive signal from the video processor that synchronizes vertical
deflection in the monitor.
VERT RESET - Signal that occurs at the bottom of the screen to start the video processor at the top.

Vertical interval - The portion of a raster when the beam is turned off and returning to the top of the
screen.

VID WR 1 - Video Write 1. Signal to load control data into the DCOI 1.
VID WR 2 - Video Write 2. Signal to load control data into the DCO12.

Video processor — The circuitry that converts character codes stored in RAM into video signals that
display as graphic characters on the screen.

VID IN - Video input (to the DCO012).
VID OUT - Video output (two outputs from the DCO012).

VSR LD - Video shift register load. A signal that determines whether the video shift register performs
a parallel load or a shift when clocked.

VT52 - The DEC video terminal that preceded the VT100. It responded to escape sequences conforming to an internal Digital Equipment Corporation standard.

Wait - Displayed message for operator during NVR operations. Also, an indefinite state in the 8080
controlled by Ready (and not used in the VT100).

Wire-ANDed - TTL devices with open-collector outputs can be tied together to form a logical AND
gate at the outputs.

WRITE LB - Write line buffer. Signal that writes a character into the line buffer.

C-12

XMIT flag - Transmit flag. Signal to microprocessor from TxRDY at PUSART.
XOFF - Control character that asks the sender to stop sending.
XON - Control character that asks the sender to resume sending.

C-13

VT100 SERIES TECHNICAL MANUAL

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