Digital PDFs

EK-VAXV2-HB-002

August 1983

347 pages

Original

7.7MB

view download

OCR Version

7.7MB

view download

Document:	VAX Maintenance Handbook VAX-11/780
Order Number:	EK-VAXV2-HB
Revision:	002
Pages:	347
Original Filename:

OCR Text

EK-VAXV2-HB-002

VAX
Maintenance
Handbook
VAX-11/780

1983 Edition

Prepared by Educational Services
of

Digital Equipment Corporation

First Edition, August 1982

Second Edition, March 1983

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any

errors which may appear in this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation:
DEC

DECnet
DECsystem-10
DECSYSTEM-20

DECwriter
DIBOL

dlilgliltlall

EduSystem

IAS
MINC-11
OMNIBUS

0S/8
PDP

PDT

RSTS

RSX
TOPS-10
UNIBUS

VAX
VMS

CONTENTS

CHAPTER 1

INTRODUCTION

Introduction. . .. ... ... ...

e e

VAX-11/780 Hardware Manuals. . . .. ............c.cv.v... 4
CHAPTER 2

HARDWARE DIAGRAMS

VAX-11/780 Block Diagram . . . .. ... ...... ... 7
KA780 CPU Module UtilizationChart.

. . . ... ............... 8

KA780 CPU Block Diagram. . . . ... ....... .0

.. 9

SBI Control Low Bits (SBL) Block Diagram . .. .............. 10
SBI Control High Bits (SBH) Block Diagram.

.. .............. 11

Cache Address Matrix Block Diagram . . ................... 12
Cache Data Matrix Block Diagram . . ... .................. 13
Translation-Buffer Data-Matrix Block Diagram . ... ........... 14
Translation-Buffer Address-Matrix Block Diagram . .. .......... 15
Instruction Buffer Block Diagram. . .. .................... 16

Instruction Decode Block Diagram . . . .. .................. 17
DataPathBlock Diagram . .. ... ......... .00t 18
Clock Module Block Diagram. . ... ............
... ...... 19
Writable Control Store (WCS) Block Diagram . ............... 20
PROM Control Store (PCS) Block Diagram. . .. .............. 21
Microsequencer Block Diagram . . ... ..........
... .... 22

Console Interface Board Block Diagram. . ... ............... 23
Floating-Point Accelerator (FPA) Block Diagram. . ............ 24

KA780 TR and System ID Register Jumpers. . . .............. 25
KA780WCS Jumpers. . . .. ... ittt ittt i

i ittt

eennnn 26

CHAPTER 3

MICROCODE

Control Store FieldMap. . ....... .. i, 29
Microcode Routines That Support Console Software
e 30
i t
Starting Addresses. . . .. ... ..o
Microcode Branch Enable Functions. . . ... ................ 31
Microtrap VeCtOrS . . . . . i v i it et ittt i et 33
Microcode Memory Control Functions .. .................. 34
ScratchPad Operation .. .. ... .. ..t 35
Control ROM Field Definitions . .. .... ... ... ... oL 36
System Microcode Macros. . . .. ... ... ..t 49
FPAControlWord Fields . . ... .........
... ...t 73
FPA Control ROM Field Definitions.
CHAPTER 4

. ... ................. 74

CONSOLE

CIB O-Bus Registers (Lower).

.. ...........iiiernnen.. 85

CIB Q-Bus Registers (Upper) . . . ... i, 86
Explanation of Version Numbers for Console Booting . .. ... .... 87

Console Help File . . ... ... .

ie e 88

Console AbbreviationRules. . . ... .............
... ... ... 90
Error Message Help File . . .. ... .. ... ... 91
Console Remote Access HelpFile. . ... ................... 94
Microdebugger Help File. . . . ... ... ... ...

...

..., 95

LSI-11 Console ODTCommands .. ............ ..., 97
Console Subsystem Configuration. . .. .................... 99
KD11-F Module Jumper Configuration . . . ................ 100
MSV-11B Module Jumper Configuration . . . ............... 101
M9400-YE Cable Connections . . . .. .................... 102

DLV11 Jumper Configuration . . .. ..................... 103
DLV11-E Jumper Configuration. . . .. .........¢ccivvenn. 104

Q-Bus Signal Description. . .. .... .. ...t

tiinnnn.n 105

Console Boot/TroubleshootingFlow. . . . ................. 108

CHAPTER 5

INTERNAL REGISTERS

Processor Register Addresses . .. . ... ....

ennn. 117

Processor Register Bit Configurations . .. ................. 118

ID-Bus Map .. ...ttt
it it e e e e e e e
e 126
ID-Bus Register Bit Configurations . . ... ................. 133
Silo Register Interpretation.

. .. .. ...........
... ....... 156

Microcode Machine Check Error Logout . .. ............... 159
Double ErrorHalt.

. . ... ...t 160

V-Bus Channel Configuration. . ... ........... ... ... 161

V-Bus Directory . ... ... ci ittt ittt it ittt

CHAPTER 6

it nn e 162

SYSTEM BACKPLANE INTERCONNECT (SBI)

SBl Configuration . . .. .. ...... .. .. 183
SBI Parity Field Configuration.

. .. ..................... 184

SBI Information Transfer Formats . .. ................... 185
SBI Field Description. . . ... ... ... i, 187

SBI 1/0 Register Addressing and Interrupt Vector Generation . .. . 189
SBI Faults (Adapter Configuration Register). . . ............. 190

SBI Configuration Rules for TR Selection . ... ............. 191
SBI Signals, BackplanePins.
CHAPTER 7

. .. .............
... . ...... 194

SBI NEXUS

Memory Configuration Register A . . ... ................. 197

Memory Configuration RegisterB. . .. ................... 198
Memory Configuration Register C. . . .. ...........
... .... 199
Memory Array Addresses . . ... ... ..o

ii ittt

nnnn. 200

MS780 Configuration for Rev H Backpanel . .. ............. 201

MS780A Module Utilization . . ... ..................... 202
MS780C Module Utilization . ..............
... ... ... 203

Memory Block Diagram . . . ... ...... .. ... . ... 204
Memory {/ODatalogic..........conviiiiiiiinnnnennn 206

UBA Address Spaceand C/AFormat . ................... 207
UBA ReGiSters . . ..

vttt ittt et e

et e

DW780 (UBA) Backpanel Jumper Configuration.

e ie e 208

. ........... 211

SB! to UNIBUS Control Address Transtation .. . ... ......... 212
UNIBUS to SBI Address Translation.

. ... ................ 213

Addresses and Vectors for UNIBUS Devices . . . . ... ......... 214
Floating Vectors and Floating Addresses . . . ... ............ 215

UNIBUS Configuration. . . .. .........
... ...
... 217
DW780 (UBS) Block Diagram . . ... .................... 218

Simplified Flow of Major Control Functions Within the UBA . .. .219
Standard and Modified UNIBUS Pin Assignments . . ... ....... 220
UNIBUS Signal Descriptions . . . .. ................c..... 221
DW780 Module Utilization . . .. .. ..........
.. ......... 223

MBA Registers - Base Addresses and Bit Configurations . ....... 224
RH780 (MBA) Backpanel Jumper Configuration.

. ........... 228

MASSBUS Disk Drive Register Address Calculation Chart.

... ... 229

MASSBUS Signal Cable Pin Assignments . .. ............... 230
RH780 Module UtilizationChart . . . ... ... .............. 232
MBA (RH780) Block Diagram . . . . ... .. ... ¢, 233
MA780 Multiport Memory Registers.
MA780 Array Addresses.

. . . .. ............... 235

. .. .. .. ittt 238

MA7Z780C Jumpers . . . . ..

MATZ80A JUMPEIS . . . . o

e e e e

MA780 BackplaneData ... ... .. ... ...

e 239

e e 240

.. ...

. ...

... 241

M8210 Memory Array Card Mnemonics. . . . ... ... ......... 242

M8212 Data Path/ECC Card Mnemonics . . ... ............. 244
MA780 Multiport Memory Block Diagram . . ... ............ 246

MA780 Multiport Memory Interface Module (M8258)
Block Diagram . . .. .. ... . . . e 247

MA780 Multiport Memory Controller Module (M8259)
Block Diagram . . . . . . .

e e e 248

MA780 Multiport Memory Array Timing and Control Module
(M8260) Block Diagram . . . .. ... ... .. .. ... 249
MA780 Multiport Memory Synchronizer Module (M8261)

Block Diagram . . . ... . .. . .

e 250

MA780 Multiport Memory Invalidate Map Data Path
Block Diagram . . . ... . ...

251

MA780 Multiport Memory Interlock Arbiter Block Diagram . . . .. 252

MA780 Multiport Memory Data Path/ECC Module (M8212)
Block Diagram . . . . .. ...

. e 253

DR780 Registers.

. . . ... ..ottt
it e e

DR780 TR Arbitration Jumper and Wirewrap Selection . . . .. ...

DR780 Backplane . . .. .. ..ottt
e
e

DR780 Block Diagrams . . .. .. ...

i i

SBI Control (DSC)MB296 . ......................

Control Board (DCB)M8297. . . ... ......
... .......
Microprocessor (DUP)M8298 . . .. .. ...............
SiloModule (DSM)M8299 . . . .... ... .............
CI780 Registers. . . .. .o vt

Cl780 Backplane Jumpers. . . .. ...

CI780 Block Diagram. . .. .. . ..o

e e e e e

... v

it e

CHAPTER 8

PROCESSOR-SPECIFIC DIAGNOSTICS

CHAPTER 9

MISCELLANEOUS

VAX-11/780

Integrated Circuit Diagrams . . ... ............

25510 Four-Bit Shifter Chip with Tristate Qutput.

. ... ...

26510 Bus Transceiver Chip . . ... .................

74LS181 ALUChIp.

. . ..

74182 Lookahead Carry Chip . . .. .. ...............
74LS670 4 X 4 Register FileChip . . .. ..............

82523, 825123 256-Bit Bipolar PROM Chip. . . ......
...
85568 64-Bit Edge-Triggered D-Type Register File Chip
with Tristate Outputs.

. . .. ...................
...

DEC 8646 Four-Bit Tristate Backplane Interconnect

Transceiver Chip.

.. .. .. ... ... .. ... . ... . . . ... ..

9403 FIFOBufferChip . . .. ............
.. .. ...
.
DC101 Arbitrator Chip. . . . ............
. . ... ..
DCOO3 InterruptChip . .. ......... ...

DCO004 Protocol Chip. . .. ..........
.. ..
....
.. ...

vii

CHAPTER 1

V
ez )le]\
RiNjf;{elo]

o, 71233

HARDWARE DIAGRAMS

CHAPTER 3

[|[{ef:{e]ele]s]3

CHAPTER 4

[e{el}{0]RS

o, T\1

INTERNAL REGISTERS

oIS

SYSTEM BACKPLANE INTERCONNECT

CHAPTER 7

B3IV UL]

o I\A 1

PROCESSOR-SPECIFIC DIAGNOSTICS

CHAPTER 9

RVI[ejaWW.\|e]V}S

CHAPTER 1

INTRODUCTION

The

purpose

compact,

the

VAX

quick-reference

Maintenance
source

Handbook

troubleshooting,

provide

maintenance,

operating,
and
programming
information
that
1is
frequently
referenced by DIGITAL field service, manufacturing, training, and
engineering

This

second

exclusively

personnel.

volume
to

the

information

VAX

Maintenance

Handbook

the

VAX-11/780

processor.

devoted

VAX-11/780 HARDWARE MANUALS

Document

Title

System Technical

VAX-11/78%

Power

VAX-11/78¢

System

Installation

Description

EK-PS780-TD-001

Manual

EK-SI980-IN-0@1

DS78¢

Diagnostic

System User's Guide

DS78@

Diagnostic

System Technical

FP78¢

Floating-Point Processor Technical

EK-DS780-UG-001

Description

EK-DS780-TD-002

EK-FP780-TD-901

Description

VAX-11/780

Central

Processor

EK-REP@6-TD-00@1

Documentation

Subsystem Technical

REPA5/REP#6

Technical
EK-KA780-TD-0081

Description
VAX-11/780

Memory

System

DW78@

UNIBUS Adapter

KC78@

Console

VAX-11/780

Architecture

VAX-11/7808

Multiport

VAX-11/78¢

Cache,

Description

EK-KC780-TD-001

EB28126
EBB7466

Handbook

E7-MA780-TD-001

Subsystem

Interface

SBI

User's

Control

Guide

EK-DR780-UG-001

Technical

Description

VAX-11/780
VAX

EK-MM780-TD

Technical

RH780

Diagnostic

System

444

Equipment

Whitney

Northboro,

Attention:

For

EK-RH780-TD

Guide

ordered

EK-VX11D-UG-281

from:

Corporation

Street
MA

01532

Printing

and

Customer

Services

information

Digital

Description Manual

User's

can

Hardcopy manuals
Digital

EK-MS780-TD-00

EK-DW780-TD-0081

Description

Technical

Memory

Purpose

TB,

Description

Handbook

Software

General

Technical

Interface

VAX-11/78@

DR78@%

Number

Circulation

concerning

microfiche

Equipment Corporation

Micropublishing (E46)
12 Crosby Drive
Bedford, MA 01738

Services

(NR2/M15)

Section
libraries,

contact:

CHAPTER 2
HARDWARE DIAGRAMS

VAX-11/780 BLOCK DIAGRAM

CENTRAL PROCESSING UNIT
v

wes

cPU

| WITH FULL

| FLOATING POINT,

FPA |

DECIMAL, AND

CHARACTER STRING

pisTaucrions

CONSOLE

ACHE MEMORY

SUBSYSTEM

CAC

_——_———

MEMORY SUBSYSTEM

PORT FOR

~ L

DIAGNOSIS

SI1

REMOTE _| MICRO-

FLOPPY
DISK

MEMORY

ecc mos | Iy1

]

CONTROLLER [~

_,J

COMPUTER

r—=—="

- ~— 4 MEMORY

r—="

-4 256KB

_ b —~ 4 CONTROLLERE- 4 Ecc mos!

CONSOL E

LTy

TERMINAL

g
—_

[ 1]

I/0 SUBSYSTEMS

UNIBUS

(1.5 MB/sec)
ONIBUS

MASSBUS

{2.0" MB/sec)

BE ADAPTOR

(13.3

MB/sec)

FPA=FLOATING POINT ACCELERATOR

]
I

ADAPTOR

ASSBUS

WCS= WRITABLE CONTROL STORE
TK-0733

KA780 CPU MODULE UTILIZATION CHART

MODULE UTILIZATION KA780
29 | MB236

CiB

28 | M8289

FCT

27 | M8288

FAD

26 | m8287

FML

25 | M8286

FMH

24 | M8285

FNM

23 | M8235

usc

22 | M8234

PCS

20 | m8233 or M8238

WCS

18 | M8233 or M8238

0Cs

17
16 | M8232

CLK

15 | M8231

iICL

14 | M8230

CEH

13 | M8229

DAP

12 | M8228

DCP

| M8227

DDP

10 | MB8226

DEP

9 | M822%

DBP

| M8224

IRC

7 | M8223

1DP

| M8222

TBM

5 | M8221

CDM

4 | M8220

CAM

3 | M8219

SBH

2 | m8218

SBL

TRS

m8237
e

WHEN NOT INSTALLED USE

BLANK MODULE 7014103

TK-8346

BUFFER

VBUS

{

DATA

s8I

CACHE

CONTROL

REQUEST LEVELS

YanpamEE—

fi-

> TO/FROM MEMORY

S8l

PABUS

TRANSLATION JF—

<<
>

[

ainstl

FLOATING

POINT
ACCELERATOR

GRD

bATA

MD BUS

RAM

ROM

CONTROL
STORE

[t]

NIRE

IR0

[1]

INSTRUCTION

p—ed BUFFER AND
DECODE

PATHS

—

CSBUS

uPC

VBUS

SRl - SYNCHRONOUS BACKPLANE INTERCONNECT
VA
-

VIRTUAL ADDRESS LINES

PA BUS - PHYSICAL ADDRESS BUS

| ‘ I l:
1D BUS

cLock

convroL |

cLocK

Lock

ouTPUT

|GENERATOR

|3[7

DIAGNOSTI

|SianaLs

consote

Ale

DATA BUS
iD BUS - INTERNAL

V BUS -

VISIBILITY BUS

UPC - MICROPROGRAM COUNTER
GRD- GENERAL REGISTER DATA

WICRO

SEQUENCER

INTERFACE

MD BUS - MEMORY DATA BUS

CS BUS - CONTROL STORE BUS

ltl {l b

LSI-11CP

AND 8K
MEMORY

l
DLV-11

Q8US
TOCAL
TERMINAL
-—

}

_{§3M6f3'1

LIERMINAL

TRAPS AND

pmmeed |NTERRUPTS
ARBITRATOR

WVYH5VIA X309 NdD 084V

— 1

TIMEOUT | SBLB.J TIMEOUT ADRS (17 021

ADDRESS

VYT

BUS PA 117 021

REGISTERSS
A ADDR|

SBLA

$BLB.J
) ADDRESS REG (17 02)

S8 LE

TRANSMIT

SBLA TRANS DATA (15 00)

Mux

SBLE RECEIVE DATA (1500)

SBLJ ADDRESS REG {1712, 08 02
BUS PA (17.12.

0802)

SBI
| xcE(v

BUS SBI 8 (15 00)

BYTE 1-0 PAR

| ADDRESS

MUX

SBLC READ DATA (1511, 07 00!

SBLY

Sty

SBLJ ADDRESS REG (11°09)

SBLB PA (11 09) FAST

ARB

LOGIC

SBLC READ DATA (10 0B)

ARB

89 OK

TRSELS 4 2

SBLC

BUS MD (15.00)

SBLC READ DATA (15 00)

| BUS MD BYTE 11 0) PAR|

[«]

SBLC

READ DATA

BUS

DRIVER

SBLC
BUS MD (15 00}

WRITE DATA | SBLC WRITE DATA (15 00}

SBLA

\/
FROM

INTERRUPT ICLB IPL ACT (1 O}

CONTROL
LOGIC

ISR

DECODE
SBL FH

BUS 1D {15 00)

SBLF,H
o

SBLB.J TIMEOUT ADRS (17 02)
SBLN PARITY REG (15 00)

BUS T MiSC MAINTENANCE CONDITIONS]
MUX

(MISC ERROR CONDITIONS)

XCEIWV

sBi

SBLM

ERROR

!
TER
REGISTE

CDM/CAM (G1.GO} BYT(Z 0) PAR 0D
FROM

CACHE
FROM
T8

_ CDM/CAM (G1.GO) (B3:B0)PAR ODD
TBMN BUF UADS

UFS

YBMN BUF UMCT {3 0)

SBLF 1D RECEIVE {15 00)

BUFFER

SBLS 1D BUFF (15 00}

SBLN

MAINTENANCE

W
REGISTER

SBLN

CACHE
-

PARITY ERROR
HeiSTER

sBLp
u CODE
CONTROL
T

0114

WYHOVIA 2018 (18S) S118 MO TOHLNOD 18S

SBLB.J

:SOM TBMK (11 09)

SBHC

SBHR

FUNCTION | SBHR FUNCTION CODE (3°0)
LATCH

| » CODE | ROM ADR _} FuNncTiON
ROM
LATCH

TRANSMIT|
MUX

SBHD RECEIVE DATA {31.18)

SBHD REC PAR (7:4)

FUNCTION

DECODE

SBHD

SBHC TRANS DATA (31:16)

SBI

BUS SBI 8 (31:18)

XCEWV

SBHB
SBHB

MASK

CONTROL

BUS PA (29:18)

»
2

SBHB RECEIVE MASK (3.0)

SBHA

"] ReGIsTER

DECODE

SBHK
SIiLo
sio.

ADRS)
(SILO
s

SBHD READ DATA (27 16}

CNTS

SBHK

SBHB

BUS MD (31.16)

BUS MD BYTE (3:01 Mask | fEiTE DATA

SBHD

2| Bus MD (3118}
BUS MD BYTE (3:2) PAR

BUS MD BYTE (3.0) Mask_|

BUS ID {31.16}

BUS

DRIVER

o
I

XCEIV

SBISILO

icLi D RIGHT ADDR (5:0) { |5

e 1D RIGHT WRITE

CONTROL

DECODE

s8I

BITS)*

XCEV

ADR)
(WC
READ DATA

P10}

FAULT

.
j
SBI 1D {4:0)
BUS

ALERT
(2:0)
TAG
UNJAM

sere smALERTR oo
ONIAM R

SBHA TIMEOUT ADRS (29:18)

SBHK SILO DATA (28.18)

(e e

con

REQI7:4) R

BUS

1 SBHF

SBHP

SBHE

[ |{HIGH

SBHD

MUX

SBHB WRITE DATA {31 16}

SBHD READ DATA (31 16)

BUS S8I M (3:0)

MASK

ADDRESS

BUS PA (29 18)

XCEIV

SBHB

TIMEOUT | SBHA TIMEQUT ADRS (2918)

S8l

MUuX

LOGIC

SBHA

PA ADDRESS | SBHA ADDRESS REG (29:18)

MAINTENANCE

BHP

sBHH.J 1D RECEVE (31 16 [ 1D

BUFFER

|SBHP ID BUFF (3116

SBHF

SBHF K

COMPARATOR

FAULT/STATUS

+LOW BITS ARE LOCATED ON TAM
TK.0337

WVHOVIA %2019 (H8S) S119 HOIH T041NOD 18S

UADS

FROM TBMN BUFF UMCT (300
T8

CAMP GO WRITE EN H

rauie (11 9)

CAMC GO

WRITE ENABLE L

CAMB BLOCK WRITE L

T8 DATA————————

CAMC

CAMC.D.E

MATRIX

BUS

LATCH

BUS PA (83)

CAMC PA LATCH (11 3
£

\ CAMC PA BUFF {11.3)

lc)zrnwvcens

L___/

BYTE

PARITY
CHECK

CAML GO BYT (2 0) PAR EV. QD

TO V BUS AND

SBI CONTROL

CAMK

GO
TAG

MATRIX
@

CAM GO TAG PAR i2 0)

TO CACHE

DIN

_CAMB

D OUT

CAM GO TAG {2812}

CAME VALID 0O

COKPARATOR

CAMK GO MATCH

CAMB LATCH VALID BIT
BUS PA (29:12)

CAMO GO

CAMB PA LATCH (29-12)

BUS

LATCH
GEN

;

CAMB TAG PAR (2.0} EV

Yot

;:?M

SBLR VALID

CAM F, HJ

CAMP

CONTROL

—eloIN

DOUT
Gt

WRITE EN

TO CACHE DATA

CAMP G 1

MATRIX ANO

WRITE EN

CAMK

COMPARATOR

CAMK & 1 MATCH

CAMJ VALID 1
CAM

TRANSLATION

e | N ren
-

G G1 TAG ! {2812 )

CAMG1TAG PAR (2.0

DATA MATRIX AND

SBI CONTROL

CAMK

TAG

DATA MATRIX AND

SBI CONTROL

—

MATRIX

CAMF

TM~

DRIVERS|aMF PABUFF (1) 3)
l_/

BYTE

PARITY
CHECK

[CAML G1BYT (2:0) PAR EV.0D,

TOV BUS AND

SBI CONTROL

CAMF

CAMP G1 WRITEEN H

CAMF G1 WRITE

CAMB BLOCK WRITE L

ENABLE L
CAMM

CAMB

CPLECLTITOL H ]

[ SBHF REV

PAR{20)

CAMB DISABLE G1 B2:BO

SBHF REV

|LCAMMCPT (301 L H

USED TO FORCE READ

FAOM

S8l CONTROL

¢ ook
I
LoGic

o oogr | CAMB DISABLE GO B2:80

> PARITY ERRORS DURING

DIAGNOSTICS

PAR 3

CAMB BLOCK WRITE L

1x 6230

AWVYHOVIA %0078 XIHLVIN SS3HAAV IHIVI

CAMC
CAMA

FROM

CDMD,F J.K

CDMR

PARITY
CHECK

CDMC

Sl suspaiiioz | pa
@

BUS

COMH ADDR LATCH {11:02)

LATCH

DRIVERS

CDMC ADDR LATCH (11 02)

DATA
MATRIX
N

pouT

CDMR GO {B3:B0) PAR EVEN. ODD

TO V BUS AND
S$BI CONTROL
LOGIC

CDM READ DATA GO (31:00}

CDM RD BYTE PAR GO (3.0}

FROM CAMP GO WRITE ENH COMB GO BYTE (3:0) WPL

CDMT

8US MD (31:00)
MD

CACHE

MUx

MATRIX wws G1BYTE (3:0) WP L

ADDRESS

|BUS MD BYTE (3:0) PAR

CAMK GO MATCH
P
COML,M.N

CDME ADDR LATCH (11:02)

CDMS

CDMR G1 {B3:80) PAR EVEN, 00D

PARITY

G
DATA

MATRIX
DIN

CDM

S$B1 CONTROL

READ DATA G1 (31:00}

LOGIC

com RD BYTE PAR G1 (3:0)

€l

DouT

TO V BUS AND

CHECK

MD BUS

COME

CDMA

BUS MD BYTE (3.0) PAR

CDMA BYTE(3.0) PAR
CDMA WRITE DATA (31.00) | MD
DATA

CDMA MASK (3:0) H

LATCH

BUS MD (3100)

BUS MD BYTE (3:0} MASK

comu

CP LEC (T3:TO)

cLOCK

CDMU (CPT3:.CPTO)

LOGIC

TK.0331

WVYHOVIA 0078 XIY1VIN Vivad JHIVI

coMu

TO TB CONTROL

TBMN UMCT (3:0). UADS. UFS

BUS

LOGIC AND

RECEIVERS

TBMK PA MUX SEL O

THE SBI CONTROL

TBMD VIRT ADRS BUFF A

TBMA

VAMX (29:14}

DRIVERS

FROM

PATHS

TAME

DATA

VAMX (139. 311}

120.12)

TBMA VA MUX (28 14) BUFF

Tamy

129 12)

BUS PA (29 12)

TBMF VA MUX (13 9. 31) B

(29 12)

TBMF

Lomm|

TBMP

A zfi:lx

’\

DOUT | TBMF
TBMF GRPO GRPO

DATA 1209)
DATA

(11:09)
TBMP
BMP
GRP GRP 0 DATA T (29-09)

[

TBML

TBMM

111 09)

TBML IPA DATA IN (29 09)

(11 09}
e

—

DIN

TBMC G1 MATCH BUFF _|

TBMF

PARITY

1 TBMF GO PAR (2 1) EV. 0D

TBMT MME BUFF

BUS

CHECK

TBMM

To v BUS LOGIC

TBMH

D
BUS

TBMT
8

ICLJ 1D RIGHT

ADDR (5.0}

ICLS 10
RIGHT WRITE

VA {08 02)

l5ecopE

FROM DATA PATH

REG

TBMU ER

TBMM {PA (0B 02)

TBMH GRP 0 DATA (11 08}
TBMH GRP 1

ramy

TBMK

TBMK PA (11 09)

5818 SBI PA (11 09)

TBMT ER REG 1 (20 00)

TBMK SEL {PA

CAMU TB GRP 0 MATCH

CAMU TB GRP 1 MATCH

TBMD SEL D MUX

BUS PA 108 02)

CAMV PROTECT
CODE (3 0)
CBHH CUR

FROM

DATA {11 09)

TBMF VA MUX (11 09)

REG O (20:00}

FROM
TB ADDRESS
MATRIX

TBMM (PA (29 09)
(11 09

“__TBMR SRP1 DATA (29 09}

DRIVERS

TEMX TRANS DATA (20 001

REG_0

1o
ICONTROUY

TBMR

DouT

DIN

T8M
P:R
(;roE)c 1 2

DATA

MATRIX| | ramH GRP1 DATA (20-9)

TBME REC 1D

(——_{20:00)

BUS 1D (20 00} xcvER

G1 PAR (2 1] EV.

CHECK

Gt
A

TBME

PARITY HoMH G

TBMH
L

16MB PROTECT CODE OK__
|necoperl TBME CAUSE PROT TRAP

1 oaqyrecTion

TBMC NOT SBI CYCLE

CODE LOGIC

TBMK SEL IPA

MODE (1 0}

PSL.
TBMB
T

onan

WVYHOVIA XO0178 XIHLVIN-VLVA H344N8-NOILVISNVHL

BUS CS (47°42)

TBMF GRP O WP L
CAMS

WP
_VAMX (31. 13:9)

‘

TO v 8US
LOGIC AND

TB REGISTER 0

R
CAMS GRP 0 PROTECT (3:0/MODIFY

DATA

AMS GO AD PAR

[~~*1 CHECK

FROM

CAMY
PARITY

CAMS GRP 0 VALID

matRix POUT] || cams GRP 0 ADRS (30.15)
cAMY

PATHS

pARITY

CAMR
(30:14]
{ DEP VAMX (30:14)

lDRIVERS

Ams

oIN

CAMS

crporanaor
0 PAR 2.0}

GRP

]

OMPARATOR

c
CAMU TB GRP 0 MATCH

[CAMU T8 PAR (10)

GEN
CAMU

A
CAMR
VA MUX X (30 (301 16} BUFF

CAMY

DRIVER

CAMV PROTECT (3.0)

TBMA VA MUX (30:15) BUFE

ON TBM

TO
8

r DATA

MATRIX

cAMY
BUS ID (31:26)
iD

BUS|

cAMUY

CAMV REC ID (31:26)

BUS ID PTY 3

RECEIVERS]

CAMV REC PAR 3

CAMT
Ll

CAMT GRP

PAR 2 0)

CoMPARATOR || CAMUY TB

GRP

MATCH

CAMT GRP 1 ADRS (30.15)

61
e

DOUT

CAMT GRP 1 VALID

MATRIX

[_C:W GRP 1 PROTECT (3 O1 MODIFY

CaMP
RO, TBMT FORCE ERR (2.0)
ol

BMT

FORCE

ERR

(2.0)

£CODER

CAMP DISABLE
GO (A2.40) _ TOTB
L
CAMP DISABLE G1

(A2 AD)

ADDRESS

CAMT G1 AD PAR

—

L —of Pl
e

CHECK
—

12.0) EV_OD

TOVBUS

socic ano

TB REGISTERO

TBMF GRP 1 WP L

CAMP DISABLE G1{AZ2A0) L

1K 0342

WVHOVIA 00178 XIHLVIN-SS3HAAV H344NA9-NOILVISNVYHL

CAMP DISABLE GO (A2:AQ)

SHF MUX
B2
|pelBs (Balsz

SHF MUX
SHF MUX
83
B4
Bs?e 85 T84 Yarles Teales

SHF MUX
B85
87
186

SHF MUX
B1
|Bs(ea |z (81

iDPL

1DPK

SHF 8O 7 0 SXT

10PD

VLA

SHF MUX
80
|Ba|82 |B1|BO

B3 7:0
DMX

DMX

Lol

— |

B6 |BUF

B7 {BUF

VAL BG 7.0

vAL|B7 70

BUFFER

BYTE 6

BYTE 7

(B6) D,,c

(B7) ,Dpc

VAL|B4 70

VAL,

BYTE 5

(BS) ,Dpc

BYTE 4

(B4) 1ppe

IMX

BUF B7 7:0

SHF BG 70

SHF as 7.0

SHF B4 7:0

RMD B3 7:0
IBA 1

IBAO—=

RAMD B2 70

AMD B170

}

§2

VAL[B2 7.0

BYTE 2

(B2) 1op8

B1 |BUF

VAL|B17.0

BYTE 1

(B1) ppa

DMX

BO [BUF

VAL|BO 7.0

BYTE 0

(BO) |DPA

SHF B1 VAL

SHF B2 VAL

SHF B3 VAL

DMX

oMxB170

DMX B0 7:0

{

BUFB170 1 NSTRUCTION

IMX BO 7:0 | DECODE

LOGIC

SHF BO VAL

IMX

SHF B2 7.0 SHF B17:0

1RC

SHF B0 70 1

AMD B0 7:0
Y3

-1

(83) 0p8

SHF B3 7:0

Y2
MEMORY DATA BYTE SHIFTER (25510)

VAL|B3 7:0

BYTE 3

B2 |BUF

IMX

B85

B3 [BUF

SHF B4 VAL

SHF B5 VAL

SHF B6 VAL

SHF B7 VAL

B4 |BUF

DMX B2 7:0

{DPN

BUS MD 07:00 (BYTE 0)
BUS MD 15: 08 (BYTE 1)

BUS MD 23:16 (BYTE 2)

MEMORY DATA

(MD) BUS

BUS MD 31:24 (BYTE 3)

Tr 0299

WYHOVIA 2018 4344N8 NOILONYLSNI

0. VA VAL S HF B4 7 0. VAL SHF B3 7:0. VAL ISHF B2 7 0. VAL ISHF 81 7:0. VAL
SHF HF 85 77 0.
S HF B6 7 0. VAL
IDPE

IRCF

MODE MUX

CODES

—_——

BRANCH

BR COND 2 0. VAX

DECODE

BR INSTR

LOGIC

IBUF EN (07:00}

(CALL = 3)

CONTEXT

IRCE

€TX39L specirien
CTX

POINT

DECODE

LOGIC

SERVICE

ADDRESS
fom

1B STALL,

SPECIFIER DECODE BITS

1RCC
I
EXECUTION !

IRCC

EXECUTION

ERRORS

SEL SPC

ADRS 07 00

VAX DECODE 7.0

SEL EXEC

TRAP.

—1" CIX30

EXCCT 2.0

COUNTER

IRCA

MICROSEQUENCER

DECODE

INTERRUPT,

T8 MISS

PDP-11

EXECUTION

ADDRESS

INSTRUCTION

BUEFER

[

IDPA

BYTE 1

svieo

IRCC

ROM

]

I__

CM DECODE 7:0

CM MODE (VAX) i

)'/—a
IRCB

SRC MODE

—_————

_DST MODE__|
SEL SRC

CM EXEC
TK-049C

WVYHOVIA X3079 3a023Ad NOILONYILSNI

CONDITION

NVHOVYIA XD0178 H1Vd Viva

EXPONENT SECTION

—~4= VAMX 31.16

TO ARITHMETIC SECTION

% VA 08:02

VAMX 15:09

IVAX MODE
l

'BUS CS {34:32]

BUS CS [15:13]

lTBUF ADDRESS
<p-

BUS CS |34 32!

INTERFACE

i
BUS CS (34:32

ADORESS SECTION

UPCK

BUS CS (17:16)

—

ARITHMETIC SECTION

r T

CON

BUS CS {69:66]

CON

FLOATING POINT OPERANDS

RLOG

16x9

t
RA ADDRESS.

KMX 03.00,

ADD/SUB BIT

]/[

[ATCH B

(LB)

necorsten] Ldmecisten|
B
SET
SE
(RB}
(RC)
i6 X 32

16 X 32

—— — S— —

[

roatnG

D NIBBLE SWAP

US!

BUS Cjcii“ 51}

Qamx

us Cs (91881

DATA

Jxcew

(LA}

RBMX

DATA

INTERNAL

(RA}
16 X 32

MEMORY

LATCH A

LdrecisTen
|
A
SET

8US

BUS CS [57 55|

DECIMAL

BUS CS [77] CONSTANT————

|
:.&'I;CH [

—

TO/FROM

ACCELERATOR

Eax

USPO

]

I\‘ DFMx

'——U“Mx

AMX

BUSCS (29261 BUS CS A1 3]

F
STACK

BMX \

(SD, EALU EXP, DREGI

8US CS [81:801

BUS CS {95:92]

—

DATA

DET

BUS CS (84:82]

3591

c————

ZERO

SHF

—

BUS CS {87:85]

BUS CS (63:58]

BUS
u

SCRATCH PAD REGISTER SETS
T o0z

SBI CLOCK

r--—a= STOPPED H

OSCAXF H

FREQUENCY | Osc2xF1A

GENERATION | osC2XF1 L

START/STOP/STEP

CONTROL

OSC2XF2 L

AND
SELECTION
(CLKM}

eTP 0 1H

T
GATEDCLK H

|SATEDCLK L | sequence

fee——,

GENERATOR

PCLK (1) H

PCLK (0} H
ST

DRIVER

(CLKS)

PDCLK (0 H

(CLKS)

KN
(CLKN)

SBITP H
SBIPCLK H
SBIPCLK L
SBIPDCLK H
SBIPDCLK L

JUMPERS
EXT OSC H

EXTERNAL OSCILLATOR

BRKMAT L

§ §

x E

CONTROL

SIGNAL

STS L —————o SYNCRONIZER |SBESYNC (1) H
sBs L

‘

(CLKT)

(CLKR}

Bl FAIL L

T T 1 1 T T T T

PSDCLO L

PSACLO L.

341

DCLO

ACLO

FROM POWER SUPPLIES

.
f——

CPU CLOCK DISTRIBUTION

SBI DEAD L

POWER FAIL FETS

|SOMM ENAB (1} H

SOMM L

PROSYNC (1) H

STSS:NC ( :' .

DISTRIBUTION

— -

(CLKP)

zgg’:ow PROCEED L
NTERFACE

———

FAKEDEAD L

SEQUENCER

FRO L

'——— | TOCPUCLOCK

FAKEFAIL L

SOWER UP

FROM MICROSEQUENCER
FRIL

SBITP L

TTerT

CPU POWER FAIL SEQUENCER

LEDS
(CLKJ)

[ 1

F—=

| .
-

DRIVERS |
(CLKB,

K
gtxg'

SBITPH :j

[——®] DECODERS
RECEIVER _—_—
SBITP L
SBIPCLK H ——d

SBIPCLK L ——

SBIPDCLK H ——af

SBIPDCLK L ——t}

(CLKA}

—*1
|——u]

(CLKA)

[

CLKE,

CLKE.

CLKH, |

PSEUDO - ECL

b CLOCK SIGNALS

BAT DCLO H

o/ cneen

PFAILINT (1) H

ACLO OR FAIL H

ACK PWR FAIL L ————

TO CPU MODULES

CPUACLO L
POWER FAIL .

QBUS ACLO L———
o

—scPUDCLO L

—

CNSL RESET L———f

F——————®sysiNITAL
b

SYSINITB L

(CLKK, CLKL) f——————#SYS INIT H

}—————— UPROG INIT H

CLKI | o ]
|

MAINT PF TEST POINT L

I
—_—

e
TK-0724

AVHOVIA X2019 3TNAON XIJ01D

—

WCS WR CYCLE

WCS |P,RS,T

WR SEL

32 DATA
le-3 PARITY-wte——

DATA

BUS CS 85 00

I EFHJ
wCs

wcsT K,L.MN
32 DATA

32 DATA—s
CSA 09 00

SELECTOR
ADDRESS
MUX

WCS ADRS 12

BUS UPC

WCS ADRS 10

WCSA

CS WR (95 64)

WCSA

€S WR (63-32)

€S WR 131 00)

WCS EVEN PAR

TO INTERRUPT

0900

\ycs apRs
08 00

+—+
+—+

+—+
DECODER

—+

DATA

—+

SELECTOR

+—+
}

CONTROL LOGIC

+—+
BUS UPC 12

EVEN

U;(

WCS ADRS 11

PARITY GEN

BUS UPC 11 ——1
WCSA

DATA 31 00!

8US UPC 10
CLK DELAYED

ENCODER

ODD

WCS

PAR INV

DATA 31 00

BD SEL 70

WR DATA 31 00

WR SEL

XCEIV

BUS 1D 07 00,

D BUS

WesB
BUS 1D 31 00

>
0215

WVYHOVIA MXJ018 (SOM) 3HOLS TOHLNOD 378VLIHM

CS BUS

2 0
Taus CS UPAR

PARITY
CHECKERS

BUS CS UPAR 2:0

BUS CS 85:00

BUS CS

raus CS UPAR 2:0

5US CS 95:00

cLK

DECODER TMTM g\ ecroR
——»

DATA

—

CLK DELAYED
~

_‘-::D}

e~ 3 PARITY

32 DATA

[
3 PARITY

32 DATA

32 DATA ——sfe—— 32

le—3 PARITY

32 DATA

32 DATA —

32 DATA ——f

BUS UPC 10 -

32 DATA ——ste—
32 DATA——f

DATA

——»

32 DATA

13
[

le
3 PARITY

! !

BUS UPC 12 -

BUS UPC 11—

32 DATA —»

8US UPC 09:.00

TK-0243

WVHOVIA X079 (SOd) 3HOLS TOHLNOD NOYd

PARITY ERROR INDICATORS

TO TRAPS AND INTERRUPT CONTROL

WRITABLE

CONTROL STORE

1PCS)

IWCS}

—(>
INSTRUCTION

DECODE

cLK

UPC LOOP

V BUS

USCF

CATCH

SERIAL OUTPUT

LOGIC

cPU

VvV BUS CHANNEL O

SHIFT REGISTER
uscL

UPC BUS

<‘r

uscJ

CONDITIONS | —"] SEQUENCER

USCF

ECO DISPATCH 06
USCF

UECO REG

UPC MuX

PICO

—

J‘>

LED S
CLK

FPA OR CiB UPC 12

FAOM FPA
OR CONSOLE

NUA BUS

{CONSOLE MAINT)

DECISION

POINT BRANCH
RETURN

CALL

BRANCH
MUX'S

NOP

DECODE

BRANCH

COMPARE

BREAK MATCH

RETURN

UPC BREAK REG I
uscc

MICRO

DECODE

INPUT

USUB REG J

BREAK

usuBs=2)

USTACK REG

ENABLE

us CA

RETURN

uscK

BRANCH

USCA

SYNC PULSE

USCH
=

usus

(N
MICROSEQUENCER
INPUTS

[

VARIOUS

WVYHOVIA X20718 HIONINOISOHIIN

PAOM

UPC 07 00

—

Cs BUS

<|r

STACK

WCS

(16 X 16)

ADDRESS

TO WCS

AND

SETS

CONTROL

UBEN REG

CS BUS

> {—

ID BUS

Ix 0734

f~———————=—* ROM NOP, UPC12
—————————— CLK CNTRLS

(> V BUS CNTRL
[V BUS CLK
SCP SWITCHES
ID ADDRS

AND CNTRL

|CLCINTR

V BUS DEL CLK

V BUS SER DATA >-|

ACK

[—<—‘PF SIGNALS

)[
CIBA.B
QBUS

e
o
Jre

+5v

<
a

[ciBC,D.E

DATA

CIBE

CIBK,jL

<
)

cigs

?Ds

VAXTT Jo

INPUTS

CNTRL

j2)

f {

MUX

INTR

LoGIC__

CIBA,B

tD BUS
XCVRS

QMuUx

DATA
o

MUx

|
o1

.M_‘C'R_‘
LOGIC
CIBN

1D BUS DATA

€c

CIBC.D,E

cigv

[4pons nes |

cigp

CIBS

Tie|

C18S

|me|

|rov]

CIBD.E

[one

CIBC,D

cisJ

FMip
a8US

PROTOCOL,

LOGIC

Q BUS SYNC/CONTROL

2
o

QBUS DATA/ADDRESS

CLOCKS, ENABLES

TERMINATOR

TERM-

cies,J

INATOR

TK-0195

NVYHOVIA X201789 adv09g 30V4H43LNI 3TOSNOD

—————-————-—e CNSL RESET

FAD

M8B288 SLOT 27

FNM m8285 SLOT 24

FMH/FML M8286/M8287 SLOT 25/SLOT 26

FRACTION NORMALIZER

FRACTION MULTIPLIER

FRACTION ADDER

WVYHOVIAQ D018 (Vdd4) HOLVHITIOOV LNIOd-ONILVO14

FCT m8289 SLOT 28

FPA CONTROL. SIGN PROCESSOR.
EXPONENT PROCESSOR
L

EXPONENT

DIFFERENCE

DOUBLE

PRECISION

TEMP
FALU

DALY

l
I

CARRYS

CALU
8

QUOTIENT

SIGN PROCESSOR

SHF

EALU —+»

PROCESSOR

LOGIC

MUX

144

OPCODE —

ADER

MUX

SIGN

EALU

SIGN

ouTt

out

25|32 74 25

BUS

rpg 4

CONTROL

OPCODE
SPECIFIERS

CONTROL,
STORE

512x48

|o1

QUTBUF
SEL
MUX

FPA CONTROL

FALU

MUX

BUS FP
8 < 33:00:

TO ALL

ROM | FPA LOGIC

HBRK

BUF.

NSHF

BUS FP
A < 33:00TM

pATA ——>|

l
I

BUS
DRIVERS

NEXT ADDRESS

32
-

CS BUS- .95:00 ~

SYSTEM D BUS - 31:.00°

BUS DFMUX .31 00+

(T .S)
T 0838

KA780 TR AND SYSTEM ID REGISTER JUMPERS

to Assert

Bit

—

Jle

B
]

]

Jll

(

]

J12

1
A

J13

System

TR Arbitration

Signal | SEL

Remove Jumper

Level

Bit

SEL

Name

TR#

Jlé
J

J1é
F

J1e
D

J1@
B

Signal

[

J13

Jl13

J13

Jl3

SYSTEM

Wire Wrap
FA2M2 to

S
6
7

J13
J1l3
Jl3

J3
FF
DD

SERIAL
NUMBER

Fp2Cl

8
9

J13
Jl13

BB
2

F@2D1

J13

)

MFG

’

-—

FO2E]

-—

FO2F2

FB2J1

Fo2M1

Jumper

FO2H2
F@2J2

Ji3

J13

Jl3

PLANT

-—

FO2N1

Faz2prl

FO2P2

J13

CLUSTER

FB252

13
14

I
I

FO2T2

Jlz

ECO

-—

FP2Ul

J12

Fé2u2

J12

ee-—-

24
25

Jl2
Jlz2

LL
J3

SYSTEM

Jl2

TYPE

Jl12

28
29

J12

92=?

Jl2

93=7?

Jl2

Ji2

SYSTEM IDENTIFICATION REGISTER (SID)

24 23

TYPE

1918

NUMBER

1514

LETTER

ECO LEVEL

1211

PLANT

SERIAL NUMBER

TRans

J1l3

Jl3

CPU

LEVEL

@1-11/788

KA780 WCS JUMPERS

WCS

Optional

Slot

J11

VWV

WCS

J1ll

P-1K | -

1-2K | —-

-—

-—-

2-3K | -

-—

-—-

3-4K | --

~--

-—-

4-5K

5-6K | I

6-7K | I

-—-

7-8K | I

for

PCS.

PCS

Slot

J12

NOTES:

Addresses

M8233

@-4K

addresses

are

increments.

M8238 starting addresses
even boundaries only.

are

increments

starting

are

reserved

and

begin

CHAPTER 3
MICROCODE

CONTROL STORE FIELD MAP

{15
14
13
12)
R
et e
B

]

EALLU

art

]

77
e

16}

e aatatd S DL

SMX

e e

72,

92]

s s

PCK

52}

ACF

48|
L

SGN

64)

68!

66
S

St Satat ]

ALY
e

86
L

H
o

H
T e

sus

88!

L ST

ST L

32}

H
bt Do

QK
e

{

H
o

BEN
B

56!

SI/ACM

18C
e

EBMX

36{

76,

SPO

IRMX}

20}

CCK

60}

el et

FS)

{179

40)

KMX

e e

61
e

gt
SO
L LD AL L

e At

00}

{VAK} FEK|SCK)}

MCT/CID
R

02
Ot
e Sl

et S

24}

e B

MSC

O5
04} 03
e S e D

1ADS)}

28}

07
06
i At

JMP

29
e

IEK

08,

09
e

amtt S

{

SHF
o

84)
S

'
e

82
o

BMX
§

e i

80!

e Al ]

OAMX
e =

MICROCODE ROUTINES THAT SUPPORT CONSOLE SOFTWARE

STARTING ADDRESSES

"CONSOLE

MICRO-CODE"®

MICRO-CODE

ROUTINES

SUPPORT

CONSOLE SOFTWARE.
AND IN ID[T1]),1D[T2]
STATUS IN ID[D.SV],
JAND ADDITIONAL INFORMATION IN ID[T3].
(PC IS USED WHENEVER R15 1S REFERENCED.
tROUTINES

&€xPECT

DATA

RXDB,

;AND

THEY

RETURN

DATA

TXD8B,

+NO

EFFORT

MADE

SAVE

INTERNAL

s INFORMATIGN AND PARAMETERS
ARE LOADED IN ID{RXCS] AND

;RESULTING DATA
{AND

STATUS

;ROUTINE:
.

EXAMINE

MEMORY

IS LCADED

INFORMATION

REGISTERS,

NEEDED FROM THE
1D{T1],ID[T2].

ID[TXD8]

LOADED

AND

CONSOLE,

ID{T3],

IO[D.SV].

START-ADDRESS:

PARAMETERS:{(*

120

ID[T1)=8BYTE,/WORD/LONG-PARAMETER

MEANS

SUPPLIED

ID[RXDB]=VIRTUAL

ADDRESS
ID[TXDB}=ME“IRY DATA
ID[T3}=PHYSICAL ADDRESS
I1D{D.SV]}=STATUS-CODE

.
.

CONSOLE)

’

DEPOSIT

MEMORY

121

1D{T1]=BYTE/WORD/LONG-PARAMETER
ID{RxDB]=VIRTUAL ADDRESS =*
10{T2)=MEVCRY DATA =
ID[TXDB]=PHYSICAL ADDRESS
I1ID[D.SV]=STATUS-CODE

122

ID[RXDB]=REGISTER

NUMBER

10[TXDB]=REGISTER

DATA

*
v

’

EXAM._GEN.REG.
v

=»

;DEPO.GEN.REG.
H

123

ID[RXDB]=REGISTER NUMBER
ID[T2]=REGISTER DATA =

;sEXAM.PROC.REG.

124

ID[RXDB}=REGISTER
ID[TXDB]=REGISTER

NUMBER
DATA

;DEP.PROC.REG.

125

ID[RXDB]=REGISTER NUMBER
ID[T2)}=REGISTER DATA =

;CONTINUE

127

;QUAD-CLEAR

129

;SBI-UNJUAM

124

ID[RXDB)=QUAD-ADDRESS

UCP<91>

UPC<@0>

NOP

ALU Z

ROR

LA<G1>

PSL<C>

LALGO>

Cc31

ALU C31

IRC.ROM

ACC UB®O

Name

IB.O

ACCelerator

ACC UB2

ACC

Read +
Modify

ASRC +
VSRC

ASRC +
Q + D

UB1

8
VAX

DATA TYPE

@ = Normal
1 =Q0+0D

2 = Field Src
3= Addr Src

8
-11

END DP1

Read +
Modify

D Class

J Class +
DM27

IR2-1

IR<2>

IRK1>

9
-11

PC Modes

SM or DM
47 + 57

Dst R
.eq. PC

REI

IB
running

IB ERROR +
DATA VALID

VAX

Mode

.1lt.

ASTLVL

IB TEST

MUL

SC.ne.®

D<@1>

D<Ag>

SIGNS

Q<31>

D.ne.0

D<31>

INTERRUPT

Internal

Interrupt

Request

DL7:08>

D<3:0>=

Decimal

#
1

= TB Miss
= Error

2 = Stall
3 = Data OK

Low

39-39

SNOILONN4 379VN3 HONVYHE 3A0J0HIIN

UPC<@2>

BEN

Name

UPC<@3>

uTrap

Last

Vector

EALU

ucp<gl>

UPC<0B0>

UVECT< 3>

uVECT<2>

uVECT<1>

uvECT<@>

-PSL<FPD>

Nested

-Read+

Error

-Intlk

Intlk

SC.ne.@

Sign

SC.gt.d

SC<9:5>

ALU<Q1>

ALU<QO>

Reference
12

UPC<@2>

EALU

Chk*

Src

1-31

.gt.31

cycle)

5C<9:8>
.ne.g

Rlog

ALUl-@

Empty

.eq.0

STATE7-4

STATE<7>

STATE<6>

STATE<LS5>

STATE<4>

STATE3-&

STATE<3>

STATE<2>

STATE<1>

STATE<D>

D<31:24>

D<23:16>

D<15:8>

D<7:0>

.ne.@

.ne.g

.ne.g?

D<A3>

D<@2>

D<@l>

D<aod>

Bytes

D3-9

ALU<1:8>

.ne.g

(previous

PSL

PSL<N>

PSLKZ>

PSL<V>

PSL<C>

ALU

IR<B>

ALU

BEN

Name

UPCk@@>

PSL

Mode

Translation
Test

C31

UPC<@4>

UPC<@3>

UpPC<e2>

UPC<a1>

~VAMX<31>

-VAMX<38>

-Console

-PSLCIS>*

Kernel

Mode

-PSL<KCM>

Mode

TB Miss +
Access Viol.

TB Miss +
1st Modify

PTE
~Valid

Data
Aligned

(LNOD) SNOILIONNL 379VN3 HONVHE 3A0J0HIINW

BEN

MICROTRAP VECTORS

Number

Function

100

System

Initialization

l1e1

Unaligned

102

Page

163

Modify

Data

Bit

104

Protection

165

Translation

Violation

Buffer Miss
Floating Operand

186

Reserved

107

Translation

108
189

Cache

10A

Reserved

10B

Trap

Parity

Buffer

Error

Parity

Reserved

1eC

RDS

16D
10E

Timeout or Error Confirm
0dd Address Error

1aF

Control

Error

Store

Parity

Error

DOPPOCOCOQ

MICROCODE MEMORY CONTROL FUNCTIONS

condition

utrap

utrap on cond:tion uniess MSC/
SECOND.REF or RETRY.NO.TRAP

hardware

not

ucode

qcoe

TEST.RCHK

03201

MEM.NQP

0010

TEST.WCHK

utrap

prevent

<<
<<

<~<Z
ZzZ2ZZ
Z

z 2z

22z
2
22z

<=~<ZZ

VALIDATE

WRITE.P

z2z2Z

22z
Z z

581.HOLD

<7ZZ

READ.V.NEWPC

pdid

=< <

READ.V.WCHK

LOCKREAD,V.NOCHK
LGCKREAD.V.WCHK

SBI.HCLD+UNJAM
INVALIDATE

EXTWRITE.P

LOCKWRITE.P

READ.P

zzZ

Abort

Trap?

z2Z

zZZz

Ref

—

—_-

P
LOCKREAD.
ALLOW.IB.READ

ZzZ

s
e

READ.INT,SUM

>
>
>

READ.V.NOCHK

KEAD.V.IBCHK

< < Z <

|
Z2
2

< 2Z2Z
Ed

22222

[=]

ZzZ

[«]
-

VAL

'
v

[eReRNoN]
[eNeNeoR ]

'
'

VUNUAM N
L INVAL, N

LOCKWRITE.V.XCHK

- .

READ.V.RCHK

(o]
_

- eh e

HOLD

-t s s

WRITE.V.WCHK

< <Z

< Z

[eRoN
ol o)

0011

WRITE.V.NOCHK

MEMORY

CEFAULT:
(A=any,

OPERATION

ALLOW

R=read)

condition

benaviour

must

READ

undefined.
condition

Field

Value

Scratch

aN-a5

[’}

[}

[’}

BUS

Pad

Operation

operation

Load

Write

pe~gF

Load

LC
RC,

LA,

;Address

SC@3:00

;Address

SC@3:00

;Address
by

13-17

[

Load

ACN

determined
value

;Address

18-1F

Write

RA,

;Address

20-2F

Load

ACN

determined
value

;Address

Write

;Address

[4]

Load

LA,

;Address

Write

RA,

;Address

Load

LA,

and

Write

;Address

Load

RA,

;Address
;Address
Register

Temporary

(T@-TF)

Write

General

(R1)
=

T70-7F

General
(R@-RF)

General
(RO-RF)

Temporary

(T@-TF)

50-5F

Temporary
(T@-TF)

General

(R@-R7)

Temporary
(T@P-TF)

General
(R1)

NOILVH3dO Avd HOL1V YOS

USPO
Hex

Machine

definition

ACF,

JACCELERATOR

ACM,

ADS,

ALU,

SNOILINIJA3d @1314 WOY TOHLNOD

.TOC

ACF/=<71:70>, ,DEFAULT=0

AMX"

CONTROL

NOP=0

SYNC=1

TRAP=2

CONTROL=3

ACM/z<573:55>

$ACCELLERATOR=DEPENDENT CUNTROL

JACCELERATOR

FUNCTION

MISCELLANEOUS CONTROL

PWR,UP=0
ABORT=1

tRETURN

ACCEL

MONITORING

1IRD

POLY.DONE=6

ADS/=<47:47>

3 ADDRESS

SELECT

VA=0

IBA=1
ALU/=<69:66>, .DEFAULT=0F
A=B=00

;ALU

CONTROL

FUNCTIONS

A=B,RLOG=01
A=B=1=202

INST,DEP=03

JINSTRUCTION

DEPENDENT

9€

A+B+1=04

A+8=05

A+B,RLOG=06
ORNOT=07

XOR=0W

ANDNOT=09

NOTA=0A

JA .GR. .NOT. B
tA .XOR, B
iA +AND, .NOT. B
3 «NOT. A

A+B+PSL.C=0R

OR=0C
AnD=00D

3A
:A

LOR. B
JAND, B

B=0E
AsOF

AMX/=<81:80>

$AMX

ALU

LA=0
RAMX=1

RAMX ,SXT=2

KAMX,0XT=3

3RAMX

SIGN

EXTENDED

ACCORDING

JRAMX

ZERN

EXTENDED.

OXT(L)=0

Machine

oP=0
=1
ROR=2

$NO

BEN,

BMX"

ENABLE

BRANCH

Cc3i=3
IRC,ROM=4
1B,0=sS
ACCEL=6
DATA,TYPE=S8

END,DP1=8
IR2=1=29
PC.MODES=9

3 (VAX

MODE)

$ (VAX
3 (=11

MODE)
MODE)

SRC.PC=0A

IB.,TEST=0B
MUL=Z0C

SIGNS=0D
INTERRUPT=0E
-

JBRANCH

3} ALU Z
$tLA<E>, PSL<C>, LA<O>
4 ALU C31, O
JOUTPUT OF EXTENDED IRC=ROM
$IB 0 READY
3CODE FROM ACCELERATOR
3 (VAX MODE) *, ASRC+VSRC, ASRC+Q+D
H
0=--NORMAL, 1==QUAD OR DOUBLE
3-=ADDRESS
2=--FIELD,
H

REI=0A

definition

$(=11 MODE)

3(=11
3

MODE)

O=-TB

%, O CLASS, J CLASS+DM27
IR<2:1>

¥,

MODE.LSS.,ASTLVL,
SRC R=PC

MISS,

JAC

D<31>

D.NE,.O,

LOW,

*%,

1=<=ERROR

$ 2--STALL, 3-=DATA
3SC.NE,0, D<1:0>

$Q<31>,

INTERNAL

INT

INTERRUPT,

REQ

DECIMAL=OF
UTRAP=10
LAST.REF=11

30, D BYTE O VALID DIGIT, D2-0 NEG
}MICROTRAP DISPATCH VECTOR
3=FPD, NESTED ERROR, LOW TwO BITS:

EALU=12

} 2=-=WRITE, 3=-READ, WRITE
;EALU N, EALU Z, SC.NEG,0,

sC=14
ALU1=0=15

STATET=4=16
STATE3=0=17
D.BYTES=18

D3=-0=19
PSL.CC=1A
ALU=1B

PSL.MODE=1C
TB.TEST=1D

BMX/=2<84382>
MASK=0
PC.OR.LB=1

PACKED.FL=2
LB=3

O==READ

SIGN

READ CHK

1--READ,

CHK
SS

SC<9:5>,NE,O

SC.GT.0,

JRLOG EMPTY, ALU<1:0>=0, ALU<1>,
3 (ALU BITS FROM PREVIOUS STATE)
$STATE <T7:4>
ISTATE <3:0>
JBYTES 3, 2, 1, 0 OF D,NE,O

ALU<O>

3D<3:0>

3N,Z,V,C OF PSL
JALU N, ALU 2, IR<O>, ALU C31
$§=VA<31:130>, =CONSOLE, IS+CM,
sPTE

VALID,

ALIGNED,

}

0==TRANSLATION

2==ACCESS

OK,

QUAD,

l==WR

VIOLATION,

PC=$
KMX=6

;D OR

KERNEL

CHK

3-~TB

$BMX TO ALU
$A 0 IN THE BIT SELFCTED
3LB UNLESS R=PC, THEN PC
3PACKED FLOATING

LC=4

REMX=7

INTERLOCK,

$1SC<9:8>,NE.0,

DST R=PC

SM474+SM57+DM4T+DM57,

AND

MISS

SC<4:0>

M=0

(LNOD) SNOILINIZ3a a7314d NOY T0HLNOD

«TOC

BEN/=2<76:72>, .DEFAULT=0

nachine

deflinltion

DEFAULT=0

;CONDITION

CCk,

CIb,

DK,

DT"

RESERVED

CODES
}Note

HRAA LA

=
PR L

NATIVE

[

SIZE

]

DEPENDENT

MODE

PSL

A
L

[

et 3

]

Cci

s« VALIDITY=<V1>;

Z.and.(ALU,eq,0)

ARX

SIGN

Z.and,(ALU.eq.0)

{

ALU

SIGN

ALU,.eq,0

AMX<O>

ALU

SIGN

ALU.eq,0

AMX

s VALIDITY=<VO>;

SIGN
*

NZLALU.VC.VC=6

y o VALIDITY=<V1I>;

ALU

SIGN

ALU,eq,0

C.AMX0=6

y e VALIDITYS<VOD>;

INST.DEP=7

]

;CONSOLE

NOP=1

:DEFAULT,

ACK=S

JSET

BUS

ALLOW

CONSOLE

CONTROL

AUTO

READ

ACKNOWLEGE

FLAG

FS/t

CONT=7
READ.SC=9

sCLEAR CONSOLE MODE
JREAD ID BUS REG SELECTED

§C

READ ,KMX=0H

JREAD

UKMX

WR1TE,.SC=0D

JWRITE

REG

SELECTED

WRITE .KMX=0F

JWRITE

REG

SELECTED

UKMX

LEFT

BUS

REG

SELECTED

DK/=<91:88>, ,DEFAULT=0
NOP=0

sDEFAULT,

LEFT2=1

sDOUBLE

SHIFT

RIGHT2=2
DIv=4

$COUBLE
3 IF NOT

SHIFT RIGHT
ALU CRY, SHIFT

HOLD

ELSE

LOAD

3SHIFT

LEFT

SHF

FROM

RIGHT=6

JSHIFT

SHF =8

$LOAD

SHF

MUX,

INTEGER

SHF .FL=9

sLOAD

SHF

RIGHT
MUX,

UNPACKED

ACCEL=0A

3LOAD

ACCELERATCR

G=0C

sLOAD

DAL.SC=0D

$LOAD

DALISC]

DAL,.SV=0E

JLOAD

DAL(SHF

CLR=OF

s LOAD

ZEROS

3DATA

TYPE

DATA

FORMAT
FLOATING

FROM

$REFLECT BYTES AROUND BIT
THRU

3 CONTROLS

3CONDITION

AMX

VAL)

SIGN/ZERQ

CODE

SETTING,

EXTENDER,
AND

WORD=}
BYTE=2

JINSTRUCTION

FORMAT

BUS

DAL

JDEFAULT

JANY

Instruction

INST.DEP=3

ARE

ALU,eq.0

LONG=0

SIGN"

COMPATIBILITY

tvic

)

DT/=<79:78>, ,DEFAULT=0

"AMX

SIGN

BYTE,.SwWAP=0B

AND

ALU

LEFT=5

;

ClD/=<45:42>

SIGN"

)

NZ_ALU.VC.O035

8¢

"ALU

NoAMX,Z2.1ST,.VC_VC=3
ROR=4

PSL

LOAD,UBCC=1

SET.V=2

NOP=0

OPERATION,
e

MODE

DEPENDENT =
ABOVE, OR QUAD/DOUBLE

SHF

MEMORY

AMOUNT,

REFERENCES

]

AMX<O>

dependent

|
|

it LoD LT

(LNOD) SNOILINIZ3A a1314 NOY TOHLNOD

« 1TUL

CCK/=<22:20>,

Machine

definition

EALU,

EBMX,

FEK,

FS,

IEK,

1BC"

ALU

JEXPONENT

Az0

OR=1
ANDNOT=2

B=3
A+B=4

A=B=5
A+1=6
MNABS,A=B=7

EBMX/=<19:18>
FE=0

?=ABS(A=B)

EALUY

JEBMX TO
sDEFAULT

kMX=1

AMX
. EXP=2
SHF
. VAL=3

FEK/=<24:24>, ,DEFAULT=0

NOP=0

VALUE

JSHIFT

JFE REGISTER CONTROL
sDEFAULT, HOLD

LOAD=1

}FUNCTION

SELECT

FOR

43~-46

MCT=0

FENABLE

MEMORY

CONTROL

ClD=1

JENABLE

BUS

AND

JINTFRRUPT

AND

EXCEPTION

IEK/=<31:30>

CONSOLF

CUNTRO!L

ACKNOWLEDGE

NOP=0O
ISTR=1

IACK=2
EACK=3

IBC/=<95:92>, ,DEFAULT=0
NOP=0

;STROBE INTERRUPT REQUESTS
3INTERRUPT ACKNOWLEDGE
JEXCEPTION

ACKNOWLEDGE

FUNCTIONS

CONTROL

;IBUF

sDEFAULT

STOP=1

FLUSH=2
START=3

sFLUSH

CLR,0,154

sCLEAR

BYTES

0,1

CLR,2,3=5

JCLEAR

BYTES

2,3

BDEST=7

$TRANSFER

LOAD

AND

BRANCH

IBA

(=11

OPCODE)

(=11

ISTREAM

DATA)

DISPLACEMENT

CLR,0=0C
CLR.1=0D

sCLEAR
JCLEAR

BYTE
BYTE

CLR,0~-3=0F

JCLEAR

BYTES

0~3

(=11

CLR,1=5,COND=OF

$CLEAR

BYTES

1=5

CONDITIONALLY

CLEAR

SPECIFIER,

THERE

0
1

ABSOLUTE,

6€

F§5/=<42:42>

ISTREAM

(VAX
(VAX

SPECIFIER

NOTHING.,
CLEAR
OR

OPCODE)
SPECIFIER)

IT.

DATA)
EVALUATION,

SELF~CONTAINED
1IF

IMMELCIATE,

DISPLACEMENT,

LITERAL,

CLEAR

THE

(LNOJ) SNOILINIZ3A aT1314 NWOY TOHLNOD

.TOC

EALU/=<15:13>

machine

;

definition

;1D

IRUF=0

$RD

DAY .TIME=1

JHD+WK

SYS.ID=3

JRD

ID,ADDR,

ADDRESS

RXCS=4

FRD+ WP

RXDB=S

sRD

TXCS=6

I1RD+WR

DATA FROM IB
sCURRENT TIME OF DAY...
; MUST READ UNTIL STOPS CHANGING
;SYSTEM IDENTIFICATICN
;CONSOLE RFCIEVE CONTROL/STATUS
sCONSOLE RECIEVFE DATA BUFFER
;7 (TO=1D REGISTER)
7CONSOLE TRANSMIT CONTROL/STATUS

TXDB=7

3 WR

;CONSOLE

3SPECIFIER/LITERAL

TRANSMIT

;7 (FROM=ID
;DATA PATH

DG=8
NXT,PER=9

IWR

CLK,CS=0A

$RD+WR

JINTEKVAL
JINTERVAL

DATA

(MAINT ONLY)
NEXT PERIOD REGISTER
CONTROL/STATUS
INTERVAL COUNT
CLOCK
CLOCK

INTERVAL=0B

JRD
;RD+WR

VECTOR=0D

SRD+WR

sCURRENT
;CPU ERROR/STATUS
JEXCEPTION & INTERRUPT

SIR=0F

JKD+WR

JSOFTWARE

INTERRUPT

PSL=0F

SHD+WR

;PROCESSOR

STATUS

TBUF=10

BUFFER

REGISTFR)
D/QG REGISTERS

CES=0C

CONTROL

LONGWORD

ACC,2=16

;TRANSLATION BUFFER DATA
;TR ERROR/STATUS 0
}TB ERROR/STATUS 1
JACCELERATOR REGISTER #0
JACCELERATOR REGISTER #1
$ACCELERATOR REGISTER %2

ACC,CS=17

JACCELERATOR

SILO=18

sNEXT ITEM
$SB1 ERROR

TBERO=12
TBER1=13

BUS

ACC.0=14

ACC.1=15

SBI1.ERR=19

CONTROL/STATUS
FROM SBI HISTORY
REGISTER

$SBI TIMEOQOUT ADDRESS
$FAULT/STATUS
;SB1 SILO COMPARATOR

TIME,ADDR=1A
FAULT=18

comMP=1C

7SB1I MAINTENANCE
$CACHE PARITY
$MICROSTACK
JMICRO BREAK

MAINT=10D
PARITY=tE

USTACK=20
UBREAK=21
wCS.ADDR=22

WCS,DATA=23

JwWR

JWRITING

WCS

COUNTS

ADDRESS

(LNOD) SNOILINIZ3a g1314 WOYH TOHLNOD

.TOC

ID,ADDR/=<63:58>

BUS

ADDRESSES

CONTINUED.

ADDRESSES

24«=3F

ARE

POBR=24

JPROCESS

P1BR=25

3PROCESS

SBR=26
KSP=28

7SYSTEM
JKERNEL

RAM

SPACE

SPACE
SPACE
STACK

LOCATIONS

BASE

BRASE REGISTER
POINTER

ESP=29

JEXEC

SSP=2A

7SUPERVISOR

usp=28

sUSER STACK POINTFR
3 INTERRUPT STACK POINTER

IsP=2C
FPDA=2D

STACK

POINTER

STACK

POINTER

D.SV=2E
Q.SV=2F

T0=30

}GENEKAL

TEMPS

PCBB=3A

3PROCESS

CONTROL

SCBB=3B
P1LR=3D

JSYSTEM CONTROL PLOCK BASE
sPROCESS 0 LENGTH REGISTER
;PRUCESS 1 LENGTH REGISTER

SLR=3E

JSYSTEM

Ti=31
T2=32
T3=33
T4=34
T5=35

T6=36
T7=37

(87

T8=38
T9=39

POLR=3C

LENGTH

BLOCK

EASE

«CREF
J/=<12:0>,
+NOCREF

,NEXTADDRESS

JNEXT

MICRO

WORD

ADDRESS

(LNOD) SNOILINI43d 1314 WOY TOHLNOD

;ID

Machine

.8=20
o151

.22
.3=3
.454
SP1,CON=S
SP2,CON=6

[A%

2ERO=6
sC=7

.14=8
+AR0=9
«34=0A
.28308
.40=0C
.50=0D
. TFFO=0E
+EF=0F
.80=10
.8000=11
FF=12
FF00=13
.1E=14
+3F=15
.TF=16
«71=17
.F=18
.10=19
.FFE8=1A
.FFFO=18B
.FFF8=1C

.20=1D
.30=1E
.18=1F
.3FF=20
.C=21
.D=22
.1F=23
L1F00=224

.DFCF=28
.4000=2C

definition

KMX"

JCONSTANTS QR
48 FROM FK
s#1 FROM FK
$#2 FROM FK

FROM

FROM FK
FROM FK
$SPECIFIER 1

143

CONSTANT

$SECIFIER 2 CONSTANT (=11
3 OR ZFROS (VAX MODE)
$SC(9:0]1 FRUM FK

38 = 3F: CONSTANTS

MODE)

(1 CYCLE SETUP IF ALU IN ARITH MODE)

$DECIMAL VALUE OF CONSTANT
(AF,JL,MH)
120
(AF,JL)
31160
352

(AF)

340

(AF)

364

(AF ,JL,MH,TF)

;80

(AF,MH)

;239
3128

(JL)
(AF ,JL,MH,TF)
(AF)

1255
=256
330
363
1127

(MH,TF)
(MH,AF,JL)
(AF)
(MH, AF,TF)

7=32768

(TF)

***%MACHINE=DEPENDENT!!!

(AF ,MH)

315
316
1=24
i=16

(MH,CM,AF,TF)
AF ,JL,TF)
(MH,
(MH,TF)
(CM,JL,TF,MH)

1-8
132

(CM,TF,MH)
(CM,JL,MH,TF)

348
124

(CM,AF ,MH,TF)
(MH,AF,TF)

31023

(CM)

212
513
131

(CM,JL,TF,MH)
(TF)
(AF,JL,MH,TF)

37936

(JL,MH)
(MH)

7176

;
1124
;=32

196

(CM)
(AF)
(JL)
(TF)

(JL)

!
(TF)*%%sMACHINE-DEPENDENT!

(LNOD) SNOILINIZ3d a7314 WOYH TOHLNOD

.TOC

KMX/=<63:58>

+F0=33

+C0=34
.6=35

.9236
+FFF6=37
FFF5=38

«1A=39
»24=3A
.1B=3B
FFFCz3C

+A=3D
. 7E=3E

SPARE=3F

(AF)***¥¥MACHINE~DEPENDENT!!
(AF)
C(AF)
(MH,JL, TF)
(AF)
(TF)
(TF)
(TF,MH)

(CM,JL,TF)
(cm)
(CH)
(CM)
(CM,AF,TF)

(CM,MH)
(CM,AF,TF)
(CM,TF,MH)
C(AF ,MH)
C(AF,TF)

(LNOD) SNOILLINIZIA AT314 WOY TOYLNOD

+FFF1=2D
. 19=2E
FFF9=2F
+FFFF=30
.88=31
.3030=32

Machine

definition

TEST.RCHK=00
MEM

NOP=02

TEST.WCHK=04
WRITE.V.NOCHK=0A

WRITE,V.WCHK=0C
LOCKWRITE,.V,XCHK=0E
READ,V,RCHK=10
READ,.V.NOCHK=12
READ,.V,WCHK=14
READ,.V.IBCHK=16
READ.V.NEWPC=18

144

LOCKREAD.V,NOCHK=1A
LOCKREAD.V.WCHK=1C
SBI.HOLD=20
SBI.,HOLD+UNJAME22
INVALIDATE=24
VALIDATE=26
EXTWRITE,P=28

MCT,

MSC®

JMEMORY CONTROL
JTEST TBUF WITH READ CHECK
JNEITHER CPU NOR IB GETS MEM
JTEST TBUF WwITH WRITE CHECK
JWRITE,

INHIBIT

TRAPS

JWRITE,

NORMAL

VARIETY

$INTERLOCK WRITE, VIRTUAL
IREAD, NORMAL VARIETY
JREAD,

INHIBIT

CYCLE

ADDRESS

TRAPS

JREAD FOR MODIFY
JREAD, CHECK CONTROLLED B8Y IBUFFER
JBEGIN NEW INSTRUCTION STREAM
3 DATA GOES TO INSTRUCTION BUFFER
sINTERLOCK READ, INHIBIT CHECK
fINTERLOCK READ, NORMAL VARIETY
$STOP ALL SBI ACTIVITY
JRESET SBI
JCLEAR CACHE ENTRIES
$MICRODIAGNOSTIC FORCE VALID
SEXTENDED WRITE TO CLEAR MOS ERRORS

WRITE.P=2A

JWRITE,

LOCKWRITE,P=2E
READ.P=32
READ,INT.SUME36
LOCKREAD.P=3A
ALLOW,.IB.READ=3E

$INTERLOCK
JREAD,

PHYSICAL

WRITE,

PHYSICAL

$INTERRUPT SUMMARY READ
JINTERLOCK READ, PHYSICAL
JGIVE IB A CYCLE IF IT wANTS ONE

MSC/=€29:26>, ,DEFAULT=0
NOP=Z0
CHK.CHM=01

CHK.FLT.OPR=02
CHK.ODD.ADDR=03
IRD=04
LOAD.STATE=05
LOAD.ACC.CC=06
READ,RLOG=07
CLR,.FPD=08
SET.FPD=09
CLR.NEST.ERR=0A
SET.NEST.ERR=0B

SECUND.REF=0C
RETRY.NO.TRAP=0D
RETRY.TRAP=0E
INH,CM,ADDK=OF

JDEFAULT

JCREATE NEw PSL FOR CHM
SUTRAP IF ALUK1S>=1, ALU<14:7>=20

3THIS STATE

INSTRUCTION DECODE

:TAKE CONDITION CODES FROM ACCELERATOR
$ (AND

POP RLOG STACK)

JCLEAR PSL<FPD>
3SET SAME

BIT

;CLR NESTED ERROR FLAG IN CPU STATUS

}SET SAME
3OF UNALIGNED DATA REFERENCE
sAPPLY SAVED CONTEXT, INHIBIT TRAPS
3APPLY SAVED CONTEXT TO THIS REF

3ALLOW USE OF FULL 32-BIT ADDRESS

(LNOJ) SNOILLINIZ3Q a731d WOYH TOHLNOD

MCT/=<47:42>, ,DEFAULT=3E

Machine

NOP=0

PC.VA=1

definition

PCK,

$ADDRESS

OK,

COUNT

RAMX,

RBMX*"

CONTROL

sDEFAULT

PC.IBA=2
VA+4=)]

PC+1=4
PC+2=5

PC+4=6

PC+N=7

SVALVA+4
JPCaPC+1
3PC..PC+2

3PC.PC+4
JPC.PC+N,

$DEFAULT,

HOLD

DETERMINED

INSTR

BUFFER

QK/=<54:51>, ,DEFAULT=0

NOP=0

LEFT2=1

}DOUBLE

SHIFT

RIGHT2=2

LEFT

;DOUBLE

SHIFT

RIGHT

LEFT=S
RIGHT=6
SHF=8
SHF ,FL=9
DEC.CON=0A

ACCEL=08

D=0C
ID=0E

CLR=0F
RAMX/=<77:77>, .DEFAULT=0

D=0
Q=1
RBMX/=<17:77>

Q=0
D=}

LOAD
LOAD

SHF,

INTEGER

SHF,

UNPACKED

FORMAT
FLOATING

FORMAT

sDECIMAL CONSTANT = 6°S IN EACH NIBBLE
JFOR WHICH ALU CRY OUT IS FALSE
$LOAD ACCELERATOR DATA FROM DF BUS
JLOAD
#LOAD

ID BUS
ZERO

$DATA PATH
sDEFAULT

MIXER

AMX

}DATR

MIXER

BMX,

PATH

SAME

BIT

RAMX

(LNOD) SNOILINIZ3AQ aT131d WOYH TO0HLNOD

.TOC

PCK/=<34:32>, ,DEFAULT=0

"
NOP=0
LOAD=1

SGN/=<50:48>, ,DEFAULT=0
NOP=O

LOAD,SS=1
SS.FROM,SD=2
NOT.SD=3

SD.FROM.55=4
S8 .X0R ALU=S
ADD,SUB=6
CLR.SD+58=7

SHF/=<87:85>, ,DEFAULT=0
ALU=0

LEFT=}
RIGHT=2
ALU.DT=3
RIGHT2=4

LEFT3=5

S1/5<57:55>, ,DEFAULT=3

D1VD=0
ASHR=1

ASHL=2

ZEKRO=3

s SCK, SGN, SHF, SI1, SMx"

Machine deg¢inition

SPARE=4
DIV=S
MUL+=6
MULe=7

SMX/=<17:16>
EALU=O
FE=1
ALU=2
ALU,EXP=3

3SC

s DEFAULT,

3LOAD

CONTROL

HOLD

SMX<09:00>

$SIGN CONTROLS
sDEFAULT
35SLALUC1S>

3SD.ALU<15>,

SS_SS.XOR,ALU<C1S>

1SD_ALUC1I5>, SS.SS.XUR,ALUC19>,X0R,IRCI>
;CLEAR

BOTH

;ALU SHIFTER CONTROLS
3DEFAULT, SHF.ALU

$SHFLALU(L1),

$SHF_ALU(R1),

INSERT SI CNTL
INSERT SI

CNTL

$SHF_ALU(DT: LO,L1,L2,L3), INSERT O

3SHF.ALU(R2),

INSERT SI CNTL

3 SHF.ALU(L3)

3SHIFT
:

INPUT CONTROLS
D
SHF

’

;
H

PSL<N>
ALU 31

Q31
QO

ALU C31
Q31

D31

H
3

G311
0

ALU C31
031
ALD 0,1 0

;
JMIXER

JEALU <9:0>
sFE<930>
3ALU<C0S:00>
JALU<14:07>

ALU 0,1

(LNOJ) SNOILINIZ3d G1314 WOY TOHLNOD

.TOC

SCK/=<23:23>, ,DEFAULT=0

Machine definition

NOP=0

LOAD.LC.5C=6
WRITE,RC,SC=7

SWRITE

WRITE.RAB=3

SP1,SP1=0
SP2.5P2=1
SP2.,5P1=2
PRN=3

PRN+1=4
§C=S

SP1+1=6

SPO.ACN11/=<37:35>

3LOAD
3LOAD

LALRN,

$WRITE

RA,

NUMBER

SPO

MODE

30
51
12
33
1

13-

SP1

HOLD

FI ELD
RB

SP1 R
SP2 R
SP2 R
PRN
PRN+ 1
8C«<0 3:00>

PRN+1}
SC<03:00>

SRC

5C<0 3:00>

WRITE,RC=3

LOAD.LAB=4
WRITE,RAB=S
LOAD,LAB1 ,WRITE.RC=6

LOAD.LC.WRITE.RAB1=7

JWRITE

JLOAD

RA,

LA,

PRN

R+l

MODE
RB

SRC
SRC

LOW

AN D

WRITE

AND WR ITE RA,

SRC R
SRC R ,OR,
S$C<03:00>

PITS

LB[R1),

JLOAD LC(RN1l,

DST R

,OR,

$SCRATCH PAD FUNCS W ITH
JLOAD LC, ADR=S5PO.RN
$WRITE RC
3LOAD LA, LB

R
R
R

SP1
SP2
SP1

SP1

FI ELD
RA
SRC R
DST R
DST R
SRC R

SPO

SRC.OR.1=4
5C=S

SPO.R/=<41:39>
LOAD.LC=2

SRC,.SRC=3

DST.SRC=32

SPO.R"

BITS

(ACN)

P+1

BITS OF SPO FIELD
FROM RCACN)

$AC NUMBER
}=11 MODE
0
’
1
i
2
’
3
i

SRC.SRC=0
DST.DST=1

}

$AC

$VAX

LA,

UPCODE,

AD R=zsC(03:00]
A DR=SC[03:00)

FUNCTION

SPO,AC/E<41338>
LOAD.LAB=1
LOAD.LA=2

PAD

RC,

SPO.ACN11,

SPO.ACN,

SPO.AC,

3SCRATCH
$DEFAULT
JLOAD LC,

. DEFAULT=0
SPO/=<41135>,

SPO.ACN/=<37:35>

SPO,

RCLRN)

RB[R1)

ADR

(LNOD) SNOILINIZ3A a131d WOH TOHLNOD

. TOC

Machine

definftion

JRA/RB

RO=0

SPO,RAB,

SPO.RC,

SUB,

VAK"

LOCATIONS

R1=1
R2%2
R3=3
R4=4

R5=5
R6=6

R7=7
AP=0C

FP=0D
SP=0E
R15%QF

SPO,RC/=<38835>

T0=0

JR12
3R13
$R14

=
=

ARGUMENT LIST POINTER
STACK FRAME POINTER

STACK

#R15

PC,

JRC

POINTER

TO SOFTWARE,

SCRATCH

TO UCODE

LOCATIONS

Ti=1
T2=2

T3=3
T4=4
TS5=5

T6=6

T7=7

LC.sv=g
VA,5v=9

$MEM

MGMT

SAVES

MERE

PTE.VAZ0A
PTE.PA=0B
PC.SV=0C

SC,SV=0D

VA .REF=0E
MBIT,VA=0F

PTE.MASK=OF
SUB/=<65:64>, ,DEFAULT=0
NOP =0

CALL=1
RET=2

$SUBROUTINE CONTROL
JDEFAULT
JPUSH UPC OF THIS MICROINSTRUCTION
!} ONTO USTACK
$"OR" TOP OF USTACK TO UPC
3

SPEC=3

AND

POP

JREPLACE

USTACK

LOW

UPC

INSTRUCTION

WITH

VAK/=<25:25>, ,DEFAULT=0
NOP=0

sDEFAULT

LOAD=1

JLOAD

BITS

SPECIFIER

BUFFER

DECODE

FROWM

(LNOD) SNOILINI43a @1314 WOY TOHLNOD

SPO.RAB/=<38:35>

Machine

definition

Validity

Reglons"

checks"

+SET/VO=< NOT{<KNATIVE>}>
+SET/V1=<NATIVE>

Macro
D

|
|
]
|
|

L L

|
|
I
]
t
{

|
|

W6
e

Q-------’-----’---.-----------------*

V¢

]

]
|

|
|

PCS

!
|

I
|
|

We
e
%s

|
t

4095

4096

6143

6144

7167

]

]
|

]

DEC’S

region

1
|

|
|
I

|
]
|

User

WCS

G&H

WwWCS

I
|
I

]
]

Q-----.-Q----Q------‘.-.----------.’

I
|
{
|
I

Ts
%a

1FFF

1C00

|
|
|
|
|

.SET/WCSR3H=1BFF

|
|

+SET/WCSR3L=1800

01
|
|
|
|

|
|

«SET/WCSR2L=1200
+SET/wCSR2H=1T7FF

«SET/WCSRI1L=1000
+SET/WCSRIH=113F

detinition

.T0C

7168

8191

|
|
I
]
|

7k
to
Bk

i
|
|
|
|

User

wCs

|
|
{
]
]

brocconniononjoccasnanrdtooanenasEEed

hote

1140

1iFF

the FPLA trap
address region

SOHOVIN 3A0J0YIIN WILSAS

. TOC

ALU-OC(A)
ALU.O+D
ALULO+D+1

ALULO+K
(]
ALULO+K[]+1
ALULO+LB+1

ALULO+LC
ALU_O+LC+1

ALU_O+MASK+1
ALU.0+Q
ALULO+Q+1
ALU.O=D
ALULO=D=-1

ALULO=KI]
ALULO-K([]=1

0§

ALULO~-LB
ALULO-LC
ALULO=LC=1
ALULO=Q
ALU.O0=Q=1

ALULOL)ID
ALULO(ILC
ALULD
ALU.D(B)

Macro

definition

Reglister

transfer

macros"”

"AMX/RAMX.0XT,DT/LONG,ALU/NOTA"
"AMX/RAMX,0XT,DT/LONG,ALU/ATM

“AMX/RAMX,0XT,DT/LONG,RBMX/D,BMX/RBMX,ALU/A+B"
"AMX/RAMX.OXT,DT/LONG,RB¥X/D,BMX/RBMX,ALU/A+B+L"
"KMX/@1,BMX/KMX,AMX/RAMX ,OXT,DT/LONG,ALU/A+B"
"KMX/@1,BMX/KMX,AMX/RAMX,0XT,DT/LONG,ALU/A+B+1"
"AMX/RAMX,0XT,DT/LONG,RMX/LB,ALU/A+B+1"

"AMX/RAMX,0XT,DT/LONG,BMX/LC,ALU/A+B"
"AMX/RAMX,OXT,DT/LONG,BMX/LC,ALU/A+B+1"
"AMX/RAMX,0XT,DT/LONG,BMX/MASK,ALU/A+B+1"
"AMX/KAMX,0XT,DT/LONG,RBMX/0,BMX/RBMX,ALU/A+B"
"AMX/RAMX,OXT,DT/LONG,RBMX/Q,BMX/RBMX
,ALU/A¢B+1"

"AMX/RAMX,0UXT,DT/LONG,RBMX/D,BMX/RBMX,ALU/A=B"
"AMX/RAMX,0XT,DT/LONG,RBMX/D,BMX/RBMX,ALU/A=B=1"
"AMX/RAMX,0XT,DT/LONG,KMX/81 ,BMX/KMX,ALU/A=B"
"KMX/@1,BMX/KMX,AMX/RAMX ,0XT,DT/LONG,ALU/A=B=1"
"AMX/RAMX,0XT,DT/LONG,BMX/LB,ALU/A=B"
"AMX/RAMX,0XT,DT/LONG,BMX/LC,ALU/A=B"
"AMX/RAMX.0XT,DT/LONG,BMX/LC,ALU/A=B=1"
"AMX/RAMX,0XT,DT/LONG,RB¥X/Q,BMX/RBMX,ALU/A=B"
"AMX/KAMX.OXT,DT/LONG,RBMX/Q,RMX/RBMX
,ALU/A=B=1"
"ALU/@1,AMX/RAMX ,0OXT,LONG,BMX/REMX ,RBMX/D"
"ALU/®1,AMX/RAMX,0OXT,LONG,BMX/LC"
"RAMX/D,AMX/RAMX,ALU/A"

ALU_D+LB

"RBMX/D,BMX/RBMX,ALU/B"
"RAMX/D,AMX/RAMX,KMX/83
,BMX/KMX , ALU/A+B"
"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/A+B+1"
"AMX/RAMX,RAMX/D,KMX/@1,BMX/KMX,ALU/A+B.RLOG"
"RAMX/D,AMX/RAMX,BMX/LB,ALU/A+B"

ALULD+LC

“RAMX/D,AMX/RAMX,BMX/LC,ALU/A+B"

ALULD+LC+1

"RAMX/D,AMX/RAMX,BMX/LC,ALU/A+R+1"
"RAMX/D,AMX/RAMX ,BMX/LC,ALU/A+B+PSL.C"
"RAMX/D,AMX/RAMX ,RBMX/Q,BMX/RBMX,ALU/A+B"
"RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX
,ALU/A+B+1"

ALU.D+KI[]
ALU.D+K[]+1
ALULD+K
(] .RLOG

ALULD+LC+PSL.C

ALU.D+Q
ALU.D+Q+1
ALULD+0+PSL.C
ALULD+RLOG

ALU.D=K[]
ALU_D=K{])=1

"ALU/A+B+PSL,C,AMX/RAMX
,RMX/BMX ,RBMX/Q,RAMX/D"
"ALU/A+B,AMX/RAMX ,RAMX/D,BMX/0,#SC/READ.RLOG"
"RAMX/D,AMX/RAMX
,KMX/@1 ,HMX/KMX ,ALU/A~B"
"RAMX/D,AMX/RAMX
,KMX/@1 ,BMX/KMX,ALU/A=B=1"

ALULD=LB

"RAMX/D,AMX/RAMX ,BMX/LB,ALU/A=B"

ALU.D=LB,RLOG

"RAMX/D,AMX/RAMX,BMX/LB,ALU/A=B,
RLOG"

ALU.D=LC
ALU_D=LC=1
ALU.D=Q
ALULD=Q=1

"RAMX/D,AMX/KAMX ,BMX/LC,ALU/A=B"

ALU_D,OXT()
ALULD.OXT)+K
L]
ALULD.OXTL]+LC
ALULD.OXT(]+Q
ALULD.OXTL]}=K[])

"RAMX/D,AMX/RAMX,BMX/LC,ALU/A=B=~1"
"RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX
,ALU/A=B"
"RAMX/D,AMX/RAMX ,RBMX/Q,BMX/KBMX ,ALU/A=B=1"
"RAMX/D,AMX/RAMX
. 0XT,DT/81,ALU/A"

"RAMX/D,AMX/KAMX,OXT,DT/81,KMX/02,BMX/KMX,ALU/A+B"
"ALU/A+B,AMX/RAMX.0XT,DT/@1,RAMX/D,BMX/LC"
"ALU/A+B,AMX/RAMX,0XT,DT/@1,RAMX/D,BMX/RBMX,RBMX/Q"
"RAMX/D,AMX/RAMX
. O0XT,DT/®1,KMX/82,BMX/KMX,ALU/A~B"

(LNOD) SOHOVI 3C0J0HIIN WILSAS

.TOC
ALUa=1

ANDNOT, K]

ALULD,OXT[),.OR,Q
ALU.D.AND.K
]
ALULD,AND ,MASK

ALULD.ANDNOT,
K (]
ALULD.ANDNOT,MASK
ALU.D,ANDNOT.Q

ALULD,OR.K]
ALU.D.OR.LC
ALULD.OR.Q
ALU.D,OR.RCI[]

ALU.D.DRNOT,MASK

ALU.D.SXT(]

ALULD.SXT(1+K([}
ALULD.SXT()+G

ALULD.SXT[).ANDNOT
K[}
ALU.D,.SXT([).,AND.K(]
ALU.D.XOR.K[]
ALU_D.XOR,LC

ALULD.XOR,Q
ALULD.XOR.RCI[]

ALULD.XOR.RI[]

ALULDIIKI{)
ALULDILILB
ALULDILILC
ALU.DI)OQ

ALUK(]

"RAMX/D,AMX/RAMX,.0XT,DT/@1 ,RBMX/Q,BMX/RBMX,ALU/A~B"
"RAMX/D,AMX/RAMX.0XT,DT/@81,KMX/82,BMX/KMX,ALU/AND"
"ALU/ANDNOT,AMX/RAMX.0OXT,DT/@1,RAMX/D,BMX
,KMX/@2"
/KMX
"RAMX/D,AMX/RAMX,0XT,DT/@1,BMX/RBMX,ALU/OR"

"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/AND"
"RAMX/D,AMX/RAMX ,BMX/MASK,ALU/AND"

"KAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/ANDNOT"

"KAMX/D,AM
,BMX/MASK
X/RAMX
,ALU/ANDNOT"
"RAMX/D,AMX/RAMX ,KBMX/Q,BMX/RBMX,ALU/ANDNOT"

"RAMX/D,AMX/KRAMX,KMX/@1,BMX/KMX,ALU/OR"

"RAMX/D,AMX/RAMX ,BMX/LC,ALU/UGR"
"RAMX/D,AMX/RAMX,RBMX/0,BM,ALU/OR"
X/RBMX

"KAMX/D,AMX/RAMX,SPO.R/LOAD,LC,SPO.RC/R1,BMX/LC,ALU/OR"
"RAMX/D,AMX/RAMX,BMX/MASK,ALU/ORNOT"

"RAMX/D,AMX/RAMX,SXT,DT/@1,ALU/A"

"RAMX/D,AMX/RAMX .SXT,DT/@1,KMX/82,BMX/KMX,ALU/A+B"

"RAMX/D,AMX/RAMX ,SXT,DT/@1,BMX/RBMX,ALU/A+B"

“"RAMX/D,AMX/RAMX .SXT,DT/®1,ALU/ANDNOT,BMX/KMX ,KMX/82"

"RAMX/D,AMX/RAMX .SXT,DT/@1,KMX/@2,BMX/KMX,ALU/AND"
"RAMX/D,AMX/RAMX ,KMX/R1,BMX/KMX,ALU/XOR"
"RAMX/D,AMX/RAMX ,BMX/LC,ALU/XCR"
"RAMX/D,AMX/RAMX,RBMX/Q,BMX/RKBMX,ALU/XOR"

"HAMX/D,AMX/RAMX,SPO,R/LOAD.LC,SPO.RC/@1,BMX/LC,ALU/XOR"
"RAMX/D,AMX/RAMX,SPO.R/LOAD.LAB,SPO.RAB/®1,BMX/LB,ALU/XOR"

"RAMX/D,AMX/RAMX ,KMX/82,BMX/KMX ,ALU/@1"
"ALU/@1,AMX/RA¥X,RAMX/D,BMX/LB"
"RAMX/D,AMX/RAMX ,BMX/LC,ALU/@1"
"RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX,ALU/@L"
"KMX/81,BMX/KMX,ALU/B"

ALULLA

"AMX/LA,ALU/A"

ALU_LA+KI[]

"AMX/LA,KMX/@1,BMX/KMX ,ALU/A+B"

ALULLA+K
(] +1
ALU_LA+K([].RLOG

ALU_LA+LB
ALULLA+LC

ALULLA+LC+1
ALULLA+LC+PSL.C
ALU_LA+Q

ALULLA=~D
ALU.LA=D=1

ALULLA=K[]
ALULLA=K{]=1

ALU_LA=K
() .RLOG
ALULLA=LC
ALU.LA=Q
ALULLA=Q=1

ALULLALAND,K(]
ALULLALAND,LC

ALU_LA.ANDNOT.K
(]
ALU_LA.ANDNOT.MASK

"ALU/A+B+1,AMX/LA,RMX/KMX,KMX/@1"
"AMX/LA,KMX/@1,BMX/KMX,ALU/A+B,RLOG"
"AMX/LA,BMX/LB,ALU/A+B"
"ALU/A+B,AMX/LA,BMX/LC"

“ALU/A4B+1,AMX/LA,BMX/LC"
"ALU/A+B+PSL,C,AMX/LA,BMX/LC"
"ALU/A4B,AMX/LA,BMX/RBMX,RBMX/Q"
"AMX/LA,KBMX/D,BMX/RBMX ,ALU/A=B"
“AMX/LA,RBMX/D,BMX/RBMX ,ALU/A=B=1"

"AMX/LA,KMX/R1,BMX/KMX ,ALU/A=B"
"AMX/LA,KMX/81,BMX/KMX ,ALU/A=B=}"
"AMX/LA,KMX/@1,BMX/KMX,ALU/A=B
,RLOG"

"ALU/A=B,AMX/LA,BMX/LC"
“ALU/A=B,AMX/LA,BMX/RBMX,RBMX/G"
®"ALU/A=B=1,AMX/LA,BMX/RBMX,RBMX/Q"
"AMX/LA,KMX/@1,BMX/KMX,ALU/AND"
“ALU/AND,AMX/LA,BMX/LC"
"AMX/LA,KMX/@1,BMX/KMX ,ALU/ANDNOT"
"AMX/LA,BMX/MASK,ALU/ANDNOT"

(LNOD) SOHOVIN 3A0J0HIIN WILSAS

ALU.D.OXT[])=Q

ALULD.OXT(].AND,.
K[}
ALULD.OXT()

ALU_LATILB

ALULLAL)Q
ALU.LB
ALU.LC
ALU_NOT.D
ALU.NOT.K{]

ALU_NOT.RCI]
ALULPACK.FP

ALU_PC
ALU.Q

ALU.Q(B)
ALU_Q+K[)
ALULQ+K[]1+1
ALULQ+LB
ALULG+LB+1
ALULQ+LC
ALULQ+LC+1

ALU_Q+LC+PSL.C

¢s

ALULQ+MASK

ALULQ=D
ALU.Q=D~1
ALULO=KI[]

ALULO~LB
ALULG=LC
ALULQG=MASK=1

ALULQ.OXT(]
ALULQG,OXTL(]+D

ALU_G.OXT[)+D+1
ALULG,OXT{l+K(]
ALULG.OXT(]=D
ALU_Q.OXTI[)=K()
ALULQ.OXT[].,ANDNOT
K]
ALU.Q,OXT[).OR.K()
ALUL.Q.OXT([].OR.D
ALULQ.AND.D

ALULQ,AND.K
(]
ALULQ.ANDNOT,K(]
, MASK
ALU.Q.ANDNOT
ALULQ.ANDNOT,.R{]
ALULG.OR.K[]
ALULQ,OR.LC
ALU.G.ORNOT,.K{]
ALULQ,SXT(]
ALULG,.SXTLI+K({]
ALULG.SXT[]I+LB
ALULQ.SXT()+LB+1
ALULO.SXTL)+PC

*ALU/OR,AMX/LA,BMX/KMX,KMX/01"

"AMX/LA,BMX/LC,ALU/XOR"
"AMX/LA,RBMX/D,BMX/RBMX,ALU/81"

"AMX/LA,BMX/LB,ALU/RL"
"AMX/LA,RBMX/Q,BMX/RBMX,ALU/@1"
"BMX/LB,ALU/B"

"BMX/LC,ALU/B"
"ALU/NOTA,AMX/RAMX,RAMX/D"

"BMX/KMX ,KMX/®1,ALU/ORNOT,AMX/RAMX,0XT,DT/LONG"

*SPO.R/LOAD.LC,SPO.RC/91,BMX/LC,AMX/RAMX,0XT,DT/LONG,ALU/ORNOT"

"BMX/PACKED.FL,ALU/B"
"BMX/PC,ALU/B"
"RAMX/Q,AMX/RAMX ,ALU/A"
"RBMX/Q,BMX/RBMX,ALU/B*

"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/A+B"

/KMX
,KMX/@L"
"ALU/A+B+1,AMX/RAMX,RAMX/Q,BMX

"RAMX/Q,AMX/RAMX,BMX/LB,ALU/AR+B"
"RAMX/Q,AMX/RAMX,BMX/LB,ALU/A+B+§"
"RAMX/Q,AMX/RAMX,BMX/LC,ALU/A+B"
"ALU/A+B+1,AMX/RAMX,RAMX/G,BMX/LC"

“ALU/A+B4PSL.C,AMX/RAMX ,RAMX/Q,BNMX/LC"
"ALU/A+B,AMX/RAMX ,RAMX/Q,BMX/MASK"
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/RBMX,ALU/A=B"
"ALU/A=B=~1,AMX/RAMX ,RAMX/Q,BMX/RBMX,RBMX/D"
"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/A=B"
"RAMX/Q,AMX/RAMX,BMX/LB,ALU/AR=B"
"RAMX/Q,AMX/RAMX ,BMX/LC,ALU/A=B"

"ALU/A=B=1,AMX/RAMX,RAMX/Q,BMX/MASK"

"RAMX/Q,AMX/RAMX,0XT,DT/Q@1,ALU/A"

"ALU/A+B,AMX/RAMX,0XT,DT/@1,BMX/RBMX,RBMX/D,RAMX/Q"
"ALU/A+B+1,AMX/RAMX,0XT,DT/@1,BMX/RBMX,RAMX/Q,RBMX/D"
"ALU/A+B,AMX/RAMX,0XT,DT/@1,RAMX/Q,BMX/KMX,KMX/02"
"ALU/A=B,RAMX/Q,AMX/RAMX ,0XT,DT/@1,BMX/RBMX"
"ALU/A=B,AMX/RAMX,0XT,DT/81,RAMX/Q,BMX/KMX,KNX/82"
KMX/@2"
"ALU/ANDNOT,AMX/RAMX,0XT,DT/R1,RAMX/Q,BMX/KMX,
KMX/@2"
"ALU/OR,AMX/RAMX,0XT,DT/@1,RAMX/G,BMX/KMX,
"ALU/OR,AMX/RAMX,0XT,DT/81,RAMX/Q,BMX/RBMX,RBMX/D"
"AMX/RAMX,RAMX/Q,BMX/RBMX,RBMX/D,ALU/AND"
"RAMX/Q,AMX/RAMX,KMX/81,BMX/KMX,ALU/AND"
"RAMX/Q,AMX/RAMX,KMX/@1,BMX/KMX ,ALU/ANDNOT"
"RAMX/Q,AMX/RAMX
,BMX/MASK ,ALU/ANDNOT"

“ALU/ANDNOT,AMX/RAMX,RAMX/Q,BMX/LB,SPO.R/LOAD.LAB,SPO,RAB/81"

"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/OR"
"RAMX/Q,AMX/RAMX,BMX/LC,ALU/OR"

"ALU/ORNOT,AMX/RAMX ,RAMX/Q,BMX/KMX ,KMX/@1"
"ALU/A,AMX/RAMX,SXT,DT/81,RAMX/Q"

"RAMX/Q,AMX/RAMX,SXT,DT/®#1,KMX/@2,BMX/KMX,ALU/A+B"
"RAMX/G,AMX/RAMX ,SXT,DT/@1,BMX/1.B,ALU/A+B"
"RAMX/Q,AMX/RAMX,SXT,DT/@1,BMX/LB,ALU/A+B+L"
"RAMX/Q,AMX/RAMX.SXT,DT/@1,BMX/PC,ALU/A+B"

{LNOD) SOHOVI 3Q0J0HIINW WILSAS

ALU_LA.OR.KI[}
ALU.LA.XOR.LC
ALU.LALID

ALU.GQ.XOR,.D

ALU.Q.XOR.LC

ALU.G.XOR.RC(]

ALU.QL)D
ALU_R(DST)

ALU_R(SC),ANDNGT,
K]

ALU_R(SP1)+K[)
.RLOG

ALULRC(SC)
ALU_RCI)
ALULRLOG

ALULRI]
ALULRI[)=K(]
ALULR({].AND.KI[]

ALULRL) .AND.LC
ALULR() .ANDNOT.K{]
ALULRI[] ,ANDNOT.MASK
ALU_R{).OR.KI[)
ALU_R([]).ORNDT.K[]

€§

ALULR().XOR.K
[}

CACHE.P.DI(]
CACHE().D

CACHE.D(QUAD)

CACHE.D,.,INST,DEP
CACHE.DI[]
CACHELD(1,LKk

CACHE.D{] ,NOCHK
D&Q.D+0Q
D&RC
(] .PC

D&VALALU

D&VA_D+LC
D&VALD+G
DEVALD=K
(]

D&VA_LA

D&VA.LB
D&VALQ

DEVA_Q+LB,PC

D().CACHE

O(}.CACHE,IBCHK
D{)_CACHE,LK
D{).CACHE.NOCHK
D{).CACHE,P
DI).CACHE, wCHK

“ALU/ANDNOT,AMX/RAMX.SXT,RAMX/O,BHX/
KMX,KMX/Q2,DT/OI'
“RAMX/Q,AMX/RAMX,BMX/RBHX,RBMX/D,ALU
/XOR'
'FAMX/Q.AMX/RANX,KMX/Gl,BMX/KHX,ALU/
XOR'
"RAMX/Q,AMX/KAMX ,BMX/LC,ALU/XOR"

'RAMX/Q,AMX/RAMX,SPO.R/LOAD.LC,SPO.R
C/Ol,BHX/LC,ALU/XOR'
"RAHX/Q,AMX/RAMX,RBMX/D,BHX/RBMX
,ALU/GI'

'SPO.AC/LOAD.LAB,SPO.ACNIl/DST.DST'AMX/L
A,ALU/A'
"SPO.AC/LOAD.LAB,SPO.ACN/SC.AMX/LA,K
NX/G!,BMX/KMX,ALU/ANDNOT'
/LA,KHX/BI,BMX/KHX,ALU/AOB.RLOG'
"SPO/LOAD.LC,.SC,BMX/LC,ALU/B"
'SPO.R/LOAD.LC,SPO.RC/GI,BMX/LC,ALU/
B"
"BMX/0,ALU/B,MSC/R
,RLOG"
EAD
"SPU.R/LOAD.LAB,SPO.RAB/BI,AHX/LA,AL
U/A'
"SPO.R/LOAD.LAB,SPO.RAB/GI,ANX/LA,KMX/E2
,BNX/KMX,ALU/A-B'
'SPO.R/LOAD.LAB,SPO.RAB/GI,AMX/LA,KMX/Q?
,BMX/KMX,ALU/AND'
'SPO.R/LOAD.LAB,SPO.RAB/GI,AHX/LA,BMX/LC
,ALU/AND"
'SPO.P/LOAD.LAB,SPO.RAB/OI,AMX/LA,KM
X/O2,BHX/KHX,ALU/ANDNOT'
'SPO.R/LOAD.LAB,SPO.RAB/Gl,AMX/LA,BH
X/MASK,ALU/ANDNUT'
'SPO.R/LOAD.LAB,SPO.RAB/OI,AMX/LA,KH
X/GZ,BMX/KNX,ALU/OR'
'ALU/ORNUT,AMX/LA,BHX/KHX,SPO.F/LOAD
.LAB,SPO.RAB/E!,KNX/OZ'
”SPU.R/LOAD.LAB,SPO.RAB/@I,AMX/LA,KM
X/BZ,BMX/KHX,ALU/XDR'
'SPO.AC/LOAD.LlB,SPO.ACN/SPl.SPi,AMX

"VAK/NOP,MCT/WRITE.P,DT/@1,DK/NOP"
'VAK/NOP,HCT/hRITE.V.RCHK,MSC/D!,DK/

NUP"

'MCT/EXTURITE.P,LUNG,VAK/NOP,DK/NOP'

'VAK/NOP,NCT/HRITE.V.WCHK,DT/INST.DEP,DK

/NOP'

'VAK/NOP,MCT/NRITE.V.HCHK,DT/@i,DK/N

OP"

'VAK/NOP,MCT/LOCKNRITE.V.XCHK,DT/@I,

DK/NOP'

"VAK/NOP,MCT/HRITE.V.NOCHK,DT/OX,DK/

NOP'

'RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX,ALU

'BMX/PC,ALU/B,SHF/ALU,DK/SHF,SPO.R/U

/A¢B,5HF/ALU,DK/SHF,QK/SHF'

RITE.RC,SPD.RC/OI'
"VAK/LOAD,SHF/ALU,DK/SHF"
'RAHX/D,AMX/RAMX,BMX/LC,ALU/A#B,VAK/
LOAD,SHF/ALU,DK/SHF'
"DuD+Q,VAK/LOAD"

'RAMX/D,AMX/RAMX,KMX/OI,BMX/KHX,ALU/
'AHX/LA,ALU/A,VAK/LUAD,SHF/ALU,DK/SH

A-B,VAK/LO!D,SHF/ALU,DK/SHF'

'BMX/LB,ALU/B,VAK/LOAD,SHF/ALU,DK/SH

"RAMX/Q,AMX/RAMX,ALU/A,VAK/LOAD,DK/O

'
'RAMX/Q,AMX/RAMX,BMX/PC.OR.LB,ALU/A+
B,VAK/LOAD;SHF/ALU,DK/SHF'
'VAK/NOP,NCT/READ.V.RCHK,DT/@I,D
K/NOP"
“VAK/NOP,MCT/READ.V.IBCHK,DT/fil,DK/NOP”
'VAK/NOP,MCT/LOCKREAD.V.HCHK,DT/@!,DK/NO

'VAK/NOP,MCT/READ.V.NUCHK,DT/BI,DK/NOP'
"VAK/NOP,MCT/READ,P,DT/a1,DK/NOP"
'VAK/NOP,MCT/READ.V.HCHK,DT/G!,DK/NO

(LNOD) SOHOVIN 3A0J0HIIN WILSAS

ALU_Q,.SXT().ANDNOT
K (]
ALULQ.XOR.KI[]

D.O=D

D.O=K(]
D.0-G
D.0=0=1
D.ACCEL&SYNC
D.ALU

D.ALU(FRAC)
D_ALU.LEFT
D_ALU.LEFT2
D.ALU.LEFT3
D.ALU.RIGHT

D-ALU.KRIGHT2

D_BLANK

D.CACHF ,INST,DEP
., LK (]
D_CACHE
D.CACHE ,WCHK (]
L[]
D.CACHE

D.D(FRAC)
()
DD+K
D.D+K[)+1
D._D+LB

D.D+LC

D_D+LC+PSL.C
DaD+Q

D.D+G+1
D.D=KL]}
D.D-LC
oOCTCOUDOoOOUTO

-D= Q
D -q-1
Q

0 XT0)

D . 0 XTOI+K{]
D . 0

0 XTL)+0+1

~D,OXTL].ANDNOT.K{]
.

<D.O0XT(].0R.Q

<D.OXT(].XOR.Q
D_D.OXTI[).XCR.RC(]
DuD.AND,.K{]

D.D.AND.K[]) LEFT2
D.D.AND.K[1,RIGHT
D_D.AND.LC
D-D.AND.MASK
D.D.AND.G

DD AND,RC(]
D.D.ANDNOT.K[]
D.D.ANDNOT,LC
D-D.ANDNOT.PSWZ
D.D.ANDNOT,.Q

"ALU.O0=Q=1,D.ALU"

"DK/ACCEL ,ACF/SYNC"

"SHF/ALU,DK/SHF"

F
,FL"
"SHF/ALU,DK/SH
"SHF/LEFT,DK/SHF"

"SHF/ALU.DT,DT/LONG,DK/SHF"
*"SHF/LEFT3,DK/SHF"
"SHF/RIGHT,DK/SHF"
"SHF/RIGH12,DK/SHF"
"Duk(.202"

'VAKINDP,MCT/READ.V.IBCHK,DT/INST.DhP,DK/NOP'
'VAK/NOP,MCT/LOCKREAD.V.WCHK:MSC/OI,DK/NOP'
“VAK/NOP,MCT/READ.V.WCHK,MSC/GI,DK/NOP“
'VAKINOP,MCT/RERD.V.RCHK,MSC/@I,DK/NOP'
"RAMX/D,AMX/HAMX,ALU/A,SHF/ALU,DK/SHF.FL'

'
”RAMX/D,AMX/RAMX,KMX/OI,BMX/KMX,ALU/A#B,SHF/ALU,DK/SHF
/ALU,DKISHF'
'RAMX/D,AMX/RAMX,KMX/@I,BMX/KNX,ALU/A¢B+1,SHF
DK/SHF‘
SHF/ALU,
ALU/A#E,
,BMX/LB,
AMX/PAMX
'RAHX/D,
'RAHX/D,AMX/RAMX.BMX/LC,ALU/AOB,SHF/ALU,DK/SHF‘
'RAMX/D,ANX/RAMX,BMX/LC,ALU/AOB#PSL.C,SHF/ALU,DK/SHF'
F'
'RAMX/D,AHX/RAMX,RBMX/O,BMX/RENX,ALU/A#B.SHF/ALU,DK/SH
F/ILU,DK/SHF'
'RAHX/D,AMX/RAMX,RBMX/Q,BMX/RBMX,ALU/A#Bfl,SH
'
LU,DK/SHF
A-B.SHF/A
/KMX,ALU/
HX/B!,BMX
'RAMX/D,AMX/RAMX,K
'RANX/D,AMX/RAMX,BMX/LC,ALU/A-B,SHF/ALU,DK/SHF"
ALU,DK/SHF"

"RAMX/D,AMX/RAMX,RBMX/O,BMX/RBMX,ALU/A-B,SHF/F/ALU,DK/SHF'

/A-B-l.SH
"RAMX/D,AMX/RAMX,RBMX/O,BMX/RBFX,ALU
"RAMX/D,AMX/RAMX.OXT,DT/@l,ALU/A,SHF/ALU,DK/SHF'
X/KHX,ALU/AQB,SHF/ALU,DK/SHF'
KHX/BZ,BH
XT,DT/BI,
"RAMX/D,ANX/PAMX.O
X/Q,D-ALU“

“ALU/A*B,AHX/RAMX.OXT,DT/@I,BMX/RBMX,RBN
,D-ALU'
"RAMX/D,AMX/RAMX.OXT,DT/EI,BMX/PBMX,ALU/A#B+1
X/KMX,ALU/ANDNOT,SHF/ALU,DK/SHF'

"RAMX/D,AMX/RAMX.OXT,DT/Pl,KMX/BZ,BH
U/OR,SHF/ALU,DK/SHF'
"RAMX/D,AMX/FAMX.OXT,DT/OI,RBMX/Q,BMX/RBHX,AL
/O,BNX/RBHX'
'DK/SHF,ALU/XOR,SHF/ALU,AMX/RAMX.OXT,RAMX/D,DT/91,RBMX
RC/OZ,BMX/LC,ALU/XOR,SHF/ALU,DKISHF'

D.LC,SPO.
XT,DT/Ol,SPU.P/LOAAND,SHF/A
”RAMX/D,AMX/RAMX.OHX/@l,BMX
LU,DK/SHF"
/KMX,ALU/

"RAMX/D,AHX/RAMX,K
ALU/AND,SHF/ALU.DT,DT/LONG,DKISHF'
"RANX/D,AHX/RAMX,KMX/@!,BMX/KMX,
X/KMX,ALU/AND,SHF/R!GHT,DKISHF'

"kAMX/D,AMX/RAMX,KMX/fli,BM

”RAMX/D,AMX/RAHX,BMX/LC,ALU/AND,SHF/ALU,DK/SHF' '

U.DK/SHF
"RAMX/D,AMX/RAMX.BMX/FASK.ALU/AND.SHF/AL
F'
"PAMX/D,AMX/RAMX,RBMX/O,BMX/RBMX,ALU/AND,SHF/ALU,DK/SH
LC.ALU/AND,SHF/ALU,DK/SHF'

'RAMX/D,AMX/PAMX,SPO.R/LUAD.LC,SPO.RC/@!,BMX/

ANDNOT,SHF/ALU,DK/SHF'
"RAMX/D,AMX/&AMX,KMX/@!,BHX/KHX,ALU/HF/ALU,DK
/SHF'
"RAMX/D,AMX/RANX,BMX/LC,ALU/ANDNOT,S
X/.4,SHF/ALU'
“DK/SHF,ALU/ANDNOT,AMX/RAHX,RAHX/D,BMX/KMX,KH
U,DK/SHF'
NOT,SHF/AL
MX,ALU/AND
X/Q,BFX/RB
X/RAMX,RBM
'RAMX/D,AH

(LNO9D) SOHOVIN 3GOJ0HIIN WILSAS

D.O+K[]+1
DLO+LC+1

I,SHF/ALU,DK/SHF”
"AMX/RAMX.OXT,DT/LONG,KMX/GI,BMX/KNX,ALU/A*BO
'AMX/RAMX.OXT.DT/LONG,BMX/LC,ALU/A0501,SHF/ALU;DK/SHF'
'
U/A-B,SHF/
“ANX/PAMX.OXT,DT/LONG,RBMX/D,BNX/RBMX,AL/A-B,SHF/AALU,DKISHF
'AMX/RANX.OXT,DT/LONG,KMX/OI,BNX/KMX,ALUU/A-B,SHF/LU,DK/SHF'
"
ALU,DK/SHF
MX/RBMX,AL
"AMX/RAMX.OXT,DT/LONG,RHVX/Q,B

"DK/CLR"

0.0

DoINT,SUM
D.KI(]

D_K[] .RIGHT
D.K{} RIGHT2
D.LA
D_LA(FRAC)
D_LA+D+PSL.C
D.LA=D

D.LA=K[]
D.LA.AND,.KI[]
D_LA,RIGHT
D.LB

D.LB,PC
D.LC

D_LC(FRAC)
D.NOT,D
D_NOT.K{)
D.NOT.MASK

D.NOT.Q

D.NOT.RI(]
D.PACK,FP

"DK/LEFT"

"DK/LEFT2"
"D.D.OR.K[,30]"

"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/OR,SHF/ALU,DK/SHF"
"DK/SHF ,ALU/OR,AMX/RAMX
,RAMX/D ,BMX/KMX,KMX/.1,SHF/ALU"
"DK/SHF ,ALU/OR,AMX/RAMX ,RAMX/D,BMX/KMX ,KMX/.2,SHF/ALU"
"RAMX/D,AMX/RAMX,RRMX/0,BMX/RBMX,ALU/OR,SHF/ALU,DK/SHF"

"RAMX/D,AMX/RAMX,SPO.,R/LOAD.LC,SPO.RC/R1,BMX/LC,ALU/OR,SHF/ALU,DK/SHF"
"ALU/OR,AMX/RAMX,RAMX/D,BMX/LB,5P0.R/LOAD.LAB,SPO.RAB/@1,DK/SHF"
"RAMX/D,AMX/RAMX ,BMX/MASK,ALU/ORNOT,SHF/ALU,DK/SHF"
"DK/RIGHT"
*RBMX/D,BMX/RBMX
,ALU/B, SHF/RIGHT,DK/SHF"

"DK/RIGHT2"
"DK/BYTE.SWAP"

"RAMX/D,AMX/RAMX,SXT,DT/@1,ALU/A,SHF/ALU,DK/SHF"
"RAMX/D,AMX/RAMX.SXT,DT/@1,ALU/A,SHF/RIGHT,DK/SHF"
"RAMX/D,AMX/RAMX
,KMX/@) ,BMX/KMX ,ALU/XOR,SHF/ALU,DK/SHF"
"RAMX/D,AMX/RAMX,BMX/LC,ALU/XOR,SHF/ALU,DK/SHF"
"RAMX/D,AMX/RAMX ,RBMX/0,BMX/RBMX,ALU/XOR,SHF/ALU,DK/SHF"
"DK/DAL.SV"
*DK/DAL,.SC"

"RAMX/D,AMX/RAMX ,KMX/@2,BMX/KMX,ALU/@1,SHF/ALU,DK/SHF"
"RAMX/D,AMX/RAMX,BMX/MASK,ALU/@1,SHF/ALU,DK/SHF"
"RAMX/D,AMX/RAMX,RBMX/0,BMX/RBMX,ALU/81,SHF/ALU,DK/SHF"
"MCT/READ.INT,.SUM,DK/NOP"

"KMX/@1,BMX/KMX,ALU/B,SHF/ALU,DK/SHF"
"KMX/@1,BMX/KMX,ALU/B,SHF/RIGHT,DK/SHF"
"KMX/@1,BMX/KMX,ALU/B,SHF/RIGHT2,DK/SHF"
"AMX/LA,ALU/A,SHF/ALVU,DK/SHF"
"AMX/LA,ALU/A,SHF/ALU,DK/SHF
. FL"
"AMX/LA,RBMX/D,BMX/RBMX,ALU/A+B+PSL.C,SHF/ALU,DK/SHF"

"DK/SHF ,ALU/A=B,AMX/LA,BMX/RBMX,RBMX/D,SHF/ALU"
"AMX/LA,KMX/@1,BMX/KMX,ALU/A=B,SHF/ALU,DK/SHF"
"AMX/LA,KMX/@1,BMX/KMX,ALU/AND,SHF/ALU,DK/SHF"
"AMX/LA,ALU/A,SHF/RIGHT
,DK/SHF"
"BMX/LB,ALU/B,SHF/ALU,DK/SHF"
"BMX/PC,OR.LB,ALU/B,SHF/ALU,DK/SHF"
"BMX/LC,ALU/B,SHF/ALU,DK/SHF"
“BMX/LC,ALU/B,SHF/ALU,DK/SHF.FL"

"RAMX/D,AMX/RAMX ,ALU/NOTA,SHF/ALU,DK/SHF"
"KMX/@1,BMX/KMX,AMX/RAMX ,0XT,DT/LONG,ALU/ORNOT,SHF/ALU,DK/SHF"
"BMX/MASK,AMX/RAMX ,0XT,DT/LONG,ALU/ORNOT,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,ALU/NOTA,SHF/ALU,DK/SHF"
"LA_RA[@1) ,AMX/LA,ALU/NOTA,D.ALU"
"BMX/PACKED.FL,ALU/B,SHF/ALU,DK/SHF"

D-PC
D.PC.LEFT

"BMX/PACKED.FL,ALU/B,SHF/LEFT,DK/SHF"
"BMX/PC,ALU/B,SHF/ALU,DK/SHF"
"BMX/PC,ALU/B,SHF/LEFT,DK/SHF"

D.G

"DK/G"

DPACK,.FP.LEFT

(LNOJ) SOHOVIN 3AOJ0HIIN WILSAS

UCOOUUFUUCOO

~D.ORNOT.MASK
«DRIGHT
D_D.RIGHT(B)
D_D.RIGHT2
DaD.SWAP
D.D.SXTI(]
DD SXTI{}.RIGHT
DD+ XOR.KI(]
D.D.XOR.LC
D.D.XOR.0Q
D.DAL(NORM
D.DAL.SC
D-DIKI]
D_D{IMASK
b.DI)Q

"RAMX/D,AMX/RAMX,SPO.R/LOAD.LC,SPO.RC/@1,BMX/LC,ALU/ANDNOT,SHF/ALU,DK/SHF"

"RAMX/Q,AMX/RAMX,ALU/A,SHF/ALU,DK/SHF
.FL"
“RAMX/Q,AMX/RAMX ,RBMX/D,BMX/RBMX,ALU/A+B,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/A+B,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,BMX/LB,ALU/A+B,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX ,BMX/PC,ALU/A+B,SHF/ALU,DK/SHF"
YRAMX/Q,AMX/RAMX ,RBMX/D,BMX/RBMX,ALU/A~B,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/KBMX,ALU/A=B~1,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX
,KMX/R]1 ,BMX/KMX ,ALU/A~B,SHF/ALU,DK/SHF"

"RAMX/Q,AMX/RAMX,KMX/81,BMX/KMX ,ALU/A=B~1,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,BMX/0,MSC/READ ,RLOG,ALU/A=B,SHF/ALU,DK/SHF"

DaQ.0XTI()

“RAMX/Q,AMX/RAMX.0XT,DT/81,ALU/A,SHF/ALU,DK/SHF"

D.Q.AND.K[]

"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/AND,SHF/ALU,DK/SHF"

D.0,.AND.LC

"RAMX/Q,AMX/RAMX,BMX/LC,ALU/AND,SHF/ALU,DK/SHF"

D.Q.AND.MASK
D.Q.ANDNOT.D

"RAMX/Q,AMX/RAMX,BMX/MASK,ALU/AND,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,SPO,.R/LOAD,LC,SPO.RC/®1,BMX/LC,ALU/AND,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/RBMX,ALU/ANDNOT,SHF/ALU,DK/SHF"

D.LQ,ANDNOT.KI[]

"RAMX/Q,AMX/RAMX
,KMX/@1,BMX/KMX ,ALU/ANDNOT, SHF/ALU,DK/SHF"

DoQ.ANDNOT,.MASK

DaQ.RIGHT

"RAMX/Q,AMX/RAMX ,BMX/MASK,ALU/ANDNOT,SHF/ALU,DK/SHF"
"DK/SHF ,ALU/ANDNOT,AMX/RAMX ,RAMX/G,BMX/KMX,KMX/.1,SHF/ALU"
"DK/SHF,ALU/ANDNOT,AMX/RAMX ,KAMX/Q,BMX/KMX ,KMX/ 4B ,SHF/ALU"
"DK/SHF ,ALU/ANDNOT ,AMX/RAMX ,RAMX/Q,BMX/KMX ,KMX/ .4 ,5HF/ALU"
"RAMX/Q,AMX/RAMX,ALU/A,SHF/LEFT,DK/SHF"
"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/OR,SHF/ALU,DK/SHF"
"DK/SHF ,ALU/OR,AMX/RAMX,RAMX/Q,BMX/KMX,KMX/.1,SHF/ALU"
"RAMX/Q,AMX/RAMX,SPO,R/LOAD,.LC,SPO.RC/@1,BMX/LC,ALU/OR,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,BMX/MASK,ALU/ORNOT,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,ALU/A,SHF/RIGHT,DK/SHF"

D.Q,RIGHT2

"RAMX/Q,AMX/RAMX,ALU/A,SHF/RIGHT2,DK/SHF"

D.G.SXTI)

"RAMX/Q,AMX/RAMX SXT,DT/@1,ALU/A,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX,SPO,R/LOAD.LC,SPO.RC/@1,BMX/LC,ALU/XOR,SHF/ALU,DK/SHF"
"RAMX/Q,AMX/RAMX ,RBMX/D,BMX/RBMX ,ALU/81,SHF/ALU,DK/SHF"
"ALU/®1,SHF/ALU,DK/SHF ,BMX/KMX,KMX/@®2,AMX/RAMX,RAMX/Q"
"RAMX/Q,AMX/RAMX,BMX/MASK,ALU/@1,SHF/ALU,DK/SHF"
"SPO,AC/LOAD,LAB,SPO,ACN/PRN+1,AMX/LA,ALU/A,SHF/ALU,DK/SHF"
"SPO,AC/LOAD,LAB,SPO,ACN/SC,AMX/LA,ALU/A,SHF/ALU,DK/SHF"
"SPO,AC/LOAD.LAB,SPO,ACN/SP1+1,AMX/LA,ALU/A,SHF/ALU,DK/SHF"
"SPO/LOAD.LC.SC,BMX/LC,RLU/B,SHF/ALU,DK/SHF"
"SPO.R/LOAD.LC,SP0O,RC/81,BMX/LC,ALU/B,SHF/ALU,DK/SHF"
"BMX/0,MSC/READ,.RLOG,ALU/B,SHF/ALU,DK/SHF"
"BMX/0,MSC/READ.RLOG,ALU/B,SHF/RIGHT,DK/SHF"
"SPO.R/LOAD.LAB,SPO,RAB/@1,AMX/LA,ALU/A,SHF/ALU,DK/SHF"

D.G.AND,RC(]

D.Q.,ANDNOT,.PSWC
DoQ.ANDNOT,PSWN

D.Q.ANDNOT,PSWZ
D.Q.LEFT

D.Q,OR.K([]
D.QG.OR.PSWC

D.QG.0R.RCI[]
DoQ.ORNOT,MASK

D.Q.XO0R,RC[]
b.GllD

D.GUIKIL]
D_G[IMASK
D.R(PRN+1)

D.R(SC)

D_R(SP1+1)
D-RC(SC)

D.RCI]
D-RLOG
D.RLOG.RIGHT

D-RI[)

DoR[}.ORNOT.K[]

"SPO,R/LOAD.LAB,SPO.RAB/@1,AMX/LA,ALU/A,SHF/ALU,DK/SHF
,FL"
*“SPO R/LOAD.LAB,SPO,RAB/@1,AMX/LA,KMX/@2,BMX/KMX,ALU/AND,SHF/ALU,DK/SHF"
"SPO.R/LOAD.LAB,SPO.RAB/@1,AMX/LA,KMX/@2,BMX/KMX,ALU/OR,SHF/ALU,DK/SHF"
"LAB.R[@1),AMX/LA,BMX/KMX,KMX/82,ALU/ORNOT,D.ALU"

DuRIL] (FRAC)
D.R{],AND.K
(]
D.R{).0R.K[]

EALULD(EXP)

"RAMX/D,AMX/RAMX,EBPMX/AMX

EALU_FE

"EBMX/FE,EALU/B"

EALU_KI(]
EALULR(] (EXP)

“KMX/®1,EBMX/KMX,EALU/B"

EXP,EALU/B"

"SPO.R/LOAD,LAB,SPO,RAB/@1,AMX/LA,EBMX/AMX
. EXP,EALU/B"

(LNOJ) SOHOVI 3A0J0HIIN WILSAS

D.Q(FRAC)

"EALU/A"

EALU_SC+FE

"EBMX/FE,EALU/A+B"

EALULSC+K (]
EALU.SC-FE
EALU.SC=K[]

"KMX/@1,EBMX/KMX ,EALU/A+B"
"EBMX/FE,EALU/A-B"
"KMX/81,EBMX/KKX ,EALU/A~B"

EALU_SC,ANDNOT.K
()

"KMX/@1,EBMX/KMX ,EALU/ANDNOT®

EALULSTATE

"EALU/A,MSC/LOAD.STATE"

FELSC.KI[]

"KMX/@1,EBMX/KMX,EALU/B,FEK/LCAD,SMX/EALU,SCK/LOAD"

FE.O(A)
FE.D(EXP)
FELEALU

"AMX/RAMX,0XT,DT/LONG,EBMX/AMX ,EXP,EALU/B,FEK/LOAD"
"RAMX/D,AMX/RAMX
,EBMX/AMX .EXP,EALU/B,FEK/LCAD"
"FEK/LOAD"

FE.KI[]

"KMX/@1,EBMX/KMX,EALU/B,FEK/LCAD"

FE.LA(EXP)
FE.NABS(SC~FE)
FE_NABS (SC=LA(EXP))
FE.Q(EXP)
FEL.R[] (EXP)
FE.SC

"AMX/LA,EBMX/AMX
. EXP,EALU/B,FEK/LOAD"
"EALU/NABS,A=B,EBMX/FE,FEK/LOAD"
"AMX/LA,EBMX/AMX ,EXP,EALU/NABS . A=B,FEK/LOAD"

"RAMX/Q,AMX/RAMX
,EBMX/AMX ,EXP,EALU/B,FEK/LOAD"
*"SPO,R/LOAD.LAB,SPO.RAB/@1,AMX/LA,EBMX/AMX.EXP,EALU/B,FEK/LOAD"
"EALU/A,FEK/LOAD"

FE_8C+1
FE_SC+FE

"EALU/A+1,FEX/LOAD"
"EBMX/FE,EALU/A+B,FEK/LOAD"

FELSC+K (]
FE_SC+LA(EXP)
FE.SC=FE
FE.SC=K(]
FE-SC=LA(EXP)
FE.SC=SHF,VAL
FE.SC.ANDNOT.FE
FE.SC.ANDNOT.K[]
FE.SC,OR,.K[]
FE.SHF,.VAL

"KMX/@1,EBMX/KMX,EALU/A+B,FEK/LOAD"
"AMX/LA,EBMX/AMX.EXP,EALU/A+B,FEK/LOAD"
"EBMX/FE,EALU/A=B,FEK/LOAD"
"KMX/@1,EBMX/KMX ,EALU/A=B,FEK/LOAD"
"AMX/LA,EBMX/AMX,EXP,EALU/A=B,FEK/LOAD"
"EBMX/SHF
. VAL,EALU/A=B,FEK/LOAD"
"EBMX/FE,EALU/ANDNOT,FEK/LOAD"
"KMX/@1,EBMX/KMX ,EALU/ANDNOT ,FEK/LOAD"
"EALU/OR,EBMX/KMX, KMX/@1,FEK/LOAD"
"EBMX/SHF
VAL ,EALU/B,FEK/LCAD"

FE.STATE

"MSC/LOAD.STATE,EALU/A,FEK/LOAD"

ID(SC).D
Io{l.D

"CID/WRITE,.SC"
"CID/WRITE.KMX,ID.ADDR/@Y"

IDD&ENO,SYNC

"CID/WRITE.KMX,ADS/IBA,KMX/S5P1,CON"

ID.D.SYNC

“CID/WRITE.KMX,ADS/IBA,KMX/SP1,CON,ACF/SYNC"

"KMX/01"

LAB-R(DST)
LAB.R(PRN)
LAB.R(PRN+1)
LAB_R(SC)
LAB.R(SP1)
LABLR(SP1+1)
a0
UABLR1&RC()
LAB_RI&RC(1.0+LC+1
LAB_R1&RC(].0=D
LAB_R1&RC(1_ALU

"SPO,AC/LOAD,LAB,SPO,ACN11/DST,DST"
"SPO.AC/LOAD.LAB,SPO.ACN/PRN"
"SPO.AC/LOAD,LAB,SPO.ACN/PRN+1"
"SPO.AC/LOAD.LAB,SPO,ACN/SC"
"SPO,AC/LOAD.LAB,SPO,ACN/SP1.S5P1"
"SPO.AC/LOAD.LAB,SPO.ACN/SP1+1"
“ALU.O(A) ,LAB_R1&RC{@1]_ALU"

“ALU/A+B+1,AMX/RAMX,0XT,DT/LONG,BMX/LC,SPO.R/LOAD.LAB1
., WRITE,RC,SPO.RC/@1,SHF/ALU"
"SPU.R/LOAD.,LABL .WRITE,RC,SPO.RC/@1,ALU/A=B,AMX/RAMX,0XT,DT/LONG,BMX/RBMX,RBMX/D,SHF/ALU"
"SPO.R/LOAD,LAB]1 ,WRITE.RC,SPO.RC/@},SHF/ALU"

(LNOJ) SOHOVIN 3A0J0HIIN WNILSAS

EALU.SC

LALR(DST)&LB.R(SRC)
LA_R(SP2)6LB.R(SP1)

LALRAL]

"SPU,R/LOAD,LAB1.WRITE,RC,SPO.RC/@1,SHF/RIGHT2"

"ALU.D+LC,LAB.R1&RC[@1).ALU"
"ALU.D,OXT{@2)+K(@3]) ,LAB.RI&RC[@1].ALU"
"ALU.Q-K[®2]),LAB.R1&RC[@1].ALU"
"SPO,R/LOAD.LAB,SPO.RAB/@1"

"SPO,AC/LOAD,LAB,SPO.ACN11/DST.SRC"
"SPO.AC/LOAD.LAB,SPO.ACN/SP2.5P1"
"SPO,AC/LDAD,LA,SPO.RAB/@1"

LCoRC(SC)
LCRC
(]
)
. LEFT
LC_RC[I&R1_(LA+LB
LC.RC[}I&R1_(LA+LB+PSL.C).LEFT
LC.RC[J&R1_(LA+LB.RLOG).LEFT
)
LEFT
LC.RCI1&R1_(LA=-LB
LC-RC[]&R1.(LA=LB,RLOG).LEFT
LC.RCLI&R1_ALU
LC.RCLJ&R1.D
LC_RCLI&R1I_LA+KI(]
LC_RCIJ&RILA~KI[]
LCoRC(J&R1.LB
LC.RC[J&R1.0Q

*"SPQ/LOAD,LC,SC"

N&ZLALU

"CCK/NZ_ALU,VC.VC"
"CCK/NZ_ALU.,vC.O"
o Z.TST.VC.VC"
"CCK/NoAMX
"VAK/LOAD,PCK/PC.VA"

N&Z_ALU.V&CLO
NoAMX ,Z.TST

PC&VA_ALU
PC&VALD
PCEVALD+K
(]

PC&VA_D=K[]
PC&VALD=PC
PC&VA_D,OXTI]

PC&VALD.OXT[]+PC
PC&VA_D.SXT[]+PC

PC&VALKI(]
PC&VAL.PC
PC&VALQ
PC&VA_Q+PC

PC&VALQ=D

PC&VA_Q~K[]
PC&VALQ.SXTL])+PC
PC&VA_RC(]
PC&VALR[).ANDNOT.K(]
PC.PC+1
PC.PC+2

PC.PCt+4

"SPC,R/LOAD.LC,SPO.RC/@1"

"AMX/LA,BMX/LB,ALU/A+B,SHF/LEFT,SPO.R/LOAD.LC.WRITE,RAB1,SPO,RC/081"
“AMX/LA,BMX/LB,ALU/A+B+PSL.C,SHF/LEFT,SPO,R/LOAD.LC.WRITE,RAB1,SPO,RC/01"
"AMX/LA,BMX/LB,ALU/A+B
. RLOG,SHF/LEFT,SPO.R/LOAD.LC.WRITE.RAB1,SPO.RC/01"
"AMX/LA,BMX/LB,ALU/A=B,SHF/LEFT,SPO.R/LOARD.LC.WRITE.RAB1,SPO,RC/81"
"AMX/LA,BMX/LB,ALU/A~B,RLOG,SHF/LEFT,SPO.R/LOAD.LC.WRITE.RAB1,SPO.RC/81"
"SPO.R/LOAD.LC.WRITE,RAB1,5P0O.,RC/81,SHF/ALU"

"ALU.D,LCoRC{@81]J&RILALU"

"SPO,R/LOAD.LC.WRITE.RAB1,SPO.RC/®1,SHF/ALU,ALU/A+B,AMX/LA,BMX/KMX
KMX/82"

"ALU.LA=K[@2],LC.RC{®81]J&R1LALU"
"ALU_LB,LC.RC[(O1]&R1_ALU"

"SPO,R/LOAD.LC.WRITE,RAB1,SPCO.RC/@1,SHF/ALU,ALU/A,AMX/RAMX,RAMX/Q"

"RAMX/D,AMX/RAMX ,ALU/A,VAK/LOAD,PCK/PC_VA"

"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/A+B,VAK/LOAD,PCK/PC.VA"
,ALU/A=B, VAK/LOAD,PCK/PCLVA"
"RAMX/D,AMX/RAMX,KMX/@1,BMX/KMX
"RAMX/D,AMX/RAMX,BMX/PC,ALU/A=B,VAK/LOAD,PCK/PC.VA"
"RAMX/D,AMX/RAMX,0XT,DT/@1,ALU/A,VAK/LOAD,PCK/PC.VA"

"RAMX/D,AMX/RAMX,0XT,DT/@%,8MX/PC,ALU/A+B,VAK/LOAD,PCK/PC.VA"
"RAMX/D,AMX/RAMX.SXT,DT/@1,BMX/PC,ALU/A+8,VAK/LOAD,PCK/PC.VA"
"KMX/81,BMX/KMX,ALU/B,VAK/LOAD,PCK/PC_VA"
"BMX/PC,ALU/B,VAK/LOAD,PCK/PC.VA"

"RAMX/Q,AMX/RAMX ,ALU/A,VAK/LOAD,PCK/PC_VA"
"RAMX/Q,AMX/RAMX,BMX/PC,ALU/A+B,VAK/LOAD,PCK/PC_VA"
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/RBMX,ALU/A~B,VAK/LOAD,PCK/PC.VA"
"RAMX/Q,AMX/RAMX,KMX/81,BMX/KMX,ALU/A=B,
VAK/LOAD ,PCK/PC.VA"

"RAMX/Q,AMX/RAMX.SXT,DT/@1,BMX/PC,ALU/A+B,VAK/LOAD,PCK/PC_VA"
"SPO.R/LOAD.LC,SPO.RC/@1,BMX/LC,ALU/B,VAK/LOAD,PCK/PC_VA"

VAK/LOAD,PCK/PCLVA"
"SPO,R/LOARD.LAB,SPO.RAB/®1,AMX/LA,KMX/@82,BMX/KMX,ALU/ANDNOT,
"PCK/PC+1"
"PCK/PC+2"
"PCK/PC+4"
"PCK/PC+N"

PC.PC+N
PC_Q+FPC

"ALU/A4B,VAK/LOAD,PCK/PC_VA,BMX/PC,AMX/RAMX,RAMX/Q"

PC.VA

"PCK/PC_VA"

(LNOD) SOHOVW 3A0J0HIIN INILSAS

LAB.RI&RCL]I_ALU.RIGKT2
LAB_RI1&RCI[1I_D+LC
LABLRIGRC[I.D.OXTII+KI[]
LAB_R1&RC[1.0Q~KI[]
LABLRI[]

PSLKCO>_AMXO

Q&VA_ALU

Q&VALD

Q&VALD+LC

G&VA_LA
Q&VA_Q+LB,PC
Q0. (Q+LB)D.RIGHT2

QD (Q+LC)ID.RIGHT2
0D (Q=LBID.RIGHT2
GD=(Q@=LCID.RIGHT2
QD.QD.RIGHT2

0.0
Q.O0+LC+1
QO0+MASK+1
Qa0+PC.RLOG

G.0-D

Qal=K[1}
Q.0=LC
G.0=Q

6§

Q_ACCEL&SYNC

QLALU
QLALU(FRAC)
Q-ALU.LEFT

Q.ALU.LEFT2
QLALU,LEFT3
QALU.RIGHT
QoALU.RIGHT2

Q.D
QLD(FRAC)(B)

Q.D+KI[]

QuD+K[]+1

Q.D+K[].LEFT
Q.D+LC

Q.D=K[])
G.D~LC
0.D=0

Q.D.0XTL)

QLD,OXT[J}+K([)
LEFT
0.D.0XT().OR,PACK,.FP
Q_D.AND.KI[]

Q.D.AND,K[].RIGHT
Q.D,AND
K[} ,RIGHT2

Q.D.AND.RCI])

G.D.,ANDNOT.RC(]
Q.D0.LEFT3

Q.D.,OR.KI[]

"PCK/PC_IBA"
"CCK/C_AMXO"
"VAK/LOAD,SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX,ALU/A,VAK/LOAD,SHF/ALU,QK/SHF"

"RAMX/D,AMX/RAMX,BMX/LC,ALU/A+B,VAK/LOAD,SHF/ALU,QK/SHF"

"AMX/LA,ALU/A,VAK/LOAD,SHF/ALU,QK/SHF"
“RAHX/O,AMX/RAHX,BMX/PC.OR.LB,ALU/A+B,VAK/LOAD,SHF/ALU,OK/SHF"
"ALU_G+LB,QuALU.RIGHT2,D_D.RIGHT2"
"ALU~Q+LC,Q.ALU,RIGHT2,D.D.RIGHT2"
"ALU.Q=LB,Q.ALU.RIGHT2,D.D.,RIGHT2"

"ALU.G=LC,Q_ALU,RIGHT2,D.D.RIGHT2"
"ALU.Q,Q.ALU,RIGHT2,D.D,RIGHT2"

"GK/CLR"
"ALU/A+B+1,AMX/RAMX,0XT,DT/LONG,SHF/ALU,QK
,BMX/LC"
/SHF

"AMX/RAMX,0XT,DT/LONG,BMX/MASK,ALU/A+R+1,SHF/ALU,QK/SHF"

"AMX/RAMX,0XT,DT/LONG,BMX/PC,ALU/A+B. RLOG,SHF/ALU,QK/SHF"

"AMX/RAMX,0XT,DT/LONG,RBMX/D,BMX/RBMX,ALU/A=B,SHF/ALU,QK/SHF"

"AMX/RAMX,0XT,DT/LONG,KMX/A1,BMX/KMX ,ALU/A=B,SHF/ALU,QK/SHF"
"RMX/RAMX.OXT,DT/LONG,BMX/LC,ALU/A~B,SHF/ALU,QK/SHF"
'AMX/RAMX.OXT,DTILONG.RBMX/Q,BHX/RBMX,ALU/A-B,SHF/ALU,QK/SHF“
"QK/ACCEL,ACF/SYNC"

“SHF/ALU,GK/SHF"
"SHF/ALU,QK/SHF
,FL"
"SHF/LEFT,QK/SHF"
"SHF/ALU.DT,DT/LONG,QK/SHF"
"QK/SHF ,SHF/LEFT3"
"SHF/RIGHT,QK/SHF"
"SHF/RIGHTZ2,0K/SHF"
"QK/D"

"RBMX/D,BMX/RBMX,ALU/B,SHF/ALU,QK/SHF
,FL"
"RAMX/D
,KMX/@1 ,BMX/KMX,ALU/AR+B,SHF/
,AMX/RA
ALU,QK/SHF"
MX

"RAMX/
,KMX/@1
D,AMX/
,BMX/KMX ,ALU/A+B+1,SHF/ALU,
RAMX
QK/SHF"

"RAMX/D,AMX/RAMX,KMX/R1,
,ALU/A+B, SHF/LEFT,UK/SHF"
BMX/KMX

"RAMX/D,AMX/RAMX ,BMX/LC,ALU/A+B,SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX ,ALU/A=B,SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX,BMX/LC,ALU/A=R,SHF/ALU,QK/SHF"

"RAMX/D,AMX/RAMX ,RBMX/Q,BMX/RBMX ,ALU/A=B,SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX,0XT,DT/@1,ALU/A,SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX.0XT,DT/81,KMX/@2,BMX/KMX,ALU/A+B, SHF/LEFT,QK/SHF"

"RAMX/D,AMX/RAMX,.0XT,DT/@1, BMX/PACKED FL,ALU/OR,QK/SHF"
"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX ,ALU/AND, SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX,KMX/BI,BMX/KNX,ALU/AND,SHF/RIGHT;OK/SHF'
"RAMX/D,AMX/RAMX,KMX/@1,BMX/KMX,ALU/AND,SHF/RIGHT2,QK/SHF"

"RAMX/D,AMX/RAMX,SPO,R/LOAD,LC,SPO.RC/81,BMX/LC, ALU/AND,SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX,SPO.R/LOAD,LC,SP0O.RC/®1,BMX/LC, ALU/ANDNOT SHF/ALU,QK/SHF"
"RAMX/D,AMX/RAMX ,ALU/A, SHF/LEFT3 OK/SHF"

"RAMX/D,AMX/RAMX, KMX/@I BMX/KMX,ALU/OR,SHF/ALU,QK/SHF"

(LNOJ) SOHOVIN 3A0J0HIIN WILSAS

PC.VIBA

Q0LIB.DATA

Q-ID(SC)
Q.IDE)

Q-K(1]
Q_K{)+1
Q.K(},CTX
QK[ RIGHT
Q.K[]1.RIGKHT2
Q.LA

Q.LA+K[]
Q.LA+G

Q.LA=KI(]
Q.LALAND.K[)

GLA,ANDNUT,.RCI[]
Q-LB

QuNOT.Q
Q_NOT,.R{]
Q.PACK.FP
G.PC

0.0 (FRAC)

(B)
0.Q(FRAC)
QaQ+D

(]
Q-Q+K
QuQ+K[)+1
Q.Q+LC
Q.QePC
Q-Q0=0D

Qu@=D=1
¢.0=K1{)
<G=K{])=1
Q
«0=LC
Q =LC=1
[}

COOODLOPDO [>l]

Q.LC

Q «MASK=1

-Q JOXTLI=KI(]

U]
. LEFT
Q LOXT

Q «O0XT{).0OR.D
Q «AND,KI[]

<Q Q AND K] RIGHT2

.
K] RIGHT
«Q.AND
G.0.AND,.R[]
QeG.AND.RCI)
Q.Q.ANDNDT.D
K]
Q.G ANDNOT

C/B!,B”X/LC.ALU/OR,SHF/ALU,QKISHF'
"RAMX/D,AHX/PANX,SPO.R/LOAD.LC,SPO.RSHF“
"RANX/D,AMX/RAMX,ALU/A,SHF/RIGHT,OK/
"RAMX/D,AMX/RAMX,ALU/A,SHF/RIGHTZ,QK/SHF'

"RAMX/D,AHX/RAMX.SXT.DT/@l,ALU/A,SHF/ALU,QK/SHF”

"QK/SHF,ALU/XOR,AMX/RAMX,RAMX/D,BMX/RBMX,RBMX/Q,SHF/ALU'
"QK/DEC.CON"

»"1BC/BRDEST,QK/ID,MCT/ALLOW,IB.RFAD"
"OK/ID,MCT/ALLOW.IB,READ"
“CID/READ.SC,QK/ID"

"CID/READ.KMX,1D,ADDR/@1,0QK/ID"

WKMX/@1,BMX/KMX,ALU/B,SHF/ALU,GK/SHF"

"AMX/RAMX.OXT,DT/LONG,KMX/EI,BHX/KMX,ALU/A#B#!,SHF/ALU,GK/SHF'

'KNX/@l,BHX/KMX,ALU/B,SHF/ALU.DT,DT/INST.DEP,OK/SHF'
“KMX/O!.BMX/KMX,ALU/B,SHF/RIGHT,QK/SHF"
"KMX/OI,BMX/KHX,ALU/B,SHF/RIGHTZ,QK/SHF"
"AMX/LA,ALU/R,SHF/ALU,QK/SHF"

"AMX/LA,KMX/@I,BMX/KMX,ALU/A*B,SHF/ALU,OK/SHF"
"AMXILA,RBMX/O,BMX/RBMX,ALU/A#B,SHF/ALU,QK/SHF'
“AMX/LA,KMX/QI,BMX/KMX,ALU/A-B,SHF/ALU,OK/SHF'

"AMX/LA,KMX/@I,BHX/KMX,ALU/AND,SHF/ALU,QK/SHF'DNOT,SHF/ALU,OK/SHF'

'AMX/LA,SPO.R/LOAD.LC,SPO.RC/QI,BMX/LC,ALU/AN
"BMX/LB,ALU/B,SHF/ALU,QK/SHF"
"BMX/LC,ALU/B,SHF/ALU,QK/SHF"

'RAMX/Q,AMX/RAMX,ALU/NOTA,SHF/ALU,QK/SHF'
"LA_RA[@1],AMX/LA,ALU/NOTA,Q.ALU"
"BMX/PACKED.FL,ALU/B,SHF/ALU,Q0K/SHF"
"BMX/PC,ALU/B,SHF/ALU,QK/SHF"

"RAMX/Q,ANX/RAMX,ALU/A,SHF/ALU,OK/SHF.FL“
"RBMX/Q,BMX/RBMX,ALU/B,SHF/ALU,OK/SHF.FL"

K/SHF'
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/RBMX,ALU/A+B,SHF/ALU,Q/SHF'
"RAMX/O,AHX/RAMX,KNX/GI,BMX/KMX,RLU/A#B,SHF/ALU,QK

'RAHX/Q,AMX/RAMX,KMX/@I,BMX/KMX,ALU/A+B#1,SHF/ALU,QK/SHF“

'RAMX/O,AMX/RAMX,BMX/LC,ALU/A#B,SHF/ALU,QK/SHF"
'RAMX/Q,AMX/RAMX,BMX/PC,ALU/A¢B,SHF/ALU,QK/SHF“

'RAMX/Q,AHX/RAMX,RBMX/D,BMX/RBFX,ALU/A-B,SHF/ALU,QK/SHF'
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/RBMX,ALU/A-B-I,SHF/ALU,QKISHF“
“RAMX/Q,AHX/RAHX,KMX/BI,BNX/KMX,ALU/A-B,SHF/ALU,QK/SHF'

I,SHF/ALU,GK/SHF'
"RAMX/Q,AHX/RAMX,KMX/O!,BMX/KMX,ALU/A-B-QK/SHF'
"RAMX/Q,AMX/RAHX,BMX/LC,ALU/A'B,SHF/ALU,
”RANX/Q,AMX/RANX.BMX/LC,ALU/A-B-],SHF/ALU,OK/SHF"

'RAMX/O,AMX/PAMX,BNX/MASK,ALU/A-B-l,SHF/ALU,QK/SHF‘SHF/ALU,QK/SHF'

X,ALU/A-B,
"RANX/O,AMX/RAHX.OXT,DT/GI,KMX/@Z,BMX/KHT,QK/SHF'
'RAMX/Q,AMX/RAMX.OXT,DT/@I,ALU/A,SHF/LEF
'RAMX/O,AMX/RAHX.OXT,DT/OI,RBMX/D,BMX/RBMX.ALU/DR,SHF/ALU,OK/SHF'
"RAMX/O,AMX/RAMX,KMX/GI,BMX/KPX,ALU/AND,SHF/ALU,QK/SHF'

"RANX/O,AMX/RAMX,KMX/Q!,BNX/KMX,ALU/AND,SHF/RIGHTZ,OK/SHF“
"RAMX/Q,ANX/RAMX,KMX/?!,BMX/KMX,ALU/AND,SHF/RIGHT,QKISHF'
ALU/AND,SHF/ALU,GK/SHF’

'RAMX/Q,AMX/RAHX,SPO.R/LOAD.LAB,SPO.RAB/@I,BHX/LB, U/AND,SHF/ALU,QK/SHF'
"RAMX/Q,AMX/RAMX,SPD.R/LOAD.LC,SPO.RC/R!,BMX/LC,AL
SHF/ALU,QK/SHF”
"RAMX/Q,AMX/RAMX,RBMX/D,BMX/RBNX,ALU/ANDNOT,
'RAMX/G,AHX/RAMX,KMX/@I,BMX/RMX,ALU/ANDNOT,SHF/ALU,QK/SHF'

(LNOD) SOHOVIN 3A0J0HIIW WILSAS

Q-D,0R.RCI[]
G.D,RIGHT
9.D.RIGHTZ
G.D,SXT{]
Q-D.X0R,Q
Q.DEC,.CON
Q.IB.BDEST

Q.Q.LEFT2

"GK/LEFT2"

Q.Q.0R,K{]

"RAMX/Q,A
,KMX/R1 ,BMX/KMX
MX/RAMX
,ALU/OR,SHF/ALU,QK/SHF"

Q.G ,ORNOT ,MASK

Q.Q,RIGHT

"RAMX/G,AMX/RAMX,BMX/MASK,ALU/ORNOT,SHF/ALU,QK/SHF"
"GK/RIGHT"

0_0.,RIGHT2

"QK/RIGHT2"

Q0aQ.S8XT(]

"RAMX/Q,AMX/RAMX .5XT,DT/@1,ALU/A,SHF/ALU,QK/SHF"

QLB

"RAMX/Q,AMX/RAMX,KMX/R1
,BMX/KMX ,ALU/XOR, SHF/ALU,UK/SHF"
"SPO.AC/LOAD,LAB,SPO,ACN/PRN,AMX/LA,RRMX/Q,BMX/REMX,ALU/ANDNOT,SHF/ALU,QK/SHF"
“SPO.AC/LOAD,LAB,SPO,ACN/PRN+1,AMX/LA,ALU/A,SHF/ALU,GK/SHF"
"SPO,AC/LOAD.LAB,SPO.ACN/PRN+1,AMX/LA,RBMX/Q,BMX/RBMX ,ALU/AND,SHF/ALU,QK/SHF"
"ALU/A,SHF/ALU,AMX/LA,SPO.AC/LOAD,LAB,SPO.ACN/SC,uK/SHF"
"SPO.AC/LOAD,LAB,SPO.ACN11/SRC,OR.1,AMX/LA,KMX/@1 ,BMX/KMX,ALU/AND,SHF/ALU,QK/SHF"
"ALU/B,SHF/ALU,BMX/LC,SPO/LOAD.LC.SC,QK/SHF"

X0R.KI[]

G_R{PRN),ANDNOT.Q

Q_R(PRN+1)
Q.R(PRN+1).,AND,.Q
Q_R(SC)

QLR(SRC!1).AND.K()

QRC(SC)

"RAMX/0Q,AMX/RAMX,SPO.R/LOAD.LC,SPO.RC/R@1,BMX/LC,ALU/ANDNOT,SHF/ALU,QK/SHF"

"QK/LEFT"

QuRC]

"SPO,R/LUAD.LC,5P0.RC/R1,BMX/LC,ALU/B,SHF/ALU,QK/SHF"

QLRC[) (FRAC)

"SPO.R/LOAD.LC,SPO.RC/@1,BMX/LC,ALU/B,SHF/ALU,QK/SHF
.FL"

QuR ()
QuR
(] (FRAC)
QR[] .AND,K[)

"SPO.R/LOAD,LAB,SPO,RAB/@1,AMX/LA,KMX/82,BMX/KMX,ALU/AND,SHF/ALU,QK/SHF"

QuRIJ.AND.KI[) RIGHT
QuR(],ANDNOT,.K[]
Q.R[).,OR.KI[]

"SPO.R/LOAD.LAB,SPO,RAB/@1,AMX/LA,ALU/AND,BMX/KMX,KMX/82,SHF/RIGHT
,QK/SHF"
“SPO,R/LOAD.LAB,SPO.RAR/@1,AMX/LA,KMX/@2,8MX/KMX,ALU/ANDNOT
,SHF/ALU,QK/SHF"
"ALU/OR,AMX/LA,SPO.R/LOAD,LAB,SPO.RAB/@1,BMX/KMX,KMX/@2,QK/SHF"

"SPO.R/LOAD.LAB,SPO.RAB/@1,AMX/LA,ALU/A,SHF/ALU,QK/SHF"

"SPO.R/LUAD.LAB,SPU.,RAB/®1,AMX/LA,ALU/A,SHF/ALU,UK/SHF
,FL"

Q..SC

"ALU/B,BMX/KMX,KMX/SC,SHF/ALU,QK/SHF"

QLSHF

"QK/SHF"

R(DST).ALU

"SHF/ALU,SPO,AC/WRITE.RAB,SPO.ACN11/DST.DST"

R(DST).D

"RAMX/D,AMX/RAMX,ALU/A,SHF/ALU,SPO.AC/ARITE ,RAR,SPO,ACN11/DST.DST"

R(DST)D.SXT[].RIGHT

"RAMX/D,AMX/RAMX .SXT,DT/@1,ALU/A,SHF/RIGHT,SPO.AC/WRITE.RAB,SPO.ACN11/DST,DST"

R(PRN).0+D.RLOG

R(PRN).D

"ALU/A+B.RLOG,BMX/RBMX ,RBMX/D,AMX/RAMX,0XT,DT/LONG,R(PRN)_ALU"
"SHF/ALU,SPO,AC/WRITE.RAB,SPO.ACN/PRN"
"RAMX/D,AMX/RAMX ,ALU/A,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN"

R(PRN).D+K[],RLOG

"RAMX/D,AMX/RAMX,KMX/@1,BMX/KMX,ALU/A+B,RLOG,DT/LONG,R(PRN).ALU"

R(PRN)_ALU

R(PRN).D=K[),RLOG

"RAMX/D,AMX/RAMX ,KMX/@1 ,BMX/KMX ,ALU/A=B RLOG,DT/LONG,R(PRN)LALU"

R(PRN).D,OR.Q

"RAMX/D,AMX/KRAMX ,RBMX/Q,BMX/RBMX,ALU/COR,R(PRN).ALU"

R(PRN).DI(]Q

"RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX,ALU/@1,R(PRN)_ALU"

R(PRN).K(]

"KMX/@1,BMX/KMX,ALU/B,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN"

R(PRN).LA+K([],RLOG

"AMX/LA,KMX/@1,BMX/KMX,ALU/A+B
. RLOG,DT/LONG,R(PRN)_ALU"

R(PRN).LA+Q

"AMX/LA,RBMX/G,BMX/RBMX ,ALU/A+B,SHF/ALU,SPO.AC/WRITE.RAB,SPO,ACN/PRN"

R(PRN).LA=K(].RLOG

"AMX/LA,KMX/@1
,BMX/KMX ,ALU/A~B,RLOG,DT/LONG,R(PRN)_ALU"

R(PRN)._LA[)JMASK

"AMX/LA,BMX/MASK,ALU/81,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN"

R(PRN).LC

"BMX/LC,ALU/B,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN"

R(PRN).PACK.FP

"BMX/PACKED.FL,ALU/B,SHF/ALU,SPO,AC/WRITE
. RAB,SPO.ACN/PRN"
"RAMX/Q,AMX/RAMX ,ALU/A,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN"

R(PRN).Q
R(PRN)_G+K
[} ,RLOG
R(PRN).0=K[) .RLOG

"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/A+B
. RLOG,DT/LONG,R(PRN)ALU"
"RAMX/Q,AMX/RAMX ,KMX/@1,BMX/KMX ,ALU/A~B . RLOG,DT/LONG,R(PRN)ALU"

R(PRN+1).ALU
R(PRN+1).D

"SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN+1"
"RAMX/D,AMX/RAMX ,ALU/A,SHF/ALU,SPO.AC/WRITE.RAB,SPO,ACN/PRN+1"

R(PRN+1).D.0R.Q

"RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX ,ALU/OR,SHF/ALU,SP0.AC/WRITE,RAB,SPO,ACN/PRN+1"

(LNOJ) SOHOVIN 3AOJ0HIIN WILSAS

QaQ,.ANDNOT,.RC(]

Q.G,LEFT

'KMX/Gl,BHX/KHX,ALU/B,SHF/ALU,SPO.AC/HRITE.RAB,SPO.ACN/PRNOI'

R(PRN+1).0Q

'RAHX/Q,AHX/RAMX,ALU/A,SHF/ALU,SPO.AC/HRITE.RAB;SPO.ACN/PRN#[‘

R(PRN+1).LA
R(PRN+1).LC
R{SC)-ALU

"SHF/ALYU,SPO,AC/WRITE ,RAB,SPO.ACN/SC"

R(SC).LA

'AMX/LA,ALU/A,SHF/ALU,SPO.AC/HRITE.RAB,SPO.ACN/SC"
RITE.RAB'SPO.ACN/SC'

ALU,SPO.AC/H
'AMX/LA,RBMX/D,BMX/RBNX,ALU/A*B,SHF/ALU,SPO.AC/U
RITE.RAB,SPO.ACN/SC“
'AMX/LA,RBHX/D,BHX/RBMX,ALU/A-B,SHF/
"ALU.LC,R(SC).ALU"
/SC'
RAB,SPO.ACN
O.AC/HRITE.
"RAHX/G,AMX/RAMX,ALU/A,SHF/ALU,SP

R(SP1).ALU

"SHF/ALU,SPO,AC/WRITE.RA
SP!'
”RANX/D,AHX/RAHX,ALU/A,SHF/ALU,SPO.AC/HRITE.RAB,SPO.ACN/SPI.
.SPl'
'Kfixlfll,BMX/KMX.ALU/B,SHF/ALU,SPO.AC/HRITE.RAB,SPO.ACN/SPl
N/SP!.SP!'
TE.RAB,SPU.AC
'BHX/PACKED.FL,ALU/B.SHF/ALU,SPO.AC/HRI
ACN/SPI.SPl'
'RAMX/Q,AHX/RAHX,ALU/A,SHF/ALU,SPO.AC/WRITE.RAB,SPO.
'BMX/LC,ALU/B,SHF/ALU,SPO.AC/HRITE.RAB,SPO.ACN/SPl#l'
'RAMX/O,AMX/RANX,ALU/A,SHF/ALU,SPO.AC/HRITE.RAB,SPO.ACN/SPl#l'

R(SRC!1)oALUY

C/HRITE.RAB,SPO.ACNI1/SRC.0R.1'
"RBMX/D,BMX/RBHX,ALU/H,SHF/ALU,SPO.ASKC.SRC"
"SHF/ALU,SPO,AC/WRITE.RAB,SPO.ACNI1/
ACNIl/SRC-SRC'
'RAMX/D,AHX/RAMX,ALU/A.SHF/ALU,SPD.AC/HRITE.RAB,SPO.
SPO.ACN!l/SRC.SRC'
'RBHX/D,BMX/RBHX,ALU/B,SHF/ALU,SPO.AC/HRITE.RAB,
.RLOG,DT/HORD,R(SRC)_ALU"

R(5C).D
R(SCIK{]

R(SC).LA+D
R(SC).LA~D
R(SCI.LC
R(SC).0
R(5P1).D
R(SP1}.KI[]
R(SP1).PACK,FP
R(SP1).0
R(SP1+1).LC
R(SP1+1).0
29

'AMX/LA,ALU/A,SHF/ALU,SPO.AC/hRITE.RAB,SPD.ACN/PRN#i'
"BMX/LC,ALU/B,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN+1"

R(SRC!1).D(B)
R(SRC)-D
R(SRC).D(B)
R(SRC).ALU

R(SRC).D+K[],RLOG
R{SRC).D=K[].RLOG
R(SRC).LC
R(SRC).0

R6.D+K[]) .RLOG
R6.LA+K[].RLOG
R6.LA=K(],.RLOG
RC(SC)-0-LC
RC(SCI-ALYU

“RAKX/D,AHX/RAHX,ALU/A,SHF/ALU,SPO.AC/HRITE.RAB,SPO.ACN/SC'
'KMX/Gi,BHX/KMX,ALU/B,SHF/ALU,SPO.AC/NRITE.RAB,SPO.ACN/SC'

B,SPO.ACN/SP1,5P1"

"SHF/ALU, SPO,AC/WRITE,RAB,SPO.ACN11/SRC,OR.1"

- 'RAMX/D,AHX/RAMX,KHX/OI,BMX/KMX,ALU/A#B
'RAMX/D,AHX/RAMX,KHX/Gl,BMX/KMX,ALU/A-B.RLDG,DT/NORD,R(SRC)-ALU"
"BMX/LC,ALU/B,R(SRC)..ALU"
'RAMX/Q,AMX/RAHX,ALU/A,SHF/ALU,SPD.AC/KRITE.RAB,SPO.ACN)I/SRC.SRC'

MX/KMX,ALU/A#B.RLOG,SHF/ALU'
”SPO.R/HRITE.RAB,SPO.RAB/RS,RAMX/D,AMX/RAMX,KMX/Bl,BSPO.R/HRITE.R
AB,SPO.RAB/R6'
"AMX/LA,BMX/KHX,KNX/@X,ALU/I#B.RLOG,DT/HORD,SHF/ALU,
SPO.R/HRITE.RAB,SPO.RAB/Rb'
HDRD,SHF/ALU,
/A-B.RLOG,DT/
'AMX/LA,BHX/KMX,KNX/@I,ALU
*ALU.O=LC,RC(SC)_ALU"
"SHF/ALU,SPO/WRITE.RC.SC"

RC(SC)-ALU.RIGHT

"SPO/WRITE.RC,.SC,SHF/RIGHT"

RC(SC).Q

"ALU.Q,RC(SC).ALL"

RC(SC).D

RCLI&VALD+G
RC{} .0
RC(1.0+4K()+1
RC(1.0+LC+1
RCLI_O+MASK+1
RC()_O+MASK+1 RIGHT2
RC(1.0=D
RCI}.ALU

"ALU.D,RC(SC).ALU"

U,SPO.R/HRXTE.RC,SPO.RC/R!”
“RAMX/D,AHX/RAMX,RBMX/Q,BNX/RBMX,ALU/A+B,VAK/LDAD,SHF/ALCIGI"
“AMX/RAMX.OXT,DT/LONG,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPO.R PO.R/HRITE.RC,SPO.RC/Ol'
¢B+1,SHF/ALU,S
'AMX/RAMX.OXT,DT/LDNG,KMX/@Z,BNX/KMX,ALU/A
”AHX/RAMX.OXT,DT/LONG,BNX/LC,RLU/A*B+1,SHF/ALU,SPO.R/HRITE.RC,SPD-RC/OI'
"AHX/RAMX.OXT,DT/LONG,BMX/MASK,ALU/A¢B¢1,SHF/ALU,SPO.R/HRITE.RC,SPO.RC/G!'
"AHX/RAMX.OXT,DT/LONG,BMX/HASK,ALU/A+H+1,SHF/RIGHTZ,SPU.R/RRITE.RC,SPO.PC/@I'
'AHX/RAMX.OXT,DT/LONG,RBNX/D,BHX/RBMX,ALU/A-B,SHF/ALU,SPO.R/HRITE.RC,SPO.RC/OI'
"SHF/ALU,SPO,R/WRITE.RC,SPO.RC/@1"

(LNOD) SOHOVIAN 3A0J0HIIN WILSAS

R(PRN+1).K[)

"SHF/LEFT,SPO,R/WRITE.RC,S5PO.RC/@1"

RCIJ_ALU.LEFT2

"SPO.R/WRITE.RC,SPO.RC/@1,SHF/ALU.DT,DT/LONG"

RC()J.ALULLEFT3
RC[1LALU.RIGHT
RC()JLALU.RIGHT2

"SPO,R/WRITE,RC,SPO,RC/®1,SHF/LEFT3"

RCC}.D
RCI).D(B)
RCL1.D+K
(]
RCL1_D=K(]

"RAMX/D,AMX/RAMX ,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"

RCII.D.OXTI(]

€9

RC{J.D.AND
.K(}
RC{}.D.AND ,MASK
RC{1.D.ANDNOT.Q
RC{1.D.CTX

"SHF/RIGHT,SPO.R/WRITE,RC,SPO.RC/01L"
"SHF/R1GHT2,SPO.R/WRITE.RC,SPO.RC/8L"
"RBMX/D,BMX/RBMX,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"
"RAMX/D,AMX/RAMX ,BMX/KMX,KMX/82,ALU/A+B,SHF/ALU,SPO.R/WRITE,RC,SPO,RC/01"

"RAMX/D,AMX/RAMX ,BMX/KMX,KMX/82,ALU/A=B,SHF/ALY,SPO.R/WRITE,RC,8P0O,RC/@1"
"RAMX/D,AMX/RAMX,0XT,DT/@2,ALU/A,SHF/ALU,SPO,R/WRITE.RC,SPO.RC/01"
"RAMX/D,AMX/RAMX ,BMX/KMX ,KMX/82,ALU/AND,SHF/ALU,SPO.R/WRITE,RC,SPO,RC/01"
"RAMX/D,AMX/RAMX ,BMX/MASK,ALU/AND,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/81"

RCIJ_D.LEFT
RC{I.D.LEFT2

"RAMX/D,AMX/RAMX ,RBMX/Q,BMX/RBMX,ALU/ANDNOT,SHF/ALU,SPO,R/WRITE.RC,SPO,RC/@1"
"RAMX/D,AMX/RAMX ,ALU/A,SHF/ALU.DT,DT/INST.DEP,SPO.R/WRITE,RC,SPO.RC/01"
"RAMX/D,AMX/RAMX ,ALU/A,SHF/LEFT,SPO.R/WRITE.RC,S5PO.RC/@1"
"RAMX/D,AMX/RAMX,ALU/A,SHF/LEFT3,SP0O,R/WRITE.RC,S5P0O.RC/A1"

RCI}J.D.OR.KI[)

"RAMX/D,AMX/RAMX ,KMX/R2,BMX/KMX,ALU/OR,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"

RC{).D.OR.0Q

RC{1.D.ORNOT,.K()

"RAMX/D,AMX/RAMX ,RBMX/Q,BMX/RBMX,ALU/OR,SHF/ALU,SPO.R/WRITE,RC,SPO.RC/81"
*SPO.RC/@1,SPO,R/WRITE,.RC,ALU/ORNOT, AMX/RAMX,RAMX/D,BMX/KMX,KMX/82,SHF/ALU"

RC{}.D.SXTI[]

"RAMX/D,AMX/RAMX ,SXT,DT/@2,ALU/A,SHF/ALU,SPO,R/WRITE.RC,SPO,RC/01"

RCIJ.KI[]

"KMX/@2,BMX/KMX ,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/01"

RCI{I_K[}l+1

"AMX/RAMX.O0XT,DT/LONG,KMX/@2,BMX/KMX,ALU/A+B+1,SHF/ALU,SPO,R/WRITE,RC,S8P0O,RC/@L"

RCLI.K(].LEFT2

"KMX/92,BMX/KMX,ALU/B,SHF/ALU.DT,DT/LONG,SPO.R/WRITE.RC,SPO.RC/81"

RCLI_K[].LEFT3

"KMX/82,BMX/KMX,ALU/B,SHF/LEFT3,SPO.R/WRITE.RC,SPO.RC/@#1"

RCII_K[]1.RIGHT2

"KMX/82,BMX/KMX ,ALU/B,SHF/RIGHT2,SPO,R/WRITE,.RC,SPO.RC/@1"

RC{).LA

"AMX/LA,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/R1"

RC{)_LA+LB,CTX
RC{).LA=K(]

"AMX/LA,BMX/LB,ALU/A+B,SHF/ALU,.DT,DT/INST.DEP,SPO.R/WRITE,RC,SPO.RC/81"
“AMX/LA,KMX/@2,BMX/KMX,ALU/A=B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/01"

RCII_LA.AND.K[]
RCIJ_LA.CTX

"ALU.LA.,AND.K{82],RC[@1]_ALL"
"AMX/LA,ALU/A,SHF/ALU,DT,DT/INST.DEP,SPO.R/WRITE.KC,SPO,RC/01"

RC{).LB

"BMX/LB,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/AL"

RCI{)_LB.LEFT

"BMX/LB,ALU/B,SHF/LEFT,SPO.R/WRITE.RC,SPO.RC/7@1"

RC[1.LC
RC{]NOT.Q

"BMX/LC,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"
"RAMX/Q,AMX/RAMX,ALU/NOTA,RC[O1]_ALU"

RC{)J_PACK,.FP

"BMX/PACKED.FL,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/81"

RCLILPC
RCLI.Q

"BMX/PC,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"

RC(].G+1

"ALU.O+0+1,RCl@3]ALU"
"RAMX/Q,AMX/RAMX ,BMX/KMX,KMX/82,ALU/A+B,SHF/ALY,S5PO0.R/WRITE,RC,SPO,RC/81"

RC{1.Q+K
(]
RC{).G+LC
RC{1.G+PC
RC{).O+PC+1

RCL]-Q=K(]
RC{}.QG=LC
RC{).G=MASK=1

RC{I~G.OXT[]
RCI)_Q.AND.KI[]
RC()_0.ANDNOT,.K(]
RC().Q.LEFT

RC()J_Q.LEFT3

"RAMX/Q,AMX/RAMX ,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPC.RC/81"

"ALU/A+B,RAMX/Q,AMX/RAMX,BMX/LC,SPO.R/WRITE.RC,SPO.RC/01"
"RAMX/Q,AMX/RAMX,BMX/PC,ALU/A+B,SHF/ALU,SPO,R/WRITE,RC,SPO,RC/01"
"RAMX/G,AMX/RAMX,BMX/PC,ALU/A4B+},SHF/ALU,SPO.R/WRITE,RC,SPO.RC/01"
"RAMX/Q,AMX/RAMX ,BMX/KMX ,KMX/@2,ALU/A=B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/0@1"
"ALU/A=B,RAMX/Q,AMX/RAMX,BMX/LC,SPO.R/WRITE.RC,SPO.RC/@1"
"RAMX/Q,AMX/RAMX ,BMX/MASK,ALU/A=B=~1,SHF/ALU,SPO,R/WRITE.RC,SPO,RC/@1"
"RAMX/Q,AMX/RAMX,0XT,DT/@2,ALU/A,SHF/ALU,SPO,R/WRITE.RC,SPO.RC/@1"
"RAMX/Q,AMX/RAMX,BMX/KMX ,KMX/@2,ALU/AND,SHF/ALU,SPO,R/WRITE.RC,SPO,RC/@1"
"RAMX/Q,AMX/RAMX,BMX/KMX,KMX/82,ALU/ANDNOT,SHF/ALU,SPO,R/WRITE,RC,SPO.RC/81"
"RAMX/Q,AMX/RAMX,ALU/A,SHF/LEFT,SPO.R/WRITE,RC,SPO.RC/@1"
“KAMX/Q,AMX/RAMX,ALU/A,SHF/LEFT3,S5P0.R/WRITE,.RC,SPO.RC/0L"

(LNOJ) SOHOVIN 3A0J0HIIN WILSAS

RC(]J_ALU.LEFT

RCI1.G.RIGHT2

"RAMX/Q,AMX/RAMX.SXT,DT/82,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/Q1"

RC{JLKLOG.RIGHT

"BMX/0,MSC/READ.RLOG,ALU/B,SHF/RIGHT,SPO.R/WRITE.RC,SPO,RC/01"

RIJ&VA_LA+KI([])

"AMX/LA,KMX/@2,BMX/KMX,ALU/A+b,VAK/LOAD,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/081"
"AMX/LA,KMX/@2,BMX/KMX,ALU/A~B,VAK/LOAD,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/0@L"

RII&VALLA=KI)

R{J&VA_LA=K(].RLOG
RIJ&VALQ=K[]
RI1.0

R[)J_0+LBR+1
R[)1.0O=1
R(J.0=D

R().0~KIL]
R{}.0-LB

R{).0=«0

RIJLALY
R{J_ALU.LEFT

R(1.ALU.LEFT3

R{}=ALU.RIGHT
RIJ_ALU.RIGHT2
R{1.D

R{1.D+K
{1

¥9

"KAMX/Q,AMX/RAMX ,ALU/A,SHF/RIGHT,SPO,R/WRITE,RC,SPO.RC/@1"
“ALU.G,SHF/RIGHT2,SPO.R/WRITE.RC,SPO,.RC/Q1"

R[1.D+Q
RI{I.D+G+1

R{I.D=KI[]
R(}].D=LC~1

R{).D=Q
RII_D.AND
.KI[]
R[).D.OK,LC
R[)_D,0OR,PACK,FP
R[]1.D.0OR.Q
R{J_KL)

RIY_LA
RI).LA+D

RI)J.LA+D+1
RIJLLA+K[])

RIJ.LA+KL[]+1
R{).LA+K{]),RLOG
R{).LA+LC

RIJ_.LA+MASK+]

R{)J_LA+Q
R[).LA=D
R{}_LA=KI[)

R{}_LA=K[].RLOG
RI}.LA=MASK=1

R{]LA=Q

R{)_LA,AND,KI[]
R(J.LA,OR.D
R[J_LA.,ORNOT,.MASK

"AMX/LA,KMX/€2,BMX/KMX,ALU/A=B ,RLOG,DT/LONG,VAK/LUAD,SHF/ALU,SPO.R/WRITE,RAB,SPO.RAB/OL"
"RAMX/G,AMX/RAMX ,KMX/82,BM¥X/KMX,ALU/A~B,VAK/LOAD,SPO.R/WRITE.RAB,SPO,RAB/01"
"SPO.R/WRITE,RAB,SPO,RAB/@1,AMX/RAMX,0XT,DT/LONG,ALU/A,SHF/ALU"

“AMX/RAMX.OXT,DT/LONG,BMX/LB,ALU/A+B+1,SHF/ALU,SPO.R/WRITE
. RAB,SPO,RAB/R1"
"AMX/RAMX ,0XT,DT/LONG,BMX/KMX ,KMX/.1,ALU/A=B,SHF/ALU,SPC.R/WRITE.RAB,SPO,RAB/@1"
"AMX/RAMX,0XT,DT/LONG,RBMX/D,BMX/RBMX ,ALU/AB,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/O1"
*AMX/RAMX,0XT,DT/LONG,KMX/@2,BMX/KMX,ALU/A=B,SHF/ALU,SPO.R/WRITE.RAB,SPO,RAB/@1"
"AMX/KAMX.0XT,DT/LONG,BMX/LR,ALU/A~B,SHF/ALU,SPO.R/WRITE.RAB,SPO,RAR/A1"
®"AMX/RAMX.0XT,DT/LONG,RBMX/Q,BMX/RBMX,ALU/A=B,SHF/ALU,SPO,R/WRITE.RAB,SPO.RAB/R1"
"SHF/ALU,SPO.R/WRITE,RAB,SPO.RAB/@1"
"SPO.R/WRITE,.RAB,SPO.RAB/@1,SHF/LEFT"
"SPO.R/WRITE,RAB,SPO,RAB/R1,SHF/LEFT3"
"SHF/RIGHT,SPU.R/WRITE ,RAB,SPO.RAB/B1L"
"SPO.R/WRITE ,KkAB,SPO,RAB/®1,SHF/RIGHT2"

"SPO,R/WRITE,RAB,SPO.RAB/@1,RAMX/D,AMX/RAMX ,ALU/A,SHF/ALU"

MX/RAMX
,KMX/82,BMX/KMX ,ALU/A+B,SHF/ALU"
*SPO.R/WRITE ,RAB,SPO.PAB/@1,RAMX/D,A
X
,ALU/A+B,SHF/ALU"
RAMX/D,AMX/RAM
,RBMX/Q,BMX/RBMX
"SPO.R/WRITE.PAB,SPO.RAB/@1,
,ALU/A+B+1,SHF/ALU"
"SPO.R/WRITE,RAB,SPO.RAB/@1,RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX
"SPU.K/WRITE,RAB,SPO.RAB/@1,RAMX/D,AMX/RAMX ,KMX/82,BMX/KMX,ALU/A=B,SHF/ALU"
"ALU.D=LC=1,R(@1}ALU"

"SPO,R/WRITE,RAB,SPO.RAB/@1,RAMX/D,AMX/RAMX,RBMX/Q,BMX/RBMX,ALU/A=B,SHF/ALU"
"SPO.R/WRITE,.RAB,SPO,RAB/R1,ALU/AND,AMX/RAMX
,RAMX/D,BMX/KMX ,KMX/R2,SHF/ALU"
"SPO,k/WPITE,RAB,SPO.RAB/@1,ALU/OR,AMX/RAMX ,RAMX/D,BMX/LC,SHF/ALU"
“SPO,R/WRITE,RAB,SPO.RAB/@1,ALU/OR,AMX/RAMX,RAMX/D,BMX/PACKED.FL,SHF/ALU"
,ALU/OR,SHF/ALU"
,RBMX/Q,BMX/RBMX ,AMX/RAMX
"SPO.K/WRITE.RAB,SPD.RAB/@1,KAMX/D
"RMX/KMX,KMX/@2,ALU/B,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@L"
"SPC.R/WRITE,RAB,SPO.RAB/@1,AMX/LA,ALU/A,SHF/ALU"

"AMX/LA,RBMX/D,BMX/RBMX,ALU/A+E,SHF/ALU,SPO.R/WRITE.RAB,SPO,RAB/&1"
"AMX/LA,RBMX/D,BMX/RBMX,ALU/A+B+1,SHF/ALU,SPO,R/WRITE.RAB,SPO,RAB/0L"
"AMX/LA,BMX/KMX,KMX/®2,ALU/A+B,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@1"
“AMX/LA,BMX/KMX ,KMX/@2,ALU/A+B+]1,R[@1)ALU"

“AMX/LA,BMX/KMX,KMX/@2,ALU/A+B RLOG,DT/LONG,SHF/ALU,SPO.R/WRITE.RAB,SPO,RAB/#1"
"AMX/LA,BMX/LC,ALU/A+B,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@1"
“AMX/LA,BMX/MASK,ALU/A+B+1,R(81])_ALU"

“AMX/LA,RBMX/Q,BMX/RBMX,ALU/A+B,SHF/ALU,SPO.R/#RITE.RAB,SPO,RAB/@1"
"AMX/LA,RBMX/D,BMX/RBMX,ALU/A~B,SHF/ALU,SPO.R/WRITE.RAB,SPO,RAB/01"
"AMX/LA,BMX/KMX,KMX/@82,ALU/A=B,SHF/ALU,SPO.R/WRITE.RARB,SPO,RAB/@1"
"AMX/LA,BMX/KMX,KMX/®2,ALU/A=B RLOG,DT/LONG,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/81"
"ALU/A=B=1,AMX/LA,BMX/MASK,SPO,R/WRITE,RAB,SPO.RAB/@1,SHF/ALU"

"AMX/LA,RBMX/Q,BMX/RBMX,ALU/A-B,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@1"

"AMX/LA,BMX/KMX,KMX/82,ALU/AND,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@1"

"AMX/LA,RBMX/D,BMX/RBMX,ALU/OR,SHF/ALU,SPO.R/WRITE,RAB,SPC.RAB/@L"
"AMX/LA,BMX/MASK,ALU/ORNOT,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/R1L"

(LNOJ) SOHOVIW 3A0J0HIIWN WILSAS

RC(JoQ.RIGHT

RCIILQ.8XTI)

"BMX/LB,ALU/B,SHF/ALU,SPO.R/WKITE.RAB,SPO,RAB/QL"

R{J.LC
R{J_LC.RIGHT

"BMX/LC,ALU/B,SHF/ALU,SPO,R/WRITE.RAB,SPO.RAB/R1"
"AMX/RAMX ,0OXT,DT/LONG,ALU/NOTA,R[@1)_ALU"

R{}J.NOT,.D

"RAMX/D,AMX/RAMX,ALU/NOTA,R[@1]_ALU"

R{)J.NOT,FASK

"BMX/MASK,AMX/RAMX ,OXT,DT/LONG,ALU/ORNCT,SHF/ALU,SPO.R/WRITE,RAB,SPO.RAB/2L"

R(J.NOT.Q

"KAMX/Q,AMX/RAMX,ALU/NOTA,R(@1)_ALU"

R{)_PACK,FP

"BMX/FPACKED,.FL,ALU/B,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/R1"

RI{}.0

"SPO.R/WRITE ,RAB,SPO.RAB/@1,RAMX/Q,AMX/RAMX,ALU/A,SHF/ALU"

R{).Q+1

"ALU.O+0Q+1,R[€1)_ALU"

R(].Q+5

"SPO.R/WRITE.FAB,SPO,RAB/®1,ALU/A+B+1 ,BMX/KMX,KMX/,4,AMX/RAMX,RAMX/Q,SHF/ALU"

R[1.0¢+K
(]

“SPO.R/WRITE.RAB,SPN,RAB/@1,RAMX/Q,AMX/RAMX,BMX/KMX,KMX/@2,ARLU/A+B,SHF/ALU"

R{]_Q+LB

“SPU.F/WRITE,RAB,SPO,RAB/®1,ALU/A+B,AMX/RAMX,BMX/LB,RAMX/Q,SHF/ALU"

R[].0G+LC

"SPO.R/WRITE,RAB,SPO.RAB/@1,RAMX/Q,AMX/RAMX,BMX/LC,ALU/A+B,SHF/ALU"

R[1.G~D

"SPO.R/WRITE.RAE,SPO.RAB/®1,RAMX/0,AMX/RAMX,RBMX/D,BMX/RBMX,ALU/A=B,SHF/ALU"

R{]1.G=D=1

"SPO.R/WRITE,RAB,SPO.RAB/@1,ALU/A=B=1,AMX/RAMX,RAMX/Q,BMX/RBMX,RBMX/D,SHF/ALU"

R[1.Q=KI[]

“SPO.K/WRITE,RAB,SPO,RAB/@1,RAMX/Q,AMX/RAMX
,BMX/KMX ,KMX/@2,ALU/A~B,SHF/ALU"

R[J.Q=K[].RLOG

"RAMX/Q,AMX/RAMX ,BMX/KMX,KMX/@2,ALU/A=B.RLOG,DT/LONG,SHF/ALU,SPO.R/WRITE,RAB,SPO,RAB/OL"

R{).Q=LC
R{}.Q.AND,.K()
RIJ.OG.ANDNOT,.K
(]}

“SPO.R/WRITE,RAB,SPO.RAR/R1,RAMX/Q,AMX/RAMX,BMX/LC,ALU/A=B,SHF/ALU"

R[1.Q.0R.D

"SPO.R/WRITE,RAR,SPO,RAB/R1,ALU/OR,AMX/RAMX,RAMX/Q,BMX/RBMX,RBMX/D,SHF/ALU"

RI)J_QC.ORMOT,KI[]

"BMX/LC,ALU/B,SHF/RIGHT,SPO.H/WRITE.RAB,SPO.RAB/QL"

R{}_NOT.O

"ALU/AND,SPO.R/WRITE.RAB,SPO.RAB/@1,AMX/RAMX
,RAMX/Q,BMX/KMX , KMX/@2"
"SPO.R/WRITE,RAB,SPO.RAR/@1,ALU/ANDNOT,AMX/RAMX,RAMX/Q,BMX/KMX,KMX/82,8HF/ALU"
"SPO.R/WRITE.RARB,SPO.RAB/@1,RAMX/Q,AMX/RAMX,BMX/KMX ,KMX/@2,ALU/ORNOT,SHF/ALU"

R{J_Q.RIGHT,!

"ALU.Q,SHF/RIGHT,SPO.R/WRITE.RAB,SPO,RAB/@1"

R{J.RLOG,RIGHT,.1

"BMX/0,MSC/READ.RLOG,ALU/B,SHF/RIGHT,SPO,.R/WRITE.RAB,SPO.RAB/R1"

SC&STATELSTATE=R(]
(EXP)
)

"LAB.R([@1) ,AMX/LA,EBMX/AMX

SC.0(A)

"AMX/RAMX.OXT,DT/LONG,EBMX/AMX ,EXP,EALU/B,SMX/EALU,SCK/LOAD"

SC.0=K[]

"BMX/KMX ,KMX/@1,AMX/KAMX.0XT,DT/LONG,ALU/A=B,SMX/ALU,SCK/LOAD"

EXP,MSC/LOAD,.STATE, ,EALU/A=B,SMX/EALU,SCK/LOAD"

SC.ALU

"SMX/ALU,SCK/LOAD"

SC.ALUCEXP)

"SMX/ALU.EXP,SCK/LOAD"

SC.D

"RAMX/D,AMX/RAMX ,ALU/A,SMX/ALU,SCK/LOAD"

SC.D(EXP)

"RAMX/D,AMX/RAMX ,ALU/A,SMX/ALU,EXP,SCK/LOAD"

SC.D(EXP)
(A)

"RAMX/D,AMX/RAMX
,FBMX/AMX ,EXP,EALU/B,SMX/EALU,SCK/LOAD"

SC.D(EXP)
(B)
SC.D=K[]

"RAMX/D,AMX/RAMX ,KMX/81,BMX/KMX,ALU/A=B,SMX/ALU,SCK/LOAD"

"KBMX/D,BMX/RBMX,ALU/bB,SMX/ALU,EXP,SCK/LOAD"

SC.D.OXT(I=~K([]

"RAMX/D,AMX/RAMX ,0XT,DT/81,KMX/82,BMX/KMX,ALU/A=B,SMX/ALU,SCK/LOAD"

SCaD.OXT[]

"RAMX/D,AMX/RAMX,0XT,DT/@1,BMX/KMX,KMX/@2,ALU/X0OR,SC_ALU"

XOR.K([]

SC.DAND.KI[]

"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX ,ALU/AND,SMX/ALU,SCK/LOAD"

SC.D.OR.K(]

"RAMX/D,AMX/RAMX ,KMX/@1,BMX/KMX,ALU/OR,SMX/ALU,SCK/LOAD"

SC.D.SXT(]

SC_EALU
SC.FE

"RAMX/D,AMX/RAMX .SXT,DT/@1,ALU/A,SMX/ALU,SCK/LOAD"
"SMX/EALU,SCK/LOAD"
"SMX/FE,SCK/LOAD"

SCKI(]

"KMX/@1,EBMX/KMX,EALU/B,SMX/EALU,SCK/LOAD"

SC.K[].ALU

"KMX/@1,BMX/KMX,ALU/B,SMX/ALU,SCK/LOAD"

SC.LA

"AMX/LA,ALU/A,SMX/ALU,SCK/LOAD"

SC_LAJAND.KI[]

"AMX/LA,KMX/@1,BMX/KMX,ALU/AND,SMX/ALU,SCK/LOAD"

SC.LC(EXP)
SC_NABS(SC=FE)

"BMX/LC,ALU/B,SMX/ALU.EXP,SCK/LOAD"

SC_PSLADDR

"SMX/EALU,EBMX/KMX,SCK/LOAD,KMX/
,F,EALU/B"

"EBMX/FE,EALU/NABS,A~B,SMX/EALU,SCK/LDAD"

(LNOJ) SOHOVIN 3A0J04IIN NILSAS

R{).LB

"RAMX/Q,AMX/RAMX,ALU/A,SMX/ALYU,SCK/LOAD"

SC.G{EXP)

"RAMX/Q,AMX/RAMX,EBMX/AMX EXP,EALU/B,SMX/EALU,SCK/LOAD"
"RBMX/Q,BMX/RBMX,ALU/B,SMX/ALU.EXP,SCK/LOAD"

SC.Q(EXP)
(B)

SC_Q+K[]

SC.0=K[)
SC.Q.AND K]

SCaQ@.0R.KI[)
SCa0,SXT(]
SC.RCI)

SCLRCL) (EXP)
SC.RI[}

SCoRI[J(EXP)
SC_R[].AND.KI[]
SC_S8C+1
SC.SC+EXP(Q)(A)
SCLSC+FE

SC.SC+K[)
SC.SC+SHF
VAL

SC.SC=FE

SC_SC~KI[]
SC.SC=SHF.VAL

SC_SC.ANDNOT.FE

SC.SC.,ANDNOT.K(]
SC.SC.OR.K[]
SC.SHF.VAL

SC.STATE
SC.STATE ,ANDNOT.KI[]

SC.STATE.OR,.K{]
SD_NOT.SD
SD.SS

SS.0&SD.0O
SS-ALULS
55.8D

SSW55.XORALU1S&SDLALULS
STATE.O(A)
STATE_AMX ,EXP
STATE.D(EXP)
STATELFE
STATE_FIRST

STATELINNEROBJ
STATELINNERSRC

STATE.KI[]
STATE_OUTER
STATE.PREDEC

STATELOG(EXP)
KMX
STATELSC.,VIA
STATE.SKPLONG
STATE.STATE+1
STATE.STATE+FE
STATE.STATE+K[)

"RAMX/Q,AMX/RAMX,BMX/KMX ,KMX/81,ALU/A+B,SMX/ALU,SCK/LOAD"
"RAMX/Q,AMX/RAMX
,BMX/KMX ,KMX/@1,ALU/A~B,SMX/ALU,SCK/LOAD"
"RAMX/Q,AMX/RAMX ,BMX/KMX,KMX/81,ALU/AND,SMNX/ALU,SCK/LOAD"
"RAMX/Q,AMX/RAMX,BMX/KMX,KMX/81,ALU/OR,SMX/ALU,SCK/LOAD"
"RAMX/Q,AMX/RAMX ,SXT,DT/@1,ALU/A,SMX/ALU,SCK/LOAD"
"SPO.R/LOAD,.LC,SPO.RC/81,BMX/LC,ALU/B,5MX/ALY,SCK/LOAD"
"SPO.R/LOAD,.LC,SPO.RC/R1,BMX/LC,ALU/B,SMX/ALU.EXP,SCK/LOAD"
"SPO.,R/LOAD,LAB,SPO,RAB/@1,AMX/LA,ALU/A,SMX/ALU,SCK/LOAD"
"SPO.R/LOAD.LAB,SPO,RAB/R1,AMX/LA,ALU/A,SMX/ALU.EXP,SCK/LOAD"
"ALU/AND,AMX/LA,SPO.R/LOAD,LAB,SPO.RAB/@1,BMX/KMX,KMX/92,SMX/ALU,SCK/LOAD"
"EALU/A+1,SMX/EALU,SCK/LOAD"

"EALU/A+B,EBMX/AMX .EXP,SMX/EARLU,SCK/LOAD,AMX/RAMX,RAMX/Q"
"EBMX/FE,EALU/A+B,SMX/EALU,SCK/LOAD"
"KMX/@1,EBMX/KMX,EALU/A+B,SMX/EALU,SCK/LOAD"
"EALU/A+B,EBMX/SHF ,VAL,SMX/EALU,SCK/LOAD"
"EBMX/FE,EALU/A-B,SMX/EALU,SCK/LOAD"
"KMX/81,EBMX/KMX,EALU/A=B,SMX/EALU,SCK/LOAD"
"EBMX/SHF ,VAL,EALU/A=B,SMX/EALU,SCK/LOAD"
"EBMX/FE,EALU/ANDNOT,SMX/EALU,SCK/LOAD"
"KMX/&1,EBMX/KMX,EALU/ANDNOT,SMX/EALU,SCK/LDAD"
"KMX/@1,EBMX/KMX,EALU/OR,SMX/EALU,SCK/LOAD"

"EBMX/SHF,VAL,EALU/B,SMX/EALU,SCK/LOAD"
"EALU/A,MSC/LOAD,STATE,SMX/EALU,SCK/LOAD"

"EALU/ANDNOT,EBMX/KMX,MSC/LOAD,STATE, SMX/EALU,SCK/LOAD,KMX/@1"
"EALU/OR,EBMX/KMX,MSC/LOAD,STATE, SMX/EALU,SCK/LOAD,KMX/81"

"SGN/NOT,SD"
"SGN/SD.,FROM,SS"
"SGN/CLR.SD+Ss"
"SGN/LOAD,.Ss*"
"SGN/SS,FROM,SD"
"SGN/S5.XOR.ALU"

"AMX/RAMX.0XT,DT/LONG,EBMX/AMX
. EXP,EALU/B,MSC/LOAD,STATE"
"EBMX/AMX.EXP,EALU/B,MSC/LOAD.STATE"
"RAMX/D,AMX/RAMX
,EBMX/AMX ,EXP,EALU/B,MSC/LOAD,STATE"
"EBMX/FE,EALU/B,MSC/LOAD.STATE"

"STATE.K(ZERO]"
“STATE.K[.11"

JEDITPC
$MATCHC

STATES
STATES

“STATE_K(.3]"
"KMX/®@1,EBMX/KMX,EALU/B,MSC/LOAD.STATE"
"STATE.K(ZERO]"
"STATE.K(.80)"

"RAMX/Q,AMX/RAMX
,EBMX/AMX ,EXP,EALU/B,MSC/LOAD,STATE"
*MSC/LOAD.STATE,EALU/B,EBMX/KMX
,KMX/SC"

"STATE.K{.4])"

3 SKPC STATES

"EALU/A+1,MSC/LOAD.STATE"
"EBMX/FE,EALU/A+B,MSC/LOAD.STATE"
"KMX/@1,EBMX/KMX ,EALU/A+B,MSC/LOAD.STATE"

(LNOD) SOHOVIN 3A0J0HIIN WILSAS

S5C.Q

[O1+X[M1*LXO0NG°NQV~°vQA=VvA

ATY=YA
YA 0+aTM

adyms

a=va

THI N4VT VA
IqQ+07VYAxo*a+d1~vaA
Jd=vA

JT+0=vA

YITYA

qQ+¥17vA [IX+VT1=VA Jd+¥1TYA O+YTMVA Q=¥T7VA 0=¥T"vA

gT+07vA 24

N«AAwYOAL/0T NYA«Wwd¥MS°

oTwANY,NXaOVNHVG'YO4/¥//OXNTNTVYYEX*HN/AXYVANHOY/AT/GVXYTNWXE/NWAXYDTNHR‘E//XHHEXYQ0N!+34XTWAYH/W/UN/INVXYTX/NYYIOw/QVOXTWYA/UAVA/wNTY/3HS

W
w
A
L
Y
L
S
*
A
Y
O
T
/
I
S
H
*
8
=
Y
/
N
I
V
I
‘
T
I
/
X
W
E
T
)
u
X
N
T
8
/
X
W
A
/
X
W
E
Z
=
Y
/
N
I
V
E
’
A
V
O
T
/
I
S
H
«
w
d
L
V
Y
I
S
L
O
N
O
N
Y
*
F
L
V
I
S
=
T
L
Y
L
I
S
w
l
P
*
I
N
A
A
L
V
I
S
=
I
L
V
Y
I
S
.
"
)
N
w
[
J
E
F
I
*14[3I[LI0S)ILIOL°JL3IN°V*NV0V°¥IOA°II°H0LSNLSSYV0°TYO==0L°IINI**ILOLLISLALNVIYTVLLYVVIMILVY"IISSSILSS~SLYS=INFVD=~ILSLV433LIVL°QLVSIIALIYTISVNOAMSINYI344SSCG4ANVLAYHIYOSNTYYA° WXAFAR*uwL*AWLA{LWINYEX0VO)VYVIIRNYYXIISVIu°NTSST)/8TRTM1OI/0=MII/%S3IXL"NXVNVILuTFWEILOYI4TASNSJ/.A/H,XN.a.SXWYAN/wNWwB*GX0[(OD3ITW/EdNIE°"LAVVFI*NLTYS‘NOIY1IVA"NSNWLATHW°APOMOL4YINIO0YS«wL’/N/T[lVAN9/dIwIN°ASLONY,"YwSOE30NL’TOAY/NVLIYwOS/ATWNL/YTOLYSwSIHIA‘LTVYwLAS3L®YLIS
0432030
7JIZT1A¥LI40OV1YW41Id5S°*H¥3T4¥OI00*°°L°I3¥3A0VLLV°IV3SLII4SYS0TTI=IIS3LT"LIYILLYVISLIdSVIS ww3w[{[{lL00Z9LV§°°*I°)IS1%3N~1°*"A°XHHHL°80V400"*I°°AFS3AL.JLYLVVLVIwIISV[SSTI(==MS133I=°LLLIVVYYNLLIII°VSSS¥I..,0S..
YuWXowoww«wwWXYVXHXANANNIAH/AVQYVY/YXNVVTXXYWVOYNOTTTAUOY//I/H/OYO''X/'A XTOXXNVNXXTAWTNHAHHNN/EY’NYVY/TO*D/EXXEAUAXHWAA/N/NW'VAX/YXT/EENXNYY/YAWXY/A/EVA‘NLEYNAXNA’/HVT‘GEAOTXN‘ARNIXDTE/GOR8NYVY‘GV//1T/A“/A+4NXN'ETWNe4YTNX‘’YT‘/WT/XYGEOAVN/4RBTVYGU/YXG+Ww/NRANTO'V4IYOTYN//AYA+’VHYNAYw/AAYOT/NTYAYV
4
¥
/
N
T
X
w
A
O
T
O
A
G
E
/
X
H
E
G
+
u
N
Y
Y
1
/
B
’
X
N
’
X
N
E
N
/
E
=
¥
TT[IN°LONGNY
=JTANY
[IMVVI¥YN=YI7VA s.w4wwADXXANWWAdREYVV/YASXY0HTTTVE/O/OTYT'X'/TX/XWNAHN/E0YNHYE//D=A/XXYTAWXHN//V‘YNEN‘YTAESYYX+//CNAY’NANTTAVORTN/IYYVTY*YL/AON/LTNXYI/A0ONBTYITLGYV/IANY’VXTwWYAwELYAwOV@XQTWOYVER/TOA/TVN/DAV/AAVAwYNTIV/AHS

3ONOTA
(T90LS
IINIL4LY°NV-V*=3IIILSSLVY~TYVIIIISLLSTVVMIIILSSLVVYNLNISVLVSVOIANS0L9
SYSTEM MICROCODE MACROS (CONT)

0=vYA

[I%+0=VA 9T+0=VA

"RAMX/Q,AMX/RAMX ,BMX/PC,ALU/A+R,VAK/LOAD"
'RAMX/Q,AHX/RAMX,KHX/OI,BMX/KMX,ALU/A-B,VAK/LOAD'
'RAMX/Q,AHX/RAMX,BHX/LB,ALU/A‘B,VAK/LOAD”

VALQ=K({]
VA.Q-LB

"RAMX/Q,AMX/RAFX,KMX/@l,BMX/KNX,ALU/ANDNOT,VAK/LOAD'
'SPO.R/LUAD.LC,SPO.RC/fll,BHX/LC,ALU/B,VAK/LOAD“
'SPU.R/LOAD.LAB,SPO.RAB/Pl,AMX/LA,ALU/A,VAK/LOAD"

VA.Q.ANDNOT.K[]
VALRCL]
VALRI()

"PCK/VA+4"

VA.VA+4

.TOC

B,FORK

Non-transfer

macros"

"LAB_R(SP1),0K/ID,CLR.IB.COND,PC_PC+N,SUB/SPEC,J/B.FORK"

BYTE

"DT/BYTETM

C.FORK

*SUB/SPEC,J/C,FORK"
"MCT/INVALIDATE,VAK/NOP"

CACHE,INVALIDATE
CALL

CALL()
CHK.FLT.OPR
CHK,ODD.ADDR
CLK,.UBCC

Macro definition

CLR.FPD
CLR.IB.COND
CLR.IB.OPC
CLR,IB.SPEC
CLR,IBO=1
CLR,IBO-3
CLR,IB2«3
CLR.1IB2=5
CLR,NEST,ERR
CLR,.SD&SS

"“suB/CALL"
"CALL,J/81"

"MSC/CHK.FLT,OPR"

"MSC/CHK.ODD,ADDR"
"CCK/LOAD,UBCC"
"MSC/CLR.FPD"

"IBC/CLR.1=5,COND"
"IBC/CLR,O,IEK/ISTR"
"IBC/CLK.1"
"IBC/CLR,0.1,IEK/ISTR"

"IBC/CLKR,0=3"
“IBC/CLR.2.3"
“IBC/CLR.,1=5,COND"

"MSC/CLR.NEST,ERR"
"SGN/CLR.,SD+S5"

:DISCARD =11 INSTR & OPERAND
311 MODF DISCARD ISTREAM OPERAND
32ND PART OF Q/D IMMEDIATE

EXCEPT.ARCK

"SUB/SPEC,J/E.FORK"
"IEK/EACK"

FLUSH.IB

*IBC/FLUSH,VAK/LOAD,IEK/ISTR"

G.FORK

"SUB/SPEC,J/G.FORK"

E,FORK

INHIBIT.IB
INTRPT.ACK
INTRPT .STROBE
IRDC

IRD. 11
IRDO
IRD1

"MCT/MEM.NOP"

"IEK/IACK"
"IEK/ISTR"

"IRDO,CLK . URCC,IRD1,SUR/SPEC,J/A.FORK"

SC-K(.10],PCK/PC#N,HSC/IRD,SUS/SPEC,J/DPO'
'LA-R(DST)&LB_R(SPC),D-LB.PC,VAK/LOAD,Q-IB.DATA,XP),SS-ALU!S
'
“LA-R(SP?)&LB_P(SP!),D&VA-LB,SC-ALU(EXP).FE-LA(E
"MSC/IRD,GK/ID,MCT/ALLON.IB.READ,IBC/CLR.1-5.CDND,PCK/PC+N'

(LNOD) SOHOVIN 3A0J0HIIN WILSAS

"RAMX/G,AMX/RAMX,BMX/LC,ALU/A+B,VAK/LOAD"

VALQ+LC
VALQ+PC

LOAD.IB.11

LONG

"VAK/NOP,MCT/READ,V.NEWPC"

"VAK/NOP,MCT/READ.V,NEWPC"
"DT/LONG"

MEMORY .NOP

"MCT/MEM ,NOP"

MUL,OXT

"SI1/MWUL+,8C.SC~K{.1),BEN/MUL"
"SI/MUL=,5C.5C=K[.1],REN/MUL"

MUL.1XT
MULM,.DONE

MULP.DONE

"D.D.RIGHT2,S5I/MUL=,INTRPT,STROBE"
"Du.D.RIGHT2,SI/MUL+,INTRPT,.STROBE"

POLY .DONE

"ACF/CONTROL,ACM/POLY.DONE"

RETURNO

“SUB/RET,J/0"

RETURN1

"SUB/KET,J/71"

RETURN10

"SUB/RET,J/10"

RETURN100

"SUB/RET,J/100"

RETURN10C

"SUB/RET,J/10C"

RETURNLIOE

"SUB/RET,J/10E"

RETUKN12

"MSC/LOAD.ACC,CC"

RETURN1SB

"SUB/RET,J/12"
"SUB/RET,J/s18"

RETURNIF

"SUR/RET,J/1F"

RETURN2

"SUB/RET,J/2"

RETURN20

"SUB/RET,J/20"
"SUB/RET,J/24"
"SUB/KET,J/3"
"SUB/RET,J/74"
"SUB/RET,J/40"

RETURM24

RETURN3
RETURN4
RETURN40
RETURN60
RETURNG6Y

RETURNS
RETURNS
RETURNF
RETURNI(]

"SUB/RET,J/60"
"SUB/RET,J/61"
“SUB/RET,J/8"
"SUR/RET,J/9"

"SUB/RET,J/O0F"

"SUB/RET,J/R1"

(LNOD) SOHOVIN 3A0J0HIIN WILSAS

LOAD,ACC.CC
LOAD.IB

SET.V

"CCK/ROR"
"CCK/INST.DEF, DT/WORD"
"MSC/SET.FPD"
"MSC/SET.NEST, ERR"

"CCK/C_AMXO"
"CCK/SET.V"

,SUB/SPEC,J/C.FDRK'
IB.D&TA,CLR.IB.COND,PC-PC#N,MCT/ALLO‘.IB.READ
IB.DATA,CLR.IB.COND,PC-PC#N,MCT/ALLOH.IB.READ,SUB/SPEC,J/G.FURK'

18
START,
STOP.IB

"LAB_R(SP1),0.
"LAB.R(SP1),0a
“IBC/START"
"IBC/STOP"

TEST,.TB.RCHK
TEST,TB.WCHK
TRAP.ACCI)

*MCT/TEST.RCHK,VAK/NOP"
"MCT/TEST.WCHK,VRK/NOP"
"ACF/TRAP,ACH/@1"

SPEC
SPECG

WORD

WRITE,DEST

WRITE.G.DEST

"CCK/INST.DEP, DT/BYTE"
"CCK/INST.DEP, DT/INST,DEP"
“CCK/INST.DEP, DT/LONG"

*DT/WOR
’LAB-R(SPI),QK/ID,CLR.IB.COND,PC-PC#N,SUB/SPEC,J/NRD''
"LAB_R(SP1), QK/ID,CLR.IB.COND,PC-PCON,SUB/SPEC,J/NRG

(LNOD) SOHOVIN 3AOJ0HIIN WILSAS

SET.CC(BYTE)
SET.CC(INST)
SET.CC(LONG)
SET.CC(ROR)
SET,CC(WORD)
SET.FPD
SET.NEST,FREK
SET,PSL.C(AMX)

Macro

Branch

"BEN/INTERRUPT"

ACCEL?
ALIGNED?

"BEN/ACCEL"

enable

*BEN/ACCEL"

macros"

3 ,J3/73"
?,J3/73"

"BEN/TB.TEST"
“BEN/ALU"
"BEN/ALU1=0"
"BEN/ALU"

?,d5/717"

ALU1-07
ALU?

BCDSGN?

"BEN/DECIMAL"

?eJ2/2"

c3it?

"BEN/C31"

CONSOLE ,MODE?

"BEN/PSL,.MODE"

D(1)7?

"BEN/MUL"
"BEN/D.BYTES"
“BEN/D.BYTES"

3 ,J4/0E"
3,J4/0D"

"BEN/D.BYTES"

?,J4/0B"

ALU.N?

D.BO?
D.B17?
D.B27?

D.BYTES?
D.NE.O?
Do?
D2=-07
D27

definition

D3=07
D317
D3?
DATA.TYPE?
DBL?

3 ,JS/71B"

"BEN/D,.BYTES"

"BEN/SIGNS"
"BEN/D3=0"
"BEN/D3-0"
"BEN/D3=0"
"BEN/D3=-0"
"REN/SIGNS"
"BEN/D3-0"
"BEN/DATA.TYPE"
"BEN/DATA.TYPE"

EALU.N?
EALU.Z?
EALU?
END.DP1?

“BEN/EALU"®

FPD?

“BEN/LAST.REF"

IB,TEST?
INT?
INTERRUPT,REQ?
IR0.C31?
IR0O?
IR1?
IR2~17

"BEN/1B,TEST"
*BEN/INTERRUPT"
"BEN/INTERRUPT"
"RBEN/ALU"
"BEN/ALU"®
"REN/IR2-1"
"BEN/IR2-1"

LAST.REF?

“BEN/LAST.REF"

MODE.LSS.ASTLVL?

"BEN/REI"
"BEN/MUL"

MUL?

1 ,J4/07"

"BEN/EALU"
"BEN/EALU"
“BEN/END,DP1"

5 ,J3/75"

?,J4/0E"

$,J4/08"
1,J4/08"
31,0376

2 ,J4/07"

3 ,J4/07"
?,J4/08"

3,J4/707"

1,J3/5"

3 ,J4/70D"
3.J3/76"

$,J3/73"

sPREFERED

FORM

(LNOD) SOHOVIN 3AOJ0HIIN INILSAS

.TOC

AC.LOW?
ACC,SYNC?

"BEN/LAST.REF"

PC.MODES?

"BEN/PC.MODES"

PSL.C?

"BEN/PSL.CC"
"BEN/PSL.CC"

PSL.CC?
PSL,MODE?

:,J4/0B"

$,J4/0E"

PSL.N?

“BEN/PSL.MODE"
*“BEN/PSL.CC"

PSL.V?

"BEN/PSL.CC"

3,J4/7"
$,J4/70D"

PSL.Z?
PTE,VALID?

"BEN/PSL.CC"

3 ,J4/0B"

"BEN/TB,TEST"

3 ,JS/O0F"

Q312

"BEN/SIGNS*"

3,J3/73"

QUAD?

"BEN/DATA,TYPE"

RLOG.EMPTY?
ROR?

"BEN/ALUI=-0O"
"BEN/ROR"

7.J4/7"

"BEN/SC"

5C.GT,.0?
SC.NE,O?

"BEN/MUL"

5C?

"BEN/SC"

SIGNS?

"BEN/SIGNS"

SRC.PC?
S8?
STATE(7)?
STATEO?
STATE1=07

"BEN/SRC.PC"
"BEN/EALU"
“STATET=47"
"BEN/STATE3~=0O"
"SEN/STATE3=0"

STATEL1?
STATE2?
STATE3=0?
STATE3?
STATE4?
STATES?
STATE6?
STATET7~47

“BEN/STATE3~0"
"BEN/STATE3=0"
"BEN/STATE3=0"

7,J4/0D"
7,J4/08"

"BEN/STATE3-0"
"BEN/STATET=4"

3,J4/07"

7,J3/3"

$COMP

MODE,

?,J4/0E"
7,J4/0E"

7 .J4/0C"

"BEN/STATE7=4"
"BEN/STATET~4"
"BEN/STATET-4"

TB.TEST?

"BEN/TB.TEST"

VA31=-307

"BEN/PSL .MODE"

$,J5/07"

VA31?

"BEN/PSL.MODE"

2,J5/0F"

7
ZONED?

"BEN/Z"
"BEN/DECIMAL"

1 ,J2/71"

BEN

SRC

(LNODJ) SOHOVIN 3A0J0HIIN WILSAS

NEST.ERR?

FPA CONTROL WORD FIELDS

“

—

EALU

MCTL

CONTROL

—

BRANCH

EALUA

EALUB

ENABLE

INPUT

)

—

V_—);T

EXPONENT

MISCELLANEOUS

PROCESSOR

CONTROLS

)

SCRATCH
PAD

CONTROL

NORM.

waAIT

CONTROL

FPSYNC

NEXT ADDRESS

y .

A 4

BUSA -BUSB

FRACTION

SIGN LATCH

MULTIPLIER

DATA SOURCE

PROCESSOR

CONTROL

OPERAND

CONTROL

REMAINDER

CONTROL
TK-0513

ARRANGED

FROM

ORDER

BITS

LRTOL
CHEXADECIMAL
NAD/=0,9,39,+

ADDREISS

tMICRO

WCRD

DEFAULT

THE

FOLLOWING

s BRANCH

;DEFAULT
=

oo
oo

ENAELE

;SEE

TABLE

FOR

EXPLANATION

NOU bW

[

POV g (I

SIS

LT
T 2722
£
L.
I &L

U«‘U’C{QTUU)D‘QZ

BEN/=C,3,26,D

AMXC/=22,2,34,D

BEMXC,/=0,2,32,D

INPJT

JEALU

JSEL
;SEL

ALy

kALY

(SEL

EALY

sA0D.

COMDITIONAL

JEALU

OINFPUT

;PC NCRTVALIZATION
v REGISTHR
(RESTCRE
ySeEL

EALUC,=2.2,30,0

yEALU

TXTESS
Yo

EALU

COWTRELS

CONSTANT

30(18)

NUTATION

SNOILINIA3AQ AdT7314 WOY TOHLNOD Vvdd

;FIELDS

A-B=i

Ad+E=D2
W3FF=3

yPASS

AM Y

AMX

WMING T

[

AMX

PLUS

BML

VEALU=3FF
*

MCTL/=0,1,28,D

N
2 = =0
N

C N T- 1

START

7 o>

DO OO

X rmor
e Z

EAC/=0,4,24,0D

MULTIPLY

EXFONENT

PCLY

PROCES53R

AR w

EXP

LOAD

GETS

BUS

GET:

U5,

LA_BUS

CETS

EALU

GETS

EALU

GETS

EALU

ER_EALU

LB_BUS,

ERAXK_EALU
A

LA_BUS,

LA_BUS.

LA_BUS

L3_BUS

AR_SALU

LA_BUS

LB_BUS

XR_EALU

LA_BUS.

REG

LB_BUS,

LC.ALL=0F

EXP

PRODUCT

CONTROLS

LA_BUS

LB_BUS

PR_EALU

PR_ZALY

PR&XR_EALU

(LNOJ) SNOILINI43A d7314 INOY TOHLNOD Vd4

~A=C

NOP=0
WAIT=1

tMISCELLANZIOUS CONTROLS

w
wn

;1 LOAD SIGL CF

ERROR

~NIOh

- OTM =z

TDUOUOOULO.

;20LY ADO FOR SICN PROCESSOR
+SET ERRIF BLT FOR RESRVD OPND
JCLEAR RoANLEJER REGISTER
CONDITION

FDR POLY

s INSTRUCTICN

3RANCH

+NORMALIZER

REGESTER

s+ INSTRUCTION BRANCH

—

msc/=G6,3,20,D

—D!
2
oo x oo

STALL

sENABLE

NRC/=3,2,18.0

NOP =2

Si=2
£D=0

SCR,/=0,2,16,0

CPU=0

<SHIFT LEFT
s LCAD BUS A,

;FPA

SCRATCH

sREGISTER

(NORMALIZE)
BUS B

PAD

A4DCRESS

DPR.R=1

;SP2+1 ,PRN+1

R.R=2

;1SP1,SP2

DP=3

i PRN+1,

PRN

CONTROLS

FROM CPU

(LNOJ) SNOLLINI43a 7314 NOY TOYLNOD Vdd

WAIT/=0,1,23,D

INTH=3

DATA

SOURCE

FOR

BUS

NH=5

s INTEGER FRODUCT HI TO
TNSHFL TC B8US A, BUS A
iNSHFH & 2XP TQ BUS A,

PQ=6

;PROD/QUTTH

INTL=7

JINTEGER

NL=4

BUS

PRIZL

A,
BUS

AND

BUS

P/QL
A

B
BUS

10=8

;1D

yIBUF

ID.RE=0A

R=0B

71D
tRA

FAL.X=0C

yHARDWARE

DETERMINED

FAL.LH=0D

yFALUL

3Us

FALUH

BUS

FaL.HL=CE

tFALUH

5US

FALUL

BUS

LTI

BuUs
BUS

i FRACTION

;s LCAD

BR1
ARH

BUS

A,
A,

BUS
BUS

; LOAD

AR:,

BR?Y,BR

s LOAD

BRS
ARD2
BRC,

yLOAD

AR,

‘HARDWARE

JOUTPUT

;OUTPUT

CONTROLS

DEITERMINED

;SIGN

LATCH

ySIGN

LATCHES

3SIiGN

ADD/SUB

CINTROLS

VBUS A(13) TZ
yIF SUB,
SA<-

TRESULT

T0O
7O

ARO

yLCAD

y LCAD

RBE
RB

PROCESSOR

; LOAD AR,

i LOAD

w P

BUS

RIEGISTER

TO
TO

;LCAD

DATM

VIS &1

AR=0

BUS

LRk=2

FADC/=2C,4,8,0D

UNCHANGED
SA
NOT

;

ELSE

(LNOD) SNOILINIZ3a 1314 WOY TOHLNOD Vdd

BSC,/=8,4,12,D

1SE

;SA

BuS 3(35)

T3 SA

NOP =0

s LOAD REMAINDER

LD.3R=1

NCP=O

s LOAD MULTIPLICAND

MC=1

1LOAD UPZZR HALF OF MULTIPLICAND

Mct1=2

MC.P0=4

LOR.R=8

0w HALVES

LOAD

; LOAD

ALL

T LOAD

MZ0=5

LOwEx

RALF OF MULTIFLICAND

F0OR

R-R

LOAD M'CLND INTEGESEMULTIPLIER HIGH FRACTION

NCL.WP1=0A

:LOAD MULTIPLIC:IND

L1208

:LOAD LOLZR HALF OF MULTIPLIER
:LOAD MULTIP_IER, HIGH FRACTION

MPO=0D

MP1=0E

;CONTROL

INIT=0F

% ok ok o ok 3k ok 3k sk ok sk ok KK B K ok K

INITIALIZATION

Kk R ok KK R R Rk s x Lk ok R Rk
»

.
#*

BEN

TABLE

*
*

o wr k k ok A o oK K K

INTEGER

s LOAD MULTIFLIER

MP=0C

tMULTIPLIER CPERAND CONTROLS

OPLD/=6, 4,0.D

T BEN

TO S8

TREMAINDEZR RECISTER CONTROLS

LRR /=0,

SA
XOR »

sSB

B(1n:

K XK K K

kR ok

R R ROK R OROK e K K kR

UADRS<C>

(LNOD) SNOILINIZ3A a13i14 NOYH TOYLNOD Vdd

;BUS

-8US A(15;

IRERD

(OPCODE

BRANCH)

SWR H

SwWR

(NOOMALIZATION

RSV H

B=0

A=0

(ZERQES

POLY DONE L

CPSYNC

(A OR B)=0 H

SUB=*ED<2 H

SJUS+S0YBLEXEC>8

‘6

WMUL/DIV

DONE

[PR=0+PR<9>]

PF<8>

(OVER/UNDERFLOW

AR_PROD
BFCRK

BUS_O

CFPU_ANSH
CPU _ANSL
EALU_PR

MACROD

H
H

FLOAT

AND

SHIFT WITHIN RANGE)

RESERVED OPERANDS)

(SYNCHRONIZATION
H

WITH CPU)
(EXP.

DIFF.)

POLY)

DEFINITICNS"

"BSC/PQ,FADC/AR"

WMSC/IR1,NAD 100, WAIT/WAITY
"BSC/NL,EALUC/K3FF, AMXC/FR"

SENXC/NK ., 55C . NH, AMXC/PR, EALUC/A"

“BMXC/NK.33C,/NL, AMXC/PR,EALUC/A"

ELLU_PR-XR

A"
"AMXC/PR,ZALLC/
"AMXC/PR,SMAZ, XR,EALUC, A-B"

ERCH
FoALIRD

"4CR/R.R. FADC/R1,MSC/IRO.ESC/R.SGNC/LDS,DPLD/LDR.R.EAC/LDAB“

FI57¢NC

IR0

LA&FR_LB

LagPR_PR-K
LASSA_O
LA_0

La_LB
LA_PR

LA_PR+K
LA~F"—\ ~K

LS_C

LB_FRr

wricc/cer

"FRSYNC/F=57

"NAD/OAS.E LJC/3,FeDC/LD,SGNC/A.RES,BSC/NH, OPLD/INIT,MSC/RR.O"

A, SAC/PR. LAY
xC/LUB,EALUZ/
"BSC/NH,
WAMXC/PR,EALUS,/ A8, BWAC/#30,BSC/NH,EAC/PR. LAY

"EALUC/KJ F,F“KC,NK,EBCNH,EAC/LDA.SGNC/A.RES.AMXC/PR“
WEALUC/KI3EF, EVAC, in, B3C,/ N, EAC/LDA, AMXC/PR"

KO LB ERALUC/A,BSC/NH,EAC/LDAY
WAMXC/LB.
"ANXL/PR,uA JC’A BN XC/LB, dSC/hH.EAC/_DA"

“AHXC/PR

A LC /AR, ENXC/#20,B5C/NH, EAC/LDA"

wANK /“R,'aLLL,A 8,EMXC,s60,BSC/NH,EAC/LDA"

WEALUC/KIZF,2/ AC /NK,BSE,/NIL, EAC/LDB,SGNC/LDSB!
"Amxc/pa,aAL\ CA, emx:/LB ESC,/NH,EAC/LDB"

(LNOD) SNOILINIZ3A d1314 NOYH TOYLNOD Vdd

FLGAT

SwR H

"TRANSFER

IRBR1

HR!

"AMXAC/PR,
XA LUCl/A~B,BMXC,/#80,BSC/NH,EAC/LDB"

LCAD.AD

"FADC/AR, ;) : I‘F(-OI)
“FADC/ARY
,E A;/L-A.SGNC/LDSA.OPLD/LDR.R“

B
LCAL.

"FADC/BR
,EX L

LOAD.BO

“FADC/BRu.C :J_n/m.gou

O
LCAD.

“FADC/BR1.EAC/LDE,3GNC/LDSB,0PLD/MCI.
. MP1TM

LOAD.COEFH

"BSC/1D,=2ZC.BR1,EAC/LDB,S5GNC/LDSB"

LOAD.CDEFL

"BSC/ID,FAL CEROTM
"SGNC/LD5,* ADC/R1,EAC/LDAB,OPLD/LDR.R"

LCAD.MR

LCAD.2D8B
MCO_NSHFL

MC1_NSHFH
MIONT

MC_EgR
MINIT

"BSC/R,SCR. DF%.R,FADC/RO"
"BSC/NL,CFLD
'MCO"
"BSC/NH,DPLD
RKCi"
CMITL/CNT

“8SC/FAL.HL,FADC/B,0PLD/MCY
"OQPLD/INIT"

NOFP

"BEN/O"

NCIML. PQ

"EAC/LDP?, SL\C/A.n:S,,JC/NH,MSC/CC,EALUC/A+B,AMXC/PR.BMXC/NK“

NCRM.SUM

LD2.5GNC/LDSB,0PLD/MP"

"EAC/LDPR,
= UNC/ALRESLVESC/WH,MSC/P.ADD,EALUC/A+B,
AMXC/PR, BMXC/NK*

NR_AR

"FADC/A, 550 "AL.HL,NRC/LD“

NR_ER

“FADC/B,SVC/

ALVHL,NRC,
LD

NR_FID

“FADC/A.S,L5C /FAL.X,NRC/LD"

NR_PRCD

“BSC/PQ,‘TC

NP _QulT

"8SC/PQ,

SREINE

STLYLOADD

"MSC/P.ADD

PR_0

"AMKC/LB,VJJW

PR_CLND

TAMXC/COT

FR_K

"BMXC/”SJ.:

LUC/A-B,EAC/LDPR"

PR_LA

YAMXC
/LA . vaLes

FR_LA+WK

"AMXC/LA
L ED ;u;

+5,EVXC,#80,EAC/LDPR"

PR_LA+LB

"AMXC/LA
L BT

,EALU\./ r\”.) pr/LDpR"

PR_LA+NROM

"ANXC/LA,
L

PR_LE

"AMXC/LB.ZALUZ

\n,EALUC/A 3,EAC/LDFR"

A,EAC/LDFR"

(LNOD) SNOILINIZ3A @1314 WOY T0YLNOD Vdd

LB_FX-K
A1
LCAD.

MACRO

DEFINITIGHS

"ANMXC/LB. E4LUC/A+B, BUMXC/#EO0,EAC/ LDPR"
"ANMXC/ LS. SALLC, A~E, EMXC/#80,EAC/DPR"
£iNs XR,EALUC,/A-B,EAC/LDPR"
L
“AMXC/LB.
" AMXC/PR 3al /250 .EALUC/A+B,EAC/LDPR"

PR_LB+K
PR_LE-K
PR__LB=XR

PR_PR+K

ONK L, EALUC/A+B,EAC/LDPR®
»ANNC /PR, ST

PR_ CR+NROM
FR_ PR+EXR

=
Y AR XC/PR.

PR_PR-K

.S
YAMXC/PR

PP_UNDR

"FAC/LDDK

a0 ‘JIR/ WIFF"

A.%”/LB EMXC/XR,EALUC/A+B"

FR_ “R+LB

“LRn/LD.R?"

&R
_ X

RSV

"MSC /10"

SA_ SA. XGR.SUB

SA_ SR

"SGNC/A. SNA
R
. XY
"SGNC/A22
5
"SCGNC/A.
"SGNC/A. &5

S¥_ SA

"MSC/LES
4"

SA_ SA. XCR.SX

SA_ cB

xn,EALUV/A+B,EAC/LDPR“
AC/a8) ,EALUC/A-B,EAC/LDPRY

‘

wAl

"WAIT/WAITY
"ANMXC/LA, EALUC,/A,EAC/LDXR"

XR_ LA

"BRANCH

MACRO

DEFINITIONS®
8E N/"n

{A.0R.E).O?

CPSYNC?

"BFN/4"

ERECR?

"BEN/6"
“BEN/7"

ExP.CIFF?

"SEN/S"

.OONE?

FLIAT?

MUL.CONE?

"BEN/6"

“D”CDE”

"BEN,’1

SHR"

"BEN/Q"

ZER3ZS?
POLY.DONE?

"BEN/3"

(LNOD) SNOILINIZ3A a73id WOY TOHLNOD Vdid

TRANSFER

CHAPTER 4

CONSOLE

CIB Q-BUS REGISTERS (LOWER)

IDBUS

QBUS

ADDRESS

—

173000

ROM 0 I

173002

ROM 1 l

173004

SPARE I

1 R/O

ROM 1 DATA <15:0>

*ln/o

SPARE

ITIMEOUT

—

173006

D DATALO |

—

173010

ID DATA HI I

SPARE L

173014

RX DONE {0

ID DATA <15.0>

]R/O

ID DATA <31:16>

1R/O

SPARE

173016

TX READY

lo
»

DNE [g

o|RX

ROM 0 DATA <15:0>

0 lam' 0
TX

]nmeom
0

of RW
0

ofrm

BASE ADDRESS ON M8236:

W1 INSTALLED — 1730XX

W1 REMOVED — 1630XX
TK-0204

CIB Q-BUS REGISTERS (UPPER)

1D 8US
ADDRESS

QBUS
ADDRESS

(05}

173020 TOID LO I

(05)

173022 TO ID HI I

173024 FMID LO r

{07)

173026 FM 1D HI l

l RAW

T0 1D <31:16>

I R/O

FM 1D <15:0>

l R/O

FM 1D <31:16>

1D C/S ‘ 1 lINVERTED AND READ ONLY

173030

J RW

TO 1D <15:0>

ADDRS <5:
ID DDRS

<505

RCV ID ADDRS <5:0>

)

MAINT

CYCLE

RCV

WRITE

WRITE
QBUS
ADDRESS

wor

T DT T

v [

RET

INTR

T T LTI
|

RESET

ENAB | pisaB

UPC12

HLT

REQ

STPD

CEED

SBC

FREQ

CLK

NOP

PRO-

SsTS

<1>

ROM

<0->

vor e AT IATTTT AA LT
15

173036

V-BUS |

AUTO RST|

~ CNSL

HALT

DNE

CMND

STATE

V BUS SER CHNL <7:0>

LOCK

BOOT

RDY

RUN

FLPY

MAINT | sTAR | somm | FREQ

CcPU

LT LT ]

[

REMOTE

I I

1
cPT

cPT

SLFTST |

CLK

I 1 J RIW
v

cPT

LOAD
TK-0205

EXPLANATION OF VERSION NUMBERS FOR CONSOLE BOOTING

When

WCS

has
been
status, for

revision
VER:

The

PCS=@1

PCS

reloaded,
example:

WCS=0E-10¢

code

refers

control

store

(ROM).

contains

two

PE}

refers

FPLA=@E

the
The

numbers.
to

the

The

console

terminal

CON=V@7-p@#-L

revision

number

WCS

(writable
primary version

prints

KE780

out

PRESENT

the

programmed

control
store)
number
(in this

code
case,

the

FPLA
number
that
is
required
for
this
WCS
version.
The secondary version number
(in this case,
18)
refers
to the version of WCS that has been loaded.

The FPLA (field programmable logic array) code refers to the FPLA
chip revision that is currently installed in the VAX-11/788 CPU.
This chip causes
the microprocessor to
retrieve microwords from
WCS instead of from PCS when specific locations are addressed.

The

CON

console
Two

(console)
software

types

match

the

the WCS
mismatch

FPLA

code

that

mismatch

has

may

revision,

revision does
is fatal.

refers
been

occur.

the

not

the

loaded
If

console

match

revision

into

the

WCS

program

the

PCS

number

LSI-11

revision

issues

revision,

the

memory.
does

not

warning.

however,

the

CONSOLE HELP FILE

UVAX-11/780

SYNTAX?

CONSOLE

ALL

HELF FILE

COMMANDS ARE

‘EXAMINE’ ANDIN
/P’

March

29,

1982

CARRIAGE

RETURN.

“DEFOSIT’ < QUAL> SWITCHES FOR ADDRESS
= FHYSICAL MEMORY(THE DEFAULT)

/v’

VIRTUAL

/1’
/G’

=
=

INTERNAL (FROCESSOR) REGISTERS
GENERAL REGISTERS O THRU F(RO

‘/VB’
/1D’

=
=

VBUS REGISTERS
IDRUS REGISTERS

‘EXAMINE’

<ADDR>

REV.

TERMINATED BY

AND

SFACE

MEMORY

THRU FC)

<QUAL> SWITCHES FOR DATA-LENGTH

‘DEFOSIT‘

/B’
/W

BYTE

BITS)

WORD

BYTES)

/L7
‘/Q7

=
=

LLONGWORD
QUADWORID

(2
(4

WORDS)
WORDS)

IS A <NUMBER>»» OR ONE OF THE FOLLOWING SYMROLIC AIDRESS
‘ROsR1IsR2r.sssssssR11sAFsFPsSFsFC’
(GENERAL REGISTERS)
‘FSL’

FROCESSOR

X’

LAST

STATUS

WORID

ADIRESS

= ANDRESS FOLLOWING ‘LAST’(x) ADDRESS
ot
s
= ANDRESS FRECEEDNING ‘LAST (k) ADDIRESS
‘e’
= USES LAST EXAMINE/DEPOSIT DATA FOR ADDRESS
“NUMBER: = STRING OF DIGITS IN CURRENT DEFAULT RADIX»
OR STRING OF DIGITS FREFIXED WITH A DEFAULT RADIX
QUERRIDE

(%0

FOR

OCTAL>»

FOR

~ROOTS

‘ROOT
‘BOOT

HEX),

‘CLEAR

STEF”

‘CLEAR

SOMM’

‘CONTINUE
TDEPOSITL
/< QWITCH(ES) -1
“ENABLE

SADDR>

<DATA:

CFPU

FROM

DEFAULT

DEVICE

MICRO-MATCH REGISTER.
~I8SUES A CONTINUE TO THE ISF
~DEFOSIT «DATA: TO <ADDRESS:

~-ENABLES CONSOLE SOFTWARE TO ACCESS
FLOPFY DRIVE 1 ON THOSE SYSTEMS WITH

DxX137

IUAL
EXAMINEL/-SWITCH(ES)
»]
‘EXAMINE

THE

-TAKES THE FIRST THREE ALFHANUMERIC
CHARS OF <DEVNAM>»s
AND EXECUTES THE
INDIRECT FILE ’<DEVNAM:BROO.CMD’
~ENARLE NORMAL (NO STEF) MODE
~CLEAR ‘STOF ON MICRD-MATCH’ ENAERLE.
NOTE: ID REGISTER 21 IS THE

<LEVUNAM>
-

<ADDR>

IR~

FLOFFIES.

~-DISFLAY

CONTENTS

~EXAMINE

INSTRUCTION

REG(IR).

DISFLAYS

OF~-CODEy

SFECIFIERy

EXECUTION

FOINT

COUNTER
-HALTS

HALT”
“HELF
“INITIALIZE
LINKS

THE

ISF

~FRINTS THIS FILE
~INITIALIZES THE CFU
~CAUSES CONSOLE TO BREGIN
LINKING.
PROMFT

CONSOLE

COMMAND

FRINTS

INDICATE

REVERSED

LINKING.

ALL
COMMANDS TYFED BY USER WHILE LINKING
STORED IN AN INDIRECT COMMAND

ARE

FILE

FOR

LATER

TERMINATES

‘LOANL/START
! < ADNR:]

<FILENAME:-

-LOAD

FILE

AIDRESS
“LOAD/UWES
NEXT

<FILENAME

“NUMBER:7

-LOAD

~NUMBER>

FILE

EXECUTION.

LINKING.(SEE

MAIN

MEMORYr,

<ADDRX:

SFECIFIED

STEP

CONTROL-C

FERFORM)

CYCLES

IF
TO

STARTING

SPECIFIED
WCS

ARE

DONE»

TYPE

CONSOLE HELP FILE (CONT)

STEF DEFENDS

LAST

‘SET

STEF’

COMMAND
~-EXECUTE A FILE OF LINKED COMMANDS
FREVIOUSLY GENERATED VIA A ‘LINK’

‘FERFORM’

.
COMMAND

‘QCLEAR

<ADDRESS:‘

“RERQOT”

‘REPEAT

<ANY-CONSOLE-COMMANI:”

SLOW’

/SET

CLOCK

‘8SET

CLOCK FAST”
CLOCK NORMAL
ey COFTION:]"
DEFAULT =OFTION>Ls

‘SET
“SET

-DOES A QUAD CLEAR TO <ADDRESS:,WHICH
IS FORCED TO A QUAD WORD BOUNDARY.,
(CLEARS ECC ERRORS)
-CAUSES A CONSOLE SOFTWARE RELOAD
-CAUSES THE CONSOLE TO REFEATEDLY
EXECUTE THE <CONSOLE-COMMAND:» UNTIL
STOFFED RY A CONTROL-C (7C).
~-SET CFU CLOCK FREQ TO SLOW.
-SET CPU CLOCK FREQ TO FAST
~SET CPU CLOCK FREQ TO NORMAL
~SET

CONSOLE DEFAULTS
<OFTIONS> ARE?
OCTAL yHEX»FHYSICAL
s VIRTUAL » INTERNAL
GENERAL » VRUS» IDBUS y RYTE » WORD » LONG y QUAL
~FUT <NUMBER:> INTOQ CONSOLE RELOCATION
REGISTER. RELOCATION REGISTER IS
ADDED TO EFFECTIVE AIDRESS OF
FHYSICAL ANIN VIRTUAL EXAMINES AND

NOTE:

RELOCATION? <NUMBER’

DEFOSITS.
~SET ‘STOF

/SET

SOMM

SET

STEF

BUS”

~ENARLE

‘SET

STEF

INSTRUCTION’

~ENABLES

SET

STEF

STATE”

~ENARLE

SETY

TERMINAL

FILL {<NUMBERX:"

TSHOMW
“SHOW

VERSION'

MICRO-MATCH’

SINGLE

RUS

SINGLE
SINGLE

CYCLE

ENAEBLE

CLOCK

INSTRUCTION
TIME

STATE

MOLE

MODE

CLOCK

MODE

~SET FILL COUNT FOR # OF BLANKS
WRITTEN TO THE TERMINAL AFTER <CRLF:
~FUT CONSOLE TERMINAL INTO ‘FROGRAM
1/07 MODE
-SHOWS
~SHOWS

CONSOLE AND
VERSIONS OF

CFPU STATE
MICROCODE

AND

CONSOLE
‘START

<ADDRESS:’

~INITIALIZES
TO

FCs»

“TEST’
‘TEST/COM’

~RUNS

“UNJAM

~-UN.JAMS

‘WS

-CALL.S

THE

ISSUES

CFU,»DEFOSITS<ANDRESS:
CONTINUE

THE

ISF.

MICRO-DIAGNOSTICS

~LOADS

MICRO-DIAGNOSTICS»

AWAITS

COMMANDS

THE

CS1.

(FOR

SRI

MICRO-DEBUGGER.

DERUGGER

FLOFFY

ELSEs

MUST

"FILE

WCS
BE

NOT

MICRO-

INSERTED

FOUND®

ERROR.

DEBUGGER HELFs INSERT WCS DERUG
THEN TYFE ‘EWCSMON.HLF')

FLOPFYy
‘WAIT

DONE-

~WHEN

EXECUTED

COMMAND
COMMAND

)]

FROM

INDIRECT

FILEs» THIS COMMAND WILL CAUSE
FILE EXECUTION TO STOF UNTIL?

A ‘DONE’ SIGNAL IS RECEIVED FROM
THE FROGRAM RUNNING IN THE VAX
(COMMAND FILE EXECUTION WILL
CONTINUE)» OR
THE

VAX-11/780

ATOR

TYFPES

HALTSr

OFER-

CONTROL-C

(~C

COMMAND FILE
.
TERMINATE)

EXECUTION

WILL

TP (CONTROL-F)

-FUT CONSOLE TERMINAL INTO ‘CONSOLE
1/0° MODE
(UNLESS MODE SWITCH IN ‘DISABLE")

@<F ILENAME: *

~FROCESS

INDIRECT

COMMAND

FILE

CONSOLE ABBREVIATION RULES

UAX-11/780

CONSOLE

THIS FILE

SHOWS

ABBREVIATION

THE SHORTEST

REV-&

RULES

SHORTEST

COMMAND

ABBREVIATION

RECOGNIZED

“BROOT
‘CLEAR

SOMM’

‘CLLEAR

STEF”

‘cL

TENARLE

S§°

<ADDRESS:

‘I

< DATA:~

ZADDRESS:

"EN

I1X137

‘EXAMINE

s0¢

‘CL

"CONTINUE
‘DEFOSIT

‘E

~ADDRESS:”

<DATA:‘

DX1%’

<ADDRESS:”

THAL T

‘HE

HELF

"INITIALIZE'

‘LINKY

‘LOAD
NEXT

12-AFR~-79

UNIQUE COMMAND AND QUALIFIER STRINGS.

<FILENAME:’
<NUMERER:’

‘L
‘N

‘QCLEAR

<ADDRESS:

‘Q

< CONSOLE-COMMANL:“

‘R

"REROOT
‘REFEAT

<FILENAME:
<NUMBER:’

TFERFORM

<ADDRESS:

‘RER’

‘SET

CLOCK

‘SE

F’

“SET

CLOCK

SLOW’

‘SE

§°

‘SET

CLOCK

NORMAL
‘

“SE

N’

‘SET

RELOCATION?
- NUMBER:

‘SE

Ri<NUMBER:"

‘SET

SOMM’

“SE

§0°

‘SET

FAST”

<CONSOLE~COMMANI/

STEF

RUS”

‘SE

‘SET

STEF

STATE”

‘SE

‘SET

STEF

INSTRUCTION-

‘SE

I’

SET

TERMINAL

FILL?!<NUMEBER:‘

“SE

Fi<NUMERER:"

'SET

TERMINAL

FROGRAM’

‘SE

PR’

‘SET

DEFAULT

‘SE

OPTION-LIST:’

<OFTION-LIST>’

S GHOW
‘SHOW

B’
§”

fan

VERSION’

‘START

‘SH

<ADDRESS:’

‘S

‘TEST”

-y

‘UNJAM

‘WAIT

‘WA

DONE-

v’
<ALDDRESS:

‘WCS”

‘@ FILENAME:
"

‘@<F ILENAME:/

QUALIFIERS

SHORTEST

ABEREVIATION

/RYTE

/WORD

/LONG

/RUAT

/0CTAL

/HEX

/PHYSICAL

/VIRTUAL

/INTERNAL

/GENERAL

/VRUS

/VR

/IDBUS

/10

/WCS

/WC

< NUMBER~
/NEXT

/NINUMBER-

/COMMAND

/START
! <ADDRESS >

/5!

ADDRESS:

RECOGNIZELD

ERROR MESSAGE HELP FILE

12-AR-79

REV-4

'UAX-11/780 ERROR MESSAGE HELFP FILE

THIS FILE LISTS ALL THE FOSSIRLE CONSOLE ERROR MESSAGES, INDICATING
CAUSE» AND FOSSIELE CORRECTIVE FROCEDURES (IF NOT SELF-EXFLANATORY)
SYNTACTIC

ERRORS

?/<TEXT-STRING:’

INCOMPLETE

!
!

PITEXT-STRING:

TFILE

INCORRECT

CONSOLE

COMFLETE

IS NOT RECOGNIZER

COMMAND

VALID

IS NOT A

COMMAND

THE <TEXT-STRING:>
AS

NAME ERR

7IND-COM

THE <TEXT-STRING:

A “FILE-NAME: GIVEN WITH A COMMAND
CAN NOT BE TRANSLATEL TO RADSO.
(<FILE-NAME> IS INVALID.)
THE CONSOLE DETECTED AN ERROR IN THE
FORMAT OF AN INDIRECT COMMAND FILE.
FOSSIBLE ERRORS ARE: 1) MORE THAN 80

ERR

CHARACTERS IN AN INDIRECT COMMAND LINE
OR
2) A COMMANI' LINE DID NOT END
WITH A CARRIGE RETURN AND LINE FEED.
COMMAND-GENERATED'
TFILE

TNO

NOT

CPU

PCFU

NOT

ERRORS

A <FILE-NAME: GIVEN WITH A ‘LOAD’
OR ‘@’ COMMAND [OES NOT MATCH ANY
FILE ON THE CURRENTLY LOADED FLOFFY
nISC. CAN ALSDO BE GENERATEDl RY
‘HELFP’»“BOOT’» OR AN ATTEMFTED WCS
LOAD IF HELF FILEy BOOT FILE, OR WCS
FILE IS MISSING FROM FLOFFY,

FOUND

RESFONSE

CONSOLE WAIT LOOF,
COMMAND' ARORTEL

CONSOLE TIMED-OUT WAITING FOR A
RESPONSE FROM CFU. (RETRY. INDICATES
FOSSIRLE CFU-RELATED HARDWARE FAULT.)

!
!

A CONSOLE COMMAND REQUIRING ASSISTANCE
FROM THE CFU WAS ISSUED WHILE THE CFU
WAS NOT IN THE CONSOLE SERVICE LOOF.

]

?CPU

PCANT

CLK

STOF»

DISARLE

COMMAND

BOTH FLOFFIES,
FUNCTION ARORTED

FLOFPY-GENERATEL'

?FLOPFY ERRy

ERRORS

CODE=X

(HALT

CFUj

RE-ISSUE

COMMAND.)

A CONSOLE COMMAND THAT REQUIRES THE
CFPU CLOCK TO BE RUNNING WAS ISSUED
WHILE THE CLOCK WAS STOPFED.
(CLEAR STEF MODE$; RE-ISSUE COMMAND.)

ARORTED

!
!

AN ATTEMPT
THE REMOTE

WAS
AND

MADE TO DISABLE
LOCAL FLOFFY.

EOTH

THE

CONSOLE

AN ERROR.
(CODES
CODE=1

CODE=2
CODE=3
CODE=4

FLOFFY

CODES

ARE

DRIVER
AS

DETECTED

FOLLOWS:

ALWAYS FRINTED IN HEX RADIX)
FLOFFPY HARUWARE ERROR
(CRCyPARITYSETC)
FILE NOT FOUND

FLOFFY DRIVER QUEUE OVERFLOW
CONSOLE SOFTWARE REQUESTED
AN ILLEGAL SECTOR NUMBER

ERROR MESSAGE HELP FILE (CONT)

PFLOFFY

PNO

NOT

BOOT

PFLOFFPY

READY

FLOFFY

ERROR

THE

BECOME

!
!

CONSOLE ATTEMFTED TO
FLOFFY THAT DOES NOT

ATTEMFTING A

WHILE

SEI

THIS

(ACTION

EROOT

PINT-REG

ERR

CONSOLE

FLOFPY

FAULT,CODE=XX

MESSAGE

MICRO-ERROR

THE

CODE

THE

RANGE

‘X’

THE

CFU.

VIRTUAL

ERROR

MICRO-ROUTINE.

ERROR

WITH

BIT

EITS

CFU

: CFU FAULT-GENERATED ERRORS @

THE

STACK

]

PINT-STK

INVLD

OCCURREI.

CPU

ERROR

WAS
OR

ACCESS

NOT

CODES.

RETURNED

CAUSELD

MANAGEMENT
A

ONE

THE

RYTE

ROUTINE,

ASSIGNMENTS?

VIOLATION(RITS

RIGHT)

FAULT

FTE

MODIFY

NUMEERED

REFERENCE

INTENT

VIDLATION

SHOULD

HALTED

WAS

ERROR.

DEFOSIT

BIT

FROM

ATTEMFP-

ILLEGAL

WAS

RETURNED

THRU

AFTER

INTERNAL

THE

MEMORY
‘XX’

FOLLOWING

WRITE

]

WHILE
AN

THIS

THAT

THE

LENGTH

CFU

REQUEST.

ERROR.)

CFU

EXAMINE
IN

THE

DUMFED

RECOGNIZED

CODE

=
RIT

WHILE

(RETRY)

MICRO-ERROR

RETURNED

THE

CAUSE

OCCURRED

A
VALID

PRINTELD.

UNRECOGNIZED

THE

ARE

WILL

CONSOLE

REFERENCE

]

DEPENDANT

BOOT.

QCCURRED

(RETRY,)

DETECTED

REGISTERS

WAS

FAILED

EBOOT FROM
CONTAIN A

CONSOLE

SERVICING

ERROR

ADDRESS

PHEM--MAN

EBOOTING.

ERROR

(FROCESSOR)

CODE=X

DRIVE

WHEN

MICRO-ERROR

TING

PMICRO-ERR»

FLOFFY

READY

BECAUSE

MARKED

IGNORED

THE

INTERRUFT

INVALIID.

PCPU

DBLE-ERR

HLT

CHECK

OCCURRED

MACHINE

CHECK

)

HANDLEDy

MACHINE

CAUSING

THE

]

30-3F (HEX)3 DATA
MACHINE CHECK .)

?PILL

I/E

VEC

‘DNOUBLE

THE

EXCEFTION

CFU

ERROR’

HALT.

DETECTED

REFORE

HADI

CFU

EXECUTE

(EXAMINE

INDICATES

BEEN

ILLEGAL

IDI

CAUSE

REG
OF

INTERRUPT/

VECTOR.

?NO

USR

WCS

CFU

DETECTED

VECTOR

]

EXISTS,

TED

USER

INTERRUFT/EXCEFTION
WCS

AND

USER

WCS

[ p——

I
1

PCHM

ERR

CHANGE

FROM

MODE

THE

INSTRUCTION

INTERRUFT

WAS

STACK,

ATTEMP-~

ERROR MESSAGE HELP FILE (CONT)

INT

THIS

PENDING

IS NOT ACTUALLY AN ERROR,

EBUT

INDICATES THAT AN ERROR WAS FENLING
AT THE TIME THAT A CONSOLE-REQUESTED
HALT WAS PERFORMED. CONTINUE CFU TO

CLEAR
TMICRO-MACHINE

TIME

INTERRUPT,

INDICATES THAT THE VAX-11/780 MICROMACHINE HAS FAILED TO STROBE INTERRUPTS WITHIN THE MAXIMUM TIME PERIOI

OUT

ALLOWED,

VERSION

MISMATCH

PWARNING-WCS

PFATAL-WCS

PREMOTE

THE MICROCODRE IN WCS IS NOT COMPATIELE
WITH THE FFLA. THIS MESSAGE IS FRINTED
ON EACH ISF START OR CONTINUE,BUT NO
OTHER ACTION TAKEN BY CONSOLE.
!

ERRORS

RESTARTING CONSOLE

FLOPFYs

THEN TYFE

THE MICROCODE IN FCS IS NOT COMFATIELE
WITH THAT IN WCS. ISP START AND CONTINUE ARE LRISAELED BY CONSOLE.
PRINTED WHEN CONSOLE MODE SWITCH
ENTERS A 'REMOTE’ FOSITION, AND THE
REMOTE SUFPFORT SOFTWARE ROUTINES ARE
NOT INCLUDED IN THE CONSOLE.

ACCESS NOT SUFFORTELD

CONSOLE

PR-BLKD

& FPCS VER MISMATCH

PUNEXPECTED TRAF

MOUNT

FFLA VER MISMATCH

CONSOLE-GENERATED

PTRAF~4y

ERRORS

TRAF.

THE CONSOLE TOOK A TIME-QUT
CONSOLE WILL RESTART.

CONSOLE TRAPFED TO AN UNUSED VECTOR.
CONSOLE REROOTS WHEN ~C TYFED.

~C!

!
!

CONSOLE’S TERMINAL QUTPUT QUEUE
BLOCKED. CONSOLE WILL REEOOT,

CONSOLE REMOTE ACCESS HELP FILE

UAX-11/780
TENABLE

CONSOLE

REMOTE

TALKS

ACCESS

BETWEEN

“ENARLE

ECHO~

"ENABLE

LOCAL

COFY’

"ENARLE

LOCAL

CONTROL

‘ENABLE

CARRIER

‘DISARBLE
‘DISARLE

ECHO”
LOCAL

‘DISABLE

CARRIER

LOCAL

OTHER.

CONTROL-F

-CAUSES

CHARACTERS

OFEN

FILEy

TALK

MODE

THE
70

"DISARLE
THE

CARRIER

INTERFACE.

DIRECTORY

FIRST.

DIRECTORY

THE

CARRIER
AN

LOCAL
IS

NOT

SEARCHED

ONLY)

SEARCHED

ATTEMPT
FLOFFY
FOUNDy
FOR

FILE.

ATTEMFT

FOR

ONLY.

FILEs

WILL

LOCAL

FLOFFY’

OFEN

DIRECTORY

ATTEMFT

FILE

DETECTED.

ONLY)

FLOFFY

REMOTE

WHEN

TYFED IN TALK MODE.
RECEIVING COFY OF

PRINTING

FLOFFY

LOCAL

DIS-

TERMINAL.

LOST’

INHIBIT

OFERATION

FILE

ATTEMFT

REMOTE

LOSS

OFERATION

'REMOTE’

POSITION(S).

THE

“?CARRIER

FILEy

THE

SEARCHED

FROM

FROTOCOL
A

~ALLOWS

REMOTE

DETECTED

THE

FLOFFY’S

FLOFFY‘-ON

FLOFFY’

KEYS

TALK.

TERMINAL.

WHEN

‘REMOTE’

ANIl
REMOTE

FROTOCOL
A

OFEN

FRINT

REMOTE

CONSOLE

’“—(AFFECTS

OF
"ENAELE

FRINTED

OF CHARACTERS
TERMINAL FROM

SEARCHED

THE

REMOTE

IS
TO

ERE

TO
‘DISARLE

MESSAGE

WILL

FLOFFY

TYFED

COMMUNICATION

TERMINAL.

ARE

TERMINATES

CONTROL-F

CARRIER

-(AFFECTS
TO

LOCAL

CONSOLE

~INHIRITS ECHO
~-IISABLE LOCAL

LOST

‘DISABLE

REMOTE

TERMINAL

SWITCH

“-CAUSE

ERROR‘-CAUSES

FLOFFY

26-JUL-78

TERMINAL

OF OUTFUT BEING SENT TO REMOTE TERMINAL.
‘-ALLOWS LOCAL TERMINAL TO CONTROL SYSTEM WHEN

QUTFUT

LOCAL

ONE

REV-02
TO

RE
RACK TO THE ORIGINATING TERMINAL.
THE LOCAL TERMINAL TO GET A COFY OF

ECHOED
~CAUSES

L0SS
COPY”

ANDN

ARLEDl
ERROR

TERMINAL

STRUCK

CONSOLE

‘ENAEBLE

HELF FILE

-ESTARLISH

THE

ONLY

THE

SEARCHED.
ARE

‘REMOTE’

OFEN

DRIRECTORY
THIS

MUTUALLY

FILE.

COMMAND

EXCLUSIVE.

FLOFFY

MICRODEBUGGER HELP FILE

MICRO-DERUGGER
DERUGGER

'E/F

HELF

COMMANDS

FILE

(ALL

REV

TERMINATED

<ADDRESS:-‘

‘E/ID

<ADDRESS!:’

2.0y

Arril

CARRIAGE

13,

1982

RETURN)

~EXAMINE

FHYSICAL

~-EXAMINE

WCS

BUS

MEMORY

‘E

<ANDRESS:’

~EXAMINE

‘E

<ADURESS:

<FIELUNAME=-1l9 <FIELINAME-23yyyy <F IELINAME~N
EXAMINE

NOTE?!

<FIELDNAMES:

WCS

LOCATION,

LOCATIONs

DISFLAY

ALL

FIELLDS

ONLY

FIELDS

THE FIELDS SFPECIFIED.
ACFyACM» ADSsALUY BENy EMXyCCKyCID
DKy BT yEAL

EBRMsFEKyFSs
IBCy IEKyUIMyKMX s MCT sy MSCyFCK y OK

RMX»SCKySGNsSHF
+ ST » SMX»SFQOsUSU s VAK

‘E

<ADDRESS:’

-EXAMINE

‘E

< ADDRESS:’

-EXAMINE

‘E

<SYMBOLIC-NAME:’

—EXAMINE

ONE

THE

SYMBOLICALLY

NAMELD

REGISTERS
NOTE?
‘D/F

<ADDRESS:

‘D/IN
‘D

<SYMBOLIC-NAMES:
<DATAX’

<ADDRESS:

<ADDRESS»

DRsFERsIBAsLArLEsLCsQsRLsSCs»SKyUFC

—DEFOSIT

< DATA:’

<DATA>

-DEFOSIT

<FIELDNAME-1>

INTO

THE

“/Z‘

FIELDS

ARE
MAY

QUALIFIER
TO

«<DATA-1>s<FIELONAME-2>
-DEFOSIT

NOTE?!

FHYSICAL

<DATA>

WCS

MEMORY

BUS

LOCATIONs

<FIELDNAME-13:s,

UNCHANGEID.
BE USED TO

REGSITER

<DATA-2%r¢essssee
FUTTING

UNSFECIFIED

ALL

UNSFECIFIED

CAUSE

<ADDRESS:

< DATA:’

~DEFOSIT

< DATA>

‘D

<ADDRESS:

< DATAX’

-DEFOSIT

<DATA:>

‘D

SYMBOLIC-NAME:

~DEFOSIT

<DATA:

ONE

NAMED'
NOTE:

DEFOSITS

THE

‘CONTINUE

RLOG

REGISTERS(SEE

STACK(RL)>

-RESUME

<ADDRESS:’

‘HALT

‘SET

SOMM‘

‘CLEAR

‘SET

~START
~HALT

SOMM~’

STEF”

THE

ARE

NOT

LIST

THE

SYMBOLICALLY

ABOVE).

SUFFORTEL.

MICRO-INSTRUCTION

SPECIFIED

‘START

FIELDS

CLEARED.

‘I

<DATAX:’

<DATA-1

ETC.

EXECUTION

CONTENTS

MICRO-FC(UFC)

MICRO-SEQUENCER

<ADDRESS:.

MICRO-SEQUENCER

~SET

THE

-CLEAR

~ENABLE
START

‘STOF

THE

SINGLE
OR

‘STOF

MICRO-MATCH’
ON

MICRO-INSTRUCTION

CONTINUE

INSTRUCTION

ENAELE

MICRO-MATCH’

WILL

EXECUTEs

ENABLE

STEF

MOLE.

ALLOW

ONE

MICRO-

THEN

HALT

THE

MICRO-SEQUENCER.

'CLEAR

STEF~

~DISABLE

SINGLE

MICRO-INSTRUCTION

STEF

MOLE.,

MICRODEBUGGER HELP FILE (CONT)

"OFEN “FILENAMETM:’

OFEN DX1$<FILENAME:’
NOTE :

"RETURN’

OFEN’

~OFEN SFECIFIED FILE ON FLOFFY DRIVE O

-OFEN SFECIFIED FILE ON FLOFFY DRIVE 1

IS USED TO SFECIFY A FILE CONTAINING THE MICRO-CODE

CURRENTLY LOADED IN THE WCS FORTION OF THE CONTROL STORE.
(ADDIRESSES 1000(16) & UF IN THE CONTROL STORE)
THIS FILE WILL RE USED FOR ALL EXAMINES OF THE WCS»
SINCE THE WCS IS NOT DIRECTLY READAELE.

~RETURN TO THE CONSOLE FROGRAM.

BB+
et
Hm
'
[0 NOT USE THE RETURN COMMAND
!
!
UNLESS THE CONSOLE FLOFFY IS IN CS1.
!
o+
{ TO RETURN TO THE CONSOLE FROGRAM; REMOVE !
! THE WCS DERUG FLOFFY, INSERT THE CONSOLE !
!
FLOFFY, THEN TYFE ‘RETURN <CR:’.
'
+
o
+

LSI-11 CONSOLE ODT COMMANDS

Format

Description

RETURN

LINE

FEED

Close current
location.

}

Open

Take

contents

opened

location

Take

contents

address

Open

location

Open

last

$n or

Open

open

opened

location,

plus

opened

and

open

and

location
as
that location.

(#-7)

(PS

location

initialize

the

bus,

and

device

CSR

program.

Execute

RUBOQUT

Proceed

bootstrap

loader

using

address.
;P

that

location.

general

start

index

open

command.

sequential

location.

opened
location
location.

absolute

and

location;

Erase

with

program

execution,

character.

Response

DELete

backslash

Maintenance.
Display
of
an
register follows the M command.

(134)

each

digit displayed is
the
CPU
entered
follows:

time

RUBOUT

significant,

the

Halt

entered.

internal

CPU

Only the last
indicating how

(ODT)

mode,

Last

Digit
g

Halt
4

Source

HALT

signal
1

instruction

BHALT

Bus
error
occurred
while
device interrupt vector.

bus

asserted.
getting

LSI-11 CONSOLE ODT COMMANDS (CONT)

Last

Digit

2 or 6

Halt

Source

Bus

error

memory

doing

while

occurred

refresh.

Double bus error occurred

Reserved

(stack was

nonexistent value).

instruction

trap

occurred

address
micro-PC
(nonexistent
occurred on internal CPU bus).

combination

and

occurred.

CTRL-SHIFT-S

For

manufacturing

command

tests

only.

Escape

function by typing NULL and @

1008).

this

(888 and

CONSOLE SUBSYSTEM CONFIGURATION

D BUS iffe—

[——‘

V BUS

MICROSEQUENCER

CLOCK CONTROL

CONSOLE/CPU
INTERFACE

CONTROL

:' K
!
1

PANEL

ROM

[
J

]
LSI-11

4K MEM

Q-BUS

A
RXV11

FLOPPY

DLV-11

CONTROLLER
|

‘

RXO01

TERMINAL

DLV-11

(OPT)

EIA CONNECTION

FOR REMOTE
TERMINAL

TK-0192

|
-

w11

0
A BANK
RESIDENT MEMORY AT
0
RESIDENT MEMORY AT A BANK
LTC INTERRUPT ENABLED
MEMORY REFRESH ENABLED

POWER UP AT 173000
POWER UP AT 173000
PRECONFIGURED*

ENABLE REPLY FROM RESIDENT MEMORY

DISABLE REPLY FROM RESIDENT MEMORY DURING REFRESH

W10

ENABLE ON BOARD MEMORY SELECT

[

w11

w7
w3

l_K/ W5

—

W10——_)|

|\‘\we

M7264 ETCH REV. E ( AND LATER)

[

*FACTORY CONFIGURED DO NOT CHANGE (W7 & W8)

TK-0700

NOILVHNOIINOD HIdWNI ITNAOW J4-L LA

W1
W2
w3
w4

W5
W6
W7 & W8

oot

RESULT

IN/OUT

JUMPER

MSV-11B MODULE JUMPER CONFIGURATION

JUMPER

IN/OUT

RESULT
MEMORY BANK

SELECT 1

(20000-37776)
ENABLES BRPLY

DURING REFRESH

[
TK-0702

101

BCOS5L-10

Red Stripe

Jl--—r——————————— J8

Red Stripe

Down,

Left, Smooth

Ribbed

BCOSL-10

col

Side Up

J2-————mmmmmm—————— J7

Configuration of RXV-11

Should be preconfigured
Address:

Vector:

177170-177172
264

for:

Ribbon cable should be installed with
red stripe toward center of module.

Side to Backpanel

(M7946)

SNOILJ3INNOD 378VI IA-00V6
N

Backpanel

M9400-YE

DLV11 JUMPER CONFIGURATION

JUMPER

IN/OUT

RESULT

2SB

[

1STOPBIT

NB2

8 DATA BITS

NB1

NO PARITY

8 DATA BITS

PEV

DON'T CARE PARITY EVEN/ODD

FEH

NO HALT ON FRAMING ERROR

EIA

FR3
FR2

SELECTS 300 BAUD

FR1

SELECTS 300 BAUD

CL4-CLO

20 MA ACTIVE XMIT.
& RECEIVE

NO EIA OPERATION

VECTOR JUMPERS SET 70O 60-64
V7=1, V6=1, Vb=— V4=1 V3=1

ADDRESS JUMPERS SET TO 177560-177566
A12=—, A11=—, A10=—, A9=—, AB=—,

cCL3

CL4

FRO

FR1

-n

—_

CL2

~»

A7=], A6=—, Ab=—, Ad=—, A3=|

TK-0701

103

DLV11-E JUMPER CONFIGURATION

DLV {IE

R3 R2 R1

-t

T3IT2T1TO
[

A12 A11
!

A10

A9 AB A7 A6 A5 A4 A3

-t

V8 V7 V6 V5 V4 V3

12P
-E PBBG C CI

SS1H-BB-FR -FD RS

-——

-1

[

FB
M M1

TTTTTT

T0-3

—_——

M|\\
-

BG\\/
|

RO-3

=-/
——"t—5I

“\‘_——FR
| —

TTTTTT

Q-BUS SIGNAL DESCRIPTION

1/0 Transfer Control Signals

Name
BSYNC L

Description
Synchronize - The bus master (LSI-11 processor) asserts BSYNC L to in-

dicate that it has placed an address on BDAL <15:00> L. The transfer is in
progress until BSYNC L is negated.
BDIN L

BDOUT L

Data Input - The LSI-11 asserts BDIN L for two types of operations:

When it is asserted during BSYNC L time, BDIN L
specifies an input transfer with respect to the processor. It requires BRPLY L as a response. The processor asserts BDIN L when it is ready to accept data
from the slave device.

When the processor asserts BDIN L without BSYNC
L, it is requesting an interrupt vector from an interrupting device.

Data Output - When the LSI-11 processor asserts BDOUT L, valid data is

on the bus for an output transfer from the processor to an 1/0 slave device.

The slave device deskews BDOUT L (pauses) before latching the data. The
slave device responding to the BDOUT L signa! must assert BRPLY L to
complete the transfer.

105

Q-BUS SIGNAL DESCRIPTION (CONT)

1/0 Transfer Control Signals
Name

Description

BWTBT L

Write/Byte - The LSI-11 processor uses BWTBT L to contro! bus cycles in
two ways:

BRPLY L

The processor asserts BWTBT L on the leading edge
of BSYNC L to indicate that an output sequence
(DATO or DATOB) is to follow.

The processor asserts BWTBT L together with
BDOUT L, on a DATOB cycle, for byte addressing.

Reply - A slave device asserts BRPLY L in response to BDIN L and
BDOUT L on data transfers and in response to BIAKO L during interrupt
transfers. BRPLY indicates that the slave has asserted input data on the bus,
accepted output data from the bus, or asserted an interrupt vector on the
bus.
Interrupt Control Signals

BIRQ L

Interrupt Request - A device asserts this signal when its interrupt enable and
interrupt request flip-flops are set. BIRQ L informs the processor that a
device has data to send to the processor (input) or that the device is ready to
accept output data from the processor. If the processor’s PS word bit 7 is 0,
the processor responds by acknowledging the request, asserting BDIN L and
BIAKO L.

BIAKO L

and BIAKI L

Interrupt Acknowledge Output and Interrupt Acknowledge Input - The processor asserts this signal in response to an interrupt request (BIRQ L). The
processor asserts BIAKO L which is routed via the Q bus to the BIAKI L pin

of the first device on the bus. If this device is requesting an interrupt (asserting BIRQ L), it will block the passing of BIAKO L to the next device and
then place the interrupt vector on the bus. At the same time the device will
negate BIRQ L and assert BRPLY L. If the device is not asserting BIRQ L, it
passes BIAKI L to the next device via its own BIAKO L pin and the BIAKI
L pin of the lower priority device.
Address and Data Signals
BDAL <15:00> L

These 16 lines form the data/address path. Address information is first

placed on the bus by the bus master (processor). The processor then either
receives input data from or transmits output data to the addressed slave

device or memory location over the same 16 bus lines.
BBS7 L

Bank 7 Select - The bus master asserts BBS7 L when an address in the upper
4K bank (address in the 28K-32K range) is placed on the bus. BSYNC L is

then asserted, and BBS7 L remains active for the duration ofthe addressing
portion of the bus cycle.

106

Q-BUS SIGNAL DESCRIPTION (CONT)

Initialization, Power Fail Signals
Name

Description

BPOK H

Power OK - The power supply asserts this signal when primary power is
normal. If BPOK H is negated during processor operation, the processor
initiates a power fail trap sequence.

BDCOK H

DC Power OK - The power supply asserts this signal when there is sufficient
dc voltage available to sustain reliable system operation.

BINIT L

Initialize - The processor asserts BINIT L to initialize or clear all devices
connected to the Q bus. The signal is generated in response to a power up
condition (the negated condition of BDCOK H).

BHALT L

Processor Halt - When BHALT L is asserted, the processor responds by
halting normal program execution. External interrupts are ignored, but
memory refresh interrupts are enabled if W4 on the processor module is

Halt and Refresh Signals

removed. When the processor is in the halt state, it executes the ODT microcode, invoking console device (terminal) operation.
BREF L

Memory Refresh - This signal can be asserted by a processor microcodegenerated refresh interrupt sequence (when enabled) or by an external device.
BREF L forces all dynamic MOS memory units to be activated for each
BSYNC L/BDIN L bus transaction.

107

CONSOLE BOOT/TROUBLESHOOTING FLOW

console

the

VAX-11/788
subsystem

program does

system

powered

not

is suspected,

and

run

properly when

problem

the

console

Response

Action
Turn

start

up,

proceed as follows.

off.

Turn ac off.
push HALT/ENABLE switch
down

(HALT).

Turn

on.

DC ON (LED on LSI-11 control panel)

Turn dc on.

17380680

@ (printed on terminal)
RUN (light flashes)

If the responses are incorrect, go to the Console DC ON Flowchart.

Examine location 173008

173000/0068137

Examine location #37776

#37776/XXXXXX

(type

1730008/)
.

837776/).

(type

the

response

not

correct,

the

Examine

173@880

Flowchart.

push
up

HALT/ENABLE

Ensure

switch

(ENABLE).

that diskette

installed properly

floppy disk

ZZ-ESZAB

in the

drive.

Type 144200G.

BOOT

This command executes the ROM resident quick check console
On successful completion of these tests,
subsystem diagnostics.
If
the ROM code boots the console program from the floppy disk.

the boot fails, go to the 1402808G Console Boot Failure Flowchart.
The program listing for the ROM resident diagnostics
should be referenced when using this flowchart.

108

(ESKAA.DOC)

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)

CONSOLE DC ON FLOWCHART
DC ON, RUN LIGHT FLASH,
AND/OR 173000 PRINTOUT DID NOT OCCUR
XXXXXK

@ WAS PRINTED

CPU JUMPER IS WRONG OR CPU IS BAD

BOMRA L

NO. GO TO POWER FLOW

PRINTOUT GARBLED. CHECK BDALO

BREF L

ASSERTED AND GO TO TERMINAL FLOW

BSACK L

ONE OF THE FOLLOWING
1S DC ON LED ON?

SIGNALS IS ASSERTED

YES. WHAT WAS;

———

BRPLY L
BDIN L

PRINTED?
NOTHING

YES. DID THE
RUN LIGHT FLASH?

WAS PRINTED

BPOK H iS NOT ASSERTED

|—

BSYNC L

BOMG O L
BDAL T L

GO TO TERMINAL FLOW

NO, REMOVE M9400-YE. DOES

NO. IS THE
RUN LIGHT ON?

BDOUT L

TERMINAL PRINT 173000 ON POWER UP?

NO. CHECK POWER SUPPLY TO

BACKPLANE CABLE

NO. CHECK BDCOK H NOT
ASSERTED
NO. CPU IS BAD
YES. CABLING IS INCORRECT

YES. THE HALT SWITCH IS

YES. CIB IS BAD

NOT ASSERTING BHALT L

OT
ASSERTING
BHALT
L

YES. WAS
PRINTED?
| PROMPT
PROMPT PRINTED?
|

YES. CPU IS BAD

NO, REMOVE M9400-YE.
POWER UP. DID
PRINTOUT OCCUR?

YES. CABLING OR CIB IS BAD

NO. CHECK JUMPER

CONFIGURATION AGAINST
KC780 PRINT SET

INOBDALT L. BDAL 15 t,

BINIT L OR BDMGO L

IS ASSERTED
Tx-0378

EXAMINE 173000 FLOWCHART
LOCATION 173000 OR LOCATION 037776
DID NOT RESPOND CORRECTLY

RESPONSE
173000/?

NO RESPONSE

037776/7
@

OR THE CI8 IS NOT WORKING

THERE IS A BAUD RATE PROBLEM BETWEEN THE
TERMINAL AND THE DLV11 INTERFACE

THERE iS A PROBLEM iN THE DLV11, THE CABLE.

OR THE TERMINAL TRANSMITTING CIRCUIT (TERMINAL TO DLV11)

THE TOP OF MEMORY BANK 1

DOES NOT RESPOND

CHECK JUMPER CONFIGURATION AGAINST KC780
PRINT SET

WHAT WAS RESPONSE?

GARBLED RESPONSE

INTERPRETATION
THE CABLES ARE NOT CORRECTLY MOUNTED.

K037

109

VERIFY THAT REFRESH

“141236

o 141262

R2 CONTAINS FAILING ADDRESS

IS WORKING CORRECTLY AT

R3 CONTAINS EXPECTED DATA

FAILING LOCATION

1:11076

THE CPU TEST FAILED.

1::0332

NOT WORKING.

REPLACE THE CPU

CPU MAY BE BAD)

CHECK

CONFIGURATION

CLOSED. THE DRIVE IS BROKEN. RUN DZRXA AND DZRXB DIAGNOSTICS
VERIFY THAT FLOPPY

“FLOPPY NOT READY”

DOOR IS CLOSED
NOT CLOSED,

CORRECT PROBLEM

YES. THE FIRST DISKETTE IS EITHER BAD OR THE WRONG ONE

oLl

“NO BOOT ON VOLUME"

TRY ANOTHER

DOESIT

DISKETTE,

BOOT?

THE FLOPPY CAME READY, | NO, THE DRIVE 1S BROKEN, RUN DZRXA AND DZRXB DIAGNOSTICS

WHAT WAS PRINTED?

BUT DID NOT READ

"FLOPPY ERROR"

A BLOCK

NOTHING PRINTED

BAD CPU

HALT CPU,

NOTRING PRINTED

“000104

7140216

WHAT WAS PRINTED

“000002

“XXXXXX
@

BAD CPU
OR BAD CiB.

THE LTC SWITCH IS ON.

OR BEVNT L IS NOT CLAMPED LOW BY THE LTC SWITCH

BHALT L IS STILL ASSERTED

OR BDAL 9L OR BDAL10 IS ASSERTED

173000

A DOUBLE BUS ERROR HAS OCCURRED, SET R6 TO

UXXXXXX
@”

BAD CPU
OR CIB

@”

SEE LISTINGS (ESKAA.DOC).
XXXXXX = CURRENT LOCATION + 2

1000, TYPE 173000G. AND THEN REENTER THIS TROUBLESHOOTING PROCEDURE

SEE LISTINGS {ESKAA.DOC), XXXXXX = CURRENT LOCATION + 2
TK-037%

(LNOD) MO14 ONILOOHS3IT18N0YHL/1008 3TOSNOD

REPLACE FAILING

MEMORY. (NOTE

WORKING,

LUHYHIMO
14 3HNTIV4 L0008 3TOSNOD D0020vL

DEVICE DID NOT BOOT WHEN 140200 WAS TYPED

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)
CONSOLE POWER TROUBLESHOOTING FLOWCHART
CONSOLE DC POWER FAILURE
YES. ONE MODULE IS SHORTING DC. REPLACE
MODULES UNTIL THE BAD ONE S LOCATED

NO, CORRECT THE FAULT
1S AC PRESENT

NO. CORRECT THE FAULT

AT POWER SUPPLY?

YES, IS THE BOX WIRED
CORRECTLY FOR AC?

YES. REMOVE THE MODULES
FROM THE BOX IS DC ON?

YES. BAD POWER SUPPLY

NO, ARE VOLTAGES

CORRECT AT
BACKPLANE?

YES. BAD BACKPLANE

YES, DISCONNECT THE POWER
SUPPLY-TO- BACKPLANE
CABLES 1S DC

PRESENT?
NO. BAD POWER SUPPLY

ARE CABLES CONNECTED FROM POWER

@iJPPLY TO FRONT PANEL AND BACKPLANE?

NO. CORRECT THE FAULT
TK.0376

CONSOLE TERMINAL TROUBLESHOOTING FLOWCHART
CONSOLE TERMINAL FAILURE
NOT

REMOVE DLV11

AND ENSURE THAT
BAUD RATE IS

COMPATIBLE WITH LA36

COMPATIBLE. CORRECT FAULT

COMPATIBLE,
WILL TERMINAL
WORK IN LOCAL?

NO. REPAIR TERMINAL

YES. 1S TERMINAL 20MA CURRENT LOOP?

NO. BAD TERMINAL
NO (EIA),

WHILE CYCLING DC ON
1S THERE ACTIVITY ON
THE DLV11 BERG PIN F?

@— YES. WHILE CYCLING DC ON
IS THERE ACTIVITY ON

THE WHITE WIRE?

YES, WHILE PRESSING A KEY ON THE TERMINAL.
1S THERE ACTIVITY ON THE CABLE PIN M?

OR CABLE

YES. BAD TERMINAL,

FORMAT BUAD RATE

lNO, BAD DLV

NO. BAD DLV11 OR CABLE LOOP
YES. WHILE PRESSING A KEY ON

NO. REPAIR TERMINAL

OR CABLE LOOP

THE TERMINAL, IS THERE

ACTIVITY ON THE GREEN WIRE?

YES. BAD BAUD RATE.
FORMAT TERMINAL

TK-0377

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)

using

RXDP

the

flowcharts

package

diagnostics

Program

fails

help

(diskette

locate

problem,

DLV~-11E

vDvC

DLV-11F

VKAA
VKAB

LSI-11
LSI-11

CPU
EIS

VKAE

DLV~-11

VKAF

DRV11l

Test
Test

ZKMA

Memory

ZLAC

LA36

Test

ZRXA

RX11l

ZRXB

RX11

Disk Exerciser
Interface Tests

following

the

Function

Name

VDVA

The

run

AS-F824C-MC).

figure

shows

the

flow

sequence.

112

Test

Test
Test
Instruction

Test

events

the

LSI-11

boot

CONSOLE BOOT/TROUBLESHOOTING FLOW (CONT)

LSI-11 BOOT AT 173000 FLOWCHART, PART 1

TEST

MEMORY

START

(200)

TERMINAL
REVERSE

ADDRESSES

(1234)*

ADDRESS

GOOD DATA R3

TEST

BAD DATA (R2)

’—D

DOUBLE

011110

](216)

TERMINALS

)

TEST

BooT

140.000

ASSIGN

CHECK FIRST

DUAL

(204) l

ADDRESS +

TEST 1

BUS ERROR

GOOD DATA R3

BAD DATA (R2)

CHECK BYTE

TEST 2

SINGLE OP
INST DEST
MODE 0
T

(372)

OF MEMORY

]

CHECK SOURCE

{TEST 3

DO REST

MOOE DOUBLE

OP WORD

INST DEST MODE o | 436)

* ADDRESSES OF FSET

FROM 140,000

JMP INST
DEST MODE

136

TSTB & TST

TEST 4
(462)

TEST 5

DEST MODE

1246

(552)

%
CHECK BYTE

TEST 6

DOUBLE OP
INST DEST

MODE 0

{600)

TX-0380

BOOT LS!

(REBOOT)

TEST 7

BUT NOT
VAX-11/780

USE MEMORY

!
SET PWR-UP/
CRASH FLAG

WORD INST

DEST MODE # O

(1330)

(752)

YES

ERROR

500 & 502

TEST 8

BYTE DEST
READ

(1048)

MODE # 0

TEST 9

"8-1/0
ERROR"”

DIRECTORY

LOC 500

DISPLAY

:
CHECK JSR
DEST MODE

1074=JSR

1116 = RTS

FIND
DIRECTORY

“B-NO
TEST 10.11

CONSOLE"
READ BOOT

121"

DISPLAY

LOAD

BLOCK FROM

CONSOLE

FLOPPY

PWR/UP

CRASH
FLAG

PRINT
MESSAGE

READ

SOME MORE

INIT

VAX-11/780

WAIT

FOR CONSOLE

KEY

CONSOLE

PROGRAM

LOAD

VAX-11/780

L
|
TK

0381

(LNOJ) MOT4 ONILOOHS3IT18N0HL/1009 3TOSNOD

Z 1HVd '1HVYHOMOT4 000€4L 1V L1008 LL-IST

START

CHAPTER 5
INTERNAL REGISTERS

PROCESSOR REGISTER ADDRESSES

HEX

DEC

KSP

Kernel

01
02

1
2

ESP

Executive

SSP

Supervisor

usp

User

ISP

Interrupt

05
06

reserved

reserved
reserved

POBR

stack

pointer

stack

pointer
pointer

stack

base

pointer

stack

pointer

POLR

length

P1BR

base

PILR

length

SBR

System

base

SLR

System

length

reserved

PCBB

Process

11
12

17
18

SCBB
IPL

System control block base
Interrupt priority level

ASTR

AST

SIRR

Software

interrupt

request

SISR

Software

interrupt

summary

reserved

17
18

23
24

reserved
ICCS

Interval

clock

19
1A

25
26

NICR
ICR

Next interval count register
Interval count register

1B
1C

27
28

TODR
reserved

Time

1D
1E

29
30

reserved
reserved

1F
20

31
32

RXCS

Console

receive

21
22

33
34

RXDB
TXCS

Console

receive data buffer
transmit control/status

Console

23
24

35
36

TXDB
reserved

Console

transmit

reserved

27
28

reserved
reserved
ACCS

29
2A
2B

41
42
43

ACCR
reserved
reserved

2C
2D

WCSA

Writable

control

store

address

WCSD

Writable

control

2E
2F

46
47

reserved

store

data

30
31
32

SBIFS

SBI

fault/status

SBIS

SBISC

SBI
SBI

silo
silo

SBIMT

SBI

maintenance

SBIER

SBI

error

control

level

block

base

day

control/status
WO
RO

reserved
control/status

data

buffer

Accelerator

control/status

Accelerator

reserved

reserved
RO

comparator

35
36

SBITA

SBI

timeout

address

SBIQC

SBI

quadword

clear

reserved

MME

TBIA

Translation

buffer

invalidate

TBIS

all

Translation

buffer

invalidate

reserved

single

MBRK

Microprogram

Performance monitor register
System identification

PMR

SID
reserved

Memory management

117

enable

breakpoint

PROCESSOR REGISTER BIT CONFIGURATIONS

REG =

«ksP

28 KERNEL STACK POINTER

esp

29 EXECUTIVE STACK POINTER

02
03
04

ssP
usp
1sp

2A SUPERVISOR STACK POINTER
28 USER STACK POINTER
2c INTERRUPT STACK POINTER

3
4

VIRTUAL ADDRESS OF TOP OF STACK

[

Pos8R

DEC. HEX NAME 1D#

24 PO BASE REGISTER
RESERVED OPERAND FAULT IF VLA < 2%*31

pP1BR

25 Pl BASE REGISTER
RESERVED OPERAND FAULT IF VLA < 2**31 - 2**21
31

[

VIRTUAL LONGWORD ADDRESS

POLR

3¢ PO LENGTHREGISTER

PiLR

30 Pl LENGTH REGISTER

LENGTH OF POPT IN LONGWORDS

2**21 - LENGTH OF P1PT IN LONGWORDS

SLR

3t SYSTEM LENGTH REGISTER
LENGTH OF SPT IN LONGWORDS
RESERVED OPERAND FAULT IF MBZ #0
31

MBZ

LENGTH IN LONGWORDS
TK-0709

118

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG. #
DEC.

HEX NAME

PCBB

3A PROCESS CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ # 0.

313029

IMBZ—I

ScBB 38

02 01 00

PHYSICAL LONGWORD ADDRESS OF PCB

JMBZ]

SYSTEM CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ # 0.

313029

WZ]

IPLR

‘MBZ]

INTERRUPT PRIORITY LEVEL REGISTER

0504

020100

PHYSICAL PAGE ADDRESS OF SCB

M8z

IPSL<20:16q

ASTR 0C AST LEVEL REGISTER
RESERVED OPERAND FAULT IF NOT VALID {.E., MBZ #0.

03 02

sBR

MBZ

ASTLV

26 SYSTEM BASE REGISTER
RESERVED OPERAND FAULT IF MBZ # 0.

313029

IMszl

PHYSICAL LONGWORD ADDRESS

02 01 00

lMBfl
TK0711

119

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG. #

DEC. HEX

NAME

ID#

ICCS

O0A

INTERVAL CLOCK CONTROL/STATUS
3130

161514

08 0706050403

[L]]
vz ]
13
BITS

NICR

0100

SGL CLK

4,5 ARE 11/780 SPECIFIC

NEXT INTERVAL COUNT REGISTER
00

[

NEXT INTERVAL (1 MICROSECOND INCREMENTS, TWO'S COMPLEMENT) j
WRITE ONLY

ICR

INTERVAL COUNT REGISTER
RESERVED OPERAND FAULT IF WRITE

INTERVAL COUNT (1 MICROSECOND INCREMENTS)
READ ONLY

TODR

TIME OF DAY REGISTER
31

l
20

TIME OF DAY (10 MILLISECOND INCREMENTS)

SOFTWARE INTERRUPT REQUEST REGISTER

SIRR

RESERVED OPERAND FAULT IF READ
31

0403

WRITE ONLY

SISR

SOFTWARE INTERRUPT SUMMARY REGISTER
3

1615

0100

]

SOFTWARE INTERRUPT REQUEST
EDCBAOY987654321

MBZ

TK-0710

120

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#

DEC

HEX

NAME

ID#

RXCS

CONSOLE RECEIVE CONTROL/STATUS
31

08 070605

MBZ

lusl

MmBZ

DONE

RXDB

CONSOLE RECEIVE DATA BUFFER
RESERVED OPERAND FAULT IF WRITTEN

[

BYTE 3

2423

BYTE 2

1615

BYTE 1

08 07

BYTEO

READ ONLY

CONSOLE TRANSMIT CONTROL/STATUS

TXCS

[

08 07 0605

MBZ

l H

MBZ

]

READY

TXDB

CONSOLE TRANSMIT DATA BUFFER
RESERVED OPERAND FAULT IF READ

[

BYTE 3

2423

BYTE2

1615

BYTE 1

08 07

BYTE 0

WRITE ONLY
TK-0707

121

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
DEC

HEX

NAME

ID#

ACCS

ACCELLERATOR CONTROL/STATUS
3130

]

ACCR

[=2]

ERR

282726

16 1514

RES OPR

ACC ENA

%«fi:CELLERATOE}4 %AINTENANCE

[

ACC TYPE

16151413

l TRAP ADDRESS

WRT

TRP

BRK

ADD

09 08

MICRO BREAK (WRITE)

CURRENT ADDRESS (READ)

WCSA

MIC MAT

WRITEABLE CONTROL STORE ADDRESS
31

1615141312

[

WCS ADDRESS

]

PINV I

MOD 3

CTR
45

WCSD

WRITEABLE CONTROL STORE DATA
WRITE: WCS DATA

READ: WCS PRESENT
3

WCS PRESENT
0706 050403020100
TK-0708

122

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#

DEC

HEX

NAME

SBIFS 1B

ID#

SBI FAULT/STATUS
3130292827 2625

LLLTTE]
AR

wee

PTY

FLT

XMT

FLT St

FLT

wc{LTH

MLT

UNX

201918171615

LO LOCK}
WC

—FLT SIG }R/0

INT
EN

R/O

sSBIS

SBI SILO
313029

2524

SBI ID
AFTL
FLT

2221

18171615

SBI
TAG

_INT

SBI <M3:M0>

)
SBI TR <15:0>

S8t
CNF
< 1:0>

_ LOC

<B31:828>

80.

SBIsC

1Cc

SBI SILO COMPARATOR
313029282726

2322

.
111

2019

1615

COMP|
| SouP]
coonT |

]

COUNT

INT

COND

LOCK

cMP
SILO

LCK
UN

LOCK

CND

COMP CMD
OR MASK

CODES

*CLEARED
ON ANY WRITE TO SBISC

SBIMT

SB| MAINTENANCE
31302928 27

23222120

UL fwanrod ]
I'TT

F|R

WRT |MLT

SEQF {XMIT

REV

SBl

UNEX

R/O

17161514131211 10090807

F”E\I/

sl | CACHE
INv | PAR
EN

FIELD

SBI

R/IO

INV

—
R/O

(1T
Fl
Gl

]Gt

MISS REP

Fl‘

|miss|Rep
GO

F TME OUT

GO MAT
G1

MAT

R/O

REV SBI P1
DSBL SBI

CYC

TK-0705

123

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
HEX

NAME

1D#

sBler

19 SBI ERROR REGISTER

DEC

16 151413 121110 0908 07 06 0504030201
00

L LT TET1
RDS CRD INT EN—.
CRD
we

RDS

CP TIME OUT

R/0 {CP TIME OUT STATUS
MB2

R/O{CP SBI ERR CNF
wC

I8 RDS

1B TIME OUT

1B TIME OUT STATUS

1B SBI ERR CNF
MLT ERR

NOT BSY
MBZ

SBITA

1A SB! TIMEOUT ADDRESS
RESERVED OPERAND FAULT IF WRITE

31302928 27

lOJ

PHYSICAL ADDRESS
< 29:2>

MODE

READ ONLY

PROT
CHK

SBIQC

SB8I QUAD CLEAR
RESERVED OPERAND FAULT IF READ
RESERVED OPREAND FAULT IF MBZ #0

3130 29

IMB?I

PHYSICAL QUADWORD ADDRESS
WRITE ONLY

124

0302

I MBZ ]

PROCESSOR REGISTER BIT CONFIGURATIONS (CONT)

REG.#
DEC HEX

NAME

MME

MEMORY MANAGEMENT ENABLE

WRITE 1 ALSO CAUSES MICROCODE TO INVALIDATE TB.

TRANSLATION BUFFER INVALIDATE ALL

TBIA

RESERVED OPERAND FAULT IF READ

MBZ
WRITE ONLY

TRANSLATION BUFFER INVALIDATE SINGLE

TBIS

RESERVED OPERAND FAULT IF READ

[

VIRTUAL ADDRESS
WRITE ONLY

3C-

MBRK

MICROPROGRAM BREAKPOINT

1312

[
61

PMR

MICRO PROGRAM ADDRESS ]

PERFORMANCE MONITOR REGISTER
RESERVED OPERAND FAULT IF >1
3

0100

|
62

SID

SYSTEM IDENTIFICATION
RESERVED OPERAND FAULT IF WRITE
31

24 23

SYSTEM TYPE

1514

ECO LEVEL

1211

MFG

PLANT

READ ONLY

125

SYSTEM SERIAL NUMBER
TKO704

IBUF

DAY.TIME | 01

31/15 ] 30/14 129/13 l 28/12 |27/11 |26/10 125/09[ 24/08 23/07 I 22/06 l 21/05 120/04 I 19/03 118/02‘17/01 l 16/00
31

1B TODR

3E SID

SYS.ID

]

ocl

RXCS

20 RXCS

Data Byte 1

27 | 26

1] w0

Time Byte 3
l 28
27 |
Time Byte 1

]

[

18 I 17

[

Time Byte 2
21 4[ 20 | 19

18 |

]

18 l

]

27 | 26

[

13|

m|lw

7486

| 20

Serial Number

Data Byte 2

Data Byte O

Type

Plant

ECO

Levet

Data Byte 3

Time Byte O

| 4

ECO Level
| 20

5|4

3|2

18 I

Intrpt

RXDB

21 RXDB

Data Byte 3

31130[29'28127126!25124
Data Byte 1

| Done | Enable|]

23
7

]
I

22
6

|
l

Data Byte 2
l 20

Data Byte O

dVvW Sng-al

REG.NAME | REG.ID
NO. | INT.REG.NO

INT. REG. NO. | 31/15 | 30/14 | 29/13 | 28/12 | 27/11|26/10 | 25/09 | 24/08 | 23/07 | 22/06 | 21/05
22 TXCS

TXDB

23 TXDB

19 NICR

Lel

NXT. PER

CLK.CS

18 1CCS

Data Byte 3

[

Data Byte 1

27 | 26

|
|

D{read)

27 | 26

Ready | Enable

]

18 ]

Data Byte 2

[

18 J

[

110

] 20

I 2 ! 1

Interval

9 TRy 7 |

6 I

5 | 4

15 ] 14 I 13 I 12
0

Data Byte O

Q{write}

Next Interval

|20/04 | 19/03 | 18/02 | 17/01 | 16/00

Q{write)

0
intrpt

D{read)

| 3

Run

18 J

Intrpt | Intrpt | Single

Error

INTERVAL | 0B

1A ICR

30
14

27 | 26
11

Req

Count {microseconds)

23 |

Count {microseconds}
7

|2 ]=®]

Enable | Clock | Xfer

| 20

L I N

A I

(LNOJ) dVIN Sng-al

REG. NAME | REG. ID NO.|
TXCS

CES

INT. REG. NO. | 31/15 | 30/14|29/13 | 28/12(27/11]26/10 | 25/09|24/08]23/07 | 22/06 | 21/05 | 20/04 | 19/03
13 ASTR

30 PME

Control Store Parity Error

Summarlv
VECTOR

SIiR

15 SISR

]

8cl

F
PSL

TBUF

12 IPL

EALU|EALU

ALU | ALU | ALU

Arithmetic

Perf

08107|06]05104103102101100

Mode | Pend

Trace

Protection Code

8]
FPD

Valid

Priority

}lIntrpt

Number of Ones

Current

Modify

Mode

Decmal|

Page Frame Number

1r]o

Interrupt Priority Level

Float | Intger

Active

s | a1

|Ovrflo | Undflo| Ovrfio

Interrupt Priority Level

Mode

15|14|13|12[11|10]9

AST Level

Vector

Software Interrupt Register

Stack

Mon En

|Error

Prior

Trap Code

Nested

C31

Compat|

Valid

18/02| 17/01 | 16/00

Condition Codes

Page Frame Number

18 l

17 l 16

sl514‘3121110

(LNOD) dVW Sn8-al

REG. NAME | REG. ID NO.{

l ADS IMCT 3 |mcT 2| MCT 1 | MCT 0|1chm<

22/06

| 1A0 l 0A2

| 0A1

|0Ao

T8 Parity Error Bits

0D0

] 1A2 [ 1A1

TB Hit

AR | G1

[18/03

uBreak | Match

Error

|Oprand}

28 ACCS

0
CPTB

102

[TPwrg

IPA

Last

SBLERR

318BIS

GO
Mem

Parity Error

Man En

TB Parity Error Bits
1D1
| 1D0
| Qap2 IQDI

Bad

Miss

IPA

IProt ElAuto L

Trap Address
0
Micro-break {write)

Current Address {read)

Resrvd

Enable|

| 17/01|16/00

Replace | Force | TB Misc

Force TB

Accel

SILO

| 18/02

Both | G1

Write | Micro

6C1

[20/04

Write
TrpAd|

ACC.CS

|21/05

ACC.MN

24/08 | 23/07|

Replace|Force

Last Reference

FS
TBER1

|25/09

After

| SBI

Fault | Intik

[ 14

(13

|12

SBI ID

SBI TR

SBI TAG

Accelerator Type

SBI

s8I

M3/831|M2/330|M1/B29 | M0/B28 | CNF 11CNF 0

[

]

110

34 SBIER

RDS
IntEn | CRD

[RDS

[cPTO

|CPTO

TO | sT1

STO

| ©

CPEr

(IBTO

|IBTO

(IBErr

|Mult

CNF|RDS | TO | sTt

Not

STO

| CNF

| Error

Busy

(LNOJ) dVIN SNa-ai

REG. NAME | REG. ID NO.[INT. REG. NO. | 31/15 | 30/14|29/13 | 28/12(27/11 | 26/10

TBERO

35SBITA

Mode

17
FAULT

ocl

COMP

MAINT

30 SBIFS

32 SBISC

33 SBIMT

Parity

[

15
Unexp

Silo

Int En

Uncond

Lock

Rev
PO
Force

1€

Check

Fault

|20

1413

Lock

Force

Any

Rep GO|

Rep G1

|28

|27 |

|12 |

|Xmit

[Fault | EFP

Cond Lock

26 1 25

]

I 19

l 18

| &

Fauit | Fauit | Fault

|Fault

Latch | Int En| Signal | Lock

Compare

Count

Tag

0 l o] I 0
Force Enable
SBI invalid

0 I o] | 0 I 0
Reverse Cache Parity

Force
Miss GO

Force

]

[Match|Match

1 20

Maintenance 1D
G1

Compare

o] | 0 1 0 l [}

0 l 0
P1

24 1 23

Spare

Command or Mask

SBI

Physical Address

Code

Disabl | Rev

‘

Physical Address

Mult | Xmit

Wr Seq | Unexp | Mult
Fault
RD
Xmit
Force

Miss G1|
PARITY

Prot

]

O
Data Parity

Address Parity OK

(LNOJ) dVIN SN8-al

31/15 | 30/14 | 29/13|

28/12 | 27/11

12
UBREAK

WCS ADDR. | 22

]

Contro! Store Address

12|

8|5

Control Store Address

Counter

| 12

2D WCSD

Data

Mod 3

Parity
|23

20/04 | 19/03 | 18/02|17/01 | 16/00

[

2C WCSA

Invert

€L

| 21/05

3C MBRK
0

WCS DATA

26/10 | 25/09 | 24/08)23/07 | 22/06

Data

Data | Data

Data

Data | Data
24
23

Data | Data

Data

Data | Data

Control Store Address

Data | Data
22
21

Data

Data | Data

Data

Data | Data
18

Data

Data | Data

Data

(LNOD) dVIN SNg-al

REG. NAME | REG. IDNO. | INT. REG.
NO.
USTACK

ID-BUS MAP (CONT)

Scratch Pad Locations

Name
POBR

Addr

POBR

KSP

25
26

Q. sv
T0

2F
30

Symb

P1BR
SBR
KSP
ESP
Ssp
usP
ISP

FPDA
D. SV

IR No.

29
2A
28
2C

2D
2€

0A
ocC

01
02
03
04

Name

Addr

PCBB
sces

3A
38

T3
T4
T5
T6
T7
T8
T9

P1BR
SBR

ESP
SSP
uspP
ISP

POLR
PILR
SLR

1457
1458

33
34
35
36
37
38
39

3C
3D
3E

.BIN

132

IR No.

Symb

10
1

PCBB
SCB8

SLR

09
08

POLR
P1LR

ID-BUS REGISTER BIT CONFIGURATIONS

ID#:

Bit

020

NAME:

IBUF

Fields

<31:00>

Description
Data

Bytes

Instruction

Read

Only

Located

ID#:

Bit

NAME:

Fields

<31:00>

Buffer

<3:8>

TIME

M8223

(IDPL)

DAY

Description
32

bit

102

counter

Hertz

rate

Read/Write

ID#:

Bit

SYSTEM

NAME:

Fields

<31:24>

Located

M8224

(IRCN)

Description

System

Type

#1=VAX-11/78@
<23:15>

ECO

Level

<14:12>

Manufacturing

<l1l:006>

System Serial Number
Read

Only

Selected

Read

ID#:
Bit

NAME:

Fields

<87>

from

jumpers

M8236

backpanel

CIBC,D,E

RXCS
Description

Done

Set

<06>

Plant

console

data

available

Read

Only

Interrupt

software

signifying

RXDB

Enable

Allows

interrupt

when

Done

Read/Write
Located

M8236

133

(CIBE)

set

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#:

Description

Bit Fields
<31:8>

RXDB

NAME:

Data from Console Subsystem
Only

Read

on M8236

Located

ID#:
Bit

(CIBC,D,E)

TXCS

NAME:

Description

Fields

Ready

<B7>

Set

Read

indicate

Enable
interrupt when

Allows

Ready

Read/Write
Located

ID#:
Bit

Data to console subsystem
Write

Only

Located

ID#:

Bit

on M8236

(CIBC,D,E)

NAME:

Description

Fields

<31:00>

(CIBE)

Description

Fields

<31:8>

M8236

TXDB

NAME:

D Register

Read:
Write:

ready

data

Only

Interrupt

<@6>

by console

receive

Q Register

Read/Write
Located

on:

<15:468>

M8227

<7:008> M8228

(DCPC)

<31:16> M8226

134

(DDPC)

(DEPL,M)

set

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#:

Bit

NAME:

Fields

<31:00>

INTERVAL

Description
Data

loaded

ID#:

NAME:

Fields

<15>

into

overflow or
Write

Bit

COUNTER

interval

XFER

bit

counter

CLK

CONTL

REG

Only

<31:16>

M8238

(CEHP)

<15:0@>

M8231

(ICLS)

INTERVAL

CLOCK

STATUS

Description
Error
Over

run

second

overflow

before

first

serviced.
Read/Write

<a7>

when

clear

counter

Read/Write

<@6>

Request

Interrupt
Set

Interrupt

overflows
clear

Enable

Enables

interrupt

overflow

Read/Write

<85>

Single CLK
Advance

Write
<g4>

step

Only

XFER
Forces

Write
<pa>

counter

interval

counter

Only

RUN

Allows

counter

increment

rate

Read/Write
Located

M8231

135

(ICLS)

microsecond

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID§:

NAME:

<31:00>

INTERVAL

Bit

Up Counter

Read

ID#:

Bit

Only

M8230

(CEHP)

<15:9@>

M8231

(ICLS)

NAME:

CPU

ERROR

(CES)

Error

Used

Read

Only

Control

Memory Management

Store

"OR"

Only

Control

M823¢

Control

M8231

<14>=Group

1
@

Read

ALU

<089>

ALU N

<08>

ALU

<87>

ALU

C31

(ICLS)

Only

Located

<10>

Parity

<12>=Group

<11>

Store

Summary

Store Parity Error Bits

<13>=Group

M8231

(ICLS)

M8231

(ICLS)

Read/Write
Located

136

Microcode

(CEHP)

Parity Error

Read

Located

<14:12>

STATUS

Description
Nested

Located

<15>

rate

microsecond

<31:16>

Fields

<16>

COUNTER

Description

Bit Fields

Error

Bits

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<P6:04>

Arithmetic

Trap

Code

7=Decimal Divide by
6=Decimal Overflow
5=Float Underflow
4=Float Divide by @
3=Float Overflow
2=Integer divide by
l=Integer Overflow
p=No Trap Pending

Read/Write
Located

M8231

Enable

Performance Monitor

<B3>

Loaded

(ICLS)

read

microcode

Read/Write
Located
<@f2:01>

AST

M8231

(ICLS)

Level
Used

deliver

AST

SIR

during

RET

Read/Write
Located

ID#:
Bit

NAME:

Fields

<25>

VECTOR

valid

Prior

Indicates

priority

field

least

one

bit

was

bits

set

last

Only

Located

M823@

(CEHP)

Priority

encoded

value

bit mask

last

Priority

Read

Number

written

into

Only

Located
<20:16>

(ICLS)

Description

Read

<24:21>

M8231

M823¢

(CEHP)

Ones

Number

ones

into

vector

Read

Only

Located

last

written

M823¢

137

(CEHP)

<31:16>

vector

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<p8:00>

Vector

Hardware

Located

ID#:
Bit

NAME:

Fields

<20:16>

vector

SOFTWARE

M8231

(CEHJ)

INTERRUPT

Description

Interrupt

Priority

Level
at

last

Read

Software

Level

Pending

highest

interrupt

strobe

active

time

Only

Located

<15:81>

generated

Only

Read

M823¢9

Interrupt

Pending

(ICLS)

software

interrupt

flags

Read/Write
Located

ID#:
Bit

NAME:

Fields

<31>

M8231

PROCESSOR

(ICLS)

STATUS

LONGWORD

Description

Compatibility
CPU

Mode

executing

PDP-11

mode

instructions

Read/Write
Located

<38>

Trace

M8238

(CEHP)

Pending
At

end

equal

instruction

trace

trap

and

trace

pending

initiated

Read/Write
Located

<27>

First

Part

M823¢

Done

Microcode
within

sets

certain

instruction
if

(CEHP)

this

bit

defined

instructions,

may

restarted

interrupt

instruction

Read/Write
Located

M8239

138

(CEHP)

points

stating
from

that

occurs.

point

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<26>

Interrupt

Stack

Indicates

CP operating

interrupt

software

stack

Read/Write
Located
<25:24>

Current

M8238

(CEHP)

Mode

Current

operating

mode

3=USER

2=SUPERVISOR
1=EXECUTIVE

#=KERNEL

Read/Write
Located

<23:22>

(CEHP)

Mode

Previous
mode

M823@

operating

mode

(before

change

instruction)

3=User
2=Supervisor

l1=Executive
@=Kernel
Read/Write
Located
<20:16>

Interrupt

M8230¢

Priority

Current

(CEHP)

Level

interrupt

priority

level

Read/Write
Located

<97>

Enable

decimal

<@6>

Enable

floating

<@5>

Enable

integer

M823@

overflow

exceptions

underflow

overflow

exceptions

Read/Write

<@4>

Located

M8231

(ICLS)

Results

setting

T bit

<P3>

N bit

<92>

<p1>

V bit

bit

139

Trace

Pending

CPU

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

C bit

<ga>

Read/Write
Located

ID#:
Bit

M8231

(ICLS)

TRANSLATION BUFFER DATA REGISTER

NAME:

Fields

<31>

Description

valid
Allows

hits

with

VA<13:9>

and

used as index and address<30:14>
equals VA MUX<3@:14>
Write

Only

Located

<30:27>

Protection

(CAMV)

Code

Define

Protection

Address

Kernel

Exec

Super

User

gflgg

geel
0019

Unpredictable
R/W
*

gg11l

0100

R/W

g1e1l

R/W

gl10

R/W

gl11
1000

RO
R/W

*
R/W

*
*

1001
1010
1911

R/W
R/W
R@

R/W
RO
R@

RO
RO
RO

*
*
*

1100

R/W

1101
1110

R/W
R/W

R/W
RO

R@
RO

RO
RO

1111
*

access

R/W

Read/Write

Read

Write Only
Located on

<26>

M822¢

M8228

(CAMV)

Modify
Notes

Write

Only

Located

modified

M8224

140

page

(CAMV)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<20:9>

Page

Frame

Number

When

translation

page

numbers,

Write

ID$#:

NAME:

Fields

<20:18>

these

bits

become

PA<29:09>

Only

Located

Bit

occurs

i.e.,

BUFF

M8222

REG

(TBME)

Description

Force

Replace

Directs

writes

defined

20=Write
19=Force

Both
Replace

Group

18=Force

Replace

Group

groups

Read/Write
Located

<17:16>

Force

M8222

(TBME)

Miss
Force

miss

17=Group

16=Group

defined

group

Read/Write
Located

<15:08>

Last

last

<15>

Status

<14>

Status

<13:18>

<#9>

uADS
of

memory

reference

bit

uMCT

field

1 means IB WCHK existed on an
1 means reference delayed one
auto reload

M8222

(TBME)

Hit

Indicate

which

7=Group

6=Group

Read

group was

Only

Located

M8222

141

(TBME)

reference

cycle

Only

Located

non-nop

uFS

Status

Read

<p7:06>

(TBME)

Reference
Data

<#8>

M8222

hit

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<@4:81>

Force

Parity

bad

Allows

Error

parity

be generated

errors

2
3

Group
"

@
)

Data Byte #
"1
"

5
6
7
8

.
"
"
"

1
1
1
g

"9
"
|
A
"
"
"2
Address Byte

"9
"2

errors

Read/Write
Located
<00>

M8222

(TBME)

MME

Enable

Memory

Management

Read/Write

ID#:
Bit

NAME:

Fields

<20:89>

Located

TBUFF

REG

M8222

(TBME)

Description
TB

Parity

Error

20=1

Group

18=1

15=1
14=1
13=1
12=1

"
"
"

2
1
1

19=1
9=1

17=1
16=1

11=1

"
"

7}
"}

Status

Data

Byte

"
"

"2
"1

Address
"

Byte 2
"1

17}

Read/Any Write
Located

Clears

on M8222

142

(TBME)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<98>

CP TB

Error

Parity
Indicate

TB microtrap has

Read/Any Write
Located
<P6>

M8222

Indicates which
@=Group

1=Group

Both

Bad

Read

Only

last written

M8222

(TBME)

IPA are

not meaningful

Only

Read

Located

IPA

TB group was

IPA

Contents

<g3:00>

(TBME)

Unpredictable

Located
<p4>

requested

Pulse

TB Write

Last

been

Clears

M8222

(TBME)

Info
Status

3=1
2=1

last

load

from

IPA

TB miss on load
TB parity error

1=1 Protection violation or miss
#=1 Automatic hardware initiated load
Only

Read

Located

NAME:
Bit

(TBME)

ACCELERATOR MAINTENANCE

Write

Trap Address

When

set

Write

Trap

clocks

trap address

Only

Located
<23:16>

M8222

Description

Fields

<31>

M8286

(FMHR)

form

ROM

address

M8286

(FMHR)

Address
Use

ACC

trap

Read/Write
Located

143

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<15>

Write

Micro

Match

Setting

clocks

bits

<8:0>

Write

Only

Located

<14>

Micro

Indicates

M8287

match

from

(FMLP)

micro

match

has

occured

Only

Located

Micro

micro
this

Match

Read

<p8:00>

M8287

Break/Current
Writes

micro

Reads

current

(FMLP)

Address

break

micro

program

counter

Read/Write

Located

ID¥:

Bit

NAME:

Fields

<31>

ACCELERATOR

CONTROL

STATUS

Description

Located

Reserved

Read

write
on

M8286

this
(FMHR)

Operand

Minus

zero

error

Only

Located
<15>

(FMLP)

Error
Read/Any

27>

M8287

Accelerator

M8286

(FMHR)

Enable

l1=Enable Accelerator
@=Disable Accelerator
Read/Write
Located

<03:00>

Accelerator

M8287

(FMLP)

M8287

(FMLP)

type

@1=FpA
Read

Only

Located

144

will

clear

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#:

Bit

NAME:

Fields
16

<31>

SILO

Description
location

After

SILO

used

entry

after

Read

MASK<3:#>
Silo

written

Read

Only
on

Bit

NAME:

Fields

<15>

with

SBI<KB31:B28>

address.

M8219

(SBHJ)

M8219

(SBHJ)

M8237

(TRSF)

Only

SBI

ERROR

Description

RDS

Interrupt
Enable

Enable

interrupt

for

RDS

Read/Write
Located

M8218

145

(SBLH)

when

Otherwise

Only

Located

(SBHJ)

SBI<KB31:B28>

TR<15:00>
Read

ID$#:

M8219

CNF<1:0>

Located
SBI

(SBHJ)

are

Read

<15:00>

M8219

command

Located
SBI

(SBHJ)

written

equals

<17:16>

M8219

Only

Located

SBI

(SBHJ)

TAG<2:0>
Read

<21:18>

M8219

Only

Located

SBI

cleared

ID<4:8>
Read

<24:22>

fault

Only

Located

SBI

activity

Interlock
Read

<29:25>

SBI

Only

Located

SBI

store

Fault
First

<38>

errors

SBI

TAG

<M3:M@>

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<14>

CRD

Received

<13>

corrected

Read/Write

Located

M8218

read

Located

M8218

Timeout

Status

12=1

Timeout

1
o

Waiting

requested

Error

cycle

response

data

clear

bits<l1l:10>,

Located

98,

Only

M8218

(SBLH)

Confirmation

when

requested

cycle

command

Read

Only

Write

bit

Located

M8218

receives

address

data

clear

(SBLH)

substitute

Read/Write

Located

M8218

Timeout

Status

6=1

Timeout

for

data

clear

for

(SBLF)

requested

cycle

)

No device

response

Device

busy

Waiting

for

Impossible

Read/Write

Also
05:84

clears
-

Located

clear

bits<5:3>

Read
on

read
code

Only

M8218

146

(SBLE)

data

error

transfer

RDS

memory

busy

Read/Write

clears
Read

SBI

for read
Impossible code

<11:18>

from

(SBLH)

device

Device

substitute

clear

for

Read

g
1

confirmation

<P6:04>

memory

(SBLH)

data

Set

<p7>

from

clear

Read/Write

Also

<8>

data

RDS

Received

<12:10>

read

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<93>

SBI

Error

Set

Confirmation

when

requested

cycle

receives

confirmation
Read

Only

Write

bit

Located

M8218

Multiple

<@2>

Set

SBI

pending

Only

bit

M8218

(SBLF)

M8218

(SBLF)

Not

SBI

error

clear

Only

ADDRESS

physical

latch

for

Read

Only

Latched

Error

address

data

until

bit

(SBI

SBI

timeout;

will

timeouts

timeout

ERR

REG

bit

12)=1

not

subject

s
W W

R~
W

Mode

Kernel
Executive

Supervisor
User

Located

Protection
Equal

Located

Physical

M8219

(SBHJ)

Check

hardware

<27:08>

Busy

TIMEOUT

Latches

<29>

timeout

serviced

Description

not

<31:30>

Located

NAME:

Fields

not

Read

Located

ID#:

clear

(SBLF)

Write

Read

Bit

Error

with

confirmation

<@1>

error

for

references

protection
on

M8219

check

(SBHJ)

Address

<27:00>=PA<29:02>

Located

<27:16>

(SBHH,J)

<16:088>

(SBLF,H)

147

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#:

Bit

NAME:

<31>

SBI

FAULT

Parity

SBI

Parity

Read

Only
on

M8219

Read

M8219

During

(SBHJ)

Fault

Only

Located

First

Pass

Set

(SBHJ)

Fault

Only

Transmitter

Error

Fault

Data

Located

<25>

(SBHJ)

Transmitter

Read

<26>

M8219

Only

Located

Multiple

Fault

Read

Unexpected
Read

<27>

Fault

Located
<29>

STATUS

Description

Fields

M8219

(SBHJ)

by microcode

first

handling

code;

used

time

through

fault

note

double

errors

Read/Write
Located
<24>

M8219

(SBHJ)

M8219

(SBHJ)

Spare

Read/Write
Located
<19>

Fault

Latch
Set

<18>

Fault

from

SBI

fault

Read/Write

Located

M8219

Interrupt
Interrupt

clear
(SBHH)

Enable
on

SBI

fault

M8219

({SBHH)

M8219

(SBHH)

Read/Write
Located
<17>

SBI

Fault
Read

Signal
Only

Located

148

enable

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<16>

Fault

Silo

Lock

Indicates

ID#:

Bit

Only

bit

Located

M8219

SILO

locked

from

SBI

fault

clear

(SBHH)

COMPARATOR

Description

Allows

<31>

Silo

Write

NAME:

Fields

SBI

Read

than

lock
fault

Comp

Silo

Lock

unconditional

Locks
B.

silo

when

predetermined

(see

counter

Conditional

Lock

counter

Unlock

29)

19:16)

certain

looks

equals

writing

conditions

SBI.

signal
is generated
increment.
When

other

lock

when

Comparator

bit

(bits

data

When

which

silo

number

will

equals

exist.

match,

allows

compare

counter

lock
F

into

counter

Read

Only

Clear

writing

number

not

equal

counter

Located
<38>

Silo

Lock

M8219

Interrupt

(SBHJ)

Enable

Read/Write
Located

<29>

Lock

M8219

(SBHJ)

Unconditional
Enables

silo

lock

when

counter

equals

Read/Write
Located

<28:27>

Conditional

M8219

Lock

(SBHJ)

Codes

only

TAG

compare

TAG,

command

Read/Write

Located

M8219

149

(SBHJ)

function

mask

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<26:23>

Compare

Mask<3:08>

Command

Read/Write
on

Located
<22:20>

Compare

(SBHJ)

M8219

(SBHH)

Tag<2:8>

Read/Write
Located on
<19:16>

(SBHH)

M8219

Field<3:0>

Count

When

equals

allows

silo

lock

Read/Write
Located
1D

ID#:

Bit

M8219

MAINTENANCE

NAME:

(SBHH)

Description

Fields

<31>

Force

Reversal

SBI

Read/Write
Located
<38>

Force Write

M8219

Sequence

(SBHJ)

Fault

Read/Write
Located

<29>

M8219

(SBHJ)

Force Unexpected Read Data Fault
Causes

ID,

transmit

unexpected

SBI

read

TAG=#,

data

Maintenance

parity

good

Data,

Undefined

for

selected

nexus

Read/Write
Located

M8219

(SBHJ)

<28>

Force Multiple Transmitter

<27:23>

Maintenance
Used

Fault

ID<4:0>
force

unexpected

read

data

Read/Write
Located
<22>

Force

SBI

M8219

(SBHJ)

(SBHH)

Invalidate

Forces

writes

become

cache

done

CPU

invalidates

Read/Write
Located

M8219

150

(SBHH)

SBI

faults

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<21>

Enable

SBI

Invalidate

Allows

SBI

Must be =1

writes

for

invalidate

normal

cache

operation

Read/Write
Located

<28:17>

Reverse

Cache

M8219

(SBHH)

Parity

Reverse

1}
%}
2
0
)
%}

]
2
)
1%}
1
1

A
'}
1
1
@
@

B
1
0
1
%}
1

No P
Group
Group
Group
Group
Group

)

1%}

2
1

1
2

1
@

1
0

1
1

14
@

A
1

1
%}

Parity

1
1

Byte A
Byte B

Address
Address

1
8
#

Byte C
Byte A
Byte B

Address
Address
Address

Group ¥

Byte

Address

Unused
Group 1

Byte

Data

Group 1
Group 1

Byte
Byte

2
1

Data
Data

)

Group

Byte

Data

]

1%}

Group #

Byte

Data

Group

Group #

Byte

Group

Byte

Read/Write

<16:15>

Located

Cache

Miss

Force

M8219

(SBHH)

g
l1
1

1
0
1

Force miss Group 1
Force miss Group @
Force miss Groups 4,1

miss

forced

Read/Write
Located

<14:13>

<16>

M8219

(SBHH)

<15>

M8218

(SBLH)

Replacement

Cache

Random

g
1
1

1
0
1

Group 1 always
Group @ always
Undefined

Read/Write
Located on

M8218

151

(SBLH)

Data

Data
Data

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<12>

Disable

SBI

When

set,

SBI

cycles

M8218

(SBLH)

will

started

Read/Write
Located

<1l1>

Force

Reversal

SBI

Read/Write
Located

<1p:09>

Cache

(SBLH)

Match
1#=1

Group

cache

match

#9=1

Group

cache

match

Read

Only

Located

<08>

M8218

Force

M8218

(SBLH)

Timeout
Forces

read

timeouts

Read/Write
Located

ID#:

Bit

NAME:

Fields

CACHE

M8218

PARITY

(SBLH)

ERROR

Description

<15:14>

Error

Bit

]

read

reference

caused

error

read

reference

caused

error

Read/write

located
14

Read

only.

152

clears

M8218

entire

(SBLH)

Located

M8218

(SBLH)

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

<13:06>

Data

Parity
If

0.K.

set,

parity

meaningful

O0.K.,

bit

Parity

CDM

Group

”

“

l fi

”

”n

”

set

Address

Parity

set,

NAME:

<15:00>

M8218

<13:8>

(SBLH)
(SBLF)

0.K.

parity

0.K.,

bit

must

information

Parity

CAM

Group

”

Byte

Only

Located

Byte

Read

M8218

(SBLF)

USTACK

Description
Reading

pops

Writing

pushes

<15:808>

top

address

from

address

Control

Store

M8235

(USCD)

micro

stack

Address<15:00>

Read/Write
Located

ID#:
Bit

21
Fields

<12:0¢>

NAME:

for

Only

meaningful

Fields

set

<7:6>

ID#:

1 1

Located

Bit

must

l 2

Read

<A5:80>

information

UBREAK
Description

Data used to compare micro PC
or stopping system clock when
Read/Write
Located

M8235

163

(USCD)

for scope
SOMM set

sync

for

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#:

Bit

NAME:

ADDRESS

Description

Fields

<15>

WCS

Invert

Parity

When

set

inverts

WCS

parity

Read/Write
Located
<14:13>

Modulo

M8235

(USCD)

Counter

used

quantity

WCS

point

which

written

Read/Write
Located

<12:80>

Control

Store

Use

M8235

(USCD)

Address

address

WCS

for

writing

Read/Write
Located

ID#:

Bit

NAME:

Fields

WCS

M8235

(USCD)

DATA

Description

<31:00>

Data

<P7:08>

Number

Used
of

to
WCS

write

data

Boards

into

Present

g=1

#-1K

Present

1=
2=

1-2K
2-3K

"
"

3-4K

4-5K

5-6K

6-7K

"
"

7-8K

<31:8>Write

Only

<7:0>Read/Write
Located

M8233

154

(WCSB)

WCS

bit

ID-BUS REGISTER BIT CONFIGURATIONS (CONT)

ID#

Name

P@BR

P1BR

SBR

KSP

All

Registers

<31:00>

<31:24>

M8230

CEHN

<23:16>

M823¢

CEHM

<15:08>

M8231

ICLR

<@7:90>

M8231

ICLP

ESP

SSp

2B
2C

usp

ISP

FPDA

stored

registers
in

through

temps

CEHK,

are

ICLL

D.SY

Q.5Y

stored

registers
in

3¢ through 3E
temps on CEHK,

are

ICLL

PCBB

SCBB

PALR

P1LR

SLR

All

155

registers

are

Read/Write

SILO REGISTER INTERPRETATION

The

SBI

storage
The

silo

read

only

various

SBI

signals

assertion

silo

lock

through

the

use

set

the

silo

the

fault

the

silo

result

all

zeros

Following
the

is a

various

AFTER

for

any

nexus

The

comparator
register

rather

when

provides

locks

the

and

silo

that

last

SBI

makes
may

being

file

the

SBI

comparator

Examining
in

fault

the

silo,

the

also

but

than

silo

sets

data

comp

fault

temporary

cycles.
fault

available

locked

silo

through

lock

silo

lock.

not

locked

will
will

returned.

breakdown of

the

silo

and a description of

fields.

Fault

Set

Interlock

The

for

first

entry

after

fault

clears.

(31)
SBI

(INTLK

38)

interlock

commander
read

and

nexus

then

1line

1is

when

issuing

by memory

asserted

when

the

interlock

asserting

the

ACK

confirmation.

Identifier

(ID

29:25)

Field

Identifies the
of information,
TAG

logical

source or destination
depending on the TAG type.

Type

Command address
Write data

Interrupt
Read data

(TAG

Field
24:22)

summary

read

code

the

device

Source
Destination

corresponds

the

line

20001

Memory

P0e11
21000
#1001

UNIBUS Adapter 1
MASSBUS Adapter 1
MASSBUS Adapter 2

Adapter

3
8
9

Processor

the

transmit

receive

information

types.

TAG

which

Device

Defines

operates.

ID Code

106060

TAG

Source
Source

Type

200

Read

211
191

Command Address
Write Data

110

Interrupt

156

Data

Summary

Read

SILO REGISTER INTERPRETATION (CONT)

Function
(F

Field

21:18)

Used

with

command

with

command

type.

function
bits

bits

B31:B28

when

the

SBI

address,

otherwise

SBI

here.

Function
Definition

0000

Reserved

Read

pola

Write

g1l

Reserved

010¢
glo1

Reserved

Interlock

Extended

1010

Reserved
Reserved
Extended

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

function:

of
operation.

Byte

2001

)

function:

during

Mask

Field

Masked

Write

Maskked

particular

1location

data

for

Specify

Data

Type

Data

Read

Corrected

gole

Read

Data

response

(N/R)

Acknowledge

(ACK)

11
18

Error
Busy

(ERR)

response

Indicates

the
and

data

normal

unasserted

when

SBI.

access

read

Read Data
Substitute

particular

read.

0000

NOTE:

15:80)

2081

activity

Lines

Specify

addressed

Write

Read

1
2

types

(TR

Masked

Second

Arbitration

Mask

2109

Code

Read

Reserved

1611

bytes

17:16)

Masked

1000

10090

Masked

2110
g111

2010

the

written

2001

Primary

specify
are

command

1001

Confirmation

21:18

Function
Code

Mask Field
(M 21:18)

TAG

bits

are

specified

mask

address

Silo

devices

control

157

that
the

are

SBI.

there

requesting

SILO REGISTER INTERPRETATION (CONT)

Example

following

E/ID

Depos it

would

it was

silo

the

appear

locked.

Cycles

Silo

IDAO0OAG18

20C800A1

Cc2

IDPAOOOPL18

21440000

IDAPEO0018

0PB100060
40010000

Byte:

508

D/B

The

Interpreting

IDJPRo0018

Bit

Breakdown

CPU,

TAG

HOLD

MASK,

CPU,

BYTE

CNF

ACK

CNF

ACK

TAG

C/A,

WRITE

FUN

DATA,

MASK

These cycles correspond to the following figure.

\_3——+——c4

-i

SBI CYCLES
|-——cc
(C0-a)

NEXUS

COMMANDER/// NEXUS

2?7

RECEIVER

TRANSMITTER | TRANSMITTER | TRANSMITTER | RECEIVER

| {CONFIRMATION}
(ARBITRATION) | (INFORMATION) | (INFORMATION) | (CONFIRMATION)

ASSERTS
TR# ON

NO HIGHER

TR#

STROBES

ASSERTS

ACK INTO

LATCHES

DATA

IASSERTED
ASSERTS
C/A AND
HOLD

sel

TIME

raveN_

[
T3

[

]

[

ToO

ASSERTS
C/A ACK

STROBES

C/A INTO

LATCHES

RESPONDER

<81 UINE

SAMPLING

RECEIVER

NEXUS

STROBES

;‘:TS: ZLSK

DATA INTO
LATCHES

RECEIVER

NEXUS

TRANSMITTER | TRANSMITTER

NEXUS

///

(INFORMATION) | INFORMATION}
| (CONFIRMATION) | (CONFIRMATION

TK-0080

158

MICROCODE MACHINE CHECK ERROR LOGOUT

any

check,

machine

the

error

log out the following information.
stack as

but

shown,

Ordinarily, it appears on the

error

a double

attempts

microcode

handling

halt

occurs,

operator

the

This
can find the same information in the ID-bus temporaries.
information is VAX-11/788 specific, of course, and does not apply
to other members of the family.
Memory

Data

Byte Count

Location

Notes

(SP)

None

40 (dec)

(SP)+12

T2 (32)

(SP)+20

(34)

(39)

Summary Parameter
CPU Error Status

(SP)+4
(SP)+8

VA/VIBA

(SP)+16

Trapped UPC
D register

Location

TB ERR 0§
TB ERR 1
Timeout Address
Parity
SBI Error

(SP)+24
(Sp)+28
(SP)+32
(SP)+36

PSL

(SpP)+48

(SP)+4¢0

timeout

See TBER# format
See TBER1 format
Physical addr/4
See PARITY format

(35)
(36)
(37)
(38)

See SBI.ERR format

None

The summary parameter is a longword.
nonzero

virtual address

None

(SP)+44

error

Byte 1 is a flag, which is
confirmation

pending at the time the machine check occurred.
any, has been cleared.

(hex)

Microcode error location

T3 (33)

T5
T6
T7
T8

= 28

See below
See CES register format

16 (30)
Tl (31)

interrupt

was

The interrupt, if

Byte zero indentifies the type of machine

check:

g@ - CP Read Timeout or Error Confirmation Fault

@2 - CP Translation Buffer Parity Error Fault
#3 - CP Cache Parity Error

#5
gA
@C
@D
@F

CP
IB
IB
IB
IB

Fault

Read Data Substitute Fault
Translation Buffer Parity Error Fault
Read Data Substitute Fault
Read Timeout or Error Confirmation Fault
Cache Parity Error Fault

F1 - Control

Store

Parity Error Abort

F2 - CP Translation Buffer Parity Error Abort
F3 - CP Cache Parity Error Abort

Fg§ - CP Read Timeout or Error Confirmation Abort
F5 - CP Read Data

Substitute Abort

F6 - Microcode "not supposed to get here" abort

"IB" refers to memory reads generated by the instruction buffer in
In these
the process of prefetching the instruction stream,

cases, the address stored at

memory

address

references
comes

explicitly

(SP)+16 is from VIBA.

requested

from VA.

1569

"CP" refers to

microcode

and

whose

DOUBLE ERROR HALT

The

CPU

will

microcode
The

halt

that

information

U-STACK

if
it
is set.

EFP

(trapped

the

finds

first

entry

error

microaddresses).

will

the

error

handling

ID[38-39]

Unpredictable

and

parity

errors.

The

information

error/status

The

CPU

ID[D.SV]

the

will

second

error

will

registers.

be halted
ID(2E).

after

leaving

double

ID
SUMMARY

PARA.

T@
T1

UPC

CES

TRAPPED

VA/VIBA

D-REG

TBER®

TS5

TBER1

TIME.ADDR

PARITY

SBI.ERR

160

No.

the

error

associated

halt

code

V-BUS CHANNEL CONFIGURATION

V BUS

CHANNEL

MODULES

—

usc

M8235

CEH

M8230

2
|

DAP

ICL

TBM
M8222

IDP
M8223

CAM

CDM

M8229

M8231

|
3

IRC

M8224

|
4

M8220

M8221

I
5

SBL

SBH

FCT

FAD

M8218

M8219

|
M8289

M8288

|
7

RESERVED
TK-0703

161

V-BUS DIRECTORY

CHAN

RrT
C=F XY

arr

Dwh

MODULE

7,8,

SIGNMAL

NAME

(PCTAL)

4p
ve

LRI

(AMy

EAEURB |

USLF
USCF

mMB215
MR218

cera
cPYR

USCF
USCF

UPCSV
UPCSV

@@
21

EERS)

JSCF

MADYR

reTe

USCF

LRT R

USCF

UPCSY

MA23%5

cpra

USCF

UPCSV

rraly

AAEAAD

wAAY

IE1d3

naag

M8235

SRV

rerp

USCF

LPCSV

MB 218

cPTR2

USCF

]

UPCSY

AP AL

YRR TS

ISCF

M8215

CPTH

USCF

AAT

UPCSY

AAANT

I1SCF

MB235

cpYe

USCF

UPCSV

Aveta

USCF

MR235

(PTR

USCF

UPCSV

¥8

INPL

2221

USCF

MB35

(PTA

USCF

UPCSV

JSCF

MR21g

cPrTR

USCF

UPCSY

ArALY

JSCF

MR235

cera

USCF

UPCSV

H
W

SRRE]

eAve

Avatd

USCF

nann

MB2135

HSCR

MRQ21S

UPCSv

CPTX

USCR

ve
vo

STALL

Nt g
PWAAF

21
AR 7

1JSCB
1scJ

M&238
MR238

CPTX
CPTX

USCR
USCJ

UTRAP H
ECO NISPATCH

cPTa

USCF

wag A

2211

USCE

w2y

MR23g

11SCE

USCE

MB235

BUS

0
%2

g2
LJERIR §

cPT3

nea2e
A2y

USCE

SCE
USCE

M82135
MA23S

(31:42)

cePTy
CPT3

USCE
USCE

CS
CS

wR
wR

(63332)
(95364)

(4]
v

Bald
IR

2AP24
02A2S

USCE
1ISCE

mMa239
MB235

cPTX
cory

USCE
USCE

w(CS
wCS

MR21S

CPTX

USCM

TBUF

(-]
vo

[J:]

2p
up
1)

24l e

Von2e

CPTY

FCTX

apn2y

HSCTM

AULR

HARTD

USCw

Ma23s

CPTX

Py a

[ BIRY

SCH
usey

MR2135
MB2135

CFTX
CPTX

CCPA
D

FERE)
VLR

P1C

warly

neayy

pvaly

LERE)

“wapls

WALE

AR 3e

AALF

Pvaly

éa

mA23S

¢il7

UsCL

cery

dirds
et

TN
2¢nad

SCN

ISCN

USCN

useN
uscwN

HSCN
USCN

MB23S

MR23S

MB235%
MA23%

MB23s

MR23S
MB218

cPTX

CPTX

coTX

ACCA

RIT

(1)

UBY

ANyl

USCN

MB23S

cerx

[

AraALu

MR23S

cPTYX

nees

RANYS

UseN

PIZET

MR23S

uSCN

CPTX

ACCA

an27

MB23%S

CPTX

anpuy

uscw

MR23S

€CoTx

USCN

MR23S8

cerx

2229

NDCPA

AR5

USCN

MB23§

ety

1]
1)

¢dea
aa2n

Q0252
aA3pSY

USCN
iISCN

MB235

cPTX

“823%s

CPTx

162

ALU

w2l

URQ

PSL

CPTX

uscx

ICL*

MR21E

226

(1)

usecTM

CEHR

FILF Y]

LAPP

(BA7300)

cPTX

Pa22

CPTX

wR CYCLE =
MEM AVAIL L

ACC OVERPRIDE (

ICLK ALY Z

CPTX
CPTY

XCVR

LAKY

V-BUS DIRECTORY (CONT)

ep
de

an2c

fn2n

ARASY

VeAs5s

USCN

MA23S

MB235

CPTX

cPTX

ACCA UB2 H

CERE UTRAP VECT P W

A02E
An2F

anuse
arasy

USCN
USCN

MB235S
MB23s

290

A232

el IY

USCN

mMa215

CPTX

ée
L2

na32
ey

70062
Haney

USCN
USCN

MR23S
MA23g

cPTX
CPTX

TBMD
DDPS

USCN

mM8235

cPTX

USCN

MB23S

cPTX

ICLK

oo
09

2031

*n34

ea3s
oale

037

9038

')
0o

2034
pole

ep
1]
20
ep

1314
ee3D
nR3E
2A3F

[ 1]

#ou0

2039

LYY

2065
.11 T°YY

e0e67

USCN
USCN
USCN

M823S§
M8238

eoaTy
20e7s
20076
PaRTY

USCN
USCN
USCN
USCN

MB35
ME235
M823S
M8235

en100

2843

-1
20

enuY
094S

90104
aa1as

0046

M823S
M823S

20070

roy10t
eagee
ea103

-] ]

USCN
USCN

M8235

a0aT2
20073

-L'T -}

1]
L1
02

eayy
eeu?

USCN

28106

USCN

M8238

M823S

cPTX
CPTX

cPTX

CPTX
CPTX

CPTX

cPTX

TBMD
NAPD

LAST REF
SS(1) H

CEHE UTRAP

CODE

VECT

LAST REF CODE
SC N,E, O H

CEME UTRAP VECY 2 H
CEWF NESTED ERR (1) W
EALU Z

(1)

CEHE UTRAP VECT 3 W

CPTX
CPTX

CEMH
ICLK

FPD BIT L
EALU N (1)

CPTX
cPTX
CPTX
CPTX

TT
USCN BEN EN
USCN BEN EN
USCN BEN EN

(1Bgi1U)
(IFsIC)
(13110)

M
M
H

USCN

M823%

cPTX

USCN BEN EN (B7100)

USCN
usce
usce

MB23S
M821s
M8235

cPTX
CPTX

CPTX

USCN BEN EN (OF308) W
USCP BRBITA(CIFIIC) W
ICLE BRBITO(1Bs114) H

usce
Usce

M8235
MB823S5

CPTX
cCPTX

ICLE
USCP

BRABITA(OF128)
BRBIT1I(1Fs1C)

H
H

M8235

CPTX

ICLE

BRBIT1(GF188)

usce

M8213s%

CPTX

ICLE BRBITI(1B114)

0047

e0107

20
2o

@aus
2049

ary1e
.L.ERN!

2044

usce
usce

PP112

M8235
M8235

uSCP

CPTX
CPTX

MR23S

USCP BRBIT2(1F31C)
ICLE BRBIT2(1Rt114)

(PTX

H
H

ICLE

BRBIT2(MF1A8)

2o
'L}

2a4c
@eap

AA114U
pA11S

POUE

usce
usce

ge116

MB235
M823S

CPTX
cPTX

o117

CPTS

~
W

Q0uF

MB23S

ICLE BRABITI(1RS14)
USCP BRBITU4(1FIIC)

USCH

é0

CLTT)

o113

usce

uscJ

“8235

M8235

CPTX

cPTA

USCP BRBITI(iFs1C) W

CIBN

SYNC

PULSE

(1)

MAINT

RTN

2059

00129

uscJ

MB235

CPTX

po122
an1e3

Ma23s

INIT

ans2
2053

uscJ

USCJ

"]
-]

f0121

uscJ
uscJ

CPTX

USCJ

mM823s
M823S

STALL

CPTX
cPTX

USCJ UTRAP () W
USCJ UECO (1) W

20
20
2o
éa

8054
2055
2956
oes?

20124
en12s
#8126
en127

uscJ
uscJ
USCY
uscJ

“821315
MB23S
MB23S
M8238

CPTX
cPTX
cPTX
CPTX

USCJ MAINY
USCJ PRIOR
USCJ PRIOR
USCJ PRIOR

163

(1)

RET
2 L
1 L
2 L

W
M

(1)

V-BUS DIRECTORY (CONT)

o8
14
20

opS8
@959
20SA

ot la
en1 3y
on13e

uscTM
uscH
uscH

M821s
M823S
Ma23s

CPT2
cpPT2
cP12

USCTM BUF UPC @2 H
USCM BUF UPC 21 M
usc® BUF UPC @2 H

20SC

n0134

UseH

MB23s

cPT2

USCM RAYF UPC wd W

uscH
usScM

ma23s
M821%

cPT2
cPT2

UsSCTM BUF UPC @6 H
USCTM BUF UPC a7 H

oS8

Pa50

00133

n013S

uscH

uscTM

MA23S

8218

cPT2

cPYe

usC“ BUF UPC @23 H

UsScTM BUF UPC #S W

L4
oo

Q0SE
00SF

22136
o137

oo
09
14

2060
2061
o062

pR140
ee141
pRqa2

USCH
usce
USCM

M8238§
Ma23s
Ma23s

cPT?
cPT2
cPT2

USCTM BUF UPC P8 W
USCTM RUF UPC A9 M
uscM BUF upPC 10 ¥

dLY

ee144

usSCH

mM823s

cpPT2

USCM BUF UPC 12 H

2067

eay47

uscx

M823s

CPTX

RESERVED

09
29

00e63

0365
8066

20143

20145
fajae

USCH

ysCx
uscx

M823S

M823%
“a215%

164

CPT?2

CPTX
cPTX

uUscM BUF UPC 11¥

RESERVED
RESERVED

V-BUS DIRECTORY (CONT)

@209

BIT
(0CTAL)

DWG

MODUL E

7,8,

SIGNAL

CPTX

PCSC PAR ERR
PCSC PAR ERR
PCSC PAR ERR

(95164)

(6313132)

(31100)

SALP

PAR

TRAP

TaMW
CEHF

PROT

aoaoe

CEHE

mMg23n

anet

a0ea1

cPTX

nean2
a0nnl

MB823p
MB232

cPTX

roes

CEME
CEME
CEHE

mMg2le

ARn2

CPTX

CEME

M8230
mgale
M8230

CPTX

Ma23A

M8230
Mga3a
Ma239

cPTX

DEPM

8230

CPTX

DOPD

PRy

a2oud

f0es

n0aas

evesé

avaade

aaa7

eeaar

CENF
CEWF

@008

a1
e

CENWF

enaty

ARAA

ang12

ane13

CEnpP
CEMA
CEHA

0eacC

CENF

aa014

20200

CEHA

avals

CEMA

AAQE

Vet
e

ajaF

eveLr7

CEHA
CEHA

ania

CPTX
CPTX
cPTX

CEWF

LOAD

cPTY

CEMF

CLR

cPTx

ICLS

EN 1D
BMX 3y
BMX1S

CPTX

DCPD

cPTY
CPTX

DEPD
oDPR

CPTX

oCPD

arg2a
22021

CEHA

CENA

M8230p
mM8230

CEWa

2213

aan2e
22923

CEMA

Ma23¢@
M823n

en1y

0224
2702s

M8239

CPTX

2ve2e

CEMHA
CEMA
CEHA

M8239

29027

CEMA

mM823e

ea18

aea3p

CEHA

Me239

CPTX

2019

20031
oeul?2
oPe33

CEHA

M8239
M8230
M8230

DEPN

CEMA

CPTX
CPTX
CPTX

DcPF

"B
B
as12

“e1S
gate
2017

Ag1A

fR1R

aa1c

20034

310

2d03s

vo1E

neale

ARLF

anayy

an20

peaae

CEMA

CEMA
CEHA
CEHB
CEHB
CEHB

0221

enauy

3022

CENC

20942

CENC

Q2043

CEWC

2p24

naQuy

MB230

Mg2la
Ma23e
M823@
M8230

Ma23e

UTRAP

IRD STATE
READ RLOG

M8230

ERR

CEWF

M823@
M823¢g

NAME

W
TM

STATE
UWORD

BMXQ@Y
AMX 3]
AMX1S

AMYQY

(1)

XCEIV

CPTY

DEPK

ALU

oceL
DCPL

ALU

CPTX

DCPL

CARRYSS

ALU

CARRYBT

CPTX

ALU

BUFF1T

ALU

BUFF16

CPTX

CEMA
CEMA
CEHA

CPTX

CEHA

ALU

CPTX
CPTX

cPTX

CPTX

DOPF

BUS

BUFF31

CARRY31

MB23a

CPTX

DAPB
DDPN
DOPN

cPTX

ACCX

ALU BUFF1S
BUFFQT7

ALU(3BI18)=0 |

ALU(BYIP0)30

ALU

BYTER2,3

AUALUSA

MINUS

rARYLS

CEMC
CEHC

MB23¢
MB23p

24ade

CENC

CPTX
CPTX

ACCX

Ma23a

VDATA

hoe7

CPTX

peeuy

CEHWD

ACCX

M8239

CPTX

CEHD

CDATA H
SECOND REF

CPTX

S8LT

STALL

CPTX

IRCY DQ CONT H
IRCJ FLOAT H
IRCJ WORD CONT H

erasa

CEHD

220Sy
avas2

M8230

CEHWD
CEHD

Ma23p
M8239

ao2g

CPTX

ePasy

CEND

M8230

CPTX

165

ACCX

IDATA

]

|
L

As8

EALUOBY H
EALURS N
NDATA H

026

na28
2729

ALUC1SIR8)SD

292S

2024

BUS ALU BYTE1 A=B
BUS ALU BYTEQ® A=B
DCPA AMX@Q L
DaPB AUALUSA PLUS

M8238
MB23e

L
L

CPTX
CPTY

ALU

rree

BIT
(HEX)

V-BUS DIRECTORY (CONT)

IRCJ BYTE CONT W

Mg23n
MB230

cPTX
CPTX

TRMW

Ma230a

CPTX

DOPS

SAVE CONTEXT W
FLOAT NZERO W

anes?y

M823Y

CPTX

usce

CLR

LYY

Ma234

CPTX

DCPH

vaga(1)

walt

anast

Mg23la

cPTy

DCPJ

VARLI(1)

ncey

VARA(L1)

TRMW

aa2c

rIASy

*a20

NO2E

pAASS
ensSeé

wyeF

anse

pPAE2

MA23Q

crPTYXY

2033

07063

M8230

CPTY

2234
eals
LAY
eas?

20064

80065
[

neee?

EDGE

cPTX
cPTX

TBMN

PAGE

M8239
Mg230

CPTX

TRMW
SRLM

TIMEOUT

cPTYX

SBLR

RDS

“g23a
Mg239
Mg23n
M8230

CPTX

TAMW

CPTX
CPTX
CPTX

TAMW

TB PAR UTRAP
MISS UTRAP |

TBMW

MBIT

CEHE

M823@
MB239
Ma23e

CPTX

RESERVED

20079

a9074

CEHE
CEHE

2034
2o3e

00072
20073

CEHE
CEME

003C
2330

e0eTy

CENX

020075

CEMX
CEMX
CEHX

va3F

CMODADRS

MB23Q
MA23p

ne3s

23a76
eeaty

{

CEME
CENE
CEHE
CEHE

2039

2A3E

UTRAP

MB230@

166

TRAP
TRAP L

UNALIGN

CPTX

RESERVED

CPTX
CPTX

RESERVED

TRAP

RESERVED

UTRAP

{

TRAP

V-BUS DIRECTORY (CONT)

CHAN

82
02
02
02

383

OWG

MODULE

T,S,

SIGNAL NAME

(HEX)

(0CTAL)

2000
0001
0002
geel

2000P
20001
00002
29023

DAPA
DAPA
DAPA
DAPA

M8229
M8229
M8229
M8229

CPTX
CPTX
CPTX
CPTX

IRCF
IRCF
IRCF
IRCF

CLLY

20904

384

OPC@
OPCY
OPC2
OPCY

W
M
W
W

02
22
82

eeos
0006
paa?

a30P5S
20006
aeeay

DAPA

DAPA
DAPA
DAPA

M8229
M8229
M8229
M8229

CPTX
CPTX
CPTX
cPTX

IRCF OPC4 M

02
02
02
02

2008
2009
200A
goes

900412
20011
0812
29213

DAPX
OAPX
DAPX
DAPC

M8229
M8229
M8229
M8229

CPTX
CPTX
CPTX
CPTX

CEMD MEMREF DT3B TM
CEHD MEMREF OTE{FDG M
RESERVED
RESERVED

02
02
02
02

anac
90D
LLLI3
'T'].14

QU014
#2015

(.l 3Y
#9817

DAPC
DAPC
DAPC
DAPD

M8229
M8229
“8229
M8229

CPTX
CPTX
cPTX
CPTX

IRCE
IRCE
IRCE
IRCH

02
02
22
02

2210
9011
aa12
2013

20020
CELH
20022
20023

DAPF
DAPF
DAPP
DAPF

M8229
M8229
M8229
M&a229

CPTX
CPTX
CPTX
CPTX

RESERVED
IRCE SP1 CONZ2 W
IRCE SP1 CONY H
IRCE SP! CONB M

22
02

neLy
099015
2416
0017

90024
2060825

DAPX
DAPD

MB229
M8229

CPTX
CPTX

DAPB RLOG UPDATE W
CEHF READ RLOG W

02
82

00826
02327

DAPF
DPAF

MB229
M8229

CPTX
CPTX

IRCF OPCS W
IRCF OPCé M
IRCF OPCT W

RYTE CONT W
WORD CONT H

LFDQG CONT K
PC REG H

RESERVED
RESERVED

RESERVED

22
82
02

on319
rO1A
eQ18

enol3t
#2032
g0l

28038

DAPX

M8229

CPTX

CPTX
CPTX
cPTX

RESERVED
RESERVED
10PN SP1 ADRQ L

02
B2
82
82

201¢
8010
@21E
2a1F

89034
280835
02036
02037

DAPL
DAPL
DAPL
DAPL

M8229
M8229
Mg229
M8229

CPTX
CPTX
cPTX
CPTX

IDPN
IOPN
IDPN
IDPN

ga20

90040

DAPL

M8229

CPTX

IOPN SP2 ADRY L

po22

goede

DAPL

Mg229

cPTX

22
a2

0018

2021

enes

2024

22
e

2026
ea27

@925

CLLTB]

DAPX
DAPX
DAPL

DAPL

M8229
MB8229
Ma229

M8229

CPTX

SP1
SP1
S$P)1
SP2

ADRY
ADR2
ADRI
ADRO

IDOPN SP2 ADR2 L

IDPN 8$P2 ADR3 L

20043

DAPL

Mg229

cPTX

IDPN PRN @ |

2004y

DAPL

M8229

CPTX

IDPN PRN | L

geeus
2UB4T

DAPL
DAPX

M8229
M8229

cPTX
CPTX

IOPN PRN 3 L
RESERVED

*30US

DAPL

M8229

167

CPTX

L
L
L
L

10PN PRN 2 L

V-BUS DIRECTORY (CONT)

CHAN

82
02
e2
02

BIT

(HEX)

(OCTAL)

2028
2929
2024
9028

fnese
enasy
oees2
20053

902C

20054

MODULE

1.9,

SIGNAL

1cLY
ICLA
ICLA
ICLA

M8231
M823 1
8231
8231

CPTX
cPTX
cPTX
cPTX

WCSC
SBLM
SBHL
SRHE

1CLA

M823 4

CPTX

NaMg

WCS EVEN PAR W
TIMO CNF INTR
FAULT INTR M
SBI ALERT R MW

SBLM CRD RDS

INTR |

@020

200ssS

ICLA

M8231

cPTX

SBHK COMP INTR M
SAHE $B]
SBHME SBY

REQRT R H
REQ6 R

92
02
22
82

eele
003l
2032
2433

20060
20061
8ro62
20063

1CLA
ICLA
IcLe
ICL8

M8231
MB23y
MB231
M8231

cPTX
cPTX

SBHE SBI
SBME SBI

REQS R M
REQU R TM

CPTX
CPTX

ICLB
ICLB

ACT 4 M
ACT 3 &

20064

ICLB

M823 1%

cPTX

243S

ICLB

arges

IPL

ACT

1cLB

M8231

nA3e

cPTX

WCITY

ICLB

ICLA

IPL

M8234

ACT

cPTX

ICLB

IPL

ACT

@ w

02
82

LF]
e

202E
202F

20056
gaesy

837

avaeT

LR Y)

aRaTe

ICLA
ICLA

M8231

cPTX

ICLC

mM823y

CPTX

2039
¥A3A
7238

fdaTy
avare
feaTy

1CcLC
1cLe
ICLC

02
02
02
02

©#a3c
aa3n
203E
203F

eeavy
nanTrs
neave
20077

ICLC
ICLD

1CLD

02
02

2040
204t

nojep
22101

1CL0
ICLD

a04?2

22102

1cLe

ICLD

ae4l

°R123

ICLD

B2
Fs

AQuu
an4s

ev104
2010s

1CLD
ICLE

02
02

]
82

82
e2
v

AR46
204y

Quus

2949
VOUA

2¢43

fe110

2r1 11
anLy12

42113

apuc

LIRY

va4D

2n115

82
02

@I4E
.11 4

@2
82
22

2052
9051
pes2

ARy
ea1ay

aas3

1CLE
ICLE

ICLE

ICLE
ICLE

1CLE

MB23¢
mM823y
mMB23y

MB23¢

M8231
M823 4

CPTX
CPTX
cPTX

CPTX

CPTX
cPTX

M8231

cCPTX

M8231
MB234

IPL
IPL

CEXRJ PRIOR 2 H

CIAS CNSL RCV INTR H

CIBS CNSL XMIT INTR W
CEHC TRAP CODE2 (1) MW

CEHC TRAP CODEY

(1)

cPTYX
cPTX

CEHC TRAP CODE@
CEWP 1D30 W

(1)

MB231

CPTX

CIBN

mMa23y
M8231

CPTX
CPTX

RESERVED
ODPS BRANCHY W

mMB23

M8234
Ma23y

MB23t

MR231
MB2131

“a231

cPTX

CPTX
CPTX

cPTX

TRCE STALL+SVC L

DDPS
DBPV

BRANCHI

BITY)

BITO

NDPS BRANCHA

cPTX

DBPYV

CPTX

IRCH

BRCY

1CL?
IcL?
ICLE
1CLE

mMa23y
mMB23
MB23

MB23 1

168

CPTX
CPTX

CPTX
cPTX
CPTX

CPTX

DBPV BR BIT2 M

MB23 1

MB231
MB231

REQ

DEPY BR BITI W
DDPS BRANCH2 W

cPTY
CPTX

CPTX

HALTY

M8231

pa12e
an121
80122

CEHJ PRIOR | MW
CEHJ PRIOR @ W
CENR INTR REO L

1CLE

ICLE
1CLE

2 W

CEHJ PRIOR 3 M

ICLe

eR11e
f2117

0123

cPTX
cPTX

1CLe

b2
22
02

8231
M8231

IRCH BRCO W
IRCF OPC @ MW

TRCH READ 0P H
RESERVED
ICLE REM BEMX S2

ICLE REM BEMX 81

W
W

V-BUS DIRECTORY (CONT)

20aS4

00124

20%8S

A28

2056
aARsY

272126
na127

ICLE
ICLH
ICLM
ICLTM

M8231

cPTY

MB231

CPTX
CPTX
CPTX

M8231
M8231

nass

20139

1CLH

MB231

ans9

ne431

B0SA
2058

na132

ICLw
ICLM
ICLH

M8234
MB231
mM8231

8231
MB231
8234
Mg23y

an133

PASE

20134
2135
21136

BASF

00137

0L
ICLy
1CLJ
ICLJ

aasc

aash

cPTY
CPTX
CPTX
CPTX

CPTX

ICLE REM BEMX 80 M
ICLH ID TO PSL H
ICLH 1D YO VECT L
ICLK ID TO CES W
ICLH
ICLH
ICLH

ID YO ATMP
ID TO BTMP
IDM 82 L

TCLK IDM 81 L

ICL+

IDOM SO L

CPTX
CPTX
CPTX

DDPR
ODPR
DDPR

8C@S
8CB4
SC@3

(1)
(1)

W
W

(1)

8CB2
SC231
SC@2

(1)
(1)
(1)

M
M
H

enean

Prd1ue

IcLy

M8231

cPTY

DDPR

2061

ALYy

MB23}

CPTX

DOPR

2062

2ngde

MB231

0263

rat4Ly

10LJ
1CLJ
IcLy

MB231

CPTX
CPTX

DDPR
1ICLJ

mM8231

CPTX

ICLJ ID 70 0 L
DOPN EALUGY W
DDPN EALUs? |
RESERVED

Pde4d

Av1UY

8065

28145

8066

na1de

2967

an1ay

1CLJ
ICLK

ICLK
ICLX

MB23y
MB23y

MB231

169

cPTX

CPTX
ceTX

{
|

V-BUS DIRECTORY (CONT)

DWG

MODULE

1,8,

SIGNAL NAME

ANABEA

TRMD

MR22?2

cPTX

TRMD D TO TMD L

aag2

eeee

TRMD

MR222

cPYX

ARG

PE I

TRMF

MB222

03
23

¥Ire
aenT

LIPS
au@ny

CHAN

RYTT

RIT

(HEX)

(0CTaL)

apiny

apnl

*nas

03
03
03
o3

eepe
ARR9
PARA
AUAR

(l’d

o3
03

o3
23

LTS

peAdY

CPTX

TRMD MASK TO MD L

TRMB EN TP DRIVERS L

TAMS CPY@

TRMF GRP @ WP L

TRMF GRP 1| wP |

MB222
MAaR222

CPTX
CPTX

CAMU TR GRP @ MATCH H
CAMU TR GRP | MATCH W

eprtle
puntt
APy
P013

TBMU
TRMY
TRMW
TRMX

MB2?2
magee
MBR22
MB222

CPTX
CPTX
CPTX
CPTX

CEHE CMODDC ADRS TRAP |
CEHE PAGE TRAP W
CEHME CS PAR ERR M
RESERVED

ARy

TRMN

Ma22

CPTYX

USCR ABORY CYCLE H

areLe

TRMX

MB222

CPTX

RESERVED

aca2e

TRMK

MB222

CPTX

SBLB SRI PA 29 {

nruee

TRMK

MR222

CPTX

SALA

017

CPTY

TRMC
TRMC

@20QF

110

Mg222

CPTX

CPYTX

P¢rts

a1y

TAMS

MB222

fAFNE

xean
CANE

T8MD

2veet

TRMF

TAMN

TBMY

TBMK

TBMC

Ma222

MB222

CPTX

MR22?2

cPTX

Mag222

CPTX

IRCKH IR WRITE CHK H

TRMU CANCEL L

SBL8 SBI PA 10 L
SBI

a1y

neR23

23
23

2vtd
eais

w2y
age2s

TRMX
TRMX

MB222
Mg222

CPTX
CPTYX

RESERVED
RESERVED

aney

TRMW

Ma222

CPTX

SALY STALL L

2216

720026

TBMX

nALe

nenle

TBMX

2018

Pea3y

TBME

o3
93

"wnie
BeLA

209234
pRe32

Ma222

cPTX

CPTX

SBLS

RESERVED

MB222
MB8222

cCPTY
CPTX

RESERVED
RESERVED

CPTX

IB ERR LTH H

TRAMX
TRMX

MB222

TRAMC ENABLE 1A K

CAMV MODIFY |

23
03

woLc
aeLn

woela
P0a3s

T8MR
TRMB

mMa222
MR222

CPTYX
CPTX

CAMV PROTECT CODE @ L
CaMy PROTECT CODE 1 L

Lratd

aney?

TRMR

mMga2e

CPTX

CAMYy PROTECY CODE 3 L

AP1E

ra2¢

opede

2pe2
f223

enade
erpul

wp21

03
03

é3

vate

10P &

MB22>?

¥8223

CPTX

CaMy PROTECT CODE 2 L

cPrR

IDPA RUF BReT(1)

cPTQ
cPTe

IDPA RUF BReS(1)
1DPA BUF BO=4(1)

K
M

IDPA BUF RO=g(]) TM

PRy

I1DPA

M8223

cPre

pRRdy

1DPA

M8223

cPTo

I10PA BUF Bye3(1)

CPTR

10PA BUF BRPe1(1)

a02s

neR4s

ap27

eauY

nazge

TBMR

AANUG

10PA
10PA

JDPA

10P&

10PA

mM8223
MB8223

MB8223

%8223

M8223

170

cPTER

cetTa

IDPA BUF BDe2(1) K

IDPA BUF ROeR(1) W

V-BUS DIRECTORY (CONT)

@3
23

WoR
ag29

2rASQ
BAesy

Wia2A

pase

10PA
10PA

M8223
M8223

IDPA

CPTo
cPY®

IOPA
10PA

BUF
BUF

10P4

IDPA

W
W

23053

CPTo

Bi=T(1)
Bles(1)

nR2R

MB223

BUF

ceTe

B{eS5(1)

IDPA

BUF

Bled(t)

v3
v3

au2c
pazn

23
v3

neasy
#PUSS

vwo2k
Ne2F

wasSe
wopsy

TDPA
1DPA

1DP 4
INDPA

M8223
M3223

CPT2
cPTR

IDPA
IDPA

BUF
BUF

Rie3(1)
Bie2(1)

enee

2231
wag3e

eest
LY

23
L

©¥iag3

APALT

Pa3y

M8223
MB223

CPTe
cera

10PH

MB223

IDPH
I0PH

M§223
M8223

CPTo

10PH

cPTA
cPT@

MB223

cere

CPTX

IDPA
IDPA

BUF
BUF

IDPH

18C

INPH
IDPH

IBC
IBC

IDPH

Blef(l)
Bled())

2(1)

3(1)

1(1)

IBC @(1)

W
W

nea6y

1CPH

0035

Mg223

00065

IDFH

MB8223

0036

CPTX

00066

IRCE

SAVE

ILFA

¥B223

0037

CFTO

00067

IIFA

IDFA

VAX

¥8223

CFTX

IDFA

DST

0038

00070

0039

1S (=N

00071

MB8223

INFX

IE READ DIATA

I1DPH CLR

L
H
MODE

CRTX

003aA

00072

MB223

SELR

CFTX

003K

MB8223

RESERVED

1DFJ

0007X

CFTO

10E)

M8223

CPTX

ILFJ COUNT H

IDFJ

FLUSH

003C

00074

IS (2N

003D

00075

nrd

M8223

CFTX

INFJ

003E

00076

VAL (1)

1DFJ

M8223

CPTX

IDFJ

003F

VAL(O)

00077

1nFJ

M8223

CPTX

IDFJ

VAL(O)

MODE

0040

00100

M8223

CPTX

IDFJ BS VAL (1)

CRTX

0041

IRCD

00101

IDFM

M8223

0042

CPTX

00102

IRCDH

I0FM

SEL

LONG

MB8223

0043

CFTX

00103

IRCIr

IDFM

SEL

WORD

M8223

CPTX

IRCD

SEL

BYTE

0044

00104

I0FM

M8223

CPTX

0045

IRCE

00105

CTX

0046

TDFM

00106

MB8223

IDPL.

CFPTX

IRCE

CTX

0047

00107

CPTX

M8223

IDFX

M8223

IDFL

CFTX

ID'

BUS

RESERVEI

XCVUR

0048

00110

ILFM

0049

M8223

00111

CFTX

INFM

IDFM

MB8223

004a

CPTX

00112

IDFM

RIT

M8223

004K

CPTX

00113

ILFM

IDFM

DEST

M8223

CPTX

IDFM

DELTA

004C

00114

I0FM

M8223

DELTA

CFPTX

0040

IDFM

VAXSL

00115

IDFM

M8223

CFTX

004E

IDFM

00116

DELTA

I0FM

004F

MB8223

00117

IDFM

M8223

CFTX
CFPTX

TEMX
TEMX

VA
VA

01
00

EN L

DEST

H
H

0050

00120

IRCH

M8224

CFTX

0051

TEMX

00121

ERR

IRCH

M8224

CFPTX

TEMX

0052

MISS

00122

IRCC

0053

M8224

00123

CFTX

IRCX

CEHH

MB8224

FFDI'

RIT

CPTX

RESERVED

171

V-BUS DIRECTORY (CONT)

RIT

DWG

MODULE

T.S.

03
03
03
03

0054
0055
0056
0057

00124
00125
00126
00127

IRCE
IRCJ
IRCJ
IRCHM

M8224
MB224
M8224
MB8224

CFTX
CFTX
CPTX
CPTX

IRCE IR ADVANCE H
IRCS SF2 CON 1 H
IRCJ SF2 CON O H
IRCM DATA EN L

0058

0059
005A
O0SR

00130

00131
00132
00133

IRCE

M8224

CFTO

ICLD SERVICE H

03
03
03

005C
oosn
00SE

00134
00135
00136

IRCC
IRCC
IRCC

MB224
MB224
M8224

CFTO
CFTO
CFTO

IRCC EXEC CT O H
IRCC EXEC CT 1 H
IRCC EXEC CT 2 H

03
03
03

(HEX)

005F

(OCTAL)

00137

IRCE
IRCE
IRCE

IRCX

M8224
MB8224
MB8224

MB8224

172

CFTO
CrTO
CFPTO

CFTO

ICLD SERVICE RIT
ICLD SERVICE RIT
ICLD SERVICE EIT

RESERVED

T
x

BIT

)=
O

SIGNAL NAME

CHAN

V-BUS DIRECTORY (CONT)

2000

DWG

CamMp

M8220
M8229
Mg220

anal

neees

CAMB

M822@

20094

CAMA

é90S

a009s

CAMB

2206

20007

aea7

CAMB

M8220
M8220
Ma220

goepay

CAMS

M8220

sontn

cPTX

CAMS
CANMS
CAMY
CAMY

GO
GO
Gi1
G1

ADR PAR
ADR PAR
ADR PAR
ADR PAR

Mge2a
Mag220¢
M8220

CPTX
cPTX
cPTX
cPTX

CAMY
CAMyY
CamMy
CAMy

G1 ADR
T8 PAR
T8 PAR
T8 PAR

mg22e
Mg22n
mg22p
Mg22p

cPTX
cPTX
cPTX
CPTX

CAMK Gy MATCH H
CAMK GO MATCH M
SBLN $81 MISS DATA
$BLN 881 MISS DATA

2" 11.]

20013

CAMT

M8220

PQBF

fea17

CamMy

(1.3

a20e20

€ AMK

[ 'B
B!

poely

CAMK

Aen22

CAMP

ea13

RAn23

CAMP

“waty

”0024

CAMM

24
vy

2215
a1s

2pe2s
83026
ezt

CAMM

ADR

M8220
M8220

onty

CaMM

CAMM

M8220

Mg22@

CPTX
CPTX

cPYX
CPTX
CPTX

CAMM

CPT3
CPY2

CAMM

CPT1

CAMM

CPTY

aeL8

2230

CAmP

Mg22a

cPTYX

0203y

Camp

2014

1Y)

20032
72033

CAMP

CPTX

cAMP

Ma22¢
MB22¢
mg22e

eaic
2210

M822e@

QR1E

CAMB
CAMX

en1F

20ea3Y

CAMB

mMg220
MB22¢
mMg220

CaML
CAML
Camg
CAML

vaze

2094e

2021
0a22

26042

2023

20043

Q2941

o224

20044

84
a4

222s%
2a26

2004s

RroQ4e

8m27

gaedy

CAML
CAML
CanmMg
CAML

M8220
m822e
M8220

mMg22a

mg229
mga2e
mg22n
Ma22@e

173

CPTX

CAMP G!

CAMP

WRITE
WRITE

SBHN FORCE
SBHF FORCE

CAML
CAML
CamL
CAML

BYTE
BYTE
8YTE
BYTE

CAML
CAML

BYTE
BYTE
BYTE
BYTE

CAML

MISS

CPTX
cPTX
cPYX
CPTX

CaML

61
G@

ENABLE
ENABLE

RESERVED

CPTX
CPTX
CPTX
CPTX

MW
MW
H
M

MISS Gy M

CPTX
CPTX
CPTX
CPTX

CAMB
TBMX
SBHF

{ 0D
© 0D
2 0D
{ 0D

]

H
W

B
8

Ll
o YN, V]

CAMY

CPTX

CAMM

LYR RN

20934y

a003s
2ve3e

CPTY
CPTI

CPT3

2219

PAR
2 MW
{ H

cPT2

FIELD

FIELD | H
FIELD 0 TM
PAR 2 0D M

M8224
M8220
M822n
MB22@

¢y

CAMT

CAMYV

PAR

CANMS
CAMg

CAMT

PAR
PAR

araty

CAMU

REV

ko012

e0ntd

FORCE ERR 2 |
FORCE ERR | L
FORCE ERR @ L
REV PAR FIELD

REV
REV

QNG
A

20015
22016

CPTX
CPTX

TBMX

NAME

SBHF
SBHF
SBHF
CAMS

2009

anec

TBMX
TBMX
SBHF

CAMP

CANP

eeep

CPTX
CPTX
CPTX
CPTX

fnaaa
esnoy

AIRE

SIGNAL

enraee

-1

7.8,

3131

Llad7d.]

MODULE

oaa2

817
(OCTAL)

LAYCH VALID BIT
FORCE ERR 3 |
REV PAR FIELD 3

PAR
PAR
PAR

PAR

PAR
PAR

H
M

M
L

XIXTIXX

BIT

(HEX)

IXITX

CHAN

V-BUS DIRECTORY (CONT)

NAME

817

DWG

MODULE

T.8,

SIGNAL

(' J14
0RAAS1
enes?2

4228

BAeS3

cPTX
cPTX
CPTX
cPTX

CAML
CAML
CAML

CamML
CAML
CAML
CaMy

MB229
Ma229

naz29
2024A

04
L]

ea2c
ae20

28054y

@3t
0a2F

Mg22¢n
mMga2e
MA227

CPTX

04
04

caMR
camMB
CAMB
CAMB

Ma22¢

cPT1

CamMB
CAMB
CaMB
CAMB

TAG PAR 2 EVEN M
EVEN M
TAG PAR
TAG PAR @ EVEN W
PA LATCH 12 M

MR220
MA220%

cPTY

CAMB

LATCH

cPTY
CcPTY
cPTY

Camg PA
CAMB PA
CAMB PA

LATCH
LATCH

LATCH

CPT1
cPTY
cPTH
cPTY

Cavg Pa
CAMB PaA
CAMB PA

LATCH
LATCH
LATCH

2033

22063

CAMB

M822¢
Mg2@

MB22@
MB822¢

wela

ana6d

CAMB

2923%

n1B6S

f336

anase

[1]

0n37

20067

CAMB
caMB
CAMB

0038
2039

eeave
ovoT1
eae72

CAMB

M8220

cAMB

NB22¢

CAMS

neer3

CAMB

MB226
mMg220

20074
0ders
22076

CAMB

mM8220

04
04

003A
eo3s

ee3’

0830
003k
oa3F

Mg22n
MB22¢

cPTY
cPT1
CPTY
CPTY

CAMB

M8229

CAMB

Ma22nm

CPTH
cPTH
cPTY

LATCH

CaMB PA

LATCH

CaMB

CAMB PA

LATCH

CAMB PA

LATCH

CAMB

LATCH

CamMB Pa
CAMB PA

LATCH

CAMB

LATCH

2a877

CAMB

MB220

cPTH

00109
ey
eeie2
29103

COMX
cOMX
comMX
coMy

M8221%

cPTX

M8221

cPTX
CPTX
cPT2

comy
coMU
cOMy
coMu

Mg221
mMa221
MB221

cPTH

RESERVED

cPTY
cPTH

comMy

eeu?y

28104
ee10s
22106
ee107

2048
2049
P04A
agas

L BRY

CoMT

mMa221

- LARB!
0112
20113

coms
COMS
COMS

mMg221
mMaaey
MB221

20114
ea11s

COMS
coMS

Mg2214

20940

OAUE
2a4rF

20116
09117

coms

0040
2041

804
@43
0044

eeus
2246

eaac

coMs

MB221

M8221

Mg221

mM8221

174

CcPT1

cPTX
cPTX

CAMA

Irrrx

XTIXTX

CAMB

cAamMB
CAMR

nrR62

AVe60

2361

ne32

[

nazae

2031

00
EV

IXIXIcx

8y
24

cPTX
CPTX

~n
~

2205S
anasSe
anas?

MB22V
MB22n

i PAR
1 PAR
9 PAR
] PAR

GO AYTE
Ga BYTE
G@ BYTE
CAML G@ BYTE

IIITX

na2e

(0CTAL)

BIT
(HEX)

XITIXIX

CHAN

RESERVED
RESERVED
RESERVED

coMu CPT2 M
RESERVED

coMy
TBMD

cPTX

coMS
CDMS

CPTX

COMS

CPTX
cPTX
CPTX
CPTX

coMs
COMS
COMS
COM8

CPT1
CPYY

a4
A

L
H

EN COM DATA L
61 B3 PAR 00D H
Gt B3 PAR EVEN W
] B2 PAR 00D H

B2
81

PAR
PAR

EVEN H
0bD H

81
BR

PAR

EVEN

PAR

000

V-BUS DIRECTORY (CONT)

(1]
LT
04

2050
2051
008%2

eoi2e
eo12¢
ed122

COMS
CDOMR
COMR

M8221
m8221
LLYZ3!

CPTX
cPTX
cPTX

CDMS Gy BP PAR EVEN H
COMR G@ B3 PAR ODD H
COMR G@ B3 PAR EVEN M

g
24
04
ea

2084
2a5S
2056
2057

90126
#2125
00126
ee127

COMR
COMR
COMR
COMR

M8221
M8221
MB221
MB221

cPTX
cPTX
ceTX
CPTX

CDMR G@ 82 PAR EVEN H
COMR G@ Bi1 PAR 0DD TM
CDMR G@A B8] PAR EVEN M
COMR GO B@ PAR 0DD H

04
04

2958
2059

00130
29131

COMR
cOMX

Mg221
MB8221

cPTX
cPTX

COMR G@ B PAR EVEN M
RESERVED

0058

22133

CDOMH

M8221

cPT1

COMH ADDR LATCH 11 H

By
ey
04
04

205C
205D
oase
00SF

22134
2043%S
90136
20137

COMKH
CNMH
COMM
COMM

o060

0062

#o142

8264

92144

2066
02067

ge{46
@e147

24
04

008%3

20S8A

1. I'Y}

1.1}

90123

e2132

0¢149

COMR

COMX

COMKW

MB221

M8221

M8221
me221
M8221
MB221

CPTY
cPTL
cPTY
CPTY

RESERVED

CDMH ADDR
COMH ADDR
COMH ADDR
CDMH ADDR

LATCH @ H
LATCH § W
LATCH 8 H
LATCH 7 H

M8221

cPTY

COMM ADDR LATCH &6 M

cPTy

COMM ADDR LATCH 4 H

COMHW

mMa221

00143

COMM

mMB221

COMM

cPTX

COMR G@ B2 PAR ODD MW

Ma221

90141

COMM

cPTX

M8221

cPTY
CPT}

CPTY

COMH ADDR LATCH S M
COMH ADDR LATCH 3 H

COMH ADDR LATCH 2 W

P014S

COMB

M8221

CPTX

SBHF REV PAR 3 |

2068
2069
0064

20150
00154

COMB
coMn

92153

COMX

M8221
MB221
M8221

cPTX
cPT3
cPT3

SBHF REV PAR @ {
CAMP Gi WRITE ENABLE M
CAMP GO WRITE ENABLE M

806C

20154

o0a6rF

00157

02865

8y
04
04

04
24

24
04

2268

0060
206E

20152

20155
20156

COMA
COMB

CDMB

COMA

CDMA
CDMA

COMA

M8221
MB8221

MB221

m8221

mM8221
mM8221

M8221

175

CPTX
CPTX

cPTX

CPT2

cPTR
cPTR2
cPT?2

SBHF REV PAR 2 L
SBNF REV PAR | |

RESERVED

COMA MASK 3 H

COMA MASK 2 W
COMA MASK § H
COMA MASK B W

V-BUS DIRECTORY (CONT)

CHAN

81T

BIY

(HEX)

(OCTAL)

[F.IT]

nanng

onet

ages

02003

es
oS
2s
es

LLLL
rRARS
LLTTY
2207

LT F)

peanry

22082

SBLHN

SBLF

8BLF

MODULE

M8218

MB218

7,8,

cPYX

cPTX

SIGNAL

NAME

SBHP EN 1D DRIVERS |

SBHP 1D ADOR 2 L

CPTX

SBHP ID ADDR | L

CPTX
CPTX
CPTX
cPTX

88LS ADRS LATCH 29 H

SBLE

MB218

ANAAdY
0004S
2anaae
LT3

8BS
LLIR
$8LP
SBLF

MB8218
MB218
M8218
MA218

2008

.LLRY

s8LMTM

“8218

CPTX

SBHN CRD L

os
s

anaa
faas

ene12
evo1y

sBLp
SBLP

M8218
mM8218

CPTX
CPTX

TBMN BUF UMCT
TBMN BUF UMCT

05
es
es
os

eanc
2890
NRRE
eooF

enaiy
aP01S
peate
22017

SBLP
S8LP
saLe
SBLM

MA218
MB218
M8218
MB218

cPTX
CPTX
cPTX
cPYX

TBMN
TBMN
TBMN
SBHN

es
s

anto
ant

frp2e
pe@2y

$BLR
SBLE

MB218
“B218

cPTX
cPTX

SBHM SET
SBHM SET

2829

2012

22011

nag22

s8LP

$BLL

2n13

aee2sy

SBLE

aeyy

nag24

SBLK

os
es
es

vs
es
0s

MB218

SBLK

MB218
MB218
M8218

LELYT)

SBLC

MB218

$BLC
$8LC
s8Lc
S8LC

MB218
M8218
MB218
M8218

SBLC

MB218

en22

¢s

0023

20043

PRy

fRa4y

SB8LC

MB218

2026
au27

2404e
20047

SBLC
$BLC

8218
8218

(4]

es
os
0s

2p2s

¥n28

AB9

LEFYY

ee2e

Arauy

2A842

argys

2ApSQ

000S1

oues2

20053

$BLC

sALC
8BLC

SBLC

S8LC

SBLC

$BLC

SBLC

INVALID (
SBI CYCLE W

cPTX

SBLX
$BLX
SBLC

naz2o

UMCY 3 |
UADS
UFS |
|

MB218

ganlp
00031
22a32

20034
2293s
22023¢s
nees?

BUF
BUF
BUF
RDS

§ L
2 L

SBHM ANY READ DATA L

pnis
ae19
2314

paLe
weip
fNLE
BALF

TBMN BUF UMCY @ L

cPTYX

MB218
M8218
MB218

0s
es
es
es

10PJ IB REQ M

SBLP MD TO D L
88HP 1D ADOR @ |

MB218

$8LD
SBLwW
SBLR

20033

IA w

SBHR

n002%
00026
avne2y

dais

CPTX

TBMC ENABLE

cPTYX

2u1s
0216
1?7

MB218

cPYX

mMg218

M8218
M8218

M8218

MB8218

M8218

176

cPTX
cPTX
cPTX

cPTX
CPTX
cPTX
cPTX

cPTX
cPTX
CPTX
CPTX

CPTX

SEND

DATA

LAYCH TIMO REG L

TBMU CANCEL L
CLKL 8YS INIT B L
SBLR FORCE SBI L

RESERVED
RESERVED
SBLC WRITE DATA @0 W
SBLC

WRITE

DATA

SBLC WRITE DATA
SBLC WRITE DATA
$BLC WRITE DAYA
SBLC WRITE DATA

02
@3
94
O0S

H
W
W
W

SBLC WRITE DATA Q6 K

CPTX

SBLC

WRITE

DATA

CPTX

SBLC

WRITE

DATA

CPTX

SBLC

WRITE DATA

1@ H

cCPTX
cPTX

SBLC
SBLC

WRITE DATA
WRITE DATA

12 W
13 H

cPTX

cPTX
CPTX

CPTX

WRITE DATA Q8 H

SBLC WRITE DATA 1t H

8BLC
SBLC

WRITE
WRITE

DATA
DATA

TBMD EN 3B] DATA

BUS

BYTE

t4 W
1S

PAR

W
MW

V-BUS DIRECTORY (CONT)

.I'F 19

VA2E

1LY

L1146

70056

SBLA

Mg218

cPTX

BUS MD BYTE t PAR M

CPTX

1CLe IPL ACT @ L

SBLS

MB8218

cPTYX

avas?

sBLA

MB218

cPTX

we2op

200855

@92F

8218

SBLS SELECY SBI ADR L
ICL8 IPL ACT 1 L

16
17
18
19

DATA
DATA
DATA
DATA

H
H
H
W

o5
0s
es
es

2030
rayy
8032
2733

nap6e
gd061
o0n62
20063

8BMHB
$B8HB
SBHB
8BMB

M8219
M8219
MB219
8219

CPT3
CPT3
CPT3
CPTY

SB8HB WRITE
SBHB WRITE
88HB WRITE
88HB WRITE

0034

0AP6u

SBHB

M8219

CPT3

SBHB WRITE DATA 20 H

M8219

cP13

M8219
M8219

cPT3
CPT3

es
es
es

2238
fase
2937

00068
20066
70067

LLLT]
8BHB
SBHB

2238

eap70

SB8HB

os
os

2834
o038

#e@72
pA@73

SBHB
SBHB

(4]
os
es
s

283C
203D
003E
a03F

M8219
MB219
M8219

M8219
MB219
M8219
M8219

cPT3
CPT3
CPT3
CPT3

SBHB
SBHR
SAMB
$aHB

S8HB

M8219

cPTI

S8HB RECEIVE MASK @ W

22103

8BHB

SBHWB

M8219

CPTI

SBHR RECEIVE MASK 2 M

PP874
ee@7S
20076
20077

SBHB
SBHB
SBHB
SBHS

2040

foi0e

8042

201082

oe4s

SBHB WRITE DATA 24 H

SBHR WRITE DATA 25 W

8219

2041

SRHB WRITE DATA 21 H
SBMB WRITE DATA 22 H
8BHB WRITE DATA 23 M

cPT3

s8He

2239

cPT3
cPTS
CPT3

20071

ne1ey

S8HA

M8219

M8216

CPT1H

cPTY

SBHB WRITE DATA 26 H
SBHB WRITE DATA 27 H

WRITE
WRITE
WRITE
WRITE

DATA
DATA
DATA
DATA

28
29
32
33

W
H
H
H

SBHB RECEIVE MASK | M

SBHB RECEIVE MASK 3 W

és

or4y

PAI04

SBHD

M8219

CPTX

BUS MD RYTE 2 PAR W

s
os

2046
2047

0a106
08107

$BHA
SBHL

“8219
Mg249

cPTX
cPTX

SBHA BUFFER FULL L
SBLE LATE EXPECT RD L

SBHE
SBHE
8BHE

M8219
M8219
M8219

204s

22105

00119
201114
2112

8$BHWD

M8219

CPTX

CPTx
CPTX
cPTX

BUS MD BYTE 3 PAR H

SBLE REC PAR 2 W
SBLE REC PAR | H
SBLE REC PAR 2 W

U1
es
es

onus
2049
POUA

Qeuc

2940

SBHM

M8219

TR SEL 2 L

PBUE
BA4F

90115

CPTX

es
s

M8219
M8219

cPTX
cPTX

TR SEL 4 L
TR SEL 8 L

gese

poi2e

SBHR

MB219

cCPTX

TBMN BUF UMCT @ L

s
es

eas2
20s3

0122
22123

$BHR
SBHR

M8219
M8219

CPTX
CPTX

TBMN RUF UMCT 2 L
TBMN BUF UMCT 3 L

0054

os
es
es

2a4p

2951

205S
28056
2es7

P2113

LLISY]

20116
29117

en121

90124

22125
8a126
00127

SBHE

SBNM

SBHM
SBHM

SBHR

SBHR
SBHM
SBHR

M8219

M8219
M8219
“g219

177

CPTX

CPTX
cPTO
CPTX

SBLE REC PAR 3 H

TR SEL 1 L

TBMN BUF UMCT

TBMN BUF UADS L

TBMN BUF UFS L
SBHM SELECTY SRI ADRS L

SBHR TRANS ENABLE L

V-BUS DIRECTORY (CONT)

CHAN

RIT
(HEX)

oS
es

es
es

BIT

058

20132

a9SA

90132

20959
o0s8

20SC
2esD

1114

CoCTaL)

29131

24133

SAMD

SBHE

SBHR

MODULE

M8219

M8219
M8219

SBHM

MB219

en134
2013S

SBHS
SBHM

MB219
M8219

20136

SBHM

M8219

T,S,

CPTX

SIGNAL NAME

TBMD EN SBI

SPLE TRANS PAR |

CPTX

CEHK CUR

CPTX
CPTX

CLKL SYS INIT B L
CEHN CUR MODE | W

CPTX

SBLL TRANSMIT Ca

e0SF

92137

SBHX

M8219

CPTX

RESERVED

2A6Q

20140

8BHX

MB219

CPTX

RESERVED

0062

20142

$BHX

M8219

CPTX

RESERVED

os
14
os
os

2s
es

os
es
os

1-I'S |

0063

2964
0065
2066
0067

2068

0069

@064A

0068

- 1.TY

206D
@06E
206F

Pe14y

AB143

ea1ay
POL14S
eatde
PO147

891%@

S$BHX
SBHX

SBHY
SBHX
SBHX
$BHX

SBHX

MB8219

MB219

M8219
M8219
M8219
M8219

M8219

CPTX

RESERVED

CPTX
CPTX
CPTX
CPTX

RESERVED
RESERVED
RESERVED
RESERVED

CPTX

$BHYX

M8219

CPTX

22153

8BHX

MB219

CPTX

90152

00154

A015S
20156
92157

SBNMX

SBHX

SBHX
$BMWX
8BMX

M8219

MB219
M8219
M8219

178

RESERVED

CPTYX

00151

CPTX

CPTX
CPTX
CPTX

MNDE

@ W

TRMN DIS PROT L

DATA |

CPTX

RESERVED

RESERVED
RESERVED

RESERVED

RESERVED
RESERVED
RESERVED

V-BUS DIRECTORY (CONT)

CHAN

a1T

(HEX)
26

anne

BIT

DwG

MODULE

T,S8,

SIGNAL

FCTP

M8269

CPTX

DAPL

(OCTAL)
panee

ACC

CONTEXT

FCTC

CLR

(

FNME
FCTJ
FCTC
FCTC

BUS, EXP L
ACC N DATA
ACC Z DATA

M8289

cPTX
CPTX
CPTX
CPTX

M8289
MB8289

ceT3
cers

FCTD RA ADRS 3 L
FCTD RA ADRS 2 L

M8289

cPT3

290921

2402

Jel R}

ArAn2

FCTC

M8289

CPTX

26
e
v
0o

2404
@ros
nAd6

FNME
FCTJ
FCTC
FCTC

M8289
48289
M8 289

aRay

arRaY
AA@0S
neeae
ad0n7

e
113

naae
2209

nr@a1Q
n3a11

FNMY
FNMT

anne

a0013

FNMT

2004

aANe

2200

nanas

pngy2

FCTP

FCTTM

FNMT

NAME

M8289

MB8289

CPTX
CPTX

CPTY

DAPL ACC RA CONTEXT

ACC

FCTD RA
FCTD

ADRS

FNMT

MB289

CPT3

AROF

M8289

cPT3

FCTP

FNMY

cCPT3

FCTP RB ADRS

nee1Y

FNMT

M8289

cPT3

FCTP

eata

@229

xXXX

mg289

CPTX

RESERVED

nat2

FNMT

M8289

CPTX

FCTE COMPL L
FADA

143

en13

20716

anQ2y

X XXX

AUR23

FNMT

M8289

48289

M8289

CPTX

FCTP

{

ADRS

| L
|

RESERVED

EALU C

@ |

LAY/

20924

FNMT

MB8289

cPTX

06
26
de

an1s
ule
2417

21025
2un2e
AAR27.

FNMY
FNMT
FNMT

MB289
M8289
M8289

CPTX
CPTX
cPTX

@6
2

"I X¥ ]
7”019

2apla
erasy

FNMY
FNMT

M8288
M8 288

cPT2
cPT2

FCTN LOAD ARG H
FCTN LOAD ARY W
FCTN LOAD
FCTN LOAD

ARX
BRY

M
H

231C
@210
A3LE

no03d

FNMT

MB 288

cer2

FCTN LOAD

BRO

FNMTY

MB288

CPTX

RESERVED

86
[T

e
Yo

143

Q¢

oa1a
2418

AALF
an2e

anpl3?2
nvely

#3038
20n3s

fa03Y

goeup

FNMT
FNMY

FNMT
FNMT

ENMT

Mg28s
MB288

M8 288
mMa288

MBa 288

cPT2
cPT2

cPTO@
cPTX

cPTY

ve
1Y
1Y

aa2t
@aa22
2023

naay
LI]. 'Y
pepus

FNMT
FNMT
FNMT

M8288
M8288
mM8288

cPT3
cPT3
cPT3

@6
1

0324
2p2s
no26

LY
2094S
LT

FNMT
FNMT
ENMT

Ma288
MB288
Ma288

CcPTy

ea27

29047

FNMY

8288

179

cPTH
cPTY
cPT!

W
H
H

DATA

ana1s

Q20E

FCTH CP SYNC M

L I-IY

SPC

(2)

FNMS EALU CIN L
FCTC SEL NORM W
RESERVED

FADS BUS_FAD L
RESERVED

FCTN FAMX EN @ L

FCTA

A GT

B H

FCTN SHF MUX ENY L
FCTN SHF MUX ENOA |
FCTN FALU FUNC
FCTN FALU FUNC

FCTN FALU FUNC
FCTN

FAMX

SEL

SEL 2 M
SEL 1| W
SEL @ H
W

cPT3

cPTY

cPT3

FCYF
4944
FCTF

an2en

e0aps3

FNMT

8228
MBo28
mMg228

cPT3

FCTF

go2C
fgen
902E

ro0SYy

FNMY

8228

0405S
-1.1- 31
20057

FNMT

MB228
8228

FNMT

M8228

cPT3
cPT3
cPT3
CPTY

FCTF
FCTF
FCTN
FCTN

o02F

180

8HF
SHF
8HF
8HF

SHF
SHF

COUNTY
COUNY

COUNT
COUNTY

XIITX

M8228

FNMY
ENMT

COUNT
COUNT
CARRY IN
FAMY SEL @ M
FALU

¥TYXY

FNMT

neest
20052

20050

n32A

en28s
8629

V-BUS DIRECTORY (CONT)

CHAPTER 6
SYSTEM BACKPLANE
INTERCONNECT

SBI CONFIGURATION

ARBITRATION

TR <15:00>

INFORMATION TRANSFER

P <1:0> (PARITY)

TAG <2.0> (TAG)

ID <4.0> (IDENTIFIER)

M <3.0> (MASK)

J‘>

B <31:00> (INFORMATION) ¥>
RESPONSE

FAULT
TRANSMIT/

CNF <1:0> (CONFIRMATION)

RECEIVE

NEXUS

CONTROL

TRANSMIT/

RECEIVE
NEXUS

UNJAM

FAIL
DEAD

FOVAN NN

INTLK (INTERLOCK)

CLOCK (6 LINES)
INTERRUPT REQUEST

REQ <7.4> (REQUEST)

>
>

ALERT

MP1-2

SPARE (2 LINES)

)
TK-0077

183

SBI PARITY FIELD CONFIGURATION

P11 PO

1ER F'ELJ

PARITY

TAG

IDENTI -

——

IflELD J L FIELD
TAG <2:0>

P<1:0>

ID <4.0>

M <3.0>

ufme

—

INFORMATION FIELD

EIELD J [

MASK

B <31.00>

]

COMMAND FORMAT
SBI CONFIRMATION

CONF1]conF2]

FUNCTION
FIELD

conDiTION

| NO RESPONSE
ACK

| ssy

ERR

—"
F <3.0>

ADDRESS
FIELD

A <27:00>

TK-0166

184

SBI INFORMATION TRANSFER FORMATS

READ DATA FORMAT
TAG

[P,Pglo 0 ol

MASK

Io 00 o]

DATA BITS

]

DATA BITS

]

DATA BITS

]

CORRECTED READ DATA FORMAT
TAG

MASK

[Pfl’olo 0 OI ) ]0 00 ;1
READ DATA SUBSTITUTE FORMAT
TAG

bPOIO V] Ol

MASK

1D IO [ OI

INTERRUPT SUMMARY RESPONSE FORMAT
MASK

TAG

[P,P({O 0 o]

Io 00 ol

DATA

lol

DATA

lol

COMMAND ADDRESS FORMAT FOR READ MASKED
TAG

IP1P0[0 1 1]

MASK

FUNCTION

[ . .lo 00 1|

ADDRESS BITS

]

COMMAND ADDRESS FORMAT FOR WRITE MASKED
TAG

IP1PJO1 1]

MASK

FUNCTION

D T . -lo 01 ol

TK-0723

185

SBI INFORMATION TRANSFER FORMATS (CONT)

COMMAND ADDRESS FORMAT FOR INTERLOCK READ MASKED
MASK

TAG

[pipdo 1 1!

FUNCTION

l. - .[o 10 ol

ADDRESS BITS

COMMAND ADDRESS FORMAT FOR INTERLOCK WRITE MASKED
TAG

MASK

FUNCTION

ADDRESS BITS

[;’ol‘“ 1] 1D l . -Io 11 1|
COMMAND ADDRESS FORMAT FOR EXTENDED READ
TAG

|P1 PJO 1 1]

MASK__FUNCTION

ADDRESS BITS

]-— - - AI1 00 OJ

COMMAND ADDRESS FORMAT FOR EXTENDED WRITE MASKED
MASK

TAG

[p1p010 1 1]

FUNCTION

I. . a .11 01 1|

ADDRESS BITS

WRITE DATA FORMAT
MASK

TAG

[P1P0|1 0 1| 10

I .. l

BYTE 3

BYTE 2

BYTE 1

BYTEOD

INTERRUPT SUMMARY READ FORMAT
TAG

IP,Polnol

MASK

looooloooooooooooooooooooooooolHlloooo]
e

REQ <7:4>
TK-8409

186

SBI FIELD DESCRIPTION

Field

Description

Arbitration Group

Arbitration Field
[TR (15:00)]

Establishes a fixed priority among nexus for access to
and control of the information transfer path.

Information Transfer
Group

Information Field
[B (31:00)]

Bidirectional lines that transfer data, command/address, and interrupt information between
nexus.

Mask Field
[M (3:00)D]

Primary function: encoded to indicate a particular byte
within the 32-bit information field [B (31:00)].

Secondary function: in conjunction with the tag field,
indicates a particular type of read data.

Identifies the logical source or destination of informa-

Identifier Field
[ID (4:0)]

tion contained in B (31:00).

Tag Field
[TAG (2:0)]

Defines the transmit or receive information types and
the interpretation of the content of the ID and informa-

Function Field
[F (3:0)]

Specifies the command code, in conjunction with the tag
field. This field is part of the 32-bit information field.

Parity Field
[P (1:0)]

fields.

tion fields.

Provides even parity for all information transfer path

Response Group

Confirmation Field
[CNF (1:0))

Fault Field
(FAULT)

Encoded by a receiving nexus to specify one of four response types and indicate its capability to respond to the

transmitter’s request.

A cumulative error line to the CPU that indicates one of
several errors stored in the transmitting nexus fault register, and the associated SBI cycle in which the error

occurred.

187

SBI FIELD DESCRIPTION (CONT)

Field

Description

Interrupt Request
Group
Request Field
[REQ (7:4)]

Allows a nexus to request an interrupt to service a condition requiring CPU intervention. Each request line

represents a level of nexus request priority.

Alert Field
(ALERT)

A cumulative status line that allows those nexus not
equipped with an interrupt mechanism to indicate a
change in power or operating conditions.

Control Group
Clock Field
(CLOCK)

Six control lines that provide the clock signals necessary
to synchronize SBI activity.

Fail Field

A single line from the restart nexus to provide a restart
signal to the CPU to initiate a system restart operation.

(FAIL)
Dead Field
(DEAD)

A single line to the CPU to indicate an impending clock
circuit or SBI terminating network power failure.

Unjam Field
(UNJAM)

A single line from the CPU to attached nexus that initiates a restore operation.

Interlock Field
(INTLK)

A single line that provides coordination among nexus
responding to certain read/write commands to ensure
exclusive access to shared data structures.

188

ADDRESS)

ADDRESS

3¢

2¢

082

190

@06

681

TR#
(Base

10)

[1]e

Physical

SBI

Address
(Hex)

20000000

8000000

20002000

80008080

20004000

8001000

20006000

8001860

20008000

8002000

2000A000

8002800

SBI

2006C000

800300¢

2000EQQQ

8003800

REQ/BR

290010000

8004000

Device

Vector
6

LEVEL

LEV

20012000

20014000

80048090

80065000

20016000

8805800

200180090

8006000

2001A000

8006800

2001Co09

8007000

2001E0AQ

8027800

TR# |

LEV

LEV 7 =11

Generation
4

NO.

1dNHYILNI ANV DNISSIHAAV HIL1SID3IY O/1 189S

(PHYSICAL

SBI

NOILVH3INID HOLI3IA

CONSOLE

SBI FAULTS (ADAPTER CONFIGURATION REGISTER)

313029282726 2524232221201918 1716151413 121110 09080706 050403020100

NEXUS TYPE CODE

PAR

|URD|MXT|

PWR|OVR

000X XXXX

MEMORY

FLT

[FLT|FLT

DWN|{TMP

00100000

MBA

00101000

uBA

XMT

WSQ

1SQ

FLT

FLT FLT

PWR
uP

—

— WRITE SEQUENCE FAULT

PARITY FAULT

—

UNEXPECTED READ DATA FAULT

—

INTERLOCK SEQUENCE FAULT

— MULTIPLE TRANSMITTER FAULT

— TRANSMITTER DURING CYCLE THAT

00101001

00101010

00101011

Y Y* MA780
010000
00110000

DR780

*YY =PORT NUMBER

CAUSED FAULT

23 —

POWER DOWN

—

POWER UP

— OVER TEMPERATURE
TK-0695

190

SBI CONFIGURATION RULES FOR TR SELECTION

The

systems.
and,

the

These

some

VAX-11/782

and

deviation may be desirable

rules are guidelines;
necessary.

cases,

The TR level of a device determines its relative priority in
High TR levels mean low priority.
competing for SBI access.
TR 1 is the highest priority and TR 15 the lowest to which any
may be assigned.

(other than the CPU)

NEXUS

The standard order of assigning devices to TR levels is:
All

000000

for

levels

selecting

VAX-11/78¢

apply

They

SBI.

for

suggested

are

rules

following

NEXUS

MS780s

All

MA780-Cs

All

DW788s

All

RH780s

DR788
C1780
CpPU

The

default

currently

assignments

used

manufacturing

are:

= TR

First MA78¢ port
First DW784@
First RH780 (for disks)
Second RH78¢ (for tapes)

= TR

CPU

= TR 16

First

MS78@

= TR 3
= TR 8
= TR 9

= TR 13
= TR 14

DR780
CI1789

defaults

These

systems,
changes

should

well

cover

some

most

(the implied TR level)

VAX-11/788

applications,

systems.

will

require

Large

field

TR levels.

When selecting TR levels for complex systems, you should try
to minimize latency effects (such as data lates) in memory
Therefore, always give memory controllers the lowest
access.

RH780s and DW78@s for
TR levels and assign the CPU to TR 16.
peripheral devices should be assigned TR levels based on the
the

devices

MS78¢s

per

sensitivity of

device

(or

to memory

controllers)

latency.

One

requires

two

consecutive

system.

levels

Interleaving

as well

with

MS780s

amounts

must

equal

levels

memory in the even/odd pair; consecutive TR levels are
When a MS780-A
strongly suggested even without interleaving.
and MS786-C controller reside on the same system, the MS7808-C
should be assigned the lowest TR level.

Zero

four

consecutive.
MS78¢ memory

MA780-C memory

One

four

MA780-Cs

per

system.

A given MA78¢ must have the same TR on all SBIs.
controllers should always have lower TRs than
ports.

DW780s

per

system.

191

SBI CONFIGURATION RULES FOR TR SELECTION (CONT)

Zero

disks

four

have

The

main

tapes.
and

RH788s

should

RH780s

memory

system.

the

Since

2.2

RP@7

1.3

RM@3,

for

the

one

3.64

RH788s

device

disk

microsec/quadword
microsec/quadword

RM8@

6.67

microsec/quadword

10.008

microsec/quadword

6250

BPI

12.24

microsec/quadword

160@

BPI

40 .00

microsec/quadword

TE16

160¢

BPI

>100.08 microsec/quadword

figures

from

define

the

times

the

device.
an

the

average

Due

occasional

average

response

RH780

time

requirement

buffering,

memory

fiqure

sector

determined

6.15

response

just

given

RH788

time

without

devices

nearly

causing

late,.

The
RP@7
at
2.2
megabytes
enough that only interleaved
expected

MA780

the

three

not

devices

than

for

TU77

withstand

data

less

used

only

TU78

These

seen

has

used

latency
requirement
is
by the device data rate:

RP34/5/6

can

RH78@s

RH788s

sensitivity

RH780

Mbyte/sec

RM@5,

general,

than

allocating

relative

the

of
buffering,
the
memory
(slightly pessimistically)
RP@7

priority

criterion

TRs

latency.

per

higher

unless

MA78¢

the

determining

device,

Zero

only

one

VAX-11/782

prevents

RP@7

VAX-11/78¢

I/0

the

level

the

DR780

for

memory
RH788s

per

RH788s

with

time

needs

considered.

suggested

system.

The

data

per
the

second or as high as 8 megabytes per
attributes
of
the connected
device.

second
faster
Since

the

DR788

may

set

one

requirement

low

that

systems

156

type

the

DR788

devices

One

CI78@

the

same

The

CI788

SBI

rate
per

(usually

system.

the

One

CPU.

(implied)

not

only

kilobytes

second depending on
156
kilobytes
per

fully

buffered,

solutions

concurrent

practical),

suggested

assigned

synchronous

peak), but it is fully
the highest TR number
than

and

The

prevention

the

and

are

I/0

may

faster

from

other

decreasing

the

setting.

level

synchronous
lates.

memory,

the

data

(interleaved)

the

DR78%

use

is slower than a TU77, while 8 megabytes per second
than any current VAX-11/780 memory will support.

experience

DR780

with

accessing

than

response

pairs that are used to interconnect VAX-11/788
same TR assignment in each VAX-11/78@.
rate

from

space.

the

device

per
second
requirement
is
high
MS780 memory can be used.
It is

application

address

fastest

function

and

each

fast

that

for

network,

CI78¢.

(8.75

megabytes

per

second

buffered.
Therefore,
(lowest priority)
of

CI780 should have
any device other

per

and

CPU.
Only

one

CPU

SBI

16.

192

supported,

must

SBI CONFIGURATION RULES FOR TR SELECTION (CONT)

10.

These

VAX-11/786

selection
and

devices.

with

systems

useful

are mainly

rules

VAX-11/782

systems

little

with

I/0

many

when configuring
fast

activity,

peripheral

the

SBI

and

memory will be so lightly loaded that TR selection has little
On the other hand, when the memory demand greatly
importance.
exceeds the capacity of the SBI and the memory, TR selection
will not make the memory cycle faster.

selection

bandwidth

megabytes

for

important

any

active

concurrently

system

DMA

with

devices

aggregate

above

two

second.

If you run out of TR levels, you need another VAX-11/78@.

The following example illustrates these guidelines for a large

VAX-11/788¢ system consisting
three RH780s,

Device

M5788-C

MA780-C
MA780-C
DW780
DW78@

RH780
RH780
C1780

of:

two

MS78¢-Cs,

one CI788.

MS786-C

RH780

and

OV
B W

two DR788s,

BRI

12.

per

1is

—

11.

193

two

MA780-Cs,

cl
Cc2
D1

D2
El

+ 5V
BUS SBI BOO

BUS SBI DEAD L

+ 5V
BUS SBI B20 L

+ 5V

BUS SBI B2l L
GND

BUS SBI BO1l
GND

BUS SBI BO0O2

BUS SBI B22 L

BUS SBI BO3

+ 5V
BUS SBI REQ4 L

BUS SBI M1 L
GND

BUS SBI REQS5 L
GND

BUS SBI TRO1
GND

BUS SBI M3 L

BUS SBI REQ7 L

+12 V
BUS SBI TRO3

BUS SBI PO L

BUS SBI TP L

F2
H1

H2
Jl
J2

BUS SBI Bl2 L

GND

BUS SBI B13 L
BUS SBI Bl4 L
BUS SBI B15 L

V6l

K1
K2
L1
L2

N1
N2
Pl
P2

GND

BUS SBI B04
BUS SBI BOS
GND
BUS SBI BO6
BUS SBI BO7

-5V

GND

+ 5V
BUS SBI TROO

+ 5V
BUS SBI MO L

BUS SBI M2 L

BUS SBI B23 L

BUS SBI INTLK

GND

BUS SBI Pl L
BUS SBI SPARE 0
BUS SBI SPARE 1

BUS SBI REQ6 L

BUS SBI

BUS SBI TRO2

BUS SBI TRO4

GND

BUS SBI PCLK H
BUS SBI PCLK L
BUS SBI PDCLK H
-5V
BUS SBI PDCLK

GND

BUS SBI TROS
BUS SBP TPO6
BUS SBI TRO7

BUS SBI B24 L

BUS SBI TAGO L

BUS SBI MPl

BUS SBI B25 L
GND
BUS SBI B26 L
BUS SBI B27 L

BUS SBI TAGl L
GND
BUS SBI TAG2 L
BUS SBI IDO L

BUS SBI MP2 L
GND
BUS SBI UNJAM L
BUS SBI ALERT L

BUS SBI TRO8
BUS SBI TRO9
GND
BUS SBI TR10
BUS SBI TR11

BUS SBI B28
GND
BUS SBI B29
BUS SBI B30
BUS SBI B31
+ 5V

BUS SBI ID2 L
BUS SBI ID3 L

BUS SBI ID1 L
GND

BUS SBI CNFO L
GND
BUS SBI CNF1 L
BUS SBI FAULT L

BUS SBI TR12
GND
BUS SBI TR13
BUS SBI TR14
BUS SBI TR1S
+ 5V

S2
T1

T2
ul
u2

+12

BUS SBI BO08
GND
BUS SBI BO09
BUS SBI B1lO
BUS SBI Bll
+ 5V

BUS SBI Bl6
GND
BUS SBI Bl7
BUS SBI B18
BUS SBI B19
+ 5V

L
L
L

BUS

SBI

FAIL

L
L

BUS

SBI

ID4 L

+ 5V

SNId AINVIdI0VE ‘STYNDIS 18S

A2
Bl

(o4

A
Al

CHAPTER 7

SBI NEXUS

4K CHIP ARRAY SIZE

{64KB BOUNDARY)

CONSOLE ADDRESS
20002000

DESCRIPTION

(64K BYTE BOUNDARY)

—— e

3130 292827 2625242322 21201918 17 1615
14 13 12
1110 0908 0706 05 0403 0201 00

ofo

BUS PARITY ERROR —

WRITE DATA SEQUENCE FAULT
TRANSMIT FAULT

MEMORY ARRAY SIZE

FAULT CONDITIONS
0|0j0|0|0|0|0jO(O

é.

{SETTO A 1" IF MEMORY

MEMORY

FOR 4K

TYPE

CHiP

{000= NON-INTERLEAVED

001 = TWO-WAY INTERLEAVED)

(1" INDICATES POWER UP:

MULTIPLE TRANSMITTERS
ON BUS

INTERLOCK SEQUENCE FAULT ———

INTERLEAVE STATUS (WRITABLE}

POWER UP ALERT

WAS A TRANSMITTER DURING A FAULT)

L6l

olojo

NOT USED

10
0

SET TO “0”; FOR AN 581 DATA

| MEMORY ARRAY SIZE

11|

[}

(WHEN WRITING TO INTERLEAVE

BITS <00:02>, THIS BIT MUST 8E

{*1” INDICATES POWER DOWN ALERT;
WRITE "1 TO CLEAR THIS BIT)

4K CHIP

WRITE “1° TO CLEAR THIS 8IT)

POWER DOWN ALERT

TABLE A
0

[

INTERLEAVE ENABLE.

TRANSFER, 1T IS SET TO 1)

TABLE B

16K CHIP

14]

13[

12|

11 [ 10]

64K BYTE

[- [ =

[256KBYTE

128K BYTE

[ ==

]612KkBYTE

182K BYT

256K BYT|

320K

BYT,

o]0

[0 [ 1

08 [ MEMORY ARRAY SIZE

|768KBYTE

[ ==

{1280KBYTE

|~ | 1024KBYTE

384K

BYT|

448K

BYT|

(1]

[

512K BYTE

[—

|~ | 204BKBYTE

|1536KBYTE

576K BYTE

{00

|— | —

[2304KBYTE

[1792KBYTE

640K BYTE

1[0

[ =]~

]2560KBYTE

704K BYTE

0|1

| <=

|2816KBYTE

768K BYTE

[ =

832K BYTE

1100

896K BYTE

[ 1[0 [

B60K BYTE

[

1024K BYTE

117

[ 1

[

[3072KBYTE

|3328KBYTE

]~ [ - | 3584KBYTE
==

[3B40KBYTE

[~- | 4086K BYTE

A SINGLE CONTROLLERWITH TR LEVEL =1

A THESE BITS ARE USED ONLY BY MEMORY

CONTROLLERS NOT HAVING A ROM BOOTSTRAP

[;}X MEMORY TYPE
0 | 0 | ERROR CONDITION;
NO ARRAY

BOARDS PLUGGED INTO BACKPLANE
0 | 1|

4K MOS

| 0 |

| 1

16K MOS

ERROR CONDITION; BOTH 4K AND 16K

BOARDS PLUGGED INTO BACKPLANE

TRorTIC

V H31S1934 NOILVHNOIANOD AHOWIW

SEE TABLE AFOR

CONSOLE ADDRESS

20002004

2322212019181716 1514 1312 1110
262524 92827
31302

(LU

weasrens

0908 07 0605 0403020100

TT T LT
LT
[SE————————

—_—

FILE
WRITE

WRITABLE ECCBITS
FOR DIAGNOSTICS

COUNTER

861

FILE

READ
COUNTER
ENABLE WRITE TO
STARTING ADDRESS

READS ALWAYS0

BITS<27:16>

ECC BYPASS BIT

WHEN WRITING INTO BITS <27:15>

WRITE 1" TO BYPASS ECC
WRITE “0” TO CLEAR THISBIT

THE MEMORY

WRITE "1 TO FORCE ERROR
WRITE “0” TO CLEAR THIS BIT

A "1 DURING
BIT 14 SHOULD BE
sBI DATA TRANSFER INTO

FORCE ERROR AT A PREDEFINED ADDRESS
REFRESH BIT

MEMORY

INITIALIZING
& BATTERY
BACKUP STATUS
INIT. STATUS

COLD START
INZ IN PROGRESS
INZ COMPLETE
VALID DATA
N MEMORY

ILLEGAL STATE

A STARTING ADDRESS IS ON 64K BYTE
BOUNDARIES

*MUST BE O FOR MS780C
TK-Q7178

g 431S1934 NOILVHNOIINOD AHOW3IW

WRITABLE STARTING ADDRESS
FOR THE MEMORY CONTROLLER
—

20002008

313029282726 252423222120191817161514 13121110 0908‘0706050403020100

INHIBIT CRD (CORRECTED READ

INERIRENENRREEND

4K CHIP ADDRESS IN ERROR

WRITE “1” TO INH CRD TAGS

DON'T
CARE
FOR 4k| MEMORY ADDRESS IN ERROR)

WRITE “0” TO CLEAR THIS BIT

CHIP

(SEE NOTE 5 FOR 16K CHIP

DATA) PASS

HIGH ERROR RATE IN
MEMORY FLAG

“1” HIGH ERROR RATE
INDICATION

ERROR SYNDROME

POINTSTO
BIT INERROR

ARRAY BANK IN ERROR

WORD IN ERROR

LOWER BANK
“1"" UPPER BANK

“0"

LOWER WORD

“1"" UPPER WORD

WRITE “1"” TO CLEAR THE
FLAG

661

ERROR LOG SERVICE
REQUEST FLAG
1" SERVICE REQUEST

ARRAY BOARD

WRITE “1 TO CLEAR

27|

IN ERROR

2625

010
|0
|0
0
/0
[0
[1
0
10
{1
|0
|1
0101
0|1
]0
|0
011
]0
1
0!1
(1
[0
011
]1
[1
1
|0
[0
[0
i
{0
[0
|1
7
[0
|1
|0
110
[1
|1
111
[0
|0
1
|1
10
|1
111
110
111
|1
|1

A EVEN # SYNDROME BITS = DBE
ODD # SYNDROME BITS = SBE

THE ERROR SYNDROME BITS ARE INVALID
UNLESS THE ERROR LOG SERVICE REQUEST BIT

(BIT 28, REGO) ISSET TO A “1".

& REGISTER C, BITS <22:09> ARE

16K CHIP ADDRESS IN ERROR.
BIT <23> 1S THE ARRAY BANK
IN ERROR (0 IS LOWER BANK & 1

1S THE UPPER BANK)
THE MEANING FOR ALL OTHER

BITS IN REGISTER C IS SAME FOR
4K & 16K CHIPS.

NOTE: WHEN INSTALLING AN MS780A & MS780C

ON THE SAME 11/780, THE MS780C SHOULD
HAVE THE LOWEST TR.
TK-0777A

O H31S1934 NOILVHNOIANOD AHOWIW

MEMORY ADDRESS IN ERROR

CONSOLE ADDRESS

MEMORY ARRAY ADDRESSES

M8211

Array

Address Range

Size

1
2

64 K
128 K

256 K

192 K

@- FFFF
10A@0-1FFFF
20000-2FFFF

M8210

Address Range

Size

256 K
512 K

768

30000-3FFFF

1924 K

384 K

S5@@AA-SFFFF

1536 K

512 K

70408@8-7FFFF

2048 K

640 K

90AAA-9FFFF

2560 K

2304

768 K

AGOAD-AFFFF

2816

CA@B0-CFFFF
DO@R@-DFFFF

3328 K
3584 K

320 K
448

576

704

13
14

832 K
896 K

960

1924 K

4000@-4FFFF

60020-6FFFF
80000-8FFFF

B@O#@@-BFFFF

EA@Q@-EFFFF

F@@@@-FFFFF

Memory Starting

200000

MEG

800000

MEG

Ceoooe

1792 K

3072 K

3840

40996 K

Address Jumpers

Boundary|Address

128¢ K

400000

200

@- 3FFFF
40000~ TFFFF
80600- BFFFF

Co@@@- FFFFF

190060806-13FFFF

140000-17FFFF
180000¢-1BFFFF

1C200@-1FFFFF
200000-23FFFF

240000-27FFFF
280000-2BFFFF

2Ce00Q-2FFFFF

300000-33FFFF
340000-37FFFF
380000~-3BFFFF

3C@000-3FFFFF

d
c

*
*

£
e

j
h

1
k

n
m

r
P

t
s

Y
u

X
w

z
y

bb
aa

SAl

*
*

*
IRD *

L0¢

SEL

TR#

Wlg

W1l

Wl2

Wire Wrap
F20

-—

-- 5

F20 C1

4
5
6

-—

I
I

I
-

I
I

F29 F2
F2¢ H2
F2¢ J1

I
-

rr
pp

tt
ss

wvv
uu

W10

W1l

W12

*
*

W10

W1l

W12

F20

-—

F20

F20 Pl

I
I
I
I

-—

-I
I
I

I
-I

I
-I
-—-

w8=1

MS788 Configuration
for REV A Backpanel

Configuration for
REV -- Backpanel

TR 1

ROM

No response2

confirmation
for Read to ROM
Address Space

F2¢ D1
F20 E1

12
13
14
15

nn
mm

*
*

TR8

Inhibit

11
kk

Decode

Signal | SEL

3jj
hh

Arbitration

Name

ff
ee

Level

2
3

dd
cc

W8=—-

Read to ROM

Address Space
receive Normal
confirmation

F29 N1

Starting Address

F2¢0 P2

F2¢
F29
F2¢
F2¢

S2
T2
Ul
U2

| w6 | W7

4 Mega Byte
8 Mega Byte
12 Mega Byte

W1-W5

; - Standard for Memory 1
-

Standard

for

Memory

Spare

-—I
I

11
I

NOTES:

1.
When installing an MS788A
and MS78@C on the same VAX-11/780

system,

the MS780C should be the

first memory (i.e., have the

lowest TR).
2.
The memory with the ROM bootstrap must be at TRIl.

TINVAINIVE H A3H HO4 NOILVHNDIINOD 08LSK

b
a

MS780A MODULE UTILIZATION

M8214

MSB

M8213

MCN

M8212

MDT

M8211

MAY

MB211

MAY

M8211

MAY

M8211

MAY

MB8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M8211

MAY

M9A4¢

TRM

When

not

installed,

use

blank

module

202

78141@63.

MS780C MODULE UTILIZATION

M8214

MSB

M8213

MCN

M8212 MDT

M821¢

M8218

MAY

M821¢9

MAY

M8218 MAY

M8219

MAY

M8219 MAY

M8219

MAY

M8218 MAY

M8210

MAY

M8210 MAY

M821@

MAY

M8210 MAY

M8210

MAY

M8210 MAY

M8214

MAY

M8210

MAY

M9049

TRM

* When

not

MAY

installed,

use

blank

module

203

7014143.

MSBA, PU

BUS SBII

SBI TRANCEIVERS

R
z5|

MSBU REC PAR (1:0)

oliwls5
O =

MSBF

MSBU REC

RESPONSE
LOGIC

TAG (2:0)

TAG
DECODE

msep
MSBU REC BIT (31:28)

MSBE

PARITY
CHECK

MSBA PAR (10:00)
MSBU REC ID (4:0)

MSBE F

MSBU REC ID (4:0)

FUNCTION

MSBU L WR, EXT

MSBJ

2|
|

GEN

MSBU L REC ID {4:0

wsps

PARITY

MSBS

DECODE

o
o«

Msan

cneck

@
2

crom

MCNT
BUS FL

MSBU XMT 1D (4:0)

MSK (1:0}

LATCH

MSBA REC BIT (31:00), REC MSK (3:0)
MSBD

SB!

¥0c

FROM

MSBA BT REC (27:10)|

OST

DECODE

COMMAND

MSBD DST ROM,

FILE

CNFG REG, ARY

MSBU L REC BIT (31:00)

CNFG

REG B

MSBBE

MSBA REC BIT (27:00)

oRiveRs | MCNP ST AOR (20:14)

MSBF P
"

BUS AC/DC LO

POWER/FSIL

CONTROL

MSBR

MSBU L REC MSK (3:0)

MSBU L DST ROM, CNFG-REG, ARY
MSB REC BIT (31:16)

MSBU L WR, EXT

ADDRESS | MSBD MUX REC BIT (15:00)
DECODE

MSBM

BUS FL INF

(31:00), MSK (3:0)

TYCLE

cle

stromes & 2|

WTM

CoNTROL

pEcope | CONTROL
CONTROL

DRIVERS

[=)

[ MEWORY

Cosie

MSBE
H

FILE

aly

CONTROL

LOGIC

§ x

MSBD
BUS SBI

PCLK, TP

CLOCK

LOGIC

BUS SBI TR (15:00)
BUS TR

TR SEL 8421

MoB

INTLV
ADR
COR

MCN ARY SZ {5:0)

CHIP

pod

MEM
&7

COR

ENCODE

MAY

.0)
( (15:00
) FROM
ROM
v
ARRAY

ARBITRATION

| LOGIC

TR0V 9

L 1HVd ‘WYHOVIA XD018 AHOWINW

VAN

é'o"flTNgofi‘

MDTD,P

LOGIC

CONTROL

BUS FL MSK (1:0)

[

BUS FL INF (31:00)

TAG

MDTD XMT TAG (1:0) | 1ag

XMT

MCNF.C
REFRESH

MCNF
REF ADR
c! A

Lo6IC

(15:01)

(7:1)

GEN

MCNE
MCNE ARY ADR (15:01)

‘

BUS FL INF

MCONM__

(19:00) | ADDRESS

REG

MCNE MEM ADR (15:00)

MCNL

MCNM,N

MCNE ARY ADR (19:15)

BOOTSTRAP|MCNL ROM DAT (31:00

MCNEP.H

]
a

(9:0)

ROM

BUS FL INF

CNFG

REG A

mMDT

AB.C

(174

2
z

ARRAY

DATA

BUS FL INF

CNFG

REG

|MUX

Mot

LATCH

| e I

eus eLine

CNFG REG €
MDTE

BUS FL MSK (3:0)

MDT C.T

BUS MOS DAT (c7:c0)| CHK BITS l MOS DAT (C7:CO)

“I

MEMORY

MCNK P

ece

LOGIC

BUS MOS L31:L00)|
DAT
] |(u31:uoo,
BUS MOS DAT
U31:U00,
DATA
L.3:1.00)
LATCH

BYT MSK

.
(U3:U0,

L3:L0)

MASK
DECODE

BUS MOS DAT
DATA
1 (y31:U00,L31:L00)
XMT
LATCH

MDTE
MDTE

CHK
BITS | gy MOS DAT (C7:CO)
DRIVERS

MOS DATA BUS

MDT MOS DAT (U31:U00Q)

BUS FL INF

(31:00

BUS FL

(31:00

INF

MDT MOS DAT (L31:L00)
BUS MOS DAT

MDTH-R

(U31:U00)

BUS MOS DAT (L31:L00)
TK-0180

Z 14Vvd ‘WvHOVIA X2019 AHOWIW

MCNC,D.K

STROBE

FROM CYCLE comnosL& TIMING

DECODE AND——
"~
of&CONTROL
| “ONTROL |

MEMORY 1/0 DATA LOGIC

BUS FL INF {31 .00)

MCNB MUX EN 1 L

MCNB MUX EN 2 L

MCNB MUX EN 3 L

&
IS

2
x
£

BUS FL INF
1

CNFG | cNEG REG A
REG
A

MCNB MUX SEL 2 L

CNFG |CcNFG REG B

v
|——o}

MCNB MUX SEL 1 L

REG
8

1/0 DATA MUX
STB

CNFG
REG
STATUS
SIGNALS

FROM

ADDRESS
REGISTER

CNFG REG C

SO | OUTPUT

REG A

L
L

L
Ho|

H
L

| REGB
REG C

L
H

H
«

| v | romBooT
x|

MCNE MEM ADR (9:0) _| BOOTSTRAP|MCNL ROM DAT (31:00)
Rom

ENB

MCNA ROM EN l.j

TK-08638

206

UBA ADDRESS SPACE AND C/A FORMAT

SBI C/A Format for UBA Register Access

MASK

FUNC

<3.0>

<3:.0>

1]0{0{010}0{0]0f0]0}0|0|0F

Nymger

(sBIADDRESS)

|O]

Tx-032¢

Base

J.us.flddm

TR
Num
Base 10

Address
(Physical
hex)

SBI
Address
(hex)

Num
Base 10

1
2

20002000
20004000

8000800
8001000

4
5
6
7

20008000
2000A 000
2000C000
2000E000

8002000
8002800
8003000
8003800

12
13
14
15

20006000

8001800

Base

Address
{Physical
hex)
20010000

8004000

20012000
20014000

8004800
8005000

20018000
2001A000
2001C000
2001 E000

8006000
8006800
8007000
8007800

20016000

SBI
Address
(hex)

8005800

Byte

UBA

Reg

SBI

hex)

(hex)

002
003
004

.
.
078
DPR 14
07C
DPR 15
Reserved | 080

01E
O0lF
020

007

Reserved | 7EC

SBI

hex)

(hex)

(Physical

CNFGR | 000

Address

000

UBACR | 004

001

FUBAR | 014
018
FMER

005
006

UBASR | 008
00C
DCR
010
FMER
FUBAR | 0iC

BRSVR 0 | 020
BRSVR 1 | 024

008
009

BRRVR 4| 030

00C

BRSVR 2 | 028
BRSVR 3 | 02C

BRRVR 5} 034

BRRVR 6| 038
BRRVR 7| 03C
040
DPR O
DPR |

044

Byte

Address

UBA

Reg

011

207

.
.

MR 0
MR |

800
804

200
201

MR 494

FB8

3EE

Reserved | FCO
.
.
Reserved | FFC

3FO
.
IFF

MR 495

00D

00E
00F
010

Address

.
.

00A
00B

(Physical

.
.

FBC

IFF

.
.

3EF

UBA REGISTERS

UBA STATUS REGISTER, BIT CONFIGURATION

27262524

109876543210

RERRRNNARNNENRNNRRNRNNRRNRNAR]
BRRVR 7 FULL
BRRVR 6 FULL
BRRVR 5 FULL

BRRVR 4 FULL
READ DATA TIMEQUT
READ DATA SUBSTITUTE

CORRECTED READ DATA
COMMAND TRANSMIT ERROR
COMMAND TRANSMIT TIMEQUT
DATA PATH PARITY ERROR

INVALID MAP REGISTER
MAP REGISTER PARITY FAIL

LOST ERROR BIT

UNIBUS SEL TIMEOUT
UNIBUS SSYN TIMEOUT

TK-0121

UBA DIAGNOSTIC CONTROL REGISTER, BIT CONFIGURATION

UNUSED

313029282726

UNUSED

24232221

1918

1615

Y
8 7

)

SAME AS CONFIGURATION REGISTER BITS <23:00>

MICROSEQUENCER OK

SPARE

DISABLE | DEFEAT
INTERRUPT | DATA
PATH

PARITY
DEFEAT

MAP

TK-0055

PARITY

208A

UBA REGISTERS

UBA CONFIGURATION REGISTER, BIT CONFIGURATION

313029282726

2322

181716

76543210

UNIBUS ADAPTOR CODE
UNIBUS INIT COMPLETE
UNIBUS POWER DOWN

UNIBUS INIT ASSERTED
ADAPTOR POWER UP

ADAPTOR POWER DOWN
TRANSMIT FAULT
MULTIPLE TRANSMITTER FAULT
INTERLOCK SEQUENCE FAULT

UNEXPECTED READ DATA FAULT
WRITE SEQUENCE FAULT
PARITY FAULT
TK-0119

UBA CONTROL REGISTER, BIT CONFIGURATION

313029282726

6543210

a|3]2l1]o

MAP REGISTER
DISABLE BITS

INTERRUPT FIELD SWITCH
BR INTERRUPT ENABLE
UNIBUS TO SBI ERROR INTERRUPT ENABLE

SBI TO UNIBUS ERROR INTERRUPT ENABLE
CONFIGURATION INTERRUPT ENABLE
UNIBUS POWER FAIL
ADAPTOR INIT

TK-0120

208

UBA REGISTERS (CONT)

UBA FAILED MAP ENTRY REGISTER, BIT CONFIGURATION

9 8

UNUSED
-

MAP REGISTER NUMBER
TK-0056

UBA FAILED UNIBUS ADDRESS REGISTER, BIT

CONFIGURATION

16 15

UNUSED
—

—~

FAILED UNIBUS TO SBI ADDRESS
UNIBUS ADDRESS BITS <17:02>
TK-0057

UBA BUFFER SELECTION VERIFICATION REGISTER, BIT CONFIGURATION

16 15

UNUSED

—Y"

TEST DATA
TK-0054

NOTE:
THE INFORMATION FOUND IN THESE REGISTERS
IS MEANINGFUL ONLY IF A CORRESPONDING
ERROR BIT IS FOUND IN THE UBA STATUS
REGISTER.

209

UBA REGISTERS (CONT)
UBA BR RECEIVE VECTOR REGISTER, BIT CONFIGURATION
130 29 2827 262524 2322 212019 18 17 16 1514 1312 1110 09 08 07 06 0504 03 02 01 00

IsllHHHHHHIl\HHHHHIlIHld
ADAPTOR INTERRUPT REQUEST INDICATOR

UNIBUS DEVICE INTERRUPT VECTOR

TK-0092

UBA DATA PATH REGISTER, BIT CONFIGURATION
0

16 15

2423

31302928

UNUSED
[

BUFFER STATE BITS BUFFERED UNIBUS ADDRESS (2-17)

BUFFER|

DATA

EMPTY

FUNCTION

BUFFER
TRANSFER

ERROR

TK-0053

UBA MAP REGISTER, BIT CONFIGURATION
0

212019

27262524

3130

UNUSED

~—
SBI PAGE ADDRESS

k__Y_)
RESERVED

AND

ZERO

MAP

BYTE

OFFSET

VALID BIT

BIT

LONGWORD

ACCESS

ENABLE

DATA

PATH

DESIGNATOR
ADDRESS

BIT 27

I/0 DESIGNATOR

TK-0052

210

DW780

c¢c

for

W1p

Wll

W12

W13

W14

W15

Backpanel

Configuration

REV

W1P

W1l

W12

W13

W14

Arbitration

UNIBUS

Level

Lie

Space

UsIcC

uUsic

USIC

Usic

SEL

Signal

Adapter

Name

TR#

-—

—

FRlCl

17}

FA1D1

—-—

F@1F2

-——

UsSID

Adapter#|

—_—

USID

wé

F@1EL

-—

FO1H2

FplJ1

-—

FO1M1

Selection

-—

FO1IN1

Signal

FglpPl

Fp1J2

Interrupt

Level

Name

-—
-

I
I

FalP2
F@l1s2

UAIF
SBI

FglT2

PRI

FglUl

PRI

JMP

Fa1u2

DW78¢@

]

first

for

~NOY

ISR#

Normal

for

Backpanel

Address

Wire Wrap
D@1R2 to

Select

Signal

<L —3

Configuration

REV

UAIF
SBI
adl

ook

m?ig”il

PYe

NOILVHNODIANOD HIJWNI TINVINIVE (V8N) 08ZMa

SBI TO UNIBUS CONTROL ADDRESS TRANSLATION

SBI COMMAND ADDRESS FORMAT

031

2827262524232221201918171615

r<3:0> ‘ <310>\1l010 olololololo‘1lblal
MASK | FUNC

UBA UNIBUS

ADDRESS DECODE .
UBA NUMBER

UBAO

upa1l
UNIB

—

CONTROL
A ND

UBA 2

___ O
0
——
1

—

UBA 3 —1

ADDRESS

- Ol

S ——

—_ O

—

LONG WORD

BYTE ADDRESS
ENCODER

UNIBUS

ADDRESS

UNIBUS ADDRESS BITS <17:02>
UA <17: 00>

C \ <1:0>
7

210

{

CONTROL

|
X

212

UNIBUS TO SBI ADDRESS TRANSLATION

l ct I co |
\

UNIBUS
CONTROL ADDRESS

MAP REG NUMBER

~—

98
N

BYTE WITHIN PAGE
—

—_—

MAP
REG
NUMBER

UNIBUS TO SBI

MAP

—
——SBI PAGE ADDRESS

|[#—

(PAGE FRAME NUMBER)
(21 BITS)

.
494

ADDRESS
TRANSLATION

2
3
5
6
L]

[

FUNC

MASK

495

SBI COMMAND ADDRESS

ENCODE

goi3ty

lMASKl FUNC I

SBI PAGE ADDRESS (PFN}

LONG WORD ADD ]
TK-01561

213

ADDRESSES AND VECTORS FOR UNIBUS DEVICES

UNIBUS

VAX-11/78¢

Physical
(Hex)

2013FE78

UBA No.

Device

Address
{Octal)

]

CR11

777160

Vector
(Octal)

230

DR11B/DR11W

772419

2013F508

124

DMC11/DMR11

Float

-—

Float

DZ11

Float

-—

Float

LP11

777514

2013FF4C

200

LP11

764004

2013E804

178

LP11

764014

2013E86C

174

LP11 3
LPAll

764024
770460

2p13E814
2013F130

270
Float

RL211

774400

2013F9¢@

168

KMC11

RK711
NOTE:

Address

Floating

777440
addresses

2013FF2¢0

and

vectors

convention.

214

are

219

according

PDP-11

FLOATING VECTORS AND FLOATING ADDRESSES

(Start

Floating Vectors
366 and Proceed

Upwards)

Device

Vector Size

DC11

DL11-A,-B

19*

DP11

DM11-AA

10%

DN11
DM11-BB

4
4

DR11-A

DR11-C
PA611 Reader

10
4

Punch

PA611
LPD11

DT11

1g*

DX11

10%*

pLilc,p,E

19%

DJ11
DH11
GT40
LPS11
DQ11

10%*
19**
10

DUP11
DVll-Data
DV11-Modem Control

19%*
10*

30%*
19**

KW1ll-W
DUll

109*
10%*

LK11-A
DWUN

DMC-11
DZ11
DWR70
LPP11

VMV21
VMV31

VTV@1l
KMC11

RL11/RLV11**%*
RX@2
TS11
LPAll-K

IP11/1P300
DMP11-AD

The

vector

(14)

octal

The

device

vector
* %

bit

module.

for

the

device

boundary.

can

have

second

However,

(No

2.)

either

this

M7838

should

later

device.

boundary.

***

Only

for

type

switch

215

always

must

jumper
M7821

always

interrupt

connection

(l18)

for

control

octal

FLOATING VECTORS AND FLOATING ADDRESSES (CONT)

Floating

(Default

Address

Addresses

Nothing

Precedes

it)

VAX-11/780*

Rank

(Hex)

DJ1l1

760010

2013E008

DH11

762020

2013EQ1@

DQ11

760030

2013E@18

DUl1l

760040

2013E02¢

DUP11

760050

2013EQ28

LK11-A

760060

2013EB30

760870

2013E038
2013EQ44¢

DMC11/DMR11

DZ11

760100

DWR78

760118

10
11

LPP11

760120

2013E0@48
2013EQ58

VMV21

VMV31

760130
768140

2013E@58
2013EQ640

KMC11

760150

2013E@68

760170

2@13EQ78

RL11/RLV]1]1**

DMP11

This

address

Only

for

applies

second

NOTE:

Floating

8-byte

(18

floating

registers
be

left

the

760160

UBA

Address

2013E07¢

TR3.

device.
space

gap must
be
that
is not

after

the

later

octal)

gap

must

Physical

(Octal)

present.

Address

Device

begins

left
for
present.

registers

alignment

address

for

each

device

requirements

must

216

760010.

every
device
In addition,

One

type
with
an 8-byte

type that
preserved.

UNIBUS CONFIGURATION

AQ00-17 (ADDRESS)

DO00-15 (DATA)

C0-C1 (CONTROL)
MSYN (MASTER SYNC)

SSYN {SLAVE SYNC)

PA-PB (PARITY)
DEVICE

BR4-7 (BUS REQUEST)

UBT

BG4-7 (BUS GRANT)

NPR (NONPROCESSOR REQUEST)
NPG (NONPROCESSOR GRANT)

SACK (SELECTION ACKNOWLEDGE)
INTR (INTERRUPT)

BBSY (BUS BUSY)
INIT (INITIALIZE)
ACLO (ACLINE LOW)

DC LO (DC LINE LOW)

TK-0085

217

UMD M8272

BUS REQ MSK

UAl M8273
UNIBUS
D <15:00>

REG

RCVR

XCV

S$B1 B <31:00>

58I MASK <3:0>

RECV D <15:00>

SBI TAG <2.0>

$BI 1D <4-0>

BUS IB <31:00>

REC B <31:00>

SBI TR <15:00>
SBI REQ <3.0>

UniBUS }g

SBI UNJAM

WRITE

SBI DEAD

|
|DOUT

Junisus

DATA

SBIINTERLOCK

AR
A rev [ vaiRECV
1B

MsK

ACV MASK

BUS BRIN <7 4> (BUS OUT)
BUS BROUT <7 4> (BUS
IN]

Nunisus

CONTROL
Joaasline

JconTrolk UN1BUSA <17 00> 7}

ENCODER|

JanDRESS| UNIBUSC <10>
xCvRS

CONT

sTATUS |

lanD

REG

STORE

STORE
SBI

INTER-

FUBAR

FACE

SBI DEAD.

NIBUS TO SBI
[ADDRESS MAP

UNJAM
sB!

]

NIBUS

DP RAM

FUNC

BUS IN

81c

SHIFTERS

DP ADD <5:2>

UBATO

Pt MSYN

UNIBUS

[e——— SSYN

AND

BDP NO.

BOP

STORED

MASK

BOP

AND

———
BUS INTR OUT {BUS

fa—————— BUS NPR IN (BUS OUT)

j#-——————8US SACK
IN {BUS OUT)

INTERAUPT

p————aBUS BG QUT (BUS OUT)

FUNC

CONTROL
ucB mM8271

U B ATT SEL
MICRO

SBI DEAD, UNJAM

LOGIC

OMA

DMAATT SEL ] operaTION
DECODE
1
POWER SUPPY ACLO. DCLO:

|
I

BUS NPR OUT (BUS IN)

UBA POWER FAIL
LOGIC

INSERTED

BUS NPR

INTO

BUS SACK

———e

IMgou

SB SEL

BUS BGIN <7:4> (BUS IN)

BUS SACK OUT (BUS IN)
BUS NPG IN (BUS IN)

fosT
FUNC <3:0>

IN}

UNIBUS
CONTROL

ENCODE

fe————BUS INTA IN (BUS OUT!

MASTER

CONTROL

STATE

MASK

8uUS OUT

————BUS NPG QUT {(BUS OUT)

EL])
LOGIC

UNIBUS

ARBITRATION [ BBSY

TN <3:0>

TRANSMIT

UNIBUS

—

[*RUsNPG

‘

l&———BUS DCLO

OF
UBA L

l—

eBUSINIT

BUS 8G <7 4>
{GROUND)

UNIBUS ACLO

UNIBUS DCLO

UNIBUS BUS INIT

WVH9OYVYIA %3019 (san) 08.Mma

USt M8270
REQ <7:4>

INTERFACE

WRITE

US| REGISTER STROBES

———CcnNFGR. DCR.
SR, CR

UAI REGISTER STROBES
USTRIP

- READ CNFGR, DCR

RECEIVE
LOGIC

SBATTENTION

LOGIC (UCB)

IFREAD CR, SR, BRSVR,

DPR, MR, FMER, FUBAR

FREAD UNIBUS
TRANSMIT

CONFIRMATION
LOGIC

FAULT

TOCAL

{READ IN PROGRESS)

-WRITE BRSVR,DPR,MR

l-WRITE UNIBUS

MAP REGISTER STATE

{UNIBUS

MASTER LOGIC

BRRVRIP

FREAD BRRVR

UNIBUS

(st

LOGIC

AOM A
UNIBUS DEVICE

vip

IN PROGRESS)

OMATRANSFER

READ

BDP STATE

UNIBUS DATI

(UAI)

{UMD)
UNIBUS DATO

INTERRufil
LOGIC

(UAI)

UB ATTENTION

]

DMA ATTENTION

LOGIC

(VA1)

{uce)

<UNIBUS

INTERRUPT SUMMARY
FINTERRUPT SUMMARY

READ LOGIC

READ

{USH)
READ DATA

FRECEIVE READ DATA—

FUNCTION
DECODE

174

{usn

PREFETCH

PREFETCH READ DATA

{PFRD RCVD)
DIRECT READ DATA

(DRD RCVD)

ATTENTION

(PFRD RCVD}
MICROSEQUENCER

MICROSEQUENCER

INSTRUCTION
v

DECODER LOGIC

(ucs)

MICROSEQUENCER

RECEIVE

{ucs)

CONFIRMATION
LOGIC

s8B!

TRANSMIT

{uce)

HUDLH

LOGIC

ARBITRATION
LOGIC

OP
A

BUS AD

CONTROL

BUS 18

CONTROL

MAP AND DATA
PATH SELECTS

TK-0308

'NIHLIM SNOILONNS TOHLNOD HOr'vIN 40 MOTd4 A3141TdWIS

UNIBUS

INTERFACE

SBI

ven 3HL

SBt

Standard

Modified

Signal

Standard

Modified

Signal

Standard

Modified

Signal

AAI

INIT L

APl

GROUND

PO*

BH1

AOl L

AA2

+S5V

+5V

AP2

BBSY L

BH2

AQO L

AOO L

ABI

INTR L

ARI

GROUND

BAT BACKUP +15V

BJI

AO3 L

AB2

GROUND

TEST POINT

AR2

SACK L

BJ2

AO2 L

AC1

DOO L

D00 L

AS1

GROUND

BAT BACKUP +15V

BK1

AOS L

A0S L

AC2

GROUND

AS?2

NPR L

BK?2

AO4 L

ADI

DO2 L

ATl

GROUND

BL1

AO7L

AQ7 L

AD2

DO1 L

DOI L

AT2

BR7 L

BL2

AO6 L

AE]

D04 L

AUl

NPG H

+20V

BMI

AQ9 L

A0S L

AE2

DO3 L

D03 L

AU2

BRoO L

BR6 L

BM?2

AOS L

AO8 L

AF1

DO6 L

DO6 I

AVl

BG7H

+20V

BN1

All L

AllL

AF2

DOS L

AV2

GROUND

+20V

BN2

AlIOL

AlOL

AHI

DO8 L

BAL

BGoe H

SPARE

BP1

Al3L

AH2

bo7 L

DO7 L

BA2

+5V

BP2

Al2 L

All

DIOL

BGS H

SPARE

BR1

AlSL

D09 L

BB2

GROUND

TEST POINT

BR2

Al4L

Al4 L

AKl1

DI2L

D12 L

BC1

BRS L

BS1

Al7L

AK2

DITL

DIIL

BC2

GROUND

BS2

Al6 L

ALl

D14 L

Di4 L

BDI

GROUND

BAT BACKUP +5V

BT1

GROUND

AL2

DI3L

AM1
AM2
AN1

PAL

DI3L
PAL

BD2
BE 1

BR4 L
GROUND

BR4 L
INT SSYN*

BT2
BUI

ClL
SSYN L

CiL
SSYN L

DISL
GROUND

DISL
Pl*

BE2
BF1

BG4 H
ACLO L

PAR: DET*
ACLO L

BU2
BV1

coL
MSYN L

CoL
MSYN L

AN2

PB L

PBL

*Pins used by parity control module.

BF2

DCLO L

DCLOL

BV2

GROUND

-5V

SLNINNDISSVY Nid SNGINN A3141GOW ANV AYVANVLS

0ce

UNIBUS SIGNAL DESCRIPTIONS

Signal Line

Description

Data Transfer Group
Address Lines
[SA (17:00)]

These lines are used by the master device to select the
slave (actually a unique memory or device register address). SA (17:01) specifies a unique i16-bit word; SA00
specifies a byte within the word.

Data Lines

[D (15:00)]

These lines transfer information between master and
slave.

Control (Ct, C0)

These signals are coded by the master device to control

the slave in one of the four possible data transfer operations specified below. Note that the transfer direction is
always designated with respect to the master device.
Data In (DATI): a data word or byte transferred into
the master from the slave.
Data In Pause (DATIP): similar to DATI except that it
is always followed by a DATOQ/B to the same location.

Data Out (DATO): a data word is transferred out of the
master to the slave.
Data Out Byte (DATOB): identical to DATO except a
byte is transferred instead of a full word.
Parity A-B (PA, PB)

These signals transfer Unibus parity information. PA is

currently unused and not asserted. PB, when true, indicates a device parity error.
Master
Synchronization
(MSYN)

MSYN is asserted by the master to indicate to the slave
that valid address and control information (and data on
a DATO or DATOB) is present on the bus.

Slave
Synchronization

SSYN is asserted by the slave. On a DATO it indicates
that the slave has latched the write data. On a DATI/P
it indicates that the slave has asserted read data on the
Unibus.

(SSYN)

Interrupt (INTR)

This signal is asserted by an interrupting device, after it
becomes bus master, to inform the UBA that an interrupt is to be performed, and that the interrupt vector is
present on the D lines. INTR is negated upon receipt of
the assertion of SSYN by the UBA at the end of the
transaction. INTR may be asserted only by a device that
obtained bus mastership under the authority of a BG
signal.

Priority Arbitration
Group
Bus Request (BR7-BR4)

These signals are used by peripheral devices to request
control of the bus for an interrupt operation.

Bus Grant (BG7-BG4)

These signals form the CPU and UBA response to a bus
request. Only one of the four will be asserted at any
time.

221

UNIBUS SIGNAL DESCRIPTIONS (CONT)

Signal Line

Description

Priority Arbitration
Group (Cont)

Nonprocessor Request

This is a bus request from a device for a transfer not

(NPR)

requiring CPU intervention (i.e., DMA).

Nonprocessor Grant

This is the grant in response to an NPR.

(NPG)
Selection Acknowledge
(SACK)

Bus Busy (BBSY)

SACK is asserted by a bus-requesting device after having received a grant. Bus control passes to this device
when the current bus master completes its operation.
BBSY indicates that the data lines of the bus are in use.

It is asserted by the Unibus master.

Initialization Group
Initialize (INIT)

This signal is asserted by the terminator board (UBT)
when DC LO is asserted on the Unibus, and it stays
asserted for 10 ms following the negation of DC LO.

AC Line Low (AC LO)

This is an anticipatory signal that warns of an impending power failure. AC LO initiates the power fail trap
sequence and may also be issued in peripheral devices to
terminate operations in preparation for power loss.

DC Line Low (DC LO)

This signal is available from each system power supply
and remains clear as long as all dc voltages are within
the specified limits. If an out-of-voltage condition occurs, DC LO is asserted.

222

DW780 MODULE UTILIZATION CHART

TYPICAL

CONFiGURATION

B
L

U
A
|

U
M
D

U
C
B

U
S
i

0
D
U
L

0
D
u
L

8
2
7
3

8
2
7
2

8
2
7
1

8
2
7
0

TK-8357

223

MBA REGISTERS

MBA

Base

Function

Address

Number

Base

TR
Num

Base

Address

SBI

(Physical

Address

Hex)

(Hex)

20002000

8000800

20004000

8001000

20006000

8001800

20008000

8002000

2000A000

8002800

2000C000

80030600

2000EQQ0

8003800

20010000

8004000

20012000

8004800

20014000

8005000

20016000

8025800

20018000

8006000

2031A000

8006800

2001C000

8007000

2001EQQ0

8007800

MBA CONFIGURATION/STATUS REGISTER

e
-

SBI PARITY ERROR ——]

OVER TEMPERATURE

WRITE DATA

{NOT IMPLEMENTED)

SEQUENCE ERROR

ADAPTOR CODE

ADAPTOR POWER UP

UNEXPECTED READ

ADAPTOR POWER DOWN

DATA ERROR
MULTIPLE

TRANSMITTER

TRANSMITTER DURING FAULT

ERROR

TK-D692

MBA CONTROL REGISTER
381

{

103020100,

Loooo]oooo]oooolooooJooooloooolooool ] | ] I04
MAINTENANCE MODE

INTERRUPT ENABLE

ABORT
INITIALIZE

NOTE:

ALL BITS ARE READ/WRITE EXCEPT INITIALIZE
WHICH

ALWAYS READS AS 0
TK0692

224

MBA REGISTERS (CONT)

MBA STATUS REGISTER

313029

DATA TRANSFER
BUSY

123

(19181716415

1312,1110
0908,07 06 05 04,0302
100

RRNRE

(1 ofelofofolelefole] [ ] [ lefe[ [ [ 1]
PROGRAMMING
ERROR

NO RESPONSE
CONFIRMATION

NON EXISTENT
DRIVE

CORRECTED
READ DATA

MASSBUS CONTROL
WRITE ERROR
MASSBUS ATTENTION

DATA TRANSFER COMPLETE

DATA TRANSFER ABORT

DATA TRANSFER LATE
WRITE CHECK-UPPER ERROR

WRITE CHECK-LOWER ERROR
MISSED TRANSFER

MASSBUS EXCEPTION
MASSBUS DATA PARITY ERROR
MAP PARITY ERROR
INVALID MAP

ERROR CONFIRMATION
READ DATA SUBSTITUTE

INTERFACE SEQUENCE TIMEQUT
READ DATA TIMEOUT

NOTE: WRITE 1 TOCLEAR BITS IN
THIS REGISTER EXCEPT BITS 31
AND 16, WHICH ARE READ ONLY.

TK-0698

MBA VIRTUAL ADDRESS REGISTER
31

28,27

24,23

20,19

FOOOOOOOOOOOOOO

16,15

12,11

MAP POINTER

09,0807

04,03

)

PHYSICAL PAGE BYTE
ADDRESS
TK-0696

225

MBA REGISTERS (CONT)

MBA BYTE COUNT REGISTER

24,23

16,15

08, 07

MASSBUS BYTE COUNTER

SBI BYTE COUNTER

(READ ONLY)

(READ/WRITE)

NOTE: DATA WRITTEN INTO THE

2's COMPLEMENT OF THE NUMBER

SBI BYTE COUNTER ISCOPIED

OF BYTES TO BE TRANSFERRED

INTO THE MASSBUS BYTE

COUNTER,

o697

MBA DIAGNOSTIC REGISTER
31

24232221

16 15

12,

COUL T
INVERT MASSBUS

08,07

[

MASSBUS

DATA PARITY

DRIVE

INVERT MASSBUS

SELECT

{READ ONLY)

CONTROL PARITY
INVERT MAP PARITY

MASSBUS REGISTER SELECT

BLOCK SENDING —

(READ ONLY)

COMMAND TO SBI

SIMULATE SCLK

SELECTED MDIB (READ ONLY)

SIMULATE EBL

(VALID DURING MAINTENANCE

SIMULATE OCC

MODE ONLY)

SIMULATE ATTN
MDI 8 SELECT

MASSBUS FAIL (READ ONLY)
MASSBUS RUN (READ ONLY)

MASSBUS WCLK (READ ONLY)

NOTE: BITS 21 AND 22 ARE READ/WRITE

MASSBUS EXC (READ ONLY}

FOR DIAGNOSTIC TEST PURPOSES

ONLY

MASSBUS CTOD {READ ONLY)

TK-0694

226

MBA REGISTERS (CONT)

MBA MAP REGISTER

24,23

16415

08,07

[ Lelelelefelefe]ele]e
|

VALID BIT

_»
y

—V

PHYSICAL PAGE FRAME NUMBER
TKLO715

COMMAND/ADDRESS REGISTER (CAR)

2827

I FUNCT ]

ADDRESS

] 1c

*The CAR is read-only, and is only valid when DT BUSY is set.
This register contains the value of bits 31 through 00 of the SBI

during the command/address portion of the MBA's next data
transfer.
TK-8349

227

¢ttt

RH788

for

Wl@

W1l

Wl2

Configuration

for

W10

W1l

W12

8¢t

TR Arbitration
Level

Interrupt

MBA

Signal

Name

SEL

Signal
Name
Wire
Bus

TR#

Level

Selection

from

Wrap
SBI

TRXX

FO2F1

MBA

Intr
Code

INTR
Code

[

BR#

Fa2Cl

—-—

Fe2D1

FB2E1l

F@2F2

FO2H2

6
7

I
I

Fg2J1

9
18

1
1

Fg2pPl

11
12

I
I

Fpg2p2
Fp2s2

Fp2T2

Fp2ul

Fp2U2

Fp2J2

Fa2Mml
F@2N1

Normal

for

first

RH788

W12

SPARES

Configuration

REV A

REV

Backpanel

NOILVHNDIINOD HIdIWNF TINVAINOVE (VEW) 08/HYH

b
a

MASSBUS DISK DRIVE REGISTER ADDRESS CALCULATION CHART

1ST MBA BASE ADDRESS — 20010400 {TR8}

3RD MBA BASE ADDRESS — 20014400 (TR 10}

2ND MBA BASE ADDRESS — 20012400 (TR9)

4TH MBA BASE ADDRESS — 20016400 (TR11)

DRIVE

TYPE

DRIVE NUMBER

{DISK)

{TAPE)

RMCS1

100

180

200

HEX

OCTAL

CSt

300

380

RMDS

104

184

204

284

304

384

ER1

RMER1

108

188

208

288

308

388

5
280

RMMR1

28C

30C

RMAS

110

190

210

290

310

390

RMDA

114

194

214

294

314

394

RMDT

10C

18C

20C

38C

RMLA

11C

19C

21C

29C

31C

39C

RMSN

AQC

120

1A0

220

2A0

320

3A0

OFF

RMOF

124

1A4

224

2A4

324

3A4

DCA

RMOC

128

1A8

228

2A8

328

3A8

CCA

RMNR

12C

1AC

22C

2AC

32C

3AC

ER2

RMMR2

130

1BO

230

2B0

330

3BO

118

198

218

298

318

398

ER3

RMER2

134

184

2B4

334

ECCPOS | RMEC1H

138

188

238

288

338

3B8

ECCPAT | RMEC2

[]
[]

13C

1BC

23C

2ZBC

33C

[]

3BC

234

[

)

[]

(]

[

[]

[

[]

[

17C

1FC

27C

2FC

37C

3FC

[]

MBA BASE PHYSICAL ADDRESS TRANSLATION
16

HENEE
TR

DS
M

MAPREGSELECT

SET IF EXTERNAL REGISTER

DRIVESELECT
#

ZERO

BYTE

TK8347

229

MASSBUS SIGNAL CABLE PIN ASSIGNMENTS

Massbus Signal Cable Designations

Pin*

Cable
Massbus

Cable A

A
B

Designation

Cable

MASS D00

Cable B

F
H
)
K

6
7
8
9

Polarity

vV
v
X
Y
Z
AA

118
|19
J20
2
2
|23

+
+
+
+

|24

|25

j1?

DD } 26

+
-

}27

]28

130

}32

{34

HH | 29

KK | 31

MM | 33
PP

|35

RR | 36

|37

]38

Uy
vV

{39
|40

MASS D11

MASS C06

MASS C07

MASS D10

MASS DOS

+
-

MASS D08

MASS D04

{12

|11

MASS D07

6
7
8
9

F
H
J
K

MASS D06

MASS D02

+
+
-

MASS D03

Designation

MASS DOt

111

Massbus

Polarity

Pin*

|12

MASS C00

MASS €01

MASS C02

117

+
+
-

+
-

MASS D09

MASS C08

|18
vV
{19
W
J2
X
|2t
Y
122
Z
AA | 23

+
+
+
+

|24

MASS SCLK

|25

MASS EXC

MASS RS3

EE | 27

MASS RSO

MASS ATTN

HH | 29

|28

MASS RS4

130

|32

MM| 33

MASS CTOD

NN | 34

RR | 36

MASS C03
MASS C04
MASS C0S

DD | 26

{31

|35

MASS WCLK

MASS RUN

SPARE
GND

Uu | 39
vV | 40

{37

TT | 38

*Alternate pin designation schemes

Note: Massbus cables are to be installed per markings on the cable.

230

+
+

MASS C09
MASS C10
MASS C11

MASS EBL

MASS RS1

MASS RS2

MASS INIT

MASS SP1
SPARE
GND

MASSBUS SIGNAL CABLE PIN ASSIGNMENTS (CONT)

Massbus Signal Cable Designations

Massbus

Cable C

Polarity

Pin*

Cable
A

|12

Designation
MASS D12
MASS D13
MASS D14
MASS D15
MASS Di6
MASS D17

MASS DPA
MASS C12

U
\4

17
18

MASSC13

MASS C14

|21

AAl

BB | 24

DD { 26

EE | 27

FF | 28

HH | 29

130

KK | 31

LL | 32

MM]

NN | 34

|35

RR | 36

137

TT | 38

Uu | 39

vV | 40

MASS C1S

MASS CPA
MASS OCC
MASS DSO
MASS TRA

MASS DS1
MASS DS2

MASS DEM

MASS SP2
MASS FAIL
GND

*Alternate pin designation schemes

231

RH780 MODULE UTILIZATION CHART

TYPICAL
CONFIGURATION
6

E
TK-8356

232

M8275 SLOT|

MBA INTERNAL REGISTERS

INT BUS

M8276 SLOT 2

DRIVERS

(TRISTATE}

INTERNAL BUS (TRI-STATE)

W—-@

INT BUS

CONTROL

STORE

RECEIVERS

(R/W,ID)

MIR

MSI

DECODE

¢/a

CONTROL/

| FuncTion|

mw cmp

REGISTERS

CHECK
MS

STATUS
—

gglov;?m_

ADDRESS/

TAG

INTERNAL

DRIVE SEL

y—

INT/EXT)
MIR

MSi

ADDRESS

IREG SEL

€ec

XCEIVER/

ISR

LATCH

INTERNAL
VALID

wol

ISR
MSI

Fa oK

]
25

{RECISTER

OPERATION

MIR

sTRosE RS |

[—*

MIR

]

:l >

MAP

CHECK

MIR

1
I

CMD/ADRS

mst

CONFIRM

MUX SEL

(TLRC;\GN':MIT) CONF

- — — —{Busy
{RECEIVE}

VALID ISR

n/R

AND ENAB
[—RETRY

MDP

OUTPUT DATA MUX
(8:1 TRI-STATE)

MIR

mS!I

INT BUS

MuXx

RECEIVERS
INTERNAL BUS (TRI-STATE)

ISR DATA
TK-0T19

L LHVd ‘WVHOVYIA MD019 (08ZHYH) VAW

MBA/SBI INTERFACE

MASSBUS CONTROL PATHS

M8277 SLOT 3

M8278 SLOT 4

INTERNAL BUS (TRI-STATE)
|

INT BUS

RECEIVERS

MDP

MASSBUS
IN
DATA

MDP

g8
8[=}

®
O W

RECEIVERS

BUFFER

INT BUS

MDP

MUX

MCP

MASSBUS

CONTROL

CONTROL
PATH OQUT

MASSBUS

MCP

MDP
MASSBUS

DATA

MDP

WRITE

IMASSBUS

CHECK

XCEIVERS

COMPARE

MDP

<
MDP

l
MASSBUS

OuTPUT

MUX
4:1
o
@n

DATA
ouTt

{CONTROL

(DATA PATH

SILO

MDP

XCEIVERS

—

PATH)

MCP

]

MASSBUS
DRIVE/REG

——>

SNASSYW

vee

MUX

MASSBUS

CONTROL

SEL

PATH IN

(TRI-STATE)

{TRI STATE}

MCP

mce

p—

CONTROL
ENAB
MCP

BUFFER
MDP

LJ;

OUTPUT DATA MUX

MUX SEL

(2:1 TRI-STATE)

AND ENAB
MDP

@-—T

MIR

INTERNAL BUS (TRI-STATE)

A4
TK-0720

Z 14Vd ‘WvHOVIA %0019 (08LHY) VAW

MASSBUS DATA PATHS

123

[TTT1]
SBI

SBI

SBY

PWR[PWR

OWN|UP

SBI

o o

119

0O 0 ©

)

6|0 o0 O ol o t) o 0 0

INTLK MULT XMT

FLT SEQ

SEQ

XMT

FLT

0 0

0o o lPORTNO

MA780 NEXUS
1DENT (ALWAYS
1S 010000)

PORT

PTY WRT

SHA1SI934 AHOW3IN LHOJILTNW 08LVIN

PORT CONFIGURATION REGISTER 2000X000 MPI

DUR
FLT

—

SBI FAULT STATUS

PORT INTERFACE CONTROL REGISTER 2000X004 MPI

RAM|
IOV

TTMMO

I o} ‘ 0 ’ 0

MRK

—r

RAM210
COUNT
A

0 0o 0 4] 1] 0 0 0 0
L

GET

0 [1]

MRK
REQ

| 1

INPUT
BDI

INHB
RAM

PTY

MSTR
INTR

ARB

INV

PTY

FLTON
INPUT

LOST

ON
BDI

voT

MARK

QUTPUT

]

NOT
REC

PTY
INV

INTR
EN

ACK

INLK

8DI

ERR

(MPC)

PORT CONTROLLER STATUS REGISTER 2000X008 MPC

L1
|

ADM!

CcMD
ABORT
MULT
XMTR
FLT

XMT

DUR
FLT

DURING
FAULT

ADMI
GRNT
PAR ERR

EREEEOEEOEEEEEEDEREERDORR

—

ADMI

CACHED | EX

ADMI

831 H

H
|B20

WRTH
RD L
ADMI

B29 H

ARRH
1/OL
ADM|

B27 L

NOC/AON
ADMIWHEN
REQSTD

INTLK | SINGLE|

STEP

TTMMO

VDT
DATA
LOST

MPC

ARY
INIT
IN

INLK

PROG

ADMI

INHIBIT | SLF

ADMI

ARB
INLK
GRNT
ACPTD

INVAL | PTY

INVAL
DIS

FORCE
ADMI
MULT

XMTR

INV

TR.NO.|

ERR
INTRPT
EN

FLT

TK-3394

| 23

22721

1818 ' 17 ' 16

STARTING ADDRESS <26:16>

wfo[mw[m][

O | ARRAYSIZE | 4ot

(13|12

][]

(LNOJ) SH3LSID3H AHOW3IW LHOJILINW 08LVIN

PORT INVALIDATION CONTROL REGISTER 2000X00C MPC

D[IO]IIG]ID{ID]D]ID]ID

{10|o|8]|7]|6f{s5|alal2|[1]o

| S

CACHED
FORCED
CACHE

DEVICE

IDENT.

BIT

ARRAY ERROR REGISTER 2000X010 MAT

]

IVDT

INH

MAP

| 19

| 15

[ 11

ERROR ADDRESS
'} A
1
L

{ 07

| 03

ERROR SYNDRONE
i
1 il
1
L

ERR

CRD ERR

PTY

LOG

TAG RATE REQ

ERR

9ee

1 23

0 |e—
1
i

CONFIGURATION STATUS REGISTER 0 2000X014 MAT

oflo

ofo

0|0

| 19

0
i

, 1

PORT OFF LINE

POIRTPI()WEA

PORT ERROR

DOWN STATUS
1

I 1

(—

ARRAY

NON-CONTIG.

INIT

RROR

STATUS 4K

ARRAY

CHIP

ARRAY
ERR

CONFIGURATION STATUS REGISTER 1 2000X018 MPS

y 27
T

| 23
T

{19
T

15
T

;1
T

, 07

PRTPRT"RTPRTI
3

INVALIDATION

VDT

FORCE

MAP

MULT

PRES

PRT3 PRT2
1

—
ACK RECEIVED

, 03
T

00
T

PRT1

INLK
ACPTD

MULT

FORCE sLOW

INLK

INLK ARB

PORT TYPE/PRESENCE

TR.NO

PRTO_I
4

ACPTD
TK 3295

(LNOJ) SH3LSIDIH AHOWIW LHOJILTNWN 08LVYIN

MAINTENANCE CONTROL REGISTER 2000X01C MAT
127

1 23

119

, 03

SUBSTITUTE ECC BITS (07:00)
T

FORCE | ECC

NO.

ACC

SLOW

DIS

ADMI

TO PRT 1

[——)

MULTIPORT | ARRAY|

TOPRTO

BYPASS

ARB

VDT

FORCE

MAP

ADMI

ECC

PTY

GRNT

INV

PAR
ERR

INTERPORT INTERRUPT REQUEST REGISTER 2000X020 MPS
31

L 27
T

LET

, 23
T

L FROM PRT3

FROM PRT2
T

19
T

15
L)

FROMPRT 1 ]

, 07
T

TOPRT2
i

00
I

PRT PRT PRT PRT PRT PRT PRT PRT PRT PRT PRT PRT PRT PRT PRT PRT
2

TOPRT3
T

TO TO TO TO TO TO TO TO TO To TO TO TO TO TO TO
3

LN
T

FROM PRT0

prRT2 | pRTO

FROM

PRT3

PRT1

| PRT2

FROM

FROM

PRT1

PRT3

PRT1

PRT3

PRT1

INTERPORT INTERRUPT ENABLE REGISTER 2000X024 MPS
19
T

TOPRT 3

TOPRT
2

TOPRT 1

11
T

TOPRT
O

07
H

FOR PRT 3

FOR PRT 2

| PRT1

FROM
PRT 2

| PRT3 | PRT1

FROM

PRT O

PRT 2

| PRT3

FROM
PRTO

[ PRT1

FROM

PRT 2

| PRT3

FROM
PRT O

| PRT1

FROM

PRT 2

PRT3 | PRT1

FROM
PRT O

PRT 2

PRT3 | PRT1

F
PRTO

FOR PRT 1

| PRT2

2
4

PRT1

| PRT3

1
2

FROM l FROM ! FROM |

PRT1

TR NO

FOR PRT 0

FROM

PRT 2

PRTO

PRT 2

PRTO

PRT 2

PRT O

5
TK-3420

MA780 ARRAY ADDRESSES

Array

M8210

Address

256K

3FFFF

Range

512K

40000

7FFFF

768K

80000

BFFFF

1824K

Coooo

FFFFF

1280K

100000

13FFFF

1536K

140000

17FFFF

1792K

180000

1BFFFF

2048K

1Cooe0

1FFFFF

238

MA780C JUMPERS

W1@ W1l W12 W13 W14 W15 W16 W17 W18 W19 wW2@

*
*

SBI TR Level Jumpers

Optional port Interface Slots 1 and 2

Standard Port Interface Slots 3 and 4
Level

Wire Wrap

Jumper

Wire Wrap

Jumper

TR
W17

W18

W19

W29

F@3H1 to

F@2H1 to

FO3C1

F@2Cl

F@3E1

F@2E1 *

12
13
14
15

I
I
I
I

I
1

I
I
-

I
I
I
I
-

1
I
I
I

1
I
I
I
-

I
I
I

4
5
6
7
8
9
l¢
11

I
I
I

F@3D1 *

FO3F2
F@3H2
F@3J1
F§3J32
F@3M1
FA3N1
F@3P1
Fe3p2

I
1
I

I
I
I
1

Fp382
F@3T2
FA3Ul
F@3u2

1
I
b
1
I
I
I

1
I
I
I
I
I

F@2D1

FO2F2
FB2H2
F@2J1
FP2J2
F@2M1
FO2N1
F@2P1
F@2pP2

I
I
I
I
-

F@2s2
F@2T2
Fo2ul
Fo2u2

I
I
-

The memory that contains the ROM bootstrap must be at TR 1l.
0000

MA789 (s) must have the next highest SBI priority, that is, lowest TR number.

MS788 (s)
DW780(s)
RH786 (s)

have the next highest.
have the next highest.
have the next highest.

If a MS78@ contains the ROM bootstrap,
the system and are to be interleaved,
number

past

the

last

it must be at TR 1.
If MS78¢ memories are on
the second MS780 must be at the next even TR

TR.

Jumpers

Interrupt

Level

Interport

Interrupt

Level

MA780

Error

Level

4
6

Interrupt

5
7

I = Jumper inserted.
= No jumper.
* = Standard configuration.

239

Standard Port
Slots 3 and 4

Optional Port
Slots 1 and 2

w16

- *
I

MA780A JUMPERS

WI1Z

W1l

W12

W13

W14

W15

W16

W17

W18

W19

W2p

Memory Starting Address
(Used Only on Power-up)
Strap

Port

Jumpers

Port

Name

SA23

SA22

SA23

SA22

SA23

SA22

SA23

SA22

Jumper

w19

w2@

w15

W16

wll

W12

#MB

16MB

20MB

24MB

Number Jumpers
Visible on Control

Panel)

Multiport

(Number
Signal

Set

Jumper

Multiport

Set

Multiport

Jumper inserted.
No jumper.
Standard

configuration.

240

MA780 BACKPLANE DATA

PORT 3
INTERFACE BACKPLANE

(OPTIONAL)
1

2
3

1 {M8210 MAY

2 [M8210 MAY

1.75 ~ 2M BYTE

15> 1.75M BYTE

OPTIONAL

3 |[M8210 MAY

1.25 > 1.5M BYTE

OPTIONAL

|m8210

mMAY

1.0+ 1.25M BYTE

OPTIONAL

5|M8210

MAY

756 ~ 1000K BYTE

OPTIONAL

MAY

512~ 756K BYTE

OPTIONAL

|[M8210

7 [MB210 MAY

256 ~ 512K BYTE

|M8210

MAY

0—+ 256K BYTE

[M8210

MAP

SELECTIVE CACHE MAP

OPTIONAL

MDT

MEMORY DATA PATH

[

MAT

MULTIPORT ARRAY TIMING

MULTIPORT PORT SYNCHRONIZER

‘—] !

16 |M9045 PORT 2 BDI CONNECT FROM REAR

OPTIONAL

[M9045

PORT 1

MULTIPORT PORT CONTROL PORT 2

INTERFACE BLANKPLANE

OPTIONAL

7014103 BLANK MODULE

’

M9040 SBI TERMINATOR

pe— -

M3045 PORT 1 BDI CONNECT FROM REAR

M8258 MULTIPORT INTERFACE

PORT 1

BDI CONNECT FROM REAR

19 |[M8259 MPC

MULTIPORT PORT CONTROL PORT
0
BDI CONNECT FROM REAR

PORT 0

PORT 2

M9045 PORT 2 BDI CONNECT FROM REAR

MULTIPORT PORT CONTROL PORT 1

{M9045

MB8258 MULTIPORT INTERFACE

PORT 1

OPTIONAL

mPC

14 [M9045 PORT 3 BD! CONNECT FROM REAR

|[M8259

M9040 SBI TERMINATOR

f—bd

|M8261

]

|[MB260

MULTIPORT PORT CONTROL PORT 3

7014103 BLANK MODULE

|M8212

{M8259 MPC

PORT 3

(OPTIONAL)

MPS

M9040 SBI TERMINATOR
M8258 MULTIPORT INTERFACE

M9045 PORT 3 8DI CONNECT FROM REAR

IPNO:E.I.RZFACE BACKPLANE

15 |M8269 MPC

TF‘?:ETR(::ACE BACKPLANE
{SEE NOTE 3)

117014103 BLANK MOOULE

NOTES:

-4

7014103 BLANK MODULE

SEE NOTE 2

INSERT BLANK MODULES 7014103 IN ALL FRONT

THE SBI TERMINATOR (M9040) IS REMOVED IF THE

S8/ CONTINUES BEYOND THE PORT INTERFACE
BACKPLANE.

2 | M7040 SB! TERMINATOR
3 | M8258 MULTIPORT PORT INTERFACE

SLOTS CORRESPONDING TO M9045 BD!I CONNECT{ONS.

PORT
0

M3045 PORT 0 BDI CONNECT FROM REAR

SEE NOTE 1'—/

EACH PORT INTERFACE BACKPLANE MOUNTS INTO

A DIFFERENT CPU CABINET.

IF ADDITIONAL MEMORY STORAGE IS TO BE ADDED
TO THE MA780, IT MUST BE CONTIGUOUS WITH THE

EXISTING MA780 MEMORY. FOR EXAMPLE:

IF A

256K BYTE BOARD (M8210) IS ADDED TO A 512K
BYTE SYSTEM, THE NEW BOARD MUST BE LOCATED

INSLOT 6 AS THE 512 — 756K BYTE.

IF THE MEMORY

STORAGE BOARDS ARE MISCONFIGURED, A RED

LED ILLUMINATES ON THE M8260 MODULE IN SLOT
12.

TK8358

241

M8210 MEMORY ARRAY CARD MNEMONICS

The

following

table

shows

the

cross-correlation

between

the

mnemonic when the card is used in the MS788¢ main memory and the

The
MA780 multiport memory subsystem of the VAX-11/788 system.
M821¢ array card, in addition to its identical memory storage
the multiport memory.

(one card)

As Array Card in MA788

As Array Card in MS78@

Multiport Memory

BUS ENAB ARRAY OUT H

EL1 MATJ ARY OUT EN H

BUS
BUS

MOS
MOS

DAT
DAT

Cg¢@
C21

BUS
BUS
BUS

MOS
MOS
MOS

DAT C#A2
DAT C@3
DAT C@4

BUS
BUS
BUS

MOS
MOS
MOS

DAT C@5
DAT C#6
DAT C@7

BUS

MOS

DAT

L@@

BUS
BUS

MOS
MOS

DAT
DAT

L@l
L@2

BUS

MOS

DAT

L@3

BUS
BUS

MOS
MOS

DAT
DAT

L@4
L@5

BUS
BUS
BUS
BUS
BUS
BUS

MOS
MOS
MOS
MOS
MOS
MOS

DAT
DAT
DAT
DAT
DAT
DAT

L@6
L@7
L#8
L@9
L1@
L11

BUS
BUS

MOS
MOS

DAT
DAT

L12
L13

BUS
BUS

MOS
MOS

DAT
DAT

L14
L1S

BUS
BUS

MOS
MOS

DAT
DAT

L16
L17

BUS

MOS

BUS

MOS
MOS

DAT
DAT
DAT

L19

BUS

L18

BUS

MOS

DAT

L21

BUS

MOS
MOS

DAT

BUS

DAT

L22
L23

BUS

MOS

DAT

L24

BUS
BUS

MOS
MOS

DAT
DAT

L25
L26

BUS

MOS

DAT

L27

BUS

MOS

DAT

L28

BUS

MOS

DAT

L29

BUS

MOS

DAT

L30

BUS

MOS

DAT

L31

BUS

MOS

DAT

Ug#

BUS

MOS

DAT

U@l

BUS
BUS

MOS
MOS

DAT
DAT

Ug@2
U@3

L2@

BUS

MOS

DAT

U@4

BUS

MOS

DAT

U@5

BUS

MOS

DAT

U@6

BUS

MOS

DAT

Un7

BUS
BUS

MOS
MOS

DAT
DAT

U@8
U9

BUS

MOS
MOS

DAT

Ul#@
U1l

BUS

DAT

:I::I:EIIEIIIIIIEEEI:IIIIII::IIIEI:EEI:I:IIII:IE:I:II:II

Main Memory

as the invalidate

As Invalidate Map in MA789

Mgltiport Memory
Pin

EL1 MPSK INVAL OUT EN
BUS
BUS
BUS
BUS
BUS
EB1 BUS
DP2 BUS
DR2 BUS

INVAL
INVAL

AF1
AEl1
DL1

INVAL DAT P@2
INVAL DAT P@3
INVAL DAT P¢4
INVAL DAT P@5
INVAL DAT P@6

BUS
BUS

INVAL
INVAL

AL1 BUS
AK1 BUS
BA1l BUS
AV2 BUS
AUl BUS
AR]1 BUS
BE1 BUS
BD1 BUS
BC1 BUS
BBl BUS

INVAL

BK1 BUS
BJ1 BUS
BH2 BUS
BF1 BUS
BP1 BUS
BN1 BUS
BM1 BUS
BL1 BUS

INVAL DAT Bl2
INVAL DAT B13
INVAL DAT Bl4

AN1
AM1

BV2

BUS

BU2

BUS

BS1
DR1

BUS
BUS

CK2
CJ2
CM1
CK1
BH2
CF2
CE2
CD2
DV2
DU2
DT2
DS2

BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS

ED1
EEl1
EF2
EH2
EJ2
EK2

BUS
BUS
BUS
BUS
BUS
BUS

EL2 BUS
EM2 BUS

242

DAT P@@
DAT P&l

AJ1
AH2

INVAL DAT P@7

B@#
B@l
DAT B@2

DAT
DAT

INVAL DAT
INVAL DAT
INVAL DAT
INVAL DAT
INVAL DAT
INVAL DAT
INVAL

INVAL
INVAL

B@3
B@4
B@S

B@#6
B@7
B@8

DAT

B@9
DAT Bl@
DAT Bll

DAT B15S
INVAL DAT Bl6
INVAL DAT Bl7

INVAL

INVAL DAT
INVAL DAT
INVAL DAT
INVAL DAT

Bl8
B19
B2#
B2l

INVAL DAT B22
INVAL DAT B23
INVAL DAT B24
INVAL DAT B25
INVAL DAT B26
INVAL DAT B27
B28

DAT
INVAL DAT
INVAL DAT
INVAL DAT
INVAL DAT

B29
B3@
B3l
B32

INVAL
INVAL
INVAL
INVAL
INVAL
INVAL

B33
B34
B35
B36
B37
B38

INVAL

DAT
DAT
DAT
DAT
DAT
DAT

DAT B39
INVAL DAT B49
INVAL DAT B4l
INVAL DAT B42
INVAL DAT B43

r-'t-'rr‘rrrr‘r‘r‘r‘r‘r“r‘r‘r‘r'r'r‘r'r'rr*r*r'r'r'r'r‘r*r'r-r‘r*r-r'r‘r*r'r'r*r‘r'r':!::::x::::x::z::::z:

function in both memories, is used

map of

M8210 MEMORY ARRAY CARD MNEMONICS (CONT)

BUS

MOS

DAT

uls

BUS

MOS

DAT

uie

BUS

MOS

DAT

ul7

BUS

MOS

DAT

UlR

BUS

MOS

DAT

ul9

BUS

MOSs

DAT

u2g

BUS

MOS

DAT

uz21

DAT

U22

BUS

MOS

DAT

BUS

MOS

DAT

u23
u24

BUS

MOS

DAT

u25

BUS

MOS

DAT

U26

BUS

MOS

DAT

u27

BUS

MOS

DAT

BUS

MOS

DAT

u29

BUS

MOs

DAT

u3e

BUS

MOS

DAT

U3l

ouT

SEL

BUS

u2s

MAY

CHIP

16K

MAY

CHIP

MAY

1 5L

MCNB

CAS

MCNB

INT T

CNTRL

REA D

ARY

EXT

MCND

ARY

ADR

MCND

ARY

ADR

MCND

ARY

ADR

MCND

ARY

ADR

MCND

ARY

ADR

ARY

ADR

MCND
MCND

ARY

ADR

MCND

ARY

ADR

MCND

ARY

ADR

MCND

ARY

ADR

MCND

ARY

ADR

MCND

ARY

ADR

ARY

ADR

MCND

ARY

ADR

MCND

ARY

Ccs

MCND

RAS

MCND

REF

cyc

ITXINTITT

ARY ADR
MCND ARY ADR
MCND ARY ADR

MCND

MCNB
MCND

MUX

MCNB

L
H

DAT

INVAL

DAT

B4S

EP2

DAT

B46

EF1

BUS

INVAL

DAT

B47

EV2

BUS

INVAL

DAT

B48

EUl

BUS

INVAL

DAT

B49
B50

BUS

INVAL

ET2

BUS

INVAL

DAT

FJ2

BUS

INVAL

DAT

B52

FH2

BUS

INVAL

DAT

B53

FF2

BUS

INVAL

DAT

B54

GND

FR1

BUS

16K

BUS

FB2

BUS

PRES

BIT

cJ1

MATJ

ARY

CAS

DBl

MATR

INIT

MATJ

CHIP

ARY

MUX

CNTRL

DL2

MATJ

ARY

READ

DAl

MATA

ARY

ADR

14
21
22

DB2

MATA

ARY

ADR

Ccv2

MATA

ARY

ADR

DJ2

MATA

ARY

ADR

DH2

MATA

ARY

ADR

83
64

CT2

MATA

ARY

ADR

DK2

MATA

ARY

DF1

MATA

ARY

ADR

DF2

MATA

ARY

ADR

CR2

MATA

ARY

ADR

Cs2

MATA

ARY

ADR

DD1

MATA

ARY

ADR

DE1

MATA

ARY

ADR

DM2

MATA

ARY

ADR

CM2

MATA

ARY

ADR

Ccp2

MATA

ARY

ADR

CL2

MATA

ARY

ADR

DAT

B51

FE2

BUS

INVAL

DAT

B55

Fp2

BUS

INVAL

DAT

BS56

Fpl

BUS

INVAL

DAT

FM2

BUS

INVAL

DAT

B58

FL2

BUS

INVAL

DAT

B59

FU2

FS1

INVAL

B44

B57

BUS

INVAL

DAT

Fv2

BUS

INVAL

DAT

B61

FT2

BUS

INVAL

DAT

B62

FS2

BUS

INVAL

DAT

B63

CD1

GND

FRI

BUS

16K

FS1

BUS

FB2

INVAL

MAP

CJ1

MPSK

INVAL

DB1

MATR

INIT

CL1

MBSK

CHIP
CH IP

B69

L
L

PRES

CAS

L
CNTRL

INVAL

MUX

DL2

MPSK

INVAL

READ

DAl

MATA

ARY

ADR

DB2

MATA

ARY

ADR

Ccv2

MATA

ARY

ADR

DJ2

MATA

ARY

ADR

DH2

MATA

ARY

ADR

CT2

MATA

ARY

ADR

DK2

MATA

ARY

ADR

DF1

MATA

ARY

ADR

DF2

MATA

ARY

ADR

CR2

MATA

ARY

ADR

Cs2

MATA

ARY

ADR

DD1

MATA

ARY

ADR

DE1

MATA

ARY

ADR

DM2
CM2

MATA

ARY

ADR

ARY

ADR

GND

Cp2

GND

CL2

GND

CN1

GND

DC1

MATA

ARY

ADR

DC1

MATA

CpPl

MATJ

ARY

RAS

CPl

MPSK

DJ1

INVAL

RAS

MATK

REF

CcYcC

DJ1

MPSK

INVAL

REF

CYC

243

]

INVAL

BUS

EU2

CL1

MA789

BUS

ES2

ER2

CDl1

Map

Memory

ol ol ol ol o

Ul13
ul4

Invalidate

Multiport

DAT
DAT

ol ol ol ol

Ulz2

MOS

MA78@

ol ol o

DAT

BUS

Memory

TrXrIDnonDIIxronToTrmoic
:

MOSs

Card

Pin
TIITIINIIOSOoTDIaOaDITI@NXXTInT
X

BUS

Array

Multiport

MS780

o S

[

Card

Array

DN IITISII@ID
ST X

As
As

Main Memory

H
H

M8212 DATA PATH/ECC CARD MNEMONICS

The

following

path/ECC

card

shows

memory

used

Used

function

the

subsystem

identical
As

table

MS78¢

the

MS78%

MCNA

ARY

CLR

MCNA

ECC

mnemonics
between

memory

VAX-11/780

system,

for

and

Used

the

M8212

the mnemonic

MCNA RD
MCNA RD
MCNA WR

DAl EN L
LO SEL L
EN LO H

MCNA

MCNB

ARY

UP H
DAT CK

MCNB

CHK

BIT

DAT

MCNB

CHK

DAT

MCNB

INIT

MCNB

MSK

CLR

MCNB

READ

MCNB

TAG

CLK

MCNB

UNCOR

H
CK

H
L

ERR

MA788

multiport

when

the

The

M8212

serves

in MA780

CLK

MATK

ARY

EB1

MATJ

CYC

CLR

FUl

MATJ

ECC

ED2
EC1
EJ1

MATK RD
MATK RD
MATJ WR

DAT EN L
LO SEL L
EN LO H

EF1
DM1

MATJ

ARY

UP H
DAT CK

DD2

MATJ

CHK

BIT

DAT

DD2

MATJ

CHK

BIT

DAT

CLK

DB2

MATR

INIT

DF2

MATJ

MSK

CLR

ELl

MATJ

DJ1

MATJ

GEN

ECC

DF1

MATJ

TAG

CLK

DE2

MATJ

UNCORR

EAl1

MATJ

XMT

DAT

EM1

MATF

CRD

INH

L
H

L
L

ERR

XMT

DAT

MCNE

CRD

INH

MCNE

DIAG

FS1

MATE

DIAG

MCNL

FRC

CHK

FR1

MATD

FRC

CHK

MCNL

FRC

CHK

FPl

MATD

FRC

CHK

MCNL

FRC

CHK

FN1

MATD

FRC

CHK

MCNL

FRC

CHK

FM1

MATD

FRC

CHK

MCNL

FRC

CHK

FL1

MATD

FRC

CHK

MCNL

FRC

CHK

FK2

MATD

FRC

CHK

MCNL

FRC

CHK

FK1

MATD

FRC

CHK

MCNL

FRC

CHK

MDTC

SYN

MDTE

FULL

DUl

MCNB

H
WR

FJ1

MATR

FRC

CHK

FD1

MDTA

SYN

DJ2

ADR

BUS

CM1

MATH

ADR

BUS

DAT

BUS

CL1

MATH

DAT

BUS

MSBJ

EXT

DR1

BUS

ADMI

EXT

MSBJ

DP1

BUS

ADMI

B29

BUS

CMD

DS1

SUB

ADMI

B29

BUS

INF

AAl

BUS

ADMI

B@#9

BUS

INF

@21

AB2

BUS

ADMI

B@l

AD2

BUS

ADMI

B@2

AE2

BUS

ADMI

B@3

AF2

BUS

ADMI

B@4

AJ2

BUS

ADMI

B#5

AK2

BUS

ADMI

B#6

AL2

BUS

ADMI

Bg7

AM2

BUS

ADMI

B#8

AR2

BUS

ADMI

B#9

INF

BUS

INF

¢4

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

olia offite ofife s Ja ofifa

FL
FL

jaofa ofiie ofif sflie sfiia o« ofiie ofifa pille s

BUS
BUS

AV2

BUS

ADMI

Bl#@

BAl1

BUS

ADMI

Bll

BB2

BUS

ADMI

Bl2

BD2

BUS

ADMI

B13

BE2

BUS

ADMI

Bl4

BK2

BUS

ADMI

B15

244

jacilis cle sfic ofifia ol s Je ofite olite offt = ofiie olife offie ofic offifa o

H
H

ofiis sfifa ofiba o}

MSBH
MSBH

ARY

data

the

Multiport Memory

main

in both memories.

Main Memory

MCNA

signal

the cross-correlation

M8212 DATA PATH/ECC CARD MNEMONICS (CONT)

MS78¢

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

BUS

INF

28
29

BUS

INF

MSK

BUS

MSK

BUS

MSK

BUS

MSK

BUS

PAR

INF

BUS
BUS

siie sl ol 2 ol sflfe plte slie ol e o fle o« o« o]

BUS

BM2

jecliie ~iie cjiie e

BUS

Used

Multiport

245

BUS

MA78¢
Memory

ADMI

B16

BP2

BUS

ADMI

B17

BR2

BUS

ADMI

B18

BS1

BUS

ADMI

B19

BV2

B29

BUS

ADMI

CAl

BUS

ADMI

B21

CB2

BUS

ADMI

B22

CE2

BUS

ADMI

B23

CF2

BUS

ADMI

B24

CH2

BUS

ADMI

B25

CJ2

BUS

ADMI

B26

CK2

BUS

ADMI

B27

CL2

BUS

ADMI

B28

cM2

BUS

ADMI

B29

CR1

BUS

ADMI

B39

CR2

BUS

DM2

BUS

ADMI
ADMI

B31
MSK

DL1

BUS

ADMI

MSK

DK2

BUS

ADMI

MSK

DL2

BUS

ADMI

MSK

DK1

BUS

ADMI

WhHHFRIIIIIDIIn
I
oIS @m@mx

Memory

2 =fiia e riiie

Used

Main

ja siie ofite ofibe of

S8 TO CPU B

SBI TO CPU C

$81 TO CPU D

M8258
MULTIPORT
INTERFACE
MODULE (MP})

M8258
MULTIPORT
INTERFACE
MODULE (MP1}

MB258
MULTIPORT
INTERFACE
MODULE (MPI)

M8258
MULTIPORT
INTERFACE
MODULE (MPD)

(RESIDES IN CPU
A CABINET)

(RESIDES IN CPU
D CABINET)

(RESIDES IN CPU
C CABINET)

(RESIDES IN CPU
B CABINET)
BIDIRECTIONAL INTERCONNECT (BD1)

WVHOVIA XJ079 AHOWIW LHOdILTNIN 08LVIN

SBI TO CPU A

16 FEET OF CABLE

213 COMMAND AND s STATUS L LINES

SEPARATES THESE

MODULES

[*—1=z—15 COMMAND AND STATUS LINES
1243 BIDIRECTIONAL LINES {FOR
COMMAND/ADDRESS, MASK,

M8258
MULTIPORT
CONTROLLER
MODULE (MPC)
ADDRESS/DATA

)74

4 INFORMATION LINES —]

[we2r2

DATA PATH/ECC
MODULE

(MOT)

INTERCONNECT (MAI)

9 CONTROL LINES —2
8 PRESENCE BIT LINES

{1 PER BOARD)

TIMING INPUTS

m8210

é::gv

NO. 1

M8210
22:8"

NO. 2

* {;

JCONTROL OUTPUTS MODULE (Mps) |—BCONTROLLINESo) (0pTIONAL)
Y
7

| CONTROL INPUTS

M8261

PRESENCE BIT

INVALIDATE
MULTIPORT m MAP
SYNCHRONIZER
15

CONTROL
PANEL

MODULE (MAT!

ADDRESS | CONTROL

L INES | LINE

—1

—

A;’RAY TIMING
A TROL

—o—o——
[

8260 oRT

38 ADDRESS/DATA LINES

}

_'i

STATUS

—

T ; 4\ i i

‘

§ ECC DIAGNOSTIC CONTROL

19 ADDRESS LINES

72 DATA LINES _r+—~

DATA PATH TIMING

—

T 1 F

r__A__fi

MEMORY CONTROL SECTION

I T

—

25 COMMAND LINES —]

M8259
MULTIPORT
CONTROLLER
MODULE {MPC}

MB259
MULTIPORT
CONTROLLER
MODULE (MPC)

fl'

/MASK INTERCONNECT

MEMORY ARRAY

ID, AND PARITY)

NOTES:
1.

ALL MODULES EXCEPT M8258 MULTIPORT INTERFACE MODULES

(IN CPU CABINET) PLUG INTO MULTIPORT CONTROLLER BACKPLANE,

(256 K BYTES).
2. EACH M8210 ARRAY CARD STORES 32,768 72 BIT WORDS MB210
MEMORY

CONTROLLER CAN ACCOMMODATE UP T ) 8
MULTIPORT
3. ARRAY
CARDS, PROVIDING TOTAL MAXIMUM STORAGE CAPACITY OF

U
M8210

ARRAY

figfig

2 MEGABYTES.

1641

MPID

TAG

MPIH

BUS BDI TAG<1:0>

LOGIC
e

BUS SBI REQ<7:4>

MPIB,N,M.P,R

INTERRUPT
LOGI
GIC

BOI

BUS SBI FAULT

MPIM

FAULT

RECEIVERS

SBt
CONFIRMATION
LoGIC

PARITY
LOGIC

BUS 8DI P<t:0>

MPCB,C.O MNP T

LYC

MPIB,F

BUS SBI {T, PD, PD) CLKS

CONTROL INFO

LOGIC

MPIB.F
BUS SBI CONF<1:0>

CONTROL INFO

DRIVERS

MPIJX

RAM ADDRESS

CONTROL LOGIC

.|
CLOCK
|
Js

MPIP,R

BUFFERED ECL CLKS

LOGIC

MPIC

LOGIC

DATA PATH

BUS SB1<31:00>

BUS BD!I 8<31:00>

WPIAEF.HKLRS

BUS SBI DEAD

DEAD

BUS S81 UNJAM

PWR FAIL AND

UNJAM LOGIC
MPIB,H
.M

INVALIDATE

LOGIC

BUS SBI TR<15:00>

SBt

MPIH

ARBITRATION

LOGIC

BUS $BI 1D<4:0>

MPIBJ
1D LOGIC

BUS BDI 1D<4:0>

MPIB.F.LMNPU

BUS SBi M<3.0>

MASK LOGIC

BUS BDI MSK<3:0>

MPIAM.N.P.U

TK-1049

WYH5VIA %0079

CHECK

BUS SBI TAG<2:0>

MARK CONTROL
AND TIMEOUT
LOGIC

SBI PARITY

(8G28W) 3ITNAOW JOVIHILNI AHOWIW LHOdILTININ 08LVIN

MPCB,L,

BDI TO MPC AND ADMI

ADMI

DATA PATH LOGIC

MPCA,B,D,E,J

ADM! AND MPC TO BDI

8ve

DATA PATH LOGIC

MPCA,F
HJ KR T

CLOCK

LOGIC

MPCT

MASK
AND PARITY
LOGIC
MPCB.F H.P R

ADDRESS

AND
FUNCTION

1/0
DECODE

DECODE
MPCC, LM

MPCN

WRITE

COMMAND

BDI

ADMI

CONTROL
MPCN

CONTROL
MPCE, L

BUFFER

INTERLOC

RLOCK

DATA

AND
MARK

EXPECTED

CONTROL

MPCN

ID LOGIC
MPCB,E

ADMI

LATCH

COMMAND

CONTROL
MPCR

SYNC

MPCK P

NIT

CONTROL
MPCM,
R

1648

(6GZ8W) 3TNAOW HITTOHLNOD AHOW3IW LHOJILTNW 08LVIN

WVHOVIA %0019

TAG LOGIC

ADMI TRANSFER

<—»]

DECODE
(MATH)

TRANS

READ DATA RETURN FLAGS

ADMI TRANSFER

g |TMING
e TMG | (MATH)

POR. OUT EN RD DATA RETURN

START 10 CYCLE

ON BUS
ADDR

DATA ON BUS |END OF

_MAP GO

REFRESH )

START ARRAY CYCLE

ADMI ’,4

ARBITER

(MATLM)

GRANT

COMMAND
ABORT

ERR

o6
CHECK
[MATH)

—

BUFFERED|

WRITE ABORT

ADMI

ADDR ON ausj

6v¢

MAP TIMING BUSY

COMMAND

81Ts28-31|

ADMI

je—REFRESH REQUEST

DECODE

1/0

ADI;RESS
BIT

(MATR)

PORT POWER
STATUS

[mERRORIN XFER

BTs0_15 | REGO

| (MAT D.E.F)

BUFFERED

ADMI

1/0 COMMAND

[1/O ADDR SELEC

4
[#<PORT ERROR

222'“ ?;RI‘F:/;)TOR
-

:CC

UBSTITUTE

BITS T
BI

MATD.EF) |, ARRAY ACCESS

32BITS

(MATD,E,F)

PARITY ERROR
[ CRD INHIBIT

MASKD2

le— 20 81T ADDRESS | REGISTER

le— ERROR SYNDROME :z:::f

LATCH

TAG CLOCK

ARRAY OUT ENABLE
CHECK BIT DATA CLK

BANK SEL

COMMAND

pretlietodes

FULL WRITE

SIGNALS _l

RewRITE CORRECT

DATA CLOCK

WRITE ARRAY

o Timine

MAT
ADDRESS BIT0 | (NTJ (MATY

BUFFER

&BANK

SEL - 48ITS

WRITE ENABLE LO

WRITE ENABLE UP

s ARRAY READ
L5/
ARRAY ADDR

COMMAND ARRAY

LIS

2817
7

LATCH

(MATC)

PARITY [ERROR
CHECK

4k/16K

pp——

REFRESH
&

INIT
114 REFRESH
REQUEST *—] ADDRESS

REFRESH

GRANT

LATCH
(MATC)

L= END OF WRITE
GENERATE

,
ARRAY SIZE] 8
Y siz
(MATC)
ENCODER & |7~ ARRAY PRESENCE
PARITY ~ ARRAYSIZE=—4

EVEN PARITY 0,1

READ ERROR

ECC ENABLE

ARRAY BOARD

COMMAND WRITE
COMMAND EXT.

ADMI (32)

BUFFER

DATA CLOCK

L
.

MOS CHIP ADDRESS 1-+14

BUFFERED

32817

REWRITE CORRECT

(MATJ)

ECC CHECK CLOCK

BOARD SEL
ADDRESS [ 2

BITSO-18

CORRECTION
—
] TIMING

ECC ENABLE

XMIT DATACLK

BITS 27,28, 31
(MATC)

EXPECTED

}
ERROR

ECC BYPASS

REFRESH

ARRAY DATACLK

MAP PARITY INVERT

BUFFERED
B(29:3T]
ADM!

READ
READ

COMMAND

AT
|~ ECC BYPASS
gg;«%m
REGISTERS |—# FORCE ECC ERROR

ARRAY
REGISTER

Loans

(MATK)

FULL WRITE

END OF

(MATK!

le— NITSTATUS | SIGNALS

10 RD DATA EN

REFRESH GRANT

ADR
ADDR ON BUS
I LATCH ERROR INVAL
MAP

16 8ITS

BITS 031

DATA ENABLE

REFRESH
TIMING

[CONFIG.€RR
[,

INITIATE
READ DATA
ECC CHECK CLOCK — TrANSFER

READ ERROR

10 READ

DISABLE

PARITY

8ITSO - 31

Y4 of

STATUS

10 DATA READY

TOWRITE ENABLE

MEMORY |TIMING BUSY

OFF LINE

CONFIG.

L"A“'TY ERROR

/0
purreren] ADDRESS
ADMI——1

ARRAY MUX CNTRL

L’nAs

ARRAY CAS

|MEMORY TIMING BUSY

le—ENABLE ARBITER

TIMIN

(MATR)

ARRAY

REFRESH GRANT

PROCESS ADMI TRANSFER

5o 7 aom

CYCLE TYPE—a|

(MAT 0.K)

ADMI HOLD NEXT DATA REQUEST

ADMI

END OF WRITE

" FRONTEND | eRROR IN XFER

END OF READ | ARRAY
JANCT

{

CONFIG.

BITS

CONFIG ERROR |ERROR

NON CONTIG «—{ (MATE)

[

DETECTION

GENERATION

TIMING
&

+5V BAT

INIT STATUS |

INIT IN PROGRESS

4K/16K LINES

TK.4176

WVYHOVIA X2019 (09Z28W) 3TNAON

COMMAN

ASIGNALS

RD DATA EN

TYPE

TOHLNOID ANV ONINIL AVHHY AHOW3IW LHOJILTNN 08LVIN

READ SEL,

[_. CYCLE

MAT

DECODE

MPSLM [ ADDRESS ON BUS
d

MAT

"E;RESH

CMD ABORT

MUX CTRL | MAP

REFRESH

MAP ACC EN

|MAP ACCESS EN
<

MAP PTY DISABLE

Ty
ERR

READ

OUT EN

ADDRESS/
FUNCTION

LATCH

MAP

BUS ADMI<B31,829,827] ADDRESS/
B20,818,817,818,810:
]FUNCTION

745734

MAT

| CMPT

REG WRITE CLK

BOO> ID1,1D0

MPC

cvc | PRES| TYPE

RO DAT TOADMI

MAP

MAP | MAP | PORT | MAPGO

DAT ON BUS

INVALIDATE MAP
TIMING & CONTROL

MPSJ

y
BUS INVAL DAT<B63:B800,P07:PO0>
INVALIDATE MAP DATA PATH

MPSE 1K

MPSAB.C.D.E

BUS INVAL DAY <B863:800,P07:P00>

)

AOMI

TRANSMIT

SEND IVDT
BACKUP MODE

RETURN DATA EN

0S¢

RECV ADMI<B31:800>
D KBuS ADMI<B32:800>] mpsL i M (BUS
M
NS

ENAGM DATA |
wps paTA BUS

BUS

745373
US RECV ADMI<E31:800]

DATA

BUS ADM!I<B832:B00>

BOOTSTRAP
ROM
1K X 32

ENWRITE DATA

LATCH
TM7
DATA ON BUS
MPSLM | BUS RECV ADMI<B31:800>

GRANT

MPC

MPC MPC MPC

<B31:800>
;
| |

|ReADseLecT1

EN READ DATA

REQUEST

BUS RECV ADMI

READ SELECT 0

MPSN

MPSP.R

4:1 MUX
(16 BITS)

16,
7

7415253

7415240

CLKENABREG 2,

MULTIPLEXER|
'

DETECTION

MPSU

Ps DCLO

COLODGSTA':l: MAT.MPC

LOGIC INIT,

pat

CLK REQST REG

745373

}A{

READ DATA

23;;‘1'.

BOO>
—

:'\

RECV

BUS ADMI P1

LATCH BIT<7:0>
RECV PTY BIT

BUS RECY ADMI<B31:
{TRI-STATE)

MPC

BACKUP

oD T

ADDR<A09: AO0>

BUFFER

DCLO/POWER

LOGIC INIT

REFRESH

INTERLOCK ARBITER

MPSR,V.W,X
VW,

BUS RECY ADMI <B31:800

INTERPORT INTERRUPT REQUEST REGISTER]

INTERPORT INTERRUPT ENABLE REGISTER

MPSS,T

;

oW8

CONF
CLK K CONFG
REG

BUS RECV ADMI <B15:8122%

PORT TYPE MAP PRESENT
GRANT ACCEPTED

|INTERRUPT

UNJAM

MPC

CONFIGURATION
§TATUS
REGISTER 1
MPSH,R

MK GRANT ERR 44—e-MPC
VDT ACK

4 wrc

K33

S
Tx 2298

(L9Z8) 3TNAOW HIZINOHHIONAS AHOWIW LHOdILTNW 08LVYIN

MPC

ADR ON BUS

AWVYHOVIA %0018

MAT

MAP INIT H

BUS RECY ADMI<807:800> H

MAP DATA BUFFER
MPSE

745373

8
8

:
OlBYTE MUX

WYHDVIA X008

745373

1
MPSE

PULSE

CORRECT

LATCHED BIT<7:0>H

(TO READ DATA MUX)

SEND IVDTH

(TO PORT CONTROLLERS)

MPSC

ENABLE L

MAP INIT L

MAP PTY DISABLE L

MPSC

BUS INVAL DAT<PO7:P00> L -S4

RECV PTY BITH

{TO READ DATA MUX)

MpsC

MAP PTY ERR L

{TO TIMING & CONTROL BOARD)

LGC

TIMING

MAP PRESENT
H

MAP PRESENT H
REFRESH CYCLE H

RECV ADDR A27 H
MPSC
TK-3390

HLVd V1Va dVIN 31VAITVANI AHOWIW LHOdILTINN 08LYIN

8164 BIT DEMUX

MAP DATA LATCH

BUS INVAL DAT<B63:B00> L

PRTO INLK GNT

FIRST

LATCH

SECOND

TIE-BREAKER

LATCH

ROM

ax4

PRTTINLK GNT

PENDING

]7\

PRT2 INLK REQ#-

PRTIINLK REQ

r"l_J
Mrsy

GRANT

| o

MPSV

ARB INPUT
cLKY

FILE

MPSY

MPSV

ARB INPUT CLK2

LAST GNT B1|

LAST

FILE WRITE CLK

PRT2 INLK GNT

PRT3 INLK GNT

MPSV

PENDING CLK

FILE

|GNT BO

MPSV

PENDING

INPUT

GRANT
ENABLE

MPSW

TIMING

CHAIN

J
ey

MPSW

L——a

PENDING STATUS

{e—o]

[ATA

AND

LAST GRANT
CLEAR

PENDING
PENDING CLK

MPSV

P3 PENDING

PO PENDING

GRANT

PENDING

PRTO ACPT INLK

OUTPUT

PRTT ACPT INLK

TIMING
CHAIN

PRT2 ACPT INLK®—
PRT3 ACPT INLK®—

MPSX
TX3399

WVYHOVIA 30019

PRTT INLK REQP—

431194V JO0THILNI AHOWIW LHOdILTNN 08LVYIN

Sfelste

PRTO INLK REQ

AWVYHOVIA %3079

v
B8 SYNDROMES TO CONFIGURATION REG ‘C’ (MB213) 4—————1

4 MASK

SYNDROME

:ECODE

2 TAG LINES

MDTS
MASK

CONTROL
LOGIC

BUS ADMI

SATA

TRANSMIT

Efzg:

CORRECTION

|—» 8 MASK CONTROL

8 (31:00)

LOGIC

SIGNALS

64 CORRECTION FLAGS

MDTD,F

64 CORRECTED
DATA BITS

MDTE

MDTH,R

MDTH-R

WRITE

€6¢

DATA

BUS MOS DATA UPPER

WORD<31:00>

BUS MOS DATA XX

UPPER<31:00>

LATCH

ECC

LOWER<31:00>

(UPPER

64 DATA BITS

CHECK
LOGIC

WORD)

8 MASK

MDTAB.C

CONTROL
SIGNALS
\g:gfi

8US MOS DATA

LATCH - f

LOWER
WORD
s

(LOWER

WORD)

UPPER/LOWER

PARITY

CHECKPARITY
F—T* WORD

MDTH.K,

64 ARRAY

oaTA UNes|

REC

Mos

ARRAY

REC

DATA

LATCH

MDTJ,L
NR

MDTH.A

NSNS

MDTC

TO MOS

ARRAY

CHECK

e CHECK BITS

BIT

DATA
MDTE

M8214

CHECK BITS

MOS

—

MDTS

ARRAY

mDTB

8 DIAGNOSTIC CHECK BITS

8 CHECK BITS TO MOS ARRAY

MDTC.T

8 CHECK BITS

FROM MOS ARRAY
MEMORY ARRAY INTERCONNECT

N
TK-3448

(ZLZ8W) ITNAOW J23/HLVd V1vA AHOWIW LHOJILTINW 08LVIN

BUS ADMI B {31:00): BUS ADMI MASK (03:00)

DR780 REGISTERS

DCR ADDRESS REGISTER
313029282726 25242322212019181716

13121110 0908

U 11}0]010[01010]0!01010[0]0’ TR NO. IOIO[PSL REG. ADDRESS ]
PAGE SELECT
TK-4608

DCR READ REGISTER

pup

pce*

31302928272625242322 212019181716 15141312 1110

covon ([T

L oL LI

Dcs*
0908 07 06 05 04 03 020100

LLL AL L ol el

PTY|URD

[XMT

[PWR

INT [DCR|CRD

tD2

FLTIFLT

FLT

[DWN

ERR

EPR

WSQ

MXT

EXT PWR

FLT

ABT UP

BIT

|ABT

PKT DCR RDS
INT

HLT

FUNCTION

IDD|25':'-(:L$:'ATUS
IDI TO STATUS

BIT

FUNCTION

PARITY FAULT

PACKET INTERRUPT

WRITE SEQUENCE FAULT

UNEXPECTED READ DATA

HALT

UNUSED

CORRECTED READ DATA

MULTIPLE TRANSMITTER FAULT

READ DATA SUBSTITUTE

TRANSMITTER DURING FAULT

COMMAND/ADDRESS TIME OUT ID1

UNUSED

READ DATA EXPECTED TIME OUT ID1

ABORT

EXTERNAL ABORT

POWER DOWN

DATA INTERCONNECT STALL

POWER UP

COMMAND/ADDRESS TIME OUT ID2

UNUSED

READ DATA EXPECTED TIME OQUT ID2

INTERRUPT ENABLE

RECIEVED ERROR CONFIRMATION 1D2

30 15) ADAPTER TYPE CODE

*DCB = CONTROL CODE

254

RECIEVED ERROR CONFIRMATION ID1

DR780 REGISTERS (CONT)

DCR WRITE REGISTER
31

1514

;

20018000 If

121110

0807

—I

——

CONTROL

FIELDB

conTROL
FIELD A

0
0

0
4]

0
1

1
0
0
1
1

1
1
1

1
0
1
0
1

NO OPERATION
CLEAR CORRECTED READ DATA

0
0

[1]
0

0
0

SET EXTERNAL ABORT

4]
1

1
1]

SET OUT OF SEQUENCE TEST
CLEAR OUT OF SEQUENCE TEST
NO OPERATION

1
1

4
1

1
0

NQ OPERATION
CLEARPOWER UP
CLEARPOWER DOWN
NO OPERATION
CLEAR ABORT INTERRUPT AND READ
DATA SUBSTITUTE
CLEAR INTERRUPT ENABLE
SET INTERRUPT ENABLE

CLEAR HALT

CLEAR PACKET INTERRUPT
RESET

1
0

TK-4617

DR780 UTILITY REGISTER

3130292827262524

LI
LT
i

T
(F:I

121110

ABT| PE
DI

WCS FRC

08 07

WCS

S
DATA RATE

VAL

FF THRU FC

—

¢ ARE NOT VALID

D!
PE

TK-4607

265

DR780 TR ARBITRATION JUMPER AND WIREWRAP SELECTION

Signal

SELD

SELC

SELB

SELA

F@2L2

Name

Fp2Cl

2
3
4

I
I

F@2D1
FB2E1
F@2F2

No.

Wirewrap

F@2H?2

Fg2J1

Fg232

I
-

I
--

I
-~

F@2M1

9
10

Fa2P1

-—

Fa2p2

Fp252

-—

F@g2T2

F@2u2

Level

are

and

W3,

for

jumpers
of 14.

for

the

second

DR788

Wirewrap

BUS

Jumper

Wirewrap

FB2L2

F@2T2.

FP2L2

F@2Ul.

Clock

for

the

from

arbitration
a

are

SBI

jumpers

13.

the

first

DR78¢

from

the

second

DR78¢

from

the

DR78¢

W12

the

(these

device
on

backpanel

Wl,

the

should

jumpers

for

the

not

level

for

jumper

DR788

for

the

first

through

the

and

arbitration

TRXX

jumper

customer's

for

W3,

TRXX

install

Fg2Ul

W4,

SBI

the

level

number

BUS

Select

then

DR780) .

then

Wirewrap

Jumper
DI,

anywhere
clock,

FO2N1

clock
be

source

installed

used

source

number

the

DDI

W8.

MSEL Jumper Select - Install the jumper at W7 if the DR788 is not
going to perform DDI arbitration, or be its master.
If the DR788
is to be the master device, the jumper should be installed on any
pins from W9 through W1l2.

256

DR780 BACKPLANE

-M

o TM o —

- "$ |b - x 1 --a E

J16

<&t

Bs3 -

|069 =Sk 9
=

+5V
*PIN1

o©e-~

pb——GND

(REAR VIEW)
TK-5167

257

DR780 BACKPLANE (CONT)

M8296 { M8297 | M8298 | MB8299

M9046

DSM

DDIP

DSC

DCB

DupP

{VIEW FROM SIDE 2)
TK8348

258

DR780 BLOCK DIAGRAMS

SBI CONTROL (DSC) M8296

PARITY CHK, GEN;
MASK CHK,

s8I

GEN;

xmIT

FUNCTION
DECODE;

8065::63

1D COMP,
REC

XMIT

DSCC, H,LM

ADRS

CMND

LOGIC
pscF

REG
| lpsen

0C102

745194

Misc

DCR WRITE

DECODE

745138

DSCH

ocrR | 32

| l7as112

SBI

DSCJ

DATA

RATE

DAR

REG

COUNT}—c

DSCS

745194
DSCS

93516
8

s8I

XCVR XMIT

—

g0
OSCA Rec ——

- /
7l

OUTMUX

s
53

4
16

|'s®

TR JMPR—~~] DSCL
7415259

ouT Of

SEQ
DSCC

132
SBUS REC
745573
DSCT

Tsz
¢

S BUS

()
TK -8352

259

DR780 BLOCK DIAGRAMS (CONT)

CONTROL BOARD (DCB) M8297

132
¥

132

SBI ADRS

BYTE COUNT

REG

LOOK AHEAD

CONTROL
RAM

}

85568

7415377

DCBC

DCBA

DCBB

SBI ADRS

SBI BYTE

COUNTER

7418377

DCBDR

7415169 |

pcec

DDI BYTE

COUNTER

(4 5169] /] DCBE

32} \| 745194

127

7aLs283(

32,

745157

’

S BUS MUX

745153

H
DCBF,

$ 745373

S BUS

S BUS DRIVERS

745241

H
DCBF,

745241

MASK DRIVER

SRE(‘:JS
A

DCBA

S BUS

O
TK8353

260

DR780 BLOCK DIAGRAMS (CONT)

MICROPROCESSOR (DUP) M8298

)}

CONTROL INTERCONNECT

{
18

DUPC

FLAGO, 1
STATE REG
DUPU

745241

CONTROL
INTERCONNECT
CTRL/DATA

745153

'8
LITERAL <15:00>

BUS D<29:02>
+2

LOCAL
STORE

256 X 32
DUPD
%)

a
LS ADR

CNT/REG
DUPU

4WORD REG

WCS PARITY

[DUPM

L
|DUP

i i

wes Ram | o | 32000

BUS WCS D<39:00> | 1K X40
DUPE

fe—r—] usEQ

DUPN

745373

3
32
$BI FUNCTION

745241

S BUS

S BUS RCVRS

E‘Ls‘f; !

DRIVERS

745374

DUPA

}32

DATA

S BUS

O,
TK-8354

261

DR780 BLOCK DIAGRAMS (CONT)

SILO MODULE (DSM) M8299

DATA INTERCONNECT
32

]

DI CONTROL
DSMP,R,S,T

2007

— 1

XMIT REG

| RCVR LATCH

]

< | DSMH
[

[72]

[+ ]

7415161
DSMC

—1

——
0AR

745158

psmD | Low

|HIGH

BANK | BANK
85568 | 85568

DSME | DSMF

| o

@©

|__ReQ1

-4

ssC

—REQ2
L—STALL

L—DD! REQ
DSMM,N,P
SILO CTRL
DSMLMN

BYTE ROTATORS
25510

DSMK

/),

{«32

745241
D

SMA

745241
S BUS
DRIVERS

DSMN
4

BYTE

ROTATORS

25510 DSMB

+32

S BUS
MASK

S BUS RCVRS
745374
DSMA

DRIVER

132

S BUS

P
TK-8355

262

C1780 REGISTERS

313029282726252423222120191817161514 13 1211100908

of | [ofo] | |o
T

PAR|URD

FLTIFLT

WSQ
FLT

8IT

1.7

[xMT

PDN|

[FLT

MXT
FLT

TTITT

cx-

|cx-|cRo
TTMO|TER

PUP

FUNCTION

|eFD

FAIL

RDTO

DEAD

PARITY FAULT

WRITE SEQUENCE FAULT

UNEXPECTED READ DATA FAULT
MULTIPLE TRANSMITTER FAULT
TRANSMIT FAULT
ADAPTER POWER DOWN

ofof1]1[1[ofofo] CONFIGURATI
SeoremagRATION
TT.I

RDS

27
2%
23

07 06050403
02 0100

olojojofo

BIT

FUNCTION

COMMAND TRANSMIT TIMEOUT

ADAPTER POWER UP

READ DATA TIMEOUT

COMMAND TRANSMIT ERROR

17
16
10

READ DATA SUBSTITUTE
CORRECTED READ DATA
TRANSMIT FAIL

08
07:00

POWER FAIL DISABLE
ADAPTER CODE (38 HEX)

TRANSMIT DEAD

313029282726252423222120191817161514131211100908
17161
1312111
070605040302
0100

PORT MAINTENANCE

ojojojojojo|ojo|otojolojofofjo]|oO

CONTROL
AND STATUS

PE ILSP
l

CSPE

BIT
15

FUNCTION

| IPE
1

BIT
07

TRANSMIT MULTIPLE PARITY ERROR

INPUT PARITY ERROR

06
05
04
03

OUTPUT PARITY ERROR
TRANSMIT BUFFER PARITY ERROR

)

UNIN

OPE

XBPE

PARITY ERROR
LOCAL STORE PARITY ERROR
RECEIVE BUFFER PARITY ERROR

09
08

| XMPE
RBPE

CONTROL STORE PARITY ERROR

13
12

IPSA WP | MIE] MIN

02
o1
00

LRI

2001C004 OR 2001C010

MIF MTD
RSVD

FUNCTION
UNINITIALIZED STATE

PROGRAMMABLE STARTING ADDRESS
RESERVED
WRONG PARITY

MAINTENANCE INTERRUPT FLAG

MAINTENANCE INTERRUPT ENABLE
MAINTENANCE TIMER DISABLE
MAINTENANCE INITIALIZE

3130 29282726 262423222120191817 1615 14 1312 111009
08 0706 05 040302 01 00

ololo|olofofo|olo]o]o[c]olo|ejolo]o]0

MAINTENANCE

ADDRESS 2001C014
|-

MAINTENANCE CONTROL STORE ADDRESS <12:00>~———J

313029282726 252423222120191817 161514 1312 1110

0908 0706 05 04 030201 00

MAINTENANCE CONTROL STORE DATA <31:00>

MAINTENANCE DATA

2001C018

NOTES:
1.

ADDRESSES SHOWN ARE FOR A CI780 AT TR14.
TK-8538

263

Ci1780 REGISTERS (CONT)

3130292827262524232221201918171615141312 11100908 0706 050403020100

Lololelefelelelefefefelelelefefelelelelelefelelol [ [T []]]

PORT STATUS
2001C900

ME lDSE'PDSIRQA
MSE

FUNCTION

MAINTENANCE ERROR

MEMORY SYSTEM ERROR

PIC

MFQE

MAINTENANCE TIMER EXPIRATION

DATA STRUCTURE ERROR

PORT INITIALIZATION COMPLETE

02
01

PORT DISABLE COMPLETE
MESSAGE FREE QUEUE EMPTY

RESPONSE QUEUE AVAILABLE

3130292827262524 232221201918 1716 151413 12 11 1009 0807 06 050403020100
TT T T T T T T T T T T T T 1T 1T 7171

[OTOT

PORT QUEUE BLOCK
BASE <29:09>

IOIOIOI"IO[O‘O]OIOI

PORT QUEUE BLOCK BASE
2001C904

3130 29282726252423222120191817
161514 1312 111009 08 0706 050403 020100
L
rrrryv1r
1
rertry T T 1Ty T T T 1T d
FAILING ADDRESS <31:00>

PORT FAILING ADDRESS
2001C938

31302928272625242322212019
1817161561413 12 111009 0807 06 050403020100
T

rrrrryrrrrrrerrrTrrd
|

PORT ERROR STATUS

ERROR CODE <31:00>

2001C93C

3130292827262524232221201918171615 141312 11 10090807060504
03 020100

||IllHIHHHHl°l°l°l°l°l°l°I°IHHIII|
L12‘L10|L08)L06’L04|L02|L00
T

SIZE

LO7

LO5

LO3

PN07—!

LO1

PORT PARAMETER
2001C940

L—PNOO

PNOB

PNO1

PNO5

PNO2

28:16

INTERNAL BUFFER LENGTH

PNO3

07:00

PORT NUMBER

LO9

FUNCTION

BIT

L11

CLUSTER SIZE

PNO4

3130292827262524232221201918 171615141312 111009 080706 050403 02 0100

elelelelololelelelolelofelololelolelelololefefefefofole]lol]|
2001C908
2001C90C

PORT COMMAND QUEUE 0 CONTROL
PORT COMMAND QUEUE 1 CONTROL

2001C910
2001C914
2001C918
2001C91C
2001C920

PORT COMMAND QUEUE 2 CONTROL
PORT COMMAND QUEUE 3 CONTROL
PORT STATUS RELEASE CONTROL
PORT ENABLE CONTROL
PORT DISABLE CONTROL

2001C924

PORT INITIALIZE CONTROL

2001C928

PORT DATAGRAM FREE QUEUE CONTROL

2001C92C

PORT MESSAGE FREE QUEUE CONTROL

2001C930

PORT MAINTENANCE TIMER CONTROL

2001C934

ONE BIT REGISTERS

CNTL
BIT

PORT MAINTENANCE TIMER EXPIRATION CONTROL
TK-B539

264

30 (QTY 20)
SEE NOTE 3

SEE DETAIL
D

2 REF

TEE

+ |+

+ {4

SEE NOTE 1

00T TIMER

SEE NOTE 2

TIME

SECONDS

RLEVEL

0 = JUMPER OUT
1=JUMPER IN

LEVEL
4

{?
0= JUMPER IN

INTERRUPT PRIORIT
LEVEL

JUMPER OQUT

1 = JUMPER IN

t = JUMPER QUT

THE SELECTED TR LEVEL MUST MATCH
THE LEVEL CHOSEN BY THE Ci780 TR

ARBITRATION JUMPER,

C1780 JUMPERS

57
E

TOCO1-53

(BUS
TR L.
1

C1780 BACKPLANE JUMPERS

SIGNA

LT JUMPER (W1}
IN = 2048 SBi CYCLE BEFORE CXTMO.

OUT
=512 SBI CYCLE BEFORE CXTMO.
PANIC MODE JUMPER (W8)

IN
= PANIC MODE DISABLED
QUT = PANIC MODE ENABLED
W11 IS RESERVED
H
=]

)

pi(e)[e][e]e}[e)

G9¢

J17
w1

[e]'e

AEDel

[w}
o] P~

C1780 TR ARBITRATION

BOOT JMP

BOOT JMPR 2 H
/14|

[WT5 | EXTEND HDR/T TRLR

NOTES
@JZO

THE SELECTED TR LEVEL MUST

6
EXISTING

HARNESS

MATCH THE TR LEVEL SELECTED

J21
RA
J15

BY W2, W3, w4,

DISABLE ARB

ALTDELTATIM

Exrm
Al

2080 JMPR 805 05/B05-06

TROIS RESERVEDAS THE HOLD

THE STANDARD CONFIGURATION
IS TR 14 {W2, W3, W4 IN} AND ALL
OTHER JUMPERS OUT.

J14

D|SABLE ARBITRATION (W14)
0 ARBITRATION ON CI BEFORE TRANSMISSION
NORMAL CI ARBITRATION

EXTEND HEADER/TRAILER (W15)

IN = EXTENDS HEADER/TRAILER

QUT
= NORMAL HEADER/TRAILER
(tF W15 1S IN, W17 MUST ALSO BE IN)
ALTER DELTA TIME (W16}
IN = LONG DELTA TIME

=SHORT DELTA TIME
N = LONG TIME OUT
OUT = SHORT TIME OUT

BACKPLANE
MATE-N-LOK CONNECTIONS

SIGNAL NAME

TGO P/SJ3
TR

ofic

BACKPLANE | = || =
CONNECTOR

SCALE:

[Z
o

[|& (| » | 2
|lo
o | Z

LIRS

NONE

J15

NCINC

NC | 3

J13

J16

NC|

NC | 1+2]

{3
3+4

NOTES

1.
2.
3.

CONN J1.J6 ARE SBI BUS OUT CONN.
CONN J7-J12 ARE SBI BUS IN CONN.
EXTRA JUMPERS, ITEM 30, TO BE
SHIPPED IN ITEM 42, PLASTIC BAG.

NC = NO CONNECTION
Tk8549

SH3adWNr INV1dX0VE 081D

DETAIL D
SCALE: NOI

DATA PATH (I0P.0i02)

L 14Vd ‘WYHOVIA X2018 081D

SBI INTERFACE (IS :LOIO4)

PARITY
GEN/

VAN

TRANSMIT
BUFFER

CHK

liifiliilll
GEN/CHK

(BUS1B)

PACKET
suFFer

[|J )

33;‘;50
P

RECEIVE

BUFFER

PACKET

2901

BUFFER

{

BUS

DATA

(LN ReG

&_f

DECODE
& CONTROL

(BUS MO)

=] H

s8i

99¢

(DATA)

{ADRS)

PORT

CNTL

ADDRESS
SOURCES

XBUS XI ATE INDEX_LIT

{IB IN)

CLOCKS }

DATA
4

+5V

ey
BOOT

)

JUMPERSE

(LITERAL)

CLOCKS

PATH

CNTL

ENABLES

—
.

BRANCH

conoiTions}

—

NOTES: /~ INDICATES A TRISTATE OUTPUT
K54t

TRANSMIT

ggg"‘”

TRANSMIT
BUFFERS

REG

LOOPBACK
R

£G

CONTROL|
|
RECEIVER

mux | 8i
[+~
-

RECEIVE

(

LINK

|
of

2ggpu7

[*1

RECEIVE

surFers

RECEIVE

CMD

DISABLE

STATUS

DECODE

MUX

[

C?’E

ICROWOR

CHKR

MANCHESTER

DECODER

Mux

DETECTION

LINK

CNTL

TRANSMIT

NODE

STATUS

ADRS

Jers

PARITY

EGISTER

]

IRNEPGUT

]

L‘l

RECEIVE

LINK

ENABLE/

CONTROL
(PORT DATA)

L9¢

7”

}C.A

ENCODER

8,
.

LINK (ILI:LOIOO)

TRANSMITTER
MANCHESTER

INPUT

CONTROL

STORE

SYNC

+5V

CSA

DISPLAY

N
<

<3:0>

4,
7

12{<11:00>
[ MADRj
(NUA)

[ssousncsn]

NOTES:

.~~~ INDICATES A TRISTATE QUTPUT
TK-8542

Z 14Vvd ‘WvHDVIa 320718 081D

8
TRANSMIT

PACKET BUFFERS (IPB:LOIOI)

CHAPTER 8

PROCESSOR-SPECIFIC
DIAGNOSTICS

MICRODIAGNOSTIC MONITOR COMMANDS

Description

Command/FPlag

DIAGNOSE

Initializes

the

program

control

and

starts

microdiagnostic

test

number

one.

valid

qualifiers

/TEST:

flags,

execution

are:

number

specified

prior

tests)

Dispatch

and

not

(do

loop

the

test

execute

any

the

test

indefinitely.

/SECTION:
section
any

number

prior

Dispatch

specified

sections)

section

indefinitely.

/PASS:

diagnostics

the

returning

number

~1,

execute

the

micro-

number
the

the

execute
on

the

specified

before

the

not

loop

Execute

passes

diagnostics

(do

and

console.

the

micro-

indefinitely.

/CONTINUE -- This switch

used with the

/TEST

automatically

/SECT

switch

continue

after

the

section has

271

been

specified

reached.

test

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

/TEST:

<N>

execute

<M>

Dispatch

tests

<N>

and

returnn

/SECT:

<M>

<N>

execute

(inclusive),

command

Dispatch

sections

and

test

<N>,

through

(inclusive),

<N>,

mode.

section

<N>

return

command

mode.

NOTE

the

"/TEST"
value
to

<M>.

will

above

variations

and

“/SECTION"

<N>

must

<M>

start

<N>

the

qualifiers,

the

less

than

and

<N>,

continue

equal

testing

the

end.

NOTE

/TEST

and

/SECT

cannot

specified

simultaneously.

Examples:

DIAG/TEST:2F
Dispatch

test

number

and

execute

indefinitely.

DIAG/SECT:B

Dispatch

section

number

and

execute

indefinitely.

DIAG /PASS: -1

Execute

all

indefinitely.

272

the

micro

diagnostics

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

DIAG/TEST:2F /CONT

Dispatch

the

Continues

CONTINUE

test

without

and

start

execution

tests.

remaining

microdiagnostic

changing

the

execution

program

control

flags.

Set

and

Clear

SET/CLEAR

FLAG

Flags

Sets

(or

clears)

Detection

SET/CLEAR

FLAG

Sets

(or

clears)

Isolation

SET/CLEAR

FLAG

SET/CLEAR FLAG

LOOP

Sets

NER

Sets

(or

the

Halt

Error

the

Halt

Error

flag.

clears)

(or

the

clears)

Loop on

the

Error

flag.

Report

flag.

SET/CLEAR

FLAG

SET/CLEAR FLAG

CLEAR

FLAG

BELL

Sets

(or

clears)

the

Bell

ERABT

Sets

(or

clears)

the

Error

Clears

the

Loop

(Note

that

this

flag

Clears
(Note

the
that

273

Loop
this

Special

flag

Error

Abort

flag.

Section

cannot be

set.)

Special

Test

cannot

set.)

flag.

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

SET/CLEAR

FLAG

ALL

Sets

(or

<clears)

all

the

flags.

SET/CLEAR

SOMM

Sets

(or

clears)

the

Stop

Micro

Match

bit.

SET/CLEAR

SOMM: <ADDRESS>

Loads

address

and

SET/CLEAR

FP:<ADDRESS>

into

sets

(or

Micromatch

bit.

Loads

Micromatch

clears)

into

the

stop

FPA

micro

sync

SET

STEP

STATE

Sets

the

CPU clock

single

time

SET

STEP

BUS

Sets

the

CPU

clock

single

bus

cycle.

Both

the

SET

STEP

STATE

SET

STEP

commands

mode.

cause

Step

state

terminal
clock

the

monitor

types

UPC

input.

value

the

mode

1is

typed
is

the

out.

step

clock

waits

for

typed,

the

current

UPC

the

entered,

BUS

and

space

and

enter

current

value,

triggered

character

and

state.

any

step

other

mode

|is

Instruction

flag

exited.

SET

STEP

INSTRUCTION

Sets

the

hardware

and

returns

hardcore

tests

value

the

274

Single

the
are

Test

monitor.
invoked,

(TPC)

When
the

the

current

typed.

The

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

monitor

waits

space

SET CLOCK

FAST

terminal

typed,

instruction
value

for

the

executed

TPC

input.

1If

current

pseudo

and

current

the

typed.

any other

character

Sets

CPU

clock

speed

the

fast

CPU

clock

speed

the

slow

the

typed,

step mode

exited.

margin,

SET

CLOCK SLOW

Sets

the

margin.

SET

CLOCK

SET CLOCK

NORMAL

Sets

EXTERNAL

Sets

the

CPU

the

clock

CPU

speed

clock

normal.

for

external

oscillator.

Examine

Commands

The

following

current
before
the

examine

commands

microinstruction
the

examine

first

examine

since

command

mode.

examines

execute

microinstructions.
T1-T8

are

destroyed

except

for

the

following

Bus,

advance

executing

275

the

Bus

and

command.

entering

is
the

successive

any

additional

Bus

registers

the

examines,

VBus

examines.

examines,

clock

the

executed

All

during

All

cause

performed,

monitor

not

except

CPTO0

before

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

EXAMINE

ID:<ADDRESS>

VBUS:<CHANNEL>

Displays

the

specified

Displays
channel

contents

the

BUS

<ADDRESS>.

contents

specified

the

VBUS

<CHANNEL>.

Bit

the

right

side

the

contents

the

display.

EXAMINE

RA:<ADDRESS>

Displays
Scratch

EXAMINE

RC:<ADDRESS>

Displays
Scratch

EXAMINE

SBI:<ADDRESS>

Pad

specified

the

Pad

Displays

contents

specified

the

<ADDRESS>.

the

<ADDRESS>.

the

contents

the

SBI

the

contents

the

contents

the

contents

address.

EXAMINE

Displays
Latch

EXAMINE

Displays
Latch.

EXAMINE

Displays
Register.

when

Displays
Register.

276

not

examining

EXAMINE

(Do

use

the

address

wuse

command.)

the

contents

the

MICRODIAGNOSTIC MONITOR COMMANDS (CONT)

EXAMINE

Displays

the

contents

the

contents

the

contents

the

EXAMINE

Displays

EXAMINE

Displays

EXAMINE

Registers

Program

Deposit

Command

1ID:

RA:

<DATA>

DEPOSIT

RC:

<DATA>

DEPOSIT

LA:

<DATA>

DEPOSIT

LC:

<DATA>

DEPOSIT

DR:

<DATA>

DEPOSIT

QR:

<DATA>

DEPOSIT

SC:

<DATA>

DEPOSIT

FE:

<DATA>

DEPOSIT

VA:

<DATA>

DEPOSIT

PA:

<DATA>

DEPOSIT
REPEAT

SBI:

the

Counter.

command

the

same

the

examine

command,

except

that

the

data

must

<DATA>

<COMMAND

deposit

<DATA>

DEPOSIT

<contents

The

supplied

DEPOSIT

the

STRING>

277

the

deposited

user.

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS

BLKMIC

Move

<SCR ADDRESS>,

[SCR INDEX], <WCS ADDRESS>,

<WORD COUNT>,

[<WCS ADDRESS INDEX>]

number

the

from

the

<SCR

starting

<WCS

96-bit microwords
to

INDEX>,

WCS

the

ADDRESS>,

indexed

<SCR

ADDRESS>,

indexed

<WCS5 ADDRESS INDEX>.

specified,

the <SCR ADDRESS> is indexed by six PDP-11 words (i.e.,

bits).

the

ADDRESS>

Otherwise,

INDEX> *

pointer

is used as a

the

example,

For

used

with

starts

ADDRESS>

<WCS

If an <SCR INDEX>

alpha

physical WCS address.

current value of

index

the

would be added to the <SCR ADDRESS>

96-bit microword

load

memory.

LSI-11

the

table

<WCS

the

character,

into

14g

(<SCR

find the

first

is
to

the WCS.

CHKPNT

the

{[<PASS ADDRESS>},

error

flag,

set

instructions),

zero,

during

zero,

the

<FAIL

<PASS

fail

address

is specified,

The

address

instruction

on the

the

typed

COMPARE

flag

appear

not

[<FAIL ADDRESS>]

instruction
ADDRESS>.

ADDRESS>.

to the next

line named TRACE:.

278

1If

neither

instruction

typed.

(see

These

CMPXXX

the

error

pass

line.

addresses

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

CLOCK

<TIMES>

CLOCK

Step

the

system clock

<TIMES>

1is

evenly

executed

for

each

<TIMES>

number

divisible

four

single

time

states.

four,

single

bus

cycles

are

<TIMES>.

CMPCA

[<MODE>],

<REGISTER>,

<DST ADDRESS>,

(<DST ADDRESS

INDEX>]

Compares

the

contents

with

the

ADDRESS>,

indexed

the

<MODE>

not

in the most

READID

specified

the

is specified as IDREGLO or IDREGHI,

the

INDEX>.

false,

location

specified

<DST

the

in the compare

recent

console

specified,

If the <REGISTER> argument
register used

the

<DST ADDRESS

argument

contents

set

the

error

it defaults

the

ID Bus

instruction.

279

flag.

EQUAL.

that was

read

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

CMPCAD

[<MODE>],

<REGISTER>,

<DST

ADDRESS>,

[<DST

ADDRESS

INDEX>]

Compare

the

contents

and

<REGISTER>+2

specified

<DST

ADDRESS

INDEX>.

<MODE>

the

argument

the

used

most

the

not

recent

and

the

<DST

false,

specified,

argument
the

console

with

ADDRESS>

argument

<MODE>

the

compare

READID

registers

contents

ADJRESS>+2,

set

the

<DST

flag.

the

EQUAL.

specified

IDREGLO or

Bus

the

registers

indexed

error

defaults

specified

the

IDREGHI,
that

was

the
read

instruction.

CMPCAM

[<MODE>],

INDEX>],

Take

the

mask

contents

with

the

<REGISTER>,

<DST

the

INDEX>,

indexed

by <DST ADDRESS

<MODE>

the

<MODE>

argument

console

contents

ADDRESS

and

compare

not

the

ADDRESS>,

[<DST

<MASK

[<MASK

ADDRESS

INDEX>}

specified

ADDRESS>,

with

the

contents

false,

set

the

ADDRESS

<REGISTER>,

indexed
of

<DST

<MASK

ADDRESS>,

INDEX>.

argument
is

<MASK

ADDRESS>,

specified,

280

defaults

error
to

flagqg.

EQUAL.

the

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

the

the

The

used

most

mask

argument

the

recent

compare

READIN

performed

indexed

<MASK

clearing

the

contents

specified

IDREGLO

Bus

the

IDREGHI,

that

was

the

read

instruction.

taking

ADDRESS
of

the

INDEX>,

contents

<MASK

complimenting
with

ADDRESS>,

it,

and

bit

it.

cMpCMD

CMPCMD

[<MODE>},
INDEX>),

Take
and

the

contents

<REGISTER>+2,

<MASK

with

ADDRESS>+2,

the

contents

<DST ADDRESS

<REGISTER>,
<DST

the

mask

<MASK

ADDRESS>,

console

with

ADDRESS

registers

the

indexed

ADDRESS>

<DST

ADDRESS>,

([<DST

specified

contents

<MASK

[<MASK

ADDRESS

INDEX>]

<MASK

ADDRESS>

and

ADDRESS

INDEX>,

and

compare

and

ADDRESS>+2,

indexed

<DST

INDEX>.

the

If the <REGISTER> argument is specified as IDREGLO or IDREGHI,

the

read

the

argument

<MODE>

<MODE> argument

the most

false,

is not specified,

in the compare

recent

READIN

set

error

the

it defaults

is the ID Bus

instruction.

The mask is performed by taking the contents of
<MASK

it,

ADDRESS>+2,

indexed

flag.

to EQUAL.

<MASK

ADDRESS

<MASK ADDRESS> and

INDEX>,

complementing

and bit clearing the contents of <REGISTER> and <REGISTER>+2.

281

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

CMPPCSV

CMPPCSV <DST ADDRESS>,

[<DST ADDRESS INDEX>]

Compare the contents of the PC Save register with the contents of
the

location specified by <DST ADDRESS>,

indexed by <DST ADDRESS

If the contents are not equal, set the error flag.

INDEX>.

ENDLOOP

<INDEX

ENDLOOP

Add the

NAME>

(see LOOP

increment value of <INDEX NAME>

instruction)

the

value

current

instruction).
last

value,

instruction.

with
the

current

the

value

last

the

value

(specified

less

following

instruction

than or
the most

Compare

the current value of the index specified by <INDEX NAME>.

the

equal

LOOP

to the

recent LOOP

Otherwise, go to the next sequential instruction.

ERRLOOP

Save

the

address

the

instruction.

detected, and the Loop or Error flag is set
execution

instruction

restarted

this

saved

executed.

282

error

(ref. subsection 4.6),

address

after

the

IFERROR

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

FETCH

<WCS

the

<WCS

ADDRESS>,

ADDRESS>

[<WCS ADDRESS

numeric

1location

specified

ADDRESS

INDEX>.

execute

contents

NOP>

specified,

<WCS

maintenance
<WCS

maintenance

string,
by

return

ADDRESS>,

bit

<WCS

ROM NOP>]}

indexed

specified

ADDRESS

MCR

return

alpha-numeric

location

the

[<WCS

maintenance

ADDRESS>,
is

the

indexed

clear

execute

<WCS

ADDRESS>

INDEX>},

INDEX>.

<WCS

string,
by

the

<ROM

during

the

one

the

return.

FLTONE

Generate
bit

<DST

32-bit

postion

NAME>,

and

ADDRESS>

ADDRESS>,

and

<INDEX

NAME>

word

all

zeros.

Insert

specified

the

current

value

load

word

this

<DST

into

the

logic

minus

location

one

specified

<INDEX
by

<DST

ADDRESS>+2.

FLTZRO

Generate
bit

<DST

32-bit

position

NAME>,

and

ADDRESS>

ADDRESS>,

and

<INDEX

NAME>

word

all

logic

specified

the

current

load

<DST

this

word

into

the

ADDRESS>+2.

283

ones.
value

Insert
minus

location

zero

one

specified

the

<INDEX
by

<DST

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

IFERROR

the

test
to

[<MESSAGE

error

flag

number,

<FAIL

NUMBER>],

[<FAIL

nonzero,

type

subtest

number,

and

ADDRESS>

the

HALTD

zero,

ADDRESS>]

the PC

the

good

flag

this

and

not

instruction,

bad

data.

set

Then,

the
go

(ref.

subsection

specified,

4.6).

the

error
the

flag

the

not

instruction.

INITIALIZE

Set

and

clear

bit,

Machine

the

set

Control

CPU

the
the

1Initialize

single
ROM

NOP

bit

time

state

bit,

and

bit,

set

the

set

Machine

the

Proceed

Control

single

bus

bit

the

minus

one

the

KMXGEN

Generate
of

the

<INDEX

<SRC

ADDRESS>,

<INDEX

address

specified

KMUX
NAME>

microinstruction

and

load

specified

NAME>

the

current

into

<SRC

ADDRESS>.

284

the

KMUX

value
field

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

LDIDREG

Load
of

the

Bus

<SRC

<SRC

locations

indexed

<REGISTER>,

specified

ADDRESS

the

<SCR

microstack,

<SCR

ADDRESS>

bits.

[<SRC

ADDRESS

INDEX>]

with

the

ADDRESS>

and

<SCR

microbreak,

WCS

contents

ADDRESS>+2,

INDEX>.

contents

taken

ADDRESS>,

taken

address,

the

bits.

Otherwise,

ADDRESS

INDEX>]

LOADCA

Load

the

contents
<SRC

<REGISTER>,

console
of

the

ADDRESS

<SRC

ADDRESS>,

location

INDEX>.

specified

This

[<SRC

instruction

with

the

ADDRESS>,

indexed

data.

<SRC
loads

bits

Looe

LOOP

<INDEX

Initialize
value

the

loop

specified

the

ENDLOOP

for

the

NAME>,

<START>,

parameter

<START>.

instruction.

Save

instruction

the
to

increment

less

with

than

value

[<SIZE

specified
the

Calculate

ENDLOOP

<START>

<END>,

the

or
+1;

-1.

285

value
and

<INDEX

NAME>

specified

save

following

equal

DEPENDENT>)

the

<END>

for

increment

algorithm:

<END>,

otherwise,

set

set
it

value

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

<END>

name

I1f

the

<INDEX NAME>,

<END>

value

<END>

two

save

this

the

is specified,

there

current

index

divide the

only

value

that

index

name.

one

WCS

larger of

module

<START>

the

and

system.

them unchanged.

leave

Otherwise,

MASK

<DST

ADDRESS>,

Take

the

contents

bit

clear

<MASK

location

the contents of

ADDRESS>

<MASK

location

ADDRESS>,

complement

<DST ADDRESS> with

it,

and

it.

MOVE

Move

the

INDEX>)

,SRC

ADDRESS.,

contents
to

the

[<SRC

<SRC

location

ADDRESS

specified

INDEX.[,

<DST

INDEX>

(indexed

ADDRESS>.

<DST

ADDRESS>

<SRC

ADDRESS

NEWTST

<TEST NAME>,

[<TEST DESCRIPTION>],

DESCRIPTION>],

[<ERROR

[<LOGIC

DESCRIPTION>},

[<SYNC

POINT

DESCRIPTION>]

This

instruction

arguments.

instruction

for

creates

clears

the

looping

test
error

header
flag,

test.

286

document

and

saves

for
the

the
PC

specified
the

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

READIN

READID

Reads

the

contents

Bus

into

specified

locations

IDREGLO

and

IDREGHI.

and

loads

the

RESET

Executes

<LSI-11

reset

instruction>.

REPORT

<MODULE

Types

out

NAME

STRING>.

the

NAME

module

Microdiagnostic

STRING>

numbers
the

the

HALTI

modules

flag

specified
set,

<MODULE

return

the

<SRC

with

the

Monitor.

TSTVB

Load

and

<SRC

read

the

TABLE

ADDRESS>,

data

Bus

TABLE

just

ADDRESS>,

VBus.
indexed

read.

[<SRC

TABLE

Compare

the

TABLE

The

<SRC

{SRC

contents

TABLE>

287

ADDRESS

has

the

INDEX>]}

the

data

INDEX>,

following

format:

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

1$:

.WORD

<NUMBER

VBUSG

<CHANNEL

BITS

TO CHECK>

NUMBER>,

<BIT

NUMBER>,

<EXPECTED

BIT

<EXPECTED

BIT

VALUE>

2%:

.WORD

<NUMBER

VBUSG

<CHANNEL

BITS

NUMBER>,

CHECK>
<BIT

NUMBER>,

VALUE>

The

following

TSTVB
If

<SRC

example

the

<SRC

TABLE

ADDRESS

INDEX>:

15,1

the

and

current

the

<SRC

TABLE

value

the

<SRC

TABLE>

looks

ADDRESS>

would

TABLE

the

ADDRESS

above

table,

INDEX>
the

physical

2$.

SETPSW

Load

the

<DATA>

LSI

processor

status

word

with

the

value

specified

<DATA>.

SETVEC

Set

the

expected

<VECTOR

LSI-11

trap

ADDRESS>

address

specified

routine.

288

<VECTOR

ADDRESS>

the

MICRODIAGNOSTIC PSEUDO-INSTRUCTION DEFINITIONS (CONT)

SKIP

the
S,

SKIP

[<DST ADDRESS>]

the

<DST ADDRESS>.

next
go

test.

the

1If

<DST

ADDRESS>

starts

not

specified,

with

the

alpha

character

subtest.

SUBTEST

Increment

the

subtest

counter.

TYPSIZE

Use

the

contents

location

configuration

and

that

tested.

the

will
test

stream

type

BADDATA

message

any

aborted

and

and
the

the

Set:

WCS

module

bits

3-0

are

nonzero

5th

WCS

count

not

zero

present

289

determine

the

number

following

NER

(No

the

WCS

conditions

Error

Report)

module

modules
exist,
flag

ARRANGED

ALPHABETICALLY

ACCELERATCR

SNOILINI4Z3Q d131d WOYH TOYLNOD J1LSONOVIAOHIINW

;FIELDS

ACF/=0,2,70,D

CONTROL

wN32=0

SYNC=1
TRAP=2

CONTROL=3
ACM/=0,3,55
PWR.UP=0

ABCRT=1

(ACCELLERATCR-DEFENDENT CONTROL FUNCTIGN

{ACCELERATCR MISCELLANEQUS CCNTROL
:RETURN ACCEL TO MONITIRING IRD

PCLY.DONE=6

;ADDRESS

SILECT

06¢C

;ALU CONTROL

FUNCTICNS

;INSTRUCTION

CEPENDENT

A+B=05

A+B8.RLCG=0¢
ORNJT=07
XCR=08

ANDNGT=03
NOTA=C

A+C+PSL.C=CB
OR=0C
AND=0D
£=0E
A=0F

ANX/=0,2,80

JAMX

ALY

LA=0
= 1
2ANX

(AWK
X

RAMX.SXT=2
BAMX.CX7=3

SIGN

ZERQ

EXTENDED ACCORDING 10
EXTENDED.

OXT(L)=0

;BRANCH

ENABLE

NOP=0

BRANCH

sLAKI>,

C3tx3

ACCEL=6

DATA.TYPE=S

END.CP1=8

ALU

ALy

PSLKC>,

LALKO>

31,

1CODE

FRCM

ACCELERATOR

(VA

WCDE)

ASRC+VIRC,

ASRC+Q-C

G==NGRMAL,

1--QUAD

COUBLE

@==FlELD,

3-~ADDRESS

(=11

=+,

MODE)

»,

IR2-1=9

siVAX

MCDE)

IR<2:1>

PC.MODES=9

=11

MODE)

CLASS,

CLASS+([127

SMIT7+SNS7+DM4T7+DMIT,

REI=0A

sUVAX

MUDE)

SRC.PC=CA

MODE.LSS.ASTLVL,

; (=11

M2DE)

SKRC

IB.TEST=08

C=~T5

2--STALL,

MUL=0C

SIGNS=00
INTERRUPT=0E

16¢

sNO

=1
ROR=2

DECIMAL=JF
UTRAP=10

;3<31>,

1--ZRROR
3--DATA CK

D<1:C>

D.NE.O,

L0,

‘MICROTRAP

;=FPO,

EALU="

tEALU

INTERRUPT,

DISPATCH

NESTED

INT

0--READ

2--ARITE,
N,

INTERLOCK,
3--READ,

EALU

SC=14

;SCLe:IB8>.NELO,
(RLCG
v

EMPTY,

(ALU

BITS

STATE7-4 1 6
STATE2-C i 7
D.BYTES= 1 8

1STA1E

310>

3YTES

D3-2=19

1 D<5:13>

VSTATE

N.Z,V,C

TwD

SC.GT.O0,

FROM

SIGN

BITS:

1--READ,
WRITE

READ

CHK

SC.NEG.O,

SC<CS:5>.NELO

ALUKtI:0>=0,

PSL

ALU

TALU

PSL.MODE=1C
TB.TEST=1D

i=VA<31:30>,

yPTE

LCW

£Q

ALU<KI>,

PREVICUS

ALUSD>

STATE)

<7:4>

ALU=18

VECTOR

ERROR,

ALU1=-0=15

PSL.CC=1A

D<31>

INTERNAL

LAST.REF=1

CST

NISS,

;SC.NE.C.
JAC

R=PC

VALID,

D.NE.O

IR<0>,

ALU

-CONSOLE,

ALIGNED,

C=—TRANSLATION

2--ACCESS

OK,

C3t%

IS+CM,

KEARNEL

QUAD,

1--WR

CHX

VICLATION,

3--TB

AND

MiSs

M=0

R=PC

(LNOJ) SNOILINIZ3A d7314 WOYH TOHLNOD J1LSONOVIAOHIIN

BEN/=0,5,72,D

;BMX

ALU

YASK=0

{LE

UNLESS

PACKED.FL=2

{PACKED

SELECTED BY

BIT

THE

PC.OR.LB=1

R=PC,

THEN

$C<4:0>

FLOATING

LB=3

LC=4

PC=5
KMX=6

NOP=0

Y0P
C

;CONDITION CCODES
)y nin U
LOwwu
~mmawe () TM

RBMX=7

CCK/=0,3,20,0

R
ET
.

{

ALU & EALU CONDITICNS
v, N0 EFFECT CN N, Z, C
IF ALULNELD '
FROM AX{iDT)

No&

Z
AND

N
RS

PRI ALU, C FROM
Z FROM ALULDT]

AMX

UNAFFECTED

INGT.CEP=7

®
N

c10/=0,4,42
=

" noP=1

ACK=5S

CONT=7
READ.SC=2
READ.:4iX=0B

WRITE.SC=0D

WRITE.HKMX=0F

DK/=0,4,88,D
NOP=0

LEFT2=1
RIGHT2=2
DIv=4
LEFT=5
RIGHT=6
SHF=8

SHF.FL=9
ACCEL=0A
BYTE.SWAP=08

;CONSOLE

IF FS/1
ALLCy AUT

CONTHOL
JOEFAULT,

EU S

1 B

READ

JSET CONGOLE ACKNDOWLEG E
JCLELAR CONSOLE WUDE

FLAG

;READ
(READ

JWRITE
;WRITE

ID BUS REG SELECTED BY SC
[D BUS REG SELECTED BY UKM~
REG
REG

SELECTED
SELECTED

EBY
BY

SC
LUKMX

:DOUSLE SHIFT RIGHT
:IF NCT ALU CRY, SHIFT
ELSE LOAD FROM SHF

LEFT

DEFAULT, HOLD
;ONUBLE SHIFT LEFT

ySHIFT

{SHIFT

LEFT

RIGHT

s LOAD SHF MUX,

;LOAS SiHF MUX,

:LCAC

INTEGER

ACCELERATCR DATA

REFLECT

BYTES

FORMAT

UNPACKED FLOATING FORMAT

ARCUND

FROM DF BUS

BIT

(LNOD) SNOILINIZ3A 1314 WOYH TOH1LNOD J1LSONOVIAQOHIIN

BMX/=0,3,82

;LOAD
;LOAD
;LOAD

DAL.SC=0D
DAL.SV=0E
CLR=0OF

DT/=0,2,78,D

O THRU DAL
DAL[SC]
DAL[SHF VAL]

;LOAD ZEROS
;DATA

TYPE

;CONTROLS

AMX

;CONDITION

SIGN/ZERO

CCODE

LONG=0

EXTENDER,

SETTING,

AND

SHF

MEMORY

AMOUNT,

REFERENCES

yOEFAULT

WORD=1

BYTE=2

INST .DEP=3

tINSTRUCTION

DEPENDENT

;ANY

OF ABOVE,
sEXFONENT ALU

EALU/=0,3,13

=--

QUAD/DOUBLE

A=0

OR=1
ANDNOT=2

B=3
A+B=4

€6¢

A-B=S
A+1=z86
NABS.A~-B=7

EBMX/=0,2,18

;—-ABS (A-B)
sEBMX

EALU

FE=0

tDEFAULT

KMX
= 1

AMX
. EXP=2

SHF.VAL=3

FEK/=0,1,24,D

ySHIFT

sFE

VALUE

CONTROL

NOP=0

sDEFAULT,

HOLD

LOAD=1

FS/=0,1,42

yFUNCTION

SELECT

FCR

43-46

MCT=0

ENABLE

MEMCRY

CONTROL

CID=1

JENALLE

AND

IEK/=0,2,30

VINTERRUPT

ANDC

EXCEPTION

BUS

CONSOLE

ACKNOWLEDGE

NOP=0

ISTR=1

;STRCBE

TIACK=2

PINTERRUPT

ACKNOWLEDGE

EACK=3

:EXCEFPTION

ACKNOWLELGE

INTERRUFT

REQUESTS

CONTROL

(LNOD) SNOILINIZ3A a1314 WOH TOYLNOD J1LSONOVIAOHIIW

Q=0C

s IBUF CONTROL FUNCTICHD

NQP=0

VDEFAULT

STOP=1
FLUSH=2

;FLUSKF

START=3
CLR.C.1=4
CLR.2.3=5

!B AND

ISTREAM DATA)

;CLEAR BYTE 1 (VAX SPECIFIER)
:CLEAR BYTES 0-3 (=~11 OP & DATA)
sCLEAR BYTES 1-5 CONDITIONALLY
1F THERE IS NO SPECIFIER EVALUATION,
IF A SELF-CONTAINED
CLEAR NOTHING.
IF IMMEDIATE,
SOECIFIER, CLEAR IT.
ASSOLUTE,

;1D BUS ADDRESS
:RD

;RD+WR

OR DISPLACEMENT,

CLEAR ThE

LITERAL.

ISTREAM

OPCCDE)

:TRANSFER BRANCH DISPLACEMENT
:CLEAR BYTE O (VAX OPCODE)

CLR.0~-3=0E
CLR.1-5.COND=0OF

I18UF=0
DAY.TIVE=1

1BA

(-11

:CLEAR 8YTES 2,3 (=11

BDEST=7
CLR.0=0C
CLR.1=0D

1D.ADDR/=20,6,58

LOAD

:CLEXK ZYTES C¢,1

:SFECIFIER/LITERAL DATA FROM IB
TIME OF

sCURRENT

;

DAY...

MUST READ UNTIL STOPS CHANGING

;SYSTEM

IDENTIFICATICN

RXDB=5

+RD

;CONSILE

RECIEVE DATA BUFFER

TXCS=6
TXDB=7

;s RO+WR

{CCONSCLE TRANSMIT CONTROL/STATUS
1CONSOLE TRANSMIT DATA BUFFER

SYS.10=3
RXCS=4

DQ=8
NXT.PER=9
CLK.CS=0A

INTERVAL=0B
CES=0C
VECTOR=0D
SIR=0E
PSL=0F
TBUF=10

TBERO=12
TBER1=13
ACC.C=13

:RD

tRD+WR

s WR

1CONSCLE
i

(TO-1D

tRC+WR
;s RD

;s RD+WR
:RD+WR

sRC+4R
;s RD+WR

(FROM-1D

:DATA
T WR

RECIEVE CONTROL/STATUS

PATH D/Q REGISTERS

(MAINT ONLY)

INTERVAL CLOCK NEXT PERIOD REGISTER

INTERVAL CLOCK CONTROL/STATUS
;CLRRENT INTERVAL COUNT
;CFU ERPOR/STATUS

{EXCEPTION &
;SOFTWARE

INTERRUPT CONTROL

INTERRUPT REGISTER

;BRCCESSOR STATUS LONGWORD
s TRANSLATION BUFFER DATA
:TB ERRCR/STATUS O
:TB ERROR/STATUS 1

;ACCELERATOR

(LNOD) SNOILINIZ3Q 1314 WOY TOHLNOD J11LSONOVIAOHIIW

18¢/=0,4,92,0

ACCELERATOR

RECISTER

\4L£RATDQ

ACC.CS=17

RECISTER

CELERATOR

CONTRIL,STATUS

SILt0=18

SBI.ERR=19

ITEM

HSICH

FAULT=18B
MAINT=1D

PARITY=1E

IVEQUT
5110

;SB1I

MAINTENANCE

JCACHE

FARITY

UBREAK=21

TMICRD

ZREAK

WCS.ACDR=22

1SP=2C
FPCA=2D

FWELTING

WCS

“RE

COUNTS

RAM

ADDRESS

LCOCATIONS

x:N
OO

24~3F

€

;-‘"

EGISTER
NEL

uf"

SSP=2A
USP=28

P Wk

ADDRESSES

flr‘)’-u\(

K5P=28

ESP=29

CONTINUED.

s«"([}."l)’U)UT)

PCBR=24
P1BR=23

SBR=26

56¢

COVPARATOR

MICTCSTACK

ADDRESSES

HISTORY

ADDRESS

;S8

USTACK=20

WCS.CATA=23

BUS

SBI

:FAULT,STATUS

CComMp=1C

;1D

FRGOIA

t~\-R

TIME.ADDR=1A

S Auh

STACK

LnJ’SOQ

ISLR

STACK

NTERRKUPT

POINTCQ
STACK

POINTER

PQINTER

STACK

POINTER

D.Sv=2E
D.SV=2F
T0=33

T1=31

;GENZIRAL

TEMPS

T2=32

T3=33
T4=34

T5=35
16=3%
T7=37

T8=33
T9=3%
FCBB8=3A

SC8B=38
POLR=3C

;PROCESS

SYSTEN
+PRCCESS

P1LR=3D

{FPROCESS

SLR=3E

;SYSTE'TM®

CONTROL

BLOCK

BASE

LENCTH

LENGTH

(LNOD) SNOILINI43A 1314 WOY TOHLNOD J1LSONOVIAOHIIN

ACC.1=15
ACC.2=16

:SYMBOLS

MICRO

ARE

":i*

FRON

1A3

FROY

FRCM

FRCM FK
;58 FROM FK

;SPECIFIER

SP1.CON=5

CCONSTANT

+SECIFIER 2 CONSTANT (=11 MODE)
; OR 2ERQS (VAX MOQODE)

SP2.CON=6
ZERD=6

96¢

CEFINED

;CONSTANTS QR #

SC=7

WCFD

FROM

;SCL9:0]

.8 — 3F: CONSTANTS (1
;DECIMAL

CYCLE SETUP IF ALU IN ARITH MCCE)

VALULE OF

CONSTANT

;20
1160
;52
: 40
164
;80

(AF,JL,MH)
(AF,JL)
(AF)
(AF)
(AF,JL,MH,TF)
. NH)
(AF

.EF=0F
.80=10

1239
;120

(JL)
(AF,JL,MH,TF)

LFFG0O=13

1=256

.14=8
.A0=9
.34=0A
.28=08
.40=0C
.50=0D

(JL)

.3000=0¢

112288

.8000=11
LFF=12

;-32765
;255

(AF)
(MH, TF)

;30

(AF)

-1E=14

.3F=15

.7F=16

163

1127

(MH,AF,JL)
(MH, AF,TF)

.7=17
.F=18

7
;15

{AF ,MH)
(MH,CM,AF,TF)

LFFES=1A
.FFFO=1B

1-24
1=16

(MH,TF)
(CM,JL,TF,MH)

L3FF=20

;1022

.10=19

_FFFB=1C
.28=1D
.30=1E
.18=1F

$16
i-E
13z
i3
124

(MH, AF,JL,TF)
TF MH)
(CM,
Mk, TF)
(CM,JL,
(CM,AF ,WMH, TF)
(MH,AF,TF)
(CM)

(LNOD) SNOILINI43A @1314 WOYH TOHLNOD JI1LSONOVIAOHIIW

Wononnon

s FOLLOWING

bHWN
- O

BWN
= @©

KMX/=0,6,58
.

DEFAULT IS THE

NEXT MICRO WORD ADDRESS,

J/=0,13,0,+

112
113
;31

(CM,JL,TF
MH)
(TF)
(AF,dJL ,MH,TF)

.1F00=24

17936

(JL,MH)

.B0=25

1176

(MH)

.E003=26

(CM)

.7C=27
.FFEO=28

1124
;=32

(AF)
(Jt)

.60=29

196

(TF)

.DFCF=28

(Ji)

SPARE=2A
.FFEF=2C

=17

.FFF1=20

;=18

(AF)

.19=2E

125

(AF)

i=7

(AF)

.FFFF=30

(MH,JL,TF)

.88=31

1136

(AF)

P 7

(TF)

.FFF9=2F

KMX

DEFINITION

CONTINUED

L6C

.3030=32

.F0=233

1240

(TF)

.C0=34

1192

(TF,MH)

.6=35

(CM,JL,TF)

.9=36
.FFF6=37

19
=10

(CM)
(CM)

.FFF5=38

=11

(CM)

.1A=39

126

.24=3A

(AF)

(CM,AF,TF)

136

(CM,MH)

.1B8=38
.FFFEC=3C

127
1-4

(CM,AF,TF)
(CM,TF,MH)

.A=3D

110

(AF ,MH)

.7E=3E

1126

(AF,TF)

SPALRE=3F

MCT/=02,6,42,D

+MEMORY

CONTROL

TEST.RCHK=00

;TEST

MEM.NOP=02

{NEITHERX

TBUF

WITH

CPU

TSUF

READ

NOR

CHECK
GETS

TEST.WCHK=04

;TEST

WITH

WRITE

WRITE.V.NOCHK=CA

;WRITE,

INHIBIT

TRAPS

WRITE.V.WCHK=CC

(WRITE,

NORMAL

VARIETY

LOCKWRITE.V.XCHK=0E

{INTERLOCK

wRITE,

MEM

CYCLE

CHECK

VIRTUAL

ADDRESS

(LNOJ) SNOILINIZ3A 41314 NOY TOHLNOD JI1LSONDVIAOHIIW

.C=21
.D=22
.1F=23

. D
READ.Y

KEAD.YV.NZAPC=13

ELD.
¢ .NICHA=1A
LOCAR
D.
V. alHA=1C
LOCKRTA

FOR

ZCR

Wil

I.
L+ NJAM=22
SBI.H
INVALIZATE=

IBUFFCK

WOXI1AL VARIETY

READ,

3BI

sBI

JACHE

ACTIVITY

ENTRIE

'CTAGNDSTIC FORCE VALID
NDED WRITE TO CLEAR MOS ERRIRS

Crrave X
=

VALIZATE=:8
EXTWEITZ.P=

£, PHYSICAL
- ILTCK WRITE,

FHYSICAL

FHYSICAL
IALPT

SLMMMARY

R.CCK

READ,

MsC/=0,4,26,C

READ

PHYSICAL

NOP=0

MNEW

CHK.CHW=01
CHX.,FLT.CPR=02
CHK.GZZ.ADDR=03

MCDIFY

CHECK CONTROLLED EVY

NONEW INSTRUCTION STREAM
SO0ES TO INSTRUCTION BUFFEX
TIR.LCK READ, INHIZIT CHECK

S3I1.hC.2:28

LOCKWRITE. P=2E
READ.FP=32
READ.IWT..LTM=36
LOCKREAD.E=3A
ALLOW.IB.READ=3E

NORMAL VARIETY
INHIBIT TRAPS

PSL

FOR

CHI

ALU<IS>=1,

ALUK14:7>=0

IRD=043

:THIS STATE IS INSTRUCTION DECOD:Z

LOAD.ALC.LC=06

i TAKE CONDITION CODES FROM ACCELERATC

SET.FrZ=C2

JSET

SAN

SET.NEST.ERR=08

JSET

SAWVE

LOAD.STATE=015

READ.5c.CGC=C7
CLR.FPC=CE

CLR.NEST.ERR=CA

SECONC . #EF=0C
RETRY.NC.TRAP=0D
RETRY.TRAP=CE
INH.CV.ADDR=0F
FCK/=0,3,32,0
NOP=C

P (AND FZP RLOG STACK)
(CLEMR PSLKFRPDE> BIT

;CLR NESTED ERRGR FLAG IN CPU STATUS
;OF UNIZLIGNED DATA REFERENCE
TAPPLY SAVED CONTEXT, INHIEIT TRA®S
JAPPLY SAVED CCNTEXT TO THIS REF
;A_LOW USE OF FULL 32-BIT ADDRESS

;ADDRESS CCUNT CONTRCOL
JDEFAULT

(LNOD) SNOILINIZIA a1314 WOYH TOHLNOD J1LSONOVIAOHIIN

o a0 00

READ.V.~CHR=10
READ.V.NIIHK=12
~K=14d
N.V.
READ

PC_1BA=2

IVA_VA+L

VA+4=3
PC+1=4
PC+2=5
PC+4=6

EC_FC+1

tPC_PC+2

sPC_PC+4

N IS DETERMINED BY INzTH 3UFFER

pC_®PC+N,

PC+N=7

QK/=0,4,51,D

OLFALLT,

NOP=0
LEFT2=1
RIGHT2=2

HOLD

;COUBLE SKIFT

LEFT 2

;DOUBLE SHIFT RIGHT 2

LEFT=5

66¢

RIGHT=6

INTEGER FCRMAT

SHF=8

tLCAD SHF,

SHF.FL=9
DEC.CON=CA

sDECIMAL COWSTANT

SLCAD SHF,

UNPACKED FLOATING FOR. AT

= 6'S IN EACH ~i33LE

FOR WHICH ALU CRY OuT IS FALSE

ACCEL=08

s LOAC ACCELERATOR DATA FROM DF B.S

D=0C
1D=0E

;1 L0AD

RAMX/=0,1,77,0

;DATA PATH MIXER TO AMX

(DEFAULT

£=0

Q=1
RBMX/=0,1,77

1D BUS

:LCAD ZERO

CLR=0F

;DATA PATH MIXER TO EMX.

SAME EIT AS RAMX

Q=0
D=1

SCK/=0,1,23,C

:1SC REGISTER CONTRCL

(DEFAULT,

NOP=0

tLCAD

LOAD=1

SGN/=0,3,48,0
NOP=0

LOAD.S5S=1

SS.FrRoM.50=2
NOT.S0=3
SD.FRCM.S5=4
SS. XCH A y=5

CLR.SD?SS=7

SIGN CONTROLE

HOLD

SNMX<09:C0>

:DEFAL T
1SS SLuxN15>
:SS"iD
$8D_NCT SD
T ST_S%

$RT_ALLk15>,

S5_SS.XCR.ALULIS>

;SD AL'\15>. $S_SS.XOR.ALUKIS> . X I~ IF<1>

(LNOD) SNOILINI4A3a a131d WOYH TOHLNOD J1LSONDVIAOHIIN

PC_VA=1

;ALU

SHIFTER

CONTROLS

ALU=0

IDEFAULT,

LEFT=1

7SHF_ALU(L1),

RIGHT=2

INSERT

CNTL

iSHF_ALU(R1),

INSERT

CNTL

ALU.DT=3

;SHF_ALU(DT:

LO,L1,L2,L3),

RIGHTZ2=4

iSHF_ALU(R2),

LEFT3=5

1SHF_ALU(L3)

S1/=3,3,55,D

00€

SHF_ALU

SHIFT

INPUT

INSERT

CONTROLS
H

SHF

DIVD=0

PSL<SN>

Q31

ASHR=1

ALU

Q31
031

ALU

ASHL=2

ZERQ=3
SPARE=4
DIv=5

Q31

MUL+=6

Q31

ALU

MUL-=7

ALU

0,1

ALU

0,1

SMX/=0,2,16

‘MIXER

EALU=0

TEALU

sFE9:0>

VALUKO9: 00>

ALU.EXP=3

07>
TALUKTS:I

:SCRATCH

PAD

OPCODE,

NOP=0

iDEFAULT

LOAD.LC.S5C=6

i LOAD

WRITE.RC.5C=7

LC,

;WRITE
74

FUNCTION

BITS

RC,

SPO

BITS

ADR=SC[03:00]

FIELD

LOAD. LAB=1

tLOAD

LA,

FROM

R{ACN)

1 LOAD

WRITE.RAB=3

LA_RN,

HOLD

iWRITE

RA,

+AC

NUMBER

C3t

ADR=SC[03:00]

LOAD.LA=2

SPO.ACN/=0,3,35

C31

<9:0>

FE=1

SPO.AC/=0,4,38

ALU=2

$P0/=0,7,35,D

INSERT

CNTL

;VAX

SPO

MOCE

(ACN)

FIELD

SP1.SP1=0

SP1

SP2.5P2=1

SP2

(LNOD) SNOILINIZ3A @1314 WOH TOHLNOD J1LSONOVIAOHDIIN

SHF/=0,3,85,D

PRN=3

-1

SC<03:00>

PRN+1=4

SC=5
SP1+1=6

;—-11

DST.SRC=2

SC<03:00>

SP1

R+1

SRC R

:SRC.SRC=3

SRC R .DR.
SC<03:00>

14
B

SC=5

R+1

RB
SRC R
DST R
SRC R

RA
SRC R
DST R
DST R

MCDE
;0
HA
H3

SRC.OR.1=4

SPO.R/=0,3,39
LOAD.LC=2

SP1

PRN+1

+AC NUMBER IN SPO FIELD =-- 11 MODE

SRC.SRC=0
DST.DST=1

SRC R

SRC R .OR.
$C<03:00>

:SCRATCH PAD FUNCS WITH LOW 4 BITS OF SP AS ADR
: LOAD LC, ADR=SPO.RN
(WRITE RC
;LCAD LA, LB
;WRITE RA, RB
1 LOAD LA, LB[R1], AND

WRITE.RC=3
LOAD.LAB=4

L0E

SP2 R
PRN

SPD.ACN11/=0,3,35

SP1
PRN

;2
'3

WRITE.RAB=5

LUAD.LABT1.WRITE.RC=6
LOAD.LC.NRITE.RAB1=7
;RA/RB
SPO.RAB/=0,4,35

LOCATIONS

;L0AD LC[RN],

WRITE RC[RN]

AND WRITE RA,

RB[R1]

RO=0
R1=1

R2=2

R3=3
R4=4
R5=5
R6=5
R7=7

sR12

AP=0C

ARGUNENT LIST POINTER
STACK FRAME POINTER

FP=0D

;R13

SP=0E
R15=0F

sR14

STACK

R1S

PC,

SPO.RC/=0,4,35
T0=0
T1=1
T2=2
13=3

+RC

LOCATIONS

PGINTER

SOFTWARE,

SCRATCH TO UCCDE

(LNOD) SNOILINIZ3a d1314 WOY TOH.LNOD J1LSONOVIAOHIIN

SP2.SP1=2

T6=6
T7=7

LC.Sv=8

MEM

VA.Sv=2

MGMT

SAVES

HERE

PTE.VA=0A

PTE.PA=0 B
PC.SVv=0C

SC.SV=CD
VA.REF=Q0E
MBIT.VA=CF
PTE.MASK =0F

suB/=0,2,64,D

tSUBROUTINE

CCNTROL

NOP=0

tDEFAULT

CALL=1

JPUSH

A1>

CNTO

UPC

RET=2

y"CRY

TCP

FOP

SPEC=3

(REPLACE
UFC

THIS

MICROINSTRUCTION

USTACK
OF

USTACK

TOD

UPC

USTACHK

LOW

WITH

BITS

SPECIFIER

INSTRUCTION

DECODE

BUFFER

VAK/=0,1,25,D

NOP=0

£F
(CEFAULT

LOAD=1

1 LCAD

VALU_O0...

THRU

ALU_O(A)

ALU_O[]D

A LU_D.AND...

"AMX,; RAMX.OXT ,DT/LCNG,ALU/A"
"ALU,/@Y,AMX/RAMX
. 0K T, LONG, BMX, REMX , kBMX /D"

ALU_0O-D

YAMX, RAMX.OXT,DT/
D,
LONG.RBMX
BMX,/RBMX,ALU/A-B"

ALU_0=D-1

YAMX,/RAMX.OXT ,DT/LONG,R3MA/D,EVA/RBMX, ALU/A~B=1"%

ALU_O+D

TAMX RAMX.OXT

ALU_0-K[]

"ANK/R
DT/ LONG
AVX,OX
KM 721, BUX/KMX, ALY, T
A-B"
"KMX /81, BMX/KMX, ANIX, RAX.OXT, DT /LONG,ALU/A=B-1"

ALU_O-K[]1-1
ALU_O+KI[]
ALU_O+K[
]+

DT, "LONG, R2MA/D, EVX/REMX , ALU/A+B"

"KMX /@1, BMX/KMX , AMC/RAM
DT /LONG,ALU/A+B"
ALOXT

YEMXS@1,BMK/KMX
AMX RAMYCOXT DT /LONG,ALU/A+B+1 TM

FROM

(LNOD) SNOILINIZ3a a1314 WOY TOHLNOD JILSONDVIAOHIIW

T4=4

15=5

" AMX
; RAMX LOXT ,OT/LONG,EMX
LB, ALU/A+B+1"

/ RAMX LOXT,DT/LONG,BMX/LC,ALU/A+B"
“ AMX

ALU_O~LC
ALU_O+LC+1
ALU_O~-LC=1
ALU_O+MASK+1
ALU_0+Q

/R AR)
“AMX

ALU_D-Q

"AMX/RAMX
. OXT,DT/LCNG,R3MX,/Q,BIX/REMX
,ALU/A-B"

ALY_0=-Q-1

"AMX
/ RAMX . OXT,DT,/LONG,R3WX
- Q, EMX/REMX ,ALU/A-B~1"

ALU_O+Q+1

"AMX/RAMX
. CXT,DT/LONG.RBVX/Q,BNX/RBMX,ALU/A+B+1"

LOXT,DT/LONG,EMX/LC,ALU/A-B"

"AMX
/ RAMX OXT,DT/LONG,2MX "'LC,ALU/A+B+1"

" AMX, RANX LOXT,DT/LONG,2¥MX "LC,ALU/A-B~-1"
YAMX/RAMX., CXT,DT,/LONG,EMX/NVASK,ALU/A+B+1
"

"AMX, RAMX LOXT,OT/LCNG,
&BWX/Q, BMX/RBMX,ALU/A+B"

ALy_=-1

“ANMX,/RAMX
. OXT,DT/LCNG,ALU/NDOTA"

ALU_D
ALU_D.OXT[]

"RAMX /D, ARMX /RAMX.OXT
,DT /@1 ,ALU /A"

"RAMX /L, AMX/RAMX
,ALU /A"

ALU_D.OXT[].AND.K[]

SRAMX /D, AMARAMX.CXT,OT,/@1,KMX
/@2, BMX/KMX , ALU/AND

ALU_D.OXT[].ANDNIT.K[]

“ALU/ANDNOT,AMX/RAMX.OXT,DT/@1,RAMK/D,BMX/KMX,
KMX,/E2"

ALU_D.OXT[)+K[]
ALU_D.OXT[1-K[]
ALU_D.OXT[]+LC
ALU_D.OXT[]1+Q
ALU_D.OXxT[1-Q
ALU_D.AND.K[
]

CRAMX /D, AMX/RAMX.OXT

ALU_D.AND.MASK

CRAMX /D, AWMX/RAMX,
BMX /MASK , ALL, AND"

"ALU/A=B, AMX/RAMX.OXT,
DT &1 ,RAVY/D, BMX/LC"

MALL A+, AMX/RAWY . OXT,DT

ALU_D[ IKI[]
ALU_D+K([
]

ALU_D~-K[]
ALU_D+K[
]+1
ALU_D-K[]-1
ALU_D-LB
ALU_D[]tC

ALU/ANDNOT"

“RAMX/D, AMX,/ RAMX, BIIX, NASK, ALU/ANDNOT "

“RAMX/D, AMX,/RAMX,REBMX,/Q,EMX,/RIMX,
ALU/ANDNOT*"

THRU

ALU_D(B)

/D, 3MX,/RBMX , RBMX /Q"

"RAMX /D, AMX, RAMX , KEX "&1 , BMX/KMX ,

ALU_D.ANDNOT .MASK

JALU_D(B)
...

81, 24K

"RAMX/D,AMX/RAMX.0XT
,DT 71, REBMX, Q, BMX/RBMX , ALU/A-B"
"RANMX /L, AMX/RAIMX , KMA, E1, BMX, WX, ALU/AND"

ALU_D.ANDNOT.K[
]
ALU_D.ANDMNOT.Q

DT,/21,KMX/82, BMX/KMX,ALU/A+8"

C"RAMX /D, AAX/RAMX. OXT ,OT /@1, h4X /72, BMX,/KMX , ALU/A=B*

ALU_D.XOR...

"“RBMX/D,BMX/RBMX,ALU/B"
CRAVK/ D, AMX/RANX , KMA /B2, B\

RMX, ALU/B1 "

PRANMX,/ D, AMX RAMA, KM, @1, BMX KMYX , ALU/A+B"
PRAMX, D, AMX/RAMX , K% /&1, BMX ‘KM« , ALU/A-B"
CRANMK/D, AMX,/RAMX , KMX /81 ,EMX, aNX, ALU/A+B+1*
PRAMX /D, AMX/RAMK , KMA /@1, EWX, kWL

ALU_D+LC

"RAMX,; D, AMX/PANMX,BMA/LB,ALU/A-B"
CRAVX /D, AMX/RAMX,
BV LC, ALY, T
“RAMX/D., AMX/RAMK , BLX/LC,ALU,
A+S"

ALU/A=B=1"%

ALU_D-LC

CRANMX,/D,ANX/RAMX,
EMX /LC,ALU, A=B"

ALU_D-LC=-1

"RAMX,/D.,AMX/RAMX ,B/X/LC,ALL, A=B=1"

ALU_D+LC+PSL.C

“RAMX /D, AMX /RAMX, E¥L/LC,ALU,/Av3+PSL.C"

ALU_D.DR.K[]
ALU_D.GR.LC

“RANX/D, AMX/RAMY ,8Mx/LC,ALLU,
QR

BRANMX/D, AMX/RAMK , KX /BT, B2/ WY, ALU/OR"

(LNOD) SNOILINI4Z3Aa 7314 WOH TOHLNOD J1LSONSDVIAOHIIW

€0¢g

ALU_O+LB+1

ALU_O+LC

ALU_D[]Q
ALU_D+Q
ALU_D~-Q
ALU_D+Q+1
ALU_D-Q-1

ALU_D+Q+PSL.C

YRAMX /D, AMA,

"RAMX /D, AMX/RAMX,RBMX/Q,BMX/RBMX,ALU/A+B"
"RAMX /D, AMX/RAMX ,REBMX,'Q, BMX/RBMX ,ALU/A-B"
"RAMX /D, AMX/RAMX ,RBMX,/Q,BMX 'RBVX,ALU/A+B+1"
"RAMX /D, AMX/RAMX ,REMX/Q,BMX /RBMX, ALU/A-B-1"
RBLX,RBMX/Q, RAMX/D"
SL.C,AMX,
RAMX, BMX,
"ALU/A+B+P

ALU_D.SXT[]

T
DT, 81 ,ALU/A"
"RAMX/D,AMX,/RAMX.SX

ALU_D.SXT[]+K[]
ALU_D.XOR.K[]

1,KWX,
32, BMX/KMX,ALU/A+B"
CRAMX,/D,ANX/RAMX.SXT,DT/@
"RAVIX /D, AMX/RAMX ,KMX /@1 ,BMX, KMX , ALU/XOR"

ALU_D.SXT[].AND.KI ]
ALU_D.XOR.LC

ALU_D.XOR.Q

ALU_D.XOR.R[]
ALU_D.XOR.RC[]
{ALU_K...

140

RAMX, EMX ,'MASK, ALU/ORNOT*®

"RAMX/D,AMX/RAVX,REMX,/Q,BMX, REMX,ALU/OR"
X/RAMX
, REMX,/Q,BMX/RIMX,ALU/@1"
"RAWX/D,AM

THRU

ALU_K[
]
ALU_LA

"RAMX,/D, AMX - RAMX.SXT,DT/@1,KMX/@2,BMX/KMX,ALU/AND"

“RAMX /D, AMX/RAMX , BMX,/LC,ALY/XIR"

"“RAMX/D,AMX/RAMX ,REMNX/Q.BMX/RBMX,ALU/XOR"

“RAMX/D,AMX/RAMX,S570.R/LOAD.LAB,SPO.kAB/@1,BMX/LB,ALU/XOR"
“RAMX/D.AMX/RAMX ,SFO.R/LOAD.LC,SPO.RC/@1,BMX/LC,ALU/XOR"

A LU_PC...
"KMX/@1,BMX/KMX,ALU/B"
“AMX/LA,ALU/A®

"AMX /LA ,KIAX /@1, BMX/KMX,ALU/AND"
ALU_LA.AND.K[]
"AMX /LA, KMX/@1,BMX/KVMX,ALU/ANDNOT"
A ]
. ANDNOT.K{
ALU_L
"AMX,/LA,BMX/MASK,ALU/ANDNOT*
ALU_LA.ANDNOT.MA SK
ALU_LA.XOR.LC
ALU_LAT]D
ALU_LA-D

ALU_LA-D-1

ALU_LA+KI[]
ALU_LA=-K[]
ALU_LA+K][
]+1
ALU_LA+K[ ].RLOG
ALU_LA-K[].RLOG
ALS_LA[]LB
ALU_LA+LC

ALU_LA[]1Q
ALU_LA+Q

“AMX/LA,BMX/LC,ALU/XCR"

"AMX/LA,RBMX/D,BMX/REMX,ALU/®1"

/RBMX, ALU/A~-B"
TAMX,/LA,RBMX/D,BMX
“AMX/LA,RBMX/D,BMX/RBMX,ALU/A-3=1"
"AMX/ LA, KMX/@1,BMX,/KMX,ALU/A+B"
"AMX/ LA, KMX/®1,BMX/KMX,ALU/A-B"

X
BMX/KMX , KMX/@1"
1,AM
/LA,
"ALU; A+S+
"AMX/LA,KMX/@1,3MX/«uMX,ALU/A+B.RLOG"
YAMX, LA, KMX/®1,3MX/XMX,ALU/A~B.RLOG"

YAMX, LA,ENX/LB,ALU/21"

/LC"
"ALU,/A+8,AMX/LA,BMx
"AMX/LA,RBVMX/Q,BMX/RBMX,ALU,/G1"

YALU/A+B,AMX/LA,BMX/RBMX,RBVX/Q"

ALU_LA-Q

"ALU/A=B,AMX/LA,BMX/RBMX,REMX/Q"

ALU_LA-Q-1
ALU_LB
ALU_LC

“BMX,/LB,AaLU/B"

“ALU/A-B-1,AMX/LA,BMX,/RBMX,RBMX/Q"

"BMX/LC,ALU/B"

(LNOD) SNOILINI43a d1314 WOY TOYLNOD J11LSONOVIAOHIINW

ALU_D.ORNOT.NMASK
ALU_D.OR.Q

"ALUNJTA,

“BMX/PACKED.FL,ALU/B"

ALU_PC

{ALU_Q...

AMX/RAMX,RAMX /D"

"SPO.R/LOAD.LC,SPO.RC/@1,BMX/LC,AM
,DT/LONG,ALU,
X/RAMX.0XT
ORNOT"

ALU_PACK.FP

“8MX/PC,ALU/B"

THRU

C ACHE_...

ALU_Q

"RAMX/Q,AMX/RAMX,ALU/A®

ALU_Q.OXT[]

"RAMX/Q,AMX/RAMX.OXT ,DT/@1,ALU/A"

ALU_Q.OXT[].ANDNOT.K[]
ALU_Q.OXT[].0OR.K (]

“ALU/ANDNOT,AMX/RAMX.OXT,DT/@1,RAMX/Q,BMX/KMX,KMX
/32"
“ALU/OR,AMX /RAMX.OXT,DT/@1,RAMX/Q,
BMX/KMX , KMX/@2"
ALU_Q.0OXT[].0OR.D
"ALU/OR, AMX,/RAMX.OXT,DT/@1,RAMX/Q,
BMX/RBMX , RBMX/D"
ALU_Q.OXT[]+D
"ALU/A+B,AMX/RAMX.0OXT,CT/@1,BMX,/RBMX,RBMX/D,
RAMX/Q"
ALU_Q.OXT[ ]+D+1%
ALU_Q.OXT[]+K([]

G0€

ALU_Q.OXT[ ]J-K[]
ALU_Q.AND.K[]

“ALU/A+B+1,AMX/RAMX.OXT ,CT/®1,BVX/RBMX,

RAMX/Q, RBMX /D"

"ALU/A+B,AMX/RAMX,OXT,DT
81 ,RAMX/Q, BMX/KMX , KMX /62
.
%
“ALU/A-B,AMX/RAMX.0AT,DT/21,RAMX/Q
BMX/KMX , KMX /@2%
,

"RAMX/Q, AMX/RAMX , KMX /€1, BMX, KMX , ALU/AND"

ALU_Q.ANDNOT.MASK

"RAMX/Q, AMX/RANX,EMX, NASK,ALU/ANDNOT "

ALU_Q.ANDNGCT.K[]

TRAMX/Q, AMX /RAMX, KMX,/ @1, BMX/KMX, ALU/ANDNOT¥

ALU_Q(B)

"RBMX/Q,BMX/RBMX ,ALU/E"

ALU_Q[
JD

"“RAMX/Q, AMX/RAMX , RBMX /D, BMX /REMX , ALU/@1 "
"RAMX,/Q,AMX/RAMX
,RBMX,/ D, BMX, RBMX ,ALU/A=B"

ALU_Q-D
ALU_Q-D-1

"ALU/A-B-1,AMX/RAMX,
RAMX /Q, BMX, RBMX , RBMX /D"

ALU_Q+K[
]
ALU_Q-KI[]
ALU_Q+K[
]+1
ALU_Q+LB

“RAMX/Q, AMX/RAMX , KMX /@1, BMX /KMX , ALU/A+B"

ALU_Q-LB

"RAMX/Q,AMX/RAMX,BMX/LB,
ALU/A~B"

ALU_Q+LB+1

“RAMX/Q, AMX /RAMX , BMX /L3, ALL,/ A+B+1"

ALU_Q+LC
ALU_Q-LC

"RAMX/Q, AMX/RAMX , BVMX /L, ALU/A+B"

"RAMX/Q, AMX/RAMX , KMX /@1, BMX /KMX , ALU/A=B"

"ALU/A+B+1,AMX/RAMX
, RAMX/Q, BMX/KMX , KMX /@1 ¥
"RAMX/Q ., AMX/RAMX , BMX /LB, ALU,A+B"

“RAMX/Q, AMX/RAMX,
BMX /L, ALU/A=B"Y

ALU_Q+LC+1

"ALU/A+B+1,
AMX/RAMX , RAMX,/Q, BMX/ LC"

ALU_Q+MASK

"ALU/A+B,
AMX/RAMX , RAMX/Q, BMX /MASK"

ALU_Q-MASK-1

“ALU/A=B=1,AMX/RAMX,
RAMX 'Q, BMX /MASK"
"RAMX,/Q . AMX /RAMX , KMA /@1, BMX/KMX, ALU/OR"
"RAMX/Q,
AMX/RAMX ,BMX/LC,ALU/OR"

ALU_Q.OR.K[]
ALU_Q.OR.LC

ALU_Q.ORNOT.K[]
ALU_Q.SXT[]

“ALU/ORNOT,
AMX/RAMX , RAMX,/Q ., BMX/KMX , KMX /@1 "

"ALU/A,AMX,/RAMX.SXT,DT/81
,RAKX, Q"
ALU_Q.SXT[].ANDNGT
.K[]
"ALU/ANDNGT,AMX/RAMX.SXT,RAMX/Q,BMX/KMX,KMX/®2,DT/@1"
ALU_Q.SXT[]+K[] "RAMX/Q,AMX/RAMX.SXT,DT/@1,KNX
/82, BMX,/KMX,ALU/A+B"
ALU_Q.SXT[]+LB
“RAMX,/Q, AMX/RAMX.SXT
,DT /@1 ,EMX/_B,ALU/A+B"

(LNOD) SNOILINIZ3a a13id WOY TOHLNOD JILSONOVIAOYIINW

ALU_NOT.D
ALU_NGT.RC[]

“RAMX/G,AMX/RAMX.SXT,DT, 31, ENX PC,ALU/A+B"
YRAVX,Q,AMX/RAMX, BMX /RBIAXK,REMX, D, ALU/XOR"

ALU_Q.XQR.LC

"RAMX/Q,AMX,/RAMX BV

ALU_Q.XOR.K[]

YRAMX /G, AMX/RAMK, h»(/fil sux,kmx ALU/XOR“
LC,ALU. XOR"

“SPO.R/LOAD.LAB.SPQ.RAB/@1,AMX/LA.ALU/A"

ALU_R[ ]

ALU/AND"
,A%WX,
LA, KMX/®2,BMX/KNMX,
ALU_R{].AND.K[] “SPO.R/LCAD.LAB.SFD.R&3,/&1
"SPO.R/LOAD.LAS.S?O.RAS/@!.AMX/LA,BMX/MASK,ALU/ANSNOT"
ALU_R[ ].ANDNOT .MASK
ALU_R(DST)

ALU_R[]).OKr.K[]

“SPO.AC/LOAD.LAB,SCG.ACNt1/D3T.0ST,AMX/ LA, ALU/A"

"SPD.R/LOAD.LAB.SPS.RAP;@1,AMX/LA,KMX/@2,SMX/KMX,ALU/OR"

ALY_R[}.ORNIDT.K[] "ALU/ORNDOT, AMX /LA, BUX hMX,S5PC.R/LCAD.LAB,SPC.RAB/@ KMy, 22
ALU_R[].XOR.K[} "SPO.R/LOAD.LAB,SPJI.RAS, &1, ANX LA, KMX/€2,BMX/KMX,ALU/XOR"
ALU_RCI[]

"SPO.R/LDOAD.LC,SPO.RC,/B1,3MX/LC,ALU/B"

ALU_RC(SC)

"SPO/LCAD.LC.SC,.BMX, LC, ALY/ B"

CACHE_DOI[ ]
CACHE[ J_D

"VAK/NQP ,MCT/WRITE.V.NCHK,DT,&1,DK/NOP"
"VAK/NOP ,MCT/WRITE.V.WCHK MSC /@1 ,DK,/NOP"

CACHE.o_DI]
CACHE_D[].LK

"VAK/NCP ,MCT/WRITE.P,DT/&1, DK, \up'
"VAK/NOP,MCT/LOCKWRITE,.V.XCHK,DT/@1,DK/NOP"

ALU_R(SP1)+K[].RLOG

"SPO.AC, LOAD.LAE,SFO.ACN,/SP1.SP1,AMX/LA ,KMX/@1, BUX, KiiX,ALU/A+B. RLOG"

90t

YVAK/NOP MCT/WRITE. V. hyHK DT/INST.DEP,DK/NOP"
CACHE_D.INST.DE?
CACHE o[] NOCHK °“VAK/NOP ,MCT/WRITE.V. NZCHK,DT, &' ,DK/NOP"
:0_0...

THRU

D_0O

D_CACHE...

“DK/CLR"

D_0-D

“AMX/RAMX.OXT,DT/LONG.RBMX/D.BMX/RBNMX,ALU/A=8,SHF /ALY, DK "SHF "

D_O+LC+1
0_0-Q

"ANMX,RAMX.OXT,DT/LCNG.BMX LC,ALU/A+B+1,SHF/ALU,DK/SHF"
"AMX, RAMX.OXT DY,LV.J.RS‘x,O eMX /RBMX, ALU/A-B, SHF/ALU,DK/SHF"

D_O+K[ ]+t
D_ACCEL&SYNC

"Amx,RAMX.QXT,DT/Lf\,,uM\ @1, BMX/KMX, ALU/A+B+1,SHF/ALU, DK/ SHF "
“DK/ACCEL.ACF/bYNC

D_ALU

"SHF/A_U,DK/SHF"

D_ALU.LEFT2
D_ALYU.LEFT3

"SHF//ALU.CT,.DT,/LONG,DK/SHF"
/SHF"
“SHF,LEFT3,CK

D_ALU. LEFT

D_ALU.RIGHT
D_ALU.RIGHT2
D_ALU{FRAC)
D_BLANK

"SHF,/LEFT,DK/SHF"

"SHF /RIGHT , DK,/ SHF"
“SHF,/RIGHT2,DK/SHF"
"SHF,ALU.DK/SHF.FL"
"D_K[.z01"

"VAK/HSF,MCT/READ.V.RCHK.DT‘@1.DK/NOF“
D[ J_CACHE
"VAK,/NCP,MCT/READ.V.RCFK, %f'a. DK/NOP*
D_CACHE( ]
LDK/NCP"
D[ ]_CACHE.IBCHK "VAK/NCP,MCT/READ.V.IBC(HK.DY

(LNOD) SNOILINI4Z3AQ A1314 WOH TOHLNOD JILSONOVIAOHOIIW

ALU_Q.SXT[]+PC
ALU_Q.XOR.D

O J_CACHE.LK
O[ J_CACHE .NOCHK
D[ J_CACHE.P

“VAK/NOP ,MCT/LOCKREAD.V.WCHK,DT,/@1,DK/NOP*
“VAK/NOP.MCT/READ.V.NOCHK.DT
/@1 .DK/NOP"

"VAK/NCP ,MCT/READ.P,DT /@1,DK/NGP"
,DK/NOP"
/@1 HK,DT
"VAK/NOP ,MCT/READ.V.WC
"VAK/NOP ,MCT/READ.V.WCHK ,MSC,/®1,DK/NOP"

D[ 1_CACHE .WCHK
D_CACHE .WCHKI ]
sD_DAL... THRU D_D...
D_DAL. NORM

D_DAL.SC

D_D.OXT[]

*"DK/DAL.SV"
"DK/DAL.SC"

HF"
OXT
,SHF/ALU,DK/S
/RAMX.
,DT/®1,ALL/A
"RAMX,/D,AMX

"RAMX/D,AMX/RAMX.QXT.DTJ@1,KMX/@2,BMX/KMX.ALU/ANDNOT.SHF/ALU.DK/SHF”
“RA“X/D.AMX/RAMX.OXT,DT/@1,RMX/®2.BMX/KMX.ALU/A+B.SHF/ALU,DK/SHF“
"RAMX/D.AMX/RAMX.OXT,DT/@1,RBMXvQ,BMK/REMX.ALU/OR.SHF/ALU.DK/SHF"

D_D.OXT[].ANDNOT K[

LOE

D_D.OXT[]+K[]
D_D.OXT[].OR.Q
D_D.OXT[1+Q

"ALJ/A+B,AMX/RAMX.O(T,DT,@1.BMX/RBMX,RBMX/O,D_ALU"
ALU"

"RAMX/D.AMX/RAMX.OXT,DT/©1,BMX/RSMX,ALU/A+B+1,D_
D_D.OXT{ ]+Q+?
1.RBMX/Q,BNX/RBMX“
D_D.OXT[].X0OR.Q “DK/SHF.ALU/XOR,SHF/ALU.AMX/RAMX.OXT.RAMX/D,DT/@
“RAMX/D,AMXfiRAMX.JXT.DT/@1,SPO.R/LOAD.LC.SPO.RC/@2,BMK/LC.ALU/XOR,SHF/ALU.DK/SHF“
D_D.OXT{].XOR.RC (1
"RAMX/D,AMX/RAMX,KMX/@l,BMX/hMX,ALU/AND,SHF/ALU,DK/SHF"
D_D.AND.K[]
D

_D.AND.K[].LEFT2

D_D.AND.K[].RIGH T
D_D.AND.LC

D_D.AND.MASK

D_D.AND.Q

D_D.AND.RC{]
D_D.ANDNOT.K{]

D_D.ANCNOT.LC
D_D.ANDNOT.PSW2Z
D_D.ANDNOT.Q

O_D.ANDNOT.RC[]

D_D(FRAC)

D_D[IK[]
D_D+K[]

D_b-K[]
D_D+K[ ]+1
D_D+LB
D_D+LC
D_D-LC
D_D+LC+PSL.C

"RAMX/D,AMX/RAMK,KMX{@Y.BMX/KMX.ALU/AND,SHF/ALU.DT.DT/LONG.DK/SHF"
"RAMX/D.AMX/RAMX.KMX/©1,BMX/KMX,ALU/AND.SHF/RIGHT,DK/SHF“

U
SHF/ALU,DK/SHF"
AND, ,/LC,AL
"RAMX, D.AMX/RAMX,BAX
"RAMX/D.AMK/RAMX,BMX/MASK.ALU/A\D,SHF/ALU.DK/SHF“

"RAMX/D,AMX/RAMX.RBMX/O.BMXjQSYK,ALU/AND.SHF/ALU,DK/SHF"
"RAMX/D.AMX/RAMX,SPO.R/LOAD.LC.SPO.RC/@1,BMX/LC.ALU/AND,SHF/ALU,DK/SHF"
”RAMX/D.AMX/RAMK.KMX/@1.EMX,KVK.ALU/ANDNOT,SHF/ALU,DK/SHF"
/ALU, DK/SHF"
ANONOT , SHFRAMX
AMX/
, BMX /LC,ALU,
"RAVX,D,

"DK/SHF,ALU/ANDNOT.AMK/RAMX,RATK/D.BMX/KMX.KMX/.4,SHF/ALU"
"QAMX;D,AMX/RAMX,RBMX/Q.BVK«REMK,ALU/ANDNOT.SHF/ALU.DK/SHF"

"RAMX;D,AMX/RAMX,SFS.R/LOAD.LC,SPO.RC/@I,BMX/LC.ALU/ANDNOT,SHF/ALU.DK/SHF“
HF
/2 U, OK,/SHF.FL"
CRAVX /D, AMX/RAMX,ALU/A,S

CRAMX /D, AMX/RAMK , KMX /@2, BVX WX, ALU,/@1,SHF/ALU,DK/SHF"
"RAMX]D,LMX/RAMX,KY({@I.BMX/KMK.ALU/A*B,SHF/ALU.DK/SHF“
“RAMX/D.AMX/RAMX,KMX/@1,BMX/KMX.ALU/A-B,SHF/ALU.DK/SHF"

"RA%X'D,AMX/RAMX,KMX/@!.BMX/KMX,ALU/A+B+1,SHF/ALU.DK/SHF“

"RAWX/D.AMX/RAMX.BMX/LB,ALU[A+B.SHF/ALU,DK/SHF"
"RAMX,D,AMX/RAX,BMX, LC,ALU/A+B,SHF/ALU,DK/SHF"
“RAMX /D, AMX/RAMX ,BMX/LC,ALU/A~B,SHF/ALU,DK/SHF"

“QAMK/C.,ANX/RAMX,BMX/LC,ALUA+B+PSL.C,SHF/ALU,DK/SHF"

(LNOJ) SNOILINIZ3A a131d WOYH TOHLNOD JILSONODVIAOHIIN

D_CACHE. INST.DEP
"VAK/NOP ,MCT/READ.V.1BCHK,DT/INST.DEP,DK/NOP"
D_CACHE.LK[]
"VAK/NGP ,MCT/LCCKREAD.V.WCHK,MSC/@1,DK/NOP"

“DK/LEFT”

"DK, LEFT

_D[ )MAsSK
.OR.ASCII

"D_D.OR. K[.30]"

.OR.K[
]

"RANX /D AV

RAMX EMX /21, BMx KNX, ALU/OR, SHF/ALU, DK /SHF "

.ORNOT. MASK

"RAMX.
D, ANIX/RAMX ,

.OR.PSWC

"Dk, SHF, ALu/OR,AMX/QAmx,RAxx,C.SMX/Kmx,xmx/.1,SHF/ALU"

.OR.PSWV

"LK,SHE, ALU/OR, AMX /AKX, RALC ,:HX/wa KMX/.2,SHF/ALU"Y

OR.Q

VX /MASK ALU, GRNOT,SHF,/ALU,DK,/SHF"

“RAMX.'D, AN
X RAMX, RSLA, Q,BMX, K87 %, ALU/
7 . SHF/ALU, DK/SHF
"

.OR.RC[]

YRANK //T

.:U(,RA”A,Sfld.?,L_A”

C ‘PO RC/21,8¥%X/LC,ALL/0OR,S-F/ /ALY,DK/SHETM"

"RANX, T, AVX/RAMX RBINX. G, '"A/ E”K ALU/@1,SHF/ALU,DK/SHF"
"RAMK,D. AVX/RAMX, K214, Q, 25
JRIVMX ,ALU/A+B,SHF/ALU,DK/SHF"
"RANX,
DL AVX/RAMY REMXQ, CNA

ETK,ALU/A-E.SHF/ALU,DK/SHF“

"RAMX/CLAVXRANING, RO, G, :vx REVA,ALU/A+8+1 ,SHF/ALU,DK/SHF "

CRAVK D AmX/RAJX,BV X, Q, BMX,
REMNX,ALU/A-B-1,SHF/ALU,DK/SHF
"

]

Lol

80¢€

"RAMX /D, AMX/RAMX,BMX/MASK,ALU/@I,SHF/ALU,DK/SHF"

"OK, RIGHT"

LRIGHT2

u.lnlufi

Tom

LRIGHT(B)

REVX,D,BVX/RBUX,ALU/3,SHFRIGHT
,CK/SHF "

.SWAP

EYTE. SwAP"

LSXT[]

"TRANVX/SVAVX/RANX.SXT
DT, %1, ALU/A,SHF/ALU,DK 'SKF®

.SXT[].RIGH T

URANK,D, ANX/RAMX . SXT, CY, @1, /LU

.XOR.KI[]

“RAMX /D, AMX/RANMA,KMX
/€5, 20X

.XOR.LC

"RAMX/D SAMX/RAMX
, Bivix LT, ALU

"D.XCR.Q

;D_INT.SuUMm.
.

D_INT.SUM

D_K[]

D_K[].RIGHT
D_K[].RIGHT2

SHF/RIGHT,CK/SHF"

RMX,ALU/XCR, SHF/ALU, DK/SHF "

CR,SHF/ALU,DK/SHF"

"RAMK/D, AMX /RANMX, REMX,'Q, BVMX/RBMX,ALU/XOR,SHF/ALU,DK/SHF"
THRU

D_PC. ..

"MCT/READ.INT,.SUM,DK/NCP"
YKMX /@1 BMX/KMX AL, B, SHF/ALU,DK/SHF"

, ALU /B, SHF 'RICHT ,DK/SHF"
“KMX,@1 , SMX/KMX
KX
@

SBMX/KMX, ALU B, ST /RIGHRT2, DK/SHF TM

D_LA

YANMX S LA ALU/A,SHF/ALL,CK/ShHF"

D_LA.AND.K[]

“AMX/LA KMX /@1, BMX,/kMX, ALU/AND,SHF/ALU,DK/SHF"

D_LA+D+PSL.C

"AMX, LA, REMX/D,EMX/SBMX,ALU/A+B+PSL.C,SHF/ALU,DK/SHF"

D_LA-D

"DK/SHF, ALU/A=B,AMX/

D_LA(FRAC)

"AMX /LA, ALU/A,SHF/ALL
, DK/ SH7 b L"

D_LA-K[]

D_LA.RIGHT

LA, KX,/ @1, BMX

LA, 2V /R3MX,RBMX,/D,
SHF/ALU"
wMX, AL/ A-B,SHF/ALU,DK/SHF"

TAMX /LA, ALU/A,SHF/RIGHT ,CA/SHF"

D_.B

"HMX, LB, ALU/B,SHF /ALY, Cihy SHFY

D_L8.PC

“3AX/PC. OR.LB,ALU/S,SHE/
ALY, DR /SHF"

(LNOJ) SNOILINI43a @1314 WOH TOHLNOD J1LSONOVIAOHIIN

O(DC(DUCDOEDFEJO(DOfDO(DOEJO(DOUCDO

O(SO(JO(DDC?OC7U?EJO(JUCJUDEJU(DU

LLEFT

.LEFT2

"BMX/LC,ALU/B,SHF/ALU.DK/SHFE"
“BMX,/LC,ALU/B,SHF/ALY,DK/SHF.FL"

D_NOT.D
]
D_NOT.K[

CKMX, @1, BIMX,/KMX, AMX/RAMX.CXT ,DT/LONG, ALU/ORNOT, SHF/ALU,DK/SHF*"

D_NOT.MASK
D_NOT.Q

D_NOT.R[]

QOOODOOLOLODLOODO

i
OUOUEFJOUOOUOUOOUU

OUUOOOUOUU

60€

D_PACK.FP
D_PACK.FP.LEFT

"RAMX /D, AMX /RAMX ,ALU/NOTA,SHF/ALU,DK/SHF"

“BMX/MASK, AMX/RAMX.0XT,D7/LONG,ALU/ORNOT,SHF/ALU, DK/SHF*"
“RANX/Q,AMX/RAMX, ALY /NCTA,SHF/ALU,DK/SHF"

“LA_RA[®1],AMX/LA,ALU/NDOTA,D_ALU"

‘8 K,rApKED FL,ALU, B,S“F/A U,CK/SHF"
“BMX/PA”KED FL,ALY/B,SHF/LEFT ,DK/SHF"
"BMX,/PC,ALU/B,SHF/ALU,DK/SHF"
“BMX/PC.ALU/B,SHF/LEFT,DK/SHF"

IIDK/OII

.OXT[]
.AND.K[]

.AND.LC

. MASK
. AND
.ANDNCT.D

]
.ANDNOT.K[
.ANDNOT .MASK

.ANONOT.PSWC
.ANCNOT.P3SWN

.ANDNOT.PSWZ

.AND.RC[]

"RAMX/Q.AMX/RAMX. OXT ,DT/®1,ALU/A,SHF/ALU,DK/SHF"

TRAMX/Q, AMX/RAMX, Klik /@1, BMX,/KMX,ALU/AND, SHF /ALU, DK/SHF*"
"RAMX/Q,AMX/RAMX,BMX;L” ALU,; AND,SHF/ALU,DK/SHF"
,/MASK , ALU AND,SHF /ALU,DK/SHF"
BMX MA,
CRANMK Q,ANX/RA

"RAMX/Q, AMX TRAMX,RBMX /D, BMX, R3a¥X, ALU/ANDVDT SHF/ALU,DK/SHF"
, BUX, RYX, ALu/AhuhOT SHF/ALU,DK/SHF"
TRANMX/Q, AMX/RAMK KMLC/D1
CRAMX /ST, AMX,/RAMX, B”K/VA\¢ ALU/ANDNOT,SHF/ALU,DK,/SHF"

RAMX , RANX/Q, BMX/KMX, KMX /.1, SHF/ALU"
DIT,
AMX,
"DK/SHF, ALU/ANDN

"DK/SHF,ALU/ANDNOT,AM(,«Amx,FANX/Q.SMX/KMX.KMX/.8,SHF/ALU“
WDKK,/ SHF,ALU/ANDND T, AVMX/RANX, RAMX/Q, BMX/KMX ,KMX/ .4, SHF /ALY"

D,
SHF/ALU,DK/SHF"
WRAMX/G.AMX/RAMX,SPO.R LOAD.LC,SPO.RC/€&1,BMX/LC,ALU/AN
3K /SHF*"
"RAMX /D, ANX/RAMX , R3VX,/Q.ENX REYX,ALU/A+B,SHF/ALU,DK/SHF
DK/SHF "
RAMX
REMX ,ALU/A+B, SHF/ALU,
, REMX, D, BMX AMX/
CRAMX/Q.
ALU,DK/SHF"
"HAMK/O AMX /RAMK , R3MX, D, BYX, R5VX,ALU/A-B,SHF/
NRAWXD, AMX/RAVMX. RBMX, D, EMX, REVX,ALU/A-B-1,SHF/ALU,DK/SHF"
"RAMX/Q.ANY/RAAX REMX, D, 2WMX, &53.xX,ALU,/®1,SHF/ALU,DK/SHF"
SHF/ALU,OK/SHF . FL"
, ALL /A,X/RAMX
CRAMX /Q,ANM

WRANMX /D, AMX/RAMK, KK /@1, SMX, nMX, ALU/A+B, SHF /ALU,DK/SHF"
WRAVX /G, ANX/RAMX KW A /@1, BWX, nMX, ALU/A-B, SHF /ALU, DK/ SHF"
Q. AVX,RAMX , KMX /&1, EMX, r¥x, ALU/A-B8-1,SHF/ALU,DK/SHF"
VRANX
YRAMX/Q, AMX/RAMX,BMX/LE,ALU/AwD,SHF/ALU.DK/SHF“
K, ALU, @1,SHF/ALU, DK/SHF"
BVX, MASY
DRAMK Q. ANX/RAM
TRANX, S, AMX/RAMX , ALU /A, \HE,;-rT DK/SHF"

CRANMKQ, AMX/RAMX, KMX /81 GM) ¥MX,ALU/OR,SHF/ALU,DK/SHF"
Q. AMX/RAMX, B K’VAS?
PRANMX,

OR PSWC

LU, ORNOT ,SHF /ALU,DK/SHF"

“DK, SHF,ALU/QOR, AMX/RAMX, RANx/Q.fiMX/KMX.KMX/.1.SHF/ALU"

(LNOD) SNOILINI43d @1314 WOY TOHLNOD JILSONOVIAOHIIN

D_LC
D_LC(FRAC)

"RAVK,Q,aflX/RA#X,S?Z.P;LDAD.LC.SPO.RCf@1.SHX/LC,ALU/OR

"RANK

D_Q.RIGHT

"RAMX/QVAV
ALY /A SHFE/RIGHT
X/RAN
DK/ SHF"
X
“RAMX/Q,AMX/RAMX ,ALU/A,SHF/RIGHT2, DK, SHE®

D_Q.RIGHT2
D_Q.5XT[}
D_Q.XOR.RC[]
;D_R...

THRU

AN
G ATUX/RAMA L BIX, B0, 2L
A+3 SHF /ALU, DK /SHE
SLANN/RANMK, B0, MEC, READRLOG,ALU/A-B, SHF/ALU, DK/SKE®

"RAVIX
.SXT
/Q,AMX
,DT,/@1,ALU/A,SH
/RAMX
F/ALU,DK/SHF "
"RAMX/Q.AMX/RAMX,SPC.R/LOAD.LC,SPO.RC/®1,BMX/LC,ALU/XOR,
SHF /ALU,DK/SHE"

D&VA_...

D_RI[]

"SPO.R,LOAD.LAB,SPC.RA3/81,AMX/LA,ALU/A,SHF/ALU,DK/SHF?"

D_R[].ORNOT.K[]
D_RC{}

“LAB_R[®1],AMX/LA,BVX, KX, K\WX,/@2,ALL/ORNOT ,D_ALU"
“SPO.R/LOAD.LC,SPO.RC/®1.2WMX, LC,ALU/B.SHF/ALU,DK/SHF"

D_R[].AND.KI[]

D&RC[]_PC

D_RC(SC)
D_R[J(FRAC)
D_RLOG

D_RLOG.RIGHT

D_R(PRN+1)

oLe

.SHFfALU.DK/SHF"

CRAIMN

O_Q-PCsv

“BMX,PC,ALU/B,
DX, SHF ,SF5.R/WRITE.RC,SP
SHF/ALU
O.RC/@1*%
,
"SPQ/LOAD.LC.SC,BW
LC,ALU, B,SHF/ALU,DK,/SHF"
N.
“SPO.R/LOAD.LAB.SPO.RA3/&1 ,ANVX/LA,ALU/A,SHF/ALU,DK/SHF . FL®

“BMX/0,MSC./READ.RLCG,
B, SHF/ALU,DK/SHF"
ALU,

"BMX,/0.MSC/READ.FLCG,AL
"B, 5HF, RIGHT , DK,/ SHF"
U

"SPO.AC/LOAD.LAB,SPO.ACN
1, AMX /LA, ALU/A, SHF/ALU,DK/SHE"
,/SRN+
“SPG.AC/LOAD.LAB
SC,AMX ‘LA, ALU/A,SHF/ALL,DK/
,SPC.ACN
SHF"
,

D_R(5C)
O_R(SPI+1)

“SPO.AC/LUAD.LAB,SFO.ACN, SP1+1,AMX/LA,ALU/A,SHF/ALU,DK/SHE"

D&VA_ALUY

"VAK/LOAD,SHF/ALU,DK
/SHE"

D&VA_D-K[ ]

"TRAMX /D, AMX,/ RAMX ,KMA /&1, BMX KMX , ALU/A~B, VAK/LOAD,SHF/ALU,
DA /SHF "
"RAMX /D, AlMX/RAMX ,B¥VX/LVAK/LOAD,
C,ALU/A
SHF/ALU,DK/SHF"
+B,

D&VA_D+LC

D&VA_D+Q

“D_D+Q,VAK,/LCAD"

DEVA_LA

“AMX/LA
A, VAK/LOAD,SHF/ALU,DK/
,ALU,
SHF"

DE&VA_LS

"BMX/LB,ALU/E,VAK/LCAZ
ALY,,SHF,
DK/SHF"

D&VA_Q
D&VA_Q+LB.PC

;EALU_...

"SPJ.R/LOAD.LAB,SPO.RAB/&1,AMX /LA, KMX/€2,BMX/KMX, ALU/AND, SHF/ALU, DK/SHF"

THRU

EALU_D(EXP)
EALU_FE

EALU_K[]
EALU_R[](EXP)

"RAMX/Q, AMX,/RAMX
VAK,
,ALU/A,
LOAD,DK/Q"

“RAMX,’Q,AMX/RAMX, BMX/PC.CR.LB,ALU/A+B,VAK/LOAD, SHF/ALU, DK/ SHF"

FE_...

"RAMX/C.,AMX/R
EEMX, AMX .EXF,
AMX,
EALU/B"
“EBMX/FE,EALU/B"

"KMX, ®1,EBVX/KIMX,EALUB"
,
"SP0.R,LOAD.LAB,SPD.RAS,/@1,AMX/LA,EBMX/AMX.EXP,EALU/B"

EALU_SC

“EALU/A"

EALU_SC+FE

“EBVX/FE,EALU/A+B"

EALU_SC-FE
EALU_SC+K[]

TRMX, @1

EALU_SC.ANDNOT.KI ]

"KMX/@®1,
/KMX ,EALL/ANDNOT®
EBMX

“ESMX/FE,EALU/A-8"
EEMX/KMX ,EALU/A+B"

(LNOJ) SNOILINIZIA a1314 WOY TOHLINOD J11LSONOYIAOUIIN

D_Q.0R.RC[)

D_Q+PC

YKIX,/ @1, EBMX/KNY. ,EALU/A-B"

FE_O(A)

"AMX/RAMX.OXT,DT/LCNG.
EBMX/AMX . EXP,EALU/B, FEK/LOAD"
"RAMX, D, AMX/RAMX , ESNX, AMX . EXF,EALU/B,FEK/LOAD"

"EALU/A,MSC/LOAD.STATE"

FE_D(EXP)

LIE

FE_EALU

"FEK, LOAD"

FE_KI[]

"KMX /@1, EBMX/K!MX , EALU, S, FEK, LOAD"

FE_LA(EXP)

“AMX,/LA,EBMX/AYMX.EXP
,EALU/B, FEK LOAD"

FE_NABS(SC-LA(EXP)) "AMX/LA,EBMX/ANX.EXP,EALU/NABS.A-B,FEK/LOAD"
FE_Q(EXP)
TRAMX/Q. AMX /RAMX , EBLiX/ ANMK.EXP ,EALU/B, FEK/LOAD"
FE_R[J(EXP)
"SPO.R,/LOAD.LAB,SPO.RAS/&1,AMX,/LA,EBMX/AMX.EXP,EALU/B,FEK/LCAD"
FE_SC
“EALU/A,FEK/LOAD"
FE_SC.ANDNOT.FE
“EBMX/FE,EA_U,
ANONOT, FEK/LOAD"
FE_SC.ANDNOT.K([
]
TKMX,/@1, EEMX /KMX , EALU/ANDNOT,
FEK/LOAD"
FE_SC+1
"EALU/A+1,FEK/LJAD"
FE_SC+FE
“EBMX/FE,EALU/A+B,FEK,'LOACTM
FE_SC-FE
"EBMX,/FE,EALU/
4B, FEK/LOAD"
“KMX /@1, EBMX KMX,EALU, B, FEK, LOAD,SMX/EALU,SCK/LOAD"
FE&ESC_K[)
"KMX, @1, EBMX /KA, EALU/A+B, FEX,/ LOADTM
FE_SC+K[
]
FE_SC-K[
]
YKMX /21, EBMX/KWX,EALU/A=B,
FEK, LOADY
FE_SC+LA(EXP)
"AMX /LA, EEMX/AMX.EX?,EALU/A+B,
FEK,/LOAD"
FE_SC~LA(EXP)
"AMX/LA,EBMX/AMX.EXP,EALU/A=5,
FEK,/LOAD"
FE_SC.OR.K][]
“EALU/OR, EBMX/KMX, KMX,/@®1,FEK/LOAD"
FE_SC-SHF.VAL
“EBMX,/SHF.VAL,EALU/A-B,FEK/LOAD"
FE_SHF
. VAL
"EBVMX/SHF.VAL,EALU/B,FEK/LOAD"

110_...

THRU

ID[])_D

LC_

“CID/WRITE.KMX,1D.ADDR/®1*

1D_D&NO.SYNC

"CID/WRITE.KMX,ADS/IBA,KMX/SP1.CON*

10(SC)_D

“CI1D/WRITE.SC*

K{]

"KMX/@1"

]
LA_RA[

"SPO.AC/LOAD.LA,SPO.RAB/B1"

ID_D.SYNC

“CID/WRITE.KMX,ADS/IBA,XMX/SP1.CON,ACF/SYNC"

LA_R(DST)&LB_R(SRC)
LA_R(SP2)&LB_R(SP1)
LAB_R1&RC[]_0O

"SPO.AC/LOAD.LAB,SPO.ACN11/DST.SRC*
"SPO.AC,/LOAD.LAB,SPO.ACN/SP2.SP1"

"ALU_O(A),LAB_RIERC[{®1]_ALU"

LAB_R1SRC[]_ALU “SPO.R/LOAD.LAB1.WRITE.RC,SPO.RC/®1,SHF/ALU"

(LNOJ) SNOILLINI43d 7314 NOY TOYLNOD JLLSONOVIAOUHIIN

EALU_SC-K[
]
EALU_STATE

LAB_R(DST)
LAB_R(SC)
LAB_R(SP1)

"SPO.AC/LOAD.LAB,SPC.ACNT1/DST.DST®
“SPDO.AC/LDAD.LAS,SFO.ACN/SC®
“SPC.AC/LOAD.LAB,SPO.ACN/SP1.SP1"

LC_RZ[)

“SPO.R/LCAD.LC,SPC.RC,/
31"

LC_RC{]&R1_D

LC_RC[1&R1_LA-KI[]

"ALU_D,LC_RC[®@®1]&R1_ALU"

“ALU_LA-K[®2],LC_RC{®1]}6R1_ALU"

LC_RC(53C)
LC_RC[]J&R1_ALU

“SPO/LOAD. LC.SC”
"SPO.R/LOAD.LC.WRITE.RAB1,SFO.RC/@1,SHF/ALU"

LC_RC[]&R1_LB

“ALU_LB,LC_RC[oet]&%1_ALU"

(AR

LC_RC[{ JSR1_(LA+LB).LEFT "AMX/LA,BMX/LB,ALU/A+B,SHF/LEFT,SPC.R/LOAD.LC.WRITE.R:51,5FD.RC/@1"
LC_RC[ J8R1_(LA-LB).LEFT "AMX/LA,EMX/LB,ALU/A-B,SHF/LEFT,SPO.R/LOAD.LC.WRITE.RAB1,SPO.RC/@®1"
LC_RC[)&R1_LA+K[]
"SPO.R/LOAD.LC.WRITE.RAB1,SPO.RC/@1,SHF/ALU,ALU/A+3,
MAK /LA, BMX/KMX , KMX/@2"
LC_RC[]&r1_Q
;PC_...

THRU

"SPQ.R/.0AD..C.WRITE.RAB1,SPO.RC/®1,SHF/ALU,ALU/A
AMX/RAMX ,RAMX/Q"
PC&VA_...

PC_PC+1
PC_PC+2

PC_PC+4
PC_PC+N

"PCK/PC+1"
“PCA,/PCy2"
"PCK/PC+4"
"PCK, PC+N"

PC_R+PC

"ALJ/A+8,VAK/LOAD,PCK/PC_VA,BMX/PC,AMX/RAMX
,RAMX/Q"

PC_VA

“PCK/PC_VA"

PCAVA_ALU

"WAK, LOAC,PCK/PC_VA"

PC&VA_D

"RAMX /D, AMX/RAMX ,ALU/A,VAK,/LCAD,PCK/PC_VA®"

PC&VA_D.OXT[]
"TRAMX/D.,AMX/RAMX.OXT
,OT ®: ALU A,VAK/LDAD,PCK/PC_VA"
PC&VA_D.OXT[ }+PC
"RAMX /D, AMX /RAVC.CXT,DT @1,8BMX/PC,ALU/A+3,VAK/LOSZ ,PCK/FC_VA"

PC&VA_D.SXT[
J+PC
PC&VA_D+K]
]
PC&VA_D-K][
]
PC&VA_D-PC
PCEVA_K]
]
PC&VA_PC
PC&VA_Q

PC&VA_Q-D

"RANX/D,AMX/RAMX.SXT,DT/®1,5MX PC,ALU/A+B,VAK,/LCAD,PCK/=C_VA"
PRAVX/DLAMX/RAMX
KM @1 ,8M) WX, ALU/A+B,VAK/LOAD,PCK/PC_VA"
CRAMX, D, ANX/RAMK , KVMX, BT, BMX,»¥X,ALU,/A-B,VAK/LOAD,PCK/PC_VA"

CRAVX/DLAVX/RAMX,
BN /PC,ALU, A-8, VAK/LOAD,PCK/PC_VA"
PKAMX/ B BVIX/KMX L AL B, VAR, LCAD ,FCK/PC_VA"
"BUMX/PCL,ALU/B,VARK/LCAD,PCA/FC_VAY
YRAMX/Q,ANX/RAMX
,ALL /A, vAK, LOAD ,PCK/PC_VA®"
DRAMK QL AVX/RARX ,REVX, D,EVX, REVX,ALY/A-B,VAK/LCAD
,PCK/PC_1 A"

(LNOD) SNOILINIZ3A a7314 WOYH TOHLNOD J1LSONSDVIAOHIINW

“"SPO.R;LOAD.LAB1.wWRITE.RC,SPO.RC/@1,SHF/RIGHT2"
LAB_R1&RC[
] _ALU.RIGHT2
LAB_R1&RC[] TD.OXT[]+K[] “ALU_D.OXT[{®2]+K(@3],LAB_R1&RC[@1]_ALU*
LAB_R1&RC[
] _D+LC
"ALU_D+LC,LA3_R1SRCI&®1]_ALU"
"ALU_Q~K[{®2],LAB_R1&RC[EG1]_ALU"
LAB_R1&RC[
] TQ-Ki]
,DT/LONG, BMX/RBMX,RBMX/D, SHF/ALU*
LAB_R1&RC[
] “0-D "SPD.R/LOAD.LAB1.WRITE.RC,SPO.RC/®1,ALU/A=B,AMX/RAMX.OXT
"ALU/A+B+1,AMX,RAMX.0XT,DT/LONG, BMX/LC,SPO.R/LOAD.LAB1.WRITE.RC,SPO.RC/@1,SHF/ALU"
LAB_R1&RC[
] ~o+LC+
“SPD.R/LOAD.LAB,SPC.RASB/@1"
LAB_R[]

"RAMX/Q. AMX /RAMX , KMX, B1, BVIX/KMX, ALU/A~B,VAK/LCAD
,PCK/PC_Va"
FRAMX,/Q, AMX /RAMX , 350X /PC, AL/ A+, VAK/LOAD, PCK,/PC_VA"

“RAMX/Q.AMX, RAMX.SXT . DT @1,BMX/PC,ALU/A<E VAK/LOAG,BCK/PC_VA"
PC&VA_Q.SXT[
J+PC
PC&VA_R[].ANDNOT.K]] “SFO. R/LOAD.LAB,SPC.RAB /&1 ,AMX/ LA, KMX/®2,BMX/hnMX,ALL /ANDNOT,VAK/LOAD,PCK/PC_VA*
PC&VA_RC[
]
"SPO.R/LOAD.LC,SPO.RC/®1,BMX/LC,ALU/B,VAK/LOAD,PCK/PC_VATM

"PCK/PC_1BA"

PC_VIBA

'Q.0...

THRU Q_D...

Q_0

"QK. CLR"

Q_0-K[]

CAMX/RAN

Q_0-D

Q_0-LC

Q_O+MASK+1

€le

Q_O0+PC.RLOG

Q_0-Q
Q_ACCEL&SYNC
Q_ALU
Q_ALU.LEFT
Q_ALU.LEFT2

YAMX, RAMX . OXT,CT/LCNG, I3%X/D,EVX/RBMX,ALU/A-B,SHF/ALU,QK/SHF"

LOXT,DT/LONG,KMX, @1,BVX/KMX,ALL/A-8,SHF/ALU,QK/SHF"

"AMX, RAMX . OXT,DT/LONG,SMX'LC,ALU/A-B,SHF/ALU,QK/SHF"
"ANMX/RAMX
. OXT,DT/LONG,
BYMX, MASK ,ALU/A+B+1 ,SHF/ALU,QK/SHF"
YAMX, RANX . OXY,.DT/LONG,8WX/PC,ALU/A+B.RLCG,SHF/ALU,QK/SHF
"

"AMX/RAVIX .OXT,DT/LONG,R3MX/Q,BNX/RBMX,ALU/A~-B,SHF/ALU,QK/SHF"

"QK/ACCEL., ACF/SYNC"
"SHF,/ALU,JK/SHF®
"SHFLEFT, QK/SHF®

"SHF,ALU.DT,DT/LONG,QK/SHF"

Q_ALU.RIGHT

"SHF/RIGHT ,QK/IHF*

Q_ALU.RIGHT2

“SHF/RIGHT2,0UK,/SHF"
"SHF/ALU,QK/SHF.FL"

Q_ALU(FRAC)

Q_D

“QK/’D“

“REWMX/D,BMX/RBVMX ,ALU/B.,SHF/ALU,GK/SHF.FL"
Q_D(FRAC)(B)
D.OXT[]
"RAMX/D,AMX/RAMX
. CXT ,DT/®1,ALU. &, SHF/ALU,QK/SHF®"
Q o)
Q ) LOXT[]+K[].LEFT PRAMX DL, AMX S RAMALCXT DT /&1 [\ /@2, BMX/ KMX, ALU/A+B,SHF /1 LEST ,QK/SHF"

Q
Q

D LAND.KI]

"RAMX /D, ANMX/RAMX ,KMX /21, EVX. AMX,ALU/AND,SHF
/ALY QK/SHF"

TRAMX /D, AMX . RANMX, RN @1, BVX/KMX,ALU/AND,SHF
/RICHT ,Qn ' SKF"
D.AND.K[].RIGHT
YRAMX /D, A4, RAMX, KiVX, &1, BMA/RKGX VALU/AND ,SHF /RICHT 2, S0, SHEY
D.AND.K[].RICHT2
,5~F /ALY, QK /SHF"
D.ANDNOT.RC[
] “RAMX/D,AMX,RAMX,SPO.R/LCAD.LC,3PO.RC/21,BMX,/LC,ALU/ANDNIYT
"RAVMX /D, ANX/RAMX,SPO.R/LCAD..C,.SPO.RC/G1,BMX/LC,ALU/AND,
SHF /ALU, QK /SHF"
D .AND.RC[
]
D EC.CON
"QK,/DEC.CON"
VRAMX/D L AMX/RAMX, KMX /@1 ,BWX, KVX,ALU/A+B,SHF
/ALY, QK/SHF"
D

Q
Q

Q
Q
Q

YRAMX /D, AX /RAMX , AMX /@1, BX, KWMX,ALU/A+B,SHF,/LEFT,QK/SHF"
"RAMX /D, AN IX/RANMX KMK /@1, BVX, RMX,ALU/A-8B,SHF/ALU,QK/SHF"
"RAMX/D,AVX /RAVX , BYY(,/LS,ALU/A+8B, SHF/ALU,QK/SHF"
YRAMX /D, AYX/RAMA, BidX /LT ,ALU, A-B,SHF/ALU,QK/SHF"
"RAVA/D,AMX/RANMA,ALU/A,SHF/LEFT3,QK/SHF"
“RAMX /D, ARX/RATIX ,KMX /@1, BYA KX, ALU,/CR, SHF/ALU, OK/SHF"

(LNOD) SNOILINI43Aa @T314 WOYH TOY.LNOD J1LSONDVIAOHIIW

PC&VA_Q-K[
]
PC&VA_Q+PC

"RAMX /D, AMX, RAMX,SE0.R,/LOAL.LC,5P0.RC/@1,BMX/LC,ALU/OR,SHF
‘ALU,QK/SHF "
“RANMX/D,ANVX,/RAMX,REAX,Q,EVX/7BVX,ALU/A~B,SHF/ALU,QK/SHF"
YRAMX /D, ANX/RAMX ALY /A, SHF/RIGHT ,QK/SHF"

D.RIGHT
_D.RIGHT2

_D.SxT{]

"RAMX/D.,AMX/RAMX .SXT,CT/21,ALU,; A,SHF/ALU,QK/SHF*

_D.XOR.Q
Q_IB...

“OK/SHF ,ALU/XOR, AMX
THRU

Q. IB.BDEST
Q_ I1B.DATA
Q_ 10[]

o_ ID(SC)
Q _K[]

145

PRAMX /D, AWMX, RAMK ,ALU /A, SHF,RIGHTZ,QK,/SHF"

RAMX,RAMX /D, BMX/RBMX RBMX/Q,SHF/ALU"

Q_PC...

“IBC/BDEST,QK/ID, MCT/ALLCW.IB.READ"

"QK/ID.MCT/ALLCW.IS.READ"
“CID,;READ.KMX,ID.ADLR,/®1,QK,/1D"
“"CID/READ.SC,QK/ID"
“KMX, ®1,BMX,/RMX,ALU,/E,SHF/ALU,
GK/SHF"
YKMX, ®1,80X/KMX,ALU,/B,SHF
/ALL.CT ,DT/INST.DEP,QK/SHF"
YKMX, @1, BUX/KMX,ALL
/B, SHF /RIGHT ,QK/SHF

Q- K[].CTX
Q- K[].RIGHT
YKMX /@1, BVMX/KMX,ALU
3, S=F RIGHT2,QK/SHF"
Q_ K[].RIGHT2
Q_LA
“AVX/LA,ALU/A,SNF,//ALU.
QA SHF®"
Q_LA.AND.K[}
CAMX, LA, KMX/®1,50X #»MX,ALU,/AND,SHF/ALU,QK/SHF"
Q_LA.ANDNOT.RCI]
"AMX/LA.SPO.R,/LGAD.LC,SPO.RC,/@®1,310¢/LC,ALU/ANDNOT
, SHF /ALU,QK/SHF "
Q_LA+K[ ]
CAMX/ LA ENX /@1, BVX,
nMX,ALU,/A+E, SHF/ALU,QK,/SHF"
Q_LA-K[]
AMX, LALKNX /@1 BMX, KM, A J/A=C SHF/ALL, QK /SHF"
Q_LA+Q
CAMX/LAL,RPNXQ,BUX REMX,ALU/A+B, SHF/ALU QK/SHF"
Q_LB
"E X,LE ALU,/B,SHF,/4.U,QK, SHF"
“BMX/LC,ALU/B,SHF/ALUY, QK SHF"
Q_LC
Q_NOT.Q
"RAMX/3.,ANX/RAMX,ALU/NOTA,SHF /ALU,QK/SHF"

Q_NCT.R[]

Q_PACK.FP

Q_PC

1Q_Q.

“LA_RA[@1],AMX/LA, A'U/\uTA Q_ALU"

“BMX/PACKED.FL, ALU/B SHF/ALU,QK/SHF"

"8MX/PC,ALU/B,SHF/ALU,QK/SHF*

THRU Q&VA_

Q_Q.0xXT[]-K[]

"RAMX/Q.AMX/RAMX.OXT ,DT/@1,KMX/82,BMX/KMX,ALU/A-B,SHF/ALU,QK, SHF"

Q_Q.0XT[].O0R.D
Q_Q.AND.K[]

SHF/ALU,QK/SHF"
,RBMX, D, BMX/RBMX,ALU/OR,X.0XT
,AMX/RAM
DT /@1
"RAMX,/Q
TRAMX/Q ., ANX,/RAMX , KMX /&1, 3MX/AMX , ALU/AND, SHF /ALU,QK/SHF "

Q_Q+D

MX,
ALU/A+B, SHF/ALU,QK/SHF"
YRAMX/Q.AMX/RAMX,RBMX /D, EMX/RE

Q_Q.OXT[].LEFT

“RAMX,/Q.,AMX/RAMX.OXT
,DT, /@1 ,ALU/A,SHF/LEFT,QK/SHF"

,QK/SHF"
/RIGHTD,SHF
CRAMX/Q, AMX/ RAMY,KVMX /81, BMX/KMX,ALU/AN
Q_Q.AND.K[].RIGHT
/ALU,QK/SkF "
/RAMX
D, BMX, RSMX ,ALU/ANCNOT,SHF
Q.,AMX
,RB¥X,
“RAMX/
Q_Q.ANDNOT.D
="
,BMX,
KX, ALU/ANDNOT,SHF/ALU,QK/SH
“RAMX/Q,ANMX/RANX,KiA/®1
Q_Q.ANDNDT.K[]
Q.Q. AND RC[]
YRAMX/Q,AMX/RAMX,SFO.R/LCAD.LC,SPO.RC/®1,BNMX/LC,ALU/AND,
SHF/ALU,QK/SHF"
“RAMX,'Q.,AMX/RAMX,REMX,; D, BMX/FBML,ALU/A-B,SHF/ALU,QK/SHF"
Q_Q-D

(LNOJ) SNOILINIZ3AQ @1314 NOY TOHLNOD J1LSONSDVIAOHDIW

D.OR.RCI[]
D-Q

"RAMX/Q,AMX /RAMX ,R3MX,/D,BVX/RBYX,ALU/A-B~-1 ,SHF/ALU,QK/SHF"

"RAMX/Q, AMX/RAMX,ALL/A,SHE/ALY, OK/SHF FL"

Q_Q(FRAC
(B)
)

Q_Q+K[]
Q_Q-K[]
Q_Q-K[]-1

Q_Q+LC
Q_Q-LC
Q_Q-LC-1
Q_Q.LEFT
Q_Q-MASK-1

"RAMX/Q,AVX/RANMK, KMX /@1

,BMX/nWMXx,ALU/A+B,SHF/ALU,QK/SHF"

"RAMX/Q,AMX/RAMX, KMX /&1, EMX KN, ALU/A~B,SHF/ALU,QK/SHF*®
YRAMX,/Q., AMX/RAMX, KMX /@1, BMX/KMX,ALU/A-B-1,SHF/ALU,QK/SHF
"
YRAMX, G, AMX/RAMX , BMX/LC,ALU/A+8,SHF
/ALY, QK/SHF"

"RAMX/Q.AVMX/RAMX,BMA/LC,ALU/A=B,SHF,/ALU,
QK/SHF"
"RAMX, Q,AMX/RAMX,BMX/LC,ALU/A~8=1,SHF/ALU,QK/SHF"

“QK/LEFT"

"RAMX/Q,AVX/RANMX,
BMX /MASK ,ALU/A-B~1,SHF/ALU,QK/SHF*

Q_Q.0R.K[]

“RAMX/Q, AMX/RANX , KM /@1, BMX, KMX, ALU/OR, SHF/ALU, QK/SHF"

Q_Q.0RNOT.MASK

"RAMX/Q, AMX/RAMX , BNMX /MASK,ALU, ORNQT ,SHF /ALU,QK/SHF"

Q_Q+PC

"RAMX

Q_Q.RIGHT

“QK/RIGHT"

Q_Q.RIGHT2

W_Q.5XT[]

Q_RI[]

SLE

YREMX/Q,BWMX/RB8MX,ALU/B,SHF/ALU,.QK/SRF.FL"

3, AWMX,RAMX , BMX/PC,ALU/A+B,
SHF/ALU, QK/SHF "

"QK/RIGHT2"
PRAMX/Q, AMX/RAMX . SXT,DT /@1 ,ALU/A,SHF/ALU,QK/SHF*

"SPO.R/LOAD.LAB,SPC.RAB/St
,ANX LA,ALU/A,SHF/ALU,QK/SHF"

Q_R[].AND. K[]
"SPO.R/LCAD.LAB,SPC.RAB,/®1
,AMX /LA ,KMX/GZ,BMX/KMX, ALU/AND,SHF ‘ALU,QK,/SHF"
Q_R[].AND.K[ ] .RI GHT
"SPO.R/LOAC. LAB,SPO.RAS ©1,AMX,/ LA, ALU/AND, BMX/KMX , KX,/ @2, SHF/RIGHT, QK/SHF "
“3PD.R/LOAD. LAB,SBC.RAZ, ®1,AMX/LA,KMX,/ 62, BMX/KMX , ALU, ANDNOT, SHF/ALU, QK/SHF"
“$P3.R,LCOAD.LC,SPO.RC,/€1,BMx/LC,ALU/B,SHF/ALU,
QK/SHF"

"SPQ.R/LCAD.LC.SFO.RC,®1.B%X,/LC,ALU/B,SHF/ALU,QK/SHF.FL"
"SPO.R/LCAD.LAZ,SPC.RAB/@1,ANX,/LA,ALU/A,SHF/ALU,QK,/SHF.FL"

Q_R(PRN).ANDNOT. Q
"SEO.AZ/LCAD.LAB,3P0.ACN/PRN,ANX/LA,REMX/Q,
BMX/RI¥X , ALL,ANDNOT . SHF/ALU,QK/SHF"
Q_R{PRN+1)
"SPO.AC/LCAD.LAB,SQO.ACN/FRV+2.AMX/LA,ALU/A,SHF/ALU.QK/SHF"
Q_R(PRN+1).AND.Q
"SPO.AC/LOAD.LAS,5PS.ACN/PRN+1 ,AMX/LA,RBVX/Q,BMX, /RSVMX,ALU/AND,SHF/ALU,QK/SHF"
Q_R{SRC'1).AND.K (]

“SPO.AC/L0AD.LAB,SFO.ACN11/SRC.GR.1,AMX/LA,KMX/@1,EMX/ KMX,ALU/AND,SHF /ALY, QK/SHF"

Q_sC

YALU/B, BAX,KNX

QEVA_ALU

"VAK,/LCAD,SHF/ALU,GK
/SHF"
"RAMX/D, AMX /RAMX ,ALU/A,VAK/LOAD,.SHF/ALU,QK/SHF"
"RAMX /D, AMX/RAMX, BMA/LC,ALU,/A+3,VAK/LCAD,SHF/ALU,QK/SHF"

QuVA_D

Q&VA_D+LC

Q&VA_LA
Q&VA_Q+LB.PC

iR[]_0...THRU

,KNMX 'SC, SHF /ALY, QK /SHF
"

"AMX/LA,ALU/A,VAK/LCAD,SHF/ALU,QK/SHF*"
“RAMX/Q, AMX /RAMX , BMX /PC.OR.LB,ALU/A+B,VAK/LOAD,
SHF/ALU, QX ,/SHF"
R] ]_PACK.FP
"SPO.R/WRITE.RAB,SFO.RA3/31, AMX/RAMX.OXT,DT/LONG,ALU/A, S*F

TAVX S RAMX.CXT,DT,/LONG,fBf"“ BVX/RBMX,ALU/A-8B,SHF/ALU,SPZ

E.RAB,SPO.RAB/G1"

"AMX,RANMX.OXT,DT/LONG, KWL 72 Pv('KVX ALU/A=8,SHF/ALY,SPO,

RAB,SPJ.RAB/®1"

VAMX RAMX.OXT,DT,/LONG, EMX,LB,A J/A-B,SHF/ALU,SPO.R/WRITE.

RAB/G1"

(LNOD) SNOILINIZ3A a7314 WOY TOHLNOD J1LSONDVIAOHIIW

Q_Q-D=-1

Q_Q(FRAC)

“AMK/RAMX.OXT,DT/LCNG,EMX'hmx,nvx/.1.ALU/A‘B.SHF/ALU.SPO.Q/leTE.RAB.SPO.RAB/@?“
"SHF,ALU.SFPO.R/WRITE.RA2.SFO.RAB/G1"
LEFT"
O.RAZ
31 ,SHF,
"SPO.R,/WRITE.RAB,SF
"SHE,/RIGHT,SPO.R/WRITE.RAS,S0.RAB/@1"

ey
e

,RAMX
AMX/RAMX ,ALU/A,SHF/ALU"
FO.RAB/&1
“SPO.R/WRITE.RAB,S/D,
/@2, SHF /ALU"
RANX,/ D, BMX /L 1X nhX RAS,
AE,SP0.
/@1 ,ALU/AND, AMX/RAMX,
"S20.R/WRITE.R
.
K, L U A+B, SHF/ALUY
S2.RAZ
, KNX /@2, BMX/K"
.RAE,S
D1, RANMX /D, AMX/RAMX
"SPO.R/WRITE

RAS
/€2, BMX /K~ , AL,/ A-B,SHF/ALU"
AB,SFO.
21 ,RAVX/D, AMX/RAMX KVMX
“SPO.R,WRITE.R

e ()

“SP3.R WPITE.RAB,SPD.RAB, R6,RAMX /D, AMX/RAMX ,KMX,/ @1, BMX/K'" <, ALU/A+B.RLOG, SHF/ALU"

“ALU_D-LC-1,R{@1]_ALu"

e e e

SHF "ALU"
,RANX/D,BMX/LC .RA2
AB,SP2.
G1,ALU OR,AMX/RAMX
"SPO.R,WRITE.R
Blix, PACRED. FL,SHF/ALU"
/@1,ALU/OR,
AMX/RAMX ,RAMX . T,
"SP0.R/WRITE.RAS,SP0.RAE
Q,
ALG /0%, SHF/ALU"
X,REVX/
BMX/REV<,
“SPO.R WRITE.RAB,SPI.RAS 81,RAMA/D, AMX/RAM
AU,/ A+B,SHF/ALU"
,
FC.RAB
,REMX,'Q, BMX/RTIX
.RAB,S
/&1, RAVX /D, AMX/RAMX
“SPI.R/WRITE
_U/A-B,SHF/ALU"
A
BMX/RIVX
/Q,
REMX
,
RAMX
AMX,
"SPO.R WRITE.RAB,SEG.RAB, 31.RAMX/D,
ALl /A+B+1,SHF/ALU"
, RENIX/Q, BMX/RENMX, 1,R5X/D,
SPC.RA3/@
AMX, RAMX
“GPO.R,/WRITE.RAB,

e e

PBMX /KMX , KMX,@®2.ALU, B,SHF /ALU,5P0.R/WRITE.RAB,SPO.RAB/@1"
,
LA, ALU/A,SHF/ALU"
&1 ,AMX,,SFO.RAB
"SPO.R/WRITE.RAB

WRITE
. RAB,S5C.Fa2,€
WARIX/ LA, BYIX/KMX, KMX 32 ,ALL/AND,SHF/ALU,S5PO.R/
“AMX/LA,RBMX/D,3MA/REVMN ,ALU/A+B,S5HF/ALU.SPO.R, WRITE.RAB,S-C

qlLg

X
A8 ,5PJ.RAZ,/B1"
G,BY
SPO.R/WRITE.
/LON
/A+E+1,SHF /ALY,
. LE ALT,DT
WANX RAYMX.OX

“AMX/RAMK.OXT,DT/LGNG,RBfix/O,SVX/RBMX,ALU/A-B.SHF/ALU.SPU.R/mRITE.RAB.SPO.RAS/O1"

_LA+K[ T+1

_LA=K[]

}_LA+K[].RLOG
R[]_LA-K[].RLOG
R6_LA+K[ ].RLOG
R6_LA-K[].RLOG
RIV_LA+LC
RIJ_LA+MASK+1
R[] _LA-MASK=-1
RI{]_LA.OR.D

57
WAMX, LA, REMX/D, EMA, RBMX, ALU, A+E+1,SHF /ALY, SPO.R/WRITE.RAZ.
WANX, LA, RBWMX/D, BMX,'R3MX, ALY, A~B,SHF/ALU,SPO.R/WRITE.RAB,5-3
/WRITE.RAB,SPU.R
WAMX . LA, EMX,/KMX, RMX ‘@2, AL/ A+B,SHF/ALU,SPO.R
KMX 32, ALU/A+B+1,R[®1]_ALU"
WAMX /LA, BVX/KMX,
WAMX, LA, BYX/KMX , KMX /32 ,ALU/A-B,SHF/ALU,SPO.R/WRITE.RAB,SFD.RAS @1

“AMX/LA,EVX/KM¥,KMK/?Z,ALU/A+B.RLDG,DT/LONG,SHF/ALU.SPO.? WRITE.RAB,SPO.RAB/®1"
"
NG,SHF
/ALU,SPO. R,/ WRITE.RAB,SPO.RAB/@1
WATAK - LA L BMX/KMA, hMX, 32, ALU/A-B.RLOG,DT/LO
FAMX, LA, BdX/KWMA, KMX /@1 ,ALU/A+B.RLOG,DT/WORD,SHF/ALU,SPO.% WwRITE.RAS,S5P0.RAB/R6"
”AMX/LA.B”X/KMX,KMX/@1,ALU/A—B.RLOG.DT/WDRD.SHF/ALU.SPO.Q,NRXTE.RAB.SPO.RAB/RG“
nAUAX - LA,BMX/LC,ALU/A+3,5HF, 4LU,SPO.R/WRITE.RAB,SPC.RAB/@1"
"AMX LA, BVX,/MASK,ALU/A+B+1 ,R[@1]_ALU"

‘ALU"
WALU/A-B—1,AMX LA ,CUX,/MASK,SPO.R/WRITE.RAB,SPO.RAB/@1,SHF
@1
“AMX/LA,RBMX/D,BVX, RBMX,ALU OR,SHF/ALU,SPO.R/WRITE.RAB,SFG.RAB

R{ J_LA_QORNOT.MASK
RIT_LA+Q

R[]_LA-Q
R{]_LB
R{]_LC

CAMX /LA, EMA MASH,ALU, ORNOT,SHF/ALU,SPO.R/WRITE.RAEZ,
SPC.RAB/@1"

WAMX/LA,REMX/Q,BEMX

@1
%3%MX, AU, A+B,SHF/ALU,SPO.R/WRITE.RAB,5°30.%4aB

SPC.RAB/@1"
,BMX,
A=8, SHF/ALU,SPC.R,/WRITE.RAB,
,RBVX/Q
BBYX,ALU,
WAMX/LA
"BMX/LB,ALU,/B,SHF/ALU,SFZ.R WRITE.RAB,SPO.RAB &1"
'@1"
"BMX LC,ALU/B,SHE/ALU,SPS.R,/WRITE.RAB,SFO.RAB

(LNOD) SNOILINIZ3a a1314 WOH TOYLNOD J1LSONOVIAOHIIN

0~-1

T e e

D VVDDVDOVDDDIVDODDDIDDIVDAVDODNDIDTDIOI

_0+LB+1

_0-Q

“BMX, LC,ALU/8,SHF,/RIGHT ,5P0.R/WRITE.RAB,SPO.RAB/®1"
TAMX, RAMX.OXT,DT/LGONG,
ALU, NCTA,R[@1]_ALU"
"RAVMX /D, AMX,/RAMX ,ALU/NOTA R[&1]_ALU"
“BMX, MASK, AMX/RAMX.OXT,DT/LONG,ALU/ORNCT,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@1"

R[]_Q

“SPO.R/ WRITE. RAB,SPO.RAB/@®1,RAMX/Q,

R[]_Q+5
R[1_Q-D
R[]_Q-D-1

"SPO.R,/WRITE.RAB,SFC.RAB/®1,ALU/A+B+1,BMX/KMX,KMX /.4, AMX /RAMX,RAMX/Q,SHF/ALU"
“SPO.R/WRITE.RAB,SPC.RAS
‘21 ,RANMX/Q, AMX/RAMX ,RBMX,D, BMX/R"“X ALU/A-B,SHF/ALU"
"SPO.R,/WRITE.RAB.SPI.RPAE '®1,ALU A=B~1,A%MX,/RAMX,RAMX/Q,BMX, REMX, REMX /D, SHF /ALU"

R{]J_NOT.Q
“RAMX/Q,AMX/RAMX,ALU/NOTA R[@1]_ALU"
R[]J_PACK.FP
"“BMX/PACKED.FL,ALU/B,SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@1"
iR[1_Q... THRU R[]_RLOG.
R[]1_Q+1

"ALU_C+Q+1 ,R[@1]_ALU"®

R[{]1_Q+K[]

"SPO.R/WQXTE.RAB.SPD.RAE‘31.QAMX/O,AMX/RAMX,BMX/K"X KMX/22,ALU/5+B,SHF/ALU"

R[I_Q-K[].RLOG

"RAMX,/G,ANX,/RAMX,
2K/ KVX, KW¥X, 82, ALU/A-B.RLOG,DT/LONG,SHF ALYU,SP0.R/WRITE.RAB,SPO.RAB/B1"

R{J_Q-K[]

“SPO.R,/WRITE.RAB,SPT.RAB @1,mAux/o AMX /RAMX, BMX /KMX, KMX/22,ALU/A-B,SHF/ALU"

R[]1_Q+LB

LLE

AMX/RAMX ,ALU/A,SHF/ALU"

"SPD.R,WRXTE.RAB.SPO.RAB,v1,ALL A+B, AMX /RAMX,BMX/LB,RAMX/ Q,SHF/ALU"

R[]_Q+LC
“SPO.R,WRITE.RAB,S+J.RAS
/&1 ,RAMY/Q,AMX,/RAMX,BMX/LC,ALU/A+B, SH=/A'U"
R[]_Q-LC
“SPO.R/WRITE.RAB,SPC.RAR
@1 RANX/Q,AMX/RANMX,BMX/LC,ALU/A-S
54F/ALU"
R{]_Q.AND.K[]
"ALU/AND,SPO.R/SRITE.PA3,3F0.RAS/S1,ANMX/RAMX, RAMX/Q, Bmx/a“x KMX/O2”
R{]1_Q.ANDNOT.K[]
"SPG.R/WRITE.RAB,SPU.RA3/®1,ALU/ANDNOT, AMX/RAMX, 2411X /Q, BMX /KN, , KMX/@2
, SHF /ALU"
R[]_Q.CR.D
"SPO.R/WRITE.RAB,SFC.RAR =1,ALU/OR, AMX,/RAMX,RAMX/Q, BMX/R:"4, RBMX T, SHF /ALU"

R[]_Q. DRNOT.K[]

"SPO.R/WRITE.RAB,SPO.RAE’$1,RAMX/O,AMX/RAMX,BMX/KMX.KMX/D2,ALU/ORNOT,SHF/ALU“

JRCLI_ o...

RC({]_D...

R[]_Q. RICHT
“ALU_Q,SHF/RIGHT,SPO.R, WRITE.RAB,SPO.RAB/O1"
R[1_RLO RIGHT 1
“BMX/0,MSC/READ.R.GG,ALU/B,SHF/RIGHT ,SPO.R/WRITE.RAB,SPO.RAB/@1"

THRU

RCI])_O

“AMX/RAMX.OXT.DT/LONG,ALU/A.SHF/ALU,SPQ.R/WRITE.RC.SPQ.RC /&1"

RC[]_0-D
RC[]_O+K[ ]+1
RC[]_O0+LC+1
RC[ J_O+MASK+1

"AMX/RAMX.0XT,DT/LCONG,RBMX/D,EMX/RBMX,ALU/A-B,SHF/ALU,SPC.R/WRITE.RC,SPO.RC/@1"
“AMX/RAMX.O0XT,DT/LONG,KMX/®2,BMX/KMX,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPC.RC/@®1"
TAMX/RAMX.OXT,DT/LONG,BMX /LC ,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@®1*
"AMX/RAMX.OXT ,DT/LONG, BMX/MASK,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/O1"

RC[J_ALU
RC[)_ALU.LEFT

"SHF/ALU,SPO.R/WRITE.RC,SPO.RC,/®1"
"SHF/LEFT.SPO.R/WRITE.RC,SPO.RC/@1"

RC[]_D
RC[]_D.0oXxT[]

“RAMX/D,AMX/RAMX ,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPC.RC/®1"
“RAMX/D,AMX/RAMX.OXT ,DT/@2,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SPD.RC/@1"

RC[]J_O+MASK+1.RIGHT2

RC{]J_ALU.LEFT2
RC[)J_ALU.LEFT3
RC{])_ALU.RIGHT

RC[J_D.AND.K[]

"AMX/RAMX.O0XT,DT/LONG, BMX/MASK, ALU/A+B+1 SHF/RIGHT2,5P0.R/WRITE.RC,SPO.RC/@1"

*"SPD.R/WRITE.RC,SPO.RC/@1,SHF/ALU.DT,DT/LONG"
*“SPO.R/WRITE.RC,SPO.RC/@1,SHF/LEFT3"
"SHF/RIGHT,SPO.R/WRITE.RC,SPO.RC/@1"

"RAMX/D,AMX/RAMX,k BMX/KMX, KMX /@2, ALU/AND,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/G1"

(LNOD) SNOILINIZ3d d1314 WOYH TOHLNOD J1LSONSVIAOHIIN

R{J_LC.RIGHT
R[]_NOT.O
R[J_NDT.D
R{ J_NOT.MASK

RC[]. D.CTX
RC[] _D+K[]
RC[] D-K[1

"RAMX /D, AlMX,/RAMX,R2%X/Q,BMX RBVX,ALU/ANDNOT ,SHF/ALU,SPO.R'WRITE.RC,SPO.RC/@1*
"REAX D, SMX/REMX,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@®1"
YRAVIX/D, 8MX/RAMX ,ALU/A,SHF/ALU.CT,DT/INST.DEP,SPO.R/WRITE.RC,SE0.RC/®1"

YRAVY /D, AMX SRAMX, BMX/KMX , kWX, 82, ALU/A+B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"

TRAMX /D, AMX,/RAMX , BMX /KMX ,KMX /82, ALU/A-B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"
YRAMX /D, AVK/RAVMX,ALU “A,SHF/LEFT ,SPO.R/WRITE.RC,SPO.RC/®1"
RC[] _D.LEFT
RC[] _D.LEFT3
“RAMX/D, AMX/RaMX,ALU/A,SHF/LEFT3,SPO.R/WRITE.RC,SPC.RC/@®1"
"RAMX/D,AMX/RAVX, KMX /@2, svx "KMX,ALU/OR,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/G1"
RCI] _D.OR.K[]
RC[] _D.OR.Q
"RAMX /D, AMX /RAMX,RBWX/Q,EX,/RBMX,ALU/OR,SHF/ALU,SPO.R/WRITE.RC,S50.RC/@1"
RC[]_D.CRNOT.K[]
"SP0.RC, &1,5P0.R,/NRITE.RC,ALU/ORNOT, AMX/RAMX,RAMX /D, BMX/KMX,KMX /@2, SHF/ALU"
“RAMX/D.AMK/RAMX.SXT,DT/@Q.ALU/A,SHF/ALU.SPQ.R/NRITE.RC,SPO.RC/@1"
D.SXT[]
RC[].

iRC[]_K...

THRU

RCI1_KI[]
RC[]I_K[1+1
RC[)_K[].LEFT2

8Le

RCII_K[].RIGHT2
RCI]_tLA

RC[J_LA.AND.K[]

RC[ J&VA_

FKMX,/ 82, BVMX/KMX,ALU/B,SHF/ALU,S®0.R/WRITE.RC,SPO.RC/@1"
"AMX, RAMX . OXT,DT/LONG,KWMX, &2 ,BVX/KMX,ALU/A+B+1,SHF/ALY,S50.R/WRITE.RC,SPO.RC/0O1"
“KMX, ®2,BMX/KMX,AL!"' 'B,SHF,ALU.CT,DT/LONG,SPO.R/WRITE.RC,SPO.RC/81"

"ALU_LA.AND.K[22].RC{®&1]_ALU"

RC{J_LA.CTX

"AMX/LA,ALU/A,SHF/ALU.DT,DT, INST.DEP,SPO.R/WRITE.RC,SPO.RC/@1"

RC[]_LA-K[]

TAMX, LALKNX/32 ,BMX,/KEMX, ALU/A-B,SHF /ALU,SPO.R/WRITE.RC,SPC.RC/G1"

RC[]_LB.LEFT
RC[]_LC
RC[]_NOT.Q
RC[ ]_PACK.FP
cfi_rc

“BIAX/LB.ALU/B,SHF/LEFT,S2C.R, WRITE.RC,SPC.RC/®1"
“8MX/LC,ALU/B,SHF/ALU,SFO.R,/WRITE.RC,SPO.RC/@1"
"RAMX,Q,AMX/RAMX,ALL/NCTA ,RC[®1]_ALU"
Y“BMX,PACKED.FL,ALU/B,S5HF/ALU,SPI.R/WRITE.RC,SPO.RC/B1"
"BiAX,/PCL,ALU/B,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"

RC[]_LB

RC[]._Q

"BMX/LB,ALU/B,SHF,ALL.SP2.R,/wWRITE.RC,SPO.RC/@1"

RAMX,/Q.AMX/RAMX ,ALU/A,SHS/ALU,SPO.R/WRITE.RC,SPDO.RC/@1"

RC[1_Q.0xT[]
“RAMX/Q.,AMX/RAMX.OXT ,DT/®2,ALU/A,SHF/ALU,SPO.R/WRITE.RC,SFO.RC/@1"
RC[]_Q.AND.K[]
“"RAMX/Q,AWX/RAMX,BW(/KMX,
KMX, 82,ALU/AND,SHF/ALU,SPO.R/WRITE.KC,S5PO.RC/@1"
RC{]_Q.ANDNOT.K[!
YRAMX/Q, AMX, RAMX, BMX, KMX , KMX /@2, ALU/ANDNOT,SHF/ALY, SF3.R/WRITE.RC,SPO.RC/®1"

RC[]_Q+1

‘ALU_O+30+1 ,RC[&1]_ALU"

RCI]_Q+K][]
RCI1_Q-K[]

"RAmx/o,Amx/anx,svx;xwx.nr(/@z.ALU/A+s.SHF/ALu,SPO.R/wR:'E.:C.SPO.RC/@1"
YRAVKAS QL ANMN/RAMX,
BMA /KN Y, KNiX &2
ALU/A-B,SHF/ALU,SP0.R/WRITE.RC,SPO.RC/@1"

RC[]_Q.LEFT3
RC[{]_Q-MASK-1
RC{]_Q+PC
[1_Q+PC+1

"RAMK, Q,LMX/RAMX,ALU
/A, SHF, LEFT3,SP0.R/WRITE.RC,SPC. RC/@,“
TRAMX/Q,AVIX/RANK, BMA/NASK, A;U/"—B—1 SHF/ALU,SPO.R/WRITE.RXC.SPC.RC/@1"
MRENK/Q,AVX/RAMX, BWMX/PC, AU,
SHF/ALU,SP0.R,/WRITE.RC,S"2.RC/ 81"
CRAMX/Q.ANMX/RAMX,BVX,
PC, ALY, A+8+‘ SHF/ALU,SPO.R/WRITE.RC,3»J.RC/@1"

[1_Q.LEFT

"“Amx,u ANX/RAMX JALU/A,SHE/LEFT,SPO.R/WRITE.RC,SPO.RC/@1"

(LNOD) SNOILINI43d a1314 WOY TOHLNOD J1LSONSVIAOHIIW

21"
RC[] _D.AND.MASK "RAMX /D ,AMX/RAMX,BUX/MASK,ALU/AND,SHF/ALU,SPO.R/WRITE.RC,SP3.RC/

RCI] _D.ANDNOT.Q
RC[] _D(3)

iR(DST)_...

THRU

R(DST) _ALU
R(DST)_D

"RAMX, D, AWMX/RAMX ,REMX/Q, BMX/KBMX ,ALU/A+B, VAK/LOAD,SHF/ALY,SPO.R/WRITE.RC,SPO.RC/P1"
"SHF/ALU,SPO/WRITE.RC.SC"
R[]&VA_..

"SHF,/ALU,SPO.AC,/WRITE.RAB,SPG.ACNT1/DST.DST"
CRAMX /D, AMX/RAMY ALU/A,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN11,/DST_OST"
"RAMX /D, AMX RAMY,.SXT, DT @1 ,ALU/A,SHF/RIGHT,SPO.AC “RITE.RAB,SPO.ACN11/DST.DST"
“SHF/ALU,SFO.AC/WRITE.RAZ SPC.,ACN/PRN"

R(DST)_D.SXT[].RIGHT
R(PRN) _ALU

R({PRN)_D
R(PRN)_D.OR.Q

C"RAMX, D, AMX/RAMX,ALU/A,SHF
/ALY, SPO.AC/WRITE.RAB,SPO.ACN/PRNTM
YRAMX/D,AVX/RAMK,REMX,/Q,
57X, REUX,ALU/OR,R(PRN) _ALU"

"RAMX /T, ANX/RANX , R3WA,/Q,EMX, RENMX,ALU/@1,R(PRN)
_ALU"
R(PRN)_D[]Q
R(PRAN)_D+K[].RLCG "RAMX/D,AMX/RAMK,AMX
/31, BMX, nMX,ALU/A+B.RLOG,DT/LONG,R: 2RN)_ALU"
R{PRN)_D-K[].RLOG "RAMX./D,AMX/RAMX,
aMX. 31 EUA/RVX,ALU/A-B.RLOG.DT/LONG,R PRN)_ALU"
"KMX/®1 . BMX/KMX,ALL,8,.SHF /ALL,SP0.AC/WRITE.RAB,SPO.ACN/PaN"
R({PRN)_KI[]

61€

CAMX/ LA KMX @1, 3MX, KivX, ALU/A+B.RLOG,DT/LONG,R(PR!
) _ALU"
R(PRN)_LA+K[].RLOG
TAMX/ LA, KMX . 81, BMA/KGX,ALU/A-B.RLOG,DT/LONG,R(PRN
I _ALU"
R(PRN)_LA-K[].RLCG
=RN"
R(PRN)
_LA[ IMASK "AMX /LA, BYX/MASK,AL./&1,SmF/ALU,SPO.AC/WRITE.RAB,5P0.ACN
R(PRN) _LA+Q
R(PRN)_PACK.FP

_Q
R(PRN)
R(PRN+1)_D
R{PRN+1)_D.OR.Q

R(PRN+1)_LC

R(PRN+1)_Q

R(SC)_ALU

R(SC)_D
R(SC)_LA+D
R(SC)_LA-D

R(SC)_LZ
R(SC)_Q

R{SP1+1)_LC

R(SP1+1)_Q
R(SP1)_ALU
R(SP1)_D

R(SP1)_K[]
R(SP1)_PACK.FP
R(SP1)_Q

R(SRC)_ALU

TAMX LA ,REMX/Q,EMX, S3MX,ALLU/A+8,SHF/ALU,SPC.AC/WRITE.RAB,5F0.ACN/PRN"
"BMX,/PACHED.FL,ALU/B,SHF ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRY"
PRAVX,/Q.ANMX/RAMX,
AL /A, SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/=RNK"

YRAMX /D, ANK/RANX ALY, A,SHF/ALU,SPO,AC/NRITE.RAB,SPC.ACN/#FIN+1"
YRAMX /D, ANX/RAMX , REMX, Q,8MX,/REMX,ALU/OR,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/PRN+1"
C.
AL/ WRITE.RAB,SPO.ACN/PRN+1"
"BNX/LC,ALU/B,SHF/ALU,SP

"RAMX /G, AMX/RAMNX AL /A, SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/FRN+1"
"SHF,/ALU,5PD.AC/WRITE.RAZ,SPO.AIN/SCH
C"RAMX, T, ANVX,/RAMX ,ALU/A,SHT/ALL,SPO.AC/WRITE.RAB,SPC.ACN/SCTM
YAMX /LA, REMX/D,BMX 'REVIX,ALU/A+5,SHF/ALU,SPO.AC/WRITE.RAB,SFO.ACN/SC"
“AlMX /LA, REMX/D,5MX /RBMX,ALU/A-E,SHF/ALU,SPO.AC/WRITE.RAB,SF0.ACN/SC"
"ALU_LC,R(SC)_AaLue

YRAMX/Q,AMX/RAMX,ALLU
/A, SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/ZC"
/SP1+1"
/ALU,SP0.
AL WRITE.RAB,SPO.ACN
“BIAX/LC,ALU/2,SHF
RITE.RAB,SPO.ACN/SPi+1"
,ALU/A,SHF,/ALU,SPO.AC/W
AMX/RAINK
/G,
YRAMX

“SHF/ALU,SP0.AC/WRITE.RAB,SPC.ACN/SP1.SP1"

"TRAVX/D,AVX/RAVX ,ALU/A,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACN/321,5P1"
5P 1"
TKMX, 81, BMX/KMX,ALU ‘8, S5F JALY,SPD.AC,/WRITE.RAB,.SPO.ACN/SP1.

"BMX,/PACKED
. FL,ALU &,5HF/ALU,SFO.AC/WRITE.RAB,SPO.ACN/SP1
. 5P
TRAMX /D, ANMX/RANK, ALU/A,SHF,/ALU,SPO.AC/WRITE.RAB,SPO.ACN/5P1
5P1"
“SHF/ALU.SPD.AC/WRITE.RA3,SPC.ACN11/SRC.SRCH

(LNOD) SNOILINIZ3A d1314 NOY TOHLNOD JILSONOVIAOHIIN

_RLOG.RIGHT
&VA_D+Q

RC(SC) _ALY

"RAMX/Q.,AMX/RAMK,ALU/A,SHF/RIGHT ,SPO.R/WRITE.RC,S5P0.RC/@1"
"RAMX/Q,AMX/RAMX,.SXT,BT/22,ALU/A,SHF/ALL,SPO.R/WRITE.RC,5FPO.RC/@1"
"BMX,0,MSC/READ.RLCC,ALU/B,SHF/RIGHT,SPO.R/WRITE.RC,SPO.RC
/@1

"RAMX, D, ANX/RAMX ,ALU/A,SHF /ALU,SPO.AC/WRITE.RAB,SPO.ACN11,53C.SRC"

"RBMX/D,BVX,/RBMX ,ALU/B,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACNT
1, 5RC.SRC"

R(SRC) _D+K[].RLEG

"RAMX/D,AMX/RAMX,
kMX, @1 ,BMX, hMX,ALU/A+B.RLOG,DT/WORD,R(S&C;_ALU"

R(SRC)_D=-K[].RLOG

"RAMX/D,AMX/RAMX

KMX, @1 ,BMX/KVX,ALU/A-B.RLOG,DT/WORD,R(SRC)_ALU"

R(SRC)_LC
R(SRC)_Q

“BMX/LC,ALU/B,R(SRC)
_ALU"
"RAMX/Q, AMX/RANX,ALU/A,SHF/ALU,SPO.AC/WRITE.RAB,SPO.ACNt11,/SRC.SRC"

R(SRC!1)_ALU

“SHF/ALU,SPO.AC,/WRITE.RAS,SPG.ACNT1/SRC.OR.
1"
"RBMX/D,BVX/RBMX,ALU/B,SHF/ALU,5P0O.AC/WRITE.RAB,SPO.ACNT
1 SR{.GR.1"

R(SRC!1)_D(B)

R[JEVA_LA+K[]
“AMX/ LA, KMX,/@2,BMX/KMX, ALYS/A+B,VAK/LOAD, SHF/ALU,SPO.R/WRITE.RAB,SPO.RAB/@1"
R[J&VA_LA-K[]
“ANX/ LA KNMX/82,BMX/KMX,A_U/A~B,VAK/LCAD,SHF/ALU,SPO.R/WRITE.RAB,SPC.RAB
/@1"
R[ ]J&VA_LA-K[].RLOG
"ANMX/LA,RNMX /@2, BMX/KMX,ALU/A-B.RLOG,DT/LCNG,VAK/LCAD,SHF/ALU,SFO.R/WRITE.RAB,SPO.RAB/O1"

R[J&VA_Q-K[]
H

-—t

SC_O(A)
SC_0-K[]
SC_ALU

oce

"RAMX/Q,AMX/RAMX , KMX /€2 ,BWX,/KMX,ALU/A~B,VAK/LOAD,SPO.R/WRITE.RAB,SPQO.RAB,/
1"

"AMX/RAMX.OXT,DT,/LONG,EBYX/AMX.EXP,EALU/B,SMX/EALU,SCK/LCAD"

“BMX/KMX , KMX /@1, AMX/RAMX.OXT ,DT/LONG,ALLU/A-B, SMX/ALU,SCK/LZAD"
"SMX,/ALU,SCK/LOAD"

SC_ALU(EXP)

“SMX/ALU.EXP,SCK/LOAD"

SC_D

"RAMX,D,AMX/RAMX ,ALU/A,SMX/ALY,SCK/LOAD"

"RAMKX/D,ANMX/RAMX.OXT
,CT, /@1, wMX, @2, BMX,/ KIIX ,ALU/A=B,SMX/ALJ,SCY/LOAD"
SC_D.OXT[}=K[]
SC_D.OXT[].XOR.K[]
"RAMX /D, AMX /RANMX.OXT ,DT,/@1,BMX/KMX,KMX
/82 ,ALU/X0OR,SC_ALU"

SC_D.AND.K[]

"RAMX /D, AVX/RAMX ,KNMX /81, BMX, KMX, ALU/AND, SMX/ALU,SCK/LOAD"

SC_D(EXP)

“RAMX,/D,AMX/RAMX
, ALU/A,SWX/ALU.EXP,S5CK/LOAD"

SC_D(EXP)
(A)

“RAMX /D, AMX/PAMX, EBMX,/AMX .EX® EALU/B,SMX/EALU,SCK/LOAD"

SC_D(EXP)(B)

YRBMX/D,BMX/RBMX,ALU/B,SMX/ALU.EXP,SCK/LOAD"

SC_D-K[]
SC_D.OR.K[]
SC_D.SXT[]

“RAMX/D, AMX/RAMX , KMX /€1 ,BMX/KMX,ALU/A-B,SMX/ALU,.SCK/LOAD"

"RAMX/D,AMX/RAMX
,KMX /@1 ,BMX/KMX ALU/OR, SMX/ALU,SCK/LOAD"
“RAMX/D, AMX/RAMX.SXT DT/@1,ALU/A,SMX/ALU,SCK/LOAD*

SC_EALU
SC_FE
SC_NABS(SC-FE)

“SMX/FE,SCK/LOAD"
“EBMX/FE,EALU/NABS.A~B,SMX/EALU,SCK/LOAD"

SC_K[]
SC_K[].ALU

"KMX/@1,EBMX/KMX,EALU/B,SMX/EALU,SCK/LOAD"
"KMX/®1,BVIX/KMX,ALU,/B,SMX/ALU,SCK/LOAD"

SC_LA
SC_LA.AND.K[]

"AMX/LA,ALU/A,SMX/ALU,SCK/LOAD"
“AMX/ LA ,KMX/@1,BMX/KMX,ALU/AND, SMX/ALU,SCK/LOAD"
“BMX/LC.,ALU/B,SMX/ALU.EXP,SCK/LJOAD"
*“SMX/EALU, EBMX/KMX,SCK/LOAD,KMX/.F,EALU/B"
“RAMX/Q,AMX/RAMX ,ALU/A,SMX/ALU,SCK,/LOAD"
"RAMX/Q.,AMX/RAMX
, BMX /KMX ,KMX/®1 ,ALU/AND, SMX/ALU,SCK/LOAD"
"RAMX/Q.AMX/RAMX,EBMX/AMX
. EXP , EALU/B,SMX/EALU,SCK/LOAD"

SC_LC(EXP)
SC_PSLADDR
SC_Q

SC_Q.AND.K[]
SC_Q(EXP)

“SMX/EALU,SCK/LOAD"

(LNOJ) SNOILINIZ3Aa a1314 WOY TOHLNOD J1LSONSVIAOHIIW

R(SRC)_D
R(SRC)_D(B)

“RAMX/Q,AMX/RANX.SXT ,DT/€1,ALU/A,SMX/ALU,SCK/LOAD"

SC_Q.SXT[]

sC_R{]

SC_RC[]

“SPD.R/LOAD.LC,SPO.RC/®1,BMX/LC, ALU/B,SMX/ALU,SCK/LDAD"

SC_R[].AND.K[]
SC_R[J(EXP)

“ALU/AND.AMX/LA.SPO.R/LOAD.LAB.SPO.RAB/@1,BMX/KMX.KMX/GQ.SMX/ALU,SCK/LOAD"
"SPD.R,LOAD.LAB,SPC.RAB/®1,ANMX/LA,ALU/A,SMX/ALU.EXP,SCK/LCAD"

SC_SC+1

"EALU/A+1,SMX/EALU,SCK/LOAD"

SC_RC[ ] (EXP)

“SPO.R/LOAD.LC,SPO.RC/®1,BMX/LC,ALU/B,SMX/ALU.EXP ,SCK/LOAD"

SC_SC.ANDNOT.FE "EBMX/FE,EALU/ANDNOT,SMX/EALU,SCK/LOAD"

SC_SC.ANDNOT.K[]

SC_SC+FE
SC_SC-FE

SC_SC+KI[]
SC_SC-K[]

"KMX /01, EBMX/KMX,EALU/A+B,SMX/EALU,SCK/LOAD"
PKMX,/®1,EBMX/KMX ,EALU/A=B,SMX/EALU,SCK/LBAD"

SC_SC~SHF.VAL
SC_SHF . VAL
SC_STATE

“EBMX/SHF.VAL,EALU/A-B,SMX/EALU,SCK/LOAD"
"EBMX/SHF.VAL,EALU/B,SMX/EALU,SCK/LOAD"
"EALU/A,MSC/LOAD.STATE,SVMX/EALU,SCK/LOAD"

SC_SC.OR.K[]

"KMX/®1, EBMX/KMX,EALU/ANDNOT ,SMX/EALU,SCK/LOAD"

“"EBMX/FE,EALU/A+B,SMX/EALU,SCK,/LOAD"
"EBMX/FE,EALU/A~B,SMX/EALU,SCK/LOAD"

"KMX,/®1,EBMX/KMX,EALU,/OR,SMX,/EALU,SCK/LOAD"

SC_STATE.ANDNOT.K[ ]

"EALU/ANDNGT , EEMX/KMX ,MSC/LOAD.STATE, SMX/EALU,SCK, LOAD, KVX/@1"

SC&STATE_STATE-R[ ] (EXP) "LAB_R[@1],AMX/LA.EBMX/AMX.EXP,MSC/LOAD.STATE,EALU/A'S,SMX/EALU.SCK/LOAD“
+SD_...

THRU

SD_NOT.SD

VA_...

“SGN/NOT.SD*"

SD_SS

“SGN/SD.FROM.SS"

§S_SD

"SGN/SS.FROM.SD"

STATE_O(A)

"AMX/RAMX.OXT,DT/LONG.EBMX/AMX.EXP,EALU/B.MSC/LOAD.STATE"

SS_0&5D_0
SS_ALUtS

“SGN/CLR.SD+55"
*SGN/LDAD.SS*

SS_SS.XOR.ALU15&S5D_ALU15

STATE_AMX.EXP

STATE_D(EXP)

"SGN/SS.XCR.ALL"

“EBMX/AMX.EXP,EALU/B ,MSC/LOAD.STATE"

"RAMX /D, AMX/RAMX , EBMX/AMX . EXF,EALU/B,MSC/LOAD.STATE"

STATE_FE

“EBMX/FE,EALU/B,MSL LOAD.STATE"

STATE_STATE+1

"EALU/A+1,MSC/LOAD.STATE"

“KMX/@®1,EBVMX/KMX,EALU/B,MSC/LCAD.STATE"
STATE_K[]
CRAMX/Q, AMX/RAMY ,EBMX/AMX . EXF,EALU/B,MSC/LOAD.STATE"
STATE_Q(EXP)
"MSC/LOAD.STATE,EALU/B,EBMX/KMX,KMX/SC"
STATE_SC.VIA.KMX
STATE_STATE.ANDNOT.FE

“EBMX/FE,EALU/ANDNOT .NSC/LOAD.STATE"

(LNO9D) SNOILINIZ3A @134 WOYH TOHLNOD J1LSONOVIAOHIIW

“REMX,/Q.BMX/RBMX,ALU/B,SMX/ALU.EXP,SCK/LOAD"
“RAMX/Q, AMX/RAMX , BMX /KMX ,KMX /61 ,ALU/A+B,SMX/ALU,SCK/LOAD"
"RAMX/Q.,AMX/RAMX , BMX/KMX ,KMX /@1, ALU/A-B, SMX/ALU,SCK/LOAD"
"RAMX/Q . AMX/RAMX , BMX /KMX , KMX/®1 ,ALU/OR, SMX/ALU,SCK/LDAD"

SC_Q(EXP)(B)
SC_Q+K[}
SC_Q-K[]
SC_Q.0R.K[]

STATE_STATE+K[]

STATE_STATE=-K[]

TATE"

'KM>/31 ESWMIX/KMY, EALU A+8 ,MSC 'LOAD.STATE"

"KMX,/®1,EEMX/KMX,EALU, A-B,MSC, LOAD.STATE"

STATE_STATE.QR.FE

"EALU/CR,EBVX,/FE MSZ/LOAD.STATE"

STATE_STATE.OR.K[]

"KMX /@1

VSKPC

STATES

,EBWX/KMX,EALU/CR,M5C/LOAD.STATE"

STATE_SKPLONG

"STATE_K[.4]"

STATE_STATE.AN.SKPLONG

"STATE_STATE.ANDNOT.K[.4]"

1EDITPC

cce

"WMX/®1,E30.¢,VX, EALL;A\DNOT.MSC/LGAD.STATE“

"E BNX/F: EnLU'A‘o.fl<C/L34

"EEMX,/FE,EALU/A=-B.M3IC, ;JAD SIAYE“

STATES

STATE_FIRST

"STATE_W[ZEzO]"

STATE_PREDEC

"STATE_K[.821"

STATE_STATE.AN.37GO

"STATE_STATE.ANONCT.K[.3F]Y

STATE_STATE.AN.6704

"STATE_STATE. ANDNOT.K[.7F]"

STATE_STATE.AN.SESTCBL

"STATE_STATE ANDNCT ki)

STATE_STATE.AN.NOTPREDEC

"STATEZ_STaATE. ANDNOT K[.7F]*

STATE_STATE.AN.PREDECIERD

"STATE_STATZ.ANDNOT. K[.CO}l"

STATE_STATE.CR.ACZJINP

"STATE_STATE.QOR. K[ 3{

STATE_STATE.OR.CEST

"STATE_STATE.QR.AK[.41¥

STATE_STATE.OR.CESTDOBL

“STATE_STATE.QR.K[.G]"

STATE_STATE.CR.FILL

"STATE_STATE.CX.K[7]"

STATE_STATE.CU&.FLCAT

"STATE_STATZ.OR.K[.eQ}"

STATE_STATE.OR.MOVE

"STATE_STATE.QOR.K!.801"

TATE_STATE.CR.PATT1

USTATE_STATE.CR.K[.1]"

STATE_STATE.QR.PATT2

"STATE_STATZI.CR.K[.2]"

‘MATCHC

STATES

STATE_INNEROBJ

"STATE_K[.1]"

STATE_INNERSRC

“STATE_k[.3]"

STATE_OUTER

"STATE_K[ZERO]"

SWAPD

"CK,BYTE.SWAPY

VA_ALU

“VAK LOAD"

VA_D

‘RA'X DLAMX

RAMX, A'J’A,VAK LOADTM

VA_D.OXT[ ]4Q

PRAVIX U,AVK RAMX QAT

VA_D.ANDNOT.
K[ ]

“RAVIXIT,AVX/RAX, BU(,'“( LNVEOB1,ALU/ANDNOT, VAK/LOAD"

DT ,81 EVX/REBMX,ALU/A+B,VAK,/LCAD"

VA_D+K[]
VA_D+LC

TRAMX D, ANMK/RAMX KK 2T, prx WX, ALU/A+B,VAK/LOAD"
PRAVIX/D,AVY/RANMA,BYY, L, A ,n+3,VAK/LOAD"

VA _D+Q

"RANVA

DAV A/RANMK
,REV Y, S, DM\

RBNVX,ALU/A+B,VAK/LOAD"

(LNOJ) SNOILINI43a 1314 WOYH TOHLNOD J1LSONSDVIAOHIIW

STATE_STATE.ANDNIT W[1

STATE_S*ATE+FE
STATE_STATE~FE

KX/ @T, BN /KMK
CAX

VA_LA.AND.LC

“AMX/LA,BYX/LC,ALU

VA_LA.ANDNOT.K[
]
VA_LA+D

VA_LA-D

VA_LA+KI[
]
VA_LA-K[]

VA_LA+K[
]+1
VA_LA-K[]-1

B, VAK, LOADTM

CAMX/ LA, EMX

AND,VAK,/LOAD"
amx,Kmx,@l.ALU/ANDNOT,VAK/LOAD"

"AMX/ LA, RENX/D,
CMX R3VIX, AU, A+3, VAK/LCAD"
"AMK/LA,QTWX/D,EVX/«_JA ALU/A=3,VAK/LOAD"
CANMKS LA, SV, KMX, AMXC 3T, ALLY A*B.\AK/LOAD"

WAMX, LA BV
/KM L KX, E1,ALL,/A~B,VAK/LOAD"
"AMX,LA,E'X M, KMA/TT,ALU/A?E+1,VAK/LOAD“
CANX,

LA, BVX/KME,
WML @1, AL,/ A=5~1 VAK/LOAD"

VA_LA+P2C

PANA

VA_LA+Q

LALBYWX/PC,ALY. A+a VAA/LOAD"

CAMR

LA, REMX/Q,
BMX . HEMX, 4LU,A+3,VAK,'LOAD"

VA_LA-)
VA_LB+D.0XT

VA_PC

“VAK.LOAD,ALU/A~B, 4WxX/LA.

x,R:flx R3MX/Q,SHF/ALU"

“BIAX,LE,ALU/A+B.ANMX RANX. VxT DT 'BYTE,VAK/
LCAD"

“BMX, PC,ALU/B,VAK LTAD"

VA_Q

TRAMX /Q, AMK/RAMA, AL

VA_Q.ANDNOT.
K[ ]
VA_Q+D

,A,VAA/LCN-

NRANX /G, AN RAMK, REX /2, SV WM, ALU/AN
,VAK
DNGT
/LOAD"

"VAK/LOAD.ALU/A+B, AVA,RAVY, SNX . R3MX, RAMX/Q, RBMX /D,
SHE/JALL "
VRAVK. G, AN, RAMK, KA/81 .3
S
ALU/A+E, VAK/LDADY
WRAMX/Q, ALX/RAMK KA /BT, Sun nMX,ALU/A=B,VAK/LQAD"

VA_Q+K[
]

€ce

ALY

LA, ELUS A, VAK/LDADY

VA_Q-K[]
VA_Q+LC

VA_Q+L8
VA_Q-L8B

VA_Q+LB.PC
VA_Q+PC

"RAMX/Q AWK,/ RAMX, 8L /LC,A;LUA+BLVAK/LOAD"
"RAYX, 9, NX/RAYVA, BMA/ LB, ALL, A+B, VAK/LOAD"
"TRANX/Q,ANMK/RAVK BN/LB
AL U, A-8,VAK/LOAD"
"RAijQ.Amx/QAMx,BMX/PC.OR.LB.ALU/A+B,VAK/LOA

"RAMX,/Q, AMX/RAMX,BMX/PC,ALL,/A+8.VAK/LOAD"

VA_RI[]
VA_RC[
]

"SPO.R/LOAD.LAB.SPO.RAB/@!.AMX/LA.ALU/A,VAK/LOAD"
“SPO.R/LOAD.LC,SPO.RC/@Y.BMX/LC.ALU/B.VAK/LOAD"

VA_VA+4

"PCK/VA+4"
"Non-transfer

B.FORK

BYTE
CACHE. INVALIDATE

CALL

Functions"

"LAB_R(SP1),QK/ID,CLR.IB.CCND,PC_PC+N,SUB/SPEC,J/B.FORK®"
"DT/SYTE"

"MCT/INVALIDATE,VAK/NOP"
*SUB/CALL"

CatL[]
C.FORK

"SUB/SPEC,J/C.FORK"

CHK.0DD.ADDR

*MSC,/CHK.ODD.ADDRTM"

CHK.FLT.OPR

“CALL,d/@1"

"MSC/CHK.FLT.OPR"

CLX.UBCC

"CCK,/LDAD.UBCCTM

CLR.FPD

"MSC/CLR.FPD"

CLR.1BO-1

“IBC/CLR.O0.1,1EK/ISTR"

(LNOJ) SNOILINI43d a1314 WOY TOHLNOD 21LSONDVIAOHIIW

VA_K[]
va_LA

CLR.IB.COND
CLR.IB.OPC
CLR.IB.SPEC
CLR.NEST.ERR

CLR.SD&SS
EXCEPT.ACK
FLUSH.
IS

"IBC CLR.1-5.COND"
»18C,/CLR.O,IEK,/ISTR"

:DISCARS =11 INSTR & OPERAND
.11 MODE DISCARD ISTREAM OPERAND
:2ND PART OF Q/D IMMEDIATE

"IBC/CLR.1"

"MSC,/CLR.NEST.ERR"
“SGN, CLR.SD+55"
"TEK. EACK"

"1BC/FLUSH,VAK/LOAD, IEK/ISTR"

INHIBIT.IB
INTRPT.ACK
., STROBE
INTRPT

“MCT /MEM.NOP"
"TEK/TACK"
"1EK,/ISTR"

IRD

_ALL1S5"
“LA_R(SP2)&LB_R(SP1),D8VA_LB,SC_ALU(EXP),FE_LA(EXP),SS
T,
CK/PC+N\"
,MC
-5.COND,P
I1D
IBC/CLR.1
QK/
4LLOW. IB.READ,
“MSC/IRD,

IRDO
IRD1
IRD. 11

LOAD.IB

vce

"IEC,CLR.0O-3"
“IBC/CLR.2.3"
“IBC,/CLR.1-5.COND"

11
LOAD.IB.
LONG
POLY.DONE

]
RETURN(
RETURNO
RETURN1
RETURN2

RETURN3

RETURNS
RETURNY
RETURNF

RETURN10
RETURN12
RETURN13
RETURNTF
RETURNZ20
RETURNZ24

RETURNA4GO
RETURNGO
RETURNG1
RETURN1CO

RETURN10C

WIRDO,CL®.UBCC,IRD1,SUB/SPEC,J/A.FORK"

“LA_R(DST)&LB_?(SQC).D_LB.PC,VAK/LOAD.O_IB.DATA.SC_K[.10}.9CK/PC+N.MSC/IPD.SUB/SPEC.U/DPO"
“VAKfNOD,MCT/READ.V.NEWCC"
"y AK, NOB,MCT/READ.V.NEWSC"
"DT/LONG"

WACF,/CONTROL,ACM,/POLY.DONE"
"SUB/RET,d/@1"
"SUB,/RET,J/0"

"SUB, RET,J,/1"
“SUB/RET,J,/2"
"SUB,RET.J/3"

"SUB,RET,J,/8"
"5UB, RET, /9"
“3UB,RET.J/OF"
"SUB,RET,J/10"
"SU8 RET,J,/ /12"

"SUB

RET,J/18"

"SUB/RET,JUSHFY
“SUB. RET,u,20"
"SU3/RET, /24"
"3, RET,J 40"
"SUB, RET, U, 60"

“§UB, RET, U 61"
U, 100"
“§ U8 RET,
“SUB.RET,J/10C"

(LNOD) SNOILINIZ3A a1314 WOH T0HLNOD J11SONOVIAOHIINW

CLR.180-3
CLR.IB2-3
CLR.1B2-S

"SUB/RET.J/1OE"

“"CCK/INST.DEP,DT/INST.DEP"

SET.CC(LONG)
SET.CC(ROR)

“CCK/ROR"

SET.FPD

“MSC/SET.FPD"

SET.N.AND.2Z

"CCK,/TST.Z"

SET.NEST.ERR

"MSC,SET.NEST.ERR"

SET.N&Z

“CCK/N+Z_ALU"

SET.PSL.C(AMX)

"CCH/C_AMXO"

SET.V

"CCK,SET.V"

START.IB
STOP.IB

“IBC,START"

“18C/STOP"

TEST.TB.RCHK
TEST.TB.WCHK
TRAP.ACC[
]
WORD

WRITE.DEST
"Branch

"CCK/INST.DEP,DT/LONG"

ACCEL?

“MCT/TEST.RCHK,VAK/NGQP"
“MCT/TEST.WCHK, VAK/NOP"

“ACF/TRAP.ACM/@1"

“DT/WORD"
"LAB_R{(SP1),QK/ID,CLR.IB.CCND,PC _PC+N,S5UB/SPEC, J/WRD"
Enable Macro Definiticns®
"BEN

ACCEL"

ACC.SYNC?

“BEN,ACCEL"

i ,J3/3"

AC.LOW?

"SEN/INTERRUPT"

;,J3/2"

ALIGNED?

"BEN/TS.TEST"

;,d5/17"

ALU?

“BEN/ALU"

ALU.N?

"BENALU"

ALU1-0?

"BEN,[ALUIT-O"

BCDSGN?
317
CONSOLE .MODE?

"BEN/DECIMAL"

007

"BEN,

:,J4,/07"

;,u2/2"

C31"

"BEN,PSL.MODE"

“BEN,/D3-0"

;,J5/18B"

i, ud,/CE"

O(1)?

VBEN/NLL"

027

"BEN,D3-0"

1,d3/08"

D2-07

"BEND3-0"

;,Js/08"

03?

"SEN

D3-0"

P L,Ua/ 07"

D3-9?

“SEN,

33-0"

D317

"BEN/SIGNS"

DATA.TYPE?

"BEN/DATA.TYPE"

i ,J3/8"

D.BO?

WgEN, D.BYTES®

;,Jd4/0E"

D.B1?

"BEN

D.BYTES"

:,Ja&/CD"

D.B2?

“BEN,/D.BYTES"

;,J4,/0B"

(LNOD) SNOILINIZ3a 1314 WOH T0YLNOD J1LSONDVIAOHIIN

RETURN10E

SET.CC(INST)

"BEN/DATAL.TYPE®
"BEN/D.BYTES"

D.NE.O?

"BEN,SIGNS"

tALU?

"BEN, EALU"

ZALU.N?

YBENCEALU
"BENEALUT
“BEN/END.DPI

YL
,J3/08"

ENC.DP1?
FPD?

"3EIN/LAST.REF"

Ja/ern

IB.TEST?

“BEN/1B.TEST"

INT?
INTERRUPT.REQ?
1207
{R0.C31?
IR1?
1R2-1?
LAST.REF?

"BENINTERRUPT"

DBL?

EALU.2Z?

9ze

MCDE.LSS.ASTLVL?

"3IN INTERRUPTTM
"BITN ALY

;. W3/5"
’

;PREFERED

FORM

'J’i/lsn

,J2,00"

"EZNCALUT
"BEN. IR2-1"

3/6"

YBEN, IR2-1"

“BEN/LAST.PEF"
"EEN/REI"

MUL?

NSNULY

NEST.ERR?

NLAST
L REFTM

LY
odc

;,Ja/0B"
’

PC.NMOCES?

,Jd4,/CE"

pSL.C?

"BEN/PSL.CCM

PSL.CC?

"3EN/BSL.CCO

PSL.MCDE?

“BEN/P3L.MCDE"
"BEN/PSL.CC"

JA/T

“BEN/PSL.CC"
“BEN/PSL.CC"

,Ja,/08¢"

PSL.N?
PSL.V?
pPSL.2?

PTE.VALID?

QUAD?
Q31?
RLOG.EMPTY?

"BEN/TB.TEST*
"BEN,/DATA.TYPE"
"BEN,/SIGNS"
"BEN, ALUt1-0*

ROR?

" BEN/‘IROR "

sC?

SC.GT.0?
SC.NE.O?
SIGNS?

"BEN,/SC"
YBEN/SC"
YBEN,/MUL"
"BEN,SIGNS"

SRC.PC?

"BEN,/SRC.PC*

§S7?
STATEOD?

"BEN/EALU"

STATE1?
STATE1-0?
STATE2?

“BEN/STATE3-0O"
"BEN,STATE3-0O"
"BEN/STATE3-0"
"BEN,/STATE3-0"

,J4,/0D"

yUS/O0F"
'd3,l3ll

WJA/T7

yJ3/3"
COMP MODE,
+J4/CE"
,Ja/0E"
yJa/0D0"
,Ja/0Cc"

,Ja/0B"

BEN ON

SRC

(LNOD) SNOLLINI4Z3A @13i4 NOY TOHLNOD J1LSONOVIAOHIIW

D.BYTES?

"BEN/STATE3-C"

STATE3-0?

"BEN, STATE3-O"

STATES?

"BEN, STATET-4"

STATES?

"BEN,/STATE7-4"

STATEG?

“BEN/STATE7-4"

STATEL7)?

"BIN/STATET-A"

TB.TEST?

"BEN, TB.TEST"
“3EN/PSL.MODE"
"BEN,/PSL.MODE"

VvA31-307
27

ZONED?
ALEG_D
ALEG_LA

ALEG_LAB
ALEG_Q
ALU_O(K)
ALU_O+D+1

R4S

"STATET-472"

STATZ7-4?
VA31?

ALU_D.ANZ.Q
ALU_D.OR.MASK
ALU_D[]LB

ALU_D[ IMASK
ALU_D[JRC[]
ALU_DI R[]
ALU_C-KR[]

ALU_LA-LC
ALU_LA.AND.LC

IK[ ]
ALU_LAT
ALU_LAT]LC

ALU_MASK
ALU_MASK+1
]
ALU_NGT.K[
ALU_NCT.LA
ALU_NOT .MASK

;,u4/07"

”Dc‘

;,U5/0F"
;,J5,/07"

7“

;,0Z2/1"
"SEN/DECIMALY
"ENX /RAIX, RAMX/D"
H\rfix/ nh

MANX/ LA

3"
"ANMX/RANMX, RAMX/

, KX, ALY,/ B"
8K/
WKX/ZERD

WAMX/RABIX.OXT,DT/LONG,REMX/D, BMX/RBMX, ALU/A+B+1"
WRAMX /D . AMXRAVX , R2\x /0, BMX/REMX , ALU/AND"
WRAMX /D, AMX /RAMK BN MASK,ALU/CR"
WRAMX/D, AMa RAVX.EVX/LB,ALU/@1"
/D, AMY RANMS, EMXMASK,ALU/@1"
WRAMX

" AVX/RAMX,RA. MXD.LC Q“'“2] BMX/LC,ALU/@1"
WAMX/RAMX,RLMX, D, LAB_RIF2],BMX/LB,ALU/@1"
/D, LAS_RIE 1],AMX/LA.ALU/A-8"
CEMX/R2VLL,RIMX
WAMX, LA, BYX,/LC,ALd, &i=B"
ALL, AND®
YAMX/ LA, BMXLC,
WAMX /LA BMX KX, RMX, 52, ALU/@1"
CANX/LA,BVMKLC,ALU/ST"
3"
K,
A U,
CBMXMAS

WACY

RAMX .OXT, DT "LING, BMX/MASK, ALU/A+B+1"

W AMX/RAMX.OAT,DT/LONG, KIIX/@1, BMX/KMX, ALU/DRNOT"

CAVX /LA, ALL. NOTA"
"ATAX /RAMX . CAT.DT,

LOND, EiX/MASK, ALU/ORNOT TM

NDTAY
PRAMX /G, AMY . RAMS, ALG
ALU_NCOT.Q
ALU_Q+D "RAMX/Q, ALLX CRAMK , BHIA/REYMIX, ALU/A+BY
ALU_Q-SC

ALU_Q[ 12
ALU_G! IWASK
ALU_Q.ANC.MASK

X,
ALU/A-B"
WKMX ST, ETX, KX, RANX, O, ANX/RAN

“RAMX/",A‘K RAMX,BMX LE.ALU/ /@1

HRAMX/Q, AMAS RAMX, BIMX, MASK, ALL/81"Y
RAMX LBV MASK, ALU/AND®
MX
/G, ANMK.
CRA

(LNOD) SNOILINIZ3a a7314 NOYH TOHLNOD J11SONOVIAOHIINW

STATE3?

YRAMX/Q, AMA SRAVIX, B4, MASK,ALU/OR"

ALU_Q.DOINDT.MASK

"RAMA/QLAMK,
FAYMX , BMX/MASK,ALU/ORNOT"

ALU_Q.XOR.RC[]

LC_RCI®1],
AMX,/RAVX ,RAMX/Q,BMX/LC,ALU/XOR"

ALU_Q.XOR.R(SC)

"LAB- R{SC),EMX/LE,AMX/RAMX ,RAMX/Q,ALU/XDOR"

Artu_Q[1«[]

CRAMX/Q, AMX,

RAMX, KWWY, &2, BMX/KMX,ALLU/@T"

ALU_Q[]LC
ALU_Q[IRC]]
ALU_G[ 1R[]

PRAMX/Q, ANX

RANX, 2iAX/LC, ALU/@1 "

YANMX/RAMK RAMX/Q,LC_RC[®2],BMX/LC,ALU/@1"

TAMX/RAVX,RAVMA/Q.LAS_RI®2],BMX/LS,ALU/31"

ALU_R(SC)

"SPO.AC/LOAD.LAB,3PO.ACN/SC,AMX,/
LA ALU/A"

ALU_RLOG

"MSC/READ.RLOG,ALU/B"

ALU_R[].AND.MASK

ALU_R[].0R.MASK

“SPO.R/LOAD.LAB,SPO.RAB/®1,AMX/LA,BMX/MASK,ALU,
AND"

"SPO.R/LOAC.LAB,SPO.RAR,@®1,AMX/LA,BMX,/MASK,ALU/OR"

8ce

ALU_R[ ].0RNCT.MASK

"SPC.R/LOAD.LAB,SPD.RA3/®1,AMX/
LA, BMX/MASK,

ALU/CRNOT"

ALU_R[ ]-K[ ]

ALU_R[J+K[
]

"SPO.R/LCAD.LAB,S5F0.RAS/@1,AMX
/LA, KMX /82, BMX/KMX, ALL/A+B"

ALU_SC

"KMX/SC,EMX/KMX,ALL/B"

BLEG_D

“BMX/RBMX,R3MX
/D"

BLEG_LB
BLEG_LC
BLEG_Q
CPSYNC
DELAY

“BMX/LB"

“BMX/LC”
TBMX/REMX, REMX/Q"
“ACF/SYNC®

"CALL[DELAY]"
TAMX /RAMX.GKT ,KMX,; @1, BVMX/KMX,ALU/A-B,D_ALU"

“Cr/ACCEL"
PERAMX
/D, AMX 'RAMY. SWX, LB, ALU/A-B,D_ALU"

“ALU_pietrl=c{e2l.C ALY
“EEMX/D, SMX

D.CR.R[]
D.SXT j+4[ ]
D_D.X0F.RC[]
D_LA+D

D_LA.OR.D
D_MASK
D_MASK+1

D_NOT.RC[]
D_Q.0R.D
D_MD

D_R[].LEFT
D_R[].OR.D

&1, AMX/LA,ALU/AND,D_ALUY
CREBVX, S PC.R/LOAD.LAB,SPO.RAB/

“TKALEFT,S1
Clv"
TREMXA/D,BMX 'REMX,3P0.R/LOAD.LAB,SPO.RAZ/E1,AMX/LA,
AL, OR,D_ALU"
TEAMX /T, AMX/RAMXL.SXT, DT, @1, KNX/@2, BMX/KMX , ALU/A+S . D_ALU"

"RAMX/D,AMX RANX,SPO.R/LOAD.LC.SPO.RC/@®1,BMX/LC,
ALY,/ XJR,D_ALU"

MX
'RCMX, ALU/A+B,D_ALU"
"AMX/LA,REBMX,/D,E

RBMX
/D, BMX/REMX,ALU/OR,D_ALU"
"AMX/LA,
"“BMX/MASK,ALU/B,D_ALU"

“AMX/RAMX.O0XT,
BMX, MASK,ALU/A+B+1,D_ALU"

“AMX/RAMX.OXT,SPJ.R,/LOAD.LC,SPO.RC/®1,BMX/LC,ALU/GRNOT,D_ALU"
,REMX. D"
,DK/SHF
, BMX/RBMX
"RAMX/Q.,AMX,/RAMX,ALU/OR,SHF/ALU
“DK/NCP"

"spé.n/LCAo.LAB.spo.RAs/@1,AMX/LA,ALU/A.SHF/LEFT.DK/SHF"

‘

BMX
ALU/OR,D_ALU*
“SPO.R,/LOAD.LAB.SPO.RAB/@1,AMX/LA,RBMX/D,BMX/RE

(LNOD) SNOILINIZ3A a731d WOH TOH.LNOD J1LSONOVIAQOHIINW

ALU_Q.OR.MASK

EBMX_K[ ]

6c€

ENDOVR
ERLOOP
ERROR1
ERROR2

"KMX /@1, EBMX /KMX "

*"SUB/CALL,J/SCOFE"
"SUB/CALL,J/ERLOOP"
"SUB/CALL.J/ERROR1"
"SUB/CALL,J/ERRJR2"

LAB_R(PRN)
LAB_R(PRN+1)
LAB_R(SP1+1)
LAB_R(SRC! 1)
LAB_R(SP2)
LAB_R(SP2.SP1)
MESSAGE
MESSAGE2
MESSAGE3
MESSAGE4
MESSAGES
MESSAGE?
MESSAGES

"SPO.AC/LOAD.LA3,SPO.ACN/PRN"
"SPO.AC/LCAD.LASB,SPQ.ACN/PRN+1"
"SPO.AC/LOAD.LAB,SPO.ACN/SPI+1"
"SPO.AC/LOAD.LAB,SPO.ACN11/SRC.OR.
1"
"SPO.AC/LOAD.LAB,SPO.ACN/SP2.SP2"
"SPO.AC/LGAD.LAB,SPC.ACN/SP2.SP1"
“D_K[ZERQ],CALLIMSGCOM]"
“D_K[.1],CALL[M5GCOM]TM
"D_K[.2},CaLL[MSGCTM])"
“O_K[.3],CALLIMSGCC
]
"D_K[.4},CALL[MS3CON]
"D_K[.B],CALL[MSGCCM]®
"O_K[.7].CALL{MSSCCM]"

MESSAGEQ

"D_K[.8],CALLIMSSCOM]*

MESSASE10
NEWTST

NEWTST[}
NOP

“D_K[.9].CALL[MSGCOM]"

"SUB/CALL,J/SCCPE"

“NEWTST ,RC[IF]_K[a11"
"DK/NQP"

Q_ACC

“OK/ACCEL"

Q_D[]Q
Q_D[]rCI]

"RAMX /D, AMX, RAMX , BMX /REMX,RBMX/Q,
ALU/@1 ,Q_ALU"Y
"RAMX /D, AMX/RAYX,SFO.R,/LOAD.LC,SPO.RC/®2,BMX/LC,ALU/&Y
,Q_ALU"

Q_K(SP1)
Q_MASK+1

CKMX,/SP1.CON.
BMX /KX, ALU/B,Q_ALU"
“AMX/RAMX.CXT,BMYC
. MASK ALU/A+B+1,Q_ALU"

q_not.mask

"amx/ramx.0
<t ,bmx, r2sk,alu/ornot,q_alu"

Q_Q.AND.LC

"RAMX/Q, AM.i. RAWMX,3MX/LC,ALU/AND,Q_ALU"

Q_Q.AND.MASK
Q_Q.AND.R[ ]
Q_Q.ANDNOT.RC[]
Q_Q.LEFTZ
Q_Q.XOR.D

"RAMX./Q, AMX, RANK,3VX-MASK,ALU/AND,Q_ALU"
"TR3MX/Q, EMY REMX,5P0.R/LOAD.LAB,SPO.RAB/®1 ,AMX/LA,ALU,AND,Q_ALU"
"RAMX/Q.AMX RAMX,SF3.R/LOAD.LC,SPO.RC/@1,BMX/LC,ALU/ANDNOT,Q_ALU"
"OK/LEFT2Y
"RAMX/Q . AMA, RAMX . REWX /D, BMX /RBMX, ALU/XOR,D_ALU®

RC[]_0-KI[]

"LMX/RAMX.OXT
KMX 32, 8V%/KMX,ALU/A=B,RC[®1]_ALU"

Q_Q.XCR.R[]

SQK/SHF , AWK /RANX. RAMX /G, BMX/LB,ALU/XOR,
LAB_R[@1]"

(LNOD) SNOILINIZ3a 7314 WOY TOHLNOD JILSONDVIAOHIIW

D_R{].0ORNOT.MASK "SPO.R/LOAD.LAB,SPD.RA3/®1,AMX/LA,BMX/MASK,ALU/ORNOT,D_ALU"
D_SC
“KMX/SC,BMX/KMX,ALU/B, S4F/ALU,DK/SHF"
EALU_STATE-K[]
“ESBMX/KMX,KMX,/®1,MSC/LOAD.STATE,EALU/A-B*

RC{
J_D+MASK+1
RC[]_LA+D
RC{]_LAB.XOR.LC
RC[
J_MASK
RC[]_NOT.O
RC[]_NOT.D

"“AMX/LA,RBMX/D,BMX,/REMX,ALU/A+B,RC[®1]_ALU"
“ALEG_LA,BLEG_LC,ALU/XDR,RC[®1]_ALU"
"ALU_MASK,RC[®1]_ALU"
"AMX/RAMX.OXT,DT/LONG,ALU/NOTA,RC[®1]_ALU*
"ALU_NOT.D,RC[@1]_ALU"

RC[ J_NOT.MASK
RC[]_Q+LC
RC{]_Q.AND.LA
RC[]_Q.0R.SC
RC[
]_Q+MASK

"BMX/MASK , AMX /RAMX . OXT,DT/LONG,ALU/ORNOT
,RC[@®1]_ALU"
"RAMX/Q, AMX/RAMX ,BMX/LC,ALU/A+B,RC[@®1]_ALU"
“RBMX/Q.BMX,/REMX,AMX
/LA, ALU/AND,RC[®1]_ALU"
TRAMX/Q, AMX /RAMX , KMX /SC, BMX/KMX,ALU/QR,RC[®1]_ALU"

RC[

*RAMX/Q, AMX/RAMX, BMX -MASK, ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SP0O.RC/@1"

J_Q+MASK+1

RC[]_Q.XOR.LAB

OEe

“RAMX/D,AMX/RAMX, BMX,/MASK,ALU/A+B+1,SHF/ALU,SPO.R/WRITE.RC,SPO.RC/@1"

"RAMX/Q.AMX 'RAMX,BMX /MASK,ALU/A+B,RC[®1]_ALU"

“ALEG_Q,BLES_L3,ALU/
X0~ ,RC[@1]_ALU"

RC[]_Q.XOR.LC

"ALEG_Q,BLSG_LC,ALU/XCR,RC[@1]_ALU"

RC{ ) _SHF
R[]_ALU.RIGHT2
R{}_D.AND.Q

"SPO.R/WRITE.RC,3PO.RC/&1"
*“"SHF/RIGHT2,SP3.R/wR1TE.RAB,SPO.RAB/G1"
"RAMX /D, AMX 'RAMX,BMX/R3VMX,ALU/AND,SPO.R/WRITE.RAB,SPC.RAB/@1"

R{]_LA.OR.K[]
R[]_LAB.XOR.LC
R{]_NOT.LA

"R[®1]_ALU,AMX/LA,BMX/KMX,KMX/@2,ALU/OR"
“"ALEG_LA,BLEG_LC,ALU/XUR,R[®1]_ALU"
"AMX/LA,ALU/NOTA,SPC.R/WRITE.RAB,SPO.RAB/@1"

R[]_Q.XOR.LAB
R[]_Q.XO0R.LC

"ALEG_Q,BLEG_L3,ALU/XOR,R[@1]_ALU"
“ALEG_Q,BLEG_LC,ALU XOR,R[®1]_ALU"

RC[]_sC

“ALU_SC,RC[®1]_arun

R[J_D.AND.RC[]
"RAMX/D,AMX/RAMY.SPO.R,LCAD.LC,SPO.RC/®Z,BMX/LC,ALU/AND,R[®1]_ALU"
R[
)_D.ANDNOT.MASK "RAMX, D, AMX,/RAMX, B X 1ASK,ALU/ANDNOT,R[@1]_ALU"
R{]J_D.ANDNGCT.Q
"RAMX/D,AMX/ /RAMX,RBMX,Q.BMX/RBMX,ALU/ANDNOT,R[{@1]_ALU"
R[)_D.LEFT
"RAMX/D.,AMX RAMX,ALU/A,SHF/LEFT,SPO.RAB/@®1,SPO.R/wRITE.RAB"
R{]_D.OR.K[]
"RAMX /D, AMX, RAMX ,KMX/ 62 . BMX/KMX ,ALU/OR,R[@1]_ALU"
R[J_D.ORNOT.MASK "RAMX,D,AMX RANX,B¥X,/MASK,ALU/ORNOT,R[@1]_ALU"
R[]_D.XOR.LAB
"ALEG_D,BLEG_LB,ALU,/X0OR,R[®1]_ALU"
R{]_D.XOR.LC
“ALEG_D,BLEG_LC,ALU/XOR.R[@®1]_ALU"

R[ ]_SHF
RETURN4

"SPO.R/WRITE.RAB,SPO.RAB/Gt"
"SUB/RET,J/4"

SC_SC-1
SETMCR[ ]

“KMX/.1,EBMX/KMX EALU/A~B,SMX/EALU,SCK/LDAD"
"R{CA]_K[@®1],CALL,J/SETMCR"

(LNOJ) SNOILINIZ3A a7314 WOYH TOHLNOD J1LSONOVIAOHIIW

RC[])_D+0Q
"RAMX/D, AM: ‘RAMX ,RBMX/Q,BMX/RBMX,ALU/A+B,.RC[®1]_ALU"
RC[]J_D.AND.LA
“RBMX/D,BMX
/RBMX, AMX/LA,ALU/AND,RC[@1])_ALU"
RC[]_D.ORNQT.MASK "ALU_D.ORNOT.MASK,RCI[®1]_ALU"
RC{]_D.XOR.LAB
*"ALEG_D,BLEG_LB,ALU/XOR,RC{®1]_ALU"
RC[]_D.XCR.LC
“ALEG_D,BLES_LC,ALU/XOR,RC{®@1]_ALU"

]
SETRXCS[

BRANCH

TRAP.FPA

“ACF/CONTRQL ,ACM/7"

VA_D.OXT[]
VA_D.OXT[]+K[]
VA_RI{1+K[]

"ALU_D.CXT{®21],va_aLU"
®2],VA_ALU"

“SPO.R/LOAD.LAB,SPO.RAZ,@1,KMX,/82,BMX/KMX,AMX/LA,ALL
"A+B,VA_ALU"

DEFINITIONS
ALV, 2Z?

ALU.C?

D1-0?

IEE

"ALU_D.OXT{&1]+K

“BEN/ALU"
"BEN/ALU"
"BEN/D3-0"

;

NOTE

J/XXB

NESSECARY

(LNOJ) SNOILINI43a 1314 WOYH TOHLNOD J1LSONOVIAOHIINW

"SC_K[Z1].,CALL,J, SETRCF"
"R[OA]_K[&1],CALL,J/SETRXCS"
]
SETTXCS{
"R[OA]_K[®1],CALL,J/SETTXCS"
SUBTEST "CALL,J/SUBTST"

]
SETRCF[

CHAPTER 9
MISCELLANEOUS

2
L

s
1050

1 13

Ve =PIN 16
GND = PIN8

AM25S10

13-Qoe

LOGIC DIAGRAM
1-3

1-2

Gee

-1

TRUTH TABLE

OEfS1 So|'3 '2 1y 19 L4l l3[v3 Y, Yq ¥g

H=HIGH

X=DONTCARE

L=Low

Z = HIGH IMPEDANCE
STATE

HIX

XIX

X X

X1z

L|L

L|p3by 0409

x|D3D,Dq

x[P2D1060D,

H|x

D2D1DgD4

LfH

L|x

DyDgD4D,
x|D4DgD 4D,

L|H

H|X

D, AT INPUT
|, MAY BE EITHER HIGH OR LOW AND OUTPUT

¥ WILL FOLLOW THE SELECTED Dy, INPUT LEVEL.

DgDyD3D3DgD.4D
5D 3
1C-26510

SWVHODVIA LINJHID G3LVYDILNI 08L/LL-XVA

1
tg

ds;

1NdLNO 3LVLSIHL HLIM dIHD H3141HS 118-4N04 01SS2

LOGIC SYMBOL

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS

(CONT)

26S10 BUS TRANSCEIVER CHIP

BN })—

})_

——

OUTPUTS |

INPUTS

Y = VOLTAGE OF BUS

X = DON'T CARE

(ASSUMES CONTROL BY

ANOTHER BUS TRANCEIVER)
1C-26510

336

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)
74LS181 ALU CHIP

QUTPUTS

CARRY

COMPARATOR

GENERATE
CARRY

PROPAGATE

CARRY
14

A=B

couT

(—— B3

19
—~JA3
20

f2 L

21
RN
LI

—

FUNCTION

74181

WORD

INPUTsfi 22

13 3

OUTPUTS

23 A1
01

-— 80
02 | a0

tof—J

|04

|05

CIN

|08

|06

VCC=PiIN 24

= PIN 12
GND

[O7

MODE
CARRY
INPUT

FUNCTION
SELECT
INPUTS
74181

TABLE OF ARITHMETIC OPERATIONS

TABLE OF LOGIC FUNCTIONS

Function Select

Output Function

S3 S2 S1 SO | Negative Logic | Positive Logic
L
L

L
L

L L
L H
L H
L H
L H
H L
W L
H L
H L
H M
H H
H H
H H

L
L

H
L
L
H
H
L
L
H
H
L
L
H
H

L §=A
H ! f=AB

L | t=A+8

(M) high: C;,, irrelevant
With mode control
For positive logic: logical 1 = high voitage

f=A
f=A+8

t =AB

f = Logical 0
f =AB
=8
f =A®D8
t =AB
t=A+8
f =al®8
t=8
t=AB
f Logicat 1
t=a+B
t=A+B
f=A

Function Sefect

s3 sz S1
L
L

L
L
t
L
L
H
H
H
H
H
H
H
L"

L
L

L
H
H
H
H
L
L
i
L
H
H
H
H

L
L

H
L
L
H
H
L
L
H
H
L
L
H
H

Low Levels Active

Output Function

L | f=Amiou
H | t=AB minus 1

|t=ABminus1

s
(25 complement)
H | f=minu
L 1= A plus [A +B)
H = AB plus (A + 8] 1
L = A minus 8 minus
H [t=A+8
L |f=Apws(a+B)
H [f=ApusB
t t = AB plus [A +B]
H [f=A+B
L |f=ApksaAt
H | f=ABplsA
L [f=ABpusA
H lf=aA

High Levels Active

f=A
f=A+B

t=a+B

f = minus 1 (2's complement)
£=Aplus AB
t= (A +8] phs AB
f= A minus B minus 1
f = AB minus 1
= A plus AB
f=AphsB
f=[A+8) plus AB
= AB minus 1
f=AphsAt
f=(A+8] plusA
f=[A+B)phs A
t= A minus 1

With mode contro! (M} and C;, low
+ Each bit is shifted t0 the next more significant position.

0 = iow voltage
logical

For negative Jogic:

1 = low voltage
logical

H£-741819

togical 0 = high voltage

337

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

74182 LOOKAHEAD CARRY CHIP

PIN DESIGNATIONS

Designation

Pin No.

Function

G0,G1,G2,G3

3,1,14,5

ACTIVE-LOW CARRY GENERATE INPUTS

PO, P1,P2,P3

4,2,15,6

ACTIVE-LOW CARRY PROPAGATE INPUTS

CIN

CARRY INPUT

COUTX, COUTY, COUTZ

12,11,9

CARRY OUTPUTS

GOUT

ACTIVE-LOW CARRY GENERATE OUTPUT

POUT

ACTIVE-LOW CARRY PROPAGATE OUTPUT

Vee

SUPPLY VOLTAGE

GND

GROUND

|1o

l 07

dLoe

GOUT

POUT

couTZ

74182

l 06

COUTY

CouTX

13
—dcin

74182

o1
VCC:=
GND=

74182

PO
04

PIN 16
PIN 08
IC-74182

338

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

74LS670 4 X 4 REGISTER FILE CHIP

012
D2 —

g
DATA INPUTS

OUTPUT <

N }READ SELECT

wA—2

WBE }WRITE SELECT

6 s

GW—2.0l WRITE ENABLE
GR— 'O READ ENABLE
VCC

GND

WRITE FUNCTION TABLE

TRUTH TABLES

READ FUNCTION TABLE

(SEE NOTES A, B, AND C)

WRITE INPUTS

(SEE NOTES A AND D)

WORD

READ INPUTS

OUTPUTS

Gy |

Gg|

|QD

|WOB1

wOB2

WOB3

WOB4

W1B1

w1B2

W1B3

W1B4

©Q

|w2B1

w2B2

W2B3

W2B4

H O H

©Q

|W3B1 W3B2 W3B3 W3B4

|[Q

H{|

A. H=HIGH LEVEL, L= LOW LEVEL, X = IRRELEVANT, Z = HIGH IMPEDANCE (OFF)

B. (Q=D)=THE FOUR SELECTED INTERNAL FLIP-FLOP OUTPUTS WILL ASSUME THE STATES
APPLIED TO THE FOUR EXTERNAL DATA INPUTS.

C. Qp=THE LEVEL OF Q BEFORE THE INDICATED INPUT CONDITIONS WERE EXTABLISHED.
D. WOB1 =THE FIRST BIT OF WORD 0, ETC.
IC-741.5670

339

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

82823, 825123 256-BIT BIPOLAR PROM CHIP

Ce
s

Ag
Joa

(13)

(12)

(1)

(10)

J)(s)

J)m

32 x 8 ARRAY

J’m

J)(z)

gs)

&(4)

(j)(s)

THE 82523 USER OPEN COLLECTOR OUTPUTS.

VYcc =(16)

THE 825123 USER TRISTATE OUTPUTS.

GND = (8)

gg)

(N) = DENOTES PIN NUMBERS
1C-82823

825123

340

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

85568 64-BIT EDGE-TRIGGERED D-TYPE REGISTE

R FILE CHIP WITH

TRISTATE OUTPUTS

—3

ADDRESS

A3_5

OUTPU

L7
o1
8 o2

;

WE —2
OlWRITE ENABLE

02—

ATA INPUT

D4 16

05 —3.
0} ouTPUT STORE
00 —2.0l OUTPUT DISABLE
WRITE CLOCK
14
wC

VCC 18

GND
9

TRUTH TABLE

oD | WE |cLK | OS
L

{ x|

MODE

| X

[L
{x

| wRITEDATA

| ReapDATA

| OUTPUTSTORE

OUTPUTS
| DATA FROM LAST ADDRESSED LOCATION
DEPENDENT ON STATE OF OD AND OS
DATA STORED
IN ADDRESSED LOCATION

Hlx | x|L

| ouTPUTSTORE

H|X

| OUTPUT DISABLE |

| X

| miz
mi.z

1C-85568

341

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

DEC 8646 FOUR-BIT TRISTATE BACKPLANE INTERCONNECT
TRANSCEIVER CHIP

BUS4 PIN16*—
BUS3 PIN 14 *+—

]
PARITY

PIN 10

PIN
3

PIN 7
pin 13

&—

BUS1 PIN4 ,_l

CKT

REC

TRANS 1

DATA 1

——DO

TR ANS 2

A 4817

—DO

DATA
2

{4>— 4BIT

DATA 3

+ PIN 12

REC

DATA 4

t
PN

ENABLEL

LATCH L

REC

CLK
q>

PIN 18

PARITY

RECEIVE

TRANS
CLK H

PINS

REC

LATCH

[RANS3

TRANS

PIN 19

+ PIN
2

REC

LATCH

pin 17 [RANSA
pin 1

BUS2 PIN6

PARITY GEN

TRANS

PARITY CHECK [ CHECK _ o og
CKT

1C-DECBB4A6

342

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)
93406 1024-BIT ROM CHIP

0p 112

4 "2

oy |

ADDRESS ~

2
1

—

iag

—15 1A,

|10

OuTPUT

—

Vee

GND

Cs1Cs2
CHIP SELECT
1C-93406

343

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

9403 FIFO BUFFER CHIP

—
[}

—q-

MR
Q3

D2
4

—1

34 oo
2

9403

—21d

ore

—

IRF

T!s STW BTH 13T|6 17

0202

CPSO
TOP

Ds [ O2{

]

Parailet Data Inputs

Serial Data Input

Parsitel Load Input

D:|

INPUT DATA

INPUT

CONTROL

TOS

TTs

INPUT REGISTER

Serial input Clock {Operates on

| A E

Negative-Going Transition}

Seral Input Enable (Active LOW}
Transter to Stack Input {Active LOW)

Serial Output Enable Input

(Active LOW)
Transfer Out Serial input
(Active LOW)

STACK

CPSO

Transter Qut Parallet Input

14 x

CONTROL

14 STACK

Master Reset (Active LOW)

Output Enable (Active LOW!}

Serial Output Clock Input
{Operates on Nagative-Going Transition)

Qo
- Qs

Paralisi Data Outputs

Serial Dats Output

input Ragister Full Output

(Active LOW)

Output Register Empty Output
{Active LOW)

VDD = Pin 24
VSS = Pin 12
O = Pin Number

—q

(» s —
Tor —|

@ T08 ——qf

OUTPUT REGISTER

QUTPUT
CONTROL

OUTPUT DATA

CPSO

TM=
Q

344

VAX-11/780 INTEGRATED CIRCUIT DIAGRAMS (CONT)

DC101 ARBITRATOR CHIP, PART 1

——<TRSELS

BUS TR 15 L »—2-Q)
14 L »—-Q
BUSTR
TR 13 L »——Q)
BUS
12 L »—QO)
BUSTR

LSD 3SD

11 L Q)
BUSTR
TR 10 L »—2-O)
BUS
BUSTROL »——O)
INPUT
8 L »—2-Q)
FROM SBI fi BUSTR
BUSTR7L »23Q)

NEXUS TR#
JUMPER SELECTED

—<4 TRSEL 1
27

2SD MSD

[D—

BUSTRL

OUTPUT TO SBI

(YOURBUS TR L)

DC101
E143

BUSTR 6L »22-Q
BUSTRS5L 2O
4 L »220
BUSTR
BUSTR3L »—2Q)
BUSTR2L »2Q
BUSTR 1L 1O

4
< TR SEL
~4 TR SEL
2

o ARB OK L OUTPUT TO
515
NEXUS LOGIC

BUSTROL »Q
H
R CLK

EAC

CONTROL

TCLKH

SIGNALS

SEND TR H »

10
SEND HOLD H »—
1C-DC-101 A

345

’.

+VCC

.’

TRSEL4 L [26]

BUSTRGL
CH

wvee

TRSELT L DL
o> ——R1 H

ove

RkL [14 H—O

—R2H

BUSTRS L

_j}

AL
BL
BUSTML

r‘ >0+

——_—_—-|

!_@

L....___...[ -

BUSTRJL
cH

P2H

AL
BL

BUSTR2L
=

YOUR

BUS TR L

BUSTRIL

At
8L
clL

‘—J——A1 H
——A2 H

A3
H

BUS TRO L

IIIX

TCLKH

\i\

[=XeX--B4

SEND TR Hlmi

b P1H

R2 H ——

————
e o
ic.0c-10Y

(LNOD) SWVHOVIA 1INJHID AILVYDILNI 08L/LL-XVA

Z 1HVd ‘diHO HO1VvY.1i1gHYV LOLDOa

TRSEL8L | 27

BUS TR14 L

BUSTRI3 L

P——————fl

L
BUSTR12

LYE

R1H

P1H-—

| S —————

BUS TR11 L@(D
AH

1 -

JARBOK
L

P2
H

+VCC

BUS TR10 L
BUS TRS L

)

cL
DL

AL‘%

BUS TR L

=77

L—-—-—1€-0C101 €

(LNOJ) SWYHOVIA LINDHID AILVHOILNI 08L/LL-XVA

+VCC
AH

€ 18Vd ‘dIHO HOLVHLIgYY L0LDa

BUSTRISL

ENAST H

VECTOR H[Q 1

ENDATA H

ENACLK H ———-—

17[QRASTA H

BDIN L3

16[JENAST
H

NiTo L [J4
BINIT L[5

8ve

BIAKI L ___

BINIT L

180 vee

VECRQSTB H [ 2

15[JENADATA
H
DC003

14[JENACLK
H

BiAKOL [O6

13[0JENBCLK
H

paki L

12[JENBDATA
H

gira L

11[DENBST
H

GND [O9

10[JROSTBH

o>o
——-- BIAKO L

BDIN L %

—v———— BIRQ L

]I” ENDST H

ENBDATA H .“‘"—D
ENBCLK H

VECTOR H

*VECR()STB H

RQSTB H |10}

.** GND
@wrm L
oo

(LNOD) SWVHOVIQ LINDYHID QILVHOILNI 084/LL-XVA

RCSTA H |17}

diHO 1dNYH3I1INI £0000

wee—{18]

+VCC

DECODER

BDAL2 L

1 -

17] seL6 L

BDAL1 L |03

11—

o—

16| SEL4 L

15| SEL2 L

VECTOR HI]

]

6v€

L
14| SELO

)

goaLo L [0

13jOUTHS L

]

’o ::D

12|

—

E NB H
RXCX H

L
SEL6

BWTB

SELA L

L 6L

SEL2 L

BoIN L []7

SELO L

BDOUT L [J9

OUTLB L

srRPLY L

oND 10

QUTHB L

INWD L

18] RXCXH
jog] BRPLY
L
01}

ouTiLB L

vee

L ]4
BDALO

ssync L

)

BWTBT L

8oAL2 L [ 2
s8pALY L O3

VECTOR H

4EINWD L
1C-0Co04

(LNOD) SWVHOVIA LINJYID Q3 LVHDILNI 08L/LL-XVA

diHD 71030.104d 70000

VCC

¥<. VI

18}oaTo H

¥_-.ona H

BUS3 L

?.JV! H

foa] MatcH
-{03)
ATC W

— DAT1 H
MENE L

?@JV2 H
MATCH H ]

DAT2 H

CEEERE

XMIT H

20 vee
19[1JA3 L
1ePoaTon
17H0ATY H

15 ngz H

PIVIH

1PV H
13[)MENS L

120JBuso ¢

nsust L

1¢ pCoos

(LNOJ) SWVYHOVIA LINDHID AILVHOILNI 08L/LL-XVA

diHD YIAIFISNVYHL S0000

@ Q