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September 1976

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Document:	TMB11/TU10W DECmagtape System Maintenance Manual (TMB11-E/F System)
Order Number:	EK-TMBEF-MM
Revision:	PRE
Pages:	222
Original Filename:

OCR Text

S VRIS WL P
PSR

Preliminary Edition,

SEPTEMBER

Coi')y.right © 1976 by Digital Equipment Corporation.
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

~ sibility for any errors which may appear in this
S
~ manual.
’ Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

-DECtape

DECUS

RSTS

DECsystem-10

DIGITAL

TYPESET-8

MASSBUS

TYPESET-11
UNIBUS

DECSYSTEM-20

PDP

DEC
- DECCOMM

1976

- TABLE OF COHTENTS

General Information

" CHAPTER 1
1.1

Introduction

1.2

General Description

System Configuration

'1.2.1'

‘ Physical pescription

1.2.2

1.3 System Functional De;criptiqfi
1.4 Appiicable Documents ‘

1.5 Specifications.

CHAPTER 2

Unpacking, Installation and Acceptance

2.1

Testing

Site Planniné and Considerations
space Requirements
Power Requirements

2.1.1
2.1.2

'2.2

2.2.1
'2.2.2_

Unpacking

| - TU1OW Cabinet Unpacklng
TMB11 Unpacklnq

2.3

Inspection

2.4

TU10W Cabinet Installation

2.5

TMB11 Installation/Cabling

~ System Unit Installatioh

’2;5.1
2.5.2

Module Installation

2.5.3

Unibus Cabling

255;4

EnVironflental Requirements 1

2;1,3

CONTROLLER/HASTBR DRIVB CABLING

Securing Cables

2.5.5
2.6

TU10W Cabling

2.7

Acceptance Testing
-

iii

Chépter'7
M8926

Theory of Operation

7.1

General

7.2

Status/Command Logic
Command
Status

7.2‘2

7.3

Drive

Start

Logic
Logic
Up

Drive Start Signals
Start Up Delay
Sequence

Nine Track'Normal
Write Data

R TR

Tl e

Write End of Record

A ERRGISE
D N e e TCER
I G RN

Seven

Normal

Track

File

Write

Data

Write

End

Mark

Nine

Track

Record

Seven Track File Mark

Read

Sequence

Read Data‘
Error Detection
File

End

Mark

7.5.4.1

7.6

Record

Drive

Detection

Nine

Track

Zero

CRC

Seven

7.5.4.3

Detection

Normal

LRC

Characters

Track

and

File

Stop

vii
-

Mark

Fig.

C 1
k;}

No.

‘

7-3

7-4

M8926

Block

Diagram

A' RWS and CRWS Timing Diag;am
,

7-5 !‘

Title

-~ M8926 Simplified Flow Diagram
M8926 Detailed Flow Diagr;fi

‘7—1 |
7-2

Command Latch Up Flow Diagram

7-6

STATUS/COMMAND Block Diagram

7-7

M8926 Timing Diagram

Starf/Stop Control‘Block Diagram

7-9 - |
~7-10

"Drive Start Up Flow Diagram

7-8

Write Flow Diagram |

7-11

Write

7-12

7-13

k%
‘

7~14"
7-15

Read Block.Diag:am

End of Record Timing‘Non—Zero CRC and LRC
End of Record Timing, Zero CRC
o

‘7-16

7-17

End of Record Timing, Zero LRC

End of Record Timing, Sevefi Track and File Mark

7-18
7-19

Diagram

Read Flow Diagram

Block

. End of?Record Flow DiagramA'
-

| End of Record Block Diagram

7-20 |

’ .Drive-Stop Flow Diagram

- 8=1

TU10W Regulator Board and Fan

8-2

TU10W

+5V

Requlator

(

Circuit

N T STE CETE L

TRTTR L U ST LT T
IS AR b LT A

ST TR B TR
S I IO
Tk

R T

) LA

T T I TT D T C LTT BT ST P

RTT

R €

YT LT

S BT

BRI 0 5 S

e T BT

T PR T S

a4 S T

PREFACE

The TU10W transport is very gsimilar (in many areas identical)

to the TU16 transport with respect to both transport hardwarei
and electronic modules.

In this manual reference is made to the

on the TU10W txansTU16/THMP2 maintenanc e manual for information

port that is fdentical to TU16 information,
tem
specifically the references are from Chatper 5 (Sys

ter 8

Maintenance) for maintenance on the transport, and fron Chap

erences

(TU10W theory of Operation). . Chapter 8 covers the diff

between the TU10W transport and TU16 transpoxt.
pertains to the nevw

areas that would not be documented in the TU16

p- Y SR, S

e
LA
ie ettt
T

SR
s Sl
T

AN Y

Abe
X
ey WS

Nt ol adis -

R e

i W &wh‘:‘ by o RGN

manual.

xiii

This information

~~~~~~

CHAPTER |

_GENERAL INFORMATION

1.1

iNTRODUCTION

)f {is a magnet
The TfiB11—EX/FX* DECmagtape System (THB11/TU10W

ppP-11 family of
the
h
wit
s
ace
erf
int
t
tha
tem
sys
e
rag
sto
e
tap
for digital
e
raq
sto
es
vid
pro
and
s
al
er
ph
ri
pe
d
an
rs
so
proces
data in
l
ita
dig
s
ord
rec
and
ds
rea
tem
sys
The
on.
informati
ximum
ma
a
at
mat
for
I
NRZ
e
bl
ti
pa
om
-c
ry
st
du
jn
an
iparallel in
data transfer rate of 36 000 tape charactexs

per second. Tape

rd/

ectable. ‘Forwa
'density and tape character format are program sel

is performed at
reverse tape speed is 4% in./sec, while.rewind
also has forward
tem
sys
ve
dri
e
tap
0W
TU1
11/
TMB
The
c.
/se
in.
156
and reverse read/space capability,
1.2

I.Z.i

General Descripticn

System Configuration

The besic TMB11/TU10W DECmagtape System configuration is a TMB11

controller and a TU10W master tape transport. From one‘to seven
“slave" transports may be added to makea maximum pessibleuconts.

fiquration of one TMB11 controller and eight tape transpor
)

The

a 7-track
*+ The TMB11-EX is a 9-track system. The TMB11-FX is
ncy requirements
system. "X" specifies the system voltage and freque
(see table 1-1).

ent"

77 Y
Lek
NN

fi" o

sty

‘fThe TMB11—-EX/FX system is commonly referred to'by its compon

le
subunits, the TMB11 and the TU10W, hence the manual tit
this
TMB11/TU10W DECmagtape System Maintenance Manual. Wwithin
TU10W.

manual the system igs referred to as the TMB11/

1-1

oI &
master tape transport 1s cownposed
M8926 interface module.

Phne KMES25 interfazes

‘port and the slave transports

BC11A controller cable.

"hoset"

(if any}

transgsport and an
t¢he

"host"

to the TH311

wvia the

All the tape transports are "daisy

chained" on the slave bus making them essentially in
with each other.

Figure

trans-

parallel'

1-1 is an illustration of the TMBY1/TU10W

system configuration.
Physical Description

'1.2.2

The TMB11 (Figure 1-2) congists of'the foliowing six modules:A
,ffi

‘fig

M105-Address Selector Module

fi795~Word‘Count and Bus Address Module

M796-Unibus Master Control

4;Z‘M7821~Interrupt Control Module
v/

Drive

Interface

M7911-Tape

M7912-TMB11 Unibus Registers

. The 8ix modules are plugged into a TMB11
mounted invan expander box.

systcm unmt that is

Unlbus input,

Unibus output,

and

tape transport cabling also connect to the system unit.
The TU10W tape transport is contained in a single 19 inch

1(48.3 cm) cabinet along with an 861 power controller (Figure 3);

Figurea

1-4 and 1-5 illustrate front,

rear and side v1ews of

the transport and identify many of the TU10W components and‘
subassemblles.
!

The‘TMB11 Controller interfaces the DECmagtape syutem to the
PDE-!! Unibus.

It controls data transfers, issueé control

oomuands.to the TU10W master, and mouitors system operation.
Each TMB11 can control one master trangport and up to Béven slave

transports.

1-2

U
.

)

BCIIA CONTROLLERCABLIE

'« -

r |

Tuiow
MASTER
TAPE
TRANSPORT

—

|
WRITE DaTa | |

i
{

TAPE

TRANS PORT

MODULE

v 1

_ STATUS

HOST

| TINTERFACE

DECMAGTAPE K READ DATA

CONTROLLER
TMBN

(
Mga2

(/[

nco-—-2C

CONTROL

'a——-c—-va-——v""'"-"'""""

WRITE STRCBE
-

contRoLLERC

]

<«

WRITE. DA‘T‘A;>
STATUS

. READ STROBE
<R

@ READ DATA

TAPE [TRANSPORT

}l -

Tutow
SLAVE

1-1

Neeon

TMB11/TU10W Tape Drive System Configuration
.1-3’

TAPE

TRANSPORT

SLAVE BUS DAT‘A

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‘The TU10Wmaster transport consists of an M8926 interface module

and a "host“ transport. The M8926 processes commands from the
controller and issues motion and read/wyrite commands to the host

and slave transports:; the MB926 alsc monitors statfis lines fromA

the host and slave transports. Any status changes‘at tfie selected
tranéport are reported immediately to Ehé controller. 1In reaponseA
to

inputs

motion

from the

M8926

and records

and

module,

reads

the

host

transport

data on magnetic

controls

tape

tape.

The TU10W slave transport consists of a tape transport only. fIn.

response to inputs from the M8926 module in the mastervtran8port;
it controls tape motion and records and reads data on magnetic tape.

The various models

of the TU10W transport are

two-letter dashed suffix.

identified by a

The first letter of the suffix desF

ighates,the number of tracks on the transport; E for a 9 track
transport, F for a 7 track transport.
‘the

transport

and specifies

a master

the

or
a

voltage and

slave

The second letter identifies
(A,B,C,D=master;

frequency requirements.

E,F,H,J=slave)

Table

1-1

- summarizes the TU10W models and their'identifying suffix.
Table

§U10w-mka§\track

1-1

TUI10W

TUTOW-EX&? track

Master/Slave | X= Voltaée/?req
Master

Slave

Models

~ Haster/81a§e

‘A '115v/60.Hz

Master

B
' C

|230v/60 fiz'
|
|115v/50 H=z e

|230v/50 Hz

|115v/60 Hz

Slave

|230v/60 Hz

115v/50

|230v/50 Hz

)

X= Voltage/Freq?
A

i15v/60 Hz

B | B |230v/60 Hz
;.
C |115v/50 H=z
|

.A
_

;
f

|230v/50 Hz

|115v/60 Hz

|230v/60 Hz

|115v/50

|230v/50 Hz

1.3

SYSTEM FUNCTIONAL DESCRIPTION

redd‘ji}
The basic functions performed by the contrxollexr are: off-line,
write,
IRG,

write

and

EOPF,

rewind.

space
Each

forward,
of

space

reverse,

these

functions

Table

1-2

write-with-extended-

briefly

Controller

Function
"Off-Line

described

Functions

Description
The

off-line

function

used

desired to return control to
transport

changed,

etc.

that

tape

when

the tape

can be

rewound,

reels

without usinglprocessor time.,

The off~line function

places the selecte&

tape transport in the off-line (local) mode i <fi
and

causes

The

controller cannot write

the

magnetic

Read

tape

when

rewind

the

operation.

onh

zead

off- llne

fxom

function

used

This function permits reading from the magfietic
tape.

During the read operation,Athe data

portion of the

RISt SRR
CIELATEY

begin

record

loaded into

the

)

controller data buffer for transfer to the
nemory.

The

LRC

read

not

transferred

but

and

CRC

characters

into

are

memory.

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This function permits writing'on.the magnetic
tape. During the write operation, data from
the bus is loaded into the controller data

buffer register.

The controller then transfers

the data to the tape transport write heads.
’The necessary LRC and CRC characters are gen-

erated by the master transport and written on
the tape following the data.

The write

function advances the tape one record.

Write

EOF

This function writes anend—bféfile (EOF)

B g

mark on the tape.’ When selected, ;his
funétion erases a 3-in. segment of fiape
prior to writing the first cha:actef. Thé\
EOF mark andAthe‘associated LRC charactér
are considered one record.
48

an octal

character

*The EOF mark

{9-track drive;

octal 17 for 7-track drive) foilowed by an.
octal

Space

Forward

(or octal

17)

LRC

character.

This function is used to skip over a nufiber
of records toffind a specific record on the
tape.

When selected,

the space forward

function causes fihé tape fitansport to advance
a specified number of records.

The number

of recorxrds is determined by the value in the

byte

record

counter.

This

wvalue

loaded

'}into the byte record counter by the program.
Space

forward

used

for

tape positioning

'iny‘and, therefore, does not affect infbrmation
the

stored on

in memory.

tape or

This function is identical to the space

Space Reverse
.

forward
Jthe

function

reverse

except

rather

the

than

tape
the

moves

feorward

direction.

| W:ite-with-Extended—IRG

This

function
'is identical

function

tape

except that

3-in.

the

write

segment

erased before writing the

first

(

character.
R)

This function is used for rewinding the tape
on

the

feed

reel

that

the tape

can

either

ee
.

TR ea|

e M

haad AT e TNTR Wy AL A

(R
S

Rewind

be unloaded from the transport or operation

can start at the beginning of‘the tape.
When this function is used;'the tape moves in

the reverse directién, at a much higfier spaed
(150 in./sec) than for other'functions, until

the beginning-of-tape (BOT) narker is detected;
When the BOT marker is detected,
|] slows

down

point

and

comes

stop.

1-12

stop

It then

until the BOT marker is

again detected, whereupon,
final

complete

beyond the BOT marker.

moves forward

the tape

it comes to a

,(:

Rewind is used for tape positioning only and
has

effect

information

stored

the

tapsc

‘or in the memory.

Figure 1-6 is a functional block diagram of the TMB11/TU10W DECmagtape

System;

The processor initiates a TMB11/TUiI0W operation by addressing

the TMB11 registers via the address decoder and loading the operation

‘parameters into the registers.

The BUS CO-C1 bits specify an .out
-

transfer

(with respect to the processor) causing SEL OUT to be asserted

for the particular register addressed.

each register is

selected,

the processor places the appropriate data on the Unibus data lines

which is then loaded into the register with the SEL OUT strobe.

Thus,

the command register receives the type of operatioh to be performed;
~ the byteérecord count register receives the number of bytes to be
- transferred;

and the current memory address

the

memory address of the first byte to be transferred.
The command register selects which transport is to be involved in the

transfer via the SEL O-SEL 2 lines, supplies the functibn command to
"the command decoder which generates the required commands.
for the
tape

transport,
and asserts

"start

logic

senses

that

the

the
tape

GO bit to the
transport

start logic.

has

been

When

selected

the

(SELR)

and

is ready (TfiR), it asserts SET to the transport to start,the operation.
" If
a read operation is commanded, the transport command logic asserts
" FOR to the tape drive system which drives the capstan servo and moves
the

tape

forward.

When

the tape

speed

the

M8926

read

channels

are enabled
by READING and start to transfer data from the read heads

to the controller.

The read data from the tape transpoft (RDB-RD7, RDI

is checked for CRC, LRC and vertical parityverrOtS by the M8926 board.
1-13

if any such errors are detected, the THB11 errxor logic is notified ‘ (
(CRCE, LRCE, VPE)

for appropriate corrective action.

The tead data 18 supplied to the controller along with a read strobe
(RDS)

which signifies

the availability of read data from the transport.

RDO-RD7 becomes CHARO-CHAN7 and is gated to the data buffer register

where it is loaded into the registexr by RDS.
RDS also requests an NPR transfer from the NPR logic.

When the reques!

is granted BUS BBSY is asserted by the logic along with DATA-—»BUS

- which gates the output of the data buffer to the Unibfi@ data bus
via the register select output multiplexer.

(BUS D00-D15)

accomplishes this by asserting'either HI DATA BYTE,or‘#O DA?A BYTE fro:

%
;
;3

§ .

the read byte select logic according to whether the CHA register is
addressing the low byte or the high byte in memory. rhus,‘tha date (fi
byte from the data buffer will outfiut on either BUS DOQfDO7 or‘ z;,

BUS D08-D15.

of the

oAo AT

S e

pATA->BUS

The next character read will output
on the alternate hal:
|

data bus.

When the NPR logic

receives

BUS SSYN from the memory

it asserts NPR CLEAR BBSY which increments the byte-record counter and

the CMA register to prepare for the next transfer.

;

When the M8926 read logic detects the end of a record it asserts CRCS

(9 track only) and LRCS to the controller and RD CLR PLS to the motion

_‘.

control logic.

The motion control logic asserts EMD and STOP to the

drive to stop the capstan servo notor,
If a write operation is commanded by the command register,

the GO BIT,

in addition to enabling the start operation logic, raquesfs an NPR trai
When the request is granted, the logic agsar\

fer from the NPR logic.

TN TR

T e

1—14

et f

;’»tj‘

Maw

DTSN

VgL

’,ri}

[RE

(RNR

‘

20 A

SRRit i B Bl e T Ak £k M

)

[

LIRS

BUS

BBSY

and

that the
NPR

The
In
:

the

STB

tape

PR
L de, v 2o rR e L

the

and

write

ragah St
JECY 2

each

by 3 T,
R G
o ST, DbtL
ST L e S
e D U BT et
TT
o

ek
o
s 3

and

on the

which

available

the

data

asserts

CMa

start

speed
of

via
is

bus

(BUS

D00~
=D1%).

the

data

character

the

transport

either
is

the

drive

the

data

also

produces

write

the

tape

into

the

WbOo-wD7.

gates,

BYTE

the

low

SET

moving

CLK pulses
begins..

SEL

byte

with

the

BYT
or

transport

command

logic

forward.

Wher

the

write

WDR'(write

which

parity

along

two

transport

REC_pulses

heads.v - A

fThe

gate ocrresponding

system

WRT

indicate

bhus.

the

charactere

asserted

servo

sends

SEL

data

will cause

the

one

addressing

has

capstan

recorded

data

buffer via

the

enabling

character

operation,

SSYN

thereby

with

loads

operation logic

logic

tape

character

time

tape,

character

the

writing

the

responds

record

data

the

bxt

the

character.

data

generated

for

| character (9-track only) and
the LRC character on tape.
‘Each

‘4

and

channel

,characters
"

read

BIT

memory,

start

FOR

channels

The

location

CMA

enters

whether

byte

assert

the

making

mode

Meanwhile,

which,

thus

write

the

DATA

character

hlgh

memory

asserts

accordlng

- the

The

character

buffer,

data

MSYN.

first data

logic

data

BUS

"NPR

logic

a
2

data
WRS

to
and

character

pulse

isg

issued

written.

the

cycle

(not

The
is

the
to

WRS

cac

the

1~15‘

LRC

character)

controller

pulse

repeated

makes

Note

requesting

an- -NPR

that

isg

request

written
the

from

the

write'operation,

GO BIT makes the first NPR request and the WRS strcbes maks the

_ L\

aeéond and subsequent requests,. After the NPR logic issues DATA S?EME

o
~
it asserts NPR CLEAR BBSY which increments the byte/record counter aad

t2e CMA reglster to prepare for the next transfer.

When the byte/record

confiterAfienaea that the desired number of bytes have baen transfexred
. (written), it assettg CARRY OUT 2 which negates WODR Lo the
transport thereby signaling the M8926 write logic to write the end
of record chaeck characters

(CRC and LRC).

The fi8926 read logic is enabled during a write operation

and roeads each charécter right #ftex it is written.

Whén the read logic detectsz (reads) the end of the

record it issues a CRCS (9-track only) and LRCS strobe

| |

.'(-

to the controllei.

The LRCS gstrobe at the end of the record indicatefi to the contrcller

that the Aata transfer is completed.

The LRCS strobe is afipiied to

the done logic which then asserts DONE DELAYED to the bua'inter:upt'

logic.

The 1nterrupt logic requests a bgs interrupt to nofiif} the

procstox thag the command operation hés been completed and the THB11/
TUI10¥W

ready

for

another

command.

1-16

parity,
ing
lud
inc
tus
sta
ort
nsp
tra
rs
ito
mon
ic
log
or
err
The TMB11
erxor
rors and asserts ERR(1) to the done logic if an

CRC, and LRC exx
s erxors warrant terminating an
condition exists. Some typeof
il the end
operation befo

re it is completed while others

wait unt

(1) .

of the operation before asserting ERR
L4

ers DbY addressing the registers

11 regist
The processor can read the TMB

) via the

p:ocessor
and requesting an in-transfer (with respeet to the

the
fot
MIN
SEL
s
ert
ass
n
the
r
ode
dec
ts
rec
add
The
s.
BUS CO-C1 bit
to the
er bits out

partlcular reglster selected which gates the regist

data bus via the register select output

multiplexer.

manual.
s
thi
of
6
r
pte
cha
in
en
giv
is
11
TMB
the
of
ion
rat
epe
ed
Detail
the TU10W tape
Detailed operation o f

the M8926 interface board and

d along
use
be
can
1-6
ure
Fig
8..
and
7
rs
pte
cha
in
en
transport are giv
contained therein.

e e TR

R
ST e e eTE A

o R

A T

LTS
i

OSSRR
S
RS bR Sy
o SRV
© At 2 RO

"
‘ ’3,‘;‘ 5
H
VY ‘“‘"“4{&;

ms and flo w
ra
ag
dl
k
oc
bl
al
on
ti
nc
fu
e
th
th
wi

)
)tvl’

diagrams

K TBUS 0@ -DI15

UNIBUS
DRIVERS

D27 PO-15

SELECT
MUX

_BOT
BUS

BUS BBSY

DONE DELAYED

INTERRUPT

_BUS INTR

-LOGIC

SEL 1IN

M7912

llrl

CMA
REGISTER

WRITE

(REG 3)

CMA BIT @@

SEL 2 IN

BUS D@2-D08

SEL STATUS IN

'BUS BGX"

BUS BRX
TM

SEL 3 IN

J (VECTOR ADDRESS)

SEL 4 IN

M7821

SEL

S5 IN

DONE LOGIC

ouTtpPuT

M7912

—
e
—
- .

/1;

COMMAND
- REGISTER

M7911

(REG 1)

ER R (1)

M7911

[}

. CARRY OUT 2

——

Lete

R
S
RN

L RCS

BUS NPR

"UNIBUS

BUS

PSS

B8BSY

BUS

MSYN

BUS

SSYN

SEL 2 OuT
|

WRS

NPG

NPR
LOGIC

GO BIT
NPR CLEAR

BBSY

M795

.
o

STATUS
REGISTER
M7914

AN
T
\5\" ‘\\..‘u.
v
>'&'fi\\'\'u
N RN
TRG0
N
PR

COUNT

(REG 2)

—

DATA —-BUS

BYTE/RECORD
REGISTER

DATA sT8 2
M796/M782!

BUS

e QN

KIS
3 0 etNN . MRS

RDS

8US Agp-aAl8

BUS MSYN
BUS

SSYN

ADDRESS

BUS AQQ - Al8

(SELECT TTMmBI
REGISTERS)

BUS COo-Ct
MIO5/MT7912

SEL STATUS IN_

SEL
{ IN/OUT

SEL 2 INJOUT
_

SEL 30uT

M795

SEL 3 INJOUT

SEL 4 INJOUT

SEL 5 INQUT

DATA —=BUS

N
oo

NQ N\

RTINS

. Bt N

TMB1I/
TS O3
DECODER

e e *:». N

v oa, e

UNIBUS
RECEIVERS

D20 -DI5

M7912

N S\

4 \‘i

- BUS D@@-DIS: -

— MBIl

CONTROLLER __

Ml .
Ae

PTRYER

by e -

1-18

*«
4

‘~

)

GATE

\b s e

M7912

OPERATION PAR’AMETER‘S
.~
o

_—~— BYTE/RECORD COUNT

__ 16 STATUS BITS
—— CURRENT MEMORY ADDRESS

SEL 4 OUT

BIT @-7

' DATA BFR IN

GATE

]

| 'HAN @ -CHAN 7,

M7912

{\‘

| L)\(fl)

GATE

{

M7912

fi >

M7912|

g
3

B
PRl Je IS

.-;

A,
4
PSR
e

SELECT

lseL HiBYTE

M7912

—
EAD BYTE
SELECT

MI DATA BYTE

WRITE

DEN
5

WOR

—

M7912

—

READY | wrsS
DATA
‘o Cic
°%

M7911

GO BIT

L} e
. | TRe
d-

)

L—-READ

RDS (READ LOAD)

CHAN@ -CHAN 7

TRANS
ERS K
RECEIVPORT

RO2-RD7, ROP

7012

ERROR

osic

M7911

|LO DATA BYTE

Rwe. PEVN
—
NENV

’
SEL LO BYTE

’

]

START |o&T
|SELR
TUR
LOGIC
M7 b

RR (1

\_REV

OPERATION

ERRWI

'RITE BYTE

‘ié.__.
S Y\'_"i_WFMK
'

CARRY OUT 2|

M7912

N—

M7911

}———— WRITE
WRITE

*HAN-P (REG 5)

N\ FWD

2
SEL @-SEL

DATA BUFFER
(REG 4)

CATA STB 2
(WRITE LOAD)

WXG

T ot
B

wo@ -wD7

DECODER

———— READ

NCTION COMMANDS (READ,WRITE, ETC.)

‘

COMMAND

BFR .
DATA
OuT BIT -7
‘

LO DATA BYTE

MT7912

it SR

SFORST
TRANDRIVER

Hi DATA BYTE

|
MT912

e
Lo
:

)

B
-

TRANS PORT®

STATUS

. CTOT

LOGIc.

4 CRWS

CSPWN oo

CEot

Rot

E%SV:

B TYR
L

«—S3ELR

. _SDWN|

—

< CTUR

;QRL —

- vy

< IIRK

chcH
< cwil

‘

~MOoL
!

csELE -CSEL 2,
;fWRE

;]RWD

_
3

RWND

ycpeng

\ CSET

\.—é&&.}.
SET

» CWF MK

’

;

md~ <32
.'
are

> CRDENS

S CINIT

{

.
o] COMMAND

pen &
DENT

v CWDR
¢ CWRS

;

CHANMELS

wReT

CWRE

PARITY

N FILE MARK

.Jflzau1P+.

—EWEHX

1IRK

TAPE
TRANSPOR

EWFMK,

L
WRITE

cwbg—-cwbd?

G ENERATOR

— GENERATOR
END

wDP

D
RECOR

cLK

LRC.

STRB

GENERATOR

[

DRV SET PLS,

v CWXG

SToP

T START/STOP

EMD-

ACCL
cLock

MOTION

SEY

CONTROL

EADING

RDP

<CBDP" cRD7, ®DP

S SNl

- CRDS

P
‘4L,‘_‘, rem g
A v Ll T e
T L

ROE=RDE,

OuTPuUT

READ

GATE

<j:

ROE—RD7 RDP

CHANNELS | ¥y

RSDO

)

-_*—-! | FILE MARK 4_;,1_'[&&
DECTOR

ALY

é_CLRCS

<8R CLR

END

RECORD

_PLS

DET ECTOR

-a CVPE.

ERROR

—w CCRCE

<LERCE

DETECTOR

|
|

ReAD

| LoGIC

e
AT REN e
e SNSRI
LA S

l—,‘

o~
:

;

R S TSR AR
AR A T B L A LA

LN (R

U R N IS

A CHSRO A B L R

PEPTETTESTDT L

O R S

!
V
P
R
T
T
'
N
ek el M Lot wded csnny F T
Bk

(RE

N 1
S

NP I

T8 MAGNETIC TAPE TRANSPORT

TUIC W

LOGIC B WRITE

SUAVE SELECT
COMMANOS:

(MBN0)
<

]

FwD ,REY .RWND B WRITE

OF F=LINE

SIGNALS

‘I

'
)

9 9 2 (;

WRITE DATA LINES

ket S

z NTER FA( E

RECORD

- —

DPPER REECB BRAKE DRIVE

DRIVE

ENABLE
- VACUVM MOTOR
=
————

080

t VACUVM SWITCH SIGNALS

——e c:DD SERVO
‘LMR REELE BRAXE

REWIND CAPSTAN

LINE

Pl B OAR D

REV/REW

MEDIUM ONL WRITE

)

FOR | POWER BOARD (HG06)

SWITCHES

« INDICATOR1 |NDICATORS

SLAVE SEY PULSE

)

CONTROL
PANEL

CONTROL

VACUUM

SYSTEM

:J ‘

HEAD

DELAY (MB8911)

SLAVE CLOCK B8 MOTION

READ AMPS

(GO56)

|
READ

DATA LINES

READ

ENABLE MOTION DEL AY

ACCL

WRT CLK

‘

RSDO(READ STROBE DELAY OVER)

‘

THICW

wam® POWER
SUPPLY

SLAVE BUS

)

“»

TMB11/TU10W Eunctional Block Diagram

Crrpe e

-1

1.4

APPLICABLE

DCCUHMENTS

- Table 1-3 liata documents that are applicable to the TMNBIi1/TUIOW

(

DECmagtape Syafem.

Title

Number

861-A;B,C Power

EK-861AB-MM~-

Controller Maint. | 002
'~ Manual
|
TU16/TMO2 tape
drive system
Kaint. Manual

Processor

Contains theory of operation and
maintenance instructions for the
TU16/TM@B2 tape drive system

‘manuals

that provide

general handbook

system

the

PDP-11 Peripherals|112-00973-

detailed

that

architecture,

asysten

discusses

addressing

modes/

instruction
set, programming

techniques,

and

)

software.

A handbook devoted to a discussior.
if

2908

the

description of the basic PDP-11

1‘
|

o ‘«L’&'v‘:,d—-"__"v.‘fl.fl&“-‘ isvg;‘?su ¥ e

for the

A serles of maintenance and th%ézy~

Handbook

Dascription

maintesance instructions
861 Powex Controller

" Manual

Contains theory of operation and

EK-TU16~MM~002

and Systems

PDP-11

PDP-11 Processor | *

Documents

Applicable

1i-3

Table

various peripherals

PDP-11

geysters.

‘detailed

theory,

descriptions
of

device logic;
construction;

used with

also

flow,;
the

provides

and logic

Unibus

and

externs

methods of interface
and examples of typical

interfaces.

DIGITAL Logic

Handbook,

1973-74

Edition

|
;;

Presents functions and specificatianfi

of the M-series logic moduleg,
sories,

‘TMB11
.

Eaite

N
M

Controller

DECmagtape

-1

types

used with

and

tha

Transport.

logic

used

acces-

the

TZ10W

Includes

produced

PDP-11

DEC

other

but

not

devices.

and connectors

GGPB-D

Handbook

dump;

the

detailed

Bsoftware
edit,

programs;

INY... AU

R
. AP RO~ ol ST N

SRR
N KPR

Provides

PDP~11

SoftwareDEC-11-

Programming

aanary s

ay
L

Paper-Tape

assemble,

input/output

floating-point

and

discussion

systen used

—

and

the

to load,

debug

PDP~11

programming;
math

package.
|

‘

an
i
\

taApplicable manuals are furnished with the system at time of installati@
- The document number depends upon the specific PDP-11 family procsssor.

T Use the processor handbook unique to the actual CPU.
’

1-22

1.5

_ (

SPECIFICATIONS

‘Table 1-4 contains operational, environmental, mechanical and
-

electrical

specifications

Table

Category

1-4

for the

TMB11/TU10W
Tape

TMB11/TU10W

Specification

Storage madium

1/2 in.

Specifications
-

tape
| Capacity/tape
Data

Systen.

Specifications

Parameter

Main

Drive

reel!

transfer

rate|

Drives/contxol,’

(1.27 cm) wide magnetic

(industxy

million

36,000

compatible)

characters

char/sec

maximum
Data

Number

Organization

tracks

Recording

Density | 200,

Interracord

gap

556,

0.5

in.

800 bpi;

(1.27

program

co)minimum;

selectab.
0.65

in.’

nominal
Recording

method

NRZX;

industry

Tape Motion

)

Spead;
'

Forward

and

Tape

speed

150

drive

distance
tine

Tape
|

Thickness

1.5

mils

8.0

diameter

hub

~Mechanical
~

TMB11

Controller

‘

Tape

drive,

mounting

c=m)

(0.038

(227

iron-oxide

coated

m=m)

qg)
-

10.5

(26.7

cm)

|3+69

(9.37

cm)

diameter

(industr:

g5 e y
T

[tyLT=

B,
4
DTS

g
(&

s mrad
Y ———
T
e
s mne )t .
T
T Y

- {a

TR LUe
A

(731.6mn)

base,

Tension
| Reel

columns

£t.

Hylar

vacuum

(6.3=:m)

(1.27

Reel

,
in

maximum

2400

Type

0.5

Zength

in.

B
:

(3.8m/sec)

capstan;

0.25

‘

Width

in/sec

single

gstart/stop

Charactexristics|

(1.14&/3@&)
|

Start/stop

'/,

in./sec

Reveaerse

Rewind

N
2 L
e

CoR

compatible

‘

standarc

Mountas

system

unit

Mounts

(48.3

cm)

a single

16-1/2X2-1/4

(41.9X5.7

slides

standard

cabinet

TU10W Transport

(without

cabinet)

Depth

width
Height
Weight

o
25

in.

(0.64m)

in.(0.48m)

in.,

(0.66

150

(70kg)

1-23
m)

in.

cm)

861

Power

Controllgr

Dapth

in.(0.20m)

Height

in.(0.13m)

Weight

width

Incezehannel

Write

Power

Input current

|Erase head

'Full width

(TU10W)
Input Power

'47

:
4A

115V;

i1115/230Vac

Frequency

230V

132W at

%+ 10%

Hz;

o
230V

single phase

Temperature
Relative

|
:264W at

Voltage

. 9A at +5Vdc

(THMB11)
Input current

Operating

(1.92m) maximum

(1.9xm) maximum

754 in.

Displacement

1lb(4.54kqg)

v§75fiain,

. .

.Read

Envizronnment

19 in. (0.48m)

15°c to 32%*

humidity

i{20%

80%,

with

maximum

wet

bulb 25°C and minimum dew point
29C (no condensgation)*
|

Miscellaneous

i e

Altitude

BOT, EOT

detection
Broken tape
detection
Magnetic

L AN NG S DO i

8000

head

(2438m)

Photoelectric sensgsing of
reflective strip,
Vacuum fail-gafe

Dual

gap,

read

industry
|

after

compatibl
|
{o
e

write,

(0.4cm) gap

Electrical

*Magnetic

tape

operation

skew

is more

Write deskew only. Read skew
mechanically aligned
-

reliable

the

temperature

to 40

to 60%.

Eoliar i v
-SSR

R
Sl ot ool
b et

,1‘_‘\,

‘limited to 65° to 75°F (18° to 24°C) and the relative humidity

1-24

SRR
|/

0.15

in.

CHAPTER 2

UNPACKING, INSTALLATION,
AND ACCEPTANCE TESTING

2.1

SITE PLANNING AND CONSIDERATIONS
Space Requirements

2.1.1

arances required.
Figure 2-1 ijllustrates the space and service cle
ent out of the
ipm
equ
the
de
sli
to
ed
vid
pro
be
t
mus
ce
spa
te
@ua
Ade
TU10W DECmagtape
the
n
.
o
or
do
nt
fro
the
n
ope
to
and
ing
vic
ser
rack for
te cabinets.
ara
sep
in
sed
hou
are
11
T1B
and
0W
TU1
The
.
fransport
, consideration
If the cabinets are separated by long distances
ing ducts for the cablinga.

ey
:

’-should‘be given to overhead trench
Powver Requirements

2.1.2

Pg
=

from a nominal
ed
rat
ope
be.
can
tem
Sys
e
tap
mag
DEC
0W
TU1
11/
TMB
The
tage should be
115 or 230 Vac, 50/60 Hz power source. :Line vol

PUOR
V. sty P e LU

1 s

ORI S

maintained to within 10 percent of the nomial value

e BEiales = SR (7PN LL S

uency should not vary'more than 3

Hz.

Environmental Requirements

'2.1.3

Eveie

and the freg-

PRSI
g 2e
il b Y NE
SR S PPOAes
.oy

e
‘The'TU10W DECmagtape should be ljocated in an area fre

of excessive.

e
AR IR
PR
.T
R
T

To ensure proper
.
ors
vap
and
es
fum
ive
ros
cor
or
t
dir
and
st
"du
t the top of
leat
in
fan
the
and
t
ine
cab
the
of
tom
bot
the
', ~cooling,

ironment should
the cabinet must not be obstructed. The operating env

ge of'15o

have cool, well-filtered,‘humidified air; a temperature ran
to 27°C; and relative humidity of 40 to 60 percent.
-

UNPACKING

2.2

installed
ns:
tio
ura
fig
con
ent
fer
dif
two
in
d
ppe
shi
be
may
E11
The TMEB
ing and installaf
in an equipment rack or packaged separately. Unpack
figuration.

e system con
‘Procedures vary depending on th
2-1

e T E

R Ly

PRI

R T

NP SR TR

T
A R eO
TR RO
e TD
S Sl ST R S e

SRR T TR IR

RStA

YTy

TnPR RS
PSRN SR
ANBN
S S LR SSUREI LSN& S ‘T'Xh‘flv(
b SIS NS
T Gs BL T
S

L AR

B ISAU
3

S R

For example,

SWINGING DOOR
\ (RH) NOTE 1

SWINGING DOOR

|
(LH) NOTE

€

)

’/9

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REMOVABLE

+ -

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CASTER SWIVEL

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NOTES:

—

TUiow

FROM CABINET

’

2em) ) |
(7638”

@ 25

€ TM)
poicaml (2.8
,

‘

#-3092

‘
a

.
-

.
|
fp— — — — — = — — — —J'—MM—

(floor line to cabinet top).

LEVELER
4 PLACES

7$53 EXTENDED

.2 cfgMit 7172 us2.28cm) high

MAE o
g ”’T?"Ffl'?*l

o
st N
!
o

1. Door maoy be L.H.or RH.
Allow spoce for either case.

’e

"54.87 cm)

(4) CASTERS

PORTS

]

1)
7N

FAN

”V?M
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Space and Service Clearance, Top View
.

Figure 2-1

(

M_j
XY /39
)
S &M 03? d C:

|
:

- RADIUS 2 1'3/3;

REMOVABLE

/END PANEL

---

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.’a’

‘CABLE ACCESS ——

2.2- "

f BP0
S A BT

,‘:3

RSN

R AL LR AL MR

the

;

Pbk v B 4 S

user

L [ S SX

has

i i

Loi

P
i

ordered

’.

‘

‘i

‘

complete

YL
mr
ie vl

PDP-11

system

'shipped installed in its appropriate rack.
part of
basic

the

system i1s

PDP-11

system,

appropriate

2.2.1

shipped because
then

cables.

TU10W

the

TMR11

Cabinet

the

;

[EESRAY WU PO
E
FR VR CORUAITICE
Y ST ¢JU U S0 SN GETE SO URYWY

TMB11

However,

if onlv a

user .already has.a

shipped

“

the

)

separately

with

Unpacking

_To unpack the cabinét, proceed as follows:
1.

Remove outer shipping éontainer.
NOTE

The

cqntainer may be

either heavyA

corrugatéd cardboard or plyfiood.

either case, remove all metal straps.
;

- first, then remove any fastefiers and
-qleats

N
L

'~ framing and supports frém'around

the.cabinet perimeter. -

'ff

2..*RefiOVe the polyethylene cover frofi the cabinet.

container-to the

skid.JIf applicable, remove wood

g w0 PR

Remove

Ra
sy
iy

LD,SR

securing the

Year

the

tape

access

plastic

shipping

pins

from

the

cabinet

door.
~

Unbolt

cabinet(s)

located

from

the

shipping

the

lower

by opehing

the

access door(s).

Raise

the

leveling

supporting

feet

above

side

skid."The
rails

Remove
the

the

level

and

bolts
are

are

exposed

bolts.
the roll-around

casters.
Use

wood

blocks

the

floor

and

planks

carefully

roll

form

the

ramp

cabinet

from

onto

the

skid

floor.

LEUB

oy Tl
by 3, T

Roll theAsystem to the proper location for installation.
2-3

the

2.2.2

TMB11

Urnpacking
e

controller check the shipping list to

Before unpacking the TMB11

ensure that the correct number of packages has been received.

.Check the shipping list for the correct TMBI11 module types.
caxton.

shipping

from its

each device

Carefully remove

2.3 INSPECTION

After removing the equipment from its‘container(s), inspect it

and report any damage to the responsible shipper and the 1éca1.
follows:

1Inspect

Office.

DIGITAL sales

and panels

indicators,

switches,

for damage.

Inspect all

Remove equipment covers where necessary and inspect

for

loose or broken modules, bldwer or fan damage, and loose
-

nuts,

etc.

"%
.
,
rial
s
te
t
n ma
n
reig
foe
dn
o
mpan
o
c
al
rn
te
ex
e
loos
S

wires,

Check TU10W transport(s)

for any

foreign material

that

Y A

screws,

Inspect wiring side of logic panelsAfor bent pins, broken g

bolts,

may have lodged in th¢ tension arm, reel hubs, and other
parts.

moving

¢Check TU10W power supply for proper éeating of fuses and

e MT

T 1y
w

power

connectors.

Inspect

each

TMB11

module

for

shipping

damage.

T e

2.4

TU10W

CABINET

INSTALLATION

g R

To install the TU10W cabinet, prdceed aé follows:

- |

Lower the leveling feet so thét the cabinet is resting

on the floor; not on the roll-aiound casters.
2. Use a spirit level to level the cabinet;fensufe that all
leveling

@ ‘;‘;’WJ;},A‘K%}”? + h } ;»S —;!‘;, 4.1‘: Cop i
i

g,‘._,:{“‘.,‘i‘,
i

P
A
L

feet

EEE

.
A

HAEN
d

)

s ;

.
SRR
B
!

i
N

TR »“',.‘ T f I
R.
.

el
.

firmly

2-4

the

floor.

’ ‘« - ,.' '[\’ }fo{ ;3 :}n N DR

. leg 5 z) ‘n ;. ,‘- e ‘~ e ! ‘Y X { TT,.‘H‘:"S"{ W -1 ] i AATNEL 1

Coah
o

are

[

e
.

;

i
.

T i L S . LRC
iy

[

P
.

[
.

LA
HERNIE & A
I
oy
.

T T T

i
o
.
i
A
o.
.

A ‘g&,,fi?,! {{ by

the
3. Remove the shipping screwvs that secure

equipment

to the cabinet.

together,
4. If two OY more cabinets are to be polted

install

inets as shown
filler strips (p/N H952-G) between the cab
ure the cabinet
in Figure 2-2. Tighten the bolts that sec

ts are level.
groups together and then recheck that the cabine
the site plan,
5. After the TU10%W has been positioned per
the transport
loosen the two shlpping brackets that secure
ure 2- 3)
to the rear of the cabinet frame (see Fig
NOTE

REN ) Lo

ST
L
WUREET el
e eais, WD
IR0 R

If the TU10W is to be reshipped or
installed in a hew location,.the shipping“
brackets should be repositiened and

Soper

P P LRI,
T LTSV ST

tightened.

and the TU10W cabinet are
Fnsure that the THMB11 cC abinet

"tied to the same ground or install a ground

strap between

the cabinets.

7. If necessary, clean all outer surfaces.
2.5

TMB11 Installatlon/Cabllng

2.5.1

System Unit Installation

Ensure that power is removed from the

PDP 11.

the
1. Extend the expander box on its slides and remove
‘access cover.

usi
2. Install 2 TMB11 system unit into the expender box

%@5
L

(An extended BRA11K and BEA11F box is shown

in Figure 1-2.)

module

the two captive SCrews (Flgure 2-4).

t-on

fas
3. Install the option power harness by connecting the
‘

2-5

p :

‘

|
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’
]/‘f B
T

|
71 7716 |,

[

’

|
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NOTE:
-

\_/\H

FILLER STRIPS

ALL DIMENSIONS IN INCHES

H-apes

H950 CABINET

HS50 CABINET

—#
VERTICAL MOUNTING

le— VERTICAL MOUNTING

MEMBERS

| i o T4 e T WL

SOl

L i

Figure 2-2 Installation of Filler Strips

TRANSPORT
CRUCIFORM

B2,

[,
e
Y

s 4

______ _...’.)1

SHIPPING BRACKET l

CP-0099

Figure 2-3 Transport Hold-Down Shipping Bracketg

—

2-6

V
.
.
)
B
-

.
.

e
.

“d

oty

fra—
et
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~ TMB11 SYSTEM UNIT

RIS

Figure 2-4

iy e

Cenamis,

Desend

Toate

aeiade

Expander Box Backpl

ane (BA11F box sho

wn)

e
s
_—

—

RIS,

ey
-

.
——

SOUN

—

caeam
o

——

oY,

)
’

‘
.

connectors

Plug(s)

the

syster

expander

unit

box

backplane

(Figure

and

the

harress

2-5).

Dress the option power harness along the top
of the BRAY1F
-

expander
used

2.5.2

the

box

dress

Module

the

shown

harness

Installation

Figure

2-5.

underneath

the

BA11K

expander

box

{:}

box.

1.¢<Check the Jumpers on the N7821 module tor
a bus lnterrupt
address of 224,

)

“

~2., Check the prlorlty Jumoer.on the M7912 modu
le for the
‘correct lnterrupt prlorlty level

(usual‘y BRS). )

3..4Check the Jumpers on the M105 module for
the correct‘; |
haddress range for the TMB11 reglsters (772520 to
772536)
4.

Plug

tne

51x

TMB11

modules

and

M930

into the system unlt accordlng to Flgu
res 2
6,‘2 7,
englneerlng

draw1ng
.

..,

V-

,'.\' "

Unlbus

and

BD~T%B?1-fi-7

P
-

—

2.5.3

termlnator module

A R
IR

e
-

DRI

Y
S

)

_'u..x;_

Cabllng-—System
o,

unlts

are

connected

the Unlbus

e
P

dalsy chaln

'yUnlbus

in-

~Un1bus

1nto

fashlon

shown

Flgure

and a Unlbus outJack |

the

flrst

system unlt

BC11A

M920

Each

cable

unlt

connects

Jumper modules

has a

the

connect

‘the Unlbus to the other system unlts in
a glven conflguratlon.

M930

terminator

module

1nstalled

the Unlbut

out
Jack

the

—

- last

system unlt

another

expander

in the chaln.
box,

BC11A

-If the
Unibus

Unlbus

cable

to be

used

carrled onto
connect

the

Unibus from the Unibus out-connector of
the last system unit in the
first

box

the

Unibus

in- connector

The

Unibus

second

box.

out- Jack

the

last

termlnated

system

the

first

unlt

M930

systen
module

2-8

—

Y—

p—

an e

BR
——,

-y

unit

the

1nstalled

_'tc

_'f:)

(

.
.

.
’

'
i

’

’%r

)

@
.
.
.
.
.

.
A

)

o0 .

.
-

OPTION POWER
HARNESS PLUGS
st oy
A B AR5 MRS+ AT A P BANS N TP e APO AWk
.

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.

)

L e
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Tann

ek,

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MRS

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&

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Sornht

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5

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g
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BRI

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2-9

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R i

- .. - B e R T e i » SN

-y

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‘ e NS B2 B W A R $rar4

. .._'-

i g of TMB11 System Unitit 1n
in BAI1F B 0X
Power Cablin

|
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POWER HARNESS

)

D
o

eV ANAR

e v e memeoa

- .e

CABLE STRAIN
RELIEF
[

BC11A UNIBUS

OUT CABLE:

‘

TR T
e

AL o By

g, el

-1t

ke
e

-3

7 'BC11A CABLE TO

. TAPE TRANSPORT
T

Mo30

—

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M920

cereees

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M7912

LBeT

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Nad

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ejery

XD..:&

WMTW

- M7911

e
A

7997-1
Rl

Figure 2- 7

TMBI1 Module Locat ion a_nd Cabl ing in BA11F Box

2-11

InStall the Unibus in-cable, Unibus oot-cable, M§20 jumper and/or
M930 terminator according to the particular configuration.

The s

Unibus in-connections on the TMB11 system unit are slots A1 and :w%
The

Unibus

out~connections

are'slots

and

(Figure

2-9

and

englneerlng drannGBD-T%E11-%~7). The conflquratlon shown‘ln Figure 2- 6

utlllzes a Unlbus ootcable and an M920 brlnglng tfie Unibus in from
'the next systefi.device,' The oonfigurariondshownoio Figore 2-7
usestQZO jumpersAfor‘both'lnpur and ootfiut.Unibus connections.
|

fiOT#‘”‘

.BCllA"cebletoonoectorsloill.pldginfo‘tfie
system‘pnits“elther wey bot will hotlfully seat

'ifsincorrectly lnStalled. lfieke sure the oon~
‘heororsferehfolly‘seated'andthet'the ootchesA
on’the conhector edées are up.agalnst the system'

. - ‘(j

unlt slots.

2.5.4

COntroller/Haster brivo'Ceblinqe-Connecé the BC11A caEIe to

slots E4 and F4 on the system unlt (Flgure 2-9)
_M930

termlnator

cable.
V:Z;S.S
-

1nto

slots

and

termlnate

the

(Flgure 2 6 and englneerlng drauing 33-53311-9-7)

Securlng Cables--If the 1nstallatlon is performed in a BA1IF

expander

through

nodule

Install an

box,

the

lift

the

cable

trough

and

the

trough

cable

cover

holding

the installation is performed in

and

feed

the BC11A

cable(s}

bracket.

a BA11K expander box,

perform

the following:
=~

Remove

the

one

other

screw

(Figure

from

the

center

strain

relief

and

loosen

(

2-6€).

2-12

G e

e b amaaa

e ot

s dams Wb

4 B

Wems

ey .

b g

b b by v are A

e ar

ot
e
e e 4

e -~

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— -t
TM ."

TO NEXT

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ay o as bt
ot s e
3 o wonat A
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ok U

I, .

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dime
e e R

e AT Fhee

- amte alep®
ey
T e @i

e e i m il

e At gt e
s b o

A T

(T !

BC1IA

UNIBUS

cABLE

EXPANDER
BO

M930
UNIBUS
TERMINATOR
MODULE

(IF USED)

M920

, UNIBUS JUMPER
MODULES

BCit
A

UNIBUS

)

poaits SREAPTNE R

CABLE

SYSTEM UNITS
-

;

outr

—

(NOT SHOWN)

E4 —

UNIBUS
IN

U NI

SOURINIEE S

(oS oo 0

oS
i Wyt

B et i e R u.w,‘*‘w,»‘“g K

)

" TAPE
(NOT
TRANSPORT { SHOWN)
10

R
R
LY RSN

ORI

Figure 2-9

‘

7941-1.

TMBII Mounted in System Unit
2-13

nean

e bt
N

Al Rt

ke S Wi

against

the

edce

the

and piace

out

the strain relie!

Swing

BC11A

the

caxnle(s]

chassis.

i?é

Swing the top of the strain relicef lkack into place.
4.

the

Insert

TU10%W

screw

removed

screws.

both

tighten

and

Cabling

Siide.ghe TU1PW master transport out of the.éébihet.

Remove the‘M8926 inteffacevfioard'from the transport
system unit aésembly.

Install 3851vedge'cognector§‘on the J and K jacké of the
| A |
|
)
¥M8226 board (Figuré 2;10).
If there is only one Tfi1fiw in the system (thé'fiaster dfive)'
install HS8800 terminators intovjacks J1, J2 and J3 as
shown in Figure 2-10.

Feed the BC11A cable from the'TMB11 through the slot between

the system ufiit and the logic sheet-metal chassis (Figure 2—11)iij
If the system contains two or more tape drives, route
‘three

BC@P6R

slave

bus

cables

through

the

same

slot

used

'step 5 but from underneath (Figure 2-11).
Position the MB8926 board’in'its approximate location and

on the M8926

(Figure 2-12).

multidrive

PSR

2t P

e SR TRMRS

connect the BC11A controller cable to the HSST edge connectors

this

"slave

cables

the

cables

Mark

the

BC@6R

J1,

that

the

slave

system,
and

smooth

connect

the

side

the

MES26

three
board.

up (Figure

BC@6R
Connect

2-13).

cables.

- Insert the M8926 board into the system unit.
10.

If this is a multidrive system, secure the slave cables
with the cable strain relief (Figure 2-11).

) (:
|

iufi

2-14

[

R
i
s

€

HSEO00

TERMINATOR (3)
|

ity

HRS1

EDGE

CONNECTORS

M8926 with H851 Edge Connectors and H8800 Terminators

F|G. 2-—’0

O
J

e T R L

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T T

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LI T

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CoNv TROLLER

BClA

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CABLE

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YRN

CABLE

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BC11A

and

#LR CABLES

NE¥XT

Routing

STRAI N

RELI EF

BC@P6R Cables

DRIVE

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i

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HRSI

EDGE

COMNECTO

COIVN ECTORS

|
|
FIRST SLAVE

Hesl EDGE

)

MASTER DRIVE
‘

-—,-__|

(

‘

~ UNIBUS IN.

'
|

'*
|

—ane

\ |
R

—~

Rl A

|§%o'g;f£

SMOOTH

SLavE

CABLE

M920 JUMPER

[L—*
4

' COLORED

;

) !

—

/-5an£ CABLE

M930 TERMINATOR

,o
:

(

~
o

EXPANDER_BOX

—

‘
! ~

T] .

sTriPe \_|

SYSTEM UNIT

4 J3

|
'

BIDE UE

&.'-

. 1

SIDE UP

BC1A

ChRBLE

N 'COLORED
STRIPE

‘

CONTROL LER:;\.{:~ 'l

[

‘e

2""3

FIG

(

TMB11/TU10W Master/TU10W Slave Cab;ing Diagran

2-18

T o

e By Uy PPN M R SRS4

Pi——

urereany

m——

O——

ESw—p—

FIRST

|
l

Vi2a21

|
|
I

ROUGH S/o

178

iJ
|.

|
g
L

SLAVE

COLOKRED

COLORED
STRIFPE

STRIFE

l
|

RCUGH SICE

/ L__,_Lfi

|\ 510 UP )
COLORED
STRIFPE

COLORE D

STRIPE

M22dI-YA

RCUGH SI1DE

+E29

;

I i
(Y]
rn

(OLORED

—

/ ur

STRIPE
—

—

—p—

|
|
.

“IX IS
e,

E——

—

—— -

&<
(OLORED

S7RIPE

C——

GRS

—

2-19

e
n
——t

system

12.

unit

the

slave

Lhe
£

and M2001-YA

transport

(Figure 2-14).

Connect J1
Twist

M22313

Remove M9001,

LT}

11.

on M8926 to the input jack on cabkle card M90015i}
BC@O6R one-half turn

to‘obtain

the

color

stripe

and smooth side/rough side oriehtation shown in Fiqure 2-13.

13.

Repeat step 12 for M8926-J2 to cable card M8913, and
18926~
33 to

cable

card

9001 ~YA.

14, If this is atwo—drive’system, install H880b terminators
in the output jacks of M9001, M8913 and.M9001-YA. ~If the

system contains more than two drives,iastall BC@6R
vcables in'daisy-chain fashion from one drive to the other

observingthe colored strifie and'smooth.side/rough side
orientation shown in Figure 2—13;"Install HB8800 terminators

»in the 39001,M8913 and M9001-YA output jacks of the last
drlve

15,

the

{

chaln.

Pluc the 861 power cord into a power receptacle.

16.

Set

the

861

c1rcu1t

breaker

the

p051tlon.

T?.W'Sllde the TU10W transport(s) back into the cablnet.
2.7

Acceptance Testing

Refer

‘and

Acceptance

A-SPTU1OW
-@- 3

TMB11/TU10W

T T

tape

Procedure,

for

drive

the

Engineering

acceptance

Drawing

test

Nos. A-SP- TU16
-70-8

procedures

for

the

system.

g o

TEmme

PRI

Can

OGN

o ————a S

S @yt

—

e S

|
(|

M&T2b)

MEFI]

M eeir

‘MT00/~YA|

MEYI2

METIL
|

A. MASTER
TU10W

( | FlG. 2"‘4}-

DriveE

System

Unit

Mool | METO | pyeqiy

MEID | g | ¢ hsh

Module

Backplane
2-21

Siave

Location,

Viewed

DrRive

from

g.gf\s“(j

CHAPTER

e RA T

I T

T e

SYSTEM O‘PF;‘“RATING INSTRUCTIO&S
and Indicators

Controls

3.1

at the ieft of -the
fhe operator control box (Figufe}3-1) is located
file reel.“iThe functions of the control box switches ahd indicators
are listed in Tables 3-1

and

3-2.

Operating Procedures

3.2

3.2.1

Application of Power

h in
1. If the 861 Power Controller REMOTE ON/OFF/LOCAL ON switcis
the REMOTE ON position, TU10W power is controlled by the processor
POWER key switch, This method is used in normal operation.

2. If the processor POWER key switch is not activated, TU10W power
may be turned on locally by setting the 861 Power Controller

REMOTE ON/OFF/LOCAL ON switch to LOCAL ON.
used during

This method may'be'

maintenance.

- 3.2.2 Loadin§ and Threading Tape--Use the followingiprocedure to
mount

and thread magnetic

tape.

1. ‘Apply power to the tfansport..'Place LOAD/BR REL switch
|
|
to center position.
2. Place a write enable ring in the tape reei groove if data
is to be written on the tape.

Ensure that there is no

ring in'the groove if data on the tape is noto be erased
or

written

over.:

o |l EnDIFILE
pwRllLOAD || ROY || o7 |} 567 || pror

OFF
Ofre |l seL || wRT

‘

|{Fwo || REV

||REW

ON-LINE

START

OFF-LINE

STOP

LOAD

FWD

UNIT

SELECT

REL

‘

REV

’

Figure
@

10-1267

Operator Control Box

3-2

)

syl

3. Mount the file reel onto the lower hub, with the groove facing
'\_:

"toward the back (away from the operator). Ensure that the reel
is firmly seated against the flange of the hub and that the reel
hub is securely tightened by hand.

To tighten the reel hub, turn

it clockwise. Do not grip reel by outef flanges.
brakes are on while tightenind the hub.
Table 3-1

Ensure that

TUT10W Cohtrol Box Switches

Switch
' LOAD/BR REL

LOAD position

Canter position

BR REL poaitioh
ON-LINE/OFF-LINE

ON-LINE position
OFPFP-LINE position

~ FWD/REW/REV

FWD position

REW position
REV position

'START/STOP ition
STA: RT pos

gTOP position

(plug activated)

UNIT SELECT

Function

]

Nkiogsct

motor, which draws tape into’
Enables vacuum
columns.
the buffer

Disables vacuum,motor;’brakes.are full on.

Releases brakes.

Selects remote operation.
Selects local operation.

ward tap:
s not initiate, for
"~ gelects, but n doe
transport is off-line.
motion whe

tiate, tap:e rew» ind
does isnotoff{ni
ectns,trabut
Selwhe
-line.
nsport

te, reverse tap
5clects, but does not initia
off-line.

motion when transport is

S W/
<
/RE
FWDne.
by
ectised off-li
ionnspsel
e nmottra
testchtapwhe
tiaswi
Ini
ort
REV

any motion commands when transport
Clears
off-line.
is

|
unit by number
nsp
tra
e
tap
the
calects s number is ort
used in the program

(0-7); thi

addre:
to address the tapce transport (slave

3-3

e me,

e e wm—

) Se ot o —

- WS

Table
Status

3-2

Indicators

Indicator

Function
——
e

AL
it

—ne

TR
e g
S e

. — o e

PWER

Indicates

power has been applied to the transport.

LOAD

Indicates

the

into

buffer

RDY

Indicates

on
LD

the

that

and

the

tape

of
PT

loade d

colunmns.

the

tape

settleedown

transport

delay

ready

complete)-

(vacuum

tape

Indicates that the tape is at load point

END

and

vacuum

motion.

(beglnnlng

tape~-BOT)

Indicates

that

the

Indicates

that

write

the

enable

tape

end

point

(end

tapeA

--EOT).

FILE PROT

write

OFF~LINE

Indlcates

local

'SEL

Indlcates

the

-controller

operations

ring

is' not

operation

tape

that

write

FWD

Indicates

that

forward

REV

Indicates

that

a reverse

REW

'Indicates

that

5.
6.

the

step

Place

Manually

the
!/«

the

Wind
the

tape

LOAD/BR
unwind

reel

REL

tape

four
in

from

turns
the

(at

switch

guides ‘and head

about
tape

take-up

the

control

selected

because

file

reell.

(;

box.
by the

(program)

,Indlcates

Install

inhibited

mounted

transport

WRT

are

rewind

the

operation

file

tape

onto

command

has

been

issued.

command

has

been

issued.

using

BR
reel

assembly as

been initia ted.

command

top)

the

has

REL
and

shown

the

has

the

been

same

issued.

procedure

used

position.
thread

the

in Figure

take-up

tape

3- 2

reel.

Ensure

t hatA

guides.

memmra
e

¢ e

om0 (b R

aanl
LR Lt
S BT

TAKE-UP. REEL

(UPPER MOTOR)

TAPE GUIDES (2) —
fi«

'~~-

CAPSTAN

:
| o

TAPE MOVES INTO BOTH

‘

|&
:

I
|

VACUUM COLUMNS
__|

WHEN "LOAD" SWITCH
IS PRESSED

3
|

\\_~——HEAD TAPE GUIDES (2)
()
|
R/W ERASE
i

HEAD ASSEMBLY

Y S

|
¥

W
'

TAPE PATH
WHEN LOADING

]

o
-

|
\

/
o

)

FILE

REEL

(LOWER MOTOR)
10-1308

-2

Figure ¥ Tape Loading Path

”

Place
into

the
the

©Select

When

LOAD/BR
vacuum

FWD

the

and

BOT

REL

switch .to

the

LOAD

pesition

draw

tape

'(f

columns.
press

marker

START

advance

sensed,

tape

the

tape

motion

the

load

stops,

the

FWD

point.

indicator

goes out, .and tfie LuVPT indicator comes on.
NOTE

if'tape motion continues for more'than 10 sec; itA

is-possible that originally too much tape was
wouud by hand onto the take-up reel,vpassing the
BOT

=marker.

this

happens,

press -STOP,

.REV (reverse), and press START.
move to the BOT marker
L)

0 3.2.3

se;ect

The tape should

(load p01nt)

and stop.

Unloadlng Tape—-leferent procedures are used to unload tapes,

depending

whether

not

theftape

BOT.

)

Unloading Tape at BOT--To unload a tape which.isat the BOT marker,

perform the folloWing procedure:

Place the LOAD/BR REL switch in tueBR.REL position to release
the brakes.

2.. Gently hand wind-the file reel (lower) iu a oounterolockwise
direction unril all of tue tape is wound onto the reel.

" CAUTION
When

reel.
which
3.

Remove

the

winding

the

tape

hand, do

not

Jerk

the

Thls can stretch or compress the tape,.
could
file

counterclockwise

cause

irreparable

reel

from

loosen

the

hub

damage.

assembly.

Turn

the

hub

it.

"Unloadinq Tape Not At BQI--To unload a tape which is not at the BOT
’marker, perform the following procedure:
1.

Place

the ON-LINE/OFF-LINE
|

switch in the OFF-LINE position.

3-6
:

‘

(»

(j'

Press

STOP;

select

Press

START.

The

REW.

tape

should

rewind

until

the

BOT

marker

reached.

Place the LOAD/BR REL switch in the BR REL position to release
the brakes.

Gen%ly hand wind the file (lower) reel in a counterclockwise
direction until all of the tape is wound onto the reel.
CAUTION

When

winding

the reel.

the

tape

hand,

not

jerk

This can stretch or compiess the

tape, which could cause irreparable’damage.
6. Remove the file reel from the hub assembly.

Tfirn the’hub

¢ounterclockwise to loosen it.
3;2;4

Restart After Power Failure--In the event of a power failure,
theTU10w automatically

shuts

physical damage to the tape.

down

and tape motion

stops without

Howe#er, if the TU10W was on-line

and wés either reading or writing at the timéofvthe power
‘<failure,

the last record was probably lost;

refef to system

recbvery procedures documentation if this happens.
the

transport,

proceed

To restart

as follows:

NOTE

Return of power
is indicated when‘tée PWR
indicator lights.
l.

Set

the

ON-LINE/OFF-LINE

switch

OFF-LINE.

2.’ Place the LOAD/BR REL switch in the BR REL position fo
release

the

Manually

brakes.

wind

the

reels

take

any

slack

the

tape.

4. Set the LOAD/BR REL switch to the LOAD position to draw
back

tape

3.2.5

into

vacuum

columns.

Set the ON-LINE/OFF-LINE switch to the desired position.

Restart After ngl~Safé-4If the tape lodfi in either buffei

colunn exceeds the limit shown in figufe 3—3,‘£he‘vacuum system
automatically shuts down énd‘tape moti¢n stops without dafiage to
the tape. When‘this'fai1~séfe condition occurs,‘the'TU1bw does not
"respond to éither on-line or~off-lin; commands. To restart‘thé
transport, refer to Parégraph'3.2.4.

3.3 »Operatbr Troubleshbotihgfi'

Before any maintenance persohhel afé called to édtredtlé pfoblem,‘

the operator can make several‘éhecks with'minimai effért.'-Tfiesé

)

.precafitions may isglafe éh easily correctable efror:

l. Ensunre that tfie vacuun doér-(Figure1-4) is'éloéédA;hd
" sealed groperly.

’

If the fape does not stdp at BOT,‘be‘ceitain fihé tape

has a BOT marker,

‘

3. Ensure that the write enable rifig is inserteavin the tépe

reel if a write operétion is fo be performed.
4.

Clean the fape path aécording to the daily (8-hour) pfeventive
maintenance

procedures

Chapter

SHORT LOOP

VACUUM

%—— (TRANSPORT

SWITCHES TM

WILL SHUTDOWN)

‘

BUFFER
COLUMN

O
LONG LOOP

<“—}— (TRANSPORT

WILL SHUTDOWN)

10-1288

Figure 8 - Fail-Safe Limits

s
Dl e
B
A
e e

CHAPTER

CUSTOMER

AND

The

CUSTOMER

RESPONSIBILITIES

customer

directly

tape,

supplies,

MAINTENANCE

including disk cartridges,

and.filters,'magnetic

cassettes,

CARE

e
for:
responsibl

Obtaining operating
digk packs

PREVENTIVE

printer paper,

tape,

DECtape,

printer

paper

ribbons,

plotter

etc.

Supplying accessories, including disk storage racks, DEC—
tape
and

storagé racks, carrying cases for disk cartridges
DECtape,

cabinetry,

tables,

and

chairs.

NOTE

Ucsers
may

Digital

obtain

the

Equipment

proper

Corporation

operating

equipment

supplies

and

acces-

ories by contadting:

Digital Equipment Corporation

DEC Supplies Order Processing‘
146 Main Streetw

Maynard, Massachusetts 01754»

Phone: (617)897—5111, Ext. 5218,5907
Boston Area:

(617)890-0330

TWX:710-347-0212

Cable:
Telex:
3.

Maintaining

the

Digital
94-8457

required

accurately,

logs
4-1

Mayn

e e

e b

and

report

files

consistently

and

"y" i

Téfi\,

necessary

the

docunmentation

available

in a

location

convenient

Cel T

Making

the

systen.

Keeping the exterior of the

TM
system and the surrounding area clean

Turning off the teletypewritef and/or line printer when these
i

devices

are

not

use.

Ensuring ;hat ac plfigs are'securely pluggéd in each time.equipmunt
is used.
‘
Performing the spécific equipment care operationé'déscribed in
Paragraphs
often

4.2

usage

and 4.3
and

at the

suggested

environment

frequencies

or more

warrant.

CARE OF MAGNETIC TAPE

Do not expose magnetic tape to excessive heat or dust. Most
tape read errors are caused by dust or dirt on the read head;

it is imperative that the tape be kept clean.

Always store tabe reéls inside containers'when not in fisé}keep

the empty containers tlghtly closed to keep out dust and‘dlrt

O P

e A

Never touch the portion of tape between the BOT and EOT markers,

e «»fig

oil from fingers attracts dust and dirt.
o
Mever use a contaminated reel éf tape;:this will épread dift to
clean tape reels and could héve an adverse-affeét oh’tapé transport
reliability.
|
B
e
Always handle tabe reels by the hub hole; squeeéing;thereel
flanges could lead to tape edge damage in windingkor unwinding
tapes.

Do not smoke near~the tape transport or storage area; tobacco
smoke

and

ash

are

especially

damaging
to

tapes;
&

Do not place magnetic tape near any line printer or other device

that produces paper dust.

4-2

e
e

Dl L

ARR S

eCe

Do not place magnetic tape on top of the tape transport, or in
any other location where

4.3

it might be

affected by hot air.

CUSTOMER PREVENTIVE MAINTENANCE OF TU10W TAPE TRANSPORT

4.3.1

General

Digital Equipment Corporation tape trahspoits are highly feliable
precision instrufients that will provide years of troube-free perfor-

mance when properly maintained.

A planned program of'ioutine inspection

and maintenance is essential for optimum performance andireliability.

fhe following information will assist the customer in caring for his
equipment

4.3.2

ensure

Preventive

ensure

should

few

and

the

kept.

items,

but

level

performance

and

reliability.

Maintenance

trouble-free

highest

operation,

Preventive

the

preventive

maintenance

cleanliness

proper tapejtransport'operation.

these

maintenance

consists

items

very

schedule

cleaning

only

important

The frequency of performance will

vary somewhat with the environment and degree of use of the transport.
Therefore,

define.

rigid

'Daily

schedule

cleaning

applying

recommended

all

machines

difficult

forunita.in.

cdnsgantoperation ih ordinary environments.

This

schedule should be modified if axperiénce shows'other
periods

the

are more

cleaning

. cefore

store

basis.

membered
~not

come

any

properly.

and

that
in

Paragraph

4.3.4

contains’

instructicns,

performing

a daily
gentle

suitable.

All

avoid

the

cleaning

cleaning,
certain

tape

contact

items

the

tape

painted

path

strong

the

to be

reel

cleaned

and

thorough vet .

cleaning
or

supply

éhould

practices.

surfaces

4-3

remove

important

dangerous

cleaner

with

operation,

should

agent

plastic.

and

re-

should

CAUTION

not

use

acetone

alcohol,

careful

not

ball

4.3.3

lacquer

excessive
to

allow

bearings,

thinnex,

cleaner.
the

tension

cleaner

rubbing

extremely

penetrate

rollers,
and motors.

fiAGNETiC TAPE DRIVE CLEANING KIT

A magnetic tape drive cleaning kit

has been carefully configured

to provide cleaning materials thafiiwill not harm fape equipment and

will not leave/any residue behind to interfere with data reliability.

ffie hints contained in the following few péragraphs will

ensure

that

the

The

the

very

FREON

best

results

#TF113 cleaning

best

degreasing

part

of'DIGITALfs

possible

fluid

agents‘available.
tape

equipment.

will

this

be obtained

kit

one

will

ready the

not

from

the

adversely
can

kit.

safest

affect

fluid

and

any

for

service, unsc:efi the top and punch a small hoie in the méfiai.séal

covefing ihe pour spout.
|
|
o
|
V
WARNING
TF113 is a non-restricted, non-hazafdoussubsténce{‘
Howevgr,

when

using

TF113,

avoid

excessive

skin

contaci, do not allow TF113 to come in contact Qith
the eyes, and do not swallow it.

Use TF1130nly in a

Well-ventilated area.
When cleaning tape
Oor wipe
out

into

remaining

the

equipment,'never dip a contaminated cleaning swab

the can.

screw

and

fluid

cap

when

the

transfer
dip

the

cleaning

fluid onto
swab

into

operation

*Ragistercd ttade mark; Dow Chenmical Co.
4-4

the
the

swab,
cap.

pouf a
Discard

complete.

little
the

Always keep the can of fluid tightly closed when not in use, because

LR U A A U

e s

FREON TF113 evaporates rapidly when exposed to air.

“the cleaning materials contained in the kit to filean tape

Use

any part of the drive where a dirty
heads, gufaes; reels and o
resiaue‘could ultimateiy come in contact with tape. To clean othef

parts éf the‘drive, such as the exterior surfaces’of‘doors or the

frictiofi pads of brakes, use any reasonably clean, 1int~free‘méteria1

with or without cleaning fluid;
.NOTE

Shoulid you encounter an unusually stubborn
dirt deposit that appears to reSlSt TF113,

try

a. mlld soap and water solution to dlslodge it.

After using soap, be'sure to wash down the
affected area thoroughly with TF113

sbapy residues.

to remove

4.3.4 Cleaning the TU10W DECmagtape Drive

Dismount the tape frém the unit.

2; Cléan the.followiné components of théidrive using a foam-tippéd

#rase head (Location B)

Tape cleaner (Location C)

d. ‘UpperAroller guide (Location D)
e. Lower roller guide (Location E)

s&ab soaked in cleaning fluid (Figure 441).
|
a. Read/write heéd (Location A)

| ~ ~

‘

NOTE

Be careful to keep cleaning fluid only on the
tape-bearing

surface

roller

guides

to prevent

degreasing the roller guide bearings.

When cleaning the head area, avoid the sping-loadedAceramic washerS(j

on the tape diive assembliés.' If it apfiears necessary to run thé swal

over the tape bearing surfacé oftheseAguides fo refiove oxide deposit;,
do'so;ihowever, when cleaning istOmpleted, be.shre that the washer’

is‘preésed snugly up against the tape guide surface and hbt “hung.up"_
on

its

shaft

Next,

vacuum
another
remove

(Figure

clean the vacuum pockets

door

(G)

using

lint-free
any

4-2).

wipe

remaining

lint-free
over

the

(F)
wipe

head

and the
and

inner surface of the

cleaning

using

fluid.

polishing

Pass

action

deposits.

cema

mam

raa s

e e

Wrime
g e

e
b

e
e

tem

‘

’

v
"

€

]
)

v
)

11 .3357

Figure 4~| Location of Read/Write and Erase Heads and Tape Cleaner

’

CERAMK

WASHER

{ ¢

PLATE
NOT THIS

THIS
’

n-4120

Figure 4 -2 Proper Ceramic Washer Positioning

c—

CHAPTER

R e T RGeS

e 4S R';2',(?4SRR

TN G T

L )

TEREE,

MAINTENANCE

Tiamimaan N

SYSTEM

B S

5.1

SCOPE

This chapter provides a conplete description of TMB11/TU19W

preventive and corrective maintenance procedures.

TMB11/TU1PW MAINTENANCE PHILOSOPHY
" mhe TMB11/TU1#W DECmagtape System is highly reliable and will
5.2

.
provide years of trouble-free performance when properly maintained
A planned program of routine inspection and maintenance is essential
for optimum performance and reliability.

revantive maintenance required on the THB11 differs from that ragui

on the TU19W transport. The TMBi1 controller and the M8926 interface &are
total solid-state units with no moving parts; therefore, no preventi

maintenance is regquired on these units.

The TU1¢W transport, how-

ever, requires daily customer care consisting of head and tape patb
Otherwise, the transport requires very few
adjustments and these should not be performed unless problems are

cleanlng (Chapter 4).

encountered in transport operation.

See Paragraph 5.4 for the

recommended preventive maintenance procedures.

Corrective‘maintenance consists'of troubleshooting at the system

level using system diagnostics and Visual observations to localize

the failure to a particular‘unit, whether it be the TMB11 Controller:

the M8926 Interface or TU19W transbort. Ouce the faulty unit is

identified, unit level troubleshooting can be performed using unit

u
functional block diagrams, engineering flow diagrams, timing dlagra
and detail logic diagrams to localize the failure to an electrical
module or mechanical part.

Once the faulty module or mechanical paft is located, it should be
replaced.

the

faulty part

to the depot for repair;
if

repaired only

5.3

should be

if a mechanical part fails,

cost warrants

the

module,

returned

it should be

it.

EQUIPMENT

TEST

Test eguipment reguired
to maintain the TMB11/TU10W falls into two
‘categories:
5.3.1

standard test cquipment and special test equipment.

Standard

Equipment

Test

Maintenance procedures for the TMB11/TU10W require the\stahdard
test equipment and diagnostic programs listed in Table 5-1, in
addition

standard hand

tools,

cleaners,

test.cables,

and probes.

Table‘5~1'.étanaaid fest Eéuibfient ReqfiiredTw .~
Equipment
Multimeter

Manufacturer

Designation

Triplett or Simpson | Model 630NA or 260

Oscilloscope .
X10 Probes i2)‘

V Tektronix ;
Tektronix |

Diagnostics (MAINDECS)

DIGITAL

MAINDEC*11?DZTMA“¥

MAINDEC-11-DZTMF—t*
MAINDEC-11-DZTMG—*

*Revision

level

5-2

MAINDEC-11-DZTME—*

Type 453 6r equi§aient
P6008 o
MAINDEC-11-DZTMH—*

".': (”
|

5.3.2

L Y

e i

o el

e
R R

R
B

e
N

S e

Equipment

Usage of the special tools and'equipment is also given.
mable
Special

Tools

5-2

and Equipment

and Their Use

Usage®*

Item
1.

Skew

Tape (800BPI)

1200

ft.

29-19224

GO0

ft.

29-22020

or
2.

Reel

Roller

Microscope

29-20273

Magna-see

29-16871

Penlight

BPub

Part No.

Tool

Guide

Tool

Depth

Shimstock

20-18607

Alignment Glass

29-18611

Micrometer

.001
.002(red)

74-13969

29-22039

48-50023-01

48-50023-03

.003(green)

48-50023-04

.004 (tan)

48-50023-05

«005(blue)

- 48-50023-06

.0075(transparent)

48~-50023-07

.010 (brown)

48-50023-08

10.

TMB11/TU10W

11.

Feeler

Gauge

Set

12,

Allen

Wrench

Set

13.

EOT/BOT Markers

(Reflective

14.

Ground

Isolation

Plug

15.

Vacuum

Relt

Lecgend

Tension

*Usage

Module

Swap

Kit

Strilps)

(Scope

x | x

Fldat)

Gauge

Routine

Corrective

Monthly

P.H.

Cuarterly

Tape

Maintenance

P.M.

Semi-Annual
Major

P.IM.
Fath

5-3-

Alignment

e
S e

The special test eauipment and tools required are listed in Table 5-2.

B WwN
-

)

Test

Special

R R
R

- 5.4

Preventive

The.TMB11

controllexr

and

requiring

asgsemblieg
maintenance

Chapter
service

the

TU1l0W

drive

5.5

Adjustments
TMB11

TU10W
of

"No.

the

mU10“

System

MB926

interface

preventive
to

preventlve

techn1c1an

tape

The

Maintenance

module

maintenance.
by

the

naintenance

maintenance

Chapter

manual;

all~electron1g

Care

performed

contalned

are

user

and
is

given

performea

document

the
No.

preventive

the

TUl6/TM@B?2
EK-TU16-}M-002

‘

controller

adjustments

and

TUl6/TM@2

tape

EK~TU16MM 002.

and

M8926

alignment
drive

interface

module

procedures

system

are

malntenance

contain

contalned
manual

adjustments.

Chapter

document

A .;:V:l.t;wxl‘_..'&.J.;afiau;umbi.w;«_fi.a Ml

R e
T S e i et NIRRT

5.6

LR T st S e T

s e |

o, S

3
e
AT Zhsre

eG R

R I

CORRECTIVE MAINTENANCE

Corrective maintenance information is provided to guide and aid the
maintenance technician when isolating and repairing faults. The
information consists of five troubleshooting aids: the TMB11/TU1T0W
diagnostics, the corrective action flow diagram, the functional
block diagram,
5.6.1

troubleshooting,

TMB11

and TU10W Troubleshooting.

TMB11/TU10W Diagnostics

Diagnostics, consisting of a paper tape and documentation, are

The documentation includes instructions
on loading, running, and interpréting diagnostic printouts. The

provided with each system.

W listed and described
are
diagnostics provided with the TMB11/TU10

in Table 5-3.

Appendix B contains the diagnostic documentation less

the program listings.

Table 5-3 Diagnostic Descriptions

Number:

(

Description

Title

MAINDEC-11-—

DZTMA

TMA-11

Instruction Test

"DZTMH

TMA-11

Multidrive Data

"DZTHE

TU10W Drive Function

Reliability Bxerxrclsex
Timer

A series of basic tests that
checks TMB11 registers for
proper operation.

Tests all TMB11/TU10W function
for evaluation and debugging.

Selected TMB11/TU10W operation
are executed, timed, and the
times

are

then

printed,

that check

special

DZTMF

TU10W Supplemental
Instruction Test

Four tests

DZTMG

- TU10W Utility Driver

Executes designated operation
of errors or result
regardless

5.6.2

data transfers of the TMB11/TU

Corrective Action Flow Diagram

Figure 5-1 provides sequential procedures for troubleshooting the
TMB11/TU10W.
5-5

g3v4 vod
W3l378YVIVAY

YO 371N0OW

11nv4 133130

a3.ivi0si

VYH 340
NOILg3ivd

SNvVHL OL H343IH

n S3IOVLI0A

nvs

Ol NUN11Y

3 . 1 !

oTM | OL1QOHS IUNIVS

1Invd,-||
:‘

398V IVAY

5.6.3

Functional

Figure

1-6 functionally

Block

Diagram

separates

major

units

(TMB11,

M8926,

signal

flow

between

those

interfacing

between

each

the

TU10W)

circuitry comprising the three

into

blocks

functional

within

each

blocks

unit;

also

depicts

unit

and

interfacing

between

the

diagram

TMB11

and

‘the

Unibus.

The

functional

block

can

used

conjunction

s T

e o

and

with

Figure

5-1

for

troubleshooting

and

maintenance.

5.6.4 .TMB11 Controller Troubleshooting

The‘diagnostics lieted in Table 5-3 will test and troubleshoot all
functions

the

TMB11

Controller.

functional block diagram
can

isolated

5.6.5
Table

TU14W
5-4

and

drlve

5.7

possible

procedures

are

most

causes

diagnostics

and

the

troubles within the controller

when

problems

are

encountered

"More specific and more detailed trouble-

found

system maintenance

PARTS

1°5),

the

Troubleshooting

with the TU19W transport.
shooting

using

repaired.

Transport

suggests

(Figure

manual,

Chapter

document

No.

the

TU16/TM¢2

tape

EK-TU16-MM-002.

REPLACEMENT

instances,

"Electronic

parts

assembly

are

nearly

methods

all

for

parts

plug-in

replacement

modules.

are

Items

obvious.

the

transport

only

one

complete
Removal

Al d

drive

tape

item

path

the

alignment
and

system

may

requlre

transport

procedure

Replacement

maintenance

machine

reallgnment

tape path

may

usually

procedures

manual,

replaced

avoided.

Chapter

document

No.

replaced

the

time,

Refer

the
the

TU16/TM@2

EXR-TU16-HM-002,

tape

Table

5-4 TU10W DECmagtape Transport Troubleshooting Hint(

Hints

Problem

- General

Problems in the TU10W transport can usually be classified
as either mechanical or electrical but often the clasé?

ification may be confusifig because a basically mechanical
problefi can. cause w%at apbears to be an electroni¢ malfunction

and vice versa.

any

case

the problem

should

‘be thoroughly analyzed before adjustments are made.

Electronic troubleshooting is greatly facilitated by the
modular

construction--a new card may be

the effect observed.
subtle problems

Visualizing

and

Most difficult, of course are
those

solution

(Magna-See)

‘conditions for troubleshooting.
’

substituted and

intermittent nature.

useful

under

certak

At high‘dehsities the

data cannot be satisfactorily resolved but such problems

as a dead track,

improper gap length, etc., can be

isolated rapidly by its use.
If a tape has had visualizing solution applied to it, 490
not

reuse

the

head.

use

that portion

the

visualizing

remove top,
the

Cut

the

visualized

soltuion,

tape

portion

shake

will

off

and

the

can

contaminate

discard.

thoroughly,

and pass portion to be visualized through

solution.

Snap

the

tape

vigorously

remove

excess

solution and let dry. Iron powder will be left in
magnetized areas.

This

can be picked off using Scotch¥
5-8

(

tape and applied to a sheet of papex for a permanent
recoxd.

High

Error

Usually

the

difficult

problems

involve

higher

Rate

than

permissible

reéson,

error

rate

for

which

there

obvio:

If operating properly with good tape, the

“transport

should make

very

few errors
in writing

and,

if rewriting is included in the program, it should make
no

read

erros.

are:

Useful

clues

what

mode

what

point
in

What

CRC,

LRC?

Are

the

(read

the

nature

error

write)

are

block

does

the

error:

many
the

eXYrors

error

vertical

occuriy

occur?

pazxity,

|
patterns

raelated?

5. Do errors occur only on cerfain sets of ¢ommands?
The first thing to be done is to ia@p@ctthe head and
other items in the tépe path for dirt accululations.
Be

sure everything is

clean.

Check the tape being used

and try a new reel if tape is doubtful.
connections

for broken wires

or bad

Check'intfirfqbe

contacts.

Table

5-4

TU10W

DECmagtape

Problen

Compatibility

Transport

Troubleshoot

ing

Hints

(Cont)

Hints

The TU10W transport accepts and produces tapes confbrminéi
to

ANSI

standards.

Occasionally

compatibility

problem; can ariée:

Tapes.written by and acceptable to'the TU{OW transport
are'not acceptab}e to anothét transporfi.

Forelgn tapes cannot be read_ by the TU10W transport

but its own tapes can be read satisfactorily.

Pdur items may be involved:'ékew, speed, ramp tines,
and tapé path alignment.
described in

the

Th@&@ éhonld be checkea as

adjustment proéedureg.

5~10

Foiier

Ut e

et el T

T R

S AR

R BT L

Y s B
D

el RS e

e SR BT

ATR Ty T AT
e

s T

T R R Ne

TR BT A
I

i 3

e S L

R L

DB RUER E

e M e B NN B

6
" CHAPTER

TMB11 THEORY OF OPERATION

6.1

INTRODUCTION

The TMBI11 Controller has three main functions: handling data transfers, issuing control commands,
|

and monitoring operation of the system.

During data transfer functions, the controller assembles the data word from the magnetic tape and
places it on the bus (read operation) or assembles it from the bus and loads it into the tape transport
read/write heads (write operation) for recording on magnetic tape. The commands neccssary to perform the specified operation are generated by the controller under program control.

Normal data word transfers are performed by direct memory access transactions at the NPR level. If
the controller is ready to begin a new function or if an error condition exists, it issues an interrupt request so that it can be serviced by the program.

<. In addition to the commands required for data transfers, the controller may issuc other commands
write end-

governing tape unit selection, direction of tape travel, rewind, space forward, space reverse,
of-file mark, etc. The controller also monitors various functions and provides an indication of error
conditions. The status of the monitored functions is stored in the status register.
6.2

GENERAL OPERATION

The prime function of the TMB11 Controller is to control transfers of information so that digital data
can either be taken from the bus and recorded on magnetic tape (write operation) or read from the
magnetic tape and transferred to the bus for use by another device such as memory (read operation). In
addition, the controller performs tape transport selection, tape positioning, tape formatting, and sysS

‘

tem monitoring functions.

‘The controller contains a command register, which allows the program to specify desired operations
by loading control data (transport selection, packing density, function, etc.) into the register. System
status information (end-of-tape, errors, tape unit ready, etc.) is loaded into a status register, which can
|

be read from the bus.

Data transfers are controlled by a byte record counter (MTBRC) and a current memory address
register (MTCMA). The program loads the byte record counter with the 2’s complement of the desired
number of data transfers. The counter is incremented before each transfer; therefore, the byte transfer
that causes the byte count overflow (MTBRC becomes zero) is the last transfer to take place. The byte
counter is also used to count the number of records during space forward and space reverse operations.

(

The current memory address register is also incremented before each transfer and, therefore, always
points to the next higher address than the one most recently accessed. Thus, when the entire record is
“ransferred, the register contains the address plus 1 of the last character in the record. For certain error
conditions, the register contains the address of the location in which the failure occurred.
-

e ko
PN,

i L e

SR
R SB

Read

2.1

During read operations, the controller assembles bytes from successive characters read from the tape
channels. When reading a 7-channel tape, the 6 data bits are assembled in a data buffer register for
temporary storage. The parity bit is read but not loaded into memory. Because the PDP-11 uses 8-bit
bytes, the remaining 2 bits in the buffer are forced to 0. When the byte is assembled, it is placed on the
“us Tor transfer to memory. If an NPR transfer is used, bytes from the data buffer are alternately
|
stored into the low and high byte portions of memory.
¥hen reading 9-channel tape, operation is identical except that 8 data bits are assembled. It is not

necessary to force any bits to 0, because the 8 data bits constitute a complete PDP-11 byte. In the case
of both 7-channel and 9-channel tapes, the parity bit can be loaded into the data buffer but is not
~

loaded into memory.

-When reading 9-channel tapes, either the CRC character.or the LRC character at the end of a record is

stored in the data buffer, depending on the state of bit 14 in the MTRD. If this bit is 0, the CRC
character is loaded into the data buffer and can be used for error detection. If the bit is 1, then the data
buffer contains the LRC character at the end of the record. When reading a 7-channel tape, bit 14 in
the MTRD operates in a similarmanner. If bit 14 is set, the LRC character is present, and wien bit 14
a

i Fiiset g e T

is cleared, the last data character-is present in the data buffer.

6;2.2 Write

During write operations, the controller disassembles 8-bit bytes from the bus and distributes the bits so
that they can be recorded on successive frames of the tape. The controller selects one of three recording
densities (200, 556, or 800 bpi) for 7-channel tapes. All 9-channel tapes are written at a density of 800
bpi. There are three possible write functions: write, write-with-extended-IRG, and write end-of-file
‘

EOF) mark.

When a write function is selected, the program loads the byte record counter with the 2's complement

of the number of bytes to be written in the record. Although the parity bit is generated by the master
tape transport, the polarity of the bit is determined by the controller so that either odd or even parity
can be selected. When the buffer is loaded, the controller transmits the byte to the master tape transport, which places the byte on the read/write heads of the selected slave transport so that data can be
written on-the magnetic tape.

The write-with-extended-IRG function is identical to the write function except that a 3-in. gap, rather

than the normal gap is used between records. When this function is selected, a 3-in. segment of tape is
S

erased before writing begins.

- The write end-of-file (EOF) function is used to indicate that a block of records is complete. When this

is written on the tape followed by an LRC character. In 7* function is selected, a special EOF character

channel mode the EOF and LRC characters are octal 17. In 9-channel mode the EOF character (and
the LRC character) are octal 23. These two characters constitute a complete record. This command
causes a 3-in. gap to be placed before the EOF mark. The XIRG command must be absent to have this
gap written.
6.2.3

System Monitoring

‘

System monitoring functions are performed by the controller status register. The 16 bits in this register
retain error and tape status information. Some status data is combined, such as lateral and longitudinal parity errors, or has a combined meaning, such as illegal command, for optimum use of the
ar-ailable bits. The status register only monitors the tape transport selected by the command register;
‘herefore, other units that may be rewinding do not interrupt the system when ready for data.

6-2

T eT e T

v e e

A s
wwm e Y

e o RB
T

T e

Interrupts

6.2.4

i oo

fi\i@inw{é<x,_g,;‘w:fl»...a~

ool

3 The TMBI! Controller uses NPR or BR interrupts to gain control of the bus in order to perform data
~transfers or to cause a vectored interrupt, thereby causing a branch to a handling routine. The NPR
requests are used for direct memory access whenever it is desired to transfer data between memory and
the data buffer register without processor intervention. The BR requests are made when processor
|
or error conditions.
servicing is required for completed operations

6.2.4.1 NPR Requests — The controller issues an NPR request whenever it is necessary to transfer
data between memory and the data buffer register. During a read operation, the direction oftransfer is
from the data buffer to the core memory. The RDS pulse (read strobe, from master tape transport to

controller), which is used to strobe data from the tape transport into the data buffer register, generates
the NPR request. When the request is granted, the controller performs a DATOB bus cycle and
transfers information from the data buffer into memory.

During a write (or write-with-extended-IRG) operation, the NPR request is generated by the write

strobe (WRS) pulse from the transport. When the request is granted, the controller performs a DATI
bus cycle and transfers a byte from core memory into the data buffer register.

During both read and write operations, the address in memory that data is read from or loaded into is

determined by the value in the current memory address register (MTCMA).

6.2.4.2

BR Requests -~ A BR interrupt can occur only if the interrupt enable (INT ENB) bit in the

command register is set. With INT ENB set, setting the CU RDY bit in the command register, or
o

completing a rewind operation initiates an interrupt request.

When CU RDY is set, it indicates that the controller is ready to perform another command.

When ERR is set, it indicates that some type of error condition exists. In this case, an interrupt is used
o

to cause the program to branch to an error handling routine.

If a function command is issued with the GO bit cleared and INT ENB set, an interrupt is initiated.
If the selected tape unit (as indicated by the SEL bits in the cqmmand register) completes the rewind

operation before a new command to that unit is received and INT ENB is set, an interrupt is initiated.

If the interrupt is enabled (INT ENB set) and selection of the tape unit is not changed (as indicated by
the SEL bits), then a rewind command causes two interrupts: an interrupt when the rewind function
begins and an interrupt when the tape unit completes the rewind function. If, however, the tape unitis already at the BOT marker when rewind is issued, only one interrupt occurs.

6.3 FUNCTIONAL BLOCK DIAGRAM DESCRIPTION

" The TMBI11 flow diagram (Figure 6-1) provides a brief functional description of the controller. This
diagram should be read in its entirety while referencing the controller functional block diagram, Figure
6.4

TMBI1 REGISTERS

All software control of the magtape system is performed by means of six device registers within the
controller. These registers have been assigned bus addresses and can be read or loaded using any PDPIl instruction that refers to their address. The six device registers are listed in Table 6-1. The register
addresses are determined by jumpers on the M 105 address selector module. Any programs that refer to
these addresses must be modified accordingly if the jumpers are changed.

e
L TNi R oB e R TR
e s TE e
NS I TR
T 2S
eISL e el
e TS
e E LS o eet e sS ep
Lt A
TS
ee
ee
Tt B bTR
St
S PR
S e LA
SR
Ry
e i T R B A SS
R
i L N
S TRe e

RRRETRL
- Lty i RIS G S $hoae helt eTlL i G e
b B RN I e B TR Ie
R e
=

8 Tl b T Tt

T e AT T e e R e
S A Rl N S e LT R R e S s R L G S
R
iTl eehen

M I BRI
L L
e

( START )

PROCESSOR ADDRESSES TMB11 REGISTERS

PROCESSOR LOADS TMB11 REGISTERS:

1. LOADS COMMAND REGISTFR WITH NECiroen
FUNCTION AND DFS3IRED TRANSPORT

2. LOADS BYTE/RECORD COUNT REGISTER WITH
NUMBER OF BYTES TO BE TRANSFERRED.
3. LOADS CURRENT MEMORY ADDRESS REGISTER
WITH FIRST MEMORY ADDRESS INVOLVED IN
TRANSFER.

4. CMA BIT 00 SELECTS LOW DATA BYTE OF
SELECTED MEMORY LOCATION.

COMMAND REGISTER ESTABLISHES OPERATION

PARAMETERS:
1.

‘

ASSERTS SELO-SEL2 TO SELECY DESIRED
TRANSPORT.

2. SENDS FUNCTION COMMAND TO COMMAND
DECODER WHICH ASSERTS COMMAND TO

TRANSPORT.

3. ASSERTSGOBIT TO ENABLE START
OPERATION LOGIC.

START OPERATION LOGIC INITIATES

OPERATION:

1. CHECKS THAT TRANSPORT IS SELECTED
~

AND ON LINE (SELR).

2. CHECKS THAT TRANSPORT IS STOPPED

(TUR).

AND READY TO START AN OPERATION

’

3. ASSERTS SET TO TRANSPORT TO START

(

THE OPERATION.

A
READ OPERATION

TRANSPORT ASSERTS WRS

WRITE OPERATION

WHEN READY TO
RECEIVE DATA

!
1

GO BIT REQUESTS AN NPR

TRANSPORT ASSERTS RDS WHEN DATA

{(RDO-RD7, RDP) IS READY TO BE TAKEN

)

‘

RDS:

WRS REQUESTS AN NPR

TRANSFER FROM NPR LOGIC
'

)

TRANSFER FROM NPR LOGIC

‘

)

.. 1. LOADS RDO-RD7? DATA FROM TRANSPORT

NPR LOGIC:

INTO DATA BUFFER VIA READ/WRITE MUX.
2. REQUESTS AN NPR TRANSFER FROM NPR
LOGIC.

1. ASSERTS NPR TO BUS.
2. RECEIVES NPG FROMBUS.

3. ASSERTS BBSY AND MSYN TO BUS.

"
|

RECEIVES SSYN FROM SLAVE INDICATING

DATA IS ON UNIBUS READY TO BE RECEIVED.

5. ASSERTS DATA STB 2 TO TAKE DATA FROM

BUS.
NPR LOGIC:

1. ASSERTS NPR TO BUS.

2. RECEIVES NPG FROM BUS.

3. ASSERTS BESY AND MSYN TO BUS.
A ASSERTS DATA
. BUS TO ENABLE EITHER

DATA STB 2 LOADS INPUT DATA BYTE INTO
DATA BUFFER VIA EITHER HI BYTE GATE OR

LO DATA BYTE OR HI DATA BYTE.

LO BYTE GATE, AND READ/WRITE MUX. DATA
NOW AVAILABLE TO TRANSPORT AS WDO-WD7.

T IB11 Flow Diagram (Sheet 1 of 2)

Ve -

cr e -

T umneprr N

AA i

e Ted A i

——— S

S e

> PS

L PR

RED TO
DATA BYTE IN DATA BUFFER TRANSFER
UNIBUS VIA EITHER il BYTE GATE OR LO BYTE
GATE.

NPR LOGIC:

1. RECEIVES SSYN FROM SLAVE INDICATING
DATA HAS BEEN RECEIVED.

2. ASSERTS NPR CLEAR BBSY TO INDICATE NPR
TRANSFER IS COMPLETED.
S

NPR CLEAR BBSY:

1. INCREMENTS CMA REGISTER TO NEXT MEMORYLOCATION FOR NEXT DATA TRANSFER. CMA
BIT 00 TOGGLES WRITE BYTE SELECT LOGIC TO
ASSERT ALTERNATE BYTE SELECT SIGNAL.
2. INCREMENTS BYTE/RECORD COUNTER.

LRCS

RECEIVED
NO

FROM TRANSPORT
INDICATING END OF RECORD
AND THAT THE READ
OPERATION IS
COMPLETED.

ABORTIVE

YES

ERROR

YES

LRCS STROBE OR ABQ
LOGIC ASSERTING DOI
LOGIC.

BUS INTERRUPT L
1. ASSERTSBUS 8

{

F‘\\M

2. RECEIVES BUS
3. ASSERTS BBSY

4. ASSERTS VECTY

INTERVENTIOR-

NPR LOGIC ASSERTS NPR CLEAR BBSY

NPR CLEAR BBSY:

1. INCREMENTS CMA REGISTER TO NEXT
MEMORY LOCATION FOR NEXT DATA

‘

TRANSFER. CMA BIT 00 TOGGLES WRITE
BYTE SELECT LOGIC TO ASSERYT ALTERNATE

‘

LA
L
et
:

~”

CARRY

‘

OUT 2 ASSERTED

BY BYTE/RECORD

.‘,:.,‘

COUNTER TO WRITE DATA

READY LOGIC

INDICATING DESIRED
NUMBER OF BYTES

e a

HAVE BEEN

WRITTEN

" ABORTIVE
ERROR

YES

BYTE SELECT SIGNAL.

2. INCREMENTS BYTE/RECORD COUNTER.

WRITE DATA READY LOGIC NEGATES WDR TO

TRANSPORT INDICATING END OF WRITE OPERATION.

)

TRANSPORT WRITES LRC CHARACTER AND ISSUES
LRCS STROBE TO TMB11.

RTIVE ERROR ENABLES DONE

TO BUS INTERRUPT
JE DELAYED

{

OG.lC:

*X=4,560R?

RX*® TO UNIBUS,
BGX®* FROM UNIBUS.

AND BUS INTR TO UNIBUS.
OR ADDRESS FOR PROCESSOR

¥ (NEW COMMAND, ETC.).

’

DONE

L R 4!4;6

Figure 6-1 TMBI11 Flow Disgram (Sheet 7 ¢ 2
'/‘

&.«-' 5 -

NRAN

M
Lol

K24
7

a US D@ - DIS 7,. et n el
/q’
N

W06

DRIVERS

kid

"BUS INTR

SELECT

OUTPUT
MUX

RwS

BOT

BUS BRXTM
BUS BGx
TM

PV
PALS
LA

s D BIT Q@ =15 vy iz
cagil

M7912
2,

BUS BBSY

8484

M79i2

¥ —

SEL STATUS IN

BUS
INTERRUPT

.1’/

SCL 1IN

DONE DELAYED

SEL 21N

LOGIC

_—

UNIBUS

1-47/

SEL 3 IN

BUS D@g2-D@8
(VECTOR ADDRESS)

] /‘/ L
‘V/

/.-

SEL 4 IN
M722Y

SEL SN

SEL 1 QUT

COMMAND
REGISTER

DONE LOGIC

(REG 1)

TM~
R
.
W
NNAU
S
IR
N
RSN TN
S
g
PRI
3

M7911

tEflR(l)

M7911

NNY N BN

LRCS

CARRY OUT 2
]

RDS

BUS NPR

BUS HPG

BUS

BBSY

BUS

MSYN

BUS

SSYN

NPR

LOGIC

seEL 2 ouT

AWRS

NPR CLEAR BBSY

BYTE/RECORD

COUNT

Phesiaes

GO BIT

(REG 2)

DATA STB 2

M795

DATA—-BUS
M796/M7821

STATUS

MESVMUIARTS
NN

BUS A@Z - A8

SEL 3 INJOUT

REGISTERS)

BUS CO-CH
MIO5/M7912

SEL 4 IN/OUT _

SEL 5 IN/OUT _

’

T M795

K-

DATA —e8US

UNIBUS

RECEIVERS

CMA BIT @82

(REG 3)

AON

SEL 3 0UT

2 DPP -DIS -

Pty

SIS

Srce

PSS

s
B

2
v

,
I o
AL

LI T e I e
e
A

M7912
14

'SEL 2 IN/OUT

DECODER

(SELECT TMBIM

SSYN

DAMAMICEAMI

SEL1 IN/OUT

SEL STATUS IN_

ADDRESS

WRITE

CMA REGISTER

TMB11/TSO3

4.77.BUS DEG-DI5

‘M7911

BUS MSYN
BUS

RTINS RN e [N

BUS ADQ-A18

-5\‘\‘\% Kae RS
T AR e \.\\ . CYNN

UNIBUS 3LA

.....

(;-lo

GATE

MT 012 A e o, L

7 1

LQ DATA BYTE
<

)

COMMAND

‘

\ FwD

\PEV

DATA BFR

OUT BIT @-7

\WRE
WFMK

s 2

pvenzrzannd -

_—16 STATUS BITS

DEN 5 2
NENM

———+ WRITE
DATA READY
CARRY OUT 2 | P% ‘0

coBIT

>:}

START

’

DATA BUFFER
(REG 4)

OPERATION

:HAN ¢ - CHAN 7,

RDS (READ LOAD)

SELECT

M7912

'EAD BYTE

SELECT

IseL Wi BYTE

HI DATA BYTE

|10 DATA BYTE

‘

)

ERROR

Locic

G
-

M7911

Figure 6-2

—

RO@-RD7, RDP . .

RECEIVERS
M7912

ERR

CHANG -CHAN 7 | TRANSPORT | A

*HAN P (REG 5)

=
-

t—-— READ

- | TR

|SELR

BIT @-7

SEL LO BYT

JoET

<D > Ta

LoGIC
TR
MTon ke

DATA BFR IN

'RITE BYTE

SEL @-SEL 2

CATA STB 2
(WRITE LOAD)

| wr S

M7911

NCTION COMMANDS (READ, WRITE, ETC.)

SEL 4 OUT

WDR

WRITE

PEVN

]

= READ

~— CURRENT MEMORY ADDRESS

WXG

DECODER

»!

M79ll

~— BYTE/RECORD COUNT

)

M7912

~— OPERATION PARAMETERS

DRIVERS }/i WD® = WD"'W’/”

M7512

i G

TRANSPORT

rrrpryereresy

TMBI11 Functional Block Diagram

6-60L

08-173

T
e
e
SR
Pt

B RO

ST o

T
il

FT
g Rk
e

SR e R
S
AR

O
e
],

S
e ik
bt

B
e
W SRR B

wizaein
DT i

O
B

Sl JELT AT
L
L
i B

S Tk Bm
Lot oL LT By S
i
Xy ek b
e s Be
e iMR e
e

A RS
S

Table 6-1

( Repister
,Status Register

Command Register

Device Register Functions

Nnemonic

Function

MTS

Provides detailed information on the status of the controller. Such information includes error indications and
tape unit status indications.

MTC

This is the main control rcgistér in the controller. Speci- -

fies the operation to be performed on the tape unit,
sclects the tape bit packing density, and selects the tape
unit to be used.

ALT
g

Indicates when the controller is ready, when an error
condition exists, and when the controller is cleared.

Provides the two extended address bits for bus

addresses.

Byte Record Counter

MTBRC

e A o MR
BS ReitBERSs eyi L i
¢ AlS ATbtR el iA Ri
Tey
ER S AletTR s egli
s T
oL4k g
: Do
£ e

R ? B TR
eety
L
e b B Boi AL
e R
Came o e
s e
s
ak e sl
RIS

A
GRlsnyTN R,
B e

operation, and the number of bytes in a read operation.
Desired byte count is preset by the program. When the
register counts the number of specified bytes, it prevents
further transfers.
|

(, Current Memofy Address
~.

MTCMA

Specifies the bus or memory address to or from which

data is transferred during read and write operations.
After each transfer is completed, the register is automatically incremented by 1 (next byte -location).
When BGL or NXM errors occur, the register contains
the address of the location in which the failure occurred.

Note that this register is incremented by 1, and there-

fore, accesses byte, rather than word, locations.
Data Buffer Register

MTD

Contains the information read from or written on the

tape. Serves as a buffer between the tape unit and the

memory.
Tape Unit Read Lines

MTRD

Permits storage of data read from the tape transport. A

parity bit indicates the occurrence of a parity error and
the channel containing the error.

L
[ S ar R GTlPOet
et
R
RVNP
e
oys S D
% " 9 "SR
eSR e b SIS TN
RT G
S, bl SRS

Counts the number of bytes in any write operation, the
number of records in a space forward or space reverse

A character selector bit is used to select the last charac- .
ter of a record that is to be loaded into the data buffer
register.

| A timer bit is used for diagnostic purposes by measuring

| the time duration of the tape operations.

A BTE/OPI bit is used to set transfer done prematurely
in order to provide a bad tape error indication.

6-7

Figures 6-3 through 6-9 show the bit assignments thhm the six devrce registers, Exceptin thecase off+ A
the data buffer register, the “unused” and *load only” bits are always read as 0s. Loading “unused’ or =
“read only” bits has no effect on the bit position.

The mnemonic INIT refers to the initialization signal issued by the processor. Initializationis caused
by one of the following: issuing a programmed RESET instruction; depressing the START switch on.
- the processor console; or occurrence of a power-up or power-down condition of either the processor
power supply or the controller power supply.
The INIT signal clears the entire system; however the INIT signal produced by a RESET instruction
does not clear the processor. Clearing only the controller and the tape units can be accomplished by
loading a 1 into bit 12 (POWER CLEAR) of the command register (MTC).
NOTE
INIT and POWER CLEAR deselect the current
tape unit and select tape unit 0. Also, a rewind oper-

ation in progress continues to the load point.
6.4.1

Status Register (MTS)

ILC | EOF | CRE | PAE | BGL | EOT | RLE

OBF-)TIF{

NXM | SELR|

BOT | 7CH

|SDWN | WRL | RWS| TUR
1n-0430

Fignrel6-3

Bit
.

Status Register (MTS) Bit Assignments

Meaning and Operation

ILC - Illegal command blt Indicates an illegal command. This b1t1s set whenever one

- of the followmg 1llegal commands occur:

Any DATOor DATOB transfer to the command register (MTC) durin g tape

operatnon (CU DY bit clear). The register cannot accept a new command
whilein the process of executing another command.

A write, write end-of-file, or wrlte-thh extended-IRG (command reglster
funcnons 2, 3, and 6, respectively), when the WRL (write lock) bit is set.
Writingis mhrblted with WRL set, and write commands are illegal.

Any command to a tape unit that has its SELR bit clear is illegal, because |
SELR clear, indicates that the unit is not on-line,

Any time the SnLR bit becomes 0 during any operation except off-line, it

sets the ILC bit, because no command can be issued to a unit thatis not online.
.'

If any of the illegal commands listedin a through c above occur, the command is
loaded into the command register.
|
o
,
In all ofthe above cases, the ILC bit and the ERR b1t (b1t 15in the command reglster)
are set snmultaneously

Cleared by INIT or by the GO pulse to the tape unit.
6-8

|
(

BTt

te
e,

rmoEen

SRR

i eSRR v

Meaning and Operation

EOF - End-of-file bit, used to indicate that the tape has reached the end ofthe file. An
end-of-file (EQF) character is detected during a read, space forward, or space reverss
is set when the
operation. During the read or space forward operations, the EOF bit
EOF character is read. During a space reverse operation, the EOF bit 1s set when the
LRC character following the EOF character is read. The ERR bit (bit 15 in the com. mand register) is set when the LRC character following the EOF character is detected.
|

1t is also set during WRITE EOF command.

or by the GO pulez
The EOF bit is set only by the tape unit logic; it is cleared by INIT
|
tothe tape unit.

The EOF character is loaded into memory during read operations.
13

CRE - Cyclic redundancy error bit. A cyclic redundancy error can be detected during
~ either a read or write operation. This check compares the CRC character, written on a
9-channel tape during a write or a write-with-extended-IRG operation, with the CRC
character generated during a read operation.

If the two CRC characters are not the same, the CRCE from the tape unit becomes a i,

forcing the CRE bit to a 1. The ERR bit in the command register, however, is not set
|

until the LRC character is detected.

Cleared by INIT or by the GO pulse to the tape unit. |
PAE - Parity error bit. When set, this bit indicates that a parity error exists. The PAE
bit is the logical OR of both vertical and longitudinal parity errors.

A vertical parity error is indicated on any character in a record; a longitudinal parity

error occurs only after the LRC is detected.

A vertical parity error does not affect the transfer of data. In other words, the entire
record is transferred to the tape during a write operation or transferred into memory
|

during a read operation.

‘

Both vertical and longitudinal parity errors are detected during read, write, and write-

with-extended-IRG operations. The entire record is checked, including the CRC and
LRC characters.

Longitudinal parity occurs when an odd number of Is is detected on any channel in the
record. Vertical parity error occurs when an even number of Is is detected on any
character, provided the PEVN bit (bit 11 in the command register) is clear, or if an odd
number of 1s is detected when the PEVN bit is set.

When a parity error occurs, PAE is set, and the ERR bit (bit 15 in the command
register) is set after the LRC character has been detected.

Cleared by INIT or by the GO pulss-to the tépc unit.

6-9

GhraSle

Sete

ee s

e R

e N

SRRS

SRl

Bit

e e

eA
e
R R
es N

ee e

SRS

D L e

e e

T R

O e

e SRS L e R

s
S
e
ee

e L T BBSR S

I
Dl
Se
O
I

St s DL

e eb W T D T

B
R
T

e
R
D
Te N
e
A R S

e e
R

1
RO
b
S
e
T
s e e

R U S

G et

Méaning and Operation

e elR
S
e
R i
e
R N
Gl
e

e
R
S
g

A
e

SR S

ie
R S

R e
BB
S R e
R
R
T

RS
B
S
eT
e

BGL
- Bus grant late bit. If the controllerissues a request for the bus and does not, TM,

receive a bus grant before it must issue another bus request for the following tapes.”
character, a bus grant late error occurs.

This error conditionis tested only for NPRs (non-processor requcsts) The BGL
bit is
set if an NPR bus request is not honored before the controller receives a WRS pulse for
a write operation or an RDS pulse for a read operation.
The BGL bit and the ERR bit (bit 15in the MTC) are set sxmultancously, halting the
operation.
If the BGL error occurred during a write or write-with-extended-IRG operation, the
controller does not send the WDR signal to the master tape unit to allow the master
tape unit to write data characters on the tape.

Cleared by INIT or by the GO pulse to the tape unit.
10

EOT
- End- of-tapc bit. The EOT bit is set as soon as the EOT marker is detected, when
the tape is moving in the forward direction. Itis cleared as soon as the EOT markcr1S
detected, when the tape IS moving in the reverse derCthn '
=

The EOTis an error condition if the tape is moving forward. Therefore, when EOQT is
set, ERR bit is also set when the LRC character is read.

Cleared by tape transport head passmg over EOT marker when tapc is moving in the
‘reverse direction,
,.

| RLE Record length error bit. The record length error is tested only durmg read

operations. An error is indicated as soon as the byte record counter (MTBRC)

- attempts to increment beyond 0.

When a record length error occurs, the RLE bit is-set, igrilcr'ementation of the MTBRC

and-the current memory address register (MTCMA) ceases, and the ERR bitis set
when the LRC characteris read.
|
o
The CU RDY (bit 07 of the command register) remains clcared until the LRC charac—

fer is read at which time CU RDYis set.

Clcared by INIT or by the GO pulse to the tapc»unit

If the exact record lengthis desired following the occurrence of a rccord length error, it
can be found by setting the MTBRC to a value so large as not to generate an RLE and
re-reading the record. Record length can be derived by subtracting the current value of
the MTBRC from its initial setting.
L.
3

L 2

6-10

R Le
T

(

[e
LA
ks

AR
LST
n
e AN

Bit

i
B

T
P
O

I R . sy

TGy
e
R
e
b e

e R
R

eRy

PR
T R T

L
e
T
T

iy,
NNt
e
eg

T L e
RO el
e SO
)
SS

SR R

Meaning and Operation

BTE/OPI - Bad tape error operation incomplete bit. A bad tape error occurs when a
character is detected (R DS pulse) during the gap shutdown or settle down period for
any tape function except rewin

During write, write EOF, or write-with-extended- IRG ¢ operations, a bad tape errof sets

- both the BTJE/OPI and ERR bits immediately on detectmg the error.
i

During both read and space forward or space reverse operations, the BTE/OPI bit is

set immediately on detection of bad tape.

During a read operation, the MTBRC increments continuously and words are read
into memory until the MTBRC overflows. During a space operation, the MTBRC
stops incrementing as soon as BTE occurs. When BTE is discovered, the tape umt.
stops, regardless of the state of the MTBRC

Because it is not-possible to artificially generate bad tape, bad tape may be indicated by

setting the CU RDY bit prematurely, thereby producing the gap shutdown period
while the data is still being read. The CU RDY bit is set by loading a 1 into bit 13 ofthe
MTRD. If bit 13 of the MTRD is set during a record for either a read or write operation, a bad tape error indication occurs.

Any initiated tape operation other than a REWIND or OFF-LINE command that

:
4

does not detect an LRC character within seven seconds results in setting the BTE/OPT

~ bit. This 7-second time-out is called Opcration Incomplete. Any legal size record with a
legal size gap results in detection of an LRC character within seven seconds. During a
spacing operation, the OPI timer is restarted at each interrecord gap. When the 7second time-out occurs, the tape unitin operatlon is RESET by CINIT The BTE/OPI
bitis set and at TUR the CU RDY bitis set.

Cleared by INIT or GO.

NXM- Nonexistent memory bit. This error condition occurs when the controller is bus |
master during NPR transfers and docs not receive an SSYN response within 20 us after
asserting

MSY N.

The NXM bit and the ERR bit are set simultaneously, halting the operation.

" Cleared by INIT or by the GO pulse to the tape unit.
SELR - Select remote bit. The SELR bit is set when the tape unit has beemr properly
selected. The SELR bit is 0 if the tape unit that is addressed does not exist (UNIT

SELECT setting does not correspond to SEL bits), if the selected tape unit is off-line
(ON-LINE/OFF-LINE switch set to OFF-LINE), or if the tape unit power is off.

BOT - Beginning of-tape bit. The BOT bit is set as soon as the BOT marker is detected.

When BOTis set, it has no effect on the ERR bit. The BOT bit remains cleared whenever the BOT markeris not being read.
<
This bit is set and cleared only by the tape transport.

6-11

e
-

Bit

Meaning and Operation
7CH - 7-channel bit. This bit is cleared or set by the
a 7-channel or 9-channel tape is being used.

tape transport to indicate whether

When 7CH bit is set, it indicates a 7-channel tape; when
it is clear, it indicates a 9channel tape.
,
|

The 7CH bit is also used in conjunction with the DEN 8 and DEN 5 bits in the command register to cause the core dump mode of operation. When
the TCH, DEN 8, and
DEN 5 bits are all set, the core dump mode of operation
is used.

SDWN - Settle down bit. The settling down period is provide
d to allow the tape to
fully stop prior to starting a new operation. This settling down
period sets the SDWN
bit. When the tape unit stops, SDWN is cleared, and the tape unit
ready (TUR) bit is

set,

During a tape reverse operation (this does not include rewind
operations), the gap
shutdown period begins immediately after the first gap encountered
after spacing over
a record.
'
:

WRL - Write lock bit. The write lock bit is under control

of the tape transport. When

set, it prevents the controller from writing information on the tape.

RWS - Rewind status bit. This bit is under control of the tape unit. It is set at the start
of a rewind operation and clears as soon as the rewind sequence 1s complete

TUR -~ Tape unit ready bit. This bit is under control of the tape transport.
Whenever
the selected tape unit is being used (such as rewind), this bit is cleared.
When the tape
unit is stopped and ready to receive a new command, the tape transpor
t sets the TUR

bit.

NOTE

Status register bits 00 — 05 are cleared or set by the
tape transport, not the controller.

6,42

Command Register (MTC)

15
'

ERR

DEN | DEN | PWR

.| CLR

11
PEVN

SEL

| SEL|

SEL |

RDY

Figure 6-4

06
|

-—————

—

e et
e, o

ENB

BIT
17 |

BIT
18

BIT
2

BIT
1

BIT
0

H-043

Command Register (MTC) Bit Assignments

6-12

00
GO

e e L P

P I

Gl 2 T

»”vgv,»h I e

R T D

e R

el B

e o

[RgeT)

)

e S

B R

T &
DR

R R

CiE

e B s NS R SEr

Meaning and Operation |

Bit

ERR- Indicates an error condition thatis the inclusive OR of all error conditions (bits

15 - 07in the Status Register, MTS). Causes an interrupt if enabled (see bit C6). The
ERR bit is not set for some errors until the longitudinal redundancy check (LRC)
- characteris read, in order to allow the current operation to be completed. Specific error
conditions are describedin the status register bit assignments (Figure 6-3).

When ERR is set, it sets bit 07 (CU RDY) when the tape unit asserts TUR.

Cleared by INIT or by the next GO command (bit Q0).
14

8 - This bit, in conjunction with bit 13, selects the bit packing density ofthe tape.
DEN

_ These combinations are shown below. Note that this bit, in conjunction with DEN 5
and 7CHin the MTS, can be used to select the core dump mode for 7-channel tapz.
Bit 13
~ .(DENS)

Bit 14
(DEN8)
-

L S

1]
|

|
0

Density
(bpi)

200

556
800

8§00

)

»-7-channeltape

9-channel tape/7-channel core dump

5 - This bit, in conjunction with brt 14, selects the bit packing densny of the tape.
DEN

See. b1t 14 above for combmatlons

PWR CLR - When a 1 is loaded into this bit position, it clears the controller logic and

all tape units. This bit becomes a 1 for 1 us during a processor DATO cycle, provided

the corresponding bit on the bus is a 1. Always read by processor as a 0.
1

" PEVN - This is the even parity bit. This bit is set whenever the selected tape unit is to

write or read even vertical parity on or from the tape. The bit
is 0 whenever the selected
tapc unit is to write or read odd vertical parity on or from the tapc.

A search for panty error is made whenever the tape moves. The control}crignores
parlty errors during space forward, space reverse, or rewind opcratlons
Cleared by INIT or by loading with a 0.
-

10-08

SEL
- These three unit select bits specify the number of the tape unit thatis to functron
as the unit under program control. These three bits (SEL 2, SEL 1, and SEL 0) are set
or cleared to represent an octal code that corresponds to the unit number of the tape
- unit to be used. The tape unit numberis selected by the UNIT SELECT plug on the
tape transport

Cleared by INIT or by loadmg wrth a 0.

6-13

e Tae SRR

St o

s P

T N

IR
SRR

LR et

llvaln

e e

[

L
e

LA
Y

)
SR

Vil

s
B S

eL
e e

N R

I e

R e ety PS

e I
TR

e
PR RSy, N
bteem
i dapatny

Bit

'Meaning,and Operation

(

CURDY - When set, indicates that the controller is ready to receive a new command.

This bit is set at the end ofa tape operation (indicating that a new operation can be
started) and 1s cleared at the beginning of a tape operation (indicating that the controller is not ready for new commands).

This bit is also set (in.dicating CU RDY) whenever ILC (bit 15 of MTS) is set or
whenever INIT is generated.

INT ENB - Interrupt enable bit. This bit, when set, allows an interrupt to occur, pro-

- vided either CU RDY (bit 07) or ILC (bit 15 of MTS) is set. With INT ENB set, a
REWIND command
completion,

can

cause

two

interrupts — one at initiation

and

one

An interrupt also occurs whenever an instruction sets the INT ENB bit but does not set
the GO bit (bit 00). Interrupts are described in Paragraph 6.2.4.

" Cleared by INIT or by loading with a 0.
05

ADRS BIT 17 - Extended bus address bit 17. Used to specify address line 17 in direct
memory transfers. Increments with the current memory address register (MTCMA).
Cleared by INIT.
~
:

03-01

ADRS BIT 16 - Extended bus address bit 16. Function is the same as ADRS BIT 17
(bit 05 above).
|
o

(

FUNCTION - These bits specify a command to be performed by the selected tape unit.
These functions are:
S
‘

v
OctalNo.

| Function Bits
03

Function

-1

-2
3

Read

0
0

I
1

0
1

Write
Write end-of-file

5
6
7.

|
|
|

0
|
1

1
-0
1

Off-line

Space forward -

Space reverse
|
Write-with-extended IRG
Rewind
|

All function bits cleared by INIT.

GO - Loaded with a 1 from the bus to initiate the function selected. Clears CU RDY

bit.

Cleared when GO pulse is sent to tape transport. Normal time duration of bit is 1 s,
but this time may extend to as long as several minutes in the case where the bit is loaded
for-a tape unit that is in the process of rewinding.

Also cleared by INIT or cleared whenever ILC in the status register is set.

6-14

(

P e R Y Pl

N ke

ek, T

£
e nPe R,
(VNS

4
s
e R

[N R

SG L S

SR B

o e

W S LR

L
e
e R SR

P Sl

e s R DA B e R NG s
DR ST

e RO

L e

2's

COMPLEMENT OF NUMBER OF BYTES (OR RECORDS} TO BE COUNTED
1-0432

Figure 6-5

Byte/Record Counter (MTBRC) Bit Assignments
Meaning and Operation

Bit

Contains the 2's complement of the number of bytas.or records to be transferred. The

15-00

desired value is loaded by the program on a processor DATO. Cleared by INIT,
‘

Increments by 1 after each memory access.

The byte record counter (MTBRC) is a 16-bit binary counter used to count bytes in a
‘read or write operation and used to count records in- space forward or reverse
operations.

When used in a write or write-with-extended-IRG operation, this register is set by the
program to the 2’s complement of the number of bytes to be written on the tape. After
the last byte of the record has been strobed from memory, the MTBRC becomes 0.
Thus, when the next write strobe signal is received from the master tape transport, the
controller lowers the write data ready line to indicate te the master transport that there
are no more data characters in the record.

When used in a read operation, the MTBRC is set to a number equal to or greater than
the 2's complement of the number of words to be loaded into memory. A record length
error, which occurs for long records only, occurs whenever a read pulse is generated
after the MTBRC is at 0. Neither the CRC or LRC character is loaded into memory
during a read operation, although both characters are checked for parity errors.
When used in a space forward or space reverse operation, the MTBRC is loaded with

the 2's complement of the number of records to be spaced. The counter is incremented
by 1 at LRC time, regardless of tape direction.

6.4.4 Currefit Memory Address Register (MTCMA)
00

BUS

ADDRESS
fi- 0433

Figure 6-6 Current Memory Address Register (MTCMA) Bit Assignments

6-15

el el | et e

R R

Sy,

GhERG ste
S

“

)

S eea N e e e

e 45

P es ee W SR e e e

PRI
i SR

ol 5A

e LT S ST I S

L e

a e sl

Rl R
Ll

Meaning and Operation

Bit

15-01.

These bits specify the bus or memory address to or from which data is to be transferred

during write or rcad operations. Only bits 01-15 of the MTCMA are accessible by the
program, although bits 00-15 participate in
NPR transfers. Bit 00 always starts in the
cleared or even byte state because all NPR transfers access even boundaries for a starting byte address. Therefore, MTCMA must be initially loaded with an even
address. The MTCMA contains 16 of the possible 18 memory address bits. The remain-

ing two bits (16 and 17) are part of the command register.

Before issuing a command, the program loads the MTCMA with the memory address

“thatis to receive the first byte of data (read operation) or with the memory address
from which the first byte is to be taken (write operation). After each memory access
(read or write), the MTCMA is immediately incremented by 1 (the next byte boundary). Therefore, at any given time, the MTCMA points to the next memory byte
address that is to be accessed. On completion of the record transfer, the MTCMA
points to the address plus 1 of the last character in the record.

If a bus grant late (BGL) or nonexistent memory (INXM) error occurs, the MTCMA

contains the address of the locationin which the failure occurrf-'d

If an 18-bit memory address is required, the program loads the appropriate address
into bits 01-15 of the MTCMA and into extended address bits 16 and 17 of the com-

mand register. The extended address bits are a logical extension to the MTCMA register and participate in any required incrementation.

6.4.5 Data Buffer Register (MTD)
08
PARITY

'
'

DATA
11-04 34
es

e ector

Gew

mee

wmes
&
v

Figure 6-7 Data Buffer Register (MTD) Bit Assignmcx{ts
Bit

15-09
(not shown)

Meaning and O peratlon

Correspond to bits 07-—01 respcctwely on a processor DATI cycle

- Example: Bit 15
= bit
7, bit 14
= bit
6, etc.

Correspond to the parity bit on the magnetic tape. During a processor read operation,
this bit is stored in memory. During NPR operations, this bit is read by the controller
but not loaded into memory. During operation of a 9-channel tape unit, this bit is valid
only after the CRC character has been read, provided bit 14 of the MTRD is a 1.
NOTE
The parity bit is generated by the master tape transport; it is not generated by the controller. However,
the polarity of the parity bit (ocdd or even) is determined by the PEVN bit in the command register.

e
O SR

6-16

g
aadl.

R e
O

LRy SN

g BE

:
2 g
.
R ey
i
b
G
v T
L
R T
T:

S By
R
s e
T
SR
e
e
L TR

£
s
TR PR

N LT

T
e
GRAERT

9 TRACK TAPE-

FULL 8-BIT BYTES ARE RECORDED OP{ TAPE.

035

T TRACK TAPE-

ONLY 6 BITS OF EACH 8~BIT BYTE ARE RECORDED
ON TAPE.BITS 6,7,14,AND 15 ARE NOT USED.

.00
A

7 TRACK TAPE (CORE DUMP)FULL B8-BIT BYTES ARE RECORDED ON TAPE
BY USING TWO 4-BIT CHARACTERS

¢[

{

Figure 6-8
Bit

R.EAD/WR'ITF»

HEAD

E’

L
i1-2061

Relationship Between Tape Characters and Memory Byte Characters

. 07-00

B‘

TAPE MOTION

. Meaning and Operation

During read operations, these bits are used for temporary storage of characters read

from tape prior to loading into memory. During write operations, these bits are used
for temporary storage of data from memory before writing on tape.

During read operations, the LRC character enters the data buffer when bit 14 of the
address location for the read lines register is a 1; the LRC character is prevented from
entering the data buffer when bit 14 is a 0. Thus, after reading a 9-channel tape, the
data buffer contains an LRC character (if bit 14 isa 1) or a CRC character (if
bit 14 1s a
0). After reading a 7-channel tape, the data buffer contains either the LRC character (if
bit 14 is a 1) or the last data character (if bit 14 is a 0). After reading an EOF character,
the data buffer contains either all Os (bit 14is a 1) or the EOF character (bit 14 15 2 0).
The data buffer can store only bytes; therefore, two bus cycles are required to transfer a
word. During NPR operation the data bits are written into or read from alternate low
and high byte positions. The relationship between tape characters and high and low
memory byte characters is shown in Figure 6-8.
6.4.6

Read Lines Register (MTRD)
- —

s
.

..
.

15
TIMER

14
CHAR|

13
BTE

SEL | GEN

12
GAP

Sgtjv;l;

UNUSED

00
DATA
1H-0435

Figure 6-9

Read Line Register (MTRD) Bit Assignments

6-17

fr,

e Sls

e R B e Q‘M-‘xm;‘awhfk&w-fiwp-izl’zmgdwu;fi’ e

NMeaning and Operation

BBit

R RS eSS B

T R T RR R

it e LA e

TINER = The timer bit is used for diagnostic purposes by measuring the time duration

of the tape operations. The timer signal 1s a 100 us signal with a 50% duty cycle and is.

scnerated by the controller. It is read as bit 15 in the memory location reserved for the

(

read data lines register. Read only bit.

CHAR SEL - This bitis used to select the last character ofa record that is to be loaded

into the data buffer. Read/write bit. Selection is as follows:
O-channel

7-channel

Set

Clear

LRC Character

LRC character

CRC character

_ast data character

be artifically
- BTE GEN - Bad tape error generator bit. Actually, bad tape cannot
set, a premature gap

‘generated. When set, this bit sets the CU RDY bit. With CU RDY

shutdown is generated, which produces a bad tape error indication when data is read
'

during this period. Write only bit.

GAP SHU'!‘D()WN — Read only bit. When set, indicates a gap shutdown period.

11-09

Unused.

tape by the master tape transPARITY — Corresponds to the parity bit read from the
a longitudinal parity error. After

port. Used in conjunction with bits 07-00 to indicate

: (

bits
a read or write operation, bits 08-00 should all be 0. If one or more of these The

remains a | after the operation is complete, it indicates a longitudinal parity error.
bit position containing the I indicates the tape channel containing the error. Read only

07-00

tape transDATA - These bit positions contain information read from the magnetic
clear unless a

- port. After these positions are read by the processor, all bit positions
parity error exists.

channels 00-07, respectively.
'B-its 07-00 in the read lines register correspond to tépe
~
S
~
Read only bits.

6.5

PROGRAMDMING NOTES

in the middle of a
In normal programming practice no attempt should be made to modify one record
ng part of the
destroyi
and
record
file. This practice could result in overwriting the boundary of the
least one
without
n
next record. Also, a read operation should never directly follow a write operatio previousatoperatio
n
the
if
intervening tape move operation. This prevents generating a BTE/OPI

a space
involved the last record on the tape. If it is desired to read a record that was just written,
only when

reverse command should be issued before the read command. New commands are issued

CU RDY is set, which is true after interrupts.

causes the
Attempting to write an all zero character with even parity on a-7-track or 9-track tape unittape,
2 20 1s
zero character to be converted to a tape character of 20. When reading this | character from
~
|

read instead of zero.

6-18

Ri e SR

L e

S e

approxASCIT standards provide for a 25-ft trailer following the end-of-tape marker. This allows
to write past

imately 10 ft of writing space after passing EOT. Care should be taken when attempting
the EOT marker if the operator is not familiar with the tape that he is working with, because after a
tape has been used, the reflctive markers are often changed, possibly decreasing the length of the
|

standard 25-ft trailer.

Because the physical displacement of the heads differ between 7-channel and 9-channel drives, records

written on one cannot be read by the other. However, a tape that is recorded on one can be re-recorded
by the other, providing you begin at the load point.

If two drives are sharing one controller, care should be taken not to allow both drives to have the same
unit number selected on the unit select plugs. If they are both set to the same number and a command
is issued, they will both attempt to respond and data transfers will become totally confused.
The industry-standard packing density for 9-channel drives is 800 bpi. However, 9-channel drives may
be recorded at 200, 556, or 800 bpi, providing the data is read back at the same rate.

Rewind Operation

Assume drive 0 is to be rewound. The command to rewind drive 0 is issued to the controller. At this
~ time the master tape unit asserts bit 1 (RWS) in the status register. If bit 6 (INT ENB) in the command
register was set at the start of the rewind operation, an interrupt occurs from the controller as soon as
bit 7 (CU RDY) of the command register has been set by RWS. This informs the program that the
controller is ready to accept a new command. By testing bit 1 (RWS) in the status register, the program
can determine if this interrupt was issued as a result of drive O completing its rewind operation or just
-

beginning it.

When the reflective marker, signifying BOT, is sensed, bit 5 (BOT) is asserted in the status register only
for the duration of time that the reflective marker is being read. Tape motion does not stop at this time.
Drive 0, still moving in the reverse direction, passes over the reflective marker, reverses its direction,
and proceeds in the forward direction back to the load point. Upon sensing the reflective marker while
proceeding in the forward direction, drive O halts tape motion, asserts bit 3 (SDWN) allowing the tape
|

“to fully deskew, and then sets bit 0 (TUR) in the status register.

" An interrupt is issued coincident with bit 0 (TUR) being asserted in the status register, providing the
|

following conditions have been met.

Bit 6 (INT ENB) in the command register is set,

The drive has not been desclected by changing the status of bits 10-8 in the command
register since issuing the REWIND command.

If multiple tranéports are used, it i1s not necessary to wait for a REWIND command to be completed

on one transport before switching to another. After a REWIND is issued, another transport can be
‘

switched to as soon as RWS is set.

6-19

T b eB

B T

o L ik
g

ERSI
e
N
gNy vt
. oTb T BBy
i Sl
s R TP i el
SR S . e
s
AT LR
st
e e R
oSR g e L T
RS A
i
T
Te s
R WR S
BN
e Qe LBR il
L

65,T
S
TeeSRA S e eSs
b . i Ry
T R- G
O
EE

it
MHeis

T SRprdnrR
T
e ey
et
Bl
be
I L
T MU b PO
3

B e
SO0R
ot ib Tl
LtSR
e
e

Te e ee R s e
T eBOLSRRE

sP
T e, 5L
e
aS
Epehy
R S e elSNs
ei
ANe D gLR

When operations on the second transport have been completed, 2 switch to the rewinding transport
“can be made as soon as SDWN or TUR is true on the second transport {so the status bits will be from

(

‘the rewinding unit). Only the unit select bits in the command register have to be changed to the unit
that is rewinding to get its status. If the rewind is complete when the unit is sclected, TUR is set in the
status register. If the RWS bit is still set, the software can either work on another transport or load the
next command to be executed in bits 1-3 of the command register where it is buffered until the rewind

Norsd

is completed. 1f INT ENB is set at.this time, the completion of the buffered command causes an
interrupt to occur. A REWIND command may take from 3 to 5 minutes to complete.

6.5.2

New Ilrive Selection

Figure 6-10 is a flowchart for new drive selection.

START NEW
‘OPERATION

YES

NEW UNIT =

OLD UNIT
?

LOAD NEWUNIT #
AND CLEAR INT.

‘

)

DELAY ~ 28 us

ERROR

LOAD NEW
COMMAND
AND INT. ENB.

. 1-2673

Figure 6-10 New Drive Selection Flowchart

Other programming restrictions occur when using select remote along with tape unit ready. The select
remote lines for all tape units that are not addressed are at 0. A tape operation may be performed only
" on a selected tape unit and one whose SELR line is a 1. Thus, whenever a command is sent to a
different tape unit from the one presently indicated by the unit select bits, the SELR line becomes O
almost immediately (less than one instruction time later) and becomes a 1 from 1 to 28 microseconds
later.

ol g

620

ENB.

Ll
S
SRR S

R S

L T

BRI

U B

i T

oe S

A
s

Frror Handling

6.5.3

e AU
R i

Write Operations

6.5.3.1

ILC- Illegal Command
¢

[If SELR (bit 6 of MTS) is not set to a 1, or WRL (bit 2 of MTS) is set to a 1, then
T

operator intervention is required to ensure that the drive to be usedis properly selected

~andis not write locked.

EOF - End-of-File

CRE
- Cyclic Redundancy Error
Backspace and try operation again with extended IRG.

4,
-

3
3

I SELR (bit 6 of MTS) is sct to a I and WRL (bit 2 of MTS) is not set to a 1., then a

command has been issued while CU RDY (bit 7 of MTC) was cleared. Try the oper- ation again, ensuring first that CU RDY is set before issuing a new command.

N/A

PAE
- Parity Error
~
Backspace and try operation again with extended IRG.

BGL - Bus Grant Late
Backspace and try operation N times.

EOT
- End-of-Tape

The reflective marker signifying the end-of-tape has been passed Operations past

this point are not illegal, however, they are not recommended unless the programmer
is familiar with the tape being used andis knowledgeable about the length of tape
existing past the EOT marker. Conducting any write operations past the EOT marker leaves the programmer open to the possxbxhty ofrunnmg the tape off
of the reel.

1.
- 8.

RLE Record Length Error

N/A

BTE/OPI - Bad Tape ErrOr/Operation Incomplete .

Regain a known tape position and try the operation again with extended IRG.
NOTE
A known tape position refers
records, or EOF marks.

6.5.3.2

BOT, header

NXM —Nonexistent Memory
| Rcsolve the memory discrepancy and try the operation again.
Read Operations

[ILC -

( | |

- o

lllegal Command

IfSELR (bit 6 of MTS) is not set, then operator intervention is required to ensure that

the drive to be used is properly selected.

IfSELR (bit 6 of MTS) s set, then a command has been issued while CU RDY (bit 7 of

MTC) was cleared. Try the operation again ensuring that CU RDY is set prior to
issuing the new command.

6-21

;*y«;sfihfimm;.,fl.w,.»_:._mw-:Mm_d:@z%i‘.‘,.m,m_,
Se bl
P slL

S
S eS ee SReok se 08,RyRSe Ml
Be Ve
SEsn eR
e U ARRS D Be eRN
Nee
e T gL e e T
e
e eet
S Chpr
ol |S e
e R S eT
A R
Rk e % ilSl
kg B s hse R

FOF - End-of-File

. The characters signifying the end of a file have been read.

CRE = Cyvclic Redundancy Error
Backspace and try the operation N times.

PAE - Parity Error
‘Backspace and try the operation N times.

BGL- Bus Grant Late

Backspace and try the operation N times.

EOT - End-of-Tape

The reflective marker signifying the end-of-tape has been passed. Continue only if it
is certain that an EOF mark exists after the EOT marker, or the tape will run off of
the reel.

RLE - Record Length Error

Reset the MTBRC to a value that is equal to or greater than the number of bytes in
.

the record, backspace, and try the operation again.

§.

|
‘

BTE/OPI - Bad Tape Error/Operation Incomplete

Regain a known tape position and try the operation again. If, after doing so,
the condition still persists, the data from the failing point to the next known

tape position is lost.

NXM -Nonexistent Memory

Resolve the memory location discrepancy and try the operation again,

6.5.3.3 Write End-of-File Operation

BTE/OPI - Bad Tape Error/Operation Incompletc.

Regain a known tape position and try the operation again.

Spacing Operations

6.5.3.4

[ILC - Illegal Command

EOF - End-of-File

Same as read operation.

.
|

“

The characters signifying the end of a file have been read. Detection of the EOF
marks stops a spacing operation even if the MTBRC is not equal to zero.

EOT - End-of-Tape

G
s e

e eS R
R

‘

Same as read operation.

BTE/OPI - Bad Tape Error/Operation Incomplete

Regain a known tape position and try N times.

6.5.3.5 Write-with-Extended-IRG Operation - Same as write operation.

, regardless
s until complete
6.5.3.6 Rewind Operation - Once a rewind operatio| n isA started, it continue
N
|
|

of errors or unit deselection.

622

6.6

e S

oy T e

e e
R e

g R L

B SRS

e T

FUNCTIONAL DESCRIPTIONS

The TMBI1 Controller may be divided into eight functional areas as follows:

Processor Data Transfer- The reading or writing of TM 311 registers by the processor
(DATI/DATO).

Operation Start - The sequence from setting the GO bit to issuing SET to the transport to

start tape motion.

NPR Bus Cycle - Acquiring bus mastership for an NPR transfer.

NPR Read (DATO) - The transfer of characters from the tape transport to memory.

NPR Wri‘ts (DATI) - The transfer of characters from memory to the tape transport.

Operation Done - The terminating sequence of a TMBI1 opcration.

Errof Sequence -~ The system errors detected by the controller and. how they occur.

Interrupt Bus Cycle - Acquiring bus mastership for a' processor interrupt.

These eight functional areas are discussed in the following paragraphs. Block diagrams, flow diagrams,
and timing diagrams complement the discussions.
~

NOTE

The biock diagrams that follow use logical AND and
OR symbols. It does not necessarily follow (hat a
corresponding gate exists on the controller logic
prints. The assertion of inputs A and B causing the

assertion of output C may be represented on a hlock
diagram by a single AND gate yet the enginecring
drawing may show that several circuit stapes are
involved in the ANDing operation.

The signal names used on the functional block dia-

~grams are the names used on the engineering circuit

schematics (C'S prints). Where other signal names or
notes are used they are enclosed in parenthesis,

Integrated circuit
Appendix F.
6.6.1

data

sheets
,

are

contained

Processor Data Transfer

6.6.1.1

Processor Qut (DATO) Transfer (TMBI1 Register Write) (Ficures 6-12 and 6-13) - The
processor selects the TMBI11 for a data transfer by asserting the proper address on BUS A04-A17 to

the TMBI1 address decoder (address range = 772520 to 772536). When the decoder recognizes the
proper address it enables the address MSYN gate which asserts ADDR DEC MSYN when BUS

MSYN is received from the processor. ADDR DEC MSYN enables the select in/out logic which
looks at BUS AO1-A03 to select one of the six controller registers. The control select logic looks at
BUS CO-C1 and BUS AQ0 and asserts OUT HI, OUT LO, or neither according to whether a high byte
Is to be written, a low byte is to be written, or a processor read operation is to occur. The control select
output enubles the corresponding portion of the select in/out logic which outputs the loading strobe
for the selected register.
|

i sIS eIR “uw«.we,-aA«-MM“MWW LM,&w..fk.—avSt“MMWMML«S
;

“.«il..s”me

§Y

Lo Ee M o
g LS N e N
B S ;w
e T T
Md,,im.%S ea’...uM&_Mw,..«ft«’u«._.)m:’" _..‘..a&a"..‘“afirawgumwuwfimwkm;xwfllm

When an “out” transfer is commanded, the SEL (1,4,5) OUT HI strobes will load their respective
registers. when selected.® The SEL 2 OUT HI, SEL 3 OUT HI, and SEL | OUT LO through SEL 4
OUT 1.0 strobes are ANDed with SSYN INH to produce corresponding SLCT loading strobes.
SSYN INI is produced by inverting ADDR DEC MSYN on the M 105 module. A delay occurs with
the inversion, thus the loading of registers with SLCT strobes will be later (with Fespect to BUS

Pt
Ny

MSY N) than the loading of tlxose w;th SEL strobes.

- DlS
The information is strobed into the seleeted register a byte at a time; 300~ D07 = low byte, D08
|

= high byte '

-4

SSYN INH becomes BUS SSYN to notify the processor that the information on the data bus has been

strobed into the selected register.

.’The command register contains the type of operation to be performed and the operation parameLers

ing to the desxred mode of operation as shownin Table 6-2.

D13 and D14 are the density bits outputtmg DEN 5 and DEN 8. The processor sets these bits accord“Table 6-2

Mofies of Gperatmn

Mode

E
R

fi;

i
'*

200 bpi, 7-track
556 bpi, 7-track

800 bpi, 7-track
800 bpi, 9-track

DENS

DEN 8

0
1

0
0

0
1

1
1

The core dump modeis enabled when the program asserts both DEN 5 and DEN 8 while the 7-channel
(7CH) signal from the tape transport is true (indicating that a 7-channel tape transport is being used).
DEN 5 (1) and DEN 8 (1) are applied to an AND gate thatis enabledby the 7CH signal from the
transport. The output from this AND gate is CORE DUMP which, when true, inhibits the DEN 5
~ AND gate thereby negating DEN 5. Thus an 01 density codeis sent to the tape transport indicating an
800 bpi data transfer.

The command register also specifies even or odd pamy to the transport (PEVN), selects the desired
transport (SELO SEL2), enables or inhibits BR cycles (INT ENB), and specifies the function that the
transport is to perform via a 3-bit function decoder. In addition, the command register carries 2
memory address bits to extend the current memory address register to 18 blts Bit 00 of the command
register is the GO bit which initiates the commanded operatxon

- Other registers addressed during a processor out-operation are:

® The current memory address register, whichis loaded with the address of the first byte to be
|

~ transferred

* The byte record counter, whichis loaded with the 2’s complement of the number of bytes to be
|

transferred

e The LRC ENB (1) bit of the read lines register which, when set, allows the LRC character to be
- read into the data buffer.

*See Figure 6-27 for processor write of register 4.

6-24

(

the eight functions generrts
6.6.1.2 Command Decoder (Figure 6-11) - The command decoder conve
by the tape transport.
ated by the command register function decoder into the six commands required
Figure 6-11 illustrates the functions that make up each of the transport commands. Table 6-3 1llus|

trates the conversion in tabular form.

READ + WRITE

(C4)

WRITE

ENB
FwOD

READ

SPACE FWD

e
[

REV

(C1)

SPACE REV

REWIND

RWD

OFF LINE
WRE

WRITE

WRITE XIRG

WRITE EOF

WRT
DATA
ENB
WXG

SPACE

WFMK

NOTE:

Designations in parenthesis refer to engineering drowings

N-4129

conlaining corresponding logic.

Figure 6-11 Command Decoder Logic Diagram.'
-

Table 6-3 Function Decoder Output vs Transport Command
- —————

—

“TRANSPORTCOMMANDS

COMMAND

B %|E

pecoDER | 2B

OFF LINE

X| X

FUNCTIONS | & | & | & | =
READ

WRITE

SPACE FWD_|
SPACE REV

WRITE XIRG | X

|Z | &

X | X|

WRITE EOF | X
X

REWIND

6-25

X |X

The conversion is mostly ORing and is straightforward except for the OFF LINE function. If the

processor orders an OFF LINE function, RWD (rewind) and WRE (write enabie) is asserted to the

transport. Writing during a rewind is an impossible situation that the transport interprets as an OFF
LINE command. Four other signals are generated in the command decoder for use throughout the
TMBI11. These signals are OR functions of decoder commands as shown in Table 6-4.
B

Table 6-4

Decoder ORed Functions for TNMB11

ThMBI I‘Signal
WRITE DATA ENB

ORed Function
WRITE
WRITE XIRG

WRITE ENB

WRITE
WRITE XIRG
WRITE EOF

READ + WRITE

WRITE

" WRITE XIRG
WRITE EOF
READ

it SN A it

SPACE

6.6.1.3

SPACE FWD
SPACE REV

Processor In (DATI) Transfer (TVMIBI1 register read) (Figures 6-12 and 6-14) - When an “in”

transfer is commanded by the processor, OUT HI and OUT LO from the control select logic are

negated thereby enabling the select in logic. BUS A01-AO03 selects one of the six controller.cegisters
" and outputs the corresponding SEL IN gating strobe to the output select multiplexer. Accordingly the
16 bits of the status register, register 1, 2, 3, 4, or the 12 bits of register 5 are gated out to the Unibus via
he Unibus drivers (see Figure 6-23 for processor read of register 4).

START

]

BUS A04-A17 SELECTS DEVICE

VIA ADDRESS DECODER.

BUS A01-A03 SELECTS ONE OF

6 TMB11 REGISTERS.

3. BUS CO-C1, ADD ASSERTS OUT HI,
OUT LO. OR NEITHER

PROCESSOR ASSERTS BUS MSYN
INDICATING DATA IS AVAILABLE
ON UNI{BUS

[

’

ADDR DEC MSYN
IN

TRANSFER

VES

SELECTED BY

BUS CO-C1.

ASSERTS SEL STATUS IN OR SEL(1:5)
HI TRANSFER

IN AS SELECTED BY BUS A01-AD03.

YES

]

SELECTED BY

BUS A00.

[

OUT LO

]

OUT HI

ASSERTS SEL(1:4) OUT LO AS

ASSERTS SEL(1:5) OUT Hl AS

SELECTED BY BUS AD1.A03

SELECTED BY BUS A01-AD3

LOADS BITS 1,2, 3 AND 6 OF

SELECTED REGISTER GATED

~ THROUGH OUTPUT MUX TO

UNIBUS VIA UNIBUS DRIVERS.

Hi BYTE LOADED INTO

SELECTED REGISTER IF

SSYN INH

———

[

‘

SSYN INH

ASSERTS SLCT(2:3) OUT HI

ACCORDING TO REGISTER

IF REGISTER2OR 3

’

)

SELECTED.

LOBYTE LOADED INTO
SELECTED REGISTER.

H! BYTE LOADED INTO
REGISTER 2 OR 3.

‘

DONE

NOTE:

During processor address of the TMB11
an IN transfer is a processor in transfer
or a read of the TMB11. An OUT

transfer is a2 processor out transfer or
.8 write into the TMB11,
114145

]

ASSERTSSLCT(1:4) OUT LO

SELECTED.

‘

|
|

| Figure 6-12 Processor In/Out
Flow Diagram (DATI/DATO)

- 6-27

BUS SSYN

(ADDR DEC MSYHM)

SSYN INH

—

| ADDRESS

BUS

OUTHI——=|
{m

OECODER

M105

)

@sus AOI- AO3

BUSA AOD

.
conTROL JQUTH!

SELECT

BUS CO-C1 .|

M105

o e

SEL 2 IN

o?fi‘LES:T

SLCT 2 OUT M1

_"\

SLCT 3 OUT HI

SUT i1

@ SSYM INH

(D7)

(1)

OuUT LO
a

8 us AOLA0
BUS

AOI-AO3

(07)

SEL 4
QuT LO

OUT LO

|(MTCMA)

ADDRESS
08-15
SLCT 3 l N BITS
SLCT3

Ut L0

M735

ADORESS

BITS 00-07
M795

BITS 08-15) .

{(ADDRESS
|

l(Aooness
I

BITS 00-07)

(FIG

QUT Hi

000 -DO7

6-18)
)

(COUNTER
(MTBRC)
'
BITS

SLCT 2 l

D0O8-DI5

SLCT 2

ouT Lo

l
l

‘

NG,
16 6-23
o

(

(07)

(k)

SLCT 3 OUT LG

[-QP—B—MF:G 6-23)

[BYTE/RECORD

(FIG 6-33!

&~ lF1G 6-23

—~\
\

QEEEIE
[CURRENT MEMORY |

'(07) \ SLCT )4 OUTLO

SEL 3
'

LO
D7) \ SLCT | OUT

o7y )_SLCT 2 0UT LO
»——L_/

OuT Lo

)

-0

__LJ

SEL 2

/—“e» (FIG &-31

SEL 1 OUT LO / ’
SELECT
OuT LO
~\

poo-007 |

> {FIG 6-23
;@

SEL 5 OUT HI

SEL 2 OUT HI

~(F1G 6-31)

.,@

SEL 4 OUT HI

(D7)

~
UNIBUS
RECEIVERS

!=-(FIG & -23)

SELt OUT HI

B8US DOO-DI5

i~ OUT M|

N\ SEL 4N

‘

DOB8-D15

SEL 5 IN

BUS AQ!- AD3 -

’

SEL 1IN

SEL 3 IN

0 OUT HI

OUT LO }

(D7)

SEL STATUS IN

SELECT

)

BUS

AO{-AO3

O
¢

BUS MSYN

AO4-A17

08-15

M 795

g
'

M795

gSlf 5H] ’ CHQ?SE%‘;ER ,____._‘___‘;E_C_:

MTRD )
l‘REGISTER
..- LAST

D14

B51TS

00-07

READ LINES

(08)

——— o)

NOTES:

1. REGISTER t = COMMAND REGISTER (M

s
Gemm
-

e
w

Awn

S T

(FROM TAPE

RaCAGRLD

TRANSPORT)

SRSy

COMMAND

7 CH

l (MTC)
DI3-014
i

SELECT

€

Dit

SRR

CLEAR

(D8)

1O
PRIy ST

DCe-D10

PARITY

- SRR
R

(C1)

N
I

001- DO3
f

SEL1

QUT LO

! o|
!
I

D04
- D05

3§ 6-27)

INTERRUPT
ENABLE

DECODER

TRANSPORT

SEL
2

«(FIG &6-33)

OFF LINE.

N\READ

(C1)

EXTENDED
ADDRESS

aoRs BiT
16 (FIG
EIC

’

ADRSBIT17

(D8)

isoen'U) (FIG

WRITE

FWD

To
—s=TAPE

EOF

\. SPACE FWD
SPACE REV

WRITE XIRG

(Fic 6-14
ond 6-19)

)

WRITE

B(1)

(F16 6-16)

SELO

INT ENB (1)

FUNCTION

SEL

|
|

(C4)

I,
|

o8)

T0
TAPE

SELECT

TRANSPORT

PEVH

TAPE

DOs

TO
TAPE

DEN B

(C4)

DRIVE

SEL
S
@ OUT HI

" ond 6-27)

DEN 5

(cn

BUS INIT

SELECT

rASALNA

POWER

_ (FIG6-23,6-24

| DENB

(c1
D12

DUMP

CORE DUMP—

| DERS (1)

DENSITY

CORE

(cn

COMMAND
DECODER

(Ch)

| RITE DATA
ATA ENB
WRITE

ENB

READ

SPACE

(FIG 6-11)

WRITE

»(FIG 6-180nd 6-24)

\JEV

::}(F!G 6-31)

\ WRE

*\_RWD

> (FIG 6-16,6-18and 6-29)
~

TRANSPORT)

WXG
:

]

35S REGISTER (MTCMA)

ITD) |

ITRD)
ering drowings
11-4132

Figure 6-13

Processor Out (DATO)

Block Diagram

6-29.

WFMK
-~

‘MTBRC)

‘

[
My

g B

R SR
e
L eS S

e S

e m be R

CSELECT

Imux
|

D BIT p3-15
-

D BIT 89-15
|

l
l

';’

BUS DP@-DI5 | UNIBUS

PR —

D BIT §9-15
'

|
'

\_ D BIT oo P@-07

\_ DBIT9,1244,15

{ -

NOTE:

1. Designation in parenthesis refer to engineering

— PAE

T(FIG.6-13)

CATE

Jot 22-15)

GATE

Le g SEL 2 IN

16-BIT

— CRE

[ SEL STATUS IN

|(p4-05)]

(COUNTER BITS

1 gféz o

. TuR

|— PEVN

: g’gl’_"fl

— INT ENB

8-BIT

SEL 3 IN

r(FlG.6~13)
|CHAN @-CHANT

_
M (FIG.6—-23)

5-BIT

[

- RWS

@-15)

GATE

7CH
— BOT

— ;ngRNS 88‘?127256 WAL

(FIG. 6-13)

|er

— RLE

— CU READY (1)

l(gooness R

1795

— EOT

— SEL2-SEL
@

12;87!; ]

— B8GL (1)

— DENS

(04-05) po—port 1N

| | oo |

__;Ezc.)cFm

’gAi'ET 7

b | w79s

_oBiTop-15

'
.

QUTPUT

‘

CHAN P (F1G.6-23)

SEL 5 IN

GSD (FIG. - 6~-31)

TIMER (NOTE 3)

drawings confaining corresponding logic.

2.See NPR read for processor read of data

buffer (reqister 4).
1-4124

b ]

. 3. Mointenance use only.

Figure 6-14 Processor In (DATI)
- Block Diagram

631

e e

RS
i
ey e
el i B e it
sl AT,
g Le eBS8
g T eD R ee
ei
e
e
sk e
e e
Ree
R b T b e TS
e
TeS
L

e e Tl
eN Bet e
BT
SSR e T S
S

e
e S
gt eB
T - S ee eye LB
oktR RSTbBl ele
e Dl
o i
i
] esR GB
e
i iS TRel el G
R
e eS
GR
R
Y,T

T
el GPR R
e
L
R
TR s Se

T b
b
e eeS S
R TR
R
e

eeLR

‘6.@.2 Operation Start (Figure 6-15 a.mi 6-16)
6.6.2.1 Basic Sequence - When the command register GO bit is set by the processor a command start
sequence is initiated. GO BIT (1) resets the CU ready bit in the comimand register indicating that the
TMBII is processing a command. If the tape transport is not rewinding and TUR 1s true, GO BIT (1)

triggers the GO strobe 1 one-shot. If the tape transport is rewinding (RWS true) GO BIT (1) will not

trigger the one-shot due to the “0” output from the transport remndmfy flip-flop. When the rewindis
- complete, TUR asseris resetting the rewinding flip-flop thereby triggering the GO strobe | one-shot.
The GO STROBE 1 output of the one-shot resets the request store flip-flop and if SELRis true, the

“0” output of the request store f{lip-flop triggers the GO strobe 2 one-shot. When GO STROBE
2
(1) |

asserts, the following occurs:

SET is asserted to the tape transport if there is no illegal command and if the function is not
REWIND or SPACE REV while the tape transport is at BOT (REV BOT false).

The GO flip-flopis reset and the request store flip-flopis set in preparation for another GO
.command from the processor.

The trailing edge of GO STROBE 2 (1) resets the CUR delay flip-flop. CUR DEL (1)is
negated indicating to the error logic and the done logic that a transport operation is now in
progress.
'
|

6.6.2.2 Time Out - If the transport is not selected or is not on-line (SELR false), the output of the
request store flip-flop will not trigger the GO strobe 2 one-shot. In this case, GO BIT (1) initiates a 28
us delay after which TIME OUT (1) asserts and triggers the GO strobe 2 one-shot. The assertion of
GO STROBE 2 (1) while SELRis negated causes the assertion of S£7 ILC and ILC (Paragraph 6.6.7)
which respectively inhibit th@ assertion of SET to the transport and initiates a done scquence (Paragraph 6.6.6).

6.6.2.3 Restart - If the system is performmg a spacing operation, either forward or reverse, thc tape
will space through records without coming to a stop at each interrecord gap.

In this case the SET commands required by the transport are gcneratcd by RESTART which triggers

the GO STROBE 1 one-shot without the ncccssity of TUR being true. RESTART asserts in the
SPACE mode of operation each time SDWNis sensed and the following errors are false: BTE, BGL,
NXM, ILC (1), OVERFLOW (1), EOFF (1), and BOT.

6.6.24 OPI/BTE - When GO STROBE 2 (1) asserts, a 7-sccond delay is initiated. If the 7-second
time period elapses before an LRCS terminating strobe occurs, OPI
is asserted indicating an operation
incomplete error. OPI asserts the OPI/BTE bit in the status register and also CINIT to the tape
‘transport resetting the transport logic circuits. The 7-second delay sequence is inhibited during a
rewmd operation (RWD true) as rewinding the tape could exceed 7 seconds.
6.6.2.5 Initialize- GO STROBE 1 (or an INIT from the processor) asserts INIT + GO which causes
a general reset of the TMBI1 logic circuits. A general reset of the tape transport 13 caused by CINIT
whichis asserted by any of the following conditions:

1.
2.
3.

The processor asserts INIT.
BOTis reached during a space reverse operatlon
OPIlis asserted.
|

6-33

.~ -

ia e R e
eaaTn

R G

AL
S
BN

s DR
S T
e

S
Ty

. START

[ 1—-GOoBIT (1)

I
0 — CU READY (1)
TRANSPORT

REWINDING

SELR

28 ps

TIME OUT (1)

[

ISTART)

—]

‘
.1+ GOSTROBE 1

J
RESETS REQUEST
STORE FF

SLER

YES

1 -+ GO STROBE 2 {1)

0- GO BIT (1)

:
1 - OPI/BTE (1)

SETS REQUEST
CINIT

STORE FF

YES

D
7

NO
.

it~ ERR
DONE

(1)

DELAYED

REV BOT

:
:
5

X
RESTART

[
|

é.

‘

l
0 - CUR DEL (1)

lo—«GOSTROBEZ(n]

]

INIT + GO

(:;

DONE

l '

]
N

GENERAL

TMB11

RESET

|
:

Any one of the following:

BTE
BGL (1)

NXM

e
OVERFLOW (1)

EOFF (1)
BOT

11-4139

Figure 6-15 (jperation Start
Flow Diagram

35—

LiOE i

(FIG. 6-13)

(FROM TAPE got | 807

(c1)

COMMAND
REGISTER

leit o7

(FIG. 6-29)

seTcur]

——

u;T\

TRANSPORT) ———#] O.S.

OPI

SPACE REV

(cy) H-CHHLT 3}7TO TAPE-

—

L IHIT

l - (F16.6-13)

RARSP

\ ONUIMIT+G0 (GEKER:!

'—-—“J
(FIG.6-14
i' ADY(?) ® AND
' ' “|reapy
6-33)
F.F.
(RESET)®
cu

e “j

(C2)

TRB
Ry

= (FIiG.6-29)

GO STROBE 2 (1)@

ILe (1)

(FIG. 6 -39) ———]
—

TUR

GO 14

GOT
BIT

F.F.

(seT) | (c2) 0

(FIG.6-13) ———=

(

(SET)

(1)

1 (C0.5S.
2)

—

TRANSPORT

®)

SDWN

)

(FIG. 6-43) — 2CE

FF.

(C2)0

—

‘

—

(C2)

(D9)
DELAY LTIME OUT (1)
GOB!T(1)::::>_“&
—
(D9)

RESTART

BTE

HX M

4
(FIG. 6-31)

T
e ()
ILC
(1)

(02)>
NOTE:

OVERFLOW (1)
|

(FROM TAPE
TRANSPORfl

EOFF (1)

BOT

‘

(c2j ,

TAPE

FF
(c2) J (RESET)|
:
‘ c2 g

SELR

STORE

FROM

( SET - TAPE

RWS

*Rosg

[STROBE] STROBE1 |RESET)|

" TUR

FROM

Desrgnohon in pcrenlhesvs refer $o enginesring drawings

containing corresponding logic.

TR B €

L
Y
P
S
P

s T

W i A Bs

(FROM TAPE

TRANSPORT)

LRCS

(FI16.6-13)

(SET)

STATUS

DELAY| ]

ET)

A
(;)

(RESET)

|INHISIT

SECOND

i BIT 08

EE
(C5)0

(C5) OPI

—

DELAY

OPI/BTE (1) (FIG.

(C5}

(FI1G.6-31)

(6-18,6-23

L-n—:&g—-m——_J

eY R

0
+d

e S

BTE

T 6-14)

| 6-27,6-31

STROSE
2 (1)

B 6-33)

(C2
(FI1G. 6-31)

(FIG. 6-29)

)

SET _ (1O TAPE

)
—TRANSPORT
.

SET ILC

REV

BOT

-24
}—=(F1G.6

GO STROBE
2 (4)(RESET) |CUR

DELAY |cuRr D

F.F.
SET CUR >l| (Cc2)
(F16.6-29)
T

)

(FIGS.6-24

e 6-29'a
6-31)

A44-4125

Figure 6-16 Operation Start
- Block Diagram

6-37,C

LS e AR

e A

6.6.3

LobS

MU e

L e

eRS L

e R

s
e

NPR Bus Cycle (Figures 6-17 and 6-18)

6.6.3.1
Basic Sequence -~ An NPR bus cycle is initiated via the NPR request logic. The request logic
A
|
generates NPR ENB (1) if:

Y.
3.

No mhibiting condition exists.
The logic is enabled.
NPR SET is asserted.

The request logic is inhibited if OVERFLOW (1) is true (the desired number of data records have

already becn transferred), BGL or NXM is true from the last NPR request, or CRCS or LRCS are
asserted (CRC and LRC characters are not transferred to memory). The request logic is enabled by

EVEN CHAR STB which is always high in normal 7-track or 9-track modes but only high during even
character transfers in core dump mode. Thus in core dump, two characters are read from (or written

onto) tapé for each NPR bus cycle,

The request logic is set by read strobes or write strobes (RDS + WRS) from the tape transport. If a
write operation is being executed (WRITE DATA ENB true) GO STROBE 2 (1) triggers the first NPR |
bus cycle as the first write strobe

is not generated until the first character is written on tape.

The request logic asserts NPR ENB (1) to the Unibus NPR acquisition logic which requests control of
the Unibus by asserting BUS NPR. When the processor responds with BUS NPG iN the acquisition
logic asserts BUS SACK and the processor responds by negating BUS NPG IN. The acquisition logic

checks for BUS BBSY true (by some other device) and if it finds the bus free asserts BUS
(indicating bus mastership) and NPR MASTER to enable the NPR master logic.

BBSY

When the NPR master logic is enabled the following actions occur.
ADRS — BUS becomes true and gates the address register and the two extended address bits
of the command register to the Unibus as BUS AQ00 - A17.

BUS CO-Clisgatedto the Unibus. If a read operation 1s to occur, READ is true and BUS

CO - CI are high. If a write operation is commanded, READ is false and BUS C0 - C1 are
low.
:
.
|
|

If the transfer is a read operation, DATA - BUS is asserted and gates the character in the
data buffer out to the Unibus.
~

Another output from the master logic undergoes a 150 ns delay (to allow for deskewing on

SRR

the Unibus address lines) and then sets the MSYN logic circuit.

The MSYN logic asserts BUS MSYN to the slave device which then returns BUS SSYN to the
TMBII. BUS SSYN becomes SSYN and is applied to the read and write termination circuits. Ifa read
operation is being performed the read termination circuit asserts an input to the termination OR logic..
If a write operation is being performed (READ false) the write termination circuit asserts DATA STB
I which undergoes a 150 ns delay (for input data deskewing) and then becomes DATA STB 2. DATA
STB 2 loads the data buffer with the input character that is to be written on tape. DATA STB 2 also
asserts an input to the terminator OR logic. The asserted output of the OR logic is delayed 75 ns (for

data deskewing into the data buffer) and then triggers the NPR clear logic.

The NPR clear logic assertsNPR CLR BBSY which resets the NPR request logic and increments the

bus address register and the byte/record counter for the next character transfer. If a spacing operation
“isin progress the byte/record counter is incremented by LRCSD and no bus cycle is involved.

6-39

6.6.3.2 Bus Grant Late (BGL) and Nonexistent Memory (NXM) - When NPR ENB (1) is asserted the
bus grant flip-flop is conditioned to set. If another NPR SET is asserted to the NPR request logic
before the logic is reset, the bus grant late flip-flop will set asserting BGL (1) which in turn asserts BGL

+ NXM to the error logic.

If the MSYN 1oéic is not reset within 20 ps after being set, NXM asserts and terminates the‘bts’cyéié |

by asserting the termination OR logic output. NXM also asserts BGL + NXM to the error logic.

6.6.3.3 BUSNPG QUT - An NPG from the processor is passed from one system'devicé'to another in

daisy-chain fashion until it reaches the device that issued the BUS NPR. A BUS NPG IN received by
the following conditions:
the TMBI1 is gated back to the Unibus as BUS NPG OUT under either-of

1.~ NPR MASTER is true (TMBI11 is preéemly bus master), or

2. NPR ENB is false (TMB11 did not issue the BUS NPR that cau'séidi the BUS NPG IN).
I

[

GO STROBE
2 (1)

READ OR

BUS CoLt

WRITE STROBE

8US A00-A17

NPR SET

(NPR
INHIBIT)

YES

EVEN

CHARSTB

—

NXM

—

NPR ENB (1)

)

t NPR SET

YES

BGL (1)

Pre——

)

BGL + NXM

BUS NPG IN

BUS SACK

l
1 - ERR (1)

—I

DONE DELAYED

)

0 -+ BUS NPR

LIBUSNPGIN

]

j
*

Any one of the following:

OVERFLOW (1)

BGL (1)

BUS
BBSY

YES

NXM

CRCS

LRCS

NO
BUS BBSY

NPR MASTER

ADRS — BUS

l///‘

e S

T RANGOE
RN

PR U

PRt

Sl S

S
e
e e SR

i oY

1 - BUS MSYN

DATA =+ BUS

CLK 2

1~ MPR CLR BESY(1)

INCREMENTS

COUNTER

DESIRED

DATA STE 1

]

{1)

ADDRESS REGISTEL

IRCRESENTS

BUS

| NPR MASTER

Chumaen oF Byt

NPR ENB (1

| BUS BASY

BYTE/RECORD

NO
=

CARRY OUT 2 _]

150 s

[

DATASTB 2

ENABLE

DONE

TERMINATION
OR LOGIC

75 ns

L CNTRL CLR

RESET M3YM LOGIC

L $ BUS MSYN

RESET NPR

{ ADRS - BUS

‘

]

{ DATA - BUS

‘

MASTER LOGIC

4 BUS co<1

‘

»
:

‘

LTRSS

SETHSYN LOGIC

114140

(

Figure 6-17

NPR Bus Cycle

Flow Diagram

64l

]

;

h
E

NPG | SACK | BBSY

NPR | NPG IN

(FIG.
6-33)
—>

.
(FIGURES

. \

BUS | BUS |BUS

|BUS

BUS

ouT

7821

BUS

Ca-Ci

;

BUS

MSYN

— AND
6-27)

UNIBUS NPR
LOGIC

M7821

NPR MASTER

::
.

)

BGL

‘

)

READ
(FIG. 6-13 }——]
M796

o0 BUS %

_
(&)

)

. | GRANT

LATE

FF
NPR SET +1C (c5)

( SET)o

B CHTRL

ANPR |
CLR ( (RESET )| MASTER
LOGIC

HSET) e
ns b—ed
b beray
MSYHN
150 n:

LOGIC

M796

MT96

. L
.| pEtay
20us

MT796

1796

o(nase*r)

‘.

REA

( FIGURE 6-31) OVERFLOW (1)

OBGL + NXM
: CRCS +LRCS

(FIGURE '6-19)

( HPR INHIBIT) .

EN
N CHAR STB
(NPRNFR ENABLE)
(FIGURE 6-27) (oREAD
OR WRITE STROSE)

( FIGURE 6-19)
GO
TR
: S1oook
: E e-f6)
201)
(FIGUR
WRITE DATA

(FIGURE 6-13) gpo

@m CLEAR B3SY (1)

Wt
s

Een
e nee
w

NPR
REQUEST
LOGIC |
(08)

TERMINATION

MT26

WRITE ON| pata sT8 1_["
READ TERMINATI
L
3

M796
D
REA

{FI1G.6-13) ALTLA
'

(NPR RESET)

ssyN

u79s

‘

UNIBUS

}v/

@
gus

BUS

At6-AIT

|AQG-A

EXTENDED

BUS
ADORESS BiTS | ADDRESS
|BTSH-IT)| ADDRESS |
ate—ar7
(BITS 94-05

~>{

OF MTC; FIG.

GATE

(08)

€-13)

(D8)
&

CARRY
ouT 3

BUS

+ NXM
NXM Y (cs)\ BGL

(FIG.6-24

! ® AND 6-31)

BGL (1)

CNTRL
c |CLR

Jors.
M796

NPR
.|

CLEAR
LOGIC

NPR CLR BBSY (1)

Ins
LAY

s ( FIG.6 ~23)

BYTE/

om7es

NOTE: Designations in parenthasic

RECORD

{CARRY OUT
2

COUNTER

( FIGS.

contcining corresponding b

g-29 AND

6-31)

M795

(FIG.6-2T)

(FIG. 6-19)

(FIG. 6-13)

DATA —= BUS

Aogzz;egs

rafer 10 enginedring Grown;

| M796

DATA STB 2

A~
REGISTER
oG |(ADDRESS BITS 00 15)

796

TERMINATION
OR LOGIC

——

( CLOCK)
] ADDRESS

LRCSD
SPACE

& (FIG.6-23)
ADRS —=

BUS

$1- 49

Figure 6-18

NPR Bus Cycle

| Block Diagram

6-43

Ne g
T
i . fnid e M T
Bke
gt
B SN eety
gS

T
N il £ g BYt
sl R i e S SRe iesriEalLo e
NV e e
Rt

g i

S§ il

e BTT Bee Be A ST
R A st
eU T O B

! ET F . e e R B
L ey AR
e i, io emp
Tl rhenBnE@i BBl
;Saf;gf’{;,;‘.g
es L
R To e
e eeee N ei eGo el
e RNN
bt

e ki

6.6.4 NPR Read (DATO)

arebinuseedd t
spor
tran
e
tap
the
m
fro
bes
stro
s
iou
Var
)
6-19
ure
(Fig
g
sin
ces
Pro
obe
com
Str
nspctiorton and i other functional areas of the TMB11. Many of the strstra
obeteds arein a separate
4.1a reaFra
6.6.
fun
d
illu
is
g
sin
for
ces
pro
This stros.beMNote the gencration of READ STE. It
before beiappnglicuseatid onin tothethecontTMrollB1er.1 func
and,¢+duemodLoifi‘scdcom
tion obe associated with the LRC character
mon AD is true, however,
figure rted by RDS whe
Sthestr LRC ENB bit is set in the read lines
RD
the
.willassenot assert a READn RE
ss
unle
CS
STB' pulse due to LR
.
”
|
register.

)

LRCS

FROM TAPE J ‘

TRANSPORT

CRCS

L WRS

DELAYE
MS

CRCS + LRCS

(08) »
’

RDS-

TAPE
FROMSPOR
T LRCS
TRAN

(C3)

(Fig. 6-13) READ——

‘

' LRCSD

LRCS

‘

— 10

' BLOCK
(READ OR WRITE STROBE) DIAGRAMS
L TMB1

READ STB |
'

‘

LRC ENB (1)
{Fig 6-13)

[

s refer 1o engineering drowings
in parenthesi
Designotionscorce
sponding logic.

NOTE:

containing

11-4128

Figure 6-19 Strobe Processing

isLrecREeivADed
ter
rac
cha
a
en
Wh
3)
6-2
and
2
6-2
es
gur
(Fi
ion
rat
Ope
mal
Nor
k
rac
7-T
SE
g
9-Ttaprac
andescauA.sinB, and C which
4.2
-flosp gat
6.6.
theADselectDAreaTAd flip
sionsetSEtinLg RE
ert
ass
B
ST
AD
RE
,
ort
nsp
trak and
ebecome
the
m
ble
fro
ena
operat4-5*% and CHAN 6-7* to become DATA BFR IN BIT 0-3h,
9-t*, racCHk AN
In
ue.
-tr
to
TA
DA
witand
0-3
ves
hal
AN
CH
two
e
o
int
gat
d
ely
ide
tiv
div
pec
is
fer
~ res
buf
a
dat
The
.
6-7
BIT
IN
R
BF
TA
DA
0-3
and
,
BIbufTfer4-5 loaded by a separate strobe. DATA BFR STB | loads BF
bufRferSTbitsB 1 (via the
BFf ofR IN
TA
DA
the
TA
hal
DA
h
rts
eac
REwhiADch STloaBd asse
ut
inp
The
.
4-7
bits
and
fer
buf
fer
ds
buf
a
loa
2
dat
the
STB
R
of
BF
ves
hal
TA
h
DA
bot
2
B
ST
R
BF
TA
DA
and
the
c)
s
logi
ize
obe
mar
str
sum
ter
6-5
le
Tab
s.
“evproenvidchae rac
gate
e
byt
a
dat
low
and
h
hig
the
to
0-7
BIT
|
DAionTAassBEociRateOUd witT h the data buffer.
|
|
act
gating
the
or
e
gat
e
byt
a
dat
h
hig
the
her
eit
s
ble
ena
and
le
cyc
bus
R
NP
LO
the
Whenthence
ster07.and
ertorded ingduring
regi
ass
s
is
S
res
BU
add
—
ry
mo
TA
me
DA
t
ren
cur
the
in
00
bit
of
te
sta
the
to
acc
00e
gat
BIT
D
data_bBYyteTE is true the data buffer output is gated to the Unibus
drivers trus ase and the buffer output is
low
TA
ome
DA
bec
TE
BY
le HI DATA
cyc
R bus
. |
. Onbustheas nexD tBITNP08o
to the toUnithebusUni
15.
gated

N 0 - CHAN 7
- RDO corresponds to CHA
nel reversal occurs in the input read amplifiers where RD7
*A chan
.
»
ctively.
respe

6-45

BT
e
s
e R
PR

Baos

o Ee

Shadi
T
g
T
BB

e
e
T

el
I D e B
i
e
G

e
RR

T
T
R
B
e

T
T
e
e
o

e b

T
S

e ]
e
e
R e
S A

e
e

e
o
e

I Se L
§ g e
MR
By el (i
e
L R
e RS
Y R

(
The 7-track operation is identical to the 9-track operation except that the buffer input gate C is inhib- £y
ited. (See Table 6-5.) Consequently CHAN 6-7 are not loaded into the data buffer and there is no data o’
on buffer output lines DATA BFR OUT BIT 6-7, or on Unibus driver input lines D BIT 06-07 (low
data byte) and D BIT 14-15 (high data byte).
|
-

Table 6-5

Mode of

Operation

Data fi"’fiuitip!exing in 9-Track, 7-Track Normal, and Core Dump Modes

Enabled
Gates

Channe‘! Bits
From

Transport

9-Channel

7-Channel
(Normal)

7~Chafmci Iirst

(Core

Dump)

! Cycle
:
Second
Cycle

DATA BIFR QUT

Output Bits

Data Buffer

per Data Cycle

CHAN 0-3

0-3

CHAN4-5

4-5

CHAN 6-7

6-7

A
B

CHAN 0-3

0-3
4-5

CHAN 4-5

- CHANO0-3

CHANO-3

Number of

BITS - From

|
|

|
-

8§

|
0-3

427

4
.
|

|
4

6.6.4.3 Core Dump Op’eration (Figures 6-22 and 6-23) — Core dump operation can be implemented

~only in the 7-track mode, thus both 7 CH and CORE DUMP are true throughout this discussion.

When the first character is received from the transport, READ STB sets the select read flip-flop, SEL

READ DATA becomes true, and gates A and D are enabled. CHAN 0-3 are passed through both
gutes to become DATA BFR IN BIT 0-3 and DATA BFR IN BIT 4-7 into the data buffer. The input

READ STB asserts DATA BFR STB 1 (via the even character strobe logic) and DATA BFR STB 2
thereby loading both halves of the data buffer with the same character. The second character received
from the transport triggers the same sequence except no read strobe is issued from the even character
~strobe logic and DATA BFR STB 1 is not asserted. DATA BFR STB 2 is asserted and loads bit 4-7 of
the data buffer with the second tape character. (See Table 6-5.) The read strobe associated with the
second character initiates an NPR bus cycle causing DATA — BUS to go true and gate the contents of
the data buffer out to the Unibus. Thus, NPR bus cycles are initiated after each even numbered
character is read from tape thereby allowing the two characters to be.assembled into a byte in the data
buffer before being gated out to the Unibus.
|
6.6.4.4

Processor Read (Figure 6-23) -~ During a processor read of the data buffer SEL 4 IN asserts

both HI DATA BYTE and LO DATA BYTE. The latter gates the 7 bits of the data buffer to the
Unibus while the former serves to gate D BIT 08 IN to D BIT 08 on the Unibus. During a processor
read (NPR ENB false) D BIT 08 IN reflects the state of the parity flip-flop as determined by the parity
bit of the LRC character.
p
I

6-46

GO STROBE 2 L

—_L__j——-

EVEN CHAR (@) H

- EVEN CHAR STB L

EVEN CHAR STB H

READ

RDS

STB

o e

i e

el i i

READ STB H

(READ OR WRITE STROBE)IH

m =t
B Nl

(0.S.)

INT+6G0 L |

E63-9 (1) H __[_'

NPR ENB (1)H

S 1,

[

L-_

| I I
11-4127

Jia

Figure 6-21

Even Character Strobe Timing Diagram

LRC ENB

Gy Be
P SR SRRRS S R R R

Sadluid

(1)

ARG

READ STB
-1

(SEL READ

DATA)

CORE

NQO

YES

DUMP

GATES A AND

D ENABLED
YES

SELECTS CHAN
\

GATES A, B AND

C ENABLED

SELECTS CHAN
l

DATA BFR IN

BiT 0.7
l

DATA BFRSTB 2

DATA BFR OUT
BIT 0-7

SELECTS CHAN
Mt

"DATA BFR IN
BIT 0-5

DATABFRSTB 1

B ENABLED

0-3

GATES A AND

DATA BFR IN
BIT 0-7

DATA BFRSTB 1
DATA BFR STB 2

DATA BFR OUT
L

BIT 0-7 l

DATA BFRSTB 1

DATABFRSTB 2

DATA BFR OUT
BIT 0S5

r READ STB

1 - (SEL READ
DATA)

LG.&TES A AND D
ENABLED

_
:

SELECTS

CHAN

0-3

DATA GFA IN

BIT G-7

l DATA BFA STE 2}
DATA BFR QUT

BIT 6.7

CMA
ASSERTED

[

DATA — BUS 1

)

* DATA — BUS

L LO DATA BYTE ]
l

D BIT 0007

]

L BUS DE5-07 1 _

]

Hi DATA BYTE E

L D BIT ©3-15

L BUS Df8-15

‘1141473

Figure 622 NPR Read (DATO) |
Flow Diagram

Tewt

)

$osi

SRS

;i.f':'i;"*t;ié‘z—-«/

S e

ORI

R
R

Dt
R

SRR
R

SS
R

b e

sSR

s
R
oo

e
S

JET

AR,

S Lo

(’
:-

—

A
r

(DS)

PAR BIT (1)
NPR

ENB

(1)

DW——@

PARITY

BIT
FF

GATE

(D5)

NPR ENB (1)

@ DATA BFROUT BIT.O
)

oF
z

BUS

DOO-DI5

UNIBUS

OBITOS-15

DRIVERS <
(D1)

é;\[‘?’lET

(D5)

H! DATA

BYTE

(FIG &-18)

(D&Y

DATA BFR OUT BIT 1-7
Akl

SEL
4 IN

z
|

(FiC

D BIT

00-07!]

;

&-mIT

LO DATA

|®

BYTE

( D6)

DATA BFR OUT BIT 0-7

~—

DATA BFR

OUT BIT 0-3

@DATA

DATA BUFFER

BFR STB

1 (LOAD)

BITO-BIT3

{

DATA BFR IN
BIT 0-3

GATE A

(FIG 6-19)

READ

STB

(SET)

I
3l

—l

SELECT
READ
FF

(FI6

(MTD)

BITa=BIT 7

(D2)

OUT BIT 4-7

“og)"
1

(LC

(D3)

ATA

Da’

L_§'_T.

BFR IN

BIT
4,5

DATA BFR iN
|BIT6.7

GATE B

GATE C

St
)

(SEL READ DATA)

—

(FIG 6-27)

CORE

DUMP (FIG
-

6-13)

6-1g)-NRP ENB (1)

(D2)
[

(FIG 6-19)

LRCSD ( RESET)

(FIG 6-14){ =

[

TRRS

T T

fl_r_;’-«fi; :_L’A‘Y‘,a.'ws.‘ L

-———

(FIG 6-13)

LO8

(05) | CRCS + LRCS

Te——

‘

(FIG 6-19)
CRCS +

(D5)

-—1

LRCS

SEL

36-13)

CMA BIT
00 (1)

————@ CMA BIT
00 (0)

(FIGE6-27)
@‘_‘fiDATA BFRSTB 1

(SET)

CMA

(06)

NPR CLEAR BBSY

B';FOO

(

ol
(02)

J{TOGGLE)

{ (D)

Cl®

[_(resen

}(FIG. 6-13

DOO

(D6)
‘

NOTE 2)

CORE DUMP

< INIT + GO

EVEN

LOGIC

SLCT 4 OUT LO (FIG 6-13)

FIG 6-20

(D2,D6)

.
DATA BFR STB

(FIG 6-18)

3 OUT LO
SEL

STCF;GOBE

CHARACTER

1AD)

’

(FIG 6-13)

DATAT> BUS (fiG 6-18)

‘

(FIG 6-19)

STB HI
L_READ4 OUT

_-———-@1_1

(FROM TAPE TRANSPORT)

| CHAN P

293
|<

TROBE 2 (1

(FIG 6-13)

1G
66-16)
(FIG

(READ OR WRITE STRO

M FIG 6-19)

(D3)

READ STB

\—J

BFR IN

4-7

NOTES:

1. Designotions in parenthesis refer to engineering drowings
~containing
GATE D

every reod slrobe. In

4-(083;T

oulput is

CORE DUMP

corrisponding logic.

2. In 9-CHANNEL and 7-CHANNEL NORMAL MODES outputis

the odd

7-CHANNEL CORE

DUMP MODE

numbered read strobes (Ist, 3rd,5th, ---)

(F1G 6-13)

+u(FROM

M raPE

TRANSPORT)

CHAN 6.7

CHANG4,5

READ

CHANO-3

AMPS

(F166-14)<

CHAN P

RD7-RDO, RDP

(TF:tPOEM

‘

TRANSPORT)

(D2)

1-4122

(

)

Figure 6-23

NPR Read (DATOQO)

Block Diagram

EE T

6.6.6

T S

e T

e N

WA G se
e

NPR Write (DAT]) (Figures 6-26 and 6-27)

6.6.5.1 9-Track and 7-Track Normal Operation - An NPR request must be made (NPR ENB true)

before a write operation (READ false) can be initiated. With NPR ENB true and READ false either
SEL LO BYTE WRITE DATA or SEL HI BYTE WRITE DATA asserts to gate respectively
D00-D07 or DO0S-D15 from the Unibus to the input of the data buffer. The state of bit 00 in the
current memory address register determines whether the high byte or the low byte is gated to the
buffer. During the write NPR bus cycle DATA STB 2 is asserted (Paragraph 6.6.3.1) and asserts

DATA BFR STB 1, 2 which loads the data buffer with the selected input byte. DATA BFR GUT BIT

0-7 is now available to gatés A, B, C, and D. In 9-track operation gates B, C, and D are enabled gating

DATA BFR QUT BIT 0-7 to the tape transport as WD7-WDO. (Note the reversal in the bit/track
numbering sequence at the write gate outputs.) The 7-track normal write data sequence is identical to
~ the 9-track sequence except that write gate D is inhibited. Thus DATA BFR OUT BIT 0-5 are gated to
the transport as WD7-WD2, Table 6-6 summarizes the gating action for all modes of operation.
Table 6-6

Gates

7-Track

" (Core
|

Dump)

Data Buffer

First

Cycle
Second

Cycle

4-5

B
C

0-3
4-5

0-3

4-7

Input Bits

per Data Cycle
'3

WD7-WD4

6-7

7-Track
(Normal)

To Transport

BITS - kFrom

9-Track

Number of

DATABFR OUT | Write Data

Enabled VWrite |

Mode

Write Data Gating for 9-Track, 7-Track Normal and Core Dump Modes

WD3-WD2

"WDI-WDO
WD7-WD4
WD3-WD2

WD7-WD4
|

WD7-WD4

|
.

4
-

6.6.5.2 Core [)ump Operation - Core dump operation is identical to 9-track and 7-track normal

operation with regard to the input gating and loading of the data buffer. The difference is that only

write gates A and B are enabled and they are alternated by EVEN CHAR STB so when one gate is on
the other is off. With CORE DUMP true, the even character strobe logic is enabled and EVEN CHAR
STB is a square wave with its alternations switched by write strobes. (See Paragraph 6.6.4.5.)

A sequence is started by GO STROBE 2 (1) which sets EVEN CHA. STB to a high level'and triggers
the first NPR write bus cycle. DATA STB 2 asserts during the bus « . cle asserting DATA BFR STB I,
2 which loads the data byte into the buffer register. DATA BFR OUT BIT 0-3 is gated through gate B

and passes into the tape transport as WD7-W D4. The first character is written on tape and the first
write strobe is generated. The first write strobe sets EVEN CHAR STB to the low state thereby
inhibiting gate B and enabling gate A which gates DATA BFR OUT BIT 4-7 to the transport as
WD7-WD4 and the second character is written on tape. The low state of EVEN CHAR STB inhibits
another NPR bus cycle. The second write strobe will set EVEN CHAR STB high enabling gate B once
again and triggering the second NPR bus cycle. Thus, the even character strobe logic disassembles the
input data byte intc two 4-bit characters for the tape transport while inhibiting an NPR bus cycle on
the odd numbered write strobes.

6-53

T G

e L

R T

. Ut W

- T

s gt e M B

R T e e bl et B Bl

S TV Rt e e T e T SRS e SR e

R TR O

Processor Write — If a processor write is being executed, SEL READ DATA and NPR ENB

6.6.5.3

(1) are false, thereby asserting SEL LO BYTE WRITE DATA and gating the Jow data byte from the
Unibus to the buffer register. SLCT 4 OUT LO then asserts (Paragraph 6.6.1.1) in turn asserting /TM

‘

DATA BFR STB 1, 2 which loads the buffer register with the input data.

(

6.6.5.4 Write Data Ready (Figures 6-24 and 6-25) - WDR to the tape transport must be true toenable
the write logic within the transport. The write data ready logic supplies WDR to the transport, under
_the proper conditions, and assures a minimum record length of three characters in normal operation
and four characters in core dump. Also during core dumnp, when OVERFLOW (1) occurs, indicating
that the last character has been transferred to the controller, the logic holds WDR true for one more

write strobe to allow the second half of the last data byte to be written on the tape,

WDR is asserted true by the third stage output of a 3-stage counter or by the asserted output ofa 5input AND gate. When a write operation is initiated GO STROBE 2 (1) L is asserted and resets the

R via the OR gate. OVERFLOW (1) H is
counter. The third stage output of the counter asserts WD
set. The first three write strobes set the
to
counter
the
of
stage
first
the
false, thereby conditioning
causing its output to the OR gate to
stage
third
the
sets
strobe
write
third
The
in order.
counter stages
true. Note that WDR is held true
WDR
holds
and
enabled
now
is
gate
assert high; however, the AND

- for three write strobes regardless of the state of OYERFLOW (1) H.

When the desired number of characters have been transferred to tape, OVERFLOW (1) H goes true,
conditioning the first stage of the counter to reset. The next WRS strobe resets the first stage inhibiting
the AND gate causing WDR to go false. If CORE DUMP L is asserted the AND gate will not be
inhibited until the next WRS strobe when the second stage is reset. Thus, in core dump mode WDR is
|

held true for one more write strobe after OVERFLOW (1) H asserts.
<

( FIG.6-18)
~ (FROM UNIBUS )

(FIG. 6 -16)

—

BOL

NXML

LO
L

___CUR DEL (1) H

D__

(C3)

WRT DATA ENB H

(FIG.6-13)
CORE DUMP

( TO TAPE
"TRANSPORT )

OVERFLOW (1) H
(FI6.6-31)

15! !

Dznd‘

(C3)

STAGE

(FROM TAPE

TRANSPORT)

(FIG 6-16)

0} —

WRS H

D3rd‘

STAGE

STAGE
€3

GO STROBE2(1) L

NOTE :

Desigpo.tions in porenthesis refer 10 engineering drawings
containing corresponding logic.

11-4131

Figure 6-24 Write Data Ready Logic Diagram
6-54

(

e e eg e

GO STROBE 2 .

es S

e i

[

}\X

WRS H

(9st. STAGE OUT(1))

OVERFLOW (1) H
O

(2nd. STAGE QUT (1))

(3rd. STAGE CUT (1))
WOR

(3 TRACK AND

TRACK NORMAL)

V/DR

CHARACTERS —

}@/

( CORE DUWP)

,
~m
e

4 CHI%RACTERS

!Ag’

demm—
-

e
‘

| -

Figu‘reé-ZS

11-4123

Write Data Ready Timing Diagram

Due to feedback from the second counter stage to the first, two write strobes must occur (to set the

(

second stage) before the first stage can be reset. Consider the case where OVERFLOW (1) H asserts
after the first or second write strobe (Figure 6-25). The first stage will reset on the third WRS which
also sets the third stage. If, in core dump mode, the AND gate holds WDR true until the fourth WRS
_ strobe which resets the second stage thereby negatmg WDR. Thus at least four write atrobcs are -

issuredin core dump operation.

o i

il A bt e

6-55

DATA BFR QUT
BIT 0.7

GO STROBE 2 (1)

\
t EVEM CHAR STE

GATE B ENABLED

YES

CHANNEL

GATES B, C AND

SELECTS DATA
BFR OUT BiT

GATES B AND C

D ENABLED

ENABLED

0-3

WD7

WD7-WD4

WD7-WD2

{
WRS

YES

_ miTtoo(0)
ASSERT-

{SEL LOBYTE
WRITE DATA)

{READ OR WRITE

STROBE)

’

- SEL HI BYTE
WRITE DATA

SELECTS D&g-DF7

STROBE)

SELECTS D38-D15

’

]

GATE A ENABLED

DATA BFR IN
BIT 0-7

SELECTS DATA BFR

OUT BIT 4-7

WD7-WD4

_
-

(READ OR

WRITE STROBE)

]

DATABFRSTB 2

t EVEN CHAR STB

DATABFRSTB 1

)

( DONE

114141

Figure 6-26 NPR Write (DATI)
Flow Diagram

6-57

e e(L5 LT

T e

——t= (F|

(FIG. 6-13)

CORE

(FI6..6-16) —

" 6O

(FIG. 6~ 19)

DUMP

STROBE

EVEN

! CHARACTER

g U;SE?BE

(READ OR WRITE STROBE)

FIG. 6= 20

(FIG. 6 -13)

(FIG. 6-18)
.

CORE DUMP MODE)

.E DUMP

(FIGURE 6-13)

CORE

7CH

(FROM TAPE TRANSPORT)

SLCT 4 OUT LO

STB

(D2, D6)

)

(HIGH WHEM NOT IN
EVEW CHAR

WLOAD) DATA BFR STB 1, 2

DATA BUFFER8 R:

DATA STB_Z

(D2~
]

)

A/A\>

8-8BIT
GATE

D2,D3

BUS D@P - D15

UNIBUS

DPP - DB7 f

(D1)

(SEL

"NOTE
Designotions in parenthesis rafer to engineering drawings
containing corresponding loglc.

GATE
A
e

BFR OUT BIT 4-7

wD7 D7-WD4
-~

(o)

DATA BFR OUT BIT 0-3

DATA BFR OUT BIT 4,5
[~

"1 GaTE
B
4-BIT
=~

(D6)

GATE
C
‘

(o)

WD7-WD4

WDD -WD7

5 (TO TAPE TRANSPORT)

2-BIT

WD3,

3 WD 2

)

DATA

BFR OUT BIT 6,7

TM1

GATE
C

2-BIT

WD1,

.DATA

BFR OUT

"BIT@-7
l

ZGISTER

(MTD)

-D3)

i DATA BFR
BIT @-7

—

8-BIT

(FIG. 6-13)
|

GATE

(FIG. 6-18)

D2,03

‘

~
t(SEL
Hi BYTE WRITE DATA)

L LO BYTE WRITE DATA)\-L_*_
/(02) F—

/(02)
\___‘

READ

‘
NPR
ENB

(D2) }—

CMA BIT

<
po (9) (FIG. 6=-23)

(D2)

DATA

(D2)

(

SEL READ DATA

NPR ENB (1)

)

(FIG. 6-23)
(FIG. 6-18)

11-4134

Figure 6-27 NPR Write (DATI)
|

Block Diagram

6-59
_

6.6.6

Done Logic (Fipures 6-28 and 6-129)

The done logic senses the completion of an operation and functions to assert control unit ready (for
another command) and issue an interrupt request to the interrupt logic.

Ila spucing operation was being executed CARRY QUT 2 signifies the completion of the operation by
asserting when the desired number of records has been spaced over. If a read or write operation was
being executed (SPACE false) the asgertion of LRCSD significs the operation is over.

during t‘h@ operIn both cases the done flipsflop is set and DONE (1) is asserted. If ERR (1) asserts
errors will interrupt
ation a done sequence will be triggered before the operation is completed. Certainallow
the operation to
will
an operation by asserting ERR (1) as soon as they are detected. Other errors
terminate normally. (See Paragraph 6.6.7.)

When DONE (1) asserts and the tape transport comes to a stop (TUR t‘rue) DONE DELAYED (1)
asserts in turn asserting (GET NEW CMD) to the bus interrupt logic and SET CUR to the operation

start logic.

e
el e

Some conditions that will assert DONE DELAYED (1) without waiting for TUR to come true are:
An illegal command [ILC (1)] -

Reaching BOT during a space reverse operation

Reaching BOT during a rewind operation that was commanded by the processor
o

Deselecting the drive

a local command.
When the transport starts a rewind from

6-61

SELR

R¥S

BOYT

k¥

CHG TU EFREB

REV BOT

CUR DEL (1)

114142

Figure 6-28 Operation Done
~

Flow Diagram

6-630_ ‘

ogresmme spppms T
-

START

J
CARRY OUT 2

LRCSD

ERR (1)

YES

SPACE

TUR

iLc (1)
YES

‘

DONE DELAYED
1

(GET NEW CMD)

SET CUR

[Lgi.

)

‘ DONE
\

ARl

(FIG. 6-13) { SPACE REV
)

.
“ (C3)
l.____..._
/

SELR

TAPE TRAMNSPORT

> (FIG. 6-16) [_~

REV BOT

) J

)(03)

BOT

FROM

CUR DEL (1)

(FIG.6~16)

REWIND

(C3)

R¥S

CHG TU ENB

& (FIG, 6~ 31)

(FIG. 6-18)

CARRY OUT 2

(C3)

FROM

LRCSD

SPACE

TAPE TRANSPORT

(FIG. 6 -13)

(FIG. 6~13)

SPACE

(c3) Jj}

TUR

7:2;?}—7:
DONE (1) L
i

(C3) YISET)
DONE

vy
BE 1
—2 >TROBE

( RESET .

(FIG.6-16)

(c3) o

(FIG. 6~6-31)
_fLe |
(FI6.6-31)—

NOTE

‘Designations in parenthesis refer 1o enginearing drowings
contalning corrssponding qulc.
e

s—

Ela S RS e e

s S

IR0

(FIG. 6-33)
DONE

; DELAYED
DONE

(SET) DELAYED

(1)

(cqy‘(GETrNEV/C M D)
‘

0.S.

(C3) 0

Figure 6-29 Operation Done
Block Diagram

6-65

Nn-4133

6.6.7

Fevor

Logic (Fipures 6-30 and 6-31)

FRR (1)is asserted by any of the error conditions that could arise within the system, When ERR (h)
comes true it sets bit 15 in the command register and triggers a done sequence. The error conditions
that assert ERR (1) are in two classes: those that assert ERR (1) immediately and abort the current
operation, and those that allow the operation to terminate normally. In the latter case ERR (1) will
become true with the assertion of LRCSD,
Errors that abort an operation are: NXM
BGL
1L.C
BTE

Errors that allow an operation to terminate normally are:
RLE

CRE
PAE
EOFF
End of Tape Error

an NPR bus cycle.
NXM and BGL are error conditions that arisc from the execution of
[LC is asserted under the following circumstances:

¢ When the processor attempts to access the command register while the controller is busy executing a command (SEL1 OUT asserted while CUR DEL [ is false),

e When an on-line transport is deselected while an operation is being executed (SELR negates
while OFF LINE and CUR DEL 1 are false).

® The controller attempts to initiate an operation on a deselected transport (GO STROBE 2 (1)
asserts while SELR

1is false).

¢ The controller attempts to initiate a write operation on a write protected transport (GO
STROBE 2 (1) asserts while WRITE ENB and WRL are true).

BTE is asserted when a read strobe occurs during the gap shutdown or settle down periods provided no
BGL, NXM, or ILC errors exist. (RDS asserts when either SDWN or GSD is true and the following
are false: BGL, NXM, ILC.) Gap shutdownis the period between the end of a record and the begin- ning of the settle down mterval (from the assertion of LRCS to the assertion of SDWN).

RLE (1)is asserted when a read strobe occurs after an overflow condition has been sensed except if the
read strobeis a CRC or an LRC strobe (READ STB asserts when OVERFLOW (1)is true and CRCS
+ LRCSis false).

CRE (1) is asserted during a read or a, write operation when a read strobe occurs and a CRC error
exists. (RDS asserts while CRCE and READ + WRITE are true.)

PAE (1)is asserted during a read or a write operation when a read strobe occurs and either a vertical

parity error or a longitudinal redundancy check error exists. (RDS asserts while either VPE or LRCE
is true and READ + WRITEis true.)

6-67

EOFF (1) is asserted when a file mark (FMK) is received from the tapé‘ ‘;trféns:pvort. .
An end-of-tape error is asserted when the end-of-tape marker is sensed during a transport operatiot
.other than rewind or space reverse (EOT asserts when REWIND and SPACE REV are false).

]

=
R

‘.:

“

23
N

-’

)

6-6R

—

A rv———

READ STB

RDS

FMK

RDS

EOT

REWIND

RLE (1)

(END OF TAPE

EOFF (1)

CRE (1)

ERROR]

PAE (1)

YES

B
A

ERR (1)

BGL

NXM

]

| ( DONE
114137

Figurc 6-30

Error Scquence

Flow Diagram

6-69:L

(SET)

iLC (1)

&= (FIG, 6-~29)

ILLEGAL
COMMAND
FF

(C4)

I@/& T

()

BGL + NXM

IG. 6-18)

(ED

iLc (1)

(C5)

& (FIG, 6-16)

(CS)

BTE

-14)
.

L[]

NXM

(FIG. 6-18){ BGL

WRITE

9 ©

CRE (1)

FIG. 6-14 AND
6-29

-18 AND 6-24)

T
LRCS

RLE (1)

—

(FIG. 6-19)

LRCSD

SET)

PAE (1)

DpariTY
ERROR
FF

| (RESET)

(C4)

11- 4135

Figure 6-31

Error Sequence

Block Diagram

A -

< TR i SR dirhamiye Rt e, Voo find i AT B
T TR Sy St Se pt
e 2t e L e
e bye
e ST i
Bl T e s
e PD0gt
ikLied
b
eet il
e
T R D St
S
e e DR
e Be e e
Gi

i
e

ot
# sy

Interrupt Bus Cycle (Figures 6-32 and 6-33)

6.6.8

An interrupt bus cycle is initiated if the interrupt enable bit (bit 06) in the command register is set and
anv one of the foliowing occurs:

GET NEW CMD asserts from the done logic.

The tape comes to a stop (TUR asserts) after a rewind operation.

The processor requests an interrupt.

The setting of the BR interrupt flip-flop starts the interrupt sequence. The flip-flop is set via a gate

enabled by INT ENB (1) from the command register. The other gate input comes from the set interrupt one-shot or from the processor. The set interrupt one-shot is triggered by GET NEW CMD from
the done logic (if an interrupt bus cycle is not already in progress) or when the tape transport stops
(TUR asserts) after a rewind operation (BOT is reagched when CU READY and RWS are true), The

processor initiated interrupt is accomplished by the processor asserting SLCT 1 OUT LO and DOO

“after it has set the interrupt enable bit in the command register.
|

NOTE

Processor initiation of an interrupt is done for special software purposes and is not a normal occurrence of TMB11/TS03 operation.

When the BR interrupt flip-flop is set, BR INT (1) asserts enabling the Unibus request logic. The

Unibus request logic asserts BR QUT which becomes BUS BRX to the Unibus. The value of X is
determined by the priority jumpers and may be 4, 5, 6, or 7 (usually 5). The processor responds to the
bus request with BUS BGX IN which becomes BG IN and enables the Unibus acquisition logic. The
Unibus acquisition logic asserts BUS SACK to the processor which responds by negating BUS BGX
IN. The acquisition logic checks for BUS BBSY (by some other device) and if it finds the bus free
% asserts BUS BBSY to the Unibus (indicating bus mastership) and BR MASTER to the interrupt
circuits. BR MASTER becomes BUS INTR and is placed on the Unibus along with BUS D02-D0S3,
thereby commanding the processor to-initiate an interrupt routine starting at the address specified by
BUS D02-D08 (address = 224). Processor acceptance of this data is indicated byits assertion of BUS
SSYN to the TMBI11. BUS SSYN becomes SSYN and triggers the interrupt done logic. The interrupt
done logic asserts INT DONE B which completes the interrupt bus cycle by resetting the interrupt flip-

A RN

flop and acquisition circuits.

6.6.8.1

BUS BGX OUT

A BUS BGX IN from the processor is passed from one system device to another in daisy-chain fashion
until it reaches the device that issued the BUS BRX. A BUS BGX IN received by the TMBI 1 1$ gated
back to the Unibus as BUS BGX OUT if the controller is not making an NPR bus request (BUS NPR
false) (NPR requests take priority over all BR requests) and one of the following conditions exist:
I.

BR MASTER is true (TMBII is presently bus master).

SRS
e

2. BRINT (1) is false (TMB!! did not issue the BUS BRX that caused the BUS BGX IN).

6-73

t BOT

START

t (GET NEW CMD)
BBSY FF

SET

tSLCT10UT LO

INTERRUPTTM
CYCLE
IN

PROGRESS
BUS BRX*

BUS BGX*® IN

SET INT (1)

BG IN

1 -+ SACK FF

A
{ BROUT

BR INT (1)

BUS SACK

\
1 BUS BRX*

SACK FF

SET

| BUS BGX" IN

(- 75

——

INT DONE B

0— BR INT

\Y
0 - BBSY FF

{ BR MASTER

V
| BUS BBSY

I BUSINTR

{ BUS D2.068

1- BBSY FF

0 -+ SACK FF

BUS BBSY

BR MASTER

\
1
| BUS SACK
‘

BUS INTR

BUS D02-D08

t BUS SSYN

)

A
SYNC
*X=4,560r7

11-4138

Figure 6-32

Interrupt Bus Cycle

Flow Diagram
-

BSOS

INT ENB (1),

" SLCT 1 OUT LO

beéd
. (FIG.
6 -13) <
\

INT ENB (O)

.
(DY)

J—

)

INTERRUPT

(INTERRUPT ENABLE PULSE)

ENABLE
0.8S.

(D 9)

(FIG. 6-16)

CU READY

BOT

RWS

FROM TAPE

( TRANSPORT

L—fl

L—--—--‘(09)

TUR

SET INT (1) (SET)

(D9)

%
1

FF
cq4)

(FIG. 6-16)
)

(FIG, §-29)

SET

INTERRUPT

{D9)
:

GO STROBE 2 (1) j

(D9)

(RESET)

(GET NEW CMD)

NOTE

Desighations in porenthesis refer to engineering drawings
contalning corresponding loglc.

X=z4 5607,

6-77

SET INT (1)

}(DS)

—

INTERRUPT

(D9)

e ad e

UNI
lr

BUS

[

BUS

BG X *

BUS

SACK

BUS

BBSY

BUS

INTR|

Dg2-Dgs

BG X ¥

SSYN

ouT

PRIORITY

‘”Jgg%’?
JUMPERS

JUMPERS

(D9)

M7821

(D9)

JUMPERS

PRIORITY

BG IN

UNIBUS

)

ACQUISITION

‘

LoGic

BR MASTER

M7821

—

BR INT (1)

(FIG. 6-18)

BUS NPR

INT DONE

Laam/

7821 )

INTERRUPT
DONE

LOGIC
K7621

7821

OUT

"——L—J
SSYN

\J
-

)

11~

4130

F igure 6-33 lntérrupt Bus Cycle

dedal

Block Diagram

D PSP
SR
Po AR

LRC H

;

GO H

MTBRC

~l_

T
i

H
CU READY

777775l

777776

00G000

TrTTev

"W-03867

Spacing Reverse Three Records

CU READY H -1

LRC H

/ pm

[¥\

‘ l

. /”

SN TS S

SIS WU

ol RPN MO

e R ——

s R T

‘

g
o g
b T

Figure 6-36

, £

MTBRC

BTE

SISSN STy

777775

Figure 6-37

777776
/

H-0386

Spacing Forward Three Records, Bad Tape Error Appearing in First Record

680

i F il

Ve
e
ey

auldl..u

TUR H )]

ey e

L s, T e

v oy
I & L. o I EL
S . Bl
e e g q go T e
eb

P——

e ] 2

‘fl-—/f.m»

CLR BBSY H

H .

400
s ——|
———+{a——

NPR END H

Ly
Ry - fl—-{ o

RDS

e 4005

be— 1005+

CU READY H i

MTBRG

777123 ‘ 777124 %* 777125 { 777126

MTCMA

123123 ! 423124

123125 ‘ 123126

CRCS

{

CRCE

LRCS

LRCE
]
VPE

r—=

Lo
Lo
vy 1 | T | ]

[i
'Jrl_fl

I skt

¢
et L 1 | |

r—-

10t

A i

11-0383

Sldl.

6-81

GO H _,M[1
EVEN

CHAR

RDS H

H
NPR INT

CLR

BBSY H

2 00ns ——

;}fl

'r@j—““\OO;us

[LF

MTBRC .

777123

——

MTCMA

123123

123124

READ STB M

)

B ‘

LRCS

l l .

| l

B
e

['“] )
:

R K4

11-~-3992

Figure 6-39 Reading Record of Two Tape Characters in Core Dump M'q_de‘

6-82

CU READY H “]

“‘%”*”“‘OOPS*—@J

MASTER H

NPR INT H

GO STROBE 2H u__[;;]

J_L,

CLR BBSY H

MTBRC 777775

/L__-//__J———'L__.f;._—__

WRS H

‘777776

777777

lOOOOOO

WDR

CRCS

)

e e

e g

OVERFLOW H

[

Tl e
.
Tl
e DT
i T by T

CRC ERROR

LRCS

LRC ERROR

.
gl |

!
'
U

="
'| '1

74N

‘
.

r—"
'
r .,

1 K4

'
t

it |
'
1,
1A

]

r—"
|
'
'
'
11-0384

Figure 6-40 Writing Record of Three Data Characters

w‘#‘l\f i

6-83

Soovd

LRI

CU READY H 1

CU READY H

GO STROBE 2 H

//?f

(

L
100ryps —]l
le—

CHAR

NPR

INT

CLR BBSY

MTBRC

MTCMA

UL BN SRS 2]
S
T o
PSR A

reimco bbbl WP T
1

]

777777]4

000000

123123fif23;24

OVERFLOW

WRS 'H

EVEN

‘

CRCS

LRCS

I
-

‘

l
'

'FigL.er 6-41 Writing Record of Two Tape Characters in Core Dump Mode

11-3593

CHARPTER

M8926 Theory of Operation

{
7.1

General

(Figures'7~1,7~2

and

7-3)

Figure 7-1 is a simplified flow diagramvof the M8926 interface anrda

The CSET command from the contrgller triggers'a drive start-up sequenc
The start-up sequence signals the drive to start the &xive motor and
introduces an 8.9 ms delay for. the drive motor to get'up to speed
(45

ips)

before

211 commandszs
read

enabling
a read or write

seguence.

from the controller except rewind,

seguence

to occur.

The

read sequence

from the drive to the M89%26 board.
asgerted by the

controller to

will

cause a

tranasfers data

A write command (WRE) must be

enable

a write

sequence.

a write

~command is asserted by the controller, data is transferred from the

controller to the drive to be written on tape (write sequencé).
data

written

tape

immediately

read

back

via

the

read

The

sequence.

This read-after~write fea?ure allows the recorded data to be checked
for errbrs by the M8926 board.

The read-after-write data is madgf

available to the controllerAwhére it can be accessed by the processor

for’maintenance purposes.

During normal operation read data is not

accepted by the controller unless a read command is asserted.

When

the

- sequence

circuits

triggered.

the

drive

motor

and

the

drive

motor

read

terminated.

detect

The

down

end

stop sequénéé

initiates
slow

the

another
to

stop

8.9

the

record
a

signals
ms

before

stop

the drive to

delay.
the

drive

The

command

delay

stop
allows

operation

ad..

‘functional description of the M8926‘interface board. This diaqramh
shouldvbe read in its entirety while referencing the functional

block diagran, Figure 7-3. Subsequent sections in this éhapter

fireat the M8926 board according to the functional divisions shown
in Figures

7-1, 7-2 and 7-3,

namely:

Status/Command

Drive

Writé Segquence

Read

Drive

Start

Logic

Sequence

Stop

It will be helpful to refefence'Figures 7-2 and 7-3 és an overview.
while reéding,thréggh Chapter 7. |
HOTE

The block diagrams that follow use 1ogi§al |
AND and OR symbols. It does not necessarily |
follow that a correspondihg gate exists on'the
controller logic prints.

n
The assertioof

inputs A and B causing the assertion of
output C may be
by a

represented on

single AND gate yet

the

a block diagram

engineering

Qrawing

may show that several circuit stagés are involved
in the ANDing operation.

The signal names used on tfie functional block
diagrams are the names used én the engineering‘
circuit schematics (CS prints).‘ Where other
okt

"signal names or notes are used they are enclosed in

Set B

(Figure 7-2) provides a more detailed

The MB8926 detailed flow diagram

.- parenthesis.

7=2

ég}

mdu

)
( START
Y

CPAPE

)

DRIVE

UP Te

(%a Cf f‘"fi S»')

SPEED

“@Wfi%\ NC

LeoMMANDS

READ

SEQMENCE

SEQUENCE
R

>
‘«w‘«h

SLow
TAPE DORWE
SToP
powlN Yo

(gacf MS)

PR
RP

- (oore)
FiIG

7-1

M8926 Simplified Flow Diagram
7-3

CSET

TAPE DRIVE UP Te
(.9 Ms)

(

WRITE

SEQUENCE

SPEED

READ

SEqQUENCE

TAPE DR\WE Stow
STOP
‘DowN TO

(gec[ Mg) |

)
(DONE

(

'F,Gl' 7-1

M8926 Simplif»iAed Flo’w' Diagram
7-=3

.S‘.|RIs|ESw&EuL%Ru:EmFfIi:CIF)ITE..xWta,f.omwsmmr_guolHefwLfMi.rea)2ede.yLd.;a4mo

| ~ |A| . s
| |

01907 341dm | A

7-4

)
QWvo3uadywmf2i1.9|07sne>y+go& CAR ?Jrfn.u.42

:MS- | ‘ _.Y4.81dnm?mzfm1u]°3no%T‘v,ZQ|:. .|_‘w‘Nfg4iO.SoIsmMg[wpLauer\!Oyu,oW\mT.:\R'y2H]TdA+dL0a.UQo)rQLtl-iE.IuwtsnNAefeG\ms)Ylpreqvuwu%%e2%%M1fd9iDWwHu0m+.a7i»L9+qO%&y1uA3nMu2mLWa4do48oCi0QMf)SogdW2d(WT‘@yoE«<s»lpdS|”PMx.oAm4\q%)e&PuMP:\Le.TL(S\of:Al.duvPrOY4e»:e+Q&daadwv1hsa..m3.u_;tfi%sowlf.\lim,*.a.%uumoVx1mt_4n,mmI&.»rom.f°.faiv3:av2uwabfmyif]iupu{we.peod.I.Tm.sod
B

!|.

39Z2b3WaoTwz.Wmxw|12574MwmnwZ-L9CZ68NWI.3@@@.@@M|w@ymm.uwexb.eld-A
)

mo.FMflwlfxwamcl“.‘FAIP

wfNiofil.LfiO.:W.H»m10p¥yaLN%OoD0922419o~071:]o2aav4uqw)A.mxfmi_hw . |

¢nh . ||o72C5‘83Sv5ss32MeJuar,4y&ffdnw)N.ice4:afOmaiu.pwsswdu.uv@iys\LpL9DoH\w4+‘f0QImTi7QYNPr:9sz4.IR0o&WcGy9¥oavDf17dads32uuYoP0aLwaTM9x¥ynSEu0sbI|mod4yeTt-sOA¥:Aom7.ob1aM¥..$0&mmP18nocu&£.fvi,.5w«e\o.1uow#s.4yEfwg:l_\fN&Iii|sYox_mDpfEn\ietwd;fPsle\¥AoEmu\u".wn§Y\Sow|dTehuoL.4Mo%2e"ySwfDM.l*ZsmmJ|.I\-*B:A‘B:YD . |o ‘ a.0|
3

[

+LCH

S Rl
a-cnerl
i

TRANS PORT[#

STATUS

4 CRWS

SOHWN

)

END_PT

¢
<

TUR
MoL

£,

CSELR.

$Sp~ ss2

2
CSELE - CSEL
CWRE

Rws

“TUR

ROT

LOGIc.

£C CEOT
CEDLN

)

| COMMAND

TA —

L CRWD

WRITE

LOGLC.

REV

JcnEng

L CRwD

)

EWFME,

»
5

EPEVN .

Y- COEN T

v CWEMK

« CPEVN

Clr

vag

RwND

’

pEN &,
DENI

EWD

~APE

TRANSPORT

e
'
b

‘

>-£
¥ DX
4 C WRS

_,gfi_g_\ifii_fi,
.

WeT _CLK

PARITY

wDP )

GENERATOR

‘

L Fiie mare | |

~LuELE

- GENERATOR | |

LIZE

)

Wpé~ WD
7

J}fi

CWRE

‘

» END OF

RECORD

LeevEraer

WRITE

LRC STRE

oG IC

—_ - =
|

SET

RD_CiR PLS,]

MOTION

coNTROL

r—

LT AR

.
« CRDS

—

Reap

CHANNELS

& SEMK

<CCRCS

< CLRCS

« CYPE

< CCRCE

CLRCE

|
.

‘

FILE

DECTOR
OF

ERROR

DETECTOR

KOG —RD7T RDP

RsDO

|
< HWRT CLk

DET ECTOR

ACCl

CLOCK

RECORD

MARK 4_1_213&

END

<BR CLR PLS

<ro P

RbP=RD%, RDP
77—

DRY SEY PLS,

CADINE

—

\ CWAG

Rreadp

LoGIC

l
<

EPEVN

[eTEFoR
|

FIG.

7-3

7-6

M8926 Block Diagram

(

Status/Command Logic (Figures 7-5 and 7-6)

7.2

7.2.1

Command Logic

Some operational commands are coupled from the controlier to thedrive via passive logic circuilts.

Other commands that must stay

asseited during the entire operation, are latched up in flip-flops

- set by CSBT~from the controller. 'Note the conversion of CDENS

to DEN® and CDENS8 to DEN1 during the latch-up process.
CSEL@-CSEL2 selects a slave unit via a 3-bit code.

The 3-bit code

" is latched up in the slave select latch-up flip-flops which output
SS@P-SS2 to the drive.

( '

The input code from the controller 1s com-

pared to the output code in the slave select comparator.

If the

two

clocked

codes

not match

the

latch-up

flip-flops

are

forcing SS@P-SS2 to agree with the select code from the controller.

An AND gate must be enabled by MOVE before clocking of the flip=Llops c:

occur.

MOVE is asserted true during‘every command operation’except

rewind.

Thus'a new slave drive cannot be selected during a data

transfer operation; Note that a bit reversal tékes piace in the

latch flip—flofis where the CSfiLfl, 1 and 2 inpfit'bits become bits‘
§s2, 1 and g respectivély in the output.
-

7.2.2»

Status Logic

~Some status signals are directly coupled from the drive to the

controller while others such as RWS and MOL undergo conditional

gating.

’

Rewind status

(RWS)

from the drive negates at the end of

SDWUN simultaneous with the assertion of TUR (see Figure 7-4).

timing requirement within the controller is that RWS negate before
f§

TUR

asserts.

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6
|

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SLAVE

v iitfig\gflflfii

;

(Fie qu)fi@———b SLAVE

L—-——A{H& ’7-/3)

fwp

EWFMK

}(FIG 7-9

EPEVN

;Q:uc -1 AND '7—/3)

_EDENS

AND 9-11)

pENd
DENYT ,.

> (Fn@uees 7-9,.7—1l AvD 7~ IS’)

COMMAND
7-10

’

Fie.
STATUS/COMMAND

7-6
Block

Diagram

This

requirement

proper

CSELR

CRWS

timing

1is

negated

the

slave

select

with

the

allows

. new

is met by ANDing

for

shown

logic.

output

settling

Figure

while
This

the

1is

slave

select

RWS with SDWN thus producing

new

7-4.

drive

accomplished

select
code

the

being
by

one-shot.

before

CSELR

selected

the

gating

The

MOL

delay

asserted

for

the

drive,

When a 7 track drive is béing used 7CE is asserted from.the drive
causing the éssertion of C7CH to the controller and R7CH to the’

7TRK fiip—flop.

When SET asserts 7TRK becbmes true to indicate

L05k:A&fiwL:fl):kw)‘MM’SRVN R

the presence of a 7 track, slave drive to the M8926 boérd.

Note

thatthe assertion of EDEN5 will alsq cause 7TRK to becomé true

at SET time.

Compatibility between the TU10 and TU10W drives requires

that both EDEN5

7.3

Drive

Start

and R7CH cause

(Figures

the

7-7,

assertion of

7-8

and

7TRK at

SET pulse

time.

7-9)

7.3.1 Drive Sfart Signals
The

SET pulse

starts

the

command

operation

the

drive

by:

é.

Setting the EMD flip-flop and asserting EMD to the‘ drive

Asserting DRV SET PLS to the drive

'Setting the MOVE flip-flop thereby negating STOP to the drive

MOVE remaihs asserted and holdé STOP false during the entire command
operation.

During a rewind operation the MOVE flip~flop’is not Sét.

In this case‘
sufficient

for

DRV S5ET PLS negates STOP at SET time which is
the

drive

start

the
-

7-11

rewind

sequence.

Start Up Delay

' 7.3.2

PSR

XD e

RS BT
S VNN S VSIS SIS LR 0TI

" The output of the EMD flip-flop loads

the motion delay counter with

is preset to

of the counter

clock pulses are obtained

The

and gates in the clock pulses.

¢ 4 counter which receives CLOCK

from a

pulses from the slave bus.

Bit 13

RDP by the drive.

deiay data set onto read lines RD@-RD5,

An output from the 4 counter is obtained

after the first 2 CLOCK pulses and every 4 CLOCK pulses thereafter.
After

8.9

bit

counter

counted down

and

Input clock pulsés to the delay counter aré inhibited

READING is asserted enabling the read seguence |

ACCL is negated to the drive thué gafiing WRT CLXK pulses
in

delay

At this time:

bit 14 is asserted.

the

from

command

generated

the

prior

drive

CWXG

for

the

or CWFMK

writing

the

write

segquence.

extended

record.

interrecord

CWXG

EWFMK,

gap
if

1is

asserted,’

input into the delay counter increasing the 8.9 ms delay time and
allowing the
write

tape to travel

sequences

are

an extra distance before the

enabled.

The

CWXG

and

EWFMK

delay counter are via a gate enabled by ACCL.
start-up

7.4

time

gap

WritéSequence

7.4.1

Nine

7.4.1.1

Track

Write

prior

the

record

inputs

read and
to

the

Thus only the

extended.

(Figures 7-10 and'7-11)

Normal

Data

If a write command is asserted
by the controller, WRE will be fixue
;fi

allowing

the

SET pulse

set

the

WRITING

7-12

flip-flop.

The

assertion

(

:
DU i i
e T b Re
s
SESNSIOYIRINSE
<SN
e T A S
e
e et

START-UP

S e

i A

Ao gL
s e

e r o i

JRIWVE

ciock

COUlv Té@;

(%00 BPD

Acel
_
READING

B e
T
s

e
R

;

's.\.

AEMD
pIT 13

RIT )4 __

RIT 15
RD CLR PLS .__

7=13

DRIV

N
SHUT] oW

WW’:’;@ -

—

oy s eI

—

gYwdt

TSbl

7-7

Flc.

—~

M8926 Timing Diagram

4
-+ T
RESE

couwTER

[AErD]
‘i’

——

[LOAD,S MOTION DELAY COUNTE;‘?]

liNHIBITS

MoTioN]

PELAY COUNTER

E@—&Brrlgj
¥

[ clock PULSES]

1> E88—9

[INcREMENT MOTION DELAY COUNTER)|
Z-»BIT13>-10

YES

:
!

| 2 CcLock PULSES]

|
Y

INHIBITS MOTION
COUNTER

DELAY

|g— E33~9|

|1— BIT 14
o

| # —EMD FF|

l¥ EMD|

READIN G

$ ACCL

(Fle. 7-12)

Fre. 7-10)
7-15

[2 clock PULSES]
[

PCLR

[sEr MOVE |
b

YES

DRV SET PLS |

[ MoVE
|
5

g
| STOP

—

14 AEMD]

CLEARS CRC AND
LRC GENERATORS

Fig 7-8
Drive

Start
Up

Flow

Diagram

(
7-16

e TR

NS St

s B0 s B
4

T L LR SR T

somta

e b

T e

Sl
pe
R

S TR
D

R eT

ARk

RIS
SN RT PR

R CR T

{

PCQR

B WS L

GR@M HoST DRWE}

SET

G‘EG ."7«-&5

| (1)) SET

RW D
GcT

MOVE

__gm

)

ACCL

(B)-4

CoNTROLLER

FROM

TAPE

DRIVE

cLock

(CcLEAR)

(HGQ r,'-jq>~' RD_clR PLS (3>

e ARG R

g Bty

e flg}ifig&g ik

e e

o ii

v i T S i

el S

Tt i

g ssiduising JEalia

G Bl

sy i o A A SO I RV Susnifio R

e il SO

SRA D T

et g

From

7-17

COUNTER

(3)

MoV E

AoV

LMoY

prv SET pLS (SR)

@NVG) o 2TOP
L

> (Ficuees

an @} |

0-9, 7-4, 7-13 ano

CCZ’LEAR) .

16—

BIT

LResEDY rems
|

(seT)

1§

(crock) .

(3,.)

~§&i? [4)

Gr‘

{}JL
'

Embp (Loab)

7-1

Anp

7”/

o aceion), Ggg%
PRiVE

‘—:@Afim—’?
é: TAAMA

,G—

DELAY
COUNTER

BIT

MOTION

G’"G 7“12>JRD¢~RRD$‘J RRD P

(WG '@

7-17)

-3/

f@)\EM D (SBB (To TAPE
DRWE-'

FIG.

7-9

Start/Stop Control

Block

Diagram

- 7-18
SP

—

(ro TAPE DRIVE)

of WRITING'loads the end of record counter which is preset to a
The 8 bit output from the counter gates R WRT CLK

count of 8.

The assertion

pulses from the drive to produce WRITE STROBE pulses.
of

each WRITE STROBE pulse will:

latch up write data from the controller making it available

"a.

CWRS

assert

via

drive

the

assert REC to

the

output

gates

controller

the CRC generator.

the drive and to

Vertical fiarity is produced by a parity generator which monitors

the 8 write lines and outputs a true or false parity bit according to
the number of 1 bits and whether odd or even parity 1z specified

(EPEVH).

The write logic contains a circuit to detecfi a zero~charactef

condition when even parity 1is specifged. Such a.éondition résults
a blank

the tape

which can not be

§ensed by

the

read

Should an attempt.be made to write a zero character with

even parity~the Zzero character detectoi output wouldiassert WRX3

thereby generating a 1 bit on the third write'channél. a sifiéle bit

i eb

e LbB8

Btk

logic.

space on

Caut

character demands a 1 parity bit when EPEVN is true.

The parity bit

is also artificially generated via the zero character detector output
which

asserts

The

CRC

REC

pulses

the

body

WRXP to the parity write

generator

clock
the

receives
the

each

generator

record.

channel.

data

character

which

develops

from
the

the

write

channels.

CRC character

during

7.4.1.2

UWrite

When

the

data

The

WRT

last

data

WRT

End

Record

transfer
CLX

pulse

character,

has

been

completed

produces

nd
a

issues

resets

the

WRITE
a

CWRS

the

controller

STRORE
pulse

which

and

When

WRITING

negates:

CWRS pulses to the controller are inhibited

REC pulses’tc the drive are inhibited

the end of record counter is enabled

WRITE

STROBE

pulses

clock

the

end

record

counter.

When

switches

the

b."
The
&

REC

write

CRC

the

WRITE

STROBE

for

later

character

data/CRC

enables

pulse

STROBEs

the

onto

the

write

the

counter reaches a count of 3JCHK‘CHAR SiRB asseits and:
a&a.

thefi?g
The

‘a.

flip-flop.

pulse.

pulse

WRITING

latches

CWDR@(

REC

CLK

also

negates

lines

via

mux

REC AND

gate

pulse

latches

up
the

drive

record

counter

the

count

CRC

CRC
of

character

character.
7

and

again

enabled

LRC

STROBE

and

generates:

Three

WRITE

asserts

CHK

ifii

CHAR STRB which:

»a:

enables the REC AND gate

b.
LRC

asserts

STROBE

latch

LRC

asserts

LRC

STROBE
STRB

setting

via
to

all

the

drive and

write

chaiééter is generated in the drive).
REC to record the‘LRC character,
thereby

7.4.2
Seven

-for

inhibiting

any

further

resets

lines

the

zero.

AND

gate.

write

(The

data

LRC

Thé néxt WRITE STROBE asserts

and.résets the end of record counter

WRITE

STROBE pulges.

Seven Track Normal
track

the

normal

write

end

operation

record

is identical

sequence.

7~20

nine

seven

track

normal

except

operation

both

(;

the

and

the

bits

the~emd

record

counter

are

preset

Thus when the countexy reaches a cofint of 3 the same conditions exist
as a

count

sequence

nine

track

operation.

the last data character

three

the LRC character

reset

end

write

sequence.

Nine

7.4.3.1
fille

The

seven

track

end

recor

is:

7.4.3

blank

spaces

Track

record

File

counter

terminate

the

and‘forces

the

Mark

Write Data
mark

operation,

EWFMK is

true

mux to output all 1is on the write lines.

write

dafia/CRC

After‘the i1s are

latched up in the latch up tegister théy are applied to the output

gates.i EWFMK enables gates g, 1 and 4 thus‘outputing an octal‘23
(nine

track

file

mark)

the

drive.

\CWRE is true and CWDR is false for a CWFMK command.
SET pulse'to set the WRITING flip-flop.
WRITE

Thus

STROBE

one

CWRS

7.4.3.2

but,

WRITE

pulses

due

CWDR

STROBE

issued

are

being

returned
to

for

the

The first WRT CLK pulse assert

false,

the

CWRE allows the

resets

file

controller

mark

the

WRITING

flip-floy

character.

file

mark

operation.

Write End of Record f

The write end of recprd seqfiehce for a nine track file fiark is

identical to the write,énd'of record sequenéeAfdr nine track normal

except that the CRC character is.skipped and only the LRC character
7-21

.1s written.

The énd of record

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{F’g@ '7._?) AEMD

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FROM
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Tare

TRANSPORT

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(mc 7~ )—SET

FROM

{

Cp,

.(c,oNTROLLE(?>“4C R3S
CONTROLLER

(Reser)
|

(5) Y RXE

GENERATOR |

(5)

(C,LREC (crock),

(seT)

] ®)

‘

P writive 'r/R,T’NG'
[@\ R WRY Ctk
.l
PF
=)

wWRT CLk

”‘%(FIG T-13 ANnD '7*1‘7)

—'L(l_)/’

" 0 V\wmre STROBE
L~/

(F;@ 7—5) 7rRKk_(PRESETS 4 BIT) |
A)WRITING (LoAds countERYyd

Enp
(&(4 BIT)
(_
\EWFMK ) 0
o
BiT)
1-6)
FIC\

—————

(FIG- - C]> Move (ENABLE; COUNTER) |

)

4geir)

_STROBE (cLock) ,[RECORD
e

@ WRITE

G:‘G‘ q-é)n EWFMEK

7
S——"—

"1 CHARACTER@

CHK

CHAR

STRB

w RC STRORE

7 TE
I
EW FME

WRITE DATA/é? ol
MUX

(Swiren),

CrC

(cLoc k)

'Ic&t)%

w@i‘
:’"é
fm‘rfif
LATCH

f‘;‘@ T4 Pfi-’\{

4
e

DATA

our PUT

{fimfis PoR ?

GATES

RIEGISTER

(&)

()

» 1

PEC

‘@

Fla.

7-25

LRC

7-11

STRB

Write

Block

/To TAPE
TRANSPORT

Diagranm

counter

must

reach

point

the

same

this

mode;

thus

the

terminated.

LRC

The

count

before

conditions

character

nine

track

exist

CHKXK

recorded

file

mark

and

end

CHR

the

the last dafia characte;{th@ file na rk

seven‘filank spaces

the

reset end of record‘counter to terminate
the

7.4.4

nine

write

record

a&.

LRC

STRB

asserted.

track

normal

sequence

seguence

1is

ig:.

characteyg)

character

write

sequence

Seven'Tfack

File

Mark

" The write data sequence for the seven track file mark is
identical
to

that

for

the

output

the

nine

gates

track

via
-

outputting

~The

end

that

for

7.5,

octal

record
a

file

the

gates

(seven

sequence

seven

enabled

Output

track

mark

for

except

EWFMK

now

file

the

seven

7TRK

asserted

gate.

enabled

track

normal

that

are

markto
)

track

the

file

2 -and

thus

drive.

mark

ddentical

sequence.

Read Sequence

7;5.1

Read Data (Figures 7—12'and 7-13)

RSDO pulses -from the drive assert COMP RD STRB thch:

clocks the read data latch up register

"b.

triggers the read‘strobe one~shot'asserting CRDS to
the controller

uses

(CHECK

second

REG

flip-flop

|
output

PLS)
in

the

from

clock
end

the

read

LRC

record

paragraphv7.5.4).
|

‘

7-26

strobe

generator
detection

one-shot

(and

the

sequence,

LRCS

(

When the read data latch up regisfiér is clocked by COMP.RD
read data is made available to the controller
via the read data
output mux.

VWhen READING is true the mux selects the data chavacter

When READING 1s false {(not

from the read.lines for the cpntroller.

during a no%mal dafia transfer) the LRC‘characfier is output to éhe
purposes.

r maintenance
for
controlle

Error Detection

7.5.2

Read data ERD@-ERD7,

7-12

(Figures

and 7-13)

ERDP is checked for CRC,

LRC and vertical

parity errors.
Each data character is clocked into the CRC and
At the end of the
LRC generators by the CHECK REG PLS.
racord the CRC character is elocked into the CHC generatox

causing the CRB-CRT7, CRP @ufiput‘fia bae all zeros.

The CRC

error detector l@@ka»fmy afli&il zaros charactexr from the
CRC genarxatoxr at CRCS time. if.th@ CRC generatorx éutput
is fiét all zerocs %h@n CR{S8 is true, CCRCE i3 agsserted
to

the

controller

a similar

manner,

indicatling

the

LRC

CRC ezror.

character

LEBC generator ca@@iag the LRS=-LR7,
detector

looks

LRCS time.
is

true,

for

all

zero

clocked

into

LRP output to be
character

from

the

all zeres.The LRC erro

the

LRC

generator

If the LRC generator output is not all zeros when LRCS

CLRCE

is asserted

the

controller

indicating

LRC

error.

CRC and LRC error outputs are enabled only when the drive is executing a forward motion command.

(This

the

end

EFOR

CRC

and

must

LRC

characters

true

for

CCRCE

at
or

the

CLRCE

of
to

is due to the
the

record.)

assert.

location of
Accordingly

(Fic 7—-8)
-

€7

[RRsvO |
| COMP RD STRE|

|[ERDB-ERDY, ERDP]

ICHECK REG PLS|

[CLOCKS LRC GENERATOR]

Each

data

character

occurring

during

the

body

record

checked

for vertical parity exror by a vertical parity error detector circuitfi
If

parity

error

sensed

controller.

CVPE

inhibited

vertical

parity

check

made

the

detector

during
on

the

CRCS
CRC

CVPE
and

and

LRCS

LRC

asserted

times

thfif@

cha &BeTErS.
<=

7.5.3 File Mark Detecticfi (Figureé 7-12 and 7@13)
The

file mark detection logic monitors

the read data and outputs

CFMK to the controller if a £ilé mark is deteéted.

Three conditions

must be met befor
the record
e is idemtified as a file mark.

These

are:

d.. there must be two characters and only'two chaiacteis

to the record

both characters must be file mark éhafactérs

the

second file mark character must be.followedAby éight

"blank

spaces

To meef cofidition b, réaddata(ERDfi~ERD7, ERDP) is examined by the

file‘mark character detector which outputs FMK CHR if a file-Eafifi

- character 1is sehsed.

A filé'markAcharadfer-flip-flopis:set‘by the

SET pulse at the start of the'operafion‘aha then clocked bf RRSDO |
pulses. The flip—flop is conditioned to set by FMK CHR, via an
AND gate, such that if the flip—flbp‘is clockéd to the“reset state
it cannot be set again dfiring the current opératibn.

Thus the first

two characters read must be file mérk,charactefs in order to keep the
~file

mark

character

flip-flop

set.

. 7-28

Mo,

SWITCHES

LRCG-LRCT

LRCP ONTO

CRDB~CRDT, CRDP

(TAPE CHARACTER)

ET3~5

(FHMK CHR FF)

READ OVUTFUYT
LIMES

CRDE — CRDY CRDP

(LRC GENERATOR
GUTPUT
!

FOR

MAINTENANCE USE)

DISABLES

MARK
)

ERTICLEN_

PARITY

|4 R WRT CLK|

ERRO

YES

eereE]

|2 CouNT|

lcvPE|

[91{‘& FriE]
.

[BE'COR D ACTIVE|

Fle,

7-12

Read Flow Diagram

GAP

DETECTOR

(Fic 7-18)

|
(v
\GB;

)

...’>
VERTICAL 2 E-PEVNI A (FIG 76
ERROR
PARITY
DETECTOR]

+ CVPE

(

;

}Cflc7-1%)
e
C(

(7)

CRES_ (Fre 7-19)

-,
o @O
oéfi-%%o& LRE-CRT, CRP] CRC
EFOR (Fi¢

;

Error

|ebRE=LRT LRP

| pETECTOR

~
S

.5*%&.3; QFIC- '7“1‘?)

(7)

GEMERA?‘OR

(%)

keserd | AEMD (g9~ 9)
]

LRC

GENER ATOR

CHECK A

- ) L=(cLock) fiFCr pLS{2

Q
-k

(.,,

<CRDP-CRDT CRDP[READ |« LRCE-LRCT, LRCP
‘
DATA
OUT PUT (<

pMUY

< CRDS

f—EI-‘-(FIG '7-(:)

FILE MARK la
PETECTOR |, 7TRK

‘

FILE MARK Dfe

‘

m [

i (RESET)
|

(Fie 7-t)

CHARACTER

L CFMK

)

(8 BLANK SPACES

FILE

—

MARK
[

GAP

(ENABLE)

< (CLEAR)

PETECTOR

R WRT CLK @w_ ,7_“)

(F'G V‘H>
7-31

RECORD ACT \VE /@’

LT
|

KEDT

by —

;

ROP~RDI7Z

RDP

Rsbo

RRSD@@

ST T
llelouc) coppP R0 sTRE

(FIG 7-19) e
é;“; ?”g%ézHfiCk REG_PLS

/éflA.

}

“2

TR0
"

MRDE-MRDY,_MEDP.

CARTIFICIAL
READ STROBE)

()|

Mol

RSDO

READ
STROEBE
0.5,

(4)
FROM

HOST

(Fic ’7-1?){““"_“4

TRANS PO

£R SpoO
D = 2)__ READ . STRo‘ fiEfi_(c

_ (Rspo>2Y

COUNTER

Lock)

RESETY

FIOVE (g 7_9)

FIG,

7-13

Read

7-32

Block

Diagram

Conditions
a

read

& &and

strobe

of two the
R

WRT

are met

counter.

by means

When

the

read

file mark gap detector is

file

strobe

.
three,

the

gap

BLANK

nablaed

the gap

the

detector

ARRD

counter

reachkes

P
RSELI2

SPACES

gap detector

and

reachss

CFHK

asserted

gate.

1g
a

count

third

detector reaches

eight;

the

ocutputs

controller

pulse

the

ovcecurs

detector

and
count

counting

count

,
detector.

gap

eight

R3DO

reaches

enabled and starts

CLE pulses

mark

B8
via

before

cleared

and

the

file

‘mark character flip~flop is reset indicating that the recoxd is not
a

file mark

and

a ncrmal

record

transfer

PRrograss.,.

The end of record detection sequence is enabled from the read data
channels

via

record

is iniprogress

active

OR gate.

normal

record

transfer

(RSDO>2 is true) or a file mark has been detected

(FMK true), RECORD ACTIVE is asserted and enables
(bet does rot @%&r%} the end of record detection seguence.

7.5.4

End of.Record Detection (Figures 7-18 and 7-19)

7.5.4.1

Nine track Normal (Figure 7-14)

The ehd of a record is detected by looking for the three blank spaces

that occur between the last data charactei and the CRC character (LRC
character for sevén track).

The blank spaces are deteqted by afi efid

of record counter which is.clocked by R WRT CLK Pulses and effectively
reset by COMP RD STRB pulses.

(Actualiy the COMP RD STRB pulses load

7-33

—_

Ve
VU

VDD

TUPRV DU

e
r e

gt
e

g
dme
e

count of

RSDO pulses from the drive.

8.}

COMP

RD STRB pulses

ave

asserted by

The R WRT CLK pulses and the RSDO pulses [
)

counter with a

the

are not necessarily in sync but they are of the

Hence

same freguency.

the end of record counter is continually being ciockefl and
during

the

bedy

recopd.

Two

WRT

CLRK pulses

might

sgqueeze in batwaen twé RELO pulses thereby clocking the

counter to a count o0f two befoxe it 4is raset, éufi it should
fevay reach & count highéz than ¢two dugring the b@é% of @.éé@@z@&
If the counter does reach a count of three (three RWRT CLK pulses
3 COUNT'is asserted signifying that this

with no RSDO pulse)

is the end of the record and the end of record sequence is started.

The assertion of 3 COUET clocks the CRCS flip-flop set outputting
CCRCS to the controller indicating that the next character will be

the CRC character.~}The next RSDO pulse will be the CRC character
"strobe which will:

the CRC character in the read data latch up register

latch up

“reset"

assert CRDS

assert CHECK REG PLS which clocks the LRCS flip-flop set

the

end of

the

record

counter

controller

The asserted output of the LRCS flip-flop will reset the CRCS flip"flop and assert CLRCS to the controller indicating that the next

character will be the LRC character.

the LRC character strobe which will:

The next RSDO pluse will be

a. latch up the LRC éharacter in the read‘data latch up'regigter
b. "resetTM the end of record counter
|
|
o
C. assert‘CRDS to the controller
d.

assert CHECK REG PLS which resets the LRCS flip-flop
7-34

negation

LRCS

sets

the

locks

the

CRCS

end

record

flip~-flop

asserting

the

state

END

f/—‘\

The
OF

RECORD

the

which

flip-=flep

reset

until

operation.

when END OF RECORD asserts

decision delay period begins.

The

decision delay period is a time interval (normally 8 R WRT CLK
pulses long)

between the assertion of END OF RECORD and the assertion

of RD CLR PLS.

The’deIAy period is & "last chance" look for more RSDO

7-35

Covwter

Jf’“’“g

RESL

gg,

R VW& CLic ]

as Ai‘m’ C%W&'

cRC cl

Lov
LOADS

Rspo |
Comf

QD mfl

LAT |

CoOUNTER

[

STRB

CRCS

(END 6F Eécom\)

®0 ClR PLS

7-36

| J7fi

;flcg

T MiTO ¢

DECISIEN DE

" BRI

O iy

;:1

qoin

3 ! {

h
Ayt

‘~?

SOV
N

2dog

[

(1
C

*LODS {

[

2103

3 SRS Slelef
-

.563sb

9 Fiqw

.-IA

Styy

q J9 616D
-4

< T

_ku

bhao

r. N

r—~

Oad
L -’1

[UINL

« O 1 _!: JoD

[}
-~

‘~—L

930U

gars e

ard

9 Q3
?

Dfiijiffi

Y I

ofrr

imin
RgcordrT
)
P’ SRR T R
ing ~Non-Zerxro
e

CRC,agd:LRC

DV L P

[

"Foe
o¥

gt
<

SATL 3

oAda

OxXacx

————

o DLnw

bas

Pas

—

————

——

~
-t

o3< L
.

L3
JELTL

£y Joe s rf 2

—_

YsdonsasdD

g02

IRt

A, v LS

A
[y

—rry

eemt

ey
e o

pulses

kefore

triqggering

the

drive

thcchisron d>lay . the.end
‘

Vit

stop

record

T&Jm,rj Te
Y

sequence.

counter

"reset"

the

start

(preo@t

(

o
sW ANKN
ey
, Vhon%the
countindK [ URTi CLX, fi;lée
j
and SLdTr
a>¢ouri/of"é§
to
i? - “
/
/g
¢ et
i

- m."'*“v w(/

‘

pemt?

o
R S T

reaches

counter

which

G
S
I
2
LJ.

counter

REDO

aRCe

count

PRSP A

t@ephas%erLs

pulses

end of
will

G2
=

od the

]

bg
]

“mey O

f““""*"‘"""T e b et i T

overflows

CLR

PLS

I—

_—

L i
P
S

into

the

drive

decision

stop

delay

logic.

Sh uld

——

SA 5

re-occur

anytlme

during

record counter will be

the

(}‘3’}’\3'
‘\

decision
i

set"and

delay

the

read

"h\ nfoz30’ BT \}S?o*1”‘

contlnfiemww0henwfihe~actuai”@nd of~record
)

does—occur—-

the decision delay count“WIil*startWPgamfl but—the—end—of—record———— _

sequence

will

not

repeate

]

[ -

?he

end

progress
e

(WRITING

true).

1is

1nh1b1ted

During

wrlte

et edian o

write

operation

Operatlon

defective

spots

s gy FJ—~—

the

tape

may

simulate

record sequence.
.

ket ] e
PRy

still

w1th

the

trying
R

VRT

gap

and

erroneously

In this case

functioning

.(-»"'

P. s

seguence

B R

record

trigger

the

end

the end of record logic 1is

stop

write

data.

CLK

pulses

into

the

fih

drive

prevent
end

whrlfiwjhe“g_ntroller

this

WRITING

record

counter

gated

thereby

al%owing

counter

to operate

only

if WRITING is

false.

PSS
T

the

7.5. 4 2

TM~

o
S

Zefip CRC or LRC Characters

aaaae
20T SN

It is possible that the CRC or the LRC character C0fild bé aizero éhargéter
resulting in no corresponding RSDO pulse being received from the drivé.
In %flish%ésgza Cbfi%"fibqsfifiéflfialEECESfigz %a%ed artifi@idlly so clocking

of thé end of record
received

"reset"

sequence can
the

end

continue.

record

counter

If no RSDO pulse 1is
counting

will

continue

up to six at which time COMP RD STRB will be assertéd via a gate_

enabled by CRCS or LRCS.
the

timing

sequence

for

Figures 7-15 and 7-16 illustrate réspecti#ely
a

zero

CRC

VE--T

7-38

and

zero

LRC

character.

-~ >

R S itk

NET

SUGTELD

: L,

!% Mh

T
!
N
i

‘

y o
4;4“

CumMp

RD STRBE-

LRCS

JETIRp—

‘a-’w?tsvtm\i“n.“

END o%

(

=
1

TM~
L

PELORD 4

eNy
P

CLR

PLS

g
[

g w AT st

- I

WAL

R W

L St 7 e

—~

e &

BB e

iv ro

_fl,}yl;xw.—

7-39

~at e

A+ S

e P

\
. el
S o
R

e
5{

”:_“

i
;

%..,fl:.fl,,-w:‘

)

l‘:rv

‘l

/ &

b
e eot A

e AP

e reeam
s

4“'%

/ %

poné

STE

DMJM»

PO VP Al b

PTA

‘

LAY

‘l

)

J'f

5‘

f’.i

o
e

2
e

,
s

Q{f

‘:@
T

ffl,z};é;% DECISION

i,‘v.;"v" ¥y, Q

—?

Y SURTN
< S B IR VA S

e it
Y
Tt

COUNMNTER

)

5
S

RS
e RC

‘3

T
te

PEC

j b

"r'M‘mfi'I‘”‘~

e N
A

—

L AT
.

e e e
e s

J——
S

A
e —

Rt et
et =
vt

s oo

PR by Ad PP

.
}

p————.
va——

)

w2
W

§ v
-

“

“7
t“
R

VU Sy

Ptk

N
e
ey
s

F? . 7-15

End of Record Timing, Zero CRC

7-40

itk K ST7<
5

fifi'\‘;

@;@@ié%” é%f%’é, C’%\év%ater
feSDO_

Liy

TRECS

zéwaoFfigwfié>

—

PLS

7-41

HiL1

[ohns | ior
COUNTER

(

R Wil |

€

,,,,,,,

DELAYLA

)

oD Ects oy

Aafw#fihv»

or STRO =

F'IG-,

7-16

End of Record Timing,

. L

7-42

Zero LRC

is normally eight R WRT CLK pulses

The decision delay

long but is extended to 24 pulses if nmo LRC character is detected.
Failure to detect an LRC character may be due to the characterx

being zero but it could also be due to a bad area 1in the tapes

Phes when no LRC character is detected some doubt exists
the end of the record has been ryeachaed.
Extending the decision distance to 24 pulses pr@vides‘

The

extra assurance that the end 6f the record has been reached.

decision delay counter is a count down counter whigh is loaded by

each RSDO pulse. The counterxr is loaded with zeros except for.éhe
i bit which is loaded with LRCS.

If‘thefe is an LRC character

then LRCS is true dfiring the last RSDO pulse (Figure 7-14) and the

counter is loaded with‘;ll Zeros. If tfiere‘is no LRC character
vthen LRCS is false during the last RSDO pulsé (Figure7-16) and the
delay counter is loaded with a

In this case the end of record

counter must count an additional 16 pulses to count down the 1 and
assert

CLR

PLS.

7.5.4.3 Seven Track and File Mark (Figure 7-17)

In seven track or file mark operation the end df recbrd sequence 1is
modified to eliminéte the CRC character from thé sequehce.‘ With

either fMK or 7TRK true the 3 count 6utput from the énd of recorad
counter directly

sets

the

LRCS

flip—flop which in

turn

holds

the

CRCS flip-flop IESet; Also, when in filebma;k operétion, the decisi<
delay is
extand@d to 24 R WRT CLK pulseé.as there is no
RSDO pulse

7.6

Drive

associated

Stop

with

(Figures

the

7-7,

assertion

7-9

and

LRCS.

7-20).

RD CLR PLS triggers the drive stop sequence by setting the EMD
flip-flop

and

asserting

EMD

the

drive.

The

output

the

EMD

IUT—

—

- sHyt

0y Y10 sad
Y
SIS

151394

4gyd34siul.\elm.w..?a .2@3&1 ARE
S

H—to AND

-J
F

s I
]

READING Aj}if_:;mm

[t R WRT dk]
'

INCREMENTS END OF|
COUNTER

RECORD

|4 R_WRT clg]
Y

'HQEEMENTS

END

COUNTER

RECORD

PRESET DECISION
COUNTER

DELAY

T R WRT CLK

COMP RD STRB]

INCREMENTS END OF

CRDS

——

RECORD

COUNTER

RESETS END OF
.

RECORD COUNTE

3 COUNT

l
7-45

dili

¥
\4

LRCS

PRESET DECISION

DELAY CCUNTER To4

[4 R WRT CLK]

L COUNT

7-46

(

e tt
4

[COMP RD STREB
¥

[CHECK REG PLS]

RECETS END OF|

RECORD COUNTER

[LRCS]
[l cres]

ICLRCS]|

T e

PRESET DECISION

H;R

PELAY COUNTER TO 0

|
!
|

[coMP RD STRB]
A

Y
o

ICRD

RESETS END COF

RECORD COUNTER

‘

[CHECK REG_PLS|
I

[¥ LrCS]

|
[{ CLRCS]|

[END oF RECORD|
[

7-47

[¢ CounT]

ICOMP RP STRB
2ES

CCHARACTERrs
jig*%

Z 0

“RECORD)
“1s A FILE N

YE.S

RESETS

END OF

RECORD

COUNTER

(Fie 7-20

.FFG,7-18

7-48

End of Record Flow Diagram

(gRTWHCtAL

’

FIG T~ |3 )2

(@)

READ STROBE )

Q
~

CONTROLLER
_CLRCS

‘/(‘fi
SET)

® S END

OF RECO!

RECORD,

@ESEK
T)
|

res U®

|
|

(ZR ‘; ¢

REsem)

13)
clieck MOVRe E UL((FFIiGc r]7-.-q) ‘

LS
EGcPk
|CitRE

(zic 19}
v

RESETS —+ 4
COUNTER

1= EMD FE|

LOADE

[4OT 0N

DPELAY

COUNTER

[1— BIT

]

[EMD]

I3]

1=+ BIT

14]

i— BIT

[ READING|

|2 clocK puLses]|
v

[1— E 889
INCREMENT
DELAY

MOTION

COUNTER

BiT 13

= @

YES

[2 clock PULSES]

[§— Egg—7]

cz..ock: puLsesN, NO
RECEIVED

\'d

YES

[#— EMD FF
l{ EMD|

<
v

[2 clock PULSES |

INRIBITS MOTION

D— BIT 14|

DELAY COUNTER

ACCL-

{ MOVE

[S_TOFT[

Fie
Drive

DONE
7-52

7-20

Stop Flow Diag.ram

(
.

Saldl..

ri iy flop also loads the motion delay counter with data set onto
is
il lines RD@-RD5, RDP by the drive. Pit 13 of the counter

o
s

genelt tooa 1.

The bit 14 output, which has been a 7 all during

{ Iy record transfer, is connected to the data input of bits 54 and

)

Thus when EfiD loads the counfier; outfiut bits 13, 14 and 15

foine 18 READING negates due to exclusive ORing of output bits~

14 and 15 while bit 13 gates clock pulses into +he counter from the

. i counter. The = 4 counter receives CLOCK pulses ffem the slave bus.
A nutput from the = 4 counterisvobtained after the firsf two

(G pulses and'every four CLOCK pulseéthereafter. LAfter 8.9 ms
s motion delay counter 1is clgcked reset and:A. input clock pulses to the delay countexr are inhibited
(bit

13=0)

ACCL is asserted to the drive
CLK pulses

(bit 14=@) and inhibits WRT

from the drive.

Wi assertion of ACCL resets the MOVE flip-flop which negates
M(VE and asserts STOP to the drive thereby terminating the command
@p@ration.

daiig

r»«-«»w{fl/f LRCS @
DECISION |,
{E .
DELAY

CounTERA—=Ch b
|= (ENARLE)
@)

__CRCS

CRCS PP

2 COUNT)

(&6 counT)

lEND

RD R
CONTE
COU
(’3 COL!HT) RE
(4
A )

@)
A c}=
_T(RESET)‘ |

‘&_CENAELE)

RESEY)

Fl G

7-19

End of

RESCRD ACTIVE. (Fic- 7-/3)

T
I NG
WRA
.
WRI Clk ?(F!G- r7m/,>
%R

CoMP RD

(FiGop-9)
DIN.G 7_13)
REA(Fnc

STRR

Record Block Diagram'

- CHAPTER

TU1T0W

8.1

Transport;

Theory

QOpevration

(TU16/TUT0W

differences)

General

i:n many areas

the

TUT0W tape

transport

identical

the

TU16.

Hence the reader is féferred to the theory of operafiion, Chapter 2
of

the

TU16/THMP2

tape

drive

system

maintenance

manual

(document

No; EX-TU16~-MM~-002) for a functional description
of the TU1I0W.
The

reader

detailed

also

referred

discussions

the

Chapter

functional

the

same

areas

the

manual

forx

transport.

-The paragraphé that‘follow are concerned with the differences between
the TU10W and the TU16.

They provide a supplémefit to the TU16/THO2

manual such that this manualAtogether with thé TU16/TMO02 manuél will
provide full coverage of the TU10W tape drive transpo#t.

Paragraphs

8.2 thréugh 8.5 cover the differences between the TUTOW and TU16
transports.

Paragraph‘8,6‘is an erratta.for the TU16/TMZS2 manual.

It lists errors that were discovered in the'TU16‘manualvand are being
_correcfed, but will likely still be in the copy used by'the reader Of.
this preliminary manual.

8.2

Delete

TMH2

The TU1@W does not contain the TM@2 tape controller.
descriptive

8.3

Add

The

M8926

theory

M8926

Interface

interface

installed

M8913

M9001-YA

and

that

the

pertains

the

TM@2

Chapter

tape

Delétévall

controller.

Module

module

(covered

system unit
modules.

of
(See

the master drive,
Figure

- 8-1

2-14.)

this

manual)

replacing

the

M9001,

g.4

The

Replace

TU16

capability.

extra power

Volt

reqguired

a maximum

rated

Regulator

regulator was
.

current

had

vredesigned

to provide
o

The

new regulatcocr

for

the MB89Y926 module.

current output

82.058

4.8

(Figure

The

greater
b Q%

output

8-1/ supplies

Formerly
new

the

(

the

+5V regulator

regulator

current

output

maximum.

To incorporat@~the new +5V reg@latpf, make the foilawing changes to
the information in the TU16/TMH2 manuale}
a.

Delete paragraph 3.15.2 and substitute the/foliowing:
3.15.2

‘+5VDC Regulator circuit

The +5Vdc regulator circuit is shown in Figure 3.715=3. Raw
<dc,volfage i8 input to pins
11 and i2.of’the 723 voltage
regulator.

The

output

voltage

from

fed

trans-

(

istors Q6 and QS,‘which are series regulators used to increase
~the

current

output

capabilities

the

circuit.

_.Resistors

R62 through R66 inclusive sense the output current.

used as a current limit monitor by'the 723.

R62 is

As the current

increases, the voltage across R62 ificreaseé. 4Wheh the refaxenes
voltagé 1s exceeded, the 723 begins'td turh off 06 and Q5, im=
'peding current flow. The current does not siofi, but instead
decreases toa safei level; this is called cufrefit foldbéck. It sssures
that the outpft current never goés over 8.0 A,

Refer to

Figure 3.15-4 which shows how the current foidbaék procedure
works. As the current surpasses the limit of 8.0 A, the con;

| duction of Q5 and Q6 slows down (téward being shut off£) until
no voltage is produced

(at‘the short circuit current rating).

The

output

divide

the

voltage

actual

may

output

regulated.

voltage.

8-2

Resistors

R58,

R59

and

(\
R60

..)W ¥ ,V

o & |

| 4 ot

o oyt ol

ADT

L] - )

. bVi .

!2.@ y 3% g:
%. tY. 9e B .oi3. .&

)‘".*Lua"..-.1X“.itsMyw<aywS¥kNamkndIwRatyvt LTV2ATESI .. [.0n¥:
L:

8.4

Replace

The

TU16G

current

Reqgulator

regulator

capability.

extra

power

had

maximum

Veolt

is rated at

required

was

redesigned

The

new regulator

for

the

M8926

current

output

B.0a

A NLMUIM .

provide

(Figure

module.

4.8

greater

The

output

8m1§supplieg

Formerly

new

(

the

+5V

regulator

the

§ §

regulatcy

current

output

TO incapofate‘thé new +5V regfilatei; make the following changes to
the information in the TU1I6/TM@2 mamualej
a.

Delete

3.15.2

paragraph

3.15.2

and

substitute

the

following:

+5VDC Reéulatar circuit

The +5Vdc

regulator

circuit

shown

in Figure

3.15=3.

Raw

. dc valéage i8 input to pins 11 and 12’of the 723 voitage
requlator;

The output voltage from.pin 10 is fed to trans-

istors Q6 and 05, thch are series regulators used to increase
the. current
~R62

through

ocutput
R66

capabilities

inclusive

sense

the

circuit.

ocutput

(

_.Resgistors

current.- RE2

used as a current limit monitor by‘the 723.

As thé current

increases, the voltage across R62 ificreaseé.

Wheh the refexenee

Voltaqé is exceeded,‘the.723 begins to turnoff‘QB and Q5, im=

‘peding current flow.

The currenfi does not sfiob, but instead

decreases to
a safer level; this is called currefit foldback.

It sSsures

thafi the output current never goeé over 8.0 A, ‘Refer to
Figure 3.15-4 which shows how the current'foidbaék procedure
works.A

the

current

surpasses

the

limit

of 8.0

the

con;

dfiétion of Q5 and Q6 slows down (tofiard being shut of$#) finfiil
no voltage is produced

(at‘the short circuit currenfi tatia@)-

The

output

divide

the

voltage

actual

may

output

regulated.

voltage.

8-2

Resistors

R58,

R59

and

(
RE6E0

CHAPTER

TU10W Transport;

Theory

of Operation

(TU16/TU1T0W differences)

Tty

General

8. 1

many

areas

the

TU10W

tape

transport

identical

the

TU16.

Hence the feadef is referred to the theory of operation, Chapter 2
of

the

‘No.

TU16/TMEZ2

tape

EK-TU16-MM-002)

drive

system

maintenance

manual

(document

for a functional description
of the TU1I0W.

The readexr is also referred to Chépter 3 of the same manual for
detailed discussions of the

' The paragraphs that

functional

areas of the transport.

follow are concerned with the differences between

the TU10W and the TU16.

They provide a supplément to the TU16/THM02

manual such that this manual together with thé TU16/TMO2 manuél will
provide full coverage of the TUI0W tape drive'trangpoft,

Paragraphs

8.2 thréugh 8.5 cover the differences between the.TU10Wand TU16
transports.

Paragraph

8.6

erratta

for

the

TU16/TMS2

manual.

It lists errors that were discovered in the TU16 manual and are being
corrected,
this

will

preliminary

8.2
The

but

likely,stili

the

copy used

by the

reader
of

manual.

Delete TMP2
TU1PW

does

descriptive

8.3

Add

-The

M8926

installed
M8913

not

theory

M8926

contain the

that pertains

Interface

interface

in the

TM@2
to

tape

controller.

the

TM@2

Chapter

tape

Delete all

controller.

Module

module

(covered

system unit of

and M9001-YA modules.

(See

the master drive,
Figure

this

manual)

replacing the M9001,

2-14.)

8-1

year

A
m

mev

mence}

d g

T\ FEE R e

“

. o) |

N’

40 W wo”fim‘_& .

LN ocd
~

— T

IV O\ P

rin

the

adjustment

the

addition

crowbayr

for

723
of

R59

the

cixcuit

some

accepts

the

regulates

current

used,

reaSOmAQS

output

feedback

the

+5V

feoldback

offering

or Q6 become

. protection circuit pzeté@ts

voltage

through

RE@

output.

feature,

overvoltage

shorted,

the

voltage

protection.

overvoltage

any load connected to the power

gupplyGJHWhefi.QS'éélQfi short @ixcuiéss the output voltage

fitarts'inCKeaSingjfiéryzépidlyé’ As the voltage across the D16
zenexr ciode becames'gréafier thean 6.8V,

it breaks down and begins

conducting;

normal

beqing
D16

gate
a

path

thus

and

flow

R22

D?S);
for

does

not

through

becomes

the

R22.

fires

from

it.

dufing
When

greater

SCR

current

protecting

conduct

and

the

The

fihan

output

Delete

Figure

Table

3. 15 2

column from:
d.
£from

Table

R1€é

3.15-3

change

Subctltuue

the

b arpge

the

flrst

¢5¥

0.7V

con&ucthg.
ground,

the

conducting

]anctia

{(at

This

shunting

Current

the

offers

any

load,

until the

%3 [A fuse is blown.
Flgure

1tem in

"5A maxmmum“rto A

3.15%5-3

SCR continues

and

vcltage

apprQXLm&tely

beglns

,pcwéz supply is turned off'ér the
L,

the

operation.

‘now

the

"Specification”

maximunm”

adimctment

potintiom

RS59.

In Table 3.15-4;

replace the second and third items

("+5V

low"

output

too

+5V

output

723

too

low

Ré4,

and

+5V ¢teeo high
|

Y"+5V

too

high")

the

following:

R5%

open

bad

shorted

R65,

R66,

D16

open

R59

8-4

with

R60

open

R33,

Table

3.15-3;

"Wire

Coloer

TU16

Code"

Power

Supply

column

Regulated

given

as:

Voltages:

the

RED

’

YEL

GRN
ORN
ORN

The

second

column

and

should

third

read:

items

should

switched.

RED
GRN
YEL

ORN

Figure 2~2;

the ninth signal line down has the foli
owing

mnemonic:
The
d.

signal

Figure

mnemoniec

2-2;

mnemonic:

The

SLAVE

signal

the
EOT

SET PLS
should

21st

be:

signal

line

DRV
down

SET
has

PLS

the

mnemonic

should

be:

END

following

Table

and

fuse

3.15-5;
F12

change

type

In Pigure 3.15-1

from

fuse
"5A"

F4
to

type

from

"5A"

"10A",

"15A",

change the +5 veolt adjustment from

R16 to REY and relocate 1¢ ag

shown in figure B-1.

Alaso note the addition of Q6 to the power transistor
heat

sink.

Change other areas in the TU16 manual, as reqfiired, that

pertain to the +5V regulator.
8.5

»Aadd

Logic

Assembly

Fan

A fan has been added on top of the logiclaséembly to supply aa&itional
The fan and

Coclihg fgr the new +5V régulator and the M8926 module.
associated wiring

8.6

are

shown

Figure

8-1.

TU16/TM@P2 Errata

Exrrors found in the TU16/TMJ2 maintenance mafiual are listed in this
pafagraph° These are“fiot TUTO0W/TU16 differences but errors in the

TU?S/TM@Z manual that are applicable to both fifie TU16 and thé TU10W., *
|
a. In Eigure 3.15-1; TU16 Power Suppiy Regulator Board:
|
|
R44 is designated as (—-64)
R44 should be designated as (-6.4).

These
of

the

errors

are

TU16/THM@P2

being

corrected

maintenance

and

manual.

- 8-6

will

not

aprear
in

the

e
R eeB e R N R S e

e B

R PL

e bl i D

R S

MAGNETIC TAPE FUND

MAGNETIC TAPE FUNDAMENTALS - DEFINITIONS

Reference Edge — The edge of the tape as defined by Figure A-1. For tape loaded on a tape
,

transport, the reference edge is toward the observer.

REFERENCE

EDGE
P

TAPE

LEADER

€

]

4
Tk
4

N\
3

OXIDE
SURFACE

2
5
5

1%
i

SUPPLY

REEL

10-1265

Figure A-1

Reference Edge of Tape

) BOT (Beginning-of-Tape) Marker — A reflective strip placed on the nonoxide side of tHe
.

tape, against the reference edge, 15 ft, £1 ft (457 cm, £30.5 cm) from the beginning of the
tape.

‘

3. EOT (End-of-Tape) Marker - A reflective strip placed on the nonoxide side of the tape,
against the nonreference edge, 25 to 30 ft (762 to 914 cm) from the trailing edge of the tape.

4, 9-Chafinel Recording - Eight tracks of data plus one track of vertical parity. Figure A-2
shows the relationship between track and bit weight for a 9-channel transport.*

*When the track vs bit channel standard was adopted, the outer tracks were more susceptible to bit dropping
errors. Consequently, channels containing the least 1s were assigned the outer locations on the tape.

A-l

%:fi
s
1

$.2.2

£h e dae

Chaneel
7

'fl.‘

Tape

7‘4

A RT

Foomna
UL

The format (Figure A-4) 1s composed of from 18 to 2048 nine-bit characters spaced 1 /800 in. (3 mm)
apart. followed by 3 character spaces, a CRC character, 3 more spaces and an LRC
character. This

utit of data 15 called 4 record. At 800 characlers per inch, the record is between 1/32 in. (79 mm)
mninvnm and S on, (12,7 ¢m) maximum, Between each record is a gap of at least 1/2 in.t The tape
ucture consists of a number of records followed by a file mark (Figure A-3). Since

data is recorded

and read at high speed, IRGs are used to provide space for starting and stopping a tape transport. A
transport accelerates from standstill (o full speed in approximately 0.2 in. (0.5 cm) of tape and
decelerates from full speed { to standstill in 0.2 in. (0.5 cm) of tape; thus, the minimum IRG of 0.51n.(1.27
cm)
I
provides adequate
space for starting and stopping the tape transport.
‘

LRC 0.005"* 10% (NOTE 3)
CRC 0.005"
2 10%

—&| |« 800 CPI
0.00125"

. INTERBLOCK GAP
.
0.50 MIN

REFERENCE EDGE

(FRONT FLANGE
' OF REEL)
|

\grg‘g {mécx

(NOTE 2)

TM [Fte MIN USASCII CHTM|
{

>lll!ll

(

END

|_2048 MAX USASCII

TAPE

,,lm::;

“

—

HHH.H}HHH-(

—t

HHHHHH‘TH7

LAl

(0 R

S5 A0 0

SIDE
OF TAPE

——PARITY (0ODD)
BEGINING
OF

4182y oty

TAPE

[

INITIAL GAP
(NOTE. 2)

TAPE MOTION
:

LEGEND:

NONOXIDE (SHINY)

——t :s:u::m:swj

END POINT
STRIP ON NONOQXIDE
(SHINY) SIDE OF
TAPE
-

)

LHHH

POINT

B9 MARKE
-y Gy
R_

%HHHHH%H'rwl

g,uwml
e Bk

LOAD

gumz

~~~~~~~~~~ BEG'N[NGOF

ARSI

)

11111l1|11111117

Pmm

uuuuuuuuuu

B Pl

* 39,

>
|

NOTES:

‘Tape Bits par Inch

BE-0500

1. Tape is shown with oxide side up. read/write head on same side as

BOT

Beginning of Tape

LRC

Longitudinal Redundancy Check

CRC

Cyclic Redundancy Check

oxide. Tape is shown representing 1 bits in all NRZI recording; 1

bit produced by reversal

each direction.

of flux polarity, tape fully saturated in

2. Tape to be fully saturated in the erased direction in the interrecord
gap and the initial gap.

3. An LRC bit is written in any track if the longitudinal count in that
track is odd. Character parity is ignored in the LRC character.
4. CRC - Parity of CRC character is odd if an even number
of data

characters are written, and even if an odd number of characters

are written.

Figure A-4

Tape Recording Format

*USASCII program standards, not a hardware limit.

10.5 in. (1.27 cm) minimum; 0.6 in. (1.5 ¢m) nominal.

A-4

The data characters are recordedin blocks of characters termed records (Fxgm@ A- 3). Each record

contains a %pecmd number of characters ddermmce by the word count. The minimum record length

. is 3 characters: the minimum word count is the 2's complement of 3 or 7775,
72

BEGINING

GAP

TAPE

jGAP

FILE MARK= 234

}. RECORD

RECORD..|

RECORD

enp
OF

TAPE

FILE MARK =234

(IRG)

_ RECORD { GAP

GAP

(IRG)

NS B

FILE

|
v
‘5

APPROX 3.8"———sd

CRCC

’

[}

]

foee—

||} e ]
!

DATA PREVWOUS—AM

FILE MARK

LRCC

LAST DATA

CHARACTER
OF PREVIOUS

FILE

LRCC

FIRST DATA —

CHARACTER
OF NEXT

Fw—lRG—«#»—-DATAhEXT

*"’-—O 6""‘"

IHH

1111 i‘*» %«i
LAST DATA

CHARACTER

OF PREVIOUS
RECORD

RECORD

LRCC

FIRST DATA

CHARACTER

OF NEXT
RECORD

FILE

FILE MARK AND GAP FORMAT
¥

RECORD

t@Ofi&M

IRG

FORMAT

=3 CHAR.SPACE

¥ #=7 CHAR SPACE
11-3069

Figure A-3 Data Recording Scheme
Records are separated by interrecord gaps (IRGs). The IRG is 0.5 in. (1.27 cm) minimum [approximately 0.6 in. (1.5 cm) in normal operation], but may be extended to 3 in. (7.62 cm) by performing an
extended gap operation. Tape IRGs (unrecorded areas) provide areas on the tape for the transport to
start or stop and also separate data records.

A.2.1

NRZI Recording Method (non-return-to-zero change on one)
In the NRZI recording method, a 1 bit is represented by a reversal in the direction of tape magnetization on a track; a 0 bit is represented by no change in tape magnetization.
|
|

BIT

WY TRACK

REFERENCE

i Bl) e
——

20— 2

«~ EDGE

—

RD 7

RD
6

— 3

— D —

— —— -

RD
5

—

—— — —

RD
4

§ —— P

—— ——

?C RD3

o 6 — D — — — — :

T — TP —— — —
2l
g
P
23—

— — — — -

0 — D

—

— —

READ HEAD

RD 2

1
7

RD
9

RD
P

CABLE

READ AMPS
1{-3091

Figure A-2

Track-Bit Weight Relationship for 9-Channel Transport

Tape Character — A bit recorded in each of the nine channels.

Record - A series of consecutive tape characters.

File - An undelined number of records (minimum = zero, no maximum).

Interrecord Gap (IRG) - A length of erased tape used to separate records [0.5 in., (1.27 cm)

minimum for 9-track; maximum IRG is 25 ft (762 cm)].

Extended IRG - A length of erased tape [3 in. (7.62 cm)"minimum] optionally used to

separate records. It must be used between BOT and the first record.

0. Tape Speed - The speed at which tape moves past the read/write heads; normally stated in
inches per second.

I1.

Tape Density - The .density of sequential characters on the tape. It 1s normally specified in
bytes per inch (bpi}, which is equivalent to characters per inch.

12.

Write Enable Ring - A rubber ring that must be inserted on the supply reel to allow the
transport to write on the particular tape. This safety feature helps prevent accidental
destruction of previously recorded data.
|

13.

Tape Mark (TM) - A record written on the tape to designate the end of
a file; sometimes
referred to as a file mark (FMK).
|
|

A2
RECORDING METHODS AND DECmagtape FORMATS
|
|
The DECmagtape system is an on-line mass storage system for programs or data. Data is recorded on
tape in vertical rows called characters. Each character consists of eight data bits and one vertical parity
bit. The vertical parity bit is program-selected as even or odd. The odd parity bit guarantees that each
character records at least one [ bit.
|

The parity bit is generated according to the rule that the number of s in a character (parity bit
included) is odd or even. For example, if odd parity is used and the character contains an even number
of I bits, the parity bit is generated as a | bit and an odd number of1 bits are recorded; then,
if an even

number of bits are read back from tape, a vertical parity error is generated to notify the program
that
the data is in error.

= -

i
R

DR
i

The CRC chavacter is generated during a write operation and written at the end of
a record. The chee
m‘%i.

?f‘d

jou g

J&)]

(0]

""@

Cl-

"'13
@)

ot g

pflg

.Mz

E,:';

character performs the same function to a fccord as the parity bit does to a character.

ra k coni‘.ammg an add numbm of Es a Gis szii@n on each Emgk
Qau:mg a ? ‘é@ be writien oneach i

containing an even number of |

A.2.3 T-Channel ’Fag}@ Format
Each character framein a 7-channel tape (Figure A-5) consists ofsix chararter bits (B, A, 8,4,2, I}in
descending order chsémz?gqma The parity bit, or check bit (C), is the seventh bit andis set or ciared
by the transport write head. One byte of a data word corresponds to one tape character. However,
bccmm one bjh contains eight bits and a tape character contains only six data bits, two bits within
each byte are not used. During 2 read operation, the extra bits are forced to 0; during a write oper‘ation, the bits remain unchanged. During the core dump mode of aperation, one byt@ correspandg to
two tape characters. Thus, fH bits within the byte are used; however the two most significant bits on

the i,csz, are not used.

/5 FORWARD
=

MOTION

ONE BYTE DURING
CORE DUMP MODE

J:
|

-l s i gl atd i 0l .

anie oul

R
P

EOF MARK

/LRC CHARACTER
gnld
th wt
ah
o
i
-l

ki
el o ot

- gy i WO el vl g

7
STE——— yee——

EXTENDED

IRG

b. EOF RECORD

EOF
, [*REcoRD

3 bt AN

BEGINNING
OF NEW

DATA BLOCK

C*A@%fié&%“
- 41-0391

Figure A-5

7-Channel Tape Format

ASS

w&ddi.

IN BLOCK

(IRG)

FORMAT

LAST DATA
RECORD

anll o> amih

it waln
i

oin wS

el
OISt
S

adn 2l

wal
it ol
o

-t oe Sulh oW

W
el
B

DATA

DATA
NEXT
RECORD

INTERRECORD

PERIOD

MIN.

a. 7T-CHANNEL

CHAHACTERS

3—CHARACTER
DATA

BOT GAP

[LRC CHARACTER

ln ol wlh wds ol

‘

{

uuuuuu

2
{

Beth wmh

.
———
o
>

1
{
{
1

A
B

otn

(PAR!TY)‘ C

s
s ) coll guit et

/—TAPE CHANNELS

The end of a block of records is indicated by an end-of-file mark character. The end-of-file (EOF)

mark 1s scparated from the data23 by an extended IRG. The extended IRG is a 3-in. strip of blank tape
compared to the standard 3/4- . JRG for 7-channel tape and the 1/2-in. IRG for 9-channel tape! The'
ECOF mark and assoctated LEC ¢ naracter are considered to be one complete record.
-

The 9-channel tape format (Figure A-6) is similar to the 7-channel format; however, because each

character consists of eight data bits and one parity bif, a byte corresponds to a tape character. Therefore, there 1s no need for a core dump mode, because information can be transferred from the syster
to the tape on a one-to-one ratio. A record for 9-channel tape may be any length from 18 characters to
2048 characters. In addition, the 9-channel format includes a cyclic redundancy check (CRC) charac[ter. Data is followed by three blank character periods, the CRC character, three more blank
character
periods, and the LRC character. The LRC character is followed by an IRG as before.
°

(PARITY)4

[+——80T GAP

8
t
v
1
1
1
SRR
RS
6
3
111
1t
I
S
T T I T
T
B

e
| BOT 148}

r"""'“"\

%J*j (A

CRC CHARACTER

ONE BYTE

1
R
1
T

/- ‘

1
1

I
f

R T

]

DATA

3 -CHARACTER

:
i

1
{9
11
1

'
1 1

PERIODS

1
{
1
{

ARACTERst CHARACTER
=

{
1
{
{

{

BRIIEEREE
IR

LRC CHARACTER

‘

INTERRECORD

GAP

{IRG)

—

mle—

NEXT
DATA

RECORD

11-0392

Figure A-6 9-Channel Tape Format A3
CYCLIC REDUNDANCY CHECK (CRC) CHARACTERS
The CRC character provides a method of error detection and correction on magtape

|
transports. The
code has nine check bits that form a check character at the end of each record. To perform a
correction, a record in which an error has been detected must be reread into memory
with the LRC and CRC
characters for program evaluation. Errors involving more than one track can
be detected but not
corrected.
|
»~

The CRC character is generated as follows:

1. The CRC register is cleared at the beginning of each record. As each data bit is written on
tape, it is exclusively ORed with its corresponding bit in the CRC register.

The CRC register is shifted one position to the right after the exclusive OR operation
has
‘taken place.

A-6

The magnetic tape is divided into data records, each record separated by an interrecor
d gap (IRG). A
record for 7-channct tape miay be any length from a minimum of 24 characters to a maximum
of 4008
charawters. In a block Tormat, a number of records are written together with an I1RG before
the first
record and after the lust record. In cither case, the IRG is an unused portion
of tape preceding and
following the record or the block.
|
|

The bits entering CRC 2, CRC 3, CRC 4, and CRC 5 of the CRC register are inverted if the
bit entering CRCP s a 1. Data is shown in Table A-1; the resultant CRC characier is shown
in Table A-2.

Table A-1

Five-Character Record

Characters

Dats

Data

Character ¢

Character 2

Character 3

Character 4

P
0
!
2

0
i
0

0
0
l
1

1
0
0
0

0
|
1

1
1

0
0

1
1

0
0

i
i

1
0

0
|

1
0

0
1

|
0

0
1

3
4

5
6
7

Table A-2

Data

Dats

- Character5
i
0
0
.
0

CRC Character in Register When Writing

CRC Register
.

CRC

‘

Bits

Cleared | Character1 |Character2 {Character3 [Character
4

CRCP
CRCO
CRCI
CRC2
CRC3

0
0
0
0
-0

0
0
1
0
0

0
0
0
0
1

CRC4
CRECS
CRC6
CRC7

0
-0

0
0

l
0

0
0

0
1

0
0
I
0

0
|
1
0

0
I
0

CRC

Character

Final

On Tape

1
0
0
0
0

0
0

|
1
i
1

0
1

1
0
0
-0

1
1

1
0

1
1
1
1

Steps 1 -3 are repéated for each data character of record.

AtCRCtime, all positions of the CRC register, except CRC2 and CRC4, are complemented
and the resultant CRC character is written on tape.

The CRC register is cleared for the next record.

fffff

TONCITUBINAL REDUNDANCY CHECK (LRC)

CHARACTED

The
LRC characteris written three spaces after the CRC
character. The vertical pa ?y bit is always
written on the LRC character; the vertical parify
of LRCis never checked. The .%;RC character makes
the longitudinal
p
amy ever f@x the entire record, including the CRC.
The LRCis generated by the
LEC repisterin if ¢ followingmanner:

The LRC registeris cleared at ?h@ beginning

Ascharg«clers are written on tape, corresponding | bits
complement the LEC register at the
time data is written on tape.

of @ record.

AtLRCtime, theLRC
%zmm clears the write buffer and s arc written on tape
in only thos=
channels for which the write bufferis set prior to clearing.

Following this method, the LRC character forces an even number
of bits to be recorded
o
each track of the tape. The CRC characterisinclude
d in determining the LRC gxmmfim

A5
DATA FILES
As previouslystaied, a recordis a group of characmm

preceded by an IRG and terminated by thres
spaces, a CRC character, three more spaces, and
an LRC character. A fileis a group of r@,mrfii;fi
separatedby IRGs and terminated by a 3 in. (7.62 cm)
gap followed by a file mark. The file mark is a

record consisting of a single data character [the end- of«fi
¢ (EOF) character] followed by seven blank
~characters and an LRC character. The CRC character
iis not written on an EQF r@%@@rd The LRC
character with a file mark is 2 duplicate of the EOF
characier (235)
A6 TRACK ASSIGNMENTS
i
'
- The track assignments for read, write, and pamy bits are

Table A-3
Transport
Track Number

I furthest from
‘

Track &mgfimw% for Data and Paflfiy

‘

Write

Read

Data Bits

Binary

Data Bits

Weight

WDS5

RDS

transpmfi

2
3
4
5
6

wD7
wWD3
WDP
WD2
WD1

8
9.closest to

WD6
WD4

transport

|
shownin Table A-3.

|
-

WDQ

A-8

-22
B

RD7
RD3
RDP
RD2
RD1I
RD6
RD4

20
2%
23
28

27
2

(