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EK-RX01-MM-001

July 1976

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Document:	RX8/RX11 Floppy Disk System Maintenance Manual
Order Number:	EK-RX01-MM
Revision:	001
Pages:	126
Original Filename:

OCR Text

RX8/RX11

floppy disk system

_maintenance manual

RX8/RX11

floppy disk system
maintenance manual

EK-RX01-MM-001

digital equipment corporation - maynard. massachusetks

Ist Edition, May 1975

2nd Printing (Rev), September 1975

3rd Printing, July 1976

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

5
4

CONTENTS
Page

CHAPTER 1
1.1

1.2
1.2.1

1.2.2

1.2.3
1.2.4

1.2.5

1.3
1.3.1

1.3.2
1.3.3
1.3.3.1

1.3.3.2
1.3.3.3
1.3.34

GENERAL INFORMATION

INTRODUCTION . . . i o e e e e e e e e e e e e e e e e e e e e e e e e e e e s 1-1
PHYSICAL DESCRIPTION . .. .. ... ... ... ... e e e e e e e e 1-1
RX8E/RX11 Interfaces . . . v v v v v v v v i e e e e e e e 1-2
Microprogrammed Controller . . . . . . . . . . oo .12
Read/Write BIECtIONICS . . .« v v v v v v e e e e e e e 1-2
Electro-Mechanical Drive . . . . . . . o o v v i e e e e e e e e e e e e e e e e 1-2
e 1-3
e e
e e e
Power SUPPLY . . v o o e e e e
e e e e e e e e e e e e e e e e 1-3
SYSTEMS COMPATIBILITY . . . . o o o e e
Media . . . . . e e e e e e e e e e e e e e e e e e e e e e e e e e e e 1-3
Recording Scheme . . . . . . . . . Lo 1-10
Logical Format . . . . . . . . o v v v e 1-10
e 1-10
e
Header Description . . . . . . . o v v v it
Data Field Description . . . . . . . . v v v v vt o e 1-11
1-11
Track Usage . . . o v o v v o e e e e e e e e e e e
CRC Capability . . . . . . o oo i e 1-12

1.6

e e 1-12
APPLICABLE INSTRUCTION MANUALS . . . . . . . . o oo e o i o e
e e 1-12
e
e
e
e
e
e
e
e
e
e
e
e
e
CONFIGURATION . . . . o o e e et e e e e e e e e e e
e 1-13
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
SPECIFICATIONS . . . . . o et e e e e e e e e e

CHAPTER 2

INSTALLATION AND OPERATION

1.4

1.5

2.1

2.2

2.2.1
2.2.2
2.2.3
224

2.3
2.3.1

2.3.2
2.3.3

2.34
2.3.5

2.4
2.4.1
2.4.2
2.4.3

2.4.3.1
2.4.3.2

244

2.5
2.5.1
2.5.2

2.5.3

2.5.3.1
2.5.3.2
254

PURPOSE AND ORGANIZATION . . . . . o o e e e e e e e e e e e e e e e 2-1
e e e e e e e e e e e e e e e e e e 2-1
SITE PREPARATION . . . . . o
SPACE . v v e e e e e e e e e e e e e e e e e e e e e e e e e 2-1
e 2-1
e
e e e e e e e e e e e e e e
Cablig . . .« v v e e e
e 2-1
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
AC POWET . . o e e e e e e e e e e e e
2-2
o
o
.
.
Fire and Safety Precautions . . . . . . . .
2-2
e
e
e
e
e
e
e
e
e
e
...
...
ENVIRONMENTAL CONSIDERATIONS . . ...
2-2
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
General . . . o e e e e e e e e e e e e e e
o 2-3
Temperature, Relative Humidity . . . . . . . .. .« oo
2-4
e
e
e
e
Heat Dissipation . . . . . . . o v v v it e
2-4
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
Radiated EMISSIONS + « « v o v v v v o e o e e e
v v v v e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e 2-4
CleanlineSS
e e e e 2-4
INSTALLATION . . . . o o o e e e e e e e e e et e e e e e s e e e
e e e 2-4
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
GeneTal . o ot e e e e e e e e e e e e e e
e e e e 2-4
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
TOOIS . . e e e e e e e e e e e
e e 2-4
t
i
v
v
v
o
.
Unpacking and Inspection . . . . . .
2-4
e
e
e
e
e
e
e
e
e
e
e
e
e
e
i
v
v
v
o
Cabinet-Mounted . . . . . . .
2-6
.
.
.
..
.
.
.
Separate Container . . . . .
2-6
e
e
e
e
e
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e
e
e
e
e
e
e
e
e
e
e
e
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e
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e
e
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e
e
e
Installation . . . . v o
2-8
e
e
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e
e
e
e
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e
e
e
e
e
e
e
e
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e
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e
e
e
e
OPERATION . . . o e e
2-8
e
e
e
o
c
oot
.
.
.
.
.
.
.
.
.
Operator Control .
2-8
oo
.o
.
.
.
.
.
.
.
.
.
.
.
.
Precautions
and
Practices
Diskette Handling
2-12
e
e
e
e
e
e
e
e
e
e
e
e
e
e
o
.
.
.
.
.
.
.
.
Diskette STOTAgE
Short Term (Available for Immediate Use) . . . . . . . . ..o« o oo 2-12
e e e e e e e e e e e e e e e e e e 2-12
Long Term . . ... ... e
.o 2-12
.
.
.
.
.
.
.
.
.
.
Diskettes
Shipping

CONTENTS (Cont)
Page

CHAPTER 3

RX11 INTERFACE PROGRAMMING INFORMATION

3.1

3.2

. . . . . . . . .. .. . . .. ... ... ....

3-1

. . . . . . . . . . . st
s et
.

3-2

3.2.1

RXCS — Command and Status (177170)

322

RXDB — Data Buffer Register (177172)

3.2.2.1

RXTA —RX Track Address

3222

RXSA —RX Sector Address

3.2.2.3

RXDB —RX DataBuffer

3.2.24

3.3

. . . . . . . . . . . . . .. ...

. . . . . . .

...
.. ......

3-3

3-4

. . . . ... ... .. ... ... ........

e e

e et

Fill Buffer (000)

3.3.2

Empty Buffer (001)

. . . . . . . . . .

Fndd

Write Sector (010)

. . . . . . . . . .

3.3.4

Read Sector (O11)

. . . . . . . .

3.3.5

Read Status (101)

. . . . . . . . . e

3.3.6

Write Sector with Deleted Data (110)

. . . . . . . . .

Read Error Register

3.3.8

Power Fail

3.4

Function (111)

3.4.1

Read Data/Write Data

3.4.2

Empty Buffer Function

3.4.3

Fill Buffer Function

3-4
3-5

3-5
. e

3-5

e e

3-6
3-6

3-7

. . . . .. .. P

3-7

. . . . . . . . . . . . . .. ... ... .....

3-7

. . . . . . . . . . o,

PROGRAMMING EXAMPLES

3-3
3-3

. . . . .. .. .. ... ... . . ... ......

3.3.1

3.3.7

3-2

. ... ... ... ... ... ... ........

RXES — RX Errorand Status
FUNCTION CODES

. . . . . . . . . . ... .

. . . . . . . . . . .. .. ... . ......

. . . . . . . .. i,
. . . . . . . . . . . . .

3-7

3-8
3-8

. . .. . . ... ... ... .. .. ... ... . ... ...

3-8

. . . . . . . . . .. . . .. . .. . ... 3-11

335

RESTRICTIONS AND PROGRAMMING PITFALLS

3.6

ERROR RECOVERY

CHAPTER 4

RXS8E INTERFACE PROGRAMMING INFORMATION

4.1

DEVICE CODES

4.2

INSTRUCTION SET

. . . . . .

. . .. ... ... ... ....... 3-11

. . . . . . .

e e e e

Load Command (LCD)

e, 3-11

e s

4-2

e it et e,

4-2

. . . . . . . ... . .. . ... .. .. .. .. ....

4-2

. . . . . . .

4.2.1

e e e e e e

. . . . . . . . . . . .

4-1

4.2.2

Transfer Data Register (XDR)

4.2.3

STR

. e
e
e
e e e e

4-3

4.2.4

SER

. e
e
e e
e

4-3

4.2.5

SDN

e
e e
e e e e e e
e

4-3

4.2.6

INTR

. o

4-3

INIT

4.2.7

4.3

e e

e e e

e e

e e e

4-3

e e e

e e

4-3

. . . . . . . . . .

4.3.1

Command Register

4.3.2

Error Code Register

4.3.3

RXTA — RX Track Address

. . . . . . . . . . . . . . .

4.3.4

RXSA — RX Sector Address

. . . . . . . . . . . o o e

4-5

4.3.5

RXDB — RX Data Buffer

. ... ... ... ... .. .. ... ... .. ... ...

4-6

. . . . . . . . . . .. e

4-6

4.3.6
4.4

4.4.1

. . . . . . . . . . . . .

RX Error and Status

e e

4-3

. . . . . . . . . . . . . . . e

4-4

FUNCTION CODE DESCRIPTION

Fill Buffer (000)

. . . . . . . . . . .

i i .

4-7

. . . . . . . . . e

4-7

4.4.2

Empty Buffer (001)
Write Sector (010)

. . . ... .. .... s

4.4.4

Read Sector (011)

. . . . . . . . .

4.4.5

Read Status (101)

4.4.3

. . . . . . . . . . e

4-8

5 & & B 5. E B g ma s w k8 kwommw s wa

4-8

4-9

. . . . . . . e
e

4-9

CONTENTS (Cont)
Page

4.4.6

Write Deleted Data Sector (110)

4.4.7

Read Error Register Function (111)

4.4.8

4.5

. . . . . . . . . . e
e e e e e

4-9

. . . . . . . . .

4.5.1

Write/Write Deleted Data/Read Functions
Empty Buffer Function

4.5.3

Fill Buffer Function

e s 4-10

. . . . . . . . .. . . ... ... ..... 4-10

. . ;.. & 2503w o0 v

588 0 0 s s e

. . . . . . . . . . . . . . .

4.6

RESTRICTIONS AND PROGRAMMING PITFALLS

4.7

ERROR RECOVERY

CHAPTER 5

THEORY OF OPERATION

5.1

6 8 2 8 8 o8 4-10

e 4-10

. ... .. ... .. ......... 4-15

. . . . .

e e e e e e e e e e

e e e 4-16

OVERALL SYSTEM BLOCK DIAGRAM

. . . . .. . . .. .. . ..

5-1

5.1.1

Omnibus to RX8E Interface Signals

. . . . . . . .. .. ... ... .. .. .....

5-2

3 B

Unibus to RX11 Interface Signals

. . . . . . .. ... . ... ... ... ......

5-3

5.1.3

Interface to uCPU Controller Signals

. . . . . . . . . . . .. .. .. ... ......

5.14

uCPU Controller to Read/Write Electronics Signals

3i1.5

Read/Write Electronics to Drive Signals

5.2.1

. . . . . . .. R B

5-6

. . . . . . . . . ... ... ... ... ...

5-7

DETAILED BLOCK DIAGRAM AND LOGIC DISCUSSION

RX8E Interface

. . . . . . . . . .

. . . .. ... ... .. ...

5-8

e e e

5-8

5.2.1.1

Device Select and IOT Decoder

. . . . . . . .. ... .. ... .. ... ...

5-8

5.2.1.2

Interrupt Control and Skip Logic

. . . . . . . . . . . ... oL,

5-8

5.2.1.3

CLine Select Logic

5.2.14

Interface Register

5.2.1.5
Hedai

. . . . « . . . « v o v

Sequence and Function Control Logic
RX11 Interface

0T o000 0f 4 o o 6 a8 5 5 o 3

. . . . . . . . . . . .. L

e e e e e e e e e e e

Address Decoder

3edslnd

Data Path Selection

5.2.2.3

Interface Register

5.2.2.4

Sequence and Function Control Logic

. . . . . . . . .

e e

5.2.2.5

Interrupt Control Logic
Vector Address Generator

. . . . . . . . . . . .
. . . . .. .. e

S5,
1

Control ROM and Memory Buffer

5.2.3.2

Program Counter and Field Counter - .

e e 5-13

Instruction Decode Logic

5.2.3.4

Do Pulse Generator

5.2.3.5

Branch Condition Selector and Control

0. .0 oL

. . . . . . . . . . . . .

Scratch Pad Address Register and ScratchPad

Counter Input Selector, Counter, and Shift Register

5.2.3.8

MCPU Timing Generator

5.2.3.9

Sector Buffer and Address Register

5.2.3.10

CRC GeneratorandChecker

5.2.3.11

Data Synchronizer and Separator

5:2.3.12

Output Cireuit

Wait Branch

L oo 5-16
e v v v e s 5-17

. . . . . . . ... .. ... 5-17
0 i i i e

e e e

. . . . . . . ... ... ...

. . . . /o iy o

A3 o Vo

e e e e 5-18

... 5-18

o o o v o 5 s 5-18

. . . . . . . . .. ... ..., 5-19

. « = ¢ + « + » 5 ¢ & &« S

5.2.4.3

...... 5-14

o vie oo o v v o s 5-16

. . . . . .. ... ... ... .. 5-17°

. . . . . . . . . . . .

BRI

VE VI

Bd o v o v v v s 5-20

. . . . . . . .. .. ... ... ..., 5-21

. . . . . . . o o i

. . . .

e 5-14

. . . . . . ... .. ... . ...... 5-17

ML Du

DO Instruction

wive

100 00 3% Fo 2000

5.2.3.6

Conditionadl Branch

. . .. ... ... ... ... .... 5-14

. . . . & s o s s 5 o

Microprogram Instruction Repertoire

o e 5-14

e e e e e e e e e e e

. . . .. ... ... ... ...

5.2.3.3

5.2.4.2

5-11

. . . . . .. ... ... ... ...... 5-13

Microprogrammed Controller (uCPU) Hardware

5.2.4.1

e e e e e 5-11

. . . . . . . . . . . . . .. 5-13
. . . . . . . . . . ..

5.2.2.6

5.24

5-8

e 5-10

. . . . . . ... .. .. ... ...... 5-10

. . . . . . . . . o

5.2.2.1

5.2.3

4-9
49

4.5.2

5.2

Power Fail

. . . . . . . . . . .. . . . ... ... .....

PROGRAMMING EXAMPLES

. . . . . . . . . . . . . . .

e e

% . o v

. . . . . . . . .

e e e e e e e e e e e e e 5-21

madlaply SIS

o 0 o« 0 6 s 5-22

e e 5-22

CONTENTS (Cont)
Page

5244
5.2.4.5
5.2.5

5.2.6

5.2.6.1

5.2.6.2

5.2.6.3
5.2.64
5.2.7
5.2.7.1

5.2.7.2

5.2.7.3
5.2.74
CHAPTER 6

6.1
6.2
6.3
6.3.1

6.3.2
6.4

6.4.1
6.4.1.1

6.4.1.2

6.4.2

. . . . . . . . .. . . o e 5-22
Open ScratchPad
e 5-23
e e
e e
e
Jump . ..
5-23
..
...
..
...
..
.
.
.
.
.
.
.
Microprogram Flowchart Description
5-36
e
e
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e
e
e
e
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e
e
e
e
v
v
v
v
v
v
«
Read/Write EIeCtronics . . .
5-36
e
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e
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e
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e
e
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e
0
.
.
.
.
.
.
.
Diskette Position .
Head Read/Write Circuitry . . . . . o« v v v v v i et e e e e e e e e e 5-36
. . . . . . . . . . . . .. .. .. 5-36
Head Load Control and Solenoid Drivers

Stepper Motor Control and Motor Drivers

Mechanical DIive . . . . . v v o v e e e e e
Drive Mechanism . . . . . . v o v i e
. e
Spindle Mechanism . . .. ...
Positioning Mechanism . . . . . . . .
Head Load Mechanism . . . . . . v v

. . . . .. . . ... ... B 5-36

e e e e e e e e e e e e e e e e e e e e 5-38
e e e e e e e e e e e e e e e e e e e e 5-39
5-39
e e e e e e e e e e e e e e e e e e
. ... L o o s 5-39
v v v v e e e e e e e e e e e e e e 5-41

MAINTENANCE

RECOMMENDED TOOLS AND TEST EQUIPMENT . . . . ... .. ... ... .. ...
e e e
e e e e e e e e e e e e e e e e e
CUSTOMER CARE . . . . .
s
e e e e e e e
REMOVAL AND REPLACEMENT . . . . . . . . .
e e
e
e
Module Replacement . . . . . . . . . . ..o
Drive Placement . . . . . . v i i e e e e e e e e e e e e e e e e e e e e e e e e
e e
e e
. . . . . . . .
CORRECTIVE MAINTENANCE
. . . . . . o . e e e e e e e e e e e e e e e e e e e e
Initialize Errors
oo oo
Interface Diagnostic in Memory . . . . . . . . . ..o
. . . . . . . . . . oo oo
Diagnostics Not in Memory
e
KMITUSQZE . . v v v o e e e e e e e e e e e e e e e e e e e e e e e e e

6-1
6-1
6-2
6-2
64
64
6-4
64
6-9
6-9

ILLUSTRATIONS
Figure No.
1-1

1-2
1-3
1-4

1-5
1-6

1-7
1-8
1-9

1-10
1-11

2-1
2-2

2-3
24
2-5

2-6

Title

Page

v 1-2
oo
. . . . . .. ... ... .
Floppy Disk System Configuration
. . . . . . . . . .. .. v 1-3
Front View of the Floppy Disk System
M8357 Module (RX8E Interface) . . . . . . . . o v v i i i 1-4
. . . . . . . . o v v v i it e 1-5
M7846 Module (RX11 Interface)
Top View of the RX01 . . . . . . . . . . o o e 1-6
e e e e e e e e e e e e 1-7
Underside View of Drive . . . . . . . . o o o e e e
1-8
e
e
e e
Top View of Drive . . . . . . . . . o o e
1-9
e
e
e
e
e
e
e
e e e e e e e e e e e e e
Diskette Media . . . . . . . o i i e
1-10
e
e
e
e
e
e
e
e
Flux Reversal Patterns . . . . . . o o v v v i e e e e e e e e e e e e
o oot 1-10
. . . . . . . . . ..
Track Format (Each Track)
e 1-11
Sector Format (Each Sector) . . . . . . . . . o v vt i
e 2-2
e
e
e
e
e
e
e
e
e
e e
e e e e e e e e e
. .
RXO1
e 2-3
e
e
e
e
e
e
e
e
e
e
e
e
b
i
v
v
v
v
Cabinet Layout Dimensions . . . . . . .« v v
2-5
e
e
oo
v
o
.
.
RXO01 Shipping Restraints . . . . . . . . .
2-7
e
e
e
e
e
e
e
e
e
e
RX8/RX11Unpacking . . . . .« v v i i i e e
2-8
e
..
.
.
.
.
.
.
.
RXO01 Cabinet Mounting Information . . .
2-9
e
e
e
e
o
Cable Routing, BCOSL-15 . . . . . . . . o

THITE

ILLUSTRATIONS (Cont)
Title

Figure No.

2-7

Flexible Diskette Insertion

3-1

RXCS Format (RX11)

. . . . . . o

. . . . . . . . . . . . . o

RXTA Format (RX11)

. . . . . . . .

e e e e

RXSA Format (RX11)

. . . . . . . .

3-4

RXDB Format (RX11)

. . . . . . .

3-5

RXES Format (RX11)

. . . . . . . . o

e i e e

3-6

RX11 Write/Write Deleted Data/Read Example

3.7

RX11 Empty Buffer Example

3-8

RX11 Fill Buffer Example

4-1

LCD Word Format (RX8E)

4.2

Command Register Format (RX8E)

4.3

Error Code Register Format

4-4

RXTA Format (RX8E)

. . . . . . .

4.5

RXSA Format (RX8E)

. . . . . . . . .

e e e e e e e

e e e
e

e e

e et e e e
e

e
e e

. . . .. .. . .. ... .. .. ......

. . .. . ... ... ...

. . . . . . . . . . . . . .

. . . . . . . . . .

0o
e

e e

. . . . . . . . . . . .. v

. . . . . . . . . . . . . . . i

e e

e s e

4-6

RXDB Format (RX8E)

4.7

RXES Format (RX8E)

. . . . . . . . .

4-8

RX8E Write/Write Deleted Data/Read Example

4.9

RX8E Empty Buffer Example

4-10

Fill Buffer Example

Omnibus to RX8E Interface Signals

. . . . . . .

e
e

. . ... ... ... ... .. .. .....

. . . . . . . . . . . . . .

Bus Structure

. . .. . .. ... ... ...

5-1

e
e

. . . . . . . . .

. ... ...

...

e e e

e e e e e e e e e e e e e e e e e e e e e e e

. . . . .e

e e e

. . . . . . . . . . . . ..

e e

5-3

Unibus to RX11 Interface Signals

5-4

Interface to uCPU Controller Signals

5.5

5-6

uUCPU Controller to Read/Write Electronics Signals
. . . . . . . . . . . .. ...
...
Read/Write Electronics to Drive Signals
. . . . . . . . . .. .. ..
o
oo

5-7

RXS8E Interface Block Diagram

. . . . . . . . . .

5-8

RX11 Interface Block Diagram

. . . . . . . . . . . . . o o i

MCPU Controller Block Diagram

. . . . . . . . . . .

5-10

Data and Clock Separation

. . . . . . . . . . . .

5-11

ID Address Mark Data Separation

Initialize and Function Decode Flowchart

5-13

Empty and Fill Buffer Functions Flowchart

Read Sector and Read Status Functions Flowchart

5-16

FINDTR Subroutine Flowchart

5-17

FINDHD and GETDAM Subroutines Flowchart

5-18

HDRCOM, BDSRT, BADHDR Routines Flowchart

521

DIF and CHKRDY Subroutine Flowchart

5-22

Read/Write Electronics Block Diagram

5-23

Disk Drive Mechanical System

6-2

Troubleshooting Flow

6-3

BCOSL-15Cable

...

e e e

. . .. ... .. ... ... ......

STEPHD, WAITRN, MAGCOM Subroutines Flowchart

RXO01,Rear View

...

. . . . . e e e e e e e e e

DELAY, FINDSE, WRTOS, GETWRD Subroutines Flowchart

Positioning Mechanism

. . ... ... ... ... ... ....

5-19

5-26

. . . . . . . . . . . . ..

. . . . ... ... .. ...

. . . . ... .. ... ... ....

. . . . . . . ... .. ... ...

... ...

. . . . . . . . . ... ...

. . . . . . . . . . .

. . . . . . . .

e e

. . . . . .. . . .. .. ... .. .. ... ... ...

5-20

Drive MechaniSm

. . . ... ... ... ... ... .......

Write Sector Function Flowchart

Centering Coneand Drive Hub

e e e

e e e e e

. . . . . .. ... ... ...

5-14

5-25

v v v oo

o v ittt e e

. . . . .. . . . ..

5-15

5-24

oo v

o o i v i

. . . . . . . . . . o o o i i i i

5-12

6-1

i i
o o

it e e

. . . . . . . . . . .

L0
e

e e e e e

e e

vii

e e e e e e

oo
e

. . . . . . . . . . . o o o

. . . . . . o o

e e e e e e e e e e e e e e e e e e e e e e

. . . . . . . . . . . ...

. . . . . . . o i o i

e e e e e

e e e e e e e

e e e e e

oo
e

e e

e e e

ILLUSTRATIONS (Cont)

Title

Figure No.

Page

6-4

RX8 Status Routine

6-5

RX11 Status Routine

. . . . . . . . . . ..
e e e e 6-10

6-6

KM11 Maintenance Module Inserted

6-7

KM11 Light and Switch Definitions for RX01

. . . . . . . . . . .

e e e e

. . . . . . . . . . . ... ...

e e

e e 6-10

.. ...

... 6-11

. . . . . . .. .. .. ... ... .. .... 6-12

TABLES

Title

Table No.
2-1

Interface Code/Jumper Configuration

4-1

Device Code Switch Selection

5-1

C Line Transfer Control Signals

Page

. . . . . .. ... .. ... .. . .

. . . . . . . . . . . . . .

. . . . .. ... ... ...

6-1

Recommended Tools and Test Equipment

6-2

M7727 Connectors

. . . . . . . . L

Viii

... ... .. 2-10
e

. . . . . . .. e

e e e

e e e e e e e e e e e e e e

4-1

oL 5-10

e e

6-1

6-3

CHAPTER 1

GENERAL INFORMATION

This manual presents information on the installation, operation, programming, theory of operation, and
maintenance of the RX8 or RX11 Floppy Disk System. Chapter 2 (Installation and Operation) should be consulted
for unpacking and installation information. Chapter 2 also provides information on the proper care of the media and
should be read carefully.
1.1

INTRODUCTION

The RX8 and RX11 Floppy Disk Systems consist of an RX01 subsystem and either an RXS8E interface for a PDP-8

system or an RX11 interface for a PDP-11 system.

The RXO01 is a low cost, random access, mass memory device that stores data in fixed length blocks on a
preformatted, IBM-compatible, flexible diskette. Each drive can store and retrieve up to 256K 8-bit bytes of data
(PDP-11 or PDP-8) or 128K 12-bit words (PDP-8). The RX01 consists of one or two flexible disk drives, a single
read/write electronics module, a microprogrammed controller module, and a power supply, enclosed in a
rack-mountable, 10-1/2 inch, self-cooled chassis. A cable is included for connection to either a PDP-8 interface
module for use on the PDP-8 Omnibus or a PDP-11 interface for use on the PDP-11 Unibus.

The RX01 performs implied seeks. Given an absolute sector address, the RXO01 locates the desired sector and
performs the indicated function, including automatic head position verification and hardware calculation and
verification of the Cyclic Redundancy Check (CRC) character. The CRC character that is read and generated is
compatible with IBM 3740 equipment.

The RX01 connects to the M8357 Omnibus interface module, which converts the RX01 I/O bus to a PDP-8 family
Omnibus structure. It controls interrupts to the CPU initiated by the RXO01, controls data interchange between the
RXO01 and the host CPU, and handles I/O transfers used to test status conditions.

The RXO01 connects to the M7846 Unibus interface module, which converts the RX01 I/O bus to a PDP-11 Unibus
structure. It controls interrupts to the CPU initiated by the RX01, decodes Unibus addresses for register selection,

and handles data interchange between the RX01 and the host CPU.
The interface modules are dc powered by their host processor.
1.2 PHYSICAL DESCRIPTION

A complete system consists of the following components:
M7726 controller module

M7727 read/write electronics module
H771A or B power supply

RX01-CA floppy disk drive (60 Hz, max of 2)
RXO01-CC floppy disk drive (50 Hz, max of 2)

M8357 (RX8E) or M7846 (RX11) interfaces

1-1

TrHmE

All components except the interface are housed in a 10-1/2 in. rack-mountable box. The power supply, M7726
module, and M7727 module are mounted above the drives. Interconnection from the RXO01 to the interface is with a
40-conductor BCOSL-15 cable of standard length (15 ft). Figure 1-1 is a configuration drawing of the system, and
Figure 1-2 is a front view of a dual drive system.

DRIVE # 0

DISKETTE
0

1l
—

=0
N

DRIVE

ELECTRONICS

M7727

MB357

owmniBus
ERFACE

INTERFAC

CONTROLLER
!

M7 846

INTERFACE

UNIBUS

pCPU

M7726

DRIVE # 1

DISKETTE

POWER
SUPPLY,
..

CP-1505

Figure 1-1

1.2.1

Floppy Disk System Configuration

RXS8E/RX11 Interfaces

Interface modules M8357 (RX8E) and M7846 (RX11) are both quad modules. The M8357 plugs into an Omnibus
slot and allows the RXO01 to be used on the PDP-8 processors. The M7846 plugs into an SPC (small peripheral

controller) slot with any PDP-11 processor. Figure 1-3 shows the M8357 module and its major sections. Figure 14
shows the M7846 module and its major sections.
1.2.2

Microprogrammed Controller

The M7726 microprogrammed controller module is located in the RX01 cabinet as shown in Figure 1-5. The M7726
is hinged on the left side and lifts up for access to the M7727 read/write electronics module.

1.2.3

Read/Write Electronics

The M7727 read/write electronics module is located in the RX01 cabinet as shown in Figure 1-5.
1.2.4

Electro-Mechanical Drive

A maximum of two drives can be attached to the read/write electronics. The electro-mechanical drives are mounted

side by side under the read/write electronics board (M7727). Figure 1-6, which is an underside view of the drive,
shows the drive motor connected to the spindle by a belt. (This belt and the small pulley are different on the 50 Hz

and 60 Hz units; see Paragraph 2.2.3.2 for complete input power modification requirements.) Figure 1-7 is the top
view showing the electro-mechanical components of the drive.

1-2

Figure 1-2 Front View of the Floppy Disk System
Power Supply

1.2.5

is rated at
The H771 power supply is mounted at the rear of the RX01 cabinet as shown in Figure 1-5. The H771A
voltage
four
over
Hz
1/2
+
Hz
50
60 Hz *+ 1/2 Hz over a voltage range of 90—132 Vac. The H771C and D are rated at
ranges:

90—120 Vac
100—132 Vac
180—240 Vac

200—264 Vac

} 3.5 A circuit breaker; H771C
} 1.75 A circuit breaker; H771D

Two power harnesses are provided to adapt the H771C or D to each voltage range. This is not applicable to the
H771A. See Paragraph 2.2.3.2 for complete input power modification requirements.
1.3

—

SYSTEMS COMPATIBILITY

This section describes the physical, electrical, and logical aspects of IBM compatibility as defined for data

interchange with IBM system 3740 devices.
1.3.1

Media

The media used on the RX8 or RX11 Floppy Disk System is compatible with the IBM 3740 family of equipment
and is shown in Figure 1-8.

The “diskette” media was designed by applying tape technology to disk architecture. This resulted in a flexible
drive spindle
oxide-on-mylar surface encased in a plastic envelope with a hole for the read/write head, a hole for the
surface.
diskette
the
cleans
that
material
fiber
a
with
lined
is
envelope
hub, and a hole for the hard index mark. The
The media is supplied to the customer preformatted and pretested.
1-3

BCO5L-15
INTERFACE

CABLE

CONNECTOR

DEVICE

CODE

SWITCHES

7408 3

F igure 1- 3

M8357 Module (RXS8E Interface)

1-4

CONNECTOR
FOR THE

BCO5L-15
INTERFACE

CABLE

PRIORITY
PLUG

RX11
INTERFACE

Figure 144 M7846 Module (RX11 Interface)

7408-4

M7726 uCPU

CONTROLLER
MODULE

SET OF 12

BCO5L-15

ROMS

INTERFACE

CABLE

H771
POWER

SUPPLY

M7727
READ/WRITE
ELECTRONICS

MODULE

Figure 1-5

Top View of the RXO01

DRIVE MOTOR

DRIVE SPINDLE

BELT

PULLEY

AC
DRIVE
MOTOR

POWER

CONNECTOR

STEPPER
o

MOTOR

7408-5

igure 1 -6

Underside View of Drive

1-7

READ/WRITE
HEAD

HEAD LOAD

HELIX

ARM

DRIVE

7408-7

Figure 1-7

Top View of Drive

1-8

REGISTRATION
INDEX HOLE

HOLE

READ/WRITE
HEAD
APERTURE

Figure 1-8

Diskette Media

1-9

7408-2

TTERT

1.3.2

Recording Scheme

The recording scheme used is “double frequency.” In this method, data is recorded between bits of a constant clock
stream. The clock stream consists of a continuous pattern of 1 flux reversal every 4 us (Figure 1-9). A data “one” is

indicated by an additional reversal between clocks (i.e., doubling the bit stream frequency; hence the name). A data

“zero” is indicated by no flux reversal between clocks.
A continuous stream of ones, shown in the bottom waveform in Figure 1-9, would appear as a “2F” bit stream, and
a continuous stream of zeros, shown in the top waveform in Figure 1-9, would appear as a “1F” or fundamental

frequency bit stream.

l
o,

|
0o

1
|

I
1

D
o

]

N
!

|
o

O O O O
1,

|
|

]

LO
o

!
|

|
|

oV
|

]

.,
i

CHANGING

|
!

ALL ONES
PATTERN
I

B
|

Figure 1-9

| PATTERN

_.4: 4usec :...

1.3.3

ALL ZEROS

]

CP-1506

Flux Reversal Patterns

Logical Format

The logical format of the RX8 and RX11 Floppy Disk Systems is the same as that used in the IBM 3740.
Data is recorded on only one side of the diskette. This surface is divided into 77 concentric circles or “tracks”

numbered 0—76. Each track is divided into 26 sectors numbered 1—26 (Figure 1-10). Each sector contains two
major fields: the header field and the data field (Figure 1-11).
/— L.E.D. TRANSDUCER OUTPUT
HARD
INDEX
MARK

15
SECTOR

PRE-INDEX
GAP

SECTOR

# 26

R320BYTES

# 1

SECTOR
#2

SECTOR
#3

SECTOR
#4

—\

CP-1507

SOFT INDEX MARK
V

1 BYTE
<« ROTATION

Figure 1-10

1.3.3.1

Track Format (Each Track)

Header Description — The header field is broken into seven bytes (eight bits/byte) of information and is

preceded by a field of zeros for synchronization.
1.

Byte No. 1: ID Address Mark — This is a unique stream of flux reversals (not a string of data bits) that is

decoded by the controller to identify the beginning of the header field.
2.

Byte No. 2:

Track Address — This is the absolute (0—114g) binary track address. Each sector contains

track address information to identify its location on 1 of the 77 tracks.

DATA FIELD

HEADER FIELD
.

OSlox | =

S 28|

SYNC

FIELD

ALL"0'S"
33 BYTES

29|

om | D5

39| 3a|

Mlmx | g | M3 | m
)
4

MARK

——

)

[

> | TMM
=)
2
m

>
S

Gre"

sByTEs

DATA MARK | o 3

|SYNGFIELD | 3o
|ALLOS

17 BYTES

m
m

128,, BYTES

OF DATA

DATA

CRC

2 BYTES

2—

11BYTES—=

]4—1 BYTE

WRITE GATE TURN OFF

FOR WRITE OF PRECEEDING

le—6 BYTES

\‘ WRITE GATE TURN ON
FOR WRITE OF NEXT

DATA FIELD

cP-

1508

<+—— ROTATION

Figure 1-11

Sector Format (Each Sector)

Byte No. 3 — Zeros (one byte)

Byte No. 4: Sector Address — This is the absolute binary sector address (1-323g). Each sector contains
sector address information to identify its circumferential position on a track.
Byte No. 5 — Zeros (one byte)

Bytes No. 6 and 7: CRC — This is the Cyclic Redundancy Check character that is calculated for each
sector from the first five header bytes using a polynomial division algorithm designed to detect the types
of failures most likely to occur with “double frequency” recorded data and the floppy media. The CRC
is compatible with IBM 3740 series equipment.

1.3.3.2 Data Field Description — The data field is broken into 131 bytes of information and is preceded by a field

of zeros for synchronization and the header field (Figure 1-11).
1.

Byte No. 1: Data or Deleted Data Address Mark — This is a unique string of flux reversals (not a string
of data bits) that is decoded by the controller to identify the beginning of the data field. The deleted

data mark is not used during normal operation but the RXO01 can identify and write deleted data marks
under program control, as required. The deleted data mark is only included in the RX8/RX11 system to
be IBM compatible. One or the other data address marks precedes each data field.

Bytes No. 2—129 — These bytes comprise the data field used to store 128 8-bit bytes of information.
NOTE

Partial data fields are not recorded.

Bytes No. 130 and 131 — These bytes comprise the CRC character that is calculated for each sector
from the first 129 data field bytes using the industry standard polynomial division algorithm designed to
detect the types of failures most likely to occur in double frequency recording on the floppy media.

1.3.3.3 Track Usage — In the IBM 3740 system, some tracks are commonly designated for special purposes such as

error information, directories, spares, or unused tracks. The RXO01 is capable of recreating any system structure

through the use of special systems programs, but normal operation will make use of all the available tracks as data
tracks. Any special file structures must be accomplished through user software.

1.3.3.4

CRC Capability — Each sector has a two-byte header CRC character and a two-byte data CRC character to

ensure data integrity. The CRC characters are generated by the hardware during a write operation and checked to
ensure all bits were read.correctly during a read operation. The CRC character is the same as that used in the IBM
3740 series of equipment. A complete description of CRC generation and checking is presented in Paragraph 5.2.3.

1.4

APPLICABLE INSTRUCTION MANUALS

This manual is designed to be used in conjunction with the RX8/RX11 Engineering Drawings. Other documents
useful in operating and understanding the RX8/RX11 system are:
PDP-11%* Processor

Handbook

PDP-11 Peripherals and Interfacing Handbook
PDP-8 Small Computer Handbook
PDP-84 User Manual

1.5

CONFIGURATION

Option number designations are as follows:
PDP-8 Systems

RX8-AA

Single drive system, 115V, 60 Hz

RX8-AD

Single drive system, 50 Hz

RX8-BA

Dual drive system, 115 V/60 Hz

RX8&-BD

Dual drive system, 50 Hz

PDP-11 Systems

RX11-AA

Single drive system, 115 V/60 Hz

RX11-AC

Single drive system, 50 Hz

RX11-BA

Dual drive system, 115 V/60 Hz

RX11-BD

Dual drive system, 50 Hz

NOTE
50 Hz versions are available in voltages of 105, 115, 220, 240

Vac by field pluggable conversion. See Paragraph 2.2.3.2 for

complete input power modification requirements.

*Appropriate handbook for the particular processor used with the system.

1-12

1.6

SPECIFICATIONS

System Reliability

Minimum number of revolutions per track

1 million/media (head loaded)

Seek error rate

1in 10° seeks

Soft read error rate

1 in 10° bits read

Hard read error rate

1 in 10'? bits read
NOTE

The above error rates only apply to media that is properly
cared

for.

Seek

error

and

soft

read errors are usually

attributable to random effects in the head/media interface,
such as electrical noise, dirt, or dust. Both are called “soft”
errors if the error is recoverable in ten additional tries or less.
“Hard” errors cannot be recovered. Seek error retries should
be preceded by an Initialize.

Drive Performance
Capacity

8-bit bytes

12-bit words

256,256 bytes

128,128 words

Per track

3,328 bytes

1,664 words

Per sector

128 bytes

64 words

Per diskette

Data transfer rate

Diskette to controller buffer

4 ps/data bit (250K bps)

Buffer to CPU interface

2 us/bit (500K bps)

CPU interface to I/O bus

18 us/8-bit byte (>50K bytes/sec)
NOTE

PDP-8 interface can operate in 8- or 12-bit modes under
software control. The transfer rate is 23 us per 12-bit word

(>40K bytes/sec).
Track-to-track move

10 ms/track maximum

Head settle time

20 ms maximum

Rotational speed

360 rpm * 2.5%; 166 ms/rev nominal

Recording surfaces per disk

Tracks per disk

77 (0—76) or (0—1143)

Sectors per track

26 (1-26) or (0—32g)

Recording technique

Double frequency

Bit density

3200 bpi at inner track

Track density

48 tracks/in.

Average access

488 ms, computed as follows:

Seek

(77 tks/2) X 10ms

Settle

+ 20ms

Rotate

(166 ms/2) =488 ms

Environmental Characteristics
Temperature

RXO01, operating

15° to 32° C (59° to 90° F) ambient; maximum
temperature gradient = 20° F/hr (-6.7° C/hr)

RXO01, nonoperating

-35° to +60° C (-30° to +140° F)

Media, nonoperating

-35° to +52° C (330° to +125° F)
NOTE

Media temperature must be within operating temperature
range before use.
Relative humidity
RX01, operating

25° C (77° F) maximum wet bulb
2° C (36° F) minimum dew point
20% to 80% relative humidity

RXO01, nonoperating

5% to 98% relative humidity (no condensation)

Media, nonoperating

10% to 80% relative humidity

Magnetic field

Media exposed to a magnetic field strength of 50 oersteds
or greater may lose data.

Interface modules

Operating temperature

5°t0 50° C (41° to 122° F)

Relative humidity

10% to 90%

Maximum wet bulb

32° C (90° F)
2°C(36° F)

Minimum dew point
Electrical
Power consumption

RX01

3 Aat24 V (dual), 75W;5 Aat5V,25W

PDP-11 interface (M7846)

Not more than 1.5 A at 5 Vdc

PDP-8 interface (M8357)

Not more than 1.5 A at 5 Vdc

AC power input

4 Aat 115 Vac

2 A at 230 Vac

1-14

CHAPTER 2

INSTALLATION AND OPERATION

2.1

PURPOSE AND ORGANIZATION

This chapter provides information on installing and operating the RX8/RX11 Floppy Disk System. This information

is organized into four sections as outlined below.

1.
2.

4.
2.2

Site Preparation — The planning required to make the installation site suitable for operation of the

floppy disk system, including space, cabling, and power requirements, and fire and safety precautions.

Environmental Considerations — The specific environmental characteristics of the floppy disk systems,
i.e., temperature, relative humidity, air conditioning and/or heat dissipation, and cleanliness.

Installation — The actual step-by-step process of installing the floppy disk system from unpacking

through the preliminary installation checks, power conversion techniques, and acceptance testing.

Operation Practices — The recommended practices for using the floppy disk system, handling the media,
and shipping and storing the diskettes.

SITE PREPARATION

2.2.1

Space

The RXO1 is a cabinet-mountable unit that may be installed in a standard Digital Equipment Corporation cabinet.

This rack-mountable version is approximately 10-1/2 in. (28 cm) high, 19 in. (48 cm) wide, and 16-1/2 in. (42 cm)

deep (Figure 2-1).

Provision should be made for service clearances of approximately 22 in. (56 cm) at the front and rear of the cabinet
(Figure 2-2).
2.2.2

Cabling

The standard interface cable provided with an RX8/RX11 (BCO5L-15) is 15 ft (4.6 m) in length, and the positioning
of the RXO01 in relation to the central processor should be planned to take this into consideration. The RX01 should

be placed near the control console or keyboard so that the operator will have easy access to load or unload disks.
The position immediately above the CPU is preferred. The ac power cord will be about 9 ft (2.7 m) long.

2.2.3

AC Power

2.2.3.1 Power Requirements — The RXO01 is designed to use either a 60 Hz or a 50 Hz power source. The 60 Hz
version (RX01-A) will operate from 90 to 132 Vac, without modifications, and will use less than 4 A operating. The
50 Hz version (RX01-D) will operate within four voltage ratings and will require field verification/modification to
ensure that the correct voltage option is selected. The voltage ranges of 90 to 120 Vac and 180 to 240 Vac will use
less than 4 A operating. The voltage ranges of 100—132 Vac and 200—264 Vac will use less than 2 A. Both versions
of the RX01 will be required to receive the input power from an ac source (e.g., 861 power control) that is
controlled by the system’s power switch.
2-1

TTITTE

10.5"

REERER AR

AN | 1

(26.7¢cm)

]9Il

(48.3 cm)
(FRONT VIEW)

17.0"
(43.2 cm)

—_

(FRONT)

L_©

/SEE

NOTE

/-INSIDE TRACK

C—

26.5"
(66.3 cm)
SIDE VIEW)
NOTE

Dust cover attached to cabinet
not

RXO1.

CP-1811

Figure 2-1

2.2.3.2

RXO01

Input Power Modification Requirements — The 60 Hz version of the RX01 uses the H771
A power supply

and will operate on 90 to 132 Vac, without modification. To convert to operate on a 50 Hz power source in the

field, the H771A supply must be replaced with an H771C or D (Figure 1-5) and the drive motor belt and drive
motor pulley must be replaced (Figure 1-6). The 50 Hz version of the RX01 uses either the H771C or D power
supply. The H771C

operates

on a 90—120 Vac or

100—132 Vac power source.

The H771D operates on a

180—-240 Vac or 200—264 Vac power source. To convert the H771C to the higher voltage ranges or the H771D to

the lower voltage ranges, the power harness and circuit breaker must be changed. See Figure 2-3 for appropriate
power harness and circuit breaker.
2.2.4

Fire and Safety Precautions

The RX8/RX11 Floppy Disk System presents no additional fire or safety hazards to an existing computer system.
Wiring should be carefully checked, however, to ensure that the capacity is adequate for the added load and for any
contemplated expansion.
2.3

2.3.1

ENVIRONMENTAL CONSIDERATIONS

General

The RX8/RX11 is capable of efficient operation in computer environments; however, the parameters of the
operating environment must be determined by the most restrictive facets of the system, which in this case are the

diskettes.

2-2

TTEEEE

SWINGING DOOR
R.H. OR L.H.
MOUNTING

SWINGING

DOOR R.H OR L.H.

FRAME

yod

4\2\<\\X\

ANN

//”

18 74

N\\

(46.35¢cm)

\\
\

|‘\

—

REMOVABLE

/ END PANEL
REMOVABLE

END

PANEL

CABLE

-7

\
‘\‘1
|

ACCESS
—
|

|
A

/) |

RADIUS 2'%35"

(122.47¢m)
FAN

PORTS

(76.2¢cm)
LEVELER

4 PLACES

n
+‘/a

q'\\._.//

CASTER SWIVEL

487/32"

)

;'1

RXO1 EXTENDED

}r"l

21 e

(6.12cm)

(4) CASTERS

I
|

FROM CABINET

L e e o o

(48.26 cm)

I
I
I

high
CABINET 717 (182.28c¢m)
(floor line to cabinet top)

CP-1612

Figure 2-2

2.3.2

Cabinet Layout Dimensions

Temperature, Relative Humidity

The operating ambient temperature range of the diskette is 59° to 90° F (15° to 32° C) with a maximum

temperature gradient of 20° F/hr (-6.7° C/hr).

The media nonoperating temperature range (storage) is increased to ~30° to 125° F (-34.4° to 51.6° C), but care

must be taken to ensure that the media has stabilized within the operating temperature range before use. This range
will ensure that the media will not be operated above its absolute temperature limit of 125° F.

Humidity control is important in any system because static electricity can cause errors in any CPU with memory.

The RXO01 is designed to operate efficiently within a relative humidity range of 20 to 80 percent, with a maximum

wet bulb temperature of 77° F (25° C) and a maximum dew point of 36° F (2° C).
2.3.3

Heat Dissipation

The heat dissipation factor for the RX01 Floppy Disk System is less than 225 Btu/hr. By adding this figure to the
total heat dissipation for the other system components and then adjusting the result to compensate for such factors

as the number of personnel, the heat radiation from adjoining areas, and sun exposure through windows, the
approximate cooling requirements for the system can be determined. It is advisable to allow a safety margin of at

least 25 percent above the maximum estimated requirements.
2.3.4

Radiated Emissions

Sources of radiation, such as FM, vehicle ignitions, and radar transmitters located close to the computer system, may

affect the performance of the RX8/RX11 Floppy Disk System because of the possible adverse effects magnetic
fields can have on diskettes. A magnetic field with an intensity of 50 oersteds or greater might destroy all or some of
the information recorded on the diskette.
2.3.5

Cleanliness

Although cleanliness is important in all facets of a computer system, it is particularly important in the case of
moving magnetic media, such as the RX01. Diskettes are not sealed units and are vulnerable to dirt. Such minute

obstructions as dust specks or fingerprint smudges may cause data errors. Therefore, the RX01 should not be
subjected to unusually contaminated atmospheres, especially one with abrasive airborne particles. (Refer to
Paragraph 2.5.2.)
NOTE

Removable

media

which

beyond

are

involve use, handling, and maintenance

DEC’s

direct control.

DEC

disclaims

responsibility for performance of the equipment when oper-

ated with media not meeting DEC specifications or with media
not maintained in accordance with procedures approved by
DEC. DEC shall not be liable for damages to the equipment or

to media resulting from such operation.
24

INSTALLATION

2.4.1

General

The RX8/RX11 Floppy Disk System can be shipped in a cabinet as an integral part of a system or in a separate
container. If the RXO01 is shipped in a cabinet, the cabinet should be positioned in the final installation location

before proceeding with the installation.
2.4.2

Tools

Installation of an RX8/RX11 Floppy Disk System requires no special tools or equipment. Normal hand tools are all
that are necessary. However, a forklift truck or pallet handling equipment may be needed for receiving and installing
a cabinet-mounted system.
2.4.3

Unpacking and Inspection

2.4.3.1

Cabinet-Mounted

Remove the protective covering over the cabinet.

Remove the restraint on the rear door latch and open the door.

Remove the two bolts on the cabinet’s lower side rails that attach the cabinet to the pallet.

Raise the four levelers at the corners of the cabinet, allowing the cabinet to roll on the casters.

Carefully roll the cabinet off the pallet; if a forklift is available, it should be used to lift and move the
cabinet.

Remove the shipping restraint from the RX01 and save it for possible reuse (Figure 2-3).

Slide the RX01 out on the chassis slides and visually inspect for any damage, loose screws, loose wiring,
etc.

NOTE

If any shipping damage is found, the customer should be
notified at this time so he can contact the carrier, and record
the information on the acceptance form.

JUMPER P1

SHIPPING

FILTER

POWER PLUGS

FILTER

RESTRAINT (RED)
7436-12

VOLTAGE (Vac)
90—120
100—132
180—240
200—-264

POWER HARNESS
70-10696-02
70-10696-01
70-10696-04
70-10696-03

Figure 2-3

CIRCUIT BREAKER
3.5A,12-12301-01

3.5 A, 12-12301-01
1.75 A, 12-12301-00
1.75 A, 12-12301-00

RXO01 Shipping Restraints

2.4.3.2

Separate Container

Open the carton (Figure 2-4) and remove the corrugated packing pieces.

Lift the RXO01 out of the carton and remove the plastic shipping bag.

Remove the shipping fixtures from both sides of the RXO01 and inspect for shipping damage.

Attach the inside tracks of the chassis slides provided in the carton to the RX01 (Figure 2-1).

Locating the proper holes
in the cabinet rails (Figure 2-5), attach the outside tracks to the cabinet.

Place the tracks attached to the RXO01 inside the extended cabinet tracks and slide the unit in until the
tracks lock in the extended position.

244

Locate the RXO01 cover in the cabinet above the unit and secure it to the cabinet rails (Figure 2-3).

Installation
1.

Loosen the screws securing the upper module (M7726) and swing it up on the hinge.

Inspect the wiring and connectors for proper routing and ensure that they are seated correctly.

This step is for 50 Hz versions only. Check the power configuration to ensure that the proper power

harness and the correct circuit breaker are installed (Figure 2-3).
4.

Connect the BCOSL-15 cable to the M7726 module and route it through the back of the RX01 (Figure

2-6) to the CPU, then connect it to the interface module (RX8E, M8357; RX11, M7846).

Refer to Table 2-1 for correct device code or addressing jumpers.

Ensure that power for the system is off.

Insert the interface module into the Omnibus (RX8E) or available SPC slot (RX11). (Refer to PDP-11

Processor Handbook, Specifications, Chapter 9.)
8.

Connect the RX01 ac power cord into a switched power source.

Turn the power on, watching for head movement on the drive(s) during the power up, initialize phase.
The head(s) should move ten tracks toward the center and back to track 0.

10.

Perform the diagnostic in the sequence listed below for the number of passes (time) indicated. If any
errors occur, refer to Chapter 6 for corrective action.

RX8 or RX11 Diagnostic — 2 passes

Data Reliability /Exerciser — 3 passes
DECX-8 or DECX-11

— 10 minutes

2-6

SLIDES

ONE PIECE
FOLDER

9905711

PLYWOOD
FIXTURE

HOLDING
RT.SIDE
9905712-01
\

FOLDER

9905128-41

9905714
PLYWOOD HOLDING

FIXTURE

LT SIDE

\—/9905712-00
RXOI

FLAT WASHER (8)
5\@/ 90- 09024-00

LOCK WASHER

(8)

90-07906-00

%m\\\\\SCREW(B)

90-06076-01

SCORED
SHEET
9905713

REGULAR
CARTON

SLOTTED

9905710

SHIPPING
CARTON

CP-1596

Figure 2-4

RX8/RX11 Unpacking

_ COVER

®
)
®

SCREWS,

17 CHASSIS SLIDES

CP-1594

Figure 2-5

2.5

2.5.1

RXO01 Cabinet Mounting Information

OPERATION

Operator Control

The simplicity of the RXO01 precludes the necessity of operator controls and indicators. A convenient method of
opening the unit for diskette insertion and removal is provided. On each drive is a simple pushbutton, which is
compressed to allow the spring-loaded front cover to open. The diskette may be inserted or removed, as shown in
Figure 2-7, with the label up. The front cover will automatically lock when the bar is pushed down.
CAUTION

The drive(s) should not be opened while they are being
accessed because data may be incorrectly recorded, resulting in
a CRC error when the sector is read.
2.5.2

Diskette Handling Practices and Precautions

To prolong the diskette life and prevent errors when recording or reading, reasonable care should be taken when
handling the media. The following handling recommendations should be followed to prevent unnecessary loss of
data or interruptions of system operation.

Do not write on the envelope containing the diskette. Write any information on a label prior to affixing
it to the diskette.

Paper clips should not be used on the diskette.

Do not use writing instruments that leave flakes, such as lead or grease pencils, on the jacket of the
media.

2-8

M7726

BCO5L-15

M7727

7436-18

Figure 2-6

Cable Routing, BCOSL-15

Table 2-1

Interface Code/Jumper Configuration

RX11 (M7846)

BR Priority
BR7 — 54-08782
BR6 — 54-08780
*BRS — 5408778
BR4 — 57-08776

RXS8E (M8357)

Device Codes

SW1 | SW2 | SW3 | SW4 | SW5 | SWé6
*670X
671X
672X
673X
674X
675X
676X
677X

ON
ON
ON
ON
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
ON
ON
OFF
OFF

ON
OFF
ON
OFF
ON
OFF
ON
OFF

OFF
OFF
OFF
OFF
ON
ON
ON
ON

OFF
OFF
ON
ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF
ON
OFF
ON

*Unibus Address 17717X
A12/W18 — Removed

Al11/W17 — Removed
A10/W16 — Removed
A9/W15 — Removed
A8/W14 — Installed
A7/W13 — Installed
A6/W12 — Removed
A5/W11 — Removed
A4/W10 — Removed
A3/W9 — Removed

*Vector Address (26453 )

V2/W1 — Installed

V3/W2 — Installed
V4/W3 — Removed
V5/W4 — Installed
V6/W5 — Removed
V7/W6 — Installed
V8/W7 — Removed

*Standard

2-10

Figure 2-7

Flexible Diskette Insertion

Do not touch the disk surface exposed in the diskette slot or index hole.
Do not clean the disk in any manner.

Keep the diskette away from magnets or tools that may have become magnetized. Any disk exposed to a
magnetic field may lose information.

Do not expose the diskette to a heat source or sunlight.

Always return the diskette to the envelope supplied with it to protect the disk from dust and dirt.

Diskettes not being used should be stored in the file box if possible.

When the diskette is in use, protect the empty envelope from liquids, dust, and metallic materials.
10.

Do not place heavy items on the diskette.

11.

Do not store diskettes on top of computer cabinets or in places where dirt can be blown by fans into the
diskette interior.

12.

If a diskette has been exposed to temperatures outside of the operating range, allow 5 minutes for
thermal stabilization before use. The diskette should be removed from its packaging during this time.

2.5.3

Diskette Storage

2.5.3.1

Short Term (Available for Immediate Use)

Store diskettes in their envelopes.

Store horizontally, in piles of ten or less. If vertical storage is necessary, the diskettes should be
supported so that they do not lean or sag, but should not be subjected to compressive forces. Permanent
deformation may result from improper storage.

Store in an environment similar to that of the operating system; at a minimum, store within the
operating environment range.

2.5.3.2

Long Term — When diskettes do not need to be available for immediate use, they should be stored in their

original shipping containers within the nonoperating range of the media.
2.5.4

Shipping Diskettes

Data recorded on disks may be degraded by exposure to any sort of small magnet brought into close contact with
the disk surface. If diskettes are to be shipped in the cargo hold of an aircraft, take precautions against possible
exposure to magnetic sources. Because physical separation from the magnetic source is the best protection against

accidental erasure of a diskette, diskettes should be packed at least 3 in. within the outer box. This separation should
be adequate to protect against any magnetic sources likely to be encountered during transportation, making it
generally unnecessary to ship diskettes in specially shielded boxes.

When shipping, be sure to label the package:
DO NOT EXPOSE TO PROLONGED HEAT OR SUNLIGHT.

When received, the carton should be examined for damage. Deformation of the carton should alert the receiver to
possible damage of the diskette. The carton should be retained, if it is intact, for storage of the diskette or for future
shipping.

2-12

CHAPTER 3

RX11 INTERFACE

PROGRAMMING INFORMATION
This chapter describes device registers, register and vector address assignments, programming specifications, and

programming examples for the RX11 interface.

All software control of the RX11 is performed by means of two device registers: the RX11 Command and Status
register (RXCS) and a multipurpose RX11 Data Buffer register (RXDB). These registers have been assigned bus
addresses and can be read or loaded, with certain exceptions, using any instruction referring to their addresses.

The RX01, which includes the mechanical drive(s), read/write electronics, and uCPU controller, contains all the
control circuitry required for implied seeks, automatic head position verification, and calculation and verification of
the CRC; it has a buffer large enough to hold one full sector of diskette data (128 8-bit bytes). Information is
serially passed between the interface and the RX01.

A typical diskette write sequence, which is initiated by a user program, would occur in two steps:

Fill Buffer — A command to fill the buffer is moved into the RXCS. The Go bit (Paragraph 3.2.1) must
be set. The program tests for Transfer Request (TR). When TR is detected, the program moves the first
of 128 bytes of data to the RXDB. TR goes false while the byte is moved into the RX01. The program

retests TR and moves another byte of data when TR is true. When the RXO01 sector buffer is full, the
Done bit will set, and an interrupt will occur if the program has enabled interrupts.

Write Sector — A command to write the contents of the buffer onto the disk is issued to the RXCS.

Again the Go bit must be set. The program tests TR, and when TR is true, the program moves the
desired sector address to the RXDB. TR goes false while the RX01 handles the sector address. The
program again waits for TR and moves the desired track address to the RXDB, and again TR is negated.
The RXO01 locates the desired track and sector, verifies its location, and writes the contents of the sector
buffer onto the diskette. When this is done, an interrupt will occur if the program has enabled interrupts.

A typical diskette read occurs in just the reverse way: first locating and reading a sector into the buffer (Read
Sector) and then unloading the buffer into core (Empty Buffer). In either case, the content of the buffer is not valid

if Power Fail or Initialize follows a Fill Buffer or Read Sector function.
3.1

The RXCS register is normally assigned Unibus address 177170, and the RXDB register is assigned Unibus address
177172. The normal BR priority level is 5, but it can be changed by insertion of a different priority plug located on

the interface module. The vector address is 264.

3-1

3.2

3.2.1

RXCS — Command and Status (177170)

Loading this register while the RX01 is not busy and with bit 0 =1 will initiate a function as described below and

indicated in Figure 3-1. Bits 0—4 write-only bits.

—

—_—

NOT USED

ERROR

—

RX
INIT

—_—

FUNCTION

DONE
INT
ENB

UNIT
SEL
CP-1509

Figure 3-1

RXCS Format (RX11)

Bit No.
0
1-3

Description
Go — Initiates a command to RX01. This is a write-only bit.
Function Select — These bits code one of the eight possible functions described in Paragraph

3.3 and listed below. These are write-only bits.
Code

Function

000

Fill Buffer

001

Empty Buffer

010

Write Sector

011

Read Sector

100

Not used

101

Read Status

110

Write Deleted Data Sector

111

Read Error Register

Unit select — This bit selects one of the two possible disks for execution of the desired

function. This is a write-only bit.
5

Done — This bit indicates the completion of a function. Done will generate an interrupt

when asserted if Interrupt Enable (RXCS bit 6) is set. This is a read-only bit.
6

Interrupt Enable — This bit is set by the program to enable an interrupt when the RX01 has

completed an operation (Done). The condition of this bit is normally determined at the time

a function is initiated. This bit is cleared by Initialize and is a read/write bit.
7

Transfer Request — This bit signifies that the RX11 needs data or has data available. This is a

read-only bit.
8—13

Unused

3-2

Bit No.

Description

RX11 Initialize — This bit is set by the program to initialize the RX11 without initializing all
of the devices on the Unibus. This is a write-only bit.
CAUTION

Loading the lower byte of the RXCS will also load the upper
byte of the RXCS.

Upon setting this bit in the RXCS, the RX11 will negate Done and move the head position
mechanism of drive 1 (if two are available) to track 0. Upon completion of a successful
Initialize, the RXO01 will zero the Error and Status register, set Initialize Done, and set RXES
bit 7 (DRV RDY) if unit O is ready. It will also read sector 1 of track 1 on drive O.
15

Error — This bit is set by the RX01 to indicate that an error has occurred during an attempt
to execute a command. This read-only bit is cleared by the initiation of a new command or
an Initialize (Paragraph 3.6).

3.2.2

RXDB — Data Buffer Register (177172)

This register serves as a general purpose data path between the RX01 and the interface. It may represent one of four
RXO01 registers according to the protocol of the function in progress (Paragraph 3.3).
This register is read/write if the RX01 is not in the process of executing a command; that is, it may be manipulated
without affecting the RXO01 subsystem. If the RXO01 is actively executing a command, this register will only accept
data if RXCS bit 7 (TR) is set. In addition, valid data can only be read when TR is set.
CAUTION

Violation of protocol in manipulation of this register may
cause permanent data loss.

3.2.2.1

RXTA — RX Track Address (Figure 3-2) — This register is loaded to indicate on which of the 1144 tracks a

given function is to operate. It can be addressed only under the protocol of the function in progress (Paragraph 3.3).
Bits 8 through 15 are unused and are ignored by the control.

NOT USED

O-114g
CP-1510

Figure 3-2

3.2.2.2

RXTA Format (RX11)

RXSA — RX Sector Address (Figure 3-3) — This register is loaded to indicate on which of the 325 sectors a

given function is to operate. It can be addressed only under the protocol of the function in progress (Paragraph 3.3).
Bits 8 through 15 are unused and are ignored by the control.
15

—_—

NOT USED

1-32¢
CP-151

Figure 3-3

RXSA Format (RX11)
3-3

3.2.2.3 RXDB — RX Data Buffer (Figure 3-4) — All information transferred to and from the floppy media passes

through this register and is addressable only under the protocol of the function in progress (Paragraph 3.3).

NOT USED

cP-1512

Figure 34

RXDB Format (RX11)

3.2.2.4 RXES — RX Error and Status (Figure 3-5) — This register contains the current error and status conditions

of the drive selected by bit 4 (Unit Select) of the RXCS. This read-only register can be addressed only under the
protocol of the function in progress (Paragraph 3.3). The RXES is located in the RXDB upon completion of a
function.

DRV

RDY

~—

)

NOT USED

PAR | CRC

)

NOT USED
CP -1513

Figure 3-5

RXES Format (RX11)

RXES bit assignments are:

Description

Bit No.

CRC Error — A cyclic redundancy check error was detected as information was retrieved
from a data field of the diskette. The RXES is moved to the RXDB, and Error and Done are
asserted.

Parity Error — A parity error was detected on command or address information being
transferred to the RX01 from the Unibus interface. A parity error indication means that
there is a problem in the interface cable between the RXO01 and the interface. Upon
detection of a parity error, the current function is terminated; the RXES is moved to the
RXDB, and Error and Done are asserted.

Initialize Done — This bit is asserted in the RXES to indicate completion of the Initialize
routine which can be caused by RX01 power failure, system power failure, or programmable
or Unibus Initialize.
Unused

Deleted Data Detected — During data recovery, the identification mark preceding the data

field was decoded as a deleted data mark (Paragraph 1.3.3).

Bit No.

Description

Drive Ready — This bit is asserted if the unit currently selected exists, is properly supplied

with power, has a diskette installed correctly, has its door closed, and has a diskette up to
speed.

NOTE 1

The Drive Ready bit is only valid when retrieved via a Read
Status function or at completion of Initialize when it indicates
status of drive 0.
NOTE 2

If the Error bit was set in the RXCS but Error bits are not set
in the RXES, then specific error conditions can be accessed via
a Read Error Register function (Paragraph 3.3.7).
3.3

FUNCTION CODES

Following the strict protocol of the individual function, data storage and recovery on the RX11 occur with careful
manipulation of the RXCS and RXDB registers. The penalty for violation of protocol can be permanent data loss.
A summary of the function codes is presented below:
000

Fill Buffer

001

Empty Buffer

010

Write Sector

011

Read Sector

100

Not used

101

110

Read Status
Write Deleted Data Sector

111

Read Error Register

The following paragraphs describe in detail the programming protocol associated with each function encoded and
written into RXCS bits 1—3 if Done is set.
3.3.1

Fill Buffer (000)

This function is used to fill the RX01 buffer with 128 8-bit bytes of data from the host processor. Fill Buffer is a
complete function in itself; the function ends when the buffer has been filled. The contents of the buffer can be
written onto the diskette by means of a subsequent Write Sector function, or the contents can be returned to the
host processor by an Empty Buffer function.

RXCS bit 4 (Unit Select) does not affect this function, since no diskette drive is involved. When the command has
been loaded, RXCS bit 5 (Done) is negated. When the TR bit is asserted, the first byte of the data may be loaded
into the data buffer. The same TR cycle will occur as each byte of data is loaded. The RX01 counts the bytes
transferred; it will not accept less than 128 bytes and will ignore those in excess. Any read of the RXDB during the
cycle of 128 transfers is ignored by the RX11.
3.3.2

Empty Buffer (001)

This function is used to empty the internal buffer of the 128 data bytes loaded from a previous Read Sector or Fill
Buffer command. This function will ignore RXCS bit 4 (Unit Select) and negate Done.

3-5

When TR sets, the program may unload the first of 128 data bytes from the RXDB. Then the RX11 again negates
TR. When TR resets, the second byte of data may be unloaded from the RXDB, which again negates TR. Alternate

checks on TR and data transfers from the RXDB continue until 128 bytes of data have been moved from the RXDB.
Done sets, ending the operation and initiating an interrupt if RXCS bit 6 (Interrupt Enable) is set.
NOTE

The Empty Buffer function does nor destroy the contents of
the sector buffer.
3.3.3

Write Sector (010)

This function is used to locate a desired track and sector and write the sector with the contents of the internal sector

buffer. The initiation of this function clears bits 0, 1, and 6 of RXES (CRC Error, Parity Error, and Deleted Data
Detected) and negates Done.

When TR is asserted, the program must move the desired sector address into the RXDB, which will negate TR. When

TR is again asserted, the program must load the desired track address into the RXDB, which will negate TR. If the
desired track is not found, the RX11 will abort the operation, move the contents of the RXES to the RXDB, set

RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
TR will remain negated while the RX01 attempts to locate the desired sector. If the RX01 is unable to locate the
desired sector within two diskette revolutions, the RX11 will abort the operation, move the contents of the RXES
to the RXDB, set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
If the desired sector is successfully located, the RX11 will write the 128 bytes stored in the internal buffer followed

by a 16-bit CRC character that is automatically calculated by the RX01. The RX11 ends the function by asserting
Done and initiating an interrupt if RXCS bit 6 (Interrupt Enable) is set.
NOTE 1

The contents of the sector buffer are not valid data after a
power loss has been detected by the RX01. The Write Sector
function, however, will be accepted as a valid function, and

the random contents of the buffer will be written, followed by
a valid CRC,
NOTE 2

The Write Sector function does nor destroy the contents of
the sector buffer.
3.3.4

Read Sector (011)

This function is used to locate a desired track and sector and transfer the contents of the data field to the uCPU
controller sector buffer. The initiation of this function clears bits 0, 1, and 6 of RXES (CRC Error, Parity Error,
Deleted Data Detected) and negates Done.

When TR is asserted, the program must load the desired sector address into the RXDB, which will negate TR. When
TR is again asserted, the program must load the desired track address into the RXDB, which will negate TR.
If the desired track is not found, the RX11 will abort the operation, move the contents of the RXES to the RXDB,

set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.

3-6

TR and Done will remain negated while the RXO01 attempts to locate the desired track and sector. If the RXO01 is
unable to locate the desired sector within two diskette revolutions after locating the presumably correct track, the
RX11 will abort the operation, move the contents of the RXES to the RXDB, set RXCS bit 15 (Error), assert Done,
and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.

If the desired sector is successfully located, the control will attempt to locate a standard data address mark or a
deleted data address mark. If either mark is properly located, the control will read data from the sector into the
sector buffer.

If the deleted data address mark was detected, the control will assert RXES bit 6 (DD). As data enters the sector
buffer, a CRC is computed, based on the data field and CRC bytes previously recorded. A non-zero residue indicates
that a read error has occurred. The control sets RXES bit 0 (CRC Error) and RXCS bit 15 (Error). The RX11 ends
the operation by moving the contents of the RXES to the RXDB, sets Done, and initiates an interrupt if RXCS bit 6
(Interrupt Enable) is set.
3.3.5

Read Status (101)

The RX11 will negate RXCS bit 5 (Done) and begin to assemble the current contents of the RXES into the RXDB.
RXES bit 7 (Drive Ready) will reflect the status of the drive selected by RXCS bit 4 (Unit Select) at the time the
function was given. All other RXES bits will reflect the conditions created by the last command. RXES may be
sampled when RXCS bit 5 (Done) is again asserted. An interrupt will occur if RXCS bit 6 (Interrupt Enable) is set.
RXES bits are defined in Paragraph 3.2.2.

NOTE

The average time for this function is 250 ms. Excessive use of
this function will result in substantially reduced throughput.
3.3.6 Write Sector with Deleted Data (110)

This operation is identical to function 010 (Write Sector) with the exception that a deleted data address mark

precedes the data field instead of a standard data address mark (Paragraph 1.3.3.2).
3.3.7

Read Error Register Function (111)

The Read Error Register function can be used to retrieve explicit error information provided by the uCPU controller
upon detection of the general error bit. The function is initiated, and bits 0—6 of the RXES are cleared. Out is
asserted and Done is negated. The controller then generates the appropriate number of shift pulses to transfer the
specific error code to the Interface register and completes the function by asserting Done. The Interface register can
now be read and the error code interrogated to determine the type of failure that occurred (Paragraph 3.6).
NOTE

Care should be exercised in use of this function since, under
certain conditions, erroneous error information may result
(Paragraph 3.5).
3.3.8

Power Fail

There is no actual function code associated with Power Fail. When the RXO01 senses a loss of power, it will unload

the head and abort all controller action. All status signals are invalid while power is low.

When the RX01 senses the return of power, it will remove Done and begin a sequence to:
1.

Move drive 1 head position mechanism to track O.

Clear any active error bits.

3-7

Read sector 1 of track 1 of drive O into the sector buffer.

Set RXES bit 21 (Initialize Done) (Paragraph 3.2.2) after which Done is again asserted.

Set Drive Ready of the RXES according to the status of drive O.

There is no guarantee that information being written at the time of a power failure will be retrievable. However, all
other information on the diskette will remain unaltered.

A method of aborting a function is through the use of RXCS bit 14 (RX11 Initialize). Another method is through
the use of the system Initialize signal that is generated by the PDP-11 RESET instruction, the console START key,
or system power failure.
3.4

3.4.1

PROGRAMMING EXAMPLES

Read Data/Write Data

Figure 3-6 presents a program for implementing a Write, Write Deleted Data, or a Read function, depending on the

function code that is used. The first instructions set

up the error retry counters, PTRY, CTRY, and STRY. The

instruction RETRY moves the command word for a Write, Write Deleted Data, or Read into the RXCS.

The set of three instructions beginning at the label 1$ moves the sector address to the RX11 after Transfer Request

(TR), which is bit 7, has been set. The three instructions beginning at the label 2$ move the track address to the
RX11 after TR has been set. The group of instructions beginning at the label 3$ looks for the Done flag to set and

checks for errors.
An error condition, indicated by bit 15 setting, is checked beginning at ERFLAG. If bit O is set, a CRC error has

occurred, and a branch is made to CRCER. If bit 1 is set, a parity error has occurred, and a branch is made to
PARER. If neither of the above bits is set, a seek error is assumed to have occurred and a branch is made to
SEEKER, where the system is initialized. In the case of a Write function, the sector buffer is refilled by a JMP to
FILLBUF. In the case of a Read function, a JMP is made to EMPBUFF.
In each of the PAR, CRC, and SEEK routines, the command sequence is retried ten times by decrementing the
respective retry counter. If an error persists after ten tries, it is a hard error. The retry counters can be set up to retry

as many times as desired.

NOTE
A Fill Buffer function is performed before a Write function,
and an Empty Buffer function is performed after a Read

function.

3.4.2

Empty Buffer Function

Figure 3-7 shows a program for implementing an Empty Buffer function. The first instruction sets the number of
error retries to ten. The address of the memory buffer is placed in register RO, and the Empty Buffer command is
placed in the RXCS. Existence of a parity error is checked starting at instruction 38§. If a parity error is detected, the
Empty Buffer command is loaded again. If an error persists for ten retries, the error is considered hard.

3-8

T ETRRE

vABS

JP<OGRAMMING EXAMPLES FOR THE RX41/R¥@{ FLEXIBLE DISKETTE

JTHE FOLLQWING 1S THE RX11i STANDARD DEVICE ADDRESS AND VECTQR ADDRESS
]

}

VOO

[

pee000
poEGED6
epPE14

012767
12767
012767

;
;
;
;
;

RXCS®177178
RXDBw177172
RXSAs4177172
RXTA®177172
RXES:177172

177470
177472
177172
177472
177472

COMMAND STATUS REGISTER
DAYA BUFFER REGISTER
SECTOR ADORESS REGISTER
TRACK ADORESS REGISTER
ERROR 8TATUS REGISTER

THE PROTOCOL REQUIRED
:THE FOLLOWING ISA PROGRAMMING EXAMPLE.AY gF
SEETOR "§" (THE CONTENTS OF PROGRAM
}TO0 WRITE, WRITE DELETED DATA, OR READ
JLOCATION SBECTOR) OF TRACK "T" (THE CONTENTS OF PROGRAM LOCATION TRACK)

17777@
177770
177773

gpe320

pPB3IL4

}

START!

ppo3ig

MoV #=10, PTRY

#=10, CTRY
MOV #e1@, STRY

; PAR]TY RETRY CQUNTER

i CRC RETRY EOUNTER
3 SBEEK RETRY COUNTER

}

;WRITE, WRITE DELETED DATA, oR READ

BITS 4 THRU L oF PRQGRAM LOCATIQN CoMMAND GONTAIN THE FUNCTION
BIT 4 & 4 MEANS UNIT 1 ( ® @ MEANS UNIT 8)

}

i
}

} BITS 3 THRU 4 I3 THE COMMAND ( 4 ® WRITE, 14 s WRITE DELETED DAYA, 6 = READ)

ppop22

216767

JO0306

gpee30

gpop34
e00B36

188767
go177%
116767

0308274

pe0044
pBe050
6060852

108767
201775
116767

177140

}
R

ETRY!

177134
177126

}

pRB262

; UNLIY ¢ (WRITE, WRITE DELETED DATA, OR READ)

MOVB SECTOR, RXSA

; LOAD SECTOR ADDRESS

TSTB RXCS
BEQ 2%

i TESY F?R THE TRANSFER REQUEST FLAG
; BEO UNYIL THE TRANSFER REQUEST FLAG SETS

'WALT FoR THE TRANSFER REQUEST FLAG THEN TRANSFER THE TRACK ADDRESS
2§

177129

MoV COMMAND, RXCS

;WAIT FOR THE TRANSFER REQUEST FLAG THEN TRANSFER THE BECTOR ADDRESS
i
; TESY FgR THE TRANSFER REQUESY FLAG
TSTB RXCS
1§}
; BE® UNTIL THE TRANSFER REQUEST FLAG SETS
BEQ 1§
}

MOVB TRACK, RXTA

177112

; LOAD TRACK ADDRESS

JTHE SECTQR AND TRACK ADDRESSES HAVE BEEN TRANSFERRED To THE RXBY
]
}

aNSAIT FQR THE DONE FLAG AND CHECK FgR ANY ERRORS

xIF THE FUNCTIQN HAS CoMPLETED SUCCESSFULLY (No ERRQR FLAG) THEN HALY

200069
000066
200870
goPB74
poea7é

p32767
201774
0058767

pp1001
goo000

0poo4n

177102

3sx

BIT #DQNEBIT, RXCS
BEQ 3§

F
; TEST FgR THE DQNE
; BEQ UNTIL YHE DONE FLAG SETS

BNE ERFLAG

; BNE IF AN ERROR HAS OCCURED

TST RXCS

177074

; TEST FOR TWE ERROR FLAG
; OK = GOMPLETED

HALT

$THE ERROR FLAG 1§ SET
i

JTHE GCONTENTS OF THE RXES ]S THE ERROR STATU®

THEN SQME YYPE OF SEEK ERROR 0CCURED
;IF THE RXES BITS 1 AND @ ® ¢A CRC
ERROR HAS OCCURED
JIF THE RXES BIT @ = 1 THEN
JIF THE RXES BIT 4 = 1 THEN A PARITY ERROR HAS OCCURED

ERFLAG! BT #3, RXES
BEQ SEEK
]

608100

goBL06

020110
poBLL6

p32767
001414
032767
@01404

oneees

177064

0Qe002

177054

BIT #2, RXES

BEQ CRC

; TEST FOR CRC AND PAR]TY ERRORS
; NOY A PARITY OR GRC CHUSTJ BE A SEEK
; TESY FOR PARITY ERRO
i NOY A PARITY ERROR CHUBTJ BE A CRC

’

}A PARITY ERROR HAS OCCURED

} INCREMENT AND TEST THE PARITY ERROR RETRY COUNTER PROGRAM LOCATIPQN " PTRY "

}

JAND RETRY THE " COMMAND " UNTIL THE PARITY ERRQR RECOVERS

}

JgR UNTIL THE PTRY COUNTER OVERFLOHWS Yo 8

pe0120
peaL24
peBL26

005267
pE1336
pooo00

ING PTRY

200202

; RETRY THE GOMMAND
; HARD PARITY ERROR

BNE RETRY
HALT
]

’
.

’

}

A CRC ERRQR HAS QCCURED

INGREMENT AND TEST THE CRC ERRQR RETRY COUNTER PROGRAM LOCATION TM CTRY

' AND RETRY THE COMMAND UNTIL THE CRC ERROR RECOVERS
;oa UNTIL THE CTRY CoUNTER QVERFLONWS To @
pepL30
p0P134
PE01L36

005267
gp1332
poeoeoo

CRCI

0g08L74

INC CTRY

; RETRY THE GOMMAND

BNE RETRY

; HARD CRC ERROR

HALT

i THE ERROR FLAG 18 SET
i

;THE ERROR IS [NoTI A PARITY ERROR AND 18 UNpTJ) A CRC ERROR

:THEREFQRE IT MUST BE A SEEK ERROR
p00140

012767

p40000

177022

(STATE oF RXCS BITS @ AND 1 ARE 8)

?EEK:

Mov #INIT, RXCS

i INITIALIZE

EINCREMENT AND TEST THE SEEK ERROR RETRY COUNTER PRQGRAM LOCATIQN TM STRY "
;AND RETRY THE CoMMAND UNTIL THE SEEK ERRQR RECQVERS
i

JOR UNTIL THE CTRY COUNTER QVERFLOQWS To 0
i

pPB146
peB152

gPD154

pp5267
@P1323
000800

0160

INC STRY

; RETRY THE EGOMMAND

BNE RETRY

; HARD SEEK ERROR

HALY

Figure 3-6

RX11 Write/Write Deleted Data/Read Example

3-9

THREE

iTHE FOLLOWING

IS A PROGRAMMING EXAMPLE

OF PROTOCOL REQUIRED TO

177779
000342
0aoo54

Pp0E56

176706

EENTRY!
ESETUP:

#=10, PTRY
#BUFFER, RO
COMMAND, RXCS

IWAIT

MoV
MOV
MOV

FQR

TRANSFER

JDATA BUFFER FRON THE

oF 128

8<B!T BYTES
we

212767
12700
216767

SECTOR BUFFER

gPB242
006250
pP0254

JEMPTY THE

;

REQUEST

FLAG

8 TRYS To EMPTY THE SECTOR BUFFER
PROHGRAMS DATA BUFFER

1SSUE THE GOMMAND
BEFQRE

TRANSFERRING

DATA

THE

PROGRAMS

RX®1 SECTQR BUFFER

iWAIT FQR A DQNE FLAG Tg INDICATE THE CoMpLETIQN oF THE EMPTY BUFFER CQMMAND
’

JPRIOR To
PBE262
gBB266
200270
po@a276

108767

01014
232767
201774

200040

ELOQP!

TSTB

;TEST FoR
176664

THE ERROR

BIT #DONEBIT,
BEQ ELOOP

iTHE DONE

205767
p01001
gopoon

RXCS

BNE EMPTY

176672
}

epa3ne
08304
paB306

TESTIN

FLAG

}

176702

FLAG

RXCS

;

TESY

;

BNE

;
;

FOR

TRANSFER

REQUEST

FLAG

IF TRANSFER REQUEST FLAG

TEST FOR DONE FLAG
BED UNTIL THE DONE FLAG

1§ SET

SETS

IS SET

ANY ERRQRS

(ONLY ERROR POSSIBLE

A PARITY ERRQR)

TST
BNE

HALT

RXCS
1§

;

) INCFEMENT AND TEST THE

|
NO ERRORS = OK = COMPLETE

PARITY ERROR RETRY PRQGRAM LQGCATIQN "

pTRY TM

JAND RETRY THE CoMMAND UNTIL THE ERRpR RECOVERS
i

JOR UNTIL

THE PTRY

CUNTER

QVERFLOWS

To @

’

go6310
PP@a314
'PPB3IL6

005267
001355
gpopog

paeo12

INC

PTRY

BNE ESETUP

;

HALT

;

RETRY YO0 EMPTY THE SECTOR BUFFER

HARD PARITY ERROR

)

}THE TRANSFER REQUEST FLAG IS SETY
}

} TRANSFER DATA
08328
000324

116730 176646

POR756

EMPTY!

To THE PRQGRAM

MoVB RXDB,
B8R ELOOP

DATA BUFFER FRoM THE RX®1 SECTQR

BUFFER

@(RO)+

- JTHE FOLLOWING 3 PROGRAM LOCATIONS ARE THE ERROR RETRY COUNTERS
eeB326
PP0330
PR332

geoBap
goo0og
020000

éTRY:

CTRY!
STRY!

i PARITY ERROR RETRY COUNTER

2
@

;
;

CRC ERROR RETRY COUNTER
BEEK ERROR RETRY COUNTER

}

JPROGRAM LOCATION " CQMMAND " CONTAINS THE COMMAND To BE ISSUED VIA THE LCD 10T

}

IWRITE (4),
}

poB3I34

000029

COMMAND §

WRITE DELETED DATA (414), OR READ (6),
2

;

14,

QR EMPTY BUFFER (2)

BR 2 & (GO BIT 1 8 1)

}

{PROGRAM LOCATION " SECTOR " CONTAINS THE SEGTOR ADDRESS (4 70 32 0CTAL)
2PB336

pee0oe

SECTOR: @

;1 70 32 OCYAL

S PROGRAM LOCATION " TRACK " CONTAINS THE TRAGK ADDRESS (@ To 414 OCTAL)
opB348

goeoeg

TRACK:

;@ 7O 144 OGTAL

PROGRAM EQUIVALENTS
H

232

o040
040000
90342
p0@542
poepal

DONEBITH4D

INIT=40000
BUFFER=,
,SBUFFER+200
'END

Figure 3-7

RX11 Empty Buffer Example

3-10

If no error is indicated, the program looks for the Transfer Request (TR) flag to set. The Error flag is retested if TR
is not set. Once TR sets, a byte is moved from the RX11 sector buffer to the core locations of BUFFER. The
process continues until the sector buffer is empty and the Done bit is set.
3.4.3

Fill Buffer Function

Figure 3-8 presents a program to implement a Fill Buffer function. It is very similar to the Empty Buffer example.
3.5

RESTRICTIONS AND PROGRAMMING PITFALLS

A set of restrictions and programming pitfalls for the RX11 is presented below.

1.
2.

Depending on how much data handling is done by the program between sectors, the minimum interleave
of two sectors may be used, but to be safe a three-sector interleave is recommended.

If an error occurs and the program executes a Read Error Register function (111), a parity error may

occur for that command. The error status would not be for the error in which the Read Error Register
function was originally required.

The DRV SEL RDY bit is present only at the time of a Read Status function (101) for both drives, and

after an Initialize, depending on the status of drive 0.

Tt is not required to load the Drive Select bit into the RXCS when the command is Fill Buffer (000) or
Empty Buffer (010).

Sector Addressing: 1-26 (No sector 0)
Track Addressing: 0—76

A power failure causing the recalibration of the drives will result in a Done condition, the same as
finishing reading a sector. However, during a power failure, RXES bit 2 (Initialize Done) will set.
Checking this bit will indicate a power fail condition.

Excessive usage of the Read Status function (101) will result in drastically decreased throughput,

because a Read Status function requires between one and two diskette revolutions or about 250 ms to
complete.

3.6

ERROR RECOVERY

There are two error indications given by the RX11 system. The Read Status function (Paragraph 3.3.5) will assemble
the current contents of the RXES (Paragraph 3.2.2), which can be sampled to determine errors. The Read Error
Register function (Paragraph 3.3.7) can also be used to retrieve explicit error information. The RX11 Interface
register can be interrogated to determine the type of failure that occurred.
A list of error codes is presented on the following page.
NOTE

A Read Status function is not necessary if the DRV RDY bit is
not going to be interrogated, because the RXES is in the

Interface register at the completion of every function.

3-11

Octal
Error Code Meaning

Code
0010

Drive O failed to see home on Initialize.

0020

Drive 1 failed to see home on Initialize.

0030

Found home when stepping out 10 tracks for INIT.

0040

Tried to access a track greater than 77.

0050

Home was found before desired track was reached.

0060

Self-diagnostic error.

0070

Desired sector could not be found after looking at 52 headers (2 revolutions).

0110

More than 40 us and no SEP clock seen.

0120

A preamble could not be found.

0130

Preamble found but no I/O mark found within allowable time span.
CRC error on what we thought was a header.
The header track address of a good header does not compare with the desired track.

0140
0150

0160

Too many tries for an IDAM (identifies header).

0170

Data AM not found in allotted time.

0200

CRC error on reading the sector from the disk. No code appears in the ERREG.

0210

All parity errors.

3-12

;THE FOLLOWING IS A PROGRAMMING EXAMPLE OF THE PROTOCOL REQUIRED TO
}

JFILL THE SECTOR BUFFER WITH 128 8eB1Y BYTES

} NOTE: THE DATA To FILL THE SECTQR BUFFER CAN BE ASSEMBLED IN CORE IN THE
EVEN ADDRESSES BYTES OF 128 WORD8 OR [N BOTH BYTES OF 64 WORDS
i
p@@L56
po@L64
p0OL70

012767
12700
616767

177770
paB342
PA0140

poRL42

176772

)

; 8 TRYS 7O FILL THE SECTOR BUFFER
; PROGRAMS DATA BUFFER

FENTRY: MOV #=18, PTRY
SETUPI MOV #BUFFER, R@

;

MOV COMMAND, RXCS

I1SSUE THE COMMAND

}

iWAIT FOR A TRANSFER HEQUEST FLAG BEFORE TRANSFERRING DATA FROM THE PROGRAMS
}

iDATA BUFFER TO THE RX@1 SECTOR BUFFER

;NAIT FOR A DONE FLAT TO INDICATE THE COMPLETION OF THE FILL BUFFER COMMAND
)

JPRIOR To TESTING THE ERROR FLAG
4

@e0176
pe@e02
poo2p4
90212

109767
p01414
232767
poL771

Loop!

176766
opopan

TEST FOR TRANSFER REQUEST FLAG

TSTB RXCS

. BEQ IF TRANSFER REQUEST FLAG SET

BEQ FILL

: TEST FOR THE DONE FLAG
: BEG UNTIL THE DONE FLAG SETS

BIT #DONEBIT, RXCS
BEQ LOOP

1767586

THE DONE FLAG 1§ SET
H

JTEST FgR ANY ERRQRS (gNLY ERRQR poSSIBLE IS A PARITY ERROR)
]

200214
poa220
ppB222

pP8767

po01001
po0e00

176750

TST RXCS
BNE 1§

; NO CRRORS = OK = COMPLETE

HALT
}

| INCREMENT AND TEST THE.PARITY ERROR RETRY PROGRAM LOGATION " PTRY ®

}

JAND RETRY THE CoMMAND UNTIL THE ERROR RECOVERS

JQR UNTIL THE PTRY COUNTER QVERFLOWS Yo 9
poD224
gAae3n

200232

05267
0@1335
e00000

gpoe76

18!

INC PTRY

; RETRY T0 FILL THE SECTOR BUFFER
; HARD PARITY ERROR

BNE SETUP
HALT

I THE TRANSFER REQUEST FLAG IS SET

}

i TRANSFER DATA FRQM THE PROGRAMS DATA BUPFER To THE RX84 SECTOR BUFFER

P00234
0@pe4n

113067
pee7%6

176732

}

FILLS

ggVE 3;RG)+; RXDB

Figure 3-8

; PROGRAMS DATA BUFFER 1S 64 WORDS IN LENGTH

RX11 Fill Buffer Example

3-13

4
CHAPTER

RXS8E INTERFACE
PROGRAMMING INFORMATION
The RXSE interface allows two modes of data transfer: 8-bit word length and 12-bit word length. In the 12-bit
mode, 64 words are written in a diskette sector, thus requiring two sectors to store one page of information. The
diskette capacity in this mode is 128,128 12-bit words (1,001 pages). In the 8-bit transfer mode, 128 8-bit words
are written in each sector. Disk capacity is 256,256 8-bit words, which is a 33 percent increase in disk capacity over
the 12-bit mode. Eight-bit mode must be used for generating IBM-compatible diskettes, since 12-bit mode does not
fully pack the sectors with data. The hardware puts in the extra Os. Data transfer requests occur 23 s after the
previous request was serviced for 12-bit mode (18 us for 8-bit mode). There is no maximum time between the
transfer request from the RXO01 and servicing of that request by the host processor. This allows the data transfer to
and from the RXO01 to be interrupted without loss of data.
4.1

DEVICE CODES

The eight possible device codes that can be assigned to the interface are 70—77. These device codes define address
locations of a specific device and allow up to eight RX8E interfaces to be used on a single PDP-8. These multiple
device codes are also shared with other devices. Depending on what other devices are on the system, the RX8E
device code can be selected to avoid conflicts. (Refer to the PDP-8 Small Computer Handbook for specific device
codes.)

The device codes are selected by switches according to Table 4-1. These switches control AC bits 6—8, while AC bits
3—5 are fixed
at 1s. The device code is initially selected to be 70. Switches 7 and 8 are not connected and will not
affect the device selection code. The switches are all located on a single DIP switch package that is located on the
M8357 RX8E interface board.

Table 4-1

Device Code Switch Selection

0 (OFF)

1 (ON)

Code | S1|s2|s3|s4/|ss]|s6]|s7]|ss

|X]|X

1lol1]lol1]o]x]|xXx

[

|X | X

]

Device

ololol1

olo | 1|1
1

|11

[|x]x

|X | X

|10

1110|001
1

4-1

|XxX]|X

—

4.2

INSTRUCTION SET

The RX8E instruction set is listed below and described in the following paragraphs.

I0T

Mnemonic

Description

67x0

4.2.1

No Operation

67x1

LCD

Load Command, Clear AC

67x2

XDR

Transfer Data Register

67x3

STR

Skip on Transfer Request Flag, Clear Flag

67x4

SER

Skip on Error Flag, Clear Flag

67x5

SDN

Skip on Done Flag, Clear Flag

67x6

INTR

Enable or Disable Disk Interrupts

67x7

INIT

Initialize Controller and Interface

Load Command (LCD) — 67x1

This command transfers the contents of the AC to the Interface register and clears the AC. The RXO01 begins to

execute the function specified in AC 8, 9, and 10 on the drive specified by AC 7. A new function cannot be initiated
unless the RX01 has completed the previous function. The command word is defined as shown in Figure 4-1.
00

—

—~

NOT

USED

MAINT

NOT

Figure 4-1

FUNCTION

USED

8/12

NOT
USED

DRV
SEL

cCP-1514

LCD Word Format (RXS8E)

The command word is described in greater detail in Paragraph 4.3.1.

4.2.2

Transfer Data Register (XDR) — 67x2

With the Maintenance flip-flop cleared, this instruction operates as follows. A word is transferred between the AC
and the Interface register. The direction of the transfer is governed by the RXO01, and the length of the word
transferred is governed by the mode selected (8-bit or 12-bit). When Done is negated, executing this instruction
indicates to the RX01:

That the last data word supplied by the RXO01 has been accepted by the PDP-8, and the RX01 can
proceed, or

That the data or address word requested by the RXO01 has been provided by the PDP-8, and the RXO01
can proceed.

A data transfer (XDR) from the AC always leaves the AC unchanged. If operation is in 8-bit mode, AC 0—3 are
transferred to the Interface register but are ignored by the RXO01. Transfers into the AC are 12-bit jam transfers

when in 12-bit mode. When in 8-bit mode, the 8-bit word is ORed into AC 4—11, and AC 0—3 remain unchanged.
When the RXO01 is done, this instruction can be used to transfer the RXES status word from the Interface register to
the AC. The selected mode controls this transfer as indicated above.

4.2.3

STR - 67x3

This instruction causes the next instruction to be skipped if the Transfer Request (TR) flag has been set by RX01
and clears the flag. The TR flag should be tested prior to transferring data or address words with the XDR
instruction to ensure the data or address has been received or transferred, or after an LCD instruction to ensure the
command is in the Interface register. In cases where an XDR follows an LCD, the TR flag needs to be tested only
once between the two instructions. (See programming example in Paragraph 4.5.1.)
4.2.4

SER — 67x4

This instruction causes the next instruction to be skipped if the Error flag has been set by an error condition in the
RXO1 and clears the flag. An error also causes the Done flag to be set (Paragraph 4.3.6).
4.2.5

SDN — 67x5

This instruction causes the next instruction to be skipped if the Done flag has been set by the RX01 indicating the
completion of a function or detection of an error condition. If the Done flag is set, it is cleared by the SDN
instruction. This flag will interrupt if interrupts are enabled.
4.2.6

INTR — 67x6

This instruction enables interrupts by the Done flag if AC 11 = 1. It disables interrupts if AC 11 =0.
4.2.7

INIT — 67x7

The instruction initializes the RX01 by moving the head position mechanism of drive 1 (if drive 1 is available) to
track 0. It reads track 1, sector 1 of drive 0. It zeros the Error and Status register and sets Done upon successful
completion of Initialize. Up to 1.8 seconds may elapse before the RXO01 returns to the Done state. Initialize can be
generated programmably or by the Omnibus Initialize.
4.3

Only one physical register (the Interface register) exists in the RX8E, but it may represent one of the six RX01

registers described in the following paragraphs, according to the protocol of the function in progress.
4,3.1

Command Register (Figure 4-2)

The command is loaded into the Interface register by the LCD instruction (Paragraph 4.2.1).

NOT USED

MAINT

NOT

FUNCTION

USED
8/12

NOT
USED

DRV
SEL

Figure 4-2 Command Register Format (RX8E)

4-3

CP-1514

The function codes (bits 8, 9, 10) are summarized below and described in Paragraph 4.4.
Code

Function

000

Fill Buffer

001

Empty Buffer

010

Write Sector

011

Read Sector

100

Not used

101

Read Status

110

Write Deleted Data Sector

111

Read Error Register

The DRV SEL bit (bit 7) selects one of the two drives upon which the function will be performed:
AC7=0

Select drive O

AC7=1

Select drive 1

The 8/12 bit (bit 5) selects the length of the data word.
AC5=0

Twelve-bit mode selected

ACS5=1

Eight-bit mode selected

The RX8E will initialize into 12-bit mode.
4.3.2

Error Code Register (Figure 4-3)

Specific error codes can be accessed by use of the Rear Error Register function (111) (Paragraph 4.4.7). The specific
octal error codes are given in Paragraph 4.7.
00

NOT USED

ERROR

Figure 4-3

CODE

cpP-1515

Error Code Register Format

The Maintenance bit (M bit) can be used to diagnose the RX8E interface under off-line and on-line conditions. The
off-line condition exists when the BCO5L-15 cable is disconnected from the RX01; the on-line condition exists when
the cable is connected to the RXOL1.

If an LCD IOT (I/O Transfer) is issued with AC 4 =1, the Maintenance flip-flop is set. When the Maintenance

flip-flop is set, the assertion of RUN on following XDR instructions is inhibited, and all data register transfers (XDR)
are forced into the AC. The Maintenance bit allows the Interface register to be written and read for maintenance
checks. The Maintenance flip-flop is cleared by Initialize or by an LCD IOT with AC 4 = 0.
The following paragraphs describe more explicitly how to use the Maintenance bit in an off-line mode.

The contents of the interface buffer cannot be guaranteed immediately following the first LCD IOT, which sets the
Maintenance flip-flop. However, successive LCD IOTs will guarantee the contents of the Interface register. The

contents of the Interface register can then be verified by using the XDR IOT to transfer those contents into the AC.

4-4

In addition, the Maintenance flip-flop directly sets the Skip flags, which will remain set as long as the Maintenance

flip-flop is set. Skipping in these flags as long as the Maintenance flip-flop is set will not clear the flags. Setting and

then clearing the Maintenance flip-flop will leave the Skip flags in a set condition. The skip IOTs can then be issued
to determine whether or not a large portion of the interface skip logic is working correctly.

The Maintenance flip-flop can also be used to determine if the interface is capable of generating an interrupt on the
Omnibus. The Maintenance flip-flop is set, thus causing the Done flag to set. The Interrupt Enable flip-flop can be
set by issuing an INTR IOT with AC bit 11 = 1. The combination of Done and Interrupt Enable should generate an
interrupt.

The Maintenance flip-flop can also be used to test the INIT IOT. The Maintenance flip-flop is set and cleared to
generate the flags, and INIT IOT is then executed. If execution of INIT IOT is internally successful, all of the flags
and the Interrupt Enable flip-flop should be cleared if they were previously set.

In the on-line mode, use of the Maintenance bit should be restricted to writing and reading the Interface register.
The same procedure described to write and read the Interface register in the off-line mode should be implemented in
the on-line mode. Additional testing of the RX8E in the on-line mode should reference the appropriate circuit
schematics. Exiting from the on-line Maintenance bit mode should be finalized by an initialize to the RXO01.
4.3.3

RXTA — RX Track Address (Figure 4-4)

This register is loaded to indicate on which of the 77 tracks a given function is to operate. It can be addressed only
under the protocol of the function in progress (Paragraph 4.4). Bits O through 3 are unused and are ignored by the
control.

O-1l4g

NOT USED

cP-1516

Figure 44

4.3.4

RXTA Format (RX8E)

RXSA — RX Sector Address (Figure 4-5)

This register is loaded to indicate on which of the 26 sectors a given function is to operate. It can be addressed only
under the protocol of the function in progress (Paragraph 4.4). Bits O through 3 are unused and are ignored by the
control.

——

—~—

NOT USED

1-32g

Figure 4-5

RXSA Format (RXSE)

4-5

CP-1517

4.3.5

RXDB — RX Data Buffer (Figure 4-6)

All information transferred to and from the floppy media passes through this register and is addressable only under
the protocol of the function in progress. The length of data transfer is either 8 or 12 bits, depending on the state of

bit 5 of the Command register when the LCD IOT is issued (Paragraph 4.3.1).

)

12BIT

8 or 12 BIT

MODE

MODE ONLY

Figure 4-6
4.3.6

cpP-1518

RXDB Format (RXS8E)

RX Error and Status (Figure 4-7)

The RXES contains the current error and status conditions of the selected drive. This read-only register can be
accessed by the Read Status function (101). The RXES is also available in the Interface register upon completion of

any function. The RXES is accessed by the XDR instruction. The meaning of the error bits is given below.

~—

38\4

)

NOT USED

Figure 4-7

10 | PAR | CRC

NOT USED

CP-151¢

RXES Format (RX8E)

Bit No.

Description

CRC Error — The cyclic redundancy check at the end of the header or data field has

indicated an error. The header or data must be considered invalid; it is suggested that the

data transfer be retried up to ten times, as most data errors are recoverable (soft). (See
Chapter 6).

Parity Error — When status bit 10 = 1, a parity error has been detected on command and
address information being transferred to the RXO01 uCPU controller from the RXS8E
interface. Upon detection of a parity error, the current function is terminated, the RXES
status word is moved to the Interface register, and the Error and Done flags are set. The
function can be retried to determine if the parity error is a soft or hard error. A parity error

indication means that there is a problem in the interface cable between the RXO01 and the
interface.

Initialize Done — This bit indicates completion of the Initialize routine. It can be asserted
due to RXO01 power failure, system power failure, or programmable or bus Initialize. This bit

is not available within the RXES from a Read Status function.

4-6

Bit No.

Description

Deleted Data (DD) — In the course of reading data, a deleted data mark was detected in the
identification field. The data following will be collected and transferred normally, as the
deleted data mark has no further significance within the RX01. Any alteration of files or
actual deletion of data due to this mark must be accomplished by user software. This bit will

be set if a successful or unsuccessful Write Deleted Data function is performed.
4

Drive Ready — This bit is asserted if the unit currently selected exists, is properly supplied

with power, has a diskette installed properly, has its door closed, and has a diskette up to

speed.
NOTE 1

This bit is only valid for either drive when retrieved via a Read
Status function or for drive 0 upon completion of an Initialize.
NOTE 2

If the Error bit was set in the RXCS but Error bits are not set

in the RXES, then specific error conditions can be accessed via
a Read Error Register function.
4.4

FUNCTION CODE DESCRIPTION

RXS8E functions are initiated by means of the Load Command IOT (LCD). The Done flag should be tested and
cleared with the SDN instruction in order to verify that the RX8E is in the Done state prior to issuing the LCD
instruction. Upon receiving an LCD instruction while in the Done state, the RX8E enters the Not Done state while

the command is decoded. Each of the eight functions summarized below requires that a strict protocol be followed
for the successful transfer of data, status, and address information. The protocol for each function is described in the
following sections, and a summary table is presented below.
AC

Octal

0
2

Function

Empty Buffer

Write Sector

Read Sector

Not Used

Fill Buffer

Read Status

Write Deleted Data Sector

Read Error Register
NOTE

AC bit 11 is assumed to be 0 in the above octal codes, since
ACDbit 11 can be 0 or 1.
4.4.1

Fill Buffer (000)

This function is used to load the RXO01 sector buffer from the host processor with 64 12-bit words if in 12-bit mode
or 128 8-bit words if in 8-bit mode. This instruction only loads the sector buffer. In order to complete the transfer
to the diskette, another function, Write Sector, must be performed. The buffer may also be read back by means of
the Empty Buffer function in order to verify the data.

4-7

Upon decoding the Fill Buffer function, the RX01 will set the Transfer Request (TR) flag, signaling a request for the
first data word. The TR flag must be tested and cleared by the host processor with the STR instructions prior to
each successive XDR IOT (Paragraph 4.2.3). The data word can then be transferred to the Interface register by
means of the XDR IOT. The RX01 next moves the data word from the Interface register to the sector buffer and
sets the TR flag as a request for the next data word. The sequence above is repeated until the sector buffer has been
loaded (64 data transfers for 12-bit mode or 128 data transfers for 8-bit mode). After the 64th (or 128th) word has
been loaded into the sector buffer, the RXES is moved to the Interface register, and the RX01 sets the Done flag to
indicate the completion of the function. It is, therefore, unnecessary for the host processor to keep a count of the
data transfers. Any XDR commands after Done is set will result in the RXES status word being loaded in the AC.
The sector buffer must be completely loaded before the RX8E will set Done and recognize a new command. An
interrupt would now occur if Interrupt Enable were set.
4.4.2

Empty Buffer (001)

This function moves the contents of the sector buffer to the host processor. Upon decoding this function, RXES bits
10 and 11 (Parity Error and CRC Error) are cleared, and the TR flag is set with the first data word in the Interface
register. This TR flag signifies the request for a data transfer from the RXS8E to the host processor. The flag must be
tested and cleared, then the word can be moved to the AC by an XDR command. The direction of the transfer for
an XDR command is controlled by the RX01. The TR flag is set again with the next word in the Interface register.
The above sequence is repeated until 64 words (128 bytes if 8-bit mode) have been transferred, thus emptying the
sector buffer. The Done flag is then set after the RXES is moved in the Interface register to indicate the end of the
function. An interrupt would now occur.if Interrupt Enable were set.
NOTE

The Empty Buffer function does not destroy the contents of
the sector buffer.
4.4.3

Write Sector (010)

This function transfers the contents of the sector buffer to a specific track and sector on the diskette. Upon

decoding this function, the RX8E clears bits 10 and 11 (Parity Error and CRC Error) of the RXES and sets the TR
flag, signifying a request for the sector address. The TR flag must be tested and cleared before the binary sector
address can be loaded into the Interface register by means of the XDR command. The sector address must be within
the limits 1—-325.

The TR flag is set, signifying a request for the track address. The TR flag must be tested and cleared, then the binary
track address may be loaded into the Interface register by means of the XDR command. The track address must be
within the limits 0—1145.

The RXO01 tests the supplied track address to determine if it is within the allowable limits. If it is not, the RXES is
moved to the Interface register, the Error and Done flags are set, and the function is terminated.

If the track address is legal, the RX01 moves the head of the selected drive to the selected track, locates the
requested sector, transfers the contents of the sector buffer and a CRC character to that sector, and sets Done. Any
errors encountered in the seek operation will cause the function to cease, the RXES to be loaded into the Interface
register, and the Error and Done flags to be set. If no errors are encountered, the RXES is loaded into the Interface
register and only the Done flag is set.
NOTE

The Write Sector function does not destroy the contents of
the sector buffer.

4-8

4.4.4

Read Sector (011)

This function moves a sector of data from a specified track and sector to the sector buffer. Upon decoding this
function, the RXS8E clears RXES bits 5, 10, 11 (Deleted Data, Parity Error, CRC Error) and sets the TR flag,
signifying the request for the sector address. The flag must be tested and cleared. The sector address is then loaded
into the Interface register by means of the XDR command. The TR flag is set, signifying a request for the track
address. The flag is tested and cleared by the host processor, and the track address is then loaded into the Interface
register by an XDR command. The legality of the track address is checked by the RXO01. If illegal, the Error and
Done flags are set with the RXES moved to the Interface register, and the function is terminated. Otherwise, the
RX01 moves the head to the specified track, locates the specified sector, transfers the data to the sector buffer,
computes and checks CRC for the data. If no errors occur, the Done flag is set with the RXES in the Interface
register. If an error occurs anytime during the execution of the function, the function is terminated by setting the
Error and Done flags with RXES in the Interface register. A detection of CRC error results in RXES bit 11 being set.
If a deleted data mark was encountered at the beginning of the desired data field, RXES bit 5 is set.
4.4.5

Read Status (101)

Upon decoding this function, the RX01 moves the RXES to the RXS8E Interface register and sets the Done flag. The
RXES can then be read by the Transfer Data Register command (XDR). The bits are defined in Paragraph 4.3.6.
NOTE

The average time for this function is 250 ms. Excessive use of
this function will result in substantially reduced throughput.
4.4.6 Write Deleted Data Sector (110)

This function is identical to the Write Data function except that a deleted data mark is written prior to the data field
rather than the normal data mark (Paragraph 1.3.3.2). RXES bit 5 (Deleted Data) will be set in the RXS8E Interface
register upon completion of the function.

4.4.7 Read Error Register Function (111)

The Read Error Register function can be used to retrieve explicit error information upon detection of the Error flag.
Upon receiving this function, the RX01 moves an error code to the Interface register and sets Done. The Interface
register can then be read via an XDR command and the code interrogated to determine which type of failure
occurred (Paragraph 4.7).

NOTE

Care should be exercised in use of this function because, under
certain conditions, erroneous error information may result
(Paragraph 4.6).
4.4.8

Power Fail

There is no actual function code associated with Power Fail. When the RX01 senses a loss of power, it will unload

the head and abort all controller action. All status signals are invalid while power is low.

When the RXO01 senses the return of power, it will remove Done and begin a sequence to:
1.

Move drive 1 head position mechanism to track O.

Clear any active error bits.

Read sector 1 of track 1 of drive O.

Set Initialize Done bit of the RXES, after which Done is again asserted.

4-9

There is no guarantee that information being written at the time of a power failure will be retrievable. However,
all
other information on the diskette will remain unaltered.
A method of aborting an incomplete function is with the INIT IOT (Paragraph 4.2.7).
4.5

PROGRAMMING EXAMPLES

4.5.1 Write/Write Deleted Data/Read Functions
Figure 4-8 presents a program for implementing a Write, Write Deleted Data, or a Read function with interrupts
turned off (IOF). The first three steps preset the PTRY, CTRY, and STRY retry counters, which are set at ten

retries but can be changed to any number. Starting at RETRY, the program tests for 8- or 12-bit mode, type of

function, and drive. Once the command is loaded, the program waits in a loop for the controller to respond with

Transfer Request (TR). When TR is set, the sector address is loaded and the AC is cleared. The program loops while
waiting for the controller to respond with another TR. When TR is reset, the track address is loaded, and the AC is

cleared again. The program loops to wait for the Done condition.

When the Done flag is set, the program checks for an error condition, indicated by the Error flag being set. If the

AC =0000, then the error is a seek error; if bit 10 of the AC is set, the error is a parity error; and if bit 11 of the AC
is set, the error is a CRC error. Error status from the RXES is saved and tested to determine the error (Paragraph

4.3.6). The RXES will not include the Select Drive Ready bit. If a parity error is detected, the program increments

and tests the PTRY retry counter. If a parity error persists after ten tries, it is considered a hard error. If ten retries
have not occurred, a branch is made to RETRY and the sequence repeated.

If the Parity Error bit of the RXES is not set, then the program tests to see if the CRC Error bit is set. If a CRC error
is detected, the program increments and tests the CTRY retry counter. If a CRC error persists after ten retries, it is

considered a hard error. If ten retries have not occurred, a branch is made to RETRY and the sequence repeated.

A seek error is assumed if neither a CRC nor a parity error is detected. An Initialize (INIT) instruction is performed

(Paragraph 4.2.7). During a Write or Write Deleted Data function, the sector buffer must be refilled, because INIT

will cause sector 1 of track 1 of drive 0 to be read, which will destroy the previous contents of the sector buffer. The

instruction sequence for a Fill Buffer function is not included in Figure 4-8, but is presented in Figure 4-10. After

the system has been initialized, the program increments and tests the STRY retry counter. If a seek error persists
after ten tries, it is considered a hard error. If ten retries have not occurred, a branch is made to RETRY and the

sequence repeated.

4.5.2

Empty Buffer Function

Figure 4-9 shows a program for implementing an Empty Buffer function with interrupts turned off (IOF). The first

instruction sets the number of retries at ten. A 2 is set in the AC to indicate an Empty Buffer command, and the

command is loaded. When TR is set, the program jumps to EMPTY to transfer a word to the BUFFER location. A
jump is made back to loop to wait for another TR. This process continues until either 64 words or 128 bytes have

been emptied from the sector buffer. When Done is set, the program tests to see if the Error bit is set. If the Error
bit is set, the program retries ten times. If the error persists, a hard parity error is assumed, indicating a problem in

the interface cable.
4.5.3

Fill Buffer Function

Figure 4-10 presents a program to implement a Fill Buffer function. It is very similar to the Empty Buffer example.

4-10

/PROGRAMMING EXAMPLES FOR THE RX8/RXO1 FLEXIBLE DISKETTE
/

/THE FOLLOWING ARE RX@1 10T CODE DEFINITIONS
/

OO~V

/THE STANDARD 10T DEVICE CQDE IS 670~
/

67081

6702
6703
6704

6705
6706
6707

LCD=670%
XDRE6702
STRa6703

/10T TO LOAD THE COMMAND, (AC) 1§ THE COMMAND
/10T TO LOAD OR READ THE TRANSFER REGISTER
/10T TO SKIP ON A TRANSFER REQUEST FLAG

INTR=6706

/ (AC) = @ INTERRUPT ENABLE OFF/ (AC) = 1 MEANS ON

/10T TO SKIP ON AN ERROR FLAG
/107 TO SKIP ON THE DONE FLAG

SER26704
SON36705

/10T TO INITIZLIAE THE RX8/RX@BL SUBSYSTEM

NIT=67¢7

/THE FOLLOWING IS A PROGRAMMING EXAMPLE OF THE PROTOCOL REQUIRED

/TO WRITE, WRITE DELETED DATA, OR READ AT SECTOR "S" (THE CONTENTS OF PROGRAM

p200

9201
p202
@203
@2p4

g205

1254

3257

;LOCATION SECTOR) OF TRAGK "T" (TYHE CONTENTS OF PROGRAM LOCATION TRACK)
;IN 8 OR 12 BIY MODE
/ =10
gTART. TAD KMiD
/PARITY RETRY COUNTER
OCA PTRY

DCA CTRY

TAD KMig@

/GRC RETRY COUNTER

DCA STRY

TAD KMi®

/SEEK RETRY COUNTER

/WRITE, WRITE DELETED DATA, OR READ
@206
0207

1260
1261

@210
pail

1262
6701

RETRY,

TYAD MODE
TAD COMMAND
TAD UNIT

LCO

/0 |F 12eB]T, 1080 [F 8eB
/ 4 IF WRITE, 14 IF NR!TE DELETED

/DATA,

OR 6 IF READ

¢/ B {F UNIT B, 20 IF UNIT 4

/10T 67X4{ TO LOAD THE COMMAND

/WAIT FOR THE YRANSFER REQUEST FLAG THEN TRANSFER THE SECTOR ADORESS
/

g212
@213
@214

@213
g216

6703
5212
1263
6702
7200

STR

/107 67X3 70

TAD SECTOR
XOR

/ 1 7O 32(0CYAL)
/10T 70 LOAD SECTOR

JMP =l
CLA

@220
@221
g222

@223

JWALT FOR THE TRANSFER REQUEST FLAG THEN TRANSFER THE TRACK ADDRESS
.
STR
JMP el
TAD TRACK

6703
5217

1264
6702
7200

/CLA BECAUSE 10T XDR DOESN'T

@217

/HALT FOR TRANSFER REQUEST FLAG

/10T 67%X3 T0
/WA1T FOR TRANSFER REQUEST
/8 T0 114(0CTAL)

/10T 70 LOAD TRACK
XDR
/CLA BECAUSE 10T XDR DOESN'T
CLA
TO THE RXZ1 VIA THE XDR 107
TRANSFERRED
BEEN
HAVE
ADDRESSES
TRACK
AND
/THE SECTOR
/

/NA!T FOR THE DONE FLAG AND CHECK FOR ANY ERRORS

@224
@225

2226
@227

6705
5224
6704
7402

/IF THE FUNCTION HAS COMPLETED SUCCESSFULLY (NO ERROR FLAG) THEN HALT
/10T 67X9 TO
SON

JMP =i

SER
HLT

/WALIT FOR DONE FLAG

/10T 67X4 SAMPLES ERROR FLAG
/ OK e COMPLETED

/THE ERROR FLAG IS SET

/THE CONTENTS OF THE TRANSFER REGISTER IS THE ERRQR STATUS

~/IF TRANSFER REGISTER BITS 10, AND 11 = @ THEN SOME TYPESSEgEEK ERROR HAS OQCCURED,
/1F TRANSFER REGISTER BIT 11 = 1 THEN A CRC ERRQR HAS 0C
/1F TRANSFER REGISTER BIT 1@ = 1 THEN A PARITY ERROR HAS OCCURED
/

6702

XOR

/GET CONTENTS OF TR (ERROR STATUS)

DCA ASTATUS

/AND SAVE

AND ASTATUS

/TEST FOR PAR]ITY ERROR

CLL CLA T1AC RAL

SNA CLA

JMP TCRC

/SK1P 1F PARITY ERROR

/NOT A PARITY ERROR = MAYBE CRC

;A PARITY ERRQR HAS QCCURED
;INCREMENT AND TEST THE PARITY ERROR RETRY COUNTER PROGRAM LOCATION " PTRY "
;AND RETRY THE " COMMAND TM UNTIL THE PARITY ERROR RECQVERS

20R UNTIL THE PTRY COUNTER OVERFLOQWS TO @
ISE

PTRY

JMP RETRY
HLY

/RETRY THE COMMAND
/HARD PARITY ERROR

/THE ERROR FLAG 1S SET BUT THE ERROR IS NOT A PARITY ERROR
/

/TEST FQR A CRC ERRQR
/

g241
g242
0243

g244

7301

@265
7650
5250

TCRC,

CLL CLA ]AC
AND ASTATUS
SNA CLA

JMP SEEK

/1
/TEST FOR A GRC ERROR
/SKIP IF A CRC ERROR

/NOT A CRC = MUST BE A SEEK

Figure 4-8 RXS8E Write/Write Deleted Data/Read Example (Sheet 1 of 2)

CRC ERROR HAS

QCCURED

ZINCREMENT AND TgST THE CRC ERROR RETRY COUNTER PROGRAM LOCATION "TM CTRY
/AND

RETRY

THE

COMMAND

UNTIL

THE

CRC ERROR

RECOVERS

EOR UNTIL THE CTRY COUNTER OVERFLOWS TO @
0245
@246
p247

IS2 CTRY

2256
5206
7402

JMP

RETRY

HLY

/RETRY THE
/HARD

COMMAND

CRC

ERROR

;THE ERROR FLAG 1S SET
;THE ERROR 1S ENOTI A PARITY ERROR AND (S ENOTI A CRE ERROR
5THEREFORE 1S MUST BE A SEEK ERROR
2 (CONTENTS OF THE TRANSFER REGISTER BITS 18, AND i1 ® @)
@250

6707

?EEK.

INIT

/INCREMENT AND

/10T 67X7

TEST THE

SEEK ERROR RETRY COUNTER PROGRAM

INITIZBLIAE

LOCATION "

STRY #

;AND RETRY THE COMMAND UNTIL THE SEEK ERROR RECOVERS
EOR UNTIL THE CTRY COUNTER OVERFLOWS TO @
ISE STRY
JMP RETRY

@251
p252
@253

/RETRY THE COMMAND

HLT

/HARD

/THE FOLLOWING PROGRAM LOCATIONS

@254

7778

KM18,

SEEK

ERROR

ARE REFERENCED WITHIN THIS EXAMPLE

=10

/THE FOLLOWING 3 PROGRAM LOCATIONS ARE THE ERROR RETRY COUNTERS
P255
p256
@257

0000
000D
pooo

PTRY,

CTRY,
srav.

@
?

/PARITY

/PROGRAM LOCATION " MODE " CONTAINS
/CONTAINS A 1908 IF 8=BIT MODE
2608

oPo0

¢ODE.

p261

o000

(4),

p263

aeoe

@264

pooo

WRITE

DELETED

/AT

Figure 4-8

(14),

MODE,

READ

(6),

UNIT

CONTAINS

THE

UNJT

DESJGNAT[ON

OCATION

SECTOR

[SSUED VA

EMPTY

BUFFER

THE LCD

(2)

/ B, OR 20
"

CONTAINS

THE

ézcron. ?

;PROGRAM

pooo

DATA

5u~17 g (0), OR UNIT 1 (20)
gNIT' 7]

IRACK:

COUNTER

/ 4, 14, OR 6, OR2
"

SECTOR

ADDRESS

QCTAL)

/ 1 10 32 0CTAL

;PROGRAM LOCATION "

p263

IF 12<BIT

CONTAINS THE COMMAND T0 BE

§ommAND, 0

/PROGRAM

RETRY

/ @.0R 180

/PROGRAM LOCATJON

p262

A @

)

;PROGRAM LOCATION "TM COMMAND "
/WRITE

ERROR

/CRC ERROR RETRY COUNTER
/SEEK ERROR RETRY COUNTER

TRACK

" CONTAINS THE TRACK ADDRESS

/ ©
LOCATION

ASTATUS

THE DETECTION OF AN

ERROR

CONTAINS

(ERROR

THE

FLAG

CONTENTS

= 1)

(@ YO 114

0CTAL)

TO 114 OCTAL
OF

THE

TRANSFER

WHICH CORRESPONDS T

THE

;ERROR STATUS
; = g IF SEEK ERROR, 1 IF CRC ERROR, 2 IF PARITY ERRQR
ZSTATUS. [
/STATUS AT ERROR
RX8E Write/Write Deleted Data/Read Example (Sheet 2 of 2)

4-12

10T

/THE FOLLOWING 1S A PROGRAMMING EXAMPLE OF PROTOCOL REQUIRED TO
/

/EMPTY THE SECTOQR BUFFER OF 64 12=BlT WORDS (12 BIT MODE), OR
/

/EMPTY THE SECTOR BUFFER OF 128 8=BIT BYTES (8 BIT MODE)
/

DCA PTRY

/PARITY ERROR RETRY COUNTER

DCA A10

/AUTO INQEX REGISTER 10

TAD COMMAND
LCD

/ 2 MEANS EMPTY BUFFER
#2107 YO0 ISSUE THE CGOMMAND

/PROGRAMS DATA BUFFER

ESETUP, YAD (BUFFER=1)

315
@316
8317

/ @ IF 12=-B1Y, 100 IF 8 BIY

TAD MQODE

8320

@321
@322
p323
0324
p325

/ 8 TRYS TO EMPTY THE SECTOR BUFFER

EENTRY, TAD KMig@

0312
@313
P314

;NAIT FOR A TRANSFER REQUEST FLAG BEFOQRE TRANSFERRING DATA T0 THE PROGRAMS
;DATA BUFFER FROM THE RX@1 SECTOR BUFFER
;NAIT FOR A DONE FLAG TO [NDICATE THE COMPLETION OF THE EMPTY BUFFER COMMAND PRIOR TO
ETESTING THE ERROR FLAG
6703

7410
8333

ELOOP,

STR

/TEST FOR TR FLAG

JMP EMPTY

/TR FLAG SET

JMP LOOP

/NOT TR, OR DONE YET

SKP

/TR NOY BET,

6705
5274
/

TEST FOR DONE FLAG

/TEST FOR DONE FLAG

/THE DONE FLAG S SET
/

/TEST FOR ANY ERRORS (ONLY ERROR POSSIBLE IS A PARITY ERRQR)
2326
g327

6704
7402

/TESY FOR THE ERROR FLAG

SER

HLT

/NO ERRORS = 0K

‘

/INCREMENT AND TEST THE PARITY ERROR RETRY PRQGRAM LOCATION " PTRY "
/

/AND RETRY THE COMMAND UNTIL THE ERROR RECOVERS
/

/0R UNTIL THE PTRY COUNTER OVERFLOWS TO @
/

p338
331
@332

22585

IS8 PTRY

/RETRY TO EMPTY THE SECTOR BUFFER

JMP ESETUP

5314
7402

/HARD PARITY ERROR

HLT
/

/THE TRANSFER REQUEST FLAG IS SET
/

/TRANSFER DATA TO THE PROGRAMS DATA BUFFER FROM THE RX®1 SECTQR BUFFER

@333
p334
p3I35

8377

6702
3410
5321
@377
o408

EMPTY,

XDR

/FROM THE RX@1 SECTOR BUFFER

JMP ELOOP

/LO0P UNTIL THE DONE FLAG SETS

/70 THE PROGRAMS DATA BUFFER

DCA 1 Aig
PAGE

/THE FOLLOWING PROGRAM LOCATIONS ARE RESERVED FOR THE PROGRAMS DATA BUFFER
/

0400

poao
2608

BUFFER,

#BUFFER+200
%

Figure 4-9

RX8E Empty Buffer Example

4-13

/THE FOLLOWING
/

1S A PROGRAMMING EXAMPLE OF PROTOCOL REQUIRED TO

/FILL THE SECTOR BUFFER WITH 64 12-BIT WORDS

(12 BIT MODE).

/F1LL THE SECTOR BUFFER WITH 128 8-BIT BYTES (8 BIY MQOE)

0010

9266
p267
p270
@271
ga72
8273

1254
3255
1377
3010
1260
6701

p274
#2753
B276
@277
p300

6703
7410
5306
6705
5274

/
AL@a1d
/

FENTRY,

SETUP,

TAD KMi@
DCA PTRY

/ 8 TRYS TO FILL THE SECTOR BUFFER
/PARITY ERROR RETRY COUNTER

DCA ALPD
TAD MODE

/AUTO INDQEX REGISTER 1@
/ 0 IF 1@-BIY, 1060 |F 8 BIT

TAD

(BUFFER=Y1)

/PROGRAM§ DAYA BUFFER

LCD

/10T 70 ISSUE THE COMMAND

STR

/TEST FOR TR FLAG

;HAIT FOR A TRANSFER REQUEST FLAG BEFORE TRANSFERRING DATA FROM THE PROGRAMS
;DATA BUFFER TO THE RX@1 SECTOR BUFFER
5war FOR A DONE FLAG TO INDICATE THE COMPLETION OF THE FILL BUFFER COMMAND PRIOR TO
2TESTING THE ERROR FLAG
LOOP,

SKP

/TR NOT SET,

JMP FILL
SON
/

JMP LOOP

/THE DONE FLAG

TEST FOR DONE FLAG

/TR FLAG SET
/TEST FOR DONE FLAG

/NOT TR, OR DONE YET

IS SET

/TEST FQR ANY ERRORS (ONLY ERROR POSSIBLE [S A PARITY ERROR)

P304
9322

6704
7402

SER
HLT

/TEST FQR THE ERROR FLAG
/NO ERRORS = 0K

/INCREMENT AND TEST THE PARITY ERROR RETRY PROGRAM LOCATION " PTRY ¥

/AND RETRY THE COMMAND UNTIL THE ERROR RECOVERS
/

/0R UNTIL THE PTRY COUNTER OVERFLOWS TO B
‘
f/
p303
0304

0308

IS8 PTRY

2255
5270

/RETRY 70 FILL THE SECTOR BUFFER

JMP SETUP
HLT

7402

/HARD PARITY ERROR

/THE TRANSFER REQUEST FLAG IS SET
/

/TRANSFER DATA FROM THE PROGRAMS DATA BUFfFER TO THE RX84 SECYOR BUpfrER
/

9306
8307
@310
p311

1410
6702
7200
5274

FiLbl,

TAD | Al

/VIA AUTO INDEX REGISTER 10

XDR
CLA
JMP LOOP

Figure 4-10

/70 THE RXB1 SECTOR BUFFER
/GLA BECAUSE 10T XDR DOESN'T
/LO0P UNTIL THE DONE FLAG SETS

Fill Buffer Example

4.6 RESTRICTIONS AND PROGRAMMING PITFALLS

A set of 11 restrictions and programming pitfalls for the RX8E is presented below.
1..

When performing the following sequence of instructions, interrupts must be off.
> STR
SKP
JMP

SDN
JMP

(done)

(fill or empty buffer) <=

If interrupts are not off, the following sequence of events will occur. Assume interrupts are enabled and
the RXSE issues an interrupt request just before the SDN instruction. The SDN instruction will be
executed as the last legal instruction before the processor takes over. However, since the Done flag is

cleared by the SDN instruction, the processor will not find the device that issued the interrupt.
The program must issue an SER instruction to test for errors following an SDN instruction.

For maximum data throughput for consecutive writes or reads in 8-bit mode, interleave every three

sectors; in 12-bit mode, interleave every two sectors. (This of course depends on program overhead.)

When issuing the IOT XDR at the end of a function to test the status, the instruction AND 377 must be
given, because the most significant bits (0—3) contain part of the previous command word.

If an error occurs and the program executes a Read Error Register function (111) (Paragraph 4.4.7),a
parity error may occur for that command. The error code coming back would not be for the original
error in which the Read Error Register function was issued, but for the parity error resulting from the
Read Error Register function. Therefore, check for parity error with the Read Status function (101)
before checking for errors with the Read Error Register function (11 1).

The SEL DRV RDY bit is present only at the time of the Read Status function (101) for either drive, or

at completion of an Initialize for drive 0.

It is not necessary to load the Drive Select bit into the command word when the command is Fill Buffer
(000) or Empty Buffer (001).

Sector Addressing: 1—26 or 1-32g (No sector 0)

Track Addressing: 0—76 or 1-11454

If a Read Error Register function (111) is desired, the program must perform this function before a
Read Status function (101), because the content of the Error register is always modified by a Read
Status function.
10.

11.

The instructions STR, SDN, SER also clear the respective flags after testing, so that the software must

store these flags if future reference to them is needed after performing one of these instructions.

Excessive use of the Read Status function (101) will result in drastically decreased throughput, because a
Read Status function requires between one and two diskette revolutions or about 250 ms to complete.

4-15

4.7

ERROR RECOVERY

There are two error indications given by the RXS8E system. The Read Status function (Paragraph 4.4.5) will assemble
the current contents of the RXES (Paragraph 4.3.6), which can be sampled to determine errors. The Read Error

The results of the Read Status function or the Read Error Register function are in the Interface register when Done
sets, indicating the completion of the function. The XDR IOT must be issued to transfer the contents of the

Interface register to the PDP-8’s AC.
NOTE

A Read Status function is not necessary if the DRV RDY bit is
not going to be interrogated, because the RXES is in the

Interface register at the completion of every function.
The error codes for the Read Error Register function are presented below.

Octal

Code

Error Code Meaning

0010

Drive O failed to see home on Initialize.

0020

Drive 1 failed to see home on Initialize.

0030

Found home when stepping out 10 tracks for INIT.

0040

Tried to access a track greater than 77.

0050

Home was found before desired track was reached.

0060

Self-diagnostic error.

0070

Desired sector could not be found after looking at 52 headers (2 revolutions).

0110

More than 40 us and no SEP clock seen.

0120

A preamble could not be found.

0130

Preamble found but no I/O mark found within allowable time span.

0140

CRC error on what we thought was a header.

0150

The header track address of a good header does not compare with the desired track.

0160

Too many tries for an IDAM (identifies header).

0170

Data AM not found in allotted time.

0200

CRC error on reading the sector from the disk. No code appears in the ERREG.

0210

All parity errors.

4-16

CHAPTER 5
THEORY OF OPERATION

This chapter presents a discussion of the hardware and yCPU firmware of the RX11 and RX8 Floppy Disk Systems.
This information, combined with the programming information and functional descriptions contained in Chapters 3
and 4, should give the reader a complete knowledge of the theory of operation of the RX11 and RX8 Floppy Disk
Systems.

The first section of this chapter describes the overall system block diagram and the signals that interconnect each of
the blocks. The second section presents a detailed block diagram and logic discussion of each of the system blocks.
The uCPU microprogram is discussed in Paragraphs 5.2.4 and 5.2.5.
5.1

OVERALL SYSTEM BLOCK DIAGRAM

The floppy disk system consists of four elements (Figure 5-1):

Drive mechanics, which includes actuators and transducers (up to two per controller)

Read/write electronics, which translates power levels between drive mechanics and control logic

Microprogrammed controller, which includes all control logic.

Bus interface, which translates between host processor bus protocol (Unibus or Omnibus) and RXO01
data bus

RXO1
DATA BUS

DISK DRIVE

RX8

INTERFACE

8
o

INTERFACE "\

DRIVE

‘

READ/WRITE

ELECTRONICS

M CPU
CONTROLLER

RX 11

INTERFACE

v
N

B
S

CP-1520

Figure 5-1

Bus Structure

5-1

TIETHE

There are three levels of data transmission in the floppy disk system (Figure 5-1):

Unibus for PDP-11 or Omnibus for PDP-8 for data transmission between bus interface and host
processor

RXO01 data bus for data transmission between the RX01 uCPU controller and the bus interface

The disk drive interface for data and control information transmission between the read/write

electronics and the RX01 uCPU controller.

Signals between the read/write electronics and mechanical drive are analog signals used to control head motion and
sense diskette motion and position. The sections which follow describe the signals used in the three levels of data

transmission and the analog signals between the read/write electronics and mechanical drive.
5.1.1

Omnibus to RX8E Interface Signals

The RXSE interface communicates with the PDP-8 Omnibus via the signals shown in Figure 5-2 and described

below. These signals are further explained in the PDP-8 Small Computer Handbook.

DATA BUS (12)

MEMORY DATA BUS (9)
TP3

TP4 H

RX 8E

INTERNAL I/0 L

INTERFACE

SKIP L

nwCcCo—=20

INT RQST L

co,Cl
INIT H
I/0 PAUSE

V
CcP-1521

Figure 5-2 Omnibus to RX8E Interface Signals

DATA BUS — Twelve parallel bits of data are transferred along a bidirectional bus for both input and output data
between the AC register in the processor and the Interface register in the RX8E interface.

MEMORY DATA BUS — This signal provides 1/O transfer (IOT) instructions from memory to the RX8E interface.
TP3 H, TP4 H — These signals are used to clear the flag and clock the Interface register of the RX8E interface in

transferring data along the data bus.

INTERNAL I/O L — This signal is grounded by the RX8E interface selector decoder to inhibit decoding any internal
Omnibus 1/O transfer (IOT) instructions. Failure to ground this line will result in long IOT timing.

SKIP L — An IOT checks the flag for a ONE state. If the flag is set, SKIP L is asserted and the address of the
program counter (PC) plus one is loaded into the Central Processor Memory Address (CPMA) register to implement a
skip.

5-2

INT RQST L — This signal is part of the interrupt structure of the Omnibus. It is the method by which the RXS8E
interface signals the processor that it has data to be serviced.

C0, C1 — Signals CO and C1 determine the type of transfer between the RX8E interface and the processor. These
signals control the data path within the processor and determine if data is to be placed on the data bus or received
from the data bus. They are also used to develop the necessary load control signals required to load either the
accumulator (AC) or the program counter (PC) in the processor.

INIT

H — INIT H is a signal used to clear all flags in the RX8E interface and initialize the RX01.

I/O PAUSE L — This signal is used to gate the RXS8E select and operation codes into the programmed I/O interface
of the PDP-8 decoders.

5.1.2 Unibus to RX11 Interface Signals

The RX11 interface communicates with the PDP-11 Unibus via the signals shown in Figure 5-3 and described below.

These signals are further explained in the PDP-11 Peripherals Handbook.

QADDRESS SIGNAL (18)

<—DATA SIGNAL (16)

)

MSYN L

NPR

INT ERFACE

clL

wnwcmw—=Z2C

SSYN L
RX1

INIT

INTR L
SACK L
BBSY

BR(7:4)
BG(7:4)
L

cpP-1522

Figure 5-3

Unibus to RX11 Interface Signals

ADDRESS (A Lines) — The 18 address lines are used by the CPU to select the device register addresses of the RX11,
which are 177170 (RXCS) and 177172 (RXDB).

DATA (D Lines) — The 16 parallel data lines are used to transfer information in and out of the RX11 interface.

MSYN L — This signal is the master synchronization control signal that is initiated by the RX11 when it has control
of the Unibus for data transmission.

SSYN L — This signal is the slave synchronization control signal that is initiated by the RX11 in response to an

MSYN L signal from the processor or another device that has control of the Unibus and is about to send data to the
RX11.

5-3

NPR L — This signal from the processor will inhibit the RX11 interface from issuing a bus grant.
NOTE

The RX11

is not an NPR device.

Cl L — This bus signal is coded by the master device to control the slave in Data In mode (passing data to the
Unibus) if it is negated and Data Out mode (passing data from the Unibus) if it is asserted.
INIT L — This is the signal asserted by the processor when the START key on the console is depressed, when a
RESET instruction is executed, or when the power fail sequence occurs. This signal will initialize the RX11 system.

INTR L — This signal is asserted by the RX11 when it has bus control during an interrupt sequence. It directs the
processor to go to interrupt service routine.

SACK L — This signal is sent by the RX11 to the processor in acknowledgment of Unibus control being transferred
to it. This signal inhibits further bus grants by the processor.

BBSY L — This is the signal sent by the RX11 when asserting master control of the Unibus. This signal follows the
SACK L signal.

BR (7:4) — These four priority bus request lines are used by the RX11 to request bus mastership. Each device of the
same priority level passes a grant signal to the next device on the line, unless it has requested bus control; in this
case, the requesting device blocks the signal from the following devices and assumes bus control.

BG (7:4) — These are four priority bus grant lines corresponding to the four request lines. The processor uses them
to respond to a specific bus request.
5.1.3

Interface to uCPU Controller Signals

The uCPU controller and RX8E or RX11 interface communicate via the signals shown in Figure 5-4 and described
below.

DATA L
DONE L
TRANSFER REQUEST L

HIFT

SHIFT

1CPU

RXSE

OUT L

CONTROLLER

ERROR L

RUN L

INIT

RX
11

INTERFACE

12 BIT L

<— (RX8E ONLY)
CP-1523

Figure 54

Interface to uCPU Controller Signals

INIT L — The RXO01 will negate DONE L and move the head position mechanism of drive 1 (if it exists) to track O.
The RX01 will also read sector 1 of track 1 of drive 0 and then assert DONE L without error upon successful
completion of the function.

DONE L — Asserted low, DONE L indicates that there is no RX01 function in progress. Initiating any function will
cause DONE L to go false for the duration of that function. Attempting to initiate any function other than Initialize
while DONE L is false is illegal and may result in an error.

TTEETE

RUN L — RUN L initiates communication between interface and controller. RUN L, asserted while DONE L is true,
passes a command from interface to controller serially. DONE L will go false until the command has been executed
(or until Initialize is asserted). RUN L, asserted while DONE L is false, signals transfer of data to or from the
controller. All control lines to the controller must be stable 75 ns before RUN L is asserted.

OUT L — OUT L signals the direction in which the RXO01 is prepared to transfer data. When OUT L is asserted, the
direction of transfer is from controller to interface. When OUT L is negated, the direction is from interface to

controller. OUT L is never asserted while DONE L is true, and OUT L is negated by Initialize.

TRANSFER REQUESTL (TR L) — The TR L line, with RUN L and OUT L, forms a bidirectional handshake set.
On transfers from controller to interface (OUT L asserted), TR L going true indicates that the next data element has
been transferred to the Interface register. The transfer of the following data element will be initiated by asserting
RUN L. This will negate TR L until the new data element has been assembled in the interface.

On transfers from interface to controller (OUT L negated), TR asserted indicates that the controller is prepared to

accept the next element of data. The arrival of the new data element will be signaled by assertion of RUN L.
Assertion of RUN L while TR L is negated is an error.

DATA L — DATA L is a bidirectional line for transfer of data to and from the controller. A parity bit is appended to
the serial data stream by the interface when the direction of the data transfer is into the controller. The controller
will interrogate the parity bit for validity.

SHIFT I — The SHIFT L pulse strobes information to or from the controller bit-by-bit.

Interface to Controller Transfer — The transfer of either commands or data words begins with assertion
of RUN L. Following the assertion of RUN L, DONE L or TR L will be negated and a number of SHIFT
L pulses will occur. The number depends on the length of the data element to be passed. The first bit of
data (or command) must be stable when RUN L is asserted. The SHIFT L pulse width is 200 ns nominal.
SHIFT L pulses will not occur more often than every 400 ns. Subsequent bits of data may be brought up
on the trailing edge of SHIFT L. DONE L or TR L will be reasserted following the last SHIFT L pulse.

Controller to Interface Transfer — The assertion of TR L indicates the controllers readiness to transfer
data. Assertion of RUN L will negate TR L and initiate a train of SHIFT L pulses. The data is to be
sampled on the leading edge of SHIFT L and is valid only while SHIFT L is asserted. TR L will be
reasserted at the end of each element of data. DONE L will be asserted following transfer of the last
element of data in a block.

12 BIT L — This signal is asserted by the interface to controller and determines the number of shift pulses generated

by the controller for each byte transferred.

Signal 12 BIT L asserted will produce 12 SHIFT L pulses for data transfer between the interface and controller upon
the assertion of RUN L. Signal 12 BIT L negated will produce eight SHIFT L pulses for data transfer between the
interface and controller upon the assertion of RUN L. This line must remain asserted throughout the entire data
transfer. When data is transferred, the most significant bit is transferred first.
NOTE

Signal 12 BIT L is only asserted by the RXS8E interface for
PDP-8 12-bit words. It is never asserted by the RX11 interface.

ERROR I — This is an error summary bit generated by the controller that sets when any error is detected
(Paragraphs 3.2.1 and 4.3.6). The detection of ERROR L stops all controller action and asserts DONE L and the
Error flag. This line is cleared by INIT L or the initiation of a new function.

5.1.4

uCPU Controller to Read/Write Electronics Signals

The puCPU controller and read/write electronics communicate via the signals shown in Figure 5-5 and described

below.

WRITE GATE H
ERASE GATE H
LOW CURH
LD HD H
WRITE DATA

HD STEP H

R/W

ELECTRONICS

HD DIROUTH

1 CPU
CONTROLLER

SEL TRK OH

SEL INDEXH
RAW DATA L

SEL1H
DC LO
L

CP-1524

Figure 5-5

uCPU Controller to Read/Write Electronics Signals

LOW CUR H — This signal is asserted by the controller to select the lower of two write current levels when operating
on a track above 43. As the head moves closer to the center of the disk, the bit density increases as linear velocity

decreases, necessitating a reduction in write current.
WRITE DATA H — This signal conveys the complete data stream to the read/wnte electronics at TTL logic levels.

Each transition on this line resultsin a flux reversal on the disk.
In general, the pattern will be one clock transition every 4 us with an intervening transition between two successive

clocks to represent a data one and no intervening transition to represent a data zero. It should be noted that the data
content of this stream cannot be inferred from its instantaneous logic level, but only from the pattern of its

transitions (Paragraph 1.3.2).
RAW DATA L — This signal conveys the complete data stream recovered from the diskette at TTL logic levels. It
includes a regular pattern of clock transitions which the controller will separate from the data transitions. As above,

the data content is in the pattern of transitions rather than the absolute level at any instant of time (Paragraph

1.3.2).
SEL 1 H — This signal uniquely selects one of the two possible diskette drives. The assertion of this line will select
logical drive 1 for use. Unit O is physically the left-hand unit in the rack.

WRITE GATE H — This signal is asserted by the controller to enable the selected write drivers. This level must be
asserted prior to the beginning of the data field to be written and is negated after the last bit of the data field. This
timing is completely under microprogram control.

ERASE GATE H — This signal is used in conjunction with WRITE GATE H to enable the tunnel erase drivers. It is
asserted and negated after the assertion of WRITE GATE H, with timing determined by the microprogrammed
controller.
LD HD H — This signal is asserted by the controller to hold the media against the selected head.

TR
T

HD STEP I, — This signal is asserted twice by the controller to change head position by one track in a direction
determined by signal HD DIR OUT H. The maximum step rate is 10 ms per step. Minimum pulse width is 200 ns.
H — This signal determines the direction in which the head will move in response to an HD STEP L
HD DIR OUT
signal. If HD DIR OUT H is unasserted, the heads will travel toward the center of the disk (IN), increasing the track
address. If HD STEP L is asserted when HD DIR OUT H is asserted, the heads will travel toward the outside edge of
the disk (OUT), decreasing the track address.

SEL TRK 0 H — This signal is asserted by the selected drive to indicate that its head is positioned over track O.

SEL INDEX H — This signal is asserted by the selected drive to indicate that the hard index hole has been detected.
This occurs once per revolution and is used by the control to time operations and detect “up to speed.” This pulse is
400 us minimum width.

DC LO L — This signal is asserted by an Initialize signal from the controller to the drives.

to Drive Signals
5.1.5 Read/Write Electronics
The read/write electronics and drive(s) communicate through five sets of signals per drive as shown in Figure 5-6 and
described below. The plug designations for the cabling are also shown in Figure 5-6.

DRIVE

HEAD

INDEX

TRACK 00

HEAD STEPPER

HEAD LOAD SOLENOID

P5
READ/WRITE

ELECTRONICS

DRIVE

HEAD

INDEX

TRACK 00

P7 ,

HEAD STEPPER

HEAD LOAD SOLENOID

CP-1525

Figure 5-6 Read/Write Electronics to Drive Signals

HEAD — This is an analog signal to and from the drive head.

INDEX — This is a set of signals connected to a LED-phototransistor pair which locates the index hole for
determination of diskette rotational position and speed.

TRACK 00 — This is a set of signals connected to a LED-phototransistor pair, which indicates positioning at track O.
HEAD STEPPER — This signal is output from the read/write electronics, which moves the head from track to track.

read/write
HEAD LOAD SOLENOID — These signals activate a solenoid to load the head onto the diskette during a read/write
a
g
performin
not
when
wear
diskette
operation. The head is unloaded from the diskette to reduce
operation.

5.2

DETAILED BLOCK DIAGRAM AND LOGIC DISCUSSION

This section presents a detailed block diagram and logic discussion of each of the system blocks of Paragraph 5.1 and
a discussion of the pCPU instruction set and microprogram. The logic discussion makes references to the engineering

drawings included in the RX11 and RX8 Print Sets, which are separate documents.
5.2.1

RXSE Interface

Figure 5-7 presents a block diagram of the RXS8E interface. The page references in the following discussion are from
the RX8 Print Set, which is a separate document.
5.2.1.1 Device Select and IOT Decoder — The Device Select and IOT Decoder Logic, shown on page D2, decodes
RX8E instructions from the memory data bus and generates signals to the Interrupt Control and Skip Logic, the C

Line Control Logic, and the Sequence and Function Control Logic. Device selection codes are determined by the
switch configuration with relation to the state of MD6, MD7, and MD8. When the correct code for the RXS8E is
input to the Device Select Logic on MD03 L to MDO8 L and I/O PAUSE L is asserted, MD09 L to MD11 L are

decoded by the 7442 decoder, and signal INTERNAL I/O L is asserted on the Omnibus. I/O PAUSE L is present
anytime an IOT instruction is being executed by the program. INTERNAL I/O L prevents the processor from

executing other I/O transfers (IOTs) while this instruction is being executed.

The 7442 is a BCD to decimal decoder. All Os applied to inputs A, B, and C (C is MSB) will cause pin 1, which is
unused, to be asserted low. An input of 001 (C is MSB) will cause signal LCD IOT L to be asserted. An input of 010

(decimal 2) will cause XFER IOT L to be asserted. Therefore, for each function code input on MDO9 L to MD11 L,
only one of the output lines of the 7442 will be asserted. The function codes are further explained in Paragraph 4 .4.

5.2.1.2 Interrupt Control and Skip Logic — The Interrupt Control Logic, shown on page D2, asserts the BUS INT
RQST L signal on the Omnibus. Bit 11 of the data bus must be set and an INTERRUPT IOT L must be decoded by

the RX8E to set the Interrupt Enable flip-flop. The combination of the Interrupt Enable and Buffered Done
flip-flops will assert BUS INT RQST L. Setting the Buffered Done flip-flop indicates that no RXO01 function is
currently in progress.

The Skip Logic implements the three IOT commands Skip on Transfer Request Flag (STR), Skip on Error Flag
(SER), and Skip on Done Flag (SDN) as described in Paragraph 4.2.
NOTE

When using these instructions, the respective flags are cleared

after they are tested (Paragraph 4.6).

Signal SKIP L will be asserted if any of the above instructions are decoded by the IOT decoder and the respective
flag has been asserted by the RX01.
The RX8E asserts the RXS8E flags by causing a positive transition on the clock inputs of flip-flops XFER REQ, ERR,
and DONE. The signal MAINT (1) L will directly set the Skip flags to allow the Skip IOTs to assert the BUS SKIP L
signal when decoded by the IOT decoder.
5.2.1.3

C Line Select Logic — The C Line Select Logic (page D3) controls the direction of data flow between the

processor AC and the data bus and determines whether or not the AC is cleared upon completion of the transfer.

CO L will be asserted during an LCD (Load Command) instruction when signal LCD IOT L is asserted. Assertion of
C1 L requires XFER IOT H to be asserted and either MAINT (1) L or B DONE L to be asserted or WRT H to be

negated. Data transfers occur under the control of the C bits according to Table 5-1.

5-8

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Table 5-1

C Line Transfer Control Signals
Type of Transfer

Action Required by RXS8E Interface

Output AC to

Load data bus into buffer.

Action by Processor

Transfers AC to data

data bus; AC

bus. AC remains

unchanged.

Output AC to

data bus; AC

Load data bus into buffer. Ground

Transfers AC to data

CO.

bus and clears AC.

cleared.

Input AC ORed

with peripheral data

Jam input data

bus to AC.

5.2.1.4

Gate peripheral data to data bus.

AC ORed with

Ground C1.

peripheral data.

‘Gate peripheral data to data bus.

Transfers data bus

Ground CO and C1.

to AC register.

Interface Register — The Interface register shown on page D3 is made up of three 8271 4-bit shift registers.

This register temporarily stores data during transfers from the Omnibus to the RX01 uCPU controller or during
transfers from the RX01 uCPU controller to the Omnibus.

During a data transfer from the Omnibus (Fill Buffer), the 12 parallel data lines to the register are enabled by signal
RX8 SEL L from the Device Select Logic. Data is parallel loaded into the register when signals ENB BUFF LOAD L

and CLK BUFF L are asserted. In shifting data out of the register serially for transmission to the uCPU controller,
ENB BUFF LOAD L must be negated. Signal CLK BUFF L from the Sequence and Function Control Logic clocks
data out of the buffer (Paragraph 5.2.1.5).

During data transfer to the Omnibus (Empty Buffer), serial data from the yCPU controller is shifted into the buffer.
ENB BUFF LOAD L must be negated while CLK BUFF L supplies the clock pulses. The parallel data is enabled

from the outputs of the register when MAINT (1) H, RD H, or B DONE H is asserted, and when XFER IOT L is

asserted as decoded by the IOT decoder. Only eight bits of data will be output if signal 8/12 (0) H is low; otherwise,
12 bits will be transmitted.

5.2.1.5 Sequence and Function Control Logic — The Sequence and Function Control Logic shown on pages D2 and
D3 performs six distinct functions:

Controls loading and shifting of the Interface register to and from the uCPU controller.

Senses 8- or 12-bit mode and outputs RX 12 BIT L.

Senses maintenance conditions.

Generates INIT L signal to the uCPU controller.

Generates RUN L signal to the uCPU controller.

Generates a parity bit for the serial bit stream to the RXO01.

Interface register operation is controlled by signals ENB BUFF LOAD L and CLK BUFF L generated by the
Sequence and Function Control Logic. To assert ENB BUFF LOAD L, signal RX OUT L cannot be asserted and

either RX TRANSFER REQUEST L or RX DONE L must be asserted.

5-10

In parallel data entry to the buffer, CLK BUFF L will be asserted if any of the following conditions hold:
1.

ENB BUFF LOAD L is asserted.

Either LCD or XDR instructions are being performed.

Signal BUS TP3 H is asserted.

In serial data entry to the buffer, the CLK BUFF L pulses are derived from the RX SHIFT L pulses from the uCPU
controller.

The 8/12 flip-flop will set and signal 8/12 (1) H will be asserted if BUS DATA 5 L is asserted during a Load
Command (LCD) operation. Signal 8/12 (1) H is used to control whether 8 or 12 bits of data are transferred to or
from the Omnibus and whether 8 or 12 bits of data are transferred between the RX8E and the uCPU controller.
The MAINT flip-flop will set, and signal MAINT (1) H will be asserted if BUS DATA 4 Lis asserted during a LCD
operation. Signal MAINT (1) H is used to allow parallel writing and reading of the Interface register from the
Omnibus. It is also used to assert signal RUN L and C Line Control signals.

An Initialize signal to the uCPU controller (RX INIT L) is generated either by a BUS INIT H signal from the
Omnibus or an INIT IOT L decoded from the IOT decoder.

The RUN L signal, which is used to initiate communication between the interface and uCPU controller, is asserted
by setting the Run flip-flop. This flip-flop is clocked either in Command Transfer mode when LCD IOT H is asserted
or Data Transfer mode to or from the pCPU controller when XFER IOT H is asserted. (RUN L cannot be asserted if
DONE L is asserted.) RX BUSY L and INIT L must both be high for a RUN L signal to be asserted. Assertion of
either RX BUSY L or INIT L will clear the Run flip-flop.
5.2.2

RX11 Interface

A block diagram of the RX11 interface is shown in Figure 5-8. In the following discussion, it is assumed that the
reader is familiar with Unibus operations as described in the PDP-11 Peripherals and Interfacing Handbook. Page
references are to the RX11 Print Set, which is a separate document.

52.2.1 Address Decoder — The address decoder determines whether its associated RX11 is being addressed and
whether control information or data is being transferred.

The hardware on page D2 is a combinational logic network that decodes two discrete addresses assigned to the
RX11. Address bits (17:13) must always be asserted to satisfy the decoder. The state of address bits A (12:03) is
determined by the placement of jumpers Al2 through A3 on the board. For each of these bits, one 8242
exclusive-NOR gate is used. Insertion of a jumper for a particular bit position stores a 0 on one leg of the 8242, so
that a 1 appearing on the other leg causes the output to go low. This is a mismatch condition which is met when the
associated address bit is a 1. When both legs match (1s or Os on both), the output is high. The output of these 12
gates are wire-ORed and applied to pin 9 of the 7400 NAND gate. Pin 10 of this gate receives the NANDed signal of
A (17:13) and BUS MSYN. Pin 8, the output of this gate, is signal REG SELECT L and is asserted when the proper

Unibus addresses are decoded.

The states of address bits A02 and AO1 and REG SELECT L are used to produce signals D2 SELECT 00 H or D2
SELECT 02 H. The state of AO1 determines which of the mutually exclusive signals, D2 SELECT 00 H or D2
SELECT 02 H, is generated. If BUS AO1 L is asserted, D2 SELECT 02 H is asserted. If BUS A0l L is negated, D2
SELECT 00 H is asserted. These signals, in turn, allow access to the RXCS register as in the case of D2 SELECT 00
H asserted, or to the RXDB register as in the case of D2 SELECT 02 H asserted. (Refer to Paragraph 3.2 for register
descriptions.)

5-11

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5.2.2.2 Data Path Selection — Data Path Selection Logic is shown on pages D2 and D3. Signal BUS C1 L from the

Unibus controls whether Data Out or Data In operation is to be executed. Assertion of BUS C1 L indicates Data Out
(from Unibus), and negation of BUS C1 L indicates Data In (to Unibus). Signals D2 OUT H and its complement D2
IN H from page D2 are derived from BUS C1 L and are input to the rest of the Data Path Selection Logic on page
D3. With BUS C1 L negated and D2 SELECT 02 H asserted, all eight bits from the data buffer are enabled through
the 8838 bus transceivers. With BUS C1 L negated and D2 SELECT 00 H asserted, only lines BUS D04 through BUS
D07, providing control and status information (RXCS), are enabled. With BUS C1 L asserted, none of the 8838s are
enabled, and data is being input from the Unibus on lines BUS D0OO through BUS D07.

The 74157 multiplexer controls passage of status and control information (RXCS) in the form of signals D3 DONE
H, D3 INT ENB (1) H, and D3 TRANSFER REQUEST H from the Sequence and Function Control Logic or passage
of data from the Read/Write Data Buffer register (RXDB). If D2 SELECT 02 H is asserted, then data is output from
the 74157. If D2 SELECT 02 H is negated, then control information (RXCS) is output from the 74157.
5.2.2.3 Interface Register — The Interface register is a 74199 eight-bit, parallel load, shift register shown on page
D3. Data transfer through the register can take place from the Unibus to the uCPU controller or from the uCPU
controller to the Unibus.

In data transfer to the RX11 from the Unibus, parallel data is loaded into the register when D3 RX BUSY H is
negated and D3 LOAD H is asserted. Data is serially shifted in the register from Qp to Qg by the D3 B SHIFT H
signal derived from the uCPU controller when D3 RX BUSY H is asserted. Serial data is shifted to the Sequence and
Function Control Logic, which transmits data to the uCPU controller (Paragraph 5.2.2.4).

Data is assembled in a serial fashion for parallel transfer on the Unibus. Serial data is input at D3 B SER DATAH
and shifted by D3 B SHIFT H when D3 RX BUSY H is asserted and D3 LOAD H is negated. The eight bits of
parallel data appearing at the output of the buffer are input to the Data Path Selection Logic for transmission to the
Unibus.

5.2.2.4 Sequence and Function Control Logic — The Sequence and Function Control Logic schematics are shown
on page D3 and in the lower left-hand corner of page D2. This portion of the RX11 interface provides key signals to
control the Interface register and the Interrupt Control Logic as shown in Figure 5-8. Operation of this circuitry is
controlled by signals from the uCPU controller and D2 SELECT 00 H and D2 SELECT 02 H from the address
decoder.

Signals RX TRANSFER REQUEST L, RX OUT L, RX DONE L, and RX RUN L control data transfer between the
interface and the uCPU controller. The RX RUN L signal from the RX11 interface initiates communication between
the RX11 interface and the uCPU controller. The Run flip-flop is set in passing either a command from interface to
controller or data between interface and controller. Run asserted while Done is true passes a command from
interface to controller. Run asserted while Done is false signals transfer of data to or from the controller.
Once a particular function has been decoded by the uCPU controller, it requests a data transfer by assertion of RX
TRANSFER REQUEST L. The access of the RXDB in the RX11 interface sets the Run flip-flop and thereby asserts
RX RUN L. The Run flip-flop is cleared either by assertion of D2 B INIT H or RX BUSY H. RX BUSY H is asserted
when both RX TRANSFER REQUEST L and RX DONE L are negated. Assertion of RX BUSY H also allows the
Interface register to shift serially in communicating between uCPU controller and interface.

RX OUT L from the uCPU controller determines in which direction the data transfer is about to take place. When

RX OUT L is asserted, the direction of data transfer is from controller to interface. When RX OUT L is negated, the
direction of data transfer is from interface to controller.

On transfers from controller to interface, assertion of RX TRANSFER REQUEST L indicates that the next data
element has been assembled in the RXDB. Transfer of the next data element is initiated by RX RUN L. On transfers
from interface to controller, assertion of RX TRANSFER REQUEST L indicates that the controller is prepared to
accept the next element of data. Arrival of the next data element will be signaled by assertion of RX RUN L.
5-13

The three signals D3 DONE H, D3 INT ENB (1) H, and D3 TRANSFER REQUEST H from the Sequence and
Function Control Logic to the Data Path Selection Logic represent the three bits that may be read in the Control

and Status (RXCS) register. A functional programming description of this register is given in Paragraph 3.3.
During serial data transfer from the RXDB, a 8281 binary counter and a 74H106 JK flip-flop are used to count eight

bits of data and to append the parity bit to the data element.
An error indication from the uCPU controller results in assertion of RX ERROR L. This indication is passed to the
Unibus when a read from the RXCS to the Unibus is performed. When this occurs, signal BUS D15 L is asserted.
5.2.2.5

Interrupt Control Logic — The Interrupt Control Logic, shown on page D2, is a combinational logic

network that receives and generates the control signals required for the RX11 to become bus master. With signals D3

DONE H and D3 INT ENB H both asserted, D2 BUS REQUEST L will be generated if the SACK and BBSY

flip-flops are not set. The D2 BUS REQUEST L signal is routed to the appropriate bus request line (normally BR5)
through the priority plug shown on page D3. Etch on the plug selects both request and grant lines. When the bus
grant signal is generated by the processor, it is routed via the priority plug and becomes signal D3 BG IN H. This

signal clocks the GRANT flip-flop and the SACK flip-flop. The SACK flip-flop is set because the RX11 had

requested bus mastership. The SACK flip-flop is cleared and the BBSY {flip-flop set when BUS BBSY L, BUS SSYN
L, and D3 BG IN H are negated on the Unibus. Thus the BUS BBSY L signal will be asserted again by the RX11,
which is now bus master. The BBSY signal is inverted and applied to the vector address generator, generating the
BUS INTR L signal and the vector address of 264.
5.2.2.6

Vector Address Generator — The vector address generator, shown on page D2, consists of eight bus drivers

that are used to generate a vector address and the BUS INTR L signals. When BUS BBSY L is asserted by the RX11,
the inputs to the bus drivers are active. Seven drivers are connected to the Unibus data lines D (08:02) via jumpers.

The placement of these jumpers determines the vector address.
5.2.3

Microprogrammed Controller (uCPU) Hardware — A block diagram of the uCPU controller is shown in Figure

5-9. The controller is a hardware microprocessor controlled by a ROM with 1536 eight-bit words; the ROM contains
the microprogram. This section discusses the various parts of the hardware while Paragraph 5.2.5 discusses the
microprogram.

5.2.3.1

Control

ROM and Memory

Buffer — The heart of the controller is the ROM, which contains the

microprogram shown on page D6. All control and processing activities executed by the RX01 are controlled by the

microcode sequences stored within the ROM. The ROM is divided into six fields, each with a storage capacity of 256

eight-bit words. Sequencing through the ROM microcode is accomplished by updating the contents of the program

counter (PC) every 200 ns. The eight bits from the PC indicate the address of the next instruction to be executed.
The eight-bit instruction addressed by the PC is loaded into the memory buffer on assertion of LD MB + CLK PC L.
Each instruction consists of three fields that are sampled by the uCPU logic circuits to allow processing action
appropriate to the instruction to be taken. The three fields can be defined as follows:

INST | INST | SEL

INSTRUCTION
CODE

SEL | SEL | SEL

{

SELECT
FIELD

FIELD

Ci
A

o
—~

CONTROL
FIELD
CcP-1531

5-14

—— RUN

RX RUN —fe]— (8640
~

12 BIT
RX

RX DATA

—}e
—t-e

RX INIT '—-e

RAW
DATA

DRIVE

Cvi

RCVR

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|12 BIT MODE

INTRF

(D2)

DATA

. DRV INIT

LOW
ORDC INIT

SELECT| FLD

(4LINES)

SEP DATA
[ SEP
DATA SEPERATOR
—
AND
SYNCRONIZER(D4) [—= MIS CLKCLK
DRV
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(D6).

] HINES)
|
FLD DECODE
|¢
ROM
FLD {'D| NES)
ENAB
:

SEL T

&l\;{j

(06)

(D6)

SELECT FLD

REG

ol— cLk 108 0

108 2
2l—CLK
S — oLk 108 3

12— CLK FLAG

CLK SCRATCH PAD
13—

14— CLK CNTR

DATA —2

CBR

SYN INDEX —|3

WBR

SR MSB —]4

I_— JUMP

CNTR OVFLW —15

CRC BIT16 —6 BRAN o
HOME 7 cONDITION
ECTOR

WRT PROT —8 SEL
SEP CLK —9
12 BIT MODE —10
sR7(3) SEP DATA —{!!
SEC BUF OVFLW

BRANCH

(08)

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T
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srR7

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SELECT
FLD

(4 LINES)

(D5)

(74174)

(4 LINES)

ADDR

REG

15— CLK SR

(D3)

[——NOSRATCHPAD

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OF 8 BITS (D3)

(BLINE)

1
'

(8 LINES)

(8266)(TWO)

CNT INPUT SEL

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(D3)

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(8 LINES

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BUFR
SEC
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e
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—s| INTRF/DRV INTERF/ D RV

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l
CNTR
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(8 LINES)

(D3)

(74194)(TWO)

LSB

SHIFT
REGISTER

‘
f

(D3)

2102)
SECTOR
BUF u FER
BUFR
s|> SEC
ONE Bleworn

PRESET CRC

CLKCLKUNITLD SELHD —8{(7474)
—» outoyT

CLK FLG —»] BUFFERD

(D7)

»_—.———)D_ ®

DATA
SEP

sR7(+)SEP DATA

\
?@MIS CLK
MIS- __)D—SR

CLK

DATA
RXRX SHIFT
DRV CONNECTOR

DRV WRT GATE
DRV
DIR
DRV HDHD STEP
DRV ERASE GATE
DRV LOW CUR

DRV UNIT SEL

DRV HD LD
DRV WRT DATA

DRV INDEX

SYNCRONIZER t—s

DRV TRk 00

HOME

INDEX

HD DIR OUT

(See note)

\J
,

(05) INDEX

DRV INIT

_
NOTE:

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o

RX OUT
RX DONE

.
.

FLAG
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)
>>SR MSB

DISK
BUS

(6)

(7408)

== GATING
(DS)os) F—

16 BITS

*..

(05)

(D5)

(D4)

DATA _1(74174)(THREE)
CRC
GENERATOR
BIT
CHECKER [—& CRC
—&

BUS — 1.
= DRIVERS
-o

OUT PUT

CLK
—=
CLK 0B0B S6 —

INTERFACE

INTERF

—»| BUFFER | . oo
0B34 —»f
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(6)

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.

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|

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(LD=0)
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LOAD SR
SHIFT ONE
SHIFT SEP DATA

CLK
CNTR

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GEN
TIMING

(0=LD)

CONTROL ROM

#CONTROL

SET CRC

(t=NCR)

FROM

(74891(TWO)

SEP DATA

UNTIL
BRANCHIS ASSTALL
WAIT
DESIRED
CONDITION
OR COUNTER OVERFLOW

INTERF/ DRV

WORD IS ADDRESS Ci=|

0
1
‘

8f— CLK LO HD

RUN —]0(74150)

INTERF DATA

ci0 | co0 SHIFT ZERO

9|—CLK BUF ADD REG
10— CLK SECTOR BUF
11— CLK CRC

0oB3 —!

]

JUMP TO FLD X N EXT

—t

(o7) |—=> TP4
EAR HLT SW —te
(1=4K
MODULE
MAINT
i COUNT)
CONNECTO
COUNT)
(O=1K

1}—CLK 10B 1

(4 LINES)

CONTIN SW

4. MEM FLD
DO PULSE FLD
00 INSTRUCTION
BRANCH
CONDITIONAL
01 GPEN
SCRATCHPAD

00 PULSE i"— cLk 1088
SELECT
(4 LINES)
FLD
GENERATOR —— CLK UNIT SEL

HLT SW .

CONTROL FLD- FUNCTION

CONDITIONS
2. BRANCH
3.D0 PULSES

Sb—CLK 10B5

R03)

= pROG%EJTCNTR e 8 BIT1536WORDS

(74154)

DEPENDS ON INSTRUCTION
’

OF 16
ONE
1. SCRATCH PAD REG

4f—cLK 10B 4

Ta751(TWO!

| (8 1.
(23-XXX42)(12)
CONTROL ROM | LINES)
(8 LINES)

LD SP ADDR
CBR
WBR
JUMP
DO

(D8)

INSTR
FLD
LINES)(2

(D6)

(74161) (TWO)

‘

WBR CLK CNTR

DECODER
—| INSTRUCTION

JUMP—=| FLD CNTR

PC LOAD-l

CONT INIT

4 3 1 2 I 1 | oJ MEMORY BUFFER
I'? T 6 ' 5 T
'

ronics

cP-1528

SEC BUFR ouT — |
FLAG

—

(D8)

Figure 5-9

uCPU Controller Block Diagram

5-15

The high-order two bits of the control word are the instruction code bits, INST 0 and INST 1. There are five types
of instructions, which are determined by these two bits and the C1 bit:
INST O

INST 1

Instruction

Do Pulse (DO)

Conditional Branch (CBR)

Open Scratch Pad (OSP) if C1 =0

Jump (JMP) if C1 =1
1

Wait Branch (WBR)

A more detailed explanation of the instruction set is given in Paragraph 5.2.4.

The function select field, consisting of the four bits designated SEL 0, SEL 1, SEL 2, and SEL 3, is used for either

subfunction selection or addressing. For example, DO instructions controlling the interface lines differentiate
between the Interface Buffer flip-flops based on the contents of the function select field. One select code sets the
Done flip-flop, another sets the Error flip-flop, etc. During an Open Scratch Pad instruction, the select lines convey

address information that is applied to the Scratch Pad Address register to address 1 of 16 Scratch Pad locations.
During a Jump instruction, the select lines specify which of the six ROM fields is to be selected.

Control field bits C1 and CO are the two low-order bits of the instruction. These bits are used not only to initiate
subfunctions of an instruction, but also to route data bits and addressing information within the uCPU controller.
For example, certain DO instructions that have the C1 bit asserted can be used to set an appropriate flip-flop in the

Interface register; when the C1 bit is negated, the same DO instruction clears the related flip-flop. Therefore, the

microprogram controls information flow between the interface and the read/write electronics.
5.2.3.2

Program Counter and Field Counter — The program counter and field counter, shown on page D6,

determine the next instruction word to be placed in the memory buffer. The contents of the program counter are
updated in one of two ways:
1.

Incrementing the present count by one when processing an uninterrupted series of DO instructions,

Open Scratch Pad instructions, and Branch instructions when the branch condition is not met.
2.

Loading a completely new eight-bit address into the program counter. Signal PC LOAD EN L from the
Branch Control Logic initiates such an operation during execution of either Branch instructions or the
Jump instruction. The new address originates from the ROM itself or from Scratch Pad memory. When

the ROM supplies the new address, it is contained in the location following that of the Branch or Jump
instruction.

The decision to increment the program counter or load a new eight-bit address is governed by the signals LD MB +
CLK PC L and PC LOAD EN L. When LD MB + CLK PC L is asserted, the counter is incremented, and when PC
-

LOAD EN L is asserted, a new address is loaded into the program counter.

The field counter selects which of the six ROM fields contains the next instruction to load into the memory buffer.

This counter can be incremented (e.g., when the firmware routine being executed spans two ROM fields) or parallel

loaded (e.g., in execution of all Jump instructions). The field address (O through 5) is conveyed over the four
function select lines SEL 0 to SEL 3.
5.2.3.3

Instruction Decode Logic — The Instruction Decode Logic (page D8) is a combinational logic circuit that

uses the two instruction field bits, INST O and INST 1, to generate the six signals (shown on Figure 5-9) that are

asserted when one of the five instructions is loaded into the memory buffer. The DO signal is input to the Do pulse
generator; WBR, CBR, and JMP signals are input to the Branch Control Logic; and the LD SP ADDR REG signal

goes to the Scratch Pad Address register. Instruction decoding is inhibited by setting the INST DIS flip-flop, which
occurs when the ROM word is an address word as opposed to an instruction. Assertion of signal INST DIS H always

occurs during a Branch or Jump instruction and a counter load operation.

5-16

5.2.3.4 Do Pulse Generator — Detection of a Do instruction by the instruction decoder and assertion of signal TP3
L will enable the Do pulse generator (page D5), which is a 74154 decoder. The function select bits determine which
of the outputs is asserted. All outputs supply clocking to various flip-flops, counters, and shift registers, depending
on the function select bits. If the select field is 0000, signal CLK IOB 0 is asserted; if the select field is 0001, signal
CLK IOB 1 is asserted; etc.

5.2.3.5 Branch Condition Selector and Control — The 74150 branch condition selector (page D8) is always enabled
during a Branch instruction. The function select field determines which data line is selected for input to the Branch
Control Logic. The output signals from the Branch Control Logic, PC LOAD EN L and LD MB + CLK PC L, are
used to either increment the program counter or load in a new address. LD MB + CLK PC L is also used to load the
memory buffer,

The C1 bit, which the firmware has converted to data, is compared with the output of the branch condition selector.
If the conditions match, the PC LOAD EN L and LD MB + CLK PC L signals are enabled. The WBR CLK CNTR L
signal is asserted when a WBR instruction is decoded by the instruction decoder.

5.2.3.6 Scratch Pad Address Register and Scratch Pad — During execution of an Open Scratch Pad instruction, the
function select field contains an address in the Scratch Pad. The four-bit function select field is input to the Scratch
Pad Address register (page D3), which consists of four D-type flip-flops. The function select field appears at the
output of this register upon assertion of the CLK SP ADDR REG L signal generated by the instruction decoder.

The Scratch Pad (page D3) itself consists of two 7489s (64-bit read/write memory), capable of storing 16 eight-bit
words. Data from the shift register is written into the address indicated by the Scratch Pad Address register when LD
SCRATCH PAD L is asserted. Reading occurs when this signal is negated. Data read out is input to the Counter
Input Selector Logic.

5.2.3.7 Counter Input Selector, Counter, and Shift Register — The counter input selector, counter, and shift
register (page D3) act as buffering circuitry for information flow in and out of the Scratch Pad. Signals CO and C1
control operation of this logic.

The counter input selector consists of two 8266 multiplexers that select eight parallel bits from either the ROM or
the Scratch Pad, depending on the state of CO(1) H. If CO(1) H is asserted, the Scratch Pad data is selected; if CO(1)
H is negated, the ROM data is selected. The state of CO is determined by the low order bit of the instruction code
from the memory buffer.

The outputs of the counter input selector are presented to both the program counter and the counter. During
execution of a Jump instruction and Branch instruction when the branch conditions are met, a new address is loaded
into the program counter. The control field of the instruction will determine the source of the new address. If the
source is the ROM, the address is in the location following the instruction. If the source is the Scratch Pad, some
previous calculation was performed to determine the new address.

The counter is made up of two 74161 synchronous four-bit counters. The output of the counter input selector is
loaded in the counter if signal C1(1) H is negated. If C1(1) H is asserted, the counter increments upon detection of
signal CLK CNTR L. During execution of a DO instruction, the Do pulse generator supplies the clocking signal if the
select field is correct. An overflow condition, indicated by all 1s in the counter, is detected by assertion of signal
CNTR OVFLW H, which is input to the branch condition selector.

Data output from the Scratch Pad counter is loaded into the shift regsiter if CO(1) L is asserted and C1(1) H is
negated. Data appears at the outputs after the positive transition of the clock input CLK SR L. When CO(1) L and
C1(1) H are asserted, data from the data separator is serially shifted into the shift register by signal CLK SR L.
Therefore, input to the Scratch Pad is either by way of serial data from the data separator or parallel data from the
counter. The data from the data separator originates from the read/write electronics during access from the diskette.
SRMSB, the MSB of the shift register, is exclusive-ORed with data [SEP DATA (1) L] and a missing clock indication
[MIS CLK (1) L] from the data separator for input to the branch condition selector. SRMSB (1) H alone is also
presented to the branch condition selector.
5-17

Bits can be shifted into the shift register via CLK SR L, CO, and C1. Signal SR LOAD H is asserted when CO(1) L is
asserted and C1(1) H is negated, allowing the shift register to be parallel loaded from the counter. With CO(1) H and
C1(1) H both asserted, SEP DATA from the data synchronizer and separator is serially input to the shift register. If
CO(1) L is negated, 1s and Os from the C1(1) H bit stream are loaded into the shift register. In summary, CO
determines shift or load of the shift register; C1 and SEP DATA are two serial bit streams.

5.2.3.8

CO0

Shift Zero

Load Shift Register

Shift One

Shift SEP DATA

uCPU Timing Generator — The uCPU timing generator, shown on page D7, produces signals TP3 and TP4,

which are used as timing signals for the rest of the uCPU controller. The 74H74 flip-flops are used as a wraparound

shift register to derive TP3 and TP4 from the 20 MHz oscillator. TP3 and TP4 are 5 MHz signals with a pulse width
of 50 ns. In normal operation, a recirculating 1 bit in this shift register causes TP3 to occur before TP4. Inputs to the

maintenance module connector and signal INIT + PC L control operation of this shift register.
5.2.3.9

Sector Buffer and Address Register — The 2102 sector buffer, which is a 1024-bit MOS RAM, and the

address register, composed of three 74161 synchronous four-bit counters, is shown on page D4. The address register

is used as a loop counter for the microprogram as well as an address register for the sector buffer. The ten LSB

inputs to the register are grounded, and the upper two MSB inputs are connected to signal CO(1) L.
When used as a loop counter or an address register, C1(1) H is negated and the ten LSB bits of the register are zero.
With C1(1) H asserted, the count is incremented by signal CLK BAR L, which occurs once per disk data bit. If CO(1)
L is asserted, the two MSB bits are also zero, enabling the counter to count 4096 clocks before the SEC BUF

OVFLW H signal is asserted. If CO(1) L is negated, the two MSB bits are one, enabling the counter to count only
1024 clocks before the SEC BUF OVFLW H signal is asserted.

Reading or writing is controlled by a flip-flop. If CO(1) H is asserted and CLK SEC BUF L is asserted, the write
enable line to the 2102 is asserted by setting the flip-flop. The CLK SEC BUF L signal is asserted twice per bit, once

to set the flip-flop and once again to clear it. It is cleared when CO(1) H is negated and the second CLK SEC BUF L

pulse is asserted. Data to be written in the sector buffer is contained in signal SEP DATA (1) L from the read/write
electronics while reading from the diskette; the data is contained in signal DATA I L from the interface while writing
on the diskette.

In reading data out of the sector buffer, the write enable line is negated, and the serial data stream appears at SEC
BUF OUT (1) H as the Buffer Address register is incremented.
5.2.3.10

CRC Generator and Checker — Each sector has a two-byte CRC character for the header field and another

two-byte CRC character for the data field (Figure 1-11). The CRC generator and checker shown on page D7
produces the CRC character to be written on the diskette and checks the CRC character read from the diskette.
A
16-bit shift register with properly placed exclusive-OR gates implements the polynomial divide algorithm. The CLK
CRC L signal clocks the shift register so that the entire header field or data field is divided by a selected CRC divisor

which is 21° + 212 + 2° + 1. The mathematical expression for this operation is:

an 20+ ... +a32> +a,2% +a,2" +2,2°
215+212+25+1

where a = coefficient of the bit position

n = number of bit positions in the data block

5-18

In writing data on the diskette, each bit is shifted through the CRC generator. This data stream appears on signal
C1(1) L and is produced by the firmware. Signal CO(1) L negated will enable this data stream to the CRC register.
After the data field has been written, the CRC register contains the remainder of the division, which is the two-byte
CRC character that is written after the data field.

During a read operation, the data stream from the data synchronizer and separator, SEP DATA (1) L, is enabled to
the CRC register. This data stream is manipulated in the same way as in the write operation. When the CRC
character on the diskette is encountered, it is shifted into the CRC generator as if it is part of the data stream. If all
the data and CRC bits that were previously written on the diskette are retrieved, the CRC register, which contains
the remainder of the division, should be zero. The contents of this register are input to the condition selector, where
the firmware checks to see that the register contents are all zero.

5.2.3.11 Data Synchronizer and Separator — The data synchronizer and separator (page D4) separates clocking
information from data, identifies missing clocks, and synchronizes the clock to the data. Clocking and data are
mixed in the output data stream (Paragraph 1.3.2). In the read/write electronics, one-shots set to produce 200 ns
pulses for each transition convert the flux reversal signals to a series of pulses as shown in Figure 5-10. The clock
pulses can be separated from the 1 data pulses as shown. If no data pulse occurs between two clock pulses, a O bit is
indicated. Notice that there is a clock pulse every 4 us.

FLUX

REVERSAL
STREAM

RAW DATA |
c

SEP CLOCK

—-|

SEP DATA

|~— 4 pusec

‘

MIS CLK

CP-1529

Figure 5-10

Data and Clock Separation

The data synchronizer and separator produces three outputs: separated clock (SEP CLK), separated data (SEP
DATA), and missing clock (MIS CLK). SEP DATA is one bit position delayed from the flux reversal stream. In the
example shown in Figure 5-10, there are no missing clock indications because the RAW DATA stream does have a
clock pulse every 4 us. The MIS CLK indication is used in locating the ID address mark of the sector header field and
the data or deleted data mark of the sector data field. (See Figure 1-9.) Each of these data marks is a unique

sequence of data and missing clocks that the microprogram identifies by examining the data synchronizer and
separator circuit.

Figure 5-11 is the ID address mark which contains missing clocks. Since clocks must occur every 4 us, the missing

clocks can be identified as C. SEP CLK output will include clock pulses that are separated by 6 us and will be out of
synchronization with the real clock pulses. SEP DATA will indicate a 1 bit when a data pulse exists between SEP
CLK pulses; it will indicate a O where there is no data pulse. As in the first case, SEP DATA is delayed by one clock
period. MIS CLK is also delayed by one clock period and occurs when SEP CLK pulses occur more than 5 us apart.

5-19

|11 2]3]4]5]6]7]8]
l'—‘- | D ADDRESS MARK
fil
—

-1

FLUX REVERSAL

RAW DATA

coct1ci1ci1cicicici1cococ
SEP CLK

SEP DATA
ed

I
—si

je— 4 uSec

Figure 5-11

MIS CLK

CP-1530

ID Address Mark Data Separation

The data synchronizer and separator uses two timing windows to separate data from clocks. If a pulse occurs within

3 us from a valid clock pulse, it is a data 1 bit. If it occurs between 3 and 5 us from a valid clock pulse, it is the next

clock pulse. If it occurs after 5 us, there was a MIS CLK. The logic is shown on page D4. The timing windows are
produced by two pairs of 74193 counters, which are preset to a given count and clocked by the 20 MHz clock after

it has been divided down to 10 MHz. The carry of these counters is used to clear flip-flops to provide timing
indications. The END WIND L signal from the 3 us timer clears the 74H103 flip-flop. The two following 74S74s

synchronize the data to the 20 MHz clock. The SEP DATA output delayed by one SEP CLK clock period appears at
the output of the 74H103. MIS CLK is produced when the 5 us timer issues a carry to clear the 74H103. SEP CLK is

produced by the 74H103 flip-flop, which is cleared by a state of the 3 us timer. The following flip-flop synchronizes
the SEP CLK signal with BTP3H.
5.2.3.12

Output Circuit — The output circuit shown on page D5 consists of the interface/drive output buffer, drive

output buffer, interface bus drivers, disk bus gating, and index synchronizer. Signals CLK I0BO0 to CLK IOB6 from
the Do pulse generator are used to clock the flip-flops in the interface/drive output buffer. The interface bus drivers
and the disk bus gating outputs are appropriate combinations of signals from the interface/drive output buffer that

are output to the interface or to the read/write electronics. IOBO selects the output bus to which the rest of the IOB
signals are to be assembled. A further explanation of these signals is given in Paragraphs 5.1.3 and 5.1.4.
The drive output buffer consists of three flip-flops,

FLAG, UNIT, and HD LD, which respectively produce signals

DRV WRT DATA, DRV SEL 1 H, and DRV HD LD H to the read/write electronics.
The index synchronizer consists of two flip-flops used to synchronize the SEL INDEX H signal from the read/write

electronics. The flip-flops are cleared and SYN INDEX (1) H is negated by the Do pulse generator. SYN INDEX (1)
H will be asserted by the first TP3 after the SEL INDEX H assertion and input to the branch condition selector.

5-20

5.2.4 Microprogram Instruction Repertoire — The firmware within the RX01 Read-Only Memory (ROM) employs
five different instruction types to implement the various control sequences used to process each function code.
Regardless of type, an instruction is made up of eight bits and contains three fields as shown below:

INSTRUCTION

SELECT

CONTROL

FIELD

CODE

FIELD

CP-1532

The RX01 uCPU controller distinguishes between the different instruction types by the content of the instruction
code field. The select field is used to define subfunctions of a single instruction type. This field is also used for
addressing locations in the uCPU Scratch Pad memory. The control field allows for still further definition of the
instruction purpose and, in one case, serves to distinguish between two instructions having the same instruction field
code. The five basic instructions executable by the uCPU controller are:
1.

DO instruction

Conditional Branch

Wait Branch

Open Scratch Pad

Jump

5.2.4.1

DO Instruction — The most frequently executed uCPU firmware instruction is the DO instruction. Its

format is:

—

INSTRUCTION

CODE

——

SELECT

FIELD

CONTROL

FIELD

CP-1533

Through use of different function select codes, the DO instruction is used to assert/negate many of the interface
lines going to both the interface and the read/write electronics. The DO instruction is also used in shifting data bits
to/from the interface for the Empty/Fill Buffer function and writing data bits onto the disk for the Write Sector
function. Furthermore, the DO instruction is used for function decoding, parity checking, CRC field
generation/detection, and numerous housekeeping functions inherent in the various uCPU controller sequences. A
complete breakdown of all DO instruction subfunctions is given in the RX8/RX11 Print Sets.

5-21

5.2.4.2

Conditional Branch — The Conditional Branch instruction is used to sample status conditions within the

RXO01. On detection of a given condition, a branch to another area of the ROM occurs. The format of the

Conditional Branch instruction is given below:

NSTR

UCTION CODE _:

O— BRANCH ADDRESS

FIELD

TAKEN FROM ROM

{ — BRANCH ADDRESS

TAKEN FROM OPEN
SCRATCH PAD

BRANCH WHEN

BRANCH

DEFINES CONDITION

CONDITION IS FALSE

BEING SAMPLED

WHEN

CONDITION IS TRUE
CP-1534

Many conditions are sampled by the Conditional Branch 'instruction; examples are 12-bit mode, drive ready,
read/write head located at track zero, and two index pulses have occurred. A complete breakdown of all Conditional
Branch subfunctions is given in the RX8/RX11 Print Sets.
5.2.4.3

Wait Branch — The Wait Branch instruction is similar to the Conditional Branch instruction; the difference

is that the Wait Branch instruction is used to stall uCPU controller operations until a given condition becomes true.
The format of the Wait Branch instruction is given below:

{

° F%%EE

]’

INSTRUCTION

O—- BRANCH ADDRESS

TAKEN FROM ROM

{ — BRANCH ADDRESS

TAKEN FROM OPEN
SCRATCH

DEFINES CONDITION
BEING SAMPLED

PAD

O -

BRANCH WHEN
CONDITION IS FALSE

{

BRANCH

-—

WHEN

CONDITION IS TRUE
CP-1535

A breakdown of all Wait Branch subfunctions is given in the RX8/RX11 Print Sets.
5.2.4.4

Open Scratch Pad — The Open Scratch Pad instruction is used to address (select) any of 16 locations in the

UCPU controller prior to executing a read/write operation. The format of the Open Scratch Pad instruction is given
below:

07
1t

06
|

0
yu

INSTRUCTION

SCRATCH

FIELD

ADDRESS

CODE

PAD

MusT

NOT

USED

ZERO
CP-1536

5-22

Some of the Scratch Pad memory locations are dedicated as fixed storage locations. For example, the first two

locations store the current track address for units O and 1, respectively. Error and Status register information is also
stored in fixed Scratch Pad locations. A breakdown of all Scratch Pad locations and their uses is given in the
RX8/RX11 Print Sets.
5.2.4.5

Jump — The Jump instruction has the same instruction code as the Open Scratch Pad instruction, but is

distinguished from the latter by the presence of a one in the bit 1 location. The Jump instruction format is shown
below:

|
o7

CODE

FIELD

~—

INSTRUCTION

00
o)

——

0- JUMP ADDRESS TAKEN

SELECT

ANY OF SIX

ROM

FROM ROM

FIELDS

| — JUMP ADDRESS TAKEN
FROM

OPEN SCRATCH PAD

MUST BE A1. DIFFERENTIAL
BETWEEN JUMP AND OPEN
SCRATCH PAD INSTRUCTION
CP-1537

5.2.5

Microprogram Flowchart Description

Since the microprogram controls the operation of the RX11 and RX8 Floppy Disk Systems, it is possible to
understand the hardware operation and not know how the system operates. This section gives an explanation of
UCPU controller operation as implemented by the microprogram. The flowcharts presented in Figures 5-12 to 5-21

serve to guide the reader through the rather complex microprogram which is listed in its entirety, along with a
complete instruction set and error code listing, in the RX11/RX8 Print Sets.
Figure 5-12 shows the operation of the system in response to an Initialize or Power Low signal, which clears the

system. Sector 1 of track 1 of drive O is located and read. The programmer can put anything he wants in this sector
to aid him in programming. Bus direction is established as being from drive to CPU and eight bits of status
information are moved to the interface. The Done flag is set and the controller waits for the RUN signal from the
interface. If this signal is not detected within 46 ms, the head is unloaded. Once the RUN signal is detected, the
Done flag is cleared and either 8-bit or 12-bit mode is detected. Parity is checked and, if found to be incorrect, an
error condition is indicated. Function decoding of bits 1-3 of the RXCS results in entering one of the seven
function flowchart branches. .

The Empty and Fill Buffer functions (Figure 5-13) are similar except that the Empty Buffer function occurs when
the bus direction is OUT and data moves from the drive to the CPU. The Fill Buffer function occurs when the bus

direction in IN and data moves from the CPU to the drive. In IN mode, the TR (Transfer Request) signal is set and

cleared after the interface responds with a RUN signal. Twelve- or eight-bit mode is checked, and either nine or
thirteen bits are moved from the interface to the buffer. The extra parity bit is checked. In OUT mode, no parity
bits are moved. The byte count is incremented and checked to see if the buffer is full for a Fill Buffer function or
empty for an Empty Buffer function. If not, the cycle repeats until the condition is met, at which time status is
checked and DONE is asserted. Now another function can be decoded.

Decoding a Read Sector function (Figure 5-14) will cause a branch to a subroutine to get the diskette address and
find the track and sector. Three tries are allowed to find the data mark or a format error will be indicated. Once it is
found, the Data Mark bit will be set to either a O or a 1, depending on whether the Deleted Data Mark bit is set. A
CRC character is generated as 1024 bits are loaded into the sector buffer. If the CRC is correct, status is checked by
a branch back to the DONE condition; otherwise, an error will be indicated.

5-23

— REFERS TO 1°'S COMPLEMENT

(X) MEANS CONTENTS OF REG X

—

INIT OR POWER

LOW CLRS PC.

FLAG = ZERO

TIMING RESUMES

UPON NEGATION
OF INIT OR

-0— TEMPD

POWER LOW

-0~ CURTKO
-0— CURTK1

’

( OK DONE

’

;

20, - ERREG

10, — CNTR

[DRV 1 HOME

[DRV 0 HOME

(CNTR) —~ ERREG

IN -~ DATA DIR

COULD NOT

BE FOUND]

0~ ERREG

( GOERDN

FLAG = ONE

-1- TARSEC

CLR DONE

-1 - TARTRK

SET DONE

CLR XFRQ

GOERDN
262,

— R5

GET COMMAND

SELECT DISK BUS

FLAG = ZERO

125, - R10
DLY 20

[-COMMAND — SR]

SELECT INTRF BUS

FLAG = ONE

\
SHIFT SR 3 TIMES

SET FLAG

SET ERR

FOR UNITBIT IN

CLR ERR

‘
SET FLAG

SELECT UNIT ONE

SR7

SELECT UNIT ZERO

SAVE UNIT IN

]
FLAG = ONE

RD ERREG

OPEN STAT

OPEN ERREG

FLAG.

UNIT 0= FLAG ON

CHECK READY

FLAG = ZERO

[FOR DRV 0]

IN - HD DIR

NOT RDY

(R5) — SR

RDY

SHIFT SR ONCE

(OPEN SP) — SR

FOR FUNCTION

-10 - SR

OK DONE

BIT

CLR SHIFT
CLR DONE
CLR XFRQ

SR =252,

SR # 252,

fe—

(R10) — SR

BOOTSTRAP

STEP HEAD

}

ECTOR 1

DONE

SELECT INTERF BUS

SET ERR

SR7 = ZERO

SR7 = ONE

[FIND TRK 1

FOR 2ND FUNC

SHIFT SR ONCE
FOR 2ND FUNC

BIT

SHIFT SR ONCE

OUT — HD DIR

READ

HOME

NOTES:

SHIFT SR ,

INSERTO

All numerals are decimal

INTER 2
-80— SR

FLAG = ONE

TO SUBROUTINE

CLR FLAG

BEGINNING OF

FLAG = ZERO

INDICATES CALL

UNLOAD HEAD

4; — STAT

BEGINNING OF
A ROUTINE

ACTIONS

SR7 = ONE

‘

SR7 = ZERO

SR7 = ONE

SR7= ZERO
.|

SHIFT SR ONCE
FOR 3RD FUNC

SHIFT SR ONCE

FOR 3RD FUNC

FOR 3 RD FUNC

BIT

‘

OUT — DATA DIR

GOERDN

FOR 3RD FUNC

BIT

—

(SR)— INTERFACE
[SERIAL
STEP HEAD

SYNCHRONOUS

SR7 = ONE

SR7 = ZERO

SR7 = ONE

SR7 = ZERO

FILL BUFR

EMPTY BUF

0—CNTR

RDSECTOR

SR7 = ONE

SR7 = ZERO

SR7 = ONE

SR7 = ZERO

< CLRID [NOOP])

RD STAT

100, -~ CNTR

ERREG
-RD

TRANSFER]

A SUBROUTINE

BRANCH TO OR

DATA LINE

SOURCE

30, - CNTR

unless subscripted.

LEGEND

SELECT SR7 AS

DONE

HOME

WRT SECTOR

CP-1544

Figure 5-12

Initialize and Function Decode Flowchart

5-24

( FILL BUFR

‘

EMPTY BUF

’

END WRITE PULSE

(CNTR) + 1 — TEMPA
[INCR BYTE CNT]

OUT — DATA DIR

SET XREQ

INCREMENT SEC
BUFR ADDR
-8
- CNTR
SHIFT SR, INSERTO

[FOR BIT COUNT]

TWICE [CLEAR SR]

(CNTR) + 1~
OPENED SP

[INCREMENT
ISSUE SHIFT PULSE

12 BIT MODE

8 BIT MODE

(SR) — STAT

WAITRN

START WRITE

-12—- CNTR

’

( BYTEOUT

[FOR BIT COUNT]

(SR)
—~ ERREG

BYTE COUNT]

PULSE

OPEN TEMPA

[FOR BYTE CNT]I

(CNTR) +1—~CNTR
INCR BIT COUNT

-8~ CNTR

CLR FLAG:

ISSUE SHIFT PULSE

CNTR = OVFLW

BUF ADDR TO O

CNTR # OVFLW

INITIALIZE SEC

INCREMENT SEC

[FOR BIT COUNT]

12 BIT MODE

END WRITE PULSE

BUF ADDR FOR

8 BIT MODE

;

NEXT BIT

-12—-> CNTR
-128 - CNTR

12 BIT MODE

BUFR ADDR

INCR BIT COUNT

8 BIT MODE

(OPENED SP) - CNTR

DATA DIR = OUT

[GET BYTE COUNT]

:
-64—CNTR

[FOR BIT COUNT]

INCREMENT
SEC

(CNTR) + 1= CNTR

CNTR # OVFL

CNTR =OVFL

;

(OPENED SP) -~ CNTR
[GET BYTE COUNT]

[FOR BYTECNT]

NOTES:
All numerals are decimal
unless subscripted.

CNTR # OVFLW

SET XREQ

SELECT SECTOR
BUFFER AS
DATA SOURCE

RUN=T

)

LEGEND

DATA DIR =

4
FILL 1

CNTR # OVFLW

CNTR = OVFLW
DATA DIR = 0QUT

;
BYTEOUT )

CNTR =OVFLW

( OK DONE )

OPEN TEMPA

‘

DATADIR = IN

RUN=F

;

INDICATES CALL
TO SUBROUTINE

BEGINNING OF

A SUBROUTINE

BRANCH TO OR
BEGINNING OF
A ROUTINE

CLR XREQ
ACTIONS

( OK DONE

’

CP-1545

Figure 5-13

Empty and Fill Buffer Functions Flowchart

5-25

C READ

)

( RDSECTOR

)

‘

INITIALIZE SEC

0— STAT

’

OPEN TEMP D

(STAT) — SR

BUFFR ADDRESS

RDSTAT

[FOR SOFT UNIT
SELECT]

FINDTR

]

END AROUND

[LOCATE SECTOR]

SHIFT OF DRV

SEPCLK=F

SELECT UNIT 1

RDY BIT

SEPCLK=T

-3—+ TEMP B

[DATA MARK
TRY COUNTER]I

START WRITE
PULSE

SHIFT SR, INSERT
1

SEP DATA —»CRC

[TO SIGNIFY
LOOKING FOR

[UNIT 1 - SOFT
UNIT SEL BIT]

;

SET FLAG

0—CNTR

FLAG = ONE

FLAG = ZERO

SHIFT SR, INSERTO

[SET DEL DATA

[CLR DEL DATA

BIT]

DATA MARK]

R
FLAG =1

FLAG=0
2

SEC BUF ADDR # OVFLW

WAIT 96 us

SELECT UNITO

;

END AROUND

FINISH WRITE

SHIFT OF NEXT

PULSE

5 SR BITS

[TO PASS WRITE
TURN ON SPLASH

AREA]

SEC BUF ADDR = OVFLW

200,

— CNTR

[UNIT 0~ SOFT

C GET DAM )

UNIT SEL BIT]

SHIFT SR, INSERT 1

INCREMENT SEC

-16
- CNTR

-16
— CNTR

BUFFR ADDR

[BIT COUNT TO

[BIT COUNT FOR

PICKUP CRC]

CRC CHECK]

[SET CRC ERROR
BIT OF STAT]

CRC16=1

(SR) —~ OPENED SP

[RESTORE STAT]

[STORE SOFT UNIT
SEL BITI

CRC16=0

NOTES:

All numerals are decimal
unless subscripted.

LEGEND

A~
-

(CNTR)—~ OPENED SP

SEPCLK=F

SEPCLK=T

0— CRC

[BRING UP NEXT
CRC BITI

‘
200,

- CNTR

CHKRDY

[ERROR CODE FOR
DATA CRC ERROR]

SEP DATA — CRC

[PICK UP A CRC BIT]

INDICATES CALL

TO SUBROUTINE

)

(CNTR) + 1~ CNTR
[INCREMENT BIT

BEGINNING OF

(CNTR) +

END AROUND

CNTR # OVFLW

|
CNTR = OVFLW .,_m._.]

STAT BITS

IN SR

SHIFTOF5

BITS IN SR

CNTR # OVFLW

BEGINNING OF

ACTIONS

END AROUND
SHIFT OF LAST TWO

BRANCH TO OR

(STAT) — SR

COUNT]

1— CNTR

[INCR BIT COUNT]

A SUBROUTINE

A ROUTINE

( GOERDN. )

CNTR = OVFLW

(SR} -~ OPENED SP
[RESTORE STATI
SHIFT SR, INSERT 0

SHIFT SR, INSERTO

[CLR INIT DONE

[CLR CRC ERROR
BIT OF STATI]

(SR) —~ OPENED SP
[RESTORE STAT]

BIT]

( OK DONE )

( OK DONE

’
CP-1547

Figure 5-14

Read Sector and Read Status Functions Flowchart

5.26

The Read Status function (Figure 5-14) checks to see if the Drive Ready conditions are met by calling the CHKRDY
subroutine. If they are, the Drive Ready bit of the Status register is set, and the system status is checked. If not, the
Drive Ready bit is not set, and the system status is checked by a branch to the DONE condition.

The functions Write Sector and Write Deleted Data Sector (Figure 5-15) are similar except that the Deleted Data flag
is set in the Write Deleted Data Sector function. The diskette address and sector are found and WRITE GATE and

ERASE GATE signals are sent to the read/write electronics. The sector must be correctly formatted with proper
header, header CRC, 1024 bits of data, and data CRC. After the WRITE GATE and ERASE GATE signals are
negated and the next header is located, a branch is made back to the DONE condition to check status.

The FINDTR subroutine (Figure 5-16) locates the track as specified by the diskette address. Status and Error
Scratch Pad locations are cleared. The Drive Select bit is interrogated to determine which drive is being used. The
sector address is moved from the interface to the controller shift register by the subroutine GETWRD, and its parity
is checked. Then the eight-bit track address is moved from the interface to the target track register, and parity and
track legality are checked. The current track address of the drive selected is compared with the target track address

by the subroutine MAGCOM to determine if the head must step in or out to reach the target track. Head stepping is
accomplished by the subroutine STEPHD once the proper track is located and the head is loaded. If the track

address is greater than 44, the low write current level is selected. If the track address is less than 44, the high write
current level is selected. Subroutine

FINDSE locates the target sector.

The FINDHD and GETDAM subroutines (Figure 5-17) locate the header field and identify the data address mark.

The data address mark is a unique combination of data, clocks, and missing clocks for which the microcode searches.
Figure 5-18 contains the routines HDRCOM, BDSRT, and BADHDR, which are continuations of the FINDHD
subroutine. The routine HDRCOM is used in comparing a located header with a desired header. A sector address
compare and a track compare are made. The BDSRT and BADHDR routines count the number of retries for finding
a data mark or an ID address mark. If too many tries are made, the appropriate error codes are set.
Figure 5-19 contains the four subroutines, DELAY, FINDSE, WRTOS, and GETWRD. The DELAY subroutine

produces a delay period as set by the delay multiplier that resides in the shift register. The DELAY subroutine is

called throughout the microcode to establish waiting times, such as a head load wait of 20 ms. The FINDSE

subroutine uses the sector address to locate the correct sector by calling the subroutine FINDHD to find the correct
header. The subroutine WRTOS writes the specified number of zeros indicated in the shift register. The GETCMD
and GETWRD subroutines differ in that a Transfer Request must be set for

a GETWRD. The microcode calls the

subroutine WAITRN to wait for a RUN signal from the interface. Error and Done flags are cleared, and either 12 bits
or 8 bits are transferred. Parity is checked and the appropriate error code results if a parity error is detected.
Figure 5-20 shows the flowchart for the STEPHD, WAITRN, and MAGCOM subroutine. The STEPHD subroutine
moves the head in or out a certain number of tracks as indicated by the counter. When the head is positioned over
the desired track, the head is loaded, and a 20 ms delay occurs before the microcode exits from the subroutine. The
WAITRN subroutine waits for the RUN signal from the interface. If RUN does not come within 45.87 ms, the head

is unloaded, Transfer Request is cleared, and an exit is made out of the subroutine. If RUN does occur within
45.87 ms, Transfer Request is cleared and an exit is made out of the subroutine.
The MAGCOM subroutine compares track addresses and is called by the FINDTR subroutine.

Figure 5-21 shows flowcharts for the DIF and CHKRDY subroutines. The DIF subroutine determines the difference

between target track and desired track, so that the STEPHD routine can move to the right track. The CHKRDY
subroutine checks for a Drive Ready condition during an Initialize sequence or during a Read Status function.

5-27

C WRT SECTOR )

( WRTCRC
[CLK TRANSITION

FINDTRK

SR=0

[FLUX TRANSITION

[PRESET OBIT

10, - STAT

‘

-7 +-CNTR

TRANSITION

SET WRITE GATE

[SET WRT

COUNT]

PROTECT BIT]

CNTR = OVFLW

TOG FLAG

[END OF 2ND ZERO]

100, -~ CNTR |
[ERROR COD E

(STAT) — SR

\
WRT 0S
SHIFT SR, INSERT 0

[MOVE DEL DATA

GOERDN

[WRITE 22 BITS

INIT SEC BUFFER

OF 2 ZEROS]

ADDRESS

CURRENT IN

[TO USE FOR
DATA MARK]

NOTES:

PREAMBLE]

unless subscripted.

WAIT .8 us

PRESET CRC

LEGEND

INDICATES CALL
TO SUBROUTINE

FIVE 1'S— CRC

-22
-+ CNTR

0 — CRC

[SPECIFY 22

[JAM 1ST 6 BITS

CNTR # OVFLW

CNTR = OVFLW

SHIFT SR, INSERTO
[BRING NEXT
TRANSITION TO SR7]

BITS FOR WRT
0 S]

OF DATA MARK

(CNTR) + 1~ CNTR

TOG FLAG

ACTIONS

SR7=0

SR7 =1

‘

‘
[2ND HALF TRANSITION PATTERN
' FCR DELETED
DATA MARK]

LAST HALF OF

FOR NORMAL

TWO 1'S— CRC

SECBUF OUT =0

SEC BUF OUT =1

;

0— CRC

1—-CRC

(TEMPB) — SR
[GET 2ND HALF
TRANSITION

1's

[JAM LAST 2BITS

[JAM LAST 2 BITS

OF DEL

DATA MARK

INTO CRC]

INTO CRCI

Write Sector Function Flowchart

]

;

WRTOS

SR7=0

[DELAY 210 us]

SR7 =1

( SELFER

[SET UP
TRANSITION
COUNT]

[BRING UP

0— CRC

[STOP ERASING]

-25- CNTR [BIT

1—-CRC

[BRING UP

NEXT CRC BIT]

'WRTOS
[DELAY 101 us]

TOG FLAG

TRANSITION]

[DATA TRANSITION]

]

[LOOK

FIND HD

FOR HEADER
TO ASSURE

DISK IS SPINNING]

C OK DONE )

SEC BUF ADDR = OVFLW

( o )

CLR EGATE

\COUNT FOR WRTOS]

(CNTR) + 1> CNTR
[INCR BIT COUNT]

}

PREAMBLE]

CRC16 =1

CRC16=0

[WRITE A DATA

SEC BUF ADDR # OVFLW

’

-7+~ CNTR

CNTR # OVFLW

CNTR = OVFLW

}

376, —~ CNTR

TWO 0'S — CRC

DATA MARK

FOR WRTOS]

TOG FLAG

PATTERN]

OF NORMAL

[INCREMENT
TRANSITION
COUNT]

( GOERDN )

NEXT DATA BIT]

325, —~ CNTR

[BIT COUNT

[ERROR CODE FOR

INCR SEC BUF

[2ND HALF TRAN-

DATA MARK]

5-28

A SELFTEST ERROR]

ADDRESS

337, = CNTR

~52—+ CNTR

TIMES, INSERTING

60, ~ CNTR

WRTOS

[WRITE 22 ZEROS

SITION PATTERN

Figure 5-15

[END OF 25TH
ZERO]

A ROUTINE

[STOP WRITING]

TO SR7]

INTO CRC

BRANCH TO OR

CLR WGATE

SHIFT SR FOUR

TRANSITION

GENERATOR]

BEGINNING OF

CNTR # OVFLW

[BRING NEXT

TRANSITION]

MIDDLE OF

All numerals are decimal

)

[CLOCK
TRANSITION]

TOG FLAG [WRITE

FLUX

[START ERASE

OPEN TEMPB

;

SHIFT SR, INSERTO

[8 BITS
POSTAMBLE]

SR7=0

TOG FLAG

BIT TO SR7]

SET EGATE

[

SR7 =1

SR7=0

[GET DEL DATA BIT]

WRTOS

SR7 =1

377, —» CNTR

(CNTR) + 1—> CNTR
[INCREMENT

[TRANSITION COUNT]

TRANSITION OF LAST

[WRITE CLOCK

CNTR = OVFLW

CNTR # OVFLW

' TOG FLAG [CLOCK

[FOR SELFTEST]

TRANSITION]

COUNT TO 22]

357, - SR

CNTR # OVFLW

TOG FLAG

PATTERN FOR 1ST
HALF OF BOTH

-22 -+ CNTR

WRTENAB=T

[BIT COUNT

| FOR WRT 0S]

. CRCBIT]

352, — SR

DATA MARKS]

WRTENAB=F

CNTR = OVELW

{WRITE A FLUX

TRANSITION]

WAIT 2.4 us

[WRITE FLOP]

TOG FLAG

(END OF 48TH
ZERO BIT)

MARK TO TEMP BI

CLR FLAG

-8 —>CNTR

[BIT COUNT]

SR=1

TOG FLAG

(CNTR) — OPENED SP
[2ND HALF OF DATA

-16 ~CNTR

(CNTR) + 1~ CNTR

OF FIRST 0BIT]

BITI

]

WAIT 1.0 us

TOG FLAG

(CNTR) — STAT
[SAVE DEL DATA

CP-1546

FINDTR

‘

SUBROUTINE

RETURN ADDR —

GETWRD

MAGCOM

RTN

[-SEC ADDR FROM

[CHECK IF LEGAL
TRACK]

HOST
— SR]

0— ERREG

TARTRK > 77

TARTRK = 77

TARTRK < 77

OF OTHER

SEC

7 BITS OF

ADDR IN SR

TARGET < CURRENT

‘

40, ~ CNTR

TARGET > CURRENT

TARGET < CURRENT

SR7 =0

)

(TARTRK) - TEMPF
[PASS TO MAGCOM]

SELECT HD

‘DLY 20
.[LD HD AND WAIT

20 ms]
-44 > TEMPG

(TEMP D) — SR
[GET UNIT SEL]
(SR) = TARSEC

BIT

PRIATE CURRENT

DIRECTION IN

ERROR CODE]

SR7 =1

GET HD LOADED

TRACK REG]

TARGET > CURRENT

(TEMPD) —SR

SR7=0

(TEMPE ) > SR

(CNTR) —~ OPENED SP
[TARGET TO APPRO-

SUBROUTINE

TARGET = CURRENT

( NOSTPS

END AROUND SHIFT
|

(

[NECESSARY
STEPS — SR]

BOOTSTRAP

—

(TEMP D) — SR
[GET SOFT UNIT
SEL BIT]

DIF

[IS TARGET SAME
AC CURRENT]

—

SHIFT SR, INSERT 1

[SET MSB OF
SECTOR ADDR]

MAGCOM

NOSTPS 3

[PASS #44 TO
MAGCOM]

( GOERDN )

OPEN CURTKO

UNLOAD HEAD

SELECT LOW

OPEN CURTK 1

FLAG=0

FLAG =1

FLAG=0

SELECT UNIT O

SELECT UNIT 1

FLAG =1

[-TRACK ADDR

SELECT DISK

FROM HOST
— SR]

INTERFACE

STEP HD

0— CNTR

[UNIT 0~ SOFT
UNIT SEL]

[UNIT 1 - SOFT
UNIT SEL]

(SR) > TEMP F
[PASS TAR TRACK

MAGCOM

[COMPARE

SR7 =1

(SR) - TARTRK
SR7=0

[GO TO TARGET
TRACK]

SR7=0
200 , > CNTR

WRT CURRENT

GETWRD

TARGET TO 43]

SR7 =1

)

—

OPEN CURTKO

OPEN CURTK 1

DONE

HOME

50, -~ CNTR

(TEMP D) — SR

TO SUBR MAGCOM]

[GET SOFT

[ERROR CODE

UNIT SEL]

FOR HOME

BEFORE DONE]

" (CNTR) —~ OPENED SP

(OPENED SP) — SR

-77 > TEMP G

[RESTORE SOFT

[PASS #77 TO

UNITBITTO

SUBR MAGCOM]

TEMPD]

TRACK TO DIF SUBR]

(TARTRK) -~ CNTR

[PASS CURRENT
TRACK TO MAGCOM]

[PASS TO DIF]

[CLR SOFT HD
LOADED BIT
BECAUSE A NEW

All numerals are decimal
unless subscripted.

LEGEND
SELECT HIGH

INDICATES CALL
TO SUBROUTINE

GOERDN )

BEGINNING OF

FINDSE

(TARTRK) — CNTR

0 — TEMPE

TARGET <44

WRT CURRENT

[PASS CURRENT
(OPENED SP) » TEMPG

N TARGET=44 1
TARGET > 44

NOTES:

[LOCATE THE

OPEN CURTK 0

(TARTRK) — TEMPF
[PASS TARGET

A SUBROUTINE

TARGET SECTOR]
BRANCH TO OR
BEGINNING OF

TO MAGCOM]

UNIT IS SELECTEDI
3

A ROUTINE
SELECT HD

OPEN RTN

DIRECTION OUT
SR7=0

ACTIONS

SR7 =1

¢
OPEN CURTK 1

RETURN TO

ALLING ROUTINE

CP-1548

Figure 5-16

FINDTR Subroutine Flowchart

5-29

DAM)

WAIT 40 us FOR
FOURTH CELL

SEP DATA=0

SEP DATA =1

TIMERR )

MISCLK =1

MISCLK =0

}

SEP CLK

;

40 us

_ 3 |

SEP DATA =0

MISCLK = F

MISCLK =T

WAIT 40 us

MISCLK =0

[JAM 6TH
DAM BIT]

MISCLK
= 1

l
SEP DATA =1

0— CRC

1—CRC

WAIT 40 us

[JAM 7TH
IDAM BIT]

FOR SIXTH CELL

WAIT 40 us FOR

LAST CELL]

—

SEPCLK

40 us

SEP CLK

—

;

SEP DATA =1

[ERROR CODE

[

FOR NO SEP

CLOCKS]

MISCLK = 1

SEP DATA =0

SEP DATA =1

0->CRC

[JAM LAST

GOERDN

MISCLK =0

FLAG=0

FLAG =1

MISCLK =0

SEP DATA =0

SEP DATA =1

110, -~ CNTR

SEP DATA =0

MISCII.;1

40 us

SEPCLK

FOR FIFTH CELL

1—CRC

0— CRC
[JAM 7TH DEL

[JAM 7TH NORMAL
DAM BIT]

IDAM BIT]

DAM BIT]

MISCLK =1

MISCLK =0

( HRDCOM

;

'WAIT 40 us FOR

’

WAIT 40 us FOR
SEVENTH CELL

SEVENTH CELL

1-CRC

[JAM 6TH

IDAM BIT]

SEP CLK

40 us

SEP CLK

WAIT 40 us FOR
SIXTH CELL

CLR FLAG

1—~CRC

NOTES:

[JAM LAST

[INDICATES

TIMERR

NORMAL DAM BIT]

All numerals are decimal

DEL DATA]

uniess subscripted.
SEP CLK

i
0—CRC

LEGEND

‘

BADSRT

)

NE
M

40 us

[JAM LAST
DEL DAM BIT]
INDICATES CALL

TO SUBROUTINE
—

BEGINNING OF
A SUBROUTINE

BRANCH TO OR

SEP DATA=0

—

SEP DATA =0

SEP DATA =1

]

BEGINNING OF
A ROUTINE

MISCLK =1

ACTIONS

MISCLK =0

(o)

( BADSRT

’

CP-1550

Figure 5-17 FINDHD and GETDAM Subroutines Flowchart (Sheet 1 of 2)

5-30

( ‘GETDAM )

(FIND HD SUBR)
RETURN ADDR —

RTNB

WAIT 40 s

INIT BUFF ADDR

FOR SEP CLK

REG FOR 4096

[INNER COUNT

[OUTER COUNTER

SEP DATA =

COUNT]

SEPC

40 us

‘

[INCR PREAMBLE

FAIL COUNT]

SEP DATA =0

(CNTR) — OPENED SP

BUF ADDR = OVFLW

BUF ADDR # OVFLW

nea

INCR

120, —» CNTR

OF 4096
[PREAMBLE

NON EXISTENT
PREAMBLE]

REG FOR COUNT

BUF ADDR # OVFLW

NOTES:

(CNTR) + 1~ CNTR

(CNTR) — OPENED SP
[RESTORE OBIT

COUNT]

CNTR = OVELW

067, — SR

[CLR SR7 FOR

COMPARISONS]

T ADDR

MISCLK = F

MISCLK = T

TIMERR

FOR THIRD CELL

SRESET CRC

j
BUF ADDR = OVFLW

70 ALL 1'S

SEP CLK

1 —-CRC TWICE
IDAM OR DAM]

{

INDICATES CALL

CLR FLAG

INNING

BEGINNING O

[SIGNIFY, IDAM]

SEP DATA =1

‘

TO SUBROUTINE

]

SEP DATA =0

GOERDN

40 us

]

MISCLK = F

MISCLK _=T

0— SR

A SUBROUTINE

CELL 4

)

BRANCH TO OR

BEGINNING OF
A ROUTINE

)

ACTIONS

BADSRT

WAIT 40 us

LEGEND

CNTR = OVRLW

MISCLK = F

[JAM 3 MORE

All numerals are decimal

unless subscripted.

AM BITS]

1308 - CNTR
IDAM START
FAILURE]

GOERDN

[0 BIT COUNT]

SEP DATA =1

[NOSTART COUNT]

FAILURE COUNT]

-24 > CNTR

SEP DATA =0

T GRC THREE

‘

[ERROR CODE

‘

TIMES

‘

INIT BUFF ADDR

MISCLK = T

40 us

“

‘

ADDR REG

SEP CLK

WAIT
40us
FOR SEPCLK

( TIMERR

INCR BUFFR

[0 BIT COUNT]

[OUTER COUNT]

FOR SECOND CELL

SEP DATA =1

(OPENED SP) | - CNTR

-3— CNTR

WAIT 40 MS

SEP DATA =1

—o

FOR BADSTARTS]

[NOSTART

40lus

OPEN TEMPB

TRYAGN

SEP CLK

FOR BAD STARTSI

COUNT

-0~ TEMPA

G
CP-1549

Figure 5-17

FINDHD and GETDAM Subroutines
Flowchart (Sheet 2 of 2)

5-31

( HDRCOM )
(TARTRK) — SR
[GET 1'S COMPLE-

-8 - CNTR

0 —-CRC REG

SHIFT SR, INSERT 0O

[FOR OBYTE

BIT COUNT]

MENT OF TRACK
ADDRESS]

SEP DATA -~ CRC
REG

SEPCLK=F

0~ FLAG

]

;

TRACK COMPARE]

FOR SECTOR

COMPARE]

CNTR = OVFLW

[FOR 0BYTE AND
2BYTE CRC BIT

SHIFT SR,
INSERT O

SHIFT SR,
INSERT
1

[GET TRACK
COMPARE RESULT
TO SR7]

-24 -~ CNTR

SEP DATA — CRC REG

COUNT]

CNTR = OVFLW
SR7 =0

[

(SR) -~ ERREG
[SET ERREG BIT O
TRACK SEEK
ERROR IF THIS

IS LEGAL HDR]

SEPCLK =F

SEPCLK=T

TO INDICATE A

CNTR # OVFLW

CNTR = OVFLW

;

[ERROR CODE

150, -~ CNTR

FOR TOO MANY

[ERROR CODE FOR

TRIES FOR A

POSITIONING

DATA MARK]

CNTR # OVFLW

SEPCLK=T

SEPCLK=F

;

> CNTR
-16

( GOERDN )

[TO INDICATE
SECTOR

MISMATCH]

CNTR # OVFLW

unless subscripted.

( TRYAGN )

LEGEND

CRC16=0

CRC16=1

| (CNTR)+1—~CNTR

CNTR = OVFLW

)

160, CNTR

[ERROR CODE
FOR TOO MANY

1— FLAG

All numerals are decimal

[BIT COUNT FOR

CRC CHECK]

SEP DATA =SR7

( TRYAGN )
(TEMP B) — CNTR
[GET OUTER

NOTES:

CNTR # OVFLW

GETDAM )

-8 — CNTR

[INCREMENT BIT
COUNTER]

CNTR # OVFLW

(CNTR) +1—CNTR

[FOR SECTOR
BIT COUNT]

CNTR = OVFLW

170,— CNTR

(CNTR) + 1 — CNTR

(CNTR) +1—CNTR

CNTR = OVFLW

BADSTART

ROUTINE

[UPDATE CRC]

CNTR # OVFLW.

COUNT]

ADDRESS]

(CNTR) — OPENED
SP

ERROR]

CALLING

MENT OF SECTOR

(CNTR) —~ OPENED
SP

RETURN TO

REG

(TAR SEC) — SR
[ONES COMPLE-

SEP DATA — CRC

OPEN RTNB

SEPDATA —CRC

(CNTR)+1—CNTR

SR7 =1

(CNTR) +1—CNTR
A

[GET INNER

BADSTART COUNT]

(CNTR)+1—CNTR

SHIFT SR 7 TIMES
INSERT ZERO

CNTR # OVFLW

SEP DATA # SR7

SEP DATA = SR7

(TEMPA) — CNTR

(ERREG — SR
[GET RESULT OF

(CNTR)+ 1—~CNTR

[PREPARATION

SEPCLK=F

(TEMPB) — CNTR
[GET DAM
BADSTART COUNT]

CNTR = OVFLW

CNTR # OVFLW

[FOR BIT COUNTI
SEPCLK=T

[

-8 -~ CNTR

FLAG=0

FLAG =1

SEPCLK=T

( BADHDR )

BDSRT

140, — ERREG

[ERROR CODE FOR

INDICATES CALL

TRIES FOR

TO SUBROUTINE

AN IDAM]

BEGINNING OF

A SUBROUTINE

( GOERDN )

BRANCH TO OR

BEGINNING OF
A ROUTINE

HEADER CRC

ERROR]

ACTIONS

( BAD HDR )
CP-1609

Figure 5-18

HDRCOM, BDSRT, BADHDR Routines Flowchart

5-32

FINDSE

DELAY

SUBROUTINE

(SR)— RTNB

[SAVE RETURN
ADDRESS]

WRTOS

GETCMD

GETWRD

SUBROUTINE

(CNTR) - RTNA

(SR) = RTN
[SAVE RETURN

SET XREQ

ADDRESS)

WORD FROM

[STORE RETURN
ADDRY]

SUBROUTINE

[REQUEST A

DATAIN =0

INTERFACE]

-52— CNTR

{CNTR) — SR

(CNTR) = SR
[BIT COUNT WILL

[FOR SECTOR

[DELAY MULTI-

TRY COUNT]

(CNTR) — RTNA
[SAVE RETURN
ADDRESS]

RESIDE IN SHIFT

PLIER WILL

[

REG]

RESIDE IN

[FOR PARITY]

ONE

[FOR PATH

[STORE COUNT]

TOG FLAG

SHIFTSR, INSERT

OPEN TEMPA

[COMPLEMENT OF

WAITRN

THROUGH SP]

STALL 98 us

;

SHIFT REG]

(CNTR) - TEMPG

;

DATAIN =1

CNTR = OVFLW

DATA TO SR]

[WAIT FOR RE-

CNTR # OVFLW

‘

SPONSE FROM

FIND HD

INTERFACE]

SHIFTSR, INSERT O

[COMPLEMENT OF
DATA TO SRI

STALL 2.6 us

(SR) -~ CNTR

0— FLAG

[IN PREPARATION
FOR PARITY CHECK]
TOG FLAG

{CNTR) + 1= CNTR
[INCREMENT DE-

LAY MULTIPLIER]

FLAG =1

FLAG=0

[FOR A CLOCK FLUX

‘

WRITE GATE IS SET]

CNTR # OVFLW,

CNTR = OVFLW

‘

CLR DONE

FOR WRITE TURN

ON TIME]

OPEN RTNA

(CNTR) +

[INCREMENT BIT

ROUTINE

COUNT]

CNTR # OVFLW

All numerals are decimal

unless subscripted.

;

CNTR = OVFLW

‘

RETURN TO

ROUTINE

OPEN RTNA

(STAT) — SR

DATA BIT

END AROUND

8 BIT MODE

ROUTINE

IN THE SR

COUNT

(CNTR) » SR

SHIFT SR, INSERT 0

-12— CNTR

[CLR INIT DONE]

[FOR BIT COUNT]

[ERROR CODE

LEGEND

FOR NONEXISTENT SECTOR

INDICATES CALL

HEADER]

TO SUBROUTINE

]
FLAG =0

INTERFACE

BIT
[INCREMENT
:

12 BIT MODE

CALLING

I
FLAG =1

RETURN TO

70, -~ CNTR

[SHIFT UP NEXT

-8 - CNTR

1> CNTR

CALLING

NOTES:

CLR SHIFT

(SR) >~ CNTR

[ASSUME 8 BIT
MODE]

(CNTR) + 1-CNTR

RETURN TO

CLR ERR

STALL 323.2 us
[WAIT 10.1 BYTES

(TEMPG) - CNTR
[RECALL TRY

COUNT]

SET SHIFT

TRANSITION IF

BEGINNING OF

A SUBROUTINE

CNTR # OVFLW

i
:

GO ERDN

1
FT
SR, INSERT
SHI
[SET PARITY
ERROR BIT]

CNTR = OVFLW

4
OPEN RTN

END AROUND

SHIFT OF CRC BIT
OF STAT IN SR

BRANCH TO OR

BEGINNING OF

RETURN TO

A ROUTINE

CALLING
ROUTINE

(SR) = STAT

[RESTORE STAT]

ACTIONS

210, —~ CNTR

[ERROR CODE FOR

PARITY ERRORI

‘

GOERDN

>
CP-1610

Figure 5-19

DELAY, FINDSE, WRTOS,

GETWRD Subroutines Flowchart

5-33

WAITRN
(SUBROUTINE

STEPHD
SUBROUTINE

ADDR]

> CNTR
(SR)
[STEP COUNT

CNTR # OVFLW

TO CNTR]

]
CNTR = OVFLW

DLY 20

SUBROUTINE

(CNTR)+1—CNTR
[INCREMENT
‘

OPEN TEMPC

- CNTR

[INCREMENT

(CNTR)
-~‘ TEMPA
[KEEP STEP

[TO PRESET
LOOP COUNT]

(CNTR) ~ RTNA
‘

RETURN TO
CALLING

COUNT]

T
FOR RUN

DELAY

‘

PLIER TO

[3 MS]

[20 MS FOR HD
LOAD SETTLE

TIME]

-30— CNTR
[PASS MULTI-

— =

[3 MS]

OPEN RTNA

NOTES:

INDICATES CALL

BEGINNING OF

(TEMPG) — SR

[RESTORE F]

[GET G]

CNTR = OVFLW

CNTR # OVFLW

;

SR7 =1

SR7 =1
r

SR7 =0

‘

(RTNA) + 2~ RTNA
>

(RTNA) + 2> RTNA

)-I1

SHIFT SR,

‘

INSERT 0

UNLOAD HEAD

‘

RETURN TO
CALLING
ROUTINE

(SR) - OPENED SP

[RESTORE G]

TO SUBROUTINE

A SUBROUTINE

(TEMPG) — SR

LOAD BIT]

gfib'}m

LEGEND

(SR) » OPENED SP

[CLR SOFT HD

RETURN TO

unless subscripted.

[
0~ TEMPE

All numerals are decimal

INSERT ONE

(SR) -~ OPENED SP

SR7 =0

(CNTR) +1— CNTR

STEP PULSE]
DELAY]

DELAY

CLR STEPHD
[GIVE SECOND

SHIFT SR,

[GET GI

(OPENED SP) —~ CNTR
[GET LOOP COUNT]

DELAY]

l
SET STEPHD
PLIERTO

45.87 us

RUN=T

,
fsz(s);mcggg

INSERT 0

‘

[RESTORE F]

LOAD BIT]

[GIVE STEP PULSE]

SR7 = 1

SHIFT SR,

‘

CLR STEPHD

SR7=0

ROUTINE

%3281_;;?7”:%
SET STEPHD

(TEMPF) — SR
[GET F]

OPEN RTNB

(CNTR)
— OPEN SP
[RESTORE LOOP

LOAD HEAD

TO DELAY]

— OPENED SP
(CNTR
[STORE BIT COUNT]

0— CNTR

COUNT IN TEMPA]

[PASS MULTIPLIER

CLR XREQ

(CNTR) +2— CNTR

RETURN ADDRESS
TWOI
BY

;

CNTR
-8~
[FOR BIT COUNT]

I
RUN = F

1O o

STEP COUNT]

-30- CNTR

RUN=T

RUN = F

RUN =T

LOOP COUNTI

HOME =T

OPEN TEMPA

ADDRESS]

(RTNA)

HOME = F

‘

]

}

[SAVE RETURN

[GET STEP COUNT]

[SAVE RETURN

MAGCOM
GROUTINE

(CNTR) —~ RTNB

(TEMPA) — CNTR

(CNTR) - RTNA

(TEMPA) + 1~ CNTR

\_/

[INCREMENT BIT
COUNT]

BRANCH TO OR

BEGINNING OF

A ROUTINE

ACTIONS

CNTR # OVFLW

CNTR = OVFLW

CP-1607

Figure 5-20

STEPHD, WAITRN, MAGCOM Subroutines Flowchart

5-34

CHKRDY
\|

SUBROUTINE

(CNTR) = RTN

OPEN TEMPA

[SAVE RETURN
ADDRESS]

[PATH THROUGH
SP]

INDEX =T

INDEX =F

CNTR = OVFLW

(CNTR) +

[FOR PASS COUNT]

;

-2—CNTR

(TEMPA) +

1= CNTR

CNTR # OVFLW

{

OPEN RTNA

OPEN TEMPA

(SR) - OPEN SP

- SP]
[B

[A>B]

CNTR # OVFLW

CNTR = OVFLW

CNTR # OVFLW

(TEMPC) + 1 = CNTR
[INCREMENT % MS

(CNTR) — OPEN SP

(CNTR) - SR
[A ~SR]

RETURN TO
CALLING

1~ CNTR

[INCREMENT PASS
COUNT]

(SAVE PASS COUNT]

OUNT]

ROUTINE
FLAG =0

0— FLAG [CLOSE

,(OPEN SP) - CNTR

INDEX

B— CNTR

CNTR = OVFLW

(RTNA) +2 — RTNA

(B > Al

[INCREMENT B]

}

COUNT]

(STAT) — SR

RETURN TO

(SR) — OPEN SP

[A - SP]

[FOR 10 MS COUNT]

(CNTR) -+ TEMPB

CNTR = OVFLW

(CNTR) —» SR
[B -» SR]

alnlm

[A — CNTR]

[OPEN INDEX
WINDOW]

(STAT) —> SR
[G ET STAT]

BEGINNING OF
A SUBROUTINE

STAT IN SR
-3— CNTR

[FOR 10 MS COUNT]
(CNTR) +

1= CNTR

[INCREMENT A]

(CNTR) - OPEN SP
[SAVE % MS COUNT]

BRANCH TO OR
BEGINNING OF
A ROUTINE

END AROUND SHIFT
OF NEXT 3BITS OF

OPEN TEMPC

TO SUBROUTINE

)

CLR FLAG

SET FLAG

(OPEN SP) » CNTR
INDICATES CALL

FLAG =1

;

-40 - CNTR

[FOR % MS COUNT]

unless subscripted.

LEGEND

[SET DRV RDY BIT
IN STAT]

;

}
FLAG =0

All numerals are decimal

SHIFT SR,INSERT 1,

[SAVE 10 MS COUNT]I

ROUTINE

NOTES:

-15 = CNTR

CNTR # OVFLW

CALLING

(RTN) + 2— RTN

(TEMPB) + 1 - CNTR
[INCREMENT 10 MS

CNTR #= OVFLW

(CNTR) + 1~ CNTR

CNTR = OVFLW

CNTR # OVFLW

CLR INDEX SYNC

FLAG =1

WINDOW]

-250 —+ CNTR

SHIFT SR, INSERT 0
[CLR DRV RDY BIT
OF STATI

FLAG = 1

FLAG =0

(SR) - OPEN SP

'WRTEN=T

WRTEN = F

SHIFT SR, INSERT 0

1
SHIFT SR, INSERT

[RESTORE STAT]

ACTIONS

RETURN TO

[SET STAT BIT 3]

[CLR STAT BIT 3]

CALLING

ROUTINE

;
SET FLAG

CP-1608

Figure 5-21

DIF and CHKRDY Subroutine Flowchart

5-35

5.2.6

Read/Write Electronics

A detailed block diagram of the read/write electronics is shown in Figure 5-22. The read/write electronics can be
separated into four functions:
1.

Diskette position

Head read/write circuitry

Head load control and solenoid drivers

Stepper motor control and motor drivers

5.2.6.1

Diskette Position — Track O and index hole detection are accomplished by an LED-phototransistor pair.

There are separate circuits for drive 0 and drive 1 for a total of four sensing circuits. A schematic diagram of the
circuitry appears on page D4 of the RX8/RX11 Print Sets.

The six sensor indicator lines are input to a 74157 data selector shown on page D6, which outputs track 0 and index
hole sensing information to the uCPU controller. The 74157 is data-selected by the SEL 1 H signal from the uCPU
controller, indicating which drive is being used.

5.2.6.2

Head Read/Write Circuitry — The head read/write circuitry is shown on page D3 and is composed of a write

section and a read section.

Head writing is controlled by six signals from the uCPU controller as shown in Figure 5-22. Each of these signals is
further explained in Paragraph 5.1.4. During a write operation, D6 WT GATE H initiates a Write command, and D6
ERASE H activates the tunnel erase drivers. The data stream D6 WT DATA H is amplified by the head write current

amplifiers and directed to the proper drive by D6 SEL DKO H and D6 SEL DK
1 H signals. Head writing is inhibited
by D6 SEL WT PROT L or D6 DC LO L

signals. The signal ABOVE TK 43 H controls proper write current to the

heads.
Head reading is accomplished by the circuitry shown on page D3. The diode and resistor circuitry on the R/W BUS +

and R/W BUS - protect the 733 preamplifier during a write operation. The filter following the preamplifier
eliminates unwanted head noise. The next 733 amplifier stage drives the peak detection circuitry, composed of a

differentiator and crossover detector (1414). The output of the 1414 is fed to 74123s (monostables), which are used
as pulse shapers. RAW DATA L, which represents digitized data from the diskette, is sent to the uCPU controller.
5.2.6.3

Head Load Control and Solenoid Drivers — Head load control and solenoid driver circuitry is shown on

page D6. A D6 LOAD HEAD H signal from the uCPU controller causes either head load solenoid to be activated,

depending on whether signal D6 SEL DK1 H is high or low. D5 INIT L, an initialize signal from the stepper motor
control, will reset the drive and cause the head to unload.
5.2.6.4

Stepper Motor Control and Motor Drivers — Stepper motor control and motor driver circuitry is shown on

page D5. A separate and identical control section and motor driver section exists for each drive. Signals D6 SEL DK
1
H and D6 SEL DKO H determine which drivers to activate.

D6 OUT H determines the direction of movement of the head in response to the pulse D6 STEP L from the uCPU

controller. If D6 OUT H is asserted, the head moves outward toward track 0; if it is negated the head moves inward

toward track 77. The two 7473s and the 7450 in the two control sections are connected as up/down counters to
control the four motor driver transistors. In moving OUT, the counter counts up to turn on the driver transistors to
move the head outward. In moving IN, the counter counts down to turn on the driver transistors to move the head

inward. Each track position requires two phases of the counter. Therefore, two step pulses are required for each
track moved.

5-36

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14N

IXd

5-37

oxa

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xXIHmA3NaIu_

WOVYL

S3AINA

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HX1a3NsI=

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269L-dd

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HOLOW

5.2.7

Mechanical Drive

The mechanical drive consists of four major parts:
1.

Drive mechanism

Spindle mechanism
Positioning mechanism

Head load mechanism

The complete mechanical structure of the drive is shown in Figure 5-23, and each section is described in the
following paragraphs.

DISK

CENTERING CONE

HEAD LOAD
ACTUATOR

READ/WRITE
HEAD

HEAD
CARRIAGE
HEL IX

STEPPER
MOTOR

COOLING
FAN

DIS K
DRIVE
MOTOR

CP-1138

Figure 5-23

Disk Drive Mechanical System

5-38

5.2.7.1 Drive Mechanism — The drive system provides rotational diskette movement using a single-phase motor
selected to match primary power of the controller system (Figure 5-24). The diskette drive attains ready status

within 2 seconds of primary power application.

A cooling fan is mounted on one end of the drive motor shaft. Rotation of the diskette is provided by a belt and
pulley connected to the other end of the motor shaft. The drive pulley and belt are selected for either 50 or 60 Hz
power to achieve a diskette rotational speed of 360 rpm. See Paragraph 2.2.3.2 for complete input power
modification requirements.

("/'

S+

|‘
IMPELLER

SPINDLE DRIVE

PULLEY

—

~—

MOTOR

BELT

DRIVE MOTOR
APULLEY

CP-15%95

Figure 5-24

Drive Mechanism

5.2.7.2 Spindle Mechanism— The spindle mechanism consists of a centering cone and a load plate. In the unload
position, the load plate is pivoted upward, creating an aperture through which the floppy diskette is inserted. In this
position, the centering cone disengages the diskette from the drive mechanism.

To load a diskette, the operator inserts the floppy diskette and presses down on the load handle, which latches the
load plate in the operating mode. The centering cone is mechanically linked to the load plate and is activated at the
same time. (Figure 5-25).

The centering cone is an open splined nylon device that performs two functions:
1.

Engages the diskette media and drive mechanism.

Positions the diskette media in the correct track alignment.

As the load plate is pivoted to the load position, the centering cone enters the floppy diskette center. At
approximately 80 mils from the fully down position, a centering cone expander is automatically activated. This
device then expands the centering cone, which grips the inner diameter of the diskette media in the correct track
alignment.

The track O position serves as the diskette drive reference track. This position is sensed by a phototransducer, which
generates track O status. This status is sent to the controller for initial track positioning. The controller generates
step pulses to position the carriage from the current track to a new track.

5.2.7.3 Positioning Mechanism — The positioning mechanism comprises a carriage assembly and a bidirectional
stepper motor (Figure 5-26). The stepper motor rotational movements are converted to linear motion by the rotor
helix drive.

The read/write head mount rides in the grooved helix shaft and is held in horizontal alignment by the way. When the

stepper motor is pulsed, the helix drive rotates clockwise or counterclockwise, moving the mount in or out.

5-39

EXPANDER SPRING
CENTERING CONE

CENTERING CONE
EXPANDER
CENTERING
CONE

SPINDLE DRIVE

HUB

SPINDLE DRIVE

PULLEY

CP-1675

Figure 5-25

Centering Cone and Drive Hub

TRACK OO

FIXED WAY

/ TRANSDUCER

READ/WRITE
HEAD

CAKRRAGE

|
__— ASSEMBLY
~—

[T———_ HEAD LOAD
ARM

!
|
/
/
/

\ STEPPER
MOTOR

HELIX DRIVE

FRONT

BEARING

MOUNT

CP-1576

Figure 5-26

Positioning Mechanism

5-40

The stepper motor includes four pairs of quadrature windings. In detent, current flows in one winding and maintains
the rotor in electro-magnetic detent. For positioning, one or more step pulses are sequentially applied to quadrature
windings, causing an imbalance in the electro-magnetic field. Consequently, the stepper motor rotor revolves through
detent positions until the step pulses are halted. The rotor then locks in that position. The sequence in which the

stepper motor quadrature windings are pulsed dictates rotational direction and, subsequently, higher or lower track
addressing from a relative position.

527.4 Head Load Mechanism — The head load mechanism is basically a relay driver and a solenoid. When
activated by signal LD HD from the controller, the spring-loaded head load pad is released and rests in parallel
alignment with the floppy diskette surface. Part of the casting provides the lower alignment dimensional surface,

while the head load solenoid bar provides the upper alignment surface.

In the load position, the read/write head tang rides between these two alignment surfaces and keeps the read /write
head in contact with the diskette surface. The load pad is located behind the read/write head and holds the floppy
diskette flat against the lower alignment block.

To minimize diskette surface and head wear, the head is automatically disabled by the controller if no new

command has been issued within 48 ms. Head settling time is 20 ms.

5-41

ECHTHO

TENEE

6.1

RECOMMENDED TOOLS AND TEST EQUIPMENT

Table 6-1 lists the recommended tools and test equipment for maintenance of the RX8/RX11 Floppy Disk System.
Table 6-1

Recommended Tools and Test Equipment

Manufacturer and Model/Part No.

Equipment
- Multimeter

Triplett 310 or Simpson 360

Oscilloscope

Tektronix 453

Oscilloscope Probes,

Tektronix P6010

Field Service Tool Kit

DEC 29-18303

Head Cleaning Kit

DEC 22-00007

Voltage (X10, two required)

(includes TEX pads and wand)

DEC 29-19557

DEC 29-19558

RX8/RX11 Service Kit
DEC-O-LOG

6.2

DEC ECO log and computer on-line synopsis

CUSTOMER CARE

Although there is no scheduled preventive maintenance, there are two tasks that should be performed on an

as-needed basis.
1.

R
with a damp cloth, using either a solution of nonabrasive cleaner or mild
Clean the exterior of the RX01
soap.

Examine the air filter (Figure 6-1) and clean the element as necessary. Use water and a mild soap, drying

thoroughly before reinstalling.

6-1

JUMPER P1

SHIPPING

FILTER

POWER PLUGS

FILTER

RESTRAINT (RED)
7436-12

Figure 6-1

6.3

RXO01, Rear View

REMOVAL AND REPLACEMENT

The following steps define the procedures for replacing the subassemblies of the RX8/RX11 Floppy Disk System.
6.3.1

Module Replacement

Floppy Disk Controller,
1.

M7726 (Figure 6-6)

Remove power from the RX01.
Unscrew the two captive screws on the right side of the module and raise the module to the servicing
position.

Remove the plugs in connectors J1, J2, and J4.

Lower the module and remove the three screws holding the module onto the hinge.
Remove the module and remove the two captive screws.

To install a module, insert the two captive screws removed from the original module and perform the
reverse of the steps 1-—35.

6-2

)
TR

Read/Write Control, M 7727 (Figure 6-6)
1.

Remove power from the RXO1.

Raise the floppy disk control module to the servicing position.

Remove the plugs from connectors on the module, ensuring that they do not drop into the drive.

Remove the six screws holding the module to the frame and remove the module.

To install a M7727, replace the screws and plugs removed in steps 3 and 4, ensuring that they are

reinstalled into the correct connector (Table 6-2).

Table 6-2

M7727 Connectors

Connector

Description

J1
J2
DKO(P3)
DKO0(P4)
DKO(P5)
DKO(P6)
DKO(P7)
DKO(P8)
DK1(P3)

Disk drive interface cable
Power from H771 power supply
Head cable
Stepper motor
Head load solenoid
Index signal
Track O signal
Write protectTM
Head cable

DK1(P4)

DK 1(P5)
DK 1(P6)
DK1(P7)
DK 1(P8)

Stepper motor

Head load solenoid
Index signal
Track O signal
Write protectTM

*Not used.

H771 Power Supply Regulator, 70-10718 (Figure 6-6)

With the power off, remove the plug from the regulator.

Unscrew the leads going to the capacitors, checking with the H771 prints to ensure that the wiring
matches the prints.

Remove the plugs from the M7726 and M7727.

Remove the six screws holding the regulator to the power supply chassis.

Replace the regulator by performing the reverse of steps 1-—4.

6-3

[ 3

6.3.2

Drive Placement (Figure 6-6)
1.

With the powér removed, remove the power plug in the rear of the drive (Figure 6-1).

Remove the plugs for this drive (Table 6-2).
Loosen the six screws holding the drive to the chassis.

While holding the drive, remove the screws from the four corners.
Carefully remove the two remaining screws without allowing the drive to drop down.
Slowly lower the drive, guiding the wiring as the drive is lowered.
To install a drive, place the two center screws in the holes in the chassis.
Raise the drive, guiding the wiring through the hole.
With the drive centered, start the two screws carefully so as not to cross-thread them. Do not tighten

these screws all the way.

10.

Start the remaining screws, being careful not to cross-thread them.

11.

Tighten all screws.

12.

Insert the plugs listed in Table 6-2.

13.

Insert the power plug.

6.4 CORRECTIVE MAINTENANCE
Figure 6-2, Sheet 1, illustrates the method to be used when correcting a fault in the RX8/RX11 system. The proper

use of the KM11 module is described in Paragraph 6.4.2.

6.4.1
6.4.1.1

Errors
Interface Diagnostic in Memory — Use Figure 6-2, Sheet 2.

6-4

SYSTEM FAILURE

\
LOAD

;

DEC-X8 X11
EXERCISER

POWER

TOGGLE CONT.
INITIALIZE

15 TIMES

ERROR

LOADED

CORRECTLY

RUN

(LISTING)

LOADED

PERFORM INTERFACE ONLY TESTS

THROUGH
RX01

(REF.TO
RX01

DEC-X8/X11

SWITCH ABOUT

ANY

NO (Ref.54-11398)

DIAGNOSTICY

FIRM-

WARE FOLLOW
LISTING

REFER TO
PARAGRAPH 6.4.1.2.

—

S TER.DOWN

PERFORM
DATA

_NO

R:;.IABILITY

ERROR

ENABLE ERROR

TEST

OFF

RX01

RX8/

YES

REPLACE
FUSE

EXERCISER

HLT & RUN

YES

ENAB SWITCHES

RX11

FAILURE

;gfiggs

INSERT KM11

54-1139é

MAINT. MODULE
(FIGURE 6-4)

REPLACE

YES

MEDIA

TROUBLESHOOT

FACE CABLE

SOFTWARE

(FIG. 6-3)

REVERSED

m—

POWER-UP
DISCARD

INTERFACE
'MODULE

INSERT INTER-

USING FAILING

POWER

REPLACE

COUNTER = 60

W/O RUN ENABLE

POWER OFF

DIAGNOSTIC

RX01

ERROR

DOCUMENT
FOR
TROUBLE-

SHOOTING

INFORMATION

ERROR

LOAD

ERROR

YES

INTERFACE
DIAGNOSTIC

POWER ON

//”/’//’—

DOES

DIAGNOSTIC DOCUMENT

REPLACE

YES

DEFINE

INTERFACE

~CABLE

REPLACEABLE

LOADED

CORRECTLY

LOADED

UNIT

POWER

THROUGH

OFF

TROUBLESHOOT

RX01
|

USE

OSCILLOSCOPE

YES

POWER OFF,
RUN INTERFACE

REFER TO

DIAGNOSTIC

PARAGRAPH 6.4.1.2

(SA-200)

POWER
OFF

EXITTO

APPROPRIATE

REPLACE
FALTY UNIT

REPLACE

CONTROLLER

ERROR

MODULE

ROUTINE

YES

DISCONNECT
INTERFACE

USE

POWER ON

OSCILLOSCOPE
TO

CABLE

TROUBLESHOOT

FIELD
= 0

SELECT FLD=0010

COUNTER=0'S

NO
ERROR

YES

'CP-1542a

Figure 6-2

Troubleshooting Flow (Sheet 1 of 2)

6-5

POWER

OFF

COUNTER=
10,20

REPLACE

INTERFACE
NO

MODULE
COUNTER=30

DKO, DK1
P7-7 18

POWER

> 0VOLTS AND
<5VOLTS
NO

HEADS
STEP OUT 10
YES

TRACKS

POWER OFF

NO
.

CHECK SEL TRK OH
'ERROR

ON ONE DRIVE

SIGNAL

(M7726-D5)
(M7727-D6)

DKO, DK1

ONLY

REPLACE DRIVE

P7-7 IS ALWAYS

> 0VOLTS
AND <5 VOLTS

YES

POWER

OFF
POWER OFF

POWER ON

POWER OFF

REPLACE

REPLACE R/W

DRIVE

REPLACE

POWER

FAILING

OFF

PART

MODULE
INSERT THE

BCOSL-15

POWER ON

ERROR

REVERSED
(Fig. 6-3)

POWER ON

i
YES

POWER

{
YES

POWER OFF

ERROR

‘

REPLACE

ERROR

YES

CONTROLLER
MODULE

YES

REPLACE

CABLE

POWER ON

USE

OSCILLOSCOPE
TO

TROUBLESHOOT
PERFORM

ERROR

THE ACCEP-

TANCE TESTS

(CHAPTER
2,
PARAGRAPH

2.4.4)

USE KM11 &
OSCILLOSCOPE

TO
TROUBLESHOOT
CP-1542b

Figure 6-2

Troubleshooting Flow (Sheet 2 of 2)

6-6

BCO5L-15

7436 -1

F igure 6-3

BCOSL 15 Cable (Reversed) (Sheet 1 of 2)

6-7

BCO5L-15

7436-16

Figure 6-3 BCO5L-15 Cable (Correctly Inserted) (Sheet 2 of 2

6.4.1.2 Diagnostics Not in Memory — Since the RX8/RX11 may be the only input device for a system, there may

not be a way to input the diagnostics into the system. In that event, the following routines (Figures 6-4 and 6-5) and
the use of the Initialize Diagnostic Routine residing in the controller’s firmware may aid in the repair of the floppy
disk system.
1.

Load the following routines (Figures 6-4 and 6-5) into main memory.

Starting at location 200 (RX8) or 1000 (RX11), initiate the program.

Examine the status locations for failure information.
ESTAT,R1

DSTAT,RO
EREG,R2

DRSTAT

A good pass with a media installed in drive O will be:
ESTAT)/Os

DSTAT/45 or 104
EREG/Os

DRSTAT/2045 or 3044

Neither the read/write controller module nor the drives will cause the program to continuously loop on
the first check of the Done flip-flop.

If the program halts at any location other than the halt at the end of the program, the controller or
interface module could be at fault.

If the program halts at the end of the program with the following status, the controller is most likely at
fault.

ESTAT/4s
DSTAT/Os
EREG/60g

DRSTAT/X

All other valid error status will probably be caused by the read/write controller module, the drive, or the
floppy disk controller module. It should be noted that a Read Sector is not performed on drive 1;
therefore, it is possible for a fault to inhibit reading on both drives without reporting that information.
6.4.2

KMI11 Usage

The KM11 maintenance module may be used to single-step through a routine in the floppy controller’s firmware. It
should be noted that at times the controller will be accessing a signal produced from the media; in this case, the
KM11 cannot single-step the microprogram. For the correct method of inserting the KM11, refer to Figure 6-6. The
representation of the lights and use of the switches is shown in Figure 6-7. To start a functional routine, the
command must be issued from the central processor.

6-9

TRIEE

/RX8

STATUS

6771

ROUTINE

LCD=6771
XDR=6772

6772
6774

SER=6774

6775

SDN=6775

6777

INIT=6777

0200

¥0200

0200

6775

SDN

0201
0202

5200

JMP

6774

SER

0203

5207

. +4

0204

6772

JMP
XDR

/BRANCH QON NO ERROR
/TRANSFER DATA = RX01

0205

3227

DCA

ERSTAT

/SAVE

/SKIP

/WAIT

FOR

DONE

FLAG

/SKIP

ERROR

FLAG
FLAG

LOCATION

0206

5211

JMP

. +3

/BRANCH

0207

6772

XDR

0210

3226

DCA

DNSTAT

/SAVE

LOCATION

0211

1225

TAD

RDEREG

/GET

READ

ERROR

0212

6771

LCD

/LOAD

THE

0213

6775

SDN

/SKIP

0214

5213

JMP

0215

6774

SER

0216

. 7410

SKP

/UNCONDITIONAL

0217

7402

HLT

/FATAL

OVER

/TRANSFER

FOR

DONE

ERROR

6772

XDR

0221

3230

DCA

0222

7402

HLT

/REPLACE

0223

67717

INIT

/INITIALIZE

0224

5200
0016

0226

0000

0227

0000

RDEREG,
DNSTAT,
ERSTAT,

JMP 200
0016
O

/L0OP

0225

0230

0000

EREG,

/TRANSFFR

/SAVE

HASH
RX01

STATUS

DONE

STATUS

COMMAND

FLAG
SKIP

FAILURE

ERROR

0220

STATUS

FLAG

/SKIP

"READ

COMMAND
DONE

/WAIT

/A
EREG

THIS

DATA

STATUS

ERROR

REG"

DATA

EXECUTE

COMMAND

RX01

ERROR

REG

LOCATION

ERROR

REG

WITH

(7000)

LOOP

NOP

RXO01

0
$

Figure 6-4

sRX11

177170
177172
000000

STATUS ROUTINE
sRO = STATUS REG
sR1 = STATUS REG
sR2 = RX01 FRROR
RXCS=177170

000002

R2=%2

001000

001006

001774

001010

005767

001014

100424

001016

010067

DONE
DONE

COMES
COMES

UP
UP

CONTENTS

&
&

NO ERROR FLAG
ERROR FLAG
(SPECIFIC ERROR CODE)

RO=%0
Ri=%1

032767

IF
IF

RXDB=177172

000001

001000

RX8 Status Routine

.=1000
000040

176162

START:

176154

BIT

#40,RXCS

; TEST

DONE

BIT

BEQO

START

sWAIT

FOR

DONE

s TEST

ERROR

TST

176150

RXCS

BIT

(MSB)

INITER

‘

BMI

INITER

sBRANCH

RO,RXDB
#17,RXCS

sPUT DONE STATUS IN RO
s ISSUE READ ERROR REG COMMAND

INITIALIZE

s TEST

DONE

BIT

FOR

DONE

001022

012767

000017

176140

READ:

MOV
MOV

001030

032767

000040

176132

READ1:

BIT

#40,RXCS

001036

001774

REQO

READI1

sWAIT

001040

005767

RXCS
READ2

s TEST ERROR BIT (MSB)
sBRANCH TO READZ2 IF NO

176124

001044

100001

001046

TST
BPL

000000

HALT

s FATAL

]
MOV RXDB,R2
HALT

sIN "READ ERROR REG" COMMAND
sPUT SPECIFIC ERROR CODE IN R2

MOV

;ISSUE

RXO01

+ START

OVER

001050

016702

001054

000000

001056

012767
000745

040001

016701

176100

001064
001066

001072

176116

READ2:

176104

INITER:

#40001 ,RXCS
START

MOV

RXDB,R1

000753

000001

+END

READ

Figure 6-5

ERROR

s NORMAL

sPUT
;GO

HALT

ERROS
READ

RX11 Status Routine

6-10

ERROR

REPLACE

STATUS

BIT

ERROR

OCCURED

INITIALIZE

ERROR

WITH

NOP

BIT

(240)

LOOP

M7726

70-10718

7436-8

Figure 6-6 KM11 Maintenance Module Inserted

’

|
HALT

RUN

ENAB

INST 1

INSTO

[
SELECT

CONTINUE

l
FIELD

FIELD

PCO

ERROR
HLT

UNUSED

PROGRAM

COUNTER

COUN TER

CP-1543

Switch

Function

RUN ENAB

ON:

M7726 Clock

OFF:

Maint. Clock Pulses (Continue)

CONTINUE

ON:

Advance Controller Firmware Once

ERROR HLT

ON:

Halt Controller When Error Detected

OFF:

Do Not Halt On Error Condition

OFF:

—

Lights

Function

HALT

Firmware Halted

INST 1and O

Instruction Bits

SELECT FLD

Selects 1 of 16 Conditions (Depends on Instruction)

CO and C1

Control Functions (Depends on Instruction)

FIELD

ROM Field

PROGRAM COUNTER (0-7)

(Halted) Address +1 of Instruction Displayed

COUNTER (0-7)

Displays Contents of Counter Register

Figure 6-7

KM11 Light and Switch Definitions for RX01

6-12

TENEE

Table 6-3

Power Supply Output Voltages

Voltage
+5 Vdc

Measured At

" Tolerance
= +4.75 Vdc

P14
P2-4

<+5.25 Vdc
Ripple < 200 mV (p-p)
+9.5 Vdc

2 +9.0 Vdc

P2-7

< +10.3 Vdc

Ripple < 2.0 V (p-p)
+24 Vdc

= +23.6 Vdc

P1-1

< +28.0 Vdc

Ripple < 1.2V (p-p)

-5 Vdc

P1-6

= -4.6 Vdc
< -5.6 Vdc

Ripple < 200 mV (p-p)

+10 Vac

J1-1,3

+24 Vac

J1-2,4

NOTE

This table should be used in conjunction with the DC Power

Checks performed with Figure 6-2, Sheet 1.

6-13

Reader’s Comments

RX8/RX11 FLOPPY DISK SYSTEM
MAINTENANCE MANUAL
EK-RX01-MM-PRE2

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of
our publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, ete.? Is it casy to usc?

CUT OUT ON DOTTED LINE

What features are most useful?

What faults do you find with the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your nceds?

Why?

Would you please indicate any factual errors you have found.

Plcase describe your position.

Name

Organization

Street

Department

City

State

Zip or Country

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NORTHEAST

MID-ATLANTIC (cont.)

CENTRAL (cont.)

REGIONAL OFFICE:
235 Wyman Street, Waltham, Mass. 02154
Telephone: (617)-890-0330/0310
Dataphone: 617-890-3012 or 3013

Princeton

MICHIGAN

U.S. Route 1, Princeton, New*lersey 08540 *

CONNECTICUT

Telephome: (609)-452-2940

Meriden

240 Pomeroy Ave., Meriden, Conn. 06540

Telephone® (203)-237-8441/7466

Long
1

Dataphone: 203-237-8205

Dataphone: 609-452-2940

Island

NEW YORK

810 7th Ave., 22nd Floor

Rochester

New York, N.Y. 10019

Telephone:

130 Allens Creek Road, Rochester New Yo k

Dataphone 716-244-1680

Syracuse
6700 Thompson Road. Syracuse, New York 13211
Telephone: (315)-437-1593/7085
Dataphone: 315-454-4152

Marfborough

(212)-582-1300

MID-ATLANTIC

12401 East 43rd Street, Independence, Missouri 64055
Telephone: (816)-252-2300

Digital Hall

-St.

Suite 110, 115 Progress Parkway

Telephone: (312)-498-2500

TEXAS

(317)-243-8341

Northbrook, lllvnoxs 60062

253 Passaic Ave., Fairfield, New Jersey 07006
Telephone: (201)-227-9280

New Orleans

Metuchen

Dataphone: 412-324-9730

UTAH
A
Salt Lake City.

Telephone: (713)-777-3471

429 Lawn Dalg Drive, Salt Lake City, Utah 84115
Telephone: (801)-487-4§§9
Dataphone: 801-467-0535

6656 Hornwood Drive
Monterey Park, Houston, Texas 77036

Datophone: 312-498-2500

LOUISIANA

Dataphone: 201-227-9280

WASHINGTON®- .

Dataphone 713-777-1071

WISCONSIN

Bellevue

5100 Ridgelake Drive, Suite 108

Milwaukee

Metairie, Louisiana 70002

8531 West Capitol Drive, Mil
ke ,
Wis
1 53222
Telephone (414)-463-9110
Dataphone 414 463 9115

95 Main Street, Metuchen, New Jersey 08840
Telephone: (201)-549-4100/2000
Dataphone: 201-548-0144

Telephone: (504)-837-0257

EUROPEAN HEADQUARTERS

UNITED KINGDOM (cont.)

Dataphone: 504-833-2800

Dataphone: 505-294-2330

OREGON
Portland
Suite 168
.
5319 S.W. Westgate Drive, Portland, Oregon 97221
Telephone: (503;;?9]-3761 /3765

HOUSTON

1850 Frontage Ro

Dataphone: 303-770-6628

10200 Menual N £Albuquerque, New Mexico 87112

Plaza Nagth, Suite 513
o
2880 LBJ Freeway, Dallas, Texas 75234
Telgphone: (214)-620-2051
Dataphone: 214-620-2061

ILLINOIS

*Fairfield

Dataphone: 918-749-2714

’

Dall“;s

Dataphone: 317-247-1212

Chicago

NEW JERSEY

Albuquerque

Telephone: (505)-296-5411/5428

Telephone: (412)-243-9404

21 Beachway Drive, Suite G
Indianapolis, Indiana 46224
Telephone:

Dataphone: 213-478-5626

NEW MEXICO

400 Penn. Center Boulevard, Pittsburgh, P(enn%yWanla 15235

Indianapolis

NORTH CAROLINA
Durham/Chapel Hill
' Executive Park
3700 Chapel Hill Blvd.
Durham, North Carolina 27707
Telephone: (919)-489-3347Dataphone: 919-489-7832

Dataphone: 513-298-4724 .

PENNSYLVANIA
Pittsburgh

INDIANA

Dataphone: 305-859-2360

1510 Cotner Avenue, Los Angeles, California 90025

COLORADO
7901 E. Bellevue. Avenue
Suite 5, Englewood, Colorado 80110
Telephone: (303)-770-6150

Telephone: (918)-749-4476

Dataphone: 312-498-2500
Ex. 7
rd

Dataphone: 415-562-2160

Telephone: (213)-479-3791/4318

OKLAHOMA
ulsa -

Dataphone: 415-964-1436

West Los Angeles.

+ 3140 S. Winston
Winston Sq Bldg., Suite 4, Tulsa Oklahoma 74135

1850 Frontage Road, Nnrthbrook “Illinois 60062

Atlanta, Georgia 03040

Telephone: (404)-451-7411

Dataphone: 3%}1-455-7900 X53

-«

7850 Edgewatp'F Drive, Oakland, California 94621

3101 Kettering Boulevard
Dayton, Ohio 45439
Telephone: (513)-294-3323

CENTRAL

REGIONAL OFFICE:

GEORGIA
2815 Clearview Place, Suite 100

Te!ephone £301)-458-7900

Oakland

Telephone: (415)-635-5453/7830

- Dayton

2500 Euclid Avenue, Euclid, Ohio 44117
Dataphone: 216-946-8477

4900 Prmg_e;s Garden Parliway, Lanham, Pflewla
nd

* Dataphone: 30%5-859-2360

Atlanta

P
Dataphone: 714-280-7825

Francisco>’

Telephone: (41'5);964—6200

Dataphone: 816-461-3100

Cleveland

3
W,

1400 Terra Bella, Mountain View, California 94040

Felephone: (216)-946-8484

Dataphone: 615-584-0571

Lanham 30 Office Building

.
Orlan
Suite 130 7001 Lake Ellenor Drive, Orlando. Florida 32809

Telephone: (305)-851-4450

San

Maryland Heights, Missouri 63043

Telephone: (615)-588-6571

FLORIDA

Telephone: (714)7280-7880/7970

OHIO

San Diego
6154 Mission Gorge Road
Suite 110, San
go, California

Dataphone: 816-461-3100

Louis

Telephone: (314)-878-4310

WASHINGTON D C.

Kansas City

Philadelphia

Knoxville, Tennessee 37919

REGIONAL OFFICE:

PENNSYLVANIA

6311 Kingston Pike, Suite 21E

U.S. Route 1, Princeton; New Jersey 08540

Dataphone> 612-854-1410

MISSOURI

Knoxville

Telephone: (609)-452-2940

CALIFORNIA
Santa And
2110 S. Anne Street, Santa Ana, California 92704
Telephone: (7143-979-2460
Dataphone: 714-979-7850

8030 Cedar Ave. South, Minneapolis, Minnesota 55420

TENNESSEE
Telex: 710-347-0348

Dataphone: 313-557-3063

Telephone: (612)—8546562-345-5

Dataphone: 408-735-1820

Phoenix
e
1
4358 East Broadway Road, Phoenix, Arizona 85040
Telephone (602)-268-3488
Dataphone: 602-268-7371

Minneapolis

Telephone: (215)-825-4200

One Iron Way
Marlborough, Mass. 01752
Telephone: (617)-481-7400

Detroit

ARIZONA

Southfield, Michigan 48075

1740 Walton'Road, Blye Bell, Pennsylvanla 19422

MASSACHUSETTS

Telephone: (408);2.3&9200

Dataphone: 313-769-9883

Suite 189

Manhattan

230 Huron View Boulevard Ann Arbor, Michigan 48103

MINNESQOTA

Dataphone: 516-293-5693

REGIONAL OFFICE:

310 Soquel Way, §Sunnyvale, California 94086

23777 Greenfield Road

Huntington Quadrangle

Telephone.

1275 Post Road, Fairfield, Conn. 06430
Telephone: (203)-255-5991

WEST

Telephone: (313)-761-1150

Suite 1507 Huntington Station, New York 11746
(516)-694-4131, (212)-895-8095

Fairfield

Telephone: (716)-461-1700

Ann Arbor

NEW YORK

13401 N.E. Bellevue Redmond Road, Suite 111
Bellevue, Washington 98005
Telephone: (206)-545-4058/455-5404
Dataphone: 206-747-3754

INTERNATIONAL
Digital Equipment Corporation ints1rational Europe
81 route de I'Aire

1211 Geneva 26, Switzerland
Telephone: 42 79 50

FRANCE

GRENOBLE

Digital Equipment France

gELGI"gM
igital

France

108

Marco-Polo-Strasse 1

Telephone: (0771)-4530-65

Digital*Equipment AB

Telephone:

= A

Telex: 841-722-393

AUSTRIA

Digital Equipment Corporation Ges.m.b.H.
VIENNA

Calgary, Alberta, Canada

Telephone: (403)435-4881

Suite 202

644 S W

FINLAND

Mariahilferstrasse 136, 1150 Vienna 15, Aus!rla

UNITED KINGDOM

370133

Telex:

Helsinki

‘

Fish Ponds Road. Fnsh Ponds

Telephone:

133

Digital Equipment Corporation S.A.

Spring Hill

(08)-42-1339

Bristol. England BS163HQ"

Casilla 14588, Correo
1
Telephone: 396713
Cable COACHIL

5067

Telex:

INDIA

790-82825

Telephone

Telex:* 22371

43 Parker St.. Holborn, London

WT 2B 5PT, England
Telex:

27560

House

Chester Road. Stretford, Manchester M32 9BH
Telephone (061)-865-7011
Telex 668666

)
'

Cable: TEKHIND

St.

MEXICO

56059

ITALY

Apdo. Postal‘T? 1012

Telephone

Telephone: [995) 536-09-10

Mexico 12,
(03)-699-2888

Telex:

790-30700

PHILIPPINES|

West Perth, Western Australia 6005

‘

)

’

SEANIG

;

Ataio !ngemp‘é&s S.A, En.;IQIUE La7rreta 12, '[\Aadrld 16
elex-

Telephone (092)-21-4993

P.O. Box 491, Crows Nest

27249

Australia 2065

Telephone

(02)-439-2565

¢
MANILA] |
Stanford Computer Corporation
P.O. Box 1608

Telex: 790-92140

SYDNEY
N S W

;

416 Dasmarinas St., Manila

Telephone: 49-65-96

)
Telex

790-20740

NEW ZEALAND

Digital Equipment Corporation Ltd.

AUCKLAND

. CARACAS

Ceasin, C.A.
Apartado 50939

Hilton House, 430 Queen Street, Box 2471

Ataio Ingenieros S.A | Granduxer 76, Barcelona 6

Auckland, New Zealan

Telephone

Telephone 22144
6

Telephone: 75533

Cable: INSTRUVEN

printed in U.S.A.

Telex: 742-0352

VENEZUELA

BARCELONA
\

60 Park Street, South Melbourne, Victoria 3205

643 Murray Street

Corsosaribaldr 49. 20121 Milano, Italy

Telephone: 215 35 43

Mexitek:,'S A.

Eugenia 408'Deptos 1

PERTH

MILAN

Telex: 011-2594 Plenty

MEXICO CiTY

Australia

Telex:

SPAIN
Bigital Eauipment Corporanon Ltd

MANCHESTER

Switzerland

01-46:41-91

790-40616

MELBOURNE

Telephone: (02)-879-051/2/3/4/5 . Telex: 843-33615

LONDON

Management House

Telex:

Fyshwick, A.C.T. 2609 Australia
4G

A Digital Equipment S p A.

3
¢

Collie

Bombay-6 (WB) India
Telephone: 38-1615: 36-5344

Australia 4000

Telephone: (062)-959073

CH-8050 Zurich;

Schaffhauserstr. 315

EALING

727113

69/A, L. Jagmohandas Marg.

(072)-293088

Telephone No. 022 20 4C 20 and 20 58 923 and 20 68 93

Hinditron Computers Pvt. Ltd.

Street

Quecnsland,

Telephone:

CANBERRA

Digital Equipment Corp.

EDINBURGH
“
il
Shiel House, Craigshill. Livingston.,
West Lothian, Scotland
~

. Brisbane.

Ernest Ansermet

SANTIAGO
Coasin Chile Ltda. (sales only)

Ltd.

BOMBAY

Leichhardt

Boite Postale 23, 1211 Geneva 8, Switzerland

ZURICH

. Bilton House. Uxbradge Road, Eallnq Londoh W 5

01-405- 2614/4067

South Australia

SWITZERLAND

Telex: 28 92 01

337-060

BRISTOL

Telex:

Equipment Australia Pty.

Norwood.

Telephone: 24-7411

CHILE

AUSTRALIA

20, Quai

Buildings

Teléphone: 01-579-2334

Rua Coronel Vicente ‘421/101
Porto Alegre — RS

From Metropolitan Boston, 646-8600
710-347-0217/0212

Digital

—=*SP

. Telex', 94-8457

GENEVA

BIRMINGHAM
+29/31 Birmingham Rd . -Suttbn Coldfield
Warwickshire. England
7

Telephone' Bristol 651-431

Telephone: (617) 897-5111

PORTO ALEGRE — RS

BRISBANE

Telex* 8483278

Telephone: 021-355-5501.

Telephone: 52-7806/1870, 51-0912

Cable: DIGITAL MAYN

REGIONAL OFFICE

ADELAIDE
6 Montrose Avenue

Digital

SAO PAULO
Ambriex S.A.
Rua \Tupi, 53%

TWX:

(090)

Rio De Janeiro —
Telephone: 264- 7406/0461/7625

s
GENERAL INTERNATIONAL SALES

Digital Equipment AB

Cable

U.K. HEADQUARTERS
Fountain House. Butts Centre
Reading RG1 70N. England

Marine Dr., Vancouver

Titismaantie 6
SF-00710. Helsinki 71

Telephone:

Digital Equipmen{”Co. Ltd.

Rua Ceara, 105 2e 3 andares ZC- 29

146 Main
Street, Maynard, Massachusetts 01754
)

HELSINKI

Telephone: 85 51 86

BRAZIL
RIO DE JANEIRO— GB
Ambriex S.A.

TWX: 403-255-7408

British Columbia. Canada V6P 5Y1
Telephone: (604)-325-3231
Telex: 610-929-2006

.
Telex: 19079 DEC N

Virrey del Pino, 4071 Buenos Aires
Telephone: 52-3185 . Telex: 012-2284

610-422-4124

Suite 140, 6940 Fisher Road S.E.

2900 Hellerup. Denmark

BUENOS AIRES /
Coasin S.A.

Telex:

CALGARY /Edmonton

Telex: 170 50

Digital Equipment Aktiebolag
COPENHAGEN
3
Hellergpveg 66

(514)-636-9393

VANCOUVER

DENMARK
e
)

\'~

610-492-7118

ARGENTINA

Dorval, Quebec, Canada H9P 2M9

Oslo 5, Norway
Telephane: 02/68 34 40

Telex: 922-952

STUTLGART

TWX:

9045 Cote De Liesse

NORWAY

. D-7301 Kemnat, Stuttgart

TWX: 610-562-8732

¢ MONTREAL

Digital Equipment Corp. A/S

HANNOVER

)

SWEDEN

osLo
.
Trondheimsveien 47

Telex: 41-76-82

3 Hannover, Podbnelskvstrasse 102,

Arndale

Cable: Digital Stockholm

FRANKFURT

Telephone:

Telephone: (416)-270-9400

Telex: 25297

Telex: 781-4208

PUERTO RICO
Digital Equipment Corporation De Puerto Rico
407 del Parque Street
Santurce, Puerto Rico 00912
Telephone: (809)-723-8068/357
Telex: 385-9056

JGRONTO
%
2550 Goldenridge Road, Mississauga, Ontario

Englundavagen 7, 171 41 Solna, Sweden

6078 Neu-lsenburg 2
Am Forstaus Gravebruch 5-7

32705

Telephone. (613)-592-5111

Belgium

Telephone: 98 13 90

Telegram: Flip Chip Koeln

Telephone

STOCKHOLM

Telex: 888-2269

Telephone: (0734)-583555

Minato-Ku, Tokyo,
Japan
N

KoH

COLOGNE
5 Koeln 41, Aachener Strasse 311

Telephone: 0511-69-70-95

‘

N.V./S.A.

Telephone: 02-139256

Telex: 524-226

Telephone: 06102-5526

No. 18-14 Nishishi mbashl 1-Chome

Telephone: 5915246

Ottawa Ontarlo Canada

Rue D'Arlon

1040 Brussels,

GERMAN FEDERAL REPUBLIC

MUNICH
8 Muenchen 13, Wallensteinplatz 2

0221-44-40-95

Equipment

)

BRUSSELS

Telex: 212-32882

Digital Equipment GmbH

Telephone: 0811-35031

FiSr R 1

Kozato-Kaikan®

Digital Equipment of Canada, Ltd.

CANARIAN HEADQUARTERS

)

Telex 1-26428

Rikei Trading Co . ltd. (sales only)

~g%-v’\.lf'AGtUE Churchillian 370
:

16 Rue Du Gal Mangin
38100 Grenoble,

Telephone: 94 9220

Telex: 32533

Telephone: 586-2771

Telex: 922-33-3163

CANADA

Sl
ol
Rijswijk/The Hague, Netherlands

Tour Mangin

Telephone: (76)-87-56-01

Digital Equipment N.V.

Kowa Building No. 16
— Annex, First Floor

9-20 Akasaka 1-Chome
Minato-Ku, Tokyo 107, Japa

Tel Aviv, Israel
Telephone: (03) 443114/440763

NETHERLANDS

Digital Equtpmen' Corporation International

Suite 103, Southern Habakuk Street

Telex: 8483278

)

Centre Silic — Cidex L 225
94533 Rungis, France
Telephone: 687-23-33
Telex: 26840

Maney

TEL AVIV

Telephone: (0734)-583555

Digital Equipment France

Telephone:

DEC Systems'Computers Ltd.

Fountain House. Butts Centre

Reading RG1 70N, England

Telex- 22 683

JAPAN

ISRAEL

READING

v oo

Sabana Grande Mo. 1, Caracas 105
72-8662; 72-9637