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Document:	RQDX1 Controller Module User's Guide
Order Number:	EK-RQDX1-UG
Revision:	001
Pages:	62
Original Filename:

OCR Text

EK-RQDX1-UG-001

RQDX
Coniroller Module
User’'s Guide

dlilglitial1|

EK-RQDX1-UG-001

RQDX1
Controller Module

- User’s Guide

Prepared by Educational Services
oOf
Digital Equipment Corporation

First Edition, January 1984

Printed in U.S.A.

The material in this document is for informational purposes and is subject to change without notice; it should not be
construed as acommitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

Notice: This equipment generates, uses, and may emit radio frequency energy. The equipment has been type tested
and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules,
which are designed to provide reasonable protection against such radio frequency interference when operated in a
commercial environment. Operation of this equipment in a residential area may cause interference in which case the
user at his own expense may be required to take measures to correct the interference.

The manuscript for this book was created using a DIGITAL Word Processing System and, via a translation program,
was automatically typeset on DIGITAL’s DECset Integrated Publishing System. Book production was done by
Educational Services Development and Publishing in Marlboro and Bedford, MA.
The following are trademarks of Digital Equipment Corporation.

dlijgliltlall

DEC
DEChnet
DECUS
DECsystem-10
DECSYSTEM-20
DECwriter
DIBOL
DIGITAL
EduSystem

IAS

LA
LETTERPRINTER 100
LETTERWRITER 100
LSI-11
MASSBUS
MICRO/PDP-11
MINC-11
OMNIBUS
0S/8

PDP

PDT
RSTS
RSX
TOPS-10
TOPS-20
UNIBUS
VAX
VMS
vT

CONTENTS
Page
PREFACE

FEATURES .. o

ENEIRE S

SN
G
s B
T
T

DE SCRIPTION ..o

INTRODUCTION

LW W WA

CHAPTER 1

1-1

ettt

1-2

SPECIFICATIONS........... e e e et
e,
RQDX1 Disk Controller Module. ............c.iiiiiiiiiiiinnennnn...
RDSIDiskDrive . .. oot
it i i i st e e i
RXS0 Diskette Drive . .. ..ottt
iii ittt it i it e iinenns,
RQDXI1-E Extender Module Option. ..............ccoiiiiiiniiiinenn...

1-2
1-2
1-3
1-4
1-6

CHAPTER 2

FUNCTIONAL DESCRIPTION

2.1

INTRODUCTION. . .

2.2
2.3

2.4
2.5

2.6
2.7
2.8
2.9

2.10
2.11

2.12
2.13

2.14

2.15
2.16
2.17

ettt

it
i i
it et it ettt ettt ennnens 2-1
BLOCK DIAGRAMDESCRIPTION . ...ttt
ittt e
e 2-1
SHUFFLE STEP OSCILLATOR. . ...ttt
it i ittt eiieeens 2-3
PHASE LOCKED LOONP. . . ...ttt
it
ettt sttt ettt e iie s 2-4
DATA RECOVERY ...ttt
it et sttt 2-5
SYNC MARK DETECTOR ...t
it it e it 2-5
SERIALIZER/DESERIALIZER . ...ttt
ittt et iie e 2-6
MFM ENCODER/PRECOMP GENERATOR. ...........c.ciiiiiiinnnnnn.. 2-6
INTERRUPT VECTOR REGISTER. . .....oitiiiii
ittt
iie e 2-8
SA READ REGISTER, SA WRITE REGISTER, IP REGISTER ............ 2-8
QBUS TRANSCEIVERS AND HANDSHAKE CONTROLLERS........... 2-8
RQDX1 CONTROL LOGIC. . ...ttt
ittt
ettt e i iiaee e 2-10
MEMORY ADDRESS COUNTER/REGISTER ...............ccoivvunnnn.. 2-12
2 K X 16 RAM .
e
e e
e 2-12
DISK DRIVE CONTROL REGISTER AND STATUS BUFFER............ 2-12
T-11 RAM ADDRESS POINTERAND ALU ..........iiiiiiiiiiiinnn.. 2-14

2.18

BIDIRECTIONAL BYTE MULTIPLEXER ..........ccoiiiiiiiiiiinnnnn, 2-14
30 SO
3020
)
2-14

2.19

QBUSDMA POINTER AND ALU .....iiiiiiii
ittt iiineinnennns 2-14

CHAPTER 3

CONFIGURATION AND INSTALLATION

INTRODUCTION. ...

e tieeenns

DEVICE ADDRESS SELECTION . .......ciiiiiiiiiiiii
ittt iie i

LOGICAL UNITNUMBER SELECTION ........cciiiiiiiiiiiniieinenns.
INTERRUPT VECTOR ...t
i et ettt it cie e inenns
INTERRUPT REQUEST LEVEL ...... ..ottt
ittt iiiiinnnenn.

£ i

RQDX1 CONTROLLER MODULE INSTALLATION ....................
RQDXI1-E EXTENDERMODULE OPTION ..........coiiiiiiininnnnnnn

RQDX1-E Extender Module Jumper Configuration......................
RQDX1-E Extender Module Installation..................ccivvenn....

iii

3-1
3-2
3-3
34
3-4
3-4
34
3-5
3-6

CONTENTS (Cont)
Page

CHAPTER 4

REGISTERS AND COMMANDS

4.3.1
4.3.2
4.4
4.4.1
4.4.2

INT RODU CTION . .ttt ittt ittt ettt tstrataneasnenaacansnsas RS . ..ot ittt ittt it ettt teeneastetasnennanensnsnnnnanensns
REGISTE
Initialize and Poll Register (IP)........ ..ot
Status and Address Register (SA) ... .o iiii ittt
MASS STORAGE CONTROL PROTOCOL (MSCP).........coiviviinn.n.
MSCP Commands . .. ovvvvrerinneensasrensereasnsasnsnsesoonasasas
MSCP Status Codes. ..o vvive ittt iiiinieniianttnareasenasansnns e
DIAGNOSTICS AND UTILITIES PROTOCOL(DUP)...........covivn.n.
DUP Commands ......ouvietierreeenenearoretoeessasssnsnsenesanens
DUP RESPONSES .+« vt veetveraneeeseenunsteenananrsssninensonsansees

CHAPTER 5

ERROR DETECTION

4.1
4.2

W
W

W N

4.2.1
4.2.2
4.3

4-1
4-1
4-1
4-1
4-2
4-3
4-4
4-5
4-5
4-6

ittt it ananaans AP e 5-1
ttt
ittt
INTRODUCTION . ..o
DIAGNOSTIC LED ERRORDISPLAYS . ...t e 5-1
i iiiiiin i e 5-3
DIAGNOSTIC SOFTWARE ..ottt
DISK DRIVES

6-1
6-1
6-2
6-3
6-4

INT RODU CTION . . .ottt ittt ittt et e e estn e tietasnenrarrannens
RDSIDISK DRIVE ...ttt ittt ittt tatstrttitnensarasenoasaans
inena.
ittt iiii
RD51 Disk Drive Installation. .........ccoiiiiii
Formattingthe RD51 Disk Drive. ......ccoviiiiiiiii i,
TE DRIVE . .. it ittt it e iiiasaenanans
RXSODISKET

APPENDIX A

RQDX1 CONTROLLER MODULE BACKPLANE PIN ASSIGNMENTS

APPENDIX B

RQDX1 CONTROLLER MODULE CABLE SIGNALS

APPENDIX C

DISK DRIVE CABLE CONNECTOR PIN ASSIGNMENTS

C.1
C.2

RD51 DISK DRIVE CONNECTOR PIN ASSIGNMENTS................. C-1
RX50 DISKETTE DRIVE CONNECTOR PIN ASSIGNMENTS ........... C-3

o\ O O O O
Wi
=

CHAPTER 6

FIGURES

VB WNNEEEFOOVMAEWN=O® NN
B WN

A WLWW WWWWwWNNNdDNDNDNDNDN
> ANV
T+t
1§
1t
1
1
1_t
&
bt
ot

Figure No.

Title

Page

RQDX1 Controller Module Functional Block Diagram ....................... 2-2
Shuffle Step OScCillator . ......oviiiiiiii
i i i i it i it ct it eeenens 2-3
Phase Locked Loop LOgiC .....ciiiiiiii
ittt ittt it it it i 2-4
Data Recovery and Sync Mark Detector Logic...........coviiiiniiinnenn.. 2-5
Serializer/Deserializer and MFM Encoder/Precomp Generator Logic ........... 2-7
Interrupt Vector Register, SA Registers and QBus Interface Logic............... 2-9
T-11,RAM and ROM LogiC . v vt ittt it i et
e e et ettt
enenens 2-10
Main High-Speed Controller Architecture ............covvvvnvnnn.. P 2-11
Disk Drive Control Register and Status Buffer ....................civvin.... 2-13
RQDX1 Controller Module Jumper and LED Locations ...................... 3-1
RQDX1 Address Selection Jumper Format .................cciiivinnnnnnn. 3-2
RQDX1 Logical Unit Number Jumper Format ..............covviiinvun.n.. 3-3
RQDX1 MICRO/PDP-11 Signal Distribution Connections. ................... 3-4
RQDX1-E Extender Module Jumper Locations. ..............covvvvvvnnnn... 3-5
RQDX1-E Extender Module Connections .............cciiiiiiniennnennn. 3-6
Memory “Communications Area” Organization.............ccoviiiinvnnennn.. 4-2
Diagnostic LED Locations. . .......cuvtiiiii
ittt it it ieieriennnens 5-1
RD ST Disk Drive. . oottt ittt it i s e ettt it et et
ennens 6-1
RD351 Disk Drive Read/Write Printed Circuit Board.......................... 6-2
RD51 Disk Drive Head Positioner Flag. . ..............c
i iiniiiinnn... 6-3
RD51 Serial Number Label Location. . .............coiiiiniininiininnnnen.. 6-4
RX S0 Diskette Drive .. .oivi
ittt ittt ittt ettt et et et in e nenns 6-5
Quad Module Contact Finger Identification .................ciiiiiiiinn.n. A-1

TABLES

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oloRoXoNe!

f—t

R
|iw|> — DD] =] G[] N1 P1 G] N1 keI ]
WN = -

b bobWw
W

Title

Page

RQDX(1 Controller Module Configurations. ...........ccciiiiiiiieennnnn.

1-1

RQDX1 Standard Address Jumper Configuration ..................ccivvnn...

3-2

RQDX1 Standard Logical Unit Number Jumper Configuration................. 3-3
RQDX1-E Extender Module Jumper Configuration .......................... 3-5
MSCP Commands. . ...oviittt ittt ittt ittt etn e
enenneanns 4-3
MSCP Status Code Messages . ... vvvvtittin it ittt it
e iteeneenennen, 4-4
DU
P Programs. .. i ittt ittt ittt ittt it et i te ettt 4-5
Diagnostic LED Error Displays . ......c.cooiiiiiiiiiiiiiiiiiiiiiiiirennnen. 5-2
XXDP+ Diagnostic Programs .......... ett
ettt i e
e 5-3
DIP Shunt Jumper Configuration ............ciiiiiiniiiiiiiniiernennenenn. 6-2
RQDX1 Controller Module Backplane Pin Assignments ...................... A-2
J1 Connector Signals. . ...vvii ittt ittt ittt ettt i
e B-1
. RDS51 Disk Drive J1 Signal Connector Pin Assignments ......................

C-1

RD51 Disk Drive J2 Signal Connector Pin Assignments ..............c.covvn..

C-2

RDS51 Disk Drive J3 Power Connector Pin Assignments ......................
RX50 Diskette Drive J1 Connector Pin Assignments .........................
RX50 Diskette Drive J3 Power Connector Pin Assignments ...................

C-2
C-3
C-3

PREFACE

This user’s guide provides information on the configuration, installation, and operation of the RQDX1 disk
drive controller module, the associated disks (the RD51 Winchester fixed disk drive and the RX50

diskette drive), and the RQDX]1-E extender module option.

Chapter 1 provides environmental and functional specifications for the RQDX1 controller module,
the
RDSI fixed disk drive, the RX50 diskette drive, and the RQDX1-E extender module option.

Chapter 2 gives a functional description of the RQDX]1 controller module.

Chapter 3 presents configuration and installation information for the RQDX1 controller module and the
RQDX1-E extender module option.
Chapter 4 describes the programmable registers that are LSI-11 bus addressable on the RQDXI controller
module. Mass storage control protocol (MSCP) and diagnostics and utilities protocol (DUP) are also
briefly described.

Chapter 5 provides testing and error detection information.
Chapter 6 presents installation and operation information for the RD51 fixed disk drive and the RX50
diskette drive.
RELATED DOCUMENTATION
The following documents provide additional information and may be of interest to RQDX1 controller
module users.
Document Title

Document Number

RQDX1 Field Maintenance Print Set
UDASO Programmer’s Documentation Kit

QP-905-GZ

MP-01731-01

In addition, users may refer to documentation for the specific system in which the RQDXI1 controller
module is installed.

vii

CHAPTER 1
INTRODUCTION

1.1
DESCRIPTION
The RQDX1 disk drive controller module interfaces the RD51 disk and/or RX50 diskette drives to any

quad- or hex-size backplane that uses a 16-, 18-, or 22-bit LSI-11 bus. The backplane must be in a
mounting box (such as a BA23) that provides a control panel and a signal distribution panel. A single
RQDX1 module controls any one of the configurations listed in Table 1-1.

Table 1-1

RQDX1 Controller Module Configurations
Logical Disk

Configuration

Physical Disk Drives

Drive Numbers

One RDS51, one RX50

Unit 0 = RDS51

Unit 1, 2 = RX50
2

Two RX50s

Unit 0, 1 = RX50

Unit 2, 3 = RX50

Two RD51s

Unit 0 = RD51

One RXS50

Unit 1 = RD51
Unit 2, 3 = RX50

Two RDS51s

Unit 0 = RD51
Unit 1 = RDS51

One RX50

Unit 0, 1 = RX50

One RD51

Unit 0 = RD51

These configurations require the use of the optional RQDXI-E extender module. Refer to Paragraph 3.7 for additional
RQDX1-E information.

The RD51 disk drive is a random access storage device, which uses two nonremovable 133.4 mm (5.25

inch) disks as storage media. The RDS1 disk drive has a total formatted storage capacity of 11 megabytes.
The RX50 diskette drive is a random access storage device, which uses two single-sided 133.4 mm (5.25

inch) RX50K diskettes. The total storage capacity of the RX50 diskette drive is 800 kilobytes of
formatted data.
The RQDX1-E extender module option provides cable connection to a single disk or diskette that is

mounted externally from the MICRO/PDP-11 (BA23) mounting box.

1-1

1.2

FEATURES

The RQDX!1 controller module has the following features.

1.3

1.3.1

Single quad-size module.

Supports DMA data transfers in 16-, 18-, or 22-bit addressing modes.

Supports block mode transfers with MSV11-P memories.

Supports 22-bit addressing on an LSI-11 bus.

Memory parity error abort feature for use with memories that have a parity option.

Requires no jumper/switch reconfiguration when adding or removing RD51 or RX50 drives.

SPECIFICATIONS

RQDXI1 Disk Controller Module

Module

1 quad-size module, M8639

Size

Height: 26.56 cm (10.46 in)
Width: 1.27 ¢cm (0.5 in)
Length: 22.70 cm (8.94 in)

Power Requirements

+5 Vdc £5% at 6.4 A (typical)
8.0 A (maximum)

+12 Vdc 5% at 7.3 mA (typical)

10 mA (maximum)

Bus Loads
AC Bus Loads
DC Bus Loads

2.5
1

Addressing Modes

16-, 18-, and 22-bit
(determined by user)

Limitations

The RQDX1 will not fit in the
dual-height LSI-11 mini-series
H9281 backplane.

Drives Per Controller

Up to four logical units, no more
than two RD51 disk drives

LSI-11 Bus-Addressable
Registers

Base Device Address
(Standard)

Addressing Mode

Address (Octal)

16-bit
18-bit

172150
772150

22-bit

17772150

1-2

Vector

Software selectable
(Normally set at 154)

Data Transfer Rate

800 ns/word (peak) controller to host

Environmental Specifications
Temperature

Storage
Operating

—40°C to 66°C (—40°F to 150°F)
5°C to 50°C (41°F to 122°F)

Relative Humidity

Storage
Operating

10% to 95%, noncondensing
10% to 95%, noncondensing

Altitude
Storage
Operating

9.1 km (30,000 ft) maximum
2.4 km (8,000 ft) maximum

Airflow

Operating up to 50°C

Maximum temperature rise across
module must not exceed 20°C (68°F)

input to output.
1.3.2

RDSI1 Disk Drive

Storage Type

Medium

Winchester fixed disk

Recording Surfaces

4 cata surfaces

Magnetic Heads

4 read/write heads

Recording Method

Modified frequency modulation (MFM)

Performance Specifications

Recording Capacity
(Formatted)
Bytes Per Sector

512 bytes

Sectors Per Track

18 sectors (track size)
Each sector has a logical block
number (LBN)

Tracks Per Group

4 tracks (group size)

Groups Per Cylinder

3 groups (cylinder size)

Cylinders Per Unit

100 cylinders

Total Cylinders
Per Unit

102 cylinders*

Total Bytes Per Unit

11.059 M bytes
5,000,000 bits/s
(625 K bytes/s)

Transfer Rate

Access Time (Buffered Seek, Including Settling)
Average

85 ms

Maximum

205 ms

Average Latency

8.33 ms

Functional Specifications

Rotational Speed

3,600 r/min (x1%)

Recording Density

9,074 bits/in (maximum)

Track Density

345 tracks/in

Environmental Specifications

1.3.3

Ambient Temperature

10°C to 50°C (50°F to 122°F)

Relative Humidity

20% to 80% noncondensing

Maximum Wet Bulb

25.6°C (78°F)

RXS50 Diskette Drive

Storage Type
Medium

Diskette

Recording Surfaces

2 data surfaces

Magnetic Heads

2 read/write heads

Recording Method

Modified frequency modulation (MFM)

* Cylinders 100 and 101 are assigned as follows.
Cylinder 100, Group 0:
Cylinder 100, Groups 1, 2:
Cylinder 101, Groups O, I:
Cylinder 101, Group 2:

Replacement and caching table (RCT)
Format control table (FCT)
Replacement block numbers (RBNs)
Diagnostic block numbers (DBNs)
Reserved

1-4

Performance Specifications

Recording Capacity
(Formatted)
Bytes Per Sector

512 bytes

Sectors Per Track

10 sectors (track size)
Each sector has a logical block
number (LBN).

Tracks Per Group

5 tracks (group size)

Groups Per Cylinder

16 groups (cylinder size)

Cylinders Per Surface

1 cylinder

Bytes Per Surface

404,480 bytes

Surfaces Per Unit

2 surfaces (2 diskettes)

Bytes Per Unit

808,960 bytes

Transfer Rate

250,000 bits/s
(31.25 K bytes/s)

Access Time

Minimum

Typical

Maximum

Track to Track

6 ms

Head Settling Time

—

30 ms

Head Load Time

30 ms

Rotational Latency

100 ms

200 ms

Random Access

—

264 ms

Drive Motor Start

—

250 ms

Functional Specifications
Rotational Speed

300 r/min (+1.5%)

Recording Density

5,576 bits/in (maximum)

Track Density

96 tracks/in

Environmental Specifications
Ambient Temperature

15°C to 32°C (59°F to 90°F)

Relative Humidity

20% to 80% noncondensing

Maximum Wet Bulb

25°C (78°F)
1-5

1.3.4

RQDX1-E Extender Module Option

Module

1 dual-size module, M7512

Size

Height: 13.2 cm (5.2 in)
Width: 1.27 cm (0.5 in)
Length: 22.8 cm (8.9 in)

Power Requirements

+5 Vdc at 0.5 A (typical)

0.6 A (maximum)

Bus Loads

AC Bus Loads
DC Bus Loads

Provides signal distribution to a
single disk or diskette drive

Limitations

Cannot be used on the PDP-11/23 Plus
Environmental Specifications
Temperature

Storage
Operating

—40°C to 66°C (—40°F to 150°F)
5°C to 60°C (41°F to 140°F)

Relative Humidity
Storage
Operating

10% to 95%, noncondensing
10% to 95%, noncondensing

Altitude
Storage
Operating

9.1 km (30,000 ft) maximum
2.4 km (8,000 ft) maximum

Airflow

Operating up to 50°C

Maximum temperature rise across
module must not exceed 20°C
(68°F) input to output.

CHAPTER 2
FUNCTIONAL DESCRIPTION

2.1
INTRODUCTION
The RQDXI1 controller module interfaces the RD51 disk drive and/or RX50 diskette drives to a 16-, 18-,
or 22-bit LSI-11 bus. One RQDXI controller module can support up to four logical units in any
combination of RD51 and RXS50 drives (up to two RD51 drives per RQDX1 controller module). The
RQDXT1 controller module (M8639) has the LSI-11 bus transceivers and decoders, programmable registers, controller timing and sequence logic, and the data formatting circuits necessary to read and write on
the RDS51 disk media and/or the RX50 diskette media.

2.2
BLOCK DIAGRAM DESCRIPTION
The main functional subsections of the RQDX1 module are shown on the block diagram in Figure 2-1.
The block diagram illustrates the basic architecture and the data path relationships of the major subsections. The RQDXI1 controller module is a bus-oriented system controlled by a system control function
shared by the T-11 chip and the main high-speed controller.
The major subsections of the RQDX1 are as follows.
Shuffle step oscillator
Phase locked loop
Data recovery
Sync mark detector
Serializer /deserializer
MFM encoder/precomp generator
Interrupt vector register
SA read/write registers, IP register
QBus transceivers and handshake controller
RQDXI1 control logic: T-11 chip and main high-speed controller
Memory address counter/register
2K X 16 RAM
Disk drive control register and status buffer
T-11 RAM address pointer and arithmetic logic unit (ALU)
Bidirectional byte multiplexer
8 K X 16 PROM
QBus DMA pointer and ALU

2-1

N
Q-BUS

Q-BUS

CONTROL

SIGNALS
Q BUS/XQDAL
RAW READ DATA

TRANSCEIVER

Q-BUS TRANSCEIVER

SHUFFLE

XQDAL BUS

os¢
PHASE

LOCK LOOP

—
NRZRDDATA

TRANSCEIVE

XQDAL/DAL R

“SA" WRITE

“SA” READ

PLL CLOCK

RECOVERY

DATA

IVNEI;ET%F;UPT

{SINGLE MODE)

AND SATELLITE
HANDSHAKE CONTROLLERS

—A0H

SYNC MARK

(no data)

MICROPROCESSOR

(7.5 MHZ, 16 BIT)

REQTIIDMA

z':“G'S SPEED

INIT

T1IDMAACK

CONTROLLER

TIMEUP

TAKE BUS

{100 ns/STATE)

{}

- ADDRESS (DAL) BUS
DATA

-~ CONTROL -

WRITE DATA

XTAL

DETECT

{

\\»n16

1 *1P~ REGISTER |
L__.[___I

r—-—=

WRITE

CLOCK

MEMORY ADDRESS
.

Bi DIR

SERIALIZER/DESERIALIZER

NRZ WRITE DATA

MUX

—
READ DATA

\1——|

ADR

x 16
2K

MFM ENCODER AND

CONTROLLER

STATIC RAM

PRECOMPENSATION

DMA POINTER

Q BUS ADDRESS
DMA POINTER

and ALU

’____—I

—_—

TIMER

T1t RAM ADDRESS

PROGRAMMABLE

ADR

DAT

8K x 16
EPROM

DEVICE CTL BLOCK

DRIVE CONTROL

DRIVE STATUS

BUFFER

SECTOR BUFFER

WRITE DATA

DISK DRIVE

MR- 10587

Figure 2-1

RQDX1 Controller Module Functional Block Diagram

2.3 SHUFFLE STEP OSCILLATOR
The shuffle step oscillator (Figure 2-2) is a system of two matched 10 MHz oscillators, a small asynchronous oscillator controller, and a read data delay equalizer. When one of the oscillators is generating a raw
read clock signal for the phase locked loop (PLL), the other oscillator is in stand-by. At each raw read data
pulse, the active oscillator is commanded to turn off and the stand-by oscillator is commanded to become

active. This causes the oscillators to “shuffle” to keep in step with the RAW read data. The read data
delay equalizer section delays the RAW read data to compensate for the short amount of time that it takes
to shuffle the oscillators.

o =

ajo

P Y

<1<

ac|x

ZI>|2

Jlzlz

3210
SELFLOPY(H)—#TM B

8 TO 1 MUX

SELWINCH1(H)—} A

(74LS151)
,

RSTRDF/F(L)

JL +V

ROF/F|

INITDVDR(L)

(74574)

5§

l
ECL—>T2L

T2L—+ECL

EXanRs

(10131)

0SC 1

(10131)

D.L

0SC 2

DELAY

EQUALIZER

At
—
= 50 NS

’

ECL—+T2L

ECL->T2L

1OMRAWOSC(H)

DLQRDDATA(H)

v
MR-11289

Figure 2-2

Shuffle Step Oscillator

2-3

2.4

PHASE LOCKED LOOP

The phase locked loop (PLL) logic is shown in Figure 2-3. The PLL is a dual-channel, single-mode system.
Dual channel provides one channel for the RX50 diskette drive(s) and one channel for the RD51 disk
drive(s). The function of the PLL logic is to provide the “flywheel” effect for the shuffle step oscillator
output, thus integrating the effects of the “pulse drift” in the RAW read data. The output of the PLL is
fed into a counter which generates two data recovery window signals. These “windows” are generated in a
way to center the read data pulses. (At any given time the data will be framed by one of these windows.)
The proper data framing window is selected automatically by the sync mark detector.

REFCLK(H)

)
PHASE DETECTOR

(74574

74564)

PMPUP(L)I

I PMPDWN(L)}

ACTIVE FILTER
AND CHARGE PUMP

SELFLCPY(H)

HE
(LF347)

DUAll. VCO

FLOPPY

10MRAWOSC(H)

500KHZOSC(H)

1MHZVCO(L)

DLQRDDATA(H)

WINNY

(741.5626)

20MHZVCO(L) T

SELFLOPY(H)

270 1 MUX

(748157)

MFM

BIT CELL

2XVCO(L)

— BIT ceu.———»{

2XVCO(H)
2

REFCLK(H)

RDDATA(H)

veooutrutH)[

(1/2745112)

AWINDOW(H)

[

VCOOUTPUT(H)
MR-11200

Figure 2-3

Phase Locked Loop Logic

2-4

2.5

DATA RECOVERY

The data recovery logic (Figure 2-4) consists of two single-bit, edge-triggered, double-buffered registers.
The registers are cross-coupled in order to capture the read data occurring anywhere within either data
framing window. Together with the phase locked loop output, an NRZ read data stream is produced.
2.6

SYNC MARK DETECTOR

The sync mark detector logic (Figure 2-4) provides two functions. One, it detects the sync mark, and, two,
it selects the proper stream from the data recovery llogic Both data recovery bit streams are analyzed to
find the sync mark. Upon detection of the sync mark in either stream, the serlallzer/deserlallzcr logic
receives the desired data stream.

VCOOUTPUT(H)

‘!

RDDATA(H)

(1/2745112)

BWINDOW(H) ?
r

AWINDOWI(H)

“B'" DATA

“A"” DATA

SEPARATOR

(74S74)

2
X

—t—

I—

“"'LS MUX
-

]

<:
>

STATE REGISTEF

LT ]
N

ADRMRKFND(H) l

)

SERLSRCLK(H} —

-,_I

PROM

|
l

I
I

[_twarses]

ols 1MUXO
¥ NRZRDDATA(H)

SERLSRCLK
NGO OUTPUT"

jEpgipipipininpipEn
Ny

AWINDOW

T
r

BNRZDAT W\
MFM

OB po

n
l

ANRZDAT

BNRZDAT

WHEN

WINDOW

R
N

WHEN WINDOW

IS LOCKED TO

)

CELL CENTERS
“ONES"

ADRMRKFND(H)

|
MR-11288

Figure 2-4

Data Recovery and Sync Mark Detector Logic

2-5

2.7

SERIALIZER/DESERIALIZER

The serializer/deserializer is shown in Figure 2-5 and consists of the following four parts.
A double-buffered serial in/parallel out register
A double-buffered parallel in/serial out register
A CRC generator/checker
A high-speed finite state machine controller

The serial in/parallel out (SIPO) logic shifts the serial read data through the CRC generator and forms an
8-bit parallel byte. The byte is buffered for data transfer.
The parallel in/serial out (PISO) logic receives the parallel write data, buffers it, and shifts this data
serially through the CRC generator to the MFM encoder and precomp generator. This serial data becomes
the write data to be sent to the disk.

Both the SIPO and the PISO logic are controlled by the high-speed machine controller.
2.8

MFM ENCODER/PRECOMP GENERATOR

The MFM encoder/precomp generator logic (Figure 2-5) receives the serial data to be written to the disk
and performs the following operations.

It generates a modified frequency modulation (MFM) data bit stream.

It precompensates the MFM bit stream (for both the RD51 disk drive and the RX50 diskette
drive).

It generates the sync mark bit sequence on command.

HIGH SPEED CONTROLLER
A

O
-

W/RBUFFLG (H)

252
'__1

w
g

74157

{

)

§ 2|8
NRZRDATA (H}

W/R BUF FLG
R

z|Z|Ez

LDPISOBUF {H)

pae

¥lel=

g §§§

—

;

’J,

ERROR FLG

r|aclefe

CRCERROR
(H)

(74LS74)

le|e

SER

SIPO

—*P> scLk

HOLDING REGISTER

_—»

Perar HoLo aea
>

ADRMRKFND (H})

LASTWORD (H)

(2x 74L8175)

SER

CRC

1> CLK

(74L5374)

(7aLs164)

(74L5165)

GEN/CHECK

ERR

pser A" owe °0f7]
fi?

NRZDOUT
(H)

LOADREGS (H)

]

500KHZ

STATE REGISTER

[¢]

‘
—

—

(PAL|6R4L‘

—

BIT (74L5161)
COUNTER

OUTPUT DECODER

—1
> 4 BiT PRECOMP

REAL TIME

slslglgl

BITCNTR=8 (H)

1 S

I
I

SHIFTREGS (H)

SELPRECOMPT1 (H)

SELPRECOMPQ (H}
TM
SELFLOPPY (H)

T3y

MFM LOGIC

ENBLBNDRY (L)

MISSING
BIT

|
|

ENBLCENTA

{PALIGLS)

UPSTRMNRZ (H)

MFMPAL

REQADRMRK (H)

—

s c:ac ;ux

-F———————
SHIFT REG

SELCHKWRD (L}

SERLSRCLK (H) |
"

CRCDOUT (H)

PRESETCRC (L)

NEXT STATE LOGIC

SHIFTREGS (H)

PRECOMP LOGIC

0AN
BN
MFMWRT (H)

WRTADRMRK (L)

(PALIGR4)

]

fasisl

2|2

HHHEEREE
ST

IS E B Rl

PRECOMP MUX

{748151)

WRTDATA
{H}

MR-11291

Figure 2-5

Serializer/Deserializer and MFM Encoder/Precomp
Generator Logic

2.9

INTERRUPT VECTOR REGISTER

During an interrupt sequence, the contents of the interrupt vector register (Figure 2-6) are gated to the
QBus to be used as the vector. The MSCP initialization function supplies the T-11 chip on the RQDXI1
controller module with the vector number. The T-11 chip loads this number into the interrupt vector
register.

2.10

SA READ REGISTER, SA WRITE REGISTER, IP REGISTER

The status and address registers (SA) shown in Figure 2-6 are used by the T-11 chip and the QBus
processor for the MSCP port initialization sequence. Both SA registers occupy the same QBus 1/O page
address.

The SA read register is written into by the T-11 chip and read from by the host QBus processor. This
register is used to pass initialization status to the QBus processor.

The SA write register is written into by the QBus processor and read from by the T-11 chip. This register
is used during the initial sequence to pass the MSCP command buffer address and interrupt vector to the
T-11 chip.

The IP register is used to begin the initialization sequence when this register is written into by the QBus
processor. When the host QBus processor reads from the IP register, the RQDXI controller module
initiates a polling routine.

2.11

QBUS TRANSCEIVERS AND HANDSHAKE CONTROLLERS

The RQDX]1 controller module interfaces to the QBus through QBus drivers, QBus receivers, and control
circuits. The control circuits, shown in Figure 2-6, provide the handshake signals necessary to interrupt the
QBus, obtain control of the QBus for DMA, and interface the programmed SA and IP registers to the
QBus.

2-8

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16
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(2x 74L5374)

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16
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SA READ REG

{2 74LS374)

VECTOR REG
A

(2x 74L5374)

(172741L574)

6-C

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CONTROLLER

z|=

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[N
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;

T11 MEMORY MAP

HIGH SPEED CONTROLLER
MA-11369

Figure 2-6

Interrupt Vector Register, SA Registers
and QBus Interface Logic

RQDX1 CONTROL LOGIC

2.12

The supervisory control of the complete RQDX1 controller module is a shared function between the T-11
chip and the main high-speed controller. These two devices share the internal data address bus (DAL bus).
(Refer to Figure 2-1)

The T-11 chip has control over all housekeeping functions that are considered to be slow or those that
require data processing. The T-11 chip is configured into the 16-bit static mode driven by a 7.5 MHz
clock. The T-11 logic, along with the RAM and ROM memories, is shown in Figure 2-7.
HIGH SPEED

CONTROLLER

QBUS CONTROL

T-11 MEMORY MAP

AEEE

256 CSR's

177400

REQT!IDMA(H)

=
2|5

200000

THDMAACKI(L)

Elals == 2|21 5| 3| B

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383

py
=

INTERRUPT REGISTER
PWR UP AND DMA LOGIC

(2 X PAL16LE}

[#]

(74L8373)

3
2

dIZITlSl5ials
]~

o
&

S MUX

(74L5158)

z
z

E
HEE
an|lo|mfja
<1

HEHE

T11 INTERRUPTS

DEVICE 2= P10 IP READ (POLL)

DEVICE 1 = PIO SA WRITE (ADDRESS)
DEVICE 0 = DIAGNOSTIC INTERRUPT

[(2xa4018)

8K X 16
EPROM

(2 x 2764)

\21

2|3

3
-

z
&

2|8|3
S

2 |k&
&z

DEVICE
SELECT

Figure 2-7

177400 W/O

3 = PIO 1P WRITE (INITIALIZE)
DEVICE

2K X 16 RAM
i

W/O
177404
177402 W/O

(741530, PAL16LE 2 x 74L5138)

177412 W/O
177410 w/0

MEMADR<15:00>H

MEMORY DECODE

S
3

177406 W/O

8
D

o
2

SA PIO REGISTER

DRIVE SELECT

000000

(1/2 74L5240)

177420 W/O
177416 W/Q
177414 W/O

(WORD ONLY)

(4 X 74L5163)

LOAD TIMER

177422 W/O

16 BIT

MODE BUFFER

RESET TIMER
FLAG
“GO"
DRIVE CONTROL

040000

RAS(H) | ADDRESS LATCH

177424 W/O

INTERRUPT Q8S
LOAD INT VECTOR |

27128

HHEEE
wigpapa 3

BYTE

177426 W/O

LOAD SYS DISP.

DIAGNOSTIC INT,

AVAIL WITH

RST PARITY FLG

8K
NOT USED

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HIGH SPEED
ONTROL 2R

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T11 (16-BIT STATIC)

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177436 R/O
LOGICAL INE # | 17743480

104000

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NOT USED

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2-10

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MRA.11202

The main high-speed controller controls the high-speed read, write, and DMA functions to or from host
memory. This controller is configured as a microprogrammed multibranch controller operating at 10
MHz. The main high-speed controller architecture is shown in Figure 2-8.

LDGOFLAG(H)

DALO(H)

CONTROL

INPUTS

|
\vam-

GO FLAG
N21

SLock

(1/2 74L574)

GO(H

CONTRCLK(H)

CLR

WATCH DOG

TIMER

FLAG MUX

(H)

(74LS292)

> ADR (74L5251)

MUX1<C:A>(H

7.5 MHZ

j———

' MUXO0<D: A>(H) J

FLAG MUX

ADR

(2 X 74LS251)

SYNCHRONIZER

é::

[a]

(1/2 74574)

S SYNCHRONIZER

NXTSTATE1(H)

(1/2 74574)

EN4AWAY (L)

1.0
S MUX

(74L.S00)

NXTSTATE<9:2>(H)

FLAGO(H)

]

FLAG1(H)

RESETCTL(L)

(9 X AM27535)

N \\9 I'
—

MICROCODE ROM

|
| >>

i
I
I OE
|
: STATE REGISTER : CLR (0w

]

-_—

= = d

e e—m ]

ENDALOUTI(L)

CONTROL

T11BUS

OUTPUTS

Figure 2-8

Main High-Speesd Controller Architecture

MR-11293

The T-11 chip sets up all disk drive control signals, initializes the timer, clears the parity error flag, and
resets the shuffle step oscillator. The T-11 chip then sets up the device control block (DCB) with
parameters for the high-speed controller, initializes the response word with 1s, and then sets the GO flag in
the I/O map. The high-speed controller, upon receipt of the GO signal, requests direct memory access to
the DAL bus from the T-11 chip. Upon receipt of the T1 IDMAACK signal, the controller takes control
of the DAL bus and begins the operation specified in the function code. Upon completion, various
parameters are placed in T-11 RAM, the controller response word is filled in (in the DCB), the GO bit is
cleared, and control is returned to the T-11 chip. All high-speed controller operations must be completed
within 1 second or the timer logic will terminate controller operation.
MEMORY ADDRESS COUNTER/REGISTER

2.13

The memory address counter/register (shown in Figure 2-7) is used to latch the T-11 memory address
during the address phase of the bus cycle. The counter function of the address register is used by the highspeed controller to form a RAM pointer which can be incremented.
2 K X 16 RAM

2.14

As shown in Figure 2-7, the 2 K X 16 RAM is divided into the following three major sections.
e
®

T-11 work space
Device control block
Sector buffer

This RAM can be accessed by both the T-11 chip and the high-speed controller.
2.15

DISK DRIVE CONTROL REGISTER AND STATUS BUFFER

The disk drive control register and status buffer are shown in Figure 2-9. Under T-11 control, the disk
drive control register provides drive selection and head control, including cylinder seeks on the selected
drive. This register also contains static control information for the PLL and serializer. The drive status
buffer is designed to interface the selected drive status to the DAL bus so that it can be interrogated by
either the T-11 chip or the high-speed controller.

2-12

T11 MEM DECODER

L——0 (1dsiVasasan

(N4109

DIAGNOSTIC REG

(7415174}

W[\

aN\

DIAGNOSTIC LED'S

{13sayan

(1)74.10AHAN

DATA RECOVERY

SERIALIZER

CONTROLLER

JV(HO)3LYIOLE.M_EO.E;

(HIVivaLldm

AT?:ZQME[VayAd{H

Lv1SAYANT{1

CONTROLLER

(HILYQYLANIM .

(114708

{H)3gowosvid

DD @

DRIVE STATUS READ

DRIVE SELECT REGISTER

(741.5240, 741.5244)

O~ O’

O——

()a3Ldmexy

(NAqyiay {Aaqy1oay

(7418273, 74F240)

00000

(H)LHONIMI3S Y(1INOHOLOWX (T)e73sAHa

(INOILO3HIa

DATA

rTvyvw

(N)d3ls

SERIALIZER

RECOVERY

TTTOTO

(M)1g71133assaavvaaHn
((Mo13savaH

(IMOVOISAHA

(1)1 40%3 s

(Tloydrymoay
(7()H@I3A1J.OLTd4m1o3xSy

(710 M0ovHL

DRIVE CONTROL REGISTER

(7416, 2x741.S273, 74F240)

TY¥9%%9% T
L

{(M1INvdLi8m (TYAQvay

50 WIRE DISK DRIVE CABLE

Figure 2-9

(NV1ivaiymxy

0O—

t (9638)
O’

{H)LYGHOANIM

é i {26L532)|

(LYQHyIN)4W (NoLvadCw4nw (HIOLYAQHNAW

(HLALYMNAN
(HIOLOLYMNAN
Lvaadindw(M

DAL <15:00> (H})

Disk Drive Control Register and Status Buffer

(10LALYMASN

" {r \ B
MR-11294

2.16

T-11 RAM ADDRESS POINTER AND ALU

The T-11 RAM pointer logic consists of an address counter and an ALU. The high-speed controller logic
loads the beginning and ending T-11 RAM addresses into the registers within the address counter. The
controller then uses these pointers to specify the locations in the T-11 RAM where data is to be transferred
during QBus DMA and disk data transfers. The high-speed controller increments the pointers and
monitors the ALU to determine when the ending address has been reached.
2.17

BIDIRECTIONAL BYTE MULTIPLEXER

The bidirectional byte multiplexer is used to interface the 8-bit input/output of the serializer/deserializer
to the 16-bit RAM via the DAL bus.

During the read operation, the byte multiplexer causes the 8-bit byte from the serializer/deserializer to
appear on both high and low bytes of the 16-bit DAL bus. The high-speed controller can then selectively
write the byte into either the high or low byte section of the 2 K X 16 RAM.

During a write operation, the bidirectional byte multiplexer, again under control of the high-speed
controller, can be used to place the high byte into the low byte position of the DAL bus. The low byte
output of the RAM is disabled at this time.
2.18

8 K x 16 PROM

2.19

QBUS DMA POINTER AND ALU

The 8 K X 16 PROM is used solely to store the T-11 instructions.

The QBus DMA pointer logic consists of an address counter and an ALU. This logic is controlled by the
high-speed controller and is used to hold the QBus address during a DMA process.

This logic is also used as a byte comparator. The high-speed controller utilizes this compare function to
perform sector seek functions during read/write operations.

2-14

CHAPTER 3
CONFIGURATION AND INSTALLATION

3.1
INTRODUCTION
The RQDXI1 controller module must be mounted in the last occupied slot of the backplane due to the
DMA and interrupt structure of the LSI-11 bus. The module’s device address and logical unit number may

be changed by reconfiguring jumpers on the module. Figure 3-1 shows the RQDX1 controller module
jumper and diagnostic LED locations.

D8 D9 D10

fwa (ws

pay

NOTES:

R
o

. ADDRESS SELECTION (A12 THROUGH A2) AND
LOGICAL UNIT NUMBER SELECTION (LUN7 THROUGH
LUNO) IS MADE BY ATTACHING TWO POSITION
JUMPER CLIPS (PART NO. 12-18783-00). THIS
ELIMINATES THE NEED TO WIRE WRAP JUMPERS
ONTO THE ADDRESS OR LOGICAL UNIT NUMBER

STAKES.
JUMPERS W1 AND W2 ARE IN FOR Q/Q AND Q22/Q22
MACHINES AND ARE OUT FOR Q/CD AND Q22/CD
MACHINES, THEY PROVIDE GRANT CONTINUITY.
MR-99156

Figure 3-1

RQDX1 Controller Module Jumper and LED Locations

3-1

3.2

DEVICE ADDRESS SELECTION

The location of the RQDX]1 controller module address jumpers is shown in Figure 3-1. Table 3-1 lists the
jumper configuration for the standard module address (772150). To configure the module for an address
other than 772150, use the format shown in Figure 3-2 to determine the appropriate jumper configuration.
RQDX1 Standard Address Jumper Configuration

Table 3-1

Jumper

State

Out

A3
A4
AS
Ab
A7
A8
A9
AlO
All
Al2

In
Out
In
In

Out
Out
Out
In
Out
In

Address selection (772150)

aANK
SELEoT
FOR 18-BIT
v

ADDRESSING
~

BANK SELECT 7 FOR

22.BIT ADDRESSING

1
J

I
1
0

A12

A11

A10

Y 1 A0

A
A6

BUS ADDRESS JUMPERS

CONNECT TWO POSITION JUMPER CLIPS (PART NO. 12-18783-00)
TO DECODE
A 1.

NO CONNECTION DECODES A 0.
*FACTORY
CONFIGURATION
MR-11287

Figure 3-2

RQDXI1 Address Selection Jumper Format

3-2

3.3

LOGICAL UNIT NUMBER SELECTION

The location of the RQDXI1 controller module logical unit number jumpers is shown in Figure 3-1. These

jumpers are set to the lowest logical unit number assigned to any disk/diskette drive controlled by the
module. The controller module automatically sizes the logical unit configuration during initialization to
determine how many (of the four possible units) are actually present. This automatic sizing eliminates the
need for reconfiguration of jumpers when units (RD51 or RX50 drives) are added to or removed from the
controller module. The standard configuration for the logical unit number jumpers (selecting logical unit
number 0) is listed in Table 3-2. To configure the module for logical unit numbers beginning with other
than unit number O, use the format shown in Figure 3-3 to determine the appropriate jumper
configuration.

Table 3-2

RQDXI1 Standard Logical Unit Number Jumper Configuration

Jumper

State

LUNI1

Out

LUN2

Out

LUN3

Out

LUN4

Out

LUNS

Out

LUNG6

Out

LUN7

Out

LUNS

Out

Logical unit number (0)*

This indicates that logical unit numbers 0--3 are assigned to this controller module.

The controller will automatically determine if less than four logical units are present.

LUN
JUMPER

LOGICAL
UNITS
SPECIFIED

3235

6 |

2831

2427

"4 |2023

1619

2 [1215

ol
a7
ONLY ONE JUMPER IS
INSTALLED AT ANY
TIME
ALL JUMPERS REMOVED
SPECIFIES LOGICAL
UNITSO0-3
MR-11286

Figure 3-3

RQDXI1 Logical Unit Number Jumper Format

3-3

3.4

INTERRUPT VECTOR

3.5

INTERRUPT REQUEST LEVEL

3.6

RQDX1 CONTROLLER MODULE INSTALLATION

The interrupt vector has a range of 0 to 774 and is software selectable. (A vector selected by software
must be greater than 0.) The normal interrupt vector used by the RQDX1 controller module is 154.
The RQDX1 controller module interrupts at priority level 4 determined by E3, a DC003 chip.

The RQDX!1 module (M8639) is typically installed in the last occupied slot of the backplane. If empty
slots are left between the other modules and the M8639 module, install grant cards (part number G7272)
in those empty slots to accommodate the interrupt and direct memory access structure of the backplane.
Before installing the module, make sure that the address and logical unit number jumpers are properly
configured.

Install the 50-conductor signal cable (part number BC02D-1D) to the J1 connector on the M8639 module.
This cable must be connected to a signal distribution panel that will connect the appropriate signals to the
RDS51 and/or RXS50 drives. An example of the MICRO/PDP-11 signal distribution panel connecting the
M8639 module to an RD51 disk drive and an RX50 diskette drive is shown in Figure 3-4. The RDS51 disk
drive requires two signal cable connections. One is a 20-conductor cable (part number 17-00282-00), the
other is a 34-conductor cable (part number 17-00286-00). The RX50 diskette drive requires a single 34conductor signal cable (part number 17-00285-02).

BA23

DISTRIBUTION

'IT

BOARD

FRONT PANEL

Q-BUS

RX50

RQDX1
M8639

MR-11286

Figure 3-4

RQDXI1 MICRO/PDP-11 Signal Distribution Connections

3.7 RQDXI1-E EXTENDER MODULE OPTION
Typically (in the MICRO/PDP-11), the RQDX1 controller module is located in the same mounting box as
the disk and/or diskette drives that it controls. However, if the system mounting box cannot accommodate
all of these drives, the optional RQDX1-E extender module may be used to connect the RQDX1 controller
module signals to any drive that is external from the system mounting box.

3-4

WA —

o0
@ XIDTM

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No iy

‘..U:U(_

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SS0000080
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3.7.1
RQDX1-E Extender Module Jumper Configuration
As shown in Figure 3-5, the RQDXI1-E extender module is a dual-height module that provides signal
connectors and requires appropriate jumper configurations. The J2 connector receives signals from the
RQDXI1 controller module. The other connectors (J1 and J3) distribute these signals to the disk and
diskette drives. Jumper functions for the RQDX1-E extender module, as well as the jumpers installed in
the factory configuration, are listed in Table 3-3.

-1

MR-11677

Figure 3-5

Table 3-3

RQDXI-E Extender Module Jumper Locations

RQDX1-E Extender Module Jumper Configuration

Factory
Configuration*

Jumpers

Functions

W1 through W4

Must be installed
(Manufacturing use only)

JRDI1 through JRD3

Select the external drive
to be connected to the J3

JD2 to JRD2

connector

JD3 to JRD3

Determine which connector
(J2 or J3) the RD
read/write will connect to

JA1 to JCI

JD1 through JD3
JRX1 through JRX3
JB1 through JB8
JA1 through JAS8

JC1 through JC8

W1 through W4

JD1 to JRD1

JA2 to JC2
JA3 to JB3

JA4 to JB4

JAS to JBS
JA6 to JB6
JA7 to JC7
JAS8 to JC8
*

Factory configuration is set to connect an external RDS1 disk drive to connector J3. To configure the module for an external
RX50 (conncected to J3), jumpers JD1 through JD3 are connected to JRX1 through JRX3, jumpers JA1 through JA8 are
connected to JBI through JBS.

3.5

NOTE

Jumper selection (for configurations listed in Table
3-3) is made by attaching two-position jumper clips

(part number 12-18783-00).

3.7.2

RQDXI1-E Extender Module Installation

Figure 3-6 shows the installation of the RQDX1-E extender module option in the MICRO/PDP-11 system
(BA23 mounting box). The M7512 dual-height module is installed in the backplane slot directly below the
M8639 (RQDX1) module, in connectors A and B. A cable (part number BC02D-0K) connects the
RQDX!1 controller module to the RQDXI1-E extender module through the J2 connector. Another cable
(part number 70-18652-01) attached to the J3 connector connects the RQDX1-E extender module to a
mounting plate (part number 74-2866-01) that is mounted to the system’s patch and filter panel assembly.
(The entire cable and mounting plate assembly may be ordered as part number 70-20691-01.) This
external plate provides the signals to be sent to the external drive. A third cable (part number BC02D-1D
— attached to the J1 connector on the RQDX1-E extender module) is connected to the signal distribution
panel in the mounting box, providing signals to the disk or diskette drives that are installed in the system
mounting box.

BA23

'1;“3

DISTRIBUTION
BOARD

FRONT PANEL.
Q-BUS

RX50

i
=

PLATE*

RQDX1

M8639

MQUNTING

"’)l
-

*MOUNTING PLATE INSTALLED IN SYSTEM
PATCH AND FILTER PANEL ASSEMBLY
MR-11295

Figure 3-6

RQDXI1-E Extender Module Connections

CHAPTER 4
REGISTERS AND COMMANDS

4.1

INTRODUCTION

The RQDXI1 controller module contains two registers that can be accessed by a QBus address. A number
of other registers reside on the module, but these are accessible only to the T-11 logic within the module.
The module uses mass storage control protocol (MSCP) to communicate with the host QBus processor.
Detailed information regarding MSCP is available in the UDAS0O Programmer’s Documentation Kit

(document number QP-905-GZ).
4.2
REGISTERS
The programmable registers contained on the RQDX1 controller module are the initialize and poll register
(IP) and the status and address register (SA).
These registers can be addressed like any memory location.
4.2.1

Initialize and Poll Register (IP)

The initialize and poll register (IP) has a standard LSI-11 bus address of 772150. This address is

determined by the address selection jumpers on the RQDX1 module. (Refer to Paragraph 3.2 for jumper
selection information.)
The host begins the initialization sequence by either issuing a bus initialize or by using the IP initialize
operation. The IP register is not an actual register, but is simply a circuit that checks for a write operation

at the IP address. Any write to that address will cause an initialize operation to take place.
4.2.2 Status and Address Register (SA)
The status and address register (SA) has a standard LSI-11 bus address of 772152. This address is

determined by the address selection jumpers on the RQDX1 module.
The SA register consists of a set of two registers, the SA read register and the SA write register. These are

named according to their function in relation to the QBus host processor.
The SA read register is written into by the RQDX1 module’s T-11 and read from by the QBus. This
register is used to pass initialization status to the QBus processor.
The SA write register is written into by the QBus processor and read from by the T-11. This register is
used during the initialization process to pass the mass storage control protocol (MSCP) command buffer

address and interrupt vector to the T-11 chip.

4.3

MASS STORAGE CONTROL PROTOCOL (MSCP)

Mass storage control protocol (MSCP) is the message-oriented set of rules by which the RQDX1 controller
module communicates with the host system. MSCP provides the protocol that allows the host to send a
command message and the controller module to send a response message. The host designates an area of
memory to be used as a communications area, and provides the location of this area to the controller
module. The size of the communications area is variable and is determined by the host software. Its
organization is shown in Figure 4-1. For additional information regarding MSCP, refer to the UDASO
Programmer’s Documentation Kit (document number QP-905-GZ).

4—-—16-BIT WORD———»
LOWER

ADDRESS | COMMAND INTERRUPT WORD
RESPONSE INTERRUPT WORD
-

TWO WORD
BUFFER DESCRIPTOR
RESPONSE

" RING

TWO

= 0s
MSBs

| COMMAND
RING

HIGHEST
ADDRESS

)
MR-10588

Figure 4-1

Memory “Communications Area” Organization

4-2

4.3.1
MSCP Commands
Table 4-1 lists MSCP commands and their functions that are supported by the RQDX1 controller module.

MSCP Commands
Command

Function

Access

Reads data from the specified unit.

Abort

Guarantees that referenced MSCP command will complete within the controller timeout period.

Available

If specified unit is on-line, returns it to the unit-available state. If specified unit is currently in the unit-available state, this command is essentially a no-operation.
(The RQDX1 cannot spin down a unit.)

Compare Host Data

Reads data from the disk and compares it with the data
in the host buffer.

Erase

Writes zeros to the specified logical blocks on the unit.
(No data is accessed from the host.)

Get Command Status

Reports on the status of a specified command by
number that reflects the command’s

returning a
progress.

Get Unit Status

Reports on the status of a specified unit.

On Line

Places the specified unit on line, if possible.

Read

Reads data starting from the specified logical block on
the disk into host memory.

Set Controller Characteristics

Sets host-settable controller characteristics.

Set Unit Characteristics

Sets host-settable unit characteristics.

Write

Writes data starting at the specified logical block on
the disk from the host memory.

4-3

4.3.2

MSCP Status Codes

The RQDX1 controller module provides MSCP status code response messages listed in Table 4-2.

Table 4-2

MSCP Status Code Messages

Message

Meaning

Command Aborted

The current command was aborted before it could be

Compare Error

While performing a Compare command, a discrepancy
was found while comparing the disk data to the host

completed normally.

data.

Controller Error

The RQDXI1 controller module detected an internal
error, but is able to continue processing its outstanding
commands.

Data Error

Data could not be read or written due to CRC errors,
“header not found”, or due to a sector being read
whose forced error bit was set.

Drive Error

Media Format Error

Host Buffer Access Error

A drive-related error was detected (such as a seek
failure).

Indicates the the media mounted on the unit was incor-

rectly formatted.

Reports bus timeouts and parity errors during data
transfers. (Applies only to the data portion of an MSCP
command.)

Invalid Command

The RQDXI1 controller module found some field in the

Success

The command was successfully completed.

Unit Available

The RQDXI1 controller module is not on line, but it can
accept an On Line command from the host.

Unit Offline

The RQDX! controller module is not on line, and it

Write Protected

A write or erase command was attempted to a unit that
is either physically or logically write-protected.

command to be in error.

cannot be brought on line.

4.4 DIAGNOSTICS AND UTILITIES PROTOCOL (DUP)
The diagnostics and utilities protocol (DUP) provides a diagnostic mode of communication between the
host QBus processor program and the diagnostic and utilities server task (DUST). This protocol allows the
host program to request that the DUST load a diagnostic or utility program and execute it. Some
diagnostic programs access the diagnostic blocks on the RDS51 disk. This allows the diagnostic to test
reading/writing on the disk without accessing or affecting customer software.
During execution of the diagnostic or utility program, the host program can make inquiries to the DUST
about the progress of the program being executed, or abort the program if there are unexpected results.

The diagnostic and utility programs executed by DUP commands (see Table 4-3) may require the host
program to specify certain parameters (such as starting host buffer addresses, byte count, block count,
etc.).
For additional information regarding DUP, refer to the UDASO Programmer’s Documentation Kit
(document number QP-905-GZ).

Table 4-3

DUP Programs

Program

Function

Write DBN (RD51 only)

Writes and transfers a diagnostic block with a data.
pattern.

Read DBN (RD51 only)
Format (RD51 only)

Reads a diagnostic block.
Formats the entire disk, verifies the disk, and implements bad block revectoring.

Read Sector (RD51 or RX50)

Reads a physical sector. The data is not transferred to
the host, but drive problems will be detected.

Restore (RD51 or RX50)

Moves the read/write head of the drive to the home

position.

Self Test

Verifies that certain RQDX1 controller module logic is
functioning properly. Self Test results are reported in
the diagnostic LEDs (refer to Paragraph 5.2). Self Test
is always executed on power up or Bus INIT.

4.4.1
DUP Commands
The following commands are available to DUP and are supported by the RQDX1 controller module.

Get DUST Status
Execute Supplied Program
Execute Local Program (Diagnostic or Utility)
Send Data
Receive Data
Abort Program

4-5

DUP Responses

4.4.2

The following responses are available to DUP and are supported by the RQDXI1 controller module.
®

Success

[llegal Command

In the case of an Execute Supplied Program command, the following responses are also available.
e
e

No Region Available
No Region Suitable

In the case of an Execute Local Program command, the following responses are also available.
No Region Available
No Region Suitable
Program Not Known
Load Failure
Standalone

CHAPTER 5
ERROR DETECTION

5.1
INTRODUCTION
Each time that the RQDX1 controller module is powered up, the module executes a selftest that verifies
the operation of the T-11 chip and the ROM and RAM memory chips. Successful completion of the
selftest takes approximately five seconds. The RQDX1 controller module provides a set of four diagnostic
LEDs that display a code corresponding to the functional block of the selftest currently being executed or
the type of failure that occurred. The diagnostic LIEDs and error codes are described in Paragraph 5.2.
Diagnostic programs determine whether or not the RQDX1 controller module, the RD51 disk drive,
and/or the RX50 diskette drive are working properly. If they are not, they isolate the failing component.
Diagnostic programs are used exclusively for maintenance purposes and play no part in normal system
operation. The programs are provided on the XXDP+ diagnostic software system available from Digital
Equipment Corporation. The diagnostic programs that test the RQDX1 controller module, the RD51 disk
drive, and the RX50 diskette drive are described in Paragraph 5.3.

5.2
DIAGNOSTIC LED ERROR DISPLAYS
The diagnostic LEDs provided on the RQDX1 controller module indicate faults during the selftest. On
power up, all of the LEDs are lit and then immediately cleared as the RQDX1 module enters the selftest.
The LED:s indicate (in a binary sequence) the functional block of the selftest or the type of failure that has
occurred. All four LEDs are off after successful completion of the selftest. Figure 5-1 shows the diagnostic
LED locations on the RQDX1 module. Table 5-1 lists the diagnostic LED codes and the corresponding
failure description.

D10

]

NNNN

In
MR-11284

Figure 5-1

Diagnostic LED Locations

5-1

Table 5-1

Display

MSD

LSD

Diagnostic LED Error Displays

D9
Bit 2

D8
Bit 1

D7
Bit 0

Type of Error

Off

No error

Off

T-11 failure

Off

T-11 2942 failure

Off

QBus 2942 failure

Off

Serializer deserializer failure

Off

CRC failure

Off

Microcode version

Off

Diagnostic interrupt failure

Off

Shuffle oscillator failure

Off

RQDX1 ROM checksum

Off

RQDX1 RAM failure

Off

Undefined

Off

Undefined

Off

Undefined

Off

Undefined

LED
Octal

D10
Bit 3

5-2

Exit from selftest

failure

Power up of the RQDX1 or

reception of Bus INIT

5.3
DIAGNOSTIC SOFTWARE
The XXDP+ diagnostic software system provides the diagnostic programs necessary

controller module, as well as any RD51 disk drives and/or RX50 diskette drives

to test the RQDX1
that are connected to the

RQDX1. Table 5-2 lists the appropriate XXDP+ diagnostic programs and the
testing function performed
by each program. The individual program listings may be used to further isolate
component failures.

Table 5-2

XXDP+ Diagnostic Programs

XXDP+ Program Name

Title

ZRQA?.BIN*
ZRQB”?.BIN

RDRX Performance Exerciser
RDRX Formattery

* 77 indicates any revision of the program.
T This program formats the RD51 disk. The procedure is described in Paragraph
6.2.2.

5-3

CHAPTER 6
DISK DRIVES

6.1

INTRODUCTION

The RQDXI1 controller module is used to interface an RD51 disk drive(s) and/or an RX50 diskette
drive(s) to the extended LSI-11 bus.

The RDS51 disk drive is a random access storage device which uses two nonremovable 133.4 mm (5.25
inch) disks as storage media. The total formatted capacity of the RD51 disk drive is 11 megabytes.
The RX50 diskette drive is a random access dual diskette storage device which uses two single-sided 133.4
mm (5.25 inch) RX50K diskettes. The total drive capacity is 800 K bytes of formatted data.

6.2
RDS1 DISK DRIVE
The RD51 disk drive, shown in Figure 6-1, is a field replaceable unit (FRU) that is installed in a system

mounting box. The RD51 drive is connected to the controller module (via the distribution panel) by two
signal cables (J1 and J2). A third cable (J3) provides power supply connections to the RD51 drive. The
connector pin assignments for each of the three cables is provided in Appendix C.

MR-9408

Figure 6-1

RDS5I1 Disk Drive

The RDS51 disk drive capacity is 11 megabytes on two nonremovable 133.4 mm (5.25 inch) disks. Each
disk surface uses one movable head to service 306 data tracks. The head and disk technology used allows
the heads, which normally fly over the disk surface, to land when the drive is powered off. This
technology, termed Winchester, utilizes lubricated media and lightly loaded read/write heads.

High bit densities on the media are achieved by flying the heads at a height of 20 microinches. This flying
height requires a clean air environment which is achieved by manufacturing and sealing the head and disk
assembly (HDA) in a clean room environment.

6-1

6.2.1

RDS51 Disk Drive Installation

Installation of the RD51 disk drive requires proper configuration of the dual in-line package (DIP) shunt
jumper pack located on the RD51 read/write printed circuit board. Location of the shunt is shown in
Figure 6-2. The proper jumper configuration (required for the RD51 drive to be used with the RQDXI

controller module) is listed in Table 6-1.

]
\

—
MR- 9539

Figure 6-2

RD51 Disk Drive Read/Write Printed Circuit Board

Table 6-1
Pin
Numbers

Pin
Connection

1 to 16

Not used*

2to 15
3to 14
4to13
Sto 12
6toll
7 to 10
8t09

In
In

DIP Shunt Jumper Configuration

In
Out
In
Out
Out

The 14-pin DIP jumper pack is offset into a 16-pin socket toward the contact pins on the read/write printed circuit board. If
the DIP shunt (jumpers) need to be replaced, a new DIP shunt can be ordered (part number 29-24115).
NOTE

Any replacement RD51 disk drive must be formatted
using the ZRQB??.BIN program to be compatible
with the RQDX1 controller module. (Refer to Paragraph 6.2.2 for the formatting procedure.)
WARNING

When sliding the RD51 disk drive in or out of a
system chassis, do not hold the drive by its front
right side. Doing so will cause the head positioner
flag to rotate, resulting in damage to the drive. Figure 6-3 shows the head positioner flag location on
the disk drive.

6-2

HEAD POS|TIONER FLAG

MR- 10835

Figure 6-3

RDS51 Disk Drive Head Positioner Flag

6.2.2
Formatting the RD51 Disk Drive
The ZRQB?? (any revision) program, provided by the XXDP+ diagnostic
software system, is used to
format the RD51 disk drive. The procedure for formatting is as follows.

In response to the XXDP+ . (period) prompt, type R ZRQB”?
.R ZRQB?? <CR>

(The question marks will allow any revision of the program to be used.) A response
appears on the console terminal.

similar to the following

DRSDO
RDRX -X-X

(where -X-X is the current revision information)
RD51 DISK FORMATTER
UNIT IS RQDX1 DISK DRIVE SUBSYSTEM
RSTRT ADR AAAAAA (where AAAAAA specifies a restart address)
DR>

You must respond to this prompt with a command to run the program. For
DR>START

example:

(default will cause the program to run one pass)

You are then asked the following.

CHANGE HW (L) ? N
CHANGE SW (L) ? N
ENTER UNIT TO BE FORMATTED (D) ? X

(where X is the unit number assigned to the drive
to be formatted)

USE EXISTING BAD BLOCK INFORMATION (L) N ? N
USE DOWN LINE LOAD (L) N? N
CONTINUE IF BAD BLOCK INFORMATION IS INACCURATE (L)
ENTER 8 CHARACTER SERIAL NUMBER (A) ?

6-3

N? Y

The 8-character serial number is a unique serial number assigned to each RD51 disk drive. It is labeled on
the left side of the disk drive (refer to Figure 6-4).

MR-11296

Figure 6-4

RDS51 Serial Number Label Location

ENTER DATE IN MM-DD-YY FORMAT (A) ?

As shown above, the current date should be entered.

The format routine takes approximately 11 minutes to complete, and its successful completion results in a
message similar to the following.

FORMAT COMPLETED, X REVECTORED LBNS

RDRX EOP 1
0 TOTAL ERRS

The RQDX1 controller module automatically revectors any bad sectors and prints the total number of
revectored sectors in the format completed message. The maximum number of sectors that will be
revectored is 144.

If the formatting process is not successful, an error message appears on the terminal. Refer to the
individual program listing to use this message (if necessary) to isolate the failure or to determine which
FRU to replace.

6.3

RX50 DISKETTE DRIVE

The RX50 diskette drive is shown in Figure 6-5. The RX50 diskette drive is a field replaceable unit (FRU)
that is installed in a system mounting box. One cable connects the RX50 to the RQDX1 controller module
(via the distribution panel), another cable connects the drive to the power supply. There are no field
alignment procedures for the RX50 diskette drive, since it is adjusted and aligned at the time of
manufacture.

6-4

MR-9632

Figure 6-5

RXS50 Diskette Drive

The RX350 diskette drive is a random access, dual-diskette storage device. It has two access doors and slots

for diskette insertion and removal. An active drive light for each diskette slot informs you when that drive
is busy. The RX50 diskette drive capacity is 800 K bytes of formatted data on two single-sided diskettes.
This is accomplished by utilizing a 133.4 mm (5.25 inch) RX50K diskette that contains 80 tracks, 10
sectors per track, and 512 bytes per sector of modified frequency modulation (MFM) data. The average
access time, including latency, is 264 ms.

6-5

APPENDIX A

RQDX1 CONTROLLER MODULE BACKPLANE PIN ASSIGNMENTS

A b3

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R
2
3
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e
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:
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/W.oOO.NMV,HMWH&M\WOHPM/Afl/.wq\5N/W\oo.u\fl.nlfixwmnonm\lmxofiWAWV\W;\!UPy< Lfilvy

Digital Equipment Corporation’s plug-in modules, including the RQDX1 controller module, all use the
same contact (pin) identification system. Figure Aby
v. Q < w—

43 SRA2L}E )S,== < who=% YNK, =5 <S 3=

u-zg2Q5S3 ,—o.nf%b=,Olv0q_o,/w5urml”f\yhlMDof.Ow0mloHflnu.Wo/egSo—3=RBS=z>VT~SoD

quad -height module. Each connector contains 36 lines (18 lines on each side of the printed circuit board).
Table A-1 lists the backplane pin assignments for the RQDX1 controller module.

N
N
O

COMPONENT SIDE

Figure A-1

./ g A\ g AN g wV AN +\

—

Quad Module Contact Finger Identification

Table A-1

RQDX1 Controller Module Backplane Pin Assignments

Signal Name

AAL
ABI
ACI
ADI
AE]l
AF1

(BIRQS L)
(BIRQ6 L)
BDALI16 L
BDAL17 L
(SSPAREI or +5B)
(SSPARE2)
(SSPARE3)
GND
(MSPAREA)
(MSPAREB)
GND
BDMR L
(BHALT L)

AA2
AB2
AC2
AD2
AE2
AF2
AH?2
AJ2
AK?2
AL2
AM?2
AN2
AP2

+5V
(—12V)
GND
(+12V)
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
BIRQ4 L
BIAKI L
BIAKO L
BBS7 L

(+5B)

AV?2

BDALI1 L

AHI1
AJl
AKI
ALl

AMI
ANI
APl
ARI1
AS]
ATI
AUl

AVI

BREF L
(+12B or +5B)
GND
(PSPAREL)

AR2
AS2
AT2
AU2

BA1
BBI

(BDCOK H)
BPOK H

BA?2
BB2

BK1

(MSPAREB)

BK?2

BClI
BDI
BEI1
BF1
BH1
BJ1

BL1
BM1
BNI1
BPI
BR1
BSI
BT1
BUI
BVI

BDALI8 L
BDALI9 L
BDAL20 L
BDAL21 L
(SSPAREDS)
GND

(MSPAREB)
GND
BSACK L
(BIRQ7 L)
(BEVNT L)
(+12B)
GND
(PSPARE?2)
+5V

BC2
BD2
BE2
BF2
BH2
BJ2

BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

BDMGI L
BDMGO L
BINIT L
BDALO L

+5V
(—12V)
GND
+12V
BDAL2 L
BDAL3 L
BDAL4 L
BDALS L
BDALG6 L
BDAL7 L
BDALS L
BDAL9 L
BDALI0 L
BDALI11 L
BDALI12 L
BDALI3 L
BDAL14 L
BDALIS L

Table A-1

RQDX1 Controller Module Backplane Pin Assignments (Cont)

Signal Name

CAl
CBI
CCl
CDI
CEl
CFl1
CHI1
CJl
CKl1
CLI1
CMI
CNI
CPI
CRI1
CS1
CTI
CUlI
CV]

(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)
GND
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)

CA2
CB2
CC2

+5V
(Unused)
GND

DAI

DBI
DCl1
DDI
DEI
DF1
DHI
DJ1
DK 1
DLI
DM1
DNI1
DPI
DRI1
DSI1
DTI
DU
DVI

CD2

(Unused)

CE2

(Unused)

CF2

(Unused)

CH2
CJ2

(Unused)
(Unused)

CK2

(Unused)

CL2
CM2

(Unused)
CIAKI L

CN2
CP2
CR2
CS2
CT2
Cu2
CV2

CIAKO L
(Unused)
CDMGI L
CDMGO L
(Unused)
(Unused)
(Unused)

(Unused)

DA2

+5V

(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)
GND
(Unused)
(Unused)
(Unused)
(Unused)
GND
(Unused)
(Unused)

DB2
DC2
DD2
DE2
DF2
DH2
DJ2
DK?2
DL2
DM2
DN2
DP2
DR2
DS2
DT2
DU2
DV2

(Unused)
GND
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)

APPENDIX B
RQDX1 CONTROLLER MODULE CABLE SIGNALS

Table B-1 lists the RQDX1 controller module signals on the J1 connector.

MFMWRTDT1 (H) (RD51 only signal)
MFMWRTDT1 (L) (RD51 only signal)
GROUND
HEAD SEL 2 (L) (RDXX only signal)*
GROUND
SEEKCPLT (L) (RD51 only signal)
RD1 RDY (H) (RD51 only signal)
WRT FAULT (L)
DRVBUSOE (L)
HEAD SEL 1 (L) (RD51 only signal)
RXOWPTLED (L) (RX50 only signal)

OO ~INWL

Signal Name

bW —_ O

J1 Pin
OOV
W
-—

J1 Connector Signals

p—t

Table B-1

20
21

22
23

24
25
26
27
28
29

RDO RDY (H) (RD51 only signal)
RX1TWPTLED (L) (RX50 only signal)

DRVSLOACK (L) (RD51 only signal)
MFMRDDATO (H) (RD51 only signal)
MFMRDDATO (L) (RD51 only signal)
MFMWRTDTO (H) (RD51 only signal)
MFMWRTDTO (L) (RD51 only signal)
MFMRDDAT1 (H) (RDS1 only signal)
MFMRDDAT1 (L) (RDS51 only signal)
GROUND
REDUCWRTI (L)
RDOWRTPRO (L) (RD51 only signal)
DRV SEL 4 (L)
GROUND
INDEX (L)
RDIWRTPRO (L) (RD51 only signal)
DRV SEL 1 (L)
DRV SEL 2 (L)

* Reserved for future use.

B-1

Table B-1

J1 Connector Signals (Cont)

J1 Pin

Signal Name

30
31
32

DRV SEL 3 (L)
RX2WPTLED (L) (RX50 only signal)
RXMOTORON (L) (RX50 only signal)

33
34
35
36
37

GROUND
DIRECTION (L)
GROUND
STEP (L)
GROUND

GROUND

RXWRTDATA (L) (RX50 only signal)

WRT GATE (L)

GROUND

42
43
44

TRACK 00 (L)
RX3WPTLED (L) (RX50 only signal)
DRVSLIACK (L) (RD51 only signal)

GROUND

READ DATA (L) (RX50 only signal)

GROUND

HEAD SEL 0 (L)

GROUND

READY (L)

* Reserved for future use.

APPENDIX C
DISK DRIVE CABLE CONNECTOR PIN ASSIGNMENTS

C.1
RDS51 DISK DRIVE CONNECTOR PIN ASSIGNMENTS
The connector pin assignments for the RD51 disk drive signal and
power cables are listed in Tables C-1
through C-3.

Table C-1

RD51 Disk Drive J1 Signal Connector Pin Assignments

GND Return
Pin

Signal

Name

Reserved

5
7

Head Select 2
Write Gate

Seek Complete

Track O

Write Fault

Head Select 0
Reserved (to J2 pin 7)
Head Select 1

Ready

Step

Drive Select 1
Drive Select 2

Index

Drive Select 3
Drive Select 4
Direction In

C-1

RD51 Disk Drive J2 Signal Connector Pin Assignments

Table C-2

GND Return
Pin

Signal
Pin

Signal
Name

2
4
6

]
3
5

Drive Selected
Reserved
Reserved

Reserved (to J1 pin 16)

Reserved

9,10

GND

+MFM Write Data
—MFM Write Data
GND
+MFM Read Data
—MFM Read Data

13
14
15
17
18

RDS51 Disk Drive J3 Power Connector Pin Assignments

Table C-3

GND Return
Pin

Signal
Pin

Signal
Name

2
3

1
4

+12 'V
+5V

C-2

C.2
RXS50 DISKETTE DRIVE CONNECTOR PIN ASSIGNMENT
S
The connector pin assignments for the RX50 diskette drive signal
and power cables are listed in Tables C4 and C-5.

Table C-4
GND Return

RXS50 Diskette Drive J1 Connector Pin Assignments
Signal

Signal

Name

7
9

Reserved

Drive Select 3 L

Index L

Drive Select 0 L

TKA43L (controls write current level)

Drive Select 1 L
Drive Select 2 L

Motor On L
Direction (head movement direction)

Step L (head movement distance)

Write Data L
Write Gate L

Track O L

Write Protect L

Reserved

Ready L

Table C-5

Read Data L

RXS50 Diskette Drive J3 Power Connector Pin
GND Return

Signal

Name

+12 'V

+5V

C-3

Assignments

Digital Equipment Corporation e Bedford, MA 01730