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Document:	RLV12 Disk Controller User's Guide
Order Number:	EK-RLV12-UG
Revision:	001
Pages:	53
Original Filename:

OCR Text

User’s Guide

CORLVI2

Disk Controller

User’s Guide

'Prepcred by Educational Services
of

Digital Equipment Corporation

Ist Edition, July 1981

The material in this manual is for informationa
l purposes and is subject to change without
notice.

Digital Equipment Corporation assumes
no responsibility for any errors which may appear in this
manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECse

t-8000 computerized

typesetting system.

The following are frademarks of Digital Equipment
Corporation:
DIGITAL

DECsystem-10

DEC

DECSYSTEM-20

PDP

DIBOL

DECUS

EduSystem

UNIBUS

VAX

DECLAB

VMS

MASSBUS
OMNIBUS

0S/8
RSTS

RSX
IAS
MINC-11

W55

CONTENTS
CHAPTER 1

INTRODUCTION
DESCRIPTION
e
e
e
ee
FEATURES <ot
SPECIFICATIONS ..o
ee

REVI2 Disk Controller ..o et
RLOT/RLO2 DisSK DFIVES....uviiiiie
e iieeeeeee
e

INTRODUCGTION ..ottt
ettt eee e
BUS PROTOQCOL ..ttt
BUS TRANSCEIVERS ..o et
PROGRAMMABLE REGISTERS .....oooiiiiicee
e
Bus Address Register (BAR) .....oooievevooiieeeeeeeeenne e e
Bus Address Extension Register (BAE) .....o.cooiiiiiiiieeeieeeeeeeeeeeeeeeeeee
e
Disk Address Register (DAR) ..o..ovcviieieeceeeceecceeeeee
e
Control/Status Register (CSR) ....ooooviii
e
iiieeeeeeee
eeneea
Multipurpose Register (MPR) ....occooiiimieieeiceccc
ee
ee
FIFO Memory, FIFO Serializer and Word Difference Counter...................

E-1
I-1

I-1
E-1
I-3

2-1
2-3
2-4
2-4
2-5

2-5
2-5

2-7
2-8
2-9

DATA SOURCE MULTIPLEXER AND CRC GENERATOR .....ccooeovveeenn. 2-10

MICROSEQUENCER, CONTROL STORE PROMS,
AND BUFFER REGISTER .....c.ooiiii
e, et
2.6.1

re e

ener s 2-10

2.8

Buffer Register Fields.......coooveiiriiiiiiiiiiieceeeeeee
e, SU 2-11
Fatal Error Clearing LOZIC ....ccoovrvieviiiiciieieecc
e cceeeeneeeeeeee et
cevnenenee. 2711
CONTROL REGISTERS AND PULSE GENERATORS ...coovvioiieiieeeeeenn. 2-12
WRITE ENCODER AND PRECOMPENSATION LOGIC .....ooooviiiiiioccene. 2-12

2.9

DATA SEPARATOR READ CIRCUIT .cocviiiieeeeeceeeeeeeeeeeeee e 2-15

2.6.2
2.7

INTRODUCGTION ...ttt ettt
ettt
s
ee
3-1
DEVICE ADDRESS SELECTION ..ot 3-1
BUS SELECTION ..ottt
se e aa
3-1
INTERRUPT VECTOR ..ottt
3-1
INTERRUPT REQUEST LEVEL ..oooriiie
e s 31
MEMORY PARITY ERROR ABORT FEATURE.......cooooiieieeeeecceeein, 3-4
JUMPERS THAT REMAIN INSTALLED ..ottt 3-4
INSTALLATION ettt
et e en e ene e
3-5
ACCEPTANCE TESTING ..ottt
3-5

CHAPTER 4

REGISTERS

4.1

INTRODUCGCTION ettt —
CONTROL/STATUS REGISTER (CSR).ceiiiiieciiteeeeeeeeeeeeeeee
e
BUS ADDRESS REGISTER (BAR) ..o, e
DISK ADDRESS REGISTER (DAR) ..evieeeeeeeeeeeeeeeeeeeeee
et

4-1
4-1
4-1
4-4

DAR During a Seek Command.......c..oeeceuivreevieiiiiieeeieiiecceee
e e
DAR During a Read, Write, or Write Check Command .........cccoovvveeeeeenen...
DAR During a Get Status Command......... e
e
et e e st re e ne

4-4
4-4

e AT

WwW LWL
ww

CHAPTER 3

4.2

4.3

4.4
4.4.1
4.4.2
4.4.3

4-4

CONTENTS (Cont)
o
I -

B
o i o in

MULTIPURPOSE REGISTER (MPR) oo
Writing the MPR 1o Set the Word Countu ..o

Reading the MPR After a Read Header Command ..o,ereeenen
Reading the MPR After a Get Status Command.....oooinne

BUS ADDRESS EXTENSION REGISTER (BAE) i 4-7

CHAPTER 5

COMMANDS

s nssa s aan s
e e e s b e e s st e e s et
t
ettt e s e e e
INT RO DU CTION et

eiss
t
ereec
e
et eieee
GET STATUS (2) cotioeeeieieeee
steseasees
R b
s e s e s et eeeee
e aenaes seeies
SEEK (3) 1ot etieueeteeteeee

i~ ==

—ooo

——— e

Y R

st
READ HEADER (4) ettt
s st an s sassas s st
s
sesse
et
esenes
e
eeieetee
WRITE DATA (5) cooeeiiieeie et
e
eete
st
eete
st
eetr
et
eiee
eeiieses
e
READ DATA (6) ceeeoeei

o Nl=

DN
=

CHAPTER 6

e
READ WITHOUT HEADER CHECK (7) cooiviiiii
iie
e
iiiiin
iinss
e
ieaeei
uriett
(0)..n
ON
MAINTENANCE FUNCTI
t
.
.
.
NDS
COMMA
EXAMPLES OF USING
s
SEEK OPETALION 1ueeeeiriiireeinie ettt

Data Transfer OPEration ...t
ERROR RECOVERY ..ttt eseteaeeeireee s s inss e s ssn e et seiia s s an s s s nsees
DISK DRIVE

INTRODUGCTION

ettt

USER SWITCHES AND INDICATORS. ...

110/220 VOLTAGE AND NORMAL/LOW VOLTAGE

t
s st
tt
RANGE SETTING .ost

TABLES

11§

Duvmun
b b h H N

Title

Control/Status Register Bits ...t
Address Selection......c.o.ceeeen. et eatterseeeeeresessaesevesesessesenstseansreenenesectiestrrranatearien
nsee
s s rssranransnns
trasees
senrtrnasat
eeaeesr
b saseasaaaasessst
CSR WOTA FOTTNAL .eeeeieeeeeeeeieeeeeeee

DAR Seek Command Word FOrmat........oooveriiirimnnnaseeeeeemnnnn

DAR Read/Write Data Command Word Format.........ccinn.,
e
DAR Get Status Command Word FOrmat ...

asoes
iiar
sranasasatras
oiiie
s s sessassstaass
iiiii
e aerntisesreaa
MPR Word Count FOPMAL ...oouuiii
st
amen
s
e
e
eessncssies
ecemriri et
MPR S1atus WoOrd FOTMal. oo
Controller Status EITOrS ..o i
e s se s s e
ite e e ittt
Disk Drive STALUS EITOS oottt
o
.
Voltage and Range Selector SELHNE .

FIGURES

e — OO0~
e e

¢
N

AL
b

bbb DD

NN DB WN =

B WN

R A

R WL WL N NN

B WY —

|lx\)£|\)t?')[?)l|\)tl\)ryt|\)ll\)tc\)

Title

Page

RLVI2 Block DIagram cocoooooiiii
e
e
e
BUuS Protocol LOZIC cviiii e
e, s

BUS TraNSCEIVETS woiiiiiiii

Bus Address Register (BAR) Circuit.

e ettt

oo ioioeeeoeeieeeeeeeee e SOUSRUR
Bus Address Extension Register (BAE) CIrCUit cueee oo e

Disk Address Register (DAR) CIrCUit e oot

Control/Status Register (CSR) CIrCUIL. v ieee oo,
FIFO RAM. Buffers, and Serializer.......ooocoooiiiicioe oo,

2-2

2-3
2-4
2-5
2-6
2-6
2-7

2-9
Microsequencer., Control Store PROMs, and Buffer Register.
oo ieeeeecvienn 2-10
MEM ERCOING..ottt 2-12
Peak Shift Wavelorm. oo e 2-13
Write Encoder and Precompensation Circuit .o.....ocooovviieoceieeeiee e 2-14
Data Separator Read CIFCUI ...t
eeee e 2-15
RLVIE2 Jumper LOCAUIONS ciiveit ittt
3-3
RLVI2 Device Address FOrmMat. ...t
3-4
RLVI2 Interrupt Vector FOrMat..ooooooiiiiiiiiis
e
3-4
RLEVI2 Installation ..o, ereer e,
3-6
Control/Status Register (CSR) .ooviviiviieeeee e, ettt
ae s
4-3
Bus Address Register (BAR) oo
4-3
DAR During a Seek Command ..o
e
e 4-5
DAR Durmo a Read, Write, or Write Data COMMANGe e 45
DAR Durmg a Get Status Command....c.ooooiieii oo 4-6
Writing the MPR to Set the Word Count...
U UPRUUPUUNUUPPUPRT - &
Reading the MPR After a Read Header Command
'
(Three Header Words) .o oo
e, e
4-7
Reading the MPR After a Get Status Command ......o..ooveieoreeeereeeeeeeeereeeeeeeeens 4-7
BAE Register Word FOrmat ......ocooiiiiiiiiii

e
RLOT/RLO2 Disk Drive (Front VIEW) ....ouueie oo
eees e

4-8

e e eee e

6-3

RLOTI/RLO2 Disk Drive (Rear VIEW) .....coouii
itiiiie
eeeeieeee e

6-1

CHAPTER 1
INTRODUCTION
1.1
DESCRIPTION
The RLV12 Disk Controller interfaces RLO1 and RLO02 disk drives to any quad- or hex-size backplane
that uses a 16-, 18-, or 22-bit LSI-11 bus. One RLVI2 controls up to four disk drives. The RLV12

~consists of one quad-size module (M8061), a BC80M cable, a drive terminator, and drive identification
hardware.
The RLOI and RLO2 disk drives are random-access, mass-storage, subsystems that store data in fixedlength blocks on a preformatted disk cartridge. Each RLO! can store 5.24 million bytes, and cach R1.02

can store 10.48 million bytes. The drives are 26.67 c¢m (10.5 in) high, self-cooled, rack-mountable units
and come complete with a power supply. Option RLV12-AK includes one RLOI drive, and option
RLV22-AK includes one RLO2 drive.
-

The RLVI2 transfers data to and from the LSI-11 bus using direct memory access (DMA) transactions. This allows data transfers to occur without first going to the processor.
1.2
FEATURES
The RLV12 controller has the following features.

Single quad-size module; needs no C-D connections.
Supports DMA data transfers in 16-, 18-, or 22-bit addressing modes.
Software compatible with RLV11 controller (16- or 18-bit mode only).
Supports 22-bit addressing on an LSI-11 bus.
Controls from one to four RLO1/RL02 drives.
,
Memory parity error abort feature for use with memories that have a parity option.
1.3
1.3.1

SPECIFICATIONS
RLV12 Disk Controller

~ Module
Size

1 quad-size module, M8061

Height: 26.56 cm (10.457 in)
Width: 1.27 cra (0.5 in)

Length: 22.70 cm: (8.94 in)
Power Requirements

+5 Vdc +

5% at 5.0 A
+12 Vdc + 5% at 0.1 A

Bus Loads

ac bus loads

dc bus load

Addressing Modes

16-, 18-, and 22-bit (determined by user)

Minimum Configuration
- for 22-Bit Address Mode

H9275-A or similar backplane that supports 22-bit addressing, and
memory capable of 22-bit addresses, such as the MSVI11-L or the
MSV11-P.

Limitations

The RLV12 will not fit in the dual-height LSI-11 mini-series H9281

Drives per Controller

Up to four RLO1 and RLO2 drives in any combination

LSI-11 Bus-Addressable

8 (5 are used; 3 are not used)

backplane.

Registers

Base Device Address

Device Interrupt Vector
Data Transfer Rates

Selected by jumpers as follows.
Addressing Mode

Base Devi‘ce Address

16-bit
18-bit
22-bit

174400g
774400g
17774400g

0001603, jumper sclectable

4.9 ps/word (avg) drive to controller, controller to memory
3.9 us/word (peak) drive to controller
2.0 us/word (peak) controller to memory

Error Detection Capability

Cyclic redundancy check (CRC) on data and héaders
Memory parity error abort for use with memories that have parity
checking

Maximum Cable Length
Controller to Last Drive

30 m (100 ft)

Environment Specifications
Temperature

Storage
Operating*

—40° C to 66° C (—40° F to 150° F)
5° Cto 60° C (41° F to 110° F)

Relative Humidity
Storage
Operating

10% to 90%, noncondensing
10% to 90%, noncondensing

Altitude

Not operating
Operating*

9 km (5.6 mi) max
2.4 km (1.5 mi) max

Airflow

Operating

Max temperature rise across module must not exceed 10° C
(18° F) input to output.

*Reduce the maximum operating temperature by 1.8° C for each 1000 m altitude above sca level or 1° F for cach 1000 ft
above sea level.

1-2

1.3.2

RLO1/RLO2 Disk Drives

Storage Type

Medium

Magnetic disk cartridge

Recording Surfaces

2 data surfaces

Magnetic heads

Recording Capacity (formatted)

Cylinders per cartridge
Tracks per cylinder
Tracks per cartridge
Sectors per track
Bytes per sector

Bytes per track
Bytes per cylinder
Bytes per cartridge

Recording Method

2 read/write heads

RLO1

RILO2

256
2
512
- 40
256
10,240
20,480
524 M

512
2
1024
40
256

10,240
20,480
10.48 M

Modified frequency modulation (MFM)

Performance

Transfer Rate

40-sector (16-bit data words):
4.9 us/word (avg) drive to controller, controller to memory
3.9 us/word (peak) drive to controller

Head Positioning Time

55 ms (avg)
17 ms (one track)
100 ms (max)

Revolution Latency

12.5 ms (avg)

Operating Environment
Temperature Range
Relative Humidity
Wet Bulb Temperature
Altitude
Heat Dissipation

10° C to 40° C (50° F to 104° F) at sea level
10% to 90%, noncondensing

28° C (82° F) max

Up to 2400 m (8000 ft) at max temperature of 36° C (96° F)
150 W (546 Btu/hr)

Operation
Start Time
Stop Time

Revolutions per Minute

50 s
30 s
2400

Power

Drive

Single-phase

Starting Current

5 A (rms) max, 120 V, 47/63 Hz
2.5 A (rms) max, 240 V, 47/63 Hz

Mechanical Drive

48 cm wide X 63.4 cm deep X 27 cm high (19 in wide X 25 in

Size

deep X 10.5 in high)

Weight

33.75 kg (75 1b)

Mounting

The drive mounts on slides in a standard 48.26 cm (19 in) cabinet
(provided). Recommended max height from floor is 18.9 cm (43
in).

Embedded servo

Cartridge

Top loading cartridge with 2 data surfaces.

Standard Cable Lengths
Power cord

2.74 m (9 ft)

Controller to First Drive

1.83 m (6 ft)

Drive to Drive

3.05 m (10 ft)

Optional Drive Cables

Cable

Part No.

Length

BC20J-20
BC20J-40
BC20J-60

7012122-20
7012122-40
7012122-60

6 m (20 ft)
12 m (40 ft)
18 m (60 ft)

NOTE

Total length of cable(s) from controller to the last
drive must not exceed 30 m (100 ft).

CHAPTER 2

'FUNCTIONAL DESCRIPTION

2.1
INTRODUCTION
The RLV12 controller interfaces the RLO1 and RLO2 disk drives to a 16-, 18-, or 22-bit LSI-I1 bus.
One RLVI2 can support up to four RLO1 and RLO2 disk drives in any combination. The RLVI12 module, M8061, has the LSI-11 bus transceivers and decoders, programmable registers, the controller timing and sequence logic, and the data formatting circuits necessary to read and write on the disk.

The main sections of the RLV12 are shown in Figure 2-1. The RLV12 has the following five programmable registers.

Control/status register (CSR)
Bus address register (BAR)
Disk address register (DAR)
Multipurpose register (MPR)
Bus address extension register (BAE) (22-bit addressing only)

These registers can be addressed like any memory location. The CSR is always written last of these five
registers because it starts the microsequencer operation.

An RLV12 program can select16-, 18-, or 22-bit LSI-11 bus addressing. When not cnabled for 22-bit
addressing, the module is software compatible with and can replace the RLVI1 or RLV2I.

To issue a command to the RLV12, the processor [irst places the address of the register on the LSI-11
" bus. Then it places the data on the bus. The RLV12 controller decodes the address and channels the
data to the correct register. The processor loads the bus address register (BAR) with bits O through 15.
If 18- or 22-bit addressing is used, the processor also loads the bus address extension register (BAE)
with bits 16 through 21. Bits 16 and 17 may also be written to or read from the control/status register
(CSR). The CSR is loaded in the same way.

Once the command is written into the control/status register, the RLV12 starts a microsequencer routine. The microsequencer decodes the command and branches to an address in the control store
PROMs. There the microsequencer finds a routine for the command issued. The microsequencer then
generates the control signals needed to channel the data through the controller.
Included on the controller are error detection features, such as the memory parity error abort feature
for use with memories that have parity error checking. When reading system memory, data bits 16 and
17 from the bus are checked for a parity error. If an error is detected, the current command to the
controller is aborted.

Cyclic redundancy checking (CRC) is used to check the serial data integrity from the disk drive. A
CRC check word is created from the data being sent to the disk and this check word is written immediately following the data. When a header or data field is read from the disk, the incoming bit stream and
CRC check word are checked for errors. If an error is detected, a header CRC or a data CRC error
flag is set in the CSR.

2-1

16—, 18—, OR 22-8BIT

LSi—11 BUS

[

EDAL

MEMORY

SOAL|

eamiTY erROR

171

ABORT

ORT

DRIVE ERRCR
NXM

LOG!

Logic

PARERR

NXM

1ERROR

LoGiC

” DR ERR

DRIVE READY

A
CSR

ERROR

BUS
PHOTOCOL

| TROTOCOL

S51LLECTION
A

HoL

CONTROL

BAE

BUS

EXTENSION

(WRITE ONLY)

DISK

TRANSCEIVERS

ADDRESS

AND

DAR

ADDRESS

DA 15:00

FIFO

ZEROBIT

FIFO

INPUT

BUFEER

TS FIFQ 15:00
1

FIFO

DATA IN

SERIAL—

DR CMD
MO

CMb
[.E
}

DS CLK

g2 MHZ

STATUS

CLK

WR DATA PLS

READ CIRCUIT

(PHASE LOCK LOOP)

1ZER

W OATA_

FSMS CLK (MAINT)

DATA
SEPARATOR
/

STATUS IN

MS CLK
CLOCK[——*

IMUX

CLKSEL

MUX SEL—

DS DATA

PELSATION

WRITE MARKER BIT

SER

[mux oaTa b | MRITE ENCODER]

MS CLK

55 DATA | MULTIPLEXER

OUTPUT

DATA

SER DATA OUT,| SOURCE

SYS0 1

SEND DRIVE COMMAND

SER DA

SHIFT

Gvs CLK

CRC
-

lsvstw

B2 M1

MS CLK~—]

GENERATOR

Lad

BUS

ClL K SEL

_— CHC CHLCKER [

BAR | ApDRESS/
WO fwonrp COUNT

BUFFER

tFIEQ CONTROL,

CRCER .

BUS

@
u

DECODER

|MUX SEL

DATA PATH CONTROL

WRITE
CHECK

JADDRESS

cLock

AB.C. AND D PULSE

AND MUX SELTCT)

WR GATE

Sverem |B2MHZ

GLNERATORS,

LOGIC

WRITE GATE

CONTROL KEGISTERS

WH PR

lrd

t51-11 BUS

INTERRUPT

L ot TeompAnt

BUFFER REGISTERS

HDR |SEARCH
A

HNF

lomsect

STATUS FLAGS

comp RSLT

DL/

—

DRSELO

MICROSEQUENCER

DATA LATE

ZERO L
FUNCTION CMDS

INT EN (IE)

DR ROY

DRIVE SELECTO
DRIVE SELECT 1

SET OPI—+py

O NPR—>

DRIVE
|O
] BUS

FATAL ERR H

RD DATA

_ RD DATA
STAT

ATUS

MAINT
READ STATUS

FIFO RAM -

256 X 16

WORD
CNTUP

spoK

POWER
oK

Fovsci

DIFFERENCE }— WD FOUR (RD NPR)

COUNTER

{ON TRANSFER TO RAM )

CNT DN
'
(ON TRANSFER FROM RAM)

rox

PR FAIL
:

DISK DRIVE BUS |_|

BUFFER

TRANSCEIVERS

Figurec 2-1

RLV12 Block Diagram

The RLV12 has a 256 X 16-bit RAM 1o store data for or from direct memory access (DMA) transactions. The RAM is a first-in, first-out (FIFO) memory that can store up to 256 words of data.
During a write command, a FIFO serializer is used with the FIFO RAM to convert parallel data into
serial format to be written on the disk. During a read command, the FIFO serializer converts the serial
data into parallel data to be loaded into the FIFO RAM.
'
2.2

BUS PROTOCOL

The bus protocol logic (Figure 2-2) generates the control signals to read from or write to the controller.
This logic uses a DC004 as a bus protocol chip. Two negative logic decoders and one positive logic
decoder provide the read and write signals to the five RLV12 registers: CSR, BAR, DAR, MPR, and
BAE. The following events occur.

At addressing time,

R SYNC H clocks in the address bits (TSDAL 1, 2 and 3). Thesc ad-

dress bits are decoded to read or write to the five registers.

The DCO004 generates a slave reply signal, SRPLY H, that becomes BRPLY L to the processor and completes the LSI-11 bus protocol.

ENADD
L
EN DAT L

TO BUS

TRANSCEIVERS

XMITH

WRITE

FROM

gTHEEEE*

D-TYPE

BUS

Eltg’g,s

5 DAL
3

DECODER

REGISTERS

O-

TS DAL
2 —

REG SEL
B

TS DAL 1—

REG SEL
A

REGISTERS

O~ WR CSR L

O WR BAR L

RD DAR L

(O—WR DARL

RD MPR L

O— WR MPR
L

Ol RD BAE L

O—WRBAEL

SEL

[Tor

~
|}

——O

L —— WR CSR PLS H

}—WwRBARPLSH

L~ WR DAR PLS H

—— WR MPR PLS
H
|

SEL

—

WR BAE PLS H

SEL

RD BAR L

RDIN L——0

R SYNC H=——] CLK

pecoper

RD CSR L

REGSEL C

READTO

DATA

DEVSEL L

R DOUT L-O)

\
WR PLS H

SEL

BRPLY [O

ouT Lepy-ouTLeL
N WD

DCO04

MRPLY L——CLK

SDEVENH

—NWD L

STE

-MASTER H

eowRT Mo
H—
DSKWRT

_ BRPLY L

TO LSi-11 BUS

—

)

MRPLY H—L___/

RECH

I‘g ANSCE}
Bussce VERS

SINGLE RANK
SYNCHRONIZER
MA 5738

Figure 2-2

Bus Protocol Logic

H——] D

¢ RDY

SRPLY H

the slave device (the
A single rank synchronizer monitors controller ready (CRDY))esto enable
S DEV EN H.

addressed register). MRPLY L clocks in CRDY and generat

4 When CRDY is asserted, the RLV12 is ready to accept another command.

The signals XMIT H and REC H go to the DCO005 transceivers that interface the LSI-11 bus

and the 16-bit three-state DAL bus.

2.3 BUS TRANSCEIVERS
2-3. These transceivers transmit The bus transceivers on the RLV12 are DC003s, as shown in FigureLSI-11
BDAL 0-15 H signals and
and receive both data and address information. They interface the asserted
during address time to
the RLV12 TS DAL 0-15 H bus/address signals. BBS7 L must be
enable the transceivers. The transceivers are controlled by the signals XMIT H and REC H from the
.

bus protocol logic.

interrupt vector of the
The jumper pins connected to the transceivers select the device address and the
B
RLVI12.

DCo05

DCO05

IN/OUT

L | TO/FROM

IN/OUT

&-ESQEE—STATE

\ TS DAL 8, 9, 10, 15

TS DAL 1114

]

BDAL 8104 —

BBS7 L —O

_E—o

TO/FROM

-144
Lsi-11 gus BPAL 11

TO WIRE

WRAP PINS

ESS

ADDRESS

TOWIRE

WRAPR PINS

"RD BAE H—

—— MATCH H

[—

L MATCHH

-—

__]

VEETOR

XMIT H —

REC H —

Figure 2-3

2.4

—— TO OTHER DCO05

BUS TRANSCEIVERS

Bus Transceivers

PROGRAMMABLE REGISTERS

ate bus (TS DAL BUS). These
The five programmable registers of the RLV12 interface to a three-st
registers receive address, data, and control information, via the bus, and they return data and status
information on the same bus.

2.4

2.4.1
Bus Address Register (BAR)
The BAR (Figure 2-4) has two DCQ06 binary counte

to which the first word of a DMA transfer is to

load this address.

WR BAR L———

rs. The BAR is loaded with the 16-bit bus addres
s
be made. The signal WR BAR L enables the registe
r to

‘
~— SEL BAR

RD BAR L—

BUS ADDRESS REGISTER

e 19

DCO06

DUAL/

BIN

COUNTER

‘

——]MAX-CH

L—OX

—OX

—CX RD
-MAX A CRY L.—COX CLK-A
WR MPR L

-MAX C CRY L‘o

CLK-C

.— MAX A CRY H

—C RD

—— MAX C CRY H

W_;—-—-—-—o

CLK-A

“‘0“""—"'()

CLK-C

SEL MPR L_O S-C
_

BINITL

S-C

_
!
:

—— \WC OF LW

‘

~SRPLY L O

WC BAR LD

R DOUT L —C)

OVER
FLOW

WC BARCLK L -(D*—J

K
MR 5740

Figure 2-4

Bus Address Register (BAR) Circuit

2.4.2
Bus Address Extension Register (BAE)
The BAE (Figure 2-5) is a 6-bit register for the extende

‘
d address bits, 16 through 21. For 22-bit addressing, the BAE is loaded from TS DAL 0-5 using a
write BAE command.

For 18-bit addressing, the extended address bits 16 and
17 can be loaded either into BAE bits 0 and 1 or
into CSR bits 4 and 5.
NOTE
|
Writing CSR bits 4 and 5 modifies BAE bits 0 and 1

and vice versa.

2.4.3
Disk Address Register (DAR)
:
:
o
The DAR (Figure 2-6) holds the next sector address to read
or write data on the disk. After each sector
is read or written, the contents of the DAR is incremented
by 1. The output of the DAR goes to the
DAR secrializer.
During a Seek command, the DAR is used for the head selected
, the direction to travel, and the cylinder address difference. During a Read, Write, or Write Check
command, the DAR is used for the head
selected, the next sector address to read or write, and the cylinder
address. During a Get Status command, the DAR is used to get the drive status and to clear
the drive error register of soft errors.

The DAR scrializer has two 8-bit shift registers that load parallel
DAR scrializer sends the data to the header compare circuit.

2-5

data in and shift serial data out. The

BixN CNTR

TSDALS — D

21X H
— BAE

TSDAL4 —{ D

- BAE 20X H

TSDAL3 —{D

- BAE 19X H

TSDAL2 —D

18 X H
- BAE

RD BAE L O} OD
_
LOAD

BIN

CNTR

WR BAE L —O{

BAE
RSLT M

—

P
BAE
YR
WRBAEPLSH|

TSDAL1TH

MUX

BAE 17X H

BAE 16X H

TS DAL
OH

TSDAL4 — 0
WR CSR L

TSDALO —} 1

RD BAE L
LOAD

TSDALS — 0
TSDAL1

—

WR BAE L

— CLK

~WR CSRH —| 1SEL

WR BAE PLS H —
WR CSR PLS H
MAX-A H —
MR 53741

Bus Address Extension Register (BAE) Circuit

Figure 2-5

{1 0F 2)

{1 OF 4)

FROM

THREE-STATE

BUS

SHIFT
REGISTER

BINARY
COUNTER

TS DAL 0-15 H

INC DAR H

H
WR DAR PLS

DAR

SERIALIZER

DAO=15 H

DAR

RDDARL

o op

—DASHIFTL ~ SHET LD

WRDARL

| gaD

MS CLK H
MARKER H

CLK

SER DA ENH

SER DA H

CLK
_

ySERDAINH LY NIt
MR 5742

Figure 2-6

Disk Address Register (DAR) Circuit

2-6

2.4.4

Control/Status Register (CSR)

The CSR (Figure 2-7) is a holding register for the command to the microsequencer. The register also
holds the interrupt enable bit, the controller ready signal, the drive sclect bits, and error flags. A command to read the CSR gets status information as shown in Table 2-1.

I ; TS DAL
O

TS DAL1 H

FROM

THREE~

STATE

BUS

CSR

IE H

TSDAL2H
TSDAL3H

Fl
F2H

TSDALGH,

—

]

DR
DR
SEL 1 HH

———="]

TS DAL B

CLK
TS DAL T7H

wreshpisH|

WATCH

T0
THREE—
PARERRL

TIMER

—

.
|
oPl

STATE

l=cRovH [
_

DOG

\Ts DAL3

CRDY H

F/F

TS DAL 1

TS DAL 2

DR SEL O H

TS DAL9 H

PLS R0OPIRl
H
LS

FO H

BUS

OPIH

TS DAL 10
LS(
:

D/HCRCH

"\ TS DAL 11

DLT/HNF H|

\ TS DAL 12

R DAL 16X H|

R DAL 17X H|

DATA FROM
LSt-11 BUS

M25

WR CSR L
3

| _L——°2g"24 AN
FiE

_(?

550 MS

~
EN ADD H s

|
enapD L[,

NXM

(LPAR ERR L
|

NXMH

:
TS DAL 13

NXM |

L O| one

SHOT

10uS

ERR H

RD CSR L

‘\\TS DAL 15

57423

Figure 2-7 Control/Status Register (CSR) Circuit
When set by the hardware, the controller ready flip-flop indicates that the RLV12 is ready to accept a

command. The CRDY bitin the CSRis cleared by software. After this bitis clear, the firmware-gener—
ated signal PLS OPI H starts the OPIl watchdog timer.

The watchdog timer allows 550 ms for the controller to complete an instruction. The timer prevents the
controller from taking too much time to perform an instruction and keeping out other instructions. If
the instruction is not complete within 550 ms, the timer clocks the OPI flip-flop, enabling OPI H, which
turns off the controller.

2.7

Some of the CSR status.error signals have two meanings depending on the state of the OPI flip-flop.
When the D/H CRC flag is set without OPI H set, a data CRC error occurred with OPl H set, a
header CRC error occurred.

When the DLT/HNF flag is set without OPl H sct a data late error occurred; with OPI H set, a
header not found error occurred

During a DMA transfer, the NXM one-shot allows 10 us for-the addressed memory location to send and
return BRPLY L. This one-shot prevents the RLV12 from indefinitely holding the LSI-11 bus. If the
one-shot times out, it clocks the NXM flip-flop, setting NXM H, and releascs the LSI-11 bus.
If NXM H is set without OPI H set, a nonexistent memory error occurred. If NXM H is set with OPI
H set, a memory parity error occurred. (A memory parity error forces both the NXM flip-flop and the

OPI flip-flop set.)

Any error that occurs also sets status bit 15.
Table 2-1

CSR Bit(s)

1-3
4,5

6
7
8.9
10
11

10, 11

12
10. 12
13
10. 13
14
15

Control/Status Register Bits

Status Information

Drive recady (DRDY)

Command function code (FO, F1, F2)
Extended address bits 16 and 17 (DAL 16-17)
Interrupt enable (IE)
Controller ready (CRDY)
Drive selected (DS)
Operation incomplete (OPI)
Data CRC error (DCRC)

Header CRC error (HCRC)

Data late (DLT)
Header not found (HNF)
Nonexistent memory (NXM)
Parity error abort (PAR ERR)
Drive error (DE)
Error flag (ERR)

Multipurpose Register (MPR)

2.4.5

The MPR has three functions and uses different circuits dcpcndmg on the command being performed.
I.

Word Count Register — During a Read Data or Write Data command, the MPR functions as
a word count (WC) register and uses the same circuit as the bus address register, shownin
Figure 2-4. Before either commandis issued, the number of words to be transferred (the word
count)is written into the MPR. The words transferred go through one of the FIFO buffers to
the FIFO memory (see Paragraph 2.4. 6) At the end of each sector read or written, the word
count is incremented. When the count is complete, the word count overflow (MAX-C H in
Figure 2-4) clocks the word count flip-flop and ends the data transfer.

Status Register — Following a Get Status command, the MPR functions as a status register.

The controller places the disk status information in the FIFO output buffer, shown in Figure
2-8. The disk status word from the selected drive is placed in this buffer and can be read by
reading the MPR. (See Paragraph 4.5.3.)

2-8

Memory Buffer Register — Following a Read Hcader conumand, the MPR functions as a
memory buffer register. The controller places the three header words in the FIFO memory.
in the FIFO output buffer. To read
Recading the MPR places the header words, one at a time,
the three header words requires three successive read MPR instructions. (Sce Paragraph

4.5.2.)

2.4.6

FIFO Memory, FIFO Serializer, and Word Difference Counter

The FIFO memory is a first-in, first-out 256 X 16-bit RAM that can store up to 256 data words. A
FIFO serializer takes serial data from the disk, makes it parallel, and places it in the FIFO memory.
The FIFO scrializer also takes parallel data out of the FIFO memory, makes it serial, and sends it to
the disk. See Figure 2-8.

A word difference counter keeps track of the number of words coming from the disk to the FIFO buffer. After four words are read from the disk, the word difference counter signals the microsequencer to
:

start a DMA transaction.

RD FIFO EN L

RD MPE L
DMPH LG

ADDRESS

ATOR

GENER-

CLKC

RAMADDD? H> (256 X 16-81T WORDS) —1¢ | ADDR
DECODER |
|

{}

SELAPTH

CLK A

INC B PT H

FIFO RAM

TSFIFO0-15H

FROM

D PULSE
GENERATORS

FIFO INPUT
BUFFER

FIFO OUTPUT
BUFFER

A PT H—
INC
'

F/F

TSFIFO0-15H

D-TYPE}

D-TYPE

A——

N FIE

TS DAL 0-15H

TS FIFO 0—15H|

THREE-STATE BUS

RD MPR H

H
EN DAT

RD MPR OUT L ~few ouT

RDMPRIN L ~en ouT|

Hi - o
AMPR CLK OUT

T DINH

CLK

DISK STATUS IN H

H
~RD STATUS

FROM DATA DS DATA H

SEPARATOR

SER DATA IN H

[

FIFO

ISZ"?SF"AL" ,

TS FIFO 0—15 H

—2

'
ODD/EVEN DATA.

(SER DATA OUT)

TO DATA SOURCE

MULTIPLEXER

MR 5744

Figure 28 FIFO RAM. Buffers, and Serializer

RD STATUS H

FROM CONTROL

2.5

AND CRC GENERATOR
DATA SOURCE MULTIPLEXER

Data that is to be written on the disk goes to a data source multiplexer (see Figure 2-1). MUX SEL 0,
1, and 2 determine which of the follewing inputs reaches the multiplexer output.
Source

Serial Input

SER DA (disk address)
SER DATA OUT
DS DATA

DAR (disk address register)
FIFO serializer
Data separator

CRC checker/generator

CRC

The multiplexer’s serial output, MUX DATA H, goes to the write encoder precompensation circuit to
be written on the disk. At the same time, a CRC check word is being created by the CRC checker/generator. This check word is then added to the end of the data field of the sector.
When the header or sector is read from the disk, the data is again sent through the CRC checker/generator. Any errors in the data or in the CRC word are detected, and a data CRC (DCRC) or a
header CRC (HCRC) error bit is set in the control/status register.

2.6 MICROSEQUENCER, CONTROL STORE PROMS, AND BUFFER REGISTER
The microsequencer decodes the function commands of the CSR and points to an address in the control
store PROMs, where the routine resides, to exccute the command. The microsequencer sends an address (PR ADD 0-9 H) to the control store PROMs. (See Figure 2-9.)

A Micro

SEQUENCER

50 H —| DIRECT IN

- CONTROL

S1H——] SEL STACK

STORE

-INSTR 3 L —O{ PUP
FE L —Ol EN

CRDY H

LD CTRL B
|

PROMS

CNTRL

f-——*LDCTRLC

[PR OUT 0-23

PRADD0-9 X

BUFFER

»LDCTRLA

CONST
NST
011

RE L—IREG EN

AND PULSE D

GENERATORS

{ T MUX SEL 0-2

ZERO L
DEV SEL H

INSTR 04

T MUX SEL

— RE L

CQONDITIONAL

W.ELAG L

BRANCH
LOGIC

— FE L

SOH

|—S1H

SEL

—*
STATUS —TM
FLAGS

STATUS

FLAG
MUX

DUAL

RANK
SYNC

TFLAG X L
)

___
——p

MF-5746

Figure 2-9

Microsequencer, Control Store PROMs, and Buffer Register

2-10

The control store PROMs receive the address from the microsequencer and generate a 24-bit microinstruction at the outputs (PR OUT 0-23 H). The PROM outputs go to a buffer register, which is
hdlhadbadi
dhae

divided into five fields as follows.
Instruction field
T MUX SEL ficld

T FLAG X L (test flag don’t care)
.
Constant ficld
LD CTRL register field

Buffer Register Fields

2.6.1

The instruction ficld signals (INSTR 0, 1, 2 and 4) go to the conditional branch multiplexer to provide
the microsequencer with the next address to access. These instruction signals generate the select inputs
(SO H and S1 H) and the enable inputs (FE L and RE L) to the microsequencer. INSTR 3 goes
directly to the push/pop input of the microsequencer.

The T MUX SEL field signals select one of the status flags to enable the instruction from the conditional branch multiplexer. One of the status flags that go to the status flag multiplexer is cnabled to
pass to the dual-rank synchronizer. The status flag becomes T FLAG L and goes to the select input of
the conditional branch multiplexer selecting the instruction field signals from the buffer register.

The T FLAG X L signal from the control store buffer register allows the microcode to branch on a
specific flag as follows.

WhenTFLAG X L is low, the instruction in the instruction field is executed unconditionally.

(The state of T FLAG L is a don’t care condition.)

When a status flag appears on the dual-rank synchronizer, it asserts T FLAG L. If at the

same time T FLAG X L is high (unasserted), the microsequencer conditionally executes the
instruction in the instruction field.

Ifboth T FLAG X L and T FLAG L are high, the microsequencer skips to the next instruc- |

tion in the control store PROMs.

The constant field has two purposes. 1t provides a direct input to the microsequencer, and it provides
inputs to load one of three control registers (A, B, and C) and the two D-pulse generators. (See Paragraph 2.7.)

When loading a control register or pulse generator, the signals LD CTRL A, B, or C are decoded to

determine which register or pulse generator to load.
2.6.2

Fatal Error Clearing Logic

If a fatal pulse occurs it halts the clock on the RLV12 and sets CRDY H. CRDY H generates ZERO
L, which resets the microsequencer to location. zero, where it stays until the controller is restarted
(CRDY is cleared). When the controller is accessed, DEV SEL H clocks and initializes the micro-

sequencer

2.7

CONTROL REGISTERS AND PULSE GENERATORS

The control signals for the RLV12 logic, such as clock sclection, FIFO control, and data path control,
come from three control registers (A. B, and C) and two D-pulsc generators. These registers and Dpulse generators are loaded from the constant ficld of the microsequencer’s control store buffer. They
|

provide the following functions.

Two D-pulse generators, one positive and onc negative, provide pulses for clearing, in:

crementing, and decrementing the logic.

28 WRITE ENCODER AND PRECOMPENSATION LOGIC ~

The write encoder converts binary data into modified frequency modulated (MFM) data, which is re.

corded on a disk.

MFM is a magnetic recording method for disk drives, in which a clock signal is encoded in the flux

transitions recorded on the disk. When reading data from the disk, one can synchronize on the data
transitions, and with a phase-locked loop and MFM decoder, recover the clock and data.
Each bit cell (Figure 2-10) can have a transition at its beginning or at its center or may have no transition at all. Each 1 produces a transition at the center of the bit cell time; a 0 preceded by a 1 produces
no transition; and a 0 preceded by a 0 produces a transition at the beginning of the bit cell time. Therefore, with MFM encoding, flux transitions are always present even with an all Os or-all 1s data pattern.

SYS (01 H

NRZWRT DATA |
MFM DATA
writecurrent

|
|

O
1

|
J

[

]

p—BIT —»
1

S
0

|
|

|
I

[

|
!

I
1

|
I

1 L

L
l

|
1

n
|

.
0

||
I

| l

L
I

[
NMR-5908

Figure 2-10

MFM Encoding

A problem with this recording method is that adjacent flux transitions appear to be moved from where
they were written. This is called peak shifting. The direction of the peak shift is linked to the position of
the MFM pulses. Two pulses close together shift the peaks of the read voltage away from each other.

(See Figure 2-11.)

2-12

To offset this peak shifting, the write encoder uses a delay line to shift the data in the opposite
to that expected by the peak shift. This shifting of the data is called precompensation.

direction

The delay line has nine taps off it. Each tap delays the data input 5 ns more from its entry point.
(Sce
Figure 2-12.) All nine taps go to a multiplexer. (The center tap is a reference line.)
The select lines to the multiplexer come from a PROM and binary counter, which keeps a history
of the
previous data. The select lines determine whether to advance or delay the new data
from the previous
- data, creatingp precompensat
ed MFM data.
'
Y

BIT CELLS

MFM DATA

¢}

DISK TRACK FLUX

[

REVERSALS

INDIVIDUAL PULSE
CONTRIBUTION TO VOLTAGE

WAVEFORM

[2]

- ""l e

IDEALIZED READ SIGNAL

VOLTAGE PULSE

fw]

[

e '-"—“‘J**-O-G“-O--fl-] —-b—c-—o--u—--u-ulq-—q—c-—o—«l—n—o-—o——-b—.—s
(3)

l 3

Y (2:
:

‘\.\

b
|

[

[a]

Hil
//’l N

(14

T ST
~. -

(5)

;

[

il
:

| (3)
,"+\\
\: N

(5)
,"T"‘-..\

A
e
\‘w
-

\\k“

I
{

(21

’/

(4)

/,/

'
:

o
>

!
|

(.N

COMPOSITE READ VOLTAGE

H T PEA!l SHIFT /H
MR 5909

Peak Shift Waveform

(V)

Figure 2-11

WAVEFORM

8.2 MHZ

D-TYPE

CRYSTAL

0sc

8.2 MHZ

O
SYSOH

SYS1 H
SYS O H

O
O
IT

DELAY LINE 5 NS/ITAP

)

WRT DATAPLS H

—Q
we

TO BUS INTERFACE
TRANSCEIVERS

_
SELECTABLE
MUX

—————C}

SEL

———C)

BINARY
BO

(EJ(;U

(]

NT-

LD CK

-2:23

8.2 MHZ

PROM

SYSOH

————-}

B3
B4

PREVI-

MUX DATA H—

gus

FROM

DATA

DATA SOURCE | g1 1p.

ADDR

MULTIPLEXER | FLopPs

{1 OF 6)
MR 5746

Write Encoder and Precompensation Circuit

Figure 2-12

2.9

DATA SEPARATOR READ CIRCUIT

The data separator read circuit (Figure 2-13) takes the MFM data from the disk drive and produces
binary data and a clock. This circuit uses a phase-locked loop to generate a clock signal to synchronize
to the MFM data. (A variable capacitor scts the free-running frequency of the voltage-controlled oscillator (VCO). This frequency is set at the factory and should not be changed.) Then, the read circuit’
decodes the MFM data. The serial binary data then goes to the FIFO scrializer, as DS DATA H.and is
.

clocked in by DS CLK.

PHASE DETECTOR
UP H

—

DURING READ)
EN LOOP LOCK H

(ASSERTED

FROM DRIVE

pYEL
DOWN

\_lrcan

CLKH

(1)

RCB H

‘

pATA

FIF

(JloeLay LinE 10 NS TAP)

eons
—

~-—0DETEN
L

MARKER L
[

;

_RCE L-O

|
g

BUS TRANSCEIVERS 1K

DS DATA L-

INPUT

INPUT DATA LA

pata|l

DS CLK H

MARKER

R=n
T

_VCO CLK L-OfF/F
—K

l_
-

UP L

DATA H

RCE L

PHASE-

LOCKED|
LOOP

VCO CLK H

RCE

F/F

o
74574

E/E

—iC

DN L-C1 vco

RCE H

C66

DS DATA H

DS DATA|Y-DS DATA L

F/F

TO FIFO

SERIALIZER

CRDY L

AND MARKER

rurFLOP

—0
MR.5747

Figure 2-13

Data Separator Read Circuit

2-15

CHAPTER 3
CONFIGURATION AND INSTALLATION
3.1
INTRODUCTION
This chapter provides the user or installer with information to configure and

install the RLVI2 ina 16-,
18-, or 22-bit LSI-11 bus. The user can change the device address, interrupt vector,
and memory parity
error abort feature.

3.2 - DEVICE ADDRESS SELECTION
'
Software control of the RLV12 is by means of four or five device registers — CSR, BAR,
DAR. MPR.
and BAE. Four registers are used for 16- or 18-bit addressing: five registers are uscd
for 22-bit addressing. The bus address extension register (BAE) is added for upper address bit selection
for 22-bit addressing. The usual device starting address is as follows.
Addressing Mode

16-bit

18-bit

Starting Address (Octal)

174400

774400*

22-bit

17774400

The first register, the CSR, is assigned the starting address., and the other registers
next sequential addresses, as shown in Table 3-1.

arc assigned the

The device starting address is selected by jumpers for bits 3 through 12. These jumpers are
shown in
Figure 3-1. A jumper from the selected bit to ground (M22) decodes a 1: no Jumper
decodes a 0; and a
jumper to +5 V (M11) decodes an X (don’t care) condition. Figure 3-2 shows the RLV
12 device starting address format.
.

NOTE
For 22-bit addressing, bit A3 is not decoded in the

starting address.

3.3

BUS SELECTION

The RLV12 module can be used on 16-, 18-, or 22-bit LSI-11 buses. When sent from the factory,
the
module operates on 16- or 18-bit buses. To enable the module to operate on a 22-bit bus, install jumper
M1 to M2, shown in Figure 3-1. When installed, the jumper enables bank select 7 (BBS7) to be deter-

mined by the upper address bits (13-21). When the jumper is removed, the RLV12 has an 18-bit mode
bank select 7 and can replace an existing RLV11 or RLV21 as the disk controller for RLOt and RLO?2
disk drives.
|
|
)

3.4
INTERRUPT VECTOR
|
The interrupt vector has a range of 0 to 774. The interrupt vector is preset at the factory to 160. The
~uscr may select another vector by changing the jumpers for bits V2-V8, as shown in Figure 3-3. A
connection to VEC TO BUS H (M3, shown in Figure 3-1) generates a 1 for that bit; no connection
generates a 0.

3.5
INTERRUPT REQUEST LEVEL
|
The RLVI2 interrupts at priority level 4 determined by the interrupt chip E23, a DCO003.

3-1

Table 3-1

Address Selection

22-Bit
Addressing

Device
Address

16-Bit
Addressing

18-Bit
Addressing*

,
Starting
Address Range

160000177770

760000-777770

Starting

174400

774400

17774400

8 (5 are used: 3 are not)

CSR (174400)
BAR (174402)

CSR (774400)
BAR (774402)

CSR (17774400)
BAR (17774402)

17760000-17777760
e

Address

No. of
Registers

Registers
Used

Jumpers Used

DAR (174404)
MPR (174406)

Tie M22 (*17)

DAR (774404)
MPR (774406)

Tie M22 (1)

DAR (17774404)
MPR (17774406)
BAE (17774410)

CTie M22 (*1TM)

to M17, M20,
and M21;

to M17. M20,
and M21

to M17, M20,
and M2l

Vector Range

0-774

Standard

160

Tie M3 (“17)
to M6, M7,
and M8

Tie M3 (1)
to M6, M7,
and M8

Tie M3 (*1TM)
to M6, M7,
and M8

Tie M11 (©“X")
to M12

Interrupt

Vector

Jumpers Used

*Factory Configuration

ENABLE CRYSTAL
M29

£M28
ENABLE

VCO CLK
M27 M26

MEMORY PARITY ERROR
. | ABORT SELECTION

M11 - +5V 713 M23

X TEST POINT

oeE NOTE

M24

M12- A3

M30

- Ad
M13

- A5
M14

W3
DEVICE

ADDRESS
PINS

- AB
M15

Mi0 MG M8 M7 M6 M5 M4 M3

Mi6. A7

| M8

Moz
M18 - A9

V7 V6 V5 v4 V3 V2 VECTOBUSH
'
v

- A10
M19

M20-A11

- A12
M21
W2

E23

M22-- GND |

11/

PASS CD PRIORITIES

JUMPER

ASSEMBLY

(CDMG, CIAK)

M2 M1

ENABLE
22-B1T ADDRESSING

'NOTE:

THE MEMORY PARITY ERROR ABORT
FEATURE IS AVAILABLE FOR USE
WITH MEMORIES THAT HAVE PARITY
ERROR CHECKING.

THIS FEATURE DOES NOT HAVE TO
BE DISABLED FOR MEMORIES THAT
DO NOT HAVE PARITY ERROR
CHECKING. THE PINS ARE CONNECTED AS FOLLOWS:

CONNECTION | FUNCTION
M23 - M24
M24 - M25

NO PARITY
PARITY ERROR ABORT
MR 5748

Figure 3-1

RLV12 Jumper Locations

3-3

Al2 1 A1l | A10

M17

Mie

MI15

M14_

M13

M1,2

BANK SELECT 7

FOR 18817

—

ppo

BANK SELECT 7 FOR
22-BIT

FACTORY

ADDRESSING

3/121

{CONNECT M1 TO M2}

CONFIGURATION

CSR

ADDRESSING

M20

M19

M18

774402

DAR

774404

MPR

774406

BAE

774410

BUS ADDRESS PINS

774400

BAR

CONNECT TO GROUND (PIN M22)
TODECODEA1.CONNECTTO+5V(PINMH)
FOR

A DON'T CARE

{X)

CONDITION.

NO CONNECTION DECODES
A 0.
‘
MA.47249

|vea|vri|[ve]|vs|va|vs]|val

CONFIGURATION

160

)

Mé

Se——0e——

{

FACTORY

-—

RLVI2 Device Address Format

——
]

—

Figure 3-2

ANTERRUPT VECTOR PINS

CONNECT TO PIN M3
TO DECODE A 1.
NO CONNECTION DECODES A 0.
MR-§750

Figure 3-3

RLVI2 Interrupt Vector Format

3.6 MEMORY PARITY ERROR ABORT FEATURE
When reading the system’s optional memory with
parity error detection, a parity error will set OPI
and
NXM of the CSR. This is a unique error condition
that aborts the current command to the RLV12.
This error abort feature is possible only with memori
es that have parity data bits.
The RLLV12 is sent from the factory with the memor
y parity error abort feature enabled. To disable
parity error abort, remove the jumper between
pins M24 and M25 and install a jumper betwee
n pins
M23 and M24. (See Figure 3-1.) This feature does
not have to be disabled for non-parity memories,
as
parity errors are not generated. Parity error abort uses
data bits 16 and 17.
.
3.7 JUMPERS THAT REMAIN INSTALLED
The module has two jumpers, W1 and W2, that enable
priority signals to pass through the module. The
module has these jumpers installed, and they should
be left in.

Jumper

Wi
w2

Signal

CIAKI to CIAKO

CDMGI to CDMGO

One jumper, W3, enables the word count register to automat
ically increment during a DMA operation.
This jumper is used for factory testing and should be
left in.

3-4

Two jumpers on the module disable the crystal oscillator and the voltage-controlled oscillator (VCO)
during factory testing. Thesc jumpers should be left in.
Jumper

Oscillator

M26-M27
M28-M29

vVCO
Crystal

|
/
3.8 INSTALLATION
The RLV12 can be installed in any quad LSI-11 bus slot. The controller’s priority level is based on its

“electrical distance from the processor module. Use the following procedure to install the module.
1.

Examine the module to make sure that the base address jumpers and vector address jumpers
are set correctly (See Parag’raphs 3.2 and 3.4))

F 20 '_.ChcckjumpersM} and \/I? for enabling the correct b'mk select 7 (BBS?) for the 18- or 22~bit LSI-11 bus.

If desired, disable the memory parity error abort feature. This feature can only be used with
system memories that have parity options. but this feature does not have to be disabled for
non-parity memories. (See Paragraph 3.6.)
:

Insert the BC80\4 controller cable (or cquwalent) into JI on the M806] as shown1n mec
3-4.

3.9

lnsert the M8061 in the selected slot in the LSI-11 bus.

Attach the ground strap on the cable to the metal cabinet chassis.

Connect the other end of the BC80M cable to the back of the first disk drive.

Continue with the disk mstallatnon Refer to the RLOI/RLO2 Disk Subsystem User’s Guide
(EK-RLO12-UG).

ACCEPTANCE TESTING

The RLV 12 controller is tested by running the RLV12 diskless diagnostic test and, if a drive is attached, by running the diagnostics that exercise the RLO1 and RLO2 disk drive. The diskless diagnostic
should be run first. The RLV12 diagnostics are available on different media. Contact your local Digital.
sales office for the types of media available and their part numbers.

Run the XXDP-+ diagnostics in the following order.

CVRLB RLVI12 Diskless Diagnostic (16-, 18-, or 22-bit mode)

NOTE

When the RLV12 is configured for 16~ or 18-bit addressing, the RLV11 diskless diagnostic (CYRLA)
is compatible with the RLV12 diskless diagnestic
and checks the same logic.
2.

CZRLG Controller Test Part 1

CZRLH Controller Test Part 2

CZRLI Drive Test Part 1

CZRLJ Drive Test Part 2
CZRLN Drive Test Part 3

CZRLK Pcrformanc; Exerciser
CZRLL Compatibility Test

CZRLM Bad Sector File Utility
NOTE
The Bad Sector File Utility is not a diagnostic test.

- It is used by field service to examine the bad sector
- file on the disk and to write entries into that file.

ATTACH TO
METAL CHASSIS

ATTACH TO
FIRST DiISK
DRIVE

M8061

o—RLV12

BACKPLANE -

MR 5898

Figure 3-4

RLVI12 Installation

3-6

CHAPTER 4

REGISTERS
4.1

INTRODUCTION

This chapter describes the functions of the bits in each of the five programmable registers.

NOTE

To prevent accidental writing on a disk, the RLV12
:synchromzes on controller ready (CRDY). If the
CRDY bit in the CSR changes from clear to set

while the processor is in ODT mode, the next read
access of any RLV12 register produces all 0s.

4.2 CONTROL/STATUS REGISTER (CSR)The control/status register (Figure 4-1)
is a 16-bit, word-addressable register with a standard address of
774400 for 18-bit addressing. Bits 1 through 9 can be read or written; the other bits can only be read.
The bit functions are described in Table 4-1.

When the LSI-11 bus is initialized with BINIT L, bits 1-6 and 8-13 are cleared, and bit 7 (CRDY) 1s
set. Bit 0 (DRDY) is set when the selected drive is ready to accept a command; otherwise, this bit is
cleared. Bit 14 (DE) is clear as long as there is no drive error. Otherwise, this bit is set and stays sct
until the drive error is corrected; or if bit 3 (drive reset) is set in the DAR and the controller is sent a
Get Status command, the DE bit is cleared.

Bit 15 (ERR) is set When there is a drive or controller error in bits 10-~14.
At the beginning of each controller command, error bits 10-13 are automatically cleared. At the completion of each controller command, bit 7 is automatlcally set. (Bit 7 is also set if an error is detected
during command execution.)

4.3

BUS ADDRESS REGISTER (BAR)

The bus address register (Figure 4-2)is a 16-bit, word-addressable register with a standard address of
774402 for 18-bit addressing. Bits O through 15 can be read or written; bit O is usually written as 0. The
bus address register indicates the: memory location for the DMA data transfer during a read or write
operation. The register’s contents are automatically incremented by 2 as each word is transferred between the system memory and the controller.

The bus address can be expanded for an 18-bit LSI-11 bus by using bxts 4 'md 5 (BA 16 and 17) ofthe
CSR or by using bits 0 and 1 of the BAE register.

The bus address can be expanded for a 22-bit LSI-11 bus by using the BAE register (BAE 16-21).
NOTE
When using 22-bit mode, writing CSR bits 4 and §
modifies BAE bits 0 and 1 and vice versa.

The BAR is cleared by initializing the bus (BINIT L.).

4-1

Table 4<1

Bit(s)

Name

DRDY

CSR Word Format

Description

Drive Ready — When set, this bit indicates that the selected drive is ready to receive a command or supply

valid read data. The bit is cleared when a Seck or head select operation is started and set when the Seek

operation is completed.

1-3

FO-F2

Function Code — These bits are the function code set by software to indicate the command to be executed.
Octal
Code

Function
F1
F2

Command

0
0
0
0
0 - . L

0
1
..0.

Maintenance mode
Write Check
:GetStatus . _ _ -

0
1
,
-~ 2

0
I
1

1
0
]

Write Data
Recad Data
Read Data Without

-5
6
7

1
1
1

Header Check

Command execution starts when CRDY'(bit‘ 7) of the CSR is cleared b),-" software: The commandsL).are’
described in more detail in Chapter 5. The function code is cleared by initializing the bus (BINIT

4,5
6

BAIlG6,
BA17

Extended Address Bits = These two bits are the upper-order bus address bits for 18-bit buses. These bits
arc read and written as bits 4 and 5 of the CSR. They function as address bits 16 and 17 of the BAR.

Interrupt Enable - When CRDY is asserted, bit 6 allows the controller to interrupt the processor. This

Writing bits 4 and 5 of the CSR also writes bits 0 and 1 of the BAE. -

interrupt occurs at the termination of a command. Once an interrupt request is placed on the LS1-11 bus,
it is not removed until acknowledged by the LSI-11 processor even if 1E (bit 6) is clcared. This bit is

Controller Status Errors — These bits are the error code set by the controller to indicate one of the follow-

ing errors.

Operation incomplete (OPI)
Data CRC (DCRC)
Hcader CRC (HCRC)
Data late (DLT)

Header not found (HNF)
Nonexistent memory (NXM)
Parity crror abort (PAR ERR)

—_ O

Error

VN AW~

Octal
Code

E0
D —

Error Code
E2
E3

EO0-E3

Drive Select — These bits determine which drive will communicate with the controller via the drive bus.

These bits are cleared by initializing the bus.

10-13

DS1

—_—

DSO,

QOO0
= —=O

8.9

Controller Ready — When cleared by software, this bit indicates that the command in bits 1-3 is to be

executed. This bit is set by the controller at the completion of a command, at the dctection of an crror, or
by initializing the bus. Software cannot set this bit because no registers are accessible while CRDY is 0.

COmm= OO0

CRDY

—_——
0 o000

clearcd by initializing the bus.

Opcration incomplete indicates that the current command was not completed within the OPI timeout peri‘

od of 550 ms.

A data CRC ecrror indicates that while reading the data field from the disk, an crror was found.
A header CRC error indicates that while rcading the header from the disk, an error was found. The CRC
check is performed on the first and second header words, although the sccond header word is always 0.

4-2

Table 4-1

CSR Word Format (Cont)

Description

Data late indicates that the FIFO RAM was more than half full and the controller was not able to read the
next sequential sector. This error may occur during a Read Without Header Check command.

Header not found indicates that an OPI timeout occurred while the controller was scarching for the cor-

rect sector to read or write. A header compare did not occur.

A nonexistent memory error indicates that during a DMA transfer the memory location addressed did not
respond with RPLY within 10 ps.

A memory parity error abort indicates that a parity error was detected while reading the system’s optional
memory that has parity error checking. If an error was detected, the current command to the RLVI2 is
:

aborted.

Drive Error — This bit is buffered from the drive crror interface line. When set. it indicates that the se-

lected drive has flagged an error, the source of which can be determined by exccuting a Get Status command. DE will not set ERR (bit 15) or CRDY (bit 7) until the usual occurrence of CRDY.

Composite Error — When set, this bit indicates that one or more of the error bits (bits 10-I4) are set.

When an error occurs, the current operation terminates and an interrupt routine is started if the interrupt

enable bit (bit 6 of the CSR) is set.

the bus by starting a new command. with the exception of DE and
All error bits are cleared by initializinig
ERR if they were caused by a drive error.

) Y,

15 14 13 12 11 10 09,5 08 07 os[ 05 04 03/ 02 01 00
D

ERR| DE INXM|DLT|~pe|

PAR

|opi

{

H | OPI

errlfNFlerel

|DS1{DSO

DRDY

BA17

CRDY

F1 | FO

BA16

READ ONLY

gmg

READ/WRITE

MR 5757

Figure 4-1

|
BA15 l BA13
BA14

BA12

11
|
BA11

Control/Status Register (CSR)

BA9|BAS|BA7|BAG}BASIBA4|BA3|BA2]IBA1]

BA10

—
~—

READ/WRITE

Figure 4-2

Bus Address Register (BAR)

4.3

MR 5752

4.4

DISK ADDRESS REGISTER (DAR)

The disk address register is a 16-bit, read/write. word-addressable register with a standard address of
774404 for 18-bit addressing. Its contents has one of three meanings, depending on the command being
performed.

Command

DAR Function

Seck

Head selected, number of cylinders to move, direction

Read Data

Head selected, cylinder address, sector address

Get Status

Send drlve status to MPR; reset error reglsters :

or Write Data

) '_The DAR1s cieared by mmahzmo the bus (Bl\llT L)

4.4.1

DAR Durmg aSeek Command

To perform a Seek command, the program must provide the head selected (HS), direction to move
(DIR), and the cylinder address difference (DF) as indicatedin Fxgure 4-3. The blts are descnbedin
Tablc4’)

- -4 4.2

DAR Durmo a Read, W nte, or W rlte Check Command

For a Read, Write, or Write Check command, the DAR provxdes the head selected (HS) 'md the address of the first sector to be transferred (SA), as indicated in Figure 4-4. The bits are describedin
Table 4-3. As each sector is transferred, the DAR sector address increments by 1.
.
4.4.3

DAR During a Get Status Command

Both the CSR and the DAR must be programmed to perform a Get Status command. The DAR must
be programmed as shownin Figure 4-5. Then a Get Status commandis placedin the CSR. The DAR
bits are described in Table 4-4.

4.5

MULTIPURPOSE REGISTER (MPR)

The multipurpose register is a 16-bit, read/write, word-addressable register. It is accessed using the
standard address of 774406 for 18-bit addressing. Following a Read Header command or a Get Status
‘command, reading the MPR obtains sector header or drive status information.

Writing to the MPR is uscd to set the word count. The word count is cleared by initializing the bus

(BINIT L).
4.5.1

Writing the MPR to Set the Word Count

Before starting a DMA transfer, the MPRis loaded with the word count. The program must load the
MPR with the 2’s complement of the number of words to be transferred. The MPR is written in the
format shownin Figure 4-6. The bits are describedin Table 4-5. As each wordis transferred, the MPR
is automatically incremented by 1. The reading or writing operation contmues until a word count overflow occurs, indicating that all words have been transferred.

"The word count can range from 1 to 5120 data words. The maximum word count is limited by the
maximum number of sectors available (40) and the maximum words per sector (128).
NOTE

Once written the word count cannot be read back.
Reading the MPR does not change the word count.

4-4

[DF8| DF7]DF6 {DFS |DF4{DF3 DFZ DF1IDFOf

O | O

{HS}| O

[DIR} O

(RLO2 ONLY}
MR 5753

Figure 4-3

Table 42
Bit(s)

Name

Description

MRKR

Markcr ~ Must bea 1.

none
DIR

DAR During a Seek Command

DAR Seek Command Word Format

Must be a 0, mdncannu to the drive that a Sc.ek commandis being issued and that the other bitsin thc.

Direction — This bit indicates the direction in which the Seek is to take plauc When the bitis set, the

heads move toward the spindle (to a higher cyvlinder address). When the bit is cleared, the heads move

away from the spindle (to a lower cylinder addrem) The acnual distance moved depends on the cylinder
address difference (bits 7-15).
3

none

Must be a 0.

Head Select — Indicates which head (disk surface) is to be selected: 1 = lower, 0 = upper.

5.6

none

Reserved

7-15

Cylinder Address Difference — Indicates the number of cylinders the heads are to move on a Seek.

CAB|CA7|{CAG|{CAS5|CA4|CA3|CAZ2|CAT|CAQl HS [SA5ISASL SAS SAZ! SAT{SAD
MR-5754

Figure 44

DAR During a Read, Write, or Write Check Command

Table 43

DAR Read/Write Data Command Word Format

Bit(s)

Name

Description

0-5

Scctor Address — Address of one of the 40 sectors on a track. (Octal range is 0 to 47.)

Head Sclect ~ Indicates which head (disk surface) is to be selected: 1 = lower: 0 = upper.

7-15

Cylinder Address — Address of one of the 236 ¢vlinders for RLO1 or 512 c_‘,lmdc.rs for RLO2. (Octal range
is0 to 777.)

4-5

o|lo}o

0O'

0 |RST| O

1
MR 5755

Figure 4-5

Table 4-4

Bit(s)

Name

Description

MRKR

\fhrkcr3 Must bea 1.

oGS
'

DAR During a Get Status Command

DAR Get Status Command Word Format

Get Smlus — Must be a |, indicating to the drive to send its status word At thc compl:.lton of thc Get

Status command, the drive status wordis read into the controller multipurpose n.gmcr (MPR). With this.
bit set, bits 8-15 are ignored by the drive.

‘none

Must bc a0.

RST

" Rcsct - When thm bit is sct, thc disk drive ClLdI‘b its error register oi ‘;ofi crrors bn.foru scndmg a status |

4-7

none

Must be a 0.

8-15

none

Not used.

)

word to the controller.

01t

WCHWCBIWC7IWCEIWC5|WC4WC3WC2|WC1|{WCO

wC12

wC10

WC11

Figure 4-6

MR-5756

Writing the MPR to Set the Word Count

Table 4-5

MPR Word Count Format

Bits

Name

Description

0-12

Word Count — This is the 2's complement of the total number of words to be transferred.

13-15

none

Must be all 1Is for word count in correct range.

4-6

4.5.2

Reading the MPR After a Read Header Command

4.5.3

Reading the MPR After a Get Status Command

When a Read Header command is exccuted. three words can be sequentially read from the MPR. as
shown in Figure 4-7. The first word includes the sector address, the head selected, and the eylinder
address. The second word is all Os. The third word has the header CRC information.

After a Get Status command is executed. a status word is stored in the MPR, as shown in Figure 4-8.
The status word from the selected disk drive includes information on the functional state of the drive
and any drive errors. The bits are described in Table 4-6.

4.6

BUS ADDRESS EXTENSION REGISTER (BAE)

The bus address extension register is a 6-bit read/write register used to drive address bits 16-21 for a
27.bit LSI-11 bus. The BAE has a standard address of 17774410 for 22-bit addressing. A write to the
- BAE loads TS DAL 0-5 into BAE 0-5, shown in Figure 4-9. Reading the BAE enables bank scleet 7
(A jumper must be connected between M1 and M2 on the controller to
(BBS7 L) to the LSI-11 bus.
~enable 72-bit addressing; see Chapter 3.) When address bits 13-21 are all 1s, the RLV12 drives BBS7
L to direct data t_ort_'he 1/0 page.

“The two least significant bits.of the BAE (bus address lines 16 and 17) are mirrored in bits 4 and 5 of
the CSR. The same bits can be rcad or written as CSR bits 4 and 5 or BAE bits 0 and 1.
Writing CSR bits 4 and 5 medifies BAE bits 0 and 1
and vice versa.

The BAE register is cleared by initializing the bus (BINIT L)
04 03

0OV

06 05

o010

SAZ|SATISAD]
C\IS(;-RD caslcazlcae|cas|CA4|CAZ{CAZ|CAL|CAO| HS |SAG|SALISAI

2ND

worp|

3RD

WORD

CRC1
CRC3
CRCSH
CRC7
CRCS
CRC11
CRC13
CRC15
CRCQ
CRC2
CRC& CRC4
CRCS8
CRC10
CRC12
CRC14
MR-5757

Reading the MPR After a Read Header Command

Figure 4-7

(Three Header Words)

’

SPE |WGE| VC |DSE! DT | HS | CO { HO | BH |STC}STB|STA

[WDEJHCE] WL
|

SKTO

STATE
MR 5758

Figure 4-8

Reading the MPR After a Get Status Command
4-7

Table 4-6

MPR Status Word Format

Bit(s)

Name

Description

0-2

STA.
STB.

These bits (A, B. and C) define the state of the drive as follows.
‘

STC

Load state

Spin up

Brush cycle

0
1
1

1
0
0

1
0
} ..

Load heads
Seektrack counting
Secek lincar mode (lock on)

State of Drive

b 1. 1.0, - Unload heads. .,,;T;_,‘,;_u--,*. .
- l~ ‘*"i_l-_j_»f-_ 1--“ Spmdown T T TR

BH.

Bruah Homc - Aaacrted when thc brushcs are¢ not over the disk..

Heads Qut
- As:crted when the heads are over the disk

-5

- CO.

Cover Open—~ Asserted when the cover is open or the dust_rcdvervis'not' in place. -

| HS

Hea‘d» Select — Indicates the head selected: | = lower, 0 = uppef.

Drive Type — Indicates the type of disk drive: 0 = RLO!l, 1 = RLO2.

DSE

Drive Sclect Error — Indicates multiple drive sclection is detected.

vVC

Volume Check — VC is sct every time the drive goes into load heads state. This asserts a drive error at the
controller, but not on the front panel. VC is an indication that the program does not know which disk is
present until it has read the serial number and bad sector file. (The disk might have been changed while
the heads were unloaded.)

WGE

Write Gate Error — Indicates that the write gate was asserted when thc drive was not ready. the sector
pulse was asserted, or the drive was write-locked.

SPE

Spin Error — Indicates that the spindle did not reach full speed within a specific time, or it is turning too
fast.

SKTO

Seek Time Out — Indicates the heads did not come onto track within a specmc time during a Seek com-

mand.
13

Write Lock - Indicates write lock status of selected drive: 0 = unlocked; | = protected.

HCE

Head Current Error — Indicates write current was detected in the heads when write gate was not asserted.

IS5

WDE

Write Data Error - Indicates write gate was asserted, but no pulses were detected on the write data line.

010

010
]
BA21

[

BA20

1
BA19

BA18

[

BA16

BA17
MR 5899

Figure 4-9

BAE Register Word Format

4-8

CHAPTER 5

COMMANDS
INTRODUCTION

5.1
This chapter describes the commands that are sent to the control /status register, FO, F1, F2, to perform
a specific disk function. The number in parentheses after each command is the octal code for the com-

“mand.

CRDY (controller ready) is set in the CSR (bit 7). Softand
is'that
A prerequisittoe issuing any comm
T
* ware cannot set this bit and cannot access any-régister if this bitisO0.

are automatically cleared. At |
At the start of each new command, the error bits in the CSR (bits 10~13)
(CRDY is also set if an crror is

the completion of each command, the CRDY bit is automatically set.

detected during command execution.)

Prerequisite: The disk heads must be placed at the correct track by issuing a Seek command if neces-~
sary. The BAR must be loaded with the address of the first location of the data block in system memory. The word count of the data block length must be loaded in the MPR. The DAR miust be loaded with
the starting disk address location.

The Write Check command is used to verify that data was written on the disk correctly. It is used after
writing a block of data on the disk by the Write Data command.

The Write Check command reads this same block of data and compares it with the data in the computer’s system memory. Because this comparison is performed in the controller, this source data must
be transferred out of memory into the controller’s FIFO buffer. A bit-by-bit comparison of the header
on the disk and the contents of the disk address register checks for a header match.

Once a header match is found and the header CRC validates the match, the 128 words of data are read
from the disk. This data is then compared with the serial data coming out of the FIFO serializer (SER
DATA OUT). A compare error or a data CRC error sets bit 11 in the CSR.
-

NOTE

When writing only a partial sector (less than 128
words), words with all Os are used to fill the remaining portion of the sector.

5.3

GET STATUS (2)

does not
Prerequisite: The software should first verify that the controller ready bit is set. (The drive
be set;
must
1
and
0
Bits
have to be ready.) Then a status request word must be loaded into the DAR.
4.4.3.)
h
Paragrap
bit 3 (reset) can be either 0 or 1; and all other bits must be 0s. (See
A Get Status command in the CSR asks the selected disk drive to return information about its current
operation and error status. If the reset bit (bit 3) is set in the DAR, the disk drive first clears its error
register of all soft errors before sending back the drive status. When the drive sends back its status
word, it is stored in the FIFO buffer and can be accessed by reading the MPR.

DRDY (drive ready) does not have to be sct to issuec a Get Status command. For example, a Get Status

is in its load state.
command can be issued during a scek operation or when the drive
5.4

SEEK (3)

Prerequisite: The present location of the disk head must be known. This can be determined with a Read
Header command. Then the software must compute the cylinder address difference (DF) needed by the
drive to move the heads to the new location. Then the DAR must be loaded with the head positioning
information. The DAR must include the number of cylinders to move (bits 7-15), the head sclect bit

(bit 4), and the direction to move (bit 2). Bits 6, 5, and 1 must be sct to 0; bit 0 must be set to 1.

The Scek command shifts the contents of the DAR to the disk drive. The DAR contains the head selected for the next data transaction, the cylinder difference address, and the direction of movement.
Once the drive receives this head positioning information, it moves the head to the new track location.

READ HEADER (4) - Prerequisite: A Get Status command must be issued and DRDY must be sctmtheCSR

on the sclc'ctéd drive andstorcs thh‘e :tfiréé_" :
the first-he'ader found
: Thc Read ’i-léader- c&fimand-réads The
first word, WD, includes the cylinder address, the head seheader words in the FIFO RAM.
lected, and the sector address. The second word, WD?2, is all zeros. The third word, WD3, has the head-

~er CRC information. These words can be read from the FIFO RAM buffer by consecutive rcad MPR
“instructions. Three read MPR instructions are needed to read three FIFO words. Reading the first - header word provides enough head positioning information to permit software computation of the cylin~der difference for another Seek command to a new track address.
5.6

WRITE DATA (5)

Prerequisite: The head must be loaded at the correct track, by issuing a Seek command if necessary.
The 2’s complement of the words to be written (word count) must be loaded into the MPR.

The Write Data command enables the controller DMA circuitry. The RLV12 becomes LSI-11 bus
master, and data words are loaded into the FIFO buffer. When the drive is ready, header information is
read from the disk and compared with the first sector address stored in the DAR. Once a header match
is found, the FIFO data is written on the disk in sequential sectors until the word count is complete. The
BAR and word count are incremented for each word transferred. If only part of a sector is filled by the
new data, the rest of the sector area is filled with 0s. At the end of the sector, the sector part of the
DAR is incremented. At the end of a transfer, CRDY is set and an interrupt is made if 1E is set.
5.7

READ DATA (6)

Prerequisite: The head must be loaded at the correct track, by issuing a Seek command if necessary.
The 2’s complement of the words to be read (word count) must be loaded into the MPR.

The Read Data command causes headers to be read from the disk and compared to the sector address
stored in the DAR. When a header match is found, disk data words are transferred into the FIFO memory. Both the BAR and word count are incremented for each word transferred. After four words are
read from the disk, the microsequencer starts a DMA transfer on the LSI-11 bus. The data transfer
ends when the word counter overflows. If the word count is not complete, the next sector is read. Otherwise, CRDY is set and an interrupt is made if IE is set.
5.8

READ WITHOUT HEADER CHECK (7)

Prerequisite: The location of the scctor with the bad header must be known. The BAR must be loaded
with the starting memory location to place the words to be rcad. The MPR must be loaded with the
word count in 2’s complement form.

5-2

The Read Without Header Check allows the recovery of data if the headers cannot be read. If header
not found (HNF) or header CRC (HCRC) errors are found on a sector. then data cannot be recovered
by the usual Read Data command.

A Scck command must be issued to position the head on the sector with the bad header. Then the sector
preceding the bad sector must be found by performing consecutive Rcad Header commands. Finally a
Read Without Header Check command must be issued within 300 us to recover the data in the bad
sector. The BAR and word count are incremented for ecach word transferred. Data CRC is checked at
the end of a sector. If the word count is not complete, the next sector is read. Otherwise, CRDY is sct
and an interrupt i1s made if 1E is set.

NOTE
The DAR is automatically incremented after each
~ sector is transferred

:_5 MAlN F]ENANCE FUNCTIOV (0)

o 'Prerequmte The 'BAR must be set to the first location of a test data buffer. The word count register
~ must be sct to transfer 511 words (117701g). Too large or too small a WC resultsin a FINF error. (To
- be compatible with RLV
11 software, a WC of 510 should not be used.)
The maintenance function allows the RLV12 to perform a self-test operation. This functionis used to
~ test the controller and may be executed with-or without a disk drive attached. The maintenance func. tion pcrforms six internal tests-as. fo]lows The DARis incremented afler compleuon of each test.
Test

I and 2
3
4
5
)

Function

Check internal logic
Checks DMA transfers
Checks the CRC of (DAR -+ 3)
Checks the CRC of (DAR + 4)
Checks the CRC of (CRC of DAR -+ 4)
CAUTION
Memory locations are modified by this function.

Under DMA control, 256 words are transferred from memory, beginning at the starting address in the
BAR through BAR + 7763, to the FIFO RAM. Then all but the last word is transferred back into the
next 255 memory locations, starting at BAR + 1000g through BAR + 17744.
Next, the contents of the DAR are used to test the serial read/write data paths. The data uses an internal loop and
is not transmitted to the disk drive. The CRC of the DAR + 3 and the CRC of the (CRC
of DAR -+ 4) are storedin the FIFO RAM and can be read by reading the MPR. The DAR’s low byte
(bits 0-7) holds its original contents + 6.

The DAR’s high byte (bits 8-15) is not incremented even when an overflow occurs out of the low byte.

5.10

EXAMPLES OF USING COMMANDS

Paragraphs 5.10.1 and 5.10.2 provide examples of thc use of RLV12 commands in software programs.

Seek Operation

5.10.1

The following example illustrates the scquence of events for programminga seck operation.
1.
2.

Issue a Rcad Header command to the desired disk drive and wait for an interrupt request or

wait for CRDY.

Check error flag in the CSR.

3. Read the header word‘ from the MPR.
4.

Compute the difference address and the direction for the seek.

5. erte the dlfference word into- the DAR.

6. f"lssue the Seek command to the drwe and wart for seek to be completed '15 mdlcated by

'”"3DRDY

7Check error flagin the CSR
'Steps ],2 and 3 above are not needed for the next Seek commands lf the software program l\ceps the
';\;__.-'

~current. cylmder address and head selectedin memor)

.._,_

| Readmg sequentnal headers gnves head posmon and present dlI‘CCthfl SO the program can optnmzethef,
:

shortest distance to the new location.
5.10.2

Data Transfer Operation

The following example illustrates the sequence of cvents for programming a data transfer (read or
write) operation.

Perform the steps of the seek operation previously described.

Write the bus address in the BAR.

Write the extended bus address in the BAE if using 22-bit addressing.

Write the DAR with the cylinder address, head selected, and sector address of the first disk
o

location to be transferred.

5. Load the MPR with the word count (2’s complement of words to be trannsferred).
6. Issue a Read Data, Write Data, or Write Check command in the CSR.
|
7. | Wait for interrupt or test for CRDY.
8.

Check the CSR for an error flag.

Seek commands or data transfer commands may be given to other drives between issuing a Seek to the
:

first drive and issuing a data transfer command.

As soon as a Seek commandis issued to the first drive, it returns an interrupt and sets CRDY. A Seek
command may be given to another drive while the first driveis seeking. No interrupts occur when all
the seeks are complete, so as soon as all Seek commands are issued, data transfer commands may be
issued. Starting with the drive that was given the shortest seek distance makes it possible for the drive
that completes its seek first to immediately perform its data transfer and interrupts when done.

5-4

ERROR RECOVE
of the errors can
Errors can be detected and flagged in the RLV12 and RLO1/RLO2 subsystem. Some
of the errors
Some
again.
occur
not
may
error
the
again,
tried
be recovered; that is, if the operation is
are listed
errors
The
t.
equipmen
or
media
the
to
damage
or
are fatal and could result in loss of the data,
to
questions
of
kinds
the
suggest
examples
following
The
5-1.
Table
with the recommended action in

5.11

consider when programming error recovery routines.

The type of error is a factor in determining how many times to retry the operation. For example, a data
latc (DLT) error could be caused by a hardware system failure. but it could also be the result of bus
activity by other 1/0 devices exceeding their throughput capability for a short duration. In the later
-

case, the operation could be successful on the first retry.

e. logging routine should
An error
" “The rate of erfor,occurrence’is a good indicator ofsystem performanc
If the rate of DLT errors increases_, it-.could indicate hardware sys-~ =~ ©
~ be used to obtain this informa tion.
" tem failures, or it could indicate that the system is reaching its throughput capacity in its prescnt configuration.

is with a header not found (HNF)erto an error
Another example of applying practical consideratio
the head is not positioned over the correct: - ..

if the error occurs again, then possibly
ror. Aftera retry,

, the current
track. If a read header operation is performed and the address for the media is examined
IS a
possibly
cylinder and head can be determined to see if it is a position problem. If it is not, thenthat sectorthere
address
bad spot on the media and another area should be tried. If there is a bad header,use this bad sector.
should be entered into the Bad Sector File on the disk and the software should not

When an error ocError log files should be maintained and consulted to help determine error causes.
status of the unit,and

, the
curs, the program should log it with facts such as the contents of the registersthe
faster the cause can be
log,
whether or not a retry was successful. The more complete the error
diagnosed.

5-5

Table 5-1

Controller Status Errors

Controller

CSR

Error

Bit(s)

Recommended Action

OP1

Opcration incomplete; retry a limited number of times.

DCRC/HCRC

DLT

- HNF

Data or header CRC crror; retry a limited number of times. Record the contents of the
.

DAR.

Data late; retry.

Header not found; perform a Read Header com_m_zmd and vcrify cyli_ndér.

"NXM -

,'Non"e.ii.s_te_'n‘t memory; retry once. Record 't.hC‘LQO!:lt.CfltS of,__t_h';‘ BAR.

Parity Error - - .

" The command to the 'contr_ollcr_ is ab'or_téd: rc‘tr’y_. .

- Perform a Get Status command and check MPR for disk drive status errors: see Table 5-2.

Drive Error

Table 5-27 Disk Dfi\e Status Errors
Drive
Error

MPR Drive
Status Bit

Recommended Action

Cover open; close cover.

DSE

Multiple drive selection is detected. Retry once before telling operator to verify unit select plug.

WGE

| Write gate error; retry. Drive is not ready, drive is write protected, or drive has another error.

SPE

Spin crror; retry.

SKTO

Seek time out; reset drive and wait for 1.5 second before sending another Seek command.

Write lock: drive is write protected.

CHE

Current head error. This error is fatal: do not retry. Write current is detected
in the heads.

WDE

Write data error. This error i§ fatal; do not retry. No transitions are detected.

CHAPTER 6
DISK DRIVE
6.1

INTRODUCTION

The RLV12-AK and the RLV22-AK come complete with an RLO! or RLO2 disk drive, respectively.
The following switches and indicators are found on the front of the disk drive (see Figure 6-1).
Run/Stop switch with LOAD mdlcator o
- Unit Select plug with READY mdlcator
FAULT indicator. .

WRITE PROTECT switch and mdicator

~ Power ON/OFF control is a circuit breaker switch on the back of the dlsk dnve Operatnon of thns
swntch W1H not ddmage the dnve however this sw1tch15 usudH\ feft ONI-

: fThe user can %e]ect the voltaoe and ranoe for each dlsl\ drwe on the back of the drive.

LOAD
(RUN/STOP}
READY

(UNITSELECT)

.
/7

]

|
|

WRITE
PROT
MR-1860

Figure 6-1

RLO1/RLO2 Disk Drive (Front View)

6-1

6.2 USER SWITCHES AND INDICATORS
This paragraph provides information on cach switch and indicator.

Run/Stop Switch with LOAD Indicator — The run/stop switch when pressed, encrgizes the spindle motor. When pressed again, the switch turns off the spindle motor as long as the heads and brushes are
home. If the heads are loaded, pressing the switch causes the heads to unload and then turns off the
spindle motor.
‘
The switch has a mechanical memory. If the spindle motor is energized and the main power is lost for a
short time, the spindle motor energizes again.

The LOAD indicatoris on when the spindleis stopped, headis home, brushes arc home and the spmdle_
_motor is not energxzed A cartridge can be loaded when this mdncatoris lits

~ Unit Seleqtl’lugthh READY. Indlcatm;——Ihe umt sclczctpluois, a cam’buttonthatasmscrtcdin 1
- switch.*The switch_contacts are binary encodedfor the unit select number (0, 1,°2; or 3) on thecam
- button.-The READY indicator lights tmndncate a drwe I't.dd} condmon thals, the headsare. loaded

oma cylmder ready for a read or a wme operatlon

FAULT Indlcator= The F/\ULT mdlcator comes on whc.n an error condmon occurs m the drnw
,.';v.WRl]E
PROI‘ ECTSw:tch and

lndlcamr-T he WR!TEPROTECT

swnch when

pressed

scts tht

. drive in write protect mode. If the -drive is in the process of writing at the time that the switchis L
pressed, writing continues until the next sector pulse. The WRITE PROTECT indicatoris on when the
write protect function is enabled. Pressing the WRITE PROTECT switch again turns off the write
protect mode and indicator.

6.3 110/220 VOLTAGE AND NORMAL/LOW VOLTAGE RANGE SETTING
The voltage selection and voltage range are each sct by a terminal block cover, shown in Figure 6-2.
They should be set according to Table 6-1.

- For systems operating wnth low line voltage, proceed as follows to change the NORMAL/LOW termi=

nal block cover.

Remove the two screws from the NORMAL/LOW terminal block cover.

Withdraw the cover and reinsert it turned upside down.

After insertion, “LOW” must be showing through the small window in the cover.
Replace the two screws.

For systems operation at 220 Vac, 50 or 60 Hz, proceed as follows to change the voltage selection.
1

Remove the two screws from the 110/220 terminal block cover.

-~ Withdraw the cover and reinsert it upside down.

After insertion, “220" must be showing through the small window in the cover.
Replace the two screws.

6-2

1/O0 CABLE

NORMAL/LOW
TERMINAL BLOCK

'~ ONJOFF

+ o .COVER "

CIRCUIT BREAKER -

TERMINATOR

110220
TERMINAL

BLOCK COVER
MR 6584

Line Voltage

90105 Vac

100-127 Vac
180-210 Vac
200-254 Vac

Figure 6-2

RLO1/RLO2 Disk Drive (Rear View)

Table 6-1

Voltage and Range Selector Setting

110/220

Setting

110
220
220

NORMAL/LOW
Setting

LOW

NORMAL
LOW
NORMAL

Eflgflnan

FEB 82/Rg"

EK-RLVI2Ccl

RLViZ Disk Controiier
Configuration Sheet
OPTIONS INCORPORATING THE RLV12

MODEL

MODULE

NUMBER

QOTY |COMPONENTS | NUMBER | DESCRIPTION

RLV12
RLV22-AK

1
|1
1

M8061
M8061

DISK CONTROLLER
DISK CONTROLLER
10.4 MB CARTRIDGE DISK DRIVE

The
RLV12 isa
RLO1/RL02 cartridge disk drive controller contained
on one quad-height multilayer module (M8061). The RLV12 may reside in any quad- or hex-size 16-, 18-, or 22-bit LSI-11 backplane and

can support up to four RLO1/RL02 disk drives in any combination.

BC80M CABLE SHIELD SHOULD BE CONNECTED TO CHASSIS GROUND
AT BOTH ENDS OF THE CABLE.

The RLV12 transfers data to and from the LSI-11 bus using direct
memory access (DMA) techniques. This allows data transfers to occur,
without processor intervention.

The RLV12 contains the following features.
Single quad-height module requiring no C-D interconnect.

Supports DMA data transfers in 16-, 18-, or 22-bit addressing modes.
Software compatible with RLV11 controller in 16- or 18-bit mode.
Factory configured to support 22-bit addressing with a backplane such
Copyright © 1982 Digital Equipment Corporation

NOTE:

RLV12
RLV12
RLO2-AK

as the H9275-A.

Controls from one to four

RLO1/RL02 drives.

Memory parity error abort feature for use with memories that have
a parity detect option.

Table 1

FACTORY CONFIGURATION

ERROR ABORT

INSTALL JUMPER BETWEEN M24 TO M25

INSTALL JUMPER BETWEEN M23 TO M24

DISABLE ABORT

VCO CLOCK

ENABLE*

CRYSTAL CLOCK

ENABLETM

["\___“__J']

NO JUMPER BETWEEN M24 TO M25
INSTALL JUMPER BETWEEN M26 TO M27
INSTALL JUMPER BETWEEN M28 TO M29
NO JUMPER BETWEEN M1 TO M2

16 BIT = 174400

INSTALL JUMPER BETWEEN M17 TO M20

OR
STANDARD

18 BIT = 774400

INSTALL JUMPER BETWEEN M21 TO M22

ENABLE CRYSTAL

INSTALL JUMPER BETWEEN M20 TO M21

M29

DEVICE

INSTALL JUMPER BETWEEN M1 TO M2

ADDRESS

INSTALL JUMPER BETWEEN M11 TO M12

22 BIT = 17774400"

O w28
ENABLE

INSTALL JUMPER BETWEEN M17 TO M20

VCO CLK

INSTALL JUMPER BETWEEN M21 TO M22

M27 M26

MEMORY PARITY ERROR

INSTALL JUMPER BETWEEN M20 TO M21

INSTALL JUMPER BETWEEN M3 TO M6

STANDARD

VECTOR

160

X TEST POINT

INSTALL JUMPER BETWEEN M7 TO M8

ADDRESS

M30

M12 - A3

M24

M13 - A4
W3

M25

M14
. A5

*FACTORY CONFIGURATION

DEVICE
m;:g
ADDRESS
PINS

STANDARD REGISTER ASSIGNMENTS

M10 M3 M8 M7 M6 M5 M4 M3
V8 V7 V6 V5 V4 V3 V2 VECTOBUSH

M17 - AB

16 BIT

| 18BIT

M21 - A12

174400 | 774400 |

BUS ADDRESS

174402 | 774402 | 17774402

DISK ADDRESS

174404 | 774404 | 17774404

;)

17774412

RESERVED 2

17774414

RESERVED 3

17774416

16 BIT MODE

£23

17774400

RESERVED 1

PASS CD PRIORITIES

JUMPER

{CDMG, CIAK)

ASSEMBLY

18 BIT MODE

ENABLE

22-81T ADDRESSING
MR

Figure 3

22 BIT MODE

160000-177770

760000-777770

|17760000-17777760

0-774

VECTOR

M22-- GND

174406 | 774406 | 17774406
17774410

BUS ADDRESS EXTENSION

ADDRESS

| 22BIT

CONTROL/STATUS

MULT!-PURPOSE

- A1T
M20

ADDRESS
REGISTER NAME

cesmiEn

Mi1g-A9

mM19-A10

CONFIGURABLE RANGES|

ABORT SELECTION

M11-+5v
|9 M23

INSTALL JUMPER BETWEEN M6 TO M7

Table 2

)

NO JUMPER BETWEEN M23 TO M24

ENABLE ABORT”

MEMORY PARITY

JUMPER LOCATIONS

JUMPER CONFIGURATION

DESCRIPTION

FUNCTION

Figure 2

(¢

1421

VECTOR CONFIGURATION
10

{velv?|ve|]vs{valval|v2a]

Figure 1
21

ADDRESS CONFIGURATION
14

[TTTLLLT] 1
\

FACTORY
a3

A4 | A3

NEEERNY

FOR 18-BIT
ADDRESSING

{CONNECT M1 TO M2}

A12] Al lATO[ AS l AB
s

BANK SELECY 7

22-BiT ADDRESSING

3!2‘

M20

MT12

MIB

M17

M1s

MIS

MI4

mi3

o
({

CONFIGURATION
160

i i 1 1 1 1) T

[

INTERRUPT VECTOR PINS

MI12

CONNECT TO PiN M3 TO DECODE A LOGICAL ONE.

BUS ADDRESS PINS

NO CONNECTION DECODES A LOGICAL ZERQ.

CONNECT TO GROUND (PIN M22) TO DECODE A LOGICAL ONE. CONNECT
TO +5V {PIN M11) FOR A DON'T CARE (X} CONDITION. NO CONNECTION
DECODES A LOGICAL ZERO.
MR.3749

MA-5750