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March 1979

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Document:	VAX-11/780 RH780 Massbus Adapter Technical Description
Order Number:	EK-RH780-TD
Revision:	001
Pages:	139
Original Filename:

OCR Text

SRR, -

(Tt 3IRYEONRYY:

o SATHO NSNS

EK-RH780-TD-001

RH780 Massbus Adapter
Technical Description

digital equipment corporation « maynard, massachusetts

First Edition, March 1979

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS

0S/8

PDP

DIBOL

DECUS

EDUSYSTEM

RSTS

UNIBUS

VAX

RSX

VMS

IAS

CONTENTS

e
B

BUS

Parallel

Sync

s wih -

W OO Ja U

Clock

Drive

(SCLK),

Write

Clock

BUS

Parallel

Control

Select

Controller

(DS<K@2:2@>)

Drive

(CTOD)

(RS<04:20>)

(TRA)
Transfer
Attention (ATTN)
Initialize (INIT)
FAIL
COMMAND

Paths

Occupied
(OCC)
End of Block (EBL)
Exception (EXC)
CONTROL

Data

RUN

INITIATION

Nondata Transfer Commands
Data Transfer Commands
READING AND WRITING REGISTERS
DATA

TRANSFER

(WCLK)

AUVt
B WWwwWww wwwN

Ut
Y

[

DATA

MASSBUS

DD N

INTERCONNECT

MASSBUS AND SYNCHRONOUS BACKPLANE

i
I

Device

Massbus

Write Check Data Transfer
Read From Massbus Device
Data Transfer Rate
2

e
e
e
s

bt b

TRANSFERS

DATA

Registers

—

Write

Write to External Registers
Read Internal Registers
Read External Registers

Path
SBI OPERATIONS
Write to Internal

RO OCOWOOT
D ND LN NV

Data

NN
N

W N

MBA/SBI Interface
MBA Internal Registers
Control Path

ADAPTER

D wWwN

AU
D BWWWwWWwwwwwwwhoNNdNDdNbNbDND
-

(SBI)

NN MONNDNDNODNDNODNNDDNDNNDD
NN

e
e

[

e b
e b
.

DD WWWW W

b
b
e

o
«
L]
@
*
L]

Interconnect

Massbus

S S D

Related Documentation
MASS STORAGE SUBSYSTEMS
Synchronous Backplane

MASSBUS

GENERAL
Scope

MBA

CHAPTER
NN DN NDONDNDNDNDNDNDNDNODDNDNDN

INTRODUCTION

MASSBUS

bt et b

N -

)

CHAPTER

(Cont)

CONTENTS

Page

2.7

MASSBUS

2.8

SYNCHRONOUS

2.8.1

o
o

WN
B

o
o

SBI

o
o

DESCRIPTION

Synchronization

Single

2.8.3
2.8.4

2-7

INTERCONNECT

Derived Time States
Transmit Data
Receive Data

2.8.1
2.8.2

DESCRIPTION

BACKPLANE

Interconnect

2.8.1

2.8.1
2.8.1

PHYSICAL

Time

2-11
2-11
2-11

2-11

States

Summary

Arbitration

Group

Information

Transfer

2-11

Functions

Group

and

Assignments

Description

2-11
2-13
2-16
2-17

2.8.4.1
2.8.4.2

Parity Field
Tag Field

2-17

2.8.4.3

Identifier

2-21

2.8.4.4

Mask
Response

2.8.5

2.8.5.1

2-18

Field

Field
Group

2-22

Description

2-23

2.8.5.2
2.8.5.3

Confirmation Codes
Response Handling
Successive Cycle Confirmation

2-23
2-23

2.8.5.4

SBI

2-24

2.8.5.5

Sequence

Fault

2.8.6
2.8.6.1

Detection

Interrupt

Request

Interrupt

2.8.6.2
2.8.6.3

Timeouts

2-25
Group

Description

Operation

Status Register Alert
Alert Flag Operation
Command

2.8.7

Code

2.8.7.1

Read

2.8.7.2
2.8.7.3

Extended
Write

2.8.7.4

Extended

2.8.7.5

2-29

Masked

2-32

Function

2-33

Function

Write

Interlock

2-32

Function

Read

Masked

Function

2-25

2-28
2-29

Flags

Description

Masked

2-24

2-35

Function

2-38

Description

2-42
2-43

2.8.8
2.8.8.1

Control
DEAD

Function

2-43

2.8.8.2

FAIL

Function

2-43

2.8.8.3

UNJAM

INTERRUPT

3.6
3.6.1

3.6.2
3.6.3

PROGRAMMING

NOTES

CONDITIONS

TERMINATION

MBA

W WwWwwWwwWww
Wi
!
I
VUV WWNN -

3.4
3.5

DATA

TRANSFERS

REGISTERS

Configuration
Control

Status

3.6.4
3.6.5

Virtual

Address

Count

(BCR)

3.6.6

Diagnostic

(DR)

Byte

(CRS)

(CR)
(SR)

(VAR)

DEFINITIONS

SPECIFICATIONS

WUNO

GENERAL

3.2
3.3

AND

3.1

DEFINITIONS

PROGRAMMING

2-43

Function

W
w w

CHAPTER

Group

CONTENTS

(Cont)

Page

Selected MAP Register (SMR)
Command/Address Register (CAR)
MAP
DRIVE

MBA FUNCTIONAL/LOGIC

SBI

Control

N -

[]

and

Data

(Overview)

Transceivers

(MSIA,

Parity Error Checking (MSIC)
TAG Decoding (MSID)
Address Validation (MSID)
Function Decoding (MSID)
MBA BUSY Generation Logic (MSIE)
Confirmation Logic (MSIJ, MSIM)
Response Generation (MSIM)
Confirmation Check (MSIJ)
Interface Fault Assertion
Request Logic (MSIK)
Timeout Logic (MSIH)

OO 0000
D

NN NODNNDMNDNDNDDNDDNDDNDNDDND

Command/Address Generation
MASK Decoding

Internal

.
[
o

DESCRIPTION

MSIB)

3-19

CALCULATIONS

MBA/SBI INTERFACE
SBI Decoding and Validating
Timing (MSIR)

wN
=

o
o

o
s

3-19
3-19

Registers

GENERAL

[

g S

CHAPTER

3-19

Bus

and

Interrupt

(MSIM)

Summary

Read

W
-

MBA

[

S
N
.

~N 3
o

[
=Y
fte

D
1N

Registers

DATA PATHS
Command Condition (MDPA)
Internal Bus Receivers/Buffers
Data Input Buffer Enable (MDPD)
Silo and Control Logic (MDPF, MDPH)

Data

Output

(MDPJ,

Address

Diagnostic

Command/Address Generation
Byte Counter Register
Output Data Multiplexers

[]
®
e

W Www
W

Virtual
MAP

B DWW

o
o

LN,
[)

TS
SO
S

INTERNAL REGISTERS
Internal Bus Receilvers
Internal Register Control

Configuration, Control, Status,
and Command/Address Registers

s
W
-

Www
ww

MBA

Logic

Buffer

and

Control

Logic

MDPM)

Internal Bus Output Multiplexers
Massbus Cutput Multiplexers and
Parity Generator
Write Check Logic

(MDPR,MDPS)

CONTENTS

(Cont)

L
[T

D wWN
-

MBA

ST T

nWn

Page

CONTROL

PATH

Internal

Bus

Data

Transfer

Massbus
End

4-44
Receivers
Control

(MCPA)
Logic

4-44

(MCPB)

4-44

Receiver/Drivers

Data

Transfer

Logic

4-5¢
(MCPA)

4-51

FIGURES

Typical Mass Storage
MBA Block Diagram
Virtual

Address

Massbus

Interface

—

Fault

Page

OO JAau; b WK~ W
NS

Write

BwW

Title

NDNDNNDNNDNODNDNDNNNDNON
P
II I
I
T
|

No.

Figure

SBI

Time

Transmit

Subsystem

Translation

and

Phase

Data

Path

Relationships

Receive

Data Path
SBI Configuration
Parity Field Configuration

Command/Address

Format

Control

Space

Read

Address

Data

Interrupt

Mask

Format

Fault

2-21

Timing

2-22

Flags

2-26
2-26

Confirmation

and

Level

Interrupt

Formats

Format

Status

Alert

2-20

Summary

Field

Request

Assignment

Formats

Fault

and

Nexus

Operation

Status

Decision

Flow

2-27

Identification

Timing

and

2-28

Flow

2-30

Bit

2-31

SBI Command
Read Masked

Codes

2-32

Read

Timing

Function

Masked

Extended

Read

Format

Function

2-34

Format

Extended Read Timing Chart and
Write Masked Function Format

Write

Masked

Timing

Extended

Write

Extended

Write

Chart

Masked
Masked

Configuration/Status

and

Byte

Address

Count

(BAR)

Diagnostic

(DAR)

MAP

Registers

2-35
2-36

Flow

2-38

Flow

Function Format
Timing Chart and

Control Register (CR)
Status Register
(SR)
Virtual

2-32

Chart

(CSR)

2-39

Flow

2-40
2-41

3-5
3-8
3-19

(VAR)

3-15

3-16
3-17

3-19

(MSID)

Validation

Functioning

Simplified

Decoding

Block

Diagram

(MSID)

Address

(MSIC)

Decoding

MBA BUSY Generation

Response Generation

Confirmation

Check

(MSIM)

Internal Bus Drivers and
Read Data Logic
MBA Internal Registers

Internal

Bus

Virtual

Address

Internal

Summary

Control

Output Multiplexers and
Data

Interrupt

Receivers

MAP Registers
Command/Address Format
Byte Counter Register
MBA

—

Tag and ID Generation
Mask Decoding

Request Logic (MSIK)
Timeout Logic (MSIH)
Mask Generation (MSIM)

Internal

Select/Enable

Logic

Paths

Bus

Receivers/Buffers

Data Input Buffer Enable
MBA Silo
Data Output Buffer and Control

Logic

Internal Bus Output Multiplexers
Massbus Output Multiplexers and Parity
Generator

Write Check Logic
MBA Control Paths
Data Transfer Control

Internal Bus Data

Generator

Logic

Massbus Control

Path Data

Check

Massbus

End

(Received

Data

Transfer

NN UODDNHRIWOI

Check

Logic

Vil

Registers and

Data)

Parity
Parity

Tag

Timing

Internal
Parity

MBA Block Diagram
MBA/SBI Interface

Y
Q
1)

Title

No.

O IS
DS S DD
[T
!
|
[
|

OO0
o D W

[

Figure

(Cont)

FIGURES

TABLES

Documentation

Massbus Signal Cable
SBI Field Summary

MBA

Registers

MBA

Base

Diagnostic

(CR)

Bit

(CSR)

Bit

Assignments

(DR)

Bit

Internal

Data Input Buffer Enable
Function and Direction Select
Massbus Transmit Enable Signals

Bus

Assignments

Conversion

Address

Output

Multiplexer

viii

Bit

Assignments

(SR)

HOJowW

E
A

Status

W WW

Assignments
Control Register

Drive

Definitions

Addresses

Types
Code

Data

Confirmation

Read

Designations

B W N

[

W N

WWWWNN
NN -

Title

CHAPTER

INTRODUCTION

1.1
The

GENERAL
RH780
Massbus

Adapter

(MBA)

1is

the

interface

between

the

(SBI) and Massbus storage
Synchronous Backplane Interconnect
devices
(disk and tape). The RH780 is used with the VAX-11/780

processor

memory.

can be
1.1.1

The

transfer

processor

used with up to

data

can

between

mass

accommodate

eight drives.

storage

devices

seven

and main

MBAs.

Each

resource

and

MBA

Scope

This manual is intended to be
field reference guide for the

used as a training
RH78¢ MBA.

1.1.2
Related Documentation
Table
1-1
lists
related documentation
information in this manual.
Table

1-1

Title

that

supplements

Documentation

Document Number

RH780

Set+4

B-DD-RH784%

RPO5/RP@6 Device Control
Logic Maintenance Manual+

EK-RP@#55-MM

RP@5/RP(6 Disk Drive
Installation Manual*

EK-RP055-IN

Digital

Logic

#58.63173.2505

Memorex

RP@5/RP#5

Operation

Handbook*

and

Maintenance

Manual+

Memorex RP@S5/RP@5
5677-91/677-51 Disk
Storage Drive Illustrated
Parts Catalogue+
Memorex
Disc

RP@5/RP#6

Storage

Tester

EK-RPO5M-MM

EK-RPA5M-IP

809

Subsystem

Operator's

Manual+

Memorex RP@#5/RP0O5
5677-91 Logic Manual+t

EK-RP@5M-OP

EK-RPA5M-TM

VAX-11/789
Architecture

Handbook*

VAX-11/788 Central Processor
Technical Description+

EK-KA78@-TD

the

Table

1-1

Documentation

Title

(Cont)

Document

System

VAX-11/780@

Installation

Manual*

EK-SI780-1IN

Diagnostic

VAX-11/78@4
System

Number

User's

Guide*

EK-DS7803-UG

TE16/TE10W/TE10N
DECmagtape

Transport

Maintenance

Manual+4

EK-TE156-MM-

TE156/TE10W/TE1ON
DECmagtape

User

Transport

Manual*

EK-TE16-0P

Tape

TU45A Magnetic
Subsystem

Maintenance

TM@3 Magnetic Tape
Formatter Technical

Formatter

User's

Manual+

Manual*

Technical

Manual+

RM@3

Drive

Disk

Maintenance

1.2

MASS
1-1

beyond

the

Set+

STORAGE

scope

data.

mass

Logic

(DCL)

device

disk)

this

Synchronous

SBI

between

the

central

(drive)
is

Backplane

The

synchronous

SBI

with

can

and

1its

presented

device

MBA

defined

Drive

1is

various

the

subsequent

Control

the

basic

paragraphs.

(SBI)

path

for

memory,

and

checked,

system

1-2

the

with

explanation
in

provides

common

detail,

associated

Interconnect
(CPU),

subsystem.

used

Massbus

1information

processor

storage

discuss,

that

interfaces.

bidirectional

system.

mass

manual

subsystem

1.2.1

exchanges

typical

formatting
the

The

VAX-11/780

and

Throughout

copy.

this manual

(tape

storage

components

ER-RM@3I-MP

SUBSYSTEMS

1illustrates

configurations

store

EK-TM@3-0P

ER-RM@3-TM

* Hard copy only.
+ Microfiche and hard

Figure

EK-TM@3-TM

Drive

Disk

RM@3

EK-TU45A-TM-

Tape

Magnetic

TM@3

Manual+

data

parallel

clock.

exchanges

adapters

the

information

MEMORY

CPU

<SYNCHRONOUS BACKPLANE INTERCONNEFF>
MASSBUS
ADAPTER

MASSBUS

DRIVE «
7

| _ _ _ _

DRIVE
0

*NOTE: UP TO EIGHT
DRIVES MAY BE
USED PER MBA
MA-1735

Figure

A communications

such

multiplexed

simultaneously.

1-1

Typical

protocol

that

allows

several

each

Mass

clock

Storage

the

data

period

Subsystem

information

path

(or

the

exchanges

can

cycle)

time

progress

cycle's

interconnection arbitration, or information exchange, and transfer

confirmation
in

about

information

exchange

two

cycles

ago

can

occur

parallel.

Every

checking
signals.

and

SBI

signals

are

clocked

subsequent decision making

Error

checking

logic

reports single bit failures in the

1-3

every

into

data

latches.

All

SBI

device

detects

and

is based on these latched

information path.

The

SBI

has

the

following

Distributed
200

arbitration

bus

cycle

width

data

32-bit

bits

following

time

physical

13.3 megabyte
The

characteristics:

address

maximum

terms

are

data

space

transfer

defined

for

rate

SBI-specific

units

and

operations:
a.

Nexus

or
b.

all

physical

connection

the

functions

Commander

—--

nexus

the

described

that

SBI

capable

b --

any

transmits

command

and

address

recognizes

command

and

address

requires

information.
C.

Responder

information

which

that

directed

and

response.

Transmitter

Receiver

nexus

that

drives

samples

the

and

signal

lines.

examines

the

signal

lines.

Massbus

1.2.2
In

the

MBA.

VAX-11/780

The

system

Massbus

1is

control

bus

exchange
drives.

control

bus

provides

The

data

plus

parity

transferred

Only
rate

and

the

composed

data

bus.

Massbus

two

These

independent

information

bit)

connects

separate,

and

data

bidirectional,

between

synchronously,

the

using

buses

between

parallel

MBA

and

clock

the

drive

independent
allow

for

the

MBA

and

its

path

(16

bits

the

data

1its

drives.

generated

the

buses:

Data

the

1is

drive.

one drive can transfer data at any one time, with the datsa
being drive dependent, and the data bus dedicated to a single

drive
for
the
duration
of
a
data
transfer
operation.
The
asynchronous control bus provides the parallel control and status
path

(16

and

write

bits

plus

registers

transfer

data

1.3

MASSBUS

The

MBA

over

the

Massbus
device
interface
board,
board,
and
diagram
of

parity

within

the

data

ADAPTER
interface

The

drives

control

and

bus

other

command

SBI

and

used

the

read

drives

bus.

between

the

(disk
and
tape).
It
consists
an
internal
registers
board,

a
data
path
the
MBA.
A

interface to the
between them.

bit).

the

board.
Figure
1-2
tristate
internal

boards

and

provides

1-4

the

,
high-speed

of
an
SBI/MBA
a
control
path

is
a
simplified
block
bus
connects
the
SBI

for

the

passage

data

'
|

<Il:

INTERFACE

——

SBI BUS

CONTROL
PATH

BATA

DATS

MASS BUS

! INTERNAL BUS !

MASBUS ADAPTER

INTERNAL

REGISTERS

N4
MA-1736

MBA Block Diagram

Figure 1-2

The

MBA

accepts

status

necessary

will

and

CPU

executes

changes and
command

what

registers,

kind of a

Special

thereby

transfer

diagnostic

from

the

CPU and

reports

the

write

within

the

transfer

and

read

knowing

when

is.

features

are

built

begin

into

the

on-line diagnosis of the MBA and Massbus drives.
features

the

The
MBA
transfer

The Massbus data
handled

The

data

hardware

allow

maximum

data

The following are

MBA.

The MBA

fault conditions to the CPU.

The MBA always monitors the data written to

MBA or within a drive.
drive

commands

silo

handles
speed of

the

a
1

Massbus
drive
us per 15 bits.

path

MBA.

(32-byte

deep

with

15-bits wide;
data

buffer)

18-bit data
smoothes

out

transfers between the SBI and the Massbus drives.
MBA

can

with no drives

exercised,

the

through

Massbus.

1-5

diagnostic

is not
data

features,

1.3.1
The MBA

cycle.

MBA/SBI Interface
examines
the
information

receiving

contains

decoding
sources

1.3.2
There

nexus,

logic

and

are

the

are

physically

the

accordingly.

SBI

The

preliminary

internal

for

decides

SBI

every

SBI

interface

SBI

The

eight

monitor

also

control

the

timing signals

from

the

MBA

internal

located

the

MBA address

space:

registers

are

MBA.

external

The

the

Massbus

converting

data

eight

internal

registers

the

operating

internal

status

such

conditions.

certain phases of data

device,

and

registers

internal

that

registers

are

256

32-bit

control

The

internal

wvirtual

maintaining

addresses

byte

The

the

MBA

registers

count

physical

addresses

ensure

for,

and

that

read

in memory.

follows:

RS = 00

MBA Configuration/Status

MBA

Status

MBA

Virtual

Address

RS
RS
RS

=
=
=

@4
g5
@6

MBA Byte Count Register (BCR)
MBA Diagnostic Register (DR)
MBA Selected Map Register (SMR)

MBA

RAM.

transfers between the SBI and

timing

registers

that all of the data to be transferred has been accounted

The

board

command/address

SBI.

function

and

write

bus

if the MBA is the

in the Massbus drives and are drive dependent.

are

primary

acts

accomplish

MBA Internal Registers
two sets of registers

external.

located

and

generation

and

There

It checks the parity of the data,

internal

registers

Control

Command

are

listed

Address

(CSR)

(CR)

(SR)

(VAR)

(CAR)

NOTE

Registers

registers

and

are

read-only

are valid only during data

transfers.

The

maps

MBA

physical

from

contains

virtual

2556

addresses

addresses.

contiguous

The

32-bit

RAM

(bits

from the virtual
mapping

noncontiguous

21--30

address

registers

allow

physical memory.

1-6

read

into

transfers

SBI
or

1.3.3

The

Control

control

path

the Massbus

device

and

handles

devices.

device

determine

(read,

Path

the

write

transfer

contains

the data

write,

control data

and

transfer

check).

The

1logic

control

1.3.4

Data

Path

The

data

path

controls

and

from the Massbus device and the SBI.

32-bit

SBI

input

function.

path
a

SBI

When

check

into

and

performing

two

the

format.

smoothing

write

word

Massbus

assembles

32-bit

for

data

the

manner

its

read

8-bit

from

bytes

silo

and

circuit

that

allows

of a preceding data

transfer

I/O

the

function.

1-7

the

and

from

Massbus

transfer

any)

path

performed

also

coordinates

the

SBI activity.

data

transferred

These circuits divide
segments

when

the

buffer

The data

user

required

performing

Massbus

from

data

rate.

the

bytes)

data

select

(if

which

devices

the data

16-bit

perform

function

function with other MBA and

the

control

device,

the

write

Massbus

into

provide

the

data

the

means

path also contains
verify

the

accuracy

1.4
An
SBI

MBA SBI OPERATIONS
write operation
1is specified

SBI

the

SBI

cycles.

MBA or
The

Massbus
first

cycle

second

cycle

contains

SBI

read

operation

Massbus

device

the

SBI

cycles.

The

device.

the

data

contains

the

transfer

from

the

requires

two

command/address;

the

transfer

word.

specified

first

This

SBI.
cycle

SBI

read

data

transfer

from

operation

the

MBA

requires

two

MBA

command/address

specifying a read operation.
register
contents.
Several

The MBA then
SBI
cycles

accesses the
later,
the

arbitrate

and

requested

the

CPU.

The

MBA

use

the

SBI

accepts

The

following

paragraphs

wvarious

functions

the

described

1.4.1

SBI

Write

data

aligned

send

only

writes.
the

for

detail

Internal

(one

decoded,

MBA)

The

bits)

data

back

reads

and

description

basic

These

functions

will

this manual.

Registers

checked

whose

MBA

(32

provide

supports.

later

command/address

the

MBA

constantly

transceivers.

longword

the

requested
MBA
will

address

by
1is

the

latched

section

decodes

MBA.

within

in
of

the

the
the

When
range

SBI/MBA
address

valid

recognized

interface

range

which

selects
registers
internal
to
the
MBA.
If
the
function
to
be
performed is a write, and the MBA's SBI interface is not busy, the
command will be accepted. The selected register address is latched
in the
internal
register board.
The next SBI cycle will
contain

the data to be written.
to

the

internal

is then passed

board

and

through the

written

into

internal
the

bus

selected

register or map. Certain registers can be written when the MBA 1is
processing
a data
transfer;
however,
most
registers
cannot.
Any
attempt

write

Programming

Error

not modify the
will continue.
A

confirmation

received

1.4.2

Write
and

has

the

not

status

and

the

decoded

External

internal

registers,

the

allowed

data

validated

set

The

transfer

transmitting

and

will

MBA

progress

device

and

the
will

the

that

the

data

has

Registers

processing

function

1is

except

the

same

address

command/address

that

specifies

for
a

for

write

within

device.
The
MBA will
not
accept
another
SBI
command
write
to
external
register
function
is
complete.
All

command/address
drivers as they
1is
and

and data
words are applied
to
are latched in the SBI interface

made
data

available
paths

via

the

the command/address
(assuming
is performed
satisfactorily),

the

that

informs

been

1initial

write

address

bit

signal

external

paths,

correctly.

Receipt

a
Massbus
until
the

(PGE)

intended

command/address
been

control

path

internal

the

internal

bus.

the
internal
transceivers.

registers,
Following

bus
The
control

receipt

the decoding and validation process
the command/address
is loaded
into

bus

receivers,
1-8

then

latched

into

the

control

control
lines.

path

address

storage

When

exchanged,

the

registers

proper

protocol

and

applied

between

the

Massbus

into the control path

is loaded

Data

lines.

path address

the

MBA

and

the

drive

The MBA busy logic

the drive has accepted the data.

then cleared
and
the write
to external
register
function
completed. The MBA is now ready to accept another SBI command.
1.4.3

The

Read

Internal

command/address,

read.

The

MBA

then

and

saves

content.

requester,

the MBA gains
destination.

control

the

MBA

can

transfer

SBI,

data

the

which

selects

sent

received

place,

the

receivers.

MBA

will

control

device

the

SBI

MBA.

the

requested

and

the

data

the SBI,

the

for

the

MBA

handbook

and

the

move

data

bus

data

and

SBI

the

first

strobed

the

and

provides

MBA

for

data

control

the

further

details).

with

prepare

valid

for

the duration of

between

the

eight

quadword:

the

the MBA may
been

one

that

the

Once

1its

selects

path,

control

the

within

the

device

from

has

Massbus

When

been

has

taken

control

path

protocol

internal

the

SBI.

the

and

bus

MBA

gains

its

The

last

one

Once

MBA

this

for

the

time

interrupt

the

loaded

command

will

cause

both

the

drive

transfer.

The

transfer

the

one

the

time

1-9

the MBA will

The

and

from

the

prepare

MBA buffers

command/address,

the

four

last

number

memory

one

the

(this

for

the

have

been

bytes

of data

that

the

transfer

disconnects

from

the

drive

the CPU to

completed.

and

seize

will

Three SBI cycles are needed to

for

drive

memory.

and

specified

informs

The loading of a drive's

the

and

device

bytes

specific registers within
loaded (the programmer's

must

drive

is the control

quadword.

terminated.

and

SBI.

requested data can be transferred

selected

transfers

transferred,

has

data

the

requested

command/address

into

transferred

four bytes of data,

the

1ssues

transferred

Massbus

proper

eight byte quantity is a quadword).
transfer

the

destination.

within a device
control

then

sent

MASSBUS DATA TRANSFERS
1.5
In order to initiate a data transfer,

the

retrieve

the

control

for

that

the

After

then

into

During this time a confirmation signal

indicating

Data

arbitrate

specified

the

is to be read.

which data

address

the

drive,

loaded

information,

accesses

Read External Registers
command/address received from

MBA to

and

1.4.4
If the

the

SBI,

the

arbitrate

it to the specified destination.

destination

Before

first

must

instructs

transfer

the

and validation,

process

acknowledge

comand/address
register's

decoding

internal

decoding

addressed data word
The

after

the MBA to select the

1is

inform

that

the

data

has

bus

transfer

1.5.1

Write To Massbus Device

The

constantly

MBA

monitors

data

sent

the

drives

via

the

Massbus control path. If the MBA sees a write command to a drive,
it will
initialize
itself in preparation for
the transfer
(data
path
cleared).
The virtual
address
supplied
by the program
1is
translated,
via
the
MAPs,
into
a
physical
address.
Virtual
addressing makes data storage appear as if all of the information
transferred

(contiguous
Virtual

place

from
pages).

address

under

address

memory

1is

translation

system

control.

translation

process.

stored

1in

transparent

Figure

1-3

successive

the

user

illustrates

fashion

and

the

takes

virtual

VIRTUAL ADDRESS

17416

9:8

MAP POINTER

312

QUADWORD | BYTE

MAP REGISTERS

DIRECT

RESERVED ALL 0s

TRANSFER

PHYSICAL PAGE ADDRESS

VALID-BIT

DIRECT

TRANSFER

256

SBI COMMAND/ADDRESS

31,30, 29,2827
110

716
PHYSICAL PAGE ADDRESS

1,0
QUAD WORD

ke INDICATES EXTENDED FUNCTION

————— INDICATES THE FUNCTION IS NOT INTERLOCKED
SPECIFIES READ OR WRITE

Figure

1-3

Virtual

1-10

Address

Translation

MA-1737

Bits

through

address

the

data

and

order

use

this

registers

integrity of
set

the MBA.
the

directly

transferred

memory page

through

pointed

the

address

map

(bit

31)

Bits

by the

address

parity

255

through

gquadword

command

issued

the

1in

This value

the physical address.
the

internal

checked

will

the

bit must

byte

silo.

ensure

that

cause

the

map

Invalid

there are no parity errors.

errors

MAP

page

indicates

The valid

specify

into or from the
1s

that

MAP register.

1 through 6 of

virtual

one

the physical

the

address

translation

information

specify

is valid and that

information

bit

in this

bits

the quadword to be loaded
Virtual

address

valid

the

specify

address

Bits

virtual

The MAP register contains

information

virtual

physical

the

transfer

aborted.

Once

the

MBA

of a drive,

sees

it will

write

data
from memory.
MBA's silo.

The

prefetched

The

data

MBA

requests

instructing

specified

data

sending

transfer

location

the

control

then

loaded

into

its data path and begin prefetching

clear

the

1is

command/address

(eight

quadword

MBA.

Memory

will

bytes)

Response

(NR)

memory

the

MBA

respond

Command/address

retransmitted

timeout

Busy

(BSY)

Error

When

memory

until

occurs.

Command/address
retransmitted
received.

will

to memory

until

ACK

Transfer aborted.

(ERR)

Acknowledge

will

to memory

the

from

command/address by issuing one of four confirmation outputs.
No

the

(ACK)

has

Indicates
memory
has
received
command/address correctly.

accessed

the

requested

data,

arbitrated,

codes.

MBA will

the

and

obtained the SBI,

the data will be transferred to the MBA with the

the

its

proper
and

begin

data
go

identification

data

through

another

from memory.
zero

and

the

SBI

and

silo

status

onto

transfer

Eventually
transfer

the

obtain

the byte

will

The

Massbus

(two

the

eight

counter within

complete.

then

bytes

transfer

time)

bytes

the MBA will

1.5.2

Write

Check

has

been

written

from

the

drive

the

write

The

write

that

check

function,

except

the

Massbus

set

and

data

received

1.5.3
The

Read

command

device

1.5.1.

data

Massbus

device
writes

with

data

the

write

This

drive.

device.

the

data

into

integrity

write
in

same

check

compared

mismatch

will

check,

memory.

the

write

then

function

Massbus

verify

During

data

the

MBA,

write

occurs,

instead

the

Massbus

error

bit

aborted.

Device
initiation

the

same

described

will

cleared

and

data

will

selection

and

the

1location

Device

the

buffer

with

the

manner

command/address

circuit

essentially

clocked

check

specifying

the

drive.
1is

drivers.

From

used

compared

processed

path

Transfer

function

from

the

Data

function

1is

read

processed

from

Massbus

Paragraph

satisfactorily,

read

the

from

within

the

from which data
is
to be read
is specified by previous
to the MBA and the drive. Data from the Massbus will then

be loaded
operation

into
will

the Massbus input data buffers and a
be
initiated.
Data
from
the
Massbus

silo
data

input
input

buffers is loaded into the silo one byte at a time. As data is
being
loaded
into
the
silo
from the Massbus,
other
data may be
transferred from the silo to the output buffer registers.
After
the eight bytes are loaded
into
the output buffer
register,
the
MBA

will

are

translated

initiate

write

into

1.5.1.

When

the

output

buffer

1is

the

data

memory

physical

proper

operation.

address

confirmation

1.5.4

Data

The

data

transfer

the

Massbus

arbitration
transfer
MBA

transfer

Transfer

time
of

signals
data

are

will

addresses

Paragraph

received,
1loaded

the

command.

Rate

rate

device.

rates

and

Virtual

described

be
transferred to memory. Once the byte count register goes to @, the
data transfer operation is terminated and the MBA will be ready to
next

cleared

from

The

the

and

memory

drive

memory

determined

transfer

cycle

rate

depends

time.

The

MBA

extended

hex

board

clock

can

cycle

handle

us/word.

Specifications

Packaging

Four

backplane
for cable
Power

Requirements

vdc,

plus
one
paddle
connection
A,

175

Configuration

The

minimum

slot

-5 Vdc, 1 A, 5 W
Total wattage < 180
Operating

slots

card

operating

configuration

consists
of
a
CPU,
a memory,
least one Massbus device.
(A

and

special

diagnostic feature enables the Massbus
to be checked with no Massbus device.)

1-12

CHAPTER

MASSBUS

MASSBUS
2.1
The Massbus provides
drives (Figure 2-1).
ft)

data
bus
following

length;

configuration.

and
a
control
paragraphs.

BACKPLANE

The

eight

drives

Massbus

bus.

These

can

consists

buses

DATA BUS

D <17:00> (DATA)

are

connected

two

DPA (DATA BUS PARITY)
’

0CC (OCCUPIED)
EBL (END OF BLOCK)

EXC (EXCEPTION)
SCLK (SYNC CLOCK)
WCLK (WRITE CLOCK)
CONTROL BUS

< C <15:00> (CONTROL STATUS) >
-

CPA (CONTROL BUS PARITY)

MASSBUS
DRIVE

DS <02:00> DRIVE SELECT

CTOD (TRANSFER DIRECTION)

RS <04:00> REGISTER SELECT >
DEM (DEMAND)
TRA (TRANSFER)
ATTN (ATTENTION)

INIT (INITIALIZE)
FAIL

TK-1109

Figure

Massbus

2-1

sections:

described

RUN (START, CONTINUE, STOP)

MBA

INTERCONNECT

(160

SYNCHRONOUS

interface between the MBA and the Massbus
total external Massbus cable can be up to

daisy-chain

the
The

AND

Interface

1in

the

2.2

DATA

BUS

The data bus section of the Massbus consists of a 17-bit (16 data
bits plus parity bit)
parallel data path and six control 1lines
(Figure

2-1).

The

control

1lines

are

described

the

following

paragraphs.
2.2.1

Parallel

The

parallel

data

path

The

MBA

format

16
bit

and

using

bits

set

18-bit

employs
clock

plus

odd

parity

bus.

The

parity.

Data

1is

generated

time;

thus,

the

drive

control

the

drive.

drive

logic.

must

Bits

unasserted.

always

RUN

After

data

asserts

the

sector,

transfers

16-bit

2.2.2

consists

synchronously,

are

and

path

bidirectional

only

its

Paths

data

1is

transmitted
have

Data

transfer

drive,

RUN

the

strobed

the

for

initiate
If

been

written

connects

edge of

drive.

the

has

drive

trailing

continues

line

command

the

(End

still

into

the

data

function.

EBL

sector;

The

MBA

each

pulse,

RUN

function

1is

the

end

Block)

asserted,

negated,

control

bus.

the

function

terminated.
2.2.3

This

Occupied

signal

soon

the

drive

(0OCC)

generated
OCC.

Various

errors

command.

(Missed

Transfer)

negated

the

where

trailing

set

the

into

can

prevent

timeout

(Sync

last

drive

terminate

time

terminated

busy."

drive,

drive

these

Clock),

the
EBL

from

cases,

and

the

MXF

controller.

OCC

1is

pulse

transfer.

for

operations

for

prior

the

end

each

For certain error conditions,
immediately,

the last SCLK.

the

end

the

MBA

when

EBL

this case,

the

sector.

(EXC)

asserted

occurs

signal

indicate

write,

write check).

and

SCLK pulse).

condition

EBL

SCLK

bus

written

will

the

the normal

Exception
is

necessary

transfer

signal

edge

last

2.2.5
This

will

the

prior

data

"data

(EBL)

asserted

(after

controller

OCC

error

asserted
the

The
of

End of Block
signal

sector

indicate

asserts

assertion

2.2.4

command

This

drive

transfer

executing
no

the

data

due

valid

during
an

negated

the

drive

data

transfer.

error
at

EXC
the

during

data

asserted

negation

2-2

at,

The

drive

transfer

EBL.

prior

abnormal

asserts

command

to,

this

(read,

assertion

2.2.6

Sync clock

These

signals

the

data

operation,

and

the

back

write

are

the

drive

MBA

strobes

2.3

CONTROL

the

drive

the

data

signals

controller

changes

strobes

Write Clock

timing

the

operation,

the

(SCLK),

the

and/or
data

data

controller

WCLK.

lines;

the

(WCLK)

used

the

lines

the

on
an

control

bits

plus

control

read

SCLK

SCLK.

WCLK,

and

WCLK,

During

echoes

the

drive

controller

BUS

bus

section

parity)

lines

strobing

negation

SCLK

assertion

negation

changes the data on the data lines.

The

the

During

assertion of

receives

the

control

drive.

parallel

(Figure

Massbus

control

2-1),

consists

status

data

and

which

are

described

2.3.1
Parallel Control
The parallel control path

consists

designated

17-bit

path

the

(16

and

following

paragraphs.

control

C<15:90>

lines

are

and

15-bit

associated

bidirectional

and

employ odd

2.3.2
These

Drive Select (DS<02:006>)
three lines transmit a
3-bit

select
(unit)

a particular drive.
number in the drive

parallel

parity

bit

parity.

data

path

(CPA).

The

binary code
from the MBA to
The drive responds when the selected
corresponds to the transmitted binary

code.

2.3.3

This

which

Controller

signal

control

controller

drive

Drive

and

status

drive

controller

five

the

(CTOD)

information

transfer,

lines

drive.

the

controller

transferred.

asserts

negates

For

CTOD.

this

For

in
a

signal.

(RS<04:006>)

transmit

selected

the

transfer,

2.3.4

These

is generated by the MBA and indicates the direction

The

5-bit

binary

code

from

selects

the

one

controller

the

drive

registers.
2.3.5

This

Demand

signal

transfer

transfer,

settled
DEM

asserted

take

DEM

(DEM)

1is
is

the

has been

DS,

and

the

strobed

assertion

CTOD lines
of DEM.

2.3.6

Transfer

This

For

signal

MBA

the

bus.

off

the

are

controller

control

the

For

MBA

when

drive
to

request

data

control

bus.

generated

and

bus.

indicate

that

For

MBA

data

present

controller

and

negated

and

transfer,
when

the

RS,

In both cases,

allowed

to drive

settle

before

(TRA)

asserted

drive
and

onto

the

and

negated

transfer,

the

transfer,

strobed
bus

the

MBA

been

controller

asserted

control

asserted

data

place

negated

TRA

selected

TRA

after

is
DEM

is asserted
after

the
2-3

drive

asserted
1is

after

response

after

negated.

negation

the data
of

DEM

the

For

DEM.

data

has

drive

has been gated

received.

2.3.7
Attention (ATTN)
This line is shared by all
be

asserted

status

change

any
in

in each drive
line. ATTN can
1.

drive

the

drive.

drives

result

attached

Attention

abnormal

Active

MBA;

may

condition

(ATA)

status

or
bit

is set whenever that drive is asserting
the ATTN
be asserted due to any of the following conditions.

error

occurring

(asserted

while

data

transfer

taking

place

immediately).

Upon completion of
occurred during the
the data transfer).

a data transfer command
if an error
data transfer (asserted at the end of

Upon

completion

recalibrate,

etc.)

result

states
(except
configuration,
assertion
The

eight
as

ATA bit

mechanical

the

Medium

ATTN

both

drive

can

cleared

INIT on

the

Massbus

Writing

the

attention

into

Writing a valid
the control and
clearing

may

the

also

the

bit

ATA

line

asserting

all

changing

MBA
the

negated,

one

GO
no

actions.

eight

drives).

This clears
error.

bit

the

following

summary

command
(with the
status register if

the

ATTN

(MOL)

(affects

bit position for this drive).
however, it does not clear the

that

Line

MBAs.

Asserting

cause

(seek,

in the unload operation). In the dual
a change
in state of MOL will
cause

command

command.

motion

the

ATA

bit;

bit asserted)
error occurs.

into
Note

drive

the

(in

does

because

not

always

other

drives

line.

NOTE

There

are

three

not

reset

when

the
the

control
GO
bit

cases

command

which

ATA

written

and
status
register
set):
1)
if
there

into

(with
1is
a

control bus parity error
in the write,
2)
if an error was previously set, or 3)

Illegal

Function

(ILF)

code

1is

written.

2.3.8
Initialize (INIT)
This signal
is asserted by

the

MBA to perform a system reset of
when a 1 is written into the INIT bit
a
drive
receives
the
INIT
pulse,
it

all drives.
(bit
@1
of

It is asserted
MBA CR).
When

immediately

aborts

the

performs

actions

described

all

execution
for

any

the

drive

current
clear

command

command.

and

NOTE

In the dual-MBA configuration,
a drive
will honor an INIT pulse only from the
MBA that has seized the drive,
or
from

either controller
unseized

the drive

asserted,

this

has

occurred

and

DEM signals at

2.4
COMMAND INITIATION
To initiate a command in a drive

via

the

CPU

via

the

command

code

and

Commands

are

and

valid

in the

and

check).

The

control

and

29--3F

functions.)

transfer

merely

drive's

commands

writes

the

control

execution,

the

Massbus,

the

control

condition

maintenance

reception

the

nondata
data

the

commands

and

power-fail

MBA

mode.

INIT

(or

the

The

asserted,

the

selected

bit

the

drive.

command.

types:

etc.)

into

transfer

command

for

data

only

are

the

word

(with

the

code

bits

for

commands

state

(such

91--37

transfer

affect

command

commands

function

Nondata Transfer Commands

2.4.1

Nondata

MBA

the

transferred

valid

inhibits

word

are

two

seek,

drive

bit

executes

write

including

transfer

clear,

write,

writes

specified

drive

the

the drive.

MBA)

selected

drive

asserted,

the

function

MBA

that

the

indicates

MBA

FAIL

signal

the

While

are

FAIL

2.3.9
When

state.

the

bit

completion

read,

(#5--04,

nondata

(not

all

drive.

The

into

the

signal

its

set)

the

the drive typically asserts the ATTN line to

command

completion.

the

nondata

transfer

the

recognized

immediately signal
is set.

command

drive

error

code

written

into

the

command,

valid

asserting

the

ATTN

drive

1is

line.

The

not

will

ILF

error

2.4.2

When

Data

any

written

into

transfer

its

OCC

line.

written

Transfer

data

the

BUSY

drive's

The

command

data

bus

soon

bit

into

Commands

transfer

drive.

MBA

The

asserts

from the specified drive,
cylinder) is found.
If

drive

error

occurs

asserts

trailing

edge

the

EXC

the

control

(with

MBA

begin

the

data

transfer

RUN

and

then

data

transfer

drive
after

1line.

thereafter.

normally
the

line

pulse.

2-5

responds

proper

during

This

EBL

soon

the

drive

last

code

MBA

bit

set)

data

The

MBA

sets

command
by

1is

code

asserting

transferred

address

remains

The

expects

(sector,

1is

the

track,

command,

the

asserted until

the

always

negates

the

RUN line when
is
terminated

it
at

detects EXC
the
end
of

asserted, so that the data transfer
the
sector
in which
the
error was

signaled.
2.5

READING

The
via

AND WRITING

REGISTERS

process of reading or writing drive registers
the asynchronous (control bus)
portion of the

the action
RS<94:00¢>

is accomplished
Massbus
(Figure

2-1). The MBA
selecting
a

initiates
register

direction of
register
via

transfer
(CTOD),
and either reading or writing
the
17
bidirectional
control
1lines
(C<15:08¢>

CPA).

After
a
deskew
delay
stabilize, the MBA asserts DEM.

assertion,
checks
write is to occur.

the

operation

contents
TRA.

When

onto
the
negation

read

the

CTOD

specified

MBA

allow

the

The

drive,

upon

line

by selecting a drive DS<@2:00>,
in
that
drive,
selecting
a

receives

TRA,

control

ascertain

specified,

onto

will

1lines
to
receiving the DEM

whether

the

drive

control

gate

read

will

gate

the

bus

the

and

issue

control

1lines

SBI.
After
a
deskew
delay,
the
MBA
negates
DEM.
of
DEM
causes
TRA
to
be
negated
and
completes

operation.
The MBA
the Massbus data to

will
then arbitrate
its destination.

for

the
and

the

SBI

and

The
the

transfer

NOTE

Since
Massbus
drive
registers
are
16
bits wide,
the MBA appends bits 31--16
of
its
status
register
to
create
the
longword
If

write

sent

operation

the

requester.

specified,

the

MBA

control data onto
will transfer the

the control bus when it issues DEM.
data
from the control
bus
into the

drive register and
negation
of
DEM

assert TRA, which causes DEM
causes
TRA
to
be
negated

gates

the

The drive
specified

to be negated.
to
complete

The
the

operation.
The

Massbus

data

structure

transfer

attempt

(on

the

MBA

allows

asynchronous

write

data

for
the

Modification

bit.

2.6

Refused

DATA

Before

data

sector/track
count

are

(RMR)

bus)

data transfer operation
(except
summary
registers)
will
cause

error

read
in

operation

is
a

taking

drive

the maintenance
drive
to
set

while

place.

Any

performing

and
the

a
a

attention
Register

TRANSFER

transfer
address,

specified

takes

place,

cylinder
the

the

address,

program.

The

selected
bus

program

unit,

address,
then

desired
and

word

transfers

the

read or write data transfer command
(with the GO bit asserted)
to
the control
register.
Upon
receipt of the data transfer command,
The

the

drive will assert OCC,
MBA logically connects

RUN

and

then

waits

for

indicating that the data
the Massbus data bus

SCLK

pulses

2-6

from

the

drive.

bus is busy.
by asserting
For

write

data

transfer,

SCLK

pulse

disk

sends

data

sector

asserted

each

causes

words
an

transferred.

pulse

causes

word

transferred

pulse

has

EBL

this

WCLK

logic;

the drive

written onto

been

the

for

time,
RUN

the

line

MBA.

word

read data

the

read
the

sector

negated,

written

into

Massbus.

When

each

transfer,

from

the disk,

RUN

1line

the

data

1is

the

still

words

transfer

1is

terminated.
2.7

MASSBUS

The

Massbus consists

the

cabinet

status,

and

PHYSICAL

parity.

DESCRIPTION

56 signal

These

contains

that

signal

MBA(s)

the

including data,

lines,

lines

are

via

routed

three

control,

externally

BC@#6-R

Massbus

cables.

the

cabinet

(containing

the

first

MBA),

the

BC@6-R

cable

plugs

into the AD-7@15145 connector panel, which is mounted at the lower

rear

the

receptacle

cabinet.

housing

This

connector

assemblies

panel

accommodate

has

cutouts

for

four MBAs

four

and

associated
cabling.
The
other
side
of
the
receptacle
housing
assembly accepts three BC@6-S round Massbus cables. To accommodate
additional MBAs, the BC@6-R cables plug into the 78013678 cabinet

cabinet

verticals

Table

2-1

connector

panel,

the

right

1lists

the

end

which

Massbus

the

is mounted between the cabinet

cabinet.

signals

assignments.

2-7

and

their

associated

Table

2-1

Cable

Massbus

Signal

Pin¥*

Cable

Designations

Polarity

Designation

MASS

D@g

MASS

D@1

MASS

D@2

Massbus

Cable

MASS

D@3

J
K
L

8
)
10

MASS

Dg4

MASS

D@5

N
P

12
13

MASS

C0@

R
S

14
15

+
+

MASS

C@1

MASS

C@2

\'A

MASS

C@3

X
Y

29
21

MASS

C@4

MASS

C@5

MASS

SCLK

MASS

RS3

MASS

ATTN

MASS

RS4

MASS

CTOD

MASS

WCLK

MASS

RUN

277

LL
MM

SPARE

GND

Table

2-1

Massbus

Signal

Pin#*

Cable

Designations

(Cont)

Polarity

Designation

MASS

D@5

Massbus

Cable

C
D
E

3
4

+
-

MASS

D@7

MASS

D#8

MASS

D@9

J
K

8
9

MASS

D193

MASS

D11

N
P

12
13

MASS

C@6

R
S
T
U

15
16

+
-~

MASS

C@7

C@8

MASS

\'
W

MASS

C#9

X
Y

29
21

MASS

C149

C11

+
-

MASS

BB
CC

MASS

EXC

DD
EE

RS#H

28
29
30
31
32

+
-

MASS

FF
HH

+
+

MASS

EBL

MASS

RS1

MASS

RS2

NN
PP

MASS

INIT

RR
SS

35
37

MASS

SP1

TT
uu

38
39
40

JJ
KK
LL
MM

\A'

SPARE

GND

Table

2-1

Massbus

Cable

Signal

Cable

Pin*

Designations

(Cont)

Polarity

Designation

MASS

D12

MASS

D13

MASS

D14

MASS

D15

MASS

D156

MASS

D17

MASS

DPA

MASS

C12

MASS

C13

MASS

C14

MASS

C15

MASS

CPA

MASS

0OCC

MASS

DS#@

MASS

TRA

MASS

DS1

MASS

DS2

MASS

DEM

MASS

SP2

MASS

FAIL

Massbus

Cable

Alternate

—

designation

GND

schemes
NOTE

Massbus cables are to
markings on the cable.

2-10

installed

per

2.8

SYNCHRONOUS

The

SBI

the

interconnects

BACKPLANE

INTERCONNECT

backplane

the

CPU

with

the

memory

DESCRIPTION

VAX-11/780

system

and

system.

all

the
system.
The
following
paragraphs describe all
lines and their associated communication protocol.
Interconnect Synchronization

2.8.1

Six
control
group
lines
are
clock
signals
universal time base for all nexus connected
clock signals are generated on the CPU clock

The

clock

signals,

synchronize

the

basic

PDCLKH,

and

SBI

conjunction

activity.

time

nexus

PDCLKL)

are

driver/receiver

define

period.

The

transmit,

time

states

propagate,

generate

individual

illustrates

the

CPU

SBI T1l.

start

phase

(CPT@)

All

1is

receive

functions.

2.8.1.2

Transmit

asserted

Figure

line.

Receive

Data

latches

are

opened

basic

information

after

may

1is

decoding,

and

latched

(nominal)

and

operation
Nexus

same

produce

PCLKL,

for

the

and

backplane,

time

T2,

times

states

and

period.

CPT@

T@ and T2 for
be

inputs

diagram

case

receiver

for

one

and

undefined

1is

transceivers.

information

path

data,

the

T3.

Figure

1logic.

are

internal

transmitting

wvalid.

making

transmitted

SBI

between

considered

required

the

receive

latch

2-2

corresponds

T@#

latched

the

with

SBI transmit and

SBI

<clock

Figure

Note that

Information

SBI,

relationships

one

determine

the

clock
T@.

the

1in

T3)

the

(within

clocks

derived

SBI

decision

Time

T1-T2,

will

proceed

must

normal

timing

set

However,

Note

nexus

2-4

that

and

the

T3;

only

based

these

states,

the

Nexus

then

single

time

period

T3-T#

and

long

normally.

from

though
an

late

SBI

the

timing

external

and

checking,

2-11

from

SBI

time

operation

implement

the

SBI

cycles.

Memory

source

(e.g.,

these

nexus

remains

overrun
of

vary

time.

that

SBI

operation

normal.

may

Nexus

counting

even

data

the

T2-T3,

indefinitely

derive

device)

appropriate.

States

T@-T1,

functions

that

storage

(PCLKH,

compensate

cable,

Immediately prior

information

Single

any

protocol

timeout

help

signals.

2.8.1.4

between

and

clock

nexus

attached

four

time states.

considered

subsequent

and

timing

one-line

T1,

enable

receiver

the

TPL)

particular

block

2.8.1.3
shows

(TPH

receive

the

transmit

signals

The

a minimum of

basic

its

nexus

due

(T@,

and

standard

clocks

derived

Data

the

remaining

The

SBI at T@.

(nominal)

the

enables

2-3

not

nexus need

within

delays.

and

the

nexus

skew

clock

States

Time

four,

representing
to

phased

propagation

Derived

2.8.1.1

nexus)

Two

states.

distribution

clock

with

clocks

derived

the

provide

logic,

interconnect

that
are
used
as
a
to the SBI. All SBI
module and provide a

period.

200 ns clock

adapters

may be

nexus

different.

error

bits

mass

e Y

PCLKH

100 NS

PCLKL

le——200 NSEC ——]

PDCLKH M

PDCLKL —l__l—l___l—__L_

TPL

L_IIIWIIHII[_
|

PCLKL||||
I

|l'|

ENABLES SBI

TO (DERIVED)

DRIVERS

TPH

| TRANSMITTER NEXUS

[—_lJllllllJL_

—

TPL

]_|!!1JLJLI_
| ALL NEXUS OPEN

T2 (DERIVED)
Ho

[

[11

EE%E:—IVE%R

PDCLKH

T3 (DERIVED)

ALL NEXUS CLOCK

|? I EE%(E::-IVEESR
TK-0165

Figure

2-2

SBI

Time

and
2-12

Phase

Relationships

TRANSMIT DATA—
ENABLED PRIOR

TOTO

TRANSMIT
DATA

—

SBI

TRANSMIT

BUFFER

DATA

CLOCKED AT TO—T
2-3

Figure

TK-0162

Transmit

RECEIVE —-4>_DATA

Data

SBI

RECEIVER

DATA

LATCH

Path

|, RECEIVE
DATA

OPENED AT T2
LATCHED AT T3

Figure

2.8.2
Table

SBI Summary
2-2
summarizes

functional
following
individual

group.

2-4

the

Figure

TK-0163

Receive

signal

2-5

Data

fields

shows

the

Path

associated

SBI

with

configuration.

paragraphs
provide
detailed
descriptions
group field layouts and functions.

2-13

each

The

the

Table

2-2

Field

SBI

Field

Summary

Description

ARBITRATION

GROUP

Arbitration

Field

INFORMATION

TRANSFER GROUP

Information

Field

(TR

<15:98>) | Establishes a fixed priority among
nexus for access to and control of
information transfer path.

(B<31:00>)

Bidirectional
lines
that
transfer
data,
command/address,
and
interrupt
information
between
nexus.

Mask

Field

(M<3:0>)

Primary

function:

encoded

indicate a particular byte
the
32-bit
information

within

field

(B<31:28>)
.
Secondary

function:

conjunction

with
the
tag
field,
indicates
particular type of read data.
Identifier

Field

(ID<4:8>)

Identifies

the

destination

contained
Tag

Field

(TAG<2:0>)

Defines

logical
of

B<31:00>.

the

transmit

Field

(F<3:8>)

Specifies

types

the

receive

and

interpretation
of
the
the ID and information
Function

information

source

command

conjunction
with
the
This field is valid as

the

content
fields.
code,

tag

1in

field.

part

of the
only when

32-bit information field
tag equals command/address.

the

Parity

Field

(P<1:8>)

Provides

even
parity
for
all
information transfer path fields.
P(@)
1s
generated
as
parity
for
the
information
field.
P(2)
1is

generated
ID,

RESPONSE

and

parity

mask

fields.

for

the

tag,

GROUP

Confirmation

Field

(CNF<1l:@>)

Asserted

specify
and

one

indicate

respond
request.

2-14

receiving

nexus

four

response

its

capability

the

types

to
transmitter's

Table

2-2

Field

Fault

SBI

Field

Summary

(Cont)

Description

Field

(FAULT)

A cumulative
that

error

1indicates

line

one

the

CPU

several

errors, stored in the transmitting
nexus
fault
register,
and
the
associated
error

INTERRUPT REQUEST GROUP
Request Field
(REQ<K7:4>)

SBI

cycle

which

the

request

occurred.

Allows

interrupt
requiring

nexus

to
service
a
condition
CPU
intervention.
Each

request
lines
represents
a
of nexus request priority.

Alert

Field

(ALERT)

cumulative

allows

with

CONTROL GROUP
Clock Field
(CLOCK)

those

1line

not

that

equipped

interrupt

mechanism

indicate

power

operating

conditions.

provide

the

Six

status
nexus

level

control

change

lines

that

clock
signals
necessary
synchronize SBI activity.
Fail

Field

(FAIL)

A
single
1line
from
the
restart
nexus to provide a
restart signal
to

the

CPU

restart

Dead

Field

(DEAD)

Field

Interlock

(UNJAM)

Field

(INTLK)

initiate

system

operation.

single

indicate

Unjam

1line

the

CPU

impending

clock

circuit or SBI
power failure.

terminating

network

1line

from

the

attached

nexus

that

initiates

restore

operation.

single

1line

that

CPU

to
a

provides

coordination
responding
to

among
nexus
certain
read/write

commands

ensure

access

shared

data

exclusive
structures.

TRVAVAVAVAV LY

Ve VAV VaYaNra:

ARBITRATION
TR <15:00>

INFORMATION TRANSFER
P <1:0> (PARITY)

TAG <2:0> (TAG)

ID <4:0> (IDENTIFIER)

M <3:0> (MASK)

B <31:00> (INFORMATION)
RESPONSE

NEXUS

RECEIVE

FAULT

TRANSMIT/

CNF <1:0> (CONFIRMATION)

TRANSMIT/

RECEIVE
NEXUS

CONTROL

UNJAM
FAIL

DEAD

VAYS
AV AV

INTLK (INTERLOCK)

CLOCK (6 LINES)

ININTON

INTERRUPT REQUEST
REQ <7:4> (REQUEST)
ALERT

MP1-2

SPARE (2 LINES)

TK-0077

Figure
2.8.3

The

group).

establish
to

Configuration

Arbitration Group Functions and Assignments

arbitration

nexus

SBI

2-5

TROB,

lines

arbitrate
One

for

the

arbitration

the

fixed

where

TR@PF

for

the

CPU,

The

nexus

are

Request

information
1line

priority

reserved
other

(Transfer

access.

the

highest.

and

assigned

Priority
The

2-16

priority

actual

through

each

increases

lowest

allow

(information

assigned

requires
TR15

TR<15:0¢>)

lines

TRd1.

transfer
nexus

from

level

signal

TR15
1is

line.

for those nexus that
The highest priority level, TRE8, is reservedTRA@
may only be used
require more than one successive SBI cycle.

by nexus that require:

Two or three adjacent cycles for a write type exchange.

Two adjacent cycles for an extended read exchange.
Adjacent cycles for interrupt summary read exchanges and

b.
C.

restore operations.

ing 1its
A nexus requests control of the information path by assert
SBI
same
the
of
assigned TR line at TO of an SBI cycle. At T3
cycle, the nexus examines (arbitrates) the state of all higher

lines are asserted, the
priority TR 1lines. 1If no higher TR inform
ation path at T# of
requesting nexus assumes control of the
, the nexus negates
the following SBI cycle. At this T# time statedata
ation on
its TR line and asserts command/address or nge is inform
the
fied,
speci
B<31:048>. In addition, if a write type excha
nexus asserts TR@AP to retain control of adjacent SBI cycles.

can
If higher priority TR lines are asserted, the requesting nexus
1its TR
not gain control of the information path. The nexus keeps
ity
prior
r
of highe
line asserted and again examines the state
TR
higher
no
lines at T3 of the next SBI cycle. As before, 1if

at
lines are asserted, the nexus assumes information path control
Ta.

2.8.4

Information Transfer Group Description

2.8.4.1

Parity Field -- The parity field

ibed in detail in the
Each information group field 1is descration
field (B<31:£0>) is
following paragraphs. However, the inform
described in the context of the other information group fields.
(P<1l:8>)

provides even

parity for detecting single bit errors in the information group
(Figure

2-6).

|l —

| PO
P1

N —

MASK
IDENTI FIELD FIER FIELD FIELD
_
—_——) —> —
>
<3:0
M
<4:.0
ID
>
<2:0
P <1:0> TAG
PARITY

FIELD

TAG

_A
INFORMATION FIELD
00>
<31:
BY
o

J
-~

COMMAND FORMAT

ADDRESS

FUNCTION

FIELD

F <3:0>

A <27:00>
TK-0166

Figure 2-6

Parity Field Configuration
2-17

transmitting

and

M<3:0>.

are

denerated

nexus

The

generates

parity

bit

such

that

the

sum

checked
field,
including
the
transmissions, the information
state;

thus,

transmission

P<1:8>

with

odd

2.8.4.2
Tag Field
by a
transmitting

conjunction

and

write

Command/Address

the

content

asserted

source

Tag

this

--—

time,

divided

into

the

command

and

write

type

and

destination.
the
ID

For

sent

with

SBI

always

parity.

carry

considered

even

zeros
Any

error.

(TAGK2:0>)
is asserted
the
information
type
being
The tag field determines the

associated

for

the

read

unique

field

code

command.

function

describe

6——FFFFFFF

each

content.

field

type

identifying

shown

field

associated

the

read

paragraphs

field

and

1in

the
logical
Figure
2-7,

address

field

address.
code

represents

specifies

the

logical

logical
command

command,
the
addressed
nexus holds
with the requested data.
The

transmission
data

indicate

destination.

The
28
bits
of
the
SBI
address
field
define
a
268,
longword
address
space,
which
is
divided
into
two
Addresses @--7FFFFFF
are reserved for primary memory.

80203002

all

field

following

address

transmitted

With

and

its

command,

the

bit,
is
even.
transfer path assumes

parity

the

B<31:90>

Pl
the

tag
field content of @11
indicates that
1is
a
command/address
word.
ID<4:0>,

specify

source

and
in

The

code,

B<31:00>

(commander)

logic

ID<K4:0>,

ID and B fields. In addition, the tag field,
the mask field,
further defines special read

tag

TAG<2:0>,

B<31:948>.

bits

-- The tag
to
indicate
information lines.

conditions.

type,

all

nexus

with

data

information

for

one

should

parity

generated

Formats

transmitted on the
interrelation of the

reserved

for

device

control

435,

454

sections.
Addresses

registers.

Generaliy, primary memory begins at address @; the address space
is

dense

address
type.

and

space

Each

consists

only

1is

with

nexus

sparse
is

for
control.
The
number as shown in

assigned

of
storage
elements.
The
control
address assignments based on device

addresses
Figure

2¢48,

32-bit

assigned

are

longword

address

determined

2-8.
B <31:00>
o

TAG

TAG <2:0>

ID <4:0>

MASK

FUNCTION

ADDRESS

M <3:0>

F <3:0>

A <27:00>

TAG <2:0> = 011 = COMMAND/ADDRESS FORMAT

ID <4:0> = LOGICAL COMMAND SOURCE

M <3:0> = COMMAND DEPENDENT
F <3:0> = COMMAND CODE
A <27:00> = READ/WRITE, ADDRESS OF INTENDED NEXUS
TK-0167

Figure

2-7

Command/Address

2-18

Format

space

the

SPECIFIES ONE OF THE

SPECIFIES ONE

2048 LOCATIONS

OF 16 NEXUS

ASSIGNED TO EACH NEXUS

27 26

15 14

F_N_\f

1110

MUST BE ZERO

TR# (ADDRESS

SPACE BLOCK)

ADDRESS

A <27:00>
TK-0168

Figure

2-8

Control

Address

Space

Assignment

000.

LOGICAL
DESTINATION

0000

ERROR-FREE DATA

TAG <2:0>

ID <4:0>

M <3:0>.

B<31:00>

pesTinaTion ||

TAG <2:0>

000

ID <4:0>

0001

CORRECTED DATA

M <3:0>

B <31:00>

0010

UNCORRECTED DATA OR OTHER

|fLoGICAL
DESTINATION

TAG <2:0>

MEANINGFUL INFORMATION

ID <4:0>

M <3:0>

B <31:00>
TK-0169

Figure

Read

Data

Tag

Read

2-9

Data

tag

field

is a

unique code

Formats

content

@0¢

indicates

that

B<31:08> contains data requested by a previous read type command.
In

this case,

read

command

ID<4:¢>

and

requested

data.

The

particular

type

identifies

retrieved

the

data

that was

logical
may

received with the

destination

one

three

the

types:

read data; corrected read data; or read data substitute, where the
identified

by M<3:0>.

Read data is the normally expected error-free data having M<3:8> =
#P0@

(Figure

of the tag

2-9).

Note

that

this tag

code

is also

field and that ID code 4 is reserved.

respond when the tag

is @#¢ and

the

2-19

ID code

is 0.

the

idle state

No device will

Corrected
read
data
is
data
subsequently corrected by the

the
device
field flags

in which an
error
was detected
and
error correction code (ECC)
logic of

transmitting
the
read
data.
In
the corrected data with M<3:0> =

this

case,

the

mask

gggl.

Read
data
substitute
represents
data
in
which
an
error
was
detected
but not corrected.
In
this case,
B<31:8¢> will
contain
the
substitute
data
in
the
form
of
uncorrected
data
or
other
meaning
ful information. The mask field
flags the uncorrected data
with
M<3:8>
=
@@10.
As
with
the
other
read
data
types,
the
ID
field identifies the read commander.

Write

Data

B<31:00>

Tag

contains

the

address
field
of
write
data
will

the

tag

field

write

data

content
for

1#1

indicates

that

the

location specified in
command
(Figure
2-17).

write

the
The

be
asserted
on
B<31:0#>
in
the
SBI
cycle
immediately
following
the command/address cycle.
Certain command
codes use M<3:#> to specify particular bytes within B<31:0¢>.

101

LOGICAL
SOURCE

MASK

WRITE DA TA

TAG <2:0>

ID <4:0>

M <3:0>

B <31:00>
TK-0170

Figure

Interrupt

B<31:08>

Summary

command.

the

The

interrupt

Tag

2-19

Write

tag

interrupt

1level

level

mask

being

serviced

The

for

content

the

ID
field
Although

11@

interrupt

sequence

first

consists

exchange

two

indicates

defines

summary

read

the

used

indicate

result

identifies

unused,

interrupt

the

commander,

M<3:8>

zero.

interrupt

The

Format

field

mask

(B<@7:74>)

request.
In
this
case,
the
which
1is
wusually
a
CPU.

transmitted

Data

must

exchanges:

the

interrupt

level

being

the

device

serviced.

The

second

requesting
The

interrupt

Figure

2-11.

TAGL2:0>

Reserved

Tag

diagnostic
reserved

exchange
the

summary

Note

interrupt

read

that

and

the

the
response,
where
identifies itself.

response

interrupt

formats

are

summary

illustrated in
response
encodes

000.

Codes

purposes.

for

future

TAG<2:8>

Tag

codes

@@#¢1,

definition.

2-20

Tag

code

@910,

and

111

180

reserved

are

unused

for

and

FIRST EXCHANGE:

INTERUPT SUMMARY

READ

TAGL2:0>

SECOND EXCHANGE:

INTERUPT SUMMARY

RESPONSE

COMMAND-

1D<L4:0>

B31

0000

DESTINA000
TAG<2:0> 1D<4:0>

04 03

S EQUEST

LEVEL

ZERO-

REQ<7:4>

M<3:0>
831

LOGICAL

ZER

08 07

01 00

111615

0000
M<3:0>

: J

BIT PAIRS

(BIT PAIRS =B17 AND BO1-B31 AND B15)
TK-0171

Figure 2-11

2.8.4.3

Identifier

Field

Interrupt Summary Formats

The

field

(ID<4:@>)

contains

code that identifies the logical source or logical destination of
the information contained in B<31:088>. ID codes are assigned only
to commander and responder nexus (i.e., those that issue and
recognize command/address information). Each nexus is assigned an
ID code that corresponds to the TR line that it operates. For
example, a nexus assigned TR@5 would also be assigned ID code 5.

More than one ID code may be assigned to a nexus. However, that
nexus must be capable of responding to read type commands for
which the read data returns in an order different from the order
in which the commands were given. For write masked and extended

commands,

the mask

transmitted

the

cycle

write

masked

Nexus

using more than one code take the first code from the

preceding the cycle for the data to which the mask applies.

standard ID code assignment (@--15). The second code is taken from
the range 17--392 (i.e., first ID code plus 16).
2-21

Certain

ID
diagnostic

the

SBI

codes

are
purposes.
(read
data,

selection.
nexus

are

2.8.4.4

ID = 16, unit processors; ID = 31,
reserved so that the idle state of
destination
ID =
#)
will
not
cause
a nexus
that
even
though
a
nexus
is
not
selected,
all

Note

checking

Mask

Field

interpretation,
data

bytes

read

masked,
masked,
and

2-12,
on

each

for

interpretations:
all

reserved:

correct

SBI

The

mask

The

appearing

write

Table
and

2-3.

are

bit

the

mask

field

interpretation

B<31 200>

corresponds

used

defines

has

two

particular

byte

when

TAG<2:2>

data

types

specified

the

@gg

(read

read

in
codes
(8011--1111)
are
reserved
data
substitute
by
the
receiving

Table

2-3

Read

Data

M<3:0>

Data

Type

o907

Read

data

A0a 1

Corrected

read

agly

Read

substitute

All

other
interpreted

mask

field

nexus.

M<3:0>13]

(M<3:0>)

secondary.
For
the
primary
to specify operations on any or
B<31:8¢>.
The mask is
used with
the

masked,
interlock read masked,
interlock write
extended
write
masked
commands.
As
shown
in
Figure

secondary
This

field

primary
and
M<3:0> is encoded

B<31:00>.

data).

parity.

data

Types

data

21110

BYTE 3

BYTE 2

BYTE1

BYTEO

TK-0172

Figure

2-12

Mask

2-22

Field

Format

2.8.5

"Response Group Description

The

(CNF<1:08>),

three

and

whether

not

indication

protocol

the

response

receiver

asserted
Either

lines

Fault

can

the

field

transmitted

propagate,

allow

cycle,

every

decisions

bit

nexus

the

response

CNF.

(or

all)

information
2.8.5.1

1in

the

code.

malfunction;

1is

the

each

information

nexus
FAULT

one

signals

then

each

and

makes

for

multiple

(or more)

will

asserts

after

During

latches,
Except

the

recognize

the

detecting

path

receivers;

responder.

signals.

error

field.

the

receives,

path

Codes

—--

Table

2-4

Confirmation

appropriate

protocol

2-4

Code

1lists

the

confirmation

Definitions

Response

(N/R)

The

unasserted

response
1,

cumulative

and be decoded by all
by

and

after

allow

transfer

assert

CNF Code
No

cycles

system

interpretation.

their

path

Confirmation

transmitter

correctly

nexus malfunction,

This

may

FAULT

confirmation

generation

the

failure.

path

Table

two

information

Confirmation

and

codes

the

be checked,

errors or

nexus

delayed

information

receiving

address
Any

confirmation

transmission

nexus

information

timing

fields:

received

same

signals

was

command.

the

two

informs

the

with

Confirmation

into

CNF<K1:£#>

information

process

transfer.
and

are divided

(FAULT).

Acknowledge

(ACK)

The

state;

commander's

positive

indicates

selection.

acknowledgment

any

transfer.
19,

Busy

11,

Error

(BUSY)

The

(ERR)

response

transfer

that

selection

unable

execute

The

transfer

BUSY

(13)

command/address

the

(11)

nexus

The

1is

command/address

selection

execute

the

transfers

considered

presently

command.

indicates

successful

that

the

cannot

response

will

command/&eddress

command.

other

than

response

from

responder.

2.8.5.2

CNF

ERR

transfers

that

indicates

response

nexus

&and

Response

FAULT

transmission.

ACK

command

will

Handling

1lines
is

the

transmitting

expected

executed,

the

third

confirmation

information

correctly).

2-23

nexus

samples

cycle

has

response

been

the

following
(i.e.,

received

Should a command/address transfer

receive a BUSY confirmation,

period)

timeout occurs.

will

commander

until

the

repeat

is accepted

(after

transmission
or

the

waiting

a nominal

An N/R confirmation should be treated like BUSY, except that its

occurrence may be
invoke

Some

the

appropriate

may

nexus

whether

flagged

programming

result of a

function

in a

will

completed

cannot

completed,

read

cannot

completed,

the

command

transmitted

successfully.

write

interrupt

requested.

with

type

transfer

data

For

responds
read

aborted

cycles,

SBI

two

it is later determined that a

and

is the

abort the command and

and

success

presumes

the

ERR confirmation

within

determine,

cases,

confirmation.

should

and

recovery routine.

unable

nexus

status bit.

error,

these

ACK

function

1is

all

zeros

and

interrupt

type

request

In either case, the cause of the interrupt is indicated

requested.

in a configuration/status register.
2.8.5.3

extended

Successive

Cycle

masked,

write

successive transfers,

and

Confirmation

extended

acknowledgment

Since

write

masked,

consist

operations

read

is more complex.

If the command/address transfer is confirmed with N/R or
then

BUSY,

notice

will

taken

data

the

transfer

confirmation and the entire sequence will be repeated.

If the command/address transfer receives ERR, the
sequence is aborted and recovery routines are invoked.

If ACK is not received as confirmation
command, the command is repeated.

Transmissions of read data

are confirmed with ACK by the

ignore

since

receiver

SBI

timeout.

Both

timeout

this

that

The

data.

confirmation,

read

data

only

data

write

may

transmitter

commanders

execute

sequences.

retry

2.8.5.4

for

Sequence

functions:

Timeouts

interface

timeouts

All

sequence

specified

are

commanders

timeout
102.4

1implement

and

read

(or

512

two

data

SBI

cycles).

The

interface sequence timeout determines the maximum time allowed

complete

defined

the

interface

time

from:

The

sequence.

interval

sequence

1is

when SBI arbitration is initiated, until ACK 1s received
for a command/address transfer that specifies read, or

when

for

SBI arbitration

initiated,

for

each

a command/address transfer

ACK is

also

received

2-24

until

ACK

received

that specifies write,

transmission

of write

and

data,

when

SBI

arbitration

confirmation

1initiated,

received

for

any

and

ERR

command/address

transfer.

The

read

data

timeout

interface

sequence

the

that

time

commander.
longwords

the

sequence

must

that

specifies

specified

the

case

retrieved

receives

bit.

Certain

nexus

due

occurs,

both

timeouts

are

data

late

When

occurs,

the

Fault

assertion

nexus

FAULT

the

and

leading

lines

requiring
encoded

asserts

SBI

completed,
to

to
the

function,

both

us).

interface

recorded

for

requests

those

nexus.

When

when

detects

nexus

SBI

(e.g.,

provides

read

this

the

actual

address

the

timeout

occurred.

data).

Either

timeout

the

type

timeout

received

will

retry.

Each

nexus

The

and

equipped
(register

contains

fault

with a
#).

flags

status

32-bit

The

that

portion

the

nexus

fault

cause

the

described

and

nexus

The

CPU

the

will

each

and

then

the

which

the

fault

the

fault

the

signal

continues

assert

all

nexus

bits

Figure

confirmation

The

the

latches

fault

FAULT.

assert

nexus

cycle during
signal

examined

and

2-14

fault

shows

decision

the

flow

Group Description

group

(ALERT)

consists
1line.

represent

request

lines

order

(or

simultaneously
lines

line)

The

may

2-25

the

CPU

than

asserted

are

lines

assigned

interrupt

levels.

service

condition

lines

are

priority

request

Any of

request

lines

requesting

asynchronously

four

REQ4--REQ7.

interrupt.

Request

assigned

that

intervention.

request

of
REQ
nexus.

the

FAULT.

ascending

FAULT

has

causes

error conditions.

alert

request

conditions

configuration

the

Request

fault

FAULT then

negation

request

processor

combination

requesting

the

and

used

the

refer

illustrates

clock

asserted

software

Interrupt

(REQ<7:4>)

the

terminate

their

cycle.

examines

responses

interrupt

some

prior

which

line.

latched

specified

2.8.6

(1#2.4

for

respective

edge

the

2-15

The

read

timeout

confirmation,

one

CPU

Figure

The

FAULT

thus

The

involved.

all

extended

records

status

this

its

timing

for

fault

for

lock

until

has

returned

transfer

transmission

detecting

status bits

FAULT

1is

when

2-13.

occurred.

command

from

commander

sequence

and

the

signal

system

time

data

occurrence

Detection --

portion

Figure

may

the

address

command

configuration

read

cancelled

commander

interface

terminate

status

N/R

unusual

reconstructed

addition,

2.8.5.5

the

error).

timeout

(i.e.,

prior

read

command/address

timeout

status

control

defined

the
be

last

the

one
by

nexus

with

respect

nexus,

and

any

REQ lines

the

may

collection

be
of

FAULT STATUS

“31

PARITY

NOT USED

INTER-

FAULT

ALERT/INTERRUPT
AND DEVICE STATUS

PWR |WSQ | URD | 1SQ | MXT | XMT
FLT | FLT | FLT | FLT | FLT | FLT

LOCK
WRITE

SE&UUELNFCE

SEQUENCE

FAULT

UNEXPECTED

TRANSMITTER

READ DATA

DURING CYCLE

FAULT

THAT CAUSED FAULT
MULTIPLE
TRANSMITTER

FAULT
TK-0076

Figure

2-13

Fault

Status

Flags

A NEXUS

CPU

DETECTS A
'FAULT ON
THE SBI

Tl1

LATCHES
FAULT

| l
T|3

l |

111

TI'O

TI1

T|2

T|3

]

CYCLE THAT

T|1

T|2

71O

CAUSES FAULT

DETECTING

ALL NEXUS

NEXUS

LATCH FAULT STATUS

ASSERTS

BITS

FAULT
TK-0098

Figure

2-14

Fault

2-26

Timing

SBI FAULT DEFINITIONS

DEFINITION

FAULT

PARITY |REPRESENTS AN INFORMATION PATH ERROR GENER-

ATED BY ONE OR MORE NEXUS WHEN THE CALCULATED
PARITY DISAGREES WITH THE RECEIVED PARITY.

SBIT3

PARITY

WRITE| RESULTS WHEN A NEXUS WHICH RECEIVED A WRITE

WRITE MASKED, OR INTERLOCK
SEQUENCE| MASKED, EXTENDED
COMMAND IN THE PRECEDING CYCLE

WRITE MASKED
DOES NOT RECEIVE THE ANTICIPATED WRITE DATA IN

EVEN

TRANSMmIT

MULTIPLE

CYCLE

XMITTER
FAULT

RCVD =
D TRANS

YES

PARITY
FAULT

R UENCE
PAULT

READ DATA
]

TAG

THE CURRENT CYCLE.

FOR
UNEXPECTED| RESULTS WHEN A NEXUS WHICH 1S NOT WAITING
READ

PARITY
FAULT

READ|READ DATA FROM A PREVIOUSLY ISSUED

DATA| MASKED, EXTENDED READ, OR INTERLOCK READ

MASKED COMMAND RECEIVES A RESPONSE TO A READ

YES
ID
=
RCVD
{D TRANS

EXPECT

TYPE COMMAND.

INTERLOCK |RESULTS WHEN A NEXUS RECEIVES AN INTERLOCK
SEQUENCE |WRITE MASKED COMMAND AND INTERLOCK HAS NOT

MULTIP
XMITTER
FAULT

BEEN SET BY AN INTERLOCK READ MASKED COMMAND.

MULTIPLE | RESULTS WHEN A TRANSMITTING NEXUS DETECTS MUL-

CYCLE BY COMTRANS. | TIPLE TRANSMITTERS IN TOTHETHESAME
TRANSMITTED 1D ONE
MITTER| PARING THE RECEIVED ID

PARITY
FAULT

CYCLE AFTER TRANSMITTING.

RESERVED

INTERRUPT SUMMARY

WORD TAG

READ TAG

REQ
LINE

ACTIVE

INTERRUPT
MASK/

DATA

FUNCTION

EXPECTED

SUMMARY

RESPONSE

VALID

UNEXPECTED
READ DATA

FAULT

INTERLOCK
SEQUENCE
FAULT

TK-0086

Figure 2-15
Fault

Confirmation and
Decision

Flow

The

ALERT
signal
is
asserted
by
nexus
that
do
not
implement
interrupt request lines.
Its purpose is to indicate to the CPU a
change
in
the
nexus
power
condition
or
operating
environment.

Nexus

that

requesting

implement

interrupt.

the

REQ

lines

report

such

changes

2.8.6.1

Interrupt
Operation
-When
a
nexus
requires
an
interrupt,
it asserts its REQ line on the SBI. At a time judged
appropriate,
the
CPU
will
recognize
the
interrupt
request
and
issue
an
interrupt
summary
read
command
(TAG<2:0>
=
11¢).
The

command

will
have a
single
bit
set
in
its
interrupt
level
mask
(B<7:4>),
which corresponds to
the REQ line being serviced.
For
example, B P4 set to a logic one indicates that the REQ4 level is
being
serviced.
Note
that
the
remaining
information path
fields
(i.e., B<31:08>, ID<@3:00>, and M<3:0>) are transmitted as zero.

Nexus receiving the interrupt summary read command without error
and asserting the REQ line specified in the
interrupt level mask

will assert a 2-bit code in B<31:00>. This code, which identifies
the
requesting
nexus,
is
asserted with
the
timing
of
CNF<1:04>.
However,
the responding nexus does not assert any CNF, TR, ID,
TAG line. Nexus that detect incorrect parity will assert FAULT.

As shown in
positions in

Fiqure 2-16,
the asserted bits are in corresponding
upper and lower 16 bits of B<31:8¢>. The bit pair
uniquely identifies the nexus among ‘those using the particular REQ
line. Only 15 bit pairs in the information field are used
(i.e.,
the

B31 and
Bl5
through Bl17 and
B@l).
asserted,
parity
remains
correct

responding
are

equal

nexus.
to

the

The

two

bits

nexus

number

Since

only

regardless

assserted
and

the

nexus

INTERRUPT B3]

pairs of bits are
the
number
of

of
TR

requesting
number

0807

SUMMARY

ZERO

nexus

plus

15.

0403

> fg\?EULEST @ ZERO
>

READ

INTERRUPT B3

1716 15

SUMMARY
RESPONSE

0100

0
¥

[

0
¥

BIT PAIRS

TK-0164

Figure

2-16

Request

Level

2-28

and

Nexus

Identification

holding

before

latching

the

after

cvcles

the

SBI

with

B<31:#8>

into

internal

the REQ level and

read

summary

interrupt

the bit pair

received

nexus

CPU

the

TR@#@,

control

While

command

two

waits

transmitted

By encoding

the

from responding nexus,

CPU generates a vector unique to that level and nexus. The vector,
in

turn,

routine will

used

invoke

the

service

routine.

The

service

take explicit action by writing a device register to

clear the interrupt condition. Clearing the interrupt causes the
nexus to negate the REQ line, provided that the nexus does not
have any other outstanding interrupts at this level. The negation

of REQ occurs .within two cycles of the write data transmission.
Normally,

the

CPU

will

service

REQ7--REQ4.

Similarly,

nexus

requesting

interrupts

requests

descending

identified

are

order,

order

descending

beginning with the nexus that asserts bits B31 and Bl5 and ending
with the nexus that asserts bits B17 and Bl. If multiple nexus are

read
and

the

Figure

2-17

1is

serviced

the

are

commands

summary

REQ line

same

REQ

line,

all

wuntil

1issued

multiple

nexus

longer

asserted.

functional

timing

chart

the

for

interrupt

been

have

interrupt

operation.

2.8.6.2

Status

indicate

conditions

status bits
if
present

that

Flags

cause

shown

configuration

its

assertion

are provided, but additional
such as
conditions,
other

Figure

2-18

ALERT

(or

the

ALERT status bits
overtemperature,

are
are

Power

implemented).

1line

REQ

appropriate

Alert

bits

maintains

nexus

each

and

down

power

detectable.

The

ALERT

asserted
cleared

line

when

clear

the

written

these

status

Alert

bits

set during

are

Flag

request

during

when

power

the

1logic

Note

the

alert

status

SBI

clock.

Alert

one;

when

written

that

the

UNJAM

bits;

1logic

=zero,

status
as

signal

bits

does

are

not

bits.

2.8.6.3

interrupt

logical

received.

signal

UNJAM

synchronously

Operation

when any of
the

power

following

failure

supply AC

the

nexus

its alert
at

asserts

ALERT

status bits are

set.

The

events:

the

nexus

when the assertion of

recognized;

restoration of

power

when

the negation of AC

recognized;

other

environmental

overtemperature,

are detected;

2-29

conditions,

such

SBI CYCLES

(CO-CN)

COMMANDER|

SBI LINE

(CPU)

SAMPLING

CN +

Reie

SOME TIME

_+_ CN + 2 ___+_ CN + 3 ____|__ CN
+ 4

SMITTER

(ARBITRATION) |(INTR. SERVICED)

SBI LINE

RECEveR

SAMPLIN

NEXUS

LATER

CN + 6 + X

| DECDDES REQ

AND
B <31:01>|

ROUTINE

_'|
CPU NEXUS

REQUEST NEXUS

ARBITRATES ALL

DECODES

REQ LINES
]

(FOR SBI)

COMMAND
l

SBI

STROBES

ASSERTS TROO AND

REQ LINE
INTO LATCHES

$BI

TIME

STROBES

ISSUES INTERRUPT
SUMMARY READ

ID CODE INTO
LATCHES

ASSERTS

Lttt

NEXUS CODE

ASSIGNED

COMMAND

REQ LINE

INTO LATCHES

L';’;('L"J:M'TTER

SBI LINE

NEXUS

s T)

SAMPLING

zgifi'g“
|

REQUEST NEXUS
ASSERTS CODE

LINE

AT TO

PRIORITY REQ

SBI LINE

INFORMATION | SAMPLING

2 aTion) | PATH DECODE

| NEGATES

ON B <31.01>

CPU NEXUS

ARBITRATES

STROBES CODE

OF SBI

AT T3

INTO LATCHES

CPU GETS

S8i

ARB OK

CYCLEN+4

ATT3

SBI LINE
SAMPLING

REQUEST LINE

START

CPU NEXUS

ENCODES REQ

LINEAND

AND ISSUES

B <31:01>

COMMAND AT TO

)]

REQUEST NEXUS

REQUEST NEXUS
ASSIGNED

REQUEST LINE

(REQ <7:4>)

INTERRUPT

CYCLEO

ASSERTS

'
CPU NEXUS

ASSERTS TROO

SUMMARY READ

SBI

CPU

INTERRUPT
SUMMARY RESPONSE

REQUESTING

SELECTS
HIGHEST

FOR CONTROL

B <31:01>

]

CPU NEXUS

ID
ASSERTS

STROBES

SB!
CYCLE N+3

crrrrrtrrrrrrrtrrtrrrerrtrrrrr

amesNe |

0¢-¢

CYCLE N+1
l

CLEAR
INTERRUPT

INTERRUPT
SUMMARY READ

ENCODED DATA
PROVIDES

INTERRUPT
VECTOR

STROBES CMD

INTO LATCHES
ATT3

)

SBI CYCLE
CN+5+X

SOME TIME LATER

LATCH CONTENT
IDENTIFIES REQ

SBI

LEVEL BEING

N
CYCLE

SERVED

SBI l

!
CPU NEXUS

CLEARS
INTERRUPT
INVOKES SERVICE
ROUTINE

CYCLEN+2
TERMINATE

Figure

2-17

Interrupt Operation
Timing and Flow

TK-0106

The

alert

status
them

caused

that

bits

are

only

The power down status bit

setting

the

nexus

power

down

the

transition of

bit

overtemperature bit is set when there
normal to the overtemperature state.

power

asserting

clears

the

ALERT,

status

the

power

asserting

interrupt

Setting

bit;

down

all

alert

status

bits

are

cleared

likewise,

The

from

the

transition

request

(written

the

bit.

due

an alert status bit set, continues to assert ALERT until:
a.

event

transition of

state.

clears

bit

is a

the asserted
power

A nexus

status

is set when there

negated

the

from

set

set.

with

logic

one),

The

UNJAM

signal

nexus

loses dc

negation

occurs
clear

within

the

ALERT

two

ALERT

received,

power.

(or

cycles

condition.

REQ)

synchronous

write data

the

SBI

clock

transmission

used

ALERT OR
INTERRUPT STATUS

232221201918 17 16

15
DEVICE
DEPENDENT STATUS

FAULT
STATUS
\

M
PWR | OVR DEVICE
DWN | TMP hepenDENT

PWR
UP
TK-0107

Figure

2-18

Alert

2-31

Status

Bits

and

2.8.7
The

Command

Code

operations

Description

executed

command/address

format

fields.

2-19

lists

reserved

codes

Figure

the

command

for

with

future

over

wusing

summarizes

codes.
use.

the

the
the

Several
All

SBI

mask,

specified

command/address

function

nexus

are

function,
codes

must

respond

The

read

are

and

formats

and

unused

and

these

reserved

an N/R confirmation.

2.8.7.1
Read
Masked
Function
specified in Figure 2-20.

MASK

masked

function

FUNCTION | ADDRESS

M <3:0>

F <3:0>

A <27:00>

MASK

FUNCTION

USE

CODE

DEFINITION

RESERVED

IGNORED

0000

USED

0001

READ MASKED

USED

0010

WRITE MASKED

RESERVED

IGNORED

0011

USED

0100

IGNORED

0101

IGNORED

0110

RESERVED

USED

0111

INTERLOCK WRITE MASKED

INTERLOCK READ MASKED

RESERVED

IGNORED

1000

IGNORED

1001

RESERVED
RESERVED

EXTENDED READ

IGNORED

1010

USED

1011

IGNORED

1100

RESERVED
RESERVED

EXTENDED WRITE MASKED

IGNORED

1101

IGNORED

1110

IGNORED

RESERVED

1111

RESERVED
TK-0083

Figure

igmflg‘sm/

FORMAT

2-19

SBI

Command

Codes

LOGICAL

BYTE

SOURCE

COMBINATION

TAG <2:0>

ID <4:0>

M <3:0>

000

gg%w ATION

TT)T:E

RETRIEVED DATA

ID <4:0>

M <3:0>

B <31:00>

CORMAT

gifi?\

1in

address

TAG <2:0>

0001

DATA

PHYSICAL
ADDRESS

F <3.0>

A <27.00>

TK-0084

Figure

2-29

Read

Masked
2-32

Function

Format

Prior
to
issuing
the
command,
the commander
arbitrates
for
SBI
control. When the commander gains control of the SBI, it asserts
the
information
transfer
lines at T@.
At T3
of
the
same cycle,
each
nexus
strobes
the
command/address
information
into
its
receiver
latches
for
decoding.
The
command/address
format,
presented on the SBI, instructs the nexus selected by the address
field, SA<K27:08>, to retrieve the addressed data word and transfer
it
to
the
logical
destination
addressed nexus will respond to

ACK
(assuming
no
command/address.
The

addressed

the

errors)

specified

the

field.

the command/address transfer with
SBI cycles
after
the assertion of

two

data

is retrieved in a time frame that is dependent
response
time.
Following
the
response delay,
the

nexus

responding

nexus

OK
on

for the responder, the information fields are
at T@. TAG<2:8>
is coded as 000,
specifying

is true
the
SBI

The

must

the

After

the

identify

uncorrectable

substitute

(M<3:8>

read

the

SBI.

After

ARB

asserted
the

read

commander.

data,

the

The

responder

¢g919).

assertion

of
read
data,
the
commander
1latches
the
B<31:08> at T3 of the same SBI cycle. At T@ two cycles
commander confirms the successful transfer by asserting

content of
later, the
ACK.

Figure

case

data

the

data is asserted on B<31:00> and received by the commander as
data
(M<3:8>
=
@000),
or
as corrected
read data
(M<3:8>
=

read

coded

read
read

control

format;

transmits

ID<4:0>

for

data

@#l).

and

arbitrate

2-21

functional

timing

chart

for

the

read

masked

operation.
2.8.7.2

Extended

similar

format

the

shown

Figure

field

and

bit

The

mask

are

ignored.

However,

extended

transmitted,
and
cycles.
In
this
SAK27:80>

the

Read Function -- The extended
read
function is
masked
function
in operation.
The
function

read

commander

SA@@

the mask

read,

thus

the

field

bits

must

F<3:08>

the

(specified

received

instructs
addressed 64-bit

command/address

transmitted

word

zero.

(two
data
longwords)
are
always
two
contiguous
SBI
data
transfer

require

case,

retrieve

2-22.

the

function.

2-33

field)

the
nexus
selected
data and transfer it

the

read

by
to

masked

Co_CN]

SBI CYCLES

|-—o
C

————

‘|c—c1—-|'—cz

COMMANDER TRANSMITTER | TRANSMITTER
NEXUS
NEXUS
(ARBITRATION) | (INFORMATION)
ASSERTS

ASSERTS

TR# ON SBI

C/A

NO HIGHER

CN—+—CN+1—+—CN+2—+—CN+3—+—CN+4—-|

SBI LINE
RECEIVER
READ DEVICE
SBI LINE
RECEIVER
RESPONSETIME | SAMPLING | NEXUS
SAMPLING | NEXUS
(CONFIRMATION)
(INFORMATION)

STROBES

C/A ACK INTO

DATA INTO

S8l

ASSERTS
ACK
DATA

LATCHES

TR#
[ASSERTED

SBI LINE
TRANSMITTER
SAMPLING | NEXUS
(CONFIRMATION)

CYCLEN+2

RESPONDER

sl
rr1rrr1rr1r11r 11161ttt PPl
TO T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 TO T1 T2 T3 70 T1 T2 T3 70 T1 T2 T3 70 T1 T2 T3 T0 T1 72 73 T0O T1 T2 T3
LYYV NG T
N T
T T T
I
I O B
R
Y
O I

TIME

C/A 1S VALID IN

RECEIVER LATCHES

NO HIGHER/

ASSERTS

ve-C

TR#ON SBI

RESPONDER |

S8l LINE

RECEIVER

NEXUS DECODE |TRANSMITTER [ oo e

g mpLnGg | NEXUS
(INFORMATION) TIME

ON INFO LINES
ATTO

!
COMMANDER

STROBES DATA

Lgismeo

C/A ACK

ASSERTS DATA

DSX:E?AECSK

INTO LATCHES

ATT3

ASSERTS

READ DATA

SBI

ON SBI

ITTER
TRANSMITT

TRANSMITTER

NEXUS
NEXUS
(CONFIRMATION) RESPONSE TIME | NEXUS
(ARBITRATION) | (INFORMATION)

CYCLEN+3

SBI LINE

RECEIVER

SAMPLING | NEXUS
{CONFIRMATION)

COMMANDER
SAMPLES AND

RESPONDER
DECODES s8B!

START

SBI

CYCLE 1

CYCLE O

COMMANDER

ASSERTS C/A
ON INFO LINES

ASSERTS TR

]

COMMANDER

RESPONDER

AT T3

SAMPLES AND
DECODES SBI
LINES

STROBES C/A ACK

INTO LATCHES
SBl

CYCLE 3

LINE AT TO

RESPONDER
TEST TR LINE
ATT3

STROBES INFO
LINES INTO

LATCHES AT T3

S8l
CYCLE 2

RESPONDER

ASSERTS C/A ACK

CYCLEN

‘
SBI

SBI

CYCLEN+1

CYCLE N+4

RESPONDER

COMMANDER

ASSERTS TR

ASSERTS DATA
ACKON

CONFIRM.

REPRESENTS

DEVICE RESPONSE

ON CONFIRM,

TIME REQUIRED

LINES AT TO

FOR CMD

LINES

LINES AT TO

TEST TR LINE
ATT3

RESPONDER

STROBES DATA

ACKINTO
LATCHESATT3

EXECUTION

TE%W NATE
TK-0082

Figure

2-21

Read

Timing

Chart

2-34

Masked

COMMAND
FORMAT

HYSICAL

0000

ADDSI'R(E:SS

;83::‘%? (LoGgicaLLy| 1 1000

011

ADDRESS

IGNORED)

A<27:01>

F<3:0>

M<3:0>

ID<4:0>

TAG<2:0>

(AOO LOGICALLY IGNORED)

FIRST DATA TRANSFER

000

oDésTTpr Al | TYPE OF
-

TION

FIRST 32 BITS OF

DATA

RETRIEVED DATA

READ DATA
FORMATS

SECOND DATA TRANSFER
DATA

000

DESTINA-

TAG<2:0>

ID<4:0>

the

commander

command/address
nexus

strobes

latches

for

assertion

arbitration,

on
in

B<31:80>
the read

M<3:0>

B<31:00>

gains

control

T@.

command/address

decoding.
transfer

The

responder

the

SBI,

the

same

information

addressed

returning

command/address.
the

RETRIEVED DATA

TK-0173

Extended Read Function Format

information
the

command/address

SECOND 32BITS OF

DATA

TION

Figure 2-22

When

TYPE OF

(SAP® = @). The other
masked operation. The

nexus

ACK

Following

asserts

the

into

two

the

first

the

cycle,

each

its

receiver

<confirms

cycles

after

response

delay

32-bit

information
second data

asserts

data

The

the

and

longword

fields are coded
longword (SAQ@ =

is asserted on B<31:00> at T@ of the succeeding cycle.
The
field describing the data
type will
be asserted with each

data

the

as
1)

mask
read

longword.
commander

latches

B<31:00>

(first

data

longword)

the

cycle when
it
was
transmitted.
At
T3
of
the next cycle,
the
commander again latches B<31:@¢0> (second data longword). Then, at
T@ of the following cycle, the commander confirms the first data
transfer with ACK. The commander confirms the second data transfer
with ACK at

Figure

2-23

the

cycle

functional

after

that.

timing

chart

showing

the

extended

read

operation.
2.8.7.3

Write

Masked

Function

-- The

write

is shown in Figure 2-24.
F<3:0>
instructs
modify
the
bytes
specified
by
M<3:8>
in

addressed

SA<K27:80>

using

data

cycle.

2-35

masked

function

format

the selected nexus to
that
storage
element

transmitted

the

succeeding

(CO-CN)

SBI CYCLES

|‘_C°—+—C1——+———cz
TRANSMITTER

| TRANSMITTER

COMMANDER | (ARBITRATION)
NEXUS
NEXUS
| (INFORMATION)
ASSERTS

ASSERTS

TR# ON

C/A

SBI

NO HIGHER

[
S8l

TIME

FRAMES

g:MLIL':IENG

READ

DEV

RECEIVER

SBI LINE

NEXUS
REQF?ONSEK;EME
(CONFIRMATION)
STROBES

EEREE R

TRANSMITTER

STROBES

LATCHES

ASSERTS

LATCHES

| TRANSMITTER

T T

ASSERTS

DATA
2 INTO

DATA 1 INTO

LATCHES

RECEIVER

SAMPLING | (INFORMATION)
NEXUS
NEXUS
NEXUS
NEXUS
| (INFORMATION) |(CONFIRMATION)| (CONFIRMATION)

C/A ACK INTO

ASSERTED

CN—-l'——CN+1——+—-CN+2—+—CN+3—'.—CN+4_+_CN+5__.I

RECEIVER

TR#

ACK

DATA 2

DATA 1

HEEEENEEEE

TT]

NO HIGHER
STROBES

C/A INTO

Assfgf

9¢t-C

LATCHES

C/A

TR#

f ASSERTED
ASSERTS
TRETO

S#BI

RESPONDER

RECEIVER

:i:vmfwe

NEXUS

(INFORMATION)

‘

TRANSMITTER

;"m’s DECODE | Nexus

(CONFIRMATION)

ASSERTS

READ DATA2
TO S8

STROBES

DATA1ACK

INTO LATCHES

STROBES

DATA
2 ACK

INTO LATCHES

READ DATA
1

AND HOLD
TO SBI

TRANSMITTER | TRANSMITTER | TRANSMITTER

:EQPDO?VESVS'?ME NEXUS

NEXUS

|RECEIVER

NEXUS

'RECEIVER

NEXUS

(ARBITRATION) | (INFORMATION) | (INFORMATION) |(CONFIRMATION)| (CONFIRMATION)
TK-0079A

Figure

2-23

Timing

Extended

Chart

(Sheet

and
of

Read

Flow

i
sBl
CYCLEO

;

RESPONDER

COMMANDER

RESPONDER

ASSERTS C/A ACK

STROBES DATA 1

STROBES DATA 2

ON CONFIRM,

INTO LATCHES

ACK INTO

LINESATTO

ATT3

LATCHES

COMMANDER
ASSERTS TR

COMMANDER

LINEATTO

sel

STROBES C/A ACK

TEST TR LINE

SBI CYCLE

AT T3

RESPONDER

AT T3 ON NEXT

ASSERTS DATA 2

SBI

ON INFO LINES

CYCLEN

;

CYCLEN

COMMANDER

REPRESENTS

STROBES DATA 2
INTO LATCHES

DEVICE RESPONSE

ASSERTS C/A

TIME REQUIRED
FOR CMD

ON INFO LINES

EXECUTION

COMMANDER

ATTO

LEC

RESPONDER

STROBES INFO
LINES INTO

LATCHES AT T3
SBi

ATTO

SBl
CYCLE 1

ATT3

SBI

CYCLEN+1

COMMANDER

ASSERTS DATA 1

ACK ON CONFIRM.

RESPONDER

LINES ATTO

ASSERTS TR

LINE AT TO

RESPONDER

TEST TR LINE

COMMANDER
SAMPLES AND

AT T3 ON NEXT

STROBES DATA 1
ACK INTO
LATCHES AT T3

s8I CYCLE

RESPONDER
DECODES SBI

SBi

CYCLEN+5

s8Il

CYCLEN+2

CYCLE 3

;

S8l

CYCLE N+4

i
S8l

CYCLE2

LINES

TERMINATE

CYCLEN+3

INTO LATCHES

RESPONDER

ASSERTS DATA 1

AND HOLD ON

COMMANDER

ASSERTS DATA 2
ACK ON CONFIRM.
LINES AT TO

INFO LINES AT TO

TK-00798

Figure

2-23

Timing

Extended

Chart

(Sheet

and
of

Read

Flow

COMMAND/

ADDRESS

011

FORMAT

LOGICAL

BYTE

0010

PHYSICAL

SOURCE

COMBINATION

TAG <2:0>

ID <4:0>

M <3:0>

101

LOGICA
L
SOURCE

?EgglCALLY

WRITE DATA

ID <4:0>

M <3.0>

B <31:00>

WRITE

DATA

FORMAT

TAG <2:0>

ADDRESS

F <3:0>

IGNORED)

A <27:00>

TK-0091

Figure

‘When

the

2-24

commander

Write

gains

control.

command/address

information

control

retain

the
the

commander
selected

the

Format

SBI,

asserts

the

commander

also

asserts

TR##

T@#.

The

the

succeeding

during

the same cycle, each nexus
into
its receiver
latches
cycle,
cycle,

Masked Function

SBI

cycle.

strobes the command/address information
for decoding.
At
T@ of
the
succeeding

asserts data on B<31:A0>; at T3 of
nexus
strobes
the
data
into
1its

the same
receiver

latches. TAG<2:0>, which accompanies the data, is coded 11
(write
data format). The successful command/address transfer is confirmed

the

receiving

successful

nexus

data

with

transfer

ACK

1is

T@#

confirmed

the

succeeding

ACK

chart

for

the

cycle.

T@#,

one

The

cycle

later.

Figure

2-25

functional

timing

write

masked

extended

write

operation.
2.8.7.4

Extended

Write

Masked

masked
function
format
is
coded 1011 to specify the

Function

extended write masked transfer, the number of
on the mask, but two SBI data transfer cycles
When
the
commander
gains
command/address information
to

retain

same

control

cycle,

each

longword,

during

the

nexus

strobes

corresponding

bits written depends
are always required.

control
of
the
SBI
it
at T@. The commander also
succeeding
the

SBI

SAfQ

2-38

cycle.

command/address

into
its
1latches
for
decoding.
The
mask
command/address
indicates
the
bytes
to
be
data

The

illustrated
in
Figqure 2-26.
F<3:0>
1is
extended write masked
function.
In the

asserts
asserts
At

the
TR@#
the

information

that
accompanies
the
written
in
the
first

START

SBICYCLES
|N
(CO-4)
7

NEXUS

RECEIVER

TRANSMITTER | TRANSMITTER | TRANSMITTER | RECEIVER

COMMANDER / NEXUS

NEXUS

/
%

/// (ARBITRATION) | (INFORMATION) | (INFORMATION) | (CONFIRMATION) | (CONFIRMATION) é

SBI
CYCLEO

SBI
CYCLE 3

COMMANDER

HESPONDER

CONFIRMATION
LINES AT TO

TEST TR LINE

SBI

AT T3 ON NEXT

STROBES
ACK INTO

ASSERTS

[ ASSERTED

DATA

LATCHES

11717171717
17 b1t b1 i1 1 1]

O O

STROBES

C/A INTO

LATCHES

STROBES

DATA INTO

SAMPLING

RECEIVER
NEXUS

RECEIVER

NEXUS

COMMANDER
ASSERTS HOLD

RESPONDER
ASSERTS DATA

AND C/A ON
INFO. LINES AT TO

ACK ON

CONFIRMATION
LINES ATTO
l

STROBES INFO.
LINES INTO

COMMANDER

LATCHES AT T3
SBI

SBI LINE

SBI

RESPONDER

S:f:fi::i

LATCHES

CYCLE 4

C/A ACK

ASSERTS

RESPONDER/

LATCHES AT T3

CYCLE 1

6¢-C

ACK INTO

STROBES C/A

SBI

HOLD

COMMANDER

LATCHES

C/A AND

SBl CYCLE

STROBES
ACK INTO

ASSERTS

ACK ON

LINEATTO

TR# ON

NO HIGHER
TR#

SBI

ASSERTS C/A

ASSERTS TR

ASSERTS

TIME

TRANSMITTER | TRANSMITTER
NEXUS

NEXUS

(INFORMATION) | (INFORMATION) | (CONFIRMATION)| (CONFIRMATION)

V/,

STROBES DATA

ACK INTO

LATCHES AT T3

CYCLE 2

COMMANDER
ASSERTS DATA

WORD ON INFO

LINES AT TO

RESPONDER

STROBES DATA

WORD INTO
LATCHES AT T3

in-0080

Figure 2-25
Timing

Write Masked

Chart

and

Flow

COMMAND/

011

ADDRESS

TAG <2:0>

LOGICAL

BYTE

SOURCE

COMBINATION

1011

ID <4:0>

M <3:0>

PHYSICAL
ADDRESS

F <3:0>

A <27:00>

FIRST DATA TRANSFER

101

LOGICAL

BYTE

FIRST 32 BITS OF

SOURCE

COMBINATION

WRITE DATA

FORMAT
SECOND DATA TRANSFER

0000

LOGICAL

101

TAG <2:0>

SECOND 32 BITS OF

(LOGICALLY

SOURCE

IGNORED)

iD <4:0>

WRITE DATA

M <3:0>

B <31:00>
TK-0081

Figure

B<31:80>
the

same

latches.
SBI

the

and

2-26

succeeding

codes

cycle,

control

Extended

the

nexus

data

strobes

holds

longword

negates
the

Format

asserts

format).
the

TR##

data

into

asserted

transfer.

mask that accompanies the first data word
be written in the second data word. At the
commander

Function

commander

(write

the commander

second

Masked

the

101

receiver

addition,

for

cycle,

TAG<K2:4>

the

Write

Note

1its

retain

that

the

indicates the bytes to
end of this cycle, the

TROG.

succeeding

cycle,

the

second

data

word

asserted

B<31:00>,
and
TAG<K2:0>
receiver nexus confirms

is coded 141.
At the same time
(T@)
the
the command/address transfer with ACK,
if

there

strobes

the

second

data

two

error.
data

longword

succeeding

transfers

into

with
is

its

cycles,

Figure

2-27

masked

operation.

ACK

the

same

latches.

ignored
the

the

mask

the

receiver

each

functional

cycle,

The

nexus

that

receiver

nexus

accompanies

nexus.

confirms

During

the

two

the

the
data

cycle.
timing

2-40

chart

for

the

extended

write

START
k-

SBl CYCLES

(CO-C5)

" —Co

COMMANDER % NEXUS

(ARBITRATION)

CYCLE O

CYCLE 4

A\g

TRANSMITTER

TRANS/REC

RECEIVER

NEXUS

(INFORMATION)

(INFO/CONFIRM)

{CONFIRMATION)

TRANSMITTER

S8l

COMMANDER

RESPONDER

ASSERTS TR

ASSERTS DATA 1

LINE AT TO

CONFIRMATION

LINES AT TO

ASS ERTS

TEST TR LINE

TR#TO
SBI

SBi
TIME

NO HIGHER

ASSERTED

ASSERTS

C/A

DATA 2

HOLD

/A ACK INTO

STROBES

DATA 1 ACK

DATA 2 ACK

LATCHES

INTO LATCHES

STROBES

ASSERTS

DATA 1 AND

ASSERTS

HOLD

STROBES DATA 1

ACK INTO
LATCHES AT T3

CYCLE 1

AND

FRAMES

ASSERTS

C/A ACK

DATA 1 ACK

STROBES

C/A INTO

DATA 1

DATA 2

LATCHES

INTO LATCHES

COMMANDER

SAMPLING

ASSERTS HOLD

RESPONDER

INFO. LINES AT TO

ASSERTS DATA 2

ASSERTS

LATCHES AT T3

RECEIVER

TRANS/REC.

TRANSMITTER

NEXUS

TRANSMITTER

NEXUS

{INFORMATION)

(INFORMATION)

(INFO/CONFIRM)

(CONFIRMATION)

COMMANDER

ASSERTS DATA 2

STROBES DATA 2

AT TO

LATCHES AT T3

ON INFO. LINES

ACK INTO

RESFONDER

COMMANDER

ASSERTS C/A

AND HOLD ON

CONFIRMATION

INFO LINES AT TO

LINES AT TO

ASSERTS DATA 1

LINES ATTO

CYCLE 2

CONFIRMATION

CYCLE 3

STROBES INFO
LINES INTO

ACK ON

SBI

RESPONDER

DATA 2 ACK

CYCLE 5

AND C/A ON

SBI LINE

SBI

RESPONDER

AT T3 ON NEXT
TR#

;

ACK ON

RESPONDER

COMMANDER

STROBES DATA 1
INTO LATCHES

ACK INTO

AT T3

LATCHES AT T3

STROBES C/A

TK-0078

Figure
Masked

2-27
Timing

Extended

Chart

and

Write

Flow

2.8.7.5

Interlock

used

exclusive

Function

provide

access

Description

coordination

shared

between

data

The

interlock

memory

structures.

nexus

When

function

ensure

interlock

sequence
1is
addressed
to
the
UBA,
it
1indicates
that
a
Data-In-Pause/Data-Out
(DATIP/DATO)
sequence
1is
required
on
the
Unibus. The UBA will initiate an interlock sequence when a
Unibus
device
has
1initiated
a
DATIP/DATO
sequence.
The
interlock
functions
operate
like
the
read
and
write
functions
with
the
additional
responsibility
of
setting
and
clearing
the
receiver
nexus
interlock
assertion/negation

flip-flop.
This
flip-flop
<controls
of the receiver's interlock line. However,

the
not

all nexus implement the
interlock function.
Those nexus that do
not will respond to the interlock read and write masked functions
exactly as they do to read and write masked functions.
All

memory

through
the

nexus

the

use

commander

implement

this

nexus

the

interlock

signal.

which

The

1issued

functions

interlock
the

and

line

interlock

cooperate

asserted
read

masked

function
for
that
SBI
<cycle
following
the
command/address
transfer.
The
interlock flip-flop is set
in
the
receiving nexus
memory.
When
the
memory
nexus
confirms
the
interlock
read
function,
it asserts
the
interlock
signal
in
the
same
cycle
as
ACK.

With

interlock

confirmation

Interlock
masked

Read

function

asserted,

subsequent

the

interlock

Masked

Function

format

the

nexus
read

responds

masked

Operation
same

that

with

commands

The

shown

BUSY

only.

interlock

read

2-20

Figure

except that F<3:0> is coded @#10@. F<3:8> causes the nexus selected
by SAK27:00> to retrieve and transfer the addressed data exactly
as in the read masked operation. In addition, this function causes
the

selected

nexus

set

1its

1interlock

flip-flop.

interlock
flip-flop set,
the nexus will assert
line at T@ of the ACK confirmation cycle.

the

SBI

With

the

interlock

The
1interlock
flip-flop
1is
cleared
on
receipt
of
an
interlock
write masked
function.
Interlock read masked and
interlock write

masked functions are always paired by commanders.
If the flip-flop
remains
set
for more than
1€2.4 us,
the memory assumes
that
the
commander
has had
a catastrophic error.
In this
will clear the flip-flop at T# of the next cycle.

Interlock Write
masked
function
2-22,
write

except
masked

SAK27:0M>
storage

Masked
format

case,

the

nexus

Function Operation -- The interlock write
is the same as that
illustrated
in Figure

that F<3:0> is coded @111, specifying the interlock
function.
F<3:8>
instructs
the
nexus
selected
by
modify

element

the

using

bytes
data

specified
transmitted

with
TAG<2:8>
=
101.
In
addition,
the
interlock
flip-flop
set
by
the
previous

function.

2-42

M<3:0>

the

addressed

succeeding

cycle

write
data
clears
the
interlock
read
masked

2.8.8
Control Group
The
control
group
functions

synchronize

system

activities

and

provide
specialized
system communications.
The clock
functions
provide
SBI
activity
synchronization
and
are
described
in
Paragraph
2.8.1.
The
interlock control,
also one of the
system
commmunication
functions,
1is
described
in
Paragraph
2.8.7.
The

remaining

control

1lines

are

described

1in

the

following

paragraphs.

2.8.8.1

DEAD Function —-- The
DEAD signal
indicates
a
dc
failure to the clock circuits or bus terminating networks.
will not assert any SBI signal while DEAD is asserted. Thus,

power
Nexus
nexus

prevent

invalid

unstable

state.

circuits

assertion
of
DEAD.
DEAD
and occurs at least 2

1is
~s

The

assertion

data

from

being

the

power

supply

terminating
networks
causes
asserted asynchronously to the

before

the

clock

will

clock
be

negated.

The

2.8.8.2

FAIL

negation

the

CPU

negated

Function

asserted
from

the
SBI

for

SBI

clock,

that

nexus.
a

with

the

With
2

SBI

clock

when
The

power-up
respect

power
~s

restart,

before

the
1is

DEAD.

enables

1initiating

1least

negates

nexus

while

clock

the

asynchronously

1inoperative.

operational

asynchronously
signal

becomes

received

the

fail

(FAIL)

signal

power

supply

assertion
service
to

the

FAIL

routine.

SBI

inhibits
FAIL

clock

when

1is
all

nexus that are required for the power-up operation have detected
the negation of AC LO. The CPU samples the FAIL line following the

power-down
power—-up

routine

(assertion

should

2.8.8.3
UNJAM
Function
(initializes)
the system to

FAIL)

-The
a known,

by the CPU or
the
SBI.
The

when

sequence)

console
pulse

key

(or

a minimum

determine

unjam
function
well-defined state.

signal is asserted only
all
nexus
connected
to
UNJAM

the

initiated.

SBI

restores
The UNJAM

console, and is detected by
console
asserts
UNJAM only

selected.

cycles

2nd

The
is

duration

negated

the

T@.

When the console intends to assert UNJAM, the CPU will assert TRA®
for a minimum of 15 SBI cycles. The CPU will continue to assert
TRAP for the duration of UNJAM and for a minimum of 15 SBI cycles
after the negation of UNJAM. This use of TR@@ ensures that the SBI
is inactive preceding, during, and after the UNJAM operation.

2-43

Each nexus receives UNJAM at T3 and begins a restore sequence. Any

short duration will

current operation of

operation might leave the nexus

not

operations

perform

the

addition,

UNJAM.

While

UNJAM

using

nexus

not be aborted

in an undefined

the

must

during

SBI

Nexus will

state.

the

idle

if that

assertion
state,

respect to SBI activity, at the conclusion of the UNJAM pulse.

nexus

asserting

preserve

registers.

the

asserted,

FAULT

content

nexus

will

the

nexus

prior
of

The restore sequence

assert

not

UNJAM must

FAULT.

continue

However,

to do

configuration/fault

(UNJAM asserted)

with
a

so to

status

should not cause

a nexus to pass through any states that will assert any SBI lines.

All read commands issued before the UNJAM are canceled.
In

the

assert

event

FAIL and/or

power

DEAD.

nexus to negate ALERT or
any device

status bits.

failure

The

during

restore

UNJAM,

some

nexus

will

sequence should cause the

interrupt requests, but should not clear

2-44

CHAPTER

PROGRAMMING DEFINITIONS AND SPECIFICATIONS
GENERAL

3.1

This chapter describes some of the Massbus signals, clearing
methods, and interrupt conditions; and each bit of the registers
in

the

3.2

Some

MBA.

DEFINITIONS

the

Massbus

signals

that

are

used

information are described in this paragraph.
-

ATTN

(and

sets

condition

error

condition occurs.

The

logical

ATTN

= ATAg

+ ATA

...

ATAi = ERRi + completion
in power conditions.

represents

drive

that

asserted

the

whenever

has

power

change

statements

finished

Jjust

are:

movement

command

select code of a drive,

performing

drive

change

0--7)

data

error

transfer.

occurs

during

1is

the

in the

is used to distinguish errors

This line

transfer.

has

that

Each drive

-- The EXC line connects from the MBA to

(EXC)

Exception

the

the unit

bit)

these

for

expressions
+ ATAl

own ATA

asserted),

command,

movement

any

executing

its

(ERR

status

line

shared

connects from all drives in common to the MBA.
asserts

-- The ATTN line

(ATTN)

Attention

generating

drive performing a data transfer from errors signaled by
the

ATTN

transfer

1line.

never

that

drive

1is

performing

ATTN while the data

asserts

data

transfer

underway.)

End of Block

(EBL)

-- The EBL line

is pulsed by the drive

performing a data transfer at the end of each sector.
Methods

Clearing

Bit

@0 of

the MBA control

the

Initialization

(writing a 1) of this bit will:

(INIT) bit. The setting

Clear status bits in the MBA configuration register

Clear abort data transfer on interrupt enable bits in

the

MBA control

Clear MBA status
Clear

MBA byte

count

3-1

Clear

the

control

and

Cancel

all

pending

commands

Abort

data

Assert

3.3
This

status bits of

tables

The

Massbus

subsequent

Abort

and

is associated only with
error

affect

the
the

data

Abort

MBA,

transfer

command,

data

transfer

asserted

and

transfer

command

the

negated

but

command

any

error

the

drive

ready

DT BUSY bit

1indicator

is
INIT

asserted,

the

MBA

command

not

the

DT BUSY

for

another

bit

ready

initiate
and

the

data

transfer

appropriate

drive

transfer command
can
be
ready
bit
1is
asserted,

the MBA.
initiated,

negated.

initiated,

not

than

the

DT END clears

successfully

other

clear

the DT BUSY bit
is

of
the

MBA

asserted

command

the

When

bits

located

The

When

that

regardless

other

RH788.

does

must
be
asserted.
A nondata
a
drive
any
time
a
drive

state

the

transfers

successfully

not

the

bit

drive

ready
bit
issued
to

the

pending

the MBA.

must

data

conditions during data

MBA.

indicates

command.

BUSY

Abort)

error

the

bit

features

describe

Transfer

and

bit

read

INIT.

paragraphs

(Data

conditions

except

transfers

PROGRAMMING NOTES
paragraph describes miscellaneous

MBA.

the diagnostic

the

When

BUSY

nondata

drive

ready

bit

drive

that

has

asserted.

issued

command

will

1ignored

the

drive.
If

data

indicator

Missed

the

command

asserted,

the

Transfer

Error

issued

drive

that

has

does
@8

not

execute

the

command,

the

CPU

the

bit

set

occurrence

MBA

set;

drive

(MXF,

bit

the

status

error

the

occurs

MBA.

3.4
The

transfer

MBA

INTERRUPT

CONDITIONS

generates

interrupt

due

following

conditions:
1.

upon

termination

when

the

upon

assertion

error,
3.

upon

MBA

while

power

become
of

the

data

ATTN

MBA

transfer,

ready;

line

not

busy

up.

3-2

the

and

the

IE bit

TERMINATION OF DATA TRANSFERS

3.5

data

transfer

the

following

that

has

initiated

successfully

Normal Termination -- Byte count overflows
MBA becomes ready (DT BUSY cleared).

MBA

Error

-- An

Bit

Error

the

PGE

(Program

(Non-Existing

DT ABORT

DLT
WCK

(Data Late)
UP ERR (Write

WCK

LWR ERR

(Write Check

MXF

(Missed

Transfer

MAPPE

INVMAP

MCPE

MBA

terminate

(Massbus

Device)

Control

Parity

(Page

Frame

(Invalid

ERR CONF

(Error

RDS

(Read

Data

21
a0

IS
RD

TIMEOUT
TIMEOUT

Error

MBA

the

Check

Upper

Lower

all

Error)

MAP

Error)

Parity

Error)

MAP)

Confirmation)
Substitute)

error

Sequence
Timeout)

occurs

error

Abort

aborts

Error)

(Interface
(Read Data

appropriate

Error)

Aborted)

Transfer

(Data

the

status

and

Error)

MBEXC (Massbus Exception)
MDPE (Massbus Data Parity

bit

the

causing

operations

Timeout)

drive.

The

drive

drive.

INIT

and

all

asserted,

status

and

error

lost.

information
3.6

may

Indication

Program—-Caused
the

NED

Drive
sets

occurs

@7
1K)

error

18
17

MBA REGISTERS

The

RH78#

registers
longword

given

the

when
bit

and

256

MAP

registers.

the

drives

can

only

accessed

must

longword

aligned

(on

byte

attempt

MOVB

MOVW

from

MBA

This

will

result

attempt

bit

the

registers

paragraphs.

registers

and

occur

MBA

references

either

these

contains

subsystem

also
if

been

ways.

Table

made

machine

check

trap.

from

MOVL

address

and

their

functions

1is

3-1

lists

the

RH780

various

3-3

or
An

provided

All

registers.

explanation

subsequent

MBA Registers

Table 3-1
Massbus
Address

(Hex)

Mnemonic

Configuration/Status

CSR

Control

Virtual

Diagnostic

Status

The

eight

can

base

and

control

derived

address

the byte offset

added

the

information.

from

Tables

respect

for

MBA's

contain

registers

MBA

internal

VAR

Read/write

CAR

Read

Read/write

Read/write
Read only

SMR

Command Address

status,

Read/write

BCR

Selected Map

Read/write

Address

Byte Counter

Type

the

The

3-2

and

its

various

registers

base

address

3-2

these
shows

registers
the MBA's

levels.

Table

3-3

Table

3-3.

the MBA.

produce

configuration,

various

addresses

only

shows

This byte offset

particular

address.
Example

address
Base
Byte

the diagnostic

address from Table 3-2
offset for the DR from
DR

Example
The address

for

an MBA with

the

control

from

Base

address

Table

Byte

offset for
CR address

the

Table

MBA TR
Level

Table
CR

3-3

3-2

TR of

MBA with

3-3

for

200107014

3-2
from

20010009
+

address

QEHEDUOUO@WPOWOIANDS
W

The

TR of

20018009

Table

MBA Base

Addre Sses

Console Phys ical
Base Address
20002000
20004909
20006000
29008000

20002009
2989C000
2000EQ000
200192009

20012000
29014000

20016000
20013000

200 1A0900
2001C0040

2001E000
200290800

3-4

g4
28¢18a04

Table 3-3
Register

Offset

Configuration/Status Register

Control

Virtual

Address

Status Register

(VAR)

Selected MAP Register

(SMR)

gcC

(DR)

(CAR)

Configuration/Status Register

3.6.1

that

Command/Address

The

(CR)

(BCR)

Diagnostic

configuration/status

contains

status,

and

adapter

code

status,

fault

(CSR)

(SR)

Counter

Byte

from Console

Address

Base

interrupt

bits.

Figure

(CSR)
a

read/write

status,

3-1

MBA

adapter

dependent

illustrates

these

bits

0807

04103

and Table 3-4 provides an explanation for the various bits in this
register.

313029282726

25 24123 222120119

0|0

16115

1211

ololololojo]lolo|ololojo|lo|olo|oj1|0|O]O]|O|O
o

SBI PARITY ERROR —
WRITE DATA

—

DATA ERROR

MULTIPLE

TRANSMITTER

ADAPTOR CODE

ADAPTOR POWER UP

SEQUENCE ERRORTM
UNEXPECTED READ |

OVER TEMPERATURE
(NOT IMPLEMENTED)

ADAPTOR POWER DOWN

TRANSMITTER DURING FAULT

ERROR

TK-0692

Figure 3-1

configuration/Status Register (CSR)

Table 3-4

Configuration/Status Register

(CSR) Bit Assignments

Bit

Set By/Cleared By

Remarks

31 PE
SBI Parity

Set when an SBI parity error
by
Cleared
detected.
is

The
this

of
setting
will
bit

cause

fault

(Fault

Error
A)

Set

30 WS
Write

Data

Sequence
(Fault B)

when

URD

Unexpected
Read

Data

(Fault

data

command

ID)

following

power

fail

Cleared

command.

Set

read

when

Cleared

and

one

the

cycle.

The

setting

this

bit

cause

fault

of
will

asserted

the

for one cycle.

SBI

fault.

deassertion

received

the

for

data

by power

fail

fault.

deassertion of

expected.

not

the

The

setting

this

bit

cause

fault

for

one

the

asserted
SBI

will

cycle.

Reserved

Set

Transmitter

does

the

when

agree

not

transmitted

with

by the

the

SBI

MBA while

the MBA is transmitting data

the

power

SBI.

Cleared

fail

deassertion

fault

The

setting

cause

fault

bit

this

asserted
SBI.

signal

the

asserted

will

fault

will

the

confirmation

for

one

the

MBA

the

(The

the

SBI.

for

use.

future

Multiple
(Fault

write

asserted
SBI

=
tag
(neither
received
ID = write
write data nor
write

the

or
fault.

fail
power
deassertion of

time

cycle

detects

fault
the
of
one
The
conditions.
the
of
negation
fault
signal
on
the SBI will clear
all
the
fault
status bits. Fault
= Fault A + Fault
+
B
Fault

25 XMTFLT
Transmit
Fault

Set

when

detected

the

fault

2nd

by power

fail

the
after
information
Cleared

SBI

the

1is

cycle

transmits
MBA
on to the SBI.

deassertion of

fault.
3-6

the

Fault
D.

Table

Configuration/Status

3-4

(CSR)

Remarks

Set By/Cleared By

Bit

future

Set

Adapter

Power

Down

for

Reserved

25:24 All @'s
23

Assignments

Bit

(Cont)

when

MBA

Cleared

down.
goes

the

power

when

goes

power

use.

The

setting

this

bit

cause

up.

interrupt

1is

CPU

the

will

set.

Set

Adapter

Power

when

MBA

when

power

goes

Reset
up.
down.
Cleared
by assertion
or
LO,
DC
UNJAM,
INIT,
of
writing a 1 into this bit.
Always

the

setting

The

this

set

bit

will

IE bit

the

interrupt

the

also

and
CPU.

Over

Temperature

20: 088

All

@7:0@

Adapter

Reserved

@B's

future

use.

Each

adapter

for

1is

unique
assigned a
code
1identifying

Code

The
it.
adapter
code
Bit

<07:90>

agl1o¢ona

3-7

MBA
1is:
=

3.6.2

Control

control

bits:

can

The

control

illustrates
explanation

Interrupt
put

the

this
of

1is

the

(CR)

read/write

Enable,

MBA

Abort,

the

and

that

Initialization.

maintenance

bits;

contains

Table

mode.

3-5

the

This

Figure

3-2

provides

bits.

03020100

0000j0000|0O00O0C|]0O0O0O0O|O0OOO0O0|0O0O0DO0}0O0O00DO

MAINTENANCE MODE

INTERRUPT ENABLE
ABORT
INITIALIZE

NOTE: ALL BITS ARE READMWRITE EXCEPT INITIALIZE WHICH ALWAYS READS AS 0
TK-0693

Figure

Table

3-5

Set
Bit

Control

All

(CR)

Assignments

Bit

By/

Cleared

31:04
g3

3-2

Remarks

@'s

Reserved

for

The

setting

Maintenance

put

the

Mode

mode,

MBA

which

future

use.

this

the maintenance

will

bit

allow

will
the

diagnostic programmer to
exercise and examine the
Massbus operations without
Massbus

device.

the

set,

DEM,

and

Massbus

MBA will

assert

When

that

this

a
bit

block

FAIL

all

the

RUN,

the

devices

on the Massbus will detach from
the Massbus. This bit can only
be set if a data transfer is

not

3-8

progress.

(CR)

Remarks

Set

by writing

Allows

Interrupt

Enable

Cleared
writing

Table

3-5

Control
Set

Bit
g2

(Cont)

By/

Cleared
1E

Bit Assignments

power

the

MBA to

interrupt

CPU

up. | when certain conditions occur.

by
@ or

INIT.

ABORT

Abort

Set

Data

Transfer

writing

cleared

writing

INIT,

4@,

The

setting

UNJAM.

sequences

sending

bit

stop

the

will

EXC

set

ABORT to

byte

also

will

stop

addresses,

counter.

negate

Massbus,

will

transfer

that

commands and

RUN,

wait

assert

for

EBL,

trailing

edge

EBL.

Interrupt

Initialization

this

initiate the data

abort
and

ga4 INIT

CPU

bit

This bit is

The setting of this bit will:

self-clearing

clear

(always
as

status

bits

configuration

reads

ABORT

0).

and

the

clear
clear

the

MBA

clear
control

MBA status
MBA byte count

It will

registers.
all

3.6.3
The

Status

status

status information
indicators. Figure

pending

also

commands

Cancel

except

read data

pending

abort

transfer.

Asserts

Massbus

data
INIT.

(SR)
read/write
register
error
indications,
as:
a

such
3-3 illustrates

that
contains
MBA
timeouts, and busy

the bit assignments and Table
bits in the status register.
3-6 describes the functions
All interrupts will occur immediately if there is no data transfer
data
the
until
postponed
will
be
interrupt
The
in
progress.

transfer

has

terminated.

the

313029

,27

1918171615

0jojojojolojojojo

DATA TRANSFER
BUSY

NO RESPONSE
CONFIRMATION

PROGRAMMING

ERROR

‘

131241110 0908;07 06 05 04,0302
0100

0|0

NON EXISTENT
DRIVE

CORRECTED

MASSBUS CONTROL

READ DATA

WRITE ERROR
MASSBUS ATTENTION:
DATA TRANSFER COMPLETE
DATA TRANSFER ABORT
DATA TRANSFER LATE
WRITE CHECK-UPPER ERROR

WRITE CHECK-LOWER ERROR

MISSED TRANSFER
MASSBUS EXCEPTION
MASSBUS DATA PARITY ERROR
MAP PARITY ERROR
INVALID MAP

ERROR CONFIRMATION

READ DATA SUBSTITUTE

INTERFACE SEQUENCE TIMEOUT
READ DATA TIMEOUT

NOTE:WRITE 1 TO CLEAR BITS IN
THIS REGISTER EXCEPT BIT 31
WHICH IS READ ONLY.
TK-0698

Figure

3-3

Status

3-10

(SR)

DTBUSY

Transfer

Data
Busy

Remarks

By/Cleared

Set

Bit

(SR) Bit Assignments

Status Register

Table 3-6

transfer

data

Set

when

data

Set

when

the

read

command

the

SBI.

Cleared

command is received.

Read

only.

1is

transfer

aborted.

NRCONF

Response

Confirmation

receives

MBA

the

no-response confirmation for
and

command

write

sent

Cleared

setting

cause

retry

bit

this

will

the

command.

bit

this

writing

data

write

The

INIT.

Read

28:20 All

from memory is CRD.

received

writing
INIT.

by
Cleared
this bit or

Data

data

read

tag

when

Set

CRD

Corrected

19 PGE

for

Reserved

@'s

future

one

when

Set

the

following conditions exists.

Program

currently

initiate

the

MBA

performing

one.

when

transfer

data
is

tries

Program tries to load MAP,
or byte counter while
VAR,
the MBA is performing a data
operation.

transfer

The

setting

this

bit
an

cause

the

bit

interrupt

the

1IE

CPU

will

control

set.

Program

set MBA maintenance

tries to

mode

use.

during

operation.

transfer

data

Program

tries

drive

fails

nonacceptable
a
initiate
command.
transfer
data
¢to
1
a
by writing
Cleared
this bit.
18

NED

Nonexisting
Drive

Set

when

assert
after

Cleared

this

TRA

within

assertion

bit.

writing

1.5

DEM.

The

setting

this bit will

send

zZero

data

read

SBI,
the
to
back
the
interrupt
and

CPU

the
register

bit

control
is set.

Table

3-6

Bit
17

Status
Set

MCPE

By/Cleared

Set

Massbus
Control
Parity Error

when

(SR)

Bit Assignments

(Cont)

Remarks

Massbus

control

parity occurs.
Cleared
writing a 1 to this bit.

The

setting

Set

from Massbus

when

the

attention

Massbus

1line

asserted.

The

setting

bit

cause

@'s

interrupt

COMP

Transfer

Set

when

writing

Completed

data

completed.
a

transfer

Cleared

this

The

setting

this

bit

IE
is
12

DTABT

Data

Set

with

the

EBL

when

transfer

has

Cleared
by
this bit or

trailing
the

been

edge
data

aborted.

writing
INIT.

bit

set.

The

setting
of
bit
will
cause an interrupt
to the CPU if the
IE
bit
in
the
this

is
DLT

Data

This

bit

either
or
a

Late

set:

write
write

for

data transfer
check
data

transfer providing the data
buffer is empty when WCLK is
sent
a

the

read

providing

19 WCK UP ERR
Write Check
Upper

Error

Massbus,
data

the

full

when

from

the

Set

when

set.

The

setting

this

bit

cause

the

transfer

data

for

buffer

received

Massbus.
The

setting

this

bit

cause

the

transfer

compare

check

error

operation.

Cleared

writing

this

INIT.

bit

aborted.

detected
in
the
upper
byte
while the MBA is performing

write

will

transfer

data

SCLK

the

control

of
will

cause an interrupt
to the CPU if the
control

Transfer
Aborted

for

use.

bit.

the
the

Reserved

future

Data

will

the CPU if
bit
in

control
is set.
All

set.

this
to
IE

15:14

control

the

bit

Attention

this
bit
will
cause an interrupt
to
CPU
1if
the
1IE

3-12

aborted.

will
data

Table

3-6

Bit

Set By/Cleared

@9 WCK LWR
ERR Write

Set when
detected

Error

Check

Lower

while

the

Cleared

g8 MXF Missed
Transfer

Remarks

MBA

performing

operation.

check

writing

this

bit

INIT.

Set

when

OCC

SCLK

writing

INIT.

within

Cleared

transfer

this

received

data

Error

a compare error 1is
in the lower byte

write

bit

busy

after

1is

set.

Set

MBEXC

when

cause

writing

Exception

received

Cleared

this

bit

INIT.

Data

Parity

Error

data

The

setting

this
cause

bit
will
an interrupt

the

CPU

bit

the

set.

The

setting

this

bit

cause

the

transfer

will
data

aborted.

Set

o MDPE
Massbus

aborted.

control

1is

the

transfer

EXC

Massbus.

from

Massbus

of
setting
will
bit

The
this

is
@7

(Cont)

Bit Assignments

(SR)

Status Register

when

parity

during

The

setting

detected

this

bit

data

transfer

cause

the

Massbus

error
a

read

Cleared

operation.
writing

data

transfer

bit

aborted.

error

The

this

will

data

INIT.

Page

@5 MAPPE
Frame

Map

Parity

Error

Set

INVMAP

Invalid

Map

parity

the

data

read

detected

transfer.

Cleared by writing

from

a
34

when

the

map

this

during

bit

Set

when

the

page

zero

not

2zero.

writing

and

frame

data

byte

bit

this
bit
will
data
the
cause
transfer
to
be

number

counter

The

setting

this

bit

cause

the

Cleared

transfer

this

aborted.

INIT.

3-13

bit

aborted.

INIT.

wvalid

the

setting

will
data

Table

3-6

Bit
93

CONF

ERR

Status

(SR)

(Cont)

Remarks

Set

By/Cleared

Set

when

MBA

the

Bit Assignments

receives

The

setting

for

this

bit

confirmation

of
will

Error

error

Confirmation

read
or
write
command.
to
1
a
by writing
Cleared

cause
the
data
transfer
to
be

this

bit

INIT.

aborted.

Set

when

the

TAG

RDS

Read

Data

Substitute

read
Cleared

this
g1

TIMEOUT

Interface

bit

Set

interface

sequence

the

defined

when

arbitration

is begun

until:

1is

ACK

that

write

RD TIMEOUT
Data

is
any

for

Timeout

Cleared

that

read

data

read

data

specifies

timeout

that

data

1is

the

writing

INIT.

read

the

specified

read

returned

commander.

timeout

completed

time

bit

cause

the

transfer

will
data

aborted.

as the time from
sequence
interface

command

setting

INIT.

bit

The

this

1022.4

writing

defined

when

transfer.

us.

when

data
to

for

confirmation

timeout

Set

and

The maximum

occurs.

the

transfer

write

command/address

this

cause

of
will

received

bit

transfer

specifies

data;

ERR

SBI

for

read;

command/address

that

setting

transfer

received

1is

from

the

received

specifies

ACK

timeout

time

for

address

command

interface

occurs.

timeout

The
this

aborted.

INIT.

when

sequence

Timeout

read

data
substitute.
1 to
a
by writing

Sequence

Read

the

data received from memory 1is

The

1€¢2.4

“s.

the

max imum

3-14

Cleared
this

bit

The

setting

this

bit

cause

the

transfer
aborted.

will
data

3.6.4

Virtual

Before

initial

data

wvirtual

transferred)

address

(VAR)

1initiated,
(pointing

3-4

256 MAP registers.

and

the

assemble
through

physical

indicate

byte.

during

The

data

Figure

the

virtual

the

address

transfer

will

The

illustrates
Bits

contents

MBA

read

write

byte

selected

through

are

used

memory.

Bits

into

the

page

may

not

written

will

set

PGE,

modified

the

and

address

eight

after

will

not point

transferred

transfer

does

not

end

boundary

(it

will

point

1is

memory

the

quadword

eight

bytes

address.

28 27

24 .23

20,19

16,15

09,0807

000O0|00O0O0O|O0O0O0O0]0O00O0
|

MAP POINTER

PHYSICAL
PAGE BYTE
ADDRESS
TK-0696

Figure

3-4

Virtual

Address Register

3-15

(VAR)

current

but

the

ahead). When a write check error occurs,
the
virtual
address
register will
not
point to the failing data in memory due
to
the
preloading
of
the
silo
data
buffer. The virtual address of the bad
data
may
be
found
by
determining
the
number of bytes actually compared on the
Massbus
(the difference between bits 16
to
31
of the byte count
register and
their
1initial
value)
and
adding
that
difference
to
the
1initial
wvirtual

the

sent

not

bit

will

and

the

attempt

virtual

NOTE

incremented

through

continue.

The

1load

byte

offset

address
An

must

first

bits

address
byte

virtual

transfer.

virtual

address

value

SBI

program

the

one

for

the
to

this

select

data

into

assignments
MAP

Address

transfer

into
the

data

3.6.5
Byte Count Register (BCR)
The program loads the 2's complement
the data
hardware
15
as

the

transfer to bits 15 through 080 of
will load these 16 bits into bits

through 0@ of the
the byte counter

number

bytes

for

this register. The MBA
31 through 16 and bits

byte count register. Bits 31 through 16 serve
for
the number of bytes
transferred
through

the Massbus and bits 15 through #¢ serve as the byte counter for
the
number
of
bytes
transferred
through
the
SBI
interface.
The
starting byte count with 16 bits of zeros is the maximum number of
bytes of a data transfer.
Figure
3-5
illustrates
the byte count
register's
bit
assignments.
The byte
modified
during
a
data
transfer.
An

ignored

and

PGE

will

16,15

08, 07

SBI BYTE COUNTER

(READ ONLY)

(READ/WRITE)

NOTE: DATAWRITTEN INTO THE

2's COMPEMENT OF THE

5BI BYTE COUNTER ISCOPIED

~ NUMBER OF BYTES TO BE TRANSFERRED

INTO THE MASSBUS BYTE

COUNTER.

3.6.6
The

Diagnostic

diagnostic

be
be

MASSBUS BYTE COUNTER

Figure

may not
so
will

set.

24,23

count
register
attempt
to
do

3-5

TK0687

Byte

Counter

(BCR)

that

(DR)
contains

MBA

diagnostic information. This register allows diagnostics to be
without any drives on the Massbus. Figure 3-6 illustrates the

read/write

run
bit

assignments, and Table 3-7 describes the function of the various
bits in this register. The diagnostic register may not be written
unless the MBA is in the maintenance mode. An attempt to write the
diagnostic
register
when
not
in
the
maintenance
mode
will
be
ignored. Caution should be exercised
maintenance mode. The data path

when
used

reading this register in
to read bits #4 through

silo

the

may

data

inject
from

initiation
or

invalid

memory.

modifying

data

transfer

this

into

the

1is

advisable

the

deassertion

resister.

3-16

the

MBA

has

just

read

wait

from

the

SCLK before

reading

08,07

INVERT MASSBUS

MASSBUS

DATA PARITY

DRIVE

16 15

24,2322 21

SELECT

INVERT MASSBUS

(READ ONLY)

CONTROL PARITY

INVERT MAP PARITY ——

MASSBUS REGISTER SELECT

BLOCK SENDING

(READ ONLY)

COMMAND TO SBI

SIMULATE SCLK

SELECTED MDIB (READ ONLY)

SIMULATE EBL

(VALID DURING MAINTENANCE

SIMULATE OCC

MODE ONLY)

SIMULATE ATTN
MDI B SELECT

MASSBUS FAIL (READ ONLY)
MASSBUS RUN (READ ONLY)
NOTE:BITS 21 AND 22 ARE READ/WRITE

MASSBUS WCLK (READ ON LY)

FOR DIAGNOSTIC TEST PURPOSES

MASSBUS EXC (READ ONLY)

ONLY

MASSBUS CTOD (READ ONLY)

TK-0694

Figure 3-6
Table

3-7

Diagnostic Register

Diagnostic

(DR)

Bit Assignments

Description

Bit

IMDPG

Invert Massbus Data Parity Generator.

IMCPG

Invert Massbus Cohtrol Parity Generator.

IMAPP

Invert MAP Parity.

BLKSCOM
|

Block

data

Sending

transfer,

eventually

Command
the

cause

the

SBI.

bit

set

setting
DLT

During

this bit
and

will

ABORT.

SIMSCLK

Simulate SCLK.
When
the
MM bit
1is
set,
the
simulate
will
bit
this
to
1
a
writing
assertion of SCLK; writing a @ to this bit
will simulate the deassertion of SCLK.

3-17

Table

Diagnostic

3-7

Bit
25

(DR)

Bit Assignments

(Cont)

Description
SIMEBL

SIMOCC

Simulate

EBL.

When

bit

will

simulate

EBL.

this

EBL;

writing

the

deassertion

Simulate

OCC.

When

bit

this

set,

the

assertion

bit

writing

will

set,

simulate

writing

this
bit will
simulate the assertion of
writing
a
#
to
this
bit
will
simulate
the deassertion of OCC.

OCC;

SIMATTN

Simulate

MPIB

SEL

this

bit

set,

writing

simulate

assertion

this

will

simulate

deassertion

Buffer

Select.

writing

Maintenance

When
bits

When

will

ATTN;

the

ATTN.

bit

ATTN.

Massbus

Data

Input

this bit is set to a 1, the
(B<15:98>) of the MDIB will

upper eight
be sent out

from
bits
@7
through
008
of
the
diagnostic
register if the diagnostic register is read.
When

the

bit

the

MDIB

(BK@7:00>)

bits @7 through
if it is read.

22:21

MAINT

MFAIL

ONLY

1lower

will

the

eight

sent

diagnostic

out

bits
from

Read/write with no effect.
writability of these bits.

Used

test

Massbus
when MM

Fail

1is

asserted

Fail

(read

only).

set.

MRUN

Massbus

Run

MWC LK

Massbus

WCLK

ME XC

Massbus

EXC

NCTOD

Massbus

METOD

15:13

MDS

Massbus

Device

12:8

MRS

Massbus

7:0

U/L

MDIB

the

Maintenance

(read

only).

(read

only).

(read

only).

Select

(read

only).

Select

(read

Upper/Lower

MDIB.

3-18

only).

the

3.6.7
Selected MAP Register (SMR)
This
register 1is
read-only
and
has
register

This

(Paragraph

the

‘through

3.6.9)

contents
the

but

the

virtual

MAP

same

only

address

the bit assignments of the

the

valid

format as

when

pointed

Figure

MAP

BUSY

set.

bits

3-7

illustrates

selected MAP register.

3.6.8
Command Address Register (CAR)
This register is read-only and valid only when DT BUSY is set. It
contains the value of bits 31
through @68 of the SBI during
the

command/address
part of
3.6.9
The MBA

MAP Registers
contains 256 MAP

by address

to @#7.

through

represent

bits

and

write

written

registers,

bits

bit,
P9

the MBA's next data

through

are

when
a

and

there

MAP

are

Bit

each

#8's

the

data

while
a

data

MAP registers

physical

for

page

MAP

transfer

,
may

which

(intended

respectively.

31 of the

all

transfer.

future

frame

transfer

can

a valid

use),

number.

registers

operation

selected

and

Bits

only

progress.

progress

will

be ignored and cause the setting of PGE and interrupt the CPU at
the end of a transfer if IE is set. Figure 3-7 illustrates the bit
assignment of the MAP registers.

VALID BIT

—

08407

16415

24,23

PHYSICAL PAGE FRAME NUMBER
TK-0715

MAP Registers

Figure 3-7

3.7

DRIVE

The

registers

The

address

the

drive's

unit

controls

the

within
a

drive

particular

number

drive(s).

and
To

contain
register

the

Obtain

the

Locate

the

drive

the

row and

base

assigned

calculate

procedure outlined

desired

the

drive

information.

drive

dependent

level

the

MBA

address

that

below.

address

various
in

the

column will

number

Table

MBA

the

from Table

3-8.

and

The

3-2.

drive

number

intersection

for

Add the MBA base address to the register offset to obtain
the

address.

3-19

Example
To determine
with

MBA

base

MBA

§2

drive

number

20010000

Since Massbus drive
convention has been
1.

number

address

Intersection
Register

the address of register
with a TR level of ¢8:

writes

and

number

drive

number

registers

608
200173608

are

only

low

bits

wide,

the

following

adopted.
only,

the

bits

the

longword

will

written.
2.

reads,

and the
16 bits

the

drive

will

MBA's Status Register
(B<31:16> of
the SR)

supply the low 16 bits
(SR) will supply the upper
when a drive
register
is

read.

Table
MBA

Base

Address

Drive

3-8

(Value

Drive

Address

from

table

Conversion

below)

Number

30
g1

400 | 480 | 500 | 580 | 600 | 680 | 700 | 780

@2
@3

408 | 488 | 508 | 588 | 608 | 688 | 708 | 788
49C | 48C | 50C | 58C | 60C | 68C | 70C | 78C

g4
@5

410 | 490 | 510 | 590 | 610 | 690 | 710 | 790
414 | 494 | 514 | 594 | 614 | 694 | 714 | 794

418 | 498 | 518 | 598 | 518 | 698 | 718 | 798

41C | 49C | 51C | 59C | 61C | 69C | 71C | 79C

404 | 484 | 504 | 584 | 604 | 684 | 704 | 784

420 | 4A0 | 520 | S5AQ | 620 | 6AQ | 720 | 7A0Q

424 | 4A4 | 524 | 5A4 | 524 | 6A4 | 624 | 6A4

@A
@B

428 | 4A8 | 528 | 5A8 | 628 | 6A8 | 728 | 7A8
42C | 4AC | 52C | 5AC | 62C | 6AC | 72C | 7AC

gC
@D

4390 | 4B@ | 530 | 5B@ | 630 | 6BO | 730 | 7BY
434 | 4B4 | 534 | 5B4 | 634 | 6B4 | 734 | 7B4

438 | 4B8 | 538 | 5B8 | 638 | 6B8 | 738 | 7B8

43C | 4BC | 53C | 5BC | 63C | 6BC | 73C | 7BC

3-20

address

CHAPTER

MBA FUNCTIONAL/LOGIC DESCRIPTION
GENERAL

4.1

This chapter provides a functional description of the RH780
Massbus Adapter. Logic descriptions are included in subsequent
paragraphs, where necessary, to clarify operation of the MBA. The

chapter is divided into four sections: MBA/SBI interface, internal
data

registers,

with

familiar

control

and

paths,

material

the

reader

The

paths.

chapters

preceding

should

and

(REV B or

timing diagrams in the RH780¢ Field Maintenance Print Set

The

later).

discussion.

set

Figure 4-1

this

throughout

referenced

will

information

from

Massbus

RH788

the

block diagram

the

Adapter.

INTERFACE

MBA/SBI

4.2

MBA/SBI

The

accepts

interface

when

SBI

the

recognizes itself as the intended receiver. Figure 4-2 is a block

interface

diagram of the interface. The various components of the
are discussed in the following paragraphs.
SBI Decoding and Validating

4.2.1

(Overview)

registers require one or

CPU transfers to or from MBA (or drive)
two

successive

the

command

cycle

first

The

cycles.

transfer

SBI

always

contains the command/address. The second contains the data word if
was

write.

The command/address placed on the SBI data lines by the CPU at T@

The

T3.

latched

the

into

loaded

transceivers

SBI/MBA

between

lapse

time

between

assertion

T2 and

T3 and

latching

and

the input in the transceivers provides deskew and settling time to
for any propagation delays on the SBI.

compensate

The parity of the latched information is then checked and the TAG
the

tag

address

will

not

continue

check

MBA only recognizes

the

read masked,

and

field

decoded.

command/address,

the

address

SBI

device

preselected

MBA

MBA's,

information

1is

B<14:11>

the

a confirmation

circuits

will

(no

the

MBA

1is

determine

compared

processed,

response).

the

with

nor

In this case,

will

the

interlocked

write

masked

If the MBA recognizes the

SBI

mask

data

issue

and

transfer

lines

SBI

data

SBI

commands:

the

MBA

during

the

only),

1longword

interrupt summary read.

(MBA

indicate

confirmation

BUSY

read

the

CPU

a valid

receipt of the

asserted)

not

command,

command/address has been received correctly.
two cycles after

write

masked,

address and is not performing another

operation

function bits
ACK

following

(entire

the

interface

following SBI cycles until a valid command/address is latched.

The

the

If the address is not the

intended recipient of the SBI command.
issue

determined

verifying

the

that

the

Confirmation occurs

command/address.

4-1

and

the MBA will

MBA/SBI INTERFACE

MBA INTERNAL REGISTERS

M8275 SLOT |

INT BUS

M8276 SLOT 2

INTERNAL BUS (TRI-STATE)

DRIVERS

(TRI-STATE)

MSI

INT BUS

CONTROL

RECEIVERS

STORE

(R/W,ID)

INTERNAL

MIR
mSI

DECODE

c/a

| FUNCTION | rw cmD

DRIV

CHECK

MS!

g_?g;sm

ADDRESS/

TAG

CONTROL/

ESEL

—

XCEIVER/

—

ISR

LATCH

—»|

INTERNAL
vALID

ISR

mS|

{\
(RO

]

:|J>

MAP

MIR T

CHECK

—']
1

MsI

L
e |CONF
o (Transmim)
VALID ISR

(

RECEIVE

) N/R

mS!

INT BUS

MUX

RECEIVERS

MSI

CMD/ADRS

)

— — — —{BUSY

STROBE RS [

OPERATION

]

.
ADDRESS

IREG SEL

S8l

REGISTERS

VIRTUAL

INT/EXT)
MIR

MSI

STATUS

MSI

MUX SEL

[—RETRY

AND ENAB [*—1
MDP

OUTPUT DATA MUX
(8:1 TRI-STATE)

INTERNAL BUS (TRI-STATE)

)

ISR DATA
TK-0719

Figure

4-1

MBA

(Sheet

Block
of

Diagram

MASSBUS CONTROL PATHS

MASSBUS DATA PATHS

4
m8278 SLOT

M8277 SLOT 3
INTERNAL BUS {TRI-STATE)

INT BUS

RECEIVERS

MDP

MASSBUS

MCP

DATA IN

BUFFER
SILO

MDP

]

DATA IN
BUFFER

MASSBUS

CONTROL

»| CONTROL

‘

MDP

PATH OUT

MUX

MCP

2:1

MDP

’

MASSBUS

WRITE

IMASSBUS

COMPARE

(DATA PATH)

CHECK

(CONTROL

XCEIVERS

MDP

13 4

XCEIVERS

PATH)

MDP

)

SILO

MDP

]

MASSBUS

MASSBUS
PATHIN

MASSBUS
OUTPUT

SEL

DATA

ZHS

(TRI-STATE)

ouT

MCP

MDP

DRIVE/REG

CONTROL

le—]

SNASSYW

DATA
MUX

MASSBUS

CONTROL

ENAB e

BUFFER

MODP
l

OUTPUT DATA MUX

(2:1 TRISTATE)

MDP

MUX SEL
[*—| AND ENAB
MIR

INTERNAL
BUS (TRI-STATE)

TK-0720

Figure 4-1

MBA Block Diagram

(Sheet

2 of

, 32

INT BUS

PARITY

1D
SAVED 1D —»{
HARDWIRED ID —

3
PARITY

cHeck

PROK I cueck

MSIF

MSIC

BYTE
MASK

ADRS

L
BYTE

y
ADRS

REQUEST

CHECK

MSID
l

MSIF
|

MSIH

)
VALID CMD
1

DECODE
|

IFUNCflON

SBI
XCEIVERS/
LATCH

SBI BUS

BUSY

MSIL

RCLK (MSIR)

]

TAG

RCONF

C/A

MSI CONTROL STORE

MSIE

CYCLE

INTERNAL
BUS

I
READ/
WRITE

(TRISTATE)

MSIN, P

CHECK

MSIF

DRIVERS

MSIE |

MSIM

[ savenio

#CLK VALID CMD (MIR)
W
»WRITE
FCN (MIR)

MSID, E

DECODE [ ISR

+CLK EXT CMD (MCP)

CS READ/WRITE

VALID

Wb
RD

ISRMSIF,L

(MIR

- W

EXP

]

<\r:>

= EXP WD (MIR)

-» CLK DIB2

MSIF

WD ACK

MSIA, B

TCLK (MSIR) f

MSIF
¥

RD ACK

((:MEP)

CLK

DIB1

—» RCON (MIR)

INTERNAL READ READY —
(MCP) EXTERNAL READ READY—p
(MIR) COMMAND READY
)|

RequesT [ SEND TR

LOGIC

s INT READ REQUEST

—* EXT READ REQUEST

—» COMMAND REQUEST

)

BUSY

Eggr(';RMAT'ON
DT R/W (MDP)—{ CONF
RETRY (MIR)
MSL
CHECK | N/R
| ACK
(MIR)
ERROR
ARB OK—»

READ

,?:J&NG
MSIF
<:;:::::)

/SBI XMIT

< DATAMUX

LCENERS
MSIN. P

ISR DATA

N
Figure

REQ INTR (MIR}

(HARDWIRED)
(FROM TR LEVEL)
TK-0786

4-2

MBA/SBI

Interface

If the MBA is busy, a BUSY confirmation signal

is sent to the CPU
then

will

CPU

The

use of the SBI and repeat the transmission until

for

rearbitrate

command/address.

wvalid

the

response

the command/address

is accepted or until

the CPU times out.

It should be noted that there are two busy indications in the MBA,

DT BUSY and

MBA

MBA BUSY.

to or

progress

registers

asserted,

transfer

read

BUSY

SBI

issued

the

commands

may

MBA's

the

that

DT BUSY indicates that a data

MBA

will

duration of a data

and

some

respond

with

MBA

BUSY

all

confirmation

for

the

ms).

During

data

8-byte

burst.

cause

asserted

remains

(typically 106--190

the

indicates

MBA

While

use.

1in

BUSY

CPU.

the

transfer

written.

interface

set,

While DT BUSY is

storage media.

from the

transfer, MBA BUSY will be set or reset as the MBA uses the SBI to
transfer

Typically,
remain

data

bytes

clear

until

enough

may access

MBA registers.

recognizes

MBA

the

command/address causing

and/or

memory

the

data

has

accumulated

expected

function

read/write

described

later.

Note

the

that

parity

write

but

the

command

CPU to

abort

the

flip-flop

checking,

decoding,

invalid,

attempted

set,

and

BUSY

MBA

depending

will

functions

These

transfer.

appropriate

the

performed.

another

the CPU

receipt of the

issued two cycles after

data

1 us and will

While MBA BUSY is clear,

command/address,

the

receipt

the

for approximately

address

error confirmation will be

After

from

set

(approximately 1@ us).

transfer
the

MBA BUSY will be

validation

the

functions

described in the following paragraphs are performed in parallel by
the

SBI

interface.

Timing (MSIR)
4.2.2
All data transfers between

six

signals:

timing

BUS SBI PCLK L,

signals

BUS SBI

are

generated

time

states

signals

timing

signals

derived

BUS

derive

illustrated

MBA operations

4.2.3

four

and

the

The

SBI

SBI Control

control

and

BUS

the MBA are synchronized by

the

CPU.

time

states:

Tl,

SBI

cycle

T@#,

(200

relationship

T2,

ns).

These

these
and

T3.

SBI

first

longword,

longword

address.

(MSIA,

MSIB)

the

transceivers

1is

to synchronize

data

Data

Transceivers

to and from the MBA is loaded and latched
transceivers

transferred

(Figure

any

transmitting

information

and

MBA

SBI.

and

When

These

timing

4-2)

(T@, transmit) or RCLKA and RCLKB (T2, receive).

command

timing

The major

the

are used

signals

These

uses

MBA

The

PCLK H,

SBI

BUS

SBI TP

PDCLK L.

their

the

SBI and

and BUS SBI

Fiqgure 4-3.
with

PDCLK H,

define

Information transferred

TCLKB

the

SBI

transmitted

1is

1loaded

4-5

the

TCLKA

SBI/MBA

operation

control

command/address
the

and

SBI at the appropriate

and

the

data

time.

SIGNALS

BUS SBI PCLK H _l_

BUS SBI PCLK L

]

BUS SBI PDCLK H

L |

BUS SBI PDCLK L

MSIR INT DIF TOCLK H

MSIR INTDIF TOCLK L

MSIR INT DIF T1 CLK L

MSIR INT DIF T2 CLK H

MSIR INT DIF
T2 CLK L

[

[]

MSIR INT DIF T1 CLK H

9-v

e
e

SBI

TIMING

§¢EJ

BUS SBI TP L

]

N |

N N

BUS SBI TP H

150 NS|50 NS 150 NS 150 NS 150 NS |50 NS |50 NS |50 NS 150 NSI150 NS | 50 NS|
50 NS|
I
|
|
|
|
|
|
|
|
|

MSIR INT DIF T3 CLK H

MSIR INT DIF T3CLK L

r ECL LEVELS

[]

TIMING

SIGNALS | iR, MIRV, MDPW, MCPK TO H, MSIR RCLK H

MSIR, MIRV, MDPW, MCPK T1 H
MSIR, MIRV, MDPW, MCPK T2 H, MSIR RCLK H

—

]

[

MBA

MSIR, MIRV, MDPW, MCPK T3 H

]

> TTL LEVELS

MSIR INT BUS OCLK H

MCPK INT BUS ICLK L

MSIR STROBE MAP H

:
I

[

I
|

SBI CYCLE

200 NS

]

I
|
T1

|
T3

|
I

SBI CYCLE

200 NS

|
SBI CYCLE

TO
|

200 NS
TK-0781

Figure

4-3

1Internal

Timing

When

errors

command/address

and

identify

decoded

transferred,

establish

or
1interrupt
destination of

4.2.4

parity

incoming

EBrror

check

Checking

decoded. Each control
parity bit; each byte
parity

bits.

the

control

and

even

function

provides

format

and

checked

for

1information

the

performed

parity

(read,

1identify

the

detecting

single-bit

write

source

and

(MSIC)

means

Figqure

4-4

shows

how

the

errors

parity bits

are

field is parity checked to produce a single
of the address is parity checked to produce

These

data

number

the

read),

information.

two

received,

the

summary
the data.

Parity

The

bits

are

fields,
of

bits

configured

plus

their

(even

parity).

have

data

longword containing an odd number of

that

parity
Any

bits

the

contents

bits,

will

always

control

field

is assumed

to be

error.

there

will

are

parity

generated.

errors,

These

signals,

verify

the

interface

circuits

CNTRL

signals,

1incoming

continue

PAR

together

1information

processing

and

with

and

the

DATA

other

PAR

enable

REC SBI PARO H

CONTROL " CNTRLPAR ERR H
PARITY

CHECK

— CNTRL PAR OK H

FROM

DATA

—— DATA
PAR ERRH

SBI

PARITY

MASK

M
H———

REC SBI PAR1

PARITY

DATA

RECEIVERS
(4 DATA BITS

CHECK

8 BITS

DATA PAR OK H

PER PARITY BIT)
TK-0760

Figure

4-4

Parity

4-7

Check

(MSIC)

other

command/address

data.

TAG

wvalidation
or

If a parity error is detected, the parity check circuit produces a
fault indication CNTRL PAR ERR H or DATA PAR ERR H, depending on
the source of the error.
Either signal will
inhibit
the
tag
and
function

decoding

command)

and

set

(preventing

the

MBA

from

configuration/status

recognizing

parity

the

fault

flag
causing
assertion
of
the
fault
line
to
the
CPU.
The
continues to assert fault until the program examines the fault
negates the condition.
(Refer to Translation Buffer, Cache and
Control Technical Description, EK-MM78@-TD-001.)

4.2.5
If no
The
the

Tag
parity

tag
SBI

Decoding (MSID)
errors are detected,

field
and

identifies

the

relationship

the

type

the

field also functions in conjunction
special read and write conditions.
The
decoding
of
decoder
(Figure
transfer

not

the

tag

4-5).

field

The

MBA

decodes

tag

information

transferred

and

data

fields.

with

the

mask

field

accomplished

and
SBI

field.

decoder
is
enabled
(NOT USING SBI L and

progress

the

CPU

over

The

3-to-8

provided
XCYCLE L

tag

define

1line

an
are

MBA
not

asserted),
and
there
are
no
parity
errors.
Tag
bits
<2:0>
are
decoded
to
produce
one
of
four
outputs:
READ DATA,
WRITE DATA,
CMD/ADRS,
and
ISR
(Interrupt
Summary Read).
The
tag
is
decoded

(provided a parity error did not occur)
during every SBI cycle.
When
a
command/address
is
received,
the
tag
decoder
generates
CMD/ADRS
H.
This
signal
is
sent
to
the
confirmation
circuit.
Further decoding and validation checks are then performed.
If the
decoded
tag
indicates
the
read data,
write data,
or an ISR,
the
appropriate output will
set the corresponding flip-flop preparing
the MBA for execution of the first data longword during the next
SBI cycle.

4.2.6
Address

Address

Validation

validation

corresponds

(MSID)

determines

that

the

address

assigned

the

simplified
block diagram of
the
logic.
address
validation
1is
accomplished
by
<14:11>

with

the

preselected

corresponds

arbitration

level.

bits

address

address
address

single

code

<14:11>

1is
invalid
and
bits and the TR

output

REC

SBI

and

VALID

address

the

(H).
H,

ADRS

This

REC

level

and
the

(TR

identifying

received

MBA.

from

Figure

seen

the

4-6

this

SBI

figure,

comparing
address
bits
SELA:SELD). TR SELA:SELD

the

MBA

and

represents

the

TR SELA:SELD do not compare
(#),
MBA will
ignore
the command.
If

the
the

bits are equal,
output produces

SBI
B<1%,27:15>H
VALID
ARDS
H
is

the comparator
ADRS OK H when

produces a
ANDed with

(which must be
all
zeros),
generated
by
decoding
the

selection bits,
REC SBI B<@#9:93>d, which select
the internal or external register addressed by this command. ADRS
OK
H
is
sent
to
the
configuration
logic
along
with
CMD/ADRS
H

described

Paragraph

4.2.3.

4-8

NOT USING
SBI L

XCYCLE L

CNTRL PAR ERR H———L_O

-O

DATA PAR ERR H

——— WRITE DATA

‘ ————

TAG

REC TAG2H

DECODE ————— CMD/ADRS

RECTAG1H

» READDATAL,H
———

RECTAGOH

TAG

DATA TYPE

21110

ISR

11110

WRITE DATA

11011

CMD/ADRS

ol1]1

READ DATA

ojo}oO
TK-0757

Figure
REC SBI

B<11:14>

4-5

Tag

Decoding

(MSID)

COMPARATOR

TR SEL A-D—»

REC SBI <27>H

FROM

DATA

XCEIVERS

REC SBI

fi B<10,15:26>—
(ALL 0'S)

REC SBI

B<03:09>
(REGISTER

L SELECT)

Figure

4-6

Address

COMB

ADRS OKL

LOGIC

—» VALID ADRS H

CcOmMB
LOGIC

————— [NT OR EXT REGISTER SELECT

‘
Validation

4-9

-+» MAP ADRS
Simplified

Block

TK-0761

Diagram

4.2.7

Function

Since

the

MBA

mask

bits

order

enable

and

will

the

VALID
4-7

mask

the

only

respond

decoder

that

longword

from

the

generates

INVALID

FCN

format

specify

the

type

illustrates
or

(MSID)

command/address

the

FCN

command/address

Figure

Decoding

the

function

valid the decoder
confirmation.

function

bits

generates

4.2.8

MBA

BUSY Generation

MBA

BUSY

asserted

SBI

command.

The

when

busy

reads

SBI

WRITE

Function
of

<31:28>

bits

command

which

Logic

(MSIE)

flip-flop

interface

1is

write

the

1's

READ

FCN

the

command.

process.

FCN

MBA/SBI

all

<31:28>

INVALID

the

writes,

FCN

read

decoding

must

set

address

returns

1is

wupon

are

processing

the

not

error

successful

completion of the command/address decoding and validation process.
If MBA BUSY is already asserted, a confirmation signal
(SEND BUSY
CNF
H)
1is
returned
and
the
function
1is
not decoded.
Write
to
internal
register
functions complete
immediately and do not
set
MBA BUSY.

MBA BUSY generation

REC SBI B 31 H

logic

illustrated

Figure

REC MASK <0:3> H { :3}—0 EN )

> WRITE FCN H

—» READ FCN H
DECODE

—® VALID FCN H

—— INVALID FCN H

RECSBIB 30 H——
RECSBIB29 H

RECSBIB 28 H

DECODED FUNCTION BITS

B31 | B30 | B29 | B28
WRITEFCN |

WRITEFCN [

READFCN

0
TK-0762

Figure

4-7

Functioning

4-10

Decoding

(MSID)

4-8.

REC BUSY CMD H

:D——-MBA BUSY H

INIT COND L—

RESET

LOGIC

SEND BUSY CNF H

> .

VALID FCN H—

CMD/ADRSH
ADRS OK H
TK-0759

Figure

When

valid

followed

MBA BUSY

by
is

write

after

has

TRA

MBA BUSY

command/address

the

cleared

occurred

time period,

When

read

sent

has

the

requested

data

put

drive

MBA BUSY

cleared

after

set

Generation

MBA BUSY.

decoded,

granted within

received.

NED

assertion

was not

the SBI

4-8

specific

the

TRA

and

MBA BUSY is cleared.

the

SBI

254

When

specific

after

SBI,

occurred,

time period.

received

not

ACK

MBA BUSY is not asserted when there is a parity error and we are
expecting write data (EXP WP H and PAR ERR H asserted) or a write
data error (WD ERR H) occurs. WDERR H is asserted when we are
expecting write data, but do not receive it. SEND BUSY CNF H is

when

asserted

command/address

received

and

function

CNF1l

the

has

(MSIJ,
MBA

read

encoded
or

write)

CNF@ | CNF1

be performed.

MSIM)

informs

the

CPU

whether

been received correctly and,

command/address,

are

function

the MBA can process

decoded

(depending

specify one

| Response
No

Response
Acknowledge

Busy

(BUSY)

Error

(ERR)

4-11

received

the

and

asserted

valid

transfer

o=
oI

logic

e s qu e I

information

CNFg@

indicated

Confirmation Logic

4.2.9

Confirmation

1is

BUSY

MBA

has

(N/R)
(ACK)

not

the

command.

upon whether

four

in the case

responses:

the

ACK

the
cause

will
cause

anticipated

the

retry

When

the

MBA

When

the

data

response to a successful data transfer. ERR
transfer to be aborted, and N/R or BUSY will

data

the

data

the

transfer.

receiving

transfer

from

nexus
a

Massbus

generates
storage

the

response.

device

memory,

memory
dgenerates
the
response.
During
a
data
transfer,
synchronization of the confirmation codes with the command/address

or data

word

accomplished

4.2.9.1

Response

(read

write)

will

information

1is

asserted),
cleared),

(VALID
the

FCN

function

write
MBA

the
and

data

will

generates
be

received
there

-- When

response

MBA

cannot

the

command

specified

CS WRITE

processing
must

Acknowledgment

FCN

read

write

and

data

the

MBA

receives

the

transmitting

ACK

(CMD/ADRS

ADRS

command

specify

write

was

successful

WRITE

DATA

the

read

(ID
OK
H,
READ
DATA
H,
and
When
the
received
information

are

function.

XMIT

the

read data
or
if the
EQ L
BUSY

not
is

MBA

write

FAULT
data

(WD

will
ERR

also
H),

was

transfer

command.

response

generation.

Figure

4-9

asserted

the

MBA

SEND ERR CNF H ——

the

logic

RESPONSE

SEND BUSY CNF H —
—— XMIT CNF1 H

——— XMIT MBA FAULT H

CLR

TIBH

PWRF + UNJAM H
TK-0785

Figure

4-9

Response

4-12

Generation

generated when MBA
processing
a
data

ENCODE

CLK

unexpected

(PAR ERR H),
(XMIT/REC
1ID

— XMIT CHFO H

SEND FAULT H —»

ERR CNF
invalid

there

receives

will be
MBA
1is

illustrates

SEND ACKH ——»

The

received

READ
DATA
PEND
H
are
is not wvalid,
an error

(UNEXPECTED RD H), if a parity error occurs
transmited and received IDs are not equal

asserted). A BUSY confirmation
asserted
indicating
that
the

when

(received

confirmation will be sent to the transmitting nexus. SEND
H will be asserted when the command/address specifies an
error

BUSY

asserted).

data

function

occurs

and

(MBA

valid

data

when

received

another

data

nexus.

asserted)

acknowledge

errors

address

was

flip-flop.

(SEND

<correctly.

must

acknowledge

correctly
asserted).

(MSIM)

generated

asserted).

and

cycle

Generation

Acknowledge

command/address

by the

(MSIM)

used

1in

4.2.9.2

Confirmation

Check

(MSIJ)

When

response to
the MBA for
received data,
the
interpret the response in order to react to
data

transfer

asserted.

ERROR
RETRY

successfully,

received

The

MBA will
memory.

CLR

C/A

MBA.

This

was

MBA must be able
to
the transfer.
If the
WD2
ACK
H
will
be

detected

be asserted. The MBA will retry to
any one of the following conditions

retry

XCYC

will

the

assert CLR

until

1is

timeout

asserted

occur
data

C/A

when

transfer.

XCYC

One

memory,

transfer
exist:

SET

(SET

ERR

N/R

CNF

any

occurs

during

received

has

the

for

1indicates

been

the

retry

late

received

status

within

occurs

following

the

error

conditions

will

received

transfer

the

that

received

following

first
no

response

the

data

MBA.

N/R

CNFL

conditions

No ACK
CPU

C.
d.

N/R received from memory
No ACK received for the second

ACK

for

the

first

requested

SET

memory

asserted

exists:

not

longword.

the

did

data

Memory is BUSY
N/R received from memory

requested

transfer

ACK

occurs

clear

data

b.
C.

when

data

generates

N/R received from memory
No ACK received for the first longword
Memory is BUSY
No ACK received for the second longword.

from

occurs

occurred

error

CNF L will
L) data if

a.
b.
C.
d.

SET

has

memory

longword

data

longword.

REQ COMPLETE L will be asserted when the data transfer requested
is complete or when a nonrecoverable error occurs. Figure 4-19 is
a

simplified

diagram

the

logic

that

performs

the

confirmation

check.

4.2.10

Interface

Fault

Assertion

Faults that occur during the SBI decoding and validation process,
such
as
parity
and unexpected
read
data,
set
a
corresponding

interface fault flip-flop. This output sets the appropriate bit in
the configuration/status register and asserts the SBI fault line.
The

fault

line

status

will

bits

explanation

remain

asserted

until

and

negates

the

fault.

the

various

faults.

the

program

Paragraph

examines

3.6.1

the

provides

—

REQ COMPLETE L

—» WD2 ACK H

RECCNF 1 H —»

COMBINATIONAL [— SET N/RCNF L
LOGIC USED
TO DECODE

REC CNF O H ——

— SET RETRY L

MEMORY

CONFIRMATION

|——9 CLR C/A XCYC L
— SET ERROR CNF L

TK-0784

Figure

4-1¢

Confirmation

Check

4.2.11
When

Request Logic (MSIK)
requesting control of the

external

read,

CURRENT

REQ

(indicating

which
sets
applied to

the

send

internal

SBI to respond to an internal read,
data the request flip-flop produces

transfer

that

SBI

flip-flop.

operation

output,

SEND

1Its

assertion of
the MBA's
SBI cycle.
If
the MBA's

arbitration logic,
assigned TR level at T@

occur),

which causes
the
of the following

arbitration

line
represents
the
highest
priority,
the internal
register arbitration logic issues ARB OK,
allowing the MBA to assume control of the SBI. The combination of
SEND
TR,
ARB
OK,
and
the
function
requested
may
initiate
many

functions

such

setting

starting the timeout
within
the
internal
Figure
4-11
is
accomplish this.
4.2.12

Timeout

Interface

the

interface

MBA

1logic

control
diagram

and

pending

and

flip-flop,

transfer

functions

paths,
and
data
paths.
of
the
logic
used
to

sequence

read

data timeouts on the
in
Figure
4-12.
The

shown

counters

timeout

MBA are
counter

cascade.

(SET

TIMEOUT

can

occur

when

arbitrating

for control of the SBI.
The counter will
cycles after an attempt to get the bus (SEND TR

wait up to 512 SBI
H)
before the timeout
a

data

control

(MSIH)

timeouts

accomplished
by
the
consists of two 4-bit

read

and

registers,
simplified

Logic

sequence

the

operation,

during
within

read

512

SBI

(RDPD1

H),

SET

data

occurs.

transfer.

read

the

data
read

timeout can occur only
data
is
not
received

cycles after memory has accepted
TIMEOUT L is asserted.

4-14

the

read

command

—>CMD REQBH

INT RD READY H

INT RD REQ H ——

—— INT RD REQ

CSWRITE FCN L —
EXT RD REQH

COMBINATIONAL
LOGIC

REQUEST

EXT RD READY H

GENERATION
LOGIC

:XT OP DONE + TO H—

CMD RDY H

MASTER INIT B L —

—— EXT RD REQ
———

CMD REQAH

——

CMD REQ L

CURRENT REQH

REQUEST

CURRENT

FLIP-FLOP

REQH

TK-0763

Figure

4-11

Request

Logic

(MSIK)

CMD REQBH

SET IS
TIMEOUT L

T3H

CMD REQ B H—
SEND TR H—]

coOMB

RDPD1 H—{

LOGIC

SET RD

CRY

TIMEOUT L

T2H—>»

Ccup

COUNTER

T1BH

READ DATA PEND H —
TK-0758

Figure

4-12

Timeout

Logic

(MSIH)

4.2.13
Command/Address Generation (MSIM)
The
command/address
format
that
consists
of
a parity,
tag
1D,
function,
and
address
fields
is
used
to
process
data
transfers

from

the

MBA

During

the

which

bytes

logic

associated

receiving

nexus

command/address,

data

(read

with

BYTE MASK

the

(memory)

mask

write)

mask

via

field

are

the

SBI.

encoded

valid.

Figure

4-13

specify

bits.

\\\\\\\\‘

<1-3:1-0>H

MASK 1
4

MUX

ALL 1'S

————

DT READH

XMIT MASK 3 H

‘

XMIS'I|'<

——
> XMIT MASK 2 H

MGX

XMIT MASK 1 H

———

XMIT MASKO H

BYTE MASK

<2-3:2—-0>H

fm( —

2
MASK

MUX

4
ALLO'S

STB

T1L—

INT RD REQH

SEND TR H—

H
EXT RD REQ

A HCMD REQ

ENABWDL MUX H———
TK-0782

Figure

4-13

Mask Generation

4-16

(MSIM)

the

When
of

INT

REQ

internal

bits

send

the

READ
will

all

EXT

external

zeros.

REQ

MBA

asserted

read

the

mask

will

the

MBA

device

asserted),

the

mask

bits

be all 1's. During a write to memory indicating a read
device, mask bits BYTE MASK 1<3:0>H will be selected. These
bits indicate which bytes in the first transferred quadword

from
mask

cleared;

SEND

transfer,

cause
to

data

indicates

will

where

command

This

write

read

During

memory

(indicating

and

REQ A

CMD

have
valid data.
In this case DT READ H,
SEND TR H, and CMD REQ A H
will be asserted.
ENAB WDI MUX H indicates transfer of the
first
data
quadword.
When
this
1is
asserted,
BYTE
MASK
2<3:0>H
1is
selected, which indicates which bytes of the second quadword are
valid. The mask bits of the second quadword will be
mask bits are latched through multiplexer at Tl and

MBA/SBI

control

transceivers.

The

field

the

identifier

for

the

MBA.

The

with the ID field is illustrated in Figure 4-14.
be derived from either of two sources, depending
to

A-D

performed.
H),

which

The

first

1is

representative

assigned at system
select multiplexer

talk to
SBI/MBA

latch
and

to
of

memory.
control

every

the

hardwired

the

MBA

The
the

logic

associated

The ID
on the

field can
operation

MBA

priority

build time.
This is always available at
input. The hardwired ID is used by the

The second ID
transceivers.

time

applied

source

all zeros.
applied to

(TR

SEL

1levels
the ID
MBA to

source is the received ID from the
This
is loaded
into
the
saved
1ID

the

MBA

receives

the

select

command/address

multiplexer.

The

from

saved

the

SBI

used

return data to the CPU. ID selection is determined by the state
CMD REQ. When requesting memory data, CMD REQ is high and the

hardwired

(TR

SEL

A-D

1is

transmitted,

wvia

the

SBI/MBA

transceivers. When the MBA is excepting read data from memory, the
received ID is compared with that of the MBA.
If the received ID
and

the

MBA

compare,

the

read

data

has

arrived,

assuming

that

all
other
decoding
and
validation
<checks
are
performed
satisfactorily. The MBA also monitors the ID on the SBI while it
is

asserting

not

equal,

data
the

the

SBI.

equal

the

comparator

received
issues

and

fault

MBA

are

indication

setting
the
appropriate
configuration/status
register
fault
bit
and
asserting
the SBI fault line.
The fault
is asserted
only if
the
the

MBA is putting
same
as
the

situations, the
fault signal.
The

tag

field

data on the SBI and the
one
the
MBA
asserted.

fault

can

determined

cleared

the

ID on the SBI
As
in
other

INIT or

state

deassertion

SEND

and

is not
fault
of

the

select

input CMD REQ B. When TR H is high and CMD REQ is low (the MBA is
responding
to
a
CPU
read),
the
encoded
output
of
the
tag
multiplexer

represents

read

data

4-17

format.

SEND TR H

XMIT

XMIT TAG

TAG
MUX

<2:0>H

SELECT

CMD REQ BH

RECID4 H—»
ID

REC ID3 H—»

LATCH
XMIT

REC ID2 H ————»

XMIT ID
<4:0> H

MUX

REC ID1 H———¥
REC IDO H——®

CLK

VALID CMD H‘———T
HARDWIRED ID

(TR SEL <D:A>H

SEND TR

CMD REQ

OPERATION

NONE

READ DATA

WRITE DATA

COMMAND/ADDRESS
TK-0783

Figure

4-14

Tag

and

4-18

Generation

(MSIM)

Conversely

(during

data

transfer),

the

tag

field

represents

command/address
TR H is low and

when SEND TR and CMD REQ are both high. When SEND
CMD REQ is high, the tag field represents a write
data format. The tag field remains latched in the tag multiplexer
until receipt of Tl. At this time the tag field is available to be
loaded
1into
the
<control
transceivers
for
subsequent
SBI
transmission.

Figure
4.2.14

Mask

seen

the

specifies

three

with

the

tag

4-15,

the

MBA,

the

mask

field

type

read

data

the

MBA

the

Read

has

types:

Read

Data.

occurred.
but

there

been

has

field

shown

Decoding

that

occurred

4.2.15

associated

Figure

data

error

logic

Normal

The

4-14.

when

CORRECTED

been

error.

Internal

Bus

SBI

DATA

corrected.

and

TAG

data

NORMAL

Interrupt

read

received

which

Read

and

the

SBI

There

are

Data,

and

uncorrectable

which

DATA

1is

Summary Read

data

from

received.

Corrected

data

indicates
has

Substitute,

SUBSTITUTE

has

INT
BUS
O CLK
H
MBA/SBI
interface

Data

the

error

data

1in

has

which

Logic

1latches
data
from
the
internal
bus
into
receivers.
This
occurs
independently
of

decoding and validation process described previously.
select the data to be transferred to the SBI, either

the
the

Multiplexers
internal bus

data or Interrupt Summary Response data
(ISR RESP<15:00>H).
Data
is transmitted to the SBI only if T/R ENAB A L is asserted for the
internal bus data or T/R ENAB B L is asserted for the ISR data.
4-16
is a simplified diagram of the 1logic associated with

Figure

the

functions.

READ DATA L—Q

[~ 71
I

READ DATA PEND L —Q)

H
ID OK
REC MASK
O H

DECODE

SEL C

B SEL B

——

LATCH

—— CLK DIB2
L
—— SET CORRECTRD

| COMB
Logic |

SEL A

CLK DIB1

- SETRD SUB L

REC MASK 3 H —Q

REC MASK 2 H—O

REC MASK 1 H —O
MASK
READ DATATYPE

|[3]2]|1]0

RD SUBSTITUTE

X{x|1][x

CORRECTED DATA

[o{ofo

NORMAL DATA

ofo]ofo

TK-0764

Figure

4-15

Mask

Decoding

RCLK =

ISR RESP <31:00>H —

MBA/SBI

INTERNAL

XMIT SBI B<31:00>H

BUS

BUS MBA INT

ENB

INT BUS0 CLK H—-|

REC SBI
B<31:00>L

SBI

MBA INTERNAL BUS

TRANSCEIVERS

RECEIVERS

B<31:0>H

0c-v

MULTIPLEXER

BUS SBI

B<31:00>H

SO =L INTERNAL BUS

REC SBI B <7:4>H—»{ A

S0 = H ISR RESPONSE

A=B —0O
INTR REQ <7:4>H—»|

—Q
—O

ISR COND H

TCLK

INTERRUPT CPU L

ISR L
TRI-STATE
DATA BUFFER

SBI TO INT CLK
TK-0808

Figure

4-19%

Internal

Bus

ané
Logic

Drive

Interrupt

Summary

Read

Data

4.3

MBA

The

MBA

INTERNAL

internal

REGISTERS

registers

information.

A description

functional

1logic

provided

Paragraphs

Internal

Information

logic

and

their

assertion

from

into

the

Internal

control

logic

function.

The

the

internal

status

function

this

manual.

the

subsequent

diagram

processed

bus

INT

receivers.

the

MBA

the

interface

receivers on T@ following

BUS

ICLK

Figure

4-18

Control

decodes

registers

logic

SBI

internal

SBI

4.3.2

block

and

their

provided

detailed

the

internal bus

the

3.7.9

and

Receivers

received

latched

illustrates

Bus

control

through

description
is

various

each

3.7

paragraphs. Figure 4-17
internal registers.
4.3.1

store

used

the

command/address

perform

the

accomplish

specified

this

select

read

shown

one

write

Figure

4-19.

Selection

one

decoding

the

control

other

bits

path

six

B<@9:08>

output

internal
to

set

registers,

registers

MAP

1is

corresponding

registers,

accomplished

flip-flop.

When

an internal register operation is selected, bits CS B<K@##:82> are
applied to decoding logic that selects the appropriate register.

The

output

enabling

should

the

appropriate

logic

clock.

noted

only

the

control

(if

the

decoding

that

enabled)

can

MBA is processing a data
any

the

set.

PGE
If

will

other

than

attempt

(programming

will

continue

not

implemented

own

these

write

within

The

simple gating

the

these

the

modified

CLK

and

diagnostic

written
a

data

the

during

MAP

very

transfer

data

complex.

made,

transfer

Status,

will
the

the

Each

status,

bit,

which

and

registers,

registers

is composed

and

self-explanatory upon

examination

diagram

Figure

4-17

logic

and

for
a

these

functional

operation

byte
counter,
and
MAP
registers
are
described in the following paragraphs.

4-21

not

block

the

virtual

obvious

with

and

these

associated

MAP

progress

Diagnostic,

control,

time

operation,

the

and

is made to write

status

configuration,

not

logic

The

Control,

the

with

If an attempt

and

control

networks

sets.

registers.

one

during

bit

unaffected.

registers

flip-flop.

read

transfer.

error)

4.3.3
Configuration,
Command/Address Registers
The logic associated with

diagnostic

ANDed

its

address,

and

are

Y INTERNAL BUS
INT BUS

RECEIVERS
INTERNAL BUS
TIRA

CLK

)

WRITE FCN

CONTROL

( MSI)

STORE

(DRIVE SEL,}
REG SEL,

CLK VALID

REG SEL

INTERNAL

[STROBE

MIR INT CS (7:0)

4Tre

1STROBE
WRITE | RS04

MIRB

)

FAULT CONDITIONS

{MSI)

»|

CONFIG
REG
RS00

DATA

4122

STROBE

RS05

STROBE

RSO1

MAP

ISTATUS
STA
REG

RS02

COUNTER
RS04

(SBI/MBA)

DATA
RS02

—

MIRH
RS04

DATA

v
DIAG

3 v
CONTROL

RS05

RSO1

REG

POINTER| | ADRS

v
MAP

DATA

VALID

l
|

2:1

L1 4

| | BUS

BITS

BYTE

e
P

]

413

j~h

[

(MDP)
VAR CNT

DOWN {MDP)

» VAR BYTE

CONTROL

fiflflfifik.ago>

—+ % | cmp/aprs

I
DATA

LvaRcnT
UP

(MDP)

VAR VYTE

"—‘—SNI’ELOWN
|

I'CNTRH4——1jMDm
I

Al
—_—

]

RS06
,

[4:’/{:——-1

]

LOGIC

CNT UP

(MDP}

et P
MASS

MUX gg?;g;

RSO1

DATA

(447

MIRE

RS05

CNTRL

r——=1r-— il
IMAP
| | LOWER

(MCP)

REG

MIRJ

VAR BYTE

RSO3

(MSI)

CPO

MCP)

VIRTUAL ADRS REG RSO3

GEN PAR

v
BYTE

(

STROBE

DT BUSY

fi%%$2314~—

REQ INTR o
(MS1)

170

MIRC,MIRD
RSO0

CLEAR

EXP WD —/

(MS1}
s
(MSI)

INT/EXT| opeRaTiON | RSO2

INT/EXT)

CMD (MSI)

HARDWIRED

lL,ABorRTMBOT

FUNCTIONS

(MDP)

PHYS

CMD/ADRS

’

‘1
DT

» SBI BYTE CNT=0

READ

(Mce)

(MDP)

4120
2

DATA
RSO3

8:1 MUX

MUX SEL

AND ENAB

(TRI-STATE)

MIRR,MIRS

MIRT,MIRU

TRI-STATE

BUS
DRIVER

MIRW ::
TK-0807

Figure

4-17

MBA

Registers

Internal

BUS MBA

8-BIT

REC INTB

INT B<31:00>H

LATCHES

<31:00> H

CLK

INTBUSICLK L ~—|
Figure

TK-0789

4-18 Internal

Bus Receivers

» CSB<07:03> H
L

WRITE FCN H—
SAVED
ADDRESS

LATCHES

MB MAINT MODE H

» CLK DIAG REG H

— LOAD BYTE CNTR H

CS B<02:00> H

& CLKBYTECNTR L

REC INT B<09:00> H

147

L
»CLK VAR REG L

COMB
CLK VALID CMD H

LOG!

—» ADDRESS
L

F—CLK STATUS REG H

|—+CLK STATUS REG L
——»CLK CONTROL REG L

DECODE

——» CLK CONF REG H

CLKIRH

CS B<09:08> H

DECODER

EXPWD H

WRITE DATA L

F-F

—————» CLK MAP H
CLK

TK-0803

Figure 4-19 Internal
Register

Control

4.3.3.1
Virtual Address Register -- The virtual address register
(VAR)
(Figure 4-2¢)
consists of five synchronous, up/down, 4-bit
binary counters.
Its function is to convert the virtual address,
received
from
the
SBI
upon
initiation
of
a
data
transfer
operation, to a physical address pointing to the location of the
first byte of data to be transferred.
Bits VAR BIT<16:99>H are the map pointer bits that select the page
frame
of
one
of
256
map
locations.
The
map
pointer
bits
are
incremented by one each time the physical byte address crosses a
page

boundary

during

data

transfer.

Bits VAR BIT<08:03>
the location of the

are the physical byte address bits specifying
quadword address within the page. These bits
are incremented each time VAR CNT H is received from the Massbus
data paths indicating that a successful quadword data transfer to
or from memory operation has been completed. Bits VAR<K@2:0@>H are
used

pack

and

unpack

the

quadword

into

Note
that
the map
pointer
bits
are
multiplexers. The multiplexers select

bytes.

applied
either

VAR

two

data

select

BIT<16:08>H

B<@7:00>H.

The

purpose

the

multiplexer

the

source

map

the

transfer

transfer,

from
to

operation

the

data

set,

them

provide a means of selecting
as
required,
to support

are selected by the
data transfer busy

the
register
select
bits
are
be read or written directly.

4.3.3.2

MAP Registers

information,

to
be performed.
When
processing
a
flip-flop is set and the map pointer

busy

the virtual address
sent to the maps.

not

The

256

sent

MAP

the

registers

multiplexers
flip-flop is

map,

map

data
bits

allowing

virtual

page

addresses from the virtual address register into SBI physical page
addresses.
This allows
for
data
transfer
to and
from contiguous

virtual
(noncontiguous
translation
(mapping)

physical)
is

memory

described

locations.

Virtual

Paragraph

1.5.1

manual.

write

enable
MAP H

MAP

(WE)
input
(MIRB).
If

(DT
MAP

BUSY

INT

B<31:00>H

MBA

the

enabling
at

the

STROBE

not busy
MAP H and

signals,
DI

location specified by the
virtual
address
register.
stored

this

operation
is
performed
when
the
write
B<K@9:08>H, when asserted, produce CLK

low.

cleared),

address
of

processing a data transfer
CLK MAP H generate the two

MAP WE1lL

1input

the

and

MAP WE2L.

RAM

The

loaded

data

REC

into

the

address bits RAM ADRS<#7:00> from the
The parity bit
for
this data
is also

in the MAP registers.
This
information will
be placed on
the
internal
bus
1if
selected
by
the
internal
bus
output
multiplexers. The MAP register can be read when MAP WE1L and MAP
WE2L

are

validity

not

illustrates

asserted.

the

MAP

registers

information

stored
operation.

4-24

are

read

them.

check

Figure

the

4-21

CS B <07:00> ;fi>

RAM ADRS <7:0> L Jl>

oT BOSY L—lso VX

SELECT

COUNTER

VAR BIT <16:09> H >

REC INT B <16:00> ID

SCv

VARCNTH —»CLK

VAR BIT <08:00>

DT REVH ——»{DN/UP

LD
A

TO DATA PATH
/0 BUFFER
VAR BIT <2:0> LOGIC

GRTST L

CLK VAR REG L

TK-0804

Figure

4-20

Virtual Address Register

R/W
MEMORY

j:>

GEN MAP PARITY H—1 DI

» MAP PARITY H

T
R/W
MEMORY

RAM ADRS<7:0>L

H
> MAP VALID

(FROM VIRTUAL

ADDRESS
REGISTER)

INT B31H —
REC

(VALID BIT)

MAP VALID L

R/W
MEMORY

—»{DI

REC INT B<20:00> H

MAP WE1L

MAP WE2L

Figure

4.3.3.3

Command/Address

4-21

MAP

Generation

the
MBA
1is
to
perform an
write
to
memory).
When

» MAP OUT <20:00>H

TK-0790

Registers

CMD

REQ

indicates

SBI data transfer operation
this
signal
1is
asserted,

that

(read or
OUT
MUX

SEL<@2:00>H
are asserted
(MIRP).
indicate that the D7 input of the

These multiplexer select 1lines
internal bus output multiplexers

will

OUT<K2@:0%3>H,

are

be
at

selected.
the

multiplexers
generated

the

extended

write

the

(i.e.,
read

1in

MBA

data

INT

B<31:0@¢>L.

memory

memory.

write
to

MAP

multiplexers.

transfer

command

Figure

the

command

write

extended

shown

READ
of

generate

command.
read

input

read,
If

The

4-22.

4-26

VAR

BIT<K@#8:00>H

the

bus

command/address

response

check),

memory.

and

The internal
to

the

data

MBA must

data

format

MBA
of

must

transfer

generate

transfer
the

output

not

generate

command

an
a

address

28 27

07 06

J \

COMMAND

PAGE NUMBER

QUADWORD

THE PAGE
WITHIN

BIT 31 ALWAYS 1 }nggxggg

BIT 30 ALWAYS O

01 00

BYTE WITHIN

FUNCTION

THE QUADWORD
—
(ALWAYS
0)
TK-0788

Figure

When

READ

indicating

INT B<29:28>L are
indicating a data
are

asserted

The

page

number

the

MBA

MAP

address

MBA

specified

data

transfer

(MIRF).

MBA

bits

MAP

quadword

generated

INT

generated

not asserted
(l1).
transfer write or

the

BIT<@#8:03>H

bit

Command/Address

Format

read

When DT READ
write check,

asserted,

MBA

H is not asserted
MBA INT B<29:28>L

(9).

B<P6:91>L

4-22

B@@#
the

within

B<27:07>L

OUT<K20:90>H
the

page

generated

from

(MIRK,L,M,N).

The

specified

MBA

INT

from the virtual address register bits VAR

Only

INT

quadwords

must

always

can

transferred;

zero

for

therefore,

command/address

MBA.

4.3.3.4
Byte Counter Register —-- The byte counter register (BCR),
shown in Figure 4-23,
is a 32-bit register consisting of eight
4-bit
synchronous
binary counters.
The
byte
count
register
maintains
a
record
of
the
number
of
bytes
of
data
to
be
transferred

The

byte

counters.

counter

and

from

counter
Bits

and

SBI

BYTE

bits

the

and

Massbus.

divided

CNT<K31:16>H

BYTE

the

are

CNT<K15:00>H

into

two

1l6-bit

byte

the

Massbus

byte

used

are

used

the

SBI

byte

counter.

The

SBI

byte

received

counter

from

maintains

the

SBI.
SBI

Massbus

device,

the

byte

data

loaded

When

the

1last

byte

record

When performing
byte

counter

the

silo

data

1is

transferred

output sets
is loaded.

4-27

the

data

from

the

(write

incremented

into

silo,
the
SBI
counter
carry
flip-flop and no further data

from

number

write

SBI

bytes

check)

each

input

the

SBI

BYTE

time

buffer.
to

the

CNTR=0

[

—— MB BYTE CNTR=0 L

CouT
CLKBYTE CNTR L

MB BYTE CNT L

::::::>BYTECNT<31fl6>r+

COUNTER

CLR CNTR L —O CLR
LD

LOAD BYTE
CNTR L

REC INT B <15:00> H :

CouT

» SBI BYTE CNTR=0 L

CLKBYTECNTR L
VAR BYTE CNT L

COUNTER |

> BYTE CNT <15:00> H

CLR CNTRL—O CLR
LD

LOAD BYTE CNTR L————j

CLRCNTR L

DTGOL

Figure

4-23

Byte

Counter

Oo§

TK-0787

d
1is written the SBI byte counter is ofloade
data
automatically into the Massbus byte counter. As each word
s byte counter is
is transferred to the Massbus device, the Massbu
ting that the
decremented twice until the counter equals 4, indica
the Massbus
to
d
last byte of data in the silo has been transferre
r
device. At this time the carry output from the Massbus counte
the
and
sets the Massbus counter = g flip-flop, RUN is negated,
Each

time

transfer will be completed when EBL is asserted.

e, the operation of the
when performing a read from Massbus devic
ins a
byte counter is reversed. The Massbus byte counter mainta
us
Massb
the
ved from
record of the number of bytes to be recei
r
counte
byte
device and 1loaded 1into the silo, and the SBIferred from the
trans
maintains a record of the number of bytes byte counter goes to
silo to the data output buffers. The Massbus
-ero as data 1is transferred into the silo. When the data is

When
transferred to the SBI, the SBI byte counter goes to =zero.
data
the
=zero,
is
FBL is received and the SBI byte counter register, CS B#9
L
transfer is complete. To read the byte counter

and CS B@2 H must be asserted and CS B<@l:99>H must be clear.
plexer
Output Data Multiplexers -- The output multiso
4.3.4
that
lel
in paral
consists of 32 8-way multiplexers connected
l
contro
or
s
one bit of each of the internal register output
.
4-24)
re
(Figu
signals is applied to each of the multiplexers
asserted on the
Selection of the register or control outputs to be store
selection
ol
internal bus is accomplished by ANDing contr
bits

C€S<99,02:080>H with

INT

RED

REQ

(internal

read),

EXT

st), depending on the
(external read), or CMD REQ (command reque
MUX SEL<@2:00>H. The
OUT
function to be performed, to produce
output combinations and corresponding data source selected are
provided

in Table 4-1.

the internal
Once data from the output multiplexers 1is selected, read
or data
nal
inter
the
bus drivers are enabled by ANDing SEND
erred
transf
is
Data
TR.
transfer command request input with
to the internal bus upon receipt of INT BUS O CLK.

4-29

AND CONTROL

OUTPUT

INFORMATON

MULTIPLEXERS

INTERNAL

INT B<31:00>L

BUS

INTERNAL BUS

DRIVERS

MUX SELO H

MUX SEL 1 H
MUX SEL 2 H

TRI EN<31:20>L

INT BOS O CLK 4—»

comB
LOGIC

TRI EN <19:16>L
TR1 EN <15:00> L

SEND
TR H

CMD REG L

RD REQ H
INT
EXT
RD REQ L

Figure

TK-0791

4-24

Output

Multiplexers

4-30

and

Select/Enable

Logic

CMD

EXT

REQ

L | REQ

Table

4-1

RD | INT

RD|

BA9

REQ

Internal

Bus

Output

Multiplexer

CS|Bits | MUX SEL | Data
L

Source

|86]|2]|]1]|

@ | Register

X|H|H}

H ] Command/Address

| X|X|H|H}|

H |

|[L|H|H]|L!

HI|L|IL|H|L]L]|Byte

|H|H|L|H|H]|Virtual

L |[ILI{H|{L|L]|]H]|Control

I[ILIL{L}JL}L]|JConfiguration

|[X|X]|]L|H|L]|Status*

bits

enabled,

Don't

H|L|L|H]

L || MAP

H]|

Diagnostic
Counter

Address

L ]| Status

care.

Only
wupper
16
control path.

4-31

lower

bits

from

Massbus

4.4

MBA DATA PATHS

The

MBA

data

paths

transfer

data

between

the

SBI

and

the

device.
The
data
paths
contain
transfers between the 32~data bit

the
SBI

silo
that
smooths
and the 16-data bit

Figure

the

data

4-25

block

4.4.1

Command

COMMAND

CONDITION

use the SBI to
during
a data

diagram

Condition
H

Massbus

out
the
Massbus.

paths.

(MDPA)

is asserted when the
from or write data to

MBA data paths want
to
memory. This will occur

read
transfer

to or
from
a mass storage device.
For a
read from device or a write (write check) to device, the following
conditions must exist:
a.

MBA

BUSY

asserted,

the

MBA

1is

processing

the

transfer;
b.

BLOCK

SEND

CMD

cleared,

command

memory;

CMD

cleared,

REQ

not

enabling

yet

processing

Other
conditions must
also
exist
for
read
(write
check)
to device.
These
conditions
following paragraphs.
Read

from

CMD

CONDITION

will

forward
2-3

the data

direction

transfer

from

send

command.

device

are

described

one

write
in

the

following

read

(DT READ H)

and

DOB7

full

read

(DT

and

DOBZ

data

REV H)

END

FWD,

forward

output

END

(SBI

the

in the

(BYTE

MASK

but

the

FWD

SBI

byte

(BYTE
read

filled

(DT

some

counter

the

reverse

MASKX

1-9

READ

the

now

H);

data
(SBI

the

data transfer
is a
read
(DT READ H)
1in
direction.
DT REV H
filled
some
number
of
buffers
but
the
SBI
byte
counter
is
now 0

CNTR

Massbus

exception

SILO

its

silo

transfer

READ

full

L);

REV,

BYTE

data

direction.
.DT

buffers

CNTR

the
reverse
data
output

the

is a

the

READY

any

FWD

(DT

BYTE

(DT

REV,

the

asserted

direction
DT

this

H);

FULL

exist:

FULL FWD,

MBA

Device

conditions

the

data

not

transfer

L).

parity error occurs
(MB EXC + MDPE H),
indicating that the MBA will empty

asserted,

all

data

prior

4-32

the

error.

32,

i
fi

MBA INTERNAL BUS

INT BUS

TRISTATE

RECEIVER|

BUS

MDPB,C

MDPE

A/\&

DIRECTION (McP)—]

|+,

[

FULL

—=

INPUT |
CONTROL
MDPE,P

DOB BYTE FULL

ge-v

MDPB,C

SILO

L0 INPUT

BUS DRIVER

S
B
SILO OUTPUT

IVER

ENABLE

RESISTER FULL

] e
WRITECHECK

’

BUFFER

SILO

MDPT

MDPH

§)

18x8

TRANSFER SILO OUTPUT

mOAD R

DOB1
MDPM
|

BYTE

DOB2

%EM%RY.

MDPM

’

DRIVERS

MuXx

BYTE MASKS (MSI)

MASSBUS

ouTPUT

MDPL

’6
%

MDPT

MASSBUS

CHECK

BUFFER

MASKS

»{

EQUALS

MDPT

MASSBUS

FUNCTION (MCP)_. CHECKER |- WCK ERR (MIR)

WRITE CHECK

I I

En%':EROL

MDPV,V

SILO INPUT RESISTER EMPTY LOAD SILO

OUTPUT

CLEAR

SILO INPUT BUS

|| ReQuEsT
MDPA

LOWS BITS

MDPR,S

COMMAND
REQUEST-—
(MIR)

VIRTUAL ADDRESS(MIR) —_

{ v4

SILO

xEAgg?yERs
—

DRIVERS

MDPF

%1 COMMAND

)

BUS

SILO DATA/IN BUFFER

SBI BYTE CNT=0 (MIR)—

{ 5

DIB2

DATA XFER

]

P DIB 0-7

TRI STATE

CLK DIB1(MS!)
CLK DIB2 (MSH)—

DATA TRANSFER

DIAGNOSTIC REGISTER READ(MIR)-—I

DRIVERS

>
fi

MDPU,P

DRIVE ENABLE

MDPU,V

,//:’,,—
32
A

OUTPUT

MUX

CONTROL

MUX-ENABLE (MSI) —s{ MDPS

INT BUS

MASSBUS

OUTPUT

MUX

DRIVER
CONTROL

MDPR,S

MDPK

CLEAR DOB PAIRS
TK-0806

Figure

4-25

MBA

Data

Paths

Write
CMD

(Write

Check)

CONDITION

Device

will

asserted

exist:
a.

READ

cleared,

the

data

the

following

transfer

not

device;

DIB2

FULL

READ

DATA

PEND

from

memory;

SBI

BYTE

cleared,

the

second

full;
C.

CNT=f)

cleared,

the

cleared,

data

MBA

the

input

MBA

conditions

read

buffer

not

waiting

has

from

for

data

not
;
data

transferred.

4.4.2

Internal Bus Receivers/Buffers
Data from the internal bus is loaded into four 8-bit latches
receipt of INT BUS ICLK from the control path clock circuits.

upon

The MBA input buffer consists of two sets of 32-bit latches. Their
function
is to control
the manner
in which
the
two
32-bit data
words from memory are loaded into the silo for subsequent transfer
to the Massbus. CLK DIB1 latches the first SBI data word into the
first data
input buffer
(DIBl). CLK DIB2 latches the second
word
into
the
second
data
input
buffer
{DIB2).
CLK
DIB2
H

increments

The
to

counter
zero,

buffers

4-bit

initialized

asserting

are

counter.

full,

WRITE

and

the
a

check.
Figure
4-26
1is
receivers and buffers.

four
READY

MBA
is
1logic

and counts
indicating

data
also

down
that

at CLK DIB2 H
all data path

ready
to
begin
diagram
of
the

a
write/write
internal
bus

4.4.3
Data Input Buffer Enable (MDPD)
The output of the data
input buffer select

is used to enable the
eight
data
input
buffers
(Table
4-2).
Virtual
address
register
bits VAR BIT<@2:00>H point to the data buffer where the data
is
stored.
The virtual
address
register
is
incremented by VAR BYTE

CNT

(MDPA).

When

the

function

write

(write

check)

and

the

fill
silo
operation
is
initiated
(LOAD SILO H),
the data
input
buffers are enabled sequentially onto the silo data input bus. The
data
input buffers
are disabled at T1 while VAR BITS <2:4> are
changing. Figure 4-27 is a diagram of the data input buffer enable

logic.

4-34

INTERNAL

DIB1-3

BUS

ENA L

RECEIVERS

BUS MBA

RECEIVERS

INPUT
BUFFER

INT

B <31:24> H

DIB1

ENA

pomm—

DIB2

[

BUS MBA
INT
B <15:08> H

ENA

St-p

DIB1

BUS
RECEIVERS
BUS MBA

INT

B <23:16> H

INTERNAL
BUS

RECEIVERS
BUS MBA

BUFFER

DIB2

ENA

BUFFER
DIB1

DIB1-2
L
ENA

INPUT

INPUT
BUFFER
DIB2

INPUT

ENA

INTERNAL

NA L

INT

B <07:00> H

ENA

DIB1-0
ENA L

INPUT

BUFFER

ENA

1B1—1

DIB2—1 ENA L‘?

DIB2-3 ENA |_j>
.

s —J

BUFFER
DIB1

INTERNAL

INPUT
BUFFER

INPUT

INPUT
BUFFER

DIB2
ENA

ENA

DIB2—0 ENA L9

DIB2—-2 ENA L—9

BUS SILO
D <07:00> H

TK-0796

Figure

4-26

Internal

Bus

Receivers/Buffers

Table

VAR
BIT

VAR
02

BIT

4-2

Data

Input

VAR
01

BIT

Buffer

Enable

DT
00

Input

READ

Buffer

Enabled

none

L
L

L
H

L
L

H
H

DIB
DIB

1-4
1-1

ENA
ENA

L
L

DIB

1-2

ENA

DIB

1-3

ENA

DIB

2-9

ENA

none

DIB

2-1

ENA

DIB

2-2

ENA

DIB

2-3

ENA

are

decoded

NOTE

VAR

BIT

<02:00>

they
have
been
latch by SET SBI

clocked
SEL H.

after

through

DATA INPUT|
DIB2-3
O—
ENA L
BUFFER

SELECT

VAR BIT 2

SEL A

VAR BIT 1

SEL B

VAR BITO

SELC

O— DIB2-2 ENA L
O— DIB2-1ENA L

O—

DIB2.0 £

OENA L

DIB1-3ENA L

O— DIB1-2
ENA L
O— DIB1-1
ENA L

DT READ H

TI
L

VARBITH02
—]

LATCH

VAR BITO01 H —
VARBITOOH

]

O— DIB1-0 ENA L

» SBI DATA SEL 00 H
—————
SBI DATASELO1H

—

+»

SBI

DATA SEL 02 H

CLK

SETSBISELFi___J
Figure

TK-0802

4-27

Data

Input

4-36

Buffer

Enable

Silo and Control Logic (MDPF, MDPH)
4.4.4
The MBA silo is 16-bytes deep by l-byte wide. Its function is to
provide a source of interim storage for SBI or Massbus data,
permitting regulation of the data transfer rate. Figure 4-28 is a
simplified diagram of the silo logic.

When

transferring

data

into

8-bit

LOAD

prior

input buffer

will

from

the

SBI

SILO

the

loads

data

Massbus

device,

the

and enable circuits divide the two 32-bit data words

bytes.

loaded
T@:

SBI

BYTE

CNTR = @

into

the

silo.

The

SBI byte

count

input

buffer

must

conditions

following

the

all

L cleared,

the

must indicate more bytes to be transferred;
DIB2

FULL

second

asserted,

data

exist

full;

(write

READ

cleared,

the

data

transfer

must

the

silo cannot be

full.

write

check);

SILO FULL L cleared,

STROBE MAP H
LOADSILOH ———I
DATA

ouT

ENABLE

BUS SILO D<07:00>H M DATA IN

CNTR |

CNTR

CUP CLR

SILO OUTPUT
D<07:00>H

DATA OUT

ADDRESS

CUP CLR

LOAD SILO L —J

DATA

MUX F1
FO

SEL

LOAD DOB L
READ/WRITE CYCLE

TK-0793

INIT + DT GO H

Figure 4-28

4-31

MBA Silo

As mentioned
previously,
the byte counter maintains
the number of bytes to be received
from the SBI and

byte

counter

transferred

The

silo

full

maintains

record

Massbus

device.

function

process

the

until

the

will

number

continue

bytes

into

the

silo.

silo

filled

and

data

remains

the
Massbus,
the
of the silo data

silo
loading
process
is transferred to the

occurs,

the

process

the

silo

transferring
read),

Massbus

data

the

set

and

The
following
function:
DT

MDIB
must

SILO

FULL

there

are

received,

and

the

READ

set

previously,

set

SCLK

were

set,

RUN

data

the

silo

that
been

continue.

Massbus device to
the SBI
(data
via
the Massbus
receivers,
into

transfer

must

asserted,

the

cleared,

parity

data

will

enable

will

ready

and

the

1load

must

the

Massbus

data

input

Massbus

silo

cannot

SCLK

buffer

silo

read;

buffers

data;

from

ready

the

full.

Massbus

flip-flop

ready and
data
input
buffer
receipt of data from the Massbus.

received and
occur.

aborted.

transfer

the

would

data

the

errors,

input

operation

exist

asserted,

ready

upon

overrun

the

READY

will

the

loaded,

conditions

data

until

data
input
buffers
(MDPE).
If
a
parity
error
is
Massbus input data,
the MBA PE bit in the status

detected

from

will

transferred from the
will
stop
until
a
Massbus. When this

SBI
to
portion

transfer

SBI byte counter goes to
zero
indicating
required to complete the data transfer have

the

When

record

the Massbus
bytes
to
be

the

all of
loaded

the

has

device

full

not

been

flip-flop

the ready flip-flop was already set, a
The DLT bit in the status register will

cleared,

and

the

transfer

operation

will

terminated.
Setting

the

silo

same

Unlike

input

described

the

write

transfer

begins

During

data

operation.

for

input

buffer

full

Actual

silo

Massbus

the

write

Massbus

device

flip-flops

operation,

initiates
operations are the
device

however,

operation.

the

data

loaded into the
data
word
has

silo
been

immediately.

READ,

each

time

byte

the
MBA
byte
counter
is
bumped.
transferred to the silo, the ready
are
reset and
the data
input
Massbus device data word.

and

buffer

4-38

data

After
is

is
the

data

input

ready

full
flip-flops
accept the next

Each

time

byte

data

transferred

from

the

silo

the

data

output buffer, the SBI byte counter is decremented. The process of
loading
the silo and
transferring bytes of data,
via
the
output
buffer, to the internal bus continues until the last byte has been
transferred

from

the

silo.

counters
will
equal
@
terminated upon receipt

this

time

both

the

and
the
data
transfer
of EBL from the Massbus

4.4.5
Data Output Buffer and Control Logic
The
data
output
buffer
consists
of
eight

(MDPJ,
8-bit

receive silo data
(SILO OUTPUT D<7:80>H). Virtual
bits VAR BIT<@2:00>H are decoded to produce LOAD
signals
(Figure

are used
4-29).

data

each

enable

one

output

buffer

corresponding
BYTE

flip-flops

MASK<2-3:2-@0>H,

the

eight

enabled,

LOAD

(MDPL)

and

that

byte

will

MDPM)
1latches

output

DOB<7:9>H

DOB

SBI

that

address register
DOB<7:@>H. These

data

generate

DOB<K7:0>FULL

and

operation
device.

latches

set

eight

BYTE

MASK<1-3:1-0>H,

SELC

DOB

SELB

and DOB SELA H are decoded to produce NEXT DOB FULL L each time a
byte of data
is loaded
into the output buffer
register.
If
the
next data output buffer already has valid data
(byte mask set),
the silo output logic will not load the next byte until the byte
mask

1is

cleared.

LOAD

DOB

from

the

byte

mask

selection

logic

also

the virtual address register each time a byte of
into the output buffer to select the next storage

from

which

4.4.6

The

data

Internal

internal

bus
and

the

When

from

read

buffer

Massbus

the

internal
H

must

bus

written

Output

output

device

internal

the

multiplexers.

DT READ

asserted.

CMD

ENAB

are

selected;

D<77:40>H

are

INT

BUS

WD2

selected.
OCLK

MUX

when

These

bump

data is loaded
location to or

MDPS)

consist

eight

drivers.

the

occurs,

internal

data

from

2-to-1

Figure

4-3¢

bus

drivers.

the

data

output

bus output multiplexers,

well

data

the

and

ENAB

WD2 MUX

WDl

MUX

the

data

word

REQ

Selection

(MDPR,

1line

with

D<37:0@0>H

multiplexers

Massbus

read.

Multiplexers

associated

determined

bus

corresponding

logic

applied

Bus

multiplexers

illustrates

used

this

signal

the

signal

1is

words

4-39

are

strobed

When

asserted
be

not

ENAB

asserted

asserted,

DOB

asserted,

DOB

onto

the

internal

LATCH

O—> DOBO FULL L

—1

EnB

LOAD DOB7 H

LOAD DOB6 H

- ENB
:

—» BYTE MASK 1-1H

—LATCH

O—> DOB1 FULL L
— BYTE MASK1-2H

DOB2 FULL L

—{LATCH

—» BYTE MASK 1-3 H

ENB
|

LOAD DOB5 H

DOB3 FULL L

SIL OUTPUT D<7:0>H
Efi;f”
L—
[
|
Loapposan

— BYTE MASK 2-0 H

O—> DOB4 FULL L
>

BYTE MASK 2-1 H

—1LATCH
ENB

0] 7 %

(O— DOB5 FULL L

LOAD DOB3 H

— BYTE MASK 2-2 H

I
—

(O—» DOB6 FULL L

Loappos2H |

—» BYTE MASK 2-3 H

[

LATCH
ENB

—ILATCH

O—» DOB7 FULL L
LOAD DOB1 H

DOB SEL C H —

BH —
DOBSEL

FJ ENB
:

—{LATCH

DOBSELA H —|

ENB

DECODE

VVVVVV
VWV

— BYTE MASK 1-0 H

DOB D<77:70>H

DOB D<67:60>H

DOB D<57:50>H

DOB D<47:40>H

DOB D<37:30>H

DOB D<27:20>H

DOB D<17:10>H

DOB D<07:00> H

LOAD DOBO H

LOAD DOBL ——]

TK-0792

Figure

4-29

Data

Output

Buffer

and

Control

Logic

DOB D<77‘6°>HJI>(MULT|PLEXER
2:1

DOB D<37:20>H

ENAB WD2 MUXH

MBA INT B<31:16>H

STB

)Cfi

INT BUS OCLK H

—

MBA
BUS MBA
fi" BUS

1 FEC MB EXC H ]

LUS MBA

DIAG INT

BUS EN H

DOB D<57:40>HJI>
2:1

DIAG INT BUS ENL—]

INT B17 H

BUS MBA

INT B16 H

MBA INT B<15:00>H

MULTIPLEXER

(o3]

)

ENAB WD2 MUX H

192]

=e |

DOB D<17:00>H

INT B19 H

REC WCLK H—

DIAG REG REQH

BUS MBA

RUN H

EN L

QUAD WD

}——OUAD WD EN L

ENABWD1 MUX H
INT BUS OCLK H

DT READ L —(O

CMD REQ L —O

Figure 4-30

Internal

Bus Output Multiplexers

TK-0800

4.4.7

Massbus Output
illustrates

Figure

Multiplexers and Parity Generator
the Massbus output multiplexers and

4-31

parity

generator.

For

write

loaded

into

Massbus

the

device,

Massbus

data

data
from
the
output
buffer
is
multiplexer.
The
Massbus
data

multiplexer consists of eight dual 4-to-1 line multiplexers that
divide the 32-bit words into two 8-bit bytes
(16 bits)
to comply
with the input requirements of the Massbus device. Byte selection
is determined by DOB BYTE CNTRL 1 and DOB BYTE CNTRL 2, developed
by the
data
output
select
logic
in
response
to
SCLK
from
the
Massbus device.
The output from the MBA multiplexer is checked to
ensure

odd
XMIT

that

number
MB

the

DPA

WRITE

byte

transmitted

bits.
to

the

they

ensure

odd

parity.

asserted

multiplexer

not,

and

Massbus

parity

the

RUN

flip-flop

transmitted,

via

the

device

contains

generator

Massbus

set,

data

drives,

Massbus.
4.4.8
Write

Write
check

Check

logic

4-32)

the

MBA

the h data

verifies

from

the following additional
multiplexers
1is
stored

Massbus

buffer

received

the

data

two

write

validity
(each
exists in data

the

integrity

Massbus

output

data

operation except for
the
Massbus
output
buffer memory.
Data
identical to
data
in
the

from

on the Massbus. DT WRITE CHK H
order
for
the
write
check
operation
to
be
operation is performed
identical
to a write

must
be
asserted
in
valid. A write check

check

Logic

(Figure

of
write
data
by
comparing
multiplexers with that of the

write

produces

out

the

processes. Data from
in
the
write
check
Massbus
is
stored
in the

This
Massbus

received data
should
be
output multiplexers. The

from

memory.

check

compared
bit
bits <15:98>,

the

memories
is
compared
to
test
its
must
be
equal).
If
an
inequality
WCK UPPER ERR H is asserted,
if an

inequality exists in data bits <@7:00>, WCK LWR ERR H is asserted.
The assertion of either one or both of these
signals causes the

data

transfer

aborted.

4-42

DOB D<77:70, 67:60>;>{\

DOB D<57:50, 47:40> +>}
DOB D<37:30, 27:20> v

—

DOB BYTE CNTRL2 H

PAR

——

GEN

XMIT MB DPA L

DOB BYTE CNTRL1H

4-31

TK-0801

Massbus

XMIT MB DPD<1 5:08>H>

Output Multiplexers

WRITE

CHECK
MEMORY

MASSBUS

REC MB DPD<15:08>H

WRITE

CHECK

MEMORY

-—J—_—“

Parity

Generator

D—oWCK UPPER ERR

MB SCLK H

WRITE OR

and

Figure

XMIT MB DPD
<15:00> H

0
S/

DOB D<17:10, 07:00> H

DOB
MUX

DT WRITE CHK H —

)

TE
)
CHECK
0>H> WRI
XMIT MB DPD <07.0
MEMORY

]

NOT MAINT H—

D——‘WCK LWR ERR

MASSBUS

REC MB DPD <07:00>H>

WRITE

CHECK
MEMORY

DIB SCLK
4

Figure

4-32

TK-0799

Write
4-43

Check

Logic

4.5
A

MBA CONTROL
control

path

PATH

data

transfer

initiated

when

the

command/address, decoded by the interface logic, specifies a read
or
write
external
register
operation.
Figure
4-33
is
a
block
diagram of the MBA control path logic. The control logic has the
following

”

major

functions:

derive timing signals from the SBI and Massbus clocks
decode and store function codes for data transfers
decode external register addresses
transfer data to and from external
initiate

set

Massbus

certain

status

synchronize

The

following

perform

these

control

SBI

and

paragraphs

path

error

Massbus

registers

cycles

conditions

the

MBA

operations.

describe

the

control

1logic

wused

functions.

(MCPA)

Bus Receivers

Internal

4.5.1
The

control

path

internal

bus

receivers

consist

two

8-bit

registers.
Internal
bus
data
(bits
BUS
MBA
INT
B<15:0¢>H)
1is
latched into the receivers, to be processed by the control
path
logic upon receipt of INT BUS ICLK L from the control path clock.
4.5.2

Data

Transfer

Control

The data
transfer
control
When
a
control
path
data

asserts

drive

(DS<@2:09>)

and

select
1lines
monitored when

drive.

performed,

(transfer

INT

pulse

start

write

MBA

also

the

and

latched

that
a

direction).

B<@7:090>H
are

(MCPB)

the

illustrated
is
to
take

three

address

Massbus

the

external

the

controller

Assertion

the

following

manner.

RS,

The

are

decoded

select

Massbus

1lines

WRITE

FCN

H from

the

into

the

control

store

the

transfer

output
enable

DS,

the

drive

and

is
REC

internal

bus

and

MBA

the

clocks

the

operation.

EXT

CMD

.
4-3)

4-44

to
the

interface

CTOD

bits

logic

function

lines

internal

direction

line

CTOD

(EXT CS BIT<4:8>L) are
a 3-to-8 line decoder.

select

indicate

function

only
(R#)

command/address

information
through these
registers to the
for assertion on the
Massbus.
The
register

B(@2:31>H

drive

five

asserts

intializes

data

control store
H (go bit)
to

in
Fiqgure 4-34.
place,
the
MBA

(RS<K@4:00>).
Data
transfer
commands
are
the selected register is the control register

the

accomplished
logic

address
a

Logic

logic
is
transfer

Massbus transceivers
select
1lines
of
the

ANDed with REC INT B@g
Bits REC INT B<@5:@3>H

performed.

indicated

Bits

function

REC

INT

(Table

INT BUS
RECEIVERS

MCPA
EXT

CONTROL

STORE

CLK EXT

DRIVE SEL

DT CMD

DT BUSY —»

(MIR) CLK CPO —|

DT BUSY — DT BUSY
MCPC

— SET DT COMPLETE

READ
. DT WRITE
DT

—)

MCPD

—» DT WCK
MCPB |—» DT FWD;REV

INT/EXT (MSI) —l

—#
DT

Sv-v

STORE |. pTCmD

CTOD
REGISTER SEL

CMD (MS1)

DATA FER OPERATION
TRANS

\
e

RSO0

MASS BUS
CONTROL
PATH CUT

CONTROL

ASSERT DEM

EXTERNAL

" | REGISTER

—

—®1 OPERATION
-

MCPB

MASS BUS

RECEIVERS

(CONTROL
PATH)

MCPC

MASSBUS

<|NTERNAL BUS >

MCPE,F,N

M&A BUSY (MSI) ———j
EXT HEAD
READY

MASS BUS
CONTROL
PATH IN

{TRI-STATE)

EXTERNAL READ READY (MS|) «—

MCPC

MCPJ

N
TK-0798

Figure 4-33

MBA Control

Paths

WRITE FCN H——
]

EXT CS WRITE (BECOMES CTOD)

LATCH

> EXT CS BIT<7:5>H (DRIVE SELECT)
> EXT CS BIT<4,3,1,0>H (REGISTER SELECT)

RECINTB<D%0¢>£;>
CLK CLR|

CLKEXTCMDH——————J
MASTER INIT L

r -—

—

Ifgg%NAHON
Lo

— —J

DT CMD H

(ROSELECT)

>
EN

TYPE

9-v

COMMANDL

DECODER

(COMMAND) REC INT B<5:3>H

> TYPE

DT BUSY L

CHKH

& DTREVH

PWRF INIT L

CLR DT BUSY L

PGM INIT
L

4-34

DT BUSY H

. DT WRITE

Figure

> DT WRITE H

COMMAND

N SEL

DT READ
H

Data

Transfer

Control

Logic

DT RWD H

'
TK-0805

Table

4-3

Function

and

Direction

Function

REC
g4

INT Bits
23
g2

Read

X
1

Select

g1
1

Reverse

Read

Forward
Write

/)]

X
1

Reverse

Write

Forward
Write

Check

)

)]

Reverse

Write

Check

Forward

‘

Don't

The

care.

decoded

flip-flop.

clocked

output

through

the

read.

EXT

function
is

BIT

the

corresponding

function

bus

1latches.

<@4:00>H

indicate

EXT

BIT

<87:05>H

is written or from which data

to which data

the

source

destination
'

the

select

already

selected

wvalid

function,

output

flip-flops

sets

the DT BUSY flip-flop.

MBA

asserted,

flip-flop

cannot

(9OF-00).

Regardless

this

stored

internal

(8-8)

select the drive
is

REC INT B<@7:00>H also produce EXT CS BIT <@7:09>H when

the

set,

MBA will

the

new transfer

not

the

processing

command

until

the

£from

the

DT BUSY

new command.

data

current

When

transfer

and

complete.

The

decoder

the

MBA

asserted,

CMD
not

also

received

indicating

asserted,

busy

triggers

output

has

with

XMIT

Massbus

device

indicates

that

DEM

the
is

data

write

ASSERT

data

one-shot

output,

produces

CMD

transfer
to

DEM

transfer

external

H will
(DT

sets

the

transfer

control

when

take

asserted

place..

4-47

which

DEM

indicates

BUSY

that

command.

CLK

function,

generated

cleared).

flip-flop

the

path

Massbus

data

that

CPO

the

ASSERT

and

MBA

DEM

(MCPC).

demand

Its

line,

from

the

write

control

data

external

(REC

B<15:00>)

INT

function is to
is
stored
in

be performed,
the
a
temporary latch

(MCPD)
to be transferred, via the control path data output logic,
to the Massbus device. Parity checking is performed to ensure that
this data
contains
an odd
number
of
bits
(odd
parity).
If
the
content of
the data word
represents an even number of bits,
the
parity

generation

asserted

Upon

the

receipt

control

DEM,

path data

should

control

noted

for

produces
XMIT
line
(Figure

CPA

the

into

the

that

CNTRL
4-35).

addressed

Massbus

selected

there

PAR

device

which

will

load

the

data

a 250 ns delay from the assertion
lines
to
the
assertion
of
DEM
to

skew

the

MBA,

data

compensate

1logic

Massbus

cables,

drivers,

receivers.
Once

the

:
control

the

and

path

Massbus

the

DONE

data

has

been

loaded

drive

will

issue

TRA

one-shot

1is

triggered

250
to

into

the

later.

indicate

write to external
assertion of DEM,
the
the

and

selected

DEM

that

is
the

register function has been completed.
If after
TRA is not returned to the MBA within 1.5 us,
NED (nonexistant device)
flip-flop is set, DEM is negated, and
write to external register function is terminated.

PARITY

GENERATION
b

oDD F—> XMIT CNTRL PAR

REC INT B<15:00>H

BUFFER

XMIT MB CPD<15:00>H >

CLK

CLK CPO H—
TIH—
TK-0794

Figure

4-35

1Internal

Massbus

Bus

Parity

4-48

Data

Generator

and

If the attention summary register is the destination of the write
operation, TRA will be ignored and NED will not be set. A 1.5 us
timeout will occur followed by the 2580 ns delay and DEM will be

negated. When the attention summary register is read, no timeout
will

occur.

When a read from external register function is executed, assertion

of the device and register select address and DEM on the Massbus

lines is accomplished in the same manner as described previously
for the write function; however, CTOD is not asserted. Upon
receipt of DEM, the device will load the contents of the selected

the MBA and
register on the C<15:88> 1lines for transmission to control
path
MBA
the
via
,
applied
is
data
assert TRA. This

es the data
receivers, to data latches. DESKEW DATA L (MCPC) latchtransmis
sion
in. Parity is checked to ensure that there were no
bit
error
parity
MCPE
the
ed,
detect
errors. If a parity error is
parity
no
If
4-36).
(Figure
set
be
will
r
in the status registe
errors are detected, the latches are clocked by DESKEW DATA L. The
output from the data latches is placed on the
receipt of SEND TR H from the interface logic.

REC CNTRL PAR H—

oDD

PARITY

H
EXT OP DONE

RS04 L

internal bus upon

Do—»sg MCPE L

EXT CSWRITE L

—

REC MB CPD<15:00>H

MASSBUS
CONTROL
PATH

REGISTERS

CLK CLR

DESKEW DATA L———-|
SET NED L

BUS MBA INT B<15:00>H

DATA

INT BUS OCLK H —j

T SEND TR H ——13]
RD-O
EXT
REQ L

TK-0795

Figure 4-36 Massbus Control Path Data Registers
and Parity Check (Received Massbus Data)

4-49

When

the

MBA

prevents

DEM

from

the

being

maintenance

mode,

asserted

the

has

been

check

MAINT

Massbus.

MODE

The

MBA

(MCPE)

performs

a write asserting data on the Massbus followed by a read of the
data just put on the Massbus. The MBA uses a timeout to complete
the read. The register select and drive select lines are also read
to

ensure

that

diagnostic

the

correct

data

read

operation.

4.5.3
Massbus Receivers/Drivers
Information is transferred to and from

control

path

summarized
are

always

Table

receivers

Chapter

enabled.

and

Control

Path

4-4

Signal

the

these

Massbus

The

via

signals

Massbus

Transmit

Enable

Massbus

Signal

the

are

path

Signals
Signal

BIT<K7:5>H

MASS

DS<2:0>

(always

enabled)

EXT

BIT<4:0>H

MASS

RD<4:9>

(always

enabled)

MASS

DEM

MAINT

XMIT

DEM

INIT

XMIT MB CPD<15:0@>H

MASS

INIT

MASS

C(15:00>

XMIT

EXT

CNTRL

RAR

WRITE

SIMULATE

OCC

FAIL

EXC

DEM

enabled)

EXT CS WRITE
MB

MAINT

MODE

MASS

CPA

(always

enabled)

MASS

CTOD

(always

enabled)

MASS

0OCC

SIMULATE
AND

XMIT

MODE
MB

(always

NAND

OCC

MAINT

H
MODE

MASS

EXC

(always

enabled)

MASS

FAIL

(always

enabled)

4-50

Massbus

summarized

Enabling

The

the

receivers

EXT

XMIT

information

control

enable

lines.

validity

Massbus

Transmit

4-4.
Table

the

drivers.

this manual.

put

End Data Transfer Logic (MCPA)
4.5.4
End data transfer
1logic
is
responsible

appropriate

signals

monitors various signals
produce the following:

the
in

end

the

data

control

generating

transfer.

path and

MBA

DT END L

Data

CLR DT BUSY L

Clear data transfer busy

BLOCK SEND CMD H

Block sending

SET DT ABORTED L

Set data transfer aborted

SET

DT COMPLETE

Figure

4-37

functions.

Set

transfer

for

data

the

illustrates

the

logic

interface

complete

the

command/address

transfer

logic

The

complete

used

accomplish

these

SBIBYTECTR=0L

Lfl:)__

MB EXC+MDPE H —

LAST MB DATA H ——

DTEND L

DT READ L ——

EOS H

SBI ABORT IMM H

CLR DT BUSY
L

T2
H

BLOCK SEND CMD H

:::)CF——SETDTABORTEDL
SET DT COMPLETE

INIT COND L
TK-0797

Figure

4-37

End

4-51

Data

Transfer

Logic

END

the

will

drive

has

asserted

only

EBL

after

one

the

MBA

the

has

dropped

following

RUN

and

conditions

occur.

The

data

transfer

SBI

byte

counter

and

memory

has

function
has

was

gone

acknowledged

read

zero

the

(DT

(SBI

second

READ

BYTE

data

H),

the

CNTR=g

H),

word

(WD2

ACK

H).
2.

The

data

READ

transfer

not

was

asserted)

write

and

the

SBI

byte

check function (DT
counter has gone to

zero.

The

END

data

transfer

error

(SET

SBI

There

has

been

is to be aborted
ABORT IMM H).

EXC

+ MDPE

synchronized

Massbus

exception

immediately

parity

due

error

(MB

H).
with

T@.

CLR DT BUSY L will be produced at
L will
be
asserted
as
a
result

If
the

DT END L has
following T2.

been asserted,
Block SEND CMD

of
an
abort
condition,
Massbus
exception, or a Massbus data parity error. SET DT ABORTED L will
be asserted at T2 of the SBI cycle
if DT END H
is asserted,
a
Massbus
exception
or
parity
error
occurs,
and
there
is
no
initialize condition
(INIT COND L not asserted).
SET DT ABORT L

will
MXF

also
L).

SET

initialize

asserted
DT

COMPLETE

condition

and

a missed
L

will

END

transfer

has

4-52

error

asserted

been

has
T2

occurred

asserted.

there

(SET
is

RH780 MASSBUS ADAPTER

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