Digital PDFs

EK-PDP44-MC-001

2000

60 pages

Original

3.4MB

view download

OCR Version

2.1MB

view download

Document:	PDP-11/44 Maintenance Card
Order Number:	EK-PDP44-MC
Revision:	001
Pages:	60
Original Filename:

OCR Text

PDP-11/44

Maintenance Card

CONTENTS
Console COMMAENGS. . ... ..vvrenr e 1
Module Utilization . ...... ...
....
.o
...
.. 6

Fowerup/Boot FIowW .. ... 7
Register Addresses ............ ... 8
Front Panel Operation..................... P 10

Processor Status Word Register. . .................... 11
CPU Error Register. ... .. e

et e 12

PIRQ Register............ e

PDP-11/44 MAINDEC Diagnostics. . .................. 14
CCIM(M7080) ..o e 15

CIS(M7091 and M7092) . ....ooooveinean
~ Control (M7095)............... e

e e 19

- MFM (M7096) ....... .40

S Cache (M7097) .o

;

et 24

UBIL(MT7098). ..ttt e 29
MST1-M (M8722) . ... .. e, 41

Memory Manégement ............................ .47
~ Power Supply (H7140) .....oovoeeeeseenn.. 53
NOTES. .. ..., it 55

EK-PDP44-MC-001

Copyright © 1981 by Digital Equipment Corporation
The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for

any errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computer-

ized typesetting system.

To obtain a copy of this document, use the number above and

order from Printing and Circulation Services, NR2/M15.

CONSOLE COMMANDS
CONSOLE MODE
Entered by:

CPU halting.

User typing the console break character (CTRL-P).

Exited by:

Continue command.

Start command.

Boot command.

PROGRAM 1/0 MODE
Entered by:

Continue command.

Start command.

Boot command.

Exited by:

CPU halting.

CTRL-P.

CONSOLE COMMAND SYNTAX EXPRESSIONS
<SP>

One space

<COUNT>

Numeric count in octal

Address argument in octal

<DATA>

Data argument in octal

Command modifier

>
<INPUT-PROMPT

Console prompt string (> >>)

<CR>

Carriage return

<LF>

Line feed

CONSOLE COMMANDS - continued
ADDRESS MODIFIERS

Increment last address used by two

Decrement last address used by two

Address last used

Last data used becomes address

Hardware switch register

CONTROL CHARACTERS

CTRL-C

Cancels command processing before a terminal
session.

CTRL-O

Alternately suppresses and continues display of
data at the terminal.

CTRL-P

CTRL-Q

initiates console mode.

Restarts terminal output that was suspended by
CTRL-S.

CTRL-S

Suspends terminal output until CTRL-Q is pressed.

CTRL-U

Cancels current line and discards it.

QUALIFIERS
/G

Specifies general register space.

Permits multiple examines or deposits for one command.

Specifies a machine-dependent register. The address of
each machine-dependent register is:

CONSOLE CON

VIANDS - continued

Address

0 (Read only)

Floating-point data

1 (Read only)

CIS Micro PC (CPC)

2 (Read only)

CIS data

3 (Read only)

CPU data

4 (Read/Write)

CPU Micro PC (MPC)

5 (Read only)

Cache data

6 (Read only)

CPU error register

7 (Read only)

MFM data

10 (Read only)

UNIBUS data

11 (Read only)

Signal register

/TB

Take bus, maintenance feature if bus is hung.

/CB

Cache bypass, do not read cache.

Specifies test-extensive, used with (T) command.

Specifies test-extensive-apt, used with (T) command.

CONSOLE COMMANDS
Adder

A<CR>

Boot

B[<SP><DEVICE-IDENTIFIER>]<CR>

Continue

C<CR>

Deposit

D[ <QUALIFIER-LIST>]

<SP><ADDRESS><SP>
<DATA><CR>
Examine

E[[<QUALIFIER-LIST>]
<SP><ADDRESS>|<CR>

Fill

FI<SP><COUNT>]|<CR>

CONSOLE COMMANDS - continued

Hait

H<CR>

Initialize

I<CR>

Microstep M[<SP><COUNT>]<CR>
Repeat

R<SP>(COMMAND)<CR>

Single-

N[<SP><COUNT>|<CR>

Instruction

Step

S;tart

S[<SP><DATA>]<CR>

Self-Test

T[<QUALIFIER>]<CR>

CONSOLE ERRORS

201 SYN

711 IPR ERR

illegal command.

lllegal internal processor register. Applies
to the use of the /M qualifier.

215 HLT CPU

?20 TRAN ERR

Command illegal while CPU is running.

Console tried to examine or deposit but
failed due to memory timeout or parity error.

220 MPC=15

An examine was attempted while the CPU
was halted and at micro PC 015.

721 HLT ERR

Console tried to halt the processor, but
failed.

2722 HUNG

Console initiated a CPU transfer, but it was
never started.

CONSOLE COMMANDS - continued
?30

Checksum error was found while executing
a binary load/unload command.

781

Checksum error was found in PROM 1 of
console control store (while running selftest).

782

Checksum error was found in PROM 2 of
console control store (while running selftest).

785

Error in read/write test for console RAM.

Halt/continue test of T/E failed.

PAX data bus test of T/E failed.

7A9

PAX address test of T/E failed.

?AA

Switch register test of T/E failed.

MODULE UTILIZATION
PROCESSOR BACK PLANE

KD11-Z

CiM a

M7090

cis

CIs

M7093

DATA PATHS

M7094

CONTROL

M7095

MFM

M7096

M7097

CACHE

uBl

M7098

MS11-M

M8722

MS11—M

M8722

MS11-M

M8722

MS11—M

M8722

SPC* ®

14 {M9302 OR UNIBUSCABLE|

M7091
M7092

SPC* m

* MUST CONTAIN MODULE OR BG CARD

® REMOVE JUMPER CA1—-CB1 TO USE NPR DEVICE
DO NOT PLACE A MULTI-LAYER EXTENDER
& CAUTION:
BOARD IN ROWS A& B OF SLOT #1
TKA184

Module Utilization

POWERUP/BOOT FLOW
FRONT

PANEL

NORMAL

BOOT

MFM CONSOLE

MFM

POWE RUP

SWITCH

BOOT COMMAND

COMMAND

CPU CONTROL

“B DEV NAME"TM

CPU CONTROL

S1 OPEN

$2 CLOSED

024

{024)

773024

UBIE28 ~ 2

USER

]

SOFTWARE
—

S
P
AUXILLIARY

ON UNIBUS

CLOSED

uBl E28— 1
CLOSED

usw =020
BOOT DIAGN.
ROM TESTS

BOOTSYSTEM

UBI E28 -1
OPEN

165000 OR ‘D

PC 173000 OR ‘D

UB! USWITCH

Usw

OPEN

UBI E28 - 2

UBI SWITCH

144

glsva-N BOOT W/

Usw = 020

=020

USW
= BOOT WO/

DIAGN.

BOOTSTRAP ROM—~JUMPS
TO BOOT DIAGN. ROM

BOOT DIAGN. ROM
ISSUES CPU HALT

MFM CONSOLE T
SELF TEST
EXECUTED

MFM CONSOLE

BOOT DIAGN. ROM TESTS

BOOTSTRAP ROM
PRIMARY BOOT

SECONDARY BOOT

MODE

TK6141

Powerup/Boot Flow

PDP-11/44 CPU AND I/0 DEVICE REGISTER
ADDRESSES

Address

17 777 776

Processor status word (PSW)

17 777 772

Program interrupt request (PIRQ)

17 777 766

CPU error

17 777 707 -

CPU general registers

17 777 700

17 777 676 -

User data PAR, registers O-7

17 777 660
17 777 656 -

User instruction PAR, registers 0-7

17 777 640
17 777 636 -

User data PDR, registers O-7

17 777 620

17 777 616 -

User instruction PDR, registers 0-7

17 777 600

17 777 576

MM status register 2 (SR2)

17 777 574

MM status register 1 (SR1)

17 777 572

MM status register O (SRO)

17 777 566 -

Console terminal SLU

17 777 560

17 7XX XX6 17 7XX XXO

TU58 DECtape SLUs (normally 17 776 500)

Address

17 777 570

Switch register

17 772 516

MM status register 3 (SR3)

17 772 376 -

Kernel data PAR, registers O-7

17 772 360

17 772 356 -

Kernel instruction PAR, registers 0-7

17 772 340

17 772 336 -

Kernel data PDR, registers 0-7

17 772 320
17 772 316 -

Kernel instruction PDR, registers O-7

17 772 300
17 772 276 -

Supervisor data PAR, registers 0-7

17 772 260

17 772 256 -

Supervisor instruction PAR, registers 0-7

17 772 240
17 772 236 -

Supervisor data PDR, registers 0-7

17 772 220
17 772 216 -

Supervisor instruction PDR, registers 0-7

17 772 200

17 770 372 17 770 200

Map registers

FRONT PANEL OPERATION
KEYSWITCH POSITIONS

Logic and fan power off. AC and DC power

DC Off

still present in power supply.

Normal ON position. Logic and fans have

Local

power. Console can be used in either program I/0 or console mode.
Local Disable

Locks out console mode. Program 1/0 is still
available. Locks out RD interface if W21 is
installed on the M7090.

Shuts off main +5 V, +15 V, and -156 V

Standby

power. Memory voltage and fans remain on.
THREE-POSITION TOGGLE SWITCH
Boot

Momentary position.

Continue

Normal operating position.

Halt

Halts CPU.

LIGHT-EMITTING DIODES (LEDs)
Run Light

ON: CPU executing instructions.
OFF: CPU halted.

DC On Light

ON: DC power within tolerance.

Blinking: DC power out of tolerance.
Battery Light

ON: >90% charged.
Siow Blinking: < 90% charged and charging.
Fast Blinking: Discharging.

OFF: Fully discharged or not present.
Remote Light

ON: CPU under RD control.

QOFF:. CPU not under RD control.
10

PROCESSOR STATUS WORD REGISTER
PROCESSOR STATUS WORD
15

11 10 09

|7 777 776

08 07 06

05 04 03

02 01 00

CURRENT MODE
PREVIOUS MODE

CIS INSTRUCTION SUSPENSION
PRIORITY
TRACE TRAP

CONDITION CODE

te]

@ BIT <08> 1S SET WHEN A CIS INSTR. IS ENTERED AND CLEARED

WHEN THE INSTRUCTION IS COMPLETED. IF SET WHEN AN
INTERRUPT OCCURS, IT INDICATES THAT THE CIS INSTRUCTION

WAS NOT COMPLETED AND MUST BE CONTINUED UPON RETURN
FROM THE INTERRUPT. WHEN SET IT PREVENTS THE SETTING
OF THE T-BIT.

Processor Status Word 17 777 776

CPU ERROR REGISTER
CPU ERROR REGISTER
15

14 13 12

|7 777 766

1110 09

08 07 06

0504 03

02 01 00

ITI*HH*I ennianging

DATA TRANSFER(O)DATO(B)

CACHE RESTART
KT ERROR

BUS ERROR
PARITY ERROR
AC LO

DC LO

ILLEGAL HALT

ODD ADDRESS ERROR
MEMORY TIMEOUT

UNIBUS TIMEOUT
PROCESSOR INIT

STACK OVERFLOW
INTERRUPT
CIM POWER FAIL

*% = SOFT-WARE TRANSPARENT; PROVIDED AS A
MAINTENANCE AID FOR THE DIAGNOSIS AND
REPAIR OF THE KD11-2
TK-4477

CPU Error Register 17 777 776

PIRQ REGISTER
PROGRAM INTERRUPT REQUEST REGISTER
ADDRESS—I7 777 772
15

7 &

PROGRAM INTERRUPT

08 07

)

VECTOR =240

050403

|IO S N
PIA

—
PIA

REQUEST LEVEL

PROGRAM INTERRUPT ACTIVE
TK-4479

Program Interrupt Request Register

PDP-11/44 MAINDEC DIAGNOSTICS
PDP-11/44 MAINDEC DIAGNOSTICS
NOTE

items should be executed in the order they are

ONooRLON
=

listed.

KKFA??

11/44 Diagnostic ROM*

KKAA??

11/44 CPU/EIS

KKAB??

11/44 Traps

KKTA??

11/44 Memory Management, Part A

KKTB??

11/44 Memory Management, Part B

ZM9B??

M9312/11/44 UBI Boot

KKUA??

11/44 UBI MAP

KKKA??

11/44 KK11-B Cache

ZMSD??

MS11/M/L Memory

ZDLD??

DL11-W/11/44 MFM SLU

KKAC??

11/44 Power Fail

KFPA??

FP11-F, Part A

KFPB??

FP11-F, Part B

KFPC??

FP11-F, Part C

ZKEE??

PDP-11 CIS Instruction Exerciser

ZKUA??

UNIBUS Systems Exerciser

ZKUB??

UNIBUS Exerciser Module

* Diagnostic ROM is on the M7098 module.

LED

EIA DATA

CONSOLE

TERM

TU58

W20 OmeemD OmeeO W16

TRANSMISSION

w190

Owis
FRONT

PANEL

O=—=OW14

w130

OWwWs

ows

ow?

OwW6

OWws

ow4d

W12 OemeeeO
o

owai

W11 Ome
W10 OO

W18 OO

w30

W20

wio

W70

CiM

M7080
TK5978

CIM Jumper Lead Locations, Connectors, and LED Indicator
CIM CONFIGURATION
20 mA Configuration

Mode

Jumper Leads

Transmitter

Active

OUT IN

Passive

EIA Device

OUT OUT OUT OUT OoUuT

W5E

W13

OUT IN

OUT OUT IN

ouT

090) - continued
Modse

Jumper Leads

Receiver

Active
Passive
EIA Device

ouT
IN
QUT IN
OUT IN
IN
ouT
OUT IN
OuUT IN
OuUT IN
OUT OUT OUT OUT OUT OUT IN

W17 Wis

Jumper W11 should always be installed. Jumpers W12, W15,
W16, W19, and W20 may remain installed for 20 mA operation.

ElA Configuration
Mode

Jumper Leads

WwWi2

W15

W16

RS-232-C

OuUT

ouT

RS-423

OuUT

OUT

ouT

RS-422

OUT

ouT

Mods

Jumper Leads

w20

wi-9
Wi3

wig

WwWig

RS-232-C

OuUT

ouT

RS-423

OuUT

ouT

RS-422

ouT

cCiM

(M7090) - continued

TUS8 Configuration

Jumper Lead

Mode

W14

RS-232-C

RS-423

ouT

Connector J4 should have a test connector (74-22428-00)
when there is no TUS8 for diagnostics. In order to run operating
software, this turn-around plug must be removed.
Remote Diagnosis Configuration
w21

IN:

RD disabled if in local disable.

QUT:

RD enabled if in either local disable or local enable.

Voltage Monitoring
W10

IN:

Enables +12 V monitoring.

OouUT:

Disables +12 V monitoring.

LED Indicator

The LED is lit when EIA data transmission to the console terminal occurs in both directions. The 20 mA operation has no effect
on this LED.

CIM

The CIM (M7090) can not be extended on multi-layer exten-

ders. A multi-layer extender can not be inserted into slot 1, rows
A and B.

M7092
c1s

[

NOTE:

S11S FOR MANUFACTURING USE ONLY.
S1 SHOULD BE IN THE "OFF"” POSITION
OR TOWARDS CENTER OF MODULE.

M7092 CIS

KE44-A (CIS)
CIS instructions are clocked in.

The CPU addresses MPC 000 in order to process an illegal
instruction trap. However, the KE44-A asserts the signal
CIS ENAB L. This forces an MPC value of 740 onto the
KD11-Z MPC lines.

NOTE

KD11-Z

microcode addresses

740-776 are

utilized for CIS instructions.

During execution of the CIS instruction, the CIS processor

controls the next MPC generation for the KD11-Z.

Upon completion of the CIS instruction, the KE44-A stops
controlling the KD 11-Z's next MPC lines. It also drops the
signal CIS ENAB L.

The KD11-Z attempts to address MPC 000 in order to
process the illegal instruction trap. When CIS ENAB L is

dropped, it makes the signals serve IR L and serve IR H on
K2-2. This forces a no OP (BR2) to be clocked into the IR
which removes the trap condition. Instead of processing
an illegal instruction trap, the KD11-Z fetches a new instruction.

CONTROL (M7095)
A

JIN

JIx

L
OPEN = NO BOOT ON POWER UP
CLOSED = BOOT ON POWER UP

M7095
CNTRL

1. f
.
n
L
TK-5983

M7095 CPU Control

5P
- W9
W5
OOOOI

D__ SELF-TEST
LED

W10-W14
iOOOO

INDICATOR

0000

WBi

S1—wS7

S} ——e 510

sz W’I

St—=359

St —e=5S8

MFM

M7096

[
TK-5879

MFM Jumper Lead Locations, Switches, and LED Indicator
MFM CONSOLE TERMINAL BAUD RATE SELECTION
Swiitch Pack E6

Receiver Switch
2

OFF

110

OFF

134.5

OFF

Locations

Transmitter Switch
Locations

Baud Rate

150

OFF

200

OFF

300

OFF

600

OFF

1200

OFF

1800

OFF

2000

OFF

MFM (M7096) - continued
Switch Pack E6
Receiver Switch
Locations

Transmitter Switch
Locations

Baud Rate

2400

OFF

3600

OFF

4800

OFF

9600

OFF

19200

OFF

MFM CONSOLE TERMINAL JUMPERS
IN: Enable address decode.

QUT: Disable address decode.

IN: Enable receiver error bits {15:12).

OUT: Disable receiver error bits (15:12).
IN: Enable terminal break.

OUT: Disable terminal break.
IN: Enable parity.

QUT: Disable parity.
W7 & W8

Character length for console UART.

6 Bits

7 Bits

8 Bits

Jumper

5 Bits

ouT

M (M7096) - continued

IN: Odd parity.

OUT: Even parity.

S1 (E6)

ON: 1 stop bit.
OFF: 2 stop bits.

OFF: 1.5 stop bits if W7 and W8 are in.
TERMINAL RECEIVER STATUS REGISTER

ADDRESS-I7777560
2

08 07

ol lmllr]

TERMINAL RCVR DONE

TERMINAL REC INT ENAB

TERMINAL RECEIVER BUFFER REGISTER
ADDRESS-— 7777562
14

EHIH lfl

READ ONLY

TERM OR ERROH

TERM R DATA<07:00>

TERM FR ERROR
TERM P ERROR

TERMINAL. TRANSMITTER STATUS REGISTER
ADDRESS—I7777564
15

| Pal e sl
TERM READY

CiM REMOTE
ENABLE CONSOLE

TERM MAINT

TERM BREAK
TK-4505

MFM Registers

MFM (M7096) - continued
TERMINAL TRANSMITTER BUFFER REGISTER
ADDRESS—I7 777 566

XMIT DATA BITS<07:00>
WRITE ONLY

TUS8 RECEIVER STATUS REGISTER
ADDRESS [7 7XX XXO
11

08 07 06

o o2
|

TUG8 RCVR INT ENAB

TU58 RECEIVER BUFFER REGISTER
ADDRESS—I7 7XX XX2
05

08 07 06

1413 12

HR[ o 1L 1L

TU58 OR ERROR

—

READ ONLY

—

TU58 RCV DATA<07:00>

TUS8 ERROR

TU58 FR ERROR

TUS8 P ERROR

TK-4478

TUS8 TRANSMITTER STATUS REGISTER
ADDRESS—I7 7XX XX4

o ] oJlH]JImicne
15

TUS8 XMIT INT ENAB
TUS8 MAINT
TUB8 BREAK

TUS8 TRANSMITTER BUFFER REGISTER

ADDRESS—I7 7XX XX6

o o

)

XMIT DATA BITS<O7 00>
WRITE ONLY

LINE CLOCK STATUS REGISTER
ADDRESS -7 777 546
08

00 JH L/vgl[
LTC INT MON
LTC INT ENAB

MFM Registers
23

KK11-B

4K words (8K bytes).

Single set, direct mapped caches with write through features.

Can be removed without affecting overall KD11-Z operation.

Switch S1:

ON: Force miss upper 2K words of cache.

OFF: Enable upper 2K words of cache.
e

Switch S2:

ON: Force miss lower 2K words of cache.

OFF: Enable lower 2K words of cache.
e

Jumpers W1 and W2:

W1:IN., W2:0UT - Single port memory and force miss
only {cache not affected).

W1:0UT, W2:IN - Multiport memory and force miss only
(cache invalidated).
NOTE

This is for CPU read hit with bypass.

CACHE (M7097) - continued
CACHE RESPONSES TO HIT/MISS OPERATIONS

Read

DMA

CPU

Hit

Miss

Hit

Miss

Not

Cache

Write Data

Affected

Read

Write Tag

Write Valid

Read

invalid

Bypass

Write

Bypass

Invalid

Not

Invalid *

Not

Affected

or Not Affected

Affected

Not

Write

Not

Affected

Data

Affected

Not

Invalid

Affected

* Depends on jumpers W1 and W2.

Not

Affected

17097) - continued

5
D2 D1 D3

51|

Nee=OFF
%

coo

|s2

o—0

w20

i LOW

PARITY
HIT

ADDRESS MATCH

KK11-B

M7087

T
st

TK-5980

Cache Memory Module, Switches, LED Indicators, and Jumper
Lead Locations
CACHE MEMORY ERROR REGISTER 17 777 744

07 06
15 14 13 12 11 10 09 08

‘

CACHE MEMORY
PARITY ERROR
PARITY ERROR HIBYTE
PARITY ERROR LOBYTE
TAG PARITY ERROR
TK-A574

Cache Memory Error Register 17 777 744
CACHE CONTROL REGISTER
14

7 777 746
08

05 04

§fln \\\\\\ Iw IR/W‘R/wl W [R/SE@R,WI

VALID STORE IN USE
VALID CLEAR IN PROGRESS
WRITE WRONG PARITY TAG

UNCONDITIONAL CACHE BYPASS
FLUSH CACHE
PARITY ERROR ABORT

WRITE WRONG PARITY DATA
FORCE MISS Hi

FORCE MISS LO

DISABLE CACHE PARITY INT.
TK4575

Cache Control Register 17 777 746

7097) - continued

‘CAQHEE

CACHE MAINTENANCE REGISTER
1514

7 777 750
07

_[7]1 nojnnnjns: [exrizzs

COMPARE 2

COMPARE 3 s
VALID

HI PARITY BIT

LO PARITY BIT
TAG PARITY BIT
HIT

ENABLE STOP ACTION
ADDRESS MATCHED
ENABLE HALT ACTION

HIT ON DEST ONLY
TAG DATA FROM AMR
NOTE:

THE CACHE MAINTENANCE REGISTER CAN ALSO BE REFERENCED AS THE
ADDRESS MATCH REGISTER. WHEN WRITING TO BITS <15:10> OF THE
CACHE MAINTENANCE REGISTER IT CONTAINS BITS <21:16> OF THE ADDRESS
MATCH REGISTER.
TK-4577

Cache Maintenance Register 17 777 750

17 777 750

ADDRESS MATCH REGISTER

L
I-

BITS <21:16> OF ADDRESS
MATCH REGISTER WHEN WRITTEN
TK-4578

Address Match Register 17 777 750
CACHE HlT REGISTER

17T 777 752

e [ o | == e

08 07

TAG ADDRESS

CONTAINS TAG FIELD
OF LAST VALID ACCESS

HIT REG.

ToRIT 0-MISS

INDICATES NUMBER OF
HITS ON LAST SIX CPU

ACCESSES TO NON-1/0
PAGE MEMORY (READ ONLY)

NOTE:

THE CACHE HIT REGISTER CAN ALSO BE REFERENCED
AS THE ADDRESS MATCH REGISTER. WHEN WRITING

TO BITS <15:00> OF THE CACHE HIT REGISTER

IT CONTAINS BITS <15:00> OF THE ADDRESS MATCH REGISTER.
TK-4579

Cache Hit Register 17 777 752

CACHE (M7097) - continued
ADDRESS MATCH REGISTER
15

17 777 752
f(_}_g 07

BITS <15:00> OF ADDRESS MATCH
REGISTER WHEN WRITTEN (WRITE
ONLY)

Address Match Register 17 777 752

CACHE DATA REGISTER
15

12
13

17 777 754

08 07

OO O
~

03
05 04

LOADED WITH CACHE DATA BITS
<15:00> ON EACH CPU READ 7O
NON-1/0 PAGE MEMORY.
{READ ONLY}

Cache Data Register 17 777 754

CO
02 01

]

%’F———J}———‘('P‘-——S?—?

Oy W17

1.7
TK-3836

UB! Module, Switch and Jumper Lead Locations

UBI DIAGNOSTIC AND BOOTSTRAP ROMS
Switch Pack E28
Switch S1:

ON: 765 XXX device bootstrap program.

OFF: 775 XXX CPU diagnostic program.
Switch S2:

ON: Bootstrap/diagnostic enabled.

OFF: Bootstrap/diagnostic disabled.

Switches S3-510 are bits (08:01) of the starting address
(ON = 1, OFF = 0).
Device ROM identification:

To identify the device bootstrap ROMS that are installed,
initiate the diagnostic program MAINDEC CZMSB?? or

examine the following five addresses and compare the response with the bootstrap ROM identifiers listed.

775774

(CPU diagnostic ROM)

773000

(Device ROM #1)

773200

(Device ROM #2)

.—

oTM

iT {q,O f

[(fgy, ¢

M7098) - continued

773400

(Device ROM #3) +— )

773600

(Device ROM #4)

=O4

A 177 776 response indicates the continuation of a ROM
diagnostic program to an additional ROM.

A XXX 777 response indicates a ROM failure or no ROM
present at the addressed location.

The position of the bootstrap ROM on the module must be

sequential, starting with device #1 through device #4.
IC Location

Bootstrap ROM

EA48

Device #1

E49

Device #2

ES0

Device #3

E b1

Device #4

W1:IN

ouT

W2:IN

ouT
e

W17.W18

—~ Enable parity error abort.

— Disable parity error abort.

- Enable diagnostic ROM.

— Disable diagnostic ROM.
- Always installed.

BOOTSTRAP ROM IDENTIFIERS
Octal 1D Number

Device ROM

041524

TA11

042104

TUB8

042113

RKO3/05/05J

042113

TUbB5/66

042114

RLO1

042115

RK06/07

042120

RP02/03

042120

RP04/05/06
30

uBl (M7098) - continued
Octal ID Number

Device ROM

042120

RMO02/03

042123

RS03/04

042130

RXO01

042131

RX02

046515

TU16/45/77/TE16

046523

TS04

046524

TU10, TE10, TSO3

050122

PCO5

050122

ASR 33

054115
DL11

177776

054115
DMC-11

177776
177776

054125
DU11

177776
177776

054127
DUP-11

177776
177776

PDP-11/44 UBI! DIAGNOSTIC ROM
e

Tests 1-14 loop ON error.

Tests 15-16 halt ON error.

Loop/Halt

Test

Address

Numbers

Description

165070

Unconditional branch

165106

CIR, Mode 0O, BMI, BVS, BHI, BLT,
BLOS

UBl (M7098) - continued
Loop/Halt

Test

Address

Numbers

Description

165122

DEC. Mode O,

BBPL,

BEQ, BGE,

165172
165202

165220

DN
b

165134

ROR. Mode O, BUC, BHIS, BNE

BLE

ADD, INC, COM, BCS, BLE

ROL. BCC, BLK

165240

BOR, DEC, BIS, ASS, BLO

165246

COM, BLOS

165260

BIC, BGT, BLE

165302

SWAB, CMP, BIT, BNE, BGT

165312

MOVB, BPL

1656334

SOB. CIR, TST, BNE

165346

JSR

1656356

Push onto stack failed

165366

RTS

165400

RTi

165406

JMP

Main memory data error without

165526

cache
165550

Main

memory data

error without

cache

165634

No hit in cache

165652

No hit in cache

165664

15 or

165702

Any Test

Parity error

Hardware trap to 4 (check stack)

| DEVICE ROM PART NUMBERS
Device

ROM Part Number

ASR 33

23-760A9

DL11

23-926A9
23-927A9

23-928A9
DMC-11

23-862A9
23-863A9
23-864A9
32

UBI (M 7098) - continued

Device

ROM Part Number

23-868A9
23-869A9

23-870A8
DUP-11

23-865A9
23-866A9

23-867A9
PCO5

23-760A9

RKO03/05

23-756A9

RKO06/07

23-752A9

RLO1

23-751A9

RP02/03

23-755A9

RP0O4/05/06

23-75BA%

RS03/04

23-759A9

RXO1

23-753A9

RX02

23-811A8

TS04

23-764A9

TU10, TE10, TSO3

23-758A9

TU16. 45, 77, TE16

23-757A9

TUbS, 56

23-756A9

TUS8

23-765A9

TUBO

23-761A9
33

UBIl (M7098) —~ continued

DEVICE BOOTSTRAP IDENTIFIERS
TA11

RP04/05/06, RM02/03

TUS8

RK03/05/05J

RLO1

RKO6/07

RP02/03

RS03/04

TUbb/56

RXO1

RX02

TU16/TE16 (TM02/03)

TUTO/TET10/TSO3

PCOb

ASR 33

DMC-11

DUP-11

DU1T1

DL11

UNIBUS MAP REGISTERS
Register

UNIBUS

Mapping

Address

Address Page

770200,

- 017777
000000

770204,

- 037777
020000

770210,

- 067777
040000

770214,

- 077777
060000

770220,

- 117777
100000

770224,

120000 - 137777

770230,

- 157777
140000

770234,

160000
- 177777

770240,

200000
- 217777

UBI (M7098) - continued
Register

UNIBUS

Mapping

Address

Address Page

770244,

220000
- 237777

770250,

240000
- 257777

770254,

260000
- 277777

770260,

300000
- 317777

770264,

320000- 337777

770270,

340000
- 357777

770274,

360000 -377777

770300,

400000
- 417777

770304,

420000
- 437777

770310,

440000
- 457777

770314,

460000 -477777

770320,

500000 -517777

770324,

- 537777
520000

770330,

540000
- 557777

770334,

560000 -577777

770340,

600000
- 617777

770344,

- 637777
620000

770350,

640000
- 657777

770354,

660000-677777

770360,

700000 -717777

770364,

720000-737777

770370,

- 757777
740000

* 37

770374,

* Register 37 is not used for relocation as the corresponding
mapping address is the /0 page.

UNIBUS ADDRESS SPACE JUMPERS, UPPER LIMIT
Defines the last address which will not pass to main memory.
UNIBUS ADDRESS SPACE JUMPERS, LOWER LIMIT
Defines the first address which will not pass to main memory.

1Nno NI

1no

¢l 91

A
NI

1no NI

1no
1No
1no
1No

NI
NI NI NI

Ol L
NI

1No 1Nno 1noNo1No 1no
1Nno

NI
NI

1NO

iiale

1no
1no

NI NI NI

NI NI NI NI

Ni NI NI NI Ni

iRale

L LLEYL

9M NI NI

0
144
8¢

YA NI NI NI

1no
1Nno 1N0O
1no LNo
1No 1no 1no
1No

LLLLLY
LLLLSL
LLLLLL
LLLLLT
LLLLET
LLLLST
LLLLLT
LLLLLVE
LLLLEE

1587

LLLLL
LLLLE
LLLLS
LLLLL

2120
jueg
A7098) -~ continued

NI NI NI NI NI

NI
NI

£l vl Gl gl

144 8t

- V) e

= o o) 0

&QoG

1no
1no
1no
ino
1no
1no
1No
1no
1No
1Nno
1Nno
ino
1no

NI NI

1no 1Nno 1No

1no

NI NI

1no 1Nno NI NI

(44

1No
1No
iNno
1no

1Nno

1Nno NI

1Nno

9L 08 v8 88

£¢ e

o€

1No

1no

G¢
g¢

1No

1No 1No
NI

14>

oLl ocl

LLLLSE
LLLLLE
LLLLLY
LLLLEY
LLLLSY
LLLLLY
LLLLES
LLLLSS
LLLLLY
LLLLES
LLLLSY
LLLLLS
LLLLLL
LLLLEL
LLLLSL

AMH

3se

1no NI N! Ino
1No NI

1no NI

1No
1no

18190 jued

Ni NI NI NI

074

1No

1No 1Nno 1No 1No

1No -

1no

1No

S€E
9¢
LE

(gjewida

1No

1no

1no 1no

1No
LNno

1no

L L LS L L LS

SNEINN

3sdig

seipy

1LNo
1no

NI NI

009

9¢

0¢

]! e

0 0 %1 0 0 91
NI NI

8¢ [A

)7 144

1no

1No
1Nno
1no

NI NI NI

Lno
1NO
1no
1Nno
1Nno
iNno

NI NI NI NI NI NI
NI

NI NI

1No
1no

1N0
iNno
1NnO
1Nno

Ni NI

00000¢
0000¢¢
0000%¢
000092
00000€
0000¢E
0000%E

jewde

0 0 ¢t

jueg

000001

CLA
1N0
LNO

1no
1No
Ni
iNno
1N0O
LNo
1Nno
1Nno

0000¢
0000Y

18130

SNEINseipyosedg‘sedwingJemoMW
UBl (M7098) - continued

NI NI NI NI NI

LNo
NI NI NI

NI NI

Gl 91

00009¢
00000V
0000ZY
0000tV
00008Y
00000S
S0000¢S
0000V
000095
000009
0000¢2¢
0000%9
000089
00000L
0000¢L
0000%L

SNAINN

jewise

yueg

14 89
NI

LNO
1No

£¢C

1Nn0O
1no

96 00l
NI NI

1Nno
1No

1No
1N0O
1NO
1No

1No
ino
1No
1No

NI NI

£t vE

801 cll 91t 0Zl 144}

Geg
]
LE

1Nno
1No

14!

1Nno
NI

L€

ino
NI NI NI NI

1no
1NO
iNno
1Nn0o
1Nno
1N0
1Nno

1N0
NI

144
S¢
9¢

l¢

1Nno
ino
1NoO
1Nn0
1No
NI
1Nno
1No
NI
1Nno
NI
1Nn0O

L AM

0¢

1NO
1No
1Nno
1No
1No
iNno
1Nno
iNno
1N0O
1No
1no
ino
1N0O
1Nno
1Nno
1no

8M
|

08
v8

18100
P~ o o 0
z 0 c el Bm = @ -

NI NI NI NI NI Ni

1No

009.L

17098) - continued

UNIBUS

—

ADDRESS

BA <17 13> SELECTS

ONE OF 32 MAP
REGISTERS

0
37g

lzx

o1
1

N
ADDER

l
=

122-8IT PHYSICAL ADDRESS)

[0!

UNIBUS MAP RELOCATION ALLOWS A UNIBUS ADDRESS TO REFERENCE
ANY PHYSICAL MEMORY ADDRESS

UNIBUS MAP RELOCATION IS ENABLED IF SR3<05> =1
TK

4499

Constructing a Physical Address from a UNIBUS Address

MS11-M

3722)

MS11-M MEMORY

MS11-M can accommodate battery backup (H7750). The
module is partitioned for +5V, +12 V, and -12 V battery
backup voltages.

WARNING:

The green LED indicates +5 V BBU is present, in which case the module should not be

removed until such voltages are powered off.
e

The red LED on the module indicates that an uncorrec-

table error has occurred.

When the MS11-M is used with a PDP-11/44, the memory should be inserted into one of the designated extended UNIBUS slots 9-12 in the processor’s backplane.
Jumper W1 must be out.

Power voltage checks:

Voltage

Tolerance Backplane

45V Maximum ripple = .2 VP-P

(.25V)

+5V BBU Maximum ripple =.2 VP-P

(.25V)

BD1

+12 V Maximum ripple = 1.0 VP-P

(.60V)

AR1

-12 V Maximum ripple = 1.0 VP-P

(1.2V)

AS1

AA2Z, BAZ,
CA2

GREEN LED (VOLTAGE
PRESENT)

FOR SETTING

CSR ADDRESS

RED LED (UNCORRECTABLE
ERROR)

\fi D QD
1

. E;] S1

wisS——""_|
=

W1FOR

INSTALL

L uniBUS

opeRATION

ONLY

FOR SETTING THE MEMORY

NOTES:
1.

STARTING ADDRESS AND FOR

INTERLEAVE/NON-INTERLEAVE

SELECTION

JUMPER W1 IS A ZERO OHM
RESISTOR

JUMPER W2 IS NOT SHOWN SINCE 1T
SHOULD NOT BE TAMPERED WITH IN
THE FIELD

[
TR-5982

Switch and Jumper Locations
41

YyIR

A0 A9

440
440
440
440
440
440
440
440

ACB1

ABY ACTLS AGLS
440
440
440
440

NO
NO
NO

440
3440
440
440

440
440

NO
NO

440

3440
440

440

440
440

NO
NO

440
440

NO
NO

ATES
H1968

(LZv)

NO
NO
NO
NO
NO
NO

NO
NO
NO
NO

E-EMS

NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO

C-CMS L-CMS
(Liv)

AGGT
Aoce

(8190
NO

G-ZMSE -TAS
18722) —
continued

0000 000710 00020 000€0 000%vE0 000%0 00080

Aol
A91LCL
A08¢C1
LAPPEL
8OV
ACLpL
0091
ABCLL
9681

jewida

0 0 0v91L

00000001
1100000¥01L
0000001
L 1L
100000%
0000007
1L00000vC1
000000€
LL00000vE
000000%
00000¥Y¥
L00000081
00000%S
00000091

€130

(L2V)

440

8 01 ACSlLl

440

3440
340
440
340
440
440

140
140
440

440

440
3440
440
440

NO
NO

440
440

NO
NO

440

NO
NO

440
440

NO
NO

440

NO
NO

440
440

NO
NO

C-EMS

440

3440

440

(LLY)

L-ZMS

440
440
440
340
440
NO

G-CMS v-ZMS €-CMS
M (M8722) — continued

LJ9EG AP9 1 AC6L1

440
440

SNFIN 10PepuaixeSNGIN uonesdojo8ylLSINALstpeioajesAqLM

440
440

4 0 = 'LNO = 0 =pepusixySNE8INN

G-CMS

440
440
440

L-ZMS
NO

00 M~ o

o <) c ] h= = ® °

¢CTMS (8LY)

(61V)

(0Zv)

PSRN=YEIPNON

M LM

pepuexy

coLeLLLl

SooLZLLLY
NEINN s eip y

440

NO
NO
NO
NO

(rOV)

SeIpy 0LlcL

440
440

(E0V)

NO
NO
NO
NO
NO

440
440

LMS ¢

3440

440

(¢ov)

L-LAAS

[AVXANA
YOLZLL
90L¢ZLL
OLLZLL

SNGINN

310N

9-ZMS

440

L-CMS L-CAMS

paABa|1a1yUI-sUaONlBuiuiewesyouamssuoneinByuospjnoysieasu8q‘pesn

9pON

IisA|VpIaTneHsIjiLsNiuI]SNNIOAII/LWVNHINOIINOD
pAuLgiHpVaYndesj1iSaiOujSad3oH/AW3WYNSNOILVHNDI NOD
NO

440

v-LMS
(LOV)

MS11-M (M8722) — continued

YOLCLLY 90LZLLn OLZLL)

440
440
340
440
440
340
440
3440
NO

440
440
3440
440

NO
NO
NO

440

3440
440

440

440
440

NO
NO

NO
NO
NO

440

440
440
440

(YOV)
3140
440

LMS¢ E-LAMS (Lov)
P-LMS
NO

(E0V)

OEleLLl 9ELCTLLY

ocleL [A XAN OELZL 9€lcL

440 = 'NOL

cliecliLi QLCLL

vilcLL
9LLCLL

(Zov)

L-LAAS
MS11-M (M8722) — continued

MEMORY MANAGEMENT
MEMORY MANAGEMENT RELOCATION CONSTANTS
Relocation

Physical
Bank

Physical Address

Constant

(4K)

000000 -017776

0000

(8K)

020000 - 037776

0200

(12K)

040000 - 057776

0400

(16K)

060000 - 077776

0600

(20K)

100000 - 117776

1000

(24K)

120000- 137776

1200

(28K)

140000 - 157776

1400

(32K)

160000 - 177776

1600

(36K)

200000 -217776

2000

(40K)

220000 - 237776

2200

(44K)

240000 - 257776

2400

(48K)

260000 - 277776

2600

(52K)

300000 -317776

3000

(56K)

320000 - 337776

3200

(60K)

340000 - 357776

3400

(64K)

360000 -377776

3600

(68K)

400000 - 417776

4000
4200

(72K)

420000 - 437776

(76K)

440000 - 457776

4400

(80K)

460000 - 477776

4600

(84K)

500000 -517776

5000

(88K)

520000 - 537776

5200

(92K)

540000 - 557776

5400

(96K)

560000 - 577776

5600

(100K)

600000 -617776

6000

(104K)

620000 - 637776

6200

(108K)

640000 - 657776

6400

(112K)

660000 -677776

6600

(116K)

700000 - 717776

7000

(120K)

720000 -737776

7200

(124K)

740000 - 757776

7400

(128K)

760000 -777776

7600

IORY

MANAGEMENT
— continued

STATUS REGISTER BITS

151412121110 090807060504 03020100

UNCORRECTABLE __l
ERROR INDICATION

A1T|ATS A3

|A20f

L_ UNCORRECTABLE
ERROR INDICATION
ENABLE

EUB ERROR

ADDRESS RETRIEVAL

ERROR CORRECTION
DISABLE

INHIBIT MODE
ENABLE

DIAGNOSTIC

cTi{ciefca|Ct

NOT USED

CHECK

A6 Al4 A1Z
or

INHIBIT MODE

POINTER

SINGLE ERROR

A2l AIS

0
or

c32

INDICATION

|R
——

ERROR ADDRESS/CHECK BITS
TK.5981

Control and Status Register

VIRTUAL
ADDRESS

[

13
P

;._T_.__)\

SELECTS

{

06 05

PLus———J

‘]

I N

PAR

]

EQUALS
v

PHYSICAL

S————
00

ADDRESS

TK.4494

Physical Address Generation, 22-Bit Mapping

- continued
MANAGEMENT

ORY
SRl

17 777 574 READ ONLY
15

1110

08 07

———" N———

[

CHANGED

SR2

s3]

P |S

—

AMOUNT

e e

CHANGED

|7 777 576 READ ONLY

121

02 01

|
VIRTUAL PC

772 5l6

SR3 |7

RIR IR

1[R IR Ir

ENABLE UNIBUS MAP

ENABLE 22 BIT MAPPING
ENABLE CALL SUPERVISOR

ENABLE KERNEL D SPACE
ENABLE SUPER D SPACE
ENABLE USER D SPACE

TK 4426

Memory Management Registers
PAR'S R/W

1]
15

18 BIT MODE RELOCATION CONSTANT

22 BIT MODE RELOCATION CONSTANT

PDR'S
15

05 04

Pl PP BT £ T
l

CACHE BYPASS
PAGE LENGTH FIELD
WRITTEN INTO

ACCESS CONTROL FIELD

SRO
15

17 777 572
1 413

R | R1R

glaazy.
Yy

ABORT:

08 07

05 04 03

njank

\'—'—fl p—

NON-RES

ABORT. PAGE LENGTH
ABORT:

READ ONLY

MAINTENANCE MODE
MODE
1/D SPACE

PAGE NUMBER

RELOCATION ENABLE
TK-4495

Memory Management Registers

MEMORY MANAGEMENT - continued
TUS8 JUMPER CONFIGURATIONS

IN: Enable receiver error bits (15:12).
QUT: Disable receiver error bits (15:12).

Wi0

IN: Enable break bit.
QUT: Disable break bit.

IN: Enable parity.

W11

QUT: Disable parity.

W12 & W13

Character length for TU58 UART.

Jumper

W14

5 Bits

6 Bits

7 Bits

8 Bits

W12:

QuUT

ouT

wi13:

ouT

QuT

IN: Odd parity.
OUT: Even parity.

TUS8 BAUD RATE SELECTION
Switch Pack E7

Receiver Switch

Transmitter Switch

OFF

Baud Rate

38,400

OFF

9600

OFF

Console RCLK

OFF

Switch S7 is not used

MEMORY MANAGEMENT — continued
SWITCH PACK E70

————\02

13—

ADDRESS BIT

DATAHIIHIHHHHIIHHH
At
NoT swiTH IT_?“

SWITCH ON= LOGICAL 1,

OFF=LOGICAL 0
TK-3637

TU58 Device Address Selection Switch Pack E70

SWITCH PACK E79

BUS DATABIT

0706 050403020100
1514131211100908

o T 11T bl

NOT SWITCH

NOT

SELECTABLE

SWITCH
SELECTABLE

SWITCH ON = LOGICAL 1, OFF = LOGICAL O

NOTE: DATABIT# 21S0 FOR RECEIVER VECTOR AND 1 for TRANSMITTER VECTOR
TK-3638

TUB8 Vector Address Selection Switch Pack E79

LINE TIME CLOCK
W2

IN: Enabled
OUT: Disabled

MEMORY MANAGEMENT — continued

VIRTUAL

ADDRESS

ouaEEnn
21

]

—

PHYSICAL

ADDRESS

TK 4480

Physical Address Generation, 16-Bit Mapping

VIRTUAL

[

1312
P

ADDRESS

]

SELECTS

l 15

l—

12° 11

PLUS'J

{

PAR i NOT USED ]

l
J

EQUALS
<17

PHYSICAL {

1817

13>

{

}

ADDRESS

4491

Physical Address Generation, 18-Bit Mapping

H7140 POWER SUPPLY

The dc LED on the front panel must be lit. If the dc LED is
blinking check the following:

All dc voltages. Replace H7140.

Battery backup jumpers on DD11-CK or DD11-DK
backplanes. The jumpers should be out. No voltages
on the backplane should be jumpered together. The
jumpers are usually #20 insulated bus wire.

D25 on the M7090 module is in backwards. Replace
the M7080.

H7140 provides the following voltages:

+5.1 Vdc at 120 amperes
+15.0 Vdc at 3 amperes
-15.0 Vdc at 3 amperes
4+12.0 Vdc at 5 amperes
-12.0 Vdc at 1 ampere

+5.0 Vdc at 10 amperes

Battery backup option (if applicable)
The BAT LED on the front panel indicates battery backup
status. If the "BAT"” LED is:

Continuously ON - battery backup is present and
greater than 90% charged.

OFF - no battery backup is present or it is fully discharged.

Pulsing at a slow rate (1 Hz) - battery backup is present and less than 90% charged.

Pulsing at a fast rate (10 Hz) — battery backup is
present and being discharged.

POWER SUPPLY — continued

CPU MODULE CURRENT REQUIREMENTS
Option

{(Modules)

Current
+5.1V

+12V

-12 V

+5.1 BB

1.0A

50 mA

1.5A

KD11-2

M7090

05 A

M7094

7.5A

M7095

75A

M7096

50A

M7098

7.0A

KK11-B

M7097

6.5 A

FP11-F

M7083

A
7.0

KE11-A

M7091

3.1A

M7092

6.0A

MS11-MB

M8722-BA
M9302

48A
1.5A

Digital Equipment Corporation « Bedford, MA 01 73{3»

}
|