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EK-NIA20-RM-001

January 1985

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Document:	NIA20 Technical Reference Manual
Order Number:	EK-NIA20-RM
Revision:	001
Pages:	292
Original Filename:

OCR Text

EK-NIA20-RM-001

NIA20 Technical
Reference Manual

dlilgliltial
i}

EK-NIA20-RM-001

NIA20 Technical
Reference Manuadl

Prepared by Educational Services

of
Digital Equipment Corporation

lst

All

Rights

Printed

Digital

Equipment

manual.

Reserved.

U.S.A.

in this manual is for informational
is subject to change without notice.

responsibility

this

January

Equipment Corporation 1985.

The material
purposes and

Edition,

for

Corporation

any errors

assumes

that may appear

This
book
was
produced
on
a
DIGITAL
Word
Book production was done by
Processing System.
Educational Services Development and Publishing
in

Marlboro,

The following
Corporation:

MA.

are

trademarks

Digital

Equipment

dilg]i]t]a] 1 |

MICRO/PDP-11

RSX

DEC
DECmate
DECUS
DECwriter

MicroVAX
PDP
P/0S
Professional

RT
UNIBUS
VAX
VAXcluster

DIBOL

O-Bus

VMS

LSI-11
MASSBUS

Rainbow
RSTS

VT
Work

Processor

1985

CONTENTS
Page

PREFACE

Control

CBUS—PLI

Interface

Module

MOdU].e

(M3001).....00...

Module

(M3002)....

(M3003) ® 00 000606060000

TranSCeiver'...........‘..0.......0.......

Transmit

FUNCEIOoN. ... eeeeeoeseceooocooeceessss

Watchdog

Timer

Collision

FUNCEioN
e eereeonc
...e
oooecess
ee
s

e e

ALU

Microprocessor

Interface/Port

Port

Presence

FUNCLIiON.eeeeeeesoooocecnssal=7
Collision Presence Test Function (Heartbeat)...l1-7
Receive FUNCEioN.ieeeeeeeeeeesescesncacoconnseal=?
DC

CONVerter.ceeeeseeesoseocoossescssceeesl=7

Coaxial

Cable

Maximum

Packet
Packet

Minimum

SiZ@.eeeeeeeeeeosoeeocoonnooceceslm

SizZe...veeeeeeoseeoscoooooocosneslm

Preamble. ...t ieeeeeeeeceeeensscsensescsessscocesslm

YO 0

ConnecCtioN...eeeeeeeececcoceceesasl=7
Transceiver Cable ConNeCtioNS..eeeeeeceoeoessssasl—
ETHERNET SPECIFICATION OVERVIEW. ..0eeeeeeeocooaosaesl—
Packet Format..............-............l‘........l—

WO WO

wN
-

*
.

]

[}

OO
WN

o
o
¢

QOO
WN
=

o
o

ModUle....eoeeeeosen

EBus

Destination AdAreSS..c..eeeeeceeseeeeccscssccssssl=9
Source AddreSS..ceeesseeseosssessssesceosanssnsal=l0
TYPE

Data

Filield...iiieeieeeeeeeoecoonesssnnencessneal=l0
Field..ieeeieeeeeeeeeenosoesosasoscooannnsal=lO

Packet

Check

ROUNA=Trip
ContrO].

Adapter

Port................Q........O..........0...0....

H4000

Urdd

oVERVIEw..................l.........

Interconnect

SUBSYSTEM

I
VRN,
We W W, W, IS

INTRODUCTION

Network

e
o«
.

[]
[
L]
.

»
o
«

o
o
&
o
o
o
e
¢

VU WNNNNNN
R
e

WWWWWWwwWwWwhhNDNDN

NNMNNNOMNNNNNONNNDNNNODNONNNONDNONNNODNE
R
b o b e e e

AP S
R

S
.

o S Ty SV

ol el e e e el el el

o
o

e el

&
o

e e

¢
o
®

el e e

NIA20

[

S S

CHAPTER

SequUenCe..cieeececececcesssncaeeal=10
Delay..eeeeescececccecosoccnsasnseeal=l

ProcedureSoooooooooooooo‘oooo.ooo..oooool—lo
-o
s X

Transmit. ...ttt eeeeeeeeeeoeooeesscssnsseseessl=ll
2 ¢
o D,
e 1 |
RetransSmMit..eeieeeeeeeeeesoeoooonsonosssssesesasasl=ll
BACKOEf . it iieeeereeeeeeoecaceanosescesnsoonsnsnsl=ll
Manchester Encoding.....
ooooooooooooooooooo.oool-ll
CaArriler SeNSCiueeeeceeeeecoosoaccoasosesssssssesl=l?
Transceiver ConNNeCtioNS...ueeeeeeosesesocceceocessal=l?
TraANSCeiVer S .ttt eeeeeeeeeeeeeooscenosssseescesoaal—l?

iii

CONTENTS

(Cont)

Page

LoCAtioNS..eceeeececscscsocsoscscsssoscsssscsncsocasse

HANDLING .o e e coecocooococsocscssoosossosssscssse

&
o

dWwN

Linking.eeeeeoeeooeeecssoscscsscccnossosoceaos

Entry

Removal...eeececesescsocesossceccscsocsssnscsscs

Buffer Segment DesSCriptorS...ececececccsccecscsns
Buffer Segment Descriptor Format....eeceeveeee2-13
COMMANDS AND RESPONSES . ¢ eeccecososcsoscssoscscsssecesl2—ld
Command and Response FormatS.ecceeecececsccsceeeas2—1d
Send Datagram (SNDDG) Command....cscecesseessess2—l5
Datagram Sent (DGSNT) ReSpPONSE€icceacecsccssesasl2—l9
Datagram Received (DGRCV) REeSPONSE€.icesssosssse2—21
Load Protocol Type Table (LDPTT) Command......2-24
Protocol Type Table Loaded (PTTLD) Response...2-25
Load Multicast Address Table (LDMCAT)

HeaderS.eeeeececoesssesocscsossscssssssscscnscsse

Entry

)
|
L
NE~OYWOOWWNN
-

INterloCKS . ceeeecocecesocvsoosssassncsssssoscss

QuUeue

ComMMANAd . eeeseccooscosssesassssosccosssosccsnsssseealr2d
MCAT Loaded Response LDMCAT...ceeeteenoscasess2—26
Read

LinKage.ieceeeeeosocsocsescssscsossosssscsssocssonas

Queue

[]

[\)No
[
|
NN
NDN

w N~

o
o

WWwwo
-

s
o

eel

L[]
[]

OVERVIEW., ¢ ¢ c e ctecoevoccccnsscenscoscsse

STRUCTURE ¢ e ceeovesccocscecossoscccscscsscsoscscsoscse

Queue

QUEUE

¢«

PRPLWWWWWWNDDNONDNDE

IMPLEMENTATION
IMPLEMENTATION

QUEUE

[]

DNDNNDNDNMNMDNNODNMNNDNNODNDNDNDDNMNNMNDDNDNDDN

CHAPTER

and

Clear

Performance

Counters

RCCNT

= \D

NoO
S W

[]

)

[
et b
L[]

L]
et b
[]
L]

[]

1]
[]

L]
|]
b
[]
b
L]
[]
L]
[]
N = = b

Read Port Link Interface (RDPLI) Command......2=-33
Port Link Interface Read (PLIRD) Response€.....2-34
Read NI Station Address (RDNSA) Command.......2=-35
NI Station Address Read (NSARD) ReSPONS€ese...2—36

Write NI Station Address (WRTNSA) Command.....2-37
NI Station Address Written (NSAWRT) Response..2-38
Self-Directed

o
&

WN
-

Commands

FORMATTING/PACKING

MAINTENANCE

L4
e
o
wnN
-

WWOWWOWWONNINNJO0O
01 .o 0 0 DD DD

Counters Read or Cleared (CNTRC) Response.....2-27
Write Port Link Interface (WRTPLI) Command....2-32
Port Link Interface Written (PLIWRT)
RESPONSEC .t eeecesececoescsscensssosssssssscsssosesesl=33

DATA

o
e
o

NNONNMNDNNDNDNMNMNNNMNMNDNNMNDNMNMDNDNNDDNDN
®
*
o
9
L]
L]
[]
[)
.
[]
[

BSOS

ComMaNd.eeeeeceeoocesssosossossoccsccsonsscoscsnssccseelr2]

OPERATION

—-—

Loopback..eeeeeeeeeesea2-38

MODE .. ccoeoeccccssssccsess2=39

PROTOCOL.:ccceoseccsosssccsceessl2=39

ERROR HANDLING . ¢ceeotooossoscooscscsocososssosssccsesssscsel239
EXror EVENtS.eeeecesccecscsssosossscoensnsssssnsasseel2=ll
Discarded DatagramS..ceeseesecsssssccsccsscscoseasl2il
Event CoOUNtEerS.eceeecocscccccscssascsossscssnscsccssssl—idl

NETWORK ARCHITECTURE AND FUNCTIONAL
Physical Link Layer and Data Link

ROUEING

LAYERS........2-43°
LayerS..e.e....2-43

LAYEr ceeeeeeerssocsnssoscososscccssssceesl2=dd

End-to-End

Communications

Layer..cceeeeeeccecoes.2-44
"

CONTENTS

(Cont)

L oOoJO0
U b

O
e
O
e

OO WYY

NDNNNMNDNDDNDDN

Page

RWN

Layel..eeeeecscceosoceces ...2-44

Network

Management

Layer....ceecececeocccsacecs ...2-44

USEr

LaAYyer eceeeoeoeoseosocsansesccssscscosssccssaoa c..2-44

Layer

InterfacesS..ceececeecescoscecscccscccocaes ...2-44
ETHERNET

INSTALLATION
OF

NetwWorKS.ceeceeeeoeoooooceoso «eo2-45

NIA20

AND

NEEDED

KL10-E

CHECKOUT ® & & & 6 6 & & & &6 8 O 0 5 0 s 0 P
FOR

INSTALLATION

oSO 000 N

AND

CHECKOUT. «oee3-7
PROCEDURE......................... eese3-8

Preinstallation CheCKOUt.eceeeeeeveooosoeoonsesos cees3-8
Backplane Wire AddS..eeeeececcesccccccccnceaes eees3-8
Installation of Port ModuleS..eeeeececonocoss ees»s3-9
Power

Supply

Regulator

Installation....ceecces eee3-12

of NIA20 Card Cage/Internal Cable..3-13
Installation of NIA20 Current Limiter...... 0003-17

Installation

Harness InstallationNeeeeeecesceceoccococooe 0003-17
Installation of KL10 Adapter Board and Blank

B D

YT
D WN

o
o
o

UNPACKING
EQUIPMENT

INSTALLATION

o
e
e

Layer..eeseseseseccsccococces ...2-44

OVERVIEW...............0..................‘.... eees3-1

o
o
o
o
e

Control

Application

Expanded

CHAPTER
WWwWwwWwwwwwwww

Session
Network

Module

Assembly...ceieeeeseceoscscacosccssncnaes * o 03-23
CheCKOoUt it eteeseesecessoosccccaccscsoccosccssos 0003-24

FUNCTIONAL

DESCRIPTION

w N

9
©
e

STATES. ® & 6 &6 & ¢ & & 5 6 6 0 O 6 O O O P O s O s s OG0 o000 e ....4- 1
4Uninitialized. ® & & & 5 ¢ 5 O 5 5 & O O & 0 0 S 3 0 0 s OO eSS e cee.d-1
Disabled. o @ & o 0 o . ® 6 & & & & & 0 5 & 8 O O O 0PSO S I P W S 0 0 9 0 0 ceeosd-1
Enabled.....Q.'..Q.......O........00.....0..0 ceelsd-1

CONTROL

[]

AND

STATUS

cee.4-6

EBus

InterruptS.ceeececssecocsccccsescsvossoasssas «s.4-10

Examine/Deposit

RequeSt

ReSpPONSE€.ccseevsssens ceood-12

CBUS i it seeeosecesevcssssssscesssssoscsscsscnssnsas ee.4-13
et eeeeeoccosesceocsscssescscscscscsossoccsosocsscsse ...4-20
PLI Interface SignalS.eeeeecsceocecsosssssccncas ...4-21
Data (7:0)
(Asserted High) ieeeeeeeeoeeoeoeonse .c..4-21

Select (Asserted LOW) cceeeceosccoccossocncose eeed-21
Receiver Attention (Asserted High) cceceeecess ...4-21
End of Frame (Asserted High) .ieeeeceveeeoeccnes «e.d4-22
Transmitter Attention (Asserted High)...oee.. eee4-22
bW

o
o
e

NN NN

[]

PLI

VOO
UOU DWW WN

o
o
®
e
e
e

o
o
o

PORT

B
O

[

[]

DD DD

CHAPTER

PLI/Link Control (Asserted High)...eoesceoeee ceed-22
Write Transmit Buffer (WT XMIT BUF) .ceeee.n «..4-23
Transmit Action (FOUR COMMAND) GroUP...se.. ...4-23
Read

Transmit

Read

Receive

Status

Buffer

(RD

XMIT

REC

STATUS) ce.e... ...4-24
BUF) e oceoecocoss ...4-24

CONTENTS

(Cont)
Page

Read

4.5.7.5

(RD

0004—'24

0004-24
. 004_24

.ee4-25

LOGIC

DESCRIPTION
MODULE........

« oD

IntroduCtion\il.'.....'..................

INTERFACE

AND

PORT

ALU

Lo
ol

e
b=

U
W N -

&
e
o
e
e
o
o

= O
o

=
N

EBus Control and Status Register.ceececeececes R
EBus Control LOgiC.iceeeosecesescsossosccncscoas «ee5-1
Port Microprocessor Not Running....ceeececee ...5-14
Port Microprocessor RUNNing...eeeeeesccses
ee.5-15
*

e
e
o
«

I—‘I—-'KQW\]O\lU'IbwwwaJNI—‘
= O

o
o
o

*
[

b
b

o
¢«

=
N
NN NN

W
N

@
e
¢
s
o

.0 04—24

ooooo

EBUS

«..4-24

...4-25
Clear Receive Buffer (CLR RCV BUF) ceeeceees «o.4-25
Write Address Register (WT ADRS REG).voeesee ...4-25
Read Register (RD REG)...ID............I
.s.4-25
» «4-25
Write Register (WT REG) .i.seeeocscscscss
(TTL Asserted High).... «o.4-25
Transmit Parity (0dd)
(TTL Asserted High) .eo.4-25
Receive Data Parity (0dd)
...4-26
Clock Timing (PLI BusS) .ieeeososse
Initialize (TTL, Asserted High)....e....
.e.4-26
Receive and Transmit StatuS....ceececesscas
...4-26
...4-26
SIMPLIFIED NIA BLOCK DESCRIPTION..:¢ceccoeoe
... 4-27
Simplified Transmit Operation,...eeeeees
Simplified Receive Operation...ceeceececss
«s.4-30
®

CHAPTER

(WT REC BUF RD ADRS REGISTER) ¢eceececcccse
Write Free Buffer List (WT FREE BUF LST)..

HHHEFOOJINNdNJ

o
®

Syttt
gt U

D
DD
DD
D
DS
DD
B

Db
D

4.5.7.7

Status

STATUS)..'.i.....0‘...............

Read Receive Memory Used Buffer Address
List (RD USED BUF LST)........Q.‘.......‘.
Transfer Byte from Receive Memory to the
Transmit Buffer (REC TO XMIT BUF)....
Reset Receive Attention (RESET REC ATT) ...
Enable Link Control/Disable Link Control..
Write Receive Memory Buffer Read Address
to the Read Memory Address Register

4.5.7.6

U
aoag

Receiver
REC

Interrupts............0..........
«s+5-16
Examine/Deposit Request ResSponNSe..ceesecses
«++5-19
Microprocessor to EBus Register.icesececscss
...5-20
EBus to Microprocessor Multiplexer (EMUX).... «es5-20
Microprocessor to EBus Multiplexer (KMUX)... «ee5-21
EBUS Parity Generator.‘.....................
«es5-23
EBus Parity Checker...cee..
«ee5-23
EBUS Transceivers......0.’......0............ eeeD—23
Arithmetic Logic Unit.......OO...........O.. «..5-23
Constant MultipleXer.iceeeeeesseosesocasn
«..5-26
CBUS/DATA MOVER (CMVR) INTERFACE MODULE...
«se5-27
CMVR Control LOgiC.:.sscevoeeeoscscscosacs
«++5—28
Data Mover and Formatter (MVR/FMTR).....
«e.5—29
Data Input Multiplexer.....eceeeeeesccecs
«e+5-33
PLI Serial Up Multiplexer (SUMUX) .ceeeeo
+..5-33
EBUS

CONTENTS

(Cont)

OV U

Down

Output

Multiplexer

O 00~

CMVR

S wN
-

(CBUF)...

..5-35

Buffer.....cceeeerieeceececccens

..5-36

Checker.....

Buffer....iceeeeeecenns

9
3 & 0
@

L
[
¢
[]

[

L
[)
\J
[)

[}
*

..5-39
..5-41

..5-41

Condition
U S WA

Code Multiplexer...
MicrosequenCer..cceeeeeeeeeoss

RAM

Address

O 0 N

Latch

Address

..5-44
..5-46

Address

..5-47

MultipleXer....eeeees

..5-48

Control

RAM..veeeesesoeacconas

Buffers.........v.e

..5-48
..5-49

Parity Checker.eeeeeeesen
RegisSter.icessvoeescencess

..5=-50
..5-50

CRAM

- CRAM
CRAM

Load

Microword

oAU dWwoEHEO

..5-39
«e.5-39
.5-39

[]

MICROPROC.4
ESSOR.
eeeeeasss

[]

Parity Out Generator...
PLI Control LogiCeseeeeeons
Parity Predictor...eceeeeeesee
PLI

..5-36
..5-36
..5-38
..5-38

Checker........

Buffer....

Output

L
L]

Parity

PLI

L]
®

PLI

[]

Out Parity Generator....eee...
Control LogiC.eeeseeeas
Input Buffer.....coece..
e

..5=-36
..5-36

Parity

[

PLI

..5-34
.+«5=-35

(CMUX)..

CBus

CMVR

Field

Definitions..

...5-51

= = =

Microword Output Multiplexer.
Jump Multiplexer.ceeeceeeceeese
Local Storage RAM...veeevs
e
RAM Mode Multiplexer..eeeeceeens
Local Storage Address Register.
Skip Condition Field Decoder...

Microprocessor

Control

««5-62
«.5-62
.+5-63
«+«5-63
.+5-64
..5-64

Logic...

«+5-65

MICROCODE
. eeeseoeesccooscascaess

..5-65

Initialization.ieeeeeseenneeces
Idle

««5-65

LOOPeeeseoescsccsonocosnosse

RECEIVE .ttt evesssveassioencecs
Transmit and Local Command.....
A

..5-34

Multiplexer

[

Qutput

(SDMUX)...ceeeeos.

(PMUX) .ceeeeeoooosceos

=
b
=
e
e
CoOoONONUIDdWNDHFO

CBus
CBus
CBus

Multiplexer

Microprocessor

Input

CBus

PORT

APPENDIX
> >
>

Microprocessor

L]
o
o

o
s

Serial

PLTI

=t =

L]
o
o
&
¢

PLI

S W
-

BB
BB

D WWWWWWLWWWWWWWWWWWWWNNNONNNDMODNDNMNONNDNDND
DN

Page

INSTALLATION

OF NIA20 IN

AND

EQUIPMENT

NEEDED

INSTALLATION

CHECKOUT
.. ¢eceooees
FOR

.+.5=-70
«e5=-73
..5-81

KL10-D

OVERVIEW.....00............"

UNPACKING

INSTALLATION

toooaoooooooo..o-oA—l
»

AND

o o .A—7
CHECKOUT.....A-7
¢

PROCEDURE....C'............'..........A-7

vii

CONTENTS

(Cont)
Page

A.4.1

Preinstallation

A.4.2

Backplane

Wire

Checkout.i.isiccoececesccnseossssA-T
AddS...eceeeeceassososesscssssescsesA—8

A.4.3

Installation

A.4.4

Power

Regulator

A.4.5

Installation

Supply

Port

A.4.5.1

Installation

A.4.5.2

Harness

ModulesS....eeeseecscscscsesA=9

NIA20

Installation......ece....A=-13
Card

NIA20

Cage/Cable...........A-14

Current

Limiter.........A-17

Installation...cceeeceesoceescssssoeaesA-1l7

A.4.6

Installation

A.4.7

Module Assembly....evecevececsccscscsrnseecceeseeBA=23
CheCKOUt .ot oeeooeoeesesesnscssscansassnsescsesA=24

APPENDIX

INSTALLATION

KL10

NIA20

Adapter

Board

and

Blank

KL10-R

B.1l

OVERVIEW. .o oo ceeeeoeecsccasstooscosssssssssscssscsscsassseB—]l

B.2

UNPACKING

B.3
B.4

EQUIPMENT NEEDED FOR INSTALLATION AND CHECKOUT.....B-7
INSTALLATION PROCEDURE ... ceeeeseeccoeecoccssscsosossosacesd—8

AND

CHECKOUT . et eeseoeeossosssssossessssascseB—7

B.4.1

Preinstallation

B.4.2

Backplane

B.4.3
B.4.4
B.4.5
B.4.5.1

B.4.5.2
B.4.6

Checkout.ieoeeeeeseesececasesasssassB—8
AddS...cceeeocooscscscscsosscsansceaB—8

Installation of Port ModuleS....eeeoceceoscassansB=9
Supply Regulator Installatlon.............B-l3
Installation of NIA20 Card Cage/Internal Cable..B-13
Installation of NIA20 Current Limiter.........B-17

Power

Harness Installation...eciosiieovocessssveessB—18
Installation of KL10 Adapter Board and Blank
Module

B.4.7

Wire

Assembly...cieeeeeeeceesossssessscsancssssB—24

CheckoUt iuiieesisovesoencseccsosoossscsscscsacsoscsnseB=25
FIGURES

Figure No.

Title

1-1

Large-Scale

1-2

Simplified

1-3

Ethernet

1-4

Manchester

2-1

Queue

2-2

QUeue

2-3

KL10

Memory

2-4

Error

Word

Ethernet
NIA20

Data

Page

Configuration...eeeeecaseeesssl=2

Block

Packet

Diagram..eeeeeeessreesccsessl=4

Format...eieeeeeecsseessccasesl=9

Encoding...icceeeeeecesssssssscenrsossseeaal=ll

Entry

Format......cseessessesscacssossssasnoessl-l
LinKaAge .ie:iieeeeesscovseossosoccssssasccsnocccesl
2

2-5

Protocol

2—6

Multicast

PCB
3

Type

FOIrMAt.ieseesoeececssrssoscescsscsesl4

Format...eeeesssseesoscscsccscscnccncsel=D
Table

Address

Format.seeeeseeoess

Table

sseessssesseal—b

Format.....................2—7

2-7

Queue

2-8

Use

2-9
2-10

EMPtYy
Queue

QUEUE .. it e veeossccscssossssasscccsonsssssssssesld—lO
with Entry at Address A...ceeeessecssssesseesl=1l0

2-11

Entry

Address

the

Tail

the

Queue.......2-10

2-12

Entry

Address

the

Tail

the

Queue.......2-11

Header

Format..ceeeeeesessosccscscecsrosssasee’2=8

Queue

HeadersS....coeeeeevsosescsccsscccsenaanl9

viii

CONTENTS

Queue

Containing

ACan

(Cont)

Entries

and

2-14

BSD

2-15

SNDDG

2-16

SNDDG

2-17

Send

2-18

Non—-Send

2-19

Destination

2-20

DGSNT

Response

Format

(Non—-BSD)

2-21

DGSNT

Response

Format

(BSD)....

Format,
.,

Format

(Non-BSD)

Datagram..eeeceseooss

2-24

Originating

2-25

LDPTT

Command

Format...

2-26
2-27

PTTLD

Response

Format..

LDMCAT

Command

Format..

2—-28

MCATLD

Response

2-29

RCCNT

Command

Format...

2-30

CNTCL

Response

Format..

2-31

WRTPLI

Command

Format..

2-32

PLIWRT

Response

2-33

RDPLI

Command

2-34

PLIRD

Response

Format,.

2-35

RDNSA

Command

Format...

2-36

RDNSA

Response

Format..

WRTNSA

Command

Format..

NSAWRT

Response

[]

Format.....

NN
N

Address

Field

from

Address

[]

Format

Port

Queue........
Format...cseeee.

[)

Format.

Format...

KL10

Functional
=

Word
(Industry- Compatlble Mode)
Digital Network Architecture (DNA)

LayerS..eeeeeescscscocccocosss

DNA

and

Command

Response

Where

Datagram..e.eeeeceeeeseesss

Status

W wWww

(BSD)....

DGRCV

O W WO

Format

2-23

i
I
N WD

Command

2-22

WWwwwWwhN

Removed..........‘...........C......

DECnet

Layers

NIA20

InterfaceS..eeececececenss

Network

with

Many

KL10-E,

Rear

NIA20

KL10-E,

Front

MBus

Cable

Ethernet Segments.
view...b......O......

Interboard

View......O.....O..‘
Connection,

Top

NIA20

De-skew

Timing.

External

Sync

NIA20

De-skew

Timing.

EBUS

MTR

MBOX

H7420

CLK::ieeeeeeesrs

Power

CLK
&6

Card

Cage

NIA20

Card

Cage

NIA20

Current

Limiter..eeeee..

NIA20

Harness

and

ViewsS..... .o

KL10-E..eeveowoeonseonans
Cable

oooooo

Cable

and

Power

Interconnection

DC Power Cable..Q.........l..’ll"'l..
Vane Switch Cable.v.eeeeeeececeesss
Vane Switch Harness Installation...
DC Voltage Monitor Cable
AC

and

Supply....

NIA20

Fan

View..

(CHTO

Cord.eeeeees

Diagram.

00000

Block

Diagram....

Signals..ceeceeeceesorsaeocconcooococass
Word.eeeeeoesesoeoses

Simplified

NIA

Block

Diagram........

PLI

Interface

PLI
CSR

Interface Receive Flow Diagram..
BitS.eeeoeooesooorrseascsesnncnses

IOP

Function

EBus

Transmit

Diagram.

[

Microprocessor
ALU

Constant

Block

EBus

«s.4-35
S

e»s5-16

eseD—21
¢ eeD—22

(Simplified)

.. eD5-24

(Simplified)....

«oeD=27

DMUX

(Simplified)..cevvveeeeensnns

SUMUX

«ee5=32
«se5-33

SDMUX

(Simplified) ceeeeeecesoeenss
(Simplified) ceeeeeeecocossns

PMUX
CMUX

o~.05_33
«.+5-34

(Simplified)...eeveeeeeenen. (Simplified) ceeeeeeeecoocenssan

5-19

RAM

Buffers

Output

Mode

[]

5-20

Initialization
Idle

5-22
5-23

Receive Microcode Flow Diagram.....eeeces.
Transmit and Local Command Microcode

Microcode

Flow

KL10-D,

ReaAr

W N

NIA20

KL10~D,

Front

MBus

Cable

«ee5-71
«se5-74

Interboard

MBOX

ceeA-2

VieW..oceeeceeooooeaos
Connection,

CLK...... ceces
et e oo

Top

eee.A-3

View...

«..A-10

H).
2

+ o oA-11
0

SUPPlY.ceeeeeveoennonssons

NIA20

Card

Cage

NIA20

Card

Cage

VieWS.cieeoertonsesaoooonoasoses

NIAZ20

Current

Limiter...eeecensecceccncons

NIA20

Harness

and

Power

KL10-D.uveeooean

Cable

.A-12

«..A-13

Power

»5-82

VieW..eeceeocooooses

NIA De-skew Timing. External Sync
(CHTO
NIA20 De-skew Timing. EBus CLK L and
MTR

Diagram....

Diagram.........

Diagram..eeeesesosseccccecconeosossesos

NIA20

H7420

«se5-62
ees5-63
ce.5-66

(Simplified)....oeee..

5-21

Flow

+s+>-48
.++5=-50
ces5-62

(Simplified)...ceeeeeesss

Multiplexer

Loop

(Simplified)

es+5=-35
«++5-35
«..5-44

[]

(Simplified)......

Multiplexer

CRAM

(Slmpllfled)...
(Simplified)....

Diagram

Multiplexer

[

Block

[}

Am2910

Address

eee5-29

[

]

Timing.eeeeeeeseeocecones
Mover/Formatter Data FloWe.coeeee..

Jump

»».4-28
...4-31

Clock

5-18

3’3’?3’3’

Port

5-17

H W3O

c..4-16
.c..4-18
«..4-20
«eod-27

[]

Multiplexer...

Diagram

Multiplexer

Load
Microword

D>>3>3|>3>3>'

Control Word.....eoee..
Microprocessor Multiplexer..

AM2901

Flow

[]

Diagram

[ 4

...4—10
c..4-14

[]

Block

Simplified

TiMiNg.ieeeeersoneeesoscscccssas

[ ]

PLI-to-Port

Clock

Signals....... cetocessssesssense
Operation...icesceeeeecccoccenss

CBus
CBus

Diagram....

[]

Block

Control

Simplified

Function

CBus—-to-Port

IOP

Status

Simplified

VMdbWN
O

and

Ut
UtU

5-16

Control

EBus—-to-Port

(Cont)

[

EBUS

= O

Port

D DS DD DD D DD

|T R
[
T
I
T
M
O
T
R
I
|
HROYONAOAUDWNOHRFERHFEFEOLONOUID
W N -

CONTENTS

Interconnection

«esA-15

...A-16

...A-16
Diagram...A-18
*

Cable...iieeeeeeee O
X

CONTENTS (Cont)
Page

Vane

Switch

Cable.,.....

Vane

Switch

Harness

Voltage

Fan

NIA20

NIA20
MBus

Monitor

Cable.iieeeeeececsen
Power Cordececeeecees
Rear ViewW.eeeeooosoo

Cable and
in KL10-R,

NIA20

De-skew

Timing.

External

Sync

De-skew

Timing.

EBUS

MBOX

H7420

[3EY QA—'21
[J

CLK

in KL10-R, Front View...oeeeosoe
Cable Interboard Connection, Top

NIA20
MTR

.A-20

Installation.....

View.

(CHTO

SUPPlYy.ieeeeeeeeecoeacnsosoosances

NIA20

Card

Cage

NIA20

Card

Cage

NIA20

Current

VieWS.eeeeoooooonns

in KL10-R.....
Limiter, Cutaway

..B-3
.B-10

.B-12
.B-13

.B-14
.B-15

.B-16
View.....

NIA20 Harness and Cable Interconnection
DC Power Cable.eiieeeeesececocoeas

Vane

Switch

JA-22
A-23
«B=2

and

CLK.......Q.........’l......‘......

POWer

Cable..eeeececeocoesan

Diagram

*®

.B-21

.B-22

Vane Switch Harness Installation.
DC Voltage Monitor Cable.......
Fan AC Cable and Power Cord...
L4

.B-17
.B-20

.B-23

.B-24

TABLES

No.

Title
AssignmentS.ceeseese
3

Bit

[]

Descriptions.

Error Log @and TYPCeeseeecececccscoscsossaes
Transmission Failure Bit Mask Assignments

Reception
Command

Code

Control

Bit

Possible

Failure

Bit

Values

and

List,
in

KLlO E

Harness

NIAZO

KLlO E

wlre

KL10

Function

CSR

Bit

KL1O0-E..veeeeoooocosaes
and

Cable

Status Register Bit
Description......

Definitions.

Functions....

Control

Connectlons.

Adds...................

Word....

Descriptione..eeceeces.

SignNalsS.eeeeeeececsecoscoacconeecss
Link Control SignalS..cececsses
Transmit Action Command Group....
Write Address Register Access Table....
*

*»

PLI

Cyclesot.i.....0...'0....

CBuS

NIA20

Diagnostic

IOP

FunctionNnS...eeee.

B DB

Parts
NIA20

Control and
EBus Signal

Assignments...

FunctionS.......

ConditionNnS.eeeeeeeeceonces

Error

Mask

and

I
O

Word

Error

H4000

DB WWWNNNNDDNNDDDNDND
-

HOOJAA UM WNHFWNFEJAOUTD
WN -

Table

.4-23

CONTENTS

(Cont)

W N

EflUJWED?JPU’P(fl
i

= O

oo
ono oo

i
OO
U D W

Page

CSR

Bit

EBUS

DescCriptioN.ceececcescscccsscscscsssocscsscsssd—3

FUNCLIONS .t eeeeesososscscsssosscsenossccsssssesed—ld

I0P

Function

ALU

Control

Decoder

Control

Word

Bit

Description.........5-16

CommandS.ceeceesesescscsccscssossscosssed—24

Output

SignNalS.eececececcscsoscsosssesasessesd—28

Mover/Formatter Control CommandSeeceeececooccesscscsesd—30
Condition Code DefinitionS.ceceecseccscssossccsccesd—il2
Microsequencer InNStruCtionNS.cieecececesescesccsseead—4lb
Microword Field DefinitionS.ceeeeececescscescsssseed=5l
Skip/Condition Function..eeeeceseosscssecoscscseseesd—64
Cache Base AdAresSSeS.ceeseeccccssssssscssscccsocsessd=b67
Local Store Address Register Command Status
Block OffSetS.eeceeancescescsccoccscascsssoscssancsceesd—68
Command Queue Status Block Flag Word....eeeeeceseed=69
NIA20 in KL10-D Parts List...seeececcccoscscscscssssA—4
NIA20 in KL10-D, Harness and Cable Connections.....A-5
NIA20 in KL10-D Wire AddS..:.veececescscsssscssscccsA=8
NIA20 in KL10-R, Parts LiSt.cecccececcccscssssccsesesB—4
NIA20 in KL10-R, Harness and Cable Connections.....B-5
MBus Cable Interboard Connection, Top View..eeoe...B-10
NIA20 De-skew Timing. External Sync (CHTO H)......B-12
NIA20 De-skew Timing. EBUS CLK L and
MTR

MBOX

H7420
NIA20
NIA20
NIA20
NIA20
DC

CLK.:teeoeeeeoossososocsoscscosscsssoscosesnsebB—1l3

POWEY SUPPlYeeeeecscoscscscescssssscssascsesB—1ld
Card Cage VieWS..eeoeesssesssoscscsssosssseeB—lb
Card Cage in KL1O0-R..ceeessoosscessossscassasB=1l6b
Current Limiter, Cutaway View...eeeoeseseeseB=17
Harness and Cable Interconnection Diagram...B-20

Power

Cable.icieeeceseeseceeosscssscscssossossseseaB—2l

Vane Switch Cable.siveeeesseescesoscsscscsccsscnsesB=22
Vane Switch Harness InstallationN.eeceeecoccscceeseB=23
DC Voltage Monitor Cable..ciseeecesccsccccscnsaesseB=24
Fan

Cable

and

Power

COrQ..ceeeocecsccososssscssseB—25

xii

PREFACE

This
of

reference
the

manual

Network

provides

Interconnect

technically

Adapter

oriented

(NIA20).

This

description
description

includes
detail
on
implementation
and
installation,
as
well
as
functional
and
logic
characteristics.
The
NIA20
is
required
by
Digital
Equipment
Corporation
field
service,
manufacturing,
engineering, software, and operational personnel.
This
as

manual

outlined

contains
in

the

preface,

Table

five

Contents.

xiii

chapters,

and

two

appendices

CHAPTER

INTRODUCTION

The

network

architecture
coaxlal

(NI),

Equipment

Digital

used

transmit

serial

area

local

processing

equipment

within

complex

buildings)

through

channels.

Extensive

the NI
as
the
communications
The

has

allows

server

several

wiring

network

Also,

and

power

element

Corporation,

the

uses

network

complex

not

link

high-speed

configurations

simply

failure

over

and

are

the

added

There

connected

other

into

can

possible
to

systems

to
on

the
the

This

cable

wherever

removed

centralized

using

corporate

1link.
or

communications

interconnects.

point-to-point

Nodes

information

building

processor

other

tapping

operation.

advantages

its

All

(limited

products.

then

among

(LAN)

area

reliable,

needed.

system

datagrams

network

communications

nodes

major

interprocessor

network,

during

and

primary

multiple-access
computing

single
between stations
(or
form of the datagrams
(also called frames or packets)
in the Ethernet specification.

cable

nodes). The
is dictated
The

interconnect

should

design

the

from

control.

not

affect

NI.

NI
must
conform
to
the
same
Ethernet
rules
transfers
and
arbitration.
Digital
Equipment
integrated
Ethernet
into
the
Digital
Network
Architecture
(DNA)
in
its DECnet products,
all
of which conform
closely
to
the
International
Standards
Organization
(ISO)
model
for Open Systems Interconnection. Ethernet is a specification for
governing
data
Corporation
has

the

physical

provides
common

implementation

high-speed

bus,

with

of
1local
area
communications.
It
communications
(10 megabits per second)
and a

all

nodes

communicating

peers

using

standard

link-level
protocol
=-Carrier
Collision Detection (CSMA/CD).

Sense

The

efficient.
It
1is
a
is free to communicate
provided two
simple
rules are

CSMA/CD
protocol
first-come/first-served

with any
followed.

other

node

node.can

talking.

Once

the

starts
stop

and

Ethernet

any

start

Ethernet

talking

and

try

wait

simple

system.

at
a

Each

time,

Multiple

Access

and

node

talking while another node
cable

exactly

short,

with

idle,
the

than

still

one

node

same

instant,
each
must
randomly-determined time interval

again.

technology

allows cable segments up to 500 meters
(1650
long. Through the use of repeaters, multiple segments can be
connected, with up to 100 nodes each and connections separated by
at
least 2.5 meters
(8.25 feet).
LANs can be constructed with as
feet)

1-1

but two nodes cannot be separated by more than

many as 1024 nodes,
two

repeaters.

The maximum length of coaxial cable between any two nodes is 1500

meters
(4950 feet), and the maximum length of the transceiver
cable (between a transceiver and the controller) is 50 meters (165
feet).

A maximum of 1000 meters (3300 feet) of point-to-point 1link is
allowed for extending the network. One possible example would be
high-speed,
a
using
segments,
Ethernet
two
connect
to
point-to-point

fiberoptic

link.

The 2800-meter (9240 feet) maximum end-to-end length of the LAN
between any two nodes is the sum of three 500-meter (1650 foot)
coaxial cable segments, plus six 50-meter (165 foot) transceiver
cables, plus 1000 meters (3300 feet) of point-to-point link.
1-1

shows

large-scale

configured

Ethernet LAN.

TRANSCEIVER CABLE

NODE

TRANSCEIVER

SEGMENT 1EP—

F—1

]SEGMENT 2

ereares

SEGMENT 3

t—

]

COAXIAL

}

CABLE

REMOTE

POINT-TO-POINT

REPEATER

LINK (1000 M MAX)

—{
SEGMENT 4['_'}——

[

Figure

]SEGMENT 5

]

—{]]

Figure

1-1

Large-Scale Ethernet Configuration

1-2

1.1

NIA20

The

Network

option

that

KL10

The

NIA20

the

SUBSYSTEM

OVERVIEW

Interconnect

will

high-speed

subsystem

The

port,

port

Adapter

used

serial

consists

which

consists

(NIA20)

interface
NI

the

will

reside

three

standard

EBus

Microprocessor

control

M3003

CBus

module.

port
to

interface

NIA

system

the

RH20
hex

slot

number

The

modules:

module

interface

interfaces

the

hardware/firmware

following:

M3002

and

operating

line.

M3001

The

the

module

KL10

via

the

module

via

the

port

which

extended

the

link

EBus

and

CBus,

interface

(PLI)

bus.
-

The

NIA

module,

residing
NI

card

The

in
cage

NIA

manner

the

1is

and

through

CPU

and

bay

backplane

controlled
is

KL10.

tri-board

module

housed

unit

located

the

port

master/slave

used

to
transmit and
receive data
transceiver
and
onto
the
serial NI

the

cable.

CPU

bay.

packets
coaxial

The

The
NI
cable,
which
is
a
10
megabit-per-second,
multiaccess
serial
interconnect.
It
allows
up
to
1024
different
nodes
to
<communicate
by
exchanging
data

H4000 transceiver
(and transceiver cable), which taps
into the coaxial NI cable and allows the NIA to transmit,
receive, and detect data collisions.

packets.

The

current

limiter board (and bulkhead connector), which
the
interface
between
the
NIA
and
H4000
and
current—-limits the 15 volts to the H4000.

provides

The

relationships

among

these

units

shown

graphically

Figure

1-2,

Although

listed

part

NIA20

part

not

included

the

configuration

the

LAN.

the

The

NIA20

MBus

and

PLI

cables,

cage,

and

four

modules:

and
and

logic

made

the

because

transceiver
limiting

module,

unit
(ALU)
module,
CBus-PLI interface.

the

coaxial

need

varies

cable

according

current
NIA

subsystem,

port

EBus

(and

transceiver

bulkhead

interface/port

microprocessor

cable),

connector,

card

arithmetic

control

module,

Loo7Z2

CBUS INTFC
AND

KL-10
DATA

CHAIN

DATA MOVR

NIA

MODULE

M-3003

CUR
LIM

(A21)
)

)

PORT
MICROPROC
CONTROL
MODULE
M-3002

CRAm (O Bivs MK
X

(A20)

micRoP

EBUS INTFC

AND

geceFSOR PU2

PORT ALU

KL-10

MODULE

EBOX

M-3001

‘

(A19)

DRoF
TRANSCEIVER CABLE

XCEIVER

H 4000

XCEIVER

444 oo

4006

——
NI

NI NODE

NI NODE
MR-13651

Figure

Three

Block Diagram

modules
(EBus
1interface/port
ALU,
and
CBus-PLI
interface)
make
up
the
control,

these

microprocessor

Simplified NIA20

1-2

four

port
port.

The port is responsible for implementation of the data link and
port
1layers
of
the
Systems
Communications
Architecture
(SCA)
protocol. The port is responsible for all data transfers, between
KL10 memory and the NIA module. The port gets its instructions
from queued I/0 structures in KL10 memory, and makes the transfers
through

the

use of

command/response queues.

l1.1.1
The NIA
bus and

Network Interconnect Adapter Module
module acts as the link and buffer between the KL10
the NI transceiver cable (between port and NI Wire).

Ethernet

port

PLI
The
NIA module contains a transmit buffer (2K X 10 bits), a receive
buffer (16K X 10 bits) and a permanently stored ROM containing the
address.

As the NIA module receives a packet/frame from the NI wire,
receive buffers are loaded and organized via the use of free
used buffer lists. The buffers are read by the port modules
data

sent

to KL10

memory via

the

CBus.

the
and
and

The

transmit

the

entire

transmit.
buffer as

- COJO
N D WN -

w N

has

loaded

been

When the NIA
it transmits

reception,

the

CRC

NIA

the

loaded,

is free to
the frame.

performs

generation

Transmission

the

and

deferral

frame

data.

commands

the

When

NIA

9
*

L]
[2
[

transmit, it reads the transmit
In addition to transmission and

following

functions:

when

wire

busy

Port

Am2901

based

operation

the

NIA20.

The

microprocessor

port

has

memory in addition to 4K by 60 bits
sequencing is done by an Am2910.

Control

and

status

KL10

via

the

KL10

port

and

the

KL10

The

port

inserted

The

with

port

checking

port

slot

port

the

Detection of collisions during transmission
Automatic retry after collisions
Maintenance of transmit status conditions
Parallel/serial bit stream conversion
Encoding/decoding of the bit stream
Carrier sensing and data synchronization
Destination address decoding
Maintenance of receive status conditions
Buffering of incoming frames from 10 to 64
(depending
their size)
Parity generation and checking
Various internal loopback and checkout features.

1.1.2

The

buffer

frame

left

three

are

consists
into

information
EBus

three

dedicated

empty)

modules

are

the

EBus

interface/port

the

RAM

control

RAM.

Microprogram

acts

between

the

transfers

KL10

CBus

interface.

hex

36-bit

data

fine-line

RH20

slot

local

port

data

All

which

DMA

RH20-DTE20

(MBus).

module

standard

Interface/Port

ALU

low-priority

KL10

linked

the microprocessor bus
modules via this bus.

1.1.2.1

via

the

bits

passed

interface.

done

controls

and

the

between

the

etch
(slot

modules
5,

with

backplane.
tristate

data

passed

ALU

Module

low-speed

(M3001)

path

called

among

the

port

The

EBus

asynchronous

control

interface between
the KL10 EBOX and the port. It performs all of
the functions required for passing data between the EBus and the
microprocessor.
It
also
contains
a
36-bit
control
and
status
register,
which
enables
the
port
to
control
and
monitor
EBus
operations. Most of the port protocol is processed over the EBus

through

this

interface.

addition,

ALU

consists

four

Am2902

this
of

module

nine

high-speed

multiplexer

the

pass

ALU.

is also
preassigned

1.1.2.2

houses

Am2901

the

bit

port

slice

1look-ahead

microprocessor

ICs

(36-bit

carry

data

generators.

ALU.

The

path)

and

constant

included, which allows the port microprocessor
constants from the control store RAM (CRAM) to

Port Microprocessor

Control

Module

(M3002)
-- The port

microprocessor consists of a bit slice microprocessor controller,
which controls the CBus/mover and the EBus/port ALU interfaces. It
performs such functions as data mapping, NI packet interpretation,

and
some
packet
buffer
manipulations.
It
contains
a
2910
type
microsequencer, a CRAM 4K deep by 60 bits wide, a scratch pad RAM
1K
deep
by
36
bits
wide,
a
CRAM
control
register,
and
other

associated control logic.
Once

the

CRAM

port

entirely

from

the

each

clock

1is

CRAM

[

1loaded
under

into

and

the

control

the

CRAM

———

microprocessor

the

that

control

microwords

started,
are

the

strobed

the

beginning

=--

The

cycle.

1.1.2.3

CBus~PLI

1Interface

Module

(M3003)

CBus-PLI

interface
module
acts
as
a
high-speed
synchronous
DMA
data
transfer path and data formatter between the packet buffer and the
KL10 CBus channel. This module employs a 4-bit parallel by 12-bit

serial
mapping

shift register
between
8-bit

contains
among
In

necessary

shift

addition,

(MBus)

the

module

the

port

read/write

microprocessor

and

transfers

direct

data

control

the

between

8-bit

for
the data
formatter, which
bytes
and
36-bit words.
This

the

logic
CBus,

supports

for
and

PLI
to

path
from

and

(PLI

interface.

and

PLI

36-bit

microprocessor

data

performing
the

the

1is

data

bus)

Thus

the

CBus

for
also

transfers

interfaces.

read/write

the

used

module

between

port
the

data

formatter,

the

path
and
port

microprocessor

PLI

interfaces.

The port is controlled by a four-phase clock generator located on
the CBus/data mover module. One microcycle normally requires 270
ns (see Chapter 5, section 5.2, for details).
1.1.3
H4000 Transceiver
This section gives a brief overview of the H4000 Transceiver.
a full description on interfacing and operational theory, see

H4000 technical manual

(Digital P.N.

EK-H4000-TM-001).

The

the

basic

functions

Transmit

data

from

H4000
the

are

For
the

follows:

controller

(NIA)

onto

the

data

transmitting)

coaxial

cable

Receive

data

(including

from

cable

Detect

collision

conditions

and

1-6

notify

the

controller.

the

The

transceiver

also

has

circuitry

from
affecting
the
Ethernet
(no
affect the network adversely).
l1.1.3.1

Transmit

the
transceiver
cable. A squelch

Function

~--

The

internal
can

transmitter

megabit-per—-second
before transmitting

1.1.3.2

Timer

Watchdog

transmitter

watchdog
event of

node

problems

allowed

amplifies

data

cable
pair
and
transmits
it
onto
the
coaxial
circuit ensures that transitions on this pair are

valid
Ethernet
10
(not random noise)

the

prevent

faulty

opens

Function

(permitting

Manchester
encoded
signals
onto the coaxial cable.

When

the

data

squelch

timer circuit is enabled. This timer
a controller or transceiver runaway,

circuit

transmitted),

ensures that, in the
the transmitter will

be disabled within approximately 50 ms. This protects the Ethernet
from
being
"hung."
Digital's
H4000
watchdog
timer
is
¢triply
redundant, for enhanced protection and reliability.

1.1.3.3
Collision Presence
determines
if
more
than

Function -- A collision sense circuit
one
transceiver
1is
simultaneously
transmitting
on
the
coaxial
cable.
A
1low-pass
filter,
which
extracts the dc component of the signal on the coaxial cable,
is
used to make the collision determination.
1.1.3.4

end

Collision

each

Presence

normal

Test

transmission,

Function

the

(Heartbeat)

collision

presence

the

oscillator

is turned on for a short duration
(pause about 360 ns and on for
about 400 ns)
to test the collision presence circuit. Its absence
should
warn
the
controller
(NIA)
that
the
collision-sensing
circuitry in the H4000 may be faulty.

1.1.3.5

Receive

Function

=--

The

receiver

amplifies

the

data

received
from
the
coaxial
cable
and
retransmits
it
onto
the
receive
pair
of
the
transceiver
cable.
Squelch
1is provided
to
ensure
that
the
receiver
1is
enabled
only
when
valid
Ethernet
signals are present on the coaxial cable.
1.1.3.6

convert

the

+12

Converter

—-—-

-5.2

the

The

H4000

has

and

-10.2

dc-dc

converter

required

the

transceiver.
The
converter
also
provides
electrical
isolation
between
the
controller
and
the
transceiver
«circuits
and
the
coaxial cable, further protecting the Ethernet from node faults.

1.1.3.7

Coaxial

Cable

Connection

The

H4000

electronics

module

is custom fit into the casing, which also acts as the tap into the
coaxial
cable.
The
tap
requires
that
the
coaxial
cable
be
preconditioned by drilling two small holes
(opposite each other)
into the outer jacket and braid.
An

installation

the

necessary

H4000.

kit

parts,

(H4090-KA)

1is

tools,

instructions

and

available,

which

needed

contains

install

all
the

The tap is designed to be reusable up
that
certain
conditions
are met
(see
Installation

Procedure,

and

Appendix

to five
Chapter

times, providing
3,
section
3.4,

and Appendix

B).

l1.1.3.8
Transceiver
Cable
Connections
-The
transceiver
|is
equipped
with
a
15-pin
D
connector,
meeting
the
Ethernet
specification. The H4000 transceiver pin assignments are given in
Table

1-1.

Table

1-1

1.2

H4000

Signal

Pin Assignments

Name

Transceiver

Collision

Transmit

(reserved)

5
)

Receive +
Power Return

(reserved)
(reserved)

ETHERNET

Collision

Transmit

presence

(reserved)

Receive

Power

(reserved)

SPECIFICATION

shield

This section gives a

cable

presence

OVERVIEW

brief overview of

the

Ethernet

specification.

A full description of the data link protocol and physical details
of
the
communications
medium
can
be
found
in
the
Ethernet

specification
to

show

Data

how

manual.

the

data

This

serial

condensed

packaged
NI

and

cable

description

provided

here

handled.

must

conform

the

Ethernet

specification. The arbitration protocol used by the NI is Carrier
Sense Multiple Access with Collision Detect (CSMA/CD). The service

provided

1is

datagram

class

which

the

data

packets

are

delivered on a best-effort basis; no confirmation of delivery
made,
and
no
guarantee
of
sequentiality or
non-duplication
made.

Higher

1levels

network

software

must

provide

1is
is

these

services.

l1.2.1

Packet

Format

Packet format
1is
illustrated
contains the following:
l.
2.

Preamble - 64 bits (8
Destination address -

Fiqure

bytes)
48 bits

1-8

1-3.

bytes)

packet

(or

frame)

s
«

YU
W

Source

address

—

Type

field

Data

field

(46

Cyclic

bits

bytes

redundancy

bytes)

minimum,

check

1500 bytes maximum)
field - 32 bits (4 bytes).

(CRC)

LSB

MSB

PACKET/FRAME
DEST.

(F;‘F:EAMBLE/

—]

ADDR.

SRCE

TYPE

HELD

%ATA FIELD

(8n)

INTERFRAME

]

|4———— CRC COVERS THESE FIELDS—————.{

4+—9.6Us —p

'q———o|

MIN.

MR-13652

SPACING

Figure

Nodes

(or

coaxial

the

1-3

stations)

Ethernet

must

able

Maximum

l4-byte header

the

1.2,1.2

according

Packet

1500

destination
Minimum

Packet

Format

receive

and

transmit

format

and

spacing

the

packets

shown
in Figure 1-3. Each packet is a sequence of 8-bit bytes. The least
significant
bit
of
each
byte
(starting
with
the
preamble)
1is
transmitted
first.
The minimum packet spacing
is 9.6 wus
between
the end of one packet and the start of another.

1.2.1.1

cable

Data

Size

1526

data

bytes

4-byte

CRC).

and

source

addresses

and

Packet

Size

bytes

(8-byte
The

the

preamble

header

type

(8-byte

made

field.
preamble

l4-byte header + 46
data bytes + 4-byte CRC).
Any received bit
sequence smaller than the minimum valid packet (with minimum data
field)
is considered to be a collision fragment and is discarded.
These small collision fragments are also called runts.
1.2.1.3

Preamble

(alternating

1ls

and

This
0s

and

64-bit

ending

1in

synchronization
two

pattern

consecutive

1s).

Synchronization and stabilization occur during the preamble,
two
1ls
at
the
end
indicate
the
start
of
coded
data.
If
consecutive 0s are detected, an error must have occurred, and
receive
1link
management
component
of
the
data
link
blocks
further bits of the current £frame.

and
two
the
all

1.2.1.4

the

station(s)

Destination Address

—-- A

packet

48-bit
being

field

that

specifies

which

the

transmitted.

examines this
The first bit

field
(1 sb)

to determine if it should accept
transmitted indicates
the type of

Each

the packet.
address:

If the least significant bit (LSB)
is a 0, the field
the unique address of the one destination station.

1-9

station

contains

the

LSB

the

field

specifies

logical

group

recipients.
A

special

all

1.2.1.5

case

1.2.1.6

station

Type

Field

higher

field

determines

1.2.1.7

Data

stations)

will

1.2.1.8

This

48-bit

field

transmitting

address,

16-bit

field

how

the

data

field

This

field

contains

associated

1500.

distinguishable

which

Packet

Check

Sequence

used

with

unique

identify

the

packet.

integral

minimum

ensures

collision

the

packet.
the

This

interpreted.

(The
from

contains

the

protocol

from

—--

that

1level

Field

ranging

packets

Address

the

type

bytes

(all

1s.
Source

address

broadcast

This

number
that

valid

fragments.)

32-bit

field

contains

cyclic
redundancy
check
(CRC)
code.
The CRC
checks
the
address
(destination
and
source),
type,
and
data
fields.
A
simplified
explanation
is
to
have
both
the
transmitter
and
receiver
(using
the

same

covered

algorithm)

data.

The

calculate

transmitter

32-bit

sends

the CRC it calculated with the CRC it
match; if not, an error has occurred.
1.2.1.9

round

Round-Trip

trip

l1.2.2
The

delay

for

Control

control

packets

establish

fair

transmitting
same

The

51.2

bit

CRC.

The

received.

maximum

The

2800

two

meter

the

composes

CRCs

must

end-to-end,

us.

determine

how

to
the
common
resolution
of

and

when

host

station

cable.
The
main
purpose
occasional
contention

stations.

If multiple stations attempt
(transmission overlap), the result is

time

based

receiver

Procedures

procedures

transmit

the

Delay

polynomial,

its

may

is
to
among

transmit

collision.

NOTE

Only transmitting stations can recognize
a collision. Normal transmissions have an
ac

component

when

two

same

time,

the

1.2.2.1

Defer

cable

when

within

the

(9.6 us).

the

level

normal

collision

minimum

that

level,

transmit

component

but

the

varies

about

approximately

twice

1level.

This

activates

the

signal.

station

(message

packet

stations

detect

carrier

varying

must

from

spacing

not

transmit

another

time

station)

after

the

carrier

coaxial

present

has

ended

1.2.2,2

Transmit

deferring.

may

reached

1.2.2.3

must

transmitted
also

its

1is

the

transmission

that

arbitrary

all

other

participants

After

and

then

not

frame

detected.
detected,

interval

end

bytes

usual,

time

the

(4-6

must

random

transmit

until

jam

may

transmit

collision

aborted,

defer

occurrence.

Retransmit

has

station

and

ensure

recognize

l1.2.2.4
and

stop

collision

Abort

packet

continue

wait

station
for

attempt

computed

has

the

data)

collision

retransmission

retransmit

using

the

detected

random

delay,

the

packet.
The
algorithm given

backoff

in Section 1.2.2.5. After 16 transmission attempts, a higher
1level
(such
as
software)
decision
is
made
to
determine
whether
to
continue or abandon the effort.

l1.2.2.5

Backoff

—--

truncated

binary

exponential

resolving

contention

station
each

has

station

window).

slot
time
stations
a

fails,

fairly

10-bit
looks

the

bit

the

2-bit

computed
with

the

aim

many

bit

its

transmit.

generator

the

bit

1look

window)

using

the

as 1024 stations.
Each
generator. After a collision,

number

first

are

algorithm,

and
transmit.
This
gives
chance
of
success.
If
the

stations

delays

backoff

among

random

(51.2
usec)
50
percent

both

generators

Retransmission

the

and

wait

first
the

two

wait

one

two
contending
second
attempt

bits

indicated

one-bit

number

their
of

slot

times
(0,1,2, or 3),
thereby reducing the chance of collision to
25 percent. This procedure continues until each station is
looking

all

bits.

retransmission

number,

representing

1.2.3

Manchester

Manchester
percent

Since

encoding

duty

the

attempts

cycle

maximum

some

random

through

random

number

use

the

between

number

1023

(10

entire

and

bits),
10-bit

1023.

Encoding
is

and

used

ensures

the

coaxial

transition

cable.

the

middle

has
of

bit
cell
(data
transition).
The
first
half
of
the
bit
contains
the
complement
of
the
bit
wvalue,
and
the
second
contains

per

the

second

true

100

value

per

BIT CELL

the

bit

cell

bit.

The

(see

data

Figure

rate

1-4).

,
HIGH=0 v

—_
|<—1 00 ns —DI

———

low=—205v
MR-13653

Figure

1-4

Manchester

Encoding

every

cell
half

megabits

1.2.4
The

Carrier

presence

present.

times
has

Carrier
either

1.2.5
Up to

since

been

last

the

1is

not

the
the

derived
detect

any

that

between

bit
a

cell,

carrier

sense

1.25

bit

0.75

and

then

carrier

sense

packet).

data

collision

transitions

detect

Transceiver Connections
transceivers may be connected

has

network

attached

built-in

while

only

manufacturer,

detected

circuitry

within

on
the

the

2.5

meter

which

remains

special

points

devices

taps

the

general

rule,

shielded

cable

host with

the

Shield
Power

provide
and

they

depend

have

signals

taps

must

the

cable

manufacturers.

They

the

coaxial

and,

interface

the

(minimum

connection

connection
Transmit pair connection
Receive pair connection

pair
pins

connector.

pair

Collision
Remaining

The

marked

into

interface

15-pin

following

operation.

intervals.

have

that

to the coaxial cable. Each
can be attached or removed

tap,

1.2.6
Transceivers
Individual transceiver
a

last

end

from
or

indicates
seen

ns.

100
a

receive

transceiver
from

center

(indicating

sense

160

transitions

transition

lost

the

Sense
data

connection
are reserved.

their

host

cable,
system

via

Transceivers

provide

the

standard

unit):

type

CHAPTER

IMPLEMENTATION

This

chapter

implementation

deals

with

the

wvarious

large

elements
computer

involved

group

(LCG)

the

systems.

The

NIA20 uses a queued I/0 structure with the NIA20 handling the
actual I/0 between the NI and KL10 memory. This structure involves
concepts and protocols new to LCG systems.
2.1

IMPLEMENTATION

There

are

two

(port

driver)

first,

the

OVERVIEW

mechanisms

and

port

the

used

NIA20

command

and

communication

port

(port

status

between

the

microprocessor).

(CSR)

can

KL10

the

read

and

written by the KL10 over the EBus. The port can also use the EBus
to
read and write KL10 memory.
In the second method,
the queued
protocol is used for both port control and data transfer. The CBus
is the data path to and from KL10 memory when the
is used.
The EBus is used for control and status
interrupts when using queued protocol.
In

the

doubly

queued

response

command
queue

protocol,

linked

dqueue,

queue,

and

command

the

and

the

KL10

1links

port

them.

queue

the

tail,

response

queue

its

head.

used

the

port

mechanisms.

The

use

queues

transfer

KL10

removes

The

response

Other

port

The

processes

NIA20

queue

port

and

The

free

Figure
link
queue.

the

commands

from

tail

queues

When

are

When

used

either

queue,

entry

queue

the

gets

the

has

the

head

the

responses

the

KL10

removes

entries

from

the

data

the

type

the

KL10

implement

queues

the

entry

been

depends

are up to 16
one unknown

gueue

KL10

from

processed

the
by

the KL10,
the entry
1is put back
into
the
free
total number of queue entries remains fixed.

needs

protocol
protocol

queue.

RESERVED FOR SOFTWARE
QUEUE DATA

MR-13654

Queue

2-1

Entry

either

BLINK

2-1

entries

Format

free

(see

entry

appropriate

FLINK

Fiqure

command

repositories

port

from

put

links

these

the

are

queue.
The
1locations
of
the
protocol-dependent
discussed in sections 2.2 and 2.3.1.

2-1).

instructions

Responses
to

of protocol used to assemble the data. There
type
free dqueues
(if
all
are
enabled)
and
type
free
queues are

its

commands

the

takes

memory.

queued protocol
information and

the

port

Thus,

free
or
the

Sometimes,

the

term

process

used

when

explaining

operations

queues or commands. This convention will apply when the operations
are the same, whether the CPU or the port performs themn.
2.2
The

QUEUE STRUCTURE
queues used by the NIA20

and

responses.

used by both
microcode.
Text

data

The

the

queues

port

out,

from

command

portion

port

the

port

response

dqueue

appended

data.

2.2.1

Queue

are doubly

reside

driver

the

port

command

driver,

entries.

linked

KL10

software

the

port,

appears

entries.

Text

data

appears
Status

after

the

information

KL10

and

in,

response
may

commands

memory

driver
queue

lists

physical

and are
the port

after

the

from

the

portion

may

not

have

Linkage

Each queue entry contains two pointers (see Figure 2-2). One, the
forward
1link
(flink)
points
to
the next queue entry.
The other,

the
its

backward
flink).

entry,

link
Both

never

(blink)
pointers

points

to the
point

actually

previous queue entry (to
to the flink of the next

blink.

QUEUE
PCB

QUEUE
ENTRY

Q1 FLINK

FLINK

Q1 BLINK

BLINK

QUEUE

DATA

OTHER
DATA

QUEUE
ENTRY
QN FLINK

Lfi

QN BLINK

QUEUE
ENTRY

FLINK

BLINK

OTHER
DATA

FLINK
L

BLINK

QUEUE

DATA

MR-13655

Figure

Any

entry

using

one

the

both

2-2

queue

can

these

Queue

Linkage

accessed

pointers.

from

The

any

other

pointers

from entry to entry until the desired queue entry
can be done in either direction from the original
either

the

flinks

the

blinks

through

the

are

entry

followed

is found. This
entry by using

queue.

The

queues

all originate in the port control block
(PCB). Both the
and the port gain access to queues through the PCB. The PCB,
located in KL10 physical memory,
is used to control access to the

KL10

queues

The

PCB

queue

and

entries

entry.

queue.

time,

each

queue.

entry,

the

interlock
If

the

-1

PCB

queue

parameters.

not

information

entries

KL10

there

1link

device

are

queue

have

field

the
in

headers

same

the

(see

1s).

format

PCB

entries

section

and

the

NIA20

interlock

entry

performing

from

word

the

accessing

the

queue

operation

available,
When

the

interlock

attempting

for

2.3.1).

queue

remove
first

associated

must

word

gain

PCB

word.

queue

(all

each
is

queue

Interlocks

the

same

certain

for

Queue

prevent

There

The

2.2.2
To

set

dqueue

obtain

set

queue,

access

the

with
the

value

of
the

interlock word must be incremented and tested for a value of 0.
If
the
value
after
incrementing
is
0,
the
interlock
has
been
obtained and the requesting process can manipulate the queue.
If
the word is positive, the queue is interlocked by another process
and

access

The

interlock

There

prohibited.

processes

only

hardware

that

1ignore

"good

the

processes

manipulate

the

lost,

the

would

and

results

will"

interlock

condition

queue

access

control

prevent

queue

the

same

mechanism.
access

interlock.

time,

linkage

two

could

unpredictable.

The

queue
should
be
interlocked
only
for
the
time
required
to
insert or remove an entry. When the process manipulating the queue
is
complete,
with
the
insertion
or
removal,
it must
leave
the
interlock word with a value of -1.

2.2.3
The

Queue

PCB

Locations

used

memory

and

NIA20

(port)

must

address

the

PCB

Before

the

NIA20

channel

jump
the

word

channel
word 24

port‘driver
to

PCB

must

command

with

must

word

specify

the

certain

queues

initial

be
told,
by
is located.

transfer

setting
up a
starting with

The

anchor

provide

the

initialized,

the

port

base
address of
command word
(CCW)
octal of the PCB.

also

build,

octal

PCB.

starting

point

parameters

the

known

The

where

the

base

driver

must

set

the

the port by
three words

octal

the

EPT,

contents

the

CCW

three-word

forward

data

transfer

word

octal

host

driver,

address

the
port.

the
PCB
to
to transfer

word

the

and

PCB.

halt

At initialization, the port will start the channel with a CBus
Start, which reads the contents of these locations. This provides
the port with the base address of the PCB and two words not
currently defined,

but

reserved

Figure

the

format

2-3

shows

for

future

the

PCB

use.

appears

KL10O

memory.

OCTAL
O

COMMAND QUEUE INTERLOCK

COMMAND QUEUE FLINK

COMMAND QUEUE BLINK

RESERVED FOR SOFTWARE

RESPONSE QUEUE FLINK

RESPONSE QUEUE BLINK

RESPONSE QUEUE INTERLOCK

RESERVED FOR SOFTWARE

UNKNOWN PROTOCOL TYPE FREE QUEUE INTERLOCK

UNKNOWN PROTOCOL TYPE FREE QUEUE FLINK

UNKNOWN PROTOCOL TYPE FREE QUEUE BLINK

UNKNOWN PROTOCOL QUEUE ENTRY LENGTH

RESERVED FOR SOFTWARE

PROTOCOL TYPE TABLE STARTING ADDRESS

MULTI-CAST ADDRESS TABLE STARTING ADDRESS

RESERVED FOR SOFTWARE

ERROR LOGOUT O

ERROR LOGOUT 1

EPT CHANNEL LOGOUT WORD 1 ADDRESS

EPT CHANNEL LOGOUT WORD 1 CONTENTS

PCB BASE ADDRESS

PIA ASSIGNMENT

RESERVED TO PORT

CHANNEL COMMAND WORD

READ COUNTERS DATA BUFFER STARTING ADDRESS

30
MR-13656

Figure

KL10

2-3

Memory PCB

Format

Word 22 of the PCB is written by the port during initialization
time with the address of the EPT channel logout word 1, which the
port gets from the port driver software. Words 22 and 23 of the
PCB

are

used

the

port during

channel

error

recovery.

Word 23 contains the
any kind of channel
direct memory access
shown in Figure 2-4,

channel logout word 1 written by the port on
error detected during or immediately after a
(DMA) transfer. The format of error word 3 is’
and Table 2-1 provides bit descriptions.

Word

PCB

PCB;

octal

the NIA20

the

has no

the

address

other way of

finding

the

first word of

PCB.

the

00 01

02 03 04 05 06 07 08 09 10 11

12 13

14 15

T
1

]

LXE

SHOR

{

LONG

OVER

RUN

Figure

Table

Bits

Name

MEM

—-ADR

-WC=0

NXM

LXE

Error

Memory

Not

Channel
did

Port

Overrun

octal

CCW-style

word

the

CBus.

Word

should

jump
RH20
is

3233

34 35

]

CURR

CCWH1
i

Bit

Descriptions

Format

always

write

parity

error

count
to

did

nonexistent

aborts

after
next

still

device

slot

reserved

this

has

read,

were

device

the

when

channel

memory

port

transfer,

transferred

port

term

transfer.

but

word

count

reached

port

into

transfer

but

port

write,

the

when

driver

for

port

location

specified

sent

port

were

CCW,

data

but

channel

requested

data

but

empty

where

the

port

writes

wishes

is
appropriate

(slot

data

full

buffers

for

EBus

not

EPT

Channel

the

The

word

error

completes

reserved

over

backplane

never

Word

detected

not

the

22 23 24 25 26 27 28 29 30 31

ref

channel

word

buffers

KL10

Word

store

Error

Short

channel

Error

address

CCW

parity

Channel

Long

Word

Description

Channel

2-4

2-1

‘

20 21

wcC

NXM

18 19

DD B

ADR

—ADR

MEM | —WC

16 17

to transfer data over
responsible
for
writing
a
EPT

where

location

the

corresponding

NIA20

microcode

use.

The

depend

its

value.

installed.
port

driver

Word 30 of the PCB
counter data buffer.
software

When

the

is a pointer to the beginning of the read
This address is supplied by the port driver

initialization.

NIA20

being

initialized,

the

port

driver

must

set

the channel to transfer the contents of the PCB to the port. This
is done by setting up a CCW to transfer three words starting with
word 24 of the PCB, from KL10 memory to the channel. The port will
start the channel and read the contents of these locations. This
setup provides the port with the base of the PCB, and its physical
interrupt

assignment

(PIA).

Since the port will be using the channel to transfer large blocks
1logout
writing
be
will
1logic
control
channel
the
data,
of
that
error
An
(EPT).
table
process
executive
the
into
information
the channel discovers will be reported in the usual manner via the

EPT. Normal operation of the port will generate many long word
count errors, due to incoming frames of indeterminate size. These
errors

may

ignored.

Command queue and response queue locations are obtained directly
from the PCB. Use of the protocol type table (PTT), (see Figure
2-5), multicast address table (MCAT) (see Figure 2-6), and unknown
protocol type free queue is less direct. Received datagrams will
be node address filtered prior to entry into the NIA receive
buffer. The buffered datagrams will be multicast filtered, 1if
their destination address is a multicast address. Protocol type
filtering determines which queue to use for handling the frame.

ENABLE

<16-31>

FREEQ O QUEUE HEADER ADDRESS

RESERVED FOR SOFTWARE

R EEPELIED 15>

PROTOCOL TYPE VALUE O

MBZ

<16-31>

FREEQ 1 QUELE HEADER ADDRESS

RESERVED FOR SOFTWARE

D P— 15>

PROTOCOL TYPE VALUE 1

MBZ

[J
[]

ENABLE

<16-31>

L ETTTT N 16>

PROTOCOL TYPE VALUE N

MBZ

M-2

FREEQ N QUEUE HEADER ADDRESS

M-1

RESERVED FOR SOFTWARE

M
MR-13658

Figure

2-5

Protocol

2—-6

Type Table

Format

........... DI

<32:34><35>

MULTI-CAST ADDRESS 0, WORD 0

MBZ

MULTI-CAST ADDRESS 0, WORD 1

MBZ

MULTICAST ADDRESS 1, WORD 0O

ENA

MBz

MULTICAST ADDRESS 1, WORD 1

MBZ

MULTICAST ADDRESS 2, WORD 0

ENA

MBz

MULTICAST ADDRESS 2, WORD 1

MBZ

MULTICAST ADDRESS 3, WORD 0

ENA

MBZ

MULTICAST ADDRESS 3, WORD 1

MBZ

MULTICAST ADDRESS 4, WORD 0

ENA

MBZ

MULTICAST ADDRESS 4, WORD 1

MBZ

ENA

[4
o

MULTICAST ADDRESS N-1, WORD 0

MBz

MULTICAST ADDRESS N-1, WORD 1

MB2Z

MULTICAST ADDRESS N, WORD 0O

ENA

MBZ

MULTICAST ADDRESS N, WORD 1

MBZ

ENA

w1 3650

Figure

All

received

following

2-6

Multicast

datagrams

manner:

the

must

Address

pass

destination

Table

address

Format

filtering

-1

(all

1in

1s),

the

is
a
broadcast message
and
the port
accepts
it.
If the destination
address has bit 47 a 0, it is a specific physical address.
If this
specific
physical
address
matches
the
port
address,
the
port
accepts

it.

protocol

type.

Protocol

type

received,

the

table

enabled

address
table,

for
the

filtering

the

entry

queue

anchored

the

The

address

multicast

follows:

checked

The

table.

from

datagram

types.

pointer

the

used

match

unknown

When

the

PCB
a

match
get
not

address

address.
is

checked

addresses.

has

Further
by

The

the

PCB

2-7

bit
port

has

the

for

datagram

1is

against

the

has

the

found

starting
in

this

the

queue entry to
found, the required

protocol

address

filtered

port

PCB.

destination

multicast

type

datagram.
the

accepted

occurs

protocol

obtained

datagram

follows:
enabled

received

the

type

protocol

associated

store

ls)

cases,

protocol

queue

both

type

(and

filtering

against
starting

free

the

list

not

all

occurs

table

address

for

the MCAT. If a match is found, protocol type filtering occurs. If
no match is found, the datagram was not intended for this port and
is

discarded.

Both the PTT and MCAT have an enable bit. The bit must be set for

the entry to be considered valid. Both tables are arranged 1in
ascending order and both tables are allocated beginning on a
four-word block. The tables are cached within the port when the
appropriate command

issued.

QUEUE HANDLING

2.3

The port driver and the port modify the queue with the port driver
putting commands on the command queue and the port removing and
processing the commands. The port puts responses to commands on
the response queue and the port driver of the KL10 removes the
responses.

When the port driver needs a queue entry, it removes the entry
from the appropriate free queue. It builds a command and links the
command

a command dqueue.

The port removes commands from the head of the command queue and
processes them. After processing, the queue entry containing the
command is either linked to the response queue or back to the free
queue.

2.3.1

Queue Headers

The PCB contains queue headers to anchor the command queue, the
response queue, and the unknown protocol type free queue. The PCB
also contains base pointers to the MCAT and the PTT.

Queue headers anchor a queue structure. A dqueue header may be
located in the PCB or in the host memory as a free-standing queue
structure (used by the PTT as the header for the different type
queues). Queue headers are made up of a queue interlock word,
queue flink, queue blink, and a queue length word as shown 1in
Figure

2-7,.

QUEUE INTERLOCK WORD
QUEUE FLINK
QUEUE BLINK

QUEUE ENTRY LENGTH
MA-13660

Figure

2-7

Queue Header Format

The

queue

entry

entries

interlock

entries

and

The

example
a

specifies

the

queue.

operation

obtained

and

length

for

shown

freestanding

code

words

queue

are

Figqure

2-8

queue

the

This

length,

words,

includes

the

flink,

blink,

addition

the

uses

same

both

the

PCB

QUEUE
ENTRY

QUEUE

Q1 FLINK

FLINK

BLINK

QUEUE 7
{ DATA
I

/7 QUEUE /
[ DATA
1

QUEUE

QUEVUE

}—

l&—

J OTHER

DATA

data.

PCB

queue

All

headers

ENTRY

INTERLOCK

the

length.

header.

Q1 BUNK

the

{

ENTRY

Qn FLINK

+———3»

FLINK

Qn BLINK

}—

BLINK

ja—]

Qan

INTERLOCK

’

otwer

{

/7
1

QUEUE /
DATA
I

/7
{

QUEUE /
DATA
]

)

DATA

]

MR-13661

Figure

2-8

Use

Queue

Headers

2.3.2

Entry Linking
an entry to the tail of a queue,
the interlock word for
the queue must be obtained. Then the process uses the blink
word
of the PCB to find the tail of the queue.

link

The

flink

the

entry

entry.

The

blink

entry.

The

flink

the

PCB

entry

point

When

the

release
An

the
new

the

empty

Figure

queue

2-9,

tail
is

also

changed
changed

entry

the

queue.

The

blink

tail

entry.
to

the

entry

queue

the

the
PCB

new

for

old

the

linked

interlock

specified

set

header

to
at

point

the

queue,

setting

its

to
to

new

the

entry

process

the

new

the

new

flink

set

must

then

-1.
address

shown

— FLINK

(POINTING TO ITSELF)

— BLINK

H+1:

MR-13787

Figure

gqueue

entry

address

is as shown

2-9

Queue

Empty

inserted

into

empty

queue,

the

in Figure 2-10.

= FLINK

— BLINK

H+1:

00
A

— FLUINK

Atl:

— BLINK
MR-13788

Figure

2-10

Queue

with

Entry at Address A

If an entry at address B is inserted at the tail of the queue, the
queue is as shown in Figure 2-11.
35

00
H:

— FLINK

H+1:

— BLINK

00
A

= FLINK

A+1:

— BLINK

00
B:

= FLINK

B+1:

— BLINK

MR-13789

Figure

2-11

Entry at Address B

the Tail

the

Queue

entry

appears

2.3.3
To

the

flink

from

flink

address

Figure

Entry

remove

obtain

The

inserted

from

the

head

interlock

word

for

the

PCB

find

the

PCB

now

pointing

second

entry

are

entry
in

the

made

the

queue,

queue.

first

the

queue

tail,

the

queue

Removal

blink
in
the
flink in the PCB.

entry

The

2-12.

equal

queue

to
is

Then

the

process

must

uses

the

entry.

The

entry.
flink

the

second

then

changed

the

entry
to

the

point

list.

has

now

been

removed

and

the

only

process

that

removed

it.

The

process

pointers
can

the

then

set

the interlock word
in the PCB to -1 so that another process
gain access to the queue. The process that removed the entry
manipulate the data areas of the entry.
00

35
H:

H+1:

—

FLINK

= BLINK

35
A

A+1:

—

FLINK

— BLINK

35
B:

= FLINK

B+1:

— BLINK

35
C:

— FLINK

C+1:

— BLINK

wR.13750

Figure

2-12

the

Entry

Address

the

Tail

the

Queue

can

In the previous example, with the queue containing entries A, B,
and C, the entry at A can be removed, giving the queue illustrated
in

Figure

2-13.

00
H:

=— FLINK

H+1:

- BLINK

00
B:

— FLINK

B+1:

— BLINK

00
C:

- FLINK

C+1:

— BLINK
MR-13791

Queue Containing

Figure 2-13

Entries A,

and C, Where A Can

Removed

2.3.3.1 Buffer Segment Descriptors -- A buffer segment descriptor
(BSD) is a construct that is convenient for the network software
(for example, DECnet). It is used to describe a segment of KL1O
memory and gives the software the ability to append layering or
handling data to a message without rearranging the entire message
or creating overhead by copying the datagram from buffer to
buffer.

A buffer consists of a list of physically contiguous segments of
memory. Different segments of a buffer are not assumed contiguous
and may be anywhere within the physical address space of the host.
It is assumed that different segments of a buffer are unique (that
is, they do not overlap) within a host. A buffer is described by a
list

BSDs.

Each BSD describes a single contiguous piece of a buffer. Each
four-word
a
on
allocated
block,
four-word
a
is
descriptor
boundary, and built by the driver in physical host memory. In each
of these blocks is a pointer to the next descriptor block (if
any), a pointer to the segment of the buffer so described, and a
field indicating what packing mode the segment is in. In addition,
within each block is a field giving the size of the buffer
segment,

bytes.

buffer

referenced

word

the

first

out

the

send

that

command

flags

BSD

by
in

giving
the

datagram

indicates

the

chain

command

that

BSDs

physical

BSDs.

packet,

are

address

This

when

address

the

first

called

flags

byte

use.

bit

in
the
command
format
for
a
send
datagram command,
indicates that the datagram to be sent is in immedia
te
mode,
meaning
that
the
data
to
be
transmitted
follows
the
destination
address
in
the
command
queue
entry.
The
same
flags
bit, when set, indicates the use of a BSD.

when

clear,

BSDs

are

message

the

used

datagram

network

2.3.3.2

The

BSD

(RSVD)
.

when
--

necessary

different

helpful

for

programs

messages

Buffer
the

different

different
down

the

sections
layers

Segment

Descriptor Format
specified in Figure 2-14. The packing mode field
packing mode of the buffer segment pointed to.
The

<6>

PACKING MODE

MB2Z

bit
--

values

are
0
mode

Packing

<12-35>

SEGMENT BASE ADDRESS
<12-35>

mBZ

NEXT BSD ADDRESS-

<20-------35>

mMB2Z

SEGMENT LENGTH

' RESERVED FOR USE BY SOFTWARE

MBZ

sections

modes,
with
the
associated
Industry
compatible,
and
1

mez

send

build

passing

software.

format

describes

packing
mode
=

whenever

<6>

PACKING MODE

MBZ

<12-35>

SEGMENT BASE ADDRESS

<12-35>
NEXT BSD ADDRESS

MBZ

mBZ

36>

SEGMENT LENGTH

RESERVED FOR USE BY SOFTWARE

M.R-13552

Figure

2-14

BSD

Format

Packing
Reserved

The segment base address field gives the physical address of the
buffer segment described. The buffer segment must begin on a whole
word boundary. The next BSD address points to the first word of
the next buffer segment descriptor in the chain. If the next BSD
field is 0, there is no next segment descriptor.

The

segment

length

pointed

field

gives

the

length

bytes

the

buffer

to.

It is standard use for BSDs to be built in the queue entries on
the
command
queues.
BSDs
must
be
allocated
on
a
four-word
boundary.
For
incoming
datagrams
there
is
only
BSD-type
processing.
2.4

COMMANDS

AND

RESPONSES

Communication between the port driver and the port is accomplished
by using command packets and
response packets. A command
is a
request from the port driver to the port. Placing a command on the
command queue initiates processing in the port.

A response is a packet from the port to the driver,
of an event. The event may be one of the following:
An

error

causes

occurred

while

processing

informing

command.

This

always

response.

A response to a command which had the response bit set
flags field. The port must send the driver a response
original command had the response bit set.

The

reception of an

incoming

in
if

the
the

packet from the wire.

If the response queue is empty when an entry is added by the port,
a non-vectored interrupt is sent to the host (to indicate that the

driver

empty,

look

the

processes

the

entry

the

response

will

queue).

seen

the

response

driver

queue was

not

sequentially

queue.

After processing a command, the port always checks to see if
another exists on the command queue. If not, the port goes idle.
The port wakes up again when the port driver places a command in
the command queue, and writes the command queue available bit in
the control

command

status

(CSR)

with a

indicate that a new

available.

The commands available to the
port can build eight possible
response
other
one
generate

port driver are listed below. The
responses to the commands and can
from
recieved
datagrams
for
--

Ethernet.

Send Datagram (SNDDG) causes an NI datagram to be built
and transmitted as an Ethernet packet. The command may or

may not

use buffer

segment descriptors.

2-14

The port

response

datagram

requested,
or

sent

(DGSNT).

follows

the

The

format

the

response,

the

command

<can

only

(i.e.,

if
BSD

non-BSD).

Datagram

Received

(DGRCV)

notifying
packet

the port driver
that the port
over
Ethernet.
This
response
1is

response,

has
received a
always
in
BSD

format.
Load

Protocol
Type
Table
internally
cached
by
the
protocol type table loaded
Load

Multicast

Address

(LDPTT)

causes

port.

The

the

port

and/or

counters

Clear

kept

response

the

MCAT

response

(PTTLD).

Table

(LDMCAT)

causes

be cached
internally by the port.
The port
multicast address table loaded (MCATLD).
Read

PTT

Counters

(RCCNT)

the

microcode

port

causes
to

all

the

read

event
if

the

response bit in the flags field is set. If bit 14 in the
flags
field
is set,
all
the counters are cleared.
This
command
is
a
performance
monitoring
and
diagnostic
feature.
The
port
response
1is
counters
read
and/or
cleared (CNTRC).

Write

PLI
(WRTPLI)
causes a PLI
specified control bits and data
diagnostic
feature.
The
port
interface written (PLIWRT).

write function with the
byte. This command is a
response
1is
port
1link

Read

read

PLI

(RDPLI)

causes

specified

control

bits.

PLI

function

with

the

for

this

response

command,
the
data
byte
read
This command is a diagnostic
is PLI read (PLIRD).

the

PLI

returned.

feature.

The

port

response

Read
NI
address

Station

from

Address

from

(RDNSA)

reads

built

the

station

the

NI
1link
physical
address
ROMs.
This
command also reports the state of several link mode bits.
The port response is NI station address read (NSARD).

Write

NI Station Address
(WRTNSA)
writes the NI station
into
the NI
1l1link
address RAMs.
Also
sets
the state of
several
link mode bits.
The port response is NI station
address written (NSAWRT).

Command and Responsé Formats

2.4.1
The

following

sections

describe

and

responses

that

port

2.4.1.1
KL10

Send

gets

datagram

the

Datagram
entry

putting

(SNDDG)

from

the

data

the

format

receives

and

Command

associated

into

the

2-15

the

various

commands

produces.

free

queue

send
queue

entry.

datagram,
and

The

builds

queue

the

the
entry

datagram

(SNDDG)

command.
The port de-links commands from the head of the
queue and processes them, When the send datagram command
the head of the queue it is processed by the port.

then

command
reaches

the

put

onto

the

completion

determine

command

the

should

command

build

command.
If the response bit
will build a response entry.

particular
occurred

error
The

command,

during

condition

format

packet;
non—-0
to

the

response

indicate

Section
2.4.1.2
for
values
for
the

sent

response

SNDDG

command

queue

the

particular

the

wire

BSD

from

linked

The

applies

1is

the

left

used,

words,
is off

the
for

port
this

unless

built
of

port

build

similar

status

the

send

Any

packet.
datagram

field

returned

type

failure.

error

packet.

response

queue
tail

then

available

the

data

the
the

entry

flags

bytes

right.

data in bits 0-7
is transmitted
transmitted second,
the data
in
so
on.
transmitted

this

in the flags
response bit

built,

queue

format

and

will

for

transmission

the

microcode

with

Refer

all

called

the
a

(DGSNT).

BSD

the

port

a
detailed
description
of
status
field.
The
response

format

the

entry

conditions

will

port.

send

queue

will

packet

the

allowable
datagram

set
the

that

response

response
causes

difference

value

is
If

SNDDG,

processing

always

the

queue

This
1left-to-right
from a BSD.

the

byte

are

That

entry

containing
associated
for

specifies

transmitted

reuse,

BSD

usage.

onto

the

data in bits 8-15 is
transmitted third,
norm

word,

for

first,

given

the

is,

bits 16-24 is
format
is
the

the
free

for

all

the

data

NOTE

Buffers

and

always

describe

for

buffer

text

1length

full

fields

must

bytes.

illegal

terminate

the

middle

of
a
byte.
The
result,
if
this
restriction is violated, is undefined. It
is
legal
for
a
BSD
to
terminate
in
a
half-byte, under certain conditions.
The

format

Figures

The

have

command

this

2-15

and

command

queue

entry

specified

2-16.

status

fields

non-zero

status

are

zero.

field

The

response

command

(see

DGSNT

response

datagram

command

commands

shown

for

will

bit

definitions).
The

operation

code

for

The

format

the

flags

2-17

and

2-18.,

and

response

commands

and

There

(and

send

field

are

the

responses.

two

DGRCV

for

all

formats;

one

response),

for

and

the

one

Figures

SNDDG

command

for

all

other

QUEUE FLINK

QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

<8-15>

STATUS

<16-23>

FLAGS

OPCODE

MBZ

<0-19>

<20-35>

MBZ

LENGTH
OF TEXT DATA

<16-31>

MBZ

PROTTYPE
OCOL
VALUE

FREEQ HEADER ADDRESS

HIGH ORDER DESTINATION
LOW ORDER DESTINATION
BSD BASE ADDRESS

QUEUE END

MR-136863

Figure
The

O-pack

non-BSD

When

2-15

(packing

datagrams:

the

ICRC

four-character

format)

set,

used

instead

used

transmission

design

the

receive

and

packets

When

the

not

two
to

low-order

byte

two-length
or

presented
bytes,
an

the

bytes
the

the

first,

not

data.

and

are

always

padding

When

padded,

clear,

the

data

1length
are

necessary

to the port without
error response for

bytes

does

when
for

not

with

sent

will

zeros.

text

bytes

packet.

The

enabled,

particular

such

the
1In

transmitted

actual
the

padding

command

by
appending
packet
size.

valid

within

be
the

characters.

length

number

a
be

between

the

packets

port

padded

pad

the

must

generator/checker

will

the

because

extra

occur

feature

datagrams,

fields

for

appended

four

transmitted

This

format

CRC

the

was

will

CRC.

minimum
size
the
minimum

These

that

Reserved.

has

CRC

indicate

padding)

packing

This

length

indicating

the

driver

the

port

(BSD)

datagram.

The

addition

set,

text

bytes

transmitted.

packet

the

self-directed

circuits.

reflect

including

whether

adapter

field

addition,

defines

port

less
than
the
Ethernet
bytes
with
zeros
to

prepended

(not

the
end

Format

compatible,

internally generated

transmit

pad

that
are
remaining

the

Command

field

Industry

CRC

SNDDG

packet

padding.

If a
packet
is

this bit set, and it is less than 46
a runt
(less than the minimum legal

size of 46 bytes)
packet is generated. Packets presented
larger than the maximum Ethernet packet size always cause
error and generate an error response packet.

2-17

that are
a length

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE
<0-7>

<8-15>

STATUS

<16-23>

FLAGS

MBZ

OPCODE

<0-19>

<20-35>

MBZ

LENGTH OF TEXT DATA

<16-31>

MBZ

PROTOCOL TYPE VALUE

FREEQ HEADER ADDRESS

HIGH ORDER DESTINATION
LOW ORDER DESTINATION
TEXT DATA O

TEXT DATA 1

TEXT DATA 2

TEXT DATA N-1

TEXT DATA N

QUEUE END

WR-13664

Figure

2-16

PACK

SNDDG

ICRC

PAD

Command

RSVD

Format

BSD

(Non-BSD)

RSVD

MR-13792
Figure

RSVD

RESP

RSVD

2-17

RSVD

Send

Datagram

RSVD

CLRCTR

RESP

wr13783

Figure

2-18

Non-Send

Datagram

If
the
BSD
bit
is
1,
the
datagram
is
using
the
BSD
format
described under the SNDDG command.
If the bit is 0,
the datagram
is in immediate mode; that is, the data to be transmitted follows
the destination address in the queue entries.

Bit

reserved

field

valid

set,

all

the
in

When

response

the

The

FREEQ

the
The
of

the

bit

the

header

entry

send

and

non-send

datagram.

read

counters

command.

will

cleared

after

packet

for

port

the

address

indicates

obtained

correct

free

queue.

high

low

destination

byte

packet.

this

will

Their

that,

format

words
is

the

when

02 03 04 05 06 07 08 09 10 11
v

BYTE O
[T

free

specify

described

values

build

queue

from

the

can

is
are

response

2-19.

address

Note

that
NI, and byte 5 is the
low-order
destination
is

32 33 34 35

BYTE 3
S

the

back

destination

Figure

BYTE 2

NN N

which

put

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BYTE 1

always

done,

is the first byte transmitted on
last
byte
transmitted.
Bit
31
of
the
therefore the multicast address bit.

their

This

bit

command.

00 01

this

command.

was

the

datagram

the

response

processing

queue

for

counters

reported

after

for

only

TN NN

MBZ
O

LOW

MULTICAST BIT 7

00 01
IR

)

02 03 04 05 06 07 08 09 10 11

2.4.1.2
SNDDG

BYTE 4
1

BN B

AN S

12 13

SN [

Figure

2-19

Datagram

Sent

command

built

BENN RN

BYTE 5
1

16 17 18

SN U

19 20 21

pa o

Destination

(DGSNT)
if

22 23 24 25 26 27 28 29 30 31 32 33 34 35
T

' 'MBZ
1

Address

Response
error

occurred

[

HIGH
1

Format

response
during

the

processing

the command, or 2)
the response bit of the flags field of the
original
datagram
packet
was
set.
The
format
of
the
returned
packet is shown in Figure 2-20. The format of the response follows
the
format of the original command.
Thus,
if the BSD bit of the
flags
field was on,
then
the
response
is
in BSD format as well.
Figure 2-20 shows the format for a non-BSD packet:

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

<8-15>

<16-23>

MBZ

OPCODE

FLAGS

STATUS

<0-19>

<20-35>

MBZ

LENGTH OF TEXT DATA

<16-31>

MBZ

PROTOCOL TYPE VALUE

FREEQ HEADER ADDRESS

HIGH ORDER DESTINATION

LOW ORDER DESTINATION
TEXT DATAO

TEXT DATA1

TEXT DATA 2

TEXT DATA N-1

TEXT DATA N

MR-13666

Figure

2-20

DGSNT

Response

Format

(Non-BSD)

The format of a response for a send datagram command packet
the BSD bit of the flags field set is shown in Figure 2-21,

The
to

format
the

the

individual

information given

for

words
the

and

SNDDG

the

bits

command

therein

with

conforms

format.

The status
field shown
in Figure
2-22
is used by the port to
report the status of all completed commands. This field appears in
the
response
word of
the queue
entry.
When valid,
this
field
indicates the logging of an exception event.

When the
response

CRAM PE field is set to 1, the forthcoming read counter
is due to execution of a planned CRAM parity error.

Wwhen the send/receive bit is 0, an error occurred on receive;
receive failed. When this bit is 1, an error occurred on transmit;
transmission

failed.

QUEUE FLINK

QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

<8-15>

STATUS

<16-23>

FLAGS

OPCODE

mBz

<0-19>

<20-35>

MBZ

LENGTH OF TEXT DATA

FREEQ HEADER ADDRESS

HIGH ORDER DESTINATION
LOW ORDER DESTINATION

<16-31>

MBZ

PROTOCOL TYPE VALUE

BSD BASE ADDRESS

o
| ]
[ ]

TEXT DATA N

MR-13667

Figure

2-21

CRAM
PE

DGSNT

Response

SEND/
RECEIVE

Format

(BSD)

ERROR TYPE

ERROR

MR-13794

Figure

When
be

the

zero

error

bit

(MBZ).

When

an
error
event.
The
the direction field,

The

error

field

2.4.1.3

type

set

datagram

The

operation

code

from

Queue

has

the

status

field

bit

the

status

definition

the

error

comes

effect.

into

indicates

Figure

for

error

meaning

field
type

event

fields,

being

Response

built.

The

—--

When

format

2-23.

and

must

reporting
and

logged.

The

datagram

2-2.

(DGRCV)

packet

field

the

Table

Received

response

Field

field

shown

Status

this

according

Datagram

received,

2-22

received

datagram

received

Table

2-2

Error

Event

Type

Log

and Type

Bit Value
(Octal)
00

Excessive

Carrier

Collision

03
04

Open

collisions

check

failed

detect
circuit

Short

Note
2
(carrier

check

circuit

11
12

Data overrun
Unrecognized

Frame too short
Channel error WC not equal
Queue length violation
Illegal PLI function
Unrecognized command
Buffer length violation
Reserved

Transmit buffer

30
31
32
33
34

failed

Frame too long
Remote failure to
Block check error
Framing error

06
07

lost)

Internal

defer (late
(CRC error)

(NIA

buffer

protocol

collision)

space

exhausted)

type

3
zero
5

parity error

error

NOTES:

For

transmission,

this
error
means
that
the
1length
information in the transmitted BSD was inconsistent,
such as
when
the
1length
field of
the
transmitted datagram does
not
match the total length of the BSDs to be transmitted.

When

this event is being logged, bits 26-35 of the opcode word
in
the
response
packet
of
the
queue
entry
become
the
time
domain reflectometry (TDR)
reference number obtained from the

NIA

when

the

tics,

from

error

event

error

the

was

occurred.

This

time

transmission

detected

the
by

the

NIA

indicates

the time,
in
started
until

100

the

hardware.

This

error occurs only when padding of the transmitted frame
is disabled, and the frame length is smaller than the smallest
legal Ethernet frame size of 46 data bytes (64 bytes including
all physical channel protocol). No indication is given if the
frame size would be a runt, and padding is enabled.
In that

case,

PAD

the

flag

frame

Figure

padded

noted

the

description

the

2-17.

These
errors
are
also called
late collision errors.
A late
collision error
is defined as a collision that occurs after
the slot time
(51.2 usec)
has expired. The slot time is the
maximum length of time for a signal to propagate from one end
of an NI network and back. All other nodes on a network should
observe

that

station

transmitting
2-22

and

they

should

defer.

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE
<0-7>

<8-156>

<16-23>

STATUS

FLAGS

OPCODE

MBZ

<0-19>

mBZ

<20-35>

LENGTH OF TEXT DATA

HIGH ORDER DESTINATION

LOW ORDER DESTINATION
HIGH ORDER SOURCE

LOW ORDER SOURCE
MBZ

<16-31>
PROTOCOL TYPE VALUE

BSD BASE ADDRESS

(BUFFER SEGMENT DESCRIPTOR)
<6>

<12-35>

MBZ | oacking MODE | MBZ | SEGMENT BASE ADDRESS
<12-35>

MBZ

NEXT BSD ADDRESS
<20meraemeameaees 35>

MB2Z

SEGMENT LENGTH

RESERVED FOR USE BY SOFTWARE

TEXT DATAO

TEXT DAfiIA 1

TEXT DATA 2

TEXT DATA N-1

TEXT DATAN

1
MR-13669

Figure

2-23

This error indicates
while there was data

DGRCV

Response

the host memory free
remaining in the NIA

Format

space was exhausted
receive buffer.

The text data field contains the length of the transferred text
data in bytes, plus four bytes to include the cyclic redundancy
check
bytes
at
the
end
of
the
packet.
A received packet has
appended to it the CRC transmitted by the transmitting node. The
length value does not
include the packet header.
This
is
the
length of the data portion of the datagram.
The packet length
field always indicates the actual number of bytes in the packet,
even
if
the packet
is
too
1long,
or
if an error of some sort
occurs. The received CRC bytes are placed into the host memory
buffer immediately following the end of memory data to allow a
software double-check of packet integrity.

The

protocol

type

field

contains

the

protocol

type

the

The
format
for
this
field
is the same as that
command, and the protocol type field of a PTT entry.

packet.

SNDDG

destination

The

address
that

messages

received

distinguished

physical

00 01

address

RS B

BN SR

BYTEO
T
T
T

wire.

multicast

from

(by the driver)
of the port.

02 03 04 05 06 07 08 09 10 11

| NN

for

the

This

messages

received

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

T
T

BYTE 1
N
T
NS N

destination
port
field is included so
address
(by the port)
can

contains

high/low
field
from the NI

received

BYTE 2
S
N TN W

received
for the

| B

BYTE 3
U
N
R

the

32 33 34 35

for

mMBz
11

LOW

‘00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3233 34 35
LI

| EN B

BYTE 4
|W

BRN |

-Trrrrrre-reero
T
v

BYTE 5
W

mBZ

§UNN U WO W

I W

VN W

NN NNV W

TN WY NN U

HIGH
WU U

SN N

N|
MR-13668

Figure

2-24

Originating

Port Address

Format

The source high/low field contains the originating port address.
The format of this address 1is given in Figure 2-24, where byte O
is the first byte received over the NI wire. Byte 5 is the last
byte received.
Text
text

data 0 contains the first byte of the received packet.
portion of a received datagram is always assembled by

data

modes.

For

The
the

port left to right. That is, the first byte of text received will
be placed into bits 0-7 of the first text word, the second byte of
text received will be placed into bits 8-15, the third into bits
16-23, the fourth into bits 24-31, and so on. This occurs for all
description

the

BSD

base

address

refer

Section

2.3.3.1.

2.4.1.4
Load Protocol Type Table
(LDPTT)
Command =-- When this
command is accepted by the port, the PTT specified will be cached
internally to the port local RAM storage memory. Note that the

protocol

free

queue

addresses

are

cached

internally

well,

Therefore, the free queue headers cannot change addresses unless
this command 1is issued as well. The addresses specified in this
table point to the free queue header, not to the first queue entry
of the queue chain.

The address of the PTT specified in the
a running port without initialization.
The

format

the

LDPTT

command

PCB

may

not

specified

Figure

altered

2-25,

in-

QUEUE FLINK
QUEUE BLINK

RESERVED FOR SOFTWARE

<0-7>

<8-15>

STATUS

<16-23>

FLAGS

OPCODE

MBZ
wA.13670

Figure

The
is

operation
accepted

additional
If

the

after

queue

command

Protocol
signals

internally

not

(by

setting

enabled.
be linked

Type

Table

completion

the

end

response

given

should

not

driver

packet

PTT

the

Command

Format

When

cached.

the

command

There

data.

response

The

command

port,

initialization

2.4.1.5

this

for

the

protocol
types
are
address filter will

command

LDPTT

code

LDPTT

2-25

executed
bit

before

enabling

the

CSR),
the
type

Loaded

—--

(PTTLD)

Response

building

response

the

response

queue.

and

The

port

then

Any
packets
that
pass
to the unknown protocol

Figure

the

The

LDPTT

putting

format

receive
queue.

that
that

2-26.

assume

that

protocol

type

has

been

until this response is received from a LDPTT command. The
and
flags
fields are not modified by this response
(same
the command).

enabled

opcode
for

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

STATUS

<8-15>

FLAGS

<16-23>

OPCODE

mMBZ
MR-13870

Figure
2.4.1.6

2-26

PTTLD

Response

Format

Load
Multicast Address Table
(LDMCAT)
Command
-- When
this
command
is
issued,
the
multicast
address
table
(MCAT)
1is
loaded
in the port from the table whose address
is specified by
the PCB. At initialization, no multicast addresses are enabled to
allow
upper
layers
of
software
(users)
to
1initialize
before
enabling.

For

the

driver

running

port,

PCB

MCAT

the

increasing
When
the
addresses
The

numerical

1is

must

multicast

memory

into

Then

the

address

the

internal
stated

with

the

cache

the

from

pointed

addresses

command

returned,
effect.

for

address

LDMCAT
is
in

format
be loaded
code
for

pointer

this
command
this table are

the

2-27). This table must
effect.
The
operation
other queue data.

address

order.

to
in

loaded

delete

built

base

response
specified

table

add

MCAT

the

issued.

multicast

the

port.

MCAT

(see

This
Figure

before address checking will take
this
command
is
2.
There
is
no

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE
-

§19A7TTJS

:L8Aé5é>

Figure

2.4.1.7
of
the

o;cooe

MBz

<16-23>

2-27

LDMCAT

Command

Format

MCAT Loaded Response LDMCAT -- The successful completion
LDMCAT
command
is
signalled
by
the
building
of
the

following
response
on
the
response is shown in Figure

response
queue.,
2-28. The driver

The
format
of
can assume that

the
the

QUEUE FLINK

QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

<8-15>

STATUS

<16-23>

FLAGS

OPCODE

MBZ
MR-13670

Figure

specified

MCAT

response

packet.

modified

this

has

2-28

been

The

MCATLD

loaded

command

command.

Response

Format

only

after

opcode

and

flags

has

received

fields

are

this
not

2.4.1.8

Read

and

command

reads

the

Clear

Performance

performance

Counters

counters,

RCCNT

Command

returning

the

their

—-

This

value

read
counters
block
pointed
to
by PCB
+30,
and
clears
the
performance event counters as specified by a bit (14)
in the flags
field.
The format of the
in Figure 2-29,.

command

queue

entry

accomplish

this

given

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

<8-13> | <14>

STATUS

FLAGS

| cLRCTR

<16-23>

|<'5>|

oprcopE

MB2Z
MR-13871

Figure

2-29

RCCNT

Command

Format

The
operation
code
for
this command packet
is
4.
built if the response bit in the flags word is set.

Datagram

protocol

discarded

queues,

and

can

get

for

execution
of
protocol
type
corresponding

returned

with

on,
has
By

bit

combining

event

the

passes

—--

following

the

Bytes

data

the

text

data

over

the

NI.

the

entries

Cleared

field

are

not

clear

commands,

skewed

when

note

that

address
This

counter

operation

This

type

driver

exhausted

for

every

counters

enabled

are

Response
-If
the
command packet is
built.
The response

the

driver

knows

clear

command

packet

that

issued.

not

received

represents

the

number

8-bit

datagrams

over

the

NI.

This

filter.

received

characters

original

not

transmitted.

queue

the

returned
PTT.
Those

(CNTRC)

the

to
the above command
in Figure 2-30.

list,

Thus,

that

and

received.

text

are

characters

Bytes

bits

free

counter

read

includes maintenance
in section 2.6.
BX

type

flags

receive

the

zero.

Read

the

counters

protocol

allowed

protocol

each

queue.

entry

value

for

type

command.

then a
response
the format shown

the

when

kept

protocol

this

Counters

response

are

unknown

indication

2.4.1.9

counters

the

response

protocol

counter

transmitted

(MOP)

packets,

represents

the

successfully

unless

explained

number

datagrams

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

STATUS

<16-23>

<8-15>

OPCODE

FLAGS

WWWW

WWNMM
BR

BX
FR

FX
MCBR
MCFR
FIXD
FXSC

FXMC
XF

XFBM
CDCF
RF

FRBM
DDUPT
DDPT1

DDPT2
DDPT3
DDPT4
DDPTS
DDPT6

MR-13672

Figure

FR -- Frames
frames

2-30

received.

CNTCL Response Format
(Sheet 1 of 2 sheets)

This counter

(packets or datagrams)

represents “the number

that have been received over the NI

wire.

Frames

transmitted.

This

counter

represents

the

number

frames that have been successfully transmitted over the NI wire.

DDPT?7
DDPT8

DDPT9

DDPT10
DDPT11

DDPT12
DDPT13

DDPT14
DDPT15
DDPT16

URFD
DOVR

SBUA
UBUA

PLI REG RD PAR ERROR

PLI PARITY ERROR

MOVER PARITY ERROR

CBUS PARITY ERROR

EBUS PARITY ERROR

EBUS QUEUE PARITY ERROR

CHANNEL ERROR

SPUR CHANNEL ERROR

SPUR XMIT ATTN ERROR

CBUS REQ TIMEOUT ERROR

EBUS REQ TIMEOUT ERR

CSR GRNT TIMEOUT ERROR

USED BUFF PARITY ERR

XMIT BUF PARITY ERROR

RSVD FOR UCODE

17 18

35
MA-13873

Figure

2-30

CNTCL

Response

(Sheet

Format
sheets)

MCBR
—-Multicast
bytes
received.
This
counter
represents
number of 8-bit bytes received in packets with the multicast
set in the destination field. This includes broadcast.

the
bit

MCFR
-Multicast
frames
received.
This
counter
represents
number of frames that were received with the multicast bit in
destination field set. This includes broadcast.

the

FXID

represents

other

Frames

transmitted,

the

traffic

number

the

initially

frames

wire

deferred.

transmitted

before

2-29

that

transmission.

This

had

the

counter
defer

FXSC

Frames

represents

the

transmitted,

and

transmitted,

single

<collision.

number

frames

that

which

collided

with

another

This

were

counter

successfully

transmission

exactly

once.

FXMC

Frames

represents

transmitted,
than once.
XF

that

number

and

Transmit

frames

transmitted,

the

which

not

frames

collided

failures.

were

multiple

This

with

This

that

successfully

were

another

counter

successfully

collisions.

counter

transmission

represents

transmitted.

the

This

number

counter

incremented
for excessive collisions,
parity errors, and so on.
This counter
is associated with the XFBM, which notes occurrence
of error classes.
XFBM

Transmit

failure

accumulated

reasons

are

Table

given

Table

2-3

for

mask.

This

Transmission

Failure

Bit No.

Reason for Failure

0-23

Unassigned

Loss of carfier

Transmit

Remote

Frame

Open

Short

Carrier

buffer

failure
too

The

gives

bit

the

meanings

detect

Bit

Mask

parity
to

Assignments

error

defer

long

circuit
circuit

check

failed

(collision

detect

failed)

Excessive

Collision

counter

failures.

2-3.

check

CDCF

bit

transmission

collisions

check

failed.

This

counter

gives

the

number
of
times
that
the collision detect check
failed after a
transmit.
This
is
the
number
of
times
that
heartbeat
failed
to
assert after a
transmit ended.
This counter has meaning only if
the

H4000

mode

bit

set.

—--

Receive

frames

failures.

whose

associated with the
various error types.
RFBM

Receive

accumulated

given

reasons

Table

This

reception

counter

RFBM

counter,

failure

bit

for

gives

wultimately

which

mask.

receive

the

number

This

counter

failed.

marks

This

failures.

The

received

occurrence

counter

bit

gives

|is

the

definitions

are

2-4.

2-4

Reception

Failure

for

Bit Mask

Bit No.

Reason

0-26

Unassigned

Free

list

Data

overrun

Frame

Framing

Block

too

Assignments

Failure

parity

error

(no

free

buffers)

long

error

check

error

DDUPT
-Datagram
discarded
for
unknown
protocol
type.
This
counter Kkeeps track of the number of datagrams discarded for the
unknown protocol type free queue. Any time a datagram is discarded
with an unrecognized protocol type, this counter is incremented.
DDPT1 to DDPT16 -- Datagram discarded for protocol type N. These
counters keep track of the number of datagrams discarded for each
of the protocol type free queues. When a datagram is discarded
because
of
no
available
free
space,
one
of
these
counters
is
incremented,
if the protocol type was enabled. There are as many
of

these

types

counters

allowed

the

needed

support

configuration

the

number

URFD
-Unrecognized
frame
destination.
This
meaning for the NIA20 and will always be reported
DOVR

Data

overrun.

This

counter

space

SBUA -- System buffer unavailable. This counter
the NIA and will always be reported as zero,

{

[\®)

protocol

counter
as zero.

represents

packets incorrectly received due to buffer
exhausted. Such packets are discarded.

the

has

the

has

number

NIA

being

no meaning

for

UBUA

User

number

buffer

packets

This

number

type

counter.

Words
have

the

counters

47-55
an

unavailable.

discarded

total

and

the

NIA20

are

initial

the

This

the

port

represents

free

datagram

threshold

counter

because

queue

discarded

recoverable

for

—--

the

port

Reserved

2.,4.1.,10
command

For

microcode
Write
causes

microcode.

and

for

Port
a

PLI

the

Link
write

These

present

1Interface
cycle

for

protocol
protocol

These

are

counters

reserved

returned

(WRTPLI)

the

total

port
initialization.
be
set
via
a
write

counters

will

the

exhausted.

unknown

errors.

of
5,
set during
variable
and
can

This
threshold
count
1is
station information command.
RSVD

was

Command

indicated

for

zeros.
--

operation

This
to

bit

performed.
CAUTION

Execution

of
illegal or
random commands
will compromise the functionality of the
interface in an indeterminate fashion. It
is
recommended
that
the
port
not
be
executing
meaningful
commands when
this
command
is
issued.
This
command
is
for
diagnostic purposes only.

The WRTPLI

command

format

shown

Figure

2-31.

QUEUE FLINK
QUEUE BLINK

RESERVED FOR SOFTWARE

<0-7>

<8-15>

STATUS

<16-23>

FLAGS

OPCODE

MBZ

<20-23>

MBZ

CONTROL

<28-35>

MBZ

PLI DATA
MR-13674

Figure

The

operation

the

flags

code

word

for
on,

this

command

anchored

the

PCB.

the
interface.

same

port
link

in
driver

2-31

will

this

WRTPLI

packet

response

built

Command

confirming

and

placed

Format

the
the

response

correct

the

execution

response

dqueue

This
command,
along
with
RDPLI,
gives
the
visibility as the port itself into the port

The
the

control
field specifies the PLI control bits to be
put onto
PLI when the write cycle is done. The PLI data field
is light
bits
wide.
The
use
of
these
control
bits will
be explained
in
Chapters 4 and 5. The command codes map into the PLI
commands as
shown in Table 2-5,

Table

Value

2-5

(octal)

Command

Code

Values

and

Function

Illegal

Receive

Write

Read receive buffer
Write transmit action (4
Reset receive attention
Enable link control

04
05
06
07
10

buffer

free

transmit

buffer

list

command

group)

Disable link control
Write address register
Write transmit buffer

11
12
13

Write
Clear

2.4.1.11
WRTPLI

Functions

Port

Link

command

Interface

results

Written

(PLIWRT)

response

the

Response

response

The

bit

the

format

When

flags field of the original packet was set. The driver
is assured
that the port
interface has executed this command only after the
response

has

shown

Figure

been

received.

2-32.

built,

the

response

has

QUEUE FLINK
QUEUE BLINK
RESERVED FOR SOFTWARE
<0-7>

<8-15>

STATUS

<16-23>

FLAGS

OPCODE

<20-23>

MBZ

CONTROL

<28-35>

M8z

PLI DATA
MR-13674

2.4.1.12

executed,
using

the

response

Figure

2-32

PLIWRT

Read

Port

this

Link

command

1Interface

control

queue

bits

entry.

causes

Response

read

specified.

The

Format

(RDPLI)

PLI

Command

cycle

data

executed,

returned

the

The data for this command is returned in the response entry built
if the response flag is set when the command is executed,

The format of this command is specified in Figure 2-33.

QUEUE FLINK
QUEUE BLINK

RESERVED FOR SOFTWARE
R

E?A7T1>Js

MBZ

<16-23>

OPCODE

:3\2;?5)

MB2

CONTROL

MB2

<20-23

RDPLI Command Format

Figure 2-33

2.4.1.13 Port Link Interféce Read (PLIRD) Response -- The format

of the response given to this command if the flags response bit is
on is specified in Figure 2-34. The operation code for this packet
is 7. This command does not generate an NI packet. Through this
command,

processor

the

port

driver

read

can

any

itself can read over the PLI.

dquantity

that

the

port

QUEUE FLINK

QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

STATUS

<16-23>

<8-16>

OPCODE

FLAGS

<20-23>

CONTROL

MBZ
MBZ

MBZ
<28-35>

PLI DATA
MR-13676

Figure 2-34

PLIRD Response Format

The four control bits specify the state of the control bits to be
used during the read cycle. The use of these control bits will be
explained in Chapter 4. The command codes map into PLI commands as
defined

in the Table 2-6.

Table

2-6

Control

Value
00

(octal)

Bit

Values

and

Functions

Function

Illegal

Read
Read

Read

used

Read

transmit

Read

receive

buffer

list

status
status

If
the command
selected
is not defined
in Table
2-6
as a
legal
function,
a
response will be generated with the status field set
illegal PLI function.
The

PLI

the

data

field (and
response
built

response

bit

field

the

data

the

RDPLI

the

for

flags

that

was

word

that

this
field

read

contains

command
is

from

command.

set.

the

it)
is present only
occurring
when
the

-In

the

PLI

response,

the

this

execution

CAUTION
is
recommended
that
the
driver
not
execute this command while other commands
are pending or while packet reception is
enabled. Careless use of this command can

cause

the

normal

port

functionality

compromised.

2.4.1.14

this
link
data

Read

NI Station Address (RDNSA) Command -- When executed,
causes the NI station address to be read from the NI
In addition,
some
status mode
bits
are read.
This
returned in the response queue entry, if specified by
the

command
module.
is

response

bit

the

flags

field

the

command.

The
format
of
this
command
is
specified
in
Figure
2-35.
operation code for
this packet
is 8.
If the response bit
in
flags word
is on, a response confirming the correct executio
the
command
will
be
anchored in the PCB.

built

and

placed

onto

the

response

QUEUE BLINK

RESERVED FOR SOFTWARE
<8-15>

STATUS

<16-23>

FLAGS

OPCODE

MBZ

MR-13670

Figure

2-35

RDNSA

2-35

the

QUEUE FLINK

<0-7>

The

Command

Format

queue

2.4.1.15 NI Station Address Read (NSARD) Response -- If built, the
response to the RDNSA command is shown in Figure 2-36.

QUEUE FLINK
QUEUE BLINK

RESERVED FOR SOFTWARE

OPCODE

FLAGS

STATUS

MEZ

<16-23>

<8-15>

<0-7>

<0
HIGH ORDER NI ADDRESS

<32-35>
MBZ

31>

MBZ

LOW ORDER NI ADDRESS
Do S—— 31> | <32>

ACRC

MBZ

P NS 15>
MBZ

<33>

AMC

<34>

H4000 MODE

O [ — 23>
UCODE VERSION

<35>

PRMSC MODE

<24-29> | <30-35>
PTT
MCAT

MR-13681

Figure

2-36

RDNSA Response

Format

The high and low order NI address value is the physical station
address stored in the physical address RAM on the NI link board.
It corresponds to the address of the NI

link.

The ACRC bit indicates whether the NI link will discard incoming
packets with CRC errors. If set, the link will accept all incoming
packets with CRC errors and place them on the unknown protocol
type free queue if an entry is available. If reset, the link will

discard all

incoming packets with CRC errors. The initial value of

this

bit

1link will accept all
the NI
indicates whether
bit
The AMC
multicast packets (if set) or perform normal multicast address
filtering (if reset). The initialization value of this bit is 0.

The H4000 mode bit shows its current state. This bit, 1if set,
enables the heartbeat detection checking for the H4000 type NI bus
tranceiver.

The

initialization value of this bit is 0.

The PRMSC mode bit, if set, indicates that the link is operating
in promiscuous mode. All packets detected on the wire will be
interpreted as being addressed to this node. The initialization
value

this

bit

The Ucode version field gives the version of microcode loaded into
the

port.

The

MCAT

The

PTT

field
field

gives
gives

2.4.1.16

Write

executed,

this

response

the

number
number

Station

of
of

MCAT
PTT

sets

the

well

the

several

for

this

command

the command
illustrated

entries

Address

command

link board,
operation.
A

the

allowed.

(WRTNSA)

physical

mode

built

Command

address

bits

only

data

response

packet flags byte is on. The format of
in Figure 2-37. The operation code for

the

for

the

RAM

this
this

When

the

1link

bit

command
command

is
is

QUEUE FLINK

QUEUE BLINK
RESERVED FOR SOFTWARE

<0-7>

<8-16>

STATUS

<16-23>

FLAGS

OPCODE

MBZ

31>

<32-35>

HIGH ORDER NI ADDRESS

MBZ

LOW ORDER NI ADDRESS

MBZ

P — 31> |

<32>

<33>

MBZ

ACRC

<34>

AMC

<35>

H4000 MODE

PRMSC MODE

23>

<24-

MUST BE ZERO

35>

RETRIES ALLOWED

MR-13882

Figure

The

high/low

RAM

link
The

the

will
ACRC

bit

with

packets

with

free

discard
value

Setting
mode.

the

indicates

incoming

this

the

bit

AMC

bit

and

entry

place
is

packets

the

physical

completed,

address

link

will

link

will

them

available.

with

Format

command

physical

the

set,

Command

written
the

the

whether

errors

After

with

errors.

CRC

WRTNSA

address

board.

packets

CRC

queue

all

1link

packets
type

order

2-37

CRC

discard

The

puts

the

When

enabled,

all

receive

address

filter.

port

multicast

into

the

packets

all

unknown

reset,

errors.

the

specified.

the

address

the

incoming
incoming

protocol
link

will

initialization

receive

all

multicast

received

are

passed

The H4000 mode bit, if set by the driver, will enable H4000 mode
-- enable heartbeat detection checking by the transceiver.
If PRMSC mode is set by the driver, all packets seen on the NI
cable will pass the received address filter. This is a diagnostic
feature.

CAUTION

Turning

cause

can

mode

this

significant degradation of system network
performance, depending upon network load.

of
retries
many
how
specifies
field
allowed
retries
The
retrievable errors are to be attempted by the port before the
error is declared uncorrectable. The default number of retries is
3.

2.4.1.17 NI Station Address Written (NSAWRT) Response -- The
response format to the WETSNA command is given in Figure 2-38. The
definitions of the bits for this response are the same as those
for

the WRTNSA command.

QUEUE FLINK
QUEUE BLINK

RESERVED FOR SOFTWARE

OPCODE

FLAGS

STATUS

<16-23>

<8-15>

<0-7>

B8Z
<32-35>

31>

MBZ

HIGH ORDER NI ADDRESS

MBZ

LOW ORDER NI ADDRESS
Sttty <32>

MBZ

MUST BE ZERO

<34>

<33>

H4000 MODE

AMC

<35>

PRMSC MODE
35>

<24

-23>

RETRIES ALLOWED
MR.13683

Figure

2-38

NSAWRT Response

Format

Self-Directed Commands -- Loopback

2.4.2

It is specifically allowed for a datagram transmitted to be
destined for the transmitting node, as one form of loopback. The

design

the

adapter

(the

physical

channel),

however,

shares the CRC generator/checker between the receive and transmit

circuits.

Since

the

packets

CRC

circuits

destined

that

will

This

driver

for

must

the

transmitted

CRC

1is

and

the

included

The

text

length

2.5
The

DATA
KL10

used

place

appended

packet,

set.

CRC

does

supports

the

onto

the
bit

not

one

02 03 04 05 06 07 08 09 10 11

BYTE O

Figure

2.6
The

handle

]

KL10

Request
Loopback

Read

Higher

the

layers

normal
FLAGS

appended

data

field

CRC.

mode.
The mode
is
illustrates
the
industrybytes into 36-bit KL10 words.

19 20 21 22 23 24 25 26 27 28 29 30 31
SR

- BYTE 2
H

Word

]

32 33 34 35
T

BYTE 3

]

(Industry-Compatible

mMBZ '

Mode)

PROTOCOL

Ethernet

specification

includes

these

client
these

will

fact,

MOP

messages

and

functioning.

software

ERROR

these

should
higher

handle

the

not

giving

layers

MOP

messages;

correct

software

responses

are

not

present

HANDLING

The

port

fail

into

the

port

encounters

microcode

allow

is
capable
of
retrying
large part of the error

microcode

any
to

The

node

(RDCNT)

microprocessor

interrupt.

the

packet

space considerations do not allow
in the NIA20 port microcode.

entry

the

Microcode
implemented

port

processing

end

(REQID)

counters

the

2,7

CRC.

(LPBK)

protocols.
to

code

internally generated

formatting

| B

OPERATION

packet,
CRC

specification
requires
that each NI
maintenance operation protocol (MOP) messages:

certain

features

16 17 18

MODE
data

incoming
supply

management

addition,

queue

2-39

layer

BYTE 1

MAINTENANCE
network

12 13 14 15

the

must

include

industry
compatible.
Figure
2-39
compatible mode for mapping 8-bit NI

00 01

check
node

(ICRC)

FORMATTING/PACKING
port

transmitting

and

fatal,

more
the

port

removed

commands.
tail

will

from

nonrecoverable
of

then

the

port

error,

The

port

the

response

enter

many
operations
that
recovery to be built

will

the

driver.

the

port

then

move

queue

and

disabled

When
will

the

the
stop

command

request

state.

While
the port
is waiting
for port driver
intervention,
it will
not be emptying packets out of the receiver buffer, so packets may
be discarded due to lack of available buffer space. While the port
is
in the disabled state,
event counter is made.

increment

datagrams

discarded

A class of more severe errors causes the port to cease operations
immediately and exit to a special microcode location that has a
CRAM parity error. The host will notice the error location, and
will reinitialize the port, if possible. Errors in this class
indicate a failure in the interfaces between the port and the
interrupt
the CBus,
the EBus,
(e.g., memory,
external world
port
serious
Errors of this severity indicate a
structure).
that
indicate
to
trying
hardware problem. In general, the port is
it cannot communicate with anything.

2.7.1

Error

Events

Some errors may not necessarily involve a hardware malfunction,
Such errors include excessive collisions, CRC errors, and framing
errors. The occurrence of these errors terminates the packet
transmission or reception in progress when the error occurs, but
does not affect the processing of other commands or packets being
received.

Errors of this sort are reported by creating a response packet for
the transfer involved, and setting the status field accordingly.
Table 2-7 provides a list of possible error conditions.
2.7.2

Discarded Datagrams

Under certain conditions, received datagrams may be discarded
because of insufficient buffer space -- characteristic of the
datagram class service offered by the NI port. For example, if a
in the NIA and
received datagram is occupying buffer space
fails, the
queue
free
some
from
entry
queue
free
obtaining a
and the datagrams discarded
is discarded,
involved
datagram
counter for the appropriate free queue is incremented. This occurs
even if buffer space in the link is still available.

The reasons for this are that 1) other packets being received may
be able to be stored since the free queue error condition is
protocol-type-dependent, and 2) if the link fills up, datagrams
will be discarded without increment of a datagrams discarded event
counter. No other error indication or response is made. It is up
to higher levels of the network to detect and recover from such
errors.

If the port is addressed by a burst of packets such that the
internal buffer space in the NI physical channel 1is exhausted,
datagrams may be discarded without increment of the datagrams
The buffer space allowed in the physical
discarded counter.
channel (NI 1link) is sufficient to make this event unlikely. The
NIA has 16K bytes of buffering, normally organized as 32 pages of
512 bytes each. This storage is sufficient for 32 minimum-size
packets and

10 maximum size packets.

Table
Error

2-7

Possible

Condition

Unrecognized

Error

Description

command

Packet

(from

operation
Buffer

length

Conditions

violation

BSD

has

driver)

has

invalid

buffer

1length

code
inconsistent

information
CRC

error

Framing

error

Received

packet

Received

data

has

not

CRC

error

byte

aligned

an
integral
number
of
frame
(number
of
bits
divisible by 8)
Packet

too

Excessive

long

collisions

Packet

length

Ethernet

packet

Packet

16
Carrier

lost

exceeds

Carrier

maximum

length

transmission

times

(not

octets
1in
not
evenly

attempt

collided

succession

1lost

before

end

packet

detected

Collision

detect

check

Collision

detect

heartbeat

failed

assert

Remote

failure

(also

called

System

late

buffer

2.7.3

defer

Collision

collision)

time

expired

Port

microcode

free

queue

unavailable

occurred

after

was

KL10

unable

slot

get

memory

Event

provide

purposes,

Counters
for
performance

number

event

measurement,
counters

are

and

for

provided

These record the occurrence of certain events,
cleared
upon
command
by
the
driver
program.

and
The

counters

these

returns
These

the

(RCCNT)
command
reads
the
value
them in the read counters block.

event

errors,

but

hardware
follows:

counters
high

not

counting

software

Received

2.,

Transmitted

necessarily
rates

failure.

byte

for
list

record,

some
of

them

diagnostic

the

port.

can be read and
read and clear
counters

imply,
may

applicable

and

abnormal

point

events

to
is

a
as

.
.

Received a frame
Transmitted a frame

.
.

Received a multicast byte
Received a multicast frame
Transmitted a frame that was

.
.
.
10,
11.
12.
13.
14.

15.
16.
17.
18.

Transmitted a
Transmitted a

Failed to transmit a frame successfully
Sent failure reason bit mask
Transmitted a frame with a late collision
Failed to receive a frame successfully
Received failure reason bit mask

Discarded a datagram for unknown protocol type free queue
Discarded a datagram for protocol type entry 1 free queue
Discarded a datagram for protocol type entry 2 free queue
Discarded a datagram for protocol type entry 2 free queue
through

2.8

initially deferred
frame with a single collision
frame with multiple collisions

free

queue

CONTROL AND STATUS

The control and status register (CSR) is another mechanism for
communication between the KL10 and the NIA20 port. It is a 36-bit
register that resides in the port's EBus interface module.
The KL10 accesses the CSR by executing CONO and CONI commands and
the port accesses the CSR by executing MPLOADCSR and MPREADCSR
commands to load or read the register. The register
1is read/write
interlocked

prevent

simultaneous

access.

A complete explanation of the register bits and their meaning is
provided in Chapter 5. It is important here to understand that
this
method
of
communication
exists.
Some
of
the
functions
performed

.
L]

OO
U
Wi

l.
.

using

the CSR

include:

Port is enabled or disabled
Port is in the idle loop
Microprocessor is in the run
Port requested an interrupt

Port error:

port

CRAM parity error
MBus error exists
EBus parity error

state

informs driver
exists

that an error occurred

exists

The CSR is important in error handling and reporting. Some classes
of errors are severe and are reportable only through the use of

the CSR -for example, a planned CRAM parity error, which is the
result of the port executing a known bad parity microinstruction.
These instructions are purposely written to the CRAM with bad
parity and are used only when certain error conditions appear. It
will
be detected by the CRAM parity
logic and will force a
nonvectored

interrupt.

2.9

NETWORK

Networking

ARCHITECTURE

systems

AND

FUNCTIONAL

are designed

and

LAYERS

constructed

functional

layers.
Each
layer
performs
a
specific
set
of
functions
and
services. The combination of the layers creates what is called the
network architecture, where the layers interact to provide total,
end-to-end network operation.
Most

network

architecture

conforms

the

International

Standards

Organization's
model
for
Open
Systems
Interconnection,
and
the
Digital Network Architecture
(DNA)
is no exception.
Figure 2-40
shows
how
the
functional
1layers
of
the
ISO model
and
the
DNA
layers

correspond.

lt— 1S0 —8>]

|¢——————— DIGITAL NETWORK ARCHITECTURE ————————
|

@ ARCHITECTURE LAYERS ————

APPLICATION

|« CAPABILITIES ——————
|

USER

}----

FILE TRANSFER

REMOTE RESOURCE ACCESS

NETWORK

DOWN LINE SYSTEM LOAD

MANAGEMENT

REMOTE COMMAND FILE
SUBMISSION

NETWORK

PRESENTATION

VIRTUAL TERMINALS

APELICATION

SESSION

SESSION CONTROL
———

PROGRAM-TO-PROGRAM

END-TO-END

TRANSPORT

COMMUNICATIONS

NETWORK

ROUTING

DATA

LINK

DATA LINK

PHYSICAL

PHYSICAL LINK

ADAPTIVE ROUTING
|

oocme

PTTO PT

X.25

ETHERNET

MULTIPOINT
MR-13685

Figure

2-40

Digital

Network

Architecture

(DNA)

Functional

Layers

2.9.1
Physical Link Layer and Data Link Layers
The physical layer is the bottom and most basic layer. It manages
the
physical
transmission of
information over
the
channel.
The
data
1link
1layer,
residing
immediately
above
the
physical
1link

layer,
frames
nodes,

creates
a
communications
path
among
adjacent
nodes.
It
messages
for
transmission on
the channel
connecting
the
checks the integrity of received messages, and manages the

use

channel

resources.

The physical and data link layers operate together to provide a
packet
delivery (or
datagram)
service
between
nodes
1in
the
network, where packets are sent from the doorstep of one node to
the
doorstep of
another.
The
Ethernet
specification deals with
these
two
layers
and
describes
the
necessary parameters
and
protocols,

2.9.2

Routing

Layer

The routing
layer provides a message delivery service,
routing
user data packets to their destinations. The routing layer and the
remaining
upper
layers
support
multiple
types
of
data
1link
circuits. In addition to Ethernet, for example, point-to-point and
X.25

(packet

switched)

virtual

circuits

could

supported.

2.9.3
End-to-End Communications Layer
'
The end-to-end communications layer provides a system-independent
program—to-program communication service. It allows two processes
to exchange data reliably and sequentially, independent of which
network
systems
are
communicating
or
their
location
1in
the
network. Network services protocol
(NSP)
is used for end-to-end
control of addressing, data integrity checking, transaction flows,
interrupts, and flow control among communicating processes.
2.9.4

Session

Control

Layer

This
layer
provides
system—-dependent,
program—to-program
communications functions that bridge the gap between the previous
layer and the logical link functions required by processes running
under

Session

operating

control

addresses,
processes,

system.

functions

identifying
and validating

1include

mapping

node

names

end
users,
activating
incoming connect requests.

node

creating

2.9.5
Network Application Layer
The network application layer controls the network functions used
by the two higher layers of DNA.
Services
include remote file
access, remote file transfer, remote interactive terminal access,
gateway access to non-DNA systems, and resource managing programs.
2.9.6

Network

Management

Layer

The network management layer is the only layer that has direct
access to each lower layer.
It provides the functions to plan,
control,
and maintain
the operation of the network.
Functions
include down-line loading, up-line dumping, remote system control,
test functions, and event logging functions.
2.9.7

User

Layer

The user layer contains most user-supplied functions,
including
programs that access the network and those network services that
directly support

user

and

application

tasks.

Some
examples
of
the
more
common
services
accessed
by
users
include
resource
sharing,
file
transfers,
remote
file
access,

database management,
2.9.8
Figure

and

network

management.

Layer Interfaces
2-41 shows the relationships

three

layers

layer

for

each have a

logical

link

direct

services,.

among the DNA layers. The top
interface with the session control

USER

—-[

NETWORK MANAGMEMENT

—»I

NETWORK APPLICATION

—»L

SESSION CONTROL

]

—-—D-hEND commumc;mous]

——>|

ROUTING

———b{

DATA LINK

PHYSICAL LINK

]

PHYSICAL CHANNEL

MR-13686

Figure

Each

layer

2-41

interfaces

DNA

Layers

the

layer

with

and

directly

services. The network management layer
layer to get the data needed to control
Horizontal
of

network

arrows

show

direct

parameters.

layers
for
normal
down—-line loading.

access

Vertical

user

below

use

its

interfaces to every other
and manage the network.

for

control

arrows

operations

Interfaces

show

such

and

communication

interfaces

file

between

access

and

2.9.9
Expanded Ethernet Networks
Extending
the
capabilities
of
Ethernet
networks
can
be
accomplished
by
adding
communication
server
products.
These
products include:
-

Terminal

and

terminals

and

unit

servers,
record

which

connect

equipment

clusters
an

Ethernet

network

Router

servers,

Ethernet
or

other

convert

with

which

remote

DECnet

network.

protocols,

architecture

connect

DECnet

systems

another

Router

servers

they

enable

nodes

since

communicate

not

Ethernet
need
of

1like

Gateway

Servers

Systems

network

architecture

which connect DECnhet
2.

X.25

Gateway

(SNA)

gateway

systems with an

servers,

which

enable

X.25

packet-switched
network
to
connect
DECnet
with remote DIGITAL or non-DIGITAL systems

Gateway

between
Figure

servers

can

translate

nodes with different
2-42

shows

protocols

network

allow

architectures.

a DECnet with many connected

ETHERNET

servers,

IBM SNA network
public
systems

communication

Ethernet

segments.

ETHERNET

[

VAX

NONDIGITAL

PRO
350

ETHERNET

RSX

ROUTER

Y AX

VAX

‘ ETHERNET

RSTS

VAX

RSTS

RSX

MULTIDROP

.
RT

RSX

VAX

MR-13687

Figure

2-42

DECnet Network with Many Ethernet Segments

INSTALLATION

3.1
This

OVERVIEW
chapter
describes

Interconnect

Adapter

the

installation

KL10-E

system.

CHAPTER 3
IN KL1lO-E

NIA20

the

Appendix

NIA20

Network

describes

the

installation of the NIA20
in a KL10-D. Appendix B describes the
installation of the NIA20 in a KL10-R. Figure 3-1 and Figure 3-2
show
the
NIA20
installed
in
a
KL10-E,
rear
and
front
views,
respectively.
Table 3-1
itemizes the NIA20 parts,
and Table 3-2
lists the harness and cable connections used in the NIA20/KL10-E
installation.

::i
—
120

—

CAGE

CARD

PT6
~5.2H

MBUS
701927014

PT5 | DC POWER |VANE SW(TCH

rl_i

GND|

CABLE

DC POWER

CABLE

N 70]19272-00 | 7019862-00

7018273-00

NIA20

{}

—

CARD

#10

CABLE

H7420
T R

DC VOLTAGE MONITOR CABLE Y 2| |

\PLI 8US BCosR-sl[1

7020852-00 7021448-5C ——pm

CAGE

CABLES

SUPPORT
PANEL

LIMITER

NIA20

CABLE

NIA20~——p

#3LJ

7428311-01

7019274-06 _N]_

CURRENT

fl r

AC FAN CABLE

AC FAN
HARNESS

NIA20

CPU CABINET

I/0 CABINET

CABLES

REAR VIEW

Figure

3-1

NIA20

Table

KL10-E,

3-1

Parts

Rear

View

List,

NIA20

KL10-E

Line
Item

Part No.

Description

7019268-00

Card

Cage

Assy

IPA-20-L

7019268-01

Card

Cage

Assy

CI20

7428312-01

Bracket,

4
6
7

7428222-01
9006073-01
9006022-01

Baffle, Air
Screw, Mach
Screw, Mach

9006633-00

Washer,

Qty

Interface

Pan Phil 10Pan Phil 6Lock Internal Steel

1
1
13
6
6

Table

3-1

Parts

List,

NIA20

KL10-E

(Cont)

Line
Item

Part

No.

Description

9
10

1213716~00

Spacer,

7020539-06

Cable,

Fan

Qty

Foam Polyu
AC

1/2

4
1

7019274-06

Cable,

7019272-00

Harness,

DC-5.2

AC
Sect

N1l-1

DC+5

7019273-00

Harness,

DC~5.2

Sect

N1-2

DC+5

7019893-2L

Cable

Assy

BCOG6R

BCO6R

I/0 Cable

7019266-00

Module

Ethernet

Blank

Assy

M3002-00

CI20

Microprocessor,

M3003-00

CI20

C-Bus/PLI

M3001-00

CI20

E-Bus

Interface,

Multiwire

9007032-00

Tie,

Cable

Bundl.

0-1-3/4"=101

21
22

1213715-00
H7440-00

Clip, Flat
POAl1l H7440

Cable

W/Adhesive

L0072-00

NI20

(KL10

Adaptor)

7014103-~00

Blank

Module

9107673-06

Pwr

26
27
28
29

7011432-02
9007651-00
9006664-00
7020352-00

Pow Cord Extension 50Hz
Washer, Lock External Steel
Washer, Flat SST
:
Harness, DC Voltage Monitor

14
12

7019862-00

Harness,

Vane

5414506-01

Voltage,

Monitor

7019270-13

Bus,

Assy

33
34
35
36

3621499-01
3613272-00
9007031-00
9008264-00

Label, DCV Monitor CI20
Label, Adh Back, Mylar Cap
Tie, Cable Bundl. Dia 0-3/4"=101
Mount, Cable Tie, Adhesive Back

1
1
36
A/R

Cord,

Multiwire

Interface,
Dia

Multiwire

1
1
1
A/R
4

1
NI

Term

Cable,

Assy

3-14

SJT

115

Switch

Board

Airflow CPU/NI

3621498-02

Label,

9105740-55

Wire

7428311-01

(12 ft. required)
Support, Cable

A/R
1

40
41

9006659-00
5415695-01

Washer,
Current

2
1

7020488-00

Cable,

Short

7021448-5C

Cable,

(Wrap)

30AWG

KYNAR

20
UL1l4

Flat S/PAS
Limiter
Switch

Voltage

Vane

Monitor

W/0

3617674-00

Label,

Serial/Power

3617674-01
3617880~09

Label,
Label,

Serial/Power W UL & CSA
Class "A" Subassembly

1
1

3621501-02

Label,

Module

NI20

CSA

45
46

Location,

Sect.l

A/L/J_I:Y J"‘

H7420
POWER

SUPPLIES

PT6

—5.2H

PT5

\GND
3,

h¥

c120

1 CARD CAGE
L+—NIA20

CARD CAGE

CABLE
SUPPORT
7428311-01

OPTIONAL
(NOT INSTALLED

DC VOLTAGE — 1T

/’

WHEN CABLE

MONITOR
BOARD

SUPPORT PANEL
IS INSTALLED)

/0 CABINET

CPU CABINET

FRONT VIEW
MR-13890

Figure

Table

3-2

NIA20

in KL10-E
Harness

KL10-E,

Harness

and

Front View

Cable

Connections

pParts

List

Harness Terminals

Item

No.

Point

Connection

Remarks

NIA20

CPU

SECT.

N-2
J1

GND

-5.2H

——

Parts

H7440

——

See

Figure

3-5

See

Figure

3-5

Fan

Brkt.
Figure

—

See

——
-

Jl
P3

See Note
NIA20 BP

2
J6

——

NIA20

+5V

——

3-11

See

Figure

See

Note

See

Note

See
See

Note 1
Notes 1

Parts

Mon.Bd.

J1-5

List

See

List

Figure

Item

3-5

and

Item

A-2

Table

NIA20

3-2

in KL10-E Harness and Cable Connections
Harness

(Cont)

Connections

Parts

List

Harness Terminals

Item

No.

Point

Connection

Remarks

P3
P2
Pl

Pl
-=
-=

CI20 Cable Vane Switch
NIA20 Fan Brkt. Jl
CI20 Fan Brkt. Jl

See Note 4
See Note 4
See Note 4

Parts

Mon.Bd.

List

Item

Parts List

Item 31

NOTES:

Items

needed

not

when CI

kit

installed:

Item

Qty

Part No.

Description

5
6

8
8

9007786-00
9006073-01

Retainer, U-Nut 10-32X
Screw, Mach Pan Phil 10-

3
30

7428312-01
7019862-00

27
28

8
8
1

parts

9007651-00
9006664-00

existing

connector

Relocate

cable

into NIA20

list,

card

item
P4

from

(see

CI20

cage J6

Washer,
Washer,

Lock Ext ST
Flat SST
Bracket, Interface

Harness, Vane Switch

(harness,

vane

switch)

card

connector

Figure

3-11).

cage

connector.

connects with
and

insert

Table

3-2

NIA20

KL10-E

Cable

Harness

and

Cable

Connections

Parts

List
Item

From

No.

Unit

Location

Ref.Desig.

Unit

Location

Ref.Desig.

Remarks

C.Cage

Gnd

25 or

NIA20-CB

C.Cage

25/26

1Item 10

861

Fan

Brk J2

P2
PC

Connect
to

any

avail.
switched
outlet

1/2

C.Cage

NI20 BP J3

Gnd

Stripe

Cabrail

Hole 1

RH20

M3003 J2

P2 Stripe

Down

DTE

M3003
M3001

P3
Pl

M3002

P2
P2

RH20

BP B1lON1

RH20 BP

B13B1l

CcloL2

B13B2

B13Bl

B13B2
Cl0K2
B13Ul
cl0T2

Cl13B1

Cl2H2

B19B1

B19B2
B13Ul
B19Ul
Cl3Bl

Ccl9Bl

C1l3Nl

C13N1

clarl

cl3B2

Al5El

Cl3B2
Cl4Hd2
Cl4F1l
Al4J2

Ccl4pP1
Cl4K2

C20F1
A20J2
C20P1

B14J1
C20H2

C20K2
B20J1

Cl9Nl

Cl19B2
Al5R2
F15A1l

Al5D2
Al15S2
B15Al
A21R2

F21Al
A21El

A21D2

A21S2
B21Al

(Cont)

The NIA20
positions

installation uses assigned slots in RH20 logic assembly
4 and 5, with RH20 positions 6 and 7 reserved for

installation of a CI20 computer interconnect. A system\containing

the
1In
RH20s.
four
a maximum of
to
1limited
is
NIA20
an
installation of an NIA20, a module blank assembly, Digital P.N.
7019266-00, is used to prevent plugging any other module into RH20
gog?tion 4 as described in subsection 3.4.3, instruction 7 (Figure

\1\

MODULE
BLANK

M3003
SLOT 21

ASSEMBLY
SLOT 22

M3002
SLOT 20

o 8

)

MR-13891

Figure 3-3

MBus Cable Interboard Connection, Top View
NOTE

Previous or subsequent installation of a
minor
requires
NIA20
an
with
CI20
be
will
and
e
procedur
the
deviations from
described when applicable.

system requires
in an existing
Installation of +the NIA20
in this
described
are
which
s,
procedure
following
the
ing
implement

chapter.

COdOAUT
D WN

and checkout of
Preinstallation checkout
Backplane wire adds

Installation

NIA

Installation

10.

Installation

vane

l1l.

Installation

12.

Installation

PLI

13.

Installation

fan

Unpacking

14.

Installation

port

Installation

power

Installation

NIA

Installation

supply

3.2
Before
area.

all

cage
current limiter

power

voltage

If
one

harness
monitor harness

and

bus

and power
cable
adapter
board

KL10

module

cord
and

blank

module

Checkout.

Check

boxes

the

shipment

were

sent.

and

the

boxes are sealed,
holes, or damaged

harness

switch

UNPACKING AND CHECKOUT
unpacking any equipment,

Customer

regulator

card

ac cable
internal NIA

kit

modules

assembly

15,

installation

move

against the

branch

any

boxes

field

and there
corners).

all

are

service

boxes

packing

sign

into

list

missing,

manager.

the

computer
sure

Check

external

that

contact

the

that

damage

all

(dents,

any

boxes are open or damaged, document it on the install
ation
field service
report and
inform the customer.
Open the boxes
at

time,

starting

with

the

box

marked

"READ

FIRST"

and

phase,

advise

the

find the packing slip. Check the contents of the
box against the
packing
slip and
examine
each
item
for
damage.
Note missing or
damaged items on the installation report or
field service report.
At

completion

branch

this

field

phase.

manager

may

the

service

any

want

3.3

are

any

checkout

problems

damaged,

customer

branch

and

occurred

the

branch

insurance

file

field

that

service

manager

field

Wire

wrap

P.N.

29-18301

Wire

unwrapping

tool

(or

Tektronix
KLAD

Scope,

475

wire

tool,

Phillips

Regular

No.

gun),

AWG,

No.

Digital

screwdriver

oscilloscope

pack

digital

wrap

voltmeter

equivalent

service

should

EQUIPMENT NEEDED FOR INSTALLATION AND CHECKOUT
equipment is required for installation and
NIA20:

the

(100

For

get

checkout

AWG,

P.N.

during

claim.

following

items

the

missing
items,
the
short-ship request.

The

unpacking

manager

Digital

29-13513
MHz)

PROCEDURE

3.4

INSTALLATION

3.4.1

Preinstallation Checkout

Before performing the installation, verify that the configured
the
preclude
to
properly,
operating
1is
wuse
in
now
system
possibility of current system problems being ascribed to the NIA20
after

its

installation.

Remove all customer media, to minimize the possibility of
corrupting

customer

data.

Mount the supplied KLAD pack; bring up the diagnostic
monitor; and run the "B" string to verify that the system
is

working

properly.

the

system.

Power-down

Verify that the system has a M8532-YA board installed. If
a
with
M8532
installed
currently
the
replace
not,
M8532-YA.

RH20 positions 4 and 5 will be used for the NIA20., If
there is an RH20 in position 4, remove it. If there is an
RH20 in position 5, leave it installed temporarily and
perform diagnostic DFRHB to verify the reliability of the
backplane wiring. If there is no RH20 in position 5,
relocate a module from one of the other RH20 positions to
position

This
run diagnostic DFRHB.
Power-up the system and
is
5
position
RH20
of
wiring
verifies that the backplane
functional.
in

Power-down the system and

its original

position.

reinstall the RH20

Perform diagnostic DFRHB also in RH20 position 7, to
verify the reliability of existing backplane wiring in
RH20 positions 6 and 7, before implementing any NIAZ20
modifications.

8.
3.4.2

Power-down

original

the

system

and

reinstall

the

RH20

its

position.

Backplane Wire Adds

For the installation of the NIA20, 24 new wires must be added to
RH20 backplane positions 4 and 5. An examination of the RH20
backplane must be performed to confirm the physical addition of
the wire wraps listed in Table 3-3. A check column is included in
the table for the wire installer to record installation progress.

To prepare the wire adds, strip approximately 1 inch of insulation
from the wire to allow sufficient turns to be made on the wire
wrap post. After each wire is added, enter a check mark in the
blank space adjacent to the wire listing in Table 3-3.

3-8

Table

Signal

3-3

Name

NIA20

KL10-E Wire

Adds

From

To/From

Check
L

EBUS

D11

B1ON1

B13B1

EBUS

D12

B19B1

ClOL2

B13B2

B19B2

EBUS D13
EBUS

PARITY

Cl0K?2

B13Ul

Cl0T2

Cl3B1

B19Ul

Cl9B1

EBUS

PIOO

EBUS

Cl2H2

PARITY

C1l3N1

ACTIVE

- C19N1

Cl1l2L1

Cl3B2

Cl9B2

Cl4H2

A15R2

Cl4Fl

F15A1

Al4J2

Al15E1l

Cl4p1

Al5D2

MPR7

MWBUSCTLFLDO1

MPR7

MWMGCFLDOS8

MPR7

MWTIMEFLD

CBI1

CLK2

CBI2

CLK4

CBI2

CCCHANERR

MPR7

MWBUSCTLFLDOl

MPR7
MPR7

MWMGCFLDOS8 H
MWTIMEFLD H

CBIl

CLK2

CBI2 CLK4
CBI2

Cl4K?2

A15S2

B14J1

B15A1

C20H2

A21R2

C20F1
A20J2

F21A1l
A21E1l

C20P1

CCCHANERR

T
T

T
o

A21D2

C20K?2

A21S2

B20J1

B21Al

T
_

assure the reliability of the new wiring, an ohmmeter
each new wire add should be performed by a person other
wire installer.
:

3.4.3

Installation

Protective

backing

cover

gold

Port

placed

check

than

the

Modules
on

the lower third non-component side
of each port module and the upper third of the non-component side
of
the M3002.
As
the modules
are
inserted
and/or
removed,
the
protective
backing
protects
the
MBus
and
PLI
bus
cables.
The
protective
backing
should
not
interfere
with
the
card
guide
or
the

modules
1.

Connect

orient
cable
2.,

finger

contacts

the

follows:

module.

Insert

the

port

MBus

cable, Digital P.N.
7019270-1J.
Be sure to
cable so that the flat wire comes out of the
header away from the board, as shown in Figure 3-3.

the

Insert
the M3001
EBus
interface/port ALU module
in
the
rightmost
slot
of
RH20
position
number
5
(slot
19,
looking at the backplane from the module side). The arrow
on cable should
be aligned with the arrow.on the board

connector,.

Connect the MBus cable to the
module as shown in Figure 3-3.

M3002

Insert

Module

installed

M3001

M3002
as

shown

slot
in

Port
'

Figure

to
3-3.

the

microprocessor

1left

the

Connect the MBus cable to the M3003 module as shown 1in
3-3.

Figure

Install the M3003 CBus/PLI interface module in slot 21,
which is located to the left of the installed M3002.
P.N.
Digital
assembly,
blank
module
the
Install
7019266-00, in RH20 position 4, slot 22. This assembly
blocks slots 22, 23, and 24. It prevents modules from
being inserted into RH20 position 4 and provides a baffle
for

system cabinet airflow.

Perform

PT17U0

ohmmeter

check

between

cable

into

the module

verify that there are no shorts to ground.

MBus

ground

assembly

and

blank

Fold

the

10.

the module door.

11.

decal,
utilization
module
self-sticking
the
Attach
panel.
baffle
rear
Digital P.N.”3622344-02, on the upper

12,

Power—-up

13.

3-3.

the KL1O.

Readjust the existing +5 V power supply to 5.0 + 0.25 V.
This adjustment is located on H7420 number 1 in H744
number 4. The location of this regulator is farthest away
from the circuit breaker. The voltage is monitored at
+5H,

14,

Figure

shown

between

PT17U

and ground.

Type MR (CR) with KLDCP loaded and running, then type FX1
(CR) in response to the command prompt, as shown below:
>.

FX1

(CR)

(or
the port modules using a Tektronix 475
ng
performi
equivalent 100 MHz minimum) oscilloscope by

15. De-skew

the steps given in Figures 3-4 and 3-5.

16.

Connect channel 1 of the oscilloscope to MTR MBOX CLK
4D33P1, on the CPU backplane. Use a ground clip.

17.

Set

18.

Set channel

the

ground

level

base

time

vertical

reference

the

to 20

ns.

gain to

1.3

oscilloscope.

0.5 V/division.

Set

the

ECL

above
(MTR

the

MBOX

horizontal
CLK

~signal.)
19.

Set the oscilloscope sync to positive external.
3-10

center

oT
T
ITET

50:_nV

[

EAREE!

——

—Q

EXTERNAL SYNC
(CHTOH, 4BO9K1)

EXTERNAL SYNC (CHTO H)

Timing.

Sync

(CHTO

TTT

CHANNEL 2
(EBUS CLK L. 2A21F1)

CHANNEL
1

TN
T

(NP

—

MTR MBOX CLK,
(4D33P1)

[=}

F =

50mV

> nl

PR3
e b oy s ETi1 e

——

External

De-skew

NIA20

3-4

> ar.m

Figure

EBUS CKL L AND MTR MBOX CLK
MR-9846

Figure

3-5

20.

Connect

21.

Connect

NIA20

De-skew

Timing.

EBUS

CLK

external sync input to CHTO H, 4B09K1
backplane (Figure 3-4). Use a ground clip.

and

MTR

MBOX

the

CPU

channel 2 to CDS1, EBUS CLK L,
2A21Fl1 on the I/O
backplane.
Set
the
channel
2
vertical
gain
to
0.5
V/division. Use
a ground clip. To measure TTL voltages,
set
the ground
reference
to
1.5 V below the horizontal
center

line

the

oscilloscope.

3-11

CLK

22. Press the trigger view switch of the oscilloscope and
display the external sync. Adjust the display, so that
the rising edge of the external sync aligns with the
vertical center line of the oscilloscope.

23. Display MBOX CLK H, channel 1. Identify the rising edge
of MBOX CLK H that occurs prior to the vertical center
line of the oscilloscope. Display channel 1 and channel
'

24. Put

the KL10-E

the

override

fault

state.

1/0 rear door to access the I/0 backplane.

25. Locate

the bottom
e e
s

ézf//TEBSSQY#WEfi"slot

potentiometer

the

I/O

the

Remove

clock

backplane.

the

module

Using

this

potentiometer, adjust the falling edge of channel 2, EBUS

%fi&M

-2 15
26.

CLK L so that it crosses the rising edge of MBOX CLK H.

This crossing occurs on the horizontal center line of the
oscilloscope.

Disconnect all

probes.

27. Mount the KLAD pack on the front end RPO06.

©proper
verify
to
DFPTA
diagnostic
run
and
28. Load
fail,
modules
the
If
modules.
port
the
of
functioning
the
1If
diagnostic.
the
by
directed
as
t
troubleshoo
the
continue with
properly,
functioning
are
modules
installation.

Power Supply Regulator Installation

3.4.4

Three H7420 power supplies are located on the I/O cabinet side
wall as shown in Figure 3-1. The H7440 regulator to be added is
This
location.
supply
©power
H7420
upper
the
1in
installed
card
NIA20
the
support
to
required
is
additional +5 V regulator
cage and is installed as follows

(see Figure 3-6):

Remove the spare slot filler panel from slot 5 of the
H7420 number 1 power supply. Save all existing hardware.

Take the new H7440 regulator from the kit and install the

on
H7440 in slot 5 of H7420 number 1, using two screws
may
systems
top and one thumbscrew at the bottom. (Some
/
use H744 or H7440 regqulators.)

PT?7

PT8

'15 PIN CONNECTOR

T 177

DC HARNESS

H744 1 H744 | H744 | H744

|H7440

+5K | 64

[|+5

+5H

| —6F

T
MHA-13692

Figure

3-6

H7420

Installation

Power

NIA20

Card

Supply

Cage/Internal

Cable

NOTES

2.,

When

CI20

installed, the NIA20
shown in Figure 3-1.

is mounted

1If

cabinet

the

CPU

side panel cannot
removed, the current limiter (see
Section 3.4.5.1)
should be installed
before the card cage to avoid making
the location inaccessible.

install

internal

the

NIA20

card

NIA20

cage

shown

Figure

3-7

and

1Install

the

two

NIA20

mounting

brackets

shown

3-80
a.

Remove

and

reposition

right-side

frame

any

member

tie-wrapped

the

from
the
front)
to
accommodate
brackets and card cage.

the

cable:

1Install

total

P.N.

9007786-00,

the

CPU

cabinet

U-nuts
the

the

(viewed

NIA20

mounting

(Tinnerman
from

from

cabinet

the

right-side

(viewed

cables

CPU

Figure

nuts),

Digital

frame

members

the

front)

in
preparation for NIA20
card cage and current limiter
installation.
Insert
the Tinnerman nuts
into
frame
holes 5,
11,
15, and 52 on each vertical side frame
member
counting
up
from
the
bottom
of
the
cabinet
(see
Figure
3-8).
Four
Tinnerman
nuts
are
inserted
into each vertical side frame member.

TOP

o} |

e
O

"O—

|Bl|=

WW BN

.
o

REAR

FRONT

L.
o

[

CABLE
STRAIN

RELIEF—»

oz =
_E__'-;__‘J

d'_::‘_v

®)

===

REAR VIEW

SIDE VIEW

FRONT VIEW
MR-13693

Figure

3-7

NIA20

Card

Cage

Views

r\f

REAR

CONNECTOR PANELS

KL10-E
RIGHT-SIDE

CPU CABINET
(FRONT VIEW)

————— HOLE 52

N)---4

€120

) _-&0

CARD CAGE

NIA20
CARD CAGE

HOLE 52

MOUNTING
BRACKETS

)
0

/
0

)

(=)

]

{

)

NS | @

HOLE 15

ELARZI-S()ENT

T OMITER
'

HOLE 11

;

INTERFACE

BRACKET

HOLE &

MR-13694

Figure

Use

3-8

four

screws,

NIA20

10/32

Digital

Card

Cage

one-half

inch

Phillips

P.N.

lockwashers, Digital
side of the frame.
Locate

the

rear

Because

NIA20

9006073-01

P.N.

internal

left-side

and

9007651-00

cable

NIA20

KL10-E

strain

card

cage

panhead

four

No.

each

relief

(see

machine

star

vertical

(white)

Figure

3-7).

of the inaccessibility of this strain
relief once
the card cage
is mounted,
the
internal cable
is
routed
through it before installing the card cage.

Locate the three-foot

internal NIA20 cable, Digital P.N.

7019893-2L,

Prepare the 1internal NIA20 cable for installation by
positioning a stick mount on the right-side frame member
of the CPU cabinet (viewed from the front), above the
reserved CI20 connectors on the bracket interface (see
Figure

3-9).

7019893-2L
INTERNAL CABLE
J1

CONNECTOR
BNE3

CONNECTOR
(ETHERNET
TRANSCEIVER)
STICK
MOUNT
LOCATION

HOLE 11
BRACKET

INTERFACE

7428312-01

HOLE 5

J/o

N €120
CONNECTORS

NIA20
CURRENT
LIMITER

5415695-01

r——‘

KL10-E CPU CABINET

MR-13695

(REAR VIEW)

Figure 3-9

NIA20 Current Limiter

Route the three-foot internal NIA20 cable through the
white plastic strain relief on the NIA20 card cage. Allow
enough slack to connect the internal cable to the NIAZ20
card cage backplane and tighten the strain relief.
Connect the internal NIA20 cable to the J4 connector (see
Figure 3-7) on the rear of the NIA20 card cage and route
the cable as shown in Figure 3-1. The cable connector
engages a detent when properly seated.

Mount

the
NIA20
card
cage
on
the
brackets
(see Figure 3-8),
using a

two
NIA20
mounting
total of four 10/32

screws,
external
lockwashers,
and flat washers
in frame
- holes 15 and 52. Hang the NIA20 card cage on the top two
screws; then install the bottom two screws.

Install
3-7).
a.

the

Install

frame

NIA20

card

Tinnerman

member

cage

nut

the

ground

CPU

hole

cable

cabinet

(see

Figure

the

left

side

(viewed

from

the

rear).

c.
9.

Connect
the
ground
member (viewed
from
and using
cable.

Attach

ground

closest

cable
on
the
rear)

starwasher

hole

label,

the
1left-side
by inserting a

each

side

Digital

P.N.

the

frame
screw
ground

3613272-00,

Run the internal NIA20 cable to the previously positioned
stick mount and
insert
its other
end
into
the
rear Jl
connector of the NIA20 current limiter.

3.4.5.1
Installation
of
NIA20
Current
Limiter
-The
NIA20
current
limiter, Digital P.N.
5415695-01
is preinstalled on the
bracket
interface,
Digital
P.N.
7428312-01],
as
shown
in
Figure
3-9.
The
bracket
interface,
NIA20
internal
cable,
and
BNE3
external cable are installed at the site as follows:
l.

Locate

the

bracket

interface,

which

1is

located

the
1lower
right-side
frame holes
5
and
11
of
the CPU
cabinet
(viewed
from
the
front).
Four
10/32
screws,
external
lockwashers,
and
flat
washers
are
used
to
install the bracket interface.
‘
2.

Connect the internal cable to the rear Jl1 connector and
also
connect
the
BNE3
external
(Ethernet
transceiver)
cable
to
the
front
Pl connector
located on
the
NIA20
current limiter (see Figure 3-9).
’

Vane

Direct

3.4.5.2
Harness
installed:

Installation

current

switch

power

-- The

harness

cable

following

(two

harnesses

sections)
N

Direct current voltage monitor cables
Fan alternating current cable and power
PLI bus
External

BNE3

NIA20

cable

cord

are

interconnections.

The harnesses are

installed as

from

edges.

+5 V CABLE

J1 42

/ 7019272

JIF

NI CARD CAGE

SLOT SLOT SLOT
19
20
21

H7420
P1 11 |POWER

SUPPLY

, 112]314|5

H7440

DC VOLTAGE
MONITOR

Ji| Pt

l—l
POINT 6

V CABLE
+6
7019273

J8|

g 9

DC VOLTAGE MONITOR

J1 P1
{D

/
DC VOLTAGE MONITOR

CABLE 7020362

RH20 DTE

p2|J5
{

TARA YA J3 MTTPLICABLE

- ? MODULE M3003-J2
BCOBR-8

P1{J2

FROM CBUS

]

BACKPLANE

151 424 |P2

VANE SWITCH CABLE

3
-5.2H

(P2

CARD CAGE

P3| J1

cPU

{

SECTION #1 7021448

TM8

J1}

«cable

follows:

Install tie wraps approximately eight inches apart on all
harnesses.
When
routing
<cables
close
to
internal
assemblies, use spiral wire-wrap to protect the cables

and

harness

the

shows

3-10

Fiqure

diagram

The

7019862

P1 41

SEE TABLE 3-3

FOR POINT TO POINT

N 7019270

M-BUS CABLE

POWER CORD

9107673 OR 7011432
861

SWITCHED OUTLET

AC FAN CABLE

7019274 OR 7020639

GND

'}
/O INTERFACE

7019893-2L.

Figure 3-10
2.

5415695-00

MR-13896

' NIA20 Harness and Cable Interconnection Diagram

Locate the dc power harness, Digital P.N. 7019272-00 and
and its black and blue
(see Figure 3-11),
7019273-00
wires labeled PT5 and PT6. Connect the black wire to =5.2
ground and the blue wire to -5.2H in the CPU cabinet (see
Figure

3-2).,

Locate and connect Pl of the dc power cable, Digital P.N.
into connector Jl1 of the NIA20 card cage
7019272-00,
backplane (see Figure 3-7). Next, connect P3 of of dc
power

cable

Connect

into J2

the NIA20

P2 of the 7019272-00

7019273-00

power

cable,

card

dc power

cage.

cable

to Jl

the

CPU CABINET

CARD

]

CAGE

7019272-00

P3 ON H7430

REDWIRE 12 = 5| wiRe sipg)

CONNECT

H7440
POWER “*

TOGETHER

REGULATOR

7019273-00

Figure

3-11

Power

Tie-wrap

the

new

harness

harnesses

and

route

this

Use

spiral

side

wrap

the

along

CPU

supplies.
Locate

the

power

cable

red

and

(see

white

Figure

Connect

the

Figure

3-6).

the

I/0

power

shown

Figure

3-1.

harness

where

contacts

member

the

wires

labeled

Disconnect

connect
of

7019273-00

previously

nearest

3-11).

supply H7420 number 1, then
and 4,
respectively,
on P3
P3 to the H7420.
|

J1l

existing
as

cable

the

frame

Cable

the

PT7

H7420

and
P3

PT7 and PT8
H7420. Then

PT8
atop

the

power

pins 3
reconnect

dc power cable to connector
installed
H7440
regulator
(see

Locate the vane switch cable, Digital P.N. 7019862-00,
(see Figure 3-12). Connect Pl of the vane switch cable to
connector J1 located on the NIA20 card cage (see Figure
3-7). Also, connect P3 of the vane switch cable to
connector J6 of the NIA20 card cage. Use stick mounts and
spiral wire-wrap as needed to route and protect the vane
switch

cable.

7019862-00

BACKPLANE

CPU

MA-13698

Figure

Vane Switch Cable

3-12

NOTE

short
the
1installed,
1is
CI20
a
When
P.N.
Digital
cable,
vane
switch
combined
a
in
used
is
7020488-00,
CI20/NIA20 installation. Consult the CI20
(Digital Order Number
reference manual
EK-CI20-RM-001) for other applicable CI20

installation procedures.

Remove the original KL CPU vane switch cable (P4) and
connect this to the NIA20 vane switch cable connector Jl.

10. Connect P2 of the vane switch cable to the original
CPU vane switch assembly (see Figures 3-1 and 3-13).

11. Overlay the CPU/NIA20 air £flow fault decal over the
existing CPU air fault message decal on the 863 fault
switch.

P.N.
Digital
cable,
monitor
voltage
dc
the
12. Locate
Connect P2 of the dc
3-14).
Figure
(see
7020352-00
voltage monitor cable to J5 on the NIA20 card cage and
connect the other cable end (Pl) into connector Jl on the
new dc voltage monitor

board.

VANE
SWITCH

CONNECTOR

P4
P——

BEFORE

VANE SWITCH CABLE

VANE
SWITCH

CONNECTOR

CPU
BACKPLANE

AFTER

Figure

13,

Locate

3-13

the

Vane

switches

Digital

MR-13899

Switch

Harness

the

Installation

voltage

monitor

board,

P.N.
5414506-01.
Only
switch
S1
should
be
ON,
while all other dc voltage monitor board switches should
be OFF.
14,

Insert

the
15,

Attach

16.

17.

the dc voltage monitor board
voltage monitor card cage.
the

monitor

indicate

the

monitor

board.

Connect

the

panel

slot

remaining

decal,

used

single

to
the

Tie-wrap

monitor

the

voltage

the

power

cable.

mounts

support

the

Use

the

Digital

P.N.

for

voltage
monitor
cable
existing orange wire on
+5L.

into

slot

3621501-02,

the

NIA20

voltage

orange

wire

the

a
location
adjacent
to
dc voltage monitor board

and

vane

switch

adhesive-backed

harness.

the
zone

harnesses

square

cable

CONNECT

7021448-5C

7020352-00

ADJACENT TO
ZONE +5L

DC VOLTAGE
MONITOR
BOARD
MR-13700

Figure

18.

Locate

the

Hz)

3-14

fan

DC Voltage Monitor

cable,

7020539-06

Digital

(240

Vac

Cable

P.N.

7019274-06

Hz),

and

the

(120

power

Vac

cord,

Digital
P.N.
9107673-06
(120 Vac
60
Hz)
or
7011432-02
(240 vac 50 Hz),
(see Figure 3-15). Connect the fan ac
cable connector P2 to connector J2 on the NIA20 card cage
and then join the fan ac cable to the power cord. Insert

the

other

switched

ground

end

the power

outlet

the

wire

the

cord

power

adjacent

NIA20
card
cage.
Use
electrical connection.

19.

861

into

any

controller.

side

ground

starwasher

available

Connect

screw
ensure

the

good

Install
a
Tinnerman
nut
in
hole
11 on
the
frame
and
attach the ground cable from the NIA20 card cage to the
frame.
Use two starwashers to ensure a good electrical
connection.

20.

Locate the cable support panel, Digital P.N. 7428311-00
(see Figure 3-1).
Install the smooth side of panel (used
to
support
the
cable
harnesses)
toward
the
rear
when
facing the CPU cabinet. Use four of each: Tinnerman nuts,
screws, flat washers, and lockwashers in holes 36 and 39.

CONNECT

FAN AC CABLE

7019274-06 (60 Hz)

GROUND

7020539-06 (50 Hz)

WIRE

POWER CORD

9107673-06 (60 Hz)
7011432-02 (50 Hz)

861 POWER

—

switchep < | lm’

CONTROLLER

OUTLET

Figure

21.

3-15

Fan AC

Cable

and

Power

Cord

Locate the PLI cable, Digital P.N. BCO6R-08
(see Figure
3-1
for
<cable
route
and
Figure
3-10
for
cable
connection). Connect one end of the PLI cable (identified
by a
red line imprinted on top of the cable)
to module
M3003 and
route through the cable strain relief on the
NIA20

card
cage.
The
other
end
of
the
PLI
cable
(identified
by
a
red
1line
imprinted
on
bottom
of
the
cable) to connector J3 on the NIA20 card cage (see Figure
3-7).
To
secure
the
PLI
cable,
install
adhesive
foam,

Digital
P.N.
1213716-00,
within
each
of
the
four
flat
cable clamps.
Install one cable clamp on the side of the
CPU card cage and three cable clamps across the rear of
cable support panel.
22.

Route

the

cables

shown

Figure

3-1.

23. Replace the CPU cabinet door.
3.4.6

Installation

of KL10

Adapter

Board

board,

Digital

P.N.

and

Blank

Assembly
The

KL10

module
NIA20

adapter

assembly,
card

cage

Digital

The
KL10
assembly

opening

P.N.
follows:
to

are

its

7014103-00,

L0072-00,
are

hinged-end

panel

door.

and

the

installed

NI
adapter
board
and
the
installed
into
the
NIA20

front

Module

blank
card

blank

the

module
cage

LEFT

Ryveur

3.4.7

(L0072-00)

the

(7014103-00)

1in

the

board

slot.

the

Install

adjacent

adapter

KL10

the

Install

w@ght-hand

slot

blank
to

module

assembly

theeiggg.

Checkout

The physical part of the installation is complete at this point.
All that remains is to verify that the system runs properly in the
Perform the following steps to verify the
new configuration.
installation.

Verify that the KL10-E

is no

longer

in the override

fault

state.

Power-up

Readjust the 5 V power supply to 5.0 + 0.25 V. This
adjustment is located on power supply H7420 number 1,
regulator H7440 slot 5 (see Figure 3-6). This regulator
is located nearest the H7420 power supply breaker. The
voltage
1is
monitored
at
the
black
and
red wires
on
connector Jl1 of the NIA20 card cage (see Figure 3-11).

Load and
execute

run diagnostic DFPTA for at least five passes

Load and run diagnostic DFNIE for at least five passes

Load and run diagnostic DFNIA for at least five passes
Enable

Run

mode.

execute

KL10-E.

mode.

execute

the

mode,

the

operating

diagnostics

system.

DFPTA

for

UETP

NIA20

least

five

passes

user

four

hours

mode.

Run
in

diagnostics
user

10.

Disable

the operating

11.

Remove

all

customer's

Transfer

for

least

field

service

system and

and

sign

system.

store

off

packs
in a

system

representative.

{

12.

test

mode.

and

secure

tapes

from

the

area.

customer's

authorized

CHAPTER

FUNCTIONAL

This

chapter

CBus,

and

sample

describes

PLI.

transmit

the

also

and

port

functions

provides

receive

performed

simplified

NIA

over

block

DESCRIPTION

the

EBus,

diagram

and

operations.

Detailed
descriptions
of
hardware
components,
register
formats,
microcode bit maps,
and
field descriptions,
if not part of the
descriptions
in
this
chapter,
are
found
in
Chapter
5,
Logic
Description.
Chapter
5 describes how the hardware and microcode
implement the port functions.

4.1

PORT

When

reset

port

and

that

the

can

STATES

reset

the

port

issued

microcode

the

running

program

port,

counter

the

hardware

set

zero

power-up,

self-check initialization code
(see Chapter 5)
executed.
This
guarantees
that
the
port
enters
a
well-defined state after the reset. All of the port registers
are
set
to
the
power-up state.
The
port
can
be
in one of
the
three
states:

uninitialized,

4.1.1

disabled,

enabled.

Uninitialized

The port
1is not
running -- the power-on state.
The port enters
this state after a power-up or a master reset. The port exits this
state only after valid microcode is loaded into the port and the

port
clocks
are
started.
Port
clocks
are
enabled
when
the
port.
.
driver
sets
the microprocessor
run bit
in
the
port control and®®
e1
status
register
(CSR32) .
If
the
port
and
microcode%*~
"
functioning, the port driver sets the disable bit (CSR30), tfihg%ng "

the port to put itself into the disabled state.
4.1.2
port

Disabled
running

The

process

command

o
is not accepting NI packets. The port will entries that do not involve transmitting angd.

but

queue

receiving
(that is,
local commands).
From the
the
disabled
state
1is
entered
when
the
microprocessor
run
and
disable
(CSR32
and
microcode

then

s@afi=‘é%

informs

the

port

driver

that

unitialized staté&,
port
driver
sets
CSR30).

The

has

itself

put

port

in
the disabled state by setting disable complete
(CSR12). From the
enabled state,
this
state
is entered by a command from the port
driver
to
enter
the disabled
state,
or when the port microcode
detects a nonrecoverable internal port hardware error.

4.1.3

Enabled

The

port

This

from

the

fully functional, processing commands and NI packets.
normal state for the port. This state
is entered only

the disabled state, when the port driver sets the enable bit
(CSR31).
The port microcode
informs the port driver that it has
put
itself
into
the
enabled
state
by
setting
enable
complete
(CSR13).

CONTROL AND STATUS REGISTER

4.2

The KL10 and the port microprocessor exchange control and status
information through the port CSR, which is a 36-bit register (see
Figure 4-1).

BIT

The

CSR

bits are

BIT DEFINITION

RD/WR

defined

BIT

in Table

4-1.

BIT DEFINITION

NO.

RD/WR

KL10 | PORT

kLo | porT| | no.

PORT PRESENT

CLEAR PORT

DIAG RQST CSR

DIAG TEST EBUF

RW | *

DIAG CSR CHNG

RIH

| H

DIAG GEN EBUS PE

RW | *

DIAG SEL LAR

RIW | *

03
04

RQST EXAM OR DEP

RIH

| R/S

DIAG SINGLE CYC

RIW | *

RQST INTERRUPT

R/H | RIS

SPARE

RIW | *

CRAM PARITY ERR

RC | H

EBUS PARITY ERR

wre|

MBUS ERROR

FREE QUEUE ERR

R/C

R/S

RIC

| R/S

DATA PATH ERR

CMD QUEUE AVAIL

rs | rc

RSP QUEUE AVAIL

R/IC

| R/S

IDLE

R/W

DISABLE COMPLETE

R/W

112

ENABLE COMPLETE

13
14

DISABLE

R/S | R/C
R/S

R/W

ENABLE

MPROC RUN

RAW | R/H

PIA 00

RIW | R

PORT ID CODE 01

PIA O1

RW |

PORT ID CODE 02

PIA 02

rRwW | R

=
=

C
S
H

=
=
=

| R/C

PORT ID CODE 00

g
R

NOT DEFINED
READABLE

WRITEABLE (SET OR CLEAR)
CLEARABLE ONLY
SETTABLE ONLY
HARDWARE CONTROLLED

MR-13775

Port Control and Status Register

Figure 4-1

The CSR is read/write interlocked to prevent the port and the KL10
from accessing it at the same time. When the port wants to access
the CSR, it executes a request CSR microprocessor command. If the

register is available, the interlock is asserted. If the CSR is
not available because the KL10 is currently accessing the register
with a CONI or a CONO, the interlock is not asserted until the
CONI or CONO function is complete. The port microprocessor waits
until the interlock is asserted before it attempts to access the
CSR. In the same way, if the port microprocessor is accessing the
CSR when the KL10 executes a CONI or CONO, the CONO/CONI waits
until

the

port

access

completed.

4-2

Table

Bit

Name

PORT

DIAG

4-1

Control

and

Status

Bit

Definitions

Definition
PRESENT

RQST

CSR

Indicates

the

installed

and

powered-up.

When

set,

that
CSR.

the
|

This

CHNG

this
port

KL10

that

diagnostic

has

the

bit

requested

port

indicates

access

the

diagnostic
bit
indicates
that
the
of the CSR have changed since it
last read by the port microprocessor.

contents

was

UNUSED

Not
or

RQST

EXAM

DEP

used
the

either

the

port

microprocessor

KL10.

Used by
an EBus

the

port

microprocessor

interrupt

or
deposit
immediately

function).
generates

level

request

Setting

(examine
this
bit

the

interrupt

request.

RQST

INTERRUPT

Used
an

07.
the
06

CRAM

PAR

ERR

the

EBus

port

microprocessor

interrupt

levels

to
01

request
through

Setting this bit immediately generates
interrupt request.

Indicates
error

set,

that

has

been

the

control

RAM

(CRAM)

parity

this

detected.

bit
microprocessor

port

immediately
halted
and
RQST
INTERRUPT
(CSR05)
1is set. A hardware nonvectored (40
+ 2n) interrupt will be forced. A CRAM PAR
ERR

may
be
forced
in
order
to
halt
the
port microprocessor at a specific location
(break
point).
The
port
microprocessor

MBUS

ERR

cannot

bit

cleared.

restarted

that

has

Indicates
been

turned

is,

than

one

(CSR32

than
at

set

the

set)

one

until

MBus

same

port

this

driver

time.

That

1logic

trying to drive the MBus at the same time.
If this bit is set the port microprocessor
is
immediately halted and RQST INTERRUPT
(CSR05)
is set. A hardware nonvectored (40
+
2n)
interrupt will be
forced.
The port

microprocessor cannot be restarted
set) until this bit is cleared.

4-3

(CSR32

Table

Control and Status Register Bit Definitions (Cont)

4-1

Bit

Name

Definition

UNUSED

Not
or

used
the

either

the

port

microprocessor

KL10O.

UNUSED

Not used by either
or the KL10.

the

port

UNUSED

Not used

the

port microprocessor

IDLE

the

Indicates that the port microprocessor is
in the idle loop, and is not hung in some
other

by either

KL10.

DISABLE COMPLETE

ENABLE

COMPLETE

microcode

Informs
the
microprocessor
disabled

state.

Informs

the

Not

UNUSED

16
17

PORT

CODE

either

Three-bit port
Informs

PORT

CODE

port

has

that

placed

the

itself

port

the

port microprocessor

KL10.

PORT

state.

used
the

KL10
that
the
port
has placed
itself
1in
the

KL10

microprocessor

enabled

routine.

identifier

software

and

Hard-wired

that

not

that:

this
00

code

field.

an NIA20

RH20
=

controller.

CLEAR

When set by the KL10, this bit resets the
port. The microprocessor is halted and all
pertinent registers and control logic are
placed
in a reset state.
The bit clears
itself
after
the
reset
function
is

PORT

completed.
19

DIAG

TEST

This

diagnostic bit enables the KL10 to do
an
EBus
interface
loopback
function
by
loading
and
reading
the
EBus
buffer
(EBUF). If the port is not running (CSR32
is reset) and this bit is set, a KL10O:

EBUF

DATAO loads EBus
places EBUF data
20

DIAG

GEN

EBUS

This
test
to

data into the
on the EBus;

diagnostic
bit
the EBus parity

decode

EBus

EBUF;

DATAI

enables
the KL10
checker by forcing

parity

error.

When

to
it

this

Table

Bit

4-1

Control

Name

and

Status

Bit

Definitions

(Cont)

Definition
bit
set

no
21

DIAG

SEL

set,
EBUS PAR ERR
(CSR24)
1is also
the
same CONO,
assuming
there was
real EBus parity error.
on

This

LAR

diagnostic

read

the

CRAM

bit enables a KL10 DATAI
address contained in the

latch

address register
(LAR).
If this bit
is set and bits 19 and 32 are reset, then
the
DATAI
causes
the
LAR
contents
to
be
asserted on EBus D0l1-Dl2.
22

DIAG

SINGLE

CYC

This
diagnostic
bit
enables
the
port
microprocessor
to
be
single
cycled.
1If
this
bit
is
set and the KL10
sets MPROC
RUN
(CSR32),
the
port
microprocessor
executes
one microcycle
and
halts.
MPROC
RUN
will
be
cleared
microprocessor halts.

The

current

fetched

address

from

(RAR). The

the

RAM

address

when

executed

address
to

the

executed

stored in the LAR at the completion of the
microcycle. The KL10 must read the address
from
the
LAR
and
load
it
into
the
RAR
before executing the next single cycle.
23

SPARE

EBUS

Reserved
PARITY

ERR

When

for

read

future

the

software

KL10,

this

use.

bit

indicates

that
an
EBus
parity
error
has
been
detected. When written as a 1 by the KL10,
this bit will clear itself and CRAM PARITY
ERR (CSRO06).
25

FREE

QUEUE

ERR

Used
that

by the
there

available
26

DATA

PATH

ERR

Informs

on
the

port
are

the

to inform
no
free

free

port

the port driver
queue
entries

queue.

driver

that

the

port

microprocessor
has
detected
an
error
the direct memory access data path.
27

CMD

RESP

QUEUE

AVAIL

Used
that

by the port driver to inform the port
it has placed a command queue entry

previously

Used

the

port

empty
to

command

inform

the

queue.
port

that
it
has
placed
an
entry
previously empty response queue,

driver

the

Control and Status Register Bit Definitions

Table 4-1
Bit

Name

Definition

UNUSED

Not
or

DISABLE

used
the

by either

the

(Cont)

port microprocessor

KL10.

Used by the port driver to tell the
to place itself in the disabled state

port
(set

CSR12).

ENABLE

Used by the port driver to tell the
to place itself in the enabled state

port
(set

CSR13).

MPROC RUN

When set by the KL10, this bit causes the
CRAM control register to reset and enables
the

port

microprocessor

clocks.

The

port

starts cycling at the address contained

the RAR. The next and subsequent addresses
will be fetched from the Am2910 sequencer.

33
34

PIAOO
PIAO1l

PIAO2

4.3

Three-bit KL10 EBus physical interrupt
assignment (PIA) field (PI level 01
through 07).

EBUS

The port EBus control logic arbitrates the EBus protocol and the
port microprocessor protocol
for
interfacing to the EBus,
and
performs
synchronization
between
the
two.
Figure
4-2
shows
EBus-to-port
interface.
Figure 4-3 shows the EBus signals and
EBus signals.

:\W
EBOX

RAR

MUX

IEI

N\\\]
ADR

EBUF

MBUS

KL1O

EBUS

MUX
////J

[92]

the

Table 4-2 describes

CRAM
_

MUX

CSR

NV
Figure 4-2

V
MR-13778

EBus-to-Port Simplified Block Diagram

ARV

EBUS

CS00-CS06 (CONTROLLER SELECT)

ROO-FO2 (FUNCTION)

D0O0-D35 (DATA)
DEMAND
4—————————ACK (ACKNOWLEDGE)

XFER (TRANSFER)

KL10 |
EBOX

PORT

P100-P107 (PRIORITY INTERRUPT)
RESET
DATA DISABLE
—>

CLOCK
——CLK—

DISTRIBUTION
MODULE

EE—
}—m
-

CLK
n

[
-——
>

Figure

Table

4-2

Signal

Direction

Cs00-Cs06

EBOX

port

4-3

EBus

Signals

Signal

Description

Description
Select
a

the

CONO,

CS04-CS06
during
a

port

CONI,

device
DATA®,

EBOX

port

Specify

during

DATAI.

specify the channel number
PI
SERVED
and
PI
ADR
IN.

CS00-CS03
select
the
physical number during
FOO-F02

code

the

EBus

port
by
its
PI ADR IN.

command

executed:

D00-D35

FO0--F02

Command

000

CONO

001

CONI

010
011

DATAO

100

DATAI
PI SERVED

101

ADR

Bidirectional

data

lines

Transfer
information
port.

control
between

and
the

status
and

EBOX

Table 4-2

EBus Signal Description (Cont)

Signal

Direction

Description

DEMAND

EBOX to port

Causes

ACK

Port to EBOX

Indicates the port has received and

the

executing

Port to EBOX

EBus

the

during PI

asserted

XFER

port

execute

command specified by FO00-FO02.

Indicates

command;

the

not

SERVED.

the port has executed the

EBus command;

not asserted during PI

SERVED.,

PIO0O-PIO7

Port to EBOX

Signals a port interrupt request by
PIA
the
asserting
assignment) loaded in
a

EBOX to port

DATA

CONO.

When

asserted,

disables

EBus

data

line.

Disables

DISABLE

channel
(PI
the port with

allow

drivers

diagnostic

1in

the

port

operations

transfer diagnostic data.

RESET

EBOX to port

Initializes the port.

CLK

EBOX to port

Clock source for the port.

The KL10 has full control of the port only when the
microprocessor is not running (MPROC RUN, CSR32 is reset).

port

With the port in this state, the primary functions of the KL10 are
to:

Load and read/verify the port microcode

Set up the correct initial CSR functions

Check for error conditions if the state of the port is due to
an,unexpected halt.

When the microprocessor is not running, the KL10 can also perform
diagnostic functions, such as write and read/verify the E buffer,
generate bad parity, and single-cycle the port. The KL10 performs
these functions by executing CONOs, CONIs, DATAOs, and DATAIs,
which are processed by the port. The specific functions are listed
in Table 4-3. For a more detailed description of CRAM, RAR, and
LAR,

see

Chapter

Table

Function

LOAD RAR

4-3

Load RAR.
=

EBus
MICROWORD

the

least

into

MICROWORD

the

DIAG

LAR

Read

the

port

RAR.

DATAO

contents

executes

port
of

the

SEL

LAR),

KL10

placed

bit

EBus

port

the

DATAI

are

EBus

are

CRAM

the

loaded

location

CSR21

the

(not

selected

half

(specified

placed

CRAM

from

RAR.

and

executes

the

loaded

the

location

RAR)

LAR.

with

the

contents

CRAM

the

(DIAG

LAR)

the

a DATAO with bit

address

executes

LAR),

the

executes
CRAM

significant bits
selected half of

KL10

SEL

contents

READ

Functions

port

into

KL10

the

the KL10

D01-D13

specified
READ

Diagnostic

Description

LOAD

KL10

the

EBus.

DATAI

and

address

the

CSR21

(contents

D01-D12.

LOAD

EBUF

Load
EBus Buffer.
If
the KL10 executes a DATAO
and CSR19 = 1
(DIAG TEST EBUF)
, EBus D00-D35 are
loaded into the EBUF.

READ

EBUF

Read

LOAD

CSR

READ

EBus

and

CSR19

the

EBUF

Load

CSR

TEST

placed

the

CSR

writable

CSR.

the

When the
the
KL10
commands.

(LOAD
Table

port
can

The

port

KL10

software

illegal
the

port

are

the

KL10

of all CSR
on the EBus.

bits

KL10

executes

EBUF),

the

DATAI

contents

EBus.

executes
loaded

into

CONO,

the

all

the

KL10.
executes

readable

CONI,

the

KL10

the

are

microprocessor
is
running
access
the
CSR
only
by

With

CSR and
4-3,

KL10

EBus

contents
placed

the

(DIAG

CSR.

bits

contents

Read

Buffer.

the

port

READ

CSR)

(MPROC RUN,
CSR32
set),
executing
CONO
or
CONI
in
this
state,
CONO
and
CONI
commands
operate according to the description
in

ignores

DATAO
and
DATAI
instructions,
executed
by the
while the port is running (CSR32 set), as unexpected
functions. Therefore, an EBus timeout will occur, because
does

DATAO

previous
function.

not

port

return

DATAI

examine

EBus

the

Transfer
KL10

deposit

(XFER).

microcode

request

However,
in

1is

execution

response

not

to
a
illegal

4.3.1

EBus

Interrupts

When the port is running, the port microprocessor controls the
EBus by loading an IOP function control word (IOP word) 1into the
EBus buffer and simultaneously generating an EBus interrupt. (The
IOP word is identical to port error word 1 and equivalent to the
(Figure 4-4 shows the format of the
API function control word.)
IOP word and Table 4-4 describes the bit functions.) The types of
interrupts that may be generated by the IOP word are listed by
function. The hardware can generate all of the interrupts, but the
port microcode currently uses only bits 0, 4, 5, and 7.

00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

ADR

SPACE

FUNC Q
1

DEV|CE

Figure

0 0
|

4-4

Table 4-4

S INTERRUPTADDRESS‘

]

IOP Function Control Word

I0OP Function Control Word

Bits

Name

Description

00-02

ADDR SPACE

The

address

location

space

addressed

containing

the

13-35,

bits

where:

0 = Executive process table (EPT)
1 = Executive virtual address space
4

Physical

memory

All other codes are reserved.

FUNC

Function requested by the interrupt,
‘

where:
Noyund
W
-=O

03-05

Standard
Not

used

Not
Not

used
used

Not

used

DATAO
DATAI

DATAO

+ 2n)

interrupt

(examine)
(deposit)

(examine

formerly

queue

interlocks.

the

and

increment).

reserved

This

enables

(40

NIA20

function

manipulate

A qualifier is interpreted according
to the function code, as follows:

Table

Bits

4-4

IOP

Function

Name

Control

Word

(Cont)

Description
Function

Interpretation

0,7

Ignored

4,5

and

apply

protection

relocation

address

specified

the

bits

14-35
07-10

DEVICE

Physical

the
11-12

12-35

INTERRUPT ADDRESS

The

device

address

handling
If

the

EBus
or

level

7),

interrupt

the

microprocessor

port

00.

PI
1level
processed
by

always

level 00 interrupts
can
1interrupts
on
processes

enable
If

the

port

examine

deposit

the

KL10

(as

highest

selectively

through

deposit

conditions

the

07.

requests

KL10

function

interrupt

CSR

33-35).

level

through

outline

before
2.

the

interrupt

on PI
requests
are

regardless

the

system.

interrupt

through

(function

interrupt

because
PI
or disabled as
Therefore,
the
KL10

the

request

the

priority),

EBus

Steps

interrupt

enabled

requests

bits

which

interrupt

and

requests

examine/deposit

cannot
levels

assigned

begins.

examine

disable

number

system.

the

port
07

microprocessor
(as

assigned

1in

sequence.

still

active,

the

port

waits

continuing.

The port then builds an IOP word and loads
it
into the
EBUF.
With
the
same
microword,
it
requests
either
a
standard interrupt or an examine or deposit interrupt.

Examine
The

deposit

basic

examine

IOP

and

interrupt

words

deposit

(function

The

(40

IOP

word

request.

RQST

assert

the

port

the

interrupt

are

predefined

interrupt

1is

all
PI

for

(CSRO5)

request

line

(PIA00-PIAO02,

4-11

7):

address)
in

the

for
port

OR
DEP
(CSR04)
1is
set,
PI request line PIO0O.

(function

=zeros

INTERRUPT

level

(less

2n)

EBus

requests

local
storage
RAM.
RQST
EXAM
causing the port to assert EBus
Standard

0):

standard

set,

causing

(PI0l-PIO7)

CSR

bits

interrupt
the

port

specified

33-35).

EBOX

KL10

the

When

The

port

SERVED

The

responds

channel
(4)

port

number

EBus

after

responds

EBus

CS04-CS06

F00-FO02

delay determined

asserting

the

by the KL1O.

EBus

data

line

corresponding to the port physical device number
(EBus
D07 for RH20 position 7, the CI20 position; or EBus D05
for RH20 position 5, the NI port position.)

After

EBus

data

lines

and

negates

Next,

the

KL10

EBOX

asserts:

KL1l0-determined

channel

number

The

port

The

port physical

ADR

(5)

The

port

responds

EBus

ACKN

The

IOP

device
EBus

the

EBus

KL10

EBOX

reads

the

DEMAND.

EBus

number

CS04-CS06

EBus CS00-CS03

FO00-FO02

by asserting:

(acknowledge)

word

(previously

microprocessor)

EBus

delay,

after a KL1l0-determined delay.

EBus DEMAND,
7.

request

asserting

EBus DEMAND,

the Pl

recognizes

XFER,

after

loaded

on EBus D00-D35

into

EBUF

by the

port

a port-determined delay.

it strobes the data

When the KL10 EBOX detects EBus XFER,
from

the EBus data lines and negates EBus DEMAND.

The

trailing

edge

EBus

DEMAND

causes

the

port

negate EBus ACKN, EBus XFER, and the EBus data lines.

4.3.2

Examine/Deposit Request Response

sequence

is outlined

the
executes
and
word
IOP
the
decodes
microcode
KL10
The
appropriate function. If the IOP word specifies a port examine or
deposit request, then the first EBus cycle following the IOP word
read will be a DATAO or DATAI to the port. The examine/deposit
1.

The

KL10

in the

EBOX

following

asserts

A device code of
DATAO or

five steps:

DATAI

zero

(2 or

(000)
3)

4-12

on EBus CS00-CS06

on EBus FOO0-FO02

~ Data on the EBus data
DEMAND,

after

lines,
if a DATAO function

KL10-determined

The

port

responds

the

EBus

request

condition

asserting

delay.

EBus

microprocessor.. (Condition
in Chapter 5.)

code

codes

are

The

the

device

code

returned

zero,

not

the

port

device

port.

The

port

does

not

expects

DATAI

that

this

in response

and

examine

the

cycle

its

and asserting
flag
to the port
described in detail

KL10

code,

EBus

ACKN,

code,

response

DATAI,

the

EBus.

(It

data

into

the

response

from

After

When

the

DEMAND.

the

strobes

lines.

The

trailing

and
For

the

EBus

request

port

EBus

the

data

same

from

the

MBus

into

the

port

asserts

EBus

negates

EBus

delay,

was

XFER,

data

lines

(if

until

the

code,

EBus

XFER

deposit

the
in

does

reads

strobes

function

from

causes

the

was
EBus

port

condition

code,

function).

microcode
to

attempt
the

the

data

request

DATAI

port

order

not

detects

DEMAND
EBus

(DATAI),

responds

prevent

EBus

execute

negation

the

4.4
port

EBus

microprocessor

transfers

MBus.

EBus

functions,

previously

microprocessor

data
lines.
de-asserts
the

have

the

EBus

edge

condition

must

microprocessor

port

code.

The

the

port

the

ACKN,

EBus

examine/deposit

EBus

The

from

request.

onto

detects

function

(DATAO),

data

negate

EBOX

the

because

DATAO

deposit

EBUF.)

storage.

KL10

data

examine

DATAO,

EBus

port-determined

XFER.

the

microcycle,

the

loaded

internal

the

data

one

is
the

EBus DEMAND,
and
the
EBus
request
following:

places

data

does

code

either

Therefore,
as soon as the port senses
when
the
port
microprocessor
detects
condition

CS00-CS06

ignored

device

examine

EBus
is

the

time-outs.

additional
condition

CBUS
port

CBus

control

microprocessor

logic

protocol

arbitrates
for

the

starting

CBus
and

protocol

stopping

and

the

CBus,

and
performs
synchronization
between
the
CBus
and
the
port
mover/formatter. The CBus control
logic also generates the clock
timing for the port.
Figure 4-5 shows to CBus—-to-port interface,

Figure 4-6 shows the CBus, Table 4-5 describes the CBus signals,
Figure

4-7

shows

CBus

timing,

and

Table

4-6

describes

the

CBus

cycles.

MBOX

FMTR

MUX

BUF

KL10

MVR/

—{csurfe—

CBUF

BUF

ouT

—

CBus-to-Port Simplified Block Diagram

Figure 4-5

The CBus (channel bus) is a synchronous, high-speed, time-division
multiplexed, tristate data bus. It runs between the KL10 MBOX and
the channel devices (the port, in this case -- see Figure 4-6 and
Table 4-5). Each device on the CBus has a unique time slot. A CBus
data transfer has four cycles: select, request, wait, and data
(see Figure 4-7

and Table 4-6).

CBUS

»SEL O

» SEL 1

—= SEL 2
» SEL 3

SELn

» SEL 4

» SEL5

-»= SEL 6

— SEL 7
START
RESET

'PORT

READY

KL10

MBOX

REQUEST

DOO-D35 (DATA)
PAR LEFT (LEFT PARITY)
PAR RIGHT (RIGHT PARITY)

CTOM (CONTROLLER TO MEM)
>

LAST WORD
DONE

STORE
ERROR

MR-13780

Figure 4-6

CBus Signals

Table

4-5

Signal

Direction

SEL

One line from the MBOX
to each CBus device

0-7

CBus

Signals

Description

Continuosly
selects
a
different
one
of
eight
CBus
devices. Defines the start of

the four data transfer cycles
(select,
request, wait, data)
for the selected device.
START

Port

MBOX

Asserted
its

data

the

port

cycle)

(during
start

data
transfer.
The
port
asserts START during only one
data
cycle
of
the
data
transfer, and only if READY is
negated.
RESET

Port

MBOX

Asserted
the same
is

by
the
port
during
data cycle that START
asserted.
Causes
the MBOX

to:

Clear
the
data
buffers
associated with the port
Reset the command list pointer
associated
with
the
port
to
the
1initial
channel
control
word
Negate

all

the

port

status

and

data
lines
after
the
two
previous steps are completed.
READY

MBOX

port

Asserted by the MBOX
data cycle)
when
it

(during a
is ready

for a data transfer, and after
it
detects
START
from
the
port.
For
an
output
data

transfer,
the
MBOX
has
at
least
one
data
word
in
its
buffer before asserting READY.

READY
1is
negated
after
the
MBOX
senses
DONE
and
is
prepared to start another data

transfer.

negated

READY

errors.

also

Table
Signal

4-5

CBus Signals

(Cont)

Description

Direction

negated
and
asserted
The
only
apply
READY
of
states
is
READY
during data cycles.
is
it
said to be asserted when
cycles,
asserted during data
not
1is
it
when
negated
and
cycles.
data
asserted during
between
READY
of
state
The
pertinent.
not
is
cycles
data
REQUEST

Port

REQUEST

asserts

port

The

MBOX

if
request cycle
its
during
its CBus output buffer is full
(device read -- data input to
its CBus input
the KL10 and
(device write
empty
buffer is
the KL1lO).
from
-- data output

MBOX

The

has

assert

not

does

port
The
REQUEST if:

asserted

not

READY

The MBOX has

asserted ERROR

asserted
has
MBOX
The
WORD during the current

LAST
data

asserted
current

DONE
data

the

port

the

same

transfer

has
port
The
the
during
transfer.

device

For

the

trailing

read,

places data on the data lines
(during its data cycle), and
the MBOX strobes the lines at

cycle.
data
the
write,

edge

device
a
For
is
operation

reversed.

D00-D35

Bidirectional
lines

data

data
a
during
only
Vvalid
not
is
port
the
If
cycle.
requesting data from the KL10O,
the MBOX places zeros on the

data
data

lines

cycle.

during

the

port's

Table

4-5

CBus

Signals

(Cont)

Signal

Direction

Description

LAST

MBOX

Asserted

WORD

port

the

data

output

the

MBOX

cycle)

data

(during

only

transfers

same

for

the

time
the
last
data word
sent to the port. The port
does not assert REQUEST after
it detects LAST WORD.

DONE

Port

MBOX

Asserted

the

its data cycle
data
transfer.
not

assert

asserts

STORE

Port

MBOX

REQUEST

the

cycle,

data
to

the

STORE

port

channel

status

and

the

port

the

data

cycle)

port

terminate

the

data

transfer
detected
senses

the

terminated

port-detected

that

MBOX

area.

when

port

Asserted

port

assigned

microcode

STORE

asserted.

with

status

logout

asserted

specifies

MBOX

(during

together

transfer

because

ERROR

after

channel's

and

current

the

store

reset

error

during

DONE.

Asserted

DONE)

port

to terminate a
The
port
does

MBOX

(during

tell

the

current

because
error.

When

the

ERROR,

terminates the transfer by not
asserting
REQUEST,
and
asserting DONE in a subsequent

data

cycle.

KL10
MBOX

CLOCK S

SEL

CYCLE
REQUE ST

i I

J'j

CYCLE

CYCLE
DATA

CYCLE

WAIT

[

START

RESET

CTOM

READY
REQUE

DATA

I L

[

LAST

WORD
DONE

STORE

la——START UP

DATA TRANSFER ————-.lfl——TERMINATION—————-D‘
MR-13781

Figure

4-7

Table 4-6

Cycle

Description

SELECT

There

REQUEST

SEL

line

Cycles

for

each

time
when

slot
occurs.
The
port
its SEL line is active.

The

port

asserts

time

and

port

ignores

This

any

CBus

data

CBus

asserts

DATA

Operation

KL10

cycle

WAIT

CBus

for

port

has

make

this

CBus

data

dummy

cycle

for

device
the

CBus

REQUEST

the

ready

SELECT

the

when

control

during

detected

data

port

the
its

transfer.

CBus.

The

the

port's

logic

senses

entire

request

SEL

line

active

Otherwise,

the

transfer.

the

port.

does

not

execute

functions.

transferred

this

CBus

data

transfer

slot,
it 1s placed on the CBus data lines by either the
KL10
(output
data
transfer)
or
the
port
(input
data
transfer)
during
the
data
cycle
time.
Otherwise,
the
port ignores the data cycle.

The

port

executing

transfer
write
logic

microcode
a
to

prepares

start

the

CBus

data

start CBus microprocessor command.
For an
the KL10 memory,
the port microcode also

to
KL10
1latches

memory
microprocessor
command.
The
these
microprocessor
commands
until

4-18

channel

input data
executes a

CBus
they

control
can
be

executed

when

control

logic

line.

When

using

port

CBus

detects

the

asserted

the

slot

time

becomes

slot

available.

sensing

its

The

CBus

SEL

)

CBus
and

time

port

control

the

CBus

latched

1logic

READY

start

detects

line

CBus

the

port

CBus

SEL

starts

the

channel

command

negated,

microprocessor

assert

START

1line
by

CBus

and
CBus
RESET during
the
subsequent data cycle.
The CBus
control logic then clears the appropriate latches set by previous
port microprocessor commands.
If the transfer
is to KL10 memory,
the CBus control logic also uses the latched write to KL10 memory

microprocessor

command to assert CBus CTOM at this time. However,
does
not
clear the
latch
set
by
the
write
to
KL10
memory
microprocessor command until the data transfer is complete.

When

the

channel

CBus,

asserts

CBus

READY

After

receiving

CBus

READY,

REQUEST

during

(i.e.,

its

KL10)

request

ready

during
the

cycle

transfer

the

port

CBus

whenever

data

control

from the channel
channel accept a

data

over

the

cycle.
asserts

requires

data

CBus
word

(device write), or whenever it requires that the
data word
(device read). The words are asserted
on the CBus DATA lines during the port data cycle following
its
corresponding request cycle.

The

port

CBus

input

ready

buffer

to
is

transfer
empty,

data

full.
CBus

input

mover—-formatter)

CBus

buffer

with

whenever

output

its

buffer

the

CBus

emptied

input

microprocessor
when
the
port
available condition code and
is

(transferred

buffer

formatter

command

microprocessor
senses
the
CBus
prepared to accept data from the

CBus.

CBus

output

mover-formatter
output

buffer

senses

the

for

the

its

The

across

whenever

buffer
is
transferred

microprocessor

CBus

transfer

are

available

the

1loaded
to
it)

(the
with a

contents
formatter

of
to

the
CBus

command

when

the

port

microprocessor

condition

code

and

has

data

CBus.

available

When

the channel places the last word on the CBus during a device
write operation,
it asserts CBus LAST WORD. In response, the port
CBus control logic asserts the CBus last word condition code. When
the port microprocessor detects this condition code,
it responds

with

control
The

stop

CBus

logic

port

microprocessor
assert

CBus

command.

DONE

makes
no more
data
cycles.
CBus DONE causes the
CBus
READY
1is
negated
when
another data transfer.

during

This
the

causes
next

the

port

data

CBus

cycle.

requests
during
subsequent
request
channel to terminate
the operation.
the
channel
1is
prepared
to
begin

The

port

microprocessor

can

information microprocessor

also

execute

command with a

store

stop CBus

CBus

command

status

the

same microcycle. This causes the port CBus control logic to assert
CBus
STORE
along
with CBus DONE
on the next port data cycle.
Asserting CBus STORE and CBus DONE during
the same data cycle
forces
the
channel
to
store
channel
status
in
the channel's
assigned reset and status logout area.

The port microprocessor

executes both the stop CBus microprocessor

command

microprocessor

and

store

CBus

command,

causing

the

port

CBus control logic to assert CBus DONE and CBus STORE when it has
transferred all data over the CBus during a device read operation.
The port microprocessor also executes these commands during a read
or write when
it detects one of the
following
transfer
error
conditions (described in more detail in section 5.2):
CBus parity error
Mover/formatter parity
CBus channel error
PLI parity error.

The

port

makes.
no

check

data

requests

during

subsequent

request

cycles.

4.5

PLI

The port PLI control logic arbitrates the PLI protocol and the
port microprocessor protocol for accessing the PLI, and performs
synchronization
functions between the PLI and the CMVR module.

Figure
PLI

4-8

shows

the

PLI-to-port

interface and Table

4-7

shows

signals.

MVR/

FMTR

CBUF |—

MUX

PLI

“

MUX

PLI
IN

BUF

MR-13782

Figure 4-8

PLI-to-Port Simplified Block Diagram

the

Table 4-7
.

Signal
DATA

(7:0)

SELECT

PUFFP Ful)-RCVR ATTENTION
END

Signals

Direction
Port Link

Lines

<==>

—-———D

{-—-

TTL

ATTENTION

TTL

PLI/LINK

CONTROL

TRANSMIT

PARITY

RECEIVE

DATA

PARITY

INITIALIZE

PRANSMIP—STAPYS

interface

communications

——D

TTL

<K---

TTL

——>

TTL

-—>
K

provides

between

the

TTL

-—=>

TTL

— 8

TTL

RESETVER—SPAPYHS————lmme

PLI

TRI-ST
- TTL

===

CLOCK

The

Logic

FRAME

XMTR

PLI

the

port

means

and

the

for
NIA

data

transfers

occur.

The

a master/slave relationship with the NIA.
functions are controlled by the port.

All

data traffic

The

some

following

that

has

signal

descriptions

been

previously

not

Description,

contains

additional

4.5.1

Interface

Signals

The

PLI

4.5.2

interface
Data

signals

(7:0)

refer

defined.

has

and

PLI

circuitry
5,

Logic

information.)

are

shown

(Asserted

High)

These lines are used to transfer data
pass
control
and
status
information
PLI/link
control 1lines
determine
information being transferred.
4.5.3
Select (Asserted Low)
The select line must be asserted
transfers and control
functions.

logic

(Chapter

and

port

Table

to
to

the

4-7.

and from the NIA and to
and
from
the
NIA.
The
direction

the port to
line acts

This

and
'

type

execute all data
an enable for

the PLI/link control lines. The NIA provides a pullup resistor on
this signal so that,
if the port is not installed,
the NIA does
not respond to the floating control lines.

4.5.4
RCVR

Receiver
ATTENTION

Attention
a

PLI

(Asserted

signal

High)
the

port.

When

asserted,

indicates that the receive status register contains a valid status
on the next frame to be unloaded from the receive buffer. It also
signifies
that
the
frame buffer addresses are available on
the
used

buffer

list.

Receiver

attention

asserted

when

the

destination

address

the

frame
1is
equal
to
the address
stored
in the physical
address
register or the multicast bit is set in the destination address of
the frame. It is cleared by the reset receiver attention command
(explained

Section

4.5.7.8).

4.5.5
End of Frame (Asserted High)
END OF FRAME is a signal to the port (data mover). When asserted,
it indicates that the previous byte of data read from receive
memory was the last byte of the frame. End-of-frame signal timing
is the same as the data. The signal is asserted for one port clock
cycle.

4.5.6

Transmitter Attention

XMTR ATTENTION

(Asserted High)

is a signal to the port processor.

When asserted

indicates that the transmit status is available on the last frame
transmitted and that the transmit buffer is available for the next
frame to be loaded. Transmitter attention is cleared by the read
transmit

status

command.

4.5.7

PLI/Link

Control

(Asserted High)

Four PLI/link control 1lines originating at the port are used to
control
the
interface
activities
of
the
NIA.
Control
1lines,
denoted by asterisks,
utilize the data
1lines to pass auxilary
control information to the NIA. The SELECT line must be asserted
to make the control lines valid. The control lines are encoded as
shown

Table

4-8.

Table

4-8

Link

Control

Signals

Function
WT XMIT

PLI/Link Control
BUF*

1100

XMIT ACTION*
RD XMIT STATUS
RD REC BUF
RD REC STATUS
RD USED BUF LST
REC TO XMIT BUF

0110
1101
0010
1110
1011
0011

RESET REC ATT
ENABLE LINK CNTL*

0111
1000

DISABLE

1001

LINK

CNTL*

WT REC BUF ADRS*
WT FREE BUF LST*
CLR RCV BUF

0101
0100
0001

WT ADRS*
RD REG
WT REG*

Control

1lines

information

use

the

NIA,

data

1lines

1010
0000
1111

pass

auxiliary

control

4.5.7.1

Write

buffer

function

Transmit
causes

Buffer
the

(WT

data

XMIT

BUF)

presented

-on

The

write

the

data

transmit
lines

and

its associated parity bit to be written into the transmit buffer.
The
end-of-frame
bit
is
always
written
as
a
=zero.
The
buffer
address counter will be incremented at the end of each cycle in
which
the
1load
transmit
buffer
command
is
present.
The
1load
transmit buffer command is necessary for each byte transfer to the
NIA.

4.5.7.2
action

the

Transmit
command

state

commands

and

Action

(FOUR

set

four

port

data

bits

corresponding

Table

4-9

data

Command

Port
1

FRAME

RESET

BUF

ADRS

DEC

EOF

Command

XMIT

Transmit

FRAME

and
bit

Data

Group

whose

The

coding

Transmit Action

Name

XMIT

COMMAND)

commands

four

are

The

action

transmit

shown

BUF

DEC

ADRS

Command Group

Function

Frame

Informs

NIA

buffer;
transmit

also
clears
the
status register.

Transmit

Resets

Address

address

Transmit

Causes

the

EOF

Write

Transmit

End-of-Frame

transmit

the

address

Buffer

Flag

Causes
be

transmit

counter

transmit

counter

decremented
WT

frame

Buffer

Address

begin

stored

Reset

Buffer

4-9.

Bit

Name

Decrement

upon

action

Table

transmission

RESET

transmit

depends

one

buffer

bit

one

the transmit buffer at
current
address
of
transmit
counter.

count.

end-of-frame

written

buffer

into

the
the

address

4.5.7.3
Read Transmit Status (RD XMIT STATUS) -- This
enables the contents of the transmit status register onto
lines. The transmit attention signal
is cleared.
(The
status

4.5.7.4

Read

described

Receive

Buffer

Chapter

(RD

REC

function
the data
transmit

5.)

BUF)

This
function
enables
the
contents of
the
currently addressed
location
in
the
receive
buffer
onto
the data
lines.
The
read
address counter is incremented at the end of each cycle in which
this function is asserted. The parity bit for read data is passed
to the port with the data on the receive data parity line.

The
the

data is available from the receive
first byte received to the last byte

The
port must,
while
signal END OF FRAME to
has

been

buffer sequentially
received.

reading
the
receive
packet,
determine when the last byte

monitor
the
of the frame

read.

4.5.7.5
function

Read Receiver Status Register
(RD
enables the contents of the receive

the

lines.

data

from

REC STATUS) -status register

This
onto

NOTE

The
receive
attention
signal
asserted
in
order
to
obtain
receive
status.
The
contents

receive

status

Chapter

are

must
be
a
wvalid
of
the

described

4.5.7.6
Read Receive Memory Used Buffer Address List (RD USED BUF
LST) -- This command enables the first byte of the used buffer
address list onto the data lines. The list contains addresses of
data buffers used by the NIA during
provided to the port in the order that

frame reception.
They are
they were used by the NIA.

4.5.7.7
Transfer Byte from Receive Memory to the Transmit Buffer
(REC TO XMIT BUF) ~- This command causes the NIA to transfer one
byte of
data and
1its parity bit
from the currently addressed
location in receive memory to the currently addressed location in
the transmit buffer. Both address counters are incremented at the
end of each cycle when this command is executed.
4.5.7.8

Reset

Receive

Attention

(RESET

REC

ATT)

This

command

clears
the
receive
attention
signal.
When
this
function
Iis
executed, the current receive status is lost. If there is another
frame in the receive buffer,
the status for that frame will be
available when the receive attention signal is reasserted.
4.5.7.9
Enable
Link
Control/Disable
Link
Control
-These
functions
are
wused
to
enable
and
disable
certain
long-term
functions in the NIA. A particular control may be set by executing
ENABLE
LINK
CNTL
with
a
1
1in
the
data
1line
bit
position

4-24

corresponding

- to

that

executing

DISABLE

LINK

Transfers

with

4.5.7.10

Write

a.
0 in

Memory

Address

command

causes

into
is

the

14-bit

address.

4.5.7.11
causes

Write

the

bit

Memory
(WT

data

read

the

Free

Buffer

presented

have

proper

cleared

bit

the

address

effect.

List

(WT

the

data

lines

order

FREE

data

The

address

bits

are

BUF

lines

position.

Buffer
Read
Address
to
the
BUF
RD ADRS
REGISTER)
--

lower

may

the

read-receive-memory

All

data

control
1

REC

presented

buffer
the

position

Receive
the

with

any

with

receive

combined

control.
CNTL

written

buffer

address

counter

set

LST)

to
--

Read
This

form

0.
This

written

command
into

the

free buffer
memory that

list.
It
informs the NIA of free buffers
in receive
are available
(free)
to
store received data packets.
The NIA uses the buffer addresses in the order they were received
and combines them with the write-receive-memory address counter to
form a 14-bit address.

4.5.7.12
the

Clear

entire

Receive

free

Buffer

(CLR RCV BUF)

list,

used

buffer

This

command

clears

list,

and

receive

status

first in,
first out (FIFO). The command must be executed whenever
a free buffer
1list parity error is detected. After the execution
of this command, the free buffer list must be reloaded with buffer
entries.
4.5.7.13

Write

Address

(WT

ADRS

REG)

When

this

function is executed,
the data lines must contain the address of
the
register
or
buffer
to
be
accessed.
The
NIA will
save
the
address.
The
transfer
to
or
from
the
desired
register
will
be
executed when
the RD REG
or
the WT REG
command
is
given.
Table
4-10 lists the registers and buffers available through the address
register.

4.5.7.14

Read Register
(RD REG)
-- This function
of
the
register/buffer,
whose address
is stored
register, onto the data lines.

4.5.7.15 Write Register
pPlaced

onto

whose

address

4.5.8
0dd

the

data

(WT REG)

lines

stored

Transmit Parity

parity

calculated

-- This

function takes the data

and

writes

the

address

(0dd)
by

into

(TTL Asserted
the

places the data
in the address

the

High)

port

and transferred to the NIA
using this line. The NIA stores the parity as supplied and checks
parity when reading the buffer during a transmission.
4,5.9

Data
was

Receive Data Parity (0dd)
(TTL Asserted
being read from the receive buffer includes

generated

before

the

data

parity bit
1is conveyed
to
line and must be checked by

the
the

was

written

port via
port.

into

the

High)

parity

the

receive

bit

that

buffer.

This

data

parity

Table
ADRS

4-10

(HEX)

Address

Buffer

Access

REG

Table
RD

00 *

PHY

ADRS

REG

01*

PHY ADRS
PHY ADRS

REG
REG

1
2

X
X

02%

03%*
04%*
05%*
06

PHY ADRS REG
PHY ADRS REG
PHY ADRS REG
07

3
4
5

X
X
X
-

X
X

N/A
PHY

09
0A

PHY

ADRS

ROM

PHY

ADRS

ROM

PHY

ADRS

0cC

ROM

PHY ADRS

ROM

PHY

ROM

ADRS

ROM

ADRS

N/A

XMIT

11%*

BUF

REC MEMORY WT

TDR

REG

TDR

REG

14
15

The

COLLISION
THRU

enable

access

link

bit

addresses,

4.5.10

Clock

Timing

The

interface

operation.

The

165

ns,

the

(PLI

shown

-—

TEST

REG

link

control

-—

~—

must

equal

Bus)

requires

interface

these

NIA

REG

Write

clock

will

source

operate

Figure

with

from

the

port

minimum

for

cycle

its

period

4-9,

4,5.11
Initialize (TTL, Asserted High)
This signal from the port is used to initialize the NIA. A pullup
resistor will be provided on this signal so that,
if the port is
not
installed,
the NIA will not
interfere with the NI
bus.
The
initialize signal must be asserted during power-up.
4.5.12

Receive and Transmit Status
signals reflect the state of the receive and transmit status
registers. They are brought out to backplane pins on the NIA link
module. They are enabled with the receive and transmit attention
These

signals.
Chapter
status bits.
4.6

This
4-10

contains

detailed

description

SIMPLIFIED NIA BLOCK DESCRIPTION
section uses the simplified NIA block
to

transmit

give

frame

overview

and

receive

the

basic

frame.

NIA

diagram

the

eight

shown

Figure

functional

operations:

le—— 200NS MAX
165 NS MIN

PORT CLOCK

50 NS

."—— MIN

PORT TO NIA

]

—-I

45 NS

MIN

—»

_—H

|-— 30 NS MIN
MR-13783

Figure

4-9

Clock

Timing

The NIA module

is functionally divided into a transmit section and
a receive section, with a CRC function shared between the two. Not
all logic blocks discussed in the following transmit and receive
descriptions
are
shown on
the
simplified
block
diagram
(status
registers,
counters,
and address
buffers).
For
this discussion,
they
are
assumed.
Chapter
5
presents
the
detailed
NIA
block
diagram with,a description of each subblock.
4.6.1

Simplified

Transmit

The

port

initiates

and

conditions

Operation

transmit

function by setting the proper data
in the NIA and issuing a transmit command. It then
waits for the NIA to perform the transmission and assert Transmit
Attention,
which
alerts
the
port
to
read
the
transmit
status
register and take appropriate action.

Initially,

the port resets the transmit buffer address to zero,
using
the
RESET
TX
BUF ADRS
command.
The port then
loads
the
transmit buffer with 8~bit bytes and parity. The last word also
sets bit 10 (bit 10 = load last byte = end-of-frame).
1.

SELECT

enables

the

link

control

lines.

The command WT XMIT BUF (via PLI/link control
to be written
(7:0)
causes the data on 1lines
transmit

Each

buffer

after

writing

The

command WRITE

the

last

parity).

automatically

command

write

counter

(plus

lines)
in the

the

increments

address

byte.

EOF writes

the end-of-frame bit

location.

X-MIT

RETRY

STATE

§
PORT

A
X-MIT

BUFFER
2xx10

SERIALIZER

CONTROL

XMIT
PAIR
RCVR

PLI

JCHK

REG.S

BUS

’

PAIR

—

4000

ECL

]

COLLISION

XCVER

PAIR

RECEIVE

MEMORY

XCVR

DE-SERIALIZER

POWER

16K X 10

COAX

RECEIVE
STATE

MR-13784

Simplified NIA Block Diagram

Figure 4-10

initiates
port
the
loaded,
is
buffer
transmit
the
After
transmission by asserting the command XMIT ACTION on the PLI/link
control lines, along with XMIT FRAME on the data lines. This
command

1.
2.

Clears

the

status

conditions)

Resets

the

(actually

transmitted

transmit
transmit

-8

first)

status
buffer

allow

for

the

(last

counter

transmission
back

preamble,

zero,

which

Iis

Enables

the

NIA

transmit

the

idle

loop

and

waits

assert

XMIT

ATT.

frame

buffer.

The

port

the

transmission

and

process

commands

while

command

XMIT

Upon

now

enters
other

receiving

the

is free to transmit.
If
busy, the NIA defers and
transmit,

FRAME,

for

The

waiting

the

port

for

the

from

NIA

can

XMIT

NIA

the

transmit

perform

also

receive

ATT.

checks

see

carrier is present, meaning the wire
waits an additional 9.6 us. When free

is
to

the
NIA
will
start
by
reading
the
preamble
ROM.
The
ROM
bytes
are
read
out
in
parallel
and
serially
shifted
through
the
Manchester
encoder (not
shown,
but
in
the
emitter

8-bit

control

logic

Without

allowing

is sent,
shifted,

section)

transmit

transmitted

onto

the

wire.

gaps in the serial bit stream, when the preamble
transmit buffer contents are likewise read, serially
transmitted. This data also passes through the CRC

the
and

generator.

and

addition,

parity

checked

the

data

buffer.

out

When
the
end-of-frame
is
detected
(bit 10
set
in the
read
from
the
transmit
buffer),
the
32-bit
CRC
that
generated is serially appended and transmitted.

During

the

transmission,

monitered.

occurred,

the

collision
transmit

the

was

«collision

not

status

detected

bits

will

detect

and

the

last byte
was
being

«circuitry

other

indicate

is
problems

successful

transmission on the first attempt.
If a collision was detected,
normal
transmission
is stopped,
a
short
jam
is
transmitted,
and
the
retry circuitry
is
enabled.
Since
the data
is still
in the
buffer,
it is available for retransmission (after a short, random
delay). Again,
the transmit status bits indicate to the port the
action and conditions of the data transmission. After the frame
has been transmitted, the NIA looks for the heartbeat signal from
the transceiver. This signal
indicates that the collision detect
circuitry
is working
properly;
if a collision had occurred,
it
would have been detected.
After

the
operation.
the

frame
During

transmit

occurred,
contents

can

transmitted,
the
NIA
must
complete
the
transmission the NIA would have set bits in

status

either

~-- Link
transmitting.
RETRY

correct

inform

DEFER

TRANSMIT

1is
the

had

the

STATUS

port

defer

-—

to
specify
the
activities
that
faulty.
The transmit status register

with

The

the

following

terms:

existing

traffic

following

transmit

retry

given:
l.

Message

transmitted

first

attempt

(no

the

wire

before

statuses

collisions).

are

transmitted on second

attempt.

Message

iMessage transmitted at some attempt after the second.

Message

failed

transmit

TRANSMIT ON TOO LONG -- Transmitter was on
take to transmit the longest valid frame,
have

been

longer than it would
(asserted after 1536

transmitted).

FAILED

INPUT

COLLISION

due

collisions.

repeated

pytes

attempts,

heartbeat signal after

Transceiver

failed

frame was transmitted.

the

assert

TRANSMIT PARITY ERROR —-- NIA detected a parity error while reading
data from the transmit buffer (remainder of transmission aborted).

LATE COLLISION —-- A collision occurred after the slot time of the
transmission
and
attempted
retries
(no
elapsed
has
channel
aborted).

LOSS OF CARRIER -- Carrier not present on the channel throughout
the transmission or the carrier dropped during transmission (the
remainder of

retrys

are aborted).

The NIA completes its operations by asserting XMIT ATT to the
port. Upon receiving XMIT ATT, the port exits from the idle 1loop,
reads the transmit status register, and takes the appropriate

action as

indicated by the conditions given in the status bits.

Normally, the port builds a response and puts it on the response
queue to the port driver, Figure 4-11 shows the basic functions of
a transmit operation summarized in a sequence flow diagram.
Simplified Receive Operation

4.6.2

At startup, when the port initializes the NIA, it sets initial
conditions and returns to the idle 1loop. The NIA functions
independently, receiving incoming frames and notifying the port by
asserting RECEIVE ATTENTION. Initialization steps performed by the
port

include:

list

(FIFO)

Clear the used buffer

Load

Set up the receive memory organization (usually 32 bit by

Enable

free

the

buffer

used during NIA frame
512

byte

1list

(FIFO)

reception

with

addresses

buffers)

the

NIA

receive

frames

(via

1link

control

START

I LOAD XMIT BUFFEfl
[WAS IT LAST BYTE ? ]“————NO—’
YES

WT EOF

L AMIT FRAME

[XMITR ATTENTION ? I.——_ NO
YES

[ READ XMIT STATUS1
[

DONE

1
MR-13788

Figure

The

NIA

4-11

receive

detect

PLI

state

a
detected,

the

receiver

looks

the

start

The

for

carrier

Interface

machine

(activity)

rests

which

the

synchronizes

signal,

Transmit

the

idle

wire.

Flow Diagram

mode,

When

waiting

incoming preamble
consecutive ones.

and

the

two

carrier

receive

shift
deserializer
accepts
the
Manchester
decoded
bit stream and parallel-loads the data bytes
(including a
calculated parity bit)
into
the
receive memory buffer.
It
1loads
the
memory
at
the
buffer
address
supplied
from
the
next
free
buffer
1list
of
addresses.
It
also
compares
the
incoming
destination to
the
internal
address,
in
search of a match.
The
serial bit stream is also sent to the CRC generator/checker.

serial

match

address,

the

occurs,

and

frame

not

intended

discontinue writing
to the beginning of
the idle state.

1is

not

for

into receive memory,
the buffer, wait for

broadcast
this

node.

or
The

multicast

NIA will
reset the address counter
no-carrier, and return to

broadcast

match

condition

had

occurred,

multicast

address,

the

destination

NIA

must

address

load

the

was

entire

frame
1into
the
receive
memory
buffer.
Each
byte
1loaded
will
automatically
increment the write counter, which contains the 8
low-order bits of the 14 memory addressing bits.
When

buffer

received),

the

boundary

current

encountered

buffer

(i.e.,

address

(six

512

bytes

have

high-order

been

addressing

bits)
is transferred from the free buffer list to the used buffer
list. The next address from the free buffer list (FIFO) is used to
continue writing received bytes into memory.
When

the

last

incoming

detects the end of
following events:
l.

bit

signal

NIA writes
the
end
receive buffer location.

The

CRC

checker

CRC

was

calculated).

The

current

free

buffer

The

NIA

next
The

frame,

CRC

free

buffer

list

and

put

set

incoming
signal

the

status

receiver

the

indicates

The 8-bit receive
register (FIFO).

received,

The

activity

carrier

wire.

OK,

written

10,

(or

CRC

used

the

ATTENTION

the

ERROR

receive

removed

buffer

idle

circuit

initiates

bit

address

the

sense

This

mode

the

bad

status

from

the

await

the

list.

frame.

RECEIVE

asserted

and

sent

the

Port.

When

the

port

receives

RECEIVE

ATTENTION

exits

the

idle

1loop

and processes the frame. The first step is to read the contents of
the receive status register, which contains the receive conditions
as seen by the NIA during frame reception. The eight status bits
can indicate the following conditions:
l.

PACKET
FRAMING
multiple
of
8
boundary was in

ERROR
bits;
error.

-The
frame
did
the
CRC
value
at

FRAME

ERROR

than

OVERFLOW

the

longest

valid

CRC
ERROR
==
The
incoming frame.

FREE
BUFFER
LIST
completely store)

were

available

The

frame

<circuit

EMPTY

the

from

the

frame

(over

free

4-32

received

1536

contain
a
1last
byte

was

longer

bytes).

calculated

-- The
incoming

not
the

bad

CRC

the

NIA could
not store
(or
frame because no buffers

buffer

list.

BUFFER

USED

buffers

depending

BITS
0,1,
to
store

used
on

used

FREE

BUFFER

the

64/256,

receiving

and
the

frame

size

32/512,

LIST

frames

PARITY
due

2
-The
number
of
received
frame
(one

and

memory

receive
to
six,

organization

being

16/1024).

ERROR

corrupt

The

data

1link

from

has

the

stopped

free

buffer

list.
If

error

decide

example,

runt

port

starts

port

now

reading
The

exists,

read

frames

are

unloading

knows

the

port

the

(unload)

how

used

reads

takes

the

frame,

usually

the

many

buffer

the

port

memory

were

action.
It
may
discard
it
(for

simply

discarded).

receive

buffers

appropriate

With

buffer.

used

errors,

Notice

store

the

that

the

frame,

where

the

bits.

used

buffer

list

addresses

learn

frame
is
stored.
It
will
then
send
the
NIA
the
first
memory
address
1location
to
be
read
by
writing
the
address
into
the
receive memory read address register. The port will then execute a
read
receive
buffer
command
to
the
NIA.
Within
the
NIA,
the
receive

memory

buffer

contents

will

(7:0), parity on the separate parity
automatically postincremented.
The

port

out

port

data

address

lines

counter

512

bytes

have

been

read

512

bytes,

the

port

must

write the next buffer address pointer to the receive memory
address register before reading more received data bytes.

read

process

detected.

continues

and
so
on)
end-of-frame

manner

the

until

end-of-frame

this

After

This

continues

put

line;

(another

until
the
bit signals

512

end
of
the port

bytes

read,

update

pointer,

frame
bit
1is
detected.
The
that the previous read command

produced

the
1last
byte
of
the
frame.
Since
the
port
has
the
desired frame data,
it now writes the used buffer list addresses
to the free buffer list and resets receiver attention.

The

port/NIA

continue
packet

the
to

clock

operation

now

operation

building

driver.

The

NIA

the

multiplexed
the NIA can
port

receive
receive
port

between
write a
cycle.

complete,

the NIA and port.
word and the port

These

simultaneous

but

the

response

receive

port

must

pass

the

time

memory

During receive operations,
can read a word during one
operations

are

performed

different memory addresses and are independent. Also, in addition
to
the
error
and
status
detection
<circuitry,
the
following
diagnostic and reliability features are employed:
l.

The

port

can

transmit

transmitted

through

back

the

through

memory

the

buffer.

port.

the

1loopback

Manchester

The

data

frame.

Manchester
is

decoder
then

The

encoder
and

read

into

from

data

1is

and

looped

the

receive

the

buffer

The port can disable the CRC, which is used 1in the
loopback mode (where the CRC circuit is dedicated to the
receiliver).

The port can transmit with its own address as the
destination (or include itself in a group address). The
data is sent on the wire and received from the wire as in
(In this case, the port must make
normal operation.
allowances
explained

the

single

5.)

CRC

generator/checker,

The port can write data directly into the transmit buffer
or receive memory buffers and then read the buffers back
into

for

in Chapter

the

port.

The port can set promiscuous mode, which causes the
receiver to receive all frames, regardless of destination
address.

The port can set generate wrong parity on the data to be
written into the receive memory buffer to allow a check
of the parity check circuitry.

The port can read the time domain reflectometry register,

which is useful in locating defective sections of cable.

The port can enable or disable the heartbeat signal.

The port can enable the collision test register (only in
internal loopback mode) to force collisions and immediate
retries

Figure

4-12

summarized

(next slot

shows

the

time).

basic

functions

in a sequence flow diagram.

receive

operation

START

J
RCVR ATTENTION ?

I———‘NO

YES

READ RCV STATUS

RD USED BUF ADRS LST

UNLOAD FRAME ?

WT BUF ADRS TO REC MEN
ADRS REGISTER

YES

l
—|

READ RCV BUFFER

END OF FRAME ?

| NO

END OF BUF

YES

WT FRAME BUF
ADRS TO FREE

BUF LST

DISCARD LAST BYTE ?

RESET RCV ATTENTION j

[

DONE

j
MR-13786

Figure

4-12

PLI

Interface

Receive

Flow Diagram

CHAPTER

LOGIC

The

first

two

B WN
-~

the major
module:

These

sections

logic

M3001

EBus

M3002
M3003

port
CBus

L0072

Network

major

logic

accompanies

each

Section

5.3

these

this

elements

three

describe

port

the

function

modules

and

the

NIA

interface and port ALU module
microprocessor control module
interface and data mover module
Interconnect

elements

module

this

1logic

chapter

the

DESCRIPTION

are

Adapter

shown

(NIA)

the

describes

the

port

and

microcode.

module.

block

diagram

description.

chapter

elements

the

functions

that

performed

follows
the
organization of the port microcode, describing initial
ization and
the
idle loop, and the major functions performed out
of the idle
loop:
interrupts,
CSR
pocessing,
transmit
packet
processing,
receive packet processing, queue manipulation.

5.1

EBUS

5.1.1

Introduction

INTERFACE

This

module
provides
interface)
between the

accesses

this

commands.

interface

The

port

a
control
KL10 and the
by

microprocessor
decoded
functions

MWMGCFLD.

The

port

PORT ALU MODULE

microprocessor

components

control

and

accessed
control

by
and

DATAOQ,

the

DATAI,

accesses

the

and

The

Logic

Logic
to
support
functions.

the

status

(described

include

(CSR).

EBus

parity

and

the

The

port

parameters

microprocessor

from

one

port

the

CONI

start

the

EBus

end

CSR

pass

other

microprocessor

EMUX,

MBus,

and the EBus.
EBUF, and KMUX

1logic
required
to
support
the
including the EBus interrupt sequence

load

the

data path between the
This data path includes

and

interface

status

KL10

status

monitors

codes

EBus

CONO,

this

by
These
microprocessor
commands
microword
fields
MWBUSCTLFLD
and

The

status
interface
(EBus
microprocessor. The KL10

commands.

condition

port

executing

interface
by
sensing
Section 5.1.2).
primary

and

microprocessor

executing
are

AND

port

EBus

protocol,

other

diagnostic

microcode

generator/checker

various

loopback

and

In
addition
to
the
EBus
interface,
this
module
contains
the
arithmetic and logic unit (ALU) for the port microprocessor, and a
multiplexer (CNST MUX) used to enter various constants to the ALU
from

the

control

RAM

(CRAM).

5.1.2
EBus Control and Status Register
The CSR
is a
36-bit
register
used to pass control and status
information between the port microprocessor and the KL10. The CSR

bits

are

the

text

shown

Figure

following

BIT

the

BIT DEFINITION

NO.

5-1,

and

described

in Table

5-1,

table.

RD/WR

’

BIT

KL10

PORT

NO.

BIT DEFINITION

RD/WR
KL10

PORT

PORT PRESENT

CLEAR PORT

DIAG RQST CSR

DIAG TEST EBUF

R/W

DIAG CSR CHNG

R/H

DIAG GEN EBUS PE

R/W

DIAG SEL LAR

R/W

RQST EXAM OR DEP

R/H

R/S

DIAG SINGLE CYC

R/W

RQST INTERRUPT

R/H

R/S

SPARE

R/W

CRAM PARITY ERR

R/C

EBUS PARITY ERR

H/R/C|

R/H

MBUS ERROR

I{REE QUEUE ERR

R/C

“R/S

DATA PATH ERR

R/C

R/S

CMD QUEUE AVAIL

R/S

R/C

RSP QUEUE AVAIL

R/C

R/S

IDLE

R/W

DISABLE COMPLETE

R/W

DISABLE

R/S

R/C

ENABLE COMPLETE

R/W

ENABLE

R/S

R/C

MPROC RUN

R/W

R/H

PORT ID CODE 00

PIA 00

R/W

PORT ID CODE 01

PIA 01

R/W

PORT ID CODE 02

356

PIA 02

R/W

NOT DEFINED

R
w
C
S
H

READABLE
WRITEABLE (SET OR CLEAR)
CLEARABLE ONLY
SETTABLE ONLY
HARDWARE CONTROLLED

=
=
=
=

MR-13756

Figure

5-1

CSR

Bits

and

Table

5-1

CSR Bit Description

Bit Name
Number
PORT

Function

PRESENT

CSROO

Indicates

always

that

reads

the

port

this

bit

present.

The

KL10

1 if the port is
present
(installed
and powered-up).
The port
always reads this bit as 0.

DIAA RQST CSR
CSRO1

This diagnostic bit indicates the status of

CCRQSTCSR.
Set

By:

The

port

the

CSR

Cleared
Port

microprocessor

(asserting

requesting

access

MPRQSTCSR).

by:

microprocessor

reading

the

CSR

(asserting

Port microprocessor
MPLOADCSR)
.

writing

the

CSR

(asserting

KL10

(CSR18).

MPREADCSR)
.

setting

General

DIAG. CSR

CSRO2

CHNG

EBus

CLEAR
reset.

This

diagnostic
bit
indicates
that
contents
of the CSR have changed since it
last read by the port microprocessor.

Set

by:

KL10

writing
function).
Detection of an

Cleared
Port

the
was

the

CSR

(executing

EBUS

PARITY

ERROR

CONO

(CSR24

set).

by:

microprocessor

reading

the

CSR

(asserting

MPREADCSR)
.

KL10 setting
General EBus

CLEAR (CSR18).
reset.

UNUSED

Not

wused

CSRO3

the

KL10.

Used

EBus

interrupt

RQST

EXAM

CSR0O4

by either

the

port

the

port microprocessor

microprocessor

deposit
function). A
immediately generated

request

(examine

PI level 00 interrupt
when this bit is set.

1level

Table

Bit

5-1

CSR

Bit

Description

(Cont)

Name

Number

Function
Set

by:

Port
or

microprocessor

deposit

requesting

interrupt

level

EBus
00

examine

(asserting

MPEXORDEP)
.

Cleared

by:

Successful

completion

deposit
The

KL10

setting

General
RQST

INTERRUPT

CSRO5

Used
EBus
PI

EBus

the

examine

CLEAR

(CSR18).

reset.

the port microprocessor to request an
interrupt
on PI levels 01 through 07. A
level
01
through
07
interrupt
will be

immediately generated
Set

sequence.

when

bit

set.

by:

Port

microprocessor

requesting

interrupt

(asserting

MPRQSTINTR).

CRAM

PAR

ERR

MBUS

ERR

(CSRO7

Cleared

levels

(CSR06

EBus

through

set).

by:

Successful

completion

the

interrupt

sequence.

KL10

setting

General
CRAM

CSR06

PAR

ERR

CLEAR

EBus

Indicates

(CSR18).

reset.

that

detected,

If
microprocessor

CRAM

bit
is
immediately

(CSR05)

(40

interrupt

CRAM

2n)
PAR

ERR

set.

may

will

port microprocessor
(breakpoint).
port

(CSR32
Set

microprocessor

set)

has

set

the

until

this

halted

hardware

specific

CRAM

parity

halt

location

be
restarted
cleared.

by:

Detection

port
RQST

nonvectored

order

cannot

bit

and

been

forced.

forced

the

The

error

this

INTERRUPT

parity

error.

Table

5-1

CSR

Bit

Description

(Cont)

Bit Name
Number

Function

Cleared by:

KL10 writing a 1 in EBus PARITY ERR (CSR24).
KL10

setting

General
MBUS|

ERR

EBus

Indicates

CSRO7

been

than one
the MBus

CLEAR

(CSR18).

reset.

that

turned on

than

one

MBus

the same time.

set of port logic
at the same time.

driver

That

trying

has

is,

drive

If this bit is set, the port microprocessor is
immediately halted and RQST INTERRUPT
(CSRO0S5)
set.,
A
hardware
nonvectored
(40
+
2n)
interrupt will be forced.
The

port

(CSR32

until

Set

by:

The

detection

being

Cleared
The
_

microprocessor

set)

the

cannot

bit

same

than

restarted

cleared.

one

MBus

driver

time.

by:

KL10

General

this

setting
EBus

CLEAR

(CSR18).

reset.

UNUSED

Not

used

CSR08

the

KL10.

either

the

port

microprocessor

UNUSED
CSRO9

Not
the

used
KL10O.

either

the

port

microprocessor

UNUSED
CSR10

Not
the

wused
KL10O.

either

the

port

microprocessor

IDLE

Indicates

that

the

port microprocessor

CSR11

the

1loop,

and

other

1idle

microcode
routine.
troubleshooting
Set

Port

not

hung

Useful

for

by:

writing

the

bit.

some

debugging

in
and

Table 5-1

CSR Bit Description

(Cont)

Bit Name
Function

Number

Cleared

Port
KL10

writing
setting

General
DISABLE

COMPLETE

CSR12

Set

Port

COMPLETE

state.

the

bit,.

Port writing

the

bit.

KL10 setting
General EBus

CLEAR (CSR18).
reset.

by:

This
microcode(software)-defined
bit is used
by
the
port
to
inform
the
KL10 operating
system that the port microprocessor has placed
in

the

enabled

state,

by:
writing

the

bit.

Port writing

the

bit,

KL10

CLEAR

by:

setting

General

EBus

(CSR18).

reset.

Not used by either the port
microprocessor or the KL10O

UNUSED

CSR14
CODE

CSR15

CODE

CSR1l4

Bit 00 of the 3-bit PORT IDENT CODE field. The
KLL10 always reads this bit as a 0 if the port
is
present
(installed
and
powered-up).
The
port

disabled

Cleared

CSR16

the

Port

PORT

Set

reset.

writing

itself

PORT

EBus

by:

Cleared

ENABLE

a 0 in the bit.
CLEAR (CSR18).

This
microcode(software)-defined
bit is used
by
the
port
to
inform
the
KL10 operating
system that the port microprocessor has placed
itself

CSR13

by:

always

reads

this

bit

Bit 01 of the 3-bit PORT IDENT CODE field.
The KL10 always reads this bit as a 1 if the
port
is
present
(installed
and
powered-up).
The port always reads this bit as a 0.

Table

Bit

5-1

CSR

Bit

Description

the

3-bit

(Cont)

Name

Number
PORT

Function

CODE

CLEAR

Bit

KL10 always
is
present
port always

CSR17

When
set
port.
The
pertinent

PORT

CSR18

placed
Set

KL10

IDENT

CODE

field.

The

by
the
KL10,
microprocessor
registers
and
a

reset

this bit resets
is
halted and
control
logic

the
all
are

state.

by:

writing

Cleared

Bit

PORT

reads this bit as a 1 if the port
(installed
and
powered-up).
The
reads this bit as a 0.

the

bit.

after

the

by:

clears

itself

reset

function

completed.
DIAG

TEST

This diagnostic bit enables the
KL10 to do an
EBus
interface
1loopback
function by loading
and
reading
the
EBUF.
If
the
port
1is
not
running
(CSR32
1is
reset)
and
CSR19
is set,
then a KL10 DATAO loads EBus data
into
the
EBUF, and DATAI places EBUF data on the EBus.

EBUF

CSR19

Set

by:

KL10 writing a 1 in the bit.
Cleared

KL10

by:

writing

KL10 setting
General EBus
DIAG

CSR20

GEN

EBUS

the

bit,.

CLEAR (CSR18).
reset.

This
the

diagnostic
bit enables the KL10 to test
EBus
parity
checker
by
forcing
it to
decode
an EBus parity error. When this bit is
set,
EBUS
same CONO,
Set

KL10

PAR ERR (CSR24)
assuming no real

by:

writing

the

bit.

is also set on the
EBus parity error,

Table

CSR Bit Description

5-1

(Cont)

Bit Name

Function

Number

by:

Cleared

KL10
KL10

writing a 0 in the bit.
setting CLEAR (CSR18).

General
DIAG

SEL

EBus

bit enables the KL10 to read
diagnostic
This
the
latch address register (LAR). If this bit
is set, the port is not running (CSR32 reset),
and the DIAG TEST EBUF (CSR19) is reset,
then
a
KL10
DATAI
causes
the LAR contents to be

LAR

CSR21

asserted
bits are
Set

KL10

SINGLE

CYC

CSR22

on EBus bits
undefined.

D0l1-Dl12.

All

other

EBus

by:

writing

the

bit.

KL10 writing

the

bit.

KL10 setting
General EBus

CLEAR (CSR18).
reset.

Cleared

DIAG

reset,.

by:

This
diagnostic
bit
enables the port microprocessor to be single-cycled.
1If this bit is
set and the KL10 sets
MPROC RUN
(CSR32), the
port
microprocessor
will
execute one microcycle and halt.
MPROC RUN is cleared when the
microprocessor

halts.

The current address to be executed is fetched
from the RAM address register (RAR). The next
address to be executed is stored in the LAR at
the
completion of
the
microcycle.
The
KL10

must
into

read the address from the LAR and load it
the RAR before executing the next single

cycle.
NOTE

This
read

bit must
and write
Set

KL10

be reset for the KL1l0
the CRAM correctly.

by:

writing

5-8

the bit.

Table

5-1

"CSR

Bit

Description

(Cont)

Bit Name
Number

Function

Cleared

SPARE

CSR%B

by:

KL10 writing

a 0

KL10

CLEAR

setting

General

EBus

reset.

Reserved

for

future

Set

the bit.
(CSR18).

software

use.

by:

KL10 writing a l in the bit.
Cleared

by:

KL10

writing

KL10

setting

CLEAR

General
EBUS

PARITY

When

ERR

CSR24

EBus

read

an EBus
written

clear

ERR

bit.

reset.

bit

indicates

that

detected.
this
bit

When
will

the

and

KL10,

CRAM

this

PARITY

ERR

(CSR06).

by:

The

detection
of
an EBus parity error
port is reading data from the EBus.

KL10

while

by:

writing

KL10 setting
General EBus
FREE
- QUEUE

the

(CSR18).

parity error has been
as
a
1
by
the
KL10,

itself

Cleared

CSR25

Set

the

bit.

CLEAR (CSR18).
reset.

This
microcode(software)-defined
bit is used
by the port to inform the port driver software
that

there

on the
queue.

are

free

queue

message free queue
The state of this

function.
Set
Port

by:
writing

the

entries

available

or the datagram free
bit has no hardware

bit.

Table

5-1

CSR Bit

Description

(Cont)

Bit Name
Number

Function
Cleared
KL10

writing

KL10

setting

CLEAR

General
DATA

PATH

ERR

CSR26

by:

EBus

the

bit,.

(CSR18).

reset.

This
microcode(software)~-defined
bit is used
by the port to inform the port driver software
that it has detected an error in the DMA data
path
(including
the
mover/formatter).
The
state of this bit has no hardware function.
Set
Port

by:
writing

Cleared
KL10
KL10

CMD

QUEUE

AVAIL

CSR27

This

KL10

the

bit.

EBus

a 1 in the bit.
CLEAR (CSR18).
reset,

microcode(software)~-defined

bit

used

by:
writing

Cleared

QUEUE

AVAIL

Port

writing

setting

CLEAR

This

the

bit.

the

bit.

by:

KL10

General

CSR28

by the port driver software to inform the port
that it has placed a command queue entry on a
previously empty command queue. The state of
this bit has no hardware function.
Set

RESP

by:

writing
setting

General

EBus

(CSR18).

reset.

microcode(software)~defined

by the port
that
it has

bit

the previously empty response queue. The
of this bit has no hardware function.
Set

Port

by:

writing

used

to
inform the port driver sofware
placed a
response queue entry on

the

bit.

state

Table

5-1

CSR

Bit

Description

(Cont)

L
4

Bit

Name

Number

Function
Cleared by:

KL10

writing

KL10

setting

CLEAR

General

reset.

either

Not

used

CSR29

the

KL10,.

DISABLE

This

CSR30

bit.

(CSR18).

EBus

UNUSED

the

port

microprocessor

microcode(software)-defined

the

port

driver

software

to
place
itself
in
the
disabled
CSR12). The state of this bit has
function.
Set

bit

tell

used

the

port

state
(set
no hardware

by:

KL10

writing

the

bit.

Port writing

the

bit.

KL10

CLEAR

Cleared

by:

setting

General

EBus

ENABLE

This

CSR31

the

place

KL10

reset.

microcode(software)-defined
port

driver

1itself

CSR13). The
function.
Set

(CSR18).

state

software

Cleared

this

bit

CLEAR

General

the

bit.

the

bit.

by:

setting
EBus

port

state

writing

used

enabled

Port

is
the

the

KL10

bit

tell

1in

by:

writing

reset.

(CSR18).

has

(set
hardware

Table

5-1

CSR Bit

Description

(Cont)

Bit Name
Number

Function

MPROC RUN
CSR32

When set by the KL10, this bit causes the CRAM
control register to reset and enables the port
start
port will
The
clocks.
microprocessor
cycling at the address contained in the RAR.
be
addresses will
subsequent
and
next
The
fetched from the Am2910 sequencer (Y-outputs).
Set

by:

KL10 writing
Cleared

in the bit.

by:

KL10 writing a 0 in the bit.
setting CLEAR (CSR18).
After each microword cycle if

KL10

(CSR22)

(PI 01

through
Set

EBus

MBUS

reset.

07).

by:

Cleared

the

bit,

by:

KL10 writing
KL10 setting

a 0 in the bit.
CLEAR (CSR18).

General

reset.

EBus

Bit 01 of the 3-bit KL10 EBus PIA field
level 01 through 07).
Set

KL10

KL10
KL10

(PI

by:

writing

Cleared

the

bit.

by:

writing
setting

General

CSR35

(CSR06)

ERR

KL10 writing

PIAOQO2

C¥YC

Bit 0 of the 3-bit KL10 EBus PIA field

setting.

PIAOl
CSR34

SINGLE

(CSRO07)

General

CSR33

DIAG

ERR

PAR

CRAM

PIAOO

set.

EBus

a 0 in the bit.
CLEAR (CSR18).
reset.

Bit 02 of the 3-bit KL10 EBus PIA field
level

through 07).

(PI

Table

5-1

CSR

Bit

Description

(Cont)

Bit Name
Number

Function

Set

by:

KL10

writing

Cleared

KL10

accesses

from

CSR

setting

CLEAR

the

CSR

EBus

bit.

the

bit.

(CSR18).

reset.

executing

accesses

the

by:

writing

read/write

accessing

KL10

port microprocessor
Section 5.1.3.2.
The

KL10

General

The

CONO

CSR

interlocked

prevent

time.

This

the

same

and

the

CONI

commands.

sequence

the

The

described

port

and

interlock

the

KL10

condition

code

grant CSR (CCGRNTCSR). When the port wants to access the CSR,
it executes a microprocessor request CSR
(MPRQSTCSR)
command.
If
the
register
1is
available,
CCGRNTCSR
is
asserted
by
the
EBus
interface logic.
If the CSR is not available because the KL1l0 is

currently accessing the register with a CONI or a CONO,
will not be asserted until the CONI or CONO function is

CCGRNTCSR
complete.

The
port
microprocessor
must
wait
until
it
senses
CCGRNTCSR
asserted
before
it
attempts
to
access
the
CSR
register.
In
the
same way, if the port microprocessor is accessing the CSR when the
KL10

executes

CONI

CONO,

the

EBus

interface

the command to wait until the port access is
conditions between the port and the KL10 are
access
to
CCGRNTCSR)

the
KL10
at CLKl
at CLK3 time.

time

and

logic will

the

port

(by

The
port
microprocessor
(in
the
MPROC
RUN
state,
accesses the CSR by executing the following sequence.

waits

de—-asserted

before

set)

interrupt
microcode

continuing.

To write the CSR, the port microprocessor then executes a
microprocessor load EBUF (MPLOADEBUF) command to load the
CSR

data

executes

into
an

the

MPRQSTCSR

EBUF.

command.

until

asserting

CSR32

The port microcode first checks condition code
active
(CCINTRACTIVE).
If
it is asserted,
the

192

cause

completed. Contesting
prevented by granting

the

same

microcycle

read

MPRQSTCSR

port

the

CSR,

the

microprocessor

executes

command.

then checks

for CCGRNTCSR.

The port microprocessor

When CCGRNTCSR is valid, the port microprocessor executes
or
(MPLOADCSR)
CSR
load
microprocessor
a
either
command.
(MPREADCSR)
CSR
microprocessor read

5.1.3

If an MPLOADCSR command is executed, the contents of
the EBUF are strobed into the CSR at CLK3 time.

an MPREADCSR command

the contents of

is executed,

same
the
On
MBus.
the
on
asserted
are
CSR
the
MBus
the
strobes
microprocessor
port
the
microcycle,
data into location TO of the Am2901 internal RAM.

EBus Control

Logic

The EBus control logic arbitrates the EBus protocol and the port
microprocessor protocol for interfacing to the EBus, and performs
synchronization between the two. Figure 4-3 shows the EBus signals
listed

and

5.1.3.1
control
running
the

described

in Table

4-2.

Port Microprocessor Not Running -- The KL10 has f£full
of the port only when the port microprocessor 1is not
(MPROC RUN, CSR32 is reset). With the port in this state,

primary

functions

and

the

Load

Set up the correct

Check

read/verify

for

With the port in this
diagnostic functions,
generate bad parity,

Table

to:

port microcode

initial CSR functions

unexpected

the

and

port

this

state

halt.

state, the KL10 can
such as write and
single-cycle

The KL10 performs these
DATAOs, and DATAIs. The
functions via the normal
in

the

are

conditions

error

because of

described

KL1l0

also perform secondary
read/verify the EBUF,

the port.

CONIs,
functions by executing CONOs,
port's EBus interface processes these
EBus protocol. The EBus functions are

5-2.

Table

5-2

EBus Functions

Function

Description

LOAD RAR

If the KL10 executes a DATAO with bit 00 =1, a

DATOLOADRAR
causes EBus
into
MBus)

signal 1is generated. This signal
bits D01-D13 to be loaded (via the
the
on
(located
RAR
port
the

microprocessor

control module).

5-14

Table

5-2

EBus

Function

Description

LOAD

MICROWORD

the

MICROWORD

executes

DATOLOADMW

signal

causes

EBus

READ

KL10

Functions

the

DATAO

1is

1least

1loaded

executes
LAR),

generated.

This

the

into

the

MBus)

the

port

CRAM

the

RAR.

DATAI

and

CSR21

contents

KL10

bits

the

SEL

significant
(via

specified
the

signal

bit

This

half

DIAG

with

generated.

'selected

the

(Cont)

a
a

DATIREADMW

signal

causes

the

location

(not

signal

contents

the
selected
half
of
the
port
CRAM
1location
(specified
by
the
contents
of
the RAR)
to
be
placed on the EBus.
READ

LAR

the

KL10

(DIAG

LAR),

generated.

LOAD

CSR

the

LAR

the

CSR

KL10

1is

CSR

bits

writable

the

KL10

contents

KL10
LOAD

EBUF

generated.

READ

EBUF

the

(DIAG
the

the

KL10.

loaded

CONI,

This

bits

placed

the

EBus.

executes

EBUF),
This

KL10

This

causes

the

CSR19

causes

DO00-D35

into

EBus

the EBUF.

DATAI

and

TESTREADEBUF

signal

placed

the

CONIREADCSR

readable

and

the

all

signal

MBus)

executes

causes
into

DATAO

TESTLOADEBUF

signal

the

EBUF),

CONOLOADCSR

signal

CSR

TEST

EBUF

signal

the

(via

generated.

CONO,

executes

KL10

loaded

all

TEST

EBus

CSR21

signal

the
contents
D0l1-D12.

EBus

This

generated.

the

(DIAG

the

and

causes

executes

DATAI

DATIREADLAR

generated.

contents

signal

This
signal
be placed on

signal

READ

executes

SEL

causes

the

CSR19

signal

contents

EBus.

5.1.3.2
Port
microprocessor
is

Microprocessor
Running
-When
the
port
running
(MPROC RUN,
CSR32
set),
the KL10
can
access
the CSR only by executing CONO or CONI commands. With the
port in this state, CONO and CONI commands (LOAD CSR and READ CSR)

operate

the

KL10

the

port

asserted.

described

software
running

This

Section

5.1.3.1.

executes

(CSR32

DATAO

set),

unexpected

DATAI

condition
illegal

5-15

code

function

instructions
CCEBUSRQST
and

while

will

ignored

the port. Therefore, an EBus timeout occurs because the port will
not return EBus transfer. A DATAO or DATAI executed by the KLI10
microcode in response to a previous port examine or deposit
illegal

is not an

request

function.

EBus Interrupts -- When the port is running, the port
5.1.3.2.1
microprocessor controls the EBus by 1loading an IOP function
control word (IOP word is equivalent to the API function control
EBus
an
simultaneously generating
and
EBUF
the
into
word)
Interrupt. Figure 5-2 shows the format of the IOP word. The types
of interrupts that may be generated by the IOP word are listed by
function in Table 5-3. The hardware can dgenerate all of the
interrupts, but the port microcode currently uses only 0, 4, 5,
and

00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 1 16 N 17 1 18 ¥ 19 L) 20 I 21 L} 22 1 23 1 24 ¥ 25 1 26 1 27 § 28 ¥ 29 ¥ 30 ¥ 31 ¥ 32 § 33 ] 34 1 35
l

QEE(':‘E

FUNC

[a|

]

Device

|0 O

Figure 5-2

Table 5-3

)

INTERRUPT ADDRESS
i

)

]

I0P Function Control Word

IOP Function Control Word Bit Description

Bit

Name

Description

00-02

ADDR SPACE

The

containing

space

address

addressed

location

the

13-35,

bits

where

0 = Executive process table
1

Physical

memory

reserved.

All other codes are

03-05

FUNC

(EPT)

= Executive virtual address space

Function requested by the interrupt,
where

0 = Standard

(40

2n)

interrupt

Note)

(see
1
2

= NOT
= NOT

USED
USED

= NOT

USED

NOT

USED

4 = DATAO
5 = DATAI

(Examine)
(Deposit)

(Examine and Increment).
7 = DATAO
This formerly reserved function
enables the CI20 to manipulate
queue

interlocks.

Table

5-3

IOP

Function

Control

Word

Bit

Name

Description

qualifier

the

07-10

DEVICE

12-35

INTERRUPT

(Cont)

according

follows:

Interpretation
Ignored

4,5

1,
and

apply
protection
relocation
to
the
address
specified
by
bits 14-35

device

“the

The

address

ADDRESS

code,

0,7

Physical

11-12

interpreted

function

Function

Description

number

assigned

system.

where

interrupt

handling

begins.

NOTE

(40

2n)

where
n
example,

means

EPT

is
the
level

location

PI
3

(40 + 2n),
1level
number.
For
interrupts
would

reference EPT location 46.
The IOP word
for Function 0 interrupts is all zeros.
If

the

level

EBus

command

7),

interrupt

the

microprocessor

port

examine

or deposit request
(function
requests the interrupt on PI

executing

the
microprocessor
examine
or
deposit
level
00
examine/deposit
interrupt
processed
by the KL10
(as highest priority),

(MPEXORDEP).

requests
are
always
because PI
level
00

interrupts
cannot be
selectively enabled or
disabled as can interrupts on PI levels 01 through 07. Therefore,
the KL10 will process CI20 examine and deposit requests regardless
of the enable or disable conditions of the KL10 PI system.
If
the
EBus
requests the

interrupt
interrupt

is
on

CSR33-35),
by
executing
(MPRQSTINTR) command.
The

interrupt

The

sequence

port

a
function
0,
the port microprocessor
PI level 01 through 07
(as assigned in
the

given

microcode

microprocessor

first

the

following

checks

request

condition

interrupt

steps:

code

interrupt

active
(CCINTRACTIVE).
If
it
is asserted,
the microcode
must wait until the condition code is de-asserted before
continuing.

The port microcode then builds an IOP function control
into the EBUF with a load EBUF
it
word and loads

it
microword,
same
the
With
command.
(MPLOADEBUF)
command
P)
(MPEXORDE
executes a request examine or deposit
or a request interrupt

IOP words (less the interrupt address) for
functions 4, 5, and 7 are predefined in local

The basic
MPEXORDEP,

RAM.

storage

function

MPRQSTINTR,

command.

(MPRQSTINTR)

interrupt,

and the IOP word

MPEXORDEP

standard

is all Os.

(40

2n)

MPRQSTINTR

to
to

The MPEXORDEP command causes RQST EXAM OR DEP (CSR04)
be set. This in turn causes the port EBus interface
assert EBus PI

request line PIO0O.

The MPRQSTINTR command causes RQST INTERRUPT (CSR05) to
be set. This in turn causes the port EBus interface to
assert the EBus PI request line (PI0Ol-PIO7) specified by
the port PI level

(PIAO0O-PIA02, CSR33-35).

When the KL10 EBOX recognizes the PI request it responds
by asserting

the

following:

The port channel number on EBus CS04-CS06
SERVED

The

EBus

port

on EBus

FO00-FO02

interface

responds

(100)

EBus DEMAND,

after delay determined by the KL1O.

asserting

the

EBus

reads

the

data 1line corresponding to the port physical device
number. (EBus D07 for RH20 position 7, the CI20 position,
or EBus D05 for RH20 position 5, the NI port position.)
KL10-determined

After

Next,

the

EBus data

delay,

the

KL10

lines and negates EBus DEMAND.,

KL10

EBOX

EBOX asserts:

The port channel number on EBus CS04-CS06
The port physical device number on EBus CS00-CS03
PI ADR IN

(10l1)

EBus DEMAND,

on EBus F00-F02

after a KL1l0-determined delay

The port EBus interface responds by asserting:
EBus ACKN

The

IOP

(acknowledge).

function

control

word

(previously loaded

into

EBUF by the port microprocessor) on EBus D00-D35.
EBus XFER (transfer), after a port-determined delay.

10.

When

the

KL10

EBOX

detects

from

the

EBus

data

lines

The
trailing
interface to

data

5.1.3.2.2
decodes

lines.

EBus XFER, it strobes the
and negates EBus DEMAND.

data

edge
of
EBus
DEMAND
causes
the
port
negate EBus ACKN,
EBus XFER,
and the

EBus
EBus

Examine/Deposit

the

IOP

function.

request,

then

function

the

IOP

the

Request

control

word

first

The

KL10

EBOX

device

DATAO

Data

port

EBus

also

flags

The

KL10
the

the

microcode

appropriate

examine

IOP

sequence

(0000000)

data

deposit

word

read
outlined in

EBus

CS00-CS06

the

EBus

F00-F02

DATAO

function

KL10-determined

the

EBus

code

0ll)

lines,

interface

code

device

port

following

port.

zero

EBus

The

(010

after

condition

the

DATAI

the

DEMAND,

cycle

executes

asserts:

code

and

specifies

EBus

will be a DATAO or DATAI to
the following five steps:

.l.

Response

word

delay.

responds

asserting

port

microprocessor

request

(CCEBUSRQST).

returned

zero,

not

the

port

device

port.

The

port

does

not

the

KL10

code,

and

examine

the

EBus
is

EBus ACKN.
asserting

CS00-CS06

ignored

device

code

it expects
that
this
EBus cycle
is
in
response
examine
or
deposit
request.
Therefore,
as
soon
port senses EBus DEMAND, it does the following:
Upon

detecting

either

CCEBUSRQST- the

microprocessor

response

(MPREADEBUS)

DATAI,

command

port

load

EBus

microcode

(MPLOADEBUS)

microprocessor

response

is
the

because

to
as

its
the

executes

command
read

EBus

DATAO.

If the port microcode executes MPLOADEBUS,
it
previously
executed
MPLOADEBUF
to
1load
the
valid data for transfer to the KL1O.
If

must

have

EBUF

with

the

port microcode executes MPREADEBUS, the EBus data
placed on the MBus. On the same microcycle, the port
microcode strobes the data from the MBus into one of its
internal storage media.

After

asserts

When

the

DEMAND.

the

data

examine

data

port-determined
EBus

KL10

the

from

EBOX

detects

function

the

(DATAO),

lines.

delay,

the

port

EBus

interface

XFER.

EBus
it

was

data

EBus

XFER

deposit

lines.

de-asserts

the

negates

(DATAI),

the
data

function
from

EBus

strobes

was

the

EBus

trailing

The

lines

(if a DATAI

EBus

port

the

causes

DEMAND

EBus

edge

interface to negate EBus ACKN, EBus XFER, CCEBUSRQST, and

the EBus data

function).

responds
microcode
port
the
functions,
examine/deposit
For
in order to prevent EBus timeouts. The
promptly to CCEBUSRQST,
port microprocessor does not attempt to execute any additional
EBus transfers until it detects the negation of CCEBUSROQST.
Microprocessor to EBus Register

5.1.4

The microprocessor to EBus register (EBUF) is a 36-bit register
normally used by the port microprocessor to pass data from the

MBus (internal tristate microprocessor bus) to either the EBus or
the CSR. The port microprocessor usually loads data into the EBUF
from the MBus. On the next microcycle, the data is strobed from

the EBUF to either the CSR or the EBus.
EBUF

are

follows:

load

then

the
the

CSR.

first

strobed

into

the

EBUF,

CSR.

transmit

examine/deposit

Data

functions of the

The major

IOP

word

over

the

EBus

for

level

requests.

To transmit an IOP word over the EBus for PI
vectored and nonvectored (40 + 2n) interrupt

levels 01-07
requests.

Once the IOP word for a PI level 01-07 interrupt request
has
been
1loaded
into
the
EBUF,
the
port
microcode
monitors condition code interrupt active (CCINTRACTIVE).
The port microprocessor does not load other data into the
EBUF

Data

until

currently

CCINTRACTIVE

the

with a microprocessor

MBus

load

EBUF

de-asserted.

loaded

into

(MPLOADEBUF)

the

EBUF

command.

CLK3

time

A diagnostic loopback path, controlled by DIAG TEST EBUF (CSR19),
enables the KL10 to load and read the EBUF. If CSR19 1is set and
the port microprocessor is not running (MPROC RUN, CSR32 reset):
1.

A DATAO executed
by
loaded (via the MBus)

DATAI

executed

asserted

the
into

the

KL10
causes
the EBUF.

KL10

causes

the

EBus

data

the

EBUF

EBus.

5.1.5
EBus to Microprocessor Multiplexer (EMUX)
The EMUX is a two-input by 36-bit multiplexer that passes data to
the MBus from either the EBus or the CSR. The EMUX is enabled by

the port microprocessor

KL10 DATAO

diagram of EMUX control

simplified

functions.

and data

flow.

Figure

5-3

is a

EBUS D *

-o\

GND

»11

EBUS D **

»{0

CSR **

1
»{SEL

MPREADCSR

MPREADEBUS———
¢
TESTLOADEBUF

DATAOLOADRAR——— | —m

DATAOLOADMW—F - —n

MBUS D00-D35
D00-D35

DO1-D13

DO6/D35

EBUF

CLK

RAR
»

cLk

CRAM

WREN

* 00-03, 06-10, 14-23, 39
** 04-05, 11-13, 24-28, 30-35
MR-13758

Figure

When

the

5-3

port

enabled

with

command

MPREADCSR

When

the

enable

port

(MPROC

Multiplexer

RUN,

CSR32
read

also

can

the

running

Microprocessor

a
microprocessor
microprocessor
read
CSR

command

either

microprocessor
location

EBus

the
is

then
Am2901

not

EMUX

selects

EBus
(MPREADCSR)

CSR

input

strobe

the

data

from

internal

RAM.

running

the

set),

(MPROC

executing

following:

RUN,

CSR32

DATAO

the

command.
EMUX.

the

reset)

commands

EMUX

The

MBus

the

KL10

write

The

CRAM

(DATAOLOADMW)

The

RAR

(DATAOLOADRAR)

The
E
buffer
(TESTLOADEBUF) .

via

the

diagnostic

(MPREADEBUS)

loopback

The
port

into

can
the

path

NOTE

CSR input to the EMUX is
with KL10 DATAO commands.

not

selectable

5.1.6
Microprocessor to EBus Multiplexer (KMUX)
The KMUX is a two-input by 36-bit multiplexer that passes data to
the EBus from either the E buffer or the CSR. The KMUX is enabled
by either the port microprocessor or KL10 DATAI or CONI commands.
Figure

5-4

simplified

diagram

KMUX

control

and

data

flow.

I CRAM |
MW OUT
MUX
LAR
= ENOUT

DO1-D13

D06-D35

DO0-D35

| —»

CLK

CSRO0O-CSR35

~:;\\\

EBUF

Y —» EBUS DOO-D35

>t 1

OfEeN

] SEL

CONIREADCSR

L/’/’

DATAIREADMW ——— | =i

DATAIREADLAR
TESTREADEBUF

MPLOADEBUS
IOPO
MR-13759

Microprocessor

Figure 5-4

When

port

the

enable the KMUX to

running

(MPROC

to EBus Multiplexer

RUN,

read the following:

CSR32

The CSR, by executing CONI commands

The

IOP

during

The

the

word,

by asserting

interrupt

port microprocessor

EBus

executing

command.

ADR

the

set)

KL10

can

(CONIREADCSR)

(101)

EBus

F00-FO02

sequence.

can enable

the KMUX to

microprocessor

load

to
(MPLOADEBUS)

pass MBus data

EBus
.

When the port is not running (MPROC RUN, CSR32 reset) the KL10 can
enable the KMUX, by executing DATAI or CONI commands, to read the
following:

CRAM (DATIREADMW)
LAR (DATIREADLAR)
EBUF (TESTREADEBUF)
.
CSR (CONIREADCSR)

5.1.7
The

EBus

Parity Generator

generator
generates
odd
parity on
every
36-bit
data
word
that
the
port
passes
to
the
EBus.
Because
the
KL10
architecture prohibits parity checking on an IOP word, the signals
EBUS

parity

PARITY

and

transmitted

EBUS

PARITY

the

ACTIVE

are

inhibited

when

IOP

EBus.

word

5.1.8
EBus Parity Checker
The EBus parity checker
normally

36-bit

data

incorrect,
However,

word
the

checker

that

EBUS

DIAG

checks

the

PARITY

GEN

5.1.9

EBus

logically

Arithmetic
1is

the

parity.

same

Logic

EBus

the

interface/port

set,

the

EBus

(assuming

writes

Am2901

four-bit

Four

type

Am2902

high-speed

Five

type

74LS157

nine

Am290ls

5-5).

(described

parity

normal

odd

will

also

CSR20

collector
EBus.

microprocessor

module.

bipolar

ALU

and

consists

microprocessor

look—-ahead

multiplexers

The

used

slices

carry

generators

input

constants

ALU
and

four

configuration,
forming
look-ahead.
Figure
5-5
Am2901s.
output

port

ALU

type

CPUCLOCK

that

set.

Unit

part

Nine

Figure

Therefore

CONO

the

(CSR20)

are
the
same
type
8838
open
other devices that interface to the

5.1.10
ALU

The

(CSR24)

Transceivers
used

The

bit

transceivers

located

ERROR

EBUS

for

even
parity
is
correct),
the
cause CSR24 to be set.

The

checks
for odd parity on every
reads from the EBus. If parity is

port

the
The

below)

(CLK4

ALU
data

and

gated

Am2902s

are

connnected

parallel

a
1is

36-bit
ALU
with
high-speed
carry
a
simplified
diagram
of
the
nine

1is

connected

input

1is

from

the MBus

both.

RUN,

MPROC

CSR

directly
the

32)

the

constant

1is

the

MBus

(see

multiplexer

clock

input

ALU.

For shift operations,
or the LSB, depending

zeros are always
on the direction

shifted into either
of the shift.

the MSB

The port microprocessor controls the ALU by executing the commands
described

Table

5-4.

MWDESTFLDOO ——»

MWDESTFLDO1 —]

MWDESTFLDO2 —»

» MBUS D00-D35

[—————1/

MWOUTPUTENA

————-—J

MWFUNCTFLDOO—

MWFUNCTFLDO1—{

MWFUNCTFLDO2 —8

ALU

» CCFEQLO

\
L

MWCARRY

—» CCMBSIGN

S \

MWSORCEFLDOO
—&

—»f
MWSORCEFLDO1

MWSORCEFLDO2 —m

: /MU_X\

[4p]

CNST00-09

MBUS D10-D25

D |

CNST26-35

MU-X\

[

CPOCLK

—»{

A LATCH

MWPORTAFLD00-03

—»

" 7DR

T5.L0C

MWPORTBFLD00-03 ————|—»{

B ADR

RAM

[fi

[
Q
REGISTER

B LATCH

| EN

Q SHIFTER

RAM
SHIFTER

MRA-13760

Figure

5-5

Table

Block

5-4

ALU

Control

The

microword

Diagram

ALU

selects

the

source

the

follows:

00-02

oogUuUNNNYP
Y

NOPIPO
WO

ALU,

00-02

wNe-=

MWSORCEFLD

ALU

(Simplified)

Commands

Description

NSO

Command

AM2901

source

field,

bits

the

and

24-26,

inputs

Table
Command

5-4

ALU

Control

Commands

(Cont)

Description
Where:
A

by
B

The

00-02

contents

MWPORTBFLD

00-03

The

RAM

location

addressed

the

RAM

location

addressed

data

CNST

The

Zero

The

microword

contents

ALU

the

MBus

10-25,

and

the

functions

and

the

Q register

function

controls

inputs,

that
as

field,
the

bits
ALU

27-29,

performs

follows:

nunununununnaown

plus

minus
minus

[

AV OVIVOVB
VD

- O

Function

~NOY

The

00-09,

26-35

00-02

MWDESTFLD

the

00-03

CONST

MWFUNCTFLD

contents
of

MWPORTAFLD

and

and
Xor
Xxnor

microword

ALU

destination

field,

bits

30-32,
determines
if
the
Am2901
output
(Y)
will
be
from
the
ALU
or
the
RAM
1location
addressed
by
MWPORTAFLD
0-3.
It
also
determines the input to the Q register and to

the

RAM

location

addressed

MWPORTBFLD

0-3.

This field also controls the RAM shifter and Q
shifter, causing the RAM and Q register inputs
to multiplied or divided by 2 (shifted left or
right).
Thus,
by
controlling
the
Am2901
internal data paths, this field determines the
destinations of the Am2901 internal data. The
effect of this field is as follows:

00-02

RAM B

Gets

ALU

HOLD

ALU

HOLD

RAM

HOLD

ALU

Table 5-4

ALU Control Commands

(Cont)

Description

Command

ALU
ALU
ALU

3
4
5

ALU
ALU

6
7

MWPORTAFLD 00-03

HOLD
Q/2
HOLD
QX2
HOLD

ALU]
ALU/2
ALU/2

ALUX2
ALUX?2

The microword port A select field, bits 35-38,

addresses one of 16 RAM locations that will be
Iis
port
This
1latch.
A
the
through
read
read-only.

MWPORTBFLD 00-03

The microword Port B select field, bits 39-42,

MWCARRY

The microword 2901 carry in field, bit 51, is

addresses one of 16 RAM locations that will be
either read through the B latch or written.
the carry into the least significant bit of
the ALU. When MWCARRY is 0, zero is carried
into the ALU LSB. When MWCARRY is 1, one is

carried

MWOUTPUTENA

The

into

the ALU

LGSB.

The microword output enable to 2901,
enables

the output of

the ALU.

bit 13,

port microprocessor monitors the ALU status by sensing

the

following condition codes:

CCFEQLO Condition Code F = 0 -- indicates that the result of the
last ALU operation produced all zeros

CCMBSIGN Condition Code MBus Sign -- indicates that the last ALU

operation set the sign bit (ALU MSB = MBus bit 00)
5.1.11

Constant Multiplexer

The constant multiplexer (CNST MUX) 1is a two-input by 20-bit
multiplexer that provides the data (D) inputs to the 10 LSBs and
MBus
10 MSBs of the Am290ls

(see Figure 5-6).

It passes either

)
D00-D09 or MWMGCFLD 00-09 (microword magic number, bits 14-23to
the MSBs, and either MBus D26-D35 or MWMGCFLD 00-09 to the LSBs.
This allows the microprocessor to load a constant number value
into the 10 most significant and 10 least significant bits of the
ALU. MBus D10-D25 are always loaded into the corresponding "D"
inputs.

MWMGCFLD 00-09 are selected as input to CNST MUX 00-09 and 26-35
when the port microprocessor executes a microword with the
microword skip/condition (MWSKIPFLD), bits 43-47, set to 24
(octal). This SKIP/COND field value causes the signal select
constant field

(SELCNSTFLD)

to be asserted.

5-26

MBUS D26-D35

>
»]

MBUS D10-D25

———

CNST26-35

N
1

—————

CNST10-25

-———=

CNSTO00-09

MBUS D00O-D0O9
MWMGCFLDOO-09

]

SELCNSTFLD

> y

MR-13761

Figure

5.2
The
the

5-6

Constant

Multiplexer

(Simplified)

CBUS/DATA MOVER (CMVR) INTERFACE MODULE
CBus/data mover
(CMVR)
interface module consists
following control logic and data paths.
l.

The

CMVR

control

logic

microprocessor

specified
port

the

microprocessor

decodes

accesses

and

executes

controller

the

primarily

the

commands

microword.

CMVR module

The

executing

microprocessor
commands.
These
commands
are
decoded
functions
of
the
microword
bus
control
(MWBUSCTLFLD)
field,
bits
48-50
and
the
MWMGCFLD
field
of
the
CRAM
control word.
The
port microprocessor monitors the CMVR
control logic status by sensing condition codes.
2.

data path between the KL10 CBus and
port link interface (PLI), including:

the

between

data

and

the

mover

PLI.

and

The

formatter

mover

into
KL10
36-bit
8-bit bytes.
CBus

input

checkers,

PLI

and
and

and

words

output
CBus

and

input

and

output

and

PLI

KL10

buffers,

control

checkers,

(MVR/FMTR)

formatter

36-bit

CBus

PLI

buffer

the

CBus

8-bit

bytes

words

into

PLI

parity

generators

and

parity

generators

and

logic.

buffers,

control

maps

packet

PLI

logic.

A
data
path
between
the
CMVR
module
microprocessor. This data path enables the

and
the
port
microprocessor

to:

Load

read

mover

Load

read

the

A parity predictor
and formatter.

and

formatter

packet

buffers

for

checking

via

the

parity

PLI.

through

the

mover

CMVR Control Logic

5.2.1

The CMVR control 1logic consists primarily of a decoder and a
series of two-input NAND gates. The decoder input is microword bus
control (MWBUSCTLFLD 00-02), bits 48-50. Table 5-5 1lists the
decoder output signals as

Table 5-5
MWBUSCTLFLD

follows:

Decoder Output Signals

0-2

Decoder Output

000

(not connected)

SELPLIFLD (select PLI field)
SELMBUSFLD (select MBus field)

001
010

SELFMTRFLD

011

SELSCUSFLD

100

101-111

(select mover and formatter field)

(select CBus field)

(not connected)

then ANDed with various
These decoder output signals are
(MWMGCFLD 02-09), bits
number
magic
d
microwor
of
ions
combinat
16-23 to control the PLI, CBus, and MBus interfaces, and the mover

and

formatter.

The CMVR control 1logic also generates and distributes the port
clocks (CLKl, CLK2, CLK3 and CLK4) to all three port modules. All
four clocks make up a single microcycle. The port clocks are
the
shows
5-7
Figure
clock.
KL10 EBus
the
from
derived
at
running
is
relationship of the clocks when the KL10 EBus clock
the normal 160 ns cycle time.

CLKl normally strobes the next microword into the port CRAM
functions,
timing
other
several
has
and
register,
control
CLK4 are
and
CLK3,
depending on the specific operation. CLK2,
execute
to
logic
generally used throughout the port control
is
which
CPUCLOCK,
microword-specified functions. CLK4 generates
the clock

input to

four

<clocks

All

the Am2901 ALU.

are

gated

control

1logic

the

port

microprocessor control module. The gated clocks are named RUNCLK1,
RUNCLK2, RUNCLK3, and RUNCLK4, respectively. Gating these clocks
and
stopping,
starting,
©port
of
control
orderly
provides
single-cycle operation.

when the microword time field (MWTIMEFLD), bit 56, is set in a
microword, CLK3 and CLK4 will occur 160 ns later than normal for
that microcycle, and the microcycle time will increase from 320 ns
time of the microcycle is a
to 480 ns. Increasing the execution
simple way to overcome specific microinstruction timing problems.

|<—— MICROCYCLE

'4— 160ns ——-l

* ADD 160ns HERE IF MWTIMEFLD IS SET — (SEE TEST)
MR-13762

Figure 5-7

5.2.2
The

Data

Mover

and

Port Clock Timing

Formatter

mover/formatter

registers
l.

and

<consists
associated control

Parallel

36-bit
2.

load

and

(MVR/FMTR)
of
four
parallel/serial
shift
logic. It is used as follows:

read

the

port

microprocessor

Parallel

load

and

read

the

CBus

interface

36-bit

Parallel

Serial
the

PLI

load and left shift

PLI,

four

eight

the

PLI,

four

Four-bit nibbles from
and shifted either up
KL10

words

the

for

bits

PLI

loaded

are

36-bit

words

After

can shift the word,
transfer to the PLI.

a
or

shifts

are

word

1loaded

down,

can

the

from MSB to LSB)

time.

into

the

mover/formatter

(MSB to LSB),
the CBus. Two

from

loaded,
into

from LSB to MSB)

time.

(LSB to MSB)
or down
parallel transfer to

The

(shift down,

bits

one 8-bit byte. One or two
microprocessor microcycle.
KL10

or eight

load
port

mover/formatter.

8-bit

(shift up,

Serial load and right shift
by

36-bit

the

executed

the

CBus

the

port

PLI

output

to form
shifts
a

single

into

the

microprocessor
register

for

the

PLI

output

1is

1loaded

from

the

bottom

the

mover/formatter
and
shifted
up
(LSB
to
MSB)
the
data
1is
not
wrapped
around,
but
1is
shifted
out
of
the
four
MSBs
of
the
mover/formatter
and
lost.
If
the PLI
output
register
1is
1loaded
from the top and shifted down (MSB to LSB) the data can be wrapped
around. That is, the four LSBs of the mover/formatter are input to
the
four
MSBs
of
the mover/formatter.
Therefore,
data
can
be
right-shifted
around
the mover/formatter
as necessary,
to
align
the
data
into
the
proper
format.
The
port
microprocessor
can
select either the four MSBs or the four LSBs of the PLI byte as
the

first

input

The commands
5—6 L ]

Table

the

mover/formatter.

control

5-6

the

mover/formatter

Mover/Formatter

Command

Description

MPCBUFTOFMTR

bufffer

contents to
registers.
MPFMTRTOPLOUT

MPZEROLFTNIB

Formatter

Control

formatter

loaded

—--

into

Table

buffer

Commands

causes

the

mover/formatter

causes

the

in
to

the
mover/formatter
be
1loaded
into
the

PLI
PLI

Zero

when

the

nibble

output

described

8-bit
data
byte
output
register
output buffer.

left

PLI

are

buffer

asserted,

causes

four MSBs
of
the mover/formatter
PLI
output
register to be forced to zeros before they are
loaded into the PLI output buffer.
MPRHTNIBFIRST

Right nibble first -- when asserted, the first
bits shifted into the mover/formatter are the
four PLI input buffer LSBs. When not asserted,
"~ the
first
bits
shifted
into
the
mover/formatter are the four PLI input buffer
MSBs.

MPSHFTFMTRS .

Shift

formatter

mover/formatter
bits
to
state of
Shift

mover/formatter

Formatter

bits

contents

Bits

the
left or
right,
MPSHIFTRIGHT.

bits
to
state of

—causes

shifted

the
left or
right,
depending
MPSHIFTRIGHT.
'

MPSHFTFMTR4A

”

contents

=--

the

eight
on

the

—causes

the

shifted

four

depending

the

Table

5-6

Mover/Formatter

Control

Commands

(Cont)

Command

Description

MPSHFTFMTR4B

Shift
Formatter
by 4
Bits
-causes
the
mover/formatter
contents
to
be
shifted
four
bits
to
the
left or
right,
depending on the
state

MPSHIFTRIGHT

Shift

MPSHIFTRIGHT.

right

currently

the

when

selected

asserted,

PLI

input

are

and

shifted

The

data

the

nibble

or
(MVROUT
36-39)
mover/formatter MSBs

four

mover/formatter
shifted into the four

either

buffer

LSBs

right.

shifted

into
the mover/formatter
1is
MPPLINTOFMTR. If both MPSHIFTRIGHT
and MPPLINTOFMTR
are
asserted,
the
currently
selected
PLI
input
buffer
nibble
is
shifted
into the four mover/formatter MSBs and shifted
right.

selected

MPSHIFTRIGHT
is
asserted
and MPPLINTOFMTR
is not asserted, then MVROUT 36-39 is shifted
into the four mover/formatter MSBs and shifted
right.
If

MPSHIFTRIGHT

MPPLINTOFMTR

nibbles

are
mover/formatter
MPPLINTOFMTR

1is

not

asserted,

asserted
the

shifted
LSBs

PLI

into
and shifted

and

input

buffer

the
left.

four

PLI
input
buffer
to formatter
-causes
the
8-bit
data
byte
currently
in
the
PLI
input
buffer
to
be
shifted
(four
bits
at
a
time)
into
the
mover/formatter.
This
command
is

executed
in
MPSHFTFMTR8.

only

four

into

the

executed,

conjunction
If

with
MPSHFTFMTR4A or
MPSHFTFMTR4A is executed, then

PLI
input
buffer
bits
are
shifted
mover/formatter.
If
MPSHFTFMTR8
is

then

all

eight

PLI

input

buffer

bits

will be shifted into the mover/formatter. Two
4-bit
shifts
can
be
executed
during
one
microcycle,
right
shifting
an
entire
8-bit
byte in a single microcycle.

Figure 5-8 shows the flow of data through the mover/formatter,
which is essentially four 12-bit shift registers. The data in and

out

CBus,

to the PLI,

is from or

or MBus.

For CBus and MBus data, the mover/formatter acts as a single
36-bit register, inputting and outputting CBus and MBus data in
36-bit

parallel

transfers.

PLI data is input to the mover/formatter, four bits at a time. It
is either loaded into the LSBs and shifted up, or into the MSBs
and shifted down. Data is output to the PLI, eight bits at a time,
from the two MSBs in each of the four registers.

The LSB of each of the four registers (36-39) can be wrapped
around and shifted into the MSBs and down, in order to align the
data.

PLI IN

SHIFT

——»

03 {-»

|00 |-»
» |04 |FROM
CBUS
MBUS

EE——

02|+

| %)

OR
04
OR
39

OR
05
OR
38

OR
06
OR
37

OR
07
OR
36

L 00

Loz

I—.Q

°°"§I>(L)|

o1 |-+

041 ) our

-»

| 02]-»
| 06 |-»

»102 |»|07]-»

-»}j13]»
»{17]-»
|21}
»|25|»

-»]14]»
»118|-»
»122]-»
| 26 |»

w|15}+> { TO
CBUS
»|19 MBUS
+»|23|»
| 27}1-»

101 |-»
»|05}]-»

»|10]-»

|11 |-

|08 |-

~»| 09|

»|28|»
| 32|
36

>=|29|»
»|33]»
37

|30
- 34 |38

02
OR

01
OR

00
OR

e —

hesersnsnmd

»l12]»
| 16]-»
-»>|20]|»
»|24]|»

03
—® OR

—

E—

DOWN

-»|
|

31 |-»
35|-»
39

SHIFT

UP
MR-13763

Figure 5-8

The

mover/formatter

packing

modes):

Mover/Formatter Data Flow

supports

three

different

data

formats

(byte

Industry Compatible: Four 8-bit bytes per 36-bit word.
Bits 32-35 of the word are forced to zero (Figure 2-39).

Core Dump: Five 8-bit bytes per 36-bit word. Four bits of
every fifth byte are discarded.

These

High

Density:

word

(Figure

2-32).

formats

are

data

subroutines
5.2.3
The DMUX

under

Data
is a

Four

control

and

one-half

1implemented

the

port

Input Multiplexer
two-input by 36-bit

8-bit

bytes

per

different

36-bit

microcode

microprocessor.

multiplexer

that

passes

36-bit

data word to the mover/formatter
from either the CBus input buffer
or
the CBUF.
When MPCBUFTOFMTR
is
asserted,
it selects the CBUF
input to DMUX; otherwise the CBus input buffer input is selected.
Figure 5-9 shows data flow through the DMUX.

CBINOO-35

»l O

CBUF00-35

MVRINOO-35

MPCBUFTOFMTR ——————1 SEL

MR-13764

Figure
5.2.4

PLI

Serial

5-9

DMUX

Up Multiplexer

(Simplified)

(SUMUX)

The SUMUX is a two—-input by 4-bit multiplexer that passes either
the four LSBs or the four MSBs of the PLI input buffer to the four
mover/formatter LSBs (see Figure 5-10). The 4-bit nibbles can then
be left shifted to form a 36-bit word. Each mover/formatter left
shift discards the four MSBs.
Each microcycle
8-bit
PLI
microcycle.

can

input

process two
buffer

MPPLINTOFMTR

enables

the

input

buffer

LSBs

inputs.

nibbles

from

the

SUMUX

The

Section

4-bit

byte

SUMUX.

nibbles,
the

MPRHTNIBFIRST

are

also

inputting

mover/formatter

selects

input

5.2.5).

PLIN4-7

~F;\\\

PLINO-3

»]

—~———————— PL4AOROUP-70R3UP

MPRHTNIBFIRST ——

SEL

MPPLINTOFMTR ———»
Oy

MR-13765

Figure

5-10

SUMUX

5-33

(Simplified)

the

entire
in

one

four

PLI

SDMUX

(see

PLI Serial Down Multiplexer

5.2.5

SDMUX

The

(SDMUX)

two-input by 4-bit multiplexer that passes either

LSBs
£four mover/formatter
the
or
nibbles
output
SUMUX
4-bit
5-11).
Figure
(see
MSBs
ter
mover/format
(MVROUT 36-39) to the four
The nibbles can then be right shifted to form a 36-bit word. Each

microcycle can process two 4-bit nibbles, inputting an entire
8-bit PLI input buffer byte to mover/formatter in one microcycle.
The capability to shift the four mover/formatter LSBs (MVROUT
36-39) back into back into the four MSBs (PL4ORODN-70R3DN) permits
data to be wrapped around and shifted indefinitely with right
shift commands. Therefore, data can be retained and shifted (in
4-bit nibbles) to any position in the mover/formatter registers.
MPSHIFTRIGHT

enables

output of SUMUX as

the

input.

SDMUX,

MPPLINTOFMTR

and

selects

the

PL4OROUP-70R3UP ——n%
| PLAORODN-70R3DN

MVROUT391-36 ———————=1 1

MPPLINTOFMTR ——————{ SEL
MPSHIFTRIGHT —————boy

MR-13766

Figure

SDMUX

5-11

(PMUX)

PLI Output Multiplexer

5.2.6

(Simplified)

The PMUX is a two-input by 8-bit multiplexer that passes either
the two MSBs from each of the four mover/formatter registers
or the eight LSBs of the CBUF to the 8-bit PLI
(MVRPLOUTO0-7)
output

buffer

(see

Figure

5-12).

The port microprocessor command, MPCBUFTOPLOUT

buffer) selects CBUF28-35
to
CBUF)
(via
D28-D35

(CBUF to PLI output

as the input to the PMUX, passing MBus
Otherwise,
buffer.
output
PLI
the

MVRPLOUTO0-7 are passed to the PLI output buffer.
If

MPZEROLFTNIB

asserted,

the

four

MSBs

the

PMUX

output

(PLOUT4-7) are forced to zeros, by disabling half of the PMUX.
This capability is needed for core dump byte-packing mode (see
Figure 5-11), where the four MSBs of every fifth byte (BYTE 5n+5)
must

zero.

MVRPLOUT4-7 ———D[O\

MVRPLOUTO-3 ——DO\
~——— PLOUT4-7

CBUF31-28

—»}

MPCBUFTOPLOUT

————

CBUF35-32

»| SEL

»l

MPZEROLEFTNIB ——-———Doy

PLOUTO-3

————p{ 1

SEL

GND—-—hOy
MR-13767

Figure

5-12

PMUX

(Simplified)

5.2.7
CMVR to Microprocessor Multiplexer (CMUX)
The CMUX
is a two-input by 36-bit multiplexer that inter
faces
to
the port's
internal MBus
(see Figure 5-13).
It enables the port
microprocessor to read
The

mover/formatter

(MPENACMUX)

command.

The

packet

buffers

PLI

input

input
CMUX

buffer

buffer
MSBs

are

MPENACMUX

must

(via

36-bit

the

CMUX

PLI

forced

also

asserted,

MVROUTO00-26

> o\

GND

»l

input

tying

command

the

with

buffer)

(MPPLINTOCMUX)

(PLINO-7)
be

enable

8-bit

bytes.

selects

the

eight

CMUX

their

inputs

enable

the

CMUX

LSBs.
to

The

PLI

ground.

multiplexer.

MVROUTZS-SS——-'JO\
————» MBUS D00-D27

PLIN7-0

|————»

———————

MBUS D28-35

MPPLINTOCMUX ——————] SEL

»1 SEL

MPENACMUX —————» () EN

¢oy

MR-13768

Figure

5-13

CMUX

5.2.8

(Simplified)

Microprocessor to CMVR Register (CBUF)
CBUF
is
a
36-bit
buffer/driver
that
passes
data
from
the
microprocessor
internal
MBus
to
the
CBus/data
mover
interface
module
(CMVR).
The CBUF acts only as an
isolation buffer to the
tristate
MBus
and
is
logically
transparent
to
the
port
microprocessor.

182

The

5.2.9

CBus

Input Buffer

The CBus input buffer is a latched 38-bit (36 data bits + 2 parity
bits)
register
that
passes
data
from
the
CBus
to
the

mover/formatter.

The

can

loaded

from the CBus whenever

it is not being read by the mover/formatter. The reverse is also
true. That is, the register can be read by the mover/formatter if
it

not

being

loaded

from

the

CBus.

The contents of the CBus input buffer are normally clocked into
the
mover/formatter
by
a
CBus
input
buffer
to
formatter
(MPCBINTOFMTR)
command
at
CLK2
time,
if
condition
code
CBus
available (CCCBUSAVAIL) was asserted on the previous microcycle.
5.2.10
CBus In Parity Checker
The CBus In parity checker checks for odd parity on each 18-bit
half of the 36-bit word that the mover/formatter reads from the
CBus input buffer. If parity is not correct, condition code CBus
parity
error
(CCCBUSPARRERR)
1is
generated
and
passed
to
the
microsequencer (Am2910) condition code multiplexer (CCMUX).

The

condition

code

remains

latched

until

cleared

the

microsequencer. When the port microprocessor senses CCCBUSPARERR
is set, it sets DATA PATH ERR (CSR26)
in the control and status
register.

5.2.11
CBus Output Buffer
The CBus
output
buffer
is

latched

38-bit

(36

data

bits

parity bits) register that passes data from the mover/formatter to
the CBus.
The
register
can
be
loaded
from the mover/formatter
whenever it is not being read by the CBus. The reverse 1is also
true. That is, the register can be read by the CBus if it is not
being

loaded

from

the

mover/formatter.

The CBus output buffer is normally loaded from the mover/formatter
by a formatter to CBus output buffer
(MPFMTRTOCBOUT)
command at
CLK2 time, if CCCBUSAVAIL was asserted on the previous microcycle.
5.2.12
CBus Out Parity Generator
The CBus Out parity generator generates odd parity for each 18-bit
half-word
passed
from
the
mover/formatter
to
the
CBus
output
buffer. The two parity bits for a complete 3¢-bit word are latched
into

the

buffer

for

output

the

CBus.

5.2.13
CBus Control Logic
The CBus control logic arbitrates

the CBus protocol and the port
protocol
for
starting
and
stopping
the
CBus,
and
performs
synchronization between the CBus and the mover/formatter. The CBus
control logic also generates the clock timing for the port.

The CBus is a synchronous, high-speed, time-division multiplexed,
tristate data bus. It runs between the KL10 MBOX and the channel
devices (see Figure 4-5 and Table 4-5). Each device on the CBus
has a unique time slot. A CBus data transfer has four cycles:
select, request, wait, and data (see Figure 4-6 and Table 4-6).

5-36

The

port microcode
prepares .to
start
the
CBus
data
channel
by
executing a start CBus
(MPSTARTCBUS)
command.
For an
input data
transfer to
the KL10 memory,
the port microcode also executes a
write to KL10 memory (MPWRITEMEM) command. The CBus control logic
latches these commands, until they can be executed when the port's
CBus time slot becomes available. The CBus control logic detects
the port's time slot by sensing its CBus SEL line.
When

the

asserted

CBus
and

control

the

CBus

1logic

READY

detects

line

the

negated,

port's

CBus

SEL

starts

the

channel

1line
by

using
the
latched MPSTARTCBUS command
to assert CBus START and
CBus
RESET
during
the
subsequent
data
cycle.
The
CBus
control
logic
then
clears
the appropriate
latches
set by previous port
microcode commands
(such as MPSTARTCBUS).
If the
transfer
is to
KL10
memory,
the
CBus
control
1logic
also uses
the
MPWRITEMEM
command

assert

CBus

CTOM

clear
the
1latch
set
transfer is complete.

the

When

ready

the

asserts
After

KL10
CBus

channel
READY

receiving

during

CBus

the

READY,

this

CBus

the

corresponding
The

port

CBus input
full,

data

DATA

word

1lines

request
ready

buffer

However,

command

transfer

data

port

data

cycle.

the

port

CBus

REQUEST during its request cycle
from the channel
(device write),
channel

time.

MPWRITEMEM

(device

during

the

read).
port

over

Control

whenever it
or whenever

until

does

not

the

data

the

CBus,

asserts

CBus

requires a data word
it requires that the

The

data

words
cycle

are

asserted

following

its

whenever

its

cycle.
transfer

empty,

data

across

whenever

the

its

CBus

output

buffer

The
CBus
input
buffer
is
emptied
(transferred
to
the
mover/formatter)
with
the
CBus
input
buffer
to
formatter
(MPCBINTOFMTR)
command
when
the
port
microprocessor
senses
the
condition
code
CBus
available
(CCCBUSAVAIL)
and
is
prepared
to
accept
The

data

CBus

from

the

output

mover/formatter

are

output

buffer

senses
CBus.

CCCBUSAVAIL

CBus.
Dbuffer

1is

1loaded

transferred

(MPFMTRTOCBOUT)

and

has

it)

command

data

(the

with

when

the

available

contents

the

formatter

CBus

port

for

microprocessor

transfer

the

When the channel places the last word on the CBus during a device
write operation,
it asserts CBus LAST WORD. In response, the port
CBus
control
1logic
asserts
<condition
code
CBus
1last
word

(CCCBLSTWD). When
the
port microprocessor detects CCCBLSTWD,
it
responds with a stop CBus
(MPSTOPCBUS)
command.
This causes the
port CBus control logic to assert CBus DONE during the next port
data
cycle.
The
port
will
make
no
more
data
requests
during
subsequent
request
c¢ycles.
CBus
DONE
causes
the
channel
to
terminate the operation. CBus READY is negated when the channel is
prepared to begin another data transfer.

5-37

The
port
microprocessor
can
also
execute
a
store
CBus
status
information
(MPSTORECBUS)
command with an MPSTOPCBUS command on
the same microcycle. This causes the port CBus control logic to
assert
cycle.

"cycle

CBus
STORE
along
with
CBus
DONE on
the next
Asserting CBus STORE and CBus DONE during
the

forces

assigned

the

reset

channel

and

status

store

logout

channel

status

port
same

data
data

command

and

the

channel's

area.

NOTE

MPSTORECBUS
should
unless MPSTOPCBUS is
same microcycle.
The

port

microprocessor

MPSTORECBUS

command,

never
be
asserted
also asserted on the

executes

causing

the

both

the

port CBus

MPSTOPCBUS

control

logic

assert

CBus

DONE and CBus STORE, when it has transferred all data over
the CBus during a device read operation. The port microprocessor
also
executes
these commands when
it detects,
during
a read or
write, one of the following transfer error condition codes set:
CBus parity error (CCCBUSPARERR)
CMVR parity check (CCCMVRPARCHK)
CBus channel error (CCCHANERR)
PLI parity error (CCPLIPARERR).
The

port

will

make

5.2.14

PLI

Input

The

input

data

requests

during

subsequent

request

cycles.

PLI

Buffer

buffer

latched

9-bit

data

bits

parity

bit)
register
that
passes
data
£from
the
PLI
bus
to
mover/formatter.
The
register
1is
loaded
with
a
receive
MPRECVPLI command at CLK4 whenever an 8-bit byte is present
input from the PLI bus. Every time the register is loaded, PLI
parity is loaded into a holding flip-flop.

the
PLI
for
bus

Once the register is loaded, the port microprocessor transfers the
data (four bits at a time) to the mover/formatter (four bits at a
time) with the commands MPPLINTOFMTR, MPLFTNIBFIRST, MPSHIFTRIGHT,
and
so
on.
The
port
microprocessor
can
also
execute
an
MPPLINTOCBUF command,
transferring 8-bit data byte to the eight
MBus
LSBs,
for
further
transfer to one of the microprocessor's
internal storage media.

5.2.15
PLI Parity In Checker
The PLI Parity In checker checks for odd parity on every 8-bit
data byte that the port reads from the PLI input buffer. If parity
is
incorrect,
condition code PLI
parity error
(CCPLIPARERR)
is
generated
and
passed
to
the
microsequencer's
condition
code
multiplexer. The port microprocessor sets DATA PATH ERR (CSR26) in
the CSR when it senses CCPLIPARERR set. CCPLIPARERR stays latched
until cleared by the microprocessor.

5.2.16
The

PLI

Output

output

Buffer

buffer

is a latched 9-bit
(8 data bits + 1 parity
that passes data from the mover/formatter to the PLI
bus.
The port loads the register
(via the PMUX)
when
it has an
8-bit byte assembled and ready for transfer to the PLI bus from
either
the
eight mover/formatter MSBs
(PLI
output byte)
or
the
eight MBus LSBs (via the CBUF). The port microprocessor loads the
register with either a CBUF to PLI output buffer
(MPCBUFTOPLOUT)

bit)

command

CLK4

time,

(MPFMTRTOPLOUT)

odd

parity

After

command
generated

the

outputs

the

data

the

5.2.17

PLI

The

parity

PLI

every
8-bit
buffer.
The
output

generator

generate

1loaded,

the

port

PLI

(MPXMITPLI)

PLI

control

normally

enables

the

tristate

command,

placing

generates

odd
parity
for
port
to
the
PLI
output
a
holding
flip-flop for

passed
from
the
is
latched
into

bus.

Control

microprocessor

The

diagnostic

forces

the

command,

'PLI

test

parity

PLI

parity

generator

Logic

logic
arbitrates
the
PLI
protocol
protocol
for
accessing
the
PLI,

synchronization
functions
Figures
4-8
and
4-9
show

between
the PLI

4-9,

PLI

4-10

buffer

parity.

5.2.18

and

output

Generator

generator

(MPTESTPLIPAR),

The

PLI

transmit

data
byte
parity bit

even

Out

out

PLI

formatter

bus.|

Parity

the

1is

with
PLI

at CLK2 time. When the register is loaded,
and loaded into a holding flip-flop.

describe

the

5.2.19

Parity Predictor

Because

the

parallel

loaded

four

correct
parity
mover/formatter.

and

the
PLI
signals,

and

the port
performs

the
CMVR module.
Tables
4-7,
4-8,

signals.

mover/formatter
read,

and
and

registers

shifted

may

several

serial

different

ways,

cannot
be
simply
propagated
through
the
Therefore, a parity predictor is used. The parity

predictor enables the port microprocessor to verify data integrity
through the mover/formatter using combined hardware and microcode
functions to predict correct parity.
The parity predictor
includes a J-K
checkers, and
related control logic.

flip-flop,
two 4-bit parity
The J-K flip-flop is toggled

every

time a CBus or PLI parity bit is detected on a data transfer
in either direction.
The output of the J-K flip-flop,
condition
code
mover
parity
check
(CCMVRPARCHK),
1is
monitored
by
the
microprocessor.
The

parity

predictor

primarily

controlled

several

microprocessor
commands
that
simultaneously
control
other
functions, and therefore does not require much separate microcode.
However, the parity predictor does require two unique commands for
proper control:

Industry-Compatible
parity
predictor

Mode
to

(MPINDSTCOMP)
operate

-sets
correctly

the
in

industry-compatible mode
(see Figure 5-10).
It enables
the parity predictor to calculate correct parity for CBus
D32-D35, which do not pass through the mover/formatter in
industry-compatible
mode.
The
calculated
parity
for
D32-D35 is then subtracted from the calculated parity for
the

entire

This
CBus
2,

Clear

36-bit

CBus

word.

command is executed when transferring data
to the PLI in industry-compatible mode.
parity

check

(MPCLRPARCHK)

clears

from

the

CCMVRPARCHK.

To detect an error, different microcode algorithms are used to
predict the state of CCMVRPARCHK that should correspond to the
number of parity bits detected at the CBus and PLI
interfaces
during data transfers. If the state of CCMVRPARCHK is not correct
when it is checked by the microcode, then it 1is 1likely that an
error
has
occurred
in
the
mover/formatter.
When
the
port
microproccessor senses the incorrect state of CCMVRPARCHK, it sets
DATA

PATH

ERR

(CSR26)

the

CSR.

There
are
six
microcode
algorithms,
each
slightly
according to data format mode (see Figures 5-9 through
direction
of
transfer.
The
algorithms
<check
the
conditions:

different
5-11)
and
following

HIGH DENSITY
~-CBus
to
PLI
~-- CCMVRPARCHK
1is always
toggled
an
odd
number
of
times
for
every
two-word
(9-byte) transfer from the CBus to the PLI.

HIGH DENSITY
-PLI
to
CBus
~-- CCMVRPARCHK
1is always
toggled
an
odd
number
of
times
for
every
two-word
(9-byte) transfer from the PLI to the CBus.

INDUSTRY
COMPATIBLE
-CBus
to
PLI
CCMVRPARCHK
1is
always toggled an even number of times for every one-word
(4-byte)
transfer
from
the
CBus
to
the
PLI.
The
port
microprocessor executes an MPINDSTCOMP command for every
transfer.

INDUSTRY
COMPATIBLE
-PLI
to
CBus
-CCMVRPARCHK
is
always toggled an even number of times for every one-word
transfer (4-byte) from the PLI to the CBus.

CORE DUMP -- CBus to PLI -- CCMVRPARCHK is always toggled
an
even
number
of
times
for
every
two-word
(10-byte)
transfer from the CBus to the PLI.

CORE DUMP -- PLI
an
even
number
transfer

from

to CBus -- CCMVRPARCHK is always toggled
of
times
for
every
two-word
(10-byte)
the PLI to the CBus.

5-40

5.3
The

port

PORT MICROPROCESSOR
microprocessor
comprises

except

the

control

module.

The

microprocessor

ALU,

the

are

following,

located

all

the

which,

microprocessor

Am290l-based

microprocessor
ALU
(physically
located
on
interface/port ALU module, and described in Section 5.1.

EBus

The

microprocessor

Am2910

microsequencer

and

output

functions
.

and

which

includes

associated

control,

input,

The
4K-word
by 60-bit
control
RAM
(CRAM),
load and read/verify path to the MBus

including

The

latches

the

memory

that

60-bit

currently

controller,

the

The

CRAM

control

executing

1K-word

which

microword.

36-bit

1local

RAM

interfaces
to
microprocessor

the

Microprocessor
microprocessor

control
logic
to
timing functions.

MBus

and

5.3.1
Condition Code Multiplexer
The
condition
code
multiplexer
(CCMUX)
multiplexer
that enables one
microword execution sequence.

storage

read

and

written

control

condition

various

16-input
codes

the

port

1l-bit

alter

the

Using

microword skip/condition
(MWSKIPFLDO01-04),
bits 44-47,
the
port microprocessor selects the CCMUX input to pass to the Am2910
TEST COND input.
In the same microcycle, the port microprocessor
enables the test condition by asserting MWCCENA (described below)
on

the Am2910 TEST EN input.
affects
the conditional

code

The state of the selected condition
microsequencer
instructions -- such

certain
Jjump,
return,
load
instuctions.
The
instructions determines the address of the next

executed

and

The

source

and

13-17),

control

the

these
to be

sequence of microprogram execution.

the
the

result
of
microword

conditon

codes

microprocessor

logic
(01,
03-04,
described in Table 5-7.

and

the

CMVR

module

ALU

(02

and

12),

The

10-11).

(00,
or

condition

05-07,

the

EBus

codes

are

Condition Code Definitions

Table 5-7
Condition Code/

MWSKIPFLD 01-04

Definition

CCCBUSAVAIL
00

CBus available -- asserted when the CBus input
buffer is available to receive a word from the

CBus, or the CBus output buffer is available
to be loaded with a word for transfer to the
CBus, or the CBus is not currently active (no
data

CCGRNTCSR
0l

transfers occurring).

CSR
Grant
access to

enables
control

-the

CSR
request
microprocessor
the KL10 does not have access

by
Asserted
if
(MPRQSTCSR)
to

the

microprocessor
port
and status register.

CSR.

-- indicates that the result

CCFEQO

ALU function = 0

CCCSRCHNG

CSR register changed —-- asserted when the KL10

of the last ALU operation was all zeros.

writes the CSR with a CONO, or an EBus parity

port
the
when
Cleared
detected.
is
error
(MPREADCSR).
microprocessor asserts read CSR
port
the
notifies
code
condition
The
the
changed
has
KL10
the
that
microprocessor
contents

CCEBPARERR

EBus

parity

the

CSR.

error —-— asserted

parity error

CCRCVRBUFAFUL
05

buffer A
Receiver
PLI. Asserted when
packet

when

an EBus

is detected.

buffer

full -- originates in the
receive buffer A in the

module

1loaded

with

packet.

CCRCVRBUFBFUL
06

buffer B
Receiver
PLI. Asserted when

packet

buffer

full -- originates in the
receive buffer B 1in the

module

1is

1loaded

with

packet.

CCXMTRATTN
07

the
1in
originates
Transmitter attention -the
in
PLI. Asserted when the transmit buffer

CCEBUSRQST
10

by an EBus DATAO or
request -- asserted
EBus
MPROC RUN state
the
in
is
port
the
when
DATAI

packet buffer module requires attention.

(CSR32

set).

Table
Condition

Code/

MWSKIPFLD

01-04

5-7

Condition

Code

(Cont)

Definition

CCINTRACTIVE

Interrupt

level

active

previously

ALU
ALU

through

processor,

CCMBSIGN
12

Definitions

waiting

for

sign
bit
operation

00)
.

that

interrupt

executed
is

1Indicates

the
KL10

the

request,

©port

micro-

processing.

set -- indicates that the last
set
the
sign
bit
(MSB
or
bit

]

CCMVRPARCHK

Mover

parity

bit

PLI,

check

sensed

during

toggled

from

when

parity

either

the CBus or the
data
transfers
between them.
the
wvalue
(1
or
0)
of
this

DMA

comparing
condition
code
with
a
predicted
value,
the
microprocessor
determines
if
a
parity
error
occurred
during
a
data
transfer
through
the
mover/formatter.
CCCBUSPARERR

CBus

error

asserted

error

detected

CBus.

The

condition

parity

cleared

microprocessor
CCPLIPARERR

word

code

when

read

the

until

it
the

latched

command
controller,

parity

from

PLI

parity
error —— asserted
when
a parity
error
is detected in a word read from the PLI.
The
condition
code
1is
latched
until
it
is
cleared by a command
from the microprocessor

controller.

CCCHANERR

CBus

ERROR

channel

condition

error

signal

code

command

asserted

the

latched

until

from

the

controller.
CCCBLSTWD

when

the

CBus

CBus.

The

cleared

microprocessor

CBus
last word -- asserted when the CBus LAST
WORD
signal
1is
asserted
on
the
CBus.
The
condition code is latched until it is cleared
by
a
command
from
the
microprocessor

controller.

The

field

controls

MWCCENA
1is
example, a
than

microword

the

way

the

condition

code

microsequencer

enable

tests

the

(MWCCENA),

bit

condition

codes.

33,

If
not
asserted,
then
the
condition
is
always met.
For
conditional jump instruction will always branch rather

execute

sequential

microword,

thus

behaving

unconditional jump. If MWCCENA is asserted, the condition is met
CCMUX by
the
through
selected
<condition code
the
if
only
jump
conditional
a
MWSKIPFLDO1-04 is also asserted. For example,
is
code
selected condition
the
if
branch
instruction will
the
then
asserted,
not
is
code
asserted. If the selected condition
is executed.

next sequential microword
5.3.2

Microsequencer

The microsequencer is an Am2910 microprocessor sequence controller
(see Figure 5-14). It selects the address of the next microword to
is configured such that:

be executed. The Am2910

(NXTADDR11-00)

The outputs
to

are always enabled, by tying OUT EN

ground.

incremented on
(+1) to +3 V.

The microprogram counter (uPC) is always
next clock by tying CIN to the incrementer
The

The

PL,

MAP,

other external

load

force

LOAD REG/CTR

feature

disabled

tying

+3 V.

VECT

and

sources

outputs

for

not

are

connected

the DIRECT INPUTS.

NXTADDROO-11

(Y11-YO) VAN

CCMUX — O INSTRUCTION
O] LOGIC
CCENA —

mPC

RUNCLK4

uPC
STACK

||| POINTER

5-WORD

STACK

[

MUX

COUNTER

MWJMPFLDOO0-03

(D11-DO)

JMPADDRO4-11

MR-13769

Figure

the

5-14

Am2910

Block Diagram

5-44

(Simplified)

enable

microsequencer
is
<controlled
by
16
instructions.
The
instruction operation code is encoded
in microword 2910 control,
(MWCTRLFLDO0-03)
bits
52-55),
the
I10-13
inputs
to
the
microsequencer. The instructions are described in Table 5-8.
The

Table 5-8

Microsequencer Instructions

Opcode/
Microcode
Mnemonic

Description

0 JMPZ

Jump to address zero -- not used.

1 CJSR

Conditional

jump

subroutine

both

MWCCENA

and
the condition code
selected
by the MWSKIPFLD
are asserted, transfer the address on the D-inputs
to the Y-outputs, and push the contents of the #PC
(that
1is,
Y+1l) on
the stack.
Otherwise,
transfer
the contents of uPC to the Y-outputs.
2

JMAP

3 CJMP

Jump

using

MAP

Conditional

output

Jjump

not

used.

both

MWCCENA

and

the

condition
c¢ode
selected
by
the
MWSKIPFLD
are
asserted,
transfer the address on the D-inputs to
the Y-outputs; otherwise, transfer the contents of
the uPC

PUSH

Push

the

¥Y-outputs.

and

conditionally

contents
and
the

of the #uPC on
condition code

value

the D-inputs.

are

asserted,
on

load

the

load

counter

push

the

the stack. If both MWCCENA
selected by the MWSKIPFLD

with

the

5 CJSR.RP

CJSR using pipeline or counter -- not used.

6 CONVEC

Conditional

CIJMP
to
counter
or
pipeline
address
-1if
both
MWCCENA
and
the
condition
code
selected
by
the
MWSKIPFLD are asserted, transfer the address on the
D-inputs to the Y-outputs; otherwise, transfer the
address
held
in
the
register/counter
to
the

CJ.RP

vector

jump -— not used.

Y-outputs.

LOOP.ON.CNT

Repeat loop if counter not zero —-- if the contents
of the register/counter are not zero, decrement the
register/counter and transfer the address from the
top of
the stack
to the Y¥Y-outputs. Decrement the
stack
pointer
(POP) ;
Otherwise,
transfer
the
contents of uPC to the Y-outputs.

Table

5-8

Microsequencer

Instructions

(Cont)

Opcode/
Microcode

Mnemonic

Description

11 REPEAT

Repeat

contents

decrement
address

the

from

transfer

Otherwise,

D-inputs

the

transfer

the

zero,

not

the

Y-outputs.

and

contents

the

are

the

zero

not

counter

instruction

the

uPC

1if

both

MWCCENA

Y-outputs.

subroutine

Conditional

12 CONRET

code

condition

and

the

Y-outputs.

return

selected

the

MWSKIPFLD

are asserted, transfer the address from the top of
the stack to the Y-outputs and decrement the stack
pointer; otherwise, transfer the contents of "PC to

CJMP using

13 CJ.PL

the

pipeline and POP -- if both MWCCENA and
by

selected

code

condition

the

MWSKIPFLD

are

the

excutes

to
asserted, transfer the address on the D-inputs
pointer;
stack
the Y-outputs and decrement the
otherwise, transfer the contents of the "PC to the
Y-outputs.

Load

14 LOADCNT

counter

D-inputs

the

into

1load

the

value/address

15 TEST.LOOP

Test end-of-loop condition -- not used.

16 CONT

Continue normally -- not used.

3WAYBRANCH

The

first

Three-way branch -- not used.

microword

that

the

port

microprocessor

an
is
CSR32)
RUN,
MPROC
set
KL10
(the
startup
initial
asserted).
not
MWCCENA
with
CJMP
a
is,
(that
jump
unconditional
This guarantees that the Am2910 register/counter 1is correctly
loaded on the
5.3.3

first executed

instruction.

RAM Address Register

The RAR is a 13-bit register that addresses the next CRAM location
to write or read. The RAR is loaded from MBus D01-D13 when the
KL10 executes a DATOLOADRAR (DATAO with EBus DOO = 1l). It 1is used
to load and read/verify the contents
of the CRAM when the port is
not running (CSR32 reset). The RAR also
address. When the port microprocessor is
set),
the
first CRAM
location
1is
rather than by the microsequencer.

holds the starting CRAM
initially started (CSR32
always
addressed by the RAR

The

60-bit

MBus.

CRAM

word

Therefore,

selected
RAR12

RAR12

the

written

RAR

LSB

Select

the

and

read

two

over

the

30-bit

36-bit

half-words,

follows:

right

CRAM

half-word,

CRAM30-59).

Select

left

the

read/verified

and

CRAM

bank

(most

up/down

(least

significant

half-word,

CRAM00-29).

Because

the

not

also

counter,

loaded

every time the KL10 wants to address a CRAM location.
In order to
write
or
read
a
CRAM
location,
the
KL10
must
execute
four
commands:
a
DATOLOADRAR
to
address
the
first
CRAM
half-word,
followed
CRAM

either

half-word;

DATIREADMW

DATOLOADMW

and

then

write

When

the

port

the

KL10

loads

the

read

being

another

the

DATIREADMW

DATOLOADRAR

other

read

single-cycle

address

executed

mode

into

(CSR22

the

RAR

end of
each
single
cycle.
The next address
is contained
latch address register (LAR),
(see section 5.3.4).
The
the

KL10 can load only the
RAR through the LAR.

5.3.4
The

LAR

every

Latch

Address

13-bit

microcycle.,

by setting DIAG SEL LAR
a DATAI when the port is

the

port

(CSR32

set),

location
LAR

LAR

executed

(CSR22)

the

SINGLE

can

that

read

latches
tool.

halts

the

determined

the

contents

the

CRAM

address

The

KL10

reads
and

on
LAR

executing

while

the

either

the

executed.

DIAG

SINGLE

CYCLE

state

(DIAG

location

the

state

MPROC

the

address

CRAM

set),
at

only

(CSR21) with a CONOLOADCSR,
not running (CSR32 reset).

contains

RUN

state

last

CRAM
The

follows:
port

1is

CYCLE,

halts for
microword
the

are

diagnostic

microprocessor
the

contents

RAR.

the

DATOLOADMW

half-word.

operated

write

and

not

running

CSR22

1is

any reason,
executed.

port

not

the

running

LAR

the

set)

the

single-cycle

and

the

port

the

address

state

(DIAG

contains

single-cycle

microprocessor

the

last

SINGLE

CYCLE, CSR22 set), it automatically halts at the completion of
each
microcycle.
The
LAR
contains
the
address
of
the
next
microword to be executed.
The KL10 executes a DATIREADLAR to
get

the

address,

the

RAR,

and

DATOLOADRAR

CONOLOADCSR

the port microprocessor
it is restarted.

set

load

the

address

MPROC

RUN

(CSR32)

execute

the

back
and

into

enable

single-cycle

when

Reading

preserve
(execute

the

LAR destroys

the current

E buffer data.

Therefore,

the KL10 must read the E buffer
before it reads the LAR. After it

valid E buffer data,
a TESTREADEBUF DATAI)

the KL10 must execute a TESTLOADEBUF DATAO to
reads the LAR,
restore the preserved data to the E buffer. The 12 LAR MSBs are
loaded by CRAMADDROO-11 from the ADDR MUX (see Section 5.3.5). The
LSB is loaded from RAR12. The LAR is loaded at CLK1l time of every
microcycle when the port is not in the single-cycle state, or CLK
4 time of every microcycle when the port is in the single-cycle
state. The LAR output is MBus D01-13. MBus D14-35 are undefined
during

5.3.5

The

LAR

read.

Address Multiplexer

address

multiplexer

(ADDR

that passes either

(NXTADDROO-11)

RARO00O-11

MUX)

two-input

12-bit

the Am2910 microsequencer Y-outputs

the CRAM address

inputs

(see

Figure

5-15).

In the MPROC RUN state (CSR32 set) the next address is normally
fetched from the Am2910 Y-outputs. But, when CSR32 is initially
set, the address of the first CRAM location to be executed is
always

When

fetched

the

always

port

fetched

from

the

not

from

RAR.

running

(CSR32

reset)

the

CRAM

address

RAR.

NXTADDROO-11 -——————-o\
- CRAMADDROO-11

RAROO-11

SELRARADR
GND

& SEL
— EN

V//
MR-13770

Figure 5-15
Note that RAR12
directly to the

Address Multiplexer

(Simplified)

is not passed through the multiplexer,
microprocessor control logic to select

but

goes

the

CRAM

half-word.

5.3.6

Control RAM

The CRAM is a 4K-word by 60-bit RAM with tristate input/output and
55 ns access time. It stores the port microprocessor microcode.
one
read/verify,
and undergoes
1loaded
initially
1is
The CRAM
half-word at a time, from the 30 MBus LSBs (MBus D06-D35) when the

port is not running (MPROC RUN, CSR32 not set). To load one CRAM
location,
four
EBus
transfers
are
needed,
1in
the
following
sequence:

DATOLOADRAR

~--

1load

the

RAR

with

location.

The

KL10

right

bank

CRAM

EBus

DOO

DOl1l-Dl12

significant,

right

the

address

executes

address,

half).

D13

EBus

undefined.

the

DATAO

with

bits

(least

D14-D35

are

-- load data
into the right half of the CRAM
location.
The KL10 executes a DATAO with EBus D00 = 0,
and D06-D36 = data. EBus bits D00-D05 are undefined.

DATOLOADRAR - load the RAR with the address of the
bank CRAM 1location.
The KL10
executes a DATAO with

DATOLOADMW

DOO0

left
4.

the

CRAM

The

D06-D36

port

1load

data

the

address

from

RAR

instead

(most

the

1left

into

data.

EBus

D00-D05

the

half

with
are

(MPROC
by

the

CRAM

EBus

D00

CSR32

set) ,

microsequencer

for
or

during

first

CRAM

initial
location

undefined.

RUN,

5.3.9)
when

is
by

DIAG

microprocessor
is

Am2910.

(see
Section
execution.
However,

set

the

DATAO

running

addressed

CRAM

1is

bits

significant,

undefined.

microcycle,

startup,

are

executes

into

(CSR22)

D13

D14-D35

KL10

currently

every

CYCLE

the

address,

bits

microprocessor

location
strobed

RUNCLK1

EBus

location.

normally
SINGLE

DO1-D12

DATOLOADMW
and

When

half).

left
EBus

always

taken

If either a CRAM parity error or an MBUS error occurs while the
microprocessor
is
running,
CRAM data may be
invalid.
The entire
CRAM
should
be
reloaded
before
the
port
microprocessor
is
restarted.

5.3.7
The

CRAM

two

buff,

CRAM

are

Load
load

used

Buffers
buffers,

load

left

the

CRAM

load

when

buff
the

and

right

port

CRAM

not

load

running

(CSR32 reset).
Each
is a 30-bit tristate buffer that inputs
data, via the MBus, to the CRAM I/O pins (see Figure 5-16).

The

with

CRAM

EBus

loaded

D00

This

DATAO

load

buffer

also

EMUX

EN,

described

The

CRAM

load

the

data.

The left
the

buffers
right

bits
30-59.
The
buffers
running (CSR32 reset).

EBus

CRAM

buff

load

are

DATAOLOADMW

D01-D05

WREN,

and

The

DATAO

undefined).

(with

RAR12)

the

CRAM

1load

latch

complete

5.3.6.

pass-through

load

CRAM

executes

asserted.

Section

are

CRAM

KL10

state

causes

and

the

enables

sequence

00-29,

when

and

EBus

passes
buff

enabled

buffers
MBus

passes

only

and

not

D06-D35

CRAM

MBus

when

D06-D35

the

port

bits
CRAM

not

EBUS D00-D35 —————uo\

LEFT

CRAM

GND/CSR04-35 ———1

BUFF

MPREADCSR ~ ——————{
SEL

+O EN

DATAOLOADMW ——» Oy

RIGHT

CRAM |
LOAD

AND

RAP12

BUFF

CRAM

ADR

1/0 j#— CRAMOO-CRAM29

-»
(I CS
WREN

ADR /O j#— CRAM30-CRAMb59
WREN

MR-13771

Figure

5-16

CRAM

Load

Buffers

(Simplified)

5.3.8
CRAM Parity Checker
The CRAM parity checker checks for odd parity on the 59 MSBs of
the 60-bit microword in the CRAM register. The LSB, MWMARKBIT bit
59,
1is not
1included
in the parity check.
If parity is incorrect
(even), CRAM PARITY ERR (CSR06) and RQST INTERRUPT (CSR05) are set
in the CSR,
and the port microprocessor is halted. A nonvectored
(40 + 2n) interrupt request will be generated over the EBus,

Microword parity is calculated and the state of MWPAR (bit 12) is
set by the microcode assembler to give the microword odd parity.
CRAM PARITY ERR (CSR06) can be force-set in order to halt the port
microprocessor
at a
specific
1location
(breakpoint).
It
1is
then
cleared
by the
KL10
executing
a
CONO with
EBus D24
=
1
(EBUS
PARITY
ERR,
CSR24).
The
port
microprocessor
1is
restarted
by
setting MPROC RUN (CSR32).

5.3.9
CRAM Register
The CRAM register
is a 60-bit register that holds the currently
executing
microword.
It
1is
1loaded
from
the
currently addressed
CRAM
location
by
RUNCLK1
of
every
microcycle.
Then
RUNCLK2,
RUNCLK3,
and
RUNCLK4
<clock
the
execution
of
the
operations
specified by the microword fields.
RUNCLK1l,

RUNCLK2,

RUNCLK3,

and

RUNCLK4

are

CLK2, CLK3, and CLK4 respectively. They
microprocessor is in the MPROC RUN state

gated

outputs

are active only
(CSR32 set).

CLK1,

when

the

5.3.10

Microword

The
definitions
5""90

Field

the

Definitions
microword

Table 5-9

fields

Microword

are

described

Table

Field Definitions

Field/
Bits

Definition

MWJIMPFLD

CRAM 00-11, jump field -- one source for all or part

00-11

of
the
next
CRAM
1location
address.
MWIMPFLD
bits
00-03 are input to Am2910 D11-D8. MWIMPFLD bits 04-11

MBus

D16-D23

are

input

Am2910

D7-D0

via

the

JMP

MUX.

MWPAR

CRAM
12,
parity bit)
-- microword
parity bit.
1Its
state
is
<calculated
and
set
by
the
microcode
assembler to give the word odd parity. Even microword
parity will

MWOUTPUTENA
MWMGCFLD
00-09

CRAM

Am2901
Am2901

13,

OUT

generate

ALU

EN.

data

When

tristate

CRAMPE

(CRAM

output

enable

asserted,
to be

Y-outputs

parity

this

error).

-- controls
bit

asserted

the

enables the
the MBus.

~ CRAM 14-23, magic number field -- provides constants

for the
Am2901
1internal
RAM,
provides
1local
RAM
storage memory
addresses,
and
with
other
microword
fields,
controls the
EBus and CMVR
1interfaces
(see
MWBUSCTLFLD, MWSKIPFLD, and MWRAMODE).

MWSORCEFLD -

CRAM 24-26,

00-02
-

‘source of
follows: -

ALU source
the

R and

field I2-I0 -- selects the

inputs
-

the

Am2901

ALU,

MWSORCEFLD

00-02

5
6

contents

Where:

= The

internal

RAM

location

addressed by MWPORTAFLD 00-03
The contents of the Am2901 internal

RAM

location

addressed

the

Am2901

by MWPORTBFLD

5-51

00-03

Table

5-9

Microword

Field

Definitions

(Cont)

Field/
Bits

Definition

The

data

CNST

00-09,

MBus

26-35

= The

contents

the

Am2901

10-25,

internal

Zero.

MWFUNCTFLD

CRAM

00-02

functions

27-29,

ALU

that

function

the

I5-I3

Am2901

ALU

controls

performs

and

CONST

the

and

inputs.

MWFUNCTFLD
00~-02

Function

plus

minus

4
5
6
7

R
-R
R

and
and
xor

S
S

Xnor

MWDESTFLD

CRAM

30-32,

ALU

00-02

the

Am2901

output

destination
(Y)

will

I8-16
be

the
internal
0-3.

This

field

shifter,
multiplied

also

RAM

location

controls

the

internal

causing

the RAM
divided by 2

and

the

ALU

the
by
MWPORTAFLD
0-3.
internal Q register

MWPORTBFLD

determines

from

internal
RAM
location
addressed
Also determines the input to the
and

addressed

RAM

shifter

and

register inputs to
or
(shifted left or
right).
Therefore,
by
controlling
the
Am290)1
internal
data
paths,
this field determines the destinations of the
Am2901
internal data. The effect of this field is as
follows:
MWDESTFLD

00-02

Gets

ALU

HOLD

ALU

HQOLD

HOLD

RAM

Gets

RAM

HOLD

ALU

HOLD

ALU

Q/2

ALU/2

ALU

HOLD

ALU/2

ALU

0X2

ALUX?2

ALU

HOLD

ALUX?2

Table

5-9

Microword

Field

Definitions

(Cont)

Field/
Bits
MWCCENA

Definition
CRAM

33,

condition

microsequencer
asserted

MWRAMODE

conditional

asserted

conditional

input

asserted.

CRAM

34,

local

storage

00-03

MWPORTBFLD

00-03

bit

the

enable

bit:

test

always

passed;

test

passed

Am2910

MWCCENA

only

not

MWCCENA
CCMUX

storage RAM mode bit —-- selects
global
addressing
to
address
the

either
1local

local
RAM:

MWRAMODE

MWMGCFLD
location

MWRAMODE

asserted

contains

the

contains

the

five

storage

RAM.

local

enable

code

addressing;
address of a

MWPORTAFLD

code

condition

five

not

00-09
in

the

local

LSBs,

MSBs

global

the

entire

storage

addressing.

address
address

asserted

contains

MWMGCFLD

05-09

SADREG

00-04

and
a

RAM.

location

the

CRAM

35-38, port A address field A3-A0 -- the Am2901
internal
RAM port A address
field,
which addresses
one of 16 RAM locations that will be read through the
A latch. This port is read-only.

CRAM

39-42, port B address field B3-B0 -- The Am2901
internal
RAM
Port
B
address
field.
This
field
addresses one of 16 RAM locations that will be either
read

through

locations

the

latch

written.

The

Port

and

are:

A/B
00-03

Name

Description

Temporary

03
04
05
06
07

T3
T4
LNGTH
CMD
FLAG/

Temporary register 3
Temporary register 4
The length of something
Command or message to process
Latest
state
flags
(global
flag word)

REG

INTLK

Address

FLINK

the
command
processed
Forward link of

13
14

BLINK
OFFSET

Backward link of a queue
Base local storage address

FLAGS

command
15

SPARE

interlock

queue

word

queue
a

for

being

queue

being

processed

Table
Field/
Bits

5-9

Microword

Field Definitions

(Cont)

Definition

R.MASK

Mask

isolate

right

half

L.MASK

Mask

isolate

left

half

word

MWSKIPFLD
00-04

CRAM 43-47, skip field -- this field is decoded by
the
microprocessor
COND/SKIP
decoder
and
the
condition

code

multiplexer

(CCMUX).

The CCMUX decodes only MWSKIPFLD01l-04, and
ignores
MWSKIPFLD0OO. The decoded function selects one of 16
condition code inputs to the CCMUX, for input to the
Am2910,

follows:

MWSKIPFLD

CCMUX

01-04

INPUT

CCCBUSAVAIL

CCGRNTCSR

02
03
04

CCFEQO
CCCSRCHNG
CCEBPARERR

05
06

CCRCVRBUFAFUL
CCRCVRBUFBFUL

CCXMTRATTN

CCEBUSRQST

CCINTRACTIVE

CCMBSIGN

CCMVRPARCHK

CCCBUSPARERR

CCPLIPARERR

CCCHANERR
CCCBLSTWD

The
COND/SKIP
decoder
decodes
only
MWSKIPFLDOO,
02-04, and ignores MWSKIPFLDOl. The decode functions
are:

MWSKIPFLD

00,
20

02-04

Function
LOADSADREG
-causes
the
1local
storage
address
register
to
be
1loaded with
the
contents

MWMGCFLDO05-09

SELMBUSFLD
through the
Am2910
Am2910

selects
MBus
jump multiplexer as
D7-DO0
(MWJIJMPFLD00-03 are

D11-D8)

D16-D23
input to
input to

Table 5-9-

Microword Field Definitions (Cont)

Field/

Bits

Definition
22

RDLOCALMEM

-- causes

the

currently

addressed

1local

storage

MBus

location
23

LDLOCALMEM

placed

the

causes

addressed

local

from

loaded

contents

the

storage
the MBus

the
RAM

currently

RAM

location

SELCNSTFLD

selects
MWMGCFLDO00-09
the
constant multiplexer
as
the
10
least
significant
and
the
10
most
significant D inputs to the Am2901 ALU.
through

MWBUSCTLFLD

CRAM

00-02

field, controls the various functions of the
the CMVR interfaces. The field is decoded as

48-50,

bus

control

field

with

the

MWMGCFLD

EBus and
follows:

MWBUSCTLFLD

00-02

Function

No function

Select

PLI

MWMGCFLD

00f01

02-05

PLI

LINK

CONTROL

0-3

PLI

LINK

CONTROL

0-3

function
-to

passes
the

PLI

PLI)

—-

bus

MPSELECTPLI
asserts

the

tristate

outputs

PLI

MPRECVPLI
the

causes

generator

(bad)

MBus

contents
PLI

MPTESTPLIPAR
-—

line

PLI)

output

the

(receive

the

into

SELECT

(transmit

enables

Bus

Select

PLI

MPXMITPLI

loads

(select

the

parity

bus
-

the

PLI

PLI)
of

input

(test
the

buffer

buffer
parity)
PAR

generate

OUT
even

Table 5-9

(Cont)

Microword Field Definitions

Field/

Bits

Definition
MWMGCFLD

function

00-01

-MPENACMUX
the
Enables
outputs

the

MPPLINTOCMUX

CMUX.
enable
tri-state
CMUX
MBus

PLI

CMUX.

into

1input path to
Enables the PLI
PLI
the
allowing
the < CMUX,
input buffer to be asserted on
the

MBus

LSBs

to
CBUF
-MPCBUFTOPLOUT
the
Loads
output' buffer.

buffer

LSBs

into

the

PLI

PLI
C
8

output

buffer

MPCLRCCCODE

MPCLRPARCHK

07-09

Select

condition

of
all
Causes
code.
status
code
condition
on
CCMVRPARCHK)
(except
CMVR module

clear

the
bits
the

cleared

<clear

parity

<condition
the
Causes
check.
code CCMVRPARCHK to be cleared
function

FMTR

MWMGCFLD

00-01

function

MPSHFTFMTR8
-- shift formatter
8 bits. Causes the contents of
be
to
mover/formatter
the

shifted eight bits to
depending
right,
or
the
of
state

the left
the
on
command

MPSHIFTRIGHT

MPSHFTFMTR4A -- shift formatter
4 bits. Causes the contents of
be
to
mover/formatter
the
shifted
four bits to the left
the
on
depending
right,
or
state
of
the
command
MPSHIFTRIGHT

Table

5-9

Microword

Field

Definitions

(Cont)

Field/
Bits

Definition
04

MPCBUFTOFMTR

formatter.

Causes

previously
buffer

stored

MPPLINTOFMTR

buffer

8-bit

the
into

C
the

PLI

formatter.

data

1loaded

mover/formatter
05

CBUF

byte

input

Causes

the

currently

stored in the PLI input buffer
to
be shifted
(four
bits at a
time)
into the mover/formatter
serial

input

command

MPSHFTFMTR4A

lines.

This

executed

with

MPSHFTFMTR8.

executed
with
MPSHFTFMTRA4A,
then only four PLI input buffer
bits
are
shifted
into
the

mover/formatter.

with
MPSHFTFMTR8,
input
buffer
bits
in.

The

executed

all
are

state

8
PLI
shifted

MPRHTNIBFIRST

the
command

determines 1if the four LSBs or
MSBs are
shifted
in
first.
If
MPSHIFTRIGHT
1is
asserted,
the
4-bit nibbles are shifted
into
the
four
mover/formatter
MSBs
and
shifted
right.
Otherwise,

they are shifted
mover/formatter
shifted left

into the
LSBs

MPFMTRTOPLOUT

formatter

PLI

output

buffer.

Causes

four
and

the

8-bit
data
byte
currently
stored
in
the
mover/formatter
PLI
output
register
to
Dbe
loaded
into
the
PLI
output
buffer

MPSHIFTRIGHT
-shift
right.
When
asserted,
either
the
currently
selected
PLI
input

buffer
nibble
mover/formatter

the

four
LSBs

(MVROUT36-39)
are shifted
into
the
four
mover/formatter MSB
serial input lines and shifted
right.
If
MPPLINTOFMTR
is
asserted,
then
the
currently

Table

5-9

Microword

Field

Definitions

(Cont)

Field/
Bits

Definition

selected
PLI
input
buffer
nibble
is
shifted
into
mover/formatter
MSBs
and
shifted right.
If MPPLINTOFMTR
is
not
asserted,
then
MVROUT36-39
are
shifted
1into
the

mover/formatter

shifted

right.

Two

MSBS

4-bit

and

shifts

can
be
executed
in
one
microcycle,
right-shifting
an
8-bit byte in one microcycle

MPRHTNIBFIRST
-right
nibble
first. When asserted, the four

PLI
input
shifted

buffer
into

LSBs

are
the

mover/formatter
serial
input
lines first. When not asserted,
the four PLI input buffer MSBs
are
shifted
into
the
mover/formatter
serial
input
lines first
MPZEROLFTNIB

--—

Zero

left

nibble.
When
asserted,
causes
the
four
mover/formatter
PLI
output
register
MSBs
to
Dbe
forced

loaded
buffer

Select

zero

into

before

the

they

PLI

are

output

CBus

MWMGCFLD
00-01

function

MPSTARTCBUS

Causes
RESET

CBus
to
be

CBus

the

proper

CBus

MPSTOPCBUS

start

CBus.

START
and
CBus
asserted
on
the

—--

time

SELECT
stop

during

cycle

CBus.

Causes

CBus DONE to be asserted on the
CBus at the proper time during
the next CBus SELECT cycle
04

MPSTORECBUS

Causes
asserted

CBus
on

store

STORE
the

CBus

CBus.

the

Table

5-9

Microword

Field

Definitions

(Cont)

Field/
Bits

Definition
proper

time

during

CBus SELECT
is executed

cycle.
at the

the

This
same

command
time as

MPSTOPCBUS

MPWRITEMEM

Causes
asserted

proper
CBus

the

time

cycle.

executed

KL10

the

for

the

the
This

same
data

next
command

time

transfer

memory

MPINDSTCOMP

compatible.

CBus

during

SELECT

memory.

CTOM

MPSTARTCBUS
to

write

CBus

industry

Enables

the

parity

predictor
parity
in

to
predict
correct
industry-compatible

mode.

command

This

executed

industry-compatible

when
CBus

transferring data from
to the PLI interface.

mode
the

MPCBINTOFMTR

buffer to
contents

CBus
input
formatter. Causes the
of
the
CBus
input

buffer
to
be
loaded
mover/formatter
08

MPFMTRTOCBOUT

~--

into

formatter

the

CBus output buffer.
Causes the
contents of the mover/formatter
to
be
loaded
1into
the
CBus
output

buffer

MPSHFTFMTR4B
contents
to be
left

Select

the

shifted

causes

the

mover/formatter

four

bits

the

EBus

MWMGCFLD

00-01

MPLOADCSR

function
--

1load

EBUFO00-EBUF17

into

MPREADCSR

read

CSR.

the

MBus

CSR0O00-CSR35

CSR.

Loads

CSR00-CSR17
Places

Table 5-9
Field/
Bits

(Cont)

Microword Field Definitions

Definition
04

MPRQSTCSR

request

CSR.

Requests
access
to
the
is granted to the
Access

CSR,
port

if the KL10 is
the
accessing

microprocessor
currently
not
CSR.

MPLOADEBUS
be

MPREADEBUS

the

EBus

read

EBus.

contents of
the

asserted
07

the

asserted

MPLOADEBUF

E buffer

the

the contents of

Causes

the EBus

MBus
Causes

EBUF.

load

Causes

EBus.

load

port microprocessor data on the
into the E
MBus to be loaded
buffer

MPRQSTINTR
interrupt.

Causes

request
port to

the

request an EBus PI level 01-07
interrupt (function 00-03). The
is
function
interrupt
determined by an IOP function

control
and

previously

word,

loaded

the

port

word

the

into

microprocessor.
passes

microprocessor

the

EBus

the

The
IOP

asserting

EBus

<code
condition
(CCEBUSRQST)

built

E buffer

redquest

or
examine
MPEXORDEP
to
port
the
Causes
deposit.
or
examine
EBus
an
request
interrupt
deposit PI Level 00
The
04-07) .
(function

function

interrupt

determined by an IOP function
control word, previously built
and loaded into the E buffer by
The
microprocessor.
port
the
1O0P
the
passes
microprocessor
word to the EBus by asserting
Condition

Code

(CCEBUSRQST)

EBus

Request

Table

5-9

Microword

Field Definitions

(Cont)

Field/

Bits

Definition
6

function

MWCARRY

CRAM 51, carry input to Am2901 ALU -- this bit is the
carry into the least significant bit of the ALU. When
MWCARRY 1is 0, a zero is carried into the ALU LSB.
When MWCARRY is 1, a one is carried into the ALU LSB.

MWCTRLFLD
00-03

CRAM 52-55, microsequencer control input field
I0-I13 -- the instruction input field to the Am2910.
Its

functions

MWCTRLFLD
00-03

Instruction
Mnemonic

JMPZ

CJISR

JMAP

3
4

CJIJMP
PUSH

CJSR.RP

)

CONVEC

CJ.RP

10
11

LOOP.ON.CNT
REPEAT

CONRET
CJ.pL

13
14
15
16

LOADCNT
TEST.LOOP
CONT

MWTIMEFLD

are:

3WAYBRANCH

CRAM 56,
current
is

time field -- when this bit

microinstruction

extended

from

320

execution

480

ns.

is asserted,
time

the

(microcycle)

MWSPAREOQOO

CRAM 57,

spare bit 00

-- no function

MWSPAREO1

CRAM 58,

spare bit 01 -- no function

MWMARKBIT

CRAM 59, mark bit -- has no microcode function.

It is

used only for hardware/microcode
be set in any microword, as an

debug. The bit can
sync
oscilloscope

parity calculation nor included
check. Therefore, it can be set

in the CRAM parity
and cleared with no

point.

The

effect on

bit

the

1is

neither

remainder of

5-61

part

the

microword

the microword content.

Output Multiplexer

Microword
5.3.11
put by
The microword output multiplexer (MW OUT MUX) is a two-in
right
the
either
passes
30-bit multiplexer (see Figure 5-17). It
sed
addres
tly
curren
on
or left half-microword (from the CRAM locati
The
ned.
undefi
are
MSBs
MBus
by the RAR) to MBus D06-D35. The six
a
by
only
ed
assert
is
which
multiplexer is enabled by READCRAM,
DATIREADMW command from the KL1O.

NE\\T

CRAMO0-29

= MBUS D06-D35
L

1 1

CRAM30-59

SEL

SELRHTCRAM ——————

READCRAM-—————————*%DLfi/,
MR-13772

Figure 5-17

Microword Output Multiplexer (Simplified)

SELRHTCRAM (generated by RARl2) selects the half-microword input
to the multiplexer as follows:

RAR12 = 0
RAR12 = 1

Select

the

right

hal f-word, CRAM30-59)

CRAM

bank

(least

significant

Select the left CRAM bank (most significant half-word,

.
CRAM00-29)

Jump Multiplexer
5.3.12
nput by 8-bit multiplexer
The jump multiplexer (JMP MUX) is a two-i
) or MBus
that passes either MWJMPFLDO4-1l (jump field 04-11
D16-D23 to Am2910 D7-D0 (see Figure 5-18). MWJMPFLD00-03 are

always input to Am2910 D11-D8.

multiplexer when
MBus D16-D23 are selected as input to the jump
ed.)
MWSKIPFLD0O, 02-04 = 21, (MWSKIPFLDOl is ignor

MW.JMPFLDO4-11 ——-—DN

s JMPADDRO4-11

| 1
MBUS D16-D23 ———
SELMBUSFLD ——» SEL

GND

>Oy

MA-13773

Figure 5-18 Jump Multiplexer (simplified)
5-62

5.3.13
Local Storage RAM
The local storage RAM is a
ns

access

time.

Its

1lK-word

I/0

pins

36-bit

are

tristate

connected

RAM

with

the

MBus.

Approximately
one-half
of
the
local
storage
RAM
locations
are
predefined for specific port functions, and many are completely or
partially loaded at initialization.
The

local

storage

RAM

addresses

through

the

RAM

It
23.

addressed
mode

with

either

multiplexer

(see

global

Section

5.3.14).

local

is loaded from the MBus at CLK2 time when MWSKIPFLDOO, 02-04 =
Data
is output
from
the
local
storage RAM to
the MBus when

MWSKIPFLDOO,

02-04

5.3.14

RAM Mode

The

mode

RAM

passes

22,

Multiplexer

multiplexer

is
a
two-input
5-bit multiplexer
that
MWMGCFLDO0~04 or the contents of the 1local storage
register
(STORADDR0O0-04)
as
the
five MSBs
of
the
1local

either

address
storage

RAM

(bit

selects

34)

address

the

(ADR

0-4)

MSBs.

The

input

(see

Figure

5-19).

MWMGCFLD00-04

microword

MWRAMODE

bit

STORADDROQO-04

11
—t——»

MWMGCFLDO5-07

LOCADDROO0-07

» 0

l—> 1

MWRAMODE

SEL

GND

>OV
MR-13774

Figure

5-19

RAM

Mode

Multiplexer

(Simplified)

The

local storage RAM is addressed in one of two modes: global
local.
In
global-addressing
mode,
all
1024
RAM
locations
addressed by MWMGCFLD00-09. In local-addressing mode, the five

address

MSBs
(LOCADDR00-04)
are
register
(STORADDR00-04),

(LOCADDRO0O5-09)

are

local-addressing

supplied

mode,

one

by
32

locations

When

MWRAMODE

eight

local

the

addressed

not

storage

the

by
the
1local
storage
five RAM address
LSBs

MWMGCFLD05-09.
storage

Therefore,

RAM

"partitions"

are

selected

is
local
storage address
register
are an index, addressing one of
partition.

asserted,

RAM

and

local

addressed by the contents of
the
(STORADDRO0-04); and MWMGCFLD05-09

supplied

or
are
RAM

MWMGCFLD

address

MSBs

00-07

(LOCADDR00-07).

the

The
two
LSBs
(LOCADDRO08-09)
do
not
go
through
the
RAM
mode
multiplexer, but are always asserted by MWMGCFLD08-09. The RAM is
now addressed in global-addressing mode.

address

When

MWRAMODE

asserted,

the

contents

the

1local

storage

address register (STORADDR0O0-04) and MWMGCFLD05-07 are selected as
the eight local storage RAM address MSBs (LOCADDR00-07). The RAM
is

now addressed

5.3.15

local—-addressing mode.

Local Storage Address Register

The local storage address register (LSAR) is a 5-bit register that
in
MSBs
address
RAM
storage
local
five
the
supplies
from
1loaded
initially
is
LSAR
The
mode.
local-addressing
02-04 = 20.

MWMGCFLD00-04 at CLK4 time with MWSKIPFLD0O,

The primary function of the LSAR is to allow the local storage RAM

to be address-organized into 32 partitions, each partition having
queue manipulation functions of the
32 locations. This simplifies
port. Changing the contents of the LSAR changes the five MSBs of
the local storage RAM address, and accesses a different partition.

The five local storage RAM address LSBs are always addressed by
MWMGCFLD05-09 of the microword, allowing any location within a
partition to be addressed without

5.3.16

reloading the

LSAR.

Skip Condition Field Decoder

the
decodes
(COND/SKIP)
decoder
field
skip/condition
The
MWSKIPFLD00-04 field, CRAM bits 43-47, to determine which of the
field functions 1is to be executed. All of the functions are
internal to port microprocessor operation. The skip functions,
encoded in MWSKIPFLD01-04, are given in Table 5-10, as are the
condition functions,

encoded

Table 5-10

in MWSKIPFLDOO,

02-04.

Skip/Condition Function

MWSKIPFLD
01-04

Function
(CCMUX Input)

CCCBUSAVAIL

CCGRNTCSR

02
03
04
05

CCFEQO
CCCSRCHNG
CCEBPARERR
CCRCVRBUFAFUL
CCRCVRBUFBFUL

06
07

CCXMTRATTN

CCEBUSRQST

11
12

CCINTRACTIVE
CCMBSIGN

CCMVRPARCHK

CCCBUSPARERR

CCPLIPARERR

16
17

CCCHANERR
CCCBLSTWD

Table

5-10

Skip/Condition
MWSKIPFLD

(CCMUX

LOADSADREG

SELMBUSFLD

RDLOCALMEM

LDLOCALMEM
SELCNSTFLD

Microdprocessor

microprocessor

functions
of
control logic

the

Control

control

controls

port

microprocessor.

address

(RAR).

all

contains

to:

Write

the

RAM

Write

and

read/verify

Read

Generate

5.4

Logic

1logic

Input)

5.3.17

(Cont)

Function

0l1-04

The

Function

the

latch

CLK2,

©Start

and

CLK3,

stop

the

address

RUNCLK1,

CLK1l,

the

control

RUNCLK2,
and

CLK4

port

RAM

the

timing

necessary

(CRAM).

(LAR).

RUNCLK3,

and

RUNCLK4

from

respectively.

microprocessor

orderly

way.

MICROCODE

This

section

contains
the
flow
diagrams
with
corresponding
of the NIA20 microcode, which performs the following
major functions:
initialization
idle loop,
receive, and transmit
and local command.
(See Figures 5-20 through 5-23.)
descriptions

5.4.1
Initialization
Figure
5-20
is
a
flow
diagram
of
the
initialization microcode
routine. When the port is powered-up, there is no valid microcod
e
in the CRAM. Valid microcode must be loaded and started when
the
port
is
in
the
wuninitialized
state.
At.
the
start
of
the
initialization sequencé,~thé.gdrf”microcode performs self-test
s,
These tests check thé Am2901 addressing and operation, the Am2910,
and“the local store
{LS) addressing. If any of these tests fails,
the microcode loops on the FAIL.SELF-TEST location
in the fatal
error

The

table.

microcode

next sets the LS -- clearing specified locations and
others with bit masks and field masks. When the NIA20
is
being
initialized,
the
port
driver
sets
the
KL
interface
data
channel
to
transfer
three words of
the port control block
(PCB)
over the CBus and into the port. A channel command word
(CCW)
is
loading

set

physical

transfer

PCB

words

containing

interrupt assignment
(PIA)
level assignment,
and a reserved word
channel.

the

PCB

base

address,

physical
interconnect
from KL memory to the

the

(PI)
data

SELF-TEST

DRIVER

DISABLE PORT

LOAD

MCAT

IN CSR

AND PTT

PORT DRIVER

CSR
SET
So

CNTS,
(ZERO
REGS. ETC.)

ENABLE PORT

COMPLETE

ai%iRSATE

PTT, MCAT, AND

GENERAL
HOUSEKEEPING

AND

AND VORDS

Y
3-WORD CBUS
XFER, START
ADDR. OF PCB

!
PIA ASSIGN
CACHE PCB
VARIABLES

LOAD UNKNOWN

PTT POINTERS

DETERMINE UPTT

\DLE

LOOP

QUEUE LENGTH

SET RCV MEM.

ALLOCATION
(32 X512)
WRITE FREE

BUFFER FIFO

Y
SET PHYSICAL
ADDR. RAM
(FROM ROM)

SET

IDLE
LOOP

MR-13702

Figure 5-20

Initialization Microcode Flow Diagram

the

sequence

of this routine, the port starts the channel
START microprocessor command and reads the contents of
these words
into
the
LS.
The
port now has
its PIA and PCB base
address and can
request
interrupts.
After stopping the CBus, the
port writes the physical addresses of the queue interlocks,
FLINKS
and BLINKS, error words, and the CCW into specified LS
locations.
These addresses are determined by the port by incrementing the
PCB
base address value it received in the CBus transfer.

with

The

microcode

CBus

then
writes
standard
(40
+
2n),
increment
interrupts
into
used.
'

for

Finally,
port

the

cache

local

store

addresses

the

basic

examine,

the

are

function

deposit,

LS.

address

that

IOP

Vectored

allocated

control

words

and

examine
interrupts
are

(LSAR)
the

offsets
LS.

These

and

not

the

caches

hold packet or command information and the microprocessor
's state
while the packet or command
is being processed. This information
includes the queue entries FLINK and BLINK, the interlock
word PCB
addresses,
the
buffer
header
address,
and
the
current
buffer
segment

descriptor

(BSD).

Table
Cache

Base

The

caches

5-11

are

listed

Cache

Base

Table

5-11.

Addresses

Address

RCVR

700

LSAR

base

offset

XMIT

enter

640

RCVR

cache

LSAR

base

offset

enter

XMIT

cache

The cache locations are referenced by the LSAR offsets listed in
Table 5-12. These offsets are contained in the microword magic

number field and can be referenced by more than one offset. For
example, offsets CQC.FLAGS, CQC.STATE, and CQC.PAK all have a
value of 4. Therefore, a mask is used to isolate a particular bit
or field in the cache word. The bits, fields, and masks for
CQC.FLAGS, CQC.STATE, and CQC.PAK are defined in an LS block
Table
called the command queue status block flag word. Refer to
For
address.
mask
LS
the
and
words
5-13 for a list of these
state
cache
for
mask
a
1is
173)
example, CSTATE.MSK (LS address
bits 20-23 in the CQC.STATE field.

Table 5-12

Local Store Address Register Command Status Block

Offsets

Offset

Name

Value

CQC.LSAR OFF

CQC.FLAGS
CQC.STATE
CQC.PAK
CQC.OPCODE

4
4
4
5,

CQC.INTRLK
CQC.FLINK
CQC.BLINK

Definition

LASAR offset of this block

Address of PCB queue interlock word
Address of PCB queue FLINK word
Address of PCB queue BLINK word

1
2
3

Flags word
Cache state
Packing mode

Operation code word

FLINK address of this command

CQC.QUEUE
CQC.RSVD
CQC.USEDBUF.O0

6,
7
7

CQC.HXCTID
CQC.LXCTID
CQC.XCTLEN

10
11
12

Transaction ID word 1
Transaction ID word 2
Transaction length

CQC.MAINTID
CQC.BLDRSP.STS
CQC .CODREV

13
14
14

ID, REQID maintenance ID word
Status field for build response

CQC.SEND1
CQC.HDEST
CQC.SEND2
CQC.LDEST

15
15
16
16

CQC .BHDBASE

CQC.SNDNAM

CQC .BHDLEN

Command reserved word
512.buf
of
Number
received

wused

store

frame

Send buffer name

ID,

REQID

microcode

revision

word

level

Sender's station address bytes 0-3
Destination station address bytes 0-3
Sender's station address bytes 4 & 5
Destination station address bytes 4 &
5

Buffer header descriptor address

5-68

Table

5-12

Local

Store

Block

Address

Offsets

Command

Status

(Cont)

Offset
Name

Value

Definition

CQC.SEGBAS

BSD

CQC.BSDBASE

Buffer

CQC.BSDLEN

CQC.FBSD

CQC.NBSD
CQC.BSDRES

25
26

CQC.BHDRES

CQC.CASAVE

CQC.BCOFF

CQC.BLDRSP.OPC

segment

base

segment

BSD

Saved

address

operation
queue

length

CQC.BCRES

32
34

Transfer

CQC.PAKRES

Number

CQC.FRQUE

Datagram

address

response

CQC.WCRES
CQC.PAKLEN

descriptor

code

word

33
of

words
free

bytes

left

queue

transfer
for

no-build

response

CQC.PR_TYPE

Table

5-13
LS

Protocol

Command

Queue

type

from

Status

received

Block

Flag

Address

Bit

Definition

(when

CC.STATE

206

20-23

Cache

word

state

bit

O0=FREE

1=MPKT
2=SPKT

3=XMIT
4=NEW
210

18-19

Packet

format

O=Industry

compatible

l=Reserved
2=Reserved
CS.DIRECTION

123

frame

Word

RAM

Name

CS.FORMAT

from

entry

Transfer

direction

0=CBUS

<=PLI

1=PLI

<=CBUS

on)

At this point in the microcode routine, the idle loop is entered.
The port is still in the unintialized state. The packet or command
state is maintained primarily in flag and status bits. The cache
can be

1in one of

the

following

states:

1.
2.

FREE - Cache
MPKT - Mover

not currently allocated
has packet (unused)

4.,
5.

XMIT - Ready
NEW
- Cache

to transmit
just built.

SPKT - Suspend packet

5.4.2

Idle

(await processing completion)

Loop

Figure 5-21 is a flow diagram of
the idle loop microcode routine.
This
routine
is
performed
after
initialization
has
been
successfully completed and all port microcode functions start from
the idle loop. When a function is completed, the microcode returns
to the idle loop. If the port conducts a power-up or reset, the
idle loop is entered from an uninitialized state.

standard

interrupt

initial
event
microprocessor

INTREQ
flag.
If
condition code is

with

regquest

(40

2n,

1level

01-07)

1is

performed
in
establishing
the
idle
1loop.
compares the
INTREQ mask
from the LS with

condition

the

The
the

the
flag
is
set,
the FEQO
(ALU
function=0)
asserted through the condition code multiplexer

jump to

GEN.INTERRUPT.

If the contents of the CSR have changed, the next idle loop
function examines the CSR by executing a conditional
Jjump to
subroutine CSR.SRV. The jump will be executed when the CSR changed
condition code is asserted through the condition code multiplexer.
The microprocessor
saves
temporary register Am2901

its
copy of
the CSR
(CSRCPY)
in
a
RAM location T1 and reads the new CSR

contents into TO and CSRCPY. It then compares the old and new
CSRCPY for a change in CSR bits 30 (DISABLE) or 31 (ENABLE) or the
setting of CSR27 (CMD QUEUE AVAIL). If either bits 30 or 31 have
set, the microprocessor
was not
not changed or bit 27
to processing of the idle loop routine.

I1f DISABLE
has
been
set
microprocessor sets CSR12
(disable flag). If DISABLE
state,

returns

and
the port
1is
wuninitialized,
the
(disable complete), and FLAGS bit 22
is set when the port is in the enable

the microprocessor performs

the

following:

Sets CSR12 (disable complete)
Clears CSR13 (enable complete)
Clears CSR31 (enable)
Clears FLAGS bit 21 (enable flag)
Sets FLAGS bit 22 (disable flag)
Disables the NIA module.

The

port

disabled

has

now completed

the

transition

state.

5-70

from

the enabled

the

GENERATE
INTERRUPT
TO

INTERRUPT
REQUEST

DRIVER

SERVICE
CHANGE
(ENABLE,
DISABLE,
CMD QUEUE AVAIL)

RECEIVE DONE

RECEIVE

SERVICE

ATTENTION

RECEIVE PACKET

TRANSMIT DONE

SERVICE

TRANSMIT
ATTENTION

XMIT STATUS
AND RESPONSE

SCAN CMD

QUEUE AND
PROCESS CMD

DATA

MOVER

FATAL ERROR

SELF-TEST

MR-13703

Figure

I1f

DISABLE

5-21

Idle

been

cleared,

has

Loop Microcode

the

(disable cdmplete), the FLAGS bit
is not set,
and
the disable
bit
microprocessor returns to continue
If

ENABLE

1is

microprocessor
If

ENABLE

performs

1is

the

set

and

returns

continue

the

port

set

and

following:

the

Flow Diagram

microprocessor

clears

CSR1l2

22
(disable)
if CSR31
(enable)
in the system state word.
The
idle loop processing.

port

was

idle

was

not

loop

disable,

the

processing.

disabled,

the

microprocessor

Set

FLAGS

bit

(run

flagq)

Set

CSR13 (enable complete)
Clear CSR12 (disable complete)
Clear CSR30 (disable)
Clear FLAGS bit 22 (disable flag)
Set FLAGS bit 21
(enable)
Clear

system

Return

Cache

PTT

Cache

MCAT

state

word

bit

continue

idle

loop

processing

1list

(FIFO)

with

addresses

used

(other

available

byte

ROM

address

Load

the

free

Set

NIA

the

(disable)

Write
during

packet

receive

RAM

buffer

reception

buffer

512

sizes are 64 x 256 and 16 x 1024)
Enable the NIA link to receive packets

LINK

the

link

control

setting

ENABLE

The port is now in the enabled state. If ENABLE is cleared, the
microprocessor clears CSR13 (enable complete), clears FLAGS bit 21
1loop
1idle
to
returns
then
and
the NIA,
disables
(enable),
|

processing.

If
the
CMD
QUEUE
AVAIL
bit
1is
set,
it
1is
cleared
by
the
microprocessor.
When
the
ENABLE
flag
is
not
set,
the
microprocessor returns to continue processing the idle loop. If
the
ENABLE
flag
1is
set,
the
microprocessor
sets
the
queue
available in the LS location port queue status (PQS).

The next idle loop function looks for a RECEIVE ATTENTION. If the
receive attention condition code is asserted, the microprocessor
executes a conditional

jump

RECEIVE.DONE.

When the microprocessor detects a TRANSMIT ATTENTION, the transmit
status of any outgoing packet is checked. If a transmit attention
is

present,

conditional

jump

TRANSMIT.DONE

executed.

XMIT ATTN signal indicates a completed or an aborted transmission,
which enables the transmit attention condition code through the
condition

code multiplexer.

The last idle loop event in the routine causes the microprocessor
to check the queues for a command queue entry by comparing the LS
location PQS contents with the ALL.QUES mask.
If
all command
gqueues are not empty, a jump to SCAN.QUEUES is executed. If all
the queues are empty, the FLAGS bit 8 (CACHE.FULL) is tested and,
if

set,

jump

jump to

SCAN.QUEUES

executed.

executed,

the

command

process

is
selected.
If
a
cache
is
ready
for
processing,
the
microprocessor activates the cache and Jjumps to SEND.PACKET. If
none
of the caches is ready for processing, the code looks for a
command queue entry to process.
If a command queue entry is
available,

processing

the

microprocessor

new command.

Jjumps

BUILD.CACHE

start

5.4.3
Figure

Receive
5-22 is a flow chart of the NIA receive
routine is called when the RCV ATTENTION

This

microcode
signal is

routine.
asserted

from the idle loop. The RCV ATTN signal indicates that an incoming
frame
has
passed
the
hardware
address
filtering
process
and
storage space is available in the NIA receive buffer.
The

microprocessor

receive

errors

status

mask

counter

When

free

disabled
If

then

are

1is

built

and

free

buffer

parity

jump

receive
transfer

response

buffer

error

status,
is

status

and,

stopped,

field,

and

any

error

the

error

ATTN

Return

the

free

detected,

receive

RCV

detected,

(location

7766)

the

NIA

module

halts

the

operation.

following

are

performed:

mask

Reset

error

PLCRPE

the error
Increment the

there

the

data

incremented.

Set

reads

detected,

idle

buffer

fail

counter

loop.
parity

error

free

buffer

error

no other error present, the number of used buffer entries is read
from receive
status
for the valid number of buffers.
If a valid
number
of
buffers
cannot
be
obtained,
the
corresponding
error
event count is incremented and a return to the idle loop executed.
The

receive

buffers.

buffer

cache

After

list

latched

successfully

read

the

after

obtaining

correct

the

number

the

valid

number

receive

cache,

the

times,

used

indicated

the receive status. With the selection of the first receive buffer
pointer in the used buffer list,
the destination address is read
and
then
filtered.
The
following
bytes
are
read
from
the
NIA
receive buffer:

The

Destination

Source

Protocol
Data

CRC.

filtering

physical,

listed

type

process

multicast,

addresses

determines
or

broadcast

the

destination

address

multicast

that

address

matches

table

any

the

(MCAT).

match
of
the
destination address
in
the
received
frame
results
from this filtering process, the no-match discard frame counter is
incremented
and
the
frame
discarded.
If
the
filtering
process
matches
cached,

an
If

type

used

address, the
the protocol

before

source address and protocol type
type is not enabled, an unknown

performing

delink

queue

operation.

(PT)
are
protocol

RCV ATTN

READ
RECEIVE

STATUS

ANY

RCV ERROR

VES

INCREMENT

COUNT AND

BUILD ERROR
STATION MASK

GET NUMBER

]
OF
USED BUFFERS

VALID
NUMBER

INCREMENT
COUNTER

RESET

RECV ATTN

CONNECT

FREE
BUFFER

DISABLE LINK
AND JUMP
PLCRPE-7766

SET CSRIDLE

RECEIVE CACHE

(::)- JUMP
TO IDLE
LOOP

IDLE

CACHE
RECEIVED

LOOP

READ USED
BUFFER LIST
CORRECT

NUMBER OF TIMES

MR-13704

Figure

5-22

Receive Microcode Flow Diagram
(Sheet 1 of 6 sheets)

5-74

USED

YES

BUFFER

WRITE

BUFFERS
WITHOUT
PARITY ERROR

Y
RESET RCV

START FILTER
SELECT RCV
BUFFER AND

ATTN AND
INCREMENT
COUNT

| READ DEST. ADDR

INCREMENT

NUMBER OF
NO MATCH
DISCARD FRAMES

PTT
ADDRESS

MATCH

/e pHYSICAL

MULTICAST

BROADCAST

YES
DISCARD

CACHE

FRAME

SOURCE

ADDRESS

INCREMENT

ECHO

DISCARD

CACHE

FRAME

PROTOCOL TYPE
SET UNKNOWN

CACHE

PROTOCOL TYPE

SET POINT FLINK

ENABLE

TYPE

USE UNKNOWN
FREE QUEUE

SET POINT FLINK

SETTO

USE RIGHT
FLINK

MR-13705

Figure

5-22

Receive Microcode Flow
(Sheet 2 of 6 sheets)

Diagram

DELINK
QUEUE

WAIT
THEN TRY
AGAIN

INCREMENT
DISCARD COUNT
‘

FOR RIGHT
PTQ AND

OVER-FRAMES

WRITE FREE
QUEUE WITH

USE

USED — RESET

UNKNOWN

RCV ATTN

QUEUE
LENGTH

YES

READ LENGTH
FROM FREE

QUEUE HEADER

READ
BSD BASE

ADDRESS

INCRMENT

COUNT, SET

CACHE
BSD

FREE QUEUE
ERROR BIT AN
REQ-INT

COMPARE
BSD LENGTH
TO
BUFFER LENGTH

USE RECEIVE

BSD
BIGGER

USE BSD SIZE
FOR
MOVER COUNT

BUFFER SIZE
FOR

MOVER COUNT

MR-13706

Receive Microcode Flow Diagram

(Sheet

5-22

Figure

sheets)

DIVIDE SMALLER
BYTE COUNT
BY 4 FOR WORDS

SAVE FULL
WORD AND
PARTIAL WORD
COUNTS

Y
BUILD CCW
AND
START CBUS

Y
LOAD WC-1
TO AM2910
LOOP CNT

READ BYTE
FROM RECEIVE

BUFFER TO PLI
INPUT BUFFER

INCREMENT
RUNNING
BYTE COUNT

PLI INPUT

BUFFER TO
FMTR AND
SHIFT LEFT

ALIGN LAST
WORD AND

YES

WRITE TO

MEMORY

NO
ABORT (STOP)

CBUS

YES

MR-13707

Figure

5-22

Receive

(Sheet

Microcode

6 sheets)

5=-77

Flow

Dlagram

FOR

UPDATE
BYTE

ALIGNMENT

CNT

SHIFT FMTR

WRITE LENGTH
IN

CBUS
AVAILABLE

DEC
TIMEOUT

RESPONSE

YES

WRITE CBUS

PLAN
CRAM PE
LOC 7757

WITH

WRITE

DADD

REMAINING
QUEU INFO

SADD

PTT

FMTR

WRITE FREE
BUFFER WITH

USED — RCV ATTN
INCREMENT

RCV FRAME CNT

BSD OR
BUFFER

EMPTY

!
DELINK

QUEUE

STOP
CBUS

WAIT
THEN

RETRY

CALCULATE
BYTES
REMAINING
IN BSD AND

YES

BUFFER
LINK

QUEUE
LESS
THAN 4

BYTES IN
RCV
BUFFER

SET

REQUEST
INTERRUPT

SELECT NEXT
RCV BUFFER

AND

INITIAL SIZE
YES

BSD

ZERO

MR.13708

Figure

5-22

Receive Microcode
(Sheet

5-78

sheets)

Flow Diagram

READ BYTE
AND
DEC COUNTS

GET NEXT
BSD

NEXT
BSD

BUILD

ERROR
STATUS

YES

SET BSD
COUNT TO
WRITE
WORD

NEW VALUE

DISCARD

FRAME

CLEAR CACHE
LOCATIONS

MARK AS FREE

WRITE USED
BUFFERS TO
FREE FIFO

SET

RESET

IDLE

RCV ATTN

IDLE

LOOP

MR-13709

Figuré 5-22

Receive Microcode Flow
(Sheet 6 of 6 sheets)

Diagram

When connecting
entered and the
the

used

to the cache fails, a discard frame subroutine is
frame discarded. In the discard frame subroutine,
buffers are written into the free buffer list FIFO, the
reset,
and a flush cache subroutine performed. A flush

RCV ATTN
cache subroutine clears the cache
free before returning to the idle

locations
loop.

and

marks

the

cache

A delink queue operation
removes an entry from a free
manipulating
entry
FLINKS
and
BLINKS
in
KL10
memory.

queue by
The
port

first generates an EBus interrupt to access an interlock word. If
the queue was interlocked, the port waits for 512 cycles
(163.84
us)
and
then
jumps
back
to
the
start
of
the
allocate
queue
subroutine.

the

queue

was

empty,

Increment

Write

used

Reset

RCV

buffers

the

Set

interrupt

free

CSR

read

port

from

the

free

protocol

free

queue

request

flush

queue

steps

occur

type

discard

sequence:
count

list

ATTN

Set

queue header.

following

respective

Execute a
known PT)

When

the

error

cache

the queue
control

bit,

this

known

subroutine

known

PT,

unknown

block

its

(whether

length

free

queue

empty

Use

the

smaller

the

data

mover

read

from

the

its

length

(PCB).

the

BSD/receive

buffer

receive
1is
the

lengths

set

count

°
®
®

Divide word count by four for a byte
Save full word/partial word counts
Build channel command word (CCW)

Start

)

Load
loop

word count
counter

Read

receive

input
Shift

buffer
each 4

Write

each

the

queue,

The BSD
is
then cached and
its
length compared to the
buffer
1length
to
determine
which
of
the
two
1lengths
smaller. A functional sequence then follows, including:
)

flag

count

CBus

buffer

When

the

loop

read

subtracted

count

minus

one

into

the

Am2910

microsequencer

buffer
to
the
port
1logic
interface
incrementing the running byte count
bytes (full word)
into the formatter

full
is

word

empty

zero,

from

the

host

(Loop

using

count

the

loop

BSD

length

CBus

until

the

total

(PLI)

BSD

zero)

stops
and

and
the

receive

bytes
buffer

length. Any partial words that remain in the BSD or receive buffer
are moved and the
next BSD accessed, if the BSD equals zero. If
the receive buffer equals zero,
the next buffer
is selected. A
return to the beginning of the loop, where the smaller size buffer
is selected, restarts the loop to repeat this transfer process.

Each

time

loop,

4-byte

test

for

word

read

from

end-of-frame

the

(EOF)

receive

signal

detection

of an EOF stops the loop and aligns
word as
it
is written
to
the
host over
parallel
transfer completed,
the CBus is then
and the following cleanup sequence occurs:
last

)

Update

byte

Write

the

and

PTT

When
empty

response

buffers

the

used

RCV

ATTN

the

response

entry

and

the

receive

response

entry

queue

has

been

bit

interrupt

the

frame

5.4.4

Transmit

and

5-23

microcode
a

CSR

Local

change

request

source

address,

free

list

linked

the

flag

CSR,

set.

the
if

The

queue,

the

queue

was

cache

then

Command

diagram

This

routine

indicates

address,

count

set

flow

routine.

format for the
CBus. With the
halted by the port

queue

flushed.

Figure

the

queue

successfully

available

the

destination

the

Reset

Increment

the

The

counts

length,

Write

Link

buffer
in
conducted.

command

the transmit and local command
started from the idle loop when

queue

available.

With

the
command
queue
available
bit
enabled
in
the
CSR,
the
microcode scans the queue for command entries. If a command entry
is present,
the code disables the command queue available bit in
the CSR, marks the queue available in the port gueue status (PQS),
and then returns to the idle loop.
If no command queue available
entry

can

Next,

accessed,

the

subroutine

returns

from

entries

the
1idle
1loop,
if
there
will
try
to
delink
an
entry
uses the same subroutine).

queue

1is

microcode

the

available
empty;

read
PLI

bit

the

into
data

was
and

empty,
returns

the

cache,

FLINK

saved

cache,

and

the

flag

transfers.

microcode

idle

CC.XMIT

the

queue

When

four-word

set

idle

loop.

marked,

delinking

clears

loop.

the

(all

the

PQS

the

queue

the

queue

command
is

header

indicate

CBus

not
is

READ

CSR

TURN OFF

CMD QUEUE
IN CSR

MARK QUEUE
AVAILABLE
IN PQS

TRY DELINK
CMD QUEUE
ENTRY

MR-13710

Figure 5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet

sheets)

WAIT

THEN
RETRY

CLEAR CMD
AVAIL BIT

IN PQS

IDLE

LOOP

SAVE FLINK
IN CACHE

READ 4-WORD
QUEUE HEADER
INTO CACHE

SET FLAG
CC.XMIT
CBUS—PLI

RSP

SET FLAG
CC.BLDRSP

BIT SET IN
OPWORD

GET OPCODE
AND
DETERMINE CMD

READ

LOAD
PTT

DATAGRAM

COUNTERS

READ

RCV

STATION

WRITE
STATION

ADDR

MR-13711

Figure

5-23

Transmit and
(Sheet

Local Command Microcode
2 of 19 sheets)

Flow

Diagram

SEND DATAGRAM

PAD
BIT SET IN
OPCODE

YES

SET FLAG
NEED.PAD

YES

ICRC

SET

SET FLAG
SELF-DIRECTED
DATAGRAM

'\ YES

BSD
BIT

SET FLAG
BSD

SET

NO
[«

SET PACKING
MODE FOR
LATER XMIT
DISPATCH

READ WORD

LENGTH FROM
COMMAND

LENGTH

ABOVE
MIN.

BUILD ERROR
RSP AND LINK

ON RSP QUEUE

IDLE
LOOP

CACHE PT, FREE
QUEUE ADDR,
DEST.ADDR

FROM COMMAND

MR-13712

Figure

5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet

3 of

sheets)

READ BSD
BASE ADDR

A
CACHE

READ BSE AND

MOVER CNT

l@—

CACHE SEG.ADDR

NEXT PKT.LENGTH

SET CACHE
STATE TO
NEW

SUSPEND
CACHE

SET

IDLE

Loor

FLAG
XMIT.PEND

REST NIA
XMIT BUFFER

ADDR

WRITE CACHE
DEST.ADDR TO
XMIT BUFFER
THRU FMTR

WRITE SOURCE
ADDR TO XMIT
BUFFER THRU
FMTR

MR-13713

Figure

5-23

Transmit

and
(Sheet

Local Command Microcode
4 of 19 sheets)

Flow Diagram

WRITE 2-BYTE
PROTOCOL TYPE
TO XMIT BUFFER

WRITE LENGTH
TO NEXT 2-BYTE
IN XMIT BUFFER

1
DETERMINE

@—- SMALLER

COUNT, IF BSD

USE B8SD
SIZE FOR
MOVER

BSD

SMALLER

USE
PACKET
LENGTH
=

DIVIDE SMALLER
BY 4 FOR
WORD COUNT

SAVE FULL
AND PARTIAL

WORD COUNTS

BUILD CCW
AND START
CBUS

MR-13714

Figure 5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet

5 of

sheets)

LOAD WC-1
* TO AM2910
LOOP CNT

—®»

" GET WORD

FROM HOST

TO FMTR

SHIFT FMTR

f—. ‘OUTPUT BYTE

TO PLI OUTPUT

!
PLI OUTPUT
TO AM2901

LOOP CNT
ZERO

ANY
PARTIAL

WORD

READ LAST
WORD OVER
EBUS TO FMTR

MR-13715

Figure

5-23

Transmit and
(Sheet

Local Command Microcode
6 of 19 sheets)
'

Flow Diagram

SHIFT FMTR

—#=

OUTPUT BYTE

TO PLI

!
PLITO
AM2901

STOP
CBUS

CALCULATE

NEW COUNTS

SUBTRACT

FLAG

FRAME LENGTH

NEED.;’AD
SE

FOR MINIMUM
PACKET SIZE

Y
LOAD RESULTS

GET NEXT
BSD AND

MINUS 1 INTO
AM2901 LOOP CNT

SET CNT

WRITE BYTE

—

OF ZEROS TO

AM2901

LooP

COUNT
ZERO

YES | WRITE

TRANSMIT

END OF FRAME

MR-13716

Figure 5-23
:

Transmit and Local Command Microcode Flow Diagram
(Sheet 7 of 19 sheets)

5-88

CLEAR FLAG
XMIT.PEND

SET DISABLE
XMIT CRC

SELF- \ YES
DIRECTED

IN LINK CNT.
REGISTER

SET FLAG
XMIT.BUSY

TELL NIA

TO XMIT
FRAME

SET CACHE

STATE TO
XMIT

CONNECT
TO XMIT

CACHE

READ
XMIT

STATUS

MR-13717

Figure

5-23

Transmit

and

(Sheet

Local
8

Command
19

Microcode

sheets)

Flow Diagram

INCREMENT
CNT AND
BUILD MASK

YES

COLLISIONS

I
INCREMENT
CNT AND
BUILD MASK

RESTART
RETRY

l
INCREMENT
CNT AND
BUILD MASK

]
READ
TDR

HALT
FATAL ERROR
LOC.7767

ANY MORE
RETRIES
\.

INCREMENT
CNT AND
BUILD MASK

OEC RETRY
CNT., INC
ERROR CNT.,
CLEAN STACK

INCREMENT
CNT AND
BUILD MASK

HEARTBEAT

CLEAR FLAG
XMIT.BUSY
MARK CACHE
AS NEW

I
RESTART | YES ANY ERROR

RETRY

ANY

over

RETRIES

16
INCREMENT

CORRECT
COUNT

Figure 5-23

\U7ES

INCREMENT

CNT, BUILD

MASK, READ TDR

Transmit and Local Command Microcode Flow Diagram
(Sheet 9 of

5-90

19 sheets)

CLEAR DISABLE
XMIT CRC

SELF-

DIRECTED

L
CLEAR FLAG
XMIT.BUSY

UPDATE
RUNNING BYTE

COUNT

UPDATE
XMIT

COUNT

)
RSP

BIT SET

SAVE COMPLETE

@—D OPCODE WORD
IN CACHE

MR-13719

Figure

5-23

Transmit and deal Command Microcode Flow Diagram
(Sheet

sheets)

TRY TO

LINK ON
RSP QUEUE i|

WAIT

THEN

RETRY

YES

READ RSP

QUEUE BLINK

SET FLAG
QUEUE EMPTY

_
LINK RSP
ONTO END
OF QUEUE

Y
RESET

INTERLOCK

BUILD MASK
FOR INTERRUPT
AND SET FLAG
INT.REQ

O—

"MARK CACHE
AS FREE

MR-13720

Figure

5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet 11 of

5-92

sheets)

SET CSR
RSP QUEUE
AVAILABLE'

GENERATE
NON-VECTOR
INTERRUPT

Y
CLEAR
INT.REQ

IDLE
LOOP

MR-13721

Figure

5-23

Transmit

and

(Sheet

Local
12

Command
19

Microcode

sheets)

Flow Diagram

° LOAD MULTICAST ADDRESS TABLE
SET FLAG
LCL.CMD

32 FOR COUNT
MCAT STARTING
ADDRESS IN PCB

BUILD CCW
WORD AND
START CBUS

|
|
I

READ WORD
FROM CBUS
TO AM290t1

Ly
[
|

WRITE LS

WITH AM2901 |

|
I
I
I
|
|
|

J
REPEAT ABOVE
32 TIMES

NO AUTO LS
INCREMENT
FOR LOOP

FLAG
CC.BLDRSP

WRITE 4-WORD
QUEUE HEADER
TO HOST MEMORY

MFA-13722

Figure 5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet 13 of

19 sheets)

CLEAR FLAG

LCL.CMD

LOAD PTT

SET FLAG
LCL.CMD

BUILD CCW
AND

r———-——=
=7

START CBUS

N
READ WORD
FROM CBUS
TO AM 2901

[

WRITE LS

|
|

WITH AM2901

REPEAT

ABOVE
47 TIMES

CC.BLDRSP

MR-13723

Figure

5-23

Transmit

and

(Sheet

Local
14

Command
19

5-95

Microcode

sheets)

Flow Diagram

WRITE 4-WORD
QUEUE HEADER

TO HOST MEMORY

Y
CLEAR FLAG
LCL.CMD

READ COUNTERS

SET FLAG
LCL.CMD

SET FLAG
CLR.CNT

|
WRITE 4-WORD
QUEUE HEADER
TO HOST MEMORY

BUILD CCW
AND

START CBUS

44 WORDS
RDCNT BUFFER
ADDR

MR-13724

Figure

5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet 15 of 19 sheets)

READ WORD

:
:
g
:
:
FROM LS

TO AM2901

WRITE HOST

WITH AM2901

REPEAT

ABOVE
44 TIMES

NO | CLEAR FLAG
LCL.CMD

YES

CLEAR LS
LOCATIONS
CONTAINING
NET COUNTERS

Y
CLEAR FLAG
LCL.CMD

MR-13725

Figure

5-23

Transmit

and Local Command Microcode
(Sheet 16 of 19 sheets)

Flow Diagram

e DATAGRAM RECEIVE

WRITE PLI

SET FLAG
LCL.CMD

Y
READ PLI

COMMAND WORD
INTO AM2901

'
DETERMINE
FUNCTION

EXECUTE
PLI
FUNCTION

FLAG

CC.BLDRSP

WRITE 4-WORD
QUEUE HEADER
TO HOST MEMORY

WRITE PLI

COMMAND
WORD

MR-13726

Figure

5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet

sheets)

READ PLI

SET FLAG
‘LCL.CMD

READ PLI
COMMAND
WORD

!
DETERMINE

FUNCTION

EXECUTE

PLI

FUNCTION

- FLAG
CC.BLDRSP

SET

WRITE 4-WORD

QUEUE HEADER
TO HOST MEMORY

WRITE PLI
COMMAND
WORD

MR-13727

Figure

5-23

Transmit

and

(Sheet

Local
18

Command
19

Microcode

sheets)

Flow Diagram

WRITE STATION ADDRESS

READ STATION ADDRESS

READ ADDR,

WRITE 4-WORD

MODE BITS,

QUEUE HEADER
TO HOST MEMORY

AND RETRY CNT

FROM COMMAND

WRITE NIA
RAM WITH

WRITE STATION
ADDRESS FROM

NEW ADDR

LOCAL STORE

GET PRESENT

WRITE MODE
BITS AND

MODE BITS

VERSION
NUMBER

YES

CHANGE
MODE
BITS

FLAG

CC.BLDRSP

SET

WRITE 4-WORD
QUEUE HEADER
AND STATION
ADDRESS

MR-13728

Figure 5-23

Transmit and Local Command Microcode Flow Diagram
(Sheet

5-100

sheets)

Next,

the

is
of

in the operation
command.

set
the

This
the

microcode

transmit

into

Send

datagram

Load

multicast

Load

protocol

Read

counters

Datagram

[]

set

code

microcode
code

Write

WOWCOOJO0
U
W N

—

operation

will

routine
nine

type

CC.BLDRSP,

and

determine

then

the

response

operation

dispatched

according

subroutines:

table

bit

code

(PTT)

receive

port

logic

Read

PLI

Read

station

Write

flag

word

interface

(PLI)

address

station

address

l.
Send Datagram Subroutine
Initially, the microcode in this subroutine looks at the PAD,
the
included
cyclic
redundancy check
(ICRC),
and the buffer segment
descriptor
(BSD)
bits
in
the
operation
code
word
and
sets
the
corresponding

from

the

determine

error

queue,

flag,

command
if

and
the

the

PAD

the

ICRC

bit

set

the

port

driver

the

BSD

bit.

the

microcode

code

and

reads

has

been

format,

the

length

check

made

exceeded.

not,

onto

continues

field,

datagram

reads

set,

1linked

code

FLAGS

then

the

response

the

added

4-byte

ICRC

absence

the

CRC.

self-directed
frame. If the

address,

the

not

of a
This
feature
must
be
used
1in
transmitting
datagrams
to
maintain
the
CRC
integrity
of
the
ICRC is not set, the port next examines the setting

port-supplied

Next,

then

set,

the

and

size

built

microcode

flag

frame

flag

instruction.

The

PAD

minimum

response

needed.

the

caches

the

destination

BSD

base

protocol

address.

address

and

then

case,

type,

the

BSD

the

flag

caches. the

free

BSD.

queue

set,
In

the

either

the mover counts are
cached
and
the cache state
is
set
to
If
either
flag XMIT.BUSY or XMIT.PEND
is set,
the cache
is
suspended and
the port returns to the
idle loop. When both flags

NEW.
are

not

set,

the

[

Set

flag

)

Reset

Write

occurs:

XMIT.PEND

NIA

through
°

following

transmit

buffer

address

<cached

destination

data

mover/formatter

Write

source
address
to
mover/formatter
Write 2-byte protocol type

5-101

address

transmit

buffer

transmit

buffer

through

buffer.

data

The code now tests the PAD flag and if the flag is set, the actual
length is written to the next 2 bytes in the transmit buffer. If
not, the subroutine continues on to perform the following set of
functions:

Use the smaller BSD/packet size for data mover
Divide smaller length by 4 for word count

1 .

2 .

Save full and partial word counts

3 .

Build channel command word (CCW) and start CBus
Load word count minus one to Am2910 loop count
Read word from host to formatter over CBus

4
5

6
7 .
8 .

Loop back for next word, if loop count is not zero
Loop back and shift, if full word (4 bytes)

Shift formatter output byte to PLI output
1 0. Move PLI output to transmit buffer.

9 .

When the loop count is =zero, the microcode checks for any
remaining partial words (1-3 bytes). If any partial word remains,
the last word is read over the EBus to the mover/formatter and
then shifted out to the transmit buffer.

The CBus is then stopped and the BSD flag tested. If it is a BSD,
the new counts are calculated. When there are more bytes to
transfer, a jump-back repeats the ten functions. If this is not a
BSD or if the transfer is complete, the PAD flag is tested. With
the PAD set, the remaining bytes are padded with zeros. The
transmit end-of-frame (TX EOF) is written when padding is done or
if the PAD is not set. Both flags XMIT.PEND and ICRC can now be
cleared, but if they are set, the transmit CRC in the link control
register

disabled.

With the flag XMIT.BUSY set, a transmit frame instruction to the
NIA hardware is executed. The cache state is set to transmit and
the port returned to the

idle loop.

The assertion of transmit attention in the idle loop initiates a
connection to the transmit cache and reads the transmit status.
When the status 1is <checked and errors are indicated, the
corresponding error counter 1is incremented and an error status
built. The following
°
®
°
°
®

is a list of error types:

Late collisions
Transmit parity error
Loss of carrier
Transmit too long
Heartbeat

When there are

error

transmit errors,

the microcode restarts the retry

subroutine.

Detection of a transmit buffer parity error causes the following
to

performed:

5-102

Clean

the

Clear

flag

Mark

cache

Next,

recache

retries
the

stack
XMIT.BUSY
as

are

command,

transmit again.
If
at location 7767.

errors

detected,

the

NEW.

not

exhausted,

reloads

the

retries

the

microcode

transmit

are

buffer,

exhausted,

jumps

and

the

back

attempts

port

error

microcode

other

checks

than
for

‘transmit

collision

buffer

retry

all

set,

error

XMIT.BUSY

the

cases,

bit
is

then

running

the

cleared
byte

ICRC

cleared,

count

tested

1link

and

counted.

flag

the

and

control

and

disable

error

the

CRC,

The

1is

then

than
16
the time

transmit

incremented

the

and

increments
the
corresponding
error counter.
When
more
retries have been attempted, an error status
is built and
domain reflectometry (TDR)
read.
In

halted

flag

detected,

transmitted

frames

the response flag is not set when checke
d, the cache is marked
free
and
the
port
returned
to
the
idle
loop.
When
the
response
flag
is
set,
the
completed
operation
code
word,
including
the

error

status,

Next,

the

saved

microcode

cache

attempts

and

link

written

the

into

response

With an empty queue, the flag INTERRUPT.RE
QUEST is
is then marked as free and the port returned
to the
Next,

from

the

idle

loop,

request,

which

causes

EBus

idle,

the

and

is
a

and

Load

The

load

performs

the
Sets

Builds

Starts

the

Reads

flag

Writes
Repeats

subroutine

four-word

the

load

the

flag

When

the

in the CSR is set
interrupt request flag

loop.

entered

multicast.

when
This

word

the

queue

subroutine

(CCW)

from
4

Am2901

(LS)

with

and

above

tests

header

CBus

store
5

the
is

the

flag

Am2901
times

for

the

CC.BLDRSP.

written

the

(since

CC.BLDRSP

not

5-103

set,

the

there

loop).

If
host

the

flag

memory

and

flag
LOCAL.COMMAND
is cleared.
The port then saves
operation code word
in cache and tries to link onto

queue.

interrupt

increment

then

queue

command

local

steps

set
EBus.

LOCAL.COMMAND

CBus

word

idle

Subroutine
subroutine
is

channel

the

idle

queue.

set. The cache
idle 1loop.

bit

The

the

for

queue

following:

automatic

tests
for

memory.

the

Table

table
code

operation

wait

generated.

returned

Multicast

multicast

command

This

port

available

interrupt

the

microcode

port

response

nonvectored

cleared

the

host

onto

cache

the
the

set,

the
complete
response

flushed.

3.
Load Protocol Type Table (PTT) Subroutine
The load protocol type table (PTT) subroutine is entered when the
queue
command
operation
code
is
a
1load
PTT.
This
subroutine

YU
W N

performs

the

following:

Sets

Builds

the

flag

.
.
.

Starts the CBus
Reads word from CBus
Writes local storage

Repeats

LOCAL.COMMAND

CCW

steps

and

to the Am2901
with the Am2901
5 above 47 times.

This
subroutine
then
tests
the
flag
CC.BLDRSP
and
if
set,
a
four-word
queue
header
1is
written
to
host memory
and
the
flag
LOCAL.COMMAND
1is
<cleared.
The
port
then
saves
the
complete
operation code word in cache and tries to link onto the response
queue. If the flag is not set, the cache is flushed.
4.

Read

The

read

operation

Counters

Subroutine

counters

subroutine

code

read

entered

counters.

when

This

the

queue

command

subroutine

performs

code

and

the

following:

Next,

Sets

the

Test

CLR.CNT

flag

LOCAL.COMMAND

bit

operation

the

3.
4.

Writes
Builds

a
a

5.
6.
7.

Repeats

the

flag

causes

CLR.CNT

four-word
CCW

steps

assertion

queue

and

the

flag

header

above

word

toc

host

the

memory

Am2901

times.

CLR.CNT

clears

the

local

locations containing net counters. The flag LOCAL.COMMAND
cleared. This subroutine saves the complete operation code
cache

and

tries

link

onto

the

set,

set

response

store

is then
word in

queue.

5.
Data Scan Receive Subroutine
The datagram receive subroutine is entered when the queue command
operation code is a datagram receive. This subroutine halts port
operations
at
1location
7750.
A
datagram
receive
1is,
as
its
designation
implies,
a
receive
function
and
not
a
transmit

function,
has

thereby

indicating

that

fatal

malfunction

the

system

occurred.

6.
Write Port Logic Interface (PLI) Subroutine
The write port
logic
interface
(PLI)
subroutine
1is entered when
the queue command operation code is a write port. This subroutine
performs the following:
l.

©Sets

Reads

the

flag

PLI

LOCAL.COMMAND

command

word

5-104

into

the

Am2901

With

Determines

Executes

the

PLI

function.

the

assertion

the

flag

written

the

PLI

host

PLI

command

word.

This

word

cache

and

the

flag

not

Read

The

read

PLI

operation
following:

code

Reads

3.
4.

Determines

the

read

command

the

complete

operation

the

response

queue.

onto

flushed.

entered
PLI.
This

when

the
queue
command
subroutine
performs
the

LOCAL.COMMAND

PLI

command

the

1is

read

PLI

word

function

function.

of the flag CC.BLDRSP causes a four-word queue
written
into
the
host
memory
-in
addition
to
PLI command word. This subroutine saves the complete

the

word

flag

cache

not

and

set,

tries

the

cache

the

code

read

link

Read Station Address Subroutine
station
address
subroutine
is

operation

performs

cache

saves

link

the
operation code

assertion

writing
queue.

flag

the

Executes

the

a four-word queue header
addition to the writing of a

Subroutine

Sets

header

subroutine

tries

subroutine

Next,

The

set,

CC.BLDRSP,

memory

code

function

station

onto

Writes

four-word

Writes

the

queue

response

entered

when

the

address.

This

subroutine

following:

the

flushed.

header

into

station

address

from

bits

version

number

host

queue

memory

1local

store

host

memory

Writes

mode

This subroutine saves
and tries to link onto
9.
The

Write
write

command

the

the
the

complete

operation
queue.

address
code

response

Station Address

station

operation

performs

and

write

entered

when

address.

The

retry

count

station

address,

mode

bits,

and

command

the

flag
is

cache

the

queue

subroutine

from

the

Writes the NIA physical address
Changes any required mode bits.

address

word

following:

Reads

2.
3.

code

memory.

Subroutine

subroutine
a

host

CC.BLDRSP

set,

four-word

host

memory.

written

into

the

complete

operation

code

word

response

queue.

the

flag

RAM

cache

not

set,

5-105

with

queue
This

and
the

new

header

address

and

subroutine

station

saves

the

onto

the

tries

link

cache

flushed.

APPENDIX

INSTALLATION

A.l

This

NIA20

KL10-D

OVERVIEW

appendix

describes
the
1installation
of
the
NIA20
network
interconnect adapter in a KL10-D system. Figures A-1 and A-2 show
the
NIA20
installed
in
a
KL10-D,
rear
and
front
views,
respectively.
Table
A-1
itemizes
the NIA20
parts
and
Table
A-2
lists the harness and cable connections used in the NIA20/KL10-D
installation.

The NIA20
installation uses assigned slots in RH20 logic assembly
positions
4
and
5,
with
RH20
positions
6
and
7
reserved
for
installation of a CI20 computer interconnect. A system containing

NIA20
is
1limited
to
installation of an NIA20,

used

a
maximum
of
four
RH20s.
In
a module blank assembly, Digital
prevent plugging any other module into

7019266-00,

position
4
Figure A-3).

(described

Section

A.4.3,

instruction

the
P.N.
RH20

see

NOTE

The

prior

or subsequent installation of a
computer
interconnect with an NIA20

CI20

requires
minor
deviations
from
the
following procedures, which are described
herein when applicable.

Installation

Backplane

NIA20

and

checkout

existing

procedures:
of

installation

requires

kit

wire adds

of
of

port modules
power supply

Installation

NIA

Installation

of
of

NIA

regulator

cage

Installation

vane

[]

current limiter
power harness

[]

card

Installation

PLI

Installation
Installation
Installation
assembly

of fan ac cable and power
of internal NIA cable
of
KL10
adapter
board

[]

system

checkout

Installation
Installation

Installation

[)

B WO

the

following

Preinstallation

15.
The

the

Unpacking

OO~
UTH WN -

implementing

switch

voltage

harness
monitor

harness

and

module

bus

cord
and

blank

module

Checkout.

following

performing

each

sections

these

provide

above

detailed

installation

instructions

procedures.

for

3622344-02

CABLE

i _Too0 P%SE%£

FAN AC

ao
N O

861 POWER
CONTROLLER—

- 0 Il

MODULE
UTILIZATION
E)ECAL

&
I/0 CABINET

REAR VIEW

0L
\

BNE3
EXTERNAL
CABLE

NIA20
CURRENT
LIMITER

’

NIA20

CARD CAGE

H—C120
CARD CAGE

;____
A |

| -DC VOLTAGE
MONITOR
BOARD

H— INTERNAL

CABLES

CABLE

E
A-6)
(SEE FIGUR
+—FAN AC
CABLE
T PLI BUS

T—NIA20 PORT
MODULES

—~MBUS
|

H7420

SUPPLIES

-;>Povven

b
CPU CABINET

BNE3

H4000

~jl~REAR DOOR
SWING-AWAY
FRAME

MR-13729

Figure A-1

NIA20 in KL10-D, Rear View

VANE

SWITCH~U
—5.2 H

QOO
[~(l5-]
S

—

)

KL10

aonon

000C

]

CPU CABINET

1/0 CABINET

FRONT VIEW

Figure

A-2

NIA20

KL10-D,

Front

View

Table A-1l

NIA20

in KL10-D,

Parts

List

Line

Part

Item

No.

Description

7019268-00

Card

cage

assy

IPA-20-L

7019268-01

Card

cage

assy

CI20

3
4
5
6

7428312-01
7430279-01
9007786-00
9006073-01

Bracket, interface
Bracket, support
Retainer, U-nut 10-32X
Screw, mach pan phil 10-

1
2
9
17

7
8

9107240-09
9105740-55

Wrap, cable, .250 OD vinyl wht
Wire (wrap) 30 AWG KYNAR UL1l4

A/R
A/R
5

Oty

1213716-00

Spacer,

7020539-06

Cable,

foam

11
12

7019274-06
7021197-01

Cable, fan ac
Harness, dc-5.2

13
14

7430277-01
7019893-3L

Cable

15
16

fan

polyu

1/2

1
dc+5

1
1

Support, bracket interface
assy Ethernet

1
1

BCO6R-08

BCO6R

7019266-00

Module

17
18

M3002-00
M3003-00

CI20
CI20

19
20
21

M3001-00
9007032-00
1213715-00

CI20 EBus interface, multiwire H
Tie, cable bundl. Dia 0-1-3/4"=101
Clip, flat cable w/adhesive bk

1
A/R
5

22
23
24
25
26
27
28
29

H7440-00

POAl H7440
NI20 (KL1l0 to NI adapter)
Blank module assy
Pwr cord, term 3-14 SJT 115
Pow cord extension 50 Hz
Washer, lock external steel
Washer, flat SST
Harness, dc voltage monitor

L0072-00
7014103-00
9107673-06
7011432-02
9007651-00
9006664-00
7021196-01

I/0

cable

blank

assy

microprocessor, mult1w1re HE
CBus/PLI interface, multiwire

switch

1
1

1
1
1
1
17
17
1

7021194-01

Harness,

vane

5414506-01

Voltage,

monitor

32
33

7019270-1J
3621499-01

Bus, cable, M assy
Label, DCV monitor CI20

1
1

35
36

3613272-00
9007031-00
9008264-00

Label, adh back, Mylar cap
Tie, cable bundl. Dia 0-3/4"=101
Mount, cable tie, adhesive back

1
36
A/R

37
38
39
40
41
42
43

3621498-01
5415695-01
9006022-01
9006633-00
7020488-00
3617674-00
3617674-01

Label, airflow CPU CI20
Current limiter
Screw, mach pan Phil 6Washer, lock internal steel
Cable, short switch vane
Label, serial/power W/0 UL + CSA
Label, serial/power W UL & CSA

1
1
4
4
1
1
1

44
45

3617880-09
3621501-02

Label,
Label,

1
1

board

class A subassembly
module location, NI20

1
1

Table

A-2

NIA20

KL10-D,

Harness

and

Cable

Connections

Parts

List

Harness

Terminals

Item

No.

Point

Connection

Remarks

NIA20

J1l

5
6

-—
-

H7440

CPU
CPU

#3
#3

BP
BP

GND
-5.2

See

Figure

Fan

Bracket

See

Note

See

Figure

A-1l1l

See

Note

-—

See

Note

NIA20

See

Note

See

Notes

NIA20

Mon.

Board

+5V Monitor

CI20

NIA20

CI20

Parts

Board

Figure

Switch

See

Note

Fan

Bracket

List

See

Vane

Fan

Jl1-5

Cable

J1l

A-5

and

Item

A-2

See

Note

See

Note

NOTES:

Items

not

needed

Item

Qty

Part

when

No.

kit

installed:

Description

9007786-00

Retainer,

9006073-01

Screw,

U-nut

9007651-00

Washer,

28
3
30

8
1
1

9006668-00
7428312-01
7019862-00

Washer, flat SST
Bracket, interface
Harness, vane switch

4
13

2
1

7430279-01
7430277-01

Bracket,
Support,

A/R

9107240-09

Wrap,

Mach

Pan

lock

10-32X
Phil

ext

support
bracket

cable,

Relocate cable from CI20 card cage
into NIA20 card cage J6 connector.

interface

.250

on parts
list Item 30
(harness,
vane
existing connector P4 (see Figure A-12).

10-

vinyl

switch)

wht

connects

connector

and

with

insert

Table A-2

Parts

NIA20

1list

Item

KL10-D,

used

Harness

when

and

CI20

together.

Cable

and

Connections

NIA20

are

(Cont)

installed

Connections

Parts

List
Item

From

No.

Unit

Location

Ref.

Desig.

Unit

Location

Ref.Desig.

Remarks

NIA20~-CB

C.Cage

Gnd

Fan

C.Cage

Item

861

25/26

Brk

Connect

any

outlet

1/2

C.Cage

Gnd

NI20

M3003

M3001
38

RH20

avail,
switched

Stripe

Cabrail

Hole

RH20

M3003

Down

DTE

P2
Up

M3002

B1lON1

RH20

B13Bl
cloL2

B19Bl

B13B2

B19B2

B13B2

B13Bl

C1l0K2

B13Ul

Cl0T2
C13B1

B1l9uUl

Cl3Bl

Cl9B1

C1l3N1

Cl2H2

C1l3N1

Clarl

cl4n2
Cl4F1
Al4J2

B13Ul

Cl9N1

Cl3B2

Al15R2
F15A1
Al5E1l

Cl4K?2

B14J1

Al1582

B15A1

C20H2

C20F1

A21R2

A20J2
c20pl
C20K2

~
-

B20J1

F21al
A21E1
A21D2
A2152

B21Al

Cl13B2

Cl4prl

cl19B2

Al15D2

Stripe

A.2

UNPACKING

Before
area.

all

unpacking
Check

boxes

customer

AND

any

CHECKOUT

equipment,

the

shipment

were

sent.

and

the

move

against

branch

all

the

any

boxes

field

are

service

boxes
are
sealed,
and
there
is no sign
as dents, holes, or damaged corners.
If

any

field

one

boxes

are

open

service

time,

damaged,

report

starting

This

completes

field

service

items

are

field

the

NIA20:

Wire

missing,

computer

sure

that

contact

Check

that

the
all

external

damage,

installation

the

customer.

marked

such

Open

the

FIRST"

"READ

boxes
and

branch

should

NEEDED

equipment

field
claim.

get

FOR

checkout

problems

phase.

service
For

the

branch

phase.

manager

any

may

missing

short-ship

INSTALLATION

required

for

Advise

this

during

items,

If
want

the

branch

request.

AND

CHECKOUT

installation

and

checkout

wrap tool, No. 30 AWG, Digital P.N. 29-18301
Wire unwrapping tool, No. 30 AWG, Digital P.N. 29-1351
3
Regular Phillips screwdriver

Tektronix
KLAD

475

digital

INSTALLATION

A.4.1

oscilloscope

performing

configured

the

system

its

operating

all

customer

media

corrupting

customer

data.

Mount
run

the KLAD pack,

the

"B"

string

bring
to

properly.

Power-down

Verify that
the
If
not,
replace

the

MHz)

installation,

of present system
installation.

Remove

(100

PROCEDURE

possibility

equivalent

voltmeter.

Preinstallation

Before

pack

Scope,

A.4

after

and

any

insurance

EQUIPMENT

the

manager

following

UL
WN

The

unpacking

manager

file

service

A.3

the

damaged,

box

the

slip. Check the contents of the box agains
t the
examine
each
item
for
damage.
Note missing
or
on the installation report or field servic
e report.

items

customer

the

into

list

manager.

document

inform

with

find the packing
packing
slip
and
damaged

and

boxes

packing

minimize

the

possibility

up the diagnostic monitor,

and

verify

that

the

system

working

system.

system has a M8532-YA board
installed.
the
currently
installed
M8532
with
a

RH20 positions 4 and 5 are used for the NIA20. If there
is an RH20 in position 4, remove it. If there is an RH20
in position 5, leave it temporarily installed and perform
diagnostic DFRHB to verify the reliability of the
backplane wiring. If there 1is no RH20 in position 5,
relocate a module from one of the other RH20 positions to
position

Power-up the system and run diagnostic DFRHB. This
verifies that the backplane wiring of RH20 position 5 is
functional. Power-down the system and reinstall the RH20
in

its original position.

Perform diagnostic DFRHB also in RH20 position 7 to
verify the reliability of existing backplane wiring in
RH20 positions 6 and 7, before implementing any NIA20
modifications.

8.
A.4.2

Power-down

the

system

original position.

and

reinstall

the

RH20

1its

Backplane Wire Adds

For the NIA20 installation, 24 new wires must be added to RH20
ane
backplane positions 4 and 5. An examination of the RH20 backplwire
the
of
on
must be performed to confirm the physical additi
wraps listed in Table A-3. The table contains a Check column for
the wire installer to record installation progress.

tion
To prepare the wire adds, strip approximately 1 inch ofoninsula
wire
the
made
be
to
from the wire to allow sufficient turns
blank
the
in
check
a
enter
wrap post. After each wire 1is added,
space adjacent to the wire listing in Table A-3.

To assure the reliability of the new wiring, an ohmmeter check of
each new wire add should be performed by a person other than the

wire

installer.

Table A-3

NIA20 in KL10-D Wire Adds

Signal Name

From

To/From

EBUS D11 L
EBUS D12 L
EBUS D13 L

B1ON1
Cl0L2
Cl0K2

B13Bl1
B13B2
B13Ul

B19Bl1
B19B2
B19Ul

EBUS PI0O0 L
EBUS PARITY ACTIVE L

Cl2H2
Cl2L1

C1l3N1
Cl3B2

Cl9nl
Cl9B2

EBUS PARITY L
MPR7
MPR7
MPR7
CBI1l

MWBUSCTLFLDOl1l H
MWMGCFLDO08 H
MWTIMEFLD H
CLK2 L

Cl0T2

Cl4H2
Cl4rl
Al14J2
Cl4prl

Cl3Bl

Al15R2
F15A1
Al5E1
Al15D2

Cl9Bl1

Check

Table

Signal

A-3

NIA20

Name

CBI2

CLK4

CBl2

CCCHANERR

MPR7

MWBUSCTLFLDOl

MPR7

MWMGCFLDO0O8

MPR7

MWTIMEFLD

L
L

KL10-D Wire

From

To/From

Cl4K2

A15S52

"B14J1

B15A1l

C20H2

A21R2

H
H

C20F1

F21A1

A20J2

A21E1l

CBIl

CLK2

Cc20pPl

CBI2

CLK4

A21D2

C20K2

CBI2

CCCHANERR

A21S2

B20J1

B21Al

A.4.3

Installation

Protective

backing

Port

placed

Adds

(Cont)

Check

Modules
on

the lower third noncomponent side
the upper third of the noncomponent side
of
the
M3002.
As
the modules
are
inserted
and/or
removed,
the
protective
backing
protects
the
MBus
and
PLI
bus
cables.
The
protective
backing
should
not
interfere
with
the
card
guide
or

each

cover

port

the

modules

module

gold

and

finger

Connect

MBus

orient

the

cable

header

Insert

the

cable

cable,

cable

rightmost
looking at
on

contacts

follows:

the

Digital

away

that

from

P.N.

the

module.

7019270-1J.

flat

board,

Insert

wire
as

comes

shown

Connect
module

should

Insert

Connect

MBus

shown

aligned

cable

the

with

the

sure

out

the

Figure

arrow

the

M3002'port

A-3.

M3002
in slot
20
to
shown in Figure A-3.
cable

the

A-3,

M3003

located

CBus/PLI
the

left

board

microprocessor

the

left

the

M3003

module

shown

interface

module

slot

21,

A-3.

Install
which

MBus

Figure

the module
installed M3001 as

Figure

the
as

port

M3001
EBus
interface/port ALU module
in
the
slot
of
RH20
position
number
5
(slot
19,
the backplane from the module side). The arrow

connector.

the

installed

M3002.

Install
the
module
blank
assembly,
Digital
P.N.
7019266-00,
in
RH20
position
4,
slot
22.
This assembly
blocks
slots
22,
23,
and
24.
It
prevents
modules
from
being inserted into RH20 position 4 and provid
es a baffle
for system cabinet airflow.

Perform
an
verify that

ohmmeter
check
between
PT17U
there are no shorts to ground.

and

ground

MODULE
BLANK

M3003

ASSEMBLY
SLOT 22

[

SLOT 21

M3002

SLOT 20

)
. 4

SN W\

M3001

SLOT 19

. |

L]
MR-1373%

Figure A-3
9.

Fold

the

MBus Cable Interboard Connection,

Top View

blank

assembly

MBus

cable

10.

the module door.

11.

the
Attach
Digital P.N.

12.

Power—-up

13.

into

the

module

Figure A-3.

shown

the

decal,
utilization
module
self-sticking
panel.
3622344-02, on the upper rear baffle
KL10.

Readjust the existing +5 V power supply to 5.0 +/- 0.25
V. This adjustment is located on H7420 number 1 in H744
number 4.

from

+5F,

the

The location of this regulator

circuit

between

PT17U

breaker.
and

The

ground.

voltage

is farthest away

monitored

14.

Type

(CR)

response

FX1

with

KLDCP

loaded

the

and

command

running;

prompt,

then

shown

type

FX1

below:

(CR)
(CR)

15.

De-skew

16.

Connect

channel

4D33P1,

the
port
modules
using
a
Tektronix
475
or
equivalent
100 MHz minimum oscilloscope and perform the
following steps. Figures A-4 and A-5 shows the acceptable
waveform pattern displays of the NIA20 de-skew timing.

the

of the oscilloscope to MTR MBOX
backplane. Use a ground clip.

CPU

%
L4d ittt
A

RN
A

1411 IIIIT:

EXTERNAL SYNC

(BN

(CHTOH'4BOQK1)

SOEnV

CLK

E ZQnS

EXTERNAL SYNC (CHTO H)

Figure

A-4

17.

Set

the

18.

Set

channel

ground

NIA

time

Set

the

20.

Connect

the

channel

backplane.
V/division.

sync

gain

above

the

(MTR

MBOX

1.3

©Set
Use

sync

input

ground

External

Sync

(CHTO

ns.

oscilloscope

external
Use

vertical

oscilloscope

backplane.
21.

base

reference

level
of
signal).
19.

De-skew Timing.

0.5

V/division.

positive
to

horizontal
CLK

Set the
center

ECL

external.

CHTO

4B09Kl

the

CPU

CLK

2A21Fl1

the

1/0

clip.

CDS1l,

EBUS

the
<channel
2
vertical
a ground clip. To measure

gain
to
0.5
TTL voltages,

TTr 1 IpriT

2
CHANNEL

(EBUS CLK L, 2A21F1)

—

TTV[IT1

P11l

LB
LIRS

-t

MTR MBOX CLK,

(4D33P1)

(et

RAR

CHANNEL 1

A HX.

prbty e

[VVVM

50mvV

20nS

EBUS CKL L AND MTR MBOX CLK
MR-13732

Figure A-5

NIA20 De-skew Timing. EBus CLK L and MTR MBOX CLK

set the ground reference to 1.5 V below the horizontal
center

22,

line of the oscilloscope.

Press the trigger view switch of the oscilloscope and
display the external sync. Adjust the display, so that
the rising edge of the external sync aligns with the
vertical center line of the oscilloscope.

23.

Display MBOX CLK H, channel 1. Identify the rising edge
of MBOX CLK H that occurs prior to the vertical center
line of the oscilloscope. Display channel 1 and channel
2.

24,

25.

Put the KL10-D

the override

fault

state.

I1/0 rear door to access the I/0 backplane.

Remove

the

Locate the bottom potentiometer on the clock module
(M8559) in slot 12 of the I/0 backplane. Using this
potentiometer, adjust the falling edge of channel 2, EBUS
CLK L so that it crosses the rising edge of MBOX CLK H.
This crossing occurs on the horizontal center line of the
oscilloscope.

probes.

26.

Disconnect all

27.

Mount the KLAD pack on the front end RP06.

28.

Load

and

run

diagnostic

DFPTA

verify

©proper

functioning of the port modules. If the modules fail,
If the
troubleshoot as directed by the diagnostic.
the
with
continue
modules are functioning properly,
installation.

A.4.4

Power

Three

H7420

Supply

power

Regulator

supplies

Installation

are

location.

This

the

additional

card

cage

NIA20

and

Remove

the

H7420

number

Take

the

H7440

new

and

one

use

H744

slot

power

H7440

slot

top

spare
1

located

on
the
rear
swing-away
shown
in Figure A-1.
The H7440
in the upper H7420 power supply
+5 V regulator
is
required
to support
installed as follows (see Figure A-6):

frame door of the I/O cabinet as
regulator to be added is installed

filler

Save

regulator

from

H7420

number

thumbscrew
at

H7440

panel

supply.

the

from

all

slot

existing

the

kit

using

bottom.

and

Some

PT8

15 PIN CONNECTOR

/7 1P

—

\‘\iu_

H744 | H744 | H744 | H744

|H7440

+5K | 5J

+5H

| —6F

MR-13892

Figure

A-6

H7420

A-13

Power

Supply

screws

systems

install

two

regqulators.

PT7

the

hardware.
the

on
may

Installation of NIA20 Card Cage/Cable

A.4.5

To install the NIA20 card cage and the internal NIA20 cable,
perform the following operations (see Figures A-7 and A-8):
l.

Install

the

7430278-01,

two
as

mounting

NIA20

Wwhen

P.N,

Digital

follows:
NOTE

CI20

brackets,

mounted as shown

installed,

the

NIA20

in Figure A-l.

Remove and reposition any tie-wrapped cables from the
right frame member of the CPU cabinet (viewed from the
rear) to accommodate the NIA20 mounting brackets and card
cage.

Install a total of 8 U-nuts (Tinnerman nuts), Digital
the CPU
frame of
swing—away
in the
9007786-00,
P.N.
cabinet

(viewed

from

the

rear).

Insert Tinnerman nuts into frame holes 3, 4, 41, and 42
counting down from the top of the swing-away frame (see
Figure A-7). Four Tinnerman nuts are inserted into each
side

the

frame.

Check that the 1lip of each support bracket 1is at the
Use four 10/32 one-half inch Phillips panhead
bottom.
machine screws, Digital P.N. 9006073-01 and four No. 10
starlock washers, Digital P.N. 9007651-00 on each side of
the

swing—-away

frame.

Locate the NIA20 internal cable strain relief (white) on
(see Figure A-8).
1left side of NIA20 card cage
the
strain
this
1location of
inaccessible
the
of
Because
relief once the card cage 1is 1installed, the internal
cable is routed through it and connected to the rear J4
connector on the card cage prior to installing the card
cage.

Locate

the

three-foot

internal NIA20

cable,

Digital

P.N.

7019893-3L.

1installation by
Prepare the internal NIA20 cable for
positioning a stick mount on the right-side wvertical
frame member of the CPU cabinet (viewed from
above the bracket interface (see Figure A-9).

the

rear),

Route the three-foot internal NIA20 cable through
white plastic strain relief on the NIA20 card cage.

the

—

/7— \

CAGE

HoLes [o

)

—-

FRAM(E AWAY

\\ 4

NIA20

-8-—’—- 3

CARD

SWING-

REAR

le¢———— CPU CABINET

SUPPORT

DOOR

> NIA20 CARD CAGE

BRACKET

MOUNTING

7430279-01

BRACKETS

11
41

\\\\~,;iij///—\‘
Figure

Connect

Figure

the

A-8)

A-7

internal

the

NIA20

Card

NIA20

cable

NIA20

card

shown in Figure A-1. The
when properly seated.
7.

Mount

the

brackets

NIA20

that

7430279-01
external
card

(see

cage

Figure

four

Install

the

top

cage

cable

the

lockwashers,

cage

bottom

card

overlay

Cage

KL10-D

the

and

the

connector

route

connector

support

A-7),

engages

two

NIA20

brackets,

using

the

eight

card

detent

mounting

Digital

10/32

P.N.
screws,

and

flat

four

screws,

and

then

install

the

cage

ground

cable

(see

Figure

A-8)

right

side

frame

washers.

Hang

screws.
NIA20

(see

cable

the

NIA20

follows:

Install

member

Tinnerman

the

CPU

nut

cabinet

hole

(viewed

the

from

the

rear).

]

TOP

o =]

-6
FRONT

REAR

:‘_,,..——-J4

L,u

H;r

CABLE

2«

RELIEF—»

STRAIN

O
o

GND —_]|

\.’Q

@
|S

REAR VIEW

uN uN

SIDE VIEW

FRONT VIEW
MR-13735

Figure

A-8

NIA20

Card

Cage

Views

INTERNAL

CABLE

7019893
TO J1 CONNECTOR
J1 CONNECTOR

INTERFACE

[~ ~

SUPPORT

BNE3

BRACKET

CONNECTOR

2430277-01

STICK
MOUNT

LOCATION

r
T

NIA20

INSTALL

FROM FRONT , ®

CPU CABINET

CURRENT

LIMITER
5415695-01

BRACKET

INTERFACE

C120

CONNECTORS

7428312-01
MR-13736

Figure A-9

NIA20 Current

Limiter

Connect

the

cable.

ground

Attach

hole

Run

the

A.4.5.1

screw

Digital

internal

NIA20

cable
to

mount

and

insert

the

NIA20

Installation
limiter,

bracket

interface,

Digital

1its

NIA20

1Install

Connect

AU
W N

previously
end

into

side

closest

positioned

the

rear

Limiter
is

The

NIA20

preinstalled

Figure

shown

the

support
1in
the

holes

support

internal

current
BNE3

bracket,

located

Digital

the

view)
using four
flat washers,.

cable

the

limiter

(see

external

cable

rear

Figure

right

10-32

side

screws,

connector

A-9).

the

NIA20

current

limiter.

cable

connects

the

Ethernet

transceiver,

The

following

harnesses

Installation

P.N.

the

limiter.

Connect

the
The

front

other

end

connector
of

the

are

DC power harness
Vane switch cable
DC voltage monitor cable
Fan ac cable and power cord
PLI

bus

BNE3

external

A-10

shows

interconnections.

member

each

3613272-00,

7428312-01,

interface

the

NIA20

A.4.5.2
Harness
be installed:

frame

follows:
the

external

Figure

the

Current

of the CPU cabinet
(rear
external lockwashers, and

P.N.

5415695-01

P.N.

side

starwasher

the
bracket
interface
on
the
interface
connect
the
internal
and
external
cables

limiter

the

right

other

current

P.N.

Digital

7430277-01,

the

using

label,

current

A-9.
1Install
bracket
and

and

ground

connector

cable

inserting

stick

current

ground

1Install

cable.

The

diagram

harnesses

tie-wraps

harnesses.

When

assemblies,

use

Locate

the

are

the

approximately
routing

spiral

power

harness

installed

harness,

eight

cables

wire-wrap

Digital

and

cable

follows:

inches

apart

<close

protect

the

P.N.

all

internal

cables.

7021197-01

(see

Figure A-11),
and
the black and blue wires
labeled PT5
and PT6.
Connect the black wire to -5.2 ground and the
blue wire to -5.2F in the I/0 cabinet (see Figure A-2).

61 0z

HIMOd [TT 1q

A-18

Locate

and

connector

connect

the

new

the

power

existing

harness

cage

power

card

A-8).
Next,
connect
the NIA20 card cage.

Tie-wrap

NIA20

cable

backplane

into

(see

Figure

cable

into

KL10-D

I/O

power

harnesses and route this cable through the cabinet floor
as shown in Figure A-1l. Use spiral wrap along the harness
where
it
contacts
the
side
of
the
CPU
frame
member
nearest
Locate

other

the
the

end

H7420
red

power

and

supplies

white

power

wires

cable

(see

Figure

labeled

PT7

(see

Figure

P3 from power supply H7420 number 1.
PT8
to pins
3 and 4,
respectively,

Then

reconnect

Connect

P2
of
regulator (see

the

A-1l).

and

A-1l).

PT8

the

Disconnect

Then connect PT7 and
on P3 of the H7420.

H7420.

the

harness
Figure A-6).

connector

the

H7440

/0 CABINET

PT5 <§,/)"

//)"

BLAC @//-, "
7

BLUE

i
RED WIRE
3

21P3ON H7430

(WIRE SIDE)

v
WHITE WIRE

H7440

POWER“®

REGULATOR

7021197-01
MR.13738

Figure

Locate

(see

the

vane

Figure

connector

A-11

A-12).

switch

cable,

Connect
the

Power

NIA20

A-19

card

Cable

Digital

P.N.

the

switch

vane

cage

(see

7021194-01

cable

Figure

A-8).

I/0

7021194-01

BACKPLANE

SWITCH

CABLE

MR-13739

Figure

Also,

A-12

connect

NIA20

card

the

wrap
as
cable.

Vane

needed

Switch

Cable

the

vane

switch

cage.

Use

stick

route

and

cable

mounts

protect

connector

and

spiral

the

vane

wire

switch

NOTE

When

CI20

switch

1is

vane

1installed,
the
cable,
Digital

short

P.N,

7020488-00,
is
used
in
a
combined
CI20/NIA20 installation. Consult the CI20
reference
manual
(Digital
order
number
EK-CI20-RM-001)
for other
installation procedures.

applicable

CI20

Remove the original KL10-D CPU vane switch cable
connect
this
to
the
NIA20
vane
switch
cable
Figure

A-13).

Connect

KL10-D
10.

11,

CPU

vane

switch

other

end

Insert

the

Figure

A-2.

Apply

the

existing
switch.
12,

13,

the

vane

CPU/NIA20

CPU

air

switch

assembly

the

air

fault

cable

the

switch

flow

fault

message

decal

Connect
on

the

connect

the

NIA20

the

card

end

voltage

monitor

backplane

the

cable

A-20

the

cable

decal

the

cable

(see

the

original

cabinet.

cable,

cage

I/0

vane

Locate
the
dc
voltage
monitor
7021196-01
(see Figure A-14).

(P4) and
J1
(see

shown

over

the

863

fault

Digital

P.N.

connector

Figure

voltage

A-8)

and

monitor

board,

Digital
the swing-away
Figure aA-1).
14.

Locate

the

P.N.

5414506-01,

frame

located

mounted on the front of
inside the CPU cabinet (see

switches

Only switch S1 should
monitor board switches

the

be on,
should

voltage

while all
be off.

monitor

other

board.

voltage

VANE
SWITCH

CONNECTOR

——————

P—————

BEFORE

VANE SWITCH CABLE

VANE

SWITCH

CONNECTOR

AFTER
MR-13740

Figure

15,

16.

Vane

Insert

the

voltage

Attach
to

17.

A-13

the

voltage

monitor

board.

Connect

the

Harness

monitor

board

monitor

indicate

Switch

the

remaining

voltage
monitor
cable
existing orange wire on

into

the

Digital

P.N.

slot

panel.

panel
slot

Installation

decal,
used

for

single

to
the

3621501-02,

the

NIA20

voltage

orange

wire

the

a
1location
adjacent
to
dc voltage monitor board

the
zone

18.

Tie-wrap

the

voltage

the

power

cable.

mounts

support

the

cable

ties

and

wrap

wire

monitor
Use

and

vane

switcht¥harnesses

adhesive-backed

harness

along

the

square

baffle

cabinet

cable

door

and

frame.

7021196-01

ORANGE

ADJACENT TO

ZONE +5L

\ DC VOLTAGE
MONITOR

BOARD
MR-13741

Figure
19.

Locate

the

Hz)

Digital
(240

A-14
fan

Voltage

cable,

7020539-06

P.N.

Vac

connector

Digital

(240

Vvac

9107673-06
Hz),

(see

Monitor

(120

connector

P.N.

7019274-06

Hz),

and

the

Hz)

Vac

Figure
J2

Cable

A-15).

Connect

NIA20

the

(120

power

Vac

cord,

7011432-02

fan
card

cable

cage

and

then join the fan ac cable and the power cord together.
Insert
the
end
of
the
power
cord
into
any
available
switched outlet on the 861 power controller. Connect the
ground
wire
to
the
adjacent ground
screw on
the NIA20
card cage.
Use
connection.,
20.

Install

attach

the

Locate

A-1

the

for

two

starwashers

PLI

cable,

—cable

connection).
by a
M3003

starwasher

Tinnerman
nut
in
ground cable
from

frame.
Use
connection.
21.

Connect

one

red
line imprinted
and
route
through

and

end

ensure

P.N.

good

electrical

good

BCO6R-08

and
the

electrical

(see

Figure

A-10

for

<cable

the

cable

(identified

on top of
the cable

NIA20

hole
13
on
the
frame
the NIA20 card cage to

Digital

route

ensure

PLI

the cable)
to
strain
relief

module
on
the

card
<cage.
The
other
end
of
the
PLI
cable
(identified
by
a
red
line
imprinted
on
bottom
of
the
cable) to connector J3 on the NIA20 card cage (see Figure
A-8).
To
secure
the
PLI
cable,
install
adhesive
foam,
Digital
P.N.
1213716-00,
within
each
of
the
four
flat

A-22

cable
card

clamps.
cage,

and

Install
three

one cable clamp on the side of the
across
top
rear of RH20
card cage

door.
22,

23.

Reinstall

the

CPU

baffle

panel.

Locate

and

connect

the

NIA20

current

route

down

along

CPU

the

BNE3

side

external

cable

into

connector

limiter

(see
Figure
A-9)
and out the bottom of

frame

and
the

cabinet.
CONNECT

FAN AC CABLE

7019274-086 (60 Hz)

GROUND
WIRE

7020539-06 (50 Hz)

POWER CORD

9107673-06 (60 Hz)
7011432-02 (50 Hz)

861

POWER

SWITCHED

CONTROLLER

—

OUTLET

‘ 1

Figure
A.4.6
The

KL10

module
NIA20

Fan

Installation of KL10
Assembly
to NI adapter board,

assembly,
card

A-15

cage

The

Digital

opening

Cable

Adapter

and

Board

Power
and

Cord

Blank

Module

Digital P.N. L0072-00, and the blank
P.N.
7014103-00,
are
installed
in
the

follows:

KL10

assembly

to
are

its

adapter

installed

front

Install
the KL10
right-hand slot.
Install

the

adjacent

slot

blank

board
into

hinged

end

adapter

module

the

left.

and

the

panel

the

NIA20

blank
card

module
cage

(L0072-00)

the

(7014103-00)

the

door.

board

assembly

Checkout

A.4.7

The physical part of the installation is complete at this point.
All that remains is to verify that the system runs properly in the
new configuration. Perform the following steps to verify the
installation.

Verify that the KL10-D is no longer in the override fault
state.

Power—up the KL10-D.

Readjust the 5 V power

supply to

5.0 +/- 0.25 V.

This

is located on power supply H7420 number 1,
5 (see Figure A-6). This regulator is located

adjustment
H7440 slot

nearest the H7420 power supply breaker. The voltage is
monitored at the black and red wires on connector Jl of
(see Figure A-8).

the NIA20 card cage

Load and run diagnostic DFPTA for at least five passes in

executive

mode.

Load and run diagnostic DFNIA for at least five passes in

Enable

Run diagnostics UETP NIA20 test in user mode for at least

executive mode.

four

system.

the operating

hours.

Disable

the

Remove

all

customer's

operating

field
system

10. Transfer/signoff
representative.

system.

service
and

store

system

packs
in

and

secure

tapes

from

the

area.

customer's

authorized

APPENDIX

INSTALLATION

NIA20

KL10-R

B.1l
OVERVIEW
This
appendix
describes
the
installation
of
the
NIA20
network
interconnect adapter in a KL10-R system. Figures B-1 and B-2 show
the
NIA20
installed
1in
a
KL10-R,
rear
and
front
views,
respectively.
Table
B-1
itemizes
the NIA20
parts
and Table B-2
lists the harness and cable connections used in the NIA20/KL10-R
installation.
‘
The

NIA20

installation

positions
4
installation

uses

assigned

and
5,
with
RH20
of a CI20 computer

slots

RH20

logic

assembly

positions
6
and
7
reserved
for
interconnect. A system containing

an
NIA20
is
1limited
to
a
maximum
of
four
RH20s.
1In
installation of an NIA20,
a module blank assembly,
Digital
7019206-00,
is
used
to
prevent
inserting
any other module
RH20 position
Figure A-3).

(described

Section

A.4.3,

instruction

the
P.N.
into
see

NOTE

The

CI20

prior

subsequent

computer

installation

interconnect

with

NIA20

requires
minor
deviations
from
the
following procedures, which are described
herein when applicable.
Installation

wire

existing

installation

of
of

port modules
power supply

Installation

NIA

Installation
Installation

of
of

NIA current limiter
dc power harness

vane

Installation

PLI

Installation
Installation
Installation
assembly

of fan ac cable and power
of internal NIA cable
of
KL10
adapter
board

kit

regulator

Installation

[]

requires

cage

[]

card

Installation

[]

system

adds

Installation
Installation

Backplane

15,

The

of
the
NIA20
in
an
the following procedures:

Unpacking and checkout of
Preinstallation checkout

S WO

CoOJOUTdxWN
-

implementing

switch

voltage

harness
monitor

harness

and

module

bus
cord
and

blank

module

Checkout.

following

performing

each

sections
of

these

provide
installation

B-1

detailed

instructions

procedures.

for

7019266-00

PLI CABLE
ROUTING
\\

7019862 VANE
SWITCH CABLE
\\
FOR MOUNTING
BRACKET WHEN
INSTALLING
BOTH C! AND NIA

{

)

-9 H7420 POWER SUPPLY

NIA20 CARD CAGE

P\2J1

|—
\

J [\

NIA20 PORT MODULES

~M3001 = SLOT 19

L\ M3002 = SLOT 20
M3003 = SLOT 21

-t
.

DC VOLTAGE
MONITOR BOARD

4 7020352 DC VOLTAGE

CABLE HARNESS
TROUGH —

|}~ MBUS CABLE ASSEMBLY

—,

P11

KL10 ADAPTER BOARD
7014103-00 BLANK
MODULE ASSEMBLY"

L - RH20 LOGIC ASSEMBLY
(POSITONS 4 AND 5 }

r v /
)

C120 CARD CAGE
(WHEN INSTALLED)

BLANK
ASSEMBLY

USE HOLES 18 AND 49

MODULE

BCO6R-8

{

i===

P17

I/0 CABINET

MONITOR CABLE

it 7019274 OR 7020539
{ )RlAN
hppa el AC VAN HARNESS TO 861
plegelopuguiy
oy Syl oyl
S

REAR VIEW

CONNECT

|0 14000

CPU CABINET

POWER CONTROLLER
Ni1A20 CURRENT LIMITER
C120 BULKHEAD PLATE
7019893 INTERNAL CABLE

“BNE3 EXTERNAL CABLE

MR-13743

BRACKET DETAIL

Figure

B-1

NIA20 in KL10-R, Rear View

CPU #3

H7420

—52H

||
—

H
,/
\?F

POWER

SUPPLIES
i
000

[

Ay'l

8
|
Hfl

—~DC POWER CABLE
CONNECTIONS

| | —C120 CARD CAGE

J.E 3

|1 —NIA20 CARD CAGE

7 iy
T

J1 POSITION 5

UL LT ©

DC VOLTAGE MONITOR BOARD

UL
BCO6R-8 PLI CABLE

I/0 CABINET

CPU CABINET
FRONT VIEW

BRACKET DETAIL
MR-13744

Figure

B-2

NIA20

KL10-R,

Front

View

Table B-1

NIA20 in KL10-R, Parts List

Line Item

Part No.

Description

Qty

1
2

7019268-00
7019268-01

Card Cage Assy IPA-20-L
Card Cage Assy CIZ20

1
1

—

-—

—

9105740-55

Wire

9007786-00
9006073-01
9107240-09

5
6
7
8

1213716-00
7020539-06
7019274-06
7019273-00
7019272-00
7019893-7L
BCO6R-08
7019266-00
M3002-00

9
10
11
12
13
14
15
16
17

M3003-00

9
Retainer, U-nut 10-32X
17
Screw, mach pan Phil 10Wrap, cable, .250 OD vinyl wht A/R
UuLl4

(wrap)
(12

30 AWG KYNAR

ft)A/R

Spacer, foam Polyu 1/2
Cable, fan ac
Cable, fan ac:
Harness DC-5.2 sect N1-2 dc+5
Harness DC-5.2 sect N1l-1 dc+5
Cable assy, Ethernet
BCO6R I/0 cable
Model blank assy
CI20 microprocessor, multiwire HE

5
1
1
1
1
1
1
1
1

multiwire

CI20 CBus/PLI interface,

CI20 EBus interface, multiwire H
Tie, cable bundl. Dia 0-1-3/4"=

19
20

M3001-00
9007032-00

21
22
23
24
25
26
27
28
29
30
31
32
33
34

1213715-00
H7440-00
L0072
7014103-00
9107673-06
7011432-02
9007651-00
9006668-00
7020352-00
7019862-00
5414506-01
7019270-1J
3621499-01
3613272-00

Clip, flat cable w/adhesive Dbk
POA1l H7440
NI20 (KL10 to NI adapter)
Blank module assy
Pwr Cord, term 3-14 SJT 115
Pow cord extension 50 Hz
Washer, lock externhal steel
Washer, flat SST
Harness, dc voltage monitor
Harness, vane switch
Voltage, monitor board
Bus, cable, M assy
Label, DCV monitor CIZ20
Label, adhesive back, Mylar cap

3621498-01
5415695-01

Label, airflow, CPU CI20
Current limiter

35
36

37
38

‘
'

9007031-00
9008264-00

101

A/R

Tie, cable bundl. Dia 0-3/4"=101
Mount, cable tie, adhesive back

39
40
41
42

9006022-01
9006633-00
7020488-00
7430278-01

Screw, mach pan phil 6Washer, lock internal steel
Cable, short switch vane
Bracket, mounting

3617674-00

Label, serial/power w/o UL + CSA

43
44

9006659-00
7021448-5C

Washer, flat S/PAS
Cable dc voltage monitor Sect.l

1
5
1
1
1
1
1
17
17
1
1
1
1
1
1
36

A/R
1
1

4
4
1
1

2
1
1

Table

Line

Item

Part

B-1

NIA20

No.

KL10-R,

Parts

(Cont)

Description

Qty

3617674-01
3617880-09

Label,

serial/power

Label,

class

3621501-02

Label,

module

Table B-2

List

w/UL &
subassembly

location,

CSA

1
1

NI20

NIA20 in KL10-R, Harness and Cable Connections
Harness

Connections

Parts

List
Item

Harness

No.

Point

Connection

NIA20

Terminals

Connection

CPU

Sect

N-2

Remarks

GND

-5.2

Parts

H7440

See

Figure

B-10

See

Figure

B-10

Fan

Brkt

See

Figure

NIA20

Jl
B-10

+5V

CI20

Mon

See

Note

See

Note

See

Notes

and

See

Notes

and

List

J1l-5

See

Figure

cable
Switch

vane

See

Note

NIA20

C120

Mon

kit

fan

brkt

Note

See

Note

See

Figure
List

NOTES
:

Items

not

needed

when

Item

Qty

Part

6
6

9007786-00
9006073-01

No.

installed:

Description
Retainer,
Screw,

B-5

U-nut
pan

mach

phil

Items

10-

B-2

See

Parts

B-5

Figure

item

See

Parts

list

B-13
Item

NIA20

B-2

=~ Oy
O

Table

27
28

in KL10-R,

9007651-00
9006668-00
7019862-00

parts

list

connector

Relocate

cable

into NIA20
Parts

lock

external

flat

SST

Harness,

cage

Item

vane

(Cont)

steel

switch

(harness,

(see

from CI20

card

list

Washer,
Washer,

Item

existing

Harness and Cable Connections

vane

switch)

connects with

Figure B-12).

card

cage

at J6

connector

and

insert

connector.

used

when

CI20

and

NIA20

are

installed

together.

Cable Connections
Parts

List

Item
No.

From
Unit

Location Ref. Desig.

Unit

‘
To
Location Ref.Desig. Remarks

Cd.Cage

Gnd

25 or

Gnd

NIA20~-CB

26
Fan

25
26

Cd.Cage

Item

861

Brkt

Connect

any
available
switched
outlet

1/2

Cd.Cage

Gnd

C120

stripe

Cabrail

Hole

RH20

M3003 J2

DTE

down

M3002

M3003

M3001

Bl N1
B13Bl

RH20

Bl3Bl
B19B1

B19B2

B1l9Ul

Ccl9Bl

Cc1l0L2

Cl0K2

Ccl0T2

B13B2

B13Ul

cl3Bl

Cl2H2
C13N1
Ccl2L1

RH20

B13F2

B13Ul

C13B1

C13N1
Cl9N1
Cl3F2

Cl3B2

Cl9B2

Cl4H2

Al15R2

stripe

Table B-2

NIA20

in KL10-R,

Cd.Cage

and Cable Connections

Cl4F1l

F15A1

Al432

Al5E1

Ccl4prl
Cl4K2

Al5D2
Al1552

B14J1
C20H2

B15A1
A21R2

C20F1

A21lEl

F21A1

c20p1
C20K2
B20J1

A21D2
A21S2
B2]1Al

Gnd

J1l

A20J2

Harness

(Cont)

NIA20-CA

26
Fan

B.2

Brkt

UNPACKING

Before

unpacking

AND

any

CHECKOUT

equipment,

move

all

boxes

into

area. Check the shipment against the packing list to
all
boxes
were
sent.
If
any
boxes
are
missing,
customer
and
the
branch
field
service
manager.
boxes are sealed, and there 1is no sign of external
dents, holes, or damaged corners.

the

computer

be sure that
contact
the

Check
that
all
damage, such as

If any boxes are open or damaged, document it on the installation
or field service report and inform the customer. Open the boxes
one at a time, starting with the box marked "READ ME FIRST" and
find the packing slip. Check the contents of the box against the
packing slip and examine each item for damage. Note missing or
damaged items on the installation report or field service report.
This
completes
the
unpacking
and
checkout
phase.
Advise
the
branch field service manager of any problems during this phase., If
any items are damaged, the branch field service manager may want
the customer to file an insurance claim. For missing items, the
branch field service manager should get a short-ship request.

equipment

required

for

installation and checkout

NIA20:

the

EQUIPMENT NEEDED FOR INSTALLATION AND CHECKOUT

following

The

YU
W N

B.3

Wire wrap tool No. 30 AWG, Digital P.N. 29-18301
Wire unwrapping tool, No. 30 AWG, Digital P.N. 29-13513
Regular Phillips screwdriver
Tektronix 475 oscilloscope or equivalent (100 MHz)
KLAD

pack

Scope,

digital

voltmeter.

PROCEDURE

B.4

INSTALLATION

B.4.1

Preinstallation Checkout

Before performing the installation, verify
properly
operating
is
system
configured

the currently
the
preclude

that
to

possibility of present system problems being ascribed to the NIA20
installation.

its

after

Remove all customer media,

corrupting

customer

data.

the

supplied

KLAD

Mount

monitor,
is

and

the

run

of
to minimize the possibility

pack,

string

bring

verify

diagnostic

the

that

system

properly.

working

the

system.

Power-down

4.,

Verify that the system has a M8532-YA board installed.
replace the currently installed M8532 with a
If not,
M8532-YA.

RH20 positions 4 and 5 are used for the NIA20. If there
is an RH20 in position 4, remove it, If there 1is an RH20
in position 5, leave it temporarily installed and perform
the
of
reliability
the
verify
to
DFRHB
diagnostic
backplane wiring.
If there is no RH20 in position 5,
relocate a module from one of the other RH20 positions to

position

This
DFRHB.
diagnostic
run
and
system
the
Power-up
5 is
position
RH20
of
wiring
backplane
verifies that the
functional. Power—-down the system and reinstall the RH20

its

original

position,

to
position 7
in RH20
Perform diagnostic DFRHB also
verify the reliability of existing backplane wiring in
before
installation,
and 7 for CI20
RH20 positions 6

backplane

wiring

modifications

for

the

NIA20

are

implemented.

original

B.4.2

For

the

Power-down

system

and

reinstall

the

RH20

its

added

RH20

position.

Backplane Wire Adds

NIA20

backplane

installation,

positions

4 and

new

wires

must

An examination of

the RH20

backplane

must be performed to confirm the physical addition of the wire
wraps listed in Table B-3. The table contains a Check column for
the wire

#ffi

(.,

installer

record

installation progress.

B-8

prepare

the

wire

adds,

insulation

strip

approximately

inch

from the wire to allow sufficient turns to be made
on
the wire wrap post. After each wire is added, enter
a check in the
~blank adjacent to the wire listing in Table B-3.
To

assure

the

reliability

the

add

performed

each

new

wire

installer.

wire

should

Table B-3
Signal

NIA20

new

wiring,

KL10-R

ohmmeter

person

other

From

To/From

D11

~B1ON1

B13B1

D12

B19B1 K

= C1l0L2

B13B2

EBUS

D13

B19B2

EBUS
EBUS

PARITY
PIOO L

~C10K2

B13Ul-

(B1901~

EBUS

PARITY

ACTIVE

MPR7

MWBUSCTLFLDOl

MPR7 MWMGCFLDOS
MPR7

MWTIMEFLD

CBI1l

CLK2

CBI2

CLK4

CBI2

CCCHANERR

~C1l0T2
=C12H2

Cl13B1l
Cl3w1

—=Cl2aLl

C13B2

.. C:4H2

Al5R2
K,

~A14J2——KI5E]L

MPR7

MWBUSCTLFLDOl
MWMGCFLDOS8

MPR7

MWTIMEFLD

CBIl1l

CLK2

CBI2

CLK4

CBI2

CCCHANERR

backing

port

module

the

M3002.

< Cl4K2

Al5S2
%

B15A1
X

<~C20H2

w C

--A2033

F21Al
¥

[AZIEI]

#C20P1

— IA21D2
= [A2TS2

and

the

protective

backing

should

cover

gold

finger

follows:

cable

MBus

the

upper

modules

protects

——

:
-

Modules

are

lower

third noncomponent side
of the noncomponent side
inserted and/or
removed,
the

third

the

not

contacts

MBus
and
PLI
interfere
with
on

the

bus

the

module.

cables.

card

Insert

The

guide
the

port

cable,
Digital
P.N.
7019270-1J.
Be sure
to
cable so that the flat wire comes out of the
header away from the board, as shown in Figure B-3.
the

Y
———

1A1{

Port

placed

backing

Connect

—B14J
==
1

protective

orient

B20J1

each

511/

Cl9B2 ¥

e Al5D2Y.

-~ C20K2

CI9B1 X,
ClON1 -AL

«C1l4P]l

Installation

modules

f/,fii—/2

_Cl4F1 - ~[FIBAT

MPR7

Check

EBUS

the

(fire Adds )| USe=

EBUS

Protective

Name

B.4.3

check

than

1Insert the M3001 EBus interface/port ALU module in
rightmost slot of RH20 position number 5 (slot
looking at the backplane from the module side).
arrow on cable should be aligned with the arrow on
board

the
19,
The
the

connector.

the M3002 port microprocessor

Connect

the MBus cable to

1Insert

module

Connect the MBus cable to the M3003 module as shown in

Install the M3003 CBus/PLI

module as shown in Figure B-3.

M3002

slot

installed M3001 as shown in Figure B-3.
Figure

the

left

B-3.

interface module in slot 21,

which is located to the left of the installed M3002.

MODULE

BLANK

ASSEMBLY
SLOT 22

[

M3003
SLOT 21

M3002

SLOT 20
M3001

77\

SLOT19

D ]

p—
|

MR-13745

Figure B-3

the

MBus Cable Interboard Connection, Top View

Install

the

7019266-00,
blocks

being
for

module

slots
plugged

system

RH20

22,

Perform

that

ohmmeter

check

there

are

the

MBus

cable

Figure

B-3.

into

11.

Attach

the

self-sticking

Digital

P.N.

3622344-02,

12,

Power—-up

the

KL10O.

l3'

Readjust

the

existing

14.

15,

16.

The

1is

between

PT17U

and

Type

(CR)

with

KLDCP

(CR)

response
MR

FX1

De-skew

power

blank

this

ground

assembly

utilization

upper

rear

supply

and

H7420

decal,

baffle

5.0

number

panel.

0.25

H744
away

regulator

farthest

voltage

monitored

The

ground.

the

loaded

and

command

running;

prompt,

then

shown

type

FX1

below:

(CR)

the

port

100

following

steps

Connect

channel

4D33P1,

17.

Set

the

time

18.

Set

channel

level

P.N.

assembly

(CR)

equivalent

ground

breaker.

PT17U

module

the

location
of

circuit

This

ground.

module

1located

from
+5E,

the

Close the mbdule door.

adjustment

between

shorts

10.

the

Digital

22,

airflow.

Fold

number

slot

and
24,
It
prevents
modules
from
RH20 position 4 and provides a baffle

shown

This

assembly,

23,

into

cabinet

verify

blank

position

MHz

the

Figures

the

base

the

B-4

Tektronix

and

475

performing

the

B-5):

Use

gain

0.5

above

the

(MTR

MBOX

MTR

ground

MBOX

CLK

clip.

ns.

vertical
to

oscilloscope

backplane.
to

reference
of

using

oscilloscope

(see

CPU

modules

minimum

1.3

oscilloscope

V/division.

Set

the

horizontal

center

CLK

ECL

CPU

signal).
19.

Set

20.

Connect

external
backplane. Use a

sync input to
ground clip.

21,

Connect

the

oscilloscope

channel

backplane.

Set

the

sync

CDS1,

external.

CHTO

4B09Kl

the

CLK

2A21Fl

the

I/O

0.5

EBUS

channel

B-11

positive

vertical

gain

V/division.
Use a ground clip. To measure TTL voltages,
set the ground
reference to 1.5 V below the horizontal
center line of the oscilloscope.
22.

Press

the

display

23.

trigger

the

view

external

switch

sync.

the

oscilloscope

Adjust

the

display,

and

that

with

the

rising

edge

the
rising
edge
of
vertical center line

the
external
sync
aligns
of the oscilloscope.

Display

MBOX

CLK

channel

of MBOX
line of

CLK
the

H that occurs prior to the vertical center
oscilloscope. Display channel 1 and channel

Identify

the

24.

25,

Put

the

KL10-R

1/0

rear

door

Locate

the

override

access

third

the

I/0

bottom

fault

state.

Remove

the

backplane.

potentiometer

the

clock

module
(M8559)
in
slot 12 of the I/0 backplane.
Using
this potentiometer, adjust the falling edge of channel 2,
EBUS CLK L so that it crosses the rising edge of MBOX CLK
H. This crossing occurs on the horizontal center line of
the

oscilloscope.

26.

Disconnect

27.

Mount

the

28,

Load

and

all

probes.

KLAD

pack

run

the

front

diagnostic

the

troubleshoot
modules
are
installation.

as
directed
functioning

DFPTA

modules.

1If

by
the
properly,

RPO06.
to

verify

©proper

the

modules

fail,

diagnostic.
If
continue
with

the
the

T{TT

b i3 i

TrTTd

functioning

end

50mV

T[T

EREEEN)

113

TT1

-4

EXTERNAL SYNC
(CHTOH, 4B09K1)

—~—

EXTERNAL SYNC {(CHTO H)

Figure B-4

NIA20 De-skew Timing.

B-12

External

Sync

(CHTO H)

PHHHH

{EBUS CLK L, 2A21F1)

MTR MBOX CLK,

(4D33P1)

-—

—

CHANNEL 1

dvs

1111

_‘_

pay

v 1 Trr

LILERIB]

—

CHANNEL
2

—

50mVv

20nS

EBUS CKL L AND MTR MBOX CLK
MR-13746

Figure

B-5

B.4.4

Power

Three
wall

NIA20

H7420
as

Supply

power

shown

installed

De-skew

Regulator

supplies

Figure

the

Timing.

upper

CLK

and

the

I/0

located

The

H7440

regulator

H7420

power

supply

additional +5 V regqulator
is
required to support
cage and is installed as follows (see Figure 3-6):
1.

Remove

the

H7420

number

Take

the

H7440

spare
1

new

H7440

slot

top

and

one

use

H744

slot

power

filler

Save

regulator

from

H7420

thumbscrew

H7440

panel

supply.

MTR

MBOX

CLK

Installation

are

B-6.

EBUS

number

the

This

the

card

NIA20

slot

existing

the

kit

using

bottom.

side

added

location.

from

all

cabinet

and

the

install

two

Some

hardware.
the

screws

systems

on
may

regulators.
[y

B.4.5

Installation

NIA20

Card

Cage/Internal

Cable

NOTE

When

CI20

mounted

install

internal
1.

the

NIA20

cable,

1Install

the

installed,

shown

card

cage

perform

the

two

NIA20

shown

Remove

reposition

and

frame

member

(see
Figure
brackets and

B-1)
card

to
cage.

B-1.

B-8

any

the

NIA20

shown
in
Figure
B-7
following operations:

Figure

the

mounting

7430278-01,

left

Figure

CPU

brackets,

DEC

and

part

the

number

follows:

tie-wrapped

cables

from

the

cabinet

viewed

from

rear

the

NIA20

accommodate

mounting

PT7

DC HARNESS

J~_PT2\Né
\\

—

PT8

15 PIN CONNECTOR

~—————T T

‘\%’?‘
i

H744 | H744 | H744 | H744
+5H | ~6F
+5K | 5J

[H7440
|+5

1 |
—
MR-13692

Figure B-6

H7420

Power Supply

Install
4
U-nuts
(Tinnerman
nuts) ,
Digital
P.N.
9007786-00, on the left side frame member of the CPU
cabinet (viewed from the rear). Insert the Tinnerman nuts
into frame holes 18 and 49 on each vertical side frame
member counting up from the cabinet bottom. Two Tinnerman
nuts are inserted into each side frame member.

bracket,
mounting
each NIA20
1lip of
the
that
Check
the
1is at
Figure B-8),
(see
7430278-01
P.N.
Digital
bottom (used only in combined NIA20/CI20 installations).
Use a total of four 10/32 one-half inch Phillips panhead
machine screws, Digital P.N. 9006073-01 and four No. 10
star

lockwashers,

Digital

P.N.

9007651-00.

TOP

ey
W

_0—1 .,/"JG

REAR

FRONT

or [=

caBLe

STRAIN

g of—‘<_ U4

{7 [lfls,
s

%una>[

e |-

Q[e]

.
O

—

GND \-:

i T——

REAR VIEW

————

SIDE VIEW

FRONT VIEW
MR-13748

Figure
.

Locate

the

left

B-7

NIA20

side

NIA20

Card

internal

NIA20

Cage

cable

card

Views

strain

cage

relief

viewed

(white)

from

the

rear

(see Figure B-7). Because of the inaccessible location of
this
strain
relief
once
the card cage
is mounted,
the
internal cable
is be
routed
through it before the card
cage is installed.
3.

Locate

the

eight-foot

internal

NIA20

cable,

Digital

P.N.

7019893-7L.

Prepare

the

positioning
of
the
I/0
current
5.

limiter

Route

the

white

plastic

enough

slack

card

internal

a stick
cabinet

cage

the

B-7)

cable
a

relief
and

internal

on
as

when

the

plate

the
the

cable

through

card

cable

strain

cable

properly

location.

NIA20

internal

of the
Figure

B-15

for
installation
by
lower left frame member
B-9)
1located
above
the

NIA20

tighten

NIA20

the rear
shown
in

detent

CI20

internal

connect

backplane

Figure
the

strain

cable

on the
Figure

reserved

eight-foot

Connect

engages

and

NIA20

mount
(see

cage.

the

Allow

NIA20

relief.

to the J4 connector (see
NIA20 card cage and route
B-1.
The
cable
connector

seated.

C120
CARD

NIA20
CARD

CAGE

-8 CAGE
(REAR CONNECTOR

HOLE 49

PANEL VIEW)

7430278-01

MOUNTING
BRACKETS
(USED ONLY
IN COMBINED
INSTALLATION)

MOUNTING

BRACKETS

HOLE 18

CPU CABINET
(REAR VIEW)

MR-13749

Figure

B-8

NIA20

Mount
the NIA20
card
brackets
(see
Figure

Card

Cage

cage
on
the
B-8),
wusing

KL1l0O-R

two WNIA20
mounting
four
10/32
screws,

external
lockwashers,
and
flat washers.
Hang
the NIA20
card cage on the top two screws; then install the bottom
two

screws.

Install

the

Install a
member of

NIA20

card

cage

ground

cable

follows:

Tinnerman nut in hole 1 of the left side
the CPU cabinet (viewed from the rear).

frame

Connect the ground cable on the left side frame member
inserting a screw and using a starwasher on each side
the

ground

Attach

cable,

ground

label,

3613272-00,

B-16

closest

hole

by
of

Run

the

stick
the

B.4.5.l

internal

mount

rear

NIA20

cable

insert

the

other

end

the

NIA20

current

Current

Limiter

and

connector

Installation

NIA20

the

previously

the

positioned

cable

into

limiter.
--

The

NIA20

filler
plate,
Digital
P.N.
7429334-01,
mounted
above
the
CI20
plate
located on the bottom panel of the I/O cabine
t is replaced
by the NIA20 current limiter, Digital P.N. 5415695
-01
(see Figure
B-9).
Install
the
NIA20
internal
cable
and
current
limiter
as
follows:
l.

Locate

the

NIA20

filler

plate

cabinet.
Remove

the

four

screws

install

aligned

threaded

Connect

the

also

screws

the

holding

NIA20

the

cable

BNE3

cable
to
the
front
current limiter (see

LOCATION

MOUNT

the

filler

current

the

external

rear

plate

save

its

rear

connector

and

located

transceiver)
on

the

B-9).

NIA20 CURRENT LIMITER

5415695-01

INTERNAL

BNE3

CONNECTOR

CABLE

<
TO 7019893-7L

_———’

TO J1 CONNECTOR

———

b=t

O O

TRANS

C120 BULKHEAD PLATE

|oo
RSCY
A

RSCV
B

“~

"
h
I

TRANS

CABLE TROUGH

I/O CABINET

2
CPU

CABINET
MR-13750

Figure

B-9

1/0

and

CUTAWAY VIEW

EXTERNAL ~__
|

the

using

limiter

(Ethernet

connector

Figure

STICK

the

holes.

internal

connect

B|
i

from

NIA20

Current

Limiter,

Cutaway

View

NIA20

B.4.5.2

Installation

The

following

harnesses

are

installed:
AU
D WIN -

Harness

Figure

power

Vane

harness

switch

cable

PLI bus
BNE3 external

B-10

shows

The

diagram

harnesses

the

harness

installed

and

cable

follows:

approximately eight inches apart on all
routing
cables
<close
to
internal

use

spiral

Locate

two

sections

7019272-00,

are

assemblies,
the

sections)

cable.

Install tie-wraps
harnesses.
When

P.N.

sections)

DC voltage monitor cables (two
Fan ac cable and power cord

interconnections.
1.

(two

and

wire-wrap
of

the

7019273-00

protect

power

(see

Attach
one-half
of
dc¢
power
7019272-00,
connecting
Pl
of

the

cables.

harness,

Figure

Digital

B-11).

cable,
Digital
dc
power
<cable

P.N.
into

connector Jl1 of the NIA20 card cage backplane (see Figure
B-7). Next,
connect P3 of of dc power cable into J2 of
the
NIA20
card
cage.
Locate
the
black
and
blue
wires
labeled PT5 and PT6 of the dc power cable and connect the
black wire to -5.2 ground; then connect the blue wire to
-5.2H in the CPU cabinet (see Figure B-2).
4,

Locate

the

half

the

power

cable,

Digital

P.N.

B-11),
and join its end labeled
half of the cable
(Digital P.N.

Tie-wrap

the

harness

and

Figure

B-1l.

contacts

H7420

other

70-19273-00
(see Figure
Jl
to
P2 on the other
7019272-00).

other

Use

the

through

spiral

side

supplies

red

and

the

the
the

wrap
the

(see

white

reconnect

Connect

harness

existing
cabinet

along

I/0

Figure

wires
(see

floor

the

frame

KL10~R

CPU

power

shown

harness

where

member

nearest

it
the

B-1).

labeled

the

power

(see

Figure

B-11l),

(see

Figure

B-6).

Figure

PT7

and

B-1l).

PT8

the

P3
from power
supply H7420
number 1,
then connect PT7 and
PT8
to pins
3 and 4,
respectively,
on P3 of the H7420.
Then

end

harness

route

power

Locate

new

Disconnect

H7420.
cable,

connector

Digital
of

the

P.N.

7019273-00

H7440

regulator

Locate the vane switch cable, Digital P.N.
70-19862-01
(see Figure B-12). Connect Pl of the vane switch cable to
connector J1 on the card cage (see Figure B-7). Use stick

B-18

mounts

and

protect

the

spiral

vane

wire-wrap

switch

needed

route

cable.

and

NOTE

When

the

two

CI20

used

installed,

supplied
in

(Digital

EK-CI20-RM-001)

installation

10.

Connect

the

cage.

card

Remove
Figure

12.

13.

14.

other

vane

switch

KL10

CPU

the

NIA20

cable

vane

of the vane switch
switch assembly.

the
CPU/NIA20
air
flow
existing
CPU
air
fault message
switch.
Locate

the

two

P.N.

Connect

and

route

cable
second

the

and

7021448-5C

the

other
(see

section

voltage

connector

end

(Pl)

Locate

the

switch

cable

along

voltage

off.

slot
cage.

16.

Attach

voltage
Connect

the
Lo
dc

the

and
(see

original

KL10

monitor

cable,

Figure

B-14).

(Digital

cage

inside

monitor

voltage

P.N.

backplane

cabinet

with

cable

connected

board

over
the
863
fault

the

(Digital

the

(Digital

monitor

top

board.

P.N.

Only

should be on, while all other switches should be
Insert
the dc
voltage monitor
board
into
the +5 V
(see
Figure
B-2)
of
the
dc
voltage
monitor
card

the

indicating

17.

the

connecting

(see

card

the

switches

voltage

the

7021448-5C)
which has its Pl
the
new
dc
voltage
monitor
5414506-01)
.

15.

the

(P4)

cable

monitor

B-1l)

P.N.

cable

Figure
dc

connector

fault
decal
decal
on
the

sections

trough

7020352-00

7020352-00)

switch

cable

Apply

Digital

CI20

switch

vane

number

applicable

B-13).

Connect

CPU

the

this

order

for

procedures.

original

connect

11.

shorter

switch
cables
is
a
combined
CI20/NIA20
Consult the CI20 reference

installation.
manual

the

vane

monitor

the

monitor

panel

RH20
board.

decal,

slot

Digital

position

P.N.

used

for

3621499-01,

the

NIA20

the remaining single orange wire of the Pl end of
voltage monitor cable
(Digital P.N.
70221448-5C)
a location adjacent to the existing orange wire on the
voltage monitor board zone +5L.

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CPU CABINET

7019272-00

REDWIRE
|3

2]P3ONH7430

(WIRE SIDE)

WHITE WIRE

H7440

CONNECT

TOGETHER

POWER
REGULATOR

7019273-00

MR-13752

18.

Tie-wrap
to

the

monitor and vane switch harnesses
Use adhesive-backed square cable

voltage
cable.

power

mounts

support

the

harness

the

side

the

cage.

Locate
60 Hz)

the fan ac cable, Digital
or 7020539-06 (240 Vac 50

end

the

861

NIA20

P.N. 7019274-06 (120 Vac
Hz), and the power cord,
Digital
P.N.
9107673-06
(120
Vac
60
Hz)
or
7011432-02
(240 Vac 50 Hz)
shown in Figure B-15. Connect P2 of the
fan ac
cable
to connector J2 on the card cage and then
join the fan ac cable to the power cord. Insert the other
power

power

adjacent

20.

DC Power Cable

the

card

19.

Fighre B-11

cord

side

any

available

Connect

ground

screw

electrical

Install

Tinnerman

attach

the

ground

frame.

Use

two

good

nut

cable

the

ensure

starwasher

connection.

controller.

NIA20

hole

from

the

NIA20

starwashers

switched
ground

ensure

outlet

wire

card

cage.

on
the

Use

connection.

the

card

good

frame

cage

and
the

electrical

Figure B-12

Vane

Switch

Cable

VANE

SWITCH
CONNECTOR

BEFORE

VANE SWITCH CABLE

P4
. ————————

VANE

SWITCH
CONNECTOR

1/O CABINET <tet

CONNECTOR

AFTER
MR-13740

Figure

21,

B-13

Vane

Switch

Harness

Locate the PLI cable,
Digital
B-1
for
cable
route
and

Installation

P.N.
BCO6R-08
Figure
B-10

(see
for

Figure
cable

interconnection).
Connect
one
end
of
the
PLI
cable
(identified by a red line imprinted on top of the cable)
to module M3003, and route through cable strain relief on
the
NIA20
card
cage.
The
other
end
of
the
PLI
cable
(identified by a red line imprinted on the bottom of the
to connector J3 on the NIA20 card cage (see Figure
B-7).
To
secure
the
PLI
cable,
install
adhesive
foam,
cable)

Digital
P.N.
1213716-00,
within
each
of
the
four
flat
cable clamps.
Install one cable clamp on the side of the
CPU card cage, and three cable clamps across the top rear

air

shroud

assembly.

the

module

22.

Replace

23,

Locate the BNE3
cable
along
the
then

out

the

(see

I/0

the

external cable.
Route the BNE3 external
bottom of
the CPU and
I/0 cabinets and

bottom

front

Figures

B-1

door.

the

I/0

cabinet.

connector

the

and

B-9).

B-23

Connect

NIA20

the

current

cable

limiter

CONNECT

7021448-5C

CAGE

J5
7020352-

00
ADJACENT TO

ZONE +5L

DC VOLTAGE

MONITOR
BOARD
MR-13755

Figure

B-14

Voltage

CONNECT

Monitor

FAN AC CABLE

Cable

7019274-06 (60 Hz)

GROUND

7020539-06 (50 Hz)

POWER CORD

9107673-06 (60 Hz) ~
7011432-02 (50 Hz)

861

POWER

CONTROLLER
SWITCHED
QUTLET

' —

Figure

B.4.6

B-15

Installation

Fan

KL10

Cable

Adapter

and

Power

Board

and

Cord

Blank

Module

Assembly

The

KL10

module
NIA20

adapter

assembly,

card

cage

board,

Digital

P.N.

follows:

P.N.

7014103-00,

L0072-00,

are

and

the

installed

blank

the

The
KL10
to
NI
adapter
board
and
assembly are installed into the NIA20
rear of the CPU cabinet.
2.

Install

LZ;

B.4.7

the

Fght-hand

adapter

board

blank
module
cage from the

(L0072-00)

the

(7014103-00)

the

slot.

Install

KL10

the
card

the

blank

module

assembly

7.
adjacent slot to the lefbwRIGH
Checkout

The physical part of the installation is complete at this point.
All that remains is to verify that the system runs properly in the
new
configuration.
Perform
the
following
steps
to
verify
the
installation.

Verify

that

the

KL10-R

longer

the

override

fault

state.

Power—-up

the

KL10-R.

Readjust

the

power

supply

5.0

0.25

This

adjustment
is
located
on
power
supply H7420
number
1,
regulator H7440 slot 5
(see Figure B-6). This regulator
is
located
nearest
the H7420 power supply breaker.
The
voltage
1is
monitored
at
the
black
and
red
connector J1 of the NIA20 card cage (see Figure
4.

Load and run diagnostic
executive mode.

DFPTA

for

least

five

passes

Load

DFNIE

for

least

five

passes

DFNIA

for

least

five

passes

mode

for

and

run

executive
6.

wires
B-7).

diagnostic

mode.

Load and run diagnostic
executive mode.
Enable

Run

the

operating

diagnostics

system.,

DFPTA

user

NIA20

test

least

five

passes.

Run
four

diagnostic

UETP

user

mode

for

least

hours.

10.

Disable

the

operating

system.

l11.

Remove
all
field
customer's system,

service
and store

12.

Transfer/sign-off
representative.

system

packs
and
in a secure
to

tapes
area.

customer's

from

the

authorized

—

INDEX

Abort,
ALU,

Heartbeat,

1-11

H4000,

5-2

Am2910,

1-7

1-6

5-49
I

Idle
Backoff,
BLINK,
BSD,

1-11

2-2,

2-12

Sense,

1-6,

Coaxial
Command

CRAM

5-36
5-29

Cable Connection,
Queue, 2-8, 2-14,

1-7
5-81

1-10

5-50

PE,

CSMA/CD,
CSR,

KL10-E,

3-1

KL10-R,

B-2

LAN,

1-1

LAR,

5-47

LDPTT

1-1

LDMCAT

2-14,

2-42,

4-2,

5-2

Field, 1-10
Formatting,

Destination

2-24

Command,

Local

Command,

Local

Storage

2-26

5-103

RAM,

5-63

1-7
:

Address,

1-9

Manchester
MBus,

3-9

2-25

Response,

2-21

MCAT,

DGSNT

Response,

2-23

MCATLD

Discarded

Datagrams,

2-40

Encoding,

Response,
Microcode, 5-65

1-11

2-26

Microprocessor Control
Microsequencer, 5-44

EBus,1-5, 4-6, 5-2,
Removal,

5-64

2-39

DGRCV

Error
Error

Command,

Local Store Address Register,
Loopback Commands, 2-38

DC To DC Converter,
Defer, 1-10

Entry

5-16

2-21

Data
Data

Word,

2-13

1-12

4-13,

CMVR Interface Module,
CNTRC Response, 2-27

CRC,

Mode,

Carrier

CRAM,

5-70

Compatible

Initialization, 5-65
IOP Function Control

2-19

CBus,

Loop,

Industry

5-14, 5-20

2-11

Events, 2-41
Handling, 2-39
Ethernet, 1-1, 1-8, 2-43
Event Counters, 2-41

Microword
MOP, 2-39
M3001,
M3002,
M3003,

INDEX-1

Fields,

1-5,
1-6,
1-6,

5-1
5-1
5-1

5-51

Logic,

5-65

Network
NI,

Architecture,

2-43

1-1

NIA20,

1-3
KL10-D Installation, A-1
KL10-E Installation, 3-1
KL10-R Installation, B-1
Receive Operation, 4-30

Transmit Operation,
NSARD Response, 2-36
NSAWRT

Response,

4-27

2-38

Self

Commands,

Command,

Source

Address,

1-10

Transceiver,

Cable
Transmit,

1-6,

1-12

Connections,
4-27,

Field,

5-81

1-10

Packet

Format,

1-8

Packing

Mode,

2-39

Parity
PCB,

Predictor,

Watchdog

5-39

PLIWRT

Pointers,
Port, 1-5
ALU,

2-37

WRTPLI

Command,

2-32

2-33

2-2
5-2

Driver

commands,

Microprocessor,
States,
Preamble,

2-14

5-41

4-1

‘

1-9

PTTLD Response,

2-25

Q
Queue

Entry

Removal,

Headers,

2-11

2-8

Interlocks, 2-3
Locations, 2-3
Structure, 2-2

R
RAR,

5-46

RCCNT

Command,

2-27

RDNSA

Command,

2-35

RDPLI

Command,

2-33

Receive, 4-30, 5-73
Response Queue, 2-6,
Retransmit, 1-11

1-7

Command,

2-34

Response,

Timer,

WRTNSA

2-4

PLI, 4-20
PLIRD Response,

2-38

2-15

Type

Directed

SNDDG

2-15

INDEX-2

1-8,

1-12

01752