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Document:	MSV11-J MOS Memory User's Guide
Order Number:	EK-MSV1J-UG
Revision:	001
Pages:	68
Original Filename:

OCR Text

EK-MSV1J-UG-001

MSV11-J

MOS Memory
User's Guide

dlililtlall}

EK-MSV1J-UG-001

MSV11-J

MOS Memory
User's Guide

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, May 1985

Printed in U.S.A.

The reproduction of this material, in part or whole, is strictly prohibited. For copy information, contact the Educational Services
Department, Digital Equipment Corporation, Maynard, Massachusetts 01754.

The information in this document is subject to change without notice. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.

The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts.

DEC
DECmate

dlilglit]al ]

MASSBUS
PDP

DIBOL

Rainbow
RSTS
RSX

VMS
VT

DECUS

P/OS

Work Processor

DECwriter

Professional

UNIBUS

VAX

CONTENTS

GENERAL DESCRIPTION AND SPECIFICATIONS

1
2
2.1
2.2
2.3
24
2.5
2.6
2.7
3
3.1
3.2
3.3
4
4.1
4.2
4.3
4.3.1
4.4
44.1
4.4.2
443
4.5
4.5.1
4.5.2

Introduction . ........ ... ..o
i
e I-1
1D J1T0) o131+ )+ P 1-3
Error Correction ........ ... . i
it e 1-3
Battery Backup ...
i e 1-3
ECC Initialization .......... ... ..ottt 1-3
Control and Status Register (CSR) ..o, 1-3
Bus Cycles . ... 1-3
Refresh ... 1-4
Simplified Block Diagram Description ...........c.coviiiniiiiinnnnnn.. 1-4
Error Correction Code (ECC) ...ttt 1-6
Advantage of ECC ... ... .. i 1-6
ECC Operation . .........c.uiuiiiiii
e
e 1-7
Example of ECC-Implementation .................coiitrnnnnnnn. i-7
SPECHICAtiONS . ......ootittii
ittt
e 1-7
General Specifications . ...........coviiiiiiiiiiiiii
i 1-7
Environmental Specifications ................ ..., 1-8
Electrical Specifications ................coiiiiiiiiiiieinanannnn. 1-9
Power Supply Requirements ..............
.. ..., 1-9
Interface Specifications ........... .. ..ottt 1-10
P-BusInterface ..........coiinuiiiiii
e 1-10
Q-BuslInterface ...............iiiiiiii 1-10
Signal AC/DC Loading ...........c.uiiiiiiiiiiiiiiiianann. 1-10
Performance Specifications .................
it 1-10
P-Protocol Access and Cycle Times (All MSV11-J Variations) ...... 1-11
Q-Protocol Access and Cycle Times (MSV11-JD and MSV11-JE
Variations Only) ......... ... i 1-12

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el jowsd busd

emd pumd jemmd jaamd powd

sl posmd pnemd mmd

CHAPTER1

CHAPTER 2

DATA FLOW

2.1
2.2
2.3
2.3.1
2.3.2
2.3.3

Introduction . ........ ... i
2-1
Address Portion of Bus Cycle .............
... ... oo
... 2-1

Data Transfer Portion of Bus Cycle .............. ..o,
Read Data Transfer .......... ... .. . . .
i
...
Write Data Transfer . ......... ... . .
Write Byte ...

2-2
2-3
2-4
2-5

CHAPTER3

MEMORY CYCLES

3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
34

ane 3-1
e
INtrOdUCHION oottt e e et ittt it aaeeaseencaneaenaa
BUS CYCIES « ittt it 3-1
it e 3-1
t
Read Cycles . ..vvviiniee iieaa
Memory Read Cycle ........ccoiiiiiiiiiiiiiiiiiiiiiinnan, 3-1
eeeanannn, 3-1
e iiiene
CSR Read CyCles ...oiiiiiiiiiiiiii
eeaes 3-2
Write Word Cycles . .....ouetiiiiiiiiiiiiii ittt
Memory Write Word Cycles .........c.oiiiiiiieiiiininna., 3-2
CSR Write Word Cycles .......oviiiiiiiiieeiiiianananneeenenns 3-2
e 3-2
Write Byte Cycle . ...
nnnnas 32
iencnenenen
nenrienenea
.vvviiniiie
..
CyCIES
Read
Biock Mode
i 3-3
e
iiieee
iiii
ittt
viei
..oo
..
Cycles
Write
Block Mode
3-3
nnnn
iiiiiiiiiiea
iiiiiiiiiiii
.........coi
Cycle
Write
Read-Modify3-3
.t
..
Cycle
Byte
-Write
Read-Modify
Refresh Cycle . ..uvinnie ittt iieraieeanesansraetoneenanannns 3-4
annnns 3-4
iii
onsessannneea
iei
it iiiiniteeanan
ECCINIT CYCIE . .ittti

CHAPTER 4

CONFIGURATION AND CSR OPERATION

4.1
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.1.3
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.3.3.1

INtrOdUCHION ..ottt t ittt it i eeeeaeeeaseacaecnacennennenaasnnanassses 4-1
Module Installation .........covieieierirenrieecenenenonaesnnananasasss 4-1
Jumper Configurations and Switch Settings ...................oooonlt. 4-1
Jumper Installation . ......... ..ot 4-2
Memory Address Switch Settings ............... ool 4-3
CSR Address Switch Settings ..........coiiiiiiiiiiinrinnnnnns 4-5
Backplane Placements ............ccoiiiiiiiiiiiiiiiiiiiiiiiaann. 4-6
Control and Status Register (CSR) ..., 4-7
nanens 4-7
tt
ittt tiieeeiaenanina
Bit Format of CSR ...ttt it
Bit Descriptions of CSR ... ... 4-7
Operating Modes ........oouiiiiiiii ittt 4-14
Normal Mode (ECC Enabled) ..............ccoiiiiiiiiin, 4-14

CHAPTER 5

DIAGNOSTICS

5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.4
5.4.1

(€ 1= 1 1= ) AR U 5-1
Preventive MaintenancCe ...........c.coeeiuuieeenneonneeenneennnnennneenns 5-1
nnnns 5-1
ii
ieniiirnaieeaniaeen
itnnnitii
Diagnostic TEStNG . ....oov
5-1
N
| £ T80 V6 1} T3 1 ) + RP
Operational Switch Settings ............coiiiiiiiiiiiiiiiiii
.., 5-1
CVMIJAQO Diagnostic Operation ...........ceeeiiiiiirrennenenennn. 5-3
Example 1 — Error Free Printout ................... ..ol 5-3
Example 2 — Printout Containing Memory Errors ................... 5-6
Example 3 — Printout Showing Non-Contiguous Memory ............ 5-7
Digital’s ServiCes . .....veeeeetetenini
ittt i
i 5-8
Digital Repair ServiCe .. ......c.uuuueeiiirnnnrieieeeeeenenns 5-8

4.3.3.2
4.3.3.3
4.3.3.4
4.3.3.5
4.3.3.6
4.3.3.7
4.3.3.8
4.3.4

Normal Mode (ECC Disabled) .........coovvvieiiiiiiiii.t. 4-15
Normal Protected Mode (ECC Disabled) ......................... 4-17
Diagnostic Mode (ECC Enabled) ..., 4-18
Diagnostic Mode (ECC Disabled) ................coooiiiiiiin, 4-19
Protected Diagnostic Mode (ECC Enabled) ....................... 4-21
Protected Diagnostic Mode (ECC Disabled) ...................... 4-22
Operating Modes Summary .........ooeeiviiiiiinineennneen, 4-23
Error REPOrting . ...ounrtitteeiiiiiitttiiennnnnaaeeenannunens 4-26

S-NNVS
R S I LBV
N O JO NS TM

—-b-t.nl\)'—

FIGURES
Q-Bus/PMI Bus Interface .....
. ...
.....
...
....
, 1-1
UNIBUS/PMI Bus Interface ........... ... .. ..o i
. 1-2
MSV11-J Simplified Block Diagram ............
e...oo
. 1-5
MOS Storage Array Architecture .................erereeiinnnn. 1-5
Address Flow (Read, Write, Write Byte) .........ooo oo 2-2
Read Cycle Data Flow ........ ... .. ... . . .. i, 2-3
Write Cycle Data Flow ......... ... ... i, 2-4
Write Byte Cycle Data Flow ....... .. .. ... ... o i 2-5
Byte Selection for Write Byte Operation ............
... ... ......
... .. .. 2-6
Odd/Even Memory Request for Block Mode ............
o .....
oo ..., 3-3

MSVII-JJumpers ......
e
.oo
e
ni
Battery Backup Jumper Connection .............. ...,
+5 V Jumper Connections ...............courueneenn
CSR Bit Assignments ..............o.oueiinmnn i

4-2
4-3
4-3
4-8

TABLES
1-1

Q-Bus Cycle- MSV11-JDand-JEOnly ............oovurininnn
. 1-4
PMIBus Cycle ...
i 1-4
Starting Memory Address Selection ..................o oo, 4-4
CSR Address Selection ... ...........uiuineeeiee 4-6
Backplane Pin Utilization ....................... et 4-7
CSR Bit Descriptions .............ouurumnmee
i 4-8
Operating Modes .......... ... i 4-14
Error Condition Summary for Various Operating Modes .................. 4-24
Error Logging ... 4-26
Switch Settings ...ttt 5-2

CHAPTER 1
GENERAL DESCRIPTION AND SPECIFICATIONS

1.1 INTRODUCTION
The MSVI11-J is a metal oxide semiconductor, random access memory. It uses error detection and
correction (ECC), a control and status register (CSR) to store status and error information, and has
starting addresses on 8 kW boundaries. The board can be configured half or fully populated with 256K
dynamic RAMs. Maximum memory capacity is 2 Mb.
The memory is designed for Q-bus systems and supports the private memory interconnect (PMI) protocol
of the KDJ11-B processor. The PMI bus is specifically designed for and used in the PDP-11/83 Q-bus
System and the PDP-11/84 UNIBUS System.

A PDP-11/83 Q-bus system uses the KDJ11-B CPU module, one or more MSV11-J memory modules and
a selection of Q-bus compatible devices. Data transfers between the KDJ11-B CPU and MSV11-J
memory use the PMI protocol. All other communications, whether originated by the CPU or other bus
master, occur via Q-bus protocol (Figure 1-1).
‘

NOTE: The location of the MSV11-J in the PDP-11/83 backplane determines the protocol used
between the KDJ11-B and the MSV11-J. For PMI protocol, the MSV11-Js must be located immediately in front (lower slot number) of the CPU; otherwise the memory and CPU communicate with the
Q-bus protocol. There should be no open slot between memory and the CPU.

mg}/fig;v

E?d‘ 18

Q-BUS

COMPATIBLE
DEVICES

N
SHRA.0259-84

Figure 1-1

Q-Bus/PMI Bus Interface

A PDP-11/84 UNIBUS system uses the KDJ11-B CPU module, one or two MSV11-J memory modules,
the KTJ11-B UNIBUS adapter (UBA) module, and a selection of UNIBUS compatible devices. The
KDJ11-B, MSV11-J, and KTJ11-B modules communicate via PMI protocol. All communication between
UNIBUS devices and the KTJ11-B occur via UNIBUS protocol. The KTJ11-B provides the appropriate
interface between PMI and UNIBUS protocols (Figure 1-2).
1-1

KDJ11-B
CPU

KTJ11-B
UNIBUS
ADAPTER

UNIBUS
DEVICES

MSV11.J
MEMORY

UNIBUS

DATA/ADDRESS

>
SHR-0274-84

Figure 1-2

UNIBUS/PMI Bus Interface

The MSV11-J memory provides the following features.
Starting addresses on 8 kW boundaries
Can be half or fully populated

Executes normal Q-bus protocol and the faster PMI protocol. Q-bus protocol is possible only

with the MSV11-JD and MSV11-JE variations.

Uses two gate arrays (VLSI technology)
Uses advanced Schottky TTL logic

Battery backup can be configured on board

Green LED on module to indicate the presence of +5 volts (+5 VBB when configured for
battery backup)

On-board refresh of RAMs is transparent to CPU
Compatible with 18- or 22-bit address backplane

Error correction logic (ECC) to detect and correct single-bit errors and to detect double-bit
errors

Red LED on module to indicate detection of an uncorrectable error
Contains control and status register which can be assigned one of 16 addresses

Error correction code (ECC) operation can be controlled via CSR
CSR operating modes facilitate diagnostic testing

Memory compatible with Q-CD backplanes (not compatible with Q-Q backplanes)
Insertion of the MSV11-J in a Q-Q backplane may damage other components or the memory
itself. The PMI bussing on the MSV11-J’s CD connectors is not compatible with the +12 V bussing on

NOTE:
sl
e

N N
Y-/

L1
...
Uulhpidrc.

1-2

1.2 DESCRIPTION
The MSVI11-J is an LSI-11 Q-bus quad-height module. It uses error cerrection (ECC) for increased
reliability and is available in the following configurations.

Option
Number

Module
Designation

MSVI11-JB

M8637-B

MSV11-JC

M8637-C
:

MSV11-1D

M8637-D

MSVI1-JE

M8637-E

Description
1 Mb ECC using 256K dynamic RAMsPDP-11/84 ONLY
2 Mb ECC using 256K dynamic RAMsPDP-i11/84 ONLY
1 Mb ECC using 256K dynamic RAMs-

PDP-11/84 or PDP-11/83

2 Mb ECC using 256K dynamic RAMsPDP-11/84 or PDP-11/83

NOTE: Modules designated MSV11-JB and MSV11-JC may be used in the PDP-11/84 (UNIBUS)
system only. Modules designated MSV11-JD and MSV11-JE may be used in both the PDP-11/84 and
PDP-11/83 (Q-bus) systems.
The memory starting address can be set at any 8 kW boundary within the 2048 kW extended address

space. (The extended address space contains 22 address lines.)
1.2.1
Error Correction
The MSV11-J contains ECC logic which detects and corrects single-bit errors and detects double-bit
errors. Detecting and correcting single-bit errors is transparent to the master device accessing the memory.

1.2.2 Battery Backup
MOS storage devices are volatile (data is not retained when power is lost). Therefore, during an ac power
failure, dc power is available to MOS memory for a limited time only. The MSV11-J memory module has
inputs for two sources of +5 V power. These inputs are designated +5 VBB and +5 V. The +5 VBB
module input can be connected to a battery backed-up power system; the +5 V input is not battery
supported. In battery support mode, power is used only to refresh the MOS storage array so that battery
backup time, and therefore data retention time, is maximized. A green LED on the module stays on as
long as +5 VBB is available. Modules are shipped in a non-battery backed-up configuration; the module
needs a jumper change to configure it for battery backed up applications.
The PDP-11/84 system can be shipped in a battery backup system configuration or in a non-battery
backup system configuration. In a battery backup system configuration, the memory is tied to the battery
backup supply through the backplane and power connector. Therefore, the MSV11-J modules should not
be configured for battery backup mode in either of the above mentioned system configurations.
1.2.3 ECC Initialization
The MSV11-J performs an error correction initialize (ECC INIT) operation after the power-up (+5 BBU
power up in battery backed up systems). For an ECC INIT operation, a pattern is written into all memory
locations in the MOS storage array. All MOS RAMs on the module are written sequentially during
initialization. The circuitry senses the presence of 5 VBB and DCOK before starting the initialization
sequence. Signal BPOK is deasserted by memory while ECC INIT is in progress.
1.2.4 Control and Status Register (CSR)
The control and status register in the MSV11-J allows program control of certain ECC functions, and
stores diagnostic information if an error occurs. The CSR has its own address in the 1/O peripheral page,

and can be read or written into by any device designated as bus master.
1.2.5 Bus Cycles
The MSV11-J supports the following Q-bus and PMI bus cycles (Tables 1-1 and 1-2). These bus cycles.
executed by bus master devices, transfer 16-bit words or 8-bit bytes to or from slave devices.

1-3

Table 1-1

Q-Bus Cycle - MSV11-JD and -JE Only

Bus Cycle
Mnemonic

Description

Function (with Respect
to Bus Master)

DATI
DATO
DATOB
DATIO

Data word input
Data word output
Data byte output
Data word input/output

Read
Write
Write byte
Read-modify-write

DATBO

Block mode output

Block Write

Data word input/byte output
Block mode input

DATIOB
DATBI

Table 1-2

Read-modify-write byte
Block Read

PMI Bus Cycle

Bus Cycle
Mnemonic

Description

Function (with Respect
to Bus Master)

(P) DATI*
(P) DATBI*
(P) DATO*
(P) DATOB*

Data input (2 words)
Block mode input
Data word output
Data byte output

Read
Block mode read
Write
Write byte

* The P in parentheses preceding the cycle type denotes PMI cycle.

1.2.6

Refresh

The MSV11-J refresh circuitry guarantees that the data stored in the MOS RAMs is valid for extended
periods of time. The interval between refresh cycles is set to about 14 us to guarantee accessing all 128
rows in 2 ms (128 cycle refresh) or 256 rows in 4 ms (256 cycle refresh).

Refresh requests are initiated every 14.0 us + 5 percent from an asynchronous oscillator on the module.
These single refresh cycles are initiated at the end of a bus memory access. If the memory does not receive
a bus memory access request within 9 us of a single refresh request, it changes that request to a double
refresh request, appending two refreshes to the end of the next bus memory access. Double refresh is not
valid on the MSV11-JB or MSV11-JC memories.

A refresh priority cycle is enabled if a bus memory access has not occurred within two refresh periods (i.e.,
28 us) and the refresh request cycles have not been peformed. During a refresh priority cycle, the next
memory cycle is preceded by two refresh cycles. If a memory cycle is not initiated within 3 us of the

assertion of refresh priority cycle, the refresh logic initiates its own refresh demand cycle.
1.2.7

Simplified Block Diagram Description

Figure 1-3 is a simplified block diagram of the memory. The bus interface, address gate array, data gate
array, and MOS storage array are shown. The address gate array contains the ECC initialization circuitry,
memory refresh circuitry, and the timing and control for PMI and Q-bus cycle types.
\
The data gate array contains the ECC logic, generates check bits for write cycles, and uses the check bits
during read cycles to detect and correct single-bit errors and to detect double-bit errors.

The half-populated MOS storage array consists of two blocks — block 0 and block 1. The fully populated
A AAC ot mom
ea momricr mcicote ~f P Wlaabe
klaaba N
1
A
o
an
Anl e
fte werida o
MUOS siorage array consists Of 10Ul DIOCKS — DIOCKS U, I, 2, and 3. Each block is 22 bits wide and 256K
deep (see Figure 1-4).

)
2

CONTROL

aooresse

ADDRESS BUS

RAS

|amver |cas

ARRAY

8LOCK 0 :EBIT

|WR

16BITS

| ECC

CONTROL

[77]

BLOCK1

| 6BIT

16BITS

| ECC

DATA

DATA BUS

DATA
GATE
DATA®

ARRAY

s
*PMI BUS SHARES QBUS ADDRESS AND DATA LINES
SHR-0264-84

Figure 1-3

MSV11-J Simplified Block Diagram

BLOCK 0

”~

_—

1
r&—— BITS

BLOCK 1

—

e—— BITS

22
— o
0

HALF

POPULATED

256K RAM CHIPS

|256K RAM CHIPS

512

( Kw

FULL
>POPULATED
22
256K RAM CHIPS

22
[256K RAM CHIPS
1024

KW J

—V

BLOCK 2

BLOCK 3

256K RAM CHIPS STORAGE ARRAY

SHR-0271-84

Figure 1-4

MOS Storage Array Architecture

1-5

The 22-bit words in memory consist of 16 data bits and 6 check bits. The check bits are generated by the
data gate array for each 16-bit data word. Although the MSV1 1-J memory word is 22 bits long, the bus
master transactions are 16-bit words. The 6 check bits are internal to the memory.
The control and status register (CSR) performs the following major functions.
e

It disables or enables error reporting to the CPU.

It allows diagnostic programs to be run without having the diagnostic interfere with the check

bits in the protected diagnostic area.

It disables ECC, if desired. MSV11-J detects but does not correct errors.

It flags single- or double-bit errors. If ECC is enabled, single-bit errors are corrected.

The address of the error is latched in the CSR unless higher priority (double-bit error) is
present.

o
1.3

In diagnostic mode, syndrome or check bits can be returned to the processor if desired.

Error Correction Code (ECC)

ECC is a technique used to increase reliability of MOS memory. This is done by correcting single-bit
errors. The use of ECC with MOS memory requires additional logic to generate check bits used in the
detection and correction process.

ECC is practical not only due to the low cost of memory and logic, but also because the predominant
failure mode in dynamic RAMs is single cell failures, distributed randomly. These failures occur at a low
rate and the probability of two such failures (or one such failure and a soft bit error) occurring in
coincidence is extremely small.

Advantage of ECC

1.3.1

MOS RAM technology is constantly evolving and the RAM density quadruples for each new RAM
introduction. Larger memory arrays make the probability of errors slightly higher even though the

reliability of RAMs is improving.

Some advantages of using ECC with MOS RAM technology are:

MOS RAMs, unlike core, are more susceptible to noisy power supplies.

Soft errors due to inherent radiation traces (alpha particles) occasionally cause an individual bit
in the RAM to lose its data. These soft errors are overwritten during the next WRITE to that
location. ECC prevents a system failure until the overwriting can occur.

Most hard errors (due to aging or premature defect of the RAM) occurring in a desired (by

CPU) address cause a failed bit.

These three types of failures cause a system failure in parity memory but are transparent in ECC memory.
ECC makes single-bit failure in the RAM transparent to the CPU by correcting single-bit errors “on the
fly” before the CPU receives it. It thereby increases the effective MTBF (mean time between failures) of
main memory. Also the memory failure rate doesn’t proportionally increase as memory capacity increases.

1.3.2 ECC Operation
A check bit code is generated on each memory write cycle. This code is written into memory along with
the 16-bit data word. On a memory read cycle, the check bits are read from memory along with the 16-bit
data word. New check bits are generated and compared with the check bits read from memory. If the two
groups of check bits are alike, no error is detected. If they are different, the difference between the two
groups of check bits (syndrome bits) determines the failed bit, provided there is only one error. The ECC
circuitry corrects the bit in the word and sends the word to the CPU.,
In the case of a multiple error, the word is not corrected and is sent to the CPU with an asserted signal line
warning the CPU that this data is invalid. This signal has the same effect as a parity flag in parity
memory, at the occurrence of a single-bit error.

1.3.3 Example of ECC-Implementation
A fully populated MSV11-J is a 2 Mb memory. The memory storage consists of 22-bit words, (16 data bits
plus 6 check bits) each bit position being in a different memory chip (RAM). However, the CPU reads
from memory, or writes to memory, in 16-bit words.
For a write cycle (DATO function), the memory receives (from the CPU) the 16-bit word and generates
the 6 check bits. This new 22-bit word is stored in the memory array.

For a read cycle (DATI function), the 22-bit word is fetched from memory and divided into two; the
original 16-bit word (data) and 6 check bits. New check bits from the 16-bit data word are generated and
compared with the check bits read from memory. If a single-bit error occurs, the ECC circuitry in
memory corrects the data word containing the error. The corrected word is then transferred to the CPU.
The data in the original memory location remains uncorrected.
For a DATOB function, only a byte is written into memory. To accomplish this function, the entire 16-bit
data word and 6 check bits residing in memory must be read and checked for errors. Any single-bit error
in the word is corrected. Assume, for example, that the CPU desires to write the lower bvte. The new
lower byte is combined with the high byte to form a new 16-bit data word. Check bits are generated on the
new word and the entire word (16 data bits plus 6 check bits) is written back to memory.

ANE
I

The sequence of events is:
22 bits read from memory.
Single-bit error corrected, if required.
New byte combined with old byte.
6 check bits generated on new 16-bit word.
New 22-bit word written to memory.

1.4 SPECIFICATIONS
This paragraph describes the various MSV11-J specifications including access and cycle times for the
Q-bus and P-bus protocol.

1.4.1

General Specifications

Height

10.436 inch quad height

Width

0.5 inch

Length

8.94 inch bottom of fingers to
top of handle, extended

Etch

8 mil multilayer

1-7

User Options

Default (All Switches Off)

Starting address

Starting address = 0

CSR address

CSR = 0 (17772100)

System size

Q22

8 kW boundaries

(1 of 16)
Q18 or Q22

New Technologies

Drams

256K dynamic RAMs

Advanced Schottky TTL

F series (fast) logic

Gate arrays

Battery Backup

5 VCC for bus support logic

5 VBB for MOS RAMs and refresh

Refresh

14.0 us + 5%

Interval between refresh cycles

(guarantees accessing all
128 rows in 2 ms or 256 rows
in 4 ms)
Error Correction Code
Detects single and double-bit
errors and corrects single-bit
errors

1.4.2

Environmental Specifications

Temperature

—40 to +66 degrees Celsius

Storage Temperature Range

Before operating a module which is at a temperature beyond the operating range, that module must first
be brought to an environment within the operating range and then must be allowed to stabilize for a
minimum of five minutes.

Operating Temperature Range

+5 to +60 degrees Celsius

De-rate the maximum operating temperature by one degree Celsius for each 1000 feet of altitude above
8000 feet.

Relative Humidity

Storage

10 to 90%, noncondensing

Operating

10 to 90%, noncondensing

1-8

Operating Airflow
When the inlet temperature is +60 degrees Celsius, adequate airflow must be provided to limit the inlet to
outlet temperature rise across the module to 5 degrees Celsius. For operation below +55 degrees Celsius,
airflow must be provided to limit the inlet to outlet temperature rise across the module to 10 degrees
Celsius maximum.
Altitude

Storage
The module will not be mechanically or electrically damaged at altitudes up to 50,000 feet (90
MM mercury).

Operating
:
Up to 50,000 feet (90 MM mercury).

NOTE: De-rate the maximum operating temperature by one degree Celsius for each 1000 feet of
altitude above 8000 feet.
1.4.3

Electrical Specifications

1.4.3.1 Power Supply Requirements — The module operates on +5 V only, with provisions made for
operating in a battery backup mode for long term data retention.
Current, Amps
MSV11-JB, JD

Standby

Active

ECC Init

Typ

Max

Typ

Max

Typ

Max

+5 V only

0.5

0.56

0.5

0.57

0.5

0.57

+5 V BBU

0.8

1.41

1.0

3.37

1.0

2.54

+5 V Total

1.3

1.97

1.5

3.94

1.5

3.11

Current, Amps
MSV11-JC, JE

Standby

Active

ECC Init

Typ

Max

Typ

Max

Typ

Max

+5 V only

0.5

0.56

0.5

0.57

0.5

0.57

+5 V BBU

1.0

1.72

1.2

3.72

1.25

4.00

+5 V Total

1.5

2.28

1.7

4.29

1.75

4.57

The 5 VCC and 5 VBB power supplies must not exceed the range minus 1.0 V to plus 7.0 V to avoid
permanent stress damage to the MOS RAMs. Operating voltage range is 5 V + 5 percent.

Interface Specifications

1.4.4

1.4.4.1 P-Bus Interface — The memory communicates with the KDJ11-B processor via an enhanced
protocol (p-protocol). Essentially, reads are two word transfers which take advantage of the KDJ11-B
restart overhead to load a second 16-bit word into the cache on the CPU module. Write operations are
initiated just after addresses are valid.

1.4.4.2 Q-Bus Interface — In addition to the p-protocol, the memory is compatible with the LSI-11 bus

(Q-bus). All signals are one bus load.

NOTE:

MSVII-JB and MSV11-JC cannot perform Q-Bus protocol.

1.4.4.3

Signal AC/DC Loading -

(1 acload= 9.35pF)

2.5 ac loads

(1 dc load = 105 uA nominal)

0.5 dcloads

1.4.5

Performance Specifications

This paragraph lists the access and cycle times for the P-bus and for the Q-bus.
NOTES:

1. Memory performance is the time measured from the output of the bus receivers to the input of the
bus drivers.

2. This assumes PWTSTB occurs within 145 ns of PBCYC. Longer time to PWTSTB extends cycle
time an equivalent amount of time.

3. Correction of single errors extend the access time of PMI DATI or DATBI cycles by 116 ns
maximum.

4. R PBCYC to T PRD STB trailing edge.

T PRD STB trailing edge to second word valid.

6. R PBCYC to memory BUSY

de-asserted.

7. T PRD STB trailing edge to next T PRD STB trailing edge with minimum PBLK response from
bus master (240 ns).

R DAL (address) valid to T PSSEL.

9. R SYNC to TRPLY with minimum time from R
10.

SYNC to RDIN/RDOUT (25 ns/50 ns).

R SYNC to memory BUSY de-asserted.

11. DATO (B) cycles assume 50 ns from R SYNC to RDOUT.

12. The first transfer in a DATBI is the same as a DATI. Subsequent word access times are measured

from R DIN de-asserted to TRPLY asserted with minimum bus timing (i.e., TRPLY negated to
RDIN asserted = 150 ns). DATBI access time alternates between these two values due to the two
word read architecture of the memory. Even word accesses (as determined by DAL 01) have a

longer access and cycle time. Subsequent odd transfers realize the faster access and cycle time.

13.

Minimum bus timing from T RPLY de-asserted to R DOUT asserted.

1-10

14.

R PBCYC to memory BUSY

de-asserted after 8 double-word transfers (16 words transferred)

assuming minimum P BLK response from master (240 ns).

15.

R QSYNC to memory BUSY
DIN bus master timing.

de-asserted after 16 word transfers assuming minimum TRPLY, R

Refresh
All access and cycle times are extended whenever a refresh conflict

occurs.

Refresh Cycle Time

Maximum (ns)

Single refresh request*

538

Double refresh request*

1006

Refresh priority+

1483

Refresh demandi

1483

1.4.5.1

P-Protocol Access and Cycle Times (Al MSV11-J

Variations)

Memory Performance (1)
Access Time (ns)

Cycle Time (ns) (6)

Min

Typ

Max

DATI (3) Ist word

390

(no error)
2nd word
DATBI (3)

417

444

35
518

58
531

DATO

DATOB (3)

Min

Typ

Max

(4)

538 .

568

597

80
545

(5)
N

3794

4166

—
4539

(14)

(8)

538

568

597

(2)

(8)

746

788

829

(2)

DATI CSR access

390

417

444

538

568

597

DATO CSR access

(8)

538

568

597

Refresh requests are added to the end of a bus memory cycle. The

next bus memory cycle is postponed

until this refresh cycle is completed. Double refresh is
not valid on MSV
| 1-JB and MSV11-

JC.

Refresh priority cycles precede a memory cycle and

Refresh demand cycles are self-initiated and may delay memory
access and cycle times up to this
length of time.

delay access and cycle times.

1.4.5.2 Q-Protocol Access and Cycle Times (MSV11-JD and MSV11-JE Variations Only)
Memory Performance (1)

Cycle Time (ns) (10)

Access Time (ns)
Min

Typ

Max

269

327

386

Even

268

324

381

Odd

212

269

325

DATO (11)

135

182

DATBO (11) (13)

135

182

DATOB (11)

135

182

DATIO (13)

269

327

DATIOB (13)

269

DATI CSR access

DATI
DATBI

Min

Typ

Max

556

605

654

(12)

7261

8032

8802

606

655

704

9423

9805

10187

772

850

929

384

1208

1333

1457

327

384

1415

1553

1691

269

327

386

556

605

654

135

182

606

655

704

DATO CSR

Access (11)

(15)

CHAPTER 2
DATA FLOW

2.1 INTRODUCTION
This chapter describes the basic data flow for read, write, and write byte cycles. Other bus cycle types are
basically combinations of these. For example, block mode read cycles are similar to a succession of read
cycles.
Each bus cycle contains an address portion and data transfer portion. The address portion of the various
bus cycle types are similar in that the processor is addressing the slave device. The data transfer portion of
each bus cycle type differs since the data flows in different directions for different cycle types. For
example, a read cycle transfers data from memory to the processor while a write cycle transfers data from
the processor to memory.

2.2 ADDRESS PORTION OF BUS CYCLE
Figure 2-1 shows the address flow portion of the bus cycle. In the PMI bus protocol, if the address
specified by the processor is within the address of the memory, the memory responds with a control signal
to indicate that it has been selected.
In the Q-bus protocol, if the address specified by the processor is within the address range of the memory,
the memory executes the requested cycle.
|
The address portion of the bus cycle is initiated when the processor places a 22-bit address on the bus. The
address is received and compared with the memory’s starting address to determine if the addressed
location resides on that memory board. Nine of the address bits specify the row address and nine specify
the column address.

After the row address becomes stable, row address strobe (RAS) is asserted.
The address gate array then switches from row address to column address. After the column address
becomes stable, column address strobe (CAS) is asserted. Note that the nine address lines at the output of
the address gate array are multiplexed and supply the row address followed by the column address.
The RAMs have multiplexed address inputs. Eighteen address bits (9 row address and 9 column address
bits) are required to supply a unique address for each memory location.
There are 22 RAMs in each data word (88 RAM:s on a fully populated board). There is onc RAM for cach
bit of the 16-bit data word and one for each of the 6 check bits.
Each set of 22 RAM chips makes up a block of memory. A fully populated board has 4 blocks or a total of
88 RAM chips (see Figure 1-4).

BUFFER
PM1

CONTROL

ADDRESS
GATE

ARRAY

CONTROL

|*+——

RAM DRIVER

9 ROW/COLUMN ADDRESS LINES

TM pee2t

[

aBUS

RAM DRIVER

TM CONTROL

CONTROL |e—— RCVR/
TRANS
QBUS

rasl. _ _
cashk

—

WR T ~—

2965

1 | I

ADDRESS

LAR

DATA

CAS

AND
‘

DCO021

RCVR/

TRANS

RAS

ADR

DATA

BLOCKO

D! |

TT1

1 11

ll I

179 ¢

GATE

CHECK BITS

1
TT 1

Ras

ADR

DATA

CAS

ADR

BLOCK
0

— DO
1

ARRAY

DATA

RAS

CAS

BLOCK 1

RAS

ADR

CHECK BITS

CAS

BLOCK 1

SHR.0253-84

Figure 2-1

Address Flow (Read, Write, Write Byte)

The row and column address bits specify the same address in all blocks. Therefore, two additional bits are
required to uniquely define one of the blocks. One bit (BDAL1) defines odd/even word selection for a read
or write cycle. In other words, BDALI selects the left (even) block or the right (odd) block (Figure 1-4).
The second bit is BDAL20 which selects the upper block or the lower block.
For a write cycle, the processor must specify which block the word is to be written to. This is accomplished
by BDAL1 and BDAL20.

2.3 DATA TRANSFER PORTION OF BUS CYCLE
The following paragraphs describe the data transfer portion of the read cycle, write cycle, and write byte
rala

CyCiC I 1erms Or

ata

Fla

Gaiad 1iow,

ADDRESS

GATE
ARRAY

BUFFER

CONTROL [*——

—

PMI

RAM DRIVER

CONTROL

QBUS
)
CONTROL | .

DCO021
RCVR/

QBUS

TRANS

‘

RAS |- —

DAL 16-21

8 ROW/COLUMN ADDRESS LINES

RAM DRIVER
o0

CONTROL

2965

CAS-I~ =~ ]T

WR
ADDRESS

_—— - —

1
1ER

-==a]

ted

AND
DATA

122

RAS
CAS

ADR
BLOCKO

RAS
CAS

DATA

TT1T

GATE

ARRAY

RAS
CAS

VAN ¥

11¢
WR

CHECK BITS

DATA

TTT

ADR
BLOCK O

RAS
CAS

ADR

K1X]
ADR
BLOCK 1

DATA

BLOCK 1

CHECK BITS
DI

SHR.0257-84

Figure 2-2

Read Cycle Data Flow

2.3.1 Read Data Transfer (Figure 2-2)
Read cycles are executed as two-word reads from two different locations — one word from block 0 and one
word from block 1.
When CAS goes low, the RAM output drivers are turned on. After data becomes valid, the two 22-bit
words are transferred to the data gate array and latched in this array under control of the address gate
array.

For a Q-bus read cycle, the processor specifies which word is to be transferred. For a PMI-bus read cycle,
the processor specifies which word is transferred to the bus first. This is accomplished by BDALI.

If Q-bus protocol is used, only one word is placed on the bus. BDAL1 selects the word to be placed on the
bus. If an error occurs in the first word, the error is corrected and no loss in access time occurs.
If PMI protocol is used, both words are placed on the bus serially. BDALI selects the word to be placed on

the bus first. If an error occurs in the first word of the two-word read, the data is stalled while the error
correction takes place. If an error occurs in the second word instead of the first word, the error is corrected
with no loss of cycle time.
2-3

2.3.2

Write Data Transfer (Figure 2-3)

Write cycles are single-word writes to RAM. The processor places a 16-bit data word on the bus thus
initiating the data transfer portion of this bus cycle. The data is received by two DCO21 transceivers and
then the data gate array. The data gate array generates 6 check bits from the 16-bit data word. The
address gate array determines which block of memory is written and asserts the write signal. The 22-bit
word is then written in the appropriate block.

The state of BDALI determines in which block of memory the word is written. If BDAL1=0, the word is
written in block 0 and if BDAL1=1, the word is written in block 1.

ADDRESS
GATE
ARRAY
BUFFER

PMI

CONTROL

QBuUS
CONTROL
QBUS

CONTROL

RAM DRIVER

2965

bco21
RCVR/
TRANS

RAM DRIVER

CONTROL
RAS

DAL 16-21

CAS
WR

9 ROW/COLUMN ADDRESS LINES

2965

-4

ADDRESS
AND

DATA

RAS
CAS

ADR
BLOCK
O

DATA

ADR
BLOCK 0

CHECK BITS

i1l

TT1
111

19¢
DATA

RAS

ADR

CAS

BLOCK 1

GATE

DATA

BLOCK 1

CHECK BITS
DI

SHR-0268-84

Figure 2-3

Write Cycle Data Flow

2-4

2.3.3 Write Byte (Figure 2-4)
The write byte data transfer is actually a read-modify-write to the RAMs. In ECC memory, the check bits

are encoded on a 16-bit word basis. Therefore, it is necessary to read the whole word (16 data bits plus 6

check bits) from memory. The word is transferred to the data gate array and checked for errors. If there is
a single-bit error, it is corrected.
The processor places a 16-bit word {iwo bytes) on the Q-bus. One of the two bytes is the byte to be written

to memory. This byte is combined in the data gate array with the appropriate byte from memory and a
new 16-bit word is formed.

Check bits are calculated on the new 16-bit word resulting in a 22-bit data word. The 22-bit word is then
written back to memory.

ADDRESS

GATE
ARRAY

BUFFER
PMI

CONTROL

RAM DRIVER
:

QBUS

DC021

CONTROL |QBUS

RCVR/
TRANS

CONTROL

DAL 16-21

]

2965]

9 ROW/COLUMN ADDRESS LINES

RAM DRIVER

RASI- — —
CASI
— 7

2965

ADDRESS

n
[

- - ZZAo

1ty \/

AND

RAS

DATA

A |

ADR

RAS

CAS

BLOCK
0

CAS

DATA

DCo21

or|

N/
_

ADR

BLOCK
0
CHECK BITS

TTT

r
I

RAS

ADR

RAS

CAS

BLOCK
1

CAS

DATA

ADR

BLOCK
1

CHECK BITS

READ

D
r
(7
—

SHR.0270-84

Figure 2-4

Write Byte Cycle Data Flow

2-5

Figure 2-5 shows how the write byte operation is performed. The figure assumes the low byte is to be
modified. The low byte from the bus is combined in the data gate array with the high byte from memory
and a new 16-bit data word is formed. BDALO determines the appropriate byte from the bus and the
appropriate byte from memory.

If BDALO=0, the high byte from memory is combined with the low byte from the bus. If BDALO=1, the
Jow byte from memory is combined with the high byte from the bus.

]«

RANDOM ACCESS MEMORY (RAM)

o
22 BITS

DATA GATE ARRAY

CHECK FOR
ERROR AND

CORRECT
ERROR

8 BITS

BDAL®

HIGH BYTE ___L

LOW BYTE ml

°o

huen

BDAL@=@

NEW 16 BIT
ILOW
BYTE | DATAWORD
BYTE

T
8 BITS

8 BITS
<

W BYTE

!
CHECK BIT

GENERATION

LOWB

NEW 22 BIT

(6 BITS)

WORD

s0ALH§

HIGH BYTE

16 BITS

Q-BUS

*IF BDALO=1, LOW BYTE
FROM RAM IS COMBINED
WITH HI BYTE FROM BUS

Figure 2-5

SHRA.0272-84

Byte Selection for Write Byte Operation

2-6

CHAPTER 3

MEMORY CYCLES

3.1 INTRODUCTION
This chapter describes the following types of MSV11-J memory cycles.

Q-bus (MSV11-JD and MSV11-JE only)
PMI bus
Refresh
ECC initialization (ECC INIT)
Bus cycles are categorized as read, write word, write byte, block mode read,
block mode write, readmodify-write, and read-modify-write byte cycles.
Refresh and ECC INIT cycles are internal to the
memory. The following paragraphs in this chapter
provide additional detail on bus cycles and interna
l cycles.

3.2 BUS CYCLES
This paragraph describes the basic differences betwee
n the Q-bus and PMI bus protocols for the various
cycle types.
3.2.1 Read Cycles
Read cycles may be memory read cycles where data
is read from RAM, or CSR read cycles where data
is
read from CSR.

3.2.1.1 Memory Read Cycle - Memory read cycles are
two-word reads from RAM. Each word consists
of 16 data bits plus 6 check bits.
For Q-bus memory read cycles, two data words are latched
into the data gate array. However, only one
word is placed on the Q-bus.
For PMI bus memory read cycles, two data words are
latched into the data gate array and both words are
placed on the bus. Either word may be selected to
be placed on the bus first. If the odd word is placed
on
the bus first, it is followed by the preceding even word.
For example, if a word at address 17362 is selected
to be placed on the bus first, the next word transfe
rred will be from address 17360. If the even word
is
selected to be placed on the bus first, the next odd
word is then transferred second. For example, if a
word
at address 17360 is selected to be placed on the
bus first, the next word transferred will be at
address
17362.
3.2.1.2 CSR Read Cycles ~ CSR read cycles on
the Q-bus and PMI bus are single-word read cycles.
No
error detection/correction occurs for
CSR data.

3-1

Write Word Cycles

3.2.2

Write word cycles may be memory write word cycles where data is written in RAM or CSR write word
cycles where data is written in the CSR.

3.2.2.1

Memory Write Word Cycles - Memory write word cycles are single-word cycles. After memory

receives the data word it generates 6 check bits. The 22 bits are then written to memory.

3.2.2.2 CSR Write Word Cycles - CSR write word cycles on the Q-bus and PMI bus are single write
word cycles. Check bits are not generated for CSR write word cycles.
Write Byte Cycle

3.2.3

Q-bus and PMI bus write byte cycles are similar. The check bits for each cycle type are generated by
memory on the basis of a 16-bit word. The write byte cycle is executed as a read cycie foliowed by a write
word cycle. The sequence of events is as follows.

The word containing the byte to be modified is read from memory and is latched in the data
gate array.

Error correction occurs if required.

The 16-bit data word on the bus containing the new byte is latched in the data gate array.

The new byte is combined with the old byte from the memory to form a new 16-bit data word.

New check bits are generated for this 16-bit word. |

The new 22-bit data word is written to RAM.

NOTE: A single-bit error is corrected if one occurs. If a double error occurs, the word cannot be
corrected and is written back to memory. No write byte cycle occurs. During subsequent reads of that
location, the errors are detected and reported back to the processor.
3.2.4

Block Mode Read Cycles

Q-bus block mode read cycles are successive 16-bit word transfers. Two 16-bit words are read from
memory and latched into the data gate array on read cycles. The address gate array takes advantage of
this fact during Q-bus block mode read cycles.

During Q-bus block mode transfer, the gate array accesses RAM and a two-word internal read occurs.
Both words are latched in the data gate array. Error correction is performed if there is an error. Either one

of the two words may be placed on the bus first.

If the processor requests an even word, the even word is placed on the bus. On the next cycle, the odd
word, which is already latched in the gate array, is placed on the bus. A second RAM access is not
necessary, in this case, as the odd word is already latched in the data gate array (Figure 3-1A).
For example, if the processor requests the data in address 17360, the data in address 17360 and 17362 is
latched into the data gate array and the data in address 17360 is placed on the bus. On the next bus cycle,
the data in address 17362 (which is latched in the data gate array) is placed on the bus (Figure 3-1A).
If the processor requests an odd word be placed on the bus, that word and the preceding word are latched
in the data gate array, and the odd word is placed on the bus. The even word is disregarded as addresses
are incremented for block mode read cycles. The next bus cycle causes two more words to be transferred
from RAM to the data gate array. The even word is placed on the bus. The odd word is transferred to the
bus during the next bus cycle.

3-2

RAM

1ST WORD TO BUS

17360

BLOCK 0

DATA

17362

GATE
ARRAY

2ND WORD TO BUS| @

BLOCK 1

(A) EVEN WORD REQUESTED (17360}

DATA FROM
17360
DISREGARDED

~saeq

;&%K o

|_17364
17362

gfg‘cx . | 17386

2ND WORD TO BUS
DATA
GATE

ARRAY

1.
>

|1ST WORD TOBUS | &

3RD WORD TO BUS

{B) ODD WORD REQUESTED (17362)

SHR:0254 84

Figure 3-1

Odd/Even Memory Request for Block Mode

For example, if the data in address 17362 is requested to be placed on the bus, the data
i address 17360 is
disregarded (Figure 3-1B). The next bus cycle causes the data in addresses 17364 and 17366 to be latched
in the data gate array. The data in 17364 is placed on the bus. The next cycle causes the data in 17366 to
be placed on the bus. Since the data in 17366 was already latched in the data gate array, a RAM access
for this data was not required.
PMI bus block mode read cycles always start on even word boundaries and consist of double-word
transfers. Two words are placed on the bus during each successive read cycle.

3.2.5 Block Mode Write Cycles
Q-bus block mode write cycles are a succession of single write word cycles to successive memory locations.
In the Q-bus write word cycle, there is overhead time between cycles. By using Q-bus block mode write
cycles, this overhead is minimized (i.e., no address required in protocol between successive writes).
There are no PMI bus block mode write cycles. In PMI bus write word cycles, the Processor can execute
the write word cycles very quickly. Therefore, it is not necessary to implement PMI bus block mode write
cycles.

3.2.6 Read-Modify-Write Cycle
Memory executes a Q-bus read-modify-write cycle as a read cycle followed by a write cycle to the same
location. Memory executes this single-bus cycle as two internal cycles.
There are no read-modify-write cycles in the PMI protocol. A read-modify-write cycle is executed as two
bus cycles - a read cycle followed by a separate write cycle to the same location.
3.2.7 Read-Modify-Write Byte Cycle
Memory executes the Q-bus read-modify-write byte as a read cycle followed by a write byte cycle to the
same location. Memory executes this single-bus cycle as two internal cycles.
There are no read-modify-write byte cycles in the PMI protocol. A read-modify-write byte cycle
is
executed as two bus cycles - a read cycle followed by a separate write byte cycle to the same location.

3-3

3.3

REFRESH CYCLE

Each memory cell slowly loses its charge so a refresh cycle is needed to restore the contents of memory.
Each row of memory must be refreshed every 4 msec.

Refresh is an asynchronous operation whose period is determined by an on-board oscillator. The refresh
logic is contained in the address gate array. The array also contains a refresh address counter which keeps
track of the rows that are refreshed.
3.4

ECC INIT CYCLE

The ECC INIT cycle is an internal cycle executed only during power up. Its purpose is to write known data
into all memory locations soon after power up. Memory writes zeroes in all cells and generates the check
bits associated with the cleared memory cells.

A memory location that has not been written to since power up contains unknown random data. If a write
byte cycle was performed at that location, an error would most likely occur. In this case, the word read
from memory is written back to memory and the write byte cycle aborts. No error indication is flagged.
Subsequent read cycles at that same location inform the processor of the error condition.
ECC INIT eliminates the error condition for write byte cycles by clearing the memory cells of invalid
data.

For systems without battery backup, ECC INIT occurs when +5 V appears during power up. For systems
with battery backup, ECC INIT occurs when the battery backup voltage (+5 VBB) occurs. When +5 V
reappears on battery backup systems, ECC INIT is not executed since the data is valid and was not lost.

3-4

CHAPTER 4

CONFIGURATION AND CSR OPERATION

4.1 INTRODUCTION
This chapter describes the module installation, control and status register (CSR) operation, operating
modes, and error reporting log.

The module installation description includes switch and jumper configurations, memory addressing, CSR
addressing, and backplane placements.
The CSR description includes CSR bit format, and descriptions of each bit.

The description of operating modes includes normal modes of operation and various diagnostic modes.
The error reporting description includes error logging performed during PMI bus and Q-bus cycles for
single-bit and double-bit errors. From a module viewpoint, errors occurring during read and write byte
cycles are latched in the CSR. From the system viewpoint, only uncorrectable errors occurring during read
cycles are reported to the central processor. Errors during write byte cycles are not reported.
4.2 MODULE INSTALLATION
Before you remove or replace an MSV11-J memory module, exercise the following cautions.
CAUTION: Static charges can damage the MOS memory chips. Be careful how you handle the
module and where you lay it down.
When you install or remove the memory module, make sure there is no dc voltage applied to the
module.
If the green LED is on, the module is receiving +5 V from the power supply or battery backup. The power
source must be off before you remove or replace a memory module.
4.2.1 Jumper Configurations and Switch Settings
The MSV11-J has jumpers installed at the factory to establish the configuration of the module.

The MSV11-J contains two switchpacks — one is an 8-switch DIP (dual in-line package) and one is a 4switch DIP. The 8-switch DIP selects the starting memory address on an 8Kword boundary. The 4-switch
DIP selects the CSR starting address. One of 16 possible CSR addresses may be selected.

4.2.1.1

Jumper Installation — The following chart summarizes the MSV11-J jumpers (see Figure 4-1).

Jumper

Description

W1 Out

256K dynamic RAMs

W2 In
W2 Out

Half populated module
Fully populated module

W5, W6 mounted

Battery backup system

horizontally

(see Figure 4-2)
W3, W4 mounted

+5 V system

vertically

(see Figure 4-3)

NOTE: PDP-11/84 systems are available in a battery backup configuration. In these systems, +5 V
BBU is bussed to the +5 V pins in the two slots reserved for the MSV11-J. These memories must NOT
be changed to the battery backup configuration.

CSR ADDRESS _~

SWITCH {SP2)

TEST

CONNECTOR

MEMORY
ADDRESS

SWITCH (SP1)

DATA
GATE
ARRAY

ADDRESS
GATE
ARRAY

SHR-0269-84

Figure 4-1

MSV11-J Jumpers

W6}— BATTERY
BACK UP
SYSTEM

MSV11-J MODULE
CONNECTOR D

—’_l
CONNECTOR C

SHR-0265-84

Battery Backup Jumper Connection

Figure 4-2

+5V
SYSTEM

MSV11-J MODULE

CONNECTOR D

CONNECTOR €

SHRA-0266-84

Figure 4-3

+5 V Jumper Connections

4.2.1.2 Memory Address Switch Settings — The memory address switch settings are shown in Table 4-1.
The table is divided into 3 columns - the decimal switch settings. in 8Kword increments, the octal
equivalent, and the actual switch settings shown in binary. The memory-address switch (SP1 in Figure 4-1)
is an 8-switch DIP (dual in-line package). The least four significant switch settings (5 through 8) of the
memory address switch (SP1) represent 8Kword increments as shown in the upper half of the table. For
example, if these switch settings (5 through 8) are Os, a memory address of 0 is represented (assuming
switches 1 through 4 are also 0). If switch setting 8 is a 1 (all others being 0Os), the memory address is
incremented by 8Kwords. If switch setting 7 is a 1, with all other switch settings set to 0, the memory
address is incremented by another 8Kwords. The upper half of the table shows the effect of switch settings
5 through 8. Note that switch settings 1 through 4 are all Os in the upper half of the table and do not come
into play until 128 Kwords are reached.

The lower half of the table represents increments of 128K until 2 M is reached. Note that switch settings 4
through 1 come into play here. Each increment of these switch settings represents an increase of 128K.
For example, if switch setting 4 is a 1 and switch settings 3 through 1 are Os, a starting address range of
128K to 248K is selected. The specific memory starting address selected within that range is determined
by switch settings 8 through 5 (indicated by Xs in the lower half of the table).

Table 4-1

Starting Memory Address Selection

Decimal (Kwords)

Octal

Switch Setting (SP1)

12345678

00000000

00040000

00000001

16
24
32
40
48
56
64
72

00100000
00140000
00200000
00240000
00300000
00340000
00400000
00440000

00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001

80
88
96

00500000
00540000
00600000

00001010
00001011
00001100

104

00640000

00001101

112
120

00700000
00740000

00001110
00001111

000-120
128-248
256-376
384-504
512-632
640-760
768-888
896-1016
1024-1144
1152-1272
1280-1400

00000000-00740000
01000000-01740000
02000000-02740000
03000000-03740000
04000000-04740000
05000000-05740000
06000000-06740000
07000000-07740000
10000000-10740000
11000000-11740000
12000000-12740000

0000 X XXX
0001 X XXX

1408-1528

13000000-13740000

1536-1656
1664-1784
1792-1912

15000000-15740000
16000000-16740000

1920-2040

1101 XX XX
1110XXXX

17000000-17740000

1111 XXXX

14000000-14740000

NOTE:
I = Switch on
0 = Switch off
X = Switch can be either
on or off

001 0X XXX
0011 XXXX
0100X XXX

0101 XXXX
0110X XXX

0111 XXXX
1000X XXX
1001 XXXX

101 0X XXX
1011 XXXX
1100X XXX

Several examples are provided below to help you understand the table.
Example 1 - Desired starting memory address = 144K

Switch

1234
0001

Selects 128K-248K range
(see lower half of Table 4-1)
144K
—128K
16K

5678
0010

represents 16K
(see upper half of Table 4-1)

Starting memory address of 144K = switch
settings of:
Switch

Setting

12345678

00010010

Example 2 - Desired starting memory address = 1.576 M

Switch

1234
1100

Selects 1536K to 1656K range
(see lower half of Table 4-1)
1576K
—1536K
40K

TENVAM

5678
0101

represents 40K
(see upper half of Table 4-1)

Starting memory address of 1.576 M
= switch settings of:

Switch
Setting

12345678
11000101

4.2.1.3 CSR Address Switch Settings — The CSR address switch (Figure 4-1) is a 4-switch DIP (dual inline package) which allows selection of one of 16 CSR addresses. Table 4-2 shows the possible CSR

addresses for 18-bit and 22-bit systems. The switch setting for a particular CSR address is the same
whether the CSR is in an 18-bit or 22-bit system. For example, the switch setting is 1110 for a 22-bit CSR
address of 17772134 or an 18-bit CSR address of 772134.

4-5

Table 4-2

CSR Address Selection

22-Bit CSR
Address

18-Bit CSR
Address

17772100
17772102
17772104
17772106
17772110
17772112
17772114

772100
772102
772104
772106
772110
772112
772114

17772116
17772120
17772122
17772124
17772126
17772130
17772132
17772134
17772136

Switch

Setting
1234
0000
0001
0010
0011
0100
0101
0110

0111
1000
1001
1010
1011
1100
1101
1110
1111

772116
772120
772122
772124
772126
772130
772132
772134
772136

NOTE:
1 = Switch on

0 = Switch off

4.2.2

Backplane Placements

The PDP-11/83 and PDP-11/84 system backplanes are designed for the MSV11-J memory which
incorporate Q-bus and PMI-bus protocols. The MSV11-JB and MSV11-JC memory variations can only be
used in PDP-11/84 systems. The MSV11-JD and MSV11-JE variations can be used in PDP-11/84 or
PDP-11/83 systems.

As a cross-product, the MSV11-J memory can be installed in a Q-CD backplane. However, you must not

install an option in a slot adjacent to the MSV11-J that uses pins in the CD connector. Instead, leave an
empty slot between the MSV11-J and this option. An option which does not use pins in the CD connector
may be placed adjacent to the MSV11-J.

NOTE: Do not install the MSV11-J in a Q-Q backplane since this backplane shorts Q-bus signals to
PMI bus signals and the system will not operate. This can also result in damage to the MSV11-J and
other modules in a Q-Q backplane.

The location of the MSV11-J memories in a PDP-11/83 system determine the protocol to be usod between

memory and CPU. For PMI protocol, the MSV11-Js must be located immediately in front (lower slot
number) of the CPU; otherwise the memory and CPU will communicate with the Q-bus protocol.

Table 4-3 shows the backplane pin assignments. Connectors A through D are shown across the top and pin

numbers A through V (excluding G, I, O, and Q) are listed down the side. Backplane pins are designated
first by slot, then by pin number, and then by the side of the module. A typical example is shown below.
C

Connector (A through D)

Pin (A through V except G, I, O, and Q)
Side (side 1 = component side,
side 2 = solder side)
4-6

Table 4-3

Backplane Pin Utilization

Connector A
Side 1
Side 2

BDALI6

GND

E
F
H
J
K
L
M
N

GND
REFKILL

BDOUT
BRPLY
BDIN
BSYNC
BWTBT

BREF

BDMGI

T
U
V

GND

BINIT
BDALO
BDAL1

BDALI17

GND

BIAKI
BIAKO

Connector B
Side 1
Side 2

Connector C
Side 1
Side 2

Connector D
Side 1
Side 2

BDCOK

S RUN

PSSEL

PBYT

PWTSTB

BDALI8

GND

S RUN

GND

PBYT

GND

BDAL20
BDAL21

BDAL2
BDAL3
BDAL4
BDALS
BDAL6
BDAL7
BDALS8
BDAL9

PBCYC
PUBSYS
PHBPAR
PSBFUL
PLBPAR

PRDSTB

BDAL1I0

PBLKM

BDAL11

PBSY

BBSY

BDAL13
BDAL14
BDAL15

GND

GND
5VBBU
S5VBBU

5VBBU
5VBBU

BPOK

BDALI19

GND

BBS7

SVBBU

BDMGO

BDALI12
GND
5V

PUBMEM

PUBTMO

PUBMEM

PUBTMO

PMAPE

NOTES:
1.
CAl is connected to CCl on the module
2.
DAI is connected to DCI on the module
3.
All PMI signals except PBYT have the connectors on side 1 etched to the respective signal on side
2 of the module
4.
AM?2 is connected to AN2 on the module
5.
ARZ is connecied io ASZ on ihe module
6.
Side | is component side
7.
Side 2 is back side

4.3 CONTROL AND STATUS REGISTER (CSR)
The control and status register in the MSV11-J allows program control of certain ECC functions and
contains diagnostic information if an error has occurred. The CSR is a 16-bit register and has an assigned
address - it can be accessed via the Q-bus, or PMI protocol.

There is one CSR per memory module. Each CSR can be assigned to one of 16 predetermined addresses
which range from 772100 to 772136 for 18-bit systems and from 17772100 to 17772136 for 22-bit
systems (refer to Table 4-2).
ECC is performed only on memory accesses and is not used when accessing the CSR.
4.3.1
Bit Format of CSR
Figure 4-4 shows the bit assignments of the CSR. Unused bits are read as 0.
4.3.2
Bit Descriptions of CSR
Table 4-4 describes each of the CSR bits shown in Figure 4-4.

——

UNCORRECTABLE]

SET

INDICATION

MODE

ERROR

SINGLE

INHIBIT

MULTI-FUNCTION REGISTER

ERROR

|[DIAGNOSTIC

|CHECK

INDICATION | MODE

EXTENDED

RESERVED

INHIBIT

igg?aZSS

(0)

MODE

RETRIEVAL

POINTER

DISABLE

CORRECTION
MODE
UNCORRECTABLE
ERROR
INDICATION
ENABLE

SHR-0255.84

Figure 4-4

Table 4-4

CSR Bit Assignments

CSR Bit Descriptions
Set By

Bit

Name

Cleared By

Remarks

Uncorrectable

Set/cleared by

Does not affect CSR. BDALI17 is
driven directly by CSR0O at same
time as data during a DATI(O)
cycle. BDALI16 is not affected by
CSRO00.

error
indication
enable
read/write

software
Cleared by power
up and BUS INIT

CSR00=0 Inhibit Error Indication
Will not allow a system parity
(uncorrectable error) trap; i.e.,
BDAL17 is not asserted with data
on DATI(O) cycles during
uncorrectable error detection.
CSRO04 and CSR135 still indicates
errors. BDAL16 is asserted with
data on DATI(O) cycle when an
uncorrectable error occurs.

CSRO00=1 Active Error Indication
This bit causes assertion of
BDAL17 with data during all
DATI(O) cycles.

Table 4-4

CSR Bit Descriptions (Cont)

Bit

Name

Disable
correction

mode
read/write

Set By

Cleared By

Remarks

Set/cleared by
software

Serves as a diagnostic aid to allow
reading data from memory without

Cleared by power
up and BUS INIT

interference from the error
correction iogic.

CSRO1=0 Enable Error Correction
Single error sets CSR04 and latches
error address and syndrome bits.
Double error sets CSR15 and latches
error address and syndrome bits.
Once a double error is detected, a
single error is flagged through
CSRO04, but does not cause the address
and syndrome bits to be overwritten.

CSRO1=1 Disable Error Correction
Single error is uncorrectable, and
sets CSR04 and CSR15. Double error
sets CSR15 only. Priority of single
and double error address and
syndrome bit latch are the same.

Diagnostic
check mode
read/write

Set/cleared by
software
Cleared by power
up and BUS INIT

This mode allows the forcing of a
single or double error in a desired
location. Also provides a means of
examining the check bits and
syndrome bits in a given location.
The check bits for a given 16 bit
data pattern are written into bits
5 through 10 of the CSR. Subsequent
DATO or DATOB cycles write the check
bits from the CSR to the MOS array
in diagnostic mode (CSR2 set).

During DATI or DATIO cycles check
bits from memory are latched into
the CSR.
In the diagnostic mode, CSR04 and
CSR15 react to single and double
errors; address and syndrome bits
are not logged. Single-bit errors
are corrected on DATI and DATOB
cycles.

CSR2=0 Normal Operation

CSR2=1 Diagnostic Mode
Next DATI stores RAM array check bits
into CSRO5 through CSR10. Next DATO
writes CSRO5 through CSR10 into RAM
array check bits.

Table 4-4

CSR Bit Descriptions (Cont)
Set By

Bit
03

Name

Cleared By

Remarks

Inhibit mode

Set/cleared by

This bit works in conjunction with

pointer
read/write

software
Cleared by power

set inhibit mode (CSR13). If
CSR13=1 and CSR03=0, the first

up and BUS INIT

block (0 to 16Kwords) of memory

cannot operate in ECC disable mode or

diagnostic check mode. If CSR13=1
and CSR03=1, the second block
(16Kwords to 32Kwords) of memory
cannot operate in these modes.

Therefore CSRO03, in conjunction
with CSR13, allows a 16K block of
memory to always have ECC coverage
(protected). The system diagnostic
can therefore reside in this
protected portion of memory and can
disable ECC and/or run the Diagnostic
Check Mode in the rest of memory
without itself becoming vulnerable
to single errors.
NOTE:
A memory resident diagnostic
must always be protected. If not protected
Sfrom the diagnostic check mode or the
disable correction mode, a memory resident diagnostic produces errors.

If CSR13=0
CSRO03 is inoperative
If CSR13=1
CSRO03 is operative

CSR03=0
CSR03=1
04

Single

Set by a single

error

bit error

read/write

Set/cleared by
software
Cleared by power
up and BUS INIT

0-16 kW ECC protect
16 kW-32 kW ECC protect

Set upon detection of a single
error if: CSR0O1=0
or

CSRO1=1, AND CSR13=1 AND CSRO03
is protecting an accessed word.
CSR4=0 No single errors detected
CSR4=1 Single error detected

Multifunction

Set by software

read/write

NOT cleared by

These seven bits log check bits in
diagnostic mode or log multiplexed
address and syndrome bits in normal

power up or BUS
INIT

maode

S1ANINBW
.

4-10

Table 4-4

CSR Bit Descriptions (Cont)

Logging of Address, Syndrome, and Check Bits
After a failure, the address and syndrome bits are logged in the CSR. The address is recovered
in normal
mode (CSR2=0) and the syndrome bits are recovered in diagnostic mode (CSR2=1) as described
below.
i5

A17 | A6 | A15|

—V

L IowADDRESS —

A14 | A13}|

UNCORRECTABLE ERROR

o LSINGLE T—NORMAL

A12 | AT

MODE

ERROR

LOW ADDRESS

ERROR RETRIEVAL

*EITHER CSR4 OR CSR 15 IS SET TO 1 UPON DETECTION OF AN ERROR
SHR-0275-84

To recover address bits 11 through 17 (low address retrieval), CSR2 is set to 0, CSR14 is set to 0, either

CSR4 or CSR1S5 is set to 1, and CSRS through CSR11 contain A11 through A17 of the failed memory
address.

[

A0l | A21 | A20 | A19 | A18

EXTENDED ADDRESS

[

ERROR RETRIEVAL
=

EXTENDED

NORMAL

ADDRESS

UNCORRECTABLE ERROR

SINGLE ERROR

MODE

*EITHER CSR4 OR CSR 15 1S SET TO 1 UPON DETECTION OF AN ERROR
SHR-0276-8¢

To recover address bits A18 through A21 and A01 (extended address retrieval), CSR2 is set to 0, CSR 14
is set to a 1, and CSR bits 5 through 9 contain A18 through A21 and A1 of the failed memory address.

|SN8|sna|sSN2]SNT|SNO|SNX|

N
EXTENDED ADDRESS

SYNDROME

ERROR RETRIEVAL

BITS

0
|

T
DIAGNOSTIC

MODE

NOTE: TO LATCH LOW ADDRESS, EXTENDED ADDRESS, OR SYNDROME BITS, CSR2=0.

TO READ LOW ADDRESS OR EXTENDED ADDRESS, CSR2=0. TO READ SYNDROME
BITS, CSR2=1.
SHR.0277-84

During normal operation (CSR2=0), a single- or double-bit error causes the address and syndrome bits to
be latched in the CSR. To recover the syndrome bits, CSR? is set (diagnostic mode) and CSR 14 is set.
During a CSR read, CSROS through CSR
10 contain the previously latched syndrome bits (SnX, Sn0, Snl,
Sn2, Sn4, Sng).

4-11]

Table 4-4

CSR Bit Descriptions (Cont)

Logging of Address, Syndrome, and Check Bits

cB8 | CB4

8
cB2

cs1}

CBO

DIAGNOSTIC MODE—I

I— LOW ADDRESS

ERROR RETRIEVAL

SHR-0257-84

During DATI cycles, check bits from memory are written into CSRS through CSR10 regardless of any
errors at that memory location.

During DATO(B) cycles, contents of CSRS through CSR10 are written into check bits of that memory
location regardless of any errors at that location.
To recover the check bits, CSR2 is set (diagnostic mode) and CSR14 is cleared. CSR5 through CSR10
will contain the memory locations check bits after a DATI cycle. If a DATO(B) cycle is executed, CSRS
through CSR10 contain the check bits to be written to memory.

Set By

Bit

Name

Cleared By

Remarks

Reserved

Set inhibit

Set/cleared by

When this bit is cleared in

mode
read/write

software
Cleared by power

diagnostic mode (CSR2=1), it allows
the diagnostic check mode and/or

up and BUS INIT

ECC disable mode to operate
throughout the MSV11-J memory. When
this bit is set, it enables the
inhibit mode pointer to inhibit
either the first 16Kwords or second
16Kwords segment from entering
diagnostic mode or ECC disable mode.
CSR3 determines which 16Kwords is
protected from entering diagnostic
mode (CSR2=1) or ECC disable mode
(CSR1=1).
CSR 13=0 enable diagnostic check
mode and ECC disable mode
CSR13=1 inhibit diagnostic check
mode and ECC disable mode

Always read as 0

4-12

Table 4-4

Bit
14

CSR Bit Descriptions (Cont)

Name
Extended

error address
retrieval
read/write

Set By
Cleared By

Remarks

Set/cleared by
software

CSR 14=0 Retrieve Low Address
(A1l - A17)
CSR 14=1 Retrieve High Address
(A18 - A2l and AO1)

Cleared by power
up and BUS INIT

Multiplexes low address (A1l through
A17) and extended address (A 18
through A21 and A0I1) to CSRO5

through CSR11 in normal mode
(CSR2=0). If CSR14 is reset, a
CSR read presents A1l through A17

to CSROS through CSR11.
If CSR14 is set, a CSR read
presents A18 through A21 and AOQl
to CSRS5 through CSR9.
NOTE:
With CSRI14 on a 1, diagnostic
data may not be loaded into the CSR syndrome register.
15

Uncorrectable

Set by uncorrectable

error

read/write

Set/cleared by
software
Cleared by power
up and BUS INIT

Set if an uncorrectable error is
detected; i.e., two or more errors
with ECC enabled (CSR 1=0) or one or
more errors with ECC disabled

(CSR1=1).
CSR15=0 No uncorrectable error
detected
CSR15=1 Uncorrectable error
detected
CSR1=0

4-13

Two or more errors
CSR1=1
One or more errors

4.3.3

Operating Modes

The MSV11-J uses seven operating modes to control error logging and error reporting during memory bus
cycles.

These modes are shown in Table 4-5. The CSR bit settings for the seven modes are also shown. For
example, in normal mode, CSR1 is cleared (error correction enabled) and CSR2 is cleared (normal mode).
4.3.3.1

Normal Mode (ECC Enabled)

NORMAL MODE :f J
ENABLE ERROR CORRECTION
SHR-0261-84

The memory usually operates in normal mode. Single- and double-bit error status is recorded in CSR 04
and CSR 15, respectively. Error address and syndrome bits are stored in multifunction register bits CSR 5
through CSR 11. This paragraph describes the error conditions for the various cycle types in this mode.
They are listed below.
Read Cycle - Single Error
CSR 4 - single error is set.
CSR 15 (uncorrectable error indication) is unaffected.
Data is corrected by error detection logic before being placed on the bus.
If CSR 15 has not previously been set, A11 through A21, A01, and the error syndrome bits are
latched in the CSR.
If CSR 15 has been set, the address and syndrome bits are unaffected. (Single-bit error status
does not override previously latched double-error status.)

Read Cycle - Double Error
CSR 4 is unaffected.
CSR 15 is set.
Red LED is on.
All through A21, AO1, and the error syndrome bits are latched in the CSR. (Double-bit errors
override single-bit errors.)
®
Error asserts BDAL 16L (uncorrectable error) during the data portion of the read cycle.
Write Byte Cycle - Single Error During Read Portion
®
®
®
®
®
®

CSR 4 is set.
CSR 15 is unaffected.
If CSR 15 has not previously been set, A11 through A21, AO1 and the error syndrome bits are
latched in the CSR. If CSR bit 15 is set, the address and syndrome bits are unaffected.
The error in the data is corrected and is combined with the new byte.
Check bits are generated on the new 16-bit data word.
The new data word and new check bits are written to memory.

Write Byte Cycle - Double Error During Read Portion
®

(SR 15 is not set.

Address and syndrome bits are NOT logged.
Error is preserved by writing the old data and check bits back to memory. The new byte is lost.
Error will be detected on the next DATI cycle to that location.

®
®

Write Word Cycle

®
®
®

CSR 4 and CSR 15 are unaffected.
Check bits generated by ECC.
Data and check bits are written into memory.
4-14

Address and Syndrome Retrieval
Read CSR
1.
If CSR 14=0, then CSR 5 through 11 contains A1l through A17 of the failed address.
If CSR 14=1, then CSR 05 through 9 contains A18 through A21 and AO1 of the
failed address.
Write CSR
Change the state of CSR 14 to obtain the other half of the stored address.
If CSR 14 was 0, then change to 1.
If CSR 14 was 1, then change to 0.

Read CSR
CSR 05 through CSR 11 (or CSR 05 through CSR 09) contain the other half of
the address (see
step 1).
‘
Write CSR to diagnostic mode
Set CSR 02=1, CSR 14=1

Read CSR (diagnostic mode)
CSR 5 through CSR 10 contains the six syndrome bits.

Table 4-5

Operating Modes

Mode

CSR Bit Settings
15

Normal, ECC enabled
Normal, ECC disabled

Normal mode, ECC disabled, protected*

Diagnostic mode, ECC enabled
Diagnostic mode, ECC disabled
Diagnostic mode, ECC enabled, protected*
Diagnostic mode, ECC disabled, protected*
*

13 ..., 4

X
X
X
X
X

1
0
0
1
i

X
X
X

01
X

O
i

X
X 01
X
01

1
0
1

X
X
X

1
1

0
1

X
X

Protected mode refers to the first 16Kwords or second 16Kwords of memory which is protected
from entering diagnostic mode or ECC disable mode. The 16Kword area selected is accomplishe
d
via CSR bit 3. If this bit is 0, the first 16Kwords are protected and if the bit is a I, the
second
16Kwords are protected.

4.3.3.2

Normal Mode (ECC Disabled)

L CLEAR INHIBIT MODE

NORMAL MODE —T

DISABLE ERROR CORRECTION

SHR.0258-84

Normal mode with ECC disabled inhibits the correction of a single-bit error.
Generation of check bits is
not inhibited by this mode. All detected errors are considered uncorrect
able.

4-15

This mode is used to gain visibility of normally corrected single bit memory errors. The error conditions
for the various cycle types are listed below.
Read Cycle - Single Error

e
e

CSR 15 AND CSR 4 are set. Single error is uncorrectable.
Red LED is on.

All through A21, AO1, and syndrome bits are latched in the CSR.
BDAL 16 is asserted on the bus during the data portion of the read cycle.

Read Cycle - Double Error
CSR 15 is set, CSR 4 is unaffected.
Red LED is on.

All through A21, AO1 and error syndrome bits are latched in CSR.
Error asserts BDAL 16 during the data portion of the read cycle.
Write Byte Cycle - Single Error During Read Portion
CSR 15 AND CSR 4 are set. Single error is corrected.
Red LED is on.

Address and syndromes are latched in the CSR.
Data containing error is corrected, then combined with new byte.
Check bits are generated by the ECC on the new word.
New word and check bits are written into memory.

Write Byte Cycle — Double Error During Read
e

CSR 15is NOT set

Error is preserved by writing the old data and check bits back into memory. The new byte is

Address and syndromes are NOT latched in the CSR.

lost. Error is detected on the next DATI cycle to that location.

Write Word Cycle

Check bits are generated by ECC on the new word.
Data and check bits are written into memory.

Address and Syndrome Retrieval
1.

Read CSR

Write CSR, Change CSR 14
If CSR 14 was 0, then change to 1.
If CSR 14 was 1, then change to O.

If CSR 14=0, then CSR 05 through 11 contains A11 through A17 of the failed address.
If CSR 14=1, then CSR 05 through 09 contains A18 through A21 and AOQ1 of the failed address.

Read CSR

CSR 05 through 11 (CSR 05 through 09) contain the other half of the address (see step 1).
Write CSR (Enter Diagnostic Mode)
Set CSR 02=1, CSR 14=1.
Read CSR

CSR 05 through 10 contains syndrome bits.

4-16

4.3.3.3

Normal Protected Mode (ECC Disabled)

xPxtr

b xpxp

x|lon]

]

cse3-cPROTECTSCi6KkW

| T

CSR 3=1PROTECTS 16KW-32KW i

‘J

NORMAL MODE
SET INHIBIT MODE

DISABLE ERROR CORRECTION

SHR-0256-84

One of two 16 kW blocks may be protected from the ECC disable mode (CSR 01=1, CSR 13=1, CSR
03=0 to protect first 16K and CSR 01=1, CSR 13=1 and CSR 3=1 to protect second 16K of memory).

Single-bit errors are corrected as in the normal mode with ECC enabled. This feature provides protection
for the memory resident diagnostic.
The error conditions for the various cycle types in this mode are listed below.

Read Cycle - Single Error
®
CSR 4 and CSR 15 are NOT set.
®
Data is corrected by the ECC before being put on the bus.
®
Address and syndromes are NOT latched in the CSR.
Read Cycle - Double Error
®
CSR 15 is set.
®
Red LED is on.
®
Address and syndromes are latched in the CSR.
®
Error causes BDAL 16 to be asserted at the same time as (uncorrected) data.
Write Byte Cycle - Single Error During Read Portion
CSR 4 is NOT set.
Address and syndromes are NOT latched in CSR.
Old data is corrected and combined with new byte.
Check bits are generated by ECC on the new word.
Write Byte Cycle - Double Error During Read Portion
¢
CSR 15 is NOT set.
®
Address and syndromes are NOT latched in CSR.
®
Write byte is not executed, old data and check bits are written back into memory, preserving
error in that location.
®
New data is lost.
Write Word Cycle

®
¢

Check bits are generated by the ECC on the new memory.
Data and check bits are written into memory.

Address and Syndrome Retrieval
}.
Read CSR
If CSR 14=0, then CSR 05 through 11 contains A11 through A17 of the failed address.
If CSR 14=1, then CSR 05 through 09 contains A18 through A21 and AO1 of the failed address.
2.

Write CSR change CSR 14.
If CSR 14 was 0, then change to 1.
If CSR 14 was 1, then change to 0.

4-17

CSR 05 through 11 (or CSR 05 through 09) contains the other half of the address (see step 1).

Write CSR (Enter Diagnostic Mode)

Read CSR

Set CSR 02=1, CSR 14=1

CSR 05 through 10 contains syndrome bits.

4.3.3.4 Diagnostic Mode (ECC Enabled)

()

DIAGNOSTIC MODE 'J J

ENABLE ERROR CORRECTION
CLEAR INHIBIT MODE

SHR-0260.88

Diagnostic mode allows the ECC of the MSV11-J to be tested. An error may be simulated by writing
‘wrong’ check bit data into a memory location. This error should be detected and corrected on a
subsequent read from that location. Data written into CSR 05 through CSR 11 in the diagnostic mode is
substituted for the generated check bits (from the parity tree logic) on subsequent DATO cycles.

Incorrect check bits can be written to any memory location in this manner. Subsequent DATI cycles to

any of these locations (while in normal mode) cause error logging.

Additionally, the check bits from a memory location are latched into CSR 05 through CSR 11 during a
DATI cycle. The bus master can force check bits during DATO cycles, it can read check bits during
DATI cycles.

The error conditions for the various cycle types in this mode are listed below.
Read Cycle - No Errors

e
e

Data is read from memory and placed on the bus.
Check bits read from memory are latched in CSR § through CSR 10.

Read Cycle - Single Error
CSR 4 is set.

Data is read from memory and corrected before being placed on the bus.
Check bits read from memory are always latched in CSR 5 through CSR 10.
Address and error syndrome bits are NOT latched in the CSR.

Read Cycle - Double Error
CSR 15 is set
Red LED is on.

Check bits read from memory are latched in CSR 5 through CSR 10.
Address and error syndrome bits are NOT latched in the CSR.
Error asserts BDAL 16 during the data portion of the read cycle.

Write Byte Cycle - No Errors

New byte is combined with old byte and written to memory.

Check bits from CSR 5 through CSR 10 (instead of the ECC) are written into memory.

4-18

Write Byte Cycle - Single Error During Read Portion

CSR 4 is NOT set.
Data containing error is corrected and combined with the new byte.
Check bits come from CSR 5 through CSR 10.
Data and check bits are written into memory.
Address and syndromes are NOT latched in the CSR.

Write Byte Cycle - Double Error During Read Portion

CSR 15 is NOT set.
Address and syndromes are NOT latched in the CSR.
Error is ignored.
New byte is combined with the old byte.
Check bits come from CSR 5 through CSR 10.
Data and check bits are written into memory.

Write Word Cycle

®
®

Check bits come from CSR 5 through CSR 10.
Data and check bits are written into memory.

Check Bit Retrieval
1.
Must be in diagnostic mode (CSR 2=1, CSR 14=0)

Read memory location
Check bits from RAMs are latched in CSR 5 through CSR 10.

Read CSR
CSR 5 through CSR 10 contain check bits Cbx, Cb0, Cbl, Cb2, Cb4, and CbS8.

Inserting Check Bits (for checking ECC logic)
1.
Write check bit pattern into CSR 5 through CSR 10 (CSR 2=1).
NNTE-

LYNS
&

Kido

If fhe

£3

write puts th

CSR 10.
2.

PP
N~ —
memory is in the normal mode, this step
iakes iwo writes io the CSR. The first CSR
memory in the diagnostic mode, the second write loads check bit data in CSR 5 through

Write to a memory location.
The contents of CSR 5 through CSR 10 are written to that locations check bit RAMs (Cbx,
Cb0,
Cbl, Cb2, Cb4 and Cb8).

4.3.3.5

Diagnostic Mode (ECC Disabled)

DIAGNOSTIC MODE —1

DISABLE ERROR

CLEAR INHIBIT MODE.

SHR-0262-84

This mode is a variation of the diagnostic mode. Check bits can be written and read through the CSR
as
described in the Diagnostic Mode. Single-bit errors are not correctable in this mode so they are reported
as
uncorrectable.

4-19

The error conditions for the various cycle types in this mode are listed below.
Read Cycle — No Errors

Data is read from memory and placed on the bus.

Check bits read from memory are latched in CSR 5 through CSR 10.

Read Cycle - Single Error

CSR 4 and CSR 15 are set. Single error is uncorrectable.
Red LED is on.

DATA is NOT corrected. Uncorrected data is placed on the bus.

Check bits read from memory are always latched in CSR 5 through CSR 10.
Address and error syndrome bits are not latched in the CSR.
BDAL 16 is asserted on the bus during the data portion of the read cycie.
Read Cycle - Double Error
CSR 15 1s set.
Red LED is on.

Check bits read from memory are latched in CSR 5 through CSR 10.
Address and error syndrome bits are NOT latched in the CSR.
Error asserts BDAL 16 during the data portion of the read cycle.

Write Byte Cycle - No Errors

New byte is combined with old byte and written to memory.

Check bits come from CSR 5 through CSR 10 (instead of the ECC) and are written into
memory.

Write Byte Cycle - Single Error During Read Portion
CSR 4 is NOT set.

Data containing error is corrected and combined with the new byte.

Check bits come from CSR 5 through CSR 10.
Data and check bits are written into memory.

Address and syndromes are NOT latched in the CSR.
Write Byte Cycle — Double Error During Read Portion
CSR 15 is NOT set.

Address and syndromes are NOT latched in the CSR.
Error is ignored.

New byte is combined with the old byte.
Check bits come from CSR 5 through CSR 10.
Data and check bits are written into memory.
Write Word Cycle

e
e

Check bits come from CSR 5 through CSR 10.
Data and check bits are written into memory.

Check Bit Retrieval

Must be in the diagnostic mode (CSR 2=1, CSR 14=0).

Read memory location.

Check bits from RAMs are latched in the CSR (CSR S through CSR 10).
2.

Read CSR

CSR 5 through CSR 10 contain check bits (Cbx, Cb0, Cbl, Cb2, Cb4, and CbB).

4-20

Inserting Check Bits
1.
Write check bit pattern into CSR 5 through CSR 10 (CSR 2=1).
NOTE: If the memory is in normal mode, this step takes two writes to the CSR. The first CSR write
puts the memory in the diagnostic mode, the second write loads check bit data in CSR 5 through CSR
10.
2.

Write to a memory location.
The contents of CSR 5 through CSR 10 are written to that location’s check bit RAMs (Cbx, Cb0,
Cbl, Cb2, Cb4, and Cb8).

4.3.3.6

Protected Diagnostic Mode (ECC Enabled)
15
X

10 1

)

CSR 3=0 PROTECTS 0-16 KW
CSR 3=1 PROTECTS 16KW-32KW
DIAGNOSTIC MODE
ENABLE ERROR
CORRECTION

— SET INHIBIT MODE

SHR-0273-84

Protected diagnostic mode may be enabled while in diagnostic mode. This protected mode protects one of
two 16 kW blocks of memory where the diagnostic program resides. The protected block remains
protected by the error correction logic.
The error conditions for the various cycle types in this mode are listed below.
Read Cycle - No Errors
®
Data is read from memory as in the normal operating mode.
®
Check bits read from memory are NOT latched in CSR 5 through CSR 10.
Read Cycle - Single Error
e
CSR 4 is set.
®
Check bits are NOT latched in CSR 5 through CSR 10.
e
Data is corrected by the ECC before being put on bus.
®
Address and syndromes are NOT latched in the CSR.

Read Cycle - Double Error
CSR 15 is set.
Red LED is on.

Check bits read from memory are NOT latched in CSR 5 through CSR 10.
Address and error syndrome bits are NOT latched in the CSR.
Error asserts BDAL 16 during the data portion of the read cycle.

Write Byte Cycle — Single Error During Read Portion
e
CSR 4 s set.
e
Address and syndromes are NOT latched in CSR 5 through CSR 10.
e
Data containing error is corrected and combined with new byte.
®
Check bits are generated by ECC on the new word.

4-21

Write Byte Cycle ~ Double Error During Read Portion
e

CSR 15is NOT set.

Error is preserved by writing the old data and check bits back into memory. The new byte is

Address and syndromes are NOT latched.

lost. Error is detected on the next DATI cycle to that location.

Write Word Cycle

e
®

Check bits are generated by the ECC.
Check bits and data are written into memory.

Address, Syndrome, Check Bit Retrieval

The diagnostic protected 16 kW block of memory stores the memory resident diagnostic. CSR 3 selects
the 16 kW block to be protected. This block, therefore, behaves as though it were in the normal mode with
ECC enabled. Check bits are not latched.

Address and syndrome bits are not latched while in this mode. The CSR is intended for check bit storage
for the memory under test (not protected).
Inserting Check Bits

Check bits are not written from the CSR to the RAM check bits while in the protected block. This
protected block behaves as though it were in normal mode with ECC enabled. Check bits are generated by
ECC.

4.3.3.7

Protected Diagnostic Mode (ECC Disabled)

0/1

CSR 3=0 PROTECTS 0-16 KW
CSR 3=1 PROTECTS 16KW - 32 KW

DIAGNOSTIC MODE

DISABLE ERROR CORRECTIO

SET INHIBIT MODE

SHR-0263-84

This mode (?1 varia.tion of the protected diagnostic mode) protects one of two 16 kW blocks of memory
where the diagnostic program resides. This block of memory remains protected by the error correction
logic and therefore behaves as though it were in the normal mode with ECC enabled. Check bits are not
latched and single-bit errors are corrected.

4-22

The error conditions for the various cycle types in these modes are listed below.

Read Cycle - No Errors
e
Data is read from memory as in the normal operating mode.
®
Check bits read from memory are NOT latched in CSR 5 through CSR 10.

Read Cycle - Single Error
&
SR 4 is set.
®
Check bits are NOT latched in CSR 5 through CSR 10.
e
Data is corrected by the ECC before being put on bus.
®
Address and syndromes are NOT logged in the CSR.
Read Cycle — Double Error
CSR 15 is set.
Red LED is on.
Check bits read from memory are NOT latched in CSR 5 through CSR 10.
Address and error syndrome bits are NOT latched in the CSR.
Error asserts BDAL 16 during the data portion of the read cycle.
Write Byte Cycle - Single Error During Read Portion
CSR 4 is set.
Address and syndromes are NOT latched in CSR 5 through CSR 10.
~ Bad data is corrected and combined with new byte.
Check bits are generated by ECC on the new word.
Write Byte Cycle — Double Error During Read Portion
e
(SR 15is NOT set.
®
Address and syndromes are not latched in the CSR. Error is preserved by writing the old data
and check bits back into memory. The new byte is lost. Error is detected on the next DATI
cycle to that location.
Write Word Cycle
®
Check bits are generated by the ECC.
®
Check bits and data are written into memory.

Check Bit Retrieval
The protected 16 kW block of memory stores the memory resident diagnostic. This block behaves as
though it were in normal mode with ECC enabled. Check bits are not latched. The CSR stores check bits
for the memory under test (not protected).
Inserting Check Bits
Check bits are not written from the CSR to the RAM check bits while in the protected block. This

protected block behaves as though it were in normal mode with ECC enabled. Check bits are generated by
the ECC.
4.3.3.8

Operating Modes Summary — Table 4-6 is a summary of error conditions in the seven operating
modes when performing the various cycle types. As an example of how to use the table, assume the
MSV11-J is in normal mode performing a write byte cycle and there is a single error. In this example,
CSR 4 is set to 1, the error is corrected, address and syndrome bits are latched in the CSR, check bits are
not latched and the source of the check bits is from the ECC in the data gate array.

4-23

Table 4-6

Error Condition Summary for Various Operating Modes

Read

Write Byte

Single Error

Double Error

Write Word

No Errors

Single Error

Double Error

No Errors

CSR 4=1
Yes

CSR 15=1, LED
No

CSR 4=1
Yes

No
No

CSR 15,

CSR 15=1, LED

CSR 15=1,

Yes

Normal Mode - ECC Enabled

Error indication
Error corrected

Latch address and syndrome
Latch check bits
Check bit source

No
No
MEM

Yes
No
MEM

No
No
ECC

Yes
No
ECC

No
No
MEM

No
No
ECC

vi-v

Normal Mode - ECC Disabled

Error indication

Error corrected

Latch address and syndrome
Latch check bits
Check bit source

No
No
MEM

4=1, LED

Yes
No
MEM

No
No
ECC

4=1, LED

Yes
No
ECC

No
No
MEM

No
No
ECC

Protected Normal Mode - ECC Disabled

Error indication
Error corrected

Latch address and syndrome
Latch check bits
Check bit source

No
No
MEM

No
Yes

No
No
MEM

CSR 15=1, LED
No
Yes
No
MEM

No
No
ECC

No
Yes
No
No
ECC

No
No
No
No
MEM

No
No
ECC

CSR 4=1
Yes
No
CSR
MEM

CSR 15=1, LED
No
No
CSR
MEM

No
No
CSR

No
Yes
No
No
CSR

No
No
No
No
CSR

No
No
CSR

Diagnostic Mode — ECC Enabled

Error indication
Error corrected
Latch address and syndrome
Latch check bits
Check bit source

No
CSR
MEM

LED - Light emitting diode
ECC - Error correction logic
MEM - Memory

CSR - Control and status register

Table 4-6

Error Condition Summary for Various Operating Modes (Cont)
Read
No Errors

Write Byte

Single Error

Double Error

CSR 15=1, LED

No Errors

Single Error

Write Word
Double Error

Diagnostic mode — ECC Disabled

Error indication

Error corrected
Latch address and syndrome
Latch check bits
Check bit source

CSR 15,
4=1, LED

No
No
MEM

No
No
CSR
MEM

No
No
CSR

No
No

MEM

No
No
No

CSR

Yes
No
No
CSR

No
No

CSR

CSR 4=1
Yes

No
No

No
No
ECC

No
No
MEM

No
No
ECC

No
No

SC-¥

Protected Diagnostic Mode - ECC Enabled
Error indication
Error corrected
Latch address and syndrome
Latch check bits
Check bits source

CSR 4=1
Yes

No
No
MEM

CSR 15=1, LED
No
No
No
MEM

ECC

Protected Diagnostic Mode - ECC Disabled

Error indication
Error corrected
Latch address and syndrome
Latch check bits
Check bit source

CSR 4=1
Yes

SR 15=1, LED
No

CSR 4=1
Yes

No
No

MEM

ECC

MEM

ECC

Error Reporting

4.3.4

During a PMI Read, a double word transfer occurs. The CSR must have a means of logging an error in

either or both words.

All reads from memory are double word reads. The cycle type determines the number of words to be
transmitted (i.e., one word during a Q-bus cycle, two words during a PMI cycle). Furthermore, the
operating mode (i.e., normal, diagnostic mode) determines what is logged (i.e., check bits, syndrome bits).
bus and Q-bus
word and no
second
the
in
errors
two
are
there
assume
chart,
the
cycles. As an example of how to use
Q-bus cycle
a
If
set.
is
15
bit
CSR
and
logged
is
word
second
The
errors in first word during a PMI cycle.

The chart below shows the error logging for single and double word errors during PMI

is executed under these conditions, no error logging occurs (Table 4-7).
Table 4-7

Error Logging

Number of

Word

1st

Double Word
Transfer (PMI)

0
0
1
1
1
0
2
2
2

0
1
0
1
2
2
0
1
2

No log
Log Ist, set CSR 04
Log 2nd, set CSR 04
Log 2nd, set CSR 04
Log 1st, set CSR 04, 15
Log 1st, set CSR 15
Log 2nd, set CSR 15
Log 2nd, set CSR 04, 15
Log 2nd, set CSR 15

Errors
2nd

Single Word
Transfer (Bus)
No log
Log Ist, set CSR 04
No log
Log 1st, set CSR 04
Log 1st, set CSR 15
Log 1st, set CSR 15

No log
Log Ist, set CSR 04
Log 1st, set CSR 15

NOTES:

Log indicates that address and syndrome bits are latched when in normal operating mode. Refer
to Paragraph 4.3.3 for details on the logging of errors for different operating modes and cycle
types.

If it is desired to log the first word in normal mode error, during a PMI transfer the access
sequence must be changed, i.e., first word must be accessed second. The reason for this is that the
CSR bits for the first word are overwritten by the second word.

In diagnostic operating mode, check bits from the first word of a two word transfer are logged in
the CSR. Check bits from the 2nd word are not logged. CSR 04 and CSR 15 will reflect the word
with the most significant error.

As an example, during a PMI read, with no error in the first word and a double bit error in the
second, the check bits from the first word will be latched in the CSR while the double bit error

from the second word will set CSR 15 and turn on the red LED.

4-26

CHAPTER 5
DIAGNOSTICS

5.1 GENERAL
No maintenance is required for the MSV11-J.

CAUTION: All power must be off before installing or removing modules. Always be sure the
component side of the memory faces in the same direction as the other modules within the LSI system.
5.2 PREVENTIVE MAINTENANCE
The MSV11-J requires no preventive maintenance, however, periodic preventive maintenance may be
performed on the system. Consult the system manual for details.

5.3

Check the fans to be sure they operate when power is on.

Check air filters (if equipped).

Run diagnostic test if an operating problem is suspected.

DIAGNOSTIC TESTING

5.3.1 Introduction
The diagnostic test for the MSV11-J memory is CYMJAOQ which is a standalone memory diagnostic.

CVMIJAQO is used to checkout ECC memories and/or parity memories. Running the CVMJAQ diagnostic
destroys all the data stored in memory. In testing ECC memories, the diagnostic writes incorrect ECC
data and verifies that the ECC logic is working correctly.
NOTE: In a PDP-11/84 UNIBUS system the diagnostic checks the Private Memory Interconnect
(PM1) memory but does not check the UNIBUS memory.

5.3.2 Operational Switch Settings
The operational software switch settings and their functions are described in Table 5-1. To change the
software switch register (SWR) contents, do a “CONTROL G” while the diagnostic is running. This
causes a display of the current SWR value and the prompt for the octal input of the new SWR value from
the terminal. This routine does not respond to CONTROL G if you have a hardware switch register.
In Table 5-1, the number in the second column is the octal value you type to select the particular SWR.
For example, to select SWR 11 type 4000 (octal) which means that SWR 0 through 10 are 0’s with SWR
11 being a 1. All other settings are 0’s.
Example:
15

haa SRR

i
SR

NS,

—nrN

———

Table 5-1

Switch

Switch Settings
Octal

Value

Detect Single-bit Errors

Definition

For manufacturing purposes this switch should always be on. For field

service purposes this switch should always be off.

This switch allows all ECC single-bit errors to be reported by disabling
error correction. Error printouts of single-bit errors are not distinguished
from double-bit errors.

NOTE: If double-bit errors are found in the memory, switch 0 should be set to make sure
that new data can be written to the locations containing double-bit errors.

1-3

Test Mode

Test modes determine the recursion algorithm to be used during pattern test.
Mode Name

Description

0
1
2
3
4
5
6
7

0
2
4
6
10
12
14
16

BAFPAF

Banks forward, patterns forward

BAWPAF
BAWPAR
PAFBAF
PAFBAW
PARBAF
PARBAW

Banks worst first, patterns forward
Banks worst first, patterns reversed
Patterns forward, banks forward
Patterns forward, banks worst first
Patterns reverse, banks forward
Patterns reverse, banks worst first

Fat Terminal

BAFPAR

Banks forward, patterns reverse

This informs the program that the console terminal has a width of at least
132 columns.

100

200

Limit Max Errors Per Bank

This limits the number of error typeouts per bank. The default is 10,
however this can be changed by changing location “ERRMAX” manually.
Inhibit Configuration Map

This inhibits the printing of a map showing the memory configuration.
Detailed Error Reports

After any normal error report is typed, this option causes the contents of
the following registers to be typed.

RO, R1, R2, R3, R4, RS, SP, “CONTROL”, “CPUERR”
Halt Program

This initiates the following sequence.

If program is relocated it moves back to bank zero.
N

400

Flushs out all possible double-bit errors.

Turns off memory management.
Restores loaders.

Unmap the Unibus Map (if there is one).

5-2

Table 5-1

Switch Settings (Cont)

Switch

Octal
Value

1000

Definition
Loop On Error
This causes looping from failure point back to the last correctly initialized
area of the current test.

2000

Bell On Error
This causes a bell (or beep or click) on each error trap.

4000

Quick Verify
If this switch is selected, about 1/64th of the possible combinations of
single-bit errors and double-bit errors are tested.

10000

Inhibit Relocation
This prevents the program from relocating and consequently prevents the
program from testing at least 16Kwords of memory.

20000

Inhibit Error Typeouts
This causes returns from the error routine without the typed messages.
Other error functions are not effected.

40000

Loop On Test

This causes looping on the present test or pattern (back to last scope trap).

If in a pattern, then the looping is for an entire bank of 16K addresses.
15

100000

Halt On Error
- Continuing from this halt, the test first checks for a chan
software switch register (“Control G” in the TTY input { buffer) then it
continues testing.

3.3.3 CVMJAO Diagnostic Operation
The following paragraphs list and describe three sample diagnostic printouts. The first example shows a
complete sequence that includes power up, the booting sequence, and the diagnostic printout. This first
example shows an error-free memory. The second example shows the diagnostic printout of a memory
containing errors. The power up and booting sequence is similar to the first example and consequently is
not shown. The third example shows the diagnostic printout of a non-contiguous memory. The power up
and booting sequence is similar to the first example so it is not shown. The underlined text is typed in by
the operator.
5.3.3.1

Example 1 - Error Free Printout

Power Up Test of KDJ11-B CPU
The following message appears each time the CPU is powered up.
Testing

Memory

Size

Progress

4088

Ster memors test
Ster 1 2 3 45 67

Message

Entering

Flease

wait

Kbutes
8

¢
Dizslog

mode

Booting Up the System

To boot the system, type B DLO and press return. Respond to the dialog that appear
Commands are: [Help, Boot, List, Map, Test]

Type a command then press the RETURN key: B DLO <CR>
Booting DLO
Starting sustem

CHMDLE1 XXDP+ DL MONITOR 28K
BOOTED VIA UNIT O

ENTER DATE (DD-MMM-YY) 31 OCT 84 <CR>
RESTART ADDR:153726
50 HZ? N <CR>

LSI? N <CR>

THIS IS XXDF+. TYFE °*H® OR °H/L*® FOR DETAILS

Running the CVMJAO Diagnostic — The diagnostic printout and a description appears below.
+R CVUMJAO <CR>
CVMJAOBIN

CVUMJAO

ECC/PARITY MEMORY DIAGNOSTIC

11/83 CACHE AVAILABLE
<CR>
SWR = 000000 NEW =
CSR MAF

CSR

MEMTYFE

0123456789%9ABCDETF
EE

2044K OF MSV1i-J

2044K WORDS OF MEMORY TOTAL

5-4

MEMORY CONFIGURATION MAP

16K WORD BANKS

1
2
3
4
>
6
7
0123456701234567012345670123456701234567012345670123454670123

ERRORS
MEMTYPE

CSR
FROTECT

EEEEEEEEEEEEEEEEEEEEEEEEC EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE

000000000000000000000000000000000000000000000000000000000000

1
1
1
1
1
1
1
o
1
2
3
4
S
6
456701234567012345670123456701234567012345670123456701234567

ERRORS
MEMTYFE
CSR

PROTECT

EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE
000011111111111111112111211221123111314211111112121313212131311111111

1
7

01234567
ERRORS
MEMTYFE

EEEEEEEE

CSR

11111111

PROTECT
END

FASS

#Qi

NOTES:
The initial switch register setting is 000000. To enter a new switch register setting, refer to
1.
Paragraph 5.3.2.

The E in the MEMTYPE row designates ECC.
There is about two minutes running time after MEMTYPE appears in the CSR map. This time is
required to size the memory and match the CSR to the memory. Actual time depends on the
memory capacity and processor speed.

In the memory configuration map each column represents 16K word banks. The total memory
consists of 167 banks octal. If all banks are filled, it represents two Sully-populated MSV11-J
memories for a total of two megawords (4 Mb) of memory. In this example, the Os in the CSR
row represent the first memory and the Is represent the second memory.

The PROTECT
a.

b.
¢.

PP directly below the row designated CSR indicates:

Diagnostic is resident in one of two 16K word protected banks.

The diagnostic cannot be destroyed because these two banks are protected.
The two banks are alternately checked by relocating the diagnostic to the alternate bank.

END PASS #Q1 (end of pass completion) is a quick verify test. It runs about 15 minutes
and
checks only 1/64th of the possible combinations of single-bit errors and double-bit errors.

To run the entire test routine, the user must enter Field Service mode. Type CONTROL
mode. An end of pass completion in this mode takes about 45 minutes.

Running time may vary, depending on memory size and speed of processor.

5-5

F to enter this

5.3.3.2 Example 2 — Printout Containing Memory Errors

This diagnostic° printout contains errors in the upper half of memory (indicated by X’s).
+R

CVMJAO

ECC/FARITY MEMORY DIAGNOSTIC

11/83 CACHE AVAILABLE
NEW = <CR>
SWR = 000000

MAF

CSR

0123456789ABCDEF

MEMTYFE

256K OF Q@-BUS FPARITY MEMORY
1024K OF ECC MEMORY
1280K WORDS OF MEMORY TOTAL
MEMORY

CONFIGURATION MAP

16K

BANKS

WORD

ERRORS

0123456701234567012345467012345670123456701234567012345670123
XXXXXXXXXXXX

CSR

000000000000000011111111111111111111111111111111111111111111

MEMTYFE
FPROTECT

FPPPPPPFPPPPPPPPEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE
PP

1
1
1
1
1
1
1
0
1
2
3
4
9
b
456701234567012345670123456701234567012345670123456701234567
ERRORS

XXXXXNXXXXXXXXXXXXXX

MEMTYFE

EEEEEEEEEEEEEEEEEEEE

CSR

11111111111111111111

PROTECT

NOTES:

2.
3.

The P in the MEMTYPE row designates parity memory and the E designates ECC memory.
This example shows that the upper half of the

ECC memory contains errors. Errors are indicated

by the X's in columns 60 to 117 (octal). (See row labeled errors.)

The O’s in the CSR row denote the first memory (parity memory) and the 1's denote the second

memory (ECC memory).

5-6

5.3.3.3

Example 3 — Printout Showing Non-Contiguous Memory

«R _CUMJAO
CVMJAOEBIN
CVMJAO

ECC/FARITY MEMORY
11/83 CACHE AVAILABLE
ZWR = 000000
NEW = LCR>

CSR

MAF

CSk

01234546789ABCDEF

MEMTYFE

236K

1024K
1280K

DIAGNOSTIC

Q-BUS

FARITY

OF ECC MEMORY
WORNS OF MEMORY

MEMORY

TOTAL

MEMORY

CONFIGURATION

16K

ERRORS
MEMTYFE
CSR

ERRORS
MEMTYFE

CSR

FPROTECT

BANKS

1
2
3
4
>
é
7
01234567012345670123456701234567012345670123456701234567
0123

FFFFFFPPPFPFPPFPF
0000000000000000

FROTECT

WORD

MAF

EEEEEEEEEEEEEEEEEEEEEEEEEEEE
111111311111111121111111111111

1
1
i
1
i
0
1
2
3
4
436701234567012345670123456701234567012345

é
670123456701234567

EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE

1111111121111113382111111111112122111131

‘

NOTES:
1.
The O’s in the CSR row denote first memory (parity memory) and the 1’s denote

(ECC memory;.

second memory

There is a non-contiguous area from 20 to 37 (octal). Indicated by blank spaces.

The example represents the MSV11-P loaded with starting address 0 and the
MSVI11-J with
starting address 0.5 Megawords (1 MB).
The memory can be made contiguous by changing the starting address switch
setting of the
MSV11-J memory.

5.4

DIGITAL’S SERVICES

5.4.1

Digital Repair Service

ance and on-site services are
Maintenance can be performed by the user or by Digital. Digital’oks mainten
described in Chapter 1 of the Microcomputer Processor Handbo (EB-18451-20).
Digital Field Service offers a range of flexible service plans.

and insurance against unplanned repair
ON-SITE SERVICE offers the convenience of service at your site
Service Specialist. Within a few hours
bills. For a small monthly fee you receive personal service from our
the specialist is dispatched to your site with equipment and parts to give you fast and dependable
maintenance.

through Friday. Options are
BASIC SERVICE offers full coverage from 8 am. to 5 p.m,, Monday
available to extend your coverage to 12-, 16-, or 24-, hour days, and to Saturdays, Sundays, and holidays.
st response and nonstop remedial
DECservice offers a premium on-site service that guarantees extra-fathis
maintenance. We don’t leave until the probiem is soived, which makes service contract ideal for those
who need uninterrupted operations.

Under Basic Service and DECservice all parts, materials, and labor are covered in full.
maintenance costs
CARRY-IN SERVICE offers fast, personalized response, and the ability to plan your
to one of 160 Digital
for a smaller monthly fee than On-Site Service. When you bring your unit (usually
24 hours). This
Servicenters worldwide, factory-trained personnel repair your unit within two days Service
Office to see
service is available on selected terminals and systems. Contact your local Digital Field
if this service is available for your unit.

Digital Servicenters are open during normal business hours, Monday through Friday.

the technical
DECmailer offers expert repair at a per use charge. This service is for users whothehave
module to
faulty
resources to troubleshoot, identify, and isolate the module causing the problem. Mail mailed back
to you

our Customer Returns Center where the module is repaired and a replacement is
within five days.

st basis.
PER CALL SERVICE offers a maintenance program on a noncontractual, time-and-material-cowho
have
customers
for
This service is available with either On-Site or Carry-In Service. It is appropriate
Field
from
support
the expertise to perform first-line maintenance, but may occasionally need in-depth
Service.

Per Call Service is also offered as a supplementary program for Basic Service customers who need
maintenance beyond their contracted coverage hours. There is no material charge in this case.
On-Site Per Call Service is provided on a best effort basis, with a normal response time of two to three
days. It is available 24 hours a day, seven days a week.

Carry-In Per Call Service is available during normal business hours, with a two to three day
turnaround.

Digital International Field Service Information Numbers

US.A.
Canada
United Kingdom
Belgium
West Germany
Italy
Japan
France

Denmark
Spain
Finland
Holiand
Switzerland
Sweden
Norway

1-(800)-554-3333
(800)-267-5251
(0256)-57122
(02)-242-6790
(089)-9591-6644
(02)-617-5381/2
(03)-989-7161
1-6873152

5-8

430-1005
91-7334370
90-423332
(01820)-34144
01-8105184
08-987350
2-256422

INDEX

G
Address bits, 2-2
Address cycle, 2-1

Gate arrays
Address, 1-4, 2-4
Data, 1-4, 2-4-2-6
B
I

Backplane, 1-2
Backplane placements, 4-6
Battery backup, 1-2, 1-3, 1-8
Block mode read cycle, 3-2
Block mode write cycle, 3-3
BUS cycles, 1-3

I/0 page,

1-3

J
Jumper configuration, 4-1
Jumper installation, 4-2

Check bits, 1-6, 1-7, 2-4, 2-5
Column address strobe, 2-3
CSR address, 4-5
CSR address switch settings, 4-5
CSR bit format, 4-7
CSR read cycle, 3-1
CSR write cycle, 3-2

LED,

1-3
M

Memory address switch settings, 4-3
Module, 1-1, 1-3, 4-1
Module installation, 4-1
MOS, 1-1, 1-4, 1-6, 1-8
MTBF, 1-6

D
Data cycles

Read (DATI), 1-4, 1-7, 2-2, 2-3, 3-1
Read-modify-write (DATIO), 3-3
Read-modify-write byte (DATIOB), 3-3
Write byte (DATOB), 1-7, 2-5, 3-2
Write word (DATO), 1-7, 2-4, 3-2
Diagnostic mode, 4-9-4-12, 4-15
ECC disabled, 4-19
ECC enabled, 4-18
Double refresh, 1-4

Normal mode
ECC disabled, 4-15
ECC enabled, 4-14
Normal protected mode
ECC disabled, 4-17

0O
Operating modes, 4-14
Operating modes summary, 4-23

ECC, 1-2-1-4, 1-6, 1-8, 2-5, 4-23
ECC INIT cycle, 3-1, 3-4
Error correction, 1-3
Error reporting, 4-26

P
PMI, 1-1, 1-3, 1-4, 2-1, 3-1, 3-3, 4-6
Protected diagnostic mode
ECC disabled, 4-22
ECC enabled, 4-21
I-1

Q
‘Q-Bus, 1-1, 1-3, 1-4, 1-7, 1-10, 1-12, 2-5,
3-1-3-3

RAM, 1-4, 1-6, 1-8, 1-9, 2-1, 2-§, 3-1, 3-3
Refresh, 1-2, 1-4, 1-8
Refresh cycle, 1-11, 3-4
Refresh priority, 1-4, 1-11
Refresh demand, 1-4, 1-11
S
Specifications
Access and Cycle Times, 1-10
Electrical, 1-9
Environmental, 1-8
General, 1-7
Interface, 1-10
Performance, 1-10
Starting Memory Address, 1-2, 4-3
U

UNIBUS, 1-1, 1-3

I-2

[2f2]']

7]ofs[<[s[2]1

S2-CSR ADDRESS

S1-MEMORY ADDRESS

dlilaliltll
i}

EK-MSV1J-HR-001

MSV11-J

CONFIGURATION SUMMARY

RESISTOR R10 D D-{m OUT (256K RAMS)
(100n)

MSV11-J is a metal oxide semiconductor, random access memory. It uses
error detection and correction {ECC), a control and status register (CSR) to

W2 IN

store status and error information, and has starting addresses on 8 kW

(HALF POPULATED)
W2 QUT

boundaries. The board can be configured half or fully populated with 256K

(FULL POPULATED}

dynamic RAMs. Maximum memory capacity 2 Mb.

The
SHA-041284

memory

is for Q-bus

interconnect (PMI}

systems

and

supports

the

private

memory

protocol of the KDJ11-B processor. The PMI bus is

specifically designed for and used in the PDP-11/83 Q-Bus System and the

PDP-11/84 UNIBUS System.

MEMORY STARTING ADDRESS

MSV11-J memory has these features.

Equivalent

Starting

Switch

Address

Uses 256K dynamic RAMs. Board can be full or half popuiated

1 MW (2Mb)

Executes normal Q-bus protocol and faster PM! protocol

WwN

Has starting addresses on 8 kW boundaries

Memory Address

512 kW (1Mb)
DEL

IC19

Ilann

wU3IES

128 kW (256 kb)

logic

Kvv

{J14

—~—

NN O

32 kW (64 kb)

64 kKW (128 kb)

8 kW (16 kb)

Battery backup can be configured on board

16 kW (32 kb)
Green LED indicator on module indicates the presence of +5 volits (+5

VBB when configured for battery backup)

Example:

0 kW Starting Address

Example:

96 kW Starting Address

On board refresh of the RAMs is transparent to CPU

SW1 through SW8 Off

Compatible with 18- or 22-bit address backplane

SW5 and SW6 = On, all others Off

Error correction logic (ECC) to detect and correct single-bit errors and

CSR ADDRESS

to detect double-bit errors

Address

Switch Settings
1

17772100

Off

Oft

Off

17772102

Off

17772104

Off

17772134

On,

Off

17772136

Example:

CSR Address = 17772106
Switches 3 and 4 On
Switches 1 and 2 Off

Red

LED

indicator on

module

indicate the

detection

of an

uncorrectable error

Contains CSR which can be assigned one of 16 addresses

ECC operation can be controlled via CSR

CSR operating modes facilitate diagnostic testing

Memory compatible with Q-CD backplanes (not compatible with Q-Q

backplane).

CSR REGISTER

UNCORRECTABLE

UNCORRECTABLE
ERROR
INDICATION

MULTI-F;‘]I}JCTION
REGISTER

ERROR
INDICATION

ENABLE

EXTENDED

.
ERROR
ADDRESS
RETRIEVAL

DISABLE
CORRECTION
MODE

DIAGNOSTIC

ISFE-IEIBIT—-

~CHECK

;

MODE

RESERVED (0}

Lm;{l;%”

POINTER

SINGLE
- ERROR
INDICATION
SHR-0051-84

CSR15
CSR14

CSR13

CSR04

No uncorrectable error detected

Uncorrectable error detected

=
=
=
=

0
1
O
1

A11 through A17 to CSR11-CSRO5
A18 through A21 and AO1 to CSRO5—-CSR09
Clear Inhibit Mode
Set Inhibit Mode
Reserved {always 0)
Log address and syndrome bits in Normal Mode and

=
CSR12
CSR11—- =
CSRO5

checkbits in Diagnostic Mode

No single error detected

Single error detected

Inhibit Error Indication

Active Error Indication

= 0 0-16 kW ECC Protect
16 kW-32 kW ECC Protect
= 1
Note: CSR13 must be set for CSRO3 to function
= O Normal Operation
CSR02
Diagnostic Mode
= 1
= O Enable Error Correction
CSRO1
Disable Error Correction
= 1

CSRO3

CSRO0O

OPERATING MODES
CSR Bits

Normal

Diagnostic, Protected

Diagnostic

ECC Disable

15 14 134

ECC Disable, Protected

Diagnostic. ECC Disable

Diagnostic, Disable, Protected

wa DU w3

W6
=

W5
CONNECTOR D

CONNECTOR D

+5V SYSTEM

BATTERY BACKUP SYSTEM
SHR-0052-84

X = don't care

Digital Equipment Corporation « Shrewsbury, MA 01545