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EK-MSV0P-UG-004

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Document:	MSV11-P User Guide
Order Number:	EK-MSV0P-UG
Revision:	004
Pages:	60
Original Filename:

OCR Text

EK-MSVOP-UG-001

o

Prepared by*Edut:ctio»n Services

~

Digital Equipment Corporation

|

1st Edition, August 1981

Copyright © 1981 by Digital Equipment Corporation
All Rights Reserved

The reproduction of this material, in part or whole,
information,

contact

the

Educational

Services

is strictly prohibited. For copy

Department,

Corporation, Maynard, Massachusetts 01754.

Digital

Equipment

The informationin this document is subject to change
without notice. Digital Equfpmént
Corporation assumes no responsibility for any errors that
may appear in this document.

Printed in U.S.A.

The

following

are

trademarks

Massachusetts.

DEC

PDP

UNIBUS

VAX

Digital

Equipment

DECnet

DECUS
DIGITAL
Digital Logo

of

|

DECsystem-10
DECSYSTEM-20

|

OMNIBUS

|

0S/8
POT

DECwriter
DiBOL

|

‘

EduSystem

IAS
MASSBUS

Corporation,

RSTS
o

-

RSX

-~

VMS

vT

Maynard

]

‘CONTENTS

CHAPTER1

CHARACTERISTICS
AND SPECIFICATIONS

1.1

INtrodUCHiON ...

1.2

General Description ........... e e AP

|

1.3

Specifications .............co i

2

1.3.1

1

Functional Specifications .............................. P

1.3.2

2
Electrical Specifications .................................
L. o2

1.3.2.1

Voltag
. .....cooiiiii es
i e

3

1.3.2.2

Power Requirements ....... e e eeeeaeenas cee.

3
3

1.3.3

Environmental Specifications ...............cuiiiiinnn...

1.3.3.1

Temperature ...,

4

1.3.3.2

Relative Humidity .......... ...,

4

1.3.3.3

Operating Aifflow . ...
e,4

1.3.34

Altitude ......... P F

1.3.4

Refres
. ...
h

1.35

Diagnostics....... e

1.3.6
1.4

e

6

e

6

e e et e
e e,
6
Backplane Pin Utilization ..............coviiininn, 6

Related Documents ...t

CHAPTER 2

e

INSTALLATION

2.1

General ...

2.2

Wire Wrap Guidelines ........co i,

2.3

Configuringthe

2.3.1

2.3.1.1

2.3.1.2

7

MSV11-P . .

9
9

...t 10

Configuring the Module Stamng Address ............ e 10
Determining Starting Address ...........PN € ¢

Determining Pinstobe Jumpered ........................ 10

23.1.3

Wire Wrap Pins for the Starting Address........ [ 14

2.3.2

Control and Status Register

2.3.3

POWer JUMP
IS ...t

................ .

1

2.3.4

e 16
Bus Grant Continuity Jumpers............ e PR 16

2.35

General Jumpers ..., e, 16

CHAPTER3

FUNCTIONAL DESCRIPTION

3.1

Introduction .............. A e 21

3.2

LSI-11 Bus Signals and Definitions ..................... Cerree.. 22

3.2.1

LSI-F11 Bus Dialogues .............cciviiiiiiiiiiiinninnn.... 24

iii

iv.

CONTENTS

o

3.3

|

/

Functional Description of Memory Module ..................... 30

3.3.1

Xcvers (Transmit-Receives) ........................ P 30

3.3.2

Address LOGIC ...t

3.3.21

30

Board Selection Decode Logic .......e 30

3.322

MOS Memory Address Logic ............................. 32

3323

CSRAddresslogiC.............coiiiiiiiiiiiiiiia... 32

3.3.3

CSRWrite ... i 32

3.34

CSR Read ... 34

3.3.5

Memory Array ... 34

3.3.6

Timing and ControlLOQIC .................................... 35

3.3.7

Parity LOGIC ... 37

3.3.7.1

Parity Generation ......... e B 37

3.3.7.2

Parity Checker .......... ..., e 38

3.38

Refresh....... e et

3.3.9

Charge Pump Circuit ...

3.4

ie et

e i heneerentanaans 38
e 40

Control and Status Register (CSR) Bit Assignment ............. 40

- CHAPTER4

MAINTENANCE

4.1

General

42

Preventive Mamtenance ........................................ 43

421

... 43

Visual Inspection ... 43

422

Power Voltage Check

423

Diagnostic Testing

43

..., 43

...................... i, 44

DIGITAL’'s Services ................... e

APPENDIX A

e 44

SIGNAL SEQUENCES

FIGURES
2-1
2-2
2-3

~2-4
2-5

3-1
3-2

3-3

MemoryBoard ........................... [ 11
Triple Voltage MOS RAM with Battery Backup e, 17
. Triple Voltage MOS RAM without Battery Backup .............. 17

Single Voltage MOS RAM without Battery Backup .............. 18

Single Voltage MOS RAM with Battery Backup ................. 18
Typical System ... ..o 21

MSV11-P Memory Interface .................. ... i
i, 22
Dialogue DATO(B) .......ccoiiniiii
i, 25

3-4

Dialogue DATI ... ..

3-5

Dialogue DATIOB) ................. e

3-6

Logic Functions ... 31
Overview of Memory LogiC ..........o.ooveoiei 33

3-7

3-8
3-9
310

3-11

3-12

26

e

28

CSR Write ...... e A e 34
CSRRead ... 35
BAKMOS RAM Chip ...
e i 36
16K MOS Chip ......e
st
e e
e n e 36

Timingand Control ..............oo i 37
Parity Generators ... 38
3-14 Parity CheCKers ..........oooieiui
39

3-13

CONTENTS

v

3-15

Refresh Logic and Charge Pump Circuit ......... e, 39

3-16

CSRBitAllocation

A-1

Memory Operation Cyc .......... .. 46

..................... e, R 40

A-2

DATO(B) Signal Sequence ............ S 47

A-3

DATI Signal Sequence................. e, e 47

A-4

DATIO(B) Signal Sequence ............ciiiiiiiniiiiinnneenanns 48

TABLES
1-1

MSV11-PVersions ..........ccoiiiiiiiiieiiiiiiiiniinnnnn

1-2

Access and Cycle Times .........e 3

1-3

Multi/Single Voltage MOS RAM ...

1-4

MSVT1-P POWET ...

e

5

1-5

Backplanepantmzatton.,,”..‘,,....,,..,.,,......,.;...,,,...

6

... i,

1

4

2-1

MSV11-P Jumper Check List ........................... e 12

2-2

Starting Address Configurations ........................o 13

2-3

CSR Address Selection ..., 15

2-4

POWET JUMP
IS . o ottt

2-5

Bus Grant Continuity ..., 19

e et 16

2-6

General JUMPBIS ...t e 19

3-1

Summaryof BusCycles ... 21

3-2

LSI-11 Bus Signals and Definitions ............................. 22

3-3
3-4

Dialogues to Perform Memory Data Transfers ......... e 24
Dialogue DATO(B) Cycle . ...
e 25

3-5
3-6

Dialogue
DATl ...
27
Dialogue DATIOB) Cycle ..o 28

3-7
4-1

PROM Output for M8067-LA (Starting Address Zero) ........... 31
Voltage Margins ... 44

CHAPTER 1
CHARACTERISTICS
AND SPECIFICATIONS

1.1

INTRODUCTION

This manual describes the MSV11-P family of memory modules. The
MSV11-P memory modules are metal oxide semiconducters (MOS), random access memory (RAM). They are designed to be used with the LSI-11
bus. The MSV11-P provides storage for 18-bit words (16 data bits and 2
parity bits) and also contains parity control circuitry and a control and sta-

tus register (CSR). There are three versions of the MSV11-P memory

modules as shown in Table 1-1.

Table 1-1

'

MSV11-P Versions
-

Number

Option

Module

Storage

MOS

Module

of

Designation

Designation

Capacity

Chips

Population

Rows

MSV11-PL

M8067-LA

256K words by 18 bit 64K

Full

8

MSV11-PK

M8067-KA

128K words by 18 bit 64K

Half

4

MSV11-PF

M8067-FA

64K words by 18 bit 16K

Full

8

1.2

GENERAL DESCRIPTION

The MSV11-P memory module consists of a single, quad-height module

(M8067) that contains the LSI-11 bus interface, timing and control logic,
refresh circuitry, and a MOS storage array. The module also contains circuitry to generate and check parity, and a control and status register.
The memory module’'s starting address can be set on any 8K boundry

within the 2048K LSI-11 address space or 128K LSI-11 address space.
The MSV11-P allows the top 4K of the LSI-11 address space to be re-

served for the I/O peripheral page. Note that there is no address interleaving with the MSV11-P.

The memory storage elements are 16,384 by 1 bit, MOS dynamic RAM devices or 65,536 by 1 bit MOS dynamic RAM devices. The MOS

storage

array contains 18 of these devices for every 16K rows of memory or 64k

rows of memory. Unlike core memory, the read operation for MOS storage
devices is nondestructive; consequently the write-after-read operation

associated with core memory is eliminated. The MOS storage devices
must be refreshed every 14.5 us so that the data remains valid.

2

CHARACTERISTICS AND SPECIFICATIONS

The MSV11-PF memory uses +5V, +12 V and —5 V. The positive voltages are received from the backplane and the negative voltage is gener-

ated from a charge pump circuit on the board. The MSV 11-PL and MSV11-

PK require +5 V, which is received from the backplane.

There
is a green LED on the module that stays on as long as +5 V power
is supplied to the logic required for memory refresh, read/write request,

arbitration, and row and column addressing.

The control and status register in the MSV11-P contains bits that are used
to store the parity error address bits. By setting a bit in the CSR you can

force wrong parity. This is a useful diagnostic tool for checking out the
parity logic. The CSR has its own address in the top 4K of memory. Bus

masters can read or write to the CSR.

The parity control circuitry in the MSV11-P generates parity bits based on

data being written into memory during a DATO or DATOB bus cycle. One

parity bit is assigned to each data byte and is stored with the data in the

MOS storage array. When data is retrieved from memory during DATI or
DATIO bus cycles, the parity of the data is determined. If parity is good,

the data is assumed correct. If the parity bits do not correspond, the data
is assumed unreliable and memory initiates the following action.
.

Ared LED on the module lights. This prewdes a visual indication of a

parity error and sets CSR bit 15.

2. If bit O in the CSR is set, the memory asserts BDAL 16 and 17. This
warns the processor that a parity error has occurred.

3. Part of the address of the faulty data is recorded in the CSR.
1.3

SPECIFICATIONS
This section of the manual gives functional, electrical, and environme

ntal

specifications and backplane pin utilization information.
1.3.1

Functional Specifications
Table 1-2 provides MSV11-P functional specifications.

1.3.2 Electrical Specifications
The electrical specifications state the voltage and power requirem

the MSV11-P.

ents for

No adjustment or maintenance is required. Two LEDs are used to indicate

board status. A green LED indicates that +5 V CR is present
on the
board. This is useful on battery backed up systems where
the boards
could be removed from the backplane with only +5 V shut
off. A red LED
indicates the detection of a parity error.

CHARACTERISTICS AND SPECIFICATIONS

Table 1-2

3

Access and Cycle Times*

Access Timet

Cycle Timet

Bus

Measure

|

Cycles

Typical

Maximum

DATI

240

260
120

DATO(B)

90

|

Measure
Notes

Typical

Maximum

Notes
4
5

2
2

560
610

590
640

DATIO(B)

660

690

3

1175

1210

6

REFRESH

-

-

-

640

690

7

* Parity - CSR configurations, refer to notes 1, 8, and 9.
1 Tacc(ns)

1 Tcyc (ns)

NOTE 1:

Assuming memory not busy and no arbitration.

NOTE 2:

SYNCH to RPLYH with minimum times (25/50 ns) from SYNCH to ( DINH/DOUTH,).

The DATO(B) access and cycle times assume a minimum 50 ns from SYNCH to DOUTH inside

memory receivers. For actual LSI-11 bus measurements, a constant (K-50 ns) where K= 200
ns should be added to DATO(B) times, i.e., Tacc (Typical) = 90 + (200 — 50) = 240 ns.

NOTE 3: - SYNCH to RPLYH [DATO(B)] with minimum time (25 ns) from SYNCH to DINH and
minimum (350 ns) from RPLYH (DATI) asserted to DOUT asserted.
NOTE 4:

SYNCH to TIM250H negated.

NOTE 5: SYNCH to TIM250H negated with minimum time (50 ns) from SYNCH to DOUTH.
NOTE 6:

SYNCH to TIM250H [DATO(B)] with minimum times (25 ns) from SYNCH to DINH

and minimum (350 ns) from RPLYH (DATI) asserted to DOUT asserted.
NOTE 7:

REF REQ L to TIM250H negated.

NOTE 8:

REFRESH arbitration adds (90 ns) typical and (110 ns) maximum to access.

NOTE9:

REFRESH conflict adds (640 ns) typical and (690 ns) maximum to access and cycle

times.

~

1.3.2.1

Voltages - The MSV11-PF memory modules require +5 V, +12 V,

and —5 V for the multivoltage MOS RAMs. The —5 V is generated from the

memory module. Single voltage MOS RAMs (MSV11-PK/PL) require only +5
V. Voltage margins for the +5 V and +12 V are 5 percent (Table 1-3).
a5

NOTE: Latest MSI available and in use at DIGITAL will be used for control.

1.3.2.2

Power Requirements - Power requirements are provided in

Table 1-4.

1.3.3

Environmental Specifications

Environmental specifications cover storage and operating temperature,
relative humidity, altitude, and air flow specifications.

|

4

CHARACTERISTICS AND SPECIFICATIONS

Table 1-3

Multi/Single Voitage MOS RAM

Multivoltage MOS RAMs (MSV11-PF)

Volitage

Pins

Service

Non Battery

+5V

Backed Up

AA2, BA2, BV1, CA2

+12V

TTL and MOS RAMs

AD2, BD2

MOS RAMs

+5V

AA2, BA2, BV1, CA2

MOS RAMs and

noncritical TTL

Battery

+5 V BBU

Backed Up

AV1, AE1

+12 V BBU

AS1

|

Critical TTL
MOS RAMs

Single Voltage MOS RAMs (MSV11-PK/PL)
Voltage

Pins

Service

AA2, BA2, BV1, CA2

TTL

DA2

MOS RAMs*

noncritical TTL

Non Battery

+5 V

Backed Up

+5V(VDD)

Battery

+5V

AA2, BA2, BV1, CA2

+5V

AV1, AE1

Backed Up

=

Critical TTL
and MOS RAMs

* For systems without +5 V on DA2, +5 V can be supplied from AA2, BA2,

and CA2.

1.3.3.1

|

BV1,

Temperature - Temperature is separated into the following

two

groups.

1. Operating Temperature Range - The operating temperature range
is
+5° Cto +60° C. Lower the maximum operating temperature by
1°
C for every 1000 feet of altitude above 8000 feet.

2. Storage Temperature Range - The storage temperature
range is
—40° C to +66° C. Do not operate a module that has been
stored

outside the operating temperature range. Bring the module
to an environment within the operating range and allow at least five
minutes
for the module to stabilize.

1.3.3.2

Relative Humidity - The relative humidity for the MSV11P

memory modules must be 10 percent to 90 percent
noncondensing for

storage or operating conditions.

|

|

1.3.3.3 Operating Airflow - Adequate airflow must
be provided to limit
the inlet to outlet temperature rise across the module
to §° C when the
inlet temperature is +60° C. For operation below
+55° C. airflow must
be provided to limit the inlet to outlet temperature rise
across the module
to 10° C maximum.

—

CHARACTERISTICS AND SPECIFICATIONS

Table 1-4 MSV11-P Power

MSV11-PF (Multivoltage MOS RAMs)
Voltage

+5 V Noncritical

Standby Current (A)

Active Current (A)

Meas Typ

Meas Typ

1.40

Max

2.21

1.45

1.65

1.20

1.55

2.55

3.76

2.65

3.76

0.10

0.12

0.35

0.53

+5 V BBU

1.15

Total +5 V
+12 V

Voltage

Max

-

2.21

Standby Power (W)

Active Power (W)

Meas Typ

Max

Meas Typ

Max

+5 V Noncritical

7.00

11.60

+5 V BBU

575

8.14

7.25
6.00

11.60
8.14

Total +5 V

1275

19.74

13.25

19.74

1.51

4.20

6.68

21.25

1745

26.42

+12 V

1.20

Total Power

-

13.95

MSV11-PK (Single Voitage, Half Populated)

Voltage

Standby Current (A)

Active Current (A)

Meas Typ

Meas Typ

Max

Max

+5 V Noncritical

1.65

2.10

1.70

2.10

+5V BBU

1.35

1.80

1.75

2.10

Total +5 V

3.00

3.90

3.45

420

-~

Standby Power (W)

Active Power (W)

Meas Typ

Max

Meas Typ

Max

(5.0)

(5.25)

(5.0)

(5.25)

+5 V Noncritical

8.25

11.00

8.50

1.0

+5V BBU

6.75

9.45

8.75

11.0

20.45

17.25

22.0

Voltage

|

Total Power

15.0

MSV11-PL (Single Voltage, Fully Populated)

Voltage

Standby Current (A)

Active Current (A)

Meas Typ

Meas Typ

Max

Max

+5 V Noncritical

1.65

2.10

1.70

+5 V BBU

1.45

1.90

1.85

2.20

Total +5 V

3.10

4.0

360

4.30

Standby Power (W)
Meas Typ
Max
(5.0)
(5.25)

Voltage

-~

-

210

Standby Power (W)
Meas Typ
Max
(5.0)
(5.25)

+5 V Noncritical

8.25

11.0

850

+5 V BBU

7.25

10.0

9.25

11.55

21.0

17.75

22.55

Total +5 V

NOTE:

15.5

11.00

Typical power calculations are done at nominal voltages. Maxi-

mum power calculations are done with maximum currents at the highest

voltage (nominal +5 percent).

5

6

CHARACTERISTICS AND SPECIFICATIONS

1.3.3.4 Altitude
- The module resists mechanical or electrical damage
at altitudes up to 50,000 feet (90 MM mercury) under storage or operating
-

conditions.

NO TE

Lower the maximum operating temperature by 1° C for every

1000 feet of altitude above 8000 feet.

1.3.4

|

Refresh

The MSV11-P memory module uses a self-contained refresh rate that is
typically 650 ns every 14,500 ns. The refresh overhead maximum is 685
ns/13,500 ns or about 5 percent.

1.3.5

|

Diagnostics

The d:agnestms are CVMSAA (22-bit system) and CZKMAA (18-bit sys-

tem)

1.3.6

Backplane Pin Utilization

MSV11-P backplane pin utilization is shown in Table 1-5. Blank spaces in-

dicate pins not used.

Table 1-5

Backplane Pin Utilization

A Connector

Pin

Side 1

B Connector

Side 2

Side 1

Side 2

C Connector

D Connector

Side 1

Side 1

Side 2

Side 2

A

-

+5V

8

BDCOK H

-

+5V

-

-

+5V

-

-

-

+5V VDD

—

-

-

-

C

BDAL16L

GND

D

BDAL 18L

BDAL 17L

GND

+12 V

-

-

BDAL 19L

—

+12V

~

-

-

-

-

E

+5VvVBBU

BDOUTL

BDAL 20L

F

BDAL 02L

-

-

-

BRPLY L

-

BDAL 21L

BDAL O3L

H

-

-

-

BDIN L

-

-

-

J

BDAL 04L

GND

-

-

REFKILL

GND

-

K

BSYNC L

-

BWTBT L

BDAL 05L

-5V MEAS*

-

-

-

-

L

-

BDAL O6L

-

-

-5V MARGIN*

-

-

M

GND

BDAL O7L

-

-

B1AK1L¢t

-

GND

-

-

BDAL 08L

-

B1AK1Lt

-

-

N

-

B1AKOL
t

-

P

-

BDAL 09L

-

BBS7L

B1AKOLt

-

-

BDAL 10L

-

-

-

-

~

R

BREF L

BDMG1Lt

-

S

+12vBBU

BDAL 11L

BDMGOLt

-

BOMG1Lt

-

-

-

T

GND

BINIT L

BDAL 12L

-

GND

BDOMG1Lt

SA16K§

-

-

+5vVBBU

-

-

\Y

BDALOOL

-

-

U

BDAL 13L
BDAL 14L

-

-

BDAL 15L

-

-

-

-

-

-

-

BDALO1L

+5V

* Must be hardwired on backplane or damage to MOS devices may result.

1+ Hardwired via etch on module.

¥ Jumpered on module.
§ When SA16K (starting address 16K) jumper is removed, there is
memory test only).

no connection to this pin (used in

CHARACTERISTICS AND SPECIFICATIONS

1.4

RELATED DOCUMENTS

Refer to the following documents for more information.
e Field Maintenance Printset (MP01239)

e Microcomputer and Memory Handbook (EB-18451-20)

e Microcomputer Interface Handbook (EB-20175-20)
e LSI-11 System Service Manual (EK-LSI-FS-SV)*

These documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street

Northboro, MA 01532

ATTN: Communications Services (NR2/M15)
~Customer Services Section

*Field Service Use Oniy

7

CHAPTER 2
INSTALLATION

2.1

GENERAL

This

chapter contains information for configuring and installing the
MSV11-P family of memory modules. This includes the M8067-LA, M8067-

KA, and M8067-FA.

The fully populated module, M8067-LA, has 512K bytes. The half popu-

lated module, M8067-KA, has 256K bytes. Both modules use 64K bit
chips. The M8067-FA module has 128K bytes of memory. This is a fully

populated module using 16K bit chips..

Installation includes the following procedures.
e Wire wrap guidelines

e Jumpers configuration

CAUTION
1.

You must remove dc power from the backplane during module in-

sertion or removal.

2. You must installfi memoriesg in sequential slots following the CPU.
3.

Be careful when replacing the memory module. Make sure that the
component side of the module faces in the same direction as the other modules in the LSI-11 system. The memory module, backplane, or
both can be damaged if the module is installed backwards.

2.2

WIRE WRAP GUIDELINES

A pin can have no more than two wire wraps. The starting address and

control and status register (CSR) address pins may require two wire
wraps. Always follow this procedure to wire wrap these pins.

1. Find out how many pins must be wrapped.
2. Each wrap must be daisy chained to its own ground.

3. Always put lower wraps on the pins first and then the upper wraps.

.

10

INSTALLATION

2.3

CONFIGURING THE MSV11-P

The jumpers on the MSV11-P memory module are divided into the following five groups.

‘Starting Address Jumpers
e CSR Address Jumpers
e Power Jumpers

Bus Grant Continuity Jumpers

e General Jumpers

Figure 2-1 shows the location of the five jumper groups, four of which are

enclosed in solid boxes and labeled. The remaining jumpers are classified
as general jumpers. The general jumpers are enclosed in dotted boxes.
Table 2-1 shows all the jumpers and their function.

2.3.1
Configuring the Module Starting Address
Each MSV11-P memory module installed in a system is jumpered for its
own starting address. To configure the starting address, perform the fol-

lowing steps.

1. Determine the starting address.

2. Determine the pins to be jumpered for the starting address.
3. Wire wrap the pins for the starting address.

2.3.1.1
Determining Starting Address — The memory module starting
address can be found if you know how much memory the system has be-

fore the replacement module. Change the byte value (how much memory

the system has) to a word value. This word value is the module starting

address (MSA).

:

2.3.1.2 Determining Pins to be Jumpered - Module starting address
jumpers consist of the following two groups:
1. First Address of the Range (FAR) - Selects the first 256K word
range address that the starting address falls in (Table 2-2, Part 1).
2. Partial Starting Address (PSA) - Selects which
8K boundry within a
specific multiple of 256K words the starting address
falls in (Table 22, Part 2).
|

At this point you know your module starting address (MSA) and yau must

find the FAR and PSA values. This is done in the following way.

1. Find the FAR value - This is done by looking at Table 2-2, Part 1 and

locating the address range the MSA falls in. The FAR value is the
first address of the selected address range. Associated with the FAR

value is a specific configuration of jumper pins (X, W, and V) that use

jumper pin Y (a ground pin).

|

msmtm'm

16K MOS CHIPS

BITS

(o
ROW O

POY
'6

'

7

BITS

|

6

BITS

BITS

lls

,

BITS

BITS

BITS

3

2

1

r

4

4’

BITS

|

WRITE WRONG

0

ROW 1

POTIL T 7
1611

6

[|s||a

ROW 2

fg‘

6

s

R

I

fle

s

BRI

aswa{

-

7

f’g‘ v

.

—

POV
17

a{}w;{

&

‘7

tasffva

15

acwz{ AP s
—
1

17

ROW 3 {

-

3

'

[la|]l3
R

P

T

.

ff

1

15

1

o

D

I T

1

13

12

|o

R

e

o]l

______

11

e

;_

. a‘}

Py

J1

——

10)

I

DAL

e || s

=

1

]

217

o181

:

L]

§

9

8

GRANT CONTINUITY

W1 AND W2 IN FOR

/O MACHINE, Q22/022

W11

w3

W10

w3

+12 VDD

5

w13

w12

+5 CR

Fid

W1 AND W2 OUT FOR

Q/CD AND 022/CD MACHINE

'

=21 23 229
S

1

e

-+

ap

oM

of

Lo—t=h J

|

{*E

o8
oC

‘

[CSR ADDRESS JUMPERS

’

LYY

Wa

Fe

POWER JUMPERS

o

*;:tw;

W18

K OYVTS

Wig

®

e~V

o9

e
;

16K MULTIPLE VOLTAGE DEVICES

.

°N

!

et

10

‘

oS

—

D SENNN Gy SUNU b SUNNNS I S

‘

versy

s1q

|

1

SR
.

JUMPERS

Xo

ets

T
R
e

;

rE24

S

'

TM = = ¥

]

(o
IS R
r=-

i

|]ls

:

g, 1 Fare

Poety
L--09

I

10 D 8

L2t

N (RN B SRS B U

R

gt

]
1

A

.

tlwoll

1

4

|

N

PING6TO 7

ROW LATCH

U

14

14

2

I

a2l

U

sl

rl]o

|tafla]l2]]1

e

el

]2

e

Sl I S I SN N NN b CNN B ON B

~

ROW 0

]

PARITY TESTING

MBO67-FA

SRS G NEUR 0 SENN 0 SUNNNO SN b SUNN b SN b UNNN ) E

BYTE

Ty

®&ITS

11

i
POWER JUMPERS FOR 16K MOS CHIPS

WITHOUT BATTERY BACKUP

—{"}—— POWER JUMPER IN FOR 16K CHIPS
«

—l}— POWER JUMPER IN FOR BOTH 84K 16K CHIPS

a 7148

64K SINGLE VOLTAGE DEVICES
NON-BAT BACK.UP

BAT BACKUP

w4

W4

W5

DECOUPLE +5

w5

DECOUPLE +5

wg
Wi3/wis

Figure 2-1

VOLTAGES

wi2

+5 CR
+5 VDD

wWigd

Memory Board

2.

Find the PSA value - This is done by inserting the MSA and FAR values into the equation PSA = MSA — FAR. After you do the subtraction, find Table 2-2, Part 2 and locate the PSA value. Associated

with the PSA is a specific configuration of jumper pins (P, N ML,

and T) that use jumper pin R (a ground pin). Examples 1 and 2 show

how to use the equation to jumper a module.

|

12

INSTALLATION

Table 2-1

MSV11-P Jumper Check List

Jumper
Name

or Pin

Jumper

Jumper

Wire

to Pin

in

Out

Wrap

Solder

Check

Function

Bto7

X

-

X

-

-

3to7

-

In — write wrong parity

-

X

-

-

2toY

In - disables wrong parity

-

-

X

-

-

2 to Y out - 22 bit machine

|

43to44

-

2to Y in- 18 bit machine

-

X

-

-

Single voltage MOS RAM access time

|
45t044

(150 ns device)

X

-

X

-

-

22t023

X

-

X

-

-

21t023

Not used

-

-

X

-

-

FtoH

-

Not used

-

X

-

-

|

f

Multiple voltage MOS RAM access

|

time (200 ns device)

F to H in - connected to force
starting address to 16K

|
F to H out - disables force function

X

-

X

-

-

13to15

X

-

X

-

-

~

3to9in-connected on 16K and

64K MOS chip
Connected on 16K and 64K MOS chip

4t010

-

-

X

-

-

14to16

-

-

Connected only on 64K MOS chip

X

-

-

Connected only on 64K MOS chip

W3

-

-

-

X

w11

-

-

-

Power for 16K chips,

-

X

W13

-

-

-

jumpers are in

-

X

-

W4

-

-

-

X

W5

-

-

-

-

Power for 64K chips,

X

-

jumpers are in

W9

-

-

-

X

W13

-

-

-

-

X

W15

-

-

-

-

X

-

W1

-

-

-

X

W2

-

-

-

-

X

-

A

-

-

X

B

-

-

-

-

X

-

-

C

-

-

D

X

~

-

-

-

X

-

E

-

-

-

X

-

-

X

-

-

W

X

-

-

-

X

-

-

-

Vv

-

-~

Y

X

-

-

-

-

X

-

-

P

-

-

X

-

-

N

~

-~

X

-

~

M

-

-

X

I

-

-

-

~

X

-

-

—

-

x

-

—

X

-

3t09

-

Bus grant continuity

CSR address

Starting address

INSTALLATION

Table 2-2

Starting Address Configurations (Part 1)

First Address Ranges (FAR)

|

Jumpers to Ground (Pin Y)

|

Decimal K Words

Octal K Words

000 - 248

0000 0000 - 0174 0000

256 -504

0200 0000 - 0374 0000

-

PinX

PinW

Pinv

(A21)

(A20)

(A19)

out
out

out
out

out
in

out

512-760

0400 0000 ~ 0574 0000

out

in

768 -1016

0600 0000 - 0774 0000

out

1024 - 1272

in

in

1000 0000 - 1174 0000

out
out

out
in

in

out

in

in

1280 - 1528

1200 0000 - 1374 0000

in
in

1526 - 1784

1400 0000 - 1574 0000

in

1742 - 2040

1600 0000
- 1774 0000

in

Table 2-2

-

Starting Address Configurations (Part 2)

Partial Starting Address (PSA)

Decimal

Octal

. K Words

|

K Words

Jumpers to Ground (Pin R)

PinP

Pin N

Pin M

Pin L

PinT

(A18)

(A17)

(A16)

(A15)

(A14)
out

0

0000 0000

out

out

~out

out

8

0004 0000

out

out

out

out

16

0010 0000

out

out

out

in

out

24

0014 0000

out

out

out

in

in

0020 0000

out

out

in

out

out

40

0024 0000

- out

out

in

out

in

48

0030 0000

out

out

in

in

out

56

0034 0000

out

out

in

in

in
out

-

0040 0000

72

0044 0000

80

0050 0000

88

0054 0000

96

00600000

-

-

-

in
-

32

64

out

in

out

out

out

in

out

out

in

out

in

out

in

out

out

in

out

in

in

out

in

in

out

out

104

0064 0000

out

in

in

112

0070 0000

out

in

in

~in

120

0074 0000

out

in

in

in

in

out

out

out

128

0100 0000

in

out

out

0104 0000

in

out

out

out

in

144

0110 0000

~in

out

out

in

out

156

0114 0000

in

out

out

in

in

160

0120 0000

in

out

in

out

out

-~

=

in
out

136

168

13

0124 0000

in

out

in

176

0130 0000

in

out

in

~in

184

0134 0000

in

out

in

in

192

0140 0000

in

200
208

0144 0000
0150 0000

in
in

216

0154 0000

224

0160 0000

232

240
248

in

in
out

|

in

out

out

out

in
in

out
out

out
in

in
-~ out

in

in

out

in

in

in

0164 0000

in

in

in

0170 0000
0174 0000

in
in

in
in

in .
in

-

-

out

o

in

in

out

out

- out

in

in
in

out
i

14

INSTALLATION

Example 1
The system has 512K bytes of memory. To jumper the memory module,
change this byte value (512K) to a word value (256K). This word value is
called the MSA.

Insert this value into the equation.

PSA = MSA — FAR
PSA = 256K — FAR

To find the value of FAR use Table 2-2, Part 1 to locate the address range
that the MSA value falls in. Take the first address of the address range

and insert nt into the equation.
PSA = MSA — FAR
PSA = 256K — 256K

PSA =0

Use Table 2-2, Part 1 - The FAR value equals 256K, this means wire wrap

pins VtoY.

Use Table 2-2, Part 2 - The PSA value equals OK th:s means no wire
wraps on pins P, N, M, L, and T.

Example 2
The system has 672K bytes of memory. To jumper the memory module
change this byte value (672K) to a word value (336K). This word value is

called the MSA.

Insert this value into the equation.

PSA
= MSA — FAR
PSA = 336K — FAR

PSA = 336K — 256K
PSA = 80K
Use Table 2-2, Part 1 - The FAR value equals 256K, this means wire wrap

pins Vto.

Use Table 2-2, Part 2 - The PSA value equals 80K, this means wire wrap

pins L to N and N to R.

2.3.1.3

Wire Wrap Pins for the Starting Address - Wire wrap the pins

according to the wire wrap procedures in Paragraph 2.2.

2.3.2

Control and Status Register (CSR) Jumpers

Each MSV11-P memory module has a control and status register. The

bus

master can read or write the CSR via the LSI-11 bus. The CSR is
a 16-bit

register whose address falls in the top 4K of system address space.

"

INSTALLATION

15

Each MSV11-P CSR is assigned to one of the 16 addresses shown in

Table 2-3. CSR addresses are assigned as follows.

1. Find out how many memory modules in your system have CSR registers.

|

|

2. List the memory modules sequential postion from the CPU.

- 3. The memory modules closest to the CPU have the lower module
starting address (MSA).
4. The memory module with the lowest MSA is assigned to the lowest

CSR address and jumpered according to Table 2-3.

5. The next sequential CSR memory module is assigned the next higher
CSR address.

|

|

Each memory module has four CSR iumpér pins (A, B, C, and D) which can
be daisy chained to pin E (the ground pin). The jumpers allow logic to de‘tect a specific CSR address that has been assigned to a ‘\CSR memory
module.

For example, assume the system has two memory modules with CSR registers. You are installing the third CSR memory. Refer to Table 2-3 and

find the column labeled module number three. The CSR jumper pin configuration is pin B wire wrapped to pin E. The memory module’s CSR address is 17772104 for large systems or 772104 for small systems.

Table 2-3

CSR Address Selection

Large System

Small System

Module

LSI-11 Bus

LSI-11 Bus

Jumper to Ground (Pin E)

Number

Address

Address

D

C

B

A

1

1777 2100

7721 00

out

out

out

out

2
3
4
5
6
7

1777 2102
1777 2104
1777 2106
1777 2110
1777 2112
1777 2114

7721 02
7721 04
7721 06
7721 10
7721 12
7721 14

out
out
out
out
out
out

out

out
out
out
in
in
in

in

out
in
in
out
out
in

in
out
in
out
in
out

in
in
in
in
in
in
in
in

out
out
out
out
in
in
in
in

out
out
in
in
out
out
in
in

out
in
out
in
out
in
‘cut
in

8
9
10
11

12
13
14
15
16

1777 2116
1777 2120
1777 2122
1777 2124

1777 2126
1777 2130
1777 2132
1777 2134
1777 2136

7721 16
7721 20
7721 22
7721 24

7721 26
7721 30
7721 32
7721 34
7721 36

“

|

in

in

16

INSTALLATION

2.3.3 Power Jumpers (Table 2-4)
The power jumpers are divided into the following two groups.

1. 16K multiple voltage devices (M8067-FA) with or without battery
backup

2. 84K single voltage devices (M8067-LA and M8067-KA) with or without battery backup

NOTE:

DIGITAL does not support battery backup.

Figure 2-1 shows all the pbssible power configurations. Figures 2-2

through 2-5 show the jumper conditions for 16K/64K devices (MOS memory chips), and the dual functions of pin 9, address or data.

2.3.4
Bus Grant Continuity Jumpers
To install W1 and W2 in your system, identify the backplane and refer to

Table 2-5 for the W1 and W2 configuration.

2.3.5

General Jumpers

The general jumper group is the catchall section. All
jjumpers and their
functions that have not yet been covered are descrnb‘ed in Table 2--6.

Table 2~4

Power Jumpers

16K Muitip!e Voltage Devices
Non-bat Backup
W3

Bat Backup

antages

W11

W3

-5

W10

W13

+12 VDD

W12

+5 CR

- 64K Single Voltage Devices

Non-bat Backup

Bat Backup

Voltages

w4

W4

W5

Decouple +5

W5

Decouple +5

W9

W12

W13/W15

+5 CR

W14

+5 VDD

INSTALLATION

e

CHARGE PUMP

16K

wos

16K

'

cHIP

fig

BYTE

3?;5

9 vce |

0

8
voD &

: |

,
+12V

1‘

|

|

R38 OUT

IS5V IS CR
w13

AABH

3%

,

for Byte 0 ROM Chips

R32 OUT

BA8H

“‘"""““"g??
oW

for Byte 1 ROM Chips
WA 7152

Triple Voltage MOS RAM without Battery Backup

Figure 2-2

)

—5V

ves it
W3
16K
MOS
CHiP

PUMP
C HAR GE PUMN

BBU
+12Vv BEUL
¥

i

'

8

BYTE

~

0

¢~
VOD
a

|

SUE——

w10

R38 OUT

+5V BBU (TM) +5 CR

waE

R39

AASH

for byte 0 ROM Chups

R32 OUT

=833

BABH

for byte 1 ROM Chips

=

Figure 2-3 Triple Voltage MOS RAM with Battery Backup

MA-7153

17

18

INSTALLATION

FORBYTEO
ROM CHIPS

+5V

=

vDD

D42

1

wis{

wa

1

1

w5

3

)

FORBYTE
1
3

ROM CHIPS

eR

(,l

£+ 1L 1L 11

» +5V CR

w13

J

+5V

'

<
GREEN LED

.

L

J.

I

T

* 45V

-

Figure 2-4

MA 7328

Single Voltage MOS RAM without Battery Backup

R

wia

VDD

1

+5V

o

R38

AA8H

R19

_

1

FORBYTEQ
ROM CHIPS

+5CR

FORBYTE 1

V

+*

o R33 o | ROMCHIPS
+5CR

W4

+5 BBU ——

W5

:
o

T

~

64Kk

MOS
CHIP

f_;[_J
1T

T

T

_4_

T

1

BYTE

I

)
,

+5VCR

A

GREEN LED
MA-7329

Figure 2-5

Single Voltage MOS RAM with Battery Backup

INSTALLATION

Table 2-5

Bus Grant Continuity

Backplane

|

Machine Type

W1

w2

H9270 (4 slot backplane)

Q/Q

in

in

H9275 (9 slot backplane)

Q22/Q22

in

in

H9273 (4 slot backplane)

Q/CD

out

out

H9276 (9 slot backplane)

Q22/CD

out

Table 2-6

~

out

General Jumpers

Pin

Numbers

Function

6to7

In - write wrong parity

8to7

In - disables wrong parity

2toY

2 to Y out - 22 bit machine
2 to Y in - 18 bit machine

43 to 44

In - single voltage MOS RAM access time (150 ns device)

45 to 44

In - multiple voltage MOS RAM access time (200 ns device)

22 t0 23

Not used

21t023

Not used

FtoH

F to Hin - connected to force starting address to 16K
F to H out
- disables force function

3to9

3 to 9 in - connected on 16K and 64K MOS chip

13to 15

Connected on 16K and 64K MOS chip

4to010

Connected only on 64K MOS chip

14 to 16

Connected only on 64K MOS chip

19

CHAPTER 3
F UNCTIONAL DESCRIPTION

3.1

INTRODUCTION

The MSV11-P memory modules interface with the LSI-11 bus. The
CPU
and DMA devices can become bus master of the LSI-11 bus to transfer or
obtain data from memory. The memory is always a slave to whatever
de-

vice becomes bus master. Figure 3-1 shows the CPU and DMA
dewces

connected to memory via the LSI-11 bus.

Devices that are ready to use the LSI-11 bus must gain control of the bus

through the arbitration that takes place in the CPU. The device that wins
the arbitration is able to use the bus as soon as bus signals BSYNC
and
BRPLY are negated. This device is now bus master and can initiate a bus
cycle. The types of bus cycles that can be pefformed are shewn m Table

3-1.

|

CPU

MEMORY

MEMORY

DMA
DEVICE

MA-7161

Figure 3-1

Table 3-1

Typical System

Summary of Bus Cycles

Bus Cycle
Mnemonics

Description

DATI

Data word input

DATO

Data word output

DATOB
DATIO

|

Data byte output

|

Function with Respect
to Bus Master
Read word
Write word

o

Data word input/output

Write byte

|

Read word, modify,
write word

DATIOB

Data word input/byte output

Read word, modify,
write byte

21

22

FUNCTIONAL DESCRIPTION

All bus cycles are divided into three sequential events.
® Address cycle
e Data cycle
e Bus cycle termination

3.2

LSI-11 BUS SIGNALS AND DEFIMITIONS

In order for the bus master to transfer data, it must generate the signals

shown in Figure 3-2. The slave device (memory) receives the signals and
initiates BRPLY. This starts a chain reaction to terminate the bus cycle.

Table 3-2 gives the signal names and definitions of the bus signals. Appendix A contains the flow diagram and signal sequences for DATO(B),

DATI, and DATIO(B).

|

BDAL 21-00L. ——o»

BBS7 L ——p
BWTBT L~

BSYNCL ——pf NTERFACE
BDOUT L —
BDIN L i
BRPLY L @

fi[“-

BDCOK L
MA-T7331

Figufé 3-2
Table 3-2

MSV11-P Memory Interface

LSI-11 Bus Signals and Definitions

Signal Name

Cycle

Bus Data

Address

Address Lines

Definitions
BDAL 21-00 L is received and decoded as an
address by the slave (memory).

(BDAL 21-00 L)
Data write

When the bus master does a memory write,

DATO(B) or DATIO(B), the data is transferred
on BDAL 15-00 L.
Data read

The bus master receives data on BDAL 15-00

L The validity of the data is noted by the
condition of BDAL 16 and 17. If BDAL 16 and
17 are active thenthe data on BDAL 15-00 L is

bad. If BDAL 16 and 17 are not active, then the
data on BDAL 15-00 L is good.

FUNCTIONAL DESCRIPTION

Table 3-2

23

LSI-11 Bus Signals and Definitions (Cont)

Signal Name

Cycle

Definitions

Bus Write/ Byte

Address

When BWTBT is active, a write operation is
enabled. When BWTBT is negated a read

(BWTBTL)

operation is enabled.
Data

If BWTBT is active during the data cycle, the
write operation that is performed is write byte.
Address bit O tells the logic what byte will be
modified.

If BWTBT is negated during the data cycle, the
write operation that is performed is write word.

Bus Bank 7
Select (BBS7 L)

Address

The bus master generates BBS7 during the
address cycle and removes the signal at the

end of the address cycle. The memory, on

receiving the signal changes the name to

BSEL 7 H. BSEL H (BBS7 L) implies the
address on the LSI-11 busis an l/O address. If
address bits 5-12 are correct for CSR, BSEL H
enables the CSR address decode logic and
inhibits the memory address decode from the

PROMs.

|

BSEL L (BBS7 H) implies the address on the
LSI-11 bus is a memory address. This allows
the memory address decode from the PROMs
and inhibits CSR address decode.

Bus Synchronize

Address

(BSYNC L)

B SYNC L is asserted by the bus master to
indicate that it has placed an address on the

LSI-11 bus.
Data

v

The transfer is in progress until B SYNC L is
negated. When memory receives B SYNC L it

does the following.
Latches address bits

- Latches row address bits
Latches column address bits
Sets read or WT request flip-flop.
Bus Data Input

(BDIN L)

Data

When asserted during

BSYNC L time, BDIN L
implies an input transfer with respect to the

current bus master and requires a response
(BRPLY) from the addressed slave (memory).
When the memory receives BDIN L it enables

the memory transmitters. This allows the data
to be sent out on the LSI-11 bus.

S

24

FUNCTIONAL DESCRIPTION

Table 3-2

LSI-11 Bus Signals and Definitions (Cont)

Signal Name

Cycle

Definitions

Bus Data Output

Data
“

is available on BDAL 15-00 L and that an

(BDOUTL)

BDOUT, when asserted, implies that valid data
output transfer, with respect to the bus master

device, is taking place. BDOUT L is deskewed
with respect to data on the LSI-11 bus. On
receiving BDOUT L the memory generates

write REQ L and if permitted, starts the
memory timing. Arbitration with refresh always

takes place with write or read request.

Bus Reply

,

|

The slave (memory) asserts BRPLY in re-

(BRPLY L)

sponse to BDIN L or BDOUT L. BRPLY L is

|

.

- generated by a slave device to indicate that it
will place its data on the BDAL lines or that it

willacceptdatafromthe BDAL lines according
to proper protocol.

Termination

|

- When the bus master receives BRPLY L, it
starts a chain of events that terminates the
transfer.

3.2.1

LSI-11 Bus Dialogues

The MSV11-P memory module responds to the following dialogues: DATI,

DATO(B) and DATIO(B). Table 3-3 explains which figure and table to use
with each dialogue.

-

Table 3-3 Dialogues to Perform Memory Data Transfers
Dialogue

DATO(B)

Figure

Table

DATI

3-4

3-3

3-4

DATIO(B)

3-5

3-6

3-5

FUNCTIONAL DESCRIPTION

25

ADDRESS CYCLE

|

ADDRESS BDAL <21-00>

BWTBT (DATO)

DEVICE

B SEL 7 NEGATED

-}

B SYNC

|

|

MEMORY

it

DATA CYCLE

DEVICE

B SYNC

-

BWTBT - YES IF DATOB

.

DATA — BDAL <15 00>

’

B DOUT

N

MEMORY

B RPLY

MA-7182

Figure 3-3

Table 3-4

Dialogue DATO(B)

Dialogue DATO(B) Cycle

Bus Master

Memory
Address Cycle

(BDAL) 21-00 L

Memory receives the address and accepts or rejects it according to how the board was jumpered. The memory board that
accepts the address generates MSEL provided BSEL 7 H is

negated.

(BBS7)L

BSEL 7 H negated enables the address decode logic to gener-

ate MSEL.

(BWTBT)L

Memory sets up to do a write cycle by preventing the setting of

the read request flip-flop.

(BSYNC)L

(BSYNC)L latches the following.

Address
Row address
Column address
Set write request flip-flop.
Data Cycle
Bus master takes

the address and

BBS7 L off-line.

(BSYNC)L
(BWTBT)L

(BSYNC)L is still active.
If BWTBT is active, it writes a byte.
If BWTBT is negated, it writes a word.

FUNCTIONAL DESCRIPTION

26

Table 3-4

Dialogue DATO(B) Cycle (Cont)
Memory

Bus Master

Data Cycle
Data is received from BDAL 15-00 L and two parity bits are

(BDAL) 21-00 L

generated. The 18 bits, 16 bits data and 2 bits parity, are inputs
to the MOS chips.

Memory receives (BDOUT)L and generates write request. Write

(BDOUT)L

request goes to the arbitration logic; if there is no refresh
request or refresh cycle in progress, write requestinitializes the

memory timing. The effects of timing enable the memory module
~ to write the data into the MOS chips and generate (BRPLY)L.

Termination of Bus Cycle
Bus master
receives (BRPLY)L

(BRPLY)L

and removes data
and (BDOUT)L from
the LSI-11 bus.
(BDOUT)L negated

Memory receives BDOUT negated and negates (BRPLY)L.

Bus master

(BRPLY)L is negated.

receives (BRPLY)L
negated and

negates (BSYNC)L
which terminates

the transfer.

ADDRESS CYCLE

ADDRESS BDAL <21-00>

BWTBT NEGATED (DATI)
-

DEVICE

B SEL 7 NEGATED

MEMORY

B SYNC

DATA CYCLE
BSYNC
BDIN

DEVICE

DATA BDAL <15-00>

MEMORY

BRPLY
I

MA-7163

Figure 3-4

Dialogue DATI

FUNCTIONAL DESCRIPTION

Table 3-5

27

Dialogue DATI Cycle

Bus Master

Memory

Address Cycle
(BDAL) 21-00 L

Memory receives the address and accepts or rejects
it, according to how the board was jumpered. The memory module

that accepts the address generates MSEL, provided BSEL 7 H
is

negated.

w

|

|

- BSEL7H negéted enables the address decode logic to gener-

(BBS7)L negated

ate MSEL.

(BWTBT)L negated

Mémcry sets up to set the read requeSt flip-flop.

(BSYNC)L

(BSYNC)L latches address and row and column address bits,

and sets the read request flip-flop. The read request goestothe
arbitration logic. If there is no refresh request or refresh cyclein

“progress, the read request initializes the memory timing.

Data Cycle

(BSYNC)L

(BSYNC)L is still active.

(BDIN)L

When memory receives (BDIN)L it enables the memory transmitters, for DAL 15-00, as soon as TRPLY is active. Then the
read data can be sent out on the LSI-11 bus.

The memory generétes (BRPLY)L as a result of receiving

Bus master
receives (BRPLY)L

BDIN L and TRPLY L.

indicating memory

will place its data
on the BDAL lines.

Bus master

Data read from memory goes to parity checking logic and is
latched and sent out through transceivers DAL 15-00. DAL 16

receives the data.

and 17 are Os if no parity error was detected, or 1sif a parity error

was detected.

Termination Cycle
(BDIN)L negated

when bus master
receives BDIN L
this causes

-

The signal (BDIN)L negated causes memory to negate

(BRPLY)L, which in turn prevents the transceivers from

. placing data on BDAL 15-00.

(BDIN)L to be
negated.

Bus master
receives (BRPLY)L

negated which

terminates bus
cycle.

(BRPLY)L is negated.

28 FUNCTIONAL DESCRIPTION

ADDRESS CYCLE

ADDRESS - BDAL <21-00>

(DATH
DEVICE li BWTBT
BSYNC

MEMORY

|

READ DATA CYCLE

e

|

8 DIN

DEVICE

B

DATA BDAL <10-00>

|

MEMORY

B RPLY

k

T——

e ————

,—..__._—-—--A
|

PAUSE

WRITE DATA CYCLE
B SYNC

|

BWTBT (DATOB)

-l

DEVICE

DATA - BDAL <15-00>

ol

B DOUT

|

MEMORY

B RPLY

:

MA-TIB4

Figure 3-5

Dialogue DATIO(B)

Table 3-6

Dialogue DATIO(B) Cycle

Bus Master

Memory
Address Cycle

(BDAL) 21-00 L

Memory receives the address and accepts or rejects it according to how the board was jumpered. The memory board that
accepts. the address generates MSEL, provided BSEL 7 H is
negated.

(BBS7)L

BSEL 7 H negated enables the address decode logic to gener-

ate MSEL.

(BWTBT) L negated

Memory sets up to set the read request flip-flop.

(BSYNC)L

(BSYNC)L latches address and row and column address bits,
and sets the read request flip-flop. The read request goes to
arbitration logic. If there is no refresh or refresh cycle in
progress, the read request starts the memory timing.

FUNCTIONAL DESCRIPTION

Table 3-6

29

Dialogue DATIO(B) Cycle (Cont)

Bus Master

Memary

Data Cycle (Read)
(BSYNC)L

(BSYNC)L is still active.

(BDIN)L

When memory receives (BDIN)L it enables the memory transmitter, for DAL 15-00, as soon as TRPLY is active. Then

data can
be sent out on the LSI-11 bus.

Bus master
receives (BRPLY)L

the read

" The memory%generates (BRPLY)L as a result of receiviné
BDIN L and TRPLY.

indicating memory
will place its data

on BDAL 15-00 L
and negates
(BDIN)L.

Bus master
receives the data.

Data read from memory goes to parity checking logic and is
latched and sent out through the transceivers DAL 15-00. DAL
16 is Os if no parity error was detected, or 1sifa parity error

detected.

was

Pause

(BDIN)L negated

Complete input transfer - remove data from BDAL 15-00
negate (BRPLY)L.

Bus master

(BRPLY)L is negated.

receives (BRPLY)L

negated and gets
ready to output
data.

Data Cycle (Write)

(BSYNC)L

(BWTBT)L

(BSYNC)L is still active.
Memory at this time uses the BWTRBT line to write byte or word

into memory.

(BWTBT)L active means write byte.
(BWTBT)L negated means write word.

Data output
BDAL 21-00 L

Memory receives the data BDAL 15-00 L and two parity bits

are generated. The 18 bits, 16 bits data, and 2 bits parity, are

- inputs to the MOS chips.

(BDOUT)L

Memory receives (BDOUT)L and generates write request, Write

request goes to the arbitration logic. If there is no refresh

request or refresh cycle in progress, write request initializes the
memory timing. The effects of timing enables the module, writes

the data into the MOS chips and generates (BRPLY)L.

30

FUNCTIONAL DESCRIPTION

Dialogue DATIO(B) Cycle (Cont)

Table 3-6

Bus Master

|

Memory

Termination of Bus Cycle

(BRPLY)L

Bus master
receives (BRPLY)L

and removes data
and (BDOUT)L from
the LSI-11 bus.

(BDOUT)L negated
Bus master

-

Memory receives BDOUT negated and negates (BRPLY)L.
(BRPLY)L is negated.

receives (BRPLY)L

negated and
negates (BSYNC)L,
which terminates

the transfer.

3.3

FUNCTIONAL DESCRIPTION OF MEMORY MODULE

All MSV 11-P memory modules have the logic functions shown in Figure 3-

6. The charge pump circuit is used only with the M8067-FA module (16K
chips). The functions shown in Figure 3-6 are discussed in detail in the
following paragraphs.

3.3.1

Xcvers (Transmit-Receives)

The Xcvers allow memory to transmit or receive: address, data, and con-

trol, via the LSI-11 bus. The LSI-11 bus signals are defined in Table 3-2.
3.3.2

Address Logic

1. The modules are jumpered for
a starting address and a CSR address.

2. MSV11-P memory modules receive all addresses from the LSI-11
bus.

3. The address decode logic on each memory module checks to see if
the board is selected (memory select) or the CSR is selected.
3.3.2.1

Board Selection Decode Logic - This consists of two PROMs

that monitor BDAL 21-14 and compare the address received against the

starting address jumpers. The PROMs are programmed to enable the log-

ic to generate memory select (MSEL) and row enables (NA 16/18 and NA

15/17). Table 3-7 shows the output of the PROMs programmed for module M8067-LA with a starting address of -zero. There are three different

types of PROMs.

|

|

|

1. MB067-LA F;ROMS programmed for 256K addresses per module
2.

M8067-KA PROMs programmed for 128K addresses per module

3. M8067-FA PROMs programmed for 64K addresses per module

FUNCTIONAL DESCRIPTION

31

DAL <15-00>

.
S

-

ADDBESS

-

CSR

LOGIC

i

LATCH

e

LATCH

LATCSRSEL® #

t

y

PARITY

PARITY

GENERATOR

CHECKER

LOGIC

LOGIC

PR ERR CLK

[

CSR SEL

¥

J

|

DATA
LATCH

ADDRESS

SWITCHES

igfiow

-E—('G-—-=

XCVERS

»|

- ADDRESS

- DATA

:

|

ADDRESSING

LOGIC

)

l
(L

MSEL ROW AND

COLUMN ADR.

f B

Y

MOS

-

MEMORY

o

ARRAY

RSYNC

B SYNC

BWTBT
B SEL 7

BDIN

|

XCVER

TIMING

CONTROL

AND

REFRESH CLOCK i

AND

ADDRESS

LATC

DATA LATCH L

LOGIC

B RPLY

v

A

CONTROL

BOOVT o

|

VDD

CHARGE
PUMP

,

COUNTER

e

-5V

CKT

MA-7180

Figure 3-6

Logic Functions

Table 3-7

PROM Output fer;MSOBT-LA (Starting Address Zero)

Octal Addresses

NA 18

NA 17

Row Enable

1

1

3

1

0

2

0

1

1

0

0

0

0177 7776
0140 0000

A

0137 7776

Generates

MSEL L

0100 0000

0077 7776
0040 0000

0037 7776
0000 0000

32

FUNCTIONAL DESCRIPTION

The address range of the two PROMs begins with the starting address

(jumper-selectable). The top limit of the memory module is then determined by what type of

PROMs are being used (e.g., 256K from starting

address).

3.3.2.2

MOS Memory Address Logic - Jumper consideration must be

taken for 16K or 64K MOS memories when loading the row and column
latches with the MOS RAM address. The logic also has a row latch used

for refresh addresses.

-

The MSV1 1-P‘famity of memory modules perform three basic operations.
e CSR read/write transfers

e Memory read/write transfers
e Refresh cycles

‘When CSR transfers take place, the row select signals (RAS 0-3) and
column select signals (CAS 0-3) are inhibited (Figure 3-7).
When read/write cycles take place, the PROM sends the row enable signals (RAS 0-3) to the MOS memory array in order to select the proper

row. All columns (CAS 0-3) are always selected (Figure 3-7). First the
row address, then the column address is loaded into internal registers in

the MOS RAM chips. One 18 bit location in memory is now selected.

When refresh cycles take place, the column select logic is inhibited. Ali
rows are selected (RAS 0-3). The refresh row address is loaded into an

internal register in the MOS RAM chips (Figure 3-7), and that address is
refreshed.

3.3.2.3

CSR Address Logic — Memory receives a CSR address and

compares (XOR) DAL 1-DAL4 with the CSR jumpers. If there is a match,

CSR selected (CSR) is generated. CSR generates MSEL, which enables a
read/write request to start the memory timing. RAS and CAS are inhib-

ited; therefore, no memory addressing occurs.
3.3.3

CSR Write (Figure 3-8)

|

CSR address and signals BBS7 and BWTBT are received by the memory. If

the CSR address matches the CSR jumpers, CSR SEL and MSEL are generated. When BSYNC is received, the address and CSR SEL are latched,
and the WT REQ flip-flop is set. During the data cycle the memory re-

ceives the data to be stored in the CSR register. Then, BDOUT is received
and write request starts memory timing. The signal LAT CSR SEL selects

the received data to be passed through the multiplexed inputs to the CSR
register. The CSR clock logic generates the CSR clock pulse which, in
turn, loads the CSR register.

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FUNCTIONAL DESCRIPTION
33

34

FUNCTIONAL DESCRIPTION

a BUS

80AL <15:00>|

|

j

l
|

I

V
WRT

REQE

B SYNC

|

|

START

|

« MEMORY
TIMING

|

|

|

BDAL <12:00>
|

DAL

|

|

|

0 2>

»

|

q

|

|V LINES

< 511>
<14, 15>
o

RPLY

-

|

w— RD R

'

|

-

TM

CSR Write

.l

3.3.4

CSR Read (Figure 3-9)

CSR address, BBS7, and BWTBT negated are received by the memory. If
the CSR address matches the CSR jumpers, CSR SEL and MSEL are generated. When BSYNC is received, the address and CSR SEL are latched,

and the RD REQ flip-flop is set, starting the memory timing. As soon as
TRPLYis generated, the contents of the CSR is latched. Memory receives
BDIN L, which enables the memory to transmit the latched CSR data onto

the LSI-11 bus.

3.3.5

Memory Array

The MSV11-P family of memory modules uses early writes. Early writes
are achieved by a write going low prior to CAS going active. Data in is
strobed into the MOS chips by CAS going active.

The following MOS RAM chips are used inthe MSV11-P memc}ry modules
M8067-LA

(64K chips) - A fully populated module that consists of
four rows of MOS RAM chips (512K bytes)

c

|

*

— REFRESH

Figure 3-8

RD REQ

L "

7 LINES

l

|

LOGIC

—_—

|

B RPLY

)

€SR CLDCK

|

B DOUT

MEMORY

REFRESH

|

|
cpu

f

\__TIMING

;

FUNCTIONAL DESCRIPTION

35

mmmmmmmmmwmmmmmmmmm

BDAL <21:00>

LATCHED CSR SEL

CSR SEL
E35

E18

ADR

—!

B SYNC

M SEL

_

RD REQ

DECODE

START
MEMORY

TIMING

E39
.

\_ TIMING

MEMORY

E2, E11

B RPLY

CPU

'

.

L=
'

RPLY
LOGIC

———— RD REQ

.
[®— REF

g TIM 190

TRPLY

N
§§§j ggg

le— LATCHED CSR SEL

‘sa

<

-

=

E54, £48

=

CSR

g

LATCH

*—-

<

E15, E10, E16, E3
CSR REG

MA 9226

Figure 3-9

CSR Read

M8067-KA

(64K chips) - A half populated module that consists of
two rows of MOS RAM chips (256K bytes)

M8067-FA

(16K chips) - A fully populated module that consists of
four rows of MOS RAM chips (128K bytes)

The MOS RAM chips used in the M8067-LA and M8067-KA memory mod-

ules are dynamic random access memory circuits organized as a 65,536

by 1 bit (Figure 3-10). The MOS chips used in the M8067-FA memories are
dynamic random access memory circuits organized as a 16,384 by 1 bit

(Figure 3-11).
3.3.6

Timing and Control Logic

The memory responds to the asynchronous read/write commands or the
synchronous refresh cycle that takes place every 14.5 us. All requests go
to the memory timing lockout gate. When timing lockout is negated, the
request goes to arbitration and the winner gains control of the memory

timing (Figure 3-12).

36

FUNCTIONAL DESCRIPTION

PIN OUT

|

PN T [

PIN FUNCTIONS

—

V

ping2 [

sax

wmos

D 13A

a5 L

CHIP

124,

AAsa [

A6 [
A, 7 E

zin

] 14 Dout
12 A

] 1A
;

|

RAS

2 C
3 [C

RAs

4[]

4

DATA OUT

ROW ADDRESS STROBE

Vee

POWER (+5V)

NOT USED

GND

j 9A, |
MA 7332

64K MOS RAM Chip

'K

MOS

] 15

CAS

] 14

Doyr

10O 13 A

A;

6 (]

1 11

A,

7007

O 10

A

Voo

8 [

] 9

Ve

A

PIN NAMES

Ao-Ag

'ADDRESS INPUTS

CAS

COLUMN ADDRESS STROBE

Din

DATA IN

Dout

DATA QUT

RAS

ROW ADDRESS STROBE

WRITE

READ/WRITE INPUT

Vg

POWER (=5V)

Vee

POWER (+5V)

Voo

POWER (+12V)

Vss

GROUND

Figure 3-11

DATA IN

READMWRITE INPUT

Ve

PIN CONNECTIONS

Din

.

WRITE

'

WRITE

COLUMN ADDRESS STROBE

3 10 A,

Veec 8 C

Figure 3-10

ADDRESS INPUTS

TAS

] 15 TAS

WRITE3 [
|

Ao A,

] 18 v

MA-7151%

16K MOS Chip

FUNCTIONAL DESCRIPTION

37

COMMAND
DECODER

RWTBT

,

RD

| FUNCT
LOGIC

RWTBT

WRITE

‘

) FUNCTION
LOGIC

HANDLER

WRITE REQ L

RDREQL —

OF

— MEMORY

REQUEST

ARBITRATION

P LATCHED ROW ADR TO MOS CHIP

WAKE UP

ARBITRATION

'\
.\

MEM
GO | memoRy |

/'

TIMING

c

> RAS - ROW ADDRESS STROBE

0

——= CAS - COLUMN ADDRESS STROBE

;‘

A
o
‘

—

TIM 0 H i)} MEMORY

|| TRPLY - WILL GENERATE
BRPLY

% RO CLR — RD END
8 WT END

———# DATA LATCH
-

TIM 160 H ————C) LOCKOUT

.

:

b= CSR PR CLK

$t ENABLES CLEARING OF FLIP-FLOPS

TIM 250 H ———C}} LOGIC

REFCLK _____ IREFRESH
145 us

CIRCUITRY

WA 715%

Figure 3-12

Timing and Control

3.3.7 Parity Logic
|
The parity logic performs the following two functions.
1.

Parity generation - when the bus master is doing
a DATO(B)

2. Parity checking - when the bus master is doing a DATI

3.3.7.1

Parity Generation - The data received from the bus master on

the LSI-11 bus (DALOO- 15) goes to the parity generators (Figure

3-13).

The low byte parity generator generates odd parity (PDI 16 H). The
high
byte parity generator generates even parity (PDI 17
H).

CSRO2 enables the diagnostic to force wrong parity. This enables the

agnostic to check out the parity logic.

di-

38

FUNCTIONAL DESCRIPTION

£a7

DAL 00 H

DAL 01 H

DAL 02 H
DAL 03 H
DAL
04 H

—

5
&- -

=

DAL 08 H -

DAL 09 H

10 H
DAL

£53

Ev

5

PDI 17 H

o

DAL 11 H —
DAL 12 H

|

13 H
DAL

DAL 08 H ——i

DAL 14 H

DAL 06 H et

DAL 07 H

|

000

DAL 15 H

p—2—PDI 16H

000 p—5—

—————————
D

CSR 02 H

6

£

7

7

-0

DAL 16

8

Figure 3-13

MA-T187

Parity Generators

3.3.7.2 Parity Checker - The MSV11-P memory modules detect parity
errors, report parity errors, and save the address of the parity error in the
CSR register. Parity detection logic always expects byte O to have an
even number of one bits and byte 1 to have an odd number of one bits. If
this does not happen, T PAR ERR L is generated (Figure 3-14).

P‘arity reporting is done if the program has set CSR bit O, the parity error

enable bit, T PAR ERR L, and RDIN negated. This allows BDAL 16 and
BDAL 17 to be sent out on the LSI-11 bus to flag a parity error.
Parity address is saved in the following way.

e After the data is read from memory, it goes to the parity checkers
and a holding register.

e When the data is latched, the signal CSR CLK is generated if there is

a parity error (Figure 3-14).
e CSR CLK latches the address in the CSR register.

CSR cycles or refresh cycles inhibit the parity logic.
3.3.8

Refresh

The MSV11-P memory modules are MOS RAM chips which are refreshed
every 2 ms. The logic refreshes a row at a time; 128 rows are refreshed in
|
a 2 ms period.
Figure 3-15 shows that a refresh timer generates a pulse every 14.5 us.
This pulse, called REF CLK, does the following.
e Generates a refresh request
e Increments the refresh address CTR

The address counter produces row address bits A1 through A7 for 16K
chips, and A1 through A8 for 64K chips.

FUNCTIONAL DESCRIPTION

LAT SEL €SR H—-——-J’

REF H—

39

x

E57

DO OO H mmef

EV e

DO 01 H —

‘

DO 02 H ———

DO 03 H ——

DO04 H——

BYTEO

DO 05 H ——

DO 06 H —

DO 07 H ——

PDO 16 H —f

00D

|

}

£63

DO 08 H

v

DO 10 H s

DO 11 H =

PAR ERR EN Dememn

TIM 160 H

T PAR ERR L
'

BYTE 1

DO 12 H ~——d

~

=

DO 13 H e

|

L/

‘

- BDAL
17

DO 14 H ——

DO 15 H =
PDO 17 H e

0DD

£13

3CR

T PAR ERR

eI

CLR

CSR CLK L

o>

£15

DATA LATCH

|

516

BLK END

Figure 3-14

MA-7156

Parity Checkers

VDD +12V

145 ys

ReFREsH

+12V
IPULSE

RECTIFIER

1V

;ggws?a;

TIMER

5v

LATO

—5V OUTPUT

FILTER
CAPACITORS

REF CLK

=

Figure 3-15

REFRESH
ADDRESS
CTR

w3

REF <AO-A6> H
——=a» REFRESH ADDRESS
TO ADDRESS LOGIC

o REF CLK

Refresh Logic and Charge Pump Circuit

MA.-7158

-FUNCTIONAL DESCRIPTION

40

3.3.9

Charge Pump Circuit

The purpose of the charge pump circuit is to generate a filtered regulated
—5 V. The M8067-LA and M8067-KA modules, which use 64K chips, do

not require —5 V. If W3 is removed (Figure 3-15), then the memory modules mentioned above will not receive —5 V. The M8067-FA modules,
which use 16K chips, require —5 V; therefore, W3 must be installed.

The —5 V is generated in the following manner (Figure 3-16). The output

of the timer is a + 12 V pulse that occurs every 14.5 us. The + 12 V pulse

goes to a rectifier whose output is —11 V. A three terminal regulator
takes the — 11 V and produces a regulated —5 V. The —5 V regulator
output goes to module pin connection BK1, which is connected to BL1 on

the backplane. Filter capacitors receive the —5 V and pass the filtered
—5 V to the output, if W3 is installed.

3.4

CONTROL AND STATUS REGISTER (CSR) BIT ASSIGNMENT

The control and status register (CSR) in the MSV11-P allows program
control of certain parity functions,
and contains diagnostic information if a

parity error has occurred. The CSR is assigned an address and can be

accessed by a bus master via the LSI-11 bus. Some CSR bits are cleared
by assertion of BUS INIT L. This signal is asserted for a short time by the
processor after system power has come up, or in response to a reset in-

struction.
The CSR bit assignments are shown in Figure 3-17 and are described as follows.
'
|
Bits 1, 3, 4, 12, and 13

- These bits are not used and are always
read as logical zeros. Writing into these

bits has no affect on the CSR.
Bit O

|

Parity Error Enable - If a parity error

occurs on a DATI or DATIO(B) cycle to
memory, and bit O is set = 1, then BDAL

16 L and BDAL 17 L are asserted on the

bus simultaneously with data. This is a
read/write bit reset to zero on power up

or BUS INIT.

15

14

13

12

11

10

09

08
A1d

07

06

05

04

03

02

NOT | NOT | o475 | A16 | a15 | OR | OR | OR | ORr | NOT | NOT

USED JUSED

PARITY

A21 | A20 | A19 | A18

L

A

ERROR

EXTENDED

01

| A13 | A12 | A1

NOT

|USED |USED

P

USED

|

PARITY

ERROR ADDRESS

;

ERROR

WRITE

CSR READ

WRONG

ENABLE

PARITY

Figure 3-16

CSR Bit Allocation

00

ENABLE
MA.-7169

FUNCTIONAL DESCRIPTION

Bit 2

41

Write Wrong Parity - If this bit is set = 1
and a DATO or DATOB cycle to memory
occurs, wrong parity data is written into

the parity MOS RAMs. This bit can be
used to check the parity error logic as
well as failed address information in the

CSR. The following diagnostic is appli-

cable.
e

With bit 2 set, writes entire memory

with any pattern.

e

Read first location in memory, if bit O
of the CSR is set, then a parity error

indication is detected on the LSI-11
bus, and the failed address (location

0) is stored in the CSR.
*

Reads the CSR and obtains the failed

address,

CSR

bit

14 = 0 implies
A11-A17 on CSR bits 5-11. CSR bit
14 = 1 implies A18-A21 on CSR bits

5-8. Bit 2 is a read/write bit reset to
zero on power up or BUS INIT.

Bits 05-11

Error Address Bits - If a parity error occurs on a DATI or DATIO(B) cycle, then

A11-A17 are stored in CSR bits 5-11 and

bits A18-A21 are latched. The 128K word
machines

(18-bit

address)

require

only

one read of the CSR register to obtain the

failed address bits. CSR bit 14 = 0 allows

the logic to pass A11-A17 to the LSI-11
bus. A 2048K word machine (22-bit ad-

dress) requires two reads. The first read
CSR bit 14 = 0 sends contents of CSR

bits 5-11. Then the program must set CSR
bit 14 =

1. This enables A18-A21 to be

read from CSR bits 05-08.

The parity error addresses locate the parity error to a

1K segment of memory.

These are read/write bits and are not reset to zero via power up or BUS INIT. If a

second parity error is encountered, the
new failed address is stored in the CSR.

Bit 14

Extended CSR Read Enable - The use of

this bit was explained in the error address

description.

42

FUNCTIONAL DESCRIPTION

Bit 14 = O, always for 128K word machine
Bit 14 = O, first read on 2048K word machine
- Bit 14 = 1, second read on 2048K word
machine
Bit 15

Parity Error - This bit set indicates that a

parity error has occurred. The bit then

turns on a red LED on the module. This
provides visual indication of a parity error.
Bit 15 is a read/write bit. It is reset to zero

via power up or BUS INIT and remains set

‘unless rewritten or initialized.

CHAPTER 4

MAINTENANCE

4.1

GENERAL

The maintenance procedures in this chapter apply to both versions

of the
MSV11-P memory module. To perform corrective maintenance
on this
product, the user must understand basic operation of the MSV11-P
mem-

ory module as described in the previous chapters. This
knowledge, to-

gether with diagnostic testing knowledge, should help the user isolate
MSV 11-L malfunctions.

CAUTION: ALL power must be off before installing or removing modules.
Always be sure the component side of the memory faces in the
same direction as the other modules within the LS/ system.

4.2

PREVENTIVE MAINTENANCE

Preventive maintenance pertains to specific tasks, performed at intervals,

to detect conditions that may lead to performance deterioration or
malfunction. The following tasks can be performed along with other scheduled preventive maintenance procedures for the LS| computer system.

1.

Visual inspection

2.

Voltage measurements

3. Diagnostic testing
4.2.1

Visual Inspection

Inspect the modules and backplane for broken wires, ccnnectors or other

obvious defects.
4.2.2

Power Voltage Check

Once primary power has been turned on, check the dc power voltage at

the backplane (Table 4-1).

44

MAINTENANCE

Table 4-1

Voltage Pins

Voltage
+

Backplane Pins

5V

+ 5VvBBU

AA2, BA2, BV1, CA2, and DA2

Single Voltage

AV1 and AE1*

MOS RAMs

or

AV1 and AS1*
+ 5V

AA2, BA2, BV1, and CA2

+12 V

AD2 and BD2

+ 5V BBU

AV1 and AE1

+12 V BBU

AS1

Multi Voltage

|

MOS RAMs

*Check backplane voltages to ensure proper configurations.

4.2.3

Diagnostic Testing

Memory diagnostic programs are available from DIGITAL for testing the

MSV11-PF/PK/PL memory modules.
For fault isolation in 22-bit systems and 18-bit systems use the following

diagnostics.

MAINDEC-11 CVMSA

(22-bit system)

MAINDEC-11 CZKMA

(18-bit system)

In most cases a bad memory module can be detected by using the error
printout and program listing.

Detailed operating instructions and program listings are included with
each diagnostic software kit.

4.3

DIGITAL’S SERVICES

Maintenance

services

can be

performed by the user or by

DIGITAL.

DIGITAL’s maintenance and on-site services are described in Chapter 1 of

the Microcomputer Processor Handbook (EB-18451-20).

APPENDIX A

SIGNAL SEQUENCES

Figures A-1, A-2, A-3, and A-4 prev:de the flow diagram and. s:gnal se-

quences for DATO(B), DATI, and DATIO(B).

45

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APPENDICES

SYNC H D2

:

RASO L

'

BN
N
ROW

WTBTO L
DATO REQ L

)O(

/

COLUMN

u

AN

/

N

/

LOCKOUT L

|

\

REPLY H

4"‘

X

NEW MEMORY

CYCLE ENABLED

//

DATA IN

U

/

CASO L
MUX <A1-A7> H

47

\

WRITE DATA

X
MR 0352
MA 727

Figure A-2

DATO(B) Signal Sequence

SYNCH _..//
RASO L

\

/

CASO L

A

MUX<A1:A7> H

y4d

COLUMN

DATI REQ L

LOCKOUT L
RPLY H

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4

|

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—

y

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*

DATA OUT

/{ NEW MEMORY

CYCLE ENABLED

BUS MASTER READS DATA

X

LATCHED DATA VALID
MR 0351
MA-7219

Figure A-3

DATI Signal Sequence

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SN 371040

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MSV11-P USER GUIDE

|

|

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