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Document:	MS7AA Memory Technical Manual
Order Number:	EK-MS7AA-TM
Revision:	001
Pages:	82
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MS7AA Memory
Technical Manual

Order Number EK–MS7AA–TM.001

The MS7AA memory module is designed for computer systems built around the LSB bus. The
module can be configured in incremental storage capacities ranging from 64 Mbytes to 2 Gbytes.

digital equipment corporation
maynard, massachusetts

First Printing, November 1992
The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.
The software, if any, described in this document is furnished under a license and may be used or copied only
in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies.

The following are trademarks of Digital Equipment Corporation:
Alpha AXP
AXP
DEC
DECchip
DEC LANcontroller
DECnet

DECUS
DWMVA
OpenVMS
ULTRIX
UNIBUS
VAX

VAXBI
VAXELN
VMScluster
XMI
The AXP logo

OSF/1 is a registered trademark of the Open Software Foundation, Inc.

FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency energy. The equipment has been type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection
against such radio frequency interference when operated in a commercial environment. Operation of this
equipment in a residential area may cause interference, in which case the user at his own expense may be
required to take measures to correct the interference.

Contents

Preface ............................................................................................................................................ vii
Chapter 1
1.1
1.1.1
1.1.2
1.1.3
1.2
1.3
1.4

Major Sections ............................................................................................................... 1-2
Memory Interface Controller ................................................................................. 1-2
Memory Data Controller ........................................................................................ 1-3
DRAM Arrays ......................................................................................................... 1-3
Internal Buses ............................................................................................................... 1-3
Transactions .................................................................................................................. 1-3
Refresh ........................................................................................................................... 1-3

Chapter 2
2.1
2.2
2.2.1
2.2.2
2.2.2.1
2.2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9

Memory Data Controller

MDC Data Paths ........................................................................................................... 3-1
MDC Transactions ....................................................................................................... 3-1
Read and Wrapped Read Transactions ................................................................ 3-1
Write and Wrapped Write Transactions ............................................................... 3-2

Chapter 4
4.1
4.2
4.3

Memory Interface Controller

Components ................................................................................................................... 2-1
Logic Elements .............................................................................................................. 2-1
Command Decode Logic ......................................................................................... 2-2
Address Decode Logic ............................................................................................. 2-2
Node Space CSR Transactions ........................................................................ 2-2
Memory Space Transactions ............................................................................ 2-3
DRAM Address Logic ............................................................................................. 2-3
DRAM Control Logic .............................................................................................. 2-3
MIC Data Path Logic .............................................................................................. 2-3
Data Wrapping ....................................................................................................... 2-4
Refresh Logic .......................................................................................................... 2-4
Self-Test Logic........................................................................................................ 2-5
LSB State Machine Control Logic ......................................................................... 2-5

Chapter 3
3.1
3.2
3.2.1
3.2.2

Overview

Memory Organization

Memory Capacity .......................................................................................................... 4-1
Memory Banking ........................................................................................................... 4-1
Memory Interleaving .................................................................................................... 4-2

iii

Chapter 5

LSB Memory Signals

Chapter 6

Memory Transactions

6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.3
6.4

Memory Read Transactions .......................................................................................... 6-1
LSB Stalled Read Transactions ............................................................................. 6-1
Module Stalled Read Transactions ........................................................................ 6-1
Memory Write Transactions ......................................................................................... 6-1
LSB Stalled Write Transactions ............................................................................ 6-2
Module Stalled Write Transactions ....................................................................... 6-2
Memory Transaction Ordering ..................................................................................... 6-2
ECC Conversion ............................................................................................................ 6-2

Chapter 7
7.1
7.2
7.3

Node Space Base Addresses ......................................................................................... 7-1
Bit Access Type Acronyms ............................................................................................ 7-2
Register Descriptions .................................................................................................... 7-3
LDEV—Device Register ........................................................................................ 7-4
LBER—Bus Error Register .................................................................................... 7-5
LCNR— Configuration Register ............................................................................ 7-7
IBR—Information Base Repair Register ............................................................... 7-8
LBESR0-3—Error Syndrome Registers................................................................ 7-9
LBECR0,1—Error Command Registers .............................................................. 7-10
MCR—Memory Configuration Register .............................................................. 7-12
AMR—Address Mapping Register ....................................................................... 7-14
MSTR0,1—Memory Self-Test Registers.............................................................. 7-17
FADR—Failing Address Register ........................................................................ 7-20
MERA—Memory Error Register A ...................................................................... 7-21
MSYNDA—Memory Error Syndrome Register A ............................................... 7-24
MDRA—Memory Diagnostic Register A ............................................................. 7-25
MCBSA—Memory Check Bit Substitute Register A .......................................... 7-28
MERB—Memory Error Register B ...................................................................... 7-29
MSYNDB—Memory Error Syndrome Register B ............................................... 7-31
MDRB—Memory Diagnostic Register B ............................................................. 7-32
MCBSB—Memory Check Bit Substitute Register B .......................................... 7-34

Chapter 8
8.1
8.2
8.3
8.3.1
8.3.2

Error Conditions

Memory-Related LSB Errors........................................................................................ 8-1
Memory-Specific Errors................................................................................................ 8-1
Error Syndrome Decoding ............................................................................................ 8-1
Quadword Memory Error Syndrome Decoding ..................................................... 8-2
Longword Memory Error Syndrome Decoding ..................................................... 8-4

Chapter 9
9.1
9.2
9.3

Registers

Self-Test

Self-Test Report............................................................................................................ 9-1
Self-Test Modes............................................................................................................. 9-1
Self-Test Performance................................................................................................... 9-2

Figures
1-1
4-1
4-2
4-3
5-1
5-2

Memory Module Block Diagram ................................................................................... 1-2
Two-Way Interleave of a 128-Mbyte DRAM Array..................................................... 4-2
Eight-Way System Interleave of Four 128-Mbyte Memory Modules......................... 4-3
Interleaving Different Size Memory Modules ............................................................. 4-4
LSB D<127:0> During Command/Address Cycles ...................................................... 5-1
LSB D<127:0> During CSR Data Cycles ..................................................................... 5-2

Tables
1
2
3
2-1
2-2
2-3
3-1
4-1
5-1
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
8-1
8-2
9-1

Definitions of Terms Used in This Document ............................................................... ix
DEC 7000/10000 and VAX 7000/10000 Documentation ................................................ x
Related Documents ........................................................................................................ xii
LSB Commands for Memory Operations ..................................................................... 2-2
LSB Data Wrapping ...................................................................................................... 2-4
Refresh Rates at Various LSB Cycle Times ................................................................ 2-4
MDC Wrap Ordering ..................................................................................................... 3-2
Memory Array Capacity ............................................................................................... 4-1
LSB Memory Signals .................................................................................................... 5-2
LSB Node Space Base Addresses ................................................................................. 7-1
Access Types of Register Bits ....................................................................................... 7-2
Memory Module Registers ............................................................................................ 7-3
LDEV Register Bit Definitions ..................................................................................... 7-4
LBER Register Bit Definitions ..................................................................................... 7-6
LCNR Register Bit Definitions ..................................................................................... 7-7
IBR Register Bit Definitions ........................................................................................ 7-8
LBESR Register Bit Definitions ................................................................................... 7-9
LBECR Register Bit Definitions ................................................................................ 7-10
MCR Register Bit Definitions .................................................................................... 7-13
AMR Register Bit Definitions ..................................................................................... 7-14
MSTR Register Bit Definitions .................................................................................. 7-17
Memory Error Address Segments ............................................................................. 7-18
FADR Register Bit Definitions ................................................................................... 7-20
MERA Register Bit Definitions .................................................................................. 7-21
MSYNDA Register Bit Definitions ............................................................................. 7-24
MDRA Register Bit Definitions .................................................................................. 7-25
MCBSA Register Bit Definitions ................................................................................ 7-28
MERB Register Bit Definitions .................................................................................. 7-30
MSYNDB Register Bit Definitions ............................................................................. 7-31
MDRB Register Bit Definitions .................................................................................. 7-32
MCBSB Register Bit Definitions ................................................................................ 7-34
Quadword Error Syndrome Table ................................................................................ 8-2
Longword LSB Error Syndrome Table ........................................................................ 8-5
Memory Self-Test Times............................................................................................... 9-2

Preface

Intended Audience
This manual describes the bit-level hardware functions of the MS7AA
memory module used in computer systems designed around the LSB bus.
It is written for developers of system and application software. It assumes
machine level programming knowledge and familiarity with the operating
system.

Document Structure
The material is presented in nine chapters.
•

Chapter 1, Overview, presents an overall introduction to the MS7AA
memory module.

•

Chapter 2, Memory Interface Controller, describes the hardware
interface to the LSB bus and discusses the functions of the logic elements implemented on the MIC chips.

•

Chapter 3, Memory Data Controller, describes the interface between the MIC chips and the dynamic random access memory array of
the memory module.

•

Chapter 4, Memory Organization, describes how memory is organized on a single module or multiple modules and explains how memory
performance is enhanced by dividing the DRAMs into two banks and
using interleaving techniques.

•

Chapter 5, LSB Memory Signals, describes the signals used by the
memory module to communicate with the LSB bus.

•

Chapter 6, Memory Transactions, describes how read and write operations are executed on the memory modules.

•

Chapter 7, Registers, lists the LSB-required and memory-specific registers and provides bit-level functional descriptions of each register.

•

Chapter 8, Error Conditions, describes the two categories of errors
detected by the memory module and explains how errors are reported
in associated error syndrome registers.

•

Chapter 9, Self-Test, tells when a memory module performs a self-test
and gives a brief overview of functions that the memory self-test provides.

vii

Conventions Used in This Document
Results and Operations
Results of operations termed UNPREDICTABLE must not be used by software.
Operations termed UNDEFINED do not cause the processor to hang, that
is, reach a state from which there is no transition to a normal state of instruction execution. Nonprivileged software cannot invoke UNDEFINED
operations.
Register and Bit Designations
Certain conventions are followed in register descriptions and in references
to bits and bit fields:
•

Registers are referred to by their mnemonics, such as MCR register.
The full name of a register (for example, Memory Configuration
Register) is spelled out only at the top of the register description
page, or when the register is first introduced.

•

Bits and fields are enclosed in angle brackets. For example, bit <31>
and bits <31:16>. For clarity of reference, bits are usually specified
by their numbers or names enclosed in angle brackets adjacent to the
register mnemonic, such as AMR<31:17> or AMR<MADR>, which are
equivalent designations.

•

When the value of a bit position is given explicitly in a register diagram, the information conveyed is as follows:
Bit Value
Designation

viii

Meaning

Reads as zero; ignored on writes.

Reads as one; ignored on writes.

Does not exist in hardware. The value of the
bit is unpredictable on reads and ignored on
writes.

•

Fields noted as must be zero (MBZ) must never be filled by software
with a nonzero value.

•

The entry in the type column of a register description table may include the initialization value of the bits. For example, entry "R/W, 0"
indicates a read/write bit that is initialized to 0.

Terminology
Table 1 gives the definition of terms and some mnemonics used in this
document.

Table 1 Definitions of Terms Used in This Document
Term

Definition

Bank

Smallest group of DRAMs that can be interleaved. A bank consists of one
or more strings.

Block

64 bytes of data within naturally aligned boundaries.

DDB

DRAM data bus. The 576-bit bidirectional data bus that interfaces between the DRAM chips and the MDC gate arrays.

LSB

The system bus.

MDB

Memory data bus. The 144-bit bidirectional data bus is the interface between the MIC gate arrays and the MDC gate arrays.

MDC

Memory data controller. Chips that buffer data between the MIC and the
DRAM arrays.

MIC

Memory interface controller. The interface of the memory subsystem to the
LSB.

String

The smallest group of DRAMs (144 1/4M x 4) needed to store and retrieve
64 bytes of data per LSB transaction. In some array implementations, the
number of banks and strings can be equal, while in others there may be
more strings than banks.

32-bit ECC

Synonymous with longword ECC.

64-bit ECC

Synonymous with quadword ECC.

Documentation Titles
Table 2 lists the books in the DEC 7000/10000 and VAX 7000/10000 documentation sets. Table 3 lists other documents that you may find useful.

Table 2 DEC 7000/10000 and VAX 7000/10000 Documentation
7000 Systems
Order Number

10000 Systems
Order Number

Installation Kit

EK–7000B–DK

EK–1000B–DK

Site Preparation Guide

EK–7000B–SP

EK–1000B–SP

Installation Guide

EK–700EB–IN

EK–100EB–IN

Hardware User Information Kit

EK–7001B–DK

EK–1001B–DK

Operations Manual

EK–7000B–OP

EK–1000B–OP

Basic Troubleshooting

EK–7000B–TS

EK–1000B–TS

Service Information Kit—VAX 7000

EK–7002A–DK

EK–1002A–DK

Platform Service Manual

EK–7000A–SV

EK–1000A–SV

System Service Manual

EK–7002A–SV

EK–1002A–SV

Pocket Service Guide

EK–7000A–PG

EK–1000A–PG

Advanced Troubleshooting

EK–7001A–TS

EK–1001A–TS

Service Information Kit—DEC 7000

EK–7002B–DK

EK–1002A–DK

Platform Service Manual

EK–7000A–SV

EK–1000A–SV

System Service Manual

EK–7002B–SV

EK–1002A–SV

Pocket Service Guide

EK–7700A–PG

EK–1100A–PG

Advanced Troubleshooting

EK–7701A–TS

EK–1101A–TS

Title

Reference Manuals
Console Reference Manual

EK–70C0B–TM

KA7AA CPU Technical Manual

EK–KA7AA–TM

KN7AA CPU Technical Manual

EK–KN7AA–TM

MS7AA Memory Technical Manual

EK–MS7AA–TM

I/O System Technical Manual

EK–70I0A–TM

Platform Technical Manual

EK–7000A–TM

Table 2 DEC 7000/10000 and VAX 7000/10000 Documentation (Continued)
Title

7000 Systems
Order Number

10000 Systems
Order Number

Upgrade Manuals
KA7AA CPU Installation Guide

EK–KA7AA–IN

KN7AA CPU Installation Guide

EK–KN7AA–IN

MS7AA Memory Installation Guide

EK–MS7AA–IN

KZMSA Adapter Installation Guide

EK–KXMSX–IN

DWLMA XMI PIU Installation Guide

EK–DWLMA–IN

DWMBB VAXBI PIU Installation Guide

EK–DWMBB–IN

H7237 Battery PIU Installation Guide

EK–H7237–IN

H7263 Power Regulator Installation Guide

EK–H7263–IN

Futurebus+ PIU Installation Guide

EK–DWLAA–IN

BA654 DSSI Disk PIU Installation Guide

EK–BA654–IN

BA655 SCSI Disk and Tape PIU Installation Guide

EK–BA655–IN

Removable Media Installation Guide

EK–TFRRD–IN

Table 3 Related Documents
Title

Order Number

General Site Preparation
Site Environmental Preparation Guide

EK–CSEPG–MA

System I/O Options
BA350 DECstor/me Modular Storage Shelf
Subsystem Configuration Guide

EK–BA350–CG

BA350 DECstor/me Modular Storage Shelf
Subsystem User’s Guide

EK–BA350–UG

BA350-LA DECstor/me Modular Storage Shelf
User’s Guide

EK–350LA–UG

CIXCD Interface User Guide

EK–CIXCD–UG

DEC FDDIcontroller 400 Installation/Problem Solving

EK–DEMFA–IP

DEC LANcontroller 400 Installation Guide

EK–DEMNA–IN

DEC LANcontroller 400 Technical Manual

EK–DEMNA–TM

DSSI VAXcluster Installation and Troubleshooting Manual

EK–410AA–MG

InfoServer 150 Installation and Owner’s Guide

EK–INFSV–OM

KDM70 Controller User Guide

EK–KDM70–UG

KFMSA Module Installation and User Manual

EK–KFMSA–IM

KFMSA Module Service Guide

EK–KFMSA–SV

RRD42 Disc Drive Owner’s Manual

EK–RRD42–OM

RF Series Integrated Storage Element User Guide

EK–RF72D–UG

TF85 Cartridge Tape Subsystem Owner’s Manual

EK–OTF85–OM

TLZ06 Cassette Tape Drive Owner’s Manual

EK–TLZ06–OM

Operating System Manuals
Alpha Architecture Reference Manual

EY–L520E–DP

DEC OSF/1 Guide to System Administration

AA–PJU7A–TE

DECnet for OpenVMS Network Management Utilities

AA–PQYAA–TK

Guide to Installing DEC OSF/1

AA–PS2DA–TE

OpenVMS Alpha Version 1.0 Upgrade and Installation Manual

AA–PQYSA–TE

VMS Upgrade and Installation Supplement: VAX 7000–600 and
VAX 10000–600 Series

AA–PRAHA–TE

VMS Network Control Program Manual

AA–LA50A–TE

xii

Table 3 Related Documents (Continued)
Title

Order Number

VMSclusters and Networking
HSC Installation Manual

EK–HSCMN–IN

SC008 Star Coupler User’s Guide

EK–SC008–UG

VAX Volume Shadowing Manual

AA–PBTVA–TE

Peripherals
Installing and Using the VT420 Video Terminal

EK–VT420–UG

LA75 Companion Printer Installation and User Guide

EK–LA75X–UG

xiii

Chapter 1
Overview

The MS7AA memory module connects directly to the LSB bus and provides
up to 2 Gbytes of dynamic random access memory (DRAM) to the CPU.
The LSB memory subsystem features the following:
•

64-Mbyte to 2-Gbyte memory capacity per module

•

Incremental configuration to a maximum of seven modules in a singleprocessor system

•

1-, 2-, 4-, and 8-way interleaving

•

64-byte block transfers, 16 bytes at a time, over the system bus

•

Memory modules with DRAM arrays of 1M x 4 or 4M x 4 components

•

Bit scattering to provide correction of data if a single DRAM fails

•

Read and write data wrapping on 32-byte naturally aligned boundaries

•

Quadword ECC protection that allows detection and correction of
single-bit failures and detection of 2-bit failures

•

Conversion logic that translates quadword ECC (DRAM ECC) to
longword ECC (LSB ECC) during memory reads and longword ECC to
quadword ECC during memory writes

Figure 1-1 shows the architecture of a memory module.

Overview 1-1

Figure 1-1

Memory Module Block Diagram

String 7

72 DRAMs

String 0

72 DRAMs

72 DRAMs
DDB

288
Data + ECC

9 Chips
MDC
72
Data + ECC

288
Data + ECC

9 Chips
MDC
72
Data + ECC

MDB
MIC-B

MIC-A

78
Data + ECC

LSB
BXB-0308-92

1.1 Major Sections
An MS7AA module consists of three major sections:
•

Memory interface controller (MIC)

•

Memory data controller (MDC)

•

DRAM arrays

The major sections communicate with each other through internal buses.

1.1.1 Memory Interface Controller
The memory interface controller (MIC) is comprised of two gate arrays,
MIC-A and MIC-B. It provides the interface to the LSB, controls DRAM
timing and refresh, runs memory self-test, and contains all LSB-required
and memory-specific registers.
The MIC-A interfaces to LSB D<63:0> and the LSB control signals. It decodes the LSB command and determines if the memory module is selected
for this transaction. The MIC-A provides the address and control signals
for the two banks and contains most of the CSRs.
The MIC-B interfaces to LSB D<127:64>. It is strictly a data path, with
some error checking logic and MIC-B-specific CSRs. The operation of the
MIC-B is controlled by the MIC-A.

1-2 Overview

1.1.2 Memory Data Controller
The memory data controller (MDC) consists of DRAM buffers that reside
between the MIC and the DRAM arrays. During a memory write, the
MDC buffers accumulate the four LSB data cycles into a 64-byte packet
that is written to the DRAMs in a single operation. During a memory
read, the DRAM buffers store 64 bytes of data, then parcel it to the MIC,
which in turn parcels it out to the LSB in four consecutive 16-byte cycles
under the control of the MIC-A.

1.1.3 DRAM Arrays
The DRAM arrays consist of DRAMs, control signal, and address buffer
components. The MS7AA memory modules can use DRAM sizes of 1M x 4
bits or 4M x 4 bits. The DRAM arrays are organized into 1 to 8 strings.
Each string requires 144 DRAMs (using DRAMs with quadword ECC), regardless of the DRAM type. A single string supports 64 Mbytes of memory
when configured with 4-Mbit DRAMs, and 256 Mbytes of memory when
configured with 16-Mbit DRAMs. The DRAM array on each memory module is configured with two independently accessible banks.
Interleaving of DRAM banks increases memory bandwith. Each memory
module supports 2-way interleaving when configured with a minimum of
two strings. Interleaving occurs between the two independently accessible
banks within a module. A memory configuration on the LSB consisting of
four memory modules, with at least two strings each, supports a maximum of 8-way interleaving.

1.2 Internal Buses
Data within the memory modules is transferred through two internal
buses: the memory data bus (MDB) and the DRAM data bus (DDB). The
MDB bus transfers data between the MIC chips and the MDC chips. The
DDB bus transfers data between the MDC chips and the DRAM arrays.

1.3 Transactions
Memory responds to but cannot initiate LSB transactions. It responds to
accesses to the memory space and to its own LSB node space. Memory
does not respond to any transaction in LSB broadcast space.
Memory modules run synchronously with the LSB. Memory transfers consist of four contiguous, 16-byte data cycles, for a total of 64 bytes per transaction. Up to three pipelined transactions can be in progress on the LSB
bus at a given time. Read and write data wrapping is supported on 32byte naturally aligned boundaries.

1.4 Refresh
Each memory module implements DRAM refresh. Module refresh is reset
and restarted under two different conditions: power-up and system reset.
All modules with the same DRAM refresh rate requirements refresh at the
same time.

Overview 1-3

Chapter 2
Memory Interface Controller

The memory interface controller (MIC) controls data movement between
the memory DRAM arrays and the LSB bus.

2.1 Components
The MIC consists of two 64-bit gate arrays, MIC-A and MIC-B.
The MIC-A interfaces to LSB D<63:0>, LSB control/status signals, and
LSB ECC<13:0>. It controls the operation of the memory module as well as
the operation of the MIC-B. The MIC-A generates the DRAM address and
timing functions necessary for all DRAM operations. It also generates all
signals used to control the memory data controller (MDC) chips.
The MIC-B interfaces to LSB D<127:64> and LSB ECC<27:14>. It functions strictly as a data path consisting of read and write data buffers, ECC
logic, and CSRs.
The MIC-A implements most of the LSB-required and memory-specific registers. When a MIC-B control/status register is accessed by the CPU, data
is transferred over an 8-bit bidirectional data path connecting the MIC-A
and the MIC-B.

2.2 Logic Elements
The MIC implements the following logic elements:
•

Command decode logic

•

Address decode logic

•

DRAM address logic

•

DRAM control logic

•

MIC data path logic

•

Data wrapping

•

Refresh logic

•

Self-test logic

•

LSB state machine control logic

Memory Interface Controller 2-1

The MIC also contains logic to support the memory data controller (MDC)
interface.

2.2.1 Command Decode Logic
The LSB command decode logic receives and latches D<37:0> into its address latch during LSB command/address cycles. D<37:35> contain the
LSB command field. Table 2-1 lists the LSB commands and the associated
operations within the memory module.

Table 2-1

LSB Commands for Memory Operations

D<37:35>

Command

Memory Operation

000

Read

Read memory at address specified on LSB D<34:0>.

001

Write

Write memory at address specified on LSB D<34:0>.

010

Reserved

Ignore command.

011

Victim Write

Write memory at address specified on LSB D<34:0>.

100

Read CSR

Read memory CSR at address specified on LSB D<34:0>.

101

Write CSR

Write memory CSR at address specified on LSB D<34:0>.

110

Reserved

Ignore command.

111

Private

Ignore command.

2.2.2 Address Decode Logic
Memory responds to two types of transactions:
•

Node space CSR transactions

•

Memory space transactions

Memory modules do not respond to transactions in LSB broadcast space.

2.2.2.1 Node Space CSR Transactions
Node space contains LSB required registers and memory-specific registers
accessed on aligned 64-byte boundaries. The MIC decodes the LSB node
space address and processes the request to the specified register.
All registers are 32 bits wide. Since not all fields within registers contain a
valit bit, CSR transactions involving bit fields with no associated valid bits
return UNPREDICTABLE data on reads. Writes to nonexistent bits have
no effect on module operations.
The MIC acknowledges memory node space requests whether the addressed CSR actually exists or not. Writes to nonexistent CSRs result in
UNDEFINED operations. Reads to nonexistent CSRs return UNPREDICTABLE data.

2-2 Memory Interface Controller

2.2.2.2 Memory Space Transactions
The address decode logic compares the LSB address with bits from the Address Mapping Register (AMR) to determine if the memory module is selected for the current transaction. Various fields in the AMR register allow selection of memory space address decode parameters as described in
the discussion of the AMR register in Chapter 7.
To support two banks per module, the address decode logic implements two
independent address paths.

2.2.3 DRAM Address Logic
The DRAM address logic generates row and column address bits for various memory configurations from the LSB address.

2.2.4 DRAM Control Logic
The timing of DRAM components requires that control signals, along with
the row and column addresses, conform to strict parameters. Each memory
bank implements a DRAM timing generator to ensure that all DRAM control signals are properly sequenced during LSB memory access, module refresh, and module self-test.
In addition to DRAM control, the two timing generators pass control information between each other. Since there is one common data path between
the MIC and the MDCs, communication between the two DRAM timing
generators is needed to prevent data path conflicts.

2.2.5 MIC Data Path Logic
The MIC data path can be broken down into two distinct blocks. The data
path to/from the DRAMs and the data path to/from the CSRs.
The data path to/from memory consists of a write path and a read path.
Within each path there are data buffers and ECC logic. The data path
to/from the CSRs implements parity generation logic needed to generate
LSB parity on returning CSR read data.
The MIC data path logic implements a 4 x 16 byte write buffer and a 4 x 16
byte read buffer that are used as temporary storage elements on the write
data path and the read data path, respectively. Storage of LSB write data
is necessary when the MDCs are busy with a previous write transaction.
Storage of LSB read data is necessary when LSB STALL is asserted by a
node other than the memory node supplying the requested read data. The
buffers are designed to minimize delays on the data paths.
The LSB operates on a 32-bit ECC algorithm, while memory stores and retrieves data with a 64-bit ECC algorithm. The write data path logic
checks, corrects, and then converts LSB longword (32-bit) ECC into
quadword (64-bit) ECC that is stored in each memory module. Similarly,
the read data path ECC logic checks, corrects, and then converts
quadword (64-bit) ECC used by memory into longword (32-bit) ECC used
by the LSB.

Memory Interface Controller 2-3

2.2.6 Data Wrapping
The data wrapping logic controls the alignment of data in the MDC chips.
LSB supports read and write data wrapping on 32-byte boundaries. During
an LSB command/address cycle, LSB D<0> is deasserted on all naturally
aligned 64-byte block transactions. It is asserted when the commander
node issues the second 32 bytes of data prior to the first 32 bytes on write
transactions, and expects the second 32 bytes of data prior to the first 32
bytes on read transactions.
Table 2-2 defines the wrapping of read or write data depending upon the
state of LSB D<0> latched during a command/address cycle.

Table 2-2

LSB Data Wrapping
LSB D<0>

Data Cycle Ordering

Octaword-1, Octaword-2, Octaword-3, Octaword-4

Octaword-3, Octaword-4, Octaword-1, Octaword-2

2.2.7 Refresh Logic
The refresh logic refreshes the memory module approximately every 15.6
microseconds regardless of DRAM type (4 Mbit, 16 Mbit). The refresh period is generated by a 10-bit divide-by counter from LSB clocks. The actual
count value is 780 ticks. A given module can be refreshed at the nominal
rate, 2 or 4 times the nominal rate as determined by bits in the Memory
Diagnostic Register. Upon power-up or reset, the default refresh rate is the
nominal value. Table 2-3 lists the refresh rate at various LSB cycle times.

Table 2-3

Refresh Rates at Various LSB Cycle Times
LSB Cycle Time (ns)

Refresh Rate

16
17
18
19
20

12.48
13.26
14.04
14.82
15.60

Each memory module is refreshed independently of the other memory
modules. Both banks of a memory array (all strings) are refreshed simultaneously with one exception: when an LSB read or write transaction is currently being serviced by one of the banks, refresh of the bank may be held
off until the transaction has completed. Refresh is performed on the memory bank immediately following the completion of the transaction.

2-4 Memory Interface Controller

2.2.8 Self-Test Logic
Upon power-up, system reset, or when EXST_A (bit <4> of the Memory Diagnostic Register A) is set by software, each module executes a self-test designed to test and initialize the DRAMs with good ECC. While self-test is
executing, any reference to memory space is NO ACKed. CSR space can be
accessed during self-test execution. However, writes to the Memory Diagnostic Register A (MDRA) and Memory Diagnostic Register B (MDRB) can
result in UNPREDICTABLE behavior. See Chapter 9 for self-test times.

2.2.9 LSB State Machine Control Logic
The LSB state machine control logic controls the data path interface
to/from the LSB and all CSR operations (read/write). This logic also starts
the DRAM timing generators.

Memory Interface Controller 2-5

Chapter 3
Memory Data Controller

The memory data controller (MDC) is the data interface between the
DRAMs and the memory interface controller (MIC). It connects the 576-bit
DRAM data path to the 144-bit MIC data path. The MDC operates under
the control of the MIC.

3.1 MDC Data Paths
The MDC provides separate read and write data paths to the DRAM array
on one side and the MIC on the other.
Each MDC block is composed of eighteen MDC chips. Each MDC chip interfaces between a 32-bit bidirectional DDB (DRAM data bus) port and an
8-bit bidirectional MDB (MIC data bus) port. Both ports are controlled by
the MIC-A.

3.2 MDC Transactions
MDC supports four types of transactions:
•

Read

•

Wrapped read

•

Write

•

Wrapped write

3.2.1 Read and Wrapped Read Transactions
During a read transaction, the MDC chip receives DRAM read data on the
DDB<31:0> port and loads it in its internal read data buffer. Once four
bytes of data are assembled in the read data buffer, the MDC chip drives
the content of the read data buffer onto the MDB<7:0> port in four separate clock cycles.
When data wrapping is selected, the order in which read data is transferred to the MIC is altered, as shown in Table 3-1.

Memory Data Controller 3-1

Table 3-1

MDC Wrap Ordering

Cycle No.

Octaword No.
Wrap Disabled
(LSB D<0>=0)

Octaword No.
Wrap Enabled
(LSB D<0>=1)

1
2
3
4

3
4
1
2

3.2.2 Write and Wrapped Write Transactions
During a write transaction, the MDC chip receives DRAM write data on
the MDB<7:0> port and loads it in its internal write data buffer in four
consecutive cycles. Once the data is assembled in the write data buffer,
the MDC drives the contents of the write data buffer onto the DDB<31:0>
port.
When data wrapping is selected, the order in which write data is latched
into the MDC is altered (see Table 3-1) so that data written to the DRAMs
is not wrapped.

3-2 Memory Data Controller

Chapter 4
Memory Organization

The system supports up to seven memory modules in single-processor
configurations. The physical memory composed of a single or multiple
memory modules can be organized in various ways to optimize memory
access.

4.1 Memory Capacity
Memory can be configured with MS7AA modules of various capacities,
from 64 Mbytes to 2 Gbytes. The DRAM arrays consist of DRAMs, control signals, and address buffer components. The memory modules can
use DRAM sizes of 4 Mbits or 16 Mbits. The DRAM arrays are organized
into 1 to 8 strings. Each string requires 144 DRAMs (using 1M x 4 or 4M
x 4 DRAMs). A single string supports 64 Mbytes of memory when configured with 4-Mbit DRAMs, and 256 Mbytes of memory when configured
with 16-Mbit DRAMs. Table 1-1 lists array capacities that can be configured based upon the number of strings on a module and the DRAM type.

Table 4-1

Memory Array Capacity
DRAM Type
(Mbits)

Number of
Strings

4
4
4
4
16
16
16
16

1
2
4
8
1
2
4
8

Memory Capacity
(Mbytes)
64
128
256
512
256
512
1024
2048

4.2 Memory Banking
DRAM arrays on all memory modules containing more than one string
are organized as two banks, Bank 0 and Bank 1. A bank is a grouping of
one or more strings that share a common address path. Each bank has
its own set of control, address, and timing signals and is accessible inde-

Memory Organization 4-1

pendently. This arrangement prevents memory idling by allowing access
to the second bank while the first bank is still busy.

4.3 Memory Interleaving
Further enhancement of memory performance can be achieved by interleaving the physical memory. Interleaving can be done at two levels: module and system.
At the module level, the DRAM arrays can be interleaved on 64-byte block
boundaries. Each memory module supports 2-way interleaving when configured with a minimum of two strings. Interleaving occurs between the
two independently accessible banks within a module. Figure 4-1 shows a
2-way interleaved 2-string memory module. The DRAM array in a 2string MS7AA memory module is always interleaved.

Figure 4-1

Two-Way Interleave of a 128-Mbyte DRAM Array
Banks 0

0000 0000 0000 0040
0000 0080 0000 00C0
64 Mbytes

64 Mbytes

07FF FF80 07FF FFC0
Block size
= 64 Bytes
DRAM size
= 4 Mbits
Memory Capacity = 128 Mbytes
BXB-0307A-92

In multi-module memory subsystems, three modes of interleave are possible at the system level: default, explicit, and none. The interleave mode
selection parameters are stored in the console EEPROM and can be modified through the console program. Initialization software uses registers in
LSB commanders and each memory module to configure the memory interleave as specified by the EEPROM parameters. A memory configuration
consisting of four memory modules supports a maximum of 8-way interleaving when each of the four modules is 2-way interleaved. The three additional modules (modules 5 to 7), if present, can be configured into the
system as two modules 4-way interleaved and 1 module 2-way interleaved.
Figure 4-2 shows four memory modules in an 8-way interleaved organization.

4-2 Memory Organization

Figure 4-2

Eight-Way System Interleave of Four 128-Mbyte Memory Modules

2-Way Module Interleave; No System Interleave
Banks 0

0000 0000 0000 0040
0000 0080 0000 00C0

0800 0000 0800 0040
0800 0080 0800 00C0

1000 0000 1000 0040
1000 0080 1000 00C0

1800 0000 1800 0040
1800 0080 1800 00C0

07FF FF80 07FF FFC0

0FFF FF80 0FFF FFC0

17FF FF80 17FF FFCO

IFFF FF80 IFFF FFC0

2-Way Module Interleave; 8-Way System Interleave
Banks 0

0000 0000 0000 0100
0000 0200 0000 02FF

0000 0040 0000 0140
0000 0240 0000 033F

0000 0080 0000 0180
0000 0280 0000 037F

0000 00C0
0000 02C0

1FFF FE00 1FFF FF00

1FFF FE40 1FFF FF40

1FFF FE80 1FFF FF80

1FFF FEC0 1FFF FFC0

Block size
= 64 Bytes
DRAM size
= 4 Mbits
Memory Capacity = 512 Mbytes

0000 01C0
0000 03BF

BXB-0307-92

If the EEPROM specifies default interleave, the console attempts to form
interleave sets so that the largest interleave factor is obtained for each
group of DRAM arrays.
The default mode optimizes interleaving of memory in any arrangement of
memory modules. For example, two 128-Mbyte modules can be combined
to appear as a single 256-Mbyte module that can then be interleaved with
a single 256-Mbyte module. In this configuration, three modules are 2way interleaved among each other. This type of configuration yields 2-way
module interleaving and 4-way system-level interleaving as shown in Figure 4-3.

Memory Organization 4-3

Figure 4-3

Interleaving Different Size Memory Modules
Two 128-Mbyte and One 256-Mbyte Memory Modules
Noninterleaved

128
Mbytes

Interleaved

256
Mbytes

128
Mbytes

256
Mbytes

128
Mbytes

BXB-0389A-92

If the EEPROM specifies explicit interleave sets, the console then interleaves the arrays as requested. In a noninterleave mode, the console configures arrays in order, by node number, with the lowest numbered array
at the lowest physical address.

4-4 Memory Organization

Chapter 5
LSB Memory Signals

A memory module interfaces the LSB bus through a total of 173 signals.
This chapter lists the LSB memory signals and describes their functions.
Refer to the Platform Technical Manual for a complete listing of the LSB
bus signals. Table 5-1 lists the LSB memory signals and identifies their
functions.
LSB Data D<127:0>
The LSB data signals transfer command/address and data information between nodes. A memory module receives command/address cycles. It
drives and receives data cycles.
During command/address cycles, only D<38:0> contain valid information
(see Figure 5-1). D<38> carries the parity bit protecting the command and
address information in D<37:0>. D<127:39> contain UNDEFINED data
that will be ignored.

Figure 5-1

LSB D<127:0> During Command/Address Cycles
127

39 38 37

UNDEFINED

CA
BXB-0266-92

During CSR data cycles, D<31:0> transfer the CSR data. D<37:32> contain
UNDEFINED data (see Figure 5-2). D<38> carries the parity bit for read
and write data. A memory module checks for correct parity on CSR writes
and supplies correct parity on CSR reads.
NOTE: Data is ignored in D<37:32>. However, memory computes CSR data cycle
parity over D<37:0>. Hence, for parity checking, D<37:32> are valid.

LSB Memory Signals 5-1

Figure 5-2

LSB D<127:0> During CSR Data Cycles
127

39 38 37

UNDEFINED

32 31

CSR DATA

UNDEFINED

Table 5-1

Signal

BXB-0267-92

LSB Memory Signals
No. of
Lines

Function

Command/Address. Asserted by a bus commander to signify a
command/address cycle.

CNF

Confirmation. Asserted by the selected memory module to signify
acceptance of a command/address cycle.
Data. Command/address and data lines.1

D<127:0>

128

DIRTY

Dirty. Asserted by a CPU module to indicate that the targeted
cache block has been modified more recently than the copy in memory. When asserted during a read transaction, the selected memory
module aborts the transaction and does not return read data to the
LSB bus.

ECC<27:0>

Error Checking and Correction. Error correction lines for data
cycles.

ERR

Error. Asserted when a memory module detects certain LSB and
memory-related errors.

NID<2:0>

Node ID. Hardwired lines that indicate the node ID (slot number)
of the memory module.

PH0 (SINE)

Sine. Used to generate the eight copies of the digital clock for each
module.

REQ<9:0>

Arbitration Request. Asserted by the I/O module or CPU modules to arbitrate for the LSB bus. Memory modules never assert
REQ<9:0>.

RESET
STALL

1
1

Reset. Causes a system reset when asserted by a node.
Stall. Asserted when the module is unable to accept write data or
supply read data.

1 Only D<38:0> are valid during command/address cycles and LSB CSR data cycles.

5-2 LSB Memory Signals

LSB CA
CA is asserted by an LSB commander node when it is driving a command/address cycle on the LSB. The memory module receives but never
drives this signal.
LSB CNF
CNF is asserted by memory to confirm the acceptance of a command/address cycle to either memory or node space. The selected module
asserts CNF only when the LSB address matches the module’s memory or
node space, and no parity errors are detected.
LSB D<127:0>
Command/address and data lines.
LSB DIRTY
Memory modules monitor LSB DIRTY. If asserted during an LSB read
transaction, memory does not supply read data for the transaction associated with the assertion of LSB DIRTY. The node that asserted DIRTY
supplies the read data in place of memory.
LSB ECC Signals ECC<27:0>
LSB ECC signals carry the longword ECC check bits protecting D<127:0>
during memory space read or write data cycles.
During the four memory space write data cycles, the selected memory module receives ECC<27:0>, with write data in D<127:0>, checks and corrects
ECC errors before data is written to memory. During read data cycles
from memory, a module checks and corrects single-bit ECC errors before
data is driven onto LSB.
During CSR data cycles, ECC<27:0> contain UNDEFINED data that is ignored.
LSB ERR
Memory modules monitor and assert ERR under conditions discussed in
the Platform Technical Manual. In addition, memory asserts ERR for
memory-specific error conditions. Refer to Chapter 8 for additional details.
LSB NID<2:0>
These three signals indicate the node ID. They are hardwired into the
backplane.
LSB PH0 (SINE)
This is the LSB-supplied clock signal. Each memory module receives and
generates multiple copies of a single-phase clock.

LSB Memory Signals 5-3

LSB REQ<9:0>
Memory modules monitor REQ<9:0> to determine when a command/ address cycle will be driven on the LSB. The OR of these ten signals initiates
the LSB state machines and gates the address lines to the DRAMs to help
reduce power consumption. The decoded DRAM ROW address is sent to all
modules and all strings independent of module selection. This is done to
speed access time. If a module is not selected for the transaction, or if the
bus goes to the idle state, the address drivers are held in their previous
state to conserve power.
LSB RESET
All modules monitor LSB RESET. When asserted, the module is reset to
its default power-up state. The assertion of LSB RESET inhibits DRAM refresh. When LSB RESET is deasserted, all memory modules start refresh
operation within a specified number of cycles.
LSB STALL
Memory modules monitor and assert STALL. Memory monitors STALL to
ensure that it stays in sync with the bus protocol. Memory asserts STALL
for two conditions:

5-4 LSB Memory Signals

•

A module asserts STALL when it is not able to supply read data to an
LSB commander at the required time due to a memory timing conflict.
STALL remains asserted until the conflict is resolved and read data
can be driven on the LSB. This condition occurs when a read transaction immediately follows a write transaction on the LSB to the same
memory bank. In this instance nine STALLs are asserted on the LSB.

•

A module asserts STALL when it cannot supply read data or accept
write data due to DRAM refresh cycles. In this case 1 to 14 STALLs
are asserted on the LSB.

Chapter 6
Memory Transactions

The design of the memory module architecture ensures that the command/address issued to the DRAMs is always driven on the address lines
of an idle memory bank. This speeds DRAM access during reads.

6.1 Memory Read Transactions
During a memory read transaction, DRAM read data is driven onto the
MDB bus to both MIC-A and MIC-B in four consecutive clock cycles. The
memory module starts the DRAM access 1.5 cycles after a command/
address cycle.
A read transaction can be stalled by the LSB bus or by the memory module.

6.1.1 LSB Stalled Read Transactions
The assertion of LSB STALL by another LSB node during memory read
transactions causes the memory module to delay the release of read data
to the LSB bus. The DRAM read timing is not affected by the assertion of
LSB STALL. Under a stall condition, the DRAM read data is latched
either in the MDC chips or is transferred to the read data buffer of the
MIC. The DRAM read data remains in the MIC until LSB STALL is
deasserted. Read data is driven on the LSB bus two cycles after the
deassertion of LSB STALL.

6.1.2 Module Stalled Read Transactions
The start of the DRAM access for a memory read transaction may be delayed due to conflicts on the memory module. These conflicts result from
either DRAM refresh cycles or from DRAM write and read timing.

6.2 Memory Write Transactions
During a memory write transaction, LSB write data is latched into the
MIC. Data is then transferred from the MIC to the MDC chips through
the 144-bit MDB bus in four consecutive cycles. The memory module
starts DRAM access a minimum of 12 bus cycles after the command/address cycle coincident with receiving the write data.
A write transaction can be stalled by the LSB bus or by the memory module.

Memory Transactions 6-1

6.2.1 LSB Stalled Write Transactions
The assertion of LSB STALL by another node delays the start of the
DRAM write access until after the first LSB write data has been received.
Once the DRAM write has started, it is completed in four consecutive LSB
cycles.

6.2.2 Module Stalled Write Transactions
The memory module asserts LSB STALL to suppress the generation of
write transactions to memory when conflicts on the memory module delay
loading of write data into the DRAMs. The stall occurs on the third backto-back write transaction to a single module preceded by a DRAM refresh.
The memory module maintains LSB STALL assertion until the completion
of the refresh cycle. When refresh has completed, the memory module
deasserts LSB STALL, and the DRAM cycle for the write transaction
starts.

6.3 Memory Transaction Ordering
In general, memory transactions are performed on a first come first served
protocol. However, this protocol is overruled when a memory read follows
a write transaction and targets different banks of the same memory module. In this case, the memory read transaction is always performed first
to enhance system performance.

6.4 ECC Conversion
Memory modules convert LSB longword (32-bit) ECC into quadword (64bit) ECC that is stored with LSB data on writes. During LSB reads,
quadword ECC is converted to longword ECC as required by the LSB.
Quadword ECC requires fewer DRAMs per string.

6-2 Memory Transactions

Chapter 7
Registers

The MS7AA memory module has two groups of registers:
•

LSB required registers

•

Module-specific registers

LSB required registers are used for internode communication over the LSB
bus. Memory-specific registers are used to perform functions unique to the
memory module.

7.1 Node Space Base Addresses
All memory registers reside on the memory controller interface. They are
mapped to the node space as offsets to a base address (BB). The base address is implemented in hardware and depends on the node ID of the module, which is determined by the LSB slot occupied by the module. Table
7-1 gives the physical base addresses of nodes on the LSB bus for processors that support a 32-bit address range (for example, KA7AA) and a 34-bit
address range (for example, KN7AA).

Table 7-1

LSB Node Space Base Addresses

Node ID
(Slot)

Module

Physical Base Address (BB)
(Byte)
32-Bit Range
34-Bit Range

0
1
2
3
4
5
6
7
8

CPU/Memory
CPU/Memory
CPU/Memory
CPU/Memory
CPU/Memory
CPU/Memory
CPU/Memory
CPU/Memory
I/O

F800 0000
F840 0000
F880 0000
F8C0 0000
F900 0000
F940 0000
F980 0000
F9C0 0000
FA00 0000

3 F800 0000
3 F840 0000
3 F880 0000
3 F8C0 0000
3 F900 0000
3 F940 0000
3 F980 0000
3 F9C0 0000
3 FA00 0000

Registers 7-1

7.2 Bit Access Type Acronyms
Acronyms are used throughout register descriptions to indicate the access
type of the bit(s). Table 7-2 lists those acronyms.

Table 7-2

7-2 Registers

Access Types of Register Bits
Acronym

Access Type

Read only; writes ignored.

Read as zero.

R/W

Read/write.

W1C

Read/write one to clear; unaltered by a write of zero.

W1S

Write one to set; self-cleared; cannot be cleared by a
write of zero.

Write only.

7.3 Register Descriptions
Table 7-3 lists the memory module registers and gives the address of each
register as an offset from a selected node space base address. Functional
descriptions of the memory registers follow.

Table 7-3

Memory Module Registers

Mnemonic

Address
(Byte Offset)

LDEV
LBER
LCNR
IBR
LBESR0
LBESR1
LBESR2
LBESR3
LBECR0
LBECR1

BB1 + 0000
BB + 0040
BB + 0080
BB + 00C0
BB + 0600
BB + 0640
BB + 0680
BB + 06C0
BB + 0700
BB + 0740

MCR
AMR
MSTR0
MSTR1
FADR
MERA
MSYNDA
MDRA
MCBSA
MERB
MSYNDB
MDRB
MCBSB

BB + 2000
BB + 2040
BB + 2080
BB + 20C0
BB + 2100
BB + 2140
BB + 2180
BB + 21C0
BB + 2200
BB + 4140
BB + 4180
BB + 41C0
BB + 4200

LSB Required
Device Register
Bus Error Register
Configuration Register
Information Base Repair Register
Error Syndrome Register 0
Error Syndrome Register 1
Error Syndrome Register 2
Error Syndrome Register 3
Error Command Register 0
Error Command Register 1
Memory-Specific
Memory Configuration Register
Address MappingRegister
Memory Self-Test Register 0
Memory Self-Test Register 1
Failing Address Register
Memory Error Register A
Memory Error Syndrome Register A
Memory Diagnostic Register A
Memory Check Bit Substitute Register A
Memory Error Register B
Memory Error Syndrome Register B
Memory Diagnostic Register B
Memory Check Bit Substitute Register B

1 BB is the node space base address of the memory module in hex.

Registers 7-3

LDEV—Device Register
Address
Access

BB + 0000
R/W
The LDEV register is loaded during initialization with information
that identifies a node.

16 15

DREV

DTYPE
BXB-0100-92

Table 7-4

LDEV Register Bit Definitions

Name

Bit(s)

Type

Function

DREV

<31:16>

R/W

Device Revision. Identifies the functional revision level
of the module. The value of this field is contained in the
EEPROM of the memory module and is loaded into the
LDEV register by console software at system initialization.
For the MS7AA memory module, the value of this field is
zero.

DTYPE

<15:0>

R/W

Device Type. Loaded at initialization with a value of
4000 (hex), which identifies the node as a memory module.
The device type may be modified by console software when
the device type field is fetched from the serial EEPROM located on the memory module.

7-4 Registers

LBER—Bus Error Register
Address
Access

BB + 0040
R/W
The LBER register stores the error bits that are flagged in memory
operations and logs the failing commander ID. The status of this
register remains locked until software resets the error bit(s).

18 17 16 15 14 13 12 11 10

RSVD
NSES <18>
CTCE <17>
DTCE <16>

DIE <15>
SHE <14>
CAE <13>
NXAE <12>
CNFE <11>
STE <10>
TDE <9>
CDPE2 <8>
CDPE <7>
CPE2 <6>
CPE <5>
CE2 <4>

CE <3>
UCE2 <2>
UCE <1>
E <0>
BXB-0101-92

Registers 7-5

Table 7-5

LBER Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:19>

R/W, 0

Reserved.

NSES

<18>

RO, 0

Node-Specific Error Summary. Set when one of
bits <11>, <10>, <9>, <5>, or <4> of the MERA register is set.

CTCE

<17>

W1C, 0

Control Transmit Check Error. Not implemented on memory.

DTCE

<16>

W1C, 0

Data Transmit Check Error. Not implemented on
memory.

DIE

<15>

W1C, 0

DIRTY Error.

SHE

<14>

W1C, 0

SHARED Error. Not implemented on memory.

CAE

<13>

W1C, 0

Command/Address Error.

NXAE

<12>

W1C, 0

Nonexistent Address Error. Not implemented on
memory.

CNFE

<11>

W1C, 0

CNF Error.

STE

<10>

W1C, 0

STALL Error.

TDE

<9>

W1C, 0

Transmitter During Error.

CDPE2

<8>

W1C, 0

Second CSR Data Parity Error. Not implemented on memory.

CDPE

<7>

W1C, 0

CSR Data Parity Error. Not implemented on
memory.

CPE2

<6>

W1C, 0

Second Command Parity Error.

CPE

<5>

W1C, 0

Command Parity Error.

CE2

<4>

W1C, 0

Second Correctable Data Error.

<3>

W1C, 0

Correctable Data Error.

UCE2

<2>

W1C, 0

Second Uncorrectable Data Error.

UCE

<1>

W1C, 0

Uncorrectable Data Error.

<0>

W1C, 0

Error. Signals assertion of error line.

7-6 Registers

LCNR— Configuration Register
Address
Access

BB + 0080
R/W
The LCNR register contains LSB systemwide configuration setup
and status information.

31 30 29 28 27

RSVD
CEEN

RSTSTAT
NHALT
NRST
STF

BXB-0102-92

Table 7-6

LCNR Register Bit Definitions

Name

Bit(s)

Type

Function

STF

<31>

R/W, 1

Self-Test Fail. When set, indicates that this node has
not yet completed self-test. Memory clears this bit at
the completion of self-test regardless of defective locations found in the DRAM array.

NRST

<30>

WO, 0

Node Reset. When set, the node enters console mode
and undergoes a reset sequence. CSRs are reset to their
initialized state. Any pending transactions are lost or
left uncompleted. Memory self-test halts, if running,
and does not restart. An internally generated reset signal remains asserted for 16 LSB bus cycles after NRST
is set, providing sufficient time to reset memory state
and clear NRST. If NRST is set, a value of zero must be
written to the MDRA register; otherwise, the memory
operation is UNDEFINED.

NHALT

<29>

Node Halt. Not implemented on memory.

RSTSTAT

<28>

Reset Status. Not implemented on memory.

RSVD

<27:1>

Reserved. Read as zero.

CEEN

<0>

R/W, 0

Correctable Error Detection Enable. When set,
enables detection of correctable errors.

Registers 7-7

IBR—Information Base Repair Register
Address
Access

BB + 00C0
R/W
The IBR register is used to access the EEPROM on the LSB memory and I/O modules. The EEPROM access is accomplished
through continual updates of this register by software.

MBZ
SCLK
XMT_SDAT
RCV_SDAT
BXB-0218-92

Table 7-7

IBR Register Bit Definitions

Name

Bit(s)

Type

Function

MBZ

<31:3>

R/W, 0

Must Be Zero. Must always be written as zero.

SCLK

<2>

R/W, 0

Serial Clock. Used by software to implement the
EEPROM serial clock interface. When this bit is written with a one, the EEPROM serial clock input is forced
to logic high. When it is cleared, the serial clock input is
forced to logic low.

XMT_SDAT

<1>

R/W, 1

Transmit Serial Data. Used by software to assert the
serial data line of the EEPROM to either high or low
logic levels. This bit is used with SCLK to transfer command/address and write data to the EEPROM.

RCV_SDAT

<0>

RO, 1

Receive Serial Data. Returns the status of the
EEPROM serial data line. Used by software to receive
serial read data and EEPROM responses. XMT_SDAT
must be one to receive an EEPROM response or serial
read data.

7-8 Registers

LBESR0-3—Error Syndrome Registers
Address
Access

BB + 0600 to 06C0
RO
The LBESR registers contain the syndrome computed from data
received on the LSB D and ECC fields during the cycle when an error was detected. These registers are locked upon the first ECC
detected error and remain locked until all LSB ECC error bits in
LBER are cleared.

RSVD

SYND_0

RSVD

SYND_1

RSVD

SYND_2

RSVD

SYND_3
BXB-0105-92

Table 7-8

LBESR Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:7>

Reserved. Read as zero.

SYND_0

<6:0>

RO, 0

Syndrome 0. Syndrome computed from D<31:0>
and ECC<6:0> during error cycle.

SYND_1

<6:0>

RO, 0

Syndrome 1. Syndrome computed from D<63:32>
and ECC<13:7> during error cycle.

SYND_2

<6:0>

RO, 0

Syndrome 2. Syndrome computed from D<95:33>
and ECC<20:14> during error cycle.

SYND_3

<6:0>

RO, 0

Syndrome 3. Syndrome computed from D<127:96>
and ECC<27:21> during error cycle.

Registers 7-9

LBECR0,1—Error Command Registers
Address
Access

BB + 0700 and BB + 0740
RO
The LBECR registers hold the contents of the LSB command and
address fields for the operation during which an error was detected.

20 19 18 17 16 15 14

11 10

3 2

CA <31:0>
RSVD

CID

RSVD

CNF
SHARED
DIRTY
DCYCLE

Table 7-9

P CMD

BXB-0106-92

LBECR Register Bit Definitions

Name

Bit(s)

Type

Function

<31:0>

Command/Address. Contents of D<31:0> during command cycle.

RSVD

<31:20>

Reserved. Read as zero.

DCYCLE

<19:18>

Data Cycle. Value indicates which data cycle had the
data error.

7-10 Registers

LBECR<19:18>

Data Cycle in Error

00
01
10
11

1
2
3
4

Table 7-9 LBECR Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

DIRTY

<17>

Dirty. Set when DIRTY is asserted for the current command.

SHARED

<16>

Shared. Set when SHARED is asserted for the current
command.

CNF

<15>

Confirmation. Set when CNF is asserted for the current command.

RSVD

<14:11>

Reserved. Read as zero.

CID

<10:7>

Commander ID. Reflects the contents of REQ<3:0> during a command cycle.

<6>

Parity. Contents of D<38> during command cycle.

CMD

<5:3>

Command. Contents of D<37:35> during command cycle.
CMD is decoded as follows:
1

Command

Function

DAS Value

000
001
010
011
100
101
110
111

Read
Write
Reserved
Write Victim
Read CSR
Write CSR
Reserved
Private

00
08
18
20
28
38

1 The hex value commonly found in the low byte of this register
when less than 8 Gbytes of memory are present in the system.

<2:0>

Command/ Address. Contents of D<34:32> during command cycle.

Registers 7-11

MCR—Memory Configuration Register
Address
Access

BB + 2000
R/W
The MCR register provides information about the DRAM array. It
is accessed by console software to determine module capacity, that
is, the DRAM type (4-Mbit or 16-Mbit) and number of strings installed. This information is necessary to set up the eight AMR registers in each LSB commander node and the AMR register located
on each memory module at BB+2040.

RSVD
STRG
RSVD
DTYP
BXB-0217-92

7-12 Registers

Table 7-10

MCR Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:4>

Reserved. Read as zero.

STRG

<3:2>

RO, X

String. Supplies information about the number of
strings installed on a module. This field, in conjunction with DTYP, indicates module capacity. It is
loaded at system initialization.
MCR<3:2>

No. of Strings

00
01
10
11

1
2
4
8

RSVD

<1>

Reserved. Reads as zero.

DTYP

<0>

RO, X

Device Type. Supplies information about the size
of DRAM technology used for the memory module.
This bit, along with STRG, indicates module capacity.
It is loaded at system initialization.
MCR<0>

DRAM Type

0
1

4 Mbit
16 Mbit

Registers 7-13

AMR—Address Mapping Register
Address
Access

BB + 2040
R/W
The AMR register is used with the LSB memory address issued
during a command/address cycle to select a memory module, a
bank within a module, and adjust the address on memory modules
based upon the interleave level selected, the number of strings,
and the DRAM type.
This register is a single copy of the eight mapping registers that
CPU modules and the IOP module must implement. When the console in the primary CPU configures memory, it determines the
slots occupied by the memory modules and loads the slot number
of each memory module in the AMR register of the module. Copies
of the AMR registers are written into the corresponding mapping
registers on all CPU nodes and the IOP node. The AMR contents
for nodes 0 to 7 are placed into LMMR0-7 registers. If a module is
not present in a memory slot, the console writes a zero to bit <0>
(Enable) of the corresponding LMMR register.

17 16

MADR

11 10

RSVD

NBANKS
INTL
BXB-0216-92

Table 7-11

AMR Register Bit Definitions

Name

Bit(s)

Type

Function

MADR

<31:17>

R/W, 0

Module Address. The contents of MADR is compared with the LSB address contained on D<34:20>
for a match. (MADR bit <17> correlates to LSB address line D<20>, and so on.)

RSVD

<16:11>

Reserved. Read as zero.

7-14 Registers

Table 7-11 AMR Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

NBANKS

<10:9>

R/W, 0

Number of Banks. Specifies the number of banks
(1, 2, 4, or 8) contained on individual memory modules.

<8:5>

R/W, 0

AMR<10:9>

No. of Banks

00
01
10
11

1
2
Reserved
Reserved

Address Width. Specifies the number of bits in
the LSB address field <34:20> that are significant.
Only those bits are compared with the same number
of corrersponding bits in the AMR<MADR> (bits
<31:17>). The remaining bits are ignored. The
theoretical range of significant bits selected by different values of the AMR<AW> is given below. In
the initialized state, no bits of D<34:20> are
matched to bits AMR<31:17> (AW = 0000). When
AW contains a value of 0001, only the MSBs are
compared (AMR<31> is compared to LSB<34>). Access is allowed if a match occurs. If a value of F
(hex) is written in AW, all bits are significant, and
the LSB <34:20> must match AMR<31:17>.

AMR<8:5>

Significant Bits Compared
LSB Data
AMR<MADR>

1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000

<34:20>
<34:21>
<34:22>
<34:23>
<34:24>
<34:25>
<34:26>
<34:27>
<34:28>
<34:29>
<34:30>
<34:31>
<34:32>
<34:33>
<34>
No compare

<31:17>
<31:18>
<31:19>
<31:20>
<31:21>
<31:22>
<31:23>
<31:24>
<31:25>
<31:26>
<31:27>
<31:28>
<31:29>
<31:30>
<31>

Registers 7-15

Table 7-11 AMR Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

<4:3>

R/W, 0

Interleave Address. Determines module selection
based upon level of interleave with other memory
modules.

INTL

<2:1>

R/W, 0

Interleave. Determines the level of interleave of
this module with other modules for a given address
space.
AMR
<2:1>

7-16 Registers

<0>

R/W, 0

Interleave Level

1-way interleave. Module is not interleaved with any other module.

2-way interleave. Module is interleaved with one other module.

4-way interleave. Module is interleaved with three other modules.

Reserved.

Enable. Enables the module to respond to LSB
memory space transactions.

MSTR0,1—Memory Self-Test Registers
Address
Access

BB + 2080 and BB + 20C0
R/W
The MSTR registers are used to isolate self-test failures to a given
address segment or segments (if multiple failures) within a module. The two registers combined break up a memory module into 64
distinct address segments. Each segment resides in a range of addresses that are sized according to the selected DRAM component
(4 Mbits or 16 Mbits).

MSTR0
31

MSTR1
BXB-0215-92

Table 7-12

MSTR Register Bit Definitions

Name

Bit(s)

Type

Function

STFAS

<31:0>

RO, 0

Self-Test Failing Address Segment. A bit in the
MSTR registers is set when the associated memory
segment fails self-test (is defective) in a noninterleaved memory configuration. Each module executes
self-test as if it were the only memory module in the
system.

Table 7-13 gives a listing of memory address segments associated with
each bit in the MSTR registers. Address segments are given for 4-Mbit
and 16-Mbit DRAM arrays.

Registers 7-17

Table 7-13

Failing Bit

Memory Error Address Segments

4-Mbit

MSTR0

16-Mbit

4-Mbit

MSTR1

16-Mbit

0000 0000 to
007F FFFF

0000 0000 to
01FF FFFF

1000 0000 to
107F FFFF

4000 0000 to
41FF FFFF

0080 0000 to
00FF FFFF

0200 0000 to
03FF FFFF

1080 0000 to
10FF FFFF

4200 0000 to
43FF FFFF

0100 0000 to
017F FFFF

0400 0000 to
05FF FFFF

1100 0000 to
117F FFFF

4400 0000 to
45FF FFFF

0180 0000 to
01FF FFFF

0600 0000 to
07FF FFFF

1800 0000 to
11FF FFFF

4600 0000 to
47FF FFFF

0200 0000 to
027F FFFF

0800 0000 to
09FF FFFF

1200 0000 to
127F FFFF

4800 0000 to
49FF FFFF

0280 0000 to
02FF FFFF

0A00 0000 to
0BFF FFFF

1280 0000 to
12FF FFFF

4A00 0000 to
4BFF FFFF

0300 0000 to
037FFFFF

0C00 0000 to
0DFF FFFF

1300 0000 to
137F FFFF

4C00 0000 to
4DFF FFFF

0380 0000 to
08FF FFFF

0E00 0000 to
0FFF FFFF

1380 0000 to
13FF FFFF

4E00 0000 to
4FFF FFFF

0400 0000 to
047F FFFF

1000 0000 to
13FF FFFF

1400 0000 to
147F FFFF

5000 0000 to
51FF FFFF

0480 0000 to
04FF FFFF

1200 0000 to
15FF FFFF

1480 0000 to
14FF FFFF

5200 0000 to
53FF FFFF

0500 0000 to
057F FFFF

1400 0000 to
15FF FFFF

1500 0000 to
157F FFFF

5400 0000 to
55FF FFFF

0580 0000 to
05FF FFFF

1600 0000 to
17FF FFFF

1580 0000 to
15FF FFFF

5600 0000 to
57FF FFFF

0600 0000 to
067F FFFF

1800 0000 to
19FF FFFF

1600 0000 to
167F FFFF

5880 0000 to
59FF FFFF

0680 0000 to
06FF FFFF

1A00 0000 to
1BFF FFFF

1680 0000 to
16FF FFFF

5A00 0000 to
5BFF FFFF

0700 0000 to
077F FFFF

1C00 0000 to
1DFF FFFF

1700 0000 to
177F FFFF

5C00 0000 to
5FFF FFFF

0780 0000 to
07FF FFFF

1E00 0000 to
1FFF FFFF

1780 0000 to
17FF FFFF

5E00 0000 to
5FFF FFFF

7-18 Registers

Table 7-13 Memory Error Address Segments (Continued)

Failing Bit

4-Mbit

MSTR0

16-Mbit

4-Mbit

MSTR1

16-Mbit

0800 0000 to
087F FFFF

2000 0000 to
21FF FFFF

1800 0000 to
187F FFFF

6000 0000 to
61FF FFFF

0880 0000 to
08FF FFFF

2200 0000 to
23FF FFFF

1880 0000 to
18FF FFFF

6200 0000 to
63FF FFFF

0900 0000 to
097F FFFF

2400 0000 to
25FF FFFF

1900 0000 to
197F FFFF

6400 0000 to
65FF FFFF

0980 0000 to
09FF FFFF

2600 0000 to
27FF FFFF

1980 0000 to
19FF FFFF

6600 0000 to
67FF FFFF

0A00 0000 to
0A7F FFFF

2800 0000 to
29FF FFFF

1A00 0000 to
1A7F FFFF

6800 0000 to
69FF FFFF

0A80 0000 to
0AFF FFFF

2A00 0000 to
2BFF FFFF

1A80 0000 to
1AFF FFFF

6A00 0000 to
6BFF FFFF

0B00 0000 to
0B7F FFFF

2C00 0000 to
2DFF FFFF

1B00 0000 to
1B7F FFFF

6C00 0000 to
6DFF FFFF

0B80 0000 to
0BFF FFFF

2E00 0000 to
2FFF FFFF

1B80 0000 to
1BFF FFFF

6E00 0000 to
6FFF FFFF

0C00 0000 to
0C7F FFFF

3000 0000 to
31FF FFFF

1C00 0000 to
1C7F FFFF

7000 0000 to
71FF FFFF

0C80 0000 to
0CFF FFFF

3200 0000 to
33FF FFFF

1C80 0000 to
1CFF FFFF

7200 0000 to
73FF FFFF

0D00 0000 to
0D7F FFFF

3400 0000 to
35FF FFFF

1D00 0000 to
1D7F FFFF

7400 0000 to
75FF FFFF

0D80 0000 to
0DFF FFFF

3600 0000 to
37FF FFFF

1D80 0000 to
1DFF FFFF

7600 0000 to
77FF FFFF

0E00 0000 to
0E7F FFFF

3800 0000 to
39FF FFFF

1E00 0000 to
1E7F FFFF

7800 0000 to
79FF FFFF

0E80 0000 to
0EFF FFFF

3A00 0000 to
3BFF FFFF

1E80 0000 to
1EFF FFFF

7A80 0000 to
7BFF FFFF

0F00 0000 to
0F7F FFFF

3C00 0000 to
3DFF FFFF

1F00 to
1F7F FFFF

7C00 0000 to
7DFF FFFF

0F80 0000 to
0FFF FFFF

3E00 0000 to
3FFF FFFF

1F80 0000 to
1FFF FFFF

7E00 0000 to
7FFF FFFF

Registers 7-19

FADR—Failing Address Register
Address
Access

BB + 2100
RO
The FADR register contains the failing 32-bit LSB address any time
the 64-bit ECC logic detects an ECC error during memory reads.
This register is locked upon either a correctable or uncorrectable
ECC error.

FADR
BXB-0214-92

Table 7-14

FADR Register Bit Definitions

Name

Bit(s)

Type

Function

FADR

<31:0>

Failing Address. Contains the LSB address driven
on D<31:0> during a command/address cycle. The
failing address bits are saved when the memory interface controller detects either a correctable or
uncorrectable ECC error within the 64-bit ECC logic
during LSB memory read transactions. If this field is
already locked with the failing address of a
correctable ECC error when an uncorrectable ECC
error occurs, it is updated with the failing address of
the uncorrectable error.

NOTE: The FADR register does not capture the entire LSB address. It drops address bits D<34:32>.

7-20 Registers

MERA—Memory Error Register A
Address
Access

BB + 2140
R/W
The MERA register provides additional error information about
node-specific error conditions that are captured in the MIC-A.
This register includes two bits that, when set, indicate the occurrence of an error on the MIC-B.

12 11 10

RSVD

FSTR
UCERB
UCERA
BNKER
CERB
CERA
APER
MULE
UCER
CER
BXB-0219 -92

Table 7-15

MERA Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:12>

Reserved. Read as zero.

Registers 7-21

Table 7-15 MERA Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

UCERB

<11>

W1C, 0

Uncontrollable Error on MIC-B. Set when MICB detects an uncorrectable 64-bit ECC error. The
high state of this bit locks bits <8:6> of this register
and the contents of the FADR register. It also
blocks UCERA (MERA<10>) from being set. If
MIC-A and MIC-B were to detect simultaneous 64bit ECC errors, then either bits <11> and <10>, or
bits <5> and <4> would be set at the same time.
The failing string and the address in the FADR register would pertain to failures detected in both MICA and MIC-B. If either MIC-A or MIC-B detects an
error, then the setting of the appropriate bit and the
blocking of the other bit in the combination allows
isolation of independent failures on MIC-A or MICB to the failing string and LSB address.

UCERA

<10>

W1C, 0

Uncorrectable Error on MIC-A. Set when MICA detects an uncorrectable 64-bit ECC error. The
high state of this bit locks bits <8:6> of this register
and the contents of the FADR register. It also
blocks UCERB (MERA<11>) from being set. See description of UCERB above.

BNKER

<9>

W1C, 0

Bank Conflict Error. When set, indicates that an
LSB request was made to a currently active memory
bank. When this bit is set, LSB ERR is asserted.

FSTR

<8:6>

RO, 0

Failing String. Indicates which of the eight
strings were being accessed during an LSB memory
read when an uncorrectable or correctable ECC error was detected by memory’s 64-bit ECC logic. This
field, along with the two syndrome registers, isolates single-bit errors to a failing DRAM component.
FSTR is locked when a correctable or uncorrectable
error bit is set in either MIC-A or MIC-B. If this
field is already locked with the failing address of a
correctable ECC error when an uncorrectable ECC
error occurs, it is updated with the failing address of
the uncorrectable error.

CERB

<5>

W1C, 0

Correctable ECC Error on MIC-B. Set when a
correctable ECC error is detected on MIC-B. The
high state of this bit locks bits <8:6> of this register
and the contents of the FADR register. It also
blocks CERA MERA<4>) from being set. See description of UCERB (MERA<11>) above.

7-22 Registers

Table 7-15 MERA Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

CERA

<4>

W1C, 0

Correctable ECC Error on MIC-A. Set when a
correctable ECC error is detected on MIC-A. The high
state of this bit locks bits <8:6> of this register, the
contents of the FADR register and the contents of the
MSYNDA register. It also blocks CERB (MERA<5>)
from being set. See description of UCERB
(MERA<11>) above.

APER

<3>

W1C, 0

Address Parity Error. Set when a row or column
address parity error is detected. If APER is set,
UCERA (MERA<1>) is also set.

MULE

<2>

W1C, 0

Multiple Errors. Set when a second correctable or
uncorrectable error is detected after either UCER
(MERA<1>) or CER (MERA<0>) has been set. This
bit sets only if an error is detected on a subsequent
read transaction. It does not set if multiple errors are
detected within the same transaction.

UCER

<1>

W1C, 0

Uncorrectable Read Error. Set when an
uncorrectable read data error is detected within
memory’s 64-bit ECC logic protecting D<63:0>. Memory supplies the data with uncorrectable errors forced
on LSB check bits ECC<13:0>. When this bit sets, the
Memory Error Syndrome Register A is locked with
the failing syndrome.

CER

<0>

W1C, 0

Correctable Read Error. Set when a correctable
read data error is detected within memory’s 64-bit
ECC logic protecting D<63:0>. Memory corrects the
data in error and supplies good data to LSB. When
this bit sets, the Memory Error Syndrome Register A
is locked with the failing syndrome.

Registers 7-23

MSYNDA—Memory Error Syndrome Register A
Address
Access

BB + 2180
RO
The MSYNDA register is used to determine which bit is in error
when a correctable ECC error is detected by the module during an
LSB memory read transaction. This register contains the syndrome bits generated by memory’s 64-bit ECC logic protecting
D<63:0>. The error syndrome is decoded by software to the bit in
error so that it can be logged accordingly. This register is locked
when either a correctable read error bit (CER) or an uncorrectable
read error bit (UCER) is set in the MERA register. MSYNDA is
unlocked when the error bit or bits are cleared in the MERA register. If this register is already locked with the failing syndrome of a
correctable ECC error when an uncorrectable ECC error occurs, it
is updated with the uncorrectable error syndrome.

RSVD

SYNDA
BXB-0223-92

Table 7-16

MSYNDA Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:8>

Reserved. Read as zero.

SYNDA

<7:0>

RO, 0

Syndrome A. Contains the error syndrome protecting D<63:0>.

7-24 Registers

MDRA—Memory Diagnostic Register A
Address
Access

BB + 21C0
R/W
The MDRA register is used by diagnostics to help isolate failures
and to force specific error conditions within the module and the
MIC-A chip. When MDRA is written, MDRB<7:0> are written concurrently. This feature allows syncronization of diagnostic operations between MIC-A and MIC-B. Bits<7:0> of MDRA and MDRB
registers have one-to-one matching functions.
NOTE: This register is reserved for Digital use.

31 30 29 28 27 26

RFR

RSVD
DCRD
BRFSH
DRFSH

FCPE
FRPE
IGSB
MODE
STPM
EXST
BPAS
DWDC
DRDC
FCBS
BXB-0225-92

Table 7-17

MDRA Register Bit Definitions

Name

Bit(s)

Type

Function

DRFSH

<31>

R/W, 0

Disable Refresh. If set, "on-board" refresh of the
module is disabled and diagnostic burst refresh (see
BRFSH, MDRA<30>) is enabled. When this bit is set
concurrently with BRFSH, a burst refresh cycle is
executed.

Registers 7-25

Table 7-17 MDRA Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

BRFSH

<30>

WO, 0

Burst Refresh. When BRFSH is set, and DRFSH
(MDRA<31>) is also set, a single row address within
the accessed DRAMs is refreshed as per CAS before
RAS refresh operation. When this bit is set concurrently with DRFSH, a burst refresh cycle is executed.

RFR

<29:28>

R/W, 0

Refresh Rate. Determines the refresh rate of the
module.
MDRA<29:28>

Refresh Rate

00
01
10
11

1 x default
2 x default
4 x default
Reserved

DCRD

<27>

R/W, 0

Disable CRD Assertion. If set, LSB_CRD does not
assert when memory detects a read CRD error in the
64-bit ECC logic.

RSVD

<26:10>

Reserved. Read as zero.

FCPE

<9>

R/W, 0

Force Column Parity Error. If set, incorrect column address parity is written into the addressed location in memory.

FRPE

<8>

R/W, 0

Force Row Parity Error. If set, incorrect row address parity is written into the addressed location in
memory.

IGSB

<7>

R/W, 0

Ignore Single-Bit Self-Test Failures. If set, selftest logic does not report errors in the MSTR0/
MSTR1 registers when a single bit is detected to be
in error for each octaword read. Only errors of two or
more bits are reported.

MODE

<6>

R/W, 0

Self-Test Mode. If set, self-test executes a defined
"ones/zeros" data pattern when running under diagnostic control. Two passes are executed. In the first
pass, all data bits in an odd hexword address are
written with ones, while those in an even hexword
are written with zeros. In the second pass, hexword
addresses are written with inverse data patterns.

7-26 Registers

Table 7-17 MDRA Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

STPM

<5>

R/W, 0

Self-Test Pause Mode. If set, self-test completes
one of its three passes. To execute the next pass,
EXST (MDRA<4>) must be set. This feature is necessary for memory manufacturing tests. STPM must
be set at the start of each pass. Otherwise, self-test
begins at pass 1.

EXST

<4>

R/W, 1

Execute Self-Test. If EXST is set, memory self-test
is invoked. The self-test logic examines this bit to determine if self-test should be executed. This bit is set
upon system power-up or LSB reset. It is cleared
when self-test completes execution. It is also cleared
in diagnostic mode when STPM is set for each pass
that the self-test state machine completes.

BPAS

<3>

R/W, 0

Bypass. If set, both the read data path and write
data path ECC logic is bypassed to aid in memory
manufacturing tests. LSB ECC<7:0> is directly
mapped to the eight ECC check bits protecting
D<63:0> in the MIC-A.

DWDC

<2>

R/W, 0

Disable Write Data Correction. If set, ECC correction of LSB memory write data is disabled. Uncorrected data is written to memory with a no error
ECC check bit code. The setting of this bit affects
the correction of D<63:0>. Thirty-two bit ECC errors, if present, are logged.

DRDC

<1>

R/W, 0

Disable Read Data Correction. If set, ECC correction of memory read data is disabled. The setting of
this bit affects the correction of D<63:0>.

FCBS

<0>

R/W, 0

Force Check Bit Substitution. If set, the contents of the MCBSB register is gated into the 64-bit
write ECC logic in place of the DRAM check bits.
The setting of this bit affects D<63:0>.

Registers 7-27

MCBSA—Memory Check Bit Substitute Register A
Address
Access

BB + 2200
R/W
The MCBSA register is used to check the 64-bit ECC logic on the
memory module during memory read transactions. This register is
first loaded by diagnostics with substitute bits for DRAM check
bits. The contents of the MCBSA register is then written to a selected memory location. When the write transaction is complete,
each of the four octawords contains the substituted check bits and
data issued on the bus. The location in memory written with substitute check bits will contain an UNDEFINED ECC code. Software executing such tests must ensure that memory is initialized
to good ECC by reexecuting self-test or by other means.

RSVD

SCB_A
BXB-0221-92

Table 7-18

MCBSA Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:8>

Reserved. Read as zero.

SCB_A

<7:0>

R/W, 0

Substituted Check Bits A. SCB_A is used in place
of the DRAM check bits protecting D<63:0> when
DRDC (MDRA <1>) is set.

7-28 Registers

MERB—Memory Error Register B
Address
Access

BB + 4140
R/W
The MERB register provides additional error information about
node-specific error conditions that are captured in the MIC-B chip.

RSVD
APER
MULE
UCER
CER
BXB-0220 -92

Registers 7-29

Table 7-19

MERB Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:4>

Reserved. Read as zero.

APER

<3>

W1C, 0

Address Parity Error. Set when a row or column
address parity error is detected. If APER is set,
UCER (MERB<1>) is also set.

MULE

<2>

W1C, 0

Multiple Errors. Set when a second correctable or
uncorrectable error is detected after either UCER
(MERB<1>) or CER (MERB<0>) has been set. This
bit sets only if an error is detected on a subsequent
read transaction. It does not set if multiple errors
are detected within the same transaction.

UCER

<1>

W1C, 0

Uncorrectable Read Error. Set when an
uncorrectable read data error is detected within
memory’s 64-bit ECC logic protecting D<127:64>.
Memory supplies the data with uncorrectable errors
forced on LSB check bits ECC<27:14>. When this bit
sets, the Memory Error Syndrome Register A is
locked with the failing syndrome.

CER

<0>

W1C, 0

Correctable Read Error. Set when a correctable
read data error is detected within memory’s 64-bit
ECC logic protecting D<127:64>. Memory corrects
the data in error and supplies good data to the LSB.
When this bit sets, the Memory Error Syndrome
Register B is locked with the failing syndrome.

7-30 Registers

MSYNDB—Memory Error Syndrome Register B
Address
Access

BB + 4180
RO
The MSYNDB register is used to determine which bit is in error
when a correctable ECC error is detected by the module during an
LSB memory read transaction. This register contains the syndrome bits generated by memory’s 64-bit ECC logic protecting
D<63:0>. The error syndrome is decoded by software to the bit in
error so that it can be logged accordingly. This register is locked
when either a correctable read error bit (CER) or an uncorrectable
read error bit (UCER) is set in the MERB register. MSYNDB is unlocked when the error bit or bits are cleared in the MERB register.
If this register is already locked with the failing syndrome of a
correctable ECC error when an uncorrectable ECC error occurs, it
is updated with the uncorrectable error syndrome.

RSVD

SYNDB
BXB-0224-92

Table 7-20

MSYNDB Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:8>

Reserved. Read as zero.

SYNDB

<7:0>

RO, 0

Syndrome B. Contains the error syndrome protecting D<127:64>.

Registers 7-31

MDRB—Memory Diagnostic Register B
Address
Access

BB + 41C0
R/W
The MDRB register is used by diagnostics to help isolate failures
and to force specific error conditions within the module and the
MIC-B chip. When the MDRA register is written, MDRB<7:0> are
written concurrently. This feature allows syncronization of diagnostic operations between MIC-A and MIC-B. Bits<7:0> of MDRA
and MDRB registers have one to one matching functions.
NOTE: This register is reserved for Digital use.

RSVD
IGSB
MODE
STPM
EXST
BPAS
DWDC
DRDC
FCBS
BXB-0226-92

Table 7-21

MDRB Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:8>

Reserved. Read as zero.

IGSB

<7>

R/W, 0

Ignore Single-Bit Self-Test Failures. If set, selftest logic does not report errors in the MSTR0/
MSTR1 registers when a single bit is detected to be in
error for each octaword read. Only errors of two or
more bits are reported.

7-32 Registers

Table 7-21 MDRB Register Bit Definitions (Continued)
Name

Bit(s)

Type

Function

MODE

<6>

R/W, 0

Self-Test Mode. If set, self-test executes a defined
"ones/zeros" data pattern when running under diagnostic control. Two passes are executed. In the
first pass, all data bits in an odd hexword address
are written with ones, while those in an even
hexword are written with zeros. In the second pass,
hexword addresses are written with inverse data
patterns.

STPM

<5>

R/W, 0

Self-Test Pause Mode. If set, self-test completes
one of its three passes. To execute the next pass,
EXST (MDRB<4>) must be set. This feature is necessary for memory manufacturing tests. STPM must
be set at the start of each pass. Otherwise, self-test
begins at pass 1.

EXST

<4>

R/W, 0

Execute Self-Test. If EXST is set, memory selftest is invoked. The self-test logic examines this bit
to determine if self-test should be executed. This bit
is set upon system power-up or LSB reset. It is
cleared when self-test completes execution. It is also
cleared in diagnostic mode when STPM is set for
each pass that self-test completes.

BPAS

<3>

R/W, 0

Bypass. If set, both the read data path and write
data path ECC logic is bypassed to aid in memory
manufacturing tests. LSB ECC<15:8> is directly
mapped to the eight ECC check bits protecting
D<127:64> in the MIC-B chip.

DWDC

<2>

R/W, 0

Disable Write Data Correction. If set, ECC correction of LSB memory write data is disabled. Uncorrected data is written to memory with a no error
ECC check bit code. The setting of this bit affects
the correction of D<127:64>. Thirty-two bit ECC errors, if present, are logged.

DRDC

<1>

R/W, 0

Disable Read Data Correction. If set, ECC correction of memory read data is disabled. The setting
of this bit affects the correction of D<127:64>.

FCBS

<0>

R/W, 0

Force Check Bit Substitution. If set, the contents of the MCBSB register is gated into the 64-bit
write ECC logic in place of the DRAM check bits.
The setting of this bit affects D<127:64>.

Registers 7-33

MCBSB—Memory Check Bit Substitute Register B
Address
Access

BB + 2200
R/W
The MCBSB register is used to check the 64-bit ECC logic on the
memory module during memory read transactions. This register is
first loaded by diagnostics with substitute bits for DRAM check
bits. The contents of the MCBSB register is then written to a selected memory location. When the write transaction is complete,
each of the four octawords contains the substituted check bits and
data issued on the bus. The location in memory written with substitute check bits will contain an UNDEFINED ECC code. Software executing such tests must ensure that memory is initialized
to good ECC by reexecuting self-test or by other means.

RSVD

SCB_B
BXB-0222-92

Table 7-22

MCBSB Register Bit Definitions

Name

Bit(s)

Type

Function

RSVD

<31:8>

R/W, 0

Reserved. Read as zero.

SCB_B

<7:0>

R/W, 0

Substituted Check Bits B. SCB_B is used in place
of the DRAM check bits protecting D<127:64> when
DRDC (MDRB <1>) is set.

7-34 Registers

Chapter 8
Error Conditions

The memory module detects two categories of ECC errors:
•

Memory-related LSB errors

•

Memory-specific errors

This chapter describes the two types of errors and explains how they are
reported in error syndrome registers.

8.1 Memory-Related LSB Errors
In general, memory responds as follows to LSB errors it detects during
memory read or write transactions:
•

Command/Address Cycles
Memory reports parity errors that it detects during command/address
cycles and captures the contents of D<38:0> in the LBECR0 and
LBECR1 registers. It does not act on the command or the address.

•

CSR Write Data Cycles
Memory does not write CSR data to the specified memory CSR when a
parity error is detected. Memory asserts LSB ERR.

•

Memory Write Data Cycles
If a single-bit ECC error is detected on memory write data, the bit in
error is corrected before data is written to memory. If an uncorrectable
ECC error is detected on memory write data, no correction is made to
the data. The bad data is written to memory along with an
uncorrectable ECC code forced on the 64-bit ECC check bits.

•

Memory Read Data Cycles
See memory-specific ECC errors in the MERA and MERB registers.

8.2 Memory-Specific Errors
Memory-specific errors relate to the 64-bit ECC logic that protects the
DRAM array. These errors are reported in Memory Error Register A
(MERA) and Memory Error Register B (MERB). Memory-specific errors
are detected only during LSB memory reads.

8.3 Error Syndrome Decoding
On the LSB bus, data is protected by 32-bit ECC error logic. However, on
the memory module, error logic implements a 64-bit ECC. Therefore, conversion of quadword (64-bit) ECC to longword (32-bit) ECC must be per-

Error Conditions 8-1

formed on memory read data. Conversely, longword to quadword ECC is
performed on memory write data. The conversion logic is implemented on
the MIC.

8.3.1 Quadword Memory Error Syndrome Decoding
When an ECC error is detected by the 64-bit memory ECC logic, the error
syndrome registers MSYNDA/MSYNDB are locked. Each of these registers contains the error syndrome associated with a failure in either the
MERA register or the MERB register.
If a correctable or uncorrectable error bit is set, the error syndrome register will contain the failing syndrome. If the error is correctable, logging
software can use this information to determine the bit in error and log it
appropriately. This information is of little use, however, if the error is
uncorrectable.
Table 8-1 shows the 64-bit ECC codes used, with associated check bits for
each of the 64 data bits. Error logging software can use this table to determine the bit in error whenever single-bit errors are detected.

Table 8-1

Quadword Error Syndrome Table

8-2 Error Conditions

MIC-A Bit
in Error

MIC-B Bit
in Error

Syndrome Value
(Hex)

No Error
0
1
2
3
4
5
6
7
8
9
10

No Error
64
65
66
67
68
69
70
71
72
73
74

00
13
23
43
83
2F
F1
0D
07
D0
70
4F

Table 8-1 Quadword Error Syndrome Table (Continued)
MIC-A Bit
in Error

MIC-B Bit
in Error

Syndrome Value
(Hex)

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55

75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119

F8
61
62
64
68
1C
2C
4C
8C
15
25
45
85
19
29
49
89
1A
2A
4A
8A
51
52
54
58
91
92
94
98
A1
A2
A4
A8
31
32
34
38
16
26
46
89
1F
F2
0B
0E

Error Conditions 8-3

Table 8-1 Quadword Error Syndrome Table (Continued)
MIC-A Bit
in Error

MIC-B Bit
in Error

Syndrome Value
(Hex)

56
57
58
59
60
61
62
63
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Row Parity
Column Parity

120
121
122
123
124
125
126
127
CB8
CB9
CB10
CB11
CB12
CB13
CB14
CB15
FD
FE

B0
E0
8F
F4
C1
C2
C4
C8
01
02
04
08
10
20
40
80

8.3.2 Longword Memory Error Syndrome Decoding
When an ECC error is detected by the LSB ECC logic, the error syndrome
registers LBESR0–3 are locked. Each of these registers contains the error
syndrome associated with a failure as seen on the LSB bus.
If a correctable or uncorrectable error bit is set, the error syndrome register will contain the failing syndrome. If the error is correctable, logging
software can use this information to determine the bit in error and log it
appropriately. This information is of little use, however, if the error is
uncorrectable.
Table 8-2 shows the 32-bit ECC codes used, with associated check bits for
each of the 32 data bits. Error logging software can use this table to determine the bit in error whenever single-bit errors are detected.

8-4 Error Conditions

Table 8-2

Longword LSB Error Syndrome Table
MIC-A Bit
in Error

MIC-B Bit
in Error

Syndrome Value
(Hex)

No Error
0,32
1,33
2,34
3,35
4,36
5,37
6,38
7,39
8,40
9,41
10,42
11,43
12,44
13,45
14,46
15,47
16,48
17,49
18,50
19,51
20,52
21,53
22,54
23,55
24,56
25,57
26,58
27,59
28,60
29,61
30,62
31,63
CB0,CB7
CB1,CB8
CB2,CB9
CB3,CB10
CB4,CB11
CB5,CB12
CB6,CB13
Cycle-0
Cycle-1

No Error
64,96
65,97
66,98
67,99
68,100
69,101
70,102
71,103
72,104
73,105
74,106
75,107
76,108
77,109
78,110
79,111
80,112
81,113
82,114
83,115
84,116
85,117
86,118
87,119
88,120
89,121
90,122
91,123
92,124
93,125
94,126
95,127
CB14,CB21
CB15,CB22
CB16,CB23
CB17,CB24
CB18,CB25
CB19,CB26
CB20,CB27
7A
79

00
4F
4A
52
54
57
58
5B
5D
23
25
26
29
2A
2C
31
34
0E
0B
13
15
16
19
1A
1C
62
64
67
68
6B
6D
70
75
01
02
04
08
10
20
40

Error Conditions 8-5

Chapter 9
Self-Test

The memory self-test performs a quick testing of the DRAM array and records sections of the array that contain defective locations. This occurs
automatically at system power-up upon assertion of LSB RESET. Selftest may be invoked by setting EXST (MDRA/MDRB<4>) through a console deposit command.

9.1 Self-Test Report
When the memory module starts self-test, it sets STF (LCNR<31>). The
memory self-test does not provide a pass/fail status. It flags the defective
segments in memory by setting associated bits in the MSTR0 and MSTR1
registers (see Table 7-13) and clears EXST and STF when it is done.
Clearing of STF lights the module LED, indicating the completion of the
test procedures.
Address segments are mapped according to the module’s total possible capacity (maximum of 8 strings), not to the actual memory capacity implemented on the module. For example, the maximum possible capacity of a
memory module using 4-Mbit DRAMs is 512 Mbytes (2 Gbytes for 16Mbit DRAMs). In this configuration, each bit in the MSTR0 and MSTR1
registers is associated with an 8-Mbyte segment of memory (32 Mbytes
for 16-Mbit DRAMs). Bit zero of MSTR0 describes an address segment
from 0 to 8 Mbytes (0 to 32 Mbytes for 16-Mbit DRAMs); bit one describes
an address segment from 8 to 16 Mbytes (32 to 64 Mbytes for 16-bit
DRAMs), and so on.

9.2 Self-Test Modes
Self-test can be conducted in several different operating modes selected
by configuring the MDRA and MDRB registers. One mode of operation
causes the self-test logic to ignore all single-bit errors. When this mode is
selected, single-bit failures do not set any of the 64 address segment bits
in MSTR0 or MSTR1. However, if a multiple-bit error is detected in a
memory segment, the associated address segment is set. By default,
single-bit errors are recorded in MSTR0 and MSTR1.

Self-Test 9-1

9.3 Self-Test Performance
The duration of the memory self-test is affected by the following parameters:
•

Memory array capacity

•

Memory array architecture

•

DRAM size

•

DRAM speed

The capacity of the memory module is the main factor that determines the
length of self-test. Table 9-1 shows self-test times for memory modules of
different capacities.

Table 9-1

Memory Self-Test Times
Module Capacity
(Mbytes)
64
128
256
512
1024
2028
1 Not applicable.

9-2 Self-Test

Self-Test Duration (Seconds)
4-Mbit DRAM
16-Mbit DRAM
1.3
1.3
2.7
5.4
N/A
N/A

N/A1
N/A
5.4
5.4
10.7
21.4

Index

A
Acronyms, bit access type, 7-2
Addresses, node space base, 7-1
Address decode logic, 2-2
Address Mapping Register, 7-14
Address Parity Error, 7-23, 7-30
Address Width, 7-15
AMR, 7-14
APER, 7-23, 7-30
Arbitration request, 5-2
Array capacity, 4-1
AW, 7-15

B
Banking, memory, 4-1
Bank Conflict Error, 7-22
Base addresses, 7-1
Bit designations, viii
Block diagram, 1-2
BNKER, 7-22
BPAS, 7-27, 7-33
BRFSH, 7-26
Burst Refresh, 7-26
Bus Error Register, 7-5
Bypass, 7-27, 7-33

C
CA, 5-2, 7-10, 7-11
CAE, 7-6
Capacity, memory, 4-1
CDPE, 7-6
CDPE2, 7-6
CE, 7-6
CEEN, 7-7
CER, 7-23, 7-30
CERA, 7-23
CERB, 7-22
CE2, 7-6
CID, 7-11
CMD, 7-11
CNF, 5-2, 7-11
CNFE, 7-6
CNF Error, 7-6

Command, 7-11
Commander ID, 7-11
Commands, 2-2
Command decode logic, 2-2
Command Parity Error, 7-6
Command/Address, 5-2, 7-10, 7-11
Command/Address Error, 7-6
Configuration Register, 7-7
Confirmation, 5-2, 7-11
Control Transmit Check Error, 7-6
Conventions, viii
Conversion, ECC, 6-2
Correctable Data Error, 7-6
Correctable ECC Error on MIC-A, 7-23
Correctable ECC Error on MIC-B, 7-22
Correctable Error Detection Enable, 7-7
Correctable Read Error, 7-23, 7-30
CPE, 7-6
CPE2, 7-6
CSR Data Parity Error, 7-6
CTCE, 7-6
Cycle times, 2-4

D
Data, 5-2
Data cycle, 7-10
Data path, MDC, 3-1
Data Transmit Check Error, 7-6
Data wrapping, 2-4
DCRD, 7-26
DCYCLE, 7-10
Default Interleave, 4-3
Device Register, 7-4
Device revision, 7-4
Device Type, 7-13
DIE, 7-6
DIRTY, 5-2, 7-11
Disable CRD Assertion, 7-26
Disable Read Data Correction, 7-27, 7-33
Disable Refresh, 7-25
Disable Write Data Correction, 7-27, 7-33
DRAM address logic, 2-3
DRAM arrays, 1-3
DRAM control logic, 2-3

Index-1

DRDC, 7-27, 7-33
DREV, 7-4
DRFSH, 7-25
DTCE, 7-6
DTYP, 7-13
DTYPE, 7-4
DWDC, 7-27, 7-33

E, 7-6, 7-16
ECC, 5-2
ECC conversion, 6-2
Enable, 7-16
ERR, 5-2
Error, 5-2
Errors, memory-related, 8-1
Errors, memory-specific, 8-1
Error address segments, 7-18, 7-19
Error bit, 7-6
Error checking and correction, 5-2
Error Command Register, 7-10
Error conditions, 8-1
Error Register, Bus, 7-5
Error syndrome decoding, 8-1
Error syndrome decoding, longword, 8-4
Error syndrome decoding, quadword, 8-2
Error Syndrome Register, 7-9
Execute self-test, 7-27
Execute Self_Test, 7-33
EXST, 7-27, 7-33

LBECR, 7-10
LBER, 7-5
LBESR, 7-9
LCNR, 7-7
LDEV, 7-4
Logic
address decode, 2-2
command decode, 2-2
DRAM address, 2-3
DRAM control, 2-3
LSB state machine, 2-5
MIC data path, 2-3
refresh, 2-4
self-test, 2-5
Longword error syndrome decoding, 8-4
LSB CA, 5-3
LSB CNF, 5-3
LSB commands, 2-2
LSB cycle times, 2-4
LSB DIRTY, 5-3
LSB ERR, 5-3
LSB errors, memory-related, 8-1
LSB memory signals, 5-1
LSB NID, 5-3
LSB PH0, 5-3
LSB REQ, 5-4
LSB RESET, 5-4
LSB STALL, 5-4
LSB state machine control logic, 2-5

FADR, 7-20
Failing Address, 7-20
Failing Address Register, 7-20
FCBS, 7-27, 7-33
FCPE, 7-26
Force Check Bit Substitution, 7-27, 7-33
Force Column Parity Error, 7-26
Force Row Parity Error, 7-26
FRPE, 7-26
FSTR, 7-22

MADR, 7-14
MCBSA, 7-28
MCBSB, 7-34
MCR, 7-12
MDC, 3-1
MDC data path, 3-1
MDC transactions, 3-1
MDC wrap ordering, 3-2
MDRA, 7-25
MDRB, 7-32
Memory banking, 4-1
Memory block diagram, 1-2
Memory capacity, 4-1
Memory Check Bit Substitution A, 7-28
Memory Check Bit Substitution B, 7-34
Memory Configuration Register, 7-12
Memory data controller, 1-3, 3-1
Memory Diagnostic Register A, 7-25
Memory Diagnostic Register B, 7-32
Memory Error Register A, 7-21
Memory Error Register B, 7-29
Memory Error Syndrome Register A, 7-24
Memory Error Syndrome Register B, 7-31

I
IA, 7-16
IBR, 7-8
Ignore Single-Bit Self-Test Failures, 7-32
IGSB, 7-26, 7-32
Information Base Register, 7-8
Interleave, 4-3, 7-16
Interleave Address, 7-16
Interleaving, 4-2
Internal buses, 1-3
INTL, 7-16

Index-2

Memory interface controller, 1-2, 2-1
Memory interleaving, 4-2
Memory module overview, 1-1
Memory organization, 4-1
Memory refresh, 1-3
Memory Self-Test Register, 7-17
Memory signals, 5-1
Memory space transactions, 2-3
Memory transactions, 6-1
ordering, 6-2
read, 6-1
write, 6-1
Memory-related LSB errors, 8-1
Memory-specific errors, 8-1
MERA, 7-21
MERB, 7-29
MIC, 2-1
MIC data path logic, 2-3
MODE, 7-26, 7-33
Module Address, 7-14
Module block diagram, 1-2
MSTR, 7-17
MSYNDA, 7-24
MSYNDB, 7-31
MULE, 7-23, 7-30
Multiple Errors, 7-23, 7-30

N
NBANKS, 7-15
NHALT, 7-7
NID, 5-2
Node Halt, 7-7
Node ID, 5-2
Node Reset, 7-7
Node space base addresses, 7-1
Node space CSR transactions, 2-2
Node-Specific Error Summary, 7-6
Nonexistent address error, 7-6
NRST, 7-7
NSES, 7-6
Number of Banks, 7-15
NXAE, 7-6

O
Ordering, MDC wrap, 3-2
Ordering, memory transactions, 6-2
Overview, 1-1

P
Parity, 7-11
PH0 (SINE), 5-2

Q
Quadword error syndrome decoding, 8-2

R
RCV_SDAT, 7-8
Read transactions, 3-1, 6-1
Receive Serial Data, 7-8
Refresh logic, 2-4
Refresh RAM, 1-3
Refresh Rate, 7-26
Refresh rates, 2-4
Register
Address Mapping, 7-14
Bus Error, 7-5
Configuration, 7-7
descriptions, 7-3
Device, 7-4
Error Command, 7-10
Error Syndrome, 7-9
Failing Address, 7-20
Information Base Repair, 7-8
Memory Check Bit Substitution A, 7-28
Memory Check Bit Substitution B, 7-34
Memory Configuration, 7-12
Memory Diagnostic A, 7-25
Memory Diagnostic B, 7-32
Memory Error A, 7-21
Memory Error B, 7-29
Memory Error Syndrome A, 7-24
Memory Error Syndrome B, 7-31
Memory Self-Test, 7-17
table, 7-3
Registers, 7-1
Register bit designations, viii
REQ, 5-2
RESET, 5-2
Reset Status, 7-7
RFR, 7-26
RSTSTAT, 7-7

S
SCB_A, 7-28
SCB_B, 7-34
SCLK, 7-8
Second Command Parity Error, 7-6
Second Correctable Data Error, 7-6
Second CSR Parity Error, 7-6
Second Uncorrectable Data Error, 7-6
Segments, memory error address, 7-18, 7-19
Self-Test, 9-1
Self-Test Fail, 7-7
Self-Test Failing Address Segment, 7-17
Self-Test logic, 2-5
Self-Test Mode, 7-26, 7-33
Self-test modes, 9-1
Self-Test Pause Mode, 7-27, 7-33
Self-test performance, 9-2
Self-test report, 9-1

Index-3

Self-test times, 9-2
Serial Clock, 7-8
SHARED, 7-11
SHARED Error, 7-6
SHE, 7-6
Signal descriptions
LASB RESET, 5-4
LSB CA, 5-3
LSB CNF, 5-3
LSB Data D<127:0>, 5-1
LSB DIRTY, 5-3
LSB ERR, 5-3
LSB NID, 5-3
LSB PH0, 5-3
LSB REQ, 5-4
LSB STALL, 5-4
Sine, 5-2
STALL, 5-2
Stalled read transactions, 6-1
Stalled write transactions, 6-2
STALL Error, 7-6
STE, 7-6
STF, 7-7
STFAS, 7-17
STPM, 7-27, 7-33
STRG, 7-13
String, 7-13
Substituted Check Bits A, 7-28
Substituted Check Bits B, 7-34
SYDROME_0, 7-9
SYDROME_1, 7-9
SYDROME_2, 7-9
SYDROME_3, 7-9
SYNDA, 7-24
SYNDB, 7-31
Syndrome A, 7-24
Syndrome B, 7-31
System interleave, 4-3

T
TDE, 7-6
Terminology, ix
Transactions
memory, 6-1
memory read, 6-1
memory space, 2-3
node space CSR, 2-2
read, 6-1
wrapped read, 3-1
wrapped write, 3-2
write, 6-1
Transaction ordering, 6-2
Transmitter During Error, 7-6
Transmit Serial Data, 7-8

Index-4

U
UCE, 7-6
UCER, 7-23, 7-30
UCERA, 7-22
UCERB, 7-22
UCE2, 7-6
Uncorrectable Data Error, 7-6
Uncorrectable Error on MIC-A, 7-22
Uncorrectable Error on MIC-B, 7-22
Uncorrectable Read Error, 7-23, 7-30

W
Wrapped read transactions, 3-1
Wrapped write transactions, 3-2
Wrapping, data, 2-4
Write transactions, 6-1

X
XMT_SDAT, 7-8