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Document:	MS11-M MOS Memory User Guide
Order Number:	EK-MS11M-UG
Revision:	001
Pages:	28
Original Filename:

OCR Text

MS11-M MOS memory
user guide

dlifgliltiall

EK-MS11M-UG-001

MS11-M MOS memory
user guide

digital equipment corporation - maynard, massachusetts

Ist Edition, May 1979

subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM

UNIBUS

VAX

MASSBUS
OMNIBUS
OS/8
RSTS
RSX

VMS

IAS

6/82-15

CONTENTS
CHAPTER 1

CHARACTERISTICS AND SPECIFICATIONS

1-1
1-2
1-3
1-3

Functional Specifications ........... .. ... . i 1-3
Electrical Specifications ...............i
i
i 1-4

GENERAL DESCRIPTION ................. e
e
DATI or DATIP Data Transfer............
...
..
DATO or DATOB Data Transfer .. ......... ... ... ..
..
SPECIFICATIONS .
e e e e e e e e

e T

o
—

e T

INTRODUCTION ...... ..o ee 1-1

Physical and Environmental Specifications. ............................

1-5

RELATED DOCUMENT
S ... . e
e 1-5

CHAPTER 2

INSTALLATION AND PROGRAMMING

2.1

GENE RAL . .

2.2

INST ALLATION ...

2.2.1

e e 2-1
e

e, 2-1

Switch and Jumper Configurations .. ................
...
.o, 2-1

2.2.1.1

Memory Addressing........ e

2.2.1.2

CSR Address Selection. . ...........c. i, 2-6

2.2.2

Backplane Placement. .. ........ ... ...

2.2.3

Power Voltage Check ........ .. .

224

2.3
2.3.1

e
. .

e 2-7

MAINDEC Testing. . ....oovii

2-2

e e

i, 2-7

e 2-7

CSR BIT ASSIGNMENT. ... .. e 2-7
Notes on CSR USage . ...t
e 2-11

FIGURES
Figure No.

Title

2-1

Switch and Jumper Locations ............
... .., 2-1

2-2

Bus Accessible Data Locations . .............
... ... 2-2

2-3

Interleaved

Versus

Noninterleaved

Memory

Organization

Two

128K Memory Banks . ...
2-4

2-5

CSR Bit Allocation . ... ...
e e e e 2-9

TABLES

Access and Cycle Times..................... e 1-4

MSIT1-M Pin Out. .. ...
e e e e e e 2-8

l\)l\)t\)ll\Jl\)'—‘*—‘

h W=
W
-

Title

[S—

Table No.

Current Requirements . ...................... e

e e 1-4

Total Module Power Requirements.............. e

e e

1-5

MS11-M Address Ranges (Noninterleaved) . .. ... e 2-3
Starting Address Configurations ................ ee 2-4
Interleave Mode Selection ..................... ee 2-6

CSR Address Selection........................ ee 2-6

TEEARSS AdorrAdhoARdsAotReIibo0dHtOs

X(ENFERTEE RXPAN
B

MSI11 M MOS Memory

e, ISLKe2R2kALEARS

pom Tz PR

YLRR R ISFEERFERFD-

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CHAPTER 1

CHARACTERISTICS AND SPECIFICATIONS

1.1
INTRODUCTION
The MS11-M is a metal oxide semiconductor (MOS), random access memory (RAM), designed to be

used with the PDP-11 Unibus or extended Unibus. The memory assumes the role of a slave device to
the PDP-11 processor or to any peripheral device designated bus master. The MS11-M utilizes an error
correction code (ECC) to increase the reliability of the memory. There are two versions of the MS11M: the MS11-MA (M8722-AA) which provides 64K X 16-bit data storage; and the MSII-MB
(M&722-BA) which provides 128K X 16-bit data storage. Note that the two versions are differentiated
by the total memory capacity available on the module.
1.2

GENERAL DESCRIPTION

The MSI11-M consists of a single hex-height module (M8722) that contains the Unibus/extended

Unibus interface, timing and control logic, error correcting code (ECC) logic, and a MOS storage
array. The module also contains circuitry for ECC-initialization and memory refresh, and a control
and status register (CSR).

The memory starting address can be set at any 64K boundary within the 128 K Unibus address space or

2048K extended Unibus address space. (The extended Unibus contains 22 address lines as opposed to
18 Unibus address lines.) The MSI11-M reserves the top 4K of the Unibus or extended Unibus address

space for the /O peripheral page. The MS11-M also allows address interleaving between two memory
modules that have the same storage capacity.

The MOS storage array is configured in 39-bit words which consist of 2 16-bit PDP-11 words and 7

check bits generated by the ECC logic. The error correction code allows the MSI11-M to detect a
single-bit or double-bit error within the 39-bit word, and to correct a single-bit data error. A double-bit
error 1s not corrected by the MS11-M and can cause a parity error trap. A single-bit error is transparent to the Unibus/extended Unibus.
The memory storage elements are 16384 X 1-bit, MOS dynamic RAM devices. The MOS storage array

contains 39 of these devices for each 32K bank of PDP-11 memory;e.g., a 128K memory contains 156
storage devices, a 64K memory contains 78 storage devices. The MOS storage devices are periodically

refreshed by specially-timed, refresh cycles, executed by the MS11-M so that the data and check bits
remain valid.

Since the MOS storage devices are volatile (data is not retained when power is lost), a battery backup
unit is available as an option to support the MOS power supply regulator(s). Therefore, dc power is
available to MOS memory only for a limited time during an ac power failure. The MS11-M memory
module has inputs for £12 V power and two sources of +5 V power, designated +5 VBB and +5 V.
The £12 V and +5 VBB module inputs are battery supported during an ac power failure; the +5 V

input is not battery supported. The power distribution lines on the module are arranged to accommodate the use of the battery backup option. In the battery support mode, power is used only to

refresh the MOS storage array so that battery backup time and therefore data retention time are
maximized. A green LED on the module stays on as long as power is applied to the +5 VBB input.

1-1

If +5 VBB (and therefore data) was lost during an ac power failure, the MS11-M performs an error

correction initialize (ECC INIT) operation after the power-up. For an ECC INIT operation, logical Os
and the corresponding check bit pattern are written twice into all 39-bit word locations in the MOS
storage array. Signal AC LO is asserted by the memory while the ECC INIT operation is in progress.

The control and status register (CSR) in the MS11-M allows program control of certain ECC functions and stores diagnostic information if an error has occurred. The CSR has its own address in the
/O peripheral page, and can be read or written into by any device designated as bus master, even

during a memory refresh cycle.
Although the MOS storage array is configured in 39-bit words, the bus master sees the MSI11-M as a

standard 16-bit memory. The memory response to the four types of data transfers (DATI, DATIP,
DATO, and DATOB) is discussed in the following paragraphs.

1.2.1
DATI or DATIP Data Transfer
Memory responds to a DATI or DATIP data transfer by performing a read cycle. (A DATIP data

transfer is interpreted as a DATI.) The 39-bit word which contains the requested data is retrieved from
the MOS storage array, and 7 check bits are calculated based on the 32 retrieved data bits. The newly
calculated check bits are then compared to the seven retrieved check bits, creating seven syndrome bits.
A logical | in the syndrome bit pattern indicates an error in the 39-bit word; an odd number oflogical
Is indicates a single-bit error while an even number of logical 1s indicates a double-bit error. If no
error is detected, the memory places the requested 16-bit data on the Unibus/extended Unibus and
asserts the SSYN signal.

If a single-bit error is detected during a read cycle, the MSI1-M initiates the following action:
1.

A single-bit error within the 32 data bits is corrected

Bit 4 in the CSR is set to |

A partial address of the requested data is recorded in the CSR, if CSR bit I5is cleared to O

The requested 16-bit data and the SSYN signal are asserted on the Unibus/extended Unibus
after a delay of approximately 70 ns. Therefore, the memory access time is increased due to a
single-bit error.

Note that the syndrome bits are used to determine if the single-bit error is contained in the retrieved

data or check bits, and to isolate a bad data bit. A check bit error is not corrected; however, the other
single-bit error reactions are the same.

If a double-bit error is detected it is not corrected. However, the memory initiates the following actions:

Bit 15in the CSR is set to 1

A red LED on the module turns on, providing a visual indication of a double-bit (uncorrectable) error

A partial address of the requested data is recorded in the CSR. Any address information
relating to a previous error is destroyed

If bit 0 in the CSR is set, the memory asserts BUS PBL which warns the processor that a
double-bit (uncorrectable) error has occurred.

1-2

The requested 16-bit data and the SSYN signal are asserted on the Unibus/extended Unibus
after a delay of approximately 70 ns. Therefore, the memory access time 1s increased due to a
double-bit error.

1.2.2
DATO or DATOB Data Transfer
Memory responds to a DATO or DATOB data transfer by performing a read-modify-write (RMW)
cycle. During the first portion of the RMW cycle the data byte(s) supplied by the bus master are
latched-in from the Unibus/extended Unibus and the SSYN signal is asserted. The 39-bit word which
includes the desired PDP-11 location is then retrieved from the MOS storage array. Based on the 32
retrieved data bits, 7 check bits are calculated and then compared to the retrieved check bits, creating 7
syndrome bits. The syndrome bits are examined to determine if the 39-bit word contains a single-bit or
double-bit error. A single-bit error in the data is corrected, but a double-bit error in the 39-bit word is
not corrected.
The manipulation of data during the remaining portion of the RMW cycle is the same for a no error or
corrected error condition. The 39-bit word 1s modified by merging the data byte(s) supplied by the bus

master with the old data bytes from the storage array. Check bits are generated based on the four data

bytes, and the modified 39-bit word is then written into the MOS storage array. For a DATO data
transfer, the modifed 39-bit word contains 2 new bytes, two old bytes, and seven new check bits. For a
DATOB, the modified word contains one new byte, three old bytes and seven new check bits.

[f a double-bit error is detected during the first portion of the RMW cycle, the four bytes of old data

and the old check bits are rewritten into the MOS storage array. Therefore, the double-bit error is
preserved and will be flagged if the 39-bit word is retrieved during a DATI or DATIP data transfer.
The data supplied by the bus master is lost.
1.3
1.3.1

SPECIFICATIONS
Functional Specifications

Capacity
MSII-MA

65,536(64K) words

MS11-MB 131,072(128K) words

}

16-bit PDP-11 words

Refresh Timing

Cycle time

620 ns (typical), 675 ns (maximum)

Repetition rate

Onecycleevery:

12.5 microseconds (typical)
11.25 microseconds (fastest)
13.75 microseconds (slowest)
NOTE

Refresh cycle time is defined as the time interval be-

tween the assertion of REF REQ (1) H and the negation of MBSY L. These signals are internal to the
memory module.
ECC INIT Time

451 ms (maximum)

NOTE

ECC INIT time is defined as the time interval be-

tween the negation of DC LO (at the output of the
memory receiver) and the negation of AC LO (on the
Unibus/extended Unibus) by the memory.
Access and Cycle Times (Table 1-1)

1-3

Table 1-1

Access and Cycle Times

Access Time (ns)

Data Transfer

Typical

Maximum

Cycle Time (ns)
Typical
Maximum

DATI/DATIP (Memory)

490(560 w /err)

525(600 w/err)

450

DATO/DATOB (Memory)

220

250

950

500

1000

DATI/DATIP (CSR)

115

150

DATO/DATOB (CSR)

115

150

NOTES

Access time - The time interval between memory reception of MSYN (at the input of the bus receiver) and the
assertion of SSYN on the Unibus/extended Unibus.

Cycle time - The time interval between memory reception of MSYN (at the output of the bus receiver) and the
negation of MBSY L. Signal MBSY L is internal to the memory module.
2.

If the memory is accessed by a bus master during a refresh cycle, the data transfer is delayed until the refresh cycle is
completed. In the worst case, memory access and cycle times are increased by the entire refresh time; 620 ns
(typical), 675 ns (maximum). Access to the CSR is not affected by a refresh cycle.

1.3.2
Electrical Specifications
Voltage Requirements
+5V £5%, max ripple =0.2 V p-p
+5 VBB +£5%, max ripple =0.2 V p-p

+12V £5%, max ripple =1 Vp-p
-12V £10%, max ripple = 1 V p-p

Current and Power Requirements (Tables 1-2 and 1-3)

Table 1-2

+5V

Current Requirements

+5 VBB

-12V

+12V

Memory

Standby

Active

Option

Typ

Max

Typ

Max

Typ

Max

Typ

Max

Typ

Max

MSI11-MA
MSI11-MB

38A
38A

48 A
4.8 A

1.2A
1.2 A

I.5A
[.5A

25 mA
30 mA

50 mA
50 mA

0.15A
0.3A

02A
04A

0.55A
0.7A

08
A
1.0
A

NOTES

. The total module consumption of +5 V current during normal operation is equal to the sum of the +5V and +5 VBB
ratings.

. The standby and active ratings for +5V, +5 VBB and —12 V are the same. The current drawn from the +12 V supply
varies directly with the frequency of operation; e.g., the stated +12 V active ratings are obtained at a 1 microsecond
repetition rate. Interleaving can almost double the current drawn from the +12 V supply depending on bus overhead
(e.g., two interleaved MS11-MB modules can collectively consume up to 4 A as opposed to 2 A for the
noninterleaved case).

Table 1-3

Battery Backup Mode

Active

Standby

Memory

1.3.3

Total Module Power Requirements

Option

Typ

Max

Typ

Max

Typ

Max

MSII-MA
MSI11-MB

27.1' W
289 W

345W
36.9 W

319W
337 W

41.7W
441 W

8.1 W
99 W

10.5W
129 W

Physical and Environmental Specifications

Module designation

MS11-MA

ME8722-AA

All versions are hex-height multilayer, 21.6 X 38.1 cm

MSI11-MB

M&8722-BA

(8.5 X 15 inches)

Operating temperature

5to50° C(41°to122° F)

Humidity

10t0 95% (noncondensing)

1.4 RELATED DOCUMENTS
Additional reference information can be found in the documents listed below.

Title

Document No.

Availability

PDP-11 Peripherals Handbook
PDP-11/04/34/45/55/60 Processor Handbook
PDP-11/44 User’s Guide

EB-05961
EB-09340
EK-11044-UG

Hardcopy only
Hardcopy only
Hardcopy only

These documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532

Attn:

Communication Services (NR2/M15)
Customer Services Section

For information concerning Microfiche Libraries, contact:
Digital Equipment Corporation

Micropublishing Group
PK3-2/T12
Maynard, MA 01754

CHAPTER 2

INSTALLATION AND PROGRAMMING

2.1

GENERAL

This chapter presents the information necessary for installation and programming of the MS11-M and
applies to both versions of the memory. Installation procedures include: switch /jumper settings, backplane placement, power voltage checks, and MAINDEC testing. Programming information includes a
discussion of bit assignments in the control and status register (CSR).

2.2
2.2.1

INSTALLATION
Switch and Jumper Configurations

The MS11-M contains two jumpers and two switchpacks; one switchpack contains four switches (S1-1
through S1-4) and the other contains eight switches (S2-1 through S2-8). The location of the jumpers
and switches is shown in Figure 2-1. The switches are used to specify the memory starting address,
interleaved or noninterleaved operation, and the CSR address. Unibus or extended Unibus operation
is specified by jumper W1. Jumper W2 is related to the storage capacity of the memory and should not
be tampered with in the field.
S1

CSR ADDRESS

\ A—i—-f{%g INSTALL

1
4

LJ‘LJ’]

NOTES:

020
nsS—
=

" OPERATION
ONLY

FLIJJ
S2

JUMPER W1 IS AZERO OHM

FOR SETTING THE MEMORY

RESISTOR

STARTING ADDRESS AND FOR

JUMPER W2 IS NOT SHOWN SINCE IT

INTERLEAVE/NON-INTERLEAVE

SHOULD NOT BE TAMPERED WITH IN

SELECTION

THE FIELD

MA-3394

Figure 2-1

Switch and Jumper Locations

2-1

2.2.1.1

Memory Addressing

PDP-11 Memory Conventions — The MSI11-M can be used with the PDP-11

Unibus or extended

Unibus. Memory in these computer systems provides storage for 16-bit data words, each containing
two 8-bit bytes. These bytes are identified as low or high, as shown below.

]

HIGH BYTE

]

DATA BITS D <15:00>

MSB

LSB

MA-2458

Each byte is addressable and has its own address location; low bytes are even-numbered and high bytes
are odd-numbered. Words are addressed by even numbered locations only, and the high (odd) byte for
each word is automatically included.
Via the Unibus, 131,072 (128K) words or 262,144 (256K) bytes can be addressed; 2,097,152 (2048K)

words or 4,194,034 (4096K) bytes can be addressed via the extended Unibus. Each byte location in
Unibus memory is specified by a 6-digit octal number, but with the extended Unibus, 8-digit octal
numbers are used. The address range is 000000-777777 on the Unibus and 00000000-17777777 on the
extended Unibus (Figure 2-2).

UNIBUS ADDRESS SPACE

|15
<——

8|7

EXTENDE
UNIBUS ADDRESS SPACE
D

|15

8¥7

16 BIT WORD —
+«——

16BIT WORD—
{

HIGH BYTE! LOW BYTE

HIGH BYTE!LOW BYTE
000001

000000

00000001

00000000

000003

000002

00000003

00000002

000005

000004

00000005

00000004

777773

777772

17777773

17777772

777775

777774

17777775

17777774

777777

777776

17777777

17777776

MA-3392

Figure 2-2

Bus Accessible Data Locations

The memory address decoding logic responds to the binary equivalent of the octal address. The binary
equivalent of 00017772 is shown below. The MS11-M decodes an 18-bit address (A17-A00) on the
Unibus or a 22-bit address (A21-A00) on the extended Unibus.

ADDRESS BITS A <21:00>

BYTE

SELECTION

BITPOSITION

l—

UNIBUS ADDRESS

EXTENDED UNIBUS ADDRESS

[l=

| BINARY

OCTAL WORD

fiJ
MA-3393

The address space on a bus occupied by a memory module is determined by the memory starting

address, storage capacity, and interleaving information. A unique starting address is selected by
switches on the MS11-M which correspond to address bits A21-A17 on the extended Unibus or A17
on the Unibus. For noninterleaved operation, the block of addresses occupied by each module is
continuous. Table 2-1 lists the noninterleaved, octal address ranges of the MSI 1-M versions and the
associated address bits which determine the word location within the module. Address bit AQO is used
to select a data byte during a DATOB bus cycle.

Table 2-1

MSI11-M Address Ranges (Noninterleaved)

Memory

Octal Address

Associated

Designation

Storage Capacity

Range (Noninterleaved)

Address Bits

MSI1-MA

65,536 words

00000000-00377777

A 16-A00

00000000-00777777

Al17-A00

(131,072 bytes)

MSI11-MB

131,072 words
(262,144 bytes)

Memory Starting Address Selection - The memory starting address is the lowest bus address to which

the MSI11-M responds in the noninterleaved mode. The starting address must be assigned to a 64K
boundary within the 128K Unibus address space or 2048K extended Unibus address space. The start-

ing address is assigned by manually setting five switches, S2-1 through S2-35, to the appropriate positions for the desired location (Table 2-2).

2-3

Table 2-2

Starting Address

Starting Address Configurations

)

Switch Positions

S2-5

S2-4

Octal

(A21)

(A20)

00000000
00400000
01000000

ON
ON
ON

192K

01400000

256K
320K
384K
448K
512K
576K

02000000
02400000
03000000
03400000
04000000
04400000

640K

05000000

704K
768K
832K
896K
960K

05400000
06000000
06400000
07000000
07400000

1024K

10000000

OFF

1088K

10400000

OFF

152K

[ 1000000

OFF

Decimal
OK
64K
128K

S2-3

S2-2

S2-1

ON
ON
ON

ON
ON
OFF

ON
OFF
ON

OFF

ON
ON
ON
ON
ON
ON

ON
ON
ON
ON
OFF
OFF

OFF
OFF
OFF
OFF
ON
ON

ON
ON
OFF
OFF
ON
ON

ON
OFF
ON
OFF
ON
OFF

OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

OFF

(A19)

(A18)

(A17)

216K

1 1400000

OFF

1280K

12000000

OFF

344K

12400000

OFF

1408K

13000000

OFF

1472K

1 3400000

OFF

1536K
600K

14000000
14400000

OFF
OFF

ON
ON

ON
OFF

1664K

1 5000000

OFF

728K

1 5400000

OFF

1792K
1856K
1920K
1984K

16000000
16400000
17000000
17400000

OFF
OFF
OFF
OFF

ON
ON
OFF
OFF

ON
OFF
ON
OFF

Switches S2-1 through S2-5 correspond to address bits A17-A21 respectively on the extended Unibus.
A switch in the OFF position corresponds to a logical 1.
NOTE
Switches S2-2 through S2-5 should be set to the ON

position if the MS11-M is used with the PDP-11
Unibus.

Unibus or extended Unibus operation of the MSI1-M is selected by jumper W1:
W1 0UT

Specifies extended Unibus operation

W1 IN

Specifies Unibus operation

Interleave /Noninterleave Selection - A continuous (noninterleaved) address block can be assigned to
each MSI11-M module, or an address block can be interleaved between two MSI1-M modules that
have the same storage capacity. Figure 2-3 shows two 128K memories in the interleaved mode and the
corresponding noninterleaved mode.

256K NONINTERLEAVED MEMORY
MEMORY BANK 1

MEMORY BANK 2

|15

817

8 17

<«——
16 BITWORD——

<——16 BIT

WORD —»

HIGH BYTE | LOW BYTE

HIGH BYTE ! LOWBYTE
01000001

01000000

00000001

00000000

01000003

01000002

00000003

00000002

01000005

01000004

00000005

00000004

4,———~\<<

01777773

01777772

00777773

00777772

01777775

01777774

00777775

00777774

01777777

01777776

00777777

00777776

ASSIGNED STARTING ADDRESS = 01000000

ASSIGNED STARTING ADDRESS = 00000000

256K INTERLEAVED MEMORY

MEMORY BANK 2

{15

817

MEMORY BANK 1

|15

16 BIT WORD

HIGH BYTE,

817

<«— 16BITWORD ____

HIGHBYTE ! LOWBYTE

LOWBYTE

00000003

00000002

00000001

00000000

00000007

00000006

00000005

00000004

00000013

00000012

00000011

00000010

/——\

01777767

01777766

01777765

01777764

01777773

01777772

01777771

01777770

01777777

01777776

01777775

01777774

ASSIGNED STARTING ADDRESS = 00000000

ASSIGNED STARTING ADDRESS = 00000000
MA-3395

Figure 2-3

Interleaved Versus Noninterleaved Memory Organization of Two 128K Memory Banks

For noninterleaved operation of a 128K or 64K memory, switches S2-6 through S2-8 should be OFF

and each module should be assigned a unique starting address (Table 2-2).
Except for the address ranges involved, interleaved operation for two 64K memories is the same as for
two 128K memories. When two 128K modules are interleaved, one memory is assigned all the even
addressed words within a 256K block of word addresses; the second memory is assigned all the odd

addressed words in the same block. Address bit A0l is used to determine if a word is even or odd
addressed. If consecutively addressed words are accessed by the bus master for a DATO or DATOB
data transfer, the two memories are accessed alternately so the memory cycles can overlap. Therefore,
the bus master sees a reduction in memory cycle time (averaged over a number of DATO or DATOB
data transfers).

To specify interleaved operation, switches S2-6 through S2-8 should be set to the appropriate positions

on each module (Table 2-3), and both modules should be assigned the same starting address (Table 22). The assigned starting address for two interleaved 128K (64K) modules is the lowest address in the
256K (128K) block.
Table 2-3

Interleave Mode Selection

Switch Positions

Mode

S2-6

S2-7

S2-8

OFF

Noninterleaved memory

OFF

One interleaved memory: contains the even addressed words (A01 =0)

OFF

Second interleaved memory; contains the odd addressed words (AQO1=1)

NOTE

The five remaining switch configurations that are not
listed should never be used.
For interleaved operation on the extended Unibus, address bits A18-A02 determine the word location
within a 128K module; A17-A02 are used for a 64K module. Address bit AQO is used to select a data

byte duringa DATOB bus cycle. Note that on the Unibus only two 64K modules can be interleaved.
2.2.1.2
CSR Address Selection - The control and status register (CSR) can be read or written into via
the Unibus/extended Unibus, even during a memory refresh cycle. Address decoding logic in the
MS11-M specifies the CSR address in the range 772100-772136 for Unibus operation or 17772100~

17772136 for extended Unibus operation. Four switches, S1-1 through S1-4, select the exact CSR

address (Table 2-4). Switches S1-1 through S1-4 correspond to address bits A04-AO0l respectively; a
switch in the OFF position corresponds to a logical 1. The CSR is always accessed as an entire data
word since bit AOO is not decoded by the CSR address logic.

The CSR address has no relevance to the memory starting address, storage capacity, or interleave

mode of the MS11-M. However, for organizational purposes only, it may be helpful to assign the CSR
address in accordance with the assigned memory starting address (e.g., assign the lowest CSR address
to the module which has the lowest memory starting address). Between two interleaved modules,
assign the lower CSR address to the module that contains the even addressed words (Table 2-3).
Table 2-4

CSR Address Selection
Switch Positions

Unibus
Address

Extended Unibus
Address

S1-1
(A04)

S1-2
(A03)

S1-3
(A0Q2)

Si-4
(AO1)

772100
772102
772104
772106
772110
772112
772114
722116
772120

17772100
17772102
17772104
17772106
17772110
17772112
17772114
17772116
17772120

ON
ON
ON
ON
ON
ON
ON
ON
OFF

ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON

ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON

772122
772124
772126
772130
772132
772134
772136

17772122
17772124
17772126
17772130
17772132
17772134
17772136

OFF
OFF
OFF
OFF
OFF
OFF
OFF

2-6

ON
ON
ON
OFF
OFF
OFF
OFF

ON
OFF
OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF
ON
OFF

2.2.2

Backplane Placement

The MS11-M is compatible with the PDP-11 Unibus or the extended Unibus (EUB) which is the main
memory bus in the PDP-11/44.
When used with the PDP-11/44, the MS11-M should be inserted into any one of slots 9 through 12 in
the processor backplane (part no. 70-16502-00). Slots 9 through 12, sections A and B, contain the
extended Unibus.

For Unibus operation, the MS11-M should be inserted into any slot in a backplane that contains
modified Unibus connectors in sections A and B. For example:
DDII-D

Slots 2 through 8

DDI11-C

Slots
2 and 3

The MSI1-M and other memory types (except the MS11-L) are mutually exclusive with respect to the

backplane since the MS11-M requires £12 V power. The backplane connections used by the MS11-M
are listed in Table 2-5.

2.2.3

Power Voltage Check

Once primary power has been turned on, the dc power voltages listed below should be checked at the
backplane.
Voltage and Tolerance

Backplane Pin(s)

+5V £5%, max ripple = 0.2V p-p

AA2,BA2,CA2

+5 VBB +£5%, max ripple = 0.2V p-p

BDI

+12V £5%, maxripple = 1V p-p

-12V £10%, max ripple = 1 V p-p

ASI

2.2.4
MAINDEC Testing
The MSI1-L/M Memory Exerciser (MAINDEC-11-CZMSD) diagnostic program should be used
with the MSI11-M memory module. To verify proper operation of the memory, run two passes of the

diagnostic. No double errors are permitted. Also, verify that the program printout agrees with the total
memory in the system.

2.3
CSR BIT ASSIGNMENT
The control and status register (CSR) in the MS11-M allows program control of certain ECC functions and contains diagnostic information if an error has occurred. The CSR is assigned an address
and can be accessed by a bus master via the Unibus/extended Unibus, even during a memory refresh
cycle. Some CSR bits are cleared by the assertion of BUS INIT L. This signal is asserted for a short

time after system power has come up or in response to a reset instruction. The CSR bit assignments are
illustrated in Figure 2-4 and are described as follows:

Uncorrectable Error

Bit 0

This bit, when set to 1, allows the assertion of BUS PB L when
BUS SSYN L 1s asserted, if an uncorrectable error 1s detected

Indication Enable

during a memory read cycle (e.g., with error correction enabled,
BUS PB L is asserted for a double-bit error. With error correction disabled, BUS PB L is asserted for a single-bit or double-bit
error). Bit 0 can be read or loaded by the program (read/write
bit) and is cleared by BUS INIT L.

2-7

Table 2-5 MS11-M Pin Out
A

1
A

| INITL

+5V

NPG

+5Vv | -

IN H

| -

+5V

Battery

NPG
OUT H_|

| DOOL

GND

| DO2L

DO1 L

+5V

Al8L

SVTP

| -

Battery
E

D04 L

DO3 L

Al9 L

| DO6L

DO5 L

ACLOL

| DOSL

D07 L

A0l L

A00 L

DIOL

D09 L

A03 L

AO02 L

K | DI2L

DIIL|

AO5L

A04 L

BUSG7
|

| DCLOL |

SOH
L

| DI4L

DI3L

A07 L

A06 L

BUS G7

OUTH _|

M | -

DISL

A09 L

AO8 L

BUS G6|

SOH
N

| A21L

PBL

AllL

AIOL

BUS G6

OUTH _

| A20L

Al3 L

Al2L

BUS G5 |

SOH

| +12V
Battery

AlSL

Al4 L

| -12v

Al7L

Al6L

INH

Battery

BUS G5
OUTH _|

| BUSG4
]

REFL | SOH
TP

| GND

GND

ClL

GND | BUS G4
OUTH _|

| +12V

SSYN L

COL

MSYNL

Battery

| -

NOTES

1. Pins AN1, AP1, BE1, and BE2 are used for address lines A21L through A18L in extended Unibus operation.
Unibus operation, the signals on these pins are ignored by the MS11-M (receivers disabled).
2. Pins marked by ] are tied together on the module to provide grant continuity.

2-8

148,
G0

2-9

Bit 1

This bit, when set to 1, disables single-bit error correction. Dur-

Error Correction
Disable

ing a memory read cycle, a single-bit error is treated as an uncorrectable (double-bit) error and is also identified as a singlebit error in the CSR. A double-bit error, detected during a
memory read-modify-write (RMW) cycle, does not prevent the

modification of the 39-bit word retrieved from the storage array. Therefore, data supplied by the bus master and the generated check bits are allowed to be written into the MOS storage
array along with old data. Bit | is a read /write bit and is cleared
by BUS INIT L.
Bit 2

This bit, when set to 1, allows the transfer of information be-

Diagnostic

tween the CSR and MOS RAM chips used for check bit storage. During a memory RMW cycle, data in CSR bits 11-5 1s
written into the MOS storage array instead of the generated

Check

check bits of a 39-bit word. During a memory read cycle, check
bits retrieved from the MOS storage array are loaded into CSR
bits 11-5. Bit 2 does not affect the detection of a single-bit or
double-bit error although a detected double-bit error is ignored
by the MS11-M during a RMW cycle. Bit 2 is a read/write bit
and is cleared by BUS INIT L.

Bit 3

Inhibit Mode
Pointer

This bit, in conjunction with CSR bit 13, selects a 16K X 16-bit
section of memory that is not affected by CSR bits | and 2.
Therefore, a 16K area of memory can be protected from manipulation in the error correction disable or diagnostic check mode.
With bit 13 set to 1 and bit 3 cleared to O, the first 16K of
memory is protected. With bits 13 and 3 set to 1, the second 16K
bank is protected. Bit 3 has no effect if bit 13 is cleared to 0. Bit
3 is a read/write bit and is cleared by BUS INIT L.
NOTE

Between two interleaved memory modules, the first 16K of address
space is protected if bit 13 is set and bit 3 is cleared on both modules. The second 16K is protected if bits 13 and 3 are set.

Bit 4

Single Error
Indication

Bits 11-5

Error Address and
Check Bit Storage

This bit, when a 1, indicates the detection of a single-bit error
during a memory read cycle. Bit 4 is not affected by any other
CSR bit (i.e., bit 1-error correction disable). Bit 4 is a read/write
bit and is cleared by BUS INIT L.

Error Address Storage — These bits store a partial address ofthe
accessed memory location, recorded on the detection of a
single-bit or double-bit error during a memory read cycle. In
Unibus operation, address bits A17-A11l are stored in CSR bits
11-5 respectively, specifying the data location to a 1K segment

of memory. In extended Unibus operation, address bits
A21-A11 are recorded; however, the address bits that appear in

bits 11-5 are determined by bit 14.

2-10

NOTE

With error correction enabled (bit 1=0), a single-bit error address

is not recorded if bit 15 is a 1, indicating that a double-bit error
has occurred.

Check Bit Storage — When bit 2 equals 1, CSR bits 11-5 store
the check bits read from the storage array, or information to be
written into the storage array as the check bits of a 39-bit word.
The check bits and error address are recorded if an error is detected during a memory read cycle in the diagnostic mode (bit
2=1). The recorded check bits appear in bits 1 1-5 while bit 2 1s
still set to 1. The error address can be retrieved once bit 2 is
cleared to O.

CSR bits 11-5 are not cleared by BUS INIT L.
Bit 12

This bit is not used and is read as a logical 0.

Bit 13
Inhibit Mode

This bit, when set to 1, enables bit 3 to inhibit either the first or
second 16K portion of memory from ever going into the error

Enable

correction disable or diagnostic check mode.
read/write bit and is cleared by BUS INIT L.

Bit

is a

Bit 14

In normal operation, this bit, when set to 1, causes the MS11-M

EUB Error

to place A21-A18 of a recorded error address into CSR bits

Address Retrieval

8-5; logical Os are placed in bits 11-9. Address bits A17-All are

placed in bits 11-5 when bit 14 is cleared to O, if bit 150or4isa 1.
Bit 14 has no effect when the memory 1s in the diagnostic mode

(bit 2=1). In extended Unibus operation, bit 14 is a read/write
bit and is cleared by BUS INIT L. In Unibus operation, bit 14 is
a read-only bit and is always a 0.
Bit 15

This bit, when a 1, indicates the detection of an uncorrectable

Uncorrectable Error

error during a memory read cycle and also turns on a red LED

Indication

on the module. Bit 15 is just a flag. This bit is a read/write bit

and is cleared by BUS INIT L.
2.3.1

Notes on CSR Usage

For two interleaved memory modules, CSR bits 14, 13, 3, 2, 1, and 0 on both modules should be set to

the same value (1.e., bit 1 on both modules is cleared to 0). The values ofthese bits can be set independently for each module in the noninterleaved mode. For normal operation in the interleaved or noninterleaved mode, CSR bit 0 should be set to 1 and bits 14, 13, 3, 2, and | should be cleared to 0.

Bit 1 (error correction disable) is usually set to 1 for diagnostic purposes, allowing data to be read or
written into memory without interference from the error correction logic. With bit 1 set to 1, a soft

double error in memory can be cleared by writing new data into one or both PDP-11 memory locations
of the bad 39-bit word. Note that a soft double error may be caused by the occurence of one hard error
and one soft error, or two soft errors within a 39-bit word (a hard double error cannot be cleared).
Bit 2 (diagnostic check mode) allows check bits in the MOS storage array to be read via the CSR.
Right after a DATI bus cycle to memory (with bit 2=1), the CSR should be read with a DATI cycle to

examine the check bits retrieved from the storage array. Note that a DATO cycle to the CSR destroys
the retrieved check bits but an error address recorded in the CSR is preserved.

2-11

The diagnostic check mode also provides a means of testing the error correction logic by allowing the
check bit pattern in a 39-bit word to be altered via the CSR. The desired check bit pattern should be
written into CSR bits 11-5 and bit 2 should be set to | with a DATO cycle to the CSR. A DATO cycle
to memory should then be performed. Writing the appropriate check bit pattern in the storage array
should cause the detection and correction of a single-bit error during a subsequent memory read cycle.
(Refer to the MS11-M Technical Manual.)

Bits 1 and 2 in the CSR will not affect the segment of memory specified by bit 3, if bit 13 issetto |. The

system diagnostic can reside in the protected portion of memory. The diagnostic can then disable error
correction and/or run the diagnostic check mode on the rest of the memory module, without itself
being vulnerable to single-bit errors.

With bit 15 or 4 set to 1 and bits 14 and 2 cleared to 0, retrieve the EUB error address (A21-A11) as
follows:

Read the CSR with a DATI bus cycle to obtain A17-All

2.
3.

Write a logical | into CSR bit 14 with a DATO bus cycle
Read the CSR with a DATI bus cycle to obtain A21-A1l8.

When the memory is not in the diagnostic mode (CSR bit 2=0), data previously loaded into CSR bits
I 1-5 cannot be read when bit 15, 14, or 4 is a logical 1.

2-12

MS11-M MOS MEMORY

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