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Document:	MS11-E J MOS Memory User's Manual
Order Number:	EK-MS11E-OP
Revision:	001
Pages:	22
Original Filename:

OCR Text

MS11-E-J MOS memory
user’'s manual

dlilgliltiall

EK-MS11E-OP-001

'MS11-E-J MOS memory
user’s manual

digital eguipment corporation - maynard, massachusetts

1st Edition, October 1976

The material in this mahual is for informational
purposes and is subject to change without notice.

Digital Equipmént Corporation assumes no respon-

sibility for any errors which may appear in this
manual.

Printed in US.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

MASSBUS

DECCOMM

PDP

DECsystem-10

RSTS
TYPESET-8

DECSYSTEM-20

DECtape
DECUS
DIGITAL

‘

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

CHAPTER 2

INSTALLATION

2.1

GENERAL

2.2

JUMPER VERIFICATION

2.3

SWITCH ARRANGEMENT

VOLTAGECHECK

2.5

2.6

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NITAOCANNAQTTIN NLILAY

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2-1

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e

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BACKPLANE INSTALLATION
1JLANTL

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2-1

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2-1

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2-1

... .................

-------

‘.

¢-

2-3
2-3

JILLUSTRATION
Figure No.

2-1

Title

MS11-F Module

Page

. . . . . . PP T

2-2

TABLES
Table No.
1-1
1-2

Title

Significant System Specifications [ ’

MS11 Options

. . ... ........ e

2-1

Module Jumper Installation

2-2

MS11 DC Voltage Tolerances

2-3

MS11 Memory Pinouts

e e e e e e e e

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. ... ......... e

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CHAPTER 1
INTRODUCTION

The MS11-E - MSI11-J (referred to herein as MS11)

The use of

memories comprise a group of MOS semi-con‘ductor, random-access memories that are designed
to be used with the PDP-11 Unibus. Each memory
assumes the role of a slave device to the PDP-11
processor or to any peripheral device that is designated bus master. The group provides storage for
16- or 18-bit data words (two parity bits are included in the 18-bit word), with capacity ranging
from 4096 (4K) words to 16,384 (16K) words in 4K
blocks. An MS11 memory can be assigned adjacent
4K blocks of addresses anywhere within the 124K
Unibus address space. A special feature of the 16K
MSI11 allows the assignment of part of the I/O
page to memory, although this can be done only
for processors without memory management. Table
1-1 lists the significant specifications of an MSI]

tages (both economical and operational) not available with core memory systems. The cost-per-bit
for MOS memories is low and, unlike core memory, this cost remains approximately constant with
size.

Unlike core, MOS memory provides non-destructive

readouts;

consequently,

the

write-after-read

cycle time associated with core memory is eliminated.
such

Furthermore,
as

those

used

with
in

dynamic
the

MSII,

MOS

devices

power

con-

sumption is much lower than with core memory.
The disadvantage of MOS storage volatility (i.e.,

data is not retained when power is lost) is compensated

system.

The logic components of an MSII

MOS memory circuits provides advan-

for

the

availability

of battery-sup-

ported power supplies that enable data retention
for as long as several hours. The MS11 is designed

memory are

for a special low-power mode to maximize the effec-

mounted on a single hex printed circuit board; the

tiveness of battery-powered operation.

module has DEC designation M7847. The storage

elements are 4096 X 1-bit, N-channel, MOS memory devices. A row of 18 of these devices 1is
mounted on a module for each 4K block of addresses that is assigned to the memory; e.g., a 16K
memory has 4 rows of 18 devices, an 8K memory
has but 2 rows of devices. Table 1-2 lists the avail-

Because the data storage element is a capacitor 1n
the MOS storage device, all memory locations in

the MOS memory must be periodically refreshed so
that the data remains valid. The controller on the

memory module includes the logic and timing cir-

able MS11 options and the respective bit and word
:
|
capacities.

cuits to carry out the periodic refreshing operation.

I-1

Table 1-1

Significant System Specifications

Characteristic

Specification

Storage Capaéity

4096 (4K) to 16,384 (16K) words, in 4K blocks

Data Word Length

16 data bits, 2 parity bits

Maximum Access Time (ns)
Normal Operation

550

Refresh Conflict*®

1250

Maximum Cycle Time (ns)
Normal Operation

700

Refresh Conflict*

1400

Refresh Cycle Rate

One cycle every 25 us (typiéal); maximum of one
cycle every 22.5 us

Maximum Power Consumption (watts)
MS11-E

Idle

700 ns Cycle

12.3

23.5

MS11-F

13.0

24.3

MS11-H

13.8

25.0

MS11-]

14.5

25.8

Maximum Current Drain (mA)

Idle

700 ns Cycle

1500

MSI11-E
+5 Vdc

BB+5 Vdc

500

+15 Vdc

800

-15 Vdc

100

- 1500

1500

MS11-F
+5 Vdc

BB+5 Vdc

500

+15 Vdc

100

850

-15 Vdc

100

100
|

MS11-H
|

+5 Vdc

1500

BB+5 Vdc

500

+15 Vdc

150

900

-15 Vdc

100

1500

MS11-]
-

+5Vdc

BB+5 Vdc

500

+15 Vdc

200

950

-15 Vdc

100

*A characteristic of dynamic MOS memory devices is that they must be cycled periodically to ensure data validity. These cycles are
known as refresh cycles and the controller on these memory modules has all the logic and timing circuits necessary to ensure that
these cycles are performed. Should a processor or NPR request (MSYN) come during a refresh cycle, it is held up until the refresh
cycle is completed and then processed. The Refresh Conflict time is the maximum amount of time that a normal cycle may be held
up by a refresh cycle. The amount of time lost to bus masters because of refresh is dependent on the bus activity. For a system that
uses the bus at a maximum rate (700 ns cycles) the loss of memory availability is less than 3 percent. For a system with an average
bus cycle every 1.4 us, the loss of availability is typically less than 3/4 percent.

Table 1-2

MS11 Options

Option

Word Bit

Data Word

Designation

Length

Capacity

MSI11-E

~ MSI11-EP

MS11-F

MS11-FP

MS11-H

12K
12K

MS11-HP

MS11]

16K

MS11.JP

16K

NOTE

18-bit words include two parity bits; an M7850 Parity

Control module must be used with the parity options.

1-3

7
s

CHAPTER 2
INSTALLATION

2.3

SWITCH ARRANGEMENT

Installation of the MS11 is relatively simple. First,

The

MSI1

the user should verify that factory-installed jumper

space by the arrangement of switches A - E. The

wires relating to the number of memory chip banks

switches must be arranged by the user before the

are in place.

memory

2.1

GENERAL

ranged

Next, certain

assign

Unibus

switches must be araddress space

Memory

assigned

Unibus

address

installed.*

the

MSI1. The backplane should then be checked to ensure that the required dc voltages are available. Fi-

2.4

nally, the module is inserted into the backplane and

Before

VOLTAGE CHECK

a diagnostic check 1s carried out to assure correct

check the backplane to ensure that the required dc

the module is

inserted

the backplane,

operation. These procedures are discussed more

voltages are present and within tolerance. The dc

fully in following paragraphs.

voltages are listed in Table 2-2;: Table 2-3 lists the
MSI11 pin-outs.

Figure 2-1 shows the MSI1 module (an 8K memory is illustrated). The array of chips is located in
the upper-right quarter of the board. At the leftcenter of the board
which

are eyelets W1

appropriate jumpers

are

- W6, into

inserted.

All four dc voltages must be supplied for system op-

eration. If data retention is desired when the ac

power is removed, the +5 Vdc supply can be powered down and the other supplies maintained.

the

lower-right of the eyelets is the DIP switch (E111)

Table 2-1

which is configured according to the MS11 address

Module Jumper Installation

assignment. E111 has eight individual contacts that
may be identified by

numbers or letters on the

switch; however, the contacts are identified by etched letters A — J on the printed circuit board (this
notation is followed throughout the text and in the
logic drawings).

2.2

JUMPER VERIFICATION

The

MSI11

Memory

shipped with

Memory

Designation

Size

MS11-E/EP

erate with switch H closed, in addition to the installed jumpers; however,

a 16K memory installed

in a 32K PDP-11 requires special consideration.*

W5-Wé6

12K

MS11-J/JP

16K

Table 2-2
MS11 DC Voltage Tolerances

The user should check the module to ensure that

installed for each. A 16K memory will normally op-

WI-W2

MS11-F/FP

factory in-

memories by size and indicates the jumpers that are

by Jumpers
W3-W4

MS11-H/HP

stalled jumpers appropriate for the memory size.

the correct jumpers are in place. Table 2-1 lists the

Eyelet Pairs Connected

Memory

DC Voltage

Minimum

Maximum

475

+15

14.50

16.50

-15

-16.50

-13.50

BB+5

4.75

5.25

*Refer to Paragraph 4.2 of MS11-E-J MOS Memory Maintenance Manual (EK-MS11E-MM

-001).

5.25

Figure 2-1

MSI1-F Module

2-2

Table 2-3
MS11 Memory Pinouts

| Doo | GND

D02 | DOl | BB+5

D
E

| Do4

| D03

| INT

| ~

GND

]

GND

| GND

| PAR | TP

SSYN | DET

| D06 | DOS

| pDos

| D07

| A0l

| AOO

D10

| D09

| A03

| AO2

D12

| D11

| A0S

| Ao4

D14

| D13

| A07

| A06

| TP

DI5 | A09 | A08 | TP

All

| Al10

A13

| A12

+15

A15

| Al4

GND

_15

A17 | A16
GND | C1

SSYN | €0

MSYN

GND

#
.

GND |

| oND

GND

*Points marked by ] are tied together to provide grant continuity on backplane.
2.5

BACKPLANE INSTALLATION

When the dc voltages have been verified, insert the
MSI11 into the Unibus backplane. Presently, three
backplanes can be used with the MSII, although
other backplanes may become available; these three
are DDI11-C, DD11-D, and DD11-P. The DDI11-C
is a 4-slot backplane; the MS11 can be inserted into

slot 2 or slot 3. The DDI11-D is a 9-slot backplane;
slots 2 — 8 can be used for the MSI11. The DDI11-P
is another 9-slot backplane, which is used with the
PDP-11/04 or PDP-11/34. If an M7850 Parity Con-

trol module is to be used with the MS11, it must be
installed in the same backplane; the M7850 can oc-

cupy any of the backplane slots that are available
to the MSI1.

2.6

DIAGNOSTIC CHECK

When the memory is connected to the Unibus, run

the MS11

diagnostic program to verify that the

memory is operable. If a problem arises, follow the
instructions in the diagnostic.

APPENDIX A

MS11 SWITCH SETTINGS

', TabléfA-l first lists the 31 addresses that can be assigned as the starting address on the MS11 module.

Listed next is the number of Unibus addresses bestarting address; e.g., there are 8096

low the MSI1
(8K)

Unibus

addresses

below

starting

address

040000;. Finally, the third column lists the switch
settings that will produce the desired address assign-

ment. The MSI1 ending address is automatically determined by the starting address and the memory
-

size. Table A-2 shows how switches H, J, and F

must be arranged for normal operation and when
I/O page space is assigned to the MSI1.

A-1

'\m_,/

~ Table A-1

Switch Séttings for MS11 Starting AddresSe_s |
MS11 Starting Address
(Octal)

Unibus Addresses Below

Starting Address

- Switch Selection
(Switch OFF = Logic 1)
AlB|]C]DI|E

000000

020000

040000

060000
100000

12K
16K

1|1

120000

20K .

1 lo

|11

140000

24K

10|11

1]o0

}J1]lo0]|1]o0

|00

{1100

160000
200000

28K
- 32K

11010
|1
1o
}1]o0]o
|1

240000
260000
300000

40K
44K
48K

‘10|00
|1
‘1 lo0
o0
]lo0}lo0olo
1

|0
|1
o

36K

220000

320000

52K

340000

56K

360000
400000

60K
64K

o1
‘o

0|1
o1

|11

11110

4{1}o0
|1
]1]0]0

420000

68K

of|1]o0

440000

72K

76K

ol1

|00

500000

80K

ol1]0o0]o0

520000

84K

o]lo

540000

88K

ojlo|1]11]o0

560000

92K

olo|1]0

460000

(|1

10]11]0

1|1

600000
620000

96K
100K

oj]o
olo

|10
o |1

]0
|1

640000

104K

ofol|lol|1

660000

108K

olo

720000

116K

|11

700000

740000

112K

120K

olo

NOTE

Switch contacts are open when switch is in OFF position

oo
1 |

|oO
1

}1]o0

“

{11100

Table A-2

Switch Settings for I/O Page Operation
Memory Size Determination

Switch
Memory Option

MS11-E/EP, MS11-F/FP,

OFF | OFF | OFF

MS11-H/HP

MS11-J/JP, Normal Use

OFF

MS11-J/JP, Lower 2K of I/O | OFF | OFF

page assigned to memory*

MS11-J/JP, Lower 3K of /O | ON

OFF

page assigned to memory*
*Set switches A through E for a starting address of
1000005 .
NOTE

Switch contacts are open when switch is in OFF position.

A-3

MS11-E—J MOS MEMORY

Reader’s

USER’S MANUAL

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