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Document:	MS11-E J MOS Memory Maintenance Manual
Order Number:	EK-MS11E-MM
Revision:	001
Pages:	54
Original Filename:

OCR Text

MS11-E—-J MOS memory
maintenance manual

dlifgliltiall

EK-MS11E-MM-001

MS11-E—J MOS memory
maintenance manual

digital equipment corporation - maynard. massachusetts

1st Edition, October 1975

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

MASSBUS

DECUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

CHAPTER 2

INSTALLATION

2.1

GENE RAL

2.2

JUMPER VERIFICATION

. . . . .

2.3

SWITCH ARRANGEMENT

VOLTAGE CHECK

2.5

BACKPLANE INSTALLATION

2.6

DIAGNOSTIC CHECK

CHAPTER 3

CHIP DESCRIPTION

3.1

PHYSICAL DESCRIPTION

. . . . . .

e e e e e e e e e e e e e e e e e e e

3-1

3.2

OPERATING DESCRIPTION

. . . . .

e e e e e e e e e e e e e e e e e e e s e

3-1

CHAPTER 4

LOGIC DESCRIPTION

4.1

BLOCK DIAGRAM

s e e e e e e e e e e e e e e

4-1

4.2

ADDRESS DECODING LOGIC

4.3

TIMING SIGNAL LOGIC

4.4

REFRESH LOGIC

4.5

ADDRESS PATH LOGIC

4.6

DATA PATHLOGIC

CHAPTER 5

TROUBLESHOOTING HINTS

. . . .

e e

2-1

e e e e e e e e e e e e e e e e e e

2-1

. . . . ..

e e e e e e e e e e e e e e e e e e e e e e

2-1

o e

e e e e e e e e e e e e e e e e e e e e s d s e

. . . .

e e e e e e e e e e e e e e e e
e e

. . . . . . .

. . . . . .

. . .

e e e e e e e e e e e e e e e e s e e s s s s

2-3

5.1

GENERAL

DIAGNOSTIC LOADING PROBLEMS

5.2.1

BUS SSYN L Not Asserted

52.2

BUS SSYN L Asserted

e e e e e e e e e e e e e e e e

e e e e e e e e e e

5.22.1

Refresh CircuitS

5.2.2.2

Data CircuitS

. . . . . . . . . . . i i

5223

Address Circuits

5224

Write Logic

5.2.2.5

Loader Memory Space

s 4-11

5-1
5-1

e e e e e e e e e i e e s s e

5-1

e e

e e e e e e e e e e e e e e e e e

. . . . . . .

4-7

e e e

e e e e e e e e e e e e e e e e e

. . . . . . . . o o o e e e

. . . . . . .

4-5

s s

. . . . . . . .

. . . . . . & o

4-1

e e e e e e e e e e s s s, 4-11

e e e e e e e e e e e e s e e e e

. . .

e e e e e e e e e s s s s e

e e e e e

. . . . .

e e e e e e e e e e e e s s s

e e e

. . . . . .

5.2

e e

5-2

e e e e e e e e e e e e e e e e e e

. . . . . . . . . L

e e e e e

e e e

. . . . . . . . . . .. ... e

5.3

DIAGNOSTIC EXECUTION PROBLEMS

APPENDIX A

MS11 SWITCH SETTINGS

APPENDIX B

IC DESCRIPTIONS

iii

2-1
2-3

. . . . . . .

e e

e e e e e e e e e e e e e e e e e e

. . . . . . . .

. . . . .

. . . . . . . . . .

e e e s e s st

5-2
5-3

5-3
5-4

ILLUSTRATIONS

Title

Figure No.

Page

2-1

MS11-FModule

3-1

Chip Pin Connections

. ............. e

3.2

(4096 X 1) Bit MOS Chip, Block Diagram

3.3

MOS Chip, Simplified Data Gating

Chip Read/Write Timing

4-1

MS11 Block Diagram

4.2

Address Decoding Logic

4.3

Address Decoding, I/O Address Space Logic

Timing Signal Logic

4-5

Bus Cycle Timing Signals

4.6

Refresh Logic

e e e e e e e e e e e

. . ... ... ... e

e e e e e

e e e e e e e e e e e e e e

e e

2-2

e e e e

3-1

. . . ... ... ... ... ... ........

3-2

. . . . . . . .. .. . .. ... .. . ...

. ... ... ... e

e e e e e e e e e e e

34
4-2

e e e e e e e e e e e e e e e e e e e e

4-3

. . . . .. ... ... ... .. ........

4-5

. . . . . . . . . . . . . .

. . . . . . . . . . . . . . .
e e

4.7

Refresh Cycle Timing Signals

4.8

Address Path Logic

4.9

Data Path Control Signal Logic

4-10

Data Path Logic [Bit D(15)]

. . . . . . . . . . o

4-11

Data Write Timing (DATO)

. . . . . . . . . . .

4-12

Data Read Timing (DATI)

5-1

Refresh Counter Timing

e e e e e e e

4-8

e e e e e e e e e e
..o

. . . . . . . . . . . . . . . 0

e e e

e 4-12

... 4-13

e e

.. 4-10

e e

. . . . . . . . . . ... .. ...

. . . . . . . . . . .

4-6

i e

. . . . . . . . ... ... ...

. . . . . . . . . . . .

3-3

e e e e e e e e e e e e e e e e e e e e e

. . .. ... ... e

. . . . . . . o o o o

...

. . ........
.. e

e e e e

e 4-14

e e e 4-15

e 4-16

5-2

TABLES
Title

Table No.

Page

1-1

Significant System Specifications

1-2

MS11 Options

2-1

Module Jumper Installation

2-2

MS11 DC Voltage Tolerances

2-3

MS11 Memory Pinouts

. . . . . . . . . . .

3-1

Chip Supply Voltages

. . . . . . . . . . 0 0 i i

4-1

Address Space Assignment

. . . . . . o

. . . . . . . .. ...

oo oo

e e e e e e e e e e e e e e

. . . . . . . . . ... ..o

. . . . . . . .. L. L

L e e e

1-2

1-3

L oL

2-1

. . . . . . . . . .t v v i v i ittt e e

e e e

2-1

e e e e e e

e e e e e e e

2-3

e e e e e

3-1

e e

4-4

CHAPTER 1
INTRODUCTION

The MSI11-E - MS11-J (referred to herein as MS11)

The use of MOS memory circuits provides advan-

memories

tages (both economical and operational) not avail-

comprise

group

of MOS

semi-con-

ductor, random-access memories that are designed

able with

to be used with the PDP-11 Unibus. Each memory

for MOS memories 1s low and, unlike core mem-

assumes the role of a slave device to the PDP-11

ory, this cost remains approximately constant with

processor or to any peripheral device that is desig-

size.

core memory systems. The cost-per-bit

nated bus master. The group provides storage for
16- or

18-bit data words (two parity bits are in-

cluded in the

18-bit word), with capacity ranging

from 4096 (4K) words to 16,384 (16K) words in 4K
blocks. An MS11 memory can be assigned adjacent
4K blocks of addresses anywhere within the 124K

Unibus address space. A special feature of the 16K
MSI1

allows the assignment of part of the 1/0

page to memory, although this can be done only

for processors without memory management. Table
I-1

lists the significant specifications of an

MSII

system.

The

logic

readouts;

components

of an

MSI11

memory

are

module has DEC designation M7847. The storage

elements are 4096 X
devices.

row

consequently,

the

write-after-read

cycle time associated with core memory is eliminated.
such

Furthermore,
as

those

used

with
in

dynamic
the

MOS

MSII,

devices

power

con-

sumption is much lower than with core memory.
The disadvantage of MOS storage volatility (i.e.,
data 1s not retained when power is lost) is compensated
ported

mounted on a single hex printed circuit board; the

ory

Unlike core, MOS memory provides non-destructive

for

the

availability

battery-sup-

power supplies that enable data retention

for as long as several hours. The MS11 is designed
for a special low-power mode to maximize the effectiveness of battery-powered operation.

1-bit, N-channel, MOS memof

these

devices

mounted on a module for each 4K block of ad-

Because the data storage element is a capacitor in

dresses that is assigned to the memory; e.g., a 16K

the MOS storage device, all memory locations in

memory has 4 rows of 18 devices, an 8K memory

the MOS memory must be periodically refreshed so

has but 2 rows of devices. Table 1-2 lists the avail-

that the data remains valid. The controller on the

able MSI11 options and the respective bit and word

memory module includes the logic and timing cir-

capacities.

cuits to carry out the periodic refreshing operation.

Table 1-1

Significant System Specifications

Characteristic

Specification

Storage Capacity

4096 (4K) to 16,384 (16K) words, in 4K blocks

Data Word Length

16 data bits, 2 parity bits

Maximum Access Time (ns)
Normal Operation

550

Refresh Conflict*

1250

Maximum Cycle Time (ns)
Normal Operation

700

Refresh Conflict*

1400

Refresh Cycle Rate

One cycle every 25 us (typical); maximum of one

cycle every 22.5 us
Maximum Power Consumption (watts)

Idle

700 ns Cycle

MS11-E

12.3

23.5

MSI11-F

13.0

24.3

MS11-H

13.8

25.0

MS11-]

14.5

25.8

Maximum Current Drain (mA)

Idle

700 ns Cycle

1500

MSI11-E
+5 Vdc

BB+5 Vdc

500

+15 Vdc

800

-15 Vdc

100

1500

MSI11-F
+5 Vdc

BB+5 Vdc

500

+15 Vdc

100

850

-15 Vdc

100

1500

MS11-H
+5 Vdc

BB+5 Vdc

500

+15 Vdc

150

900

-15 Vdc

100

1500

MS11-J
+5 Vdc

BB+5 Vdc

500

+15 Vdc

200

950

-15 Vdc

100

*A characteristic of dynamic MOS memory devices is that they must be cycled periodically to ensure data validity. These cycles are
known as refresh cycles and the controller on these memory modules has all the logic and timing circuits necessary to ensure that
these cycles are performed. Should a processor or NPR request (MSYN) come during a refresh cycle, it is held up until the refresh
cycle is completed and then processed. The Refresh Conflict time is the maximum amount of time that a normal cycle may be held
up by a refresh cycle. The amount of time lost to bus masters because of refresh is dependent on the bus activity. For a system that
uses the bus at a maximum rate (700 ns cycles) the loss of memory availability is less than 3 percent. For a system with an average
bus cycle every 1.4 us, the loss of availability is typically less than 3/4 percent.

Table 1-2

MS11 Options

Option

Word Bit

Data Word

Designation

Length

Capacity

MS11-E

MS11-EP

MS11-F

MS11-FP

MS11-H

12K

MS11-HP

12K

MS11-J
MS11-JP

16K

NOTE

18-bit words include two parity bits; an M7850 Parity
Control module must be used with the parity options.

CHAPTER 2
INSTALLATION

2.3

SWITCH ARRANGEMENT

Installation of the MSI1 is relatively simple. First,

The

MSI1

the user should verify that factory-installed jumper

space by the arrangement of switches

wires relating to the number of memory chip banks

switches must be arranged by the user before the

are 1n

place. Next,

switches must be ar-

memory is installed.

ranged

address

tempting to assign address space to the MSI11.

2.1

GENERAL

assign

certain
Unibus

space

the

Memory

assigned

Unibus

address

A - E. The

Read Section 4.2 before at-

MSI1 1. The backplane should then be checked to en-

sure that the required dc voltages are available. Fi-

2.4

nally, the module is inserted into the backplane and

Before

a diagnostic check is carried out to assure correct

check the backplane to ensure that the required dc

operation.

voltages are present and within tolerance. The dc

These

procedures

are

discussed

VOLTAGE CHECK

the module

inserted

the backplane,

voltages are listed in Table 2-2; Table 2-3 lists the

fully in following paragraphs.

MSI11 pin-outs.

All four dc voltages must be supplied for system op-

Figure 2-1 shows the MSI1 module (an 8K mem-

eration. If data retention is desired when the ac

ory is illustrated). The array of chips is located in

power is removed, the +5 Vdc supply can be pow-

the upper-right quarter of the board. At the leftcenter of the

board

are eyelets W1

which -appropriate jumpers

are

ered down and the other supplies maintained.

- W6, into

inserted.

the

lower-right of the eyelets is the DIP switch (El111)

Table 2-1

which is configured according to the MS11 address

Module Jumper Installation

assignment. E111 has eight individual contacts that

Memory

Designation

Size

notation 1s followed throughout the text and in the

MS11-E/EP

logic drawings).

MS11-F/FP

MS11-H/HP

12K

MS11-J/JP

16K

may

identified

numbers

or letters

the

switch; however, the contacts are identified by etched letters

A -~ J on the printed circuit board (this

2.2

JUMPER VERIFICATION

The

MSI1

Memory

shipped

with

factory

in-

by Jumpers

W3-W4

WI-W2

WS5-Wé

Table 2-2

stalled jumpers appropriate for the memory size.

MS11 DC Voltage Tolerances

The user should check the module to ensure that
the correct jumpers are in place. Table 2-1 lists the

DC Voltage

memories by size and indicates the jumpers that are
installed for each.

Eyelet Pairs Connected

A 16K memory will normally op-

Minimum

Maximum

4.75

5.25

erate with switch H closed, in addition to the in-

+15

14.50

16.50

stalled jumpers; however, a 16K memory installed

-15

-16.50

-13.50

BB+5

4.75

5.25

in a 32K PDP-11 requires special consideration. Re-

fer to Section 4.2, Address Decoding logic.

2-1

7572- 1

Figure 2-1

MSI11-F Module

2-2

Table 2-3
MS11 Memory Pinouts

]

| TP

GND

| PAR

| TP

c | poo | GND

GND

| po2

| Do1

| BB+5

| po4

| D03

| INT

GND

SSYN | DET

| Do6

| DO5

| TP

LO
H

| pog

| po7

| Ao1

| Aco

DI0

| D09

| A03

| AO2

| pi2

| pi1

| Aos

| Ao4

D14

| D13

| A07

| AO6

M
N

]
| TP

*
.

DI5 | A09 | A0S | TP
A1l

| Al10

| Po

A13 | A12

Al5

+15

| Al4

s | -15

Al17 | Al6

GND

| GND

SSYN | co

MSYN

P | *
| GND

oNpD |

| GND

GND

*Points marked by J are tied together to provide grant continuity on backplane.

2.5

BACKPLANE INSTALLATION

trol module 1s to be used with the MSI11, it must be

When the dc voltages have been verified, insert the

installed in the same backplane; the M7850 can oc-

MSI1 into the Unibus backplane. Presently, three

cupy any of the backplane slots that are available

backplanes can be used with the MSI1, although

to the MS11.

other backplanes may become available; these three
are DDI11-C, DDI11-D, and DD11-P. The DDI11-C
is a 4-slot backplane; the MS11 can be inserted into

2.6

slot 2 or slot 3. The DDI1-D is a 9-slot backplane;

When the memory is connected to the Unibus, run

slots 2 — 8 can be used for the MS11. The DDI11-P

the

is another 9-slot backplane, which is used with the

memory 1s operable. If a problem arises, follow the

PDP-11/04 or PDP-11/34. If an M7850 Parity Con-

instructions in the diagnostic.

DIAGNOSTIC CHECK
MSI11

diagnostic program

verify that

the

CHAPTER 3
CHIP DESCRIPTION

3.1

3.2

PHYSICAL DESCRIPTION

OPERATING DESCRIPTION

The MOS memory device used with the MSI11 is a
4096-bit, dynamic, random-access memory circuit.

A functional block diagram of the chip is shown 1n

The circuit is packaged in a standard 16-pin DIP
that provides high system bit density and is compatible with available automatic testing and insertion equipment. Figure 3-1 is an outline drawing
of the chip, showing pin connections. Table 3-1 lists

in a 64-row by 64-column array. Thus, a cell loca-

Figure 3-2. The 4096 storage locations are arranged
tion can be specified by a 6-bit row address and a
6-bit column address. Because address information
1s latched into on-chip registers, the chip can be

driven by only 6 address lines. The MS11 logic multiplexes

the chip supply voltages.

address

bits,

time,

onto

the

AO-AS lines. The RAS L (Row Address Strobe) sig-

nal causes row address information to be latched
Vge

] 16

into a 6-bit register, while the CAS L (Column Ad-

Vss

Din

115

CAS L

WRITE L

314

Dgyy

RAS

CS L

)12

J 10

Veg 8L

V¢

dress Strobe) signal causes column address information, as well as the CS L (Chip Select) signal, to be
latched into a 7-bit register. Enable signals applied
to 1-of-64 decoders result in one of the 4096 cell locations being selected for a data transfer.

A simplified representation of the chip is shown in

Figure 3-3 (all the switches are merely symbolic of

11-3203

Figure 3-1

more detailed chip operation). The basic cell stor-

age element is a capacitor; a charge voltage of 0-6

Chip Pin Connections

V represents logic 0, while a voltage of 6-12 V rep-

resents logic 1. Because the charge on the capacitor
Table 3-1

dissipates with time, it is continually refreshed so

Chip Supply Voltages

that the data it represents remains valid. Any read
or write cycle results in a refresh of the data in the

Voltage

Operating Level

addressed locations. During such a cycle, the row

address is latched first, and then the 1-0f-64 decoder closes all the switches in the selected row. The

charge voltage on each capacitor in the row is apVSS

Ground

plied to a Sense Amplifier (SA), which refreshes the

VBB

—9V/-5V*

data by restoring the charge voltage to its original
level. For example, the maximum charge voltage on

*Depending on chip type.

3-1

a cell capacitor is 12 V, representing logic 1. When

Since a cell may be addressed infrequently, if at all,

the cell is addressed, a portion of the full charge

during normal read/write operations, a special tim-

may have leaked off so that the voltage has de-

ing cycle - a refresh cycle - 1s carried out at regular

creased to, for example, 8 V. The SA forces the

intervals. In the MSI11 Memory, such a cycle occurs

voltage back to its full-charge value of 12 V. Sim-

approximately every 25 us. A different row address

ilarly, any voltage between 0 and 6 V is restored to

is supplied by the MSI1! logic during each refresh

a logic 0 level of 0 V.

cycle so that the data in all 64 row addresses is refreshed about every 2 ms. The refresh operation is
the same as during a read or write cycle, 1.e., the

After the data in the selected row 1s accessed and re-

row address is latched; the data in each cell of the

freshed, the column address is latched; the multi-

row is refreshed; the column address is latched (the

plexer

column address supplied by the MSI11 logic is the

selects

one

of the

columns,

and

the

amplified charge voltage on a single capacitor is ap-

same during all 64 different refresh cycles); and the

plied to point “A” in Figure 3-3. If the cycle is a

cell data is read out to point A. However, during a

“read’’, the data is strobed into the tri-state output

refresh cycle, the CS L signal 1s disabled so that nei-

latch and remains valid until the next time CAS L

ther the input circuit nor the output circuit is en-

goes low. If the cycle is a “‘write’”’, the input buf-

abled.

fer/latch drives point A, overriding the SA output

impedance state, ensuring that power consumption

and charging the selected cell capacitor.

1S minimal.

The

output

latch

will

Doutr =

D1n

LATCH

WRITE L

STROBE

its

high-

LATCH/P_J

TM BuUFFER

ENABLE

CLOCK

DISABLE

L —*1 GENERATOR [ ENABLE
CAS

ENABLE

-——]

cS L

7-8IT
|

LATCH
(COLUMN

ADDRESS)

INPUT DATA

_ .
:

1-OF-64 |
pecoper|

¢
©7

!
l

SENSE AMPS,
|DATA IN/OUT GATING

OUTPUT DATA
e e-B4----

AD- A5

6-BIT

LATCH

(ROW

ADDRESS)

1-OF-64

)

DECODER | &2!
\

4096 ng

(64x 64)

STORAGE ARRAY

[

LATCH

RAS
L

—]

CLOCK
GENERATOR | ENABLE
11-3204

Figure 3-2

(4096 X 1) Bit MOS Chip, Block Diagram

Row

ADDRESS

_[T*/fi*_'

1-OF -64
DECODER

—

71/

ijflff&——

—

mae

64 COLUMNS

| ROWsS

Il B adien

_—

Inntlen

N
—

?A ———————————

COLUMN
ADDRESS

LATCH

MULTIPLEXER

N — BYR e

cTEf

LATCH

> OUT

|
|

WRITE L

cS L

11-3205

Figure 3-3

MOS Chip, Simplified Data Gating

READ CYCLE

(minimum timing)

700ns

RAS L IH
Vv

VIL

150ns —
150 ng —&|

CAS L VIH

VIL

ADDRESS

O to +50ns

COLUMN

Ons Q—-.‘ I

WRITE L VIH

Ons

;}{

‘\

Ons

¢ 10C0ns

DouT VoH

WRITE CYCLE

ADDRESS

ROW

———»|

\
Onslovu e-100n

Ons le—o| [&100ns

cs L

200ng

ADDRESSES 'IH ><

200ns ————

100ns ~—->1

OPEN ———-{Kd

350ns

(minimum

timing)
700ns

)

RAS L IH

150ns

cas L VIH
Vv

ADDRESSES Vv

WRITE L

IL
Viy
Y,

cs L

<100ns#)
ROW
ADDRES

Ons
j

I0Ons -+

—#

| COLUMN
lADDRESSX

=|| l
200ns
I l‘ZOOns

Ons

4150ns

Ons

4-100ns

Ons

[+0 to+50ns

200ns

IH
IL

DouT

Ons

200ns—————-j

200ns

100ns _.-{

Vv OH

OPEN

VoL

————
Wi

350ns
11-3206

Figure 3-4

Chip Read/Write Timing
3-4

The timing of both a read cycle and a write cycle is

output

illustrated in Figure 3-4. The RAS L signal starts

RAS L 1s asserted) and remains valid until CAS L

latch/buffer

access time (350 ns

after

the timing cycle internally. To reduce the overall
system power, RAS L is decoded in the MS11 logic

goes negative during a subsequent timing cycle. A
write cycle requires that the WRITE L signal go

low before access time; the WRITE L command is

and supplied to only the selected bank of chips.
The CAS L signal is supplied to all chips, but chips
that do not receive a RAS L signal will go to their

accepted by the chip only if CS L has been asserted. The data on the Dy line is strobed into an
input latch by the negative transition of the CAS L

high-impedance output states.

signal. Note that the output latch/buffer goes to
logic | at access time.

If data is to be read from the addressed location,

the WRITE L signal must be high and the CS L signal must be asserted. The data is strobed into the

3-5

CHAPTER 4
LOGIC DESCRIPTION

4.1

generates parity bits during a write operation and

BLOCK DIAGRAM

A block diagram of the MS11 Memory is shown in

checks parity bits during a read operation. In both

Figure 4-1. Data is stored in the chip array, which

operations, the parity information is latched into

can comprise from one to four rows of chips, each

the Data Path logic along with the data itself.

row consisting of 18 chips (a data word contains 16
data bits and two parity bits, if parity checking is

The cell matrix must be refreshed periodically to en-

employed). The data can be stored or retrieved un-

sure

der control of a bus master. The master specifies

sequently,

the address of a memory location to or from which

performed. During this operation, an address is sup-

that

the

stored

every

data
us,

remains

valid:

refresh

operation

conis

the data is to be transferred. The Address Decoder

plied by the Refresh logic and is applied to the mul-

logic determines if the address is assigned to the

tiplexers

MSI1. If it is, timing signals are generated by the

logic signals gate this address information to the

timing logic to strobe the address into latches in the

cell array. The data in all 64 cells in the row speci-

the

Address

Path

logic.

The Timing

Address Path logic. Other timing signals then gate

fied by the address is refreshed. At the end of the

the address information to the storage array where

operation,

the addressed location is selected.

cremented, updating the refresh address by one; dur-

the

Refresh

logic

in-

ing the next operation, the 64 cells in the new row

The bus master supplies Unibus control signals that

address are refreshed.

describe the data transfer direction. These control
signals are decoded by the Data Path Control Sig-

The logic represented by each block in Figure 4-1 is

nal logic, which then generates signals that control

shown in detail in the referenced figures. The logic

the direction of data flow through the Data Path

1s described in the sections that follow.

logic. If data is to be placed in the addressed loca-

tion, the bus master provides the data along with

4.2

the Unibus control signals. The data is strobed into

The Address Decoding logic examines the five most

input latches in the Data Path logic and placed on

significant bits of the Unibus address to determine

the Data In (DI) lines. When the addressed location 1s selected, the data is stored therein. If, in-

if the address is one that has been assigned to the

stead, data is to be removed from the array, it is

ates

placed on the Data Out (DO) lines when the location 1s selected, strobed into output latches in the

which enables MSYN H to start the MS11 timing

ADDRESS DECODING LOGIC

MSI11 Memory. If such is the case, the logic generboth

the

ADDRESS

PRESENT

signal,

sequence, and either RSA L, RSB L, RSC L, or

Data Path logic, and placed on the Unibus. If par-

RSD L, which results in one row of memory chips

ity checking is employed, a Parity Control module

being selected for the data transfer.

4-1

ADDRESS
PRESENT

BUS A {17:13)

RAS L

ADDRESS

DECODER

TIMING
LOGIC

LOGIC

FIGURE

CAS L
s L

COLAD

STORAGE

16K WORDS x
18 BITS/WORD

REF WARN L

REFRESH | RFCY H

ADDRESS

LOGIC
4_

4-8

BUS

A@Q

[7p]

APR_ABSA

FIGURE

BUS A {12:01>
SSYN

PATH

LOGIC

FIGURE | RA@®- RAGS
BUS

‘far

DIQO-DII5

ARRAY

4x18 CHIPS

BUS MSYN L

DATA PATH

CONTROL | WB@ L,WB! L
SIGNAL

BUS C1

gflfi

- DO 15
DOPP

DI PO

LOGIC

oLS H

LOGIC

FIGURE

EN BUS L

FIGURE

DO PO
BUS CQ

4-4

4-9

BUS D <15:00)

DO P1

r—
= "
leF"?
BUS D <15-oo:>> w7850 | P
PARITY

CONTROL

. MODULE

BUS SSYN

INT SSYN

PARITY DETECT

S —

N
11-3207

Figure 4-1

MSI11 Block Diagram

The Unibus address space assigned to the MS11 de-

Unibus and the MSI11

pends on how large the memory is, 1.e., what its bit

the ADDRESS PRESENT H signal will start the

capacity is, and what Unibus address is selected as

timing

chain

the

MSII

El112-A

went low, latch

can

starting

any

address.

This starting address

one that begins a 4K

block

of ad-

which

(Figure

results in the

timing logic are not busy,
4-4).

When

the

output

E119 generated

RSA

of
L,

first row of chips being se-

dresses; for example, 0000003 (OK), 0400005 (8K),

lected; the ADSTR H timing signal will latch E119

1200005 (20K), etc. The starting address is assigned

in this state, keeping RSA L asserted until the tim-

by arranging switches E111-A through El11-E (Fig-

ing cycle is completed. Data can be transferred to

ure 4-2) so that when this address appears on the

or from the memory location specified by the start-

produces

ing address. All addresses in the 4K block that be-

five output signals (at point A) that have the binary

gins with the starting address are identical in bits

BUS

A(17:00) lines,

the adder network

logic levels 11100. These five signals enable NAND

BUS

gate E112-A and, because a jumper is in place be-

dresses in this 4K block cause ADDRESS PRE-

AI3L

BUS

AI7L;

consequently,

all

ad-

tween W3 and W4, NAND gate E123. If both the

SENT H and RSA L to be asserted.

802¢-11

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07240 1

03S2TuIU1A-np30Ppd03iYa7(4]

0.3

‘310N

JAY

4-3

If the MSI11 in question has a word capacity of 8K,

The first address in the next highest 4K block of ad-

i.e., two rows of memory chips are installed on the

dresses (12K to 16K) is 060000s. When this address

module, all addresses in the next higher 4K block

appears

of Unibus addresses will also be assigned to the

E106 becomes 11101,. With a jumper connected be-

the

Unibus,

the

output

from

adder

MS11. When any one of the addresses in this 4K

tween W1 and W2, this address, and each address

block appears on the BUS A(17:00) lines, the adder

up to and including 077777, also causes the AD-

network produces an output represented by 11101,.

DRESS PRESENT H signal to be asserted.

The RSB L signal is asserted, selecting the second
row of chips. A jumper is connected between W]

Each

and W2; thus, ADDRESS PRESENT H is asserted

causes the adder output to increase by 1,. Thus, ad-

succeedingly

higher 4K

block

of addresses

and data can be transferred to or from a memory

dresses from 16K to 20K result in an adder output

location in the second bank of chips.

of 11110,, while those from 20K to 24K produce an
output of 11111,. Each address within these blocks
can cause the ADDRESS PRESENT H signal to

A third and fourth row of memory chips can be
added to the MSI I, increasing its word capacity to

be asserted if the appropriate jumper is connected.

as much as 16K. Additional Unibus address space

(Or if the switch is closed, in the case of the fourth

is assigned by adding a jumper between W35 and

block. This difference is explained shortly.)

W6 for the third row of chips and closing switch

E111-H for the fourth row. Table 4-1 relates the

The uppermost 4K of Unibus address space is re-

memory size, the adder output signal binary repre-

served for internal general registers and peripheral

sentation, and the jumper/switch E111-H arrange-

devices. A special

ment. Appendix A lists the required switch settings

part of this address space to be assigned to the
(in

feature of this memory allows

for EI11-A through EIl11-E for all of the 31 pos-

MSI1

sible MS11 starting addresses.

ment). Figure 4-3 shows part of the Address Decod-

processors

without

memory

manage-

ing logic, modified so that certain addresses in the
reserved space can be assigned to the MSI11-J Mem-

ory. If the memory has been assigned addresses in

Table 4-1

such a way that the uppermost 4K block of ad-

Address Space Assignment

MS11

Required

Capacity | Adder Output

dresses coincides with the reserved area (i.e., when
a 16K memory is assigned space from 16K to 32K

Eyelet Pairs Connected

in a 32K machine), switch E111-H must be placed

by Jumpers

11100

W3-W4

in the open position.

11101

W3-W4, W1-W2

A small system with few peripherals may not neecd

12K

11110

W3-W4, W1-W2, W5-W6

all

16K

11111

W3-W4, W1-W2 W5-Wé6

El11-F and El111-J can be closed selectively to al-

of the

reserved

address

space.

Switches

low the use of the lower 2K or lower 3K addresses

(switch E111-H closed)

of the reserved 4K block. Specifically, when El11-]J
is closed and El11-F is open, addresses from 28K
to

specific

example will

promote

further

MSI11-J, a

16K

30K

(160000¢ -

167777g) will cause the AD-

under-

DRESS PRESENT H signal to be asserted. When

memory.

both E111-J and El11-F are closed, addresses from

Four 4K blocks of Unibus address space can be assigned to the MSI11-J. The lowest 4K block is as-

the MSI1-J. Appendix A relates the switch settings

signed by selecting a starting address, e.g., 040000g

to the MSII

(8K). Switches E111-A - EIl11-E are set so that the

operations.

standing. Consider the

28K to 31K (160000g — 1737775) will be assigned to

options and the desired

1/O page

adder output is 11100, when address 0400005 appears on the Unibus address lines (Figure 4-2). Any
address in the 4K block of addresses beginning
with 040000y and ending with 0577775 (i.e., 8K to

of addresses, he should check carefully to ensure that

12K) will cause ADDRESS PRESENT H to be

no peripheral devices (including bootstrap ROMs) are

asserted.

assigned any of the reserved addresses.

NOTE

If a user is considering use of the reserved 1/0O page

4-4

BUS A15 L

11100

= IR
—q

BUS A14 L

ET1

11101 ——Q@B Q@

11110 —O@C®

Esl\

111114 —’—{"—:‘—‘
i
|

S—

J
Q

L q
BUS A1l L

—Q

BUS DCLO L

PRESENT H

lf"EflT":

BUS A12 L

ADDRESS

)

E60

|
|

e
_

ESS

NOTE:

Logic 1 is HIGH, logic @ is LOW, except for

the bus signals, where logic 1 is LOW and

logic @ is HIGH.
11-3209

Figure 4-3

4.3

Address Decoding, I/O Address Space Logic

TIMING SIGNAL LOGIC

Three kinds of timing cycles are carried out by the
MSI1 logic: a bus read cycle, a bus write cycle, and
a refresh cycle. Each cycle uses the same basic timing signals to select the addressed memory location.
These timing signals are generated by the logic
shown in Figure 4-4. Of primary importance are
the ADSTR H, COLAD H, and RFCY signals,
which are instrumental in gating the address information to the on-chip row and column address
latches, and the RAS, CAS L, and CS L signals,
which strobe the address information into these address latches.

asserts the REF WARN L signal and attempts to
initiate a refresh cycle. If a bus cycle is in progress
at the time, the Refresh logic waits until the BUSY
L signal is negated, indicating that the bus cycle
has just been completed. Then, the Refresh logic as-

serts the SRT CLK H signal.

Because bus cycles are carried out more often than
refresh cycles, the logic i1s always preconditioned for
a bus cycle. When a refresh cycle 1s initiated, certain logic elements must be changed from their pre-

conditioned state. One of these elements is flip-flop
E130 in Figure 4-4. This flip-flop remains in the
clear state until the SRT CLK H signal is generated

The timing chain is started when the SRT CLK H

signal is generated by either MSYN H, in the case

WARN L is low, the flip-flop is set, asserting the

of a bus cycle, or the Refresh logic, in the case of
a
refresh cycle. A bus cycle is prescribed when the
bus master places on the Unibus an address that
has been assigned to the MSI1. The address information is decoded by the Address Decoding logic,

the

Refresh

logic;

that

time,

since

REF

RFCY(1) H signal. The RFCY(1) H signal, along
with

the

COLAD

signal,

controls

the

multi-

plexers in the Address Path logic (Figure 4-8), se-

lecting

either

the

master

address

the

address

specified

the

Refresh

bus

which asserts ADDRESS PRESENT H. When the

logic. Thus, the multiplexers also change from their

bus master asserts BUS MSYN, the Timing Signal
logic generates SRT CLK H to begin the timing sequence. Every 25 us, the Refresh logic (Figure 4-6)

preconditioned state. To ensure that both flip-flop
E130 and the multiplexers have passed through the
transient period into their refresh cycle conditions,

RAS AL

RSB L —

ADDRESS PRESENTH

RAS B L

RSC

L —

E123

SSYN (O) H
MSYN H

SRT CLK H

RSD L————D

RAS C L

RAS
DL

RFCY (1)
L —
BUSY L

}

WARN L

BB +5V

—— ADSTR H

RAS H

E125

E120

a:
C 124

E125

R57

BB 45V

_l
I_/OE133 75107A
*

RFCY(1)H

BB+5V

,I_

BUSY L

C129;;

130 D——RFCY (1) L

REF REQ

0 o—

RFCY (O) H

BB+5V

[e127a 75107A

-I COLAD H

E131

BB +5V

€128 ;E
i

|e
E1278B

BB +5V

RFCY (O)H

—}——CSL

BB+5V

]
[E132 75078

l CLR STRH

v
11-3210

Figure 4-4

Timing Signal Logic

4-6

the beginning of the timing chain is delayed; 1i.e.,

than that at the inverting input, the output is low;

the time duration between the respective assertions

this is the condition that exists before the ADSTR

of SRT CLK H and ADSTR H is longer for a refresh cycle than for a bus cycle. This time delay 1s
introduced between the leading edges of the two signals by the integrating capacitor, C121. At the start

H signal is asserted. Shortly after ADSTR H goes
high, the voltage at the inverting input of EI127-A

begins to rise. About 100 ns later, when it has risen
to a value greater than the reference voltage at the
non-inverting input, the COLAD H signal is

of a bus cycle (the REF WARN L signal 1s ne-

gated) the SRT CLK H signal enables NAND gate
E125-B and C121 can discharge rapidly to ground
through a very small resistance (R57 is an 18-ohm
resistor). However, at the start of a refresh cycle,
REF WARN L is asserted; consequently, E125-B remains disabled and C121 must discharge through
the added resistance of R28 (560 ohms), increasing
the delay time before ADSTR H is asserted.

asserted.
When

COLAD

goes

high,

the address multi-

plexers in the Address Path logic select the column
address information; this information 1s placed on
the AOO-AO05 lines and later strobed into the onchip column

address latches by the CAS signal.

CAS is sent to all chips in the array. Chips that receive a CAS but no RAS will have their outputs go
into a high-impedance state.

The timing signals are illustrated in Figures 4-5 and
4-7. Figure 4-5 1s oriented to a bus cycle and is the

The last signal in the timing chain to go active 1s

basis for the remaining discussion in this section.

the CLR STR H signal. This signal not only resets

Figure 4-7 is oriented to a refresh cycle and s the

the timing chain by clearing the cross-coupled flip-

basis for the discussion in Section 4.4. The timing

flop (E120/E110) but also causes NAND gate E131

diagrams have the same time scales so that the com-

to generate a pulse sufficiently wide to clear flip-

mon signals can be compared, and each diagram re-

flop E130, thus conditioning it for a subsequent bus

lates

cycle (the flip-flop is cleared at the end of each and

the

appropriate

address

signals

and

the

multiplexer outputs to the timing signals.

every timing cycle).

When ADSTR H 1s asserted, 1t gates the address in-

The

formation

BUSY

from the multiplexer outputs onto the

end

the

timing

L 1s negated.

cycle

signalled

when

Unlike the other capacitor-

A00-AO0S5 lines. It also clocks latch E119. One out-

controlled delay circuits in the timing diagram, the

put of EI19 is latched low, indicating which 4K

circuit including C129 is concerned with the trailing

block of addresses contains the decoded address.

edge of the signal. Thus, the trailing edge of BUSY

When the RAS H signal goes high after ADSTR

L goes high quite some time after RAS H is ne-

H, only the bank of chips that corresponds to the

gated (approximately 130 ns). This satisfies a chip

selected 4K block of addresses will receive the RAS

specification

signal. This selectivity reduces the overall system

minimum of 150 ns at the end of
a timing cycle.

that requires

RAS to be high

for a

power dissipation, since chips that receive no RAS
signal

not

cycle

internally

and

thus

use

less

4.4

REFRESH LOGIC

The Refresh logic is shown in Figure 4-6; Figure 4-

power.

7 relates the significant signals (Figures 4-7 and 4-5
have the same time scales so that common signals

The

RAS

signal

strobes

the

information

the

can

compared).

refresh

timing cycle

is in-

AQ00-AO0S lines into the on-chip row address latches

itiated every 25 us when EI33 generates the REF

of the selected bank of chips. After the chip row ad-

CLK

dress hold time requirement has been met, the infor-

thereby asserting REF WARN L. If the memory is

mation on the A00-AO05

signal. This signal

clears flip-flop

EI135,

lines can be changed to

not busy, the SRT CLK H signal will be asserted,

reflect the column address. Thus, the COLAD H

setting flip-flop E130 and starting the timing chain

signal 1s asserted after a sufficient delay has been in-

(the SRT CLK H signal might already be high as a

troduced by the integrating capacitor C128 and its

result of the Address Decoding logic having recog-

associated circuit components. One of these com-

nized an MS11 address; if so, even though BUSY L

ponents is half of a 75107A

may still be high, the refresh timing cycle will be de-

Dual-Line Receiver,

which 1s being used as a level comparator. When

layed

the

completed).

voltage

the

non-inverting

input is greater

4-7

until

the

normal

memory

cycle

has

been

(‘)

600 ns

BUS MSYN

I__—

SRT CLK H

REF WARN L

RFCY (1) H

ADSTR H

RAS H

BUSY L

_r—
1

COLAD H

cas v

CLR STR
RAS L

[
1

]

cas L

s L

BUS SSYN

\U)

LABI=LAY2 7WEMSRY,LOCATION MDDRESS

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AB-AS

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[ROW ADPRESS (LAT2:LAB7/1/

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S 7777
S

COLUMN 'ADDRESS "(LAg6-LAG1
/)
11-321

Figure 4-5

Bus Cycle Timing Signals

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REF WARN L

STR CLK H

RFCY H

ADSTR

BUSY

REF CLK L

GO?ns

COLAD H

CAS H

E13@0-CLR

REF RST L

CLK

IS sI,

A@-AS5

REF REG

Réflglf/'/betgfl}fi/z 4/4

NOTE:
Logic 1 is HIGH.

Figure 4-7

11-3213

Refresh Cycle Timing Signals

multiplexers in the Address Path logic. When the

discharge. When the voltage at the non-inverting input of E133 drops below the reference voltage at
the inverting input, REF CLK L is negated. When
COLAD H later goes low, C144/145 starts charg-

timing chain asserts ADSTR H, after a delay that

ing; in 25 us, it will have charged to such a poten-

is long enough to ensure that both the RFCY flip-

tial that E133 again asserts the REF CLK L signal

flop (E130) and the multiplexer output lines have

and another refresh timing cycle is initiated. Also,

settled,

when COLAD H goes low, the 6-stage counter com-

The RFCY(1) H signal, generated when
E130

set,

causes

the

refresh

flip-flop

address

bits

RAO0O-RAOS5 to be placed on the output lines of the

the

refresh

address

gated

onto

the

A00-AO0S lines. The address is then latched into the

prising binary counter E83

on-chip row address latch by the RAS signal; all 64

clocked.

cells located on the addressed row are refreshed.
When the timing chain asserts COLAD H, the mul-

placed on the RAOO-RAOS lines and the 64 cells lo-

tiplexer outputs go to ground. The AQ0-AOS5 lines

the next refresh cycle.

The

and

next consecutive

flip-flops
refresh

E77

address

cated at that row address will be refreshed during

go high and are left in this state in preparation for
One of the last events to occur during the refresh

the next memory timing cycle.

cycle is the clearing of flip-flop E130, with the reThe COLAD H signal also resets the REF CLK L

sulting negation of

signal timer by enabling NAND gate E131, thereby
asserting REF RST L. This signal sets flip-flop

L signal is negated to identify the end of the refresh

cycle and the availability of the logic for a bus

E135 and causes the timing capacitor, C144/145, to

cycle.
4-10

RFCY (1) H. Finally, the BUSY

4.5

ADDRESS PATH LOGIC

4.6

DATA PATH LOGIC

When an address is placed on the Unibus, the Ad-

The logic shown in Figure 4-9 generates signals that

dress Decoding logic determines if the address is lo-

control

cated

MSI11

within

any of the 4K

blocks of addresses

the

flow

read/write

data

within

the

memory. These signals are developed in re-

assigned to the MSI1!. The specific address within

sponse to Unibus signals BUS A00 L, BUS CO L,

the 4K block is represented by the BUS Al

and BUS C1 L, issued by the bus master. The table

L -

BUS A2 L signals, illustrated in Figure 4-8, the

Address Path logic.

BUS CO L and BUS C1 L and the type of transfer

Figure

4-9

lists

the

possible combinations

specified by each combination. Related to these enThe address information is applied to three 7475

tries are, first, the 7475 latch (E115) outputs and,

latches

second, the control signals that gate data to and

latch

(E76,

E88,

follows the

and

E82).

respective

The

Il-output of a

input when the latch

from the memory chips. These control signals are

clock input is high: when the clock input goes low,

applied to the logic shown in Figure 4-10, the Data

the state of the D-input at the time of the clock

Path logic, which is illustrated only for data bit 15.

transition is stored on the l-output.
The address information is applied to the latch D-

inputs before the timing cycle

is initiated by the

SRT CLK H signal, i.e.. before ADSTR H is asserted.

Hence,

the

address

i1s

placed

the

LAOI-LAI12 lines before the timing signals are gen-

erated. At this time, both COLAD H and RFCY(1)
H are low; thus, the signals at the A-inputs of the

745153 multiplexers (LAO7-LA12) are gated to the
f-outputs. When the ADSTR

H signal goes high,

shortly after SRT CLK H i1s asserted, the address is
stored on the I-outputs of the latches, and the mul-

tiplexer f-outputs are gated to the A00-AOS5 lines.
These

bits

represent

the

row

address

and

are

latched into the on-chip row address latch by the
RAS signal.
The timing logic next asserts the COLAD H signal.
Now, the signals at the B-inputs of the multiplexers

(LAOI-LAO6)

are gated

through

the multiplexers

and placed on the AOO-AOS lines. These 6 bits rep-

resent the column address and are latched into the

on-chip column address latch by the CAS signal.
Now that the memory location has been selected,

data can be read from or written into memory.

single-transistor cells

makes periodic re-

freshing of the stored data necessary. Every 25 us, a

refresh cycle is carried out at one of the 64 row ad-

dresses.

During

this

refresh

timing

cycle,

would have a row of 16 or 18 chips installed on the

module, chip

E97 being the left-most chip in the

row:

memory

the

12K

would

have

three

rows

chips installed, chips E97, E96, and E95 being the

left-most in their respective rows. All chips are provided with the same address and control lines, ex-

cept for the Row Address Strobe lines, which are

different for each bank of chips; those chips that receive no

chips

RAS

that

input do not cycle internally.

All

comprise the upper byte of the data

word (i.e., bits 15 - 08, and parity bit P1) are supplied with the WBI

L signal, while the lower byte

chips are supplied with the WBO L signal.
If a DATO operation is to be performed, the bus
master places the memory address, the data, and

the control bits (BUS CO L and BUS CI L) on the

Unibus (Figure 4-11 shows the timing of a DATO
operation). The Data Path Control Signal logic as-

serts the DLS H signal near the beginning of the

cycle: later in the cycle it asserts the WBO L and
WBI

The dynamic technique used to store information in
the chip

In Figure 4-10 four chips are shown, one for each

possible bank of chips. For example: A 4K memory

L signals.

DLS H clocks the data from the

BUS D15 line into hex flip-flop E36; then WBI L
and CAS L jointly strobe the data from the DII5
line into the chip selected by the RAS X L signal
(the WBO L signal clocks bus data into the chips of

the lower byte of the data word).

RFCY (1) H signal is asserted by the Refresh logic.

While COLAD H

is low, at the beginning of the

Shortly after DLS H is asserted, flip-flop E135 (Fig-

cycle, the signals at the C-inputs of the multiplexers

ure 4-9) 1s set, asserting both SSYN(0) H and INT

(RAOO-RAQS5)

SSYN L. If the memory is equipped for parity oper-

are

gated

the

f-outputs;

from

there, they are gated onto the A0OO-AO0S lines when
ADSTR H goes high. This row address is latched

into the on-chip row ddress latch by the RAS signal; all 64 cells located on the specified row are refreshed (column addresses do not matter during the
refresh cycle).

ation, the INT SSYN

L signal causes the Parity

Control Module to assert BUS SSYN L (this module grounds the PARITY DETECT L line to prevent the MSI11

from generating BUS SSYN L). If

the memory is not so equipped, BUS SSYN L is asserted by bus driver E35.

BUS

A12 L

COLAD H

RFCY (1) H

BUS

Al1O L

A9
L

BUS

>_—"

7475

R1(1)

R2 (1) 5

STB1

LA12

- A1

LA6

—IB1

R3(1) o————uno

RA5S

——C1

R4 (1) ———

ENB1 ;N(B?_) o
l

BUS

E76

LAY

—

STBO
f1

A5 A L

> €99
AQ

LAS

RA4

T74S153

A4
B L

L 1D0

BUS

A8
L

BUS

A7
L

BUS

A6
L

R1(1)

LAS

R2(1)°o

LA7

R3(1)

LAG

DJ’__FM

R4 (1)

BUS

AS
L

ENB2

]

7475

ENBT

BUS

£88

A5 B L

LAS

O
‘o)

STB1

LA10

RA3

A3 B L

A3 A L

£1

A4
L

STBQ

£93

LAS

LA2

RA{

T74Si153

E82

BUS

A3
L

jDLm

BUS A2
L

7475

RIS

R2(1)

R4 (1)

[

ENB1

BUS Al
L

S]‘

LA3

‘o)

R3(1)

_—_D—J—o:;

L 1po

LAG

]

LA2

LA1

‘o)

ens2
P

STB1 STBO

LA7

LAt

RAQD

AD B L

ADSTR

AD
A L

L 1D1

L
—_

RAQ

—

RA 1

E83

—

LAS

AQ@

LA3

RA2

co
S1

TRA?)

L—-c
D

o—
|

745153
RA4

COLAD
H| RFCY(1)H|

o—

E77

A2 AL

o}—
E77

r——o

A2 B L
0

— DO

RA2

—

T74S153

RAS5

OUTPUT

LAI2 -LAQT

LAD6-LAOQ!

RAQ5-RAQO

LOW

11 - 3214

Figure 4-8

Address Path Logic

4-12

o1 | o1

7107 (1) 1y

1a—

4-13

Hsia

SS3YAAV

| — 1@0Sns

@DH —0
) zflmm

$H1a

- r

AS
A3

CAS

rrrrcrr

wB1t

RAS AL

Dog

E97

é\_g

(“TOY9P‘5)

DO15 H

DI15 H

DIN

AD
B

DouT

A2
B

B
A3

A5
B
A4
B

E96

RAS
B L

A5
A L

A4 AL
A3

A2 A L

ESS

A1
A L

AD AL

RAS
C L

E94

RAS DL

DLS H

R2(1)

E36
74174
HEX FF

CLK
R1(1)

|8641

ENBUS L

A®

[T —

}

——

}—BUS DI5 L

11-3216

Figure 4-10

Data Path Logic [Bit D(15)]

4-14

600 ns

BUS MSYN L

BUS C1

BUS CO L

LC1 H

LCP H

BUS OIS L/ /00007

SRT CLK

[ ]

DI 15 H

ADSTR H

[

bLS H

SSYN (@) H

COLAD H

T
-

wB@ L/WB1

L
11-3217

Figure 4-11

Data Write Timing (DATO

The Data Path logic functions the same way for a
DATOB operation if the BUS A00 L signal is as-

Figure 4-12 shows the timing for either a DATI or
a DATIP operation; the two are treated identically

serted by the bus master. In this situation, a data
is transferred on the BUS D (15:08) lines,

by the memory. The DLS H signal again clocks
flip-flop E36, in this instance loading the informa-

byte

WBI L is generated, and the data is strobed into
the upper-byte chips. If BUS A00 L is not asserted,
only WBO L is generated and data is strobed into

tion

the lower-byte chips.

onto the BUS DIS line.

the

DOI5

line

into

the

flip-flop.

The

ENBUS L signal, generated near the start of the
bus cycle, gates the data from the flip-flop output

4-15

— —O

BUS MSYN L

600 ns

BUS Ci
L

BUS CO L

H
LCT

LCO H
DO1S

SRT CLK H

BUS D15 L

ADSTR H

|
—

ENBUS L

COLAD H

DLS

SSYN (@) H

Figure 4-12

Data Read Timing (DATI)

4-16

CHAPTER 5
TROUBLESHOOTING HINTS

5.1

GENERAL

(EI1TA-EI11E) for a starting address of 000000x,

The information in this chapter is designed to sup-

and halt the processor. Use a scope to check the fol-

plement the technician’s knowledge of the MSI11 by

lowing signals at the input of the Timing Signal

suggesting possible courses of action for trouble-

logic (NAND gate E123).

shooting the memory. These suggestions are based
on the assumption that the system fault has been

Signal

traced to the memory module by some means, e.g.,
module

swapping

system

troubleshooting

Expected Logic Level

ADDRESS PRESENT H

procedures.

If the diagnostic program can be loaded and exe-

HIGH

MSYN H

LOW

SSYN (0) H

HIGH

cuted, the problem will generally be solved. How-

ever,

might

not

possible

load

the

diagnostic: or, the diagnostic might not execute correctly after being loaded. This chapter deals with

The state of the ADDRESS PRESENT H signal

these

will show if the memory address has been decoded:

two problems by

providing troubleshooting

hints of two broad classes: those dealing with faults

the

that prevent the diagnostic from being loaded, and

SSYN

those dealing with faults that prevent the diagnostic
from being executed. The first class of faults is cov-

logic (Figure 4-9). If any of these signals do not
have the expected logic level, follow the lead sugges-

ered in Section 5.2, the second is discussed in Sec-

ted until the fault is found.

other

two

flip-flop

signals

relate

Data

Path Control Signal

the

state

of the

tion 35.3.

5.2
5.2.1

If these signals are good, check the Timing Signal
logic. Even though the processor is not running, the

DIAGNOSTIC LOADING PROBLEMS

Timing Signal logic is generating signals during the
periodic refresh cycles. The SRT CLK H signal is

BUS SSYN L Not Asserted

When the operator tries to load the diagnostic pro-

asserted about every 25 us to begin such a cycle

gram, the memory should respond by asserting the

BUS SSYN

L signal.

(Figure 4-7, Refresh Cycle Timing Signals).

A trap in the program in-

dicates when BUS SSYN L is not returned by the

If the problem cannot be traced to either of these

memory.

two groups of logic, devise some method of check-

ing the condition of the BUS MSYN bus receiver,
the SSYN flip-flop logic, and NAND gate E123

In order for the MSII to generate BUS SSYN L,

the Address Decoding logic (Figure 4-4) must be
working.

Set

the

address

selection

(Figure 4-4), which is enabled at the start of a bus

switches

cycle.

5-1

5.2.2

5.2.2.3

BUS SSYN L Asserted

Address

Circuits

The

simple

test

de-

If the memory issues BUS SSYN when addressed

scribed 1n this section will check the MS11 address

but the diagnostic cannot be loaded, five areas are

circuits

suspect: refresh circuits, data circuits, address cirStep |

cuits, write logic, and loader memory locations.

Deposit data word 000000 in the fol-

lowing

locations:

000000,

000002,

000004,

000010,

000020,

000040,

000100,

000200,

(Figure 4-6). Ensure that the refresh cycles are oc-

000400,

001000,

002000,

004000,

010000,

curring every 24 us. Scope the outputs of the re-

020000.

5.2.2.1

fresh

Refresh Circuits — Check the Refresh logic

counter

(E83

and

E77,

Figure

4-6);

the

counter outputs should look like the waveforms il-

Step 2

Deposit 777777 in location 000000.

Step 3

Examine location 000002; the data

lustrated in Figure 5-1.

5.2.2.2

Data Circuits - The simple tests described

this section

will check

the

MSII1

should be 000000, as deposited in Step

data in/out

paths. Use memory location 000000y. Deposit and

stuck low or high, or shorted to a previous ad-

examine all 1s, then deposit and examine all Os. If
unexpected

results

occur,

memory

location

000000s.

the

Check

for

1. If

the data i1s 777777, the current address bit is
dress bit.

symptoms.

Step 4

Deposit 777777 1n location 000002.

shorts by depositing and examining, successively,

Step 5

Examine location 000004; the data

the following data words: 000001, 000002, 000004,

should be 000000, as deposited in Step . If

000010,

Again,

use

000020,

000040, 000100, 000200, 000400,

the data is 777777, the current address bit is

001000, 002000,

004000, 010000, 020000, 040000,

stuck low or high, or shorted to a previous ad-

dress bit.

100000.

—]

|e=25ps

RA¢||||I|||||||||||||||||||||||||||

RA1||||||||||||||I|
RA2

RA3

|
|

L__.
L.

RA4

RAS
11-3219

Figure 5-1

Refresh Counter Timing

5-2

Step 6

Carry on the sequence begun 1n

Location

Step 2. That is: deposit 777777 in one of the
memory locations listed in Step 1 (000004 1s

Contents

MOV #(Low) RO

10*

012700

next): then, examine the next location to make
sure that the data in that location 1s still

000076**

14
[6

012701
020000**

MOV#High+2) RI

000000.

005004

CLR R4

005005

CLR RS

005105

COM RS

010002

A: MOV RO, R2

010422

B: MOV R4, (R2)+

020201

CMP R2, R

001375

BNE B:

010002

MOV RO, R2

011203

C: MOV (R2), R3

020304

CMP R3, R4

001401

BEQ D

000000

010512

5.2.2.4 Write Logic - To check the write logic,
toggle in the routine listed below, beginning at location 000100. Scope the circuit illustrated in Figure
4-9 between the CO L, CI L, and A0 L bus receivers and the WBI1 L/WBO L signals.

012700

MOV #1, %0

000001

005001

CLR %1

HALT

110110

A:MOVB %1, (0)

010111

%1, (1)
MOVB

011203

MOV (R2), R3

000765

BR A

020305

CMP R3, RS

BEQ E

5.2.2.5

Loader Memory Space - Load the program

listed below. This routine verifies that all bits can
hold a 0 or a I, and that writing into any address

does not affect the contents of anv other address. It
does not check for bit-to-bit shorts within a word;

001401

000000

HALT

005722

E: TST (R2)+

020201

001364

BNE C

005104

F: COM R4

005105

COM RS

000754

BR A

that test was done by Section 5.2.2.3.

D: MOV RS, (R2)

CMP R2, RI

If the general registers can be loaded from the console,

load

them

follows (locations

10 -

need

not

loaded): then load the rest of the program beginning at location 26.

The test carried out loops continuously until a failure occurs. It can be made to halt at the end of a
pass by changing location

74 to 0. A

RO - Lowest test address (generally 000076)

pass takes

about one second. When the test halts because of a

- Highest test address

plus 2

(020000 for 4K

of memory)

fatlure, R2 holds the failing address and R3 holds

R4 - 0Os

the bad data. If the test halts with the PC=50, R4

RS - 1s

has the good data; if 1t halts with the PC=62, RS

**Location 12 contains the lowest address to be tested: loca-

has the good data.

tion 16 contains the highest address to be tested (plus 2).

5-3

5.3

DIAGNOSTIC EXECUTION PROBLEMS

the diagnostic executes correctly, the upper 4K was

If the diagnostic program cannot be executed as di-

indeed

rected by the program documentation, the refresh

To remove the lower 4K from the circuit, set the ad-

circuits may not be working, or a portion of the ar-

dress

ray may be faulty. Check the refresh circuits first

[1101: then remove the jumper at location W3-W4,

(refer to Paragraph 5.2.2.1). If the Refresh logic ap-

This, in effect, moves the upper 4K down so that it

pears to be operating correctly, use the following

becomes the lower 4K. Both the diagnostic and the

procedure to check on the array (the memory capac-

loader will be placed in the new lower 4K. If the di-

ity must be 8K or greater).

faulty and can be examined more closely.
selection

switches,

ElII-A

EIII-E,

agnostic executes correctly, the original

for

lower 4K

was faulty.

The program loader is stored in the upper 4K of
memory, while the diagnostic is stored in the lower

4K (assume an 8K memory). If either bank of chips

The same technique can be used for 12K and 16K

1s suspected of being faulty, that bank can be re-

memories. To remove the highest 4K, disconnect

moved from the circuit. For example, the upper 4K

the jumper at location W5-W6 (12K memory) or

can be removed by disconnecting the jumper at lo-

open switch ElI11-H (16K memory):; to remove the

cation W1-W4, Then, both the program loader and

lowest 4K, set

the diagnostic will be loaded into the lower 4K. If

W4,

11101

and disconnect jumper W3-

APPENDIX A

MS11 SWITCH SETTINGS

Table A-1 first lists the 31 addresses that can be assigned as the starting address on the MS11 module.

Listed next is the number of Unibus addresses below the MSI11 starting address; e.g., there are 8096

(8K)

Unibus

addresses

below

starting

address

0400005. Finally, the third column lists the switch
settings that will produce the desired address assignment. The MSI11 ending address is automatically determined by the starting address and the memory
size. Table A-2 shows how switches H, J, and F

must be arranged for normal operation and when
I/O page space is assigned to the MS11.

Table A-1

Switch Settings for MS11 Starting Addresses
MS11 Starting Address

Unibus Addresses Below

Switch Selection

(Octal)

Starting Address

(Switch OFF = Logic 1)
AlB|CI]|]D

000000

020000

040000

}|o

060000

12K

120000

20K

| 1

]

140000

24K

]oO

100000

16K|

1|1

160000

28K

|10

200000

32K

|oO

220000

36K

(0!

240000

40K

(0|1

260000

44K |

300000

48K_

|00

|oO

320000

52K

340000

56K

|11

1|0
|1

360000

60K

(1|0

400000

64K

{1010

420000

68K

440000

72K

0|1

1]o0

460000

76K

o101}

500000

80K

o101}

0]oO

520000

84K

540000

88K

olo

}]1]0

560000

92K

olo

600000

96K

o]lo]1]o0]oO

620000

100K

olo

640000

104K

olo]o]|1}]oO

660000

108K

001010

700000

112K

olol]o|lo|oO

720000

116K

740000

120K

N
T T
1|1

NOTE

Switch contacts are open when switch is in OFF position

A-2

ST
ST
1|1

|1
|1

1]o0

Table A-2

Switch Settings for I/O Page Operation
Memory Size Determination
Switch

Memory Option

MS11-E/EP,MS11-F/FP,

OFF | OFF | OFF

MS11-H/HP

MS11-J/JP, Normal Use

OFF

MS11-J/JP, Lower 2K of I/O | OFF | OFF

page assigned to memory
*

MS11-J/JP, Lower 3K of I/O

OFF

page assigned to memory*

*Set switches A through E for a starting address of
100000g.
NOTE

Switch contacts are open when switch is in OFF position.

A-3

APPENDIX B

IC DESCRIPTIONS

This appendix contains descriptions of several in-

put holds the state it was in prior to the transition.

tegrated circuits used in the MS11 logic. Only those

The logic diagram, a truth table, and a pin locator

ICs of an unusual nature are described; the more

are shown in Figure B-1.

common types, i.e., NAND gates, inverters, flipflops, etc..., should be familiar to the reader.

7483

Binary Full-Adder

The 7483 is a 4-bit binary full-adder used for paral7475

4-BIT BISTABLE LATCH

lel-add/serial-carry applications. It adds two 4-bit

The 7475 is a 4-bit bistable latch. Information pre-

binary numbers (A and B) and provides a sum (S)

sent at the data input (D) of a latch is transferred

output for each bit. The resultant carry (CARRY

to the 1 output when the clock input (C) goes high.

OUT) 1s taken from the last bit of each adder. The

If the C input remains high, the 1 output follows

logic diagram and a pin locator are shown in Fig-

the D input. When the C input goes low, the 1 out-

ure B-2.

—D
g

FUNCTIONAL BLOCK

DIAGRAM (EACH BIT)

LOGIC DIAGRAM (EACH BIT)
TRUTH TABLE

(EACH BIT)

Toen

1 [ BiT 1,0-0uTPUT

2 [] eiT 1,D-INPUT

BIT 2,1-OUTPUT [ ] 15

LOW

3 [ BiT 2,0-INPUT

BIT 2,0-0UTPUT [ ] 14

Tni BIT TIME BEFORE C-INPUT

4 [] BIT 3,4,c-INPUT

BITS1,2,C-INPUT [ ] 13

D
HIGH

LOW

HIGH

TRANSITION

T(n+1):BIT TIME AFTER C-INPUT

5[] vee

TRANSITION

oND | ]12

6 [] 81T 3,0-INPUT

BIT 3,0-O0UTPUT [ ] 11

7 [] siT4,0-INPUT

BIT 3,1-OUTPUT []10

8 [] BiT4,0-ouTPUT

BIT 4,1-0UTPUT [
PIN

Figure B-1

BIT 1,1-0UTPUT [ ] 16

7475 4-Bit Bistable Latch

LOCATOR

]9
1C-0107

A1l
S1

[

*>—

81
CARRY IN

]

‘

[

A2
s2

—{
B2 >o—

S CARRY OUT

INPUT

OUTPUT

LOGIC

DIAGRAM

WHEN

Co=0

I Ir]r]

CSS?Y CAII:‘RY

GND

Vee

LOCATOR

(TOP VIEW OF IC)

]

Ofm]|s]=]O0OlO0O|O|OC|O

TM~

alajlolojlo|lol=|O|0lO]|
| 2|=|=|0O
s

=lo0olo|lo|]=|o|lOojlO|O|OC|lOQ
O

=|OC|lO|=|~|0OC]l0|w]=]|]O|]OC|=

|
=

t
&

i
w

a0l =|=2|2]|=10)]0]|C
-l cololo|ol =

»n

O|lm|=mw|lO0l0|wlwlo/lCOlw|
=100 |~=|= 0O

)

@TM

000000
|O
w220
]|
|
|
e
-

w0000
=
=lsl10]0|]0|OC

OC|w]|l=l0l0|=]=20]0|=|=10/|0

wiO|l=m|lO0|lwlo|ljOol=|0O|~=|O]=]1O0|=]0

NOTE 1:

WHEN

Co=0

/1By

WHEN

Input conditions at A3, Ay, By, B2, and C() are used to determine

outputs ¢ and X9, and the value of the internal carry Co.

The

values at Cp, A3, B3, Ag, and By, are then used to determine
outputs Z3, X4, and Cq.
1C-0093

Figure B-2

7483 Binary Full Adder

74S153

The

Data Selector/Multiplexer

74S153

dual,

4-bit

data

selec-

tor/multiplexer that provides a single output for
each input section. The logic diagram, a truth table,

and a pin locator are shown in Figure B-3.

STROBE 1G

(10

<{>

(ENABLE) !

o1€0 (6)

1C1 (5)

‘

DATA

(7)

1C2 (4)

*—

1C3 (3)

—

O—

B(2)

:|>

(14)

r_({>

o—

v )

ADDRESS

2C0 (10)

OUTPUTS

}

—

2C1 (11)

DATAZ{

]

(9)

2C2 (12)

[

2C3 (13)

}

- O—

STROBE 26
(ENABLE)

_(15)

Vee ]= PIN 16
GND:=PIN

LOGIC

Vee
CONTROL

INPUT | STROBE | QUTPUT

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

DON'T CARE

(EACH HALF)

STROBE

SELECT

DATA INPUT
A—

—
10

OUTPUT
2Y

I'——]

l—-l

[——I

E—l

r—l

r——j

9
r——-l

Vee

2C3

2C2

2Ct

2CQ

1G
B
13
1c2
1C1
LT
1
1
1
I
|

TRUTH TABLE

DIAGRAM

STROBE
B
IG
SELECT

—v~

DATA INPUT

1cQ
1Y
GND
1
1
]
6

“

OUTPUT
1Y

GND

1C-0096

Figure B-3

74S153 Data Selector/Multiplexer

B-3

74197

PRESETTABLE BINARY COUNTER

The 74197 is a presettable binary counter that can
also be used as a latch. The IC consists of four dc-

coupled. master/slave flip-flops connected to provide a divide-by-two counter and a divide-by-eight
counter. The logic diagram, a truth table, and a pin

locator are shown in Figure B-4.

DATA A

::::::

COUNT/LOAD

CLEAR
CLOCK { —{T

DATA
B

1
QB

Q¢

CLOCK
2 —{ T

DATA C
*—

DATA D

'C-0112

Figure B-4

74197 Logic Diagram (Sheet 1 of 2)

B-4

TRUTH TABLE

The 74197

in any one of three modes:

CLOCK TINPUT

90| 9c |98 ] 9a

olol]1]o0

must be externally connected to pin 6. The clock in-

2
5
e

oo ds
ol
1]
o] 1
ol
¥

put is applied at pin 8. The initial count can be preset to any value by placing a low on pin 1 and
entering the data on pins 4, 10, 3, and 11. When

8
1%

t]ojlojo
:
8
?
(‘)

pin 13 is a taken low, all outputs are set low, regardless of the state of the clock inputs.

the divide-by-two/divide'-by-eight m(?de (requiring
no external interconnection of IC pins), the latch

mode, and the binary counter mode. Only the

tpr|ofo

A T

112

binary counter mode is used in the MSII. Pin 5

75107A

(13

1 I

ceiver with common voltage supply and ground ter-

minals. It 1s designed to detect input signals of 25
mV amplitude, or greater, and convert the polarity

LOCATOR

N SA O

CLEAR

DATA

COUNT/

DATA

CLOCK

put logic levels. An outline drawing of the chip, giv-

Vee

of the signal into appropriate TTL-compatible out-

Dual Line Receiver

The 75107A is a high-speed, two-channel line re-

Qpconnected to CLOCK 2 input.

LOAD

be used

oUTPUT

can

COUNT

ing pin connections, a logic diagram, and a truth

CLOCK

table as are shown in Figure B-5.

GND

CJJrtJjtJe
1o i1 J
1

Figure B-4

iC-0113

74197 Truth Table

and Pin Locator (Sheet 2 of 2)

PIN CONNECTIONS
14

INPUT 1A

INPUT 1B

NC 33

LOGIC
INPUT 1A ——+

v—

INPUT 18 —1=

1200 INPUT 2A

1] INPUT 28

STROBE S

STROBE

1G []5

STROBE S (]6

9] OUTPUT 2Y

INPUT 24

GND 47

S TROBE 26

STROBE 26

INPUT 2B —1—
—>

TRUTH
DIFFERENTIAL

the

STROBES

L orH

25mV

Vip € —25mV

non-inverting input with respect to
.

TABLE

Vip225mV

NOTE:
voltage at

}OUTPUT 2Y

G
Lor

the

A-B

—25mV < Vip <

Vio represenis

f—‘} OUTPUT 1Y

STROBE 16

OUTPUT 1Y (4

DIAGRAM

the inverting input.

LorH

INDETERMINATE

L or H

LorH

L
11-3220

Figure B-5

75107A Dual Line Receiver

B-5

7812 Voltage Regulator

COMMON (3)

The 7812 is a 3-terminal, positive voltage regulator.
In the MSI1I, the 7812 uses the +15 Vdc supply as
its input and provides a regulated +12 Vdc output,

/) O

which 1s used as the chip Vgp source.

OUTPUT (2)

INPUT (1)

An outline drawing, locating input and output pins,

is shown in Figure B-6. Table B-1 lists some signifi-

cant electrical characteristics of the IC.

Figure B-6

7812 Outline Drawing (Top View)

Table B-1
7812 Electrical Characteristics

Parameter

Conditions

Min.

Output Voltage

Tj=25°C

11.5 | 12.0 | 125

10
10

120
20

mV
—v

120

Line Regulation

Tj=25C

Load Regulation | 1j=25"C

145V<V,
.
IN <30V
TS Vi <22V

SmA <1 QUT <15A
.

—zremg logr < 730 mA

B-6

| Typ. | Max

Units

0 [ 60 | mV

;

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