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Document:	MRV11-D Universal PROM Module User Guide
Order Number:	EK-MRV1D-UG
Revision:	001
Pages:	71
Original Filename:

OCR Text

EK-MRV4D-UG-001

MRV11-D Universal
PROM Module
User Guide

EK-MRV1D-UG-001°

MRV11-D Universal
PROM Module
User Guide

Prepared by Educational Services
of

Digital Equipment Corporation

First Edition, May 1983

The 'reproduction of this material, in part or whole, is strictly prohibited For
copy information, contact the Educational Services Department, Digital
Equipment Corporation, Maynard, Massachusetts 01754.

The information inthis document is subject tochange without notice. Digital

Equipment Corporation assumes no responsibility for any errors that may
appear in this document.

UniPak is a trademark of Data I/O Corporation.
The following are trademarks of Digital Equipment Corporation, Maynard,
Massachusetts.

Eflfiflflan

DECwriter

P/OS

Professional
Rainbow
RSTS

UNIBUS
VAX
VMS

DECUS

MASSBUS
PDP

RSX

VT
Work Processor

DEC
DECmate
DECnet

DIGITAL
LA
LSI

CONTENTS

SYSTEM DESCRIPTION

CHAPTER1

1.1
1.2
1.3
14
1.4.1
1.4.2
143
1.5
1.5.1
1.56.2
1.5.3
1.54
1.5.5
156
1.6
1.6.1
1.6.2

ee 1
GENEIAD .ottt
FeatUres ..ottt e 2
e 2
ConfigUration . ....o.iei
Addressing MOdes . ...t 4
Direct Address Mode ... 4
Page Mode Addressing ..........ccooiiiiiiiiniinns 5
BOOtStrap .. ..o 5
Physical and Environmental Specifications ................ 7
Physical Specifications ... 7
Temperature ..ol 8
Relative Humidity ................... e ]
ee 9
AU . . et
ot 9
Sea Level Operating Airflow . ..........ocoiiii
e 9
Mechanical ShOoCK ...
Eilectrical Specifications ... 9
e ]
e
P OWET o oo e
TEChNOIOGY v e ov vt 10
FUNCTIONAL DESCRIPTION

CHAPTER2

2.1
2.2
23
24

INtrodUCHION .. e 11
DireCt MOGE .ottt 11
Page Mode ...o.oiiiiii i 14
Bootstrap MOde ... ..ot 16
JUMPER CONFIGURATIONS

CHAPTER3

3.1
3.2
3.2.1
3.3

. e 21
.l
......
Introduction ...
CONFIGURAtION . ..ottt 22
Installing MXV11-B2 ROM on MRV11-D....... e 22
PROM Sizes and PiNOULS .....ovvierii it 37

CHAPTER4

4.1
4.2
4.3

PROGRAMMING

e nnes 39
INEFOGUCTION v e st ettt e e e et e e
ienenns 39
....coooii
Executing Windowed Programs ..........
..... 41
RAM
to
ROM
Transferring Application Programs from

iv.

CONTENTS

PROGRAMMING THE ARRAY DECODER

CHAPTERS5

5.1

Introduction .............ooiiL TR

53
54

Array Decoder ... ... e
Guidelines and Restrictions ................ e

5.2

5.5

Decoder Programming Hardware ......................o0

Designing an Array Decoder ...t
MAINTENANCE

CHAPTER6
6.1
6.2
6.3

Introduction ............... e N
Troubleshooting ...t
R P
1= 3 © ] 5 1 S
[070]a7=7e)

APPENDIX A

MODULE CONFIGURATION

FIGURES

Page Mode Addressing ............cooiiiiii it
Page Mode Bootstrap ...........coo it
Direct Mode Block Diagram ............coiviiiiirieiieannn
Direct Mode Addressing ..........cocoiviiiiiiiiiiiinanns

Chip Select and Out-of-Range Functions (Dlrect Mode) ...

Page Mode Block Diagram ............cocooiiiiiiiiainn
....
... ..ol
Bootstrap Mode Block Diagram ..........

Bootstrap Access to Window O (/O Page} .................
Bootstrap Access to Window 1 (/O Page) .................

MRV11-D Chip Set Locations ..................ooo,

Jumper Configuration Flowchart ..........................
Jumper and Switch Locations ............... ..ol
PROM Sizes and TYPES .ovvreiiintiiaeaaianaaianenes
Insertion of 24-Pin PROM Chips

..........c.ccoiiiiininns.

JSR and JMP Control Routines for Window Mapping ......
Bootstrap Loader for Standalone Programs in RT-11
SAV FOrmat oot
i i e e
i
2K Array Decoder .....c.iiiiiiiniiiiii

Pattern Select ...t
e
e
Pin Designations for Array Decoder .......................

Direct Mode Format for Array Decoder ....................
Page Mode Format for Array Decoder .....................
Array Decoder Design-Example 1 ...............ccovuitn.
Array Decoder Design—Example 2 ...t
Array Decoder Design~Example 3 .............ccooiiian.
Module Configuration ...t

CONTENTS

TABLES
Storage Capacity Per ROM Chip Size and Number
of Chips ..o iv i D

Typical EPROMS ... e
e

4 .

Battery Backup Shunt (W1, W2) ........................... 26

System Size Jumpers (W3) ... 27
ROM/RAM Selection Jumpers (W4, W5) ................... 28

DATO Jumper Connection (WB) ...............cccvviiian, 29
Device Size Jumpers (W7, W8) ........
... ..o
ian, 30
Power Jumper Connections (W9, W10, W11, W12) .. .. .... 31
Read Timing Jumper (W13) ... ... i, 32

Enable Bootstrap Jumper(W14) .................. e 33
Standard Decoder Pattern Select Jumpers ................ 34
PCR Address Switches ... 35
Starting Address Switches ...........
...
i, 36
Array Decoder Programming Hardware .................... 43

Chip Select and Range Bits for Fully Populated Module ... 46
Console ODT Commands......e 58
Console ODT States and Valid Input Characters .......... 59

SYSTEM DESCRIPTION

1.1

GENERAL

The MRV11-D is a universal, programmabile read only memory (PROM) module. It
is a flexible, high-density, dual-size module for 16-, 18-, or 22-bit Q-bus systems.
The MRV11-D can be used in PDP-11/02, PDP-11/03, SBC-11/21 single board
computer, PDP-11/23A, or PDP-11/23B systems. The module contains sixteen 28pin sockets that accept static random access memory (RAM) and a variety of user-

supplied ROMs, such as fusible link PROMs, ultraviolet erasable (UV E)PROMs,
and masked ROMs. It accepts several device densities up to and including 32K by
8. With sixteen 32K devices, memory capacity is 512 kilobytes.
The contents of the module can be accessed in one of two modes, direct mode

addressing or page mode addressing, which emplpys a window-mapping
technique.

Direct mode addressing provides immediate access to all memory locations on the

module. Page mode addressing, or window mapping, provides two 2-kilobyte windows in bus address space that map a 2-kilobyte page each of the memory array.

The page that is viewed or accessed through each window (2 kilobytes per win-

dow) can be varied under program control through a page controt register (PCR).
The PCR must be written with the desired page number before the access. A
bootstrap feature allows 64 kilobytes of bootstrap code.

1.2

SYSTEM DESCRIPTION

FEATURES

The MRV11-D has the following features.

Full 22-bit Q-bus addressing capability as well as 16- or 18-bit Q-bus
addressing

Four-kilobyte starting address boundaries

Dwectmode drbéée'moae addressmg )
'MXV11-B2 bootstrap PROM option
Sixteen different page control register locations
Bootstrap page control register
Standard bootstrap
Bootstrap disable

ROM sockets that house 2K, 4K, 8K, 16K, or 32K by 8 ROMs as well as static
RAM

Normal or optional high-performance timing

Optional battery backup for static RAM
Capacity of 0 to 0.5 megabytes
1.3

CONFIGURATION

The MRV11-D contains 41 jumper posts, 2 switch packs, and 16 memory chip
sockets. The user can configure desired features by connecting the jumper posts
with the 13 jumper clips that are supplied with the module. The module is shipped

from the factory with ali jumper clips installed.

The following features can be configured by means of the jumper clips or by the
two switch packs on the module.
Page/direct mode addressing
Location of PCR
Bootstrap enable/disable

Use of multiple MRV11-D modules

Normal/high-performance timing
Switch-selectable starting address
Allow/inhibit DATO bus cycle
Memory array size and response pattern

Small system/large system
Static RAM

SYSTEM DESCRIPTION

The size of the memory array is determined by the size of the memory devices

installed. The MRV 11-D is shipped with no memory devices installed, so the user
must provide and install them.
Digital Equipment Corporation supplies a standard array decoder on the module
that is a preprogrammed fusible link PROM. In the basic configuration with this
array decoder installed, all memory chips must be the same size (2K by 8, 4K by 8,
or 8K by 8). The pin configuration of the chips must conform to the Joint Electron
Device Engineering Council (JEDEC) standard pinout for byte-wide devices. The
following four patterns are available with the standard array decoder supplied by

Digital.
2K by 8 half-populated (socket sets 0-3)
2K by 8 fully populated

4K by 8 fuily populated
8K by 8 fully populated
The user can populate the module with many other combinations of devices by

programming his own array decoder. (See Chapter 5.) There are certain device
mixtures that are restricted. Chapters 3 and 5 describe these restrictions.

The user can also configure a system with more than one MRV11-D. Table 1-1
shows the storage capacity per module as a function of device size and number o6f
device chips. This table lists the capacities for configurations with similar device
sizes. It does not account for the configurations with mixed device sizes that can
be used if the customer programs his own array decoder.

Table 1-2 lists typical UV PROMs and PROMSs that can be installed on the MRV11-

D. Other UV PROMs or PROMs that conform to the JEDEC pinout can also be
used.

Chapter 3 describes how to configure the MRV11-D. Figure 3-1 shows the physical
location of the 16 memory chip sockets. They are divided into eight chip sets, chip
set O through chip set 7. Each chip set is composed of a iow byte and a high byte.

SYSTEM DESCRIPTION

1.4

ADDRESSING MODES

The MRV11-D can be configured to operate in one of two addressing modes, page
mode and direct mode. Configuration is accomplished by setting a hardware

switch on the module and is not variable under program control.
1.4.1

Direct Address Mode

In direct address mode, each memory location on the MRV11-D has a corresponding location on the system bus. The number of system bus address locations allocated to the module is equal to the module’s configured capacity. For example, an

MRV11-D that is fully populated (16 devices) with 4K by 8 PROMSs (64 kilobytes)
corresponds to 64 kilobytes of the system bus. The starting address of the module

and the array decoder pattern determine the boundaries of the module’s address
range.

The starting address of the MRV11-D can be placed on any 4-kilobyte boundary

from address Og to 17770000g. However, the module’s main memory does not
respond to any I/O page accesses, even if the address range overlaps the I/O

page. Only the bootstrap areas and the bootstrap PCR, if enabled, respond in the
I/O page under direct mode addressing.

SYSTEM DESCRIPTION

1.4.2

Page Mode Addressing

Page mode addressing is a virtual addressing scheme that extends the addressing

capability of the system bus. A 4-kilobyte segment of the system bus and an 11O

register called the page control register (PCR) are assigned to the MRV11-D. The
MRV11-D’s starting address determines the beginning of the module’s portion of
the system bus. The user configures the PCR address to 1 of 16 locations in the

/O section of the system bus.
The MRV11-D’s portion of the system bus is further divided into two sections called
windows. Each window is 2 kilobytes long and can contain any 2-kilobyte page of

data on the module. The two pages of data that are currently available to the system have their page numbers stored, one in each byte of the PCR. To move a different page into the window, simply change the contents of the corresponding PCR
-

byte to the number of the desired page.
Figure 1-1 displays the page mode function. The MRV11-D has been assigned to
the bus addresses from 16650000g through 16657776g. its PCR is at 17777036g.
In this example page 1 appears in window 0 and page 5 appears in window 1.

Notice that the low byte of the PCR contains a 1 and the high byte contains a 5,
controlling windows 0 and 1 respectively.
Bits 7 and 15 are not part of the page numbers. Bit 7 is unused and bit 15 is the
window control bit. When bit 15 is asserted (1), the windows are open and the

pages in the windows can be accessed. When bit 15 is not asserted (0), the windows are closed and attempted accesses through the windows produce a bus
timeout.

Upon power-up and restan, the PCR bits are cleared to 0. Both windows contain
the data from page 0, but they are closed because bit 15 of the PCR is also 0. Bit
15 must be setto open the windows.
1.4.3

Bootstrap

The MRV 11-D bootstrap operation is similar to page mode addressing. It is independent of the address mode chosen for the module. The bootstrap windows are

split. Window 0 begins at 17773000g and runs through 17773776g. Window 1
begins at 17765000g and runs through 17765776g. The bootstrap PCR is located
at 17777520g. There are, however, the following important differences between
page mode and bootstrap.

1. The bootstrap windows and pages are 512 bytes long. In page mode, the
windows and pages are 2 kilobytes long.
2.

Bit 15 of the bootstrap PCR is not a control bit. The windows are always

open. In page mode, the windows are open only when bit 15isa 1.

3. The bootstrap PCR address is fixed at 17777520g. The page mode PCR
address is configured by the user between 17777000g and 17777036g.

SYSTEM DESCRIPTION

PAGE CONTROL REGISTER

1413121110

DEFAULT PCR

3
7777776
NN
\ 17777036

17777036
To 0 0 01 01| |o oo oo o 1]RPRRES IV
AW

)

WINDOW #1

Twinoow #0
17760000

PAGE 127

WINDOW
ENABLE

PAGE 126

*
*
*
L]

PAGE
7

PAGE
6

PaGEs

S TM
S

STARTING ADDRESS OF MODULE
ASSUMED TO BE 166500008

FIRST LOCATION OF WINDCW 0

BEGINS AT STARTING ADDRESS

OF MRV11-D.

PAGE 2
PAGE

~o_

PAGE5

16657776

#1
| WINDOW

__
16654000

16653776
#0
PAGE1 | WINDOW

18650000
_ _

(START ADDRESS}

‘L

PAGE 0

SYSTEM MEMORY

16K BY 8

ROMS ASSUMED

128 PAGES
OF CODE
MRV 11-D MEMORY
MA-0179-83

Figure 1-1

Page Mode Addressing

The bootstrap memory device must be physically installed in chip set 7. (See
Chapter 3.) The device may be any of the JEDEC standard pinout PROMs or
ROMs that meet the requirements listed in Chapter 3. The module must be proper-

ly configured to accept the devices.

The bootstrap program size is limited by the size of the memory devices installed.
A pair of 8K by 8 devices can contain a 16-kilobyte bootstrap program. Note, however, that like page mode addressing, only two 512-byte pages are available to the .
system at a time. The program must be specially written to turn its own pages. The
MXV11-B2 bootstrap PROM set is written this way and will function if installed and
properly configured on an MRV 11-D. (See Chapter 3.)
If the bootstrap program is smaller than 512 bytes, it can be written on one page,

avoiding the need to change pages. In this case, the program should be in the first
512 bytes of the bootstrap devices. Since the bootstrap PCR clears on power-up
and restart, both windows contain page 0 of the bootstrap devices.

SYSTEM DESCRIPTION

Nothing defines the last page of the bootstrap device. If a page number that is lar-

ger than the maximum page number for the bootstrap device is placed in the
bootstrap PCR, the device in chip set 7 responds with data from the page that is
given by the following formula.

(requested page number) modulo (pages on device) = actual page number
For example, a pair of 4K by 8 bootstrap devices contain 16 pages of bootstrap
program. An access to page 18 is actually an access to page 2.
18 modulo
16 = 2
Similarly, an access to page 34 or 50 using 4K by 8 bootstrap devices is an access
to page 2. With 8K by 8 bootstrap devices (32 pages), an access to page 33 is

actually an access to page 1 (33 modulo 32).

Figure 1-2 represents the bootstrap function. Window 1 holds the data from page
3. The page number (3 or 3g) is stored in the high byte of the PCR. Window 0 holds
the data from page 28. The page number (28 ¢r 34g) is stored in the low byte of the
PCR.

If the MRV11-D that contains the bootstrap is also used as a page mode module

on the system bus, the page mode PCR is in an undefined state after the bootstrap
operation. Initialize the page mode PCR before attempting to access the module.
NOTE:

When using the MRV11-D to bootstrap the RSX11-M operating system,

a line time clock register (17777546g) must exist on another module to ensure
proper operation.

1.5 PHYSICAL AND ENVIRONMENTAL SPECIFICATIONS

The MRV11-D is a class C module conforming to the specifications described in
the following paragraphs.

1.5.1

Physical Specifications

Height

13.17 cm (5.187 in), double

Width

1.27 cm (0.500 in), single

Length

22.70 cm'(8.940 in), bottom of

fingers to top of handle

SYSTEM DESCRIPTION

1/0 PAGE

2817 SYSTEM

PAGE CONTROL REGISTER

151413121110 9 8 7 68 5 4 3 2 1 0 BOOTSTRAP PCR

||ooooo11<%?o111oo]———(—-—’—.
ADDRESS

y -

,//
/

(NOT USED

PAGE 30

MODE)

pagE29 | ,',

ENABLE

17777520
(77376

)

WINDOW

17777716

WINDOW #0

WINDOW #?

(17777520

PAGE 28 | winDOW #0

17773000

/"7,

IN BOOTSTRAP

PAGE 28 | /

[]

.
PAGE 3

/ /
7

PAGE 3

17765776

| WINDOW #1
17765000

17760000

PAGE 2

PAGE 1

]

[ ]

SYSTEM MEMORY
PAGE
0

BOOTSTRAP

CHIP SET7
8K BY 8 ROMS

— 32
ASSUMED
PAGES OF 8OOTSTRAP CODE
MRV11-D MEMORY
MA-0172-83

Figure 1-2

1.5.2

Page Mode Bootstrap

Temperature

Storage temperature

—40°Ct066°C (—-40°Fto 151°F)

range

The module must stabilize at operating temperature for 5 minutes before
operation.

Operating temperature

5°Ct060°C (41°Fto 140°F)

range

Derate the maximum operating temperature by 1.¢°> C (3.24° F) for each 1000 m
(3280 ft) above sea level.

SYSTEM DESCRIPTION

1.5.3

Relative Humidity

Storage

10% to 95%
Maximum wet bulb temperature 32° C (90" F)
Minimum dew point 2° C (36° F)

Operating

10% to 95%
Maximum wet bulb temperature 32° C (90° F)
Minimum dew point 2° C (36° F)

1.5.4

Altitude

Storage

Upto 9.1 km (5.65 mi)

Operating

2.4 km (1.5 mi) maximum (paragraph 1.5.2)

1.5.5

Sea Level Operating Airflow

Operating temperature

0°Cto55°C(32°Fto131°F)

range

Adequate airflow must be pfovided to limit the temperature rise across the MRV11Dto10°C(18°F).

Operating temperature

55°Cto60°C (131°Fto 140°F)

range

Adequate airflow must be provided to limit the temperature rise across the MRV11Dto5°C(9°F).

1.5.6

Mechanical Shock

The packaged product shall withstand half-sine shock pulses of 40 g peak for a
duration of 30 = 10 ms.

1.6

ELECTRICAL SPECIFICATIONS

This section provides the electrical specifications for the MRV11-D.
1.6.1

Power

The following values are measured for an unpopulated MRV11-D. Add operating
current for each device irstalled. Note only one pair of devices operates at any
given time; the rest are in standby mode.

Voltage

Tolerance

Current

Pins

+5Vdc

+0.25V

1.6A

AA2, BA2, BV1

Battery Backup Installed

+5VB

+0.25V

280 mA

AV1

+5Vdc

+0.25V

1.3A

AA2, BA2, BV1

1.6.2

SYSTEM DESCRIPTION

Technology

Printed Circuit Board

Board type
Etch

Dual-sized, 4-layer board
0.012/0.013-inch technology

Electronics

Latest MSI (medium scale integration) and PAL (programmable array logic)
technologies
Software

Window mapping virtual addressing

FUNCTIONAL DESCRIPTION

2.1

INTRODUCTION

This chapter describes the functional operation of the MRV11-D universal PROM
module. The description divides operation into direct mode, page mode, and
bootstrap mode.
For purposes of explanation. the discussion refers to a 22-bit Q-bus system. The

bus master asserts a 22-bit address on the Q-bus and then asserts the SYNC line
to gain control of the bus. The address Is latched into the MRV11-D by the bus

interface. Decoding begins as soon as the address stabilizes rather thar a1 the
assertion of the SYNC line.

2.2

DIRECT MODE

Direct mode addressing ts implemented by configuring the PAGE/DIR switch as
DIR. Figure 2-1 is a block diagram showing the address decoding for direct mode.

PAN

ADDRESS
£
22

DATA/

BUS

INTERFACE

DATA

/16

BUS ADDRESS 0-11

BUS ADDRESS

BITS 1218

BITS 0-11

12-21
NORMALIZER

START

PAGE

BITS 1215

DIRECT

ADDRESS 12:21
19,20.2° .
(ouT OFi
RANGE !

DRIVE DATA

ONTO BUS (READ)

SYNC

READ/WRITE

—

PR
I
—
ARRAY
3708

loecooen

DECODER
LINE

CHIP
SELECT
,
7

MEMORY
ARRAY

ACCESS

CIRCUITRY

VALID

ACCESS

BUS
CONTROL

PAGE/DIR

ARRAY

TIMING

WTBT

INTERFACE]

4,
£

O
BITS

22-BIT Q-BUS

,7
4

ACCESS

DETECTOR

g5 gANK SEL 7 (BBS7)

LINES

*BUS ADDRESS GREATER THAN
START ADDRESS PLUS 256K WORDS

(MAXIMUM MRV 11-D CAPACITY)
BITS120R200R 21 =1
MA-0171.83

Figure 2-1

Direct Mode Block Diagram
11

FUNCTIONAL DESCRIPTION

The bus interface biocks receive address and control signals from the Q-bus and
latch the address when the bus master asserts SYNC. If the bus address corresponds to an address configured for the MRV11-D, then the module responds to
the access per the Q-bus protocol. If not, the module does not respond and does
not transmit information on the bus.

The range of the MRV11-D is determined by the starting address (lower boundary)
ard the decoder PROM (upper boundary). The normalized address (bus address
minus starting address) measures the distance between the bus address and start

address. If this number is negative, the bus address is below the lower boundary of
the module. If the number is positive, but greater than the configured capacity, the
bus address is beyond the module’s range. The module responds only when the
bus address is greater than the module starting address and less than the configured array size.

Bits 0 through 11 of the bus address are directly mapped to bits O through 11 of the
memory array address. Bits 12 through 18 from the normalizer are applied to the

direct input of the PAGE/DIR multiplexer, which is set to DIR. These bits are then
a| plied to the array decoder, which determines chip select and out-of-range condition. Additional out-of-range conditions occur if either bits 19, 20, 21, or any combination are asserted. If this happens, the access detector does not issue a valid

access signal to the timing circuit and the RPLY signal is blocked.
If the bus address is within range of the module, the access detector issues a valid
access signal, which causes RPLY to be asserted on the bus. if a read cycle was
initiated, the timing circuit drives the data onto the bus. If a write cycle was initiated,
the module accepts data from the bus.

If bits 12 through 21 are all 1s, BUS BANK SELECT 7 (BBS7) is asserted to indicate that the access is not to the memory array but to the /O page. Accesses to the
PCR, bootstrap PCR (BPCR), and bootstrap areas are through the 1/O page.
Note that bits 0 through 11 of the bus address are directly applied to the memory
array and bits 12 through 21 of the bus address are applied to the normalizer with

bits 12 through 21 from the starting address switches. The starting address set in
the switches is subtracted from the bus address (Figure 2-2). This operation estab-

lishes the starting address as the lower boundary of the array. Normalized bits 12
through 15 are applied directly to the memory array to be decoded by array devic-

es larger than 2K by 8. Bits 12 through 15 are also applied to the array decoder
along with bits 16 through 18. Bits 12 through 18 perform different functions,

depending on the size of the memories, number of memories utilized in the array,
and the configuration.
For example, with a fully populated array of 2K by 8 PROMs, bits O through 11

define a particular byte within each 4 kilobyte boundary. Bits 12, 13, and 14 determine the chip set socket selected while bits 15 through 18 are used as out-of-range
bits (Figure 2-3). If any of these bits are asserted, the address is above the upper

boundary.

FUNCTIONAL DESCRIPTION

BUS ADDRESS

(12-21)

BUS ADDRESS

XX X XX X X X X X

MINUS

22.8IT Q-BUS
—

START ADDRESS
(12:21)

[

X,
X X

“

RESULT
(NDODRRMEA;IZED

ADDRESS)

DIRECT

OUT OF RANGE
BITS (19,20,21)

MAPPING

{BiTS

12-18

BITS

DECODING"

1215

‘15

1211

*USED TO DETERMINE

MEMORY

CHIP SELECT AND OUT
OF

ARRAY ADDRESS

RANGE CONDITIONS

MA-0167-83

Figure 2-2

Direct Mode Addressing

ARRAY DECODER
PATTERN

I BYTE

LOGICAL

3-10-8

EQUIVALENT

LINE DECODER { cse

12—

— —

M ——————

CSs
£s4

CS6

cs7

°
:
cs4

—&

15 —

[e]

16 —

CS2

18 —

CS1

cso

17—

L0 BYTE
cs6

cs7

°
cs4

cs5

CS2

CS3

Cs2

cs1
®

CcSo

CS*S

CS1

°
CHIP SET SOCKETS*

OUT OF ARRAY RANGE
OUT OF RANGE

PATTERN | 1 2]
FROM

SELECT

SWITCHES

PATTERN

FROM

NORMALIZERY

BIT ;g
BIT

BIT 21

2K BY 8 PROMS FULLY POPULATED

*DOTS ARE CONNECTIONS TO CHIP SET SOCKETS.
MA-0174-83

Figure 2-3

Chip Select and Out-of-Range Functions (Direct Mode)

FUNCTIONAL DESCRIPTION

Bits 19, 20, or 21 from the normalizer determine an out-of-range condition where
the maximum capacity of the MRV11-D has been exceeded. Bits 15 through 18

are applied to the array decoder to determine an unselected condition when a chjp
set socket is configured for no device, or when a small array’s capacity has been
exceeded. Bits 19 through 21 and bits 15 through 18 are combined to determine an
out-of-range condition when either of the above described situations occur.

A pair of 2K by 8 PROMs look at 12 address bits (0 through 11) to specify one byte
in a 4-kilobyte block. Therefore, the next three bits (12, 13, 14) are used by the
array decoder to select the desired pair of devices. This is accomplished by programming the array decoder for the desired configuration.

The standard array decoder has four selectable patterns as described in Chapter
1. Select these patterns with the pattern select jumpers as shown below.
Pattern Select

Device

Jumpers

2K by 8 PROMs, half-populated

2K by 8 PROMs, fully populated

4K by 8 PROMs, fully populated

8K by 8 PROMs, fully populated

if 4K by 8 PROMs are used instead of the 2K by 8 PROMs, 13 address bits (0
through 12) are required by the devices. In the fully populated case, bits 13, 14,
and 15 determine the chip set sockets where the devices are to be inserted and
bits 16, 17, and 18 are out-of-range bits. Similarly, for 8K by 8 PROMs, 14 address

bits (0 through 13) are required. Consequently, bits 14, 15, and 16 determine the

chip set socket where each device is to be inserted and bits 17 and 18 are out-ofrange bits.

2.3

PAGEMODE

For page mode operation, the PAGE/DIR switch must be configured in the PAGE

position. The page number is stored in the PCR during a previous bus cycle. This

page number supplies the more significant address bits of the array address. For
all window accesses, bit 15 of the PCR must be set to open the window areas.
Figure 2-4 is a functional block diagram showing the page mode data paths.

Bits 0 through 10 of the bus address are directly mapped to bits 0 through 10 of the
memory array address. Bit 11 of the bus address marks the boundary between
window 0 and window 1 of the bus. If bit 11 equals 1, the page of code in window 1

is accessed. If bit 11 equals 0, the page of code in window O is accessed.
The starting address is subtracted from the bus address in the normalizer block
and the result is checked against the upper boundary. (In page mode, the upper

boundary equals the starting address plus 4 kilobytes.) If any combination of normalized bits 12 through 21 are asserted, the address is greater than the upper
boundary of the module — out of its range. In this instance, the access detector gets
an out-of-range signal and never issues a valid access signal to the timing chain.
Conseguently, the MRV11-D ignores that bus cycle.

FUNCTIONAL DESCRIPTION

22/

',
BUS ADDRESS 0-10>

BUS ADDRESS 0-10
‘

ADDRESS ,

16,

DATA

DATA |,

T
PCRDATA

BUS ADDRESS
BUS
INTERFACE {1221

NORMALIZER

START

ADDRESS ——sf

@
>

RANGE

CHAIN

[ winoow #1 ]

ADDRESS
BITS 12:21*
oUT OF

TIMING

READ/MWRITE
REPLY

15 14

BUS

DRIVE DATA ONTO
BUS (READ)

]

PAGE CONTROL REGISTER
WINDOW ENABLE

[

12-21

T winoow #o |

ARRAY

BUS

ADDRESS

MEMORY

)

BIT 11=1
WINDOW #1
BIT 11=0,

WINDOW SELECT,

WINDOW #0

PAGE/
IR

PAGE \/DIRECT

SET TO

MODE SELECT

PAGE

BUS

VALID

ACCESS

INTERFACE

WTBT

BUS BANK SEL7
(BBS7)

WINDOW
ENABLE

ACCESS

DETECTOR

CONTROL
LINES

ARRAY

ACCESS

PCR 11-15

PCR 12-17

|
ARRAY DECODER

3-TO-8

LINE

DECODER

*IF ANY OF BUS ADDRESS

BITS 12:21 GO TO 1, OUT OF

CHIP

RANGE CONDITION OCCURS

SELECT
MA.0178 83

Figure 2-4

Page Mode Block Diagram

The page numbers in the PCR are multiplexed and controlled by bus address bit

11. Therefore, the appropriate page number for the accessed window is used to
construct the memory array address. This address is applied to the array and array

decoder as in the direct mode example. Note that the PCR window contains 7 bits
and these bits replace normalized bits 11 through 17. These bits are used by the
array decoder for chip select decoding and/or out-of-range conditions.

For a half-populated array of 2K by 8 PROMSs, the PROM sets look at 12 address
bits (bits O through 11) because this pattern specifies 4 kilobytes for each set. The
next two bits (12 and 13) are used by the array decoder to select one of the four

chip sets. This is accomplished by setting the pattern select jumpers for the
installed device configuration as shown below.
Pattern Select

Device

Jumpers

2K by 8 PROMs, half-populated

2K by 8 PROMs, fully populated

4K by 8 PROMs, fully populated

8K by 8 PROMs, fully populated

FUNCTIONAL DESCRIPTION

If a fully populated array of 2K by 8 PROMs is used instead of the half-populated

2K by 8 PROMSs, 12 address bits (0 through 11) are required (Figure 2-3). In this
case then, bits 12, 13, and 14 determine the chip set socket where each device

pair is inserted and bits 15 through 18 are out-of-range bits. Similarly, for 4K by 8
PROMs, 13 address bits (0 through 12) are required. Bits 13, 14, and 15 determine
the chip set socket where each device is to be inserted and bits 16 through 18 are

out-of-range bits. For 8K by 8 PROMs, 14 address bits (bits O through 13) are

required. Bits 14, 15, and 16 are chip select bits and bits 17 and 18 are out-ofrange bits.

The array address is derived as follows (Figure 2-4). Bus address bits 0 through 10
are directly mapped to memory array address bits 0 through 10. Bus address bit 11

chooses the byte of the PCR that serves as array address bits 11 through 17. The
low byte contains the page number for window 0 (bit 7 is unused). The high byte

contains the page number for window 1 (bit 15 is a window enable bit). Since a
page mode address is limited to 18 bits, the page mode array capacity is limited to
256 kilobytes. Bus address bits 12 through 21 are used solely to determine that the

access is between the base of window 0 (starting address) and the top of window 1
(starting address plus 4 kilobytes).
Bits 11 through 17 of the memory array address are supplied from the PCR (PCR
bits 0 through 6 for window 0 or PCR bits 8 through 14 for window 1). As previously

mentioned, bits 11 through 17 perform different functions depending on the PROM
devices used and the number of PROMs installed.
Bits 12 through 21 from the normalizer determine an out-of-range condition (4

kilobytes greater than starting address) where the range of the MRV11-D memory

array has been exceeded. Bits 15 through 18 applied to the array decoder determine an out-of-range condition when a chip set socket with no device configured

has been addressed or the page limit has been exceeded. Bits 12 through 21 from
the normalizer -and bits 15 through 18 from the array decoder are combined to

detect an out-of-range condition if either of the above described situations-occur.
2.4

BOOTSTRAP MODE

Figure 2-5 is a functional block diagram of the MRV11-D in bootstrap mode. Bus
address bits 0 through 8 are directly mapped to memory array address bits 0

through 8 to define one byte within each 512-byte boundary. Bus address bits 9
through 21 must be either 17773g or 17765g for a valid bootstrap access. As a
result of bits 13 through 21 being asserted, BBS7 is also asserted to indicate an I/O
page access. Bits 9 through 12 are decoded as follows.
21-15
All1s

14 13 12
1

177

10 9

876

543

210

876

543

210

21-15
All1s
177

14 13 12
1

1
6

"11-10
9
1

01
5

FUNCTIONAL DESCRIPTION

16,

DATA 16

DATA

BUS ADDRESS 08

BUS

INTERFACE

PCR DATA

16|

ADDRESS

716
BUS ADDRESS

PAGE CONTROL REGISTER
{17777520)

912,
72

15 14

[
DRIVE DATA
ONTO BUS (READ)

2
w

READ)

| winoow o |

cHip

ADDRESS
BIT 11

LWAYS

[ wnoow 1 [

BUS

READ/WRITE

WINDOW

SELECT

TIMING

CHAIN

ARRAY ADDRESS 9-1?/

SYNC

NEPLY

BUS
CONTROL | INTERFACE

17773XXX OR

]

vauo || 177eex

ACCESS

LINES

BUS BANK SEL 7

(BBS7)

(ALWAYS OBI)

L
ACCESS

CHIP SELECT

DETECTOR

WTBT

MA-0180-83

Figure 2-5

Bootstrap Mode Biock Diagram

The state of bit 11 chooses the byte of the bootstrap PCR that serves as array

address bits 9 through 15. The 17773XXX represents an access to window 0

(BPCR low byte). The 17765XXX represents an access to window 1 (BPCR high
byte). The bootstrap PCR is located at 17777520g.

’

If an I/0O address other than the above addresses is detected, the MRV11-D does
not respond.

In bootstrap mode, chip select 7 is always asserted during a bootstrap access.
Consequently, the bootstrap code must always reside in chip set 7.

Figure 2-6 shows how the bus address is mapped for the bootstrap using window 0
(location 17773270g, page 3). Bits 0 through 8 of the bus address map directly to
memory array address bits 0 through 8. Bits 12 through 9 of the bus address are

respectively decoded as 1011. When bit 11 equals 0, the low byte of the PCR is
appended to bits 0 through 8 to form the memory array address. The state of bus
address bits 9 through 21 (all asserted) indicate an access to the bootstrap area in
the I/0 page.

The page number, loaded in bits 0 through 6 of the PCR, is mapped into bits 9
through 15 of the memory array address. Chip select 7 is always asserted on

bootstrap access, so the array address (3270g) is applied to the PROMs in chip set
7.

FUNCTIONAL DESCRIPTION

BUS
ADDRESS

9 8 7 6
18
17 16151413 121110
212019

L] LD

]

DECODED

(BBS7)

270g

IF BBS7 =1

IF BIT 11 =0,

IT IS 1/0

WINDOW #0 ACCESS

PAGE ACCESS

BUS BANK

SELECT 7

s
o] Joolo]
e[ [e]ofs[o

—

4
5

ITIS

AND BITS 0 THRU 6

AND BITS 13

OF PCR ARE LOADED
INTO BITS 9 THRU 15

THRU 21 ARE
1'S.

OF MEMORY ARRAY
ADDRESS.

PAGE CONTROL REGISTER (17777520g)
WINDOW #1

15 14 13

LT
EXAMPLE ASSUMES:

WINDOW #0

—

T T Tolofololol
]

PAGE 3
WINDOW #0

MEMORY

)

ACCESS IS TO /O

ARRAY

PAGE (BBS7 =1,

[l o [ [Tl T tJo]o[o]
[T

BITS 13-21 =1}

1110

ACCESS IS TO
BOOTSTRAP AREA

IN 1/0 PAGE AS
DECODED

BITS

270g

212019 18 17 16 15 14 1312 1110
e

ADDRESS

3'2

e
]

9-12
3

LOCATION 270
IN PAGE

3 OF

WINDOW #0

22-BIT Q-BUS

X = DON'T CARE

Figure 2-6

MA.0166-82

Bootstrap Access to Window 0 (/O Page)

Figure 2-7 shows a bootstrap access to window 1, location 17765432g. Bits 0

through 8 of the bus address map directly to memory array address bits O through
8. Bits 12 through 9 of the bus address are respectively decoded as 0101 with bit
11 equal to 1. Stnce bit 11 equals 1, the page number for window 1 is selected from
the PCR. BBS7 is asserted since bits 13 through 21 are all asserted, indicating an
access to the /0 page.

To address the /O page, BBS7 and bus address bits 13 through 21 must be
asserted.

The page address (34g) in window 1 of the PCR is mapped into bits 9 through 15 of

the memory array address. The address 34432g is applied to chip set 7.

FUNCTIONAL DESCRIPTION

BUS

ADDRESS

2120

19 18

1514 13

Ll
1

121110

ol ol folofofs oo o]
7

—/

432¢

BUS BANK
SELECT 7

DECODED|o

(BBS7)

IF BBS7 = 1,

IT 1S 1/0 PAGE

IF BIT 11 =1,1T

ACCESS AND BITS

13 THRU 21 ARE

IS WINDOW #1 ACCESS,
1'S.

AND BITS 8 THRU 14
OF PCR ARE

LOADED

INTO BITS 8 THRU

OF MEMORY ARRAY
ADDRESS.

PAGE CONTROL REGISTER (17777520g)
EXAMPLE ASSUMES:

ACCESS IS TO 1/0
PAGE (BBS7
= 1 &

WINDOW #1

4131211109

WINDOW #0

8 7%

0°

ors e 2= | Jolof o[ [ Jolo] [ ] ][] ] Johsans

ACCESS IS TO

BOOTSTRAP AREA
IN 1/0 PAGE AS
DECODED BY BITS

9 THRU 12
3

LOCATION 432

IN PAGE 28 OF

MEMORY

WINDOW #1

-BIT Q-BUS
X = DON'T CARE

]

ARRAY
ADDRESS

—

432g

CDDDELl
o T ool T Lo [Tl [To[
o]
2019 1817 161514 13121110 ¢ 8
e — N
e
0

2
MA-0170-83

Figure 2-7

Bootstrap Access to Window 1 (/0 Page)

JUMPER CONFIGURATIONS

3.1

INTRODUCTION

This chapter describes how to configure the MRV 11-D to function properly for your

application. Configuration is accomplished by setting a bank of PCR switches, setting a bank of starting address switches, and connecting a series of jumper posts.

The required jumper posts are connected by means of jumper clips designated as
W3 through W16. These jumper clips allow two adjacent jumper posts to be connected. Nonfunctional holder posts are provided in many jumper groups to avoid

the loss of jumper clips when not used. There are 16 memory sockets on the module that house 8 possible chip sets. (Each chip set has a high byte device and a low

byte device.) This arrangement is shown in Figure 3-1.

}'—LO BYTE—-‘ }'—HI BYTE—-|

—

[

MA-0197-83

Figure 3-1

MRV11-D Chip Set Locations
-

JUMPER CONFIGURATIONS

3.2

CONFIGURATION

To configure the MRV 11-D properly for a specific application, use the flowchart in

Fiéure 3-2. The tables referenced in this figure provide additional information on

the jumper and switch selections.

Figure -3-3 shows the location of the jumpers and switches on the module. The
figure contains a reference to a table for each jumper and switch bank. Refer to the
appropriate table to determine the actual jumper connections or switch settings.
For example, Figure 3-3 shows the location of the DATO jumper and references
Table 3-4. Table 3-4 shows the actual jumper posts and describes the possibie
connections.

NOTE: The MRV11-D can be remotely enabled and disabled by asserting the
spare bus signal SSPARE3 (bus pin AN1). This signal is not bussed in Digital
backplanes, but may be connected in other backplanes supplied by other
manufacturers.

3.2.1

Installing MXV11-B2 ROM on MRV11-D

Perform the following steps to install an MXV11-B2 PROM set on the MRV11-D.
1. Enable the bootstrap function (Table 3-8).

2. Setthe row 4 jumper (power jumper) for an 8K by 8 device (Tabie 3-6).
3. Set the device size jumper to 8K by 8 (Table 3-5).
NOTES:

MXV11-B2 bootstrap ROMs cannot be used if the device size jumper

is set for 2K by 8 or if the power jumper connection for row 4 is set for 16K by 8 or
32K by 8 devices.

For additional information on the MXV11-B2 ROM, refer to the MXV11-B2 ROM
Set User Guide (EK-MXVB2-UG).

JUMPER CONFIGURATIONS

YES

TABLE 3-1

FAWE RY BACKUP J
lr

r SYSTEM SIZE
v

[ ROM/RAM SELECT

J
|

TABLE 3-2

TABLE 3-3

rDATO RESPOND ] TABLE 3-4

|
r

'
SELECT MEMORIES

DEVICE SIZE
JUMPERS

l
[

TABLE 35

POWER:

I TABLE 36

READ TIMING
JUMPER

J TABLE 3 7

INSTALL CHIP

]

JUMPERS

I SET 7
[

enaBLE BOOT

DISABLE

BOOT

TABLE 38
E

| TABLE 38

MA-0168-83

Figure 3-2

Jumper Configuration Flowchart (Part 1)

JUMPER CONFIGURATIONS

BOOTSTRAP AND

MEMORY OR
MEMORY ONLY

STARTING
ADDRESS =

——» ] NO

17770000

STD.

‘

PATTERN
?

TABLE 3-10

BOARD WILL RESPOND
TO BOOTSTRAP AND
BOOTSTRAP PCR,

ONLY.

SET ADDRESS

MODE TO

TABLE 3-11

DIRECT

STD. DECODER

PATTERN SELECT

|TABLE 39

END

JUMPERS

SEE

CHAPTER §

PROGRAM
NEW

DECODER

MGOLe

TABLE 3-10

’

1
ADDRESS
J

DIRECT

TABLE 3-11

STARTING
ADDRESE

Figure 3-2

Jumper Configuration Flowchart (Part 2)

TABLE E 3 3-10

JU MPER CONFIGURATIONS

POWER JUMPERS

{

(TABLE 3-6)

—|

]

ADDRESS MODE &

~— PCR ADDRESS SWITCHES
(TABLE 3-10)
o~

ENABLE BOOTSTRAP JUMPER

ROM/RAM

SELECTION

(TABLE 3-3)

— DEVICE SIZE JUMPERS

JUMPERS

(TABLE 3-8)

(TABLE 35)

STANDARD DECODER
—~ PATTERN SELECT

mn
gl|e

L
1

—_

MmN

L
bl
o~
w

SYSTEM SIZE JUMPER

(TABLE 3-2)

——

XE36

XE38

XE37

XE39

JUMPERS (TABLE 3-9}

—J

| STARTING ADDRESS
SWITCHES (TABLE 3-11)

o~
w

| BATTERY BACKUP READ TIMING

JUMPER (TABLE 3-7) [|

SHUNT (TABLE 3-1}

['%

I~ DATO JUMPER
{TABLE 3-4)

MA.0277N.82

Figure 3-3

Jumper and Switch Locations

JUMPER CONFIGURATIONS

£y

[ ¢

JUMPER CONFIGURATIONS

- 27

JUMPER CONFIGURATIONS

ROM/RAM Selection Jumpers (W4, W5)

Table 3-3

HIBYTE

‘I

ROM/RAM

SELECTION

[

xess | xeso 0 xeae!|

JUMPERS
XE44

1O BYTE
B2 —0)

Lt —o

Jap——)

HUBYTE

Q
WS[1y

~rny

J3s

O 436

LOBYTE

| |4

JUMPER CONFIGURATIONS

REV.C AND REVD ETCH CONFIGUR,
. THE TABLE BELOW REFLECTS:THE
SIDE OF THE.
ON THE COMPONENT
BOARD NUMBER IS LOCATED

| BO1S213C=REVCETCH .
50152130
= REV. D.ETCH

JUMPER CONFIGURATIONS

{

Power Jumper Connections (W9, W10, W11, W12)

—
N
o

N
"

o~
TM

xes9 | xest |[H] m'
4

5 N

3
-

| xea3

bl I

'
xeat

xe45. | xEa7 |—
2-t

|| .

sSiis

L L
0

=)
w

1IN

Xe | xess {||\ ) E‘E
N

il 3E
u’J

OR2K:BY 8 AND 4K BY'8 ROMS
EPOWER JUMPER MAY BE IN
THE 8K:BY 8:ROM: THE POSITION
‘0PN 26. THE.CONFIGURING
y
1S. ‘FOR EXAMPLE, IF 4K BY
54,2,
3:AND 16K -BY 8-ROMS

DEVICES, THE POWER JUMPER MUST
H(S POSITION,
PIN 2615 CONNECTED

JUMPER CONFIGURATIONS

3.3

PROM SIZES AND PINOUTS

The MRV11-D contains sixteen 28-pin sockets to house the various PROMs and
static RAM devices that can be used in the modute. The sockets can house 2K by
8, 4K by 8, 8K by 8, 16K by 8, and 32K by 8 PROMs. In addition, the bottom half of
the socket array (chip sets 0 through 3) can accommodate static RAM. The 2K by 8
and 4K by 8 PROMSs contain 24 pins while the others contain 28 pins.

Figure 3-4 shows the pin assignments for the 24- and 28-pin memories using the

JEDEC standard pinout. The 2K by 8 PROM is represented by the 2716 and the
4K by.8 PROM is represented by the 2732. The other PROM types (8K by 8, 16K

by 8, and 32K by 8) are represented by the 2764, 27128, and 27256 respectively.
The 8K by 8 static RAM is also shown. The basic differences on the 2764, 27128,
27256, and static RAM are in the functions of pins 26 and/or 27. Figure 3-4 shows

these differences. For example, on the 16K by 8 PROM (27128), pin 26 is used as
an address pin (A13). On the 32K by 8 PROM (27256), pins 26 and 27 are used as
address pins (A13 and A14, respectively).

INTEL 2764 PIN CONFIGURATION
8K BY 8 PROM

INTEL 2716 PIN CONFIGURATION

INTEL 2732A PIN CONFIGURATION

2K BY 8 PROM

4K BY 8 PROM

O B 24{] Ve,

Voo

VCC

ab2

26[JNC

~/ 2a[V,.

A,0s

23[JA,

Agl]2

23[JAs

25/ J A

22[]

As[]3

22[)As

24{JA,

21{ ] Vee

21JA

23[JA

A.Os

20[}

O€

As]s

20115E

22308

[Os.

A ¢

Aq[)e

19[JA

21JA

18[]CE

18]

JCE

2000

[l8

1730,

Aolls

17130,

19110+

18[J0

170105

[

18[]0,

0,9

16]]0

1510,

15{]0,

14{30,

14070,

0,013

GND[12

13(7]0s

GND[J12

13130,

GND[14

27128 PIN CONFIGURATION

27256 PIN CONFIGURATION

16K BY 8 PROM

32K BY 8 PROM

—\_

~ 283 V..

[O12

16[J0

¢CE
6
«

15[305

STATIC RAM

Vee 1

28[J V..

vee

A2
A3

27[]
PGM
261 3 A1a

A2
A3

270
26[]

Asl

Asl]4

25[ | Ag

As{

[]s

241]

As[Cls

24[]

23[JA

Ava
A

Ve[ 1 A 28] Vec
ALL2
A,[3

J Ag

As[]5

247

A.Ll6

23 JA 1

ALLl6

23[0A

A.Lj6

AsL7
A8

22[30€E

211JA

AL[07

2270

1
22(10E

20[JCE

2003

201]CE

Ao[o
0.

19(70,
18006

A0
0[]

191]0
18[00

AofJ10
0,1

180+
180306

0,12
o, O3
GND[]14

171105
16{J0
.
15303

0,02
o,
GNpd14

17|30
16{J0
4
15[30
s

o,0rn
0,03
GNo[Q14

171305
16{104
15[]05

2101A

270
WE
26{ ] CE,OR N.C.

ALLC8

25{ ] Ag

210A

MA-0203-83

Figure 3-4

PROM Sizes and Types

JUMPER CONFIGURATIONS

When installing a 24-pin PROM (2K by 8, 4K by 8) in a 28-pin socket, install it with

the notch on top and bottom justified. Pin 1 of the PROM inserts into pin 3 of the
socket (Figure 3-5). On 28-pin devices, pin 28 is the power.pin. For 24-pin devices,

pin 28 of the socket must be strapped to pin 26 of the socket to provide power to
the device. The power jumpers strap these pins together (Table 3-6).
NOTE:

If you are using 24-pin devices such as the 2716 (2K by 8 PROM) on a

revision C etch board, you must wirewrap J13 (Vpp) to J40 (pin 26 of row 4). Itis

also necessary to jumper J40 to J41 (+ 5 V). However, you cannot use the jumper
clip because a wirewrap exists on J40. Therefore, you must wirewrap, rather than
jumper, J40 to J41. This procedure ensures proper read mode operation (Table

3-5). On a revision D etch board, you can install 2K by 8 PROMs without wirewrap
(Table 3-5).

oO~NOoOT
R WN -

©O

L WN =

28 PIN PROM SOCKET

24 PIN
PROM
CHIP

MA.0307-82

Figure 3-5

Insertion of 24-Pin PROM Chips

PROGRAMMING

4.1

INTRODUCTION

The window-mapped mode can be used in two ways in LSI-11 application programs. One way is to code the application program to execute directly from the

windows. The other is to use the window-mapped board to transfer a standalone
application program from ROM into RAM memory at system start-up. This chapter
provides an example of each type.

4.2

EXECUTING WINDOWED PROGRAMS

Executing directly from MRV11-D windows allows large programs of up to 56

kilobytes of RAM on LSI-11/2 systems. However, software executed in this mode
musti be specially designed and written in assembly language.
An application designed for window mode execution must have a mechanism for
calling a subroutine or transferring control to another routine that is in a presently

unmapped section of the windowed ROM board. You must use a technique different from the standard JSR or JMP instructions. This technique is illustated in
Figure 4-1.

The routine that processes subroutine calls and jumps to other pages must, of
course, be in a section of memory that is not window mapped. To call a subroutine
using these capabilities, write CALLWO /abel instead of JSR PC /abel.
CALLWO /abe/ causes the desired subroutine to map into window 0. It also causes

the call to execute. Upon subroutine return, which is done with a normal RTS PC
instruction, the original mapping is restored and controi returns to the calling program. To invoke a subroutine and have it mapped in window 1, write

CALLW1 Jabel.

Note that the mechanism shown in Figure 4-1 preserves condition codes from the
called routine back to the calier. That is, routines can return status in the condition
codes. Instead of the unconditional jump instruction, write JMPWO /abelto jump to

a routine, and map it into window 0. Write JMPW1 /abel to transfer control to a
routing that should be mapped into window 1.

PROGRAMMING

IS RELATIWE TO BEGINNING OF MRY11-D

5ADRS

WOBASE = 1500003<<STARTING ADDRESS OF MRY11-D
W1BASE.= 134000
JMPW

JSRW

MRYPCR

177000

+MACRO

CALLWO

TRAP

JSRW

+WORD

WOBASE

+ENDM

CALLWOD

ADRS

WO
+

+MACRO

JMPWO

ADRS

TRAP
+WORD

JMPW +
WOBASE

+ENDM

JMPUWO

+MACRO

CALLW1

ADRS

JSRW

+WORD

W1BASE

+ENDM

JMPH1

+MACRO

JMPW1

TRAP

JMPW

+WORD

W1BASE

+ENDM

JMP W1

TRPHAN

7743

774%

3777%

<<ADRS/1000:

<ADRS

TRAP

<<ADRS/1000x

<ADRS

3777

<<ADDRS/1000x
<ADRS

774%

3777:

ADRS
+

W1
+

<<ADRS/1000:

<ADRS

774>

3777:

MOV

@#MRVCSR
- (5P}

tSave

Pprevious

TST
MOy
MOY

-(8P)
RO, -(SP)
B (SP)s RO

iReserve srace
jSauve caller’s
iAnd set RO to

ADD
MOV

#2, G(5P)
(RO)s Z2(SP)

MOV
BIC

- (RO)y RO
#177600, RO

ASR
ROR

RO
RO

MOV

#MRVYPCR:

for adrs
redister
address of

ITRAP

marPing

iUpdate return PC bevond
tMoue adrs (follows TRAP

adrs

sinstructions)

iRO TRAP
iExtract

instruction itself
pade #,3 window #

s JMP/ JSR

iMoue JUMP/JSR
sPlace window
iSet

gddress

imaPp

bits

iAnd
iMae

new

window

ADC
MOWB

@SP
ROy

BIS

#100000,@(5P)+

ftEnable

rROL

sJMP/JSR

back

MOV

(SPY+,

iRestore

caller’s

sIf

branch

BR(SP)

bit
C»

kit

§JUMP/JSR

-(SP)

to C
# in

update based on window
Pade in selected

iwindow

BCS

JSR

PC»

MFPS

4(SP)

B(SP)+

Moy

(SP)+4@#MRUPCR

returned

old

C
to

bit
register
1%

desired

routine

condition

iRestore

original

5And

return

sand

adrs

after

MOV

(SP)+,

BESP.

iIf

JMPs

mouve

(5P)+,

BSP

iUr

over

old

iAnd

RTI

Figure 4-1

JSK

iStore

RTI

JMPs

iElse
iin

windouws

JSR and JMP Control Routines for Window Mapping

maPping
TRAP

adrs
(caller‘s)

new

location

codes

PROGRAMMING

To use this mechanism, the program should be assembled with .ENABL AMA to

force absolute addressing in the assembly. At start-up, a bootstrap routine must be:
executed from the MRV11-D bootstrap window or elsewhere. This routine copies
the trap handler routine to RAM memory, if necessary. It initializes the trap vector
to contain the address of the trap handling routine and a new status word of all Os.

With this type of application, take care not to cross page boundaries without
remapping to the next page. If you encounter a page boundary, use the JMPWO or
JMPW!1 pseudo instructions to move to the beginning of the next page.
4.3

TRANSFERRING APPLICATION PROGRAMS FROM ROM TO RAM

In window-mapped mode, the MRV11-D can also be used as a low-cost, program
load device for standalone applications. This use allows application programs that
cannot be easily segmented into ROM and RAM sections to be loaded from a
ROM environment into RAM for execution. To use the MRV11-D in this mode, -

write a bootstrap loader program to copy the contents of the ROM board into the
RAM area at power-up. Figure 4-2 demonstrates such a program. The program is
designed to load standalone images created by the RT-11 LINK utility. It is also

possible to load an RSX-11S system image from one or more MRV11-D boards
into RAM for execution.

MRVPCR

MRVWIN

ONEKW

LLOADER:

177000

130000

003777

MOV

#100000,E#MRVPCR

jEnable

mar

low

MOV

E#MRUWIN+S0,

SRS=RT=-11

SAY

file

high

MOy
Moy
CHMP

#MRUWIN, R3
(R3)+ (Rd)+
R4y RS

iReset to base
iCopy ane word
iMoved highest

BHIS

yIf

BIT

#0ONEKW:

BNE

iIf

INC
BR

@#MRVYPCR
1%

jElse map next 1K in window
tAnd caowntinue copPvying

Moy

@#40,

iStart

CLR

1%
2%

}Start

copving

HISy

iHave

user’‘s

Bodtstrap Loader for Standalone Programs in RT-11
SAV Format

of first window
into RAM
word in Prodram?
1

bouandary?

Figure 4-2

limit

location O

ves

reached

NE»

into

words

transfer

address

PROGRAMMING THE
ARRAY DECODER

5.1

INTRODUCTION

This chapter is for users who want specific applications on the MRV11-D. As previously specified, the module is shipped with a standard array decoder supplied by
Digital. It provides four predefined patterns.

2K by 8 PROMSs, half-populated
2K by 8 PROMSs, fully populated

4K by 8 PROMSs, fully populated

8K by 8 PROMSs, fully populated
Users whose needs are satisfied by this configuration may omit this chapter with

no loss of continuity.
5.2

DECODER PROGRAMMING HARDWARE

Programming the array decoder requires specific hardware. The basic hardware is
the model 19 or mode! 29 programmer from the Data I/O Corporation or the PB11

PROM programming option for the LSI-11 from Digital. Table 5-1 lists the 512 by 4
array decoders, vendors, card sets/socket adapters, and UniPak fixtures. Either
the card set and adapter or the UniPak fixture are required in addition to the basic

hardware.

PROGRAMMING THE ARRAY DECODER

A brief description of each coiumn in Table 5-1 foliows.

Vendor's part number of the PROM

512 by 4
Array Decoder
Part Number

PROM

Manufacturer of the PROM

Vendor

Card Set

Programming card set from the Data I/O
Corporation that is used to program the PROM

Rev.

Required revision of the card set

Socket Adapter

Part number of socket adapter used with the
card set

UniPak Revision

The UniPak fixture plugs into Data I/O
Corporation’s programmer in place of the card
set. The programmer and UniPak can program

MOS and bipolar PROMs. This column lists the
required revision level. For the 5306/6306
MMI PROM, UniPak revision D or [ater can be

used. For the others, revision A or later is
applicable.
Fam. Code

Family code programmed for the UniPak and the
specified card set

Pin Code

Pin code programmed for the UniPak and the
specified card set

5.3

ARRAY DECODER

Each array decoder location controls a 4-kilobyte segment of array memory. For

example, in a 512 by 4 array decoder, there are 512 locations and each location

controls 4 kilobytes of memory. Two pattern select lines (Figure 5-1) allow one of
four patterns to be selected. Each pattern contains 128 locations (512 divided by
4). The pattern select lines are connected to the pattern select jumpers, which
select the desired pattern.
The first location (location Q) of each pattern responds at the starting address of
the module. Location 1 responds at the next address and so on up to location 127.
These 128 locations comprise the first pattern (pattern 0), which is indicated by

both pattern select lines being 0. The next 128 locations comprise pattern 1, the
next 128 locations comprise pattern 2, and the final 128 locations comprise pattern

3 (Figure 5-2).
NOTE:

Figure 5-3 shows the pin designations of the array decoder. Refer to

them when you design the array decoder for a special application.

PROGRAMMING THE ARRAY DECODER

LOGICAL EQUIVALENT
OF PATTERN 1

csB
osC

13
12

8US

ADDRESS
LINES

S0
o

csA

3708
DECODER

15
16

cs2
o3

CHIP SELECT

LINES TO

[CS4 (CHIP SELECT
SOCKETS
css

cs6

cs7

OUT OF RANGE

PATTERN

-y AI

FROM PATTERN

B |
20"

—

SELECT LINES

SELECT SWITCHES
MA-0181-83

Figure 5-1

2K Array Decoder

PATTERN SELECT LINES

511

SEL B

SEL A

PATTERN 3
________________

384
383

PATTERN 2
______________

|256
255

PATTERN 1
______________

128

127

PATTERN 0
0

MA-0177-83

Figure 5-2

Pattern Select

ARRAY ADDRESS

VT [

17—

AB =3

ARRAY ADDRESS

16.-

Mo
w

2o
<

PATT. SEL A} TO PATTERN
paTT.

ENBf————

12— a0
n—2Jdar
e

(14

45V

12
10
°

SELECT

SE
BJ JUMPER CLIPS
SEL

csA
csg b CHIP SELECT TO
CcsC

3-70-8 DECODER

OUT-OF-RANGE - TO ACCESS
DETECTOR
MA-0176-83

Figure 5-3

Pin Designations for Array Decoder

PROGRAMMING THE ARRAY DECODER

Three chip select lines from the array decoder are applied to a 3-t0-8 line decoder
(Figure 5-1). The 3-to-8 decoder asserts one of eight chip select lines. One fine is

associated with each pair of chip sets. The chip select number and the in-range

signal must be asserted to turn on a chip set. Under these conditions, the chip set
is enabled and all other chip sets are turned off.

For the 2K by 8 decoder pattern, each PROM pair monitors bits 0 through 11.
These bits specify a byte within each 4-kilobyte block. Bits 12 through 14 are chip

select lines. Bits 15 through 18 are bits that determine if the address is in the range
of the MRV11-D. A 4K by 8 PROM pair monitors bits 0 through 12. Table 5-2
shows the chip select bits and range bits for fully populated arrays using other size

PROMs. For each PROM size, bit O specifies high byte or low byte. As an example,
a 4K by 8 PROM requires 13 address bits. They are address bits 0 through 12,
where bit 0 merely specifies which byte of the chip set is specified.
The least significant bit (LSB) into the array decoder can resolve between 4kilobyte blocks. For example, in the 2K by 8 PROMs, bit 12 controls the first 4-

kilobyte boundary and is the LSB applied to the array decoder. The remaining
address bits control the memory boundaries as foliows.

Bit

Controls

8-kilobyte boundaries

16-kilobyte boundaries

32-kilobyte boundaries

64-kilobyte boundaries

128-kilobyte boundaries

256-kilobyte boundaries

An 8K by 8 PROM pair requires 14 address bits (0 through 13). In this case, bits
14, 15, and 16 are chip select bits and bits 17 and 18 are out-of-range bits.

Chip Select and Range Bits for Fully Populated Module
Monyiytars; . Chip Select
Bits

Bits

L 13,14,15
4,15,16

Qut-of¥Range

- Bits

516,17

6,17,18 =~

PROGRAMMING THE ARRAY DECODER

5.4

GUIDELINES AND RESTRICTIONS

When programming your own array decoder, you should follow certain guidelines
and restrictions. This section describes them.
Use only 2K by 8 devices or larger.

Devices must be in pairs and there must be no mixing within pairs of devices.
For example, you cannot have a 2K by 8 PROM in the high byte of chip set

socket 0 and a 4K by 8 PROM in the low byte of chip set socket 0.
If you are installing a static RAM, you must install it in the lower half of the
array. A 4K by 8 PROM can be mixed with static RAM in the same row, or 1t

can be placed elsewhere in the array. The 8K by 8, 16K by 8, or 32K by 8
PROMs cannot be mixed with RAM in the same row and must be installed in
the upper half.
If you are creating a pattern that includes bootstrap code, the bootstrap code
must reside in chip set 7. The code should not be included in your pattern.

Otherwise, the bootstrap code will appear erroneously.
Do not mix 2K by 8 devices with any other device sizes on the module.

You can mix 8K by 8 devices with 4K by 8 devices in the same row or with
16K by 8 devices in the same row.

If 32K by 8 devices are installed in a chip set, no other device sizes can be
installed in the row incorporating that chip set. For example, if 32K by 8

devices are installed in chip set 0, chip set 1 can contain only 32K by 8
devices.

When developing an array decoder pattern to handle a mixture of device

sizes, enabie the largest device to be read first. Otherwise, blocks in the
array will be offset because the larger devices sample higher order address

lines.

For example, you have an 8K by 8 RAM pair that must be installed in the
lower half of the array and you want to install a 16K by 8 PROM pair. You
must install the 16K by 8 PROM pair in the upper half. In this case, you
should enable the 16K by 8 PROM to be read first, even though RAM is in the
lower half of the array and 16K by 8 PROM is in the upper half of the array.
5.5

DESIGNING AN ARRAY DECODER

This section briefly describes the procedure for designing a decoder PROM for a

specific application. Before proceeding, become familiar with the guidelines and
restrictions described in the preceding section.

The first step is to convert the bus address to the array address. In direct mode,

select a starting address and subtract it from the bus address. To obtain the array

address in page mode, bits 11 through 21 of the bus address are stripped off. Bits
11 through 17 of the bus address are replaced by bits from the PCR that represent
the page number for the corresponding window.

PROGRAMMING THE ARRAY DECODER

Next, determine the pattern seilection and the decoder PROM address. The pattern

select jumpers determine the pattern select lines. The decoder PROM address is
obtained by appending the pattern select bits to bits 12 through 18 of the array.
address.

Finally, determine which device is to be read for each 4-kilobyte block of bus
addresses. Once the chip set number for each block is determined, it is programmed into the array decoder as out-of-range and chip select C, B, and A.
Refer to Figures 5-4 and 5-5 for help in designing the array decoder. Use the form

in Figure 5-4 when you are using direct mode addressing. Use the form in Figure
5-5 when you are using page mode addressing.
This section provides examples that show how to use these forms. The following

points are common to the exampies. Keep them in mind when you review the
examples.

* Because of space considerations, the bus address and array address in the
examples are shown in octal format. The decoder address is shown in binary
format. The binary format for the decoder address is used so you can see the

effect of bit.12 and higher order bits changing individually throughout the
pattern.

e The pattern select bits (appended to bit 18 of the decoder address) take the
value set in the pattern select jumpers.

¢ The decoder address, bus address, and array address increase sequentially
through a given pattern.

¢ Bit 12 defines 4-kilobyte boundaries, so each row represents a 4-kilobyte
increase. The bus address and array address increase by 10000g in each
row. This increase is equivalent to the 4-kilobyte increase of the decoder
address.

¢ The decoder data is the data that is programmed into the device at the speci-

fied address. This data consists of the out-of-range line and three chip select
lines labeled C, B, and A. The three select lines are supplied to a 3-to-8 line
decoder with each of the eight output lines connected to a different chip set.
* When the pattern is programmed, all other locations remaining in the pattern
represent an out-of-range condition. The out-of-range condition is denoted

by the out-of-range line going to a logic 1. When this occurs, C, B, and A
select lines are marked with Xs indicating a “don’t care” condition.

»0

14,13, 12

—

|21

1413 12

» 0] PATTERN

SELECT

r—‘mm

17116

15[l

13[n2]

DECODER DATA

(BINARY)

OUT OF

RANGEL¢ | 8 | A

MA-0189-83

Figure 5-4

Direct Mode Format for Array Decoder

§300030d AVHEY IHL ONINWVYHEDOHd

DECODER ADDRESS (BINARY)

ARRAY ADDRESS (0 (OCTAL )

PROGRAMMING THE ARRAY DECODER

PAGE NUMBER (BINARY)

PATTERN

16 | 15 | 14

12 | 11

DATA

o ECODER
C(&NARY)

DECODER ADDRESS (BINARY)
SELECT

‘\_V__.J

{17

15 | 14

13 | 12

OUT-OFR

ANGE

MA-0188-83

Figure 5-5

Page Mode Format for Array Decoder

Example 1

Figure 5-6 shows an example that uses direct mode addressing with 2K by 8
PROMs in chip sets 0 through 3 and 2K by 8 bootstrap PROMs in chip set 7. The
PROMs are to respond in sequential order from chip sets 0 through 3. Chip set 7 is

dedicated for the bootstrap PROM and will not affect the pattern. This chip set is
selected by a bootstrap access only.
Figure 5-6 shows an example with a module starting address of 0 and bus address

of 0. Each row of the figu're represents a 4-kilobyte segment (equivalent to
10000g). With 2K PROMs, bits 12, 13, and 14 are chip select lines and bits 15

through 18 are out-of-range bits. The decoder address consists of bits 12 through
18 plus the two pattern select lines, which reflect the state of the pattern select

jumpers. With both pattern select bits on Os, it means that pattern 0 of the decoder
PROM is being programmed.
Each time bit 12 toggles, a new 4-kilobyte segment is introduced. Bit 13 toggles on
-

8-kilobyte segments and bit 14 toggles on 16-kilobyte segments.

PROGRAMMING THE ARRAY DECODER

cs6

cs7

cs6

css

Cs4

sz
2K

Cs3
2K

cs2
2K

2ksoor)

cs4
Cso

14,13,12

CS5 | START ADDRESS: 00000
-

BUS ADDRESS; 00000

CS3 | ARRAY ADDRESS: 00000
2K | DEVICES: 2K BY 8 PROMS IN CSO THRU CS3 AND CS7

Cso

CSt

BUS ADDRESS

cs7

2k Boor) oot
e e o

OCTA

| ORDER OF RESPONSE: CS0, CS1, CS2, CS3

ARRAY ADDRESS

DECODER ADDRESS (BINARY)

| DECODER DATA

)

i |0

214—-———‘
A o | PATTERN
14,13,12

SELECT

00000000

000

—

00000000

A 18 171615
1413 12
000 O0OO

OUT OF
|RANGE

C B A

000

CHIP SETO

2Kby8

PROM PAIR
CHIP SET
1

00010000

000

001

2KbyB
PROM PAIR

2
CHIP SET

00020000

000

010

2Kbys
PROM PAIR

3
CHIP SET
00030000

00030000

000

00040000

000000

L —

011

100

2Kby8
PROM PAIR

’

[ I

01770000

001

111

OUTOF

~—

RANGE

111

X X X

.
A)

[

OUT OF
RANGE

NOTE THAT CHIP SET 7 1S NOT PART OF
THE PATTERN AND IS SELECTED ONLY

BY A BOOTSTRAP ACCESS THROUGH BOOTSTRAP WINDOWS
17773000 - 17773777
OR

17765000 - 17765777
MA-0192-83

Figure 5-6

Array Decoder Design — Example 1

Consequently, the pattern increments from 00000000g to 00030000g. The out-ofrange condition and the chip select fines (C, B, and A) contain the data pro-

grammed into the decoder PROM. The C, B, and A lines are the chip select lines
that enable the proper chip set sockefs via a 3-to-8 line decoder.

After pattern 0 of the decoder PROM is programmed {(array address equals

00030000g), the remaining locations in pattern 0 are considered out-of-range (outof-range bit asserted). The C, B, and A bits at this point are in the “don’t care” con-

dition and are indicated by an X in the column.
Patterns 1, 2, and 3 are programmed in & similar fashion and can be programmed

with different patterns. The pattern select lines reflect the pattern being
programmed.

PROGRAMMING THE ARRAY DECODER

Example 2

Figure 5-7 shows an example using direct mode addressing with 4K by 8 PROM
chips in all sockets except for chip set 4, which contains 8K by 8 chip sets. In
accordance with the guidelines previously described, chip set 4 must respond first
since it is the largest memory device included. For this example, the response
orderis chipset4,5,6,7,0,2,1,and 3.

In Figure 5-6 the bus address and the starting address are the same. In this example, they are different. The starting address is 20000g.

Note that the pattern select bits are 115, indicating pattern 3 is selected. Also, for
4K PROMs, hits 13, 14, and 15 are chip select lines. For 8K PROMs, bits 14, 15,

and 16 are chip select lines. Consequently, bit 12 for the 4K by 8 PROMs and bits
12 and 13 for the 8K by 8 PROMs are ignored while those devices are accessed.
Since each entry in the table represents a 4-kilobyte block, the 8K by 8 PROM pair
(16 kilobytes) requires four entries of 4 kilobytes each. The 4K by 8 PROM pair (8
kilobytes) requires two entries of 4 kilobytes each. The C, B, and A lines are the
binary equivalent of the chip set socket. For example, the C, B, and A lines for chip
set4 are 1002.

The PROMS are listed in the order they are to respond. When the last chip set is
programmed (chip set 3), the out-of-range bit is asserted and the C, B, and A lines
are contained with -Xs denoting a “don’t care”-condition. The end of the pattern

occurs when bits 12 through 18 are all 1s as shown.
This example represents the decoding of one-fourth of the decoder PROM, which
is pattern 3. Patterns 0, 1, and 2 would be similarly programmed, if required, and
the pattern select hits would be changed to reflect each pattern.

PROGRAMMING THE ARRAY DECODER

s6 | cs7
C“f
o

cs7

Cf"f

MODE: DIRECT

PATTERN SELECTED: 3 (11 BINARY)
CS4 | CS5 | CS4 | CSB | START ADDRESS: 20000 (OCTAL)

8K | 4K | 8K | 4K | gys ADDRESS: 20000 (OCTAL)

cs2 | cs3 ] cs2 | cs3 | ARRAY ADDRESS: 00000 (OCTAL}

4k | ax | ax | ax | DEVICES: 4K BY BPROMS IN ALL CHIP SETS EXCEPT
8K BY 8 IN CHIP SET 4

Toso | oot

eso | os1

OF RESPONSE: CS4, CS5, CS6, CS7, CS0. CS2, CS1, CS3
ak | ak | ax | 4x | ORDER

BUS ADDRESS (OCTAL} | ARRAY ADDRESS (OCTAL}|

14,13,12

e .

14,13,12

DECODER ADDRESS (BINARY) |DECODER DATA

PATTERN
SELECT

—
B

OuT OF

A 18 171615 1413 12|RANGE

C B A

00020000
00030000
00040000
00050000

00000000
00010000
00020000
00030000

110000000
110 000 001
110000010l
110000 01 1

0
o0
0o
0o

100)
100\
100{
100

00060000

00040000

1170000 100

101}22'25’%5

00100000

00060000

1101

00120000

00100000

001100 00

110001

110001 000
001

111}22';(35;7

00140000
00150000

00120000
00130000

110001
110001

010
011

0
0

4kgy1s
000\
000 ) prom PAIR

00160000

00140000

110001 100
110001

101

001

001}

00200000
00210000

00160000
00170000

110001
110001

110
1 11

0
0

6
010 | 4kBY
010 J proM PAIR

00220000

00200000

110010 000

011

00240000
v
S

00220000
—
J

000700 00

00110000

00130000

00170000

00230000

5000

00070000

00150000

00210000

110

110000

20100000

110l

1170000 1 11

010001

10
17100100
—
_—

“

110

:
2

m—

01770000

[

cypseTa
gkey1s
prompanr

101 ) crompam
CHIP SET 6

apyis

promPAR

110J

111 )

CHIP SETO

iKlBstfi

HIP SET 1

promeanr

CHIP SET 2

E,’:‘;’stfia
.

promepaR

011}

xxx

~—

)

t 11 111 110

sromeam

—A—

XXX

OUTOF
RANGE
.

]

CR’:’:GOEF
MA-0191-83

Figure 5-7

Array Decoder Design — Example 2

PROGRAMMING THE ARRAY DECODER

Example 3

Figure 5-8 shows an example using page mode addressing with 8K by 8 static

RAMSs in chip sets 0 and 1 and 4K by 8 PROMs in chip sets 4 and 5. The order of
response is chip set 0, 1, 5, and 4. Note that the higher capacity device must
respond first as previously described.

In page mode, bits 11 through 21 of the bus address are stripped off. Bits 11
through 17 are replaced with bits from the PCR representing the page number for
the corresponding window.

The bus address lies between the starting address and the starting address plus 4
kilobytes because this is the defined window size.

The page number is designated by bits 11 through 17. However; the decoder
address looks at bits 12 through 17 and ignores bit 11 because this bit defines 2kilobyte boundaries. Note that the pattern select bits are 015 indicating pattern 1 is
selected.

Pages are 2 kilobytes wide. in an 8K by 8 device pair (16 kilobytes), there are eight
2-kilobyte pages. In the 4K by 8 devices, there are four 2-kilobyte pages. The array

decoder looks at 4-kilobyte blocks and each bus address entry is 2 kilobytes.
Therefore, each array decoder address entry repeats to provide 4-kilobyte biocks
in the pattern.
During operation, the page number must be in the corresponding byte of the

desired window. If the page is in window G, the lower byte of the PCR is designat-

ed. If page is in window 1, the upper byte of the PCR is designated.
This example consists of 24 pages. Eight pages are for each of the two 8K by 8
devices, and four pages are for each of the two 4K by 8 devices.
When the twenty-fifth page is reached, the out-of-range bit is asserted and the C,
B, and A lines are denoted with Xs, which indicate the “don’t care” condition.

le}aMwAmTaCnE

PROGRAMMING THE ARRAY DECODER

Txod<

[}

[=) w

o«
-

h[wa)

e eo

——————
e — — =~
— —

Figure 5-8

ENDOFPATTERN
] == — — — ~— — — —

Array Decoder Design — Example 3

MA-0190-83

MAINTENANCE

6.1

INTRODUCTION

No diagnostic programs are available for the MRV11-D. Each customer supplies
his own firmware. Consequently, each module has a separate configuration, ruling
out a common diagnostic.
In lieu of diagnostics, perform the following procedures to determine whether the
module or the PROMs installed in the module have malfunctioned.

6.2

TROUBLESHOOTING

if there is a malfunction on the MRV11-D and a set of spare devices is available,

remove the devices from the module and insert the spare set. if changing devices

does not solve the problem, perform the follS\Tvinfg steps.
1. Check the LED on the module. If it is not fit, power is probably not being supplied to'the memory array.

2. Check the battery backup jumper to see that it is correctly positioned. if it is,
the problem is in the power distribution to the backplane.
3. Check the jumper configurations to ensure that the moduie is properly
configured.

4. If console ODT is available, additional steps can be performed. The following
section describes these steps.

MAINTENANCE

6.3

CONSOLEODT

The console octal debugging technique (ODT) is a portion of the processor micro-

code that is very useful for debugging and running programs. Console ODT allows.
the processor to respond to commands and information entered from a local or
remote terminal. Communication between the user and processor is generated via

a stream of ASCII characters interpreted by the processor as console commands.
These commands are a subset of ODT-11 (Table 6-1).
Terminal addresses used by console ODT are 177560g through 177566g. It uses

addresses 777560g through 777566g for 18-bit systems and 17777560g through
17777566¢g for 22-bit systems. These addresses are generated in microcode and

cannot be altered.

The following paragraphs describe the console ODT terminal command set (Table
6-1). These commands are a subset of ODT-11 and use the same command characters. Console ODT has 10 internal states, which are listed in Table 8-2. For each
state, only specific characters are recognized as valid inputs; other inputs invoke a

“?” response.

MAINTENANCE

For additional information on ODT, refer to the Microcomputer and Memories
Handbook (EB-20912-20). If you suspect the module to be malfunctioning, per-

form the steps in paragraph 6.2. If console ODT is available, perform the following
additional steps. Press the HALT switch on the front panel to initiate ODT.
1.

If bootstrap is enabled, open the bootstrap PCR at 17777520g and ensure
that all bits can be read or written.

If bootstrap is enabled, you should be able to read bootstrap code at the following locations.
17773000g ~ 177737768

177650008 — 177657768

If page mode is enabled, you should be able to read and write the page mode

PCR in the location set by the PCR address switches. You should not be able
to read other locations since a timeout should occur and ODT should
respond witha “?.”

If two MRV11-Ds are configured for page mode in the same system, two
unique PCRs should appear in two locations between 17777000g and
17777036g.

Set PCR bit 15 (window enable) to a 1 and put a desired page number in

each byte of the PCR. You should see the requested pages through window
0 (at the starting address) and window 1 (2 kilobytes above the starting
address).

Set bit 15 to a*0. Timeout should occur at the locations in step 5 and a “?”
should appear on the terminal.

if you exceed the page limit of the MRV11-D set by the decoder PROM (by
placing a page number in the PCR that is too large), timeout occurs and a **?”
appears on the terminal.

In direct mode, all unused PCR locations should time out and expected data

should appear from the starting address to the upper boundary of the array
(which is set by the decoder PROM).

.- If RAM is present on the module, it should be read/write. If you are unable to
write RAM, check the following jumpers.

W4 - DATO timeout W5 — Write enable (high byte)
W6 — Write enable (low byte)

MAINTENANCE

10. Check voltage at bus pins BV1, AA2, and BA2for +5 V.
11.

If battery backup is installed, check voltage at bus pin AV1 for +5 V.

If the above steps do not solve the problem, contact the Technical Volume Group
Hotline (617) 467-7787.
The

module may be repaired

by the Customer Return Center in Woburn,

Massachusetts provided all customer firmware is removed and the module is properly packaged. For more information, call 1-(800)-225-5385.

MODULE

CONFIGURATION

This appendix summarizes the module configuration given in Chapter 3. Figure 3-2
is a flow diagram that provides the sequence for configuring the module. Figure 3-3

shows the locations of the jumper groups on the modules. Use Figure 3-3 in conjunction with Figure A-1, which represents the location of each jumper pin on the
module.
For example, to configure the device size jumpers, use Figure 3-3 to determine
their location on the module (just to the right of E20 upper-right quadrant of mod-

ule). Then refer to the device size jumpers listed in Figure A-1. Figure A-1 shows
the device size jumpers, in detail, as a'set of five jumpers (J14 through J10)

arranged vertically. The orientation is component-side-up with the handles facing
away. It is important to maintain this orientation as the jumpers on the module are
not designated. With this orientation, J14 is the jumper closest to the handles and
J10 is farthest from-the handles. The PCR address switches and start address

switches are shown at the end of Figure A-1.

APPENDIX

FUNCTION

JUMPER CONNECTION

BATTERY BACKUP
NO BATTERY BACKUP

08o0d

(SHIPPED CONFIGURATION
(W2 REMOVED)
BATTERY BACKUP (W1 REMOVED}

HOLES ON
PRINTED

CIRCUIT

! o l o B0ARD

SYSTEM SIZE
16-8IT, 18-8IT

ddo

{SHIPPED CONFIGURATION}

J21 J22 J23

22-BIT

J21

J22 423

ROM/RAM SELECT

J3s 8]

ALL ROM MEMORY

(SHIPPED CONFIGURATION)

J37

136 0

J32 g]
331

4300

380

ROM/RAM MEMORY

J37
-

w§

J36

J320
J31 a
J3o

DATO JUMPER

DATO CYCLE CAUSES TIMEOUT

{NOT USED WITH RAM)
(SHIPPED CONFIGURATION)

315 316 J17

NO DATO CYCLE

RESPONDS TO DATO CYCLES

(USED WITH RAM INSTALLED)

J15 J16 417
MA.0201-83

Figure A-1

Module Configuration (Part 1)

APPENDIX

FUNCTION

JUMPER CONNECTION

DEVICE SIZE

REVC*
ETCH

2K BY 8 DEVICES t{SHIPPED
CONFIGURATION)

ws[ g
AND

4KBY B, BK BY 8,

OR 16K BY 8 DEVICES

g lws

N2
m

w7! g

32K BY 8 DEVICES

REVD®
ETCH

J10

AND

g lw7

D O 412 g |W7
AND
Jan

L—g

Jio

114

J12

J10

AND

*TO LOCATE THE REVISION OF THE ETCH, REFER TO THE
LEFT SIDE OF THE MODULE, COMPONENT SIDE UP.
REVISION C ETCH - 5015213C
REVISION D ETCH ~ 5015213D

tTO USE 2K BY 8 DEVICES (REV C ETCH ONLY),
REMOVE W8 AND WIREWRAP PIN J13 TO PIN J41
(+5V).
MA 020083

Figure
A-1

Module Configuration (Part 2)

APPENDIX

JUMPER CONNECTION

FUNCTON

POWER 1UMPERS
2K BY 8.AND 4K BY 8 ROMS AND

Ja1

w12

BK BY 8 STATIC RAM (SHIPPED

J40

ROW 4

CONFIGURATION)

J39 O

J35

w11

134

ROW 3

J3s3 O
J29

w10

128

ROW 2

J27 O
J26

125

ROW 1

J24 O

16K BY § AND 32K BY 8 ROMS

Jas O

{8K BY 8 ROMS ARE OPTIONAL AND
MAY USE EITHER SET OF JUMPER

J40

CONNECTIONS)

J39

w12

ROW 4

435 O

J34

133

w11

ROW 3

220
J28

w10

J27

ROW 2

J286 O

J25

ROW 1

NOTE

THE POWER JUMPERS ARE CONNECTED ON A ROW-BY-ROW
BASIS. FOR EXAMPLE, IF A 16K BY 80R 32K BY 8
DEVICE WERE INSTALLED IN ROW 2, W10 WOULD BE
CONNECTED FROM J28 TO J27 RATHER THAN J29 TO J28.
MA-0190-83

Figure A-1

Module Configuration (Part 3)

APPENDIX

FUNCTION

JUMPER CONNECTION

READ TIMING

450 ns READ TIME (NORMAL}

Wi3

(SHIPPED CONFIGURATION)

418 119 J20
200 ns READ TIME (FAST)

wi3

118 119 J20

ENABLE BOOTSTRAP
BOOTSTRAP ENABLED

(SHIPPED CONFIGURATION) .

J6
J5

g |w14

i’ ¥e)

BOOTSTRAP DISABLED

J6 O

e
Ja

w14

STANDARD DECODER PATTERN SELECT

2K BY B ROMS, HALF POPULATED

i:Ne]
J8
J7

2K BY 8 ROMS, FULLY POPULATED

g |w1s

90O

4K BY 8 ROMS, FULLY POPULATED

30O

J9 : :I
J8

w16

J70

8K BY 8 ROMS, FULLY POPULATED

J9 ::]

(SHIPPED CONFIGURATION)

: g |w1s

J2
J1

2]
J2

J10O

J30
J2

w15

w16

J70

w15

253
J2

w15

J10

MA-0202-83

Figure A-1

Module Configuration (Part 4)

APPENDIX

SWITCHES

FUNCTION

STARTING ADDRESS SWITCHES
PUSHING RIGHT ROCKER OF SWITCH
TURNS SWITCH ON (LOGIC 1}.
PUSHING LEFT ROCKER OF SWITCH
TURNS SWITCH OFF (LOGIC 0).
SET FOR STARTING ADDRESS OF THE

[(Te

SA21 MSB
SA20
SA19

MODULE.
SA18
SA17

SA16
SA15
SA14
SA13

SA12 LSB

PCR ADDRESS SWITCHES

TO SELECT DIRECT MODE, PUSH RIGHT
ROCKER DOWN. TO SELECT PAGE MODE,
PUSH LEFT ROCKER DOWN.

PCR1 THROUGH PCR4 REPRESENT THE
ADDRESS OF PCR. PUSHING RIGHT ROCKER
OF SWITCH PRODUCES A LOGICAL O

(SWITCH OFF). PUSHING LEFT ROCKER OF
SWITCH PRODUCES A LOGICAL 1 {SWITCH ON).

ON-DIRECT
OFF PAGE
PCR4
PCR3

PCR2
PCR1

NOTE

MODULE ORIENTED WITH HANDLES FACING AWAY.
MA-0198-83

Figure A-1

Module Configuration (Part 5)

Digital Equipment Corporation.Bedtord, MA 01730