Digital PDFs

EK-M9312-TM-002

2000

82 pages

Original

5.5MB

view download

OCR Version

4.7MB

view download

Document:	M9312 Bootstrap/Terminator Module Technical Manual
Order Number:	EK-M9312-TM
Revision:	002
Pages:	82
Original Filename:

OCR Text

M9312

bootstrap/terminator
module technical

manual

dlifgliltiall

EK-M9312-TM-002

M9312

bootstrap/terminator
module technical

manual

digital equipment corporation - maynard, massachusetts

1st Edition, July 1978
2nd Edition (Rev), October 1979

The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:;

DIGITAL
DEC
PDP
DECUS

UNIBUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM

MASSBUS
OMNIBUS
0S/8
RSTS

VMS

IAS

VAX

8/80-14

RSX

CONTENTS

Page
CHAPTER 1

INTRODUCTION
GENERAL DESCRIPTION.......o et
seee e een e sen b e e 1-1

SCOPE ceveiriee it ireirereueeteeeeeterteeeeeteseeeesatasanneeesesessnsaneseenseeeesrsrennnsensssrersrsntnne 1-1
Related Documentation ..........coooviiiiiiiiiiiiiiiiec
e
e 1-3
DEFINITION OF TERMS ...
et e e sre v e 1-3
PHYSICAL DESCRIPTION ...
ee
s 1-3
ELECTRICAL SPECIFICATIONS... ..ottt
ee e 1-3

External Electrical Interfaces.............ccooevveviniiiiiiiiiiiiiiiiicieeie
e 1-3

Electrical PrerequUISites ........covvuuiiiiiiiiiiiiiiiii ettt

eerae e e

eevenes 1-4

TAMINE oot
eer e eee e rre e eeraba e sesra e eeessbansseseasessseseansns 1-5

Operational Environmental Specifications..........cccoeevvivviieeiiiiiiiiiiinicieenennnn. 1-6
INST ALLATION. ... e
ee e
eee b e e e s seanns 1-6
Power-Up Boot Enable...........cooovveiiiiiiiiiiiiicn

e 1-7

BOOt SEIECHION ....oiiieiii e
e 1-7
External Boot SWitCh.......cooouiiiiiiii 1-7
CHAPTER 2

HARDWARE DESCRIPTION

2.1

GENERAL.... et
e r e e s sebr s s e e saaan s 2-1

2.2

ROM MEMORY ...ttt
ettt e e s e bt sa s e s e e e venens 2-1

2.2.1

ROM SPECIHICALIONS ......uivviiiiiiiiiiiiiiiii
et eeetn st seera e e 2-2

2.2.2

1100
J1% B Qo]
¢ 1+ -1 S TSRO 2-2

2.2.2.1
2.2.3
2.2.3.1
2.2.3.2

224

ROM Header ...ttt
e e 2-2
130\B D F: 1 ¥ WU 2-3
ROM Data Transfer ..........cooovvvieiiiieiiiiiiiiiiieic
e
e 2-3
ROM Data Organization..........c.ccuuueieeuiniiiiiniiiiieeiieeeeineeen
eeenneesenns 2-3
Requirements for new ROMs and Uses of the M9312..........oeviiivviniininnnnnnns 2-3

2.3

POWER-UPSEQUENCE.......o

2.4

POWER-UP BOOTING LOGIC.......ccoootieieiieiiiiieieeieeiie

e e 2-3
ettt

e e ee e 2-5

24.1

Power-Up and Power-Down............. et

24.2

Processor Reads New Program Counter..........cccceevivieiiiiiiiiiiiiniiinceeveineeeee, 2-8

24.3

Processor Reads New Status Word.........ccccceeeiviiiiiiiininiciiiicn

244

Power-Up Boot Enable SwitCh ............ccooovviiiiiiiiiii

taenet e tat e ruteeeatatren
b erntnrettnraenaanns 2-6
e, 2-8
v, 2-8

2.5

EXTERNAL BOOT CIRCUIT ...ttt
ettt s et s s e eevneens 2-8

2.6

POWER-UP TRANSFER DETECTION LOGIC...........ccouttuieieeeeeeeeieeee 2-8

2.7

POWER-UP CLEAR ...ttt
et e e e 2-8

2.8

ADDRESS DETECTION LOGIC ...t
ceeeeetree

e e eeveeeeeas 2-11

2.8.1

MO312 AdAress SPACE........cuuuieieeeiiiiiiiiiieeeeeeeeeeieee
e eee e e teree e seeerseennnns 2-11

2.8.2

Memory Access CONSIIAINES .......ccuuueiiiiiiiieeeeriieiieeeiiiieerret
e eeaeeeeeneessenens 2-11

2.8.3

LO ROM ENA H JUMPET ....coovieiiieiceeee ettt et e e e e e 2-11

2.9

ADDRESS OFFSET SWITCH BANK ..ottt ceieeaeeeeeveevaneas 2-13

2.10

MOIBI2TERMINATOR. ...
ettt et eee e e ves 2-14

CONTENTS (Cont)

Page
CHAPTER 3

CONSOLE EMULATOR

3.1

GENERAL.......co e eaneretattrteerata
e s aees ........ 3-1

3.2

USING THE CONSOLE EMULATOR

3.2.1
3.2.1.1

Successive Operations
Examine

....................................................

...........................................................................

.......................................................................................

3.2.1.2

Deposit

3.2.1.3

Alternate Deposit-Examine Operations

3.2.14

Alternate Examine-Deposit Operations

3.2.2

3.3
3.3.1

3.3.2
34

.........................................................................................

Limits of Operation

........................................

.........................................

...............................................................................

BOOTSTRAPS STARTED FROM THE CONSOLE EMULATOR

...........

Booting the High-Speed Reader Using the Console Emulator...............
Booting a Disk Using the Console Emulator
RECOVERING FROM ERRORS IN THE CONSOLE EMULATOR
ROUTINE

....................................................................................................
.

CHAPTER 4

BOOTSTRAPPING

CHAPTER §

EXTENDED ADDRESSING

5.1

GENERAL

5.2

VIRTUAL AND PHYSICAL ADDRESSES

5.3

ADDRESS MAPPING WITHOUT MEMORY MANAGEMENT

5.4

ADDRESS MAPPING WITH MEMORY MANAGEMENT

5.5

5.6

CREATION OF A VIRTUAL ADDRESS
CONSTRAINTS

CHAPTER 6

DIAGNOSTICS

6.1

GENERAL

6.2

DIAGNOSTICS

6.3

DIAGNOSTICS (PDP-11/60 AND 11/70)

APPENDIX A

M9312 JUMPERS

APPENDIX B

M9312 ROMs

APPENDIX C

M9312 ADDRESS OFFSET SWITCH BANK.

APPENDIX D

M9312 FASTON TAB CONNECTIONS

APPENDIX E

CROSS REFERENCE AND IDENTIFICATION TABLES

APPENDIX F

DIAGNOSTIC AND CONSOLE EMULATOR ROMS

...................................................................................................

...............................................

............

.....................

...................................................

oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

FIGURES

Figure No.

Title

Page

1-1

M9312 Bootstrap/Terminator Module................cooiiiiimimiiiiiiiiici
e, 1-2

1-2

MO312 TimIng ConStraINtS........ccuiiiiiiiiiiiiiieciee
e e et e ee e e e se s e eeaesennens 1-5 -

2-1

ROM SeBIegatiOn ....ccuuivuiiiiiiiiiiiiiiiiieriiieeeieeereeetereteeeteerneesreeeanneenesansennessnnsannsns 2-1

2-2

ROM Data Transfer.........ccouuiiiiiiiiiii
e
s ae e ee e s aea e 2-4

2-3

Power-Down /Power-Up SEqUENCE...........evieriiiiirriiiiienneerie

2-4

POWer-UpP BOOt LOZIC ....uniiiiiiiiii ittt
e s er e st e sr e e ea e sea e 2-6

2-5

Address Generation LOZIC.......cc.uiviiiiiiiiiiiiiiiiiiiii
e eeevteeeet e ee st eesaneeaneeees 2-7

2-6

External BoOot LOZIC ......couniiii it
er e v e e 2-9

2-7

External Boot TImMING .......ccccouiiiiiiiiiiiie
e e e e r e e ee e e e e e
2-10

2-8

Power-Up Transfer Detection LOZIC..........ccoiiiiiiiiiiiiiiiiii

2-9

Power-Up Clear CIrCUILTY.....couuuiiiiiiii

2-10

Address Detection LOZIC ......oouviiiniiiiiiiiiiiicce
et e e sa e e aaans eerens 2-12

2-11

Address Offset Switch BanK..........cc.oiiviiiiiiiiiiiiiiiieiee
e
ve e 2-13

e 2-5

e .2-10
e v e e saee e e e e 2-11

TABLES

ROM Data Organization ........c..ceeiiiiiiiiiiiiiiieiiiie
ittt reeneerineeaneessnersnneessans 2-3

Jumper EXplanation...........c.oooiiviiiiiiiiii

st M= M)

MO312 Pin ASSIZNMENLS ...cuuiieniiiiiiiiiiiii
e
eeetee et e eereeeneeanee e reneesnnesanns 1-4

P [
S |
'
00w
>
PN
= W N = e N =

Related Documentation ............ccooeiviiiiiiiiiiieiiiiie
e
ee vt e e e e ne 1-3

JUMPeEr CONIGUIALIONS. .......c.viiiiiieieeeiteeeeeeeeteeeeteeereeeseeeesetteseraeeeese
e eessnesesseeens A-2

Page

met

Title

WO N

Table No.

ROM P/IN 23-T52A9 ... ettt
s e e s et e s s asaan e e seees C-3

C-3

ROM P/N 23-TS3A9 ..ottt
e e e e e v e e s s e e e e rese s aeaaas C-4

Console Emulator Switch Requirements..............cccooiiiiiiiiiiiiiii

e, 3-1

Boot Command Codes .........covuuiiiiiiiiiiiiinii
e
e e s ver e s e naans 34
Deposit Errors: Useful Examples........cc.ouoeiiiiiiiiiiiiiiii

e, 3-6

Unibus Address ASSIZNMENTS ...........oeeviiuiiiiiiiiiieeiiiiiieeeeiiie
et e e ee e e eeeesenaaes 5-2
Relocation COoNStaAntS ...........ceivuiniiiiiiiniiii

et e et eesraeeaaaes 5-2
e A-1

Boot ROM Installation OTder...........ccoouuviiiiiiiiiiiieiiiiccee B-1

ROM P /N 23-78 1A e
ee et e e ar e e e s aa e e C-2

ROM P/IN23-TOLAD ..ottt
e e et e e e e e sees C-5
ROM P/N 23-T55A9 ...ttt eetetieteeteeeteeraesvteveseasseeesaeeessessesesssssesesseasens C-6
ROM P/N 23-TS56A9 ...
ettt v abe s s ae s e e besan e se e C-7

ROM P/N 23-TSTAD ettt
e ettt e e e e eevese e C-8
ROM P/IN 23-T58A9 ...

et ve e

e ee

e e eee e C-9

ROM P/N 23-TS59A9 ...ttt
e e e e e et e seare e e C-10

ROM P/IN 23-TOOAD ...t
et s e e s eaae e e e e eevana s C-11
ROM P/N 23-811A9 ... ettt
s e s e e ae e sase s s e s easesseanaes C-12
ROM P/N 23-TOAAD ...ttt
e e eeetttersee s e s s eeeeevesassesesaseasennsannes C-13
ROM P/IN 23-TOS5A9 ...t
e et e e e e e eeeeter e ese eC-14
\

TABLES (Cont)

Table No.
D-1

Title

Page

Faston Tab DesCription .......ccccuuiiiiiiiiiiiiiiiiie
ettt ertieeeeertereeeeesrane e ee e e s esannneeeans D-1

D-2

Faston Tab Substitution..........cccoiivniiiriiiii
e e e e D-1

E-1
E-2

Cross Reference ROM P/N to ROM Table Number........cc..cccovviiviiiiniiiiiennnn, E-1
Cross Reference Device to Controller ..........oocvviviiiiiiiiiiiiiiiiiiiiiereec
e
E-2

E-3

ROM IdentifiCation........cuoiiiiniiiiiiiiiie
ettt creeree s eerat e eesesrneeaena e eesneneenans E-3

F-1

Console Switch Register Settings for Diagnostic ROM ............cccooiiiiiiinniiininnnnnnn. F-1
Switch Settings for ASCII Console and Diagnostic ROM ..............cooiiiiiiiinnnnin. F-2

F-2

CHAPTER 1
INTRODUCTION

1.1 GENERAL DESCRIPTION
The M9312 Bootstrap/Terminator Module (Figure 1-1) contains a complete set of Unibus termination
resistors along with 512 words of read only memory (ROM) that can be used for diagnostic routines,
the console emulator routine, and bootstrap programs. Twelve jumpers (W-1 through W-12) are provided to allow compatibility with any Unibus PDP-11 system. Paragraph 1.6 outlines the use of these
jumpers. Five sockets on the M9312 allow the user to interchange ROMs, enabling the module to be
used with any Unibus PDP-11 system and boot any peripheral device by simply adding or changing
ROMs. One socket is solely used for a diagnostic ROM (PDP-11/60 and 11/70 systems) or a ROM
which contains the console emulator routine and diagnostics for all other PDP-11 systems. The other
four sockets accept ROMs which contain bootstrap programs. One or two bootstrap programs may be
contained in a particular ROM; however, some devices may require two or more ROMs to contain
their particular bootstrap programs. ROM placement is outlined in Appendix B.
Diagnostics, bootstrap programs, and the console emulator routine are all selectable through the
Address Offset Switch Bank on the M9312 (Paragraph 2.9). Appendix C shows the necessary switch
configurations and addresses for various M9312 routines. These switch settings and addresses depend
on the particular socket the ROMs are placed in. M9312 routines may be initiated in the following
ways:

External boot switch. This switch is connected to the module via Faston tabs TP1 and TP2.
The Address Offset Switch Bank is used to select various M9312 routines.

System power-up. This feature is enabled or disabled via switch S1-2. Again the Address
Offset Switch Bank is used to select various M9312 routines.

Programmer console load address and start sequence. The programmer loads the starting
address of a particular routine found in Appendix C.
NOTE
When the programmer console load address and
start sequence is used to start the console emulator
routine, the Address Offset Switch Bank setting determines whether or not diagnostics are run.

1.1.1 Scope
This manual is designed to provide DIGITAL Field Service and customer maintenance personnel with
sufficient installation and operation information to install and maintain the M9312 Bootstrap/Terminator Module.

1-1

FASTON TABS
TP4

TP2

TP1

ililale

BOOT ROM

TP3

ADDRESS OFFSET

/ SWITCH BANK S1

800T ROM

]

BOOT ROM ~
#4

)

(E37)

4100002000

—

w12

wn/

LO ROM ENA H

& DIAGNOSTIC ROM

JUMPER W-8

TN
L\WZ
W1

MA-0900

Figure 1-1

M9312 Bootstrap/Terminator Module

1.1.2 Related Documentation
|
Table 1-1 lists related documentation which supplements the information in this manual.

Table 1-1

Related Documentation

Title

Document Number

Media*

PDP-11 Processor Handbooks
PDP-11/34 User’s Guide
PDP-11/04 User’s Guide
Drawing Directory

EK-11034-UG-001
EK-1104-OP-002
B-DD-M9312-00

Hard copy
Hard copy
Hard copy
Microfiche

*Hard copy documents can be ordered from: Digital Equipment Corporation, 444 Whitney Street, Northboro,
MA 01532, Attention: Communication Services (NR2/M15), Customer Services Section.

For information concerning microfiche libraries, contact: Digital Equipment Corporation, Micropublishing
Group, PK3-2/T12, 129 Parker Street, Maynard, MA 01754,

1.2

DEFINITION OF TERMS

Bootstrap Program
A bootstrap program is any program which loads another (usually larger) program into computer
memory from a peripheral device.
Bootstrap
Bootstrap and bootstrap programs are used interchangeably.
Boot

Initiate execution of a bootstrap program.
1.3 PHYSICAL DESCRIPTION
The M9312 is a double-height extended module [21.6 X 14 cm (8-1/2 X 5-1/2 in)] which plugs into the
A and B terminator slots on the PDP-11 backplane. External connections are made via four Faston
tabs (TP1, TP2, TP3, TP4) provided at the handle end of the module.

1.4

ELECTRICAL SPECIFICATIONS

Power Consumption

+5 Vdc £ 5 percent at 1.5 A typical

Electrical Interfaces

The Unibus interface is standard using 8837 and 8640 receivers, 8881
drivers, and 8641 transceivers.

1.4.1
External Electrical Interfaces
The external interface consists of four Faston tabs (TP1, TP2, TP3, and TP4) provided at the handle
end of the module. These inputs were designed to operate from either a mechanical switch or a TTL
output (standard or open collector). Operation from TTL outputs is restricted to circuits inside the
standard DIGITAL enclosure having the same logic reference as the M9312. With mechanical
switches or TTL outputs, returns (TP2 and TP3) must be used. All inputs have overvoltage protection
for up to £16 V continuous; remote switch operation may require additional protection. When remote
switch operation is used, the switch should be electrically isolated from the remote device. Both signal
inputs (TP1 and TP4) have filtering and do not recognize an active input (below threshold voltage)
until the end of a 10 to 18 us delay, with any interruptions resetting the delay. The threshold range is
between +0.45 and +0.75 Vdc to logic reference. The following is a description of each input.
1-3

TP1

Boot signal input. For positive or negative inputs, represents a 1000-ohm load in

series with a forward biased diode to logic reference, and a 20,000-ohm pull-up.
Switch bounce noise must not exceed 70 ms. Triggering is disabled for a maximum of
8 ms, starting when the M9312 power supply voltage rises from less than 3.0 V to
greater than 4.5 V.,
TP2

Boot signal return. Represents a 1000-ohm load to logic reference.

TP3

Power-up boot enable return. Represents a 1000-ohm load to logic reference.

TP4

Power-up boot enable input. For positive or negative inputs, represents a 1000-ohm
load in series with a forward-biased diode to logic reference, and a 20,000-ohm pullup. This input must remain either a logical 1 or O for the entire power-up sequence.

1.4.2 Electrical Prerequisites

Power and Ground Pinouts

+5 Vdc: Pins AA2, BA2
GND: Pins AC2, AT1, BC2, BT1

(Refer to Table 1-2 for pin assignments.)

Table 1-2

M9312 Pin Assignments

Signal

AAl
AA2
ABI
AB2

BUSINITL
POWER (+5V)
BUSINTRL
TEST POINT

BAl
BA2
BBI
BB2

SPARE
POWER (+5V)
SPARE
TEST POINT

AC2
ADI1
AD2
AEIl
AE2
AF1
AF2
AHI
AH2

GROUND
BUSDO2 L
BUSDOI L
BUS D04 L
BUSDO3 L
BUSLC%% L
BUSDOS L
BUS DO8 L
BUSDO7L

BC2
BDI
BD2
BEI
BE2
BF1
BF2
BH1

GROUND
*W-6 IN: BUF VECTOR L
W-6 OUT: BAT BACKUP +5V
BUS BR4 L
INT* SSYN
PAR: DET
BUSACLOL
BUSDCLOL
BUS A0l

AJ2
AK1
AK2
ALl
AL2
AMI
AM?2
ANI1
AN?2
API

BUSDO9 L
BUSDI2L
BUSDIIL
BUSDI4L
BUSDI3L
BUSPAL
BUSDISL
P1
BUSPBL
PO

BJ1
BJ2
BK1
BK2
BL1
BL2
BM1
BM2
BN1
BN2

BUS AO3 L
BUS AO02L
BUSAOSL
BUS A04 L
BUS AO7 L
BUS A06 L
BUS AO9 L
BUS AO8 L
BUS A11L
BUS AIOL

ACI

AJl

BUSDOOL

BCl1

BUSDIOL

BH?2

*W-6 must be out for operation in a modified Unibus slot.

1-4

BUSBRSL

BUS AOOL

Table 1-2

M9312 Pin Assignments (Cont)

Signal

AP2
ARI

BUSBBSY L
BAT BACKUP +15V

BP1
BP2

BUS AI3L
BUS AI2L

AR2
ASI
AS2
ATI
AT2
AUI
AU2
AV1
AV2

BUSSACK L
BAT BACKUP-15V
BUSNPR L
GROUND
BUSBR7L
+20V
BUSBR6L
+20V
+20V

BR1
BR2
BS1
BS2
BTl
BT2
BU1
BU2
BVI

BUS AI5S L
BUS A14 L
BUS AI7L
BUS A16 L
GROUND
BUSCIL
BUSSSYNL
BUSCOL
BUS MSYNL

BV2

-5V

1.4.3 Timing
Figure 1-2 shows important timing constraints for the M9312. Values shown are typical.

BUSDCLO L

BUS ACLO L

UNIBUS ADDRESS TRUE

—1

BUS MSYN L

I
[

UNIBUS DATA TRUE

[

]

|
f— 14 —.l je—
08 _.r__—

BUS SSYN L

NOTE: ALL TIMES IN US.

i
MA-0912

Figure 1-2

M9312 Timing Constraints

1.4.4

Operational Environmental Specifications

Operating Temperature Range

5°C(41° F)to 50° C(122° F)

Storage Temperature Range

-40° C (-40° F) to 66° C(151° F)

Relative Humidity

10 percent or less to 95 percent with maximum wet bulb of 32°
C (90° F) and minimum dew point of 2° C (36° F).

1.5

INSTALLATION

As a universal bootstrap/terminator module, the M9312 in its various configurations can be adapted

by the user to meet a variety of boot requirements and system configurations. The following guidelines
should be used when installing the module.
.

System power should be turned off.

When a M9312 is used no other bootstrap module, such as the M9301, may be used, and
only one M9312 can be used in any given PDP-11 system.

In PDP-11/04, 11/34, and 11/34A systems without battery backup, TP4 should not be
connected to the processor’s power supply battery status signals unless boots on all power
restarts are desired.

On PDP-11 systems containing a Unibus repeater, the M9312 must be installed on the
processor side of the repeater.

Refer to Paragraphs 1.5.1 and 1.5.3 for power-up boot enable and external boot switches if
they are to be used in the system.
|
In PDP-11 systems that have grant pull-up resistors in the processor module (PDP-11/04,
11/34 and 11/34A) and use the M9312 as the terminator for the processor end, jumpers W-1
through W-5 must be out. All other processors require W-1 through W-5 to be in.

Jumper W-6 should be in only when the M9312 is used with PDP-11/55, 11/60, and 11/70
systems that support push-button boot.
Jumper W-7 must be in for use in all PDP-11 systems.

For PDP-11 systems with at least one peripheral device whose Unibus address lies between
7650005 and 765776g, jumper W-8 should be in. This prevents the M9312 from responding
to these addresses.

10.

11.

When the M9312 is used with a PDP-11/60 processor, jumpers W-9 and W-10 must be out,
and jumpers W-11 and W-12 must be in. For all other current PDP-11 systems, jumpers W-9
and W-10 must be in and W-11 and W-12 must be out.

Appendix C should be consulted for the switch settings (S1-1 through S1-10) required for
various boot configurations.

12.

Bootstrap ROM installation must be sequential beginning with ROM location 1 (Figure 11), for all PDP-11 systems except the PDP-11/60, whether or not the console emulator
routine is used.

1-6

13.

In PDP-11/60 systems, when only one boot ROM is used it must be installed in location 2. If
bootstraps are to be started from the console emulator routine, locations 1 and 2 must both
contain ROMs. Additional ROMs must be installed first in location 3 and then in location 4
(Figure 1-1).

1.5.1

Power-Up Boot Enable

Automatic booting on power-up can be enabled or disabled using the power-up boot enable switch
(S1-2). If this switch is set to the OFF position, the processor will execute its power-up routine nor-

mally, obtaining a new program counter (PC) from memory location 24g and a new processor status
word (PSW) from location 26g. When the switch is in the ON position during a power-up, the proces-

sor will obtain its new PC and PSW from locations 773024g and 773026g respectively. The address of

the Offset Switch Bank (S1-1 and S1-3 through S1-10) is 773024g (7732243 if the processor traps to 224g
on power-up).

The function performed by the power-up boot enable switch (S1-2) can be duplicated by an external
switch using Faston tabs TP3 and TP4. A closed switch connected to TP3 and TP4 is equivalent to S12 being ON. When MOS memory is present with battery backup, a battery status signal is generated by
the power supply. This signal should be attached to the power-up boot enable input (TP4) on the
M9312. If this status signal goes low, it indicates that the contents of the MOS memory are no longer
valid. The M9312, sensing the status of the memory, forces a boot on power-up allowing new data to
be written into memory. When TP4 is used, switch S1-2 should be off.
If the battery status input is high (logic 1) the M9312 will not automatically boot on power-up, and the
processor will obtain its new PC from location 24g, and its new PSW from location 26g.
1.5.2 Boot Selection
For power-up boot or external boot, the boot routine is selected by nine switches (S1-1 and S1-3

through S1-10) provided on the M9312. Appendix C shows switch configurations necessary for various
boot routines.
1.5.3 External Boot Switch
A device can be externally booted by using an external boot switch connected to Faston tabs TP1 and
TP2. When TP1 and TP2 are connected, BUS ACLO L will be asserted, causing the processor to
perform a power-down. Upon releasing the switch, BUS ACLO L will be unasserted, initiating a

power-up sequence in the CPU and M9312 address assertion (773000g).

1-7

CHAPTER 2
HARDWARE DESCRIPTION

2.1

GENERAL

The M9312 Bootstrap/Terminator Module, through the use of interchangeable socketed ROMs, can
be used on all PDP-11 processors. The description that follows will hold true for most applications.
Various portions of the circuitry will be analyzed separately for clarity. M9312 circuit schematics (DCS-M9312-0-1) will be referenced throughout the description.
22

ROM MEMORY

The five ROMs used for the console emulator routine, diagnostics and bootstrap programs in the
M9312 are socketed to allow reconfiguration with a minimum of effort. Only half of each ROM is used
by Unibus systems, the other half is reserved for use by other systems. The module has 512 words of
read only memory. The lower 256 words (addresses 7650003 through 765776g) are used for the storage
of ASCII console and diagnostic routines. The diagnostics (discussed further in Chapter 6) are rudimentary CPU and memory diagnostics. The upper 256 words (addresses 773000g through 773776g) are
used for storage of Bootstrap programs. These locations are divided further into four 64-word segments. If necessary more than one segment may be used for a boot program. Figure 2-1 illustrates the
segregation of the ROM:s.

765000

256 WORD CONSOLE

EMULATOR AND

LO-ROM

ROM 1K X 4

DIAGNOSTICS

765776

773000 {

| 64 WORD BOOT ROM #1

773176

ROM 612 X 4

]

773200

64 WORD BOOT ROM #2
773376

ROM 512 X 4
:

773400

{

| 64 WORD BOOT ROM #3

773576

773600

[ 64 WORD BOOT ROM #4

> HI-ROM

ROM 612 X 4

]

773776

ROM 612 X 4
J
MA-0902

Figure 2-1

ROM Segregation

2-1

2.2.1

ROM Specifications
All PROM/ROM memories used on the M9312 must meet the requirements of Digital Equipment

Corporation purchase specification 23-000A9-01 for the 512 X 4 (boot) ROMS and 23-000F1-01 for
the 1K X 4 (CPU) ROM.

2.2.2

ROM Format

The following 64-word ROM format is required when writing a device boot which requires only one
boot ROM in conjunction with the M9312 Bootstrap/Terminator Module.
1.

The boot program must begin with

a ROM header block.

Word address 243 of the ROM must remain reserved and be set to 173000g.

Word address 26g of the ROM must remain reserved and be set to 340g.

The last word of the ROM must be a CRC-16 word for the previous 63 words.

The following ROM format is required for device boots that need more than one ROM.

The first ROM follows the previously stated format.

The first word on each continued ROM must contain 177776g.

The last word of each continued ROM must contain a CRC-16 word for the previous 63
words.

Any continued ROM that would occupy word address 7732243 must reserve this location
and put 173000g in it,

Any continued ROM that would occupy word address 773226g must reserve this location
and put 340g in it.

2.2.2.1

ROM Header - As previously stated the beginning of a boot program must contain a header

section. This header section is described below:

First word

Contains the ASCII identifier which consists of two characters with a zeroparity bit that will be used by the console emulator to identify a device for
booting.

Second word

Contains the offset from this point to the next ROM header. If there is only

one ROM header, this must point to the invisible first word of the next
ROM.

Third word

Power-up entry point for unit zero, no diagnostics.

Fourth word

Power-up entry point for unit zero, diagnostic enabled.

Fifth word

Contains 000000, indicating unit O for instruction in previous word.

Sixth word

Entry point to ROM boot from the console emulator, R(0) must contain the

unit number right justified. Enter here with C bit set if diagnostics are not
desired. If diagnostics are desired, the C bit should not be set.

2-2

Seventh word

Eighth word

Address of the control/status register of the device to be booted.

Entry point when unit number of device to be booted is other than 0. This
word moves R(7) to R(4).

Ninth word

2.2.3

Contains a branch instruction (BCC) to a link to the secondary diagnostic
code.

ROM Data

2.2.3.1 ROM Data Transfer - Data stored in the ROMs is addressed four bits at a time. These four
bits are shifted through the output latches (E11 and E12) until a 16-bit word is ready to be transferred
to the Unibus. A block diagram of this procedure is shown in Figure 2-2. Table 2-1 shows the relationship between the data word bit number and the output of the ROMs. It should be noted that bits 10,
11, and 12 must be stored inverted.
2.2.3.2 ROM Data Organization - As previously stated all ROM memory on the M9312 is four bits
wide. Table 2-1 shows how 16-bit words are organized in the ROMs.

Table 2-1

ROM

Output

3
2
1
ROM Address
Data Word 1
ROM Address
Data Word 64

ROM Data Organization

Data

Word

10
9
0
23

6
5
4
1g

2
1
8
Og

3773

3763

375g

3744

14
13
12
33

Bit

Number

NOTE
Data word bits 10, 11, and 12 are stored inverted.

2.2.4

Requirements for New ROMs and Uses of the M9312

MO9312 specification A-SP-M9312-0-8 must be referred to for new uses of the M9312 and for creation
of new ROMs.
2.3 POWER-UP SEQUENCE
Typically all PDP-11 computers perform a power-up sequence each time power is applied to their CPU
module(s). This sequence is as follows.

+5 Vdc comes true.

BUS DCLO L is unasserted by power supply.

BUS ACLO L is unasserted by power supply.

BUS INIT asserts for approximately 100 ms.

2-3

+85

LATCH
TIMING

JUMPER

$ 10k

CONSOLE
EMULATOR

A<1:8>H

BYTE ADR <0:1>>

DIAGNOSTICS

E 20

LOW ROM L
=

[

DATA

D <4:7> H

14]7°
BOOT

D <1,23.8> H

ROM

LATCH

A<1:6> H

LS 374

ALLOW SWITCHES H

—

ROM

BYTE ADR <0:1> H

111

E 36

LS 374
'

BOOT 1 L

D <10:11> L,
D <0,9> H

ROM

14 Ag

DATA
LATCH

ADDRESS

SEQUENCE

A <1:6> H

BOOT

—

D <1:4>

E 12

D <12> L
D <13:16> H

ROM

TIMING

BYTE ADR <o;1>>

E33

BOOT 2 L

?13

1a]78
BOOT

A <1:6> H

ROM

BYTE ADR <0:1 >>

E 34

BOOT 3 L

S,13

—4

—

)TM

A <1:6> H

BOOT

—

ROM
#4

BYTE ADR <0:1> H )

BOOT 4 L

E 32

Y13
Figure 2-2

MA-0903

ROM Data Transfer

2-4

Processor accesses memory location 24g for new PC.

Processor accesses memory location 26g for new PSW.

Processor begins running program at new PC contents.

With an M9312 Bootstrap/Terminator Module in the PDP-11 computer system, on power-up the user
can optionally force the processor to read its new PC from a ROM memory location and the Offset
Switch Bank on the M9312 (Unibus location 773024g). A switch (S1-2) on the M9312 or an external
switch on Faston tabs TP3 and TP4 can enable or disable this feature. The new PSW will be read from
a location (Unibus location 773026g) in the M9312 memory. This new PC and PSW will then direct the
processor to a program (typically a bootstrap) in the M9312 ROM memory (Unibus memory locations
7730008 through 773776g, and 7650003 through 765776g).

If the boot enable switch (S1-2) is off, an external switch or iogic level can be used to make the
processor execute a boot program on power-up. Programs in the M9312 can also be initiated by
program jumps to their starting addresses or through the START switch feature of a programmer’s
switch console if one is available in the system.
24

POWER-UP BOOTING LOGIC

The status of every Unibus PDP-11 power supply is described by the two Unibus control lines BUS
ACLO L and BUS DCLO L. The condition of these two lines in relation to the +5 V output of the
power supply is defined by Unibus specifications as summarized in Figure 2-3.

=
wn

DC POWER

BUS DCLO L

e e
e ]

BUS ACLO L

S N P—

e e p—)

AC POWER

MA-0901

Figure 2-3

Power-Down/Power-Up Sequence

2-5

2.4.1

Power-Up and Power-Down
On the M9312, power-up sequences are detected by the circuitry shown in Figure 2-4. When +35 V first
becomes true, both BUS ACLO L and BUS DCLO L are asserted low. Assuming the power-up bootenable switch is closed a high to low transition out of E8 (pin 3) (POWER-UP BOOT L) triggers the
one shot E7 (pin 5) which asserts Unibus address lines BUS A 09 L, BUS A I0L,and BUSA 12 L
through BUS A 17 L for up to 300 ms. The logic shown in Figure 2-5 generates these Unibus addresses.

BUSDCLO L

DCLOH

SEND ACLO HO

BUS ACLOL

9 ~

POWER FAIL L

8640 \'3
E28

byt

f‘Zf

]

‘

c40

39pf

| '

0 +5V
,—

t 7N\

‘.1. A

R26 &

A28 ¢

s1.2|
-

‘ R1E

'02

7 seeNoTE

SEND ACLOH

20K 1)

20K T

NP,

TP4

ODo—

R26

8640

-0
.

12 | gg

E26

FASTON

TAB

n12'z

MMA

FASTON
TAB

_1_

/1-\043

1600pf l 47

D662

LS32 \ 8
E23

POWER-UP BOOT L —

& R32
3

ES /

;
+5
R1

30K

c37

’

__3urt+l,

VECTOR L

9602

s 1 2237
TM)

E19

oe0——T0 FINGER BD1

NOTE:

PHOTO TRANSISTOR Q2 DOES NOT
APPEAR ON THE PARTS LIST.ITIS
INTENDED FOR FUTURE USE.

BUF VECTOR L

CLEAR ADDRESS L
VECTOR H

MA-0904

Figure 2-4

Power-Up Boot Logic

2-6

BUS A16 L

A16
H

BUS A15 L

H
A15

BUS A14 L

|
L

A14 H

|
|

a1 I

-l

VECTOR L

A17 H

-d

~J
>
Ly
s el e— cEReEh GEEAED CEINEND Qe e

BUS A17L

L _-r apaspus cuE—— -F ajaEt Gl a5

BUS A13 L

VIV|V Y

—

E 30

A13 H

BUS A10 L

A12 H

A10
H

BUS A0S L

AO09 H

|
|

|
|
|
|

1 s

[*4

-l

-—b

BUS A12 L

MA-0905

Figure 2-5

Address Generation Logic

2.4.2

Processor Reads New Program Counter

During the 300 ms maximum assertion time, the central processor will be performing its power up
sequence. When the processor attempts to read a new program counter (PC) address from memory
location 24g, the address bits enabled by the one shot E7 are logically ORed to generate the address
7730245. This location is an address in the M9312 ROM space and the address of the Offset Switch
Bank, which contains the starting address of a specific routine.
2.4.3 Processor Reads New Status Word
Having obtained a new PC from location 773024g, the processor then attempts to read a new processor

status word (PSW) from memory location 26g. The address bits enabled by the one shot E7 (pin 7) are
logically ORed to generate the address 773026g which is also in the M9312 ROM address space. Once
this transfer is completed, the processor unasserts MSYN L and 150 ns (minimum) later the M9312
clears its asserted addresses. The M9312 unasserts SSYN L 800 ns after the unassertion of MSYN L
freeing the Unibus. The 300 ms one-shot (E7 pin 7) guarantees enough time for any PDP-11 processor
to complete the two memory transfers described, before releasing the address lines.
2.44

Power-Up Boot Enable Switch

The power-up boot enable switch (S1-2) can be used to disable the logic shown in Figure 2-4. With this
switch off (TP3 and TP4 open), the output of E8 (pin 3) will always be low, preventing one-shot E7
(pin 7) from ever being set on power restarts. Faston tabs TP3 and TP4 are provided to allow S1-2 to
be remotely duplicated or accept a battery status input. Note that when Faston tab TP4 is used, S1-2
must be left in the off position.
2.5

EXTERNAL BOOT CIRCUIT

The processor can be activated externally by connecting Faston tabs TP1 and TP2 or by applying a
logic ‘0’ to TP1 (Figure 2-6). This sets flip-flop E6 (pin 15), which then generates an asserted BUS
ACLO L signal on the Unibus. Upon seeing this Unibus signal, the processor will begin a power-down
routine, anticipating a real power failure. After completing this routine, the processor will then wait
for the unassertion of BUS ACLO L, at which time it will perform a power-up sequence through
location 24g and 26g.

Upon release of the external boot switch or return to logic ‘1’ at TP1, the set input to flip-flop E6 (pin
2) is unasserted and one-shot E7 on the M9312 is triggered, causing a 100 ms timeout. At the end of the
timeout, BUS ACLO L is unasserted and the 300 ms one shot E7 (pin 10) is triggered. The processor is
then forced to read its new PC and PSW from locations 773024g and 773026g respectively. The external
boot timing is shown in Figure 2-7.
2.6

POWER-UP TRANSFER DETECTION LOGIC

2.7

POWER-UP CLEAR

Any time one-shot E7 (Pin 6) is set, bus address lines [BUS A (9, 10, 12:17) L] are asserted. The circuit
shown in Figure 2-8 clears the address lines until BUS DCLO L becomes unasserted. When a boot
occurs and the new PC and PSW have been transferred, the circuitry has received two MSYN signals
and MSYN COUNT L goes low. At this time the bus address lines are unasserted. If the above
transfers do not occur within 300 ms, the address lines are unasserted.

The circuit shown in Figure 2-9 holds the external boot circuit clear for approximately 8 ms after the dc
supply voltage exceeds the threshold voltage of 3.0 to 4.5 V. This is to ensure that the external boot
circuit does not cause a boot on power-up. The circuit uses the M9312’s dc supply voltage to determine
if a real power failure has occurred, because an assertion BUS ACLO L and BUS DCLO L may occur
without a real power failure.

2-8

/"'l

bp R22
> 20K

—_——

|
|

—'
|

TAB

D2 t

' \’ |'

|
|
|

|
|

be—ed

R23
1K

D662

TP2

FAsSTON

TaB

oy
1K

R16

< 10K

30K

8640

E26

+5V

S R18

\s'.\_}f

14
AV

+5v

Q1
k<4Ma. 2 7/ SEE
NOTE

20K

TP1
FASTON

/ P"

R29 &>

+5v

10 UF +

Ca2 TN

1500PF

9602 O
E7

q
SR31

::47.(

=
=

2
4

LS76

Olcx

£6

O 14

6
8881

BUS ACLOL

+5V ——K
16

)

8881

POWER-UP CLEAR L
NOTE:
PHOTO TRANSISTER Q1 DOES NOT APPEAR

ON THE PARTS LIST. IT IS INTENDED FOR
FUTURE USE.

POWER-UP BOOT L

Ls32 \ 8
E23

MA-0906

Figure 2-6

External Boot Logic

2-9

H 10 uSEC

SWITCH CLOSURE

!
|

BUSACLO L

| 100 MSEC | [&—

_.‘

M9312 ONE SHOT
TIME OUT

|->prOCESSOR l

| PROCESSOR PERFORMS

|- POWER

I POWER-UP

l-openroams

L, oown

MA-0907

Figure 2-7

External Boot Timing

(——— VECTOR H
CLEAR ADDRESS L

1914, 1876 5
MSYN H

|
124

11
_.LL

POWER FAIL L
10
)

sea0TM\

) LES18:
> 11

8
MSYN COUNT L

MA-0908

Figure 2-8

Power-Up Transfer Detection Logic

2-10

POWER-UP CLEAR L

+5V

10K

R37 3

na2
4

20K 9
p

1.33K 3

R17

26195:

E26

s
E26

At 10
T ca

MA-0909

Figure 2-9

2.8

Power-Up Clear Circuitry

ADDRESS DETECTION LOGIC

2.8.1

M9312 Address Space

Address detection logic on the M9312 detects Unibus addresses within the address space 7730005
through 7737763 and 7650008 through 765776g. It also recognizes the specific address 773024g. Some
processors, such as the PDP-11/60, trap to locations 224g and 2265 on power-up for their new PC and
PSW. The M9312 also recognizes the specific address 773224g. Figure 2-10 illustrates the M9312’s
address detection logic.
2.8.2 Memory Access Constraints
Upon receiving a recognized Unibus address and BUS MSYN, the M9312 ROM data output is transferred to the Unibus data lines (BUS D00 L through BUS D15 L) and BUS SSYN L is enabled.

Conditions which must be met before transferring the ROM data and returning BUS SSYN are as
follows:
1.

Detection of the Unibus address 773XXXg or 765X XXg where XXXg is any even address.
Installing W-8 disables detection of address 765XXXg.

Transfer being performed is a DATI operation where BUS C1 L is not asserted.

An asserted BUS MSYN L control signal has been obtained.

2.83 LO ROM ENA H Jumper
LO ROM ENA H jumper W-8 allows the user to disable the M9312 detection of Unibus addresses
7650008 through 765776g. Disabling the detection of these addresses (W-8 in) becomes essential when
that memory space is being used by other peripheral device(s) in the system. Users should note that
when detection of these addresses is disabled the console emulator and diagnostic routines in the
M9312 are eliminated (not addressable).

2-11

ALLOW SWITCHES ROM

ADDRESSES

HIGH

ENABLE

A <8:1> H

ROM H

ROM L

| JUMPERS

JUMPERS

ALLOW

XXX

ouT

XXX

ouT

W-9 AND W-10 | W-11 ANDW-12 |

ALLOW

SWITCHESL

| SWITCHESH

024

ouT

DEFAULT

ouT

224

ouT

DEFAULT

ouT

BOOT SEL H

' HI-LO 4 1 l
L

A <9:17> H

Low

| 74LS 156FA3 [D—BOOTA4
4
L

3—

|11
L ALLOW SWITCHES L*

ROM 2[4,
1}—— ALLOW SWITCHES H*

FAOO— BOOT 1 L

E21

AgH —3—' $1 g22

E31

SWITCHES

FAT 07 BooT 2L

215

4}—— ALLOW SWITCHES L

ALLOW 3110 aj 10w SWITCHES H

HIGH ROM H

Ar1-Ag

14 A8 A

A DS BooT 3L

A <1:8> H

A5-Aq

A7H-—12- SO

LO ROM

STBA

ENAH

AAA

ENABLE

ENABLE ROM L

+
n

HIGH ROM L

HI-LO ROM DECODER
ADDRESSES | LO ROM

BOOT

LOW

HIGH

A <17:9>

ENA H

SELH

ROML

| ROMH

7656XXX

765X XX

773XXX

DEFAULT

74L.5155

BOOT1L | BOOT2L | BOOT3L | BOOT4 L

g';’:nete HIGH

:fn;iu

Ag | Ay

X | X

# THESE OUTPUTS ARE USED WHEN MODULE IS BEING USED WITH PROCESSORS THAT OBTAIN THEIR NEW PC AT
LOCATION 224(g) AND PSW AT 226(g).

MA-0910

Figure 2-10

Address Detection Logic

2-12

29 ADDRESS OFFSET SWITCH BANK
As previously mentioned, on a power-up boot or an external boot,
the M9312 forces the processor to
obtain its new PC from location 7730243 instead of location 243. When
the M9312 address detection
logic decodes address 773024g, it enables (via ALLOW SWITCHES L) the
Address Offset Switch
Bank (Figure 2-11). The contents of the switches S1-1 and S1-3
through S1-10 combined with the
contents of the specified address in M9312 ROM memory produce a

new PC for the CPU. The new PC

will point to HI or LO ROM memory depending upon the position of the
switch S1-1. With S1-1 OFF
the new PC will point the processor to a starting address of a bootstra
p program (addresses 7730008
through 773776g) in M9312 ROM memory. When S1-1 is ON, the new
PC will point the processor to a
starting address of a program in the M9312 console emulator and
diagnostic ROM (addresses 7650003
through 765776g). Several programs can be included in M9312 memory
with any one being user selectable through the Address Offset Switch Bank. Appendix C shows the
relationship between the switches
and the devices to be booted.

ALLOW SWITCHES L

+5
R7

10K

o o—
$1-8

20041

$1-9

o—

$1-10

R12

)

1Y4 12

IV
,

2v1

R10

"‘W‘"I
10K

—0” o—

$1-6

| .4

—()2A2

2y2

10K I 16

o o—
$1-6

—(l2A3

2Y3

0K | ..

o o—

—l2A4

§1-7

1Y3

10K I 1
- 21

$1-4

SWITCHES L

—o" 0—f

7] LAY

o o—

17 LA

—(143

10K

-—;1/;-—-

201142

RS
10K

310K Q
1

ALLOW

R20

S1-1

10K |

o o-

szgo

2v4

D1 H

D12
L

D8 H

10
g

]

E15

D12 H

D11 L

D7 H

s |] E18 ) —

b1 n

D6 H

D10 L

1])

E16

D10 H

DS H

D4 H

162G

OFFSET SWITCHES AND CORRESPONDING BUS
ADDRESS BITS
S1 SWITCHES

CORRESPONDING BUS
ADDRESS BITS

|10}

1211110}

X ] X

BINARY VALUE OF SWITCHES
OCTAL VALUE OF SWITCHES

*NO SWITCH IS PROVIDED FOR SETTING BIT 0, THEREFOR

E ONLY EVEN ADDRESS

(FOR THE PC) MAY BE SET.

MA - 0911

Figure 2-11

Address Offset Switch Bank

2-13

2.10 M9312 TERMINATOR
The terminator section of the M9312 consists of four resistor pack circuits, each containing the
required pull-up (178 ohms) and pull-down (383 ohms) resistors for proper Unibus termination. Since
PDP-11/04, 11/34 and 11/34A processors contain Bus Grant pull-up resistors, and other processors
do not, the M9312 allows a choice of whether or not to pull up the BUS grant lines. When jumpers W1 through W-5 are in, these lines are pulled up; when these jumpers are out, the grant lines are not
pulled up.

2-14

CHAPTER 3

CONSOLE EMULATOR

3.1

GENERAL

The console emulator routine is available when a ROM which contains the routine is used on the
M9312. This ROM is placed in the console emulator and diagnostic ROM socket shown in Figure 1-1.
3.2 USING THE CONSOLE EMULATOR
The system will execute a console emulator power-up routine when power is supplied to the system, the

boot switch is pressed, or the correct address from Table 3-1 is loaded and started, provided jumper W-

8 is out, W-7 is in, and the Address Offset Switch Bank is set according to Table 3-1. If diagnostics are
selected, secondary diagnostics (tests 6 and 7) will run after the console emulator routine, just before a
boot. Primary diagnostic tests 1 through 4 are always executed before the console emulator routine.
Completion of the primary diagnostic tests will be followed by the register display routine. The contents of RO, R4, R6, and RS will be printed out on the terminal. An @ sign will be printed at the
beginning of the next line of the terminal, indicating that the console emulator routine is waiting for
input from the operator.

Table 3-1

Console Emulator Switch Requirements
Address Offset Switch Bank S1

Console Emulator
with Diagnostics

Octal
Addresst

165020

ON | -

OFF |OFF | OFF} OFF|

165144

ON|

OFF|OFF|ON

2* | 3

|OFF}

OFF|OFF

Console Emulator
without

Diagnostics

|ON | OFF|OFF|

|OFF

*When switch S1-2 is ON, power-up boot is enabled; when S1-2 is OFF power-up boot is disabled.

TThe octal address can be loaded and program started from a programmer’s console or switch register, if a
power-up start or external boot start from the M9312 is not used.

The following symbols will be used in this discussion.
<SB>:
<CR>:

Space bar
Carriage return key

Any octal number 0-7

3-1

The four console functions can be exercised by pressing keys, as follows:
Function

Keyboard Strokes

Load Address
Examine

L<SB> XXXXXX <CR>
E<SB>

Deposit

D<SB> XXXXXX <CR>

The first digit typed will be the most significant digit. The last digit typed will be the least significant

R SCINE

digit. If an address or data word contains leading zeros, these zeros can be omitted when loading the
address or depositing the data. An example using the load, examine, deposit, and start functions
follows. Assume a user wishes to:
Load address 700
Examine location 700
Deposit 777 into location 700
Examine location 700
Start at location 700.

To accomplish this, the procedure below must be followed.

1.
2.
3.
4.
5.
6.

Operator Input

Terminal Display

Turns on power
L<SB> 700<CR>

XXXXXX XXXXXX XXXXXX XXXXXX
@L 700

E<SB>
D<SB> 777<CR>
E<SB>
S<CR>

@E 000700 XXXXXX
@D 777
@E 000700 000777
@S

NOTE
The console emulator routine will not work with odd
addresses. Even addresses must always be used.

3.2.1

Successive Operations

3.2.1.1 Examine - Successive examine operations are permitted. The address is loaded for the first
examine only. Successive examine operations cause the address to increment and will display consecutive addresses along with their contents. For example, to examine addresses 500-506, the following
procedure may be used.
Operator Input

Terminal Display

L<SB>500<CR>
E<SB>
E<SB>
E<SB>
E<SB>

@L 500
@E 000500 XXXXXX
@E 000502 XXXXXX
@E 000504 XXXXXX
@E 000506 XXXXXX

3-2

3.2.1.2 Deposit - Successive deposit operations are permitted. The procedure is identical to that used
with examine. For example, to deposit 60 into location 500, 2 into location 502, and 4 into location
504:

3.2.1.3

Operator Input

Terminal Display

L<SB>500<CR>
D<SB>60<CR>
D<SB>2<CR>
D<SB>4<CR>

@L 500
@D 60
@D 2
@D 4

Alternate Deposit-Examine Operations — This mode of operation will not auto-increment the

address. The location addressed will contain the last data which was deposited. For example, to load
address 500 and deposit 1000, 2000, and 5420 with examine operations after every deposit:
Operator Input

Terminal Display

L<SB>500<CR>

@L 500

D<SB>1000<CR>

@D 1000

E<SB>
D <SB>2000<CR>
E<SB>
D<SB> 5420<CR>
E<SB>

@E 000500001000
@D 2000
@E 000500 002000
@D 5420
@E 000500005420

3.2.1.4 Alternate Examine-Deposit Operations - If an examine is_the first instruction after a load
sequence and is alternately followed by deposits and examines, the address will not be incremented,
and the address will contain the last data which was deposited. The prior example applies to this
operation, and with the exception of the order of examine and deposit, the end result is the same.
3.2.2 Limits of Operation
The M9312 console emulator can directly manipulate the lower 28K of memory and the 4K 1/0O page.
See Chapter S for an explanation of techniques required to access addresses above the lower 28K.
3.3

BOOTSTRAPS STARTED FROM THE CONSOLE EMULATOR

Once the @ symbol has been displayed in response to system power-up, or pressing the boot switch, the
system is ready to boot a device the operator selects. The procedure is as follows.
1.

Load paper tape, magtape, disk, etc., into the peripheral to be booted, if required.

Verify that the peripheral indicators signify that the peripheral is ready (if applicable).

Find the boot command code in Table 3-2 that corresponds to the peripheral to be booted.
Type the code obtained from the table. (The @ sign will be returned at this point if the
correct boot ROM has not been installed, or if a non-existent code is typed in. If the register

display is printed first, the emulator is indicating that at least one boot ROM socket is
available for boot ROM installation.)
4.

Ifthere is more than one unit of a given peripheral, type the unit number to be booted (0-7).

If no number is typed, the default number will be O.
5.

Type <CR>, which initiates the boot.

3-3

Table 3-2

Boot Command Codes
Command

Interface

Device

Description

Code

RL11
RX11
RKI11C,D
TCl11
RX211
RK611
TMI11/A11/B11

RLO1
RXO01
RKO03,05/05J
TUS5/56
RX02
RKO06/07
TS03,TU10

DL
DX
DK
DT
DY
DM
MT

RH11/RH70
TAll
PCl11
DL11-A
RP11
RHI11/RH70

TU16,TMO02
TU60

Disk Memory
Floppy disk system
DECpack disk
Dual DECtape
Double density floppy disk system
Disk drive
Magnetic tape (9 track,
800 bits/in, NRZ)
Magnetic tape
Dual magnetic tape
High speed reader
Low speed reader
Moving head disk
Moving head disk

MM
CT
PR
T
DP
DB

Fixed head disk

RP02/03
RP04/05/06
RMO02/03

RHI11/RH70

RS03/04

Before booting a device always remember:

The medium (paper tape, disk, magtape, cassette, etc.) must be placed in the peripheral to be
booted prior to booting.

The machine will not be under the control of the console emulator routine after booting.

The program which is booted in must:

3.3.1

Be self-starting or

Allow the user to load another program by using the CONT function or

Bestartable from the console emulator or switch register after having been booted in.

Booting the High-Speed Reader Using the Console Emulator

To load the CPU diagnostic for a PDP-11/34 computer system with a high-speed reader, perform the

following procedure.

Place the HALT/CONT switch in the CONT position.

Obtain a @ symbol by either turning on system power or actuating the boot switch. (R0, R4,

Place the absolute loader paper tape (coded leader section) in the high speed reader.

Type PR<KCR>.

SP, and old PC will be printed prior to the @ symbol.)

The absolute loader tape will be loaded and the machine will halt.

3-4

Remove the absolute loader and place the leader of the program, in this case a CPU diagnostic, in the reader.

Move the HALT/CONT switch to HALT and then return it to CONT. The diagnostic will
be loaded and the machine will halt (normal for this program; non-diagnostic programs may
or may not be self-starting.)

If program is not self-starting, activate the BOOT/INIT switch. This will restart the console
emulator routine.

Using the console emulator, deposit desired functions into the software switch register (a
memory address) location. (See the diagnostic for the software switch register’s actual location and significance.)

Using the console emulator, load the starting address, and start the program as described
earlier in this section.

3.3.2

Booting a Disk Using the Console Emulator

To boot the system’s RKO5 disk, which contains the CPU diagnostics that you want to run, perform

the following procedure:
.

Verify that the HALT/CONT switch is in the CONT position and the write lock switch on
the RK11 peripheral is in the ON position.
Turn on system power or press the console boot switch. The system terminal displays RO,
R4, SP and old PC in octal numbers followed by a @ symbol on the next line.
Place the disk pack in drive 0.

When the RKO05 load light appears, the system is ready to be booted.
Type DK<CR>.

This causes the loading of the bootstrap routine into memory and the execution of that
routine.

The program should identify itself and initiate a dialogue (which will not be discussed here).

34 RECOVERING FROM ERRORS IN THE CONSOLE EMULATOR ROUTINE
Table 3-3 describes the effects of entering information incorrectly to the console emulator routine. The
following symbols are used in the table.

(9)

Represents a non-octal number (8 or 9)

(Y)

Represents:

All keys (other than numerics) which are unknown.

Keys which are known but do not constitute a valid code in the context which they are
entered.

Refer to previous sections for a discussion of the correct method operating the console emulator
routine.

3-5

Table 3-3

Error

Deposit Errors: Useful Examples

Result

Remedy

Operator

L was followed by a key | Terminal display will
other than (SB).
immediately return an @ to
signify an unknown code. No
address is loaded.

Try again

L(Y)

@L
@

An illegal (non octal)
Upon receipt of the illegal
number (8 or9) is typed | number, the Console
after the correct load
Emulator will ignore the
entrance, within an
entire address and return an
otherwise valid number. | @.

Try again

L<SB>
XXX9

@L XXX9
@

An alphabetic key is
typed after the correct
load entrance within an
otherwise valid number.

Try again

L<SB>
XXXY

@L XXXY
@

Same as illegal number.

The most significant
An address will be loaded.
octal number in a six bit |However, the state of the
address is greater than | most significant address bit

one.

| Terminal

Try againif |L<SB>
@L 6XXXXX
required
6XXXXX | @
<CR>
(address loaded

will be determined by bit 15

0XXXXX)

only:
2=0
3=1
4=0
5=1
6=0
717=1

An unwanted but legal | Unwanted address will be
octal number is loaded.
|loaded.

Try again

An extra (seventh) octal | The loaded number will be
number is typed.
incorrect. The system will
accept any size number but
will only remember the last
six characters typed in.

Try again

L<SB>
@L 1XXXXX
IXXXXX | @
<CR>
(Actually Loads
XXXXXX)

A memory location
No errors will result unlessa
higher than the highest | deposit, examine, or start is
memory location
attempted, causing Bus to
available in the machine | hang up.
is loaded.

| Try again

L<SB>
L IXXXXXX
IXXXXX | @
<CR>

L, <SB> and number | Machine will wait
were entered correctly,
|indefinitely for <CR>. @
<CR> was not entered. | will not be returned

Type
<CR>

3-6

L<SB>
XXXXX
<CR>

@L XXXXXX
|@

Table 3-3 Deposit Errors: Useful Examples (Cont)

Error

Result

Remedy

Operator

Terminal

Examine or start is
attempted to a memory

The system will hang up.

Actuate the | EXSB> or | @E or @S (stops
boot switch | SKCR>
responding)

location which is higher
than the highest available

memory location in the
machine (I/O page can
be examined) or to an
odd memory location.

Examine is performed

An examine operationofan | Tryagain

Start is performed

Start at an unknown location | Depress the

without loading an

will occur.

without loading an
address prior to first
examine.

unknown address will be
or boot if
performed. It is possible that | system
the machine may attempt to | hangs up.
examine an address which
does not exist. If this happens
the system will hang-up.

| E<SB>

boot

address prior to
starting.

switch,
load
correct

address
and then
start.

D was followed by a key | Terminal display will
other than a space or a
immediately return a @ to
valid second character
signify an unknown code. If
of a boot command
the register display is printed

Try again

Deposit is attempted to | The system will hang up
a memory location
when <CR> is executed.
which is higher than the
highest available
memory location in the
machine (with the
exception of the I/O

Depress the
boot switch
and start
over again.

code.

before the @ sign, the
emulator is indicating that at
least one socket is still
available for a boot ROM.

page).

3.7

| D(Y)

@D(Y)
@

Table 3-3 Deposit Errors: Useful Examples (Cont)

Error
o

Result

Remedy

Operator

Terminal

——

Deposit is performed

without loading an

and lost

Data will be written over | a. Immediately

address or knowing

following

what address has been

the error,

previously loaded.

perform an
examine to
determine
the
location
which was
accessed.
Restore
original
contents if
known.

Deposit into an odd
address is attempted.

b. Machine might hang up.

|b. Actuate
the boot
switch.

The system will hang up
when <CR> is executed.

Actuate the
boot
switch.

Escape Route

If an entry has not been completed and the user realizes that an incorrect or unwanted character has
been entered, press the rubout or delete key. This action will void the entire entry and allow the user to
try again.
Machine “Hang-Up”

Machine has “hung-up” (halted or gone into program loop) if the terminal does not respond to any
keyboard entry.

CHAPTER 4
BOOTSTRAPPING

The routines to bootstrap a device typically read in the first sector, block, or 512 words from the device
into location 0 through 512 of memory. The exception to this rule is the paper tape boot. The paper
tape boot is unique in that it can do no error checking and the secondary bootstrap (the absolute
loader, for example) is read into the upper part of memory. The actual locations loaded by the paper
tape boot are partially determined by the secondary bootstrap itself and by the size routine which
determines the highest available memory address within the first 28K. The flexible disk (or floppy)
reads sector 1 on track 1 into consecutive locations starting at 0. The magnetic tape boots read the
second block into consecutive locations starting with 0. If no errors are detected in the device, the
bootstraps normally transfer control to location 0 in order to execute the secondary bootstrap just
loaded. The only exception to this starting address concerns the paper tape boots. They transfer control to location XXX374, where XXX is determined initially by the size routine to be at the top of
memory. This is where the absolute loader has just been loaded.

If a device error is detected, a reset will be executed and the bootstrap will try again. The bootstrap will
be retried indefinitely until it succeeds without error unless the user (operator) intervenes. The advantage of retrying the boot is that if a particular device being booted is not on-line or not loaded, perhaps
because of a power failure, the boot will give the device a chance to power-up (essential for disks).
A magnetic tape transport, however, will not automatically reload itself after a power failure and

restart. This situation requires user intervention. The user must reload the magtape and bring it back
on-line, at which time the magtape bootstrap, which will have been continually attempting to boot the
tape, will succeed.

CHAPTER §
EXTENDED ADDRESSING

5.1 GENERAL
This chapter applies to use of the M9312 in PDP-11 systems which have no console. When the memory
of a PDP-11 system is extended beyond 28K, the processor is able to access upper memory through the
memory management system. However, the console emulator normally allows the user to access only

the lower 28K of memory. This chapter provides an explanation of the method by which the user can
gain access to upper memory in order to read or modify the contents of any location. The reader
should be familiar with the concepts of memory management in the KD11-E processor.
5.2 VIRTUAL AND PHYSICAL ADDRESSES
Addresses generated in the processor are called virtual addresses, and will be 16 bits in length. Physical
addresses refer to actual locations in memory. They are asserted on the Unibus and may be up to 18
bits in length (for 128K memories).
5.3 ADDRESS MAPPING WITHOUT MEMORY MANAGEMENT
With memory management disabled (as is the case following depression of the boot switch), a simple
hardware mapping scheme converts virtual addresses to physical addresses. Virtual addresses in the 0
- to 28K minus 2 range are mapped directly into physical addresses in the range from 0 to 28K minus 2.
Virtual addresses on the I/O page, in the range from 28K to 32K minus 2 (160000g to 177776g), are
mapped into physical addresses in the range from 124K to 128K minus 2, or the last 4K of memory.
5.4 ADDRESS MAPPING WITH MEMORY MANAGEMENT
With memory management enabled, a different mapping scheme is used. In this scheme, a relocation
constant is added to the virtual address to create a physical or “relocated” address.
Virtual address space consists of eight 4K banks where each bank can be relocated by the relocation
constant associated with that bank. The procedure specified in this section allows the user to:
1.

Create a virtual address to type into the load address command.

Determine the relocation constant required to relocate the calculated virtual address into the
desired physical address.

Enable or disable the memory management hardware.

5.5 CREATION OF A VIRTUAL ADDRESS
The easiest way to create a virtual address is to divide the 18-bit physical address into two separate
fields - a virtual address and a physical bank number. The virtual address is represented by the lower
13 bits and the physical bank by the upper S bits. The lower 3 bits of the physical bank number (bits 13,
14, 15) represent the virtual bank number (Table 5-1). Thus if bits 13, 14, and 15 are all Os, the virtual
bank selected is 0. The user should calculate the relocation constant according to Table 5-2. He can
then deposit this constant in the relocation register associated with virtual bank 0 (Table 5-1).

5-1

Virtual Address

Table S-1

Unibus Address Assignments

" Virtual
Bank

Relocation
Register

Descriptor
Register

160000-177776
140000-157776
120000-137776

7
6
5

172356
172354
172352

172316
172314
172312

100000-117776

172350

172310

060000-077776
040000-057776
020000-037776
000000-017776

3
2
1
0

172346
172344
172342
172340

172306
172304
172302
172300

Table 5-2

Relocation Constants

Physical
Bank Number

Relocation
Constant

Physical
Bank Number

Relocation
Constant

37
36
35
34
33
32
31
30
27
26
25
24
23
22
21
20

007600
007400
007200
007000
006600
006400
006200
006000
005600
005400
005200
005000
004600
004400
004200
004000

17
16
15
14
13
12
11
10
7
6
5
4
3
2
1
0

003600
003400
003200
003000
002600
002400
002200
002000
001600
001400
001200
001000
000600
000400
000200
000000

One relocation register exists for each of the eight virtual banks. In addition to the relocation registers,
each bank has its own descriptor register which provides information regarding the types of access
allowed (read-only, read or write, or no access).

The memory management logic also provides various forms of protection against unauthorized access.
The corresponding descriptor register must be set up along with the relocation register to allow access
anywhere within the 4K bank.

For example, assume a user wishes to access location 533720g. The normal access capability of the
console is 0 to 28K. This address (533720) is between the 28K limit and the I/O page (760000-777776),
and consequently must be accessed as a relocated virtual address, with memory management enabled.
The virtual address is 13720 in physical bank 25 and is derived as follows.

5-2

All locations in bank 25 may be accessed through virtual addresses 000000-017776. The relocation and
descriptor registers in the processor are still accessible since their addresses are within the I/O page.
(Note that access to the I/O page is not automatically relocated with memory management, while
access to the I/O page is automatically relocated when memory management is not used.)

The relocation constant for physical bank 25 is 005200. This constant is added in the relocation unit to
the virtual address, as shown, yielding 533720.
013720
520000

Virtual address
Relocated constant (Table 5-2)

533720

Physical address

The Unibus addresses of the relocation registers and the descriptor registers are given in Table 5-1. The
relocation constant to be loaded into the relocation register for each 4K bank is provided in Table 5-2.
The data to be loaded in the descriptor register to provide read/write access to the full 4K is always
077406.

The Unibus address of the control register to enable memory management is 177572. This register is
loaded with the value 000001 to enable memory management, and loaded with 0 to disable it.

To complete the example previously described (accessing location 533720), the console routine would
be as follows:

172340

5200

172356

7600

172300

/Access descriptor register, virtual bank 0.

77406

/Deposit code for read/write access to 4K.

172316

/Access descriptor register, virtual bank 7.

77406

/Deposit code for read/write access to 4K.

177572

/Access control register.

13720

/Access relocation register for virtual bank O.
/Deposit code for physical bank 25.
/Access relocation register for virtual bank 7.

/Deposit code for the I/O page.

/Enable memory management.
/Load virtual address of location desired.
/Examine the data in location 533720.

/Data will be displayed.
5-3

5.6

CONSTRAINTS

Loading a new relocation constant into the relocation register for virtual bank 0 will cause virtual
addresses 000000-017776 to access the new physical bank. A second bank can be made accessible by
loading the relocation constant and descriptor data into the relocation and descriptor registers for
virtual bank 1 and accessing the location through virtual address 020000-037776. Seven banks are
accessible in this manner, by loading the proper constants, setting up the descriptor data, and selecting
the proper virtual address. Bank 7 (I/O page) must remain relocated to physical bank 37 as it is
accessed by the CPU to execute the console emulator routine.
Memory management is disabled by clearing (loading with 0s) control register 177572. It should always be disabled prior to typing a boot command.

The start command automatically disables memory management and the CPU begins executing at the
physical address corresponding to the address specified by the previous load address command. Pressing the boot switch automatically disables memory management. The contents of the relocation registers are not modified.
The HALT/CONT switch has no effect on memory management.

5-4

CHAPTER 6
DIAGNOSTICS

6.1

GENERAL
The diagnostics in this chapter are standard for the M9312 when used in all PDP-11 computers.
Paragraph 6.2 explains the diagnostics used in lower order systems such as the PPD-11/04 and 11/34,
where the console emulator routine and diagnostics are to be used. An explanation of switch settings
(S1-1, and S1-3 through S1-10) necessary to select specific routines is contained in Paragraphs 2.9 and
3.1. Paragraph 6.3 explains the diagnostics used for PDP-11/60 and 11/70 computers. No console
emulator routine is present when used with these systems.

NOTE
LO ROM ENA H jumper W-8 must be out in order

to run diagnostics and/or the console emulator routine.
6.2 DIAGNOSTICS
An explanation of the seven CPU and memory diagnostic tests follows. Three types of tests are included in the M9312 diagnostics:
1.
2.
3.

Primary CPU tests
Secondary CPU tests
Memory test

Primary CPU Tests
The primary CPU tests exercise all unary and double operand instructions with all source modes.
These tests do not modify memory. If a failure is detected, a branch-self (BR) will be executed. The run
light will stay on, because the processor will hang in a loop. If no failure is detected in tests 1-4, the
processor will emerge from the last test and enter the register display routine (console emulator).
Test 1 — Single Operand Test - This test executes all single operand instructions using destination mode
0. The basic objective is to verify that all single operand instructions operate; it also provides a cursory
check on the operation of each instruction, while ensuring that the CPU decodes each instruction in
the correct manner.
Test 1 tests the destination register in its three possible states: zero, negative, and positive. Each in-

struction operates on the register contents in one of four ways.
1.

Data will be changed via a direct operation, i.e., increment, clear, decrement, etc.

Data will be changed via an indirect operation, i.e., arithmetic shifts, add carry, and subtract
carry.

6-1

Data will be unchanged, but operated upon via a direct operation, i.e., clear a register
already containing zeros.

Data will be unchanged but examined via a non-modifying instruction (TEST).
NOTE
When operating upon data in an indirect manner, the

data is modified by the state of the appropriate con-

dition code. Arithmetic shift will move the C bit into
or out of the destination. This operation, when performed correctly, implies that the C bit was set correctly by the previous instruction. There are no

checks on the data integrity prior to the end of the
test. However, a check is made on the end result of
the data manipulation. A correct result implies that
all instructions manipulated the data in the correct
way. If the data is incorrect, the program will hang in
a program loop until the machine is halted.

Test 2 — Double Operand, All Source Modes - This test verifies all double operand, general, and logical
instructions, each in one of the seven addressing modes (excludes mode 0). Thus, two operations are

checked: the correct decoding of each double operand instruction, and the correct operation of each
addressing mode for the source operand.
Each instruction in the test must operate correctly in order for the next instruction to operate. This
interdependence is carried through to the last instruction (bit test) where, only through the correct
execution of all previous instructions, a data field is examined for a specific bit configuration. Thus,
each instruction prior to the last serves to set up the pointer to the test data.
Two checks on instruction operation are made in test 2. One check, a branch on condition, is made
following the compare instruction, while the second is made as the last instruction in the test sequence.

Since the GO-NO GO tests reside in ROM memory, all data manipulation (modification) must be
performed in destination mode O (register contains data). The data and addressing constants used by
test 2 are contained within the ROM.
It is important to note that two different types of operations must execute correctly in order for this
test to operate:

Those instructions that participate in computing the final address of the data mask for the
final bit test instruction.

Those instructions that manipulate the test data within the register to generate the expected
bit pattern.

Detection of an error within this test results in a program loop.
Test 3 — Jump Test Modes 1, 2, and 3 - The purpose of this test is to ensure correct operation of the
jump instruction. The test is constructed so that only a jump to the expected instruction will provide
the correct pointer for the next instruction.

There are two possible failure modes that can occur in this test:

The jump addressing circuitry will malfunction causing a transfer of execution to an incorrect instruction sequence or non-existent memory.

Thejump addressing circuitry will malfunction in such a way as to cause the CPU to loop.

The latter case is a logical error indicator. The former, however, may manifest itself as an after-the-fact
error. For example, if the jump causes control to be given to other routines within the M9312, the
interdependent instruction sequences would probably cause a failure to eventually occur. In any case,
the failing of the jump instruction will eventually cause an out of sequence or illogical event to occur.
This in itself is a meaningful indicator of a malfunctioning CPU.
This test contains a jump mode 2 instruction that is not compatible across the PDP-11 line. However,

it will operate on any PDP-11 within this test, due to the unique programming of the instruction within
test 3. Before illustrating the operation, it is important to understand the differences of the jump mode
2 between machines.

On the PDP-11/05, 11/10, 11/15, and 11/20 processors, for the jump mode 2 [JMP(R) +C, the register
(R) is incremented by 2 prior to execution of the jump. On the PDP-11/04, 11/34,11/35,11/40, 11/45,
11/50, 11/55, and 11/70 processors, (R) is used as a jump address and incremented by 2 after execution of the jump.
In order to overcome this incompatability, the

JIMP(R)+ is programmed with (R) pointing back on the

jump itself. On PDP-11/05, 11/10, 11/15, and 11/20 processors, execution of the instruction would
cause (R) to be incremented to point to the following instruction, effectively continuing a normal
execution sequence.
On the PDP-11/04, 11/34, 11/35, 11/40, 11/45, 11/50, 11/55, and 11/70 processors, the use of the
initial value of (R) will cause the jump to loop back on itself. However, correct operation of the autoincrement will move (R) to point to the next instruction following the initial jump. The jump will then
be executed again. However, the destination address will be the next instruction in sequence.
Test 4 - Single Operand, Non-Modifying Byte Test — This test focuses on the one single operand

instruction, the TST. TST is a special case in the CPU execution flow since it is a non-modifying
operation. Test 4 also tests the byte operation of this instruction. The TSTB instruction will be exe-

cuted in mode 1 (register deferred) and mode 2 (register deferred, auto-increment).
The TSTB is programmed to operate on data which has a negative value most significant byte and a

zero (not negative) least significant byte.
In order for this test to operate properly, the TSTB on the low byte must first be able to access the even
addressed byte and then set the proper condition codes. The TSTB is then re-executed with the autoincrement facility. After the auto-increment, the addressing register should be pointing to the high byte
of the test data. Another TSTB is executed on what should be the high byte. The N bit of the condition
codes should be set by this operation.

Correct execution of the last TSTB implies that the auto-increment recognized that a byte operation
was requested, thereby only incrementing the address in the register by one, rather than two. If the
correct condition code has not been set by the associated TSTB instruction, the program will loop.

Upon successful completion of test 4, the register display routine is enabled. This routine will be
followed by a prompt character (@) on the next line.
An example of a typical printout follows.

XXXXXX

@
R6

Prompt

(Stack

(Old PC)

Character

Pointer)

NOTES
X signifies an octal number (0-7).

Whenever there is a power-up routine or the boot

switch is released on PDP-11/04 and PDP11/34 machines, the PC at this time will be
stored in RS. The contents of RS are then printed
as the old PC shown in the example.
3.

The prompting character string indicates that
diagnostics have been run and the processor is
operating.

Secondary CPU and Memory Tests

The secondary CPU tests modify memory and involve the use of the stack pointer. The JMP and JSR
instructions and all destination modes are tested. If a failure is detected, these tests, unlike the primary
tests, will execute a halt.

Secondary CPU and memory diagnostics are run immediately after test 4 when they have been evoked
by means other than the console emulator, provided that the correct microswitches have been set. If
the console emulator has been entered at the completion of test 4, the secondary CPU and memory
diagnostics will be run when the appropriate boot command is given.
The M9312 reacts to a false boot command (an invalid address code) by returning to the console
emulator routine. This should not be interpreted as a diagnostic test failure.

Test 6 — Double Operand, Modifying, Byte Test - The objective of this test is to verify that the doubleoperand, modifying instructions will operate in the byte mode. Test 6 contains three subtests:
1.
2.
3.

Test source mode 2, destination mode 1, odd and even bytes
Test source mode 3, destination mode 2
Test source mode O, destination mode 3, even byte.

The move byte (MOVB), bit clear byte (BICB), and bit set byte (BISB) are used within test 6 to verify

the operation of the modifying double-operand functions.

Since modifying instructions are under test, memory must be used as a destination for the test data.

Test 6 uses location 500 as a destination address. Later, in test 7 and the memory test, location 500 is
used as the first available storage for the stack.

6-4

Note that since test 6 is a byte test, location 500 implies that both 500 and 501 are used for the byte
tests (even and odd, respectively). Thus, in the word of data at 500, odd and even bytes are caused to be
all Os and then all 1s alternately throughout the test. Each byte is modified independently of the other.
Test 7 — JSR Test — The JSR is the first test in the GO-NO GO sequence that utilizes the stack. The
jump subroutine command (JSR) is executed in modes 1 and 6. After the JSR is executed, the subroutine which was given control will examine the stack to ensure that the correct data was placed in the
correct stack location (500). The routine will also ensure that the line back register points to the correct
address. Any errors detected in this test will result in a halt.
Test 8 - Dual Addressing and Data Check - Finally the memory test performs both dual addressing and
data check of all the available memory on the system below 28K. This test will leave all of memory
clear. Like the secondary tests the memory test will halt when an error is detected. At the time the
memory error halt is executed, R4 will contain the address at which the failure was detected. RO will
contain the failing data pattern and R6 will contain the expected data pattern. Thus after a memory
failure has occurred, the user can enter the console emulator and have this information printed out
immediately by display routine. (See section on console emulator.)
6.3 DIAGNOSTICS (PDP-11/60 AND 11/70)
The M9312 provides basic diagnostic tests for the CPU, memory, and cache when used with .PDP11/60 and PDP-11/70 computers. All diagnostic tests reside in ROM memory locations 765000
through 765776 (console emulator routine is eliminated.) These diagnostics test the basic CPU including the branches, the registers, all addressing modes, and many of the instructions in the PDP-11
repertoire. Memory from virtual address 1000 to the highest available address up to 28K will also be
checked. After main memory has been verified, with the cache off, the cache memory will be tested to
verify that hits occur properly. Main memory will be scanned again to ensure that the cache is working
properly throughout the 28K of memory to be used in the boot operation. If one of the cache memory
tests fails, the operator can attempt to boot the system anyway by pressing continue. This will cause
the program to force misses in both groups of the cache before going to the bootstrap section of the
program. The following is a list of M9312 diagnostic tests.

TEST 1
TEST2
TEST3
TEST4
TESTS
TEST6
TEST7
TEST 10
TEST 11
TEST 12
TEST 13
TEST 14
TEST 15

This test verifies the unconditional branch
Test CLR, MODE 0, and BMI, BVS, BHI, BLT, BLOS
Test DEC, MODE 0, and BPL, BEQ, BGE, BLE
Test ROR, MODE 0, and BVC, BHIS, BNE
Test register data path
Test ROL, BCC, BLT
Test ADD, INC, COM, and BCS, BLE
Test ROR, DEC, BIS, ADD, and BLO
Test COM, BIC, and BGT, BLE
Test SWAB, CMP, BIT, and BNE, BGT
Test MOVB, SOB, CLR, TST and BPL, BNG
Test JSR, RTS, RTI, and JMP
Test main memory from virtual 001000 to last address
Cache memory diagnostic tests

TEST 16
TEST 17

Test cache data memory
Test memory with the data cache on

Diagnostic Test Descriptions

Test 1 - Verify the Unconditional Branch
The registers and condition codes are all undefined when this test is entered and they should remain
that way upon completion of this test.
Test 2 - Test CLR, MODE 0, and BMI, BVS, BHI, BLT, BLOS

The registers and condition codes are all undefined when this test is entered. Upon completion of this
test, the SP (R6) should be zero and only the Z flip-flop will be set.
Test 3 - Test DEC, MODE 0, and BPL, BEQ, BGE, BLE

Upon entering this test, the condition codes are: N = 0, Z 1,
V=0,and C = 0.
The registers are: RO =7, R1 =27, R2 =7 R3 =7 R4 =7 RS5 =7 and SP = 000000.
Upon completion of this test, the conditlon codes w111 bee
N=1,Z=0,V =0, and C = 0.
The registers affected by the test are: SP = 177777.
Test 4 — Test ROR, MODE 0, and BVC, BHIS, BNE
Upon entering this test, the condition codes are: N = 1, Z =
The registers are: RO =?, R1 =272, R2 =72 R3 =7, R4 =1,

Upon completion of this test the condltlon codes w1ll be: N
The registers affected by the test are: SP = 077777.
Test 5 - Test Register Data Path

Upon entering this test, the condition codes are: N = 0, Z O,V=1,and C = 1.
The registers are: RO = ?, R1 =?, R2 =7, R3 =7, R4 = 7, RS =7, and SP
= 077777.
Upon completion of this test the condltlon codes W111 be:
N=0,Z=1,V=0,and C = 0.
The registers are left as follows: RO
= 125252, R1
= 000000, R2
= 125252, R3 = 125252, R4 = 125252,
RS = 125252, and SP = 125252.
Test 6 - Test ROL, BCC, BLT
When this test is entered, the condition codes are: N =0,Z =1,V =0, and C = 0.
The registers are: RO = 125252, R1 = 000000, R2 = 125252, R3 = 125252, R4 = 125252, RS = 125252,
SP = 125252.
Upon completion of this test, the condition codes are: N =0,Z =0,V =1,and C = 1.
The registers are left unchanged except for R2 which should now equal 052524,

Test 7 — Test ADD, INC, COM, and BCS, BLE
When this test is entered, the condition codes are: N =0,Z =0,V =1,and C = 1.
The registers are: RO = 125252, R1 = 000000, R2 = 052524, R3 = 125252, R4 = 125252, RS = 125252,
SP = 125252.

Upon completion of this test, the condition codes are: N =0,Z =1,V =0, and C = 0.
The registers are left unchanged except for R3 which now equals 000000, and R1 which is also 000000.
Test 10 - Test ROR, DEC, BIS, ADD, and BLO
When this test is entered, the condition codes are: N =0,Z =1,V =0,and C = 0.
The registers are: RO = 125252, R1 = 000000, R2 = 052524, R3 = 000000, R4 = 125252, R5 = 125252,
and SP = 125252.
Upon completion of this test, the condition codes are: N =1,Z =0,V =0, and C = 0.
The registers are left unchanged except for R1 which should equal 177777, and R4 which should now
equal 052525.

Test 11 - Test COM, BIC, and BGT, BLE
When this test is entered, the condition codes are:

N =1,Z =0,V =0, and C = 0.
The registers are: RO = 125252, R1 = 177777, R2 = 052524, R3 = 000000, R4 = 052525, R5 = 125252,
and SP = 125252.

6-6

Upon completion of this test, the condition codes are: N =0,Z =0,V =1, and C = 1.
The registers are left unchanged except for RO which should now equal 052525, and R1 which should
now equal 052524.

Test 12 - Test SWAB, CMP, BIT, and BNE, BGT
When this test is entered, the condition codes are: N =0,Z =0,V =1, and C = 1.
The registers are: RO = 052525, R1 = 052524, R2 = 052524, R3 = 000000, R4 = 052525, RS = 125252,
SP = 125252.
C = 1.
Upon completion of this test, the condition codes are: N = 0, Z = 0,V=0,and
The registers are now: RO = 052525, R1 = 052125, R2 = 052524, R 3 = 000000, R4 = 052525, R5 =
052525, SP = 12525.
Test 13 — Test MOVB, SOB, CLR, TST and BPL, BNE
When this test is entered, the condition codes are: N =0,Z =0,V =0, and C = 1.
The registers are: RO = 052525, R1 = 052125, R2 = 052524, R3 = 000000, R4 = 052525, R5 = 052525,
and SP = 125252.
Upon completion of this test, the condition codes are: N =0,Z =1,V =0, and C = 0.
RO is decremented by an SOB instruction to 000000; R1 is cleared and then incremented around to
000000.

Test 14 - Test JSR, RTS, RTI, JIMP
This test first sets the stack pointer to 000776, and then verifies that
properly.

JSR, RTS, RTI, and

JMP all work

On entry to this test, the stack pointer (SP) is initialized to 000776 and is left that way on exit.
Test 15 — Test Main Memory from 1000 to Highest Available Address up to 28K
This test will test main memory with the cache disabled, from virtual address 001000 to the last address

(up to 28K). The memory is sized before testing begins. If the data does not compare properly, the test
will halt at either 165516 or 165536. If a parity error occurs, the test will halt at address 165750, with
PC + 2 on the stack.
In this test the registers are initialized as follows: RO = 001000, R1 = DATA READ, R2 = 001000, R3
= 177746 (cache control register), R4 = count value, RS = last memory address, SP = 000776.
The following two tests are cache memory tests. If either of them fails to run successfully it will come to
a halt in the M9312 ROM. If you desire to try to boot your system anyway, you can press continue and
the program will force misses in both groups of the cache and go to the bootstrap that has been
selected.
Test 16 — Test Cache Data Memory

This test will check the data memory in the cache, on the PDP-11/60. There is only one group (1K), on
PDP-11/70 there are two groups, (1/2K) each. The test loads 0552525 into an address, complements it
twice and then reads the data, then it checks to ensure that the data was a hit. Then the sequence is
repeated on the same address with 125252 as the data. All cache memory data locations are tested in
this way. If either group fails and the operator presses continue the program will try to boot with the
cache disabled.
The registers are initialized as follows for this test: RO = 4000 (address), R1 = 2 (count), R2 = 1000
(count), R3 = 177746 (control register), R4 = 125252 (pattern), RS = (last memory address), SP =
000776 (flag of zero pushed on stack).

Test 17 — Test Memory with the Data Cache On
This test checks virtual memory from 001000 thru last address to ensure that you can get hits all the

way up through main memory. On the PDP-11/70, it starts with group 1 enabled, then tests group O,
and finally checks memory with both groups enabled. On the PDP-11/60, the test is done with the
whole cache enabled.
Upon entry the registers will be set up as follows: RO = 001000 (address), R1 = 3 (pass count), R2 =
(first address), R3 = 177746 (control register), RS = (last memory address), SP = 775
Upon completion of this test main memory from vitual address 001000 thru last address will contain
its own virtual address.

APPENDIX A

M9312

A.1

JUMPERS

INTRODUCTION

The M9312 Bootstrap/Terminator Module is compatible with any PDP-11 system through the use of
12 jumpers (W-1 through W-12.) Table A-1 explains the function of these jumpers. Table A-2 shows
necessary jumper configurations for various PDP-11 systems.

Table A-1

Jumper Explanation

Jumper

Function

Connects Pull Up for BUS BG6 H (When in)

Connects Pull Up for BUS BG7 H (When in)

W3
W4
W5
W6
W7
W8
W9, W10

Connects Pull Up for BUS NPG H (When in)
Connects Pull Up for BUS BG5S H (When in)
Connects Pull Up for BUS BG4 H (When in)
Connects BUF VECTOR L to finger BD1 (IN for PDP-11/70)
RESERVED (Always in)
Connects LO ROM ENABLE H (When out)
Install for power-up boot to 773024(g) (IN for all CPUs except 11/60)

W11, W12

Install for power-up boot to 773224(gy (IN for PDP-11/60 only)

A-1

Table A-2

PDP-11 Systems

PDP-11/04/34/34A
(Modified Unibus
Device Machine)
with the M9312in
slot AB2, 3, 4 of
processor backplane

w2 W3

Jumper Configurations

Jumpers
Wwé
w7

OuUT OouUT OUT OouT OouT OouT

W9 w10 Wil wi2

OuUT

ouT OUT

OuUT

OUT OuUT

PDP-11/70 with
M9312 inslot EF1

of processor
backplane (See note)

PDP-11/60 with M9312
in the last AB slot of the OuUT OUT
last memory backplane

Other Unibus CPUs
with an M9312, or
an M9312 in place
of an M9301 or
equivalent

OUT OuUT OuUT OUT

OUT

OouT OouT OUT IN

NOTES
If a Unibus repeater is used in the system, the M9312
must be installed on the processor side of the repeater.

For boot on power-up the 11/70 requires the following.
1.

7010329 backplane ECO 8 (wire list Rev J or
later)
M8130 ECO’s 1, 2 and 3 (CS Rev C or later)
Jumpers set as follows: W1-IN, W2-OUT, W3IN, W4-OUT, W5-OUT, W6-OUT, W7-OUT,
WS8-IN, W9-OUT
M8138 ECO 5 (CS Revs C1 or E or later)
M9312 ECO 1 (CS Rev B or later)

OuUT OUT

APPENDIX B

M9312 ROMs

The M9312, through the use of socketed ROMs, can boot most PDP-11 peripheral devices, run diag-

nostic routines or execute a console emulator routine. The Address Offset Switch Bank (Paragraph 2.9
and Appendix C) is used to select one or more of these functions. Five sockets are used to accept
ROMs with these various routines. The console emulator and diagnostic ROM socket (E20) accepts
ROMs which contain either a console emulator and diagnostic routine or just a diagnostic routine for
the PDP-11/60 and 11/70. The last two characters in the pattern number for these ROMs will always
be ““F1.” The other four sockets (locations E32, E33, E34, and E35) accept ROMs which contain
bootstrap programs. The last two characters of the pattern number for boot ROMs will always be
“A9.” Although it is not required that a particular device boot ROM go in a particular socket, the
order in which these sockets are filled is important. Table B-1 shows the necessary installation order
for Boot ROMs,

Table B-1

Boot ROM Installation Order

Order of
Installation

ROM Socket #

First Boot ROM*
Second Boot ROM
Third Boot ROM

E35
E33
E34

Fourth Boot ROM

E32

Location #
1
2
3
4

*On PDP-11/60 if only one ROM, then it must be installed in ROM location #2 to do a power-up
boot.

APPENDIX C

M9312 ADDRESS OFFSET SWITCH BANK

C.1

INTRODUCTION

Tables C-1 through C-11 contain the necessary information to boot a particular device either on
power-up boot, pushbutton boot, or console load address start sequence. A more detailed explanation
of these switches and their functions may be found in Paragraphs 2.9 and 3.2, Table 3-1, Figure 2-11,
and Appendix F.

Table C-1

Device to be | ROM Location | Diag-

Starting

ROM P/N 23-751A9

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device | SWR

Booted

from App B

nostic

Unit | Address*

RLO1
RLO1

ROM 1
ROM 1

NO
YES

0
0

173004
173006

OFF | +
OFF | +

RLO1
RLO1

ROM 2
ROM 2

NO
YES

0
0

173204
173206

RLO1
RLO1

ROM 3
ROM 3

NO
YES

0
0

RLO1
RLO1

ROM 4
ROM 4

NO
YES

0
0

|OFF | OFF | OFF | OFF
|OFF | OFF | OFF |OFF

|OFF
|OFF

|ON | OFF | NA
[ON | ON | 012

OFF | f
OFF | f

|OFF
|OFF

|ON | OFF
|ON | OFF

|OFF
|OFF

|[OFF
|OFF

|ON | OFF | NA
|ON | ON | 212

173404
173406

OFF | ¥+
OFF | +

|ON
|ON

| OFF | OFF
| OFF | OFF

|OFF
|OFF

|ON | OFF | NA
|ON | ON | 412

173604
173606

OFF
OFF

|[ON
|[ON

|ON | OFF
|ON | OFF

|OFF
|OFF

|ON | OFF | NA
|ON | ON | 612

| ¥
|+

Code

*The starting address for the console load address and start sequence.

1 S1-2:when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)
NOTES

If diagnostics are to be run, a CPU diagnostic ROM must
be in location E20, and jumper W8 must be out.

When booting from the console emulator, a device
mnemonic and unit number are required. If unit number

is not entered, it is assumed to be zero. Listed below are
the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.
Device

Mnemonic

Unit

CSR

RLO1

0-3

774400

Table C-2
Device to be

= ROM Location

Diag-

Booted

from App B

nostic

RK06/07
RK06/07

ROM 1

RK06/07
RK06/07

Starting

ROM P/N 23-752A9

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device
10

| SWR

Unit

Address*

0
0

173004
173006

OFF
OFF

OFF

OFF
OFF

OFF

ON
ON

OFF | NA

OFF

OFF
OFF

OFF

{

OFF
OFF

OFF

YES

ROM 2
ROM 2

NO
YES

0
0

173204
173206

OFF
OFF

t+
¥+

OFF
OFF

ON
ON

OFF
OFF

ON
ON

OFF | NA
ON
212

RK06/07
RK06/07

ROM 3
ROM 3

NO
YES

0
0

173404
173406

OFF
OFF

t
t

ON
ON

OFF
OFF

ON
ON

OFF | NA
ON
412

RK06/07
RK06/07

ROM 4
ROM 4

NO
YES

0
0

173604
173606

OFF
OFF

{
{

ON
ON

OFF
OFF

ON
ON

OFF | NA
ON
612

| Code

012

*The starting address for the console load address and start sequence.
TS1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTES
If diagnostics are to be run, a CPU diagnostic ROM must

be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device
mnemonic and unit number are required. If unit number

is not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.
Device

RK06/07

Mnemonic

Unit

CSR

0-7

777440

Table C-3
Device to be | ROM Location | Diag-

Starting

| Unit | Address*

ROM P/N 23-753A9

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device

Booted

from App B

nostic

RXO01
RXO01

ROM 1
ROM 1

NO
YES

0
0

173004
173006

OFF | ¥+
OFF | ¥+

|OFF | OFF
|OFF | OFF

|OFF | OFF
|OFF | OFF | ON
|OFF | OFF | OFF | OFF | ON

OFF | NA
ON | 012

RXO01
RXO01

ROM 2
ROM 2

NO
YES

0
0

173204
173206

OFF | ¥
OFF | ¥

|OFF ] ON
|OFF | ON

|OFF | OFF
|OFF | OFF | ON
OFF | OFF | OFF | OFF | ON

OFF | NA
ON
212

RXO01
RXO01

ROM 3
ROM 3

NO
YES

0)
0

173404
173406

OFF | ¥
OFF | ¥+

|ON
|ON

OFF
|OFF | OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF | OFF | ON

OFF | NA
ON
412

RXO01
RXO01

ROM 4
ROM 4

NO
YES

0
0

173604
173606

OFF | ¥
OFF | ¥

|[ON | ON
|ON
ON

OFF | OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF | ON

| SWR

| Code

OFF | NA
ON
612

*The starting address for the console load address and start sequence.

1 S1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)
NOTES
If diagnostics are to be run, a CPU diagnostic ROM must

be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device
mnemonic and unit number are required. If unit number

is not entered, it is assumed to be zero. Listed below are
the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot code.

Device

Mnemonic

Unit

CSR

RXO01

0-1

777170

Table C-4

ROM P/N 23-755A9

Device to be

ROM Location | Diag-

Starting | Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device | SWR

Booted

from App B

nostic| Unit

|Address* | 1

10 | Code

RP02/03

ROM 1

1173004

|OFF | v | OFF | OFF | OFF | OFF | OFF | OFF | ON

OFF | NA

RP02/03

ROM 1

YES

173006

|OFF | T | OFF | OFF | OFF | OFF | OFF | OFF | ON

RP02/03
RP02/03

ROM 2
ROM 2

NO
YES

0
0

173204
173206

|OFF | T | OFF | ON
|OFF | t | OFF | ON

OFF | OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF | ON

OFF | NA
ON
212

RP02/03
RP02/03

ROM 3
ROM 3

NO
YES

| 0
0

[173404
|{173406

|OFF [ T [ ON
|OFF | ¥ | ON

OFF | OFF | OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF | OFF | ON

OFF | NA
ON
412

|OFF | ¥ | ON

OFF | NA

RP02/03

|173604

RP02/03

ROM 4

YES

(173606

|OFF | ¥ | ON

RP04/05/06 RM02/03
RP04/05/06 RM02/03

ROM 1
ROM 1

NO
YES

0
0

(173050
|173052

|OFF | ¥ | OFF | OFF | OFF | ON
|OFF | ¥+ | OFF | OFF | OFF | ON

OFF | ON
OFF | ON

OFF | OFF | NA
OFF | ON
056

RP04/05/06 RM02/03
RP04/05/06 RM02/03

ROM 2
ROM 2

NO
YES

0
0

173250
(173252

|OFF | ¥ | OFF | ON
|OFF | ¥ | OFF | ON

OFF | ON
OFF | ON

OFF | OFF | NA
OFF | ON
256

RP04/05/06 RM02/03
RP04/05/06 RM02/03

ROM 3
ROM 3

NO
YES

0
0O

173450
173452

|OFF | ¥ | ON
|OFF | ¥ | ON

OFF | OFF | ON
OFF | ON
OFF | OFF | ON | OFF | ON

OFF | OFF | NA
OFF | ON
456

RP04/05/06 RM02/03
RP04/05/06 RM02/03

ROM 4
ROM 4

NO
YES

0
0

173650
(173652

|OFF | ¥ | ON
|OFF | ¥ | ON

ON
ON

OFF | OFF | NA
OFF | ON
656

OFF | OFF | OFF | OFF | ON

012

OFF | OFF | OFF | OFF | ON

OFF | ON
OFF | ON

*The starting address for the console load address and start sequence.
1 S1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTES
If diagnostics are to be run, a CPU diagnostic ROM must

be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device
mnemonic and unit number are required. If unit number
iS not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot

code.
Device

RP02/03
RP04/05/06 RM02/03

Mnemonic

Unit

CSR

DP
DB

0-7
0-7

776714
776700

612

Table C-5
Starting

ROM P/N 23-756A9

Device to be

|ROM Location | Diag-

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device

Booted

from App B

nostic

Unit | Address*

RKO03/05/05]
RKO03/05/05]
RKO03/05/05]

ROM 1
ROM 1
ROM 1

NO
NO
YES

0
2
0

173004
173164
173006

OFF | t+ | OFF | OFF | OFF | OFF | OFF | OFF | ON
OFF|
1 | OFF | OFF | ON
ON
ON
OFF | ON
OFF | t | OFF { OFF | OFF | OFF | OFF | OFF | ON

OFF | NA
OFF | NA
ON
012

RKO03/05/05]
RKO03/05/05]

ROM 2
ROM 2

NO
NO

0
2

173204
173364

OFF|
OFF|

+ | OFF | ON
+ | OFF { ON

OFF | OFF | OFF | OFF | ON
ON
ON
ON
OFF | ON

OFF | NA
OFF | NA

RK03/05/05J

ROM 2

YES

173206

OFF|

1 | OFF | ON

OFF | OFF | OFF | OFF | ON

RKO03/05/05]
RKO03/05/05]
RKO03/05/05]

ROM 3
ROM 3
ROM 3

NO
NO
YES

0
2
0

173404
173564
173406

OFF|]
OFF|
OFF|]

1 | ON
t | ON
f | ON

OFF | OFF | OFF | OFF | OFF | ON
OFF | ON
ON
ON
OFF | ON
OFF | OFF | OFF | OFF | OFF | ON

OFF | NA
OFF | NA
ON
412

RKO03/05/05]

ROM 4

173604

OFF|

+ | ON

OFF | OFF | OFF | OFF { ON

OFF | NA

RKO03/05/05]
RK03/05/05]

ROM 4
ROM 4

NO
YES

2
0

173764
173606

OFF|
OFF|

T | ON
1 | ON

ON
ON

ON
ON
ON
OFF | ON
OFF | OFF | OFF | OFF | ON

OFF | NA
ON
612

TUS55/56

ROM 1

173034

OFF |

t | OFF | OFF | OFF | OFF | ON

OFF | NA

TUS55/56

ROM 1

YES

173036

OFF | 1 | OFF | OFF | OFF | OFF | ON

TUS55/56
TUS55/56

ROM 2
ROM 2

NO
YES

0
0

173234
173236

OFF|
OFF|

1 | OFF { ON
1 | OFF | ON

OFF | OFF | ON
OFF | OFF | ON

ON
ON

OFF | NA
ON
242

TUS5/56
TUS5/56

ROM 3
ROM 3

NO
YES

0
0

173434
173436

OFF|
OFF |

¥ | ON
1 | ON

OFF | OFF | OFF | ON
OFF | OFF | OFF | ON

ON
ON

OFF | NA
ON
442

TUS55/56
TUS5/56

ROM 4
ROM 4

NO
YES

0
0

173634
173636

OFF|
OFF|

T | ON
T | ON

ON
ON

OFF | NA
ON
642

OFF | OFF | ON
OFF | OFF | ON

| SWR
| Code

212

042

*The starting address for the console load address and start sequence.

1 S1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTES
If diagnostics are to be run, a CPU diagnostic ROM must
be in location E20, and jumper W8 must be out.

When booting from the console emulator, a device
mnemonic and unit number are required. If unit number
is not entered, it is assumed to be zero. Listed below are
the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.

Device

RKO03/05/05]
TUS55/56

Mnemonic

Unit

CSR

DK
DT

0-7
0-7

777404
777342

C-6

Table C-6
Device to be | ROM Location | Diag-

Booted

from APP B

nostic

Starting

Unit | Address*

ROM P/N 23-757A9

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device

| SWR

| Code

TU16

ROM 1

173004

OFF | +

|OFF | OFF

|OFF | OFF | OFF | OFF | ON

OFF | NA

TUI16

ROM 1

YES

173006

OFF | ¥ | OFF | OFF

|OFF | OFF | OFF | OFF | ON

TU16
TUIG6

ROM 2
ROM 2

NO
YES

0
0

173204
173206

OFF | ¥
OFF | ¥

|OFF | ON
|OFF | ON

|OFF | OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF | ON

OFF | NA
ON
212

TU16

ROM 3

173404

OFF | ¥

|ON

OFF

|OFF | OFF { OFF | OFF | ON

OFF | NA

TUI16

ROM 3

YES

173406

OFF | ¥

|ON

OFF

|OFF | OFF | OFF | OFF | ON

TU16

ROM 4

173604

OFF | ¥

|ON

|OFF | OFF | OFF | OFF | ON

OFF | NA

TU16

ROM 4

YES

173606

OFF

|ON

OFF | OFF | OFF | OFF | ON

| ¥

012

412
612

*The starting address for the console load address and start sequence.
tS1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTES
If diagnostics are to be run, a CPU diagnostic ROM must

be in location E20, and jumper W8 must be out.

When booting from the console emulator, a device
mnemonic and unit number are required. If unit number

is not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.
Device

Mnemonic

Unit

CSR

TU16

0-7

772440

C-7

Table C-7

Device to be | ROM Location | Diag-

Booted

Starting

ROM P/N 23-758A9

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device | SWR

from App B

nostic

Unit | Address*

TU10 TSO3
TU10 TSO03

ROM 1
ROM 1

NO
YES

0
0

173004
173006

OFF | | OFF | OFF
OFF
|t | OFF | OFF

|OFF | OFF | OFF | OFF | ON
|[OFF | OFF | OFF | OFF | ON

OFF | NA
ON
012

TUIO TS03
TUI10 TSO03

ROM 2
ROM 2

NO
YES

0
0

173204
173206

OFF
OFF

|1 | OFF | ON
|1 | OFF { ON

OFF | OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF | ON

OFF | NA
ON
212

TU10 TSO3
TU10 TSO3

ROM 3
ROM 3

NO
YES

0
0

173404
173406

OFF
OFF

|1 | ON
|1 | ON

|OFF | OFF | OFF | OFF | ON
|OFF | OFF | OFF | OFF | ON

OFF | NA
ON
412

TU10 TSO03

ROM 4

173604

OFF | f | ON

TU10 TSO03

ROM 4

YES

173606

OFF | T | ON

OFF
OFF

OFF | OFF | OFF | OFF | ON

|OFF | OFF | OFF | OFF | ON

10 | Code

OFF | NA

612

*The starting address for the console load address and start sequence.

+S1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)
NOTES

If diagnostics are to be run, a CPU diagnostic ROM must
be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device

mnemonic and unit number are required. If unit number
is not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.
Device

TUI0 TSO3

Mnemonic

Unit

CSR

0-7

772522

C-8

Table C-8

Device to be | ROM Location | Diag-

Starting

Booted

from App B

nostic

Unit | Address*®

RS03/04
RS03/04

ROM 1
ROM 1

NO
YES

0
0

173004
173006

RS03/04
RS03/04

ROM 2
ROM 2

NO
YES

0
0

173204
| 173206

RS03/04
RS03/04

ROM 3
ROM 3

NO
YES

0
0

RS03/04
RS03/04

ROM 4
ROM 4

NO
YES

0
0

ROM P/N 23-759A9

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device
1

| SWR
| Code

OFF | + | OFF | OFF | OFF | OFF
OFF | + | OFF | OFF | OFF | OFF

|OFF | OFF | ON
OFF | NA
|OFF | OFF | ON | ON
012

OFF
OFF

|t | OFF|
|+ | OFF|

ON | OFF | OFF
ON | OFF | OFF

|OFF | OFF | ON
OFF | NA
|[OFF | OFF |ON | ON
212

173404
173406

OFF | 7 | ON
OFF | ¥ | ON

OFF | OFF { OFF
OFF | OFF | OFF.

|[OFF | OFF | ON | OFF | NA
|OFF | OFF | ON | ON
412

173604
173606

OFF | T | ON
OFF | ¥ | ON

ON
OFF | OFF
ON | OFF | OFF

|OFF | OFF | ON | OFF | NA
|[OFF | OFF { ON | ON
612

*The starting address for the console load address and start sequence.

+S1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)
NOTES
If diagnostics are to be run, a CPU diagnostic ROM must
be in location E20, and jumper W8 must be out.

RS03/04

Mnemonic

Unit

CSR

0-7

772040

Table C-9
Device to be

Booted

| ROM Location | Diag-

from App B

nostic

Starting

Unit | Address*

ROM P/N 23-760A9

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device

| SWR

Code

PCO5

ROM 1

173004

OFF

| ¥+

|OFF | OFF | OFF | OFF | OFF | OFF | ON

OFF | NA

PCO5

ROM 1

YES

173006

OFF

| ¥+

[OFF | OFF | OFF | OFF | OFF | OFF | ON

PCO5
PCO5

ROM 2
ROM 2

NO
YES

0
0

173204
173206

OFF | ¥
OFF | ¥

|OFF | ON
|OFF | ON

OFF | NA
ON
212

PCO5

ROM 3

173404

OFF | ¥

|ON

OFF | OFF | OFF | OFF | OFF | ON

OFF | NA

PCO5

ROM 3

YES

173406

OFF | ¥+

|ON

OFF | OFF | OFF | OFF | OFF | ON

OFF | OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF | ON

012

412

PCOS

ROM 4

173604

OFF | ¥

|ON

OFF | OFF | OFF | OFF | ON

OFF | NA

PCO5

ROM 4

YES

173606

OFF | ¥

|ON

OFF | OFF | OFF | OFF | ON

LO SPD RDR|

ROM 1

173034

OFF | ¥

|OFF | OFF | OFF | OFF | ON

OFF | NA

LO SPD RDR|

ROM 1

YES

173036

OFF | ¥+

|OFF | OFF | OFF | OFF | ON

LO SPD RDR|

ROM?2

173234

OFF | +

|OFF | ON

OFF | OFF | ON

OFF | NA

LO SPD RDR|

ROM?2

YES

173236

OFF | ¥+

|OFF | ON

OFF | OFF | ON

612

042

242

LO SPD RDR|

ROM 33

173434

OFF | ¥

|ON

OFF | OFF | OFF | ON

OFF | NA

LO SPD RDR|

ROM 3

YES

173436

OFF | ¥+

[ON

OFF | OFF | OFF | ON

LO SPD RDR|

ROM 4

173634

OFF | ¥

|ON

OFF | OFF | ON

OFF | NA

LO SPD RDR|

ROM 4

YES

173636

OFF | ¥

[ON

OFF | OFF | ON

442
642

*The starting address for the console load address and start sequence.

1S1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTES
If diagnostics are to be run, a CPU diagnostic ROM must

be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device
mnemonic and unit number are required. If unit number

is not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.
Mnemonic

Unit

CSR

HI SPD RDR

LO SPD RDR

N/A
N/A

777560

Device

777550

C-10

Table C-10
Device to be | ROM Location | DiagBooted

from App B

nostic

TU60
TU60

ROM 1
ROM 1

NO
YES

TU60

ROM 2

TU60

ROM 2

TU60

Starting
Unit | Address*

ROM P/N 23-761A9

Switch Settings S1 - for Power-Up Boot or Push-Button Boot of Device
1

| SWR
| Code

0
0

173004

OFF | ¥ | OFF | OFF | OFF | OFF | OFF | OFF | ON

173006

OFF | T | OFF | OFF | OFF | OFF | OFF | OFF | ON

OFF | NA
012

173204

OFF

|t | OFF | ON

OFF | OFF | OFF | OFF | ON

OFF | NA

YES

173206

OFF | T | OFF | ON

OFF | OFF | OFF | OFF | ON

ROM 3

173404

OFF

|t | ON

OFF | OFF | OFF | OFF | OFF | ON

OFF | NA

TU60

ROM 3

YES

173406

OFF | ¥ | ON

OFF | OFF | OFF | OFF | OFF | ON

TU60

ROM 4

173604

OFF

|+ | ON

OFF | OFF | OFF | OFF | ON

OFF | NA

TU60

ROM 4

YES

173606

OFF

| ¥ | ON

OFF | OFF | OFF | OFF | ON

212
412

612

*The starting address for the console load address and start sequence.

TS1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTES
If diagnostics are to be run, a CPU diagnostic ROM must

be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device

mnemonic and unit number are required. If unit number
is not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot

code.
Device

Mnemonic

Unit

CSR

TU60

0-1

777550

C-11

Table C-11
Starting

ROM P/N 811A9

Device to be|

ROM Location | Diag-

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device

Booted

from App B

RXO02

ROM 1

173004

OFF | ¥ | OFF | OFF | OFF | OFF | OFF

|OFF

|ON | OFF | NA

RX02

ROM 1

YES

173006

OFF | ¥

|OFF

|ON

RXO02

ROM 2

173204

OFF | ¥

|OFF | ON

| OFF | OFF | OFF

|OFF

|ON | OFF | NA

RX02

ROM 2

YES

173206

OFF | ¥+

|OFF | ON

| OFF | OFF | OFF

|OFF

|ON | ON | 212

RXO02
RXO02

ROM 3
ROM 3

NO
YES

0
0

173404
173406

OFF | ¥+
OFF | ¥

| OFF | OFF | OFF | OFF | OFF
OFF | OFF | OFF | OFF
|OFF

|ON | OFF | NA
|ON | ON | 412

RXO02

ROM 4

173604

OFF | +f

|ON

| ON

| OFF | OFF | OFF

|OFF

|ON | OFF | NA

RX02

ROM 4

YES

173606

OFF

|[ON

| ON

| OFF | OFF | OFF

|OFF

|ON

| nostic | Unit | Address* |

2 | 3

| f

| OFF | OFF | OFF | OFF | OFF

|ON
| ON

| SWR

10 | Code
| ON

| 012

| ON | 612

NOTE
If diagnostics are to be run, a CPU diagnostic ROM must

be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device
mnemonic and unit number are required. If unit number
is not entered, it is assumed to be zero. Listed below are
the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.
Device

Mnemonic

Unit

CSR

RX02

0-1

777170

C-12

Table C-12 ROM P/N 23-764A9
Device to be

ROM Location

Diag-

Starting

Booted

from App B

nostic

Unit | Address*

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device

SWR

110

Code
NA

TS04

ROM 1

0 | 173004

OFF | +

| OFF

|OFF | OFF | OFF

|OFF

|OFF | ON

| OFF|

TS04

ROM 1

YES

0 | 173006

OFF | ¥+

| OFF

|OFF | OFF | OFF

|OFF

|OFF|

| ON | 012

TS04

ROM 2

0 | 173204

OFF | ¥+

| OFF

|ON | OFF | OFF

|OFF

|OFF | ON

| OFF | NA

TS04

ROM 2

YES

0 | 173206

OFF | +

| OFF

|ON

|OFF

|OFF|]

| ON | 212

TS04

ROM 3

0 | 173404

OFF

| ON

|OFF | OFF | OFF

|OFF

|OFF | ON

| OFF | NA

TS04

ROM 3

YES

0 | 173406

OFF | ¥+

| ON

|OFF | OFF | OFF

| OFF

|OFF | ON

| ON | 412

TS04

ROM 4

0 | 173604

OFF

| ON

|ON | OFF | OFF

|OFF

|OFF | ON | OFF | NA

TS04

ROM 4

YES

0 | 173606

OFF | ¥+

|ON

|OFF

|OFF|

| OFF | OFF

| ON | 612

* The starting address for the console load address and start sequence.

1S1-2:when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTE

If diagnostics are to be run, a CPU diagnostic ROM must
be in location E20, and jumper W8 must be out.
When booting from the console emulator, a device
mnemonic and unit number are required. If unit number
is not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this

ROM, and the device CSR address assumed by the boot
code.

Device

Mnemonic

Unit

CSR

TS04

0-3

772520

C-13

Table C-13 ROM P/N 23-765A9

Device to be

ROM Location

Diag-

gtarting

Switch Settings S1-for Power-Up Boot or Push-Button Boot of Device

0
0

|173004
|173006

OFF | ¥ | OFF
OFF
|t | OFF

|OFF | OFF
|OFF | OFF

|OFF
|OFF
|OFF |OFF

|OFF | ON
|OFF
|ON

| OFF|
NA
| ON | 012

[173204

OFF | ¥

| OFF

|ON

| OFF

|OFF

|OFF | ON

| OFF|

YES

|173206

OFF

|+ | OFF

|ON

| OFF

|OFF

J|OFF

| ON | 212

|173404

OFF | ¥ | ON

|173406

OFF | ¥

Booted

from App B

nostic

Unit | Address*

TUSS
TUSS

ROM 1
ROM 1

NO
YES

TUSS8

ROM 2

TUSS8

ROM 2

TUSS8

ROM 3

TUSS

ROM 3

YES

TUSS8

ROM 4

|173604

OFF

TUSS

ROM 4

YES

|173606

OFF | T | ON

|ON

|10

SWR

Code

OFF | OFF

|OFF

|OFF | ON

| OFF|

| ON

| OFF | OFF

|OFF

|OFF |ON

| ON | 412

| | ON

ON | OFF

|OFF

|OFF | ON

| OFF|

|OFF

|OFF | ON

| ON | 612

| OFF

*The starting address for the console load address and start sequence.

TS1-2: when ON, power-up boot is enabled; when OFF, power-up boot disabled. (Must be OFF for PDP-11/60. See PDP-11/60 documentation for power-up boot.)

NOTE

If diagnostics are to be run, a CPU diagnostic ROM must
be in location E20, and jumper W8 must be out.

When booting from the console emulator, a device
mnemonic and unit number are required. If unit number

is not entered, it is assumed to be zero. Listed below are

the device mnemonic and unit numbers supported by this
ROM, and the device CSR address assumed by the boot
code.

Device

Mnemonic

Unit

CSR

TUSS

0—-1

776500

C-14

APPENDIX D

M9312 FASTON TAB CONNECTIONS

D.1
INTRODUCTION
The M9312 Faston tabs are defined in Table D-1. One of the frequent applications of the M9312 is to
replace the M9301. Table D-2 provides the necessary information needed to make the appropriate
substitutions with respect to the Faston tabs.

Table D-1

Faston Tab Description

Faston Tab

Function Performed

TP1
TP2

Bootinput
Return for boot input

TP3
- TP4

Return for enable boot on power-up
Enable boot on power-up

Table D-2

Module

From
|

Faston Tab Substitution

Wire
vir Connection
nnection

Faston Tab

Module

Faston Tab

M9301

TP1

M9312

TP4

M9301
M9301

TP2
TP3

M9312
M9312

TP1
TP2

D-1

APPENDIX E
CROSS REFERENCE AND IDENTIFICATION TABLES

E.1

CROSS REFERENCE TABLES

Table E-1 provides a guide used to identify a particular ROM by part number. Table E-2 is a cross
reference table which identifies each device with its corresponding controller.

Table E-1

Cross Reference ROM P/N to ROM Table Number

Part

Number
23-

Function Performed by ROM

See
Table

233F1
248F1

Diagnostic for 11/60/70 ROM ID=B0
ASCII Console and Diagnostic for

F-1
F-2

11/04/05/34/35/40/45/50/55

ROM ID=A0

The following ROMS are Bootstrap ROMs

Bootable Devices
First Device
Mnemonic | In ROM

Second Device
Mnemonic | in ROM

751A9

RLOI

C-1

752A9
753A9
811A9
755A9

DM
DX
DY
DP

RKO06/07
RXO01
RX02
RP02/03

NA
NA
NA
DB

NA
NA
NA
RP04/5/6 RMO02/3

C-2
C-3
C-11
C-4

756A9

TUS5/56

C-5

RKO03/05

757TA9
758A9

MM
MT

TUI6/E16 TMO02/3
TU10/TSO03

NA
NA

C-6
C-7

759A9

RS03 /04

C-8

T60A9
T61A9

PR
CT

PCO05
TUG60

TT
NA

LO SPD RDR
NA

C-9
C-10

T64A9
T65A9

MS
DD

TS04
TUSS

NA
NA

C-12
C-13

E-1

Table E-2

Cross Reference Device to Controller

Device

E.2

Controller

RLO1

RL11

RKO06/07
RXO01

RK611
RX11

RX02

RX211

RP02/03

RP11C/E

RP04/05/06 RMO02/03
RKO03/05
TUS5/56
TU16/E16 TMO02/03
TUI10/E10 TSO03
RS03/04
PCO05 (HI SPD RDR)
LO SPD RDR (ASR33)
TU60
TS04
TUSS8

RH11/70
RK11C/D
TCl11
RH11/70
TMI11/A11/B11
RH11/70
PC11/R11
DL11A/W
TA1l
TS11
Serial Line Unit

ROM IDENTIFICATION

When the ROM configuration of an M9312 already installed in a system is not known, it is desirable to
identify the ROM configuration without removing the module. This can be accomplished by running
‘diagnostic CZM9B, or by examining the data in five specific locations and using Table E-3 to identify
the ROM. The locations are as follows:

1.
2.
3.
4.

765774
773000
773200
773400
773600

Diagnostic ROM
ROM |
ROM 2
ROM 3
ROM 4

‘

By comparing the data observed at the above locations with Table E-3 you can identify the type and
location of each ROM in the module.

Table E-3

ROM Identification

Octal
Data

Mnemonic

040460
041060
041524
042113
042113
042114
042115
042120
042123
042130
042131
046515
046524
056122
177776
XXX771

AQ
248F1
F-2
BO
233F1
F-1
CT
761A9
C-10
CI
761A9
C-10
DK
756A9
C-5
DL
751A9
C-1
DM
752A9
C-2
DP
755A9
C-4
DS
759A9
C-8
DX
753A9
C-3
DY
811A9
C-11
MM
757A9
C-6
MT
758A9
C-7
PB
760A9
C-9
This is a Continuation ROM of a Multiple-ROM Boot
Bad ROM or No ROM Present

046523
000104

P/N
23-

TS04
TUSS

764A9
765A9

E-3

See
Table

C-12
C-13

APPENDIX F

DIAGNOSTIC AND CONSOLE EMULATOR ROMS

F.1 DIAGNOSTIC ROM (P/N 23-233F1)
There are no special M9312 switch settings that pertain to this ROM. The only way these diagnostics
can be executed is by entering a bootstrap at the entry point which calls for diagnostics to be run. This
ROM allows the user to boot via the console switch register. This can be done as follows:
1.
2.
3.

Load Address 765744.
Set switch register according to Table F-1
Start,

Table F-1

Console Switch Register Settings for Diagnostic ROM

15 [14 |13 |12 |11
NA [NA [NA [ NA

10L09 08|O7 06l05 04| 03 |02 o1|oo
|

Octal Unit
Number

]

SWR Code from Boot ROM Tables

F.2 CONSOLE EMULATOR AND DIAGNOSTIC ROM (P/N 23-248F1)
This ROM contains an ASCII console emulator routine and diagnostics for use with PDP-11/04,
11/05, 11/34, 11/35, 11/40, 11/45, 11/50, 11/55. To enter the ASCII console via power-up boot or
pushbutton boot, the M9312 switches must be set according to Table F-2.

Table F-2

Function to be

ROM

" Diag-

Booted

Location | nostic

Console Emulator
Console Emulator

E20
E20

NO
YES

Switch Settings for ASCII Console and Diagnostic ROM

Starting

S1 Switch Settings for Power-Up Boot or Push-Button Boot

| Address*

165144
165020

ON | T | OFF | OFF
|ON | ON | OFF | OFF
ON | ¥+ | OFF | OFF | OFF | OFF | ON | OFF

*The starting address for the console load address and start sequence.

tS1-2: When ON, power-up boot is enabled; when OFF, power-up boot is disabled.

F-2

|ON | OFF
|OFF | OFF

M9312 BOOTSTRAP/TERMINATOR

Reader’s Comments

TECHNICAL MANUAL

EK-M9312-TM-002

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our
publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?

What features are most useful?

What faults or errors have you found in the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs?

Why?

Please send me the current copy of the Technical Documentation Catalog, which contains information on
the remainder of DIGITAL’s technical documentation.

Name

Street

Title

City

Company

State/Country

Department

Zip

Additional copies of this document are available from:
Digital Equipment Corporation
444 Whitney Street
Northboro, Ma 01532
Attention: Communications Services (NR2/M15)
Customer Services Section
Order No.

EK-M9312-TM-002

FIRST CLASS

PERMIT NO. 33
MAYNARD, MASS.

BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation

Technical Documentation Department

Maynard, Massachusetts 01754

dlifgliltiall
digital equipment corporation

Printed

U.S.A.