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Document:	LSI-11 PDP-11/03 User's Manual
Order Number:	EK-LSI11-TM
Revision:	003
Pages:	198
Original Filename:

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EK-LSI11-TM-003

LSI-11, PDP-11/03
user’s manual

digital equipment corporation - maynard, massachusetts

1st Edition, September 1975
2nd Printing (Rev), November 1975
3rd Printing (Rev), May 1976

tion

The material in this manual is for informational
purposes and is subject to change without
notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual,

Printed in U.S.A.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

PDP

TYPESET-11

UNIBUS

6/77=14

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1

GENERAL

1.2

SCOPE

1.3

REFERENCES

CHAPTER 2

LSI-11 SYSTEM OVERVIEW

2.1

GENERAL

2.2

SYSTEM CONFIGURATIONS

2.3

LSI-11 MICROCOMPUTER

2.4

I/OBUS CONCEPT

. . . . . . .

2.5

MEMORY OPTIONS

. . . . . .

2.6

PERIPHERAL INTERFACE OPTIONS

2.7

BACKPLANE, POWER SUPPLY, AND HARDWARE OPTIONS

2.8

POWER REQUIREMENTS

2.9

GENERAL SPECIFICATIONS

CHAPTER 3

THE LSI-11 BUS

3.1

CHOOSING ANI/O TRANSFERTYPE

3.2

DEVICE PRIORITY

3.3

MODULE CONTACT FINGER IDENTIFICATION

. . .. ... ... ... ........

3-2

3.4

BUS SIGNALS

. . . .

3-4

3.5

BUS CYCLES

. . . .

. . . . e
e
e e e e e e

. . . e
e e e
e e e e e e e
. . . . . . . e
e e e e

. . . e
e e e e e e e
e

3.5.1

General

3.5.2

Input Operations

3.5.3

3.6

. . . . . . .

e e

e e e
e

e e

e e e

e e

2-1
2-1
2-1

2-2

e e e e

2-3

. . . . .. .. ... ...

2-3

e e e e e

. . . . . . . . . . . . . .

. . . . . . . .

1-1
1-1

. .

2-4

. . . .. .. .. . . .. . . .. . ... ......

3-1

. . . . . . s
e e e e e e

3-1

. . . . . . . .

e e e

e e e e

e
e e e

e e e e e e

. . . . . . . . . .

Output Operations

e e e e e e

. . . . . . . . . . . 0 o

e e e

e e

3-7

e e

3-7

3-8

e e e e e e e

3-7

. . . . o e
e 3-11

3.7

INTERRUPTS

3.8

BUS INITIALIZATION

3.9

POWER-UP/POWER-DOWN SEQUENCE

3.10

HALTMODE

3.11

MEMORY REFRESH

3.12

BUS SPECIFICATIONS

3.13

BUS CONFIGURATIONS

3.14

BUS SIGNAL TIMING

CHAPTER 4

LSI-11 MODULE DESCRIPTIONS

4.1

GENERAL

4.2

KDI11-F MICROCOMPUTER

. . . .

. .

e e e

e e e e e e

. . . . . ..

DMA OPERATIONS

1-1

. . . . .

e 3-12

e e

e 3-12

. . . . . . .. .. . .. .. ... . ... ..., 3-12

. e
e e e 3-13
. . . . . . . . e 3-13

. . . . .

e e e e e e e e e e e

. . . . . .

. . . . . . .

e e e
e

e e

e e e e

e e e e e e

e e 3-14

e e e 3-14
e e e e 3-15

. . . . e
. . . . . . .

4.2.1

Generzl

42.2

Basic Microcomputer Functions

. . . . . L
. . . . . . . . .. ...

42.2.1

Microprocessor Chip Set

42.2.2

Clock Pulse Generator

4223

Bus Interface and Data/Address Distribution

4224

Bus I/O Control Signal Logic

4225

Bank 7Decoder

4.2.2.6

Interrupt Control and Reset Logic

4227

Special Control Functions

42.2.8

Bus Arbitration Logic

. . . . . . . . . . . ..

4-1

4-2

e e e e

4.2

.. ..o

4-3

.. . ... .

4-3

. . . . . . . .. ... ... ...

4-4

. . . ... ... ... . ... ... ........

4-5

. . . .. ...

4-7

. . . . . . . . . ... .

. . . . . . ... ... ... ... . .....

4-7

. . . . . . . ... ... ... ... ...,

4-9

. . . . . . . . . ..o 4-10

iii

CONTENTS (Cont)
Page

4.2.3

KDI11-F Resident Memory

42.4

DC-DCPower Inverter

4.3

. . . . . . . . .. . .

. . .

e 4-13

. . . . . . . . . . . . . .

MMVI11-A 4K BY 16-BIT CORE MEMORY

e 4-14

. . . . . . . . . ... . ... . .. .. .... 4-14

4.3.1

General

43.2

Functional Description

4.3.2.1

Introduction

43.2.2

Core Addressing

43.2.3

Read/Write DataPath

. . . . . . . . . . . . . . . . 4-18

43.2.4

Timingand Control

. . . . . . . . . . . .. . . . . e 4-20

. . . . . . . .

. . . . . . . . . . . .. e 4-17

DC Protection and VccSwitch

4.3.2.6

DC-DC Inverter

4.4.1

General

4.4.2

Functional Description

General

Addressing

4.5

e e e

. . . . . .

e e e

Data Read Operation

e e e

4.5.2

Functional Description

. . . . . . . .. . .. .

. . . . . . L

4.6

This section was deleted

4.7

DLV11 SERIAL LINE UNIT

4.7.1

General

4.7.2

Functional Description

e 4-24

. . . . . . . . . . . ...

. ...

. . . . . . . . . . . .. ..

. . . . . . ..

UAR/T Operation
Baud Rate Generator

. . . . . . . . . v it

4.7.2.4

Bus Drivers and Receivers

4.7.2.5

Address Decoding

4.7.2.6

Function Decoding and Control

4.:7.2.7

Interface Control Logic

4.7.2.8

CSR Selection and Gating

4.7.2.9

Break Logic

e 4-24

. .. ... ... .. 4-27
e

e 4-27

o 4-27

s e
e e e e

47.2.3

e e 4-26

... ..., 4-26

. . . . . . . .

4.7.2.2

e e

e e e e e e

e e e e e e e e

. . . . . .

General

e e e

MS11-B 4K BY 16-BIT SEMICONDUCTOR READ/WRITE MEMORY
General

e, 4-29
e

e 4-29

4-32

e e e e

e e e e e

e 4-32

. . . . . . . . . . . ..o 4-32

. . . . . . . . . . . . ... oo 4-32

. . . . . . .. L. L 4-32
. . . . . . . ... ... ... ...

. . . . . . . . . . .«

... 4-32

L Lo 4-32

. . . . . . . . . . . . ... 4-34

. . . . . . . . . . L e 4-34

47.2.10

Reader RunLogic

4.7.2.11

EIA Interface Circuits

. .. .. ... .. ..

20 mA Loop Current Interface

4.7.2.13

-12Vinverter

General

4.8.2

Functional Description

L 4-34

. e 4-34

. . . . . . ... ... .. ... ... ... ... 4-35

. . . . . . e 4-35

DRVI11 PARALLEL LINEUNIT

4.8.1

. . . . . . . . . . . . . .

4.7.2.12

4.8

e e e e e e e e e e e

. ... ... .. ... ... ...... 4-24

. . . . . . . . . . . . . . . oo 4-24

. . . . . . .

4.5.1

4.7.2.1

. . . . . . . .

44272

44.2.3

. . . . . . . . . . ... . ... 4-23

. . . . . . . .

MRV11-A 4K BY 16-BIT READ-ONLY MEMORY

4421

e, 4-14

. . . . . . . ... 4-15

43.2.5
4.4

e e

. . . . . . . . . . .. . .. ... e 4-15

. . . . .. . . .

. . . . . ..

. . . . . . . . . . . .

e 4-35

General

Addressing . . . . . ..
e e 4-35
Function Selection . . . . . . . . . . .. 4-35

4.8.2.4

4.8.2.6
48.2.7

... oo 4-35

4.8.2.2

4.8.2.5

i e, 4-35

e e e e

4.8.2.1

4.8.2.3

. . . . . ..

e e e e e

e e e e e e

e 4-35

Read Data Multiplexer . . . . . . . . . . .. .. oo 4-38
DRCSR Functions . . . . . . . . .« o o i
it et e e 4-38
DRINBUF Input Data Transfer
. . .. .. ... ... ... ... . ..... 4-38
DROUTBUF Output Data Transfer
. . . . .. .. ... ... ......... 4-38

CONTENTS (Cont)
Page

4.8.2.8

Interrupts

48.2.9

MaintenanceMode

48.2.10
4.9

. . . . . L

Initialization

e e

e 4-38

. . . . . . . . . . . L 4-39

H780 POWER SUPPLY

. . . . . . . .

49.1

General

492

Specifications

4.9.3

Functional Description

. . . . . .

e e s e e e

e e

. . . . . . . L.

General

e e e e e

4.9.3.2

Unregulated Voltage and Local Power

4933

Basic Regulator Circuit

493.4

Overload and Short-Circuit Protection

4.9.3.5

Crowbar Circuits

4.9.3.6

Logic Signal Generation

. . . . . . . .

H780 Connections

e 4-39

e e e e e e e e

e e e 4-39

e e e e e 4-40

. . . . . . . . . . . . . . e 4-40

493.1

49.4

. . . . . . . ... Lo 4-39

e e

e e e e

e e

e 4-40

. . . . . . .. ... ... .. ...... 4-40

. . . . . . . . . . .. .. ...
. 4-42
. . . . . .. ... ... ... ...... 443

. . . . . . . . . . . . o

e e

e e e 4-44

. . . . . . . . . . . . . . . e 4-44

. . . . . . . . . . .

CHAPTER 5

USING KD11-F and KD11-J PROCESSORS

5.1

GENERAL

5.2

JUMPER-SELECTED FEATURES

i i i e e

e e e e e e

e e e

e 4-48

. . . e
e e
e e e

5.2.1

General

. . . . . .. . ... ... .

. . . . . . L

... ... .......

e e

5-1
5-1

5-1

5.2.2

Memory Refresh

. . . . . . . . . . . . .

5-1

5.2.3

Line TimeClock

. . . . . . . . .. . . . . . . . . e P

5-2

524

Power-Up Mode Selection

5.2.5

Resident Memory 4K Address Selection

. . . . .. . . .. ... . . ... .. .. ...

5.3

INSTALLATION

5.4

USING THE LSI-11 MICROCOMPUTER

. . .

5.4.1

General

5.4.2

Interrupt and Trap Prority

5.4.3

. . . . .

Halt Mode

. . . . . ... ... ... ... .......

. .

e e e e e e s e

. . .

5-4

e e e e e e e e e e e

. . . . . . . . . . ... ..

. . .

5-4

e e

5-4

. . . . . .. . .. . . ... . . . .. . . .. ...

e e e e e e e

5-4

. . . . .
e
e
e

6-1

5.5

INITIALIZATION AND POWER FAIL

CHAPTER 6

LSI-11 INTERFACE MODULES

6.1

GENERAL

6.2

DLV11 SERIAL LINEUNIT

. .. . . . .. . . .

6-1

. . . . . ...
e
e e e

6-1

6.2.1

General

6.2.2

Jumper-Selected Addressing, Vectors, and Module Operations

. . . . . . ... . ...

6-1

e e

6-1

. . . . . .. Lo

6-1

6.2.2.1

Locations

6.2.2.2

Addressing

6.2.2.3

Vectors

6.2.2.4

UAR/T Operation

6.2.2.5

Baud Rate Selection

6.2.2.6

EIA Interface

6.2.2.7

20 mA Current Loop Interface

6.2.2.8

Framing ErrorHalt

. . . . . . . .

. . . . . L

6-3

e e

6-3

. . . . . .. .. . ...

6-3

. . . . . . . . . e

6-3

. . . . . . . . .

e e

e e e e e e

e e e e e e e

. . . .. . .. .. .. ... ... ........

. . . . . . .. . ... ... . . ..

6.2.3

Installation

6.2.4

Interfacing with 20 mA Current Loop Devices

6.2.5

Interfacing with EIA-Compatible Devices

6.2.6

Programming

6.2.6.1

. . . . . . . . . .. .

5-2
5-3

6-4

. . . . . . . .. .. ... ... ....

6-4

6-3

. ...

. . . . . . . . L.

. . . . . .. . ... ... ... ......

6-5

. . . . . . . . . ..

6-5

Addressing

. . . . .. L L

6-5

CONTENTS (Cont)

6.2.6.2

Interrupt Vectors

6.2.6.3

Word Formats

6.2.7
6.3

Console Device

oooooooooooooooooooooooooooooooo

. . . . . . . . . . . 0 e

DRV11 PARALLEL LINE UNIT

6.3.1

General

6.3.2

Jumper-Selected Addressing and Vectors

6.3.2.1

. . . . . . . e

Locations

ooooooooooooooooooooooo

oooooooooooooooooooooooooooooooooooo

6.3.2.2

Addressing

6.3.2.3

Vectors

oooooooooooooooooooooooooooooooooooo

oooooooooooooooooooooooooooooooooooooo

6.3.3

Installation

6.3.4

Interfacing to the User’s Device

. . . . . . . . . .

6.34.1

General

6.3.4.2

Output Data Interface

6.3.4.3

Input Data Interface

6.3.4.4

Request Flags

e
oooooooooooooooooooooooooooo

. . . . . . .

e e

6.3.4.5

Initialization

6.3.4.6

NEW DATA READY and DATA TRANSMITTED Pulse Width Modification

6.34.7
6.3.5

. . . . . . . . . . ..

BCO8R Maintenance Cable
Programming

oooooooooooooooooooooooooooo

. . . . . . . . . ..

6.3.5.1

Addressing

6.3.5.2

Interrupt Vectors

6.3.5.3

Word Formats

. . . . ..

e e e

e e

e e
e e

e
e

oooooooooooooooooooooooooooooooo

----------------------------------

CHAPTER 7

USING MSV11-B READ/WRITE MEMORY MODULES

7.1

GENERAL

7.2

MSV11-B

. . . . . e

JUMPERS

7.2.1

Addressing

7.2.2

Reply to Refresh

. . . . . L. L.
e e

7.3

MSV11-B BUS RESTRICTION

CHAPTER 8

USING MMV11-A CORE MEMORY

. . . . . . . . . .

8.1

GENERAL

8.2

SWITCH-SELECTED ADDRESSING

8.2.1

. .o

ooooooooooooooooooooooooooooooo

. . . . e
e
oooooooooooooooooooooooooooo

ooooooooooooooooooooooooooooooooooooooooo

8.3

CHAPTER 9

USING MRV11-A READ-ONLY MEMORY

9.1

GENERAL

9.2

JUMPER-SELECTED ADDRESSING AND CHIP TYPE

. . . . e

9.2.1

General

9.2.2

Chip Type Selection

923

. . . . . .

Addressingand Reply

. . . . . . . . .

9.3

PROGRAMMING PROM AND ROM CHIPS

9.4

PROGRAMMING RESTRICTIONS

9.5

TIMING AND BUS RESTRICTION

e e e e

e e

o L

ooooooooooooooooooooooooooooo

CONTENTS (Cont)
Page

CHAPTER 10

USER-DESIGNED INTERFACES

10.1

GENERAL

10.2

BUS RECEIVER AND DRIVER CIRCUITS

10-1

10.3

PROGRAMMED INTERFACE

10-2

10.4

INTERRUPT LOGIC

10-5

10.5

DMA INTERFACE LOGIC

CHAPTER 11

SYSTEM CONFIGURATION AND INSTALLATION

oooooooooooooooooooooooooooooooooooooooooo

oooooooooooooooooooooooooooooooooooo

10-1

10-5

11-1

11.1

GENERAL

11.2

CONFIGURATION CHECKLIST

11.3

DEVICE PRIORITY

11.3.1

General

11.3.2

Priority Selection Using the H9270 Backplane

11.3.3

H9270 Backplane/MMV11-A Configuration

11-1
ooooooooooooooooooooo

ooooooooooooooooooooooooooooooooooooooooo

11-2

11-2
11-2

11-2

MODULE INSERTION AND REMOVAL

11-3

11.5

I/OCABLING

11-4

11.6

PDP-11/03 INSTALLATION PROCEDURE

11.4

... ................

11-4

11.6.1

Packaging and Mounting

11-4

11.6.2

Power Requirements

11-5

11.6.3

Environmental Requirements

11-5

LSI-11 SYSTEM INSTALLATION

11-5

11.7
11.7.1

General

11.7.2

Mounting the H9270 Backplane

11.7.3

DC Power Connections

11-5

ooooooooooooooooooooooooooooooooo

11.7.3.1

Voltage and Current Requirements

11.7.3.2

H9270 Backplane Power Connections

11.7.4

H9270 Backplane Ground Connection

11.7.5

Environmental Requirements

11.7.6

Externally Generated Bus Signals

11.7.6.1

General

11.7.6.2

BDCOK H and BPOK H

11.7.6.3

BEVNT L Signal

11.7.6.4

BHALT L Signal

11.8

SYSTEM OPERATION

11-5

11-7

11-8

. . . ..
ooooooooooooooooooooo

oooooo

11-9
11-9

oooooooooooo

11-10

nnnnnnnnnnnn

11.8.2

PDP-11/03 Power-On

11.8.3

LSI-11 Power-On

. . . ... ... ... ...

...

11-10
oooooooooooooooooooo

11-12

. . . .. .. ... .....
.

PAPER TAPE SYSTEM OPERATION

11.9.1

General

11.9.2

References

11.9.3

Loading the Absolute Loader

1194

Loading Program Tapes

oooooooooooooooooooo

. . . ... .. ... .. .......

. . .. ... ... ........

ooooooooooooooo

ooooooooooooooooo

ooooooooooo

11.94.1

General

11.94.2

Normal Loading Procedure

11.9.4.3

Relocated Loading Procedure

11944

Self-Starting Programs

11.9.5

Program Starting and Execution

. .. ... ... ... ...

. . . .. ..
ooooo

. . . . . .. ..

--------------------

oooooooooooooooooooo

vii

11-10

oooooooooooo

ASCII Character Console Printout Program

11-8
11-8

oooooooo

oooooooooooooo

General

119

. . .

[

11-5

. .

. . ... ... .........

11.8.1

11.8.4

11-5

. ... ... ... ... ...,

11-12

11-12
11-12

11-12

11-13

11-14
11-14

11-15
11-15

CONTENTS (Cont)
Page

11.10

RT-11 SYSTEM OPERATION

. . . . . . . .. .

11-15
11-15

Using the RX01

. . . . . . . . e

11-16

11.10.3

RXV11 Bootstrap

. . . . . . . . . e

11-16

11.10.3.1

General

11.10.3.2

Booting the System Using the REV11-A or REV11-C

11.10.3.3

Booting the System Via the Console Device

Using the RT-11

. . . . . . . . .

e e e e e
.

. . . ...

... ........

PERIPHERALS

APPENDIX A

MEMORY MAP

APPENDIX B

LSI-11 BUS PIN ASSIGNMENTS

APPENDIX C

7-BIT ASCII CODE

APPENDIX D

SUMMARY OF LSI-11 INSTRUCTIONS

APPENDIX E

H9270 BACKPLANE CONFIGURATIONS

APPENDIX F

BUS INTERFACE I.C. PINS

APPENDIX G

LSI-11 BUS ACCESSORY OPTIONS INSTALLATION AND OPERATION

APPENDIXH

DLVI11 I/O

Viii

. . ... ... .....

CHAPTER 12

JUMPER CONFIGURATIONS

11.10.2

. . . . . . . .

General

11.104

. . . . . . . .

11.10.1

11-16
11-16
11-16

11-17

ILLUSTRATIONS

Title

Figure No.

Page

3.1

Module Contact Finger Identification

3.2

Quad Module Contact Finger Identification

. . . . . . .. .. ... .. ... ... . ...,

3.3

LSI-11, PDP-11/03 Backplane Module Pin Identification

3-4

DATIBus Cycle

3.5

DATIO or DATIOB BusCycle

. . . . . . o

. . .. ... ... ... ... . ........

. . .. ... .. ... ... ...

. . . . . . . . . . . .

e e e e e e e e e e

e e e e e e

3-2

3-3

3-8

3-6

DATO or DATOB Bus Cycle

3.7

DMA Request/Grant Sequence

3.8

Interrupt Request/Acknowledge Sequence

3.9

Bus Line Terminations

. . . . . . . . . . . . . . L

3-10

Minimum Configurations

. . . . . . . . . . . . L

311

Intermediate Configuration

3.12

Maximum Configuration

. . . . . . . . . . . . . .

3.13

DATIBus Cycle Timing

. . . . . . . . . . . @ .

3.14

DATO or DATOB Bus Cycle Timing

3.15

DATIO Bus Cycle Timing

3.16

Interrupt Transaction Timing

3-17

DMA Request/Grant Timing

3-18

Power-Up/Power-Down Timing

4-1

KD11-F Microcomputer Logic Block Diagram

4.2

Clock Pulse Generator

4.3

LSI-11 Bus Loading and Driver/Receiver Interface

4-4

EDAL L Logic

4.5

Bus I/O Control Signal Logic

4-6

Bank 7 Decoder

4.7

Interrupt Control and Reset Logic

4-8

Special Control Functions

4.9

Bus Arbitration Logic

. . . . . . . . .

4-10

DMA Grant Sequence

. . . . . . . . . .

4-11

KDI11-F Resident Memory

4-12

MMVI11-A Core Memory Option

. . . . . . . . . . . ..

4-13

MMV11-A Logic Block Diagram

. . . . . .. . . ... ... ...

4.14

MMV11-A Core Addressing

4-15

MMV11-A Read/Write Bit DataPath

4-16

MMV11-A Timing and Control Circuits

4-17

Read-Restore Memory Cycle Timing

4-18

Read-Modify-Write Memory Cycle Timing

4-19

DC Protection and Vce Switch Circuits

4-20

DC-DC Inverter Circuit

4-21

MRVI11-A Logic Block Diagram

4-22

512 by 4-Bit Chip-Jumper Configuration

. . . ... .. ... ... ... ... ...... 4-26

423

256 by 4-Bit Chip-Jumper Configuration

. . . ... ... . ... ... ...

4-24

MSV11-B Logic Block Diagram

4-25

This figure was deleted

. . .

. . . . . . . . . .

. . . . . . . . . ot i

e e

e e st

e e e e e 3-10

e e e e e

e e

e 3-11

. . . . . . .. . .. ... ... .. ... ... 3-13
e e e e e e e e
L

e 3-14

e e e e e e e e e 3-14

. . . . . . . . . . . .. ... e 3-15
e e

e e e

e e e e e 3-15

e e e e e e e e e

3-16

. . . . . . . . . . . . .. . ... .. ... ..... 3-17

. . . . . . . . . . .
. . . .

. . . . . . . ...

e e e e e

. . . . . . . . . . . . . .

e 3-18

o oL 3-19

e 3-20

. . . . . . . . . . . .. ... ... ... 3-20
. . . . . ... ... ... ... .......

. . . . . . . . . . . . . . .
. . . .

4-3

. . . . . .. .. ... ... ... ....

e e

. . . . . . . . . . . . .

. . . . . .

4-2

e e e e e e e
e e e e

e e e

4-4

i e

4-6

e e

e e e e e e

e e e

4-7

. . . . . . . . . . . . . ... . .. . .. . .. . ...,

4-8

. . . . . . . . . . . . . .

. . . . . . . . . . . o

. . .

e 4-10
e

Lt e

. . . . . . . . . . . . . .

e e

e e e e
@

e 4-11

e e e e e e e e 4-11

e 4-12

i i i it 4-14

e e

.. .. . .

. . . . . . . . . . . . . . . .

..., 4-16

e 4-17

. ... 4-19

. . . . . . . . . ... ... ... ... .. .... 4-21

. . . . . . . . . .. . .. ... .. ..

... ..., 4-22

. . . . . .. .. ... ... ... ........ 4-22

. . . . . . . . . . . .. . .

. . . . . . . . . . . .

L
e

4-23
e

e e 4-24

. . . . . . .. .. . . .. . ... . . ... .. ... 4-25
....... 4-27

. . . . .. ... .. ... ... ... ... ... . .... 4-28

4-26

DLV1I1 Logic Block Diagram

. . . . . . . . .. .. .. ... .. ... .. .. ... ... 4-33

427

DRVI1I Logic Block Diagram

. . . . . . . . . ... . . ... .. .

4.28

H780 Power Supply Block Diagram

. 4-36

. . . . . . . . . . . . . . . . .. 4-41

4-29

Unregulated Voltage and Local DCPower

4-30

Basic Regulator Circuit

4.31

Overload and Short-Circuit Protection

. . . . . . . . .. .. ... .. ......... 4-41

. . . . . . . . . . . .

e 4-42

. . . . . . .. .. ... ... . ... ........ 443

ILLUSTRATIONS (Cont)

Figure No.

Title

4-32

Crowbar Circuit

4-33

Logic Signal Generation

. . . . . . . . . e
e

4-34

Power-Up/Power-Down Sequence

4-35

DC ON/OFF Circuit Timing

4-36

H780 Connections

. . . . . . . . . . ... o

5-1

Jumper Locations

5-2

Mode 0 Power-Up Sequence

oooooooooooooooooooooooooooooo

ooooooooooooooooooooooooooooooooo

. . . . . ...
e

5-3

Mode 2 Power-Up Sequence

6-1

DLV11 Serial Line Unit

ooooooooooooooooooooooooooooooooo

ooooooooooooooooooooooooooooooooooo

6-2

DLV11 Jumper Locations

6-3

DLVI1 Addresses

DLV11 Interrupt Vectors

6-5

Active 20 mA Current Loop Interface

6-6

Passive 20 mA Loop Jumper Configuration

. . . . . . . . .

. . . . . . . . . . . e
e

6-7

EIA Interface

6-8

DLV11 Word Formats

6-9

DRVI11 Parallel Line Unit

. . . . . . .. ... ... . ... ... ...

...

. . . . . . . . . e,
. . . . . . . . . . . . .

6-10

DRV11 Jumper Locations

6-11

DRVI11 Device Address

oooooooooooooooooooooooooooooooooo

ooooooooooooooooooooooooooooooooooo

6-12

DRVI11 Vector Address

6-13

J1 or J2 Connector Pin Locations

6-14

DRVII Word Formats

7-1

MSV11-B 4K by 16-Bit Read/Write Memory

7-2

MSVI11-B Jumper Locations

7-3

MSV11-B Address Format/Jumpers

8-1

MMV11-A 4K by 16-Bit Core Memory

8-2

Bank Address Switch Locations

8-3

MMVI11-A Addressing

9-1

MRV11-A Read-Only Memory

9-2

MRV11-A Jumper Locations

9-3

MRV11-A Address Word Formats

9-4

PROM/ROM Chip Pin Addressing

10-1

Bus Driver and Receiver Equivalent Circuits

10-2

Typical Bus Driver Circuit

10-3

Programmed I/O Interface

104

Dual Interrupt Interface

. . . . . . . . . . . o
. . . . . . .

e e e

. . . . . . e

. . . . . . . . . . . . .

e e e e

ooooooooooooooooooooooooooooo

----------------------------

ooooooooooooooooooooooooooooooo

. . . . . . . . . . . e
oooooooooooooooooooooooooooooooo

. . . . . . . . . . ... Lo
oooooooooooooooooooooooooooooo

. . . . . . . . . . . .

. i

ooooooooooooooooooooooooo

. . . . . . . . . . . . .« o o e

. . . . . . . . . . . .. L
...................................

10-5

DMA Arbitration Logic

11-1

Typical Configuration LSI-11 Backplane — Processor and Option Locations

. . . . . . . . ... o

11-2

H9270 Backplane/MMV11-ACore

11-3

Module Installation in the H9270 Backplane

. . . . . . . . . . . . . e

114

H9270 Backplane

11-5

PDP-11/03 Cabinet Mounting

. . . . . . . . .. . L

11-6

H9270 Backplane Mounting

11-7

H9270 Side Mounting

. . . . . . . . . . .

11-8

H9270 Rear Mounting

. . . . . . . . . . . . . .

11-9

H9270 Top and Bottom Mounting

oooooooooooooooooooooooooooooooo

e e

ILLUSTRATIONS (Cont)

Figure No.

Title

11-10

H9270 Backplane Terminal Block

11-11

H9270 Backplane Ground Wire

11-12

H9270 Backplane Air Flow

Page

. . . . ... ... ... ... ... ... ........ 11-7
. . . . . . . ..

DELETED

-« « « « « « « « « « =

11-8

. . . . . . . . . . . . 11-8

11-13

H9270 Backplane Printed Circuit Board

11-14

Power-Up Sequence

11-15

Power-Down Sequence

11-16

BDCOK H Signal Routing Diagram

. . . . . . .. .. ... ... ... ........

11-8

. . . . . . . . . . . e

11-9

. . . . . . . . . . .. ..
. . . . ..

11-9

... .. ... .. ... .........

11-10

. . e

11-10

. . . . . . . . . . .. ... ..

11-12

11-17

BEVNT L Signal

11-18

Sample Console Printout

12-1

Direct 20 mA Current Loop Interface

12-2

Telephone Line Interface ViaData Sets

12-3

Telephone Line Interface Via AcousticCouplers

. . . . . . .

. . . . . . . . . . ... ... . ... ... ... ..
.

. . . . .. . .. .. ... ... .........

. . . . . . . . . .. ... ... ......

12-1
12-1

12-1

TABLES
Table No.

Title

2-1

LSI-11 Modules Power Requirements

3.1

Backplane Pin Assignements

4.1

LSI-11 Modules

DLV11 Function Decoding

4.3

DRVI11 Device Function Decoding

5.1

Summary of KD11 Jumpers

5.2

KD11 Factory Jumper Configuration

Power-UpModes

6-1

Baud Rate Selection

6-2

Word Formats

6-3

DRV11 Input and Output Signal Pins

6-4

BC11K Signal Cable Connections

Page

. . . . . . . ... ... ... ... ... ... ...

. . . . . . . ... ..

. . . . . . .

3-4
4-1

. . . . . . . . .. . .. . .. . . e 4-34
. . . . . . .. . .. ... . .. ... ...

..., 4-37

. . . . . . . . ...
. . . . . . . . .. ... ...

... . ... .....

. . . . . . . . . . e
. . . . . .

. . . . .

2-4

. . .

5-1
5-1

5-2

. ... L

6-3

. e

6-7

. . . . . . . .. . ... . ... ... ... ..... 6-11
. . . . . . . . . . . . . . ...
.. 6-12

6-5

BCO8R Maintenance Cable Signal Connections

6-6

Word Formats

9-1

MRVI11-A Chips

9.2

PROM/ROM Chip AddressingData

. . . . . . .. ... ... ... ...... 6-14

. . . . . . ..., 6-15

. . . . . .

9-1

. . . . . . . ... .. .. .. ...

9.3

Data Pin Assignments

10-1

LSI-11 Bus Driver and Receiver Characteristics

... .

. . . . . . ... L.

. . . . . . . . . . .. ... ... ..... 10-1

11-1

PDP-11/03 Input Power Electrical Specifications

112

H9270 Backplane Standard Power Connections

11-3

H9270 Backplane Battery Backup Power Connections

114

Console Power-Up Printout (or Display)

12-1

LSI-11 Peripheral Options

. . . . . .. . .. ... ... ...... 11-4
. . . . . . . ... ... ... .......
. . . . . . .. . ... ... .....

. . . . . .. ... .. .. ... ... . .....

. . . . . . . . . . .. .. . . . ...

9-4

11-7
11-7

11-11
12-2

CHAPTERI1

INTRODUCTION

1.1

Chapters >—9

GENERAL

Use

of the

Various

LSI-11

(including

jumper

This manual contains technical data that will enable

Modules

LSI-11 and PDP-11/03 microcomputer users to inter-

configurations,

face and use LSI-11 system components effectively.

and programming information)

Before reading the detailed technical content of this

Chapter 10

manual, the user should become familiar with the basic

Chapter 11

characteristics of the LSI-11 processor, as described in

User-Designed Interfaces
System Configuration and In-

stallation

the LSI-11, PDP-11/03 Processor Handbook.
Chapter 12

1.2

interfacing,

Peripherals (including the basic
devices available and the re-

SCOPE

quired LSI-11 interface mod-

This manual contains hardware descriptions and in-

ule, and cables required for

formation for using LSI-11 system modules, including
system configuration, installation,

each)

and interfacing.

The manual is organized as follows:

In addition, quick reference information is included in

appendixes. This information includes a memory map,

LSI-11 bus pin assignments, the 7-bit ASCII code, and

Chapter 1

Introduction

Chapter 2

LSI-11 and PDP-11/03 System

a summary of LSI-11 instructions.

Overview
Chapter 3

LSI-11Bus

Chapter 4

LSI-11

Module

1.3

REFERENCES

The LSI-11, PDP-11/03 Processor Handbook is a re-

quired reference manual for using LSI-11 system comDescriptions

ponents. In addition, standard hardware and interface

(including functional theory of

components are listed and described in the Hardware/

operation)

Accessories Catalog and the Logic Handbook.

i-1

CHAPTER 2
LSI-11 SYSTEM OVERVIEW

2.1

Systems are configured using the basic modules de-

GENERAL

scribed in the following paragraphs.

All LSI-11 and PDP-i1/03 systems are configured by
selecting various LSI-11 module options which can be
installed in a backplane. Although individual system

2.3

requirements (in which the LSI-11 system functions as

This paragraph focuses on the KD11-F (processor and

LSI-11 MICROCOMPUTER

a controller and/or data processor) may vary greatly in

4K semiconductor memory), which is the basic LSI-11

each application, LSI-11’s modular concept allows for

microcomputer. The KD11-J has all of the basic fea-

efficient use of the microcomputer in a compact, cost-

tures of the KD11-F, except for the semiconductor

effective, flexible system design. The PDP-11/03 is a

memory; the

packaged LSI-11 system, including a processor, 4K

separate module.

MMV 11-A core memory is included as a

memory, enclosure, H9270 backplane, and H780 power
Each KD11-F features:

supply.

In general, all LSI-11 and PDP-11/03 systems include

A low-cost, powerful processor for integra-

the KD11-F or KD11-J microcomputer. The KD11-F

tion

is a single 8.5 by 10 inch module that contains the

computer system.

LSI-11

microprocessor

and

16-bit

semiconductor read/write memory. The KD11-J uses

into

any

small-

medium-sized

Direct addressing of 32K 16-bit words or

64K 8-bit bytes (K = 1024).

the same microcomputer module as the KD11-F; howe

ever, it is supplied with the MMV11-A 4K by 16-bit

Efficient processing of 8-bit characters without the need to rotate, swap, or mask.

core memory instead of the semiconductor memory.
Either type of basic LSI-11 or PDP-11/03 system can

be expanded by adding various memory and peripheral

Asynchronous operation that allows system
components to run at their highest possible

device interface options.

speed; replacement with faster devices means

faster operation without other hardware or
2.2

software changes.

SYSTEM CONFIGURATIONS
®*

LSI-11 systems can be configured using one of three
general approaches:
1.

ease and flexibility in configuring systems.
®

Modules only: The user purchases only the

Modules and backplane: The user purchases

in a larger system.
LSI-11 system in a box:
or

KDI11-J

The user pur-

memory,

DLVII1

processor
serial

line

and

unit,

Eight

general-purpose

registers that

available for data storage,

pointers,

are
and

accumulators. Two are dedicated: SP and

chases a PDP-11/03 system. It includes the
KDI11-F

Direct memory access for high data rate

devices inherent in the bus architecture.

an LSI-11 subsystem that is easily mounted

Hardware memory stack for handling struc-

tured data, subroutines, and interrupts.

basic module(s).
2.

A modular component design that provides

PC.

bus

structure that provides

position-

H9270 backplane, and an H780 power sup-

dependent priority as peripheral device inter-

ply installed in a rack-mountable enclosure.

faces are connected to the I1/0 bus.

2-1

Fast

interrupt

response

without

device

177777 are placed on the bus. These addresses are

polling.

®*

eliminating the need for bank address decoding on

A powerful and convenient set of program-

ming
®

normally used for addressing nonmemory devices, thus

periphera! device interface modules.

instructions.

jumper-selected

power-up

mode

that

The bus provides a vectored interrupt capability for

enables restart through a power-up vector,

any interface device. Hence, device polling is not required in interrupt processing routines. This results in

console Octal Debugging Technique (ODT)

microcode subset, or a bootstrap program.

a considerable savings in processing time when many
devices requiring interrupt service are interfaced along

On-board 4K RAM

An ODT microprogram that controls all

the bus. When a device receives an interrupt grant

(acknowledge), the KD11-F inputs the device’s inter-

manual entry/display functions previously

rupt vector. The vector points to two addresses which

pertormed by a control panel through a
serial

ASCII

device

(optional)

which

contain a new processor status word and the starting

address of the interrupt service routine for the device.

capable of transmitting and receiving ODT
commands and data.

¢
2.4

One bus signal line functions as an external event inter-

Compactsize (only8.5by10in.).

rupt input to the KD11-F module. This signal line can

be connected to a frequency source, such as a line fre-

1/0 BUS CONCEPT

quency, and used as a line time clock (LTC) interrupt.

The LSI-11 I/0 bus is simple, fast, and easy to use as

A jumper on the KD11-F module enables or inhibits

this function. When enabled, the device connected to

interface between

memory,

and

the

peripheral

LSI-11

microcomputer,

interface

modules.

this line has the highest interrupt priority external to

comprises 17 control lines and a 16-line data/address

the processor. Interrupt vector 100, is reserved for this

bus. All modules connected to this bus receive the same

function, and an interrupt request via the BEVNT line

interface signals.

causes new PC and PS words to be loaded from

locations 100, and 102,.

Address/data and control lines are open-collector lines

which are asserted low. The microcomputer module is

Memory refresh of dynamic MOS read/write memory

capable of driving six device locations along the bus.

is accomplished by bus signals. Refresh operation is

Peripheral interface or memory modules can be in-

controlled by either the processor module microcode or

stalled in any location along this bus.

a user-supplied intelligent DMA device.

Both address and data words (or bytes) are time multiplexed over 16 bus lines. For example, during a pro-

The processor can be placed in the Halt mode by as-

grammed data transfer, the LSI-11 microcomputer

serting one bus signal. This allows peripheral devices

first asserts an address on the bus for a fixed time.

or a separate switch to invoke console ODT microcode

After the address time has been completed, the proces-

operation.

sor performs either an input or output data transfer;

the actual data transfer is asynchronous and requires a

Power-up/power-down sequencing is controlled by two

response from the addressed device. Bus synchroniza-

bus signals. One signal, when in its true state, implies

tion and control signals provide this function.

that primary power is normal. The second signal is in
its true state when sufficient dc power is available (and

Control signal lines include two daisy-chained grant

voltages are normal) for normal system logic operation.

signals which provide a priority-structured I/0 system.

These signals are produced by circuits contained in the

The highest priority device is the module electrically

H780 power supply (PDP-11/03 only) or by the user’s

closest to the KD11-F (or KD11-J) module. Higher

system

priority devices pass a grant signal to lower priority

(circuits

external

the

LSI-11

system

components).

devices only when not requesting service. (Memory
options or devices which do not use these signals must

Direct memory access (DMA) operation is controlled

connect the chain.)

by three bus signals. Logic on the processor module,

The KD11-F contains a memory address register and

which is normally bus master, arbitrates DM
A requests

4K bank address decoder for its resident memory,

and grants bus mastership to the highest priority device

which can be assigned to bank O or bank 1. Bank 7 is

requesting the bus. Priority is position-dependent

also decoded when addresses ranging from 160000 to

through the use of a daisy-chained DMA grant signal.

2-2

2.5

MEMORY OPTIONS

Both interface units contain all required control/status

Memory options are available for expanding memory

registers, interrupt control logic, and bus interface

to 28K. The basic LSI-11 microcomputer is supplied

logic. The user can easily assign unique device and

withread/write memory. KD11-F’s memory consists of

vector addresses for each device by changing the

a 4K dynamic MOS array which is physically located

jumpers on each interface module.

on the processor module. KD11-J’s memory is a 4K

magnetic core array contained on a separate module;

Peripheral interface options include:

the processor module supplied with the KD11-J contains no semiconductor memory components.

DLVI1I— Serial line unit interfaceonan 8.5 by S

Optional memory modules include:

bus. Jumpers select crystal-controlled baud rates

inch module. Requires one device location on the

(50—9600 baud) and serial word format, inMRVII-AA — 4K by 16-bit programmable read-

cluding number of stop bits, number of data

only memory on an 8.5 by S inch module. Re-

bits, and even, odd, or no parity bit. Optional

quires one device location on the I/O bus. Can be

interface cables include the BCOSM, which con-

configured using either 256 by 4-bit or 512 by 4-

nects the DLV11 to 20 mA current loop peri-

bit field programmable or masked ROMs for a

pheral devices, and the BCOSC, which connects

maximum capacity of 2048 or 4096 16-bit words.

the DLV11 to EIA-compatible devices (modems)
via a Cinch DB-25P connector.

MMVII-A — 4K by 16-bit core memory on an

DRVI11— General-purpose parallel line unit in-

8.5 by 10 by 0.9 inch module. Requires two de-

terface on an 8.5 by S inch module. Requires one

vice locations on the I/O bus when installed in

devicelocationon the bus. Two 40-pin connectors

the backplane (preferred location slots A4-D4).

are included on the module for user interface

This allows a daughterboard (part of the MMV-

application. One is the 16-bit input and the other

11-A) to extend slightly beyond the backplane

is the 16-bit output. Optional interface cables

without using additional device locations. If not

are

installed in this location, the MMV 11-A requires

described

the

Hardware/Accessories

Catalog.

four device locations because of the additional
module thickness (0.9 inch instead of 0.5 inch for
all other modules).

2.7

BACKPLANE, POWER SUPPLY, AND

HARDWARE OPTIONS
Backplane, power supply, and hardware options pro-

MSVII-B — 4K by 16-bit dynamic MOS read/

vide a convenient means for configuring the LSI-11

write memory on an 8.5 by S inch module. Re-

system. An LSI-11 system usually requires an inter-

quiresonedevice locationonthel/O bus. Refresh

connection scheme. The H9270 backplane assembly is

is automatically performed by the KD11-F proc-

the most convenient to use. It is prewired for the LSI-11

essor microcode or by an external device.

I70 bus pinning and can accept one KD11-F microcomputer and up to six LSI-11 interface or memory
modules. It includes a card guide assembly which

2.6

PERIPHERAL INTERFACE OPTIONS

provides mechanical stability for the modules. Power

Two basic interface modules are used for serial and

and ground are applied to the backplane via a screw-

parallel programmed 1/0 transfer between the LSI-11

terminal block.

bus and peripheral devices. The DLV11 is a serial line

unit used for serial S- to 8-bit data transfers between a

Power can be obtained from the system in which the

device and the bus. Itinterfaces either EIA-compatible

LSI-11 subsystem is installed, or the H780 (115 or 230

or 20 mA current loop devices to the bus using optional

Vac input) power supply (included in PDP-11/03 sys-

cables which select the type of serial interface desired.

tems) can be used. The power supply provides the re-

The

cables

are

completely

pin-

quired regulated voltages for all LSI-11 modules con-

compatible with available modems, DECwriter, DEC-

nected to the backplane. In addition, it generates the

scope, and teletypewriter options. The DRV11 is a

necessary bus signals to initiate the KD11-F or KD11-]J

connector-

and

general-purpose parallel line unit interface which is

power-up or power-fail processor sequence. Hardware

capable of 16-bit input and

options include standard hardware accessories listed in

16-bit output parallel

transfers to/from user devices.

DIGITAL’s Hardware/Accessories Catalog.

2-3

2.8

POWER REQUIREMENTS

MRV11-AA

The power requirements for LSI-11 system modules

S5S%x8.50x%0.5

are given in Table 2-1.

MMV11-A

10x8.50x%x0.9

Table 2-1

DLV11

LSI-11 Modules Power Requirements

Sx8.50%0.5

Designation

+S5V £5% | +12V 3%
Typ|

Max|

DRV11

Typ | Max

KD11-F

1.8A

|2.4A

|0.8A

|1.6A

KD11-]

6.4A

|9.0A

|1.2A

|[1.5A

DLV11

1.0A | 1.6A

DRV11

0.9A | 1.6A

5x8.50%0.5

Electrical

[180mA|2S0mA

Input Logic Levels

TTL Logical Low:

MRV11-AA (with-

out memory chips)

[0.4A | 0.6A

MRYV11 (with4K
memory chips)

MSVI11-B

Output Logic Levels
2.8A

|4.1A

0.6A

|1.2A

MMV11-A (standby) | 3.0A

TTL Logical Low:

|0.3A

7.0A

0.4 Vdc max

TTL Logical High: 2.4 Vdc min

[0.7A

0.2A

Bus Receivers

MMV11-A

(operating)

0.8 Vdcmax

TTL Logical High: 2.0 Vdc min

Logical Low:

0.6A

1.3 Vdcmax,-10uA maxat(QV

Logical High: 1.7 Vdc min, 80uA max at 2.5V
Bus Drivers

The input power requirements for PDP-11/03 systems

Logical Low:

are:

Logical High: 25,A maxat3.5V

0.8 Vdcmaxat70 mA

PDP-11/03-AA or-BA
100-127 Vac (115 Vac nominal), SO = 1 Hz or
60 = 1 Hz, single phase, 400 W maximum (in-

Environmental

cluding options) (190 W typical)

Ambient Temperature, PDP-11/03 System:

Operating: 5° t040° C
PDP-11/03-AB or-BB

Ambient Temperature, LSI-11 modules:

200-254 Vac (230 Vac nominal), SO =+ 1 Hz or

Operating: 5° t0 S0° C (41° t0 122° F)

60 = 1 Hz, single phase, 400 W maximum (in-

Nonoperating: —40° to 66° C (—40° to

cluding options) (190 W typical)

2.9

+ 150° F)
Derate at 6°C /1000 ft. above 8000 ft.

GENERAL SPECIFICATIONS

Dimensions (in.)

Humidity

KD11-F

10 to 90 percent, noncondensing

10.5 x 8.50 x 0.5
MSV11-B

Air Flow

Sx8.50%0.5

200 linear ft./minute min. (modules only)

2-4

CHAPTER3
THE LSI-11 BUS

3.1

3.2

CHOOSING AN I/0 TRANSFER TYPE

DEVICE PRIORITY

Before interfacing the processor with any peripheral
device, the designer must determine the type of I/0
transfer that would be best suited for the application:

from the processor. When two or more devices request

programmed I/0 transfers, DMA, or interrupt-driven

microcomputer

transfers.

(acknowledge). The microcomputer can be inhibited

Each device has an I/0 priority based on its distance
interrupt service, the device electrically closer to the
the

interrupt

grant

priority to 4 in the PS word. Bit 7 in the new PS word

double-operand instructions. The instruction can be
used to input or output a 16-bit data word or an 8-bit
byte. By including the device’s address as the effective
source or destination address, the user selects the
input or output operation. In many instances, the

should be a 1. If further interrupts are to be serviced,
the processor’s priority should be 0, and bit 7 in the new
PS word should be a 0. Consequently, interrupts can be
nested to any level. Factors to consider when assigning
device priorities are:

programmer inputs a byte from the device’s con-

receive

from issuing more grants by setting the processor’s

Programmed 1/O transfers are executed by single- or

trol/status

will

determine that the

device has input data ready or that it is ready to

Device Operating Speed — Data from a
fastdeviceisavailablefor only a short period;

accept the processor’s output data.

highest priorities are usually assigned to fast

DMA transfers are the fastest method of transferring

devices to prevent loss of data and to prevent

data between memory and a device. They can occur

the bus from being tied up by slower devices.

between processor bus cycles and do not alter processor

Ease ofData Recovery — If data from a de-

status in any way. Addressing, controlling the size of

vice is lost, recovery may be automatic, may

the data block (number of word or byte transfers in the

require manual intervention, or may be im-

operation), and type of transfer are under the control of

possible to recover; highest priorities are as-

the requesting device. The processor does not modity

signed to devices whose data cannot be

data being moved in the DMA mode. Thus, blocks of

recovered.

data can be moved at memory speeds via the DMA
transfer mode. The processor sets up these conditions

before the DMA transfer is executed.

Service Requirements — Some devices can-

not function without help from the processor, while DMA devices can operate in-

Interrupts

allow

the

processor

continue

dependently and require only minimal proc-

programmed operation (sometimes called a back-

essor intervention; devices requiring con-

ground program) without waiting for a device to be-

tinual help from the processor for servicing

come ready to transfer data. When the device does

are assigned to lowest priorities to prevent

becomeready, it interrupts the processor’s background

tying up the processor.

program execution and causes execution of a device
interrupt service routine. After the device’s service

Both address and data are multiplexed onto the 16

routine has been executed, the background program is

BDAL lines. In addition, individual control signals se-

restored and program execution resumes at the point

quence programmed I/0O operations, direct memory

where it was interrupted.

access (DMA), and processor interrupts. Any bus-

3-1

compatible modulecan beinserted into anybus location

of the module maintain continuity of grant signals

and

BIAKI L to BIAKO L and BDMGI L to BDMGO L.

still

receive

interface

signals;

however,

the

module’s priority, which is position-dependent along

These daisy-chained signals are described later.

the bus, will change.
Slots, shown as ROW A and ROW B in Figure 3-1, in-

3.3

MODULE CONTACT FINGER

clude a numeric identifier for the side of the module.

IDENTIFICATION
DIGITAL plug-in (FLIP CHIP) modules, including

The component side is designated side “1”’ and the
solder side is designated side ‘“2.”” Letters ranging from

LSI-11 modules, all use the same contact finger (pin)

A through V (excluding G, I, O, and Q) identify a

identification system. The LSI-11 I/O bus is based on
the use of double-height modules. These modules plug

particular pin on a side of a slot. Hence, a typical pin is
designated as:

into a two-slot bus connector, each containing 36 lines
per slot (18 each on component and solder sides of the
circuit board). Although the LSI-11 processor module
and core memory module are quad-height modules

Slot (Row)

that plug into four connector slots, only two slots (A

Identifier

and B) are used for interface purposes on the processor

“Slot B”’

BE?2

f IL

Module Side Identifier
‘““solder side”’

Pin Identifier

module. Etched circuit jumpers on the unused portion

“Pin E”

ROW A

SIDE 1 oF

50 N

COMPONENT SI

ROW B

~
/ .

N
A
j

PIN BV1

PIN Bv2
CP-1403

Figure3-1

Module Contact Finger Identification

Note that the positioning notch between the two rows of

Individual connector pins, viewed from the underside

pins mates with a protrusion on the connector block for

(wiring side) of a backplane, are identified as shown in

correct module positioning.

Figure 3-3. Only the pins for one bus location (two

slots) are shown in detail. This pattern of pins is re-

peated eight times on the H9270 backplane, allowing
Quad-height modules are similarly pin numbered.

the user to install one LSI-11 microcomputer module

They are identified in Figure 3-2.

(four slots) and up to six additional two-slot modules.

N®~=zO«a®WOw=>x><5zZ5 o® 4 n

ROW IDENTIFIER

9oL5215L/S)l o1

LOCATION

ocPo oLoO

OHO

3-3

wogWCo
OMO

Figure 3-2

2 1 LDy

\‘

oRO

Figure 3-3

o -

A2RGgoRENoV-o=TSoSWUA\NSo=PNRO,MMOV&O9OTyYoooo7.GMfl
ToS5wQNAM[N/7Sy2«]AN&“S©FoN4eW’Ao-N‘oé<W0NR3.\oviA-STO@—RTE=ONos<o<]fSG5o=l©O—oy«/=folNS/\avNO/=TTn“.>eGeORVte(AwDS)a.Tne—.GOf/lA\Vof/llNxC/VS-WS<e(HVtI/s.STUET>[°SSe)¢N.T0o/eR)%Nu.N<-L<NNSt.s\RGA&,MH/uA}m(W.o‘AI)CA\LDO©N\fapo-—S _\N\WS\<oO©=—A-iWo</-oTM/‘oV/.O\-.TOV\(\V\/oo9%=\MO=©A xOJSoCo=!E)
N N

>, - —-

« w . TX > -

< a

OooDOFooHOO eE®o)JCo)S' M‘¢Ao,io)Oyo€. . o2©R3ISrA,vS<.ROAIYA\VlAJeOc(f&/> T«oQva-0Yug}oPofoeS oz-t—o
Iron

SIDE |

I 3

COMPONENT SIDE

sN-

l/'

2NEeRCwSo

LSI-11, PDP-11/03 Backplane Module Pin Identification
CP-1416

Quad Module Contact Finger Identification

O (]]
s

wn o w

CP-1773

3.4

BUS SIGNALS

respectively. Applicable bus cycle timing and specifi-

H9270 backplane pin assignments are listed and

cations are discussed in Paragraphs 3.12, 3.13, and

described in Table 3-1. Only slots A and B are listed.

3.14.

However,

they

are

identical

slots

and

Table 3-1
Backplane Pin Assignments
Bus

Mnemonic

Description

AAl
AB1

BSPAREI1
BSPARE?

:
Bus Spare (Not Assigned. Reserved for DIGITAL use.)

AC1
AD1

BADI6
BAD!7

:
.
Extended address bits (not implemented)

AE1

SSPAREI1

AF1

SSPARE?2

AH1

SSPARE3

AJl

GND

Ground — System signal ground and dc return.

AK1

MSPAREA

Maintenance Spare — Normally connected on the backplane at each option

ALl

MSPAREA

location (not bused connection).

AM1

GND

Ground — System signal ground and dc return.

AN1

BDMRL

Direct Memory Access (DMA) Request — A device asserts this signal to request

Special Spare (Not assigned, not bused. Available for user interconnections.)

bus mastership. The processor arbitrates bus mastership between itself and all
DMA devices on the bus. If the processor is not bus master (it has completed a

bus cycle and BSYNC L is not being asserted by the processor), it grants bus

mastership to the requesting device by asserting BDMGO L. The device responds by negating BDMR L and asserting BSACK L.

AP1

BHALT L

Processor Halt— When BHALT L is asserted, the processor responds by halting
normal program execution. External interrupts are ignored but memory refresh

interrupts (enabled if W4 on the processor module is removed) and DMA request/grant sequences are enabled. When in the halt state, the processor executes the ODT microcode and the console device operation is invoked.

ARI1

BREF L

Memory Refresh — Asserted by a processor microcode-generated refresh interrupt sequence (when enabled) or by an external device. This signal forces all
dynamic MOS memory units to be activated for each BSYNC L/BDIN L bus
transaction.

CAUTION
The user must avoid using multiple DM
A data transfers [Burst or

“hog’’ mode] during a processor-generated refresh operation so that
a complete refresh cycle can occur once every 1.6 ms.

AS1

PSPARE3

Spare (Not assigned. Customer usage not recommended.)

ATI

GND

Ground — System signal ground and dc return.

AU1

PSPAREI1

Spare (Not assigned. Customer usage not recommended.)

AV1

+ 3B

+5 V Battery Power — Secondary +5 V power connection. Battery power can
be used with certain devices.

BA1

BDCOKH

DC Power OK — Power supply-generated signal that is asserted when there is
sufficient dc voltage available to sustain reliable system operation.

Table 3-1 (Cont)
Backplane Pin Assignments
Bus

Mnemonic

BB1

BPOKH

Description
Power OK — Asserted by the power supply when primary power is normal.

When negated during processor operation, a power fail trap sequence is ini-

tiated.
BC1

SSPAREA4

BD1

SSPARES

BE1

SSPARES6

BF1

SSPARE7

BH1

SSPARES

BJ1

GND

Ground — System signal ground and dc return.

BK1

MSPAREB

Maintenance Spare — Normally connected on the backplane at each option

BL1

MSPAREB

location (not a bused connection).

BM1

GND

Ground — System signal ground and dc return.

BN1

BSACKL

This signal is asserted by a DMA device in response to the processor’'s BDMGO

Special Spare (Not assigned, not bused. Available for user interconnections.)

L signal, indicating that the DMA device is bus master.
BP1

BSPARE6

Bus Spare (Not assigned. Reserved for DIGITAL use.)

BR1

BEVNTL

External Event Interrupt Request — When asserted, the processor responds

(if PS bit 7 is 0) by entering a service routine via vector address 100,. A typical
use of this signal is a line time clock interrupt.

BSi

PSPARE4

Spare (Not assigned. Customer usage not recommended.)

BT1

GND

Ground — System signal ground and dc return.

BU1

PSPARE2

Spare (Not assigned. Customer usage not recommended.)

3V1

+35

+ S5V Power — +5 Vdc system power.

AA2

+35

+3SV Power — Normal + 5 Vdc system power.

AB2

-12

-12 V Power — -12 Vdc (optional) power for devices requiring this voltage.

NOTE
LSI-11 modules which require negative voltages contain an inverter circuit (on each module) which generates the required volt-

age(s); hence, -12 'V power is not required with DIGITAL-supplied
options.
AC2

GND

Ground — System signal ground and dc return.

AD?2

+12

+12V Power — + 12 Vdc system power.

AE2

BDOUTL

Data Output —BDOUT, when asserted, implies that valid data is available on

BDALO—1S5 L and that an output transfer, with respect to the bus master device, is taking place. BDOUT L is deskewed with respect to data on the bus. The

slave device responding to the BDOUT L signal must assert BRPLY L to
complete the transfer.
AF?2

BRPLYL

Reply — BRPLY L is asserted in response to BDIN L or BDOUT L and during

IAK transactions. It is generated by a slave device to indicate that it has input
dataavailable onthe BDAL bus or that it has accepted output data from the bus.

Table 3-1 (Cont)
Backplane Pin Assignments
Bus

Mnemonic

AH2

BDINL

Description

Data Input — BDIN L is used for two types of bus operations:
1.

When asserted during BSYNC L time, BDIN L implies an input transfer
with respect to the current bus master, and requires a response (BRPLY L).
BDIN L is asserted when the master device is ready to accept data from a

slave device.

When asserted without BSYNC L, it indicates that an interrupt operation
is occurring.

The master device must deskew input data from BRPLY L.

AJ2

BSYNCL

Synchronize — BSYNC L is asserted by the bus master device to indicate that it

has placed an address on BDALO—1S L. The transfer is in process until
BSYNC L is negated.

AK?2

BWTBTL

Write/Byte — BWTBT L is used in two ways to control a bus cycle:

Itisasserted duringthe leading edge of BSYNC L to indicate that an output
sequence is to follow (DATO or DATOB), rather than an input sequence.

2.
AL2

BIRQL

ItisassertedduringBDOUT L, in a DATOB bus cycle, for byte addressing.

Interrupt Request — A device asserts this signal when its Interrupt Enable and
Interrupt Request flip-flops are set. This signal informs the processor that a

device has data to input to the processor or it is ready to accept output data. If
the processor’s PS word bit 7 is 0, the processor responds by acknowledging the
request by asserting BDIN L and BIAKO L.
AM?2

BIAKIL

AN2

BIAKOL

Interrupt Acknowledge Input and Interrupt Acknowledge Output — This is

an interrupt acknowledge signal which is generated by the processor in response
to an interrupt request (BIRQ L). The processor asserts BIAKO L, which is
routed to the BIAKI L pin of the first device on the bus. If it is requesting an in-

terrupt, it will inhibit passing BIAKO L. If it is not asserting BIRQ L, the device
will pass BIAKI L to the next (lower priority) device via its BIAKO L pin and the
lower priority device’s BIAKI L pin.
AP2

BBS7L

Bank 7 Select — The bus master asserts BBS7 L when an address in the upper

4K bank (address in the 28-32K range) is placed on the bus. BSYNC L is then

asserted and BBS7 L remains active for the duration of the addressing portion
of the bus cycle.
AR?2

BDMGIL

DMA Grant-Input and DMA Grant-Output— This is the processor-generated

AS2

BDMGOL

daisy-chained signal which grants bus mastership to the highest priority DMA
device along the bus. The processor generates BDMGO L, which is routed to

the BDMGI L pin of the first device on the bus. If it is requesting the bus, it will
inhibit passing BDMGO L. If it is not requesting the bus, it will pass the
BDMGTI L signal to the next (lower priority) device via its BDMGO L pin. The

device asserting BDMR L is the device requesting the bus, and it responds to the
BDMGI L signal by negating BDMR, asserting BSACK L, assuming bus
mastership, and executing the required bus cycle.
CAUTION

DMA device transfers must be single transfers and must not interfere with the memory refresh cycle.
AT2

BINITL

Initialize — BINIT is asserted by the processor to initialize or clear all devices
connected to the 1/0 bus. The signal is generated in response to a power-up
condition (the negated condition of BDCOK H).

3-6

Table 3-1 (Cont)
Backplane Pin Assignments
Bus

Mnemonic

Description

AU?2

BDALOL

Data/Address Lines — These two lines are part of the 16-line data/address bus

AV?2

BDALIL

over which address and data information are communicated. Address information is first placed on the bus by the bus master device. The same device then
either receives input data from, or outputs data to the addressed slave device or
memory over the same bus lines.

BA2

+ S5V Power — Normal + 5 Vdc system power.

BB2

-12

-12 V Power —-12 Vdc (optional) power for devices requiring this voltage.

BC2

GND

Ground — System signal ground and dc return.

BD2

+12

+12V Power— +12 V system power

BE2

BDAL2L

BF2

BDAL3L

BH?2

BDAIAL

BJ2

BDALSL

BK?2

BDALG6L

BL2

BDAL7L

BM?2

BDALSL

Data/Address Lines — These 14 lines are part of the 16-line data/address bus

BN2

BDAL9L

previously described.

BP2

BDALIOL

BR2

BDALI11L

BS2

BDAL12L

BT?2

BDALI13L

BU?2

BDALI14L

BV?2

BDALISL

3.5

3.5.1

BUS CYCLES

transfer. The DATIO cycle provides an efficient means

General

of executing an equivalent read-modify-write operation

Every processor instruction requires one or more 1/0

by making it unnecessary to assert an address a second

operations. The first operation required is a data input

time.

transfer (DATI), which fetches an instruction from the
location addressed by the program counter (PC or R7).

3.5.2

This operation is called a DATI bus cycle. If no addi-

T'he sequence for a DATI operation is shown in Figure

Input Operations

tional operands are referenced in memory or in an I/0

3-4. DATI cycles are asynchronous and require a re-

device, no additional bus cycles are required for in-

sponse from the addressed device or memory. The ad-

struction execution. However, if memory or a device is

dressed memory or device responds to its input request

referenced,

input/output

(BDIN L) by asserting BRPLY L. If BRPLY is not

(DATIO or DATIOB), or data output transfer (DATO

asserted within 10us (max) after BDIN L is asserted,

or DATOB) bus cycles are required. Between these bus

the processor terminates the cycle and traps through

cycles, the processor can service DMA requests. In

location 4.

additional

DATI,

data

addition, the processor can service interrupt requests
only prior to an instruction fetch (DATI bus cycle) if

Note that BWTBT L is not asserted during the address

the processor’s priority is zero. (PS word bit 7 is 0.)

time, indicating that an input data transfer is to be
executed.

The following paragraphs describe the types of bus

cycles. Note that the sequences for I/0 operations be-

A DATIO cycle is equivalent to a read-modify-write

tween processor and memory or between processor and

operation. An addressing operation and an input word

I7Odevice are identical. DATO (or DATOB) cycles are

transfer are first executed in a manner similar to the

equivalent to write operations, and DATI cycles are

DATI cycle; however, BSYNC L remains in the active

equivalent to read operations. In addition, DATIO

state after completing the input data transfer. This

cycles include an input transfer followed by an output

causes the addressed device or memory to remain

SLAVE

BUS MASTER

(MEMORY OR DEVICE)

(PROCESSOR OR DEVICE)

ADDRESS DEVICE/MEMORY
®

Assert BDALO-15 L with

Assert BBS7

address and

if the

address is in the 28 - 32Krange
®

Assert BSYNC L
\
\

\
\

DECODE ADDRESS

Store ‘“device selected”’
operation

REQUEST DATA
®

Remove the address

from BDALO-15 L

and negate BBS7 L

Assert BDINL

~—

INPUT DATA
®

Place data on BDALO-15 L

Assert BRPLY L

TERMINATE INPUT TRANSFER
e

Accept data and respond by
negating BDIN L

TERMINATE BUS CYCLE

Negate BSYNC L

Figure 3-4

OPERATION COMPLETED
e

Terminate BRPLY L

11.3138

DATIBusCycle

selected, and an output data transfer follows without
any further addressing. After completing the output

Like the input operations, failure to receive BRPLY L
within 10us after asserting BDOUT L is an error, and
results in a processor time-out trap through location 4.

byte transfer; hence, this cycle is shown as DATIOB.

Note that BWTBT L is asserted during the addressing
portion of the cycle to indicate that an output data
transfer is to follow. If a DATOB is to be executed,
BWTBT L remains active for the duration of the bus
cycle; however, if a DATO (word transfer) is to be executed, BWTBT L is negated during the remainder ot

transfer, the device terminates BSYNC L, completing
the DATIO cycle. The actual sequence required for a
DATIO cycle is shown in Figure 3-5. Note that the
output data transfer portion of the bus cycle can be a
3.5.3

Output Operations

The sequence required for a DATO or the equivalent
output byte (DATOB) bus cycle is shown in Figure 3-6.

the cycle.

3-8

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
®

Assert BDALO-15 L with

address
®

Assert BBS7 L and if the
address is in the 28 - 32K range

Assert BSYNC L
\

\
\

DECODE ADDRESS

Store “device selected”’
operation

/
/

anm—

REQUEST DATA

Remove the address from
BDALO -15L

Assert BDIN L

—~—
\

INPUT DATA

Place data on BDALO-15 L

Assert BRPLY L

TERMINATE INPUT TRANSFER
®

Accept data and respond by

terminating BDIN L
\
\

\
\

COMPLETE INPUT TRANSFER

/ /

Remove data

Terminate BRPLY L

OUTPUT DATA
®

Place output data on BDALO-15 L

(Assert BWTBT

L if an output

byte transfer)
e

Assert BDOUT L
\

TAKE DATA

/ /

Receive data from BDAL lines
Assert BRPLY L

TERMINATE OUTPUT TRANSFER aa
®

®
®

Terminate BDOUT L, and remove
data from BDAL lines

\
\

OPERATION COMPLETED

TERMINATE BUS CYCLE

Negate BSYNC L

J—

cm—

Terminate BRPLY L

(and BWTBT L if in

11-3139

a DATIOB bus cycle)

Figure 3-S

DATIO or DATIOB Bus Cycle

3-9

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
®

Assert BDALO-15 L with

address and

Assert BBS7 L (if address

Assert BWTBT L (write

is in the 28 - 32K range)
cycle)

Assert BSYNC L
\

TM~

~—

\
\

DECODE ADDRESS
e

Store '‘device selected’’

operation

OUTPUT DATA
®

—

Remove the address from

BDALO-15L

and negate BBS7 L and BWTBT L

(BWTBT L remains active if
DATOB cycle)

~——

e Place data on BDALO-15 L
Assert BDOUTL

\
\
\
\

TAKE DATA
®

Receive data from BDAL lines

Assert BRPLY L

/
TERMINATE OUTPUT TRANSFER

Remove data from BDALO-15L
and negate BDOUT L

OPERATION COMPLETED
o

Terminate BRPLY L

/
TERMINATE BUS CYCLE
e

Negate BSYNC L (and BWTBT L

if a DATOB bus cycle)

11-3140

Figure 3-6

DATO or DATOB Bus Cycle

3-10

3.6

DMA OPERATIONS

dressing,

timing,

and

control

signal

generation/

DMA 1/0 operations involve a peripheral device and

response are provided by

system memory. A device can transfer data to or from

device’s DMA interface module; the processor is not

the 4K memory on the processor module or any read/

involved with address and data transfers during a

write memory module along the bus. The actual se-

DMA operation.

logic

contained

the

quence of operations for executing the data transfer
once a device has been granted DMA bus control is as

The required DMA sequence is shown in Figure 3-7. A

previously described for input and output I/O bus

device requests the I/O bus by asserting BDMR L.

cycles, except the DMA device, not the processor, is

After completing the present bus cycle, the processor

bus master

responds by asserting BDMGO L, allowing the device

(controls the operation).

Memory ad-

LS1-11 PROCESSOR

(MEMORY IS SLAVE)

DEVICE
REQUEST BUS
e

GRANT BUS CONTROL
e

Near the end of the current

bus cycle (BRPLY L

Assert BDMR L

/ -

is negated),

assert BDMGO L and inhibit
new processor generated

BSYNC L for the duration
of the DMA operation.

\
\

ACKNOWLEDGE BUS MASTERSHIP
~—a
/

TERMINATE GRANT SEQUENCE
®

‘/

® Wait for negation of

BSYNC L and BRPLY L

Assert BSACK L

Negate BDMR L

—

Negate BDMGO L and

wait for DMA operation
to be completed
\

\
\
\
\

EXECUTE A DMA DATA

\ TRANSFER (DEVICE IS
BUS MASTER)
®

Address memory and transfer

data as described for DATI,

DATIO, DATIOB, DATO,
DATOB bus cycles

Release the bus by
terminating BSACK L

_—
/
/

OPERATION

RESUME PROCESSOR

(no sooner than negation
of last BRPLY L) and
BSYNC L.

Enable processor-generated

BSYNC L (Processor is

Bus master) Or issue
another grant if BDMR L
is asserted.

Figure3-7

DMA Request/Grant Sequence

3-11

to become bus master. It also inhibits further processor

The

generation

processor-

required for interrupts is shown in Figure 3-8. A device

initiation of a new bus cycle. The device responds by

requests interrupt service by asserting BIRQ L. The

BSYNC

preventing

interface

control

and

data

signal

sequence

asserting BSACK L and negating BDMR L, causing

processor can acknowledge interrupt requests only

the processor to terminate BDMGO L; the device is

between instruction executions by generating an active

now bus master and it can execute the required data

(low) BDIN L signal, enabling the device’s vector re-

transfer in the same manner described for a DATI,

sponse. The processor then asserts the BIAKO L signal.

DATIO, DATIOB, DATO, or DATOB bus cycle.

The first device on the bus receives this daisy-chained

When the data transfer is completed,

device

signal at its BIAKI L input. If it is not requesting ser-

returns bus master control to the processor by termi-

the

vice, it passes the signal via its BIAKO L output to the

nating the BSACK L and BSYNC L signals.

next device, and so on, until the requesting device re-

ceives the signal. The device that did not pass the

3.7

INTERRUPTS

BIAKO L signal responds by asserting BRPLY L (low)

Interrupts are requests made by peripheral devices

and placing its interrupt vector on data/address bus

which cause the processor to temporarily suspend its

lines BDALO—1S5 L. Automatic entry to the service

present (background) program execution to service the

routine is then executed by the processor as previously

requesting device. Each device which is capable of

described.

requesting an interrupt has a service routine which is

NOTE

automatically entered when the processor acknowl-

edges the interrupt request.

If a device fails to assert BRPLY L in response

After completing the

to BDIN L within 10 u sec, the processor enters

service routine execution, program control is returned

the Halt state.

to the interrupted program. This type of operation is
especially useful for the slower peripheral devices.

3.8

BUS INITIALIZATION

Devices along the I/0 bus are initialized whenever the

A device can interrupt the processor only when inter-

system dc voltages are cycled on or off, or when a

rupts are enabled and the device is the closest device to

RESET instruction is executed. Initialization during

the processor along the I/O bus. The processor’s

the power-on/power-off sequence is described in Para-

priority in the PS word is 4 when external interrupts are

graph 3.9. When the RESET instruction is executed,

disabled and 0 when external interrupts are enabled.

the processor responds by asserting BINIT L for ap-

Device priority is highest for devices electrically closest

proximately 10us. Devices along the bus respond to the

to the processor along the bus.

BINIT L signal, as appropriate, by clearing registers

and presetting or clearing flip-flops.

Any device that can interrupt the processor can also
interrupt the service routine execution of a lower

3.9

priority device if the processor’s priority is O during that

Power status signals BPOK H and BDCOK H must be

execution; hence, interrupt nesting to any level is

asserted or negated in a particular sequence as dc

possible with this interrupt structure. Each device

operating power is applied or removed.

normally contains a control status register (CSR),

BDCOK H and BPOK H are passive (low). As dc

which includes an interrupt enable bit. A program

voltages rise to operating levels, BINIT L is asserted by

must set this bit before an interrupt request can

the processor module. Approximately 3 ms (min) after

actually be granted to a device.

POWER-UP/POWER-DOWN SEQUENCE

Initially,

+5V and +12V power are normal, an external signal
source, or the H780 power supply in PDP-11/03

An interrupt vector associated with each device is

systems, produces an active BDCOK H signal; the

hard-wired into the device’s interface/control logic.

processor responds by negating BINIT, and waits for

This vector is an address pointer that allows automatic

BPOK H. The BPOK H signal, produced by an ex-

entry into the service routine without device polling.

ternal signal source or the H780 power supply, goes
true (high) 70 ms (min) after BDCOK H goes high. The

When an interrupt request is issued via the external

processor responds by executing the user-selected

event signal line, the processor automatically services
the request via location 1004 ; it does not input a vector

the console microcode is executed.

This interrupt function is normally used for a line time

During a power-down sequence, the external signal

power-up routine (Chapter S); if BHALT L is asserted,

address as done for other external interrupt devices.

clock input based on the frequency of the local ac

source first negates BPOK H, causing the processor to

execute the power-fail trap (PC at 024, PS at 026).

power (S0 or 60 Hz).

3-12

DEVICE

PROCESSOR

INITIATE REQUEST

STROBE INTERRUPTS
e

Assert BDINL

‘

Assert BIRQL

RECEIVE BDIN L

e Store “‘interrupt selected’’
in device

GRANT REQUEST
e

Pause and assert
BIAKO L

RECEIVE BIAKI L
®

Receive BIAK | L and inhibit

BIAKOL

v
»

Place vector on BDAL 0-15 L

Assert BRPLY L

Terminate BIRQ L

RECEIVE VECTOR & TERMINATE

REQUEST
¢

Input vector address

Terminate BDIN L and BIAKO L

COMPLETE VECTOR TRANSFER
®

Terminate BRPLY L

»
PROCESS THE INTERRUPT

Save interrupted program PC
and PS on stack

| oad new PC and PS from
vector addressed location

Execute interrupt service

11-3142

routine for the device

Figure 3-8

Approximately

(max)

later,

Interrupt Request/Acknowledge Sequence

the

interface module when the Framing Error Halt is
enabled (Paragraph 6.2.2.8). Note that when in the
Halt mode, the processor arbitrates DMA requests,
and refresh operations. Thus, in addition to bus transactions between the processor and the console device,

processor

initializes the bus by asserting BINIT L in response to

the external signal negation of BDCOK H.
3.10

HALT MODE

bus transactions can occur for DMA and refresh.

The BHALT L bus signal can be asserted low to place
the processor in the Halt mode. When in the Halt
mode, the RUN indicator (PDP-11/03 only) is ex-

3.1

tinguished, interrupts external to the processor module

Memory refresh operations are required when any

MEMORY REFRESH

are ignored, and the processor executes the console

dynamic MOS memory devices are used in a system.

ODT microcode. Although the user could assert this

These memory devices are included on KD11-F and

line by a separate switch or a custom module, it is

MSV11-B modules. Memory refresh is normally con-

normally asserted by the

trolled by the processor microcode, which is automatically executed once every 1.6 ms. However, refresh

HALT/ENABLE

switch

(PDP-11/03 only) or the user-designated device’s SLU

3-13

could be controlled by a user-supplied DMA device on

Bus Drivers and Receivers

the bus. (For example, when used in an intelligent

Recommended Bus Drivers

terminal application, the refresh logic could be in-

Type

cluded on the user’s DMA interface module.)

NAND gates (Refer to specifications in Table

957,

P/N

DEC

8881-1,

quad 2-input

10-1.)

A complete refresh operation requires 64 BSYNC/
BDIN transactions which must be completed within 2

Recommended Bus Receivers

ms. The processor (or other device controlling the re-

Type 956, P/N DEC 8640, quad 2-input NOR

fresh operation) first asserts BREF L for each BSYNC/

gates (Refer to specifications in Table 10-1.)

BDIN transaction during the addressing portion of

each refresh operation. BREF L causes all dynamic

Recommended Bus Transceivers

MOS memory devices to be simultaneously enabled

Type DEC 8641, quad unified bus transceiver.

and addressed, overriding local bank selection circuits.

Refresh is then accomplished by executing 64 BSYNC/

3.13

BDIN transactions, in a manner similar to the DATI

BUS CONFIGURATIONS

In the following descriptions, a unit load is equal to one

bus cycle, incrementing the “row’’ address (bits 1—6)

bus receiver and two bus drivers and less than 10 pF of

once for each transaction. Address bit 0 is not signifi-

circuit board etch. Bus terminations are shown in

cant in the refresh operation. When refresh is con-

Figure 3-9.

trolled by processor microcode, the operation takes approximately 130us.

+5V

Note that only one dynamic MOS memory device is required to assert BRPLY L during the refresh BSYNC/
BDIN transactions. This should be performed by the

250 O

slowest device on the bus. MSV11-B modules each

6800

contain a jumper which the user can insert to prevent

the module from asserting BRPLY L during refresh
operations. The slowest memory device will normally
be the MSV11-B module located the greatest electrical

BUS LINE
TERMINATION

38380
1%

Figure 3-9

distance from the processor module along the bus.

3.12

120
Q

BUS LINE
TERMINATION

CP-1828

Bus Line Terminations

Minimum Configuration (Figure 3-10)
1.

BUS SPECIFICATIONS

The processor terminates the bus lines to Zt

= 250 Q.

Electrical

Refer to electrical specifications listed in Paragraph 2.9.

Ten-inch maximum backplane wire (each

bus line for a 4 by 4 backplane), 6 unit loads
or less.

NOTE
All bus lines are open-collector, resistor-

Intermediate Configuration (Figure 3-11)

terminated to a 3.4 V nominal.
1.

The processor terminates the bus lines to

7t = 250 Q.

[

BACKPLANE WIRE

10"MAK
{

T
ONE
UNIT

2508

(

]
ONE
UNIT

LOAD

ONE
UNIT

LOAD

3.4V

PROCESSOR
Figure3-10

6 UNIT LOADS

cP-1829
Minimum Configurations

3-14

BACKPLANE WIRE

14" MAX.

—

((_
)
)

ONE
UNIT

2508

LOAD

ONE
UNIT

LOAD

ONE
UNIT

LOAD

120

3.4V

—

3.4V

UNIT LOADS

PROCESSOR

TERM
o

Figure 3-11

CP-1830

Intermediate Configuration
BACKPLANE

WIRE

8" MAX.
{
)

2500

ONE

UNIT

LOAD

2500

3.4V

—

3.4v

5 UNIT LOADS MAX.

PROCESSOR

CABLE/TERM

BACKPLANE WIRE

8"MAX.
{

]

ONE
UNIT
LOAD

CABLE

—

ADDITIONAL

ONE
UNIT
LOAD

—~

CABLE

6 UNIT LOADS MAX.

CABLES

8 BACKPLANES

BACKPLANE

WIRE

8"MAX.
{ (

)}

ONE

UNIT

UNIT
LOAD

LOAD

CABLE

1208
+

.
6

3 4V

UNIT LOADS MAX.

NOTES
:
1. THREE CABLES (MAX.),15ft.

TOTAL

LENGTH.

(MAX.)

TERM

2.15 UNIT LOADS TOTAL (MAX.)

Figure 3-12

Maximum Configuration

Fourteen-inch maximum

backplane wire
(each bus line for a 9 by 4 backplane), 15

backplanes); 6 unit loads maximum each
backplane, 15 unit loads total (maximum);

unit loads or less.

daisy-chained on 2 ft (minimum) 120 Q
cable, three cables maximum, total cable

Anadditional 120 Q termination is required.

length not exceeding 15 ft.

Maximum Configuration (Figure 3-12)
1.

CP-1831

The processor terminates the bus lines to
Zt = 250 Q.

3.14

Eight-inch maximum backplane wire on
each backplane (each bus line for 4 by 4

Two additional terminations (one 250 Q
and one 120 Q ) are required.

BUS SIGNAL TIMING

Bus signal timing requirements at master and slave
devices are shown in Figures 3-13 through 3-18.

3-15

ADDR

T/R DAL

150ns

T SYNC

—fl 10,&&5

(4)

—X

DATA

e— 200 ns MAX—J

(4)

MIN

/
¢———
{50 ns MIN

200ns MIN —»

DIN

300ns MIN ——————
R

RPLY
—o’150nleN_J

‘—

'._100nsMIN

BS7

(4)

T WTBeT

(4)

RITDAL

(4)

ADDR

L—

TIMING AT

MASTER DEVICE

(4)

DATA

L—125ns MAX

R SYNC

(4)

L-lOOns MAX

(4)
\

75ns

l¢e————150ns MIN

MIN

150ns
MIN

!‘—300 ns MIN ——————»f
T

RPLY
—.l

BS7

(4)

75ns MIN

(4)
—>

WTBT

25ns MIN

(4)

TIMING AT SLAVE DEVICE

NOTES:
.

Timing shown ot Master and Slave Device

Bus Driver inputs and Bus Receiver Qutputs.

2. Signal name prefixes are defined below:
T =
R =

Bus Driver Input
Bus Receiver Qutput

Bus Driver OQutput and Bus Receiver Input

Don't care condition.

signal names include a "B'' prefix.

CP-1774

Figure 3-13

DATI Bus Cycle Timing

3-16

Ons MIN '4-

DAL

SYNC

(4) X

ADDR

150ns

"_MIN "I MIN [
/|
—

DOUT

RPLY

-»>
T

BS7

(4)

DATA

100ns

100ns |.

TM MIN
I<—100ns MIN

&—175 ns MIN

150ns MIN—>

I‘_

L—ZOOns MIN ——»

300ns MIN ———

r— 100ns MIN

(4)

—-l 150 ns MIN je—
T

WTBT

(4)

ASSERTION = BYTE

LISO ns MIN+{ ROnS L-

DAL

(4)

SYNC

—TM

DOUT

ADDR

25ns

—TM MIN

—
/

MIN

DATA

e— 25ns MIN
e

MASTER DEVICE

[

—

L—ZSnsMIN
\

\\
"

—+| 150
ns MIN [e—

MIN

RPLY

(4)

F——100nsMIN ——ol-——l50nsMIN—+

25ns
T

(4)

— | 100ns MIN L—

TIMING AT

300ns MIN ———»f
\

—D’ 75 ns MIN
R

BS7

WTBT

25ns MIN 4

i)_/L-

75ns ]
MIN

—>

ASSERTION = BYTE

l0—25 ns MIN

(4)

25ns MIN

TIMING AT SLAVE DEVICE

NOTES:
I.

Timing shown at Master and Slave Device

Bus Driver Inputs and Bus Receiver Qutputs.
2.

Signal name prefixes are defined below:
T

Bus Driver Input
Bus Receiver Qutput

Bus Driver Output and Bus Receiver Input

signal names include a "B" prefix.
4 Don't care condition.
CP-1775

Figure3-14

DATO or DATOB Bus Cycle Timing

3-17

10-150 ns MIN
R/T DAL

T SYNC

(4)

ZSSQ’L—

DATA X (4) X

DATA

(4)

100 ns MIN
|

J
100ns MIN

r—

150 ns

T DOUT

175n

__M|N -

MIN

200 ns MIN—

e 150ns MIN—O‘

T DIN

R RPLY

MIN "

300ns

150 ns

"‘l MIN [

T BS7

—

le— 100 ns MIN

—{ 100 ns MIN ‘-—

T WTBT (4>\‘

(4)

)(

ASSERTION= BYTE

(4)

le— 150 ns MIN
TIMING

R/T DAL

(4)x ADDRX

R SYNC

R DOUT

—

(4)

L-25ns MIN

DATA

(4)

L-40nsMIN

DATA

L—25ns MIN

(4)

! MAX F‘

150ns MIN e

/
_

ns MIN
—={ 100

25ns MIN— l‘-

«— 75ns MIN s

—»>

MASTER DEVICE

la— | 50 ns MIN —»

DIN

*\\\\

T RPLY
—.]

|¢—150ns MIN— / e— 300 ns MIN —

X)\ \_

e— 75ns MIN

BS7

——‘

e— 75ns MIN

R WTBT (4>\

(4)
—>

e 25ns MIN

ASSERTION = BYTE

—»

r—zsns MIN

(4)

25ns MIN
TIMING AT SLAVE DEVICE

NOTES:

Timing shown at Requesting Device

Signal name prefixes are defined below:

Bus Driver Inputs and Bus Receiver Outputs.

T =
R =

Bus Driver Input
Bus Receiver Output

Bus Driver Qutput and Bus Receiver Input

signal names include a "B" prefix.

4. Don't care condition.

CP-1776

Figure 3-15

DATIO Bus Cycle Timing

3-18

T IRQ

INTERRUPT LATENCY
MINUS SERVICE TIME

/
—D‘

150 ns MIN. (&—

R DIN
R TAKI

T RPLY

\
——I 125 ns MAX. |o—

T DAL

R SYNC

100 ns

VECTOR

MAX.

(UNASSERTED)

BS7

(UNASSERTED)
NOTES:
1.

Timing shown at Requesting Device Bus Driver Inputs and Bus Receiver Outputs.

Signal Name Prefixes are defined below:
T = Bus Driver Input
R = Bus Receiver Qutput

3. Bus Driver Output and Bus Receiver Input signal names include a "B" prefix.
CP-1777

Figure3-16

Interrupt Transaction Timing

3-19

—.1

SECOND
REQUEST

— DMA LATENCY
—r—7
S
77
v

T DMR

\/ /s Sy
{4

—>

O ns MIN.
——
i
——

DMG

T SACK

\4
ld—

250 ns MIN.—/8»

rsoe T LLNLL
|

vreeee

250ns MIN —»|

N\ N\ N
l

T DAL

(ALSO BS7,
WTBT, REF)

0 ns MIN

ADDR

—>

O ns MIN——-I

O ns MIN

"— 300 ns MAX

—»

L——> '4-100nsM X
A

DATA

NOTES:

Timing shown at requesting device bus driver inputs and bus receiver outputs.

Signal name prefixes are defined below:
T = Bus Driver Input
'
R = Bus Receiver Output

3. Bus Driver Output and Bus Receiver Input signal names include a "B" prefix.
cCP-1778

Figure 3-17

BINIT L

BPOK

DMA Request/Grant Timing

¢——3 ms MIN

DC POWER

! Max L

3 ms

1pus

70msMIN |e
BDCOK H

MAX

_.l afm I.__

L—4 ms MIN —

-.l 70ms MIN

L———Bms MIN —————»{ 5 usMIN '-—

\_f
POWER UP

SEQUENCE

NORMAL

- POWER "

POWER DOWN

SEQUENCE

POWER UP

SEQUENCE

NORMAL

POWER

CP-1779

Figure 3-18 Power-Up/Power-Down Timing

3-20

CHAPTERA4

LSI-11 MODULE DESCRIPTIONS

4.1

LSI-11 modules covered in this chapter are listed in

GENERAL

Table 4-1. Note that a separate description for the

This chapter contains detailed descriptions of each

LSI-11 module. The level of coverage is sufficient to

KD11-J microcomputer is not provided; it comprises

enable users to interface

the

the same M7264 module as the KD11-F microcom-

their

systems

with

PDP-11/03 or LSI-11 using standard LSI-11 modules

puter, except that a resident semiconductor memory is

or user-designed interfaces. Refer to Chapter 3 for de-

not supplied.

tailed bus timing information.

module is supplied with the KD11-J option.

Instead, the MMV11

Table 4-1

LSI-11 Modules

Module

Option

Number

KD11-F

M7264

Description

Module Option

Para. No.

LSI-11 microcomputerand | 4.2

4K semiconductor memory

KD11-J

M7264-YA,

LSI-11 microcomputerand | 4.2

H223,

4K core memory

G6S3
KEV-11

—

EIS/FIS processor chip

4.2

MMV11-A

H223, G653

4K by 16-bit core memory

4.3

MRV11-A

M7942

4K by 16-bit PROM

4.4

MSV11-B

M7944

4K by 16-bitdynamicread- | 4.5

write memory
DLV11

M7940

Serial line unit

4.7

DRV11

M7941

Parallel line unit

4.8

Power Supply

4.9

H780-A and
H780-B

4-1

core

memory

4.2
4.2.1

Figure4-1. KD11-F microcomputers features are given

KD11-F MICROCOMPUTER

in Paragraph 2.3.

General

NOTE

The KD11-F microcomputer is contained on a single
8.5 by 10 inch printed circuit board (M7264). The
module includes all basic microcomputer functions
common to both the KD11-F and KD11-J microcomputers and a resident 4K by 16-bit semiconductor
read/write memory. KD11-F functions are shown in

The following description reflects the circuits

shown in drawing CS M7264 Rev. E.

AP2
(@] BBS7 L
BDALY L

V28] sDALT L

BE2
BANK 7

DRIVERS

CHIP

WDAL® - 3H
1/0

BUS/

MEM READ

FAST

¢
=

DAT
Uy

DINX
MU

O-21L |

READ

ADDRESS

MICRO-

INTERNAL

ROM

CONTROL

linsTRuCTION|

RESIDENT

MEMORY

TIMING &

BDAL12 L
BDAL13 L

[B] BDAL14 L

18] epaL15 L

BV2

AND WRITE

DATA

‘

(2)

BS2

(KD11-F ONLY)

SIGNALS

CHIPS

5] epaLtoL

BT2

DATA

PROCESSOR

BP2

BR2_§yepaLtt L

DALZ-1S H

BDAL
6 L

B] BDAL7 L

2 8] BDALS L
BN2 18] spAL9 L

RECEIVERS

WDAL@-15H

—

BL2

BUS

DATA

B| BDALS L

BK2

PROCESSOR

Q-15¢

8] 80AL3 L
8] soaLa L

8J2

DECODER
—

8] BDAL2 L

BF2
BH2

we
H
RPHI-4

AJ2 8] BsYNC L

017

AKZ%@ BWTBT L

CONTROL

2 »{B] BDIN

AH2

1/0

| PrROCESSOR

BUS

—{B] BRPLY L

CHIP

KEV-11

EIS/FIS

0-21L |

MICROCODE

CHIP

BA1

RESET

BRI

BUS
ARBITRATION
LOGIC

AN1 8] BOMR L
BN!_ 5] Bsack L
AS2 18] BDMGOL

SPECIAL

AR! (8] BREF L

CONTROL

FUNCT IONS

18-21L

-9V

—— PH1-4 L

PULSE

GENERATOR

PH1-4 -

AN2 (8] BI1AKO L

'
R

CLOCK

{B] BEVNT L

ALZ%BI BIRQ L

)

{8] BDCOK H

APt —{B8] BHALT L

LoGIC

| opTiONAL |

B! 8] sPoK H

INTERRUPT

CO:LRDOL

r————"

— TM

- 5ve—]

H
DIvB (O) H

DC - DC

POWER

AT2_ (5] BINIT L
+12V
12VA__

BDZ

AJ,:] 12V

AD2

+5v

«—AA2,BAZ 1 4

M1,BT1,
) gy
1,8C2,801,8M1,BT1,.001
AC2,A
INVERTER | AC2,AJ1,AM1,AT1,BC2,BJ1,B

1
11-3143

Figure4-1

KD11-F Microcomputer Logic Block Diagram
4-2

4.2.2

Thedatachip contains the data paths, logic, arithmetic

Basic Microcomputer Functions

Basic functional blocks of the LSI-11 microcomputer

logic unit (ALU), processor status bits, and registers

are shown in Figure 4-1 and described in the following
paragraphs. The KD11-F’s resident memory is described separately (Paragraph 4.2.3).

that are most familiar to PDP-11 and LSI-11 users.

Registers include the eight general registers (RO—R7)

and an instruction register. The user’s program has

access to all general registers and processor status (PS)

4.2.2.1 Microprocessor Chip Set — The main
function contained on the processor module is the
microprocessor chip set. This chip set includes a control

bits. All PDP-11 instructions enter this chip via the

chip, a data chip, and two microinstruction ROM
chips (microms). In addition, an optional KEV-11
microm that contains EIS/FIS microcode can be installed on the module. Microprocessor chips
communicate with each other over a special 22-bit
microinstruction bus, WMIBO0-21 L. All address and
data communication between the microprocessor chips
and other processor module functional blocks is via the
data chip and the 16-bit data/address lines,

processor over this 16-bit bus.

WDAL bus. Data and addresses to and from the
microprocessor are also transferred to and from the

CAUTION
Donotremove processor chips from their sockets.
Improper handling could permanently damage
the chips.

WDALO-15 H (from the data chip).
4.2.2.2

Processor module control signals interface with the

Clock Pulse Generator — The clock pulse

generator produces four nonoverlapping clock signals

microprocessor chips via the control chip. Eight input

for processor timing and synchronization. A voltage-

and five output microprocessor control signals provide

controlled oscillator generates a basic 10 MHz CK H

this function.

signal.

Timing and synchronization of all microprocessor

Maintenance clock gates receive and distribute the

chips (and all processor module functions) are con-

basic CK H signal to a two-stage counter and an RC

trolled by four nonoverlapping clock generator signals

filter circuit. The two-stage counter outputs are de-

(Paragraph

coded by the four-state decoder, producing the basic

4.2.2.2).

Typical

operating

speed

approximately 400 ns (100 ns each phase), based on a
10

M Hz oscillator signal.

four nonoverlapping clock phases. The pulse produced

on the leading edge of each basic clock pulse inhibits
the decoder for 10 ns, preventing the overlap of each

The control chip generates a sequence of microin-

phase. Each of the four phase signals (RPH1 through

struction addresses which access the microinstruction

RPH4) are positive-going, MOS-compatible 100 ns

microm chips. The addressed microinstruction is then

(nominal) pulses which are bused to each of the micro-

transferred to the data and control chips. Most of the

processor chips through resistors. PH1 L through PH4

microinstructions are executed by the data chip; how-

L and PH1 H through PH4 H are similarly timed; how-

ever, various jumps, branches, and I/0 operations are

ever, they are TTL-compatible for distribution else-

executed in the control chip.

where on the module.

l——* DIVB (O) H (DC-DC INVERTER CLOCK)

10 MH z (APPROX)

2 -STAGE

COUNTER

MAINT

+3V

MAINT

CLOCK

MCKD L

GATES

CK
SIGNALS

———————’

DECODER

DISTRIB
NON-OVERLAP

MCKL——%——-.

4 -STATE

RPH1-4

PHI-4

AND

A
Al

0SC

PULSE

+5V

11-3144

Figure4-2

Clock Pulse Generator

4.2.2.3

Bus Interface and Data/Address Distribu-

EDAL L is a control signal which enables the 16-bit

tion
— Al LSI-11 processor module communication to

data/address bus drivers. When in the active state,

and from external 1/0 devices and memories is ac-

EDALL gates WDALO—15 H onto the BDALO—15 L

complished using the LSI-11 bus 16-bit data/address

bus.

lines (BDALO-1S L) and bus control signals. The processor module interfaces to the bus using bus driver/

EDAL L is generated by the logic shown in Figure 4-4.

receiver chips, as shown in Figure 4-3. Each DEC 8641

During a processor-controlled address/data output

chip contains four open-collector drivers and four

bus cycle, or during the addressing portion of a proc-

high-impedance

essor-controlled

receivers.

Each

driver

output

input

bus

cycle,

SACK

and

DMG(1) L are passive (high). The passive signals are

common to a receiver input. Hence, either processor
output data (from the driver outputs) or input data

gated, producing a low (passive) DMGCY H signal.

(from the bus) can stimulate bus receiver inputs.

This signal is inverted and gated with the passive DIN L

signal, producing the active EDAL L signal. During a
DMA cycle in which data in the processor module’s

resident 4K memory is to be read by a DMA device,

Note that all four drivers in a chip are enabled or dis-

BANK OR REF H goes high; this signal is gated with

abled by a pair of DRIVER ENABLE L inputs. A high

DINR H and DMG CYCLE H to produce the active

input will inhibit all four drivers; when both enable

EDAL L signal.

inputs are low, the drivers are enabled and output data
is gated onto the bus. Signals which control bus drivers

DMGCY H and INIT (1) H are processor module logic

include EDAL L, INIT (1) H, and DMGCY H. False
states

enable

certain

control

signals

which

control signals which inhibit certain bus drivers during

are

an Initialize or DMA operation.

described later.

Bus

drivers

*SVz: 25040
BUS

—d

ENABLE L{ —0

3300

DRIVER

OUTPUT DATA/

DRIVER

are

enabled when these signals are in the false (low) state.

CONTROL BIT (H) »—]

/ DRIVER ENABLE H

6809
BUS

RECEIVER

LOGICAL:
1=0.4V

TYP.

0:=33V TYP

—-

I1/0 BUS

—> %;'\TTA(G:ONTROL

INPUT DATA/
CONTROL BIT (H)
11-3145

Figure4-3

LSI-11 Bus Loading and Driver/Receiver Interface

DINR H j
BANK OR REF

—» DMGCY H

SACK L

DMG(1)

EDAL L

L
DIN L —
CP-1826

Figure4-4

EDAL L Logic

A list of bus driver output signals and their respective

Sync flip-flop sets, producing an active (high) SYNC
(1) H input to the BSYNC L bus driver. SYNC (1) H is

enable signals is provided below.

gated with REPLY (1) H (when active) to produce a
direct preset input to the Sync flip-flop. This ensures

Bus Driver
(Signal)
BDALO-1SL

that BSYNC L will remain active until after the bus

Enable Signal(s)
(Low=Enable)

slave device terminates its BRPLY L signal and the

Reply flip-flop is reset. [REPLY (1) His low.] The Sync
flip-flop then clocks to the reset (BSYNC L passive)

{EDALL

state on the trailing edge of PH3 L.

BSYNCL
BBS7L

BREFL

BWTBT L — BWTBT L is the buffered/inverted

H
INIT (1) H, DMGCY

control chip WWB H output signal. This signal asserts

BIAKOL

during PH1 of the addressing portion of a bus cycle to

BDMGL

indicate that a write (output) operation follows. It

BRPLY L

BDIN L

remains active during the output data transfer if a

INIT(1)H

DATOB bus cycle is to be executed.

BDOUTL

BWTBT L

BINIT L

BDIN L — BDIN L is the inverted, buffered control

chip’s WDIN H signal. This signal goes active during

Always enabled

PH?2 following an active RPLY H signal.

BDOUT L — The control chip initiates the BDOUT L

signal sequence by raising WDOUT H during PH2.

The near-end bus termination resistors are contained
on the processor module. Each bus driver output is terminated by a pair of resistors, as shown in the figure,
establishing the nominal 250 Q bus impedance and the

This signal is gated with the passive REPLY (1) L
(high) signal to produce an active low D input to the

DOUT flip-flop. The flip-flop sets on the leading edge
of PH3 H, producing an active BDOUT L signal. It

3.4V nominal voltage level. No additional terminations
are required for bus-compatible devices connected to

clocks to the reset state on PH3 following the REPLY
(1) L active (low) signal.

the same backplane.

BRPLY
L — BRPLY L is a required response from a

Address and data information are distributed on the

bus slave device during input or output operations.

processor module via the WDALO-1S H and DALO-15

DIN L and DOUT (1) L are ORed to produce an active

H 16-bit buses. WDALO-15 H interface directly with
the microprocessor’s data chip, the DEC 8641 bus
drivers, and the I/O bus/memory read data multiplexer. All processor input data from the I/O bus is via
the bus receivers, the DALO-15 H bus, the data multiplexer, the WDALO-1S H bus, and the microprocessor’s data chip. Resident memory data input is dis-

I/0 L signal whenever a programmed transfer occurs.
I/0 Lenables the time-out counter in the bus error detection portion of the interrupt logic. I/O L is inverted

to produce I/O H, which enables the reply gate REPLY
H signal input to the control chip.

BRPLY L is received either from the LSI-11 bus or

resident memory and inverted to produce a high

cussed later.

input to the Reply flip-flop. PH1 H clocks the flipflop to set state, producing active REPLY (1) H and

4.2.2.4

Bus I/0 Control Signal Logic — Bus 1/0

REPLY (1) L signals. REPLY (1) L is ORed with

control signals include BSYNCL, BWTBT L, BDIN L,

DMR (1) L to produce an active BUSY H signal. The

BDOUT L, and BRPLY L. In addition, BIAKO L can

processor’s control chip responds by entering a wait

be considered a bus I/0 control signal; however, since

state, inhibiting completion of the processor-gener-

it is only used during the interrupt sequence, it is dis-

ated bus transfer for the duration of REPLY (1) L.

cussed in Paragraph 4.2.2.6. Logic circuits which

REPLY (1) H is gated with I/O H to produce an

produce and/or distribute these signals are shown in

active REPLY H signal, informing the processor that

Figure 4-5. Each signal is generated or received as

the output data has been taken or that input data is

described in the following paragraphs.

available on the bus. REPLY H goes passive when

BSYNC L — The control chip initiates the BSYNC L

terminate the BRPLY L signal, indicating that it has

signal sequence by raising WSYNC H during PH2.

completed its portion of the data transfer. On the

Inverters apply the high SYNC H signal to the Sync

next PH1 H clock pulse, the Reply flip-flop resets and

flip-flop D input. On the trailing edge of PH3 L, the

REPLY (1) H and L and BUSY H go passive.

1/O H goes passive. The bus slave device will then

4.5

SYNC (1) H

DMG CYH

REPLY (1) H—}_l

WSYNC H

L—O}

F/F

—

PH3 L —

L
SYNC (1)

SYNCR

H =

WWB H

D”

DIN L

1J>° l

DIN H

4> |

WTBTR

BWTBT L

)

INIT (1) H—O
170

BDIN L

BUS

WDIN H

INIT(1)H

SYNC

SYNC L

1AK

BSYNC L

|_°

SYNC H

DINR H

PROCESSOR

CONTROL
CHIP

LSI-11

+1/0 L
DINR L

WDOUT H

REPLY (1) L——

+ DOUT (1) L
pouT
F/F

PH3 H

DOUT mHI—q

SYNC Hj

—

BDOUT L

NIT (1) H

DOUT

(1) H
DOUTR H

REPLY H

I/0 H

_I
|

(1) H

BRPLY L FROM KD11-F
RESIDENT MEMORY

RPLYR H d

REPLY (1) |_<-—|

F/F

PHI H

BUSY H

DMR (1) L

BRPLY L

INIT (1) L~j

Ve
11- 3146

Figure4-S

BusI/O Control Signal Logic

Bank7 Decoder— The bank 7 decode circuit

all active (high). This address is decoded and BBS7 L is

is shown in Figure 4-6. Buffers receive WDALO-15 H

asserted. When active, BBS7 L enables addressing of

4.2.2.5

bits and distribute them to the bank 7 decoder and

nonmemory devices along the bus. During interrupt

BDAL bus drivers. Bank 7 is decoded during the ad-

vector bus transactions, IAK L becomes asserted. IAK

dressing portion of the bus cycle. If a peripheral device

Linhibits WDAL1S H, preventing BBS7 L signal gene-

address is referenced, an address in bank 7 (28-32K

ration, which could result in an invalid input data

address space) is used, and WDAL13, 14, and 15 H are

transfer.

PROCESSOR

DATA

CHIP

WDALO-15H BUS

VAN

BDAL

BUS

DRIVERS

@
[va]

<
13

BUFFERS

-4
[/p]

INIT (1) H

BANK 7
OCDR.

)

ILAK L—T
CP-1780

Figure4-6
4.2.2.6

Bank 7 Decoder

Interrupt Control and Reset Logic — In-

If the power failure continues, BDCOK H goes passive

terrupt control and reset logic functions are shown in

(low) and produces an active DC LO L signal, clearing

Figure 4-7. Reset functions include bus error and

the Power-Fail flip-flop and the power-fail/halt and

power-fail (BDCOK H negated). Interrupt functions

reset latches and initializing the processor and all

include power-fail (impending), Halt mode (console

devices (Paragraph 4.2.2.1). The active RESET L

microcode control), refresh interrupt, event (or line

signal then initializes the processor, causing it to abort

time clock) interrupt, and external BIRQ interrupts.

console (halt) or power-fail microcode execution and

The various functions are described in the following

enter a “‘no operation’’ state. The processor remains in

paragraphs.

this condition until BDCOK H returns to the active
state.

Power-Fail/ Restart Sequence — A power-fail sequence

is initiated when BPOK H goes low, clocking the

Power-Fail flip-flop to the set state. PFAIL (1) L is

The power-up restart condition occurs when DC LO L

ORed with HALT L to produce a high signal. This

goes false; RESET L goes passive (high) on the next

signal 1s latched during PH2 H, producing an active

PH2

IPIRQ H (interrupt 1) input to the processor control

executing a fast DIN cycle to determine the start-up

chip. The processorthen interrupts program execution.

microcode option jumper configuration. Once the fast

clock pulse.

The

processor

responds

Note that the low (passive) BPOK H signal is inverted

DIN cycle has been completed, the processor executes

to produce an active PFAIL H input to the fast DIN

the power-up option selected, and normal operation

multiplexer; this signal status is checked by the micro-

resumes when BPOK is asserted.

code to ensure that BPOK H is asserted.

Halt Mode — The Halt mode is entered either by

Upon entry to this microcode routine, the processor

| requests a fast DIN cycle. This request is decoded as

executingthe HALT instruction or by a device asserting

ROM CODE 15 L, presetting the fast DIN flip-flop.

the BHALT L signal. The processor halts program exe-

FDIN (0) H goes low, enabling the fast DIN multi-

cution and enters microcode execution as described for

plexer to place start-up microcode option jumper data,

a power-fail operation. However, when the processor

the passive time-out error [TERR (1) H] signal, and the

executes the fast DIN cycle, the PFAIL H bit (WDAL3

active PFAIL H signal on WDALO-3 H. The processor

H) is not active and console microcode (not a power-fail

receives the fast DIN information via the data chip. An

sequence) is executed. Negation of BHALT L will allow

active PFAIL H signal informs the processor that a

the processor to resume PDP-11 program execution.

power-fail condition is in progress, rather than the halt

On the next PH2 H clock pulse, IPIRQ H goes false

condition.

(low) and the processor Run mode is enabled.

4.7

ROM CODE 15 L —l

|
L

—

FDIN (1)L

FAST

DIN

F/F

START

FDIN (0) H

PH3 L —

TIMEOUT
ERROR F/F

SYNC H—?

TFCLRL (ROM CODE 12)

UP MICROCODE

/SELECT JUMPERS

ws/

)

INIT(1) L

I OO

rast

(1)

|woaL o3 :>

DIN

DATA

MU
X

PH3H —=|
REPLY (1)

H —»{

5-STAGE

TIME-OUT

TERR(1)H
ERR(1)

(2)

PFAIL H

(3)

TERR L

O—

COUNTER

RESET

LATCH

RESET

k===
=-

PH2 H —={(CLK)
+3V —»

}f’;’fi

BPOKH

%{>

BHALT L

PFAIL H

POWER

F/F

FAIL/

PFAIL (1)L

HALT
LATCH

HALT L

(CLR)

IPIRQ H

4{::>

%::>°

PFCLR L

BDCOK H

PROCESSOR
CONTROL
CHIP
——
DC LO
L

1AK
L

TAK

IAK(1) L

(

(1)
H

BHI

WIAK H

INT
ACK

=
a
|

BIACK M

DMG CY
H

F/F

IAK (1)
H

INIT (1) H

BIRQ

(CLR)

EVENT(OR LTC) W3
—
INTERRUPT

DISABLE
JUMPER

EVENT (1) H

EVNT
F/F

BEVNT L

PROC MICROCODE
REFRESH

JUMPER

DISABLE

600 Hz

REF 0OSC

10 IRQ
H

lN%éggLPT

EVIRQ H

REQUEST

LAT CH
(CLK)
PH2 H—F
= — — — — —

EFCLRL

MEMORY

REFRESH
REQUEST

T~ wa

-1:,
\)

REQ LATCH

NTERRUPT

LATCH

RFIRQ H

REF

REQ

RFOSC H

RESET L

(ROM CODE 13)

F/F

I
11-3147

Figure4-7

Interrupt Control and Reset Logic

Bus Errors — A bus error results in aborting program

(approximately). An active I/O signal inhibits the reset

execution and entry into a trap service routine via

input of the S-stage time-out counter, enabling counter

vector location 004. A bus error occurs when a device

operation. [When not in a processor-controlled bus

fails torespond to the processor’s DBIN L or BDOUT L

I/0 cycle,

signal by not returning a BRPLY L signal within 10 us

counter.] The counter proceeds with counting PH3 H

I/O L

1is

passive

(high),

clearing the

clock pulse signals. Normally BRPLY L would be
asserted, producing an active REPLY (1) H signal

TFCLR L resets the Refresh flip-flop when the refresh

which inhibits the counter; the count would remain
stable until cleared by a passive I/O L signal. However,
if BRPLY L is not received within 10 us, the full count
(32 ,0) is attained. This is the error condition; TERR L
goes low and TERR (1) H goes high. The next PH2 H
clock pulse clocks the reset latch to the reset (active)
state, producing an active RESET L signal. The processor responds by executing the reset microcode. After
entering the microcode, the processor executes a fast

if DMGCY H or INIT (1) H is asserted.

operation is completed. Note that BREF is not asserted

Event Line Interrupt — The event line interrupt
function can be used as a line time clock interrupt, or
as desired by the user. This interrupt differs from the
normal I/O interrupt request by being the highest
priority external interrupt, and it does not input a

vector in order to enter its service routine. The interrupt is initiated by the external device by asserting
BEVNT L. This signal is inverted to produce a high

DIN cycle and determines that a time-out (bus) error

(active) signal, which clocks the Event flip-flop to the

TERR (1) H, rather than a power-fail condition, has

set state. (Note that when W3 is installed, the flip-flop

occurred. It then resp: nds by executing the bus error

remains reset and the event function is disabled.) On

trap service routine. TFCLR L (ROM code 2) is

the next PH2 H clock pulse, the event interrupt request

generated by the processor to clear the TERR latch.

latch stores the active EVNT (1) H signal. An active

Normal 1/0 Interrupts — ‘“‘Normal’”’ 1/0 interrupts

EVIRQ H signal is then applied to the control chip. If

are those interrupt requests which are generated by ex-

processor status word priority is O, the interrupt will be

ternal devices using bus interrupt request BIRQ L. The

serviced. Service is gained via vector 1004, which is

request is initiated by asserting BIRQ L. This signal is

dedicated to the event interrupt. Hence, a bus DIN

inverted to produce a high signal, which is stored in the

operation does not occur when obtaining the vector.

interrupt request latch on the next PH2 H pulse. The

The request is cleared by the microcode generated

stored request produces IOIRQ H, which informs the

EFCLR L signal.

processor of the request. If processor status word

4.2.2.7

priority is 0, the processor responds by producing an

Special Control Functions — Special control

functions include microcode-generated bus initialize

active WIAK H (interrupt acknowledge) and WDIN H

and memory refresh operations and five special control

signals. WDIN H is buffered onto the BDIN L signal

signals which are internally on the processor module.

line to signal devices to stabilize their priority arbitra-

Special control function logic circuits are shown in

tion. WIAK H is inverted, producing IAK L, setting

Figure 4-8. Microinstruction bus lines WMIB18-21 L

the Interrupt Acknowledge flip-flop on the trailing

are buffered to produce the four SROMO-3 H signals.

edge of PH1 L one cycle after BDIN L is asserted. The

The

high (active) interrupt acknowledge signal is enabled

actual

codes

for

the

special

functions

are

contained on SROMO-2 H; SROM3 H is always active

onto the BIAKO L signal line by passive (low) DMGCY

when a special function is to be decoded, enabling the 1

H and INIT (1) H signals. The highest priority device

of 8 decoder during PH3 H. The resulting decoded

requesting interrupt service responds to the processor’s

functions are described below.

BDIN L and BIAK L signals by placing its vector on the
BDAL bus and asserting BRPLY L, inputting its vector

ROM Code 10 — Not used.

to the processor. Note that BSYNC L is not asserted

ROM Code 11 [IFCLR and SRUN L] — This code is

during this operation and that no device addressing

produced by the processor to

occurs. The device also clears its BIRQ L signal. The

clear

the

Initialize

flip-flop and to assert the SRUN L signal for a RUN

processor responds to BRPLY L by terminating BDIN

Land BIAK L.

indicator in PDP-11/03 systems.

Refresh — Memory refresh is initiated by a 600 Hz re-

fresh oscillator. This function is enabled when jumper

ROM Code 12 [TFCLR L] — This code is a trap
function clear signal which clears the Refresh Request

W4 is not installed. The leading edge of RFOSC H

and Time-Out Error flip-flops (Paragraph 4.2.2.6).

clocks the Refresh Request flip-flop to the set state. On

ROM Code 13 [RFSET L] — This code is used to set

the next PH2 H clock pulse, the memory refresh

the Retresh flip-flop. The active (high) flip-flop output

request latch stores the request and applies an active

is gated with passive (low) INIT (1) H and DMG (1) H

RFIRQ H signal to the processor’s control chip. The

signals to produce the active BREF L signal. The

processor responds by producing an active RF SET L

flip-flop normally resets by the microcode-generated

signal and executing the refresh microcode. RF SET L

TFCLR Lsignal after completing the refresh operation,

sets the Refresh flip-flop, producing the BREF L

or whenever a power failure occurs. (DC LO L goes

signal (Paragraph 4.2.2.7) and clearing the Refresh
Request

flip-flop,

which

terminates

the

active and clears the flip-flop.)

request.

4.9

ROM CODE 11 L

(IF CLR AND SRUN L)

- INIT (1) L
ROM CODE =4

| LINIT
oy

INIT

(1) H

(INITIALIZE

BINIT L

SET)

SROMO

1\g.h_fi2I1BL

DCLO

SROMT H

BUFFERS | SROM2 H

(NOT USED)

—»ROM

1:8 ROM

CODE

ROM CODE 11 (IFCLR & SRUN L)

—

SROM3 H

CODE

(TFCLR

- ROM CODE 13 (RFSET L)

CODE

—» ROM CODE 14 L (INITIALIZE SET)

DECODER

—

PH3 H

—» ROM

ROM CODE 15

L (FAST DIN)

CODE

(PFCLR

—» ROM CODE

(EFCLR L)

T
o

-+ ROM

‘

RFSET L

1 INIT (1)H —Ol
=

REF

) BREF L

DMG
CY H—O

TFCLR L F/F

DCLO L J

REFR L

11-3148

Figure4-8

Special Control Functions

ROM Code 14 [Programmed Initialize] — A pro-

The fast DIN cycle allows the processor to read (input)

grammed LSI-11 bus initialize operation can be per-

the selected start-up mode, time-out error, and power

formed by executing the RESET instruction.

fail signal status (Paragraph 4.2.2.6).

The

processor responds by generating ROM Code 14 L

(decoded). On the positive-going trailing edge of this
signal, the Initialize flip-flop clocks to the reset (active)
state, producing the active initialize signal. Approxi-

ROM Code 16 [PFCLR L] — This code clears the
Power Fail flip-flop (Paragraph 4.2.2.7).

mately 10ys later, the processor produces a TFCLR L
signal, clearing the initialize signal.

During a power failure, the active DC LO L signal is

ROM Code 17 [EFCLR L] — This code clears the
Event flip-flop (or line time clock interrupt request)

(Paragraph 4.2.2.7).

distributed to the Initialize flip-flop clear input; when
cleared, the flip-flop is in the active state and INIT (1)
H, INIT (1) L, and BINIT L initialize signals are used

to clear (or initialize) all LSI-11 system logic functions.
When normal power resumes, the processor microcode

terminates the initialize cycle by generating TFCLR L,
presetting the Initialize flip-flop; this is the passive

(noninitialize) or normal flip-flop state and all ini-

tialize signals return to their passive states.

4.2.2.8

Bus Arbitration Logic — Bus arbitration

logic (Figure 4-9) enables the LSI-11 bus to be used by
DMA

devices

the

processor.

The

device

(or

processor) controlling the bus is called the bus master.
When no DMA requests are pending, the processor is

bus master and all data transfers are programmed.
When

DMA

device

bus

master,

processor

ROM Code 15 [Fast DIN Cycle] — The processor

operation is suspended until the DMA operation is

generates this code when a fast DIN cycle is required.

finished.

SACK L

BSACK L

OMG(1) L }TO EDAL L LOGIC

F/F

PH4 H —

BDMR L‘4>— OMA
PH{ H —

PH4 H—

DMA REQ H

REQ
F/F

DMG (1) H

INIT(1) H —o-j)_’

BDMGO L

—

SYNC L

DMA REQ L
BUSY H

REPLY (1) L
INIT(1)L

11-3149

Figure4-9

Bus Arbitration Logic

Prior to a DMA request, the DMA Request flip-flop is
reset (Figure 4-10); the DMA REQ H signal is passive
(low), clearing the DMG Enable flip-flop. A device
initiates a DMA request by asserting BDMR L. The
request is inverted to produce a high signal, which is
clocked into the DMA Request flip-flop on the next
PH1 H clock pulse, producing active DMA REQ H and
L signals. DMA REQ L is ORed with REPLY (1) L,

On the first PH4 H clock pulse following the passive
state of SYNC L, the DMG flip-flop clocks to the set

“wait” after completing its present bus cycle. On the
leading edge of PH4 H, the stored DMA request sets
the DMG Enable flip-flop. The processor is finished
with its present bus cycle and releases the bus when
SYNC L goes passive (high).

tion and keeping the DM
A Request flip-flop in the set

producing BUSY H and causing the processor to

state and DMG (1) H and DMG (1) L go to their active
states. DMG (1) H produces the active BDMG grant
(BDMGO L) signal. DMG (1) L enables EDAL L
signal generation when the DMA operation involves
KD11-F resident memory. The DMA device responds

to the BDMG signal by negating BDMR L and
asserting BSACK L, enabling EDAL L signal genera-

state. On the first PH4 H clock phase following the
active state of BSACK L, the DMG Enable flip-flop
clocks to the reset state and DMG EN H goes low. The
following PH4 H clock pulse clocks the DMG flip-flop

BOMR L |
PH1—»|

PH1—
DMA

REQ FF

BSACK

SYNC

wBUSY H

T
I

BOMG L \H;

DMG

F—

DMGEN FF

~ {00 ns + BUS

PROP. DLY.

DMA DATA
TRANSACTION

|<——INHIBIT PROCESSOR BUS CYCLES

L
1-3150

Figure4-10

DMA Grant Sequence

HSL-@va W3Wav3yViVQ@AW)(HSI-

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row address (bits A7—A12 H) through the 12:6-bit
address multiplexer and into all memory chips. After

to the reset state and BDMGO L goes passive (high),
terminating

the

DMA

request/grant

sequence.

BSACK L remains asserted for the duration of the

150 ns, address multiplex control logic generates an

DMA operation, preventing new DMA requests from

active column address strobe (CAS) and a low AMX

being arbitrated.

signal. The multiplexer output bits (A1-A6) are then
strobed into all memory chips, completing the addressing portion of the memory operation.

The DMA device releases the bus by terminating
BSACK L. The following PH1 H clock pulse clocks the
DMA request flip-flop to the passive state. BUSY H

When in a memory read operation, each of the 16

then goes passive, enabling a processor-initiated bus

memory chips places an addressed bit on the memory

cycle. Once the processor-initiated cycle is entered,

read data bus. This data is multiplexed via port A of

SY (' 1. inhibits ‘clears) the DMG flip-flop for the

the I/0 bus/memory read data selector only when in a

dui 2tios - wne pro-essor’s present bus cycle.
4.2.3

resident memory read (or refresh) operation; the select
input of the data selector is asserted low for this data

KDI11-F Resident Memory

selection. The read data is then placed on WDALO-15

The 4K by 16-bit dynamic MOS read/write memory is
included on

the

KD11-F

processor module

H, where it can be read by the microprocessor data chip

only.

or gated onto the BDAL bus via bus drivers for input to

(KDII-J basic memory is magnetic core, which is con-

a DMA device.

tained on a separate MMV11-A core memory unit.)
Resident memory can reside in either the first or
second 4K address bank. One of two jumpers can be

When in a memory write operation, the addressing

installed on the module to select the desired bank

portion of the operation is similar to the read cycle ad-

(bank O or 1).

dressing, except BWTBT L may be asserted by the
master device to indicate that a write operation is to

The basic functions involving the resident memory are

follow. After the addressing portion of the cycle has

shown in Figure 4-11. Resident memory comprises sixteen 4K by 1-bit memory chips,

addressing,

been completed, BWTBT L either goes passive (high) if

and

a DATO (word) write cycle is to be performed, or

control logic. The memory chips, which are 16-pin

remains asserted (BWTBT L remains low) if a DATOB

devices, require an address multiplexer to address the

(byte) write cycle is to be performed. Word1byte select

chips with two 6-bit bytes. The complete addressing,

logic responds to the DATO cycle by asserting both

write, and read operations are described below.

BYTE1WTLand BYTEO WT L for the duration of

the cycle, enabling DALO-15 H data bits into the

Addressing is initiated by a master device — either the

addressed location in all memory chips.

LSI-11 processor or a DMA device — by placing the

However,

when in a DATOB cycle, only one active signal is

16-bit address on BDALO-15 L and asserting BSYNC

produced, depending upon the state of the stored byte

L, latching the address in the 16-bit address register.

pointer (address bit AO). If AQ is low (even byte), only

Note that the resident memory address will appear on

BYTE O WT L goes active, enabling only DALO-7 H

the BDAL bus even when the processor is bus master;

bits to be written into the addressed location in the ap-

the resident memory functions exactly as a memory

propriate eight memory chips. Similarly, if A1 is high

located elsewhere along the LSI-11 bus. Address bits

(odd byte), only BYTE 1 WT L goes active, enabling

are routed via BDAL bus receivers onto the processor

only DALS8-15 H bits to be written into the addressed

module’s DALO-15 H bus to the address register input.

location in the appropriate eight memory chips.

Stored address bits A13—A15 H are then decoded by

the bank select decoder. SBSO L (bank 0) and SBS1 L

(bank 1) will go active (low) only when their respective

Resident memory, as well as any LSI-11 bus device,

bank addresses are decoded. W1 or W2 then applies

must respond to any data transaction by generating an

the selected address to the address multiplex control

active BRPLY L signal.

logic, enabling the resident memory response. Address

function. Approximately 150 ns after CAS L goes true

Reply gates provide this

multiplex logic immediately generates an active row

(as previously described), the reply gates are enabled;

address strobe (RAS), which remains active for the

the gates will respond to either an active BDIN L or

duration of the BSYNC L signal. Address multiplex

BDOUT L signal by asserting BRPLY L. Reply gates

control (AMX) is initially high, multiplexing the stored

are inhibited during an initialize operation.

4-13

Resident memory requires a refresh operation once

switches contained on the option. The MMV11-A is

every 1.6 ms. This operation is entirely under the

completely LSI-11

control of either processor microcode or an external

either programmed I/0 data transfers with the proc-

DMA device, as selected by the user. Resident memory

essor or transfers with another LSI-11

responds to BREF L,

device.

generated by the

refresh-

controlling device, by simulating a ‘““bank selected”
operation.

64 successive BSYNC L/BDIN L operations while in-

crementing BDAL1-6 L by one location on each bus
Refresh

simply a series

4096 by 16-bit capacity

Typical access time = 425 ns (475 ns maximum);

of forced

full

read/restore

cycle

time

1.15us.

memory read operations where only the row addresses
*

are significant. Each of the 64 rows in all dynamic

Nonvolatile

read/write

storage

—

stored

data remains valid when power is removed.

MOS memory chips in an LSI-11 system are simultaneously refreshed in this manner.
4.2.4

DMA bus

The MMV11-A features:

(All memory banks are simultaneously

refreshed.) Refresh is then accomplished by executing

transaction.

bus-compatible and capable of

User-selected bank address — three switches

allow the user to select the bank address for

DC-DC Power Inverter

the option.

The dc-to-dc power inverter circuit provides on-board
®

generation of required negative dc voltages. Input dc

+S5Vand +12V power — only the normal

backplane power is required to power the

power for the inverter circuit is obtained directly from

option.

the +12 V input. The inverter switching rate is clocked
by the clock pulse generator’s DIVB (0) H 2.8 MHz

output. Output negative dc voltages are distributed to

Noadjustments, no periodic maintenance.

The MMV11-A is contained on two modules which are

all resident memory chips. The -5 V output is distributed to microprocessor chips (data chip, microm

mated to comprise a single assembly as shown in Figure

chips, and control chip).

4-12. The modules include memory interface

timing board

(module type G653 and core

and

stack

(module type H223). The actual size of the assembly is

4.3

MMVI11-A 4K BY 16-BIT CORE MEMORY

8.5by 10by 0.9 in. The G653 module includes handles
and retractors on the top edge and fingers on the

4.3.1

General

bottom edge which plug into the LSI-11 bus. Circuits

The MMV 11-A 4K by 16-bit core memory option provides nonvolatile read/write storage of user programs
and data. Memory 4K addressing is user-selected by

contained on this module include interface, control
and timing logic, bus receivers and drivers, the 16-bit

data paths, sense amplifiers, and a +5 Vdc to -5 Vdc

—_

G653

MEMORY INTERFACE
AND TIMING
H 223

CORE STACK

CP-178l

Figure4-12

MMYV11-A Core Memory Option

4-14

inverter. The H223 module is slightly smaller, includes

LA1—6H

no handles or bus fingers, and plugs onto the No. 2

LA7—12H are applied to X drive circuits.

are

applied

drive

circuits

and

(solder) side of the G653 module via special connector
pins. Spacersare located between the modules to stiffen

X and Y Drives—
X and Y drive circuits control X and

the assembly and to maintain the 0.9 in. dimension.

Y read/write currents through all core mats. Address

Circuits contained on the H223 module include the

decoding activates 1 out of 64 X wires and 1 out of 64 Y

4096 by 16 core stack, 12-bit address register, X and Y

wires. Because the active X and Y wires each have

drives, stack charge, temperature compensation, and a

one-half the current required for core saturation, only

series +11 V, Vcc switch which removes drive power

one core out 0of 4096 cores in each core mat is saturated.

when BDCOK H goes low (power fail) or BINIT L is

Direction of current is determined by a read or write

asserted.

operation.

4.3.2

4.3.2.1

Functional Description

Introduction — The

read/write,

random

access,

Core Stack — The core stack comprises sixteen 4096-

MMV 11-A memory is a
coincident

current

magnetic core type with a cycle time of 1.15us and an
access time of 425 ns. It is organized in a 3D, 3-wire
planar configuration. Word length is 16 bits and the
memory consists of 4096 (4K) words.

Major functions contained in the MMV 11-A are shown
in Figure 4-13. Memory data can be stored (written) or
read by executing appropriate bus cycles: DATO
(16-bit word) write; DATOB (8-bit byte) write; DATI

(16-bit word) read;DATIO (16-bit word) read-modifywrite; and DATIOB (16-bit word) read-modify-(8-bit
byte) write.

core mats. Each mat is associated with one memory bit

position at all 4096 locations. Each core has three wires

passing through it: one X, one Y, and one sense/inhibit
wire. The sense/inhibit wire passes through all 4096

cores in one mat. Hence, the stack contains 16 sense/
inhibit lines.

The

ends

terminate

sense

center of the sense/inhibit line when a logical O is to be
written in the addressed core. This current splits and
one-half saturation current flows through all cores in

the mat and into termination diodes at the sense amplifier inputs. The wire is threaded through the cores in a

manner that causes the current to flow in a direction

opposite to that of the Y write current; this prevents

described below:

core saturation, which would write a logical 1 in the
addressed core.

Bus Receivers and Drivers — These devices interface

directly with the LSI-11 bus and the G633 logic

Sense Amplifiers —

circuits. BDAL bus drivers are gated on by DATA

Sense

amplifiers

respond

induced voltage impulses during the read cycle. They

OUT L during a read operation [DATI or the input

are

portion of a DATIO(B) bus cycle].

strobed

during

a critical

time

of the

cycle,

producing an active (high) output when a logical 1 is
read, regardless of the induced polarity on the two ends

Bank Decoder — The bank decoder receives address

of the sense/inhibit wires for each bit.

bits A13-15 L and responds when the bank address is as

user-selected on the three bank address switches on the

line

current, equal to saturation current, is applied to the

Each of the functions shown in Figure 4-13 is briefly

G653 module. It responds by producing an active

sense/inhibit

amplifier inputs. During a write operation, an inhibit

Inverters — The inverters receive sense amplifier out-

puts, invert them, and direct-set previously cleared

DSEL H signal which initiates memory cycle timing.

memory data register bits when a logical 1 is sensed.

This signal is enabled only when power is normal and

bus initialize or refresh operations are not in progress.

Memory Data Register — The 16-bit memory data

Timing and Control — Timing and control circuits re-

ceive bus and internal control signals and generate ap-

logical 1s set appropriate bits. During a restore cycle

propriate read/write timing and control signals. It also

(DATI bus cycle) (no memory contents are to be modi-

generates the BRPLY L signal in response to BDIN L

fied), the same bits (low-active) are written into the

and BDOUT L.

same addressed location. During a write cycle [DATO,

Address Register — The address register stores the

cycle], bus data bits are clocked into the high and/or

12-bit word address within the 4K bank during the

low byte(s), depending upon the type of bus cycle (word

addressing portion of the bus cycle. Latched bits

or high byte or low byte).

DATOB, or the write portion of a DATIO(B) bus

4-15

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Inhibit Drivers — Inhibit drivers, one for each bit posi-

and passive VCC20K H signals. These signal condi-

tion, produce an inhibit current during the write cycle

tions prevent memorycircuit operation and the possible

at INH TIME H if a logical O is to be written. The

loss of stored data.

current inhibits core saturation, which would produce
a stored logical.

Vee Switch — The Ve switch applies +11.5 V to X
and Y driver circuits when not in an initialize or power

Charge Circuit — The charge circuit applies the

fail condition.

correct operating voltage to X and Y drive circuits
during the read and write memory cycles to prevent

“sneak’ currents through unselected stack diodes.

4.3.2.2 Core Addressing— When a memory location
is addressed, one coreineach ofthe 16 mats are accessed

X—Y Temperature Compensation — X—Y tempera-

for a read or write operation. Figure 4-14 illustrates a

ture compensation circuits alter drive currents over the

portion of the X—Y drive and associated circuits for

required operating temperature

one Y wire. Six address bits (A1—A6) select 1 of 64 Y

range

provide

reliable operation.

wires. A similar circuit (not shown) involving the re-

DC—DC Inverter — The dc—dc inverter circuit

wires. Hence, by placing 64 cores (in each mat) on each

generates -5 V power for sense amplifiers from the +35

Y wire and passing a different X wire through each

V power.

core, one of 64 cores on the active Y wire will be

maining six address bits (A7—A12) selects 1 of 64 X

selected. Since the remaining Y wires have a similar 64
cores each and receive the same X wires, 64 x 64, or 1

DC Protection — DC protection circuits respond to an

active BINIT L or passive BDCOK H signal by pro-

out of 4096 addressing is accomplished in each of the

ducing active LOCKOUT L, RESET H, RESET L,

core mats. A single Y wire is driven as described below.

—

——

PART OF Y DRIVE CKT.

——

———

READ EARLY L —¢

I rPART OF TEMP.

—

———

o1
T

+12V
3

——

COMP CKT.

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R
i

WRITE
SOURCE

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—_—— e =

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_——_——

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TYPICAL CORES

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0

1
2

SINK

WRITE LATE L

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—

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=

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TYPICALY WIRE

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—>—

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CHARGE
WRITE

.
CP-1783

Figure4-14

MMV11-A Core Addressing

4-17

Two 1:8 (octal) decoders are used in Y wire selection,
each receiving three address bits from the address

active during addressing. Assuming address XX00 (the
zeros are the Y portion of the 12-bit address), the
portion of the Y drive circuit shown will be enabled.

During a read operation, READ EARLY L goes active
and turns on one of the eight read current source
transistors. A diode in its emitter circuit couples the

drive to eight Y wires, each terminating at the diode

return path for the selected X and Y wires; only those
two wires will go to approximately 0 V, causing one X

and one Y diode to become forward biased, enabling

the write half-currents to flow. Resistors coupling the
charge voltage to write sink transistors limit the charge
current through the addressed write sink transistors

during the remainder of the write cycle. This circuit
performs

the same function for read cycles by
grounding the buses and preventing sneak currents

through unselected stack diodes.

steering matrix. The diodes provide a read current
path to all eight read sink transistors. READ LATE L

4.3.2.3

goes active 25 ns after the Y source is turned on, and

write data path is shown in Figure 4-13. Upon entering

turns on

a read cycle, the memory data register is cleared by
CLROL and CLR1 L. X and Y read currents produce

one

of the

eight

read

sink

transistors,

completing a read current path to ground. Hence, 1 of

Read/Write Data Path — The basic read/

64 Y wires is selected, producing a read half-current

active

through 64 cores in all memory mats. Similar X drive

containing stored logical 1s as they are switched to the 0

sense

amplifier

outputs

for

those

cores

circuits will produce an X read half-current in 64 cores

states. These signals are inverted and applied to the

in each mat in exactly the same manner. Only one core

direct-set inputs

in each mat will receive an X and a Y read half-current,

memory data registers, setting the appropriate bits.

of the flip-flops comprising the

causing the core to saturate in the O state. If the core

During a write cycle, CLRO L (DATOB low byte ad-

was previously in the 1 state, a voltage pulse will be

dress), or CLR1 L (DATOB high byte address), or both

induced in the sense/inhibit wire as it switches to the 0

CLRO L and CLR1 L (DATO word address) clear the

state.

previously read data. The bus data is then received and

clocked into the register flip-flops by CLK MDROH
A write cycle is always preceded by a read cycle. The

and/or CLK MDR1 H, as appropriate. Write data bits

write operation is similar to the read operation, except

are then routed to inhibit drivers which inhibit writing

write current flows through the addressed wire in a

Is when write bits are Os (high). Inhibit half-current

direction opposite to the read current direction. The

through addressed cores prevents X-Y write half-

core in each mat receiving X and Y write half-currents

currents from switching cores to the 1 state.

will respond by saturating in the 1 state. However,

since a 0 may be desired, a third wire (sense/inhibit)

The sense/inhibit wire passes through all cores in a

will

the

core mat, as shown in Figure 4-15. The circuit shown in

magnetizing effect of the Y write currents. Thus, core

the figure is repeated for each of the 16 core mats.

saturation is not attained and the cores where Os are

During the read portion of a memory cycle, a logical 1

conduct

half-current

which

opposes

written remain saturated in the O state from the pre-

stored in the addressed core will cause an induced

vious read cycle.

voltage to appear on the sense/inhibit wire as the core
switches from the 1 saturation state to the O saturation

Temperature compensation is applied to driver circuits

state. If a 0 was previously written, no appreciable volt-

via a source current, which is inversely proportional to

age is produced since the core is already saturated in

temperature; an increase in temperature decreases

the

available drive current.

sense/inhibit wire functions as a loop whose ends

state.

During

the

read

operation,

the

terminate at the sense amplifier inputs. Any difference

The stack charge circuit applies a +11 V (approxi-

in potential (either polarity) will enable a sense ampli-

mately) signal to the sink ends of all X (not shown) and

fier output. STROBE H occurs during X and Y drive

Y wires during the write cycle. The level is applied

read currents at a critical time (the time of peak core

during WRITE EARLY time. Since WRITE LATE L

switching output when 1s are read). Thus, only the cor-

occurs 25 ns after WRITE EARLY L, the write sink

rect voltage pulse produced when a core goes from the 1

transistor is cut off, and the full 11 V signal charges the

state to the O state is gated into the Memory Data Re-

stray capacitance of the X-Y lines, reducing the capa-

gister flip-flop.

citive delay effect as the X and Y write source

transistors turn on; the 11 V signal also reverse biases

The threshold circuit establishes the signal voltage

diodes not selected by addressing circuits, preventing

level at which a logical 1 is read during strobe time. A

sneak currents. The addressed sink transistor, turned

signal voltage magnitude greater than approximately

on by the active WRITE LATE L signal, provides the

17 mV during strobe time results in a valid 1 level.

+5V

THRESHOLD
VOLTAGE

| TINH L

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| FOR EACH 4 BITS |

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CENTER TAPPED SENSE /INHIBIT WIRE PASSES
THROUGH ALL 4096 CORES IN THE MAT.

L
aB

[

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: STROBE H
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'
:

WRITE BIT (H=0)

L=
|

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BUS RECEIVER
MDRCLKO H

MDRCLK1 H)

0 P Q

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BUS

DRIVER

DATOUT L —O
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READ DATA BIT
TO BDAL BUS

o
MEMORY DATA REGISTER
FLIP-FLOP

CLRO L

(OR CLR1 L)
CP-1784

Figure4-15

MMV11-A Read/Write Bit Data Path

Signal levels less than the 17 mV threshold value are

circuit provides a threshold voltage for four data bits.

considered invalid and result in O levels being read.
source

When in the write portion of the memory cycle, the

resistor. Each threshold circuit provides a reference

inhibit driver remains off if a 1 write data bit is stored in
the memory data register flip-flop. However, if a 0 is to
be written, the write bit is high, enabling a gate input

Four

threshold

circuits

common

amplifier input voltage to two sense amplifier ICs, each
containing two sense amplifiers; hence, one threshold

for the inhibit driver. At INH TIME H during the write

by the RC circuit connected to

cycle, the inhibit driver produces an inhibit current

leading edge of FBUSY L, the state of FBUSY H is

FBUSY L. Thus, on the

equal to core saturation in a direction that would

clocked into the Read flip-flop, causing it to go to the

produce alogical 0. However, note that the inhibit cur-

set state. This sequence is shown in Figures 4-17 and

rent is applied to the center of the sense/inhibit wire.

4-18.

Thus, half-currents flow into each half of the sense/

inhibit wire,

preventing the

addressed

core

from

saturation in the 1 state. Diodes at the sense amplifier
ends of the wire provide a ground return for the two

inhibit half-currents. The two resistors terminate the

ends of the wires. The inhibit driver transistor collector
is clamped to ground through a diode and resistor to
prevent

breakdown

during

turnoff.

The

emitter

resistor limits peak current.

4.3.2.4

Timing and Control — All memory bus cycles

transaction,

Figure 4-17.

memory

read-restore

cycle

executed. The data is first read and placed on the I/0
bus. The same data is then written in the same
addressed location. Duringa DATO bus transaction, a
memory read-modify-write cycle is executed. After
reading the contents of the addressed location, bus
data is clocked into the memory data register. Preinto

the

addressed

that RT22S His inverted and applied to the clear input
of the Read flip-flop, establishing the 225 ns pulse
width for RT pulses. RT22S H goes low, 225 ns later.
This time occurs 400 ns (total) after BSYNC L is

asserted and it is referenced on Figure 4-16 as (TSOO L).
The pulse produced by the RC network on the leading

edge of FBUSY L is inverted to produce the CLRO L
and CLR1 L signals, which clear the memory data
register for the new read data. READ EARLY occurs

location

during

on the leading edge of FREAD H and remains active
for the duration of RTS0 H, producing a 300 ns pulse.

the

RT25 H goes high 2S ns later, producing the READ
LATE L signal; this signal remains true for the

duration of RT100, resulting in a 325 ns pulse. Read

read word is retained for the write operation. A DATIO

data is valid at the sense amplifier inputs from 200 to

bus transaction actually initiates two separate memory

275 ns after READ EARLY L goes active. RT175 H is

cycles. The first cycle (read-restore) is initiated by the

gated with RTS50 H to produce the sense amplifier
strobes STROBE O and 1 H. The trailing edge of RTS0
H occurs 100 ns after the leading edge of RT175 H,

master device by placing the memory address on
BDALO—15L and asserting BSYNC L. After receiving

and modifying the memory read data, the master

negating the strobes. During strobe time, the sense
amplifier data bits set the appropriate flip-flops that
comprise the memory data register, and store the

device outputs the new data to the memory and asserts
BDOUT L, which initiates the next memory cycle

Timing

and

control

logic

memory read data.

functions generate all of the timing and control signals
memory

cycles

FREAD H. Hence, the

225 ns after the leading edge of FREAD H, and ap-

data register is modified, and one byte of the previously

the

time

leading edge of RT22S H, shown in Figure 4-16, occurs

being executed, only an 8-bit portion of the memory

for

read

Each signal is a 225 positive-going pulse whose leading

remainder of the cycle. If a DATOB bus transaction is

(read-modify-write).

activates the

edge is delayed with respect to

viously read data is lost. The modified word is then
written

FREAD H

generator, producing time signals prefixed with “‘RT.”

proximately 275 ns after BSYNC L is asserted. Note

comprise a read and a write operation. During a DATI
bus

The read-restore (DIN) cycle continues as shown in

described

above.

Logic

operation for each type of bus transaction is described

The bus master device initiates the data transfer

in detail in the following paragraphs.

portion of the DATI transaction by asserting BDIN L.

A memory cycle is initiated when the correct bank

The Replay Enable flip-flop is set on the trailing edge
of RT100 H 375 ns after BSYNC L. If RDIN H (BDIN

L inverted) is received earlier than 375 ns after BSYNC
L, the Reply flip-flop input gates wait 375 ns to
produce an active RPLY SET L signal (Figure 4-17),

address asserted by the bus master device is decoded on
the leading edge of BSYNC L. DSEL H is the decoded
bank address signal; note that it is inhibited during

which direct-sets the Reply flip-flop and produces the
active FRPLY H and BRPLY L signals. FRPLY L is

refresh bus cycles (when BREF L is asserted), or when
an initialize or power fail condition exists. The logical

gated with RDIN L and inverted, producing the DATA
OUT L signal which gates memory data register bits
onto the BDAL bus. If RDIN H is received later than

state of DSEL H is clocked in the Busy flip-flop on the
leading edge of SYNC H (Figure 4-16). When DSEL H

is active (high), the Busy flip-flop sets and FBUSY H

and

FBUSY L goto their true states.

375 ns after BSYNC L, the Reply flip-flop sets on the
leading edge of RDIN H. The trailing edge of RT150 H
(T425L) is gated with RPLY SET L, producing a write

FBUSY L enables

one input of the read initiate gate. The remaining gate
input is enabled by the negative-going pulse produced
4-20

> RT25 H

»RT50 H
RT75 H

DSEL
SYNC

H—

FBUSY H

FREAD H

BUSY
F/F

(T500 L

READ

INIT

+5v

e
+

o<t

RDOUT H —

RT50 H :DO—'READ EARLY L

RT100 H

YO
» READ LATE L

CLR H

CLR1 L

1
RWBT H—

DATIO

WRITE

SYNC H —

F/F

RT175 H

GENERATOR| ___ RT225 H

F/F

> FBUSY

RESET H—>o—}>

|READ TIME

READ

FWBT L

RT200 H

STROBE O H

LATE L

STROBE 1 H

RT175 H

RT150 H

EARLY L
REPLY ENABLE
F/F

RT100 H

RTIS0 H

RDOUT H

Y SET L o (WRITE ENABLE)
FRPLY

FBUSY L—
WCLR

reLy

RDIN

CLR

F/F

RDOUT HiD—DjflD—
TINH

—{>o—sBRPLY L

| RPLY

»FRPLY L

RESET L WDATA ouT L
RDIN H ¥

WRITE TIME | WT250 H

FBUSY H —

SENERATOS

RDIN L

>o—+ weLr L

WRITE

F/F

RPLY

TINH H

SET L:D

RT150

WTOO H

WT175 H ‘iD&

WCLR
L

RDOUT H & WRITE
RAD H

FAO H _Do—

BYTE

F/F

RWBT H—o>-

TIME L

wreas

> WLATE L

WEARLY L

STK CHG H

:D—>CLK MDR 1 H

SEL

SYNC H—

TINH

oL M—’ CLK MDR O H

WRITE

WORD H
cP-1785

Figure4-16

MMV11-A Timing and Control Circuits

4-21

SEC

T500

500

T1000

ADDR

BDAL

MIN.)

75nsec.

BSYNC L

FBUSY

(MIN.)

FBUSY H

FREAD H
FREAD

READ EARLY

L
le— RTSOH GOES LOW

READ

r—zsns ec.
READ

LATE

CLRO
CLR!

L
L

EARLY L

READ LATE

CLRO L
CLR1 L

= RT175 H GOES HIGH

STRDBE
O H
STRDBE1 H

,‘—- RT50 H GOES LOW
STROBEO H
STROBE1 H

READ DATA VALID

\
\

MEMORY DATA REGISTER-—
WRITE DATA VALID
MEMORY DATA REGISTER-

BDIN

BRPLY

BDOUT

le— 25 nsec (MIN)

I-— 150 nsec (MIN)

BRPLY

1—_ :JK;EE]% i

DATA

}4—(25nsec.

BSYNC

1000

INPUT

BDAL

CLKMDR1 H
CLKMDRO H

DATA OUT L

FWRITE

TINH

CLKMDR! H

WEARLY L

WLATE L

STKCHG H

WCLR L

TINH H

- sl

CLKMDRO H

WEARLY L

WLATE

STKCHG H

WCLR

L— READ —»te—— WRITE —
MODIFY —#

L— READ -oL— RESTORE —-l

CpP-1787

CcpP-1786

Figure4-18
Figure4-17

Read-Modify-Write Memory Cycle
Timing

Read-Restore Memory Cycle Timing

4-22

initiate pulse which clocks the high FBUSY H signal

high, and the two byte select OR gates apply low signals

into the Write flip-flop, initiating the restore portion of

to the remaining CLK MDR gates. CLK MDR 0 and 1

the memory cycle.

H then clock the BDAL bus data into the memory data
register; the previously read data is lost. The write

Restore timing is produced by the write time generator

portion of the cycle continues as described for the

in a manner similar to that described for read time

restore portion of the DATI operation.

generation. At WT00 H time, TINH H and TINH L
When executinga DATOB bus transaction, BWTBT L

(47S ns pulses) are produced for the inhibit drivers.
TINH H also inhibits the Reply Clear gate, and the

and RWBT H remain active for the duration of the bus

Reply flip-flop remains set for the remainder of the

cycle. Hence, the WRITE WORD H signal remains

memory cycle. WEARLY L and STK CHG H go active

passive. The Byte Select flip-flop that stores byte

on the leading edge of WT175 H and remain active for

address bit RAQO H during addressing time enables

350 ns. Similarly, WLATE L goes active on the leading

generation of only one CLK MDR H signal. When RAO

edge of WT175 H and remains active for 325 ns. At

H is low, FAO L goes high and CLK MDR 0 H clocks

WT250 H time, WCLR L is produced, clearing the

low byte data bits from only BDALO—7 L into the

Reply Enable and Write flip-flops; thus, write time

memory data register. Register bits 8—1S5 remain un-

generator outputs are 250 ns pulses. Memory data is

changed. Similarly, when RAOQ H is high,

restored (written)

high and CLK MDR 1 H clocks high byte data bits

during the time that TINH H,

only

BDAL8—1S

into the

FAO H goes

WEARLY L, and WLATE L are active. The memory

from

cycle terminates when both SYNC L and FRPLY L go

memory

data

to their passive states. The Busy Clear gate detects this

The write portion of the memory cycle then continues

condition, producing a low pulse which clears the Busy

as previously described.

flip-flop, and the memory cycle ends.
When executing a DATIO bus cycle, two complete
The DATO cycle is similar to the DATI cycle except

memory cycles are executed. They include a DATI and

that during the addressing portion of the bus cycle, the

a DATO or DATOB cycle as previously described.

bus master device asserts BWTBT L. RWBT H goes

However, when executing a DATIO bus transaction,

high, and the leading edge of SYNC H clocks the byte

BSYNC L remains active for the duration of the trans-

FWBT L signal is

action. Hence, SYNC H, which generates FBUSY L

only used when in the write portion of the DATIO

during the read-restore portion of the cycle, cannot

cycle, as described later. However, duringa DATO bus

initiate the second read-modify-write memory cycle.

transaction, RDIN H is not received; instead, RDOUT

Instead,

H is received, enabling the REPLY SET L gates, as

portion of the cycle, enables a read initiate pulse on the

flip-flop to the set state. The active

FWBT

stored

during the

addressing

shown in Figure 4-18. RDOUT enables one input to the

leading edge of RDOUT H. The Read flip-flop goes to

WRITE TIME L gate. At the same time that the Write

the set state and operation continues as described for

flip-flop clocks to the set state, WRITE TIME L goes

DATO or DATOB bus transactions.

low, enabling CLK MDRO and 1 H gates. Since a

DATO bus cycle is in progress, BWTBT L remains

4.3.2.5

passive during the data transfer portion of the bus

tion and Vcc switch circuits are shown in Figure 4-19.

cycle. Hence, RWBT H is low, WRITE WORD H

The dc protection circuit is activated during power-fail

+12V —1

+5v¥*

source

SV
*

5V*

DELAY CKT

BDCOK H

DCProtection and Vce Switch — DC protec-

Vee

+12V

vec2 OK H | SWITCH

1.5V TO

X-Y DRIVERS

RESET L

PWR FAILH
LOCKOUT L I

RESET H

BINIT L

cP-1788

Figure4-19

DC Protection and Vec Switch Circuits

4-23

or bus initialize conditions. BDCOK H and BINIT L

V is removed, all MMV11 memory operations are

are inverted and ORed to produce LOCKOUT L.

disabled. However, if +5V is removed and the +12V

Normally, this signal is passive (high), enabling bank

remains, the 5 V* allows memory protect logic to

addressing and resulting in an active DSEL H signal

remain functional.

when the memory is addressed. However, if BDCOK H
goes low (power fail) or BINIT L is asserted low,

RESET Lis also applied to the VCC20K H input to the

LOCKOUT

Vce switch circuit. This signal is high only when both

immediately

inhibits

the

bank

+S5Vand +12V power sources are normal. The Vcc

addressing function.

switch comprises a transistor (Vcc switch), which is

The reset signals are also generated by this circuit.

turned on when power is normal to produce +11.5V

RESET L goes active (low) whenever LOCKOUT L is

power for X-Y driver circuits.

active. A 2 us delay circuit enables the memory to
complete its present cycle before RESET. RESET L is
also inverted to produce RESET H; both signals are

used

clear

(initialize)

memory

timing

4.3.2.6

control

DC-DC

Inverter

—

The

dc-dc

inverter

circuit is shown in Figure 4-20. It is comprised of an in-

circuits.

verter oscillator using a

saturable

transformer,

To produce a SV* source for reset circuits and bus

negative rectifier, and a filter. A 3-terminal regulator

receivers BSYNC L, BDIN L, BDOUT L, BWTBT L,

chip produces the regulated -S V for sense amplifier

and BREF L, +12 V power is regulated. Thus, if +12

operation.

r_INVERTER

]

|
|

I_RE-C_TI—F—IET?_ 1
‘|

FILTER

i
A

L_L_1

+5V

I
|
I

I
I
]

-- e

1]
|
r

|
- -

3-TERMINAL
REGULATOR

-5V TO
* SENSE AMPLIFIERS

i
=

I
]

— _— _
cpP-1789

Figure4-20
4.4

DC-DC Inverter Circuit

MRVI11-A4KBY 16-BIT READ-ONLY

MEMORY

Jumpers that allow the user to select the 4K
memory address space which the MRV11-A

will respond, chip type, and upper or lower

4.4.1

2K segment (when 256 by 4-bit chips are

General

used).

The MRV11-Ais a basic read-only memory module on

which the user can install programmable read-only

memory

(PROM)

masked

read-only

memory

4.4.2

(ROM) chips. All PROM/ROM chip sockets and addressing and control circuits are contained on a single

4.4.2.1

8.5 by Sinch module.

data stored on the module can be addressed and read
by the LSI-11 processor or other DMA devices by exe-

cuting a DATI bus cycle. Data/address lines BDALO-

4096 by 16-bit capacity using S12 by 4-bit

1S L and three bus interface control signals (BSYNC L,

chips or 2048 by 16-bit capacity using 256 by

BDIN L, and BRPLY L) comprise all interface signals

4-bit chips.
Compatibility

General
— Major functions contained on the

MRV11-A module are shown in Figure 4-21. ROM

The MRV11-A features:

®*

Functional Description

required for accessing the read-only memory. BREF L
with

chips

available

from

inhibits BRPLY L and BDAL bus drivers during

multiple sources.

memory refresh operations.

424

AL,SHIAID3YAcim1138

O8v]a1-s

4-25

oxvIg 7

NIQ H

V-TAYNo180Jo[gweldel(
16 -4v8 HA17dY0Q y

o 8]1.7vas

gv19]a

1vas 710

NASHO —

g] 7 siL 1vas

,
(
8
3
0
0
2
3
0
7vas18g] _ _

S19WasAS7]sgyvle]ysvaONAS+1—AST0QAldHHOL1oVqum/vivae>103735
T H S8S

—oO

4.4.2.2

Addressing — A master device can address

in Figure 4-22. Bank Select Stored (SBS H) is gated to

any 16-bit word in the 4K module by placing appro-

produce a low SEL L enable signal, which is applied to

priate address bits on BDAL1-15 L during the ad-

the D input of the decoder. (The decoder is actually a

dressing portion of the DATI cycle. BDALO is not used

decimal decoder; whenever a high signal is applied to

on the MRV11-A since this address bit functions only

its D input, outputs 0-7 are inhibited.) One decoder

as a byte pointer during DATOB and the write portion

output goes low, enabling the appropriate physical row

of DATIOB bus cycles. Bus receivers route DAL13-15

addressed by bits SA10-12 L.

H to the bank select decoder and DAL1-12 H to the address storage latch. Bank selection occurs when the 4K

When 256 by 4-bit chips are used, jumpers W8, W9,

address encoded on DAL13-15 H is equal to the user-

and W10 are removed and jumpers W11, W12, and

configured value selected by jumpers W17-W1S. The

either W13 or W14 are installed, as shown in Figure

resulting bank select (BS H) and address bits DAL13-

4-23. SA10 and SA11 are applied to octal decoder A

15 H are then stored in the address storage latch on the

and B inputs, respectively. Bit SA9, which is not used

leading edge of BSYNC L. Stored address bits SA1-8 H

to directly address the 256 by 4-bit chips is then applied

are buffered to produce BA1-9 L which are applied to

to input C of the octal decoder. SA12 H and SA12 L are

all

ROM /PROM

chips on the module.

available for jumper selection

of the desired

segment within the 4K bank. W13, when installed,
selects the lower 2K; W14 selects the upper 2K. When

When 512 by 4-bit chips are used, SA9 H is routed via
jumper W10 to a buffer, producing the inverted BA9
L address bit for all chips (pin 14). However, when
256 by 4-bit chips are used, W10 is removed and W12
is connected, forcing a low (chip enable) signal to
become applied to all chips (pin 14); note that 256 by
4-bit chips do not receive address bit 9.

the selected segment is addressed, OP SEL goes high.
This signal is gated with SBS H to produce the low

(active) octal decoder enable signal.
4.4.2.3

read by the bus master device. Data is available within
120 ns after BSYNC L is received. One active CEO-7 L

Memory chips sockets are arranged in eight physical

signal produces the active DO RPLY H signal, which

rows of four sockets each. The memory is expanded by

enables reply and BDAL bus driver gating. Active DO

installing all four chips in each desired row. Four chips

provide

the

full

16-bit

word

storage

for

Data Read Operation — Once the ROM/

PROM chip sockets are addressed, the data can be

RPLY H and SYNC H signals are gated, producing the

LSI-11

REPLIED L signal, which enables one of the two bus

instructions and data. Only one row is enabled by a

driver enable inputs. The remaining enable input is

chip enable (CE) signal, produced by chip row select

MDIN L. The bus master device asserts BDIN L to

logic and chip type jumpers.

request the data. DIN H is ANDed with the passive
(high) SREF L signal, producing MDIN L, and read

When 512 by 4-bit chips are used, jumpers W8, W9,

data i1s enabled onto BDALO-15 L. Active MDIN L,

and W10 are installed. The chip row select octal

SYNC L, and DO RPLY H signals also enable the

decoder receives stored address bits SA10, SA11, and

BRPLY L bus driver, producing the required response

SA12 onits A, B, and C inputs, respectively, as shown

toBDIN L.

BA1-8L
SA1-8H

W10 ysa9 H

BUFFERS

BA9 L

(ADDRESS BIT)

CEOL

SA10H

SA11 H

SA12 H
+3v

CE1L

o—0

W8
OP SEL H

CE2L

CE3
L

SA9/12 H
)SEL L

SBS H

¢ OCTAL
o CE4 L
L
DECODER [PGgs
O

CE6 L

0O————————

CE7T
L

~Nlolol
sl
=] O

SA9H

PHYSICAL

MEMORY
ROWS

11-3159

Figure4-22

512 by4-Bit Chip-Jumper Configuration

4-26

BA1-8L
SA1-8 H
BUFFERS

w12

+3v

9
BA9L
(CHIP HIP E ENABLE )

JSA9H

SA9 H

CEOL

W11
ASEN

w14
N

SAt2 H

SA12 L

—O- = O—

SA9/12H
OP SEL H

CE3L
CE4L

C OCTAL

PHYSICAL
YMEMORY

41({RrROWS
3

CE7LL_-

WI3 AND Wi4 ARE

DECODER C
P es
L |
=

SEL L

SBS H —

b
CE7L|

SEGMENT SELECT JUMPERS

(ONE INSTALLED)
W13
= LOWER 2K

w14= UPPER

2K
I1-3158

Figure4-23

256 by4-Bit Chip-Jumper Configuration

When the system is in a memory refresh operation, the

User-configured 4K

addresses

—

Three

jumpers allow user address configuration.

MRV11-A must not respond to the BSYNC/BDIN

refresh bus transactions. BREF L is asserted during
the addressing portion of the bus cycle and the refresh
latch stores REF H on the leading edge of SYNC L.

4.5.2

SREF L goes low and inhibits the MDIN L signal.

Major functions contained on the MSV11-B module

Hence, BDAL and BRPLY L bus drivers are not

are shown in Figure 4-24. Memory data can be stored

enabled.

4.5

Functional Description

(written) or read by the LSI-11 microcomputer, or

other bus master devices operating in the DMA mode,

MSV11-B4KBY 16-BIT SEMICONDUCTOR

with appropriate bus cycles: DATO (16-bit word write

READ/WRITE MEMORY

operation);

DATOB

(8-bit

byte

write

operation);

DATI (16-bit read operation); or DATIOB

4.5.1

General

[16-bit

read-modify-write (8 or 16-bit) operation].

The MSV11-B is a 4K by 16-bit dynamic MOS read/
write memory module which can be used for temporary

storage of user programs and data.

The storage

Addressing is initiated by a master device (either the

capacity is 4096, 16-bit words. Memory address selec-

LSI-11 processor or

tion is user-configured by installing or removing
jumpers contained on the module. Memory refresh is
directly controlled by LSI-11 bus signals.

L, latching the address (and bank select information)

Refresh

in the address register. Address bits are routed from

operations can be automatically controlled by the

the BDAL bus receivers onto the module’s DALO-15 H

LSI-11 microcomputer module once every 1.6 ms

bus to the 13-bit address and bank select register input.

(approximately) or performed by another device. The

Address bits BDAL13-15 L are decoded by the bank

MSV11-B is LSI-11 bus-compatible and capable of

either

programmed

I/0

data transfers

with

address decoder. Decoder output signal BS H will go

the

active (high) only when the jumper-selected bank

processor or DMA transfers with other LSI-11 bus

address is decoded. The active BS H signal is stored

devices.

along with the 13-bit memory address for the duration
of the operation.

The MSV11-B features:
®

4096 by 16-bit word.

Fastaccess time — 550 ns maximum.

The memory array comprises sixteen 16-pin 4K by

1-bit memory chips which require the address multiplexer to address the array with two 6-bit bytes.

Low power — 12.7 W for the module, worst

Address multiplexer control logic responds to the

case.

a DMA device) by placing the

16-bit address on BDALO-15 L and asserting BSYNC

active SYNC H and stored active bank select (LBS L)

Dynamic MOS memory chips — Refresh is

signal

automatically controlled by processor or by

Address Strobe (RAS). This signal remains active for

a DMA device.

the duration of the active SYNC H signal. Address

4-27

by immediately generating

active

Row

L| B ILAUZ
AV

BDAL!I L E}—i

—d

BDAL?2 L| B ILBEZ

BOAL3 L | B BF2

212

—q

apALs L [B 222

—Q

BK2

BDAL®6 Ll B IL

—g

BDALSL @BNZ

—9

BP2

soaLtt L8}

BR2

BDAL13L[ B ILBTZ

BDALMLE,LBU2

BDAL|5L@3V2
AN2

O—=e—

REF

—

p—e— DRIVE L

0
o

BIAKO LB

RECEIVERS

BDAL 12 L@

BIAKI L | B |

DAL®
- 15H

AND

BS2

AM2

BUS
pRIVERS

——d

BDALBLlBllBMZ
BDAL1OL| B lr

4K
X 16

DYNAMIC

MOS MEMORY
ARRA Y

PBL2

soaL7 L[8

D@-15H

—

DALO-12H

apaLa L [B ]

BDAL

BANK
AV1

AD2,

+58 D_V. +5V

BS
H

ADDRESS

DECODER

BANK

SELECT

JUMPERS

J
LDALI-6

BSYNC L—{ >o—
AJ2

’

ADDRESS

W4 REF REPLY

DISABLE

AS2

|| gs |

SYNC H

REF L

AMX L
ADDRESS

MULTIPLEXER

REF H

CONTROL

LOGIC

PCAS H
AF2

RPLY H

RAS L

CAS L

REPLY
LOGIC

BDIN L AH2

SAO H

DRIVE L

DINH

LBS H

WORD /

WTBT H

BWTBTL

BDCOK H -9V,-5V [
BA4

DCOK

5V —*

INVERTER

DOUT

wg L

BYTE

SELECT

LOGIC

DOUT

spouT L[ BJAEZ,

GND

12:6BIT | Ag-5H

ADDRESS

SELECT

> REEL

AR{
BREF L .+I:>¢
->
»

BRPLY L

AND BANK
| LDAL7-12H 4> MULTIPLEXER
REGR

some1 L[ B JAR2
BOMGO L| B |

13-BIT

SYNC L

wit

" MEMORY CHIPS
-9V

-5V

TO ADDRESS

MULTIPLEX CONTROL LOGIC

DACZ,ATL AJ1, AM1,BC2,BTY,BJ1,BMI
L
11-3454

Figure4-24

MSV11-B Logic Block Diagram

4-28

multiplex control AMX L is initially passive (high),

simply a series of forced memory read operations where

multiplexing the stored row address bits (LDAL7-12

only the row addresses are significant. Each of the 64

H) through the 12:6-bit address multiplexer and into

rows in all dynamic MOS memory chips in an LSI-11

all memory chips. After approximately 150 ns, address

system are simultaneously refreshed in this manner.

multiplex control logic generates an active column

The REF H signal inhibits all BDAL bus drivers for the

address strobe (CAS) and an active AMX L signal.

duration of the refresh operation.

Multiplexer column address bits (LDAL1-6 H) are
then strobed into all memory chips. This completes the

A dc-to-dc inverter circuit is included on the module

chip addressing portion of the memory operation.

for

negative

voltage

generation.

Output

voltages

include -9 V for the MOS memory chips and -S V for
When in a memory read operation, the bus master

linear devices in the address multiplex control logic.

device asserts BDIN L. The data from the accessed

Hence, only +12 V and

mernory Jocation is present on the DO-15 H bus and at

required for module operation. The BDCOK H signal

bus driver inputs. Reply logic responds to BDIN L by

starts dc-to-dc inverter oscillation when bus power is

generating an active DRIVE L signal which gates the

applied.

+S5 V power inputs are

memory read data onto BDALO-15 L for input to the
requesting device; reply logic also asserts BRPLY L to
complete the data transfer portion of the cycle.
When in a memory write operation (or the write portion
of a DATIOB cycle) the addressing portion of the

operation is similar to the read cycle addressing. After
the addressing portion of the cycle has been completed,
the master device asserts BDOUT L, and BWTBT L
either goes passive (high) if a DATO (word) write cycle
is to be performed, or remains asserted if a DATOB

(byte) write cycle is to be performed. Word/byte select

4.6

(Paragraph 4.6 and Figure 4-25 are deleted.)

4.7

DLV11 SERIAL LINE UNIT

4.7.1

General

The DLV11 is the basic interface module used for con-

necting asynchronous serial line devices to the LSI-11
bus. All circuits are contained on a single 8.5 by S inch
module.

logic responds to the DATO cycle by asserting both W0
L and W1 L for the duration of the cycle, enabling
DALO-15 H bits to be written into the addressed

The DLV 11 features:

location in all memory chips. However, in a DATOB
cycle with AQ H low (even byte), only WO L goes active,

Either an optically isolated 20 mA current

enabling the writing of DALO-7 H into the addressed

loop or an EIA interface selected by using the

location

appropriate interface cable option.

the

appropriate

eight

memory

chips.

Similarly, if AO H is high (odd byte), only W1 L goes

Selectable crystal-controlled baud rates: S0,

active, enabling only DALS8-15 H bits to be written into
the

addressed

location

the

appropriate

75, 110, 134.5, 150, 200, 300, 600, 1200,

eight

1800, 2400, 4800, 9600, and an externally

memory chips. The reply logic also responds to the
active BDOUT L signal by asserting BRPLY

supplied rate.

indicating that the data has been written, completing

Jumper-selectable

the data transfer.

formats.

stop

bit

and

data

bit

LSI-11 bus interface and control logic for in-

The memory chips in the MSV11-B require a refresh

terrupt processing and vector generation.

operation once every 1.6 ms. This operation is entirely
under the control of either processor microcode or a

Interrupt priority determined by electrical

DMA device, as selected by the user. The address

position along the LSI-11 bus.

multiplex control logic responds to BREF L, generated

by the refresh-controlling device,

Control/status

by simulating a

(CSR)

and

data

registers compatible with PDP-11 software

“bank selected’’ operation. (All system memory banks

routines.

are simultaneously selected during refresh.) Refresh is

CSRs and data buffer registers

directly accessed via processor instructions.

then accomplished by a device by executing 64 succes-

sive BSYNC L/BDIN L operations while incrementing

Plug, signal, and program compatible with

BDAL1-6 by one on each bus transaction. Refresh is

PDP-11 DL11A, B, C series.

4-29

This page intentionally left blank.

4-30

This page intentionally left blank.

4-31

4.7.2

from either the receiver (RCSR) or transmitter (XCSR)

Functional Description

control/status registers is performed.

4.7.2.1

General
— Major functions contained on the

DLV11 module are shown on Figure 4-26. Communi-

4.7.2.5

cations between the LSI-11 microcomputer and the

responds to the address present on the bus when

Address Decoding— Address decoding logic

DLV11 are executed via programmed I/O operations

BSYNC L is asserted. The DLV11 device address is

or interrupt-driven routines, as described in Chapter 3.

contained on RDAB3-12 H, along with address bits

4.7.2.2

decoding logic. Address bits are not required for bank

RDABQO, 1, and 2 H, which are decoded by function

UAR/T Operation — The main function on

the DLV 11 module is the Universal Asynchronous Re-

selection since all devices, such as any DLV11, reside in

ceiver/ Transmitter (UAR/T) chip. This is

a40-pin LSI

the upper 4K bank (addresses ranging from 28-32K).

chip that is capable of parallel I/O with the computer

The processor generates an active BBS7L signal, indi-

bus and asynchronous serial I/O with an external

cating an I/0 device addressing operation. Address

device.

Jumpers which allow the user to select parity

selection jumpers A3-A12 allow the user to configure

functions, number of stop bits, and number of data

address bits 3-12, as described in Paragraph 6.2.2.

bits are described in Paragraph 6.2.2. Both transmit

When the DLVI11 is addressed, device selection is

and receive functions are totally asynchronous

indicated by an active ME signal. This signal remains

operation. The transmit clock is always driven by the

active throughout the entire I/O cycle (while BSYNC L

baud rate generator’s CLK L signal. CLK L is applied

remains active), enabling function decoding.

to one MSPAREB backplane pin (BK1), where it is
connected to MSPAREB pin BL1; this is the receive

4.7.2.6

function UAR/T

decoding and control logic decodes DLV11 internal

clock input (RCLK L) signal.

Function Decoding and Control — Function

gating functions based upon address selection, address
bits RDABO, 1, and 2 H, bus signals BDIN L, BDOUT

When a user application requires split transmit and re-

ceive baud rates, the MSPARE jumper can be broken

L, and BSYNC L, and the VEC L signal generated by

from pins BK1 and BL1 and an external receive baud

the interface control logic. In addition to generating

rate signal can be applied to BL1 (the drive frequency

function select signals, this circuit inverts BSYNC L to

should be 16 times the desired baud rate).

produce SYNC H whose leading edge clocks

the

address decoding logic. A truth table of function select

4.7.2.3

signals is provided in Table 4-2.

Baud Rate Generator — The baud rate

generator produces the desired UAR/T clock and a
fixed 2.4576 MHz clock for the -12 V inverter circuit. A

4.7.2.7

crystal-controlled oscillator produces the basic 2.4576

logic produces the BRPLY L signal in response to 170

MHz frequency for the baud rate generator. A single

operations, contains the interrupt control logic, and

baud rate generator chip divides this frequency to

receives and distributes the BINIT L initialize signal.

produce the available baud rates.

Jumpers, which are

This function also contains the Transmit Data Inter-

described in Paragraph 6.2.2, select the desired baud

rupt Enable (TDINTEN H) flip-flop and Receiver

Data Interrupt Enable (RDINTEN H) flip-flop; both

rate for the CLK L output signal.

flip-flops

4.7.2.4

Interface Control Logic — Interface control

can

read

or written

by the

LSI-11

microcomputer. RDINTEN is set or reset by BDAL6 L;

Bus Drivers and Receivers
— Bus drivers and

receivers interface directly with the LSI-11 bus. Line

the flip-flop

receivers produce RDABO-12 H signals in response to

SELOOUT L. Similarly, TDINTEN is set or reset by

BDALO-12 L bus signals. When an input data or vector

BDALS6 L; this flip-flop is clocked on the leading edge

transfer is desired, function decoding and control logic

of SEL4AOUT L.

generates an active INPUT ENABLE signal, which

clocked

the

leading

edge

Receiver-generated interrupts occur as a result of the

enables the bus drivers. When a data input operation is

RDINTEN flip-flop being set (interrupts enabled) and

selected, the UAR/T receiver data buffer contents

an active receiver Data Available (DA H) UAR/T

(RDO-7 H) are routed through the data selector

status signal. When this condition occurs, the Recetver

(DDABO-7H) to the BDAL bus. When responding to

Data Interrupt Request flip-flop sets and generated an

an interrupt acknowledge signal, interface control

active BIRQ L signal. The LSI-11 microcomputer re-

logic generates VEC L, which selects the vector address

sponds (if its PS bit 7 is not set) by asserting BDIN L;

produced by jumpers W6-W10 (Paragraph 6.2.2). In

this enables the device requesting the interrupt to place

addition, DALO, 6, 7, and 15 are driven by CSR

its vector on the BDAL bus when the interrupt request

selection and gating circuits when a data input transfer

4-32

TBMT

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1—’ INITH

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Figure4-26

DLV11 Logic Block Diagram

4-33

Table 4-2

DLV11 Function Decoding
Address Inputs

Control Inputs

Function Select Signals (low-active)

BDINL |BDOUTL | MEL

|SELOINL | SEL2INL | SEL4INL

is acknowledged. The processor then asserts BIAKO

|SELOOUTL | SEL6INL

[SEL4OUTL|SEL6OUTL

Read RCSR (SELOIN L asserted)

L, acknowledging the interrupt request. The interface

CARRIER or CLR TO SEND or DATA SET

control logic receives

READY

BIAKI

and

responds

generating active VEC L and BRPLY

L signals,

DAH

placing its interrupt vector on the LSI-11 bus and
clearing the BIRQ L signal. Once the service routine

—

BDALI1S

BDAL7

ROINTENH

—

BOAL6

for the DLV11’s receive function has been entered, the

receiver data buffer (RBUF) can be read. The stored

Read XCSR (SEL4IN L asserted)

BIAK signalis cleared when the next BIAKI L signal is

TBMTH

received and the DLV 11 is not requesting an interrupt.

TDINTENH

BREAKH

Transmitter-generated interrupts occur in a manner

similar to the receiver-generated interrupts. However,

4.7.2.9

they occur as a result of the TDINTEN flip-flop being

BDAL7
-+

—

BDAL6

BDAILO

Break Logic — Break logic comprises the

Break status flip-flop. It is set or cleared by the LSI-11

set (interrupts enabled) and when the Transmitter

microcomputer by BDALO L while executing a bus out-

Buffer Empty (TBMT H) UAR/T signal is active

put cycle with the XCSR. Thus, the duration of the

(high). Once the service routine has been entered for

break

the DLV11’s transmit function, the transmitter data

signal

program

controlled.

The

Break

flip-flop is clocked on the leading edge of the SELA-

buffer (XBUF) can be loaded and a new character

OUT H signal. When set, the serial output line is con-

transmission initiated. Note that if the transmitter and

tinuously asserted (space). The status of the Break flip-

receiver functions request interrupts simultaneously,

flop can be read in XCSR bitO.

the receiver function has priority over the transmitter.
If BIAKI L is received and the DLV11 is not requesting

4.7.2.10

an interrupt, it passes BIAKO L for a lower priority

Reader Run Logic — The reader run logic

enables DLV11 generation of a READER RUN pulse

interrupt request.

for 20 mA current loop teletypewriter devices. It is

enabled by loading RCSR bit 0; the LSI-11 micro-

The interface control logic also generates the DLV11’s

computer asserts BDALO L and causes generation of

BRPLY L signal. It generates this signal when any

the SELOOUT H signal (load RCSR). READER RUN

function select signal is asserted or VEC L is generated.

is asserted and remains active for the duration of onehalf of a start bit. The start bit of the serial input (SI)

The system initialize signal (BINIT L) is generated by

from the low-speed reader initiates a 4-bit binary

the processor to reset all peripheral device registers.

counter. When eight CLK L pulses have been counted

Interface control logic responds by clearing all control

(equivalent to one-half of the start bit), READER

flip-flops, including the Interrupt Request, Interrupt

RUN is negated. After the complete character has been

Acknowledge, and Break flip-flops. The UAR/T’s

read by the LSI-11 microcomputer, the next character

RBUF and XBUF data registers are not cleared by

can be read in the same manner.

BINIT L; however, the initialize signal does clear the
DA H ssignal and set the TBMT H signal.

4.7.2.8

—

4.7.2.11

EIA Interface Circuits — An EIA interface

CSR Selection and Gating — CSR selection

is provided by EIA drivers and receivers. EIA signal

and gating logic enables the LSI-11 microcomputer to

drivers are provided for EIA TRANS DATA, RQST

read receiver and transmitter control/status bits.

TO SEND, DATA TERMINAL READY (always an

Functions are summarized below.

active high/space state), and BUSY (always an active

4-34

low/mark state). Jumper EIA applies -12 V to the EIA

Four control lines to the peripheral device for

driver chip when the DLVI11 is wused with
EIA-compatible devices. EIA signal receivers are

NEW

MITTED, RQSTA, and RQSTB.

provided for EIA DATA IN, CARRIER or CLEAR TO
SEND, and DATA SET READY. The optional BCOSC
modem cable connects the output signal of the EIA
DATA IN driver (EIA/TTLRCVD DATA) to the TTL

Logic compatible with TTL or DTL devices.

SERIAL DATA IN input tothe UAR/T.

Maximum drive capability of 25 ft of cable.

4.7.2.12

20 mA Loop Current Interface — The 20

4.8.2

General
— Major functions contained on the

DRV11 module are shown in Figure 4-27. Communications between the LSI-11 microcomputer and the
DRV11 are executed via programmed 1/0O operations

or interrupt-driven routines, as described in Chapter 3.
The DRV11 is capable of storing one 16-bit output

used with a 110 baud teletypewriter device, a 0.00SuF,

word or two 8-bit output bytes in DROUTBUF. The

100 V filter capacitor should be installed between

stored data (OUTO-1S H) is routed to the user’s device

terminals TP1 and TP2.

via an optional 1/0O cable connected to J1. Any programmed operation that loads either a byte or a word in

-12 V Inverter — The -12 V inverter circuit

DROUTBUF causes a NEW DATA READY H signal

generates -12 V for use by the UAR/T chip and EIA

to be generated, informing the user’s device of the

driver and receiver chips. Input to the circuit is the

operation.

CLK signal (2.4576 MHz) and +12 V. The output is
zener regulated to-12'V.

Input data (DRINBUF) is gated onto the BDAL bus
during a DATI bus cycle. All 16 bits are placed on the

DRVI11 PARALLEL LINE UNIT

bus simultaneously; however, when the processor is involved in 8-bit byte operation, it uses only the high or

General

low byte. When the data is taken by the processor, a

The DRV11 is a general-purpose interface unit used

DATA TRANS H pulse is sent to the user’s device to

for connecting parallel line devices to the LSI-11 bus.

inform the device of the data transfer.

All circuits are contained on a single 8.5 by S inch
module.

4.8.2.2

Addressing— When addressing a peripheral

device interface such as the DRVI11, the processor

The DRV11 features:

places an address on BDALO-1S L, which is received
and distributed as BRDO-15 H in the DRV11. The
address is in the upper 4K (28-32K) address space. On
the leading edge of BSYNC L, the address decoder

16 diode-clamped data input lines.
16 latched output lines.

decodes the address selected by jumpers A3-A12 and

16-bit word or 8-bit byte programmed data

sets the Device Selected flip-flop (not shown); the
active flip-flop output is the ME signal, which enables
function selection and 1/0 control logic operation. At
the same time, function selection logic stores address

transfers.

User-assigned device address decoding.
LSI-11 bus interface and control logic for in-

bits BRDO-2.

terrupt processing and vector generation.
Interrupt priority determined by electrical

4.8.2.3

position along the LSI-11 bus.

Control/status

TRANS-

Functional Description

4.8.2.1

DATA IN input of the UAR/T. When the DLV11 is

4.8.1

DATA

Program-controlled data transfer rate of 90K

optical coupler signal output to the TTL SERIAL

4.8

READY,

words per second (maximum).

mA loop current interface is provided by optical
isolation. An active 20 mA current loop is provided
when jumpers CL1 through CL4 are installed. If the
jumpers are removed, 20 mA passive current loop
operation is selected. The optional BCOSM cable
assembly connects the 20 mA/TTL RCVD DATA

4.7.2.13

DATA

registers

(CSR)

Function Selection
— Function selection and

I/O control logic monitors the ME signal and bus

and

signals BDIN L, BDOUT L, and BWTBT L. It re-

data

registers that are compatible with PDP-11

sponds by generating appropriate Select signals which

software routines. Plug, signal, and program

control internal data gating,

compatible with DR11-C.

or DATA TRANS H output signals for the user’s

4-35

NEW DATA READY H

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4-37

device, and the BRPLY L bus signal which informs the

the LSI-11 bus. Data to be read is provided by the

processor that the DRV11 has responded to the pro-

user’s device on the INO-15S H signal lines. Since the

grammed I/0 operation. Since the

DRV 11 appears to

input buffer consists of gating logic rather than a

the processor as three addresseable registers (DRCSR,

tlip-flop register, the user’s device must hold the data

DROUTBUF, and DRINBUF) that can be involved in

on the lines until the data input transaction has been

either word or byte transfers, the three low-order

completed.

address bits stored during the addressing portion of the
bus cycle are used for function selection. The select

The input data is read during a DATI sequence while

signals relative to 1/0 bus control signals and address

bus drivers are enabled by the SEL4IN L signal. The
DATA TRANSMITTED pulse that is sent to the user’s

bits 0-2 are listed in Table 4-3.

device by the function select logic informs the device of

NEW DATA READY H is active for the duration of

the transaction. Input data can be removed on the

BDOUT L when in a DROUTBUF write operation.

trailing edge of this pulse.

This signal is normally active for 300 ns. However, by

adding an optional capacitor in the BRPLY L portion

4.8.2.7

of the circuit, the leading edge of BRPLY L is delayed,

DROUTBUF

effectively increasing the duration of the

enabling either

NEW DATA

DROUTBUF
1is

Output

comprised

16-bit

Data

of two

word

Transfer
8-bit

8-bit

byte

—

latches,

output

READY H pulse to 1200 ns (maximum); adding the

transfers. Two SEL 2 signals function as clock signals

capacitor also increases the DATA TRANS H pulse

for the latches. When in a DATO bus cycle, both

width in exactly the same manner.

signals clock data from the internal BRDO-15 H bus
into the latches. However, when in

a DATOB cycle,

H is active for the duration of BDIN L

only one signal clocks data into an 8-bit latch, as

when in a DRINBUF read operation. This signal is

determined by address bit 0 previously stored during

normally active for 300 ns. The time, however, can be

the addressing portion of the bus cycle.

DATA TRANS

extended by adding the optional capacitor to the
BRPLY

portion

the

circuit

previously

The NEW DATA READY H pulse generated by the

described.

function select logic is sent to the user’s device to

4.8.2.4

be input to the device on the trailing edge of this pulse.

inform the device of the data transaction. The data can

Read Data Multiplexer — The read data

multiplexer selects the proper data and places it on the

BDAL

bus

when

the

processor

inputs

4.8.2.8

DRCSR,

Interrupts — The DRVI11 contains LSI-11

DRINBUF

bus-compatible interrupt logic that allows the user’s

contents are gated onto the bus separately. The select

device to generate interrupt requests. Two independ-

signals

ent interrupt request signals (REQ A H and REQ B H)

produced by the interrupt logic, control read data

are capable of requesting processor service via separate

selection.

interrupt vectors. In addition, DRCSR contains two

DROUTBUF

(previously

interrupt

described)

vectors;

and

VECTOR

interrupt enable bits (INT EN A and INT EN B) (bits 6

DRCSR Functions — The control/status

and S, respectively), which independently enable or

disable interrupt requests. REQ A and REQ B status

Four of the six significant DRCSR bits can be involved

can be read by the processor in DRCSR bits 7 and 15,

in either write or read operations. The remaining two

respectively.

bits, 7 and 15, are read-only bits that are controlled by

provided for each request, one of the requests could be

the external device via the REQ A H and REQ B H

used to imply that device data is ready for input and the

4.8.2.5

Since

separate

interrupt

vectors

are

signals, respectively. The four read/write bits are

remaining request could be used to imply that the

stored in the 4-bit CSR latch. They represent CSRO and

device is ready to accept new data.

CSR1 (DRCSR bits0 and 1, respectively), which can be

Aninterruptsequenceis generated when a DRCSR INT

used to simulate interrupt requests when used with an
optional maintenance cable. INT ENB A and INT

EN bit (A or B) is set and its respective REQ signal is

ENB B (bits 6 and S, respectively) enable interrupt

asserted by the device. The processor responds (if its PS

logic operation.

bit 7 is not set) by asserting BDIN L; this enables the

Note that CSRO

and

CSR1

are

device requesting the interrupt to place its vector on the

available to the user’s device for any user application.

BDAL bus when the interrupt request is acknowl-

4.8.2.6

edged.

DRINBUF Input Data Transfer — DRIN-

The

processor

then

asserts

BIAKO

acknowledging the interrupt request. The DRVI11

BUF is an addressable 16-bit read-only register that
receives data from the user’s device for transmission to

receives BIAKI L and the interrupt logic generates

4-38

tion, program execution can be initiated via console

VECTOR H, which gates the jumper-addressed vector
information through the read data multiplexer and bus

ODT commands. The LTC ON/OFF

drivers and onto the LSI-11 bus. The processor then

disables

proceeds to service the interrupt request as described in

(BEVNT L) signal. One spare LED indicator is in-

Chapter 3.

cluded. Two fans provide cooling air for the H780

H780 generation

switch enables or

of the line

time

clock

power supply and all modules contained in the PDP-

4.8.2.9

11/03 enclosure.

Maintenance Mode — The maintenance

mode allows the user to check DRV 11 operation by inThe H780 features:

stalling an optional BCO8R cable between connectors

J1 and J2. This maintenance cable allows the contents

of the output buffer DROUTBUF to be read during a
DRINBUF DATI bus cycle. In addition, interrupts

+5V + 3%, 18 A (maximum) and +12V

can be simulated by using DRCSR bits CSRO and

power must not exceed 120 W.

CSR1. CSR1isrouted via the cable directly to the REQ

Overcurrent/short circuit protection — QOut-

B H input and CSRO is routed to the REQ A H input.

put voltages return to normal after removal

By setting or clearing INT EN A, INT EN B, and CSRO
and CSR1 bits in the CRCSR register, a maintenance

of overload or short. Current limited to approximately 1.2 times the normal maximum

program can test the interrupt facility.

4.8.2.10

3%, 3.5 A (maximum); combined dc

rating.

Initialization — BINIT L is received by a

bus driver, inverted, and distributed to

DRV 11 logic to

Overvoltage protection — +35 V limited to

initialize the device interface. The buffered initialize

+6.3 V (approx); +12 V limited to +15V

signal is available to the user’s device via the AINIT H

(approx).

and BINIT H signal lines. DRV11 logic functions

Dual primary power configuration — Can be

cleared by the BINIT signal include DROUTBUF,

connected for nominal 115 V, 60 Hz or 230

CRCSR (bits 0, 1, 5, and 6), and interrupt logic.
4.9

V, 50 Hz input power.

H780 POWERSUPPLY

Efficiency — Switching regulator circuits
provide greater than 65 percent overall effi-

4.9.1

General

ciency.

The H780 power supply provides dc operating power to

System control/indicator panel — A simple

all backplane slots contained in a PDP-11/03 micro-

system control/indicator panel allows the

computer system. Depending upon the configuration

user to control dc power on/off and micro-

ordered, the primary power input is 115 or 230 Vac, 50

computer

or 60 Hz. In addition to providing operating power, the

Run/Halt

mode.

Indicators

display the actual dc power and processor

H780 generates power supply status and line time clock

status.

signals which are distributed over the LSI-11 bus.
Three LED indicators and three switches are on the

Line Time Clock — A bus-compatible sig-

H780’s front panel. The

indicators include RUN,

nal is generated by the power supply for the

which illuminates when the LSI-11 processor is in the

event (line time clock) interrupt input to the

run state, and DC ON, which illuminates when normal

processor. This signal is either SO or 60 Hz,

depending upon primary power

operating voltages

are

applied

the

LSI-11

backplane. The DC ON indicator status is controlled

line

fre-

quency input to the power supply.

by circuits contained in the H780. The DC ON/OFF

Power Fail/Automatic Restart — Fault de-

switch allows the operator to turn off the H780 dc out-

tection and status circuits monitor ac and

put voltages without turning off system primary power.

dc voltages

This allows safe module installation or removal with no

and

generate

bus-compatible

BPOK H and BDCOK H signals (respective-

dc power applied to the backplane. A normal power-

ly) to inform the LSI-11 system modules of

up/power-down sequence is produced when this switch

power supply status.

is operated. The ENABLE/HALT switch enables the
operator to manually assert the BHALT L bus signal,

Fans — Built-in fans provide cooling for the

causing the LSI-11 microcomputer to execute the con-

power supply and LSI-11 modules contained

sole (ODT) microcode. When in the ENABLE posi-

in the PDP-11/03 enclosure.

4-39

4.9.2

Backplane Signals

Specifications

BPOK H
Electrical

BDCOKH

Input Voltage

BEVNTL

100—127Vrms, S0 +

1Hzor60 + 1Hz

BHALTL

200—254V rms, S0 +

1Hzor60 +1Hz

SRUNL

Input Power (full load)

Mechanical

400 W maximum

Cooling
Two self-contained fans provide 200 LFPM air

Output Voltages

flow.

+3SV * 3%,0—18 A load (static and dynamic)

+12V * 3%,0—3.5 A load (static and

Size

dynamic)

S5-1/2in.w x 3-1/2in.
h x 14-5/8 in.

Maximum output power: 120 W (total)

Weight

Output Protection

131bs

Current limited to 1.2 times maximum normal
rating (approximately)

Environmental

Voltage +5 V and +12 V outputs limited to

Temperature

5°—50° C operating

+6.3 V (nominal) and +15 V (nominal). respectively

Humidity

90
% maximum without condensation

Output Ripple
S V output: Less than 100 mV pk-to-pk

4.9.3

12 V output: Less than 200 mV pk-to-pk

Output Regulation

4.9.3.1

Functional Description
General
— Major functions contained in the

Line:

+S5V,1.0% max

+12V,0.5% max

functions include circuits which produce unregulated

Load:

(Static and dynamic (A1<0.1 A/us):

dc voltage and regulated dc voltage for H780 circuit

+5V, 1% max

operation, +5 V and +12 V switching regulators,

+12V,0.5% max

overload and short-circuit protection, +5V and +12

H780 power supply are shown in Figure 4-28. These

Load Interaction: 1.0%

V crowbar (overvoltage protection) circuits, and logic
signal generation circuits. The following paragraphs

Load Term Stability

describe each of these functions in detail.

0.2% /1000 hr max

Line Protection

4.9.3.2

Unregulated Voltage and Local Power— Un-

H780A (11S V input): Fast blow S A fuse

regulated voltage and local power circuits provide

H780B (230 V input): Fast blow 3 A fuse

operating dc power for power supply logic and control

circuits, and dc power for the +5S V and

Noise

AC component above 100 kHz meets DEC STD

4-29. AC power is supplied to the H780 via an ac input

102.7; H780B units will meet VDE N-12 limits

plug and cable. A toggle switch mounted on the rear of

for European environment.

the H780 assembly applies ac power to the power

Front Panel Control and Indicators

DC ON/OFF

+12 V

regulator circuits. These circuits are shown in Figure

supply. Normally, this switch remains in the ON

switch

position, allowing ac power to be controlled by power

RUN/HALT switch

distribution

and

LTC ON/OFF

PDP-11/03

system

switch

control
is

circuits

installed.

which

Primary

the

circuit

RUN indicator

overload protection is provided by a fuse mounted on

DC ON indicator

the rear of the H780 unit. Primary power circuits are

Spare indicator

factory-wired for 115 Vac (model H780A) or 230 Vac
(model H780B) operation. Power transformer primary

Rear Panel Controls and Indicators

AC ON/OFF

windings and the two fans operate directly from the

power switch

switched ac power.

4-40

-{15V

REGULATOR

-15V

FANS

—

+5V

+5A

REGULATOR

ON/OFF
‘s

;

:
;

PRIMARY
POWER

LOCAL DC POWER

Acy

REC;‘I:‘F[-')IER

PWR

o o

XFMR

FLLTER | +V UNREG

45V

REGULATOR

—o~o—{

SWITCHIN

—

OVERVOLTAGE

_—__L

(CROWBAR)

CKT

AND

'-‘.l:'

OVERLOAD
SHORT-CKT
PROTECTION

BDCOK H

—-.BPOK H
LOGIC

GENERATION _.BEVNT L
SIGNAL

CKTS

——.BHALT L

+12V
SWITCHING

REGULATOR

SRUN L

—-» +12V

i
OVERVOLTAGE

(CROWBAR)
CKT

)

Figure4-28

F3
ON/OFF
5A
[(——O\p,—O0" | O—

‘

* PRIMARY

POWER <

(115V)

H780 Power Supply Block Diagram

PWR
XFMR

<i>FAN§

TRANSIENT

SUPPRESSORS

=}ACV TO

£y o] GENERATION CKTS
LOGIC SIGNAL

+_L.

]

§>FAN§
I
L
o o
*115v PRIMARY POWER CONNECTIONS ARE SHOWN ABOVE (H780A).
|

230V PRIMARY POWER CONNECTIONS
ARE SHOWN BELOW (H780B).

ON/O

FAN ( ;

UNREG

REGULATOR |— +5V
(+5V)
i:

3-TERMINAL

REGULATOR f— —15V
:

XFMR

FAN(i)

- +V

3-TERMINAL

SWR

AC
JOFF
(o

CP-1792

(15V)

1
|

230V <

1,
=

|
1

o
o

CP-1793

Figure4-29

Unregulated Voltage and Local DC Power

4-41

A single center-tapped secondary winding supplies
power for regulator circuits and internal circuit
operation. Conventional full-wave rectifiers and a -15

operates at approximately the regulated output voltage

V, 3-terminal regulator IC provide regulated voltage

regulator is connected to a potentiometer, allowing

for internal distribution. The rectifiers also provide

factory adjustment of the terminal voltage over a -0.7 to

level. Basic regulator circuits are shown in Figure 4-30.

Note that the ground terminal of the 3-terminal

+24 'V (approx) for internal distribution and regulator

+0.5V range. Hence, the 3-terminal regulator output

operation. A 3-terminal regulator integrated circuit

in the +S5 V regulator circuit can range from 4.3 to 5.4

provides +S V logic and control power for H780 cir-

V (approx).

cuits. The +5 V and +12 V regulators use the same

+24 V unregulated voltage for regulation and distri-

Normal switching regulator operation is accomplished

bution to LSI-11 modules. AC voltage from one side of

when the control transistor is turned on. Forward bias

the transformer secondary is also routed to the line

for the control transistor is supplied via R14. It is

time clock (LTC) circuit, which generates a BEVNT L

turned off only during fault conditions (overcurrent or

bus signal for a line time clock processor interrupt.

shorted output voltage) or when the input ac line

When used with a 60 Hz line frequency, the interrupt

voltage is below specifications. Its emitter supplies

occurs at 16.667 ms intervals; a S0 Hz line frequency

unregulated voltage to the 3-terminal regulator. At less

will produce interrupts at 20 ms intervals.

than 50 mA regulator output current (approx), the
3-terminal regulator supplies the output voltage. How-

Basic Regulator Circuit — Both +5 V and

ever, as load current through the 3-terminal regulator

+ 12 Vregulatorcircuitsreceive the +24 V unregulated

is increased beyond this value, the voltage drop across

input power. The +5 V and +12 V regulator circuits

R27 forward biases the driver transistor. The pass

are identical except for component values. Hence, only
the basic +5 V regulator is described in detail.

switch transistor then turns on and applies the unre-

4.9.3.3

gulated +24 V to L2. The output capacitor then

charges toward the +3 V value, current limited by the
The basic regulator is a switching regulator which

inductance of L2. When the output voltage rises to the

operates

main

3-terminal regulator regulation voltage, the 3-terminal

controlling element is a 3-terminal regulator which

regulator turns off; current through R27 stops, and the

+V UN REG.

approximately

kHz.

The

PASS
SWITCH

F 1

SNUBBER
NETWORK

FREE

DRIVER

WHEELING

R27

<¥

R14

— MWW/

_I_

—AAA~

——

AND

PROTECTION

CKT.

> +5V

TO OVERLOAD

SHORT-CIRCUIT

| CONTROL

DIODE

CURRENT
SENSE

3-TERM.

REGULATOR

(+5V)

—
|
| CROWBAR

_
3

CKT

+5V ADJ.

(FACTORY-ADJ.)

|
|

OVERLOAD

SHORT CKT.

I — 15V

—0.5V

PROTECTIO

—_—-—-J
cCP-1794

Figure4-30

Basic Regulator Circuit

driver transistor is not forward biased. Hence the

4.9.3.4

driver and pass switch transistors cut off. The energy

Each H780 dc output is overload and short-circuit pro-

stored in L2 continues to charge the capacitor bank

tected. When in an overload condition, excessive power

slightly beyond the designed output voltage via the freewheeling diode and the current sense resistor. Once the

supply current is sensed, causing both switching
regulators to go off and then cycle on and off at a

Overload and Short-Circuit Protection —

inductor’s stored energy is spent, the load discharges

low-frequency rate (approximately 7.5 Hz) until the

the output capacitor until the output voltage drops

overload is removed. Each time the power supply cycles

below the 3-terminal regulator’s regulation voltage. At

on, the circuit checks for the overload condition. If the

that point, current through R27 increases and turns on

load current returns to normal, the 20 kHz switching

the driver and pass switch transistors, and the cycle

regulator operation resumes.

repeats. Note that as the load is increased, the pass
switch must remain on longer in order to charge the

Overcurrent sensing circuits for +5 V and +12 Vdc

output capacitor to the regulated voltage value. This

outputs are identical except for component values. A S

process repeats at a 12—20 kHz rate, producing the

V power supply overcurrent condition results in an in-

switching regulator operation.

creased voltage drop across the current sense resistor

Switching losses in the pass switch transistor are

transistor. (During normal operation, this transistor is

(Figure 4-31),

forward

biasing the

current

sense

This network

not forward biased.) Current sense transistor collector

operates during the “‘off’’ switching transient (as the

voltage then drops from the normal +24 V (approx) to

pass switch is biased off) by controlling the rate of in-

the +SV regulator output value; this voltage, which is

creasing collector to emitter voltage as collector current

less than the +16 V reference applied to the current

minimized by the snubber network.

limit comparator’s inverting input, is diode-coupled to

decreases.

the comparator’s non-inverting input, causing the
The control transistor is turned off during a fault

comparator’s output to go low; the diode coupling

condition by overload and short-circuit protection cir-

provides an OR logic function for both +5V and +12

cuits. When a fault condition is detected, the control

V overcurrent fault conditions. The comparator’s low

transistor’s base voltage drops to nearly O V, causing it

output signal triggers the 20 us one-shot whose OVER-

to cut off. When cut off, operating voltage is removed

CURRENT

from the 3-terminal regulator and R27 current is 0,

one-shot and sets the Current Limit flip-flop. The

disabling the switching regulator circuit.

OVERCURRENT L pulse is also ORed with the

IPARTOF+5V

SWITCHING REG

L pulse output

LOW

|
CURRENT

the

FREQ CKT

135ms T

m————w———i——»}ngw
D

I
N

[
@5 ;ZVNSCEURRENT

2.0ms

ONE SHOT

[
_

)

ONE
SHOT

LIMIT RESET

+5V HOLDOFF L

E?MR:?TEFN/:T:

TRANSISTOR

(EXTENDED)

——@07

Q8
0202

FROM +12V
CURRENT

UNREG

e VAVAV:

TRANSISTOR
+V

Q12

D19

SENSE

135

SENSE

triggers

CURRENT LIMIT

+12V HOLDOFF L

COMPARATOR

R58

(EXTENDED)

20us

6.4v(NOM.)
vy

ONE-

| ES

SEgT

OVERCURRENT L

—
+

D13

POWER OFF L

FROM

+12V HOLDOFF L

£9

LOGIC SIGNAL ——

GENERATION CKTS

Figure4-31

HOLDOFF

D14
L

Overload and Short-Circuit Protection

4-43

Q12

CP-1796

POWER OFF L signal, turning on the +5V and +12

Q15. An overvoltage is coupled into the circuit via C7,

V hold-off transistors. Both switching regulators are

causing the gate voltage of Q9 to rise; this triggers Q9

then disabled. The high 135 ms one-shot output pulse

and its cathode voltage rises to the output (overvoltage)

is ANDed with the Current Limit flip-flop output,

potential. Q15 then fires and shorts (crowbars) the

turning on

supply output. The circuit remains in this condition

+5 V

and

+12 V extended hold-off

transistors. Hold-off signals remain in this state and

until the overvoltage is removed (Q1S current goes to

inhibit switching regulator operation for the 135 ms

zero) and either the power supply switch transistor is

pulse duration. At the end of this time, the 135 ms

off due to short circuit protection, or the regulator’s dc

one-shot

fuse opens.

resets,

terminating

the

delayed

hold-off

signals, and triggers the 2.0 ms one-shot. Its active low
output resets the Current Limit flip-flop and clears the

*+ 5V

135 ms one-shot for 2.0 ms, allowing the regulator pass

switch transistors to operate for 2 ms (minimum). At

> +5V

cit,
+5y | ci2,
C12

the end of this time, the 135 ms one-shot is again

SWITCHING

enabled (the clear input goes high) and a new over-

REGULATOR

015

OUTPUT

current cycle is enabled. If the overload is removed,

normal operation resumes; otherwise, the overload

causes a new overload condition to occur and the cycle

RTN (GND)

repeats, as described above.

CP-1797

Switching regulator operation is suspended when the

Figure4-32

operator places the DC ON/OFF switch in the OFF

Crowbar Circuit

position. Logic signal generation circuits respond by
The +12 V crowbar circuit functions in a similar

immediately asserting BPOK H low to initiate a
processor power-fail sequence.

manner. However, the reference voltage for this power

After a 5—10 ms

supply is approximately 13.5V.

“pseudo delay,” POWER OFF L is asserted low. This
low signal is wire-ORed with OVERCURRENT L, inhibiting the switching regulator operation, and dc

4.9.3.6

power is removed from the backplane.

eration circuits produce LSI-11 bus signals for power

Logic Signal Generation — Logic signal gen-

normal/power fail

and

line

time

clock

interrupt

Crowbar Circuits — Crowbar circuits are

functions and processor Run-Enable/Halt mode. The

connected across both +5V and +12 V power supply

RUN indicator circuit monitors the SRUN L back-

4.9.3.5

outputs for overvoltage protection. An overvoltage

plane (nonbused) signal and provides an active display

condition could occur if +12 V and +S5 V outputs

when the processor is in the Run mode. BPOK H and

shorted together, or if a driver or switch transistor be-

BDCOK H indicate power status. When both are high,

comes shorted. When shorted to a higher voltage

power to the LSI-11 bus is normal and no power fail

source, the crowbar fires, shorting the supply voltage

condition is pending. However, if primary power goes

that it is protecting to ground (dc return). In this

abnormally low (or is removed) for more than 16.5 ms,

condition, the overload and short-circuit protection

BPOK H goes low and initiates a power-fail processor

circuits respond by limiting the duty cycle of the switch

interrupt. If the power-fail condition continues for

transistor until the overvoltage source is removed.

more than an additional 4 ms, a ‘““pseudo delay’’ circuit

However, when the overvoltage is caused by a shorted

causes BDCOK H to go low. The circuit also causes the
overload and short-circuit protection circuit to inhibit

driver or switch transistor, short-circuit protection is
ineffective, and the excessive current caused by the

+5V and +12 V control transistors; normal output
voltages are available for S0 us (minimum) after
BDCOK H goes low (depending on the loading of the

crowbar circuit firing will blow the regulator’s fuse (F1
for +SVorF2for +12V).

output

voltages).

The

ON/OFF

switch

simulates an AC ON/OFF operation by turning
switching regulators on or off without turning system
primary power off. A normal power-up/power-down
sequence is produced by this circuit. The line time

The crowbar circuit for the +5 V output is shown in
Figure 4-32. [t comprises a 5.6 V zener diode D9, diode
D8, programmable unijunction transistor Q9, and

silicon-controlled rectifier (SCR) Q15. R19, D8, and

clock circuit produces a processor interrupt at the

D9 supply the 6.1 Vdc (approx) crowbar reference

power line frequency (either SO or 60 Hz). The circuit
simply asserts the BEVNT L line at the line frequency.

(threshold) voltage to the gate of Q9 via R21. Q9 is
normally off and its cathode supplies a0 V gate input to

4-44

DC voltage monitor circuits respond to both +5V and

R25 and R3, as shown in Figure 4-33. Voltages are

+12 V power supply outputs. A +2.5 V reference at

sensed at the anodes of diodes D17 and D18. The

the voltage comparator’s noninverting input is established by +35 A and a voltage divider comprised of

cathode of D17 is connected directly to the +5 V
output. D18 is connected to a voltage divider
+5V

VOLTAGE

SENSEINPUTS

+12v

+5V

+{2V

+5A

Di6

’

6.8V

+5A
5

SR25

R49
2 67V

~_ COMPARATOR

VOLTAGE

+2.5V

(NORMAL)

|—=

)

J,////'

;‘;é

NORMAL 5.5V

BDCOK H

Q10

R3g

R35

"PART OF
| PANEL

D27
al
PART OF FRONT

—

POWER OFF L

| PANEL 0C ON

R0 RS2 ¢ oFF voLTAGE

PSEUDO

2.5V

COMPARATOR

TO OVERLOAD AND

e
U

OFF

PWR

—»

OFF/FAIL
H

SHORTCIRCUIT

€

PROTECTION CKTS

D26

ACV

R9g

R48

| gR12
,
L

R38

+2.5V
YW—]
—
AcLow =S 28

ACLOH

ko4
023
W
\
1
3R84

Q11

iu,—]

R36

t2.ov i,

BPOK H

D10

R63

R46

POWER OK

DETECTOR

CSPARE 2

SRS

)

R24

QNESHOT

COMPARATOR

+5V

+5A

16.5

R8¢

+5A

R32¢

CiDF

+oA

+5A

BEVNT L

LINE TIME CLOCK

r-PART OF FRONT PANEL

*SA :

RUN H

|
SRUN

RUN

200

__J,

LTC

|
=

|
OFF

|
|

ONE
ONE

¥\

CSPARE 2

ENABLE

CHALT H

Figure4-33

Logic Signal Generation

4-45

+5A

BHALT L
R2e

CP-1798

comprising 6.8 V zener diode D16 and R47. The sensed

active (dc voltage normal) state. Rectifiers D2 and D3

voltage is always 6.8 V less than the +12 V power

produce positive-going dc voltage pulses at twice the ac

supply

line frequency. R32, R12, and C1 produce nominal

output

voltage

(but

not

less

than

V).

Normally, the junction of D17, D18, R57, and R49 is

+3.9 V (peak) normal line voltage pulses which are

clamped to +5.5 V (nominal) via D17, which is con-

coupled to the noninverting input of the

nected to the +5 V output. Voltage divider R49 and

comparator via R48. R8 and R9Y produce a +2.5V

ac low

RS0 provide a portion of the sensed voltage to the

reference for the comparator’s inverting input. The

comparator’s inverting input. This voltage is normally

comparator’s normal output is

2.7V, causing the comparator’s output to go low. The

occurring at twice the ac power line frequency. Each

low signal forward biases DC ON panel indicator driver

positive-going leading edge retriggers the 16.5 ms

transistor Q10, producing a DC ON indication, and

one-shot, keeping it in the set state. The 16.5 ms

a series of pulses

reverse biases the BDCOK H FET bus driver Q6. As a

one-shot output is diode-ORed with DCOK L via

result, Q6 cuts off, and its source voltage risesto +5 V,

diodes D25 and D23 and PWR OFF/FAIL H via D24.

producing the active BDCOK H signal.

Normally, the three signals are low and Q11 remains
cut off. In this condition, C4 charges to +3.125 V via

A low +35 V output results in a decrease in voltage at

R36 and R38. This signal is then applied to the power

the voltage comparator’s inverting input. A voltage less

OK comparator’s inverting input via R24. Since the

then 4.6 V reduces the voltage at the comparator’s in-

noninverting input is referenced to +2.5 V by voltage

verting input to less than the +2.5 V reference. Hence,

divider RS and R6, the comparator’s output goes low,

the comparator’s output goes high, turning off the DC

biasing off FET QS. QS’s source voltage then rises

ON indicator and allowing Q6 to conduct. Q6 asserts

toward +9S V via R46 producing the active BPOK H

the BDCOK H bus signal low, indicating that a dc

signal.

power-fail condition exists.

shown in Figure 4-34.

Power-up/power-down

sequence

timing

The low +12 V operation is similar to that described

A power failure is first detected when the pulsating dc

for low +35 V operation. An output voltage less than

voltage at the ac low comparator’s noninverting input

11.3 V results in BDCOK H being asserted

low

is less than +2.5 V (peak). The comparator’s output
then remains low, allowing the 16.5 ms one-shot to go

(power-fail condition).

out of the retrigger mode. The one-shot resets 16.5 ms
AC

voltage

monitor

circuits

include

low

after the leading edge of the last valid ac voltage alter-

comparator, 16.5 ms delay, and a BPOK H bus driver

nation; the 16.5 ms delay is equivalent to a full line

circuit which is enabled only when BDCOK H is in the

cycle

(two-alternation)

failure.

The high

one-shot

INPUT

—-OI O0O-1Oms

|je—

BPOK H

e—

70ms (MIN)—

—>

5-10ms

|e—

POWER OFF L

(PSEUDO DELAY)

—»

l&—0-1ms

BDOCOK H

—

|4— 10us -20ms

DC OUTPUT
VOLTAGES

CcP-1823

Figure4-34

Power-Up/Power-Down Sequence

(false) DC ON H signal is produced. This signal is

output is then coupled via D23 to the base of Q11, for-

ORed with AC LO L, causing a power-fail sequence to
occur as previously described. BPOK H is immediately
asserted low. After the 5—10 ms pseudo delay, dc
switching regulator operation is inhibited and dc power

ward biasing it. Q11 conducts and rapidly discharges

C4; R36 limits peak discharge current. The low voltage

thus produced is less than the +2.5 V reference at the
power OK comparator’s input, and its output goes

is removed from the backplane. When the DC
ON/OFF switch is returned to the ON position, PWR
OFF/FAIL H goes low, rapidly discharging C13.
POWER OFF L then goes high and switching
regulator operation resumes. Approximately 100 ms

high. QS5 then conducts and asserts the BPOK H signal
low (power fail). The AC LO L signal produced by the
16.5 ms one-shot is ORed with the DC ON H signal,
producing a high POWER OFF/FAIL H signal. This
signal reverse biases D26, allowing C13 tochargetoS V

later, BPOK H goes high and normal processor

via R40. After a 5—10 ms (approximately) ‘“‘pseudo
delay,” C13’s voltage rises above the dc off voltage

operation is enabled. DC ON/OFF circuit timing is

comparator’s +2.5 V reference (noninverting) input.

shown in Figure 4-33.

The comparator’s output goes low, asserting POWER

OFF L low and turning off the switching regulators

BEVNT L is the bused interrupt requet line which is
normally used for line time clock interrupts. Q4 is
forward-biased during positive alternations of the ac
line and produces low-active BEVNT L signals. D1
clips negative alternations and limits Q4’s reverse base

(Paragraph4.9.3.4).
When normal power is restored, the 16.5 ms one-shot

returns to the retrigger (set) mode. AC LO L goes high
(false) and PWR OFF/FAIL H goes low, discharging

to emitter voltage. The LTC ON/OFF switch must
be in the ON position for BEVNT L signal generation. When the LTC function is not desired, the
LTC switch is set to the OFF position; CSPARE?2
goes low, Q4 remains cut-off, and BEVNT L remains

C13. The dc off voltage comparator’s inverting input
immediately

goes

low

and

its

output

goes

high,

enabling switching regulator operation. The low AC
LO H one-shot output removes forward bias from the

base of Q11, cutting it off. Its collector voltage then
rises as C4 charges at a relatively slow rate. R38

passive (high).

controls the charging rate of C4 and ensures that ac
voltage

and

output

voltages

are

normal

for

The DC ON/OFF switch simulates a poweri failure

The RUN indicator is illuminated whenever the processor is executing programs. SRUN L, a non-bused
backplane signal, is a series of pulses which occur at
3—Sus intervals whenever the processor is in the Run

inverters provide switch debounce protection and a low

SRUN L pulse leading edge, keeping it in the retrigger

approximately 100 ms (70 ms minimum) before BPOK
H goes high.

mode. The pulses trigger a 200 ms one-shot on each

when it is placed in the OFF position. Cross-coupled

ON/OFF

SWITCH OFF

—»{

5-10ms

je—

BPOK H

—

70ms(MIN)

—»

POWER OFF L

(PSEUDO DELAY)

-'-—I

Oo-1 ms—# l‘—

| -3 ms
—

BDCOK H

10us-20ms
—»

DC OUTPUTS

[e—

—»

«—3-10ms

/
CcP-1824

Figure 4-35

DC ON/OFF

4-47

Circuit Timing

mode. Its high RUN H output signal is then inverted,
producing a 0 V signal that turns on the RUN
indicator. When the processor is in the Halt mode,
SRUN L pulses cease and the 200 ms one-shot resets

4.9.4 H780 Connections
H780 connections are shown in Figure 4-36. The
H9270 backplane connections and interconnecting
cables are also shown. Note that cable connectors are

after the 200 ms delay. The RUN indicator turns off,

wired 1:1. Both connectors on the H780/H9270 signal

indicating the Halt mode.

cable are 10-pin connectors which are wired in exactly
the same manner, as listed in Figure 4-36. Similarly,

The HALT/ENABLE switch allows the operator to

both ends of the panel signal/power cable are wired to

manually assert the BHALT L signal low, causing the

16-pinconnectors in thesame pin/signalconfiguration.

processor to execute console ODT microcode. When in
the ENABLE position, BHALT L is not asserted, and
the Run mode is enabled. Cross-coupled inverters
provide a switch debounce function.

FRONT PANEL
/P.C. BOARD

12-PIN
CONNECTOR

P.C.

AC POWER

CAB{A

PWR XFMR

10-PIN

16 -PIN SOCKET

H780 POWER SUPPLY

—

BOARD

16-PIN

CONNECTOR

/SOCKET

PANEL

SIGNAL/POWER

CABLE (11in.)

SIGNAL

“—PIN

SIGNAL

BPOK H

{

+5A

(KEY)

CSPARE2

DC POWER CABLE (12in.)

2
3

SIGNAL CABLE (10 in.)

CL3 L

BEVNT L

5
6
7
8

css L

BEVNTL
SRUN L

2
2

GROUND
CL3 L
CS3 L
CSPARE

5
6
7
8

BHALT L

DCOKH

WD | +12v Z:gu (o ove

10
11

GROUND
CL3
CS3
CSPARE!

13
14
{5
16

CSPARE 3
CSPARE 4

12 CSPARE 5
GROUND
CDCOK H
CSPARE 6
H
CBHALT

10-PIN CONNECTOR ON FRONT (SIDE 1) OF
[H927o P.C. BOARD

(H927O BACKZL[;\é\IEZ)REAR VIEW

DCOK H

V@_ +5Y

CDCONH
SRUNL

P.C. BOARD

BPOKH

LD
L@ | GND

@
TERMINAL BLOCK

CP-1825

Figure4-36

H780 Connections

4-48

CHAPTER)S

USING KD11-F and KD11-JPROCESSORS

5.1

Table 5-2

GENERAL

KD11 Factory Jumper Configuration

Before installing and using the KD11-F or KD11-]J
processor in the LSI-11 or PDP-11/03 system, the user
must

select

certain

processor

features

Jumper | Installed |Removed

(jumper-

Function

selected), determine where the processor and option
modules should be installed on the backplane, be

aware of trap and interrupt functions, and ensure the

conditions for bus initialization. These items are dis-

cussed in detail in the following paragraphs.

5.2

JUMPER-SELECTED FEATURES

5.2.1

W3S

Wire-wrap posts are provided on the LSI-11 micro-

Line Time Clock
Enable

X
X
Memory Refresh
(KD11-J) {(KD11-F)[Enable (KD11-F only)

General

BANK 1 Disabled

X
X
BANK 0 Enabled
(KD11-F)| (KD11-J)|(KD11-F only)

Power-Up

computer module to allow the user to select various

A{L

features, aslisted in Table 5-1. These features include:

} Mode0
J}g

memory refresh enable/disable, line time clock (LTC,
or external event interrupt) enable/disable, power-up

mode selection, and resident memory bank selection
(KD11-F only).

Jumpers are located as shown in Figure

S-1. Jumpers are factory-installed as listed in Table 5-2
and can be altered by the user

for

particular

application, as described in the following paragraphs.
w5 |

Table §5-1

Summary of KD11 Jumpers
W1 W2|W3|W4|W5|W6

Function

X|X|X

|R|X

X | X |R

|X | X | X |Line Time Clock Enable

X|X|X

|X|R|R

|X|[X]|I

|Power-Uptospecial

M7264

R|{X

W1 through W6 are wire-wrap jumpers
Figure 5-1

5.2.2

[|X | X | X | Resident MemoryBank 1

Memory Refresh

controlling

the

refreshing

all

dynamic

MOS

memories in a system when jumper W4 is removed.
Memory refresh is always required when dynamic

X = Don’tCare
=

Jumper Locations

The LSI-11 processor has the capability of completely

|X |Resident MemoryBankO

NOTE
I

REV.C,D
CP-1799

microcode
|X

ETCH

NOTE

|Power-UptoODT

w1 |

w4 |

|Power-Upto24
|Power-Upto173000

RI|TI

w2 |

|X | MemoryRefresh

X|X|X|X|R|I

|X|[X]|I

we |

w3 |

MOS memory devices are used in the LSI-11 system,

Installed

R = Removed
S-1

such

the

KD11-F or KD11-J processor (M7264) module. Note

MSV11-B 4K by 16-bit read/write memory module.

the

KDI11-F

resident

memory

and

that the jumpers affect only the power-up mode (after

The refresh operation can be controlled by a device

BDCOK H and BPOK have been asserted); they do not

other than the LSI-11 processor, if available, such as a

affect the power-down sequence.

DMA refresh device. If such a device is used, or if no
dynamic MOS memory devices are present in the

The state of the BHALT L signal is significant during

system (KD11-J), install W4. The refresh sequence is

the power-up sequence. When this signal is asserted, it

described below.

causes the processor’s ODT console microcode

subset of an Octal Debugging Technique program) to
The processor’s memory refresh sequence is controlled

become invoked after the power-up sequence. The

by resident microcode inthe processor which is initiated

console device must be properly installed for correct

by an interrupt that occurs once ever 1.6 ms. It is the

use of the BHALT L signal.

highest priority processor interrupt. Once the sequence
is initiated, the processor will execute 64 BSYNC

The power-up modes are listed in Table S-3. Detailed

L/BDIN L bus transactions while asserting BREF L.

descriptions of each mode are provided in the para-

The BREF L signal overrides memory bank address

graphs which follow.

bits 13—15 and allows all memory units to be simultaneously

enabled.

After

each

bus

Table 5-3

transaction,

Power-Up Modes

BDAL1—6 L is incremented by 1 until all 64 rows have
been refreshed by the BSYNC L/BDIN L transaction.
This process takes approximately 130
us during which

external interrupts (BIRQ L and BEVNT L) are ignored.

However,

DMA

requests

can

Mode

Jumpers
W6 lWs

Mode Selected

R | R

|PCat24and PSat26, orHalt mode

R | I

|ODT Microcode

|PCat 173000 for user bootstrap

| I

|Special processor microcode

granted

between each of the 64 refresh transactions.

5.2.3

Line Time Clock

LTC (or external event) interrupts are enabled when

(not implemented)

jumper W3 is removed and the processor is running.

The jumper can be inserted to disable this feature. The
LTC interrupt is initiated by an external device when it

NOTE

asserts the BEVNT L signal. This is the highest priority

R = Jumper Removed

external interrupt request; processor interrupts have

= Jumper Installed

higher priorities. If external interrupts are enabled (PS
bit 7 = 0), the processor PC (R7) and PS word are

Power-Up Mode 0

pushed onto the processor’s stack.

(or

This option places the processor in a microcode se-

The LTC

external event device) service routine is entered by

quence that fetches the contents of memory locations

vector address 100 ; the usual interrupt vector address

24 and 26 and loads their contents into R7 and the PS,

input operation by the processor is not required since

respectively.

vector 100

point interrogates the state of the BHALT L signal;

is generated by the processor.

A microcode service translation at this

depending on the state of this signal, the processor

The first instruction of the service routine will typically

either enters ODT microcode (BHALT L asserted low)

be fetched within 16 us from the time BEVNT L is

or begins program execution with the current contents

asserted; however, if optional EIS/FIS instructions are

of R7 as the starting address (BHALT L not asserted).

being executed, this time could extend to 50.45us. This
trap

Note that the T-bit (PS bit 4) 1s loaded with the contents

execution (memory refresh, T-bit, power fail, etc.), or

of PS bit 4 in location 26. This mode should be used

time

could

also

extended

processor

by asserting the BHALT L signal.

only with nonvolatile memory locations 24 and 26 or
with BHALT L asserted. This power-up sequence is

5.2.4

Power-Up Mode Selection

shown in Figure S-2.

Since the LSI-11 can be used in a variety of system

applications that have either (or both) volatile (semi-

Power-Up Mode 1

conductor read/write) or nonvolatile (PROM or core)

This mode immediately places the processor in the

memory, one of four power-up mode features are

console microcode regardless of the state of the

available for user selection. These are selected (or

BHALT L signal. This mode assumes a console inter-

changed) by wire-wrap jumpers WS and W6 on the

face device at bus address 177560.

GET

PC FROM 24

MODE 0
SELECTED

POWER UP

BHALTL

YES

EXECUTE

ASSERTED

PS FROM 26

CONSOLE
ODT nCODE

BEGIN PROGRAM

USE ANOTHER

EXECUTION

POWER UP
MODE

11-3156

Figure S-2

Mode O Power-Up Sequence

Power-Up Mode 2

set up a valid stack pointer (R6). This option should be

This mode places the processor in a microcode se-

used with nonvolatile memory (ROM, PROM, or core)

quence that loads a starting address of 173000 into R7

at address 173000. A time-out trap through location 4

and begins program execution at this location if the

will occur if no device exists at location 173000.

BHALT L signal is not asserted.

If BHALT L is asserted, the processor will not execute
Note that before 173000 is loaded into R7, PS bit 4

the instruction at location 173000 and will immediately

(T-bit) is cleared and bit 7 (interrupt disable) is set.

execute the console microcode. This power-up mode

The user’s program must set these bits, as desired, and

sequence is shown in Figure S-3.

EXECUTE

POWER UP

YES

MODE 2

PC — 173000

BHALT L

PS (BIT 4) <~ 0O

SELECTED

ASSERTED

PS (BIT 7) < 1

FIRST

CONTINUE

INSTRUCTION

PROGRAM

AT
152000

EXECUTION

EXECUTE

USE ANOTHER

CONSOLE

POWER UP OPTION

ODT uCODE

11-31567

Figure 5-3

Mode 2 Power-Up Sequence

5.2.5

Power-Up Mode 3
This

microcode

sequence

expansion

allows
the

access

fourth

to future

microm

Resident Memory 4K Address Selection

Jumpers W1 and W2 are used for selecting the 4K

page

(bank) address for the KD11-F resident memory. Only

(microlocations 3000 to 3777). After BDCOK H and

one jumper must be installed, as follows.

BPWROK H are asserted and the internal flags are

cleared, a micro jump is made to microlocation 3002. If

this option is selected and no microm responds to the

W1 installed = Bank 1 (addresses 20000—37776)

fourth page microaddress,

W2 installed = Bank 0 (address 0—17776)

a microtrap will occur

through microlocation O which will, in turn, cause a reserved user instruction trap through location 10.

NOTE

Note that the state of BHALT L is not checked before

If
no jumper is installed, the 4K resident memory

control is transferred to the fourth microm page.

will not respond to any address.

S-3

5.3

INSTALLATION

manner and arbitrate DMA requests; all external in-

terrupts are ignored.

Prior to installation, the processor module jumpers

must be configured as directed in Paragraph 5.2.
The Halt mode can be entered in one of four ways:

PDP-11/03 systems are shipped from the factory with

the KD11-F or KD11-J processor installed. Refer to

When the BHALT L signal is asserted.

Chapter 11 for LSI-11 processor module installation
2.

details.

When

HALT

instruction

has

been

executed.

5.4

USINGTHELSI-11 MICROCOMPUTER

5.4.1

By power-up sequence.
When a double bus error has occurred [a bus

General

error trap with SP (R6) pointing to non-

Most of the operational characteristics are discussed in

existent memory].

the LSI-11, PDP-11/03 Processor Handbook and related software publications. This discussion includes

The LSI-11 microcomputer does not use conventional

the use of the LTC (external event interrupt) feature,

control panel lights and switches. Instead, the ODT

bus initialization, and trap and interrupt priority.
5.4.2

console microcode routine provides all control panel
features on a peripheral device which can be interfaced

Interrupt and Trap Priority

Interrupts

and

traps

are

quite

similar

at bus address 177560 and interpret ASCII characters.

their

In a typical configuration there is no bus device that

operation. Interrupts are service requests from devices

responds

external to the processor; traps are interrupts which

are

generated

within

the

processor.

Their

address

177570

(the

PDP-11

SWR

address). The peripheral device used with the ODT

main

console microcode is called the console device, which

operational difference, however, is that external in-

can

terrupts can only be recognized when PS priority (bit 7)

be any device capable of interpreting ASCII

characters.

is zero; traps can be executed at any time, regardless of

The

prompt

character

sequence

and

detailed use of console ODT commands are contained

the PS priority bit status.

inthe LSI-11, PDP-11/03 ProcessorHandbook.

The highest priority trap is memory refresh, when

5.5

enabled (Paragraph 5.2.2). Memory refresh does not

Initialization occurs during a power-up or power-fail

require an interrupt vector since it is entirely controlled

sequence, or when a RESET instruction is executed.

INITIALIZATION AND POWER FAIL

by processor microcode; memory refresh operations

The processor responds to these conditions by asserting

are completely transparent to the user programs and

the BINIT L bus signal. BINIT L can be used to clear or

PS bits are not altered in any way. The remaining

initialize all device registers on the bus. In addition, the

traps, including EMT, BPT, IOT, and TRAP instruc-

DRV11 parallel line unit applies the buffered initialize

tions, and hardware-generated Trace Trap, Bus Error,

signal to pins on both of its device interface connectors

Power Fail, etc. are described in the LSI-11, PDP-11/

for initializing the user’s device.

03 Processor Handbook. The LTC (external event) in-

terrupt has the highest priority of all external in-

During the power-up sequence, the processor asserts

terrupts, when enabled (Paragraph 5.2.3). It is ack-

BINIT

nowledged (serviced) only when PS priority bit 7 = 0.

supply-generated BDCOK H signal. When BDCOK H

This interrupt always uses vector address 100 . It loads

goes active (high), the processor terminates BINIT L

the

response

jumper-selected

passive

power

a new PC from location 100 and a new PS from location

and

102. All other external interrupts are requested by a

executed.

device asserting the BIRQ Lsignal. If PS bit 7 = 0, the

supply-generated BPOK H signal goes passive (low)

Similarly,

power-up

(low)

power

fails,

sequence

the

power

request is acknowledged and the processor inputs a

and causes the processor to push the PC and PS onto

user-assigned vector address for the device’s service

the stack and enter a power-fail routine via vector

routine PC (starting address) and PS. For example,

location

when the requesting device is the console device,

power-fail routine until either BDCOK H goes passive

24.

The

processor

will

execute

user

vectors 60 (console input) or 64 (console output) are

(low), indicating that dc operating power may not

used. These vectors are reserved for the console device

sustain processor operation, or BPOK H returns to the

by most DIGITAL software systems.

active state. BINIT L will go active if BDCOK H goes
passive.

5.4.3

HaltMode

Note that if a HALT instruction is executed after

The LSI-11 microcomputer can operate in either a Run

entering the power-fail routine, the ODT microcode

or Halt mode. When in the Halt mode, normal pro-

will not be executed until BPOK H is reasserted. If

gram execution is not performed and the processor
executes

ODT

console

microcode.

However,

BPOK H goes passive while the processor is in the Halt

the

mode, the power-fail routine will not be executed.

processor will execute memory refresh in a normal
5-4

CHAPTER®G

LSI-11 INTERFACE MODULES

6.1

The remainder of this chapter described DLV 11 and

GENERAL

Two LSI-11 interface modules provide a simple means
for interfacing peripheral devices to the LSI-11 bus.
The DLV11 is an asynchronous serial line interface
that is capable of transmitting and receiving 20 mA
current loop or EIA serial data, ranging in rate from S0

DRYV11 functions, jumpers, installation, interfacing to
peripherals, and programming.

6.2

DLVI11SERIAL LINE UNIT

to 9600 baud. Two optional cable types are available
for connecting 20 mA or EIA devices to the DLV11.
The DRV11 is a general-purpose parallel line interface. It is capable of storing and transmitting either

6.2.1

two 8-bit bytes or one 16-bit word, and receiving 8-bit

6.2.2

bytes or 16-bit words.

Module Operations

VAN
BDALO- 5L

UNIVERSAL
ASYNCHRONOUS
RCVR./XMTR.

General

The DLV11 Serial Line Unit interfaces serial 1/0
devices to the LSI-11 bus, as shown in Figure 6-1.
Jumper-Selected

SERIAL DATA

SSQTL?_ h

BSYNC L

LOGIC

INTERFACE
CIRCUITS

ADDRESSING,
INTERRUPT

READER

ELATOTTL)

BWTBT L

BDIN L

CONTROL LOGIC

LOGIC

ANDI/O = |le—

(RCSR, XCSR)

INTERFACE

(20mA OR

RUN

and

OPTIONAL

DATA

BREAK

Vectors,

(RBUF , XBUF)

Addressing,

—

CABLE
TO /FROM
DEVICE

BCOSM (20mA)

S605C (ETA)

BOOUT L
BRPLY L
BINIT L

BIRQ

BIAKO L

BIAKI L
CP-1800

Figure6-1

6.2.2.1

DLV11 Serial Line Unit

Locations— Thirty jumper locations are pro-

6.2.2.2

Addressing

—

Jumpers

involved

with

vided on the DLV11 module, as shown in Figure 6-2.

addressing include A3 through A12. Only address bits

Jumpers are installed at the factory for use as the

03 through 12 are programmed by the jumpers for

console device (Paragraph 6.2.7) and can be altered by

correct

the user for his particular system application,

DLV11 addressing, producing the 16-bit
address word shown in Figure 6-3. The appropriate

jumpers are removed to produce logical 1 bits; jumpers

described in the following paragraph:s.

installed will produce logical O bits.

6-1

O~M

xxrocax

TP2

TRTRTHTS

O---4&---0

INSERT .005uF CAPACITOR WHEN
THE SERIAL LINE DEVICE IS A

OOOTN

dqqa

qIqZag

FEH

TELETYPEWRITER (LT33 OR LT35)

CP-1801

Figure6-2

BDAL
BITS

15
1

——

DLV11Jumper Locations

8
1

[

]

=1 (L)

1|
o

NN
¢

—~

”

0= CSR

OF
1= DATA BUFFER ( (PART
1= TRANSMITTER

ADDRESS JUMPERS:

INSTALLED
=0

REMOVED

RANGE
= 1600008 - 177776
5
CP-1802

Figure6-3

DLV11 Addresses

BDAL

BITS

|1
w

'L
>

L O = RECEIVER

I = TRANSMITTER

VECTOR JUMPERS:
INSTALLED=0

REMOVED

RANGE :0- 3744
cpP-1803

Figure6-4

6.2.2.3

DLV11 Interrupt Vectors

Vectors — Jumpers involved with vector ad-

Table 6-1

dressing include V3 through V7. Only vector bits 03

Baud Rate Selection

through 07 are programmed by the jumpers for correct

DLV11

vector

addressing,

producing

the

16-bit

Baud Rate

FR3

| FR2

| FR1 | FRO

address shown in Figure 6-4. The appropriate jumpers

are removed to produce logical 1 bits; jumpers installed

will produce logical O bits.

110

134.5

programmed via jumpers NP, 2SB, NB1, NB2, and

150

PEV as shown below.

200

300

Number of Data Bits

600

6.2.2.4

UAR/T Operation — UAR/T operation is

NB1

NB2

1200

Installed

;388

II{

}Iz

II{

Removed

Installed

2400

Installed

Removed

4800

Removed

9600

E?;e;;allng)

Number of Stop Bits Transmitted
2SB installed = One stop bit

2SB removed = Two stop bits
.

NOTE

)

Parity Transmitted

installed

R = removed

X = don’t care

NP removed = No parity bit

NP and PEV installed = Odd parity

loop interface operation. Remove EIA and remove or

NP installed and PEV removed = Even parity
6.2.2.5

install jumpers as desired for the functions listed

below:

Baud Rate Selection — Baud rate is pro-

grammed via jumpers FRO through FR3 as shown in

Active Current Loop (Jumpers configuration as shown

Table 6-1.

in Figure 6-5.)

6.2.2.6

EIA Interface — EIA drivers are enabled

when jumper EIA is installed. This jumper applies -12

Transmit

CL3 and CLA4 installed

Receive

CL1 and CL2 installed

V to the EIA driver chip. It should be removed during

20 mA current loop operation.

Passive Current Loop (Jumpers configured as shown in
Figure 6-6.)

6.2.2.7

20 mA Current Loop Interface — Jumpers

Transmit = CL3 and CL4 removed

CL1 through CLA4 are associated with 20 mA current

Receive

6-3

= = CL1 and CL2removed

DLV 11 SERIAL LINE UNIT CIRCUITS

B CO5M

CABLE ASSEMBLY

_AL

[

SO H —» COUPLER
cL3

CONSTANT CURRENT
D!ODE

MODE ENABLE \

+12V — A NW————O0—0READER

RUN

LOG IC

READER RUN

CL1

+12v—-fvv\,———</>'—ofi

e
=
e

IjKK\ |

1
\

|
|

l
|

— 2 <—|—SER|AL ouT-

|
|

l
|

|
|

|
{ PP (—-

L
_

D |

|{K< |

—

ACTIVE RECEIVE

—————< UU&———

MODE ENABLE

CURRENT LOOP

I
I

| ,

: <A\A<il

cL4

[20mADATA OUT

I
I

TTL SERIAL DATA IN| — E

opTicaL

ACTIVE TRANSmiT

{

MODE ENABLE

CURRENT LOOP

| 20mA/TTL RCVD DATA |

CURRENT LOOP

" ACTIVE RECEIVE

COUPLER

—_—
e

<3 (——l——SERIAL IN—

OPTICAL

20 mA DEVICE
_A

r—

—

DATA

20mA

CLz2

SERIAL

: < 5 ‘L:

SERIAL OUT+

| 6

ENABLE+

|fl

< |

|<7< |

READER

SERIAL IN+

|
A< |
———< W
CP-1804

Figure 6-S

Active 20 mA Current Loop Interface

The DLV 11 is supplied with jumpers CL1 through CLA4

determine the backplane slot in which the module will

wired for the active transmit,

active receive mode

be installed. Then, check that jumpers are removed or

(Figure 6-5). When in this mode, serial current limiting

installed as described for your application (Paragraph

to 23 mA is provided by resistors (one each for transmit

6.2.2). Connection to the peripheral device is via an

and receive functions) connected to the +12 V source.

optional data interface cable. Cables are listed below.

Note that when module power is removed, the 20 mA
transmit optical coupler closes the serial loop (active or

Application

Cable Type*

passive mode). When the DLV11 is used in the passive
20 mA mode (Figure 6-6), the serial device must pro-

EIA Interface

BCOSC-X Modem Cable

duce the 20 mA current. Current limiting must be

20 mA Current Loop

BCOSM-X Cable Assembly

provided for transmit and receive currents in the serial
6.2.4

device.

Interfacing with 20 mA Current Loop Devices

When interfacing with 20 mA current loop devices, the

Framing Error Halt — A framing error halt

BCOSM cable assembly provides the correct con-

allows entry to console microcode directly from the

nections to the 40-pin connector on the DLV11. The

console device by pressing the BREAK key, producing
a framing error. A framing error occurs when the
received character has no valid stop bit. This error

peripheral device end of the cable is terminated with a

6.2.2.8

Mate-N-Lok connector that is pin-compatible with the
following peripheral options:

condition is detected by the UAR/T. FEH is factoryinstalled, causing the assertion of BHALT L when the
framing error is detected. The processor then executes

LA36 DECwriter

console microcode.

LT35 Teletypewriter

6.2.3

Installation

Prior to installing the DLV11 on the backplane, first
establish the desired priority level (Chapter 3) to

LT33 Teletypewriter

*The -X in the cable number denotes length in feet, as follows: -1, -6,

-10, -20, -25. For example, a 10-ft EIA interface cable would be ordered as BCOSC-10.

DLV11

SERIAL LINE

UNIT CIRCUITS

(PASSIVE RECEIVE

AND TRANSMIT)

BCO5M CABLE ASSY

—A-

SERIAL

20mA

DEVICE

R}
{————— +5V

SERIAL

[

20mA

DATA

OPTICAL

r<s<T

CLz _ _o

COUPLER

K &

CL4o- -

AA &

20mA|/TTL ROVODATA |

SERIAL

DATA IN

ouT

-2V ——NW—————'VW|—<EE\LI

r'y
B

R-ADER

FONLOGICL

ReApER
RUN

| { pp

seriaLl

+
ouT

{7 <——I—<—SERIAL IN —

DATA OUT

[j/ 5 {——‘-<—SERIAL ouT
-

SERIAL

SO H 'l COUPLER [20ma DATA | (KK |
OF TICAL

OPTICAL

courler

< :D
<&

IN +

< 3 <7+

CL10 -\~

SLH <«

cL3

+5v

COUPLER |~ DATA IN

opTicaL

SERIAL

I - 4 él— READER ENABLE
-

|
~———< 6 {&——
READER ENABLE+

I——(uufi—

D
N
— V€
CP-1805

Figure 6-6

Passive 20 mA Loop Jumper Configuration

6.2.6

VTOSB Alphanumeric Terminal

Programming

VTS0 DECscope

RTO02 Alphanumeric Terminals

6.2.6.1

DFO1-A Acoustic Telephone Coupler

Addressing— Addresses for the DLV11 can

range from 160000

through 17777Xg. The least significant three bits (only bits 01 and 02 are used: bit 0 is

The complete interface circuit provided by the BCOSM

ignored) address the desired register in the DLV11, as

cable and the associated DLV11 jumpers is shown in

follows:

Figure 6-3S.

Address

NOTE

Addressed Register

When the DLV11 is used with teletypewriter devices, a 0.005 4F capacitor must be installed be-

IXXXX0

tween split lugs TP1 and TP2.

After configuring the module jumpers and installing

RCSR (Receiver control/status)

1XXXX2

RBUF (Receiver data buffer)

1XXXX4

XCSR (Transmit control/status)

1XXXX6

XBUF (Transmit data buffer)

the proper interface, the DLV11 can be installed in the
backplane.

6.2.5

Address bits 03 through 12 are jumper-selected as
directed in Paragraph 6.2.2.2.

Interfacing with EIA-Compatible Devices

When interfacing with EIA devices, the BCOSC modem

cable provides the correct connection to the 40-pin

Since each DLV11 module has four registers, each re-

connector on the DLV11. The peripheral device end of

quires four addresses. Addresses 177560—177566 are

the cable is terminated with a Cinch DB25P connector

reserved for the DLV11 used with the console peri-

that is pin-compatible with Bell 103, 113 modems.
Connector pinning and signal levels conform to EIA

pheral device. Additional DLV11 modules should be

assigned

Specification RS232C. The complete EIA interface
circuit is shown in Figure 6-7.

addresses

from

175610 through

176176,

allowing up to 30 additional DLV11 modules to be
addressed.

6-S

DLV 11

BCO5C MODEM CABLE

SERIAL LINE UNIT CIRCUITS
A

’,

J14opa J1

T
EIA DATA IN

-12V

TTL SERIAL DATA IN

+12V

SO H

I\J\

EIA

EIA TRANS DATA

l{oo{{

DATA TERMINAL READY

RECEIVED DATA

I{ F &

ENABLE JUMPER

TO CSR

SELECTION
AND
CATING

F/L

TRANSMITTED DATA

I
|

BB{II

CARRIER

T <:

CLEAR

|
| ¢ o
:

|
<L

PROTECTIVE GROUND

¢z

BUSY

TO SEND

DATA SET READY

fi( ¢ &
I

AK I

SIGNAL GROUND

! /oy &

88
|

+< 2 eI|—-> BA
8 &—

—< 5 €

: Y |

|
|

I
|

\;Xl

1 ¢ :

E_I : P

SIGNAL GROUND /\

<25 &

(5 (1:

AR T

: <2o<=—> cD

~ A

< 4 <= o

EIA TRANS DATA

+3V

1v<

MIN.

EIA INTERFACE

(CINCH
DB25P)
V4

REQUEST TO SEND

EIA/TTL RCVD DATA

ST <

CP-1806

Figure 6-7

6.2.6.2

EIA Interface

Interrupt Vectors — Two interrupt vectors

Address

RCSR

177560

RBUF

177562

are jumper-selected on each DLV11 as described in
Paragraph 6.2.2.3:

000XX0

Receiver interrupt vector

XCSR

177564

000XX4

Transmitter interrupt vector

XBUF

177566

Vectors can range from addresses O through 37X,.

Vector addresses must be assigned as follows:

Vectors 60 and 64 are reserved for the console peripheral device. Additional DLV11 modules should be

assigned

vectors

following

any

DRVI11

installed in the system starting at address 300.

6.2.6.3

Interrupt Vector

Address

Console Receiver

000060

Console Transmitter

000064

modules

Word Formats — The four word formats
6.3

associated with the DLV 11 are shown in Figure 6-8 and
are described in Table 6-2.

6.3.1

6.2.7

DRV11 PARALLEL LINE UNIT
General

The DRV11 Parallel Line Unit is a general-purpose

Console Device

The console device is a serial line device, such as the
LA36 DECwriter, that uses a DLV 11 Serial Line Unit.
The following device addresses must be used for the

device interface module that connects parallel I/0
devices to the LSI-11 bus, as shown in Figure 6-9.

6.3.2

console device:

6-6

Jumper-Selected Addressing and Vectors

Table 6-2
Word Formats

Word

Bit(s)

Function

RCSR

Dataset Status — Set when CARRIER or CLEAR TO SEND and

DATA SET READY signals are asserted by an EIA device. Readonly bit.
14—08 Not used. Read asO.

Receiver Done — Set when an entire character has been received
and is ready for input to the processor. This bit is automatically

cleared when RBUF is addressed or when the BDCOK H signal
goes false (low). A receiver interrupt is enabled by the DLV11
when this bit is set and receiver interrupt is enabled (bit 6 is also
set). Read-only bit.

Interrupt Enable — Set under program control when it is desired to

generate a receiver interrupt request when a character is ready for

input to the processor (bit 7 is set). Cleared under program control
or by the BINIT signal. Read/write bit.
05—01

Not used. Read as 0.
Reader Enable — Set by program control to advance the paper
tape reader on a teletypewriter device to input a new character.
Automatically cleared by the new character’s start bit. Write-only

bit.
RBUF

15—08 Not used. Read asO.
07—00 Contains five to eight data bits in a right-justified format. MSB is
the optional parity bit. Read-only bit.

XCSR

15—08 Not used. Read as 0.
07

Transmit Ready — Set when XBUF is empty and can accept

another character for transmission. It is also set during the powerup sequence by the BDCOK H signal. Automatically cleared when
XBUF is loaded. When transmitter interrupt is enabled (bit 6 also

set), an interrupt request 1s asserted by the DLV11 when this bit

is set. Read-only bit.
06

Interrupt Enable — Set under program control when it is desired to

generate a transmitter interrupt request when the DLV11 is ready
to accept a character for transmission. Reset under program control or by the BINIT signal. Read/write bit.
05—01

Not used. Read as 0.
Break — Set or reset under program control. When set, a con-

tinuous space level is transmitted. BINIT resets this bit. Read/
write bit.
XBUF

15—08 Not used.
07—00 Contains five to eight right-justified data bits. Loaded under program control for serial transmission to a device. Write only.

6-7

15
RCSR

[

DATASET
STATUS

RECEIVER
DONE

(READ ONLY)

|
READER
ENABLE

(READ ONLY)

(WRITE ONLY)

RECEIVER

INTERRUPT
ENABLE

(READ/WRITE)

RBUF

—

—_—

(NOT USED)

DATA AND

PARITY

(5-7 BIT DATA IS RIGHT JUSTIFIED. PARITY IS BIT 7.
NO PARITY

15
XCSR

BIT

IS PRESENT

WHEN

8-BIT DATA IS USED.)

]

TRANSMIT

BREAK

READY
(READ ONLY)

(READ/ WRITE)

TRANSMIT

INTERRUPT
ENABLE

(READ/WRITE)
15
XBUF

[

——

—_

(NOT USED)

DATA
CpP-1807

Figure 6-8

BDALO - 15L

DLV11 Word Formats

RDOUTBUF

OUT

0-15

J1 N

REQ A

BIRQ L

INT ENB A

BIAKTL

BDALO—15L

INTERRUPT

INT ENB B

LOGIC

DRCSR

CSRI
NEW DATA RDY

A INIT
TO /FROM

I
H

L USER

DEVICE
LOGIC

BDALG -15L

SDIN L=

BDOUTL
BRPLY L
BINITL

BDALO-15L

ADDRESS

REQ B

CONTROL

CSRO

‘
>

DATA TRANS

ORINBUF

IN 0-15
y

CpP-1808

Figure6-9

DRV 11 Parallel Line Unit

6-8

6.3.2.2

6.3.2.1 Locations — Jumpers for device address and
vector selection are provided on the DRV 11 asshownin
Figure 6-10. Jumpers are installed at the factory for
address 167770 (DRCSR) and vectors 300 (interrupt A)
and 304 (interrupt B). These can be cut or removed by
the user to program the module for his system application, as described in the following paragraphs.

Addressing

Jumpers

involved

with

addressing include A3 through A12. Only address bits
03 through 12 are programmed by jumpers for DRV11
addressing, producing the 16-bit address word shown

in Figure 6-11. The appropriate jumpers are removed
to produce logical 1 bits; jumpers installed will produce
logical O bits.

2
(—

V(_S/

[ ADDRESS JUMPERS |
| a3
a9 |

SLT
. 5te
OPTIONAL EXTERNAL

(SEE PARA.6.3.4.6)

L A8

fif;

Atz

M7941 ETCH REV. C

15
1

BBS7 L

CcCP-1809

DRV11Jumper Locations

CAPACITOR

Figure6-10

Vo]

|
‘

]

‘

’

,N_

<«

=¢

O=low byte

S¢

<IJ

ggGISTER

—

INSTALLED =0

Figure6-11

BYTE SELECT

X =

ADDRESS JUMPERS:
REMOVED

(0-7)

DRCSR

(1)01;(( * DROUTBUF

- DRINBUF
CP—1810

DRV11 Device Address

6-9

, 0

]

‘

VECTOR

]

L (DRCSR -15)

REQUEST
ING DEVICE

0:=REQ A

0
-

JUMPERS:

1t =REQB

INSTALLED=0
REMOVED

Figure6-12

6.3.2.3

= 1

DRV11 Vector Address

6.3.3

Vectors — Jumpers involved with vector ad-

Installation

dressing include V3 through V7. Only vector bits 03

Prior to installing the DRV11 on the backplane, first

through 07 are programmed by the jumpers for DRV11

establish the desired priority level (Chapter 3) for the

vector addressing, producing the 16-bit word shown in

backplane slot installation. Check that proper device

Figure 6-12. The appropriate jumpers are removed to

address and vector jumpers are installed, as directed in

produce logical 1 bits; jumpers installed will produce

Paragraph 6.3.2. The DRV11 can then be installed on

logical O bits.

the backplane. Connection to the user’s device is via
optional cables.

; 89 ’

, Vv b

pE®
vf

flNs

N y
-

po¥
-

e
%

g
P

off

”

”7

KN {
: |
/Q‘
e

|- ”fi N !o
o

i d~

”

NNRR

L }

H854

CONNECTOR

)
|

l‘A\
;

LOWE

RO W

pIN°

H856 CONNECTOR

11-3294

Figure 6-13

J1orJ2 Connector Pin Locations

6-10

6.3.4

Interfacing to the User’s Device

6.3.4.1

When using the BC11K-25 cable, connect the free end
of the cable using the wiring data contained in Table

General — Interfacing the DRV11 to the

6-4. Refer to the Hardware/Accessories Catalog for

user’s device is via the two board-mounted H854 40-pin

additional optional interface accessories.

male connectors. Pins are located as shown in Figure
6-13. Signal pin assignments for input interface J2

6.3.4.2

(connector No. 2) and output interface J1 (connector

face is the 16-bit buffer (DROUTBUF). It can be either

Output Data Interface — The output inter-

No. 1) are listed in Table 6-3. Optional cables and

loaded or read under program control. When loaded

connectors for use with the DRV11 include:

by a DATO or DATOB bus cycle, the NEW DATA
READY H 750 ns pulse is generated to inform the

BCOSR-X* — Maintenance cable, 40-conductor

user’s device of the data transfer. The trailing edge of

flat with H856 connectors on each end. Available

this positive-going pulse should be used to strobe the

in lengths of 1, 6, 10, 20, and 25 feet.

data into the user’s device in order to allow data to
settle on the interface cable. The system initialize sig-

BC11K-25 — Signal cable, 20 twisted pair with

nal (BINIT L) will clear DROUTBUF.

H856 connector on one end; remaining end is terminated by the user.

All output signals are TTL levels capable of driving

H&856 — Socket, 40-pin female, for user-fabri-

eight unit loads except for the following:

cated cables.

NEW DATA READY = 10 unit loads
DATA TRANSMITTED = 30 unit loads
INIT (Initialize)* = 10 unit loads per connector

*The -X in the cable number denotes length in feet, as follows: -1,

-6,

-10, -12, -20, -25. For example, a 10-ft maintenance cable would be

*Common signal on both connectors.

ordered as BCO8R-10.

Table 6-3
DRYV11 Input and Output Signal Pins

Inputs

Outputs

Signal

Connector]

Signal

Connector | Pin

INOO

OUTO00

INO1

OUTO01

INO2

H, E

ouTO02

INO3

OUTO03

INO4

OuUT04

INOS

OUTO0S

INO6

OuUTO06

J1
J1

N
R

INO7

OuTO07

INO8

OUTO8

INO9

OuUTO09

IN10

OUTI10

IN11

OUT11

IN12

OUT12

IN13

OUT13

IN14

OUT14

IN1S

OUT1S

REQ A

NEW DATA RDY*

\"AY

REQB

DATA TRANS*

CSRO

CSR1

INIT

RR, NN

*Pulse signals, approximately 300-ns wide. Width can be changed by user.

6-11

Table 6-4
BC11K Signal Cable Connections

Twisted Pair

Color

Black/white-orange | black

wh-org
Black/white-yellow | black

Black/white-grey

Black/white-red

Black/white-green

Brown/green

Brown/red

Black/white-blue

Black/orange

Black/white-violet

Black/red

Brown/yellow

Black/blue

Connected

To J1

To J2

A | OPEN

OPEN

| OPEN

OPEN

| OUTOO0

DATA TRANS.

wh-yel

D | OPEN

OPEN

black

| OPEN

INO2

wh-gry

| OPEN

OPEN

black

H | OPEN

INO2

wh-red

| GND

GND

| black

| OUTO1

CSRO

wh-grn

| OUTO4

GND

brown

M | GND

IN1S

green

IN13

brown

| OUTOS

IN14

red

| OUTO06

GND

| INIT

black

| GND

REQB

wh-blu

| OUTO7

GND

black

| OUTO03

IN12

orange

| GND

IN11

| black

W | OUTO8

IN10

wh-vio

| OUTO09

GND

black

| GND

INO9

red

| OUTI10

INO8

brown

AA | OUT11

GND

yellow

BB | OUTI12

INO3

black

CC | GND

INO7

blue

DD | CSR1

GND

brown
orange

EE | GND
FF | OUTI13

OPEN

Brown/blue

brown
blue

HH | OUT14
JJ | OUTI1S

INOS
GND

Black/yellow

black
yellow

KK | GND
LL | REQA

INO4
INO1

brown
violet

MM | GND
NN | OUTO2

GND
INIT

Black/violet

black
violet

PP | GND
RR | OUTO02

GND
INIT

Black/green

black
green

SS | GND
TT | OPEN

GND
INOO

pink

UU | GND

GND

wh-red

VV |

Brown/orange

Brown/violet

Pink/white-red

INO6

NEWDATARDY | OPEN

6-12

Input Data Interface — The input interface

DATA READY and DATA TRANSMITTED pulse

is the 16-bit DRINBUF read-only register, comprising
gated bus drivers that transfer data from the user’s de-

widths. The module without external capacitance (as

vice onto the LSI-11 bus under program control.
DRINBUEF is not capable of storing data; hence, the

can be added in the location shown in Figure 6-10 to

6.3.4.3

shipped) will produce 750 ns pulses. The capacitor
produce the approximate pulse widths listed below.

user must keep input data on the IN lines until read by
the LSI-11 microprocessor. When read, the DRV11

Optional External

Approximate

generates a positive-going 750 ns DATA TRANS-

Capacitance (uF)

Pulse Width (ns)

MITTED H pulse which informs the user’s device
that the data has been accepted. The trailing edge of
the pulse indicates that the input transfer has been
completed.

All input signals are one standard TTL unit load; in-

None

750

0.0047

1150

0.01

1750

0.02

2650

0.03

3850

puts are protected by diode clamps to ground and +35

6.3.4.7

the optional BCO8R maintenance cable, the connec-

BCO8R Maintenance Cable — When using

tions listed in Table 6-S are provided. Cable connectors

Request Flags — Two signal lines (REQ A H

P1 and P2 are connected to DRV11 connectors J1 and

and REQ B H) can be asserted by the user’s device as

J2, respectively. Note that CSRO (J2-K), which can be

flags inthe DRCSR word. REQ B is available via Con-

set or reset under program control, is routed to the

6.3.4.4

nector No. 2, and it can be read in DRCSR bit 15. REQ

REQ A input (J1-LL); similarly, CSR1

A is available via Connector No. 1, and it can be read in

routed to REQ B (J2-S). Hence, a maintenance pro-

(J1-DD) is

DRCSR bit 7. Two DRCSR interrupt enable bits, INT

gram can output data to DROUTBUF and read the

ENB A (bit 6) and INT ENB B (bit 5), allow automatic

same data via the cable and DRINBUF. DRCSR bits 0

their

(CSRO) and 1 (CSR1) can be used to simulate REQ A

respective REQ A or REQ B signals are asserted. In-

and REQ B signals, respectively. If the appropriate

generation

interrupt

request

when

terrupt enable bits can be set or reset under program

INT ENB bit (DRCSR bits S or 6) is set, the simulated

control.

signal will generate an interrupt request.

In a typical application, REQ A and REQ B are

6.3.5

Programming

generated by Request flip-flops in the user’s device.
The user’s Request flip-flop should be set when ser-

6.3.5.1

vicing is required and cleared by NEW DATA READY

range from 160000

or DATA TRANSMITTED when the appropriate data

nificant three bits address the desired DRV11 register

transaction has been completed.

as follows:

6.3.4.5

Initialization
— The BINIT L processor-gen-

Addressing — Address for the DRV11 can
through 17777Xg. The least sig-

Address

Device Register

1XXXXO0

DRCSR

1XXXX?2

DROUTBUF

1XXXX4

DRINBUF

erated initialize signal is applied to DRV
11 circuits for

interface logic initialization. It is also available to the
user’s circuits via connectors J1 and J2 as follows:
Connector/Pin

Signal

J1/P

AINITH

device and should not be used for DRV11 addressing.

J2/RR

BINITH

The following address assignments are normally used:

J2/NN

BINITH

Addresses 177560—177566 are reserved for the console

First DRVI1I1

An active BINIT L signal will clear: DROUTBUF

DRCSR = 167770

data; CRCSR bits 6, 5, 1, 0; bits 16 and 7 (when the

DROUTBUF = 167772

maintenance cable is connected); and Interrupt Re-

DRINBUF = 167774

quest and Interrupt Acknowledge flip-flops.
Second DRVII

6.3.4.6

NEW DATA READY and DATA TRANS-

167760to 167764

MITTED Pulse Width Modification — An optional

capacitor can be added by the user to the DRV11

Third DRVI1I

module to extend the pulse width of both the NEW

1677350t0 167754

6-13

Table 6-5 (Continued)

Table 6-5

BCO8R Maintenance Cable Signal Connections
J2

BCO8R Maintenance Cable Signal Connections

| Name

Name

VV 1 OPEN

OPEN

IN14

OUT14

UU | GND

OPEN

IN15

OUT1S

TT | INOO

OUTO00

GND

| GND

OPEN

CSRO

GND
REQ A

KK
LL

RR | INITH

OPEN

GND

OPEN

INO2

OuUTO02

NN | INITH

OPEN

GND

MM|

| GND

GND

Pin | Name

Name

GND

INO2

OUTO02

LL | INO1

OUTO1

OPEN

GND

KK | INO4

OuUTO04

DATA TRANS

OPEN

GND

OPEN

GND

81
8]

HH | INOS

GND

OuUTO0S

OPEN

NEW DATARDY|

INITH

EE | INO6

| OPEN

OuUTO06

DD | GND

GND

6.3.5.2

CC | INO7

OouTO07

are jumper-selected in the range of 0 through 37X,.

Interrupt Vectors — Two interrupt vectors

BB | INO3

OUTO03

The least significant three bits identify the interrupting

AA | GND

GND

function.

INOS8

OouUTO08

INO9

OUTO09

000XXO0

Interrupt A

GND

000X X4

Interrupt B

1 1INI10

OUTI10

IN11

OUT11

Vectors 60 and 64 are reserved for the console device

IN12

OUTI12

and should not be used for DRV11 vectors.

GND

REQB

CSR1

6.3.5.3

GND

sociated with the

IN13

OUT13

are described in Table 6-6.

15
DRCSR

REQUEST B

Word Formats — The three word formats as-

]

REQUEST A |

(READ ONLY)

DRV 11 are shown in Figure 6-14 and

INTENB B

(READ ONLY) | (READ/WRITE)
INT ENB A

CSRO

(READ/WRITE)

(READ / WRITE)
15
DROUT BUF

CSRI

(READ/WRITE)

DATA OUT

(READ/WRITE)
15
DRINBUF

[

DATA IN

(READ ONLY)

Figure6-14

DRV11 Word Formats

6-14

CP-1746

Table 6-6
Word Formats
Word

Bit(s)

CRCSR

Function

REQUEST B — This bit is under control of the user’s
device and may be used to initiate an interrupt se-

quence or to generate a flag that may be tested by the
program.

When used as an interrupt request, it is asserted by
the external device and initiates an interrupt provided
the INT ENB B bit (bit 05) is also set. When used as a
flag, this bit can be read by the program to monitor external device status.

When the maintenance cable is used, the state of this

bit is dependent on the state of CSR1 (bit 01). This
permits checking interface operation by loading a O or
1 into CSR1 and then verifying that REQUEST B is
the same value.

Read-only bit. Cleared by INIT when in maintenance
mode.
14—08
07

Not used. Read as 0.

REQUEST A — Performs the Same function as REQUEST B (bit 15) except that an interrupt is generated
only if INT ENB A (bit 06) is also set.

When the maintenance cable is used, the state of RE-

QUEST A is identical to that of CSRO (bit 00).
Read-only bit. Cleared by INIT when in maintenance
mode.

INT ENB A — Interrupt enable bit. When set, allows
an interrupt request to be generated, provided RE-

QUEST A (bit07) becomes set.
Can be loaded or read by the program (read/write
bit). Cleared by BINIT.
05

INT ENB B — Interrupt enable bit. When set, allows

an interrupt sequence to be initiated, provided RE-

QUEST B (bit 15) becomes set.
04—02

Not used. Read as 0.
Can be loaded or read by the program (read/write
bit). Cleared by INIT.

CSR1 — This bit can be loaded or read (under program control) and can be used for a user-defined command to the device (appears only on Connector No. 1).
Whenthemaintenancecableisused, setting or clearing

this bit causes an identical state in bit 15 (REQUEST
B). This permits checking operation of bit 15 which
cannot be loaded by the program.

Can be loaded or read by the program (read/write
bit). Cleared by INIT.

6-15

Table 6-6 (Continued)
Word Formats

Word

Bit(s)

Function

CSRO — Performs the same functions as

DRCSR

CSR1 (bit 01)

but appears only on Connector No. 2.
When the maintenance cable is used, the state of this

bit controls the state of bit 07 (REQUEST A).
Read/write bit. Cleared by INIT.
DROUTBUF

15—00

Output Data Buffer — Contains a full 16-bit word or
one or two 8-bit bytes: High Byte = 15—8; Low Byte
= 7—0.

Loading is accomplished under a program-controlled
DATO or DATOB bus cycle. It can be read under a
program-controlled DATI cycle.
DRINBUF

15—00

Input Data Buffer — Contains a full 16-bit word or

one or two 8-bit bytes. The entire 16-bit word is read
under a program-controlled DATI bus cycle.

6-16

CHAPTERY7

USING MSV11-A AND MSV11-B
READ/WRITE MEMORY MODULES
7.1

7.2.2

GENERAL

MSVI11-B(4K) read/write memory modules provide

Reply to Refresh

Only one dynamic memory module in a system is re-

temporary storage of user programs and data in an

quired to reply to the refresh bus transactions initiated

inexpensive,

sub-

by the processor. The module selected to reply should

system. The user can select the 4K address space

be the module with the slowest access time. Jumper W4

(bank) in. which the module is addressed by installing

enables or inhibits the

compact,

low-power

memory

MSV11-B reply as follows:

Or removing jumpers.

W4 installed: MSV11-B will not assert BRPLY
The module can be accessed by the LSI-11 micro-

in response to refresh bus signals.

computer or any DMA device that becomes bus mas-

W4 removed: MSV11-B will reply to refresh bus

ter. Interface with the LSI-11 bus is shown in Figure

BSYNC/BDIN transactions by asserting BRPLY

7-1.

7.2

7.2.1

MSV11-BJUMPERS

7.3

The MSV11-B module requires a refresh sequence

Addressing

once every 1.6 ms. This is performed automatically by

MSVI11-B address jumpers are located as shown in

the KD11-F or KD11-J LSI-11 microcomputer.

Figure 7-2. The module is supplied with all address
jumpers

installed.

Figure

address

and

jumpers

how

MSVI11-B BUS RESTRICTION

7-3

illustrates

are

assigned

16-bit

for

the

MSV11-B module.

7-1

READ DATA

BUS

ggzfi\ EAY|C16M%|;

DRA\'s%Rs

BDALO—15L

MEMORY ARRAY

ADDRESS/WRITE DATA

LSTI -11 BUS

RECEIVERS

ADDR.

READ/
WRITE

ADDRESSING
AND CONTROL

BSYNC

BRPLY

BOCOK

BREF

L
CP-1748

Figure 7-1

MSV11-B 4K by 16-Bit Read/Write Memory

M7944

Niwrd

S
W3

BOOUT

T
Y2

BWTBT

BDIN

ETCH REV B

Figure 7-2

CP-1749

MSV11-B Jumper Locations

7-2

BDAL
BITS

wi o

‘

w2z

—

4096 LOCATION ADDRESS

|
BYTE

POINTER

4K ADDRESS

SPACE JUMPERS
r

ADDRESS
O

SPACE
17776

20000

37776

40000

57776

60000

77776

100000

117776

120000

137776

140000

157776

DO NOT USE (RESERVED

FOR DEVICE ADDRESSES)

I =

Jumper

R =

Jumper removed

installed

cCP-1883

Figure 7-3

MSV11-B Address Format/Jumpers

7-3

CHAPTERS

USING MMV11-A CORE MEMORY

modules (G653 and H223) which are mated by con-

fore it is installed in the backplane is to select its bank
address. This is accomplished by opening or closing
switchesinappropriateaddress bit locations to produce

nector pins in a single 8.5 by 10 by 0.9 inch assembly. It

the desired bank address decoding.

8.1

GENERAL

The MMV11-A core memory option comprises two

requires two device locations (electrical positions) on

(Refer to Paragraph 11.3.3 for installation considerations.) Memory capacity is 4096 16-bit words. Address
decoding jumpers allow the user to select the 4K bank

the backplane when iastalled in slots A4-D4 (Figure
11-1); otherwise, because of its total thickness (0.9
inch), the MMV11-A requires four physical device

address to which the MMV 11-A will respond.

locations when installed in any other backplane slot.
8.2

8.2.1

The MMV11-A is fully LSI-11 bus-compatible and can
be accessed by the LSI-11 microcomputer or any DMA
device that becomes bus master. It interfaces with the

SWITCH-SELECTED ADDRESSING

General

bus as shown in Figure 8-1.

The only preparation required for the MMV11-A be-

READ DATA
BUS

BDAL O-I15L

DRIVERS

CORE STACK

AND

RECEIVERS

READ/ WRITE CIRCUITS
ADDRESS/WRITE

DATA

o]
a

g
H

READ / WRITE

TIMING

CONTROL

BDAL I3 —15

TIMING
AND

CONTROL LOGIC
BSYNC L
BRPLY

BDIN L
BDOUT L
BWTBT L
BDCOK H
BINIT

BREF L
CP-1752

Figure8-1

MMYV11-A 4K by 16-Bit Core Memory

8-1

MMV 11-A bank address switches are used as shown in

8.3

Figure 8-3. The figure illustrates a 16-bit address and

The BDMGI L and BIAKI L bus lines must be

how switches are assigned to each address bit. Open or
close switches to produce the desired bank address as

jumpered to BDMGO L and BIAKO L lines, respectively, under the H223 module when installed be-

directed in the figure. Switches are located on the G653

tween the processor and 1/0 device interface modules

module (component side) as shown in Figure 8-2.

in order to maintain daisy-chain signal continuity.
Pins which must be connected are:

L
M

BUS RESTRICTIONS

From

Signal

AM?2

AN?2

BIAKI/OL

CM?2

CN2

BIAKI/OL

AR2

AS2

BDMGI/OL

CR2

CS2

BDMGI/OL

Bus pins can be identified as shown in Figures 3-2 and
Swi
Sw2
SwW3
SW4 (NOT USED)

3-3.

]

Memory refresh is not required for this memory option.

If memory refresh is used for other memory options,
such

CP -1754

the

KD11-F’s

resident

memory

MSV11-B semiconductor memory, the

Figure8-2

Bank Address Switch Locations

BoAL w15
—

ADDRESS
WORD

not respond to the refresh operation.

13
1

|
1

) T

LOCATION

BYTE

ADDRESS
Sw2

Swi

BANK

O - 17776

20000 - 37776

40000 - 57776

60000 -

77776

100000 -

117776

120000 - 137776

140000 -

POINTER

ADDRESSES

4096

SW3

and

160000 -

157776

177776

NOTES:

1. C=SW ON ; O=SW OFF
:

I
ved
2. . Bank 7. is normally
reserve
for peripherals.
CP-1753

Figure8-3

MMV11-A Addressing

8-2

the

MMV 11-A will

CHAPTERY9

USING MRV11-A READ-ONLY MEMORY

compact, nonvolatile memory subsystem. Depending

(or removing) jumpers on the module. Similarly, when
using 256 by 4-bit chips, the user can jumper-select the
upper or lower 2K segment within the selected 4K address bank. Note that 512 by 4-bit and 256 by 4-bit
chips cannot be mixed on a MRV11-A module; the
user configures jumpers on the module for the chip

upon chip types, the module’s capacity is either 4096

type being used.

9.1

GENERAL

The MRV11-A (Figure 9-1) is a read-only memory

module which allows the use of user-supplied, preprogrammed, programmable read-only memory (PROM)
and masked read-only memory (ROM) chips in a

16-bit words or 2048 16-bit words, using 512 by 4-bit or
256 by 4-bit chips, respectively. Full address decoding

A partial listing of manufacturer’s chips that will

is provided on the module. The user can select the 4K

operate in the MRV 11-Ais given in Table 9-1.

address bank in which the module resides by installing

CHIP ROWS

Ot 2 3 4 5 6 7

12-15

BDAL —15L

BUS

DRIVERS

AND
RECEIVERS

8 -11

READ DATA

MEM

o« pgo,&)%w

4-7

CHIP SOCKETS

0-3
wn
@

:':

«|

“

w
O]

<|I

—

MEMORY ADDRESS AND
INTERFACE CONTROL LOGIC

BSYNC
L
BOIN
L
BRPLY
L

CP—- 1755

Figure9-1

MRV11-A Read-Only Memory

Table 9-1
MRV11-A Chips
Manufacturer or Source

512

Model/Type
Digital Equipment Corp.

Intersil

[]

by 4-Bit Chips

(]

256 by 4-Bit Chips

| PROM/ROM | Model/Type

| PROM/ROM

| MRV11-AC

PROM

—

IMS5624

PROM

IMS623

PROM

8259

PROM

Signetics

9-1

Chips used must be tristate output devices which conform to the device pinning, data, and addressing
described in the remainder of this chapter.

The user can install chips in increments of four chips
each. When using 512 by 4-bit chips, memory expansion is in S12-word increments. When using 256 by
4-bit chips, memory expansion is in 256-word incre-

ments. Jumpers on the MRVI11-A can be cut by the
user to prevent an incorrect BRPLY L signal from

being

generated when unpopulated
addressed on the module.

MMM
TMM

W7 S

W3 .

W4 I

W17 S

W15

W16

s
W13

W14

W11 S,

W12

"ol

]

v
WO

W10

VEN

M 7942 ETCH REV. D

Figure9-2

are

The information contained in the remainder of this
chapter will enable the user to prepare the MRV11-A

N
12 —-15

locations

CP-1756

MRV11-AJumper Locations

for use (Jumper-selected addressing and chip selection)

9.2.3

and includes information required for correct PROM

The user must consider both 4K bank address selection

and ROM programming.

and BRPLY L signal generation when configuring a

Addressing and Reply

module for use. Chips (either PROM or ROM, 512 by 4
or 256 by 4) are arranged in eight physical rows (CE0—

9.2

JUMPER-SELECTED

ADDRESSING

AND

CE7) of four chips each.

CHIPTYPE

Entire rows can be un-

populated, allowing those addressed locations to be

used by read/write memory contained on another
9.2.1

General

module. When this is done, the BRPLY L jumpers

Jumpers which allow the user to select the 4K bank in

(W0—W?7) associated with the unused rows should be

which tiiec module can be addressed and jumpers which

cut or removed to prevent the MRV11-A from re-

allow the ase of 512 by 4-bit or 256 by 4-bit PROM (or

turning a BRPLY L signal when those rows are ad-

ROM) chips are provided on the MRV11-A. In addi-

dressed. A listing of octal addresses (within a 4K

tion, jumpers may be removed from the module to pre-

bank),

vent the module from generating an active BRPLY L

provided in Table 9-2; use data listed for the chip type

signal when a portion of the module is addressed that

being used.

physical rows,

and

BRPLY

L jumpers

does not contain PROM or ROM chips. Jumpers are
located as shown in Figure 9-2.

The 4K

bank in which the MRV11-A

resides

programmed by connecting bank address jumpers

9.2.2

Chip Type Selection

W15—W17, as appropriate. The module is supplied

The module is supplied with jumpers W8, W9, and

with all bank address jumpers installed (bank 0).

W10 installed for use with 512 by 4-bit chips. When

Jumpers installed represent logical Os; jumpers not

using 256 by 4-bit chips, W8, W9, and W10 must be

installed represent logical 1s.

cut or removed and jumpers W11 and W12 installed; in
addition, either W13 (lower 2K) or W14 (upper 2K)

Figure 9-3 illustrates addressing words used with the

must be installed to properly address the lower 2K or

MRV11-A. Refer to the addressing format for the type

upper 2K address segment within the 4K memory bank.

of PROM or ROM chips being used.

0
4
512X

PROM/ROM

CHIPS

’

—

]

—_—

4096
- LOCATION ADDRESS
(W8
- W10 INSTALLED:

W11
- W14 REMOVED)

BYTE
POINTER

4K ADDRESS
SPACE JUMPERS

X 4
256
PROM/ ROM

CHIPS

|
o

’

|
(W11

]

2048- LOCATION ADDRESS
AND W12

L HIGH/ LOW 2K SELECT

S;AKCEABB;EPS&SRS

LOW 2K (0-7777)

—

]
INSTALLED:

W8-W10 REMOVED)

BYTE

POINTER

W13 INSTALLED:

Wi4 INSTALLED:

HIGH 2K (1000-17777)

Figure9-3

MRV11-A Address Word Formats

cP-1757

Table 9-2
PROM/ROM Chip Addressing Data
Bank Addr.

512 by 4 Chips_

Jumpers*

WI15§

256 by 4 Chips

Word/Byte

Physical

BRPLY L

Address

Row

Jumper

wi6 | w17

Word/Byte Address

‘Physical

BRPLY L

W13 Installed

W14 Installed

Row

Jumper

0-1777

CEO

0-777

10000-10777

CEO

2000-3777

CE1l

1000-1777

11000-11777

CE4

[

4000-5777

CE2

2000-2777

12000-12777

CEl

6000-7777

CE3

3000-3777

13000-13777

CES

10000-11777

CE4

4000-4777

14000-14777

CE2

12000-13777

CES

5000-5777

15000-15777

CE6

14000-15777

CE6

6000-6777

16000-16777

CE3

16000-17777

CE7

7000-7777

17000-17777

CE7

*R = Jumper removed: I = Jumper installed

9.3

locations. The actual chip within a row is designated by

PROGRAMMING PROM AND ROM CHIPS

The actual procedure for loading data into PROM

one additional digit (0, 1, 2, or 3). Hence, the data pins

chips or writing specifications for masked ROM chips

are assigned to LSI-11 bus bits as listed in Table 9-3.

will vary, depending upon the chip manufacturer.
Those procedures are beyond the scope of this docu-

Table 9-3

ment. (See chip manufacturer’s data sheets.) However,

Data Pin Assignments

the user must be aware of the chip pins versus LSI-11

Chip Pin | Chip 0

data bit relationship, and the chip pin versus memory

Chip 1

Chip 2

Chip 3

address bits. Address and data pins are described

BDAL3 | BDAL7 | BDAL11 |BDALI1S

BDAL2 | BDAL6 | BDAL10 | BDAL14

As previously discussed, chips are arranged in rows of

BDAL1 | BDALS | BDAL9

|BDALI13

four chips each. Each chip contains locations of four

BDALO | BDAL4 | BDAL8

|BDALI12

below.

bits each. Hence, four chips are used to provide the
16-bit data word formats for each row. Rows are de-

Addressing of chips is shown in Figure 9-4. All chips

signated by their respective Chip Enable (CEO—CE?7)
signals. Depending upon the chip type used, a row of

used on the MRV11-A must conform to this information. Observe that the only difference between S12 by

four chips contains S12 or 256 16-bit read-only memory

4-bit and 256 by 4-bit chip pins is pin 14. The 312 by

LSI-11 CHIP PIN SIGNIFICANCE

DAL6 L — Ag
DAL

—A

15] A7

s B3

13] Ag

14|

DAL4 L — Az [4]

DALS L

Agor CE

13] CE

DAL L — Ag [5]

12] 0y |

DAL2 L — A, [6]

11] 02

DAL3 L — A, [7]

10] 03

GND [8]

CHIP ENABLE

512 x 4-BIT PART

DALY L

(ROW)

256 x4-BIT PART

LOWER/UPPER

2K SEGMENT

(WITHIN BANK)

CHIP ENABLE

»—— DATA PINS

04 |

TOP VIEW

NOTE:

Designations immediately adjacent topins are typical
designations used by chip manufacturers —not LSI-11
designations. LSI-11 designations for correct
addressing are located away from the chip. Observe that
these signals are low — active; they are double - inverted

bus signals ( low = logical "1").

IC-0169

Figure 9-4

PROM/ROM Chip Pin Addressing

4-bit part uses this pin for address bit DAL9; the 256 by

error (timeout) because the processor will attempt to

4-bit part uses this pin for a chip enable when both

write into the same location. When fetching MTPS or

bank address and 2K segment address are true. Also

EIS instruction source operands,

note that bus address bits do not follow in sequence

source operand from the PROM or ROM location to a

first MOVe the

with chip manufacturer’s address designations. The

general register. MTPS or EIS instruction can then be

pinning arrangement shown allows for the use of

executed using the general register contents as the

commonly available PROM and ROM chips and opti-

source operand. If desired, read-write memory could

mum (compact) MRV11-A module layout.

be used instead of the general register to temporarily
store the source operand.

9.4

PROGRAMMING RESTRICTIONS

9.5

Special care must be used when programming PROMs

TIMING AND BUS RESTRICTION

Addressed memory read data is available within 120 ns

or ROMs for use with MTPS instructions and KEV11

after the BSYNC L signal is received by the MRV11-A.

option

fetch

Logic on the module responds to DATI bus cycle only.

source operands via the DATIO bus cycle, rather than

DATO or DATOB bus cycles will result in a bus time-

EIS

instructions.

These

instructions

the DATI bus cycle. Hence, fetching a source operand

out error. Logic functions on the module are not af-

from a PROM or ROM location will result in a bus

fected by the bus initialize (BINIT L) signal.

9-S

CHAPTER10

USER-DESIGNED INTERFACES

10.1

+3.4V

GENERAL

This chapter contains sample circuits and information

R1:120K,

MIN

R2:=20K,
MIN

which can be utilized in user-designed hardware that is

C1:10 pF, MAX

o__m_f_v

installed on the LSI-11 bus. The user must ensure that

the circuit, as used in a particular application, contorms to the LSI-11

bus specifications included

Chapter 3. The various interface module and prewired
backplane options previously described in this manual

are designed for ease of user prototype development.
However, in those applications that require a special

TRANSMITTER

OFF [ LOGICAL O )

interface module, hardware components listed in the

: 120K, MIN

Hardware/Accessories Catalog will enable backplane

TRANSMITTER

connector-compatible systems to be rapidly assembled.

10.2
The

10pF

MAX

ON [LOGICAL |

R3= 11 OHMS, MAX
C2 <

10 pF. MAX
113298

BUS RECEIVER AND DRIVER CIRCUITS
equivalent

circuits

LSI-11

bus-compatible

Figure 10-1

Bus Driver and Recetver Equivalent Circuits

drivers and receivers are shown in Figure 10-1. Any
device that meets these requirements is acceptable. To

perform these functions, Digital Equipment Corporation uses two monolithic integrated circuits with the
characteristics listed in Table 10-1. A typical bus driver
circutt 1s shown in Figure 10-2. Note that DEC 8641

BUS

quad transceivers can be used, combining LSI-11 bus
receiver and driver functions in a single package.

r
TYPICAL

BUS

DRIVER
11-3307

Figure 10-2

Typical Bus Driver Circuit

Table 10-1
LSI-11 Bus Driver, Receiver, Transceiver Characteristics

Characteristic

Specifications Notes

Receiver

Input high threshold

VIH

1.7Vmin.

(DEC 8640,

Input low threshold

VIL

1.3Vmax.

DEC&641)

Inputcurrentat2.5V

ITH

80uA max.

1,3

Input currentatQV

IIL

10uAmax.

1,3

Output high voltage

VOH

2.4V min.

10-1

- : 0 are+ = HSNLVLS8N3
1

12 0 H X710 v N3

v8N3 bibl

4WOY

oHV15v0y
OdI 1v

AG+

10-4

unique bus addresses for user-supplied 1/0 functions.

IRQA L signal will go low (false), causing BIRQ to go

Address bit O is a byte pointer which is only used for

tfalse. IRQA L is ORed with IRQB L and applied to a

DATOB or the write portion of DATIOB bus cycles.

type DEC 8881 bus driver, asserting the BIRQ bus

Read data should be multiplexed using stored address

L, producing a high DIN H signal. This signal clocks

signal line. The processor responds by asserting BDIN

bits SA1 H and SA2 H. In addition, an interface circuit

the device states (A or B requesting or not requesting

that also includes interrupt logic should use VECTOR

service) into the IAK flip-flops. At a later time, the

EN L to inhibit register read data and enable the

processor asserts BIAKI L, producing a high IAK H

interrupt

vector

transfer

during

the

interrupt

signal. IAK H is gated with the IAK flip-flop signals,
giving the highest priority to Request A, if both are re-

sequence.

questing service. The 7400 gate associated with the

[IAK A flip-flop Q output goes low, clearing the IAK

Write data strobed for the four addressable device

registers are produced by a 74155 dual 2:4 demulti-

ENB A flip-flop, and producing VECTOR L and

plexer; however, other devices and circuits can be used.

BRPLY L signals. VECTOR L is used for gating the

Both sections of the 74155 are simultaneously strobed

vector address

by the WRITE DATA EN L signal. During word trans-

device’s IAK ENB flip-flop clear, it will not generate

fers, WB H is passive (low), enabling the DATA and

another interrupt until

DATB demultiplexer inputs. As a result of the logical

service.

state of stored address bits SA1 H and SA2 H, one Byte

onto

the

I/O

bus. With the

the device again requests

When not requesting service, both Interrupt Acknowl-

O and one Byte 1 write data strobe will go active,

edge (IAK) flip-flops remain cleared. The flip-flop Q

enabling writing into all 16 bits of the addressed device

outputs are both gated with IAK H, producing an

active BIAKO L signal which is passed to the next
(lower priority) device on the I/O bus. The INIT L
signal, produced by a bus receiver and inverter, clears

registers, WB H goes active (high), enabling stored

address bit0 (SAO Hand SAOL) to assert only one data
input (DATA or DATB) on the 7415S. Hence, only one

all Enable and IAK flip-flops, and presets (a don’t care
condition) all INT ENB flip-flops. When requesting

of the eight write strobes will go to the active state; an
8-bit transfer to the appropriate high or low byte in the

service, the IAK flip-flops inhibit passing BIAKO L to

addressed register is this completed.

10.4

bits

the next lower priority device.

CAUTION

INTERRUPTLOGIC

TIAK flip-flops must function as synchronizers.

The basic logic functions required in an interrupt circuit are shown in Figure 10-4. This is a dual interrupt

(Data setup has no guaranteed minimum time.)

circuit which will enable and control two interrupt
request sources (A and B) supplied by the user. The

Type 7474 and 74574 are preferred.

four flip-flops, ENABLE A and B, and INT REQ A

10.5

and B comprise bits of one or two control/status

A simple DMA request circuit is shown in Figure 10-5.

DMAINTERFACELOGIC

registers (CSR). The set/reset status of the Enable flip-

In addition to this circuit, bus address, word count,

flops is established by a programmed output transfer.

control/status registers,

EN A CLK H and EN B CLK H

logic would normally be included. All registers would

signals are the write

data strobes shown in Figure 10-3; EN A DATA H and

and burst transfer control

be accessible via programmed 1/0 operations.

EN B DATA H would then be two of the received data

bits (DEC 8641 ““Rn”’ outputs). Similarly, INT REQ A

A DMA request is initiated by a device by producing an

and B flip-flop outputs INT REQ A and INT REQ B

multiplexer in the device’s logic.

active REQ H signal. The RQST H signal must remain
high until bus mastership is no longer required. The
type DEC 8881 bus driver then asserts BDMR L.

A typicalinterrupt sequence for ‘“‘device A” is described

The processor arbitrates the request by

below. An interrupt is enabled under program control

BDMGI L, setting the Claim flip-flop in the first re-

would be read as bits in the CSR via the read data

asserting

by setting the ENABLE A flip-flop. When the user’s

questing device along the BDMG daisy chain. The

device is ready for service, it produces an active RQST

state ot the Claim flip-flop is sampled by two gates

A H signal, which is ANDed with ENABLE A. The
AND gate output clocks the IAK ENB A flip-flop to

inhibits the DMGO EN H gate. Hence, when the Claim

the set state and IRQA L is produced. Note that if the

tlip-flopisset, BDMGO Lisnot passed to lower priority

user’s device terminates the RQST A H signal, the

devices. The active (high) CLAIM (1) H signal is gated

after the DMG delay. CLAIM (0) H is low (false) and it

10-S

with DDMG H producing a low signal which enables

When not requesting DMA service, the device must

one of the three 7427 gate inputs. When BSYNC L and

pass BDMG signals to lower priority devices on the 1/0

BRPLY L become negated, passive (low) SYNCR H

bus. The active (high) CLAIM (0) H signal is gated with

and RPLYR H signals are gated with CLAIM (1) H and

DDMG H producing an active DMGO EN H signal.

the 7427 output goes high. This transition clocks the

This signal enables the BDMGO L bus driver and

Master flip-flop to the set state producing the active

DMG H is gated onto the bus.

MASTER H signal, enabling BSACK L and negating
BDMR L signals. MASTER H is used by the DMA

The actual DMG delay is determined by the RC circuit

device to enable its bus cycle. BSACK L informs the

shown on the figure, and should be 100 ns (min).

processor that the bus is in use. At the end of the bus

BINIT L initializes the circuit by clearing the Claim

cycle, the device negates REQ H, clearing the Claim

and Master flip-flops.

and Master flip-flops. MASTER H and BSACK L signals then go passive.
REQ H

oS,

BOMR L

MASTER
L
BRPLY L

gggo

RPLYR

—D0
a
MASTER

> MASTER H

DDMG H—‘

BOMGI

3308

DEC
864Q

7400

ELAIM(”H

3521

BSACK L

ras74 CLAIM (0) H

DMG H

C c

6808

DEC
BINIT L —Olg&ao

CLAIM

74574

=
Q

CLR

INIT L .

7408

$360

@t |

DMG H

DDMG H

6804

DMG DELAY

(SEE NOTE)

NOTE

The DMG Delay Circuit shown above
is preferred. However, the following

DMG Delay Circuit can be used:

DMG H

7408 \ J‘g‘ovg
EL_J

i——

SYNCR H

DEC

BSYNC L

» DDMG H

pf
820

CP-1785

Figure 10-5

DMA Arbitration Logic
10-6

If dynamic MOS

memory

used

(KD11-F processor and/or MSV11-B

the

system

memory),

DMA device is restricted to one bus cycle for each
BDMG signal from the processor. This must be done to
allow the processor to execute memory refresh trans-

actions.

In systems which

include

dynamic

MOS

memory and use more than one DMA device, the DMA
interface designer must ensure that sufficient time will
be allowed for the processor to execute memory refresh
transactions.

CAUTION
The Claim flip-flop must function as a synchronizer. (Data setup has no guaranteed minimum
time.) Types 7474 and 74S74 are preferred.

10-7

CHAPTER11

SYSTEM CONFIGURATION AND INSTALLATION

11.1

MMVII-A Memory 4K Address Selection

GENERAL

4K address select switches (Paragraph 8.2)

This chapter contains the basic considerations and requirements for configuring and installing LSI-11 or

MRVI1I-A PROM/ROM MemoryJumpers

PDP-11/03 systems. The following paragraphs apply

to both LSI-11 systems and PDP-11/03 systems, except

Memory address (Paragraph 9.2.3)

Replysignal (Paragraph 9.3)

where clearly stated otherwise.

512 by 4-bit or 256 by 4-bit PROMs (Paragraph
11.2

CONFIGURATION CHECKLIST

9.2.2)

LSI-11 and PDP-11/(3 systems comprise user-selected
module options asrequired for a particular application.

MSVI1I-A IK by 16 Random Access Memory Address

Each module may require jumper alterations or switch

Jumpers (Paragraph 7.2)

settings to provide the correct addressing, operation,
MSVI1I-B4K by 16 Random Access MemoryJumpers

etc. for the user’s application. A module configuration

checklist for each module type is provided below. De-

Memory address (Paragraph 7.3.1)

tailed information for configuring the modules can be

Reply to refresh (Paragraph 7.3.2)

obtained by referring to the paragraphs listed in the

The following checklist is for LSI-11 system configurations. It includes items that are not contained on
particular modules but which must be checked to

checklist.
KDI1 Processor

Jumpers

ensure that the system is properly installed.

Power-up mode (Paragraph 5.2.4)
Memory refresh enable (Paragraph 5.2.2)
Line time clock enable (Paragraph 5.2.3)

BDCOK, BPOK, BEVNT, and BHALT sig-

Resident memory 4K address selection (KD11-F

nals connected as required to H9270 back-

only) (Paragraph S.2.5)

plane assembly (Paragraph 11.7.5).
Modules inserted in H9270 backplane slots

DLVI1I Serial Line UnitJumpers

according to desired priority (Paragraph

Device address (Paragraph 6.2.2.2)

11.3).

Vector address (Paragraph 6.2.2.3)

Universal

asynchronous

receiver

Jumpers added to H9270 backplane when

transmitter

operation (Paragraph6.2.2.4)

core

Baud rate selection (Paragraph 6.2.2.5)

between processor and 1/0 device modules

EIA interface (Paragraph 6.2.2.6)

(Paragraph 11.3.3).

20 mA current loop interface (Paragraph 6.2.2.7)

Correct

Framingerror halt (Paragraph 6.2.2.8)

(MMVI11-A)

cabling selected

for

I/0

located

device

modules (Paragraph 11.5).

DRVII Parallel Line Unit Jumpers and Pulse Width

Modules inserted in backplane slots with

Modification

components facing in the correct direction

Device address (Paragraph 6.3.2.2)

(Paragraph 11.4).

Vector address (Paragraph 6.3.2.3)
NEW DATA READY and

memory

DATA

Correct power and ground inputs to H9270

TRANS-

backplane

MITTED pulse width modification (Paragraph

connector

11.7.3.and 11.7.4).

6.3.4.6)

11-1

block

(Paragraphs

CAUTION

the front panel exposes the LSI modules and cables.
. This enables replacement or installation of a module

The LSI-11 modules and the backplane assembly

from the front of the PDP-11/03. The 11/03 power

mounting blocks may be damages if the modules

supply

are plugged in backward.

PDP-11/03 when viewed from the front. The power
supply

DC power must be removed from the backplane

located

contains

the

three

right-hand

front

side

panel

of the

switches

and

indicators which are accessible through a cutout in the

during module insertion or removal.
11.5

front panel. Therefore, when the front panel is removed, the lights and switches are still attached and

I/0 CABLING

Recommended I/0 cable options for use with the
DLV11 serial line unit and

functional.

DRV 11 parallel line unit

are listed below:

DLV11 Serial Line Unit

Cable*

20 mA Current Loop

BCOSM-X

EIA Interface

BCO0SC-X

DRV11 Parallel Line Unit

Cable*

_E.J; }t 172"
hN__,v,.w 9

Any combination of one input and one output cable

11-3303

may be selected from the

two types listed:

13.50"

—

Flat Cable

BCO8R-X

Twisted Pair

BC11K-25

11.6

11.6.1

POWER SUPPLY
AIR

AIR

FRONT

PDP-11/03 INSTALLATION PROCEDURE

Packaging and Mounting

The PDP-11/03is packaged as shown in Figure 11-4. It
is designed with a removable front panel. Removing

PROCESSOR,
MEMORY
AND

DEVICES

*The -X in the cable number denotes length in feet, as follows: -1, -6,

11-3304

-10, -20, -25. For example, a 10-ft EIA interface cable would be ordered as BCO5C-10.

Figure11-4

H9270 Backplane

Table11-1

PDP-11/03 Input Power Electrical Specifications

Parameter

Input Power

Model

Specifications

PDP-11/03-AA or | 100—127 Vac, 114 Vac nominal; S0 * 1
|Hz or 60 + I Hz, single phase
PDP-11/03-BA
PDP-11/03-AB or | 200—254 Vac, 230 Vac nominal; S0 *+ 1
PDP-11/03-BB
Hz or 60 £ 1 Hz, single phase

Input Power

All

400 W max at full load;
190 W typical

100 % of nominal voltage:
9t020 ms

Temporary Line | All
Dips Allowed

40% of nominal voltage:

20t0 96 ms

28 % of nominal voltage:
96 to SO0 ms

11-4

The PDP-11/03 is designed to mount in a standard 19

The H780 power supply provides the required dc power

in. cabinet (Figure 11-5). A standard 19 in. cabinet has

for the backplane in the PDP-11/03 enclosure. Typical

two rows of mounting holes in the front,

spaced

dc power requirements will range from 33 to 120 W

18-5/16 apart. The holes are located 1/2 in. or 5/8 in.

(max). In addition, the power supply generates the

apart. Standard front panel increments are 1-3/4 in.

necessary BPOK H and BDCOK H power supply

11.6.2

status signals, displays the RUN and DC status, and

Power Requirements

Input (primary) power requirements are listed in Table

11-1.
Ap sppropriate power cable and plug is supplied with

all PDP-11/03 models. Note that a ground wire (and

grouind pin on the plug) must be connected to the

contains the ENABLE/HALT, DC ON/OFF,
LTC ON/OFF

and

control switches.

Before attempting to operate the system, ensure that

the system is configured as previously described in this
chapter, and that environmental requirements are
met.

normal service ground to ensure sare operation. Do not

cut or remove the ground pin.
FRONT

VIEW

11.6.3

!
B
O /

1/4' C)
R
U R By ¥
T T 0|+
—

‘

TOP OF

FRONT PANEL

5/8"

STANDARD

1-3/4"

Environmental Requirements

The PDP-11/03 will operate at temperatures of 41° to
104° F (5° to 40° C) with a relative humidity of 10 to 90
percent (no condensation), with adequate air flow
across the modules. The fansin the H780 power supply
will provide adequate air flow within the specified

temperature range.

5/8"

3-172"

—_——

— f 2"

O+

O
O

O+
O+

11.7

LSI-11 SYSTEM INSTALLATION

5/8"

11.7.1

5/8"

18-5/16"

mount the H9270 backplane, provide dc operating

power, ground, and externally generated bus signals,
and observe system environmental requirements. The

—=

following paragraphs describe the

0.88" -

11.7.2

18.31"

19" TYP
——-J‘:’lofs/a"wp

FRONT OF BOX(PANEL REMOVED)

B 1/4" TYP

r-s——————— 19"

above items in

detail.

11-3297

3.50" 175"—1*

General

When installing the LSI-11 system, the user must

=IJ

Mounting the H9270 Backplane

The H9270 backplane (Figure 11-6) is designed to

accept the KD11-F or KD11-J microcomputer and up
to six I/0 interface or memory modules. Mounting of
the H9270 backplane can be accomplished in any one
of three planes, as shown in Figures 11-7, 11-8, and
11-9.

11-330%k

11.7.3

11.7.3.1

DC Power Connections

Voltage and Current Requirements — A

power supply for a single backplane LSI-11 system
0

MJI_‘L

FRONT

should have the following capacity:

+SV

2% load; 0—18 A static/dynamic

+12V * 2% load; 0—2.5 A static/dynamic
|

11-3306

Sripple: less than 1% of nominal voltage

+ 12 ripple: less than 150 mV pp (frequency
SkHz)

Figure 11-S

NOTE

PDP-11/03 Cabinet Mounting

Regulation at the H9270 backplane must be
maintained to the specifications listed in Table 21.

11.7.4

H9270 Backplane Ground Connection

11.7.6

Externally Generated Bus Signals

Connect the H9270 backplane ground wire to system
(or frame) ground in which the H9270 is installed. The

11.7.6.1

ground terminal is located as shown in Figure 11-10.

include BDCOK

11.7.5

General
— Externally generated bus signals

H and BPOK H power status,
BEVNT L (line time clock) (if required), and BHALTL

Environmental Requirements

(if desired). The signals are applied to the backplane

AN LSI-11 modules will operate at temperatures of 41°

via a connector and an optional mating connector as

to 122° F (5° to S0° C) with a relative humidity of 10 to

shown in Figure 11-13. The signals must conform to

90 percent (no condensation), with adequate air flow

LSI-11 bus configuration specifications described in

across the modules. When operating at the maximum

paragraphs 3.12,3.13, and 10.2. Connections made to

temperature (122° F or S0° C), air flow must maintain

the backplane via the ribbon cable shown in Figure

the inlet to outlet air temperature rise to 12.5° F (7° C)

11-13 must not exceed 12 inches in length. Each signal is

maximum. Air flow should be directed across the

discussed in the following paragraphs.

modules as shown in Figure 11-12.

AIR
OUTLET

CP-1764

Figure11-12

RIBBON

H9270 Backplane Air Flow

CABLE

\
ALIGNMENT

Posmow\

MATING CONNECTOR DEC PART No.12-11206-02

(3M PART No0.3473-3)

r—//3‘°gg<\socox

BEVNT/ %\‘\BHALT
GND
BPOK

SRUN

H9270

PRINTED

CIRCUIT

BOARD
3

—

SIDE 2

Figure 11-13

H9270 Backplane Printed Circuit Board

11.7.6.2

BDCOK H and BPOK H — The processor

Generation of BPOK H and BDCOK H signals can be

monitors power supply status and responds, as appro-

provided

priate, by the BDCOK H and BPOK H signals. These

manual operation can be selected, as follows:

automatically via user-supplied

logic,

signals are defined below:
Automatic: Connect BPOK H and BDCOK H

BPOK H Assertion

signals from the power supply logic to H9270

8.0 ms of dc power reserve and BDCOK has been

backplane as shown in Figure 11-13.

asserted for 70 ms min; 3.0 ms minimum as-

Manual: Connect ground to a momentary ON/

sertion of BPOK required.

OFF switch (BDCOK switch), as shown in Figure

BPOK H Negation

11-16. Connect the BDCOK switch output to the

4.0 ms of dc power reserve, but power is failing;

BDCOK H input on the H9270 backplane via a

1.0us minimum negation time for BPOK.

switch bounce eliminator. To initialize the proc-

BDCOK H Assertion

essor after power is applied, the BDCOK switch

3.0 ms of dc power has been applied; 1.0
us mini-

must be momentarily depressed (off), then re-

mum assertion time for BDCOK.

leased (on).

BDCOK H Negation

S5.0us of dc power reserve but no sooner than 3.0

NOTES

ms after BPOK negation; 1.0 us minimum nega-

A switch bounce eliminator must be used with

tion time for BDCOK.

the manual BDCOK switch, as shown.
If the manual method of applying BDCOK H is

During the power-up sequence, after dc power has

selected, contents of semiconductor read/write

been applied (Figure 11-14), the processor asserts

memory may be lost when BDCOK switch is de-

BINIT L in response to a passive (low) power supply-

pressed.

generated BDCOK H signal. When BDCOK H goes

active (high), the processor terminates BINIT L after

NOTE

approximately 12us, and waits for assertion (high) of

It is not necessary to negate the BPOK H signal

BPOK; then the user-selected power-up mode is exe-

when manually initializing the processor. BPOK

cuted. Similarly, if power fails (Figure 11-15), the

H may be left unconnected.

power supply-generated BPOK H signal goes passive
(low) and causes the processor to push the PC and PS

11.7.6.3

onto the stack and enter a power fail routine via vector

BEVNT L Signal — The BEVNT L signal

location 24 (power fail trap location). The processor

input to the H9270 backplane (Figure 11-13) is the ex-

will execute the power fail routine until either BDCOK

ternal event interrupt. Asserting the BEVNT L signal

H goes passive (low), indicating the dc operating power

initiates the LTC (line time clock) interrupt on the

may not sustain processor operation, or BPOK H

processor. The processor will trap through location

100g if PS bit 7 = 0. A typical circuit for generating

returns to the active state. BINIT L will be asserted if

BEVNT L is shownin Figure 11-17.

BDCOK H goes passive.

POWER

:\
|
|

BPOK H } H
b

20—

BDCOK H

le—
I

!
!

—»] >4ms |je—

|
|

-——-<L

AC INPUT

BOCOK H

"""""—”I""_

AC INPUT f

DC POWER

220ms —DI L—Z3ms—4¢——>70ms ——»l

—

;35;;5

le—
CP-1767

CP-1766

Figure11-14

Figure 11-15

Power-Up Sequence

11-9

Power-Down Sequence

SWITCH BOUNCE
ELIMINATOR
r—
TM

BDCOK

MOMENTARY

BDCOK ON L

SWITCH

408

Teocox OFF L

! |

7404

|ess!

I
e e

J
o

+—BDCOKH

00000

BACKPLANE

PRINTED

SIDE

CIRCUIT BOARD

NOTE:

BDCOKH

SIGNAL (ASSERTED HIGH)

LOW: 1.3V

MAX

HIGH: 1.7V

MIN
CP-1768

Figure11-16

BDCOK H Signal Routing Diagram

11.8.2

PDP-11/03 Power-On

Proceed as follows:
FREQ = AC PWR
LINE FREQ.

Ensurethatthesystemis properly configured
as previously described.

BEVNT L

Figure
11.7.6.4

11-17

Place the DC ON/OFF switch in the down

position (DC OFF).

CP-2040

BEVNT L Signal

BHALT L Signal — Manual control of the

Place the AC ON/OFF switch on the rear of
H780 power supply in the ON position.
Placethe HALT/ENABLE switch in the de-

sired power-up position.

Halt mode can be obtained by connecting a BHALT L
signal line to the H9270 backplane printed circuit

board as shown in Figure 11-13. The BHALT L signal
NOTE

level should meet bus specifications described in Paragraph 3.12.

The dc power can be applied with the HALT/

When in the Halt mode, user program execution is not

processor power-up mode is affected by this

performed and the processor executes ODT console
microcode. However, the processor will execute

listed in Table 11-4.

ENABLE switch is either position. However,

switch and jumper-selected power-up modes, as

memory refresh in a normal manner and respond to
DMA requests, even when BHALT is asserted; all

device and LTC interrupt requests are ignored.
11.8
11.8.1

Place the LTC ON/OFF switch in the OFF
position.

SYSTEM OPERATION

Placethe DC ON/OFF

switch in the up (DC

ON) position. The console device should

General

respond with a printout (or display)

The procedures included in the following paragraphs

shown in Table 11-4.

describe power turn-on and operational checks for

LSI-11 and PDP-11/03 systems. Refer to the LSI-11,

Proceed with initial power-on checkout by
entering and executing the program listed in

PDP-11/03 Processor Handbook for detailed operation, including console ODT and program execution.

Paragraph 11.8.4.

11-10

oy} ‘pejuswa[duur jou ST (LLLE—000E)

11-11

LSI-11 Power-On

This program outputs all ASCII characters and may

Enter and execute the program via the console device

as directed below:

Remove all modules from the backplane.

It is recommended that a single switch be
+12V to the

H9270 backplane. There is no required volt-

age application sequence.
4.

Turn power-on.

At the H9270 backplane,

Row 1, Slot
A, Pin A2: +5V

Row 1, Slot
A, PinD2: +12V

Enter instruction (octal code).
Press LINE FEED.
Repeat above steps until all instructions

Press RETURN.

Enter starting address.
Press G.

Row 1, Slot
A, PinV1: 45V

CAUTION

Press the BREAK key on the console device

to stop program. If the console device does

Do not plug in modules with power applied to

not include the BREAK

H9270 backplane.

HALT switch

key,

(PDP-11/03

press

panel

the

or the

manual HALT switch described in Para-

Turn power off.

Ensurethatthesystemis properly configured

graph11.7.6.4).

and installed as previously described.

Turn onsystem power. Observe that the console device responds as described in Table
11-4.

Press slash (/).

have been entered.

check for the

following voltages:

Enter Starting address.

used to apply +5V and

»ob
w
=

Ensure that there is no dc power applied to

the H9270 backplane.

include control codes for specific devices.

»®

11.8.3

Proceed as follows:

A sample console printout of the above program is
shown in Figure 11-18.
11.9

PAPER TAPE SYSTEM OPERATION

Proceed with initial power-on checkout by

11.9.1

entering and executing the program listed in

Paper tape systems include no mass storage devices

General

and programs must be read into system memory prior

Paragraph 11.8.4.

to system operation. Programs are read from punched

11.8.4

ASCII Character Console Printout Program

The following is a program that can be used to printout

paper tapes using either an optional low-speed reader,
such as the LT-33 Teletypewriter, or a high-speed

ASCII characters. The successful completion of this

reader

program can be used as a guide in determining the

operations is:

(user-supplied).

The

normal

sequence

correct operation of the following:
KD11-F or -J Processor

DLV11 Serial Line Unit

Loadthe Absolute Loader

Load program tapes

Execute the program

LSI-11 data transfer and data control bus signals
Power input connections for +12V and +35V

This program does not explicitly check the following
bus signals.

BDMRL

BHALTL

BPOK H

BIRQL

BDMGI/OL

BDCOK H

BEVNTL

BIAKI/OL

11.9.2

References

Various paper tape software options are available for

PDP-11 users. Refer to the following publication for
program descriptions and operating instructions:
PDP-11

BSACKL

Paper

Tape Software Programming

Handbook (DEC-11-XPTSA-B-D).

The above manual can be ordered as directed at the
rear of this manual.

11-12

Address/Instruction
Starting Address

001000/105737

Mnemonic
TSTB @ #177564

001002/177564

001004/100375

BPL. -4

001006/110037

MOVB RO, @ #177566

001010/177566

001012/005200

INCRO

001014/000137

JIMP @ #1000

001016/001000

1003G 1"#3%&"()%k+,~-e/0123456789:3<=>?20ABCDEFGHIJKLMNOPQRSE
1" #SR& ' ()*+,-./8123456789:;5<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ(\]t~@ABCDEFB
1V #3R&° () *+,-./3123456789:3<=>?28ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]*~@ABCDEFS
1" #82&7()%+,-./0123456789:5<=>20ABCDEFGHIJKLMNOPQRSTUVWXYZ{\]t~@ABCDEFS
1" #82&°()%+,-./012345678933<=>?0ABCDEFGHIJKLMNOPQRSTUVWXYZ(\]*+~@ABCLEFE

Figure 11-18

11.9.3

Sample Console Printout

Loading the Absolute Loader

The Absolute Loader program tape is loaded using the

Enable the tape reader as follows:
LT33 Teletypewriter

Bootstrap Loader which is resident in the processor’s

microcode. The Bootstrap Loader is executed via the

LINE position.

below:

b.
1.

Enter the Halt mode

Placethe START/STOP/FREE switch
in the START position.

PDP-11/03 — Place the HALT/ENABLE

High-Speed Reader — Turn the reader on

switch in the HALT position. The console

and place ‘“‘on line”’, as appropriate for the

device prints the @ prompt character.

type of reader being used.

LSI-11 — Since LSI-11 systems are com-

Enter the reader’s CSR address by typing

pletely user-configured, the HALT mode

thevalueon the console device. For example,

can be entered via one or more of the follow-

if the console device includes a paper tape

ing means:

Enable the low-speed reader by placing
the LINE/OFF/LOCAL switch in the

Halt mode and console ODT commands as directed

reader (such as the LT33 low-speed reader),

Momentarily place the user-supplied

type:

HALT/ENABLE switch in the HALT

@ 177560

position; return the switch to the ENABLE position.
b.

Press the BREAK key on the console

NOTE

device (FEH jumper must be installed

In the above example, and all examples

in the console SLU interface module).

which follow, characters

printed

ODT are shown underlined. Charac-

Initialize the processor by momentarily

ters entered by the operator are shown

negating BDCOK H (processor module

not underlined.

jumper WS must be installed and W6
removed).
Place the Absolute Loader tape (DEC-11-

The value 177560 is the console device's

UABLB-A-PO) in the paper tape reader.

CSR.

Note that a long portion of the tape is

Load the Absolute Loader tape by typing L

punched with the octal value 351 (Channels

immediately after the reader device’s CSR.

8, 7, 6, 4, and 1 are punched); position the

The tape will automatically be read followed

tape so that any of those characters is lo-

by printing the Absolute Loader’s starting

cated over the reader head.

11-13

RXV11 hardware includes the RX01 single or dual

11.10.3.2

floppy

or REV11-C — The

disk

drive,

M7946

interface

module,

and

Booting The System Using The REV11-A

REV11-A or REVI11-C im-

BCOSL-15 interface cable. Models are available for

plements the RXV11 bootstrap (and other bootstrap

115 V, 60 Hz and 230 V, 50 Hz operation.

programs) in four pre-programmed ROM chips. When
system power is applied, and LSI-11 processor Mode 2

RT-11 software is described in four publications:

power-up sequence is configured on the processor
module, the system responds with a dollar sign ($) on a

RT-11

System

Reference

Manual

(DEC-11-

ORUGA-C-DN2)

device to be bootstrapped. DX (or DXO0) is disk drive 0;

RT-11 System Generation Manual (DEC-11-

ORGMA-A-D)
RT-11

new line. The operator then responds by typing the

DX1 is the second drive in dual drive RXV11 systems.
A normal sequence of operations from power up

through booting DXO0 is shown below:

Software

Support

Manual

(DEC-11-

Message

Manual

(DEC-11-

$DX

ORPGA-B-DN1)
RT-11

System

RT-11S]

V02C-XX

ORMEA-A-D).
Afterexecuting the DX0bootstrap, the system responds
Refer to those documents for RT-11 system software

by displaying the RT-11 monitor in use (RT-11SJ or

operation. Manuals can be ordered as directed at the

RT-11FB)

rear of this manual. The remainder of this discussion

(V02C-XX); the version is changed as RT-11 software

involves getting the PDP-11/03 or LSI-11

system

changes are implemented. Finally, a dot is displayed

running and responding to RT-11 Keyboard Monitor

on the next line, indicating that the RT-11 Keyboard

and

the

particular

version

use

Monitor is ready to accept a command. The system is

commands.

correctly booted and RT-11 programs can be executed
11.10.2

Using the RX01

as desired.

The RXO01 contains no operator controls or indicators
other than the load door(s) on the front panel. The left
drive on dual drive models is named DXO0 and the right
drive 1s DX1. Load the RT-11 diskette in the left (or

only) drive: this drive (DXO0) is called the SYStem

11.10.3.3 Booting The System Via The Console Device — When the REV11-A or REV11-C option is not
included in the system, the operator must enter a bootstrap program via the console device. Place the processor in the Halt mode and proceed as shown below; ob-

devicein RT-11 software.

serve that underlined characters are printed by the
processor and non-underlined characters are entered

NOTE

RT-11 can be bootstrapped and run on DX1 if

by the operator:

DXO0 is inoperative.

@1000/000000 12702 <{LF)
001002/000000 1002n7 {LF>*

001004/000000 12701 <LF)

Additional details for the RX01 drive are included in

001006/000000 177170 (LF

the RX8/RX11 Floppy Disk System Maintenance

001010/000000 130211 <{LF)

Manual (EK-RX01-MM-PRE2). That manual covers

001012/000000 1776 {LF)
001014/000000 112703 (LF

hardware used with PDP8 and other PDP-11 systems.

001016/000000 7 <LF)

However, the RX11/RXO01 interface is identical to the

001020/000000 10100 {LF)

001022/000000 10220 (LF)

RXV11/RX01 interface, and the RX11 and RXV11

001024/000000 402 (LF)

are software compatible.

001026/000000 12710 (LF)

001030/000000 1 <LF>
001032/000000 6203 <LF>

11.10.3

RXV11 Bootstrap

001034/000000 103402 {LF
001036/000000 112711 <{LF)
001040/000000 111023 (LF

11.10.3.1

General — The RXV11 bootstrap loader

001042/000000 30211 (LF)

program loads the RT-11 monitor from disk into sys-

001046/000000 100756 ILF

001044/000000 1776 <(LF>

tem memory. No RT-11 operation can occur until the

001050/000000 103766 (LF)

monitor is contained in system memory. Bootstrapping
(“booting’’) the system can be accomplished via a

*n=4 for Unit 0

001052/000000 105711 {LF

n=6 for Unit 1

001054/000000 100771 {LF)

(LF)=Line Feed
(CR)=Carriage Return

hardware-implemented bootstrap in the REV11-A or

001056/000000 5000 {LF

001060/000000 22710 <LF)
001062/000000 240 <LF)

REV11-C option, or it can be entered and executed via

001064/000000 1347 (LF)
001066/000000 122702 {LF

the console device.

001070/000000 247 (LF)
001072/000000 5500 <LF)
001074/000000 5007 (CR)

11-16

The bootstrap program can be started at location 1000.

Enable the Run mode by placing the HALT/ENABLE

switch (on the PDP-11/03 panel, or an equivalent
LSI-11 switch) in the ENABLE position. Start the
program using the Go command as follows:

CAUTION

1. A temporary loss of power will abort RT-11
operation and the LSI-11 processor will power-

up through the selected mode. RT-11 must be
restarted. If the REV11-A or REV11-C option

is used, the console device will display $ and
the system waits for the operator to specify the

@ 1000G
After a few seconds the RT-11 monitor will be loaded in
system memory. The monitor will identify itself on the

console device by typing a message, such as: RT-11S]
V02X-XX. This prin.out is followed by the Keyboard

Monitor prompt character (.) printed on the next line.

desired bootstrap (DX). If the REV11-A or
REV11-Cis not used, enter the bootstrap program and start at location 1000.

. Halting the processor will cause the processor
to abort RT-11 operation. When the processor
halts it prints the address (PC) on the console
device, followed by the prompt character @ .

11.10.4 Using the RT-11

RT-11 operation can continue by typing P. If

Requests for the desired RT-11 modules are always

desired, the system can be rebooted as pre-

entered from the Keyboard Monitor. When executing

viously described.

a system program, cotirol is normally returned to the

Keyboard Monitor. The Keyboard Monitor can be

entered at any time by simultaneously typing CTRL C
keys.

11-17

VId

(Saul[ QT X

1-1S71[esdydudsuondQ
25004 '11A1d

-wo)

IS8

)

12-2

APPENDIX A
MEMORY MAP

RESERVED VECTORLOCATIONS
000

(RESERVED)

004

TIMEOUT & OTHER ERRORS

010

ILLEGAL & RESERVED INSTRUCTION

014

BPTINSTRUCTION AND T BIT

020

IOTINSTRUCTION

024

POWERFAIL

030

EMT INSTRUCTION

034

TRAPINSTRUCTION

060

CONSOLEINPUT DEVICE

064

CONSOLEOUTPUT DEVICE

100

EXTERNAL EVENT LINE INTERRUPT

244

FIS (OPTIONAL)

264

RXV11

RESERVED DEVICE ADDRESSES
165000

REV11 ROM ADDRESSES

165776

173000
REV11 ROM ADDRESSES

173776
177170

RXV11 (RXCS)

177172

RXV11 (RXDB)

177550

Eggl?)

HIGH-SPEED

(PPS)

PAPERTAPE

(PPB)

READER/PUNCH

177552

177554
177556

177560
177562

177564

177566

(RCSR)
(RBUF)

CONSOLE

(XCSR)

DEVICE

(XBUF)

REGISTERS

A-1

APPENDIX C
7-BIT ASCII CODE

Octal
Code

Char

Octal
Code

Char

Octal
Code

Char

000 | NUL

040

100

140

001 | SOH
002 | STX

041
042

!
“

101
102

A
B

141
142

a
b

003 | ETX
004 | EOT

043
044

#
$

103
104

C
D

143
144

00S | ENQ

054

10S

145

006 | ACK

046

106

146

007 | BEL

047

‘

107

147

010 | BS

0S50

(

110

150

011 | HT

051

)

111

151

012 | LF

052

112

152

013 | VT

053

113

153

014 | FF

054

’

114

154

015 | CR

055

115

155

016 | SO

056

116

156

017 | SI

057

117

157

020 | DLE

060

120

160

021 | DC1

061

121

161

022 | DC2

062

122

162

023 | DC3

063

123

163

024 | DC4

056

124

164

025 | NAK
026 | SYN

065
066

N}
6

125
126

U
\Y%

165
166

u
v

027 | ETB

067

127

167

030 | CAN

070

130

170

031

| EM

071

131

171

032 | SUB

072

132

172

033 | ESC

073

133

[

173

{

034 | FS
035 | GS

074
075

<
=

134
135

\
]or4

174
175

}

036 | RS

076

136

176

037 | US

077

137

— Or <«

177

DEL

Char

C-1

APPENDIX D

SUMMARY OF LSI-11 INSTRUCTIONS

WORD FORMAT

OPR dst

SINGLE OPERAND:
15

BINARY-OCTAL
REPRESENTATION

Mne-

monic

[
Name

Symbol ic

Description

R
(R)

auto-increment
auto-incr deferred

(R)+
« (R)+

(R) is operand [ex. R2=9%¢2]
(R) is address
(R) is adrs; (R) +(1 or 2)
(R) is adrs of adrs; (R) + 2

5
6
7

auto-decr deferred
index
index deferred

« —(R)
X(R)
@ X(R)

(R) — (1 or 2); is adrs
(R) — 2; (R) is adrs of adrs
R) + X is adrs
R) + X is adrs of adrs

0
1
2

auto-decrement

—(R)

o~
.

Mode

MODE

Op Code

#n
@ #A
A
@A

operand n follows instr
address A follows instr
instradrs + 4 + X is adrs
instr adrs + 4 -+ X is adrs of adrs

m 050DD
m 051DD
m 053DD

clear
complement (1's)
increment
decrement

TST(B)

m 057DD

test

m 052DD

NEG(B)

m 054DD

ROR(B)
ROL(B)

d—1

0100
0 1
*
*
* -

rotate right
rotate left
arith shift right
arith shift left
swap bytes

-Cc,d
Cde
d/2
2d

*~
*
*
*
*
oo
o
o
00

add carry
subtract carry
sign extend

d+Cc
d-—-¢c
oor—1

=~
*
-

negate (2's:
compl)

0
- d

d-+1
—d

m 060DD
m 061DD
m 062DD
m 063DD
0003DD

m 055DD
m 056DD
0067DD

MFPS

1067DD

MTPS

1064SS

Operations

=0 for word/1 for byte

(

= destination field
(6 bits)
= gen register (3 bits),

OPR src, dst

BRS

= contents of register

Mnemonic

OFR src, R or OPR R, dst

oF £ODE

R
9

= contents of source

= contents of destination

7
*
-

12
~

) = contents of

*
*
0

move byte from
P
S
move byte to PS

Lo |
Op Codes

*
*
*

Processor Status (PS) Operators

= source field (6 bits)

Rotate & Shift

DOUBLE OPERAND:

LEGEND

SS
DD

dstResuit

CLR(B)
COM(B)
INC(B)
DEC(B)

ADC(B)
SBC(B)
SXT
immediate
absolute
relative
relative deferred

Instruction

Multiple Precision

PROGRAM COUNTER ADDRESSING

6
7

Ss Ok DO

General

ASR(B)
ASL(B)
SWAB

2
3

. N 1 “ - 1 . " 1 . N J

oP ~00E

[

| N R

SS OR DD

RN . 1

. T

Op Code

Instruction

Operation

m 1SSDD
m 2S5SDD
06SSDD
16SSDD

move
compare
add
subtract

des
s—d
des+d
ded—s

0 oror o
e
ror o

m 3SSDD
= 4SSDD
m 5SSDD
074RDD

bit test (AND)
bit clear
bit set (OR)
exclusive OR

Oto7

XXX = offset (8 bits),
+127 to —128
N
= number (3 bits)
NN = number (6 bits)

— becomes

X
%

= relative address
= register definition

Boolean

Condition Codes

V
*
—

= AND

= inclusive OR
= exclusive OR
= NOT

—
0
1

= conditionally set/cleared

= not affected
= cleared
= set

General
MOV(B)
CMP(B)
ADD
suB
Logical

BIT(B)
BIC(B)
BIS(B)
XOR

s Ad
de(—s)ad
desvd
d «rvd

*r
* *
*r
*

0
0
0
0

Optional EIS

JUMP & SUBROUTINE

MUL
Div
ASH

070RSS
071RSS
072RSS

ASHC

073RSS

multiply
divide
shift

arithmetically
arith shift

floating add
floating subtract
floating multiply
floating divide

BRANCH: B - - location

07500R
07501R
07502R
07503R

[
L

combined

Optional FIS

FADD
FSUB
FMUL
FDIV

rerxs
r < r/s

Instruction

Notes

0001DD
004RDD

jump
jump to subroutine

PC « dst

MARK

0064NN

mark

00020R

SOB

return from

subroutine

077RNN

} use same R
aid in subr return

subtract 1 & br

(R) — 1, then if (R) # 0:

(if #£ 0)

PC « Updated PC —
(2 x NN)

TRAP & INTERRUPT:

Mne-

If condition is satisfied:

monic

Op Code

Instruction

Notes

New PC « Updated PC + (2 x offset)

EMT

104000

emulator trap

PC at 30, PS at 32

adrs of br instr -2

TRAP

104400

trap

PC at 34, PS at 36

BPT

000003

breakpoint trap

PC at 14, PS at 16

10T

000004

input/output trap

PC at 20, PS at 22

RTI

000002

return from interrupt

RTT

000006

return from interrupt

Branch to location,

1
L R

Op Code

JMP
JSR

RTS

**
00
00
00
**
00

Mnemonic

fg",

—

0
o

to 104377

(not for general use)

to 104777

inhibit T bit trap

Op Code = Base Code + XXX

Mnemonic

MISCELLANEOUS:
Base Code

Instruction

Branch Condition

Mnemonic
HALT

Branches
BR
BNE
BEQ
BPL
BMI
BVC
BVS

000400
001000
001400
100000
100400
102000
102400

branch (unconditional)
br if not equal (to 0)
br if equal (to 0)
branch if plus
branch it minus
br if overflow is clear
br if overflow is set

BCS

103400

br if carry is set

BCC

103000

equal (to 0)

BLT

002400

BLE

003400 br if less or
equal (to 0)

003000

(always)
* 0
— 0
+
—

br if carry is clear

Signed Conditional Branches
BGE 002000 br if greater or
BGT

br if less than (0)

br if greater than (0)

Z=0
Z=1
N=20
N =1
V=0
V=1

C=0

BLOS

101000

branch if higher

101400 branch if lower
or same

NOP

000240

(

“

OF “COE BASE 000240
(S GO S

—

NV =

Mnemonic

Zv(N+V)=0

Zv(N+V)=1

CLC
CcLv

CvZ=0

CvZ=1

103000 branch if higher

C=0

BLO

103400 branch if lower

C=1

wait for interrupt

reset external bus

(no operation)

50412

R lfiv fi‘ q

— —

0 = CLEAR SELECTED COND. CODE BITS
1= SET!SELECTED COND. CODE BITS
000241
000242

Instruction

- - =0
- - 0 -

clear N

clear Z

CCC

000257

clear all cc bits

000250

SEC

000261

SEZ

000264

SCC

000277

SEN

N ZVCZC

clear C
clear V

000244

SEV

D-2

Op Code

CLZ

CLN

halt

000005

Nv+V =0

BHIS

or same

000001

CONDITION CODE OPERATORS:

C=1

Instruction

000000

WAIT

RESET

Unsigned Conditional Branches
BHI

Op Code

00O

set C

set Z

-1

000262

set V

000270

set N

set all cc bits

-1

PROCESSOR STATUS WORD

NUMERICAL OP CODE LIST

G
41

CARRY
OVERFLOW

OP Code

Mnemonic

OP Code

00 00 00
00 00 01

HALT
WAIT

00 60 DD
00 61 DD

00 00 02
00 00 03
00 00 04
00 00 05
00 00 06
00 00 07 }

RTI
BPT
10T
RESET
RTT
(unused)

00 01 DD

JMP
RTS

00 00 77

ZERO

NEGATIVE

00 02 OR

TRACE TRAP

00 02 10

PRIORITY

00 02 27

| (reserved)

00 02 40

NOP

00 02 41

Icond

J codes

00 02 77
POWERS OF 2

0
1
2
3
4
5

1
2
4
8
16
32

10
11
12
13
14
15

1,024
2,048
4,096
8,192
16,384
32,768

128

8
9

256
512

ABSOLUTE

65,536
131,072

18
19

262,144
524,288

ROR
ROL

00 62 DD
00 63 DD
00 64 NN
00 67 DD
00 70 00

ASR
ASL
MARK
SXT

10 44 00
I

00 77 77

CLRB

10 54 DD

10 55 DD

ADCB

ADD

10 57 DD

TSTB

MUL
DIV

10 60 DD
10 61 DD

RORB
ROLB

10 63 DD

ASLB

o4 55 DD

BIC

06 SS DD

10 53 DD

BIS

10 56 DD

ASH

07 3R SS

ASHC

07 4R DD

XOR

SWAB

00
00
00
00
00

XXX
XXX
XXX
XXX
XXX

BR
BNE
BEQ
BGE
BLT

00 34 XXX

BLE

07 67 77

(unused)

00 4R DD

JSR

07 7R NN

SOB

00 50
00 51
00 52
00 53
00 54
00 55
00 56
00 57

CLR
COM
INC
DEC
NEG
ADC
SBC
TST

10 00 XXX
10 04 XXX
10 10 XXX

BPL
BMI
BHI

00 30 XXX BGT
DD
DD
DD

DD
DD
DD
DD
DD

FADD

FSUB

FMUL
FDIV

12
13
14
15
16

07 50 40

BLOS
BVC
BVS
BCC,
BHIS

10 34 XXX

BCS,
BLO

SBCB

10 64 SS

07 50 2R
07 50 3R

10 14 XXX

NEGB

10 67 DD

07 50 1R

10 20 XXX
10 24 XXX
10 30 XXX

DECB

10 62 DD ASRB

00 03 DD
04
10
14
20
24

TRAP

COMB
INCB

MOV
(E_‘;ll\{er

07 50 OR

10 50 DD

07 2R SS

10 51 DD
10 52 DD

01 SS DD
02 gg BB

07 OR SS
07 1R SS

EMT

10 43 77

}(unused) 10 47 77

05 SS DD

Mnemonic

10 40 00
0

SS
SS
SS
SS
SS
SS

DD
DD
DD
DD
DD
DD

BOOTSTRAP LOADER

LOADER

Starting

Address: — 500

Memory Size:
4K

8K
12K
16K
20K
24K
28K

16
17

Mnemonic OP Code

037
057
077
117
137
157

Address

Contents|Address

— 744

016

701

|— 764

Contents
000

002

— 746

000

026

|— 766

— 750

—

400

012

702

— 752
— 754
— 756
— 760
— 762

|— 770

000
005
105

352
211
711

005

|— 772
}|— 774
|— 776

267

177
000
177

756
765
560 (TTY)

100
116

376
162

TRAP VECTORS
000
004
010
014
020

D-3

(reserved)
Time Out & other errors
illegal & reserved instr
BPT instruction

IOT instruction

024
030
034
244

Power Fail
EMT instruction
TRAP instruction
FIS (optional)

ODT COMMANDS
Format

Description

RETURN

Close opened l|location and accept next command.

LINE FEED

Close current |ocation; open next sequential
location.

T
«

Open previous location.
Take contents of opened location, index by contents of PC, and open that location.

Take contents o’ opened location as absolute
address and open that location.

Open the word at location r.

Reopen the last location.

$n/or Rn/

Open general register n (0-7) or S (PS register).

r;GorrG

Go to location r and start program.

Execute bootstrap loader using n as device CSR.
Console device address is 177560.

PorP

Proceed with program execution.

RUBOUT

Erases previous numeric character.
Response is a backslash (\).

D-4

APPENDIX E

H9270 BACKPLANE CONFIGURATIONS
E.1

BASICDAISY CHAIN GRANT PRIORITY

HIGHEST

PRIORITY

(
AN

—

]

LOWEST

PRIORITY

!
R

Note:
Arrow indicates BDMG and BIAK daisy chain signal routing from
highest priority device slot to lowest priority device slot on the
backplane.

E.2

TWO BACKPLANE CONFIGURATION
'

PROCESSOR MODULE

OPTION 2

—

OPTION 1
FIRST

OPTION 3

BACKPLANE

OPTION 4

250 2 TERMINATOR/

CABLE CONNECTOR (1)

OPTION 5

/l\ 41\
EXPANSION

CABLES (1)

CABLE CONNECTOR (1)

OPTION 6

OPTION 8

OPTION 7

OPTION 9

OPTION 10

120 2 TERMINATOR/

OPTION 11

SECOND
BACKPLANE

CABLE CONNECTOR (2)
Notes:

1. Included in BCV 1B bus expansion option. (Cables are available

in 2,4, 6, or 12 ft. lengths.)
2. Included in TEV11 bus terminator option.

CP-2047

E.3

THREE BACKPLANE CONFIGURATION

PROCESSOR MODULE

—>

OPTION 2

OPTION 1
FIRST

OPTION 3

OPTION 4

250 2 TERMINATOR/

CABLE CONNECTOR (1)

BACKPLANE

OPTION 5

EXPANSION

CABLES (1)

\L N
» T Y

CABLE CONNECTOR (1)

OPTION 6

OPTION 8

OPTION 7

OPTION 9

OPTION 10

CABLE CONNECTOR (2)

OPTION 11

SECOND

BACKPLANE

N\ /lh
EXPANSION

CABLES (2)

n 1 Y
CABLE CONNECTOR (2)

OPTION 12

OPTION 14

OPTION 13

OPTION 15

OPTION 16 (4)

120 Q TERMINATION (3)

OPTION 17 (4)

THIRD

BACKPLANE

Notes:

1. Included in BCV 1B bus expansion option. (Cables are available
in 2, 4, 6, or 12 ft. lengths.)

2. Included in BCV 1A bus expansion option. (Cables are available
in 2, 4,6, or 12 ft. lengths.)
3. Included in TEV 11 bus terminator option.

4. The LSI111 Bus is restricted to 15 options, maximum. These

option slots would only be used when previous option(s)
occupy more than 1 option location.
cCpP-2048

E-2

APPENDIXF

BUS INTERFACEI.C. PINS

F.1

DEC8640 QUAD 2-INPUT NOR GATES
(Bus Receiver)
14

Vee
8

[1 1 111
r1T0]

CP-12714

F.2

DECS8881 QUAD2-INPUT NAND GATE
(Bus Driver)
Vee
14

alinlinln)

EpEpapupepEgn
CP-1272

F.3

DEC8641 QUAD UNIFIED BUS TRANSCEIVER
(Bus Receiver/Driver)
1

BUS
1 —
»

Vce

DATA IN1 ——

BUS 4

DATA OUT 1 2
BUS 2 -3
DATA IN 2 2
DATA OUT 28

ENABLE A —

GROUND °

|°
(

;
ENABLE A

_—

—

DATAINI 2

DATA IN 4
paTA OUT 4
BUS 3
DATAIN3
pataouT3

ENABLE B

1
BUS

\\_/’

DATA OUT

ENABLE B
ONE

OF FOUR
1C 0089

F-1

APPENDIX G

LSI-11 BUS ACCESSORY OPTIONS
INSTALLATION AND OPERATION

G.1

INTRODUCTION

G.1.1

General

Several

LSI-11

bus

termination,

combinations
and

bus

PDP-11/03

accessory

DMA

the

options

refresh,

available

bootstrap

preceding.

applications.

are

The

bus

read-only-memory

options

summary

for

can

the

used

options

expansion,

(ROM),

and

both

LSI-11

1is

provided

below:

Option

No.

REV11-A

Includes

M9400-YA

Module

System

120,

bus

Functions

terminator,

bootstrap

DMA

refresh,

ROM.

REV11-C

M9400-YC

Module

DAM

refresh,

bootstrap

REV11-H

M9400-YH

Module

DMA

refresh,

communication

bootstrap

TEV 11

M9400-YB

BCV1A-XX

Two

BCOS5L-XX

cables,
M9400~-YD

and

Module

one

module

one
module,

M9401

120;..bus

ROM.

terminator.

Bus

expansion:

and

two

and

TEV11

stalled

expansion

connector

M9401).

expansion

backplane

two

backplane

(M9400-YD

for

ROM.

from

Normally

second

3-backplane

120 terminator
in

backplane

the
3.)

last

cables

modules

used

third

systems.

must

device

slot

inin

NOTE

The

-XX

denotes

BCV1A-XX

cable

with

cable

For

example,

and

lengths.

lengths
a

BCV1B-XX

options

Options
2,

BCV1A-06

are
and

includes

available
10

two

feet.
6-ft.

cables.

Option

Includes

BCV1B-XX

Two

System

BCO5L-XX

cables,
M9400-YE

and one
module.

Bus

one

backplane

M9401

Normally
first to
3

G.1.2

general

paragraph

Dimensions
in.

obtained

G.1.3

The

specifications
2.9

from

also

all

Power

expansion

connector

cables,

(M9401).

used for expansion from
second backplane in 2 or

backplane

systems.

(electrical

apply

modules

the

particular

are

environmental)

options

associated

requirements

the

and

described

with

listed

backplane

these

below.

options
Note

which

that

module

included

this

are

section.

power

8.5

configuring

LSI-11,

and

using

PDP-11/03

LSI-11

and

LSI-11,

PDP-11/03

Processor

LSI-11,

PDP-11/03

Configuration

Installation

publications

PDP-11/03

Handbook
and

are

available

installed.

060/-09/02

EK-LSI1T1-IN-001

Guide

PDP-11/03

User's

Manual

G-2

for

systems:

04870

EK-LSI11-TM-002

1is

References

following

LSI-11,

250¢« terminator

two

Specifications

The

0.5

expansion:

(M9400-YE),

module,

Functions

Table

Option

Power

G-1

Requirements

Option

+5vEsg

Designation

Typ

REV11-A

1.64

REV11-C

1.0

REV11-H

1.0

TEV11

0.54

Max

2.24

1.88

0.70

BCV1A-XX:

M9400-YD

M9401

BCV1B:

G.2

0.29

M94 01

0.37

DESCRIPTION

G.2.1

The
of

M9400-YE

General

options
the

the
each

M9400

various

figures

this

module.

including

options

include

position

described

within

are

simple
a

factory

block

system,

provided.

section

generally

selected

produced.

diagram

the

appropriate.

involve

components

Figures

G-1

options,
A

list

and

variations
and

jumpers,

through

G-6

functional

options

and

Figure

Detailed
are

G-1

REV11-A

G-2

REV11-C

G-3

REV11-H

G-4

TEV 11

G-5

BCV1A-XX

G-6

BCV1B-XX

descriptions

contained

the

functions

following

Two types
signal

line

terminations
termination

Termination

includes

resistors

are

packages

which

ages.

package

contains

Each

shown

minated

the

resistor

and

connected

that

within

these

figures

paragraphs.

are provided:

dual-inline

are

contained

Terminations

G.2.2

G-7.

Option

the

figure.

jumpered;

120

BDMGO

and

values

approximately

via

shown,
and

resistors

Figure

16-pin

physically

identical

I.C.

terminations.

jumpered

actual
,

shown
in

grant

values

The

are

termination

respectively.

values

signals

BIAKO

factory-installed

2225

Each bus

contained

termination
the

250fL.

generally

Daisy-chained

BIAKI

250/L

124,

are

two

120J4Lland

are

and

jumper

values

used

ter-

BDMGI

(W1).

nominal;

pack-

Note

with

will

1is

the

MS400-YA

LSI-11 BUS

12082 BUS
TERMINATION

DMA REFRESH

BOOTSTRAP ROM

11-3594

G-1

Figure

REV11-A

Functions

M9400-YC

LSI-11

BUS

BOOTSTRAP

ROM

DMA REFRESH

11-3595

Figure

G-2

REV11-C Functions

G-5

DMA REFRESH

LSI-11BUS

M39400-YH

COMMUNICATIONS
BOOTSTRAP ROM

11-3596

<::LSI—H BUS i:}

Figure G-3

REV11-H Functions

M9400-YB
1202 BUS
TERMINATION

11-3597

Figure G-4

TEV11 Functions

A(\>

—

SECOND
BACKPLANE

imqiiye

M9400 - YE

J1
J2

BATKPLA

[M940'

BCOS5L — XX

BCO5L—XX

{2]

%]9

1 2]

250 Q BUS

| 27\|

TERMINATION

]

| < |
L
|

BCVIB—XXAEbMPONENTS
11-3598

Figure

G-5

SECOND
BACKPLANE

| ‘(A\>
|

]

M9401

BCOSL —XX

BCOSL _— XX

BN J2

| \) |
L

Functions

M9400 — YD

.
:

BCV1B

——

BCVITA—-XX COMPONENTS
11-3599

Figure

G-6

BCV1A

Fun ctions

+5Vv

<21809
TO/FROM
SIGNAL LINE

3300
TO/FROM
SIGNAL LINE

3900

TYPICAL

6800

1208

TYPICAL

TERMINATION

2508

TERMINATION
11-3600

Figure

DALY

G-7

Bus

Terminations

DALIO H
DAL{1 L

DAL12 H

FROM BUSJ BS7 H

+oV

RECEIVERS

REF H

173 XXX ,0R
165 XXX

SYNC H

+5v

MY BANK

ADDRESS

o COMPARATOR

}—

DIN H FROM

BUS RECEIVERj'—J

Jo——
=——
BRPLY L

f
=

MASTER (1) H

MY ENABLE L

FROM DMA

REFRESH
CKT

9-BIT

(DAL1-8,1O H

ADDRESS
LATCH

BA1-8,10 H

FROM BUSJ

512-WORD
1-CHIP

BOOTSTRAP | O-15 H
ROM
ARRAY

BDAL

BUS

DRIVERS

BDAL O-15 L

RECEIVERS

SYNC H

?
FROM DMA

BDCOK H —CD—FDO_—_—’ BD INIT L

REFRESH ckT REF 1-6 H

—» BD INIT H
11-3601

Figure

G-8

Bootstrap

ROM

Logic

G.2.3

Bootstrap

G.2.3.1

General

REV11-A,

REV11-C,

respective
Bootstrap

the

are

Bootstrap

ROM

contained

are

the

addressed
for

normally

addresses

used
from

cause

which

will

upon

power

two

M9400-YH

the

module

functions

and

functions

segments.

16-bit

These

peripheral

device

addresses.

the

processor

selectable

bootstrap

ROM

access

upper

the

ROM

KD11-F

contained

array

segments

address

The

reserved

power-up

location
or

below.

ROM

address

173000-173776.

are

described

reside

and

ROMs

programs

are

the

their

identical.

REV11-C

512

are

and

165000-165776

jumper

1included

bootstrap

includes

256-word

modules

REV11-A

Logic

options

for

range

mode

and

logic
Logic

communications

The

REV11

loader

options.

different.

Addressing

reserved

REV11-H
M9400-YC,

However,

REV11-H

bank,

Logic

and

programs

G.2.3.2

which

Loader

M9400-YA,

identical.
in

ROM

KD11-J

173000
processor

module.

Circuits
Wired

associated

inputs

dresses.

The

addresses

during

active
BRPLY

BANK

inputs.

with

address

BANK

signal

also

the

comparator

comparator
addressing

signal.

when

the

inverted

ROM

and

logic
circuit

responds
portion

BANK

word

applied

are

shown

reserve

any

bus

I/O

ANDed

read

the

ROM

with

the

Figure

the

ROM

ad-

reserved

cycle

generating

DIN

produce

processor.

array

G-8.

chip

enable

DALI-8

and

DAL10

latch

the

leading-edge

address

bits

the

256-word

two

G.2.3.3
cycle

able

four

512

then

strap

logic

ROM

BDAL

bus

16-bit
the

I/O

receives

BDCOKH

goes

produces

signals

0-15

Note

I.C.'s.

data,

clear

the

that

the

BRPLY

ROM

and

comparator.

the

bus

avail-

array

4-bit

BA10

within

strobes

DIN

BDIN

address

becomes

four

ENABLE

terminates

read

portion
data

address

Hence,

terminating

active

the

bus

BINIT

signal.

Refresh

G.2.4.1

General

functions

shown
every

in
30

bootstrap

This
BD

9-bit

LSI-11

The

false.

logic.

once

ROM

response

refresh

bus

the

9-bit

BA1-8

addressing

bus

DMA

detected

the

stored

location

word.

the

G.2.4

word

outthe

signal.
and

the

The
boot-

inhibiting

drivers.

only

These

The

LSI-11

the

responds

Initialization

and

inputs.

4-bit

G.2.3.4

when

SYNC

completed,

driver

onto

stored

After

bus

the

are

segment

BDAL

word

failure

bits

desired

address

been

processor

the

Transfer

has

comprise

16-bit

address

the

consists
puts

select

Data

DATI

ROM

condition

INIT

and

address

latch

option

does

The

logic

initialized

occurs

during

INIT

signals.

and
not

circuits
respond

power

contained

the

Logic

DMA

refresh

Figure
usec.

G-9.

logic

consists

Arbitration

(approx.)

and

G-10

logic

completes

the

three

requests

the

main

the

required

I/O

DMA

BDOMR L

BD INITH

_|ARBITRATION

BSACK L

LOGIC

BOMGI L
BOMGO L

oAT
d %| -~

Ojx|_ |-l

Qlcn m| 2|

Ol Ol o N

O
s| | Slg|

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BD INITH

BREF L

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BDIN L

LOGIC

BRPLY L

[T
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alaldi <

ol o zlzl

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<}DJ BDCOK H
11-3602

Figure

G-9

DMA

Refresh

G-11

Logic

signal
it

enables

BSYNC
in

sequence

fresh

the

bus

transaction

dynamic

MOS

memory

BDAL

cycle.

1-6

logic

lines

Once

the

incremented

for

released

for

dynamic
DMA

one

MOS

contained
period

for

row

the

(i.e.,

execute

contained

memory

addressing

the

refresh

takes

system

within

rows

usec

Logic

the

"row"

row

The

re-

address

the

I/O

address

1is

cycle,

and

the

bus

actual

1.2

refresh

usec.

addresses.
all

required

between

msec

trans-

Each

Hence,

dynamic

refresh

I/0O

bus

row

refreshing
the

one

system.

chip

The

row

master,

refresh

refreshing

approximately

bus

the

operations.

contains

single

portion

completed,

capable

been

chip

becomes

simultaneously

has

address

1is

When

six-bit

the

non-refresh

logic

places

cycle

one

logic

chips

during

memory

refresh

1.92

processor.

control

address

action

the

bus

L/BDIN

all

with

the

MOS

memory

(maximum)

bus

cycles

msec).

G.2.4.2
Figure

Arbitration
G-10;

timing

sequence

GRAB

BUS

with

ground

(enable)

W2,

produce

the

nals.

the

The

processor

ducing the

G-11.

usec

signal.

signal,

supplied

via

signal.

DMGR H

signal.

Refresh

clocks

the

(1)

signal

when

G-12

DMA

and

leading

H
and

1in

refresh

oscillator.

inverted

request

The

shown

clock

DMA

received

The

R PENDING

the

BDMGI

REQ

active

arbitrates

daisy-chained

active

Figure

every

producing

completed.

logic

output

REQ H

state,

the

once

clock

set

serting
cycle

initiated

shown

Arbitration

and

gated

Disable

DMR

flip-flop

and

BDMR

responds

the present

bus

inverted,

pro-

this

edge

jumper

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Signal

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signal

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the

flop,

causing

and

MINE

(0)

the

BDMGO

the

When

that

the

MINE

(0)

cient

DMA

nsec.

requesting

the

G.2.4.3

Bus

initiated

when

DMG

DLYD

low

signal.

the

passes

signal

into

state.

SACK

the

flip-flop

DMR

active
become

for

(1)H

SACK

BSACK

has

BDMGI

signal

bus

(1)

the

and

high

inhibiting

also

signal

master,

SACK flip-

goes

turns

informs

and

the

DMA

enables

refresh

transaction,

the

its

continuity

maintained

the

insures

that

the

state,

I/O

bus.

generation

delay

set

bus

signals

requesting

the

The

DMA

output
to

the

(high)

BDMGO

flip-flop

the

active

delayed

SACK

BDMGO

has

refresh

signal.

suffi-

option

bus.

Control
the

Logic

The

arbitration
These

This

signal

produce

the

Master

goes

high

and

MASTER

(0)

producing

the

active

BREF

contained

bus

logic

signals

gated

MCLK

memories

the

bus

MCLK

MOS

completed.

device

the

(1)

respectively.

device

signals.

clocks

set

clearing

driver;

signal

time

signals

low,

the

logic,

bus
a

R PENDING

daisy-chained

priority

100

goes

lugic

lower

The

requesting

arbitration
that

sequence

not

signal

BSACK

processor
grant

active

low.

signal.

the

ANDed

passive

signal,

goes
L

asserts

are

with

flip-flop

control

system

G-15

logic
the

SACK

produce

SYNC

shown

the

set

Master
BREF
to

operation

and

causes

and
active

RPLY

Figure

state;

(1)

1is

G-12.

MASTER

(1)

i1s

inverted,

all

dynamic

simultaneously

addressed

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during

the

duration
the

"A"

refresh

the

bus

transaction,

refresh

sequence

and

operation.

flip-flop;

when

remains

MASTER

high,

(0)

active
when

logically

for

low,

clears

the

enables
the

flip-flop.

MASTER

(1)

the

ENABLE

and

row

The

sequence

applied

signal.

This

bits

placed

address

trolled
nized

signal,

edge

following

signal.

produce
set

preset

set,

state
and

low
on

signal

inputs

initially

memory

and

(1)

the

flip-flop

and

has

not

signals

set

nsec.

the

SCLK

signal,

circuit

low

the

completed.

this

G-17

leading

Master-Sync.

are

flip-flop

(Note
as

MASTER

that

the

clear

the

gated

discussion.)

The

transaction

Thus,

the

high

(0)

low

signal

goes

pre-

flip-flop

bus

typical

and

refresh

producing

RPLY

clock

signals

into

con-

synchro-

used

signal

active

(0)

are

the

logic

the

pulse.

been

the

220

and

since

until

the

SCLK

state

gated,

producing

high

are

control

sequence

clocking

drivers,

Operations

(1)

produces

bus.

clocks

this

bus

B.
edge

(1)H

which

BDAL

bus

G-11.

state,

SYNC

BDAL

where

the

and

MASTER

following

active

system

logic

enables

the

leading

set

signal

Figure

MASTER

respectively,

the

clear

considered

active

The

signal

flip-flops

shown

the

clocks

(1)

the

address

involving

positive-going

SCLK

flip-flop

are

refresh

operations

sequence

the

RPLY

which

low.

1is

RPLY (0)

with

(0)

keeps

The

low

SYNC
are

(0)
H

signal

signal.

gated

PRE

the

become

asserted.

the

SCLK

the

set

B(1)

signal

the

bus

driver,

high

and

A(1)

are

become

leading

low

memory

(1)

A(1)

terminating

prevents

that

low signal

sequence

B(1)

control

reply
and

low

inhibits

clocks

goes

low,

signal.

and

low

B(0)

clocks

signals.

driver,

causing

that

logic

remains

state

refresh

RPLY(0)

the

reset

this

transaction

the

On
to

signals

sequence

inhibiting

state

the

and

B(1)

which presets

the

sequence

long

the
are

preset

following

bus

are

produced.

the

asserting

set

flip-flop

BDIN

flip-flop

signal

bus

(1)

signal

flip-flop

RPLY

resetting the

PRE

bus

clocks

RPLY

flip-flop

that

flip-flop

high

the

(1)

RPLY

the

signal

MASTER

causing

BDIN

the

produce

producing

inverted,

SCLK

SCLK H pulse.

produce

and

the

Bus

responds

RPLY(0)

and

gated

asserted.

received

edge
and

active

the

active

and

producing

BRPLY

(0)

state,

and

BSYNC

the

BRPLY

gate,

SYNC

with

edge,

system

The

ORed

leading

until

state,

driver,

ANDed

flip-flop.

RPLY (1)

This

1in the

state.

System memory responds to the passive BDIN L signal by terminating

the BRPLY L signal.
clocks

the

reset

On the next SCLK L pulse,
state;

RPLY (1)

G-18

goes

the reply flip-flop

low and

RPLY(0)

H goes

high.

The

following

flip-flop

and

BSYNC

Low

the

state

the

passive

(1)

and

(low)

RCLR

signal

BSACK

clears

the

Master

G-12),

causing
address

BDAL

bus

goes

passive

BUS

(0)

the

goes

passive;

signals

which

signals

bus

sequence

passive

go
H

the

gated

PRE

high.

SYNC

passive,

refresh
before

the

Sack
L

also

the

re-

inhibiting
SYNC

flip-flop

and

Refresh

address

binary

counter

produces

refresh

enabling

the

(1)

transaction
next

the

(Figure
in

MASTER

bus

produce

RCLR

logic

ENABLE

pulse,

clears

control

and

SCLK

Done

are

G-10)

and

the

the.B

1is
bus

the

logic

shown

the

six

operation.

G-13.

Figure

bits

portion

Address
A

which

are

the

placed

bus

output

bits

counter

pleting

the

transaction,
the

counter

one

operation,

new

refresh

the

gate;

Logic

six-bit

enables

binary

(0)

G-13)

goes

clocks

states.

G-12),

resetting

B(1)

passive

(Figure

Refresh

the

then

(Figure

MINE

and

DONE

flip-flop

logic

G.2.4.4

address

and

BREF

GRAB

transaction,
refresh

drivers.

completed.

pulse

reset

flip-flop;

ing

PENDING

active

fresh

SCLK

row

goes

count.

address

BDAL

bus

transaction.
during

RPLY (1)

signal

the

goes

high,

Hence,

1is

used.

G-19

the

during

The

low

passive,

each

address-

MASTER

operation.

Upon

inhibiting

incrementing

the

successive

row

(0)
com-

the

six-bit

refresh

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G.2.4.5

Initialization

controlled
during

the

power-up

low

passive

are

initialized

BDCOK
INIT

H),
H)

G.3

BDCOK

G.3.1

(inverted

LSI-11

DMA

REV11-C,

BUS

and

Refresh
REV11-H

cessor-controlled

DMA

(when

(except

INIT

H),

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the

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OPTIONS

memory

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Figure

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G-14.

normally

provided

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DMA

refresh

used,

bus

cycles

installing

module.

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Removing

disables

done

systems

should

the

addition,
must

DMA

which

REV11-A,

wire-wrap
W2

refresh

bus

must

operation

system,

the

However,

have

the

option

the

highest

used.

REV11-C

can

any

other

no
be

DMA

the

DMA

other

LSI-11

posts

the

REV11

shown

cycles;

dynamic

backplane,

priority
DMA

devices

installed

devices

are

any

used

the
are

used

option

the

DMA

the

pro-

disabled.

installed

contain

the

MOS

devices.

installing

option

-YC,

When

refresh

processor

(M9400-YA,

refresh

options.

When

conditions

ACCESSORY

can

this

initialization

Initialization

flip-flops

the

logic

General

G.3.1.1

signal.

either
L

refresh

signals.

USING

This

All

INIT

DMA

power-down

state).

REV11

refresh
in

the

location.

system,

the

—1

N
O

—1

DMA
REFRESH
ENABLE

BEl

—\_T

E29

E25

E22

E19

BOOTSTRAP

ROM

ENABLE

(ALWAYS

INSTALLED)

11-3607

Figure

G-14

REV11-A,

-C,

-H

Jumpers

REV11
it

must

the

located

highest

operations
insure

DMA

ROM

REV11-H

options.

stalled

the

chips
The

REV11

Figure

devices

cycles

occur

Bootstrap

and

contained
ROMs

can

When

-YC,

removed,

when

~-YH

this

order

programs

REV11-C,

only

give

intervals.

diagnostic

accessed

transaction)

timely

REV11-A,

option(M9400-YA,

G-14.

order

DMA

refresh

contained

those

DMA

processor

the

burst

executed

Bootstrap

the

data

ROM

(multiple

not

that

priority;

must

G.3.1.2

shown

closest

are

and
W4

in-

module),

feature

dis-

abled.

The

normal

This
via

address
a

When

can

console

selected.

REV11-A

described

with

operating

manuals.

address

for

REV11

entered

and

program

command

entry
This

jumper

ODT

automatic

removing

use

starting

ROM

The

Laboratory

the

instructions

processor

contents

Data

are

either

power-up.
up

installing

identical,

(LDP)

included

173000.

started

during
power

mode

must

jumper

and

their

use

1is

module.

contains

Products

are

operation

processor

selected

REV11-H

programs

automatically

desired,

mode

REV11-C

below.

ROM

and

bootstrap

systems;

programs

hence,

appropriate

LPD

for

REV11-H
system

Starting
a

CPU

program

diagnostic

tions.

execution
program

Successful

the

console

device

the

prompt

character

-C

Unsuccessful

prompt

sults

error;

Once

one

the

console

the

command

the

halt

character,

causes

memory

dollar

user

which

program

sign

enter

execution

modifying

diagnostic

($).
a

specifies

diagnostic

the

instruc-

indicated

This symbol

two

character

the

three

desired

REV11-A

the

failure

re-

instructions

due

Halt

double

device

+2),

dis-

followed

Table

printed

can

command

program

results

console

the

displayed,

halts
the

responds

operator

Note

the

program

are

either

the

G-2.

underlined

program

invalid

address

characters

the

sequence

results

(the

not

program

Instead,

processor

described

characters

the

when

character

commands

non

printed.

the

normally

prompt

the

self"

ODT

the

being

contents

prompt

command

inputs

characters.

prompt

properly,

examples,

underlined;
Command

"branch

for

execution

bus

tests

173000

executed.

not

execute

the

character

not

playing

which

displaying

character

program

location

execution

alphanumeric

entered
be

upper

entered

that

can

1in

are

the

shown

operator.

the

lower

following

by displaying

enter

case

the

after

the

invalid
example,

command

and

program

new

response

prompt

the

character

invalid

"XJ"

new

command

line.

For

shown

below:

Table
REV11-A

and

REV11-C

Command
OD

G-2
ROM

Program

Commands

Function
ODT

(Halt).

and/or

This

alter

the

console

the

REV11

memory

program

console

device

the

start

the

has

not

and

the

ODT

and

altered,

the

operator

the

prompt

(Go)

displaying

the

commands

(Proceed)

altered,

entering

via

returned

the

examine

locations

can

been

display

execution

165006

operator

entering

has

will

the

Control

been

program

address

and

device.

command

allows

the

character.

can
starting

follows:

@165006G

s
The

processor

character

can

responds
a

entered.

new

line

and

another

the
REV11

prompt
command

Function

Command

XM<CRZ

Memory

Diagnostic

completing

the

($)

are

indicated

After

diagnostic,

displayed

console

program.

the

prompt

console

following

successfully
character

device.

displays

Errors

the

device:

173732

@
This

(normal)

address

data

desired,

tion

the

memory

test

and

location

continue

entering

error.

The

the

invalid

pointed

diagnostic
P

ODT

the

expected

data

RZ2.

program

execu-

command.

173756

e
This

1is

data

(normal)

test

the

R2.

desired,
by

stored

memory

data

execution

error.

diagnostic
ODT

invalid

the

pointed

location

the

expected

and

continue

entering

The

program

command.

000010

e
A

timeout

locations
memory.

trap

has

outside

occurred
of

the

testing

first

(lowest)

memory
4K

Function

Command
4.

nnnnnn

e
A

timeout

locations

has

within

nnnnnn

displayed

The

actual

memory

test

and

writes

all

data

reads

test

consists

first

which
of

and

two

the

parts.

The

not

various

word

all

1's.

program

are

results

by:

when

consists

all

the

memory

Successful

indicated

halts

G-27

This

halts

traps

through

displayed

correctly

program

1's"

data

0's"

being

program

"all

The

part

test.

The

addresses;

second

instruction

first

The

modifying

Errors

test

program.

device.

address

locations,

Diagnostic

($)

number,

memory

Processor

character

The

all

are

diagnostic

addresses.

which

the

with

memory.

address

locations

testing

indeterminate

The

through

"all

consists

verifies

first

locations

initially

walking

the

test.

walked

are

occurred

test

memory

then

XCLCR>

trap

memory-

execution

the

prompt

console

instruction

sequence

executed.

the

trap

vector

area

for

Function

Command

NOTE

When

mand

can

mode

was

invoked.

halt

the

used

determine

successfully

nostics,
should

(and

ALKCR?

occurs,
to

used

memory)

loading
a

how

the

system

execute

the

above

diagnostic

thoroughly

com-

the

halt

fails
diag-

programs

test

processor

functions.

Absolute

that

ODT

When

maintenance

console

Loader

program,

operation.

Entering

paper

tape

device

(CSR

address

device

can

priate

CSR

address.

to
=

absolute

whose

CSR

address

(absolute

AL<CR>

loaded

177560).

specified

tapes

normal

via

For

example,

loader

format

via

177550,

specifies
the

However,

entering

enter

address)

console
another

the

appro-

load

paper

device

the

following

command:

AL177550<<CR
>

The

program

responds

memory-modifying

CPU

first

instruction

test

(refer to

the XC

and

test

execution

results

lute

Loader

program.
G-28

executing

test

memory

and

commands).

execution of

the

Successful
the

Abso-

Function

Command

A
1.

successful
The

program

console

load

device

indicated when:

displays:

165626

Q
2.

The

loaded

program

automatically

starts

execution.

Absolute

loader

Checksum
and

errors

error,

producing

are:

with

the

program

following

halting

display:

165534

c]
2.

Program

traps
3.

AR<CR?>

other

Timeout

Absolute

tion.

halts

than

trap

new

modifying

this

CPU

automatically

timeout

trap.

causing

the

first

following

for

display

device.

relocated

entered,

test

executed
by

the

area

console

instruction

execution

€

vector

command

Successful

165412

trap

program,

followed

the

commands),

with

the

occurs,

line

Loader

When

the

(refer

Absolute

results

console

and

the

display:

opera-

the

memory-

memory

test

the

Loader
program

are

and

program.
halting

Command

Function

The

operator

must

then

"software

switch

relocated

select

dress

(bias)

The

R4/xxxxXxX

the

Tape

odd

(R4)

located

must

format

for

When

large

tape,

the

enter

loaded

tape.

this

below;

ad-

switch

the

value

the

PDP-11

Observe

entered

software

that

Paper

that

must

switch

selecting

Note

selected

the

re-

program

Independent

the

Code

being

(PIC)

are

halts

contained

second

using

R4/xxxxxxXx

value

Position

the

uses

commands:

relocation

mode.

program

R4.

<CR>

logical

programs

resume

sets

software

Handbook.

relocated

"1"

the

directed

"n"

Install

User's

significant

bit

appropriate

which

following

nnnnnn

operator

number;

number

the

nnnnnn

Software

least

contained

enter

value

enter

<CR>

the

end

tape

the

ODT

than

the

first

reader

command

entering

the

one

and

shown
command.

Function

Command

The

six

octal

contents

relocated
at

the

R4.

address

program

for

The

software

the

following

execution

the

(xxxxxx)

Entering

operation.

once

digits

value

next
the

command
to

are

switch

present

selects

program

end

allows

continue

the

tape,

starting

absolute

loading
wvalue

load

loader

process

has

been

entered.

successful

The

program

console

load

device

indicated

when:

displays

165626

d
2.

The

loaded

program

automatically

starts

execution.

Absolute
AL

<LCR7or

DXn

£LCR?

floppy

<CR>

the

results
disk

and
in

drive
drive

(drive

disk

command

instruction

the

errors

are

described

for

the

command.

RXV11
DX

loader

1).

starts

test

system

and

the

number

test

execution

Successful
the

SYstem
(n)

Entering

memory-modifying

memory

commands).

execution
0,

bootstrap.

bootstrap

disk.
0

test

(drive

CPU
(see

execution

program

Otherwise,
1

the

for

specify

Function

Command

Floppy

The

bootstrap

program

halts

errors

and

are:

the

console

Done

device

displays:
165316

@
indicating

RXV11

that

the

device

interface

was

not

quired

time

can

restarted

the

and

the

The

program

(approx.

then

1.3

halts

within

sec.).

entering

displayed

bootstrap

set

flag

can

and

console

the

re-

bootstrap

command;

console

command
the

the

The

the

device

entered.
displays:

165644

e
indicating

The

that

RXV11's

stored

using

and

Error

R2,.

the

bootstrap

error

contents

examining

the

Manual,

the

error

can

determined.

R2/nnnnnn

(nnnnnn)

<CR>

contents

exact

User's

contents

are

contained

RXV11

occurred.

information

the

disk

the

follows:

nature

Examine

the

Command

Function

After

examining

started

bootstrap
prompt

The

the

program

timeout

prompt

(refer

the

programs.
Loaders

(AL

and

Start

the

strap

starting

165242,

This

R4/xxxxxXxx

165242G

vector

trap

character.
the

bootstrap

and

bootstrap

165264

program

this

(165264).

the

program

the

again

for

traps;

the

successfully

entering

the

command.

the

Halt

(console

executing

manner
for

include

the

drive

first

Start

the

REV11

shown

ODT)

absolute

(DX).

with

the

program

below:

mode

Diagnostic

the

disk

operations

<CR>

trap

Attempt

system

started
the

the

returns

first

desired

without

sequence

halts

command)

address

the

after

from

bootstrap

enter

can

immediately

started

AR)

bootstrap

command;

Programs

can

the

character.

desired

programs

command

bootstrap

Bootstrap

R2,

boot-

Start

the

absolute

appropriate

loader

starting

program

address

(AL

AR)

R5.

For

example,

with

177776.

R4:

starting

address

165414

starting

address

165406

Load

the

highest

available

memory

address

the

system

read/write

memory,

load

Proceed

plete

contains

sequence

the

starting

the

REV11

for

starting

the

program

R5
at

165242.

The

com-

shown

system

R4/xxxxxx

165414

<CR
>

below:

R5/xxxxxx

177776

<CR>

165242

G.3.1.3

Bus

Terminations

REV11-A,

BCV1B

(M9400-YB

includes

stalled

plane.

REV11-A

Either
able
two

used

250AQL
the

bus

backplane

TEV11

REV11-A

option

slot

the

backplane

systems

which

REV11's

DMA

refresh

operation

required.

refresh
is

and

must

last

enabled

The

other

disabled
or

TEV11

and

are

expanding

third)

REV11-A

DMA

refresh

the

in-

last

backplane

unless

not

availin

should

processor

operation

back-

terminations.

the

option

BCVI1B

second

bus

devices,

either

The

which

120fL

installed
or

included

options.

connector

include

(second

system.

include

when

options

TEV11

three

terminations

module),

the

Bus

terminator/cable

first

and

not

the
module

CAUTION

The

use

other

stalled

the

and

processor

the

ineffective

data.

When

addition

(no

the

device

mination

Using

G.3.2

G.3.2.1
in

the

module

properly

devices

the

REV11

the

installed

Jumpers

ROM

Module

when

the

TEV11

last

The

part

for

used

use

the

highest

result

and

the

option

REV11-A
of

service
insure

memory

in
REV11-C

TEV11;
priority

120/L bus

ter-

location.

and

normally

complete

the

system

REV11-A

backplane

factory-installed

system.

However,

modifications,

system

processor

placement

location

proper

installing

(M9400-YA

chip

loss

in-

REV11-A

likely

option,

resistors)

the

and

are

REV11-A

removed

considered

will

refresh

the

which

between

module

DMA

and

backplane

bus

REV11-C

devices

DMA

Installation

system

I/O

termination

install
DMA

DMA

operation.

are:

module).

must

Items

Jumpers

module,

moved

Three

jumpers

shown

alter

are

Figure

REV11-A

normally

G-14.

installed

Jumpers

operation

and/or

Function

(Removed)

DMA

enabled

DMA

Bootstrap

ROM

Chip

and

should

E25,

and

numbers

Placement
not

E29

are

ROM

enabled

chips

removed.
shown

listed

below,

can

re-

Altered

(Installed)
refresh

M9400-YA

follows:

Normal

Jumper

the

must

socket

G-14.

disabled

ROM

factory-installed

chip

Figure

refresh

Bootstrap

are

ROM

Function

ROM

installed

locations
chips,

only

disabled

sockets

E19,

E22,

whose

part

the

sockets

listed:
ROM

Module

Location

backplane
last

option

used

system

I/0

bus,

since

any

23-075A9-00

E22

23-076A9-00

E25

23-077A9-00

E29

location

processor module

which
on

the

applications

option

Socket
E19

Backplane

those

No.

23-074A9-00

configurations

the

allow

Part

The

require
I/O

which

devices

REV11-A

would

bus.

use

used

120 bus
The

other

must

devices

higher

priority.

the

M9400-YA

module

between

unoccupied;

option

three

termination

REV11-A

DMA

two

have

locations

remain

1is

locations

not

the

and

not

the

must

occupied

signal

last

the

order

the

pass

M9400-YA

available

the

processor's

module.
option

Hence,

location

daisy-chained

the
on

module

the

BDMGI/O

should

last

(second

located

third)

backplane.

G.3.2.2
option

Operation
are

G.3.3
The

used

Using

REV11-C

function

first
from

the

para.

G.3.4

the

programs

paragraph

the

REV11-A

This

option

DMA

device

bootstrap

desired,

jumper,
ROM

included.

ROM

included

this

G.3.1.2.

REV11-C

factory,

Bootstrap

one

directed

programs

should

ROM

the

and

the

except

DMA

the
be

bus

installed

system.

refresh

functions

termination
the

supplied

functions

can

option

are

disabled

for

the

REV11-A

this

option

are

used

REV11-C

except

the

ROM

included

(para.
as

G.3.2.1).

described

G.3.1.2.

Using

REV11-H

programs

are

Refer

REV11-H

G.3.5

Using

TEV11

the

1is

G.3.3.

The

described

(highest-priority)

removing

The

Bootstrap

identical

not

implemented.

REV11-H

identical

different.

LDP

installed

the

Install

system
for

the

manuals

detailed

module

for

directed

hardware

operating

bootstrap
in

which

para.

the

procedures.

TEV11

120fL

terminator

module

which

used

LSI-11

multiple

backplane

avalillable

location

G.3.6

Using

The

BCV1B

and

one

the

first

the

option

M92401

assemblies.

the

Install

last

the

(second

TEV11

third)

the

last

backplane.

BCV1B
includes

module.

backplane

two

This

BCO5L

option

second

cables,

one

always

backplane

M9400-YE

used

for

module

connecting

multiple

backplane

systems.

Install
first

the

M9400-YE

backplane,

first

module

slots

backplane

A4,

are

in
B4.

daisy-chained

BIAK

last

option

backplane

M9401

module

backplane.

and

M9401

the

same

second

the

Install

modules.

cable;

and

first

the

Note

Insure

BDMG
(the

option

two

BCOS5L

option
that

This

signals

slot

(A1,

cables

option

slots

necessary
be

applied

module).

B1)

between

that

each module

similarly,

each

all

will

M9400-YE

location

module

are

insure
to

the

Install

the

second

M9400-YE

connected

connected by the

cable.

The completed

required
backplane
TEV11

for a two backplane

installation

BCV1B option is

the

last

occupied.

that

the

in the

shown in Figure G-15.
last option

configuration.
option,

slot

This

previously

in the

120fL bus termination 1is
second backplane

function 1is

described.

system using the

in a two

normally provided by

PROCESSOR MODULE

OPTION 2

—

OPTION 1
FIRST

OPTION 3

BACKPLANE

OPTION 4

250
Q2 TERMINATOR/

PTION

CABLE CONNECTOR (1)

OPTION 5

)é /*\
EXPANSION

CABLES (1)

N\ 72N "/

» 1 Y s

CABLE CONNECTOR (1)

OPTION 6

OPTION 8

OPTION 7

SECOND
OPTION 9

BACKPLANE

OPTION 10

120 2 TERMINATOR/

CABLE CONNECTOR (2)

OPTION 11

Notes:
1. Included in BCV 1B bus expansion option. (Cables are available
in 2,4, 6, or 12 ft. lengths.)

2. Included in TEV 11 bus terminator option.

CP-2047

Figure

G.3.7

Using

The

BCV1A

and

one

the

second

the

option

M9401

G-15

BCV1B

Installation

BCV1A

includes

module.

backplane

two

BCO5L

This

option

the

third

cables,

one

always

backplane

M9400-YD

used
in

for

three

module,

connecting
backplane

systems.

Install

second

the

M9400-YD

backplane,

module

slots

A4,

B4.

the

last

option

Observe

that

G-39

location

all

option

the

slots

the

first

and

insure

that

plied
the

the

second

daisy-chained

last

M9400-YD

backplanes

slot

installed.

the

Install

BCO5L

cables

module

are

connected

the

same

module

are

connected

the

second

the

between

completed
option

BCV1B

option

the

second

the

last

the

shown
is

for

slot

termination

function

previously

described.

Figure

required

backplane,

option

third

and
in

the

and

M9401

necessary

will

module

Install

the

ap-

which

the

modules.

Similarly,

first

two
on

each

cable.

three

backplane
In

third

system

addition

connecting

120U bus

normally

backplane,

M9401

cable.

This

signals

second

G-16.

for

BDMG

backplane.

M9400-YD

installation
is

the

occupied.

and

slot

BCV1A

B1)

BIAK

option

The

(A1,

option

are

the

backplane.

provided

the

this

first

termination
The

using

the

option,

backplane

required

120/

TEV11

bus

option,

PROCESSOR MODULE

OPTION 2

OPTION 1

OPTION 3

OPTION 4

250 2 TERMINATOR/

CABLE CONNECTOR (1)
AN

FIRST

BACKPLANE

OPTION5

EXPANSION

CABLES (1)

Y Y

CABLE CONNECTOR (1)

OPTION 6

OPTION 8

OPTION 7

OPTION 9

OPTION 10

CABLE CONNECTOR (2)

OPTION 11

SECOND

BACKPLANE

/*\ /l\
EXPANSION

CABLES (2)

Y Y

CABLE CONNECTOR (2)

OPTION 12

OPTION 14

OPTION 13

OPTION 15

OPTION 16 (4)

120 £2 TERMINATION (3)

OPTION 17 (4)

THIRD

BACKPLANE

Noteas:
1. Included in BCV 1B bus expansion option. (Cables are available

in 2,4, 6, or 12 ft. lengths.)
. Included in BCV 1A bus expansion option. (Cables are available
in2,4, 6, or 12 ft. lengths.)
w

. Included in

TEV 11 bus terminator option.

The LS111 Bus is restricted to 15 options, maximum. These

option slots would only be used when previous option(s)
occupy micre than 1 option location.

CP-2048

Figure

G-16

BCV1A

Installation

APPENDIX H

DLVI11 I/0 JUMPER CONFIGURATIONS

G6—eoCL4

G—9© CL3

—=©CL2

=9 CL1
O

OEIA

Rahatt

11-3924

Figure H-1

20 mA Active Current Loop Interface

USE BCO5M CABLE

O
O

cL3

O EIA

e/zcu

CL1

— i

Q‘\\

11-3851

20 mA Passive Current Loop Interface

USE BCOS5C CABLE

ocCL4

OCL3

1
ocCL?

]

OocCLi

Figure H-2

[——

G—-O EIA

o—y

USE BCOSM CABLE

11-3925

Figure H-3

EIA Interface
H-1

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EK-LSI11-TM-003

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