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EK-LSI11-TM-002

September 1975

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Document:	LSI-11 PDP-11/03 User's Manual
Order Number:	EK-LSI11-TM
Revision:	002
Pages:	168
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EK-LSI11-TM-002

LSI-11, PDP-11/03
user’s manual

digital equipment corporation

maynard, massachusetts

1st Edition, September 1975
2nd Printing (Rev), November 1975

Copyright © 1975 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no respon

sibility for any errors which may appear in this
manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
FLIP CHIP

DECtape

PDP

DECmagtape

UNIBUS
LSI-11

DECsystem-10

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1

GENERAL

1.2

SCOPE

. . . .

e e

1.3

1-1

REFERENCES

. . . . . . e

1-1

CHAPTER 2

LSI-11 SYSTEM OVERVIEW

2.1

GENERAL

2.2

SYSTEM CONFIGURATIONS

2.3

LSI-11 MICROCOMPUTER

I/OBUS CONCEPT

. . . . . .

2-2

2.5

MEMORY OPTIONS

. . . . . . . e
e
e

2-3

. . . . .

1-1

. ... ... ... . ... . ... ... ...... e
. . . . . . .

2-1

. . e

2-1

. . . . . .

e e

2.6

PERIPHERAL INTERFACE OPTIONS

BACKPLANE, POWER SUPPLY, AND HARDWAREOPTIONS

2.8

POWER REQUIREMENTS

2.9

GENERAL SPECIFICATIONS

CHAPTER 3

THE LSI-11 BUS

3.1

CHOOSING ANI/OTRANSFERTYPE

3.2

DEVICEPRIORITY

MODULE CONTACT FINGER IDENTIFICATION

e e e

. . . . . . . . . . . .
. . . . . . . .

e e e

e et

2.7

. . . .. e

e e

2-3

. . .. .. ........

2-3

. .

. . . .. .. ...

2-1

2-4

3-1

. .. . . . . e
e

. ... ... ..............

3-1

3-2

3.4

BUS SIGNALS

. . . . . e

3-4

3.5

BUSCYCLES

. . . . . e
e L.

3.5.1

General

3.5.2

Input Operations

3.5.3

3.6

. . ... ................. e

e e

3-7

. . . . . . . . . . .. .

3-7

. . . . . . . . ... ... v, P

3-8

Output Operations

DMA OPERATIONS

. . . . .

3.7

INTERRUPTS

3.8

BUS INITIALIZATION

POWER-UP/POWER-DOWN SEQUENCE

e s e

e 3-11

. . . .
e e
e e e e
3-12
. . . . . .

3.10

HALTMODE

3.11

MEMORY REFRESH

. . . . . . . .

3.12

BUS SPECIFICATIONS

. . . . . .

3.13

BUS CONFIGURATIONS

3.14

BUS SIGNALTIMING

CHAPTER 4

LSI-11 MODULE DESCRIPTIONS

4.1

GENERAL

4.2

KD11-FMICROCOMPUTER

. . . .

e e e e

. . ... ... ... ...

e 3-13

et e 3-13

e e e e

e e

e e e e i

. . . . . .

. ... ........... e

e e e e

e e

e e e 3-12

... .. .. .... 3-12

e e e

e e 3-14

e
e

e 3-14
e e 3-15

. . . . . e
e e e
e
e
. . . . . .. . . . .

4-1

. it

4-2

. . . . . . ..
e e
e
e

4.2

4.2.1

General

4.2.2

Basic Microcomputer Functions

. . . .. ... .. ... ... .. ... ... . ...

42.2.1

Microprocessor ChipSet

4222

Clock Pulse Generator

42.2.3

Bus Interface and Data/Address Distribution

4224

BusI/O Control Signal Logic

4225

Bank 7Decoder

. . . . . ... ... ... . ... . . .. ..
. . . . . . . . . ... . ..

...,

4-3

i ittt

4-3

. . . . .. ... ... ......

4-4

... ...

4-5

. . . . .. .. ...
e e

. . . ... ... ... . .. ... ..

4-7

4.2.2.6

Interrupt Controland Reset Logic

4.2.2.7

Special Control Functions

42238

Bus Arbitration Logic

. . . . .. ... ... ............

. . ... ... ... .. e

. . . . . . ...

iii

e e e e e e e e e
e

4-7

4-9
4-10

CONTENTS (Cont)
Page
4.2.3

4.2.4

4.3
43.1

432
4.3.2.1

4322
4323

432.4

43.2.5
43.2.6
44
4.4.1

4.4.2
44.2.1
44.22
4423
4.5

4.5.1

4.5.2
4.6

4.6.1
4.6.2
4.7

4.7.1
472

47.2.1

4722
47223

4.7.2.4
472.5

47.2.6

KDI11-FResident Memory . . . . . ¢ v v v v i i i e i et e et
e e
e e 4-13
DC-DCPowerInverter . . . . . . . @ v v v i v i i i it e it et e e
e
e 4-14
MMV11-A 4K BY 16-BIT COREMEMORY . .. ... ... ...... e e 4-14
General . . . . .
e e
e e
e e e e e e e e
e e
e e e
e e e e e 4-14
Functional Description . . . . . .. ... ... .
oo
oo .. 415
Introduction . . . . . . . .
.
e e
e
e
e
e 4-15
Core Addressing
. . . . . . . o v i i
e
e e e
e
e e 4-17
Read/Write DataPath
. . . . . . . . . . . .
it i it i et e
e e 4-18
Timingand Control
. . . . . . . . . o . i
e
e 4-20
DC Protectionand VecSwitch . . . . . . ... ..
oo oo o 4-23
DC-DCInverter
. . . . ¢ v v v v v v i
et e et e
e e
e e e 4-24
MRV11-A 4K BY 16-BIT READ-ONLY MEMORY .. ...
.. ... e
e e e e e 4-24
General . .. .. ... .. ... e e
e e e e e e e e e e e e
e 4-24
Functional Description . . . . ... .. ... ... ... .... e e e e e e e e e 4-24
General . . .. ... .......... e
e e e e e e e
e e
e
e e 4-24
Addressing . . . . . . . ..
e
e C e e 4-26
Data Read Operation . . . . ... ... ... ......... e
e e e e e 4-26
MS11-B 4K BY 16-BIT SEMICONDUCTOR READ/WRITE MEMORY ... ... ... .. 4-27
T3
1 1<) -1
4-27
Functional Description . . . . ... ... ... ... ... e
e e i e e e e e 4-27
MSV11-A 1K BY 16-BIT SEMICONDUCTOR READ/WRITE MEMORY . ... ... ... 4-29
General . . . .. L
e
e e e e e e
e e
e e e e
e
e C e
e 4-29
Functional Description . . . . . . . . . . .. . .
e
e 4-30
DLV11 SERIALLINEUNIT
. .. .. . . . . et
e e 4-30
General . . . . .
e e e e e e e e e e e e e
e e e
e 4-30
Functional Description . . . . . . . . .. .. . .
. o 4-32
General . . . ..
e e e e e e e e e e e e e e e e e e e 4-32
UAR/T Operation
. . . . . . . .o v i vttt ittt e
e et e
e 4-32
Baud Rate Generator . . . . . v v v v v v vt
e e e e e e e e e e e 4-32
Bus Drivers and Receivers
. . . . . ... ... ... ... .. e e e
e e e 4-32
Address Decoding
. . . . . . . . ... e 4-32
Function Decoding and Control
. . . . .. ... .. .. e
e e e e e
e e 4-32

4.7.2.7

Interface Control Logic

4728

CSR Selectionand Gating

. . . . . . . . . . .
. . . . . . . . . . . .

4729

Break Logic

e e 4-34

. . . . . . .

4.7.2.10

Reader RunLogic

47.2.11

EIA Interface Circuits

4.7.2.12

20 mA Loop Current Interface

47.2.13

4.8

—12VInverter
General

482

Functional Description

. . . . . . . . o

. . . ..

. . . . . . L

v i

i i i

e e e

e
e

e e e

. . . . . . . . . .. . .

e e

e e e

Function Selection

4.82.5

48.2.7

4-34

e e e e 4-35

4.8.2.3

4.8.2.6

. ... ... ... ... e 4-35

General . . . . ..
e
e e e e e e e e e e
Addressing . . . . . .. ... ee

4.8.2.4

e 4-34

. . . .. ... ... ... .. e
e e 4-35

4.82.2

4.8.2.1

e 4-32
e e

. .. ... ... ... .. i 4-34

DRV11 PARALLELLINEUNIT

4.8.1

e e

e 4-35

e e e e e e e e 4-35
e
e e e 4-35

. . . . . . . . . . . . . e 4-35
Read Data Multiplexer . . . . . . . . . .
v
i
4-38
DRCSRFunctions . . . . . . . . . @ o
i it e i
e e e
e 4-38
DRINBUF Input Data Transfer
. . . . .
.. . .. ... ... 4-38
DROUTBUF OQOutput Data Transfer
. . . ... .. ... ... ......... 4-38

CONTENTS (Cont)
Page

4.8.2.8

Interrupts

4.8.2.9

Maintenance Mode

4.8.2.10

Initialization

4.9

. . . . .
e
e
e 4-38
. . . . . . . ... L 4-39
. . . . . . .. . ... .. 4-39

H780 POWER SUPPLY

4.9.1

. . . . . . . .
s e 4-39
General
. . . . . . . e 4-39

4.9.2

Specifications

4.9.3

Functional Description

. . . . . . ... 4-40
. . . . . . . .. . . ... . ... ..

. 4-40

49.3.1

General

. . . . . . . .

e 4-40
. . . . . . ... .. ... .. ...... 4-40

49.3.2

Unregulated Voltage and Local Power

4.9.3.3

Basic Regulator Circuit

4.93.4

Overload and Short-Circuit Protection

493.5

Crowbar Circuits

4.9.3.6

Logic Signal Generation

4.9.4

H780 Connections

. . . . . . . ... .. .. ... ... ...

. . . . . . . . . . . o

CHAPTER 5

USING KD11-F and KD11-J PROCESSORS

5.1

GENERAL

JUMPER-SELECTED FEATURES

. . . . .

General

52.2

Memory Refresh

. . . . . . ..

5.2.3

Line Time Clock

. . . . . . . . . . .

524

Power-Up Mode Selection

5.2.5

Resident Memory 4K Address Selection

. . . . .. L

. . .

INSTALLATION

USING THE LSI-11 MICROCOMPUTER

. ... ......... e

HaltMode

CHAPTER 6

LSI-11 INTERFACE MODULES

6.1

GENERAL

6.2

DLVI11 SERIAL LINE UNIT

. . . v v v v oo vt e

5-2

e e e e e e e

e s

5-4

. . . .. .. ... ... ...

...

5-4

e e e

. . .

e e

5-4
5-4

6.2.1

General

6.2.2

Jumper-Selected Addressing, Vectors, and Module Operations

e e e e

6.2.2.1

Locations

. . . . . . . . . .

6.2.2.2

Addressing

. . . . ...

6.2.2.3

Vectors

6.2.2.4

UAR/T Operation

6.2.2.5

Baud Rate Selection

e e

6-1

e e

6-1

e e e

6-1
6-1

e e

ittt

e e e

e e

6-1

e e

6-3

e
e

e e e

. . . . ... ... .. ... ... . ... ..

EIAInterface

20 mA Current Loop Interface

. . . . . . .

o i 0 i e

6-3

. . . . .. ... . ... ... ... ...

...

6-3

. . . . . ... ...

6.2.3

Installation

6.2.4

Interfacing with 20 mA Current Loop Devices

6.2.5

Interfacing with EIA-Compatible Devices

6.2.6

Programming

. . . . . . . . . . .

. . . . . . . .

5-4
5-4

. . . . . ... .. ...

e e
e

. . . . . . . .. .

6.2.2.7

Addressing

e e e e e e
e

. . . . . o

Framing ErrorHalt

e e

5-3

.
..

e e

. . . . . . .. .

6.2.2.6

5-2

e e

. . . . .. . ...

. ... ......... e

5-1
5-1
5-1

e e e e e e e e e e

.. ............ e

5-1

.. ......... e,

INITIALIZATION AND POWER FAIL

6.2.6.1

. . . . . . . . . . .. ... .

5.5

6.2.2.8

. . . .

Interrupt and Trap Priority

e 4-48

. . . .. ... .. .. ... . .. ...

5.3

General

e e

. .. .. ..

5.4

54.1

e 4-44

. . . . . . . . .. . . . i

5.2.1

543

. . . . .. ... ... ... . ... . ... ... ... 4-44

. . . . . . . . . . .

5.4.2

. 4-42

. . . .. ... .. ... ......... 4-43

... ... . ... .. ...
e
.

. . . . . . .. ..

. . . . . .. . ...

. . . . ... L

.....

6-4

.. ... .. ...

6-4

e e

... ... ......

6-5

e e e e e

6-5

CONTENTS (Cont)

6.2.6.2

Interrupt Vectors

6.2.6.3

Word Formats

6.2.7

6.3

Console Device

................................

..................................

.....................................

DRV11 PARALLEL LINE UNIT

..............................

6.3.1

General

6.3.2

Jumper-Selected Addressing and Vectors

.........................................

6.3.2.1

Locations

6.3.2.2

Addressing

6.3.2.3

Vectors

.......................

....................................

......................................

6.3.3

Installation

6.3.4

Interfacing to the User’s Device

.......................................

6.3.4.1

General

6.3.4.2

Output Data Interface

6.3.4.3

Input Data Interface

............................

......................................

..............................

...............................

6.3.4.4

Request Flags

6.34.5

Initialization

6.3.4.6

NEW DATA READY and DATA TRANSMITTED Pulse Width Modification
BCO8R Maintenance Cable

6.34.7
6.3.5

..................................

-----------------------------------

Programming

6.3.5.1

Addressing

6.3.5.2

Interrupt Vectors

6.3.5.3

Word Formats

CHAPTER 7

....................................

................................

----------------------------------

USING MSV11-A and MSV11-B READ/WRITE MEMORY MODULES

7.1

GENERAL

7.2

MSV11-A

JUMPERS

7.3

MSV11-B

JUMPERS

7.3.1

. . . .

Addressing

e e

-------------------------------------

.......................................

7.3.2

Reply to Refresh

MSV11-B BUS RESTRICTION

CHAPTER 8

USING MMV11-A CORE MEMORY

....................................

8.1

GENERAL

8.2

SWITCH-SELECTED ADDRESSING
General

.....................................

7.4

8.2.1

............................

......................................

..........................................

----------------------------

-----------------------------------------

8.3

BUS RESTRICTIONS

CHAPTER 9

USING MRV11-A READ-ONLY MEMORY
. . .

------------------------------------

9.1

GENERAL

9.2

JUMPER-SELECTED ADDRESSING AND CHIP TYPE

9.2.1

General

9.2.2

Chip Type Selection

9.2.3

Addressing and Reply

e e e e

e e e

----------------------------------

---------------------------------

PROGRAMMING PROM AND ROM CHIPS

9.4

PROGRAMMING RESTRICTIONS

9.5

TIMING AND BUS RESTRICTION

-----------------------------

CONTENT'S (Cont)
Page

CHAPTER 10

USER-DESIGNED INTERFACES

10.1

. . . . . e 10-1
. . ... ... .. ... 10-1
PROGRAMMED INTERFACE
. . . . . .. . . . i, 10-2

10.2
10.3

104

GENERAL

BUS RECEIVER ANDDRIVERCIRCUITS
INTERRUPT LOGIC

. . . . . .

10.5

DMA INTERFACELOGIC

CHAPTER 11

SYSTEM CONFIGURATION AND INSTALLATION

11.1

GENERAL

11.2

CONFIGURATION CHECKLIST

ittt et e

DEVICEPRIORITY

General

11.3.2

Priority Selection Using the H927C Backplane

11.3.3

H9270 Backplane/MMV11-A Configuration

MODULE INSERTION AND REMOVAL

e e

e, 11-1

IJOCABLING

PDP-11/03 INSTALLATIONPROCEDURE

. . ... ..

112

e 11-2

. . . ... ... ... ......... 11-2
. . .. ... ... ............

. . . ... ... ... .

11.6

112

.. 11-3

e e, 11-4

. . . .. ... ... ... 11-4
. . . . . .. .. ... ... 11-4

11.6.1

Packagingand Mounting

11.6.2

Power Requirements

11.6.3

Environmental Requirements

. . . . . . .. ... ... ... .. .. 11-5
. . . . . . .. .. ... ... ... ... .. ..., 11-5

LSI-11 SYSTEM INSTALLATION

. . . . . . . .

11.7.1

General

11.7.2

Mounting the H9270 Backplane

11.7.3

DC Power Connections

. ... ......... e

e e

e e e e e e e e e

e e

e e 11-5

e e

e e e e

e e 11-5

. . . . ... ... ... ... ... .. ....... 11-5
. . . . . e
e e e e
e e e e e e e e e e e e
e 11-5

11.7.3.1

Voltage and Current Requirements

11.7.3.2

H9270 Backplane Power Connections

11.7.4

H9270 Backplane Ground Connection

11.7.5

Environmental Requirements

11.7.6.1

. .. ... . . . e,

. . . . . ..

11.5

11.7.6

i, 10-5

11-1

. . . . . .

11.3

11.7

e 10-5

. . . . . .

11.3.1

114

e e

. .. . . ... . . .

. . . . . ... ... ... ......... 11-5
. . . . .. ... .. ........... 11-7

. . . . ... ... ... ... .........

11-8

. . . . . . ... .. ... ... ... . ........ 11-8
Externally Generated BusSignals
. . . . . . ... ... ... ............ 11-8
General

. . . . . . . L
e
e 11-8

11.7.6.2

BDCOKHandBPOKH

.. ..........
... .. ...
....
....

11.7.6.3

119

BEVNT LSignal

. ... ... ... .. ... . ..

119

BHALT L Signal

. . . .. . ... .. . .

11.7.6.4
11.8

SYSTEM OPERATION

11.8.1

General

11.8.2

PDP-11/03 Power-On

11.8.3

LSI-IT Power-On

11.84

11.9
11.9.1

. . . . .. . .

11-10
11-10

. . . . . . . .

. . . . . . . o

. . . . . . . .
o
ASCII Character Console Printout Program

PAPER TAPE SYSTEM OPERATION
General

e e e e e e

e e

. . . . .. . . ...

11-10

11-10
e

.o v

11-12

. . ... ... . ... i

11-12

. . . . . . e

11-12

11.9.2

References

11.9.3

Loading the Absolute Loader

11.9.4

Loading Program Tapes

. . . . . . . . . .

11-12

. . . . .. . ... ... ... ............

11-13

. . . . . . . . . . . . .. e

11-14

. . . . . . ...

11-14

11.9.4.1

General

11.94.2

Normal Loading Procedure

11.9.4.3

. i,

.. e,

. . . .. .. ... ... ... ...........
Relocated Loading Procedure
. . . . ... ... ... ... ... ......

11944

Self-Starting Programs

11.9.5

Program Starting and Execution

. . . . . . . . . ... ...
. . ... . ... ... .. .............

vii

11-14

11-15
11-15

CONTENTS (Cont)
Page

11.10.3.3

RT-11 SYSTEM OPERATION . . . . . . . o i i it i et et e e e e e e a o
7= T3
e e e e e
e
. . . . o o i i i
Usingthe RXOL
e e
e
RXVI1IBOOISIIAD « -« v v v o v v i v e e e e i e e e et e e
e e e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
General . . . . e e e e e e e e
..
.........
..
REV11-C
or
REV11-A
the
Booting the System Using
......
...
...
...
.
.
.
Device
Console
the
Booting the System Via

CHAPTER 12

PERIPHERALS

APPENDIX A

MEMORY MAP

APPENDIX B

LSI-11 BUS PIN ASSIGNMENTS

APPENDIX C

7-BIT ASCII CODE

APPENDIX D

SUMMARY OF LSI-11 INSTRUCTIONS

APPENDIX E

H9270 BACKPLANE CONFIGURATIONS

APPENDIX F

BUS INTERFACE 1.C. PINS

11.10

11.10.1
11.10.2

11.10.3

11.103.1
11.10.3.2

viii

11-15
11-15
11-16
11-16
11-16
11-16
11-16

ILLUSTRATIONS

Figure No.

Title

Page

3.1

Module Contact Finger Identification

Quad Module Contact Finger Identification

3.3

LSI-11, PDP-11/03 Backplane Module Pin Identification

. . ... ... ... ... ... ... ... .....
. . . . ... ... ... .. .

... . ...

3-3

. . .. ... ... . .. . . ...

3-3

3-4

DATIBusCycle

3.5

DATIO or DATIOB Bus Cycle

. . . . . . v v v vt e

3-6

DATO or DATIOB Bus Cycle

3.7

DMA Request/Grant Sequence

. . . .. . .. ... v 3-10
. . . . . . . .. ..
it e 3-11

3.8
3.9
3-10
3-11

. . . . . . . . . . .

3-8

e e

e e e

Interrupt Request/Acknowledge Sequence

. . . .. ... ... .. ... ... ....... 3-13
. . . . . .. . .. ... ... ... 3-14
Minimum Configurations . . . . . .. . .. .. ... . ... e 3-14
Intermediate Configuration
. . .. . .. ... ... ... ... .. 3-15

Bus Line Terminations

3-12

Maximum Configuration

. . . . . .. .. . .

. .0

3-13

DATIBus Cycle Timing

. . . . . . . . . .. .

3.14

DATO or DATOBBus Cycle Timing

3.15

DATIO Bus Cycle Timing

3.16

Interrupt Transaction Timing

3-17

DMA Request/Grant Timing

3.18

Power-Up/Power-Down Timing

4.1

KDI11-F Microcomputer Logic Block Diagram

4.2

Clock Pulse Generator

4.3

LSI-11 Bus Loading and Driver/Receiver Interface

4.4

EDAL L Logic

4.5

Bus I/O Control Signal Logic

3-15
it

e s

. . . . . . .. . . . .o

. . . . . . . . . .

e e e

e 3-16

v v i i i 3-17
e

e s e

. . . . . . . . . . . ... ... . ..

. . . . . . . . .. .o

. . . . . . . .

. . . . .. . ... ... ... ........

Bank 7Decoder

Interrupt Control and Reset Logic

4-3

. . . . . .. ... .. ... ... ....

4-4

4-6

. . . ... ...

4.8

Special Control Functions

4.9

Bus Arbitration Logic

4-2

. . . . . . .. .. .. .

4-6

. 3-19

3-20
. . . . . . . . .. ... ... v, 3-20

. . . . . . . . . . . . .

4.7

e 3-18

. . . . . . . ... ... ... ... .. ... ......

47
4-8

. . . . .. ... . ... .. .. ... .., 4-10
. . . . . . . .. 4-11
. . . . . . . . . .
e
e
e 4-11

4-10

DMA Grant Sequence

4-11

KDII-F Resident Memory

4-12

MMVI11-A Core Memory Option

. . . . . . . . . i v i v it

4-13

MMVI11-A Logic Block Diagram

. . . . . .. . . .. .. ... . 4-16

4-14

4.15

4.16
4-17

4-18
4.19

MMV11-A Core Addressing

. . . . . . .. ... . ittt 4-12

Read-Modify-Write Memory Cycle Timing

DC Protection and Vee Switch Circuits

DC-DCInverter Circuit

512 by 4-Bit Chip-Jumper Configuration
256 by 4-Bit Chip-Jumper Configuration

4.24

MSV11-B Logic Block Diagram

4.25

MSV11-ALogic Block Diagram

4-26

DLVI11 Logic Block Diagram

et .. 4-22

4-24

. . . . . . .. ... . ... . i 4-25

4.22

4-30

. . . . . . . . . . . v v v v vt e

. . . . . . . . .. ... ... ... .. ... 4-23

. . . . . . . . . .o o

4.23

4.31

e 4-14

e
e 4-17
. . . . . . . . . . .. . . . . .
4-19
MMV11-A Timing and Control Circuits
. . . . . . .. . . .. . .. ... ... .. ... 4-21
Read-Restore Memory Cycle Timing . . . . . . .. . ... ... ... .. ......... 4-22

MRV11-A Logic Block Diagram

4.28

e e

. . . . . . . . . i i v ittt et

4.20

4-29

MMV11-A Read/Write Bit DataPath

4.21

4.27

e i

. . . .. . .. ... ... ... ... ...... 4-26
. . . ... ... . ... ... ... ....... 4-27

. . . . . ... ... ... .. ... 4-28

. . . . . . . . . .\ v vt i 4-31

. . . . . ... ... ... . ... ... . ... ...
... 4-33
. . . . . . ... ... ... .. ... ... ......... 4-36
H780 Power Supply Block Diagram
. . . . . ... ... ... .. ... ... ... .... 4-41
Unregulated Voltage and LocalDCPower
. . . . . ... ... ... ... ... ....... 4-41
DRVI11 Logic Block Diagram

Basic Regulator Circuit

. . . . . . . . . . .. ... 4-42
. . . . . ... ... ... ... . ... ....... 443

Overload and Short-Circuit Protection

ILLUSTRATIONS (Cont)
Figure No.

4-32
4-33
4-34

4-35
4-36
5-1

5-2
5-3

6-1
6-2
6-3

6-4

6-5
6-6
6-7

6-8
6-9
6-10
6-11

6-12
6-13

6-14
7-1

7-2
7-3
7-4

7-5
7-6
8-1

8-2
8-3

9-1

9-2
9-3
9-4
10-1

10-2
10-3

104

10-5
11-1

11-2
11-3

114
11-5

11-6
11-7

11-8
119

Title

Page

e e e e e e e e 444
Crowbar CIFCUIt . . v & v v v e e e e b e e et e e e e e
o e 445
.o
Logic Signal Generation . . . . . . . . . .
Power-Up/Power-Down Sequence . . . . . .. o v v v v v it it 4-46
e e e e 4-47
e
DC ON/OFF Circuit TIMINE + « « v v v v v e v e e v e e n e oo e oo
e 4-48
e
e
e
e
e
e
e
e
e
e
e
e
e
e
H780 Connections . . « v v v v v v i e e e e e
5.1
e
o
Jumper Locations . . . . . . o . o
5-3
e
e
e
et
e
e
v
v
v
v
v
Mode O Power-Up SEqUence . . . v v v v v v
e 5-3
Mode 2 Power-Up Sequence . . . . . o v v v v vt v vt it
e e e 6-1
e
e
e
e
e
e
it
i
e
o
o
.
.
.
.
DLVI11 Serial Line Unit . . .
6-2
e
ottt
vt
v
v
oo
.«
.
.
.
.
.
.
DLVI11 Jumper Locations
6-2
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
v
e
v
v
v
v
v
&
DLVI1 AJAIESSES

e e e e e e 6-3
DLVI1 Interrupt VECLOIS . . . ot v v v v i v e e e e e
oo 6-4
Active 20 mA Current Loop Interface . . . . .. .. ... ... ...
... 6-5
Passive 20 mA Loop Jumper Configuration . . . . ... ... ... ...
e 6-6
. . v v v v i e e e e e e e e e e e e e e e e e e e e e e e
EIAINterface
e 6-8
DLV1IIWord Formats . . . . . . .« v o i e e e e e et e e e e
e 6-8
e
DRVI1 Parallel Line Unit . . . . . . . . ot et e e i e e e e e e e e
DRVI11 Jumper Locations . . . . . . . o oo v i i i it 6-9
. . . v v v vt e v e e e e e e e e e e e e e e e e e e s 69
DRV11 Device AAAIESS
DRV11 Vector Address . . v v v v v v v e e v e v e e e e e e e e e e e e e e e 6-10
e e 6-10
e e
J1 or J2 Connector Pin Locations . . . . . . . . o v v v i v i i
6-14
e
e
e
e
e
e
et
e
e
e
e
DRVI1IWord Formats . . . . . . o i i i et e e e e et
7-1
oo
...
..
.
.
.
.
.
. . .
MSV11-A 1K by 16-Bit Read/Write Memory
7-2
vttt
v
v
v
.
o
.
.
.
.
.
.
.
.
MSV11-B 4K by 16-Bit Read/Write Memory .
7-2
t
ott
.
...
.
.
.
.
.
MSV11-A Jumper Locations . .
MSV11-B Jumper Locations . . . . . . . . . ..o it 7-2

MSV11-A Address Format/Jumpers . . . . . . . . . oo e 7-3
e 7-3
e
MSV11-B Address Format/Jumpers . . . . . . . o i v it e e
8-1
it
.
.«
.
.
.
.
.
.
.
.
.
Memory
16-BitCore
by
MMV11-A4K
Bank Address Switch Locations . . . . ... ... ... ... .. . 0., C e e e 8-2
e 8-2
e e e e e e e e
MMVI11-A Addressing . . . . . . o v v i i i e e
i ii i i 9-1
MRV11-ARead-Only Memory . . . . . .. . . . .
i it 9-2
MRV11-AJumper Locations . . . . . . . . ...
e e e 9-3
MRV11-A Address Word Formats . . . . . . . . o o v v i v it i e e
e e et 9-4
PROM/ROM Chip Pin Addressing . . . . . . . . o v it vttt
Bus Driver and Receiver Equivalent Circuits . . . . . . . ... ... ..o oo 10-1
Typical Bus Driver Circuit . . . . . . . . . o oo it 10-1
it i 10-3
Programmed I/O Interface . . . . . . . . . . o
e 104
e
Dual Interrupt Interface . . . . . . . . . o L e
e e e e e e e e e e e e e 10-6
. . . . . . . 0 i
DMA Arbitration Logic
Typical Configuration LSI-11 Backplane — Processor and Option Locations
. . . . .. .. 11-2
H9270 Backplane/MMV11-ACore . . . . . . .. . ..
ittt it 11-3
Module Installation in the H9270 Backplane . . . . . . .. .. .. ... .
oo 11-3
e 114
e e e e e e e e e e
e
. . . . . . . v i it
H9270 Backplane
e 11-5
e e
. . . . v v v v v v it v et e
PDP-11/03 Cabinet MOUNting
H9270 Backplane Mounting . . . . . . . . . . oo
e
e 11-6
e 11-6
e e e e e e e e e
H9270 Side Mounting . . . . . . . o v i i
e 11-6
e
e e
e e
e e
H9270 RearMounting . . . . . . . v v 0 v i v e s
H9270 Top and BottomMounting . . . . . . . ... ... .. .. .o 11-6

ILLUSTRATIONS (Cont)

Figure No.

Title

11-10

H9270 Backplane Terminal Block

11-11

H9270 Backplane Ground Wire

11-12

H9270 Backplane Air Flow

. . . . . .. . .. . ... ... ...
. . . .. .. ..

DELETED

-+ » + « « « « o « « .

. . . . . . . . . . . .. e

11-13

H9270 Backplane Printed Circuit Board

11-14

Power-Up Sequence

11-15

Power-Down Sequence

. . . . . ... ... ... ... ... .......

. . . . . . . . . . .

. . .. . . . . . . .

e e

. e

11-16

BDCOK H Signal Routing Diagram

11-17

BEVNT L Signal

11-18

Sample Console Printout

12-1

Direct 20 mA Current Loop Interface

. . . . ... ... ... ... .. ..........

12-2

Telephone Line Interface ViaDataSets

. . . . . ... ... ... ... ... .......

12-3

Telephone Line Interface Via AcousticCouplers

. . . . .. ... ... ... ... .. ........

. . . . . . .. . ..

sttt

. . . . . . ... .. ... ...

. . . . . . . . ... ... ... ......

TABLES
Table No.

Title

2-1

LSI-11 Modules Power Requirements

3-1

Backplane Pin Assignements

. . . . . . . .. . ... ... ...

. . . . . . . . ...

4-1

LSI-I1 Modules

4-2

DLV11 Function Decoding

. . . . . .

4-3

DRV11 Device Function Decoding

5-1

Summary of KD11 Jumpers

. . . . . . . . . . . .

i i

e e

. . . .. ... ... ... ... ... .. ...

...

. . . . . . . ... . . . e

5-2

KD11 Factory Jumper Configuration

5-3

Power-UpModes

6-1

Baud Rate Selection

6-2

Word Formats

6-3

DRV11 Input and Output Signal Pins

6-4

BC11K Signal Cable Connections

. . . . ... ... ... ... .. .. .. ......

. . . . . . . . .

e e

e e e e

e e e e e

. . . . . . .. . ...
e

. . . . . . . . . e
e
e e

. . . . . . . ... ... . ... .. .. .. .....

. . . . . . . ... . ... .. ...

6-5

BCO8R Maintenance Cable Signal Connections

6-6

Word Formats

. . . . . . . . . .

9-1

MRVII-A Chips

. . . . . .

9-2

PROM/ROM Chip AddressingData

9-3

Data Pin Assignments

. . . . . . . . . ... ... ... .....
e

. . . . . . . .. ...

. . . . . . . . . ..

e e e e

it
e e e

e e e

..
e

10-1

LSI-11 Bus Driver and Receiver Characteristics

11-1

PDP-11/03 Input Power Electrical Specifications

. . . . . . .. .. ... ... ... ....

. . . . ... ... .. ..........

11-2

H9270 Backplane Standard Power Connections

. . . . .. ... ... ... ........

11-3

H9270 Backplane Battery Backup Power Connections

114

Console Power-Up Printout (or Display)

12-1

LSI-11 Peripheral Options

. . . . . ... ... .........

. . . . ... ... ... ... ... ......

. . . . . . . . . . . . . .

CHAPTER1

INTRODUCTION

1.1

GENERAL

Chapters S—9

Use

of the

Various

LSI-11

(including

jumper

This manual contains technical data that will enable

Modules

LSI-11 and PDP-11/03 microcomputer users to inter-

configurations,

face and use LSI-11 system components effectively.

and programming information)

Before reading the detailed technical content of this

Chapter 10

manual, the user should become familiar with the basic

User-Designed Interfaces

Chapter 11

characteristics of the LSI-11 processor, as described in

System Configuration and In-

the LSI-11, PDP-11/03 Microprocessor Handbook.

stallation
Chapter 12

1.2

Peripherals (including the basic

devices available and the re-

SCOPE

quired LSI-11 interface mod-

This manual contains hardware descriptions and in-

ule, and cables required for

formation for using LSI-11 system modules, including
system configuration,

interfacing,

installation,

each)

and interfacing.

The manual is organized as follows:

In addition, quick reference information is included in
appendixes. This information includes a memory map,
LSI-11 bus pin assignments, the 7-bit ASCII code, and

Chapter 1

Introduction

Chapter 2

LSI-11 and PDP-11/03 System

asummary of LSI-11

instructions.

Overview

1.3

Chapter 3

LSI-11 Bus

The LSI-11, PDP-11/03 Processor Handbook is a re-

Chapter 4

LSI-11

Module

REFERENCES

quired reference manual for using LSI-11 system com-

Descriptions

ponents. In addition, standard hardware and interface

(including functional theory of

components are listed and described in the Hardware/

operation)

Accessories Catalog and the Logic Handbook.

i-1

CHAPTER?2
LSI-11 SYSTEM OVERVIEW

2.1

GENERAL

Systems are configured using the basic modules de-

All LSI-11 and PDP-11/03 systems are configured by

scribed in the following paragraphs.

selecting various LSI-11 module options which can be

installed in a backplane. Although individual system

2.3

requirements (in which the LSI-11 system functions as

This paragraph focuses on the KD11-F (processor and

a controller and/or data processor) may vary greatly in

4K semiconductor memory), which is the basic LSI-11

LSI-11 MICROCOMPUTER

each application, LSI-11’s modular concept allows for

microcomputer. The KD11-J has all of the basic fea-

efficient use of the microcomputer in a compact, cost-

tures of the KD11-F, except for the semiconductor

effective, flexible system design. The PDP-11/03 is a

memory; the

packaged LSI-11 system, including a processor, 4K

separate module.

MMV 11-A core memory is included as a

memory, enclosure, H9270 backplane, and H780 power
supply.

Each KD11-F features:
®

A low-cost, powerful processor for integra-

In general, all LSI-11 and PDP-11/03 systems include

tion

the KD11-F or KD11-J microcomputer. The KD11-F

computer system.

is a single 8.5 by 10 inch module that contains the
LSI-11

microprocessor

and

16-bit

into

any

small-

medium-sized

Direct addressing of 32K 16-bit words or

64K 8-bit bytes (K = 1024).

semiconductor read/write memory. The KD11-J uses
*

the same microcomputer module as the KD11-F; how-

Efficient processing of 8-bit characters without the need to rotate, swap, or mask.

ever, it is supplied with the MMV11-A 4K by 16-bit
core memory instead of the semiconductor memory.

Either type of basic LSI-11 or PDP-11/03 system can

Asynchronous operation that allows system
components to run at their highest possible

be expanded by adding various memory and peripheral

speed; replacement with faster devices means

device interface options.

faster operation without other hardware or
software changes.

2.2

SYSTEM CONFIGURATIONS

®*

LSI-11 systems can be configured using one of three

ease and flexibility in configuring systems.

general approaches:

Modules only: The user purchases only the
®

Direct memory access for high data rate

devices inherent in the bus architecture.

Modules and backplane: The user purchases
an LSI-11 subsystem that is easily mounted

in a larger system.

Hardware memory stack for handling struc-

tured data, subroutines, and interrupts.

basic module(s).
2.

A modular component design that provides

Eight

general-purpose

registers

that

are

available for data storage, pointers, and
accumulators. Two are dedicated: SP and

LSI-11 systemina box: The user purchases a

PC.

PDP-11/03 system. It includes the KD11-F
or KD11-J processor and 4K memory, an

A bus

structure that provides

position-

H9270 backplane, and an H780 power sup-

" dependent priority as peripheral device inter-

ply installed in a rack-mountable enclosure.

faces are connected tothe 1/0 bus.

2-1

Fast

interrupt

response

without

177777 are placed on the bus. These addresses are

device

normally used for addressing nonmemory devices, thus

polling.

eliminating the need for bank address decoding on

A powerful and convenient set of program-

peripheral device interface modules.

ming instructions.

A jumper-selected

that

The bus provides a vectored interrupt capability for

enables restart through a power-up vector,

power-up

mode

any interface device. Hence, device polling is not re-

console Octal Debugging Technique (ODT)

quired in interrupt processing routines. This results in

microcode subset, or a bootstrap program.

a considerable savings in processing time when many
devices requiring interrupt service are intérfaced along

On-board 4K RAM

An ODT microprogram that controls all

the bus. When a device receives an interrupt grant

(acknowledge), the KD11-F inputs the device’s inter-

manual entry/display functions previously

rupt vector. The vector points to two addresses which

performed by a control panel through a

serial

ASCII

device

(optional)

which

contain a new processor status word and the starting

address of the interrupt service routine for the device.

capable of transmitting and receiving ODT
commands and data.

One bus signal line functions as an external event interrupt input to the KD11-F module. This signal line can

Compactsize (only 8.5by 10in.).

be connected to a frequency source, such as a line fre2.4

1I/0 BUS CONCEPT

quency, and used as a line time clock (LTC) interrupt.

The LSI-11 1/0 bus is simple, fast, and easy to use as

A jumper on the KD11-F module enables or inhibits

an interface between the LSI-11 microcomputer,
memory, and peripheral interface modules. It
comprises 17 control lines and a 16-line data/address
bus. All modules connected to this bus receive the same

this function. When enabled, the device connected to

interface signals.

causes new PC and PS words to be loaded from

this line has the highest interrupt priority external to

the processor. Interrupt vector 100, is reserved for this
function, and an interrupt request via the BEVNT line
locations 100, and 102,.

Address/data and control lines are open-collector lines
which are asserted low. The microcomputer module is
capable of driving six device locations along the bus.
Peripheral interface or memory modules can be in-

Memory refresh of dynamic MOS read/write memory
is accomplished by bus signals. Refresh operation is
controlled by either the processor module microcode or

stalled in any location along this bus.

a user-supplied intelligent DMA device.

Both address and data words (or bytes) are time multiplexed over 16 bus lines. For example, during a programmed data transfer, the LSI-11 microcomputer
first asserts an address on the bus for a fixed time.
After the address time has been completed, the proces-

The processor can be placed in the Halt mode by as-

serting one bus signal. This allows peripheral devices
or a separate switch to invoke console ODT microcode
operation.

sor performs either an input or output data transfer;
the actual data transfer is asynchronous and requires a

Power-up/power-down sequencing is controlled by two

response from the addressed device. Bus synchroniza-

bus signals. One signal, when in its true state, implies

tion and control signals provide this function.

that primary power is normal. The second signal is in
its true state when sufficient dc power is available (and

Control signal lines include two daisy-chained grant

voltages are normal) for normal system logic operation.

signals which provide a priority-structured I/O system.

These signals are produced by circuits contained in the

The highest priority device is the module electrically

H780 power supply (PDP-11/03 only) or by the user’s

closest to the KD11-F (or KD11-J) module. Higher

system

priority devices pass a grant signal to lower priority

(circuits

external

the

LSI-11

system

components).

devices only when not requesting service. (Memory
options or devices which do not use these signals must

Direct memory access (DMA) operation is controlled

connect the chain.)

by three bus signals. Logic on the processor module,

The KD11-F contains a memory address register and

which is normally bus master, arbitrates DM
A requests

4K bank address decoder for its resident memory,

and grants bus mastership to the highest priority device

which can be assigned to bank 0 or bank 1. Bank 7 is

requesting the bus.

also decoded when addresses ranging from 160000 to

through the use of a daisy-chained DMA grant signal.

2-2

Priority is position-dependent

2.5

MEMORY OPTIONS

Memory options are available for expanding memory
to 28K. The basic LSI-11 microcomputer is supplied

with read/write memory. KD11-F’s memory consists of
a 4K dynamic MOS array which is physically located
on the processor module. KD11-J’'s memory is a 4K
magnetic core array contained on a separate module;
the processor module supplied with the KD11-J con-

Peripheral interface options include:

MRV11-AA — 4K by 16-bit programmable readonly memory on an 8.5 by 5 inch module. Requires one device location on the I/0 bus. Can be
configured using either 256 by 4-bit or 512 by 4bit field programmable or masked ROMs for a

DLVI11 — Serial line unit interface onan 8.5 by S
inch module. Requires one device location on the
bus. Jumpers select crystal-controlled baud rates
(50—9600 baud) and serial word format, including number of stop bits, number of data
bits, and even, odd, or no parity bit. Optional
interface cables include the BCOSM, which connects the DLV11 to 20 mA current loop peripheral devices, and the BCOSC, which connects

maximum capacity of 2048 or 4096 16-bit words.

the DLV11 to EIA-compatible devices (modems)

tains no semiconductor memory components.

Optional memory modules include:

MSVII-A — 1K by 16-bit static read/write
memory on an 8.5 by S inch module. Requires
one device location on the I/0 bus.

MMVI1I-A — 4K by 16-bit core memory on an
8.5 by 10 by 0.9 inch module. Requires two de-

vice locations on the 1/0 bus when installed in

the backplane (preferred location slots A4-D4).
This allows a daughterboard (part of the MMV11-A) to extend slightly beyond the backplane
without using additional device locations. If not
installed in this location, the MMV 11-A requires
four device locations because of the additional
module thickness (0.9 inch instead of 0.5 inch for
all other modules).

MSVI1I-B — 4K by 16-bit dynamic MOS read/
write memory on an 8.5 by S inch module. Requires one device locationonthel/O bus. Refresh
is automatically performed by the KD11-F processor microcode or by an external device.

2.6

Both interface units contain all required control/status
registers, interrupt control logic, and bus interface
logic. The user can easily assign unique device and
vector addresses for each device by changing the
jumpers on each interface module.

PERIPHERAL INTERFACE OPTIONS

Two basic interface modules are used for serial and
parallel programmed 1/0 transfer between the LSI-11
bus and peripheral devices. The DLV11 is a serial line
unit used for serial 5- to 8-bit data transfers between a
device and the bus. Itinterfaces either EIA-compatible
or 20 mA current loop devices to the bus using optional
cables which select the type of serial interface desired.
The cables are completely connector- and pin-

compatible with available modems, DECwriter, DECscope, and teletypewriter options. The DRV11 is a
general-purpose parallel line unit interface which is
capable of 16-bit input and 16-bit output paraliel
transfers to/from user devices.

via a Cinch DB-25P connector.

DRVI11— General-purpose parallel line unit interface on an 8.5 by S inch module. Requires one
devicelocation onthe bus. Two 40-pin connectors
are included on the module for user interface
application. One is the 16-bit input and the other
is the 16-bit output. Optional interface cables
are

described

the

Hardware/Accessories

Catalog.

2.7 BACKPLANE, POWERSUPPLY, AND
HARDWARE OPTIONS
Backplane, power supply, and hardware options provide a convenient means for configuring the LSI-11
system. An LSI-11 system usually requires an interconnection scheme. The H9270 backplane assembly is
the most convenient to use. It is prewired for the LSI-11
1/0 bus pinning and can accept one KD11-F microcomputer and up to six LSI-11 interface or memory
modules. It includes a card guide assembly which
provides mechanical stability for the modules. Power
and ground are applied to the backplane via a screwterminal block.

Power can be obtained from the system in which the
LSI-11 subsystem is installed, or the H780 (115 or 230
Vac input) power supply (included in PDP-11/03 systems) can be used. The power supply provides the required regulated voltages for all LSI-11 modules connected to the backplane. In addition, it generates the
necessary bus signals to initiate the KD11-F or KD11-J
power-up or power-fail processor sequence. Hardware
options include standard hardware accessories listed in
DIGITAL’s Hardware/Accessories Catalog.

2.8

POWER REQUIREMENTS

MSV11-A

The power requirements for LSI-11 system modules
are given in Table 2-1.

Table 2-1

5x8.50%0.5

LSI-11 Modules Power Requirements

MRV11-AA
:

Designation

15V i;i%

Typ|

Max|

5%8.50%0.5

+12V 11\'1?’%
Typ |

KD11-F

1.8A

[2.4A

[0.8A

|1.6A

6.4A

|9.0A

[1.2A

|1.5A

DLV11

1.0A | 1.6A

DRV11
out memory chips)

0.9A

|[1.6A

MMV11-A

Max

KD11-J

MRV11-AA (with-

10x8.50%0.9

DLV11

5x8.50%0.5

[180mA[250 mA

DRVlslx8 50%0.5
'

’

[0.4A | 0.6A

MRYV11 (with 4K
memory chips)

5% 8.50x%0.5
MSV11-B

Electrical .
2.8A

|4.1A

Input Logic Levels

MSV11-A

0.8A

[1.8A

[0.1A

MSV11-B

TTL Logical Low:

0.6A

[1.2A

[0.3A

[0.7A

TTL Logical High: 2.0 Vdc min

MMV1 1,'A

(operating)

7.0A

TTL Logical Low:

0.6A

0.8 Vdc max

0.4 Vdc max

TTL Logical High: 2.4 Vdc min

The input power requirements for PDP-11/03 systems

Bus Receivers

are:

Logical Low:

PDP-11/03-AA or-BA

Logical High: 1.7 Vdc min, 80uA max at 2.5V

100-127 Vac (115 Vac nominal), 50 = 1 Hz or
60 x 1 Hz, single phase, 400 W maximum (in-

cluding options) (190 W typical)

1.3 Vdc max,-10uA max atOV

Bus Drivers

Logical Low:

0.8 Vdcmaxat70mA

Logical High: 25,A maxat 3.5V

PDP-11/03-AB or-BB

200-254 Vac (230 Vac nominal), S0 = 1 Hz or
60 =* 1 Hz, single phase, 400 W maximum (including options) (190 W typical)
2.9

Environmental

Ambient Temperature, PDP-11/03 System:

Operating: 5° to40° C
Ambient Temperature, LSI-11 modules:

GENERAL SPECIFICATIONS

Dimensions (in.)

Operating: 5° to 50° C (41° to 122° F)

KD11-F

Nonoperating: —40° to 66° C (—40° to

+ 150°F)

10.5x 8.50 x 0.5

Derate at 60° C/1000 ft. above 8000 ft.
Humidity

10 to 90 percent, noncondensing

Air Flow
200 linear ft./minute min. (modules only)

2-4

CHAPTER3
THE LSI-11 BUS

3.1

CHOOSING AN 1/0 TRANSFER TYPE

3.2

DEVICE PRIORITY

Before interfacing the processor with any peripheral

Each device has an 1/0 priority based on its distance

device, the designer must determine the type of 1/0

from the processor. When two or more devices request

transfer that would be best suited for the application:

interrupt service, the device electrically closer to the

programmed I/0 transfers, DMA, or interrupt-driven

microcomputer

transfers.

(acknowledge). The microcomputer can be inhibited

will

receive

the

interrupt

grant

from issuing more grants by setting the processor’s
Programmed I/0

transfers are executed by single- or

priority to 4 in the PS word. Bit 7 in the new PS word

double-operand instructions. The instruction can be

should be a 1. If further interrupts are to be serviced,

used to input or output a 16-bit data word or an 8-bit

the processor’s priority should be 0, and bit 7 in the new

byte. By including the device’s address as the effective

PS word should be a 0. Consequently, interrupts can be

source or destination address, the user selects the input

nested to any level. Factors to consider when assigning

or output operation. In many instances, the program-

device priorities are:

mer inputs a byte from the device’s CSR to determine

that the device has input data ready or that it is ready to

Device Operating Speed — Data from a

accept the processor’s output data.

fastdeviceisavailablefor only a short period;

DMA transfers are the fastest method of transferring

devices to prevent loss of data and to prevent

data between memory and a device. They can occur

the bus from being tied up by slower devices.

highest priorities are usually assigned to fast

between processor bus cycles and do not alter processor

status in any way. Addressing, controlling the size of

Ease of Data Recovery — If data from a device is lost, recovery may be automatic, may

the data block (number of word or byte transfers in the

require manual intervention, or may be im-

operation), and type of transfer are under the control of

possible to recover; highest priorities are as-

the requesting device. The processor does not modify

signed to devices whose data cannot be

data being moved in the DMA mode. Thus, blocks of

recovered.

data can be moved at memory speeds via the DMA
transfer mode. The processor sets up these conditions

before the DMA transfer is executed.

Service Requirements — Some devices can-

not function without help from the processor, while DMA devices can operate in-

Interrupts

allow

the

processor

continue

dependently and require only minimal proc-

programmed operation (sometimes called a back-

essor intervention; devices requiring con-

ground program) without waiting for a device to be-

tinual help from the processor for servicing

come ready to transfer data. When the device does

are assigned to lowest priorities to prevent

becomeready, it interrupts the processor’s background

tyging up the processor.

program execution and causes execution of a device

interrupt service routine. After the device’s service

Both address and data are multiplexed onto the 16

routine has been executed, the background program is

BDAL lines. In addition, individual control signals se-

restored and program execution resumes at the point
where it was interrupted.

quence programmed 1/0 operations, direct memory

access (DMA), and processor interrupts. Any bus-

3-1

compatible modulecan be inserted into anybus location

of the module maintain continuity of grant signals
BIAKI L to BIAKO L and BDMGI L to BDMGO L.
These daisy-chained signals are described later.

and still receive interface signals; however, the
module’s priority, which is position-dependent along

the bus, will change.

Slots, shown as ROW A and ROW B in Figure 3-1, include a numeric identifier for the side of the module.
The component side is designated side *“1” and the
solder side is designated side ‘‘2.” Letters ranging from
A through V (excluding G, I, O, and Q) identify a
particular pin on a side of a slot. Hence, a typical pin is

3.3 MODULE CONTACT FINGER
IDENTIFICATION
DIGITAL plug-in (FLIP CHIP) modules, including
LSI-11 modules, all use the same contact finger (pin)
identification system. The LSI-11 I/0O bus is based on
the use of double-height modules. These modules plug
into a two-slot bus connector, each containing 36 lines
per slot (18 each on component and solder sides of the
circuit board). Although the LSI-11 processor module
and core memory module are quad-height modules
that plug into four connector slots, only two slots (A
and B) are used for interface purposes on the processor
module. Etched circuit jumpers on the unused portion

designated as:

Slot (Row)

Identifier
“Slot B”

BE2

| It

Module Side Identifier
“solder side”’

Pin Identifier
“Pin E”

PIN AA1

ROW A

PIN AV

pN
-~

PIN BAt

ROW B

COMPONENT SIDE

PIN BV1

PIN BV2
CP-1403

Figure3-1

Module Contact Finger Identification

Note that the positioning notch between the two rows of
pins mates with a protrusion on the connector block for

Individual connector pins, viewed from the underside
(wiring side) of a backplane, are identified as shown in
Figure 3-3. Only the pins for one bus location (two
slots) are shown in detail. This pattern of pins is re-

correct module positioning.

peated eight times on the H9270 backplane, allowing
the user to install one LSI-11 microcomputer module
(four slots) and up to six additional two-slot modules.

Quad-height modules are similarly pin numbered.
They are identified in Figure 3-2.

3-2

AAY

AA2

FOW A

Av2

A NN

@ @
N

SIDE 1

COMPONENT SIDE

H9270 POWER AND
SIGNAL CONNECTIONS

ROW IDENTIFIER
\

> oBl D olo
| °

o_o____________o_

BV1

BV2

Z |
CA

cA2 é
ROW C

é »

cVi

cve

DA1

bA2
ROW D

e o

SIDE 2

/ SR
Z

SOLDER SIDE

/ )

cP-1416

DV2 /
l/’

TYPICAL MODULE

LOCATION
(SLOTS A1-B1)

MODULE SIDE IDENTIFIER

1 = COMPONENT SIDE
2= SOLDER SIDE

O 0 0

0 0 O

®0 [253¢ 20200 on000m0

L__—__O_OOOOOOOOO

| o°
°

Quad Module Contact Finger Identification

ROW B

Figure3-2

s
SN

i
e
iy &y
& iy s

A=ON-oN

WIRE-WRAP PINS

PASS THROUGH
H9270 PC.BOARD

NI o 06 6 o Al
o o o
)
F\)OOOOOOOOO

I_OT__—____I_____—_—I_——__—__l_—___—_—
-

| o,
Le

—\

-g—_——

o e
—
-

—_——— — — — —|—_———

| <630%02srecsnooome | 1 MODULE SIDE

]

‘

/
CP-1773

Figure3-3

LSI-11, PDP-11/03 Backplane Module Pin Identification

3-3

3.4

respeétively. Applicable bus cycle timing and specifi-

BUS SIGNALS

H9270 backplane pin assignments

are

listed

cations are discussed in Paragraphs 3.12, 3.13, and

and

described in Table 3-1. Only slots A and B are listed.
However,

they

are

identical

slots

and

3.14.

Table 3-1
Backplane Pin Assignments

Bus

Mnemonic

AA1l
ABI1

BSPAREI1
BSPARE2

AD1

BSPARE4

ACT

BSPARE3

Description

Bus Spare (Not assigned. Reserved for DIGITAL use.)

AE1

SSPARE1

AF1

SSPARE2

AJl

GND

Ground — System signal ground and dc return.

AK1

MSPAREA

Maintenance Spare -— Normally connected on the backplane at each option

AL1

MSPAREA

location (not bused connection).

AM1

GND

Ground — System signal ground and dc return.

AN1

BDMRL

Direct Memory Access (DMA) Request — A device asserts this signal to request

AH1

SSPARE3

Special Spare (Not assigned, not bused. Available for user interconnections.)

[~ Spu~

PRICSSIR

bus mastership. The processor arbitrates bus mastership between itself and all

DMA devices on the bus. If the processor is not bus master (it has completed a
bus cycle and BSYNC L is not being asserted by the processor), it grants bus
mastership to the requesting device by asserting BDMGO L. The device responds by negating BDMR L and asserting BSACK L.
AP1

BHALTL

Processor Halt—When BHALT L is asserted, the processor responds by halting
normal program execution. External interrupts are ignored but memory refresh

interrupts (enabled if W4 on the processor module is removed) and DMA request/grant sequences are enabled. When in the halt state, the processor executes the ODT microcode and the console device operation is invoked.
AR1

BREFL

Memory Refresh — Asserted by a processor microcode-generated refresh in-

terrupt sequence (when enabled) or by an external device. This signal forces all
dynamic MOS memory units to be activated for each BSYNC L/BDIN L bus
transaction.
CAUTION
The user should avoid using multiple DMA data transfers [Burst or

“hog’ mode] during a processor-generated refresh operation so
that a complete refresh cycle can occur once every 1.6 ms.
AS1

PSPARE3

Spare (Not assigned. Customer usage not recommended.)

AT1

GND

Ground — System signal ground and dc return.

AU1

PSPAREI

Spare (Not assigned. Customer usage not recommended.)

AV1

+5SB

+35 V Battery Power — Secondary +35 V power connection. Battery power can
be used with certain devices.

BA1

BDCOKH

DC Power OK — Power supply-generated signal that is asserted when there is

sufficient dc voltage available to sustain reliable system operation.

3.4

Table 3-1 (Cont)

Backplane Pin Assignments
Bus

Mnemonic

BB1

BPOKH

Description
Power OK — Asserted by the power supply when primary power is
normal.
When negated during processor operation, a power fail trap sequence
is initiated.

BC1

SSPARE4

BD1

SSPARES

BE1

SSPARE6

BF1

SSPARE7

BH1

SSPARES

BJ1

GND

BK1

MSPAREB

BL1

MSPAREB

location (not a bused connection).

BM1

GND

Ground — System signal ground and de return.

BN1

BSACKL

This signal is asserted by a DMA device in response to the processor’s BDMGO

Special Spare (Not assigned, not bused. Available for user interconnections.)

Ground — System signal ground and dc return.
Maintenance Spare — Normally connected on the backplane at each

option

L signal, indicating that the DMA device is bus master.

BP1

BSPARES6

Bus Spare (Not assigned. Reserved for DIGITAL use.)

BR1

BEVNTL

External Event Interrupt Request — When asserted, the processor responds

(if PS bit 7 is 0) by entering a service routine via vector address 1004. A typical

use of this signal is a line time clock interrupt.
BS1

PSPARE4

Spare (Not assigned. Customer usage not recommended.)

BT1

GND

Ground — System signal ground and dc return.

BU1

PSPARE2

Spare (Not assigned. Customer usage not recommended.)

BV1

+35 V Power — +5 Vdc system power.

AA2

+5V Power-—Normal +5 Vdc system power.

AB2

-12

-12V Power —-12 Vdc (optional) power for devices requirin g this voltage.

NOTE
LSI-11 modules which require negative voltages contain an inverter circuit (on ench module) which generates the required volt-

age(s); hence, -12 V power is not required with DIGITAL-supplied

options.

AC2

GND

Ground — System signal ground and dc return.

AD2

+12

+12V Power — +12 Vdcsystem power.

AE2

BDOUTL

Data Output-—BDOUT, when asserted, implies that valid data is available on
BDALO—15 L and that an output transfer, with respect to the bus master de-

vice, is taking place. BDOUT L is deskewed with respect to data on the bus. The
slave device responding to the BDOUT L signal must assert BRPLY L to

complete the transfer.

AF2

BRPLYL

Reply — BRPLY L is asserted in response to BDIN L or BDOUT L and during
IAK transactions. It is generated by a slave device to indicate that it has input

dataavailable onthe BDAL bus or that it has accepted output data from the bus.

3-5

Table 3-1 (Cont )
Backplane Pin Assignments
Bus
Pin

Mnemonic

AH2

BDINL

Description

Data Input — BDIN L is used for two types of bus operations:

When asserted during BSYNC L time, BDIN L implies an input transfer
with respect to the current bus master, and requires a response (BRPLY L).
BDIN L is asserted when the master device is ready to accept data from a
slave device.

When asserted without BSYNC L, it indicates that an interrupt operation
is occurring.

The master device must deskew input data from BRPLY L.
Al2

BSYNCL

Synchronize —BSYNC L is asserted by the bus master device to indicate that it
has placed an address on BDALO—15 L. The transfer is in process until
BSYNC L is negated.

AK2

AL2

BWTBTL

BIRQL

Write/Byte — BWTBT L is used in two ways to control a bus cycle:
1. Itisasserted during the leading edge of BSYNC L to indicate that an output
sequence is to follow (DATO or DATOB), rather than an input sequence.

2. [Itisasserted duringBDOUT L, in a DATOB bus cycle, for byte addressing.
— A device asserts this signal when its Interrupt Enable and
Interrupt Request
Interrupt Request flip-flops are set. This signal informs the processor that a
device has data to input to the processor or it is ready to accept output data. If
the processor’s PS word bit 7 is 0, the processor responds by acknowledging the
request by asserting BDINL and BIAKO L.

AM?2

BIAKIL

AN2

BIAKOL

Interrupt Acknowledge Input and Interrupt Acknowledge Output — This is
an interrupt acknowledge signal which is generated by the processor in response
to an interrupt request (BIRQ L). The processor asserts BIAKO L, which is
routed to the BIAKI L pin of the first device on the bus. If it is requesting an interrupt, it will inhibit passing BIAKO L. If it is not asserting BIRQ L, the device
will pass BIAKI L to the next (lower priority) device via its BIAKO L pin and the
lower priority device’s BIAKI L pin.

AP2

BBS7L

Bank 7 Select — The bus master asserts BBS7 L when an address in the upper
4K bank (address in the 28-32K range) is placed on the bus. BSYNC L is then
asserted and BBS7 L remains active for the duration of the addressing portion
of the bus cycle.

AR2

BDMGIL

AS2

BDMGOL

DMA Grant-Input and DMA Grant-Output— This is the processor-generated
daisy-chained signal which grants bus mastership to the highest priority DMA
device along the bus. The processor generates BDMGO L, which is routed to
the BDMGI L pin of the first device on the bus. If it is requesting the bus, it will
inhibit passing BDMGO L. If it is not requesting the bus, it will pass the
BDMGI L signal to the next (lower priority) device via its BDMGO L pin. The
device asserting BDMR L is the device requesting the bus, and it responds to the
BDMGI L signal by negating BDMR, asserting BSACK L, assuming bus
mastership, and executing the required bus cycle.
CAUTION

DMA device transfers must be single transfers and must not in-

terfere with the memory refresh cycle.
AT2

BINITL

Initialize — BINIT is asserted by the processor to initialize or clear all devices

connected to the I/O bus. The signal is generated in response to a power-up
condition (the negated condition of BDCOK H).

3-6

Table 3-1 (Cont)
Backplane Pin Assignments
Bus

Mnemonic

Description

AU2

BDALOL

AV2

BDALIL

Data/Address Lines-— These two lines are part of the 16-line data/address bus
over which address and data information are communicated. Address informa-

tion is first placed on the bus by the bus master device. The same device then

either receives input data from, or outputs data to the addressed slave device or

memory over the same bus lines.

BA2

+35

+5V Power — Normal + 5 Vdc system power.

BB2

-12

-12'V Power — -12 Vdc (optional) power for devices requiring this voltage.

BC2

GND

Ground — System signal ground and dc return.

BD2

+12

+12V Power — +12 V system power

BE2

BDAL2L

BF2

BDAL3L

BH2

BDAIAL

BJ2

BDALSL

BK2

BDAL6 L

BL2

BDAL7L

BM2

BDALSL

BN2

BDAL9L

BP2

BDALIOL

BR2

BDALI11L

BS2

BDAL12L

BT2

BDAL13L

BU2

BDAL14L

BV2

BDALISL

3.5

3.5.1

Data/Address Lines -— These 14 lines are part of the 16-line data/address bus
previously described.

BUS CYCLES

transfer. The DATIO cycle provides an efficient means

General

ofexecuting an equivalent read-modify-write operation

Every processor instruction requires one or more 1/0

by making it unnecessary to assert an address a second

operations. The first operation required is a data input

time.

transfer (DATI), which fetches an instruction from the
location addressed by the program counter (PC or R7).
This operation is called a DATI bus cycle. If no additional operands are referenced in memory or in an 1/0

3.5.2

Input Operations

The sequence for a DATI operation is shown in

Figure
3-4. DATI cycles are asynchronous and require a re-

device, no additional bus cycles are required for in-

sponse from the addressed device or memory. The addressed memory or device responds to its input request

struction execution. However, if memory or a device is
referenced,

additional DATI, data input/output
(DATIO or DATIOB), or data output transfer (DATO

(BDIN L) by asserting BRPLY L. If BRPLY is not
asserted within 10us (max) after BDIN L is asserted,

or DATOB) bus cycles are required. Between these bus

the processor terminates the cycle and traps through

cycles, the processor can service DMA requests. In
addition, the processor can service interrupt requests

location 4.

only prior to an instruction fetch (DATI bus cycle) if
the processor’s priority is zero. (PS word bit 7 is 0.)

Note that BWTBT L is not asserted during the address
time, indicating that an input data transfer is to be
executed.

The following paragraphs describe the types of bus

cycles. Note that the sequences for 1/O operations be-

A DATIO cycle is equivalent to a read-modify-write

tween processor and memory or between processor and

operation. An addressing operation and an input word
transfer are first executed in a manner similar to the

I/Odevice are identical. DATO (or DATOB) cycles are

equivalent to write operations, and DATI cycles are
equivalent to read operations. In addition, DATIO
cycles include an input transfer followed by an output

DATI cycle; however, BSYNC L remains in the active
state after completing the input data transfer. This
causes the addressed device or memory to remain

3-7

SLAVE

BUS MASTER

(MEMORY OR DEVICE)

(PROCESSOR OR DEVICE)

ADDRESS DEVICE/MEMORY

Assert BDALO-15 L with
address and

Assort BBS7

if the

address is in the 28 - 32K range
e

Assert BSYNC L
\
\

\
\

DECODE ADDRESS

Store ‘‘device selected”’
operation

REQUEST DATA
e

Remove the address

from BDALO-1S5 L
and negate BBS7 L

Assert BDIN L

\
\

INPUT DATA
®

Place data on BDALO-15 L

Assert BRPLY L

TERMINATE INPUT TRANSFER
e

Accept data and respond by
negating BDIN L

TERMINATE BUS CYCLE

Negate BSYNC L

o—

Figure 3-4

OPERATION COMPLETED
¢

Terminate BRPLY L

11-3138

DATI BusCycle

selected, and an output data transfer follows without

Like the input operations, failure to receive BRPLY L

any further addressing. After completing the output

within 10us after asserting BDOUT L is an error, and

transfer, the device terminates BSYNC L, completing

results in a processor time-out trap through location 4.

the DATIO cycle. The actual sequence required for a
Note that BWTBT L is asserted during the addressing

DATIO cycle is shown in Figure 3-S. Note that the

output data transfer portion of the bus cycle can be a

portion of the cycle to indicate that an output data

byte transfer; hence, this cycle is shown as DATIOB.

transfer is to follow. If a DATOB is to be executed,

3.5.3

cycle; however, if a DATO (word transfer) is to be exe-

BWTBT L remains active for the duration of the bus

Output Operations

The sequence required for a DATO or the equivalent

cuted, BWTBT L is negated during the remainder of

output byte (DATOB) bus cycle is shown in Figure 3-6.

the cycle.

3-8

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
®

Assert BDALO-15 L with
address

Assert BBS7 L and if the

Assert BSYNC L

address is in the 28 - 32K range

\
\~

DECODE ADDRESS

Store “‘device selectad”’
operation

k’

/ -

REQUEST DATA

Remove the address from

BDALO -15L

and negate BBS7
®

L B

—— —

Assert BDIN L

—_——
\

INPUT DATA

—"

» /

Place data on BDALO-15 L

Assert BRPLY L

TERMINATE INPUT TRANSFER

Accept data and respond by
terminating BDIN L
\
\

'COMPLETE INPUT TRANSFER

Remove data

Terminate BRPLY L

OUTPUT DATA
®

Place output data on BDALO-15 L

(Assert BWTBT

L if an output

byte transfer)
®

Assert BDOUT L
—

——

—

TAKE DATA
®

Receive data from BDAL lines

Assert BRPLY L

/ /
/

k’

—'/

TERMINATE OUTPUT TRANSFER

Terminate BDOUT L, and remove

data from BDAL lines
——

—

—_—
\

OPERATION COMPLETED

TERMINATE BUS CYCLE

Negate BSYNC L

——

mm——

—

Terminate BRPLY L

-t

{and BWTBT L if in

11-3139

a DATIOB bus cycle)

Figure 3-S

DATIO or DATIOB Bus Cycle

3-9

SLAVE

BUS MASTER

(MEMORY OR DEVICE)

(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
®

Assert BDALO-15 L with

address and

Assert BBS7 L (if address

Assert BWTBT L (write

is in the 28 - 32K range)
cycle)
Assert BSYNC L

DECODE ADDRESS
e

Store “‘device selected’’
operation

OUTPUT DATA

Remove the address from

BDALO-15 L

and negate BBS7 L and BWTBT L

(BWTBT L remains active if
DATOB cycle)

e Place data on BDALO-15 L
Assert BDOUTL

TAKE DATA
®

Receive data from BDAL lines

Assert BRPLY L

/
TERMINATE OUTPUT TRANSFER

Remove data from BDALO-15L
and negate BDOUT L

OPERATION COMPLETED
® Terminate BRPLY L

TERMINATE BUS CYCLE
¢

Negate BSYNC L (and BWTBT L

‘/

if a DATOB bus cycle)

11-3140

Figure3-6

DATO or DATIOB Bus Cycle

3-10

3.6

DMA OPERATIONS

DMA 1/0 operations involve a peripheral device and
system memory. A device can transfer data to or from
the 4K memory on the processor module or any read/
write memory module along the bus. The actual sequence of operations for executing the data transfer
once a device has been granted DMA bus control is as
previously described for input and output 1/0 bus
cycles, except the DMA device, not the processor, is
bus master (controls the operation). Memory ad-

dressing, timing, and control signal generation/
response are provided by logic contained on the
device’s DMA interface module; the processor is not
involved with address and data transfers during a
DMA operation.

The required DMA sequence is shown in Figure 3-7. A
device requests the 1/0 bus by asserting BDMR L.
After completing the present bus cycle, the processor
responds by asserting BDMGO L, allowing the device

LSI-11 PROCESSOR
DEVICE

{(MEMORY IS SLAVE)

REQUEST BUS
Assert BDMR L

_—

GRANT BUS CONTROL
o

Near the end of the current

—

bus cycle (BRPLY L is negated),
assert BOMGO L and inhibit
new processor generated

BSYNC L for the duration
of the DMA operation.

\
\

ACKNOWLEDGE BUS MASTERSHIP

® Wait for negation of

BSYNC L and BRPLY L

TERMINATE GRANT SEQUENCE
®

‘/

Assert BSACK L

Negate BOMR L

Negate BDMGO L and

wait for DMA operation
to be completed
\
\\

\
\

EXECUTE A DMA DATA

T TRANSFER (DEVICE IS
BUS MASTER)
®

Address memory and transfer
data as described for DATI,

DATIO, DATIOB, DATO,
DATOB bus cycles
o

Release the bus by

terminating BSACK L
(no sooner than negation

of last BRPLY L) and
BSYNC L.

RESUME PROCESSOR
OPERATION

Enable processor-generated

BSYNC L (Processor is
Bus master) Or issue
another grant if BDMR L
is asserted.

Figure 3-7

DMA Request/Grant Sequence

3-11

11-3141

to become bus master. It also inhibits further processor

The

generation

processor-

required for interrupts is shown in Figure 3-8. A device

initiation of a new bus cycle. The device responds by

requests interrupt service by asserting BIRQ L. The

BSYNC

preventing

interface

control

and

data

signal

sequence

asserting BSACK L and negating BDMR L, causing

processor can acknowledge interrupt requests only

the processor to terminate BDMGO L; the device is

between instruction executions by generating an active

now bus master and it can execute the required data

(low) BDIN L signal, enabling the device’s vector re-

transfer in the same manner described for a DATI,

sponse. The processor then asserts the BIAKO L signal.

DATIO, DATIOB, DATO, or DATOB bus cycle.

The first device on the bus receives this daisy-chained

When the data transfer is completed,

the device

signal at its BIAKI L input. If it is not requesting ser-

returns bus master control to the processor by termi-

vice, it passes the signal via its BIAKO L output to the

nating the BSACK L and BSYNC Lsignals.

next device, and so on, until the requesting device receives the signal. The device that did not pass the

3.7

INTERRUPTS

BIAKO L signal responds by asserting BRPLY L (low)

Interrupts are requests made by peripheral devices

and placing its interrupt vector on data/address bus

which cause the processor to temporarily suspend its

lines BDALO—1S L. Automatic entry to the service

present (background) program execution to service the

routine is then executed by the processor as previously

requesting device. Each device which is capable of

described.

requesting an interrupt has a service routine which is

NOTE

automatically entered when the processor acknowl-

If a device fails to assert BRPLY L in response

edges the interrupt request. After completing the

to BDIN L within 10 u sec, the processor enters

service routine execution, program control is returned

the Halt state.

to the interrupted program. This type of operation is
especially useful for the slower peripheral devices.

3.8

BUS INITIALIZATION

Devices along the I/0 bus are initialized whenever the
A device can interrupt the processor only when inter-

system dc voltages are cycled on or off, or when a

rupts are enabled and the device is the closest device to

RESET instruction is executed. Initialization during

the processor along the I/O bus. The processor’s

the power-on/power-off sequence is described in Para-

priority in the PS word is 4 when external interrupts are

graph 3.9. When the RESET instruction is executed,

disabled and 0 when external interrupts are enabled.

the processor responds by asserting BINIT L for ap-

Device priority is highest for devices electrically closest

proximately 10us. Devices along the bus respond to the

to the processor along the bus.

BINIT L signal, as appropriate, by clearing registers

and presetting or clearing flip-flops.
Any device that can interrupt the processor can also
interrupt the service routine execution of a lower

3.9

priority device if the processor’s priority is 0 during that

Power status signals BPOK H and BDCOK H must be

POWER-UP/POWER-DOWN SEQUENCE

execution; hence, interrupt nesting to any level is

asserted or negated in a particular sequence as dc

possible with this interrupt structure. Each device

operating power is applied

normally contains a control status register (CSR),

BDCOK H and BPOK H are passive (low). As dc

which includes an interrupt enable bit. A program

voltages rise to operating levels, BINIT L is asserted by

must set this bit before an interrupt request can

the processor module. Approximately 3 ms (min) after

actually be granted to a device.

removed.

Initially,

+5Vand +12V power are normal, an external signal
source, or the H780 power supply in PDP-11/03

An interrupt vector associated with each device is

systems, produces an active BDCOK H signal; the

hard-wired into the device’s interface/control logic.

processor responds by negating BINIT, and waits for

This vector is an address pointer that allows automatic

BPOK H. The BPOK H

entry into the service routine without device polling.

ternal signal source or the H780 power supply, goes

signal, produced by an ex-

true (high) 70 ms (min) after BDCOK H goes high. The
When an interrupt request is issued via the external

processor responds by executing the

event signal line, the processor automatically services

power-up routine (Chapter 5); if BHALT L is asserted,

the request via location 100, ; it does not input a vector

the console microcode is executed.

user-selected

address as done for other external interrupt devices.
This interrupt function is normally used for a line time

During a power-down sequence, the external signal

clock input based on the frequency of the local ac

source first negates BPOK H, causing the processor to

power (S0 or 60 Hz).

execute the power-fail trap (PC at 024, PS at 026).

3-12

PROCESSOR

DEVICE

INITIATE REQUEST

STROBE INTERRUPTS
¢

Assert BDIN L

-g

Assert BIRQ L

RECEIVE BDIN L
®

Store ‘‘interrupt selected””
in device

GRANT REQUEST
®

Pause and assert

BIAKO L

RECEIVE BIAKI L
®

Receive BIAK | L and inhibit

BIAKOL

Place vector on BDAL 0-15 L

Assert BRPLY L
Terminate BIRQ L

7’

RECEIVE VECTOR & TERMINATE

r 4

REQUEST
®

|nput vector address

Terminate BDIN L and BIAKO L

COMPLETE VECTOR TRANSFER
®

Terminate BRPLY L

PROCESS THE INTERRUPT

Save interrupted program PC

and PS on stack

Load new PC and PS from
vector addressed location

Execute interrupt service

11-3142

routine for the device

Figure 3-8

Approximately

(max)

later,

Interrupt Request/Acknowledge Sequence

processor

interface module when the Framing Error Halt is

initializes the bus by asserting BINIT L in response to

the

enabled (Paragraph 6.2.2.8). Note that when in the

the external signal negation of BDCOK H.

Halt mode, the processor arbitrates DMA requests,
and refresh operations. Thus, in addition to bus trans-

3.10

HALT MODE

actions between the processor and the console device,

The BHALT L bus signal can be asserted low to place

bus transactions can occur for DMA and refresh.

the processor in the Halt mode. When in the Halt
mode, the RUN indicator (PDP-11/03 only) is ex-

3.11

tinguished, interrupts external to the processor module

Memory refresh operations are required when any

MEMORY REFRESH

are ignored, and the processor executes the console

dynamic MOS memory devices are used in a system.

ODT microcode. Although the user could assert this

These memory devices are included on KD11-F and

line by a separate switch or a custom module, it is

MSV11-B modules. Memory refresh is normally con-

normally asserted by the

switch

trolled by the processor microcode, which is auto-

(PDP-11/03 only) or the user-designated device’s SLU

matically executed once every 1.6 ms. However, refresh

HALT/ENABLE

3-13

could be controlled by a user-supplied DMA device on

Bus Drivers and Receivers
Recommended Bus Drivers

‘the bus. (For example, when used in an intelligent

Type 957,

P/N DEC 8881-1, quad 2-input
NAND gates (Refer to specifications in the
Hardware/Accessories Catalog.)

terminal application, the refresh logic could be included on the user’s DMA interface module.)

A complete refresh operation requires 64 BSYNC/
BDIN transactions which must be completed within 2
ms. The processor (or other device controlling the refresh operation) first asserts BREF L for each BSYNC/
BDIN transaction during the addressing portion of
each refresh operation. BREF L causes all dynamic
MOS memory devices to be simultaneously enabled
and addressed, overriding local bank selection circuits.
Refresh is then accomplished by executing 64 BSYNC/
BDIN transactions, in a manner similar to the DATI
bus cycle, incrementing the “row’’ address (bits. 1—6)
once for each transaction. Address bit O is not signifi-

bus receiver and two bus drivers and less than 10 pF of

cant in the refresh operation. When refresh is con-

circuit board etch. Bus terminations are shown in

trolled by processor microcode, the operation takes ap-

Figure 3-9.

Recommended Bus Receivers

Type 956, P/N DEC 8640, quad 2-input NOR
gates (Refer to the specifications in the Hardware/Accessories Catalog.)
Recommended Bus Transceivers
Type DEC 8641, quad unified bus transceiver.

3.13

BUS CONFIGURATIONS

In the following descriptions, a unit load is equal to one

proximately 130us.

+5V

Note that only one dynamic MOS memory device is required to assert BRPLY L during the refresh BSYNC/
BDIN transactions. This should be performed by the
slowest device on the bus. MSV11-B modules each
contain a jumper which the user can insert to prevent
the module from asserting BRPLY L during refresh
operations. The slowest memory device will normally
be the MSV11-B module located the greatest electrical
distance from the processor module along the bus.

3.12

+5V

3300

1788
1%

2509

12080

BUS LINE
TERMINATION

3830

68048

Figure 3-9

cp-1828

BusLine Terminations

Minimum Configuration (Figure 3-10)
1.

BUS SPECIFICATIONS

The processor terminates the bus lines to Zt
= 250 Q.

Electrical

Refer to electrical specifications listed in Paragraph 2.9.

Ten-inch maximum backplane wire (each
bus line for a 4 by 4 backplane), 6 unit loads
or less.

NOTE
All bus lines are open-collector, resistor-

Intermediate Configuration (Figure 3-11)

terminated to a 3.4 V nominal.
1.

The processor terminates the bus lines to

Zt = 250 Q.

BACKPLANE WIRE

10"MAK
(

)

ONE
UNIT

2508

1
]
ONE
UNIT

LOAD

ONE
UNIT

LOAD

3.4V

6 UNIT LOADS

PROCESSOR

Figure3-10

cP-1829

Minimum Configurations

3-14

BACKPLANE WIRE

{(
IR}

3.4V

PROCESSOR
’

—

1200

LOAD

ONE
UNIT

2508

14" MAX.

15 UNIT LOADS

.
Figure3-11

.
.
.
Intermediate Configuration

BACKPLANE WIRE

3.4V

TERM

cCP-1830

8"MAX.
_((

[
ONE

ONE

LOAD

3.4V

3.4v

—

25080

UNIT

2508

5 UNIT LOADS MAX.

CABLE/TERM

PROCESSOR
8"MAX.
4

ONE
UNIT
LOAD

CABLE
CABLES

CABLE

_
—
6 UNIT LOADS MAX.

ADDITIONAL

8 BACKPLANES

BACKPLANE WIRE

8"MAX.

(¢

ONE
UNIT
LOAD

1200
+

CABLE

3.4y

UNIT LOADS MAX.

:
NOTES

1. THREE CABLES (MAX.),15ft. (MAX.)

TERM

TOTAL LENGTH.

2. 15 UNIT LOADS TOTAL(MAX.)

Figure 3-12

Maximum Configuration

backplanes); 6 unit loads maximum each
backplane, 15 unit loads total (maximum);
daisy-chained on 2 ft (minimum) 120 Q
cable, three cables maximum, total cable

Fourteen-inch maximum backplane wire
(each bus line for a 9 by 4 backplane), 15
unit loads or less.
3.

Anadditional 120 Q termination s required.

length not exceeding 15 ft.

Maximum Configuration (Figure 3-12)
1.

The processor terminates the bus lines to
Zt = 250 @ .

cP-1831

3.14

Two additional terminations (one 250 @
and one 120 Q ) are required.

BUS SIGNAL TIMING

Bus signal timing requirements at master and slave
devices are shown in Figures 3-13 through 3-18.

Eight-inch maximum backplane wire on

each backplane (each bus line for 4 by 4
3-15

T/R DAL

(4) x

ADDR

(4)
MIN

—’T

DATA

(4)

fe— 200 ns MAX

SYNC
l—————
{50 ns MIN
/

200ns

MIN —

300 ns MIN ——————p»
R

RPLY
_>|

15
ns 0
MIN

|&—

I._1oon5

MIN

B887

(4)

WTBT

(4)

4)
TIMING AT MASTER DEVICE

R/T DAL

(4)

ADDR X

—»y 2008 l~—

SYNC

/
75ns

(4)

—

DIN

RPLY

DATA

L’—iZSns MAX

— |——1oo ns MAX

(4)

f4————{50ns MIN

MIN

‘\

150ns MIN -

\ Ic—soo ns MIN——————»,

(4) _—.!X
R

WTBT

(4)

l— 75ns MIN

L—25ns MIN

(4)
TIMING AT SLAVE DEVICE

NOTES!

Timing shown ot Master and Slave Device

Bus Driver inputs and Bus Receiver Outputs.
.

Signal name prefixes are defined below:

T =
R =

Bus Driver Input
Bus Receiver Output

Bus Driver Output and Bus Receiver Input

signal names include a "8 prefix.

Don't care condition.
cP-1774

Figure 3-13

DATI Bus Cycle Timing

3-16

—hl Ons MIN r——

T DAL

(4) X

ADDR

DATA

150ns_y 100
l“mr?"l
MIN i"

T SYNC

150ns MIN

(4)
\

L—200ns MIN —

L—

300ns MIN ——»

F
-»>

‘4—100ns MIN

(4) X

150 nsMIN

(4)

j&—

ASSERTION = BYTE

L150nsMIN-> 13?,;‘5 L—

(4)

ADDR

‘

—

R SYNC
R DOUT

75ns

MmN

DATA

25ns MIN

—

MIN

L—ZSnsMIN

R BS7

(4) X

R WTBT

(4) /

2505 _,.
—DI 75 ns MIN

(4)

r—100nsMIN —-L—ISOnsMIN—h
——| 150 ns MIN A

MIN

T RPLY

(4)

MASTER DEVICE

25ns

—-l 100 ns MIN L—

TIMING AT

R DAL

l@—175 ns MIN

R RPLY

T WTBT

> 100MIN L_

I-—-100ns MIN

T DOUT

T BS7

‘4—300nsMIN——>
\\\

|e—

25ns MIN 4

—>

\/
75ns —
MIN

ASSERTION = BYTE

(4)

|<—25ns MIN
x

(4)

25ns MIN
TIMING AT SLAVE DEVICE

NOTES:

Timing shown at Master and Slave Device
Bus Driver Inputs and Bus Receiver Outputs.

2. Signal name prefixes are defined below:
T =
R =

Bus Driver Input
Bus Receiver Output

Bus Driver Output and Bus Receiver input

signal names include a " B" prefix.

4. Don't care condition.
CP-1775

Figure3-14

DATO or DATOB Bus Cycle Timing

3-17

& ADDR )(

|<—Om MIN

|'-—150ns MIN

R/T DAL

100ne

(4)

DATA X

— —»y200ns

(4)

DATA

/7f

T DOUT

L—lOO ns MIN

- 150ns MIN—’l

200 ns MIN—»

DIN

/
R

(4)

[]

100 ns MIN‘-| r— o— a0 IR

T SYNC

///

VL MIN TM
300ns

RPLY
150 ns

"I MIN [*

BS7

XX
—

le— 100 ns MIN

—»{ 100 ns MIN ‘-—

T WTBT (4>\L

(4)

—>|

R/T DAL

(4)

la— {50 ns MIN
ADDR)(

—

(@)

"-25ns MIN

TIMING AT

oata

—>

ASSERTION = BYTE

(4)

MASTER DEVICE

40ns MIN

DATA

— L—25 ns MIN

(@)

SYNC

<—

75ns MIN 25

R DOUT

25ns MIN

r—

—» 100
ns MIN

WMax [+

150ns MIN fe-

b— 1 50 ns MIN —

RPLY
—-‘

)

'4—150 ns MIN— [ le— 300 ns MIN —»

t— 75 ns MIN

BS7

—-I

e— 75ns MIN

R WTBT (4%

(4)
—]

e— 25ns MIN

ASSERTION = BYTE

—»

25ns MIN

(4)

25ns MIN
TIMING AT SLAVE DEVICE

NOTES:
I.

Timing shown at Requesting Device

Signal name prefixes are defined below:

Bus Driver Inputs and Bus Receiver Qutputs.

T =
R =

Bus Driver Input
Bus Receiver Output

Bus Driver Output and Bus Receiver Input

signal names include a "B" prefix.
4. Don't care condition.
CP-1776

Figure 3-15

DATIO Bus Cycle Timing

3-18

IRQ

INTERRUPT LATENCY
MINUS SERVICE TIME

—-P‘

R DIN

150 ns MIN. f&—

T RPLY

—

T DAL

R SYNC

(UNASSERTED)

BS7

W/—q J\
‘.I

125 ns MAX. |-'—

VECTOR

MAX.

100 ns

NOTES:
1.

Timing shown at Requesting Device Bus Driver Inputs and Bus Receiver Outputs.

Signal Name Prefixes are defined below:
T = Bus Driver Input
R = Bus Receiver Qutput

3. Bus Driver Output and Bus Receiver Input signal names include a "B" prefix.
CP-1777

Figure3-16

Interrupt Transaction Timing

SECOND
REQUEST

l«— DMA LATENCY
—r 7 7T
/
/S
7/

r—

\‘\ /

DMR

O ns MIN.
[———————

DMG

SACK

NN
-

250 ns MIN.—»

R/T

SYNC

NN
0 ns MIN—-I

250ns MIN —

R/T

RPLY

r— 300 ns MAX

DAL

(ALSO BS7,
WTBT, REF)

/
N\

O ns MIN

'4— 100 ns MAX

O ns MIN

X
ADDR

DATA

Timing shown at requesting device bus driver inputs and bus receiver ou tputs.

Signal name prefixes are defined below:

T = Bus Driver Input
R = Bus Receiver Qutput

3. Bus Driver Output and Bus Receiver Input signal names inciude a "B" pre fix.
cP-1778

Figure 3-17

DMA Request/Grant Timing

—»1
BINIT

BPOK

BDCOK

——~>! Sms
DC

7OmsMIN e

'474—20,15

[

4 ms MIN —»]

e 8msMIN ————»{

—-1 70ms MIN l-—
5 usMIN ’4—

POWER

POWER UP

NORMAL

SEQUENCETM —"T* POWER

POWER DOWN

SEQUENCE

POWER UP

*—"SEQUENCE

NORMAL

*~ pPOWeER TM
CP-1779

Figure 3-18

Power-Up/Power-Down Timing

3-20

CHAPTER4
LSI-11 MODULE DESCRIPTIONS

4.1

GENERAL

This chapter contains detailed descriptions of each
LSI-11 module. The level of coverage is sufficient to

enable users to interface

their

systems

with

the

PDP-11/03 or LSI-11 using standard LSI-11 modules
or user-designed interfaces. Refer to Chapter 3 for de-

tailed bus timing information.

LSI-11 modules covered in this chapter are listed in
Table 4-1. Note that a separate description for the

KD11-J microcomputer is not provided; it comprises
the same M7264 module as the KD11-F microcomputer, except that a resident semiconductor memory is
not supplied.

Instead,

the MMV11

Table 4-1
LSI-11 Modules

Option

Module
Number

KD11-F

M7264

Module Option

Description
Para. No.

LSI-11 microcomputerand | 4.2

4K semiconductor memory
KD11-]

M7264-YA,

H223,

LSI-11 microcomputer and | 4.2

4K core memory

G653

" KEV-11

—

EIS/FIS processor chip

4.2

MMV11-A

H223, G653

4K by 16-bit core memory

4.3

‘MRV11-A

M7942

4K by 16-bit PROM

4.4

‘MSV11-B

M7944

4K by 16-bit dynamicread- | 4.5

write memory
MSV11-A

M7943

1K by 16-bit static read-

4.6

write memory

'DLV11
‘DRV11

M7940

Serial line unit

4,7

M7941

Parallel line unit

4.8

Power Supply

4.9

H780-A and
H780-B

core

module is supplied with the KD11-J option.

memory

Figure4-1. KD11-F microcomputers features are given

4.2 KD11-F MICROCOMPUTER

4.2.1

in Paragraph 2.3.

General

NOTE
The following description reflects the circuits
n CS M7264 Rev. E.
in drawing
show

The KD11-F microcomputer is contained on a single
8.5 by 10 inch printed circuit board (M7264). The
module includes all basic microcomputer functions
common to both the KD11-F and KD11-J micro-

AP2 ,[§]) BBST7 L
AV2_ 51 soALg L
/—A—-

computers and a resident 4K by 16-bit semiconductor
read/write memory.
y KD11-F functions are shown in

1§ soaLt L

€2

BlsoaL2L

BF2

BANK 7

EC.T:

0-15L

G_____>

0-21L

[B] BDALSB L

5] BDALO L

BN2_
BP2

18] soaL1O L

BR2

—————{B] BDAL1I L

[PALG-ISH

BSZ 5] BDALI2 L

INTERNAL

ROM

CONTROL

|_,

N__Bu2 g
8] BOAL14 L

BDALIS L

\V4

READ
DATA

ADDRESS
AND WRITE

RESIDENT

MICRO-

INSTRUCTION | TIMING &
CHIPS

oais L

BDAL13 L

W]
| :WG

<::—’1>

K-

MUX

PROCESSOR

MEM READ

DIN

s L
1o aonL

RECE!VERS

WDALZ-15H
1/0 BUS/

FAST

BK2

BLZ [F]epAL7L

DRIVERS
g

WDAL@-15 H

WDALZ - 3H

(8] BDALS L

892

DECODER

PROCESSOR

8] 80AL3 L

BHa

MEMORY

DATA

(KD11-F ONLY)

SIGNALS

w1
w2

RPHI-4
H

21070

‘}’

AJz 8] BSYNC L

AKZ /5] BWTBT L

BUS

)

AH2

I/0

AE2 »[B] BDIN

CONTROL

PROCESSOR

LOGIC

_> CONTROL
CHIP

- »{B] BDOUT L
»{B] BRPLY L

BB! 18] 8POK H

:
r
M kEv-11

: OPTIONAL |
|

0-21L

EIS/FIS

CHIP

MICROCODE

BR1 8] BEWNT L
ALZ 5] BIRQ L

RESET
Logic

AN2 =@ BIAKO L

‘sz::
i

BUS

;:: {6] BOMR L

LOGIC

52 ,[8] BDOMGO L

ARBITRATION

SPECIAL
||

[

+12VA

+12V<—\

GENERATOR

|—#PH1-4H

PULSE

FUNCT IONS

[
> PHI-4 L

-9ve—{
-5Ve—]

DIVB (0) H

Dc-DC

—{B] BSACK L

ARl 5] BREF L

CONTROL

18-21L

CLOCK

8] BHALT L

APt

COQLRDOL

[8] BDCOK H

BA1

INTERRUPT

AT2_[B] BINIT L
BD2

12v

AD2

— r2v
+5v < AA2BAZ L]

POWER

INVERTER | ACZ,A01AMI,ATIBC2,801,BM1,BT1.DI1
) gy,

=
11-3143

Figure4-1

KD11-FMicrocomputer Logic Block Diagram
4.2

4.2.2

Basic Microcomputer Functions

Thedatachip contains the data paths, logic, arithmetic

Basic functional blocks of the LSI-11 microcomputer

logic unit (ALU), processor status bits, and registers

are shown in Figure 4-1 and described in the following

that are most familiar to PDP-11 and LSI-11 users.

paragraphs. The KD11-F’s resident memory is de-

Registers include the eight general registers (RO—R?7)

scribed separately (Paragraph 4.2.3).

and an instruction register. The user’s program has
access to all general registers and processor status (PS)

4.2.2.1

Microprocessor

Chip

Set —

The

main

bits. All PDP-11 instructions enter this chip via the

function contained on the processor module is the

WDAL bus. Data and addresses to and from the

microprocessor chip set. This chip set includes a control

microprocessor are also transferred to and from the

chip, a data chip, and two microinstruction ROM

processor over this 16-bit bus.

chips (microms). In addition, an optional KEV-11
microm that contains EIS/FIS microcode can be in-

stalled

the

module.

Microprocessor

chips

CAUTION

communicate with each other over a special 22-bit

Donotremove processor chips from their sockets.

microinstruction bus, WMIBO0-21 L. All address and

Improper handling could permanently damage

data communication between the microprocessor chips

the chips.

and other processor module functional blocks is via the
data

chip

and

the

16-bit

data/address

lines,

WDALO-15 H (from the data chip).
4.2.2.2

Clock Pulse Generator — The clock pulse

Processor module control signals interface with the

generator produces four nonoverlapping clock signals

microprocessor chips via the control chip. Eight input

for processor timing and synchronization. A voltage-

and five output microprocessor control signals provide

controlled oscillator generates a basic CK H signal,

this function.

ranging from 10 to 13 MHz (10 MHz is nominal).

Timing and synchronization of all microprocessor

Maintenance clock gates receive and distribute the

chips (and all processor module functions) are con-

basic CK H signal to a two-stage counter and an RC

trolled by four nonoverlapping clock generator signals

filter circuit. The two-stage counter outputs are de-

(Paragraph 4.2.2.2). Typical operating speed is ap-

coded by the four-state decoder, producing the basic

proximately 360 ns (90 ns each phase), based on an

four nonoverlapping clock phases. The pulse produced

on the leading edge of each basic clock pulse inhibits

11.1 MHz oscillator signal.

the decoder for 10 ns, preventing the overlap of each

The control chip generates a sequence of microin-

phase. Each of the four phase signals (RPH1 through

struction addresses which access the microinstruction

RPH4) are positive-going, MOS-compatible 100 ns

microm chips. The addressed microinstruction is then

(nominal) pulses which are bused to each of the micro-

transferred to the data and control chips. Most of the

processor chips through resistors. PH1 L through PH4

microinstructions are executed by the data chip; how-

Land PH1 H through PH4 H are similarly timed; how-

ever, various jumps, branches, and I/0 operations are

ever, they are TTL-compatible for distribution else-

executed in the control chip.

where on the module.

[——> DIVB (0) H (DC-DC INVERTER CLOCK)

11 MHz (APPROX)

2-STAGE

COUNTER

MAINT

MCKD

+3v

MAINT

CLOCK

Y
0

oscC

GATES

MCK L-———%———'

-4

RPH1-4H

DECODER

oH1-4

PHI-4

AND

DISTRIB
NON-OVERLAP

SIGNALS

4 -STATE

PULSE

+5v

ti-3144

Figure4-2

Clock Pulse Generator

4.2.2.3

Bus Interface and Data/Address Distribu-

EDAL L is a control signal which enables the 16-bit

tion
— Al LSI-11 processor module communication to

data/address bus drivers. When in the active state,

and from external I/0 devices and memories is ac-

EDALL

complished using the LSI-11 bus 16-bit data/address

bus.

gates WDALO—15 H onto the BDALO—15 L

lines (BDALO-15 L) and bus control signals. The processor module interfaces to the bus using bus driver/

EDAL L is generated by the logic shown in Figure 4-4.

receiver chips, as shown in Figure 4-3. Each DEC 8641
chip contains four open-collector drivers and four

During a processor-controlled address/data output

bus cycle, or during the addressing portion of a proc-

high-impedance

essor-controlled

receivers.

Each

driver

output

input

bus

cycle,

SACK

and

common to a receiver input. Hence, either processor

DMG(1) L are passive (high). The passive signals are

output data (from the driver outputs) or input data

gated, producing a low (passive) DMGCY H signal.
This signal is inverted and gated with the passive DIN L

(from the bus) can stimulate bus receiver inputs.

signal, producing the active EDAL L signal. During a
DMA cycle in which data in the processor module’s
resident 4K memory is to be read by a DMA device,

Note that all four drivers in a chip are enabled or dis-

BANK OR REF H goes high; this signal is gated with

abled by a pair of DRIVER ENABLE L inputs. A high

DINR H and DMG CYCLE H to produce the active

input will inhibit all four drivers; when both enable

EDAL L signal.

inputs are low, the drivers are enabled and output data

is gated onto the bus. Signals which control bus drivers

DMGCY H and INIT (1) H are processor module logic

include EDAL L, INIT (1) H, and DMGCY H. False
states

enable

certain

control

signals

which

control signals which inhibit certain bus drivers during

are

an Initialize or DMA operation.

described later.

[ —O

CONTROL BIT (H) »—

LOGICAL:

3300

OUTPUT DATA/

ENABLE L\

drivers

+*Vz. 2500

sus

DRIVER

Bus

are

enabled when these signals are in the false (low) state.

DRIVER

120.4V

TYP.

0=3.3V TYP

DRIVER ENABLE H

6500
BUS

RECEIVER

> EQ%A%UCSONTROL

COBIT (L)

INPUT DATA/
CONTROL BIT (H)
11-3145

Figure4-3

LSI-11BusLoading and Driver/Receiver Interface

DINR H —
BANK OR REF H —-

—

SACK L

DMG(1)

DMGCY H

‘

L
DIN L —~
CP-1826

Figure4-4

EDALL Logic

4-4

A list of bus driver output signals and their respective

Sync flip-flop sets, producing an active (high) SYNC

enable signals is provided below.

(1) H input to the BSYNC L bus driver. SYNC (1) H is
gated with REPLY (1) H (when active) to produce a
direct preset input to the Sync flip-flop. This ensures

Bus Driver

Enable Signal(s)

that BSYNC L will remain active until after the bus

(Signal)

(Low=Enable)

slave device terminates its BRPLY L signal and the
Reply flip-flop is reset. [REPLY (1) His low.] The Sync

BDALO-1SL

flip-flop then clocks to the reset (BSYNC L passive)

|[EDALL

state on the trailing edge of PH3 L.

BSYNCL
BBS7L
BREFL

BWTBT L — BWTBT L is the buffered/inverted

INIT (1) H, DMGCY H

control chip WWB H output signal. This signal asserts

BIAKOL

during PH1 of the addressing portion of a bus cycle to
indicate that a write (output) operation follows. It

BDMGL
BRPLY L
BDINL

remains active during the output data transfer if a

INIT(1)H

DATOB bus cycle is to be executed.

BDOUTL
BWTBTL

BINITL

BDIN L — BDIN L is the inverted, buffered control

chip’s WDIN H signal. This signal goes active during

Always enabled

PH2 following an active RPLY H signal.
BDOUT

L — The control chip initiates the BDOUT L

signal sequence by raising WDOUT H during PH2.

The near-end bus termination resistors are contained

This signal is gated with the passive REPLY (1) L

on the processor module. Each bus driver output is terminated by a pair of resistors, as shown in the figure,
establishing the nominal 250 Q busimpedance and the
3.4V nominal voltage level. No additional terminations
are required for bus-compatible devices connected to

(high) signal to produce an active low D input to the
DOUT flip-flop. The flip-flop sets on the leading edge
of PH3 H, producing an active BDOUT L

signal. It

clocks to the reset state on PH3 following the REPLY

(1) L active (low) signal.

the same backplane.

BRPLYL — BRPLY L is a required response from a

Address and data information are distributed on the
processor module via the WDALO-15 H and DALO-15

bus slave device during input or output operations.

H 16-bit buses. WDALO-15 H interface directly with
the microprocessor’s data chip, the DEC 8641 bus
drivers, and the I/0O bus/memory read data multiplexer. All processor input data from the I/O bus is via
the bus receivers, the DALO-15 H bus, the data multiplexer, the WDALO-15 H bus, and the microprocessor’s data chip. Resident memory data input is dis-

I70 L signal whenever a programmed transfer occurs.

DINL and DOUT (1) L are ORed to produce an active

I70 L enables the time-out counter in the bus error detection portion of the interrupt logic. I/O L is inverted
to produce I/O H, which enables the reply gate REPLY
H signal input to the control chip.
BRPLY L is received either from the LSI-11 bus or

resident memory and inverted to produce a high input

cussed later.

to the Reply flip-flop. PH1 H clocks the flip-flop to set
state, producing active REPLY (1) H and REPLAY (1)

4.2.2.4

Bus I/0 Control Signal Logic — Bus 1/0

L signals. REPLY (1) L is ORed with DMR (1) L to

control signals include BSYNCL, BWTBTL, BDINL,

produce an active BUSY H signal. The processor’s

BDOUTL, and BRPLY L. In addition, BIAKO L can

control chip responds by entering a wait state, in-

be considered a bus I/0 control signal; however, since
it is only used during the interrupt sequence, it is discussed in Paragraph 4.2.2.6. Logic circuits which
produce and/or distribute these signals are shown in
Figure 4-5. Each signal is generated or received as
described in the following paragraphs.

hibiting completion of the processor-generated bus
transfer for the duration of REPLY (1) L. REPLY (1) H

is gated with I/O H to produce an active REPLY H
signal, informing the processor that the output data

has been taken or that input data is available on the
bus. REPLY H goes passive when 1/0 H goes passive.

The bus slave device will then terminate the BRPLY L

BSYNC L — The control chip initiates the BSYNC L
signal sequence by raising WSYNC H during PH2.

signal, indicating that it has completed its portion of

the data transfer. On the next PH1 H clock pulse, the

Inverters apply the high SYNC H signal to the Sync

Reply flip-flop resets and REPLY (1) H and L and

flip-flop D input. On the trailing edge of PH3 L, the

BUSY H go passive.

SYNC (1) H

REPLY (1) H—]

WSYNC

)

PH3

DM@l——o
CYH

L —

—

SYNC
(1) L

1AK

WWB

BSYNC L

SYNCR

D‘:

WDIN H

4{::>c |

DIN

c{:>> |

WTBTR

DIN H

INIT (1) H—O|

BDIN L
)

1/0

PROCESSOR

BWTBT

1oL

DINR H

DINR L

WDOUT H

REPLY (1) L—

E——

-+ DOUT (1) L
DOUT
F/F

PH3

DOUT (1) H

H—

SYNC Hj

BDOUT L

INIT (1} H
‘—— DOUT (1) H
DOUTR H

1/0 H

REPLY H

/
{

——J

(N
H
-

BRPLY L FROM KD11-F
RESIDENT MEMORY

REPLY (1) L<—I
BUSY

BRPLY L

F/F

DMR (1) L

RPLYR

—— PHI

|N|T(1)L—I

\/
11~ 3146

Figure4-S

Bus1/0 Control Signal Logic

4-6

Bank7 Decoder—
The bank 7 decode circuit

all active (high). This address is decoded and BBS7 L is

is shown in Figure 4-6. Buffers receive WDALO-15S H

4.2.2.5

asserted. When active, BBS7 L enables addressing of

bits and distribute them to the bank 7 decoder and

nonmemory devices along the bus. During interrupt

BDAL bus drivers. Bank 7 is decoded during the ad-

vector bus transactions, IAK L becomes asserted. IAK

dressing portion of the bus cycle. If a peripheral device

L inhibits WDAL15 H, preventing BBS7 L signal gene-

address is referenced, an address in bank 7 (28-32K

ration, which could result in an invalid input data

address space) is used, and WDAL13, 14, and 15 H are

transfer.

PROCESSOR

DATA

CHIP

WDALO-15H BUS

BDAL

BUS

DRIVERS

@
m

[

13
14

[7p)

13
BUFFERS

BANK 7
DCOR.

INIT()H

—Of

TAK L—T
cP-1780

Figure4-6
4.2.2.6

Interrupt Control and Reset Logic — In-

Bank 7 Decoder
If the power failure continues, BDCOK H goes passive

terrupt control and reset logic functions are shown in

(low) and produces an active DC LO L signal, clearing

Figure 4-7. Reset functions include bus error and

the Power-Fail flip-flop and the power-fail/halt and

power-fail (BDCOK H negated). Interrupt functions

reset latches and initializing the processor and all

include power-fail (impending), Halt mode (console

devices (Paragraph 4.2.2.1). The active RESET L

microcode control), refresh interrupt, event (or line

signal then initializes the processor, causing it to abort

time clock) interrupt, and external BIRQ interrupts.

console (halt) or power-fail microcode execution and

The various functions are described in the following

enter a “no operation’’ state. The processor remains in

paragraphs.

this condition until BDCOK H returns to the active
state.

Power-Fail/Restart Sequence— A power-fail sequence

is initiated when BPOK H goes low, clocking the
Power-Fail flip-flop to the set state. PFAIL (1) L is

The power-up restart condition occurs when DC LO L

ORed with HALT L to produce a high signal. This

goes false; RESET L goes passive (high) on the next

signal is latched during PH3 H, producing an active

PH2

IPIRQ H (interrupt 1) input to the processor control

executing a fast DIN cycle to determine the start-up

clock

pulse.

The

processor

responds

chip. The processortheninterrupts program execution.

microcode option jumper configuration. Once the fast

Note that the low (passive) BPOK H signal is inverted

DIN cycle has been completed, the processor executes

to produce an active PFAIL H input to the fast DIN

the power-up option selected, and normal operation

multiplexer; this signal status is checked by the micro-

resumes when BPOK is asserted.

code to ensure that BPOK H is asserted.
Upon entry to this microcode routine, the processor re-

Halt Mode — The Halt mode is entered either by

quests a fast DIN cycle. This request is decoded as

executingtheHALT instruction or by a device asserting

ROM CODE 35 L, presetting the fast DIN flip-flop.

the BHALT L signal. The processor halts program exe-

FDIN (0) H goes low, enabling the fast DIN multi-

cution and enters microcode execution as described for

plexer to place start-up microcode option jumper data,
the passive time-out error [TERR (1) H] signal, and the
active PFAIL H signal on WDALOQ-3 H. The processor
receives the fast DIN information via the data chip. An

a power-fail operation. However, when the processor
executes the fast DIN cycle, the PFAIL H bit (WDAL3
H) is not active and console microcode (not a power-fail
sequence) is executed. Negation of BHALT L will allow

active PFAIL H signal informs the processor that a

the processor to resume PDP-11 program execution.

power-fail condition is in progress, rather than the halt

On the next PH2 H clock pulse, IPIRQ H goes false

condition.

(Iow) and the processor Run mode is enabled.

ROM CODE 15 L —L

_[——‘

——

FDIN (1)
L

FAST

[,’:}'f_f
PH3 L —»

TIMEOUT

SYNC H

START UP MICROCODE

/SELECT JUMPERS
‘L

FDIN (O) H

ERROR F/F

TFCLRL (ROM CODE 12)

INIT (1) L

WDAL 0-3H

st
DIN

CC’QT;‘

MUX

TERR(DH

PFAILH — (3)

PH3H —| 5-STAGE

TERR L

TIME-OUT

REPLY (1) H —=»{ COUNTER

RESET L

I/0L

PH2 H —{{CLK)

+3V

PWR
FAIL

PFAIL H

BPOKH

BHALT L

|>
E

PFAIL (1)L

T HALT L

|>
PFCLR

BDCOK H

F/F

IPIRQ H

PROCESSOR
CONTROL
CHIP

DC LOL

LSI -11

BUS

——e DC

TAK (1) H r

TAK (1) L

TAK L

WIAKH

INT
ACK

BIACK H

H
DMG CY

H
Jo—niT (1

BIRQ L

F/F

IAK (D H

BHI

DIN Hj
)

(CLR)
INTERRUPT

4\:[>

10 IRQH

REQ LATCH

EVENT(OR LTC)

INTERRUPT

DISABLE
JUMPER

BEVNT L

EVNT
F/F

J’D

REFRESH

JUMPER

DISABLE

EFCLRL

REF 0SC

_j’

EVIRQ H

MEMORY

REFRESH
REQUEST

N L

LATCH

RFIRQ H

REF

J,—

600 Hz

EVENT

INTERRUPT
REfTUCEHST
PH2 H—wflCEKY
]

PROC MICROCODE

EVENT (1) H

REQ

RFOSC H

F/F

RESET L

(ROM CODE 13)

Figure4-7

11-3147

Interrupt Control and Reset Logic

Bus Errors — A bus error results in aborting program

(approximately). An active I/O signal inhibits the reset

execution and entry into a trap service routine via

input of the 5-stage time-out counter, enabling counter

vector location 004. A bus error occurs when a device

operation. [When not in a processor-controlled bus
I/0 cycle, I/0 L is passive (high), clearing the
counter.] The counter proceeds with counting PH3 H

fails torespondto the processor’s DBIN L or BDOUT L
signal by not returning a BRPLY L signal within 10 us

clock pulse signals. Normally BRPLY L would be

TFCLR L resets the Refresh flip-flop when the refresh

asserted, producing an active REPLY (1) H signal

operation is completed. Note that BREF is not asserted

which inhibits the counter; the count would remain

if DMGCY H or INIT (1) H is asserted.

stable until cleared by a passive I/O L signal. However,
if BRPLY L is not received within 10 us, the full count
(32,¢) is attained. This is the error condition; TERR L
goes low and TERR (1) H goes high. The next PH2 H

clock pulse clocks the reset latch to the reset (active)
state, producing an active RESET L signal. The processor responds by executing the reset microcode. After

entering the microcode, the processor executes a fast
DIN cycle and determines that a time-out (bus) error
TERR (1) H, rather than a power-fail condition, has
occurred. It then responds by executing the bus error

trap service routine. TFCLR L (ROM code 2) is
generated by the processor to clear the TERR Ilatch.

Event Line Interrupt — The event line interrupt
function can be used as a line time clock interrupt, or
as desired by the user. This interrupt differs from the
normal 1I/0 interrupt request by being the highest
priority external interrupt, and it does not input a
vector in order to enter its service routine. The interrupt is initiated by the external device by asserting
BEVNT L. This signal is inverted to produce a high

(active) signal, which clocks the Event flip-flop to the

set state. (Note that when W3 is installed, the flip-flop
remains reset and the event function is disabled.) On
the next PH2 H clock pulse, the event interrupt request

latch stores the active EVNT (1) H signal. An active

Normal I/0 Interrupts — ‘““Normal”’ 1/0 interrupts

EVIRQ H signal is then applied to the control chip. If

are those interrupt requests which are generated by ex-

processor status word priority is 0, the interrupt will be

ternal devices using bus interrupt request BIRQ L. The

serviced. Service is gained via vector 1004, which is

request is initiated by asserting BIRQ L. This signal is

dedicated to the event interrupt. Hence, a bus DIN

inverted to produce a high signal, which is stored in the

operation does not occur when obtaining the vector.

interrupt request latch on the next PH2 H pulse. The

The request is cleared by the microcode generated

stored request produces IOIRQ H, which informs the

EFCLR L signal.

processor of the request. If processor status word
priority is O, the processor responds by producing an
active WIAK H (interrupt acknowledge) and WDIN H
signals. WDIN H is buffered onto the BDIN L signal
line to signal devices to stabilize their priority arbitration. WIAK H is inverted, producing IAK L, setting

the Interrupt Acknowledge flip-flop on the trailing
edge of PH1 L one cycle after BDIN L is asserted. The
high (active) interrupt acknowledge signal is enabled
onto the BIAKO L signal line by passive (low) DMGCY
H and INIT (1) H signals. The highest priority device
requesting interrupt service responds to the processor’s
BDIN L and BIAK L signals by placing its vector on the

BDAL bus and asserting BRPLY L, inputting its vector

to the processor. Note that BSYNC L is not asserted
during this operation and that no device addressing
occurs. The device also clears its BIRQ L signal. The
processor responds to BRPLY L by terminating BDIN

4.2.2.7

Special Control Functions — Special control

functions include microcode-generated bus initialize
and memory refresh operations and five special control
signals which are internally on the processor module.
Special control function logic circuits are shown in
Figure 4-8. Microinstruction bus lines WMIB18-21 L
are buffered to produce the four SROMO-3 H signals.
The

actual

codes

for

the

special

functions

are

contained on SROMO-2 H; SROM3 H is always active
when a special function is to be decoded, enabling the 1
of 8 decoder during PH3 H. The resulting decoded
functions are described below.

ROM Code 10 — Not used.
ROM Code 11 [IFCLR and SRUN L] — This code is

produced by the processor to clear the Initialize
flip-flop and to assert the SRUN L signal for a RUN

Land BIAK L.

indicator in PDP-11/03 systems.

Refresh — Memory refresh is initiated by a 600 Hz re-

ROM Code 12 [TFCLR L] — This code is a trap

fresh oscillator. This function is enabled when jumper

function clear signal which clears the Refresh Request

W4 is not installed. The leading edge of RFOSC H

and Time-Out Error flip-flops (Paragraph 4.2.2.6).

clocks the Refresh Request flip-flop to the set state. On
the next PH2 H clock pulse, the memory refresh
request latch stores the request and applies an active

RFIRQ H signal to the processor’s control chip. The
processor responds by producing an active RF SET L
signal and executing the refresh microcode. RF SET L

sets the Refresh flip-flop, producing the BREF L
signal (Paragraph 4.2.2.7) and clearing the Refresh
Request

flip-flop,

which

terminates

the

request.

ROM Code 13 [RFSET L] — This code is used to set
the Refresh flip-flop. The active (high) flip-flop output
is gated with passive (low) INIT (1) H and DMG (1) H

signals to produce the active BREF L signal. The
flip-flop normally resets by the microcode-generated
TFCLR Lsignal after completing the refresh operation,

or whenever a power failure occurs. (DC LO L goes

active and clears the flip-flop.)

ROM

CODE 11 L

(IF CLR AND SRUN L)

s 1 L » INIT (1) L

ROM CODE = 4 | T
e

(INITIALIZE
SET)

SROMO H
H

BUFFERS | SROM2

DCLO L J

(NOT USED)

(IFCLR

#+ROM CODE

(TFCLR L)

& SRUN L)

» ROM CODE

(RFSET L)

CODE

»ROM CODE

L (INITIALIZE SET)

DECODER

H —

»ROM CODE
» ROM CODE

1:8 ROM

SROM3 H

PH3

BINIT L
>

* ROM

b—‘OD

CODE

L (FAST DIN)

» ROM CODE

(PFCLR L)

»ROM CODE

(EFCLR L)

LSI-11 BUS

WMIB
18-21L

SROM1

INIT (1) H

RFSET L

BREF L

INIT (1)H =0

L
=

REF

DMG CY H—O

F/F

TFCLR L

DCLO L —?

REFR

11-3148

Figure4-8

Special Control

Functions

ROM Code 14 [Programmed Initialize] — A pro-

The fast DIN cycle allows the processor to read (input)

grammed LSI-11 bus initialize operation can be per-

the selected start-up mode, time-out error, and power

formed by executing the RESET instruction.

fail signal status (Paragraph 4.2.2.6).

The

processor responds by generating ROM Code 14 L
(decoded). On the positive-going trailing edge of this

ROM Code 16 [PFCLR L] — This code clears the

signal, the Initialize flip-flop clocks to the reset (active)

Power Fail flip-flop (Paragraph 4.2.2.7).

state, producing the active initialize signal. Approximately 10y s later, the processor produces a TFCLR L

ROM Code 17 [EFCLR L] — This code clears the

signal, clearing the initialize signal.

Event flip-flop (or line time clock interrupt request)
During a power failure, the active DC LO L signal is

(Paragraph 4.2.2.7).

distributed to the Initialize flip-flop clear input; when

cleared, the flip-flop is in the active state and INIT (1)
H, INIT (1) L, and BINIT L initialize signals are used

4.2.2.8

toclear (or initialize) all LSI-11 system logic functions.

Bus Arbitration Logic — Bus arbitration

logic (Figure 4-9) enables the LSI-11 bus to be used by

When normal power resumes, the processor microcode

DMA

terminates the initialize cycle by generating TFCLR L,

devices

the

processor.

The

device

(or

processor) controlling the bus is called the bus master.

presetting the Initialize flip-flop; this is the passive

When no DMA requests are pending, the processor is

(noninitialize) or normal flip-flop state and all ini-

bus master and all data transfers are programmed.

tialize signals return to their passive states.

When

DMA

device

bus

master,

processor

ROM Code 15 [Fast DIN Cycle] — The processor

operation is suspended until the DMA operation is

generates this code when a fast DIN cycle is required.

finished.

4-10

SACK L

BSACK L

DMG (1) L }To EDAL L LOGIC
——————

DM8
PH4 H —

0
BOMR L——4>— DMA
PH H —]

?:“/‘g

F/F

INIT(1) H —o}

PH4 H——]

BOMGO L

DMA REQ H

REQ
F/F

DMG (1) H

SYNC L
_

DMA REQ L

BUSY H

REPLY (1) L

INIT(1)L
11- 3149

Figure4-9

Bus Arbitration Logic

On the first PH4 H clock pulse following the passive

Prior to a DMA request, the DMA Request flip-flop is
reset (Figure 4-10); the DMA REQ H signal is passive
(low), clearing the DMG Enable flip-flop. A device
initiates a DMA request by asserting BDMR L. The

state of SYNC L, the DMG flip-flop clocks to the set

state and DMG (1) H and DMG (1) L go to their active
states. DMG (1) H produces the active BDMG grant
(BDMGO L) signal. DMG (1) L enables EDAL L

request is inverted to produce a high signal, which is
clocked into the DMA Request flip-flop on the next
PH1 H clock pulse, producing active DMA REQ H and
L signals. DMA REQ L is ORed with REPLY (1) L,
producing BUSY H and causing the processor to
“wait” after completing its present bus cycle. On the
leading edge of PH4 H, the stored DMA request sets
the DMG Enable flip-flop. The processor is finished
with its present bus cycle and releases the bus when
SYNC L goes passive (high).

signal generation when the DMA operation involves

KD11-F resident memory. The DMA device responds
to the BDMG signal by negating BDMR L and
asserting BSACK L, enabling EDAL L signal generation and keeping the DMA Request flip-flop in the set
state. On the first PH4 H clock phase following the
active state of BSACK L, the DMG Enable flip-flop
clocks to the reset state and DMG EN H goes low. The
following PH4 H clock pulse clocks the DMG flip-flop

BOMR L |
PH1 —»|

PH1—|
DMA

REQ FF
PH4

DMGEN FF

PH4

DMG FF 9 ' :lPH4
BOMG L

BSACK

\ [
" 100ns
+ BUS
PROP. DLY.

SYNC L

(PROC)

———————

DMA DATA

-I TRANSACTION

WBUSY H

le——— INHIBIT PROCESSOR BUS CYCLES ——»]
11-3150

Figure4-10

DMA Grant Sequence

4-11

EDAL
DATA

CHIP

[¥

BDIN L—OD

L ——»S

MEM

DINR L

SYNCR

—t\

[4 5 4

————

READ

MEM READ DATA (MD@-15H)

AMX

H —s!

12:6 BIT

AL~ Al2
ADDRESS
—_————_——DMULTIPLEXOR

BWTBT L

—» ECAS H

———

BANK OR

BREF L—l
BANK OR

TM REF H

BYTE

SELECT

loslc

BYTE!

WT L

|BYTE® WT L

REF H

DAL@- 15H
I
5

——+®CAS L

s
<

[
" AMX H

W2 SBSQ L

4K
DYNAMIC
|MOS MEMCRY

[

DOUTR H

BANK SEL

RASL,CASL

ADDRESS
WORDY

LOGIC

|ADDR (6 BITS),

BDOUT L

L
» RAS

BUS

-o| DATA SELECTOR

{6-BIT

CONTROL

L Si-if
/0

1/0 BUS/

RAM

MULTIPLEX

BDALP-15L

AND

DAL@ -15H

ADDRESS

DR!VERS
RECEIVERS

IDIN

BSYNC

L——

WDALZ-15H

SBSI

DECODER

RESIDENT

DINR H
ECAS
INIT (1)

H —_—

H —————

GATES

—— BRPLY
—— IDIN

MEMORY
BANK SELECT
ADDR JUMPERS
11-3151

Figure4-11

KD11-F Resident Memory

to the reset state and BDMGO L goes passive (high),

row address (bits A7—A12 H) through the 12:6-bit

terminating

address multiplexer and into all memory chips. After

the

DMA

request/grant

sequence.

BSACK L remains asserted for the duration of the

150 ns, address multiplex control logic generates an

DMA operation, preventing new DMA requests from

active column address strobe (CAS) and a low AMX

being arbitrated.

signal. The multiplexer output bits (A1-A6) are then

The DMA device releases the bus by terminating

dressing portion of the memory operation.

strobed into all memory chips, completing the adBSACK L. The following PH1 H clock pulse clocks the

DMA request flip-flop to the passive state. BUSY H
then goes passive, enabling a processor-initiated bus
cycle. Once the processor-initiated cycle is entered,
SYNC L inhibits (clears) the DMG flip-flop for the
duration of the processor’s present bus cycle.

4.2.3

memory chips places an addressed bit on the memory

read data bus. This data is multiplexed via port A of
the 170 bus/memory read data selector only when in a
resident memory read (or refresh) operation; the select
input of the data selector is asserted low for this data

KD11-F Resident Memory

The 4K by 16-bit dynamic MOS read/write memory is

included on the

When in a memory read operation, each of the 16

KDI11-F processor

module only.

(KDII-J basic memory is magnetic core, which is contained on a separate MMV11-A core memory unit.)

selection. The read data is then placed on WDALO-15
H, where it can be read by the microprocessor data chip
or gated onto the BDAL bus via bus drivers for input to

a DMA device.

Resident memory can reside in either the first or
second 4K address bank. One of two jumpers can be
installed on the module to select the desired bank
(bank 0 or 1).

dressing, except BWTBT L may be asserted by the

The basic functions involving the resident memory are
shown in Figure 4-11. Resident memory comprises sixteen 4K by 1-bit memory chips,

When in a memory write operation, the addressing

portion of the operation is similar to the read cycle ad-

addressing,

and

control logic. The memory chips, which are 16-pin

devices, require an address multiplexer to address the
chips with two 6-bit bytes. The complete addressing,
write, and read operations are described below.

Addressing is initiated by a master device — either the
LSI-11 processor or a DMA device — by placing the

16-bit address on BDALO-1S L and asserting BSYNC
L, latching the address in the 16-bit address register.
Note that the resident memory address will appear on
the BDAL bus even when the processor is bus master;

the resident memory functions exactly as a memory
located elsewhere along the LSI-11 bus. Address bits
are routed via BDAL bus receivers onto the processor
module’s DALO-15 H bus to the address register input.

Stored address bits A13—A15 H are then decoded by

master device to indicate that a write operation is to

follow. After the addressing portion of the cycle has
been completed, BWTBT L either goes passive (high) if
a DATO (word) write cycle is to be performed, or
remains asserted (BWTBT L remains low) if a DATOB

(byte) write cycle is to be performed. Word1byte select
logic responds to the DATO cycle by asserting both
BYTE1WTLand BYTEO WT L for the duration of
the cycle, enabling DALO-15 H data bits into the
addressed location in all memory chips. However,

when in

a DATOB cycle, only one active signal is

produced, depending upon the state of the stored byte

pointer (address bit AO). If A0 is low (even byte), only
BYTE 0 WT L goes active, enabling only DALO-7 H

bits to be written into the addressed location in the appropriate eight memory chips. Similarly, if A1 is high

(odd byte), only BYTE 1 WT L goes active, enabling
only DALS8-1S H bits to be written into the addressed

location in the appropriate eight memory chips.

the bank select decoder. SBSO L (bank 0) and SBS1 L
(bank 1) will go active (Iow) only when their respective

Resident memory, as well as any LSI-11 bus device,

bank addresses are decoded. W1 or W2 then applies

must respond to any data transaction by generating an

the selected address to the address multiplex control

active BRPLY L signal.

logic, enabling the resident memory response. Address

function. Approximately 150 ns after CAS L goes true

Reply gates provide this

multiplex logic immediately generates an active row

(as previously described), the reply gates are enabled;

address strobe (RAS), which remains active for the

the gates will respond to either an active BDIN L or

duration of the BSYNC L signal. Address multiplex

BDOUT L signal by asserting BRPLY L. Reply gates

control (AMX) is initially high, multiplexing the stored

are inhibited during an initialize operation.

Resident memory requires a refresh operation once

switches contained on the option. The MMV11-A is

every 1.6 ms. This operation is entirely under the

control of either processor microcode or an external
DMA device, as selected by the user. Resident memory

completely LSI-11 bus-compatible and capable of
either programmed I/O data transfers with the processor or transfers with another LSI-11 DMA bus

responds to BREF L,

device.

generated by the

refresh-

controlling device, by simulating a ‘“‘bank selected”
operation.

The MMV11-A features:

(All memory banks are simultaneously

refreshed.) Refresh is then accomplished by executing

4096 by 16-bit capacity

64 successive BSYNC L/BDIN L operations while in¢

crementing BDAL1-6 L by one location on each bus
transaction. Refresh

Typical access time = 425 ns; full read/
restore cycle time = 1.15 us.

is simply a series of forced

memory read operations where only the row addresses

Nonvolatile read/write storage

are significant. Each of the 64 rows in all dynamic

—

stored

data remains valid when power is removed.

MOS memory chips in an LSI-11 system are simultaneously refreshed in this manner.

User-selected bank address — three switches

4.2.4

the option.

allow the user to select the bank address for
DC-DC Power Inverter

The dc-to-dc power inverter circuit provides on-board

+5V and +12 V power — only the normal

generation of required negative dc voltages. Input dc

backplane power is required to power the

power for the inverter circuit is obtained directly from

option.

the +12 V input. The inverter switching rate is clocked

No adjustments, no periodic maintenance.

by the clock pulse generator’s DIVB (0) H 2.8 MHz

output. Output negative dcvoltages arezener-regulated
The MMV 11-A is contained on two modules which are

to -5V and -9 V. The -9 V output is distributed to all
resident memory chips. The -5 V output is distributed

mated to comprise a single assembly as shown in Figure

to microprocessor chips (data chip, microm chips, and

4-12. The modules include memory interface and

control chip).

timing board

(module type G653 and core stack

(module type H223). The actual size of the assembly is

4.3

MMVI11-A 4K BY 16-BIT CORE MEMORY

8.5by 10by 0.9 in. The G653 module includes handles
and retractors on the top edge and fingers on the

4.3.1

General

bottom edge which plug into the LSI-11 bus. Circuits

The MMV 11-A 4K by 16-bit core memory option provides nonvolatile read/write storage of user programs
and data. Memory 4K addressing is user-selected by

contained on this module include interface, control
and timing logic, bus receivers and drivers, the 16-bit

data paths, sense amplifiers, and a +5 Vdc to -S Vde

G653
MEMORY INTERFACE
AND TIMING

H223
CORE STACK

CP-1781

Figure4-12

MMV11-A Core Memory Option

4-14

inverter. The H223 module is slightly smaller, includes
no handles or bus fingers, and plugs onto the No. 2
(solder) side of the G653 module via special connector
pins. Spacers are located between the modules to stiffen

the assembly and to maintain the 0.9 in. dimension.
Circuits contained on the H223 module include the
4096 by 16 core stack, 12-bit address register, X and Y
drives, stack charge, temperature compensation, and a
series +11 V, Vce switch which removes drive power
when BDCOK H goes low (power fail) or BINIT L is

asserted.

4.3.2

4.3.2.1

LA1—6H

are

applied

drive

circuits

and

LA7—12H are applied to X drive circuits.
XandY Drives—X and Y drive circuits control X and

Y read/write currents through all core mats. Address
decoding activates 1 out of 64 X wires and 1 out of 64 Y

wires. Because the active X and Y wires each have
one-half the current required for core saturation, only
one core out of 4096 cores in each core mat is saturated.

Direction of current is determined by a read or write
operation.

Functional Description

Core Stack — The core stack comprises sixteen 4096core mats. Each mat is associated with one memory bit

Introduction — The MMV11-A memory is a

read/write,

random

access,

coincident

position at all 4096 locations. Each core has three wires

current

passing through it: one X, one Y, and one sense/inhibit
wire. The sense/inhibit wire passes through all 4096

magnetic core type with a cycle time of 1.15us and an
access time of 425 ns. It is organized in a 3D, 3-wire

cores in one mat. Hence, the stack contains 16 sense/

planar configuration. Word length is 16 bits and the

inhibit lines.

memory consists of 4096 (4K) words.

The

sense/inhibit line ends terminate at sense
amplifier inputs. During a write operation, an inhibit

Major functions contained in the MMV 11-A are shown
in Figure 4-13. Memory data can be stored (written) or

read by executing appropriate bus cycles:

current, equal to saturation current, is applied to the

DATO

center of the sense/inhibit line when a logical 0 is to be

(16-bit word) write; DATOB (8-bit byte) write; DATI

written in the addressed core. This current splits and

(16-bit word) read; DATIO (16-bit word) read-modify-

one-half saturation current flows through all cores in
the mat and into termination diodes at the sense ampli-

write; and DATIOB (16-bit word) read-modify-(8-bit

byte) write.

fier inputs. The wire is threaded through the cores in a
manner that causes the current to flow in a direction

Each of the functions shown in Figure 4-13 is briefly

opposite to that of the Y write current; this prevents

described below:

core saturation, which would write a logical 1 in the
addressed core.

Bus Receivers and Drivers — These devices interface

directly with the LSI-11 bus and the G653 logic
circuits. BDAL bus drivers are gated on by DATA

Sense Amplifiers — Sense

amplifiers respond to
induced voltage impulses during the read cycle. They

OUT L during a read operation [DATI or the input

are strobed during a critical time of the cycle,
producing an active (high) output when a logical 1 is

portion of a DATIO(B) bus cyclel].

read, regardless of the induced polarity on the two ends

Bank Decoder — The bank decoder receives address

of the sense/inhibit wires for each bit.

bits A13-15 L and responds when the bank address is as
user-selected on the three bank address switches on the
G653 module. It responds by producing an active

Inverters — The inverters receive sense amplifier out-

puts, invert them, and direct-set previously cleared
memory data register bits when a logical 1 is sensed.

DSEL H signal which initiates memory cycle timing.
This signal is enabled only when power is normal and
bus initialize or refresh operations are not in progress.

Memory Data Register — The 16-bit memory data

Timing and Control — Timing and control circuits re-

ceive bus and internal control signals and generate apgenerates the BRPLY L signal in response to BDIN L

(DATI bus cycle) (no memory contents are to be modified), the same bits (low-active) are written into the

and BDOUT L.

same addressed location. During a write cycle [DATO,

Address Register — The address register stores the

DATOB, or the write portion of a DATIO(B) bus
cycle], bus data bits are clocked into the high and/or

propriate read/write timing and control signals. It also

12-bit word address within the 4K bank during the

low byte(s), depending upon the type of bus cycle (word

addressing portion of the bus cycle.

or high byte or low byte).

Latched bits

4-15

l—>+12v

REGULATOR | +5v*

BA1

BDCOK H

BINITL

DRIVERS

s CHARGE_l

RESET H

+11.5V —»
—

READ DATA 0-16H

ADDRESS
REGISTER

Al-12H

ouTL
BDAL

BDALS L

SET

DK2

BDALS L

BUS

BDALT L

80ALS L [B

RECEIVERS

[

DO-t5H

A13-15 H

BDALIO L

MDRO H —#
MDR1

REF H

BS2

BDALI3 L

BDALIE L

DRIVERS
&
SWITCHES

1-6

= X BANK ADDRESS

nED

AND

ORECEIVERS

X DRIVE CUR

SWITCHES
COMP

INVERTERS K SENSE DATA

SENSE

-5V —» AMPLS.

STROBE H —

> CLRO. 1L

i CHARGE
CKT l : YS CHARGE
XS CHARGE

L
> STROBEH

THRESHOLD

——————— FBUSY L

TIMING

CT(_)ARE
STACK

CHARGE H

DSEL

RESET H

00UT

BSYNC L

+11.5V —»

WRITE EARLY L , WRITE LATE L

|——— DATA OUTL

CKT

> MDRO H (LOW BYTE OR WORD CLK)

Bus
AK2

READ BITS 0 -15H

RESET L,

SWITCHES

BwteT L [B o5 —

WRITE DATAO -15 L

|y DRIVE CUR.
—

XS CHARGE

gtg? tj
AO H

BDOUT L

9
DRIVERS

READ EARLY
L.
LY L, L, READ
READ LATE

‘l

DECODER

BDALIS L

H —»

LOCKOUT L~

BUSY L

MEMORY
DATA

]
BN2

]

rCOMP
v

.
L

o-15L

I
INHIBIT

——+11.5V

SWITCH

—

1] & 4

8
0

cuz

BDAL4 L

BOALI2 L

Vec
2 OK H

[515%2

spAL2 L [B] DEZ
OF2
BDAL3

BDAL L

[B}————= CIRCUT | ! o pEseT L,
+5v

BDALY L

vee

——» LOCKOUT

bC
PROTECT
|

’
BDALO L
soaLt L

INH TIMEH

+12V

+12 DBDZ

L MDR1 H (HIGH BYTE OR WORD CLK)

RWBT H

SYNC H

COMP

—» comp

sV*

BREF L |B] A

BRPLY

EAFZ

REF H

45 [JRA2:BA2.BV1,CA2,002,0V1
oND

BRPLY L

[~V

@—»—w

[
JAULAMI,ATY,B1,BM1,BT1,CC2,001,0M1,0T!

BIAKIL [B M2

BIAKO
L

BDOMGI L ARZ
BDMGO L

BIAKI L [B}°M2
BIAKO L [ B ] CNz
BOMGI L [BJSR2

BOMGO L { B | cs2

CP-1782

Figure4-13

MMV11-A Logic Block Diagram

Inhibit Drivers — Inhibit drivers, one for each bit posi-

and passive VCC20K H signals. These signal conditions prevent memorycircuit operation and the possible

tion, produce an inhibit current during the write cycle
at INH TIME H if a logical 0 is to be written. The
current inhibits core saturation, which would produce

loss of stored data.

a stored logical.

Vee Switch — The Vec switch applies +11.5 V to X
and Y driver circuits when not in an initialize or power

Charge Circuit — The charge circuit applies the

fail condition.

correct operating voltage to X and Y drive circuits

during the read and write memory cycles to prevent
“sneak” currents through unselected stack diodes.

4.3.2.2 Core Addressing— When a memory location
isaddressed, one coreineach ofthe 16 mats are accessed

X—Y Temperature Compensation — X—Y tempera-

for a read or write operation. Figure 4-14 illustrates a

ture compensation circuits alter drive currents over the

required

operating temperature

range

portion of the X—Y drive and associated circuits for

provide

one Y wire. Six address bits (A1—A6) select 1 of 64 Y

reliable operation.
DC—DC Inverter — The dc—dc

wires. A similar circuit (not shown) involving the remaining six address bits (A7—A12) selects 1 of 64 X

wires. Hence, by placing 64 cores (in each mat) on each

inverter circuit

generates -5 V power for sense amplifiers from the +5

Y wire and passing a different X wire through each

V power.

core, one of 64 cores on the active Y wire will be

DC Protection — DC protection circuits respond to an

cores each and receive the same X wires, 64 x 64, or 1
out of 4096 addressing is accomplished in each of the

selected. Since the remaining Y wires have a similar 64

active BINIT L or passive BDCOK H signal by producing active LOCKOUT L, RESET H, RESET L,

——————————— —_—

PART CF Y DRIVE CKT.

l| READ

—i

PART OF TEMP,

| comp kT,

-I

X DRIVE

CHARGE CKT.

STACK

REA

|
"»*\'—
=
PART OF STEERING

_DODEMATRX_

o—

le— A4 l

ja— A5

la— AG

- g

L reapLaTeL

WRITE_OD_'_]:

| : @

> 1

—0

CHARGE

write earyL

SFN&?

'_pArFo?ET'&:T__H;V—_—""i

waite

TYPICAL
Y WIRE
(64 TOTAL)

WRITE LATE L

EARLY L9

i_—+_12-v_ - T T T

S =—=—=T)

A3 —»

I A2 —»

—_—— e ——

T T T IYPICAL CORES

£ARLY L —0

| Al —p

+12v

core mats. A single Y wire is driven as described below.

CP-1783

Figure4-14

MMV11-A Core Addressing

4-17

Two 1:8 (octal) decoders are used in Y wire selection,
each receiving three address bits from the address
register. Only one output from each decoder will be
active during addressing. Assuming address XX00 (the
zeros are the Y portion of the 12-bit address), the
portion of the Y drive circuit shown will be enabled.
During a read operation, READ EARLY L goes active
and turns on one of the eight read current source
transistors. A diode in its emitter circuit couples the
drive to eight Y wires, each terminating at the diode
steering matrix. The diodes provide a read current
path to all eight read sink transistors. READ LATE L
goes active 25 ns after the Y source is turned on, and
turns on one of the eight read sink transistors,
completing a read current path to ground. Hence, 1 of
64 Y wires is selected, producing a read half-current
through 64 cores in all memory mats. Similar X drive
circuits will produce an X read half-current in 64 cores
in each mat in exactly the same manner. Only one core
in each mat will receive an X and a Y read half-current,
causing the core to saturate in the O state. If the core
was previously in the 1 state, a voltage pulse will be
induced in the sense/inhibit wire as it switches to the 0

return path for the selected X and Y wires; only those
two wires will go to approximately 0 V, causing one X
and one Y diode to become forward biased, enabling
the write half-currents to flow. Resistors coupling the
charge voltage to write sink transistors limit the charge
current through the addressed write sink transistors
during the remainder of the write cycle. This circuit
performs the same function for read cycles by
grounding the buses and preventing sneak currents
through unselected stack diodes.

4.3.2.3 Read/Write Data Path — The basic read/
write data path is shown in Figure 4-13. Upon entering
a read cycle, the memory data register is cleared by
CLROL and CLR1 L. X and Y read currents produce
active sense amplifier outputs for those cores
containing stored logical 1s as they are switched to the 0
states. These signals are inverted and applied to the
direct-set inputs of the flip-flops comprising the
memory data registers, setting the appropriate bits.
During a write cycle, CLRO L (DATOB low byte address), or CLR1 L (DATOB high byte address), or both
CLRO L and CLR1 L (DATO word address) clear the
previously read data. The bus data is then received and
clocked into the register flip-flops by CLK MDROH
and/or CLK MDR1 H, as appropriate. Write data bits
are then routed to inhibit drivers which inhibit writing
1s when write bits are Os (high). Inhibit half-current
through addressed cores prevents X-Y write halfcurrents from switching cores to the 1 state.

state.

A write cycle is always preceded by a read cycle. The
write operation is similar to the read operation, except
write current flows through the addressed wire in a
direction opposite to the read current direction. The
core in each mat receiving X and Y write half-currents
will respond by saturating in the 1 state. However,
since a 0 may be desired, a third wire (sense/ inhibit)
will conduct a half-current which opposes the
magnetizing effect of the Y write currents. Thus, core
saturation is not attained and the cores where Os are
written remain saturated in the O state from the pre-

The sense/inhibit wire passes through all cores in a
core mat, as shown in Figure 4-15. The circuit shown in
the figure is repeated for each of the 16 core mats.
During the read portion of a memory cycle, a logical 1
stored in the addressed core will cause an induced
voltage to appear on the sense/inhibit wire as the core
switches from the 1 saturation state to the O saturation
state. If a 0 was previously written, no appreciable voltage is produced since the core is already saturated in
the O state. During the read operation, the

vious read cycle.

Temperature compensation is applied to driver circuits
via a source current, which is inversely proportional to
temperature; an increase in temperature decreases

sense/inhibit wire functions as a loop whose ends
terminate at the sense amplifier inputs. Any difference
in potential (either polarity) will enable a sense amplifier output. STROBE H occurs during X and Y drive
read currents at a critical time (the time of peak core
switching output when 1s are read). Thus, only the correct voltage pulse produced when a core goes from the 1
state to the O state is gated into the Memory Data Re-

available drive current.

The stack charge circuit applies a +11 V (approximately) signal to the sink ends of all X (not shown) and
Y wires during the write cycle. The level is applied
during WRITE EARLY time. Since WRITE LATE L
occurs 25 ns after WRITE EARLY L, the write sink
transistor is cut off, and the full 11 V signal charges the
stray capacitance of the X-Y lines, reducing the capacitive delay effect as the X and Y write source
transistors turn on; the 11 V signal also reverse biases
diodes not selected by addressing circuits, preventing
sneak currents. The addressed sink transistor, turned
on by the active WRITE LATE L signal, provides the

gister flip-flop.

The threshold circuit establishes the signal voltage
level at which a logical 1 is read during strobe time. A
signal voltage magnitude greater than approximately
17 mV during strobe time results in a valid 1 level.
4-18

+5V

+5v

;J
M inverTER | INH TIME H

| FOR EACH 4 BITS|
LTINH L

THRESHOLD
VOLTAGE

34-SOURCE

POINT

INHIBIT

ORIVER

r
_I_

THRESHOLD. CKT_]

[

2 1

THRETSOHOLD

CKTS.

(10F

4) |

) 5. —

PART OF

(SENSE AmPL IC |

1 l

3T 14

e e

REF.V

AMPL.

(10F2)

1}
I

b——— =
e

ode

TYPICAL|CORE MAT

j _Tils_o_______

é?

C4OOR9EGS

(TOTAL)

CENTER TAPPED SENSE /7 INHIBIT WIRE PASSES
THROUGH ALL 4096 CORES IN THE MAT,
AA
VVv

__i SENSE
AMPLIFIER

WRITE BIT (H=0)

BUS

WRITE DATA BIT _CNUS RECEIVER

DRIVER

DATOUT L —O

o " a

FROM BDAL BUS

MDRCLKO H
OR
—c

MDRCLK1 H)

CLRO L

(OR CLR{ L)

READ DATA BIT

TO BDAL BUS

R
MEMORY DATA REGISTER

- FLOP
FLIP

CP-1784

Figure4-15

MMV11-A Read/Write Bit Data Path

Signal levels less than the 17 mV threshold value are
considered invalid and result in O levels being read.

circuit provides a threshold voltage for four data bits.

Four threshold circuits share a common source
resistor. Each threshold circuit provides a reference
amplifier input voltage to two sense amplifier ICs, each

When in the write portion of the memory cycle, the
inhibit driver remains off if a 1 write data bit is stored in

containing two sense amplifiers; hence, one threshold

the memory data register flip-flop. However, if a O is to
be written, the write bit is high, enabling a gate input

4-19

for the inhibit driver. At INH TIME H during the write

by the RC circuit connected to

cycle, the inhibit driver produces an inhibit current

leading edge of FBUSY L, the state of FBUSY H is

FBUSY L. Thus, on the

equal to core saturation in a direction that would

clocked into the Read flip-flop, causing it to go to the

produce a logical 0. However, note that the inhibit cur-

set state. This sequence is shown in Figures 4-17 and

rent is applied to the center of the sense/inhibit wire.

4-18.

Thus, half-currents flow into each half of the sense/
inhibit wire,

preventing the

addressed core

from

The read-restore (DIN) cycle continues as shown in

saturation in the 1 state. Diodes at the sense amplifier

Figure 4-17. FREAD H activates the read time
generator, producing time signals prefixed with “RT.”
Each signal is a 225 positive-going pulse whose leading
edge is delayed with respect to FREAD H. Hence, the
leading edge of RT22S H, shown in Figure 4-16, occurs
225 ns after the leading edge of FREAD H, and approximately 275 ns after BSYNC L is asserted. Note
that RT225 His inverted and applied to the clear input
of the Read flip-flop, establishing the 225 ns pulse
width for RT pulses. RT225 H goes low, 225 ns later.

ends of the wire provide a ground return for the two
inhibit half-currents. The two resistors terminate the
ends of the wires. The inhibit driver transistor collector

is clamped to ground through a diode and resistor to
prevent

breakdown

during

turnoff.

The

emitter

resistor limits peak current.

4.3.2.4

Timing and Control— All memory bus cycles

comprise a read and a write operation. During a DATI
bus

transaction,

memory

read-restore

cycle

This time occurs 400 ns (total) after BSYNC L is
asserted and it is referenced on Figure 4-16 as (TSOOL).

executed. The data is first read and placed on the 1/0
bus. The same data is then written in the same

addressed location. During a DATO bus transaction, a

The pulse produced by the RC network on the leading

memory read-modify-write cycle is executed. After

edge of FBUSY L is inverted to produce the CLRO L

reading the contents of the addressed location, bus

and CLR1 L signals, which clear the memory data

data is clocked into the memory data register. Pre-

viously read-data is lost. The modified word is then
written

into

the

addressed

location

during

on the leading edge of FREAD H and remains active

the

for the duration of RTS0 H, producing a 300 ns pulse.

remainder of the cycle. If a DATOB bus transaction is

RT2S H goes high 25 ns later, producing the READ -

being executed, only an 8-bit portion of the memory

LATE L signal; this signal remains true for the

data register is modified, and one byte of the previously
read word is retained for the write operation.

duration of RT100, resulting in a 325 ns pulse. Read

A DATIO

data is valid at the sense amplifier inputs from 200 to
275 ns after READ EARLY L goes active. RT175 H is

bus transaction actually initiates two separate memory
cycles. The first cycle (read-restore) is initiated by the

gated with RTS0 H to produce the sense amplifier

master device by placing the memory address on

strobes STROBE O and 1 H. The trailing edge of RTS0

BDALO—1S5 L and asserting BSYNC L. After receiving

H occurs 100 ns after the leading edge of RT17S H,

and modifying the memory read data, the master

negating the strobes. During strobe time, the sense

device outputs the new data to the memory and asserts

amplifier data bits set the appropriate flip-flops that

BDOUT L, which initiates the next memory cycle

(read-modify-write).

Timing

and

control

comprise the memory data register, and store the

logic

memory read data.

functions generate all of the timing and control signals
for

the

memory

cycles

described

above.

Logic

operation for each type of bus transaction is described

The bus master device initiates the data transfer

in detail in the following paragraphs.

portion of the DATI transaction by asserting BDIN L.
The Replay Enable flip-flop is set on the trailing edge

A memory cycle is initiated when the correct bank

of RT100 H 375 ns after BSYNC L. If RDIN H (BDIN

address asserted by the bus master device is decoded on

Linverted) is received earlier than 375 ns after BSYNC

the leading edge of BSYNC L. DSEL H is the decoded

L, the Reply flip-flop input gates wait 375 ns to

bank address signal; note that it is inhibited during

produce an active RPLY SET L signal (Figure 4-17),

refresh bus cycles (when BREF L is asserted), or when

which direct-sets the Reply flip-flop and produces the

an initialize or power fail condition exists. The logical

active

state of DSEL H is clocked in the Busy flip-flop on the

gated with RDIN L and inverted, producing the DATA

leading edge of SYNC H (Figure 4-16). When DSEL H

OUT L signal which gates memory data register bits

is active (high), the Busy flip-flop sets and FBUSY H

onto the BDAL bus. If RDIN H is received later than

and

FBUSY L enables

375 ns after BSYNC L, the Reply flip-flop sets on the

one input of the read initiate gate. The remaining gate

leading edge of RDIN H. The trailing edge of RT150 H

input is enabled by the negative-going pulse produced

(T425L) is gated with RPLY SET L, producing a write

FBUSY L go to their true states.

4-20

FRPLY H and BRPLY L signals. FRPLY L is

> RT25

—————» RT50 H
RT75 H

DSEL H —

FBUSY H

FREAD H

BUSY

SYNC

F/F

|reap TiMe[

~ RUTSH

GENERATOR

READ

RT225

(T500 L

F/F

+ FBUSY L

READ

o<}

RDOUT H —

RESET H

RTSO H :Do——» READ EARLY L
RT100 H

RT25 H

+5V

BUSY

sync L EER

FRPLY L -

Y0——— READ LATE L

CLR H

CLRO L

3
RWBT H —

SYNC H

CLR1 L
RT200 H

%Tf?
F/F | rwBT L

EARLY L

RDIN H—
I_

RTI50 H
ROOUT H
WCLR

RPLY SET
L o (WRI
TE ENAB
LE)

FRPLY

FBUSY L—

L
RDIN

STROBE 1 H

RT150 H

REPLY ENABLE
F/F

RT100 H

STROBE O H

LATE L
RT175 H

RPLY

———>0—»BRPLY L

CLR

F/F

RDOUT H:D_DO_D—

»FRPLY L

TINH H

RESET L mmm ouT L
RDIN H

| WRITE TIME{

FBUSY H —

GENERATOR

{>o——> WCLR L

TINH H

RPLY SET L

WTOO H

RT150 H

RAO H —

TIME L

FAO H
BYTE
SEL
F/F

WT225 H

WRITE

RDOUT H

SYNC H—,

WT250

RDIN L

—» CLK MDR

FAQ L T

TINH L

WEARLY L

STK CHG H

1 H

—» CLK MDR O H

RWBT H—o[>——
WRITE

WORD H
cCP-1785

Figure4-16

MMV11-A Timing and Control Circuits

4-21

N 3EC

BDAL

T500

INPUT

ADDR

T1000

DATA

BDAL

(MIN}

I ADDR n

75nsec.

BSYNC L

l
FBUSY H

FBUSY H

FREAD H

READ EARLY L

l
le—— RT50H GOES LOW

READ EARLY

1000

—-4 F— 25 nsec (MIN)

25nsec.

—

FREAD H

500

-1 ’4—-25nsec.
READ LATE L

READ LATE L

|
CLRO L
CLRI L

CLRO L

CLRt

_I
j@——— RT175 H GOES HIGH

[+ RTSO H 6OES LOW

STROBEO M

| |

STROBEQ H
STROBE! H

MEMORY DATA REGISTERWRITE

MEMORY DATA REGISTER-

READ DATA VALID

8DIN L

///

DATA VALID

|
[
F—!SOnsec(MlN)

BDOUT L

—l

—p

BRPLY L
BRPLY L

DATA OUT L

I
l

|
CLKMDR1

CLKMDRO H

FWRITE H
FWRITE H

CLKMDR1 H

TINH H

CLKMDRO H

TINH H

WEARLY L

WLATE L

STKCHG H

WEARLY L

WLATE L

I
I

WCLR L
l¢-———

WCLR L

]

STKCHG H

I —

READ

—te——

WRITE

—

MODIFY —|

|-—~ READ A"L—— RESTORE —-!

cP-1787

—

Figure4-18 Read-Modify-Write Memory Cycle
Timing

Figure4-17 Read-Restore Memory Cycle Timing

4.22

initiate pulse which clocks the high FBUSY H signal

high, and the two byte select OR gates apply low signals

into the Write flip-flop, initiating the restore portion of

tothe remaining CLK MDR gates. CLK MDR 0 and 1

the memory cycle.

H then clock the BDAL bus data into the memory data

Restore timing is produced by the write time generator

portion of the cycle continues as described for the

in a manner similar to that described for read time

restore portion of the DATI operation.

generation. At WT00 H time, TINH H and TINH L

(475 ns pulses) are produced for the inhibit drivers.

When executing a DATOB bus transaction, BWTBT L

TINH H also inhibits the Reply Clear gate, and the

and RWBT H remain active for the duration of the bus

Reply flip-flop remains set for the remainder of the

cycle. Hence, the WRITE WORD H

memory cycle. WEARLY L and STK CHG H go active

passive. The Byte Select flip-flop that stores byte

on the leading edge of WT175 H and remain active for

address bit RAO H during addressing time enables

350 ns. Similarly, WLATE L goes active on the leading

generation of only one CLK MDR H signal. When RAQ

signal remains

edge of WT175 H and remains active for 325 ns. At

H is low, FAO L goes high and CLK MDR 0 H clocks

WT2350 H time, WCLR L is produced, clearing the

low byte data bits from only BDALO—7 L into the

Reply Enable and Write flip-flops; thus, write time

memory data register. Register bits 8—15 remain un-

generator outputs are 250 ns pulses. Memory data is

changed. Similarly, when RAO H is high, FAO H goes

restored (written) during the time that TINH H,

high and CLK MDR 1 H clocks high byte data bits

WEARLY L, and WLATE L are active. The memory

from

cycle terminates when both SYNC
L and FRPLY L go

to their passive states. The Busy Clear gate detects this

The write portion of the memory cycle then continues

condition, producing a low pulse which clears the Busy

as previously described.

only

BDAL8—1S

into the

memory

data

flip-flop, and the memory cycle ends.

When executing a DATIO bus cycle, two complete
The DATO cycle is similar to the DATI cycle except

memory cycles are executed. They include a DATI and

that during the addressing portion of the bus cycle, the

a DATO or DATOB cycle as previously described.

bus master device asserts BWTBT L. RWBT H goes

However, when executing a DATIO bus transaction,

high, and the leading edge of SYNC H clocks the byte

BSYNC L remains active for the duration of the trans-

flip-flop to the set state. The active FWBT L signal is

action. Hence, SYNC H, which generates FBUSY L

only used when in the write portion of the DATIO

during the read-restore portion of the cycle, cannot

cycle, as described later. However, duringa DATO bus

initiate the second read-modify-write memory cycle.

transaction, RDIN H is not received; instead, RDOUT

Instead,

H is received, enabling the REPLY SET L gates, as

portion of the cycle, enables a read initiate pulse on the

FWBT

stored

during the

addressing

shown in Figure 4-18. RDOUT enables one input to the

leading edge of RDOUT H. The Read flip-flop goes to

WRITE TIME L gate. At the same time that the Write

the set state and operation continues as described for

flip-flop clocks to the set state, WRITE TIME L goes

DATO or DATOB bus transactions.

low, enabling CLK MDRO and 1 H gates. Since a
DATO bus cycle is in progress, BWTBT L remains

4.3.2.5

passive during the data transfer portion of the bus

tion and Vcc switch circuits are shown in Figure 4-19.

cycle. Hence, RWBT H is low, WRITE WORD H

The dc protection circuit is activated during power-fail

+12v

+5V*

SOURCE

5v*

DC Protection and Vce Switch — DC protec-

+12V

DELAY CKT

Vec2 0K H

Vce

SWITCH

+11.5vV TO

X-Y DRIVERS

BDCOK H

PWR FAILH

RESET

LOCKOUT L I
RESET H

BINIT
L

cP-1788

Figure4-19

DC Protection and Vee Switch Circuits

V is removed, all MMV11 memory operations are
disabled. However, if +5 V is removed and the +12V

or bus initialize conditions. BDCOK H and BINIT L
are inverted and ORed to produce LOCKOUT L.

remains, the 5 V* allows memory protect logic to
remain functional.

Normally, this signal is passive (high), enabling bank
addressing and resulting in an active DSEL H signal
‘when the memory is addressed. However, if BDCOK H

RESET L is also applied to the VCC20K H input to the
Vee switch circuit. This signal is high only when both

goes low (power fail) or BINIT L is asserted low,
LOCKOUT

immediately

inhibits

the

bank

+S5V and +12V power sources are normal. The Vcc
switch comprises a transistor (Vcc switch), which is

addressing function.
The reset signals are also generated by this circuit.

turned on when power is normal to produce +11.5V

RESET L goes active (low) whenever LOCKOUT L is

power for X-Y driver circuits.

active. A 2 us delay circuit enables the memory to
complete its present cycle before RESET. RESET L is

also inverted to produce RESET H; both signals are
used

clear

(initialize)

memory

timing

4.3.2.6

control

DC-DC

Inverter —

The

dc-dc

inverter

circuit is shown in Figure 4-20. It is comprised of an in-

circuits.

verter oscillator using a

saturable transformer,

To produce a SV* source for reset circuits and bus

negative rectifier, and a filter. A 3-terminal regulator

receivers BSYNCL, BDIN L, BDOUT L, BWTBT L,

chip produces the regulated -5 V for sense amplifier

and BREF L, +12V power is regulated. Thus, if +12

operation.

Miverrer ~

7~ 77 T

eirmer 1

Meimer — 7

I
I
I

|
I

L_L_
1

I
L

+5v‘§ g_u_l

| 3-TERMINAL |-5V TO

—

REGULATOR

SENSE AMPLIFIERS

| 1
|
L -

cP-1789

Figure4-20
4.4

DC-DC Inverter Circuit

MRV11-A4KBY 16-BIT READ-ONLY

module that can be shared by read/write

MEMORY

4.4.1

memory modules (MSV11-A).

Jumpers that allow the user to select the 4K

General

memory address space which the MRV11-A

The MRV11-A is a basic read-only memory module on

will respond, chip type, and upper or lower

which the user can install programmable read-only
memory (PROM) or masked read-only memory

2K segment (when 256 by 4-bit chips are
used).

(ROM) chips. All PROM/ROM chip sockets and addressing and control circuits are contained on a single

4.4.2

Functional Description

8.5 by Sinch module.
4.4.2.1
General— Major functions contained on the
MRV11-A module are shown in Figure 4-21. ROM
data stored on the module can be addressed and read

The MRV11-A features:

4096 by 16-bit capacity using 512 by 4-bit

by the LSI-11 processor or other DMA devices by executing a DATI bus cycle. Data/address lines BDALO-

chips or 2048 by 16-bit capacity using 256 by
4-bit chips.

15 L and three bus interface control signals (BSYNC L,

multiple sources.

BDIN L, and BRPLY L) comprise all interface signals
required for accessing the read-only memory. BREF L

Unpopulated addressable 1K portions of the

memory refresh operations.

Compatibility

with

chips

available

from

inhibits BRPLY L and BDAL bus drivers during

4-24

CHIP TYPE

soaL 15 L[B2Y2
4

DAL15 H

9
BoAL 14 L B2

DALt4 H

soaL 13 L[B}Fo2—
4

DAL13 H
i

BDAL 12 |_

W16

ADDRESS

W15

STORAGE

SA12 L

JSA9/12

W13

CHIP
SA11H

ROW

LATCH

10 L BF2—9
8oaL

BDAL 9 L

wia

BANK
| SELECT

DECODER

BDAL 11 |_

v
H
SA12

wi7

SELECT JUMPERS

SBS H

SELECT

(OCTAL

SA10 H

DECODER)

BANK SELECT
JUMPERS

BUS

BDAL 8L

DRIVERS

BoAL 7 L 22—
[B}

RECEIVERS

DAL1-12H

AND

SYNC H J

BDAL 6 L
q
epaL 5L[EFE—

W11

SA1-8H

w10

OP SEL H :}’T—q

w12

SEL L

+3v

JSA9 H

SYNC L

soaL 4 L[B}BH2
g

SBS H

H
SA9

ADDRESS
BUFFERS

soaL 3 L[BFE2—
o

SCv

BDAL 2 L

READ

DATA @-15H

CE@-7 L

soaL 1 L[BFY2—
8oAL 0 L [BF2—0
YrepLieD L

SYNC H

BSYNC L (B] Ad2
8DIN
L

DO RPLY H

H
BA1—9

T SYNC H
BRPLY
JUMPERS

—Do—vsmc L

[B]AHZ0

MOIN L

BIAKI L AMZ

L
BIAKO

REFH
BREF E]
AR1

BRPLY L |B] AF2

someI L [B}12R2

(THRU)

REF

CE7L

LATCH
SYNC L —

BOMGO L |B] AS2
sv

RPLY

CE@L

DIN H

AA2,BA2

fl
+5v

\ READ DATA 0-3

SREF L

MOIN L

F:SYNC L

READ DATA 4-7

DO RPLY H

READ DATA 8-11
\\ READ DATA12-15

AC2,AT1,BC2, BTt

onp (210222

PHYSICAL MEMORY ROWS
11-3152

Figure4-21

MRV11-A Logic Block Diagram

Addressing — A master device can address

in Figure 4-22. Bank Select Stored (SBS H) is gated to

any 16-bit word in the 4K module by placing appro-

4.4.2.2

produce a low SEL L enable signal, which is applied to

priate address bits on BDAL1-15S L during the ad-

the D input of the decoder. (The decoder is actually a

dressing portion of the DATI cycle. BDALO is not used

decimal decoder; whenever a high signal is applied to

on the

MRV 11-A since this address bit functions only

its D input, outputs 0-7 are inhibited.) One decoder

as a byte pointer during DATOB and the write portion

output goes low, enabling the appropriate physical row

of DATIOB bus cycles. Bus receivers route DAL13-15

addressed by bits SA10-12 L.

H to the bank select decoder and DAL1-12 H to the ad-

dress storage latch. Bank selection occurs when the 4K

When 256 by 4-bit chips are used, jumpers W8, WO,

address encoded on DAL13-15 H is equal to the user-

and W10 are removed and jumpers W11, W12, and

configured value selected by jumpers W17-W15. The

either W13 or W14 are installed, as shown in Figure

resulting bank select (BS H) and address bits DAL13-

4-23. SA10 and SA11 are applied to octal decoder A

15 H are then stored in the address storage latch on the

and B inputs, respectively. Bit SA9, which is not used

leading edge of BSYNC L. Stored address bits SA1-8 H

to directly address the 256 by 4-bit chips is then applied

are buffered to produce BA1-9 H which are applied to

toinput C of the octal decoder. SA12 H and SA12 L are

all ROM/PROM chips on the module.

available for jumper selection of the desired

segment within the 4K bank. W13, when installed,

selects the lower 2K; W14 selects the upper 2K. When

When 512 by 4-bit chips are used, SA9 H is routed via

the selected segment is addressed, OP SEL goes high.

jumper W10 to a buffer, producing the inverted BA9 H

This signal is gated with SBS H to produce the low

address bit for all chips (pin 14). However, when 256 by

(active) octal decoder enable signal.

4-bit chips are used, W10 is removed and W12 is connected, forcing a low (chip enable) signal to become

4.4.2.3

applied to all chips (pin 14); note that 256 by 4-bit chips
do not receive address bit 9.

read by the bus master device. Data is available within
120 ns after BSYNC L is received. One active CE0-7 L
signal produces the active DO RPLY H signal, which

Memory chips sockets are arranged in eight physical

rows of four sockets each. The memory is expanded by

enables reply and BDAL bus driver gating. Active DO

installing all four chips in each desired row. Four chips

provide

the

full

16-bit

Data Read Operation — Once the ROM/

PROM chip sockets are addressed, the data can be

word

storage

for

RPLY Hand SYNC H signals are gated, producing the

LSI-11

REPLIED L signal, which enables one of the two bus

instructions and data. Only one row is enabled by a

driver enable inputs. The remaining enable input is

chip enable (CE) signal, produced by chip row select

MDIN L. The bus master device asserts BDIN L to

logic and chip type jumpers.

request the data. DIN H is ANDed with the passive

(high) SREF L signal, producing MDIN L, and read
data is enabled onto BDALO-15 L. Active MDIN L,

When 512 by 4-bit chips are used, jumpers W8, W9,
and W10 are installed. The chip row select octal

SYNC L, and DO RPLY H signals also enable the

decoder receives stored address bits SA10, SA11, and

BRPLY L bus driver, producing the required response

SA12onits A, B, and C inputs, respectively, as shown

toBDIN L.

‘>
BUFFERS

W10 ysa9 H

BA9 H (ADDRESS BIT)

SA10H
SAT1H

SA12 H
+3v

A9/12 H

W8 OP SEL H

C¢

SEL L

D
SBS
H =y

OCTAL

DECODER

CE2
L
0————
o
CE3 L
CE4
L

CES L

CE6
L
0t
— |

b
CETL]

flmmbum—-oc

SA9H

BA1-8H

SA1-8 H

PHYSICAL

}MEMORY
ROWS

11-3159

Figure4-22

512 by4-Bit Chip-Jumper Configuration

4-26

BA1-8 H
SA1-8 H

+3vV

SA9 H ——

BUFFERS

Wiz JsA9H

BA9 H (CHIP ENABLE)

SATO H

SAT1 H

SA12 H——
SA12 L

cEOL l

Wit

w13
-0 = O

-1

C OCTAL b CE3L
CEaL |

P SEL H

5]\

DECODER P
CE5L|

SBS H —

CE7L

PHYSICAL
SMEMORY

4|(rows

EEn
D__C_E__F_L_

SEL L

b CE2 L]

SA9/12H
|

>—CE11]
o—==

71)

WI3 AND Wi4 ARE 2K

SEGMENT SELECT JUMPERS

(ONE INSTALLED)
W13
= LOWER 2K
W14
= UPPER

2K
11-3158

Figure4-23

256 by 4-Bit Chip-Jumper Configuration

When the system is in a memory refresh operation, the

User-configured

addresses

—

Three

jumpers allow user address configuration.

MRV11-A must not respond to the BSYNC/BDIN
refresh bus transactions. BREF L is asserted during

the addressing portion of the bus cycle and the refresh
latch stores REF H on the leading edge of SYNC L.

4.5.2

SREF L goes low and inhibits the MDIN L signal.

Major functions contained on the MSV11-B module

Hence, BDAL and BRPLY L bus drivers are not

are shown in Figure 4-24. Memory data can be stored

enabled.

4.5

(written) or read by the LSI-11 microcomputer, or
other bus master devices operating in the DMA mode,

MSV11-B4KBY 16-BIT SEMICONDUCTOR

with appropriate bus cycles: DATO (16-bit word write

READ/WRITE MEMORY
4.5.1

Functional Description

operation);

DATOB

(8-bit

byte

write

operation);

DATI (16-bit read operation); or DATIOB

General

[16-bit

read-modify-write (8 or 16-bit) operation].

The MSV11-B is a 4K by 16-bit dynamic MOS read/
write memory module which can be used for temporary

storage of user programs and data. The storage
capacity is 4096, 16-bit words. Memory address selection is user-configured by installing or removing
jumpers contained on the module. Memory refresh is
directly controlled by LSI-11 bus signals. Refresh
operations can be automatically controlled by the
LSI-11 microcomputer module once every 1.6 ms
(approximately) or performed by another device. The
MSV11-B is LSI-11 bus-compatible and capable of
either programmed I1/0O data transfers with the
processor or DMA transfers with other LSI-11 bus

Addressing is initiated by a master device (either the
LSI-11 processor or a DMA device) by placing the
16-bit address on BDALO-15 L and asserting BSYNC

L, latching the address (and bank select information)
in the address register. Address bits are routed from
the BDAL bus receivers onto the module’s DALO-15 H
bus to the 13-bit address and bank select register input.
Address bits BDAL13-15S L are decoded by the bank

address decoder. Decoder output signal BS H will go
active (high) only when the jumper-selected bank
address is decoded. The active BS H signal is stored

devices.

along with the 13-bit memory address for the duration
of the operation.

The MSV11-B features:

4096 by 16-bit word.

Fastaccess time — 550 ns maximum.

The memory array comprises sixteen 16-pin 4K by
1-bit memory chips which require the address multiplexer to address the array with two 6-bit bytes.

Low power — 12.7 W for the module, worst

Address multiplexer control logic responds to the

case.

active SYNC H and stored active bank select (LBS L)

Dynamic MOS memory chips — Refresh is
automatically controlled by processor or by

signal by immediately generating an

active Row

a DMA device.

the duration of the active SYNC H signal. Address

Address Strobe (RAS). This signal remains active for

4.27

Au2

BDALQ LI B8 =
BDALYI

Av2

L | B

BDAL2 \_I B }BEZ

BDAL3L|B|lB 2

BDAL4L|BIB 2

BDAL5L|B }BJZ

DP-15H

N
KX

BDAL7 L| B } BL2

b—«—

BDALMLI B } Buz

BDALISLI 8 } 8va

BIAKO LB]

AN2

REF

<—DRIVE
L

BDAL!BLI B } 812

BIAKI L |8 ]

AND

—A

BS2

AM2

DAL® -15H

RECEIVERS

BDAL1OL| 8 } BP2
BDAL 12 L| B ,l

DRIVERS

]

BoALSL[B }BNZ

BDALM L|B

ARRAY

BUS

soaLs L[B |rBM2

BR2

DYNAMIC

BDAL 6 L| B } BK2

o |

<«
[=]

BANK

rse [T vo

+12V D—> + 12V

ADDRESS

BSH

DECODER

BANK

SELECT
JUMPERS

ssyne L[B JA%2 ’

<>
N

SYNC L

|:>°

AD.DRESS
o

W4 REF REPLY

BANK

LDAL7-12H

;Sbgégg

4:}

MULTIPLEXER

A" SH

LBSL

H
SYNC

[:>c

[_. REF H

REF L

MULTIPLEXER
PCAS H

BRPLY L AF2

AND BANK

DISABLE

somco L[B 432

S REF
L

somc1 L [B JARE

BREF

LDALI-6

13-BIT

RPLYN H

AMX L

ADDRESS

CONTROL

CAs

Loeic

CAS
L

REPLY
LOGIC

BDIN L AH2

H
DIN

——————
= DRIVE

SAO H

LBS H

BWTBTL

WORD /

WTBT H
DOUT

soout L[ BJAE2,

BDCOK H.——’O—————
BAY > DCOK L
-9V,-5V
.

DOUT

-9V

-5V

TO ADDRESS

SELECT
LOGIC

wa L

wit

[MEMORY CHIPS

INVERTER

MULTIPLEX CONTROL LOGIC

GND

DACZ.ATI. AJ1, AMt, BC2,BT1,BJ1,BM!

1-3454

Figure4-24

MSV11-B Logic Block Diagram

4-28

multiplex control AMX L is initially passive (high),

simply a series of forced memory read operations where

multiplexing the stored row address bits (LDAL7-12

only the row addresses are significant. Each of the 64

H) through the 12:6-bit address multiplexer and into

rows in all dynamic MOS memory chips in an LSI-11

all memory chips. After approximately 150 ns, address

system are simultaneously refreshed in this manner.

multiplex control logic generates an active column

The REF H signal inhibits all BDAL bus drivers for the

address strobe (CAS) and an active AMX L signal.

duration of the refresh operation.

Multiplexer column address bits (LDAL1-6 H) are

then strobed into all memory chips. This completes the

A dc-to-dc inverter circuit is included on the module

chip addressing portion of the memory operation.

for

negative voltage generation. Qutput voltages
include -9 V for the MOS memory chips and -5 V for

When in a memory read operation, the bus master

linear devices in the address multiplex control logic.

device asserts BDIN L. The data from the accessed

Hence, only +12 V and

memory location is present on the D0-15 H bus and at

+5 V power inputs are

required for module operation. The BDCOK H signal

bus driver inputs. Reply logic responds to BDIN L by

starts dc-to-dc inverter oscillation when bus power is

generating an active DRIVE L signal which gates the

applied.

memory read data onto BDALO-15 L for input to the

requesting device; reply logic also asserts BRPLY L to

4.6

complete the data transfer portion of the cycle.

When in a memory write operation (or the write portion

4.6.1

of a DATIOB cycle) the addressing portion of the

memory module which can be used for temporary

the addressing portion of the cycle has been completed,

storage of user programs

the master device asserts BDOUT L, and BWTBT L

transfers with the processor or DMA transfers with

L and W1 L for the duration of the cycle, enabling

another LSI-11 bus device.

DAIO-1S H bits to be written into the addressed

location in all memory chips. However, in a DATOB

The MSV11-A features:

cycle with AO H low (even byte), only WO L goes active,

enabling the writing of DALO-7 H into the addressed

chips.

Similarly, if AO H is high (odd byte), only W1 L goes
active, enabling only DALS-15 H bits to be written into
addressed

location

the

appropriate

The

MSV11-A is capable of either programmed 1/0 data

logic responds to the DATO cycle by asserting both WO

the

The storage

removing jumpers contained on the module.

(byte) write cycle is to be performed. Word/byte select

memory

data.

ment selection can be user-configured by installing or

is to be performed, or remains asserted if a DATOB

appropriate eight

and

capacity is 1024 16-bit words. Memory 1K address seg-

either goes passive (high) if a DATO (word) write cycle

in the

General

The MSV11-Aisa 1K by 16-bit static MOS read/write

operation is similar to the read cycle addressing. After

location

MSV11-A1KBY 16-BIT SEMICONDUCTOR

READ/WRITE MEMORY

Fastaccesstime

Low power

Static MOS memory chips — Refresh not

eight

required.

memory chips. The reply logic also responds to the

User-programmed bank and segment ad-

indicating that the data has been written, completing

dress — Five jumpers are provided for this

the data transfer.

purpose: three are for 4K address selection

active BDOUT L signal

by asserting BRPLY

and two are for a 1K segment within the 4K

address space.

The memory chips in the MSV11-B require a refresh
operation once every 1.6 ms. This operation is entirely

Use of unpopulated 1K segment addresses of

under the control of either processor microcode or a

MRV11-A — Unpopulated 1K PROM seg--

DMA device, as selected by the user. The address

ments on the MRV11-A read-only memory

multiplex control logic responds to BREF L, generated
by the refresh-controlling device,

module

by simulating a

can

addressed

read/write

memory using the MSV11-A. Hence PROM

“bank selected’’ operation. (All system memory banks

and read/write memory can reside in the

are simultaneously selected during refresh.) Refresh is

same 4K address space.

then accomplished by a device by executing 64 successive BSYNC L/BDIN L operations while incrementing

Pin and signal compatible with LSI-11 bus-

BDALI1-6 by one on each bus transaction. Refresh is

configured backplanes.

4.29

4.6.2

Functional Description

formed, or asserted (low) if a DATOB (byte) write cycle

Major functions contained on the MSV11-A are shown

is to be performed. Word/byte select logic responds to

in Figure 4-25. Memory data can be stored (written) or

the 16-bit DATO cycle by asserting both WO L. and W1

read by the LSI-11 microcomputer, or other bus master

L for the duration of the cycle, enabling DALO-15 H

device operating in the DMA mode by executing

bits to be written into the addressed location in all

appropriate buscycles: DATO (16-bit write operation);

memory chips. However, in an 8-bit DATOB cycle with

DATOB (8-bit byte write operation); DATI (16-bit

BAOH passive (low = even byte), only WO L is asserted,

read operation); or DATIO(B) [16-bit read-modify-

enabling DALO-7 H to be written into the addressed

write (8 or 16-bit) operation].

location

the

appropriate

eight

memory

chips.

Similarly, in a DATOB cycle with BAO L active (low =
Addressing is initiated by a master device (either the
LSI-11 processor or a DMA device) by placing the 16bit address on BDALO-15 L and asserting BSYNC L,

latching the address (and bank select) in the address
register. Bus address bits DALO-15 L are received and

distributed to the address register via DAL0-10 H and

odd byte), only W1 L is asserted, enabling DAL8-15 H
to be written into the

addressed

appropriate eight memory chips.

location
The

the

reply logic

responds to the active DOUT H signal by asserting
BRPLY L, indicating that the data has been written

and completing the data transfer.

to the bank/segment address decoder via DAL11-15
H. When the five high-order address bits are equal to

the jumper-selected bank and segment address, the

4.7

DLVI11SERIALLINE UNIT

decoder asserts SEL H. SEL H is stored (SSEL H) in
the address register, along with the 11-bit address, for

4.7.1

the duration of the operation.

The DLV11 is the basic interface module used for con-

General

necting asynchronous serial line devices to the LSI-11

The memory array can only be accessed when SSEL H
and SYNC L are active. SSEL H and SYNC H are

bus. All circuits are contained on a single 8.5 by S inch
module.

ANDed to produce SYNC SEL L, which enables the
memory array via the chip enable (CE) inputs on each
memory chip.

When enabled in this manner,

the

memory chips respond to stored address bits DALO-15
H for the duration of the BSYNC L signal.

The DLV11 features:

Either an optically isolated 20 mA current
loop or an EIA interface selected by using the

appropriate interface cable option.

When in a memory read operation, the bus master
device asserts BDIN L after completing the addressing
portion of the bus cycle. The addressed 16-bit memory

read data is then placed on D0-15 H and applied to the
bus driver inputs. The DIN L signal, which enables the

bus drivers previously conditioned by an active SYNCL
signal, enables memory read data onto the BDALO-15

Selectable crystal-controlled baud rates: 50,
75, 110, 134.5, 150, 200, 300, 600,

1200,
1800, 2400, 4800, 9600, and an externally

supplied rate.

Jumper-selectable

stop

bit

and

data

bit

formats.

bus. Reply logic responds to the active DIN H signal by

LSI-11 bus interface and control logic for in-

asserting BRPLY L.

terrupt processing and vector generation.

This informs the bus master

device that memory read data is available on the BDAL

Interrupt priority determined by electrical

bus.

position along the LSI-11 bus.
Control/status

When in a memory write operation (or the write portion

(CSR)

and

data

registers compatible with PDP-11 software

of a DATIO(B) cycle), the addressing portion of the

routines.

bus cycle is similar to read cycle addressing. After the

CSRs and data buffer registers

directly accessed via processor instructions.

addressing portion of the cycle has been completed, the
master device asserts BDOUT L, and BWTBT L is

Plug, signal, and program compatible with

negated if a DATO (word) write cycle is to be per-

PDP-11DL11A, B, Cseries.

4-30

BDALO L | Bl

Av2

BDAL 1 L|B}

Av2

BDAL2 L | B}

BE2

BDALsLls} BF2

BDAL4 L IB}

BH2

-0

BDALS5 L |B}
D

BJ2
BK2

BDAL7 L |B=

BL2

O RECEIVERS

BDALS L |B|[

BM2

BDALY L IB}

BN2

—o

BDALIO L |B}

BP2

BDAL1IL|B}

BDAL12
L

BDAL13 L

BS2

BDALI4L | B

apaLIS L [ B

]—2Y2

AHZ

T
SYNC L

DIN H
OO

BANK

JUMPERS

Qe O——

BANK/

———o—o0—{

1K SEGMENT [ }—
—oW%,|
SELECT

ADDRESS

ADDRESS
AND

DECODER

BANK/ SEG
SELECT

BAO H,L

Lfi

DAVl.BVi

GND

DBCZ.ACZ,BTI,AH

BSYNC L IB }A"z

SELH

SSEL
H

———T-4 SYNC L

SYNG

fi’{>

AM2

| [———0—0—]

+58

BIAKI

v
& cel

DIN L

JUMPERS

MOS MEMORY

G4K

1K X16 -BIT
STATIC

BUS
AND

|—E12

BDIN L

D@ -15 H

>
DINH

SYNC SEL

SYNC SEL L

siao L [B]ANE
o

BreLYL [B]AF2

SYNC SEL H<}F_‘

DOUT H
AR2
BDMGI L —

BDMGO L ’fi—
BDCOK H BR'

BDOUT L | Bll

—
+5Y —» |\NVERTER[TM —5V

BA@ H

BAQ L

DCOK H

O[/\

AE2

BWTBT L l B }AKZ

DOUT L

DOUT

WORD /
BYTE
SELECT

LOGIC

)
Wg L
WilL

WTBT H

1-3155

Figure4-25

MSV11-A Logic Block Diagram

4-31

4.7.2

from either the receiver (RCSR) or transmitter (XCSR)

Functional Description

control/status registers is performed.

4.7.2.1

General— Major functions contained on the

DLV11 module are shown on Figure 4-26. Communi-

4.7.2.5

cations between the LSI-11 microcomputer and the

responds to the address present on the bus when

Address Decoding— Address decoding logic

DLV11 are executed via programmed 1/0 operations

BSYNC L is asserted. The DLV11 device address is

or interrupt-driven routines, as described in Chapter 3.

contained on RDAB3-12 H, along with address bits

4.7.2.2

RDABO, 1, and 2 H, which are decoded by function
decoding logic. Address bits are not required for bank

UAR/T Operation — The main function on

ceiver/ Transmitter (UAR/T) chip. This is a 40-pin LSI

selection since all devices, such as any DLV11, reside in
the upper 4K bank (addresses ranging from 28-32K).

chip that is capable of parallel I/O with the computer

The processor generates an active BBS7L signal, indi-

the DLV11 module is the Universal Asynchronous Re-

bus and asynchronous serial I/O with an external

cating an I/0 device addressing operation. Address

device.

selection jumpers A3-A12 allow the user to configure

Jumpers which allow the user to select parity

functions, number of stop bits, and number of data

address bits 3-12, as described in Paragraph 6.2.2.

bits are described in Paragraph 6.2.2. Both transmit

When the DLV11 is addressed, device selection is

indicated by an active ME signal. This signal remains

operation. The transmit clock is always driven by the

active throughout the entire I/0 cycle (while BSYNC L

baud rate generator’s CLK L signal. CLK L is applied

remains active), enabling function decoding.

and receive functions are totally asynchronous

to one MSPAREB backplane pin (BK1), where it is
connected to MSPAREB pin BL1; this is the receive

4.7.2.6

function UAR/T

decoding and control logic decodes DLV11 internal

clock input (RCLK L) signal.

Function Decoding and Control — Function

gating functions based upon address selection, address
bits RDABO, 1, and 2 H, bus signals BDIN L, BDOUT

When
a user application requires split transmit and re-

ceive baud rates, the MSPARE jumper can be broken

L, and BSYNC L, and the VEC L signal generated by

from pins BK1 and BL1 and an external receive baud

the interface control logic. In addition to generating

rate signal can be applied to BL1 (the drive frequency

function select signals, this circuit inverts BSYNC L to

should be 16 times the desired baud rate).

produce SYNC H whose leading edge clocks the
address decoding logic. A truth table of function select

4.7.2.3

signals is provided in Table 4-2.

Baud Rate Generator — The baud rate

generator produces the desired UAR/T clock and a

fixed 2.4576 MHz clock for the -12 V inverter circuit. A

4.7.2.7

crystal-controlled oscillator produces the basic 2.4576

logic produces the BRPLY L signal in response to 1/0

MHz frequency for the baud rate generator. A single

operations, contains the interrupt control logic, and

baud rate generator chip divides this frequency to

receives and distributes the BINIT L initialize signal.
This function also contains the Transmit Data Inter-

produce the available baud rates. Jumpers, which are

described in Paragraph 6.2.2, select the desired baud

Interface Control Logic — Interface control

rupt Enable (TDINTEN H) flip-flop and Receiver
Data Interrupt Enable (RDINTEN H) flip-flop; both

rate for the CLK L output signal.

flip-flops can be read
4.7.2.4

or written by the LSI-11
microcomputer. RDINTEN is set or reset by BDAL6 L;

Bus Drivers and Receivers— Bus drivers and

receivers interface directly with the LSI-11 bus. Line

the flip-flop

receivers produce RDABO-12 H signals in response to

SELOOUT L. Similarly,

BDALO-12 L bus signals. When an input data or vector

BDALG L; this flip-flop is clocked on the leading edge

transfer is desired, function decoding and control logic

of SELAOUT L.

clocked

the

leading

edge

TDINTEN is set or reset by

generates an active INPUT ENABLE signal, which

enables the bus drivers. When a data input operation is

Receiver-generated interrupts occur as a result of the

selected, the UAR/T receiver data buffer contents

RDINTEN flip-flop being set (interrupts enabled) and

(RDO-7 H) are routed through the data selector
(DDABO-7H) to the BDAL bus. When responding to

status signal. When this condition occurs, the Receiver

an interrupt acknowledge signal, interface control
logic generates VEC L, which selects the vector address

Data Interrupt Request flip-flop sets and generated an
active BIRQ L signal. The LSI-11 microcomputer re-

produced by jumpers W6-W10 (Paragraph 6.2.2). In

sponds (if its PS bit 7 is not set) by asserting BDIN L;
this enables the device requesting the interrupt to place

an active receiver Data Available (DA H) UAR/T

addition, DALO, 6, 7, and 1S are driven by CSR
selection and gating circuits when a data input transfer

its vector on the BDAL bus when the interrupt request

4-32

TBMT H —»

I—’ INITH

—» TDINTE NH

+12v —-wv—o—o——L< AA SERIAL OUT+

AD'2 B8D2
——

+{2V

OPTICAL
COUPLER

>
A3-A12

SELECTION
JUMPERS

—

ADDRESS

_%__

han

%o |
(M

i 1t

ADDRESS
DECODING

'RDAB3 -12H

RDAB1, 2H

DATA

UAR/T

. |

EIA/TTL
RCVD DATA

EIA DATA IN

| {E TTL SERIAL

DATA IN

XCLK

UAR/T MODE

SELECT JUMPERS

3
TBMT H

_[CLK

| INVERTER | l
DAH

=12V

-12v

j¢——— TDINTEN H

RCLK

SELECTOR [*— VEC L

4¢——RDINTEN H

l«—— BREAK

BAUD RATE

/ SELECT JUMPERS

FRO

xz|

FRI

S©|

FR2

FR3

DD DATA READY

RQAST TO SEND

i < Z

DATA SET READY

i { T

CLEAR TO SEND

l—y—( BB CARRIER

SEL4 IN L —»

SELO IN L —»

EIA TRANS DATA

somer L [B}ARE

someo L [B}AS2

20 MA DATA OUT

K (SERIAL OUT-)

Hov—m—oslo
¢ K SERIAL IN+

EXT UART
CLKINH

+12

DA H

s
GND ['_']—-’—'Il

CSR
SELECTION
AND GATING

+5
D_2
BA2

H «—

T
w
w

20 ma DATA IN

RDO-7H

TBMT

DALO

ERROR/
HALT
ENABLE
JUMPER

le—<'s

FE H=e—

FRAMING /

FEH

DAL15S

[B] AR1

DAL7

DALE

BHALT

DDABO-7H

BDALI2 L .—52——~—>—
BDALIS L [B}2YE —e—»—]

RCVD DATA

RCLK —

BDAL
11

i i ‘ RDABO He—

BDAL10

BDAL9

—O—-0—

20MA/TTL

RDABO - 7H

a3
O

BDALS

—O0—-0—

DCOK I —

VECTOR
ADDR
JUMPERS

BDAL6
BDAL?

”~

BDALS

BDAL4

BUS DRIVERS/RECEIVERS

BoAL2 L [B}BE2
BDAL3

SEL 2 IN, SEL 6 OUT

SYNC H

SEL4 IN L <

INPUT
ENABLE

F%%FT }N?F?
}
’

rCr
e
coror

MSPARE A [B} 2w —12v
MSPARE 8 [B}B%lwcLk L
MsPARE 8 [B}Be oLk L
BDALO L [B}AY2
BDAL1 L [B}A¥2

h—O0—-0—

FUNCTION
DECODING
& CONTROL

SSPARE 8 D—Eluexr UART CLK IN H
mseaReA [B12-o—oERuEia-12v

SELO IN L «—

BSYNC L [B)}A42

oo
«ME

OPTICAL
COUPLER

RDABO H —»

|
|
TP1nTP2

FUNCTION
SELECT
SIGNALS

cL4

EC L

BDCOK H .—WDCOKL

—T< EE READER ENABLE —_

RDINTE NH

]

BIAko L [B}AN2
BIAKI L [B}AM2
BIRQ L [B}AL2

—

{ PP READER ENABLE
+

INSERT FOR
TTY ONLY

BRPLY L [BJAE2

SI —»
CLK L —»

BREAK
LOGIC

INTERFACE
CONTROL
LOGIC

BINIT L [B}2T2

READER
RUN
LOGIC

DA H —

+3v—o| >—L< C BUSY
pan

CP-1790

Figure4-26

DLV11 Logic Block Diagram
4-33

Table 4-2

DLV11 Function Decoding
Address Inputs
Al

X
L
H
L
L
L
H
H

X
L
L
H
L
H
H
H

Control Inputs

Function Select Signals (low-active)

BDINL | BDOUTL | MEL

X
L
L
L
H
H
H
L

X
X
X
X
L
L
L
H

H
L
L
L
L
L
L
L

H
L
H
H
H
H
H
H

H
H
L
H
H
H
H
H

H
H
H
L
H
H
H
H

H
H
H
H
H
L
H
H

H
H
H
H
H
H
L
H

CARRIER or CLR TO SEND or DATA SET

L, acknowledging the interrupt request. The interface
control logic receives BIAKI L and responds by
generating active VEC L and BRPLY L signals,
placing its interrupt vector on the LSI-11 bus and
clearing the BIRQ L signal. Once the service routine
for the DLV11’s receive function has been entered, the
receiver data buffer (RBUF) can be read. The stored

READY
DAH

—=

-—

BDALI1S

BDAL7

ROINTENH

—

BOAL6

Read XCSR (SEL4IN L asserted)
TBMTH

BIAK signal is cleared when the next BIAKI L signal is

received and the DLV 11 is not requesting an interrupt.

—

TDINTENH
BREAKH

Transmitter-generated interrupts occur in a manner
similar to the receiver-generated interrupts. However,

4.7.2.9

TDINTEN flip-flop being

BDAL7
-+

—

BDALS6

BDAILO

Break Logic — Break logic comprises the

Break status flip-flop. It is set or cleared by the LSI-11

set (interrupts enabled) and when the Transmitter

microcomputer by BDALO L while executing a bus out-

Buffer Empty (TBMT H) UAR/T signal is active

put cycle with the XCSR. Thus, the duration of the

(high). Once the service routine has been entered for

break

the DLV11’s transmit function, the transmitter data

signal

program

controlled.

The

Break

flip-flop is clocked on the leading edge of the SELA-

buffer (XBUF) can be loaded and a new character

OUT H signal. When set, the serial output line is con-

transmission initiated. Note that if the transmitter and

tinuously asserted (space). The status of the Break flip-

receiver functions request interrupts simultaneously,

flop can be read in XCSR bit 0.

the receiver function has priority over the transmitter.
If BIAKI Lis received and the DLV11 is not requesting

4.7.2.10

an interrupt, it passes BIAKO L for a lower priority

Reader Run Logic — The reader run logic

enables DLV11 generation of a READER RUN pulse

interrupt request.

for 20 mA current loop teletypewriter devices. It is
enabled by loading RCSR bit 0; the LSI-11 micro-

The interface control logic also generates the DLV11’s

computer asserts BDALO L and causes generation of

BRPLY L signal. It generates this signal when any

the SELOOUT H signal (load RCSR). READER RUN

function select signal is asserted or VEC L is generated.

is asserted and remains active for the duration of onehalf of a start bit. The start bit of the serial input (SI)

The system initialize signal (BINIT L) is generated by

from the low-speed reader initiates a 4-bit binary

the processor to reset all peripheral device registers.

counter. When eight CLK L pulses have been counted

Interface control logic responds by clearing all control

(equivalent to one-half of the start bit), READER

flip-flops, including the Interrupt Request, Interrupt

RUN s negated. After the complete character has been

Acknowledge, and Break flip-flops. The UAR/T’s

read by the LSI-11 microcomputer, the next character

RBUF and XBUF data registers are not cleared by

can be read in the same manner.

BINIT L; however, the initialize signal does clear the
DA H signal and set the TBMT H signal.

4.7.2.8

H
H
H
H
H
H
H
L

Read RCSR (SELOIN L asserted)

is acknowledged. The processor then asserts BIAKO

they occur as a result of the

H
H
H
H
L
H
H
H

4.7.2.11

EIA Interface Circuits — An EIA interface

CSR Selection and Gating — CSR selection

is provided by EIA drivers and receivers. EIA signal

and gating logic enables the LSI-11 microcomputer to

drivers are provided for EIA TRANS DATA, RQST

read

TO SEND, DATA TERMINAL READY (always an

receiver and transmitter control/status bits.

active high/space state), and BUSY (always an active

Functions are summarized below.

4-34

low/mark state).
driver

chip

Jumper EIA applies -12 V to the EIA

when

the

EIA-compatible devices.

DLVI11

EIA

signal

used

with

receivers

are

Four control lines to the peripheral device for

NEW

DATA READY, DATA
MITTED, RQSTA, and RQSTB.

TRANS-

provided for EIA DATA IN, CARRIER or CLEAR TO
SEND, and DATA SET READY. The optional BCO5C

Logic compatible with TTL or DTL devices.

modem cable connects the output signal of the EIA
DATA IN driver (EIA/TTLRCVD DATA) to the TTL

Program-controlled data transfer rate of 90K
words per second (maximum).

SERIAL DATA IN input tothe UAR/T.

Maximum drive capability of 25 ft of cable.

4.7.2.12
20 mA Loop Current Interface — The 20
mA loop current interface is provided by optical
isolation. An active 20 mA current loop is provided

4.8.2

4.8.2.1
General
— Major functions contained on the
DRV11 module are shown in Figure 4-27. Communi-

when jumpers CL1 through CL4 are installed. If the

jumpers are removed, 20 mA passive current loop
operation is selected.

The optional BCOSM

cations between the LSI-11 microcomputer and the

cable

DRV11 are executed via programmed 1/0 operations

assembly connects the 200 mA/TTL RCVD DATA
optical coupler signal output to the TTL SERIAL

or interrupt-driven routines, as described in Chapter 3.

DATA IN input of the UAR/T. When the DLV11 is
used with a 110 baud teletypewriter device, a 0.005uF,

The DRV11 is capable of storing one 16-bit output
word or two 8-bit output bytes in DROUTBUF. The

100 V filter capacitor should be installed between

stored data (OUTO-1S5 H) is routed to the user’s device
via an optional I/0 cable connected to J1. Any pro-

terminals TP1 and TP2.

4.7.2.13

-12V Inverter — The -12 V inverter circuit

generates -12 V for use by the UAR/T chip and EIA

driver and receiver chips. Input to the circuit is the
CLK signal (2.4576 MHz) and +12 V. The output is

grammed operation that loads either a byte or a word in

Input data (DRINBUF) is gated onto the BDAL bus
during a DATI bus cycle. All 16 bits are placed on the

DRV11PARALLEL LINE UNIT

4.8.1

bus simultaneously; however, when the processor is involved in 8-bit byte operation, it uses only the high or

General

The DRV11 is a general-purpose interface unit used

for connecting parallel line devices to the LSI-11 bus.
All circuits are contained on a single 8.5 by 5 inch
module.
The DRV11 features:
®

DROUTBUF causes a

NEW DATA READY H signal
;. to be generated, informing the user’s device of the
operation.

zener regulated to-12V,

4.8

Functional Description

low byte. When the data is taken by the processor, a
DATA TRANS H pulse is sent to the user’s device to
inform the device of the data transfer.
4.8.2.2
Addressing— When addressing a peripheral
device interface such as the DRV11, the processor
places an address on BDALO-15 L, which is received

and distributed as BRDO-15 H in the DRV11. The

16diode-clamped data input lines.

address is in the upper 4K (28-32K) address space. On

16 latched output lines.
16-bit word or 8-bit byte progtammed data
transfers.

User-assigned device address decoding.

the leading edge of BSYNC L, the address decoder
decodes the address selected by jumpers A3-A12 and

sets the Device Selected flip-flop (not shown); the
active flip-flop output is the ME signal, which enables
function selection and I/O control logic operation. At
the same time, function selection logic stores address

LSI-11 bus interface and control logic for in-

bits BRDO-2.

terrupt processing and vector generation.

Interrupt priority determined by electrical
position along the LSI-11 bus.

4.8.2.3
Function Selection — Function selection and
170 control logic monitors the ME signal and bus
signals BDIN L, BDOUT L, and BWTBT L. It re-

Control/status registers (CSR) and data
registers that are compatible with PDP-11
software routines. Plug, signal, and program

control internal data gating, NEW DATA READY H

compatible with DR11-C.

or DATA TRANS H output signals for the user’s

sponds by generating appropriate Select signals which

4-35

BDALO

(e}

BDAL1
BDAL2

AV2

BUS

BODAL

N OB L pRrivERS

INO-15 H

AND
RECEIVERS

BDAL3

BDAL4

SEL4INL

BDAL6

SEL2 OUT (W+ HB)L —

BDAL?

BDALS

LOW

BDALI12

OUTO-7 H

QUT O-15H —»

READ DATA
MULTIPLEXER
AND

BUS DRIVERS

A3—A12

[B}AS2

BDMGO

SEL
SEL

L
= ADDRESS

NEW DATA

READYH

OUT L

A INIT H—»

4-B8IT
CSR
LATCH

INIT L —T

4 ME

rrrrrerr

BRDO-2 H M
@ AK2

IEERR

BRPLY

BIAKO

SELO

ADDRESS
DECODER

BRD3-12 H

BSYNC

BIAKI

REQA H

(CSR 0,1,5,6)

BBS7

~—r

BDMGI

BIRQ

{CSR 7)

BRDO,1,5.6 H
HH
ZZ

JUMPERS
Vv3-V7

BODALIS

BDOUT

CSR1 H

{CSR15)

~ ADDRESS

BDALY4

BDIN

INTERFACE

<L VECTOR

BDAL13

BWTBT

. DEVICE

—

8-BIT

BYTE
LATCH

REQB H

OUT8—-15H

BDALO —1S L

BDAL

9¢-v

HIGH

BYTE
LATCH

SEL2 OUT (W+ LB)L —

BDAL1O

B INIT H —»

8-8IT

- 15 H
BRD8

BRDO-7 H

BDALSB

CSRO H

(DROUTBUF)

INIT L—

BDALS

DATA TRANS. H —»

OUTPUT BFFR.

FUNCTION
SELECTION
AND I/0
CONTROL

SELECT

E AE2

(e}
Ee

SEL4 INL

SEL2 (W+HB) L
SEL2 (W+LB) L
VECTOR H

E‘r AH2

AL2

NEW DATA READY H
DATA TRANS. H

SIGNALS

INTERRUPT
LOGIC

—

REQ
BH

REQAH

—» INIT H,INIT L
BINIT
GND
+5

BUS RE CEIVER

D AT2

AC2,AT1,BC2,BTt
AA2,BA2

AND INVERTERS

A INITH
B INIT H

+5V
cP-1791

Figure4-27

DRV11 Logic Block Diagram

Table 4-3
DRV11 Device Function Decoding
BWTBTL

Programmed
Operation

Stored Device
Addr. Bits 0-2

During
Data Transfer

‘
BDINL

BDOUTL

Bus Cycle
Type

.
Write DRCSR

0
0

0
1

H
H

L
L

DATO
DATOB

Read DRCSR

DATIor DATIP | SELOINL

DATO

Select Signals
SELOOUTL

Write

LEV

DROUTBUF

Word

SEL20UT (W+HB)L,

SEL20UT (W+LB) L, and
NEW DATAREADYH

Low Byte

DATOB

SEL20UT (W +LB) Land
NEW DATAREADYH

High Byte

DATOB

SEL20UT (W +HB) L and
NEW DATA READYH

Read DROUTBUF

DATIorDATIP | SEL2INL

Read DRINBUF

DATI

SEIAINL and
DATATRANSH

NOTE

When addressed, the DRV11 always responds to either BDIN L or BDOUT L by asserting BRPLY L [ L = assertion].

device, and the BRPLY L bus signal which informs the

the LSI-11 bus. Data to be read is provided by the

processor that the DRV11 has responded to the pro-

user’s device on the INO-1S H signal lines. Since the

grammed I/O operation. Since the DRV11 appears to

input buffer consists of gating logic rather than a
flip-flop register, the user’s device must hold the data

the processor as three addresseable registers (DRCSR,
DROUTBUF, and DRINBUF) that can be involved in

on the lines until the data input transaction has been

either word or byte transfers, the three low-order

completed.

address bits stored during the addressing portion of the
bus cycle are used for function selection. The select

The input data is read during a DATI sequence while

signals relative to I/O bus control signals and address

bus drivers are enabled by the SEL4IN L signal. The

DATA TRANSMITTED pulse that is sent to the user’s

bits 0-2 are listed in Table 4-3.

device by the function select logic informs the device of
NEW DATA READY H is active for the duration of

the transaction. Input data can be removed on the

BDOUT L when in

trailing edge of this pulse.

a DROUTBUF write operation.

This signal is normally active for 300 ns. However, by
adding an optional capacitor in the BRPLY L portion

4.8.2.7

of the circuit, the leading edge of BRPLY L is delayed,

DROUTBUF

effectively increasing the duration of the NEW DATA
READY H pulse to 1200 ns (maximum); adding the

enabling either 16-bit word or 8-bit byte output
transfers. Two SEL 2 signals function as clock signals

capacitor also increases the DATA TRANS H pulse

for the latches. When in

DROUTBUF

Output

comprised

Data

of two

Transfer

8-bit

—

latches,

width in exactly the same manner.

a DATO bus cycle, both
signals clock data from the internal BRDO-15 H bus

DATA TRANS

only one signal clocks data into an 8-bit latch, as

into the latches. However, when in

H is active for the duration of BDIN L

a DATOB cycle,

when in a DRINBUF read operation. This signal is

determined by address bit O previously stored during

normally active for 300 ns. The time, however, can be

the addressing portion of the bus cycle.

extended by adding the optional capacitor to the
BRPLY

portion

the

circuit

The NEW DATA READY H pulse generated by the

previously

described.

function select logic is sent to the user’s device to
inform the device of the data transaction. The data can

4.8.2.4

be input to the device on the trailing edge of this pulse.

Read Data Multiplexer — The read data

multiplexer selects the proper data and places it on the
BDAL

bus

when

DROUTBUF

the

processor

inputs

4.8.2.8

Interrupts — The DRV11 contains LSI-11

bus-compatible interrupt logic that allows the user’s

contents are gated onto the bus separately. The select

device to generate interrupt requests. Two independ-

signals

ent interrupt request signals (REQ A H and REQ B H)

described)

vectors;

DRCSR,

DRINBUF

(previously

interrupt

and

VECTOR

produced by the interrupt logic, control read data

are capable of requesting processor service via separate

selection.

interrupt vectors. In addition, DRCSR contains two
interrupt enable bits INT EN A and INT EN B) (bits 6

4.8.2.5

DRCSR Functions — The control/status

and 5, respectively), which independently enable or

disable interrupt requests. REQ A and REQ B status

Four of the six significant DRCSR bits can be involved

can be read by the processor in DRCSR bits 7 and 15,

in either write or read operations. The remaining two

respectively.

bits, 7 and 15, arc read-only bits that are controlled by

provided for each request, one of the requests could be

the external device via the REQ A H and REQ B H

used to imply that device data is ready for input and the

signals,

respectively. The four read/write bits

are

Since

separate

interrupt

vectors

are

remaining request could be used to imply that the

stored in the 4-bit CSR latch. They represent CSR0 and

deviceis ready to accept new data.

CSR1 (DRCSR bits 0 and 1, respectively), which can be

Aninterruptsequenceisgenerated when a DRCSR INT

used to simulate interrupt requests when used with an
optional maintenance cable. INT ENB A and INT

EN bit (A or B) is set and its respective REQ signal is

ENB B (bits 6 and 5, respectively) enable interrupt

‘asserted by the device. The processor responds (if its PS

logic

available to the user’s device for any user application.

bit 7 is not set) by asserting BDIN L; this enables the
device requesting the interrupt to place its vector on the

4.8.2.6

edged.

operation.

Note

that

CSRO

and

CSR1

are

BDAL bus when the interrupt request is acknowl-

DRINBUF Input Data Transfer — DRIN-

The

processor

then

asserts

BIAKO

BUF is an addressable 16-bit read-only register that

acknowledging the interrupt request.

receives data from the user’s device for transmission to

receives BIAKI L and the interrupt logic generates

4-38

The DRV11

VECTOR H, which gates the jumper-addressed vector

information through the read data multiplexer and bus
drivers and onto the LSI-11 bus. The processor then
proceeds to service the interrupt request as described in

Chapter 3.
4.8.2.9

Maintenance Mode — The maintenance

mode allows the user to check

tion, program execution can be initiated via console
ODT commands. The LTC ON/OFF switch enables or
disables H780 generation of the line time clock
(BEVNT L) signal. One spare LED indicator is in-

cluded. Two fans provide cooling air for the H780
power supply and all modules contained in the PDP-

11/03 enclosure.

DRV 11 operation by in-

stalling an optional BCO8R cable between connectors

The H780 features:

I1 and J2. This maintenance cable allows the contents

of the output buffer DROUTBUF to be read during a

DRINBUF DATI bus cycle. In addition, interrupts
can be simulated by using DRCSR bits CSRO and
CSR1. CSRl1isrouted via the cable directly to the REQ

power must not exceed 120 W.

Overcurrent/short circuit protection — Output voltages return to normal after removal

B H input and CSRO is routed to the REQ A H input.

By setting or clearing INTEN A, INT EN B, and CSR0O

of overload or short. Current limited to approximately 1.2 times the normal maximum

and CSR1 bits in the CRCSR register, a maintenance

program can test the interrupt facility.
4.8.2.10

rating.

Initialization — BINIT L is received by a

bus driver, inverted, and distributed to DRV 11 logic to
initialize the device interface. The buffered initialize

Overvoltage protection — -+5 V limited to
+6.3 V (approx); +12 V limited to +15 V

signal is available to the user’s device via the AINIT H

(approx).

and BINIT H signal lines. DRV11 logic functions

Dual primary power configuration — Can be
connected for nominal 115 V, 60 Hz or 230

cleared by the BINIT signal include DROUTBUF,
CRCSR (bits 0, 1, S, and 6), and interrupt logic.

4.9

V, S0 Hz input power.

H780 POWER SUPPLY

4.9.1

General

System control/indicator panel — A simple

all backplane slots contained in a PDP-11/03 micro-

system control/indicator panel

computer system. Depending upon the configuration

computer

or 60 Hz. In addition to providing operating power, the

the

mode.

Indicators

Line Time Clock — A bus-compatible signal is generated by the power supply for the

event (line time clock) interrupt input to the

run state, and DC ON, which illuminates when normal

Run/Halt

status.

H780’s front panel. The indicators include RUN,
which illuminates when the LSI-11 processor is in the

applied

the

display the actual dc power and processor

H780 generates power supply status and line time clock
signals which are distributed over the LSI-11 bus.
Three LED indicators and three switches are on the

are

allows

user to control dc power on/off and micro-

ordered, the primary power input is 115 or 230 Vac, 50

operating voltages

Efficiency — Switching regulator circuits
provide greater than 65 percent overall effi-

ciency.

The H780 power supply provides dc operating power to

+5V % 3%, 18
A (maximum) and +12 V
+ 3%, 3.5 A (maximum); combined dc

processor. This signal is either SO or 60 Hz,

LSI-11

depending upon primary power

backplane. The DC ON indicator status is controlled

line

fre-

quency input to the power supply.

by circuits contained in the H780. The DC ON/OFF
switch allows the operator to turn off the H780 dc out-

Power Fail/Automatic Restart — Fault detection and status circuits monitor ac and
dc voltages and generate bus-compatible

put voltages without turning off system primary power.
This allows safe module installation or removal with no

BPOK H and BDCOK H

dc power applied to the backplane. A normal power-

signals (respective-

ly) to inform the LSI-11 system modules of

up/power-down sequence is produced when this switch

power supply status.

is operated. The ENABLE/HALT switch enables the
operator to manually assert the BHALT L bus signal,
causing the LSI-11 microcomputer to execute the con-

Fans — Built-in fans provide cooling for the
power supply and LSI-11 modules contained

sole (ODT) microcode. When in the ENABLE posi-

in the PDP-11/03 enclosure.

4-39

Backplane Signals

Specifications

4.9.2

BPOKH
BDCOKH

Electric

BEVNTL

Input Voltage

BHALTL

100—127Vrms, 50 + 1Hzor60 + 1Hz
1 Hz
200—254Vrms, S50 * 1Hzor60

SRUNL

Input Power (fullload)

Mechanical
Cooling

400 W maximum

Two self-contained fans provide 200 LFPM air

Output Voltages

flow.

+5V £ 3%,0—18 A load (static and dynamic)
+12V % 3%,0—3.5Aload (static and

dynamic)

Size

)

Maximum output power: 120 W (total)

Weight

Output Protection

131bs

Current limited to 1.2 times maximum normal

Environmental

rating (approximately)

Voltage +5 V and 412 V outputs limited to
+6.3 V (nominal) and +15 V (nominal). res-

Temperature

pectively

Humidity

5°—50° C operating

90% maximum without condensation

Output Ripple

5V output: Less than 100 mV pk-to-pk
12V output: Less than 200 mV pk-to-pk

4.9.3

Functional Description

— Major functions contained in the
4.9.3.1 General
H780 power supply are shown in Figure 4-28. These
functions include circuits which produce unregulated
dc voltage and regulated dc voltage for H780 circuit
operation, +5 V and +12 V switching regulators,
overload and short-circuit protection, +5 V and +12
V crowbar (overvoltage protection) circuits, and logic
signal generation circuits. The following paragraphs
describe each of these functions in detail.

Output Regulation
+5V,1.0% max
Line:
+12V,0.5% max

Load: (Static and dynamic (41<0.1 A/us):
+5V, 1% max
+12V,0.5% max
Load Interaction: 1.0%

Load Term Stability
0.2% /1000 hr max

4.9.3.2 Unregulated Voltage and Local Power— Unregulated voltage and local power circuits provide
operating dc power for power supply logic and control
circuits, and dc power for the +5 V and +12 V
regulator circuits. These circuits are shown in Figure
4-29. AC power is supplied to the H780 via an ac input
plug and cable. A toggle switch mounted on the rear of
the H780 assembly applies ac power to the power
supply. Normally, this switch remains in the ON

Line Protection

H780A (115 V input): Fast blow S A fuse
H780B (230 V input): Fast blow 3 A fuse

Noise

5-1/2in.w x 3-1/2in.h x 14-5/8in.

AC component above 100 kHz meets DEC STD
102.7; H780B units will meet VDE N-12 limits
for European environment.

Front Panel Control and Indicators
DC ON/OFF switch
RUN/HALT switch
LTC ON/OFF switch

position, allowing ac power to be controlled by power
distribution and control circuits in which the
PDP-11/03 system is installed. Primary circuit
overload protection is provided by a fuse mounted on
the rear of the H780 unit. Primary power circuits are
factory-wired for 115 Vac (model H780A) or 230 Vac
(model H780B) operation. Power transformer primary
windings and the two fans operate directly from the

RUN indicator

DC ON indicator
Spare indicator

Rear Panel Controls and Indicators
AC ON/OFF power switch

switched ac power.

4-40

-15v

+5V

| REGULATOR [ 15V
LOCAL DC POWER

FANS
%

Ac
ry
—~

* REGULATOR [ TM *5A

ON/OFF
;

|
o/c

PRIMARY
POWER

(2)

PWR |
XFMR

RECTIFIER

AND
ACVI FILTER
CKTS

swn;gxme
ot REGULATOR

+V UNREG

>o +5V

e
OVERVOLTAGE

—

(CROWBAR)

CKT

AND

OVERLOAD
SHORT-CKT
PROTECTION |. ||

-l——.eocox y

—.BPOK H
LOGIC
SIGNAL

GENERATION BEVNTL
CKTS

BHALT L
Q—DSRUN L

+{2V

SWITCHING

L—o\o—»

» +12V

'REGULATOR

OVERVOLTAGE

(CROWBAR)
CKT

CP-1792

H780 Power Supply Block Diagram

Figure4-28

F3
5A

ON/OFF

PWR
XFMR

——Np—0 o
;
|
|
:
*PRIMARY

POWER <

(115V)

_‘_

3
_ TRANSIENT

SUPPRESSORS

l
.

FAN

!
o
\

1
=

/-l:-\

PRIMARY POWER CONNECTIONS ARE SHOWN ABOVE (H780A).
*{15V
230V PRIMARY POWER CONNECTIONS ARE SHOWN BELOW (H780B).
F3
F3

PWR

AC
ON/OFF
jO

'
|

FAN ( )

LOGIC SIGNAL

—* UNREG

OR
REGULAT
(+5V)

3-TERMINAL

—l—

+5V

3-TERM
ATOR |—# -15V
REGUL
INAL

-15V

FAN<>

ACV TO

——» ) GENERATION CKTS

230V

l_
-

]

/o—

Figure4-29

CP-1793

Unregulated Voltage and Local DC Power

4-41

A single center-tapped secondary winding supplies

operates at approximately the regulated output voltage

power

level. Basic regulator circuits are shown in Figure 4-30.

for

regulator

circuits

and

internal

circuit

operation. Conventional full-wave rectifiers and a -15

Note that the ground terminal of the

V, 3-terminal regulator IC provide regulated voltage

regulator is connected to a potentiometer, allowing

for internal distribution. The rectifiers also provide

factory adjustment of the terminal voltage over a -0.7 to

3-terminal

+24 V (approx) for internal distribution and regulator

+0.5V range. Hence, the 3-terminal regulator output

operation. A 3-terminal regulator integrated circuit

inthe +35 V regulator circuit can range from 4.3 to 5.4

provides +35 V logic and control power for H780 cir-

V (approx).

cuits. The +5V and +12 V regulators use the same

+24 V unregulated voltage for regulation and distri-

Normal switching regulator operation is accomplished

bution to LSI-11 modules. AC voltage from one side of

when the control transistor is turned on. Forward bias

the transformer secondary is also routed to the line

for the control transistor is supplied via R14. It is

time clock (LTC) circuit, which generates a BEVNT L

turned off only during fault conditions (overcurrent or

bus signal for a line time clock processor interrupt.

shorted output voltage) or when the input ac line

When used with a 60 Hz line frequency, the interrupt

voltage is below specifications. Its emitter supplies

occurs at 16.667 ms intervals; a 50 Hz line frequency

unregulated voltage to the 3-terminal regulator. At less

will produce interrupts at 20 ms intervals.

than S0 mA regulator output current (approx), the

4.9.3.3

ever, as load current through the 3-terminal regulator

3-terminal regulator supplies the output voltage. How-

Basic Regulator Circuit — Both +5 V and

-+ 12 Vregulator circuits receive the +24 V unregulated

is increased beyond this value, the voltage drop across

input power. The +5 V and +12 V regulator circuits

R27 forward biases the driver transistor. The pass

are identical except for component values. Hence, only

switch transistor then turns on and applies the unre-

the basic +5 V regulator is described in detail.

gulated

+24 V to L2. The output capacitor then

charges toward the +5 V value, current limited by the
The basic regulator is a switching regulator which

operates

approximately

kHz.

The

inductance of L2. When the output voltage rises to the

main

3-terminal regulator regulation voltage, the 3-terminal

controlling element is a 3-terminal regulator which

regulator turns off; current through R27 stops, and the

PASS

SNUBBER

SWITCH

+V UN REG.—0N\_o-

NETWORK

Y
T

DRIVER

—~

Efi

AR16

FREE

WHEELING
DIODE

T
1

CURRENT
SENSE

AAA—

TO OVERLOA
ANp-OAD

SHORT-CIRCUIT
PROTECTION

> +5W

CKT.

S
rR27

|CONTROL

L AAA— G

3-TERM.

REGULATOR

(+5V)

L
AAA——]

1IN

I
| AND

_»S

-~
»

SHORT-CKT.

::ROTECTIO N

)

PART OF
OVERLOAD

)

1oV

+5V ADJ.

(FACTORY~-ADJ.)
—0.5V

[

|
CP~1794

Figure4-30

Basic Regulator Circuit

4-42

driver transistor is not forward biased. Hence the
driver and pass switch transistors cut off. The energy

4.9.3.4

stored in L2 continues to charge the capacitor bank
slightly beyond the designed output voltage via the free-

tected. When in an overload condition, excessive power

Overload and Short-Circuit Protection —
Each H780 dc output is overload and short-circuit pro-

supply current is

sensed, causing both switching
regulators to go off and then cycle on and off at a
low-frequency rate (approximately 7.5 Hz) until the

wheeling diode and the current sense resistor. Once the
inductor’s stored energy is spent, the load discharges
the output capacitor until the output voltage drops

overload is removed. Each time the power supply cycles

below the 3-terminal regulator’s regulation voltage. At

on, the circuit checks for the overload condition. If the
load current returns to normal, the 20 kHz switching

that point, current through R27 increases and turns on
the driver and pass switch transistors, and the cycle

regulator operation resumes.

repeats. Note that as the load is increased, the pass

switch must remain on longer in order to charge the

Overcurrent sensing circuits for +5 V and +12 Vdc
outputs are identical except for component values. A 5

output capacitor to the regulated voltage value. This
process repeats at a 12—20 kHz rate, producing the

V power supply overcurrent condition results in an in-

switching regulator operation.

creased voltage drop across the current sense resistor

(Figure 4-31), forward biasing the current sense
transistor. (During normal operation, this transistor is

Switching losses in the pass switch transistor are
minimized by the snubber network. This network

not forward biased.) Current sense transistor collector

operates during the “off”’ switching transient (as the

voltage then drops from the normal +24 V (approx) to

pass switch is biased off) by controlling the rate of increasing

the +35V regulator output value; this voltage, which is

collector to emitter voltage as collector current

less than the +16 V reference applied to the current

decreases.

limit comparator’s inverting input, is diode-coupled to
the comparator’s non-inverting input, causing the

The control transistor is turned off during a fault

comparator’s output to go low; the diode coupling

condition by overload and short-circuit protection cir-

provides an OR logic function for both +5V and +12

cuits. When a fault condition is detected, the control

V overcurrent fault conditions. The comparator’s low

transistor’s base voltage drops to nearly 0 V, causing it

output signal triggers the 20 us one-shot whose OVER-

to cut off. When cut off, operating voltage is removed

CURRENT

from the 3-terminal regulator and R27 current is O,

one-shot and sets the Current Limit flip-flop. The

disabling the switching regulator circuit.

L pulse output

_j:

SENSE

CURRENT

the

135

LOW

FREQ CKT
A

+5V

_‘i—' TO LOAD

135ms
ONE SHOT

2.0ms
ONESHOT

LIMIT RESET n

+5V H

CURRENT

+5V CURRENT

> SENSE

OFF

(EOX'LF%NDEDL)

LIMIT F/F

TRANSISTOR
Q8

D20%
FROM +12V

CURRENT

SENSE
TRANSISTOR
+V

UNREG

Dég

+12V HOLDOFF L

CURRENT LIMIT

R58

OVERCURRENT L pulse is also ORed with the

[ParToFssv — — T |
SWITCHING REG

triggers

COMPARATOR | 5oo

(EXTENDED)

ONE-

16.4V (NOM.)

shot
O

.]EE,
D14
=

POWER
FROM

“i"

‘I.P Q12
=

OFF L

LOGIC SIGNAL ——

GENERATION CKTS

Figure4-31

Overload and Short-Circuit Protection

4-43

+12V HOLDOFF L

jE9>
Q12

CP-1796

Q15. An overvoltage is coupled into the circuit via C7,
causing the gate voltage of Q9 to rise; this triggers Q9
and its cathode voltage rises to the output (overvoltage)
potential. Q15 then fires and shorts (crowbars) the
supply output. The circuit remains in this condition

POWER OFF L signal, turning on the +5V and +12
V hold-off transistors. Both switching regulators are
then disabled. The high 135 ms one-shot output pulse
is ANDed with the Current Limit flip-flop output,
turning on +5 V and +12 V extended - hold-off

until the overvoltage is removed (Q15 current goes to
zero) and either the power supply switch transistor is
off due to short circuit protection, or the regulator’s d¢

transistors. Hold-off signals remain in this state and
inhibit switching regulator operation for the 135 ms
pulse duration. At the end of this time, the 135 ms
one-shot resets, terminating the delayed hold-off
signals, and triggers the 2.0 ms one-shot. Its active low
output resets the Current Limit flip-flop and clears the
135 ms one-shot for 2.0 ms, allowing the regulator pass
switch transistors to operate for 2 ms (minimum). At

fuse opens.

>+5V

ci,

+5v | G2,

the end of this time, the 135 ms one-shot is again
enabled (the clear input goes high) and a new overcurrent cycle is enabled. If the overload is removed,
normal operation resumes; otherwise, the overload
causes a new overload condition to occur and the cycle

SWITCHING J 2L

REGULATOR )
OUTPUT

Q15

]

{

RTN (GND)

repeats, as described above.

CP-1797

Switching regulator operation is suspended when the
operator places the DC ON/OFF switch in the OFF
position. Logic signal generation circuits respond by
immediately asserting BPOK H low to initiate a
processor power-fail sequence. After a 5—10 ms
“pseudo delay,” POWER OFF L is asserted low. This
low signal is wire-ORed with OVERCURRENT L, in-

Figure4-32

Crowbar Circuit

The +12 V crowbar circuit functions in a similar
manner. However, the reference voltage for this power
supply is approximately 13.5V.

4.9.3.6

hibiting the switching regulator operation, and dc
power is removed from the backplane.

Logic Signal Generation — Logic signal gen-

eration circuits produce LSI-11 bus signals for power
normal/power fail

and line time clock

interrupt

functions and processor Run-Enable/Halt mode. The

4.9.3.5 Crowbar Circuits — Crowbar circuits are
connected across both +5V and +12 V power supply
outputs for overvoltage protection. An overvoltage
condition could occur if +12 V and +35 V outputs
shorted together, or if a driver or switch transistor becomes shorted. When shorted to a higher voltage
source, the crowbar fires, shorting the supply voltage
that it is protecting to ground (dc return). In this
condition, the overload and short-circuit protection
circuits respond by limiting the duty cycle of the switch
transistor until the overvoltage source is removed.
However, when the overvoltage is caused by a shorted
driver or switch transistor, short-circuit protection is
ineffective, and the excessive current caused by the
crowbar circuit firing will blow the regulator’s fuse (F1

RUN indicator circuit monitors the SRUN L backplane (nonbused) signal and provides an active display
when the processor is in the Run mode. BPOK H and
BDCOK H indicate power status. When both are high,
power to the LSI-11 bus is normal and no power fail
condition is pending. However, if primary power goes
abnormally low (or is removed) for more than 16.5 ms,
BPOK H goes low and initiates a power-fail processor
interrupt. If the power-fail condition continues for
more than an additional 4 ms, a “‘pseudo delay”’ circuit
causes BDCOK H to go low. The circuit also causes the
overload and short-circuit protection circuit to inhibit
+5V and +12 V control transistors; normal output
voltages are available for SO us (minimum) after
BDCOK H goes low (depending on the loading of the
dc output voltages). The DC ON/OFF switch
simulates an AC ON/OFF operation by turning
switching regulators on or off without turning system

for +5VorF2for +12V).

The crowbar circuit for the +5 V output is shown in
Figure 4-32. It comprises a 5,6 V zener diode D9, diode
D8, programmable unijunction transistor Q9, and
silicon-controlled rectifier (SCR) Q15. R19, D8, and
D9 supply the 6.1 Vdc (approx) crowbar reference
(threshold) voltage to the gate of Q9 via R21. Q9 is
normally off and its cathode supplies a0 V gate input to

primary power off. A normal power-up/power-down
sequence is produced by this circuit. The line time
clock circuit produces a processor interrupt at the
power line frequency (either S0 or 60 Hz). The circuit
simply asserts the BEVNT L line at the line frequency.

4-44

DC voltage monitor circuits respond to both +5V and

R2S and R3, as shown in Figure 4-33. Voltages are

+12 V power supply outputs.

A +2.5 V reference at

sensed at the anodes of diodes D17 and D18. The

the voltage comparator’s noninverting input is es-

cathode of D17 is connected directly to the +S V

tablished by +5 A and a voltage divider comprised of

output.

D18

connected

voltage

divider

+5V

VOLTAGE

SENSE INPUTS

;

+12V

45V

+2V

+5A

L
+5A

D16,

Aivie

ile

$ros

bi8

R47

BDCOK H

VOLTAGE

R49

R503

~_COMPARATOR

2.67V

(NoRMAL)

NORMAL=5.5v

s I

}

DCOKL

|23V 1,

R39

£ D15

R33

DC FAIL <5.13V

e
=

R35

PART OF

+8A —AMm—14—DC LOH l FRONT

/7Y

| PANEL

y o025

DCON

I
|

R
S
|

037

POWER OFF L

PART OF FRONT

|I PANEL DC ON
|

—

OFF

R40 $RSZ COMPARATOR
¢ oFF voLTAGE

2.5y

PSEUDO |

L - —————— _J

LDCONH,c

+5A

PROTECTION CKTS

RS1

l_—oD

+2.5v | E®

CL['.i R8g Re8 COMPARATOR
AcLow =
S

—-'L

+5A

R38

R2 -

+5V

SRS
Y

RS4 D23

SHO

VWV

ACLOH

SR84
T

+2.5V |

R36

R46

POWER OK

DETECTOR

R24

16.5
ms
ONE-

I———WV———
n

RO
o

+5A

)

R32g

» SHORT- CIRCUIT

D26 -l-cm
I

+54

RS3 D24
o

TO OVERLOAD AND

AC LO L

03
- T,
ACV

PWR OFF/FAIL H

D10

4 re3T \—»vw——

BPOK H
Qs

R10

BEVNT L

D1i

LINE TIME CLOCK

:-PART OF FRONT PANEL
|
SRUN L

+5A |

45V

200

oNES

RUN H

RUN

:
'
I

ENABLE
=

¥\

+5A

nacr

CHALT H

Figure4-33

Logic Signal Generation

4-45

BHALT L
R26
R26

cp-1798

comprising 6.8 V zener diode D16 and R47. The sensed

active (dc voltage normal) state. Rectifiers D2 and D3

voltage is always 6.8 V less than the +12 V power

produce positive-going dc voltage pulses at twice the ac

supply output voltage

line frequency. R32, R12, and C1 produce nominal

(but

not

less

than

V).

Normally, the junction of D17, D18, R57, and R49 is

+3.9 V (peak) normal line voltage pulses which are

clamped to +5.5 V (nominal) via D17, which is con-

coupled to the noninverting input of the

nected to the +5 V output. Voltage divider R49 and

comparator via R48. R8 and R9 produce a +2.5V

low

R350 provide a portion of the sensed voltage to the

reference for the comparator’s inverting input. The

comparator’s inverting input. This voltage is normally

comparator’s normal output is a series of pulses

2.7V, causing the comparator’s output to go low. The

occurring at twice the ac power line frequency. Each

low signal forward biases DC ON panel indicator driver

positive-going leading edge retriggers the 16.5 ms

transistor Q10, producing a DC ON indication, and

one-shot, keeping it in the set state. The 16.5 ms

reverse biases the BDCOK H FET bus driver Q6. As a

one-shot output is diode-ORed with DCOK L via

result, Q6 cuts off, and its source voltage risesto +5V,

diodes D25 and D23 and PWR OFF/FAIL H via D24.

producing the active BDCOK H signal.

Normally, the three signals are low and Q11 remains

cut off. In this condition, C4 charges to +3.125 V via

A low +5 V output results in a decrease in voltage at

R36 and R38. This signal is then applied to the power

the voltage comparator’s inverting input. A voltage less

OK comparator’s inverting input via R24. Since the

then 4.6 V reduces the voltage at the comparator’s in-

noninverting input is referenced to +2.5 V by voltage

verting input to less than the +2.5 V reference. Hence,

divider RS and R6, the comparator’s output goes low,

the comparator’s output goes high, turning off the DC

biasing off FET QS. QS’s source voltage then rises

ON indicator and allowing Q6 to conduct. Q6 asserts

toward +35 V via R46 producing the active BPOK H

the BDCOK H bus signal low, indicating that a dc
power-fail condition exists.

signal.

The low +12 V operation is similar to that described

for low +5
V operation. An output voltage less than
11.3 V results in

BDCOK H being asserted

low

Power-up/power-down

sequence

timing

shown in Figure 4-34.
A power failure is first detected when the pulsating dc

voltage at the ac low comparator’s noninverting input
is less than +2.5 V (peak). The comparator’s output

then remains low, allowing the 16.5 ms one-shot to go

(power-fail condition).

out of the retrigger mode. The one-shot resets 16.5 ms
AC

voltage

monitor

circuits

include

low

after the leading edge of the last valid ac voltage alter-

comparator, 16.5 ms delay, and a BPOK H bus driver

nation; the 16.5 ms delay is equivalent to a full line

circuit which is enabled only when BDCOK H is in the

cycle (two-alternation)

failure.

The

high

one-shot

INPUT

—DI 0-10ms

|[e—

BPOK H

f¢—

70ms (MIN)—fi

—»

5-1Oms

|@—

POWER OFF L

(PSEUDO DELAY)

——0{

j— {-3ms

—

I‘—3—10ms

—

|a—O-1ms

BDCOK H

—

—10ps-20ms

DC OUTPUT
VOLTAGES

CP-1823

Figure4-34

Power-Up/Power-Down Sequence

output is then coupled via D23 to the base of Q11, forward biasing it. Q11 conducts and rapidly discharges

The DC ON/OFF switch simulates a power failure
when it is placed in the OFF position. Cross-coupled

C4; R36 limits peak discharge current. The low voltage
thus produced is less than the 4-2.5 V reference at the

inverters provide switch debounce protection and a low
(false) DC ON H signal is produced. This signal is
ORed with AC LO L, causing a power-fail sequence to

power OK comparator’s input, and its output goes
high. QS then conducts and asserts the BPOK H signal

occur as previously described. BPOK H is immediately

low (power fail). The AC LO L signal produced by the

asserted low. After the 5—10 ms pseudo delay, dc
switching regulator operation is inhibited and dc power

16.5S ms one-shot is ORed with the DC ON H signal,
producing a high POWER OFF/FAIL H signal. This
signal reverse biases D26, allowing C13 tochargeto 5 V

via R40. After a 5—10 ms (approximately) “pseudo
delay,” C13’s voltage rises above the dc off voltage

OFF/FAIL H goes low, rapidly discharging C13.
POWER OFF L then goes high and switching

comparator’s +2.5 V reference (noninverting) input.
The comparator’s output goes low, asserting POWER

from

the

backplane.

When

the

switch is returned to the ON position, PWR

regulator operation resumes. Approximately 100 ms
later, BPOK H goes high and normal processor

OFF L low and turning off the switching regulators

operation is enabled. DC ON/OFF circuit timing is

(Paragraph4.9.3.4).

shown in Figure 4-35.

When normal power is restored, the 16.5 ms one-shot

BEVNT L is the bused interrupt requet line which is

returns to the retrigger (set) mode. AC LO L goes high

normally used for line time clock interrupts. Q4 is
forward-biased during positive alternations of the ac

(false) and PWR OFF/FAIL H goes low, discharging
C13. The dc off voltage comparator’s inverting input
immediately goes

removed

ON/OFF

low and

its output

goes

line and produces low-active BEVNT L signals. D1
clips negative alternations and limits Q4’s reverse base

high,

enabling switching regulator operation. The low AC

to emitter voltage.

LO H one-shot output removes forward bias from the

base of Q11, cutting it off. Its collector voltage then

The RUN indicator is illuminated whenever the proc-

rises as C4 charges at a relatively slow rate. R38

essor is executing programs. SRUN L, a non-bused

controls the charging rate of C4 and ensures that ac

backplane signal, is a series of pulses which occur at

voltage

for

3—3Sus intervals whenever the processor is in the Run

approximately 100 ms (70 ms minimum) before BPOK

mode. The pulses trigger a 200 ms one-shot on each
SRUN L pulse leading edge, keeping it in the retrigger

and

output

voltages

are

normal

H goes high.

ON/OFF

SWITCH OFF

—»

5-10ms

f——
-

BPOK H

f—

70ms(MIN)

—>l

POWER OFF L

(PSEUDO DELAY)

O-1ms —» l‘—

--ol

4— (-3 ms

BOCOK H

10us—20ms —

—

4—
3 -10ms

DC OUTPUTS

Figure4-35

DC ON/OFF

4.47

Circuit Timing

CP-1824

mode. Its high RUN H output signal is then inverted,

4.9.4

producing a 0 V signal that turns on the RUN

H780 connections are shown in Figure 4-36. The

H780 Connections

indicator. When the processor is in the Halt mode,

H9270 backplane connections and interconnecting

SRUN L pulses cease and the 200 ms one-shot resets

cables are also shown. Note that cable connectors are

after the 200 ms delay. The RUN indicator turns off,

wired 1:1. Both connectors on the H780/H9270 signal

indicating the Halt mode.

cable are 10-pin connectors which are wired in exactly
the same manner, as listed in Figure 4-36. Similarly,

The HALT/ENABLE switch allows the operator to

both ends of the panel signal/power cable are wired to

manually assert the BHALT L signal low, causing the

16-pin connectors inthesame pin/signalconfiguration.

processor to execute console ODT microcode. When in
the ENABLE position, BHALT L is not asserted, and
the Run mode is enabled. Cross-coupled inverters
provide a switch debounce function.

FRONT PANEL

12-PIN

CONNECTOR

H780 POWER SUPPLY

P.C. BOARD

AC POWER
CABLE
]

PWR XFMR

O-PIN
CONNECTOR
QZJ

P.C. BOARD

Akt

16-PIN SOCKET

16-PIN
SOCKET

PANEL
SIGNAL/POWER

CABLE ({1in.)

/
DC POWER CABLE (12in.)

SIGNAL CABLE (10 in.)

H9270

2y 1

’@']+5V

+5vB

BEVNT L
SRUN L

(KEY)

GROUND
CL3 L
CsS3 L
CSPARE
BHALT L
DCOK H

SIGNAL

+5A

114
12
13
14
15
16

SPARE
SPARE
GROUND
DCOK
CS3 H
BHALT L

DCONH
SRUNL
SPARE
GROUND
CL3 L
CS3 L
CSPARE

SIGNAL
SPARE

10-PIN CONNECTOR ON FRONT (SIDE {) OF

BEVNT L—\

BPOK H

\—PIN
O~NOODUN—-

N SIGNAL

ammqmwauw-

L._

—

P.C. BOARD

BHALT L

H9270 BACKPLANE REAR VIEW
{P.C. BOARD S{DE 2)

gQ'SN L

BPOK H

Lo | eno
®|

GND

@
/

TERMINAL BLOCK

CP-1825

Figure4-36

H780 Connections

4-48

CHAPTER)S

USING KD11-F and KD11-JPROCESSORS

5.1

GENERAL

Table 5-2
KD11 Factory Jumper Configuration

Before installing and using the KD11-F or KD11-J
processor in the LSI-11 or PDP-11/03 system, the user

must

select

certain

processor

features

Jumper | Installed |Removed

(jumper-

Function

selected), determine where the processor and option
modules should be installed on the backplane, be

aware of trap and interrupt functions, and ensure the

conditions for bus initialization. These items are dis-

cussed in detail in the following paragraphs.

5.2

JUMPER-SELECTED FEATURES

5.2.1

X
BANK 1 Disabled
X
X
BANK 1 Enabled
(KD11-F){ (KD11-I){(KD11-F only)

X
X
Memory Refresh
(KD11-J) |(KD11-F){Enable (KD11-F only)

General

Wire-wrap posts are provided on the LSI-11 microcomputer module to allow the user to select various

Power-Up

features, as listed in Table 5-1. These features include:

Line Time Clock
Enable

Aflg

} Mode0
L

memory refresh enable/disable, line time clock (LTC,
or external event interrupt) enable/disable, power-up

mode selection, and resident memory bank selection
(KD11-F only). Jumpers are located as shown in Figure
S-1. Jumpers are factory-installed as listed in Table 5-2
and can be altered by the user

for a

particular

application, as described in the following paragraphs.
w5 |

Table 5-1
Summary of KD11 Jumpers
W1|W2|W3IW4|W5|W6

Function

|R|X|X | MemoryRefresh

|Power-Upto24

X|X|X|X]|I

|Power-UptoODT

X|X|{X|X|R]|I

|Power-Upto173000

X|X|X|X|I

|Power-Uptospecial

R|I

|X |Resident MemoryBank 0

M7264

{R|X

ETCH REV. C, D

o708

NOTE
Figure5-1

5.2.2

Jumper Locations

Memory Refresh

The LSI-11 processor has the capability of completely
controlling

|X | X |Resident MemoryBank 1

the

refreshing

all

dynamic

MOS

memories in a system when jumper W4 is removed.

NOTE

Memory refresh is always required when dynamic

X = Don’t Care
I

wi |

W1 through W6 are wire-wrap jumpers

microcode
|X | X

w2 |

wa |

|X | X |Line Time Clock Enable

X|X|X|X]|R|R

wé |

w3 |

MOS memory devices are used in the LSI-11 system,

= Installed

R = Removed
5-1

such

the

KDI11-F

resident

the

KD11-F or KD11-J processor (M7264) module. Note

MSV11-B 4K by 16-bit read/write memory module.

that the jumpers affect only the power-up mode (after

memory

and

The refresh operation can be controlled by a device

BDCOK H and BPOK have been asserted); they do not

other than the LSI-11 processor, if available, such as a

affect the power-down sequence.

DMA refresh device. If such a device is used, or if no

dynamic MOS memory devices are present in the

The state of the BHALT L signal is significant during

system (KD11-J), install W4. The refresh sequence is

the power-up sequence. When this signal is asserted, it

described below.

causes the processor’s ODT console microcode

subset of an Octal Debugging Technique program) to
The processor’s memory refresh sequence is controlled

become invoked after the power-up sequence.

by resident microcode inthe processor which is initiated

console device must be properly installed for correct

by an interrupt that occurs once ever 1.6 ms. It is the

use of the BHALT L signal.

The

highest priority processor interrupt. Once the sequence
is initiated, the processor will execute 64 BSYNC

The power-up modes are listed in Table S-3. Detailed

L/BDIN L bus transactions while asserting BREF L.

descriptions of each mode are provided in the para-

The BREF L signal overrides memory bank address

graphs which follow.

bits 13—15 and allows all memory units to be simultaneously

enabled.

After

each

bus

transaction,

Table 5-3

BDAL1—6 L is incremented by 1 until all 64 rows have

Power-Up Modes

been refreshed by the BSYNC L/BDIN L transaction.
This process takes approximately 130 us during which
external interrupts (BIRQ L and BEVNT L) are ignored.

However,

DMA

requests

can

Mode

Mode Selected

granted

between each of the 64 refresh transactions.

5.2.3

Jumpers
W6 lWs

Line Time Clock

LTC (or external event) interrupts are enabled when

R | R

|PCat24and PS at 26, or Halt mode

R | I

|ODT Microcode

| R

[PCat 173000 for user bootstrap

| T

jumper W3 is removed and the processor is running.

|Special processor microcode
(not implemented)

The jumper can be inserted to disable this feature. The
LTC interruptis initiated by an external device when it
asserts the BEVNT

L signal. This is the highest priority

external interrupt request; processor interrupts have

NOTE
R = Jumper Removed
I

= Jumper Installed

higher priorities. If external interrupts are enabled (PS
bit 7 = 0), the processor PC (R7) and PS word are

Power-Up Mode 0

pushed

This option places the processor in a microcode se-

onto the processor’s stack.

The

LTC

(or

external event device) service routine is entered by

quence that fetches the contents of memory locations

vector address 100 ; the usual interrupt vector address

24 and 26 and loads their contents into R7 and the PS,

input operation by the processor is not required since

respectively. A microcode service translation at this

vector 100

is generated by the processor.

point interrogates the state of the BHALT L signal;

The first instruction of the service routine will typically

be fetched within 16 us from the time BEVNT L is

either enters ODT microcode (BHALT L asserted low)
or begins program execution with the current contents

asserted; however, if optional EIS/FIS instructions are

of R7 as the starting address (BHALT L not asserted).

depending on the state of this signal, the processor

being executed, this time could extend to 50.45us. This
time

could

also

trap

Note that the T-bit (PS bit 4) is loaded with the contents

execution (memory refresh, T-bit, power fail, etc.), or

of PS bit 4 in location 26. This mode should be used

extended

processor

by asserting the BHALT L signal.

only with nonvolatile memory locations 24 and 26 or
with BHALT L asserted. This power-up sequence is

5.2.4

Power-Up Mode Selection

shown in Figure 5-2.

Since the LSI-11 can be used in a variety of system

applications that have either (or both) volatile (semi-

Power-Up Mode 1

conductor read/write) or nonvolatile (PROM or core)

This mode immediately places the processor in the
console microcode regardless of the state of the
BHALT L signal. This mode assumes a console inter-

memory, one of four power-up mode features are

available for user selection. These are selected

(or

changed) by wire-wrap jumpers W5 and W6 on the

face device at bus address 177560.

GET

PC FROM 24

MODE 0

POWER UP

SELECTED

BHALTL

YES

ASSERTED

PS FROM 26

EXECUTE

»’

CONSOLE
ODT uCODE

BEGIN PROGRAM

USE ANOTHER
POWER UP

EXECUTION

MODE

11-3156

Figure 5-2

Mode 0 Power-Up Sequence

set up a valid stack pointer (R6). This option should be

Power-Up Mode 2
This mode places the processor in a microcode se-

used with nonvolatile memory (ROM, PROM, or core)

quence that loads a starting address of 173000 into R7

at address 173000. A time-out trap through location 4

and begins program execution at this location if the

will occur if no device exists at location 173000.

BHALT L signal is not asserted.

If BHALT L is asserted, the processor will not execute
(T-bit) is cleared and bit 7 (interrupt disable) is set.

the instruction at location 173000 and will immediately
execute the console microcode. This power-up mode

The user’s program must set these bits, as desired, and

sequence is shown in Figure 5-3.

Note that before 173000 is loaded into R7, PS bit 4

EXECUTE

MODE

POWER UP

YES

PC < 173000

SELECTED

PS (BIT 4) <~ 0

—

PS (BIT 7) <1

BHALT L

ASSERTED

FIRST

INSTRUCTION

AT
173000

CONTINUE
PROGRAM
EXECUTION

EXECUTE

USE ANOTHER

CONSOLE

POWER UP OPTION

ODT uCODE

11-31567

Figure 5-3

Mode 2 Power-Up Sequence

5.2.5

Power-Up Mode 3
This

microcode

sequence

microcode expansion

allows
the

access

fourth

microm

Resident Memory 4K Address Selection

Jumpers W1 and W2 are used for selecting the 4K

to future

(bank) address for the KD11-F resident memory. Only

page

one jumper must be installed, as follows.

(microlocations 3000 to 3777). After BDCOK H and
BPWROK H are asserted and the internal flags are

cleared, a micro jump is made to microlocation 3002. If

W1 installed = Bank 1 (addresses 20000—37776)

this option is selected and no microm responds to the
fourth page microaddress,

W2installed = Bank O (address 0—17776)

a microtrap will occur

through microlocation O which will, in turn, cause a reserved user instruction trap through location 10.
NOTE

Note that the state of BHALT L is not checked before

If no jumper is installed, the 4K resident memory

control is transferred to the fourth microm page.

will not respond to any address.

5-3

5.3

INSTALLATION

manner and arbitrate DMA requests; all external in-

Prior to installation, the processor module jumpers
must be configured as directed in Paragraph 5.2.
PDP-11/03 systems are shipped from the factory with

terrupts are ignored.

The Halt mode can be entered in one of four ways:

the KD11-F or KD11-J processor installed. Refer to

When the BHALT L signal is asserted.

Chapter 11 for LSI-11 processor module installation
details.

When

HALT

instruction

has

been

executed.

5.4

USINGTHELSI-11 MICROCOMPUTER

5.4.1

By power-up sequence.

When a double bus error has occurred [a bus

General

error trap with SP (R6) pointing to non-

Most of the operational characteristics are discussed in
the LSI-11, PDP-11/03 Processor Handbook and re-

existent memory].

lated software publications. This discussion includes
the use of the LTC (external event interrupt) feature,

The LSI-11 microcomputer does not use conventional
control panel lights and switches. Instead, the ODT
console microcode routine provides all control panel

bus initialization, and trap and interrupt priority.

features on a peripheral device which can be interfaced

5.4.2 Interrupt and Trap Priority
Interrupts

and

traps

are

quite

similar

at bus address 177560 and interpret ASCII characters.
In a typical configuration there is no bus device that

their

operation. Interrupts are service requests from devices

responds

to address 177570 (the PDP-11 SWR
address). The peripheral device used with the ODT
console microcode is called the console device, which

external to the processor; traps are interrupts which
are

generated

within

the

processor.

Their

main

operational difference, however, is that external in-

can be any device capable of interpreting ASCII

terrupts can only be recognized when PS priority (bit 7)

characters.

The prompt character sequence and
detailed use of console ODT commands are contained

is zero; traps can be executed at any time, regardless of
the PS priority bit status.

inthe LSI-11, PDP-11/03 ProcessorHandbook.

The highest priority trap is memory refresh, when
enabled (Paragraph 5.2.2). Memory refresh does not

5.5 INITIALIZATION AND POWER FAIL
Initialization occurs during a power-up or power-fail

require an interrupt vector since it is entirely controlled
by processor microcode; memory refresh operations
are completely transparent to the user programs and

sequence, or when a RESET instruction is executed.

The processor responds to these conditions by asserting

the BINIT L bus signal. BINIT L can be used to clear or

PS bits are not altered in any way. The remaining
traps, including EMT, BPT, 10T, and TRAP instruc-

initialize all device registers on the bus. In addition, the
DRV11 parallel line unit applies the buffered initialize

tions, and hardware-generated Trace Trap, Bus Error,

signal to pins on both of its device interface connectors

Power Fail, etc. are described in the LSI-11, PDP-11/

for initializing the user’s device.

03 Processor Handbook. The LTC (external event) interrupt has the highest priority of all external in-

During the power-up sequence, the processor asserts

terrupts, when enabled (Paragraph 5.2.3). It is ack-

BINIT

nowledged (serviced) only when PS priority bit 7 = 0.

supply-generated BDCOK H signal. When BDCOK H

response

passive

(low)

power

This interrupt always uses vector address 100 . It loads
a new PC from location 100 and a new PS from location

and

102. All other external interrupts are requested by a

executed.

device asserting the BIRQ L signal. If PS bit 7 = 0, the

supply-generated BPOK H signal goes passive (low)
and causes the processor to push the PC and PS onto

goes active (high), the processor terminates BINIT L

request is acknowledged and the processor inputs a
user-assigned vector address for the device’s service

the

jumper-selected
Similarly,

power-up
power

fails,

sequence
the

power

the stack and enter a power-fail routine via vector

routine PC (starting address) and PS. For example,
when the requesting device is the console device,

location

24.

The

processor

will

execute

user

power-fail routine until either BDCOK H goes passive

vectors 60 (console input) or 64 (console output) are
used. These vectors are reserved for the console device

(low), indicating that dc operating power may not
sustain processor operation, or BPOK H returns to the

by most DIGITAL software systems.

active state. BINIT L will go active if BDCOK H goes
passive.

5.4.3

HaltMode

‘The LSI-11 microcomputer can operate in either a Run

Note that if a HALT instruction is executed after
entering the power-fail routine, the ODT microcode

or Halt mode. When in the Halt mode, normal program execution is not performed and the processor
executes

ODT

console

microcode.

will not be executed until BPOK H is reasserted. If
BPOK H goes passive while the processor is in the Halt

However,

the
processor will execute memory refresh in a normal

mode, the power-fail routine will not be executed.

5-4

CHAPTER6

LSI-11 INTERFACE MODULES

6.1

The remainder of this chapter described DLV11 and
DRV11 functions, jumpers, installation, interfacing to

GENERAL

Two LSI-11 interface modules provide a simple means
for interfacing peripheral devices to the LSI-11 bus.
The DLV11 is an asynchronous serial line interface
that is capable of transmitting and receiving 20 mA
current loop or EIA serial data, ranging in rate from S0
to 9600 baud. Two optional cable types are available
for connecting 20 mA or EIA devices to the DLV11.
The DRVI11 is a general-purpose parallel line interface. It is capable of storing and transmitting either

peripherals, and programming.

6.2

UNIVERSAL

ASYNCHRONOUS

9
2

BDALO -15L

H
o

BBS7 L
BSYNC L

BWTBT L

BDIN L

RCVR./XMTR.
(RBUF ,XBUF)

6.2.2

Jumper-Selected Addressing,

Vectors,

and

SERIAL DATA

B
OPTIONAL

1
ADDRESSING,
'NTERRUPT
AND I/0 '

General

Module Operations

bytes or 16-bit words.

BDALO-15L

6.2.1

The DLV11 Serial Line Unit interfaces serial 1/0
devices to the LSI-11 bus, as shown in Figure 6-1.

two 8-bit bytes or one 16-bit word, and receiving 8-bit

DLV11 SERIALLINE UNIT

BREAK

LoaiC

EADER
«—»|

CONTROL LOGIC

(RCSR, XCSR)

INTERFACE

CIRCUITS
(20mA OR
EIATO TTL)

DEVICE

BCO5M (20mA)

—

RUN

TO / FROM

—

BCOSC (ETA)

LOGIC

BDOUT L
BRPLY L
BINIT L
BIRQ

BIAKO L

BIAKIL
CP-1800

Figure6-1

DLV11 Serial Line Unit

6.2.2.1 Locations— Thirty jumper locations are pro-

vided on the DLV11 module, as shown in Figure 6-2.
Jumpers are installed at the factory for use as the
console device (Paragraph 6.2.7) and can be altered by
the user for his particular system application, as
described in the following paragraphs.

6.2.2.2 Addressing — Jumpers

involved

with

addressing include A3 through A12. Only address bits
03 through 12 are programmed by the jumpers for

correct

DLV11

addressing,

producing

the

16-bit

address word shown in Figure 6-3. The appropriate

jumpers are removed to produce logical 1 bits; jumpers
installed will produce logical 0 bits.

{
LI

(——L

TP1

A P
[$181475)

O~
[ 41414

,'1l"\

TP2 6
L=

INSERT .005uF CAPACITOR WHEN
THE SER{AL LINE DEVICE IS A

TELETYPEWRITER (LT33 OR LT35)

> - ND

P~ OOT0

woona

DPIDDOD>

o222

N’)d’lflwl OOOTN I
qqad

M7940 ETCH

qdZag

REV.B
cP-1801

Figure6-2

BDAL
BITS

DLV11Jumper Locations

1
=1 (L)

IIIIIIIIIIJ[

<«
—

<«

ADDRESS JUMPERS:
INSTALLED
=0
REMOVED =1

1
0= CSR

1= DATA BUFFER | (PART OF

0= RECEIVER
1= TRANSMITTER

RANGE = 1600008
- 177776 ¢
CP-ig02

Figure6-3

DLV11 Addresses

6-2

BDAL
BITS

]

{

’

I_ 01 == RECEIVER
TRANSMITTER

VECTOR\JUMPERS:
INSTALLED=0

REMOVED

RANGE
=0~ 3744
cP-1803

Figure6-4

6.2.2.3

DLVI11 Interrupt Vectors

Vectors — Jumpers involved with vector ad-

Table 6-1

dressing include V3 through V7. Only vector bits 03

Baud Rate Selection

vector

addressing,

producing

the

Baud Rate

16-bit

FR3

| FR2

DLV11

through 07 are programmed by the jumpers for correct

FRO

address shown in Figure 6-4. The appropriate jumpers

Removed

Installed

Removed

1800

2400
2400

4800

9600
External

Number of Stop Bits Transmitted

3 —

(via pin BH1)

2SB installed = One stop bit
2SB removed = Two stop bits

NOTE

Parity Transmitted

NP removed = No parity bit

NP and PEV installed = Odd parity

installed

removed

X = don’t care

loop interface operation. Remove EIA and remove or
install jumpers as desired for the functions listed
below:

NP installed and PEV removed = Even parity

6.2.2.5

Installed

1200

NB2

—~|

NB1

300

600

Number of Data Bits

= =

200

134.5

150

= R

UAR/T Operation — UAR/T operation is

programmed via jumpers NP, 2SB, NB1, NB2, and
PEV as shown below.

6.2.2.4

75
110

D] BT

are removed to produce logical 1 bits; jumpers installed

will produce logical 0 bits.

Baud Rate Selection — Baud rate is pro-

grammed via jumpers FRO through FR3 as shown in

Active Current Loop (Jumpers configuration as shown

Table 6-1.

in Figure 6-5.)

6.2.2.6

EIA Interface — EIA drivers are enabled
when jumper EIA is installed. This jumper applies -12

Transmit

CL3 and CLA4 installed

Receive

CL1 and CL2 installed

V to the EIA driver chip. It should be removed during

20 mA current loop operation.

Passive Current Loop Jumpers configured as shown in
Figure 6-6.)

6.2.2.7

20 mA Current Loop Interface — Jumpers

Transmit = CL3 and CL4 removed

CL1 through CL4 are associated with 20 mA current

Receive

6-3

= CL1and CL2removed

DLV 11 SERIAL LINE UNIT CIRCUITS

BCO5M CABLE ASSEMBLY

]

20mA DATA IN

cLe
=

Moo ¢ PF

oPTICAL

COUPLER

ACTIVE RECEIVE

opTicaL |2omapataoutr

so H—sf OPTICRL

cL3

ACTIVE TRANSmIT

CURRENT LOOP

., |

[

b
.
L
—

|
|
|—v, 2 & !I

CONSTANT CURRENT
D!ODE

MODE ENABLE \

+12V —WW\-

- 12V — AN~
READER

OO
cLa

READERRUN

Loalc

+12V —AAAv

ocic

ACTIVE RECEIVE

CURRENT LOOP

MODE ENABLE

|
|
|| L KK .,& ||

SERIAL OUT

SERIAL IN—

Py 5 ¢

hall

o< TTL SERIAL DATA Nl e o

MODE ENABLE

| 20ma/sTTL RCVD DATA | ,

CURRENT LOOP

SERIAL 20 mA DEVICE

: {AA & :

:":

: {5 & :

SERIAL OUT+

| CEE€ |

| <4< l

Efifi%’.fig_

| ,pp
o

-l

)

lJK/
| AY
N\ I|
|

<uu €

)

L
\_/

¢6¢

READER

ENABLE
+

l {AN 7€A I

SERIAL IN+

VW&
CP-1804

Figure6-5

Active 20 mA Current Loop Interface

The DLV 11 is supplied with jumpers CL1 through CIL4
wired for the active transmit, active receive mode
(Figure 6-5). When in this mode, serial current limiting
to 23 mA is provided by resistors (one each for transmit
and receive functions) connected to the +12 V source.
Note that when module power is removed, the 20 mA
transmit optical coupler closes the serial loop (active or
passive mode). When the DLV11 is used in the passive
20 mA mode (Figure 6-6), the serial device must produce the 20 mA current. Current limiting must be
provided for transmit and receive currents in the serial

determine the backplane slot in which the module will

device.

6.2.4

be installed. Then, check that jumpers are removed or
installed as described for your application (Paragraph
6.2.2). Connection to the peripheral device is via an
optional data interface cable. Cables are listed below.

Application

Cable Type*

EIA Interface

BC05C-X Modem Cable

20 mA Current Loop

BCOSM-X Cable Assembly

Interfacing with20 mA Current Loop Devices

When interfacing with 20 mA current loop devices, the

6.2.2.8

Framing Error Halt — A framing error halt
allows entry to console microcode directly from the
console device by pressing the BREAK key, producing
a framing error. A framing error occurs when the
received character has no valid stop bit. This error
condition is detected by the UAR/T. FEH is factoryinstalled, causing the assertion of BHALT L when the
framing error is detected. The processor then executes
console microcode.

6.2.3

Installation
Prior to installing the DLV11 on the backplane, first
establish the desired priority level (Chapter 3) to

BCOSM cable assembly provides the correct con-

nections to the 40-pin connector on the DLV11. The
peripheral device end of the cable is terminated with a
Mate-N-Lok connector that is pin-compatible with the
following peripheral options:
LA36 DECwriter
LT33 Teletypewriter
LT35 Teletypewriter
*The -X in the cable number denotes length in feet, as follows: -1, -6,
-10, -20, -25. For example, a 10-ft EIA interface cable would be ordered as BCO5C-10.

OLV11

SERIAL LINE UNIT CIRCUITS
(PASSIVE RECEIVE AND TRANSMIT)

BCOSM CABLE ASSY

SERIAL

20mA

DEVICE

i———+15V

[

20mA

OPTICAL

DATA

CL2

COUPLER

gv s ¢ P2

XS <

oL3

cL1o

cL4o
20mA|/TTL RCVDDATA
-

SIH <

T SERIAL
DATA IN

OPTICAL

q.Y:X4

vunel

SO H =" CouPLER [2oma pata | FKS

y§

RUN LOGIC|

READER

RUN

\ 2

‘

wé&——

15y

OPTICAL

SERIAL

ouT-

< 4 £

L I Lo 6
&

\NFES

SoemiaL | coupLeER [ DATA IN
'

READER ENABLE
-

SERIAL N +

|
|

-12v ——-'VW-——-—-————JW\'|—<EE{

READER

{5 é—l-c—SERlAL ouT
+

|
|

ouT

TS
CE<T
e

SERIAL

courleR [*~ DATA OUT

[

{ K &

OPTICAL

IN
=

< 3

SERIAL

P1 ¢

READER

ENABLE
+

AT
cP-1808

Figure6-6

Passive 20 mA Loop Jumper Configuration

VTOSB Alphanumeric Terminal

6.2.6

Programming

VTS0 DECscope

RTO02 Alphanumeric Terminals
DFO01-A Acoustic Telephone Coupler

6.2.6.1

Addressing— Addresses for the DLV11 can

range from 160000

through 17777Xg. The least signi-

ficant three bits (only bits 01 and 02 are used; bit 0 is

The complete interface circuit provided by the BCOSM
cable and the associated DLV11 jumpers is shown in

ignored) address the desired register in the DLV11, as
follows:

Figure 6-5.

Address

NOTE

Addressed Register

When the DLV11 is used with teletypewriter de-

vices, a 0.005 uF capacitor must be installed be-

1XXXX0

tween split lugs TP1 and TP2.

1XXXX2

RBUF (Receiver data buffer)

1XXXX4

XCSR (Transmit control/status)

1XXXX6

XBUF (Transmit data buffer)

After configuring the module jumpers and installing

RCSR (Receiver control/status)

the proper interface, the DLV 11 can be installed in the
backplane.

6.2.5

Address bits 03 through 12 are jumper-selected as
directed in Paragraph 6.2.2.2.

Interfacing with EIA-Compatible Devices

When interfacing with EIA devices, the BCOSC modem

cable provides the correct connection to the 40-pin

Since each DLV11 module has four registers, each re-

connector on the DLV11. The peripheral device end of

quires four addresses. Addresses 177560—177566 are

the cable is terminated with a Cinch DB25P connector

reserved for the DLV11 used with the console peri-

that is pin-compatible with Bell 103, 113 modems.
Connector pinning and signal levels conform to EIA

pheral device. Additional DLV11 modules should be

Specification RS232C. The complete EIA interface

allowing up to 30 additional DLV11 modules to be

circuit is shown in Figure 6-7.

addressed.

assigned addresses

6-5

from

175610 through

176176,

DLV11

B8CO5C MODEM CABLE

SERIAL LINE UNIT CIRCUITS
Al

EIA INTERFACE

_l_

JI_

EIA DATA IN

J1
&

oy :

|, . /1

Y \Ir

EIA/TTL RCVD DATA

+12V

>
EIA TRANS DATA

+3V

TO CSR

SELECTION
AND
GATING

v . v

(e ¢l

—

TRANSMITTED DATA

CARRIER
CLEAR TO SEND

DATA SETREADY

| (BB ¢l
|
|
: ( T &;
¢ &
'

¢ a¢ |

TCAL

2 ¢ | > BA
|

: (8 &b—
cF
|
I— 5 &+— c8
<25
&[

PROTECTIVE GROUND

|(8

< 3 &

RECEIVED DATA

]

(20¢+

| |
=—
7

BUSY

TAM< |

ENABLE JUMPER

I\J\ EIA TRANS DATA ; ¢ F ¢I

EIA

TTL SERIAL DATA IN } (e

SO H
-12v

(CINCH DB25P)

DATA TERMINAL READY

REQUEST TO SEND

PROTECTIVE_GROUND

<1 ¢ :

C7¢l—

SIGNAL GROUND

| :

I <{uu (Jl

SIGNAL GROUND

CP—-1806

Figure6-7

6.2.6.2

EIA Interface

Interrupt Vectors — Two interrupt vectors

are jumper-selected on each DLV11 as described in
Paragraph6.2.2.3:

Address

RCSR

177560

RBUF

177562

000XX0

Receiver interrupt vector

XCSR

000XX4

177564

Transmitter interrupt vector

XBUF

177566

Vectors can range from addresses 0 through 37X,.

Vector addresses must be assigned as follows:

Vectors 60 and 64 are reserved for the console peri-

pheral device. Additional DLV11 modules should be
assigned

vectors

following

any

DRV11

Interrupt Vector

installed in the system starting at address 300.
6.2.6.3

Console Receiver

000060

Console Transmitter

000064

Word Formats — The four word formats

associated with the DLV 11 are shown in Figure 6-8 and

6.3

are described in Table 6-2.

6.3.1

6.2.7

Address

modules

Console Device

DRV11PARALLEL LINE UNIT

General

The DRV11 Parallel Line Unit is a general-purpose

The console device is a serial line device, such as the

device interface module that connects parallel 1/0
devices to the LSI-11 bus, as shown in Figure 6-9.

LA36 DECwriter, that uses a DLV 11 Serial Line Unit.
The following device addresses must be used for the

6.3.2

console device:

6-6

Jumper-Selected Addressing and Vectors

Table 6-2
Word Formats
Word

Bit(s)

RCSR

Function
Dataset Status — Set when CARRIER or CLEAR TO SEND and
DATA SET READY signals are asserted by an EIA device. Readonly bit.

14—08 Not used. Read asO.
07

Receiver Done — Set when an entire character has been received
and is ready for input to the processor. This bit is automatically
cleared when RBUF is addressed or when the DBCOK H signal

goes false (Iow). A receiver interrupt request is generated by the
DLV11 when this bit is set and receiver interrupt is enabled (bit 6 is

also set). Read-only bit.
06

Interrupt Enable — Set under program control when it is desired to

generate a receiver interrupt request when a character is ready for
input to the processor (bit 7 is set). Cleared under program control
or by the BINIT signal. Read/write bit.
05—01

Not used. Read as 0.

Reader Enable — Set by program control to advance the paper
tape reader on a teletypewriter device to input a new character.

Automatically cleared by the new character’s start bit. Write-only
bit.
RBUF

15—08 Not used. Read asO.

07—00 Contains five to eight data bits in a right-justified format. MSB is
the optional parity bit. Read-only bit.
XCSR

15—-08 Not used. Read as 0.
07

Transmit Ready — Set when XBUF is empty and can accept

another character for transmission. It is also set during the powerup sequence by the BDCOK H signal. Automatically cleared when
XBUF is loaded. When transmitter interrupt is enabled (bit 6 also

set), an interrupt request is asserted by the

DLV 11 when this bit is

set. Read/write bit.
06

Interrupt Enable — Set under program control when it is desired to
generate a transmitter interrupt request when the DLV
11 is ready

to accept a character for transmission. Reset under program control or by the BINIT signal. Read/write bit.
05—01

Not used. Read asO.
Break — Set or reset under program control. When set, a con-

tinuous space level is transmitted. BINIT resets this bit. Read/
write bit.
XBUF

15—08 Not used.
07—00 Contains five to eight right-justified data bits. Loaded under program control for serial transmission to a device. Write only.

6-7

15
RCSR

[

DATASET
STATUS

RECEIVER
DONE

(READ ONLY)

READER
ENABLE

(READ ONLY)

(WRITE ONLY)

RECEIVER
INTERRUPT
ENABLE

(READ/WRITE)

(NOT USED)

—

DATA AND

PARITY

(5-7 BIT DATA IS RIGHT JUSTIFIED. PARITY IS BIT 7.
NO PARITY BIT IS PRESENT WHEN 8-BIT DATA IS USED.)

XCSR

TRANSMIT
READY
(READ ONLY)

BREAK
(READ/ WRITE)

TRANSMIT

INTERRUPT
ENABLE

(READ/WRITE)
15

XBUF

|
-

[

—

)

(NOT USED)

DATA
CcP-1807

Figure6-8

BDALO - 151

DLV11 Word Formats

RDOUTBUF

OUT 0-15

)

REQ A
BIRQ L

INT ENB A

BITAKS L

INTENB B

LSI-11 BUS

BDALO—15L

INTERRUPT

Losic

DRCSR

CSR1
NEW DATA ROY
A INTT
—

BBST L

BSYNC L

BDALO —15L
BWTBT L

BDIN L

ceolrt

ADDRESS
AND I/0

BINIT [|

TO /FROM
USER

DEVICE
LOGIC

REQ B

Cf’gg ,%0'-

CSR O
DATA TRANS

BINITL

BDALO—15L

ORINBUF

IN 0-15
—

CcP-1808

Figure 6-9

DRV 11 Parallel Line Unit

6-8

6.3.2.1

Locations — Jumpers for device address and

6.3.2.2

vector selection are provided on the DRV 11 as shown in

Addressing

—

Jumpers

involved

with

addressing include A3 through A12. Only address bits

Figure 6-10. Jumpers are installed at the factory for
address 167770 (DRCSR) and vectors 300 (interrupt A)

03 through 12 are programmed by jumpers for DRV11
addressing, producing the 16-bit address word shown
in Figure 6-11. The appropriate jumpers are removed

and 304 (interrupt B). These can be cut or removed by

the user to program the module for his system appli-

to produce logical 1 bits; jumpers installed will produce

cation, as described in the following paragraphs.

logical O bits.

[]

U
Ji1

LJ
J2

:_—VECTOR JUMPERS—_:
v4

| ve

| v

vé '
7

—

= —

ADDRESS JUMPERS

A3 —

Aa_

—- 8
—-Aié

T A2

| AS——=

LAS TM= _ _ _ _

—V1]

sLi

sL2

OPTIONAL EXTERNAL

CAPACITOR

(SEE PARA.63.4.6)

M7941 ETCH REV. €
cP-1809

Figure 6-10

15
1
—

DRV 11 Jumper Locations

8
1

?18(81:,) v

N
I

—

’

e
a

INSTALLED =0
REMOVED =1

DRV11 Device Address

6-9

1= high byte(8-15)
BYTE SELECT

O=low

[

ADDRESS JUMPERS:

Figure6-11

—

byte (0 -7

byte

{

OOX = DRCSR

Oon - DROUTBUF
I

)

LV3"—‘

| °1°
<

VECTOR JUMPERS:
INSTALLED=0
REMOVED =1

Figure6-12

REQUESTING

0:REQ A
1:=REQB

cP-1745

DRV11 Vector Address

6.3.2.3 Vectors — Jumpers involved with vector addressing include V3 through V7. Only vector bits 03
through 07 are programmed by the jumpers for DRV11
vector addressing, producing the 16-bit word shown in
Figure 6-12. The appropriate jumpers are removed to
produce logical 1 bits; jumpers installed will produce
logical O bits.

L (DRCSR-15) DEVICE

6.3.3

Installation

Prior to installing the DRV11 on the backplane, first
establish the desired priority level (Chapter 3) for the
backplane slot installation. Check that proper device
address and vector jumpers are installed, as directed in
Paragraph 6.3.2. The DRV11 can then be installed on
the backplane. Connection to the user’s device is via
optional cables.

N\
N\

T\I v

H854

CONNECTOR

HB856 CONNECTOR

11-3294

Figure6-13

J1orJ2 Connector Pin Locations

6.3.4

Interfacing to the User’s Device

6.3.4.1

When using the BC11K-25 cable, connect the free end
of the cable using the wiring data contained in Table

General — Interfacing the DRV11 to the

6-4. Refer to the Hardware/Accessories Catalog for
additional optional interface accessories.

user’s device is via the two board-mounted H854 40-pin
male connectors. Pins are located as shown in Figure

6-13. Signal pin assignments for input interface J2
(connector No. 2) and output interface J1 (connector

6.3.4.2
Output Data Interface — The output interface is the 16-bit buffer DROUTBUF). It can be either

No. 1) are listed in Table 6-3. Optional cables and

loaded or read under program control. When loaded
by a DATO or DATOB bus cycle, the NEW DATA
READY H 300 ns pulse is generated to inform the

connectors for use with the DRV11 include:

flat with H856 connectors on each end. Available

user’s device of the data transfer. The trailing edge of
this positive-going pulse should be used to strobe the

inlengths of 1, 6, 10, 20, and 25 feet.

data into the user’s device in order to allow data to

BC11K-25 — Signal cable, 20 twisted pair with

settle on the interface cable. The system initialize
signal (BINIT L) will clear DROUTBUF.

BCO8R-X* — Maintenance cable, 40-conductor

H856 connector on one end; remaining end is terminated by the user.

All output signals are TTL levels capable of driving

H856 — Socket, 40-pin female, for user-fabri-

eight unit loads except for the following:

cated cables.

NEW DATA READY = 30 unit loads
DATA TRANSMITTED = 30 unit loads

INIT (Initialize)* = 10 unit loads per connector
*The -X in the cable number denotes length in feet, as follows: -1,

-6,
-10, -12, -20, -25. For example, a 10-ft maintenance cable would be

*Common signal on both connectors.

ordered as BCO8R-10.

Table 6-3
DRYV11 Input and Output Signal Pins

Inputs
Signal

Outputs

Connector Pin

Signal

Connector Pin

INOO

ouTo0

INO1

ouUTO1

INO2

H, E

ouTo02

INO3

ouT03

INO4

OouUT04

INOS

ouTo05

INO6

OouUT06

INO7

ouT07

INO8

ouT08

INO9

ouT09

IN10

OuUT10

IN11

ouT11

IN12

OUT12

IN13

OUT13

IN14

OouUT14

IN1S

ouT15

REQA

NEW DATA RDY*

\AY

REQB

DATA TRANS#*

CSRO

CSR1

INIT

RR, NN

*Pulse signals, approximately 300-ns wide. Width can be changed by user.

6-11

Table 6-4

BC11K Signal Cable Connections

Twisted Pair

Color

Black/white-orange | black
wh-org

Black/white-yellow | black
Black/white-grey
Black/white-red

Connector

No. 1

No. 2

A | OPEN
B | OPEN

OPEN
OPEN

C | OUTOO0

DATA TRANS.

wh-yel

D | OPEN

OPEN

black

E | OPEN

INO2

wh-gry

F | OPEN

OPEN

black

H | OPEN

INO2

wh-red

| GND

GND

K | OUTO1

CSRO

wh-grn

L | OUTO4

GND

Brown/green

brown
green

M | GND
P | INIT

IN15
IN13

Brown/red

brown

N | OUTOS

IN14

red

R | OUTO06

GND

| GND

REQB

Black/white-green | black

Black/white-blue

Black/orange

black

wh-blu

T | OUTO7

GND

black

U | OUTO03

IN12

orange

| GND

IN11

w | OUTO8

IN10

wh-vio

X | OUT09

GND

black

Y | GND

INO9

red

Z | OUT10

INO8

Brown/yellow

brown
yellow

AA | OUTI11
BB | OUT12

GND
INO3

Black/blue

black

CC | GND

INO7

blue

DD | CSR1

GND

Brown/orange

brown
orange

EE | GND
FF | OUTI13

INO6
OPEN

Brown/blue

brown
blue

HH | OUT14
IJ | OUTI1S

INOS
GND

Black/yellow

black
yellow

KK | GND
LL | REQA

INO4
INO1

Brown/violet

brown
violet

MM | GND
NN | OUTO2

GND
INIT

Black/violet

black
violet

PP | GND
RR | OUTO02

GND
INIT

Black/green

black
green

SS | GND
TT | OPEN

GND
INOO

Pink/white-red

pink
wh-red

UU | GND
GND
VV | NEWDATARDY | OPEN

Black/white-violet | black
Black/red

6-12

Input Data Interface — The input interface

DATA READY and DATA TRANSMITTED pulse

is the 16-bit DRINBUF read-only register, comprising

widths. The module without external capacitance (as

gated bus drivers that transfer data from the user’s de-

shipped) will produce 300 ns pulses. The capacitor can

6.3.4.3

vice onto the LSI-11 bus under program control.

be added in the location shown in Figure 6-10 to pro-

DRINBUF is not capable of storing data; hence, the

duce the approximate pulse widths listed below.

user must keep input data on the IN lines until read by
the LSI-11 microprocessor. When read, the DRV11

Optional External

Approximate

generates a positive-going 300 ns DATA TRANS-

Capacitance (pF)

Pulse Width (ns)

MITTED H pulse which informs the user’s device that

the data has been accepted. The trailing edge of the

None

300

pulse indicates that the input transfer has been

1200
1800
6000

S00
600
1200

completed.

All input signals are one standard TTL unit load; in-

puts are protected by diode clamps to ground and +3

6.3.4.7

the optional BCO8R maintenance cable, the connec-

BCO8R Maintenance Cable — When using

tions listed in Table 6-S are provided. Cable connectors

6.3.4.4

Request Flags — Two signal lines (REQ A H

P1 and P2 are connected to DRV11 connectors J1 and

and REQ B H) can be asserted by the user’s device as

J2, respectively. Note that CSRO (J2-K), which can be

flags in the DRCSR word. REQ B is available via Con-

set or reset under program control, is routed to the

nector No. 2, and it can be read in DRCSR bit 15. REQ

REQ A input (J1-LL); similarly, CSR1 (J1-DD) is

A is available via Connector No. 1, and it can be read in

routed to REQ B (J2-S). Hence, a maintenance pro-

DRCSR bit 7. Two DRCSR interrupt enable bits, INT

gram can output data to DROUTBUF and read the

ENB A (bit 6) and INT ENB B (bit 5), allow automatic

same data via the cable and DRINBUF. DRCSR bits 0

their

(CSRO) and 1 (CSR1) can be used to simulate REQ A

respective REQ A or REQ B signals are asserted. In-

and REQ B signals, respectively. If the appropriate

generation

interrupt

request

when

terrupt enable bits can be set or reset under program

INT ENB

control.

signal will generate an interrupt request.

bit (DRCSR bits S or 6) is set, the simulated

In a typical application, REQ A and REQ B are

6.3.5

Programming

generated by Request flip-flops in the user’s device.
The user’s Request flip-flop should be set when ser-

6.3.5.1

vicing is required and cleared by NEW DATA READY

range from 160000

or DATA TRANSMITTED when the appropriate data

nificant three bits address the desired DRV
11 register

transaction has been completed.

as follows:

6.3.4.5

Addressing — Address for the DRV11 can
through 17777X,. The least sig-

Address

Initialization
— The BINIT L processor-gen-

Device Register

erated initialize signal is applied to DRV 11 circuits for
interface logic initialization. It is also available to the

1XXXX0

DRCSR

user’s circuits via connectors J1 and J2 as follows:

1XXXX2

DROUTBUF

1XXXX4

DRINBUF

Connector/Pin

Signal

J1/P

AINITH

device and should not be used for

J2/RR

BINITH

The following address assignments are normally used:

J2/NN

BINITH

Addresses 177560—177566 are reserved for the console

First DRV11

An active BINIT L signal will clear: DROUTBUF

DRCSR = 167770

data; CRCSR bits 6, 5, 1, 0; bits 16 and 7 (when the

DROUTBUF = 167772

maintenance cable is connected); and Interrupt Re-

DRINBUF = 167774

quest and Interrupt Acknowledge flip-flops.
Second DRV11

6.3.4.6

NEW DATA READY and DATA TRANS-

167760 to0 167764

MITTED Pulse Width Modification — An optional

capacitor can be added by the user to the DRVI11
module to extend the pulse width of both the NEW

6-13

Third DRV11

167750t0167754

DRV 11 addressing.

Table 6-5
BCO8R Maintenance Cable Signal Connections

Connector No. 2
Pin | Name

Table 6-5 (Continued)
BCO8R Maintenance Cable Signal Connections

Connector No. 1

Connector No. 2

Name

VV | OPEN

OPEN

IN14

OUT14

UU | GND

OPEN

IN15

OUT15

TT | INOO

OuUTO00

GND

OPEN

CSRO

REQA

RR | INITH

OPEN

GND

PP | GND

OPEN

INO2

OouT02

GND

Pin | Name

Connector No. 1
Name

NN | INITH

OPEN

GND

MM|

GND

INO2

OouTO02

LL | INO1
KK | INO4

ouTo01
ouTO04

K
L

D
C

OPEN
DATA TRANS

GND
OPEN

SS
TT

1]
GND
HH | INOS

GND
OuUTO05

M
N

B
A

OPEN
OPEN

GND
NEW DATARDY|

uUu
VV

FF | OPEN

INITH

EE | INO6

OuUT06

DD | GND

GND

6.3.5.2

CC | INO7

ouTO07

are jumper-selected in the range of 0 through 37X,.

GND

Interrupt Vectors — Two interrupt vectors

BB | INO3

OouTO03

The least significant three bits identify the interrupting

AA | GND

GND

function.

Z
Y
X

INO8
INO9
GND

OuUTO08
OouT09
GND

W
X
Y

IN10

OUT10

IN11

OUT11

Vectors 60 and 64 are reserved for the console device

IN12

OUT12

and should not be used for DRV11 vectors.

GND

000XXO0

Interrupt A

000X X4

Interrupt
B

REQB

CSR1

6.3.5.3

GND

sociated with the DRV11 are shown in Figure 6-14 and

IN13

OUT13

are described in Table 6-6.

15
DRCSR

Word Formats — The three word formats as-

| |

REQUEST B

REQUEST A |

INTENB
B

CSRI

INT ENB A

CSRO

(READ/WRITE)

(READ / WRITE)
15
DROUT BUF

DATA OUT

(READ/WRITE)

15
DRINBUF

DATA
IN

(READ ONLY)

Figure6-14

DRV11 Word Formats

6-14

CP-1746

Table 6-6
Word Formats
Word

Bit(s)

CRCSR

Function

REQUEST B — This bit is under control of the user’s
device and may be used to initiate an interrupt sequence or to generate a flag that may be tested by the
program.

When used as an interrupt request, it is asserted by
the external device and initiates an interrupt provided

the INT ENB B bit (bit 05) is also set. When used as a
flag, this bit can be read by the program to monitor external device status.
When the maintenance cable is used, the state of this

bit is dependent on the state of CSR1 (bit 01). This
permits checking interface operation by loading a O or
1 into CSR1 and then verifying that REQUEST B is
the same value.

Read-only bit. Cleared by INIT when in maintenance
mode.
14—08

Not used. Read as 0.
REQUEST A — Performs the same function as RE-

QUEST B (bit 15) except that an interrupt is generated
only if INT ENB A (bit 06) is also set.
When the maintenance cable is used, the state of REQUEST A is identical to that of CSRO (bit 00).
Read-only bit. Cleared by INIT when in maintenance
mode.
06

INT ENB A — Interrupt enable bit. When set, allows
an interrupt request to be generated, provided REQUEST A (bit 07) becomes set.

Can be loaded or read by the program (read/write
bit). Cleared by BINIT.

INT ENB B -— Interrupt enable bit. When set, allows
an interrupt sequence to be initiated, provided RE-

QUEST B (bit 15) becomes set.
04—02

Not used. Read as 0.
Can be loaded or read by the program (read/write
bit). Cleared by INIT.

CSR1 — This bit can be loaded or read (under program control) and can be used for a user-defined com-

mand to the device (appears only on Connector No. 1).
Whenthe maintenancecableisused, setting or clearing
this bit causes an identical state in bit 15 (REQUEST

B). This permits checking operation of bit 15 which
cannot be loaded by the program.
Can be loaded or read by the program (read/write
bit). Cleared by INIT.

6-15

Table 6-6 (Continued)

Word Formats
Word

Bit(s)

DRCSR

Function

CSRO — Performs the same functions as CSR1 (bit 01)
but appears only on Connector No. 2.
When the maintenance cable is used, the state of this

bit controls the state of bit 07 (REQUEST A).
Read/write bit. Cleared by INIT.
DROUTBUF

15—00

Output Data Buffer — Contains a full 16-bit word or
one or two 8-bit bytes: High Byte = 15—38; Low Byte
= 7—0.

Loading is accomplished under a program-controlled
DATO or DATOB bus cycle. It can be read under a

program-controlled DATI cycle.
DRINBUF

15—00

Input Data Buffer — Contains a full 16-bit word or

one or two 8-bit bytes. The entire 16-bit word is read
under a program-controlled DATI bus cycle.

6-16

CHAPTER7

USING MSV11-A AND MSV11-B
READ/WRITE MEMORY MODULES
7.1

GENERAL

7.3.1

MSV11-A (1K) and MSV11-B (4K) read/write memory

Addressing

MSV11-B address jumpers are located as shown in

modules provide temporary storage of user programs

Figure 7-4. The module is supplied with all address

and data in

low-power

jumpers

installed.

memory subsystem. Full address decoding is provided

address

and

on both module types. The user can select the 4K ad-

MSV11-B module.

inexpensive,

compact,

Figure

how jumpers

7-6

illustrates

are

assigned

16-bit

for

the

dress space (bank) in which the module is addressed by
installing

removing

jumpers.

Two

additional

7.3.2

jumpers are provided on the MSV11-A module for

Reply to Refresh

Only one dynamic memory module in a system is re-

selection of a 1K segment within the selected 4K bank.

quired to reply to the refresh bus transactions initiated

by the processor. The module selected to reply should
Both module types are LSI-11 bus-compatible and can

be the module with the slowest access time.

be accessed by the LSI-11 microcomputer or any DMA

enables or inhibits the MSV11-B reply as follows:

Jumper W4

device that becomes bus master. The MSV11-A and

MSV11-B interface with the LSI-11 bus as shown in

W4 installed: MSV11-B will not assert BRPLY

Figures 7-1 and 7-2, respectively.

in response to refresh bus signals.

7.2

BSYNC/BDIN transactions by asserting BRPLY

W4 removed: MSV11-B will reply to refresh bus

MSVi1-AJUMPERS

MSV11-A jumpers are located as shown in Figure 7-3.

Jumpers not installed represent logical Os; jumpers installed represent logical 1s. Address jumpers are assigned as shown in Figure 7-5.

The MSV11-B module requires a refresh sequence

7.3

the KD11-F or KD11-J LSI-11 microcomputer.

7.4

MSV11-BBUS RESTRICTION

once every 1.6 ms. This is performed automatically by

MSVI11-BJUMPERS

READ DATA

BDALO - 15L

D'%EEERS
RECEIVERS

1024
8Y 16-817
ADDRESS/WRITE DATA

MEMORY ARRAY

ADDR.

WRITE

o
-~

ADDRESSING

AND CONTROL

BSYNC

BRPLY

BDIN

BWTBT

BDOUT

BREF

BDCOK H
Figure 7-1

MSV11-A 1K by 16-Bit Read/Write Memory

7-1

CP-1747

READ DATA

BUS

EMORY ARR ARRAY

ADDRESS /WRITE DATA

MEMORY

LST -11 BUS

RECEIVERS

READ/

WRITE

ADDR.

ADDRESSING
AND CONTROL
BSYNC

BRPLY

BDIN

BWTBT

BDOUT

BDCOK

BREF

L
CP-1748

Figure 7-2

MSV11-B 4K by 16-Bit Read/Write Memory

e—

W4 emm—
W3

e———

o——
o

~ N

ZEEE

M7943

ETCH

REV

o171

Figure 7-3

M7944

MSV11-A Jumper Locations

ETCH REV B

Figure 7-4
7-2

ch-1740

MSV11-B Jumper Locations

BDAL
BITS

I7e)

————

—

—_——

1024 LOCATI ON ADDRESS

BYTE
POINTER

—

LIK SEGMENT
ADDRESS
JUMPERS

4K ADDRESS
SPACE JUMPERS

Figure 7-5

BDAL
BITS

CP-1750

MSV11-A Address Format/Jumpers

4096 LOCATION ADDRESS

BYTE
POINTER

4K ADDRESS
SPACE JUMPERS

cP-1883

Figure7-6

MSV11-B Address Format/Jumpers

7-3

CHAPTERS

USING MMV11-A CORE MEMORY

8.1

GENERAL

fore it is installed in the backplane is to select its bank

The MMV11-A core memory option comprises two

address. This is accomplished by opening or closing

modules (G653 and H223) which are mated by con-

switches in appropriateaddress bit locations to produce

nector pins in a single 8.5 by 10 by 0.9 inch assembly. It

the desired bank address decoding.

requires two device locations (electrical positions) on
the backplane when installed in slots A4-D4 (Figure

11-1); otherwise, because of its total thickness (0.9
inch), the MMV11-A requires four physical device

locations when installed in any other backplane slot.

8.2
8.2.1

address to which the MMV 11-A will respond.

be accessed by the LSI-11 microcomputer or any DMA
device that becomes bus master. It interfaces with the

General

bus as shown in Figure 8-1.

The only preparation required for the MMV11-A be-

decoding jumpers allow the user to select the 4K bank

The MMV 11-A is fully LSI-11 bus-compatible and can

SWITCH-SELECTED ADDRESSING

(Refer to Paragraph 11.3.3 for installation considerations.) Memory capacity is 4096 16-bit words. Address

BDAL O-I5L

BUS

READ DATA
CORE STACK

DRIVERS

AND

AND
RECEIVERS

READ/ WRITE CIRCUITS

ADDRESS/WRITE
DATA

(7]

o}
0]

READ / WRITE

TIMING

)
wy

CONTROL

BDALI3 —I5 L
TIMING
AND
CONTROL LOGIC

BSYNC L
BRPLY

BDIN L

BOOUT L
BWTBT L
8DCOK H
L
BREF L
BINIT

cP-1752

Figure8-1

MMV11-A 4K by 16-Bit Core Memory

MMV 11-A bank address switches are used as shown in

8.3

Figure 8-3.: The figure illustrates a 16-bit address and

The BDMGI L and BIAKI L bus

BUSRESTRICTIONS
lines

must be

how switches are assigned to each address bit. Open or

jumpered to BDMGO L and BIAKO L lines, res-

close switches to produce the desired bank address as

pectively, under the H223 module when installed be-

directed in the figure. Switches are located on the G653

tween the processor and I/0 device interface modules

module (component side) as shown in Figure 8-2.

in order to maintain daisy-chain signal continuity.

Pins which must be connected are:

From

Signal

AM2

AN2

BIAKI/OL

CM2

CN2

BIAKI/OL

AR2

AS2

BDMGI/OL

CR2

CS2

BDMGI/OL

Bus pins can be identified as shown in Figures 3-2 and
Sw3
SW4 (NOT USED)

]

Memory refresh is not required for this memory option.

If memory refresh is used for other memory options,
such

CP -1754

the

KDI11-F’s

resident

memory

MSV11-B semiconductor memory, the
Figure8-2

B8DAL
BITS

Bank Address Switch Locations

—* 15

and

not respond to the refresh operation.

ADDRESS

WORD TM

]

ADDRESS

SW3

Sw2

swi

BANK

ADDRESSES

Cc
Cc

C
Cc

Cc
0

0
1

0 - 4K
4 - 8K

Cc
o
0

0
0
Cc

C
o}
C

2
3
4

8 - 12K
12 - 16K
16 - 20K

20 - 24K

24 - 28K

28 - 32K

|
J

4096 LOCATION

PgIYNTTEER

NOTES:
1. C=8W ON ; O=SW OFF
_

2. Bank
7 (28 32K? normally
reserved for peripherals.
CP-1753

Figure8-3

MMV11-A Addressing

8-2

the

MMV 11-A will

CHAPTERY9
USING MRV11-A READ-ONLY MEMORY

9.1

GENERAL

(or removing) jumpers on the module. Similarly, when
using 256 by 4-bit chips, the user can jumper-select the

The MRV11-A (Figure 9-1) is a read-only memory
module which allows the use of user-supplied, prepro-

upper or lower 2K segment within the selected 4K ad-

grammed, programmable read-only memory (PROM)

dress bank. Note that 512 by 4-bit and 256 by 4-bit

and masked read-only memory (ROM) chips in a

chips cannot be mixed on a MRV11-A module; the

compact, nonvolatile memory subsystem. Depending

user configures jumpers on the module for the chip

upon chip types, the module’s capacity is either 4096

type being used.

16-bit words or 2048 16-bit words, using 512 by 4-bit or
256 by 4-bit chips, respectively. Full address decoding

is provided on the module. The user can select the 4K

A partial listing of manufacturer’s chips that will

address bank in which the module resides by installing

operate in the MRV11-A is given in Table 9-1.

CHIP ROWS

‘f//\\

>
12-15

BDAL - 15L

BUS
DRAx[E)RS

READ DATA

0O 1 2 3 4 5 6 7

8 -1
4—7

MEMORY
PROM/ROM

RECEIVERS
CHIP

SOCKETS

0-3
(__t_,)
]

[}

]

¢|

©f

owl

<|t

MEMORY ADDRESS AND

-—

INTERFACE CONTROL LOGIC

BSYNC
L
BDIN
L
BRPLY
L

</7
CP-1755

Figure9-1

MRV11-A Read-Only Memory

Table 9-1
MRV11-A Chips
512 by 4-Bit Chips

256 by 4-Bit Chips

Manufacturer or Source Model/Type |PROM/ROM | Model/Type | PROM/ROM

Digital Equipment Corp.

Intersil

| MRVI11-AC

PROM

—

IM5624

PROM

IM5623

PROM

8259

PROM

Signetics

9-1

the MRV11-A resides can be used by another memory
device, such as the MSV11-A 1K by 16-bit read/write
memory module. Jumpers on the MRV11-A can be cut
by the user to prevent an incorrect BRPLY L signal
from being generated when unpopulated locations are

Chips used must be tristate output devices which conform to the device pinning, data, and addressing
described in the remainder of this chapter.
The user can install chips in increments of four chips
each. When using 512 by 4-bit chips, memory expansion is in 512-word increments. When using 256 by
4-bit chips, memory expansion is in 256-word increments. Unused portions within the 4K bank in which

addressed on the module.

vyl
vl
v
v
M
U

W7 -

WC SEm——

W4 Emm——

s
Wi

WO
W17 a——

mam

W16 S

W15

W13 mee—

W14

W11 E——

W12 e

WO mam——

W10

M 7942 ETCH REV. D

Figure9-2

W2 S

‘A

'UTT_UT—UTT—UT—U——U_

The information contained in the remainder of this
chapter will enable the user to prepare the MRV11-A

CP-1756

MRV11-A Jumper Locations

9-2

for use (jumper-selected addressing and chip selection)

9.2.3

and includes information required for correct PROM

The user must consider both 4K bank address selection

and ROM programming.

9.2

Addressing and Reply

and BRPLY L signal generation when configuring a

JUMPER-SELECTED

ADDRESSING

module for use. Chips (either PROM or ROM, 512 by 4
or 256 by 4) are arranged in eight physical rows (CE0—

AND

CHIP TYPE

CE7) of four chips each. Entire rows can be unpopulated, allowing those addressed locations to be

9.2.1

used by read/write memory contained on another
module. When this is done, the BRPLY L jumpers

General

Jumpers which allow the user to select the 4K bank in

(W0—W?7) associated with the unused rows should be

which the module can be addressed and jumpers which

cut or removed to prevent the MRV11-A from re-

allow the use of 512 by 4-bit or 256 by 4-bit PROM (or

turning a BRPLY L signal when those rows are addressed. A listing of octal addresses (within a 4K

ROM) chips are provided on the MRV11-A. In addition, jumpers may be removed from the module to pre-

bank),

physical rows, and BRPLY L jumpers is
provided in Table 9-2; use data listed for the chip type

vent the module from generating an active BRPLY L
signal when a portion of the module is addressed that

being used.

does not contain PROM or ROM chips. Jumpers are
located as shown in Figure 9-2.

9.2.2

The 4K bank in which the MRV11-A

resides

programmed by connecting bank address jumpers

Chip Type Selection

W15—W17, as appropriate. The module is supplied
with no bank address jumpers installed (bank 0).
Jumpers not installed represent logical Os; jumpers in-

The module is supplied with jumpers W8, W9, and
W10 installed for use with 512 by 4-bit chips. When

using 256 by 4-bit chips, W8, W9, and W10 must be

stalled represent logical 1s.

cut or removed and jumpers W11 and W12 installed; in
addition, either W13 (lower 2K) or W14 (upper 2K)

Figure 9-3 illustrates addressing words used with the

must be installed to properly address the lower 2K or

MRV11-A. Refer to the addressing format for the type

upper 2K address segment within the 4K memory bank.

of PROM or ROM chips being used.

4
512X
PROM/ROM

CHIPS

L
|

[

]

4096
- LOCATION ADDRESS
(W8
- W10

INSTALLED;

|
J

W11
- W14 REMOVED)

|
BYTE
POINTER

<2
5

4K ADDRESS
SPACE JUMPERS

256
X 4

PROM/ ROM

CHIPS

|
'

|
l

4K ADDRESS

JUMPERS

]

2048- LOCATION ADDRESS

=
z 7
z
_
SPACE

(W11 AND W12

INSTALLED;

W8-W10 REMOVED)

]

BYTE

POINTER

HIGH/ LOW 2K SELECT
W13

3 INSTALLED:
INSTAL
2K (0-7777)

LOW

Wi4 INSTALLED;

HIGH 2K (1000-17777)

Figure9-3

MRV11-A Address Word Formats

9-3

cP-1757

Table 9-2

CEO
CE1

WO
w1

6000-7777
10000-1777
12000-13777
14000-15777
16000-17777

CE3
CE4
CES
CE6
CE7

4000-5777

9.3

CE2

0-777
10000-10777
1000-1777 | 11000-11777

2000-2777 | 12000-12777

CEQ
CE4

WO
W4

W3
W4
WS
Wwo
W7

3000-3777
4000-4777
5000-5777
6000-6777
7000-7777

CES
CE2
CE6
CE3
CE7

WS
w2
Woé
w3
W7

| 13000-13777
| 14000-14777
| 15000-15777
| 16000-16777
| 17000-17777

CE1l

locations. The actual chip within a row is designated by

PROGRAMMINGPROM AND ROM CHIPS

one additional digit (0, 1, 2, or 3). Hence, the data pins
are assigned to LSI-11 bus bits as listed in Table 9-3.

The actual procedure for loading data into PROM
chips or writing specifications for masked ROM chips
will vary, depending upon the chip manufacturer.
Those procedures are beyond the scope of this docu-

Table 9-3

ment. (See chip manufacturer’s data sheets.) However,

Data Pin Assignments

the user must be aware of the chip pins versus LSI-11

ChipPin | Chip0 | Chipl

data bit relationship, and the chip pin versus memory

Chip2 | Chip3

address bits. Address and data pins are described

BDAL3 | BDAL7 | BDALI11 | BDAL1S

BDAL2 | BDAL6 | BDAL10 | BDAL14

As previously discussed, chips are arranged in rows of

BDAL1 | BDALS | BDAL9

|BDALI13

four chips each. Each chip contains locations of four

BDALO | BDAL4 |BDALS

|BDALI12

below.

bits each. Hence, four chips are used to provide the

Addressing of chips is shown in Figure 9-4. All chips
used on the MRV11-A must conform to this information. Observe that the only difference between S12 by
4-bit and 256 by 4-bit chip pins is pin 14. The 512 by

16-bit data word formats for each row. Rows are de-

signated by their respective Chip Enable (CEO—CE?Y)
signals. Depending upon the chip type used, a row of
four chips contains 512 or 256 16-bit read-only memory
LSI-11 CHIP PIN SIGNIFICANCE

DALT L — Ag [T] /"] 18] Vec
DAL6 L — Ag [2]
DALS L

15] A;

A, E

DALS L

E Agor CE

DAL4 L — A3 [4]

13] cE

DAL L — Aq [5]

12] o,

DAL2 L — Ay [6]

[11] 0,

DAL3 L

[10] 03

— Ap [7]

6ND [8]

CHIP ENABLE

612 x 4-BIT PART
DALS L

(ROW)

256 x4-BIT PART
LOWER/UPPER

2K SEGMENT

(WITHIN BANK)

CHIP ENABLE

-——DATA PINS

9] 04
TOP VIEW

NOTE:

Designations immediately adjacent topins are typical
designations used by chip manufacturers —not LSI-11

designations. LST-11 designations for correct
addressing are located away from the chip. Observe that
these signals are low — active, they are double - inverted

bus signais ( low =logical "1").
IC- 0169

Figure 9-4

PROM/ROM Chip Pin Addressing

9-4

4-bit part uses this pin for address bit DAL9; the 256 by

error (timeout) because the processor will attempt to

4-bit part uses this pin for a chip enable when both

write into the same location. When fetching MTPS or

bank address and 2K segment address are true. Also

EIS instruction source operands, first MOVe the

note that bus address bits do not follow in sequence
with chip manufacturer’s address designations. The

general register. MTPS or EIS instruction can then be

pinning arrangement shown allows for the use of

executed using the general register contents as the

source operand from the PROM or ROM location to a

commonly available PROM and ROM chips and opti-

source operand. If desired, read-write memory could

mum (compact) MRV11-A module layout.

be used instead of the general register to temporarily
store the source operand.

9.4

PROGRAMMING RESTRICTIONS

9.5

Special care must be used when programming PROMs

TIMING AND BUS RESTRICTION

Addressed memory read data is available within 120 ns

or ROMs for use with MTPS instructions and KEV11

after the BSYNC L signal is received by the MRV11-A.

option EIS instructions. These instructions fetch
source operands via the DATIO bus cycle, rather than
the DATI bus cycle. Hence, fetching a source operand
from a PROM or ROM location will result in a bus

Logic on the module responds to DATI bus cycle only.
DATO or DATOB bus cycles will result in a bus time-

out error. Logic functions on the module are not affected by the bus initialize (BINIT L) signal.

9-S

CHAPTER10
USER-DESIGNED INTERFACES

10.1

GENERAL

‘This chapter contains sample circuits and information

R1:=120K, MIN.

R2:20K, MIN.

which can be utilized in user-designed hardware that is

C1 =10 pF, MAX.

installed on the LSI-11 bus. The user must ensure that

the circuit, as used in a particular application, conforms to the LSI-11 bus specifications included in
Chapter 3. The various interface module and prewired
backplane options previously described in this manual

OUT —=

are designed for ease of user prototype development.
However, in those applications that require a special

C?2

TRANSMITTER OFF (LOGICAL 0)
R3 = 120K, MIN.

interface module, hardware components listed in the

C2 = 10 pF, MAX.

Hardware/Accessories Catalog will enable backplane

TRANSMITTER ON (LOGICAL 1)

connector-compatible systems to be rapidly assembled.

10.2

R3 =

11 OHMS, MAX.

C2 =

10 pF, MAX.
11-3298

BUS RECEIVER AND DRIVER CIRCUITS

The equivalent circuits of LSI-11

bus-compatible

Figure 10-1

Bus Driver and Receiver Equivalent Circuits

drivers and receivers are shown in Figure 10-1. Any
device that meets these requirements is acceptable. To
45V

perform these functions, Digital Equipment Corpora-

%fi

tion uses two monolithic integrated circuits with the
characteristics listed in Table 10-1. A typical bus driver
circuit is shown in Figure 10-2. Note that DEC 8641
quad transceivers can be used, combining LSI-11 bus
receiver and driver functions in a single package.

TYPICAL

BUS

DRIVER
11-3307

Figure 10-2

Typical Bus Driver Circuit

Table 10-1

LSI-11 Bus Driver, Recelver, Transceiver Characteristics

Characteristic
Receiver
Input high threshold
(DEC 8640, | Inputlow threshold

DEC 8641)

Specifications Notes
VIH
VIL

1.7Vmin.
1.3Vmax.

1
1

1,3
2

Inputcurrentat2.5V

ITH

80uAmax.

Input currentatO VvV
Output high voltage

IIL
VOH

10uAmax.
2.4V min.

10-1

1,3

Table 10-1

(Continued)

LSI-11 Bus Driver and Receiver Characteristics

Characteristic

Specifications Notes

Output high current

IOH | (16 TTLloads) 2,3

Output low voltage

VOL

Output low current

IOL

Propagation delay to

TPDH|

high state

10nsmin.

4,5

35 ns max.

Propagation delay to

TPDL

low state

Driver

0.4Vmax.

(16 TTL loads) 2, 3

10nsmin.

:
4,5

35 ns max.

Input high voltage

VIH

2.0Vmin.

(DEC8881, | Inputlowvoltage

VIL

0.8Vmax.

DEC8641)

Input high current

ITH

60pAmax.

Input low current

IIL

—2.0 mA max. 6

Output low voltage

VOL

0.8Vmax.

IOH

25pA max.

1,3

TPDL|

25nsmax.

3,7

TPDH|

35nsmax.

35,8

at 70 mA sink
Output high leakage
currentat3.5V

Propagation delay to
low state
Propagation delay to

high state
NOTES
1.

Thisis a critical parameter for use on the I/O bus. All other
parameters are shown for reference only.
This is equivalent to being capable of driving 16 unit loads of

standard 7400 series TTL integrated circuits.
Current flow is defined as positive if into the terminal.
Conditions of load are 390 @ to +SV and 1.6 K Q in parallel
with 15 pF to ground for 10 ns min and S0 pF for 35 ns max.
Times are measured from 1.5V level on input to 1.5V level on
output.

This is equivalent to 1.25 standard TTL unit loading of input.
Conditions of 100 Q to +5V, 15 pF to ground on output.

Conditions of 1 K Q to ground on output.

Address/data bus interface is provided by DEC 8641

Bus receivers and drivers should be well grounded and

bypassed with capacitors. They should be located

quad unified bus transceiver ICs, keeping component

within 4 in. (of etch) from the module fingers which

count to a minimum. Note that the DEC 8641 IC at the

plug into the backplane.

bottom of Figure 10-3 shows complete address/data

10.3

clude only the interface signals required for device

I/0 signal connections; the remaining DEC 8641s inPROGRAMMED INTERFACE

A typical programmed I/0 interface is shown in Figure

addressing. However, those ICs will normally be con-

10-3. Note that only the control logic portion is shown

nected for the same type of data I/0 interface as shown

in detail. This circuit is capable of input and output

at the bottom of the figure for bits 0, 13, 14, and 15.

data transfers to and from four addressable data
registers in the user’s device. In addition, the reply gate

Addressing occurs in the 28-32K address range; BBS7

will respond to programmed 1/0 and vector transfers.

L is always asserted for this address range. Received

10-2

data/address bits R3 H—R12 H and BS7 H are applied

dress comparison is latched in each 8136 on the leading

to 8136 (address) hex comparator/latch ICs where they

edge of BSYNC L. The 8136 outputs will latch for the

are compared to a user-configured device address

duration of BSYNC L, producing an active device

produced by switches or jumpers. The switches or

selected (DEV SEL H) signal. The 74175 hex latch

jumpers must produce high logic levels for logical 1s

shown in Figure 10-3 latches address bits 0, 1, and 2 on

and low logic levels for logical Os. The result of the ad-

the leading edge of BSYNC L. Bits 1 and 2 encode four

+5v
DEC

8640

BS7 H

BBS7 L —oD

3304
6800

{
BDAL12 L —O
BDAL 11 L —O

DE401

soaLio L —o %6
BDALS L

—9

=
nian

ri1 1

8136
| ADOR

1° 27

=
T

* DEVICE

(OR

COMPAR
a
[

LATCH

BITS FROM SWITCHES

ADDR 1

+5YV

>~ R8H

)

cLk]7 9JouT pev SEL H %3309
SYNC H

BDALS L

ADDRESS

JUMPERS)

TYPICAL ADDRESS BIT CKT (10 RQD.):

-—

LerioH
[ ro

=
-

£330

6809

68080

ADDR BIT TO 8136

)

—

= R7H

BDAL? L

—O

BOAL6 L —O

eDeE4C1

BOMGI L —]
BOMGO L —
BOAL4

[ 9

8136

[~RSH.

COMPAR

—O

ADDR

-—

fa—
> %

T
<
CLK |7

—O

elour

R 1

BOAL3 L —
BDAL2

| 7

[~ R6H

» R3H

86 41

VECTOR EN L—>17

* R2 H

SA2 H

r‘PR1 H

BDAL1

—O

BIAKI L —] i9
BIAKO

SAT

74175

[
o

:_DE 8 40_=

SAO H

3T 13
O DATA |o—

BSYNCLI

BOIN L|

BDOUT Ly

SYNC H A

DIN H

:‘D

}

SAC L

DOUT

)

—
L

o[>

o—

—a STBA

-—o pate

|
BUS IN EN L
BINITL]
g> L
nimiaLize o
|._ — — — ...I 8521
RPLY H
BRPLY L
04

REPLY
7410

E:QTLA

WRITE

DATA

| WRITE

STROBES

Oo— | BYTE
Jo—
(1

74155

READ

WB H

BYTE

jo—

2410

7
|

[o—

¢ sTB8

)
7410

BWTBT L

"MUX
ADDR

L —

DATA

‘

VECTOR EN L

VECTOR
)

<+—

ENABLE
FROM

INTERRUPT
le——

l«—— T14

BDALI5 L —

BDALI3 L

—O

BDALO L

—Of

T15

e 113

8641

CKT

( FROM READ
[ DATA MUX

- R15 H
L

» R14
H | TO WRITE

. R13H

((DATA LATCHES

RO H

RO H TO ADDR LATCH

CP-1758

Figure 10-3

Programmed I/0O Interface

IRQ
A L
+3

RQST A H

EN A STATUS H
ENABLE A H

7408 }

lmoe

7474
e 5lzaKa

¢ _af

INT

EN A CLK H

IAK A

ENB A
a4

—4_[_\

P Fa

L—do "~ @

IAK

+3
X
EN A DATAH

+3-p P QIAKENBAH

7400

ENB

IRQBL
+5

3300

P01

BIAK T L

‘%seosz

TO REPLY GATE

DEC

8640

—VECTOR
L, ON PROGRAMMED
I/0 INTERFACE

IAK H
L1

DIN H
RCVRS. ON

1/0 INTERFACE | INITIALIZE >
PROGRAMMED

INITL

EN B DATA H
EN B CLK H

TO USER'S DEVICE

1‘74°°>° (VECTOR REQ A HI (\ecTOR 1T DALOZ)
VECTOR REQ B L

’

P
oFa

INT

ENB B

+3-{p

ENABLE B H l 7408 )

QfAKENB B H

IAK
ENB B

7474

c _Gf

DATA MULTIPLEXOR

3300

!
TO USER'S
DEVICE

» READ

+5v

]

RQST B H
EN B STATUS H

MB_L,, (VECTOR
READ DATAENMULTIPLEXOR
L)

—1—9

0o
IAK B
7474

e, ojfAxe

BIAK

8861

D_
7400

—

L esoa

ol
¢

BDOMGO L

cp-1827

Figure 10-4

Dual Interrupt Interface

unique bus addresses for user-supplied 1/0 functions.

IRQA L signal will go low (false), causing BIRQ to go

Address bit 0 is a byte pointer which is only used for

false. IRQA L is ORed with IRQB L and applied to a

DATOB or the write portion of DATIOB bus cycles.

type DEC 8881 bus driver, asserting the BIRQ bus

Read data should be multiplexed using stored address

L, producing a high DIN H signal. This signal clocks

signal line. The processor responds by asserting BDIN
bits SA1 Hand SA2 H. In addition, an interface circuit

the device states (A or B requesting or not requesting

that also includes interrupt logic should use VECTOR

service) into the IAK flip-flops. At a later time, the

EN L to inhibit register read data and enable the

processor asserts BIAKI L, producing a high IAK H

interrupt

vector

transfer

during

the

interrupt

signal. IAK H is gated with the IAK flip-flop signals,
giving the highest priority to Request A, if both are re-

sequence.

questing service. The 7400 gate associated with the
Write data strobed for the four addressable device

IAK A flip-flop Q output goes low, clearing the IAK

registers are produced by a 74155 dual 2:4 demulti-

ENB A flip-flop, and producing VECTOR H and

BRPLY L signals. VECTOR H is used for gating the

plexer; however, other devices and circuits can be used.
Both sections of the 74155 are simultaneously strobed

vector address bits onto the I/0 bus. With the device’s

by the WRITE DATA EN L signal. During word trans-

IAK ENB flip-flop clear, it will not generate another

fers, WB H is passive (low), enabling the DATA and

interrupt until the device again requests service.

DATB demultiplexer inputs. As a result of the logical

state of stored address bits SA1 H and SA2 H, one Byte

When not requesting service, both Interrupt Acknowl-

0 and one Byte 1 write data strobe will go active,

edge (IAK) flip-flops remain cleared. The flip-flop Q

enabling writing into all 16 bits of the addressed device

outputs are both gated with IAK H, producing an

active BIAKO L signal which is passed to the next

registers, WB H goes active (high), enabling stored

(lower priority) device on the I/0 bus. The INIT L

address bit 0 (SAO H and SAOL) to assert only one data

signal, produced by a bus receiver and inverter, clears

input (DATA or DATB) on the 74155. Hence, only one

all Enable and IAK flip-flops, and presets (a don’t care

of the eight write strobes will go to the active state; an

condition) all INT ENB flip-flops. When requesting

8-bit transfer to the appropriate high or low byte in the

service, the IAK flip-flops inhibit passing BIAKO L to

addressed register is this completed.

the next lower priority device.

10.4

CAUTION

INTERRUPTLOGIC

IAK flip-flops must function as synchronizers.

The basic logic functions required in an interrupt cir-

cuit are shown in Figure 10-4. This is a dual interrupt

(Data setup has no guaranteed minimum time.)

circuit which will enable and control two interrupt

Type 7474 and 74574 are preferred.

request sources (A and B) supplied by the user. The
four flip-flops, ENABLE A and B, and INT REQ A

10.5

and B comprise bits of one or two control/status

A simple DMA request circuit is shown in Figure 10-5.

DMAINTERFACELOGIC

registers (CSR). The set/reset status of the Enable flip-

In addition to this circuit, bus address, word count,

flops is established by a programmed output transfer.

control/status registers,

EN A CLK H and EN B CLK H signals are the write

logic would normally be included. All registers would

data strobes shown in Figure 10-3; EN A DATA H and

be accessible via programmed I/O operations.

and burst transfer control

EN B DATA H would then be two of the received data
A DMA request is initiated by a device by producing an

bits (DEC 8641 “Rn”’ outputs). Similarly, INT REQ A

and B flip-flop outputs INT REQ A and INT REQ B

active REQ H signal. The RQST H signal must remain

would be read as bits in the CSR via the read data

high until bus mastership is no longer required. The

multiplexer in the device’s logic.

type DEC 8881 bus driver then asserts BDMR L.

Atypicalinterrupt sequence for ““device A’ is described

The processor arbitrates theTMrequest

below. An interrupt is enabled under program control

BDMGI L, setting the Claim flip-flop in the first re-

by setting the ENABLE A flip-flop. When the user’s

questing device along the BDMG daisy chain. The

device is ready for service, it produces an active RQST

state of the Claim flip-flop is sampled by two gates

A H signal, which is ANDed with ENABLE A. The

after the DMG delay. CLAIM (0) H is low (false) and it

asserting

AND gate output clocks the IAK ENB A flip-flop to

inhibits the DMGO EN H gate. Hence, when the Claim

the set state and IRQA L is produced. Note that if the

flip-flop isset, BDMGO Lis not passed to lower priority

user’s device terminates the RQST A H signal, the

devices. The active (high) CLAIM (1) H signal is gated

10-5

When not requesting DMA service, the device must

with DDMG H producing a low signal which enables
one of the three 7427 gate inputs. When BSYNCL and

pass BDMG signals to lower priority devices on the I/O
bus. The active (high) CLAIM (0) H signal is gated with
DDMG H producing an active DMGO EN H signal.
This signal enables the BDMGO L bus driver and

BRPLY L become negated, passive (low) SYNCR H
and RPLYR H signals are gated with CLAIM (1) H and
the 7427 output goes high. This transition clocks the
Master flip-flop to the set state producing the active

DMG H is gated onto the bus.

MASTER H signal, enabling BSACK L and negating

The actual DMG delay is determined by the RC circuit
shown on the figure, and should be 100 ns (min).
BINIT L initializes the circuit by clearing the Claim

BDMR L signals. MASTER H is used by the DMA
device to enable its bus cycle. BSACK L informs the
processor that the bus is in use. At the end of the bus
cycle, the device negates REQ H, clearing the Claim
and Master flip-flops. MASTER H and BSACK L sig-

and Master flip-flops.

nals then go passive.
REQ H

BOMR L

37
MASTER
L

RPLYR H

DEC
0%

BRPLY L

k SYNCR H

BSYNC L

o640

DDMG H

+5V
BOMGT L

3308

\
DEC

864

74574

ol 7427)

] o

7400

ELAIM (1) H

CLAIM

—» MASTER H

MASTER
F/F

ggg’“

BSACK L

DMG H

6800

CLR

REQ H

DEC

—Olgea0

7404

)

$360

DMG H

at |

§e

i
Latl

;408)__

DDMG H

IBZOpf

DMG DELAY
(SEE NOTE)

1800

BOMGO L

DMGO ENH

6800

L DDMG H

S |

NOTE:

The DMG Delay Circuit shown above
is preferred. However, the following

DMG Delay Circuit can be used:

DMG H —C';;;B\

1008
VVv

BINIT

INIT L ) 7408 )0

DDMG H

820pf

CP-1795

Figure 10-5

DMA Arbitration Logic
10-6

If dynamic MOS memory is

used in the system
(KD11-F processor and/or MSV11-B memory), a

DMA device is restricted to one bus cycle for each
BDMG signal from the processor. This must be done to

allow the processor to execute memory refresh transactions.

In systems which

include dynamic

MOS

memory and use more than one DMA device, the DMA

interface designer must ensure that sufficient time will
be allowed for the processor to execute memory refresh
transactions.

CAUTION
The Claim flip-flop must function as a synchronizer. (Data setup has no guaranteed minimum
time.) Types 7474 and 74574 are preferred.

10-7

CHAPTER11

SYSTEM CONFIGURATION AND INSTALLATION

11.1

MMVI11-A Memory 4K Address Selection

GENERAL

4K address select switches (Paragraph 8.2)

This chapter contains the basic considerations and re-

quirements for configuring and installing LSI-11 or
PDP-11/03 systems. The following paragraphs apply

to both LSI-11 systems and PDP-11/03 systems, except

MRVI11-A

PROM/ROM MemoryJumpers

Memory address (Paragraph9.2.3)
Reply signal (Paragraph 9.3)

where clearly stated otherwise.

512 by 4-bit or 256 by 4-bit PROMs (Paragraph

.11.2

9.2.2)

CONFIGURATION CHECKLIST

LSI-11 and PDP-11/03 systems comprise user-selected

MSVI1I-A IK by 16 Random Access Memory Address

module options asrequired for a particular application.

- Each module may require jumper alterations or switch

Jumpers (Paragraph 7.2)

settings to provide the correct addressing, operation,
MSVI11-B 4K by 16 Random Access Memory Jumpers

etc. for the user’s application. A module configuration
checklist for each module type is provided below. De-

Memory address (Paragraph 7.3.1)

tailed information for configuring the modules can be

Reply to refresh (Paragraph 7.3.2)

obtained by referring to the paragraphs listed in the
The following checklist is for LSI-11 system configurations. It includes items that are not contained on
particular modules but which must be checked to

checklist.
KD11 Processor

Jumpers

ensure that the system is properly installed.

Power-up mode (Paragraph 5.2.4)
Memory refresh enable (Paragraph 5.2.2)

Line time clock enable (Paragraph 5.2.3)

BDCOK, BPOK, BEVNT, and BHALT sig-

Resident memory 4K address selection (KD11-F

nals connected as required to H9270 back-

only) (Paragraph 5.2.5)

plane assembly (Paragraph 11.7.5).
Modules inserted in H9270 backplane slots

DLV11 Serial Line UnitJumpers

according to desired priority (Paragraph

Device address (Paragraph 6.2.2.2)

11.3).

Vector address (Paragraph 6.2.2.3)
Universal

asynchronous

receiver

Jumpers added to H9270 backplane when

transmitter

operation (Paragraph 6.2.2.4)

core

Baud rate selection (Paragraph 6.2.2.5)

between processor and 1/0 device modules

EIA interface (Paragraph 6.2.2.6)

(Paragraph 11.3.3).

20 mA current loop interface (Paragraph 6.2.2.7)

memory

(MMVI11-A)

Correct cabling selected

Framingerror halt (Paragraph 6.2.2.8)

for

I/0

located

device

modules (Paragraph 11.5).

DRVI11 Parallel Line Unit Jumpers and Pulse Width

Modules inserted in backplane slots with

Modification

components facing in the correct direction

(Paragraph 11.4).

Device address (Paragraph 6.3.2.2)
Vector address (Paragraph 6.3.2.3)
NEW DATA READY and

DATA

Correct power and ground inputs to H9270

TRANS-

backplane

MITTED pulse width modification (Paragraph

connector

11.7.3.and 11.7.4).

6.3.4.6)

11-1

block

(Paragraphs

a.
b.

daisy-chained signals when the processor module is installed in slots A1-D1. Hence, six options can be installed in the backplane. The PDP-11/03 is shipped
with the processor module installed in the backplane as
shown in the figure. Do not relocate the processor
module to another location; a separate non-bused

Voltage and current requirements met
Correct terminal block power connections made

Proper ground connection

Environmental

requirements

met

(Para-

(jumper) connection is provided on the backplane to
this location for proper RUN indicator operation.

graph 11.7.5).

NOTE

Device priority is established by the relative position of

Note that the daisy-chained BIAK and BDMG signals
always follow in increasing numbered option locations,
as shown in the figure. Do not configure the system
with unused option locations in the backplane between
the processor module and I/0 devices which require
either of the two daisy-chained signals; an unused
location will break the daisy-chain signal continuity,
and devices in higher numbered locations will not receive interruptor DMA grant signals. Unused locations
should occur only in the highest numbered option

the device interface module along the 1/0 bus in which

locations.

Special cooling

considerations

might be

re-

quired if more than one core or PROM module,
or a combination of core and PROM modules,

are implemented on one H9270 backplane assembly.
11.3

DEVICEPRIORITY

11.3.1

General

the devices are installed. The H9270 backplane is
structured to allow the user to configure device priority
by installing modules in appropriate positions. The

11.3.3

H9270 is an LSI-11 option which should be considered

The MMV 11-A position on the backplane should be

H9270 Backplane/MMV11-A Configuration

whenselecting LSI-11 system modules. The PDP-11/03

includes one factory-installed H9270 backplane.

carefully considered when configuring the system. The
MMV11-A’s physical size is four times greater than

11.3.2

Priority Selection Using the H9270 Backplane

two or four device (or option) locations on the back-

Figure 11-1 is a front view of the H9270 backplane,

plane, depending on where it is located on the back-

showing typical

plane. It is actually comprised of two 8.5 by 10 in.

other LSI-11 module options, and it will require either

module

locations.

The

processor

modules which are mated in a single assembly. How-

module should be installed in backplane slots A1-D1.

ever, only one module has fingers which plug into the
The LSI-11 bus structure includes two daisy-chained

backplane. Hence, if the MMV11-A is installed in

signals:

and

backplane row 4, the MMV11-A module not having

BDMGO L/BDMGI L (for DMA grant). These signals

backplane fingers will be located below the backplane

BIAKO L/BIAKI L (for interrupts)

normally propagate through option modules until they

(where “‘row 5’’ should be located) and rows 2 and 3 will

reach the requesting device. Option 1, as shown in

be available for other options. Thus, row 4 is the

Figure 11-1, is the first device location to receive the

recommended location for the MMV11-A.

VIEW FROM

MODULE SIDE OF BACKPLANE
A

PROCESSOR

| «— PREFERRED LOCATION FOR

KD11-F

OPTION

CONNECTOR
BLOCK

OPTION

OPTION 6

OPTION

OPTION 3

OPTION 4

OR KDi1-J

PROCESSOR MODULE.

PREFERRED LOCATION FOR
MMV1ii-A CORE MEMORY.
CP—-1759

Figure11-1

TypicalConfiguration LSI-11 Backplane
— Processor and Option Locations

If the MMV11-A is installed in row 2, as shown in

Figure 11-2,

NOTE
These jumpers are required only if the MMV11-A

row 3 will also be occupied by the

MMV11-A; however, the portion of the assembly in

is installed in row 2.

row 3 does not have backplane fingers. If any device
modules are to be installed in row 4, it is necessary to
install jumpers on the backplane in order to complete

11.4

MODULE INSERTION AND REMOVAL

Modules must be installed or removed only when dc

the DMA and interrupt grant signal chain. These
jumpers (two required) should be wire wrapped between the backplane pins listed below:

power is removed from the backplane. The PDP-11/03
contains a control/indicator panel on the front of the
power supply; the DC ON/OFF

switch allows the user

to turn off dc power for safe module insertion and

H9270 Backplane/MMV11-A Jumpers

removal.

From

Signal

AOIN2

A04M2

BIAKI/OL

A01S52

AO4R2

BDMGI/OL

Modules must be installed in the backplane with components facing row 1, as shown in Figure 11-3.

PROCESSOR

2
MMV11-A

CORE

ROW

DEVICE

J
MODULE SIDE
NOTE:
This is not a preferred configuration, for the preferred
configuration, refer to figure 11 — 1
CP-1760

Figure11-2

H9270 Backplane/MMV11-A Core

CONNECTOR
BLOCK

COMPONENT SIDE

@@ (] (D1 @] @@@QJ/MODULE

MODULE SICE
CP1761

Figure11-3

Module Installation in the H9270 Backplane

11-3

CAUTION

the front panel exposes the LSI modules and cables.
This enables replacement or installation of a module

The LSI-11 modules and the backplane assembly

from the front of the PDP-11/03. The 11/03 power

mounting blocks may be damages if the modules

supply is located

are plugged in backward.

PDP-11/03 when viewed from the front. The power
supply

DC power must be removed from the backplane

three

right-hand

front

panel

side

of the

switches

and

indicators which are accessible through a cutout in the

during module insertion or removal.
11.5

contains

on the

front panel. Therefore, when the front panel is removed, the lights and switches are still attached and

1/0 CABLING

functional.

Recommended I/0 cable options for use with the
DLV11 serial line unit and DRV11 parallel line unit
are listed below:

20 mA Current Loop
EIA Interface

()

Cable*

BCOSM-X
BC05C-X

DRYV11 Parallel Line Unit

—

DLV11 Serial Line Unit

Cable*

]

L]
I-NHIT'

Any combination of one input and one output cable

11-3303

may be selected from the

fe—————— 13.50" ——{

two types listed:

Flat Cable

BCO8R-X

Twisted Pair

BC11K-25

11.6

11.6.1

POWER SUPPLY
AR

AIR

PDP-11 / 03 INSTALLATION PROCEDURE

Paci(aging and Mounting

The PDP-11/03 is packaged as shown in Figure 11-4. It
is designed with a removable front panel. Removing

FRONT

PROCESSOR,
MEMORY AND

DEVICES

*The -X in the cable number denotes length in feet, as follows: -1, -6,

11-3304

-10, -20, -25. For example, a 10-ft EIA interface cable would be ordered as BC05C-10.

Figure11-4

H9270 Backplane

Table11-1

PDP-11/03 Input Power Electrical Specifications

Parameter
Input Power

Model

Specifications

PDP-11/03-AA or | 100—127 Vac, 114 Vac nominal; 50 + 1
PDP-11/03-BA

|Hz or 60 £ 1 Hz, single phase

PDP-11/03-AB or | 200—254 Vac, 230 Vacnominal; 50 *+ 1
PDP-11/03-BB
Hz or 60 &£ 1 Hz, single phase

Input Power

All

400 W max at full load;
190 W typical

Temporary Line | All
Dips Allowed

100% of nominal voltage:
9t020 ms
40% of nominal voltage:
20to 96 ms
28
% of nominal voltage:

96 to S00 ms

11-4

The H780 power supply provides the required dc power

The PDP-11/03 is designed to mount in a standard 19
in. cabinet (Figure 11-5). A standard 19 in. cabinet has
two rows of mounting holes in the front, spaced
18-5/16 apart. The holes are located 1/2 in. or 5/8 in.
apart. Standard front panel increments are 1-3/4 in.
11.6.2

for the backplane in the PDP-11/03 enclosure. Typical
dc power requirements will range from 33 to 120 W
(max). In addition, the power supply generates the
necessary BPOK H and BDCOK H power supply
status signals, displays the RUN and DC status, and
contains the ENABLE/HALT, DC ON/OFF, and
LTC ON/OFF control switches.

Power Requirements

Input (primary) power requirements are listed in Table
11-1.

Before attempting to operate the system, ensure that
the system is configured as previously described in this
chapter, and that environmental requirements are

An appropriate power cable and plug is supplied with
all PDP-11/03 models. Note that a ground wire (and
ground pin on the plug) must be connected to the
normal service ground to ensure safe operation. Do not
cut or remove the ground pin.
[4

11.6.3

18-5/16"

[4
~

-+ ~

11.7.1

detail.

1-3297

—-1-!#3/8" TYP

18.31"

J — 19" TYP
&

FRONT OF BOX(PANEL REMOVED)

T ine

General

When installing the LSI-11 system, the user must
mount the H9270 backplane, provide dc operating
power, ground, and externally generated bus signals,
and observe system environmental requirements. The
following paragraphs describe the above items in

-3

OO0

010

O
(&,

LSI-11 SYSTEM INSTALLATION

11.7

3-12" l————

temperature range.

—lr T

Environmental Requirements

The PDP-11/03 will operate at temperatures of 41° to
104° F (5° to 40° C) with a relative humidity of 10 to 90
percent (no condensation), with adequate air flow
across the modules. The fans in the H780 power supply
will provide adequate air flow within the specified

—_—

1-3/4"

FRONT PANEL

Ol0

47011 A STANDARD

1/4"

010

eTS

OO0

0,0

FRONT VIEW

met.

& 14" TYP

19"

11.7.2

Mounting the H9270 Backplane

The H9270 backplane (Figure 11-6) is designed to
accept the KD11-F or KD11-J microcomputer and up
to six I/O interface or memory modules. Mounting of
the H9270 backplane can be accomplished in any one
of three planes, as shown in Figures 11-7, 11-8, and
11-9.

11-330%

jo]

11.7.3

DCPower Connections

11.7.3.1 Voltage and Current Requirements — A
power supply for a single backplane LSI-11 system
should have the following capacity:

FRONT

r—v———— 13.50"

1.5"

+5V + 2% load; 0—18 A static/dynamic

+12V * 2% load; 0—2.5 A'static/dynamic

1-3306

Figure11-5

+Sripple: less than 1% of nominal voltage
+12 ripple: less than 150 mV pp (frequency
SkHz)

PDP-11/03 Cabinet Mounting

11-5

MOUNTING
6-32 THD
HOLES x 0.25"
DEEP

{4 PLACES)

-1
—-10-32
THD x 0.05 LONG

THREADED STUD

11-3299
i

Figure11-6

H9270 Backplane Mounting

0.187 DIA. HOLES
4 PLACES

\
:
.-

]

O_____ —

’4__y

143;5“

~~-o‘sr'}‘—————————-7_-29"

—{

11.15

;

{1 1 01 P

—y

‘

T ‘

f 5

11.00"

—

2-3|°"

0.74"

9.04"
1-3300

Figure11-7
.

H9270 Side Mounting
.

10-32 THDx 0.5" LONG
o;n’-:-/
THREADED STUD(4 PLACES)
CONNS%%E

|
©

”

o35 oees

6-32 THD HOLE

connector T
_

0.08"
&

1
3

263"

8lock

TMY

0.3

11-3301

H9270 Rear Mounting

11-6

Figure 11-9

VIEW FROM REAR OF BACKPLANE

Figure11-8

295"

—

5 950"

250

H
11-3302

H9270 Top And Bottom Mounting

11.7.3.2

H9270 Backplane Power Connections —

For battery backup, remove the jumper be-

Perform the following steps to connect power to the

tween +35V and +5B and connect the ap-

H9270 backplane (Figure 11-10):

plicable wires to the H9270 connector block
per Table 11-3.

Select wire size. (14 gauge is recommended.)

Consider load current and distance between

the power supply and backplane.
2.

For

standard

system,

connect

the

applicable wires to the H9270 connector

|+12v

|[+5Vv

|+5vB

|GND

|-12v

It is recommended that the H9270 frame/

casting be electrically connected to system/
power supply ground.

block per Table 11-2.

Connect the ground terminals at the power
sources.

SIDE 2

/
CcP-1762

Figure 11-10

H9270 Backplane Terminal Block

Table11-2

Table11-3

H9270 Backplane Standard Power Connections

H9270 Backplane Battery Backup Power Connections

Power Source

H9270 Connector Block

Power Source

H9270 Connector Block

(From)

(To)

(From)

(To)

+12V

Factory

+5V (System Power)

+S5V }

Connected

+5B (Battery Backup) | +58 § Connection

+12V

+5V

+5V }

+S5SB
GND

GND {

Factory

GND

Connected

-12V

(This voltage is not
required. The connection is available
for

custom

faces.)

inter-

Remove Fact()ry

GND

Factory

GND

Connected

-12V

(This voltage is not

required. The connection is available
for

custom

faces.)

inter-

11.7.4

H9270 Backplane Ground Connection

11.7.6

Externally Generated Bus Signals

Connect the H9270 backplane ground wire to system
(or frame) ground in which the H9270 is installed. The

11.7.6.1

ground terminal is located as shown in Figure 11-10.

include BDCOK

General— Externally generated bus signals

BEVNTL
11.7.5

Environmental Requirements

and

BPOK H

power status,

(line time clock) (if required), and BHALT
L

(if desired). The signals are applied to the backplane

AlILSI-11 modules will operate at temperatures of 41°

via a connector and an optional mating connector as

to 122° F (5° to S0° C) with a relative humidity of 10 to

shown in Figure 11-13. The signals must conform to

90 percent (no condensation), with adequate air flow

LSI-11 bus configuration specifications described in

across the modules. When operating at the maximum

paragraphs 3.12, 3.13, and 10.2. Connections made to

temperature (122° F or S0° C), air flow must maintain

the backplane via the ribbon cable shown in Figure

the inlet to outlet air temperature rise to 12.5° F (7° C)

11-13 must not exceed 12 inches in length. Each signal is

maximum. Air flow should be directed across the

discussed in the following paragraphs.

modules as shown in Figure 11-12.

CONNECTOR

OUATIPET ;

CP-1764

Figure 11-12

RIBBON

H9270 Backplane Air Flow

CABLE
MATING CONNECTOR

DEC PART

No.12-11206-02

(3M PART No0.3473-3)
ALIGNMENT

posmw\

BEVNT/ \\‘\BHALT

GND

BPOK

SRUN

H9270 PRINTED
CIRCUIT BOARD

SIDE 2
Figure11-13

H9270Backplane Printed Circuit Board

/4
CP-1765

11.7.6.2 BDCOK H and BPOK H — The processor
monitors power supply status and responds, as appropriate, by the BDCOK H and BPOK H signals. These

Generation of BPOK H and BDCOK H signals can be
provided automatically via user-supplied logic, or
manual operation can be selected, as follows:

signals are defined below:

Automatic: Connect BPOK H and BDCOK H

BPOK H Assertion

8.0 ms of dc power reserve and BDCOK has been
asserted for 70 ms min; 3.0 ms minimum assertion of BPOK required.

BPOK H Negation

4.0 ms of dc power reserve, but power is failing;
1.0us minimum negation time for BPOK.

signals from the power supply logic to H9270
backplane as shown in Figure 11-13.

Manual: Connect ground to a momentary ON/
OFF switch (BDCOK switch), as shown in Figure
11-16. Connect the BDCOK switch output to the
BDCOK H input on the H9270 backplane via a

switch bounce eliminator. To initialize the processor after power is applied, the BDCOK switch

BDCOK H Assertion

3.0 ms of dc power has been applied; 1.0us mini-

must be momentarily depressed (off), then re-

mum assertion time for BDCOK.

leased (on).

BDCOK H Negation

5.0us of dc power reserve but no sooner than 3.0
ms after BPOK negation; 1.0 us minimum negation time for BDCOK.

During the power-up sequence, after dc power has
been applied (Figure 11-14), the processor asserts
BINIT L in response to a passive (low) power supplygenerated BDCOK H signal. When BDCOK H goes

" active (high), the processor terminates BINIT L after
approximately 12us, and waits for assertion (high) of
BPOK; then the user-selected power-up mode is executed. Similarly, if power fails (Figure 11-15), the
power supply-generated BPOK H signal goes passive
- (low) and causes the processor to push the PC and PS
onto the stack and enter a power fail routine via vector
~ location 24 (power fail trap location). The processor
will execute the power fail routine until either BDCOK
H goes passive (low), indicating the dc operating power
may not sustain processor operation, or BPOK H
returns to the active state. BINIT L will be asserted if
BDCOK H goes passive.

AC INPUT f

If the manual method of applying BDCOK H is
selected, contents of semiconductor read/write
memory may be lost when BDCOK switch is depressed.

NOTE

It is not necessary to negate the BPOK H signal
when manually initializing the processor. BPOK
H may be left unconnected.

11.7.6.3 BEVNT L Signal — The BEVNT L signal
input to the H9270 backplane (Figure 11-13) is the external event interrupt. Asserting the BEVNT L signal
initiates the LTC (line time clock) interrupt on the
processor. The processor will trap through location

100 if PS bit 7 = 0. A typical circuit for generating

BEVNT L is shown in Figure 11-13.

AC INPUT

|
|

—'—

BPOK H

BPOK

]
1

:
BDCOK H
|
:
._|___/I !

|
!

| |

BDCOK H

20—

by
|

DC POWER

}\
I
!
|

le—
|

!
!

—»l >ams je—

DC POWER

220ms --D-l I-i-?:’)ms—-lfl——?—?Oms _—'I

—

;35;18

NOTES
A switch bounce eliminator must be used with
the manual BDCOK switch, as shown.

f—

cP-1767

CP-1766

Figure11-14

Power-Up Sequence

Figure 11-15

Power-Down Sequence

SWITCH BOUNCE
ELIMINATOR

60cOK

BDCOKON L

MOMENTARY
SWITCH

I
=

|
|

O 7404

GEINNNS

—1

BDCOK OFF L

888!

i
|

Lol 7404

[ °

]

00000

BACKPLANE

PRINTED

SIDE

CIRCUIT BOARD

NOTE
:

BDCOKH

SIGNAL (ASSERTED HIGH)

LOW: 1.3V

MAX

HIGH: 1.7V

MIN
cP-1768

Figure11-16

BDCOK H Signal Routing Diagram

11.8.2

PDP-11/03 Power-On

Proceed as follows:
FREQ = AC PWR
FREQ.

INPUT
FREQ.

as previously described.

SOURCE -—E

8881

BEVNTL

Figure 11-17

BEVNTL

Place the DC ON/OFF switch in the down
position (DC OFF).

CP~2040

11.7.6.4

Ensurethatthesystemis properly configured

Signal

Place the AC ON/OFF switch on the rear of
H780 power supply in the ON position.

BHALT L Signal — Manual control of the

Placethe HALT/ENABLE switchin the desired power-up position.

Halt mode can be obtained by connecting a BHALT L
signal line to the H9270 backplane printed circuit

board as shown in Figure 11-13. The BHALT L signal
level should meet bus specifications described in Para-

NOTE

graph 3.12.

The dc power can be applied with the HALT/

When in the Halt mode, user program execution is not

processor power-up mode is affected by this

ENABLE switch is either position. However,
performed and the processor executes ODT console

switch and jumper-selected power-up modes, as

microcode.

listed in Table 11-4.

However,

the

processor will

execute

memory refresh in a normal manner and respond to

DMA requests, even when BHALT is asserted; all
Place the LTC ON/OFF switch in the OFF

device and LTC interrupt requests are ignored.

position.
11.8

11.8.1

SYSTEM OPERATION

Place the DC ON/OFF

switch in the up (DC

ON) position. The console device should

General

respond with a printout

The procedures included in the following paragraphs

(or

display)

shown in Table 11-4.

describe power turn-on and operational checks for
LSI-11 and PDP-11/03 systems. Refer to the LSI-11,

Proceed with initial power-on checkout by

PDP-11/03 Processor Handbook for detailed opera-

entering and executing the program listed in

tion, including console ODT and program execution.

Paragraph 11.8.4.

11-10

Table11-4

Console Power-Up Printout (or Display)

Conditions

Mode 0 (Jumpers
W5, W6 removed)

BHALTL
(unasserted),
Dynamic RAM
Memory

Mode 1 (Jumper W6

Mode 2 (Jumper W6

removed, W5 installed)| installed, W35 removed)

Processor will execute program.
Terminal will print out |Processor will execute
Ifthere is no data in memory
arandom 6-digit
program at location
terminal will print out “000002.”” | number, whichisthe
|173000.
(See Note 2.)
contents of the
(See Note 2.)

Mode 3 (Jumper W5
W6 installed)
[No printout
at terminal.

program counter.

BHALTL
(unasserted), Core
Memory

Processor will execute program
in core.
(See Note 2.)

Terminal will print out |Processor will execute
arandom 6-digit
program at location
number, whichisthe
[173000.
contents of the

|No printout
at terminal.

(See Note 2.)

IT-11

program counter.

BHALTL

Terminal will print out contents

Terminal will print out

|Terminal will print out

|No printout

(asserted),
Dynamic RAM
Memory

of memory location 024
(normally “0000007’).

arandom 6-digit
number, which is the
contents of the

“173000.”

atterminal.

program counter.

BHALTL

Terminal will print out

|Terminal will printout

|No printout

(asserted),
Core Memory

contents of memory location
024 (normally “000 000”’).

arandom 6-digit
number, which is the

“173000.”

at terminal.

contents of the
program counter.

NOTES
1.

If mode 3 is selected, and microaddress

(3000—3777) is not implemented, the

processor will trap to memory location
010. Trapping to 010 will be treated as a
reserved instruction trap.
2.

Whenever the PDP-11/03 is executing a
program, the RUN indicator should be
lit. If no program is provided or if a
HALT instruction is executed, the RUN
indicator will be extinguished.

LSI-11 Power-On

This program outputs all ASCII characters and may

Enter and execute the program via the console device
as directed below:

Remove all modules from the backplane.

It is recommended that a single switch be

A
e

Ensure that there is no dc power applied to
the H9270 backplane.

used to apply +5V and +12 V to the
H9270 backplane. There is no required voltage application sequence.
Turnpower-on.
At the H9270 backplane,

Row 1, Slot A, Pin A2: +5V
Row 1, Slot A, PinD2: +12V

Enter instruction (octal code).
Press LINE FEED.

Repeat above steps until all instructions

Press RETURN.

Enter starting address.
Press G.

Row 1, Slot
A, PinV1: +5V
CAUTION

Press the BREAK key on the console device
to stop program. If the console device does

Do not plug in modules with power applied to

not include the BREAK key,

H9270 backplane.

HALT switch

(PDP-11/03

press the

panel

or the

manual HALT switch described in Para-

Turn power off.

Ensurethatthe system is properly configured

graph 11.7.6.4).

A sample console printout of the above program is

and installed as previously described.

shown in Figure 11-18.

Turn on system power. Observe that the con-

sole device responds as described in Table

11.9

11-4.
9.

Press slash (/).

have been entered.

check for the

following voltages:

Enter Starting address.

include control codes for specific devices.

®°

11.8.3

Proceed as follows:

PAPER TAPE SYSTEM OPERATION

Proceed with initial power-on checkout by

11.9.1

entering and executing the program listed in

Paper tape systems include no mass storage devices

General

and programs must be read into system memory prior

Paragraph 11.8.4.

to system operation. Programs are read from punched

11.8.4

ASCII Character Console Printout Program

paper tapes using either an optional low-speed reader,

The following is a program that can be used to printout

such as the LT-33 Teletypewriter, or a high-speed

ASCII characters. The successful completion of this

reader

program can be used as a guide in determining the

operations is:

(user-supplied).

The

normal

sequence

correct operation of the following:
KD11-F or -J Processor

DLV11 Serial Line Unit

Load the Absolute Loader

Load program tapes

[Execute the program

LSI-11 data transfer and data control bus signals

Power input connections for +12V and +5V
This program does not explicitly check the following
bus signals.
BDMRL

BHALTL

BPOK H

BIRQL

BDMGI/OL

BDCOK H

BEVNTL

BIAKI/OL

11.9.2

References

Various paper tape software options are available for
PDP-11 users. Refer to the following publication for
program descriptions and operating instructions:

PDP-11

BSACKL

Paper

Tape Software Programming

Handbook (DEC-11-XPTSA-B-D).
The above manual can be ordered as directed at the

rear of this manual.

11-12

Address/Instruction
Starting Address

001000/105737

Mnemonic
TSTB @ #177564

001002/177564
001004/100375.

BPL. 4

001006/110037

MOVBRO, @ #177566

001010/177566

001012/005200

INCRO

001014/000137

JMP @ #1000

001016/001000

1003G

!"#3%2&° () %x+,-4/0123456789:3<=>?20ABCDEFGHIJKLMNOPQRSE

I"#SR& " (I%+,-0/0123456789:3<=>2@ABCDEFGHIJKLMNOPQRSTUVWXYZL\]1t~@ABCDEFE

1'"#3R8() *+,-./23123456789:3<=>?8ABCDEFGHIJKLMNOPQRSTUVWXYZ[\1t~@ABCDEFS

1"#S2& () %+,-4/012345678923<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ(\]1t~@ABCDEFS
1"#82&'()%+,-4./012345678913<=>?20ABCDEFGHIJKLMNOPQRSTUVWXYZ(\]t~@ABCLEFE

Figure11-18

11.9.3

Sample Console Printout

Loading the Absolute Loader

The Absolute Loader program tape is loaded using the

Bootstrap Loader which is resident in the processor’s

Enable the tape reader as follows:
.

LT33 Teletypewriter

microcode. The Bootstrap Loader is executed via the
Halt mode and console ODT commands as directed

below:

LINE position.

b.
1.

Enterthe Halt mode
PDP-11/03 — Place the HALT/ENABLE

Place the START/STOP/FREE switch
in the START position.

High-Speed Reader — Turn the reader on

switch in the HALT position. The console

and place “‘on line”’, as appropriate for the

device prints the @ prompt character.

type of reader being used.

LSI-11 — Since LSI-11 systems are com-

pletely user-configured, the HALT mode

Enter the reader’s CSR address by typing
thevalueon the console device. For example,

can be entered via one or more of the follow-

if the console device includes a paper tape

ing means:
a.

Enable the low-speed reader.by p}acmg
the LINE/OFF/LOCAL switch in the

i
)
Momentarily place the user-supplied

reader (such as the L'T33 low-speed reader),
type:

HALT/ENABLE switch in the HALT

@ 177560

position; return the switch to the ENABLE position.
b.

Press the BREAK key on the console

NOTE

device (FEH jumper must be installed

In the above example, and all examples

in the console SLU interface module).

which follow, characters

printed by

ODT are shown underlined. Charac-

Initialize the processor by momentarily

ters entered by the operator are shown

negating BDCOK H (processor module

not underlined.

jumper WS must be installed and W6
removed).

Place the Absolute Loader tape (DEC-11-

The value 177560. is the console device's

UABLB-A-PO) in the paper tape reader.

CSR.

Note that a long portion of the tape is

Load the Absolute Loader tape by typing L

punched with the octal value 351 (Channels

immediately after the reader device’s CSR.

8,7, 6, 4, and 1 are punched); position the

The tape will automatically be read followed

tape so that any of those characters is lo-

by printing the Absolute Loader’s starting

cated over the reader head.

11-13

address on a new line and the @ character
on the following line. The complete command is shown below:

Readtheprogramtape:

If processor halted at Absolute Loader
starting

address (Paragraph 11.9.3,
Step 5), type P (Proceed command).

@ 177560L

037500

The starting address of the absolute loader
depends upon the size of the system read/
write memory (in any increments). Memory
sizing is automatic and the Absolute loader
will be properly located for the particular
system in which it is loaded. The above exampleis for a system containing 8K memory.

Loadadditional programs by typing the
starting address of the loader program
(previously printed out as described in
Paragraph 11.9.3, Step S5), followed by
the G command, as follows:
@037500G
NOTE

ble for an 8K memory system.

A listing of typical printouts for 4K memory

Use an appropriate starting

increments is provided below:

MEMORY SIZE
4K
8K

address as printed out on the
console device after loading

PRINTOUT

the Absolute Loader.

017500

entered as: @ 37500G.

057500

After loading the program tape, the Ab-

e
16K
20K

24K
28K

solute Loader program halts. The Halt

077500

PC+2 address is printed on a new line,

followed by the @

117500

loading sequence is shown below:

137500

@ 177560L

037500

157500

037712

Ifa proper printout of the absolute loader’s starting address is not obtained, repeat Step S.
Loading Program Tapes

11.9.4.1 General — Program tapes are loaded into
memory by the Absolute Loader program. The Absolute Loader can be used for normal loading and relocated loading operations. Normal loading causes the
program being loaded to load at an absolute address
punched in the program tape. Relocated loading
allows loading certain program tapes into any specific
area in memory, or to continue loading from where the
loader left off on a previous load operation.
11.9.4.2

character on the

following line. The complete program

11.9.4

Leading 0’s can be ignored.
For example, 037500 can be

037500

@
12K

The above example is applica-

First Prog. Tape Loaded

11.9.4.3 Relocated Loading Procedure — Relocated
loading can be specified by setting the software switch
register (in the Absolute Loader program) to a
particular value. This value is normally 0, and normal
program loading is selected by default. Note that the

software switch register’s address is dependent upon
the Absolute Loader starting address, as previously
printed. Use the first three octal digits of the starting
address as the most significant three digits and 516 as
the three least significant digits. Hence, 037516 is the
software switch register location for the Absolute
Loader when loaded in an 8K system.

To continue loading from a previous load operation,
type:

Normal Loading Procedure —

Place the program tape in the reader with
blank (leader) tape over the read head.

Enable the tape reader as described in Paragraph 11.9.3, Step 3.
11-14

@ 0375167000000 1 CRLF
@
NOTE

The above example is for an 8K memory system.

This type of relocated loading is particularly useful for
large programs which are contained on more than one
tape. To select relocated loading which uses an address
(bias) contained in the software switch register, type:

HALT/ENABLE switch in the HALT position. Enter

the starting address (or a desired address for the first
instruction to be executed) as described for normal
program execution.

@037516/ 000000 nnnnnn CRLF

is printed on the console device as shown in the following example:

NOTES

The above example is for an 8K memory sys-

@ 200G CRLF

tem.

000200 CRLE
@

Select arelocation value nnnnnn as specified
in the PDP-11 Paper Tape Software User's

Successive instruction executions will occur each time

Handbook. Observe that the least significant

the Proceed (P) command is entered via the console

“n” value entered must be an odd number;
this sets the software switch register bit 0 to a
logical 1, selecting the relocated loading

device.

An example of single word instruction execution using

mode.

the P command is shown below:

The program being loaded must be in a Position Independent Code (PIC) format to allow

@ 200G

relocation.

000200

@P
000202

11.9.4.4 Self Starting Programs — Some programs
are self starting (described in the Paper Tape Software
Programming Handbook), and can automatically
proceed execution immediately after loading. When
this is desired, the processor Run mode must be
enabled.

Place

the

HALT/ENABLE

system)

switch in the ENABLE position. Load the program

tape as previously described. Instead of the Absolute
Loader program halting after loading the program

program

- program’s

control

starting

transfers

address,

and

the

loaded

processor

proceeds with normal program execution.
11.9.5

Once a program has been correctly loaded, the Run
mode can be enabled and program execution started.

Place the HALT/ENABLE switch (PDP-11/03 panel,
user-supplied LSI-11

000204
@P

000206

switch) in

Note that after executing each instruction, the processor halts and prints the address of the next instruction.
Thus, Branch, Jump, and JSR instructions will alter
the PC as required in normal program execution,

allowing

the

operator

time

observe

program

operation.

NOTE

Program Starting and Execution

or equivalent

(PDP-11/03

panel, or equivalent user-supplied LSI-11

tape,

G command causes the

PC (R7) pointing to the first instruction. This address

@
1.

The

processor to initialize the system and then Halt with the

the

ENABLE position. Start normal program execution as
follows:

Avoid single instruction execution of programs
using interrupts. Those interrupts cannot be

serviced by the processor when in the Halt mode
because the Halt mode service has higher priority

than device interrupts.
11.10

RT-11SYSTEM OPERATION

@200G
11.10.1

The 200 in the above example is a typical starting

RT-11

General
is an optional high-performance Operating

address. Each program listing specifies the correct

System that combines PDP-11 hardware with user-

starting address. G is the Go command, and program

oriented

execution will immediately commence, starting at the

monitors are provided: The Single Job monitor (RT-11

specified location.

SJ) and Forward/Background monitor (RT-11 FB).

Single instruction execution, when desired, is obtained

device, the RXV11 Floppy Disk, and 8K read/write

by operating the processor in the Halt mode. Place the

memory.

software.

Two

RT-11

Operating

System

Minimum hardware requirements include a console

11-15

RXV11 hardware includes the RX01 single or dual

11.10.3.2

floppy disk drive,

and

or REV11-C — The REV11-A or REV11-C im-

BCOSL-135 interface cable. Models are available for

plements the RXV11 bootstrap (and other bootstrap
programs) in four pre-programmed ROM chips. When

M7946 interface module,

115 V,60 Hz and 230 V, 50 Hz operation.

system power is applied, and LSI-11 processor Mode 2
power-up sequence is configured on the processor
module, the system responds with a dollar sign ($) on a

RT-11 software is described in four publications:

RT-11

System

Reference Manual

(DEC-11-

new line. The operator then responds by typing the

ORUGA-C-DN2)

device to be bootstrapped. DX (or DXO0) is disk drive 0;
DX1

RT-11 System Generation Manual (DEC-11-

through booting DXO0 is shown below:

Software

Support Manual

(DEC-11-

Message

(DEC-11-

$DX

ORPGA-B-DN1)
RT-11

System

is the second drive in dual drive RXV11 systems.

A normal sequence of operations from power up

ORGMA-A-D)
RT-11

Booting The System Using The REV11-A

RT-11S]
Manual

V02C-XX

ORMEA-A-D).

Afterexecuting the DX0bootstrap, the system responds
by displaying the RT-11 monitor in use (RT-11SJ or

Refer to those documents for RT-11 system software

operation. Manuals can be ordered as directed at the

RT-11FB)

rear of this manual. The remainder of this discussion

(V02C-XX); the version is changed as RT-11 software

involves getting the PDP-11/03 or LSI-11

system

changes are implemented. Finally, a dot is displayed

running and responding to RT-11 Keyboard Monitor

on the next line, indicating that the RT-11 Keyboard

and

the

particular

version

use

Monitor is ready to accept a command. The system is

commands.

correctly booted and RT-11 programs can be executed
11.10.2

Using the RX01

as desired.

The RXO01 contains no operator controls or indicators

other than the load door(s) on the front panel. The left

11.10.3.3 Booting The System Via The Console Device — When the REV11-A or REV11-C option is not
included in the system, the operator must enter a bootstrap program via the console device. Place the proces-

drive on dual drive models is named DXO0 and the right
drive is DX1. Load the RT-11 diskette in the left (or
only) drive: this drive (DXO0) is called the SYStem

sor in the Halt mode and proceed as shown below; observe that underlined characters are printed by the
processor and non-underlined characters are entered

devicein RT-11 software.

NOTE

RT-11 can be bootstrapped and run on DX1 if

by the operator:

DXO0 is inoperative.

@1000/000000 12702 {LF)

001002/000000 1002n7 {LF>*
001004/000000 12701 {LF>

Additional details for the RX01 drive are included in

001006/000000 177170 {LF

the RX8/RX11 Floppy Disk System Maintenance

001010/000000 130211 (LF)

Manual (EK-RX01-MM-PRE2). That manual covers

001012/000000 1776 (LF
001014/000000 112703 {LF)

hardware used with PDP8 and other PDP-11 systems.

001016/000000 7 (LF>

However, the RX11/RX01 interface is identical to the

001020/000000 10100 LF)
001022/000000 10220 {LF)

RXV11/RX01 interface, and the RX11 and RXV11

001024/000000 402 (LF)

are software compatible.

001026/000000 12710 {LF)

001030/000000 1 (LB
001032/000000 6203 {LF)

11.10.3
11.10.3.1

RXV11 Bootstrap

001034/000000 103402 LF)
001036/000000 112711 (LF}
001040/000000 111023 (LF

General — The RXV11 bootstrap loader

001042/000000 30211 {LF)

001044/000000 1776 (LF)

program loads the RT-11 monitor from disk into sys-

001046/000000 100756 (LF

tem memory. No RT-11 operation can occur until the

001050/000000 103766 LF)
*n=4 for Unit O

monitor is contained in system memory. Bootstrapping

n=6 for Unit 1

(“booting”’) the system can be accomplished via a

(LF)=Line Feed

(CR=Carriage Return

hardware-implemented bootstrap in the REV11-A or

001052/000000 105711 (LF

001054/000000 100771 {LF)
001056/000000 5000 (LF

001060/000000 22710 {LF)
001062/000000 240 (LF

REV11-Coption, or it can be entered and executed via

001064/000000 1347 (LF
001066/000000 122702 {LF)

the console device.

001070/000000 247 (LF>
001072/000000 5500 (LF>

001074/000000 5007 (CR>

11-16

The bootstrap program can be started at location 1000.
Enable the Run mode by placing the HALT/ENABLE

switch (on the PDP-11/03 panel, or an equivalent
LSI-11 switch) in the ENABLE position. Start the
program using the Go command as follows:

CAUTION
1. A temporary loss of power will abort RT-11
operation and the LSI-11 processor will powerup through the selected mode. RT-11 must be

restarted. If the REV11-A or REV11-C option

is used, the console device will display $ and
the system waits for the operator to specify the

@ 1000G

After a few seconds the RT-11 monitor will be loaded in
system memory. The monitor will identify itself on the
console device by typing a message, such as: RT-11S]
V02X-XX. This printout is followed by the Keyboard

Monitor prompt character (.) printed on the next line.

11.10.4 Using the RT-11
Requests for the desired RT-11 modules are always
entered from the Keyboard Monitor. When executing
a system program, control is normally returned to the
Keyboard Monitor. The Keyboard Monitor can be
entered at any time by simultaneously typing CTRL C
keys.

11-17

desired bootstrap (DX). If the REV11-A or
REV11-Cis not used, enter the bootstrap program and start at location 1000.
. Halting the processor will cause the processor
to abort RT-11 operation. When the processor
halts it prints the address (PC) on the console
device, followed by the prompt character @ .

RT-11 operation can continue by typing P. If
desired, the system can be rebooted as previously described.

CHAPTER12
PERIPHERALS

This chapter contains a brief listing of peripherals

ODT Command

RT02-A Keys

available for use in PDP-11/03 and LSI-11 1/0 applications. All peripherals listed are serial line devices

SEND

which interface via the

DLV 11 Serial Line Unit inter-

SHIFT and CLEAR

face module. Refer to Table 12-1 for peripheral types,

SHIFT and +

models, brief specifications, and required interface

SHIFT and @

options (DLV11 and either the BCOSM 20 mA current

SHIFT and GO

loop interface cable or the BCOSC EIA interface cable).

SHIFT and ERROR

Contact your local Digital Equipment Corporation

Sales Office for detailed information on any of the

The console device can either be directly interfaced to

peripherals listed.

the DLV11 or it can be operated in a remote location

Typical applications are shown in Figures 12-1 through

telephone lines. However, only the LA36, LT33, and

and interfaced via data sets or acoustic couplers and

12-3. Note that peripherals listed other than the RT01

VTS0 are capable of remotely placing the LSI-11

can be used as the console device. The RTO1 is not

system in the Halt state by asserting a line break (con-

capable of use as the console device. Although the

tinuous ““space’’ transmission). (This feature is jumper-

RTO02-A is not capable of full console operation, it can

enabled on the DLV 11 through the use of framing error

be used as the console device, but it is limited to the

detection.)

following ODT commands:

oLvi

INTERFACE CABLE (BCO5M)

SLy

(LAS6:
foas. LT33
Vies
RTO!, RTO2-A,

RTO2-8B)

Figure 12-1

Direct 20 mA Current Loop Interface

INTERFACE

DLV 11

CABLE
(BeoEe)

DATA SET

(USER
SUPPLIED)

Figure 12-2

—

DLV 1

SLu

(BCOSM
OR BCOSC)
Figure 12-3

TELEPHONE

LINES

DATA SET

(USER
SUPPLIED)

Telephone Line Interface Via Data Sets

ACOUSTIC
COUPLER
DFO1

TELEPHONE
LINES

ACOUSTIC
COUPLER e
DFO1

Telephone Line Interface Via Acoustic Couplers

CP-1770

TERMINAL

(VTO5B VT50

RTOI,
LA36,
RTO2~A,RTO2-B
cP—-1771

(aga Ak
VTOS58, VT50,

(LA36,LT33

RTO1,RTO2-A,
RT02-B
cP—-1772

Table 12-1

LSI-11 Peripheral Options

Useas

Terminal Type

Model

Keyboard/Printer

LA36

Keyboard/Printer and

LT33

Name

DECwriterI1

Console
Device

Yes

Teletypewriter

Yes

VTOSB | Alphanumeric Terminal

Yes

Display Capacity

132 characters/line

1/0 Speed

(baud rate)

300

BREAK
Key

Yes

Serial

Required

Interface Type | Interface Options

|20 mA loop

DLV11, BCOSM

optional EIA

DLV1t, BCO5C

72 characters/line

110

Yes

|20 mA loop

DLV11, BCOSM

1440 characters (72 char.

110—2400

[20mAloopor

DLV11, BCOSM

EIA

DLV11, BCOSC

Paper Tape Reader/Punch

Keyboard/CRT Display
(A4

X 20 lines)

Keyboard/CRT Display
Data Entry Terminal
(Decimal 0—9display plus

| VTS0
RTO1

{ DECscope
DEC-LINK

Yes
No

960 characters (80 char.

75—9600

X 12 lines)

75—9600

4,8, or 12 characters
(optional)

110 or 300

Yes

120mA loopor

DLV11, BCOSM

optional EIA

DLV11, BCOSC

|20mA loopor
EIA

DLV11, BCOSM
DLV11, BCOSC

110—300 (20 mA)
110—1200 (E1A)

|20 mA loopor
EIA

DLV11, BCOSM
DLV11, BCOSC

110—300 (20 mA)
110—1200 (EIA)

|20mA loopor
EIA

DLV11, BCOSM
DLV11, BCOSC

110—300

—

|20 mA loopor
EIA

DLV11, BCOSM
DLV11, BCOSC

four status indicators)

Alphanumeric
Data Entry Terminal

RTO02-A | 30 Character Keyboard | Yes, with | 32 characters
Remote Terminal
limited
Command Set

Full Alphanumeric
Data Entry Terminal

RTO02-B | Alphanumeric Terminal

Acoustic Coupler
(To be used with one of

DFO1-A | Acoustic Telephone
Coupler

the above terminals)

Yes

32 characters

Al 1/0 characteristics of the
terminal are retained.

APPENDIX A
MEMORY MAP

RESERVED VECTOR LOCATIONS
000

(RESERVED)

004

TIMEOUT & OTHER ERRORS

010

ILLEGAL & RESERVED INSTRUCTION

014

BPTINSTRUCTION AND T BIT

020

IOT INSTRUCTION

024

POWER FAIL

030

EMT INSTRUCTION

034

TRAP INSTRUCTION

060

CONSOLE INPUT DEVICE

064

CONSOLE OUTPUT DEVICE

100

EXTERNAL EVENT LINE INTERRUPT

244

FIS (OPTIONAL)

264

RXV11

RESERVED DEVICE ADDRESSES
165000

REV11 ROM ADDRESSES

165777
173000

REV11 ROM ADDRESSES
173777

177170

RXV11 (RXCS)

177172

RXV11(RXDB)

177550

(PRS)

177552

(PRB)

177554

(PPS)

(P9

}

HIGH-SPEED

PAPER TAPE
READER

/PUNCH

177560

(RCSR)

177562 (RBU: F)

177564

177566

CO
NS
OLE
DEV
ICE

APPENDIX B
LSI1-11 BUS PIN ASSIGNMENTS

Row A

RowB

(Same as Row C)

(Same as RowD)
Module Side 1 (Component Side)

AA1l

BSPAREI1

BA1

BDCOK H

AB1

BSPARE2

BB1

BPOKH

AC1

BSPARE3

BC1

SSPARE4

AD1

BSPARE4

BD1

SSPARES

AE1

SSPARE1

BE1

SSPARESG6
SSPARE7

AF1

SSPARE2

BF1

AH1

SSPARES3

BH1

SSPARES

AJl

GND

BJ1

GND

AK1

MSPARE A

BK1

MSPAREB

AL1

MSPARE A

BL1

MSPAREB

AM1

GND

BM1

GND

AN1

BDMRL

BN1

BSACKL

AP1

BHALTL

BP1

BSPARES6

AR1

BREFL

BR1

AS1

BEVNTL

PSPARES3

BS1

PSPAREA4

AT1

GND

BT1

AU1

GND

PSPAREI1

BU1

PSPARE2

AV1

+5B

BV1

+ 5B

Module Side 2 (Solder Side)
AA2

BA2

AB2

-12

BB2

-12

GND

AC2

GND

BC2

AD2

+12

BD2

+12

AE2

BDOUTL

BE2

BDAIL2L

AF2

BRPLYL

BF2

BDAL3L

AH2

BDINL

BH2

BDAIAL

BSYNCL

AK?2

BJ2

BWTBTL

BDALSL

BK?2

BDAL6L

AL2

BIRQL

BL2

BDAL7L

AM2

BIAKIL

BM?2

BDALSL

AN2

BIAKOL

BN2

BDAL9L

AP2

BBS7L

BP2

BDAL10OL

AR2

BDMGIL

BR2

BDALI11L

AS2

BDMGOL

BS2

BDALI12L

AT2

BINITL

BT2

BDAL13L

AU2

BDALOL

BU2

BDAL14L

AV2

BDALIL

BV2

BDAL15L

B-1

APPENDIX C
7-BIT ASCII CODE

Octal

Code

Char

Octal

Code

Char

Octal

Code

Char

Code

Char
\

000 | NUL

040

100

001 | SOH

140

041

101

141

002 | STX

042

“

102

142

003 | ETX

043

103

143

004 | EOT

044

104

144

d
e

00S | ENQ

054

105

145

006 | ACK

046

106

146

007 | BEL

047

‘

107

147

g
h

010 | BS

050

(

110

150

011 | HT

051

)

111

151

012 | LF

052

112

152

j
k

013 | VT

053

113

153

014 | FF

054

’

114

154

015 | CR

055

115

155

m
n

016 | SO

056

116

156

017 | SI

057

117

157

020 | DLE

060

120

160

p
q

021 | DC1

061

121

161

022 | DC2

062

122

162

023 | DC3

063

123

163

024 | DC4

056

124

025 |

164

065

125

165

NAK

026 | SYN

066

126

166

027 | ETB

067

127

167

030 | CAN

070

130

170

031

| EM

071

131

171

032 | SUB

072

132

172

033 | ESC

073

;

133

[

173

{

034 | FS

074

134

174

035 | GS

075

135

] or4

036 | RS

175

}

076

136

176

037 | US

077

137

— Or <«

177

DEL

C-1

APPENDIX D

SUMMARY OF LSI-11 INSTRUCTIONS

WORD FORMAT
15

SINGLE OPERAND:
9

]

OPR dst

BINARY-OCTAL
REPRESENTATION

[

0P CODE
|

$S Ok DO

]

Mne-

monic

Mode
0
1~

5
6
7

Name

L MODE

(R) is operand [ex. R2=1/2]
(R) is address

@ (R)4

(R) is adrs of adrs; (R) -+ 2

TST(B)

m 057DD

test

@—(R)
X(R)

(R} — 2; (R) is adrs of adrs
(R)) + X is adrs

R
(R)

auto-incr deferred

R)+

(R} is adrs; (R) -+{(1 or 2)

—(R)

(R)— (1 0r2);is adrs

immediate
absolute
relative
ralative deferred

ROR(B)

wm 060DD

m 061DD
m 062DD
m 063DD
0003DD

#n
operand n follows instr
@#A address A follows instr
A tinstradrs 4+ 4 - X is adrs
@A_ instr adrs -- 4 -~ X is adrs of adrs

ADC(B)
SBC(B)
SXT

m 055DD
m 056DD
0067DD

=0 for word/1 for byte

) = contents of

X
%

= relative address
= register definition

Boolean

Condition Codes

= contents of source

= contents of destination

2ol

rotate right

-»C,d

rotate left
arith shift right
arith shift left
swap bytes

Cde
d/2
2d

*
*
*
v
oo
oo
** 00

add carry
subtract carry
sign extend

d+¢
d—-¢
or—1

*
*
-

*
*
*

*
*
0

*
-

move byte from

de«PS

1064SS

move byte to PS

PSes

OPR src, dst

OPR src, R or OPR R, dst
&

OP CODE

contents of register

L.
Mnemonlc

)

= conditionally set/cleared
= not affected
= cleared
= set

>~
~00E

Op Code

I
I

Instruction

SS OH DD

Operation

General

MOV(B)
CMP(B)
ADD

sSuB

1067DD

(

= becomes

= inclusive OR
= exclusive OR

Operations

= AND

0100
Y01
*
*
* .
* >
* _
e

MTPS

DOUBLE OPERAND:

= source field (6 bits)
= destination field
(6 bits)
R
= gen register (3 bits),
Oto7
(¢]
XXX = offset (8 bits),
~+127 to —128
N
= number (3 bits)
NN = number (6 bits)

V
v

compl)

0
- d
d+1
d—1t1
—d

MFPS

8S
DD

Processor Status (PS) Operators

Mulitiple Precision

LEGEND

Op Codes

Rotate & Shift
ROL(B)
ASR(B)
ASL(B)
SWAB

PROGRAM COUNTER ADDRESSING

2
3
6+ 7

dstResult

clear
complement (1's)
increment
decrement
negate (2's

auto-decr deferred
index
index deferred

Instruction

= 050DD
m 051DD
@ 052DD
= 053DD
m 054DD

Description

auto-decrement

Op Code

General

CLR(B)
com(B
INC(B)
DEC(B)
NEG(B)

Symbolic

auto-increment

m 1SSDD
m 2SSDD
06SSDD

16SSDD

move
compare
add

subtract

des
s—d
des+d

ded—sg

*
0 oo
rorow
o

Logical
BIT(B)
BIC(B)
BIS(B)

XOR

= 3SSDD
m 4SSDD
= 58SDD

074RDD

bit test (AND)
bit clear
bit set (OR)

exclusive OR

sad
de(—8)Ad
desvd

d «rad

R
*
*
R

¢
0
¢

B
-

JUMP & SUBROUTINE

Optional EIS

070RSS

MUL

071RSS

DIV

ASH

072RSS

ASHC

073RSS

re<rxs

multiply

r<tr/s

divide

shift

arithmetically
arith shift
combined

Mnemonic

Op Code

Instruction

Notes

roro

JMP
JSR
RTS

0001DD
004RDD
00020R

jump

PC « dst

MARK
SOB

0064NN
077RNN

Optional FIS

FADD
FSUB
FMUL
FDIV
BRANCH:

07500R
07501R
07502R
07503R

** 00
00
** 00
** 00

floating add
floating subtract
fioating multiply
floating divide

jump to subroutine
return from
subroutine
mark
subtract 1 & br

use same R

aid in subr return

(R) — 1, then if (R) # 0:
PC « Updated PC —
(2 x NN)

(if # 0)

TRAP & INTERRUPT:

B - - location

Mne-

If condition is satisfied:

monic

Op Code

Instruction

Notes

New PC « Updated PC + (2 x offset)

EMT

104000

emulator trap

PC at 30, PS at 32

104400

trap

PC at 34, PS at 36

000003
000004

breakpoint trap
input/output trap

PC at 14, PS at 16
PC at 20, PS at 22

return from interrupt

inhibit T bit trap

Branch to location,

to 104377

adrs of br instr 4 2

TRAP

to 104777

BPT
10T

000002

RTI

000006

RTT

(not for general use)

return from interrupt

Op Code = Base Code + XXX
MISCELLANEOUS:

Branches

branch (unconditional)

000400

BPL

100000 branch if plus

BNE
BEQ

BMI
BVC
BvVS
BCC
BCS

001000 br if not equal (to 0)
001400 br if equal (to 0)

100400
102000
102400
103000
103400

branch if minus
br if overflow is clear
br if overflow is set
br if carry is clear
br if carry is set

(always)

#0
—0

Z=0
Z=1

—

N=1
V=20
V=1
C=0
Cc =1

N=20

Mnemonic

Op Code

Instruction

HALT
WAIT

000000
000001

halt
wait for interrupt

CONDITION CODE OPERATORS:
5

OP CODE BASE =000240
1
1

002000 br if greater or

BLT

002400

BGT
BLE

equal (to 0)

br if less than (0)

003000 br if greater than (0)
003400 br if less or
equal (to 0)

N+V =0

>0
<0

NV =1
Zv (Nv»V)=0
Zv(NwV)=1

>
<

CvZ=0
Cvz=1

Unsigned Conditional Branches

BHI
BLOS

101000 branch if higher
101400 branch if lower

BHIS

103000 branch if higher

BLO

103400 branch if lower

or same

C=0

C=1

]

LI
|

0 = CLEAR SELECTED COND. CODE BITS
1 =='SET!SELECTED COND. CODE BITS

Signed Conditional Branches

BGE

reset external bus
(no operation)

000005
000240

RESET
NOP

NZV

Op Code

Instruction

CLC
CLv
CLZ
CLN
CCC

000241
000242
000244
000250
000257

clear C
clear V
clear Z
clear N
clear all ¢c bits

0
0

SEC
SEV
SEZ
SEN
SCC

000261

setC

- - - -1
-1 1 - 11 1

Mnemonic

000262
000264
000270
000277

setV
set Z
set N
set all cc bits

- =
-0
0 - 00

ol
!l 1o O

Branch Condition

Base Code Instruction

- =

Mne-

monic

PROCESSOR STATUS WORD

7
\

>
1

NUMERICAL OP CODE LIST

OP Code

Mnemonic

00 00 00

HfiLT

00 00 02 RTI

t
CARRY

NEGATIVE

RTT

00 64 N

RESET

00 67 DD

JMP

01 SSs DD

] (reserved)
NOP

00 02 41
1

cond

{

codes

00 02 77

00 03 DD

SWAB

00 04 XXX
00 10 XXX

BR
BNE

2_"

2,048

XXX

BGE

4'096

XXX

BLT

XXX

1.024

’

384

32,768

228

o or

512

524’288

XXX

00 30 XXX _

8,192

65 536

CMP

BIT

10 53 DD

10 54 DD

NEGB

05 SS DD
06 SS DD

BIC

BIS
ADD

10 56 DD
10 57 DD

SBCB
TSTB

MUL
DIV

07 2R

10 60 DD
10 61 DD

ASH

RORB
ROLB

10 62

ASRB

07 4R DD

XOR

07 50 OR

FADD
FSUB
FMUL
FDIV

10 64 SS
10 67 DD

MTPS
MFPS

11 SS DD
12 8S DD
13 8S DD

MOVB
CMPB
BITB

07 3R SS

07 50 1R
07 50 2R
07 50 3R
50

BLE

BGT

ABSOLUTE

10 00 XXX BPL

0051

COM

XXX

10 10 XXX

10
10
10
10

14
20
24
30

XXX
XXX
XXX
XXX

24K
28K

10 63 DD

BICB

BISB

SsuB

SOB

BMI

BHI

BLOS
BVC
BVS
BCC,
BHIS
BCS,
BLO

077
117

137
157

Address Contents|Address Contents
— 744
— 746
— 750
— 752
— 754

— 756
— 760

— 762

016
000
012
000
005
105
100

116

701 |— 764
026 |— 766
702 |— 770
352 {— 772
211 |— 774

711
376

|— 776

000
—
005
177
000
177

002
400
267
756
765

TRAP VECTORS
000

560 (TTY)

004
010

162

014
020

D-3

(reserved)
Time Out & other errors
illegal & reserved instr

BPT instruction
10T instruction

024
030
034

244

ASLB

BOOTSTRAP LOADER

Starting
Address: — 500
Memory Size:
4K 017
8K 037
12K 057
16K
20K

ASHC

(unused)

10 34 XXX

LOADER

DECB

10 55 DD ADCB

07 OR SS
07 1R 8§

INC

INCB

03 SS bD

BEQ

DEC
NEG
ADC
SBC
TST

CLRB

COMB

02 SS DD

JSR

DD
DD
DD
DD
DD

TRAP

o4 55 pp

CLR

00 53
00 54
00 55
00 56
00 57

}EMT

10 50 DD

10 52 DD

Mnemonic

10 51 DD

MOV

00 50 DD
00 52 DD

00 70 00
00 77 77

RTS

00 02 40

2_"

(unused)

10 47 77

00 00 05

00 02 27

10 44 00

10T

00 02 10

POWERS OF 2

SXT

00 00 04

00 63 DR

00 02 0R

PRIORITY

10 43 77

00 61

BPT

00 01 DD

TRACE TRAP

'IA\‘/ISALRK

00 62 DD ASR

WAIT

00 0o 77 4 (unuse

ZERO

10 40 00

00 00 03

00 00 07 }

Mnemonic OP Code

00 60 BB 28?

00 00 01

00 00 06

OVERFLOW

OP Code

Power Fail
EMT instruction
TRAP instruction
FIS (optional)

ODT COMMANDS
Description

Format

RETURN
LINE FEED

Close opened location and accept next command.
Close current location; open next sequential
location.

Open previous location.

Take contents of opened location, index by con-

Take contents of opened location as absolute

tents of PC, and open that location.

address and open that location.
Open the word at location r.
Reopen the last [ocation.

r/
/

Open general register n (0-7) or S (PS register).

$n/or Rn/

Go to location r and start program.

r;GorrG

Execute bootstrap loader using n as device CSR.

nkL

Console device address is 177560.

Proceed with program execution.
Erases previous numeric character.

PorP
RUBOUT

Response is a backslash (\).

7-BIT ASCIl CODE

Octal
Code
000

Char

NUL

Octal
Code

Char

040

o
002

SOH
STX

041
042

!
"

004
005
006
007
010
011
012
013
014

EOT
ENQ
ACK
BEL
BS
HT
LF
vT
FF

044
054
046
047
050
051
052
053
054

$
%
&
4
(
)
*
-+
'

024

DC4

064

003

015
016
017
020
021
022
023

025
026

027
030
031
032

033

034

ETX

CR
SO
Sl
DLE
DCA
DC2
DC3

NAK
SYN
ETB
CAN
EM
suUB

ESC

055
056
057
060
061
062
063

065
066

067
070
071
072

073

.
/
0
1
2
3

5
6

7
8
9
:

;

100

101
102

103

104
105
106
107
110
111
112
113
114

115
116
117
120
121
122
123
124

125
126

127
130
13
132

133

074

134

076

136

035

037

036

043

Octal
Code

075

077

135

137

Char

A
B

o}
D
E
F
G
H
|
J
K
L

M
N
0
P
Q
R
S
T

V)
Vv

w
X
Y
Z

[

Octal
Code Char
140
141
142

143

144
145
146
147
150

151
152
153
154

a
b

d
e
f
g

i
i
k
|

155
156
157
160
161
162
163

m
n
[o]
p
q
r
S

165
166

u
v

164

167
170
171
172

173

174

w
X
y
z

{

]

175

}

—_

177

DEL

176

—

APPENDIX E

H9270 BACKPLANE CONFIGURATIONS
E.1

BASICDAISY CHAIN GRANT PRIORITY

HIGHEST

PRIORITY

LOWEST

PRIORITY

}

——1.

_(
—

!
—

)

Note:
Arrow indicates BDMG and BIAK daisy ¢ hain signal routing from

highest priority device slot to lowest priority device slot on the
backplane.

E.2

TWOBACKPLANE CONFIGURATION

PROCESSOR MODULE

OPTION 2

OPTION 1
FIRST

OPTION 3

BACKPLANE

OPTION 4

250 2 TERMINATOR/

ION

CABLE CONNECTOR (1)

OPTION

% *
EXPANSION

CABLES (1)

J/ W

CABLE CONNECTOR (1)

OPTION 6

OPTION 8

OPTION 7
SECOND

OPTION 9

OPTION 10

120 Q@ TERMINATOR/

CABLE CONNECTOR (2)

BACKPLANE

OPTION 11

Notes:

1. Included in BCV1B bus expansion option. (Cables are available
in 2, 4, 6, or 12 ft. lengths.)
2. Included in TEV11 bus terminator opticn.

CP-2047

E-1

E.3

THREE BACKPLANE CONFIGURATION

PROCESSOR MODULE

OPTION 2

OPTION 1
FIRST

OPTION 3

250

BACKPLANE

OPTION 4

TERMINATOR/

CABLE CONNECTOR (1)

OPTION 5

AN %
EXPANSION

CABLES (1)

N7\

A 1 Y

CABLE CONNECTOR (1)

OPTION 6

OPTION 8

OPTION 7

OPTION 9

OPTION 10

CABLE CONNECTOR (2)

OPTION 11

SECOND
BACKPLANE

* /W*\
EXPANSION

CABLES (2)

» 1 Y

CABLE CONNECTOR (2)

OPTION 12

OPTION 14

OPTION 13

OPTION 15

OPTION 16 (4)

120 2 TERMINATION (3)

OPTION 17 (4)

THIRD

BACKPLANE

Notes:

1. Included in BCV 1B bus expansion option. (Cables are available

in 2, 4, 6, or 12 ft. lengths.)
Included in BCV 1A bus expansion option. (Cables are available
in 2, 4, 6, or 12 ft. lengths.)
3. Included in TEV11 bus terminator option.
4. The LS111 Bus is restricted to 15 options, maximum. These

option slots would only be used when previous option(s)
occupy more than 1 option location.

CP-2048

E-2

APPENDIX F

BUS INTERFACEILC. PINS

F.1

DEC8640 QUAD 2-INPUT NOR GATES

(Bus Receiver)
14

VCC

[1 11
[]
T

HEERERN
1

GND

mlim

= mp=
cP-1271

F.2

DEC8881 QUAD 2-INPUT NAND GATE

(Bus Driver)
VCC
ke

S It
=

[1[]

EpEEEEENE L
2

L
7
GND

CP-1272

F.3

DEC8641 QUAD UNIFIED BUS TRANSCEIVER
(Bus Receiver/Driver)

BUs 1 ——]

Vee

DATA IN1 —2]
DATA ouT 1 ——]

BUS
4
DATA IN 4

BUS 2 —2|

DATA IN 2 —|
DATA OUT 2 —2—

bATA OUT 4

BUS 3
DATA
IN 3

ENABLE A ——]
GROUND ——]

DATA OUT 3
ENABLE B
=

DATA [N 1

o) e

ENABLE A

ENABLE B

/
DATA OUT1

ONE OF FOUR
1€-0089

F-1

SOFTWARE SERVICES

Programs and software manuals should be ordered by
title and order (or publication) number. In the United

States, send orders to the nearest distribution center.
Digital Equipment Corp.

Software Distribution Center
146 Main St.

Maynard, MA 01754
Digital Equipment Corp.

Software Distribution Center
1400 Terra Bella
Mountain View, CA 94043

Outside the United States, orders should be directed to
the nearest Digital Field Sales Office or representative.

LSI-11, PDP-11/03 User’s Manual
Changes and Additions
November 1975
This change package will update your

revise the manual as described below

manual (EK-LSI1 l-TM-OOI) fo the
-

revision (EK-LSI11-TM-002). Caref

ully

Correct the indicated text as direct

ed.

Correct your copy of the manual as

directed below. Text to be changed

Page

is shown underlined:

Text as Printed

)

1-1, Paragraph 1.1, last line: _

Change to

|
Microprocessor

“Processor

3-1, second paragraph, line 7:

CSR

control/status register (CSR)

3-1, paragraph 3.2, 3. Service Requi

rements, last line:

i}i)i_n_g_

tying

3-4, CAUTION, line 1:

should

must

3-10, Figure title:
DATIOB

DATOB

4-5, last paragraph, line 4:
REPLAY

4-7, paragraph 4.2.2.6, second paragraph,

line 5:

PH3 H
4-7, paragraph 4.2.2.6, third paragraph,
5

PH2 H
line 3:

Change to

Text as Printed

Page
4-14, paragraph 4.2.4, lines 6 and 7:

delete: zener-regulated

to -5V and -9V. The -9V output is

6-7, XCSR, Bit 07, last line:

Read/write bit.
9.3, paragraph 9.2.3, second paragraph, line 4:

no
9.3, paragraph 9.2.3, second paragraph, line 5:

Jumpers not installed
represent logical Os;

jumpers in-

9.4, Table 9-2, 512 by 4 chips Word/Byte address, line 5:

100001777
B-1, pin BV1

D-4, 7-BIT ASCII CODE:

delete this table (refer to revised Appendix )

Read-only bit.
all

Jumpers installed
represent logical Os;

jumpers not in-

1000011777

CONFIGURING

LSI-11 PROCESSOR MODULE JUMPLRS

(SUPPLEMET TO THE LSI-11, PDP-11/03 USER'S TAHUAL)

JULY 1976

DIGITAL EQUIPFET CURPORATION
COPOIEATS GROUP HEADUARTLIS
Oit TRUH WAY

MARLBOROUGH, ., OL/52

"\ PACTDRY CONFIGURED

Do NOT CHANGE

r——
w8

~= N\
1

.
IR

ot
.

—

0} Jo

Tl g A0 PEY b

I
FIGURE 1 KD11-F and KD11-J JUMPER LOCATIONS

CONFIGURING LSI-11 PROCESSOR MODULE JUMPERS

11 wire wrap posts which allow
GENERAL - The processor module contains
fic system application.
speci
a
the user to configure the module for are
ry configured as shown in
facto
KD11-F and KD11-J processor modulesgured as descr
ibed in the following
Table 1. Jumpers can be user-confi
module .as shown in
ssor
proce
the
?aragraphs. Jumpers are located on
igure 1.

Table 1

KD11-F and KD11-J Factory-Installed Jumpers

Jumper
Wi

KD11-d (M7264-YA)
Status Function

KD11-F (M7264)
Function
Status
—® R

Resident memory bank

Resident memory

—P ]

Resident memory bank

Resident memory

Event line (LTC)

1 not selected

0 selected

interrupt enabled
Processor-controlled

Power-up mode O

Factory-configured

W9
W10

memory refresh enabled

selected

bias voltage (do not
change)

Disable reply from
resident memory

selected

bank 0 not
selected

Event line (LTC)

interrupt enabled
Processor controlled memory

refresh disabled

Power-up mode
0 selected

Factory-configured

bias voltage (do
not change)

Disable reply

Enable reply from
resident memory

bank 1 not

from resident

memory

Disable reply
from resident

“7 DisaBite on-board < T
1 Enableon-board w1l
'”~°memory=3e1ect'»w~a;m;f_w,g,w_,fffw;memQ§y¥§glectw;f;;{Zfljj’*
A
NOTE

I= Instalied

R= Removed

MEMORY REFRESH

LINE TIME CLOCK

The LSI-11 processor has the capability of completely controlling
the refreshing of all dynamic MOS

LTC (or external event) interrupts
are enabled when jumper W3 is removed
and the processor is running. The
jumper can be inserted to disable

memories in a system when jumper
W4 is removed. Memory refresh is

always required when dynamic MOS

memory devices are used in the

LSI-11 system, such as the KD11-F
resident memory and the MSV11-B
4K by 16-bit read/write memory

module. The refresh operation
can be controlled by a device
other than the LSI-11 processor,
if available, such as the REV11-A
and REV11-C options. If such a

this feature. The LTC interrupt is
jnitiated by an external device when
it asserts the BEVNT L signal. This
is the highest priority external
interrupt request; processor inter-

rupts have higher priorities.

external interrupts are enabled (PS
bit 7 = 0), the processor PC (R7)
and PS word are pushed onto the

processor's stack.

The LTC (or

device is used, or if no dynamic

external event device) service
routine is entered by vector address

in the system (KD11-J), install
W4. The refresh sequence is

ress input operation by the processor is not required since vector

MOS memory devices are present
described below.

‘The processor's memory refresh
sequence is controlled by resi-

dent microcode in the processor

which is initiated by an in-

terrupt that occurs once every

1.6 ms. 1t is the highest
priority processor interrupt.

Once the sequence is initiated,
the processor will execute 64
BSYNC L/BDIN L bus transactions,
while asserting BREF L. The
BREF L signal overrides memory

bank address bits 13-15 and allows
all memory units to be simultaneously enabled. After each bus
transaction, BDAL1-6L is incremented by 1 until all 64 rows

have been refreshed by the BSYNC
L/BDIN L transaction.

This pro-

y
s ...
130utel
cess takes.approxima

100; the usual interrupt vector add100 is generated by the processor.

The first instruction of the service

routine will typically be fetched within 16ps from the time BEVNT L is

asserted; however, if optional EIS/FIS
instructions are being executed, this
time could extend to 50.45us. This
time could also be extended by pro-

cessor trap execution (memory refresh,
T-bit, power fail, etc.), or by asserting the BHALT L signal.

POWER-UP MODE SELECTION

Since the LSI-11 can be used in a
variety of system applications that

have either (or both) volatile (semi-

conductor read/write) or nonvolatile
(PROM or core) memory, one of four
power-up mode features are available

rs. .-~ during-which external interrupts - “%ted {or changed) by wire-wrap jumpe

%bééséo?w(fl7264)‘modu1e.*'Note that
”’HGWeVér;*DMA”requeStS“cafi“be”*“”“******“*pthe
jumpers affect only the power-up
granted between each of the 64
mode (after BDCOKH and BPOK have been
refresh transactions.
asserted); they do not affect the powerdown sequence.

Reader’s Comments
[.SI-11, PDP-11/03 User’s Manual
EK-LSI11-TM-002

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