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EK-LSI11-MC-001

2006

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Document:	LSI-11 PDP 11/03 Maintenance Card
Order Number:	EK-LSI11-MC
Revision:	001
Pages:	32
Original Filename:

OCR Text

LSI-11
PDP 11/03

ODT COMMANDS
Description

Format

(CR)

(LF)

Close opened location; accept next ccmmand.
Close current location; open next sequential location,

or GPR.

torA

Open previous location or GPR.

“<or
.

Take contents of opened location, index by contents of

Take contents of opened location as absolute address and

Open the word at location r.

Reopen the last location.

PC, and open that location.

open that location.

$n/ or Rn/ Open general register n {(0-7) or S (PS register).
rGorrG

Go to location r and start program.

Execute bootstrap loader using n as device CSR. Console
device address is 177560.

PorP

Proceed with program execution.

RUBOUT/

Erases previous numeric character. Response is a back-

DELETE

slash (\).

Print internal register contents. Data indicates how CPU
entered ODT.
XXXXXN

N = 0or 4
1 or 5
2 or 6

3 °

where:

Haltinstruction on B Halt line.
Bus error while getting device interrupt vector.
Bus error during memory refresh.

Double bus error (stack contains non-existent
address).

Reserved instruction trap.

Conditions 1, 2, 4 occurred.

In order for valid data to be displayed following an error
condition, this command must be executed immediately.
1

TABLE OF CONTENTS

. . .

ODT COMMANDS

SWITCH REGISTER TO OCTAL CONVERSION . ..........

... ...

REV 11 COMMANDS

Module Version and JUMPEers . ... ..o

BACKPLANES
e

KD 1T

et e

e
oo e
v vvoevo

e e

.« .ttt

e e

MSV11-B

............ F T

I
I

I
I
T

LSI-11 INSTRUCTIONSET

.. .o

RESERVED TRAP AND INTERRUPT VECTORS . .. ........
Z-BITASCIH CODE

.o o

LSI BUSPINNING

.. .ot i e

PROCESSOR STATUSWORD

. ..... ...

SWITCH REGISTER TO OCTAL CONVERSION
LEAST
SIGNIFICANT
OCTAL DIGIT

MOST
SIGNIFICANT
OCTAL DIGIT

13[12'11
numser |'o 8"

SWITCH

1T T

FLE

SWITCH X UP

OCTAL

0
1
2
3
4
5
6
7
8

—
—
—
—
—
-

1
2
4
10
20
40
100
200
400

—

11
12
13
14
15

.
—
-

1000

2000

4000
10000
20000
40000
100000

REV11 COMMANDS AND DIAGNOSTICS (M9400)

REV11 STARTUP FLOWCHART
START AT )

(

LOCATION

173000
*

*LTC OFF

OPTIONAL STARTING LOCATION

DOES NOT RUN
165006

DIAGNOSTIC, ONLY PRINTS

EXECUTE NONMEMORY MOD-

lls’l

IFYING CPU
DIAGNOSTIC

BRANCH SELF
OR
HALT

ENTER ODT, OUTPUT:

PC+2

OUTPUT

30 TERMINAL

MEMORY

‘

DIAGNOSTIC

GNTER xXm <09
EXECUTE
MEMORY

1AG

DIAGNOS

oODT

( ENTER OD )

HALT MODE

mie

ODT FUNCTIONS
ENABLED.

HALT

R
ODT, OUTPUT
ENTE
%
0173732

S
TEST ERROR
ADDRES

YES
OUTPUT
TO TERMINAL

0173756%

DATA TEST ERROR

+000010

TIMEOUT TRAP

(ABOVE 1ST 4K)

ennnnnn

TIMEOUT TRAP

{(1ST 4K)

* GOOD DATA-R3

BAD DATA -ADDRESS R2

REV11 (Cont.)

CPU

(enTERxC <CR> )

DIAGNOSTICS

EXECUTE CPU
DIAGNOSTICMEMORY
MODIFYING

HALT

ENTER ODT, OUTPUT:
PC+2

@
(PC+2 MAY BE IN REV11
PROGRAM OR IN TRAP
VECTOR AREA. USEM
COMMAND TO DETERMINE

ouTPUT

REASON HALT MODE ENTERED)

$
TO TERMINAL

RXV11 BOOTSTRAP
ENTER DX <CR>

OR DXn* <CR>

*DISK DRIVEO OR 1
(0 BY DEFAULT)

EXECUTE CPU
AND MEMORY
DIAGNOSTICS

(XM AND XC)

HALT

SEE ERROR LISTING
FOR XM AND XC

COMMANDS

EXECUTE
BOOTSTRAP
FIRMWARE

SUCCESS-

FULBOOT

e $ - TIMEOUT TRAP
OR

HALT

ENTER ODT, OUTPUT:

e 165316

DONE FLAG NOT SET

SYSTEM
LOADED

e 165644

BOOTSTRAP ERROR

nonnnn

OTHER HALT IN TRAP VECTOR AREA

REV11 (Cont.)
ENTER DK <CR -

*DISK DRIVEO OR 1

OR DKn* <CR
.

(0 BY DEFAULT)

RK05 BOOTSTRAP

EXECUTE CPU
AND MEMORY

DIAGNOSTICS
(XM AND XC)

HALT

SEE ERROR LISTING
FOR XM AND XC

COMMANDS

EXECUTE
BOOTSTRAP
FIRMWARE

SUCCESS-

ABSOLUTE LOADER

FULBOOT

HALT

SEE ERROR

LISTING FOR
DX COMMANDS

ENTER AL <CR>

OR AL dddddd® <CR>CR
* DEVICE CSR
ADDRESS IF

EXECUTE CPU AND|

NOT 177560

SYSTEM

LOADED

MEMORY DIAGNOSTICS

(XM AND XC)

HALT

SEE ERROR
LISTING FOR

XM AND XC

COMMANDS

EXECUTE

ABSOLUTE
LOADER

PROGRAM

"OUTPUT

PROGRAM
LOADED

HALT

ENTER ODTOUTPUT:

N\YES TIMEOUT

TRAP

LOOP - PAPER TAPE

READER NOT DONE
OR

165625
HALT

ENTER ODT, OUTPUT:
*165534

CHECKSUM ERROR
«OTHER - HALT IN TRAP
VECTOR AREA

{OTHER THAN TIMEOUT)

REV11 (Cont.)

ABSOLUTE LOADER (RELOCATED)
ENTER AR <CR>

OR AR dddddd* <CR>

DEVICE CSR

ADDRESS IF

NOT 177560

‘
EXECUTE XC AND
XM DIAGNOSTICS,
THEN HALT AT
165412 ENTER
RELOCATION
ADDRESS BIAS IN
R4 AND

PROCEED (P).

ENTER”1"
IN R4 USING
ODT, LOAD TAPE
AND ENTER "P”

]
PROGRAM
LOADED

HALT

ENTER ODT OUTPUT:
165626

REFERTOAL

COMMAND ERRORS

REV11 (Cont.)

MODULE VERSIONS AND JUMPERS

0‘}9

.\;V?V &

& &Q‘@O\vquoo 7&5 é& ?0« /@«"’

\"9@‘1?’00600 o“&o‘“on\\Q &WQ4\“"\Q~:‘°‘Q~OPTION

M9400

YA*

REV 11-A

TEV11 (TERM.)

yex

REV11-C

CABLE CONN.

CABLE CONN. W/TERM

YF*

REV11-F

YH*

REV11-H**

YJ*

REV11-J

TABLE SHOWS STANDARD JUMPERS (X = INSERT)
(SOLID = MODULE FUNCTIONS)

*EACTORY SET POTENTIOMETER

**REMOTE BOOT

£19

REV11
w4

BACKPLANES

H9270 PIN IDENTIFICATION
H9270 POWER AND

SIGNAL CONNECTORS
______
|

MODULE SIDE IDENTIFIER

TYPICAL MODULE

2 = SOLDER SIDE
\\‘

“b\\

WIRE-WRAPPINS

1= COMPONENT SIDE PASS THROUGH

LOCATION

ROW

IDENTIFIER (g1 015 A1 81

PC BOARD
3270
4

1
N
8
N
!
ls | | MODULE
o Y e et et tanotes |ocovadeberazonsa
SIDE
e
Sl A w3 4 SRR
S RSO
A

R N R o L ¢3
t

_______

|
|
|
fl_._._______.__’._._______._|____.._.__.,.__
{
— .Jl. _______
e e

1
|
__Jl,_ ________ e

{

CL3L

L
cS3

BEVNT L

+12V

-1

[«]

BDCOK H

BHALT L
GND

]

+5V

SRUN L

BPOK H

+5VB

]GND

GND

PROCESSOR MODULE

NOTE 1.

OPTION 2

OPTION 1

OPTION 3

OPTION 4

OPTION 6

OPTION b

Unused slots require backplane jumpers for
BIAKI/O

BDMGI/O L

BACKPLANES (Cont.)

DDV11-B

PROCESSOR

A
-—

—5

OPTION 2

OPTION 1

OPTION 3

OPTION 4

OPTION 6

OPTION b

OPTION 7

OPTION 8

OPTION 10

OPTION 9

OPTiON'H

OPTION 12

OPTION 14

OPTION 13

OPTION 15

OPTION 16

9
-

USER DEFINED
SLOTS
NOTE 1.

NOTE 2.

Unused slots require backplane jumpers for

BIAKI/O

BDMGI/O

A terminator is required in the last unused option slot

if 7 to 15 unit loads are installed. (One module = one
unit load.)

MULTIPLE BACKPLANE CONFIGURATION

NUMBER OF

H9270

BACKPLANE OPTION

BCV 1B-XX*

BACKPLANES | 15t to 2nd
2

3rd

M9400-YE | terminate first
to MS401

BCV 1A-XX*

2nd to 3rd
unused option slot

M9400-YE | M9400-YD

terminate first

to M9401

unused option slot

to M9401

*NOTE: XX denotes cable length. BCV1B-XX and BCV1A-XX cables
in a 3 backplane system must differ by at least four feet.

KD11 PROCESSOR (M7264)

il -

— s o)

w8 W7

Iws
W1 oI IW4

wsIst
Jwo

re
e

ALL JUMPERS (EXCEPT 7 AND 8) ARE WIRE WRAPPED.

M7264 ETCH REV E (AND LATER)

IWS

Iwz

IWG

Iw1

IW3
[wa

T
L

ALL JUMPERS ARE WIRE-WRAPPED.

]

M7264 ETCH REV C, D (W7-W11 NOT USED)
OPTION IDENTIFICATION

NO EIS/FIS

EIS/FIS

DIBOL/EIS

NO MOS

KD11-H

KD11-N

KD11-Q

MOS

KD11-F

KD11-L

KD11-P

KD 11 PROCESSOR (Cont.)

ALL ETCH REV (JUMPERS)
LTC EXTERNAL

RESIDENT MEMORY ADDRESSING

(N/A KD11-H, N)

W1 W2

Bank
0
1

R
|

Not addressed

R
|

POWER UP

PROCESSOR REFRESH

| W3

Enable
Disable

MODE

Enable

0—to 24

Disable

1—to ODT

2—to 173000

3—to special

Potentiometer — Factory Set

ETCH REV E AND ABOVE ONLY (JUMPERS)
Jumper

BIAS VOLTAGE

W7, W8

Enable

Disable

FACTORY | FACTORY

ON-BOARD PROCESSOR
MEMORY

REFRESH REPLY

W10

MEMORY SELECT

W11

MSV11-B

M7944

MSV11-CD

M7955
G653/H223

MMV11-A

]

ZMS

—

AJvd a-lL ASI
12

|o = H3a4dWNTrQG3LNYA3OIWS3NYt O4 = HOLIMSN43O0

-pueH18IndWod0DINUtO-L ASI 002 1 4 0 © - 0o 0 4 oo

SFHOLIMS ¥ ANV S v:m,“wmfimt pue g

DLV11 (M7940)

STANDARD CONSOLE DEVICE
VECTOR = 06X

ADDRESS = 17756X
15

&
BIT

Hooo[o 0 0

TM
o
wojn
>l>l>
>l>

0O~

1’1

JUMPER

13 12

111

| <

1=XMITTER

A10

&
BIT

0=RECEIVER

(RANGE =0-374 )}

A1l

VECTOR

0=CSR

JUMPER
ADDRESS (RANGE

1=D8

160000,-177776,)

O=RECEIVER
1=XMITTER

ALL JUMPERS

|INSERT

REMOVE

177560

DONE

DATASET

STATUS
(READ ONLY)

INTERRUPT
ENABLE

15
XCSR

RECEIVED DATA <J

—

ENABLE

RBUF E%ééjyi///jjjzjgég

177562

READER

BREAK

READY

INTERRUPT
15

XBUF

177566 E%éééééééizzifzzéziééj

ENABLE
7

miTTEb oA

DLV11 (Cont.)

TP2

o--}:»--o

XMIT/RECEIVE MODE

CcL3

cL4

Qcu2

CL 1,2, 3,4 ALL INSERTED

CL1

CURRENT LOOP Active:

CABLE
CONNECTOR

BAUD RATE: XMIT/REC

BAUD
RATE

| R

FR—

BAUD

RATE

600

| R

1200

R|R

1800

|R|R

| R

150

| R

110

200

1345 |

300

FR—
0

2400

R|{R

I
|R

| R

4800

9600

| R

EXT

| R

(PIN BH1)

DLV11 (Cont.)

BREAK

PARITY
PEV

FEH

ENABLE odd

]

ENABLE

even

DISABLE

—

DISABLE

|
R

DATA FORMAT

2Sb

No. of Data Bits

NB1

NB2

No. of Stop Bits

[

e FOR LT33 (ASR33) or LT35 (ASR35) insert 0.005 uf

capacitor between TP1-TP2.

® EIA CABLE — BCObC-X

@ 20 mA CURRENT LOOP CABLE — BCO5M-X

NOTE:

RXV11 (M7946)

STANDARD DEVICE

ADDRESS = 17717X

BIT »

g8 7

VECTOR = 264

6 5 4
<t

1V O

3 2
N

2122

)]
00

(RANGE 0 = 374s)

131211109876543210

22:1907«:\!\
EHEEN H
H BHEHEHBEHE
1l 1 2|28

w14

»
BIT

JUMPER
0

ADDRESS (RANGE = 160000¢ - 177776s)

ALL JUMPERS

REMOVE = 1"

1=R

INSERT = "0"

RXV11 (Cont.)
RXCS

COMMAND FUNCTIONS
RX01

COMMAND PROTOCOL

Function

Read Status

000

Full Buffer

001

Empty Buffer

2. Wait for done.
3. Check buffer for status.

010

Write Sector

011

Read Sector

100

Not used

101

Read Status

110

Write Sector with

Read Definitive Error Code
1.

lssue functions and GO.

Wait for done.

3. Check buffer for definitive

deleted data
111

lIssue function and GO.

errors.

Read Error Code
CONTROL
STATUS REGISTER
15 14 13

RXCS

177170

ERROR
RX INIT

T/R |[DONE} ryNCTION
INTERRUPT
GO
ENABLE

UNIT

SELECT

ERROR AND STATUS REGISTER
15

RXES

177172

READY
DEL
DATA

INIT

| CRC

DONE|

ERR

WRITE
PROTECT

pARITY

ERR

ERR
SECTOR

ADDRESS REGISTER
15

]

SECTOR ADDRESS

(1-328)
TRACK ADDRESS REGISTER

TRACK ADDRESS
(0-1148)

DATA BUFFER REGISTER

s NI
177172

—~—

DATA BYTE

RXV11 (Cont.)
ERROR CODES AND MEANINGS
0010

/DRIVE O FAILED TO SEE HOME ON INITIALIZE

0020

DRIVE 1 FAILED TO SEE HOME ON INITIALIZE

0030

/EQUND HOME WHEN STEPPING OUT 10 TRACKS FOR

0040

/TRIED TO ACCESS A TRACK GREATER THAN 76

0050

/HOME FOUND BEFORE DESIRED TRACK WAS

0060

/SELF-DIAGNOSTIC ERROR

0070

/DESIRED SECTOR COULD NOT BE FOUND AFTER

INIT

REACHED

/LOOKING AT 52 HEADERS
0100

/WRITE COMMAND ON A WRITE PROTECTED DISK

0110

/MORE THAN 40 MICROSEC AND NO SEP CLOCK SEEN

0120

/A PREAMBLE COULD NOT BE FOUND

0130

/PREAMBLE FOUND BUT NO 1D MARK FOUND WITHIN
/ALLOWABLE TIME SPAN

0140

0150

/CRC ERROR ON A HEADER, NO FLAG
/THE HEADERS TRACK ADDRESS OF A GOOD HEADER
/DOES NOT COMPARE WITH THE DESIRED TRACK

0160

/TOO MANY TRIES FOR A ID ADDRESS MARK

0170

/DATA MARK NOT FOUND IN ALLOTTED TIME

0200

/CRC ERROR ON READING THE SECTOR FROM THE

0210

/PARITY ERROR ON SOME WORD FROM INTERFACE

DISK

RXV11 BOOTSTRAP (Drive 0 only)
(terminal response underlined)

START:

@001000/000000 5000 <LF>
001002/000000 12701 <LF>
001004/000000 177170 <LF>

001006/000000 105711 <LF>
001010/000000 1776 <LF>
001012/000000 12711 <LF>

001014/000000 3 <LF>

001016/000000 5711 <LF>
001020/000000 1776 <LF>
001022/000000 100405 <LF>

001024/000000 105711 <LF>

001 026/000000 100004 <LF>
001030/000000 116120 <LF>

001032/000000 2 <LF>
001034/000000 770 <L:>

001036/000000 0 <LF>
001040/000000 5007 <LF>
001042/000000 0 <CR>

RKV11 (M7269)

STANDARD DEVICE
VECTOR

ADDRESS 17740X

Bl e

12 1110

145

- 220

]

[01000¢mm8:,“2“£:0000‘
L1

1313131313313 | |
J

JUMPER

VECTOR (RANGE 0-7760)

Bil g

13121110

111

—

mlre

13131313 133]13(2|3]
I

1
=

BYTE

0 = WORD

JUMPER
ADDRESS (RANGE 160000- 177777)

JUMPERS

RKV11

w14

W13

wi2

INSERT = "1"

REMOVE = 0"

ALL JUMPERS

RKV11 (Cont.)
ERROR REGISTER

1110

0
1

3
4

AN =n
41312

DRIVE ERROR
OVERRUN

WRITE VIOLATION
SEEK ERROR

PROGRAMMING ERROR

MEMORY ———

NON-EXIST

DATA LATE
TIMING ERROR
NON-EXIST DISK

NON-EXIST CYLINDER
NON-EXIST SECTOR
CHECKSUM ERROR
WRITE CHECK ERROR

CONTROL STATUS REGISTER

1110 9 8
15 141312

e [LTETHA
] 1L

) §

ERROR

HARD ERROR

SEARCH COMPLETE

INHIBIT RKBA INCREMENT

FORMAT

STOP ON SOFT ERROR
CONTROL READY
INTERRUPT ON

MEMOCRY EXTENSION
FUNCTION
GO

DISK ADDRESS REGISTER

L]
1N

TN N N A A
e |

DRIVE SELECT_’
CYLINDER ADDRESS

(0-3128)

SURFACE

SECTOR ADDRESS

WORD COUNT REGISTER

RKWC

177 406

| 2's COMPLEMENT OF TOTAL NUMBER OF WORDS |
[

S I

Mi-0706

CURRENT BUS ADDRESS REGISTER

RKBA

177 410

[

CURRENT BUS ADDRESS

RKV11 (Cont.)

DRIVE STATUS REGISTER
151413121110
9
RKDS

177 400

7
6

L] L]
W

]

{

DRIVE IDENTJ

DRIVE POWER LOW
RKO5

DRIVE UNSAFE
SEEK INCOMPLETE

SECTOR COUNTER OK
R/W/S READY
ACCESS READY

WRITE PROTECT STATUS
SECTOR COUNTER-SECTOR ADDRESS
SECTOR COUNTER
DATA BUFFER REGISTER
15

HKDB

DATA

Lttt

RKV 11 BOOTSTRAP (Drive 0 only)

(terminal response underlined)
START

@001000/000000 5<LF>
001002/000000 1006 1<LF>
001004/000000 6<LF>

001006/000000 1276 1<LF>

001010/000000 177400<LF>
001012/000000 2<LF>
001014/000000 12711<LF>

001016/000000 5<LF>
001020/000000 105711<LF>

001022/000000 100376<LF>

001024/000000 5007<LF>
001026/000000 0<CR>

@RO/XXXXXX O<LF>
R1/XXXXXX 177404<CR>

LAV11 (M7949)

STANDARD DEVICE
VECTOR = 200

ADDRESS = 17751X
BiT»

933

[;lo o olo 0 0
|

~\7

SWITCH#

766

[

l
5

0 o]
1

1
SWITCH PACK

VECTOR (RANGE = 0-774)

BIT#

SWITCH# -~ \6

1,56

131211109

1 1LAGE

10 LACS

SWITCH PACK 3

2
SWITCH PACK

1 =

BYTE

0 = WORD

ADDRESS (RANGE = 160000s - 177777s)
ALL SWITCHES

OFF = "17

wa___

W7—

ON = 0"

J1q

PACK

LAV11

SWITCH

* gwWITCH NO 8 NOT USED

LAV11 (Cont.)
JUMPER CONFIGURATION

Centronics?

Jumper

LA 180"

[

R = Remove

| = Insert

1 Models 101, 101A, 101D, 102A, 303.
2 CAUTION

— The LA180

will not function unless jumper W6 on the LA180 logic board
is installed: the interface cable must be installed with P1 to
the interface and P2 to the printer.

CONTROL AND STATUS REGISTER

1775 W % J
=

177514

ERROR

DONET

INTERRUPT

11\

BUSY

ONLINE

ENABLE

DATA BUFFER REGISTER

177516 W

LADB

PARITY

XMITTED DATA l

LSI-11 INSTRUCTION SET

WORD FORMAT

BINARY oCTaL
EPRESENTATION

[

Name

Mode
0

regisier deferred

auto-increment
auto-incr deferred
auto-decrement
auto-decr deferred

2
3
4
5
6
7

index
index deferred

immediate
absolute
relative
relative deferred

Description

(R) is operand [ex. R2="/»2]

R
wm (R)+
—(R)
@ —(R)

(R) is adrs; (R) “+(1 or 2)
(R) is adrs of adrs; (R) + 2
(R) — (1 or 2)is adrs
(R) — 2; (R) is adrs of adrs

(R) is addres

(R)

X(R)
@X{R)

(R) + X is adrs
(R)+ X is adrs of adrs

PROGRAM COUNTER ADDRESSING

2
3
6
7

MODE

Symbolic

#n
@ A
A
@A

Reg =7

operand n tollows instr
address A follows instr
instr adrs + 4 + X is adrs
instr adrs 4 4 4+ X is adrs of adrs

LEGEND

Operations

Op Codes
B

= 01forword/lfor byte

(

) = contents of

SS
DD

= destination field

== contents of source
= contents of destination

= gen register (3 bits),

= contents of register

= becomes

°%

= relative address
= register definition

= source field (6 bits)
(6 bits)

Oto7

XXX = offset (8 bits),

N
NN

+127 to —128

= number (3 bits)
= number (6 bits)

Condition Codes
* = conditionally set/cleared

Boolean
N
=AND
V

= inclusive OR

= exclusive OR

—

= not affected

= cleared

= set

LSI-11 INSTRUCTION SET (Cont.)

OPR dst

SINGLE OPERAND:

Mne-

‘op CODE

‘

ss o;z DD

dstResut

N Z V C

0
— d
d+1
d—1
—d

01t 00
A ¢
oo

Op Code

Instruction

CLR(B)
COM(B)
INC(B)
DEC(B)
NEG(B)

B 050DD
m 051DD
m 052DD
m 0530D
m 054DD

clear
complement (1's)
increment
decrement
negate (2's

TST(B)

= 057DD

test

m 060DD
m 061DD
m 062DD
m 063D0D
0003DD

rotate right
rotate left
arith shift right
arith shift left
swap bytes

-Cc,d
C,de

* "
* * *
o
A
** 00

add carry
subtract carry
sign extend

d+¢Cc
d—¢c
gor—1

*
*
-

*
=
*

* *
> °
0 -

monic
General

compl)

Rotate & Shift

ROR(B)
ROL(B)
ASR(B)
ASL(B)
SWAB

d/2
2d

Multipie Precision

m 055DD
® 056DD
0067DD

ADC(B)
SBC(B)
SXT

Processor Status (PS) Operators

MFPS

1067DD

move byte from

de<PS

0 -

MTPS

1064SS

move bytetoPS

PS<«s

DOUBLE OPERAND:

0 cope

]

[*L
Mne-

monic

0P CODE

OPR src, dst

ss
!
9

Op Code Instruction

OPR src, R or OPR R, dst
6

DlD

]

SS OR DD

Operation

N Z V C

des
s—d
des-+d
ded—s

¢
R
oo
e
o

s Ad
de(—s)Aad
desvd
dervd

0
" " 0
* v 0
* T 0

General

MOV(B) m 1SSDD
CMP(B) = 2SSDD
06SSDD
ADD
168SDD
sSuB

move
compare
add
subtract

Logical

BIT(B)
BIC(B)
BiS(B)
XOR

m 3SSDD
wm 4SSDD
m 55SDD
074RDD

bit test (AND)
bit clear
bit set (OR)
exclusive OR

LSI-11 INSTRUCTION SET (Cont.)

Optional EIS

072RSS

ASHC

073RSS

*
.

rerxs
reris

multiply
divide

070RSS
071RSS

MUL
Div

ASH

shift
arithmetically
arith shift
combined

0
e

Optional FIS

FADD
FSuUB
FMUL
FDIV
BRANCH:

** 00
00
*
00
00

floating add
floating subtract
floating multiply
floating divide

07500R
07501R
07502R
07503R

B - - location

If condition is satisfied:
Branch to location,

New PC « Updated PC 4 (2 x offset)
T

adrs of br instr 4 2

[

BASE CODE
1

]
1

Op Code = Base Code + XXX

Mne-

monic

Base Code

Branch Condition

Instruction

Branches

BR
BNE
BEQ
BPL
BMI
BvC
BVS
BCC
BCS

000400 branch (unconditional)
001000 br if not equal (to 0)
(01400 br if equal (to 0)
100000 branch if plus
100400 branch if minus
102000 br if overflow is clear
102400 br if overflow is set
103000 br if carry is clear
103400 br if carry is set

(always)
*0
— 0
-+
—

Z=-0
Z=1
N=20
N =1
v=20
V=1
C=0
C=1

Signed Conditional Branches

BGE

002000

br if greater or

BLT

002400

br if less than (0)

BGT
BLE

equal (to 0)

003000 br if greater than (0)
003400 br if less or

NV =0

NV =1

>0
<0

Zv(N+V)=0
Zv(INwV) =1

>
<

CvZ—=0
CvZ=1

equal (to 0)

Unsigned Conditional Branches
BHI
BLOS

101000 branch if higher
101400 branch if lower
or same

BHIS

103000

branch if higher

BLO

103400

branch if lower

or same

C=0

C =1

LSI-11 INSTRUCTION SET (Cont.)

JUMP & SUBROUTINE
Mne-

monic

Op Code

Instruction

JMP
JSR

0001DD
004RDD

jump

RTS

00020R

MARK

0064NN

077RNN

sS08B

MNotes

PC « dst

jump to subroutine
return from
subroutine
mark
subtract 1 & br

} use same R

(if # 0)

aid in subr return

(R) — 1, then it (R) # 0:

PC « Updated PC —
(2 x NN)

TRAP & INTERRUPT:
Mne-

monic
EMT
TRAP

Op Code

104400
to 104777

BPT

Notes

Instruction

104000
to 104377

000003

emulator trap
(not for general use)

PC at 30, PS at 32

trap

PC at 34, PS at 36

breakpoint trap

PC at 14, PS at 16

PC at 20, PS at 22

10T

000004

input/output trap

RTI

000002

return from interru pt

000006

return from interru pt

RTT

inhibit T bit trap

MISCELLANEOUS:
Mnemonic

Op Code

Instruction

000000
000001
000005
000240

halt
wait for interrupt
reset external bus
{no operation)

CONDITION CODE OPERATORS:

T T
4

OP CODE BASE = 000240
i

[}

0 = CLEAR SELECTED COND. CODE BITS
1 = SET SELECTED COND. CODE BITS
Mnemonic
CLC

Instruction

Op Code
000241

clear C

N
-

ZVEC
-

-0

0
-

-1
1 =
- -

cCC

clear V
clear Z
clear N
clear all ¢c bits

0
0

SEC
SEV
SEZ

000261
000262
000264

set C
set V
setZ

SCC

000277

set ali cc bits

111

SEN

000270

set N

0
-

CLV
CcLZ
CLN

000242
000244
000250
000257

00O

LSI-11 INSTRUCTION SET (Cont.)

NUMERICAL OP CODE LIST

OP Code

Mneiranic

OP Code

00 00 00
00 00 01
00 00 02
00 00 03

HALT
WAIT
RTI
BPT

00 60 DD
00 61 DD
00 62 DD
00 63 DD

10T
RESET

00 00 04
00 00 05

RTT

00 00 0€

00 00 07

00 00 77

(unused)

}

JMP

00 01 DD

RTS

00 02 OR

00 02 10

[

00 02 27

ROR
ROL
ASR
ASL

MARK
SXT

00 64 NN
00 67 DD

00 77 77

MOV

01 SS DD

CMP

02 SS DO

NOP

00 03 DD

SWAB

00 04 XXX

00 10 XXX

BNE

00 20 XXX

BGE

00 24 XXX

BLT

00 34 XXX

00 4R DD
00 50 DD
00 51 DD
00 52 DD
00 53 DD
00 54 DD
00 55 DD
00 56 DD
00 57 DD

00 14 XXX

BIS

ADD

06 SS DD

cond
codes

00 02 77

BIT

03 SS DD

05 SS DD

00 02 &1
i
|

BEQ

MUL

07 OR SS

DIV
ASH
ASHC

07 1R SS
07 2R SS
07 3R SS

07 4R DD

XOR

07 50 OR

FADD
FSUB

07 50 1R

FMUL

07 50 2R

FDIV

07 50 3R

07 50 40

BLE

07 67 77

(unused)

JSR

07 7R NN

SOB

CLR
COM
INC
DEC
NEG
ADC
SBC
TST

10 00 XXX
10 04 XXX
10 10 XXX
10 14 XXX
10 20 XXX
10 24 XXX
10 30 XXX

BPL
BMI
BHt
BLOS
BVC
BVS
BCC
BHIS

10 34 XXX

BCS
BL

00 30 XXX BGT

10 40 00

10 43 77

}EMT

10 44 00

I LTRAP
}(unused) 10 47 77

00 70 00

}“eserved) 04 SS DD BIC

00 02 40

Mnemonic

Mnemonic OP Code

10 50 OD
10 51 DD
10 52 DD
10 53 DD
10 54 DD
10 55 DD
10 56 DD
10 57 DD

CLRB
COMB
INCB
DECB
NEGB
ADCB
SBCB
TSTB

10 60
10 61
10 62
10 63
10 64
10 67

DD
DD
DD
DD
SS
DD

RORB
ROLB
ASRSB
ASLB
MTPS
MFPS

8S
SS
SS
SS
SS
SS

DD
DD
DD

MOVB
CMPB
BITB
BICB
BISB
SUB

11
12
13
14
15
16

DD
DD
DD

17 00 00

RESERVED

17 77 77

RESERVED TRAP AND INTERRUPT VECTORS
000
004

EMT Instruction
TRAP Instruction
Console input Device
Console Output Device
External Event Line
Interrupt
LAV11
FIS (Optional)
RXV11
Floating Vectors start
here

(Reserved)

Bus Timeout and lilegal
Instructions (eg. JMP RO0)
(Odd Address and Stack

Overflow Traps Not Im010

plemented on LSI-11)
Itlegal and Reserved

014

BPT Instruction and T Bit

024

Instruction

IOT Instruction
Power Fail

7-BIT ASCII CODE

Octal

Code

Char

Code

Char

000
001
002
003
004
005
006
007
010
011
012
013
014
015
016

NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO

040
041
042
043
044
054
046
047
050
051
052
053
054
055
056

SP
!
"
#
$
%o
&

020
021

DLE
DCA

060
061

0
1

DC3
DC4
NAK

063
064
065

3
4
5

027
030
031
032
033

ETB
CAN
EM
SuB
ESC

067
070
071
072
073

075

127
130
131
132
133

035
036
037

074

7
8
9
:
;

RS
us

076
077

>
?

135
136
137

017

022

023
024
025

026

034

DC?2

057

062

SYN

066

(
)
*
+
!
.

Char

Code

Char

100
101
102
103
104
105
106
107
110
111
112
113
114
115
116

(
A
B
C
D
E
F
G
H
|
J
K
L
M
N

140
141
142
143
144
145
146
147
150
151
152
153
154
155
156

AN
a
b
c
d
e
f
g
h
i
i
k
|
m
n

120
121

P
Q

160
161

o]
q

123,
124
125

S
T
U

163
164
165

s
t
u

w
X
Y
Z
[

167
170
171
172
173

w
X
Yy
z
{

Jor ¢
A\
— Of «

175
176
177

}
~
DEL

117

122

Octal

Code

126

134

157

[o]

162

166

174

[

ik
————— ZERO

NEGATIVE

TRACE TRAP
PRIORITY

LSI-11 BUS PINNING

Row A

(Same as Row C)

Row B

(Same as Row D)

Module Side 1 (Component Side)

AA1
AB1
AC1
AD1
AE1
AF1
AH1
AJ1

AK1
AL

BSPARE1
BSPARE2
BAD16
BAD17
SSPARE1
SSPARE2
SSPARE3

BA1
BB1
BCt
BD1
BE1
BF1
BHA1

BDCOK H
BPOK H
SSPARE4
SSPARES
SSPARES
SSPARE7
SSPARES

MSPARE A
MSPARE A

BK1
BL1

MSPARE B
MSPARE B

AM1

GND

BHALT L

AN1
AR1
AS1
AT1

AU1

AV1i

BJ1

BM1

BN1

BDMR L

BP1

BREF L
PSPARE3

BR1
BS1

PSPARE1

BU1

BT1

BV1

BSACK L

BSPARES6
BEVNT L
PSARE4

PSPARE2

Module Side 2 (Solder Side)

AA2
AB2
AC2

+5
—12
GND

BA2
BB2
BC?2

+5
—12
GND

AE?2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

BDOUT L
BRPLY L
BDIN L

BE2
BF2
BH2

BDAL2 L
BDAL3 L
BDAL4 L

AD2

BD2

BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU?2
BV2

BSYNC L
BWTBT L
BIRQ L
BIAKI L
BIAKO L
BBS7 L
BDMG! L
BDMGO L
BINIT L
BDALO L
BDAL1 L

BDALS L
BDAL6 L
BDAL7 L
BDALS L
BDAL9 L
BDALIO L
BDAL11 L
BDAL12 L
BDALI3 L
BDAL14 L
BDAL1IS L

NOTES:

Prepared by Educational Services
EQUIPMENT

CORPORATION

MAYNARD, MASSACHUSETTS

EK-LSI11-MC-001

NOVEMBER 1977